diff --git a/MCUME_pico2/.DS_Store b/MCUME_pico2/.DS_Store
new file mode 100644
index 0000000..623c501
Binary files /dev/null and b/MCUME_pico2/.DS_Store differ
diff --git a/MCUME_pico2/CMakeLists.txt b/MCUME_pico2/CMakeLists.txt
new file mode 100644
index 0000000..28e15ed
--- /dev/null
+++ b/MCUME_pico2/CMakeLists.txt
@@ -0,0 +1,486 @@
+cmake_minimum_required(VERSION 3.12)
+
+# Pull in PICO SDK (must be before project)
+include(pico_sdk_import.cmake)
+
+# We also need PICO EXTRAS
+#include(pico_extras_import.cmake)
+
+#set(TARGET testkeymax)
+#set(TARGET pico20)
+#set(TARGET pico64)
+#set(TARGET pico81)
+#set(TARGET pico800)
+#set(TARGET picospeccy)
+#set(TARGET pico5200)
+#set(TARGET picocolem)
+#set(TARGET picoo2em)
+#set(TARGET picovcs)
+#set(TARGET pico8086)
+#set(TARGET picomsx)
+#set(TARGET picogb)
+#set(TARGET picopce)
+#set(TARGET picosms)
+
+set(TARGET picogen)
+
+project(${TARGET} C CXX)
+
+set(CMAKE_C_STANDARD 11)
+set(CMAKE_CXX_STANDARD 17)
+
+# Initialize the Pico SDK
+pico_sdk_init()
+
+include_directories(${TARGET})
+include_directories(config)
+include_directories(display)
+include_directories(fatfs)
+include_directories(fatfs/source)
+include_directories(sd_driver)
+include_directories(psram)
+include_directories(flash)
+include_directories(usb_kbd)
+include_directories(.)
+
+if( ${TARGET} MATCHES "pico20" )
+set(PICO20_SOURCES 
+		pico20/IC.cpp
+		pico20/mos6502.cpp
+		pico20/MOS6522.cpp
+		pico20/MOS6561.cpp
+		pico20/v20.cpp
+		pico20/pico20.cpp
+	)
+#add_compile_definitions(OVERRULE_WIDTH=320 OVERRULE_HEIGHT=192)	
+endif()
+
+if( ${TARGET} MATCHES "pico64" )
+set(PICO64_SOURCES 
+		pico64/c64.cpp 
+		pico64/cia1.cpp
+		pico64/cia2.cpp
+		pico64/cpu.cpp
+		pico64/patches.cpp
+		pico64/pla.cpp
+		pico64/roms.cpp
+		pico64/sid.cpp
+		pico64/timerutil.cpp
+		pico64/vic.cpp
+		pico64/reSID.cpp
+		pico64/pico64.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "pico81" )
+set(PICO81_SOURCES 
+		pico81/Z80.c 
+		pico81/AY8910.c
+		pico81/zx81.c
+		pico81/pico81.cpp
+	)
+# ZX81,ZX Spectrum,Colem,Vic20
+add_compile_definitions(OVERRULE_WIDTH=320 OVERRULE_HEIGHT=192)	
+endif()
+
+if( ${TARGET} MATCHES "picospeccy" )
+set(PICOSPECCY_SOURCES 
+		picospeccy/Z80.c 
+		picospeccy/AY8910.c
+		picospeccy/spec.c
+		picospeccy/zx_filetyp_z80.c
+		picospeccy/picospeccy.cpp
+	)
+add_compile_definitions(OVERRULE_WIDTH=320 OVERRULE_HEIGHT=192)	
+endif()
+
+if( ${TARGET} MATCHES "pico800" )
+set(PICO800_SOURCES 
+		pico800/antic.c 
+		pico800/atari800.c
+		pico800/cpu.c
+		pico800/crc32.c
+		pico800/gtia.c
+		pico800/pia.c
+		pico800/pokey.c
+		pico800/pokeysnd.c
+		pico800/sio.c
+		pico800/pico800.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "pico5200" )
+set(PICO5200_SOURCES 
+		pico5200/antic.c 
+		pico5200/atari5200.c
+		pico5200/cpu.c
+		pico5200/crc32.c
+		pico5200/gtia.c
+		pico5200/pokey.c
+		pico5200/pokeysnd.c
+		pico5200/pico5200.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picocolem" )
+set(PICOCOLEM_SOURCES 
+		picocolem/Z80.c 
+		picocolem/SN76489.c
+		picocolem/Colem.c
+		picocolem/picocolem.cpp
+	)
+add_compile_definitions(OVERRULE_WIDTH=320 OVERRULE_HEIGHT=192)	
+endif()
+
+if( ${TARGET} MATCHES "picoo2em" )
+set(PICOO2EM_SOURCES 
+		picoo2em/audio.c 
+		picoo2em/cpu.c
+		picoo2em/crc32.c
+		picoo2em/cset.c
+		picoo2em/Oddemu.c
+		picoo2em/table.c
+		picoo2em/vdc.c
+		picoo2em/vmachine.c
+		picoo2em/vpp_cset.c
+		picoo2em/vpp.c
+		picoo2em/picoo2em.cpp
+	)
+add_compile_definitions(OVERRULE_WIDTH=320 OVERRULE_HEIGHT=192)	
+endif()
+
+if( ${TARGET} MATCHES "picovcs" )
+set(PICOVCS_SOURCES 
+		picovcs/At2600.c 
+		picovcs/Collision.c
+		picovcs/Cpu.c
+		picovcs/Display.c
+		picovcs/Exmacro.c
+		picovcs/Keyboard.c
+		picovcs/Memory.c
+		picovcs/Options.c
+		picovcs/Raster.c
+		picovcs/Table.c
+		picovcs/Tiasound.c
+		picovcs/Vcsemu.c
+		picovcs/Vmachine.c
+		picovcs/picovcs.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "piconofrendo" )
+set(PICONOFRENDO_SOURCES 
+		piconofrendo/bitmap.c 
+		piconofrendo/config.c
+		piconofrendo/event.c
+		piconofrendo/log.c
+		piconofrendo/map000.c
+		piconofrendo/map001.c
+		piconofrendo/map002.c
+		piconofrendo/map003.c
+		piconofrendo/map004.c
+		piconofrendo/map005.c
+		piconofrendo/map007.c
+		piconofrendo/map008.c
+		piconofrendo/map009.c
+		piconofrendo/map011.c
+		piconofrendo/map015.c
+		piconofrendo/map016.c
+		piconofrendo/map018.c
+		piconofrendo/map019.c
+		piconofrendo/map024.c
+		piconofrendo/map032.c
+		piconofrendo/map033.c
+		piconofrendo/map034.c
+		piconofrendo/map040.c
+		piconofrendo/map041.c
+		piconofrendo/map042.c
+		piconofrendo/map046.c
+		piconofrendo/map050.c
+		piconofrendo/map064.c
+		piconofrendo/map065.c
+		piconofrendo/map066.c
+		piconofrendo/map070.c
+		piconofrendo/map073.c
+		piconofrendo/map075.c
+		piconofrendo/map078.c
+		piconofrendo/map079.c
+		piconofrendo/map085.c
+		piconofrendo/map087.c
+		piconofrendo/map093.c
+		piconofrendo/map094.c
+		piconofrendo/map099.c
+		piconofrendo/map160.c
+		piconofrendo/map229.c
+		piconofrendo/map231.c
+		piconofrendo/mapvrc.c
+		piconofrendo/mmc5_snd.c
+		piconofrendo/mmclist.c
+		piconofrendo/nes_apu.c
+		piconofrendo/nes_emu.c
+		piconofrendo/nes_mmc.c
+		piconofrendo/nes_pal.c
+		piconofrendo/nes_ppu.c
+		piconofrendo/nes_rom_light.c
+		piconofrendo/nes.c
+		piconofrendo/nes6502.c
+		piconofrendo/nesinput.c
+		piconofrendo/nofrendo.c
+		piconofrendo/vid_drv.c
+		piconofrendo/vrcvisnd.c
+		piconofrendo/piconofrendo.cpp
+	)
+endif()
+
+
+if( ${TARGET} MATCHES "picosms" )
+set(PICOSMS_SOURCES 
+		picosms/emu.cpp 
+		picosms/fmopl.c
+		picosms/memory.c
+		picosms/render.c
+		picosms/sms.c
+		picosms/sn76496.c
+		picosms/system.c
+		picosms/vdp.c
+		picosms/ym2413.c
+		picosms/z80.c
+		picosms/picosms.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "pico8086" )
+set(PICO8086_SOURCES 
+		pico8086/emu.cpp
+		pico8086/cpu.cpp 
+		pico8086/disk.cpp
+		pico8086/network.cpp
+		pico8086/ports.cpp
+		pico8086/i8253.cpp
+		pico8086/i8259.cpp
+		pico8086/pico8086.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picopceold" )
+set(PICOPCE_SOURCES 
+		picopce/emu.cpp 
+		picopce/h6280.c
+		picopce/memory.c
+		picopce/pce.c
+		picopce/psg.c
+		picopce/render.c
+		picopce/system.c
+		picopce/vce.c
+		picopce/vdc.c
+		picopce/picopce.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picopce" )
+set(PICOPCE_SOURCES 
+		picopce/emu.cpp 
+		picopce/pce-go/gfx.c
+		picopce/pce-go/h6280.c
+		picopce/pce-go/pce.c
+		picopce/pce-go/psg.c
+		picopce/pce-go/pce-go.c
+		picopce/picopce.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picomsx" )
+set(PICOMSX_SOURCES 
+		picomsx/fmsx.c 
+		picomsx/AY8910.c
+		picomsx/Boot.c
+		picomsx/Disk.c
+		picomsx/I8251.c
+		picomsx/I8255.c
+		picomsx/Patch.c
+		picomsx/SCC.c
+		picomsx/Sound.c
+		picomsx/V9938.c
+		picomsx/YM2413.c
+		picomsx/Z80.c
+		picomsx/picomsx.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picogenold" )
+set(PICOGEN_SOURCES 
+		picogen/emu.cpp 
+		picogen/fm.c
+		picogen/genesis.c
+		picogen/io.c
+		picogen/m68kcpu.c
+		picogen/m68kopac.c
+		picogen/m68kopdm.c
+		picogen/m68kopnz.c
+		picogen/m68kops_pre.c
+		picogen/m68kops.c
+		picogen/mem68k.c
+		picogen/membnk.c
+		picogen/memory.c
+		picogen/memvdp.c
+		picogen/memz80.c
+		picogen/render.c
+		picogen/sn76496.c
+		picogen/sound.c
+		picogen/system.c
+		picogen/vdp.c
+		picogen/z80.c
+		picogen/picogen.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "picogen" )
+
+set(PICOGEN_SOURCES 
+		picogen/emu.cpp 
+		picogen/gwenesis/bus/gwenesis_bus.c
+		picogen/gwenesis/cpus/M68K/m68kcpu.c
+		picogen/gwenesis/cpus/Z80/Z80.c
+		picogen/gwenesis/cpus/Z80/Debug.c
+		picogen/gwenesis/cpus/Z80/ConDebug.c
+		picogen/gwenesis/io/gwenesis_io.c
+		picogen/gwenesis/sound/gwenesis_sn76489.c
+		picogen/gwenesis/sound/ym2612.c
+		picogen/gwenesis/sound/z80inst.c
+		picogen/gwenesis/vdp/gwenesis_vdp_gfx.c
+		picogen/gwenesis/vdp/gwenesis_vdp_mem.c
+		picogen/picogen.cpp		
+	)
+
+file(GLOB SPECIAL_SRC_FILES
+		"picogen/gwenesis/bus/gwenesis_bus.c"
+		"picogen/gwenesis/cpus/M68K/m68kcpu.c"
+		"picogen/gwenesis/cpus/Z80/Z80.c"
+		"picogen/gwenesis/cpus/Z80/Debug.c"
+		"picogen/gwenesis/cpus/Z80/ConDebug.c"
+		"picogen/gwenesis/io/gwenesis_io.c"
+		"picogen/gwenesis/sound/gwenesis_sn76489.c"
+		"picogen/gwenesis/sound/ym2612.c"
+		"picogen/gwenesis/sound/z80inst.c"
+		"picogen/gwenesis/vdp/gwenesis_vdp_gfx.c"
+		"picogen/gwenesis/vdp/gwenesis_vdp_mem.c" )
+set_source_files_properties(SOURCE ${SPECIAL_SRC_FILES} PROPERTIES COMPILE_FLAGS "-funroll-loops  -ffast-math -feliminate-unused-debug-types -ffunction-sections -fdata-sections -O2")
+
+endif()
+
+if( ${TARGET} MATCHES "picogb" )
+set(PICOGB_SOURCES 
+		picogb/emu.cpp 
+		picogb/minigb_apu/minigb_apu.c
+		picogb/picogb.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "testio" )
+set(TESTIO_SOURCES 
+		testio/testio.cpp
+		testio/emuapi.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "testvga" )
+set(TESTVGA_SOURCES 
+		testvga/testvga.cpp
+	)
+endif()
+
+if( ${TARGET} MATCHES "testkeymax" )
+set(TESTKEYMAX_SOURCES 
+		testkeymax/testkeymax.cpp
+	)
+endif()
+
+set(DISPLAY_SOURCES 
+		display/pico_dsp.cpp		
+		display/hdmi_framebuffer.cpp		
+		display/emuapi.cpp
+		display/AudioPlaySystem.cpp		
+	)
+
+set(USB_SOURCES 
+		usb_kbd/hid_app.c
+	)
+
+set(FATSD_SOURCES 
+		sd_driver/tf_card.c
+		fatfs/source/ff.c
+		fatfs/source/ffunicode.c		
+		fatfs/source/ffsystem.c		
+	)
+
+
+set(PSRAM_SOURCES 
+		psram/psram_spi.c
+		psram/psram_t.cpp
+	)
+
+set(FLASH_SOURCES 
+		flash/flash_t.c
+	)
+
+add_executable(${TARGET}
+		${PICO20_SOURCES}
+		${PICO64_SOURCES}
+		${PICO81_SOURCES}
+		${PICO800_SOURCES}
+		${PICO5200_SOURCES}
+		${PICO8086_SOURCES}
+		${PICOCOLEM_SOURCES}
+		${PICOO2EM_SOURCES}
+		${PICOVCS_SOURCES}
+		${PICOSPECCY_SOURCES}
+		${PICONOFRENDO_SOURCES}
+		${PICOSMS_SOURCES}
+		${PICOGEN_SOURCES}
+		${PICOPCE_SOURCES}
+		${PICOGB_SOURCES}
+		${PICOMSX_SOURCES}
+		${TESTIO_SOURCES}
+		${TESTVGA_SOURCES}
+		${TESTKEYMAX_SOURCES}
+#		${PSRAM_SOURCES}
+		${FLASH_SOURCES}
+		${DISPLAY_SOURCES}
+		${FATSD_SOURCES}
+		${USB_SOURCES}
+	)
+
+pico_generate_pio_header(${TARGET} ${CMAKE_CURRENT_LIST_DIR}/psram/psram_spi.pio)
+
+target_link_libraries(${TARGET} pico_multicore
+	    pico_stdlib
+	    hardware_dma
+	    hardware_spi
+	    hardware_adc
+	    hardware_pio
+        hardware_pwm	    
+        tinyusb_host 
+        tinyusb_board
+		tinyusb_pico_pio_usb
+	)
+
+target_compile_definitions(${TARGET} PRIVATE
+        PIO_USB_DP_PIN_DEFAULT=2
+    )
+
+target_compile_definitions(${TARGET} PRIVATE PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK=1)
+
+
+#target_compile_definitions(${TARGET} PRIVATE CFG_TUSB_DEBUG=2)
+#target_compile_options(${TARGET} PUBLIC -O3)
+#target_compile_options(${TARGET} PUBLIC -Wall -Wextra -Wno-unused-function -Wno-unused-parameter)
+IF (NOT DEFINED N_SD_CARDS)
+    SET(N_SD_CARDS 1)
+ENDIF()
+target_compile_definitions(${TARGET} PUBLIC N_SD_CARDS=${N_SD_CARDS})
+
+
+pico_enable_stdio_uart(${TARGET} TRUE)
+#pico_enable_stdio_usb(${TARGET} TRUE)
+
+pico_add_extra_outputs(${TARGET})
diff --git a/MCUME_pico2/bin/.DS_Store b/MCUME_pico2/bin/.DS_Store
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diff --git a/MCUME_pico2/bin/pico64.uf2 b/MCUME_pico2/bin/pico64.uf2
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diff --git a/MCUME_pico2/bin/picocolem.uf2 b/MCUME_pico2/bin/picocolem.uf2
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diff --git a/MCUME_pico2/bin/picogb.uf2 b/MCUME_pico2/bin/picogb.uf2
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diff --git a/MCUME_pico2/bin/picomsx.uf2 b/MCUME_pico2/bin/picomsx.uf2
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diff --git a/MCUME_pico2/bin/picoo2em.uf2 b/MCUME_pico2/bin/picoo2em.uf2
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diff --git a/MCUME_pico2/bin/picopce.uf2 b/MCUME_pico2/bin/picopce.uf2
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diff --git a/MCUME_pico2/bin/picosms.uf2 b/MCUME_pico2/bin/picosms.uf2
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diff --git a/MCUME_pico2/bin/picospeccy.uf2 b/MCUME_pico2/bin/picospeccy.uf2
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diff --git a/MCUME_pico2/bin/testkeymax.uf2 b/MCUME_pico2/bin/testkeymax.uf2
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diff --git a/MCUME_pico2/build/.DS_Store b/MCUME_pico2/build/.DS_Store
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diff --git a/MCUME_pico2/config/.DS_Store b/MCUME_pico2/config/.DS_Store
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diff --git a/MCUME_pico2/config/iopins.h b/MCUME_pico2/config/iopins.h
new file mode 100644
index 0000000..b5cba2e
--- /dev/null
+++ b/MCUME_pico2/config/iopins.h
@@ -0,0 +1,51 @@
+#ifndef IOPINS_H
+#define IOPINS_H
+
+#include "platform_config.h"
+
+#define VGA_DMA_CHANNEL 2 // requires 2 channels
+#define AUD_DMA_CHANNEL 4 // requires 1 or 3 channels
+#define PSR_DMA_CHANNEL 7 // requires 2 channels (PSRAM)
+
+// Speaker
+#define AUDIO_PIN       21
+
+// TFT
+#define TFT_SPIREG      spi1
+#define TFT_SPIDREQ     DREQ_SPI1_TX
+#define TFT_SCLK        14
+#define TFT_MOSI        15
+#define TFT_MISO        12
+#define TFT_DC          28
+#define TFT_CS          13  // 255 for LORES ST7789 (NO CS)
+#define TFT_RST         255 // 255 for ILI/ST if connected to 3.3V
+#define TFT_BACKLIGHT   255 // hardwired to 3.3v
+
+// 2 buttons
+#define PIN_KEY_USER1   28
+#define PIN_KEY_USER2   27 
+
+// SD
+#define SD_SCLK         6
+#define SD_MOSI         7
+#define SD_MISO         4 
+#define SD_CS           5
+#define SD_DETECT       255
+// Second SPI bus and DMA not conflicting with USB
+#define SD_SPIREG       spi0
+
+
+#define PSRAM_PIN_SCK       10
+#define PSRAM_PIN_MOSI      11
+#define PSRAM_PIN_MISO      8 
+#define PSRAM_PIN_CS        9
+
+#define PSRAM_ASYNC         1
+
+#define PSRAM_SCLK          10
+#define PSRAM_MOSI          11
+#define PSRAM_MISO          8 
+#define PSRAM_CS            9
+
+#define PSRAM_SPIREG    	spi1
+#endif
diff --git a/MCUME_pico2/config/platform_config.h b/MCUME_pico2/config/platform_config.h
new file mode 100644
index 0000000..01d549a
--- /dev/null
+++ b/MCUME_pico2/config/platform_config.h
@@ -0,0 +1,37 @@
+#ifndef _PLATFORM_CONFIG_H_
+#define _PLATFORM_CONFIG_H_
+
+#define PICOHYPERPET   1
+#define KEYLAYOUT      KLAYOUT_UK
+
+#define INVX           1
+#define HAS_SND        1
+#define USE_VGA        1
+#define HAS_USBHOST    1
+//#define ILI9341        1
+//#define ST7789         1
+//#define SWAP_JOYSTICK  1
+//#define LOHRES         1
+//#define ROTATE_SCREEN  1
+//#define FLIP_SCREEN  1
+//#define HAS_PSRAM      1
+
+#ifdef HAS_SND
+
+#define SOUNDRATE 22050                           // sound rate [Hz]
+
+//#define AUDIO_8BIT     1
+#define AUDIO_1DMA      1
+
+
+#ifdef AUDIO_8BIT
+typedef uint8_t  audio_sample;
+#else
+typedef short  audio_sample;
+#endif
+
+#endif
+
+#include "program_config.h"
+
+#endif
diff --git a/MCUME_pico2/display/.DS_Store b/MCUME_pico2/display/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/display/.DS_Store differ
diff --git a/MCUME_pico2/display/AudioPlaySystem.cpp b/MCUME_pico2/display/AudioPlaySystem.cpp
new file mode 100644
index 0000000..8e35230
--- /dev/null
+++ b/MCUME_pico2/display/AudioPlaySystem.cpp
@@ -0,0 +1,181 @@
+#include "emuapi.h"
+
+#ifdef HAS_SND
+
+#include "AudioPlaySystem.h"
+
+#define SAMPLERATE AUDIO_SAMPLE_RATE_EXACT
+#define CLOCKFREQ 985248
+
+#ifndef CUSTOM_SND 
+static const short square[]={
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+32767,32767,32767,32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,
+};
+
+const short noise[] {
+-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,
+-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767,
+-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,
+-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767,
+-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767,
+-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767,
+32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767,
+32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767,
+32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,
+32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767,
+};
+
+#define NOISEBSIZE 0x100
+
+typedef struct
+{
+  unsigned int spos;
+  unsigned int sinc;
+  unsigned int vol;
+} Channel;
+
+static Channel chan[6] = {
+  {0,0,0},
+  {0,0,0},
+  {0,0,0},
+  {0,0,0},
+  {0,0,0},
+  {0,0,0} };
+  
+#endif
+
+volatile bool playing = false;
+
+
+static void snd_Reset(void)
+{
+#ifndef CUSTOM_SND 
+  chan[0].vol = 0;
+  chan[1].vol = 0;
+  chan[2].vol = 0;
+  chan[3].vol = 0;
+  chan[4].vol = 0;
+  chan[5].vol = 0;
+  chan[0].sinc = 0;
+  chan[1].sinc = 0;
+  chan[2].sinc = 0;
+  chan[3].sinc = 0;
+  chan[4].sinc = 0;
+  chan[5].sinc = 0;
+#endif
+}
+
+
+#ifdef CUSTOM_SND
+
+#ifdef CUSTOM_SND_C 
+extern "C" {
+#endif  
+void SND_Process(void *sndbuffer, int sndn);
+#ifdef CUSTOM_SND_C 
+}
+#endif  
+#endif
+
+#include <stdio.h>
+void AudioPlaySystem::snd_Mixer(short *  stream, int len )
+{
+  if (playing) 
+  {
+#ifdef CUSTOM_SND
+    //printf("s\n");    
+    SND_Process((void*)stream, len);
+#else
+    int i;
+    long s;     
+    //len = len >> 1;   
+    short v0=chan[0].vol;
+    short v1=chan[1].vol;
+    short v2=chan[2].vol;
+    short v3=chan[3].vol;
+    short v4=chan[4].vol;
+    short v5=chan[5].vol;
+    for (i=0;i<len;i++)
+    {
+      s =((v0*square[(chan[0].spos>>8)&0x3f])>>11);
+      s+=((v1*square[(chan[1].spos>>8)&0x3f])>>11);
+      s+=((v2*square[(chan[2].spos>>8)&0x3f])>>11);
+      s+=((v3*noise[(chan[3].spos>>8)&(NOISEBSIZE-1)])>>11);
+      s+=((v4*noise[(chan[4].spos>>8)&(NOISEBSIZE-1)])>>11);
+      s+=((v5*noise[(chan[5].spos>>8)&(NOISEBSIZE-1)])>>11);         
+      *stream++ = (short)(s>>8 /*+ 32767*/);
+      //*stream++ = (short)(s);
+      chan[0].spos += chan[0].sinc;
+      chan[1].spos += chan[1].sinc;
+      chan[2].spos += chan[2].sinc;
+      chan[3].spos += chan[3].sinc;  
+      chan[4].spos += chan[4].sinc;  
+      chan[5].spos += chan[5].sinc;  
+    }
+#endif         
+  }
+}
+  
+void AudioPlaySystem::begin(void)
+{
+  this->reset();
+}
+
+void AudioPlaySystem::start(void)
+{
+  playing = true;  
+}
+
+void AudioPlaySystem::setSampleParameters(float clockfreq, float samplerate) {
+}
+
+void AudioPlaySystem::reset(void)
+{
+  snd_Reset();
+}
+
+void AudioPlaySystem::stop(void)
+{
+  playing = false;  
+}
+
+bool AudioPlaySystem::isPlaying(void) 
+{ 
+  return playing; 
+}
+
+
+
+void AudioPlaySystem::sound(int C, int F, int V) {
+#ifndef CUSTOM_SND 
+  if (C < 6) {
+    chan[C].vol = V;
+    chan[C].sinc = F>>1; 
+  }
+#endif  
+}
+
+void AudioPlaySystem::step(void) {
+}
+#endif
diff --git a/MCUME_pico2/display/AudioPlaySystem.h b/MCUME_pico2/display/AudioPlaySystem.h
new file mode 100644
index 0000000..5d2efc0
--- /dev/null
+++ b/MCUME_pico2/display/AudioPlaySystem.h
@@ -0,0 +1,26 @@
+#ifndef audioplaysystem_h_
+#define audioplaysystem_h_
+
+#ifdef HAS_SND
+
+#include "platform_config.h"
+
+class AudioPlaySystem
+{
+public:
+  AudioPlaySystem(void) { };
+  void begin(void);
+  void setSampleParameters(float clockfreq, float samplerate);
+  void reset(void);
+  void start(void);
+  void stop(void);
+  bool isPlaying(void);
+  void sound(int C, int F, int V);    
+  void buzz(int size, int val);
+  void step(void);
+  static void snd_Mixer(short *  stream, int len );  
+};
+
+#endif
+
+#endif
diff --git a/MCUME_pico2/display/emuapi.cpp b/MCUME_pico2/display/emuapi.cpp
new file mode 100644
index 0000000..f9a7ba0
--- /dev/null
+++ b/MCUME_pico2/display/emuapi.cpp
@@ -0,0 +1,1562 @@
+#define KEYMAP_PRESENT 1
+
+#define PROGMEM
+
+#include "pico.h"
+#include "pico/stdlib.h"
+#include "hardware/adc.h"
+#include <stdio.h>
+#include <string.h>
+
+extern "C" {
+  #include "emuapi.h"
+  #include "iopins.h"
+}
+
+#ifdef HAS_USBHOST
+#include <ctype.h>
+#include "tusb.h"
+#include "kbd.h"
+#endif
+
+static bool emu_writeConfig(void);
+static bool emu_readConfig(void);
+static bool emu_eraseConfig(void);
+static bool emu_writeGfxConfig(void);
+static bool emu_readGfxConfig(void);
+static bool emu_eraseGfxConfig(void);
+
+#include "pico_dsp.h"
+extern PICO_DSP tft;
+
+#define MAX_FILENAME_PATH   64
+#define NB_FILE_HANDLER     4
+#define AUTORUN_FILENAME    "autorun.txt"
+#define GFX_CFG_FILENAME    "gfxmode.txt"
+#define KBD_CFG_FILENAME    "kbdmode.txt"
+
+#define MAX_FILES           64
+#define MAX_FILENAME_SIZE   32
+#define MAX_MENULINES       9
+#define TEXT_HEIGHT         16
+#define TEXT_WIDTH          8
+#define MENU_FILE_XOFFSET   (6*TEXT_WIDTH)
+#define MENU_FILE_YOFFSET   (2*TEXT_HEIGHT)
+#define MENU_FILE_W         (MAX_FILENAME_SIZE*TEXT_WIDTH)
+#define MENU_FILE_H         (MAX_MENULINES*TEXT_HEIGHT)
+#define MENU_FILE_BGCOLOR   RGBVAL16(0x00,0x00,0x40)
+#define MENU_JOYS_YOFFSET   (12*TEXT_HEIGHT)
+#define MENU_VBAR_XOFFSET   (0*TEXT_WIDTH)
+#define MENU_VBAR_YOFFSET   (MENU_FILE_YOFFSET)
+
+#define MENU_TFT_XOFFSET    (MENU_FILE_XOFFSET+MENU_FILE_W+8)
+#define MENU_TFT_YOFFSET    (MENU_VBAR_YOFFSET+32)
+#define MENU_VGA_XOFFSET    (MENU_FILE_XOFFSET+MENU_FILE_W+8)
+#define MENU_VGA_YOFFSET    (MENU_VBAR_YOFFSET+MENU_FILE_H-32-37)
+
+
+
+static int nbFiles=0;
+static int curFile=0;
+static int topFile=0;
+static char selection[MAX_FILENAME_PATH]="";
+static char selected_filename[MAX_FILENAME_SIZE]="";
+static char files[MAX_FILES][MAX_FILENAME_SIZE];
+static bool menuRedraw=true;
+
+#if (defined(PICOMPUTER) || defined(PICOZX) )
+static const unsigned short * keys;
+static unsigned char keymatrix[7];
+static int keymatrix_hitrow=-1;
+static bool key_fn=false;
+static bool key_alt=false;
+static uint32_t keypress_t_ms=0;
+static uint32_t last_t_ms=0;
+static uint32_t hundred_ms_cnt=0;
+static bool ledflash_toggle=false;
+#endif
+static int keyMap;
+
+static bool joySwapped = false;
+static uint16_t bLastState;
+static int xRef;
+static int yRef;
+static uint16_t usbnavpad=0;
+
+static bool menuOn=true;
+static bool autorun=false;
+
+
+/********************************
+ * Generic output and malloc
+********************************/ 
+void emu_printf(const char * text)
+{
+  printf("%s\n",text);
+}
+
+void emu_printf(int val)
+{
+  printf("%d\n",val);
+}
+
+void emu_printi(int val)
+{
+  printf("%d\n",val);
+}
+
+void emu_printh(int val)
+{
+  printf("0x%.8\n",val);
+}
+
+static int malbufpt = 0;
+static char malbuf[EXTRA_HEAP];
+
+void * emu_Malloc(int size)
+{
+  void * retval =  malloc(size);
+  if (!retval) {
+    emu_printf("failled to allocate");
+    emu_printf(size);
+    emu_printf("fallback");
+    if ( (malbufpt+size) < sizeof(malbuf) ) {
+      retval = (void *)&malbuf[malbufpt];
+      malbufpt += size;      
+    }
+    else {
+      emu_printf("failure to allocate");
+    }
+  }
+  else {
+    emu_printf("could allocate dynamic ");
+    emu_printf(size);    
+  }
+  
+  return retval;
+}
+
+void * emu_MallocI(int size)
+{
+  void * retval =  NULL; 
+
+  if ( (malbufpt+size) < sizeof(malbuf) ) {
+    retval = (void *)&malbuf[malbufpt];
+    malbufpt += size;
+    emu_printf("could allocate static ");
+    emu_printf(size);          
+  }
+  else {
+    emu_printf("failure to allocate");
+  }
+
+  return retval;
+}
+void emu_Free(void * pt)
+{
+  free(pt);
+}
+
+void emu_drawText(unsigned short x, unsigned short y, const char * text, unsigned short fgcolor, unsigned short bgcolor, int doublesize)
+{
+  tft.drawText(x, y, text, fgcolor, bgcolor, doublesize?true:false);
+}
+
+
+/********************************
+ * OSKB handling
+********************************/ 
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+// On screen keyboard position
+#define KXOFF      28 //64
+#define KYOFF      96
+#define KWIDTH     11 //22
+#define KHEIGHT    3
+
+static bool oskbOn = false;
+static int cxpos = 0;
+static int cypos = 0;
+static int oskbMap = 0;
+static uint16_t oskbBLastState = 0;
+
+static void lineOSKB2(int kxoff, int kyoff, char * str, int row)
+{
+  char c[2] = {'A',0};
+  const char * cpt = str;
+  for (int i=0; i<KWIDTH; i++)
+  {
+    c[0] = *cpt++;
+    c[1] = 0;
+    uint16_t bg = RGBVAL16(0x00,0x00,0xff);
+    if ( (cxpos == i) && (cypos == row) ) bg = RGBVAL16(0xff,0x00,0x00);
+    tft.drawTextNoDma(kxoff+8*i,kyoff, &c[0], RGBVAL16(0x00,0xff,0xff), bg, ((i&1)?false:true));
+  } 
+}
+
+static void lineOSKB(int kxoff, int kyoff, char * str, int row)
+{
+  char c[4] = {' ',0,' ',0};
+  const char * cpt = str;
+  for (int i=0; i<KWIDTH; i++)
+  {
+    c[1] = *cpt++;
+    uint16_t bg;
+    if (row&1) bg = (i&1)?RGBVAL16(0xff,0xff,0xff):RGBVAL16(0xe0,0xe0,0xe0);
+    else bg = (i&1)?RGBVAL16(0xe0,0xe0,0xe0):RGBVAL16(0xff,0xff,0xff);
+    if ( (cxpos == i) && (cypos == row) ) bg = RGBVAL16(0x00,0xff,0xff);
+    tft.drawTextNoDma(kxoff+24*i,kyoff+32*row+0 , "   ", RGBVAL16(0x00,0x00,0x00), bg, false);
+    tft.drawTextNoDma(kxoff+24*i,kyoff+32*row+8 , &c[0], RGBVAL16(0x00,0x00,0x00), bg, true);
+    tft.drawTextNoDma(kxoff+24*i,kyoff+32*row+24, "   ", RGBVAL16(0x00,0x00,0x00), bg, false);
+  } 
+}
+
+
+static void drawOskb(void)
+{
+//  lineOSKB2(KXOFF,KYOFF+0,  (char *)"Q1W2E3R4T5Y6U7I8O9P0<=",  0);
+//  lineOSKB2(KXOFF,KYOFF+16, (char *)"  A!S@D#F$G%H+J&K*L-EN",  1);
+//  lineOSKB2(KXOFF,KYOFF+32, (char *)"  Z(X)C?V/B\"N<M>.,SP  ", 2);
+/*  
+  if (oskbMap == 0) {
+    lineOSKB(KXOFF,KYOFF, keylables_map1_0,  0);
+    lineOSKB(KXOFF,KYOFF, keylables_map1_1,  1);
+    lineOSKB(KXOFF,KYOFF, keylables_map1_2,  2);
+  }
+  else if (oskbMap == 1) {
+    lineOSKB(KXOFF,KYOFF, keylables_map2_0,  0);
+    lineOSKB(KXOFF,KYOFF, keylables_map2_1,  1);
+    lineOSKB(KXOFF,KYOFF, keylables_map2_2,  2);
+  }
+  else {
+    lineOSKB(KXOFF,KYOFF, keylables_map3_0,  0);
+    lineOSKB(KXOFF,KYOFF, keylables_map3_1,  1);
+    lineOSKB(KXOFF,KYOFF, keylables_map3_2,  2);
+  }
+*/  
+}
+
+void toggleOskb(bool forceoff) {
+  if (forceoff) oskbOn=true; 
+  if (oskbOn) {
+    oskbOn = false;
+    tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00));
+    tft.drawTextNoDma(0,32, "Press USER2 to toggle onscreen keyboard.", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0x00,0x00,0x00), true);
+  } else {
+    oskbOn = true;
+    tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00));
+    tft.drawTextNoDma(0,32, " Press USER2 to exit onscreen keyboard. ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0x00,0x00,0x00), true);
+    tft.drawTextNoDma(0,64, "    (USER1 to toggle between keymaps)   ", RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true);
+    tft.drawRectNoDma(KXOFF,KYOFF, 22*8, 3*16, RGBVAL16(0x00,0x00,0xFF));
+    drawOskb();        
+  }
+}
+
+static int handleOskb(void)
+{  
+  int retval = 0;
+
+  uint16_t bClick = bLastState & ~oskbBLastState;
+  oskbBLastState = bLastState;
+  /*
+  static const char * digits = "0123456789ABCDEF";
+  char buf[5] = {0,0,0,0,0};
+  int val = bClick;
+  buf[0] = digits[(val>>12)&0xf];
+  buf[1] = digits[(val>>8)&0xf];
+  buf[2] = digits[(val>>4)&0xf];
+  buf[3] = digits[val&0xf];
+  tft.drawTextNoDma(0,KYOFF+ 64,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),1);
+  */
+  if (bClick & MASK_KEY_USER2)
+  { 
+    toggleOskb(false);
+  }
+  if (oskbOn)
+  {
+    bool updated = true;
+    if (bClick & MASK_KEY_USER1)
+    { 
+      oskbMap += 1;
+      if (oskbMap == 3) oskbMap = 0;
+    }    
+    else if (bClick & MASK_JOY2_LEFT)
+    {  
+      cxpos++;
+      if (cxpos >= KWIDTH) cxpos = 0;
+    }
+    else if (bClick & MASK_JOY2_RIGHT)
+    {  
+      cxpos--;
+      if (cxpos < 0) cxpos = KWIDTH-1;
+    }
+    else if (bClick & MASK_JOY2_DOWN)
+    {  
+      cypos++;
+      if (cypos >= KHEIGHT) cypos = 0;
+    }
+    else if (bClick & MASK_JOY2_UP)
+    {  
+      cypos--;
+      if (cypos < 0) cypos = KHEIGHT-1;
+    }
+    else if (oskbBLastState & MASK_JOY2_BTN)
+    {  
+      retval = cypos*KWIDTH+cxpos+1;
+      if (retval) {
+        retval--;
+        //if (retval & 1) retval = key_map2[retval>>1];
+        //else retval = key_map1[retval>>1];
+        if (oskbMap == 0) {
+          retval = key_map1[retval];
+        }
+        else if (oskbMap == 1) {
+          retval = key_map2[retval];
+        }
+        else {
+          retval = key_map3[retval];
+        }
+        //if (retval) { toggleOskb(true); updated=false; };
+      }
+    }
+    else {
+      updated=false;
+    }    
+    if (updated) drawOskb();
+  }
+
+  return retval;    
+}
+#endif
+
+/********************************
+ * Input and keyboard
+********************************/ 
+int emu_ReadAnalogJoyX(int min, int max) 
+{
+  adc_select_input(0);
+  int val = adc_read();
+#if INVX
+  val = 4095 - val;
+#endif
+  val = val-xRef;
+  val = ((val*140)/100);
+  if ( (val > -512) && (val < 512) ) val = 0;
+  val = val+2048;
+  return (val*(max-min))/4096;
+}
+
+int emu_ReadAnalogJoyY(int min, int max) 
+{
+  adc_select_input(1);  
+  int val = adc_read();
+#if INVY
+  val = 4095 - val;
+#endif
+  val = val-yRef;
+  val = ((val*120)/100);
+  if ( (val > -512) && (val < 512) ) val = 0;
+  //val = (val*(max-min))/4096;
+  val = val+2048;
+  //return val+(max-min)/2;
+  return (val*(max-min))/4096;
+}
+
+
+static uint16_t readAnalogJoystick(void)
+{
+  uint16_t joysval = 0;
+#ifdef PIN_JOY2_A1X
+  int xReading = emu_ReadAnalogJoyX(0,256);
+  if (xReading > 128) joysval |= MASK_JOY2_LEFT;
+  else if (xReading < 128) joysval |= MASK_JOY2_RIGHT;
+  
+  int yReading = emu_ReadAnalogJoyY(0,256);
+  if (yReading < 128) joysval |= MASK_JOY2_UP;
+  else if (yReading > 128) joysval |= MASK_JOY2_DOWN;
+#endif 
+  // First joystick
+#if INVY
+#ifdef PIN_JOY2_1
+  if ( !gpio_get(PIN_JOY2_1) ) joysval |= MASK_JOY2_DOWN;
+#endif
+#ifdef PIN_JOY2_2
+  if ( !gpio_get(PIN_JOY2_2) ) joysval |= MASK_JOY2_UP;
+#endif
+#else
+#ifdef PIN_JOY2_1
+  if ( !gpio_get(PIN_JOY2_1) ) joysval |= MASK_JOY2_UP;
+#endif
+#ifdef PIN_JOY2_2
+  if ( !gpio_get(PIN_JOY2_2) ) joysval |= MASK_JOY2_DOWN;
+#endif
+#endif
+#if INVX
+#ifdef PIN_JOY2_3
+  if ( !gpio_get(PIN_JOY2_3) ) joysval |= MASK_JOY2_LEFT;
+#endif
+#ifdef PIN_JOY2_4
+  if ( !gpio_get(PIN_JOY2_4) ) joysval |= MASK_JOY2_RIGHT;
+#endif
+#else
+#ifdef PIN_JOY2_3
+  if ( !gpio_get(PIN_JOY2_3) ) joysval |= MASK_JOY2_RIGHT;
+#endif
+#ifdef PIN_JOY2_4
+  if ( !gpio_get(PIN_JOY2_4) ) joysval |= MASK_JOY2_LEFT;
+#endif
+#endif
+#ifdef PIN_JOY2_BTN
+  joysval |= (gpio_get(PIN_JOY2_BTN) ? 0 : MASK_JOY2_BTN);
+#endif
+
+  return (joysval);     
+}
+
+
+int emu_SwapJoysticks(int statusOnly) {
+  if (!statusOnly) {
+    if (joySwapped) {
+      joySwapped = false;
+    }
+    else {
+      joySwapped = true;
+    }
+  }
+  return(joySwapped?1:0);
+}
+
+int emu_GetPad(void) 
+{
+  return(bLastState/*|((joySwapped?1:0)<<7)*/);
+}
+
+int emu_ReadKeys(void) 
+{
+  uint16_t retval;
+  uint16_t j1 = readAnalogJoystick();
+  uint16_t j2 = 0;
+  
+  // Second joystick
+#if INVY
+#ifdef PIN_JOY1_1
+  if ( !gpio_get(PIN_JOY1_1) ) j2 |= MASK_JOY2_DOWN;
+#endif
+#ifdef PIN_JOY1_2
+  if ( !gpio_get(PIN_JOY1_2) ) j2 |= MASK_JOY2_UP;
+#endif
+#else
+#ifdef PIN_JOY1_1
+  if ( !gpio_get(PIN_JOY1_1) ) j2 |= MASK_JOY2_UP;
+#endif
+#ifdef PIN_JOY1_2
+  if ( !gpio_get(PIN_JOY1_2) ) j2 |= MASK_JOY2_DOWN;
+#endif
+#endif
+#if INVX
+#ifdef PIN_JOY1_3
+  if ( !gpio_get(PIN_JOY1_3) ) j2 |= MASK_JOY2_LEFT;
+#endif
+#ifdef PIN_JOY1_4
+  if ( !gpio_get(PIN_JOY1_4) ) j2 |= MASK_JOY2_RIGHT;
+#endif
+#else
+#ifdef PIN_JOY1_3
+  if ( !gpio_get(PIN_JOY1_3) ) j2 |= MASK_JOY2_RIGHT;
+#endif
+#ifdef PIN_JOY1_4
+  if ( !gpio_get(PIN_JOY1_4) ) j2 |= MASK_JOY2_LEFT;
+#endif
+#endif
+#ifdef PIN_JOY1_BTN
+  if ( !gpio_get(PIN_JOY1_BTN) ) j2 |= MASK_JOY2_BTN;
+#endif
+
+
+  if (joySwapped) {
+    retval = ((j1 << 8) | j2);
+  }
+  else {
+    retval = ((j2 << 8) | j1);
+  }
+
+  if (usbnavpad & MASK_JOY2_UP) retval |= MASK_JOY2_UP;
+  if (usbnavpad & MASK_JOY2_DOWN) retval |= MASK_JOY2_DOWN;
+  if (usbnavpad & MASK_JOY2_LEFT) retval |= MASK_JOY2_LEFT;
+  if (usbnavpad & MASK_JOY2_RIGHT) retval |= MASK_JOY2_RIGHT;
+  if (usbnavpad & MASK_JOY2_BTN) retval |= MASK_JOY2_BTN;
+  if (usbnavpad & MASK_KEY_USER1) retval |= MASK_KEY_USER1;
+  if (usbnavpad & MASK_KEY_USER2) retval |= MASK_KEY_USER2;
+  if (usbnavpad & MASK_KEY_USER3) retval |= MASK_KEY_USER3;
+  if (usbnavpad & MASK_KEY_USER4) retval |= MASK_KEY_USER4;
+
+#ifdef PIN_KEY_USER1 
+  if ( !gpio_get(PIN_KEY_USER1) ) retval |= MASK_KEY_USER1;
+#endif
+#ifdef PIN_KEY_USER2 
+  if ( !gpio_get(PIN_KEY_USER2) ) retval |= MASK_KEY_USER2;
+#endif
+#ifdef PIN_KEY_USER3 
+  if ( !gpio_get(PIN_KEY_USER3) ) retval |= MASK_KEY_USER3;
+#endif
+#ifdef PIN_KEY_USER4 
+  if ( !gpio_get(PIN_KEY_USER4) ) retval |= MASK_KEY_USER4;
+#endif
+
+
+#if (defined(PICOMPUTER) || defined(PICOZX) )
+  keymatrix_hitrow = -1;
+  unsigned char row;
+#ifdef PICOZX  
+  unsigned short cols[7]={KCOLOUT1,KCOLOUT2,KCOLOUT3,KCOLOUT4,KCOLOUT5,KCOLOUT6,KCOLOUT7};
+  unsigned char keymatrixtmp[7];
+  for (int i=0;i<7;i++){
+#else  
+  unsigned short cols[6]={KCOLOUT1,KCOLOUT2,KCOLOUT3,KCOLOUT4,KCOLOUT5,KCOLOUT6};
+  unsigned char keymatrixtmp[6];
+  for (int i=0;i<6;i++){
+#endif
+    gpio_set_dir(cols[i], GPIO_OUT);
+    gpio_put(cols[i], 0);
+#ifdef SWAP_ALT_DEL
+    sleep_us(1);
+    //__asm volatile ("nop\n"); // 4-8ns
+#endif
+    row=0; 
+#ifdef PICOZX  
+    row |= (gpio_get(KROWIN1) ? 0 : 0x04);
+    row |= (gpio_get(KROWIN1) ? 0 : 0x04);
+    row |= (gpio_get(KROWIN1) ? 0 : 0x04);
+    row |= (gpio_get(KROWIN1) ? 0 : 0x04);
+    row |= (gpio_get(KROWIN2) ? 0 : 0x01);
+    row |= (gpio_get(KROWIN3) ? 0 : 0x08);
+    row |= (gpio_get(KROWIN4) ? 0 : 0x02);
+    row |= (gpio_get(KROWIN5) ? 0 : 0x10);
+    row |= (gpio_get(KROWIN6) ? 0 : 0x20);
+    row |= (gpio_get(KROWIN7) ? 0 : 0x40);
+#else
+    row |= (gpio_get(KROWIN2) ? 0 : 0x01);
+    row |= (gpio_get(KROWIN2) ? 0 : 0x01);
+    row |= (gpio_get(KROWIN2) ? 0 : 0x01);
+    row |= (gpio_get(KROWIN2) ? 0 : 0x01);
+    row |= (gpio_get(KROWIN4) ? 0 : 0x02);
+    row |= (gpio_get(KROWIN1) ? 0 : 0x04);
+    row |= (gpio_get(KROWIN3) ? 0 : 0x08);
+    row |= (gpio_get(KROWIN5) ? 0 : 0x10);
+    row |= (gpio_get(KROWIN6) ? 0 : 0x20);
+#endif    
+    //gpio_set_dir(cols[i], GPIO_OUT);
+    gpio_put(cols[i], 1);
+    gpio_set_dir(cols[i], GPIO_IN);
+    gpio_disable_pulls(cols[i]); 
+    keymatrixtmp[i] = row;
+  }
+
+#ifdef SWAP_ALT_DEL
+  // Swap ALT and DEL  
+  unsigned char alt = keymatrixtmp[0] & 0x02;
+  unsigned char del = keymatrixtmp[5] & 0x20;
+  keymatrixtmp[0] &= ~0x02;
+  keymatrixtmp[5] &= ~0x20;
+  if (alt) keymatrixtmp[5] |= 0x20;
+  if (del) keymatrixtmp[0] |= 0x02;
+#endif
+
+
+#ifdef PICOZX  
+  for (int i=0;i<7;i++){
+#else  
+  bool alt_pressed=false;
+  if ( keymatrixtmp[5] & 0x20 ) {alt_pressed=true; keymatrixtmp[5] &= ~0x20;};
+  for (int i=0;i<6;i++){
+#endif
+    row = keymatrixtmp[i];
+    if (row) keymatrix_hitrow=i;
+    keymatrix[i] = row;
+  }
+
+#ifdef PICOZX
+  //row = keymatrix[6];
+  if ( row & 0x02 ) retval |= MASK_KEY_USER1;
+  if ( row & 0x10 ) retval |= MASK_KEY_USER2;
+  if ( row & 0x20 ) retval |= MASK_KEY_USER3;
+  if ( row & 0x40 ) retval |= MASK_KEY_USER4;
+  row = keymatrix[0];
+  key_fn = false;
+  key_alt = false;
+  if ( row & 0x20 ) {key_fn = true; keymatrix[0] &= ~0x20;}
+  if ( row & 0x40 ) {key_alt = true;keymatrix[0] &= ~0x40; }
+  //19,20,21,22,26,27,28  
+#if INVX
+  if ( row & 0x2  ) retval |= MASK_JOY2_LEFT;
+  if ( row & 0x1  ) retval |= MASK_JOY2_RIGHT;
+#else
+  if ( row & 0x1  ) retval |= MASK_JOY2_LEFT;
+  if ( row & 0x2  ) retval |= MASK_JOY2_RIGHT;
+#endif
+#if INVY
+  if ( row & 0x8  ) retval |= MASK_JOY2_DOWN;
+  if ( row & 0x10  ) retval |= MASK_JOY2_UP;  
+#else
+  if ( row & 0x10  ) retval |= MASK_JOY2_DOWN;
+  if ( row & 0x8  ) retval |= MASK_JOY2_UP;  
+#endif
+  if ( row & 0x04 ) retval |= MASK_JOY2_BTN;
+
+#else // end PICOZX 
+  //6,9,15,8,7,22
+#if INVX
+  if ( row & 0x2  ) retval |= MASK_JOY2_LEFT;
+  if ( row & 0x1  ) retval |= MASK_JOY2_RIGHT;
+#else
+  if ( row & 0x1  ) retval |= MASK_JOY2_LEFT;
+  if ( row & 0x2  ) retval |= MASK_JOY2_RIGHT;
+#endif
+#if INVY
+  if ( row & 0x8  ) retval |= MASK_JOY2_DOWN;
+  if ( row & 0x4  ) retval |= MASK_JOY2_UP;  
+#else
+  if ( row & 0x4  ) retval |= MASK_JOY2_DOWN;
+  if ( row & 0x8  ) retval |= MASK_JOY2_UP;  
+#endif
+  if ( row & 0x10 ) retval |= MASK_JOY2_BTN;
+
+  if ( key_fn ) retval |= MASK_KEY_USER2;
+  if ( ( key_fn ) && (keymatrix[0] == 0x02 )) retval |= MASK_KEY_USER1;
+
+  // Handle LED flash
+  uint32_t time_ms=to_ms_since_boot (get_absolute_time());
+  if ((time_ms-last_t_ms) > 100) {
+    last_t_ms = time_ms;
+    if (ledflash_toggle == false) {
+      ledflash_toggle = true;
+    }
+    else {
+      ledflash_toggle = false;
+    }  
+  }  
+ 
+  if ( alt_pressed ) {
+    if (key_fn == false) 
+    {
+      // Release to Press transition
+      if (hundred_ms_cnt == 0) {
+        keypress_t_ms=time_ms;
+        hundred_ms_cnt += 1; // 1
+      }  
+      else {
+        hundred_ms_cnt += 1; // 2
+        if (hundred_ms_cnt >= 2) 
+        { 
+          hundred_ms_cnt = 0;
+          /* 
+          if ( (time_ms-keypress_t_ms) < 500) 
+          {
+            if (key_alt == false) 
+            {
+              key_alt = true;
+            }
+            else 
+            {
+              key_alt = false;
+            } 
+          }
+          */
+        }        
+      }
+    }
+    else {
+      // Keep press
+      if (hundred_ms_cnt == 1) {
+        if ((to_ms_since_boot (get_absolute_time())-keypress_t_ms) > 2000) 
+        {
+          if (key_alt == false) 
+          {
+            key_alt = true;
+          }
+          else 
+          {
+            key_alt = false;
+          } 
+          hundred_ms_cnt = 0; 
+        }
+      } 
+    } 
+    key_fn = true;
+  }
+  else  {
+    key_fn = false;    
+  }
+
+#ifdef KLED
+  // Handle LED
+  if (key_alt == true) {
+    gpio_put(KLED, (ledflash_toggle?1:0));
+  }
+  else {
+    if (key_fn == true) {
+      gpio_put(KLED, 1);
+    }
+    else {
+      gpio_put(KLED, 0);
+    }     
+  } 
+#endif
+
+#endif
+
+
+#endif
+
+  //Serial.println(retval,HEX);
+
+  if ( ((retval & (MASK_KEY_USER1+MASK_KEY_USER2)) == (MASK_KEY_USER1+MASK_KEY_USER2))
+     || (retval & MASK_KEY_USER4 ) )
+  {  
+  }
+
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+  if (oskbOn) {
+    retval |= MASK_OSKB; 
+  }  
+#endif  
+  
+  return (retval);
+}
+
+unsigned short emu_DebounceLocalKeys(void)
+{
+#ifdef HAS_USBHOST
+  tuh_task();
+#endif
+  uint16_t bCurState = emu_ReadKeys();
+  uint16_t bClick = bCurState & ~bLastState;
+  bLastState = bCurState;
+  return (bClick);
+}
+
+int emu_ReadI2CKeyboard(void) {
+  int retval=0;
+#if (defined(PICOMPUTER) || defined(PICOZX) )
+  if (key_alt) {
+    keys = (const unsigned short *)key_map3;
+  }
+  else if (key_fn) {
+    keys = (const unsigned short *)key_map2;
+  }
+  else {
+    keys = (const unsigned short *)key_map1;
+  }
+  if (keymatrix_hitrow >=0 ) {
+    unsigned short match = ((unsigned short)keymatrix_hitrow<<8) | keymatrix[keymatrix_hitrow];  
+    for (int i=0; i<sizeof(matkeys)/sizeof(unsigned short); i++) {
+      if (match == matkeys[i]) {
+        hundred_ms_cnt = 0;
+        return (keys[i]);
+      }
+    }
+  }
+#endif
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+  if (!menuOn) {
+    retval = handleOskb(); 
+  }  
+#endif  
+  return(retval);
+}
+
+unsigned char emu_ReadI2CKeyboard2(int row) {
+  int retval=0;
+#if (defined(PICOMPUTER) || defined(PICOZX) )
+  retval = keymatrix[row];
+#endif
+  return retval;
+}
+
+
+void emu_InitJoysticks(void) { 
+
+  // Second Joystick   
+#ifdef PIN_JOY1_1
+  gpio_init(PIN_JOY1_1);
+  gpio_set_pulls(PIN_JOY1_1,true,false);
+  gpio_set_dir(PIN_JOY1_1,GPIO_IN);  
+#endif  
+#ifdef PIN_JOY1_2
+  gpio_init(PIN_JOY1_2);
+  gpio_set_pulls(PIN_JOY1_2,true,false);
+  gpio_set_dir(PIN_JOY1_2,GPIO_IN);  
+#endif  
+#ifdef PIN_JOY1_3
+  gpio_init(PIN_JOY1_3);
+  gpio_set_pulls(PIN_JOY1_3,true,false);
+  gpio_set_dir(PIN_JOY1_3,GPIO_IN);  
+#endif  
+#ifdef PIN_JOY1_4
+  gpio_init(PIN_JOY1_4);
+  gpio_set_pulls(PIN_JOY1_4,true,false);
+  gpio_set_dir(PIN_JOY1_4,GPIO_IN);  
+#endif  
+#ifdef PIN_JOY1_BTN
+  gpio_init(PIN_JOY1_BTN);
+  gpio_set_pulls(PIN_JOY1_BTN,true,false);
+  gpio_set_dir(PIN_JOY1_BTN,GPIO_IN);  
+#endif  
+
+  // User keys   
+#ifdef PIN_KEY_USER1
+  gpio_init(PIN_KEY_USER1);
+  gpio_set_pulls(PIN_KEY_USER1,true,false);
+  gpio_set_dir(PIN_KEY_USER1,GPIO_IN);  
+#endif  
+#ifdef PIN_KEY_USER2
+  gpio_init(PIN_KEY_USER2);
+  gpio_set_dir(PIN_KEY_USER2,GPIO_IN);
+  gpio_set_pulls(PIN_KEY_USER2,true,false);
+#endif  
+#ifdef PIN_KEY_USER3
+  gpio_init(PIN_KEY_USER3);
+  gpio_set_pulls(PIN_KEY_USER3,true,false);
+  gpio_set_dir(PIN_KEY_USER3,GPIO_IN);  
+#endif  
+#ifdef PIN_KEY_USER4
+  gpio_init(PIN_KEY_USER4);
+  gpio_set_pulls(PIN_KEY_USER4,true,false);
+  gpio_set_dir(PIN_KEY_USER4,GPIO_IN);  
+#endif  
+
+  // First Joystick   
+#ifdef PIN_JOY2_1
+  gpio_init(PIN_JOY2_1);
+  gpio_set_pulls(PIN_JOY2_1,true,false);
+  gpio_set_dir(PIN_JOY2_1,GPIO_IN);
+  gpio_set_input_enabled(PIN_JOY2_1, true); // Force ADC as digital input        
+#endif  
+#ifdef PIN_JOY2_2
+  gpio_init(PIN_JOY2_2);
+  gpio_set_pulls(PIN_JOY2_2,true,false);
+  gpio_set_dir(PIN_JOY2_2,GPIO_IN);  
+  gpio_set_input_enabled(PIN_JOY2_2, true);  // Force ADC as digital input       
+#endif  
+#ifdef PIN_JOY2_3
+  gpio_init(PIN_JOY2_3);
+  gpio_set_pulls(PIN_JOY2_3,true,false);
+  gpio_set_dir(PIN_JOY2_3,GPIO_IN);  
+  gpio_set_input_enabled(PIN_JOY2_3, true);  // Force ADC as digital input        
+#endif  
+#ifdef PIN_JOY2_4
+  gpio_init(PIN_JOY2_4);
+  gpio_set_pulls(PIN_JOY2_4,true,false);
+  gpio_set_dir(PIN_JOY2_4,GPIO_IN);  
+#endif  
+#ifdef PIN_JOY2_BTN
+  gpio_init(PIN_JOY2_BTN);
+  gpio_set_pulls(PIN_JOY2_BTN,true,false);
+  gpio_set_dir(PIN_JOY2_BTN,GPIO_IN);  
+#endif  
+ 
+#ifdef PIN_JOY2_A1X
+  adc_init(); 
+  adc_gpio_init(PIN_JOY2_A1X);
+  adc_gpio_init(PIN_JOY2_A2Y);
+  xRef=0; yRef=0;
+  for (int i=0; i<10; i++) {
+    adc_select_input(0);  
+    xRef += adc_read();
+    adc_select_input(1);  
+    yRef += adc_read();
+    sleep_ms(20);
+  }
+#if INVX
+  xRef = 4095 -xRef/10;
+#else
+  xRef /= 10;
+#endif
+#if INVY
+  yRef = 4095 -yRef/10;
+#else
+  yRef /= 10;
+#endif
+#endif
+
+#if (defined(PICOMPUTER) || defined(PICOZX) ) 
+  // keyboard LED
+#ifdef KLED  
+  gpio_init(KLED);
+  gpio_set_dir(KLED, GPIO_OUT);
+  gpio_put(KLED, 1);
+#endif
+  // Output (rows)
+  gpio_init(KCOLOUT1);
+  gpio_init(KCOLOUT2);
+  gpio_init(KCOLOUT3);
+  gpio_init(KCOLOUT4);
+  gpio_init(KCOLOUT5);
+  gpio_init(KCOLOUT6);
+#ifdef PICOZX
+  gpio_init(KCOLOUT7);
+#endif  
+  gpio_set_dir(KCOLOUT1, GPIO_OUT); 
+  gpio_set_dir(KCOLOUT2, GPIO_OUT); 
+  gpio_set_dir(KCOLOUT3, GPIO_OUT); 
+  gpio_set_dir(KCOLOUT4, GPIO_OUT); 
+  gpio_set_dir(KCOLOUT5, GPIO_OUT); 
+  gpio_set_dir(KCOLOUT6, GPIO_OUT);
+#ifdef PICOZX
+  gpio_set_dir(KCOLOUT7, GPIO_OUT);
+#endif   
+  gpio_put(KCOLOUT1, 1);
+  gpio_put(KCOLOUT2, 1);
+  gpio_put(KCOLOUT3, 1);
+  gpio_put(KCOLOUT4, 1);
+  gpio_put(KCOLOUT5, 1);
+  gpio_put(KCOLOUT6, 1);
+#ifdef PICOZX
+  gpio_put(KCOLOUT7, 1);
+#endif   
+  // but set as input floating when not used!
+  gpio_set_dir(KCOLOUT1, GPIO_IN); 
+  gpio_set_dir(KCOLOUT2, GPIO_IN); 
+  gpio_set_dir(KCOLOUT3, GPIO_IN); 
+  gpio_set_dir(KCOLOUT4, GPIO_IN); 
+  gpio_set_dir(KCOLOUT5, GPIO_IN); 
+  gpio_set_dir(KCOLOUT6, GPIO_IN);
+#ifdef PICOZX
+  gpio_set_dir(KCOLOUT7, GPIO_IN);
+#endif   
+  gpio_disable_pulls(KCOLOUT1); 
+  gpio_disable_pulls(KCOLOUT2); 
+  gpio_disable_pulls(KCOLOUT3); 
+  gpio_disable_pulls(KCOLOUT4); 
+  gpio_disable_pulls(KCOLOUT5); 
+  gpio_disable_pulls(KCOLOUT6);
+#ifdef PICOZX
+  gpio_disable_pulls(KCOLOUT7);
+#endif   
+  // Input pins (cols)
+  gpio_init(KROWIN1);
+  gpio_init(KROWIN2);
+  gpio_init(KROWIN3);
+  gpio_init(KROWIN4);
+  gpio_init(KROWIN5);
+  gpio_init(KROWIN6);
+#ifdef PICOZX
+  gpio_init(KROWIN7);
+#endif   
+  gpio_set_dir(KROWIN1,GPIO_IN);  
+  gpio_set_dir(KROWIN2,GPIO_IN);  
+  gpio_set_dir(KROWIN3,GPIO_IN);  
+  gpio_set_dir(KROWIN4,GPIO_IN);  
+  gpio_set_dir(KROWIN5,GPIO_IN);  
+  gpio_set_dir(KROWIN6,GPIO_IN);  
+#ifdef PICOZX
+  gpio_set_dir(KROWIN7,GPIO_IN);  
+#endif 
+  gpio_pull_up(KROWIN1);
+  gpio_pull_up(KROWIN2);
+  gpio_pull_up(KROWIN3);
+  gpio_pull_up(KROWIN4);
+  gpio_pull_up(KROWIN5);
+  gpio_pull_up(KROWIN6);
+#ifdef PICOZX
+  gpio_pull_up(KROWIN7);
+#endif 
+#endif
+}
+
+int emu_setKeymap(int index) {
+  return 0;
+}
+
+
+
+/********************************
+ * Menu file loader UI
+********************************/ 
+#include "ff.h"
+static FATFS fatfs;
+static FIL file; 
+extern "C" int sd_init_driver(void);
+
+#ifdef FILEBROWSER
+static int readNbFiles(char * rootdir) {
+  int totalFiles = 0;
+
+  DIR dir;
+  FILINFO entry;
+  FRESULT fr = f_findfirst(&dir, &entry, rootdir, "*");
+  while ( (fr == FR_OK) && (entry.fname[0]) && (totalFiles<MAX_FILES) ) {  
+    if (!entry.fname[0]) {
+      // no more files
+      break;
+    }
+
+    char * filename = entry.fname;
+    if ( !(entry.fattrib & AM_DIR) ) {
+      if (strcmp(filename,AUTORUN_FILENAME)) {
+        strncpy(&files[totalFiles][0], filename, MAX_FILENAME_SIZE-1);
+        totalFiles++;
+      }  
+    }
+    else {
+      if ( (strcmp(filename,".")) && (strcmp(filename,"..")) ) {
+        strncpy(&files[totalFiles][0], filename, MAX_FILENAME_SIZE-1);
+        totalFiles++;
+      }
+    }
+    fr = f_findnext(&dir, &entry);  
+  } 
+  f_closedir(&dir);
+
+  return totalFiles;  
+}  
+
+
+
+void backgroundMenu(void) {
+    menuRedraw=true;  
+    tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00));
+    tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true);           
+}
+
+
+static void menuLeft(void)
+{
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+  toggleOskb(true);  
+#endif
+}
+
+
+bool menuActive(void) 
+{
+  return (menuOn);
+}
+
+void toggleMenu(bool on) {
+  if (on) {
+    menuOn = true;
+    backgroundMenu();
+  } else {
+    tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00));    
+    menuOn = false;    
+  }
+}
+
+int handleMenu(uint16_t bClick)
+{
+  if (autorun) {
+      menuLeft();
+      toggleMenu(false);
+      menuRedraw=false;
+      return (ACTION_RUN);
+  }
+
+  if ( (bClick & MASK_JOY2_BTN) || (bClick & MASK_KEY_USER1) || (bClick & MASK_KEY_USER4) ) {
+    char newpath[MAX_FILENAME_PATH];
+    strcpy(newpath, selection);
+    strcat(newpath, "/");
+    strcat(newpath, selected_filename);
+    strcpy(selection,newpath);
+    emu_printf("new filepath is");
+    emu_printf(selection);
+    FILINFO entry;
+    FRESULT fr;
+    fr = f_stat(selection, &entry);
+    if ( (fr == FR_OK) && (entry.fattrib & AM_DIR) ) {
+        curFile = 0;
+        nbFiles = readNbFiles(selection);
+        menuRedraw=true;
+    }
+    else
+    {
+#ifdef PICOMPUTER
+      if (key_alt) {
+        emu_writeConfig();
+      }
+#endif
+#ifdef PICOZX
+      if (bClick & MASK_KEY_USER4) {
+        emu_writeConfig();
+      }
+#endif
+      menuLeft();
+      toggleMenu(false);
+      menuRedraw=false;
+#ifdef PICOZX
+      if ( tft.getMode() != MODE_VGA_320x240) {   
+        if ( (bClick & MASK_KEY_USER1) ) {
+          tft.begin(MODE_VGA_320x240);
+        }
+      }
+#endif
+      return (ACTION_RUN);
+    }
+  }
+  else if ( (bClick & MASK_JOY2_UP) || (bClick & MASK_JOY1_UP) ) {
+    if (curFile!=0) {
+      menuRedraw=true;
+      curFile--;
+    }
+  }
+  else if ( (bClick & MASK_JOY2_RIGHT) || (bClick & MASK_JOY1_RIGHT) ) {
+    if ((curFile-9)>=0) {
+      menuRedraw=true;
+      curFile -= 9;
+    } else if (curFile!=0) {
+      menuRedraw=true;
+      curFile--;
+    }
+  }  
+  else if ( (bClick & MASK_JOY2_DOWN) || (bClick & MASK_JOY1_DOWN) )  {
+    if ((curFile<(nbFiles-1)) && (nbFiles)) {
+      curFile++;
+      menuRedraw=true;
+    }
+  }
+  else if ( (bClick & MASK_JOY2_LEFT) || (bClick & MASK_JOY1_LEFT) ) {
+    if ((curFile<(nbFiles-9)) && (nbFiles)) {
+      curFile += 9;
+      menuRedraw=true;
+    }
+    else if ((curFile<(nbFiles-1)) && (nbFiles)) {
+      curFile++;
+      menuRedraw=true;
+    }
+  }
+  else if ( (bClick & MASK_KEY_USER2) ) {
+    emu_SwapJoysticks(0);
+    menuRedraw=true;  
+  } 
+
+  if (menuRedraw && nbFiles) {
+    int fileIndex = 0;
+    tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR);
+//    if (curFile <= (MAX_MENULINES/2-1)) topFile=0;
+//    else topFile=curFile-(MAX_MENULINES/2);
+    if (curFile <= (MAX_MENULINES-1)) topFile=0;
+    else topFile=curFile-(MAX_MENULINES/2);
+
+    int i=0;
+    while (i<MAX_MENULINES) {
+      if (fileIndex>=nbFiles) {
+          // no more files
+          break;
+      }
+      char * filename = &files[fileIndex][0];    
+      if (fileIndex >= topFile) {              
+        if ((i+topFile) < nbFiles ) {
+          if ((i+topFile)==curFile) {
+            tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true);
+            strcpy(selected_filename,filename);            
+          }
+          else {
+            tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, RGBVAL16(0xff,0xff,0xff), MENU_FILE_BGCOLOR, true);      
+          }
+        }
+        i++; 
+      }
+      fileIndex++;    
+    }
+
+     
+    tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), false);
+    menuRedraw=false;     
+  }
+
+  return (ACTION_NONE);  
+}
+
+char * menuSelection(void)
+{
+  return (selection);  
+}
+#endif
+
+
+
+/********************************
+ * USB keyboard
+********************************/ 
+#ifdef HAS_USBHOST
+
+#ifdef KEYBOARD_ACTIVATED
+static bool kbdasjoy = false;
+#else
+static bool kbdasjoy = true;
+#endif
+
+static void signal_joy (int code, int pressed, int flags) {
+  if ( (code == KBD_KEY_DOWN) && (pressed) ) usbnavpad |= MASK_JOY2_DOWN;
+  if ( (code == KBD_KEY_DOWN) && (!pressed) ) usbnavpad &= ~MASK_JOY2_DOWN;
+  if ( (code == KBD_KEY_UP) && (pressed) ) usbnavpad |= MASK_JOY2_UP;
+  if ( (code == KBD_KEY_UP) && (!pressed) ) usbnavpad &= ~MASK_JOY2_UP;
+#if INVX
+  if ( (code == KBD_KEY_RIGHT) && (pressed) ) usbnavpad |= MASK_JOY2_LEFT;
+  if ( (code == KBD_KEY_RIGHT) && (!pressed) ) usbnavpad &= ~MASK_JOY2_LEFT;
+  if ( (code == KBD_KEY_LEFT) && (pressed) ) usbnavpad |= MASK_JOY2_RIGHT;
+  if ( (code == KBD_KEY_LEFT) && (!pressed) ) usbnavpad &= ~MASK_JOY2_RIGHT;
+#else  
+  if ( (code == KBD_KEY_LEFT) && (pressed) ) usbnavpad |= MASK_JOY2_LEFT;
+  if ( (code == KBD_KEY_LEFT) && (!pressed) ) usbnavpad &= ~MASK_JOY2_LEFT;
+  if ( (code == KBD_KEY_RIGHT) && (pressed) ) usbnavpad |= MASK_JOY2_RIGHT;
+  if ( (code == KBD_KEY_RIGHT) && (!pressed) ) usbnavpad &= ~MASK_JOY2_RIGHT;
+#endif
+  if ( (code == '\t') && (pressed) ) usbnavpad |= MASK_JOY2_BTN; 
+  if ( (code == '\t') && (!pressed) ) usbnavpad &= ~MASK_JOY2_BTN;
+  if ( (code == '1') && (pressed) ) usbnavpad |= MASK_KEY_USER1; 
+  if ( (code == '1') && (!pressed) ) usbnavpad &= ~MASK_KEY_USER1;
+  if ( (code == '2') && (pressed) ) usbnavpad |= MASK_KEY_USER2; 
+  if ( (code == '2') && (!pressed) ) usbnavpad &= ~MASK_KEY_USER2;
+  //if ( (code == 'c') && (pressed) ) usbnavpad |= MASK_KEY_USER3; 
+  //if ( (code == 'c') && (!pressed) ) usbnavpad &= ~MASK_KEY_USER3;
+  if ( (code == KBD_KEY_CAPS) && (pressed) ) usbnavpad |= MASK_KEY_USER3; 
+  if ( (code == KBD_KEY_CAPS) && (!pressed) ) usbnavpad &= ~MASK_KEY_USER3;
+  if ( (code == ' ') && (pressed) ) usbnavpad |= MASK_KEY_USER4; 
+  if ( (code == ' ') && (!pressed) ) usbnavpad &= ~MASK_KEY_USER4;
+}
+
+void kbd_signal_raw_key (int keycode, int code, int codeshifted, int flags, int pressed) {
+  //printf("k %d\r\n", keycode); 
+#ifdef FILEBROWSER
+  if (menuActive())
+  {
+    signal_joy(code, pressed, flags);          
+  }
+  else  
+#endif  
+  {
+    // LCTRL + LSHIFT + J => keyboard as joystick
+    if ( ( ( (flags & (KBD_FLAG_LSHIFT + KBD_FLAG_LCONTROL)) == (KBD_FLAG_LSHIFT + KBD_FLAG_LCONTROL) ) && (!pressed) && (code == 'j') ) || ( (!pressed) && (keycode == 69) ) ) {
+      if (kbdasjoy == true) kbdasjoy = false; 
+      else kbdasjoy = true;
+    }
+
+    //keyboard as joystick?
+    if (kbdasjoy == true) {
+      signal_joy(code, pressed, flags);
+    }
+    else {
+      if (pressed == KEY_PRESSED)
+      {    
+        //emu_printi(keycode);    
+        //emu_printi(codeshifted);    
+        emu_KeyboardOnDown(flags, codeshifted);
+      }
+      else    
+      { 
+        emu_KeyboardOnUp(flags, codeshifted);
+      }
+    }
+  }
+  return;
+}
+#endif
+
+
+/********************************
+ * File IO
+********************************/ 
+int emu_FileOpen(const char * filepath, const char * mode)
+{
+  int retval = 0;
+
+  emu_printf("FileOpen...");
+  emu_printf(filepath);
+  if( !(f_open(&file, filepath, FA_READ)) ) {
+    retval = 1;  
+  }
+  else {
+    emu_printf("FileOpen failed");
+  }
+  return (retval);
+}
+
+int emu_FileRead(void * buf, int size, int handler)
+{
+  unsigned int retval=0; 
+  f_read (&file, (void*)buf, size, &retval);
+  return retval; 
+}
+
+int emu_FileGetc(int handler)
+{
+  unsigned char c;
+  unsigned int retval=0;
+  if( !(f_read (&file, &c, 1, &retval)) )
+  if (retval != 1) {
+    emu_printf("emu_FileGetc failed");
+  }  
+  return (int)c; 
+}
+
+void emu_FileClose(int handler)
+{
+  f_close(&file); 
+}
+
+int emu_FileSeek(int handler, int seek, int origin)
+{
+  f_lseek(&file, seek);
+  return (seek);
+}
+
+int emu_FileTell(int handler)
+{
+  return (f_tell(&file));
+}
+
+
+unsigned int emu_FileSize(const char * filepath)
+{
+  int filesize=0;
+  emu_printf("FileSize...");
+  emu_printf(filepath);
+  FILINFO entry;
+  f_stat(filepath, &entry);
+  filesize = entry.fsize; 
+  return(filesize);    
+}
+
+unsigned int emu_LoadFile(const char * filepath, void * buf, int size)
+{
+  int filesize = 0;
+    
+  emu_printf("LoadFile...");
+  emu_printf(filepath);
+  if( !(f_open(&file, filepath, FA_READ)) ) {
+    filesize = f_size(&file);
+    emu_printf(filesize);
+    if (size >= filesize)
+    {
+      unsigned int retval=0;
+      if( (f_read (&file, buf, filesize, &retval)) ) {
+        emu_printf("File read failed");        
+      }
+    }
+    f_close(&file);
+  }
+ 
+  return(filesize);
+}
+
+static FIL outfile; 
+
+static bool emu_writeGfxConfig(void)
+{
+  bool retval = false;
+  if( !(f_open(&outfile, "/" GFX_CFG_FILENAME, FA_CREATE_NEW | FA_WRITE)) ) {
+    f_close(&outfile);
+    retval = true;
+  } 
+  return retval;   
+}
+
+static bool emu_readGfxConfig(void)
+{
+  bool retval = false;
+  if( !(f_open(&outfile, "/" GFX_CFG_FILENAME, FA_READ)) ) {
+    f_close(&outfile);
+    retval = true;
+  }  
+  return retval;   
+}
+
+static bool emu_eraseGfxConfig(void)
+{
+  f_unlink ("/" GFX_CFG_FILENAME);
+  return true;
+}
+
+static bool emu_writeConfig(void)
+{
+  bool retval = false;
+  if( !(f_open(&outfile, ROMSDIR "/" AUTORUN_FILENAME, FA_CREATE_NEW | FA_WRITE)) ) {
+    unsigned int sizeread=0;
+    if( (f_write (&outfile, selection, strlen(selection), &sizeread)) ) {
+      emu_printf("Config write failed");        
+    }
+    else {
+      retval = true;
+    }  
+    f_close(&outfile);   
+  } 
+  return retval; 
+}
+
+#ifdef HAS_USBHOST          
+static bool emu_readKbdConfig(void)
+{
+  bool retval = false;
+  char scratchpad[64]={0};
+  if( !(f_open(&outfile, "/" KBD_CFG_FILENAME , FA_READ)) ) {
+    while (f_gets(scratchpad, 64, &outfile) != NULL)  {
+      if (!strncmp(scratchpad, "keyboard=", 9)) {
+        if ( ( scratchpad[9]=='u') && (scratchpad[10]=='k') ) {
+          kbd_set_locale(KLAYOUT_UK);
+        }
+        else if ( ( scratchpad[9]=='b') && (scratchpad[10]=='e') ) {
+          kbd_set_locale(KLAYOUT_BE);
+        }       
+      }  
+    }
+    f_close(&outfile);
+    retval = true;
+  }  
+  return retval;   
+}
+#endif
+
+static bool emu_readConfig(void)
+{
+  bool retval = false;
+  if( !(f_open(&outfile, ROMSDIR "/" AUTORUN_FILENAME, FA_READ)) ) {
+    unsigned int filesize = f_size(&outfile);
+    unsigned int sizeread=0;
+    if( (f_read (&outfile, selection, filesize, &sizeread)) ) {
+      emu_printf("Config read failed");        
+    }
+    else {
+      if (sizeread == filesize) {
+        selection[filesize]=0;
+        retval = true;
+      }
+    }  
+    f_close(&outfile);   
+  }  
+  return retval; 
+}
+
+static bool emu_eraseConfig(void)
+{
+  f_unlink (ROMSDIR "/" AUTORUN_FILENAME);
+  return true;
+}
+
+
+/********************************
+ * Initialization
+********************************/ 
+void emu_init(void)
+{
+  //board_init();
+  stdio_init_all();
+
+  bool forceVga = false;
+
+#ifdef HAS_USBHOST
+  printf("Init USB...\n");
+  printf("USB D+/D- on GP%d and GP%d\r\n", PIO_USB_DP_PIN_DEFAULT, PIO_USB_DP_PIN_DEFAULT+1);
+  printf("TinyUSB Host HID Controller Example\r\n");
+  tuh_init(BOARD_TUH_RHPORT);
+#endif
+
+#ifdef FILEBROWSER
+//  sd_init_driver(); 
+
+  int retry=5;
+  FRESULT fr = FR_NO_FILESYSTEM;
+  while ((retry > 0) && (fr != FR_OK)) {
+    fr = f_mount(&fatfs, "", 0); 
+    sleep_ms(500); 
+    retry--; 
+  }
+  if (fr != FR_OK) {
+    emu_printf("mount fail"); 
+  }     
+
+#ifdef HAS_USBHOST          
+  emu_readKbdConfig();
+#endif
+
+  forceVga = emu_readGfxConfig();
+
+  strcpy(selection,ROMSDIR);
+  nbFiles = readNbFiles(selection); 
+
+  emu_printf("SD initialized, files found: ");
+  emu_printi(nbFiles);
+#endif
+  
+  emu_InitJoysticks();
+#ifdef SWAP_JOYSTICK
+  joySwapped = true;   
+#else
+  joySwapped = false;   
+#endif  
+
+int keypressed = emu_ReadKeys();
+
+#ifdef USE_VGA    
+    tft.begin(MODE_VGA_320x240);
+#else
+
+#ifdef PICOZX    
+  // Force VGA if LEFT/RIGHT pressed
+  if (keypressed & MASK_JOY2_UP)
+  {
+    tft.begin(MODE_VGA_320x240);
+#ifdef FILEBROWSER
+    emu_writeGfxConfig();
+#endif    
+  }
+  else
+  {
+    if ( (keypressed & MASK_JOY2_LEFT) || (keypressed & MASK_JOY2_RIGHT) )
+    {
+#ifdef FILEBROWSER
+        emu_eraseGfxConfig();
+#endif    
+        forceVga = false;
+    }
+    if (forceVga) {
+      tft.begin(MODE_VGA_320x240);
+    }
+    else
+    {
+      tft.begin(MODE_TFT_320x240);    
+    }     
+  }
+#else /* end PICOZX */
+  tft.begin(MODE_TFT_320x240);    
+#endif 
+
+#endif
+
+#ifndef USE_VGA    
+#ifdef PICOMPUTER
+  // Flip screen if UP pressed
+  if (keypressed & MASK_JOY2_UP)
+  {
+    tft.flipscreen(true);
+  }
+  else 
+  {
+    tft.flipscreen(false);
+  }
+#endif
+#endif
+
+  if (keypressed & MASK_JOY2_DOWN) {
+    tft.fillScreenNoDma( RGBVAL16(0xff,0x00,0x00) );
+    tft.drawTextNoDma(64,48,    (char*)" AUTURUN file erased", RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true);
+    tft.drawTextNoDma(64,48+24, (char*)"Please reset the board!", RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true);
+    emu_eraseConfig();
+  }
+  else {
+    if (emu_readConfig()) {
+      autorun = true;
+    }
+  }  
+
+#ifdef FILEBROWSER
+  toggleMenu(true);
+#endif  
+}
+
+
+void emu_start(void)
+{
+  usbnavpad = 0;
+
+  keyMap = 0;
+}
diff --git a/MCUME_pico2/display/emuapi.h b/MCUME_pico2/display/emuapi.h
new file mode 100644
index 0000000..0bbc629
--- /dev/null
+++ b/MCUME_pico2/display/emuapi.h
@@ -0,0 +1,92 @@
+#ifndef EMUAPI_H
+#define EMUAPI_H
+
+#include "platform_config.h"
+#include "emucfg.h"
+
+#define ACTION_NONE     0
+#define ACTION_RUN      1
+
+#define MASK_JOY2_RIGHT 0x0001
+#define MASK_JOY2_LEFT  0x0002
+#define MASK_JOY2_UP    0x0004
+#define MASK_JOY2_DOWN  0x0008
+#define MASK_JOY2_BTN   0x0010
+#define MASK_KEY_USER1  0x0020
+#define MASK_KEY_USER2  0x0040
+#define MASK_KEY_USER3  0x0080
+#define MASK_JOY1_RIGHT 0x0100
+#define MASK_JOY1_LEFT  0x0200
+#define MASK_JOY1_UP    0x0400
+#define MASK_JOY1_DOWN  0x0800
+#define MASK_JOY1_BTN   0x1000
+#define MASK_KEY_USER4  0x2000
+#define MASK_OSKB       0x8000
+
+#define RGBVAL16(r,g,b)  ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) )
+#define RGB888(r, g, b) ((r<<16) | (g << 8 ) | b )
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+extern void emu_init(void);
+extern void emu_start(void);
+extern void emu_resetSD(void);
+
+extern void emu_printf(const char * text);
+extern void emu_printi(int val);
+extern void * emu_Malloc(int size);
+extern void emu_Free(void * pt);
+
+extern int emu_FileOpen(const char * filepath, const char * mode);
+extern int emu_FileRead(void * buf, int size, int handler);
+extern int emu_FileGetc(int handler);
+extern int emu_FileSeek(int handler, int seek, int origin);
+extern int emu_FileTell(int handler);
+extern void emu_FileClose(int handler);
+
+extern unsigned int emu_FileSize(const char * filepath);
+extern unsigned int emu_LoadFile(const char * filepath, void * buf, int size);
+
+extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index);
+extern void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line);
+extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line);
+extern void emu_DrawScreenPal16(unsigned char * VBuf, int width, int height, int stride);
+extern void emu_DrawVsync(void);
+extern int emu_FrameSkip(void);
+extern int emu_IsVga(void);
+//extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line);
+extern void * emu_LineBuffer(int line);
+
+extern void emu_InitJoysticks(void);
+extern int emu_SwapJoysticks(int statusOnly);
+extern unsigned short emu_DebounceLocalKeys(void);
+extern int emu_ReadKeys(void);
+extern int emu_GetPad(void);
+extern int emu_ReadAnalogJoyX(int min, int max);
+extern int emu_ReadAnalogJoyY(int min, int max);
+extern int emu_ReadI2CKeyboard(void);
+extern unsigned char emu_ReadI2CKeyboard2(int row);
+extern void emu_KeyboardOnUp(int keymodifer, int key);
+extern void emu_KeyboardOnDown(int keymodifer, int key);
+extern int emu_oskbActive(void);
+
+extern void emu_sndPlaySound(int chan, int volume, int freq);
+extern void emu_sndPlayBuzz(int size, int val);
+extern void emu_sndInit();
+extern void emu_resetus(void);
+extern int emu_us(void);
+
+extern int emu_setKeymap(int index);
+
+extern void emu_FileTempInit(void); 
+extern void emu_FileTempRead(int addr, unsigned char * val, int n); 
+extern void emu_FileTempWrite(int addr, unsigned char val); 
+extern void emu_printh(int val);
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/MCUME_pico2/display/font8x8.h b/MCUME_pico2/display/font8x8.h
new file mode 100644
index 0000000..8a556f3
--- /dev/null
+++ b/MCUME_pico2/display/font8x8.h
@@ -0,0 +1,148 @@
+
+// Font: c64_lower.64c
+
+const unsigned char font8x8[128][8] =
+{
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0000 (nul)
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0001
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0002
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0003
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0004
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0005
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0006
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0007
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0008
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0009
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000A
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000B
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000C
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000D
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000E
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+000F
+
+    { 0x7f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x7f, 0x00 },  // Space  // 0x10
+    { 0x00, 0x27, 0x31, 0x27, 0x21, 0x71, 0x00, 0x00 },  // F1     // 0x11
+    { 0x00, 0x77, 0x41, 0x77, 0x11, 0x71, 0x00, 0x00 },  // F2
+    { 0x00, 0x77, 0x41, 0x77, 0x41, 0x71, 0x00, 0x00 },  // F3
+    { 0x00, 0x17, 0x51, 0x77, 0x41, 0x41, 0x00, 0x00 },  // F4
+    { 0x00, 0x77, 0x11, 0x77, 0x41, 0x71, 0x00, 0x00 },  // F5
+    { 0x00, 0x77, 0x11, 0x77, 0x51, 0x71, 0x00, 0x00 },  // F6
+    { 0x00, 0x77, 0x41, 0x47, 0x41, 0x41, 0x00, 0x00 },  // F7
+    { 0x00, 0x77, 0x51, 0x77, 0x51, 0x71, 0x00, 0x00 },  // F8     // 0x18
+    { 0x00, 0x00, 0x20, 0x24, 0x3e, 0x04, 0x00, 0x00 },  // Return // 0x19
+    { 0x00, 0x59, 0x4b, 0x5b, 0x4b, 0xd9, 0x00, 0x00 },  // Del    // 0x1A
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0010
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0011
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0012
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0013
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0014
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0015
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0016
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0017
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0018
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0019
+    //{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001A
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001B
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001C
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001D
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001E
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+001F
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0020 (space)
+    { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00},   // U+0021 (!)
+    { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0022 (")
+    { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00},   // U+0023 (#)
+    { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00},   // U+0024 ($)
+    { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00},   // U+0025 (%)
+    { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00},   // U+0026 (&)
+    { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0027 (')
+    { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00},   // U+0028 (()
+    { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00},   // U+0029 ())
+    { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00},   // U+002A (*)
+    { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00},   // U+002B (+)
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06},   // U+002C (,)
+    { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00},   // U+002D (-)
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00},   // U+002E (.)
+    { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00},   // U+002F (/)
+    { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00},   // U+0030 (0)
+    { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00},   // U+0031 (1)
+    { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00},   // U+0032 (2)
+    { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00},   // U+0033 (3)
+    { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00},   // U+0034 (4)
+    { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00},   // U+0035 (5)
+    { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00},   // U+0036 (6)
+    { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00},   // U+0037 (7)
+    { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00},   // U+0038 (8)
+    { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00},   // U+0039 (9)
+    { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00},   // U+003A (:)
+    { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06},   // U+003B (//)
+    { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00},   // U+003C (<)
+    { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00},   // U+003D (=)
+    { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00},   // U+003E (>)
+    { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00},   // U+003F (?)
+    { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00},   // U+0040 (@)
+    { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00},   // U+0041 (A)
+    { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00},   // U+0042 (B)
+    { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00},   // U+0043 (C)
+    { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00},   // U+0044 (D)
+    { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00},   // U+0045 (E)
+    { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00},   // U+0046 (F)
+    { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00},   // U+0047 (G)
+    { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00},   // U+0048 (H)
+    { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00},   // U+0049 (I)
+    { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00},   // U+004A (J)
+    { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00},   // U+004B (K)
+    { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00},   // U+004C (L)
+    { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00},   // U+004D (M)
+    { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00},   // U+004E (N)
+    { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00},   // U+004F (O)
+    { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00},   // U+0050 (P)
+    { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00},   // U+0051 (Q)
+    { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00},   // U+0052 (R)
+    { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00},   // U+0053 (S)
+    { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00},   // U+0054 (T)
+    { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00},   // U+0055 (U)
+    { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00},   // U+0056 (V)
+    { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00},   // U+0057 (W)
+    { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00},   // U+0058 (X)
+    { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00},   // U+0059 (Y)
+    { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00},   // U+005A (Z)
+    { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00},   // U+005B ([)
+    { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00},   // U+005C (\)
+    { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00},   // U+005D (])
+    { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00},   // U+005E (^)
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF},   // U+005F (_)
+    { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+0060 (`)
+    { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00},   // U+0061 (a)
+    { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00},   // U+0062 (b)
+    { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00},   // U+0063 (c)
+    { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00},   // U+0064 (d)
+    { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00},   // U+0065 (e)
+    { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00},   // U+0066 (f)
+    { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F},   // U+0067 (g)
+    { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00},   // U+0068 (h)
+    { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00},   // U+0069 (i)
+    { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E},   // U+006A (j)
+    { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00},   // U+006B (k)
+    { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00},   // U+006C (l)
+    { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00},   // U+006D (m)
+    { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00},   // U+006E (n)
+    { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00},   // U+006F (o)
+    { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F},   // U+0070 (p)
+    { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78},   // U+0071 (q)
+    { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00},   // U+0072 (r)
+    { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00},   // U+0073 (s)
+    { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00},   // U+0074 (t)
+    { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00},   // U+0075 (u)
+    { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00},   // U+0076 (v)
+    { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00},   // U+0077 (w)
+    { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00},   // U+0078 (x)
+    { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F},   // U+0079 (y)
+    { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00},   // U+007A (z)
+    { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00},   // U+007B ({)
+    { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00},   // U+007C (|)
+    { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00},   // U+007D (})
+    { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},   // U+007E (~)
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}    // U+007F
+};
+
+
diff --git a/MCUME_pico2/display/hdmi_framebuffer.cpp b/MCUME_pico2/display/hdmi_framebuffer.cpp
new file mode 100755
index 0000000..7df75c8
--- /dev/null
+++ b/MCUME_pico2/display/hdmi_framebuffer.cpp
@@ -0,0 +1,412 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hdmi_framebuffer.h"
+
+#include <stdio.h>
+#include <string.h>
+#include <cstdlib>
+
+#include "include.h"
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+#include "hardware/dma.h"
+#include "hardware/sync.h"
+#include "hardware/structs/bus_ctrl.h"
+#include "hardware/structs/hstx_ctrl.h"
+#include "hardware/structs/hstx_fifo.h"
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+#include "hardware/pwm.h"
+#include "iopins.h"
+// ----------------------------------------------------------------------------
+// DVI constants
+
+#define TMDS_CTRL_00 0x354u
+#define TMDS_CTRL_01 0x0abu
+#define TMDS_CTRL_10 0x154u
+#define TMDS_CTRL_11 0x2abu
+
+#define SYNC_V0_H0 (TMDS_CTRL_00 | (TMDS_CTRL_00 << 10) | (TMDS_CTRL_00 << 20))
+#define SYNC_V0_H1 (TMDS_CTRL_01 | (TMDS_CTRL_00 << 10) | (TMDS_CTRL_00 << 20))
+#define SYNC_V1_H0 (TMDS_CTRL_10 | (TMDS_CTRL_00 << 10) | (TMDS_CTRL_00 << 20))
+#define SYNC_V1_H1 (TMDS_CTRL_11 | (TMDS_CTRL_00 << 10) | (TMDS_CTRL_00 << 20))
+
+#define MODE_H_SYNC_POLARITY 0
+#define MODE_H_FRONT_PORCH   16
+#define MODE_H_SYNC_WIDTH    96
+#define MODE_H_BACK_PORCH    48
+#define MODE_H_ACTIVE_PIXELS 640
+
+#define MODE_V_SYNC_POLARITY 0
+#define MODE_V_FRONT_PORCH   10
+#define MODE_V_SYNC_WIDTH    2
+#define MODE_V_BACK_PORCH    33
+#define MODE_V_ACTIVE_LINES  480
+
+#define MODE_H_TOTAL_PIXELS ( \
+    MODE_H_FRONT_PORCH + MODE_H_SYNC_WIDTH + \
+    MODE_H_BACK_PORCH + MODE_H_ACTIVE_PIXELS \
+    )
+#define MODE_V_TOTAL_LINES  ( \
+    MODE_V_FRONT_PORCH + MODE_V_SYNC_WIDTH + \
+    MODE_V_BACK_PORCH + MODE_V_ACTIVE_LINES \
+    )
+
+#define HSTX_CMD_RAW         (0x0u << 12)
+#define HSTX_CMD_RAW_REPEAT  (0x1u << 12)
+#define HSTX_CMD_TMDS        (0x2u << 12)
+#define HSTX_CMD_TMDS_REPEAT (0x3u << 12)
+#define HSTX_CMD_NOP         (0xfu << 12)
+
+// ----------------------------------------------------------------------------
+// HSTX command lists
+
+static uint32_t vblank_line_vsync_off[] = {
+    HSTX_CMD_RAW_REPEAT | MODE_H_FRONT_PORCH,
+    SYNC_V1_H1,
+    HSTX_CMD_RAW_REPEAT | MODE_H_SYNC_WIDTH,
+    SYNC_V1_H0,
+    HSTX_CMD_RAW_REPEAT | (MODE_H_BACK_PORCH + MODE_H_ACTIVE_PIXELS),
+    SYNC_V1_H1
+};
+
+static uint32_t vblank_line_vsync_on[] = {
+    HSTX_CMD_RAW_REPEAT | MODE_H_FRONT_PORCH,
+    SYNC_V0_H1,
+    HSTX_CMD_RAW_REPEAT | MODE_H_SYNC_WIDTH,
+    SYNC_V0_H0,
+    HSTX_CMD_RAW_REPEAT | (MODE_H_BACK_PORCH + MODE_H_ACTIVE_PIXELS),
+    SYNC_V0_H1
+};
+
+static uint32_t vactive_line[] = {
+    HSTX_CMD_RAW_REPEAT | MODE_H_FRONT_PORCH,
+    SYNC_V1_H1,
+    HSTX_CMD_NOP,
+    HSTX_CMD_RAW_REPEAT | MODE_H_SYNC_WIDTH,
+    SYNC_V1_H0,
+    HSTX_CMD_NOP,
+    HSTX_CMD_RAW_REPEAT | MODE_H_BACK_PORCH,
+    SYNC_V1_H1,
+    HSTX_CMD_TMDS | MODE_H_ACTIVE_PIXELS
+};
+
+
+static bool vsync=true;
+
+static hdmi_framebuffer_obj_t *active_picodvi = NULL;
+
+static void __not_in_flash_func(dma_irq_handler)(void) {
+    uint ch_num = active_picodvi->dma_pixel_channel;
+    dma_channel_hw_t *ch = &dma_hw->ch[ch_num];
+    dma_hw->intr = 1u << ch_num;
+
+    // Set the read_addr back to the start and trigger the first transfer (which
+    // will trigger the pixel channel).
+    ch = &dma_hw->ch[active_picodvi->dma_command_channel];
+    ch->al3_read_addr_trig = (uintptr_t)active_picodvi->dma_commands;
+    vsync = (vsync==true)?false:true;
+}
+
+void hdmi_framebuffer(hdmi_framebuffer_obj_t *self, uint16_t width, uint16_t height, uint16_t color_depth) {
+    bool pixel_doubled = width == 320 && height == 240;
+
+    self->width = width;
+    self->height = height;
+    self->pitch = (self->width * color_depth) / 8;
+    self->color_depth = color_depth;
+    // Align each row to words.
+    if (self->pitch % sizeof(uint32_t) != 0) {
+        self->pitch += sizeof(uint32_t) - (self->pitch % sizeof(uint32_t));
+    }
+    self->pitch /= sizeof(uint32_t);
+    size_t framebuffer_size = self->pitch * self->height;
+
+    // We check that allocations aren't in PSRAM because we haven't added XIP
+    // streaming support.
+    if (self->framebuffer == NULL)
+        self->framebuffer = (uint32_t *)malloc(framebuffer_size * sizeof(uint32_t));
+    if (self->framebuffer == NULL || ((size_t)self->framebuffer & 0xf0000000) == 0x10000000) {
+        return;
+    }
+
+    // We compute all DMA transfers needed for a single frame. This ensure we don't have any super
+    // quick interrupts that we need to respond to. Each transfer takes two words, trans_count and
+    // read_addr. Active pixel lines need two transfers due to different read addresses. When pixel
+    // doubling, then we must also set transfer size.
+    size_t dma_command_size = 2;
+    if (pixel_doubled) {
+        dma_command_size = 4;
+    }
+    self->dma_commands_len = (MODE_V_FRONT_PORCH + MODE_V_SYNC_WIDTH + MODE_V_BACK_PORCH + 2 * MODE_V_ACTIVE_LINES + 1) * dma_command_size;
+    self->dma_commands = (uint32_t *)malloc(self->dma_commands_len * sizeof(uint32_t));
+    if (self->dma_commands == NULL || ((size_t)self->framebuffer & 0xf0000000) == 0x10000000) {
+        free(self->framebuffer);
+        return;
+    }
+
+    int dma_pixel_channel_maybe = VGA_DMA_CHANNEL; //dma_claim_unused_channel(false);
+    //if (dma_pixel_channel_maybe < 0) {
+    //    return;
+    //}
+
+    int dma_command_channel_maybe = VGA_DMA_CHANNEL+1; //dma_claim_unused_channel(false);
+    //if (dma_command_channel_maybe < 0) {
+    //    dma_channel_unclaim((uint)dma_pixel_channel_maybe);
+    //    return;
+    //}
+    self->dma_pixel_channel = dma_pixel_channel_maybe;
+    self->dma_command_channel = dma_command_channel_maybe;
+
+    size_t words_per_line;
+    if (self->color_depth > 8) {
+        words_per_line = (self->width * (self->color_depth / 8)) / sizeof(uint32_t);
+    } else {
+        words_per_line = (self->width / (8 / self->color_depth)) / sizeof(uint32_t);
+    }
+
+    size_t command_word = 0;
+    size_t frontporch_start = MODE_V_TOTAL_LINES - MODE_V_FRONT_PORCH;
+    size_t frontporch_end = frontporch_start + MODE_V_FRONT_PORCH;
+    size_t vsync_start = 0;
+    size_t vsync_end = vsync_start + MODE_V_SYNC_WIDTH;
+    size_t backporch_start = vsync_end;
+    size_t backporch_end = backporch_start + MODE_V_BACK_PORCH;
+    size_t active_start = backporch_end;
+
+    uint32_t dma_ctrl = self->dma_command_channel << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB |
+        DREQ_HSTX << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB |
+        DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS |
+        DMA_CH0_CTRL_TRIG_INCR_READ_BITS |
+        DMA_CH0_CTRL_TRIG_EN_BITS;
+    uint32_t dma_pixel_ctrl;
+    if (pixel_doubled) {
+        // We do color_depth size transfers when pixel doubling. The memory bus will
+        // duplicate the 16 bits to produce 32 bits for the HSTX.
+        if (color_depth == 16) {
+            dma_pixel_ctrl = dma_ctrl | DMA_SIZE_16 << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB;
+        } else {
+            dma_pixel_ctrl = dma_ctrl | DMA_SIZE_8 << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB;
+        }
+    } else {
+        dma_pixel_ctrl = dma_ctrl | DMA_SIZE_32 << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB;
+    }
+    if (self->color_depth == 16) {
+        dma_pixel_ctrl |= DMA_CH0_CTRL_TRIG_BSWAP_BITS;
+    }
+    dma_ctrl |= DMA_SIZE_32 << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB;
+
+    uint32_t dma_write_addr = (uint32_t)&hstx_fifo_hw->fifo;
+    // Write ctrl and write_addr once when not pixel doubling because they don't
+    // change. (write_addr doesn't change when pixel doubling either but we need
+    // to rewrite it because it is after the ctrl register.)
+    if (!pixel_doubled) {
+        dma_channel_hw_addr(self->dma_pixel_channel)->al1_ctrl = dma_ctrl;
+        dma_channel_hw_addr(self->dma_pixel_channel)->al1_write_addr = dma_write_addr;
+    }
+    for (size_t v_scanline = 0; v_scanline < MODE_V_TOTAL_LINES; v_scanline++) {
+        if (pixel_doubled) {
+            self->dma_commands[command_word++] = dma_ctrl;
+            self->dma_commands[command_word++] = dma_write_addr;
+        }
+        if (vsync_start <= v_scanline && v_scanline < vsync_end) {
+            self->dma_commands[command_word++] = count_of(vblank_line_vsync_on);
+            self->dma_commands[command_word++] = (uintptr_t)vblank_line_vsync_on;
+        } else if (backporch_start <= v_scanline && v_scanline < backporch_end) {
+            self->dma_commands[command_word++] = count_of(vblank_line_vsync_off);
+            self->dma_commands[command_word++] = (uintptr_t)vblank_line_vsync_off;
+        } else if (frontporch_start <= v_scanline && v_scanline < frontporch_end) {
+            self->dma_commands[command_word++] = count_of(vblank_line_vsync_off);
+            self->dma_commands[command_word++] = (uintptr_t)vblank_line_vsync_off;
+        } else {
+            self->dma_commands[command_word++] = count_of(vactive_line);
+            self->dma_commands[command_word++] = (uintptr_t)vactive_line;
+            size_t row = v_scanline - active_start;
+            size_t transfer_count = words_per_line;
+            if (pixel_doubled) {
+                self->dma_commands[command_word++] = dma_pixel_ctrl;
+                self->dma_commands[command_word++] = dma_write_addr;
+                row /= 2;
+                // When pixel doubling, we do one transfer per pixel and it gets
+                // mirrored into the rest of the word.
+                transfer_count = self->width;
+            }
+            self->dma_commands[command_word++] = transfer_count;
+            uint32_t *row_start = &self->framebuffer[row * self->pitch];
+            self->dma_commands[command_word++] = (uintptr_t)row_start;
+        }
+    }
+    // Last command is NULL which will trigger an IRQ.
+    if (pixel_doubled) {
+        self->dma_commands[command_word++] = DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS |
+            DMA_CH0_CTRL_TRIG_EN_BITS;
+        self->dma_commands[command_word++] = 0;
+    }
+    self->dma_commands[command_word++] = 0;
+    self->dma_commands[command_word++] = 0;
+
+    if (color_depth == 16) {
+        // Configure HSTX's TMDS encoder for RGB565
+        hstx_ctrl_hw->expand_tmds =
+            4 << HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB |
+                0 << HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB |
+                5 << HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB |
+                27 << HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB |
+                4 << HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB |
+                21 << HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB;
+    } else if (color_depth == 8) {
+        // Configure HSTX's TMDS encoder for RGB332
+        hstx_ctrl_hw->expand_tmds =
+            2 << HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB |
+                0 << HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB |
+                2 << HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB |
+                29 << HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB |
+                1 << HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB |
+                26 << HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB;
+    } else if (color_depth == 4) {
+        // Configure HSTX's TMDS encoder for RGBD
+        hstx_ctrl_hw->expand_tmds =
+            0 << HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB |
+                28 << HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB |
+                0 << HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB |
+                27 << HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB |
+                0 << HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB |
+                26 << HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB;
+    } else {
+        // Grayscale
+        uint8_t rot = 24 + color_depth;
+        hstx_ctrl_hw->expand_tmds =
+            (color_depth - 1) << HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB |
+                rot << HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB |
+                    (color_depth - 1) << HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB |
+                rot << HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB |
+                    (color_depth - 1) << HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB |
+                rot << HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB;
+    }
+    size_t shifts_before_empty = ((32 / color_depth) % 32);
+    if (pixel_doubled && color_depth == 8) {
+        // All but 320x240 at 8bits will shift through all 32 bits. We are only
+        // doubling so we only need 16 bits (2 x 8) to get our doubled pixel.
+        shifts_before_empty = 2;
+    }
+
+    // Pixels come in 32 bits at a time. color_depth dictates the number
+    // of pixels per word. Control symbols (RAW) are an entire 32-bit word.
+    hstx_ctrl_hw->expand_shift =
+        shifts_before_empty << HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB |
+            color_depth << HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB |
+            1 << HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB |
+            0 << HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB;
+
+    // Serial output config: clock period of 5 cycles, pop from command
+    // expander every 5 cycles, shift the output shiftreg by 2 every cycle.
+    hstx_ctrl_hw->csr = 0;
+    hstx_ctrl_hw->csr =
+        HSTX_CTRL_CSR_EXPAND_EN_BITS |
+        5u << HSTX_CTRL_CSR_CLKDIV_LSB |
+            5u << HSTX_CTRL_CSR_N_SHIFTS_LSB |
+            2u << HSTX_CTRL_CSR_SHIFT_LSB |
+            HSTX_CTRL_CSR_EN_BITS;
+
+    // Note we are leaving the HSTX clock at the SDK default of 125 MHz; since
+    // we shift out two bits per HSTX clock cycle, this gives us an output of
+    // 250 Mbps, which is very close to the bit clock for 480p 60Hz (252 MHz).
+    // If we want the exact rate then we'll have to reconfigure PLLs.
+
+
+    // Assign clock pair to two neighbouring pins:
+    hstx_ctrl_hw->bit[2] = HSTX_CTRL_BIT0_CLK_BITS;
+    hstx_ctrl_hw->bit[3] = HSTX_CTRL_BIT0_CLK_BITS | HSTX_CTRL_BIT0_INV_BITS;
+    for (uint lane = 0; lane < 3; ++lane) {
+      // For each TMDS lane, assign it to the correct GPIO pair based on the
+      // desired pinout:
+      static const int lane_to_output_bit[3] = {0, 6, 4};
+      int bit = lane_to_output_bit[lane];
+      // Output even bits during first half of each HSTX cycle, and odd bits
+      // during second half. The shifter advances by two bits each cycle.
+      uint32_t lane_data_sel_bits =
+          (lane * 10    ) << HSTX_CTRL_BIT0_SEL_P_LSB |
+          (lane * 10 + 1) << HSTX_CTRL_BIT0_SEL_N_LSB;
+      // The two halves of each pair get identical data, but one pin is inverted.
+      hstx_ctrl_hw->bit[bit    ] = lane_data_sel_bits;
+      hstx_ctrl_hw->bit[bit + 1] = lane_data_sel_bits | HSTX_CTRL_BIT0_INV_BITS;
+    }
+
+    for (int i = 12; i <= 19; ++i) {
+      gpio_set_function(i, (gpio_function_t)0); // HSTX
+    }
+
+
+    dma_channel_config c;
+    c = dma_channel_get_default_config(self->dma_command_channel);
+    channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
+    channel_config_set_read_increment(&c, true);
+    channel_config_set_write_increment(&c, true);
+    // This wraps the transfer back to the start of the write address.
+    size_t wrap = 3; // 8 bytes because we write two DMA registers.
+    volatile uint32_t *write_addr = &dma_hw->ch[self->dma_pixel_channel].al3_transfer_count;
+    if (pixel_doubled) {
+        wrap = 4; // 16 bytes because we write all four DMA registers.
+        write_addr = &dma_hw->ch[self->dma_pixel_channel].al3_ctrl;
+    }
+    channel_config_set_ring(&c, true, wrap);
+    // No chain because we use an interrupt to reload this channel instead of a
+    // third channel.
+    dma_channel_configure(
+        self->dma_command_channel,
+        &c,
+        write_addr,
+        self->dma_commands,
+        (1 << wrap) / sizeof(uint32_t),
+        false
+        );
+
+    dma_hw->ints0 = (1u << self->dma_pixel_channel);
+    dma_hw->inte0 = (1u << self->dma_pixel_channel);
+    irq_set_exclusive_handler(DMA_IRQ_0, dma_irq_handler);
+    irq_set_priority (DMA_IRQ_0, 0);    
+    irq_set_enabled(DMA_IRQ_0, true);
+
+    bus_ctrl_hw->priority = BUSCTRL_BUS_PRIORITY_DMA_W_BITS | BUSCTRL_BUS_PRIORITY_DMA_R_BITS;
+
+    // For the output.
+    self->framebuffer_len = framebuffer_size;
+
+    active_picodvi = self;
+
+    //common_hal_picodvi_framebuffer_refresh(self);
+    dma_irq_handler();
+}
+
+void hdmi_framebuffer_vsync(void) {
+    volatile bool vb=vsync; 
+    while (vsync==vb) {
+        __dmb();
+    };
+}
+
+
diff --git a/MCUME_pico2/display/hdmi_framebuffer.h b/MCUME_pico2/display/hdmi_framebuffer.h
new file mode 100755
index 0000000..b3f319c
--- /dev/null
+++ b/MCUME_pico2/display/hdmi_framebuffer.h
@@ -0,0 +1,25 @@
+#ifndef HDMIFRAMEBUFFER_H
+#define HDMIFRAMEBUFFER_H
+
+#include "stdint.h"
+#include <stdio.h>
+
+typedef struct {
+    uint32_t *framebuffer;
+    size_t framebuffer_len; // in words
+    uint32_t *dma_commands;
+    size_t dma_commands_len; // in words
+    uint16_t width;
+    uint16_t height;
+    uint16_t pitch; // Number of words between rows. (May be more than a width's worth.)
+    uint8_t color_depth;
+    uint8_t dma_pixel_channel;
+    uint8_t dma_command_channel;
+} hdmi_framebuffer_obj_t;
+
+extern void hdmi_framebuffer(hdmi_framebuffer_obj_t *self,
+    uint16_t width, uint16_t height,
+    uint16_t color_depth);
+extern void hdmi_framebuffer_vsync(void);
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/display/include.h b/MCUME_pico2/display/include.h
new file mode 100755
index 0000000..1e4b767
--- /dev/null
+++ b/MCUME_pico2/display/include.h
@@ -0,0 +1,132 @@
+
+// ****************************************************************************
+//                                 
+//                           Global common definitions
+//
+// file derived from the PicoVGA project
+// https://github.com/Panda381/PicoVGA
+// by Miroslav Nemecek
+//
+// ****************************************************************************
+
+// ----------------------------------------------------------------------------
+//                              Base data types
+// ----------------------------------------------------------------------------
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed long int s32;
+typedef unsigned long int u32;
+typedef signed long long int s64;
+typedef unsigned long long int u64;
+
+typedef unsigned int uint;
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+// NULL
+#ifndef NULL
+#ifdef __cplusplus
+#define NULL 0
+#else
+#define NULL ((void*)0)
+#endif
+#endif
+
+
+#define	B0 (1<<0)
+#define	B1 (1<<1)
+#define	B2 (1<<2)
+#define	B3 (1<<3)
+#define	B4 (1<<4)
+#define	B5 (1<<5)
+#define	B6 (1<<6)
+#define	B7 (1<<7)
+#define	B8 (1U<<8)
+#define	B9 (1U<<9)
+#define	B10 (1U<<10)
+#define	B11 (1U<<11)
+#define	B12 (1U<<12)
+#define	B13 (1U<<13)
+#define	B14 (1U<<14)
+#define	B15 (1U<<15)
+#define B16 (1UL<<16)
+#define B17 (1UL<<17)
+#define B18 (1UL<<18)
+#define	B19 (1UL<<19)
+#define B20 (1UL<<20)
+#define B21 (1UL<<21)
+#define B22 (1UL<<22)
+#define B23 (1UL<<23)
+#define B24 (1UL<<24)
+#define B25 (1UL<<25)
+#define B26 (1UL<<26)
+#define B27 (1UL<<27)
+#define B28 (1UL<<28)
+#define B29 (1UL<<29)
+#define B30 (1UL<<30)
+#define B31 (1UL<<31)
+
+// I/O port prefix
+#define __IO	volatile
+
+// request to use inline
+#define INLINE __attribute__((always_inline)) inline
+
+// avoid to use inline
+#define NOINLINE __attribute__((noinline))
+
+// weak function
+#define WEAK __attribute__((weak))
+
+// align array to 4-bytes
+#define ALIGNED __attribute__((aligned(4)))
+#define ALIGN4(x) ((x) & ~3)
+
+// swap bytes of command
+#define BYTESWAP(n) ((((n)&0xff)<<24)|(((n)&0xff00)<<8)|(((n)&0xff0000)>>8)|(((n)&0xff000000)>>24))
+
+// place time critical function into RAM
+#define NOFLASH(fnc) NOINLINE __attribute__((section(".time_critical." #fnc))) fnc
+
+// fast function optimization
+#define FASTCODE __attribute__ ((optimize("-Ofast")))
+
+
+#define BIT(pos) (1UL<<(pos))
+
+#define	BIGINT	0x40000000 // big int value
+
+#define _T(a) a
+
+#define PI 3.14159265358979324
+#define PI2 (3.14159265358979324*2)
+
+
+// system includes
+#include <string.h>
+
+// SDK includes
+#include "pico.h"
+#include "pico/stdlib.h"
+#include "pico/multicore.h"
+#include "pico/sync.h"
+#include "pico/platform.h"
+#include "pico/sem.h"
+#include "hardware/clocks.h"
+#include "hardware/dma.h"
+#include "hardware/gpio.h"
+#include "hardware/pio.h"
+#include "hardware/irq.h"
+#include "hardware/divider.h"
+#include "hardware/structs/bus_ctrl.h"
+#include "pico/binary_info.h"
+#include "pico/printf.h"
+#include "pico/float.h"
+//#include "pico/int64_ops.h"
+
+
diff --git a/MCUME_pico2/display/pico_dsp.cpp b/MCUME_pico2/display/pico_dsp.cpp
new file mode 100755
index 0000000..67eb07a
--- /dev/null
+++ b/MCUME_pico2/display/pico_dsp.cpp
@@ -0,0 +1,1488 @@
+/*
+	This file is part of DISPLAY library. 
+  Supports VGA and TFT display
+
+	DISPLAY library is free software: you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 3 of the License, or
+	(at your option) any later version.
+
+	Copyright (C) 2020 J-M Harvengt
+*/
+
+#include "pico/stdlib.h"
+#include "pico/multicore.h"
+#include "hardware/spi.h"
+#include "hardware/dma.h"
+#include "hardware/irq.h"
+#include <string.h>
+
+#include "PICO_DSP.h"
+#include "font8x8.h"
+#include "include.h"
+
+#include "hdmi_framebuffer.h"
+
+static hdmi_framebuffer_obj_t hdmi_obj;
+static gfx_mode_t gfxmode = MODE_UNDEFINED;
+
+/* TFT structures / constants */
+#define digitalWrite(pin, val) gpio_put(pin, val)
+#define SPICLOCK 60000000 
+#ifdef USE_VGA
+#define SPI_MODE SPI_CPOL_1
+#else
+#ifdef ST7789
+#ifdef ST7789_POL
+#define SPI_MODE SPI_CPOL_0
+#else
+#define SPI_MODE SPI_CPOL_1
+#endif
+#endif
+#ifdef ILI9341
+#define SPI_MODE SPI_CPOL_0
+#endif
+#endif
+
+#define LINES_PER_BLOCK  64
+#define NR_OF_BLOCK      4
+
+#define TFT_SWRESET    0x01
+#define TFT_SLPOUT     0x11
+#define TFT_INVON      0x21
+#define TFT_DISPOFF    0x28
+#define TFT_DISPON     0x29
+#define TFT_CASET      0x2A
+#define TFT_PASET      0x2B
+#define TFT_RAMWR      0x2C
+#define TFT_MADCTL     0x36
+#define TFT_PIXFMT     0x3A
+#define TFT_MADCTL_MY  0x80
+#define TFT_MADCTL_MX  0x40
+#define TFT_MADCTL_MV  0x20
+#define TFT_MADCTL_ML  0x10
+#define TFT_MADCTL_RGB 0x00
+#define TFT_MADCTL_BGR 0x08
+#define TFT_MADCTL_MH  0x04
+
+static void SPItransfer(uint8_t val)
+{
+  uint8_t dat8=val;
+  spi_write_blocking(TFT_SPIREG, &dat8, 1);
+}
+
+static void SPItransfer16(uint16_t val)
+{
+  uint8_t dat8[2];
+  dat8[0] = val>>8;
+  dat8[1] = val&0xff;
+  spi_write_blocking(TFT_SPIREG, dat8, 2);
+}
+
+#define DELAY_MASK     0x80
+static const uint8_t init_commands[] = { 
+  1+DELAY_MASK, TFT_SWRESET,  150,
+  1+DELAY_MASK, TFT_SLPOUT,   255,
+  2+DELAY_MASK, TFT_PIXFMT, 0x55, 10,
+  2,            TFT_MADCTL, TFT_MADCTL_MV | TFT_MADCTL_BGR,
+  1, TFT_INVON,
+  1, TFT_DISPON,
+  0
+};
+
+/* TFT structures / constants */
+#define RGBVAL16(r,g,b)  ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) )
+
+static uint16_t * blocks[NR_OF_BLOCK];
+static uint16_t blocklens[NR_OF_BLOCK];
+static dma_channel_config dmaconfig;
+static uint dma_tx=0;
+static volatile uint8_t rstop = 0;
+static volatile bool cancelled = false;
+static volatile uint8_t curTransfer = 0;
+static uint8_t nbTransfer = 0;
+
+/* VGA structures / constants */
+#define R16(rgb) ((rgb>>8)&0xf8) 
+#define G16(rgb) ((rgb>>3)&0xfc) 
+#define B16(rgb) ((rgb<<3)&0xf8) 
+#ifdef VGA222
+#define VGA_RGB(r,g,b)   ( (((r>>6)&0x03)<<4) | (((g>>6)&0x03)<<2) | (((b>>6)&0x3)<<0) )
+#else
+#define VGA_RGB(r,g,b)   ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) )
+#endif
+
+// 8 bits 320x240 frame buffer => 64K
+static vga_pixel * visible_framebuffer = NULL;
+static vga_pixel * framebuffer = NULL;
+static vga_pixel * fb0 = NULL;
+static vga_pixel * fb1 = NULL;
+
+static int  fb_width;
+static int  fb_height;
+static int  fb_stride;
+
+static int doorbell_id;
+
+
+void PICO_DSP::setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) {
+  int dx=0;
+  int dy=0;
+#ifdef ST7789
+  if (TFT_REALWIDTH == TFT_REALHEIGHT)
+  {
+#ifdef ROTATE_SCREEN
+    if (!flipped) {
+      dy += 80;    
+    }
+#else  
+    if (flipped) {
+      dx += 80;    
+    }
+#endif      
+  }
+#endif  
+
+  digitalWrite(_dc, 0);
+  SPItransfer(TFT_CASET);
+  digitalWrite(_dc, 1);
+  SPItransfer16(x1+dx);
+  digitalWrite(_dc, 1);
+  SPItransfer16(x2+dx);  
+  digitalWrite(_dc, 0);
+  SPItransfer(TFT_PASET);
+  digitalWrite(_dc, 1);
+  SPItransfer16(y1+dy);
+  digitalWrite(_dc, 1);
+  SPItransfer16(y2+dy);  
+
+  digitalWrite(_dc, 0);
+  SPItransfer(TFT_RAMWR);
+  digitalWrite(_dc, 1);
+ 
+  return; 
+}
+
+
+PICO_DSP::PICO_DSP()
+{
+}
+
+
+static void (* volatile Core1Fnc)() = NULL; // core 1 remote function
+
+static void VgaCore(void)
+{
+
+
+  void (*fnc)();
+  while (1)
+  {
+    __dmb();
+#ifdef HAS_SND
+//    handle_fill_samples();
+#endif
+    // execute remote function
+    fnc = Core1Fnc;
+    if (fnc != NULL)
+    {
+      fnc();
+      __dmb();
+      Core1Fnc = NULL;
+    }   
+  }
+}
+
+
+gfx_error_t PICO_DSP::begin(gfx_mode_t mode)
+{
+  // Reset SPI if we come from TFT mode
+  if ( (mode != MODE_TFT_320x240) && (gfxmode == MODE_TFT_320x240) ) {
+    fillScreenNoDma(RGBVAL16(0x0,0x00,0x00));
+    digitalWrite(_cs, 0);
+    digitalWrite(_dc, 0);
+    SPItransfer(TFT_DISPOFF);
+    digitalWrite(_cs, 1);
+    sleep_ms(20);
+    digitalWrite(_cs, 0);
+    digitalWrite(_cs, 1);
+    if (_bkl != 0xff) {
+      digitalWrite(_bkl, 0);
+    }
+    //spi_init(TFT_SPIREG, 0);
+    //spi_deinit(TFT_SPIREG);
+    //spi_set_slave(TFT_SPIREG, true);
+  }  
+  switch(mode) {
+    case MODE_VGA_320x240:
+      gfxmode = mode;
+      fb_width = 320;
+      fb_height = 240;
+      fb_stride = 320;
+      hdmi_obj.framebuffer = NULL;
+      hdmi_framebuffer(&hdmi_obj, fb_width, fb_height, 8);
+      fb0 = (uint8_t *)hdmi_obj.framebuffer;
+      visible_framebuffer = fb0;
+      framebuffer = fb0;
+      break;
+
+    case MODE_VGA_256x240:
+      gfxmode = mode;
+      fb_width = 256;
+      fb_height = 240;
+      fb_stride = 320;
+      hdmi_obj.framebuffer = NULL;
+      hdmi_framebuffer(&hdmi_obj, fb_width, fb_height, 8);
+      fb0 = (uint8_t *)hdmi_obj.framebuffer;
+      visible_framebuffer = fb0;
+      framebuffer = fb0;
+      break;
+
+    case MODE_VGA_640x240:
+      gfxmode = mode;
+      fb_width = 640;
+      fb_height = 240;
+      fb_stride = 640;
+      hdmi_obj.framebuffer = NULL;
+      hdmi_framebuffer(&hdmi_obj, fb_width, fb_height, 8);
+      fb0 = (uint8_t *)hdmi_obj.framebuffer;
+      visible_framebuffer = fb0;
+      framebuffer = fb0;
+      break;
+
+    case MODE_TFT_320x240:
+      gfxmode = mode;
+      fb_width = TFT_WIDTH;
+      fb_height = TFT_HEIGHT;      
+      fb_stride = fb_width;    
+      _cs   = TFT_CS;
+      _dc   = TFT_DC;
+      _rst  = TFT_RST;
+      _mosi = TFT_MOSI;
+      _sclk = TFT_SCLK;
+      _bkl = TFT_BACKLIGHT;
+      gpio_init(_dc);
+      gpio_set_dir(_dc, GPIO_OUT); 
+      gpio_init(_cs);
+      gpio_set_dir(_cs, GPIO_OUT);
+      digitalWrite(_cs, 1);
+      digitalWrite(_dc, 1);
+      if (_bkl != 0xff) {
+        gpio_init(_bkl);
+        gpio_set_dir(_bkl, GPIO_OUT); 
+        digitalWrite(_bkl, 1);
+      } 
+
+      spi_init(TFT_SPIREG, SPICLOCK);
+      spi_set_format(TFT_SPIREG, 8, SPI_MODE, SPI_CPHA_0, SPI_MSB_FIRST);
+      gpio_set_function(_sclk , GPIO_FUNC_SPI);
+      gpio_set_function(_mosi , GPIO_FUNC_SPI);
+         
+      // Initialize display
+      if (_rst != 0xff) {
+        gpio_init(_rst);
+        gpio_set_dir(_rst, GPIO_OUT);     
+        digitalWrite(_rst, 1);
+        sleep_ms(100);
+        digitalWrite(_rst, 0);
+        sleep_ms(100);
+        digitalWrite(_rst, 1);
+        sleep_ms(200);
+      }
+      const uint8_t *addr = init_commands;
+      uint8_t count;
+      digitalWrite(_cs, 0);
+      while (count = *addr++) {
+        uint8_t command = *addr++;
+#ifdef ILI9341
+        if ( command == TFT_INVON ) {
+          // Skip TFT_INVON for ILI
+        }
+        else 
+#endif
+        {
+          digitalWrite(_dc, 0); // command
+          SPItransfer(command);
+          uint16_t ms = count & DELAY_MASK;
+          count &= ~DELAY_MASK;
+          while (--count > 0) { // data
+            uint8_t data = *addr++;
+#ifdef ILI9341
+#else
+            if ( command == TFT_MADCTL ) {
+              data = TFT_MADCTL_MX | TFT_MADCTL_MV |TFT_MADCTL_RGB;
+            }
+#endif
+            digitalWrite(_dc, 1);
+            SPItransfer(data);
+          }
+          if (ms) {
+            ms = *addr++; // Read post-command delay time (ms)
+            if(ms == 255) ms = 500;   // If 255, delay for 500 ms
+            digitalWrite(_cs, 1);
+            //SPI.endTransaction();
+            sleep_ms(ms);
+            //SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE));
+            digitalWrite(_cs, 0);      
+          }     
+        }
+      }
+      digitalWrite(_cs, 1);
+      break;
+  }	
+
+
+  return(GFX_OK);
+}
+
+void PICO_DSP::end()
+{
+}
+
+gfx_mode_t PICO_DSP::getMode(void)
+{
+  return gfxmode;
+}
+
+void PICO_DSP::flipscreen(bool flip)
+{
+  digitalWrite(_dc, 0);
+  digitalWrite(_cs, 0);
+  SPItransfer(TFT_MADCTL);
+  digitalWrite(_dc, 1);
+  if (flip) {
+    flipped=true;
+
+#ifdef ILI9341         
+    SPItransfer(TFT_MADCTL_MV | TFT_MADCTL_BGR);
+#endif
+#ifdef ST7789
+#ifdef ROTATE_SCREEN
+    SPItransfer(TFT_MADCTL_RGB);
+#else
+    SPItransfer(TFT_MADCTL_MY | TFT_MADCTL_MV |TFT_MADCTL_RGB);
+#endif
+#endif 
+  }
+  else {
+    flipped=false;
+   
+#ifdef ILI9341        
+    SPItransfer(TFT_MADCTL_MX | TFT_MADCTL_MY | TFT_MADCTL_MV | TFT_MADCTL_BGR);
+#endif
+#ifdef ST7789
+#ifdef ROTATE_SCREEN
+    SPItransfer(TFT_MADCTL_MX | TFT_MADCTL_MY | TFT_MADCTL_RGB);
+#else
+    SPItransfer(TFT_MADCTL_MX | TFT_MADCTL_MV | TFT_MADCTL_RGB);
+#endif
+#endif  
+  }
+  digitalWrite(_cs, 1);   
+}
+
+
+bool PICO_DSP::isflipped(void)
+{
+  return(flipped);
+}
+  
+
+/***********************************************************************************************
+    DMA functions
+ ***********************************************************************************************/
+static void dma_isr() { 
+  irq_clear(DMA_IRQ_0);
+  dma_hw->ints0 = 1u << dma_tx;
+  curTransfer++;
+  if (curTransfer >= nbTransfer) {
+    curTransfer = 0;
+  }
+  if (cancelled) {
+    rstop = 1;
+  }
+  else 
+  {
+    dma_channel_transfer_from_buffer_now(dma_tx, blocks[curTransfer], blocklens[curTransfer]);
+  }  
+}
+
+static void setDmaStruct() {
+  // Setup the control channel
+  if (dma_tx == 0)  {
+    dma_tx = dma_claim_unused_channel(true);
+  }    
+  dmaconfig = dma_channel_get_default_config(dma_tx);
+  channel_config_set_transfer_data_size(&dmaconfig, DMA_SIZE_16);
+  channel_config_set_dreq(&dmaconfig, TFT_SPIDREQ);  
+  //channel_config_set_read_increment(&dmaconfig, true); // read incrementing
+  //channel_config_set_write_increment(&dmaconfig, false); // no write incrementing
+
+  dma_channel_configure(
+      dma_tx,
+      &dmaconfig,
+      &spi_get_hw(TFT_SPIREG)->dr, // write address
+      blocks[0],
+      blocklens[0],
+      false
+  ); 
+
+  irq_set_exclusive_handler(DMA_IRQ_0, dma_isr);
+  dma_channel_set_irq0_enabled(dma_tx, true);
+  irq_set_enabled(DMA_IRQ_0, true);
+  dma_hw->ints0 = 1u << dma_tx;  
+}
+
+void PICO_DSP::startRefresh(void) {
+  if (gfxmode == MODE_TFT_320x240) {
+    uint32_t remaining = TFT_HEIGHT*TFT_WIDTH*2;
+    int i=0;
+    nbTransfer = 0;
+    while (remaining > 0) {
+      uint16_t * fb = blocks[i];
+      int32_t len = (remaining >= (LINES_PER_BLOCK*TFT_WIDTH*2)?LINES_PER_BLOCK*TFT_WIDTH*2:remaining);     
+      switch (i) {
+        case 0:
+          if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0);       
+          break;
+        case 1:
+          if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0);      
+          break;
+        case 2:
+          if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0);      
+          break;
+        case 3:
+          if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0);       
+          break;
+      }
+      blocks[i] = fb;
+      blocklens[i] = len/2;
+      if (blocks[i] == 0) {
+        fillScreenNoDma(RGBVAL16(0xFF,0xFF,0x00));
+        printf("FB allocaltion failed for block %d\n",i);
+        sleep_ms(10000);    
+      }
+      nbTransfer++;
+      remaining -= len;    
+      i++;
+    }                
+    curTransfer = 0;  
+    rstop = 0;     
+    digitalWrite(_cs, 1);
+    setDmaStruct();
+    fillScreen(RGBVAL16(0x00,0x00,0x00));
+    digitalWrite(_cs, 0);
+
+    setArea((TFT_REALWIDTH-TFT_WIDTH)/2, (TFT_REALHEIGHT-TFT_HEIGHT)/2, (TFT_REALWIDTH-TFT_WIDTH)/2 + TFT_WIDTH-1, (TFT_REALHEIGHT-TFT_HEIGHT)/2+TFT_HEIGHT-1);  
+    // we switch to 16bit mode!!
+    spi_set_format(TFT_SPIREG, 16, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+    dma_start_channel_mask(1u << dma_tx);    
+  }
+  else { 
+    fillScreen(RGBVAL16(0x00,0x00,0x00));   
+  }
+}
+
+void PICO_DSP::stopRefresh(void) {
+  if (gfxmode == MODE_TFT_320x240) {
+    rstop = 1;
+    unsigned long m = time_us_32()*1000;   
+    cancelled = true; 
+    while (!rstop)  {
+      if ((time_us_32()*1000 - m) > 100) break;
+      sleep_ms(100);
+      asm volatile("wfi");
+    };
+    rstop = 0;
+    sleep_ms(100);
+    cancelled = false;  
+    //dmatx.detachInterrupt();
+    fillScreen(RGBVAL16(0x00,0x00,0x00));
+    digitalWrite(_cs, 1);
+    // we switch back to GFX mode!!
+    begin(gfxmode);
+    setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1);    
+  }
+}
+
+
+/***********************************************************************************************
+    GFX functions
+ ***********************************************************************************************/
+// retrieve size of the frame buffer
+int PICO_DSP::get_frame_buffer_size(int *width, int *height)
+{
+  if (width != nullptr) *width = fb_width;
+  if (height != nullptr) *height = fb_height;
+  return fb_stride;
+}
+
+void PICO_DSP::waitSync()
+{
+  if (gfxmode == MODE_TFT_320x240) {
+  }
+  else { 
+    hdmi_framebuffer_vsync();
+    //HdmiVSync();
+  }
+}
+
+void PICO_DSP::waitLine(int line)
+{
+  if (gfxmode == MODE_TFT_320x240) {
+  }
+  else { 
+//  while (currentLine != line) {};
+  }
+}
+
+
+/***********************************************************************************************
+    GFX functions
+ ***********************************************************************************************/
+
+dsp_pixel * PICO_DSP::getLineBuffer(int j) {
+  return ((dsp_pixel *)&framebuffer[j*fb_stride]);
+}
+
+void PICO_DSP::fillScreen(dsp_pixel color) {
+  int i,j;
+  if (gfxmode == MODE_TFT_320x240) {
+    for (j=0; j<TFT_HEIGHT; j++)
+    {
+      uint16_t * block=blocks[j>>6];
+      uint16_t * dst=&block[(j&0x3F)*fb_stride];
+      for (i=0; i<fb_width; i++)
+      {
+        *dst++ = color;
+      }
+    }
+  }
+  else {
+    vga_pixel color8 = VGA_RGB(R16(color),G16(color),B16(color));
+    for (j=0; j<fb_height; j++)
+    {
+      vga_pixel * dst=&framebuffer[j*fb_stride];
+      for (i=0; i<fb_width; i++)
+      {
+        *dst++ = color8;
+      }
+    }    
+  }  
+}
+
+void PICO_DSP::drawRect(int16_t x, int16_t y, int16_t w, int16_t h, dsp_pixel color) {
+  int i,j,l=y;
+  if (gfxmode == MODE_TFT_320x240) {
+    for (j=0; j<h; j++)
+    {
+      uint16_t * block=blocks[l>>6];
+      uint16_t * dst=&block[(l&0x3F)*fb_stride+x];
+      for (i=0; i<w; i++)
+      {
+        *dst++ = color;
+      }
+      l++;
+    }
+  }
+  else {
+    vga_pixel color8 = VGA_RGB(R16(color),G16(color),B16(color));
+    for (j=0; j<h; j++)
+    {
+      vga_pixel * dst=&framebuffer[l*fb_stride+x];
+      for (i=0; i<w; i++)
+      {
+        *dst++ = color8;
+      }
+      l++;
+    }
+  }  
+}
+
+void PICO_DSP::drawText(int16_t x, int16_t y, const char * text, dsp_pixel fgcolor, dsp_pixel bgcolor, bool doublesize) {
+  if (gfxmode == MODE_TFT_320x240) {
+    uint16_t c;
+    uint16_t * block;
+    uint16_t * dst;
+    fgcolor = fgcolor;
+    bgcolor = bgcolor;
+    while ((c = *text++)) {
+      const unsigned char * charpt=&font8x8[c][0];
+      int l=y;
+      for (int i=0;i<8;i++)
+      {     
+        unsigned char bits;
+        if (doublesize) {
+          block=blocks[l>>6];
+          dst=&block[(l&0x3F)*fb_stride+x];         
+          bits = *charpt;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor;
+          else *dst++=bgcolor;
+          l++;       
+        }
+        block=blocks[l>>6];
+        dst=&block[(l&0x3F)*fb_stride+x]; 
+        bits = *charpt++;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor;
+        else *dst++=bgcolor;
+        l++;
+      }
+      x +=8;
+    }  
+  }
+  else {
+    vga_pixel fgcolor8 = VGA_RGB(R16(fgcolor),G16(fgcolor),B16(fgcolor));
+    vga_pixel bgcolor8 = VGA_RGB(R16(bgcolor),G16(bgcolor),B16(bgcolor));
+    vga_pixel c;
+    vga_pixel * dst;
+    while ((c = *text++)) {
+      const unsigned char * charpt=&font8x8[c][0];
+      int l=y;
+      for (int i=0;i<8;i++)
+      {     
+        unsigned char bits;
+        if (doublesize) {
+          dst=&framebuffer[l*fb_stride+x];
+          bits = *charpt;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          bits = bits >> 1;     
+          if (bits&0x01) *dst++=fgcolor8;
+          else *dst++=bgcolor8;
+          l++;
+        }
+        dst=&framebuffer[l*fb_stride+x]; 
+        bits = *charpt++;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        bits = bits >> 1;     
+        if (bits&0x01) *dst++=fgcolor8;
+        else *dst++=bgcolor8;
+        l++;
+      }
+      x +=8;
+    }
+  }  
+}
+
+void PICO_DSP::drawSprite(int16_t x, int16_t y, const dsp_pixel *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh)
+{
+  int bmp_offx = 0;
+  int bmp_offy = 0;
+  uint16_t *bmp_ptr;
+  int w =*bitmap++;
+  int h = *bitmap++;
+  if ( (arw == 0) || (arh == 0) ) {
+    // no crop window
+    arx = x;
+    ary = y;
+    arw = w;
+    arh = h;
+  }
+  else {
+    if ( (x>(arx+arw)) || ((x+w)<arx) || (y>(ary+arh)) || ((y+h)<ary)   ) {
+      return;
+    }
+    // crop area
+    if ( (x > arx) && (x<(arx+arw)) ) { 
+      arw = arw - (x-arx);
+      arx = arx + (x-arx);
+    } else {
+      bmp_offx = arx;
+    }
+    if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) {
+      arw -= (arx+arw-x-w);
+    }  
+    if ( (y > ary) && (y<(ary+arh)) ) {
+      arh = arh - (y-ary);
+      ary = ary + (y-ary);
+    } else {
+      bmp_offy = ary;
+    }
+    if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) {
+      arh -= (ary+arh-y-h);
+    }     
+  }
+  int l=ary;
+  bitmap = bitmap + bmp_offy*w + bmp_offx;
+
+
+  if (gfxmode == MODE_TFT_320x240) {
+    for (int row=0;row<arh; row++)
+    {
+      uint16_t * block=blocks[l>>6];
+      uint16_t * dst=&block[(l&0x3F)*fb_stride+arx];  
+      bmp_ptr = (uint16_t*)bitmap;
+      for (int col=0;col<arw; col++)
+      {
+          *dst++ = *bmp_ptr++;            
+      } 
+      bitmap += w;
+      l++;
+    } 
+  }
+  else {
+    for (int row=0;row<arh; row++)
+    {
+      vga_pixel * dst=&framebuffer[l*fb_stride+arx];  
+      bmp_ptr = (uint16_t *)bitmap;
+      for (int col=0;col<arw; col++)
+      {
+          uint16_t pix= *bmp_ptr++;
+          *dst++ = VGA_RGB(R16(pix),G16(pix),B16(pix));
+      } 
+      bitmap += w;
+      l++;
+    }     
+  }  
+
+}
+
+void PICO_DSP::drawSprite(int16_t x, int16_t y, const dsp_pixel *bitmap) {
+    drawSprite(x,y,bitmap, 0,0,0,0);
+}
+
+void PICO_DSP::writeLine(int width, int height, int y, dsp_pixel *buf) {
+  if (gfxmode == MODE_TFT_320x240) {
+    uint16_t * block=blocks[y>>6];
+    uint16_t * dst=&block[(y&0x3F)*fb_stride];
+    if (width > fb_width) {
+#ifdef TFT_LINEARINT   
+      int delta = (width/(width-fb_width))-1;   
+      int pos = delta;
+      for (int i=0; i<fb_width; i++)
+      {
+        uint16_t val = *buf++;
+        pos--;      
+        if (pos == 0) {
+#ifdef LINEARINT_HACK        
+          val  = ((uint32_t)*buf++ + val)/2;
+#else
+          uint16_t val2 = *buf++;
+          val = RGBVAL16((R16(val)+R16(val2))/2,(G16(val)+G16(val2))/2,(B16(val)+B16(val2))/2);
+ #endif        
+          pos = delta;
+        }
+        *dst++=val;
+      }
+  #else
+      int step = ((width << 8)/fb_width);
+      int pos = 0;
+      for (int i=0; i<fb_width; i++)
+      {
+        *dst++=buf[pos >> 8];
+        pos +=step;
+      }  
+  #endif       
+    }
+    else if ((width*2) == fb_width) 
+    {
+      for (int i=0; i<width; i++)
+      {
+        *dst++=*buf;
+        *dst++=*buf++;
+      }       
+    }
+    else
+    {
+      if (width <= fb_width) {
+        dst += (fb_width-width)/2;
+      }
+      for (int i=0; i<width; i++)
+      {
+        *dst++=*buf++;
+      }       
+    }    
+  }
+  else {
+    if ( (height<fb_height) && (height > 2) ) y += (fb_height-height)/2;
+    vga_pixel * dst=&framebuffer[y*fb_stride];    
+    if (width > fb_width) {
+      int step = ((width << 8)/fb_width);
+      int pos = 0;
+      for (int i=0; i<fb_width; i++)
+      {
+        uint16_t pix = buf[pos >> 8];
+        *dst++ = VGA_RGB(R16(pix),G16(pix),B16(pix)); 
+        pos +=step;
+      }        
+    }
+    else if ((width*2) == fb_width) {
+      for (int i=0; i<width; i++)
+      {
+        uint16_t pix = *buf++;
+        vga_pixel col = VGA_RGB(R16(pix),G16(pix),B16(pix));
+        *dst++= col;
+        *dst++= col;
+      }       
+    }
+    else {
+      if (width <= fb_width) {
+        dst += (fb_width-width)/2;
+      }
+      for (int i=0; i<width; i++)
+      {
+        uint16_t pix = *buf++;
+        *dst++= VGA_RGB(R16(pix),G16(pix),B16(pix));
+      }      
+    }
+  }  
+}
+
+void PICO_DSP::writeLinePal(int width, int height, int y, uint8_t *buf, dsp_pixel *palette) {
+  if (gfxmode == MODE_TFT_320x240) {
+    if ( (height<fb_height) && (height > 2) ) y += (fb_height-height)/2;
+    uint16_t * block=blocks[y>>6];
+    uint16_t * dst=&block[(y&0x3F)*fb_stride];
+    if (width > fb_width) {
+#ifdef TFT_LINEARINT    
+      int delta = (width/(width-fb_width))-1;
+      int pos = delta;
+      for (int i=0; i<fb_width; i++)
+      {
+        uint16_t val = palette[*buf++];
+        pos--;
+        if (pos == 0) {
+#ifdef LINEARINT_HACK
+          val  = ((uint32_t)palette[*buf++] + val)/2;
+#else
+          uint16_t val2 = *buf++;
+          val = RGBVAL16((R16(val)+R16(val2))/2,(G16(val)+G16(val2))/2,(B16(val)+B16(val2))/2);
+#endif        
+          pos = delta;
+        }
+        *dst++=val;
+      }
+#else
+      int step = ((width << 8)/fb_width);
+      int pos = 0;
+      for (int i=0; i<fb_width; i++)
+      {
+        *dst++=palette[buf[pos >> 8]];
+        pos +=step;
+      }  
+#endif
+    }
+    else if ((width*2) == fb_width) {
+      for (int i=0; i<width; i++)
+      {
+        *dst++=palette[*buf];
+        *dst++=palette[*buf++];
+      } 
+    }
+    else {
+      if (width <= fb_width) {
+        dst += (fb_width-width)/2;
+      }
+      for (int i=0; i<width; i++)
+      {
+        *dst++=palette[*buf++];
+      } 
+    }    
+  }  
+  else {
+    if ( (height<fb_height) && (height > 2) ) y += (fb_height-height)/2;
+    vga_pixel * dst=&framebuffer[y*fb_stride];
+    if (width > fb_width) {
+      int step = ((width << 8)/fb_width);
+      int pos = 0;
+      for (int i=0; i<fb_width; i++)
+      {
+        uint16_t pix = palette[buf[pos >> 8]];
+        *dst++= VGA_RGB(R16(pix),G16(pix),B16(pix));
+        pos +=step;
+      }  
+    }
+    else if ((width*2) == fb_width) {
+      for (int i=0; i<width; i++)
+      {
+        uint16_t pix = palette[*buf++];
+        *dst++= VGA_RGB(R16(pix),G16(pix),B16(pix));
+        *dst++= VGA_RGB(R16(pix),G16(pix),B16(pix));
+      } 
+    }
+    else {
+      if (width <= fb_width) {
+        dst += (fb_width-width)/2;
+      }
+      for (int i=0; i<width; i++)
+      {
+        uint16_t pix = palette[*buf++];
+        *dst++= VGA_RGB(R16(pix),G16(pix),B16(pix));
+      } 
+    }
+  }
+}
+
+void PICO_DSP::writeScreenPal(int width, int height, int stride, uint8_t *buf, dsp_pixel *palette16) {
+  uint8_t *src; 
+  int i,j,y=0;
+  int sy = 0;  
+  int systep=(1<<8);
+  int h = height;
+  if (height <= ( (2*fb_height)/3)) {
+    systep=(systep*height)/fb_height;
+    h = fb_height;
+  }  
+  if (gfxmode == MODE_TFT_320x240) {
+    if (width*2 <= fb_width) {
+      for (j=0; j<h; j++)
+      {
+        uint16_t * block=blocks[y>>6];
+        uint16_t * dst=&block[(y&0x3F)*fb_stride];        
+        src=&buf[(sy>>8)*stride];
+        for (i=0; i<width; i++)
+        {
+          uint16_t val = palette16[*src++];
+          *dst++ = val;
+          *dst++ = val;
+        }
+        y++;
+        sy+=systep;  
+      }
+    }
+    else if (width <= fb_width) {
+      for (j=0; j<h; j++)
+      {
+        uint16_t * block=blocks[y>>6];
+        uint16_t * dst=&block[(y&0x3F)*fb_stride+(fb_width-width)/2];        
+        src=&buf[(sy>>8)*stride];
+        for (i=0; i<width; i++)
+        {
+          uint16_t val = palette16[*src++];
+          *dst++ = val;
+        }
+        y++;
+        sy+=systep;  
+      }
+    }
+  }       
+  else { // VGA
+    if (width*2 <= fb_width) {
+      for (j=0; j<h; j++)
+      {
+        vga_pixel * dst=&framebuffer[y*fb_stride];                
+        src=&buf[(sy>>8)*stride];
+        for (i=0; i<width; i++)
+        {
+          uint16_t pix = palette16[*src++];
+          *dst++ = VGA_RGB(R16(pix),G16(pix),B16(pix));
+          *dst++ = VGA_RGB(R16(pix),G16(pix),B16(pix));
+        }
+        y++;
+        sy+=systep;  
+      }
+    }
+    else if (width <= fb_width) {
+      for (j=0; j<h; j++)
+      {
+        vga_pixel * dst=&framebuffer[y*fb_stride+(fb_width-width)/2];                
+        src=&buf[(sy>>8)*stride];
+        for (i=0; i<width; i++)
+        {
+          uint16_t pix = palette16[*src++];
+          *dst++ = VGA_RGB(R16(pix),G16(pix),B16(pix));
+        }
+        y++;
+        sy+=systep;  
+      }
+    }
+  }
+}
+
+
+/***********************************************************************************************
+    No DMA functions
+ ***********************************************************************************************/
+void PICO_DSP::fillScreenNoDma(dsp_pixel color) {
+  if (gfxmode == MODE_TFT_320x240) {
+    digitalWrite(_cs, 0);
+    setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1);  
+    int i,j;
+    for (j=0; j<TFT_REALHEIGHT; j++)
+    {
+      for (i=0; i<TFT_REALWIDTH; i++) {
+        //digitalWrite(_dc, 1);
+        SPItransfer16(color);     
+      }
+    }
+#ifdef ILI9341  
+    digitalWrite(_dc, 0);
+    SPItransfer(ILI9341_SLPOUT);
+    digitalWrite(_dc, 1);
+#endif
+    digitalWrite(_cs, 1);
+    setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1));     
+  }
+  else {
+    fillScreen(color);
+  }   
+}
+
+void PICO_DSP::drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, dsp_pixel color) {
+  if (gfxmode == MODE_TFT_320x240) {
+    digitalWrite(_cs, 0);
+    setArea(x,y,x+w-1,y+h-1);
+    int i;
+    for (i=0; i<(w*h); i++)
+    {
+      SPItransfer16(color);
+    }
+#ifdef ILI9341  
+    digitalWrite(_dc, 0);
+    SPItransfer(ILI9341_SLPOUT);
+    digitalWrite(_dc, 1);
+#endif
+    digitalWrite(_cs, 1);
+    setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1));   
+  }
+  else {
+    drawRect(x, y, w, h, color);
+  }  
+}
+
+
+void PICO_DSP::drawSpriteNoDma(int16_t x, int16_t y, const dsp_pixel *bitmap) {  
+  drawSpriteNoDma(x,y,bitmap, 0,0,0,0);
+}
+
+void PICO_DSP::drawSpriteNoDma(int16_t x, int16_t y, const dsp_pixel *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh)
+{
+  if (gfxmode == MODE_TFT_320x240) {
+    int bmp_offx = 0;
+    int bmp_offy = 0;
+    uint16_t *bmp_ptr;
+    int w =*bitmap++;
+    int h =*bitmap++;
+    if ( (arw == 0) || (arh == 0) ) {
+      // no crop window
+      arx = x;
+      ary = y;
+      arw = w;
+      arh = h;
+    }
+    else {
+      if ( (x>(arx+arw)) || ((x+w)<arx) || (y>(ary+arh)) || ((y+h)<ary)   ) {
+        return;
+      }
+      // crop area
+      if ( (x > arx) && (x<(arx+arw)) ) { 
+        arw = arw - (x-arx);
+        arx = arx + (x-arx);
+      } else {
+        bmp_offx = arx;
+      }
+      if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) {
+        arw -= (arx+arw-x-w);
+      }  
+      if ( (y > ary) && (y<(ary+arh)) ) {
+        arh = arh - (y-ary);
+        ary = ary + (y-ary);
+      } else {
+        bmp_offy = ary;
+      }
+      if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) {
+        arh -= (ary+arh-y-h);
+      }     
+    }
+    digitalWrite(_cs, 0);
+    setArea(arx, ary, arx+arw-1, ary+arh-1);        
+    bitmap = bitmap + bmp_offy*w + bmp_offx;
+    for (int row=0;row<arh; row++)
+    {
+      bmp_ptr = (uint16_t*)bitmap;
+      for (int col=0;col<arw; col++)
+      {
+          SPItransfer16(*bmp_ptr++);             
+      } 
+      bitmap +=  w;
+    }
+#ifdef ILI9341  
+    digitalWrite(_dc, 0);
+    SPItransfer(ILI9341_SLPOUT);
+    digitalWrite(_dc, 1);
+#endif
+    setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1);  
+    digitalWrite(_cs, 1);  
+  }
+  else {
+    drawSprite(x, y, bitmap, arx, ary, arw, arh);
+  }   
+}
+
+void PICO_DSP::drawTextNoDma(int16_t x, int16_t y, const char * text, dsp_pixel fgcolor, dsp_pixel bgcolor, bool doublesize) {
+  if (gfxmode == MODE_TFT_320x240) {
+    uint16_t c;
+    while ((c = *text++)) {
+      const unsigned char * charpt=&font8x8[c][0];
+      digitalWrite(_cs, 0);
+      setArea(x,y,x+7,y+(doublesize?15:7));
+      for (int i=0;i<8;i++)
+      {
+        unsigned char bits;
+        if (doublesize) {
+          bits = *charpt;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);
+          bits = bits >> 1;     
+          if (bits&0x01) SPItransfer16(fgcolor);
+          else SPItransfer16(bgcolor);       
+        }
+        bits = *charpt++;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+        bits = bits >> 1;     
+        if (bits&0x01) SPItransfer16(fgcolor);
+        else SPItransfer16(bgcolor);
+      }
+      x +=8;
+#ifdef ILI9341  
+      digitalWrite(_dc, 0);
+      SPItransfer(ILI9341_SLPOUT);
+      digitalWrite(_dc, 1);
+#endif
+      digitalWrite(_cs, 1); 
+    }
+
+    digitalWrite(_cs, 0);
+    setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1));  
+    digitalWrite(_cs, 1);
+  }
+  else {
+    drawText(x, y, text, fgcolor, bgcolor, doublesize);
+  } 
+}
+
+
+#ifdef HAS_SND
+
+#include "hardware/dma.h"
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+#include "hardware/pwm.h"
+#include "pico/float.h"
+#include <string.h>
+#include <stdio.h>
+
+
+#ifdef AUDIO_1DMA
+#define SAMPLE_REPEAT_SHIFT 0    // not possible to repeat samples with single DMA!! 
+#endif
+#ifdef AUDIO_3DMA
+#define SAMPLE_REPEAT_SHIFT 2    // shift 2 is REPETITION_RATE=4
+#endif
+#ifndef SAMPLE_REPEAT_SHIFT
+#define SAMPLE_REPEAT_SHIFT 0    // not possible to repeat samples CBACK!!
+#endif
+
+#define REPETITION_RATE     (1<<SAMPLE_REPEAT_SHIFT) 
+
+static void (*fillsamples)(audio_sample * stream, int len) = nullptr;
+static audio_sample * snd_buffer;       // samples buffer (1 malloc for 2 buffers)
+static uint16_t snd_nb_samples;         // total nb samples (mono) later divided by 2
+static uint16_t snd_sample_ptr = 0;     // sample index
+static audio_sample * audio_buffers[2]; // pointers to 2 samples buffers 
+static volatile int cur_audio_buffer;
+static volatile int last_audio_buffer;
+#ifdef AUDIO_3DMA
+static uint32_t single_sample = 0;
+static uint32_t *single_sample_ptr = &single_sample;
+static int pwm_dma_chan, trigger_dma_chan, sample_dma_chan;
+#endif
+#ifdef AUDIO_1DMA
+static int pwm_dma_chan;
+#endif
+
+/********************************
+ * Processing
+********************************/ 
+#ifdef AUDIO_1DMA
+static void __isr __time_critical_func(AUDIO_isr)()
+{
+  cur_audio_buffer = 1 - cur_audio_buffer;  
+  dma_hw->ch[pwm_dma_chan].al3_read_addr_trig = (intptr_t)audio_buffers[cur_audio_buffer];
+  dma_hw->ints1 = (1u << pwm_dma_chan);   
+}
+#endif
+
+#ifdef AUDIO_3DMA
+static void __isr __time_critical_func(AUDIO_isr)()
+{
+  cur_audio_buffer = 1 - cur_audio_buffer;  
+  dma_hw->ch[sample_dma_chan].al1_read_addr = (intptr_t)audio_buffers[cur_audio_buffer];
+  dma_hw->ch[trigger_dma_chan].al3_read_addr_trig = (intptr_t)&single_sample_ptr;
+  dma_hw->ints1 = (1u << trigger_dma_chan);
+}
+#endif
+
+// fill half buffer depending on current position
+static void pwm_audio_handle_buffer(void)
+{
+  if (last_audio_buffer == cur_audio_buffer) {
+    return;
+  }
+  audio_sample *buf = audio_buffers[last_audio_buffer];
+  last_audio_buffer = cur_audio_buffer;
+  if (fillsamples != NULL) fillsamples(buf, snd_nb_samples);
+}
+
+static void pwm_audio_reset(void)
+{
+  memset((void*)snd_buffer,0, snd_nb_samples*sizeof(uint8_t));
+}
+
+
+/********************************
+ * Initialization
+********************************/ 
+static void pwm_audio_init(int buffersize, void (*callback)(audio_sample * stream, int len))
+{
+  fillsamples = callback;
+  snd_nb_samples = buffersize;
+  snd_sample_ptr = 0;
+  snd_buffer =  (audio_sample*)malloc(snd_nb_samples*sizeof(audio_sample));
+  if (snd_buffer == NULL) {
+    printf("sound buffer could not be allocated!!!!!\n");
+    return;  
+  }
+  memset((void*)snd_buffer,128, snd_nb_samples*sizeof(audio_sample));
+
+  gpio_set_function(AUDIO_PIN, GPIO_FUNC_PWM);
+
+  int audio_pin_slice = pwm_gpio_to_slice_num(AUDIO_PIN);
+  pwm_set_gpio_level(AUDIO_PIN, 0);
+
+  // Setup PWM for audio output
+  pwm_config config = pwm_get_default_config();
+  pwm_config_set_clkdiv(&config, (((float)SOUNDRATE)/1000) / REPETITION_RATE);
+  pwm_config_set_wrap(&config, 254);
+  pwm_init(audio_pin_slice, &config, true);
+
+  snd_nb_samples = snd_nb_samples/2;
+  audio_buffers[0] = &snd_buffer[0];
+  audio_buffers[1] = &snd_buffer[snd_nb_samples];
+
+#ifdef AUDIO_3DMA
+  int audio_pin_chan = pwm_gpio_to_channel(AUDIO_PIN);
+  // DMA chain of 3 DMA channels
+  sample_dma_chan = AUD_DMA_CHANNEL;
+  pwm_dma_chan = AUD_DMA_CHANNEL+1;
+  trigger_dma_chan = AUD_DMA_CHANNEL+2;
+
+  // setup PWM DMA channel
+  dma_channel_config pwm_dma_chan_config = dma_channel_get_default_config(pwm_dma_chan);
+  channel_config_set_transfer_data_size(&pwm_dma_chan_config, DMA_SIZE_32);              // transfer 32 bits at a time
+  channel_config_set_read_increment(&pwm_dma_chan_config, false);                        // always read from the same address
+  channel_config_set_write_increment(&pwm_dma_chan_config, false);                       // always write to the same address
+  channel_config_set_chain_to(&pwm_dma_chan_config, sample_dma_chan);                    // trigger sample DMA channel when done
+  channel_config_set_dreq(&pwm_dma_chan_config, DREQ_PWM_WRAP0 + audio_pin_slice);       // transfer on PWM cycle end
+  dma_channel_configure(pwm_dma_chan,
+                        &pwm_dma_chan_config,
+                        &pwm_hw->slice[audio_pin_slice].cc,   // write to PWM slice CC register
+                        &single_sample,                       // read from single_sample
+                        REPETITION_RATE,                      // transfer once per desired sample repetition
+                        false                                 // don't start yet
+                        );
+
+
+  // setup trigger DMA channel
+  dma_channel_config trigger_dma_chan_config = dma_channel_get_default_config(trigger_dma_chan);
+  channel_config_set_transfer_data_size(&trigger_dma_chan_config, DMA_SIZE_32);          // transfer 32-bits at a time
+  channel_config_set_read_increment(&trigger_dma_chan_config, false);                    // always read from the same address
+  channel_config_set_write_increment(&trigger_dma_chan_config, false);                   // always write to the same address
+  channel_config_set_dreq(&trigger_dma_chan_config, DREQ_PWM_WRAP0 + audio_pin_slice);   // transfer on PWM cycle end
+  dma_channel_configure(trigger_dma_chan,
+                        &trigger_dma_chan_config,
+                        &dma_hw->ch[pwm_dma_chan].al3_read_addr_trig,     // write to PWM DMA channel read address trigger
+                        &single_sample_ptr,                               // read from location containing the address of single_sample
+                        REPETITION_RATE * snd_nb_samples,              // trigger once per audio sample per repetition rate
+                        false                                             // don't start yet
+                        );
+  dma_channel_set_irq1_enabled(trigger_dma_chan, true);    // fire interrupt when trigger DMA channel is done
+  irq_set_exclusive_handler(DMA_IRQ_1, AUDIO_isr);
+  irq_set_priority (DMA_IRQ_1, PICO_DEFAULT_IRQ_PRIORITY-8);
+  irq_set_enabled(DMA_IRQ_1, true);
+
+  // setup sample DMA channel
+  dma_channel_config sample_dma_chan_config = dma_channel_get_default_config(sample_dma_chan);
+  channel_config_set_transfer_data_size(&sample_dma_chan_config, DMA_SIZE_8);  // transfer 8-bits at a time
+  channel_config_set_read_increment(&sample_dma_chan_config, true);            // increment read address to go through audio buffer
+  channel_config_set_write_increment(&sample_dma_chan_config, false);          // always write to the same address
+  dma_channel_configure(sample_dma_chan,
+                        &sample_dma_chan_config,
+                        (char*)&single_sample + 2*audio_pin_chan,  // write to single_sample
+                        snd_buffer,                      // read from audio buffer
+                        1,                                         // only do one transfer (once per PWM DMA completion due to chaining)
+                        false                                      // don't start yet
+                        );
+
+    // Kick things off with the trigger DMA channel
+    dma_channel_start(trigger_dma_chan);
+#endif
+#ifdef AUDIO_1DMA
+  // Each sample played from a single DMA channel
+  // Setup DMA channel to drive the PWM
+  pwm_dma_chan = AUD_DMA_CHANNEL;
+  dma_channel_config pwm_dma_chan_config = dma_channel_get_default_config(pwm_dma_chan);
+  // Transfer 16 bits at once, increment read address to go through sample
+  // buffer, always write to the same address (PWM slice CC register).
+  channel_config_set_transfer_data_size(&pwm_dma_chan_config, DMA_SIZE_16);
+  channel_config_set_read_increment(&pwm_dma_chan_config, true);
+  channel_config_set_write_increment(&pwm_dma_chan_config, false);
+  // Transfer on PWM cycle end
+  channel_config_set_dreq(&pwm_dma_chan_config, DREQ_PWM_WRAP0 + audio_pin_slice);
+
+  // Setup the channel and set it going
+  dma_channel_configure(
+      pwm_dma_chan,
+      &pwm_dma_chan_config,
+      &pwm_hw->slice[audio_pin_slice].cc, // Write to PWM counter compare
+      snd_buffer, // Read values from audio buffer
+      snd_nb_samples,
+      false // Start immediately if true.
+  );
+
+  // Setup interrupt handler to fire when PWM DMA channel has gone through the
+  // whole audio buffer
+  dma_channel_set_irq1_enabled(pwm_dma_chan, true);
+  irq_set_exclusive_handler(DMA_IRQ_1, AUDIO_isr);
+  //irq_set_priority (DMA_IRQ_1, PICO_DEFAULT_IRQ_PRIORITY-8);
+  irq_set_enabled(DMA_IRQ_1, true);
+  dma_channel_start(pwm_dma_chan);
+#endif
+}
+
+static void core1_func_tft() {
+    while (true) {
+        pwm_audio_handle_buffer();
+        __dmb();
+    }
+}
+
+void PICO_DSP::begin_audio(int samplesize, void (*callback)(short * stream, int len))
+{
+  multicore_launch_core1(core1_func_tft);
+  pwm_audio_init(samplesize, callback);
+}
+
+void PICO_DSP::end_audio()
+{
+}
+#endif
+
+ 
+
diff --git a/MCUME_pico2/display/pico_dsp.h b/MCUME_pico2/display/pico_dsp.h
new file mode 100755
index 0000000..3601b9a
--- /dev/null
+++ b/MCUME_pico2/display/pico_dsp.h
@@ -0,0 +1,126 @@
+/*
+  This file is part of DISPLAY library. 
+  Supports VGA and TFT display
+
+  DISPLAY library is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+	Teensy VGA inspired from the original Teensy3 uVGA library of Eric PREVOTEAU.
+	QTIMER/FlexIO code based on Teensy4 examples of KurtE, Manitou and easone 
+	from the Teensy4 forum (https://forum.pjrc.com)
+*/
+
+#ifndef _PICO_DSP_H
+#define _PICO_DSP_H
+
+#ifdef __cplusplus
+#include <stdio.h>
+#include <math.h>
+#include "pico.h"
+#endif
+
+#include "platform_config.h"
+#include "iopins.h"
+
+
+#ifdef LOHRES
+#define TFT_WIDTH      240 
+#define TFT_REALWIDTH  240
+#else
+#ifdef OVERRULE_WIDTH
+#define TFT_WIDTH      OVERRULE_WIDTH
+#else 
+#define TFT_WIDTH      320 
+#endif
+#define TFT_REALWIDTH  320
+#endif
+#ifdef OVERRULE_HEIGHT
+#define TFT_HEIGHT     OVERRULE_HEIGHT
+#else 
+#define TFT_HEIGHT     240
+#endif
+#define TFT_REALHEIGHT 240
+
+typedef uint8_t  vga_pixel;
+typedef uint16_t dsp_pixel;
+
+typedef enum gfx_mode_t
+{
+  MODE_UNDEFINED   = 0,
+  MODE_TFT_320x240 = 1,
+  MODE_VGA_320x240 = 2,
+  MODE_VGA_256x240 = 3,
+  MODE_VGA_640x240 = 4
+} gfx_mode_t;
+
+typedef enum vga_error_t
+{
+	GFX_OK = 0,
+	GFX_ERROR = -1
+} gfx_error_t;
+
+class PICO_DSP
+{
+public:
+
+  PICO_DSP();
+
+  // Initialization
+  gfx_error_t begin(gfx_mode_t mode);
+  gfx_mode_t getMode(void);
+  void end();
+  void startRefresh(void);
+  void stopRefresh();
+  
+#ifdef HAS_SND  
+  void begin_audio(int samplesize, void (*callback)(short * stream, int len));
+  void end_audio();
+#endif
+
+  // framebuffer/screen operation
+  int get_frame_buffer_size(int *width, int *height);
+  void setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2);
+  void flipscreen(bool flip);
+  bool isflipped(void);
+
+  // wait next Vsync
+  void waitSync();
+  void waitLine(int line);
+
+  // =========================================================
+  // graphic primitives
+  // =========================================================
+
+  dsp_pixel * getLineBuffer(int j);
+  void writeLine(int width, int height, int y, dsp_pixel *buf);
+  void writeLinePal(int width, int height, int y, uint8_t *buffer, dsp_pixel *palette16);
+  void writeScreenPal(int width, int height, int stride, uint8_t *buf, dsp_pixel *palette16);
+  
+  void fillScreen(dsp_pixel color);
+  void drawText(int16_t x, int16_t y, const char * text, dsp_pixel fgcolor, dsp_pixel bgcolor, bool doublesize);
+  void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, dsp_pixel color);
+  void drawSprite(int16_t x, int16_t y, const dsp_pixel *bitmap);
+  void drawSprite(int16_t x, int16_t y, const dsp_pixel *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh);
+
+  // NoDMA functions
+  void fillScreenNoDma(dsp_pixel color);
+  void drawTextNoDma(int16_t x, int16_t y, const char * text, dsp_pixel fgcolor, dsp_pixel bgcolor, bool doublesize);
+  void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, dsp_pixel color);
+  void drawSpriteNoDma(int16_t x, int16_t y, const dsp_pixel *bitmap);
+  void drawSpriteNoDma(int16_t x, int16_t y, const dsp_pixel *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh);
+
+private:
+  static uint8_t _vsync_pin;
+
+protected:   
+  uint8_t _rst, _cs, _dc;
+  uint8_t _miso, _mosi, _sclk, _bkl;
+  bool flipped=false;  
+};
+
+
+#endif
+
+
diff --git a/MCUME_pico2/fatfs/.DS_Store b/MCUME_pico2/fatfs/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/fatfs/.DS_Store differ
diff --git a/MCUME_pico2/fatfs/LICENSE.txt b/MCUME_pico2/fatfs/LICENSE.txt
new file mode 100644
index 0000000..25379e4
--- /dev/null
+++ b/MCUME_pico2/fatfs/LICENSE.txt
@@ -0,0 +1,24 @@
+FatFs License
+
+FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files.
+
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  Rx.xx                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 20xx, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+Therefore FatFs license is one of the BSD-style licenses, but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, do not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses include GNU GPL. When you redistribute the FatFs source code with changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license.
diff --git a/MCUME_pico2/fatfs/README.asc b/MCUME_pico2/fatfs/README.asc
new file mode 100644
index 0000000..1c95d4f
--- /dev/null
+++ b/MCUME_pico2/fatfs/README.asc
@@ -0,0 +1,23 @@
+= FatFs
+
+This is a copy of FatFs, a "generic FAT file system module for small embedded
+systems", by ChaN. See http://elm-chan.org/fsw/ff/00index_e.html.
+
+Please submit bug reports to the http://elm-chan.org/fsw/ff/bd/[FatFs
+User Forum], not to this repo.
+
+== License
+
+Copyright (C) 2022, ChaN, all right reserved.
+
+FatFs module is an open source software. Redistribution and use of FatFs in
+source and binary forms, with or without modification, are permitted provided
+that the following condition is met:
+
+1. Redistributions of source code must retain the above copyright notice,
+   this condition and the following disclaimer.
+
+This software is provided by the copyright holder and contributors "AS IS"
+and any warranties related to this software are DISCLAIMED.
+The copyright owner or contributors be NOT LIABLE for any damages caused
+by use of this software.
diff --git a/MCUME_pico2/fatfs/documents/00index_e.html b/MCUME_pico2/fatfs/documents/00index_e.html
new file mode 100644
index 0000000..b3b8adb
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/00index_e.html
@@ -0,0 +1,149 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<meta http-equiv="cache-control" content="no-cache">
+<meta name="description" content="Open source FAT filesystem for embedded projects">
+<link rel="start" title="Site Top" href="../../">
+<link rel="up" title="Freewares" href="../../fsw_e.html">
+<link rel="stylesheet" href="css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - Generic FAT Filesystem Module</title>
+</head>
+
+<body>
+<h1>FatFs - Generic FAT Filesystem Module</h1>
+<hr>
+
+<div class="abst">
+<img src="res/layers.png" class="rset" width="245" height="255" alt="layer">
+<p>FatFs is a generic FAT/exFAT filesystem module for small embedded systems. The FatFs module is written in compliance with ANSI C (C89) and completely separated from the disk I/O layer. Therefore it is independent of the platform. It can be incorporated into small microcontrollers with limited resource, such as 8051, PIC, AVR, ARM, Z80, RX and etc. Also Petit FatFs module for tiny microcontrollers is available <a href="http://elm-chan.org/fsw/ff/00index_p.html">here</a>.</p>
+
+<h4>Features</h4>
+<ul>
+ <li>DOS/Windows Compatible FAT/exFAT Filesystem.</li>
+ <li>Platform Independent. <a href="doc/appnote.html#port">Easy to port</a>.</li>
+ <li>Very Small <a href="doc/appnote.html#memory">Footprint</a> for Program Code and Work Area.</li>
+ <li>Various <a href="doc/config.html">Configuration Options</a> to Support for:
+  <ul>
+   <li>Long File Name in ANSI/OEM or Unicode.</li>
+   <li>exFAT Filesystem, 64-bit LBA and GPT for Huge Storages.</li>
+   <li>Thread Safe for RTOS.</li>
+   <li>Multiple Volumes. (Physical Drives and Partitions)</li>
+   <li>Variable Sector Size.</li>
+   <li>Multiple Code Pages Including DBCS.</li>
+   <li>Read-only, Optional APIs, I/O Buffer and etc...</li>
+  </ul>
+ </li>
+</ul>
+</div>
+
+
+<div class="para">
+<h3>Application Interface</h3>
+<img src="res/layers1.png" class="rset" width="245" height="220" alt="layer">
+<p>FatFs provides various filesystem functions for the applications as shown below.</p>
+<ul>
+ <li>File Access
+ <ul>
+  <li><a href="doc/open.html">f_open</a> - Open/Create a file</li>
+  <li><a href="doc/close.html">f_close</a> - Close an open file</li>
+  <li><a href="doc/read.html">f_read</a> - Read data from the file</li>
+  <li><a href="doc/write.html">f_write</a> - Write data to the file</li>
+  <li><a href="doc/lseek.html">f_lseek</a> - Move read/write pointer, Expand size</li>
+  <li><a href="doc/truncate.html">f_truncate</a> - Truncate file size</li>
+  <li><a href="doc/sync.html">f_sync</a> - Flush cached data</li>
+  <li><a href="doc/forward.html">f_forward</a> - Forward data to the stream</li>
+  <li><a href="doc/expand.html">f_expand</a> - Allocate a contiguous block to the file</li>
+  <li><a href="doc/gets.html">f_gets</a> - Read a string</li>
+  <li><a href="doc/putc.html">f_putc</a> - Write a character</li>
+  <li><a href="doc/puts.html">f_puts</a> - Write a string</li>
+  <li><a href="doc/printf.html">f_printf</a> - Write a formatted string</li>
+  <li><a href="doc/tell.html">f_tell</a> - Get current read/write pointer</li>
+  <li><a href="doc/eof.html">f_eof</a> - Test for end-of-file</li>
+  <li><a href="doc/size.html">f_size</a> - Get size</li>
+  <li><a href="doc/error.html">f_error</a> - Test for an error</li>
+ </ul>
+ </li>
+ <li>Directory Access
+ <ul>
+  <li><a href="doc/opendir.html">f_opendir</a> - Open a directory</li>
+  <li><a href="doc/closedir.html">f_closedir</a> - Close an open directory</li>
+  <li><a href="doc/readdir.html">f_readdir</a> - Read a directory item</li>
+  <li><a href="doc/findfirst.html">f_findfirst</a> - Open a directory and read the first item matched</li>
+  <li><a href="doc/findnext.html">f_findnext</a> - Read a next item matched</li>
+ </ul>
+ </li>
+ <li>File and Directory Management
+ <ul>
+  <li><a href="doc/stat.html">f_stat</a> - Check existance of a file or sub-directory</li>
+  <li><a href="doc/unlink.html">f_unlink</a> - Remove a file or sub-directory</li>
+  <li><a href="doc/rename.html">f_rename</a> - Rename/Move a file or sub-directory</li>
+  <li><a href="doc/chmod.html">f_chmod</a> - Change attribute of a file or sub-directory</li>
+  <li><a href="doc/utime.html">f_utime</a> - Change timestamp of a file or sub-directory</li>
+  <li><a href="doc/mkdir.html">f_mkdir</a> - Create a sub-directory</li>
+  <li><a href="doc/chdir.html">f_chdir</a> - Change current directory</li>
+  <li><a href="doc/chdrive.html">f_chdrive</a> - Change current drive</li>
+  <li><a href="doc/getcwd.html">f_getcwd</a> - Retrieve the current directory and drive</li>
+ </ul>
+ </li>
+ <li>Volume Management and System Configuration
+ <ul>
+  <li><a href="doc/mount.html">f_mount</a> - Register/Unregister the work area of the volume</li>
+  <li><a href="doc/mkfs.html">f_mkfs</a> - Create an FAT volume on the logical drive</li>
+  <li><a href="doc/fdisk.html">f_fdisk</a> - Create partitions on the physical drive</li>
+  <li><a href="doc/getfree.html">f_getfree</a> - Get free space on the volume</li>
+  <li><a href="doc/getlabel.html">f_getlabel</a> - Get volume label</li>
+  <li><a href="doc/setlabel.html">f_setlabel</a> - Set volume label</li>
+  <li><a href="doc/setcp.html">f_setcp</a> - Set active code page</li>
+ </ul>
+ </li>
+</ul>
+</div>
+
+
+<div class="para">
+<h3>Media Access Interface</h3>
+<img src="res/layers2.png" class="rset" width="245" height="220" alt="layer">
+<p>Since FatFs module is the <em>Filesystem Layer</em> independent of platforms and storage media, it is completely separated from the physical devices, such as memory card, harddisk and any type of storage device. The storage device control module is <em>not any part of FatFs module</em> and it needs to be provided by implementer. FatFs controls the storage devices via a simple media access interface shown below. Also sample implementations for some platforms are available in the downloads. A function checker for storage device control module is available <a href="res/app4.c">here</a>.</p>
+<ul>
+ <li>Storage Device Controls
+ <ul>
+  <li><a href="doc/dstat.html">disk_status</a> - Get device status</li>
+  <li><a href="doc/dinit.html">disk_initialize</a> - Initialize device</li>
+  <li><a href="doc/dread.html">disk_read</a> - Read data</li>
+  <li><a href="doc/dwrite.html">disk_write</a> - Write data</li>
+  <li><a href="doc/dioctl.html">disk_ioctl</a> - Control device dependent functions</li>
+ </ul>
+ </li>
+ <li>Real Time Clock
+ <ul>
+  <li><a href="doc/fattime.html">get_fattime</a> - Get current time</li>
+ </ul>
+ </li>
+</ul>
+</div>
+
+
+<div class="para">
+<h3>Resources</h3>
+<p>The FatFs module is a free software opened for education, research and development. You can use, modify and/or redistribute it for any purpose without any restriction under your responsibility. For further information, refer to the application note.</p>
+<ul>
+ <li><em>Getting Started: <a href="doc/appnote.html">FatFs Application Note</a></em></li>
+ <li>Community: <a href="http://elm-chan.org/fsw/ff/bd/">FatFs User Forum</a></li>
+ <li><a href="https://msdn.microsoft.com/en-us/windows/hardware/gg463080.aspx">FAT32 Specification by Microsoft</a>↗ (The authorized document on FAT filesystem)</li>
+ <li><a href="http://elm-chan.org/docs/fat_e.html">The basics of FAT filesystem</a> (FatFs is written based on this documentation)</li>
+ <li><a href="http://elm-chan.org/docs/exfat_e.html">The basics of exFAT filesystem</a> (FatFs is written based on this documentation)</li>
+ <li><a href="http://elm-chan.org/docs/mmc/mmc_e.html">How to use MMC/SDC</a></li>
+ <li><a href="http://elm-chan.org/junk/fa/faff.html">Playing with FlashAir and FatFs</a></li>
+ <li><a href="http://nemuisan.blog.bai.ne.jp/">Nemuisan's Blog</a>↗ (Well written implementations for STM32F/SPI &amp; SDIO and LPC4088/SDMMC)</li>
+ <li><a href="http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/">Read SD card with FatFs on STM32F4xx devices by Tilen Majerle</a>↗ (Quick and easy implementation for STM32F4-Discovery)</li>
+ <li><a href="res/rwtest1.png">Benchmark 1</a> (ATmega1284/20MHz with MMC via USART in SPI, CFC via GPIO)</li>
+ <li><a href="res/rwtest2.png">Benchmark 2</a> (LPC2368/72MHz with MMC via MCI)</li>
+</div>
+
+
+<hr>
+<p class="foot"><a href="../../fsw_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/css_e.css b/MCUME_pico2/fatfs/documents/css_e.css
new file mode 100644
index 0000000..1181a09
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/css_e.css
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+* {margin: 0; padding: 0; border-width: 0;}
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/appnote.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs Module Application Note</title>
+</head>
+
+<body>
+<h1>FatFs Module Application Note</h1>
+<ol class="toc">
+<li><a href="#port">How to Port</a></li>
+<li><a href="#limits">Limits</a></li>
+<li><a href="#memory">Memory Usage</a></li>
+<li><a href="#reduce">Reducing Module Size</a></li>
+<li><a href="#lfn">Long File Name</a></li>
+<li><a href="#unicode">Unicode API</a></li>
+<li><a href="#exfat">exFAT Filesystem</a></li>
+<li><a href="#lba64">64-bit LBA</a></li>
+<li><a href="#reentrant">Re-entrancy</a></li>
+<li><a href="#dup">Duplicated File Access</a></li>
+<li><a href="#fs1">Performance Effective File Access</a></li>
+<li><a href="#fs2">Considerations on Flash Memory Media</a></li>
+<li><a href="#critical">Critical Section</a></li>
+<li><a href="#fs3">Various Usable Functions for FatFs Projects</a></li>
+<li><a href="#license">About FatFs License</a></li>
+</ol>
+
+<div class="para doc" id="port">
+<h3>How to Port</h3>
+
+<h4>Basic Considerations</h4>
+<p>The FatFs module assumes following conditions on portability.</p>
+<ul>
+<li>ANSI C<br>
+The FatFs module is a middleware written in ANSI C (C89). There is no platform dependence, so long as the compiler is in compliance with C89 or later. Only exFAT feature requires C99.</li>
+<li>Size of integer types<br>
+<ul>
+<li>Size of <tt>char</tt> must be 8-bit.</li>
+<li>Size of <tt>int</tt>, as well as integer promotion, must be 16-bit or 32-bit.</li>
+<li>Size of <tt>short</tt> and <tt>long</tt> must be 16-bit and 32-bit respectively. (in C89 only)</li>
+</ul>
+<li>Dependency<br>
+<ul>
+<li>C89: <tt>string.h</tt>.</li>
+<li>C99: <tt>string.h</tt> and <tt>stdint.h</tt>.</li>
+<li>Optional: <tt>stdarg.h</tt> and <tt>math.h</tt>.</li>
+</ul>
+</ul>
+
+<h4>Integer Types in FatFs API</h4>
+<p>Integer types used in FatFs are defined in <tt>ff.h</tt> as described below. It is based on Win32 API (<tt>windef.h</tt>). This will not be a problem on most platform. When a conflict with existing definitions occured, you must resolve it with care.</p>
+<dl>
+<dt><tt>BYTE</tt></dt><dd>8-bit unsigned integer in range of 0 to 2<sup>8</sup> - 1.</dd>
+<dt><tt>WORD</tt></dt><dd>16-bit unsigned integer in range of 0 to 2<sup>16</sup> - 1.</dd>
+<dt><tt>DWORD</tt></dt><dd>32-bit unsigned integer in range of 0 to 2<sup>32</sup> - 1.</dd>
+<dt><tt>QWORD</tt></dt><dd>64-bit unsigned integer in range of 0 to 2<sup>64</sup> - 1.</dd>
+<dt><tt>UINT</tt></dt><dd>Alias of <tt>unsigned int</tt> used to specify any number.</dd>
+<dt><tt>WCHAR</tt></dt><dd>Alias of <tt>WORD</tt> used to specify a UTF-16 code unit.</dd>
+<dt><tt>TCHAR</tt></dt><dd>Alias of <tt>char</tt>, <tt>WCHAR</tt> or <tt>DWORD</tt> used to specify a character encoding unit.</dd>
+<dt><tt>FSIZE_t</tt></dt><dd>Alias of <tt>DWORD</tt> or <tt>QWORD</tt> used to address file offset and to specify file size.</dd>
+<dt><tt>LBA_t</tt></dt><dd>Alias of <tt>DWORD</tt> or <tt>QWORD</tt> used to address sectors in LBA and to specify number of sectors.</dd>
+</dl>
+
+<h4>System Organizations</h4>
+<p>The dependency diagram shown below is a typical, but not specific, configuration of the embedded system with FatFs module.</p>
+<p><img src="../res/modules.png" width="580" height="280" alt="dependency diagram"></p>
+<p>(a) If a working disk module for FatFs is provided, nothing else will be needed. (b) To attach existing disk drivers with different interface, some glue functions are needed to translate the interfaces between FatFs and the driver.</p>
+<p><img src="../res/funcs.png" width="750" height="420" alt="functional diagram"></p>
+
+<h4>Required Functions</h4>
+<p>You need to provide only MAI functions required by FatFs module and nothing else. If a working device control module for the target system is available, you need to write only glue functions to attach it to the FatFs module. If not, you need to port another device control module or write it from scratch. Most of MAI functions are not that always required. For instance, the write function is not required in read-only configuration. Following table shows which function is required depends on the configuration options.</p>
+<table class="lst2">
+<tr><th>Function</th><th>Required when:</th><th>Note</th></tr>
+<tr><td>disk_status<br>disk_initialize<br>disk_read</td><td>Always</td><td rowspan="5">Disk I/O functions.<br>Samples available in ffsample.zip.<br>There are many implementations on the web.</td></tr>
+<tr><td>disk_write<br>get_fattime<br>disk_ioctl (CTRL_SYNC)</td><td><a href="config.html#fs_readonly">FF_FS_READONLY == 0</a></td></tr>
+<tr><td>disk_ioctl (GET_SECTOR_COUNT)<br>disk_ioctl (GET_BLOCK_SIZE)</td><td><a href="config.html#use_mkfs">FF_USE_MKFS == 1</a></td></tr>
+<tr><td>disk_ioctl (GET_SECTOR_SIZE)</td><td><a href="config.html#max_ss">FF_MAX_SS != FF_MIN_SS</a></td></tr>
+<tr><td>disk_ioctl (CTRL_TRIM)</td><td><a href="config.html#use_trim">FF_USE_TRIM == 1</a></td></tr>
+<tr><td>ff_uni2oem<br>ff_oem2uni<br>ff_wtoupper</td><td><a href="config.html#use_lfn">FF_USE_LFN != 0</a></td><td>Unicode support functions.<br>Add optional module ffunicode.c to the project.</td></tr>
+<tr><td>ff_cre_syncobj<br>ff_del_syncobj<br>ff_req_grant<br>ff_rel_grant</td><td><a href="config.html#fs_reentrant">FF_FS_REENTRANT == 1</a></td><td rowspan="2">O/S dependent functions.<br>Sample code is available in ffsystem.c.</td></tr>
+<tr><td>ff_mem_alloc<br>ff_mem_free</td><td>FF_USE_LFN == 3</td></tr>
+</table>
+<p>FatFs cares about neither what kind of storage device is used nor how it is implemented. Only a requirement is that it is a block device read/written in fixed-size blocks that accessible via the disk I/O functions defined above.</p>
+</div>
+
+<div class="para doc" id="limits">
+<h3>Limits</h3>
+<ul>
+<li>Filesystem type: FAT, FAT32(rev0.0) and exFAT(rev1.0).</li>
+<li>Number of open files: Unlimited. (depends on available memory)</li>
+<li>Number of volumes: Up to 10.</li>
+<li>Sector size: 512, 1024, 2048 and 4096 bytes.</li>
+<li>Minimum volume size: 128 sectors.</li>
+<li>Maximum volume size: 2<sup>32</sup> - 1 sectors in 32-bit LBA, virtually unlimited in 64-bit LBA with exFAT.</li>
+<li>Maximum file size: 2<sup>32</sup> - 1 bytes on FAT volume, virtually unlimited on exFAT volume.</li>
+<li>Cluster size: Upto 128 sectors on FAT volume and up to 16 MB on exFAT volume.</li>
+</ul>
+</div>
+
+<div class="para doc" id="memory">
+<h3>Memory Usage</h3>
+<p>The memory usage varies depends on the <a href="config.html">configuration options</a>.</p>
+<table class="lst2">
+<tr><th></th><th>ARM7<small><br>32bit</small></th><th>ARM7<small><br>Thumb</small></th><th>CM3<small><br>Thumb-2</small></th><th>AVR</th><th>H8/300H</th><th>PIC24</th><th>RL78</th><th>V850ES</th><th>SH-2A</th><th>RX600</th><th>IA-32</th></tr>
+<tr class="cal">     <td>Compiler</td><td>GCC</td><td>GCC</td><td>GCC</td><td>GCC</td><td>CH38</td><td>C30</td><td>CC78K0R</td><td>CA850</td><td>SHC</td><td>RXC</td><td>MSC</td></tr>
+<!--                                                      ARM        Thumb          CM3           AVR            H8          PIC24          RL78       V850ES        SH-2A        RX600        IA-32   -->
+<tr class="ral"><td class="cal">.text (Def, R/W)</td><td>10.4k</td><td>6.7k</td><td>6.1k</td><td>12.5k</td><td>11.0k</td><td>11.4k</td><td>13.0k</td><td>8.9k</td><td>9.2k</td><td>6.5k</td><td>8.9k</td></tr>
+<tr class="ral"><td class="cal">.text (Min, R/W)</td> <td>7.0k</td><td>4.7k</td><td>4.2k</td> <td>8.5k</td> <td>7.6k</td> <td>7.9k</td> <td>9.5k</td><td>6.3k</td><td>6.4k</td><td>4.7k</td><td>6.4k</td></tr>
+<tr class="ral"><td class="cal">.text (Def, R/O)</td> <td>4.9k</td><td>3.2k</td><td>2.7k</td> <td>6.1k</td> <td>5.2k</td> <td>5.4k</td> <td>6.5k</td><td>4.3k</td><td>4.2k</td><td>3.2k</td><td>4.3k</td></tr>
+<tr class="ral"><td class="cal">.text (Min, R/O)</td> <td>3.7k</td><td>2.5k</td><td>2.1k</td> <td>4.4k</td> <td>4.0k</td> <td>4.2k</td> <td>5.1k</td><td>3.4k</td><td>3.3k</td><td>2.5k</td><td>3.5k</td></tr>
+<tr class="ral"><td class="cal">.bss</td><td>V*4 + 2</td><td>V*4 + 2</td><td>V*4 + 2</td><td>V*2 + 2</td><td>V*4 + 2</td><td>V*2 + 2</td><td>V*2 + 2</td><td>V*4 + 2</td><td>V*4 + 2</td><td>V*4 + 2</td><td>V*4 + 2</td></tr>
+<tr class="ral"><td class="cal">Work area<br><small>(FF_FS_TINY == 0)</small></td><td>V*564<br>+ F*552</td><td>V*564<br>+ F*552</td><td>V*564<br>+ F*552</td><td>V*560<br>+ F*546</td><td>V*560<br>+ F*546</td><td>V*560<br>+ F*546</td><td>V*560<br>+ F*546</td><td>V*564<br>+ F*552</td><td>V*564<br>+ F*552</td><td>V*564<br>+ F*552</td><td>V*564<br>+ F*552</td></tr>
+<tr class="ral"><td class="cal">Work area<br><small>(FF_FS_TINY == 1)</small></td><td>V*564<br>+ F*40</td><td>V*564<br>+ F*40</td><td>V*564<br>+ F*40</td><td>V*560<br>+ F*34</td><td>V*560<br>+ F*34</td><td>V*560<br>+ F*34</td><td>V*560<br>+ F*34</td><td>V*564<br>+ F*40</td><td>V*564<br>+ F*40</td><td>V*564<br>+ F*40</td><td>V*564<br>+ F*40</td></tr>
+</table>
+<p>These are the memory usage of FatFs module without lower layer on some target systems in following condition. <em>V</em> denotes number of mounted volumes and <em>F</em> denotes number of open files. Every samples here are optimezed in code size.</p>
+<pre>
+FatFs R0.15 options:
+FF_FS_READONLY   0 (R/W, read/write) or 1 (R/O, read only)
+FF_FS_MINIMIZE   0 (Def, with all basic functions) or 3 (Min, with fully minimized)
+FF_FS_TINY       0 (Default) or 1 (Tiny file object)
+And any other options are left unchanged from original setting.
+</pre>
+</div>
+
+<div class="para doc" id="reduce">
+<h3>Reducing Module Size</h3>
+<p>Follwing table shows which API function is removed by configuration options to reduce the module size. To use an API function, the row of the function must be clear.</p>
+<table class="lst2">
+<tr><td rowspan="2">Function</td><td colspan="4"><a href="config.html#fs_minimize">FF_FS_<br>MINIMIZE</a></td><td colspan="2"><a href="config.html#fs_readonly">FF_FS_<br>READONLY</a></td><td colspan="2"><a href="config.html#use_strfunc">FF_USE_<br>STRFUNC</a></td><td colspan="3"><a href="config.html#fs_rpath">FF_FS_<br>RPATH</a></td><td colspan="2"><a href="config.html#use_find">FF_USE_<br>FIND</a></td><td colspan="2"><a href="config.html#use_chmod">FF_USE_<br>CHMOD</a></td><td colspan="2"><a href="config.html#use_expand">FF_USE_<br>EXPAND</a></td><td colspan="2"><a href="config.html#use_label">FF_USE_<br>LABEL</a></td><td colspan="2"><a href="config.html#use_mkfs">FF_USE_<br>MKFS</a></td><td colspan="2"><a href="config.html#use_forward">FF_USE_<br>FORWARD</a></td><td colspan="2"><a href="config.html#multi_partition">FF_MULTI_<br>PARTITION</a></td></tr>
+<tr>                    <td>0</td><td>1</td><td>2</td><td>3</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>2</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr class="lst3">
+    <td>f_mount</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_open</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_close</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_read</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_write</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_sync</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_lseek</td>    <td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_opendir</td>  <td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_closedir</td> <td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_readdir</td>  <td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_findfirst</td><td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_findnext</td> <td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_stat</td>     <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_getfree</td>  <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_truncate</td> <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_unlink</td>   <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_mkdir</td>    <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_rename</td>   <td> </td><td>x</td><td>x</td><td>x</td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_chdir</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_chdrive</td>  <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_getcwd</td>   <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_chmod</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_utime</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_getlabel</td> <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_setlabel</td> <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_expand</td>   <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_forward</td>  <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_mkfs</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_fdisk</td>    <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td>x</td><td> </td></tr>
+<tr><td>f_putc</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_puts</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_printf</td>   <td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+<tr><td>f_gets</td>     <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>x</td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td></tr>
+</table>
+</div>
+
+<div class="para doc" id="lfn">
+<h3>Long File Name</h3>
+<p>FatFs module supports the long file name (LFN) extension of the FAT filesystem. The two different file names, short file name (SFN) and LFN, of a file is transparent on the API. The support for LFN feature is disabled by default. To enable the LFN, set <tt><a href="config.html#use_lfn">FF_USE_LFN</a></tt> to 1, 2 or 3, and add <tt>ffunicode.c</tt> to the project. The LFN feature requiers a certain working buffer. The buffer size can be configured by <tt><a href="config.html#max_lfn">FF_MAX_LFN</a></tt> according to the available memory. The length of LFN can be up to 255 characters, so that the <tt>FF_MAX_LFN</tt> should be set to 255 for any existing file names. If the size of working buffer is insufficient for the input file name, the file function fails with <tt>FR_INVALID_NAME</tt>. When use any re-entry to the API with LFN feature in RTOS environment, <tt>FF_USE_LFN</tt> must be set to 2 or 3. In this case, the file function allocates the working buffer on the stack or heap. The LFN working buffer occupies <tt>(FF_MAX_LFN + 1) * 2</tt> bytes and additional <tt>(FF_MAX_LFN + 44) / 15 * 32</tt> bytes when exFAT is enabled.</p>
+<h4>Impact upon Module Size</h4>
+<table class="lst2 rset">
+<caption>With LFN at CM3 + gcc</caption>
+<tr><th><tt>FF_CODE_PAGE</tt></th><th>Code size</th></tr>
+<tr><td>437-869 (SBCS)</td><td>+3.3k</td></tr>
+<tr><td>932 (Japanese)</td><td>+62k</td></tr>
+<tr><td>936 (Simplified Chinese)</td><td>+177k</td></tr>
+<tr><td>949 (Korean)</td><td>+140k</td></tr>
+<tr><td>950 (Traditional Chinese)</td><td>+111k</td></tr>
+<tr><td>0 (All code pages)</td><td>+486k</td></tr>
+</table>
+<p>When the LFN is enabled, the module size will be increased depends on the configured code page. Right table shows the increment of code size in some code pages. Especially, in the CJK region, tens of thousands of characters are being used. Unfortunately, it requires a huge OEM-Unicode bidirectional conversion table and the module size will be drastically increased as shown in the table.</p>
+<p>As the result, the FatFs with LFN enabled with DBCS code pages will not able to be ported on the most 8-bit MCU systems. If the target system is in legacy-free, in only Unicode and any ANSI/OEM code is not used at all, the code page setting gets meaningless. You will able to reduce the code size by configureing FatFs for Unicode API with any SBCS code page.</p>
+<p>There ware some restrictions on using LFN for open source project, because the LFN extension on the FAT filesystem was a patent of Microsoft Corporation. However the related patents all have expired and using the LFN feature is free for any projects.</p>
+</div>
+
+<div class="para doc" id="unicode">
+<h3>Unicode API</h3>
+<p>By default, FatFs uses ANSI/OEM code set on the API even in LFN configuration. FatFs can also switch the character encoding on the API to Unicode by configuration option <tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a></tt>. This means that FatFs is compliant with the full featured LFN specification. The data type <tt>TCHAR</tt> specifies path name strings on the API is an alias of either <tt>char</tt>(ANSI/OEM or UTF-8), <tt>WCHAR</tt>(UTF-16) or <tt>DWORD</tt>(UTF-32) depends on that option. For more information, refer to the description in the <a href="filename.html#uni">file name</a>.</p>
+<p>Note that setting of code page, <tt><a href="config.html#code_page">FF_CODE_PAGE</a></tt>, has actually no meaning when FatFs is configured for the Unicode API. It should be set 437 to reduce the module size. However it still affects code conversion of string I/O functions when <tt><a href="config.html#strf_encode">FF_STRF_ENCODE</a> == 0</tt>, and also backward compatibility with legacy systems. In this case, the code page may need to be configured properly if it is considered a problem.</p>
+</div>
+
+<div class="para doc" id="exfat">
+<h3>exFAT Filesystem</h3>
+<p>The exFAT (Microsoft's Extended File Allocation Table) filesystem is a succession of the FAT/FAT32 filesystem which has been widely used in embedded systems, consumer devices and portable storage media. It is adopted by SDA (SD Association) as the filesystem for SDXC card, 64 GB and larger, and they are being shipped with this format. Therefore the exFAT is one of the standard filesystems for removable media as well as FAT. The exFAT filesystem allows the file size beyond the 4 GB limit what FAT filesystem allows up to and some filesystem overhead, especially cluster allocation delay, are reduced as well. These features allow to record the large data without dividing into some files and improve the write throughput to the file.</p>
+<p>Note that the exFAT filesystem is a patent of Microsoft Corporation. The exFAT feature of FatFs is an implementation based on <cite>US. Pat. App. Pub. No. 2009/0164440 A1</cite>. FatFs module can switch the exFAT on or off by a configuration option, <tt><a href="config.html#fs_exfat">FF_FS_EXFAT</a></tt>. When enable the exFAT for the commercial products, a license by Microsoft will be needed depends on the final destination of the products.</p>
+<p><em>Remarks: Enabling exFAT discards C89 compatibility and it wants C99 because of need for 64-bit integer type.</em></p>
+</div>
+
+<div class="para doc" id="lba64">
+<h3>64-bit LBA</h3>
+<p>LBA (Logical Block Addressing) is an addressing method to specify the location of data block, called <em>sector</em>, on the storage media. It is a simple linear address beginning from 0 as the first sector, 1 as the second sector and so on. The host system does not need to consider how the data block is located and managed in the storage device. FatFs supports only LBA for the media access. 32-bit LBA is a common size in the most LBA scheme. It can address up to 2<sup>32</sup> sectors, 2 TB in 512 bytes/sector. When a storage device larger than 2 TB is used, larger sector size or 64-bit LBA will be needed to address the entire sectors of the storage device.</p>
+<p>By default, FatFs works in 32-bit LBA for media access. FatFs can also switch it to 64-bit LBA by a configuration option <tt><a href="config.html#fs_lba64">FF_LBA64</a></tt>. It also enables GPT (GUID Partition Table) for partiotion management on the storage device. For further information about GPT, refer to <tt><a href="mkfs.html">f_mkfs</a></tt> and <tt><a href="fdisk.html">f_fdisk</a></tt> function.</p>
+</div>
+
+<div class="para doc" id="reentrant">
+<h3>Re-entrancy</h3>
+<p>The file operations of two tasks to the <em>different volumes</em> each other is always re-entrant and it can work concurrently without any mutual exclusion regardless of the configurations except when LFN is enabled with static working buffer (<tt>FF_USE_LFN = 1</tt>).</p>
+<p>The file operations of two tasks to the <em>same volume</em> is not thread-safe by default. FatFs can also be configured to make it thread-safe by an option <tt><a href="config.html#fs_reentrant">FF_FS_REENTRANT</a></tt>. When a file function is called while the volume is being accessed by another task, the file function to the volume will be suspended until that task leaves the file function. If the wait time exceeded a period defined by <tt>FF_TIMEOUT</tt>, the file function will abort with <tt>FR_TIMEOUT</tt>. The timeout feature might not be supported on the some OSs. To enable this feature, OS dependent synchronization control functions, <tt>ff_mutex_create/ff_mutex_delete/ff_mutex_take/ff_mutex_give</tt>, need to be added to the project. There is an example code in the <tt>ffsystem.c</tt> for some OSs.</p>
+<p>Note that there is an exception on the re-entrancy for <tt>f_mount</tt> and <tt>f_mkfs</tt> function. You will know why it is. These volume management functions are always not thread-safe to the volume being processed. When use these functions, other tasks need to avoid to access the corresponding volume.</p>
+<div class="rset">
+<table class="lst2">
+<tr><th><tt>Function</tt></th><th>Case 1</th><th>Case 2</th><th>Case 3</th></tr>
+<tr><td>disk_status</td><td>Yes</td><td>Yes</td><td>Yes(*)</td></tr>
+<tr><td>disk_initialize</td><td>No</td><td>Yes</td><td>Yes(*)</td></tr>
+<tr><td>disk_read</td><td>No</td><td>Yes</td><td>Yes(*)</td></tr>
+<tr><td>disk_write</td><td>No</td><td>Yes</td><td>Yes(*)</td></tr>
+<tr><td>disk_ioctl</td><td>No</td><td>Yes</td><td>Yes(*)</td></tr>
+<tr><td>get_fattime</td><td>No</td><td>Yes</td><td>Yes</td></tr>
+</table>
+<small>
+Case 1: Same volume.<br>
+Case 2: Different volume on the same drive.<br>
+Case 3: Different volume on the different drive.<br>
+(*) In only different drive number.
+</small>
+</div>
+<p>Remarks: This section describes on the re-entrancy of the FatFs module itself. The <tt>FF_FS_REENTRANT</tt> option enables only exclusive use of each filesystem objects and FatFs does not that prevent to re-enter the storage device control functions. Thus the device control layer needs to be always thread-safe when FatFs API is re-entered for different volumes. Right table shows which control function can be re-entered when FatFs API is re-entered on some conditions.</p>
+</div>
+
+<div class="para doc" id="dup">
+<h3>Duplicated File Open</h3>
+<p>FatFs module does not support the read/write collision control of duplicated open to a file. The duplicated open is permitted only when each of open method to a file is read mode. The duplicated open with one or more write mode to a file is always prohibited, and also open file must not be renamed or deleted. A violation of these rules can cause data collaption.</p>
+<p>The file lock control can be enabled by <tt><a href="config.html#fs_lock">FF_FS_LOCK</a></tt> option. The value of option defines the number of open objects to manage simultaneously. In this case, if any opening, renaming or removing against the file shareing rule that described above is attempted, the file function will be rejected with <tt>FR_LOCKED</tt>. If number of open objects, files and sub-directories, is equal to <tt>FF_FS_LOCK</tt>, an extra <tt>f_open/f_opendir</tt> function will fail with <tt>FR_TOO_MANY_OPEN_FILES</tt>.</p>
+</div>
+
+<div class="para doc" id="fs1">
+<h3>Performance Effective File Access</h3>
+<p>For good read/write throughput on the small embedded systems with limited size of memory, application programmer should consider what process is done in the FatFs module. The file data on the volume is transferred in following sequence by <tt>f_read</tt> function.</p>
+<p>Figure 1. Sector unaligned read (short)<br>
+<img src="../res/f1.png" width="490" height="110" alt="">
+</p>
+<p>Figure 2. Sector unaligned read (long)<br>
+<img src="../res/f2.png" width="490" height="140" alt="">
+</p>
+<p>Figure 3. Fully sector aligned read<br>
+<img src="../res/f3.png" width="490" height="119" alt="">
+</p>
+<p>The file I/O buffer is a sector buffer to read/write a part of data on the sector. The sector buffer is either file private sector buffer on each file object or shared sector buffer in the filesystem object. The buffer configuration option <tt><a href="config.html#fs_tiny">FF_FS_TINY</a></tt> determins which sector buffer is used for the file data transfer. When tiny buffer configuration (1) is selected, data memory consumption is reduced <tt>FF_MAX_SS</tt> bytes each file object. In this case, FatFs module uses only a sector buffer in the filesystem object for file data transfer and FAT/directory access. The disadvantage of the tiny buffer configuration is: the FAT data cached in the sector buffer will be lost by file data transfer and it must be reloaded at every cluster boundary. However it will be suitable for most application from view point of the decent performance and low memory comsumption.</p>
+<p>Figure 1 shows that a partial sector, sector unaligned part of the file, is transferred via the file I/O buffer. At long data transfer shown in Figure 2, middle of transfer data that covers one or more sector is transferred to the application buffer directly. Figure 3 shows that the case of entier transfer data is aligned to the sector boundary. In this case, file I/O buffer is not used. On the direct transfer, the maximum extent of sectors are read with <tt>disk_read</tt> function at a time but the multiple sector transfer is divided at cluster boundary even if it is contiguous.</p>
+<p>Therefore taking effort to sector aligned read/write accesss eliminates buffered data transfer and the read/write performance will be improved. Besides the effect, cached FAT data will not be flushed by file data transfer at the tiny configuration, so that it can achieve same performance as non-tiny configuration with small memory footprint.</p>
+</div>
+
+<div class="para doc" id="fs2">
+<h3>Considerations on Flash Memory Media</h3>
+<p>To maximize the write performance of flash memory media, such as SDC, CFC and U Disk, it must be controlled in consideration of its characteristitcs.</p>
+<h4>Using Mutiple-Sector Write</h4>
+<div class="rset">
+Figure 6. Comparison between Multiple/Single Sector Write<br>
+<img src="../res/f6.png" width="630" height="148" alt="fig.6">
+</div>
+<p>The write throughput of the flash memory media becomes the worst at single sector write transaction. The write throughput increases as the number of sectors per a write transaction as shown in Figure 6. This effect more appers at faster interface speed and the performance ratio often becomes grater than ten. <a href="../res/rwtest2.png">This result</a> is clearly explaining how fast is multiple block write (W:16K, 32 sectors) than single block write (W:100, 1 sector), and also larger card tends to be slow at single block write. Number of write transactions also affects life time of the flash memory media. When compared at same amount of write data, the single sector write in Figure 6 above wears flash memory media 16 times more than multiple sector write in Figure 6 below. Single sector write is pretty pain for the flash memory media.</p>
+<p>Therefore the application program should write the data in large block as possible. The ideal write chunk size and alighment is size of sector, and size of cluster is the best. Of course all layers between the application and the storage device must have consideration on multiple sector write, however most of open-source memory card drivers lack it. Do not split a multiple sector write request into single sector write transactions or the write throughput gets poor. Note that FatFs module and its sample disk drivers supprt multiple sector read/write operation. </p>
+<h4>Forcing Memory Erase</h4>
+<p>When remove a file with <tt>f_unlink</tt> function, the data clusters occupied by the file are marked 'free' on the FAT. But the data sectors containing the file data are not that applied any process, so that the file data left occupies a part of the flash memory array as 'live block'. If the file data can be erased on removing the file, those data blocks will be turned into the free block pool. This may skip internal block erase operation to the data block on next write operation. As the result the write performance might be improved. FatFs can manage this function by setting <tt><a href="config.html#use_trim">FF_USE_TRIM</a></tt> to 1. Note that because this effect is from an expectation of internal process of the storage device, it is not that always effective. Most applications will not need this function. Also <tt>f_unlink</tt> function can take a time when remove a large file.</p>
+</div>
+
+<div class="para doc" id="critical">
+<h3>Critical Section</h3>
+<p>If a write operation to the FAT volume is interrupted due to an accidental failure, such as sudden blackout, wrong media removal and unrecoverable disk error, the FAT structure on the volume can be broken. Following images shows the critical section of the FatFs module.</p>
+<div class="lset">
+Figure 4. Long critical section<br>
+<img src="../res/f4.png" width="320" height="436" alt="fig.4">
+</div>
+<div class="lset">
+Figure 5. Minimized critical section<br>
+<img src="../res/f5.png" width="320" height="436" alt="fig.5">
+</div>
+<br class="clr">
+<p>An interruption in the red section can cause a cross link; as a result, the object being changed can be lost. If an interruption in the yellow section is occured, there is one or more possibility listed below.</p>
+<ul>
+<li>The file data being rewrited is collapsed.</li>
+<li>The file being appended returns initial state.</li>
+<li>The file created as new is gone.</li>
+<li>The file created as new or overwritten remains but no content.</li>
+<li>Efficiency of disk use gets worse due to lost clusters.</li>
+</ul>
+<p>Each case does not affect any file not opened in write mode. To minimize risk of data loss, the critical section can be minimized by minimizing the time that file is opened in write mode or using <tt>f_sync</tt> function as shown in Figure 5.</p>
+</div>
+
+<div class="para doc" id="fs3">
+<h3>Various Usable Functions for FatFs Projects</h3>
+<p>These are examples of extended use of FatFs APIs. New item will be added when useful code example is found.</p>
+<ol>
+<li><a href="http://elm-chan.org/fsw/ff/res/app1.c">Open or Create File for Append</a> (superseded by FA_OPEN_APPEND flag added at R0.12)</li>
+<li><a href="http://elm-chan.org/fsw/ff/res/app2.c">Delete Non-empty Sub-directory</a> (for R0.12 and later)</li>
+<li><a href="http://elm-chan.org/fsw/ff/res/app3.c">Create Contiguous File</a> (superseded by f_expand function added at R0.12)</li>
+<li><a href="http://elm-chan.org/fsw/ff/res/app5.c">Test if the File is Contiguous or Not</a></li>
+<li><a href="http://elm-chan.org/fsw/ff/res/app4.c">Compatibility Checker for Storage Device Control Module</a></li>
+<li><a href="http://elm-chan.org/fsw/ff/res/app6.c">Performance Checker for Storage Device Control Module</a></li>
+<li><a href="http://elm-chan.org/fsw/ff/res/mkfatimg.zip">FAT Volume Image Creator</a> (Pre-creating built-in FAT volume)</li>
+<li>Virtual Drive Feature (refer to lpc176x/ in <a href="../ffsample.zip">ffsample.zip</a>)</li>
+<li><a href="http://elm-chan.org/fsw/ff/res/uniconv.zip">Embedded Unicode String Utilities</a> (OEMxxx→Unicode, Unicode→OEMxxx, Unicode→Unicode)</li>
+</ol>
+</div>
+
+<div class="para doc" id="license">
+<h3>About FatFs License</h3>
+<p>FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that included in the source files.</p>
+<pre>
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  Rx.xx                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 20xx, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+</pre>
+<p>Therefore FatFs license is one of the BSD-style licenses but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, does not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses includes GNU GPL. When you redistribute the FatFs source code with any changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that compatible with FatFs license.</p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return Home</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/chdir.html b/MCUME_pico2/fatfs/documents/doc/chdir.html
new file mode 100644
index 0000000..93e116c
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/chdir.html
@@ -0,0 +1,88 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/chdir.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_chdir</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_chdir</h2>
+<p>The <tt>f_chdir</tt> function changes the current directory of the logical drive.</p>
+<pre>
+FRESULT f_chdir (
+  const TCHAR* <span class="arg">path</span> <span class="c">/* [IN] Path name */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">directory</a> to be set as current directory.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_chdir</tt> function changes the current directory of the logical drive. Also the current drive will be changed when in Unix style drive prefix, <tt><a href="config.html#str_volume_id">FF_STR_VOLUME_ID</a> == 2</tt>. The current directory of each logical drive is initialized to the root directory on mount.</p>
+<p>Note that the current directory is retained in the each file system object and the current drive is retained in a static variable, so that it also affects other tasks that use the file functions.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_rpath">FF_FS_RPATH</a> &gt;= 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Change current direcoty of the current drive ("dir1" under root directory) */</span>
+    <em>f_chdir</em>("/dir1");
+
+    <span class="c">/* Change current direcoty of current drive (parent directory of drive 2) */</span>
+    <em>f_chdir</em>("2:..");
+
+    <span class="c">/* Change current direcoty of the drive "sdcard" (at DOS/Windows style volume ID) */</span>
+    <em>f_chdir</em>("sdcard:/dir1");
+
+    <span class="c">/* Change current direcoty of the drive "flash" and set it as current drive (at Unix style volume ID) */</span>
+    <em>f_chdir</em>("/flash/dir1");
+</pre>
+</div>
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="chdrive.html">f_chdrive</a>, <a href="getcwd.html">f_getcwd</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/chdrive.html b/MCUME_pico2/fatfs/documents/doc/chdrive.html
new file mode 100644
index 0000000..4dfc7d8
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/chdrive.html
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/chdrive.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_chdrive</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_chdrive</h2>
+<p>The f_chdrive function changes the current drive.</p>
+<pre>
+FRESULT f_chdrive (
+  const TCHAR* <span class="arg">path</span>  <span class="c">/* [IN] Logical drive number */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Specifies the <a href="filename.html">logical drive number</a> to be set as the current drive.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_chdrive</tt> function changes only the current drive. The initial value of the current drive number is 0. In Unix style drive prefix configuration, this function will not be needed because <tt>f_chdir</tt> function changes also the current drive. Note that the current drive is retained in a static variable, so that it also affects other tasks that using the file functions.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_rpath">FF_FS_RPATH</a> &gt;= 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <em>f_chdrive</em>("2:");  <span class="c">/* Set drive 2 as current drive */</span>
+
+    <em>f_chdrive</em>("");    <span class="c">/* No effect (set current drive as current drive) */</span>
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="chdir.html">f_chdir</a>, <a href="getcwd.html">f_getcwd</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/chmod.html b/MCUME_pico2/fatfs/documents/doc/chmod.html
new file mode 100644
index 0000000..91e520f
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/chmod.html
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/chmod.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_chmod</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_chmod</h2>
+<p>The f_chmod function changes the attribute of a file or sub-directory.</p>
+<pre>
+FRESULT f_chmod (
+  const TCHAR* <span class="arg">path</span>, <span class="c">/* [IN] Object name */</span>
+  BYTE <span class="arg">attr</span>,         <span class="c">/* [IN] Attribute flags */</span>
+  BYTE <span class="arg">mask</span>          <span class="c">/* [IN] Attribute masks */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies an <a href="filename.html">object</a> to be changed</dd>
+<dt>attr</dt>
+<dd>Attribute flags to be set in one or more combination of the following flags. The specified flags are set and others are cleard.<br>
+<table class="lst">
+<tr><th>Attribute</th><th>Description</th></tr>
+<tr><td>AM_RDO</td><td>Read only</td></tr>
+<tr><td>AM_ARC</td><td>Archive</td></tr>
+<tr><td>AM_SYS</td><td>System</td></tr>
+<tr><td>AM_HID</td><td>Hidden</td></tr>
+</table>
+</dd>
+<dt>mask</dt>
+<dd>Attribute mask that specifies which attribute is changed. The specified attributes are set or cleard and others are left unchanged.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ok">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_chmod</tt> function changes the attribute of a file or sub-directory.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_chmod">FF_USE_CHMOD</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Set Read-only, clear Archive and others are left unchanged. */</span>
+    <em>f_chmod</em>("file.txt", AM_RDO, AM_RDO | AM_ARC);
+</pre>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/close.html b/MCUME_pico2/fatfs/documents/doc/close.html
new file mode 100644
index 0000000..f4cd2df
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/close.html
@@ -0,0 +1,65 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/close.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_close</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_close</h2>
+<p>The f_close function closes an open file.</p>
+<pre>
+FRESULT f_close (
+  FIL* <span class="arg">fp</span>     <span class="c">/* [IN] Pointer to the file object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure to be closed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_close</tt> function closes an open file object. If the file has been changed, the cached information of the file is written back to the volume. After the function succeeded, the file object is no longer valid and it can be discarded.</p>
+<p>Note that if the file object is in read-only mode and <tt>FF_FS_LOCK</tt> is not enabled, the file object can also be discarded without this procedure. However this is not recommended for future compatibility.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="read.html">f_read</a>, <a href="write.html">f_write</a>,  <a href="sync.html">f_sync</a>, <a href="sfile.html">FIL</a>, <a href="sfatfs.html">FATFS</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/closedir.html b/MCUME_pico2/fatfs/documents/doc/closedir.html
new file mode 100644
index 0000000..3f5df57
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/closedir.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/close.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_closedir</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_closedir</h2>
+<p>The f_closedir function closes an open directory.</p>
+<pre>
+FRESULT f_closedir (
+  DIR* <span class="arg">dp</span>     <span class="c">/* [IN] Pointer to the directory object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>dp</dt>
+<dd>Pointer to the open directory object structure to be closed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_closedir</tt> function closes an open directory object. After the function succeeded, the directory object is no longer valid and it can be discarded.</p>
+<p>Note that the directory object can also be discarded without this procedure when option <tt>FF_FS_LOCK</tt> is not enabled. However this is not recommended for future compatibility.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 1</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="opendir.html">f_opendir</a>, <a href="readdir.html">f_readdir</a>, <a href="sdir.html">DIR</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/config.html b/MCUME_pico2/fatfs/documents/doc/config.html
new file mode 100644
index 0000000..788e075
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/config.html
@@ -0,0 +1,304 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/config.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - Configuration Options</title>
+</head>
+
+<body>
+<h1>Configuration Options</h1>
+<p>There are many options to configure the features of FatFs for various requirements of each project. The configuration options are defined in <em><tt>ffconf.h</tt></em>.</p>
+<ul>
+<li>Function Configurations
+ <ul>
+   <li><a href="#fs_readonly">FF_FS_READONLY</a></li>
+   <li><a href="#fs_minimize">FF_FS_MINIMIZE</a></li>
+   <li><a href="#use_find">FF_USE_FIND</a></li>
+   <li><a href="#use_mkfs">FF_USE_MKFS</a></li>
+   <li><a href="#use_fastseek">FF_USE_FASTSEEK</a></li>
+   <li><a href="#use_expand">FF_USE_EXPAND</a></li>
+   <li><a href="#use_chmod">FF_USE_CHMOD</a></li>
+   <li><a href="#use_label">FF_USE_LABEL</a></li>
+   <li><a href="#use_forward">FF_USE_FORWARD</a></li>
+   <li><a href="#use_strfunc">FF_USE_STRFUNC</a></li>
+   <li><a href="#print_lli">FF_PRINT_LLI</a></li>
+   <li><a href="#print_fp">FF_PRINT_FLOAT</a></li>
+   <li><a href="#strf_encode">FF_STRF_ENCODE</a></li>
+ </ul>
+</li>
+<li>Namespace and Locale Configurations
+ <ul>
+   <li><a href="#code_page">FF_CODE_PAGE</a></li>
+   <li><a href="#use_lfn">FF_USE_LFN</a></li>
+   <li><a href="#max_lfn">FF_MAX_LFN</a></li>
+   <li><a href="#lfn_unicode">FF_LFN_UNICODE</a></li>
+   <li><a href="#lfn_buf">FF_LFN_BUF, FF_SFN_BUF</a></li>
+   <li><a href="#fs_rpath">FF_FS_RPATH</a></li>
+ </ul>
+</li>
+<li>Volume/Drive Configurations
+ <ul>
+   <li><a href="#volumes">FF_VOLUMES</a></li>
+   <li><a href="#str_volume_id">FF_STR_VOLUME_ID</a></li>
+   <li><a href="#volume_strs">FF_VOLUME_STRS</a></li>
+   <li><a href="#multi_partition">FF_MULTI_PARTITION</a></li>
+   <li><a href="#max_ss">FF_MIN_SS, FF_MAX_SS</a></li>
+   <li><a href="#fs_lba64">FF_LBA64</a></li>
+   <li><a href="#fs_gptmin">FF_GPT_MIN</a></li>
+   <li><a href="#use_trim">FF_USE_TRIM</a></li>
+ </ul>
+</li>
+<li>System Configurations
+ <ul>
+   <li><a href="#fs_tiny">FF_FS_TINY</a></li>
+   <li><a href="#fs_exfat">FF_FS_EXFAT</a></li>
+   <li><a href="#fs_nortc">FF_FS_NORTC</a></li>
+   <li><a href="#nortc_time">FF_NORTC_MON, FF_NORTC_MDAY, FF_NORTC_YEAR</a></li>
+   <li><a href="#fs_nofsinfo">FF_FS_NOFSINFO</a></li>
+   <li><a href="#fs_lock">FF_FS_LOCK</a></li>
+   <li><a href="#fs_reentrant">FF_FS_REENTRANT</a></li>
+   <li><a href="#fs_timeout">FF_FS_TIMEOUT</a></li>
+   <li><a href="#sync_t">FF_SYNC_t</a></li>
+ </ul>
+</li>
+</ul>
+
+<div class="para doc" id="func">
+<h3>Function Configurations</h3>
+
+<h4 id="fs_readonly">FF_FS_READONLY</h4>
+<p>Read/Write (0) or Read-only (1). Read-only configuration removes writing API functions, <tt>f_write</tt>, <tt>f_sync</tt>, <tt>f_unlink</tt>, <tt>f_mkdir</tt>, <tt>f_chmod</tt>, <tt>f_rename</tt>, <tt>f_truncate</tt>, <tt>f_getfree</tt> and optional writing functions as well.</p>
+
+<h4 id="fs_minimize">FF_FS_MINIMIZE</h4>
+<p>This option defines minimization level to remove some basic API functions as follows:</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>All basic API functions are available.</td></tr>
+<tr><td>1</td><td><tt>f_stat</tt>, <tt>f_getfree</tt>, <tt>f_unlink</tt>, <tt>f_mkdir</tt>, <tt>f_chmod</tt>, <tt>f_utime</tt>, <tt>f_truncate</tt> and <tt>f_rename</tt> function are removed.</td></tr>
+<tr><td>2</td><td><tt>f_opendir</tt>, <tt>f_readdir</tt> and <tt>f_closedir</tt> function are removed in addition to 1.</td></tr>
+<tr><td>3</td><td><tt>f_lseek</tt> function is removed in addition to 2.</td></tr>
+</table>
+
+<h4 id="use_find">FF_USE_FIND</h4>
+<p>Disable (0) or Enable (1) filtered directory read functions, <tt>f_findfirst</tt> and <tt>f_findnext</tt>. Also <tt>FF_FS_MINIMIZE</tt> needs to be 0 or 1.</p>
+
+<h4 id="use_mkfs">FF_USE_MKFS</h4>
+<p>Disable (0) or Enable (1) <tt>f_mkfs</tt> function.</p>
+
+<h4 id="use_fastseek">FF_USE_FASTSEEK</h4>
+<p>Disable (0) or Enable (1) fast seek function to enable accelerated mode for <tt>f_lseek</tt>, <tt>f_read</tt> and <tt>f_write</tt> function. For more information, read <a href="lseek.html">here</a>.</p>
+
+<h4 id="use_expand">FF_USE_EXPAND</h4>
+<p>Disable (0) or Enable (1) <tt>f_expand</tt> function.</p>
+
+<h4 id="use_chmod">FF_USE_CHMOD</h4>
+<p>Disable (0) or Enable (1) metadata control functions, <tt>f_chmod</tt> and <tt>f_utime</tt>. Also <tt>FF_FS_READONLY</tt> needs to be 0.</p>
+
+<h4 id="use_label">FF_USE_LABEL</h4>
+<p>Disable (0) or Enable (1) API functions for volume label, <tt>f_getlabel</tt> and <tt>f_setlabel</tt>.</p>
+
+<h4 id="use_forward">FF_USE_FORWARD</h4>
+<p>Disable (0) or Enable (1) <tt>f_forward</tt> function.</p>
+
+<h4 id="use_strfunc">FF_USE_STRFUNC</h4>
+<p>This option switches string functions, <tt>f_gets</tt>, <tt>f_putc</tt>, <tt>f_puts</tt> and <tt>f_printf</tt>. These functions are equivalents of regular string stream I/O functions in POSIX. If <tt>sprintf</tt> is available and code conversion is not needed, <tt>f_write</tt> with <tt>sprintf</tt> will be efficient in code size and performance rather than <tt>f_printf</tt>. When enable this feature, <tt>stdarg.h</tt> is included in <tt>ff.c</tt>.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>Disable string functions.</td></tr>
+<tr><td>1</td><td>Enable string functions without LF-CRLF conversion.</td></tr>
+<tr><td>2</td><td>Enable string functions with LF-CRLF conversion.</td></tr>
+</table>
+
+<h4 id="print_lli">FF_PRINT_LLI</h4>
+<p>This option switches support for long long integer argument in <tt>f_printf</tt>.</p>
+<p>Disable (0) or Enable (1). When enable this feature, C standard needs to be C99 or later.</p>
+
+<h4 id="print_fp">FF_PRINT_FLOAT</h4>
+<p>This option switches support for floating point argument in <tt>f_printf</tt>. When enable this feature, C standard needs to be C99 or later and <tt>math.h</tt> is included in <tt>ff.c</tt>.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>Disable floating point argument.</td></tr>
+<tr><td>1</td><td>Enable floating point argument in type <tt>'f'</tt>, <tt>'e'</tt> and <tt>'E'</tt>.</td></tr>
+<tr><td>2</td><td>Enable it with decimal separator <tt>','</tt> instead of <tt>'.'</tt>.</td></tr>
+</table>
+
+<h4 id="strf_encode">FF_STRF_ENCODE</h4>
+<p>When character encoding on the API is Unicode (<tt>FF_LFN_UNICODE &gt;= 1</tt>), string I/O functions enabled by <tt>FF_USE_STRFUNC</tt> convert the character encoding in it. This option defines the assumption of character encoding <em>on the file</em> to be read/written via those functions. When LFN is not enabled or <tt>FF_LFN_UNICODE == 0</tt>, the string functions work without any code conversion and this option has no effect.</p>
+<table class="lst2">
+<tr><th>Value</th><th>Character encoding on the file</th></tr>
+<tr><td>0</td><td>ANSI/OEM in current code page</td></tr>
+<tr><td>1</td><td>Unicode in UTF-16LE</td></tr>
+<tr><td>2</td><td>Unicode in UTF-16BE</td></tr>
+<tr><td>3</td><td>Unicode in UTF-8</td></tr>
+</table>
+
+</div>
+
+
+<div class="para doc" id="name">
+<h3>Namespace and Locale Configurations</h3>
+
+<h4 id="code_page">FF_CODE_PAGE</h4>
+<p>This option specifies the OEM code page used on the target system. Incorrect setting of the code page can cause a file open failure. If any non-ASCII character is not used for the path name or <tt>FF_LFN_UNICODE != 0</tt>, there is no difference between any code page settings. Set it 437 anyway.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Code page</th></tr>
+<tr><td>0</td><td>Includes all code pages below and set by <tt>f_setcp()</tt></td></tr>
+<tr><td>437</td><td>U.S.</td></tr>
+<tr><td>720</td><td>Arabic</td></tr>
+<tr><td>737</td><td>Greek</td></tr>
+<tr><td>771</td><td>KBL</td></tr>
+<tr><td>775</td><td>Baltic</td></tr>
+<tr><td>850</td><td>Latin 1</td></tr>
+<tr><td>852</td><td>Latin 2</td></tr>
+<tr><td>855</td><td>Cyrillic</td></tr>
+<tr><td>857</td><td>Turkish</td></tr>
+<tr><td>860</td><td>Portuguese</td></tr>
+<tr><td>861</td><td>Icelandic</td></tr>
+<tr><td>862</td><td>Hebrew</td></tr>
+<tr><td>863</td><td>Canadian French</td></tr>
+<tr><td>864</td><td>Arabic</td></tr>
+<tr><td>865</td><td>Nordic</td></tr>
+<tr><td>866</td><td>Russian</td></tr>
+<tr><td>869</td><td>Greek 2</td></tr>
+<tr><td>932</td><td>Japanese (DBCS)</td></tr>
+<tr><td>936</td><td>Simplified Chinese (DBCS)</td></tr>
+<tr><td>949</td><td>Korean (DBCS)</td></tr>
+<tr><td>950</td><td>Traditional Chinese (DBCS)</td></tr>
+</table>
+
+<h4 id="use_lfn">FF_USE_LFN</h4>
+<p>This option switches the support for long file name (LFN). When enable the LFN, Unicode support module <tt>ffunicode.c</tt> need to be added to the project. When use stack for the working buffer, take care on stack overflow. When use heap memory for the working buffer, memory management functions (<tt>ff_memalloc</tt> and <tt>ff_memfree</tt>) need to be added to the project.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>Disable LFN. Path name in only 8.3 format can be used.</td></tr>
+<tr><td>1</td><td>Enable LFN with static working buffer on the BSS. Always NOT thread-safe.</td></tr>
+<tr><td>2</td><td>Enable LFN with dynamic working buffer on the STACK.</td></tr>
+<tr><td>3</td><td>Enable LFN with dynamic working buffer on the HEAP.</td></tr>
+</table>
+
+<h4 id="max_lfn">FF_MAX_LFN</h4>
+<p>LFN function requiers certain internal working buffer for the file name. This option defines size of the buffer and the value can be in range of 12 to 255 characters (actually in UTF-16 code units) of the LFN. The buffer occupies <tt>(FF_MAX_LFN + 1) * 2</tt> bytes and additional <tt>(FF_MAX_LFN + 44) / 15 * 32</tt> bytes when exFAT is enabled. It is recommended to be set 255 to fully support the LFN specification. This option has no effect when LFN is not enabled.</p>
+
+<h4 id="lfn_unicode">FF_LFN_UNICODE</h4>
+<p>This option switches character encoding for the file name on the API. FatFs supports the code point up to U+10FFFF. This option also affects behavior of string I/O functions (see <tt>FF_STRF_ENCODE</tt>).</p>
+<table class="lst2">
+<tr><th>Value</th><th>Character Encoding</th><th><tt>TCHAR</tt></th></tr>
+<tr><td>0</td><td>ANSI/OEM in current CP</td><td>char</td></tr>
+<tr><td>1</td><td>Unicode in UTF-16</td><td>WCHAR</td></tr>
+<tr><td>2</td><td>Unicode in UTF-8</td><td>char</td></tr>
+<tr><td>3</td><td>Unicode in UTF-32</td><td>DWORD</td></tr>
+</table>
+<p>When Unicode is selected, <tt>FF_CODE_PAGE</tt> has actually no meaning except for compatibility with legacy systems, such as MS-DOS and any system without support for LFN.</p>
+<p>When LFN is not enabled, this option has no effect and FatFs works in ANSI/OEM code on the API. For more information, read <a href="filename.html#uni">here</a>.</p>
+
+<h4 id="lfn_buf">FF_LFN_BUF, FF_SFN_BUF</h4>
+<p>This set of options defines size of file name members, <tt>fname[]</tt> and <tt>altname[]</tt>, in the <tt><a href="sfileinfo.html">FILINFO</a></tt> structure which is used to read out the directory items. These values should be suffcient for the file names to read. The maximum possible length of read file name depends on the character encoding scheme on the API as follows:</p>
+<table class="lst2">
+<tr><th>Encoding</th><th>LFN length</th><th>SFN length</th></tr>
+<tr><td>ANSI/OEM in SBCS</td><td>255 items</td><td>12 items</td></tr>
+<tr><td>ANSI/OEM in DBCS</td><td>510 items</td><td>12 items</td></tr>
+<tr><td>Unicode in UTF-16/32</td><td>255 items</td><td>12 items</td></tr>
+<tr><td>Unicode in UTF-8</td><td>765 items</td><td>34 items</td></tr>
+</table>
+<p>If the size of name member is insufficient for the LFN, the item is treated as without LFN. When LFN is not enabled, these options have no effect.</p>
+
+<h4 id="fs_rpath">FF_FS_RPATH</h4>
+<p>This option configures relative path function. For more information, read <a href="filename.html#nam">here</a>.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>Disable relative path and remove related functions.</td></tr>
+<tr><td>1</td><td>Enable relative path. <tt>f_chdir</tt> and <tt>f_chdrive</tt> function is available.</td></tr>
+<tr><td>2</td><td><tt>f_getcwd</tt> function is available in addition to 1</td></tr>
+</table>
+
+</div>
+
+
+<div class="para doc" id="volume">
+<h3>Volume/Drive Configurations</h3>
+
+<h4 id="volumes">FF_VOLUMES</h4>
+<p>This option configures number of volumes (logical drives up to 10) to be used.</p>
+
+<h4 id="str_volume_id">FF_STR_VOLUME_ID</h4>
+<p>This option switches the support for string volume ID. When arbitrary string for the volume ID is enabled for the drive prefix, also pre-defined strings by <tt>FF_VOLUME_STRS</tt> or user defined strings can be used as drive prefix in the path name. Numeric drive number is always valid regardless of this option, and also either format of drive prefix can be enabled by this option.</p>
+<table class="lst2">
+<tr><th>Value</th><th>Description</th><th>Example</th></tr>
+<tr><td>0</td><td>Only DOS/Windows style drive prefix in numeric ID can be used.</td><td>1:/filename</td></tr>
+<tr><td>1</td><td>Also DOS/Windows style drive prefix in string ID can be used.</td><td>flash:/filename</td></tr>
+<tr><td>2</td><td>Also Unix style drive prefix in string ID can be used.</td><td>/flash/filename</td></tr>
+</table>
+
+<h4 id="volume_strs">FF_VOLUME_STRS</h4>
+<p>This option defines the volume ID strings for each logical drives. Number of items must not be less than <tt>FF_VOLUMES</tt>. Valid characters for the volume ID string are A-Z, a-z and 0-9, however, they are compared in case-insensitive. If <tt>FF_STR_VOLUME_ID == 0</tt>, this option has no effect. If <tt>FF_STR_VOLUME_ID &gt;= 1</tt> and this option is not defined, a user defined volume string table needs to be defined as shown below. The table should not be modified on the fly.</p>
+<pre>
+<span class="c">/* User defined volume ID strings for 0: to 3: */</span>
+const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb"};
+</pre>
+
+<h4 id="multi_partition">FF_MULTI_PARTITION</h4>
+<p>Disable (0) or Enable (1). This option switches multi-partition function. By default (0), each logical drive number is bound to the same physical drive number and only a volume in the physical drive is mounted. When enabled, each logical drive is bound to the partition on the physical drive listed in the user defined partition resolution table <tt>VolToPart[]</tt>. Also <tt>f_fdisk</tt> funciton will be available. For more information, read <a href="filename.html#vol">here</a>.</p>
+
+<h4 id="max_ss">FF_MIN_SS, FF_MAX_SS</h4>
+<p>This set of options defines the extent of sector size used for the low level disk I/O interface, <tt>disk_read</tt> and <tt>disk_write</tt> function. Valid values are 512, 1024, 2048 and 4096. <tt>FF_MIN_SS</tt> defines minimum sector size and <tt>FF_MAX_SS</tt> defines the maximum sector size. Always set both 512 for memory card and harddisk. But a larger value may be required for on-board flash memory and some type of optical media. When <tt>FF_MAX_SS &gt; FF_MIN_SS</tt>, support of variable sector size is enabled and <tt>GET_SECTOR_SIZE</tt> command needs to be implemented to the <tt>disk_ioctl</tt> function.</p>
+
+<h4 id="fs_lba64">FF_LBA64</h4>
+<p>This option switches media access interface to 64-bit LBA and enables GUID Partition Table (GPT) for partition management, Enabled (1) or Disabled (0). exFAT filesystem needs to be enabled to enable this feature.</p>
+
+<h4 id="fs_gptmin">FF_MIN_GPT</h4>
+<p>This option specifies the threshold of determination of partitioning format when create patitions on the drive in <tt>f_mkfs</tt> and <tt>f_fdisk</tt> function. When number of available sectors is equal or larger than this value, the drive will be partitioned in GPT. This option has no effect when <tt>FF_LBA64 == 0</tt>.</p>
+
+<h4 id="use_trim">FF_USE_TRIM</h4>
+<p>Disable (0) or Enable (1). This option switches ATA-TRIM function. To enable Trim function, also <tt>CTRL_TRIM</tt> command should be implemented to the <tt>disk_ioctl</tt> function.</p>
+
+</div>
+
+
+<div class="para doc" id="system">
+<h3>System Configurations</h3>
+
+<h4 id="fs_tiny">FF_FS_TINY</h4>
+<p>Normal (0) or Tiny (1). The tiny configuration reduces size of the <tt>FIL</tt> structure, file object, <tt>FF_MAX_SS</tt> bytes each. Instead of private sector buffer eliminated from the file object, common sector buffer in the <tt>FATFS</tt> structure, filesystem object, is used for the file data transfer.</p>
+
+<h4 id="fs_exfat">FF_FS_EXFAT</h4>
+<p>This option switches support for exFAT filesystem in addition to the FAT/FAT32 filesystem, Enabled (1) or Disabled (0). To enable exFAT, also LFN must be enabled and configureing <tt>FF_LFN_UNICODE &gt;= 1</tt> and <tt>FF_MAX_LFN == 255</tt> is recommended for full-featured exFAT function. Note that enabling exFAT discards ANSI C (C89) compatibility and wants C99 because of need for 64-bit integer type.</p>
+
+<h4 id="fs_nortc">FF_FS_NORTC</h4>
+<p>Use RTC (0) or Do not use RTC (1). This option controls timestamp featuer. If the system does not have an RTC or valid timestamp is not needed, set <tt>FF_FS_NORTC</tt> to 1 to disable the timestamp function. Every objects modified by FatFs will have a constant timestamp defined by <tt>FF_NORTC_MON</tt>, <tt>FF_NORTC_MDAY</tt> and <tt>FF_NORTC_YEAR</tt>. To use the timestamp featuer, set <tt>FF_FS_NORTC == 0</tt> and add <tt>get_fattime</tt> function to the project to get current time form the RTC. This option has no effect in read-only configuration.</p>
+
+<h4 id="nortc_time">FF_NORTC_MON, FF_NORTC_MDAY, FF_NORTC_YEAR</h4>
+<p>This set of options defines the time to be used in no RTC systems. This option has no effect in read-only configuration or <tt>FF_FS_NORTC == 0</tt>.</p>
+
+<h4 id="fs_nofsinfo">FF_FS_NOFSINFO</h4>
+<p>0 to 3. If you need to know correct free space on the FAT32 volume, set bit 0 of this option, and <tt>f_getfree</tt> function at first time after the volume mounted will force a full FAT scan. Bit 1 controls the use of last allocated cluster number for new allocation.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>bit0=0</td><td>Use free cluster count in the FSINFO if available.</td></tr>
+<tr><td>bit0=1</td><td>Do not trust free cluster count in the FSINFO.</td></tr>
+<tr><td>bit1=0</td><td>Use last allocated cluster number in the FSINFO to find a free cluster if available.</td></tr>
+<tr><td>bit1=1</td><td>Do not trust last allocated cluster number in the FSINFO.</td></tr>
+</table>
+
+<h4 id="fs_lock">FF_FS_LOCK</h4>
+<p>This option switches file lock feature to control duplicated file open and illegal operations to the open objects. Note that this feature is independent of re-entrancy. This option must be 0 in read-only configuration.</p>
+<table class="lst1">
+<tr><th>Value</th><th>Description</th></tr>
+<tr><td>0</td><td>Disable file lock feature. To avoid to collapse files due to wrong file operations, application program needs to avoid illegal open, remove and rename to the open objects.</td></tr>
+<tr><td>&gt;0</td><td>Enable file lock feature. The value defines how many files/sub-directories can be opened simultaneously under the file lock feature. Illigal operations to the open object will be rejected with <tt>FR_LOCKED</tt>.</td></tr>
+</table>
+
+<h4 id="fs_reentrant">FF_FS_REENTRANT</h4>
+<p>Disable (0) or Enable (1). This option switches the re-entrancy (thread safe) of the FatFs module itself. Note that file/directory access to the different volume is always re-entrant and it can work simultaneously regardless of this option, however, volume management functions, <tt>f_mount</tt>, <tt>f_mkfs</tt> and <tt>f_fdisk</tt>, are <em>always not re-entrant</em>. Only file/directory access to the same volume, in other words, exclusive use of each filesystem object, is under control in this feature. To enable this feature, also user provided synchronization handlers, <tt>ff_mutex_take</tt>, <tt>ff_mutex_give</tt>, <tt>ff_mutex_create</tt> and <tt>ff_mutex_delete</tt>, need to be added to the project. Sample code is available in <tt>ffsystem.c</tt>.</p>
+
+<h4 id="fs_timeout">FF_FS_TIMEOUT</h4>
+<p>Number of O/S time ticks to abort the file function with <tt>FR_TIMEOUT</tt> when the wait time exceeds this period. This option has no effect when <tt>FF_FS_REENTRANT == 0</tt>.</p>
+
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
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@@ -0,0 +1,46 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/dinit.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - disk_initialize</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>disk_initialize</h2>
+<p>The disk_initialize function is called to initializes the storage device.</p>
+<pre>
+DSTATUS disk_initialize (
+  BYTE <span class="arg">pdrv</span>           <span class="c">/* [IN] Physical drive number */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Physical drive number to identify the target device. Always zero at single drive system.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>This function returns the current drive status flags as the result. For details of the drive status, refer to the <a href="dstat.html">disk_status</a> function.</p>
+</div>
+
+<div class="para desc">
+<h4>Description</h4>
+<p>This function initializes the storage device and put it ready to generic read/write. When the function succeeded, <tt>STA_NOINIT</tt> flag in the return value is cleared.</p>
+<p><em>Remarks: This function needs to be under control of FatFs module. Application program MUST NOT call this function while FatFs is in use, or FAT structure on the volume can be broken. To re-initialize the filesystem, use <tt>f_mount</tt> function instead.</em></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/dioctl.html b/MCUME_pico2/fatfs/documents/doc/dioctl.html
new file mode 100644
index 0000000..fc5f24c
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/dioctl.html
@@ -0,0 +1,101 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/dioctl.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - disk_ioctl</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>disk_ioctl</h2>
+<p>The disk_ioctl function is called to control device specific features and miscellaneous functions other than generic read/write.</p>
+<pre>
+DRESULT disk_ioctl (
+  BYTE <span class="arg">pdrv</span>,     <span class="c">/* [IN] Drive number */</span>
+  BYTE <span class="arg">cmd</span>,      <span class="c">/* [IN] Control command code */</span>
+  void* <span class="arg">buff</span>     <span class="c">/* [I/O] Parameter and data buffer */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Physical drive number to identify the target device.</dd>
+<dt>cmd</dt>
+<dd>Command code.</dd>
+<dt>buff</dt>
+<dd>Pointer to the parameter depends on the command code. Do not care if the command has no parameter to be passed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Value</h4>
+<dl class="ret">
+<dt>RES_OK (0)</dt>
+<dd>The function succeeded.</dd>
+<dt>RES_ERROR</dt>
+<dd>An error occured.</dd>
+<dt>RES_PARERR</dt>
+<dd>The command code or parameter is invalid.</dd>
+<dt>RES_NOTRDY</dt>
+<dd>The device has not been initialized.</dd>
+</dl>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The FatFs module requires only five device independent commands described below.</p>
+<table class="lst">
+<caption>Standard ioctl command used by FatFs</caption>
+<tr><th>Command</th><th>Description</th></tr>
+<tr><td>CTRL_SYNC</td><td>Makes sure that the device has finished pending write process. If the disk I/O layer or storage device has a write-back cache, the dirty cache data must be committed to the medium immediately. Nothing to do for this command if each write operation to the medium is completed in the <tt>disk_write</tt> function.</td></tr>
+<tr><td>GET_SECTOR_COUNT</td><td>Retrieves number of available sectors, the largest allowable LBA + 1, on the drive into the <tt>LBA_t</tt> variable that pointed by <tt class="arg">buff</tt>. This command is used by <tt>f_mkfs</tt> and <tt>f_fdisk</tt> function to determine the size of volume/partition to be created. It is required when <tt>FF_USE_MKFS == 1</tt>.</td></tr>
+<tr><td>GET_SECTOR_SIZE</td><td>Retrieves sector size, minimum data unit for generic read/write, into the <tt>WORD</tt> variable that pointed by <tt class="arg">buff</tt>. Valid sector sizes are 512, 1024, 2048 and 4096. This command is required only if <tt>FF_MAX_SS &gt; FF_MIN_SS</tt>. When <tt>FF_MAX_SS == FF_MIN_SS</tt>, this command will be never used and the read/write function must work in <tt>FF_MAX_SS</tt> bytes/sector.</td></tr>
+<tr><td>GET_BLOCK_SIZE</td><td>Retrieves <em>erase block size in unit of sector</em> of the flash memory media into the <tt>DWORD</tt> variable that pointed by <tt class="arg">buff</tt>. The allowable value is 1 to 32768 in power of 2. Return 1 if the value is unknown or non flash memory media. This command is used by only <tt>f_mkfs</tt> function and it attempts to align data area on the suggested block boundary. It is required when <tt>FF_USE_MKFS == 1</tt>. Note that FatFs does not have FTL (flash translation layer). Either disk I/O layter or storage device must have an FTL in it.</td></tr>
+<tr><td>CTRL_TRIM</td><td>Informs the disk I/O layter or the storage device that the data on the block of sectors is no longer needed and it can be erased. The sector block is specified in an <tt>LBA_t</tt> array <tt>{&lt;Start LBA&gt;, &lt;End LBA&gt;}</tt> that pointed by <tt class="arg">buff</tt>. This is an identical command to Trim of ATA device. Nothing to do for this command if this funcion is not supported or not a flash memory device. FatFs does not check the result code and the file function is not affected even if the sector block was not erased well. This command is called on remove a cluster chain and in the <tt>f_mkfs</tt> function. It is required when <tt>FF_USE_TRIM == 1</tt>.</td></tr>
+</table>
+
+<p>FatFs will never use any device dependent command nor user defined command. Following table shows an example of non-standard commands which may be useful for some applications.</p>
+<table class="lst">
+<caption>Example of optional ioctl command</caption>
+<tr><th>Command</th><th>Description</th></tr>
+<tr><td>CTRL_FORMAT</td><td>Creates a physical format on the media. If <tt class="arg">buff</tt> is not null, it is pointer to the call-back function for progress notification.</td></tr>
+<tr><td>CTRL_POWER_IDLE</td><td>Puts the device idle state. <tt>STA_NOINIT</tt> in the current status flags may not be set if the device goes active state by generic read/write function.</td></tr>
+<tr><td>CTRL_POWER_OFF</td><td>Puts the device off state. Shut-down the power to the device and deinitialize the device interface if needed. <tt>STA_NOINIT</tt> in the current status flags must be set. The device goes active state by <tt>disk_initialize</tt> function.</td></tr>
+<tr><td>CTRL_LOCK</td><td>Locks media eject mechanism.</td></tr>
+<tr><td>CTRL_UNLOCK</td><td>Unlocks media eject mechanism.</td></tr>
+<tr><td>CTRL_EJECT</td><td>Ejects media cartridge. <tt>STA_NOINIT</tt> and <tt>STA_NODISK</tt> in status flag are set after the function succeeds.</td></tr>
+<tr><td>CTRL_GET_SMART</td><td>Reads SMART information.</td></tr>
+<tr><td>MMC_GET_TYPE</td><td>Gets card type. The type flags, bit0:MMCv3, bit1:SDv1, bit2:SDv2+ and bit3:LBA, is stored to a <tt>BYTE</tt> variable pointed by <tt class="arg">buff</tt>. (MMC/SDC specific command)</td></tr>
+<tr><td>MMC_GET_CSD</td><td>Reads CSD register and sets it into a 16-byte buffer pointed by <tt class="arg">buff</tt>. (MMC/SDC specific command)</td></tr>
+<tr><td>MMC_GET_CID</td><td>Reads CID register and sets it into a 16-byte buffer pointed by <tt class="arg">buff</tt>. (MMC/SDC specific command)</td></tr>
+<tr><td>MMC_GET_OCR</td><td>Reads OCR register and sets it into a 4-byte buffer pointed by <tt class="arg">buff</tt>. (MMC/SDC specific command)</td></tr>
+<tr><td>MMC_GET_SDSTAT</td><td>Reads SDSTATUS register and sets it into a 64-byte buffer pointed by <tt class="arg">buff</tt>. (SDC specific command)</td></tr>
+<tr><td>ATA_GET_REV</td><td>Reads the revision string and sets it into a 16-byte buffer pointed by <tt class="arg">buff</tt>. (ATA/CFC specific command)</td></tr>
+<tr><td>ATA_GET_MODEL</td><td>Reads the model string and sets it into a 40-byte buffer pointed by <tt class="arg">buff</tt>. (ATA/CFC specific command)</td></tr>
+<tr><td>ATA_GET_SN</td><td>Reads the serial number string and sets it into a 20-byte buffer pointed by <tt class="arg">buff</tt>. (ATA/CFC specific command)</td></tr>
+<tr><td>ISDIO_READ</td><td>Reads a block of iSDIO registers specified by command structure pointed by <tt class="arg">buff</tt>. (FlashAir specific command)</td></tr>
+<tr><td>ISDIO_WRITE</td><td>Writes a block of data to iSDIO registers specified by command structure pointed by <tt class="arg">buff</tt>. (FlashAir specific command)</td></tr>
+<tr><td>ISDIO_MRITE</td><td>Changes bits in an iSDIO register specified by command structure pointed by <tt class="arg">buff</tt>. (FlashAir specific command)</td></tr>
+</table>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>The disk_ioctl function is not needed when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 1</tt> and <tt><a href="config.html#max_ss">FF_MAX_SS</a> == <a href="config.html#max_ss">FF_MIN_SS</a></tt>.</p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/dread.html b/MCUME_pico2/fatfs/documents/doc/dread.html
new file mode 100644
index 0000000..1be191b
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/dread.html
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/dread.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - disk_read</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>disk_read</h2>
+<p>The disk_read function is called to read data from the storage device.</p>
+<pre>
+DRESULT disk_read (
+  BYTE <span class="arg">pdrv</span>,     <span class="c">/* [IN] Physical drive number */</span>
+  BYTE* <span class="arg">buff</span>,    <span class="c">/* [OUT] Pointer to the read data buffer */</span>
+  LBA_t <span class="arg">sector</span>,  <span class="c">/* [IN] Start sector number */</span>
+  UINT <span class="arg">count</span>     <span class="c">/* [IN] Number of sectros to read */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Physical drive number to identify the target device.</dd>
+<dt>buff</dt>
+<dd>Pointer to the first item of the <em>byte array</em> to store read data. Size of read data will be the sector size * <tt class="arg">count</tt> bytes.</dd>
+<dt>sector</dt>
+<dd>Start sector number in LBA. The data type <tt>LBA_t</tt> is an alias of <tt>DWORD</tt> or <tt>QWORD</tt> depends on the configuration option.</dd>
+<dt>count</dt>
+<dd>Number of sectors to read.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Value</h4>
+<dl class="ret">
+<dt>RES_OK (0)</dt>
+<dd>The function succeeded.</dd>
+<dt>RES_ERROR</dt>
+<dd>An unrecoverable hard error occured during the read operation.</dd>
+<dt>RES_PARERR</dt>
+<dd>Invalid parameter.</dd>
+<dt>RES_NOTRDY</dt>
+<dd>The device has not been initialized.</dd>
+</dl>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>Read/write operation to the generic storage devices, such as memory card, hadddisk and optical disk, is done in unit of block of data bytes called <em>sector</em>. FatFs supports the sector size in range of 512 to 4096 bytes. When FatFs is configured for fixed sector size (<tt>FF_MIN_SS == FF_MAX_SS</tt>, this is the most case), the generic read/write function must work at this sector size only. When FatFs is configured for variable sector size (<tt>FF_MIN_SS &lt; FF_MAX_SS</tt>), the sector size of medium is inquired with <tt>disk_ioctl</tt> function after <tt>disk_initialize</tt> function succeeds.</p>
+<p>There are some considerations about the memory addres passed via <tt class="arg">buff</tt>. It is not that always aligned with the word boundary, because the argument is defined as <tt>BYTE*</tt>. The unaligned transfer request can occure at <a href="appnote.html#fs1">direct transfer</a>. If the bus architecture, especially DMA controller, does not allow unaligned memory access, it should be solved in this function. If it is the case, there are some workarounds described below to avoid this issue.</p>
+<ul>
+<li>Convert word transfer to byte transfer with some trick in this function. - Recommended.</li>
+<li>On the <tt>f_read()</tt> calls, avoid long read request that includes a whole of sector. - Any direct transfer never occures.</li>
+<li>On the <tt>f_read(fp, data, btw, bw)</tt> calls, make sure that <tt>(((UINT)data &amp; 3) == (f_tell(fp) &amp; 3))</tt> is true. - Word alignment of <tt class="arg">buff</tt> is guaranteed.</li>
+</ul>
+<p>Also the memory area may be out of reach in DMA. This is the case if it is located on the tightly coupled memory which is usually used for stack. Use double buffered transfer, or avoid to define file I/O buffer, <tt>FATFS</tt> and <tt>FIL</tt> structure as local variables where on the stack.</p>
+<p>Generally, a multiple sector read request must not be split into single sector transactions to the storage device, or read throughput gets worse.</p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/dstat.html b/MCUME_pico2/fatfs/documents/doc/dstat.html
new file mode 100644
index 0000000..a891489
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/dstat.html
@@ -0,0 +1,48 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/dstat.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - disk_status</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>disk_status</h2>
+<p>The disk_status function is called to inquire the current drive status.</p>
+<pre>
+DSTATUS disk_status (
+  BYTE <span class="arg">pdrv</span>     <span class="c">/* [IN] Physical drive number */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Physical drive number to identify the target device. Always zero in single drive system.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>The current drive status is returned in combination of status flags described below. FatFs refers only <tt>STA_NOINIT</tt> and <tt>STA_PROTECT</tt>.</p>
+<dl class="ret">
+<dt>STA_NOINIT</dt>
+<dd>Indicates that the device has not been initialized and not ready to work. This flag is set on system reset, media removal or failure of <a href="dinit.html"><tt>disk_initialize</tt></a> function. It is cleared on <tt>disk_initialize</tt> function succeeded. Any media change that occurs asynchronously must be captured and reflect it to the status flags, or auto-mount function will not work correctly. If the system does not support media change detection, application program needs to explicitly re-mount the volume with <tt>f_mount</tt> function after each media change.</dd>
+<dt>STA_NODISK</dt>
+<dd>Indicates that no medium in the drive. This is always cleared when the drive is non-removable class. Note that FatFs does not refer this flag.</dd>
+<dt>STA_PROTECT</dt>
+<dd>Indicates that the medium is write protected. This is always cleared when the drive has no write protect function. Not valid if <tt>STA_NODISK</tt> is set.</dd>
+</dl>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/dwrite.html b/MCUME_pico2/fatfs/documents/doc/dwrite.html
new file mode 100644
index 0000000..fef5106
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/dwrite.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/dwrite.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - disk_write</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>disk_write</h2>
+<p>The disk_write function is called to write data to the storage device.</p>
+<pre>
+DRESULT disk_write (
+  BYTE <span class="arg">pdrv</span>,        <span class="c">/* [IN] Physical drive number */</span>
+  const BYTE* <span class="arg">buff</span>, <span class="c">/* [IN] Pointer to the data to be written */</span>
+  LBA_t <span class="arg">sector</span>,     <span class="c">/* [IN] Sector number to write from */</span>
+  UINT <span class="arg">count</span>        <span class="c">/* [IN] Number of sectors to write */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Physical drive number to identify the target device.</dd>
+<dt>buff</dt>
+<dd>Pointer to the first item of the <em>byte array</em> to be written. The size of data to be written is sector size * <tt class="arg">count</tt> bytes.</dd>
+<dt>sector</dt>
+<dd>Start sector number in LBA. The data type <tt>LBA_t</tt> is an alias of <tt>DWORD</tt> or <tt>QWORD</tt> depends on the configuration option.</dd>
+<dt>count</dt>
+<dd>Number of sectors to write.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<dl class="ret">
+<dt>RES_OK (0)</dt>
+<dd>The function succeeded.</dd>
+<dt>RES_ERROR</dt>
+<dd>An unrecoverable hard error occured during the write operation.</dd>
+<dt>RES_WRPRT</dt>
+<dd>The medium is write protected.</dd>
+<dt>RES_PARERR</dt>
+<dd>Invalid parameter.</dd>
+<dt>RES_NOTRDY</dt>
+<dd>The device has not been initialized.</dd>
+</dl>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The specified memory address is not that always aligned to word boundary because the argument is defined as <tt>BYTE*</tt>. For more information, refer to the description of <a href="dread.html"><tt>disk_read</tt></a> function.</p>
+<p>Generally, a multiple sector write request (<tt class="arg">count</tt><tt> &gt; 1</tt>) must not be split into single sector transactions to the storage device, or the file write throughput will be drastically decreased.</p>
+<p>FatFs expects delayed write function of the disk control layer. The write operation to the media does not need to be completed when return from this function by what write operation is in progress or data is only stored into the write-back cache. But write data on the <tt class="arg">buff</tt> is invalid after return from this function. The write completion request is done by <tt>CTRL_SYNC</tt> command of <tt><a href="dioctl.html">disk_ioctl</a></tt> function. Therefore, if a delayed write function is implemented, the write throughput of the filesystem will be improved.</p>
+<p><em>Remarks: Application program MUST NOT call this function, or FAT structure on the volume can be collapsed.</em></p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This function is not needed when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 1</tt>.</p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/eof.html b/MCUME_pico2/fatfs/documents/doc/eof.html
new file mode 100644
index 0000000..efacfbf
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/eof.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/eof.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_eof</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_eof</h2>
+<p>The f_eof function tests for end-of-file on a file.</p>
+<pre>
+int f_eof (
+  FIL* <span class="arg">fp</span>   <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>The <tt>f_eof</tt> function returns a non-zero value if the read/write pointer has reached end of the file; otherwise it returns a zero.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>In this revision, this function is implemented as a macro. It does not have any validation and mutual exclusion.</p>
+<pre>
+<span class="k">#define</span> f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="lseek.html">f_lseek</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/error.html b/MCUME_pico2/fatfs/documents/doc/error.html
new file mode 100644
index 0000000..bee9685
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/error.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/error.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_error</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_error</h2>
+<p>The f_error tests for an error on a file.</p>
+<pre>
+int f_error (
+  FIL* <span class="arg">fp</span>   <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>Returns a non-zero value if a hard error has occured; otherwise it returns a zero.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>In this revision, this function is implemented as a macro. It does not have any validation and mutual exclusion.</p>
+<pre>
+<span class="k">#define</span> f_error(fp) ((fp)->err)
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/expand.html b/MCUME_pico2/fatfs/documents/doc/expand.html
new file mode 100644
index 0000000..7620ba9
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/expand.html
@@ -0,0 +1,117 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/lseek.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_expand</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_expand</h2>
+<p>The f_expand function prepares or allocates a contiguous data area to the file.</p>
+
+<pre>
+FRESULT f_expand (
+  FIL*    <span class="arg">fp</span>,  <span class="c">/* [IN] File object */</span>
+  FSIZE_t <span class="arg">fsz</span>, <span class="c">/* [IN] File size expanded to */</span>
+  BYTE    <span class="arg">opt</span>  <span class="c">/* [IN] Allocation mode */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object.</dd>
+<dt>fsz</dt>
+<dd>Number of bytes in size to prepare or allocate for the file. The data type <tt>FSIZE_t</tt> is an alias of either <tt>DWORD</tt>(32-bit) or <tt>QWORD</tt>(64-bit) depends on the configuration option <tt>FF_FS_EXFAT</tt>.</dd>
+<dt>opt</dt>
+<dd>Allocation mode. Prepare to allocate (0) or Allocate now (1).</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_expand</tt> function prepares or allocates a contiguous data area to the file. When <tt class="arg">opt</tt> is 1, the data area is allocated to the file in this function. Unlike expansion of file size by <tt>f_lseek</tt> function, the file must be truncated prior to use this function and read/write pointer of the file stays at offset 0 after the function call. The file content allocated with this function is <em>undefined</em>, because no data is written to the file in this process. The function can fail with <tt>FR_DENIED</tt> due to some reasons below.</p>
+<ul>
+<li>No free contiguous space was found.</li>
+<li>Size of the file was not zero.</li>
+<li>The file has been opened in read-only mode.</li>
+<li>Not allowable file size. (&gt;= 4 GB on FAT volume)</li>
+</ul>
+<p>When <tt class="arg">opt</tt> is 0, the function finds a contiguous data area and set it as suggested point for next allocation. The subsequent cluster allocation begins at top of the contiguous area found by this function. Thus the file allocation is guaranteed be contiguous and without allocation delay until the file size reaches this size unless any other changes to the volume is performed.</p>
+<p>The contiguous file has an advantage for time-critical read/write operations. It eliminates some overheads in the filesystem and the storage device caused by random access for fragmented file.</p>
+<p>Also the contiguous file can be easily accessed directly via low-level disk functions. However, this is not recommended in consideration of portability and future compatibility. If the file has not been confirmed be contiguous, use <a href="../res/app5.c">this function</a> to examine if the file is contiguous or not.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt>FF_USE_EXPAND == 1</tt> and <tt>FF_FS_READONLY == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Creating a contiguous file */</span>
+
+    <span class="c">/* Create a new file */</span>
+    res = f_open(fp = malloc(sizeof (FIL)), "file.dat", FA_WRITE|FA_CREATE_ALWAYS);
+    if (res) { <span class="c">/* Check if the file has been opened */</span>
+        free(fp);
+        die("Failed to open the file.");
+    }
+
+    <span class="c">/* Alloacte a 100 MiB of contiguous area to the file */</span>
+    res = <em>f_expand</em>(fp, 104857600, 1);
+    if (res) { <span class="c">/* Check if the file has been expanded */</span>
+        f_close(fp);
+        free(fp);
+        die("Failed to allocate contiguous area.");
+    }
+
+    <span class="c">/* Now you have a contiguous file accessible with fp */</span>
+
+</pre>
+<pre>
+    <span class="c">/* Accessing the contiguous file via low-level disk functions */</span>
+
+    <span class="c">/* Get physical location of the file data */</span>
+    drv = fp-&gt;obj.fs-&gt;pdrv;
+    lba = fp-&gt;obj.fs-&gt;database + fp-&gt;obj.fs-&gt;csize * (fp-&gt;obj.sclust - 2);
+
+    <span class="c">/* Write 2048 sectors from top of the file at a time */</span>
+    res = disk_write(drv, buffer, lba, 2048);
+
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="lseek.html">f_lseek</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/fattime.html b/MCUME_pico2/fatfs/documents/doc/fattime.html
new file mode 100644
index 0000000..002733a
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/fattime.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/fattime.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - get_fattime</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>get_fattime</h2>
+<p>The get_fattime function is called to get the current time.</p>
+<pre>
+DWORD get_fattime (void);
+</pre>
+</div>
+
+
+<div class="para ret">
+<h4>Return Value</h4>
+<p>Currnet local time shall be returned as bit-fields packed into a <tt>DWORD</tt> value. The bit fields are as follows:</p>
+<dl class="ret">
+<dt>bit31:25</dt>
+<dd>Year origin from the 1980 (0..127, e.g. 37 for 2017)</dd>
+<dt>bit24:21</dt>
+<dd>Month (1..12)</dd>
+<dt>bit20:16</dt>
+<dd>Day of the month (1..31)</dd>
+<dt>bit15:11</dt>
+<dd>Hour (0..23)</dd>
+<dt>bit10:5</dt>
+<dd>Minute (0..59)</dd>
+<dt>bit4:0</dt>
+<dd>Second / 2 (0..29, e.g. 25 for 50)</dd>
+</dl>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>get_fattime</tt> function shall return any valid time even if the system does not support a real time clock. If a zero is returned, the file will not have a valid timestamp.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This function is not needed when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 1</tt> or <tt><a href="config.html#fs_nortc">FF_FS_NORTC</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+DWORD get_fattime (void)
+{
+    time_t t;
+    struct tm *stm;
+
+
+    t = time(0);
+    stm = localtime(&t);
+
+    return (DWORD)(stm->tm_year - 80) &lt;&lt; 25 |
+           (DWORD)(stm->tm_mon + 1) &lt;&lt; 21 |
+           (DWORD)stm->tm_mday &lt;&lt; 16 |
+           (DWORD)stm->tm_hour &lt;&lt; 11 |
+           (DWORD)stm->tm_min &lt;&lt; 5 |
+           (DWORD)stm->tm_sec &gt;&gt; 1;
+}
+</pre>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/fdisk.html b/MCUME_pico2/fatfs/documents/doc/fdisk.html
new file mode 100644
index 0000000..d8c40bd
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/fdisk.html
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/fdisk.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_fdisk</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_fdisk</h2>
+<p>The f_fdisk fucntion divides a physical drive.</p>
+<pre>
+FRESULT f_fdisk (
+  BYTE  <span class="arg">pdrv</span>,         <span class="c">/* [IN] Physical drive number */</span>
+  const LBA_t <span class="arg">ptbl[]</span>, <span class="c">/* [IN] Partition map table */</span>
+  void* <span class="arg">work</span>          <span class="c">/* [IN] Work area */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>pdrv</dt>
+<dd>Specifies the <em>physical drive</em> to be divided. This is not the logical drive number but the drive identifier passed to the low level disk functions.</dd>
+<dt>ptbl</dt>
+<dd>List of partition size to create on the drive. The data type <tt>LBA_t</tt> is an alias of <tt>DWORD</tt> or <tt>QWORD</tt> depends on the configuration option <tt><a href="config.html#fs_lba64">FF_LBA64</a></tt>.</dd>
+<dt>work</dt>
+<dd>Pointer to the function work area. The size must be at least <tt><a href="config.html#max_ss">FF_MAX_SS</a></tt> bytes. When a null pointer is given with <tt><a href="config.html#use_lfn">FF_USE_LFN</a> = 3</tt>, a memory block is obtained in this function for the working buffer.</dd>
+</dl>
+</div>
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#ip">FR_INVALID_PARAMETER</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_fdisk</tt> function creates partitions on the physical drive. The partitioning format can be in generic MBR or GPT. The partition map table specifies how to divide the physical drive. The first item specifies the size of the first partition and the partitions are located on the drive in order of from the first item. When the value of item is less than or equal to 100, it specifies the partition size in percentage of the entire drive space. When it is larger than 100, it specifies number of sectors. The partition map table is terminated by a zero, no space is remaining for next allocation or 4th partition is created in MBR format. If the specified size is larger than remaining space on the drive, the partition is truncated at end of the drive.</p>
+<p>By default, partitions are created in MBR format. It can create upto four primary partitions on a drive. GPT format is used to create the partitions when 64-bit LBA is enabled (<tt>FF_LBA64 = 1</tt>) and the drive size is equal to or larger than <tt><a href="config.html#fs_gptmin">FF_MIN_GPT</a></tt> sectors. It can create over ten partitions on a drive.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READOLNY</a> == 0</tt>, <tt><a href="config.html#use_mkfs">FF_USE_MKFS</a> == 1</tt> and <tt><a href="config.html#multi_partition">FF_MULTI_PARTITION</a> == 1</tt>.</p>
+</div>
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Volume mapping table defined by user (required when FF_MULTI_PARTITION == 1) */</span>
+
+    PARTITION VolToPart[FF_VOLUMES] = {
+        {0, 1},    <span class="c">/* "0:" ==> 1st partition in PD#0 */</span>
+        {0, 2},    <span class="c">/* "1:" ==> 2nd partition in PD#0 */</span>
+        {1, 0}     <span class="c">/* "2:" ==> PD#1 as removable drive */</span>
+    };
+</pre>
+<pre>
+    <span class="c">/* Initialize a brand-new disk drive mapped to physical drive 0 */</span>
+
+    BYTE work[FF_MAX_SS];         <span class="c">/* Working buffer */</span>
+    LBA_t plist[] = {50, 50, 0};  <span class="c">/* Divide the drive into two partitions */</span>
+                 <span class="c">/* {0x10000000, 100}; 256M sectors for 1st partition and left all for 2nd partition */</span>
+                 <span class="c">/* {20, 20, 20, 0}; 20% for 3 partitions each and remaing space is left not allocated */</span>
+
+    <em>f_fdisk</em>(0, plist, work);                    <span class="c">/* Divide physical drive 0 */</span>
+
+    f_mkfs("0:", 0, work, sizeof work); <span class="c">/* Create FAT volume on the logical drive 0 */</span>
+    f_mkfs("1:", 0, work, sizeof work); <span class="c">/* Create FAT volume on the logical drive 1 */</span>
+
+</pre>
+</div>
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><a href="filename.html#vol">Volume management</a>, <a href="mkfs.html"><tt>f_mkfs</tt></a></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/filename.html b/MCUME_pico2/fatfs/documents/doc/filename.html
new file mode 100644
index 0000000..8ff028d
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/filename.html
@@ -0,0 +1,94 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/filename.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - Path Names</title>
+</head>
+
+<body>
+<h1>Path Names on the FatFs API</h1>
+
+<div class="para doc" id="nam">
+<h3>Format of the Path Names</h3>
+<p>The format of path name on the FatFs module is similer to the filename specs of DOS/Windos as follows:</p>
+<pre>[<em>drive#</em>:][/]<em>directory</em>/<em>file</em></pre>
+<p>The FatFs module supports long file name (LFN) and 8.3 format file name (SFN). The LFN can be used when <tt><a href="config.html#use_lfn">FF_USE_LFN</a> &gt;= 1</tt>. The sub-directories are separated with a <tt>\</tt> or <tt>/</tt> as the same way as DOS/Windows API. Duplicated separator and terminating separator, such as <tt>"/<em>/</em>animal/<em>//</em>cat<em>/</em>"</tt>, are ignored. Only a difference is that the heading drive prefix to specify the <a href="#vol">logical drive</a>, an FAT volume, is in a digit (0-9) + a colon, while it is in an alphabet (A-Z) + a colon in DOS/Windows. The logical drive number is the identifier to specify the volume to be accessed. When drive prefix is omitted, the logical drive number is assumed as <em>default drive</em>.</p>
+<p>Control characters (<tt>\0</tt> to <tt>\x1F</tt>) are recognized as end of the path name. In LFN configuration, leading or embedded white spaces in the file name are valid as part of the file name, but the treminating white space and dot of the file name are ignored and truncated. In non-LFN configuration, white space is recognized as end of the path name.</p>
+<p>In default configuration (<tt><a href="config.html#fs_rpath">FF_FS_RPATH</a> == 0</tt>), it does not have a concept of current directory like OS oriented filesystem. Every object on the volume is always specified in full path name followed from the root directory. Dot directory names (<tt>".", ".."</tt>) are not allowed. Heading separator is ignored and it can be exist or omitted. The default drive is fixed to drive 0.</p>
+<p>When relative path feature is enabled (<tt>FF_FS_RPATH &gt;= 1</tt>), specified path is followed from the root directory if a heading separator is exist. If not, it is followed from the current directory of the default drive. Dot directory name is also allowed for the path name. The current directory is set by <a href="chdir.html"><tt>f_chdir</tt></a> function and the default drive is the current drive set by <a href="chdrive.html"><tt>f_chdrive</tt></a> function.</p>
+<table class="lst2">
+<tr><td>Path name</td><td>FF_FS_RPATH == 0</td><td>FF_FS_RPATH &gt;= 1</td></tr>
+<tr class="lst3"><td>file.txt</td><td>A file in the root directory of the drive 0</td><td>A file in the current directory of the current drive</td></tr>
+<tr><td>/file.txt</td><td>A file in the root directory of the drive 0</td><td>A file in the root directory of the current drive</td></tr>
+<tr><td></td><td>The root directory of the drive 0</td><td>The current directory of the current drive</td></tr>
+<tr><td>/</td><td>The root directory of the drive 0</td><td>The root directory of the current drive</td></tr>
+<tr><td>2:</td><td>The root directory of the drive 2</td><td>The current directory of the drive 2</td></tr>
+<tr><td>2:/</td><td>The root directory of the drive 2</td><td>The root directory of the drive 2</td></tr>
+<tr><td>2:file.txt</td><td>A file in the root directory of the drive 2</td><td>A file in the current directory of the drive 2</td></tr>
+<tr><td>../file.txt</td><td>Invalid name</td><td>A file in the parent directory</td></tr>
+<tr><td>.</td><td>Invalid name</td><td>This directory</td></tr>
+<tr><td>..</td><td>Invalid name</td><td>Parent directory of the current directory (*)</td></tr>
+<tr><td>dir1/..</td><td>Invalid name</td><td>The current directory</td></tr>
+<tr><td>/..</td><td>Invalid name</td><td>The root directory (sticks the top level)</td></tr>
+</table>
+<p>Also the drive prefix can be in pre-defined arbitrary string. When the option <tt><a href="config.html#str_volume_id">FF_STR_VOLUME_ID</a> == 1</tt>, also arbitrary string volume ID can be used as drive prefix. e.g. <tt>"<em>flash:</em>file1.txt"</tt>, <tt>"<em>ram:</em>temp.dat"</tt> or <tt>"<em>sd:</em>"</tt>. If the srting does not match any volume ID, the function fails with <tt>FR_INVALID_DRIVE</tt>.</p>
+<p>When <tt>FF_STR_VOLUME_ID == 2</tt>, Unix style drive prefix can be used. e.g. <tt>"<em>/flash</em>/file1.txt"</tt>, <tt>"<em>/ram</em>/temp.dat"</tt> or <tt>"<em>/sd</em>"</tt>. If a heading separator is exist, it is treated as start of drive prefix and in absolute path. Any form as "root directory in current drive" and "current directory in specified drive" cannot be used. Double dot name cannot traverse the drives such as <tt>"<em>/flash</em>/..<em>/ram</em>/foo.dat"</tt>.</p>
+<p><em>Remark: In this revision, double dot name <tt>".."</tt> cannot follow the parent directory on the exFAT volume. It will work as <tt>"."</tt> and stay there.</em></p>
+</div>
+
+<div class="para doc" id="case">
+<h3>Legal Characters and Case Sensitivity</h3>
+<p>In the generic FAT filesystems, the legal characters for object name (file/directory name) are, <tt>0-9 A-Z ! # $ % &amp; ' ( ) - @ ^ _ ` { } ~</tt> in ASCII and extended characters <tt>\x80</tt> to <tt>\xFF</tt>. In the FAT filesystems with LFN extention, also <tt>+ , ; = [ ]</tt>, white space and extended characters <tt>U+000080</tt> to <tt>U+10FFFF</tt> are legal for the object name. White spaces and dots can be placed anywhere in the path name except end of the name. Trailing white spaces and dots are ignored.</p>
+<p>FAT filesystem is case-insensitive to the object names on the volume. Object name on the FAT volume is compared in case-insensitive. For instance, these three names, <tt>file.txt</tt>, <tt>File.Txt</tt> and <tt>FILE.TXT</tt>, are identical on the FAT filesystem. This is applied to extended charactres as well. When an object is created on the FAT volume, up converted name is recorded to the SFN entry, and the raw name is recorded to the LFN entry when LFN extension is exist.</p>
+<p>As for the MS-DOS and PC DOS for CJK (DOS/DBCS), extended characters ware recorded to the SFN entry without up-case conversion and compared in case-sensitive. This causes a problem on compatibility with Windows system when the object with extended characters is created on the volume by DOS/DBCS system; therfore the object names with DBCS extended characters should not be used on the FAT volume shared by those systems. FatFs works with case-sensitive to the extended characters in only non-LFN with DBCS configuration (DOS/DBCS specs). However, FatFs works with case-insensitive to the extended character (WindowsNT specs) in LFN configuration.</p>
+</div>
+
+<div class="para doc" id="uni">
+<h3>Unicode API</h3>
+<p>The path names are input/output in either ANSI/OEM code or Unicode depends on the configuration options. The type of arguments which specifies the path names is defined as <tt>TCHAR</tt>. It is an alias of <tt>char</tt> by default and the code set used for the path name string is ANSI/OEM specifid by <tt><a href="config.html#code_page">FF_CODE_PAGE</a></tt>. When <tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a></tt> is set to 1 or larger, the type of the <tt>TCHAR</tt> is switched to proper type to support the Unicode string. When Unicode API is specified by this option, the full-featured LFN specification is supported and the Unicode specific characters, such as �☪✡☸☭ and any character not in BMP, can also be used for the path name. It also affects data types and encoding of the string I/O functions. To define literal strings, <tt>_T(s)</tt> and <tt>_TEXT(s)</tt> macro are available to specify the string in proper type. The code shown below is an example to define the literal strings.</p>
+<pre>
+ f_open(fp, <span class="e">"filename.txt"</span>, FA_READ);      <span class="c">/* ANSI/OEM string (char) */</span>
+ f_open(fp, <span class="e">L"filename.txt"</span>, FA_READ);     <span class="c">/* UTF-16 string (WCHAR) */</span>
+ f_open(fp, <span class="e">u8"filename.txt"</span>, FA_READ);    <span class="c">/* UTF-8 string (char) */</span>
+ f_open(fp, <span class="e">U"filename.txt"</span>, FA_READ);     <span class="c">/* UTF-32 string (DWORD) */</span>
+ f_open(fp, <span class="e">_T("filename.txt")</span>, FA_READ);  <span class="c">/* Changed by configuration (TCHAR) */</span>
+</pre>
+</div>
+
+<div class="para doc" id="vol">
+<h3>Volume Management</h3>
+<p>By default, each logical drive is associated with the physical drive in same drive number. An FAT volume on the physical drive is serched in the volume mount process. It reads boot sectors and checks it if it is an FAT VBR in order of LBA 0 as SFD format, 1st partition, 2nd partition, 3rd partition, ..., as MBR or GPT format.</p>
+<p>When multiple partition feature is enabled, <tt><a href="config.html#multi_partition">FF_MULTI_PARTITION = 1</a></tt>, each individual logical drive is associated with arbitrary partition or physical drive specified by volume management table, <tt>VolToPart[]</tt>. The table needs to be defined by user to resolve mappings of the logical drive numbers and the associated partitions or drives. Following code is an example of the volume management table.</p>
+<pre>
+Example: "0:", "1:" and "2:" are associated with three partitions on the physical drive 0 (a non-removable drive)
+         "3:" is associated with physical drive 1 (a removable drive)
+
+PARTITION VolToPart[FF_VOLUMES] = {
+    {0, 1},     <span class="c">/* "0:" ==> 1st partition on the pd#0 */</span>
+    {0, 2},     <span class="c">/* "1:" ==> 2nd partition on the pd#0 */</span>
+    {0, 3},     <span class="c">/* "2:" ==> 3rd partition on the pd#0 */</span>
+    {1, 0}      <span class="c">/* "3:" ==> pd#1 as removable drive (auto-search) */</span>
+};
+
+
+<img src="../res/f7.png" width="900" height="288" alt="relationship between logical drive and physical drive">
+</pre>
+<p>There are some considerations when enable the multi-partition configuration.</p>
+<ul>
+<li>The physical drive that hosts two or more mounted partitions should be non-removable, or all volumes on the drive must be unmounted when remove the medium.</li>
+<li>When make any change to the <tt>VolToPart[]</tt>, corresponding volume should be unmounted prior to make change the item.</li>
+<li>On the MBR format drive, up to four primary partitions (1-4) can be specified. The partition number 1 specifies the first item in the partition table and the partition number 2 specifies the second one, and so on. The logical patitions (5-) in the extended partition is not supported.</li>
+<li>On the GPT format drive, the partition number 1 specifies the first Microsoft BDP found in the partition table and the partition number 2 specifies the second one found, and so on.</li>
+<li>Windows 10 earlier than 1703 does not support multiple volumes on the physical drive with removable class. Only the first parition found on the drive will be mounted. Windows OS does not support SFD format on the physical drive with non-removable class.</li>
+<li>Some systems manage the on-board storage in non-standard partition format and each partition is mapped as physical drive in <tt>disk_*</tt> functions. For such system, <tt>FF_MULTI_PARTITION</tt> should be always 0.</li>
+<li>For further information about the volume management, refer to the description in <tt><a href="fdisk.html">f_fdisk</a></tt> and <tt><a href="mkfs.html">f_mkfs</a></tt>.</li>
+</ul>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/findfirst.html b/MCUME_pico2/fatfs/documents/doc/findfirst.html
new file mode 100644
index 0000000..5f1e344
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/findfirst.html
@@ -0,0 +1,118 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/findfirst.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_findfirst</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_findfirst</h2>
+<p>The f_findfirst function searches a directroy for an item.</p>
+<pre>
+FRESULT f_findfirst (
+  DIR* <span class="arg">dp</span>,              <span class="c">/* [OUT] Poninter to the directory object */</span>
+  FILINFO* <span class="arg">fno</span>,         <span class="c">/* [OUT] Pointer to the file information structure */</span>
+  const TCHAR* <span class="arg">path</span>,    <span class="c">/* [IN] Pointer to the directory name to be opened */</span>
+  const TCHAR* <span class="arg">pattern</span>  <span class="c">/* [IN] Pointer to the matching pattern string */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>dp</dt>
+<dd>Pointer to the blank directory object.</dd>
+<dt>fno</dt>
+<dd>Pointer to the <a href="sfileinfo.html">file information structure</a> to store the information about the found item.</dd>
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">directory name</a> to be opened.</dd>
+<dt>pattern</dt>
+<dd>Pointer to the nul-terminated string that specifies the name matching pattern to be searched for. It is referred by also subsequent <tt>f_findnext</tt> function, so that the string must be valid while the successive function calls.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>,
+<a href="rc.html#tf">FR_TOO_MANY_OPEN_FILES</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>After the directory specified by <tt class="arg">path</tt> could be opened, it starts to search the directory for items with the matching pattern specified by <tt class="arg">pattern</tt>. If the first item is found, the information about the item is stored into the file information structure <tt class="arg">fno</tt>. If not found, <tt>fno-&gt;fname[]</tt> has a null string.</p>
+<p>The matching pattern string can contain wildcards. For example:</p>
+<ul>
+<li><tt>?</tt> - An any character.</li>
+<li><tt>???</tt> - An any string in length of three characters.</li>
+<li><tt>*</tt> - An any string in length of zero or longer.</li>
+<li><tt>????*</tt> - An any string in length of four characters or longer.</li>
+</ul>
+<p>Since the matching algorithm uses recursion, number of wildcards in the matching pattern is limited to four to limit the stack usage. Any pattern with too many wildcards does not match any name. In LFN configuration, only <tt>fname[]</tt> is tested when <tt>FF_USE_FIND == 1</tt> and also <tt>altname[]</tt> is tested when <tt>FF_USE_FIND == 2</tt>. There are some differences listed below between FatFs and standard systems in matching condition.</p>
+<ul>
+<li><tt>"*.*"</tt> does not match any name without extension while it matches any name with or without extension in standard systems.</li>
+<li>Any pattern terminated with a dot does not match any name while it matches the name without extensiton in standard systems.</li>
+<li><a href="filename.html#case">DBCS extended characters</a> are compared in case-sensitive when LFN is enabled with <tt>!FF_LFN_UNICODE</tt>.</li>
+</ul>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="opendir.html"><tt>f_opendir</tt></a> and <a href="readdir.html"><tt>f_readdir</tt></a> function. Available when <tt><a href="config.html#use_find">FF_USE_FIND</a> &gt;= 1</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Examples</h4>
+<pre>
+<span class="c">/* Search a directory for objects and display it */</span>
+
+void find_image_file (void)
+{
+    FRESULT fr;     <span class="c">/* Return value */</span>
+    DIR dj;         <span class="c">/* Directory object */</span>
+    FILINFO fno;    <span class="c">/* File information */</span>
+
+    fr = <em>f_findfirst</em>(&amp;dj, &amp;fno, "", "????????.JPG"); <span class="c">/* Start to search for photo files */</span>
+
+    while (fr == FR_OK &amp;&amp; fno.fname[0]) {         <span class="c">/* Repeat while an item is found */</span>
+        printf("%s\n", fno.fname);                <span class="c">/* Print the object name */</span>
+        fr = f_findnext(&amp;dj, &amp;fno);               <span class="c">/* Search for next item */</span>
+    }
+
+    f_closedir(&amp;dj);
+}
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="findnext.html">f_findnext</a>, <a href="closedir.html">f_closedir</a>, <a href="sdir.html">DIR</a>, <a href="sfileinfo.html">FILINFO</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/findnext.html b/MCUME_pico2/fatfs/documents/doc/findnext.html
new file mode 100644
index 0000000..f39f0fb
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/findnext.html
@@ -0,0 +1,69 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/findnext.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_findnext</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_findnext</h2>
+<p>The f_findnext function searches for a next matched object</p>
+<pre>
+FRESULT f_findnext (
+  DIR* <span class="arg">dp</span>,              <span class="c">/* [IN] Poninter to the directory object */</span>
+  FILINFO* <span class="arg">fno</span>          <span class="c">/* [OUT] Pointer to the file information structure */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>dp</dt>
+<dd>Pointer to the valid directory object created by <tt>f_findfirst</tt> function.</dd>
+<dt>fno</dt>
+<dd>Pointer to the file information structure to store the information about the found directory item.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>It continues the search from a previous call to the <tt>f_findfirst</tt> or <tt>f_findnext</tt> function. If found, the information about the object is stored into the file information structure. If no item to be read, a null string will be returned into <tt>fno-&gt;fname[]</tt>.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="readdir.html"><tt>f_readdir</tt></a> function. Available when <tt><a href="config.html#use_find">FF_USE_FIND</a> == 1</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 1</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="findfirst.html">f_findfirst</a>, <a href="closedir.html">f_closedir</a>, <a href="sdir.html">DIR</a>, <a href="sfileinfo.html">FILINFO</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/forward.html b/MCUME_pico2/fatfs/documents/doc/forward.html
new file mode 100644
index 0000000..fdb5f49
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/forward.html
@@ -0,0 +1,139 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/forward.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_forward</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_forward</h2>
+<p>The f_forward function reads the file data and forward it to the data streaming device.</p>
+<pre>
+FRESULT f_forward (
+  FIL* <span class="arg">fp</span>,                        <span class="c">/* [IN] File object */</span>
+  UINT (*<span class="arg">func</span>)(const BYTE*,UINT), <span class="c">/* [IN] Data streaming function */</span>
+  UINT <span class="arg">btf</span>,                       <span class="c">/* [IN] Number of bytes to forward */</span>
+  UINT* <span class="arg">bf</span>                        <span class="c">/* [OUT] Number of bytes forwarded */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object.</dd>
+<dt>func</dt>
+<dd>Pointer to the user-defined data streaming function. For details, refer to the sample code.</dd>
+<dt>btf</dt>
+<dd>Number of bytes to forward in range of <tt>UINT</tt>.</dd>
+<dt>bf</dt>
+<dd>Pointer to the <tt>UINT</tt> variable to return number of bytes forwarded.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_forward</tt> function reads the data from the file and forward it to the outgoing stream. This function is suitable for small memory system, because it does not require any data buffer in the application module. The file pointer of the file object advances in number of bytes forwarded. In case of <tt class="arg">*bf</tt> is less than <tt class="arg">btf</tt> without error, it means the requested size of data could not be transferred due to end of file or stream goes busy during data transfer.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#use_forward">FF_USE_FORWARD</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+<span class="c">/*------------------------------------------------------------------------*/</span>
+<span class="c">/* Sample code of data transfer function to be called back from f_forward */</span>
+<span class="c">/*------------------------------------------------------------------------*/</span>
+
+UINT out_stream (   <span class="c">/* Returns number of bytes sent or stream status */</span>
+    const BYTE *p,  <span class="c">/* Pointer to the data block to be sent */</span>
+    UINT btf        <span class="c">/* &gt;0: Transfer call (Number of bytes to be sent). 0: Sense call */</span>
+)
+{
+    UINT cnt = 0;
+
+
+    if (btf == 0) {     <span class="c">/* Sense call */</span>
+        <span class="c">/* Return stream status (0: Busy, 1: Ready) */</span>
+        <span class="c">/* When once it returned ready to sense call, it must accept a byte at least */</span>
+        <span class="c">/* at subsequent transfer call, or f_forward will fail with FR_INT_ERR. */</span>
+        if (FIFO_READY) cnt = 1;
+    }
+    else {              <span class="c">/* Transfer call */</span>
+        do {    <span class="c">/* Repeat while there is any data to be sent and the stream is ready */</span>
+            FIFO_PORT = *p++;
+            cnt++;
+        } while (cnt &lt; btf &amp;&amp; FIFO_READY);
+    }
+
+    return cnt;
+}
+
+
+<span class="c">/*------------------------------------------------------------------------*/</span>
+<span class="c">/* Sample code using f_forward function                                   */</span>
+<span class="c">/*------------------------------------------------------------------------*/</span>
+
+FRESULT play_file (
+    char *fn        <span class="c">/* Pointer to the audio file name to be played */</span>
+)
+{
+    FRESULT rc;
+    FIL fil;
+    UINT dmy;
+
+    <span class="c">/* Open the audio file in read only mode */</span>
+    rc = f_open(&amp;fil, fn, FA_READ);
+    if (rc) return rc;
+
+    <span class="c">/* Repeat until the file pointer reaches end of the file */</span>
+    while (rc == FR_OK &amp;&amp; !f_eof(&amp;fil)) {
+
+        <span class="c">/* some processes... */</span>
+
+        <span class="c">/* Fill output stream periodicaly or on-demand */</span>
+        rc = <em>f_forward</em>(&amp;fil, out_stream, 1000, &amp;dmy);
+    }
+
+    <span class="c">/* Close the file and return */</span>
+    f_close(&amp;fil);
+    return rc;
+}
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="gets.html">fgets</a>, <a href="write.html">f_write</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/getcwd.html b/MCUME_pico2/fatfs/documents/doc/getcwd.html
new file mode 100644
index 0000000..6eb9a58
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/getcwd.html
@@ -0,0 +1,83 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/getcwd.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_getcwd</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_getcwd</h2>
+<p>The f_getcwd function retrieves the current directory of the current drive.</p>
+<pre>
+FRESULT f_getcwd (
+  TCHAR* <span class="arg">buff</span>, <span class="c">/* [OUT] Buffer to return path name */</span>
+  UINT <span class="arg">len</span>     <span class="c">/* [IN] The length of the buffer */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>buff</dt>
+<dd>Pointer to the buffer to receive the current directory string.</dd>
+<dt>len</dt>
+<dd>Size of the buffer in unit of <tt>TCHAR</tt>.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_getcwd</tt> function retrieves full path name of the current directory of the current drive. When <tt><a href="config.html#volumes">FF_VOLUMES</a> &gt;= 2</tt>, a heading drive prefix is added to the path name. The style of drive prefix depends on <tt><a href="config.html#str_volume_id">FF_STR_VOLUME_ID</a></tt>.</p>
+<p><em>Note: In this revision, this function cannot retrieve the current directory path on the exFAT volume. It always returns the root directory path.</em></p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_rpath">FF_FS_RPATH</a> == 2</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    FRESULT fr;
+    TCHAR str[SZ_STR];
+
+    fr = <em>f_getcwd</em>(str, SZ_STR);  <span class="c">/* Get current directory path */</span>
+
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="chdrive.html">f_chdrive</a>, <a href="chdir.html">f_chdir</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/getfree.html b/MCUME_pico2/fatfs/documents/doc/getfree.html
new file mode 100644
index 0000000..5e4f419
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/getfree.html
@@ -0,0 +1,94 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/getfree.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_getfree</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_getfree</h2>
+<p>The f_getfree function gets number of the free clusters on the volume.</p>
+<pre>
+FRESULT f_getfree (
+  const TCHAR* <span class="arg">path</span>,  <span class="c">/* [IN] Logical drive number */</span>
+  DWORD* <span class="arg">nclst</span>,       <span class="c">/* [OUT] Number of free clusters */</span>
+  FATFS** <span class="arg">fatfs</span>       <span class="c">/* [OUT] Corresponding filesystem object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">logical drive</a>. A null-string means the default drive.</dd>
+<dt>nclst</dt>
+<dd>Pointer to the <tt>DWORD</tt> variable to store number of free clusters.</dd>
+<dt>fatfs</dt>
+<dd>Pointer to pointer that to store a pointer to the corresponding filesystem object.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Descriptions</h4>
+<p>The <tt>f_getfree</tt> function gets number of free clusters on the volume. The member <tt>csize</tt> in the filesystem object indicates number of sectors per cluster, so that the free space in unit of sector can be calcurated with this information. In case of FSINFO structure on the FAT32 volume is not in sync, this function can return an incorrect free cluster count. To avoid this problem, FatFs can be forced full FAT scan by <tt><a href="config.html#fs_nofsinfo">FF_FS_NOFSINFO</a></tt> option.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    FATFS *fs;
+    DWORD fre_clust, fre_sect, tot_sect;
+
+
+    <span class="c">/* Get volume information and free clusters of drive 1 */</span>
+    res = <em>f_getfree</em>("1:", &amp;fre_clust, &amp;fs);
+    if (res) die(res);
+
+    <span class="c">/* Get total sectors and free sectors */</span>
+    tot_sect = (fs->n_fatent - 2) * fs->csize;
+    fre_sect = fre_clust * fs->csize;
+
+    <span class="c">/* Print the free space (assuming 512 bytes/sector) */</span>
+    printf("%10lu KiB total drive space.\n%10lu KiB available.\n", tot_sect / 2, fre_sect / 2);
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="sfatfs.html">FATFS</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/getlabel.html b/MCUME_pico2/fatfs/documents/doc/getlabel.html
new file mode 100644
index 0000000..0ec6d0d
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/getlabel.html
@@ -0,0 +1,90 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/getlabel.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_getlabel</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_getlabel</h2>
+<p>The f_getlabel function returns volume label and volume serial number of a volume.</p>
+<pre>
+FRESULT f_getlabel (
+  const TCHAR* <span class="arg">path</span>,  <span class="c">/* [IN] Drive number */</span>
+  TCHAR* <span class="arg">label</span>,       <span class="c">/* [OUT] Volume label */</span>
+  DWORD* <span class="arg">vsn</span>          <span class="c">/* [OUT] Volume serial number */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">logical drive</a>. Null-string specifies the default drive.</dd>
+<dt>label</dt>
+<dd>Pointer to the buffer to store the volume label. If the volume has no label, a null-string will be returned. Set null pointer if this information is not needed. The buffer size should be shown below at least to avoid buffer overflow.<br>
+<table class="lst2">
+<tr><td>Configuration</td><td>FF_FS_EXFAT == 0</td><td>FF_FS_EXFAT == 1</td></tr>
+<tr><td>FF_USE_LFN == 0</td><td>12 items</td><td>-</td></tr>
+<tr><td>FF_LFN_UNICODE == 0</td><td>12 items</td><td>23 items</td></tr>
+<tr><td>FF_LFN_UNICODE == 1,3</td><td>12 items</td><td>12 items</td></tr>
+<tr><td>FF_LFN_UNICODE == 2</td><td>34 items</td><td>34 items</td></tr>
+</table>
+</dd>
+<dt>vsn</dt>
+<dd>Pointer to the <tt>DWORD</tt> variable to store the volume serial number. Set null pointer if this information is not needed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#use_label">FF_USE_LABEL</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    char str[12];
+
+    <span class="c">/* Get volume label of the default drive */</span>
+    <em>f_getlabel</em>("", str, 0);
+
+    <span class="c">/* Get volume label of the drive 2 */</span>
+    <em>f_getlabel</em>("2:", str, 0);
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<tt><a href="setlabel.html">f_setlabel</a></tt>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/gets.html b/MCUME_pico2/fatfs/documents/doc/gets.html
new file mode 100644
index 0000000..89d9560
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/gets.html
@@ -0,0 +1,65 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/gets.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_gets</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_gets</h2>
+<p>The f_gets reads a string from the file.</p>
+<pre>
+TCHAR* f_gets (
+  TCHAR* <span class="arg">buff</span>, <span class="c">/* [OUT] Read buffer */</span>
+  int <span class="arg">len</span>,     <span class="c">/* [IN] Size of the read buffer */</span>
+  FIL* <span class="arg">fp</span>      <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>buff</dt>
+<dd>Pointer to read buffer to store the read string.</dd>
+<dt>len</dt>
+<dd>Size of the read buffer in unit of item.</dd>
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>When the function succeeded, <tt class="arg">buff</tt> will be returuned.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The read operation continues until a <tt>'\n'</tt> is stored, reached end of the file or the buffer is filled with <tt>len - 1</tt> characters. The read string is terminated with a <tt>'\0'</tt>. When no character to read or any error occured during read operation, it returns a null pointer. The status of EOF and error can be examined with <tt>f_eof</tt> and <tt>f_error</tt> function.</p>
+<p>When FatFs is configured to Unicode API (<tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> >= 1</tt>), data types on the srting fuctions, <tt>f_putc</tt>, <tt>f_puts</tt>, <tt>f_printf</tt> and <tt>f_gets</tt>, is also switched to Unicode. The character encoding <em>on the file</em> to be read via this function is assumed as <a href="config.html#strf_encode"><tt>FF_STRF_ENCODE</tt></a>. If the character encoding on the file differs from that on the API, it is converted in this function. In this case, input characters with wrong encoding will be lost.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="read.html"><tt>f_read</tt></a> function. Available when <tt><a href="config.html#use_strfunc">FF_USE_STRFUNC</a> &gt;= 1</tt>. When it is set to 2, <tt>'\r'</tt>s contained in the file are stripped out.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="read.html">f_read</a>, <a href="putc.html">f_putc</a>, <a href="puts.html">f_puts</a>, <a href="printf.html">f_printf</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/lseek.html b/MCUME_pico2/fatfs/documents/doc/lseek.html
new file mode 100644
index 0000000..ffd1f62
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/lseek.html
@@ -0,0 +1,139 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/lseek.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_lseek</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_lseek</h2>
+<p>The f_lseek function moves the file read/write pointer of an open file object. It can also be used to expand the file size (cluster pre-allocation). </p>
+
+<pre>
+FRESULT f_lseek (
+  FIL*    <span class="arg">fp</span>,  <span class="c">/* [IN] File object */</span>
+  FSIZE_t <span class="arg">ofs</span>  <span class="c">/* [IN] Offset of file read/write pointer to be set */</span>
+);
+</pre>
+<pre>
+FRESULT f_rewind (
+  FIL*    <span class="arg">fp</span>   <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object.</dd>
+<dt>ofs</dt>
+<dd>Byte offset from top of the file to set read/write pointer. The data type <tt>FSIZE_t</tt> is an alias of either <tt>DWORD</tt>(32-bit) or <tt>QWORD</tt>(64-bit) depends on the configuration option <tt><a href="config.html#fs_exfat">FF_FS_EXFAT</a></tt>.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>File read/write ponter in the open file object points the data byte to be read/written at next read/write operation. It advances as the number of bytes read/written. The <tt>f_lseek</tt> function moves the file read/write pointer without any read/write operation to the file. The <tt>f_rewind</tt> function is impremented as a macro.</p>
+<pre>
+#define <em>f_rewind</em>(fp) f_lseek((fp), 0)
+</pre>
+<p>If an offset beyond the file size is specified in write mode, the file size is expanded to the specified offset. The file data in the expanded part is <em>undefined</em>, because no data is written to the file in this process. This is suitable to pre-allocate a data area to the file quickly for fast write operation. When a contiguous data area needs to be allocated to the file, use <tt>f_expand</tt> function instead. After the <tt>f_lseek</tt> function succeeded, the current read/write pointer should be checked in order to make sure the read/write pointer has been moved correctry. In case of the read/write pointer is not pointing expected offset, either of followings has been occured.</p>
+<ul>
+<li>End of file. The specified <tt class="arg">ofs</tt> was clipped at end of the file in read-only mode.</li>
+<li>Disk full. There is no free space on the volume to expand the file.</li>
+</ul>
+<p>The fast seek feature enables fast backward/long seek operations without FAT access by using an on-memory CLMT (cluster link map table). It is applied to <tt>f_read</tt> and <tt>f_write</tt> function as well, however, the file size cannot be expanded by <tt>f_write</tt>, <tt>f_lseek</tt> function while the file is at fast seek mode.</p>
+<p>The fast seek mode is available when <tt>FF_USE_FASTSEEK = 1</tt>. The CLMT must be created into the <tt>DWORD</tt> array prior to use the fast seek mode. To create the CLMT, set address of the <tt>DWORD</tt> array to the member <tt>cltbl</tt> in the open file object, set the size of array in unit of items to the <tt>cltbl[0]</tt> and then call <tt>f_lseek</tt> function with <tt class="arg">ofs</tt><tt> = CREATE_LINKMAP</tt>. After the function succeeded, no FAT access is occured in subsequent <tt>f_read</tt>, <tt>f_write</tt>, <tt>f_lseek</tt> function to the file. The number of items used or required is returned into the <tt>cltbl[0]</tt>. The number of items needed is (number of the file fragments + 1) * 2. For example, 12 items in the array will be used for the file fragmented in 5 portions. If the function failed with <tt>FR_NOT_ENOUGH_CORE</tt>, the size of given array is insufficient for the file.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 2</tt>. To use fast seek function, <tt><a href="config.html#use_fastseek">FF_USE_FASTSEEK</a></tt> needs to be set 1 to enable this feature.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Open file */</span>
+    fp = malloc(sizeof (FIL));
+    res = f_open(fp, "file.dat", FA_READ|FA_WRITE);
+    if (res) ...
+
+    <span class="c">/* Set read/write pointer to 5000 */</span>
+    res = <em>f_lseek</em>(fp, 5000);
+
+    <span class="c">/* Set read/write pointer to end of the file to append data */</span>
+    res = <em>f_lseek</em>(fp, f_size(fp));
+
+    <span class="c">/* Advance read/write pointer 3000 bytes */</span>
+    res = <em>f_lseek</em>(fp, f_tell(fp) + 3000);
+
+    <span class="c">/* Rewind read/write pointer 2000 bytes (take care on wraparound) */</span>
+    res = <em>f_lseek</em>(fp, f_tell(fp) - 2000);
+</pre>
+<pre>
+<span class="c">/* Cluster pre-allocation (to prevent buffer overrun on streaming write) */</span>
+
+    res = f_open(fp, recfile, FA_CREATE_NEW | FA_WRITE);   <span class="c">/* Create a file */</span>
+
+    res = <em>f_lseek</em>(fp, PRE_SIZE);             <span class="c">/* Expand file size (cluster pre-allocation) */</span>
+    if (res || f_tell(fp) != PRE_SIZE) ...   <span class="c">/* Check if the file has been expanded successfly */</span>
+
+    res = <em>f_lseek</em>(fp, OFS_DATA);             <span class="c">/* Record data stream with free from cluster allocation delay */</span>
+    ...                                      <span class="c">/* Write operation should be aligned to sector boundary to optimize the write throughput */</span>
+
+    res = f_truncate(fp);                    <span class="c">/* Truncate unused area */</span>
+    res = <em>f_lseek</em>(fp, OFS_HEADER);           <span class="c">/* Set file header */</span>
+    ...
+
+    res = f_close(fp);
+</pre>
+<pre>
+<span class="c">/* Using fast seek mode */</span>
+
+    DWORD clmt[SZ_TBL];                    <span class="c">/* Cluster link map table buffer */</span>
+
+    res = f_open(fp, fname, FA_READ | FA_WRITE);   <span class="c">/* Open a file */</span>
+
+    res = <em>f_lseek</em>(fp, ofs1);               <span class="c">/* This is normal seek (cltbl is nulled on file open) */</span>
+
+    fp-&gt;cltbl = clmt;                      <span class="c">/* Enable fast seek mode (cltbl != NULL) */</span>
+    clmt[0] = SZ_TBL;                      <span class="c">/* Set table size */</span>
+    res = <em>f_lseek</em>(fp, CREATE_LINKMAP);     <span class="c">/* Create CLMT */</span>
+    ...
+
+    res = <em>f_lseek</em>(fp, ofs2);               <span class="c">/* This is fast seek */</span>
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="truncate.html">f_truncate</a>, <a href="expand.html">f_expand</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/mkdir.html b/MCUME_pico2/fatfs/documents/doc/mkdir.html
new file mode 100644
index 0000000..de32f83
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/mkdir.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/mkdir.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_mkdir</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_mkdir</h2>
+<p>The f_mkdir function creates a new directory.</p>
+<pre>
+FRESULT f_mkdir (
+  const TCHAR* <span class="arg">path</span> <span class="c">/* [IN] Directory name */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">directory name</a> to create. </dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Value</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#ex">FR_EXIST</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>This function creates a new directory. To remove a directory, use <a href="unlink.html"><tt>f_unlink</tt></a> function.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    res = <em>f_mkdir</em>("sub1");
+    if (res) die(res);
+    res = <em>f_mkdir</em>("sub1/sub2");
+    if (res) die(res);
+    res = <em>f_mkdir</em>("sub1/sub2/sub3");
+    if (res) die(res);
+</pre>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/mkfs.html b/MCUME_pico2/fatfs/documents/doc/mkfs.html
new file mode 100644
index 0000000..f40ebb0
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/mkfs.html
@@ -0,0 +1,127 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/mkfs.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_mkfs</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_mkfs</h2>
+<p>The f_mkfs function creates an FAT/exFAT volume on the logical drive.</p>
+<pre>
+FRESULT f_mkfs (
+  const TCHAR* <span class="arg">path</span>,   <span class="c">/* [IN] Logical drive number */</span>
+  const MKFS_PARM* <span class="arg">opt</span>,<span class="c">/* [IN] Format options */</span>
+  void* <span class="arg">work</span>,          <span class="c">/* [-]  Working buffer */</span>
+  UINT <span class="arg">len</span>             <span class="c">/* [IN] Size of working buffer */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string specifies the <a href="filename.html">logical drive</a> to be formatted. If it does not have a drive number in it, it means to specify the default drive. The logical drive may or may not have been mounted for the format process.</dd>
+<dt>opt</dt>
+<dd>Specifies the format option structure <tt>MKFS_PARM</tt> holding format options. If a null pointer is given, it gives the function every option in default value. The structure has five members in order of described below:<br>
+<dl class="par">
+<dt>BYTE fmt</dt>
+<dd>Specifies a combination of FAT type flags, <tt>FM_FAT</tt>, <tt>FM_FAT32</tt>, <tt>FM_EXFAT</tt> and bitwise-or of these three, <tt>FM_ANY</tt>. <tt>FM_EXFAT</tt> is ignored when exFAT is not enabled. These flags specify which type of FAT volume to be created. If two or more types are specified, one out of them will be selected depends on the volume size and <tt class="arg">au_size</tt>. The flag <tt>FM_SFD</tt> specifies to create the volume on the drive in SFD format. The default value is <tt>FM_ANY</tt>.</dd>
+<dt>BYTE n_fat</dt>
+<dd>Specifies number of FAT copies on the FAT/FAT32 volume. Valid value for this member is 1 or 2. The default value (0) and any invaid value gives 1. If the FAT type is exFAT, this member has no effect.</dd>
+<dt>UINT n_align</dt>
+<dd>Specifies alignment of the volume data area (file allocation pool, usually erase block boundary of flash memory media) in unit of sector. The valid value for this member is between 1 and 32768 inclusive in power of 2. If a zero (the default value) or any invalid value is given, the function obtains the block size from lower layer with <tt>disk_ioctl</tt> function.</dd>
+<dt>DWORD au_size</dt>
+<dd>Specifies size of the allocation unit (cluter) in unit of byte. The valid value is power of 2 between sector size and 128 * sector size inclusive for FAT/FAT32 volume, or up to 16 MB for exFAT volume. If a zero (default value) or any invalid value is given, the function uses default allocation unit size depends on the volume size.</dd>
+<dt>UINT n_root</dt>
+<dd>Specifies number of root directory entries on the FAT volume. Valid value for this member is up to 32768 and aligned to sector size / 32. The default value (0) and any invaid value gives 512. If the FAT type is FAT32 or exFAT, this member has no effect.</dd>
+</dl>
+<dt>work</dt>
+<dd>Pointer to the working buffer used for the format process. If a null pointer is given with <tt><a href="config.html#use_lfn">FF_USE_LFN</a> == 3</tt>, the function uses a <tt>len</tt> bytes of heap memory in this function.</dd>
+<dt>len</dt>
+<dd>Size of the working buffer in unit of byte. It needs to be <tt>FF_MAX_SS</tt> at least. Plenty of working buffer reduces number of write transactions to the drive, thus the format process will finish quickly.</dd>
+</dl>
+</div>
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ma">FR_MKFS_ABORTED</a>,
+<a href="rc.html#ip">FR_INVALID_PARAMETER</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The FAT sub-type, FAT12/FAT16/FAT32, of FAT volume except exFAT is determined by only number of clusters on the volume and nothing else, according to the FAT specification issued by Microsoft. Thus the FAT sub-type of created volume depends on the volume size and the cluster size. In case of the combination of FAT type and cluter size specified by argument is not valid for the volume size, the function will fail with <tt>FR_MKFS_ABORTED</tt>.</p>
+<p>The allocation unit, also known as <em>cluster</em>, is a unit of disk space allocation for files. When the size of allocation unit is 32768 bytes, a file with 100 bytes in size occupies 32768 bytes of disk space. The space efficiency of disk usage gets worse as increasing size of allocation unit, but, on the other hand, the read/write performance increases. Therefore the size of allocation unit is a trade-off between space efficiency and performance. For the large volumes in GB order, 32768 bytes or larger, automatically selected by default, is recommended for most case unless extremely many small files are created in the volume.</p>
+<p>When the logical drive to be formatted is associated with a physical drive (<tt><a href="config.html#multi_partition">FF_MULTI_PARTITION</a> == 0</tt> or <tt>VolToPart[].pt == 0</tt>) and <tt>FM_SFD</tt> flag is not specified, a partition occupies entire drive space is created and then the FAT volume is created in the partition. When <tt>FM_SFD</tt> flag is specified, the FAT volume is created without any disk partitioning.</p>
+<p>When the logical drive to be formatted is associated with a specific partition by multiple partition feature (<tt>FF_MULTI_PARTITION == 1</tt> and <tt>VolToPart[].pt &gt; 0</tt>), the FAT volume is created in the partition of the physical drive specified by <a href="filename.html#vol">volume mapping table</a> and <tt>FM_SFD</tt> flag is ignored. The hosting physical drive needs to be partitioned with <tt>f_fdisk</tt> function or any partitioning tool prior to create the FAT volume with this function. If the partition is not exist, the function aborts with <tt>FR_MKFS_ABORTED</tt>.</p>
+<p>There are three standard disk partitioning formats, MBR, GPT and SFD. The MBR format, also known as FDISK format, is usually used for harddisk, memory card and U disk. It can divide a physical drive into one or more partitions with a partition table. The GPT, GUID Partition Table, is a newly defined patitioning format for large storage devices. FatFs suppors the GPT only when 64-bit LBA is enabled. The SFD, Super-Floppy Disk, is non-partitioned disk format. The FAT volume is located at LBA 0 and occupies the entire physical drive without any disk partitioning. It is usually used for floppy disk, optical disk and most super-floppy media. Some combination of systems and media support only either partitioned format or non-partitioned format and the other is not supported.</p>
+<p>Some systems manage the partitions in the on-board storage in non-standard format. The partitions are mapped as physical drives identified by <tt class="arg">pdrv</tt> in <tt>disk_*</tt> functions. For such systems, SFD format is suitable to create the FAT volume in the partition.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READOLNY</a> == 0</tt> and <tt><a href="config.html#use_mkfs">FF_USE_MKFS</a> == 1</tt>.</p>
+</div>
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+<span class="c">/* Format default drive and create a file */</span>
+int main (void)
+{
+    FATFS fs;           <span class="c">/* Filesystem object */</span>
+    FIL fil;            <span class="c">/* File object */</span>
+    FRESULT res;        <span class="c">/* API result code */</span>
+    UINT bw;            <span class="c">/* Bytes written */</span>
+    BYTE work[FF_MAX_SS]; <span class="c">/* Work area (larger is better for processing time) */</span>
+
+
+    <span class="c">/* Format the default drive with default parameters */</span>
+    res = <em>f_mkfs</em>("", 0, work, sizeof work);
+    if (res) ...
+
+    <span class="c">/* Give a work area to the default drive */</span>
+    f_mount(&amp;fs, "", 0);
+
+    <span class="c">/* Create a file as new */</span>
+    res = f_open(&amp;fil, "hello.txt", FA_CREATE_NEW | FA_WRITE);
+    if (res) ...
+
+    <span class="c">/* Write a message */</span>
+    f_write(&amp;fil, "Hello, World!\r\n", 15, &amp;bw);
+    if (bw != 15) ...
+
+    <span class="c">/* Close the file */</span>
+    f_close(&amp;fil);
+
+    <span class="c">/* Unregister work area */</span>
+    f_mount(0, "", 0);
+
+    ...
+</pre>
+</div>
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><a href="../res/mkfs.xlsx">Example of volume size and format parameters</a>, <a href="filename.html#vol">Volume management</a>, <tt><a href="fdisk.html">f_fdisk</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/mount.html b/MCUME_pico2/fatfs/documents/doc/mount.html
new file mode 100644
index 0000000..57f40be
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/mount.html
@@ -0,0 +1,122 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/mount.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_mount</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_mount</h2>
+<p>The f_mount fucntion gives work area to the FatFs module.</p>
+<pre>
+FRESULT f_mount (
+  FATFS*       <span class="arg">fs</span>,    <span class="c">/* [IN] Filesystem object */</span>
+  const TCHAR* <span class="arg">path</span>,  <span class="c">/* [IN] Logical drive number */</span>
+  BYTE         <span class="arg">opt</span>    <span class="c">/* [IN] Initialization option */</span>
+);
+</pre>
+<pre>
+FRESULT f_unmount (
+  const TCHAR* <span class="arg">path</span>   <span class="c">/* [IN] Logical drive number */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fs</dt>
+<dd>Pointer to the filesystem object to be registered and cleared. Null pointer unregisters the registered filesystem object.</dd>
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">logical drive</a>. The string without drive number means the default drive.</dd>
+<dt>opt</dt>
+<dd>Mounting option. 0: Do not mount now (to be mounted on the first access to the volume), 1: Force mounted the volume to check if it is ready to work.</dd>
+</dl>
+</div>
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>FatFs requires work area (<em>filesystem object</em>) for each logical drives (FAT volumes). Prior to perform any file/directory operations, a filesystem object needs to be registered with <tt>f_mount</tt> function for the logical drive. The file/directory API functions get ready to work after this procedure. Some volume management functions, <tt>f_mkfs</tt>, <tt>f_fdisk</tt> and <tt>f_setcp</tt>, do not want a filesystem object.</p>
+<p>The <tt>f_mount</tt> function registers/unregisters a filesystem object to the FatFs module as follows:</p>
+<ol>
+<li>Determines the logical drive which specified by <tt class="arg">path</tt>.</li>
+<li>Clears and unregisters the regsitered work area of the volume if exist.</li>
+<li>Clears and registers the new work area to the volume if <tt class="arg">fs</tt> is not NULL.</li>
+<li>Performs volume mount process to the volume if forced mounting is specified.</li>
+</ol>
+<p>If there is any open object of file or directory on the logical drive, the object will be invalidated by this function.</p>
+<p>If forced mounting is not specified (<tt>opt = 0</tt>), this function always succeeds regardless of the physical drive status. It only clears (de-initializes) the given work area and registers its address to the internal table and no activity of the physical drive in this function. The volume mount process will be attempted on subsequent file/directroy function if the filesystem object is not initialized. (delayed mounting) The volume mount processes, initialize the corresponding physical drive, find the FAT volume in it and then initialize the work area, is performed in the subsequent file/directory functions when either of following conditions is true.</p>
+<ul>
+<li>Filesystem object has not been initialized. It is de-initialized by <tt>f_mount</tt> function.</li>
+<li>Physical drive is not initialized. It is de-initialized by system reset or media removal.</li>
+</ul>
+<p>If the function with forced mounting (<tt>opt = 1</tt>) failed with <tt>FR_NOT_READY</tt>, it means that the filesystem object has been registered successfully but the volume is currently not ready to work. The volume mount process will be attempted on subsequent file/directroy function.</p>
+<p>If implementation of the disk I/O layer lacks asynchronous media change detection, application program needs to perform <tt>f_mount</tt> function after each media change to force cleared the filesystem object.</p>
+<p>To unregister the work area, specify a NULL to the <tt class="arg">fs</tt>, and then the work area can be discarded. <tt>f_unmount</tt> function is implemented as a macro.</p>
+<pre>
+#define <em>f_unmount</em>(path) f_mount(0, path, 0)
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+int main (void)
+{
+    FATFS *fs;     <span class="c">/* Ponter to the filesystem object */</span>
+
+
+    fs = malloc(sizeof (FATFS));           <span class="c">/* Get work area for the volume */</span>
+    <em>f_mount</em>(fs, "", 0);                    <span class="c">/* Mount the default drive */</span>
+
+    f_open(...                             <span class="c">/* Here any file API can be used */</span>
+
+    ...
+
+    <em>f_mount</em>(fs, "", 0);                    <span class="c">/* Re-mount the default drive to reinitialize the filesystem */</span>
+
+    ...
+
+    <em>f_mount</em>(0, "", 0);                     <span class="c">/* Unmount the default drive */</span>
+    free(fs);                              <span class="c">/* Here the work area can be discarded */</span>
+
+    ...
+}
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a></tt>, <tt><a href="sfatfs.html">FATFS</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/open.html b/MCUME_pico2/fatfs/documents/doc/open.html
new file mode 100644
index 0000000..cc8b87a
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/open.html
@@ -0,0 +1,185 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/open.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_open</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_open</h2>
+<p>The f_open function opens a file.</p>
+<pre>
+FRESULT f_open (
+  FIL* <span class="arg">fp</span>,           <span class="c">/* [OUT] Pointer to the file object structure */</span>
+  const TCHAR* <span class="arg">path</span>, <span class="c">/* [IN] File name */</span>
+  BYTE <span class="arg">mode</span>          <span class="c">/* [IN] Mode flags */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the blank file object structure.</dd>
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">file name</a> to open or create.</dd>
+<dt>mode</dt>
+<dd>Mode flags that specifies the type of access and open method for the file. It is specified by a combination of following flags.<br>
+<table class="lst">
+<tr><th>Flags</th><th>Meaning</th></tr>
+<tr><td>FA_READ</td><td>Specifies read access to the file. Data can be read from the file.</tr>
+<tr><td>FA_WRITE</td><td>Specifies write access to the file. Data can be written to the file. Combine with <tt>FA_READ</tt> for read-write access.</td></tr>
+<tr><td>FA_OPEN_EXISTING</td><td>Opens a file. The function fails if the file is not existing. (Default)</td></tr>
+<tr><td>FA_CREATE_NEW</td><td>Creates a new file. The function fails with <tt>FR_EXIST</tt> if the file is existing.</td></tr>
+<tr><td>FA_CREATE_ALWAYS</td><td>Creates a new file. If the file is existing, it will be truncated and overwritten.</td></tr>
+<tr><td>FA_OPEN_ALWAYS</td><td>Opens the file if it is existing. If not, a new file will be created.</td></tr>
+<tr><td>FA_OPEN_APPEND</td><td>Same as <tt>FA_OPEN_ALWAYS</tt> except the read/write pointer is set end of the file.</td></tr>
+</table>
+Mode flags in POSIX fopen() function corresponds to FatFs mode flags as follows:<br>
+<table class="lst2">
+<tr><th>POSIX</th><th>FatFs</th></tr>
+<tr><td>"r"</td><td>FA_READ</td></tr>
+<tr><td>"r+"</td><td>FA_READ | FA_WRITE</td></tr>
+<tr><td>"w"</td><td>FA_CREATE_ALWAYS | FA_WRITE</td></tr>
+<tr><td>"w+"</td><td>FA_CREATE_ALWAYS | FA_WRITE | FA_READ</td></tr>
+<tr><td>"a"</td><td>FA_OPEN_APPEND | FA_WRITE</td></tr>
+<tr><td>"a+"</td><td>FA_OPEN_APPEND | FA_WRITE | FA_READ</td></tr>
+<tr><td>"wx"</td><td>FA_CREATE_NEW | FA_WRITE</td></tr>
+<tr><td>"w+x"</td><td>FA_CREATE_NEW | FA_WRITE | FA_READ</td></tr>
+</table>
+</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#nf">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#ex">FR_EXIST</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#lo">FR_LOCKED</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>,
+<a href="rc.html#tf">FR_TOO_MANY_OPEN_FILES</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_open</tt> function opens a file and creates a <em>file object</em>. The file object is an identifier for subsequent operations to the file. Open file should be closed with <a href="close.html"><tt>f_close</tt></a> function after the session of the file access. If any change to the file has been made and not closed prior to power off, media removal or re-mount, or the file can be collapsed.</p>
+<p>If duplicated file open is needed, read <a href="appnote.html#dup">here</a> carefully. However duplicated open of a file with any write mode flag is always prohibited.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available. Only <tt>FA_READ</tt> and <tt>FA_OPEN_EXISTING</tt> are available for the mode flags when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+<span class="c">/* Read a text file and display it */</span>
+
+FATFS FatFs;   <span class="c">/* Work area (filesystem object) for logical drive */</span>
+
+int main (void)
+{
+    FIL fil;        <span class="c">/* File object */</span>
+    char line[100]; <span class="c">/* Line buffer */</span>
+    FRESULT fr;     <span class="c">/* FatFs return code */</span>
+
+
+    <span class="c">/* Give a work area to the default drive */</span>
+    f_mount(&amp;FatFs, "", 0);
+
+    <span class="c">/* Open a text file */</span>
+    fr = <em>f_open</em>(&amp;fil, "message.txt", FA_READ);
+    if (fr) return (int)fr;
+
+    <span class="c">/* Read every line and display it */</span>
+    while (f_gets(line, sizeof line, &amp;fil)) {
+        printf(line);
+    }
+
+    <span class="c">/* Close the file */</span>
+    f_close(&amp;fil);
+
+    return 0;
+}
+</pre>
+<pre>
+<span class="c">/* Copy a file "file.bin" on the drive 1 to drive 0 */</span>
+
+int main (void)
+{
+    FATFS fs0, fs1;      <span class="c">/* Work area (filesystem object) for logical drives */</span>
+    FIL fsrc, fdst;      <span class="c">/* File objects */</span>
+    BYTE buffer[4096];   <span class="c">/* File copy buffer */</span>
+    FRESULT fr;          <span class="c">/* FatFs function common result code */</span>
+    UINT br, bw;         <span class="c">/* File read/write count */</span>
+
+
+    <span class="c">/* Give work areas to each logical drive */</span>
+    f_mount(&amp;fs0, "0:", 0);
+    f_mount(&amp;fs1, "1:", 0);
+
+    <span class="c">/* Open source file on the drive 1 */</span>
+    fr = <em>f_open</em>(&amp;fsrc, "1:file.bin", FA_READ);
+    if (fr) return (int)fr;
+
+    <span class="c">/* Create destination file on the drive 0 */</span>
+    fr = <em>f_open</em>(&amp;fdst, "0:file.bin", FA_WRITE | FA_CREATE_ALWAYS);
+    if (fr) return (int)fr;
+
+    <span class="c">/* Copy source to destination */</span>
+    for (;;) {
+        fr = f_read(&amp;fsrc, buffer, sizeof buffer, &amp;br); <span class="c">/* Read a chunk of data from the source file */</span>
+        if (br == 0) break; <span class="c">/* error or eof */</span>
+        fr = f_write(&amp;fdst, buffer, br, &amp;bw);           <span class="c">/* Write it to the destination file */</span>
+        if (bw &lt; br) break; <span class="c">/* error or disk full */</span>
+    }
+
+    <span class="c">/* Close open files */</span>
+    f_close(&amp;fsrc);
+    f_close(&amp;fdst);
+
+    <span class="c">/* Unregister work area prior to discard it */</span>
+    f_unmount("0:");
+    f_unmount("1:");
+
+    return (int)fr;
+}
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="read.html">f_read</a>, <a href="write.html">f_write</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a>, <a href="sfatfs.html">FATFS</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/opendir.html b/MCUME_pico2/fatfs/documents/doc/opendir.html
new file mode 100644
index 0000000..215c37a
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/opendir.html
@@ -0,0 +1,75 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/opendir.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_opendir</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_opendir</h2>
+<p>The f_opendir function opens a directory.</p>
+<pre>
+FRESULT f_opendir (
+  DIR* <span class="arg">dp</span>,           <span class="c">/* [OUT] Pointer to the directory object structure */</span>
+  const TCHAR* <span class="arg">path</span>  <span class="c">/* [IN] Directory name */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>dp</dt>
+<dd>Pointer to the blank directory object to create a new one.</dd>
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">directory name</a> to be opened.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>,
+<a href="rc.html#tf">FR_TOO_MANY_OPEN_FILES</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_opendir</tt> function opens an exsisting directory and creates a directory object for subsequent <tt>f_readdir</tt> function.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 1</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="readdir.html">f_readdir</a>, <a href="closedir.html">f_closedir</a>, <a href="sdir.html">DIR</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/printf.html b/MCUME_pico2/fatfs/documents/doc/printf.html
new file mode 100644
index 0000000..eb64e8d
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/printf.html
@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/printf.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_printf</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_printf</h2>
+<p>The f_printf function writes formatted string to the file.</p>
+<pre>
+int f_printf (
+  FIL* <span class="arg">fp</span>,          <span class="c">/* [IN] File object */</span>
+  const TCHAR* <span class="arg">fmt</span>, <span class="c">/* [IN] Format stirng */</span>
+  ...
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+<dt>fmt</dt>
+<dd>Pointer to the null <tt>'\0'</tt> terminated format string. The terminator character will not be output.</dd>
+<dt>...</dt>
+<dd>Optional arguments...</dd>
+
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>When the string was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or an error, a negative value will be returned.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The format control directive is a sub-set of standard library shown as follows:</p>
+<pre>
+    %[flag][width][precision][size]type
+</pre>
+<dl>
+<dt>flag</dt><dd>Padding option. A <tt>-</tt> specifies left-aligned. A <tt>0</tt> specifies zero padded. The default setting is in right-aligned and space padded.</dd>
+<dt>width</dt><dd>Minimum width of the field, <tt>1-99</tt> or <tt>*</tt>. If the width of generated string is less than the minimum width, rest field is padded with spaces or zeros. An <tt>*</tt> specifies the value comes from an argument in int type. The default setting is zero.</dd>
+<dt>precision</dt><dd>Specifies number of fractional digits or maximum width of string, <tt>.0-.99</tt> or <tt>.*</tt>. If the number is omitted, it is same as <tt>.0</tt>. Default setting is 6 for number and no limit for string.</dd>
+<dt>size</dt><dd>Specifies size of integer argument, <tt>l</tt>(long) and <tt>ll</tt>(long long). If <tt>sizeof (long) == sizeof (int)</tt> is true (this is typical of 32-bit systems), prefix <tt>l</tt> can be omitted for long integer argument. The default size is int for integer argument and floating point argument is always assumed double as the default argument promotion.</dd>
+<dt>type</dt><dd>Specifies type of the output format and the argument as shown below. The length of generated string is in assumtion of int is 32-bit.
+<table class="lst1">
+<tr><th>Type</th><th>Format</th><th>Argument</th><th>Length</th></tr>
+<tr><td><tt>c</tt></td><td>Character</td><td rowspan="6"><tt>int</tt>,<br><tt>long</tt>,<br><tt>long long</tt></td><td>1 character.</td></tr>
+<tr><td><tt>d</tt></td><td>Signed&nbsp;decimal</td><td>1 to 11 (20 for ll) characters.</td></tr>
+<tr><td><tt>u</tt></td><td>Unsigned&nbsp;decimal</td><td>1 to 10 (20 for ll) characters.</td></tr>
+<tr><td><tt>o</tt></td><td>Unsigned&nbsp;octal</td><td>1 to 11 (22 for ll) characters.</td></tr>
+<tr><td><tt>x X</tt></td><td>Unsigned&nbsp;hexdecimal</td><td>1 to 8 (16 for ll) characters.</td></tr>
+<tr><td><tt>b</tt></td><td>Unsigned&nbsp;binary</td><td>1 to 32 characters. Limited to lower 32 digits when ll is specified.</td></tr>
+<tr><td><tt>s</tt></td><td>String</td><td><tt>TCHAR*</tt></td><td>As input string. Null pointer generates a null string.</td></tr>
+<tr><td><tt>f</tt></td><td>Floating point<br>(decimal)</td><td rowspan="2"><tt>double</tt></td><td>1 to 31 characters. If the number of characters exceeds 31, it writes <tt>"±OV"</tt>. Not a number and infinite write <tt>"NaN"</tt> and <tt>"±INF"</tt>.</td></tr>
+<tr><td><tt>e E</tt></td><td>Floating point<br>(e notation)</td><td>4 to 31 characters. If the number of characters exceeds 31 or exponent exceeds +99, it writes <tt>"±OV"</tt>.</td></tr>
+</table>
+</dd>
+</dl>
+<p>When FatFs is configured for Unicode API (<tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> &gt;= 1</tt>), character encoding on the string fuctions, <tt>f_putc</tt>, <tt>f_puts</tt>, <tt>f_printf</tt> and <tt>f_gets</tt> function, is also switched to Unicode. The Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, should not be divided into two function calls, or the character will be lost. The character encoding <em>on the file</em> to be written via this function is selected by <tt><a href="config.html#strf_encode">FF_STRF_ENCODE</a></tt>. The characters with wrong encoding or invalid for the output encoding will be lost.</p>
+<p>If <tt>sprintf</tt> is used in the project and code conversion is not needed, <tt>f_write</tt> with <tt>sprintf</tt> will be efficient in code size and performance rather than <tt>f_printf</tt>.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="write.html"><tt>f_write</tt></a> function. Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_strfunc">FF_USE_STRFUNC</a> &gt;= 1</tt>. When <tt>FF_USE_STRFUNC == 2</tt>, <tt>'\n'</tt>s in the generated string are written as <tt>'\r'+'\n'</tt> each.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <em>f_printf</em>(fp, "%d", 1234);             <span class="c">/* "1234" */</span>
+    <em>f_printf</em>(fp, "%6d,%3d%%", -200, 5);   <span class="c">/* "  -200,  5%" */</span>
+    <em>f_printf</em>(fp, "%-6u", 100);            <span class="c">/* "100   " */</span>
+    <em>f_printf</em>(fp, "%ld", 12345678);        <span class="c">/* "12345678" */</span>
+    <em>f_printf</em>(fp, "%llu", 0x100000000);    <span class="c">/* "4294967296"   (<a href="config.html#print_lli">FF_PRINT_LLI</a>) */</span>
+    <em>f_printf</em>(fp, "%lld", -1LL);           <span class="c">/* "-1"           (FF_PRINT_LLI) */</span>
+    <em>f_printf</em>(fp, "%04x", 0xA3);           <span class="c">/* "00a3" */</span>
+    <em>f_printf</em>(fp, "%08lX", 0x123ABC);      <span class="c">/* "00123ABC" */</span>
+    <em>f_printf</em>(fp, "%016b", 0x550F);        <span class="c">/* "0101010100001111" */</span>
+    <em>f_printf</em>(fp, "%*d", 6, 100);          <span class="c">/* "   100" */</span>
+    <em>f_printf</em>(fp, "%s", "abcdefg");        <span class="c">/* "abcdefg" */</span>
+    <em>f_printf</em>(fp, "%5s", "abc");           <span class="c">/* "  abc" */</span>
+    <em>f_printf</em>(fp, "%-5s", "abc");          <span class="c">/* "abc  " */</span>
+    <em>f_printf</em>(fp, "%.5s", "abcdefg");      <span class="c">/* "abcde" */</span>
+    <em>f_printf</em>(fp, "%-5.2s", "abcdefg");    <span class="c">/* "ab   " */</span>
+    <em>f_printf</em>(fp, "%c", 'a');              <span class="c">/* "a" */</span>
+    <em>f_printf</em>(fp, "%12f", 10.0);           <span class="c">/* "   10.000000" (<a href="config.html#print_fp">FF_PRINT_FLOAT</a>) */</span>
+    <em>f_printf</em>(fp, "%.4E", 123.45678);      <span class="c">/* "1.2346E+02"   (FF_PRINT_FLOAT) */</span>
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="putc.html">f_putc</a>, <a href="puts.html">f_puts</a>, <a href="gets.html">f_gets</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/putc.html b/MCUME_pico2/fatfs/documents/doc/putc.html
new file mode 100644
index 0000000..747b5fd
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/putc.html
@@ -0,0 +1,60 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/putc.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_putc</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_putc</h2>
+<p>The f_putc funciton puts a character to the file.</p>
+<pre>
+int f_putc (
+  TCHAR <span class="arg">chr</span>,  <span class="c">/* [IN] A character to write */</span>
+  FIL* <span class="arg">fp</span>     <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>chr</dt>
+<dd>A character to write.</dd>
+<dt>fp</dt>
+<dd>Pointer to the open file object structuer.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>When the character was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or any error, a negative value will be returned.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>When FatFs is configured for Unicode API (<tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> &gt;= 1</tt>), character encoding on the string fuctions, <tt>f_putc</tt>, <tt>f_puts</tt>, <tt>f_printf</tt> and <tt>f_gets</tt> function, is also switched to Unicode. The character encoding <em>on the file</em> to be read/written via those functions is selected by <tt><a href="config.html#strf_encode">FF_STRF_ENCODE</a></tt>. The Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, cannot be written with this function.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="write.html"><tt>f_write</tt></a> function. Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_strfunc">FF_USE_STRFUNC</a> &gt;= 1</tt>. When <tt>FF_USE_STRFUNC == 2</tt>, a <tt>'\n'</tt> is output as <tt>'\r'+'\n'</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="puts.html">f_puts</a>, <a href="printf.html">f_printf</a>, <a href="gets.html">f_gets</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/puts.html b/MCUME_pico2/fatfs/documents/doc/puts.html
new file mode 100644
index 0000000..3695942
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/puts.html
@@ -0,0 +1,61 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/puts.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_puts</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_puts</h2>
+<p>The f_puts function writes a string to the file.</p>
+<pre>
+int f_puts (
+  const TCHAR* <span class="arg">str</span>, <span class="c">/* [IN] String */</span>
+  FIL* <span class="arg">fp</span>           <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>str</dt>
+<dd>Pointer to the null terminated string to be written. The terminator character will not be written.</dd>
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Value</h4>
+<p>When the string was written successfuly, it returns number of character encoding units written to the file. When the function failed due to disk full or any error, a negative value will be returned.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>When FatFs is configured for Unicode API (<tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> &gt;= 1</tt>), character encoding on the string fuctions, <tt>f_putc</tt>, <tt>f_puts</tt>, <tt>f_printf</tt> and <tt>f_gets</tt> function, is also switched to Unicode. The input Unicode characters in multiple encoding unit, such as surrogate pair and multi-byte sequence, should not be divided into two function calls, or the character will be lost. The character encoding <em>on the file</em> to be written via this functions is selected by <tt><a href="config.html#strf_encode">FF_STRF_ENCODE</a></tt>. The characters with wrong encoding or invalid for the output encoding will be lost.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>This is a wrapper function of <a href="write.html"><tt>f_write</tt></a> function. Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_strfunc">FF_USE_STRFUNC</a> &gt;= 1</tt>. When <tt>FF_USE_STRFUNC == 2</tt>, <tt>'\n'</tt>s contained in the input string are output as <tt>'\r'+'\n'</tt> each.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="putc.html">f_putc</a>, <a href="printf.html">f_printf</a>, <a href="gets.html">f_gets</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/rc.html b/MCUME_pico2/fatfs/documents/doc/rc.html
new file mode 100644
index 0000000..8f7fffa
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/rc.html
@@ -0,0 +1,135 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/rc.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - API Return Code</title>
+</head>
+
+<body>
+<h1>Return Code of API Functions</h1>
+<p>Most of API functions return common result code in enum type <tt>FRESULT</tt>. When an API function succeeded, it returns zero (<tt>FR_OK</tt>), otherwise it returns non-zero value indicates type of error.</p>
+
+<dl class="ret">
+
+<dt id="ok">FR_OK (0)</dt>
+<dd>The function succeeded.</dd>
+
+<dt id="de">FR_DISK_ERR</dt>
+<dd>The lower layer, <tt>disk_read</tt>, <tt>disk_write</tt> or <tt>disk_ioctl</tt> function, reported that an unrecoverable hard error occured.<br>Note that if once this error occured at any operation to an open file, the file object is aborted and any operations to the file except for close will be rejected.</dd>
+
+<dt id="ie">FR_INT_ERR</dt>
+<dd>Assertion failed and an insanity is detected in the internal process. One of the following possibilities is suspected.
+<ul>
+<li>Work area (file system object, file object or etc...) has been broken by stack overflow or something. This is the reason in most case.</li>
+<li>There is an error of the FAT structure on the volume.</li>
+<li>There is a bug in the FatFs module itself.</li>
+<li>Wrong lower layer implementation.</li>
+</ul>
+Note that if once this error occured in the operation to an open file, the file object is aborted and any operation to the file except for close will be rejected.
+</dd>
+
+<dt id="nr">FR_NOT_READY</dt>
+<dd>The lower layer, <a href="dinit.html"><tt>disk_initialize</tt></a> function, reported that the storage device could not be got ready to work. One of the following possibilities is suspected.
+<ul>
+<li>No medium in the drive.</li>
+<li>Wrong lower layer implementation.</li>
+<li>Wrong hardware configuration.</li>
+<li>The storage device has broken.</li>
+</ul>
+</dd>
+
+<dt id="nf">FR_NO_FILE</dt>
+<dd>Could not find the file in the directory.</dd>
+
+<dt id="np">FR_NO_PATH</dt>
+<dd>Could not find the path. A directory in the path name could not be found.</dd>
+
+<dt id="in">FR_INVALID_NAME</dt>
+<dd>The given string is invalid as a <a href="filename.html">path name</a>. One of the following possibilities is suspected.
+<ul>
+<li>There is a character not allowed for the file name.</li>
+<li>The file name is out of 8.3 format. (at non-LFN cfg.)</li>
+<li><tt>FF_MAX_LFN</tt> is insufficient for the file name. (at LFN cfg.)</li>
+<li>There is a character encoding error in the string.</li>
+</ul>
+</dd>
+
+<dt id="dn">FR_DENIED</dt>
+<dd>The required access was denied due to one of the following reasons:
+<ul>
+<li>Write mode open against the read-only file. (f_open)</li>
+<li>Deleting the read-only file or directory. (f_unlink)</li>
+<li>Deleting the non-empty directory or current directory. (f_unlink)</li>
+<li>Reading the file opened without <tt>FA_READ</tt> flag. (f_read)</li>
+<li>Any modification to the file opened without <tt>FA_WRITE</tt> flag. (f_write, f_truncate, f_expand)</li>
+<li>Could not create the object due to root directory full or disk full. (f_open, f_mkdir)</li>
+<li>Could not find a contiguous area for the file. (f_expand)</li>
+</ul>
+</dd>
+
+<dt id="ex">FR_EXIST</dt>
+<dd>Name collision. An object with the same name is already existing in the directory.</dd>
+
+<dt id="io">FR_INVALID_OBJECT</dt>
+<dd>The file/directory object is invalid or a null pointer is given. There are some reasons as follows:
+<ul>
+<li>It has been closed, or the structure has been collapsed.</li>
+<li>It has been invalidated. Open objects on the volume are invalidated by voulme mount process.</li>
+<li>Physical drive is not ready to work due to a media removal.</li>
+</ul>
+</dd>
+
+<dt id="wp">FR_WRITE_PROTECTED</dt>
+<dd>A write mode operation against the write-protected media.</dd>
+
+<dt id="id">FR_INVALID_DRIVE</dt>
+<dd>Invalid drive number is specified in the path name or a null pointer is given as the path name. (Related option: <tt><a href="config.html#volumes">FF_VOLUMES</a></tt>)</dd>
+
+<dt id="ne">FR_NOT_ENABLED</dt>
+<dd>Work area for the logical drive has not been registered by <tt>f_mount</tt> function.</dd>
+
+<dt id="ns">FR_NO_FILESYSTEM</dt>
+<dd>Valid FAT volume could not be found in the drive. One of the following possibilities is suspected.
+<ul>
+<li>The FAT volume on the drive is collapsed.</li>
+<li>Wrong lower layer implementation.</li>
+<li>Wrong <tt>VolToPart[]</tt> settings. (<tt>FF_MULTI_PARTITION = 1</tt>)</li>
+</ul></dd>
+
+<dt id="ma">FR_MKFS_ABORTED</dt>
+<dd>The <tt>f_mkfs</tt> function aborted before start in format due to a reason as follows:
+<ul>
+<li>It is impossible to create the volume with the given conditions.</li>
+<li>The size of the volume is too small. 128 sectors minimum with <tt>FM_SFD</tt> option.</li>
+<li>The partition associated with the logical drive is not exist. (Related option: <tt><a href="config.html#multi_partition">FF_MULTI_PARTITION</a></tt>)</li>
+</ul>
+</dd>
+
+<dt id="tm">FR_TIMEOUT</dt>
+<dd>The function was canceled due to a timeout of <a href="appnote.html#reentrant">thread-safe control</a>. (Related option: <tt><a href="config.html#timeout">FF_TIMEOUT</a></tt>)</dd>
+
+<dt id="lo">FR_LOCKED</dt>
+<dd>The operation to the object was rejected by <a href="appnote.html#dup">file sharing control</a>. (Related option: <tt><a href="config.html#fs_lock">FF_FS_LOCK</a></tt>)</dd>
+
+<dt id="nc">FR_NOT_ENOUGH_CORE</dt>
+<dd>Not enough memory for the operation. There is one of the following reasons:
+<ul>
+<li>Could not allocate a memory for LFN working buffer. (Related option: <tt><a href="config.html#use_lfn">FF_USE_LFN</a></tt>)</li>
+<li>Size of the given buffer is insufficient for the size required.</li>
+</ul>
+</dd>
+
+<dt id="tf">FR_TOO_MANY_OPEN_FILES</dt>
+<dd>Number of open objects has been reached maximum value and no more object can be opened. (Related option: <tt><a href="config.html#fs_lock">FF_FS_LOCK</a></tt>)</dd>
+
+<dt id="ip">FR_INVALID_PARAMETER</dt>
+<dd>The given parameter is invalid or there is an inconsistent for the volume.</dd>
+</dl>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/read.html b/MCUME_pico2/fatfs/documents/doc/read.html
new file mode 100644
index 0000000..9dff623
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/read.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/read.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_read</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_read</h2>
+<p>The f_read function reads data from a file.</p>
+<pre>
+FRESULT f_read (
+  FIL* <span class="arg">fp</span>,     <span class="c">/* [IN] File object */</span>
+  void* <span class="arg">buff</span>,  <span class="c">/* [OUT] Buffer to store read data */</span>
+  UINT <span class="arg">btr</span>,    <span class="c">/* [IN] Number of bytes to read */</span>
+  UINT* <span class="arg">br</span>     <span class="c">/* [OUT] Number of bytes read */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object.</dd>
+<dt>buff</dt>
+<dd>Pointer to the buffer to store the read data.</dd>
+<dt>btr</dt>
+<dd>Number of bytes to read in range of <tt>UINT</tt> type. If the file needs to be read fast, it should be read in large chunk as possible.</dd>
+<dt>br</dt>
+<dd>Pointer to the <tt>UINT</tt> variable that receives number of bytes read. This value is always valid after the function call regardless of the function return code. If the return value is equal to <tt class="arg">btr</tt>, the function return code should be <tt>FR_OK</tt>.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The function starts to read data from the file at the file offset pointed by read/write pointer. The read/write pointer advances as number of bytes read. After the function succeeded, <tt class="arg">*br</tt> should be checked to detect end of the file. In case of <tt class="arg">*br</tt> &lt; <tt class="arg">btr</tt>, it means the read/write pointer hit end of the file during read operation.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<p>Refer to the example in <tt>f_open</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="gets.html">fgets</a>, <a href="write.html">f_write</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/readdir.html b/MCUME_pico2/fatfs/documents/doc/readdir.html
new file mode 100644
index 0000000..52a96b9
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/readdir.html
@@ -0,0 +1,139 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/readdir.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_readdir</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_readdir</h2>
+<p>The f_readdir function reads an item of the directory.</p>
+<pre>
+FRESULT f_readdir (
+  DIR* <span class="arg">dp</span>,      <span class="c">/* [IN] Directory object */</span>
+  FILINFO* <span class="arg">fno</span>  <span class="c">/* [OUT] File information structure */</span>
+);
+</pre>
+<pre>
+FRESULT f_rewinddir (
+  DIR* <span class="arg">dp</span>       <span class="c">/* [IN] Directory object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>dp</dt>
+<dd>Pointer to the open directory object.</dd>
+<dt>fno</dt>
+<dd>Pointer to the <a href="sfileinfo.html">file information structure</a> to store the information about read item. A null pointer rewinds the read index of the directory.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_readdir</tt> function reads a directory item, informations about the object, from the open directory. Items in the directory can be read in sequence by <tt>f_readdir</tt> function calls. When all items in the directory have been read and no item to read, a null string is stored into the <tt>fno-&gt;fname[]</tt> without any error. When a null pointer is given to the <tt class="arg">fno</tt>, the read index of the directory object is rewinded. The <tt>f_rewinddir</tt> function is implemented as a macro.</p>
+<pre>
+#define <em>f_rewinddir</em>(dp) f_readdir((dp), 0)
+</pre>
+<p>When LFN is enabled, a member <tt>altname[]</tt> is defined in the file information structure to store the short file name of the object. If the long file name is not accessible due to a reason listed below, short file name is stored to the <tt>fname[]</tt> and the <tt>altname[]</tt> has a null string.</p>
+<ul>
+<li>The item has no LFN. (Not the case in exFAT volume)</li>
+<li><a href="config.html#max_lfn"><tt>FF_MAX_LFN</tt></a> is insufficient to handle the LFN. (Not the case in <tt>FF_MAX_LFN == 255</tt>)</li>
+<li><a href="config.html#lfn_buf"><tt>FF_LFN_BUF</tt></a> is insufficient to store the LFN.</li>
+<li>The LFN contains some character not defined in current CP. (Not the case in <tt>FF_LFN_UNICODE != 0</tt>)</li>
+</ul>
+<p>There is an issue on read directories in exFAT volume. The exFAT does not support short file name. This means no name can be returned on the condition above. If it is the case, "?" is returned as the file name to indicate that the object is not accessible. To avoid this problem, configure FatFs <tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> != 0</tt> and <tt>FF_MAX_LFN == 255</tt> to support the full feature of LFN specification.</p>
+<p>Dot entries (<tt>"."</tt> and <tt>".."</tt>) in the sub-directory of FAT volume are filtered out and they will never appear in the read items because exFAT lacks dot entries in the sub-directory.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> &lt;= 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Sample Code</h4>
+<pre>
+FRESULT scan_files (
+    char* path        <span class="c">/* Start node to be scanned (***also used as work area***) */</span>
+)
+{
+    FRESULT res;
+    DIR dir;
+    UINT i;
+    static FILINFO fno;
+
+
+    res = f_opendir(&amp;dir, path);                       <span class="c">/* Open the directory */</span>
+    if (res == FR_OK) {
+        for (;;) {
+            res = <em>f_readdir</em>(&amp;dir, &amp;fno);                   <span class="c">/* Read a directory item */</span>
+            if (res != FR_OK || fno.fname[0] == 0) break;  <span class="c">/* Break on error or end of dir */</span>
+            if (fno.fattrib &amp; AM_DIR) {                    <span class="c">/* It is a directory */</span>
+                i = strlen(path);
+                sprintf(&amp;path[i], "/%s", fno.fname);
+                res = scan_files(path);                    <span class="c">/* Enter the directory */</span>
+                if (res != FR_OK) break;
+                path[i] = 0;
+            } else {                                       <span class="c">/* It is a file. */</span>
+                printf("%s/%s\n", path, fno.fname);
+            }
+        }
+        f_closedir(&amp;dir);
+    }
+
+    return res;
+}
+
+
+int main (void)
+{
+    FATFS fs;
+    FRESULT res;
+    char buff[256];
+
+
+    res = f_mount(&amp;fs, "", 1);
+    if (res == FR_OK) {
+        strcpy(buff, "/");
+        res = scan_files(buff);
+    }
+
+    return res;
+}
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="opendir.html">f_opendir</a>, <a href="closedir.html">f_closedir</a>, <a href="stat.html">f_stat</a>, <a href="sfileinfo.html">FILINFO</a>, <a href="sdir.html">DIR</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/rename.html b/MCUME_pico2/fatfs/documents/doc/rename.html
new file mode 100644
index 0000000..326af0d
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/rename.html
@@ -0,0 +1,87 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/rename.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_rename</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_rename</h2>
+<p>The f_rename function renames and/or moves a file or sub-directory.</p>
+<pre>
+FRESULT f_rename (
+  const TCHAR* <span class="arg">old_name</span>, <span class="c">/* [IN] Old object name */</span>
+  const TCHAR* <span class="arg">new_name</span>  <span class="c">/* [IN] New object name */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>old_name</dt>
+<dd>Pointer to a null-terminated string that specifies the existing <a href="filename.html">file or sub-directory</a> to be renamed.</dd>
+<dt>new_name</dt>
+<dd>Pointer to a null-terminated string that specifies the new object name. A drive number may be specified in this string but it is ignored and assumed as the same drive of the <tt class="arg">old_name</tt>. Any object with this path name except <tt class="arg">old_name</tt> must not be exist, or the function fails with <tt>FR_EXIST</tt>.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ok">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#ex">FR_EXIST</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#lo">FR_LOCKED</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>Renames a file or sub-directory and can also move it to other directory in the same volume. The object to be renamed must not be an open object, or <em>the FAT volume can be collapsed</em>. Such the wrong operation is rejected safely when <a href="appnote.html#dup">file lock function</a> is enabled.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Rename an object in the default drive */</span>
+    <em>f_rename</em>("oldname.txt", "newname.txt");
+
+    <span class="c">/* Rename an object in the drive 2 */</span>
+    <em>f_rename</em>("2:oldname.txt", "newname.txt");
+
+    <span class="c">/* Rename an object and move it to another directory in the drive */</span>
+    <em>f_rename</em>("log.txt", "old/log0001.txt");
+</pre>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/sdir.html b/MCUME_pico2/fatfs/documents/doc/sdir.html
new file mode 100644
index 0000000..eb18cc3
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/sdir.html
@@ -0,0 +1,38 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/sdir.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - DIR</title>
+</head>
+
+<body>
+
+<div class="para">
+<h2>DIR</h2>
+<p>The <tt>DIR</tt> structure is used for the work area to read a directory by <tt>f_oepndir</tt>, <tt>f_readdir</tt>, <tt>f_findfirst</tt> and <tt>f_findnext</tt> function. Application program <em>must not</em> modify any member in this structure, or <tt>f_readdir</tt> function will not work properly.</p>
+<pre>
+<span class="k">typedef</span> <span class="k">struct</span> {
+    FFOBJID obj;        <span class="c">/* Object identifier */</span>
+    DWORD   dptr;       <span class="c">/* Current read/write offset */</span>
+    DWORD   clust;      <span class="c">/* Current cluster */</span>
+    LBA_t   sect;       <span class="c">/* Current sector */</span>
+    BYTE*   dir;        <span class="c">/* Pointer to the current SFN entry in the win[] */</span>
+    BYTE*   fn;         <span class="c">/* Pointer to the SFN buffer (in/out) {file[8],ext[3],status[1]} */</span>
+<span class="k">#if</span> FF_USE_LFN
+    DWORD   blk_ofs;    <span class="c">/* Offset of the entry block (0xFFFFFFFF:Invalid) */</span>
+    WCHAR*  lfn;        <span class="c">/* Pointer to the LFN working buffer (in/out) */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> FF_USE_FIND
+    const TCHAR*  pat;  <span class="c">/* Ponter to the matching pattern */</span>
+<span class="k">#endif</span>
+} DIR;
+</pre>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/setcp.html b/MCUME_pico2/fatfs/documents/doc/setcp.html
new file mode 100644
index 0000000..a1d124b
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/setcp.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/getcwd.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_setcp</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_setcp</h2>
+<p>The f_setcp function sets the active code page.</p>
+<pre>
+FRESULT f_setcp (
+  WORD <span class="arg">cp</span>     <span class="c">/* [IN] Code page to be set */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>cp</dt>
+<dd>OEM code page to be used for the path name. Valid values are as follows.<br>
+<table class="lst1">
+<tr><th>Value</th><th>Meaning</th></tr>
+<tr><td>0</td><td>Initial value (any extended character cannot be used)</td></tr>
+<tr><td>437</td><td>U.S.</td></tr>
+<tr><td>720</td><td>Arabic</td></tr>
+<tr><td>737</td><td>Greek</td></tr>
+<tr><td>771</td><td>KBL</td></tr>
+<tr><td>775</td><td>Baltic</td></tr>
+<tr><td>850</td><td>Latin 1</td></tr>
+<tr><td>852</td><td>Latin 2</td></tr>
+<tr><td>855</td><td>Cyrillic</td></tr>
+<tr><td>857</td><td>Turkish</td></tr>
+<tr><td>860</td><td>Portuguese</td></tr>
+<tr><td>861</td><td>Icelandic</td></tr>
+<tr><td>862</td><td>Hebrew</td></tr>
+<tr><td>863</td><td>Canadian French</td></tr>
+<tr><td>864</td><td>Arabic</td></tr>
+<tr><td>865</td><td>Nordic</td></tr>
+<tr><td>866</td><td>Russian</td></tr>
+<tr><td>869</td><td>Greek 2</td></tr>
+<tr><td>932</td><td>Japanese (DBCS)</td></tr>
+<tr><td>936</td><td>Simplified Chinese (DBCS)</td></tr>
+<tr><td>949</td><td>Korean (DBCS)</td></tr>
+<tr><td>950</td><td>Traditional Chinese (DBCS)</td></tr>
+</table>
+</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#ip">FR_INVALID_PARAMETER</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_setcp</tt> function sets the active code page for the path name. Also code conversion of string functions will be affected by the setting of code page when <tt><a href="config.html#lfn_unicode">FF_LFN_UNICODE</a> &gt;= 1</tt> and <tt><a href="config.html#strf_encode">FF_STRF_ENCODE</a> == 0</tt>. Because the initial setting of the code page is 0 and API function with extended character will not work properly, a valid code page needs to be set on the system start-up and it should not be changed on the fly.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#code_page">FF_CODE_PAGE</a> == 0</tt>.</p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/setlabel.html b/MCUME_pico2/fatfs/documents/doc/setlabel.html
new file mode 100644
index 0000000..9eb5e78
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/setlabel.html
@@ -0,0 +1,92 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/setlabel.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_setlabel</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_setlabel</h2>
+<p>The f_setlabel function sets/removes the label of a volume.</p>
+<pre>
+FRESULT f_setlabel (
+  const TCHAR* <span class="arg">label</span>  <span class="c">/* [IN] Volume label to be set */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>label</dt>
+<dd>Pointer to the null-terminated string that specifies the volume label to be set.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>When the string has a drive prefix, the volume label will be set to the volume specified by the drive prefix. Unix style volume ID cannot be used to specify the volume. If drive number is not specified, the volume label will be set to the default drive. If length of the given volume label is zero, the volume label on the volume will be removed. The format of the volume label is as shown below:</p>
+<ul>
+<li>Up to 11 bytes long as conversion of OEM code page at FAT volume.</li>
+<li>Up to 11 characters long at exFAT volume.</li>
+<li>Allowable characters for FAT volume are: characters allowed for SFN excludes dot. Low-case characters are up converted.</li>
+<li>Allowable characters for exFAT volume are: characters allowed for LFN includes dot. Low-case characters are preserved.</li>
+<li>Spaces can be embedded anywhere in the volume label. Trailing spaces are truncated off at FAT volume.</li>
+</ul>
+<p>Remark: The standard system (Windows) has a problem at the volume label with a heading <tt>\xE5</tt> on the FAT volume. To avoid this problem, this function rejects such volume label as invalid name.</p>
+</div>
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_label">FF_USE_LABEL</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    <span class="c">/* Set volume label to the default drive */</span>
+    <em>f_setlabel</em>("DATA DISK");
+
+    <span class="c">/* Set volume label to the drive 2 */</span>
+    <em>f_setlabel</em>("2:DISK 3 OF 4");
+
+    <span class="c">/* Remove volume label of the drive 2 */</span>
+    <em>f_setlabel</em>("2:");
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<tt><a href="getlabel.html">f_getlabel</a></tt>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/sfatfs.html b/MCUME_pico2/fatfs/documents/doc/sfatfs.html
new file mode 100644
index 0000000..6ecd6e5
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/sfatfs.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/sfatfs.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - FATFS</title>
+</head>
+
+<body>
+
+<div class="para">
+<h2>FATFS</h2>
+<p>The <tt>FATFS</tt> structure (filesystem object) holds dynamic work area of individual logical drives. It is given by application program and registerd/unregisterd to the FatFs module with <tt>f_mount</tt> function. Initialization of the structure is done by volume mount process whenever necessary. Application program <em>must not</em> modify any member in this structure, or the FAT volume will be collapsed.</p>
+<pre>
+<span class="k">typedef</span> <span class="k">struct</span> {
+    BYTE    fs_type;      <span class="c">/* FAT type (0, FS_FAT12, FS_FAT16, FS_FAT32 or FS_EXFAT) */</span>
+    BYTE    pdrv;         <span class="c">/* Hosting physical drive of this volume */</span>
+    BYTE    n_fats;       <span class="c">/* Number of FAT copies (1,2) */</span>
+    BYTE    wflag;        <span class="c">/* win[] flag (b0:win[] is dirty) */</span>
+    BYTE    fsi_flag;     <span class="c">/* FSINFO flags (b7:Disabled, b0:Dirty) */</span>
+    WORD    id;           <span class="c">/* Volume mount ID */</span>
+    WORD    n_rootdir;    <span class="c">/* Number of root directory entries (FAT12/16) */</span>
+    WORD    csize;        <span class="c">/* Sectors per cluster */</span>
+<span class="k">#if</span> FF_MAX_SS != FF_MIN_SS
+    WORD    ssize;        <span class="c">/* Sector size (512,1024,2048 or 4096) */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> FF_FS_EXFAT
+    BYTE*   dirbuf;       <span class="c">/* Directory entry block scratchpad buffer */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> FF_FS_REENTRANT
+    FF_SYNC_t sobj;       <span class="c">/* Identifier of sync object */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> !FF_FS_READONLY
+    DWORD   last_clust;   <span class="c">/* FSINFO: Last allocated cluster (0xFFFFFFFF if invalid) */</span>
+    DWORD   free_clust;   <span class="c">/* FSINFO: Number of free clusters (0xFFFFFFFF if invalid) */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> FF_FS_RPATH
+    DWORD   cdir;         <span class="c">/* Cluster number of current directory (0:root) */</span>
+<span class="k">#if</span> FF_FS_EXFAT
+    DWORD   cdc_scl;      <span class="c">/* Containing directory start cluster (invalid when cdir is 0) */</span>
+    DWORD   cdc_size;     <span class="c">/* b31-b8:Size of containing directory, b7-b0: Chain status */</span>
+    DWORD   cdc_ofs;      <span class="c">/* Offset in the containing directory (invalid when cdir is 0) */</span>
+<span class="k">#endif</span>
+<span class="k">#endif</span>
+    DWORD   n_fatent;     <span class="c">/* Number of FAT entries (Number of clusters + 2) */</span>
+    DWORD   fsize;        <span class="c">/* Sectors per FAT */</span>
+    LBA_t   volbase;      <span class="c">/* Volume base LBA */</span>
+    LBA_t   fatbase;      <span class="c">/* FAT base LBA */</span>
+    LBA_t   dirbase;      <span class="c">/* Root directory base (LBA|Cluster) */</span>
+    LBA_t   database;     <span class="c">/* Data base LBA */</span>
+    LBA_t   winsect;      <span class="c">/* Sector LBA appearing in the win[] */</span>
+    BYTE    win[FF_MAX_SS]; <span class="c">/* Disk access window for directory, FAT (and file data at tiny cfg) */</span>
+} FATFS;
+</pre>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/sfile.html b/MCUME_pico2/fatfs/documents/doc/sfile.html
new file mode 100644
index 0000000..9234d32
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/sfile.html
@@ -0,0 +1,43 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/sfile.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - FIL</title>
+</head>
+
+<body>
+
+<div class="para">
+<h2>FIL</h2>
+<p>The <tt>FIL</tt> structure (file object) holds the state of an open file. It is created by <tt>f_open</tt> function and discarded by <tt>f_close</tt> function. Application program <em>must not</em> modify any member in this structure except for <tt>cltbl</tt>, or the FAT volume will be collapsed. Note that a sector buffer is defined in this structure at non-tiny configuration (<tt><a href="config.html#fs_tiny">FF_FS_TINY</a> == 0</tt>), so that the <tt>FIL</tt> structures at that configuration should not be defined as auto variable.</p>
+
+<pre>
+<span class="k">typedef</span> <span class="k">struct</span> {
+    FFOBJID obj;          <span class="c">/* Object identifier */</span>
+    BYTE    flag;         <span class="c">/* File object status flags */</span>
+    BYTE    err;          <span class="c">/* Abort flag (error code) */</span>
+    FSIZE_t fptr;         <span class="c">/* File read/write pointer (Byte offset origin from top of the file) */</span>
+    DWORD   clust;        <span class="c">/* Current cluster of fptr (One cluster behind if fptr is on the cluster boundary. Invalid if fptr == 0.) */</span>
+    LBA_t   sect;         <span class="c">/* Current data sector (Can be invalid if fptr is on the cluster boundary.)*/</span>
+<span class="k">#if</span> !FF_FS_READONLY
+    LBA_t   dir_sect;     <span class="c">/* Sector number containing the directory entry */</span>
+    BYTE*   dir_ptr;      <span class="c">/* Ponter to the directory entry in the window */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> FF_USE_FASTSEEK
+    DWORD*  cltbl;        <span class="c">/* Pointer to the cluster link map table (Nulled on file open. Set by application.) */</span>
+<span class="k">#endif</span>
+<span class="k">#if</span> !FF_FS_TINY
+    BYTE    buf[FF_MAX_SS]; <span class="c">/* File private data transfer buffer (Always valid if fptr is not on the sector boundary but can be invalid if fptr is on the sector boundary.) */</span>
+<span class="k">#endif</span>
+} FIL;
+</pre>
+
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/sfileinfo.html b/MCUME_pico2/fatfs/documents/doc/sfileinfo.html
new file mode 100644
index 0000000..db0f45e
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/sfileinfo.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/sfileinfo.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - FILINFO</title>
+</head>
+
+<body>
+
+<div class="para">
+<h2>FILINFO</h2>
+<p>The <tt>FILINFO</tt> structure holds information about the object retrieved by <tt>f_readdir</tt>, <tt>f_findfirst</tt>, <tt>f_findnext</tt> and <tt>f_stat</tt> function. Be careful in the size of structure when LFN is enabled.</p>
+<pre>
+<span class="k">typedef struct</span> {
+    FSIZE_t fsize;               <span class="c">/* File size */</span>
+    WORD    fdate;               <span class="c">/* Last modified date */</span>
+    WORD    ftime;               <span class="c">/* Last modified time */</span>
+    BYTE    fattrib;             <span class="c">/* Attribute */</span>
+<span class="k">#if</span> FF_USE_LFN
+    TCHAR   altname[FF_SFN_BUF + 1]; <span class="c">/* Alternative object name */</span>
+    TCHAR   fname[FF_LFN_BUF + 1];   <span class="c">/* Primary object name */</span>
+<span class="k">#else</span>
+    TCHAR   fname[12 + 1];       <span class="c">/* Object name */</span>
+<span class="k">#endif</span>
+} FILINFO;
+</pre>
+</div>
+
+<h4>Members</h4>
+<dl>
+<dt>fsize</dt>
+<dd>Size of the file in unit of byte. <tt>FSIZE_t</tt> is an alias of integer type either <tt>DWORD</tt>(32-bit) or <tt>QWORD</tt>(64-bit) depends on the configuration option <tt>FF_FS_EXFAT</tt>. Do not care if the item is a sub-directory.</dd>
+<dt>fdate</dt>
+<dd>The date when the file was modified or the directory was created.<br>
+<dl>
+<dt>bit15:9</dt>
+<dd>Year origin from 1980 (0..127)</dd>
+<dt>bit8:5</dt>
+<dd>Month (1..12)</dd>
+<dt>bit4:0</dt>
+<dd>Day (1..31)</dd>
+</dl>
+</dd>
+<dt>ftime</dt>
+<dd>The time when the file was modified or the directory was created.<br>
+<dl>
+<dt>bit15:11</dt>
+<dd>Hour (0..23)</dd>
+<dt>bit10:5</dt>
+<dd>Minute (0..59)</dd>
+<dt>bit4:0</dt>
+<dd>Second / 2 (0..29)</dd>
+</dl>
+</dd>
+<dt>fattrib</dt>
+<dd>The attribute flags in combination of:<br>
+<table class="lst">
+<tr><th>Flag</th><th>Meaning</th></tr>
+<tr><td>AM_RDO</td><td>Read-only. Write mode open and deleting is rejected.</td></tr>
+<tr><td>AM_HID</td><td>Hidden. Should not be shown in normal directory listing.</td></tr>
+<tr><td>AM_SYS</td><td>System. Used by system and should not be accessed.</td></tr>
+<tr><td>AM_ARC</td><td>Archive. Set on new creation or any modification to the file.</td></tr>
+<tr><td>AM_DIR</td><td>Directory. This is not a file but a sub-directory container.</td></tr>
+</table>
+</dd>
+<dt>fname[]</dt>
+<dd>Null-terminated object name. A null string is stored when no item to read and it indicates this structure is invalid. The size of <tt>fname[]</tt> and <tt>altname[]</tt> each can be configured in LFN configuration.</dd>
+<dt>altname[]</dt>
+<dd>Alternative object name is stored if available. This member is not available in non-LFN configuration.</dd>
+</dl>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/size.html b/MCUME_pico2/fatfs/documents/doc/size.html
new file mode 100644
index 0000000..0be1a76
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/size.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/size.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_size</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_size</h2>
+<p>The f_size function gets the size of a file.</p>
+<pre>
+FSIZE_t f_size (
+  FIL* <span class="arg">fp</span>   <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>Returns the size of the file in unit of byte.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>In this revision, the <tt>f_size</tt> function is implemented as a macro. It does not have any validation and mutual exclusion.</p>
+<pre>
+<span class="k">#define</span> f_size(fp) ((fp)->obj.objsize)
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="lseek.html">f_lseek</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/stat.html b/MCUME_pico2/fatfs/documents/doc/stat.html
new file mode 100644
index 0000000..a4e4fc8
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/stat.html
@@ -0,0 +1,112 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/stat.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_stat</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_stat</h2>
+<p>The f_stat function checks the existence of a file or sub-directory.</p>
+<pre>
+FRESULT f_stat (
+  const TCHAR* <span class="arg">path</span>,  <span class="c">/* [IN] Object name */</span>
+  FILINFO* <span class="arg">fno</span>        <span class="c">/* [OUT] FILINFO structure */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies the <a href="filename.html">object</a> to get its information. The object must not be the root direcotry.</dd>
+<dt>fno</dt>
+<dd>Pointer to the blank <tt>FILINFO</tt> structure to store the information of the object. Set null pointer if this information is not needed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ok">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_stat</tt> function checks the existence of a file or sub-directory in the directory. If it is not exist, the function returns with <tt>FR_NO_FILE</tt>. If it is exist, the function returns with <tt>FR_OK</tt> and the informations about the object, size, timestamp and attribute, is stored to the file information structure. For details of the file information, refer to the <tt>FILINFO</tt> structure and <a href="readdir.html"><tt>f_readdir</tt></a> function.</p>
+<p>Note that the file information comes from the meta data in the directory. If the file has been opend and modified, the file will need to be synched or closed in order to obtain the latest file information.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+    FRESULT fr;
+    FILINFO fno;
+    const char *fname = "file.txt";
+
+
+    printf("Test for \"%s\"...\n", fname);
+
+    fr = <em>f_stat</em>(fname, &amp;fno);
+    switch (fr) {
+
+    case FR_OK:
+        printf("Size: %lu\n", fno.fsize);
+        printf("Timestamp: %u-%02u-%02u, %02u:%02u\n",
+               (fno.fdate &gt;&gt; 9) + 1980, fno.fdate &gt;&gt; 5 &amp; 15, fno.fdate &amp; 31,
+               fno.ftime &gt;&gt; 11, fno.ftime &gt;&gt; 5 &amp; 63);
+        printf("Attributes: %c%c%c%c%c\n",
+               (fno.fattrib &amp; AM_DIR) ? 'D' : '-',
+               (fno.fattrib &amp; AM_RDO) ? 'R' : '-',
+               (fno.fattrib &amp; AM_HID) ? 'H' : '-',
+               (fno.fattrib &amp; AM_SYS) ? 'S' : '-',
+               (fno.fattrib &amp; AM_ARC) ? 'A' : '-');
+        break;
+
+    case FR_NO_FILE:
+        printf("\"%s\" is not exist.\n", fname);
+        break;
+
+    default:
+        printf("An error occured. (%d)\n", fr);
+    }
+</pre>
+</div>
+
+
+<div class="para ref">
+<h4>References</h4>
+<p><tt><a href="opendir.html">f_opendir</a>, <a href="readdir.html">f_readdir</a>, <a href="sfileinfo.html">FILINFO</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/sync.html b/MCUME_pico2/fatfs/documents/doc/sync.html
new file mode 100644
index 0000000..9fb42a0
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/sync.html
@@ -0,0 +1,88 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/sync.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_sync</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_sync</h2>
+<p>The f_sync function flushes the cached information of a writing file.</p>
+<pre>
+FRESULT f_sync (
+  FIL* <span class="arg">fp</span>     <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object to be flushed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_sync</tt> function performs the same process as <tt>f_close</tt> function but the file is left opened and can continue read/write/seek operations to the file. This is suitable for the applications that open files for a long time in write mode, such as data logger. Performing <tt>f_sync</tt> function in certain interval can minimize the risk of data loss due to a sudden blackout, wrong media removal or unrecoverable disk error. For more information, refer to <a href="appnote.html#critical">application note</a>.</p>
+<pre>
+Case 1. Normal write sequence
+
+                                Time --&gt;                                     ↓Normal shutdown
+OwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwC &lt;Power off&gt;
+
+
+Case 2. Without using f_sync()
+
+                                Time --&gt;                             ↓System crush
+O<span class="e">wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww</span>
+ |&lt;--------------- All data written will be lost ------------------&gt;|
+
+
+Case 3. Using f_sync()
+                                Time --&gt;                             ↓System crush
+OwwwwwwwwSwwwwwwwwSwwwwwwwwSwwwwwwwwSwwwwwwwwSwwwwwwwwSwwwwwwwwS<span class="e">wwwww</span>
+                            Data after last f_sync will be lost |&lt;-&gt;| 
+O - f_open()
+C - f_close()
+w - f_write()
+S - f_sync()
+</pre>
+<p>However there is no sense in <tt>f_sync</tt> function immediataly before <tt>f_close</tt> function because it performs <tt>f_sync</tt> function in it. In other words, the differnce between those functions is that the file object is invalidated or not.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="close.html">f_close</a></tt>, <a href="appnote.html#critical">Critical section</a></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/tell.html b/MCUME_pico2/fatfs/documents/doc/tell.html
new file mode 100644
index 0000000..075f033
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/tell.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/tell.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_tell</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_tell</h2>
+<p>The f_tell function gets the current read/write pointer of a file.</p>
+<pre>
+FSIZE_t f_tell (
+  FIL* <span class="arg">fp</span>   <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>Returns current read/write pointer of the file.</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>In this revision, the <tt>f_tell</tt> function is implemented as a macro. It does not have any validation and mutual exclusion.</p>
+<pre>
+<span class="k">#define</span> f_tell(fp) ((fp)->fptr)
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Always available.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="lseek.html">f_lseek</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/truncate.html b/MCUME_pico2/fatfs/documents/doc/truncate.html
new file mode 100644
index 0000000..0ac012f
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/truncate.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/truncate.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_truncate</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_truncate</h2>
+<p>The f_truncate function truncates the file size.</p>
+<pre>
+FRESULT f_truncate (
+  FIL* <span class="arg">fp</span>     <span class="c">/* [IN] File object */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object to be truncated.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_truncate</tt> function truncates the file size to the current file read/write pointer. This function has no effect if the file read/write pointer is already pointing end of the file.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="lseek.html">f_lseek</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/unlink.html b/MCUME_pico2/fatfs/documents/doc/unlink.html
new file mode 100644
index 0000000..7809648
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/unlink.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/unlink.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_unlink</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_unlink</h2>
+<p>The f_unlink function removes a file or sub-directory from the volume.</p>
+<pre>
+FRESULT f_unlink (
+  const TCHAR* <span class="arg">path</span>  <span class="c">/* [IN] Object name */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameter</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to a null-terminated string that specifies the <a href="filename.html">file or sub-directory</a> to be removed.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ok">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#lo">FR_LOCKED</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>
+If condition of the object to be removed is applicable to the following terms, the function will be rejected.<ul>
+<li>The file/sub-directory must not have read-only attribute (<tt>AM_RDO</tt>), or the function will be rejected with <tt>FR_DENIED</tt>.</li>
+<li>The sub-directory must be empty and must not be current directory, or the function will be rejected with <tt>FR_DENIED</tt>.</li>
+<li>The file/sub-directory must not be opened, or the <em>FAT volume can be collapsed</em>. It will be rejected safely when <a href="appnote.html#dup">file lock function</a> is enabled.</li>
+</ul>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#fs_minimize">FF_FS_MINIMIZE</a> == 0</tt>.</p>
+</div>
+
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/utime.html b/MCUME_pico2/fatfs/documents/doc/utime.html
new file mode 100644
index 0000000..40e39eb
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/utime.html
@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/utime.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_utime</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_utime</h2>
+<p>The f_utime function changes the timestamp of a file or sub-directory.</p>
+<pre>
+FRESULT f_utime (
+  const TCHAR* <span class="arg">path</span>,  <span class="c">/* [IN] Object name */</span>
+  const FILINFO* <span class="arg">fno</span>  <span class="c">/* [IN] Time and data to be set */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>path</dt>
+<dd>Pointer to the null-terminated string that specifies an <a href="filename.html">object</a> to be changed.</dd>
+<dt>fno</dt>
+<dd>Pointer to the file information structure that has a timestamp to be set in member fdate and ftime. Do not care any other members.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#nr">FR_NOT_READY</a>,
+<a href="rc.html#ok">FR_NO_FILE</a>,
+<a href="rc.html#np">FR_NO_PATH</a>,
+<a href="rc.html#in">FR_INVALID_NAME</a>,
+<a href="rc.html#wp">FR_WRITE_PROTECTED</a>,
+<a href="rc.html#id">FR_INVALID_DRIVE</a>,
+<a href="rc.html#ne">FR_NOT_ENABLED</a>,
+<a href="rc.html#ns">FR_NO_FILESYSTEM</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>,
+<a href="rc.html#nc">FR_NOT_ENOUGH_CORE</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The <tt>f_utime</tt> function changes the timestamp of a file or sub-directory</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<pre>
+FRESULT set_timestamp (
+    char *obj,     <span class="c">/* Pointer to the file name */</span>
+    int year,
+    int month,
+    int mday,
+    int hour,
+    int min,
+    int sec
+)
+{
+    FILINFO fno;
+
+    fno.fdate = (WORD)(((year - 1980) * 512U) | month * 32U | mday);
+    fno.ftime = (WORD)(hour * 2048U | min * 32U | sec / 2U);
+
+    return <em>f_utime</em>(obj, &amp;fno);
+}
+</pre>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt> and <tt><a href="config.html#use_chmod">FF_USE_CHMOD</a> == 1</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="stat.html">f_stat</a>, <a href="sfileinfo.html">FILINFO</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/doc/write.html b/MCUME_pico2/fatfs/documents/doc/write.html
new file mode 100644
index 0000000..3d16674
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/doc/write.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<link rel="up" title="FatFs" href="../00index_e.html">
+<link rel="alternate" hreflang="ja" title="Japanese" href="../ja/write.html">
+<link rel="stylesheet" href="../css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - f_write</title>
+</head>
+
+<body>
+
+<div class="para func">
+<h2>f_write</h2>
+<p>The f_write writes data to a file.</p>
+<pre>
+FRESULT f_write (
+  FIL* <span class="arg">fp</span>,          <span class="c">/* [IN] Pointer to the file object structure */</span>
+  const void* <span class="arg">buff</span>, <span class="c">/* [IN] Pointer to the data to be written */</span>
+  UINT <span class="arg">btw</span>,         <span class="c">/* [IN] Number of bytes to write */</span>
+  UINT* <span class="arg">bw</span>          <span class="c">/* [OUT] Pointer to the variable to return number of bytes written */</span>
+);
+</pre>
+</div>
+
+<div class="para arg">
+<h4>Parameters</h4>
+<dl class="par">
+<dt>fp</dt>
+<dd>Pointer to the open file object structure.</dd>
+<dt>buff</dt>
+<dd>Pointer to the data to be written.</dd>
+<dt>btw</dt>
+<dd>Specifies number of bytes to write in range of <tt>UINT</tt> type. If the data needs to be written fast, it should be written in large chunk as possible.</dd>
+<dt>bw</dt>
+<dd>Pointer to the <tt>UINT</tt> variable that receives the number of bytes written. This value is always valid after the function call regardless of the function return code. If the return value is equal to <tt class="arg">btw</tt>, the function return code should be <tt>FR_OK</tt>.</dd>
+</dl>
+</div>
+
+
+<div class="para ret">
+<h4>Return Values</h4>
+<p>
+<a href="rc.html#ok">FR_OK</a>,
+<a href="rc.html#de">FR_DISK_ERR</a>,
+<a href="rc.html#ie">FR_INT_ERR</a>,
+<a href="rc.html#dn">FR_DENIED</a>,
+<a href="rc.html#io">FR_INVALID_OBJECT</a>,
+<a href="rc.html#tm">FR_TIMEOUT</a>
+</p>
+</div>
+
+
+<div class="para desc">
+<h4>Description</h4>
+<p>The function starts to write data to the file at the file offset pointed by read/write pointer. The read/write pointer advances as number of bytes written. After the function succeeded, <tt class="arg">*bw</tt> should be checked to detect the disk full. In case of <tt class="arg">*bw</tt> &lt; <tt class="arg">btw</tt>, it means the volume got full during the write operation. The function can take a time when the volume is full or close to full.</p>
+</div>
+
+
+<div class="para comp">
+<h4>QuickInfo</h4>
+<p>Available when <tt><a href="config.html#fs_readonly">FF_FS_READONLY</a> == 0</tt>.</p>
+</div>
+
+
+<div class="para use">
+<h4>Example</h4>
+<p>Refer to the example in <tt>f_open</tt>.</p>
+</div>
+
+
+<div class="para ref">
+<h4>See Also</h4>
+<p><tt><a href="open.html">f_open</a>, <a href="read.html">f_read</a>, <a href="putc.html">fputc</a>, <a href="puts.html">fputs</a>, <a href="printf.html">fprintf</a>, <a href="close.html">f_close</a>, <a href="sfile.html">FIL</a></tt></p>
+</div>
+
+<p class="foot"><a href="../00index_e.html">Return</a></p>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/documents/res/app1.c b/MCUME_pico2/fatfs/documents/res/app1.c
new file mode 100644
index 0000000..85275e1
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app1.c
@@ -0,0 +1,44 @@
+/*------------------------------------------------------------/
+/ Open or create a file in append mode
+/ (This function was sperseded by FA_OPEN_APPEND flag at FatFs R0.12a)
+/------------------------------------------------------------*/
+
+FRESULT open_append (
+    FIL* fp,            /* [OUT] File object to create */
+    const char* path    /* [IN]  File name to be opened */
+)
+{
+    FRESULT fr;
+
+    /* Opens an existing file. If not exist, creates a new file. */
+    fr = f_open(fp, path, FA_WRITE | FA_OPEN_ALWAYS);
+    if (fr == FR_OK) {
+        /* Seek to end of the file to append data */
+        fr = f_lseek(fp, f_size(fp));
+        if (fr != FR_OK)
+            f_close(fp);
+    }
+    return fr;
+}
+
+
+int main (void)
+{
+    FRESULT fr;
+    FATFS fs;
+    FIL fil;
+
+    /* Open or create a log file and ready to append */
+    f_mount(&fs, "", 0);
+    fr = open_append(&fil, "logfile.txt");
+    if (fr != FR_OK) return 1;
+
+    /* Append a line */
+    f_printf(&fil, "%02u/%02u/%u, %2u:%02u\n", Mday, Mon, Year, Hour, Min);
+
+    /* Close the file */
+    f_close(&fil);
+
+    return 0;
+}
+
diff --git a/MCUME_pico2/fatfs/documents/res/app2.c b/MCUME_pico2/fatfs/documents/res/app2.c
new file mode 100644
index 0000000..415c4bc
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app2.c
@@ -0,0 +1,81 @@
+/*------------------------------------------------------------/
+/ Delete a sub-directory even if it contains any file
+/-------------------------------------------------------------/
+/ The delete_node() function is for R0.12+.
+/ It works regardless of FF_FS_RPATH.
+*/
+
+
+FRESULT delete_node (
+    TCHAR* path,    /* Path name buffer with the sub-directory to delete */
+    UINT sz_buff,   /* Size of path name buffer (items) */
+    FILINFO* fno    /* Name read buffer */
+)
+{
+    UINT i, j;
+    FRESULT fr;
+    DIR dir;
+
+
+    fr = f_opendir(&dir, path); /* Open the sub-directory to make it empty */
+    if (fr != FR_OK) return fr;
+
+    for (i = 0; path[i]; i++) ; /* Get current path length */
+    path[i++] = _T('/');
+
+    for (;;) {
+        fr = f_readdir(&dir, fno);  /* Get a directory item */
+        if (fr != FR_OK || !fno->fname[0]) break;   /* End of directory? */
+        j = 0;
+        do {    /* Make a path name */
+            if (i + j >= sz_buff) { /* Buffer over flow? */
+                fr = 100; break;    /* Fails with 100 when buffer overflow */
+            }
+            path[i + j] = fno->fname[j];
+        } while (fno->fname[j++]);
+        if (fno->fattrib & AM_DIR) {    /* Item is a sub-directory */
+            fr = delete_node(path, sz_buff, fno);
+        } else {                        /* Item is a file */
+            fr = f_unlink(path);
+        }
+        if (fr != FR_OK) break;
+    }
+
+    path[--i] = 0;  /* Restore the path name */
+    f_closedir(&dir);
+
+    if (fr == FR_OK) fr = f_unlink(path);  /* Delete the empty sub-directory */
+    return fr;
+}
+
+
+
+
+int main (void) /* How to use */
+{
+    FRESULT fr;
+    FATFS fs;
+    TCHAR buff[256];
+    FILINFO fno;
+
+
+    f_mount(&fs, _T("5:"), 0);
+
+    /* Directory to be deleted */
+    _tcscpy(buff, _T("5:dir"));
+
+    /* Delete the directory */
+    fr = delete_node(buff, sizeof buff / sizeof buff[0], &fno);
+
+    /* Check the result */
+    if (fr) {
+        _tprintf(_T("Failed to delete the directory. (%u)\n"), fr);
+        return fr;
+    } else {
+        _tprintf(_T("The directory and the contents have successfully been deleted.\n"), buff);
+        return 0;
+    }
+}
+
+
+
diff --git a/MCUME_pico2/fatfs/documents/res/app3.c b/MCUME_pico2/fatfs/documents/res/app3.c
new file mode 100644
index 0000000..523058f
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app3.c
@@ -0,0 +1,109 @@
+/*----------------------------------------------------------------------/
+/ Allocate a contiguous area to the file
+/-----------------------------------------------------------------------/
+/ This function checks if the file is contiguous with desired size.
+/ If not, a block of contiguous sectors is allocated to the file.
+/ If the file has been opened without FA_WRITE flag, it only checks if
+/ the file is contiguous and returns the resulut.
+/-----------------------------------------------------------------------/
+/ This function can work with FatFs R0.09 - R0.11a.
+/ It is incompatible with R0.12+. Use f_expand function instead.
+/----------------------------------------------------------------------*/
+
+/* Declarations of FatFs internal functions accessible from applications.
+/  This is intended to be used for disk checking/fixing or dirty hacks :-) */
+DWORD clust2sect (FATFS* fs, DWORD clst);
+DWORD get_fat (FATFS* fs, DWORD clst);
+FRESULT put_fat (FATFS* fs, DWORD clst, DWORD val);
+
+
+DWORD allocate_contiguous_clusters (    /* Returns the first sector in LBA (0:error or not contiguous) */
+    FIL* fp,    /* Pointer to the open file object */
+    DWORD len   /* Number of bytes to allocate */
+)
+{
+    DWORD csz, tcl, ncl, ccl, cl;
+
+
+    if (f_lseek(fp, 0) || !len)     /* Check if the given parameters are valid */
+        return 0;
+    csz = 512UL * fp->fs->csize;    /* Cluster size in unit of byte (assuming 512 bytes/sector) */
+    tcl = (len + csz - 1) / csz;    /* Total number of clusters required */
+    len = tcl * csz;                /* Round-up file size to the cluster boundary */
+
+    /* Check if the existing cluster chain is contiguous */
+    if (len == fp->fsize) {
+        ncl = 0; ccl = fp->sclust;
+        do {
+            cl = get_fat(fp->fs, ccl);  /* Get the cluster status */
+            if (cl + 1 < 3) return 0;   /* Hard error? */
+            if (cl != ccl + 1 && cl < fp->fs->n_fatent) break;  /* Not contiguous? */
+            ccl = cl;
+        } while (++ncl < tcl);
+        if (ncl == tcl)             /* Is the file contiguous? */
+            return clust2sect(fp->fs, fp->sclust);  /* File is contiguous. Return the start sector */
+    }
+
+    /* File is not contiguous */
+#if _FS_READONLY
+    return 0;								/* Exit if in read-only cfg. */
+#else
+    if (!(fp->flag & FA_WRITE)) return 0;   /* Exit if the file object is for read-only */
+
+    if (f_truncate(fp)) return 0;           /* Remove the non-contiguous chain */
+
+    /* Find a free contiguous area */
+    ccl = cl = 2; ncl = 0;
+    do {
+        if (cl >= fp->fs->n_fatent) return 0;   /* No contiguous area is found. */
+        if (get_fat(fp->fs, cl)) {  /* Encounterd a cluster in use */
+            do {    /* Skip the block of used clusters */
+                cl++;
+                if (cl >= fp->fs->n_fatent) return 0;   /* No contiguous area is found. */
+            } while (get_fat(fp->fs, cl));
+            ccl = cl; ncl = 0;
+        }
+        cl++; ncl++;
+    } while (ncl < tcl);
+
+    /* Create a contiguous cluster chain */
+    fp->fs->last_clust = ccl - 1;
+    if (f_lseek(fp, len)) return 0;
+
+    return clust2sect(fp->fs, fp->sclust);  /* Return file start sector */
+#endif
+}
+
+
+int main (void)
+{
+    FRESULT fr;
+    DRESULT dr;
+    FATFS fs;
+    FIL fil;
+    DWORD org;
+
+
+    /* Open or create a file to write */
+    f_mount(&fs, "", 0);
+    fr = f_open(&fil, "fastrec.log", FA_READ | FA_WRITE | FA_OPEN_ALWAYS);
+    if (fr) return 1;
+
+    /* Check if the file is 256MB in size and occupies a contiguous area.
+    /  If not, a contiguous area will be re-allocated to the file. */
+    org = allocate_contiguous_clusters(&fil, 0x10000000);
+    if (!org) {
+        printf("Function failed due to any error or insufficient contiguous area.\n");
+        f_close(&fil);
+        return 1;
+    }
+
+    /* Now you can read/write the file without filesystem layer. */
+    ...
+    dr = disk_write(fil.fs->drv, Buff, org, 1024);   /* Write 512KiB from top of the file */
+    ...
+
+    f_close(&fil);
+    return 0;
+}
+
diff --git a/MCUME_pico2/fatfs/documents/res/app4.c b/MCUME_pico2/fatfs/documents/res/app4.c
new file mode 100644
index 0000000..c46d1a0
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app4.c
@@ -0,0 +1,315 @@
+/*----------------------------------------------------------------------/
+/ Low level disk I/O module function checker                            /
+/-----------------------------------------------------------------------/
+/ WARNING: The data on the target drive will be lost!
+*/
+
+#include <stdio.h>
+#include <string.h>
+#include "ff.h"         /* Declarations of sector size */
+#include "diskio.h"     /* Declarations of disk functions */
+
+
+
+static DWORD pn (       /* Pseudo random number generator */
+    DWORD pns   /* 0:Initialize, !0:Read */
+)
+{
+    static DWORD lfsr;
+    UINT n;
+
+
+    if (pns) {
+        lfsr = pns;
+        for (n = 0; n < 32; n++) pn(0);
+    }
+    if (lfsr & 1) {
+        lfsr >>= 1;
+        lfsr ^= 0x80200003;
+    } else {
+        lfsr >>= 1;
+    }
+    return lfsr;
+}
+
+
+int test_diskio (
+    BYTE pdrv,      /* Physical drive number to be checked (all data on the drive will be lost) */
+    UINT ncyc,      /* Number of test cycles */
+    DWORD* buff,    /* Pointer to the working buffer */
+    UINT sz_buff    /* Size of the working buffer in unit of byte */
+)
+{
+    UINT n, cc, ns;
+    DWORD sz_drv, lba, lba2, sz_eblk, pns = 1;
+    WORD sz_sect;
+    BYTE *pbuff = (BYTE*)buff;
+    DSTATUS ds;
+    DRESULT dr;
+
+
+    printf("test_diskio(%u, %u, 0x%08X, 0x%08X)\n", pdrv, ncyc, (UINT)buff, sz_buff);
+
+    if (sz_buff < FF_MAX_SS + 8) {
+        printf("Insufficient work area to run the program.\n");
+        return 1;
+    }
+
+    for (cc = 1; cc <= ncyc; cc++) {
+        printf("**** Test cycle %u of %u start ****\n", cc, ncyc);
+
+        printf(" disk_initalize(%u)", pdrv);
+        ds = disk_initialize(pdrv);
+        if (ds & STA_NOINIT) {
+            printf(" - failed.\n");
+            return 2;
+        } else {
+            printf(" - ok.\n");
+        }
+
+        printf("**** Get drive size ****\n");
+        printf(" disk_ioctl(%u, GET_SECTOR_COUNT, 0x%08X)", pdrv, (UINT)&sz_drv);
+        sz_drv = 0;
+        dr = disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_drv);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 3;
+        }
+        if (sz_drv < 128) {
+            printf("Failed: Insufficient drive size to test.\n");
+            return 4;
+        }
+        printf(" Number of sectors on the drive %u is %lu.\n", pdrv, sz_drv);
+
+#if FF_MAX_SS != FF_MIN_SS
+        printf("**** Get sector size ****\n");
+        printf(" disk_ioctl(%u, GET_SECTOR_SIZE, 0x%X)", pdrv, (UINT)&sz_sect);
+        sz_sect = 0;
+        dr = disk_ioctl(pdrv, GET_SECTOR_SIZE, &sz_sect);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 5;
+        }
+        printf(" Size of sector is %u bytes.\n", sz_sect);
+#else
+        sz_sect = FF_MAX_SS;
+#endif
+
+        printf("**** Get block size ****\n");
+        printf(" disk_ioctl(%u, GET_BLOCK_SIZE, 0x%X)", pdrv, (UINT)&sz_eblk);
+        sz_eblk = 0;
+        dr = disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_eblk);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+        }
+        if (dr == RES_OK || sz_eblk >= 2) {
+            printf(" Size of the erase block is %lu sectors.\n", sz_eblk);
+        } else {
+            printf(" Size of the erase block is unknown.\n");
+        }
+
+        /* Single sector write test */
+        printf("**** Single sector write test ****\n");
+        lba = 0;
+        for (n = 0, pn(pns); n < sz_sect; n++) pbuff[n] = (BYTE)pn(0);
+        printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba);
+        dr = disk_write(pdrv, pbuff, lba, 1);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 6;
+        }
+        printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv);
+        dr = disk_ioctl(pdrv, CTRL_SYNC, 0);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 7;
+        }
+        memset(pbuff, 0, sz_sect);
+        printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba);
+        dr = disk_read(pdrv, pbuff, lba, 1);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 8;
+        }
+        for (n = 0, pn(pns); n < sz_sect && pbuff[n] == (BYTE)pn(0); n++) ;
+        if (n == sz_sect) {
+            printf(" Read data matched.\n");
+        } else {
+            printf(" Read data differs from the data written.\n");
+            return 10;
+        }
+        pns++;
+
+        printf("**** Multiple sector write test ****\n");
+        lba = 5; ns = sz_buff / sz_sect;
+        if (ns > 4) ns = 4;
+        if (ns > 1) {
+            for (n = 0, pn(pns); n < (UINT)(sz_sect * ns); n++) pbuff[n] = (BYTE)pn(0);
+            printf(" disk_write(%u, 0x%X, %lu, %u)", pdrv, (UINT)pbuff, lba, ns);
+            dr = disk_write(pdrv, pbuff, lba, ns);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 11;
+            }
+            printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv);
+            dr = disk_ioctl(pdrv, CTRL_SYNC, 0);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 12;
+            }
+            memset(pbuff, 0, sz_sect * ns);
+            printf(" disk_read(%u, 0x%X, %lu, %u)", pdrv, (UINT)pbuff, lba, ns);
+            dr = disk_read(pdrv, pbuff, lba, ns);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 13;
+            }
+            for (n = 0, pn(pns); n < (UINT)(sz_sect * ns) && pbuff[n] == (BYTE)pn(0); n++) ;
+            if (n == (UINT)(sz_sect * ns)) {
+                printf(" Read data matched.\n");
+            } else {
+                printf(" Read data differs from the data written.\n");
+                return 14;
+            }
+        } else {
+            printf(" Test skipped.\n");
+        }
+        pns++;
+
+        printf("**** Single sector write test (unaligned buffer address) ****\n");
+        lba = 5;
+        for (n = 0, pn(pns); n < sz_sect; n++) pbuff[n+3] = (BYTE)pn(0);
+        printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+3), lba);
+        dr = disk_write(pdrv, pbuff+3, lba, 1);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 15;
+        }
+        printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv);
+        dr = disk_ioctl(pdrv, CTRL_SYNC, 0);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 16;
+        }
+        memset(pbuff+5, 0, sz_sect);
+        printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+5), lba);
+        dr = disk_read(pdrv, pbuff+5, lba, 1);
+        if (dr == RES_OK) {
+            printf(" - ok.\n");
+        } else {
+            printf(" - failed.\n");
+            return 17;
+        }
+        for (n = 0, pn(pns); n < sz_sect && pbuff[n+5] == (BYTE)pn(0); n++) ;
+        if (n == sz_sect) {
+            printf(" Read data matched.\n");
+        } else {
+            printf(" Read data differs from the data written.\n");
+            return 18;
+        }
+        pns++;
+
+        printf("**** 4GB barrier test ****\n");
+        if (sz_drv >= 128 + 0x80000000 / (sz_sect / 2)) {
+            lba = 6; lba2 = lba + 0x80000000 / (sz_sect / 2);
+            for (n = 0, pn(pns); n < (UINT)(sz_sect * 2); n++) pbuff[n] = (BYTE)pn(0);
+            printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba);
+            dr = disk_write(pdrv, pbuff, lba, 1);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 19;
+            }
+            printf(" disk_write(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+sz_sect), lba2);
+            dr = disk_write(pdrv, pbuff+sz_sect, lba2, 1);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 20;
+            }
+            printf(" disk_ioctl(%u, CTRL_SYNC, NULL)", pdrv);
+            dr = disk_ioctl(pdrv, CTRL_SYNC, 0);
+            if (dr == RES_OK) {
+            printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 21;
+            }
+            memset(pbuff, 0, sz_sect * 2);
+            printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)pbuff, lba);
+            dr = disk_read(pdrv, pbuff, lba, 1);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 22;
+            }
+            printf(" disk_read(%u, 0x%X, %lu, 1)", pdrv, (UINT)(pbuff+sz_sect), lba2);
+            dr = disk_read(pdrv, pbuff+sz_sect, lba2, 1);
+            if (dr == RES_OK) {
+                printf(" - ok.\n");
+            } else {
+                printf(" - failed.\n");
+                return 23;
+            }
+            for (n = 0, pn(pns); pbuff[n] == (BYTE)pn(0) && n < (UINT)(sz_sect * 2); n++) ;
+            if (n == (UINT)(sz_sect * 2)) {
+                printf(" Read data matched.\n");
+            } else {
+                printf(" Read data differs from the data written.\n");
+                return 24;
+            }
+        } else {
+            printf(" Test skipped.\n");
+        }
+        pns++;
+
+        printf("**** Test cycle %u of %u completed ****\n\n", cc, ncyc);
+    }
+
+    return 0;
+}
+
+
+
+int main (int argc, char* argv[])
+{
+    int rc;
+    DWORD buff[FF_MAX_SS];  /* Working buffer (4 sector in size) */
+
+    /* Check function/compatibility of the physical drive #0 */
+    rc = test_diskio(0, 3, buff, sizeof buff);
+
+    if (rc) {
+        printf("Sorry the function/compatibility test failed. (rc=%d)\nFatFs will not work with this disk driver.\n", rc);
+    } else {
+        printf("Congratulations! The disk driver works well.\n");
+    }
+
+    return rc;
+}
+
diff --git a/MCUME_pico2/fatfs/documents/res/app5.c b/MCUME_pico2/fatfs/documents/res/app5.c
new file mode 100644
index 0000000..2739019
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app5.c
@@ -0,0 +1,38 @@
+/*----------------------------------------------------------------------/
+/ Test if the file is contiguous                                        /
+/----------------------------------------------------------------------*/
+
+FRESULT test_contiguous_file (
+    FIL* fp,    /* [IN]  Open file object to be checked */
+    int* cont   /* [OUT] 1:Contiguous, 0:Fragmented or zero-length */
+)
+{
+    DWORD clst, clsz, step;
+    FSIZE_t fsz;
+    FRESULT fr;
+
+
+    *cont = 0;
+    fr = f_rewind(fp);              /* Validates and prepares the file */
+    if (fr != FR_OK) return fr;
+
+#if FF_MAX_SS == FF_MIN_SS
+    clsz = (DWORD)fp->obj.fs->csize * FF_MAX_SS;    /* Cluster size */
+#else
+    clsz = (DWORD)fp->obj.fs->csize * fp->obj.fs->ssize;
+#endif
+    fsz = f_size(fp);
+    if (fsz > 0) {
+        clst = fp->obj.sclust - 1;  /* A cluster leading the first cluster for first test */
+        while (fsz) {
+            step = (fsz >= clsz) ? clsz : (DWORD)fsz;
+            fr = f_lseek(fp, f_tell(fp) + step);    /* Advances file pointer a cluster */
+            if (fr != FR_OK) return fr;
+            if (clst + 1 != fp->clust) break;       /* Is not the cluster next to previous one? */
+            clst = fp->clust; fsz -= step;          /* Get current cluster for next test */
+        }
+        if (fsz == 0) *cont = 1;    /* All done without fail? */
+    }
+
+    return FR_OK;
+}
diff --git a/MCUME_pico2/fatfs/documents/res/app6.c b/MCUME_pico2/fatfs/documents/res/app6.c
new file mode 100644
index 0000000..4a3565e
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/res/app6.c
@@ -0,0 +1,61 @@
+/*---------------------------------------------------------------------*/
+/* Raw Read/Write Throughput Checker                                   */
+/*---------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <systimer.h>
+#include "diskio.h"
+#include "ff.h"
+
+
+int test_raw_speed (
+    BYTE pdrv,      /* Physical drive number */
+    DWORD lba,      /* Start LBA for read/write test */
+    DWORD len,      /* Number of bytes to read/write (must be multiple of sz_buff) */
+    void* buff,     /* Read/write buffer */
+    UINT sz_buff    /* Size of read/write buffer (must be multiple of FF_MAX_SS) */
+)
+{
+    WORD ss;
+    DWORD ofs, tmr;
+
+
+#if FF_MIN_SS != FF_MAX_SS
+    if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) {
+        printf("\ndisk_ioctl() failed.\n");
+        return 0;
+    }
+#else
+    ss = FF_MAX_SS;
+#endif
+
+    printf("Starting raw write test at sector %lu in %u bytes of data chunks...", lba, sz_buff);
+    tmr = systimer();
+    for (ofs = 0; ofs < len / ss; ofs += sz_buff / ss) {
+        if (disk_write(pdrv, buff, lba + ofs, sz_buff / ss) != RES_OK) {
+            printf("\ndisk_write() failed.\n");
+            return 0;
+        }
+    }
+    if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) {
+        printf("\ndisk_ioctl() failed.\n");
+        return 0;
+    }
+    tmr = systimer() - tmr;
+    printf("\n%lu bytes written and it took %lu timer ticks.\n", len, tmr);
+
+    printf("Starting raw read test at sector %lu in %u bytes of data chunks...", lba, sz_buff);
+    tmr = systimer();
+    for (ofs = 0; ofs < len / ss; ofs += sz_buff / ss) {
+        if (disk_read(pdrv, buff, lba + ofs, sz_buff / ss) != RES_OK) {
+            printf("\ndisk_read() failed.\n");
+            return 0;
+        }
+    }
+    tmr = systimer() - tmr;
+    printf("\n%lu bytes read and it took %lu timer ticks.\n", len, tmr);
+
+    printf("Test completed.\n");
+    return 1;
+}
+
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diff --git a/MCUME_pico2/fatfs/documents/updates.html b/MCUME_pico2/fatfs/documents/updates.html
new file mode 100644
index 0000000..29d881f
--- /dev/null
+++ b/MCUME_pico2/fatfs/documents/updates.html
@@ -0,0 +1,479 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<meta http-equiv="cache-control" content="no-cache">
+<link rel="start" title="Site Top" href="../../">
+<link rel="stylesheet" href="css_e.css" type="text/css" media="screen" title="ELM Default">
+<title>FatFs - Known Problems</title>
+</head>
+<body style="max-width: none;">
+<h2>Updates and Migration Notes</h2>
+<table class="lst4">
+<tr><th>Revision</th><th>Updates</th><th>Migration Notes</th></tr>
+<tr>
+<td>R0.15<br>Nov 6, 2022</td>
+<td>
+Changed user provided synchronization functions in order to completely eliminate the platform dependency from FatFs code.<br>
+Fixed a potential error in <tt>f_mount</tt> when <tt>FF_FS_REENTRANT</tt>.<br>
+Fixed file lock control <tt>FF_FS_LOCK</tt> is not mutal excluded when <tt>FF_FS_REENTRANT && FF_VOLUMES &gt; 1</tt> is true.<br>
+Fixed <tt>f_mkfs</tt> creates broken exFAT volume when the size of volume is <tt>&gt;= 2^32</tt> sectors.<br>
+Fixed string functions cannot write the unicode characters not in BMP when <tt>FF_LFN_UNICODE == 2</tt> (UTF-8).<br>
+Fixed a compatibility issue in identification of GPT header.<br>
+</td>
+<td>
+User provided synchronization functions, <tt>ff_cre_syncobj</tt>, <tt>ff_del_syncobj</tt>, <tt>ff_req_grant</tt> and <tt>ff_rel_grant</tt>, needed when <tt>FF_FS_REENTRANT</tt> are replaced by <tt>ff_mutex_create</tt>, <tt>ff_mutex_delete</tt>, <tt>ff_mutex_take</tt> and <tt>ff_mutex_give</tt> respectively. For examples, see <tt>ffsystem.c</tt>.<br>
+<tt>FF_SYNC_t</tt> is removed from the configuration options.<br>
+</td>
+</tr>
+<tr>
+<td>R0.14b<br>Apr 17, 2021</td>
+<td>
+Made FatFs uses standard library <tt>string.h</tt> for copy, compare and search instead of built-in string functions.<br>
+Added support for long long integer and floating point to <tt>f_printf</tt>. (<tt>FF_STRF_LLI</tt> and <tt>FF_STRF_FP</tt>)<br>
+Made path name parser ignores the terminating separator to allow <tt>"dir/"</tt>.<br>
+Improved the compatibility in Unix style path name feature.<br>
+Fixed the file gets dead-locked when <tt>f_open</tt> failed with certain conditions. (appeared at R0.12a)<br>
+Fixed <tt>f_mkfs</tt> can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12)<br>
+Fixed code page 855 cannot be set by <tt>f_setcp</tt>. (appeared at R0.13)<br>
+Fixed some compiler warnings.<br>
+</td>
+<td>
+From this revision, FatFs depends on <tt>string.h</tt>.<br>
+</td>
+</tr>
+<tr>
+<td>R0.14a<br>Dec 05, 2020</td>
+<td>
+Limited number of recursive calls in <tt>f_findnext</tt> to prevent stack overflow.<br>
+Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted.<br>
+Fixed some compiler warnings.<br>
+</td>
+<td>
+Number of wildcards in the matching pattern in <tt>f_findfirst</tt> is limited to 4.<br>
+</td>
+</tr>
+<tr>
+<td>R0.14<br>Oct 14, 2019</td>
+<td>
+Added support for 64-bit LBA and GUID partition table (<tt>FF_LBA64</tt>)<br>
+Changed some API functions, <tt>f_mkfs</tt> and <tt>f_fdisk</tt>.<br>
+Fixed <tt>f_open</tt> cannot find the file with file name in length of <tt>FF_MAX_LFN</tt> characters.<br>
+Fixed <tt>f_readdir</tt> cannot retrieve long file names in length of <tt>FF_MAX_LFN - 1</tt> characters.<br>
+Fixed <tt>f_readdir</tt> returns file names with wrong case conversion. (appeared at R0.12)<br>
+Fixed <tt>f_mkfs</tt> can fail to create exFAT volume in the second partition. (appeared at R0.12)<br>
+</td>
+<td>
+Usage of <tt>f_mkfs</tt> and <tt>f_fdisk</tt> is changed and some features are added to these functions.<br>
+</td>
+</tr>
+<tr>
+<td>R0.13c<br>Oct 14, 2018</td>
+<td>
+Supported <tt>stdint.h</tt> for C99 and later. (<tt>integer.h</tt> was included in <tt>ff.h</tt>)<br>
+Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)<br>
+Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)<br>
+Fixed <tt>f_getcwd</tt> cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)<br>
+</td>
+<td>
+From this revision, FatFs depends on <tt>stdint.h</tt> in C99 or later.<br>
+<tt>integer.h</tt> is removed.<br>
+</td>
+</tr>
+<tr>
+<td>R0.13b<br>Apr 07, 2018</td>
+<td>
+Added support for UTF-32 encoding on the API. (<tt>FF_LFN_UNICODE = 3</tt>)<br>
+Added support for Unix style volume prefix. (<tt>FF_STR_VOLUME_ID = 2</tt>)<br>
+Fixed accesing objects in the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)<br>
+Fixed <tt>f_setlabel</tt> does not reject some invalid characters. (appeared at R0.09b)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.13a<br>Oct 14, 2017</td>
+<td>
+Added support for UTF-8 encoding on the API. (<tt>FF_LFN_UNICODE = 2</tt>)<br>
+Added options for file name output buffer. (<tt>FF_LFN_BUF, FF_SFN_BUF</tt>)<br>
+Added dynamic memory allocation option for working buffer of <tt>f_mkfs</tt> and <tt>f_fdisk</tt>.<br>
+Fixed <tt>f_fdisk</tt> and <tt>f_mkfs</tt> create the partition table with wrong CHS parameters. (appeared at R0.09)<br>
+Fixed <tt>f_unlink</tt> can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)<br>
+Fixed <tt>f_setlabel</tt> rejects some valid characters for exFAT volume. (appeared at R0.12)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.13<br>May 21, 2017</td>
+<td>
+Prefix of configuration item names are changed from <tt>"_"</tt> to <tt>"FF_"</tt>.<br>
+Added <tt>f_setcp</tt>, run-time code page configuration. (<tt>FF_CODE_PAGE = 0</tt>)<br>
+Improved cluster allocation time on stretch a deep buried cluster chain.<br>
+Improved processing time of <tt>f_mkdir</tt> with large cluster size by using <tt>FF_USE_LFN = 3</tt>.<br>
+Improved exFAT <tt>NoFatChain</tt> flag of the fragmented file to be set after it is truncated and got contiguous.<br>
+Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)<br>
+Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)<br>
+Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)<br>
+</td>
+<td>
+ASCII only configuration, <tt>FF_CODE_PAGE = 1</tt>, is removed. Use <tt>FF_CODE_PAGE = 437</tt> instead.<br>
+</td>
+</tr>
+<tr>
+<td>R0.12c<br>Mar 04, 2017</td>
+<td>
+Improved write throughput at the fragmented file on the exFAT volume.<br>
+Made memory usage for exFAT be able to be reduced as decreasing <tt>_MAX_LFN</tt>.<br>
+Fixed successive <tt>f_getfree</tt> can return wrong count on the FAT12/16 volume. (appeared at R0.12)<br>
+Fixed configuration option <tt>_VOLUMES</tt> cannot be set 10. (appeared at R0.10c)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.12b<br>Sep 4, 2016</td>
+<td>
+Made <tt>f_rename</tt> be able to rename objects with the same name but case.<br>
+Fixed an error in the case conversion teble of code page 866. (<tt>ff.c</tt>)<br>
+Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)<br>
+Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)<br>
+Fixed <tt>f_mkfs</tt> creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12a)<br>
+Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)<br>
+Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)<br>
+Fixed some internal errors in <tt>f_expand</tt> and <tt>f_lseek.</tt> (appeared at R0.12)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.12a<br>Jul 10, 2016</td>
+<td>
+Added support for creating exFAT volume with some changes of <tt>f_mkfs</tt>.<br>
+Added a file open method <tt>FA_OPEN_APPEND</tt>.<br>
+<tt>f_forward</tt> is available regardless of <tt>_FS_TINY</tt>.<br>
+Fixed <tt>f_mkfs</tt> creates broken volume. (appeared at R0.12)<br>
+Fixed wrong memory read in <tt>create_name</tt>. (appeared at R0.12)<br>
+Fixed compilation fails at some configurations, <tt>_USE_FASTSEEK</tt> and <tt>_USE_FORWARD</tt>.<br>
+</td>
+<td>
+Usage of <tt>f_mkfs</tt> is changed.<br>
+</td>
+</tr>
+<tr>
+<td>R0.12<br>Apr 12, 2016</td>
+<td>
+Added support for exFAT file system. (<tt>_FS_EXFAT</tt>)<br>
+Added <tt>f_expand</tt>. (<tt>_USE_EXPAND</tt>)<br>
+Changed some members in <tt>FINFO</tt> and behavior of <tt>f_readdir</tt>.<br>
+Added a configuration option <tt>_USE_CHMOD</tt>.<br>
+Fixed errors in the case conversion teble of Unicode (<tt>cc*.c</tt>).<br>
+</td>
+<td>
+Usage and members of <tt>FINFO</tt> sructure used in <tt>f_readdir</tt> is changed.<br>
+Many members in <tt>FIL</tt> and <tt>DIR</tt> structure are changed.<br>
+To use <tt>f_chmod</tt>, <tt>_USE_CHMOD</tt> needs to be set.<br>
+<tt>_WORD_ACCESS</tt> is removed from the configuration options.<br>
+Dot entries are never appear in <tt>f_reeddir</tt>.<br>
+</td>
+</tr>
+<tr>
+<td>R0.11a<br>Sep 5, 2015</td>
+<td>
+Fixed wrong media change can lead a deadlock at thread-safe configuration.<br>
+Added code page 771, 860, 861, 863, 864, 865 and 869. (<tt>_CODE_PAGE</tt>)<br>
+Fixed errors in the case conversion teble of code page 437 and 850 (<tt>ff.c</tt>).<br>
+Fixed errors in the case conversion teble of Unicode (<tt>cc*.c</tt>).<br>
+</td>
+<td>
+Removed some code pages actually not exist on the standard systems. (<tt>_CODE_PAGE</tt>)<br>
+</td>
+</tr>
+<tr>
+<td>R0.11<br>Feb 9, 2015</td>
+<td>
+Added <tt>f_findfirst</tt> and <tt>f_findnext.</tt> (<tt>_USE_FIND</tt>)<br>
+Fixed <tt>f_unlink</tt> does not remove cluster chain of the file. (appeared at R0.10c)<br>
+Fixed <tt>_FS_NORTC</tt> option does not work properly. (appeared at R0.10c)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.10c<br>Nov 9, 2014</td>
+<td>
+Added a configuration option for the platforms without RTC. (<tt>_FS_NORTC</tt>)<br>
+Fixed volume label created by Mac OS X cannot be retrieved with <tt>f_getlabel</tt>. (appeared at R0.09b)<br>
+Fixed a potential problem of FAT access that can appear on disk error.<br>
+Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.10b<br>May 19, 2014</td>
+<td>
+Fixed a hard error in the disk I/O layer can collapse the directory entry.<br>
+Fixed LFN entry is not deleted on delete/rename an object with its lossy converted SFN. (appeared at R0.07)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.10a<br>Jan 15, 2014</td>
+<td>
+Added arbitrary strings as drive number in the path name. (<tt>_STR_VOLUME_ID</tt>)<br>
+Added an option for minimum sector size. (<tt>_MIN_SS</tt>)<br>
+2nd argument of <tt>f_rename</tt> can have a drive number and it will be ignored.<br>
+Fixed <tt>f_mount</tt> with forced mount fails when drive number is larger than 0. (appeared at R0.10)<br>
+Fixed <tt>f_close</tt> invalidates the file object without volume lock.<br>
+Fixed volume lock is left acquired after return from <tt>f_closedir</tt>. (appeared at R0.10)<br>
+Fixed creation of a directory entry with LFN fails on too many SFN collisions. (appeared at R0.07)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.10<br>Oct 2, 2013</td>
+<td>
+Added an option for character encoding on the file. (<tt>_STRF_ENCODE</tt>)<br>
+Added f_closedir.<br>
+Added forced full FAT scan option for <tt>f_getfree</tt>. (<tt>_FS_NOFSINFO</tt>)<br>
+Added forced mount option with changes of <tt>f_mount</tt>.<br>
+Improved behavior of volume auto detection.<br>
+Improved write throughput of <tt>f_puts</tt> and <tt>f_printf</tt>.<br>
+Changed argument of <tt>f_chdrive,</tt> <tt>f_mkfs</tt>, <tt>disk_read</tt> and <tt>disk_write</tt>.<br>
+Fixed <tt>f_write</tt> can be truncated when the file size is close to 4 GB.<br>
+Fixed <tt>f_open</tt>, <tt>f_mkdir</tt> and <tt>f_setlabel</tt> can return incorrect result code on error.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.09b<br>Jan 24, 2013</td>
+<td>
+Added <tt>f_getlabel</tt> and <tt>f_setlabel</tt>. (<tt>_USE_LABEL</tt>)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.09a<br>Aug 27, 2012</td>
+<td>
+Fixed assertion failure due to OS/2 EA on FAT12/16 volume.<br>
+Changed file functions reject null object pointer to avoid crash.<br>
+Changed option name <tt>_FS_SHARE</tt> to <tt>_FS_LOCK</tt>.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.09<br>Sep 6, 2011</td>
+<td>
+<tt>f_mkfs</tt> supports multiple partition on a physical drive.<br>
+Added <tt>f_fdisk</tt>. (<tt>_MULTI_PARTITION = 2</tt>)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.08b<br>Jan 15, 2011</td>
+<td>
+Fast seek function is also applied to <tt>f_read</tt> and <tt>f_write</tt>.<br>
+<tt>f_lseek</tt> reports required table size on creating CLMP.<br>
+Extended format syntax of <tt>f_printf</tt>.<br>
+Ignores duplicated directory separators in given path names.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.08a<br>Aug 16, 2010</td>
+<td>
+Added <tt>f_getcwd</tt>. (<tt>_FS_RPATH = 2</tt>)<br>
+Added sector erase function. (<tt>_USE_ERASE</tt>)<br>
+Moved file lock semaphore table from fs object to the bss.<br>
+Fixed <tt>f_mkdir</tt> creates wrong directory on non-LFN cfg when the given name contains <tt>';'</tt>.<br>
+Fixed <tt>f_mkfs</tt> creates wrong FAT32 volume.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.08<br>May 15, 2010</td>
+<td>
+Added an option to <tt>_USE_LFN</tt><br>
+Added support of file lock. (<tt>_FS_SHARE</tt>)<br>
+Added fast seek function. (<tt>_USE_FASTSEEK</tt>)<br>
+Changed a type name on the API, <tt>XCHAR</tt> to <tt>TCHAR</tt>.<br>
+Changed member, <tt>fname</tt>, in the <tt>FILINFO</tt> on Unicode cfg.<br>
+String functions support UTF-8 encoding files on Unicode cfg.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.07e<br>Nov 3, 2009</td>
+<td>
+Separated out configuration options from <tt>ff.h</tt> to <tt>ffconf.h</tt>.<br>
+Added a configuration option, <tt>_LFN_UNICODE</tt>.<br>
+Fixed <tt>f_unlink</tt> fails to remove a sub-dir on <tt>_FS_RPATH</tt>.<br>
+Fixed name matching error on the 13 char boundary.<br>
+Changed <tt>f_readdir</tt> to return the SFN with always upper case on non-LFN cfg.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.07c<br>Jan 21, 2009</td>
+<td>
+Fixed <tt>f_unlink</tt> may return FR_OK on error.<br>
+Fixed wrong cache control in <tt>f_lseek</tt>.<br>
+Added support of relative path.<br>
+Added <tt>f_chdir</tt>.<br>
+Added <tt>f_chdrive</tt>.<br>
+Added proper case conversion to extended characters.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.07a<br>Apr 14, 2009</td>
+<td>
+Separated out OS dependent code on re-entrant configuration.<br>
+Added multiple sector size support.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.07<br>Apr 1, 2009</td>
+<td>
+Merged Tiny-FatFs into FatFs as a buffer configuration option.<br>
+Added support for long file extension.<br>
+Added multiple code page support.<br>
+Added re-entrancy for multitask operation.<br>
+Added auto cluster size selection to <tt>f_mkfs</tt>.<br>
+Added rewind option to <tt>f_readdir</tt>.<br>
+Changed result code of critical errors.<br>
+Renamed string functions to avoid name collision.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.06<br>Apr 1, 2008</td>
+<td>
+Added <tt>f_forward</tt>. (Tiny-FatFs)<br>
+Added string functions: <tt>f_gets</tt>, <tt>f_putc</tt>, <tt>f_puts</tt> and <tt>f_printf</tt>.<br>
+Improved performance of <tt>f_lseek</tt> on moving to the same or following cluster.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.05a<br>Feb 3, 2008</td>
+<td>
+Added <tt>f_truncate</tt>.<br>
+Added <tt>f_utime</tt>.<br>
+Fixed off by one error at FAT sub-type determination.<br>
+Fixed btr in <tt>f_read</tt> can be mistruncated.<br>
+Fixed cached sector is left not flushed when create and close without write.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.05<br>Aug 26, 2007</td>
+<td>
+Changed arguments of <tt>f_read</tt>, <tt>f_write</tt>.<br>
+Changed arguments of <tt>f_mkfs</tt>. (FatFs)<br>
+Fixed <tt>f_mkfs</tt> on FAT32 creates incorrect FSInfo. (FatFs)<br>
+Fixed <tt>f_mkdir</tt> on FAT32 creates broken directory. (FatFs)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.04b<br>May 5, 2007</td>
+<td>
+Added <tt>_USE_NTFLAG</tt> option.<br>
+Added support for FSInfo in FAT32 volume.<br>
+Fixed some problems corresponds to FAT32. (Tiny-FatFs)<br>
+Fixed DBCS name can result <tt>FR_INVALID_NAME</tt>.<br>
+Fixed short seek (<tt>&lt;= csize</tt>) collapses the file object.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.04a<br>Apr 1, 2007</td>
+<td>
+Supported multiple partitions on a plysical drive. (FatFs)<br>
+Added minimization level 3.<br>
+Added a capability of extending file size to <tt>f_lseek</tt>.<br>
+Fixed an endian sensitive code in <tt>f_mkfs</tt>. (FatFs)<br>
+Fixed a problem corresponds to FAT32 support. (Tiny-FatFs)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.04<br>Feb 4, 2007</td>
+<td>
+Supported multiple drive system. (FatFs)<br>
+Changed some APIs for multiple drive system.<br>
+Added <tt>f_mkfs</tt>. (FatFs)<br>
+Added <tt>_USE_FAT32</tt> option. (Tiny-FatFs)<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.03a<br>Dec 11, 2006</td>
+<td>
+Improved cluster scan algolithm to write files fast.<br>
+Fixed <tt>f_mkdir</tt> creates broken directory on FAT32.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.03<br>Sep 22, 2006</td>
+<td>
+Added <tt>f_rename</tt>.
+Changed option <tt>_FS_MINIMUM</tt> to <tt>_FS_MINIMIZE</tt>.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.02a<br>Jun 10, 2006</td>
+<td>
+Added a configuration option <tt>_FS_MINIMUM</tt>.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.02<br>Jun 01, 2006</td>
+<td>
+Added FAT12.<br>
+Removed unbuffered mode.<br>
+Fixed a problem on small (<tt>&lt;32M</tt>) patition.<br>
+</td>
+<td>
+</td>
+</tr>
+<tr>
+<td>R0.01<br>Apr 29, 2006</td>
+<td>
+First release.<br>
+</td>
+<td>
+</td>
+</tr>
+</table>
+</body>
+</html>
diff --git a/MCUME_pico2/fatfs/readme.txt b/MCUME_pico2/fatfs/readme.txt
new file mode 100755
index 0000000..36cb1aa
--- /dev/null
+++ b/MCUME_pico2/fatfs/readme.txt
@@ -0,0 +1 @@
+https://github.com/abbrev/fatfs
diff --git a/MCUME_pico2/fatfs/source/.DS_Store b/MCUME_pico2/fatfs/source/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/fatfs/source/.DS_Store differ
diff --git a/MCUME_pico2/fatfs/source/00history.txt b/MCUME_pico2/fatfs/source/00history.txt
new file mode 100644
index 0000000..4fa1d7a
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/00history.txt
@@ -0,0 +1,369 @@
+----------------------------------------------------------------------------
+  Revision history of FatFs module
+----------------------------------------------------------------------------
+
+R0.00 (February 26, 2006)
+
+  Prototype.
+
+
+
+R0.01 (April 29, 2006)
+
+  The first release.
+
+
+
+R0.02 (June 01, 2006)
+
+  Added FAT12 support.
+  Removed unbuffered mode.
+  Fixed a problem on small (<32M) partition.
+
+
+
+R0.02a (June 10, 2006)
+
+  Added a configuration option (_FS_MINIMUM).
+
+
+
+R0.03 (September 22, 2006)
+
+  Added f_rename().
+  Changed option _FS_MINIMUM to _FS_MINIMIZE.
+
+
+
+R0.03a (December 11, 2006)
+
+  Improved cluster scan algorithm to write files fast.
+  Fixed f_mkdir() creates incorrect directory on FAT32.
+
+
+
+R0.04 (February 04, 2007)
+
+  Added f_mkfs().
+  Supported multiple drive system.
+  Changed some interfaces for multiple drive system.
+  Changed f_mountdrv() to f_mount().
+
+
+
+R0.04a (April 01, 2007)
+
+  Supported multiple partitions on a physical drive.
+  Added a capability of extending file size to f_lseek().
+  Added minimization level 3.
+  Fixed an endian sensitive code in f_mkfs().
+
+
+
+R0.04b (May 05, 2007)
+
+  Added a configuration option _USE_NTFLAG.
+  Added FSINFO support.
+  Fixed DBCS name can result FR_INVALID_NAME.
+  Fixed short seek (<= csize) collapses the file object.
+
+
+
+R0.05 (August 25, 2007)
+
+  Changed arguments of f_read(), f_write() and f_mkfs().
+  Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
+  Fixed f_mkdir() on FAT32 creates incorrect directory.
+
+
+
+R0.05a (February 03, 2008)
+
+  Added f_truncate() and f_utime().
+  Fixed off by one error at FAT sub-type determination.
+  Fixed btr in f_read() can be mistruncated.
+  Fixed cached sector is not flushed when create and close without write.
+
+
+
+R0.06 (April 01, 2008)
+
+  Added fputc(), fputs(), fprintf() and fgets().
+  Improved performance of f_lseek() on moving to the same or following cluster.
+
+
+
+R0.07 (April 01, 2009)
+
+  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+  Added long file name feature. (_USE_LFN)
+  Added multiple code page feature. (_CODE_PAGE)
+  Added re-entrancy for multitask operation. (_FS_REENTRANT)
+  Added auto cluster size selection to f_mkfs().
+  Added rewind option to f_readdir().
+  Changed result code of critical errors.
+  Renamed string functions to avoid name collision.
+
+
+
+R0.07a (April 14, 2009)
+
+  Septemberarated out OS dependent code on reentrant cfg.
+  Added multiple sector size feature.
+
+
+
+R0.07c (June 21, 2009)
+
+  Fixed f_unlink() can return FR_OK on error.
+  Fixed wrong cache control in f_lseek().
+  Added relative path feature.
+  Added f_chdir() and f_chdrive().
+  Added proper case conversion to extended character.
+
+
+
+R0.07e (November 03, 2009)
+
+  Septemberarated out configuration options from ff.h to ffconf.h.
+  Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
+  Fixed name matching error on the 13 character boundary.
+  Added a configuration option, _LFN_UNICODE.
+  Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+
+
+
+R0.08 (May 15, 2010)
+
+  Added a memory configuration option. (_USE_LFN = 3)
+  Added file lock feature. (_FS_SHARE)
+  Added fast seek feature. (_USE_FASTSEEK)
+  Changed some types on the API, XCHAR->TCHAR.
+  Changed .fname in the FILINFO structure on Unicode cfg.
+  String functions support UTF-8 encoding files on Unicode cfg.
+
+
+
+R0.08a (August 16, 2010)
+
+  Added f_getcwd(). (_FS_RPATH = 2)
+  Added sector erase feature. (_USE_ERASE)
+  Moved file lock semaphore table from fs object to the bss.
+  Fixed f_mkfs() creates wrong FAT32 volume.
+
+
+
+R0.08b (January 15, 2011)
+
+  Fast seek feature is also applied to f_read() and f_write().
+  f_lseek() reports required table size on creating CLMP.
+  Extended format syntax of f_printf().
+  Ignores duplicated directory separators in given path name.
+
+
+
+R0.09 (September 06, 2011)
+
+  f_mkfs() supports multiple partition to complete the multiple partition feature.
+  Added f_fdisk().
+
+
+
+R0.09a (August 27, 2012)
+
+  Changed f_open() and f_opendir() reject null object pointer to avoid crash.
+  Changed option name _FS_SHARE to _FS_LOCK.
+  Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+
+
+
+R0.09b (January 24, 2013)
+
+  Added f_setlabel() and f_getlabel().
+
+
+
+R0.10 (October 02, 2013)
+
+  Added selection of character encoding on the file. (_STRF_ENCODE)
+  Added f_closedir().
+  Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
+  Added forced mount feature with changes of f_mount().
+  Improved behavior of volume auto detection.
+  Improved write throughput of f_puts() and f_printf().
+  Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
+  Fixed f_write() can be truncated when the file size is close to 4GB.
+  Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
+
+
+
+R0.10a (January 15, 2014)
+
+  Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
+  Added a configuration option of minimum sector size. (_MIN_SS)
+  2nd argument of f_rename() can have a drive number and it will be ignored.
+  Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
+  Fixed f_close() invalidates the file object without volume lock.
+  Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
+  Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
+
+
+
+R0.10b (May 19, 2014)
+
+  Fixed a hard error in the disk I/O layer can collapse the directory entry.
+  Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
+
+
+
+R0.10c (November 09, 2014)
+
+  Added a configuration option for the platforms without RTC. (_FS_NORTC)
+  Changed option name _USE_ERASE to _USE_TRIM.
+  Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
+  Fixed a potential problem of FAT access that can appear on disk error.
+  Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
+
+
+
+R0.11 (February 09, 2015)
+
+  Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
+  Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
+  Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
+
+
+
+R0.11a (September 05, 2015)
+
+  Fixed wrong media change can lead a deadlock at thread-safe configuration.
+  Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
+  Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
+  Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
+  Fixed errors in the case conversion teble of Unicode (cc*.c).
+
+
+
+R0.12 (April 12, 2016)
+
+  Added support for exFAT file system. (_FS_EXFAT)
+  Added f_expand(). (_USE_EXPAND)
+  Changed some members in FINFO structure and behavior of f_readdir().
+  Added an option _USE_CHMOD.
+  Removed an option _WORD_ACCESS.
+  Fixed errors in the case conversion table of Unicode (cc*.c).
+
+
+
+R0.12a (July 10, 2016)
+
+  Added support for creating exFAT volume with some changes of f_mkfs().
+  Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
+  f_forward() is available regardless of _FS_TINY.
+  Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
+  Fixed wrong memory read in create_name(). (appeared at R0.12)
+  Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
+
+
+
+R0.12b (September 04, 2016)
+
+  Made f_rename() be able to rename objects with the same name but case.
+  Fixed an error in the case conversion teble of code page 866. (ff.c)
+  Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
+  Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
+  Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
+  Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
+  Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
+  Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
+
+
+
+R0.12c (March 04, 2017)
+
+  Improved write throughput at the fragmented file on the exFAT volume.
+  Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
+  Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
+  Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
+
+
+
+R0.13 (May 21, 2017)
+
+  Changed heading character of configuration keywords "_" to "FF_".
+  Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
+  Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
+  Improved cluster allocation time on stretch a deep buried cluster chain.
+  Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
+  Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
+  Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
+  Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
+  Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
+
+
+
+R0.13a (October 14, 2017)
+
+  Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
+  Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
+  Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
+  Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
+  Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
+  Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
+
+
+
+R0.13b (April 07, 2018)
+
+  Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
+  Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
+  Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
+  Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
+
+
+
+R0.13c (October 14, 2018)
+  Supported stdint.h for C99 and later. (integer.h was included in ff.h)
+  Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
+  Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
+  Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
+
+
+
+R0.14 (October 14, 2019)
+  Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
+  Changed some API functions, f_mkfs() and f_fdisk().
+  Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
+  Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
+  Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
+  Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)
+
+
+R0.14a (December 5, 2020)
+  Limited number of recursive calls in f_findnext().
+  Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted.
+  Fixed some compiler warnings.
+
+
+
+R0.14b (April 17, 2021)
+  Made FatFs uses standard library <string.h> for copy, compare and search instead of built-in string functions.
+  Added support for long long integer and floating point to f_printf(). (FF_STRF_LLI and FF_STRF_FP)
+  Made path name parser ignore the terminating separator to allow "dir/".
+  Improved the compatibility in Unix style path name feature.
+  Fixed the file gets dead-locked when f_open() failed with some conditions. (appeared at R0.12a)
+  Fixed f_mkfs() can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12)
+  Fixed code page 855 cannot be set by f_setcp().
+  Fixed some compiler warnings.
+
+
+
+R0.15 (November 6, 2022)
+  Changed user provided synchronization functions in order to completely eliminate the platform dependency from FatFs code.
+  FF_SYNC_t is removed from the configuration options.
+  Fixed a potential error in f_mount when FF_FS_REENTRANT.
+  Fixed file lock control FF_FS_LOCK is not mutal excluded when FF_FS_REENTRANT && FF_VOLUMES > 1 is true.
+  Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors.
+  Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8).
+  Fixed a compatibility issue in identification of GPT header.
+
diff --git a/MCUME_pico2/fatfs/source/00readme.txt b/MCUME_pico2/fatfs/source/00readme.txt
new file mode 100644
index 0000000..39f6c8c
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/00readme.txt
@@ -0,0 +1,21 @@
+FatFs Module Source Files R0.15
+
+
+FILES
+
+  00readme.txt   This file.
+  00history.txt  Revision history.
+  ff.c           FatFs module.
+  ffconf.h       Configuration file of FatFs module.
+  ff.h           Common include file for FatFs and application module.
+  diskio.h       Common include file for FatFs and disk I/O module.
+  diskio.c       An example of glue function to attach existing disk I/O module to FatFs.
+  ffunicode.c    Optional Unicode utility functions.
+  ffsystem.c     An example of optional O/S related functions.
+
+
+  Low level disk I/O module is not included in this archive because the FatFs
+  module is only a generic file system layer and it does not depend on any specific
+  storage device. You need to provide a low level disk I/O module written to
+  control the storage device that attached to the target system.
+
diff --git a/MCUME_pico2/fatfs/source/diskio.c b/MCUME_pico2/fatfs/source/diskio.c
new file mode 100644
index 0000000..81aaf59
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/diskio.c
@@ -0,0 +1,229 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module SKELETON for FatFs     (C)ChaN, 2019        */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various exsisting      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+#include "ff.h"			/* Obtains integer types */
+#include "diskio.h"		/* Declarations of disk functions */
+
+/* Definitions of physical drive number for each drive */
+#define DEV_RAM		0	/* Example: Map Ramdisk to physical drive 0 */
+#define DEV_MMC		1	/* Example: Map MMC/SD card to physical drive 1 */
+#define DEV_USB		2	/* Example: Map USB MSD to physical drive 2 */
+
+
+/*-----------------------------------------------------------------------*/
+/* Get Drive Status                                                      */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive nmuber to identify the drive */
+)
+{
+	DSTATUS stat;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		result = RAM_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_MMC :
+		result = MMC_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_USB :
+		result = USB_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+	}
+	return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive                                                    */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+	DSTATUS stat;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		result = RAM_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_MMC :
+		result = MMC_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_USB :
+		result = USB_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+	}
+	return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	LBA_t sector,	/* Start sector in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		// translate the arguments here
+
+		result = RAM_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_MMC :
+		// translate the arguments here
+
+		result = MMC_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_USB :
+		// translate the arguments here
+
+		result = USB_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+
+#if FF_FS_READONLY == 0
+
+DRESULT disk_write (
+	BYTE pdrv,			/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	LBA_t sector,		/* Start sector in LBA */
+	UINT count			/* Number of sectors to write */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		// translate the arguments here
+
+		result = RAM_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_MMC :
+		// translate the arguments here
+
+		result = MMC_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_USB :
+		// translate the arguments here
+
+		result = USB_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions                                               */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+
+		// Process of the command for the RAM drive
+
+		return res;
+
+	case DEV_MMC :
+
+		// Process of the command for the MMC/SD card
+
+		return res;
+
+	case DEV_USB :
+
+		// Process of the command the USB drive
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
diff --git a/MCUME_pico2/fatfs/source/diskio.h b/MCUME_pico2/fatfs/source/diskio.h
new file mode 100644
index 0000000..c22afaa
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/diskio.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2019          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
+#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+#define ISDIO_READ			55	/* Read data form SD iSDIO register */
+#define ISDIO_WRITE			56	/* Write data to SD iSDIO register */
+#define ISDIO_MRITE			57	/* Masked write data to SD iSDIO register */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/MCUME_pico2/fatfs/source/ff.c b/MCUME_pico2/fatfs/source/ff.c
new file mode 100644
index 0000000..2091847
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/ff.c
@@ -0,0 +1,7090 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  R0.15 w/patch3                      /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#include <string.h>
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of device I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if FF_DEFINED != 80286	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Limits and boundaries */
+#define MAX_DIR		0x200000		/* Max size of FAT directory */
+#define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+#define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+#define MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* Character code support macros */
+#define IsUpper(c)		((c) >= 'A' && (c) <= 'Z')
+#define IsLower(c)		((c) >= 'a' && (c) <= 'z')
+#define IsDigit(c)		((c) >= '0' && (c) <= '9')
+#define IsSeparator(c)	((c) == '/' || (c) == '\\')
+#define IsTerminator(c)	((UINT)(c) < (FF_USE_LFN ? ' ' : '!'))
+#define IsSurrogate(c)	((c) >= 0xD800 && (c) <= 0xDFFF)
+#define IsSurrogateH(c)	((c) >= 0xD800 && (c) <= 0xDBFF)
+#define IsSurrogateL(c)	((c) >= 0xDC00 && (c) <= 0xDFFF)
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+#define FA_MODIFIED	0x40	/* File has been modified */
+#define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+
+
+/* Additional file attribute bits for internal use */
+#define AM_VOL		0x08	/* Volume label */
+#define AM_LFN		0x0F	/* LFN entry */
+#define AM_MASK		0x3F	/* Mask of defined bits in FAT */
+#define AM_MASKX	0x37	/* Mask of defined bits in exFAT */
+
+
+/* Name status flags in fn[11] */
+#define NSFLAG		11		/* Index of the name status byte */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+#define NS_NOLFN	0x40	/* Do not find LFN */
+#define NS_NONAME	0x80	/* Not followed */
+
+
+/* exFAT directory entry types */
+#define	ET_BITMAP	0x81	/* Allocation bitmap */
+#define	ET_UPCASE	0x82	/* Up-case table */
+#define	ET_VLABEL	0x83	/* Volume label */
+#define	ET_FILEDIR	0x85	/* File and directory */
+#define	ET_STREAM	0xC0	/* Stream extension */
+#define	ET_FILENAME	0xC1	/* Name extension */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+#define BS_OEMName			3		/* OEM name (8-byte) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+#define BPB_RootEntCnt		17		/* Size of root directory area for FAT [entry] (WORD) */
+#define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media			21		/* Media descriptor byte (BYTE) */
+#define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk		24		/* Number of sectors per track for int13h [sector] (WORD) */
+#define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+#define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+#define BS_NTres			37		/* WindowsNT error flag (BYTE) */
+#define BS_BootSig			38		/* Extended boot signature (BYTE) */
+#define BS_VolID			39		/* Volume serial number (DWORD) */
+#define BS_VolLab			43		/* Volume label string (8-byte) */
+#define BS_FilSysType		54		/* Filesystem type string (8-byte) */
+#define BS_BootCode			62		/* Boot code (448-byte) */
+#define BS_55AA				510		/* Signature word (WORD) */
+
+#define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32			42		/* FAT32: Filesystem version (WORD) */
+#define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+#define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32		82		/* FAT32: Filesystem type string (8-byte) */
+#define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx			104		/* exFAT: Filesystem version (WORD) */
+#define BPB_VolFlagEx		106		/* exFAT: Volume flags (WORD) */
+#define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+#define BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+
+#define DIR_Name			0		/* Short file name (11-byte) */
+#define DIR_Attr			11		/* Attribute (BYTE) */
+#define DIR_NTres			12		/* Lower case flag (BYTE) */
+#define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+#define DIR_CrtTime			14		/* Created time (DWORD) */
+#define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+#define DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+#define DIR_ModTime			22		/* Modified time (DWORD) */
+#define DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+#define DIR_FileSize		28		/* File size (DWORD) */
+#define LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+#define LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+#define LDIR_Type			12		/* LFN: Entry type (BYTE) */
+#define LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+#define LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+#define XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+#define XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+#define XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+#define XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+#define XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+#define XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+#define XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+#define XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+#define XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+#define XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+#define XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+#define XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+#define XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+#define XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+#define XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+#define XDIR_GenFlags		33		/* exFAT: General secondary flags (BYTE) */
+#define XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+#define XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+#define XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+#define XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+
+#define SZDIRE				32		/* Size of a directory entry */
+#define DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+#define RDDEM				0x05	/* Replacement of the character collides with DDEM */
+#define LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+
+#define FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+#define FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+#define FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+#define FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+#define SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define PTE_Boot			0		/* MBR PTE: Boot indicator */
+#define PTE_StHead			1		/* MBR PTE: Start head */
+#define PTE_StSec			2		/* MBR PTE: Start sector */
+#define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+#define PTE_System			4		/* MBR PTE: System ID */
+#define PTE_EdHead			5		/* MBR PTE: End head */
+#define PTE_EdSec			6		/* MBR PTE: End sector */
+#define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+#define PTE_StLba			8		/* MBR PTE: Start in LBA */
+#define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+
+#define GPTH_Sign			0		/* GPT HDR: Signature (8-byte) */
+#define GPTH_Rev			8		/* GPT HDR: Revision (DWORD) */
+#define GPTH_Size			12		/* GPT HDR: Header size (DWORD) */
+#define GPTH_Bcc			16		/* GPT HDR: Header BCC (DWORD) */
+#define GPTH_CurLba			24		/* GPT HDR: This header LBA (QWORD) */
+#define GPTH_BakLba			32		/* GPT HDR: Another header LBA (QWORD) */
+#define GPTH_FstLba			40		/* GPT HDR: First LBA for partition data (QWORD) */
+#define GPTH_LstLba			48		/* GPT HDR: Last LBA for partition data (QWORD) */
+#define GPTH_DskGuid		56		/* GPT HDR: Disk GUID (16-byte) */
+#define GPTH_PtOfs			72		/* GPT HDR: Partition table LBA (QWORD) */
+#define GPTH_PtNum			80		/* GPT HDR: Number of table entries (DWORD) */
+#define GPTH_PteSize		84		/* GPT HDR: Size of table entry (DWORD) */
+#define GPTH_PtBcc			88		/* GPT HDR: Partition table BCC (DWORD) */
+#define SZ_GPTE				128		/* GPT PTE: Size of partition table entry */
+#define GPTE_PtGuid			0		/* GPT PTE: Partition type GUID (16-byte) */
+#define GPTE_UpGuid			16		/* GPT PTE: Partition unique GUID (16-byte) */
+#define GPTE_FstLba			32		/* GPT PTE: First LBA of partition (QWORD) */
+#define GPTE_LstLba			40		/* GPT PTE: Last LBA of partition (QWORD) */
+#define GPTE_Flags			48		/* GPT PTE: Partition flags (QWORD) */
+#define GPTE_Name			56		/* GPT PTE: Partition name */
+
+
+/* Post process on fatal error in the file operations */
+#define ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Re-entrancy related */
+#if FF_FS_REENTRANT
+#if FF_USE_LFN == 1
+#error Static LFN work area cannot be used in thread-safe configuration
+#endif
+#define LEAVE_FF(fs, res)	{ unlock_volume(fs, res); return res; }
+#else
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+
+/* Definitions of logical drive - physical location conversion */
+#if FF_MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt	/* Get partition number (0:auto search, 1..:forced partition number) */
+#else
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is associated with the same physical drive number */
+#define LD2PT(vol) 0			/* Auto partition search */
+#endif
+
+
+/* Definitions of sector size */
+#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if FF_MAX_SS == FF_MIN_SS
+#define SS(fs)	((UINT)FF_MAX_SS)	/* Fixed sector size */
+#else
+#define SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if FF_FS_NORTC == 1
+#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31
+#error Invalid FF_FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File lock controls */
+#if FF_FS_LOCK
+#if FF_FS_READONLY
+#error FF_FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS* fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+	DWORD ofs;		/* Object ID 3, offset in the directory */
+	UINT ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+/* SBCS up-case tables (\x80-\xFF) */
+#define TBL_CT437  {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT720  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT737  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+					0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT771  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT775  {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+					0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT850  {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+					0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+					0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT852  {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+					0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT855  {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+					0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+					0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+					0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+					0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT857  {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+					0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT860  {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+					0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT861  {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+					0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT862  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT863  {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+					0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+					0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT864  {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT865  {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT866  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT869  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+					0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+					0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+					0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+
+/* DBCS code range |----- 1st byte -----|  |----------- 2nd byte -----------| */
+/*                  <------>    <------>    <------>    <------>    <------>  */
+#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00}
+#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00}
+#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE}
+#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00}
+
+
+/* Macros for table definitions */
+#define MERGE_2STR(a, b) a ## b
+#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp)
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+/* Remark: Variables defined here without initial value shall be guaranteed
+/  zero/null at start-up. If not, the linker option or start-up routine is
+/  not compliance with C standard. */
+
+/*--------------------------------*/
+/* File/Volume controls           */
+/*--------------------------------*/
+
+#if FF_VOLUMES < 1 || FF_VOLUMES > 10
+#error Wrong FF_VOLUMES setting
+#endif
+static FATFS *FatFs[FF_VOLUMES];	/* Pointer to the filesystem objects (logical drives) */
+static WORD Fsid;					/* Filesystem mount ID */
+
+#if FF_FS_RPATH != 0
+static BYTE CurrVol;				/* Current drive set by f_chdrive() */
+#endif
+
+#if FF_FS_LOCK
+static FILESEM Files[FF_FS_LOCK];	/* Open object lock semaphores */
+#if FF_FS_REENTRANT
+static volatile BYTE SysLock;		/* System lock flag to protect Files[] (0:no mutex, 1:unlocked, 2:locked) */
+static volatile BYTE SysLockVolume;	/* Volume id who is locking Files[] */
+#endif
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifdef FF_VOLUME_STRS
+static const char *const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS};	/* Pre-defined volume ID */
+#endif
+#endif
+
+#if FF_LBA64
+#if FF_MIN_GPT > 0x100000000
+#error Wrong FF_MIN_GPT setting
+#endif
+static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7};
+#endif
+
+
+
+/*--------------------------------*/
+/* LFN/Directory working buffer   */
+/*--------------------------------*/
+
+#if FF_USE_LFN == 0		/* Non-LFN configuration */
+#if FF_FS_EXFAT
+#error LFN must be enabled when enable exFAT
+#endif
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res)	return res
+
+#else					/* LFN configurations */
+#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255
+#error Wrong setting of FF_MAX_LFN
+#endif
+#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12
+#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF
+#endif
+#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3
+#error Wrong setting of FF_LFN_UNICODE
+#endif
+static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* FAT: Offset of LFN characters in the directory entry */
+#define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)	/* exFAT: Size of directory entry block scratchpad buffer needed for the name length */
+
+#if FF_USE_LFN == 1		/* LFN enabled with static working buffer */
+#if FF_FS_EXFAT
+static BYTE	DirBuf[MAXDIRB(FF_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[FF_MAX_LFN + 1];		/* LFN working buffer */
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res)	return res
+
+#elif FF_USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF		WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)];	/* LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define FREE_NAMBUF()
+#else
+#define DEF_NAMBUF		WCHAR lbuf[FF_MAX_LFN+1];	/* LFN working buffer */
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+#define FREE_NAMBUF()
+#endif
+#define LEAVE_MKFS(res)	return res
+
+#elif FF_USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF		WCHAR *lfn;	/* Pointer to LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
+#define FREE_NAMBUF()	ff_memfree(lfn)
+#else
+#define DEF_NAMBUF		WCHAR *lfn;	/* Pointer to LFN working buffer */
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define FREE_NAMBUF()	ff_memfree(lfn)
+#endif
+#define LEAVE_MKFS(res)	{ if (!work) ff_memfree(buf); return res; }
+#define MAX_MALLOC	0x8000	/* Must be >=FF_MAX_SS */
+
+#else
+#error Wrong setting of FF_USE_LFN
+
+#endif	/* FF_USE_LFN == 1 */
+#endif	/* FF_USE_LFN == 0 */
+
+
+
+/*--------------------------------*/
+/* Code conversion tables         */
+/*--------------------------------*/
+
+#if FF_CODE_PAGE == 0	/* Run-time code page configuration */
+#define CODEPAGE CodePage
+static WORD CodePage;	/* Current code page */
+static const BYTE* ExCvt;	/* Ptr to SBCS up-case table Ct???[] (null:not used) */
+static const BYTE* DbcTbl;	/* Ptr to DBCS code range table Dc???[] (null:not used) */
+
+static const BYTE Ct437[] = TBL_CT437;
+static const BYTE Ct720[] = TBL_CT720;
+static const BYTE Ct737[] = TBL_CT737;
+static const BYTE Ct771[] = TBL_CT771;
+static const BYTE Ct775[] = TBL_CT775;
+static const BYTE Ct850[] = TBL_CT850;
+static const BYTE Ct852[] = TBL_CT852;
+static const BYTE Ct855[] = TBL_CT855;
+static const BYTE Ct857[] = TBL_CT857;
+static const BYTE Ct860[] = TBL_CT860;
+static const BYTE Ct861[] = TBL_CT861;
+static const BYTE Ct862[] = TBL_CT862;
+static const BYTE Ct863[] = TBL_CT863;
+static const BYTE Ct864[] = TBL_CT864;
+static const BYTE Ct865[] = TBL_CT865;
+static const BYTE Ct866[] = TBL_CT866;
+static const BYTE Ct869[] = TBL_CT869;
+static const BYTE Dc932[] = TBL_DC932;
+static const BYTE Dc936[] = TBL_DC936;
+static const BYTE Dc949[] = TBL_DC949;
+static const BYTE Dc950[] = TBL_DC950;
+
+#elif FF_CODE_PAGE < 900	/* Static code page configuration (SBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE);
+
+#else					/* Static code page configuration (DBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
+
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure                       */
+/*-----------------------------------------------------------------------*/
+
+static WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+{
+	WORD rv;
+
+	rv = ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+static DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+{
+	DWORD rv;
+
+	rv = ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+#if FF_FS_EXFAT
+static QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+{
+	QWORD rv;
+
+	rv = ptr[7];
+	rv = rv << 8 | ptr[6];
+	rv = rv << 8 | ptr[5];
+	rv = rv << 8 | ptr[4];
+	rv = rv << 8 | ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+#endif
+
+#if !FF_FS_READONLY
+static void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+static void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+#if FF_FS_EXFAT
+static void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+#endif
+#endif	/* !FF_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Test if the byte is DBC 1st byte */
+static int dbc_1st (BYTE c)
+{
+#if FF_CODE_PAGE == 0		/* Variable code page */
+	if (DbcTbl && c >= DbcTbl[0]) {
+		if (c <= DbcTbl[1]) return 1;					/* 1st byte range 1 */
+		if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;	/* 1st byte range 2 */
+	}
+#elif FF_CODE_PAGE >= 900	/* DBCS fixed code page */
+	if (c >= DbcTbl[0]) {
+		if (c <= DbcTbl[1]) return 1;
+		if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;
+	}
+#else						/* SBCS fixed code page */
+	if (c != 0) return 0;	/* Always false */
+#endif
+	return 0;
+}
+
+
+/* Test if the byte is DBC 2nd byte */
+static int dbc_2nd (BYTE c)
+{
+#if FF_CODE_PAGE == 0		/* Variable code page */
+	if (DbcTbl && c >= DbcTbl[4]) {
+		if (c <= DbcTbl[5]) return 1;					/* 2nd byte range 1 */
+		if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;	/* 2nd byte range 2 */
+		if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;	/* 2nd byte range 3 */
+	}
+#elif FF_CODE_PAGE >= 900	/* DBCS fixed code page */
+	if (c >= DbcTbl[4]) {
+		if (c <= DbcTbl[5]) return 1;
+		if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;
+		if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;
+	}
+#else						/* SBCS fixed code page */
+	if (c != 0) return 0;	/* Always false */
+#endif
+	return 0;
+}
+
+
+#if FF_USE_LFN
+
+/* Get a Unicode code point from the TCHAR string in defined API encodeing */
+static DWORD tchar2uni (	/* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */
+	const TCHAR** str		/* Pointer to pointer to TCHAR string in configured encoding */
+)
+{
+	DWORD uc;
+	const TCHAR *p = *str;
+
+#if FF_LFN_UNICODE == 1		/* UTF-16 input */
+	WCHAR wc;
+
+	uc = *p++;	/* Get a unit */
+	if (IsSurrogate(uc)) {	/* Surrogate? */
+		wc = *p++;		/* Get low surrogate */
+		if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF;	/* Wrong surrogate? */
+		uc = uc << 16 | wc;
+	}
+
+#elif FF_LFN_UNICODE == 2	/* UTF-8 input */
+	BYTE b;
+	int nf;
+
+	uc = (BYTE)*p++;	/* Get an encoding unit */
+	if (uc & 0x80) {	/* Multiple byte code? */
+		if        ((uc & 0xE0) == 0xC0) {	/* 2-byte sequence? */
+			uc &= 0x1F; nf = 1;
+		} else if ((uc & 0xF0) == 0xE0) {	/* 3-byte sequence? */
+			uc &= 0x0F; nf = 2;
+		} else if ((uc & 0xF8) == 0xF0) {	/* 4-byte sequence? */
+			uc &= 0x07; nf = 3;
+		} else {							/* Wrong sequence */
+			return 0xFFFFFFFF;
+		}
+		do {	/* Get trailing bytes */
+			b = (BYTE)*p++;
+			if ((b & 0xC0) != 0x80) return 0xFFFFFFFF;	/* Wrong sequence? */
+			uc = uc << 6 | (b & 0x3F);
+		} while (--nf != 0);
+		if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF;	/* Wrong code? */
+		if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF);	/* Make a surrogate pair if needed */
+	}
+
+#elif FF_LFN_UNICODE == 3	/* UTF-32 input */
+	uc = (TCHAR)*p++;	/* Get a unit */
+	if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF;	/* Wrong code? */
+	if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF);	/* Make a surrogate pair if needed */
+
+#else		/* ANSI/OEM input */
+	BYTE b;
+	WCHAR wc;
+
+	wc = (BYTE)*p++;			/* Get a byte */
+	if (dbc_1st((BYTE)wc)) {	/* Is it a DBC 1st byte? */
+		b = (BYTE)*p++;			/* Get 2nd byte */
+		if (!dbc_2nd(b)) return 0xFFFFFFFF;	/* Invalid code? */
+		wc = (wc << 8) + b;		/* Make a DBC */
+	}
+	if (wc != 0) {
+		wc = ff_oem2uni(wc, CODEPAGE);	/* ANSI/OEM ==> Unicode */
+		if (wc == 0) return 0xFFFFFFFF;	/* Invalid code? */
+	}
+	uc = wc;
+
+#endif
+	*str = p;	/* Next read pointer */
+	return uc;
+}
+
+
+/* Store a Unicode char in defined API encoding */
+static UINT put_utf (	/* Returns number of encoding units written (0:buffer overflow or wrong encoding) */
+	DWORD chr,	/* UTF-16 encoded character (Surrogate pair if >=0x10000) */
+	TCHAR* buf,	/* Output buffer */
+	UINT szb	/* Size of the buffer */
+)
+{
+#if FF_LFN_UNICODE == 1	/* UTF-16 output */
+	WCHAR hs, wc;
+
+	hs = (WCHAR)(chr >> 16);
+	wc = (WCHAR)chr;
+	if (hs == 0) {	/* Single encoding unit? */
+		if (szb < 1 || IsSurrogate(wc)) return 0;	/* Buffer overflow or wrong code? */
+		*buf = wc;
+		return 1;
+	}
+	if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0;	/* Buffer overflow or wrong surrogate? */
+	*buf++ = hs;
+	*buf++ = wc;
+	return 2;
+
+#elif FF_LFN_UNICODE == 2	/* UTF-8 output */
+	DWORD hc;
+
+	if (chr < 0x80) {	/* Single byte code? */
+		if (szb < 1) return 0;	/* Buffer overflow? */
+		*buf = (TCHAR)chr;
+		return 1;
+	}
+	if (chr < 0x800) {	/* 2-byte sequence? */
+		if (szb < 2) return 0;	/* Buffer overflow? */
+		*buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+		return 2;
+	}
+	if (chr < 0x10000) {	/* 3-byte sequence? */
+		if (szb < 3 || IsSurrogate(chr)) return 0;	/* Buffer overflow or wrong code? */
+		*buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+		return 3;
+	}
+	/* 4-byte sequence */
+	if (szb < 4) return 0;	/* Buffer overflow? */
+	hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6;	/* Get high 10 bits */
+	chr = (chr & 0xFFFF) - 0xDC00;					/* Get low 10 bits */
+	if (hc >= 0x100000 || chr >= 0x400) return 0;	/* Wrong surrogate? */
+	chr = (hc | chr) + 0x10000;
+	*buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07));
+	*buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F));
+	*buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+	*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+	return 4;
+
+#elif FF_LFN_UNICODE == 3	/* UTF-32 output */
+	DWORD hc;
+
+	if (szb < 1) return 0;	/* Buffer overflow? */
+	if (chr >= 0x10000) {	/* Out of BMP? */
+		hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6;	/* Get high 10 bits */
+		chr = (chr & 0xFFFF) - 0xDC00;					/* Get low 10 bits */
+		if (hc >= 0x100000 || chr >= 0x400) return 0;	/* Wrong surrogate? */
+		chr = (hc | chr) + 0x10000;
+	}
+	*buf++ = (TCHAR)chr;
+	return 1;
+
+#else						/* ANSI/OEM output */
+	WCHAR wc;
+
+	wc = ff_uni2oem(chr, CODEPAGE);
+	if (wc >= 0x100) {	/* Is this a DBC? */
+		if (szb < 2) return 0;
+		*buf++ = (char)(wc >> 8);	/* Store DBC 1st byte */
+		*buf++ = (TCHAR)wc;			/* Store DBC 2nd byte */
+		return 2;
+	}
+	if (wc == 0 || szb < 1) return 0;	/* Invalid char or buffer overflow? */
+	*buf++ = (TCHAR)wc;					/* Store the character */
+	return 1;
+#endif
+}
+#endif	/* FF_USE_LFN */
+
+
+#if FF_FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+
+static int lock_volume (	/* 1:Ok, 0:timeout */
+	FATFS* fs,				/* Filesystem object to lock */
+	int syslock				/* System lock required */
+)
+{
+	int rv;
+
+
+#if FF_FS_LOCK
+	rv = ff_mutex_take(fs->ldrv);	/* Lock the volume */
+	if (rv && syslock) {			/* System lock reqiered? */
+		rv = ff_mutex_take(FF_VOLUMES);	/* Lock the system */
+		if (rv) {
+			SysLockVolume = fs->ldrv;
+			SysLock = 2;				/* System lock succeeded */
+		} else {
+			ff_mutex_give(fs->ldrv);	/* Failed system lock */
+		}
+	}
+#else
+	rv = syslock ? ff_mutex_take(fs->ldrv) : ff_mutex_take(fs->ldrv);	/* Lock the volume (this is to prevent compiler warning) */
+#endif
+	return rv;
+}
+
+
+static void unlock_volume (
+	FATFS* fs,		/* Filesystem object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+#if FF_FS_LOCK
+		if (SysLock == 2 && SysLockVolume == fs->ldrv) {	/* Unlock system if it has been locked by this task */
+			SysLock = 1;
+			ff_mutex_give(FF_VOLUMES);
+		}
+#endif
+		ff_mutex_give(fs->ldrv);	/* Unlock the volume */
+	}
+}
+
+#endif
+
+
+
+#if FF_FS_LOCK
+/*-----------------------------------------------------------------------*/
+/* File shareing control functions                                       */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT chk_share (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */
+)
+{
+	UINT i, be;
+
+	/* Search open object table for the object */
+	be = 0;
+	for (i = 0; i < FF_FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matches with an open object */
+				Files[i].clu == dp->obj.sclust &&
+				Files[i].ofs == dp->dptr) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == FF_FS_LOCK) {	/* The object has not been opened */
+		return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK;	/* Is there a blank entry for new object? */
+	}
+
+	/* The object was opened. Reject any open against writing file and all write mode open */
+	return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static int enq_share (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;	/* Find a free entry */
+	return (i == FF_FS_LOCK) ? 0 : 1;
+}
+
+
+static UINT inc_share (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < FF_FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->obj.fs
+		 && Files[i].clu == dp->obj.sclust
+		 && Files[i].ofs == dp->dptr) break;
+	}
+
+	if (i == FF_FS_LOCK) {			/* Not opened. Register it as new. */
+		for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;	/* Find a free entry */
+		if (i == FF_FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->obj.fs;
+		Files[i].clu = dp->obj.sclust;
+		Files[i].ofs = dp->dptr;
+		Files[i].ctr = 0;
+	}
+
+	if (acc >= 1 && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;	/* Index number origin from 1 */
+}
+
+
+static FRESULT dec_share (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	UINT n;
+	FRESULT res;
+
+
+	if (--i < FF_FS_LOCK) {	/* Index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;	/* If write mode open, delete the object semaphore */
+		if (n > 0) n--;			/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (n == 0) {			/* Delete the object semaphore if open count becomes zero */
+			Files[i].fs = 0;	/* Free the entry <<<If this memory write operation is not in atomic, FF_FS_REENTRANT == 1 and FF_VOLUMES > 1, there is a potential error in this process >>> */
+		}
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;		/* Invalid index number */
+	}
+	return res;
+}
+
+
+static void clear_share (	/* Clear all lock entries of the volume */
+	FATFS* fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < FF_FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+
+#endif	/* FF_FS_LOCK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the filesystem object                */
+/*-----------------------------------------------------------------------*/
+#if !FF_FS_READONLY
+static FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs			/* Filesystem object */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Is the disk access window dirty? */
+		if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) {	/* Write it back into the volume */
+			fs->wflag = 0;	/* Clear window dirty flag */
+			if (fs->winsect - fs->fatbase < fs->fsize) {	/* Is it in the 1st FAT? */
+				if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1);	/* Reflect it to 2nd FAT if needed */
+			}
+		} else {
+			res = FR_DISK_ERR;
+		}
+	}
+	return res;
+}
+#endif
+
+
+static FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs,		/* Filesystem object */
+	LBA_t sect		/* Sector LBA to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sect != fs->winsect) {	/* Window offset changed? */
+#if !FF_FS_READONLY
+		res = sync_window(fs);		/* Flush the window */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) {
+				sect = (LBA_t)0 - 1;	/* Invalidate window if read data is not valid */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sect;
+		}
+	}
+	return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize filesystem and data on the storage                        */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT sync_fs (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs		/* Filesystem object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {	/* FAT32: Update FSInfo sector if needed */
+			/* Create FSInfo structure */
+			memset(fs->win, 0, sizeof fs->win);
+			st_word(fs->win + BS_55AA, 0xAA55);					/* Boot signature */
+			st_dword(fs->win + FSI_LeadSig, 0x41615252);		/* Leading signature */
+			st_dword(fs->win + FSI_StrucSig, 0x61417272);		/* Structure signature */
+			st_dword(fs->win + FSI_Free_Count, fs->free_clst);	/* Number of free clusters */
+			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);	/* Last allocated culuster */
+			fs->winsect = fs->volbase + 1;						/* Write it into the FSInfo sector (Next to VBR) */
+			disk_write(fs->pdrv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the lower layer */
+		if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get physical sector number from cluster number                        */
+/*-----------------------------------------------------------------------*/
+
+static LBA_t clst2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* Filesystem object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;		/* Cluster number is origin from 2 */
+	if (clst >= fs->n_fatent - 2) return 0;		/* Is it invalid cluster number? */
+	return fs->database + (LBA_t)fs->csize * clst;	/* Start sector number of the cluster */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of an FAT entry                               */
+/*-----------------------------------------------------------------------*/
+
+static DWORD get_fat (		/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+	FFOBJID* obj,	/* Corresponding object */
+	DWORD clst		/* Cluster number to get the value */
+)
+{
+	UINT wc, bc;
+	DWORD val;
+	FATFS *fs = obj->fs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];		/* Get 1st byte of the entry */
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;	/* Merge 2nd byte of the entry */
+			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);	/* Adjust bit position */
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			val = ld_word(fs->win + clst * 2 % SS(fs));		/* Simple WORD array */
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;	/* Simple DWORD array but mask out upper 4 bits */
+			break;
+#if FF_FS_EXFAT
+		case FS_EXFAT :
+			if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) {	/* Object except root dir must have valid data length */
+				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+				DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize);	/* Number of clusters - 1 */
+
+				if (obj->stat == 2 && cofs <= clen) {	/* Is it a contiguous chain? */
+					val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* No data on the FAT, generate the value */
+					break;
+				}
+				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+					val = clst + 1; 	/* Generate the value */
+					break;
+				}
+				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+						val = 0x7FFFFFFF;	/* Generate EOC */
+					} else {
+						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+					}
+					break;
+				}
+			}
+			val = 1;	/* Internal error */
+			break;
+#endif
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of an FAT entry                             */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* Corresponding filesystem object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res = FR_INT_ERR;
+
+
+	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+		switch (fs->fs_type) {
+		case FS_FAT12:
+			bc = (UINT)clst; bc += bc / 2;	/* bc: byte offset of the entry */
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc++ % SS(fs);
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;	/* Update 1st byte */
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc % SS(fs);
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));	/* Update 2nd byte */
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16:
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);	/* Simple WORD array */
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32:
+#if FF_FS_EXFAT
+		case FS_EXFAT:
+#endif
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+			}
+			st_dword(fs->win + clst * 4 % SS(fs), val);
+			fs->wflag = 1;
+			break;
+		}
+	}
+	return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_FS_EXFAT && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap                            */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+	FATFS* fs,	/* Filesystem object */
+	DWORD clst,	/* Cluster number to scan from */
+	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+)
+{
+	BYTE bm, bv;
+	UINT i;
+	DWORD val, scl, ctr;
+
+
+	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+	if (clst >= fs->n_fatent - 2) clst = 0;
+	scl = val = clst; ctr = 0;
+	for (;;) {
+		if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;
+		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+		do {
+			do {
+				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+					val = 0; bm = 0; i = SS(fs);
+				}
+				if (bv == 0) {	/* Is it a free cluster? */
+					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+				} else {
+					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+				}
+				if (val == clst) return 0;	/* All cluster scanned? */
+			} while (bm != 0);
+			bm = 1;
+		} while (++i < SS(fs));
+	}
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static FRESULT change_bitmap (
+	FATFS* fs,	/* Filesystem object */
+	DWORD clst,	/* Cluster number to change from */
+	DWORD ncl,	/* Number of clusters to be changed */
+	int bv		/* bit value to be set (0 or 1) */
+)
+{
+	BYTE bm;
+	UINT i;
+	LBA_t sect;
+
+
+	clst -= 2;	/* The first bit corresponds to cluster #2 */
+	sect = fs->bitbase + clst / 8 / SS(fs);	/* Sector address */
+	i = clst / 8 % SS(fs);					/* Byte offset in the sector */
+	bm = 1 << (clst % 8);					/* Bit mask in the byte */
+	for (;;) {
+		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+		do {
+			do {
+				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+				fs->win[i] ^= bm;	/* Flip the bit */
+				fs->wflag = 1;
+				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+			} while (bm <<= 1);		/* Next bit */
+			bm = 1;
+		} while (++i < SS(fs));		/* Next byte */
+		i = 0;
+	}
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain    */
+/*---------------------------------------------*/
+
+static FRESULT fill_first_frag (
+	FFOBJID* obj	/* Pointer to the corresponding object */
+)
+{
+	FRESULT res;
+	DWORD cl, n;
+
+
+	if (obj->stat == 3) {	/* Has the object been changed 'fragmented' in this session? */
+		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+			res = put_fat(obj->fs, cl, cl + 1);
+			if (res != FR_OK) return res;
+		}
+		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+	}
+	return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain     */
+/*---------------------------------------------*/
+
+static FRESULT fill_last_frag (
+	FFOBJID* obj,	/* Pointer to the corresponding object */
+	DWORD lcl,		/* Last cluster of the fragment */
+	DWORD term		/* Value to set the last FAT entry */
+)
+{
+	FRESULT res;
+
+
+	while (obj->n_frag > 0) {	/* Create the chain of last fragment */
+		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+		if (res != FR_OK) return res;
+		obj->n_frag--;
+	}
+	return FR_OK;
+}
+
+#endif	/* FF_FS_EXFAT && !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	FFOBJID* obj,		/* Corresponding object */
+	DWORD clst,			/* Cluster to remove a chain from */
+	DWORD pclst			/* Previous cluster of clst (0 if entire chain) */
+)
+{
+	FRESULT res = FR_OK;
+	DWORD nxt;
+	FATFS *fs = obj->fs;
+#if FF_FS_EXFAT || FF_USE_TRIM
+	DWORD scl = clst, ecl = clst;
+#endif
+#if FF_USE_TRIM
+	LBA_t rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+
+	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+	if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+		res = put_fat(fs, pclst, 0xFFFFFFFF);
+		if (res != FR_OK) return res;
+	}
+
+	/* Remove the chain */
+	do {
+		nxt = get_fat(obj, clst);			/* Get cluster status */
+		if (nxt == 0) break;				/* Empty cluster? */
+		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+		if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+			if (res != FR_OK) return res;
+		}
+		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+			fs->free_clst++;
+			fs->fsi_flag |= 1;
+		}
+#if FF_FS_EXFAT || FF_USE_TRIM
+		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+			ecl = nxt;
+		} else {				/* End of contiguous cluster block */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap */
+				if (res != FR_OK) return res;
+			}
+#endif
+#if FF_USE_TRIM
+			rt[0] = clst2sect(fs, scl);					/* Start of data area to be freed */
+			rt[1] = clst2sect(fs, ecl) + fs->csize - 1;	/* End of data area to be freed */
+			disk_ioctl(fs->pdrv, CTRL_TRIM, rt);		/* Inform storage device that the data in the block may be erased */
+#endif
+			scl = ecl = nxt;
+		}
+#endif
+		clst = nxt;					/* Next cluster */
+	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+
+#if FF_FS_EXFAT
+	/* Some post processes for chain status */
+	if (fs->fs_type == FS_EXFAT) {
+		if (pclst == 0) {	/* Has the entire chain been removed? */
+			obj->stat = 0;		/* Change the chain status 'initial' */
+		} else {
+			if (obj->stat == 0) {	/* Is it a fragmented chain from the beginning of this session? */
+				clst = obj->sclust;		/* Follow the chain to check if it gets contiguous */
+				while (clst != pclst) {
+					nxt = get_fat(obj, clst);
+					if (nxt < 2) return FR_INT_ERR;
+					if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;
+					if (nxt != clst + 1) break;	/* Not contiguous? */
+					clst++;
+				}
+				if (clst == pclst) {	/* Has the chain got contiguous again? */
+					obj->stat = 2;		/* Change the chain status 'contiguous' */
+				}
+			} else {
+				if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Was the chain fragmented in this session and got contiguous again? */
+					obj->stat = 2;	/* Change the chain status 'contiguous' */
+				}
+			}
+		}
+	}
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain                  */
+/*-----------------------------------------------------------------------*/
+
+static DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	FFOBJID* obj,		/* Corresponding object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+	FATFS *fs = obj->fs;
+
+
+	if (clst == 0) {	/* Create a new chain */
+		scl = fs->last_clst;				/* Suggested cluster to start to find */
+		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+	}
+	else {				/* Stretch a chain */
+		cs = get_fat(obj, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;				/* Test for insanity */
+		if (cs == 0xFFFFFFFF) return cs;	/* Test for disk error */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;							/* Cluster to start to find */
+	}
+	if (fs->free_clst == 0) return 0;		/* No free cluster */
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+		if (res == FR_INT_ERR) return 1;
+		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+		if (clst == 0) {							/* Is it a new chain? */
+			obj->stat = 2;							/* Set status 'contiguous' */
+		} else {									/* It is a stretched chain */
+			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+				obj->stat = 3;						/* Change status 'just fragmented' */
+			}
+		}
+		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+			} else {				/* New fragment */
+				if (obj->n_frag == 0) obj->n_frag = 1;
+				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one */
+				if (res == FR_OK) obj->n_frag = 1;
+			}
+		}
+	} else
+#endif
+	{	/* On the FAT/FAT32 volume */
+		ncl = 0;
+		if (scl == clst) {						/* Stretching an existing chain? */
+			ncl = scl + 1;						/* Test if next cluster is free */
+			if (ncl >= fs->n_fatent) ncl = 2;
+			cs = get_fat(obj, ncl);				/* Get next cluster status */
+			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* Test for error */
+			if (cs != 0) {						/* Not free? */
+				cs = fs->last_clst;				/* Start at suggested cluster if it is valid */
+				if (cs >= 2 && cs < fs->n_fatent) scl = cs;
+				ncl = 0;
+			}
+		}
+		if (ncl == 0) {	/* The new cluster cannot be contiguous and find another fragment */
+			ncl = scl;	/* Start cluster */
+			for (;;) {
+				ncl++;							/* Next cluster */
+				if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+					ncl = 2;
+					if (ncl > scl) return 0;	/* No free cluster found? */
+				}
+				cs = get_fat(obj, ncl);			/* Get the cluster status */
+				if (cs == 0) break;				/* Found a free cluster? */
+				if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* Test for error */
+				if (ncl == scl) return 0;		/* No free cluster found? */
+			}
+		}
+		res = put_fat(fs, ncl, 0xFFFFFFFF);		/* Mark the new cluster 'EOC' */
+		if (res == FR_OK && clst != 0) {
+			res = put_fat(fs, clst, ncl);		/* Link it from the previous one if needed */
+		}
+	}
+
+	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+		fs->last_clst = ncl;
+		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+		fs->fsi_flag |= 1;
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+	}
+
+	return ncl;		/* Return new cluster number or error status */
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+static DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl;
+	DWORD *tbl;
+	FATFS *fs = fp->obj.fs;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (ncl == 0) return 0;	/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+
+#endif	/* FF_USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Fill a cluster with zeros                        */
+/*-----------------------------------------------------------------------*/
+
+#if !FF_FS_READONLY
+static FRESULT dir_clear (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS *fs,		/* Filesystem object */
+	DWORD clst		/* Directory table to clear */
+)
+{
+	LBA_t sect;
+	UINT n, szb;
+	BYTE *ibuf;
+
+
+	if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+	sect = clst2sect(fs, clst);		/* Top of the cluster */
+	fs->winsect = sect;				/* Set window to top of the cluster */
+	memset(fs->win, 0, sizeof fs->win);	/* Clear window buffer */
+#if FF_USE_LFN == 3		/* Quick table clear by using multi-secter write */
+	/* Allocate a temporary buffer */
+	for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ;
+	if (szb > SS(fs)) {		/* Buffer allocated? */
+		memset(ibuf, 0, szb);
+		szb /= SS(fs);		/* Bytes -> Sectors */
+		for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ;	/* Fill the cluster with 0 */
+		ff_memfree(ibuf);
+	} else
+#endif
+	{
+		ibuf = fs->win; szb = 1;	/* Use window buffer (many single-sector writes may take a time) */
+		for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ;	/* Fill the cluster with 0 */
+	}
+	return (n == fs->csize) ? FR_OK : FR_DISK_ERR;
+}
+#endif	/* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	DWORD ofs		/* Offset of directory table */
+)
+{
+	DWORD csz, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) {	/* Check range of offset and alignment */
+		return FR_INT_ERR;
+	}
+	dp->dptr = ofs;				/* Set current offset */
+	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+		clst = (DWORD)fs->dirbase;
+		if (FF_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+	}
+
+	if (clst == 0) {	/* Static table (root-directory on the FAT volume) */
+		if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR;	/* Is index out of range? */
+		dp->sect = fs->dirbase;
+
+	} else {			/* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */
+		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+		while (ofs >= csz) {				/* Follow cluster chain */
+			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal error */
+			ofs -= csz;
+		}
+		dp->sect = clst2sect(fs, clst);
+	}
+	dp->clust = clst;					/* Current cluster# */
+	if (dp->sect == 0) return FR_INT_ERR;
+	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,				/* Pointer to the directory object */
+	int stretch				/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD ofs, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	ofs = dp->dptr + SZDIRE;	/* Next entry */
+	if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0;	/* Disable it if the offset reached the max value */
+	if (dp->sect == 0) return FR_NO_FILE;	/* Report EOT if it has been disabled */
+
+	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+		dp->sect++;				/* Next sector */
+
+		if (dp->clust == 0) {	/* Static table */
+			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+				dp->sect = 0; return FR_NO_FILE;
+			}
+		}
+		else {					/* Dynamic table */
+			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(&dp->obj, dp->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;			/* Internal error */
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+				if (clst >= fs->n_fatent) {					/* It reached end of dynamic table */
+#if !FF_FS_READONLY
+					if (!stretch) {								/* If no stretch, report EOT */
+						dp->sect = 0; return FR_NO_FILE;
+					}
+					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+					if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR;	/* Clean up the stretched table */
+					if (FF_FS_EXFAT) dp->obj.stat |= 4;			/* exFAT: The directory has been stretched */
+#else
+					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+#endif
+				}
+				dp->clust = clst;		/* Initialize data for new cluster */
+				dp->sect = clst2sect(fs, clst);
+			}
+		}
+	}
+	dp->dptr = ofs;						/* Current entry */
+	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries             */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,				/* Pointer to the directory object */
+	UINT n_ent				/* Number of contiguous entries to allocate */
+)
+{
+	FRESULT res;
+	UINT n;
+	FATFS *fs = dp->obj.fs;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+#if FF_FS_EXFAT
+			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {	/* Is the entry free? */
+#else
+			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {	/* Is the entry free? */
+#endif
+				if (++n == n_ent) break;	/* Is a block of contiguous free entries found? */
+			} else {
+				n = 0;				/* Not a free entry, restart to search */
+			}
+			res = dir_next(dp, 1);	/* Next entry with table stretch enabled */
+		} while (res == FR_OK);
+	}
+
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+
+#endif	/* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number             */
+/*-----------------------------------------------------------------------*/
+
+static DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,			/* Pointer to the fs object */
+	const BYTE* dir		/* Pointer to the key entry */
+)
+{
+	DWORD cl;
+
+	cl = ld_word(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32) {
+		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+	}
+
+	return cl;
+}
+
+
+#if !FF_FS_READONLY
+static void st_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir,	/* Pointer to the key entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	st_word(dir + DIR_FstClusLO, (WORD)cl);
+	if (fs->fs_type == FS_FAT32) {
+		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+	}
+}
+#endif
+
+
+
+#if FF_USE_LFN
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+
+static int cmp_lfn (		/* 1:matched, 0:not matched */
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc != 0) {
+			if (i >= FF_MAX_LFN + 1 || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+				return 0;					/* Not matched */
+			}
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different length */
+
+	return 1;		/* The part of LFN matched */
+}
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+
+static int pick_lfn (	/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc != 0) {
+			if (i >= FF_MAX_LFN + 1) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF && wc != 0) {	/* Put terminator if it is the last LFN part and not terminated */
+		if (i >= FF_MAX_LFN + 1) return 0;	/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+
+static void put_lfn (
+	const WCHAR* lfn,	/* Pointer to the LFN */
+	BYTE* dir,			/* Pointer to the LFN entry to be created */
+	BYTE ord,			/* LFN order (1-20) */
+	BYTE sum			/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	st_word(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+		st_word(dir + LfnOfs[s], wc);		/* Put it */
+		if (wc == 0) wc = 0xFFFF;			/* Padding characters for following items */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif	/* !FF_FS_READONLY */
+#endif	/* FF_USE_LFN */
+
+
+
+#if FF_USE_LFN && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN                                        */
+/*-----------------------------------------------------------------------*/
+
+static void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN in directory form */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sreg;
+
+
+	memcpy(dst, src, 11);	/* Prepare the SFN to be modified */
+
+	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number */
+		sreg = seq;
+		while (*lfn) {	/* Create a CRC as hash value */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sreg = (sreg << 1) + (wc & 1);
+				wc >>= 1;
+				if (sreg & 0x10000) sreg ^= 0x11021;
+			}
+		}
+		seq = (UINT)sreg;
+	}
+
+	/* Make suffix (~ + hexadecimal) */
+	i = 7;
+	do {
+		c = (BYTE)((seq % 16) + '0'); seq /= 16;
+		if (c > '9') c += 7;
+		ns[i--] = c;
+	} while (i && seq);
+	ns[i] = '~';
+
+	/* Append the suffix to the SFN body */
+	for (j = 0; j < i && dst[j] != ' '; j++) {	/* Find the offset to append */
+		if (dbc_1st(dst[j])) {	/* To avoid DBC break up */
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {	/* Append the suffix */
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif	/* FF_USE_LFN && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LFN
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry                           */
+/*-----------------------------------------------------------------------*/
+
+static BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do {
+		sum = (sum >> 1) + (sum << 7) + *dir++;
+	} while (--n);
+	return sum;
+}
+
+#endif	/* FF_USE_LFN */
+
+
+
+#if FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum                                                       */
+/*-----------------------------------------------------------------------*/
+
+static WORD xdir_sum (	/* Get checksum of the directoly entry block */
+	const BYTE* dir		/* Directory entry block to be calculated */
+)
+{
+	UINT i, szblk;
+	WORD sum;
+
+
+	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;	/* Number of bytes of the entry block */
+	for (i = sum = 0; i < szblk; i++) {
+		if (i == XDIR_SetSum) {	/* Skip 2-byte sum field */
+			i++;
+		} else {
+			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+		}
+	}
+	return sum;
+}
+
+
+
+static WORD xname_sum (	/* Get check sum (to be used as hash) of the file name */
+	const WCHAR* name	/* File name to be calculated */
+)
+{
+	WCHAR chr;
+	WORD sum = 0;
+
+
+	while ((chr = *name++) != 0) {
+		chr = (WCHAR)ff_wtoupper(chr);		/* File name needs to be up-case converted */
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+	}
+	return sum;
+}
+
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+static DWORD xsum32 (	/* Returns 32-bit checksum */
+	BYTE  dat,			/* Byte to be calculated (byte-by-byte processing) */
+	DWORD sum			/* Previous sum value */
+)
+{
+	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+	return sum;
+}
+#endif
+
+
+
+/*------------------------------------*/
+/* exFAT: Get a directory entry block */
+/*------------------------------------*/
+
+static FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+	DIR* dp					/* Reading directory object pointing top of the entry block to load */
+)
+{
+	FRESULT res;
+	UINT i, sz_ent;
+	BYTE *dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory directory entry block 85+C0+C1s */
+
+
+	/* Load file directory entry */
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR;	/* Invalid order */
+	memcpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE);
+	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+	/* Load stream extension entry */
+	res = dir_next(dp, 0);
+	if (res == FR_NO_FILE) res = FR_INT_ERR;	/* It cannot be */
+	if (res != FR_OK) return res;
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR;	/* Invalid order */
+	memcpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE);
+	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+	/* Load file name entries */
+	i = 2 * SZDIRE;	/* Name offset to load */
+	do {
+		res = dir_next(dp, 0);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;	/* It cannot be */
+		if (res != FR_OK) return res;
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) return res;
+		if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR;	/* Invalid order */
+		if (i < MAXDIRB(FF_MAX_LFN)) memcpy(dirb + i, dp->dir, SZDIRE);
+	} while ((i += SZDIRE) < sz_ent);
+
+	/* Sanity check (do it for only accessible object) */
+	if (i <= MAXDIRB(FF_MAX_LFN)) {
+		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+	}
+	return FR_OK;
+}
+
+
+/*------------------------------------------------------------------*/
+/* exFAT: Initialize object allocation info with loaded entry block */
+/*------------------------------------------------------------------*/
+
+static void init_alloc_info (
+	FATFS* fs,		/* Filesystem object */
+	FFOBJID* obj	/* Object allocation information to be initialized */
+)
+{
+	obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Start cluster */
+	obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);	/* Size */
+	obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;				/* Allocation status */
+	obj->n_frag = 0;										/* No last fragment info */
+}
+
+
+
+#if !FF_FS_READONLY || FF_FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+
+static FRESULT load_obj_xdir (
+	DIR* dp,			/* Blank directory object to be used to access containing directory */
+	const FFOBJID* obj	/* Object with its containing directory information */
+)
+{
+	FRESULT res;
+
+	/* Open object containing directory */
+	dp->obj.fs = obj->fs;
+	dp->obj.sclust = obj->c_scl;
+	dp->obj.stat = (BYTE)obj->c_size;
+	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+	dp->obj.n_frag = 0;
+	dp->blk_ofs = obj->c_ofs;
+
+	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+	if (res == FR_OK) {
+		res = load_xdir(dp);		/* Load the object's entry block */
+	}
+	return res;
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*----------------------------------------*/
+/* exFAT: Store the directory entry block */
+/*----------------------------------------*/
+
+static FRESULT store_xdir (
+	DIR* dp				/* Pointer to the directory object */
+)
+{
+	FRESULT res;
+	UINT nent;
+	BYTE *dirb = dp->obj.fs->dirbuf;	/* Pointer to the directory entry block 85+C0+C1s */
+
+	/* Create set sum */
+	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+	nent = dirb[XDIR_NumSec] + 1;
+
+	/* Store the directory entry block to the directory */
+	res = dir_sdi(dp, dp->blk_ofs);
+	while (res == FR_OK) {
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) break;
+		memcpy(dp->dir, dirb, SZDIRE);
+		dp->obj.fs->wflag = 1;
+		if (--nent == 0) break;
+		dirb += SZDIRE;
+		res = dir_next(dp, 0);
+	}
+	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory entry block */
+/*-------------------------------------------*/
+
+static void create_xdir (
+	BYTE* dirb,			/* Pointer to the directory entry block buffer */
+	const WCHAR* lfn	/* Pointer to the object name */
+)
+{
+	UINT i;
+	BYTE nc1, nlen;
+	WCHAR wc;
+
+
+	/* Create file-directory and stream-extension entry */
+	memset(dirb, 0, 2 * SZDIRE);
+	dirb[0 * SZDIRE + XDIR_Type] = ET_FILEDIR;
+	dirb[1 * SZDIRE + XDIR_Type] = ET_STREAM;
+
+	/* Create file-name entries */
+	i = SZDIRE * 2;	/* Top of file_name entries */
+	nlen = nc1 = 0; wc = 1;
+	do {
+		dirb[i++] = ET_FILENAME; dirb[i++] = 0;
+		do {	/* Fill name field */
+			if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++;	/* Get a character if exist */
+			st_word(dirb + i, wc); 	/* Store it */
+			i += 2;
+		} while (i % SZDIRE != 0);
+		nc1++;
+	} while (lfn[nlen]);	/* Fill next entry if any char follows */
+
+	dirb[XDIR_NumName] = nlen;		/* Set name length */
+	dirb[XDIR_NumSec] = 1 + nc1;	/* Set secondary count (C0 + C1s) */
+	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+}
+
+#endif	/* !FF_FS_READONLY */
+#endif	/* FF_FS_EXFAT */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+
+#define DIR_READ_FILE(dp) dir_read(dp, 0)
+#define DIR_READ_LABEL(dp) dir_read(dp, 1)
+
+static FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res = FR_NO_FILE;
+	FATFS *fs = dp->obj.fs;
+	BYTE attr, b;
+#if FF_USE_LFN
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	while (dp->sect) {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		b = dp->dir[DIR_Name];	/* Test for the entry type */
+		if (b == 0) {
+			res = FR_NO_FILE; break; /* Reached to end of the directory */
+		}
+#if FF_FS_EXFAT
+		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+			if (FF_USE_LABEL && vol) {
+				if (b == ET_VLABEL) break;	/* Volume label entry? */
+			} else {
+				if (b == ET_FILEDIR) {		/* Start of the file entry block? */
+					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+					res = load_xdir(dp);	/* Load the entry block */
+					if (res == FR_OK) {
+						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+					}
+					break;
+				}
+			}
+		} else
+#endif
+		{	/* On the FAT/FAT32 volume */
+			dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+#if FF_USE_LFN		/* LFN configuration */
+			if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+				ord = 0xFF;
+			} else {
+				if (attr == AM_LFN) {	/* An LFN entry is found */
+					if (b & LLEF) {		/* Is it start of an LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						b &= (BYTE)~LLEF; ord = b;
+						dp->blk_ofs = dp->dptr;
+					}
+					/* Check LFN validity and capture it */
+					ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				} else {				/* An SFN entry is found */
+					if (ord != 0 || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+						dp->blk_ofs = 0xFFFFFFFF;	/* It has no LFN. */
+					}
+					break;
+				}
+			}
+#else		/* Non LFN configuration */
+			if (b != DDEM && b != '.' && attr != AM_LFN && (int)((attr & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a valid entry? */
+				break;
+			}
+#endif
+		}
+		res = dir_next(dp, 0);		/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+	return res;
+}
+
+#endif	/* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp					/* Pointer to the directory object with the file name */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+	BYTE c;
+#if FF_USE_LFN
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		BYTE nc;
+		UINT di, ni;
+		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+
+		while ((res = DIR_READ_FILE(dp)) == FR_OK) {	/* Read an item */
+#if FF_MAX_LFN < 255
+			if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue;		/* Skip comparison if inaccessible object name */
+#endif
+			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched */
+			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compare the name */
+				if ((di % SZDIRE) == 0) di += 2;
+				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+			}
+			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+		}
+		return res;
+	}
+#endif
+	/* On the FAT/FAT32 volume */
+#if FF_USE_LFN
+	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if FF_USE_LFN		/* LFN configuration */
+		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (ord == 0 && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+		if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry? */
+#endif
+		res = dir_next(dp, 0);	/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp						/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN		/* LFN configuration */
+	UINT n, len, n_ent;
+	BYTE sn[12], sum;
+
+
+	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+	for (len = 0; fs->lfnbuf[len]; len++) ;	/* Get lfn length */
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		n_ent = (len + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+		res = dir_alloc(dp, n_ent);		/* Allocate directory entries */
+		if (res != FR_OK) return res;
+		dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1);	/* Set the allocated entry block offset */
+
+		if (dp->obj.stat & 4) {			/* Has the directory been stretched by new allocation? */
+			dp->obj.stat &= ~4;
+			res = fill_first_frag(&dp->obj);	/* Fill the first fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill the last fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			if (dp->obj.sclust != 0) {		/* Is it a sub-directory? */
+				DIR dj;
+
+				res = load_obj_xdir(&dj, &dp->obj);	/* Load the object status */
+				if (res != FR_OK) return res;
+				dp->obj.objsize += (DWORD)fs->csize * SS(fs);		/* Increase the directory size by cluster size */
+				st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);
+				st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+				fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;		/* Update the allocation status */
+				res = store_xdir(&dj);				/* Store the object status */
+				if (res != FR_OK) return res;
+			}
+		}
+
+		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+		return FR_OK;
+	}
+#endif
+	/* On the FAT/FAT32 volume */
+	memcpy(sn, dp->fn, 12);
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		dp->fn[NSFLAG] = sn[NSFLAG];
+	}
+
+	/* Create an SFN with/without LFNs. */
+	n_ent = (sn[NSFLAG] & NS_LFN) ? (len + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+	res = dir_alloc(dp, n_ent);		/* Allocate entries */
+	if (res == FR_OK && --n_ent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->dptr - n_ent * SZDIRE);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(fs, dp->sect);
+				if (res != FR_OK) break;
+				put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum);
+				fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --n_ent);
+		}
+	}
+
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+
+#endif
+
+	/* Set SFN entry */
+	if (res == FR_OK) {
+		res = move_window(fs, dp->sect);
+		if (res == FR_OK) {
+			memset(dp->dir, 0, SZDIRE);	/* Clean the entry */
+			memcpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+#if FF_USE_LFN
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp					/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN		/* LFN configuration */
+	DWORD last = dp->dptr;
+
+	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry block if LFN is exist */
+	if (res == FR_OK) {
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+			if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+				dp->dir[XDIR_Type] &= 0x7F;	/* Clear the entry InUse flag. */
+			} else {										/* On the FAT/FAT32 volume */
+				dp->dir[DIR_Name] = DDEM;	/* Mark the entry 'deleted'. */
+			}
+			fs->wflag = 1;
+			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been deleted. */
+			res = dir_next(dp, 0);	/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+#else			/* Non LFN configuration */
+
+	res = move_window(fs, dp->sect);
+	if (res == FR_OK) {
+		dp->dir[DIR_Name] = DDEM;	/* Mark the entry 'deleted'.*/
+		fs->wflag = 1;
+	}
+#endif
+
+	return res;
+}
+
+#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+
+static void get_fileinfo (
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno		/* Pointer to the file information to be filled */
+)
+{
+	UINT si, di;
+#if FF_USE_LFN
+	BYTE lcf;
+	WCHAR wc, hs;
+	FATFS *fs = dp->obj.fs;
+	UINT nw;
+#else
+	TCHAR c;
+#endif
+
+
+	fno->fname[0] = 0;			/* Invaidate file info */
+	if (dp->sect == 0) return;	/* Exit if read pointer has reached end of directory */
+
+#if FF_USE_LFN		/* LFN configuration */
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* exFAT volume */
+		UINT nc = 0;
+
+		si = SZDIRE * 2; di = 0;	/* 1st C1 entry in the entry block */
+		hs = 0;
+		while (nc < fs->dirbuf[XDIR_NumName]) {
+			if (si >= MAXDIRB(FF_MAX_LFN)) {	/* Truncated directory block? */
+				di = 0; break;
+			}
+			if ((si % SZDIRE) == 0) si += 2;	/* Skip entry type field */
+			wc = ld_word(fs->dirbuf + si); si += 2; nc++;	/* Get a character */
+			if (hs == 0 && IsSurrogate(wc)) {	/* Is it a surrogate? */
+				hs = wc; continue;				/* Get low surrogate */
+			}
+			nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di);	/* Store it in API encoding */
+			if (nw == 0) {						/* Buffer overflow or wrong char? */
+				di = 0; break;
+			}
+			di += nw;
+			hs = 0;
+		}
+		if (hs != 0) di = 0;					/* Broken surrogate pair? */
+		if (di == 0) fno->fname[di++] = '\?';	/* Inaccessible object name? */
+		fno->fname[di] = 0;						/* Terminate the name */
+		fno->altname[0] = 0;					/* exFAT does not support SFN */
+
+		fno->fattrib = fs->dirbuf[XDIR_Attr] & AM_MASKX;		/* Attribute */
+		fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(fs->dirbuf + XDIR_FileSize);	/* Size */
+		fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0);	/* Time */
+		fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2);	/* Date */
+		return;
+	} else
+#endif
+	{	/* FAT/FAT32 volume */
+		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+			si = di = 0;
+			hs = 0;
+			while (fs->lfnbuf[si] != 0) {
+				wc = fs->lfnbuf[si++];		/* Get an LFN character (UTF-16) */
+				if (hs == 0 && IsSurrogate(wc)) {	/* Is it a surrogate? */
+					hs = wc; continue;		/* Get low surrogate */
+				}
+				nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di);	/* Store it in API encoding */
+				if (nw == 0) {				/* Buffer overflow or wrong char? */
+					di = 0; break;
+				}
+				di += nw;
+				hs = 0;
+			}
+			if (hs != 0) di = 0;	/* Broken surrogate pair? */
+			fno->fname[di] = 0;		/* Terminate the LFN (null string means LFN is invalid) */
+		}
+	}
+
+	si = di = 0;
+	while (si < 11) {		/* Get SFN from SFN entry */
+		wc = dp->dir[si++];			/* Get a char */
+		if (wc == ' ') continue;	/* Skip padding spaces */
+		if (wc == RDDEM) wc = DDEM;	/* Restore replaced DDEM character */
+		if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.';	/* Insert a . if extension is exist */
+#if FF_LFN_UNICODE >= 1	/* Unicode output */
+		if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) {	/* Make a DBC if needed */
+			wc = wc << 8 | dp->dir[si++];
+		}
+		wc = ff_oem2uni(wc, CODEPAGE);		/* ANSI/OEM -> Unicode */
+		if (wc == 0) {				/* Wrong char in the current code page? */
+			di = 0; break;
+		}
+		nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di);	/* Store it in API encoding */
+		if (nw == 0) {				/* Buffer overflow? */
+			di = 0; break;
+		}
+		di += nw;
+#else					/* ANSI/OEM output */
+		fno->altname[di++] = (TCHAR)wc;	/* Store it without any conversion */
+#endif
+	}
+	fno->altname[di] = 0;	/* Terminate the SFN  (null string means SFN is invalid) */
+
+	if (fno->fname[0] == 0) {	/* If LFN is invalid, altname[] needs to be copied to fname[] */
+		if (di == 0) {	/* If LFN and SFN both are invalid, this object is inaccessible */
+			fno->fname[di++] = '\?';
+		} else {
+			for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) {	/* Copy altname[] to fname[] with case information */
+				wc = (WCHAR)fno->altname[si];
+				if (wc == '.') lcf = NS_EXT;
+				if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20;
+				fno->fname[di] = (TCHAR)wc;
+			}
+		}
+		fno->fname[di] = 0;	/* Terminate the LFN */
+		if (!dp->dir[DIR_NTres]) fno->altname[0] = 0;	/* Altname is not needed if neither LFN nor case info is exist. */
+	}
+
+#else	/* Non-LFN configuration */
+	si = di = 0;
+	while (si < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[si++];
+		if (c == ' ') continue;		/* Skip padding spaces */
+		if (c == RDDEM) c = DDEM;	/* Restore replaced DDEM character */
+		if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */
+		fno->fname[di++] = c;
+	}
+	fno->fname[di] = 0;		/* Terminate the SFN */
+#endif
+
+	fno->fattrib = dp->dir[DIR_Attr] & AM_MASK;			/* Attribute */
+	fno->fsize = ld_dword(dp->dir + DIR_FileSize);		/* Size */
+	fno->ftime = ld_word(dp->dir + DIR_ModTime + 0);	/* Time */
+	fno->fdate = ld_word(dp->dir + DIR_ModTime + 2);	/* Date */
+}
+
+#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
+
+
+
+#if FF_USE_FIND && FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+
+#define FIND_RECURS	4	/* Maximum number of wildcard terms in the pattern to limit recursion */
+
+
+static DWORD get_achar (	/* Get a character and advance ptr */
+	const TCHAR** ptr		/* Pointer to pointer to the ANSI/OEM or Unicode string */
+)
+{
+	DWORD chr;
+
+
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1	/* Unicode input */
+	chr = tchar2uni(ptr);
+	if (chr == 0xFFFFFFFF) chr = 0;		/* Wrong UTF encoding is recognized as end of the string */
+	chr = ff_wtoupper(chr);
+
+#else									/* ANSI/OEM input */
+	chr = (BYTE)*(*ptr)++;				/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;		/* To upper ASCII char */
+#if FF_CODE_PAGE == 0
+	if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#elif FF_CODE_PAGE < 900
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#endif
+#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900
+	if (dbc_1st((BYTE)chr)) {	/* Get DBC 2nd byte if needed */
+		chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0;
+	}
+#endif
+
+#endif
+	return chr;
+}
+
+
+static int pattern_match (	/* 0:mismatched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	UINT skip,			/* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */
+	UINT recur			/* Recursion count */
+)
+{
+	const TCHAR *pptr;
+	const TCHAR *nptr;
+	DWORD pchr, nchr;
+	UINT sk;
+
+
+	while ((skip & 0xFF) != 0) {		/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+		skip--;
+	}
+	if (*pat == 0 && skip) return 1;	/* Matched? (short circuit) */
+
+	do {
+		pptr = pat; nptr = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pptr == '\?' || *pptr == '*') {	/* Wildcard term? */
+				if (recur == 0) return 0;	/* Too many wildcard terms? */
+				sk = 0;
+				do {	/* Analyze the wildcard term */
+					if (*pptr++ == '\?') {
+						sk++;
+					} else {
+						sk |= 0x100;
+					}
+				} while (*pptr == '\?' || *pptr == '*');
+				if (pattern_match(pptr, nptr, sk, recur - 1)) return 1;	/* Test new branch (recursive call) */
+				nchr = *nptr; break;	/* Branch mismatched */
+			}
+			pchr = get_achar(&pptr);	/* Get a pattern char */
+			nchr = get_achar(&nptr);	/* Get a name char */
+			if (pchr != nchr) break;	/* Branch mismatched? */
+			if (pchr == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (skip && nchr);		/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+
+#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,					/* Pointer to the directory object */
+	const TCHAR** path			/* Pointer to pointer to the segment in the path string */
+)
+{
+#if FF_USE_LFN		/* LFN configuration */
+	BYTE b, cf;
+	WCHAR wc;
+	WCHAR *lfn;
+	const TCHAR* p;
+	DWORD uc;
+	UINT i, ni, si, di;
+
+
+	/* Create LFN into LFN working buffer */
+	p = *path; lfn = dp->obj.fs->lfnbuf; di = 0;
+	for (;;) {
+		uc = tchar2uni(&p);			/* Get a character */
+		if (uc == 0xFFFFFFFF) return FR_INVALID_NAME;		/* Invalid code or UTF decode error */
+		if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16);	/* Store high surrogate if needed */
+		wc = (WCHAR)uc;
+		if (wc < ' ' || IsSeparator(wc)) break;	/* Break if end of the path or a separator is found */
+		if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME;	/* Reject illegal characters for LFN */
+		if (di >= FF_MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+		lfn[di++] = wc;				/* Store the Unicode character */
+	}
+	if (wc < ' ') {				/* Stopped at end of the path? */
+		cf = NS_LAST;			/* Last segment */
+	} else {					/* Stopped at a separator */
+		while (IsSeparator(*p)) p++;	/* Skip duplicated separators if exist */
+		cf = 0;					/* Next segment may follow */
+		if (IsTerminator(*p)) cf = NS_LAST;	/* Ignore terminating separator */
+	}
+	*path = p;					/* Return pointer to the next segment */
+
+#if FF_FS_RPATH != 0
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++) {	/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		}
+		dp->fn[i] = cf | NS_DOT;	/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {					/* Snip off trailing spaces and dots if exist */
+		wc = lfn[di - 1];
+		if (wc != ' ' && wc != '.') break;
+		di--;
+	}
+	lfn[di] = 0;							/* LFN is created into the working buffer */
+	if (di == 0) return FR_INVALID_NAME;	/* Reject null name */
+
+	/* Create SFN in directory form */
+	for (si = 0; lfn[si] == ' '; si++) ;	/* Remove leading spaces */
+	if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN;	/* Is there any leading space or dot? */
+	while (di > 0 && lfn[di - 1] != '.') di--;	/* Find last dot (di<=si: no extension) */
+
+	memset(dp->fn, ' ', 11);
+	i = b = 0; ni = 8;
+	for (;;) {
+		wc = lfn[si++];					/* Get an LFN character */
+		if (wc == 0) break;				/* Break on end of the LFN */
+		if (wc == ' ' || (wc == '.' && si != di)) {	/* Remove embedded spaces and dots */
+			cf |= NS_LOSS | NS_LFN;
+			continue;
+		}
+
+		if (i >= ni || si == di) {		/* End of field? */
+			if (ni == 11) {				/* Name extension overflow? */
+				cf |= NS_LOSS | NS_LFN;
+				break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Name body overflow? */
+			if (si > di) break;						/* No name extension? */
+			si = di; i = 8; ni = 11; b <<= 2;		/* Enter name extension */
+			continue;
+		}
+
+		if (wc >= 0x80) {	/* Is this an extended character? */
+			cf |= NS_LFN;	/* LFN entry needs to be created */
+#if FF_CODE_PAGE == 0
+			if (ExCvt) {	/* In SBCS cfg */
+				wc = ff_uni2oem(wc, CODEPAGE);			/* Unicode ==> ANSI/OEM code */
+				if (wc & 0x80) wc = ExCvt[wc & 0x7F];	/* Convert extended character to upper (SBCS) */
+			} else {		/* In DBCS cfg */
+				wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE);	/* Unicode ==> Up-convert ==> ANSI/OEM code */
+			}
+#elif FF_CODE_PAGE < 900	/* In SBCS cfg */
+			wc = ff_uni2oem(wc, CODEPAGE);			/* Unicode ==> ANSI/OEM code */
+			if (wc & 0x80) wc = ExCvt[wc & 0x7F];	/* Convert extended character to upper (SBCS) */
+#else						/* In DBCS cfg */
+			wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE);	/* Unicode ==> Up-convert ==> ANSI/OEM code */
+#endif
+		}
+
+		if (wc >= 0x100) {				/* Is this a DBC? */
+			if (i >= ni - 1) {			/* Field overflow? */
+				cf |= NS_LOSS | NS_LFN;
+				i = ni; continue;		/* Next field */
+			}
+			dp->fn[i++] = (BYTE)(wc >> 8);	/* Put 1st byte */
+		} else {						/* SBC */
+			if (wc == 0 || strchr("+,;=[]", (int)wc)) {	/* Replace illegal characters for SFN */
+				wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(wc)) {		/* ASCII upper case? */
+					b |= 2;
+				}
+				if (IsLower(wc)) {		/* ASCII lower case? */
+					b |= 1; wc -= 0x20;
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)wc;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;				/* Shift capital flags if no extension */
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* LFN entry needs to be created if composite capitals */
+	if (!(cf & NS_LFN)) {				/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if (b & 0x01) cf |= NS_EXT;		/* NT flag (Extension has small capital letters only) */
+		if (b & 0x04) cf |= NS_BODY;	/* NT flag (Body has small capital letters only) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created into dp->fn[] */
+
+	return FR_OK;
+
+
+#else	/* FF_USE_LFN : Non-LFN configuration */
+	BYTE c, d;
+	BYTE *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	p = *path; sfn = dp->fn;
+	memset(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+#if FF_FS_RPATH != 0
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME;
+		*path = p + si;					/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];				/* Get a byte */
+		if (c <= ' ') break; 			/* Break if end of the path name */
+		if (IsSeparator(c)) {			/* Break if a separator is found */
+			while (IsSeparator(p[si])) si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (c == '.' || i >= ni) {		/* End of body or field overflow? */
+			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Field overflow or invalid dot? */
+			i = 8; ni = 11;				/* Enter file extension field */
+			continue;
+		}
+#if FF_CODE_PAGE == 0
+		if (ExCvt && c >= 0x80) {		/* Is SBC extended character? */
+			c = ExCvt[c & 0x7F];		/* To upper SBC extended character */
+		}
+#elif FF_CODE_PAGE < 900
+		if (c >= 0x80) {				/* Is SBC extended character? */
+			c = ExCvt[c & 0x7F];		/* To upper SBC extended character */
+		}
+#endif
+		if (dbc_1st(c)) {				/* Check if it is a DBC 1st byte */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+			if (IsLower(c)) c -= 0x20;	/* To upper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+	sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0;	/* Set last segment flag if end of the path */
+
+	return FR_OK;
+#endif /* FF_USE_LFN */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,					/* Directory object to return last directory and found object */
+	const TCHAR* path			/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE ns;
+	FATFS *fs = dp->obj.fs;
+
+
+#if FF_FS_RPATH != 0
+	if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) {	/* Without heading separator */
+		dp->obj.sclust = fs->cdir;			/* Start at the current directory */
+	} else
+#endif
+	{										/* With heading separator */
+		while (IsSeparator(*path)) path++;	/* Strip separators */
+		dp->obj.sclust = 0;					/* Start from the root directory */
+	}
+#if FF_FS_EXFAT
+	dp->obj.n_frag = 0;	/* Invalidate last fragment counter of the object */
+#if FF_FS_RPATH != 0
+	if (fs->fs_type == FS_EXFAT && dp->obj.sclust) {	/* exFAT: Retrieve the sub-directory's status */
+		DIR dj;
+
+		dp->obj.c_scl = fs->cdc_scl;
+		dp->obj.c_size = fs->cdc_size;
+		dp->obj.c_ofs = fs->cdc_ofs;
+		res = load_obj_xdir(&dj, &dp->obj);
+		if (res != FR_OK) return res;
+		dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+		dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+	}
+#endif
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		dp->fn[NSFLAG] = NS_NONAME;
+		res = dir_sdi(dp, 0);
+
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the segment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (FF_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						dp->fn[NSFLAG] = NS_NONAME;
+						res = FR_OK;
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;		/* Last segment matched. Function completed. */
+			/* Get into the sub-directory */
+			if (!(dp->obj.attr & AM_DIR)) {	/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* Save containing directory information for next dir */
+				dp->obj.c_scl = dp->obj.sclust;
+				dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+				dp->obj.c_ofs = dp->blk_ofs;
+				init_alloc_info(fs, &dp->obj);	/* Open next directory */
+			} else
+#endif
+			{
+				dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+			}
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static int get_ldnumber (	/* Returns logical drive number (-1:invalid drive number or null pointer) */
+	const TCHAR** path		/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp;
+	const TCHAR *tt;
+	TCHAR tc;
+	int i;
+	int vol = -1;
+#if FF_STR_VOLUME_ID		/* Find string volume ID */
+	const char *sp;
+	char c;
+#endif
+
+	tt = tp = *path;
+	if (!tp) return vol;	/* Invalid path name? */
+	do {					/* Find a colon in the path */
+		tc = *tt++;
+	} while (!IsTerminator(tc) && tc != ':');
+
+	if (tc == ':') {	/* DOS/Windows style volume ID? */
+		i = FF_VOLUMES;
+		if (IsDigit(*tp) && tp + 2 == tt) {	/* Is there a numeric volume ID + colon? */
+			i = (int)*tp - '0';	/* Get the LD number */
+		}
+#if FF_STR_VOLUME_ID == 1	/* Arbitrary string is enabled */
+		else {
+			i = 0;
+			do {
+				sp = VolumeStr[i]; tp = *path;	/* This string volume ID and path name */
+				do {	/* Compare the volume ID with path name */
+					c = *sp++; tc = *tp++;
+					if (IsLower(c)) c -= 0x20;
+					if (IsLower(tc)) tc -= 0x20;
+				} while (c && (TCHAR)c == tc);
+			} while ((c || tp != tt) && ++i < FF_VOLUMES);	/* Repeat for each id until pattern match */
+		}
+#endif
+		if (i < FF_VOLUMES) {	/* If a volume ID is found, get the drive number and strip it */
+			vol = i;		/* Drive number */
+			*path = tt;		/* Snip the drive prefix off */
+		}
+		return vol;
+	}
+#if FF_STR_VOLUME_ID == 2		/* Unix style volume ID is enabled */
+	if (*tp == '/') {			/* Is there a volume ID? */
+		while (*(tp + 1) == '/') tp++;	/* Skip duplicated separator */
+		i = 0;
+		do {
+			tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */
+			do {	/* Compare the volume ID with path name */
+				c = *sp++; tc = *(++tt);
+				if (IsLower(c)) c -= 0x20;
+				if (IsLower(tc)) tc -= 0x20;
+			} while (c && (TCHAR)c == tc);
+		} while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES);	/* Repeat for each ID until pattern match */
+		if (i < FF_VOLUMES) {	/* If a volume ID is found, get the drive number and strip it */
+			vol = i;		/* Drive number */
+			*path = tt;		/* Snip the drive prefix off */
+		}
+		return vol;
+	}
+#endif
+	/* No drive prefix is found */
+#if FF_FS_RPATH != 0
+	vol = CurrVol;	/* Default drive is current drive */
+#else
+	vol = 0;		/* Default drive is 0 */
+#endif
+	return vol;		/* Return the default drive */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* GPT support functions                                                 */
+/*-----------------------------------------------------------------------*/
+
+#if FF_LBA64
+
+/* Calculate CRC32 in byte-by-byte */
+
+static DWORD crc32 (	/* Returns next CRC value */
+	DWORD crc,			/* Current CRC value */
+	BYTE d				/* A byte to be processed */
+)
+{
+	BYTE b;
+
+
+	for (b = 1; b; b <<= 1) {
+		crc ^= (d & b) ? 1 : 0;
+		crc = (crc & 1) ? crc >> 1 ^ 0xEDB88320 : crc >> 1;
+	}
+	return crc;
+}
+
+
+/* Check validity of GPT header */
+
+static int test_gpt_header (	/* 0:Invalid, 1:Valid */
+	const BYTE* gpth			/* Pointer to the GPT header */
+)
+{
+	UINT i;
+	DWORD bcc, hlen;
+
+
+	if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1", 12)) return 0;	/* Check signature and version (1.0) */
+	hlen = ld_dword(gpth + GPTH_Size);						/* Check header size */
+	if (hlen < 92 || hlen > FF_MIN_SS) return 0;
+	for (i = 0, bcc = 0xFFFFFFFF; i < hlen; i++) {			/* Check header BCC */
+		bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]);
+	}
+	if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0;
+	if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0;	/* Table entry size (must be SZ_GPTE bytes) */
+	if (ld_dword(gpth + GPTH_PtNum) > 128) return 0;		/* Table size (must be 128 entries or less) */
+
+	return 1;
+}
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+
+/* Generate random value */
+static DWORD make_rand (
+	DWORD seed,		/* Seed value */
+	BYTE *buff,		/* Output buffer */
+	UINT n			/* Data length */
+)
+{
+	UINT r;
+
+
+	if (seed == 0) seed = 1;
+	do {
+		for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1;	/* Shift 8 bits the 32-bit LFSR */
+		*buff++ = (BYTE)seed;
+	} while (--n);
+	return seed;
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT VBR                           */
+/*-----------------------------------------------------------------------*/
+
+/* Check what the sector is */
+
+static UINT check_fs (	/* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */
+	FATFS* fs,			/* Filesystem object */
+	LBA_t sect			/* Sector to load and check if it is an FAT-VBR or not */
+)
+{
+	WORD w, sign;
+	BYTE b;
+
+
+	fs->wflag = 0; fs->winsect = (LBA_t)0 - 1;		/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK) return 4;	/* Load the boot sector */
+	sign = ld_word(fs->win + BS_55AA);
+#if FF_FS_EXFAT
+	if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;	/* It is an exFAT VBR */
+#endif
+	b = fs->win[BS_JmpBoot];
+	if (b == 0xEB || b == 0xE9 || b == 0xE8) {	/* Valid JumpBoot code? (short jump, near jump or near call) */
+		if (sign == 0xAA55 && !memcmp(fs->win + BS_FilSysType32, "FAT32   ", 8)) {
+			return 0;	/* It is an FAT32 VBR */
+		}
+		/* FAT volumes formatted with early MS-DOS lack BS_55AA and BS_FilSysType, so FAT VBR needs to be identified without them. */
+		w = ld_word(fs->win + BPB_BytsPerSec);
+		b = fs->win[BPB_SecPerClus];
+		if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS	/* Properness of sector size (512-4096 and 2^n) */
+			&& b != 0 && (b & (b - 1)) == 0				/* Properness of cluster size (2^n) */
+			&& ld_word(fs->win + BPB_RsvdSecCnt) != 0	/* Properness of reserved sectors (MNBZ) */
+			&& (UINT)fs->win[BPB_NumFATs] - 1 <= 1		/* Properness of FATs (1 or 2) */
+			&& ld_word(fs->win + BPB_RootEntCnt) != 0	/* Properness of root dir entries (MNBZ) */
+			&& (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000)	/* Properness of volume sectors (>=128) */
+			&& ld_word(fs->win + BPB_FATSz16) != 0) {	/* Properness of FAT size (MNBZ) */
+				return 0;	/* It can be presumed an FAT VBR */
+		}
+	}
+	return sign == 0xAA55 ? 2 : 3;	/* Not an FAT VBR (valid or invalid BS) */
+}
+
+
+/* Find an FAT volume */
+/* (It supports only generic partitioning rules, MBR, GPT and SFD) */
+
+static UINT find_volume (	/* Returns BS status found in the hosting drive */
+	FATFS* fs,		/* Filesystem object */
+	UINT part		/* Partition to fined = 0:find as SFD and partitions, >0:forced partition number */
+)
+{
+	UINT fmt, i;
+	DWORD mbr_pt[4];
+
+
+	fmt = check_fs(fs, 0);				/* Load sector 0 and check if it is an FAT VBR as SFD format */
+	if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt;	/* Returns if it is an FAT VBR as auto scan, not a BS or disk error */
+
+	/* Sector 0 is not an FAT VBR or forced partition number wants a partition */
+
+#if FF_LBA64
+	if (fs->win[MBR_Table + PTE_System] == 0xEE) {	/* GPT protective MBR? */
+		DWORD n_ent, v_ent, ofs;
+		QWORD pt_lba;
+
+		if (move_window(fs, 1) != FR_OK) return 4;	/* Load GPT header sector (next to MBR) */
+		if (!test_gpt_header(fs->win)) return 3;	/* Check if GPT header is valid */
+		n_ent = ld_dword(fs->win + GPTH_PtNum);		/* Number of entries */
+		pt_lba = ld_qword(fs->win + GPTH_PtOfs);	/* Table location */
+		for (v_ent = i = 0; i < n_ent; i++) {		/* Find FAT partition */
+			if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4;	/* PT sector */
+			ofs = i * SZ_GPTE % SS(fs);												/* Offset in the sector */
+			if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) {	/* MS basic data partition? */
+				v_ent++;
+				fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba));	/* Load VBR and check status */
+				if (part == 0 && fmt <= 1) return fmt;			/* Auto search (valid FAT volume found first) */
+				if (part != 0 && v_ent == part) return fmt;		/* Forced partition order (regardless of it is valid or not) */
+			}
+		}
+		return 3;	/* Not found */
+	}
+#endif
+	if (FF_MULTI_PARTITION && part > 4) return 3;	/* MBR has 4 partitions max */
+	for (i = 0; i < 4; i++) {		/* Load partition offset in the MBR */
+		mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba);
+	}
+	i = part ? part - 1 : 0;		/* Table index to find first */
+	do {							/* Find an FAT volume */
+		fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3;	/* Check if the partition is FAT */
+	} while (part == 0 && fmt >= 2 && ++i < 4);
+	return fmt;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Determine logical drive number and mount the volume if needed         */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT mount_volume (	/* FR_OK(0): successful, !=0: an error occurred */
+	const TCHAR** path,			/* Pointer to pointer to the path name (drive number) */
+	FATFS** rfs,				/* Pointer to pointer to the found filesystem object */
+	BYTE mode					/* Desiered access mode to check write protection */
+)
+{
+	int vol;
+	FATFS *fs;
+	DSTATUS stat;
+	LBA_t bsect;
+	DWORD tsect, sysect, fasize, nclst, szbfat;
+	WORD nrsv;
+	UINT fmt;
+
+
+	/* Get logical drive number */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the filesystem object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the filesystem object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the filesystem object available? */
+#if FF_FS_REENTRANT
+	if (!lock_volume(fs, 1)) return FR_TIMEOUT;	/* Lock the volume, and system if needed */
+#endif
+	*rfs = fs;							/* Return pointer to the filesystem object */
+
+	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+	if (fs->fs_type != 0) {				/* If the volume has been mounted */
+		stat = disk_status(fs->pdrv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			}
+			return FR_OK;				/* The filesystem object is already valid */
+		}
+	}
+
+	/* The filesystem object is not valid. */
+	/* Following code attempts to mount the volume. (find an FAT volume, analyze the BPB and initialize the filesystem object) */
+
+	fs->fs_type = 0;					/* Invalidate the filesystem object */
+	stat = disk_initialize(fs->pdrv);	/* Initialize the volume hosting physical drive */
+	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	}
+	if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+	}
+#if FF_MAX_SS != FF_MIN_SS				/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+	if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+	/* Find an FAT volume on the hosting drive */
+	fmt = find_volume(fs, LD2PT(vol));
+	if (fmt == 4) return FR_DISK_ERR;		/* An error occurred in the disk I/O layer */
+	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+	bsect = fs->winsect;					/* Volume offset in the hosting physical drive */
+
+	/* An FAT volume is found (bsect). Following code initializes the filesystem object */
+
+#if FF_FS_EXFAT
+	if (fmt == 1) {
+		QWORD maxlba;
+		DWORD so, cv, bcl, i;
+
+		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT version (must be version 1.0) */
+
+		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+			return FR_NO_FILESYSTEM;
+		}
+
+		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA of the volume + 1 */
+		if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be accessed in 32-bit LBA) */
+
+		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+
+		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+
+		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768 sectors) */
+
+		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+		fs->n_fatent = nclst + 2;
+
+		/* Boundaries and Limits */
+		fs->volbase = bsect;
+		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size required) */
+		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+		/* Get bitmap location and check if it is contiguous (implementation assumption) */
+		so = i = 0;
+		for (;;) {	/* Find the bitmap entry in the root directory (in only first cluster) */
+			if (i == 0) {
+				if (so >= fs->csize) return FR_NO_FILESYSTEM;	/* Not found? */
+				if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR;
+				so++;
+			}
+			if (fs->win[i] == ET_BITMAP) break;			/* Is it a bitmap entry? */
+			i = (i + SZDIRE) % SS(fs);	/* Next entry */
+		}
+		bcl = ld_dword(fs->win + i + 20);				/* Bitmap cluster */
+		if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM;	/* (Wrong cluster#) */
+		fs->bitbase = fs->database + fs->csize * (bcl - 2);	/* Bitmap sector */
+		for (;;) {	/* Check if bitmap is contiguous */
+			if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR;
+			cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4);
+			if (cv == 0xFFFFFFFF) break;				/* Last link? */
+			if (cv != ++bcl) return FR_NO_FILESYSTEM;	/* Fragmented bitmap? */
+		}
+
+#if !FF_FS_READONLY
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+#endif
+		fmt = FS_EXFAT;			/* FAT sub-type */
+	} else
+#endif	/* FF_FS_EXFAT */
+	{
+		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+		fs->fsize = fasize;
+
+		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+
+		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
+
+		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+
+		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+
+		/* Determine the FAT sub type */
+		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+		fmt = 0;
+		if (nclst <= MAX_FAT32) fmt = FS_FAT32;
+		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+		if (fmt == 0) return FR_NO_FILESYSTEM;
+
+		/* Boundaries and Limits */
+		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+		fs->volbase = bsect;							/* Volume start sector */
+		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+		fs->database = bsect + sysect;					/* Data start sector */
+		if (fmt == FS_FAT32) {
+			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
+			if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+		} else {
+			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
+			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+		}
+		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
+
+#if !FF_FS_READONLY
+		/* Get FSInfo if available */
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+		fs->fsi_flag = 0x80;
+#if (FF_FS_NOFSINFO & 3) != 3
+		if (fmt == FS_FAT32				/* Allow to update FSInfo only if BPB_FSInfo32 == 1 */
+			&& ld_word(fs->win + BPB_FSInfo32) == 1
+			&& move_window(fs, bsect + 1) == FR_OK)
+		{
+			fs->fsi_flag = 0;
+			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSInfo data if available */
+				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+			{
+#if (FF_FS_NOFSINFO & 1) == 0
+				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (FF_FS_NOFSINFO & 2) == 0
+				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+			}
+		}
+#endif	/* (FF_FS_NOFSINFO & 3) != 3 */
+#endif	/* !FF_FS_READONLY */
+	}
+
+	fs->fs_type = (BYTE)fmt;/* FAT sub-type (the filesystem object gets valid) */
+	fs->id = ++Fsid;		/* Volume mount ID */
+#if FF_USE_LFN == 1
+	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+#if FF_FS_EXFAT
+	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if FF_FS_RPATH != 0
+	fs->cdir = 0;			/* Initialize current directory */
+#endif
+#if FF_FS_LOCK				/* Clear file lock semaphores */
+	clear_share(fs);
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+	FFOBJID* obj,			/* Pointer to the FFOBJID, the 1st member in the FIL/DIR structure, to check validity */
+	FATFS** rfs				/* Pointer to pointer to the owner filesystem object to return */
+)
+{
+	FRESULT res = FR_INVALID_OBJECT;
+
+
+	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid */
+#if FF_FS_REENTRANT
+		if (lock_volume(obj->fs, 0)) {	/* Take a grant to access the volume */
+			if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */
+				res = FR_OK;
+			} else {
+				unlock_volume(obj->fs, FR_OK);	/* Invalidated volume, abort to access */
+			}
+		} else {	/* Could not take */
+			res = FR_TIMEOUT;
+		}
+#else
+		if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */
+			res = FR_OK;
+		}
+#endif
+	}
+	*rfs = (res == FR_OK) ? obj->fs : 0;	/* Return corresponding filesystem object if it is valid */
+	return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+   Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the filesystem object to be registered (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	/* Get volume ID (logical drive number) */
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];			/* Pointer to the filesystem object of the volume */
+
+	if (cfs) {					/* Unregister current filesystem object if regsitered */
+		FatFs[vol] = 0;
+#if FF_FS_LOCK
+		clear_share(cfs);
+#endif
+#if FF_FS_REENTRANT				/* Discard mutex of the current volume */
+		ff_mutex_delete(vol);
+#endif
+		cfs->fs_type = 0;		/* Invalidate the filesystem object to be unregistered */
+	}
+
+	if (fs) {					/* Register new filesystem object */
+		fs->pdrv = LD2PD(vol);	/* Volume hosting physical drive */
+#if FF_FS_REENTRANT				/* Create a volume mutex */
+		fs->ldrv = (BYTE)vol;	/* Owner volume ID */
+		if (!ff_mutex_create(vol)) return FR_INT_ERR;
+#if FF_FS_LOCK
+		if (SysLock == 0) {		/* Create a system mutex if needed */
+			if (!ff_mutex_create(FF_VOLUMES)) {
+				ff_mutex_delete(vol);
+				return FR_INT_ERR;
+			}
+			SysLock = 1;		/* System mutex is ready */
+		}
+#endif
+#endif
+		fs->fs_type = 0;		/* Invalidate the new filesystem object */
+		FatFs[vol] = fs;		/* Register new fs object */
+	}
+
+	if (opt == 0) return FR_OK;	/* Do not mount now, it will be mounted in subsequent file functions */
+
+	res = mount_volume(&path, &fs, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+#if !FF_FS_READONLY
+	DWORD cl, bcs, clst, tm;
+	LBA_t sc;
+	FSIZE_t ofs;
+#endif
+	DEF_NAMBUF
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive number */
+	mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND;
+	res = mount_volume(&path, &fs, mode);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+#if !FF_FS_READONLY	/* Read/Write configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			}
+#if FF_FS_LOCK
+			else {
+				res = chk_share(&dj, (mode & ~FA_READ) ? 1 : 0);	/* Check if the file can be used */
+			}
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+#if FF_FS_LOCK
+					res = enq_share() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				}
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+			}
+			else {								/* Any object with the same name is already existing */
+				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate the file if overwrite mode */
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					/* Get current allocation info */
+					fp->obj.fs = fs;
+					init_alloc_info(fs, &fp->obj);
+					/* Set directory entry block initial state */
+					memset(fs->dirbuf + 2, 0, 30);	/* Clear 85 entry except for NumSec */
+					memset(fs->dirbuf + 38, 0, 26);	/* Clear C0 entry except for NumName and NameHash */
+					fs->dirbuf[XDIR_Attr] = AM_ARC;
+					st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME());
+					fs->dirbuf[XDIR_GenFlags] = 1;
+					res = store_xdir(&dj);
+					if (res == FR_OK && fp->obj.sclust != 0) {	/* Remove the cluster chain if exist */
+						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+					}
+				} else
+#endif
+				{
+					/* Set directory entry initial state */
+					tm = GET_FATTIME();					/* Set created time */
+					st_dword(dj.dir + DIR_CrtTime, tm);
+					st_dword(dj.dir + DIR_ModTime, tm);
+					cl = ld_clust(fs, dj.dir);			/* Get current cluster chain */
+					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+					st_dword(dj.dir + DIR_FileSize, 0);
+					fs->wflag = 1;
+					if (cl != 0) {						/* Remove the cluster chain if exist */
+						sc = fs->winsect;
+						res = remove_chain(&dj.obj, cl, 0);
+						if (res == FR_OK) {
+							res = move_window(fs, sc);
+							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+						}
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Is the object exsiting? */
+				if (dj.obj.attr & AM_DIR) {		/* File open against a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */
+						res = FR_DENIED;
+					}
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED;	/* Set file change flag if created or overwritten */
+			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+			fp->dir_ptr = dj.dir;
+#if FF_FS_LOCK
+			fp->obj.lockid = inc_share(&dj, (mode & ~FA_READ) ? 1 : 0);	/* Lock the file for this session */
+			if (fp->obj.lockid == 0) res = FR_INT_ERR;
+#endif
+		}
+#else		/* R/O configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Is it origin directory itself? */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dj.obj.attr & AM_DIR) {		/* Is it a directory? */
+					res = FR_NO_FILE;
+				}
+			}
+		}
+#endif
+
+		if (res == FR_OK) {
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+				fp->obj.c_ofs = dj.blk_ofs;
+				init_alloc_info(fs, &fp->obj);
+			} else
+#endif
+			{
+				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+			}
+#if FF_USE_FASTSEEK
+			fp->cltbl = 0;		/* Disable fast seek mode */
+#endif
+			fp->obj.fs = fs;	/* Validate the file object */
+			fp->obj.id = fs->id;
+			fp->flag = mode;	/* Set file access mode */
+			fp->err = 0;		/* Clear error flag */
+			fp->sect = 0;		/* Invalidate current data sector */
+			fp->fptr = 0;		/* Set file pointer top of the file */
+#if !FF_FS_READONLY
+#if !FF_FS_TINY
+			memset(fp->buf, 0, sizeof fp->buf);	/* Clear sector buffer */
+#endif
+			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is specified */
+				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+				clst = fp->obj.sclust;				/* Follow the cluster chain */
+				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+					clst = get_fat(&fp->obj, clst);
+					if (clst <= 1) res = FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+				}
+				fp->clust = clst;
+				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+					sc = clst2sect(fs, clst);
+					if (sc == 0) {
+						res = FR_INT_ERR;
+					} else {
+						fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !FF_FS_TINY
+						if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+					}
+				}
+#if FF_FS_LOCK
+				if (res != FR_OK) dec_share(fp->obj.lockid); /* Decrement file open counter if seek failed */
+#endif
+			}
+#endif
+		}
+
+		FREE_NAMBUF();
+	}
+
+	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 	/* Open file to be read */
+	void* buff,	/* Data buffer to store the read data */
+	UINT btr,	/* Number of bytes to read */
+	UINT* br	/* Number of bytes read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	FSIZE_t remain;
+	UINT rcnt, cc, csect;
+	BYTE *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) {	/* Repeat until btr bytes read */
+		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (csect == 0) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+				} else {						/* Middle or end of the file */
+#if FF_USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+					}
+				}
+				if (clst < 2) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clst2sect(fs, fp->clust);	/* Get current sector */
+			if (sect == 0) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+			if (cc > 0) {						/* Read maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2		/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if FF_FS_TINY
+				if (fs->wflag && fs->winsect - sect < cc) {
+					memcpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+				}
+#else
+				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+					memcpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+				}
+#endif
+#endif
+				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+				continue;
+			}
+#if !FF_FS_TINY
+			if (fp->sect != sect) {			/* Load data sector if not in cache */
+#if !FF_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+				if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+			}
+#endif
+			fp->sect = sect;
+		}
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+#if FF_FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		memcpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#else
+		memcpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#endif
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Open file to be written */
+	const void* buff,	/* Data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Number of bytes written */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	UINT wcnt, cc, csect;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+
+	*bw = 0;	/* Clear write byte counter */
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	/* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
+	if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) {	/* Repeat until all data written */
+		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+			if (csect == 0) {				/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->obj.sclust;	/* Follow from the origin */
+					if (clst == 0) {		/* If no cluster is allocated, */
+						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+					}
+				} else {					/* On the middle or end of the file */
+#if FF_USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+					}
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+			}
+#if FF_FS_TINY
+			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back sector cache */
+#else
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			sect = clst2sect(fs, fp->clust);	/* Get current sector */
+			if (sect == 0) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+			if (cc > 0) {					/* Write maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if FF_FS_MINIMIZE <= 2
+#if FF_FS_TINY
+				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					memcpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+					fs->wflag = 0;
+				}
+#else
+				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					memcpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if FF_FS_TINY
+			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+				fs->winsect = sect;
+			}
+#else
+			if (fp->sect != sect && 		/* Fill sector cache with file data */
+				fp->fptr < fp->obj.objsize &&
+				disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
+					ABORT(fs, FR_DISK_ERR);
+			}
+#endif
+			fp->sect = sect;
+		}
+		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+#if FF_FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		memcpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fs->wflag = 1;
+#else
+		memcpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fp->flag |= FA_DIRTY;
+#endif
+	}
+
+	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Open file to be synced */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD tm;
+	BYTE *dir;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !FF_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			tm = GET_FATTIME();				/* Modified time */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+				if (res == FR_OK) {
+					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+				}
+				if (res == FR_OK) {
+					DIR dj;
+					DEF_NAMBUF
+
+					INIT_NAMBUF(fs);
+					res = load_obj_xdir(&dj, &fp->obj);	/* Load directory entry block */
+					if (res == FR_OK) {
+						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive attribute to indicate that the file has been changed */
+						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation information */
+						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);		/* Update start cluster */
+						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);		/* Update file size */
+						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);	/* (FatFs does not support Valid File Size feature) */
+						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+						fs->dirbuf[XDIR_ModTime10] = 0;
+						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+						res = store_xdir(&dj);	/* Restore it to the directory */
+						if (res == FR_OK) {
+							res = sync_fs(fs);
+							fp->flag &= (BYTE)~FA_MODIFIED;
+						}
+					}
+					FREE_NAMBUF();
+				}
+			} else
+#endif
+			{
+				res = move_window(fs, fp->dir_sect);
+				if (res == FR_OK) {
+					dir = fp->dir_ptr;
+					dir[DIR_Attr] |= AM_ARC;						/* Set archive attribute to indicate that the file has been changed */
+					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation information  */
+					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+					st_word(dir + DIR_LstAccDate, 0);
+					fs->wflag = 1;
+					res = sync_fs(fs);					/* Restore it to the directory */
+					fp->flag &= (BYTE)~FA_MODIFIED;
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL* fp		/* Open file to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+#if !FF_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(&fp->obj, &fs);	/* Lock volume */
+		if (res == FR_OK) {
+#if FF_FS_LOCK
+			res = dec_share(fp->obj.lockid);		/* Decrement file open counter */
+			if (res == FR_OK) fp->obj.fs = 0;	/* Invalidate file object */
+#else
+			fp->obj.fs = 0;	/* Invalidate file object */
+#endif
+#if FF_FS_REENTRANT
+			unlock_volume(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+#if FF_FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number to set */
+)
+{
+	int vol;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	CurrVol = (BYTE)vol;	/* Set it as current volume */
+
+	return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+#if FF_STR_VOLUME_ID == 2
+	UINT i;
+#endif
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the path */
+		if (res == FR_OK) {					/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Is it the start directory itself? */
+				fs->cdir = dj.obj.sclust;
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					fs->cdc_scl = dj.obj.c_scl;
+					fs->cdc_size = dj.obj.c_size;
+					fs->cdc_ofs = dj.obj.c_ofs;
+				}
+#endif
+			} else {
+				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+#if FF_FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+						fs->cdc_ofs = dj.blk_ofs;
+					} else
+#endif
+					{
+						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+					}
+				} else {
+					res = FR_NO_PATH;		/* Reached but a file */
+				}
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+#if FF_STR_VOLUME_ID == 2	/* Also current drive is changed if in Unix style volume ID */
+		if (res == FR_OK) {
+			for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ;	/* Set current drive */
+			CurrVol = (BYTE)i;
+		}
+#endif
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+#if FF_FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of buff in unit of TCHAR */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp = buff;
+#if FF_VOLUMES >= 2
+	UINT vl;
+#if FF_STR_VOLUME_ID
+	const char *vp;
+#endif
+#endif
+	FILINFO fno;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	buff[0] = 0;	/* Set null string to get current volume */
+	res = mount_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+
+		/* Follow parent directories and create the path */
+		i = len;			/* Bottom of buffer (directory stack base) */
+		if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path) */
+			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+				if (res != FR_OK) break;
+				res = move_window(fs, dj.sect);
+				if (res != FR_OK) break;
+				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+				res = dir_sdi(&dj, 0);
+				if (res != FR_OK) break;
+				do {							/* Find the entry links to the child directory */
+					res = DIR_READ_FILE(&dj);
+					if (res != FR_OK) break;
+					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+					res = dir_next(&dj, 0);
+				} while (res == FR_OK);
+				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+				if (res != FR_OK) break;
+				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+				for (n = 0; fno.fname[n]; n++) ;	/* Name length */
+				if (i < n + 1) {	/* Insufficient space to store the path name? */
+					res = FR_NOT_ENOUGH_CORE; break;
+				}
+				while (n) buff[--i] = fno.fname[--n];	/* Stack the name */
+				buff[--i] = '/';
+			}
+		}
+		if (res == FR_OK) {
+			if (i == len) buff[--i] = '/';	/* Is it the root-directory? */
+#if FF_VOLUMES >= 2			/* Put drive prefix */
+			vl = 0;
+#if FF_STR_VOLUME_ID >= 1	/* String volume ID */
+			for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ;
+			if (i >= n + 2) {
+				if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/';
+				for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ;
+				if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':';
+				vl++;
+			}
+#else						/* Numeric volume ID */
+			if (i >= 3) {
+				*tp++ = (TCHAR)'0' + CurrVol;
+				*tp++ = (TCHAR)':';
+				vl = 2;
+			}
+#endif
+			if (vl == 0) res = FR_NOT_ENOUGH_CORE;
+#endif
+			/* Add current directory path */
+			if (res == FR_OK) {
+				do {	/* Copy stacked path string */
+					*tp++ = buff[i++];
+				} while (i < len);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	*tp = 0;
+	LEAVE_FF(fs, res);
+}
+
+#endif /* FF_FS_RPATH >= 2 */
+#endif /* FF_FS_RPATH >= 1 */
+
+
+
+#if FF_FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File Read/Write Pointer                                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, bcs;
+	LBA_t nsect;
+	FSIZE_t ifptr;
+#if FF_USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, tlen, ulen;
+	DWORD *tbl;
+	LBA_t dsc;
+#endif
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res == FR_OK) res = (FRESULT)fp->err;
+#if FF_FS_EXFAT && !FF_FS_READONLY
+	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+	}
+#endif
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if FF_USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->obj.sclust;		/* Origin of the chain */
+			if (cl != 0) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(&fp->obj, cl);
+						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen) {
+				*tbl = 0;		/* Terminate table */
+			} else {
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+			}
+		} else {						/* Fast seek */
+			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs > 0) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clst2sect(fs, fp->clust);
+				if (dsc == 0) ABORT(fs, FR_INT_ERR);
+				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+						fp->flag &= (BYTE)~FA_DIRTY;
+					}
+#endif
+					if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sector */
+#endif
+					fp->sect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+#if FF_FS_EXFAT
+		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4 GiB - 1 if at FATxx */
+#endif
+		if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, clip offset with the file size */
+			ofs = fp->obj.objsize;
+		}
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs > 0) {
+			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->obj.sclust;					/* start from the first cluster */
+#if !FF_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(&fp->obj, 0);
+					if (clst == 1) ABORT(fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					fp->obj.sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+					ofs -= bcs; fp->fptr += bcs;
+#if !FF_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize to generate FAT value */
+							fp->obj.objsize = fp->fptr;
+							fp->flag |= FA_MODIFIED;
+						}
+						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+						if (clst == 0) {				/* Clip file size in case of disk full */
+							ofs = 0; break;
+						}
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+					}
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+					fp->clust = clst;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fs)) {
+					nsect = clst2sect(fs, clst);	/* Current sector */
+					if (nsect == 0) ABORT(fs, FR_INT_ERR);
+					nsect += (DWORD)(ofs / SS(fs));
+				}
+			}
+		}
+		if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) {	/* Set file change flag if the file size is extended */
+			fp->obj.objsize = fp->fptr;
+			fp->flag |= FA_MODIFIED;
+		}
+		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+#endif
+			fp->sect = nsect;
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dp->obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+				if (dp->obj.attr & AM_DIR) {		/* This object is a sub-directory */
+#if FF_FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						dp->obj.c_scl = dp->obj.sclust;	/* Get containing directory inforamation */
+						dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+						dp->obj.c_ofs = dp->blk_ofs;
+						init_alloc_info(fs, &dp->obj);	/* Get object allocation info */
+					} else
+#endif
+					{
+						dp->obj.sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+					}
+				} else {						/* This object is a file */
+					res = FR_NO_PATH;
+				}
+			}
+			if (res == FR_OK) {
+				dp->obj.id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if FF_FS_LOCK
+				if (res == FR_OK) {
+					if (dp->obj.sclust != 0) {
+						dp->obj.lockid = inc_share(dp, 0);	/* Lock the sub directory */
+						if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						dp->obj.lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) dp->obj.fs = 0;		/* Invalidate the directory object if function failed */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+#if FF_FS_LOCK
+		if (dp->obj.lockid) res = dec_share(dp->obj.lockid);	/* Decrement sub-directory open counter */
+		if (res == FR_OK) dp->obj.fs = 0;	/* Invalidate directory object */
+#else
+		dp->obj.fs = 0;	/* Invalidate directory object */
+#endif
+#if FF_FS_REENTRANT
+		unlock_volume(fs, FR_OK);	/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);		/* Rewind the directory object */
+		} else {
+			INIT_NAMBUF(fs);
+			res = DIR_READ_FILE(dp);		/* Read an item */
+			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+			}
+			FREE_NAMBUF();
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+		if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break;		/* Test for the file name */
+#if FF_USE_LFN && FF_USE_FIND == 2
+		if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break;	/* Test for alternative name if exist */
+#endif
+	}
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK) {
+		res = f_findnext(dp, fno);	/* Find the first item */
+	}
+	return res;
+}
+
+#endif	/* FF_USE_FIND */
+
+
+
+#if FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &dj.obj.fs, 0);
+	if (res == FR_OK) {
+		INIT_NAMBUF(dj.obj.fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+				res = FR_INVALID_NAME;
+			} else {							/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding filesystem object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, stat;
+	LBA_t sect;
+	UINT i;
+	FFOBJID obj;
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		*fatfs = fs;				/* Return ptr to the fs object */
+		/* If free_clst is valid, return it without full FAT scan */
+		if (fs->free_clst <= fs->n_fatent - 2) {
+			*nclst = fs->free_clst;
+		} else {
+			/* Scan FAT to obtain number of free clusters */
+			nfree = 0;
+			if (fs->fs_type == FS_FAT12) {	/* FAT12: Scan bit field FAT entries */
+				clst = 2; obj.fs = fs;
+				do {
+					stat = get_fat(&obj, clst);
+					if (stat == 0xFFFFFFFF) {
+						res = FR_DISK_ERR; break;
+					}
+					if (stat == 1) {
+						res = FR_INT_ERR; break;
+					}
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan allocation bitmap */
+					BYTE bm;
+					UINT b;
+
+					clst = fs->n_fatent - 2;	/* Number of clusters */
+					sect = fs->bitbase;			/* Bitmap sector */
+					i = 0;						/* Offset in the sector */
+					do {	/* Counts numbuer of bits with zero in the bitmap */
+						if (i == 0) {	/* New sector? */
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+						}
+						for (b = 8, bm = ~fs->win[i]; b && clst; b--, clst--) {
+							nfree += bm & 1;
+							bm >>= 1;
+						}
+						i = (i + 1) % SS(fs);
+					} while (clst);
+				} else
+#endif
+				{	/* FAT16/32: Scan WORD/DWORD FAT entries */
+					clst = fs->n_fatent;	/* Number of entries */
+					sect = fs->fatbase;		/* Top of the FAT */
+					i = 0;					/* Offset in the sector */
+					do {	/* Counts numbuer of entries with zero in the FAT */
+						if (i == 0) {	/* New sector? */
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+						}
+						if (fs->fs_type == FS_FAT16) {
+							if (ld_word(fs->win + i) == 0) nfree++;
+							i += 2;
+						} else {
+							if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++;
+							i += 4;
+						}
+						i %= SS(fs);
+					} while (--clst);
+				}
+			}
+			if (res == FR_OK) {		/* Update parameters if succeeded */
+				*nclst = nfree;			/* Return the free clusters */
+				fs->free_clst = nfree;	/* Now free_clst is valid */
+				fs->fsi_flag |= 1;		/* FAT32: FSInfo is to be updated */
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD ncl;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+			fp->obj.sclust = 0;
+		} else {				/* When truncate a part of the file, remove remaining clusters */
+			ncl = get_fat(&fp->obj, fp->clust);
+			res = FR_OK;
+			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (ncl == 1) res = FR_INT_ERR;
+			if (res == FR_OK && ncl < fs->n_fatent) {
+				res = remove_chain(&fp->obj, ncl, fp->clust);
+			}
+		}
+		fp->obj.objsize = fp->fptr;	/* Set file size to current read/write point */
+		fp->flag |= FA_MODIFIED;
+#if !FF_FS_TINY
+		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+			if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
+				res = FR_DISK_ERR;
+			} else {
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+		}
+#endif
+		if (res != FR_OK) ABORT(fs, res);
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj, sdj;
+	DWORD dclst = 0;
+#if FF_FS_EXFAT
+	FFOBJID obj;
+#endif
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, FA_WRITE);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+		}
+#if FF_FS_LOCK
+		if (res == FR_OK) res = chk_share(&dj, 2);	/* Check if it is an open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dj.obj.attr & AM_RDO) {
+					res = FR_DENIED;		/* Cannot remove R/O object */
+				}
+			}
+			if (res == FR_OK) {
+#if FF_FS_EXFAT
+				obj.fs = fs;
+				if (fs->fs_type == FS_EXFAT) {
+					init_alloc_info(fs, &obj);
+					dclst = obj.sclust;
+				} else
+#endif
+				{
+					dclst = ld_clust(fs, dj.dir);
+				}
+				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+#if FF_FS_RPATH != 0
+					if (dclst == fs->cdir) {	 	/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						sdj.obj.fs = fs;			/* Open the sub-directory */
+						sdj.obj.sclust = dclst;
+#if FF_FS_EXFAT
+						if (fs->fs_type == FS_EXFAT) {
+							sdj.obj.objsize = obj.objsize;
+							sdj.obj.stat = obj.stat;
+						}
+#endif
+						res = dir_sdi(&sdj, 0);
+						if (res == FR_OK) {
+							res = DIR_READ_FILE(&sdj);			/* Test if the directory is empty */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);			/* Remove the directory entry */
+				if (res == FR_OK && dclst != 0) {	/* Remove the cluster chain if exist */
+#if FF_FS_EXFAT
+					res = remove_chain(&obj, dclst, 0);
+#else
+					res = remove_chain(&dj.obj, dclst, 0);
+#endif
+				}
+				if (res == FR_OK) res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	FFOBJID sobj;
+	DWORD dcl, pcl, tm;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Name collision? */
+		if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {	/* Invalid name? */
+			res = FR_INVALID_NAME;
+		}
+		if (res == FR_NO_FILE) {				/* It is clear to create a new directory */
+			sobj.fs = fs;						/* New object id to create a new chain */
+			dcl = create_chain(&sobj, 0);		/* Allocate a cluster for the new directory */
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster? */
+			if (dcl == 1) res = FR_INT_ERR;		/* Any insanity? */
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;	/* Disk error? */
+			tm = GET_FATTIME();
+			if (res == FR_OK) {
+				res = dir_clear(fs, dcl);		/* Clean up the new table */
+				if (res == FR_OK) {
+					if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* Create dot entries (FAT only) */
+						memset(fs->win + DIR_Name, ' ', 11);	/* Create "." entry */
+						fs->win[DIR_Name] = '.';
+						fs->win[DIR_Attr] = AM_DIR;
+						st_dword(fs->win + DIR_ModTime, tm);
+						st_clust(fs, fs->win, dcl);
+						memcpy(fs->win + SZDIRE, fs->win, SZDIRE);	/* Create ".." entry */
+						fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+						st_clust(fs, fs->win + SZDIRE, pcl);
+						fs->wflag = 1;
+					}
+					res = dir_register(&dj);	/* Register the object to the parent directoy */
+				}
+			}
+			if (res == FR_OK) {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs));	/* Directory size needs to be valid */
+					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs));
+					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag */
+					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+					res = store_xdir(&dj);
+				} else
+#endif
+				{
+					st_dword(dj.dir + DIR_ModTime, tm);	/* Created time */
+					st_clust(fs, dj.dir, dcl);			/* Table start cluster */
+					dj.dir[DIR_Attr] = AM_DIR;			/* Attribute */
+					fs->wflag = 1;
+				}
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			} else {
+				remove_chain(&sobj, dcl, 0);		/* Could not register, remove the allocated cluster */
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR djo, djn;
+	BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir;
+	LBA_t sect;
+	DEF_NAMBUF
+
+
+	get_ldnumber(&path_new);						/* Snip the drive number of new name off */
+	res = mount_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+	if (res == FR_OK) {
+		djo.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&djo, path_old);			/* Check old object */
+		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check validity of name */
+#if FF_FS_LOCK
+		if (res == FR_OK) {
+			res = chk_share(&djo, 2);
+		}
+#endif
+		if (res == FR_OK) {					/* Object to be renamed is found */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* At exFAT volume */
+				BYTE nf, nn;
+				WORD nh;
+
+				memcpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+				memcpy(&djn, &djo, sizeof djo);
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+						memcpy(fs->dirbuf, buf, SZDIRE * 2);	/* Restore 85+C0 entry */
+						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+						st_word(fs->dirbuf + XDIR_NameHash, nh);
+						if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC;	/* Set archive attribute if it is a file */
+/* Start of critical section where an interruption can cause a cross-link */
+						res = store_xdir(&djn);
+					}
+				}
+			} else
+#endif
+			{	/* At FAT/FAT32 volume */
+				memcpy(buf, djo.dir, SZDIRE);			/* Save directory entry of the object */
+				memcpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						dir = djn.dir;					/* Copy directory entry of the object except name */
+						memcpy(dir + 13, buf + 13, SZDIRE - 13);
+						dir[DIR_Attr] = buf[DIR_Attr];
+						if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC;	/* Set archive attribute if it is a file */
+						fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the sub-directory if needed */
+							sect = clst2sect(fs, ld_clust(fs, dir));
+							if (sect == 0) {
+								res = FR_INT_ERR;
+							} else {
+/* Start of critical section where an interruption can cause a cross-link */
+								res = move_window(fs, sect);
+								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(fs, dir, djn.obj.sclust);
+									fs->wflag = 1;
+								}
+							}
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&djo);		/* Remove old entry */
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			}
+/* End of the critical section */
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_FS_MINIMIZE == 0 */
+#endif /* FF_FS_MINIMIZE <= 1 */
+#endif /* FF_FS_MINIMIZE <= 2 */
+
+
+
+#if FF_USE_CHMOD && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the timestamp to be set */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif	/* FF_USE_CHMOD && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Logical drive number */
+	TCHAR* label,		/* Buffer to store the volume label */
+	DWORD* vsn			/* Variable to store the volume serial number */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	UINT si, di;
+	WCHAR wc;
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+		 	res = DIR_READ_LABEL(&dj);		/* Find a volume label entry */
+		 	if (res == FR_OK) {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					WCHAR hs;
+					UINT nw;
+
+					for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+						wc = ld_word(dj.dir + XDIR_Label + si * 2);
+						if (hs == 0 && IsSurrogate(wc)) {	/* Is the code a surrogate? */
+							hs = wc; continue;
+						}
+						nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4);	/* Store it in API encoding */
+						if (nw == 0) {		/* Encode error? */
+							di = 0; break;
+						}
+						di += nw;
+						hs = 0;
+					}
+					if (hs != 0) di = 0;	/* Broken surrogate pair? */
+					label[di] = 0;
+				} else
+#endif
+				{
+					si = di = 0;		/* Extract volume label from AM_VOL entry */
+					while (si < 11) {
+						wc = dj.dir[si++];
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1 	/* Unicode output */
+						if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++];	/* Is it a DBC? */
+						wc = ff_oem2uni(wc, CODEPAGE);		/* Convert it into Unicode */
+						if (wc == 0) {		/* Invalid char in current code page? */
+							di = 0; break;
+						}
+						di += put_utf(wc, &label[di], 4);	/* Store it in Unicode */
+#else									/* ANSI/OEM output */
+						label[di++] = (TCHAR)wc;
+#endif
+					}
+					do {				/* Truncate trailing spaces */
+						label[di] = 0;
+						if (di == 0) break;
+					} while (label[--di] == ' ');
+				}
+			}
+		}
+		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+			label[0] = 0;
+			res = FR_OK;
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(fs, fs->volbase);
+		if (res == FR_OK) {
+			switch (fs->fs_type) {
+			case FS_EXFAT:
+				di = BPB_VolIDEx;
+				break;
+
+			case FS_FAT32:
+				di = BS_VolID32;
+				break;
+
+			default:
+				di = BS_VolID;
+			}
+			*vsn = ld_dword(fs->win + di);
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Volume label to set with heading logical drive number */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	BYTE dirvn[22];
+	UINT di;
+	WCHAR wc;
+	static const char badchr[18] = "+.,;=[]" "/*:<>|\\\"\?\x7F";	/* [0..16] for FAT, [7..16] for exFAT */
+#if FF_USE_LFN
+	DWORD dc;
+#endif
+
+	/* Get logical drive */
+	res = mount_volume(&label, &fs, FA_WRITE);
+	if (res != FR_OK) LEAVE_FF(fs, res);
+#if FF_STR_VOLUME_ID == 2
+	for ( ; *label == '/'; label++) ;	/* Snip the separators off */
+#endif
+
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		memset(dirvn, 0, 22);
+		di = 0;
+		while ((UINT)*label >= ' ') {	/* Create volume label */
+			dc = tchar2uni(&label);	/* Get a Unicode character */
+			if (dc >= 0x10000) {
+				if (dc == 0xFFFFFFFF || di >= 10) {	/* Wrong surrogate or buffer overflow */
+					dc = 0;
+				} else {
+					st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++;
+				}
+			}
+			if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) {	/* Check validity of the volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			st_word(dirvn + di * 2, (WCHAR)dc); di++;
+		}
+	} else
+#endif
+	{	/* On the FAT/FAT32 volume */
+		memset(dirvn, ' ', 11);
+		di = 0;
+		while ((UINT)*label >= ' ') {	/* Create volume label */
+#if FF_USE_LFN
+			dc = tchar2uni(&label);
+			wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0;
+#else									/* ANSI/OEM input */
+			wc = (BYTE)*label++;
+			if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0;
+			if (IsLower(wc)) wc -= 0x20;		/* To upper ASCII characters */
+#if FF_CODE_PAGE == 0
+			if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80];	/* To upper extended characters (SBCS cfg) */
+#elif FF_CODE_PAGE < 900
+			if (wc >= 0x80) wc = ExCvt[wc - 0x80];	/* To upper extended characters (SBCS cfg) */
+#endif
+#endif
+			if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) {	/* Reject invalid characters for volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8);
+			dirvn[di++] = (BYTE)wc;
+		}
+		if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+		while (di && dirvn[di - 1] == ' ') di--;				/* Snip trailing spaces */
+	}
+
+	/* Set volume label */
+	dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = DIR_READ_LABEL(&dj);	/* Get volume label entry */
+		if (res == FR_OK) {
+			if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+				dj.dir[XDIR_NumLabel] = (BYTE)di;	/* Change the volume label */
+				memcpy(dj.dir + XDIR_Label, dirvn, 22);
+			} else {
+				if (di != 0) {
+					memcpy(dj.dir, dirvn, 11);	/* Change the volume label */
+				} else {
+					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+				}
+			}
+			fs->wflag = 1;
+			res = sync_fs(fs);
+		} else {			/* No volume label entry or an error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (di != 0) {	/* Create a volume label entry */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+					if (res == FR_OK) {
+						memset(dj.dir, 0, SZDIRE);	/* Clean the entry */
+						if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+							dj.dir[XDIR_Type] = ET_VLABEL;	/* Create volume label entry */
+							dj.dir[XDIR_NumLabel] = (BYTE)di;
+							memcpy(dj.dir + XDIR_Label, dirvn, 22);
+						} else {
+							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+							memcpy(dj.dir, dirvn, 11);
+						}
+						fs->wflag = 1;
+						res = sync_fs(fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_LABEL */
+
+
+
+#if FF_USE_EXPAND && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File                              */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t fsz,	/* File size to be expanded to */
+	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if FF_FS_EXFAT
+	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size limit */
+#endif
+	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+	stcl = fs->last_clst; lclst = 0;
+	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+				lclst = scl + tcl - 1;
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	} else
+#endif
+	{
+		scl = clst = stcl; ncl = 0;
+		for (;;) {	/* Find a contiguous cluster block */
+			n = get_fat(&fp->obj, clst);
+			if (++clst >= fs->n_fatent) clst = 2;
+			if (n == 1) {
+				res = FR_INT_ERR; break;
+			}
+			if (n == 0xFFFFFFFF) {
+				res = FR_DISK_ERR; break;
+			}
+			if (n == 0) {	/* Is it a free cluster? */
+				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+			} else {
+				scl = clst; ncl = 0;		/* Not a free cluster */
+			}
+			if (clst == stcl) {		/* No contiguous cluster? */
+				res = FR_DENIED; break;
+			}
+		}
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+					if (res != FR_OK) break;
+					lclst = clst;
+				}
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	}
+
+	if (res == FR_OK) {
+		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+		if (opt) {	/* Is it allocated now? */
+			fp->obj.sclust = scl;		/* Update object allocation information */
+			fp->obj.objsize = fsz;
+			if (FF_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+			fp->flag |= FA_MODIFIED;
+			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+				fs->free_clst -= tcl;
+				fs->fsi_flag |= 1;
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* FF_USE_EXPAND && !FF_FS_READONLY */
+
+
+
+#if FF_USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward Data to the Stream Directly                                   */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	FSIZE_t remain;
+	UINT rcnt, csect;
+	BYTE *dbuf;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	remain = fp->obj.objsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {	/* Repeat until all data transferred or stream goes busy */
+		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+			if (csect == 0) {						/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clst2sect(fs, fp->clust);			/* Get current data sector */
+		if (sect == 0) ABORT(fs, FR_INT_ERR);
+		sect += csect;
+#if FF_FS_TINY
+		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file data */
+		dbuf = fs->win;
+#else
+		if (fp->sect != sect) {		/* Fill sector cache with file data */
+#if !FF_FS_READONLY
+			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+		dbuf = fp->buf;
+#endif
+		fp->sect = sect;
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+		if (rcnt == 0) ABORT(fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif /* FF_USE_FORWARD */
+
+
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+/*-----------------------------------------------------------------------*/
+/* Create FAT/exFAT volume (with sub-functions)                          */
+/*-----------------------------------------------------------------------*/
+
+#define N_SEC_TRACK 63			/* Sectors per track for determination of drive CHS */
+#define	GPT_ALIGN	0x100000	/* Alignment of partitions in GPT [byte] (>=128KB) */
+#define GPT_ITEMS	128			/* Number of GPT table size (>=128, sector aligned) */
+
+
+/* Create partitions on the physical drive in format of MBR or GPT */
+
+static FRESULT create_partition (
+	BYTE drv,			/* Physical drive number */
+	const LBA_t plst[],	/* Partition list */
+	BYTE sys,			/* System ID for each partition (for only MBR) */
+	BYTE *buf			/* Working buffer for a sector */
+)
+{
+	UINT i, cy;
+	LBA_t sz_drv;
+	DWORD sz_drv32, nxt_alloc32, sz_part32;
+	BYTE *pte;
+	BYTE hd, n_hd, sc, n_sc;
+
+	/* Get physical drive size */
+	if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR;
+
+#if FF_LBA64
+	if (sz_drv >= FF_MIN_GPT) {	/* Create partitions in GPT format */
+		WORD ss;
+		UINT sz_ptbl, pi, si, ofs;
+		DWORD bcc, rnd, align;
+		QWORD nxt_alloc, sz_part, sz_pool, top_bpt;
+		static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF};
+
+#if FF_MAX_SS != FF_MIN_SS
+		if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;	/* Get sector size */
+		if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+		ss = FF_MAX_SS;
+#endif
+		rnd = (DWORD)sz_drv + GET_FATTIME();	/* Random seed */
+		align = GPT_ALIGN / ss;				/* Partition alignment for GPT [sector] */
+		sz_ptbl = GPT_ITEMS * SZ_GPTE / ss;	/* Size of partition table [sector] */
+		top_bpt = sz_drv - sz_ptbl - 1;		/* Backup partition table start sector */
+		nxt_alloc = 2 + sz_ptbl;			/* First allocatable sector */
+		sz_pool = top_bpt - nxt_alloc;		/* Size of allocatable area */
+		bcc = 0xFFFFFFFF; sz_part = 1;
+		pi = si = 0;	/* partition table index, size table index */
+		do {
+			if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss);	/* Clean the buffer if needed */
+			if (sz_part != 0) {				/* Is the size table not termintated? */
+				nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align);	/* Align partition start */
+				sz_part = plst[si++];		/* Get a partition size */
+				if (sz_part <= 100) {		/* Is the size in percentage? */
+					sz_part = sz_pool * sz_part / 100;
+					sz_part = (sz_part + align - 1) & ((QWORD)0 - align);	/* Align partition end (only if in percentage) */
+				}
+				if (nxt_alloc + sz_part > top_bpt) {	/* Clip the size at end of the pool */
+					sz_part = (nxt_alloc < top_bpt) ? top_bpt - nxt_alloc : 0;
+				}
+			}
+			if (sz_part != 0) {				/* Add a partition? */
+				ofs = pi * SZ_GPTE % ss;
+				memcpy(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16);	/* Set partition GUID (Microsoft Basic Data) */
+				rnd = make_rand(rnd, buf + ofs + GPTE_UpGuid, 16);	/* Set unique partition GUID */
+				st_qword(buf + ofs + GPTE_FstLba, nxt_alloc);		/* Set partition start sector */
+				st_qword(buf + ofs + GPTE_LstLba, nxt_alloc + sz_part - 1);	/* Set partition end sector */
+				nxt_alloc += sz_part;								/* Next allocatable sector */
+			}
+			if ((pi + 1) * SZ_GPTE % ss == 0) {		/* Write the buffer if it is filled up */
+				for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ;	/* Calculate table check sum */
+				if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR;		/* Write to primary table */
+				if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR;	/* Write to secondary table */
+			}
+		} while (++pi < GPT_ITEMS);
+
+		/* Create primary GPT header */
+		memset(buf, 0, ss);
+		memcpy(buf + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16);	/* Signature, version (1.0) and size (92) */
+		st_dword(buf + GPTH_PtBcc, ~bcc);			/* Table check sum */
+		st_qword(buf + GPTH_CurLba, 1);				/* LBA of this header */
+		st_qword(buf + GPTH_BakLba, sz_drv - 1);	/* LBA of secondary header */
+		st_qword(buf + GPTH_FstLba, 2 + sz_ptbl);	/* LBA of first allocatable sector */
+		st_qword(buf + GPTH_LstLba, top_bpt - 1);	/* LBA of last allocatable sector */
+		st_dword(buf + GPTH_PteSize, SZ_GPTE);		/* Size of a table entry */
+		st_dword(buf + GPTH_PtNum, GPT_ITEMS);		/* Number of table entries */
+		st_dword(buf + GPTH_PtOfs, 2);				/* LBA of this table */
+		rnd = make_rand(rnd, buf + GPTH_DskGuid, 16);	/* Disk GUID */
+		for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ;	/* Calculate header check sum */
+		st_dword(buf + GPTH_Bcc, ~bcc);				/* Header check sum */
+		if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR;
+
+		/* Create secondary GPT header */
+		st_qword(buf + GPTH_CurLba, sz_drv - 1);	/* LBA of this header */
+		st_qword(buf + GPTH_BakLba, 1);				/* LBA of primary header */
+		st_qword(buf + GPTH_PtOfs, top_bpt);		/* LBA of this table */
+		st_dword(buf + GPTH_Bcc, 0);
+		for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ;	/* Calculate header check sum */
+		st_dword(buf + GPTH_Bcc, ~bcc);				/* Header check sum */
+		if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR;
+
+		/* Create protective MBR */
+		memset(buf, 0, ss);
+		memcpy(buf + MBR_Table, gpt_mbr, 16);		/* Create a GPT partition */
+		st_word(buf + BS_55AA, 0xAA55);
+		if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;
+
+	} else
+#endif
+	{	/* Create partitions in MBR format */
+		sz_drv32 = (DWORD)sz_drv;
+		n_sc = N_SEC_TRACK;				/* Determine drive CHS without any consideration of the drive geometry */
+		for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ;
+		if (n_hd == 0) n_hd = 255;		/* Number of heads needs to be <256 */
+
+		memset(buf, 0, FF_MAX_SS);		/* Clear MBR */
+		pte = buf + MBR_Table;	/* Partition table in the MBR */
+		for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) {
+			sz_part32 = (DWORD)plst[i];	/* Get partition size */
+			if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32;	/* Size in percentage? */
+			if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32;	/* Clip at drive size */
+			if (sz_part32 == 0) break;	/* End of table or no sector to allocate? */
+
+			st_dword(pte + PTE_StLba, nxt_alloc32);	/* Start LBA */
+			st_dword(pte + PTE_SizLba, sz_part32);	/* Number of sectors */
+			pte[PTE_System] = sys;					/* System type */
+
+			cy = (UINT)(nxt_alloc32 / n_sc / n_hd);	/* Start cylinder */
+			hd = (BYTE)(nxt_alloc32 / n_sc % n_hd);	/* Start head */
+			sc = (BYTE)(nxt_alloc32 % n_sc + 1);	/* Start sector */
+			pte[PTE_StHead] = hd;
+			pte[PTE_StSec] = (BYTE)((cy >> 2 & 0xC0) | sc);
+			pte[PTE_StCyl] = (BYTE)cy;
+
+			cy = (UINT)((nxt_alloc32 + sz_part32 - 1) / n_sc / n_hd);	/* End cylinder */
+			hd = (BYTE)((nxt_alloc32 + sz_part32 - 1) / n_sc % n_hd);	/* End head */
+			sc = (BYTE)((nxt_alloc32 + sz_part32 - 1) % n_sc + 1);		/* End sector */
+			pte[PTE_EdHead] = hd;
+			pte[PTE_EdSec] = (BYTE)((cy >> 2 & 0xC0) | sc);
+			pte[PTE_EdCyl] = (BYTE)cy;
+
+			pte += SZ_PTE;		/* Next entry */
+		}
+
+		st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+		if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+	}
+
+	return FR_OK;
+}
+
+
+
+FRESULT f_mkfs (
+	const TCHAR* path,		/* Logical drive number */
+	const MKFS_PARM* opt,	/* Format options */
+	void* work,				/* Pointer to working buffer (null: use len bytes of heap memory) */
+	UINT len				/* Size of working buffer [byte] */
+)
+{
+	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT volume (4Ks unit) */
+	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
+	static const MKFS_PARM defopt = {FM_ANY, 0, 0, 0, 0};	/* Default parameter */
+	BYTE fsopt, fsty, sys, pdrv, ipart;
+	BYTE *buf;
+	BYTE *pte;
+	WORD ss;	/* Sector size */
+	DWORD sz_buf, sz_blk, n_clst, pau, nsect, n, vsn;
+	LBA_t sz_vol, b_vol, b_fat, b_data;		/* Size of volume, Base LBA of volume, fat, data */
+	LBA_t sect, lba[2];
+	DWORD sz_rsv, sz_fat, sz_dir, sz_au;	/* Size of reserved, fat, dir, data, cluster */
+	UINT n_fat, n_root, i;					/* Index, Number of FATs and Number of roor dir entries */
+	int vol;
+	DSTATUS ds;
+	FRESULT res;
+
+
+	/* Check mounted drive and clear work area */
+	vol = get_ldnumber(&path);					/* Get target logical drive */
+	if (vol < 0) return FR_INVALID_DRIVE;
+	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the fs object if mounted */
+	pdrv = LD2PD(vol);		/* Hosting physical drive */
+	ipart = LD2PT(vol);		/* Hosting partition (0:create as new, 1..:existing partition) */
+
+	/* Initialize the hosting physical drive */
+	ds = disk_initialize(pdrv);
+	if (ds & STA_NOINIT) return FR_NOT_READY;
+	if (ds & STA_PROTECT) return FR_WRITE_PROTECTED;
+
+	/* Get physical drive parameters (sz_drv, sz_blk and ss) */
+	if (!opt) opt = &defopt;	/* Use default parameter if it is not given */
+	sz_blk = opt->align;
+	if (sz_blk == 0) disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk);					/* Block size from the paramter or lower layer */
+ 	if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Use default if the block size is invalid */
+#if FF_MAX_SS != FF_MIN_SS
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+	if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+	ss = FF_MAX_SS;
+#endif
+
+	/* Options for FAT sub-type and FAT parameters */
+	fsopt = opt->fmt & (FM_ANY | FM_SFD);
+	n_fat = (opt->n_fat >= 1 && opt->n_fat <= 2) ? opt->n_fat : 1;
+	n_root = (opt->n_root >= 1 && opt->n_root <= 32768 && (opt->n_root % (ss / SZDIRE)) == 0) ? opt->n_root : 512;
+	sz_au = (opt->au_size <= 0x1000000 && (opt->au_size & (opt->au_size - 1)) == 0) ? opt->au_size : 0;
+	sz_au /= ss;	/* Byte --> Sector */
+
+	/* Get working buffer */
+	sz_buf = len / ss;		/* Size of working buffer [sector] */
+	if (sz_buf == 0) return FR_NOT_ENOUGH_CORE;
+	buf = (BYTE*)work;		/* Working buffer */
+#if FF_USE_LFN == 3
+	if (!buf) buf = ff_memalloc(sz_buf * ss);	/* Use heap memory for working buffer */
+#endif
+	if (!buf) return FR_NOT_ENOUGH_CORE;
+
+	/* Determine where the volume to be located (b_vol, sz_vol) */
+	b_vol = sz_vol = 0;
+	if (FF_MULTI_PARTITION && ipart != 0) {	/* Is the volume associated with any specific partition? */
+		/* Get partition location from the existing partition table */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Load MBR */
+		if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if MBR is valid */
+#if FF_LBA64
+		if (buf[MBR_Table + PTE_System] == 0xEE) {	/* GPT protective MBR? */
+			DWORD n_ent, ofs;
+			QWORD pt_lba;
+
+			/* Get the partition location from GPT */
+			if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Load GPT header sector (next to MBR) */
+			if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if GPT header is valid */
+			n_ent = ld_dword(buf + GPTH_PtNum);		/* Number of entries */
+			pt_lba = ld_qword(buf + GPTH_PtOfs);	/* Table start sector */
+			ofs = i = 0;
+			while (n_ent) {		/* Find MS Basic partition with order of ipart */
+				if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Get PT sector */
+				if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) {	/* MS basic data partition? */
+					b_vol = ld_qword(buf + ofs + GPTE_FstLba);
+					sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1;
+					break;
+				}
+				n_ent--; ofs = (ofs + SZ_GPTE) % ss;	/* Next entry */
+			}
+			if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Partition not found */
+			fsopt |= 0x80;	/* Partitioning is in GPT */
+		} else
+#endif
+		{	/* Get the partition location from MBR partition table */
+			pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE);
+			if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED);	/* No partition? */
+			b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+			sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+		}
+	} else {	/* The volume is associated with a physical drive */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+		if (!(fsopt & FM_SFD)) {	/* To be partitioned? */
+			/* Create a single-partition on the drive in this function */
+#if FF_LBA64
+			if (sz_vol >= FF_MIN_GPT) {	/* Which partition type to create, MBR or GPT? */
+				fsopt |= 0x80;		/* Partitioning is in GPT */
+				b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1;	/* Estimated partition offset and size */
+			} else
+#endif
+			{	/* Partitioning is in MBR */
+				if (sz_vol > N_SEC_TRACK) {
+					b_vol = N_SEC_TRACK; sz_vol -= b_vol;	/* Estimated partition offset and size */
+				}
+			}
+		}
+	}
+	if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if volume size is >=128s */
+
+	/* Now start to create an FAT volume at b_vol and sz_vol */
+
+	do {	/* Pre-determine the FAT type */
+		if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) {	/* exFAT possible? */
+			if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) {	/* exFAT only, vol >= 64MS or sz_au > 128S ? */
+				fsty = FS_EXFAT; break;
+			}
+		}
+#if FF_LBA64
+		if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too large volume for FAT/FAT32 */
+#endif
+		if (sz_au > 128) sz_au = 128;	/* Invalid AU for FAT/FAT32? */
+		if (fsopt & FM_FAT32) {	/* FAT32 possible? */
+			if (!(fsopt & FM_FAT)) {	/* no-FAT? */
+				fsty = FS_FAT32; break;
+			}
+		}
+		if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER);	/* no-FAT? */
+		fsty = FS_FAT16;
+	} while (0);
+
+	vsn = (DWORD)sz_vol + GET_FATTIME();	/* VSN generated from current time and partitiion size */
+
+#if FF_FS_EXFAT
+	if (fsty == FS_EXFAT) {	/* Create an exFAT volume */
+		DWORD szb_bit, szb_case, sum, nbit, clu, clen[3];
+		WCHAR ch, si;
+		UINT j, st;
+
+		if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume for exFAT? */
+#if FF_USE_TRIM
+		lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1;	/* Inform storage device that the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, lba);
+#endif
+		/* Determine FAT location, data location and number of clusters */
+		if (sz_au == 0) {	/* AU auto-selection */
+			sz_au = 8;
+			if (sz_vol >= 0x80000) sz_au = 64;		/* >= 512Ks */
+			if (sz_vol >= 0x4000000) sz_au = 256;	/* >= 64Ms */
+		}
+		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+		sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss;	/* Number of FAT sectors */
+		b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1);	/* Align data area to the erase block boundary */
+		if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
+		n_clst = (DWORD)((sz_vol - (b_data - b_vol)) / sz_au);	/* Number of clusters */
+		if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED);			/* Too few clusters? */
+		if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too many clusters? */
+
+		szb_bit = (n_clst + 7) / 8;								/* Size of allocation bitmap */
+		clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss);	/* Number of allocation bitmap clusters */
+
+		/* Create a compressed up-case table */
+		sect = b_data + sz_au * clen[0];	/* Table start sector */
+		sum = 0;							/* Table checksum to be stored in the 82 entry */
+		st = 0; si = 0; i = 0; j = 0; szb_case = 0;
+		do {
+			switch (st) {
+			case 0:
+				ch = (WCHAR)ff_wtoupper(si);	/* Get an up-case char */
+				if (ch != si) {
+					si++; break;		/* Store the up-case char if exist */
+				}
+				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get run length of no-case block */
+				if (j >= 128) {
+					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 chars */
+				}
+				st = 1;			/* Do not compress short run */
+				/* FALLTHROUGH */
+			case 1:
+				ch = si++;		/* Fill the short run */
+				if (--j == 0) st = 0;
+				break;
+
+			default:
+				ch = (WCHAR)j; si += (WCHAR)j;	/* Number of chars to skip */
+				st = 0;
+			}
+			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);	/* Put it into the write buffer */
+			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+			i += 2; szb_case += 2;
+			if (si == 0 || i == sz_buf * ss) {		/* Write buffered data when buffer full or end of process */
+				n = (i + ss - 1) / ss;
+				if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+				sect += n; i = 0;
+			}
+		} while (si);
+		clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss);	/* Number of up-case table clusters */
+		clen[2] = 1;	/* Number of root dir clusters */
+
+		/* Initialize the allocation bitmap */
+		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of bitmap sectors */
+		nbit = clen[0] + clen[1] + clen[2];				/* Number of clusters in-use by system (bitmap, up-case and root-dir) */
+		do {
+			memset(buf, 0, sz_buf * ss);				/* Initialize bitmap buffer */
+			for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ;	/* Mark used clusters */
+			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the FAT */
+		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+		j = nbit = clu = 0;
+		do {
+			memset(buf, 0, sz_buf * ss); i = 0;	/* Clear work area and reset write offset */
+			if (clu == 0) {	/* Initialize FAT [0] and FAT[1] */
+				st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++;
+				st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++;
+			}
+			do {			/* Create chains of bitmap, up-case and root dir */
+				while (nbit != 0 && i < sz_buf * ss) {	/* Create a chain */
+					st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF);
+					i += 4; clu++; nbit--;
+				}
+				if (nbit == 0 && j < 3) nbit = clen[j++];	/* Get next chain length */
+			} while (nbit != 0 && i < sz_buf * ss);
+			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the root directory */
+		memset(buf, 0, sz_buf * ss);
+		buf[SZDIRE * 0 + 0] = ET_VLABEL;				/* Volume label entry (no label) */
+		buf[SZDIRE * 1 + 0] = ET_BITMAP;				/* Bitmap entry */
+		st_dword(buf + SZDIRE * 1 + 20, 2);				/*  cluster */
+		st_dword(buf + SZDIRE * 1 + 24, szb_bit);		/*  size */
+		buf[SZDIRE * 2 + 0] = ET_UPCASE;				/* Up-case table entry */
+		st_dword(buf + SZDIRE * 2 + 4, sum);			/*  sum */
+		st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]);	/*  cluster */
+		st_dword(buf + SZDIRE * 2 + 24, szb_case);		/*  size */
+		sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au;	/* Start of the root directory and number of sectors */
+		do {	/* Fill root directory sectors */
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			memset(buf, 0, ss);	/* Rest of entries are filled with zero */
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Create two set of the exFAT VBR blocks */
+		sect = b_vol;
+		for (n = 0; n < 2; n++) {
+			/* Main record (+0) */
+			memset(buf, 0, ss);
+			memcpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+			st_qword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+			st_qword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+			st_dword(buf + BPB_FatOfsEx, (DWORD)(b_fat - b_vol));	/* FAT offset [sector] */
+			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+			st_dword(buf + BPB_DataOfsEx, (DWORD)(b_data - b_vol));	/* Data offset [sector] */
+			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+			st_dword(buf + BPB_RootClusEx, 2 + clen[0] + clen[1]);	/* Root dir cluster # */
+			st_dword(buf + BPB_VolIDEx, vsn);						/* VSN */
+			st_word(buf + BPB_FSVerEx, 0x100);						/* Filesystem version (1.00) */
+			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector size [byte] */
+			for (buf[BPB_SecPerClusEx] = 0, i = sz_au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster size [sector] */
+			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+			}
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			/* Extended bootstrap record (+1..+8) */
+			memset(buf, 0, ss);
+			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+			for (j = 1; j < 9; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			}
+			/* OEM/Reserved record (+9..+10) */
+			memset(buf, 0, ss);
+			for ( ; j < 11; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			}
+			/* Sum record (+11) */
+			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+		}
+
+	} else
+#endif	/* FF_FS_EXFAT */
+	{	/* Create an FAT/FAT32 volume */
+		do {
+			pau = sz_au;
+			/* Pre-determine number of clusters and FAT sub-type */
+			if (fsty == FS_FAT32) {	/* FAT32 volume */
+				if (pau == 0) {	/* AU auto-selection */
+					n = (DWORD)sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = (DWORD)sz_vol / pau;	/* Number of clusters */
+				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+				sz_rsv = 32;	/* Number of reserved sectors */
+				sz_dir = 0;		/* No static directory */
+				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
+			} else {				/* FAT volume */
+				if (pau == 0) {	/* au auto-selection */
+					n = (DWORD)sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = (DWORD)sz_vol / pau;
+				if (n_clst > MAX_FAT12) {
+					n = n_clst * 2 + 4;		/* FAT size [byte] */
+				} else {
+					fsty = FS_FAT12;
+					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+				}
+				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+				sz_rsv = 1;						/* Number of reserved sectors */
+				sz_dir = (DWORD)n_root * SZDIRE / ss;	/* Root dir size [sector] */
+			}
+			b_fat = b_vol + sz_rsv;						/* FAT base */
+			b_data = b_fat + sz_fat * n_fat + sz_dir;	/* Data base */
+
+			/* Align data area to erase block boundary (for flash memory media) */
+			n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data);	/* Sectors to next nearest from current data base */
+			if (fsty == FS_FAT32) {		/* FAT32: Move FAT */
+				sz_rsv += n; b_fat += n;
+			} else {					/* FAT: Expand FAT */
+				if (n % n_fat) {	/* Adjust fractional error if needed */
+					n--; sz_rsv++; b_fat++;
+				}
+				sz_fat += n / n_fat;
+			}
+
+			/* Determine number of clusters and final check of validity of the FAT sub-type */
+			if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
+			n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau;
+			if (fsty == FS_FAT32) {
+				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32? */
+					if (sz_au == 0 && (sz_au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+			}
+			if (fsty == FS_FAT16) {
+				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+					if (sz_au == 0 && (pau * 2) <= 64) {
+						sz_au = pau * 2; continue;	/* Adjust cluster size and retry */
+					}
+					if ((fsopt & FM_FAT32)) {
+						fsty = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+					}
+					if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+					if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+			}
+			if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too many clusters for FAT12 */
+
+			/* Ok, it is the valid cluster configuration */
+			break;
+		} while (1);
+
+#if FF_USE_TRIM
+		lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1;	/* Inform storage device that the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, lba);
+#endif
+		/* Create FAT VBR */
+		memset(buf, 0, ss);
+		memcpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);	/* Boot jump code (x86), OEM name */
+		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+		buf[BPB_NumFATs] = (BYTE)n_fat;					/* Number of FATs */
+		st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root));	/* Number of root directory entries */
+		if (sz_vol < 0x10000) {
+			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+		} else {
+			st_dword(buf + BPB_TotSec32, (DWORD)sz_vol);	/* Volume size in 32-bit LBA */
+		}
+		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_dword(buf + BPB_HiddSec, (DWORD)b_vol);		/* Volume offset in the physical drive [sector] */
+		if (fsty == FS_FAT32) {
+			st_dword(buf + BS_VolID32, vsn);			/* VSN */
+			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+			memcpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+		} else {
+			st_dword(buf + BS_VolID, vsn);				/* VSN */
+			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+			memcpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+		}
+		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
+		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it to the VBR sector */
+
+		/* Create FSINFO record if needed */
+		if (fsty == FS_FAT32) {
+			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+			memset(buf, 0, ss);
+			st_dword(buf + FSI_LeadSig, 0x41615252);
+			st_dword(buf + FSI_StrucSig, 0x61417272);
+			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			st_word(buf + BS_55AA, 0xAA55);
+			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+		}
+
+		/* Initialize FAT area */
+		memset(buf, 0, sz_buf * ss);
+		sect = b_fat;		/* FAT start sector */
+		for (i = 0; i < n_fat; i++) {			/* Initialize FATs each */
+			if (fsty == FS_FAT32) {
+				st_dword(buf + 0, 0xFFFFFFF8);	/* FAT[0] */
+				st_dword(buf + 4, 0xFFFFFFFF);	/* FAT[1] */
+				st_dword(buf + 8, 0x0FFFFFFF);	/* FAT[2] (root directory) */
+			} else {
+				st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* FAT[0] and FAT[1] */
+			}
+			nsect = sz_fat;		/* Number of FAT sectors */
+			do {	/* Fill FAT sectors */
+				n = (nsect > sz_buf) ? sz_buf : nsect;
+				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+				memset(buf, 0, ss);	/* Rest of FAT all are cleared */
+				sect += n; nsect -= n;
+			} while (nsect);
+		}
+
+		/* Initialize root directory (fill with zero) */
+		nsect = (fsty == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+		do {
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+	}
+
+	/* A FAT volume has been created here */
+
+	/* Determine system ID in the MBR partition table */
+	if (FF_FS_EXFAT && fsty == FS_EXFAT) {
+		sys = 0x07;		/* exFAT */
+	} else if (fsty == FS_FAT32) {
+		sys = 0x0C;		/* FAT32X */
+	} else if (sz_vol >= 0x10000) {
+		sys = 0x06;		/* FAT12/16 (large) */
+	} else if (fsty == FS_FAT16) {
+		sys = 0x04;		/* FAT16 */
+	} else {
+		sys = 0x01;		/* FAT12 */
+	}
+
+	/* Update partition information */
+	if (FF_MULTI_PARTITION && ipart != 0) {	/* Volume is in the existing partition */
+		if (!FF_LBA64 || !(fsopt & 0x80)) {	/* Is the partition in MBR? */
+			/* Update system ID in the partition table */
+			if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Read the MBR */
+			buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys;			/* Set system ID */
+			if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it back to the MBR */
+		}
+	} else {								/* Volume as a new single partition */
+		if (!(fsopt & FM_SFD)) {			/* Create partition table if not in SFD format */
+			lba[0] = sz_vol; lba[1] = 0;
+			res = create_partition(pdrv, lba, sys, buf);
+			if (res != FR_OK) LEAVE_MKFS(res);
+		}
+	}
+
+	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+
+	LEAVE_MKFS(FR_OK);
+}
+
+
+
+
+#if FF_MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create Partition Table on the Physical Drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const LBA_t ptbl[],	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer (null: use heap memory) */
+)
+{
+	BYTE *buf = (BYTE*)work;
+	DSTATUS stat;
+	FRESULT res;
+
+
+	/* Initialize the physical drive */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+
+#if FF_USE_LFN == 3
+	if (!buf) buf = ff_memalloc(FF_MAX_SS);	/* Use heap memory for working buffer */
+#endif
+	if (!buf) return FR_NOT_ENOUGH_CORE;
+
+	res = create_partition(pdrv, ptbl, 0x07, buf);	/* Create partitions (system ID is temporary setting and determined by f_mkfs) */
+
+	LEAVE_MKFS(res);
+}
+
+#endif /* FF_MULTI_PARTITION */
+#endif /* !FF_FS_READONLY && FF_USE_MKFS */
+
+
+
+
+#if FF_USE_STRFUNC
+#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3)
+#error Wrong FF_STRF_ENCODE setting
+#endif
+/*-----------------------------------------------------------------------*/
+/* Get a String from the File                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the buffer to store read string */
+	int len,		/* Size of string buffer (items) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int nc = 0;
+	TCHAR *p = buff;
+	BYTE s[4];
+	UINT rc;
+	DWORD dc;
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2
+	WCHAR wc;
+#endif
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3
+	UINT ct;
+#endif
+
+#if FF_USE_LFN && FF_LFN_UNICODE			/* With code conversion (Unicode API) */
+	/* Make a room for the character and terminator  */
+	if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2;
+	if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4;
+	if (FF_LFN_UNICODE == 3) len -= 1;
+	while (nc < len) {
+#if FF_STRF_ENCODE == 0				/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);		/* Get a code unit */
+		if (rc != 1) break;			/* EOF? */
+		wc = s[0];
+		if (dbc_1st((BYTE)wc)) {	/* DBC 1st byte? */
+			f_read(fp, s, 1, &rc);	/* Get 2nd byte */
+			if (rc != 1 || !dbc_2nd(s[0])) continue;	/* Wrong code? */
+			wc = wc << 8 | s[0];
+		}
+		dc = ff_oem2uni(wc, CODEPAGE);	/* Convert ANSI/OEM into Unicode */
+		if (dc == 0) continue;		/* Conversion error? */
+#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 	/* Read a character in UTF-16LE/BE */
+		f_read(fp, s, 2, &rc);		/* Get a code unit */
+		if (rc != 2) break;			/* EOF? */
+		dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+		if (IsSurrogateL(dc)) continue;	/* Broken surrogate pair? */
+		if (IsSurrogateH(dc)) {		/* High surrogate? */
+			f_read(fp, s, 2, &rc);	/* Get low surrogate */
+			if (rc != 2) break;		/* EOF? */
+			wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+			if (!IsSurrogateL(wc)) continue;	/* Broken surrogate pair? */
+			dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF);	/* Merge surrogate pair */
+		}
+#else	/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);		/* Get a code unit */
+		if (rc != 1) break;			/* EOF? */
+		dc = s[0];
+		if (dc >= 0x80) {			/* Multi-byte sequence? */
+			ct = 0;
+			if ((dc & 0xE0) == 0xC0) {	/* 2-byte sequence? */
+				dc &= 0x1F; ct = 1;
+			}
+			if ((dc & 0xF0) == 0xE0) {	/* 3-byte sequence? */
+				dc &= 0x0F; ct = 2;
+			}
+			if ((dc & 0xF8) == 0xF0) {	/* 4-byte sequence? */
+				dc &= 0x07; ct = 3;
+			}
+			if (ct == 0) continue;
+			f_read(fp, s, ct, &rc);	/* Get trailing bytes */
+			if (rc != ct) break;
+			rc = 0;
+			do {	/* Merge the byte sequence */
+				if ((s[rc] & 0xC0) != 0x80) break;
+				dc = dc << 6 | (s[rc] & 0x3F);
+			} while (++rc < ct);
+			if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue;	/* Wrong encoding? */
+		}
+#endif
+		/* A code point is avaialble in dc to be output */
+
+		if (FF_USE_STRFUNC == 2 && dc == '\r') continue;	/* Strip \r off if needed */
+#if FF_LFN_UNICODE == 1	|| FF_LFN_UNICODE == 3	/* Output it in UTF-16/32 encoding */
+		if (FF_LFN_UNICODE == 1 && dc >= 0x10000) {	/* Out of BMP at UTF-16? */
+			*p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++;	/* Make and output high surrogate */
+			dc = 0xDC00 | (dc & 0x3FF);		/* Make low surrogate */
+		}
+		*p++ = (TCHAR)dc; nc++;
+		if (dc == '\n') break;	/* End of line? */
+#elif FF_LFN_UNICODE == 2		/* Output it in UTF-8 encoding */
+		if (dc < 0x80) {	/* Single byte? */
+			*p++ = (TCHAR)dc;
+			nc++;
+			if (dc == '\n') break;	/* End of line? */
+		} else if (dc < 0x800) {	/* 2-byte sequence? */
+			*p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 2;
+		} else if (dc < 0x10000) {	/* 3-byte sequence? */
+			*p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F));
+			*p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 3;
+		} else {					/* 4-byte sequence */
+			*p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07));
+			*p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 4;
+		}
+#endif
+	}
+
+#else			/* Byte-by-byte read without any conversion (ANSI/OEM API) */
+	len -= 1;	/* Make a room for the terminator */
+	while (nc < len) {
+		f_read(fp, s, 1, &rc);	/* Get a byte */
+		if (rc != 1) break;		/* EOF? */
+		dc = s[0];
+		if (FF_USE_STRFUNC == 2 && dc == '\r') continue;
+		*p++ = (TCHAR)dc; nc++;
+		if (dc == '\n') break;
+	}
+#endif
+
+	*p = 0;		/* Terminate the string */
+	return nc ? buff : 0;	/* When no data read due to EOF or error, return with error. */
+}
+
+
+
+
+#if !FF_FS_READONLY
+#include <stdarg.h>
+#define SZ_PUTC_BUF	64
+#define SZ_NUM_BUF	32
+
+/*-----------------------------------------------------------------------*/
+/* Put a Character to the File (with sub-functions)                      */
+/*-----------------------------------------------------------------------*/
+
+/* Output buffer and work area */
+
+typedef struct {
+	FIL *fp;		/* Ptr to the writing file */
+	int idx, nchr;	/* Write index of buf[] (-1:error), number of encoding units written */
+#if FF_USE_LFN && FF_LFN_UNICODE == 1
+	WCHAR hs;
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2
+	BYTE bs[4];
+	UINT wi, ct;
+#endif
+	BYTE buf[SZ_PUTC_BUF];	/* Write buffer */
+} putbuff;
+
+
+/* Buffered file write with code conversion */
+
+static void putc_bfd (putbuff* pb, TCHAR c)
+{
+	UINT n;
+	int i, nc;
+#if FF_USE_LFN && FF_LFN_UNICODE
+	WCHAR hs, wc;
+#if FF_LFN_UNICODE == 2
+	DWORD dc;
+	const TCHAR* tp;
+#endif
+#endif
+
+	if (FF_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+	}
+
+	i = pb->idx;			/* Write index of pb->buf[] */
+	if (i < 0) return;		/* In write error? */
+	nc = pb->nchr;			/* Write unit counter */
+
+#if FF_USE_LFN && FF_LFN_UNICODE
+#if FF_LFN_UNICODE == 1		/* UTF-16 input */
+	if (IsSurrogateH(c)) {	/* Is this a high-surrogate? */
+		pb->hs = c; return;	/* Save it for next */
+	}
+	hs = pb->hs; pb->hs = 0;
+	if (hs != 0) {			/* Is there a leading high-surrogate? */
+		if (!IsSurrogateL(c)) hs = 0;	/* Discard high-surrogate if not a surrogate pair */
+	} else {
+		if (IsSurrogateL(c)) return;	/* Discard stray low-surrogate */
+	}
+	wc = c;
+#elif FF_LFN_UNICODE == 2	/* UTF-8 input */
+	for (;;) {
+		if (pb->ct == 0) {	/* Out of multi-byte sequence? */
+			pb->bs[pb->wi = 0] = (BYTE)c;	/* Save 1st byte */
+			if ((BYTE)c < 0x80) break;					/* Single byte code? */
+			if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1;	/* 2-byte sequence? */
+			if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2;	/* 3-byte sequence? */
+			if (((BYTE)c & 0xF8) == 0xF0) pb->ct = 3;	/* 4-byte sequence? */
+			return;										/* Wrong leading byte (discard it) */
+		} else {				/* In the multi-byte sequence */
+			if (((BYTE)c & 0xC0) != 0x80) {	/* Broken sequence? */
+				pb->ct = 0; continue;		/* Discard the sequense */
+			}
+			pb->bs[++pb->wi] = (BYTE)c;	/* Save the trailing byte */
+			if (--pb->ct == 0) break;	/* End of the sequence? */
+			return;
+		}
+	}
+	tp = (const TCHAR*)pb->bs;
+	dc = tchar2uni(&tp);			/* UTF-8 ==> UTF-16 */
+	if (dc == 0xFFFFFFFF) return;	/* Wrong code? */
+	hs = (WCHAR)(dc >> 16);
+	wc = (WCHAR)dc;
+#elif FF_LFN_UNICODE == 3	/* UTF-32 input */
+	if (IsSurrogate(c) || c >= 0x110000) return;	/* Discard invalid code */
+	if (c >= 0x10000) {		/* Out of BMP? */
+		hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); 	/* Make high surrogate */
+		wc = 0xDC00 | (c & 0x3FF);					/* Make low surrogate */
+	} else {
+		hs = 0;
+		wc = (WCHAR)c;
+	}
+#endif
+	/* A code point in UTF-16 is available in hs and wc */
+
+#if FF_STRF_ENCODE == 1		/* Write a code point in UTF-16LE */
+	if (hs != 0) {	/* Surrogate pair? */
+		st_word(&pb->buf[i], hs);
+		i += 2;
+		nc++;
+	}
+	st_word(&pb->buf[i], wc);
+	i += 2;
+#elif FF_STRF_ENCODE == 2	/* Write a code point in UTF-16BE */
+	if (hs != 0) {	/* Surrogate pair? */
+		pb->buf[i++] = (BYTE)(hs >> 8);
+		pb->buf[i++] = (BYTE)hs;
+		nc++;
+	}
+	pb->buf[i++] = (BYTE)(wc >> 8);
+	pb->buf[i++] = (BYTE)wc;
+#elif FF_STRF_ENCODE == 3	/* Write a code point in UTF-8 */
+	if (hs != 0) {	/* 4-byte sequence? */
+		nc += 3;
+		hs = (hs & 0x3FF) + 0x40;
+		pb->buf[i++] = (BYTE)(0xF0 | hs >> 8);
+		pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F));
+		pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F));
+		pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+	} else {
+		if (wc < 0x80) {	/* Single byte? */
+			pb->buf[i++] = (BYTE)wc;
+		} else {
+			if (wc < 0x800) {	/* 2-byte sequence? */
+				nc += 1;
+				pb->buf[i++] = (BYTE)(0xC0 | wc >> 6);
+			} else {			/* 3-byte sequence */
+				nc += 2;
+				pb->buf[i++] = (BYTE)(0xE0 | wc >> 12);
+				pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F));
+			}
+			pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+		}
+	}
+#else						/* Write a code point in ANSI/OEM */
+	if (hs != 0) return;
+	wc = ff_uni2oem(wc, CODEPAGE);	/* UTF-16 ==> ANSI/OEM */
+	if (wc == 0) return;
+	if (wc >= 0x100) {
+		pb->buf[i++] = (BYTE)(wc >> 8); nc++;
+	}
+	pb->buf[i++] = (BYTE)wc;
+#endif
+
+#else							/* ANSI/OEM input (without re-encoding) */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 4) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &n);
+		i = (n == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr = nc + 1;
+}
+
+
+/* Flush remaining characters in the buffer */
+
+static int putc_flush (putbuff* pb)
+{
+	UINT nw;
+
+	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+		&& (UINT)pb->idx == nw) return pb->nchr;
+	return -1;
+}
+
+
+/* Initialize write buffer */
+
+static void putc_init (putbuff* pb, FIL* fp)
+{
+	memset(pb, 0, sizeof (putbuff));
+	pb->fp = fp;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	putc_bfd(&pb, c);	/* Put the character */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a String to the File                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a Formatted String to the File (with sub-functions)               */
+/*-----------------------------------------------------------------------*/
+#if FF_PRINT_FLOAT && FF_INTDEF == 2
+#include <math.h>
+
+static int ilog10 (double n)	/* Calculate log10(n) in integer output */
+{
+	int rv = 0;
+
+	while (n >= 10) {	/* Decimate digit in right shift */
+		if (n >= 100000) {
+			n /= 100000; rv += 5;
+		} else {
+			n /= 10; rv++;
+		}
+	}
+	while (n < 1) {		/* Decimate digit in left shift */
+		if (n < 0.00001) {
+			n *= 100000; rv -= 5;
+		} else {
+			n *= 10; rv--;
+		}
+	}
+	return rv;
+}
+
+
+static double i10x (int n)	/* Calculate 10^n in integer input */
+{
+	double rv = 1;
+
+	while (n > 0) {		/* Left shift */
+		if (n >= 5) {
+			rv *= 100000; n -= 5;
+		} else {
+			rv *= 10; n--;
+		}
+	}
+	while (n < 0) {		/* Right shift */
+		if (n <= -5) {
+			rv /= 100000; n += 5;
+		} else {
+			rv /= 10; n++;
+		}
+	}
+	return rv;
+}
+
+
+static void ftoa (
+	char* buf,	/* Buffer to output the floating point string */
+	double val,	/* Value to output */
+	int prec,	/* Number of fractional digits */
+	TCHAR fmt	/* Notation */
+)
+{
+	int d;
+	int e = 0, m = 0;
+	char sign = 0;
+	double w;
+	const char *er = 0;
+	const char ds = FF_PRINT_FLOAT == 2 ? ',' : '.';
+
+
+	if (isnan(val)) {			/* Not a number? */
+		er = "NaN";
+	} else {
+		if (prec < 0) prec = 6;	/* Default precision? (6 fractional digits) */
+		if (val < 0) {			/* Negative? */
+			val = 0 - val; sign = '-';
+		} else {
+			sign = '+';
+		}
+		if (isinf(val)) {		/* Infinite? */
+			er = "INF";
+		} else {
+			if (fmt == 'f') {	/* Decimal notation? */
+				val += i10x(0 - prec) / 2;	/* Round (nearest) */
+				m = ilog10(val);
+				if (m < 0) m = 0;
+				if (m + prec + 3 >= SZ_NUM_BUF) er = "OV";	/* Buffer overflow? */
+			} else {			/* E notation */
+				if (val != 0) {		/* Not a true zero? */
+					val += i10x(ilog10(val) - prec) / 2;	/* Round (nearest) */
+					e = ilog10(val);
+					if (e > 99 || prec + 7 >= SZ_NUM_BUF) {	/* Buffer overflow or E > +99? */
+						er = "OV";
+					} else {
+						if (e < -99) e = -99;
+						val /= i10x(e);	/* Normalize */
+					}
+				}
+			}
+		}
+		if (!er) {	/* Not error condition */
+			if (sign == '-') *buf++ = sign;	/* Add a - if negative value */
+			do {				/* Put decimal number */
+				if (m == -1) *buf++ = ds;	/* Insert a decimal separator when get into fractional part */
+				w = i10x(m);				/* Snip the highest digit d */
+				d = (int)(val / w); val -= d * w;
+				*buf++ = (char)('0' + d);	/* Put the digit */
+			} while (--m >= -prec);			/* Output all digits specified by prec */
+			if (fmt != 'f') {	/* Put exponent if needed */
+				*buf++ = (char)fmt;
+				if (e < 0) {
+					e = 0 - e; *buf++ = '-';
+				} else {
+					*buf++ = '+';
+				}
+				*buf++ = (char)('0' + e / 10);
+				*buf++ = (char)('0' + e % 10);
+			}
+		}
+	}
+	if (er) {	/* Error condition */
+		if (sign) *buf++ = sign;		/* Add sign if needed */
+		do {		/* Put error symbol */
+			*buf++ = *er++;
+		} while (*er);
+	}
+	*buf = 0;	/* Term */
+}
+#endif	/* FF_PRINT_FLOAT && FF_INTDEF == 2 */
+
+
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	putbuff pb;
+	UINT i, j, w, f, r;
+	int prec;
+#if FF_PRINT_LLI && FF_INTDEF == 2
+	QWORD v;
+#else
+	DWORD v;
+#endif
+	TCHAR *tp;
+	TCHAR tc, pad;
+	TCHAR nul = 0;
+	char d, str[SZ_NUM_BUF];
+
+
+	putc_init(&pb, fp);
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		tc = *fmt++;
+		if (tc == 0) break;			/* End of format string */
+		if (tc != '%') {			/* Not an escape character (pass-through) */
+			putc_bfd(&pb, tc);
+			continue;
+		}
+		f = w = 0; pad = ' '; prec = -1;	/* Initialize parms */
+		tc = *fmt++;
+		if (tc == '0') {			/* Flag: '0' padded */
+			pad = '0'; tc = *fmt++;
+		} else if (tc == '-') {		/* Flag: Left aligned */
+			f = 2; tc = *fmt++;
+		}
+		if (tc == '*') {			/* Minimum width from an argument */
+			w = va_arg(arp, int);
+			tc = *fmt++;
+		} else {
+			while (IsDigit(tc)) {	/* Minimum width */
+				w = w * 10 + tc - '0';
+				tc = *fmt++;
+			}
+		}
+		if (tc == '.') {			/* Precision */
+			tc = *fmt++;
+			if (tc == '*') {		/* Precision from an argument */
+				prec = va_arg(arp, int);
+				tc = *fmt++;
+			} else {
+				prec = 0;
+				while (IsDigit(tc)) {	/* Precision */
+					prec = prec * 10 + tc - '0';
+					tc = *fmt++;
+				}
+			}
+		}
+		if (tc == 'l') {			/* Size: long int */
+			f |= 4; tc = *fmt++;
+#if FF_PRINT_LLI && FF_INTDEF == 2
+			if (tc == 'l') {		/* Size: long long int */
+				f |= 8; tc = *fmt++;
+			}
+#endif
+		}
+		if (tc == 0) break;			/* End of format string */
+		switch (tc) {				/* Atgument type is... */
+		case 'b':					/* Unsigned binary */
+			r = 2; break;
+
+		case 'o':					/* Unsigned octal */
+			r = 8; break;
+
+		case 'd':					/* Signed decimal */
+		case 'u': 					/* Unsigned decimal */
+			r = 10; break;
+
+		case 'x':					/* Unsigned hexadecimal (lower case) */
+		case 'X': 					/* Unsigned hexadecimal (upper case) */
+			r = 16; break;
+
+		case 'c':					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int));
+			continue;
+
+		case 's':					/* String */
+			tp = va_arg(arp, TCHAR*);	/* Get a pointer argument */
+			if (!tp) tp = &nul;		/* Null ptr generates a null string */
+			for (j = 0; tp[j]; j++) ;	/* j = tcslen(tp) */
+			if (prec >= 0 && j > (UINT)prec) j = prec;	/* Limited length of string body */
+			for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad);	/* Left pads */
+			while (*tp && prec--) putc_bfd(&pb, *tp++);	/* Body */
+			while (j++ < w) putc_bfd(&pb, ' ');			/* Right pads */
+			continue;
+#if FF_PRINT_FLOAT && FF_INTDEF == 2
+		case 'f':					/* Floating point (decimal) */
+		case 'e':					/* Floating point (e) */
+		case 'E':					/* Floating point (E) */
+			ftoa(str, va_arg(arp, double), prec, tc);	/* Make a floating point string */
+			for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad);	/* Left pads */
+			for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ;	/* Body */
+			while (j++ < w) putc_bfd(&pb, ' ');	/* Right pads */
+			continue;
+#endif
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, tc); continue;
+		}
+
+		/* Get an integer argument and put it in numeral */
+#if FF_PRINT_LLI && FF_INTDEF == 2
+		if (f & 8) {		/* long long argument? */
+			v = (QWORD)va_arg(arp, long long);
+		} else if (f & 4) {	/* long argument? */
+			v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long);
+		} else {			/* int/short/char argument */
+			v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int);
+		}
+		if (tc == 'd' && (v & 0x8000000000000000)) {	/* Negative value? */
+			v = 0 - v; f |= 1;
+		}
+#else
+		if (f & 4) {	/* long argument? */
+			v = (DWORD)va_arg(arp, long);
+		} else {		/* int/short/char argument */
+			v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int);
+		}
+		if (tc == 'd' && (v & 0x80000000)) {	/* Negative value? */
+			v = 0 - v; f |= 1;
+		}
+#endif
+		i = 0;
+		do {	/* Make an integer number string */
+			d = (char)(v % r); v /= r;
+			if (d > 9) d += (tc == 'x') ? 0x27 : 0x07;
+			str[i++] = d + '0';
+		} while (v && i < SZ_NUM_BUF);
+		if (f & 1) str[i++] = '-';	/* Sign */
+		/* Write it */
+		for (j = i; !(f & 2) && j < w; j++) {	/* Left pads */
+			putc_bfd(&pb, pad);
+		}
+		do {				/* Body */
+			putc_bfd(&pb, (TCHAR)str[--i]);
+		} while (i);
+		while (j++ < w) {	/* Right pads */
+			putc_bfd(&pb, ' ');
+		}
+	}
+
+	va_end(arp);
+
+	return putc_flush(&pb);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_STRFUNC */
+
+
+
+#if FF_CODE_PAGE == 0
+/*-----------------------------------------------------------------------*/
+/* Set Active Codepage for the Path Name                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setcp (
+	WORD cp		/* Value to be set as active code page */
+)
+{
+	static const WORD       validcp[22] = {  437,   720,   737,   771,   775,   850,   852,   855,   857,   860,   861,   862,   863,   864,   865,   866,   869,   932,   936,   949,   950, 0};
+	static const BYTE *const tables[22] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct855, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0};
+	UINT i;
+
+
+	for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ;	/* Find the code page */
+	if (validcp[i] != cp) return FR_INVALID_PARAMETER;		/* Not found? */
+
+	CodePage = cp;
+	if (cp >= 900) {	/* DBCS */
+		ExCvt = 0;
+		DbcTbl = tables[i];
+	} else {			/* SBCS */
+		ExCvt = tables[i];
+		DbcTbl = 0;
+	}
+	return FR_OK;
+}
+#endif	/* FF_CODE_PAGE == 0 */
+
diff --git a/MCUME_pico2/fatfs/source/ff.h b/MCUME_pico2/fatfs/source/ff.h
new file mode 100644
index 0000000..d88febc
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/ff.h
@@ -0,0 +1,429 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem module  R0.15                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#ifndef FF_DEFINED
+#define FF_DEFINED	80286	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ffconf.h"		/* FatFs configuration options */
+
+#if FF_DEFINED != FFCONF_DEF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+/* Integer types used for FatFs API */
+
+#if defined(_WIN32)		/* Windows VC++ (for development only) */
+#define FF_INTDEF 2
+#include <windows.h>
+typedef unsigned __int64 QWORD;
+#include <float.h>
+#define isnan(v) _isnan(v)
+#define isinf(v) (!_finite(v))
+
+#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus)	/* C99 or later */
+#define FF_INTDEF 2
+#include <stdint.h>
+typedef unsigned int	UINT;	/* int must be 16-bit or 32-bit */
+typedef unsigned char	BYTE;	/* char must be 8-bit */
+typedef uint16_t		WORD;	/* 16-bit unsigned integer */
+typedef uint32_t		DWORD;	/* 32-bit unsigned integer */
+typedef uint64_t		QWORD;	/* 64-bit unsigned integer */
+typedef WORD			WCHAR;	/* UTF-16 character type */
+
+#else  	/* Earlier than C99 */
+#define FF_INTDEF 1
+typedef unsigned int	UINT;	/* int must be 16-bit or 32-bit */
+typedef unsigned char	BYTE;	/* char must be 8-bit */
+typedef unsigned short	WORD;	/* 16-bit unsigned integer */
+typedef unsigned long	DWORD;	/* 32-bit unsigned integer */
+typedef WORD			WCHAR;	/* UTF-16 character type */
+#endif
+
+
+/* Type of file size and LBA variables */
+
+#if FF_FS_EXFAT
+#if FF_INTDEF != 2
+#error exFAT feature wants C99 or later
+#endif
+typedef QWORD FSIZE_t;
+#if FF_LBA64
+typedef QWORD LBA_t;
+#else
+typedef DWORD LBA_t;
+#endif
+#else
+#if FF_LBA64
+#error exFAT needs to be enabled when enable 64-bit LBA
+#endif
+typedef DWORD FSIZE_t;
+typedef DWORD LBA_t;
+#endif
+
+
+
+/* Type of path name strings on FatFs API (TCHAR) */
+
+#if FF_USE_LFN && FF_LFN_UNICODE == 1 	/* Unicode in UTF-16 encoding */
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2	/* Unicode in UTF-8 encoding */
+typedef char TCHAR;
+#define _T(x) u8 ## x
+#define _TEXT(x) u8 ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 3	/* Unicode in UTF-32 encoding */
+typedef DWORD TCHAR;
+#define _T(x) U ## x
+#define _TEXT(x) U ## x
+#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
+#error Wrong FF_LFN_UNICODE setting
+#else									/* ANSI/OEM code in SBCS/DBCS */
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if FF_MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition mapping table */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifndef FF_VOLUME_STRS
+extern const char* VolumeStr[FF_VOLUMES];	/* User defied volume ID */
+#endif
+#endif
+
+
+
+/* Filesystem object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* Filesystem type (0:not mounted) */
+	BYTE	pdrv;			/* Volume hosting physical drive */
+	BYTE	ldrv;			/* Logical drive number (used only when FF_FS_REENTRANT) */
+	BYTE	n_fats;			/* Number of FATs (1 or 2) */
+	BYTE	wflag;			/* win[] status (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO status (b7:disabled, b0:dirty) */
+	WORD	id;				/* Volume mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+	WORD	csize;			/* Cluster size [sectors] */
+#if FF_MAX_SS != FF_MIN_SS
+	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if FF_USE_LFN
+	WCHAR*	lfnbuf;			/* LFN working buffer */
+#endif
+#if FF_FS_EXFAT
+	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer for exFAT */
+#endif
+#if !FF_FS_READONLY
+	DWORD	last_clst;		/* Last allocated cluster */
+	DWORD	free_clst;		/* Number of free clusters */
+#endif
+#if FF_FS_RPATH
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#if FF_FS_EXFAT
+	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
+	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
+	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
+	DWORD	fsize;			/* Number of sectors per FAT */
+	LBA_t	volbase;		/* Volume base sector */
+	LBA_t	fatbase;		/* FAT base sector */
+	LBA_t	dirbase;		/* Root directory base sector (FAT12/16) or cluster (FAT32/exFAT) */
+	LBA_t	database;		/* Data base sector */
+#if FF_FS_EXFAT
+	LBA_t	bitbase;		/* Allocation bitmap base sector */
+#endif
+	LBA_t	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+
+/* Object ID and allocation information (FFOBJID) */
+
+typedef struct {
+	FATFS*	fs;				/* Pointer to the hosting volume of this object */
+	WORD	id;				/* Hosting volume's mount ID */
+	BYTE	attr;			/* Object attribute */
+	BYTE	stat;			/* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
+	DWORD	sclust;			/* Object data start cluster (0:no cluster or root directory) */
+	FSIZE_t	objsize;		/* Object size (valid when sclust != 0) */
+#if FF_FS_EXFAT
+	DWORD	n_cont;			/* Size of first fragment - 1 (valid when stat == 3) */
+	DWORD	n_frag;			/* Size of last fragment needs to be written to FAT (valid when not zero) */
+	DWORD	c_scl;			/* Containing directory start cluster (valid when sclust != 0) */
+	DWORD	c_size;			/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+	DWORD	c_ofs;			/* Offset in the containing directory (valid when file object and sclust != 0) */
+#endif
+#if FF_FS_LOCK
+	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} FFOBJID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
+	BYTE	flag;			/* File status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
+	LBA_t	sect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !FF_FS_READONLY
+	LBA_t	dir_sect;		/* Sector number containing the directory entry (not used at exFAT) */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] (not used at exFAT) */
+#endif
+#if FF_USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !FF_FS_TINY
+	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	FFOBJID	obj;			/* Object identifier */
+	DWORD	dptr;			/* Current read/write offset */
+	DWORD	clust;			/* Current cluster */
+	LBA_t	sect;			/* Current sector (0:Read operation has terminated) */
+	BYTE*	dir;			/* Pointer to the directory item in the win[] */
+	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
+#if FF_USE_LFN
+	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if FF_USE_FIND
+	const TCHAR* pat;		/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	FSIZE_t	fsize;			/* File size */
+	WORD	fdate;			/* Modified date */
+	WORD	ftime;			/* Modified time */
+	BYTE	fattrib;		/* File attribute */
+#if FF_USE_LFN
+	TCHAR	altname[FF_SFN_BUF + 1];/* Alternative file name */
+	TCHAR	fname[FF_LFN_BUF + 1];	/* Primary file name */
+#else
+	TCHAR	fname[12 + 1];	/* File name */
+#endif
+} FILINFO;
+
+
+
+/* Format parameter structure (MKFS_PARM) */
+
+typedef struct {
+	BYTE fmt;			/* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
+	BYTE n_fat;			/* Number of FATs */
+	UINT align;			/* Data area alignment (sector) */
+	UINT n_root;		/* Number of root directory entries */
+	DWORD au_size;		/* Cluster size (byte) */
+} MKFS_PARM;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs Module Application Interface                           */
+/*--------------------------------------------------------------*/
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate the file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);	/* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work);		/* Divide a physical drive into some partitions */
+FRESULT f_setcp (WORD cp);											/* Set current code page */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+/* Some API fucntions are implemented as macro */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+#define f_unmount(path) f_mount(0, path, 0)
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional Functions                                         */
+/*--------------------------------------------------------------*/
+
+/* RTC function (provided by user) */
+#if !FF_FS_READONLY && !FF_FS_NORTC
+DWORD get_fattime (void);	/* Get current time */
+#endif
+
+
+/* LFN support functions (defined in ffunicode.c) */
+
+#if FF_USE_LFN >= 1
+WCHAR ff_oem2uni (WCHAR oem, WORD cp);	/* OEM code to Unicode conversion */
+WCHAR ff_uni2oem (DWORD uni, WORD cp);	/* Unicode to OEM code conversion */
+DWORD ff_wtoupper (DWORD uni);			/* Unicode upper-case conversion */
+#endif
+
+
+/* O/S dependent functions (samples available in ffsystem.c) */
+
+#if FF_USE_LFN == 3		/* Dynamic memory allocation */
+void* ff_memalloc (UINT msize);		/* Allocate memory block */
+void ff_memfree (void* mblock);		/* Free memory block */
+#endif
+#if FF_FS_REENTRANT	/* Sync functions */
+int ff_mutex_create (int vol);		/* Create a sync object */
+void ff_mutex_delete (int vol);		/* Delete a sync object */
+int ff_mutex_take (int vol);		/* Lock sync object */
+void ff_mutex_give (int vol);		/* Unlock sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and Offset Address                                     */
+/*--------------------------------------------------------------*/
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define	FA_READ				0x01
+#define	FA_WRITE			0x02
+#define	FA_OPEN_EXISTING	0x00
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define	FA_OPEN_APPEND		0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT		0x01
+#define FM_FAT32	0x02
+#define FM_EXFAT	0x04
+#define FM_ANY		0x07
+#define FM_SFD		0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+#define FS_EXFAT	4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FF_DEFINED */
diff --git a/MCUME_pico2/fatfs/source/ffsystem.c b/MCUME_pico2/fatfs/source/ffsystem.c
new file mode 100644
index 0000000..2657fe2
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/ffsystem.c
@@ -0,0 +1,208 @@
+/*------------------------------------------------------------------------*/
+/* A Sample Code of User Provided OS Dependent Functions for FatFs        */
+/*------------------------------------------------------------------------*/
+
+#include "ff.h"
+
+
+#if FF_USE_LFN == 3	/* Use dynamic memory allocation */
+
+/*------------------------------------------------------------------------*/
+/* Allocate/Free a Memory Block                                           */
+/*------------------------------------------------------------------------*/
+
+#include <stdlib.h>		/* with POSIX API */
+
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block (null if not enough core) */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return malloc((size_t)msize);	/* Allocate a new memory block */
+}
+
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free (no effect if null) */
+)
+{
+	free(mblock);	/* Free the memory block */
+}
+
+#endif
+
+
+
+
+#if FF_FS_REENTRANT	/* Mutal exclusion */
+/*------------------------------------------------------------------------*/
+/* Definitions of Mutex                                                   */
+/*------------------------------------------------------------------------*/
+
+#define OS_TYPE	0	/* 0:Win32, 1:uITRON4.0, 2:uC/OS-II, 3:FreeRTOS, 4:CMSIS-RTOS */
+
+
+#if   OS_TYPE == 0	/* Win32 */
+#include <windows.h>
+static HANDLE Mutex[FF_VOLUMES + 1];	/* Table of mutex handle */
+
+#elif OS_TYPE == 1	/* uITRON */
+#include "itron.h"
+#include "kernel.h"
+static mtxid Mutex[FF_VOLUMES + 1];		/* Table of mutex ID */
+
+#elif OS_TYPE == 2	/* uc/OS-II */
+#include "includes.h"
+static OS_EVENT *Mutex[FF_VOLUMES + 1];	/* Table of mutex pinter */
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+#include "FreeRTOS.h"
+#include "semphr.h"
+static SemaphoreHandle_t Mutex[FF_VOLUMES + 1];	/* Table of mutex handle */
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+#include "cmsis_os.h"
+static osMutexId Mutex[FF_VOLUMES + 1];	/* Table of mutex ID */
+
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* Create a Mutex                                                         */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount function to create a new mutex
+/  or semaphore for the volume. When a 0 is returned, the f_mount function
+/  fails with FR_INT_ERR.
+*/
+
+int ff_mutex_create (	/* Returns 1:Function succeeded or 0:Could not create the mutex */
+	int vol				/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	Mutex[vol] = CreateMutex(NULL, FALSE, NULL);
+	return (int)(Mutex[vol] != INVALID_HANDLE_VALUE);
+
+#elif OS_TYPE == 1	/* uITRON */
+	T_CMTX cmtx = {TA_TPRI,1};
+
+	Mutex[vol] = acre_mtx(&cmtx);
+	return (int)(Mutex[vol] > 0);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	Mutex[vol] = OSMutexCreate(0, &err);
+	return (int)(err == OS_NO_ERR);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	Mutex[vol] = xSemaphoreCreateMutex();
+	return (int)(Mutex[vol] != NULL);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexDef(cmsis_os_mutex);
+
+	Mutex[vol] = osMutexCreate(osMutex(cmsis_os_mutex));
+	return (int)(Mutex[vol] != NULL);
+
+#endif
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Mutex                                                         */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount function to delete a mutex or
+/  semaphore of the volume created with ff_mutex_create function.
+*/
+
+void ff_mutex_delete (	/* Returns 1:Function succeeded or 0:Could not delete due to an error */
+	int vol				/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	CloseHandle(Mutex[vol]);
+
+#elif OS_TYPE == 1	/* uITRON */
+	del_mtx(Mutex[vol]);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	OSMutexDel(Mutex[vol], OS_DEL_ALWAYS, &err);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	vSemaphoreDelete(Mutex[vol]);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexDelete(Mutex[vol]);
+
+#endif
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Request a Grant to Access the Volume                                   */
+/*------------------------------------------------------------------------*/
+/* This function is called on enter file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_mutex_take (	/* Returns 1:Succeeded or 0:Timeout */
+	int vol			/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	return (int)(WaitForSingleObject(Mutex[vol], FF_FS_TIMEOUT) == WAIT_OBJECT_0);
+
+#elif OS_TYPE == 1	/* uITRON */
+	return (int)(tloc_mtx(Mutex[vol], FF_FS_TIMEOUT) == E_OK);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	OSMutexPend(Mutex[vol], FF_FS_TIMEOUT, &err));
+	return (int)(err == OS_NO_ERR);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	return (int)(xSemaphoreTake(Mutex[vol], FF_FS_TIMEOUT) == pdTRUE);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	return (int)(osMutexWait(Mutex[vol], FF_FS_TIMEOUT) == osOK);
+
+#endif
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release a Grant to Access the Volume                                   */
+/*------------------------------------------------------------------------*/
+/* This function is called on leave file functions to unlock the volume.
+*/
+
+void ff_mutex_give (
+	int vol			/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	ReleaseMutex(Mutex[vol]);
+
+#elif OS_TYPE == 1	/* uITRON */
+	unl_mtx(Mutex[vol]);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OSMutexPost(Mutex[vol]);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	xSemaphoreGive(Mutex[vol]);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexRelease(Mutex[vol]);
+
+#endif
+}
+
+#endif	/* FF_FS_REENTRANT */
+
diff --git a/MCUME_pico2/fatfs/source/ffunicode.c b/MCUME_pico2/fatfs/source/ffunicode.c
new file mode 100644
index 0000000..54ad526
--- /dev/null
+++ b/MCUME_pico2/fatfs/source/ffunicode.c
@@ -0,0 +1,15593 @@
+/*------------------------------------------------------------------------*/
+/* Unicode Handling Functions for FatFs R0.13 and Later                   */
+/*------------------------------------------------------------------------*/
+/* This module will occupy a huge memory in the .rodata section when the  */
+/* FatFs is configured for LFN with DBCS. If the system has a Unicode     */
+/* library for the code conversion, this module should be modified to use */
+/* it to avoid silly memory consumption.                                  */
+/*------------------------------------------------------------------------*/
+/*
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+*/
+
+
+#include "ff.h"
+
+#if FF_USE_LFN != 0	/* This module will be blanked if in non-LFN configuration */
+
+#define MERGE2(a, b) a ## b
+#define CVTBL(tbl, cp) MERGE2(tbl, cp)
+
+
+/*------------------------------------------------------------------------*/
+/* Code Conversion Tables                                                 */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0	/* Japanese */
+static const WCHAR uni2oem932[] = {	/* Unicode --> Shift_JIS pairs */
+	0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D,	0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180,
+	0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2,	0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6,
+	0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA,	0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE,
+	0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2,	0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6,
+	0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2,	0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6,
+	0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA,	0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE,
+	0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2,	0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6,
+	0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442,	0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447,
+	0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B,	0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F,
+	0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453,	0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457,
+	0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B,	0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F,
+	0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472,	0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477,
+	0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B,	0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480,
+	0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484,	0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488,
+	0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C,	0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490,
+	0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C,	0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168,
+	0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163,	0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6,
+	0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0,	0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757,
+	0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B,	0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41,
+	0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45,	0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49,
+	0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB,	0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD,
+	0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9,	0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187,
+	0x221F, 0x8798, 0x2220, 0x81DA, 0x2225, 0x8161, 0x2227, 0x81C8,	0x2228, 0x81C9, 0x2229, 0x81BF, 0x222A, 0x81BE, 0x222B, 0x81E7,
+	0x222C, 0x81E8, 0x222E, 0x8793, 0x2234, 0x8188, 0x2235, 0x81E6,	0x223D, 0x81E4, 0x2252, 0x81E0, 0x2260, 0x8182, 0x2261, 0x81DF,
+	0x2266, 0x8185, 0x2267, 0x8186, 0x226A, 0x81E1, 0x226B, 0x81E2,	0x2282, 0x81BC, 0x2283, 0x81BD, 0x2286, 0x81BA, 0x2287, 0x81BB,
+	0x22A5, 0x81DB, 0x22BF, 0x8799, 0x2312, 0x81DC, 0x2460, 0x8740,	0x2461, 0x8741, 0x2462, 0x8742, 0x2463, 0x8743, 0x2464, 0x8744,
+	0x2465, 0x8745, 0x2466, 0x8746, 0x2467, 0x8747, 0x2468, 0x8748,	0x2469, 0x8749, 0x246A, 0x874A, 0x246B, 0x874B, 0x246C, 0x874C,
+	0x246D, 0x874D, 0x246E, 0x874E, 0x246F, 0x874F, 0x2470, 0x8750,	0x2471, 0x8751, 0x2472, 0x8752, 0x2473, 0x8753, 0x2500, 0x849F,
+	0x2501, 0x84AA, 0x2502, 0x84A0, 0x2503, 0x84AB, 0x250C, 0x84A1,	0x250F, 0x84AC, 0x2510, 0x84A2, 0x2513, 0x84AD, 0x2514, 0x84A4,
+	0x2517, 0x84AF, 0x2518, 0x84A3, 0x251B, 0x84AE, 0x251C, 0x84A5,	0x251D, 0x84BA, 0x2520, 0x84B5, 0x2523, 0x84B0, 0x2524, 0x84A7,
+	0x2525, 0x84BC, 0x2528, 0x84B7, 0x252B, 0x84B2, 0x252C, 0x84A6,	0x252F, 0x84B6, 0x2530, 0x84BB, 0x2533, 0x84B1, 0x2534, 0x84A8,
+	0x2537, 0x84B8, 0x2538, 0x84BD, 0x253B, 0x84B3, 0x253C, 0x84A9,	0x253F, 0x84B9, 0x2542, 0x84BE, 0x254B, 0x84B4, 0x25A0, 0x81A1,
+	0x25A1, 0x81A0, 0x25B2, 0x81A3, 0x25B3, 0x81A2, 0x25BC, 0x81A5,	0x25BD, 0x81A4, 0x25C6, 0x819F, 0x25C7, 0x819E, 0x25CB, 0x819B,
+	0x25CE, 0x819D, 0x25CF, 0x819C, 0x25EF, 0x81FC, 0x2605, 0x819A,	0x2606, 0x8199, 0x2640, 0x818A, 0x2642, 0x8189, 0x266A, 0x81F4,
+	0x266D, 0x81F3, 0x266F, 0x81F2, 0x3000, 0x8140, 0x3001, 0x8141,	0x3002, 0x8142, 0x3003, 0x8156, 0x3005, 0x8158, 0x3006, 0x8159,
+	0x3007, 0x815A, 0x3008, 0x8171, 0x3009, 0x8172, 0x300A, 0x8173,	0x300B, 0x8174, 0x300C, 0x8175, 0x300D, 0x8176, 0x300E, 0x8177,
+	0x300F, 0x8178, 0x3010, 0x8179, 0x3011, 0x817A, 0x3012, 0x81A7,	0x3013, 0x81AC, 0x3014, 0x816B, 0x3015, 0x816C, 0x301D, 0x8780,
+	0x301F, 0x8781, 0x3041, 0x829F, 0x3042, 0x82A0, 0x3043, 0x82A1,	0x3044, 0x82A2, 0x3045, 0x82A3, 0x3046, 0x82A4, 0x3047, 0x82A5,
+	0x3048, 0x82A6, 0x3049, 0x82A7, 0x304A, 0x82A8, 0x304B, 0x82A9,	0x304C, 0x82AA, 0x304D, 0x82AB, 0x304E, 0x82AC, 0x304F, 0x82AD,
+	0x3050, 0x82AE, 0x3051, 0x82AF, 0x3052, 0x82B0, 0x3053, 0x82B1,	0x3054, 0x82B2, 0x3055, 0x82B3, 0x3056, 0x82B4, 0x3057, 0x82B5,
+	0x3058, 0x82B6, 0x3059, 0x82B7, 0x305A, 0x82B8, 0x305B, 0x82B9,	0x305C, 0x82BA, 0x305D, 0x82BB, 0x305E, 0x82BC, 0x305F, 0x82BD,
+	0x3060, 0x82BE, 0x3061, 0x82BF, 0x3062, 0x82C0, 0x3063, 0x82C1,	0x3064, 0x82C2, 0x3065, 0x82C3, 0x3066, 0x82C4, 0x3067, 0x82C5,
+	0x3068, 0x82C6, 0x3069, 0x82C7, 0x306A, 0x82C8, 0x306B, 0x82C9,	0x306C, 0x82CA, 0x306D, 0x82CB, 0x306E, 0x82CC, 0x306F, 0x82CD,
+	0x3070, 0x82CE, 0x3071, 0x82CF, 0x3072, 0x82D0, 0x3073, 0x82D1,	0x3074, 0x82D2, 0x3075, 0x82D3, 0x3076, 0x82D4, 0x3077, 0x82D5,
+	0x3078, 0x82D6, 0x3079, 0x82D7, 0x307A, 0x82D8, 0x307B, 0x82D9,	0x307C, 0x82DA, 0x307D, 0x82DB, 0x307E, 0x82DC, 0x307F, 0x82DD,
+	0x3080, 0x82DE, 0x3081, 0x82DF, 0x3082, 0x82E0, 0x3083, 0x82E1,	0x3084, 0x82E2, 0x3085, 0x82E3, 0x3086, 0x82E4, 0x3087, 0x82E5,
+	0x3088, 0x82E6, 0x3089, 0x82E7, 0x308A, 0x82E8, 0x308B, 0x82E9,	0x308C, 0x82EA, 0x308D, 0x82EB, 0x308E, 0x82EC, 0x308F, 0x82ED,
+	0x3090, 0x82EE, 0x3091, 0x82EF, 0x3092, 0x82F0, 0x3093, 0x82F1,	0x309B, 0x814A, 0x309C, 0x814B, 0x309D, 0x8154, 0x309E, 0x8155,
+	0x30A1, 0x8340, 0x30A2, 0x8341, 0x30A3, 0x8342, 0x30A4, 0x8343,	0x30A5, 0x8344, 0x30A6, 0x8345, 0x30A7, 0x8346, 0x30A8, 0x8347,
+	0x30A9, 0x8348, 0x30AA, 0x8349, 0x30AB, 0x834A, 0x30AC, 0x834B,	0x30AD, 0x834C, 0x30AE, 0x834D, 0x30AF, 0x834E, 0x30B0, 0x834F,
+	0x30B1, 0x8350, 0x30B2, 0x8351, 0x30B3, 0x8352, 0x30B4, 0x8353,	0x30B5, 0x8354, 0x30B6, 0x8355, 0x30B7, 0x8356, 0x30B8, 0x8357,
+	0x30B9, 0x8358, 0x30BA, 0x8359, 0x30BB, 0x835A, 0x30BC, 0x835B,	0x30BD, 0x835C, 0x30BE, 0x835D, 0x30BF, 0x835E, 0x30C0, 0x835F,
+	0x30C1, 0x8360, 0x30C2, 0x8361, 0x30C3, 0x8362, 0x30C4, 0x8363,	0x30C5, 0x8364, 0x30C6, 0x8365, 0x30C7, 0x8366, 0x30C8, 0x8367,
+	0x30C9, 0x8368, 0x30CA, 0x8369, 0x30CB, 0x836A, 0x30CC, 0x836B,	0x30CD, 0x836C, 0x30CE, 0x836D, 0x30CF, 0x836E, 0x30D0, 0x836F,
+	0x30D1, 0x8370, 0x30D2, 0x8371, 0x30D3, 0x8372, 0x30D4, 0x8373,	0x30D5, 0x8374, 0x30D6, 0x8375, 0x30D7, 0x8376, 0x30D8, 0x8377,
+	0x30D9, 0x8378, 0x30DA, 0x8379, 0x30DB, 0x837A, 0x30DC, 0x837B,	0x30DD, 0x837C, 0x30DE, 0x837D, 0x30DF, 0x837E, 0x30E0, 0x8380,
+	0x30E1, 0x8381, 0x30E2, 0x8382, 0x30E3, 0x8383, 0x30E4, 0x8384,	0x30E5, 0x8385, 0x30E6, 0x8386, 0x30E7, 0x8387, 0x30E8, 0x8388,
+	0x30E9, 0x8389, 0x30EA, 0x838A, 0x30EB, 0x838B, 0x30EC, 0x838C,	0x30ED, 0x838D, 0x30EE, 0x838E, 0x30EF, 0x838F, 0x30F0, 0x8390,
+	0x30F1, 0x8391, 0x30F2, 0x8392, 0x30F3, 0x8393, 0x30F4, 0x8394,	0x30F5, 0x8395, 0x30F6, 0x8396, 0x30FB, 0x8145, 0x30FC, 0x815B,
+	0x30FD, 0x8152, 0x30FE, 0x8153, 0x3231, 0x878A, 0x3232, 0x878B,	0x3239, 0x878C, 0x32A4, 0x8785, 0x32A5, 0x8786, 0x32A6, 0x8787,
+	0x32A7, 0x8788, 0x32A8, 0x8789, 0x3303, 0x8765, 0x330D, 0x8769,	0x3314, 0x8760, 0x3318, 0x8763, 0x3322, 0x8761, 0x3323, 0x876B,
+	0x3326, 0x876A, 0x3327, 0x8764, 0x332B, 0x876C, 0x3336, 0x8766,	0x333B, 0x876E, 0x3349, 0x875F, 0x334A, 0x876D, 0x334D, 0x8762,
+	0x3351, 0x8767, 0x3357, 0x8768, 0x337B, 0x877E, 0x337C, 0x878F,	0x337D, 0x878E, 0x337E, 0x878D, 0x338E, 0x8772, 0x338F, 0x8773,
+	0x339C, 0x876F, 0x339D, 0x8770, 0x339E, 0x8771, 0x33A1, 0x8775,	0x33C4, 0x8774, 0x33CD, 0x8783, 0x4E00, 0x88EA, 0x4E01, 0x929A,
+	0x4E03, 0x8EB5, 0x4E07, 0x969C, 0x4E08, 0x8FE4, 0x4E09, 0x8E4F,	0x4E0A, 0x8FE3, 0x4E0B, 0x89BA, 0x4E0D, 0x9573, 0x4E0E, 0x975E,
+	0x4E10, 0x98A0, 0x4E11, 0x894E, 0x4E14, 0x8A8E, 0x4E15, 0x98A1,	0x4E16, 0x90A2, 0x4E17, 0x99C0, 0x4E18, 0x8B75, 0x4E19, 0x95B8,
+	0x4E1E, 0x8FE5, 0x4E21, 0x97BC, 0x4E26, 0x95C0, 0x4E28, 0xFA68,	0x4E2A, 0x98A2, 0x4E2D, 0x9286, 0x4E31, 0x98A3, 0x4E32, 0x8BF8,
+	0x4E36, 0x98A4, 0x4E38, 0x8ADB, 0x4E39, 0x924F, 0x4E3B, 0x8EE5,	0x4E3C, 0x98A5, 0x4E3F, 0x98A6, 0x4E42, 0x98A7, 0x4E43, 0x9454,
+	0x4E45, 0x8B76, 0x4E4B, 0x9456, 0x4E4D, 0x93E1, 0x4E4E, 0x8CC1,	0x4E4F, 0x9652, 0x4E55, 0xE568, 0x4E56, 0x98A8, 0x4E57, 0x8FE6,
+	0x4E58, 0x98A9, 0x4E59, 0x89B3, 0x4E5D, 0x8BE3, 0x4E5E, 0x8CEE,	0x4E5F, 0x96E7, 0x4E62, 0x9BA4, 0x4E71, 0x9790, 0x4E73, 0x93FB,
+	0x4E7E, 0x8AA3, 0x4E80, 0x8B54, 0x4E82, 0x98AA, 0x4E85, 0x98AB,	0x4E86, 0x97B9, 0x4E88, 0x975C, 0x4E89, 0x9188, 0x4E8A, 0x98AD,
+	0x4E8B, 0x8E96, 0x4E8C, 0x93F1, 0x4E8E, 0x98B0, 0x4E91, 0x895D,	0x4E92, 0x8CDD, 0x4E94, 0x8CDC, 0x4E95, 0x88E4, 0x4E98, 0x986A,
+	0x4E99, 0x9869, 0x4E9B, 0x8DB1, 0x4E9C, 0x889F, 0x4E9E, 0x98B1,	0x4E9F, 0x98B2, 0x4EA0, 0x98B3, 0x4EA1, 0x9653, 0x4EA2, 0x98B4,
+	0x4EA4, 0x8CF0, 0x4EA5, 0x88E5, 0x4EA6, 0x9692, 0x4EA8, 0x8B9C,	0x4EAB, 0x8B9D, 0x4EAC, 0x8B9E, 0x4EAD, 0x92E0, 0x4EAE, 0x97BA,
+	0x4EB0, 0x98B5, 0x4EB3, 0x98B6, 0x4EB6, 0x98B7, 0x4EBA, 0x906C,	0x4EC0, 0x8F59, 0x4EC1, 0x906D, 0x4EC2, 0x98BC, 0x4EC4, 0x98BA,
+	0x4EC6, 0x98BB, 0x4EC7, 0x8B77, 0x4ECA, 0x8DA1, 0x4ECB, 0x89EE,	0x4ECD, 0x98B9, 0x4ECE, 0x98B8, 0x4ECF, 0x95A7, 0x4ED4, 0x8E65,
+	0x4ED5, 0x8E64, 0x4ED6, 0x91BC, 0x4ED7, 0x98BD, 0x4ED8, 0x9574,	0x4ED9, 0x90E5, 0x4EDD, 0x8157, 0x4EDE, 0x98BE, 0x4EDF, 0x98C0,
+	0x4EE1, 0xFA69, 0x4EE3, 0x91E3, 0x4EE4, 0x97DF, 0x4EE5, 0x88C8,	0x4EED, 0x98BF, 0x4EEE, 0x89BC, 0x4EF0, 0x8BC2, 0x4EF2, 0x9287,
+	0x4EF6, 0x8C8F, 0x4EF7, 0x98C1, 0x4EFB, 0x9443, 0x4EFC, 0xFA6A,	0x4F00, 0xFA6B, 0x4F01, 0x8AE9, 0x4F03, 0xFA6C, 0x4F09, 0x98C2,
+	0x4F0A, 0x88C9, 0x4F0D, 0x8CDE, 0x4F0E, 0x8AEA, 0x4F0F, 0x959A,	0x4F10, 0x94B0, 0x4F11, 0x8B78, 0x4F1A, 0x89EF, 0x4F1C, 0x98E5,
+	0x4F1D, 0x9360, 0x4F2F, 0x948C, 0x4F30, 0x98C4, 0x4F34, 0x94BA,	0x4F36, 0x97E0, 0x4F38, 0x904C, 0x4F39, 0xFA6D, 0x4F3A, 0x8E66,
+	0x4F3C, 0x8E97, 0x4F3D, 0x89BE, 0x4F43, 0x92CF, 0x4F46, 0x9241,	0x4F47, 0x98C8, 0x4F4D, 0x88CA, 0x4F4E, 0x92E1, 0x4F4F, 0x8F5A,
+	0x4F50, 0x8DB2, 0x4F51, 0x9743, 0x4F53, 0x91CC, 0x4F55, 0x89BD,	0x4F56, 0xFA6E, 0x4F57, 0x98C7, 0x4F59, 0x975D, 0x4F5A, 0x98C3,
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+	0x97AB, 0xE691, 0x97AD, 0x95DA, 0x97B3, 0xE8E3, 0x97B4, 0xE8E4,	0x97C3, 0xE8E5, 0x97C6, 0xE8E6, 0x97C8, 0xE8E7, 0x97CB, 0xE8E8,
+	0x97D3, 0x8AD8, 0x97DC, 0xE8E9, 0x97ED, 0xE8EA, 0x97EE, 0x9442,	0x97F2, 0xE8EC, 0x97F3, 0x89B9, 0x97F5, 0xE8EF, 0x97F6, 0xE8EE,
+	0x97FB, 0x8943, 0x97FF, 0x8BBF, 0x9801, 0x95C5, 0x9802, 0x92B8,	0x9803, 0x8DA0, 0x9805, 0x8D80, 0x9806, 0x8F87, 0x9808, 0x907B,
+	0x980C, 0xE8F1, 0x980F, 0xE8F0, 0x9810, 0x9761, 0x9811, 0x8AE6,	0x9812, 0x94D0, 0x9813, 0x93DA, 0x9817, 0x909C, 0x9818, 0x97CC,
+	0x981A, 0x8C7A, 0x9821, 0xE8F4, 0x9824, 0xE8F3, 0x982C, 0x966A,	0x982D, 0x93AA, 0x9834, 0x896F, 0x9837, 0xE8F5, 0x9838, 0xE8F2,
+	0x983B, 0x9570, 0x983C, 0x978A, 0x983D, 0xE8F6, 0x9846, 0xE8F7,	0x984B, 0xE8F9, 0x984C, 0x91E8, 0x984D, 0x8A7A, 0x984E, 0x8A7B,
+	0x984F, 0xE8F8, 0x9854, 0x8AE7, 0x9855, 0x8CB0, 0x9857, 0xFBF4,	0x9858, 0x8AE8, 0x985B, 0x935E, 0x985E, 0x97DE, 0x9865, 0xFBF5,
+	0x9867, 0x8CDA, 0x986B, 0xE8FA, 0x986F, 0xE8FB, 0x9870, 0xE8FC,	0x9871, 0xE940, 0x9873, 0xE942, 0x9874, 0xE941, 0x98A8, 0x9597,
+	0x98AA, 0xE943, 0x98AF, 0xE944, 0x98B1, 0xE945, 0x98B6, 0xE946,	0x98C3, 0xE948, 0x98C4, 0xE947, 0x98C6, 0xE949, 0x98DB, 0x94F2,
+	0x98DC, 0xE3CA, 0x98DF, 0x9048, 0x98E2, 0x8B51, 0x98E9, 0xE94A,	0x98EB, 0xE94B, 0x98ED, 0x99AA, 0x98EE, 0x9F5A, 0x98EF, 0x94D1,
+	0x98F2, 0x88F9, 0x98F4, 0x88B9, 0x98FC, 0x8E94, 0x98FD, 0x964F,	0x98FE, 0x8FFC, 0x9903, 0xE94C, 0x9905, 0x96DD, 0x9909, 0xE94D,
+	0x990A, 0x977B, 0x990C, 0x8961, 0x9910, 0x8E60, 0x9912, 0xE94E,	0x9913, 0x89EC, 0x9914, 0xE94F, 0x9918, 0xE950, 0x991D, 0xE952,
+	0x991E, 0xE953, 0x9920, 0xE955, 0x9921, 0xE951, 0x9924, 0xE954,	0x9927, 0xFBF8, 0x9928, 0x8AD9, 0x992C, 0xE956, 0x992E, 0xE957,
+	0x993D, 0xE958, 0x993E, 0xE959, 0x9942, 0xE95A, 0x9945, 0xE95C,	0x9949, 0xE95B, 0x994B, 0xE95E, 0x994C, 0xE961, 0x9950, 0xE95D,
+	0x9951, 0xE95F, 0x9952, 0xE960, 0x9955, 0xE962, 0x9957, 0x8BC0,	0x9996, 0x8EF1, 0x9997, 0xE963, 0x9998, 0xE964, 0x9999, 0x8D81,
+	0x999E, 0xFBFA, 0x99A5, 0xE965, 0x99A8, 0x8A5D, 0x99AC, 0x946E,	0x99AD, 0xE966, 0x99AE, 0xE967, 0x99B3, 0x9279, 0x99B4, 0x93E9,
+	0x99BC, 0xE968, 0x99C1, 0x949D, 0x99C4, 0x91CA, 0x99C5, 0x8977,	0x99C6, 0x8BEC, 0x99C8, 0x8BED, 0x99D0, 0x9293, 0x99D1, 0xE96D,
+	0x99D2, 0x8BEE, 0x99D5, 0x89ED, 0x99D8, 0xE96C, 0x99DB, 0xE96A,	0x99DD, 0xE96B, 0x99DF, 0xE969, 0x99E2, 0xE977, 0x99ED, 0xE96E,
+	0x99EE, 0xE96F, 0x99F1, 0xE970, 0x99F2, 0xE971, 0x99F8, 0xE973,	0x99FB, 0xE972, 0x99FF, 0x8F78, 0x9A01, 0xE974, 0x9A05, 0xE976,
+	0x9A0E, 0x8B52, 0x9A0F, 0xE975, 0x9A12, 0x919B, 0x9A13, 0x8CB1,	0x9A19, 0xE978, 0x9A28, 0x91CB, 0x9A2B, 0xE979, 0x9A30, 0x93AB,
+	0x9A37, 0xE97A, 0x9A3E, 0xE980, 0x9A40, 0xE97D, 0x9A42, 0xE97C,	0x9A43, 0xE97E, 0x9A45, 0xE97B, 0x9A4D, 0xE982, 0x9A4E, 0xFBFB,
+	0x9A55, 0xE981, 0x9A57, 0xE984, 0x9A5A, 0x8BC1, 0x9A5B, 0xE983,	0x9A5F, 0xE985, 0x9A62, 0xE986, 0x9A64, 0xE988, 0x9A65, 0xE987,
+	0x9A69, 0xE989, 0x9A6A, 0xE98B, 0x9A6B, 0xE98A, 0x9AA8, 0x8D9C,	0x9AAD, 0xE98C, 0x9AB0, 0xE98D, 0x9AB8, 0x8A5B, 0x9ABC, 0xE98E,
+	0x9AC0, 0xE98F, 0x9AC4, 0x9091, 0x9ACF, 0xE990, 0x9AD1, 0xE991,	0x9AD3, 0xE992, 0x9AD4, 0xE993, 0x9AD8, 0x8D82, 0x9AD9, 0xFBFC,
+	0x9ADC, 0xFC40, 0x9ADE, 0xE994, 0x9ADF, 0xE995, 0x9AE2, 0xE996,	0x9AE3, 0xE997, 0x9AE6, 0xE998, 0x9AEA, 0x94AF, 0x9AEB, 0xE99A,
+	0x9AED, 0x9545, 0x9AEE, 0xE99B, 0x9AEF, 0xE999, 0x9AF1, 0xE99D,	0x9AF4, 0xE99C, 0x9AF7, 0xE99E, 0x9AFB, 0xE99F, 0x9B06, 0xE9A0,
+	0x9B18, 0xE9A1, 0x9B1A, 0xE9A2, 0x9B1F, 0xE9A3, 0x9B22, 0xE9A4,	0x9B23, 0xE9A5, 0x9B25, 0xE9A6, 0x9B27, 0xE9A7, 0x9B28, 0xE9A8,
+	0x9B29, 0xE9A9, 0x9B2A, 0xE9AA, 0x9B2E, 0xE9AB, 0x9B2F, 0xE9AC,	0x9B31, 0x9F54, 0x9B32, 0xE9AD, 0x9B3B, 0xE2F6, 0x9B3C, 0x8B53,
+	0x9B41, 0x8A40, 0x9B42, 0x8DB0, 0x9B43, 0xE9AF, 0x9B44, 0xE9AE,	0x9B45, 0x96A3, 0x9B4D, 0xE9B1, 0x9B4E, 0xE9B2, 0x9B4F, 0xE9B0,
+	0x9B51, 0xE9B3, 0x9B54, 0x9682, 0x9B58, 0xE9B4, 0x9B5A, 0x8B9B,	0x9B6F, 0x9844, 0x9B72, 0xFC42, 0x9B74, 0xE9B5, 0x9B75, 0xFC41,
+	0x9B83, 0xE9B7, 0x9B8E, 0x88BC, 0x9B8F, 0xFC43, 0x9B91, 0xE9B8,	0x9B92, 0x95A9, 0x9B93, 0xE9B6, 0x9B96, 0xE9B9, 0x9B97, 0xE9BA,
+	0x9B9F, 0xE9BB, 0x9BA0, 0xE9BC, 0x9BA8, 0xE9BD, 0x9BAA, 0x968E,	0x9BAB, 0x8E4C, 0x9BAD, 0x8DF8, 0x9BAE, 0x914E, 0x9BB1, 0xFC44,
+	0x9BB4, 0xE9BE, 0x9BB9, 0xE9C1, 0x9BBB, 0xFC45, 0x9BC0, 0xE9BF,	0x9BC6, 0xE9C2, 0x9BC9, 0x8CEF, 0x9BCA, 0xE9C0, 0x9BCF, 0xE9C3,
+	0x9BD1, 0xE9C4, 0x9BD2, 0xE9C5, 0x9BD4, 0xE9C9, 0x9BD6, 0x8E49,	0x9BDB, 0x91E2, 0x9BE1, 0xE9CA, 0x9BE2, 0xE9C7, 0x9BE3, 0xE9C6,
+	0x9BE4, 0xE9C8, 0x9BE8, 0x8C7E, 0x9BF0, 0xE9CE, 0x9BF1, 0xE9CD,	0x9BF2, 0xE9CC, 0x9BF5, 0x88B1, 0x9C00, 0xFC46, 0x9C04, 0xE9D8,
+	0x9C06, 0xE9D4, 0x9C08, 0xE9D5, 0x9C09, 0xE9D1, 0x9C0A, 0xE9D7,	0x9C0C, 0xE9D3, 0x9C0D, 0x8A82, 0x9C10, 0x986B, 0x9C12, 0xE9D6,
+	0x9C13, 0xE9D2, 0x9C14, 0xE9D0, 0x9C15, 0xE9CF, 0x9C1B, 0xE9DA,	0x9C21, 0xE9DD, 0x9C24, 0xE9DC, 0x9C25, 0xE9DB, 0x9C2D, 0x9568,
+	0x9C2E, 0xE9D9, 0x9C2F, 0x88F1, 0x9C30, 0xE9DE, 0x9C32, 0xE9E0,	0x9C39, 0x8A8F, 0x9C3A, 0xE9CB, 0x9C3B, 0x8956, 0x9C3E, 0xE9E2,
+	0x9C46, 0xE9E1, 0x9C47, 0xE9DF, 0x9C48, 0x924C, 0x9C52, 0x9690,	0x9C57, 0x97D8, 0x9C5A, 0xE9E3, 0x9C60, 0xE9E4, 0x9C67, 0xE9E5,
+	0x9C76, 0xE9E6, 0x9C78, 0xE9E7, 0x9CE5, 0x92B9, 0x9CE7, 0xE9E8,	0x9CE9, 0x94B5, 0x9CEB, 0xE9ED, 0x9CEC, 0xE9E9, 0x9CF0, 0xE9EA,
+	0x9CF3, 0x9650, 0x9CF4, 0x96C2, 0x9CF6, 0x93CE, 0x9D03, 0xE9EE,	0x9D06, 0xE9EF, 0x9D07, 0x93BC, 0x9D08, 0xE9EC, 0x9D09, 0xE9EB,
+	0x9D0E, 0x89A8, 0x9D12, 0xE9F7, 0x9D15, 0xE9F6, 0x9D1B, 0x8995,	0x9D1F, 0xE9F4, 0x9D23, 0xE9F3, 0x9D26, 0xE9F1, 0x9D28, 0x8A9B,
+	0x9D2A, 0xE9F0, 0x9D2B, 0x8EB0, 0x9D2C, 0x89A7, 0x9D3B, 0x8D83,	0x9D3E, 0xE9FA, 0x9D3F, 0xE9F9, 0x9D41, 0xE9F8, 0x9D44, 0xE9F5,
+	0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, 0x9D51, 0xEA43,	0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, 0x9D5E, 0xEA41,
+	0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48,	0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46,
+	0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B,	0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49,
+	0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53,	0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57,
+	0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59,	0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D,
+	0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB,	0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60,
+	0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63,	0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66,
+	0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69,	0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C,
+	0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E,	0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D,
+	0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80,	0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F,
+	0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B,	0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9,
+	0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79,	0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E,
+	0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83,	0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87,
+	0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A,	0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540,
+	0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8,	0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92,
+	0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91,	0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97,
+	0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4,	0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E,
+	0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B,	0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8,
+	0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75,	0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82,
+	0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D,	0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1,
+	0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3,	0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7,
+	0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57,	0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195,
+	0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196,	0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144,
+	0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251,	0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255,
+	0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146,	0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184,
+	0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261,	0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265,
+	0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269,	0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D,
+	0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271,	0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275,
+	0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279,	0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F,
+	0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282,	0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286,
+	0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A,	0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E,
+	0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292,	0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296,
+	0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A,	0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160,
+	0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4,	0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8,
+	0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC,	0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0,
+	0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4,	0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8,
+	0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC,	0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0,
+	0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4,	0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8,
+	0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC,	0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0,
+	0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4,	0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8,
+	0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC,	0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191,
+	0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55,	0xFFE5, 0x818F, 0, 0
+};
+
+static const WCHAR oem2uni932[] = {	/* Shift_JIS --> Unicode pairs */
+	0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64,	0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68,
+	0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C,	0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70,
+	0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74,	0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78,
+	0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C,	0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80,
+	0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84,	0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88,
+	0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C,	0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90,
+	0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94,	0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98,
+	0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C,	0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000,
+	0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E,	0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F,
+	0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4,	0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3,
+	0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D,	0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005,
+	0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015,	0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E,
+	0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025,	0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D,
+	0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015,	0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D,
+	0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B,	0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F,
+	0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D,	0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D,
+	0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266,	0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642,
+	0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033,	0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0,
+	0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06,	0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606,
+	0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE,	0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0,
+	0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC,	0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190,
+	0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208,	0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282,
+	0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227,	0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4,
+	0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5,	0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261,
+	0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A,	0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B,
+	0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F,	0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021,
+	0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11,	0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15,
+	0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19,	0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24,
+	0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28,	0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C,
+	0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30,	0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34,
+	0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38,	0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42,
+	0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46,	0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A,
+	0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E,	0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52,
+	0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56,	0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A,
+	0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044,	0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048,
+	0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C,	0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050,
+	0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054,	0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058,
+	0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C,	0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060,
+	0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064,	0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068,
+	0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C,	0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070,
+	0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074,	0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078,
+	0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C,	0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080,
+	0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084,	0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088,
+	0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C,	0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090,
+	0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1,	0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5,
+	0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 0x30A8, 0x8348, 0x30A9,	0x8349, 0x30AA, 0x834A, 0x30AB, 0x834B, 0x30AC, 0x834C, 0x30AD,
+	0x834D, 0x30AE, 0x834E, 0x30AF, 0x834F, 0x30B0, 0x8350, 0x30B1,	0x8351, 0x30B2, 0x8352, 0x30B3, 0x8353, 0x30B4, 0x8354, 0x30B5,
+	0x8355, 0x30B6, 0x8356, 0x30B7, 0x8357, 0x30B8, 0x8358, 0x30B9,	0x8359, 0x30BA, 0x835A, 0x30BB, 0x835B, 0x30BC, 0x835C, 0x30BD,
+	0x835D, 0x30BE, 0x835E, 0x30BF, 0x835F, 0x30C0, 0x8360, 0x30C1,	0x8361, 0x30C2, 0x8362, 0x30C3, 0x8363, 0x30C4, 0x8364, 0x30C5,
+	0x8365, 0x30C6, 0x8366, 0x30C7, 0x8367, 0x30C8, 0x8368, 0x30C9,	0x8369, 0x30CA, 0x836A, 0x30CB, 0x836B, 0x30CC, 0x836C, 0x30CD,
+	0x836D, 0x30CE, 0x836E, 0x30CF, 0x836F, 0x30D0, 0x8370, 0x30D1,	0x8371, 0x30D2, 0x8372, 0x30D3, 0x8373, 0x30D4, 0x8374, 0x30D5,
+	0x8375, 0x30D6, 0x8376, 0x30D7, 0x8377, 0x30D8, 0x8378, 0x30D9,	0x8379, 0x30DA, 0x837A, 0x30DB, 0x837B, 0x30DC, 0x837C, 0x30DD,
+	0x837D, 0x30DE, 0x837E, 0x30DF, 0x8380, 0x30E0, 0x8381, 0x30E1,	0x8382, 0x30E2, 0x8383, 0x30E3, 0x8384, 0x30E4, 0x8385, 0x30E5,
+	0x8386, 0x30E6, 0x8387, 0x30E7, 0x8388, 0x30E8, 0x8389, 0x30E9,	0x838A, 0x30EA, 0x838B, 0x30EB, 0x838C, 0x30EC, 0x838D, 0x30ED,
+	0x838E, 0x30EE, 0x838F, 0x30EF, 0x8390, 0x30F0, 0x8391, 0x30F1,	0x8392, 0x30F2, 0x8393, 0x30F3, 0x8394, 0x30F4, 0x8395, 0x30F5,
+	0x8396, 0x30F6, 0x839F, 0x0391, 0x83A0, 0x0392, 0x83A1, 0x0393,	0x83A2, 0x0394, 0x83A3, 0x0395, 0x83A4, 0x0396, 0x83A5, 0x0397,
+	0x83A6, 0x0398, 0x83A7, 0x0399, 0x83A8, 0x039A, 0x83A9, 0x039B,	0x83AA, 0x039C, 0x83AB, 0x039D, 0x83AC, 0x039E, 0x83AD, 0x039F,
+	0x83AE, 0x03A0, 0x83AF, 0x03A1, 0x83B0, 0x03A3, 0x83B1, 0x03A4,	0x83B2, 0x03A5, 0x83B3, 0x03A6, 0x83B4, 0x03A7, 0x83B5, 0x03A8,
+	0x83B6, 0x03A9, 0x83BF, 0x03B1, 0x83C0, 0x03B2, 0x83C1, 0x03B3,	0x83C2, 0x03B4, 0x83C3, 0x03B5, 0x83C4, 0x03B6, 0x83C5, 0x03B7,
+	0x83C6, 0x03B8, 0x83C7, 0x03B9, 0x83C8, 0x03BA, 0x83C9, 0x03BB,	0x83CA, 0x03BC, 0x83CB, 0x03BD, 0x83CC, 0x03BE, 0x83CD, 0x03BF,
+	0x83CE, 0x03C0, 0x83CF, 0x03C1, 0x83D0, 0x03C3, 0x83D1, 0x03C4,	0x83D2, 0x03C5, 0x83D3, 0x03C6, 0x83D4, 0x03C7, 0x83D5, 0x03C8,
+	0x83D6, 0x03C9, 0x8440, 0x0410, 0x8441, 0x0411, 0x8442, 0x0412,	0x8443, 0x0413, 0x8444, 0x0414, 0x8445, 0x0415, 0x8446, 0x0401,
+	0x8447, 0x0416, 0x8448, 0x0417, 0x8449, 0x0418, 0x844A, 0x0419,	0x844B, 0x041A, 0x844C, 0x041B, 0x844D, 0x041C, 0x844E, 0x041D,
+	0x844F, 0x041E, 0x8450, 0x041F, 0x8451, 0x0420, 0x8452, 0x0421,	0x8453, 0x0422, 0x8454, 0x0423, 0x8455, 0x0424, 0x8456, 0x0425,
+	0x8457, 0x0426, 0x8458, 0x0427, 0x8459, 0x0428, 0x845A, 0x0429,	0x845B, 0x042A, 0x845C, 0x042B, 0x845D, 0x042C, 0x845E, 0x042D,
+	0x845F, 0x042E, 0x8460, 0x042F, 0x8470, 0x0430, 0x8471, 0x0431,	0x8472, 0x0432, 0x8473, 0x0433, 0x8474, 0x0434, 0x8475, 0x0435,
+	0x8476, 0x0451, 0x8477, 0x0436, 0x8478, 0x0437, 0x8479, 0x0438,	0x847A, 0x0439, 0x847B, 0x043A, 0x847C, 0x043B, 0x847D, 0x043C,
+	0x847E, 0x043D, 0x8480, 0x043E, 0x8481, 0x043F, 0x8482, 0x0440,	0x8483, 0x0441, 0x8484, 0x0442, 0x8485, 0x0443, 0x8486, 0x0444,
+	0x8487, 0x0445, 0x8488, 0x0446, 0x8489, 0x0447, 0x848A, 0x0448,	0x848B, 0x0449, 0x848C, 0x044A, 0x848D, 0x044B, 0x848E, 0x044C,
+	0x848F, 0x044D, 0x8490, 0x044E, 0x8491, 0x044F, 0x849F, 0x2500,	0x84A0, 0x2502, 0x84A1, 0x250C, 0x84A2, 0x2510, 0x84A3, 0x2518,
+	0x84A4, 0x2514, 0x84A5, 0x251C, 0x84A6, 0x252C, 0x84A7, 0x2524,	0x84A8, 0x2534, 0x84A9, 0x253C, 0x84AA, 0x2501, 0x84AB, 0x2503,
+	0x84AC, 0x250F, 0x84AD, 0x2513, 0x84AE, 0x251B, 0x84AF, 0x2517,	0x84B0, 0x2523, 0x84B1, 0x2533, 0x84B2, 0x252B, 0x84B3, 0x253B,
+	0x84B4, 0x254B, 0x84B5, 0x2520, 0x84B6, 0x252F, 0x84B7, 0x2528,	0x84B8, 0x2537, 0x84B9, 0x253F, 0x84BA, 0x251D, 0x84BB, 0x2530,
+	0x84BC, 0x2525, 0x84BD, 0x2538, 0x84BE, 0x2542, 0x8740, 0x2460,	0x8741, 0x2461, 0x8742, 0x2462, 0x8743, 0x2463, 0x8744, 0x2464,
+	0x8745, 0x2465, 0x8746, 0x2466, 0x8747, 0x2467, 0x8748, 0x2468,	0x8749, 0x2469, 0x874A, 0x246A, 0x874B, 0x246B, 0x874C, 0x246C,
+	0x874D, 0x246D, 0x874E, 0x246E, 0x874F, 0x246F, 0x8750, 0x2470,	0x8751, 0x2471, 0x8752, 0x2472, 0x8753, 0x2473, 0x8754, 0x2160,
+	0x8755, 0x2161, 0x8756, 0x2162, 0x8757, 0x2163, 0x8758, 0x2164,	0x8759, 0x2165, 0x875A, 0x2166, 0x875B, 0x2167, 0x875C, 0x2168,
+	0x875D, 0x2169, 0x875F, 0x3349, 0x8760, 0x3314, 0x8761, 0x3322,	0x8762, 0x334D, 0x8763, 0x3318, 0x8764, 0x3327, 0x8765, 0x3303,
+	0x8766, 0x3336, 0x8767, 0x3351, 0x8768, 0x3357, 0x8769, 0x330D,	0x876A, 0x3326, 0x876B, 0x3323, 0x876C, 0x332B, 0x876D, 0x334A,
+	0x876E, 0x333B, 0x876F, 0x339C, 0x8770, 0x339D, 0x8771, 0x339E,	0x8772, 0x338E, 0x8773, 0x338F, 0x8774, 0x33C4, 0x8775, 0x33A1,
+	0x877E, 0x337B, 0x8780, 0x301D, 0x8781, 0x301F, 0x8782, 0x2116,	0x8783, 0x33CD, 0x8784, 0x2121, 0x8785, 0x32A4, 0x8786, 0x32A5,
+	0x8787, 0x32A6, 0x8788, 0x32A7, 0x8789, 0x32A8, 0x878A, 0x3231,	0x878B, 0x3232, 0x878C, 0x3239, 0x878D, 0x337E, 0x878E, 0x337D,
+	0x878F, 0x337C, 0x8793, 0x222E, 0x8794, 0x2211, 0x8798, 0x221F,	0x8799, 0x22BF, 0x889F, 0x4E9C, 0x88A0, 0x5516, 0x88A1, 0x5A03,
+	0x88A2, 0x963F, 0x88A3, 0x54C0, 0x88A4, 0x611B, 0x88A5, 0x6328,	0x88A6, 0x59F6, 0x88A7, 0x9022, 0x88A8, 0x8475, 0x88A9, 0x831C,
+	0x88AA, 0x7A50, 0x88AB, 0x60AA, 0x88AC, 0x63E1, 0x88AD, 0x6E25,	0x88AE, 0x65ED, 0x88AF, 0x8466, 0x88B0, 0x82A6, 0x88B1, 0x9BF5,
+	0x88B2, 0x6893, 0x88B3, 0x5727, 0x88B4, 0x65A1, 0x88B5, 0x6271,	0x88B6, 0x5B9B, 0x88B7, 0x59D0, 0x88B8, 0x867B, 0x88B9, 0x98F4,
+	0x88BA, 0x7D62, 0x88BB, 0x7DBE, 0x88BC, 0x9B8E, 0x88BD, 0x6216,	0x88BE, 0x7C9F, 0x88BF, 0x88B7, 0x88C0, 0x5B89, 0x88C1, 0x5EB5,
+	0x88C2, 0x6309, 0x88C3, 0x6697, 0x88C4, 0x6848, 0x88C5, 0x95C7,	0x88C6, 0x978D, 0x88C7, 0x674F, 0x88C8, 0x4EE5, 0x88C9, 0x4F0A,
+	0x88CA, 0x4F4D, 0x88CB, 0x4F9D, 0x88CC, 0x5049, 0x88CD, 0x56F2,	0x88CE, 0x5937, 0x88CF, 0x59D4, 0x88D0, 0x5A01, 0x88D1, 0x5C09,
+	0x88D2, 0x60DF, 0x88D3, 0x610F, 0x88D4, 0x6170, 0x88D5, 0x6613,	0x88D6, 0x6905, 0x88D7, 0x70BA, 0x88D8, 0x754F, 0x88D9, 0x7570,
+	0x88DA, 0x79FB, 0x88DB, 0x7DAD, 0x88DC, 0x7DEF, 0x88DD, 0x80C3,	0x88DE, 0x840E, 0x88DF, 0x8863, 0x88E0, 0x8B02, 0x88E1, 0x9055,
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+	0xE1E1, 0x77E3, 0xE1E2, 0x77EE, 0xE1E3, 0x77FC, 0xE1E4, 0x780C,	0xE1E5, 0x7812, 0xE1E6, 0x7926, 0xE1E7, 0x7820, 0xE1E8, 0x792A,
+	0xE1E9, 0x7845, 0xE1EA, 0x788E, 0xE1EB, 0x7874, 0xE1EC, 0x7886,	0xE1ED, 0x787C, 0xE1EE, 0x789A, 0xE1EF, 0x788C, 0xE1F0, 0x78A3,
+	0xE1F1, 0x78B5, 0xE1F2, 0x78AA, 0xE1F3, 0x78AF, 0xE1F4, 0x78D1,	0xE1F5, 0x78C6, 0xE1F6, 0x78CB, 0xE1F7, 0x78D4, 0xE1F8, 0x78BE,
+	0xE1F9, 0x78BC, 0xE1FA, 0x78C5, 0xE1FB, 0x78CA, 0xE1FC, 0x78EC,	0xE240, 0x78E7, 0xE241, 0x78DA, 0xE242, 0x78FD, 0xE243, 0x78F4,
+	0xE244, 0x7907, 0xE245, 0x7912, 0xE246, 0x7911, 0xE247, 0x7919,	0xE248, 0x792C, 0xE249, 0x792B, 0xE24A, 0x7940, 0xE24B, 0x7960,
+	0xE24C, 0x7957, 0xE24D, 0x795F, 0xE24E, 0x795A, 0xE24F, 0x7955,	0xE250, 0x7953, 0xE251, 0x797A, 0xE252, 0x797F, 0xE253, 0x798A,
+	0xE254, 0x799D, 0xE255, 0x79A7, 0xE256, 0x9F4B, 0xE257, 0x79AA,	0xE258, 0x79AE, 0xE259, 0x79B3, 0xE25A, 0x79B9, 0xE25B, 0x79BA,
+	0xE25C, 0x79C9, 0xE25D, 0x79D5, 0xE25E, 0x79E7, 0xE25F, 0x79EC,	0xE260, 0x79E1, 0xE261, 0x79E3, 0xE262, 0x7A08, 0xE263, 0x7A0D,
+	0xE264, 0x7A18, 0xE265, 0x7A19, 0xE266, 0x7A20, 0xE267, 0x7A1F,	0xE268, 0x7980, 0xE269, 0x7A31, 0xE26A, 0x7A3B, 0xE26B, 0x7A3E,
+	0xE26C, 0x7A37, 0xE26D, 0x7A43, 0xE26E, 0x7A57, 0xE26F, 0x7A49,	0xE270, 0x7A61, 0xE271, 0x7A62, 0xE272, 0x7A69, 0xE273, 0x9F9D,
+	0xE274, 0x7A70, 0xE275, 0x7A79, 0xE276, 0x7A7D, 0xE277, 0x7A88,	0xE278, 0x7A97, 0xE279, 0x7A95, 0xE27A, 0x7A98, 0xE27B, 0x7A96,
+	0xE27C, 0x7AA9, 0xE27D, 0x7AC8, 0xE27E, 0x7AB0, 0xE280, 0x7AB6,	0xE281, 0x7AC5, 0xE282, 0x7AC4, 0xE283, 0x7ABF, 0xE284, 0x9083,
+	0xE285, 0x7AC7, 0xE286, 0x7ACA, 0xE287, 0x7ACD, 0xE288, 0x7ACF,	0xE289, 0x7AD5, 0xE28A, 0x7AD3, 0xE28B, 0x7AD9, 0xE28C, 0x7ADA,
+	0xE28D, 0x7ADD, 0xE28E, 0x7AE1, 0xE28F, 0x7AE2, 0xE290, 0x7AE6,	0xE291, 0x7AED, 0xE292, 0x7AF0, 0xE293, 0x7B02, 0xE294, 0x7B0F,
+	0xE295, 0x7B0A, 0xE296, 0x7B06, 0xE297, 0x7B33, 0xE298, 0x7B18,	0xE299, 0x7B19, 0xE29A, 0x7B1E, 0xE29B, 0x7B35, 0xE29C, 0x7B28,
+	0xE29D, 0x7B36, 0xE29E, 0x7B50, 0xE29F, 0x7B7A, 0xE2A0, 0x7B04,	0xE2A1, 0x7B4D, 0xE2A2, 0x7B0B, 0xE2A3, 0x7B4C, 0xE2A4, 0x7B45,
+	0xE2A5, 0x7B75, 0xE2A6, 0x7B65, 0xE2A7, 0x7B74, 0xE2A8, 0x7B67,	0xE2A9, 0x7B70, 0xE2AA, 0x7B71, 0xE2AB, 0x7B6C, 0xE2AC, 0x7B6E,
+	0xE2AD, 0x7B9D, 0xE2AE, 0x7B98, 0xE2AF, 0x7B9F, 0xE2B0, 0x7B8D,	0xE2B1, 0x7B9C, 0xE2B2, 0x7B9A, 0xE2B3, 0x7B8B, 0xE2B4, 0x7B92,
+	0xE2B5, 0x7B8F, 0xE2B6, 0x7B5D, 0xE2B7, 0x7B99, 0xE2B8, 0x7BCB,	0xE2B9, 0x7BC1, 0xE2BA, 0x7BCC, 0xE2BB, 0x7BCF, 0xE2BC, 0x7BB4,
+	0xE2BD, 0x7BC6, 0xE2BE, 0x7BDD, 0xE2BF, 0x7BE9, 0xE2C0, 0x7C11,	0xE2C1, 0x7C14, 0xE2C2, 0x7BE6, 0xE2C3, 0x7BE5, 0xE2C4, 0x7C60,
+	0xE2C5, 0x7C00, 0xE2C6, 0x7C07, 0xE2C7, 0x7C13, 0xE2C8, 0x7BF3,	0xE2C9, 0x7BF7, 0xE2CA, 0x7C17, 0xE2CB, 0x7C0D, 0xE2CC, 0x7BF6,
+	0xE2CD, 0x7C23, 0xE2CE, 0x7C27, 0xE2CF, 0x7C2A, 0xE2D0, 0x7C1F,	0xE2D1, 0x7C37, 0xE2D2, 0x7C2B, 0xE2D3, 0x7C3D, 0xE2D4, 0x7C4C,
+	0xE2D5, 0x7C43, 0xE2D6, 0x7C54, 0xE2D7, 0x7C4F, 0xE2D8, 0x7C40,	0xE2D9, 0x7C50, 0xE2DA, 0x7C58, 0xE2DB, 0x7C5F, 0xE2DC, 0x7C64,
+	0xE2DD, 0x7C56, 0xE2DE, 0x7C65, 0xE2DF, 0x7C6C, 0xE2E0, 0x7C75,	0xE2E1, 0x7C83, 0xE2E2, 0x7C90, 0xE2E3, 0x7CA4, 0xE2E4, 0x7CAD,
+	0xE2E5, 0x7CA2, 0xE2E6, 0x7CAB, 0xE2E7, 0x7CA1, 0xE2E8, 0x7CA8,	0xE2E9, 0x7CB3, 0xE2EA, 0x7CB2, 0xE2EB, 0x7CB1, 0xE2EC, 0x7CAE,
+	0xE2ED, 0x7CB9, 0xE2EE, 0x7CBD, 0xE2EF, 0x7CC0, 0xE2F0, 0x7CC5,	0xE2F1, 0x7CC2, 0xE2F2, 0x7CD8, 0xE2F3, 0x7CD2, 0xE2F4, 0x7CDC,
+	0xE2F5, 0x7CE2, 0xE2F6, 0x9B3B, 0xE2F7, 0x7CEF, 0xE2F8, 0x7CF2,	0xE2F9, 0x7CF4, 0xE2FA, 0x7CF6, 0xE2FB, 0x7CFA, 0xE2FC, 0x7D06,
+	0xE340, 0x7D02, 0xE341, 0x7D1C, 0xE342, 0x7D15, 0xE343, 0x7D0A,	0xE344, 0x7D45, 0xE345, 0x7D4B, 0xE346, 0x7D2E, 0xE347, 0x7D32,
+	0xE348, 0x7D3F, 0xE349, 0x7D35, 0xE34A, 0x7D46, 0xE34B, 0x7D73,	0xE34C, 0x7D56, 0xE34D, 0x7D4E, 0xE34E, 0x7D72, 0xE34F, 0x7D68,
+	0xE350, 0x7D6E, 0xE351, 0x7D4F, 0xE352, 0x7D63, 0xE353, 0x7D93,	0xE354, 0x7D89, 0xE355, 0x7D5B, 0xE356, 0x7D8F, 0xE357, 0x7D7D,
+	0xE358, 0x7D9B, 0xE359, 0x7DBA, 0xE35A, 0x7DAE, 0xE35B, 0x7DA3,	0xE35C, 0x7DB5, 0xE35D, 0x7DC7, 0xE35E, 0x7DBD, 0xE35F, 0x7DAB,
+	0xE360, 0x7E3D, 0xE361, 0x7DA2, 0xE362, 0x7DAF, 0xE363, 0x7DDC,	0xE364, 0x7DB8, 0xE365, 0x7D9F, 0xE366, 0x7DB0, 0xE367, 0x7DD8,
+	0xE368, 0x7DDD, 0xE369, 0x7DE4, 0xE36A, 0x7DDE, 0xE36B, 0x7DFB,	0xE36C, 0x7DF2, 0xE36D, 0x7DE1, 0xE36E, 0x7E05, 0xE36F, 0x7E0A,
+	0xE370, 0x7E23, 0xE371, 0x7E21, 0xE372, 0x7E12, 0xE373, 0x7E31,	0xE374, 0x7E1F, 0xE375, 0x7E09, 0xE376, 0x7E0B, 0xE377, 0x7E22,
+	0xE378, 0x7E46, 0xE379, 0x7E66, 0xE37A, 0x7E3B, 0xE37B, 0x7E35,	0xE37C, 0x7E39, 0xE37D, 0x7E43, 0xE37E, 0x7E37, 0xE380, 0x7E32,
+	0xE381, 0x7E3A, 0xE382, 0x7E67, 0xE383, 0x7E5D, 0xE384, 0x7E56,	0xE385, 0x7E5E, 0xE386, 0x7E59, 0xE387, 0x7E5A, 0xE388, 0x7E79,
+	0xE389, 0x7E6A, 0xE38A, 0x7E69, 0xE38B, 0x7E7C, 0xE38C, 0x7E7B,	0xE38D, 0x7E83, 0xE38E, 0x7DD5, 0xE38F, 0x7E7D, 0xE390, 0x8FAE,
+	0xE391, 0x7E7F, 0xE392, 0x7E88, 0xE393, 0x7E89, 0xE394, 0x7E8C,	0xE395, 0x7E92, 0xE396, 0x7E90, 0xE397, 0x7E93, 0xE398, 0x7E94,
+	0xE399, 0x7E96, 0xE39A, 0x7E8E, 0xE39B, 0x7E9B, 0xE39C, 0x7E9C,	0xE39D, 0x7F38, 0xE39E, 0x7F3A, 0xE39F, 0x7F45, 0xE3A0, 0x7F4C,
+	0xE3A1, 0x7F4D, 0xE3A2, 0x7F4E, 0xE3A3, 0x7F50, 0xE3A4, 0x7F51,	0xE3A5, 0x7F55, 0xE3A6, 0x7F54, 0xE3A7, 0x7F58, 0xE3A8, 0x7F5F,
+	0xE3A9, 0x7F60, 0xE3AA, 0x7F68, 0xE3AB, 0x7F69, 0xE3AC, 0x7F67,	0xE3AD, 0x7F78, 0xE3AE, 0x7F82, 0xE3AF, 0x7F86, 0xE3B0, 0x7F83,
+	0xE3B1, 0x7F88, 0xE3B2, 0x7F87, 0xE3B3, 0x7F8C, 0xE3B4, 0x7F94,	0xE3B5, 0x7F9E, 0xE3B6, 0x7F9D, 0xE3B7, 0x7F9A, 0xE3B8, 0x7FA3,
+	0xE3B9, 0x7FAF, 0xE3BA, 0x7FB2, 0xE3BB, 0x7FB9, 0xE3BC, 0x7FAE,	0xE3BD, 0x7FB6, 0xE3BE, 0x7FB8, 0xE3BF, 0x8B71, 0xE3C0, 0x7FC5,
+	0xE3C1, 0x7FC6, 0xE3C2, 0x7FCA, 0xE3C3, 0x7FD5, 0xE3C4, 0x7FD4,	0xE3C5, 0x7FE1, 0xE3C6, 0x7FE6, 0xE3C7, 0x7FE9, 0xE3C8, 0x7FF3,
+	0xE3C9, 0x7FF9, 0xE3CA, 0x98DC, 0xE3CB, 0x8006, 0xE3CC, 0x8004,	0xE3CD, 0x800B, 0xE3CE, 0x8012, 0xE3CF, 0x8018, 0xE3D0, 0x8019,
+	0xE3D1, 0x801C, 0xE3D2, 0x8021, 0xE3D3, 0x8028, 0xE3D4, 0x803F,	0xE3D5, 0x803B, 0xE3D6, 0x804A, 0xE3D7, 0x8046, 0xE3D8, 0x8052,
+	0xE3D9, 0x8058, 0xE3DA, 0x805A, 0xE3DB, 0x805F, 0xE3DC, 0x8062,	0xE3DD, 0x8068, 0xE3DE, 0x8073, 0xE3DF, 0x8072, 0xE3E0, 0x8070,
+	0xE3E1, 0x8076, 0xE3E2, 0x8079, 0xE3E3, 0x807D, 0xE3E4, 0x807F,	0xE3E5, 0x8084, 0xE3E6, 0x8086, 0xE3E7, 0x8085, 0xE3E8, 0x809B,
+	0xE3E9, 0x8093, 0xE3EA, 0x809A, 0xE3EB, 0x80AD, 0xE3EC, 0x5190,	0xE3ED, 0x80AC, 0xE3EE, 0x80DB, 0xE3EF, 0x80E5, 0xE3F0, 0x80D9,
+	0xE3F1, 0x80DD, 0xE3F2, 0x80C4, 0xE3F3, 0x80DA, 0xE3F4, 0x80D6,	0xE3F5, 0x8109, 0xE3F6, 0x80EF, 0xE3F7, 0x80F1, 0xE3F8, 0x811B,
+	0xE3F9, 0x8129, 0xE3FA, 0x8123, 0xE3FB, 0x812F, 0xE3FC, 0x814B,	0xE440, 0x968B, 0xE441, 0x8146, 0xE442, 0x813E, 0xE443, 0x8153,
+	0xE444, 0x8151, 0xE445, 0x80FC, 0xE446, 0x8171, 0xE447, 0x816E,	0xE448, 0x8165, 0xE449, 0x8166, 0xE44A, 0x8174, 0xE44B, 0x8183,
+	0xE44C, 0x8188, 0xE44D, 0x818A, 0xE44E, 0x8180, 0xE44F, 0x8182,	0xE450, 0x81A0, 0xE451, 0x8195, 0xE452, 0x81A4, 0xE453, 0x81A3,
+	0xE454, 0x815F, 0xE455, 0x8193, 0xE456, 0x81A9, 0xE457, 0x81B0,	0xE458, 0x81B5, 0xE459, 0x81BE, 0xE45A, 0x81B8, 0xE45B, 0x81BD,
+	0xE45C, 0x81C0, 0xE45D, 0x81C2, 0xE45E, 0x81BA, 0xE45F, 0x81C9,	0xE460, 0x81CD, 0xE461, 0x81D1, 0xE462, 0x81D9, 0xE463, 0x81D8,
+	0xE464, 0x81C8, 0xE465, 0x81DA, 0xE466, 0x81DF, 0xE467, 0x81E0,	0xE468, 0x81E7, 0xE469, 0x81FA, 0xE46A, 0x81FB, 0xE46B, 0x81FE,
+	0xE46C, 0x8201, 0xE46D, 0x8202, 0xE46E, 0x8205, 0xE46F, 0x8207,	0xE470, 0x820A, 0xE471, 0x820D, 0xE472, 0x8210, 0xE473, 0x8216,
+	0xE474, 0x8229, 0xE475, 0x822B, 0xE476, 0x8238, 0xE477, 0x8233,	0xE478, 0x8240, 0xE479, 0x8259, 0xE47A, 0x8258, 0xE47B, 0x825D,
+	0xE47C, 0x825A, 0xE47D, 0x825F, 0xE47E, 0x8264, 0xE480, 0x8262,	0xE481, 0x8268, 0xE482, 0x826A, 0xE483, 0x826B, 0xE484, 0x822E,
+	0xE485, 0x8271, 0xE486, 0x8277, 0xE487, 0x8278, 0xE488, 0x827E,	0xE489, 0x828D, 0xE48A, 0x8292, 0xE48B, 0x82AB, 0xE48C, 0x829F,
+	0xE48D, 0x82BB, 0xE48E, 0x82AC, 0xE48F, 0x82E1, 0xE490, 0x82E3,	0xE491, 0x82DF, 0xE492, 0x82D2, 0xE493, 0x82F4, 0xE494, 0x82F3,
+	0xE495, 0x82FA, 0xE496, 0x8393, 0xE497, 0x8303, 0xE498, 0x82FB,	0xE499, 0x82F9, 0xE49A, 0x82DE, 0xE49B, 0x8306, 0xE49C, 0x82DC,
+	0xE49D, 0x8309, 0xE49E, 0x82D9, 0xE49F, 0x8335, 0xE4A0, 0x8334,	0xE4A1, 0x8316, 0xE4A2, 0x8332, 0xE4A3, 0x8331, 0xE4A4, 0x8340,
+	0xE4A5, 0x8339, 0xE4A6, 0x8350, 0xE4A7, 0x8345, 0xE4A8, 0x832F,	0xE4A9, 0x832B, 0xE4AA, 0x8317, 0xE4AB, 0x8318, 0xE4AC, 0x8385,
+	0xE4AD, 0x839A, 0xE4AE, 0x83AA, 0xE4AF, 0x839F, 0xE4B0, 0x83A2,	0xE4B1, 0x8396, 0xE4B2, 0x8323, 0xE4B3, 0x838E, 0xE4B4, 0x8387,
+	0xE4B5, 0x838A, 0xE4B6, 0x837C, 0xE4B7, 0x83B5, 0xE4B8, 0x8373,	0xE4B9, 0x8375, 0xE4BA, 0x83A0, 0xE4BB, 0x8389, 0xE4BC, 0x83A8,
+	0xE4BD, 0x83F4, 0xE4BE, 0x8413, 0xE4BF, 0x83EB, 0xE4C0, 0x83CE,	0xE4C1, 0x83FD, 0xE4C2, 0x8403, 0xE4C3, 0x83D8, 0xE4C4, 0x840B,
+	0xE4C5, 0x83C1, 0xE4C6, 0x83F7, 0xE4C7, 0x8407, 0xE4C8, 0x83E0,	0xE4C9, 0x83F2, 0xE4CA, 0x840D, 0xE4CB, 0x8422, 0xE4CC, 0x8420,
+	0xE4CD, 0x83BD, 0xE4CE, 0x8438, 0xE4CF, 0x8506, 0xE4D0, 0x83FB,	0xE4D1, 0x846D, 0xE4D2, 0x842A, 0xE4D3, 0x843C, 0xE4D4, 0x855A,
+	0xE4D5, 0x8484, 0xE4D6, 0x8477, 0xE4D7, 0x846B, 0xE4D8, 0x84AD,	0xE4D9, 0x846E, 0xE4DA, 0x8482, 0xE4DB, 0x8469, 0xE4DC, 0x8446,
+	0xE4DD, 0x842C, 0xE4DE, 0x846F, 0xE4DF, 0x8479, 0xE4E0, 0x8435,	0xE4E1, 0x84CA, 0xE4E2, 0x8462, 0xE4E3, 0x84B9, 0xE4E4, 0x84BF,
+	0xE4E5, 0x849F, 0xE4E6, 0x84D9, 0xE4E7, 0x84CD, 0xE4E8, 0x84BB,	0xE4E9, 0x84DA, 0xE4EA, 0x84D0, 0xE4EB, 0x84C1, 0xE4EC, 0x84C6,
+	0xE4ED, 0x84D6, 0xE4EE, 0x84A1, 0xE4EF, 0x8521, 0xE4F0, 0x84FF,	0xE4F1, 0x84F4, 0xE4F2, 0x8517, 0xE4F3, 0x8518, 0xE4F4, 0x852C,
+	0xE4F5, 0x851F, 0xE4F6, 0x8515, 0xE4F7, 0x8514, 0xE4F8, 0x84FC,	0xE4F9, 0x8540, 0xE4FA, 0x8563, 0xE4FB, 0x8558, 0xE4FC, 0x8548,
+	0xE540, 0x8541, 0xE541, 0x8602, 0xE542, 0x854B, 0xE543, 0x8555,	0xE544, 0x8580, 0xE545, 0x85A4, 0xE546, 0x8588, 0xE547, 0x8591,
+	0xE548, 0x858A, 0xE549, 0x85A8, 0xE54A, 0x856D, 0xE54B, 0x8594,	0xE54C, 0x859B, 0xE54D, 0x85EA, 0xE54E, 0x8587, 0xE54F, 0x859C,
+	0xE550, 0x8577, 0xE551, 0x857E, 0xE552, 0x8590, 0xE553, 0x85C9,	0xE554, 0x85BA, 0xE555, 0x85CF, 0xE556, 0x85B9, 0xE557, 0x85D0,
+	0xE558, 0x85D5, 0xE559, 0x85DD, 0xE55A, 0x85E5, 0xE55B, 0x85DC,	0xE55C, 0x85F9, 0xE55D, 0x860A, 0xE55E, 0x8613, 0xE55F, 0x860B,
+	0xE560, 0x85FE, 0xE561, 0x85FA, 0xE562, 0x8606, 0xE563, 0x8622,	0xE564, 0x861A, 0xE565, 0x8630, 0xE566, 0x863F, 0xE567, 0x864D,
+	0xE568, 0x4E55, 0xE569, 0x8654, 0xE56A, 0x865F, 0xE56B, 0x8667,	0xE56C, 0x8671, 0xE56D, 0x8693, 0xE56E, 0x86A3, 0xE56F, 0x86A9,
+	0xE570, 0x86AA, 0xE571, 0x868B, 0xE572, 0x868C, 0xE573, 0x86B6,	0xE574, 0x86AF, 0xE575, 0x86C4, 0xE576, 0x86C6, 0xE577, 0x86B0,
+	0xE578, 0x86C9, 0xE579, 0x8823, 0xE57A, 0x86AB, 0xE57B, 0x86D4,	0xE57C, 0x86DE, 0xE57D, 0x86E9, 0xE57E, 0x86EC, 0xE580, 0x86DF,
+	0xE581, 0x86DB, 0xE582, 0x86EF, 0xE583, 0x8712, 0xE584, 0x8706,	0xE585, 0x8708, 0xE586, 0x8700, 0xE587, 0x8703, 0xE588, 0x86FB,
+	0xE589, 0x8711, 0xE58A, 0x8709, 0xE58B, 0x870D, 0xE58C, 0x86F9,	0xE58D, 0x870A, 0xE58E, 0x8734, 0xE58F, 0x873F, 0xE590, 0x8737,
+	0xE591, 0x873B, 0xE592, 0x8725, 0xE593, 0x8729, 0xE594, 0x871A,	0xE595, 0x8760, 0xE596, 0x875F, 0xE597, 0x8778, 0xE598, 0x874C,
+	0xE599, 0x874E, 0xE59A, 0x8774, 0xE59B, 0x8757, 0xE59C, 0x8768,	0xE59D, 0x876E, 0xE59E, 0x8759, 0xE59F, 0x8753, 0xE5A0, 0x8763,
+	0xE5A1, 0x876A, 0xE5A2, 0x8805, 0xE5A3, 0x87A2, 0xE5A4, 0x879F,	0xE5A5, 0x8782, 0xE5A6, 0x87AF, 0xE5A7, 0x87CB, 0xE5A8, 0x87BD,
+	0xE5A9, 0x87C0, 0xE5AA, 0x87D0, 0xE5AB, 0x96D6, 0xE5AC, 0x87AB,	0xE5AD, 0x87C4, 0xE5AE, 0x87B3, 0xE5AF, 0x87C7, 0xE5B0, 0x87C6,
+	0xE5B1, 0x87BB, 0xE5B2, 0x87EF, 0xE5B3, 0x87F2, 0xE5B4, 0x87E0,	0xE5B5, 0x880F, 0xE5B6, 0x880D, 0xE5B7, 0x87FE, 0xE5B8, 0x87F6,
+	0xE5B9, 0x87F7, 0xE5BA, 0x880E, 0xE5BB, 0x87D2, 0xE5BC, 0x8811,	0xE5BD, 0x8816, 0xE5BE, 0x8815, 0xE5BF, 0x8822, 0xE5C0, 0x8821,
+	0xE5C1, 0x8831, 0xE5C2, 0x8836, 0xE5C3, 0x8839, 0xE5C4, 0x8827,	0xE5C5, 0x883B, 0xE5C6, 0x8844, 0xE5C7, 0x8842, 0xE5C8, 0x8852,
+	0xE5C9, 0x8859, 0xE5CA, 0x885E, 0xE5CB, 0x8862, 0xE5CC, 0x886B,	0xE5CD, 0x8881, 0xE5CE, 0x887E, 0xE5CF, 0x889E, 0xE5D0, 0x8875,
+	0xE5D1, 0x887D, 0xE5D2, 0x88B5, 0xE5D3, 0x8872, 0xE5D4, 0x8882,	0xE5D5, 0x8897, 0xE5D6, 0x8892, 0xE5D7, 0x88AE, 0xE5D8, 0x8899,
+	0xE5D9, 0x88A2, 0xE5DA, 0x888D, 0xE5DB, 0x88A4, 0xE5DC, 0x88B0,	0xE5DD, 0x88BF, 0xE5DE, 0x88B1, 0xE5DF, 0x88C3, 0xE5E0, 0x88C4,
+	0xE5E1, 0x88D4, 0xE5E2, 0x88D8, 0xE5E3, 0x88D9, 0xE5E4, 0x88DD,	0xE5E5, 0x88F9, 0xE5E6, 0x8902, 0xE5E7, 0x88FC, 0xE5E8, 0x88F4,
+	0xE5E9, 0x88E8, 0xE5EA, 0x88F2, 0xE5EB, 0x8904, 0xE5EC, 0x890C,	0xE5ED, 0x890A, 0xE5EE, 0x8913, 0xE5EF, 0x8943, 0xE5F0, 0x891E,
+	0xE5F1, 0x8925, 0xE5F2, 0x892A, 0xE5F3, 0x892B, 0xE5F4, 0x8941,	0xE5F5, 0x8944, 0xE5F6, 0x893B, 0xE5F7, 0x8936, 0xE5F8, 0x8938,
+	0xE5F9, 0x894C, 0xE5FA, 0x891D, 0xE5FB, 0x8960, 0xE5FC, 0x895E,	0xE640, 0x8966, 0xE641, 0x8964, 0xE642, 0x896D, 0xE643, 0x896A,
+	0xE644, 0x896F, 0xE645, 0x8974, 0xE646, 0x8977, 0xE647, 0x897E,	0xE648, 0x8983, 0xE649, 0x8988, 0xE64A, 0x898A, 0xE64B, 0x8993,
+	0xE64C, 0x8998, 0xE64D, 0x89A1, 0xE64E, 0x89A9, 0xE64F, 0x89A6,	0xE650, 0x89AC, 0xE651, 0x89AF, 0xE652, 0x89B2, 0xE653, 0x89BA,
+	0xE654, 0x89BD, 0xE655, 0x89BF, 0xE656, 0x89C0, 0xE657, 0x89DA,	0xE658, 0x89DC, 0xE659, 0x89DD, 0xE65A, 0x89E7, 0xE65B, 0x89F4,
+	0xE65C, 0x89F8, 0xE65D, 0x8A03, 0xE65E, 0x8A16, 0xE65F, 0x8A10,	0xE660, 0x8A0C, 0xE661, 0x8A1B, 0xE662, 0x8A1D, 0xE663, 0x8A25,
+	0xE664, 0x8A36, 0xE665, 0x8A41, 0xE666, 0x8A5B, 0xE667, 0x8A52,	0xE668, 0x8A46, 0xE669, 0x8A48, 0xE66A, 0x8A7C, 0xE66B, 0x8A6D,
+	0xE66C, 0x8A6C, 0xE66D, 0x8A62, 0xE66E, 0x8A85, 0xE66F, 0x8A82,	0xE670, 0x8A84, 0xE671, 0x8AA8, 0xE672, 0x8AA1, 0xE673, 0x8A91,
+	0xE674, 0x8AA5, 0xE675, 0x8AA6, 0xE676, 0x8A9A, 0xE677, 0x8AA3,	0xE678, 0x8AC4, 0xE679, 0x8ACD, 0xE67A, 0x8AC2, 0xE67B, 0x8ADA,
+	0xE67C, 0x8AEB, 0xE67D, 0x8AF3, 0xE67E, 0x8AE7, 0xE680, 0x8AE4,	0xE681, 0x8AF1, 0xE682, 0x8B14, 0xE683, 0x8AE0, 0xE684, 0x8AE2,
+	0xE685, 0x8AF7, 0xE686, 0x8ADE, 0xE687, 0x8ADB, 0xE688, 0x8B0C,	0xE689, 0x8B07, 0xE68A, 0x8B1A, 0xE68B, 0x8AE1, 0xE68C, 0x8B16,
+	0xE68D, 0x8B10, 0xE68E, 0x8B17, 0xE68F, 0x8B20, 0xE690, 0x8B33,	0xE691, 0x97AB, 0xE692, 0x8B26, 0xE693, 0x8B2B, 0xE694, 0x8B3E,
+	0xE695, 0x8B28, 0xE696, 0x8B41, 0xE697, 0x8B4C, 0xE698, 0x8B4F,	0xE699, 0x8B4E, 0xE69A, 0x8B49, 0xE69B, 0x8B56, 0xE69C, 0x8B5B,
+	0xE69D, 0x8B5A, 0xE69E, 0x8B6B, 0xE69F, 0x8B5F, 0xE6A0, 0x8B6C,	0xE6A1, 0x8B6F, 0xE6A2, 0x8B74, 0xE6A3, 0x8B7D, 0xE6A4, 0x8B80,
+	0xE6A5, 0x8B8C, 0xE6A6, 0x8B8E, 0xE6A7, 0x8B92, 0xE6A8, 0x8B93,	0xE6A9, 0x8B96, 0xE6AA, 0x8B99, 0xE6AB, 0x8B9A, 0xE6AC, 0x8C3A,
+	0xE6AD, 0x8C41, 0xE6AE, 0x8C3F, 0xE6AF, 0x8C48, 0xE6B0, 0x8C4C,	0xE6B1, 0x8C4E, 0xE6B2, 0x8C50, 0xE6B3, 0x8C55, 0xE6B4, 0x8C62,
+	0xE6B5, 0x8C6C, 0xE6B6, 0x8C78, 0xE6B7, 0x8C7A, 0xE6B8, 0x8C82,	0xE6B9, 0x8C89, 0xE6BA, 0x8C85, 0xE6BB, 0x8C8A, 0xE6BC, 0x8C8D,
+	0xE6BD, 0x8C8E, 0xE6BE, 0x8C94, 0xE6BF, 0x8C7C, 0xE6C0, 0x8C98,	0xE6C1, 0x621D, 0xE6C2, 0x8CAD, 0xE6C3, 0x8CAA, 0xE6C4, 0x8CBD,
+	0xE6C5, 0x8CB2, 0xE6C6, 0x8CB3, 0xE6C7, 0x8CAE, 0xE6C8, 0x8CB6,	0xE6C9, 0x8CC8, 0xE6CA, 0x8CC1, 0xE6CB, 0x8CE4, 0xE6CC, 0x8CE3,
+	0xE6CD, 0x8CDA, 0xE6CE, 0x8CFD, 0xE6CF, 0x8CFA, 0xE6D0, 0x8CFB,	0xE6D1, 0x8D04, 0xE6D2, 0x8D05, 0xE6D3, 0x8D0A, 0xE6D4, 0x8D07,
+	0xE6D5, 0x8D0F, 0xE6D6, 0x8D0D, 0xE6D7, 0x8D10, 0xE6D8, 0x9F4E,	0xE6D9, 0x8D13, 0xE6DA, 0x8CCD, 0xE6DB, 0x8D14, 0xE6DC, 0x8D16,
+	0xE6DD, 0x8D67, 0xE6DE, 0x8D6D, 0xE6DF, 0x8D71, 0xE6E0, 0x8D73,	0xE6E1, 0x8D81, 0xE6E2, 0x8D99, 0xE6E3, 0x8DC2, 0xE6E4, 0x8DBE,
+	0xE6E5, 0x8DBA, 0xE6E6, 0x8DCF, 0xE6E7, 0x8DDA, 0xE6E8, 0x8DD6,	0xE6E9, 0x8DCC, 0xE6EA, 0x8DDB, 0xE6EB, 0x8DCB, 0xE6EC, 0x8DEA,
+	0xE6ED, 0x8DEB, 0xE6EE, 0x8DDF, 0xE6EF, 0x8DE3, 0xE6F0, 0x8DFC,	0xE6F1, 0x8E08, 0xE6F2, 0x8E09, 0xE6F3, 0x8DFF, 0xE6F4, 0x8E1D,
+	0xE6F5, 0x8E1E, 0xE6F6, 0x8E10, 0xE6F7, 0x8E1F, 0xE6F8, 0x8E42,	0xE6F9, 0x8E35, 0xE6FA, 0x8E30, 0xE6FB, 0x8E34, 0xE6FC, 0x8E4A,
+	0xE740, 0x8E47, 0xE741, 0x8E49, 0xE742, 0x8E4C, 0xE743, 0x8E50,	0xE744, 0x8E48, 0xE745, 0x8E59, 0xE746, 0x8E64, 0xE747, 0x8E60,
+	0xE748, 0x8E2A, 0xE749, 0x8E63, 0xE74A, 0x8E55, 0xE74B, 0x8E76,	0xE74C, 0x8E72, 0xE74D, 0x8E7C, 0xE74E, 0x8E81, 0xE74F, 0x8E87,
+	0xE750, 0x8E85, 0xE751, 0x8E84, 0xE752, 0x8E8B, 0xE753, 0x8E8A,	0xE754, 0x8E93, 0xE755, 0x8E91, 0xE756, 0x8E94, 0xE757, 0x8E99,
+	0xE758, 0x8EAA, 0xE759, 0x8EA1, 0xE75A, 0x8EAC, 0xE75B, 0x8EB0,	0xE75C, 0x8EC6, 0xE75D, 0x8EB1, 0xE75E, 0x8EBE, 0xE75F, 0x8EC5,
+	0xE760, 0x8EC8, 0xE761, 0x8ECB, 0xE762, 0x8EDB, 0xE763, 0x8EE3,	0xE764, 0x8EFC, 0xE765, 0x8EFB, 0xE766, 0x8EEB, 0xE767, 0x8EFE,
+	0xE768, 0x8F0A, 0xE769, 0x8F05, 0xE76A, 0x8F15, 0xE76B, 0x8F12,	0xE76C, 0x8F19, 0xE76D, 0x8F13, 0xE76E, 0x8F1C, 0xE76F, 0x8F1F,
+	0xE770, 0x8F1B, 0xE771, 0x8F0C, 0xE772, 0x8F26, 0xE773, 0x8F33,	0xE774, 0x8F3B, 0xE775, 0x8F39, 0xE776, 0x8F45, 0xE777, 0x8F42,
+	0xE778, 0x8F3E, 0xE779, 0x8F4C, 0xE77A, 0x8F49, 0xE77B, 0x8F46,	0xE77C, 0x8F4E, 0xE77D, 0x8F57, 0xE77E, 0x8F5C, 0xE780, 0x8F62,
+	0xE781, 0x8F63, 0xE782, 0x8F64, 0xE783, 0x8F9C, 0xE784, 0x8F9F,	0xE785, 0x8FA3, 0xE786, 0x8FAD, 0xE787, 0x8FAF, 0xE788, 0x8FB7,
+	0xE789, 0x8FDA, 0xE78A, 0x8FE5, 0xE78B, 0x8FE2, 0xE78C, 0x8FEA,	0xE78D, 0x8FEF, 0xE78E, 0x9087, 0xE78F, 0x8FF4, 0xE790, 0x9005,
+	0xE791, 0x8FF9, 0xE792, 0x8FFA, 0xE793, 0x9011, 0xE794, 0x9015,	0xE795, 0x9021, 0xE796, 0x900D, 0xE797, 0x901E, 0xE798, 0x9016,
+	0xE799, 0x900B, 0xE79A, 0x9027, 0xE79B, 0x9036, 0xE79C, 0x9035,	0xE79D, 0x9039, 0xE79E, 0x8FF8, 0xE79F, 0x904F, 0xE7A0, 0x9050,
+	0xE7A1, 0x9051, 0xE7A2, 0x9052, 0xE7A3, 0x900E, 0xE7A4, 0x9049,	0xE7A5, 0x903E, 0xE7A6, 0x9056, 0xE7A7, 0x9058, 0xE7A8, 0x905E,
+	0xE7A9, 0x9068, 0xE7AA, 0x906F, 0xE7AB, 0x9076, 0xE7AC, 0x96A8,	0xE7AD, 0x9072, 0xE7AE, 0x9082, 0xE7AF, 0x907D, 0xE7B0, 0x9081,
+	0xE7B1, 0x9080, 0xE7B2, 0x908A, 0xE7B3, 0x9089, 0xE7B4, 0x908F,	0xE7B5, 0x90A8, 0xE7B6, 0x90AF, 0xE7B7, 0x90B1, 0xE7B8, 0x90B5,
+	0xE7B9, 0x90E2, 0xE7BA, 0x90E4, 0xE7BB, 0x6248, 0xE7BC, 0x90DB,	0xE7BD, 0x9102, 0xE7BE, 0x9112, 0xE7BF, 0x9119, 0xE7C0, 0x9132,
+	0xE7C1, 0x9130, 0xE7C2, 0x914A, 0xE7C3, 0x9156, 0xE7C4, 0x9158,	0xE7C5, 0x9163, 0xE7C6, 0x9165, 0xE7C7, 0x9169, 0xE7C8, 0x9173,
+	0xE7C9, 0x9172, 0xE7CA, 0x918B, 0xE7CB, 0x9189, 0xE7CC, 0x9182,	0xE7CD, 0x91A2, 0xE7CE, 0x91AB, 0xE7CF, 0x91AF, 0xE7D0, 0x91AA,
+	0xE7D1, 0x91B5, 0xE7D2, 0x91B4, 0xE7D3, 0x91BA, 0xE7D4, 0x91C0,	0xE7D5, 0x91C1, 0xE7D6, 0x91C9, 0xE7D7, 0x91CB, 0xE7D8, 0x91D0,
+	0xE7D9, 0x91D6, 0xE7DA, 0x91DF, 0xE7DB, 0x91E1, 0xE7DC, 0x91DB,	0xE7DD, 0x91FC, 0xE7DE, 0x91F5, 0xE7DF, 0x91F6, 0xE7E0, 0x921E,
+	0xE7E1, 0x91FF, 0xE7E2, 0x9214, 0xE7E3, 0x922C, 0xE7E4, 0x9215,	0xE7E5, 0x9211, 0xE7E6, 0x925E, 0xE7E7, 0x9257, 0xE7E8, 0x9245,
+	0xE7E9, 0x9249, 0xE7EA, 0x9264, 0xE7EB, 0x9248, 0xE7EC, 0x9295,	0xE7ED, 0x923F, 0xE7EE, 0x924B, 0xE7EF, 0x9250, 0xE7F0, 0x929C,
+	0xE7F1, 0x9296, 0xE7F2, 0x9293, 0xE7F3, 0x929B, 0xE7F4, 0x925A,	0xE7F5, 0x92CF, 0xE7F6, 0x92B9, 0xE7F7, 0x92B7, 0xE7F8, 0x92E9,
+	0xE7F9, 0x930F, 0xE7FA, 0x92FA, 0xE7FB, 0x9344, 0xE7FC, 0x932E,	0xE840, 0x9319, 0xE841, 0x9322, 0xE842, 0x931A, 0xE843, 0x9323,
+	0xE844, 0x933A, 0xE845, 0x9335, 0xE846, 0x933B, 0xE847, 0x935C,	0xE848, 0x9360, 0xE849, 0x937C, 0xE84A, 0x936E, 0xE84B, 0x9356,
+	0xE84C, 0x93B0, 0xE84D, 0x93AC, 0xE84E, 0x93AD, 0xE84F, 0x9394,	0xE850, 0x93B9, 0xE851, 0x93D6, 0xE852, 0x93D7, 0xE853, 0x93E8,
+	0xE854, 0x93E5, 0xE855, 0x93D8, 0xE856, 0x93C3, 0xE857, 0x93DD,	0xE858, 0x93D0, 0xE859, 0x93C8, 0xE85A, 0x93E4, 0xE85B, 0x941A,
+	0xE85C, 0x9414, 0xE85D, 0x9413, 0xE85E, 0x9403, 0xE85F, 0x9407,	0xE860, 0x9410, 0xE861, 0x9436, 0xE862, 0x942B, 0xE863, 0x9435,
+	0xE864, 0x9421, 0xE865, 0x943A, 0xE866, 0x9441, 0xE867, 0x9452,	0xE868, 0x9444, 0xE869, 0x945B, 0xE86A, 0x9460, 0xE86B, 0x9462,
+	0xE86C, 0x945E, 0xE86D, 0x946A, 0xE86E, 0x9229, 0xE86F, 0x9470,	0xE870, 0x9475, 0xE871, 0x9477, 0xE872, 0x947D, 0xE873, 0x945A,
+	0xE874, 0x947C, 0xE875, 0x947E, 0xE876, 0x9481, 0xE877, 0x947F,	0xE878, 0x9582, 0xE879, 0x9587, 0xE87A, 0x958A, 0xE87B, 0x9594,
+	0xE87C, 0x9596, 0xE87D, 0x9598, 0xE87E, 0x9599, 0xE880, 0x95A0,	0xE881, 0x95A8, 0xE882, 0x95A7, 0xE883, 0x95AD, 0xE884, 0x95BC,
+	0xE885, 0x95BB, 0xE886, 0x95B9, 0xE887, 0x95BE, 0xE888, 0x95CA,	0xE889, 0x6FF6, 0xE88A, 0x95C3, 0xE88B, 0x95CD, 0xE88C, 0x95CC,
+	0xE88D, 0x95D5, 0xE88E, 0x95D4, 0xE88F, 0x95D6, 0xE890, 0x95DC,	0xE891, 0x95E1, 0xE892, 0x95E5, 0xE893, 0x95E2, 0xE894, 0x9621,
+	0xE895, 0x9628, 0xE896, 0x962E, 0xE897, 0x962F, 0xE898, 0x9642,	0xE899, 0x964C, 0xE89A, 0x964F, 0xE89B, 0x964B, 0xE89C, 0x9677,
+	0xE89D, 0x965C, 0xE89E, 0x965E, 0xE89F, 0x965D, 0xE8A0, 0x965F,	0xE8A1, 0x9666, 0xE8A2, 0x9672, 0xE8A3, 0x966C, 0xE8A4, 0x968D,
+	0xE8A5, 0x9698, 0xE8A6, 0x9695, 0xE8A7, 0x9697, 0xE8A8, 0x96AA,	0xE8A9, 0x96A7, 0xE8AA, 0x96B1, 0xE8AB, 0x96B2, 0xE8AC, 0x96B0,
+	0xE8AD, 0x96B4, 0xE8AE, 0x96B6, 0xE8AF, 0x96B8, 0xE8B0, 0x96B9,	0xE8B1, 0x96CE, 0xE8B2, 0x96CB, 0xE8B3, 0x96C9, 0xE8B4, 0x96CD,
+	0xE8B5, 0x894D, 0xE8B6, 0x96DC, 0xE8B7, 0x970D, 0xE8B8, 0x96D5,	0xE8B9, 0x96F9, 0xE8BA, 0x9704, 0xE8BB, 0x9706, 0xE8BC, 0x9708,
+	0xE8BD, 0x9713, 0xE8BE, 0x970E, 0xE8BF, 0x9711, 0xE8C0, 0x970F,	0xE8C1, 0x9716, 0xE8C2, 0x9719, 0xE8C3, 0x9724, 0xE8C4, 0x972A,
+	0xE8C5, 0x9730, 0xE8C6, 0x9739, 0xE8C7, 0x973D, 0xE8C8, 0x973E,	0xE8C9, 0x9744, 0xE8CA, 0x9746, 0xE8CB, 0x9748, 0xE8CC, 0x9742,
+	0xE8CD, 0x9749, 0xE8CE, 0x975C, 0xE8CF, 0x9760, 0xE8D0, 0x9764,	0xE8D1, 0x9766, 0xE8D2, 0x9768, 0xE8D3, 0x52D2, 0xE8D4, 0x976B,
+	0xE8D5, 0x9771, 0xE8D6, 0x9779, 0xE8D7, 0x9785, 0xE8D8, 0x977C,	0xE8D9, 0x9781, 0xE8DA, 0x977A, 0xE8DB, 0x9786, 0xE8DC, 0x978B,
+	0xE8DD, 0x978F, 0xE8DE, 0x9790, 0xE8DF, 0x979C, 0xE8E0, 0x97A8,	0xE8E1, 0x97A6, 0xE8E2, 0x97A3, 0xE8E3, 0x97B3, 0xE8E4, 0x97B4,
+	0xE8E5, 0x97C3, 0xE8E6, 0x97C6, 0xE8E7, 0x97C8, 0xE8E8, 0x97CB,	0xE8E9, 0x97DC, 0xE8EA, 0x97ED, 0xE8EB, 0x9F4F, 0xE8EC, 0x97F2,
+	0xE8ED, 0x7ADF, 0xE8EE, 0x97F6, 0xE8EF, 0x97F5, 0xE8F0, 0x980F,	0xE8F1, 0x980C, 0xE8F2, 0x9838, 0xE8F3, 0x9824, 0xE8F4, 0x9821,
+	0xE8F5, 0x9837, 0xE8F6, 0x983D, 0xE8F7, 0x9846, 0xE8F8, 0x984F,	0xE8F9, 0x984B, 0xE8FA, 0x986B, 0xE8FB, 0x986F, 0xE8FC, 0x9870,
+	0xE940, 0x9871, 0xE941, 0x9874, 0xE942, 0x9873, 0xE943, 0x98AA,	0xE944, 0x98AF, 0xE945, 0x98B1, 0xE946, 0x98B6, 0xE947, 0x98C4,
+	0xE948, 0x98C3, 0xE949, 0x98C6, 0xE94A, 0x98E9, 0xE94B, 0x98EB,	0xE94C, 0x9903, 0xE94D, 0x9909, 0xE94E, 0x9912, 0xE94F, 0x9914,
+	0xE950, 0x9918, 0xE951, 0x9921, 0xE952, 0x991D, 0xE953, 0x991E,	0xE954, 0x9924, 0xE955, 0x9920, 0xE956, 0x992C, 0xE957, 0x992E,
+	0xE958, 0x993D, 0xE959, 0x993E, 0xE95A, 0x9942, 0xE95B, 0x9949,	0xE95C, 0x9945, 0xE95D, 0x9950, 0xE95E, 0x994B, 0xE95F, 0x9951,
+	0xE960, 0x9952, 0xE961, 0x994C, 0xE962, 0x9955, 0xE963, 0x9997,	0xE964, 0x9998, 0xE965, 0x99A5, 0xE966, 0x99AD, 0xE967, 0x99AE,
+	0xE968, 0x99BC, 0xE969, 0x99DF, 0xE96A, 0x99DB, 0xE96B, 0x99DD,	0xE96C, 0x99D8, 0xE96D, 0x99D1, 0xE96E, 0x99ED, 0xE96F, 0x99EE,
+	0xE970, 0x99F1, 0xE971, 0x99F2, 0xE972, 0x99FB, 0xE973, 0x99F8,	0xE974, 0x9A01, 0xE975, 0x9A0F, 0xE976, 0x9A05, 0xE977, 0x99E2,
+	0xE978, 0x9A19, 0xE979, 0x9A2B, 0xE97A, 0x9A37, 0xE97B, 0x9A45,	0xE97C, 0x9A42, 0xE97D, 0x9A40, 0xE97E, 0x9A43, 0xE980, 0x9A3E,
+	0xE981, 0x9A55, 0xE982, 0x9A4D, 0xE983, 0x9A5B, 0xE984, 0x9A57,	0xE985, 0x9A5F, 0xE986, 0x9A62, 0xE987, 0x9A65, 0xE988, 0x9A64,
+	0xE989, 0x9A69, 0xE98A, 0x9A6B, 0xE98B, 0x9A6A, 0xE98C, 0x9AAD,	0xE98D, 0x9AB0, 0xE98E, 0x9ABC, 0xE98F, 0x9AC0, 0xE990, 0x9ACF,
+	0xE991, 0x9AD1, 0xE992, 0x9AD3, 0xE993, 0x9AD4, 0xE994, 0x9ADE,	0xE995, 0x9ADF, 0xE996, 0x9AE2, 0xE997, 0x9AE3, 0xE998, 0x9AE6,
+	0xE999, 0x9AEF, 0xE99A, 0x9AEB, 0xE99B, 0x9AEE, 0xE99C, 0x9AF4,	0xE99D, 0x9AF1, 0xE99E, 0x9AF7, 0xE99F, 0x9AFB, 0xE9A0, 0x9B06,
+	0xE9A1, 0x9B18, 0xE9A2, 0x9B1A, 0xE9A3, 0x9B1F, 0xE9A4, 0x9B22,	0xE9A5, 0x9B23, 0xE9A6, 0x9B25, 0xE9A7, 0x9B27, 0xE9A8, 0x9B28,
+	0xE9A9, 0x9B29, 0xE9AA, 0x9B2A, 0xE9AB, 0x9B2E, 0xE9AC, 0x9B2F,	0xE9AD, 0x9B32, 0xE9AE, 0x9B44, 0xE9AF, 0x9B43, 0xE9B0, 0x9B4F,
+	0xE9B1, 0x9B4D, 0xE9B2, 0x9B4E, 0xE9B3, 0x9B51, 0xE9B4, 0x9B58,	0xE9B5, 0x9B74, 0xE9B6, 0x9B93, 0xE9B7, 0x9B83, 0xE9B8, 0x9B91,
+	0xE9B9, 0x9B96, 0xE9BA, 0x9B97, 0xE9BB, 0x9B9F, 0xE9BC, 0x9BA0,	0xE9BD, 0x9BA8, 0xE9BE, 0x9BB4, 0xE9BF, 0x9BC0, 0xE9C0, 0x9BCA,
+	0xE9C1, 0x9BB9, 0xE9C2, 0x9BC6, 0xE9C3, 0x9BCF, 0xE9C4, 0x9BD1,	0xE9C5, 0x9BD2, 0xE9C6, 0x9BE3, 0xE9C7, 0x9BE2, 0xE9C8, 0x9BE4,
+	0xE9C9, 0x9BD4, 0xE9CA, 0x9BE1, 0xE9CB, 0x9C3A, 0xE9CC, 0x9BF2,	0xE9CD, 0x9BF1, 0xE9CE, 0x9BF0, 0xE9CF, 0x9C15, 0xE9D0, 0x9C14,
+	0xE9D1, 0x9C09, 0xE9D2, 0x9C13, 0xE9D3, 0x9C0C, 0xE9D4, 0x9C06,	0xE9D5, 0x9C08, 0xE9D6, 0x9C12, 0xE9D7, 0x9C0A, 0xE9D8, 0x9C04,
+	0xE9D9, 0x9C2E, 0xE9DA, 0x9C1B, 0xE9DB, 0x9C25, 0xE9DC, 0x9C24,	0xE9DD, 0x9C21, 0xE9DE, 0x9C30, 0xE9DF, 0x9C47, 0xE9E0, 0x9C32,
+	0xE9E1, 0x9C46, 0xE9E2, 0x9C3E, 0xE9E3, 0x9C5A, 0xE9E4, 0x9C60,	0xE9E5, 0x9C67, 0xE9E6, 0x9C76, 0xE9E7, 0x9C78, 0xE9E8, 0x9CE7,
+	0xE9E9, 0x9CEC, 0xE9EA, 0x9CF0, 0xE9EB, 0x9D09, 0xE9EC, 0x9D08,	0xE9ED, 0x9CEB, 0xE9EE, 0x9D03, 0xE9EF, 0x9D06, 0xE9F0, 0x9D2A,
+	0xE9F1, 0x9D26, 0xE9F2, 0x9DAF, 0xE9F3, 0x9D23, 0xE9F4, 0x9D1F,	0xE9F5, 0x9D44, 0xE9F6, 0x9D15, 0xE9F7, 0x9D12, 0xE9F8, 0x9D41,
+	0xE9F9, 0x9D3F, 0xE9FA, 0x9D3E, 0xE9FB, 0x9D46, 0xE9FC, 0x9D48,	0xEA40, 0x9D5D, 0xEA41, 0x9D5E, 0xEA42, 0x9D64, 0xEA43, 0x9D51,
+	0xEA44, 0x9D50, 0xEA45, 0x9D59, 0xEA46, 0x9D72, 0xEA47, 0x9D89,	0xEA48, 0x9D87, 0xEA49, 0x9DAB, 0xEA4A, 0x9D6F, 0xEA4B, 0x9D7A,
+	0xEA4C, 0x9D9A, 0xEA4D, 0x9DA4, 0xEA4E, 0x9DA9, 0xEA4F, 0x9DB2,	0xEA50, 0x9DC4, 0xEA51, 0x9DC1, 0xEA52, 0x9DBB, 0xEA53, 0x9DB8,
+	0xEA54, 0x9DBA, 0xEA55, 0x9DC6, 0xEA56, 0x9DCF, 0xEA57, 0x9DC2,	0xEA58, 0x9DD9, 0xEA59, 0x9DD3, 0xEA5A, 0x9DF8, 0xEA5B, 0x9DE6,
+	0xEA5C, 0x9DED, 0xEA5D, 0x9DEF, 0xEA5E, 0x9DFD, 0xEA5F, 0x9E1A,	0xEA60, 0x9E1B, 0xEA61, 0x9E1E, 0xEA62, 0x9E75, 0xEA63, 0x9E79,
+	0xEA64, 0x9E7D, 0xEA65, 0x9E81, 0xEA66, 0x9E88, 0xEA67, 0x9E8B,	0xEA68, 0x9E8C, 0xEA69, 0x9E92, 0xEA6A, 0x9E95, 0xEA6B, 0x9E91,
+	0xEA6C, 0x9E9D, 0xEA6D, 0x9EA5, 0xEA6E, 0x9EA9, 0xEA6F, 0x9EB8,	0xEA70, 0x9EAA, 0xEA71, 0x9EAD, 0xEA72, 0x9761, 0xEA73, 0x9ECC,
+	0xEA74, 0x9ECE, 0xEA75, 0x9ECF, 0xEA76, 0x9ED0, 0xEA77, 0x9ED4,	0xEA78, 0x9EDC, 0xEA79, 0x9EDE, 0xEA7A, 0x9EDD, 0xEA7B, 0x9EE0,
+	0xEA7C, 0x9EE5, 0xEA7D, 0x9EE8, 0xEA7E, 0x9EEF, 0xEA80, 0x9EF4,	0xEA81, 0x9EF6, 0xEA82, 0x9EF7, 0xEA83, 0x9EF9, 0xEA84, 0x9EFB,
+	0xEA85, 0x9EFC, 0xEA86, 0x9EFD, 0xEA87, 0x9F07, 0xEA88, 0x9F08,	0xEA89, 0x76B7, 0xEA8A, 0x9F15, 0xEA8B, 0x9F21, 0xEA8C, 0x9F2C,
+	0xEA8D, 0x9F3E, 0xEA8E, 0x9F4A, 0xEA8F, 0x9F52, 0xEA90, 0x9F54,	0xEA91, 0x9F63, 0xEA92, 0x9F5F, 0xEA93, 0x9F60, 0xEA94, 0x9F61,
+	0xEA95, 0x9F66, 0xEA96, 0x9F67, 0xEA97, 0x9F6C, 0xEA98, 0x9F6A,	0xEA99, 0x9F77, 0xEA9A, 0x9F72, 0xEA9B, 0x9F76, 0xEA9C, 0x9F95,
+	0xEA9D, 0x9F9C, 0xEA9E, 0x9FA0, 0xEA9F, 0x582F, 0xEAA0, 0x69C7,	0xEAA1, 0x9059, 0xEAA2, 0x7464, 0xEAA3, 0x51DC, 0xEAA4, 0x7199,
+	0xFA40, 0x2170, 0xFA41, 0x2171, 0xFA42, 0x2172, 0xFA43, 0x2173,	0xFA44, 0x2174, 0xFA45, 0x2175, 0xFA46, 0x2176, 0xFA47, 0x2177,
+	0xFA48, 0x2178, 0xFA49, 0x2179, 0xFA55, 0xFFE4, 0xFA56, 0xFF07,	0xFA57, 0xFF02, 0xFA5C, 0x7E8A, 0xFA5D, 0x891C, 0xFA5E, 0x9348,
+	0xFA5F, 0x9288, 0xFA60, 0x84DC, 0xFA61, 0x4FC9, 0xFA62, 0x70BB,	0xFA63, 0x6631, 0xFA64, 0x68C8, 0xFA65, 0x92F9, 0xFA66, 0x66FB,
+	0xFA67, 0x5F45, 0xFA68, 0x4E28, 0xFA69, 0x4EE1, 0xFA6A, 0x4EFC,	0xFA6B, 0x4F00, 0xFA6C, 0x4F03, 0xFA6D, 0x4F39, 0xFA6E, 0x4F56,
+	0xFA6F, 0x4F92, 0xFA70, 0x4F8A, 0xFA71, 0x4F9A, 0xFA72, 0x4F94,	0xFA73, 0x4FCD, 0xFA74, 0x5040, 0xFA75, 0x5022, 0xFA76, 0x4FFF,
+	0xFA77, 0x501E, 0xFA78, 0x5046, 0xFA79, 0x5070, 0xFA7A, 0x5042,	0xFA7B, 0x5094, 0xFA7C, 0x50F4, 0xFA7D, 0x50D8, 0xFA7E, 0x514A,
+	0xFA80, 0x5164, 0xFA81, 0x519D, 0xFA82, 0x51BE, 0xFA83, 0x51EC,	0xFA84, 0x5215, 0xFA85, 0x529C, 0xFA86, 0x52A6, 0xFA87, 0x52C0,
+	0xFA88, 0x52DB, 0xFA89, 0x5300, 0xFA8A, 0x5307, 0xFA8B, 0x5324,	0xFA8C, 0x5372, 0xFA8D, 0x5393, 0xFA8E, 0x53B2, 0xFA8F, 0x53DD,
+	0xFA90, 0xFA0E, 0xFA91, 0x549C, 0xFA92, 0x548A, 0xFA93, 0x54A9,	0xFA94, 0x54FF, 0xFA95, 0x5586, 0xFA96, 0x5759, 0xFA97, 0x5765,
+	0xFA98, 0x57AC, 0xFA99, 0x57C8, 0xFA9A, 0x57C7, 0xFA9B, 0xFA0F,	0xFA9C, 0xFA10, 0xFA9D, 0x589E, 0xFA9E, 0x58B2, 0xFA9F, 0x590B,
+	0xFAA0, 0x5953, 0xFAA1, 0x595B, 0xFAA2, 0x595D, 0xFAA3, 0x5963,	0xFAA4, 0x59A4, 0xFAA5, 0x59BA, 0xFAA6, 0x5B56, 0xFAA7, 0x5BC0,
+	0xFAA8, 0x752F, 0xFAA9, 0x5BD8, 0xFAAA, 0x5BEC, 0xFAAB, 0x5C1E,	0xFAAC, 0x5CA6, 0xFAAD, 0x5CBA, 0xFAAE, 0x5CF5, 0xFAAF, 0x5D27,
+	0xFAB0, 0x5D53, 0xFAB1, 0xFA11, 0xFAB2, 0x5D42, 0xFAB3, 0x5D6D,	0xFAB4, 0x5DB8, 0xFAB5, 0x5DB9, 0xFAB6, 0x5DD0, 0xFAB7, 0x5F21,
+	0xFAB8, 0x5F34, 0xFAB9, 0x5F67, 0xFABA, 0x5FB7, 0xFABB, 0x5FDE,	0xFABC, 0x605D, 0xFABD, 0x6085, 0xFABE, 0x608A, 0xFABF, 0x60DE,
+	0xFAC0, 0x60D5, 0xFAC1, 0x6120, 0xFAC2, 0x60F2, 0xFAC3, 0x6111,	0xFAC4, 0x6137, 0xFAC5, 0x6130, 0xFAC6, 0x6198, 0xFAC7, 0x6213,
+	0xFAC8, 0x62A6, 0xFAC9, 0x63F5, 0xFACA, 0x6460, 0xFACB, 0x649D,	0xFACC, 0x64CE, 0xFACD, 0x654E, 0xFACE, 0x6600, 0xFACF, 0x6615,
+	0xFAD0, 0x663B, 0xFAD1, 0x6609, 0xFAD2, 0x662E, 0xFAD3, 0x661E,	0xFAD4, 0x6624, 0xFAD5, 0x6665, 0xFAD6, 0x6657, 0xFAD7, 0x6659,
+	0xFAD8, 0xFA12, 0xFAD9, 0x6673, 0xFADA, 0x6699, 0xFADB, 0x66A0,	0xFADC, 0x66B2, 0xFADD, 0x66BF, 0xFADE, 0x66FA, 0xFADF, 0x670E,
+	0xFAE0, 0xF929, 0xFAE1, 0x6766, 0xFAE2, 0x67BB, 0xFAE3, 0x6852,	0xFAE4, 0x67C0, 0xFAE5, 0x6801, 0xFAE6, 0x6844, 0xFAE7, 0x68CF,
+	0xFAE8, 0xFA13, 0xFAE9, 0x6968, 0xFAEA, 0xFA14, 0xFAEB, 0x6998,	0xFAEC, 0x69E2, 0xFAED, 0x6A30, 0xFAEE, 0x6A6B, 0xFAEF, 0x6A46,
+	0xFAF0, 0x6A73, 0xFAF1, 0x6A7E, 0xFAF2, 0x6AE2, 0xFAF3, 0x6AE4,	0xFAF4, 0x6BD6, 0xFAF5, 0x6C3F, 0xFAF6, 0x6C5C, 0xFAF7, 0x6C86,
+	0xFAF8, 0x6C6F, 0xFAF9, 0x6CDA, 0xFAFA, 0x6D04, 0xFAFB, 0x6D87,	0xFAFC, 0x6D6F, 0xFB40, 0x6D96, 0xFB41, 0x6DAC, 0xFB42, 0x6DCF,
+	0xFB43, 0x6DF8, 0xFB44, 0x6DF2, 0xFB45, 0x6DFC, 0xFB46, 0x6E39,	0xFB47, 0x6E5C, 0xFB48, 0x6E27, 0xFB49, 0x6E3C, 0xFB4A, 0x6EBF,
+	0xFB4B, 0x6F88, 0xFB4C, 0x6FB5, 0xFB4D, 0x6FF5, 0xFB4E, 0x7005,	0xFB4F, 0x7007, 0xFB50, 0x7028, 0xFB51, 0x7085, 0xFB52, 0x70AB,
+	0xFB53, 0x710F, 0xFB54, 0x7104, 0xFB55, 0x715C, 0xFB56, 0x7146,	0xFB57, 0x7147, 0xFB58, 0xFA15, 0xFB59, 0x71C1, 0xFB5A, 0x71FE,
+	0xFB5B, 0x72B1, 0xFB5C, 0x72BE, 0xFB5D, 0x7324, 0xFB5E, 0xFA16,	0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, 0xFB62, 0x73D6,
+	0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, 0xFB66, 0x73F5,	0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, 0xFB6A, 0x742E,
+	0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, 0xFB6E, 0x7501,	0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, 0xFB72, 0x769E,
+	0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, 0xFB76, 0x7746,	0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864,
+	0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19,	0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B,
+	0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB,	0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C,
+	0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52,	0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301,
+	0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6,	0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559,
+	0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20,	0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12,
+	0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE,	0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53,
+	0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12,	0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24,
+	0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26,	0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7,
+	0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4,	0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A,
+	0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E,	0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267,
+	0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7,	0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27,
+	0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325,	0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E,
+	0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370,	0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE,
+	0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448,	0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D,
+	0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743,	0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755,
+	0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B,	0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E,
+	0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72,	0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00,
+	0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19,	0xFC4B, 0x9ED1, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0	/* Simplified Chinese */
+static const WCHAR uni2oem936[] = {	/* Unicode --> GBK pairs */
+	0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3,	0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4,
+	0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA,	0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE,
+	0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9,	0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9,
+	0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1,	0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3,
+	0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8,	0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5,
+	0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1,	0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5,
+	0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9,	0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD,
+	0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1,	0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5,
+	0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1,	0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5,
+	0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9,	0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD,
+	0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1,	0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5,
+	0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7,	0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4,
+	0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9,	0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD,
+	0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1,	0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5,
+	0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9,	0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD,
+	0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1,	0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4,
+	0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9,	0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD,
+	0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1,	0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5,
+	0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9,	0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED,
+	0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1,	0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA,
+	0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF,	0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD,
+	0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846,	0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847,
+	0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1,	0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5,
+	0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9,	0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1,
+	0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5,	0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9,
+	0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA,	0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B,
+	0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6,	0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE,
+	0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE,	0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8,
+	0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF,	0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6,
+	0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4,	0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852,
+	0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1,	0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9,
+	0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD,	0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1,
+	0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7,	0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB,
+	0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF,	0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3,
+	0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7,	0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3,
+	0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7,	0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB,
+	0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF,	0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3,
+	0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6,	0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA,
+	0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE,	0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2,
+	0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6,	0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA,
+	0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE,	0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2,
+	0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6,	0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA,
+	0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE,	0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2,
+	0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6,	0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA,
+	0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE,	0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2,
+	0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6,	0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA,
+	0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE,	0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856,
+	0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A,	0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E,
+	0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862,	0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866,
+	0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A,	0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E,
+	0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872,	0x256F, 0xA873, 0x2570, 0xA874, 0x2571, 0xA875, 0x2572, 0xA876,
+	0x2573, 0xA877, 0x2581, 0xA878, 0x2582, 0xA879, 0x2583, 0xA87A,	0x2584, 0xA87B, 0x2585, 0xA87C, 0x2586, 0xA87D, 0x2587, 0xA87E,
+	0x2588, 0xA880, 0x2589, 0xA881, 0x258A, 0xA882, 0x258B, 0xA883,	0x258C, 0xA884, 0x258D, 0xA885, 0x258E, 0xA886, 0x258F, 0xA887,
+	0x2593, 0xA888, 0x2594, 0xA889, 0x2595, 0xA88A, 0x25A0, 0xA1F6,	0x25A1, 0xA1F5, 0x25B2, 0xA1F8, 0x25B3, 0xA1F7, 0x25BC, 0xA88B,
+	0x25BD, 0xA88C, 0x25C6, 0xA1F4, 0x25C7, 0xA1F3, 0x25CB, 0xA1F0,	0x25CE, 0xA1F2, 0x25CF, 0xA1F1, 0x25E2, 0xA88D, 0x25E3, 0xA88E,
+	0x25E4, 0xA88F, 0x25E5, 0xA890, 0x2605, 0xA1EF, 0x2606, 0xA1EE,	0x2609, 0xA891, 0x2640, 0xA1E2, 0x2642, 0xA1E1, 0x3000, 0xA1A1,
+	0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3005, 0xA1A9,	0x3006, 0xA965, 0x3007, 0xA996, 0x3008, 0xA1B4, 0x3009, 0xA1B5,
+	0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9,	0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BE, 0x3011, 0xA1BF,
+	0x3012, 0xA893, 0x3013, 0xA1FE, 0x3014, 0xA1B2, 0x3015, 0xA1B3,	0x3016, 0xA1BC, 0x3017, 0xA1BD, 0x301D, 0xA894, 0x301E, 0xA895,
+	0x3021, 0xA940, 0x3022, 0xA941, 0x3023, 0xA942, 0x3024, 0xA943,	0x3025, 0xA944, 0x3026, 0xA945, 0x3027, 0xA946, 0x3028, 0xA947,
+	0x3029, 0xA948, 0x3041, 0xA4A1, 0x3042, 0xA4A2, 0x3043, 0xA4A3,	0x3044, 0xA4A4, 0x3045, 0xA4A5, 0x3046, 0xA4A6, 0x3047, 0xA4A7,
+	0x3048, 0xA4A8, 0x3049, 0xA4A9, 0x304A, 0xA4AA, 0x304B, 0xA4AB,	0x304C, 0xA4AC, 0x304D, 0xA4AD, 0x304E, 0xA4AE, 0x304F, 0xA4AF,
+	0x3050, 0xA4B0, 0x3051, 0xA4B1, 0x3052, 0xA4B2, 0x3053, 0xA4B3,	0x3054, 0xA4B4, 0x3055, 0xA4B5, 0x3056, 0xA4B6, 0x3057, 0xA4B7,
+	0x3058, 0xA4B8, 0x3059, 0xA4B9, 0x305A, 0xA4BA, 0x305B, 0xA4BB,	0x305C, 0xA4BC, 0x305D, 0xA4BD, 0x305E, 0xA4BE, 0x305F, 0xA4BF,
+	0x3060, 0xA4C0, 0x3061, 0xA4C1, 0x3062, 0xA4C2, 0x3063, 0xA4C3,	0x3064, 0xA4C4, 0x3065, 0xA4C5, 0x3066, 0xA4C6, 0x3067, 0xA4C7,
+	0x3068, 0xA4C8, 0x3069, 0xA4C9, 0x306A, 0xA4CA, 0x306B, 0xA4CB,	0x306C, 0xA4CC, 0x306D, 0xA4CD, 0x306E, 0xA4CE, 0x306F, 0xA4CF,
+	0x3070, 0xA4D0, 0x3071, 0xA4D1, 0x3072, 0xA4D2, 0x3073, 0xA4D3,	0x3074, 0xA4D4, 0x3075, 0xA4D5, 0x3076, 0xA4D6, 0x3077, 0xA4D7,
+	0x3078, 0xA4D8, 0x3079, 0xA4D9, 0x307A, 0xA4DA, 0x307B, 0xA4DB,	0x307C, 0xA4DC, 0x307D, 0xA4DD, 0x307E, 0xA4DE, 0x307F, 0xA4DF,
+	0x3080, 0xA4E0, 0x3081, 0xA4E1, 0x3082, 0xA4E2, 0x3083, 0xA4E3,	0x3084, 0xA4E4, 0x3085, 0xA4E5, 0x3086, 0xA4E6, 0x3087, 0xA4E7,
+	0x3088, 0xA4E8, 0x3089, 0xA4E9, 0x308A, 0xA4EA, 0x308B, 0xA4EB,	0x308C, 0xA4EC, 0x308D, 0xA4ED, 0x308E, 0xA4EE, 0x308F, 0xA4EF,
+	0x3090, 0xA4F0, 0x3091, 0xA4F1, 0x3092, 0xA4F2, 0x3093, 0xA4F3,	0x309B, 0xA961, 0x309C, 0xA962, 0x309D, 0xA966, 0x309E, 0xA967,
+	0x30A1, 0xA5A1, 0x30A2, 0xA5A2, 0x30A3, 0xA5A3, 0x30A4, 0xA5A4,	0x30A5, 0xA5A5, 0x30A6, 0xA5A6, 0x30A7, 0xA5A7, 0x30A8, 0xA5A8,
+	0x30A9, 0xA5A9, 0x30AA, 0xA5AA, 0x30AB, 0xA5AB, 0x30AC, 0xA5AC,	0x30AD, 0xA5AD, 0x30AE, 0xA5AE, 0x30AF, 0xA5AF, 0x30B0, 0xA5B0,
+	0x30B1, 0xA5B1, 0x30B2, 0xA5B2, 0x30B3, 0xA5B3, 0x30B4, 0xA5B4,	0x30B5, 0xA5B5, 0x30B6, 0xA5B6, 0x30B7, 0xA5B7, 0x30B8, 0xA5B8,
+	0x30B9, 0xA5B9, 0x30BA, 0xA5BA, 0x30BB, 0xA5BB, 0x30BC, 0xA5BC,	0x30BD, 0xA5BD, 0x30BE, 0xA5BE, 0x30BF, 0xA5BF, 0x30C0, 0xA5C0,
+	0x30C1, 0xA5C1, 0x30C2, 0xA5C2, 0x30C3, 0xA5C3, 0x30C4, 0xA5C4,	0x30C5, 0xA5C5, 0x30C6, 0xA5C6, 0x30C7, 0xA5C7, 0x30C8, 0xA5C8,
+	0x30C9, 0xA5C9, 0x30CA, 0xA5CA, 0x30CB, 0xA5CB, 0x30CC, 0xA5CC,	0x30CD, 0xA5CD, 0x30CE, 0xA5CE, 0x30CF, 0xA5CF, 0x30D0, 0xA5D0,
+	0x30D1, 0xA5D1, 0x30D2, 0xA5D2, 0x30D3, 0xA5D3, 0x30D4, 0xA5D4,	0x30D5, 0xA5D5, 0x30D6, 0xA5D6, 0x30D7, 0xA5D7, 0x30D8, 0xA5D8,
+	0x30D9, 0xA5D9, 0x30DA, 0xA5DA, 0x30DB, 0xA5DB, 0x30DC, 0xA5DC,	0x30DD, 0xA5DD, 0x30DE, 0xA5DE, 0x30DF, 0xA5DF, 0x30E0, 0xA5E0,
+	0x30E1, 0xA5E1, 0x30E2, 0xA5E2, 0x30E3, 0xA5E3, 0x30E4, 0xA5E4,	0x30E5, 0xA5E5, 0x30E6, 0xA5E6, 0x30E7, 0xA5E7, 0x30E8, 0xA5E8,
+	0x30E9, 0xA5E9, 0x30EA, 0xA5EA, 0x30EB, 0xA5EB, 0x30EC, 0xA5EC,	0x30ED, 0xA5ED, 0x30EE, 0xA5EE, 0x30EF, 0xA5EF, 0x30F0, 0xA5F0,
+	0x30F1, 0xA5F1, 0x30F2, 0xA5F2, 0x30F3, 0xA5F3, 0x30F4, 0xA5F4,	0x30F5, 0xA5F5, 0x30F6, 0xA5F6, 0x30FC, 0xA960, 0x30FD, 0xA963,
+	0x30FE, 0xA964, 0x3105, 0xA8C5, 0x3106, 0xA8C6, 0x3107, 0xA8C7,	0x3108, 0xA8C8, 0x3109, 0xA8C9, 0x310A, 0xA8CA, 0x310B, 0xA8CB,
+	0x310C, 0xA8CC, 0x310D, 0xA8CD, 0x310E, 0xA8CE, 0x310F, 0xA8CF,	0x3110, 0xA8D0, 0x3111, 0xA8D1, 0x3112, 0xA8D2, 0x3113, 0xA8D3,
+	0x3114, 0xA8D4, 0x3115, 0xA8D5, 0x3116, 0xA8D6, 0x3117, 0xA8D7,	0x3118, 0xA8D8, 0x3119, 0xA8D9, 0x311A, 0xA8DA, 0x311B, 0xA8DB,
+	0x311C, 0xA8DC, 0x311D, 0xA8DD, 0x311E, 0xA8DE, 0x311F, 0xA8DF,	0x3120, 0xA8E0, 0x3121, 0xA8E1, 0x3122, 0xA8E2, 0x3123, 0xA8E3,
+	0x3124, 0xA8E4, 0x3125, 0xA8E5, 0x3126, 0xA8E6, 0x3127, 0xA8E7,	0x3128, 0xA8E8, 0x3129, 0xA8E9, 0x3220, 0xA2E5, 0x3221, 0xA2E6,
+	0x3222, 0xA2E7, 0x3223, 0xA2E8, 0x3224, 0xA2E9, 0x3225, 0xA2EA,	0x3226, 0xA2EB, 0x3227, 0xA2EC, 0x3228, 0xA2ED, 0x3229, 0xA2EE,
+	0x3231, 0xA95A, 0x32A3, 0xA949, 0x338E, 0xA94A, 0x338F, 0xA94B,	0x339C, 0xA94C, 0x339D, 0xA94D, 0x339E, 0xA94E, 0x33A1, 0xA94F,
+	0x33C4, 0xA950, 0x33CE, 0xA951, 0x33D1, 0xA952, 0x33D2, 0xA953,	0x33D5, 0xA954, 0x4E00, 0xD2BB, 0x4E01, 0xB6A1, 0x4E02, 0x8140,
+	0x4E03, 0xC6DF, 0x4E04, 0x8141, 0x4E05, 0x8142, 0x4E06, 0x8143,	0x4E07, 0xCDF2, 0x4E08, 0xD5C9, 0x4E09, 0xC8FD, 0x4E0A, 0xC9CF,
+	0x4E0B, 0xCFC2, 0x4E0C, 0xD8A2, 0x4E0D, 0xB2BB, 0x4E0E, 0xD3EB,	0x4E0F, 0x8144, 0x4E10, 0xD8A4, 0x4E11, 0xB3F3, 0x4E12, 0x8145,
+	0x4E13, 0xD7A8, 0x4E14, 0xC7D2, 0x4E15, 0xD8A7, 0x4E16, 0xCAC0,	0x4E17, 0x8146, 0x4E18, 0xC7F0, 0x4E19, 0xB1FB, 0x4E1A, 0xD2B5,
+	0x4E1B, 0xB4D4, 0x4E1C, 0xB6AB, 0x4E1D, 0xCBBF, 0x4E1E, 0xD8A9,	0x4E1F, 0x8147, 0x4E20, 0x8148, 0x4E21, 0x8149, 0x4E22, 0xB6AA,
+	0x4E23, 0x814A, 0x4E24, 0xC1BD, 0x4E25, 0xD1CF, 0x4E26, 0x814B,	0x4E27, 0xC9A5, 0x4E28, 0xD8AD, 0x4E29, 0x814C, 0x4E2A, 0xB8F6,
+	0x4E2B, 0xD1BE, 0x4E2C, 0xE3DC, 0x4E2D, 0xD6D0, 0x4E2E, 0x814D,	0x4E2F, 0x814E, 0x4E30, 0xB7E1, 0x4E31, 0x814F, 0x4E32, 0xB4AE,
+	0x4E33, 0x8150, 0x4E34, 0xC1D9, 0x4E35, 0x8151, 0x4E36, 0xD8BC,	0x4E37, 0x8152, 0x4E38, 0xCDE8, 0x4E39, 0xB5A4, 0x4E3A, 0xCEAA,
+	0x4E3B, 0xD6F7, 0x4E3C, 0x8153, 0x4E3D, 0xC0F6, 0x4E3E, 0xBED9,	0x4E3F, 0xD8AF, 0x4E40, 0x8154, 0x4E41, 0x8155, 0x4E42, 0x8156,
+	0x4E43, 0xC4CB, 0x4E44, 0x8157, 0x4E45, 0xBEC3, 0x4E46, 0x8158,	0x4E47, 0xD8B1, 0x4E48, 0xC3B4, 0x4E49, 0xD2E5, 0x4E4A, 0x8159,
+	0x4E4B, 0xD6AE, 0x4E4C, 0xCEDA, 0x4E4D, 0xD5A7, 0x4E4E, 0xBAF5,	0x4E4F, 0xB7A6, 0x4E50, 0xC0D6, 0x4E51, 0x815A, 0x4E52, 0xC6B9,
+	0x4E53, 0xC5D2, 0x4E54, 0xC7C7, 0x4E55, 0x815B, 0x4E56, 0xB9D4,	0x4E57, 0x815C, 0x4E58, 0xB3CB, 0x4E59, 0xD2D2, 0x4E5A, 0x815D,
+	0x4E5B, 0x815E, 0x4E5C, 0xD8BF, 0x4E5D, 0xBEC5, 0x4E5E, 0xC6F2,	0x4E5F, 0xD2B2, 0x4E60, 0xCFB0, 0x4E61, 0xCFE7, 0x4E62, 0x815F,
+	0x4E63, 0x8160, 0x4E64, 0x8161, 0x4E65, 0x8162, 0x4E66, 0xCAE9,	0x4E67, 0x8163, 0x4E68, 0x8164, 0x4E69, 0xD8C0, 0x4E6A, 0x8165,
+	0x4E6B, 0x8166, 0x4E6C, 0x8167, 0x4E6D, 0x8168, 0x4E6E, 0x8169,	0x4E6F, 0x816A, 0x4E70, 0xC2F2, 0x4E71, 0xC2D2, 0x4E72, 0x816B,
+	0x4E73, 0xC8E9, 0x4E74, 0x816C, 0x4E75, 0x816D, 0x4E76, 0x816E,	0x4E77, 0x816F, 0x4E78, 0x8170, 0x4E79, 0x8171, 0x4E7A, 0x8172,
+	0x4E7B, 0x8173, 0x4E7C, 0x8174, 0x4E7D, 0x8175, 0x4E7E, 0xC7AC,	0x4E7F, 0x8176, 0x4E80, 0x8177, 0x4E81, 0x8178, 0x4E82, 0x8179,
+	0x4E83, 0x817A, 0x4E84, 0x817B, 0x4E85, 0x817C, 0x4E86, 0xC1CB,	0x4E87, 0x817D, 0x4E88, 0xD3E8, 0x4E89, 0xD5F9, 0x4E8A, 0x817E,
+	0x4E8B, 0xCAC2, 0x4E8C, 0xB6FE, 0x4E8D, 0xD8A1, 0x4E8E, 0xD3DA,	0x4E8F, 0xBFF7, 0x4E90, 0x8180, 0x4E91, 0xD4C6, 0x4E92, 0xBBA5,
+	0x4E93, 0xD8C1, 0x4E94, 0xCEE5, 0x4E95, 0xBEAE, 0x4E96, 0x8181,	0x4E97, 0x8182, 0x4E98, 0xD8A8, 0x4E99, 0x8183, 0x4E9A, 0xD1C7,
+	0x4E9B, 0xD0A9, 0x4E9C, 0x8184, 0x4E9D, 0x8185, 0x4E9E, 0x8186,	0x4E9F, 0xD8BD, 0x4EA0, 0xD9EF, 0x4EA1, 0xCDF6, 0x4EA2, 0xBFBA,
+	0x4EA3, 0x8187, 0x4EA4, 0xBDBB, 0x4EA5, 0xBAA5, 0x4EA6, 0xD2E0,	0x4EA7, 0xB2FA, 0x4EA8, 0xBAE0, 0x4EA9, 0xC4B6, 0x4EAA, 0x8188,
+	0x4EAB, 0xCFED, 0x4EAC, 0xBEA9, 0x4EAD, 0xCDA4, 0x4EAE, 0xC1C1,	0x4EAF, 0x8189, 0x4EB0, 0x818A, 0x4EB1, 0x818B, 0x4EB2, 0xC7D7,
+	0x4EB3, 0xD9F1, 0x4EB4, 0x818C, 0x4EB5, 0xD9F4, 0x4EB6, 0x818D,	0x4EB7, 0x818E, 0x4EB8, 0x818F, 0x4EB9, 0x8190, 0x4EBA, 0xC8CB,
+	0x4EBB, 0xD8E9, 0x4EBC, 0x8191, 0x4EBD, 0x8192, 0x4EBE, 0x8193,	0x4EBF, 0xD2DA, 0x4EC0, 0xCAB2, 0x4EC1, 0xC8CA, 0x4EC2, 0xD8EC,
+	0x4EC3, 0xD8EA, 0x4EC4, 0xD8C6, 0x4EC5, 0xBDF6, 0x4EC6, 0xC6CD,	0x4EC7, 0xB3F0, 0x4EC8, 0x8194, 0x4EC9, 0xD8EB, 0x4ECA, 0xBDF1,
+	0x4ECB, 0xBDE9, 0x4ECC, 0x8195, 0x4ECD, 0xC8D4, 0x4ECE, 0xB4D3,	0x4ECF, 0x8196, 0x4ED0, 0x8197, 0x4ED1, 0xC2D8, 0x4ED2, 0x8198,
+	0x4ED3, 0xB2D6, 0x4ED4, 0xD7D0, 0x4ED5, 0xCACB, 0x4ED6, 0xCBFB,	0x4ED7, 0xD5CC, 0x4ED8, 0xB8B6, 0x4ED9, 0xCFC9, 0x4EDA, 0x8199,
+	0x4EDB, 0x819A, 0x4EDC, 0x819B, 0x4EDD, 0xD9DA, 0x4EDE, 0xD8F0,	0x4EDF, 0xC7AA, 0x4EE0, 0x819C, 0x4EE1, 0xD8EE, 0x4EE2, 0x819D,
+	0x4EE3, 0xB4FA, 0x4EE4, 0xC1EE, 0x4EE5, 0xD2D4, 0x4EE6, 0x819E,	0x4EE7, 0x819F, 0x4EE8, 0xD8ED, 0x4EE9, 0x81A0, 0x4EEA, 0xD2C7,
+	0x4EEB, 0xD8EF, 0x4EEC, 0xC3C7, 0x4EED, 0x81A1, 0x4EEE, 0x81A2,	0x4EEF, 0x81A3, 0x4EF0, 0xD1F6, 0x4EF1, 0x81A4, 0x4EF2, 0xD6D9,
+	0x4EF3, 0xD8F2, 0x4EF4, 0x81A5, 0x4EF5, 0xD8F5, 0x4EF6, 0xBCFE,	0x4EF7, 0xBCDB, 0x4EF8, 0x81A6, 0x4EF9, 0x81A7, 0x4EFA, 0x81A8,
+	0x4EFB, 0xC8CE, 0x4EFC, 0x81A9, 0x4EFD, 0xB7DD, 0x4EFE, 0x81AA,	0x4EFF, 0xB7C2, 0x4F00, 0x81AB, 0x4F01, 0xC6F3, 0x4F02, 0x81AC,
+	0x4F03, 0x81AD, 0x4F04, 0x81AE, 0x4F05, 0x81AF, 0x4F06, 0x81B0,	0x4F07, 0x81B1, 0x4F08, 0x81B2, 0x4F09, 0xD8F8, 0x4F0A, 0xD2C1,
+	0x4F0B, 0x81B3, 0x4F0C, 0x81B4, 0x4F0D, 0xCEE9, 0x4F0E, 0xBCBF,	0x4F0F, 0xB7FC, 0x4F10, 0xB7A5, 0x4F11, 0xD0DD, 0x4F12, 0x81B5,
+	0x4F13, 0x81B6, 0x4F14, 0x81B7, 0x4F15, 0x81B8, 0x4F16, 0x81B9,	0x4F17, 0xD6DA, 0x4F18, 0xD3C5, 0x4F19, 0xBBEF, 0x4F1A, 0xBBE1,
+	0x4F1B, 0xD8F1, 0x4F1C, 0x81BA, 0x4F1D, 0x81BB, 0x4F1E, 0xC9A1,	0x4F1F, 0xCEB0, 0x4F20, 0xB4AB, 0x4F21, 0x81BC, 0x4F22, 0xD8F3,
+	0x4F23, 0x81BD, 0x4F24, 0xC9CB, 0x4F25, 0xD8F6, 0x4F26, 0xC2D7,	0x4F27, 0xD8F7, 0x4F28, 0x81BE, 0x4F29, 0x81BF, 0x4F2A, 0xCEB1,
+	0x4F2B, 0xD8F9, 0x4F2C, 0x81C0, 0x4F2D, 0x81C1, 0x4F2E, 0x81C2,	0x4F2F, 0xB2AE, 0x4F30, 0xB9C0, 0x4F31, 0x81C3, 0x4F32, 0xD9A3,
+	0x4F33, 0x81C4, 0x4F34, 0xB0E9, 0x4F35, 0x81C5, 0x4F36, 0xC1E6,	0x4F37, 0x81C6, 0x4F38, 0xC9EC, 0x4F39, 0x81C7, 0x4F3A, 0xCBC5,
+	0x4F3B, 0x81C8, 0x4F3C, 0xCBC6, 0x4F3D, 0xD9A4, 0x4F3E, 0x81C9,	0x4F3F, 0x81CA, 0x4F40, 0x81CB, 0x4F41, 0x81CC, 0x4F42, 0x81CD,
+	0x4F43, 0xB5E8, 0x4F44, 0x81CE, 0x4F45, 0x81CF, 0x4F46, 0xB5AB,	0x4F47, 0x81D0, 0x4F48, 0x81D1, 0x4F49, 0x81D2, 0x4F4A, 0x81D3,
+	0x4F4B, 0x81D4, 0x4F4C, 0x81D5, 0x4F4D, 0xCEBB, 0x4F4E, 0xB5CD,	0x4F4F, 0xD7A1, 0x4F50, 0xD7F4, 0x4F51, 0xD3D3, 0x4F52, 0x81D6,
+	0x4F53, 0xCCE5, 0x4F54, 0x81D7, 0x4F55, 0xBACE, 0x4F56, 0x81D8,	0x4F57, 0xD9A2, 0x4F58, 0xD9DC, 0x4F59, 0xD3E0, 0x4F5A, 0xD8FD,
+	0x4F5B, 0xB7F0, 0x4F5C, 0xD7F7, 0x4F5D, 0xD8FE, 0x4F5E, 0xD8FA,	0x4F5F, 0xD9A1, 0x4F60, 0xC4E3, 0x4F61, 0x81D9, 0x4F62, 0x81DA,
+	0x4F63, 0xD3B6, 0x4F64, 0xD8F4, 0x4F65, 0xD9DD, 0x4F66, 0x81DB,	0x4F67, 0xD8FB, 0x4F68, 0x81DC, 0x4F69, 0xC5E5, 0x4F6A, 0x81DD,
+	0x4F6B, 0x81DE, 0x4F6C, 0xC0D0, 0x4F6D, 0x81DF, 0x4F6E, 0x81E0,	0x4F6F, 0xD1F0, 0x4F70, 0xB0DB, 0x4F71, 0x81E1, 0x4F72, 0x81E2,
+	0x4F73, 0xBCD1, 0x4F74, 0xD9A6, 0x4F75, 0x81E3, 0x4F76, 0xD9A5,	0x4F77, 0x81E4, 0x4F78, 0x81E5, 0x4F79, 0x81E6, 0x4F7A, 0x81E7,
+	0x4F7B, 0xD9AC, 0x4F7C, 0xD9AE, 0x4F7D, 0x81E8, 0x4F7E, 0xD9AB,	0x4F7F, 0xCAB9, 0x4F80, 0x81E9, 0x4F81, 0x81EA, 0x4F82, 0x81EB,
+	0x4F83, 0xD9A9, 0x4F84, 0xD6B6, 0x4F85, 0x81EC, 0x4F86, 0x81ED,	0x4F87, 0x81EE, 0x4F88, 0xB3DE, 0x4F89, 0xD9A8, 0x4F8A, 0x81EF,
+	0x4F8B, 0xC0FD, 0x4F8C, 0x81F0, 0x4F8D, 0xCACC, 0x4F8E, 0x81F1,	0x4F8F, 0xD9AA, 0x4F90, 0x81F2, 0x4F91, 0xD9A7, 0x4F92, 0x81F3,
+	0x4F93, 0x81F4, 0x4F94, 0xD9B0, 0x4F95, 0x81F5, 0x4F96, 0x81F6,	0x4F97, 0xB6B1, 0x4F98, 0x81F7, 0x4F99, 0x81F8, 0x4F9A, 0x81F9,
+	0x4F9B, 0xB9A9, 0x4F9C, 0x81FA, 0x4F9D, 0xD2C0, 0x4F9E, 0x81FB,	0x4F9F, 0x81FC, 0x4FA0, 0xCFC0, 0x4FA1, 0x81FD, 0x4FA2, 0x81FE,
+	0x4FA3, 0xC2C2, 0x4FA4, 0x8240, 0x4FA5, 0xBDC4, 0x4FA6, 0xD5EC,	0x4FA7, 0xB2E0, 0x4FA8, 0xC7C8, 0x4FA9, 0xBFEB, 0x4FAA, 0xD9AD,
+	0x4FAB, 0x8241, 0x4FAC, 0xD9AF, 0x4FAD, 0x8242, 0x4FAE, 0xCEEA,	0x4FAF, 0xBAEE, 0x4FB0, 0x8243, 0x4FB1, 0x8244, 0x4FB2, 0x8245,
+	0x4FB3, 0x8246, 0x4FB4, 0x8247, 0x4FB5, 0xC7D6, 0x4FB6, 0x8248,	0x4FB7, 0x8249, 0x4FB8, 0x824A, 0x4FB9, 0x824B, 0x4FBA, 0x824C,
+	0x4FBB, 0x824D, 0x4FBC, 0x824E, 0x4FBD, 0x824F, 0x4FBE, 0x8250,	0x4FBF, 0xB1E3, 0x4FC0, 0x8251, 0x4FC1, 0x8252, 0x4FC2, 0x8253,
+	0x4FC3, 0xB4D9, 0x4FC4, 0xB6ED, 0x4FC5, 0xD9B4, 0x4FC6, 0x8254,	0x4FC7, 0x8255, 0x4FC8, 0x8256, 0x4FC9, 0x8257, 0x4FCA, 0xBFA1,
+	0x4FCB, 0x8258, 0x4FCC, 0x8259, 0x4FCD, 0x825A, 0x4FCE, 0xD9DE,	0x4FCF, 0xC7CE, 0x4FD0, 0xC0FE, 0x4FD1, 0xD9B8, 0x4FD2, 0x825B,
+	0x4FD3, 0x825C, 0x4FD4, 0x825D, 0x4FD5, 0x825E, 0x4FD6, 0x825F,	0x4FD7, 0xCBD7, 0x4FD8, 0xB7FD, 0x4FD9, 0x8260, 0x4FDA, 0xD9B5,
+	0x4FDB, 0x8261, 0x4FDC, 0xD9B7, 0x4FDD, 0xB1A3, 0x4FDE, 0xD3E1,	0x4FDF, 0xD9B9, 0x4FE0, 0x8262, 0x4FE1, 0xD0C5, 0x4FE2, 0x8263,
+	0x4FE3, 0xD9B6, 0x4FE4, 0x8264, 0x4FE5, 0x8265, 0x4FE6, 0xD9B1,	0x4FE7, 0x8266, 0x4FE8, 0xD9B2, 0x4FE9, 0xC1A9, 0x4FEA, 0xD9B3,
+	0x4FEB, 0x8267, 0x4FEC, 0x8268, 0x4FED, 0xBCF3, 0x4FEE, 0xD0DE,	0x4FEF, 0xB8A9, 0x4FF0, 0x8269, 0x4FF1, 0xBEE3, 0x4FF2, 0x826A,
+	0x4FF3, 0xD9BD, 0x4FF4, 0x826B, 0x4FF5, 0x826C, 0x4FF6, 0x826D,	0x4FF7, 0x826E, 0x4FF8, 0xD9BA, 0x4FF9, 0x826F, 0x4FFA, 0xB0B3,
+	0x4FFB, 0x8270, 0x4FFC, 0x8271, 0x4FFD, 0x8272, 0x4FFE, 0xD9C2,	0x4FFF, 0x8273, 0x5000, 0x8274, 0x5001, 0x8275, 0x5002, 0x8276,
+	0x5003, 0x8277, 0x5004, 0x8278, 0x5005, 0x8279, 0x5006, 0x827A,	0x5007, 0x827B, 0x5008, 0x827C, 0x5009, 0x827D, 0x500A, 0x827E,
+	0x500B, 0x8280, 0x500C, 0xD9C4, 0x500D, 0xB1B6, 0x500E, 0x8281,	0x500F, 0xD9BF, 0x5010, 0x8282, 0x5011, 0x8283, 0x5012, 0xB5B9,
+	0x5013, 0x8284, 0x5014, 0xBEF3, 0x5015, 0x8285, 0x5016, 0x8286,	0x5017, 0x8287, 0x5018, 0xCCC8, 0x5019, 0xBAF2, 0x501A, 0xD2D0,
+	0x501B, 0x8288, 0x501C, 0xD9C3, 0x501D, 0x8289, 0x501E, 0x828A,	0x501F, 0xBDE8, 0x5020, 0x828B, 0x5021, 0xB3AB, 0x5022, 0x828C,
+	0x5023, 0x828D, 0x5024, 0x828E, 0x5025, 0xD9C5, 0x5026, 0xBEEB,	0x5027, 0x828F, 0x5028, 0xD9C6, 0x5029, 0xD9BB, 0x502A, 0xC4DF,
+	0x502B, 0x8290, 0x502C, 0xD9BE, 0x502D, 0xD9C1, 0x502E, 0xD9C0,	0x502F, 0x8291, 0x5030, 0x8292, 0x5031, 0x8293, 0x5032, 0x8294,
+	0x5033, 0x8295, 0x5034, 0x8296, 0x5035, 0x8297, 0x5036, 0x8298,	0x5037, 0x8299, 0x5038, 0x829A, 0x5039, 0x829B, 0x503A, 0xD5AE,
+	0x503B, 0x829C, 0x503C, 0xD6B5, 0x503D, 0x829D, 0x503E, 0xC7E3,	0x503F, 0x829E, 0x5040, 0x829F, 0x5041, 0x82A0, 0x5042, 0x82A1,
+	0x5043, 0xD9C8, 0x5044, 0x82A2, 0x5045, 0x82A3, 0x5046, 0x82A4,	0x5047, 0xBCD9, 0x5048, 0xD9CA, 0x5049, 0x82A5, 0x504A, 0x82A6,
+	0x504B, 0x82A7, 0x504C, 0xD9BC, 0x504D, 0x82A8, 0x504E, 0xD9CB,	0x504F, 0xC6AB, 0x5050, 0x82A9, 0x5051, 0x82AA, 0x5052, 0x82AB,
+	0x5053, 0x82AC, 0x5054, 0x82AD, 0x5055, 0xD9C9, 0x5056, 0x82AE,	0x5057, 0x82AF, 0x5058, 0x82B0, 0x5059, 0x82B1, 0x505A, 0xD7F6,
+	0x505B, 0x82B2, 0x505C, 0xCDA3, 0x505D, 0x82B3, 0x505E, 0x82B4,	0x505F, 0x82B5, 0x5060, 0x82B6, 0x5061, 0x82B7, 0x5062, 0x82B8,
+	0x5063, 0x82B9, 0x5064, 0x82BA, 0x5065, 0xBDA1, 0x5066, 0x82BB,	0x5067, 0x82BC, 0x5068, 0x82BD, 0x5069, 0x82BE, 0x506A, 0x82BF,
+	0x506B, 0x82C0, 0x506C, 0xD9CC, 0x506D, 0x82C1, 0x506E, 0x82C2,	0x506F, 0x82C3, 0x5070, 0x82C4, 0x5071, 0x82C5, 0x5072, 0x82C6,
+	0x5073, 0x82C7, 0x5074, 0x82C8, 0x5075, 0x82C9, 0x5076, 0xC5BC,	0x5077, 0xCDB5, 0x5078, 0x82CA, 0x5079, 0x82CB, 0x507A, 0x82CC,
+	0x507B, 0xD9CD, 0x507C, 0x82CD, 0x507D, 0x82CE, 0x507E, 0xD9C7,	0x507F, 0xB3A5, 0x5080, 0xBFFE, 0x5081, 0x82CF, 0x5082, 0x82D0,
+	0x5083, 0x82D1, 0x5084, 0x82D2, 0x5085, 0xB8B5, 0x5086, 0x82D3,	0x5087, 0x82D4, 0x5088, 0xC0FC, 0x5089, 0x82D5, 0x508A, 0x82D6,
+	0x508B, 0x82D7, 0x508C, 0x82D8, 0x508D, 0xB0F8, 0x508E, 0x82D9,	0x508F, 0x82DA, 0x5090, 0x82DB, 0x5091, 0x82DC, 0x5092, 0x82DD,
+	0x5093, 0x82DE, 0x5094, 0x82DF, 0x5095, 0x82E0, 0x5096, 0x82E1,	0x5097, 0x82E2, 0x5098, 0x82E3, 0x5099, 0x82E4, 0x509A, 0x82E5,
+	0x509B, 0x82E6, 0x509C, 0x82E7, 0x509D, 0x82E8, 0x509E, 0x82E9,	0x509F, 0x82EA, 0x50A0, 0x82EB, 0x50A1, 0x82EC, 0x50A2, 0x82ED,
+	0x50A3, 0xB4F6, 0x50A4, 0x82EE, 0x50A5, 0xD9CE, 0x50A6, 0x82EF,	0x50A7, 0xD9CF, 0x50A8, 0xB4A2, 0x50A9, 0xD9D0, 0x50AA, 0x82F0,
+	0x50AB, 0x82F1, 0x50AC, 0xB4DF, 0x50AD, 0x82F2, 0x50AE, 0x82F3,	0x50AF, 0x82F4, 0x50B0, 0x82F5, 0x50B1, 0x82F6, 0x50B2, 0xB0C1,
+	0x50B3, 0x82F7, 0x50B4, 0x82F8, 0x50B5, 0x82F9, 0x50B6, 0x82FA,	0x50B7, 0x82FB, 0x50B8, 0x82FC, 0x50B9, 0x82FD, 0x50BA, 0xD9D1,
+	0x50BB, 0xC9B5, 0x50BC, 0x82FE, 0x50BD, 0x8340, 0x50BE, 0x8341,	0x50BF, 0x8342, 0x50C0, 0x8343, 0x50C1, 0x8344, 0x50C2, 0x8345,
+	0x50C3, 0x8346, 0x50C4, 0x8347, 0x50C5, 0x8348, 0x50C6, 0x8349,	0x50C7, 0x834A, 0x50C8, 0x834B, 0x50C9, 0x834C, 0x50CA, 0x834D,
+	0x50CB, 0x834E, 0x50CC, 0x834F, 0x50CD, 0x8350, 0x50CE, 0x8351,	0x50CF, 0xCFF1, 0x50D0, 0x8352, 0x50D1, 0x8353, 0x50D2, 0x8354,
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+	0x5153, 0x83BB, 0x5154, 0xCDC3, 0x5155, 0xD9EE, 0x5156, 0xD9F0,	0x5157, 0x83BC, 0x5158, 0x83BD, 0x5159, 0x83BE, 0x515A, 0xB5B3,
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+	0x517B, 0xD1F8, 0x517C, 0xBCE6, 0x517D, 0xCADE, 0x517E, 0x83CE,	0x517F, 0x83CF, 0x5180, 0xBCBD, 0x5181, 0xD9E6, 0x5182, 0xD8E7,
+	0x5183, 0x83D0, 0x5184, 0x83D1, 0x5185, 0xC4DA, 0x5186, 0x83D2,	0x5187, 0x83D3, 0x5188, 0xB8D4, 0x5189, 0xC8BD, 0x518A, 0x83D4,
+	0x518B, 0x83D5, 0x518C, 0xB2E1, 0x518D, 0xD4D9, 0x518E, 0x83D6,	0x518F, 0x83D7, 0x5190, 0x83D8, 0x5191, 0x83D9, 0x5192, 0xC3B0,
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+	0x519B, 0xBEFC, 0x519C, 0xC5A9, 0x519D, 0x83DE, 0x519E, 0x83DF,	0x519F, 0x83E0, 0x51A0, 0xB9DA, 0x51A1, 0x83E1, 0x51A2, 0xDAA3,
+	0x51A3, 0x83E2, 0x51A4, 0xD4A9, 0x51A5, 0xDAA4, 0x51A6, 0x83E3,	0x51A7, 0x83E4, 0x51A8, 0x83E5, 0x51A9, 0x83E6, 0x51AA, 0x83E7,
+	0x51AB, 0xD9FB, 0x51AC, 0xB6AC, 0x51AD, 0x83E8, 0x51AE, 0x83E9,	0x51AF, 0xB7EB, 0x51B0, 0xB1F9, 0x51B1, 0xD9FC, 0x51B2, 0xB3E5,
+	0x51B3, 0xBEF6, 0x51B4, 0x83EA, 0x51B5, 0xBFF6, 0x51B6, 0xD2B1,	0x51B7, 0xC0E4, 0x51B8, 0x83EB, 0x51B9, 0x83EC, 0x51BA, 0x83ED,
+	0x51BB, 0xB6B3, 0x51BC, 0xD9FE, 0x51BD, 0xD9FD, 0x51BE, 0x83EE,	0x51BF, 0x83EF, 0x51C0, 0xBEBB, 0x51C1, 0x83F0, 0x51C2, 0x83F1,
+	0x51C3, 0x83F2, 0x51C4, 0xC6E0, 0x51C5, 0x83F3, 0x51C6, 0xD7BC,	0x51C7, 0xDAA1, 0x51C8, 0x83F4, 0x51C9, 0xC1B9, 0x51CA, 0x83F5,
+	0x51CB, 0xB5F2, 0x51CC, 0xC1E8, 0x51CD, 0x83F6, 0x51CE, 0x83F7,	0x51CF, 0xBCF5, 0x51D0, 0x83F8, 0x51D1, 0xB4D5, 0x51D2, 0x83F9,
+	0x51D3, 0x83FA, 0x51D4, 0x83FB, 0x51D5, 0x83FC, 0x51D6, 0x83FD,	0x51D7, 0x83FE, 0x51D8, 0x8440, 0x51D9, 0x8441, 0x51DA, 0x8442,
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+	0x51E3, 0x8447, 0x51E4, 0xB7EF, 0x51E5, 0x8448, 0x51E6, 0x8449,	0x51E7, 0x844A, 0x51E8, 0x844B, 0x51E9, 0x844C, 0x51EA, 0x844D,
+	0x51EB, 0xD9EC, 0x51EC, 0x844E, 0x51ED, 0xC6BE, 0x51EE, 0x844F,	0x51EF, 0xBFAD, 0x51F0, 0xBBCB, 0x51F1, 0x8450, 0x51F2, 0x8451,
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+	0x5203, 0xC8D0, 0x5204, 0x8455, 0x5205, 0x8456, 0x5206, 0xB7D6,	0x5207, 0xC7D0, 0x5208, 0xD8D7, 0x5209, 0x8457, 0x520A, 0xBFAF,
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+	0x5243, 0xCCEA, 0x5244, 0x8471, 0x5245, 0x8472, 0x5246, 0x8473,	0x5247, 0x8474, 0x5248, 0x8475, 0x5249, 0x8476, 0x524A, 0xCFF7,
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+	0x5273, 0x8491, 0x5274, 0x8492, 0x5275, 0x8493, 0x5276, 0x8494,	0x5277, 0x8495, 0x5278, 0x8496, 0x5279, 0x8497, 0x527A, 0x8498,
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+	0x528B, 0x84A4, 0x528C, 0x84A5, 0x528D, 0x84A6, 0x528E, 0x84A7,	0x528F, 0x84A8, 0x5290, 0xD8E5, 0x5291, 0x84A9, 0x5292, 0x84AA,
+	0x5293, 0xD8E6, 0x5294, 0x84AB, 0x5295, 0x84AC, 0x5296, 0x84AD,	0x5297, 0x84AE, 0x5298, 0x84AF, 0x5299, 0x84B0, 0x529A, 0x84B1,
+	0x529B, 0xC1A6, 0x529C, 0x84B2, 0x529D, 0xC8B0, 0x529E, 0xB0EC,	0x529F, 0xB9A6, 0x52A0, 0xBCD3, 0x52A1, 0xCEF1, 0x52A2, 0xDBBD,
+	0x52A3, 0xC1D3, 0x52A4, 0x84B3, 0x52A5, 0x84B4, 0x52A6, 0x84B5,	0x52A7, 0x84B6, 0x52A8, 0xB6AF, 0x52A9, 0xD6FA, 0x52AA, 0xC5AC,
+	0x52AB, 0xBDD9, 0x52AC, 0xDBBE, 0x52AD, 0xDBBF, 0x52AE, 0x84B7,	0x52AF, 0x84B8, 0x52B0, 0x84B9, 0x52B1, 0xC0F8, 0x52B2, 0xBEA2,
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+	0x52BB, 0x84C1, 0x52BC, 0x84C2, 0x52BD, 0x84C3, 0x52BE, 0xDBC0,	0x52BF, 0xCAC6, 0x52C0, 0x84C4, 0x52C1, 0x84C5, 0x52C2, 0x84C6,
+	0x52C3, 0xB2AA, 0x52C4, 0x84C7, 0x52C5, 0x84C8, 0x52C6, 0x84C9,	0x52C7, 0xD3C2, 0x52C8, 0x84CA, 0x52C9, 0xC3E3, 0x52CA, 0x84CB,
+	0x52CB, 0xD1AB, 0x52CC, 0x84CC, 0x52CD, 0x84CD, 0x52CE, 0x84CE,	0x52CF, 0x84CF, 0x52D0, 0xDBC2, 0x52D1, 0x84D0, 0x52D2, 0xC0D5,
+	0x52D3, 0x84D1, 0x52D4, 0x84D2, 0x52D5, 0x84D3, 0x52D6, 0xDBC3,	0x52D7, 0x84D4, 0x52D8, 0xBFB1, 0x52D9, 0x84D5, 0x52DA, 0x84D6,
+	0x52DB, 0x84D7, 0x52DC, 0x84D8, 0x52DD, 0x84D9, 0x52DE, 0x84DA,	0x52DF, 0xC4BC, 0x52E0, 0x84DB, 0x52E1, 0x84DC, 0x52E2, 0x84DD,
+	0x52E3, 0x84DE, 0x52E4, 0xC7DA, 0x52E5, 0x84DF, 0x52E6, 0x84E0,	0x52E7, 0x84E1, 0x52E8, 0x84E2, 0x52E9, 0x84E3, 0x52EA, 0x84E4,
+	0x52EB, 0x84E5, 0x52EC, 0x84E6, 0x52ED, 0x84E7, 0x52EE, 0x84E8,	0x52EF, 0x84E9, 0x52F0, 0xDBC4, 0x52F1, 0x84EA, 0x52F2, 0x84EB,
+	0x52F3, 0x84EC, 0x52F4, 0x84ED, 0x52F5, 0x84EE, 0x52F6, 0x84EF,	0x52F7, 0x84F0, 0x52F8, 0x84F1, 0x52F9, 0xD9E8, 0x52FA, 0xC9D7,
+	0x52FB, 0x84F2, 0x52FC, 0x84F3, 0x52FD, 0x84F4, 0x52FE, 0xB9B4,	0x52FF, 0xCEF0, 0x5300, 0xD4C8, 0x5301, 0x84F5, 0x5302, 0x84F6,
+	0x5303, 0x84F7, 0x5304, 0x84F8, 0x5305, 0xB0FC, 0x5306, 0xB4D2,	0x5307, 0x84F9, 0x5308, 0xD0D9, 0x5309, 0x84FA, 0x530A, 0x84FB,
+	0x530B, 0x84FC, 0x530C, 0x84FD, 0x530D, 0xD9E9, 0x530E, 0x84FE,	0x530F, 0xDECB, 0x5310, 0xD9EB, 0x5311, 0x8540, 0x5312, 0x8541,
+	0x5313, 0x8542, 0x5314, 0x8543, 0x5315, 0xD8B0, 0x5316, 0xBBAF,	0x5317, 0xB1B1, 0x5318, 0x8544, 0x5319, 0xB3D7, 0x531A, 0xD8CE,
+	0x531B, 0x8545, 0x531C, 0x8546, 0x531D, 0xD4D1, 0x531E, 0x8547,	0x531F, 0x8548, 0x5320, 0xBDB3, 0x5321, 0xBFEF, 0x5322, 0x8549,
+	0x5323, 0xCFBB, 0x5324, 0x854A, 0x5325, 0x854B, 0x5326, 0xD8D0,	0x5327, 0x854C, 0x5328, 0x854D, 0x5329, 0x854E, 0x532A, 0xB7CB,
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+	0x5333, 0x8556, 0x5334, 0x8557, 0x5335, 0x8558, 0x5336, 0x8559,	0x5337, 0x855A, 0x5338, 0x855B, 0x5339, 0xC6A5, 0x533A, 0xC7F8,
+	0x533B, 0xD2BD, 0x533C, 0x855C, 0x533D, 0x855D, 0x533E, 0xD8D2,	0x533F, 0xC4E4, 0x5340, 0x855E, 0x5341, 0xCAAE, 0x5342, 0x855F,
+	0x5343, 0xC7A7, 0x5344, 0x8560, 0x5345, 0xD8A6, 0x5346, 0x8561,	0x5347, 0xC9FD, 0x5348, 0xCEE7, 0x5349, 0xBBDC, 0x534A, 0xB0EB,
+	0x534B, 0x8562, 0x534C, 0x8563, 0x534D, 0x8564, 0x534E, 0xBBAA,	0x534F, 0xD0AD, 0x5350, 0x8565, 0x5351, 0xB1B0, 0x5352, 0xD7E4,
+	0x5353, 0xD7BF, 0x5354, 0x8566, 0x5355, 0xB5A5, 0x5356, 0xC2F4,	0x5357, 0xC4CF, 0x5358, 0x8567, 0x5359, 0x8568, 0x535A, 0xB2A9,
+	0x535B, 0x8569, 0x535C, 0xB2B7, 0x535D, 0x856A, 0x535E, 0xB1E5,	0x535F, 0xDFB2, 0x5360, 0xD5BC, 0x5361, 0xBFA8, 0x5362, 0xC2AC,
+	0x5363, 0xD8D5, 0x5364, 0xC2B1, 0x5365, 0x856B, 0x5366, 0xD8D4,	0x5367, 0xCED4, 0x5368, 0x856C, 0x5369, 0xDAE0, 0x536A, 0x856D,
+	0x536B, 0xCEC0, 0x536C, 0x856E, 0x536D, 0x856F, 0x536E, 0xD8B4,	0x536F, 0xC3AE, 0x5370, 0xD3A1, 0x5371, 0xCEA3, 0x5372, 0x8570,
+	0x5373, 0xBCB4, 0x5374, 0xC8B4, 0x5375, 0xC2D1, 0x5376, 0x8571,	0x5377, 0xBEED, 0x5378, 0xD0B6, 0x5379, 0x8572, 0x537A, 0xDAE1,
+	0x537B, 0x8573, 0x537C, 0x8574, 0x537D, 0x8575, 0x537E, 0x8576,	0x537F, 0xC7E4, 0x5380, 0x8577, 0x5381, 0x8578, 0x5382, 0xB3A7,
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+	0x58CB, 0x89B3, 0x58CC, 0x89B4, 0x58CD, 0x89B5, 0x58CE, 0x89B6,	0x58CF, 0x89B7, 0x58D0, 0x89B8, 0x58D1, 0xDBD6, 0x58D2, 0x89B9,
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+	0x591B, 0x89EF, 0x591C, 0xD2B9, 0x591D, 0x89F0, 0x591E, 0x89F1,	0x591F, 0xB9BB, 0x5920, 0x89F2, 0x5921, 0x89F3, 0x5922, 0x89F4,
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+	0x592B, 0xB7F2, 0x592C, 0x89F8, 0x592D, 0xD8B2, 0x592E, 0xD1EB,	0x592F, 0xBABB, 0x5930, 0x89F9, 0x5931, 0xCAA7, 0x5932, 0x89FA,
+	0x5933, 0x89FB, 0x5934, 0xCDB7, 0x5935, 0x89FC, 0x5936, 0x89FD,	0x5937, 0xD2C4, 0x5938, 0xBFE4, 0x5939, 0xBCD0, 0x593A, 0xB6E1,
+	0x593B, 0x89FE, 0x593C, 0xDEC5, 0x593D, 0x8A40, 0x593E, 0x8A41,	0x593F, 0x8A42, 0x5940, 0x8A43, 0x5941, 0xDEC6, 0x5942, 0xDBBC,
+	0x5943, 0x8A44, 0x5944, 0xD1D9, 0x5945, 0x8A45, 0x5946, 0x8A46,	0x5947, 0xC6E6, 0x5948, 0xC4CE, 0x5949, 0xB7EE, 0x594A, 0x8A47,
+	0x594B, 0xB7DC, 0x594C, 0x8A48, 0x594D, 0x8A49, 0x594E, 0xBFFC,	0x594F, 0xD7E0, 0x5950, 0x8A4A, 0x5951, 0xC6F5, 0x5952, 0x8A4B,
+	0x5953, 0x8A4C, 0x5954, 0xB1BC, 0x5955, 0xDEC8, 0x5956, 0xBDB1,	0x5957, 0xCCD7, 0x5958, 0xDECA, 0x5959, 0x8A4D, 0x595A, 0xDEC9,
+	0x595B, 0x8A4E, 0x595C, 0x8A4F, 0x595D, 0x8A50, 0x595E, 0x8A51,	0x595F, 0x8A52, 0x5960, 0xB5EC, 0x5961, 0x8A53, 0x5962, 0xC9DD,
+	0x5963, 0x8A54, 0x5964, 0x8A55, 0x5965, 0xB0C2, 0x5966, 0x8A56,	0x5967, 0x8A57, 0x5968, 0x8A58, 0x5969, 0x8A59, 0x596A, 0x8A5A,
+	0x596B, 0x8A5B, 0x596C, 0x8A5C, 0x596D, 0x8A5D, 0x596E, 0x8A5E,	0x596F, 0x8A5F, 0x5970, 0x8A60, 0x5971, 0x8A61, 0x5972, 0x8A62,
+	0x5973, 0xC5AE, 0x5974, 0xC5AB, 0x5975, 0x8A63, 0x5976, 0xC4CC,	0x5977, 0x8A64, 0x5978, 0xBCE9, 0x5979, 0xCBFD, 0x597A, 0x8A65,
+	0x597B, 0x8A66, 0x597C, 0x8A67, 0x597D, 0xBAC3, 0x597E, 0x8A68,	0x597F, 0x8A69, 0x5980, 0x8A6A, 0x5981, 0xE5F9, 0x5982, 0xC8E7,
+	0x5983, 0xE5FA, 0x5984, 0xCDFD, 0x5985, 0x8A6B, 0x5986, 0xD7B1,	0x5987, 0xB8BE, 0x5988, 0xC2E8, 0x5989, 0x8A6C, 0x598A, 0xC8D1,
+	0x598B, 0x8A6D, 0x598C, 0x8A6E, 0x598D, 0xE5FB, 0x598E, 0x8A6F,	0x598F, 0x8A70, 0x5990, 0x8A71, 0x5991, 0x8A72, 0x5992, 0xB6CA,
+	0x5993, 0xBCCB, 0x5994, 0x8A73, 0x5995, 0x8A74, 0x5996, 0xD1FD,	0x5997, 0xE6A1, 0x5998, 0x8A75, 0x5999, 0xC3EE, 0x599A, 0x8A76,
+	0x599B, 0x8A77, 0x599C, 0x8A78, 0x599D, 0x8A79, 0x599E, 0xE6A4,	0x599F, 0x8A7A, 0x59A0, 0x8A7B, 0x59A1, 0x8A7C, 0x59A2, 0x8A7D,
+	0x59A3, 0xE5FE, 0x59A4, 0xE6A5, 0x59A5, 0xCDD7, 0x59A6, 0x8A7E,	0x59A7, 0x8A80, 0x59A8, 0xB7C1, 0x59A9, 0xE5FC, 0x59AA, 0xE5FD,
+	0x59AB, 0xE6A3, 0x59AC, 0x8A81, 0x59AD, 0x8A82, 0x59AE, 0xC4DD,	0x59AF, 0xE6A8, 0x59B0, 0x8A83, 0x59B1, 0x8A84, 0x59B2, 0xE6A7,
+	0x59B3, 0x8A85, 0x59B4, 0x8A86, 0x59B5, 0x8A87, 0x59B6, 0x8A88,	0x59B7, 0x8A89, 0x59B8, 0x8A8A, 0x59B9, 0xC3C3, 0x59BA, 0x8A8B,
+	0x59BB, 0xC6DE, 0x59BC, 0x8A8C, 0x59BD, 0x8A8D, 0x59BE, 0xE6AA,	0x59BF, 0x8A8E, 0x59C0, 0x8A8F, 0x59C1, 0x8A90, 0x59C2, 0x8A91,
+	0x59C3, 0x8A92, 0x59C4, 0x8A93, 0x59C5, 0x8A94, 0x59C6, 0xC4B7,	0x59C7, 0x8A95, 0x59C8, 0x8A96, 0x59C9, 0x8A97, 0x59CA, 0xE6A2,
+	0x59CB, 0xCABC, 0x59CC, 0x8A98, 0x59CD, 0x8A99, 0x59CE, 0x8A9A,	0x59CF, 0x8A9B, 0x59D0, 0xBDE3, 0x59D1, 0xB9C3, 0x59D2, 0xE6A6,
+	0x59D3, 0xD0D5, 0x59D4, 0xCEAF, 0x59D5, 0x8A9C, 0x59D6, 0x8A9D,	0x59D7, 0xE6A9, 0x59D8, 0xE6B0, 0x59D9, 0x8A9E, 0x59DA, 0xD2A6,
+	0x59DB, 0x8A9F, 0x59DC, 0xBDAA, 0x59DD, 0xE6AD, 0x59DE, 0x8AA0,	0x59DF, 0x8AA1, 0x59E0, 0x8AA2, 0x59E1, 0x8AA3, 0x59E2, 0x8AA4,
+	0x59E3, 0xE6AF, 0x59E4, 0x8AA5, 0x59E5, 0xC0D1, 0x59E6, 0x8AA6,	0x59E7, 0x8AA7, 0x59E8, 0xD2CC, 0x59E9, 0x8AA8, 0x59EA, 0x8AA9,
+	0x59EB, 0x8AAA, 0x59EC, 0xBCA7, 0x59ED, 0x8AAB, 0x59EE, 0x8AAC,	0x59EF, 0x8AAD, 0x59F0, 0x8AAE, 0x59F1, 0x8AAF, 0x59F2, 0x8AB0,
+	0x59F3, 0x8AB1, 0x59F4, 0x8AB2, 0x59F5, 0x8AB3, 0x59F6, 0x8AB4,	0x59F7, 0x8AB5, 0x59F8, 0x8AB6, 0x59F9, 0xE6B1, 0x59FA, 0x8AB7,
+	0x59FB, 0xD2F6, 0x59FC, 0x8AB8, 0x59FD, 0x8AB9, 0x59FE, 0x8ABA,	0x59FF, 0xD7CB, 0x5A00, 0x8ABB, 0x5A01, 0xCDFE, 0x5A02, 0x8ABC,
+	0x5A03, 0xCDDE, 0x5A04, 0xC2A6, 0x5A05, 0xE6AB, 0x5A06, 0xE6AC,	0x5A07, 0xBDBF, 0x5A08, 0xE6AE, 0x5A09, 0xE6B3, 0x5A0A, 0x8ABD,
+	0x5A0B, 0x8ABE, 0x5A0C, 0xE6B2, 0x5A0D, 0x8ABF, 0x5A0E, 0x8AC0,	0x5A0F, 0x8AC1, 0x5A10, 0x8AC2, 0x5A11, 0xE6B6, 0x5A12, 0x8AC3,
+	0x5A13, 0xE6B8, 0x5A14, 0x8AC4, 0x5A15, 0x8AC5, 0x5A16, 0x8AC6,	0x5A17, 0x8AC7, 0x5A18, 0xC4EF, 0x5A19, 0x8AC8, 0x5A1A, 0x8AC9,
+	0x5A1B, 0x8ACA, 0x5A1C, 0xC4C8, 0x5A1D, 0x8ACB, 0x5A1E, 0x8ACC,	0x5A1F, 0xBEEA, 0x5A20, 0xC9EF, 0x5A21, 0x8ACD, 0x5A22, 0x8ACE,
+	0x5A23, 0xE6B7, 0x5A24, 0x8ACF, 0x5A25, 0xB6F0, 0x5A26, 0x8AD0,	0x5A27, 0x8AD1, 0x5A28, 0x8AD2, 0x5A29, 0xC3E4, 0x5A2A, 0x8AD3,
+	0x5A2B, 0x8AD4, 0x5A2C, 0x8AD5, 0x5A2D, 0x8AD6, 0x5A2E, 0x8AD7,	0x5A2F, 0x8AD8, 0x5A30, 0x8AD9, 0x5A31, 0xD3E9, 0x5A32, 0xE6B4,
+	0x5A33, 0x8ADA, 0x5A34, 0xE6B5, 0x5A35, 0x8ADB, 0x5A36, 0xC8A2,	0x5A37, 0x8ADC, 0x5A38, 0x8ADD, 0x5A39, 0x8ADE, 0x5A3A, 0x8ADF,
+	0x5A3B, 0x8AE0, 0x5A3C, 0xE6BD, 0x5A3D, 0x8AE1, 0x5A3E, 0x8AE2,	0x5A3F, 0x8AE3, 0x5A40, 0xE6B9, 0x5A41, 0x8AE4, 0x5A42, 0x8AE5,
+	0x5A43, 0x8AE6, 0x5A44, 0x8AE7, 0x5A45, 0x8AE8, 0x5A46, 0xC6C5,	0x5A47, 0x8AE9, 0x5A48, 0x8AEA, 0x5A49, 0xCDF1, 0x5A4A, 0xE6BB,
+	0x5A4B, 0x8AEB, 0x5A4C, 0x8AEC, 0x5A4D, 0x8AED, 0x5A4E, 0x8AEE,	0x5A4F, 0x8AEF, 0x5A50, 0x8AF0, 0x5A51, 0x8AF1, 0x5A52, 0x8AF2,
+	0x5A53, 0x8AF3, 0x5A54, 0x8AF4, 0x5A55, 0xE6BC, 0x5A56, 0x8AF5,	0x5A57, 0x8AF6, 0x5A58, 0x8AF7, 0x5A59, 0x8AF8, 0x5A5A, 0xBBE9,
+	0x5A5B, 0x8AF9, 0x5A5C, 0x8AFA, 0x5A5D, 0x8AFB, 0x5A5E, 0x8AFC,	0x5A5F, 0x8AFD, 0x5A60, 0x8AFE, 0x5A61, 0x8B40, 0x5A62, 0xE6BE,
+	0x5A63, 0x8B41, 0x5A64, 0x8B42, 0x5A65, 0x8B43, 0x5A66, 0x8B44,	0x5A67, 0xE6BA, 0x5A68, 0x8B45, 0x5A69, 0x8B46, 0x5A6A, 0xC0B7,
+	0x5A6B, 0x8B47, 0x5A6C, 0x8B48, 0x5A6D, 0x8B49, 0x5A6E, 0x8B4A,	0x5A6F, 0x8B4B, 0x5A70, 0x8B4C, 0x5A71, 0x8B4D, 0x5A72, 0x8B4E,
+	0x5A73, 0x8B4F, 0x5A74, 0xD3A4, 0x5A75, 0xE6BF, 0x5A76, 0xC9F4,	0x5A77, 0xE6C3, 0x5A78, 0x8B50, 0x5A79, 0x8B51, 0x5A7A, 0xE6C4,
+	0x5A7B, 0x8B52, 0x5A7C, 0x8B53, 0x5A7D, 0x8B54, 0x5A7E, 0x8B55,	0x5A7F, 0xD0F6, 0x5A80, 0x8B56, 0x5A81, 0x8B57, 0x5A82, 0x8B58,
+	0x5A83, 0x8B59, 0x5A84, 0x8B5A, 0x5A85, 0x8B5B, 0x5A86, 0x8B5C,	0x5A87, 0x8B5D, 0x5A88, 0x8B5E, 0x5A89, 0x8B5F, 0x5A8A, 0x8B60,
+	0x5A8B, 0x8B61, 0x5A8C, 0x8B62, 0x5A8D, 0x8B63, 0x5A8E, 0x8B64,	0x5A8F, 0x8B65, 0x5A90, 0x8B66, 0x5A91, 0x8B67, 0x5A92, 0xC3BD,
+	0x5A93, 0x8B68, 0x5A94, 0x8B69, 0x5A95, 0x8B6A, 0x5A96, 0x8B6B,	0x5A97, 0x8B6C, 0x5A98, 0x8B6D, 0x5A99, 0x8B6E, 0x5A9A, 0xC3C4,
+	0x5A9B, 0xE6C2, 0x5A9C, 0x8B6F, 0x5A9D, 0x8B70, 0x5A9E, 0x8B71,	0x5A9F, 0x8B72, 0x5AA0, 0x8B73, 0x5AA1, 0x8B74, 0x5AA2, 0x8B75,
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+	0x5AAB, 0x8B7D, 0x5AAC, 0x8B7E, 0x5AAD, 0x8B80, 0x5AAE, 0x8B81,	0x5AAF, 0x8B82, 0x5AB0, 0x8B83, 0x5AB1, 0x8B84, 0x5AB2, 0xE6C7,
+	0x5AB3, 0xCFB1, 0x5AB4, 0x8B85, 0x5AB5, 0xEBF4, 0x5AB6, 0x8B86,	0x5AB7, 0x8B87, 0x5AB8, 0xE6CA, 0x5AB9, 0x8B88, 0x5ABA, 0x8B89,
+	0x5ABB, 0x8B8A, 0x5ABC, 0x8B8B, 0x5ABD, 0x8B8C, 0x5ABE, 0xE6C5,	0x5ABF, 0x8B8D, 0x5AC0, 0x8B8E, 0x5AC1, 0xBCDE, 0x5AC2, 0xC9A9,
+	0x5AC3, 0x8B8F, 0x5AC4, 0x8B90, 0x5AC5, 0x8B91, 0x5AC6, 0x8B92,	0x5AC7, 0x8B93, 0x5AC8, 0x8B94, 0x5AC9, 0xBCB5, 0x5ACA, 0x8B95,
+	0x5ACB, 0x8B96, 0x5ACC, 0xCFD3, 0x5ACD, 0x8B97, 0x5ACE, 0x8B98,	0x5ACF, 0x8B99, 0x5AD0, 0x8B9A, 0x5AD1, 0x8B9B, 0x5AD2, 0xE6C8,
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+	0x5ADB, 0x8BA1, 0x5ADC, 0xE6D1, 0x5ADD, 0x8BA2, 0x5ADE, 0x8BA3,	0x5ADF, 0x8BA4, 0x5AE0, 0xE6CB, 0x5AE1, 0xB5D5, 0x5AE2, 0x8BA5,
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+	0x5AEB, 0xE6C6, 0x5AEC, 0x8BAB, 0x5AED, 0x8BAC, 0x5AEE, 0x8BAD,	0x5AEF, 0x8BAE, 0x5AF0, 0x8BAF, 0x5AF1, 0xE6CD, 0x5AF2, 0x8BB0,
+	0x5AF3, 0x8BB1, 0x5AF4, 0x8BB2, 0x5AF5, 0x8BB3, 0x5AF6, 0x8BB4,	0x5AF7, 0x8BB5, 0x5AF8, 0x8BB6, 0x5AF9, 0x8BB7, 0x5AFA, 0x8BB8,
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+	0x5B03, 0x8BC1, 0x5B04, 0x8BC2, 0x5B05, 0x8BC3, 0x5B06, 0x8BC4,	0x5B07, 0x8BC5, 0x5B08, 0x8BC6, 0x5B09, 0xE6D2, 0x5B0A, 0x8BC7,
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+	0x5B13, 0x8BD0, 0x5B14, 0x8BD1, 0x5B15, 0x8BD2, 0x5B16, 0xE6D4,	0x5B17, 0xE6D3, 0x5B18, 0x8BD3, 0x5B19, 0x8BD4, 0x5B1A, 0x8BD5,
+	0x5B1B, 0x8BD6, 0x5B1C, 0x8BD7, 0x5B1D, 0x8BD8, 0x5B1E, 0x8BD9,	0x5B1F, 0x8BDA, 0x5B20, 0x8BDB, 0x5B21, 0x8BDC, 0x5B22, 0x8BDD,
+	0x5B23, 0x8BDE, 0x5B24, 0x8BDF, 0x5B25, 0x8BE0, 0x5B26, 0x8BE1,	0x5B27, 0x8BE2, 0x5B28, 0x8BE3, 0x5B29, 0x8BE4, 0x5B2A, 0x8BE5,
+	0x5B2B, 0x8BE6, 0x5B2C, 0x8BE7, 0x5B2D, 0x8BE8, 0x5B2E, 0x8BE9,	0x5B2F, 0x8BEA, 0x5B30, 0x8BEB, 0x5B31, 0x8BEC, 0x5B32, 0xE6D5,
+	0x5B33, 0x8BED, 0x5B34, 0xD9F8, 0x5B35, 0x8BEE, 0x5B36, 0x8BEF,	0x5B37, 0xE6D6, 0x5B38, 0x8BF0, 0x5B39, 0x8BF1, 0x5B3A, 0x8BF2,
+	0x5B3B, 0x8BF3, 0x5B3C, 0x8BF4, 0x5B3D, 0x8BF5, 0x5B3E, 0x8BF6,	0x5B3F, 0x8BF7, 0x5B40, 0xE6D7, 0x5B41, 0x8BF8, 0x5B42, 0x8BF9,
+	0x5B43, 0x8BFA, 0x5B44, 0x8BFB, 0x5B45, 0x8BFC, 0x5B46, 0x8BFD,	0x5B47, 0x8BFE, 0x5B48, 0x8C40, 0x5B49, 0x8C41, 0x5B4A, 0x8C42,
+	0x5B4B, 0x8C43, 0x5B4C, 0x8C44, 0x5B4D, 0x8C45, 0x5B4E, 0x8C46,	0x5B4F, 0x8C47, 0x5B50, 0xD7D3, 0x5B51, 0xE6DD, 0x5B52, 0x8C48,
+	0x5B53, 0xE6DE, 0x5B54, 0xBFD7, 0x5B55, 0xD4D0, 0x5B56, 0x8C49,	0x5B57, 0xD7D6, 0x5B58, 0xB4E6, 0x5B59, 0xCBEF, 0x5B5A, 0xE6DA,
+	0x5B5B, 0xD8C3, 0x5B5C, 0xD7CE, 0x5B5D, 0xD0A2, 0x5B5E, 0x8C4A,	0x5B5F, 0xC3CF, 0x5B60, 0x8C4B, 0x5B61, 0x8C4C, 0x5B62, 0xE6DF,
+	0x5B63, 0xBCBE, 0x5B64, 0xB9C2, 0x5B65, 0xE6DB, 0x5B66, 0xD1A7,	0x5B67, 0x8C4D, 0x5B68, 0x8C4E, 0x5B69, 0xBAA2, 0x5B6A, 0xC2CF,
+	0x5B6B, 0x8C4F, 0x5B6C, 0xD8AB, 0x5B6D, 0x8C50, 0x5B6E, 0x8C51,	0x5B6F, 0x8C52, 0x5B70, 0xCAEB, 0x5B71, 0xE5EE, 0x5B72, 0x8C53,
+	0x5B73, 0xE6DC, 0x5B74, 0x8C54, 0x5B75, 0xB7F5, 0x5B76, 0x8C55,	0x5B77, 0x8C56, 0x5B78, 0x8C57, 0x5B79, 0x8C58, 0x5B7A, 0xC8E6,
+	0x5B7B, 0x8C59, 0x5B7C, 0x8C5A, 0x5B7D, 0xC4F5, 0x5B7E, 0x8C5B,	0x5B7F, 0x8C5C, 0x5B80, 0xE5B2, 0x5B81, 0xC4FE, 0x5B82, 0x8C5D,
+	0x5B83, 0xCBFC, 0x5B84, 0xE5B3, 0x5B85, 0xD5AC, 0x5B86, 0x8C5E,	0x5B87, 0xD3EE, 0x5B88, 0xCAD8, 0x5B89, 0xB0B2, 0x5B8A, 0x8C5F,
+	0x5B8B, 0xCBCE, 0x5B8C, 0xCDEA, 0x5B8D, 0x8C60, 0x5B8E, 0x8C61,	0x5B8F, 0xBAEA, 0x5B90, 0x8C62, 0x5B91, 0x8C63, 0x5B92, 0x8C64,
+	0x5B93, 0xE5B5, 0x5B94, 0x8C65, 0x5B95, 0xE5B4, 0x5B96, 0x8C66,	0x5B97, 0xD7DA, 0x5B98, 0xB9D9, 0x5B99, 0xD6E6, 0x5B9A, 0xB6A8,
+	0x5B9B, 0xCDF0, 0x5B9C, 0xD2CB, 0x5B9D, 0xB1A6, 0x5B9E, 0xCAB5,	0x5B9F, 0x8C67, 0x5BA0, 0xB3E8, 0x5BA1, 0xC9F3, 0x5BA2, 0xBFCD,
+	0x5BA3, 0xD0FB, 0x5BA4, 0xCAD2, 0x5BA5, 0xE5B6, 0x5BA6, 0xBBC2,	0x5BA7, 0x8C68, 0x5BA8, 0x8C69, 0x5BA9, 0x8C6A, 0x5BAA, 0xCFDC,
+	0x5BAB, 0xB9AC, 0x5BAC, 0x8C6B, 0x5BAD, 0x8C6C, 0x5BAE, 0x8C6D,	0x5BAF, 0x8C6E, 0x5BB0, 0xD4D7, 0x5BB1, 0x8C6F, 0x5BB2, 0x8C70,
+	0x5BB3, 0xBAA6, 0x5BB4, 0xD1E7, 0x5BB5, 0xCFFC, 0x5BB6, 0xBCD2,	0x5BB7, 0x8C71, 0x5BB8, 0xE5B7, 0x5BB9, 0xC8DD, 0x5BBA, 0x8C72,
+	0x5BBB, 0x8C73, 0x5BBC, 0x8C74, 0x5BBD, 0xBFED, 0x5BBE, 0xB1F6,	0x5BBF, 0xCBDE, 0x5BC0, 0x8C75, 0x5BC1, 0x8C76, 0x5BC2, 0xBCC5,
+	0x5BC3, 0x8C77, 0x5BC4, 0xBCC4, 0x5BC5, 0xD2FA, 0x5BC6, 0xC3DC,	0x5BC7, 0xBFDC, 0x5BC8, 0x8C78, 0x5BC9, 0x8C79, 0x5BCA, 0x8C7A,
+	0x5BCB, 0x8C7B, 0x5BCC, 0xB8BB, 0x5BCD, 0x8C7C, 0x5BCE, 0x8C7D,	0x5BCF, 0x8C7E, 0x5BD0, 0xC3C2, 0x5BD1, 0x8C80, 0x5BD2, 0xBAAE,
+	0x5BD3, 0xD4A2, 0x5BD4, 0x8C81, 0x5BD5, 0x8C82, 0x5BD6, 0x8C83,	0x5BD7, 0x8C84, 0x5BD8, 0x8C85, 0x5BD9, 0x8C86, 0x5BDA, 0x8C87,
+	0x5BDB, 0x8C88, 0x5BDC, 0x8C89, 0x5BDD, 0xC7DE, 0x5BDE, 0xC4AF,	0x5BDF, 0xB2EC, 0x5BE0, 0x8C8A, 0x5BE1, 0xB9D1, 0x5BE2, 0x8C8B,
+	0x5BE3, 0x8C8C, 0x5BE4, 0xE5BB, 0x5BE5, 0xC1C8, 0x5BE6, 0x8C8D,	0x5BE7, 0x8C8E, 0x5BE8, 0xD5AF, 0x5BE9, 0x8C8F, 0x5BEA, 0x8C90,
+	0x5BEB, 0x8C91, 0x5BEC, 0x8C92, 0x5BED, 0x8C93, 0x5BEE, 0xE5BC,	0x5BEF, 0x8C94, 0x5BF0, 0xE5BE, 0x5BF1, 0x8C95, 0x5BF2, 0x8C96,
+	0x5BF3, 0x8C97, 0x5BF4, 0x8C98, 0x5BF5, 0x8C99, 0x5BF6, 0x8C9A,	0x5BF7, 0x8C9B, 0x5BF8, 0xB4E7, 0x5BF9, 0xB6D4, 0x5BFA, 0xCBC2,
+	0x5BFB, 0xD1B0, 0x5BFC, 0xB5BC, 0x5BFD, 0x8C9C, 0x5BFE, 0x8C9D,	0x5BFF, 0xCAD9, 0x5C00, 0x8C9E, 0x5C01, 0xB7E2, 0x5C02, 0x8C9F,
+	0x5C03, 0x8CA0, 0x5C04, 0xC9E4, 0x5C05, 0x8CA1, 0x5C06, 0xBDAB,	0x5C07, 0x8CA2, 0x5C08, 0x8CA3, 0x5C09, 0xCEBE, 0x5C0A, 0xD7F0,
+	0x5C0B, 0x8CA4, 0x5C0C, 0x8CA5, 0x5C0D, 0x8CA6, 0x5C0E, 0x8CA7,	0x5C0F, 0xD0A1, 0x5C10, 0x8CA8, 0x5C11, 0xC9D9, 0x5C12, 0x8CA9,
+	0x5C13, 0x8CAA, 0x5C14, 0xB6FB, 0x5C15, 0xE6D8, 0x5C16, 0xBCE2,	0x5C17, 0x8CAB, 0x5C18, 0xB3BE, 0x5C19, 0x8CAC, 0x5C1A, 0xC9D0,
+	0x5C1B, 0x8CAD, 0x5C1C, 0xE6D9, 0x5C1D, 0xB3A2, 0x5C1E, 0x8CAE,	0x5C1F, 0x8CAF, 0x5C20, 0x8CB0, 0x5C21, 0x8CB1, 0x5C22, 0xDECC,
+	0x5C23, 0x8CB2, 0x5C24, 0xD3C8, 0x5C25, 0xDECD, 0x5C26, 0x8CB3,	0x5C27, 0xD2A2, 0x5C28, 0x8CB4, 0x5C29, 0x8CB5, 0x5C2A, 0x8CB6,
+	0x5C2B, 0x8CB7, 0x5C2C, 0xDECE, 0x5C2D, 0x8CB8, 0x5C2E, 0x8CB9,	0x5C2F, 0x8CBA, 0x5C30, 0x8CBB, 0x5C31, 0xBECD, 0x5C32, 0x8CBC,
+	0x5C33, 0x8CBD, 0x5C34, 0xDECF, 0x5C35, 0x8CBE, 0x5C36, 0x8CBF,	0x5C37, 0x8CC0, 0x5C38, 0xCAAC, 0x5C39, 0xD2FC, 0x5C3A, 0xB3DF,
+	0x5C3B, 0xE5EA, 0x5C3C, 0xC4E1, 0x5C3D, 0xBEA1, 0x5C3E, 0xCEB2,	0x5C3F, 0xC4F2, 0x5C40, 0xBED6, 0x5C41, 0xC6A8, 0x5C42, 0xB2E3,
+	0x5C43, 0x8CC1, 0x5C44, 0x8CC2, 0x5C45, 0xBED3, 0x5C46, 0x8CC3,	0x5C47, 0x8CC4, 0x5C48, 0xC7FC, 0x5C49, 0xCCEB, 0x5C4A, 0xBDEC,
+	0x5C4B, 0xCEDD, 0x5C4C, 0x8CC5, 0x5C4D, 0x8CC6, 0x5C4E, 0xCABA,	0x5C4F, 0xC6C1, 0x5C50, 0xE5EC, 0x5C51, 0xD0BC, 0x5C52, 0x8CC7,
+	0x5C53, 0x8CC8, 0x5C54, 0x8CC9, 0x5C55, 0xD5B9, 0x5C56, 0x8CCA,	0x5C57, 0x8CCB, 0x5C58, 0x8CCC, 0x5C59, 0xE5ED, 0x5C5A, 0x8CCD,
+	0x5C5B, 0x8CCE, 0x5C5C, 0x8CCF, 0x5C5D, 0x8CD0, 0x5C5E, 0xCAF4,	0x5C5F, 0x8CD1, 0x5C60, 0xCDC0, 0x5C61, 0xC2C5, 0x5C62, 0x8CD2,
+	0x5C63, 0xE5EF, 0x5C64, 0x8CD3, 0x5C65, 0xC2C4, 0x5C66, 0xE5F0,	0x5C67, 0x8CD4, 0x5C68, 0x8CD5, 0x5C69, 0x8CD6, 0x5C6A, 0x8CD7,
+	0x5C6B, 0x8CD8, 0x5C6C, 0x8CD9, 0x5C6D, 0x8CDA, 0x5C6E, 0xE5F8,	0x5C6F, 0xCDCD, 0x5C70, 0x8CDB, 0x5C71, 0xC9BD, 0x5C72, 0x8CDC,
+	0x5C73, 0x8CDD, 0x5C74, 0x8CDE, 0x5C75, 0x8CDF, 0x5C76, 0x8CE0,	0x5C77, 0x8CE1, 0x5C78, 0x8CE2, 0x5C79, 0xD2D9, 0x5C7A, 0xE1A8,
+	0x5C7B, 0x8CE3, 0x5C7C, 0x8CE4, 0x5C7D, 0x8CE5, 0x5C7E, 0x8CE6,	0x5C7F, 0xD3EC, 0x5C80, 0x8CE7, 0x5C81, 0xCBEA, 0x5C82, 0xC6F1,
+	0x5C83, 0x8CE8, 0x5C84, 0x8CE9, 0x5C85, 0x8CEA, 0x5C86, 0x8CEB,	0x5C87, 0x8CEC, 0x5C88, 0xE1AC, 0x5C89, 0x8CED, 0x5C8A, 0x8CEE,
+	0x5C8B, 0x8CEF, 0x5C8C, 0xE1A7, 0x5C8D, 0xE1A9, 0x5C8E, 0x8CF0,	0x5C8F, 0x8CF1, 0x5C90, 0xE1AA, 0x5C91, 0xE1AF, 0x5C92, 0x8CF2,
+	0x5C93, 0x8CF3, 0x5C94, 0xB2ED, 0x5C95, 0x8CF4, 0x5C96, 0xE1AB,	0x5C97, 0xB8DA, 0x5C98, 0xE1AD, 0x5C99, 0xE1AE, 0x5C9A, 0xE1B0,
+	0x5C9B, 0xB5BA, 0x5C9C, 0xE1B1, 0x5C9D, 0x8CF5, 0x5C9E, 0x8CF6,	0x5C9F, 0x8CF7, 0x5CA0, 0x8CF8, 0x5CA1, 0x8CF9, 0x5CA2, 0xE1B3,
+	0x5CA3, 0xE1B8, 0x5CA4, 0x8CFA, 0x5CA5, 0x8CFB, 0x5CA6, 0x8CFC,	0x5CA7, 0x8CFD, 0x5CA8, 0x8CFE, 0x5CA9, 0xD1D2, 0x5CAA, 0x8D40,
+	0x5CAB, 0xE1B6, 0x5CAC, 0xE1B5, 0x5CAD, 0xC1EB, 0x5CAE, 0x8D41,	0x5CAF, 0x8D42, 0x5CB0, 0x8D43, 0x5CB1, 0xE1B7, 0x5CB2, 0x8D44,
+	0x5CB3, 0xD4C0, 0x5CB4, 0x8D45, 0x5CB5, 0xE1B2, 0x5CB6, 0x8D46,	0x5CB7, 0xE1BA, 0x5CB8, 0xB0B6, 0x5CB9, 0x8D47, 0x5CBA, 0x8D48,
+	0x5CBB, 0x8D49, 0x5CBC, 0x8D4A, 0x5CBD, 0xE1B4, 0x5CBE, 0x8D4B,	0x5CBF, 0xBFF9, 0x5CC0, 0x8D4C, 0x5CC1, 0xE1B9, 0x5CC2, 0x8D4D,
+	0x5CC3, 0x8D4E, 0x5CC4, 0xE1BB, 0x5CC5, 0x8D4F, 0x5CC6, 0x8D50,	0x5CC7, 0x8D51, 0x5CC8, 0x8D52, 0x5CC9, 0x8D53, 0x5CCA, 0x8D54,
+	0x5CCB, 0xE1BE, 0x5CCC, 0x8D55, 0x5CCD, 0x8D56, 0x5CCE, 0x8D57,	0x5CCF, 0x8D58, 0x5CD0, 0x8D59, 0x5CD1, 0x8D5A, 0x5CD2, 0xE1BC,
+	0x5CD3, 0x8D5B, 0x5CD4, 0x8D5C, 0x5CD5, 0x8D5D, 0x5CD6, 0x8D5E,	0x5CD7, 0x8D5F, 0x5CD8, 0x8D60, 0x5CD9, 0xD6C5, 0x5CDA, 0x8D61,
+	0x5CDB, 0x8D62, 0x5CDC, 0x8D63, 0x5CDD, 0x8D64, 0x5CDE, 0x8D65,	0x5CDF, 0x8D66, 0x5CE0, 0x8D67, 0x5CE1, 0xCFBF, 0x5CE2, 0x8D68,
+	0x5CE3, 0x8D69, 0x5CE4, 0xE1BD, 0x5CE5, 0xE1BF, 0x5CE6, 0xC2CD,	0x5CE7, 0x8D6A, 0x5CE8, 0xB6EB, 0x5CE9, 0x8D6B, 0x5CEA, 0xD3F8,
+	0x5CEB, 0x8D6C, 0x5CEC, 0x8D6D, 0x5CED, 0xC7CD, 0x5CEE, 0x8D6E,	0x5CEF, 0x8D6F, 0x5CF0, 0xB7E5, 0x5CF1, 0x8D70, 0x5CF2, 0x8D71,
+	0x5CF3, 0x8D72, 0x5CF4, 0x8D73, 0x5CF5, 0x8D74, 0x5CF6, 0x8D75,	0x5CF7, 0x8D76, 0x5CF8, 0x8D77, 0x5CF9, 0x8D78, 0x5CFA, 0x8D79,
+	0x5CFB, 0xBEFE, 0x5CFC, 0x8D7A, 0x5CFD, 0x8D7B, 0x5CFE, 0x8D7C,	0x5CFF, 0x8D7D, 0x5D00, 0x8D7E, 0x5D01, 0x8D80, 0x5D02, 0xE1C0,
+	0x5D03, 0xE1C1, 0x5D04, 0x8D81, 0x5D05, 0x8D82, 0x5D06, 0xE1C7,	0x5D07, 0xB3E7, 0x5D08, 0x8D83, 0x5D09, 0x8D84, 0x5D0A, 0x8D85,
+	0x5D0B, 0x8D86, 0x5D0C, 0x8D87, 0x5D0D, 0x8D88, 0x5D0E, 0xC6E9,	0x5D0F, 0x8D89, 0x5D10, 0x8D8A, 0x5D11, 0x8D8B, 0x5D12, 0x8D8C,
+	0x5D13, 0x8D8D, 0x5D14, 0xB4DE, 0x5D15, 0x8D8E, 0x5D16, 0xD1C2,	0x5D17, 0x8D8F, 0x5D18, 0x8D90, 0x5D19, 0x8D91, 0x5D1A, 0x8D92,
+	0x5D1B, 0xE1C8, 0x5D1C, 0x8D93, 0x5D1D, 0x8D94, 0x5D1E, 0xE1C6,	0x5D1F, 0x8D95, 0x5D20, 0x8D96, 0x5D21, 0x8D97, 0x5D22, 0x8D98,
+	0x5D23, 0x8D99, 0x5D24, 0xE1C5, 0x5D25, 0x8D9A, 0x5D26, 0xE1C3,	0x5D27, 0xE1C2, 0x5D28, 0x8D9B, 0x5D29, 0xB1C0, 0x5D2A, 0x8D9C,
+	0x5D2B, 0x8D9D, 0x5D2C, 0x8D9E, 0x5D2D, 0xD5B8, 0x5D2E, 0xE1C4,	0x5D2F, 0x8D9F, 0x5D30, 0x8DA0, 0x5D31, 0x8DA1, 0x5D32, 0x8DA2,
+	0x5D33, 0x8DA3, 0x5D34, 0xE1CB, 0x5D35, 0x8DA4, 0x5D36, 0x8DA5,	0x5D37, 0x8DA6, 0x5D38, 0x8DA7, 0x5D39, 0x8DA8, 0x5D3A, 0x8DA9,
+	0x5D3B, 0x8DAA, 0x5D3C, 0x8DAB, 0x5D3D, 0xE1CC, 0x5D3E, 0xE1CA,	0x5D3F, 0x8DAC, 0x5D40, 0x8DAD, 0x5D41, 0x8DAE, 0x5D42, 0x8DAF,
+	0x5D43, 0x8DB0, 0x5D44, 0x8DB1, 0x5D45, 0x8DB2, 0x5D46, 0x8DB3,	0x5D47, 0xEFFA, 0x5D48, 0x8DB4, 0x5D49, 0x8DB5, 0x5D4A, 0xE1D3,
+	0x5D4B, 0xE1D2, 0x5D4C, 0xC7B6, 0x5D4D, 0x8DB6, 0x5D4E, 0x8DB7,	0x5D4F, 0x8DB8, 0x5D50, 0x8DB9, 0x5D51, 0x8DBA, 0x5D52, 0x8DBB,
+	0x5D53, 0x8DBC, 0x5D54, 0x8DBD, 0x5D55, 0x8DBE, 0x5D56, 0x8DBF,	0x5D57, 0x8DC0, 0x5D58, 0xE1C9, 0x5D59, 0x8DC1, 0x5D5A, 0x8DC2,
+	0x5D5B, 0xE1CE, 0x5D5C, 0x8DC3, 0x5D5D, 0xE1D0, 0x5D5E, 0x8DC4,	0x5D5F, 0x8DC5, 0x5D60, 0x8DC6, 0x5D61, 0x8DC7, 0x5D62, 0x8DC8,
+	0x5D63, 0x8DC9, 0x5D64, 0x8DCA, 0x5D65, 0x8DCB, 0x5D66, 0x8DCC,	0x5D67, 0x8DCD, 0x5D68, 0x8DCE, 0x5D69, 0xE1D4, 0x5D6A, 0x8DCF,
+	0x5D6B, 0xE1D1, 0x5D6C, 0xE1CD, 0x5D6D, 0x8DD0, 0x5D6E, 0x8DD1,	0x5D6F, 0xE1CF, 0x5D70, 0x8DD2, 0x5D71, 0x8DD3, 0x5D72, 0x8DD4,
+	0x5D73, 0x8DD5, 0x5D74, 0xE1D5, 0x5D75, 0x8DD6, 0x5D76, 0x8DD7,	0x5D77, 0x8DD8, 0x5D78, 0x8DD9, 0x5D79, 0x8DDA, 0x5D7A, 0x8DDB,
+	0x5D7B, 0x8DDC, 0x5D7C, 0x8DDD, 0x5D7D, 0x8DDE, 0x5D7E, 0x8DDF,	0x5D7F, 0x8DE0, 0x5D80, 0x8DE1, 0x5D81, 0x8DE2, 0x5D82, 0xE1D6,
+	0x5D83, 0x8DE3, 0x5D84, 0x8DE4, 0x5D85, 0x8DE5, 0x5D86, 0x8DE6,	0x5D87, 0x8DE7, 0x5D88, 0x8DE8, 0x5D89, 0x8DE9, 0x5D8A, 0x8DEA,
+	0x5D8B, 0x8DEB, 0x5D8C, 0x8DEC, 0x5D8D, 0x8DED, 0x5D8E, 0x8DEE,	0x5D8F, 0x8DEF, 0x5D90, 0x8DF0, 0x5D91, 0x8DF1, 0x5D92, 0x8DF2,
+	0x5D93, 0x8DF3, 0x5D94, 0x8DF4, 0x5D95, 0x8DF5, 0x5D96, 0x8DF6,	0x5D97, 0x8DF7, 0x5D98, 0x8DF8, 0x5D99, 0xE1D7, 0x5D9A, 0x8DF9,
+	0x5D9B, 0x8DFA, 0x5D9C, 0x8DFB, 0x5D9D, 0xE1D8, 0x5D9E, 0x8DFC,	0x5D9F, 0x8DFD, 0x5DA0, 0x8DFE, 0x5DA1, 0x8E40, 0x5DA2, 0x8E41,
+	0x5DA3, 0x8E42, 0x5DA4, 0x8E43, 0x5DA5, 0x8E44, 0x5DA6, 0x8E45,	0x5DA7, 0x8E46, 0x5DA8, 0x8E47, 0x5DA9, 0x8E48, 0x5DAA, 0x8E49,
+	0x5DAB, 0x8E4A, 0x5DAC, 0x8E4B, 0x5DAD, 0x8E4C, 0x5DAE, 0x8E4D,	0x5DAF, 0x8E4E, 0x5DB0, 0x8E4F, 0x5DB1, 0x8E50, 0x5DB2, 0x8E51,
+	0x5DB3, 0x8E52, 0x5DB4, 0x8E53, 0x5DB5, 0x8E54, 0x5DB6, 0x8E55,	0x5DB7, 0xE1DA, 0x5DB8, 0x8E56, 0x5DB9, 0x8E57, 0x5DBA, 0x8E58,
+	0x5DBB, 0x8E59, 0x5DBC, 0x8E5A, 0x5DBD, 0x8E5B, 0x5DBE, 0x8E5C,	0x5DBF, 0x8E5D, 0x5DC0, 0x8E5E, 0x5DC1, 0x8E5F, 0x5DC2, 0x8E60,
+	0x5DC3, 0x8E61, 0x5DC4, 0x8E62, 0x5DC5, 0xE1DB, 0x5DC6, 0x8E63,	0x5DC7, 0x8E64, 0x5DC8, 0x8E65, 0x5DC9, 0x8E66, 0x5DCA, 0x8E67,
+	0x5DCB, 0x8E68, 0x5DCC, 0x8E69, 0x5DCD, 0xCEA1, 0x5DCE, 0x8E6A,	0x5DCF, 0x8E6B, 0x5DD0, 0x8E6C, 0x5DD1, 0x8E6D, 0x5DD2, 0x8E6E,
+	0x5DD3, 0x8E6F, 0x5DD4, 0x8E70, 0x5DD5, 0x8E71, 0x5DD6, 0x8E72,	0x5DD7, 0x8E73, 0x5DD8, 0x8E74, 0x5DD9, 0x8E75, 0x5DDA, 0x8E76,
+	0x5DDB, 0xE7DD, 0x5DDC, 0x8E77, 0x5DDD, 0xB4A8, 0x5DDE, 0xD6DD,	0x5DDF, 0x8E78, 0x5DE0, 0x8E79, 0x5DE1, 0xD1B2, 0x5DE2, 0xB3B2,
+	0x5DE3, 0x8E7A, 0x5DE4, 0x8E7B, 0x5DE5, 0xB9A4, 0x5DE6, 0xD7F3,	0x5DE7, 0xC7C9, 0x5DE8, 0xBEDE, 0x5DE9, 0xB9AE, 0x5DEA, 0x8E7C,
+	0x5DEB, 0xCED7, 0x5DEC, 0x8E7D, 0x5DED, 0x8E7E, 0x5DEE, 0xB2EE,	0x5DEF, 0xDBCF, 0x5DF0, 0x8E80, 0x5DF1, 0xBCBA, 0x5DF2, 0xD2D1,
+	0x5DF3, 0xCBC8, 0x5DF4, 0xB0CD, 0x5DF5, 0x8E81, 0x5DF6, 0x8E82,	0x5DF7, 0xCFEF, 0x5DF8, 0x8E83, 0x5DF9, 0x8E84, 0x5DFA, 0x8E85,
+	0x5DFB, 0x8E86, 0x5DFC, 0x8E87, 0x5DFD, 0xD9E3, 0x5DFE, 0xBDED,	0x5DFF, 0x8E88, 0x5E00, 0x8E89, 0x5E01, 0xB1D2, 0x5E02, 0xCAD0,
+	0x5E03, 0xB2BC, 0x5E04, 0x8E8A, 0x5E05, 0xCBA7, 0x5E06, 0xB7AB,	0x5E07, 0x8E8B, 0x5E08, 0xCAA6, 0x5E09, 0x8E8C, 0x5E0A, 0x8E8D,
+	0x5E0B, 0x8E8E, 0x5E0C, 0xCFA3, 0x5E0D, 0x8E8F, 0x5E0E, 0x8E90,	0x5E0F, 0xE0F8, 0x5E10, 0xD5CA, 0x5E11, 0xE0FB, 0x5E12, 0x8E91,
+	0x5E13, 0x8E92, 0x5E14, 0xE0FA, 0x5E15, 0xC5C1, 0x5E16, 0xCCFB,	0x5E17, 0x8E93, 0x5E18, 0xC1B1, 0x5E19, 0xE0F9, 0x5E1A, 0xD6E3,
+	0x5E1B, 0xB2AF, 0x5E1C, 0xD6C4, 0x5E1D, 0xB5DB, 0x5E1E, 0x8E94,	0x5E1F, 0x8E95, 0x5E20, 0x8E96, 0x5E21, 0x8E97, 0x5E22, 0x8E98,
+	0x5E23, 0x8E99, 0x5E24, 0x8E9A, 0x5E25, 0x8E9B, 0x5E26, 0xB4F8,	0x5E27, 0xD6A1, 0x5E28, 0x8E9C, 0x5E29, 0x8E9D, 0x5E2A, 0x8E9E,
+	0x5E2B, 0x8E9F, 0x5E2C, 0x8EA0, 0x5E2D, 0xCFAF, 0x5E2E, 0xB0EF,	0x5E2F, 0x8EA1, 0x5E30, 0x8EA2, 0x5E31, 0xE0FC, 0x5E32, 0x8EA3,
+	0x5E33, 0x8EA4, 0x5E34, 0x8EA5, 0x5E35, 0x8EA6, 0x5E36, 0x8EA7,	0x5E37, 0xE1A1, 0x5E38, 0xB3A3, 0x5E39, 0x8EA8, 0x5E3A, 0x8EA9,
+	0x5E3B, 0xE0FD, 0x5E3C, 0xE0FE, 0x5E3D, 0xC3B1, 0x5E3E, 0x8EAA,	0x5E3F, 0x8EAB, 0x5E40, 0x8EAC, 0x5E41, 0x8EAD, 0x5E42, 0xC3DD,
+	0x5E43, 0x8EAE, 0x5E44, 0xE1A2, 0x5E45, 0xB7F9, 0x5E46, 0x8EAF,	0x5E47, 0x8EB0, 0x5E48, 0x8EB1, 0x5E49, 0x8EB2, 0x5E4A, 0x8EB3,
+	0x5E4B, 0x8EB4, 0x5E4C, 0xBBCF, 0x5E4D, 0x8EB5, 0x5E4E, 0x8EB6,	0x5E4F, 0x8EB7, 0x5E50, 0x8EB8, 0x5E51, 0x8EB9, 0x5E52, 0x8EBA,
+	0x5E53, 0x8EBB, 0x5E54, 0xE1A3, 0x5E55, 0xC4BB, 0x5E56, 0x8EBC,	0x5E57, 0x8EBD, 0x5E58, 0x8EBE, 0x5E59, 0x8EBF, 0x5E5A, 0x8EC0,
+	0x5E5B, 0xE1A4, 0x5E5C, 0x8EC1, 0x5E5D, 0x8EC2, 0x5E5E, 0xE1A5,	0x5E5F, 0x8EC3, 0x5E60, 0x8EC4, 0x5E61, 0xE1A6, 0x5E62, 0xB4B1,
+	0x5E63, 0x8EC5, 0x5E64, 0x8EC6, 0x5E65, 0x8EC7, 0x5E66, 0x8EC8,	0x5E67, 0x8EC9, 0x5E68, 0x8ECA, 0x5E69, 0x8ECB, 0x5E6A, 0x8ECC,
+	0x5E6B, 0x8ECD, 0x5E6C, 0x8ECE, 0x5E6D, 0x8ECF, 0x5E6E, 0x8ED0,	0x5E6F, 0x8ED1, 0x5E70, 0x8ED2, 0x5E71, 0x8ED3, 0x5E72, 0xB8C9,
+	0x5E73, 0xC6BD, 0x5E74, 0xC4EA, 0x5E75, 0x8ED4, 0x5E76, 0xB2A2,	0x5E77, 0x8ED5, 0x5E78, 0xD0D2, 0x5E79, 0x8ED6, 0x5E7A, 0xE7DB,
+	0x5E7B, 0xBBC3, 0x5E7C, 0xD3D7, 0x5E7D, 0xD3C4, 0x5E7E, 0x8ED7,	0x5E7F, 0xB9E3, 0x5E80, 0xE2CF, 0x5E81, 0x8ED8, 0x5E82, 0x8ED9,
+	0x5E83, 0x8EDA, 0x5E84, 0xD7AF, 0x5E85, 0x8EDB, 0x5E86, 0xC7EC,	0x5E87, 0xB1D3, 0x5E88, 0x8EDC, 0x5E89, 0x8EDD, 0x5E8A, 0xB4B2,
+	0x5E8B, 0xE2D1, 0x5E8C, 0x8EDE, 0x5E8D, 0x8EDF, 0x5E8E, 0x8EE0,	0x5E8F, 0xD0F2, 0x5E90, 0xC2AE, 0x5E91, 0xE2D0, 0x5E92, 0x8EE1,
+	0x5E93, 0xBFE2, 0x5E94, 0xD3A6, 0x5E95, 0xB5D7, 0x5E96, 0xE2D2,	0x5E97, 0xB5EA, 0x5E98, 0x8EE2, 0x5E99, 0xC3ED, 0x5E9A, 0xB8FD,
+	0x5E9B, 0x8EE3, 0x5E9C, 0xB8AE, 0x5E9D, 0x8EE4, 0x5E9E, 0xC5D3,	0x5E9F, 0xB7CF, 0x5EA0, 0xE2D4, 0x5EA1, 0x8EE5, 0x5EA2, 0x8EE6,
+	0x5EA3, 0x8EE7, 0x5EA4, 0x8EE8, 0x5EA5, 0xE2D3, 0x5EA6, 0xB6C8,	0x5EA7, 0xD7F9, 0x5EA8, 0x8EE9, 0x5EA9, 0x8EEA, 0x5EAA, 0x8EEB,
+	0x5EAB, 0x8EEC, 0x5EAC, 0x8EED, 0x5EAD, 0xCDA5, 0x5EAE, 0x8EEE,	0x5EAF, 0x8EEF, 0x5EB0, 0x8EF0, 0x5EB1, 0x8EF1, 0x5EB2, 0x8EF2,
+	0x5EB3, 0xE2D8, 0x5EB4, 0x8EF3, 0x5EB5, 0xE2D6, 0x5EB6, 0xCAFC,	0x5EB7, 0xBFB5, 0x5EB8, 0xD3B9, 0x5EB9, 0xE2D5, 0x5EBA, 0x8EF4,
+	0x5EBB, 0x8EF5, 0x5EBC, 0x8EF6, 0x5EBD, 0x8EF7, 0x5EBE, 0xE2D7,	0x5EBF, 0x8EF8, 0x5EC0, 0x8EF9, 0x5EC1, 0x8EFA, 0x5EC2, 0x8EFB,
+	0x5EC3, 0x8EFC, 0x5EC4, 0x8EFD, 0x5EC5, 0x8EFE, 0x5EC6, 0x8F40,	0x5EC7, 0x8F41, 0x5EC8, 0x8F42, 0x5EC9, 0xC1AE, 0x5ECA, 0xC0C8,
+	0x5ECB, 0x8F43, 0x5ECC, 0x8F44, 0x5ECD, 0x8F45, 0x5ECE, 0x8F46,	0x5ECF, 0x8F47, 0x5ED0, 0x8F48, 0x5ED1, 0xE2DB, 0x5ED2, 0xE2DA,
+	0x5ED3, 0xC0AA, 0x5ED4, 0x8F49, 0x5ED5, 0x8F4A, 0x5ED6, 0xC1CE,	0x5ED7, 0x8F4B, 0x5ED8, 0x8F4C, 0x5ED9, 0x8F4D, 0x5EDA, 0x8F4E,
+	0x5EDB, 0xE2DC, 0x5EDC, 0x8F4F, 0x5EDD, 0x8F50, 0x5EDE, 0x8F51,	0x5EDF, 0x8F52, 0x5EE0, 0x8F53, 0x5EE1, 0x8F54, 0x5EE2, 0x8F55,
+	0x5EE3, 0x8F56, 0x5EE4, 0x8F57, 0x5EE5, 0x8F58, 0x5EE6, 0x8F59,	0x5EE7, 0x8F5A, 0x5EE8, 0xE2DD, 0x5EE9, 0x8F5B, 0x5EEA, 0xE2DE,
+	0x5EEB, 0x8F5C, 0x5EEC, 0x8F5D, 0x5EED, 0x8F5E, 0x5EEE, 0x8F5F,	0x5EEF, 0x8F60, 0x5EF0, 0x8F61, 0x5EF1, 0x8F62, 0x5EF2, 0x8F63,
+	0x5EF3, 0x8F64, 0x5EF4, 0xDBC8, 0x5EF5, 0x8F65, 0x5EF6, 0xD1D3,	0x5EF7, 0xCDA2, 0x5EF8, 0x8F66, 0x5EF9, 0x8F67, 0x5EFA, 0xBDA8,
+	0x5EFB, 0x8F68, 0x5EFC, 0x8F69, 0x5EFD, 0x8F6A, 0x5EFE, 0xDEC3,	0x5EFF, 0xD8A5, 0x5F00, 0xBFAA, 0x5F01, 0xDBCD, 0x5F02, 0xD2EC,
+	0x5F03, 0xC6FA, 0x5F04, 0xC5AA, 0x5F05, 0x8F6B, 0x5F06, 0x8F6C,	0x5F07, 0x8F6D, 0x5F08, 0xDEC4, 0x5F09, 0x8F6E, 0x5F0A, 0xB1D7,
+	0x5F0B, 0xDFAE, 0x5F0C, 0x8F6F, 0x5F0D, 0x8F70, 0x5F0E, 0x8F71,	0x5F0F, 0xCABD, 0x5F10, 0x8F72, 0x5F11, 0xDFB1, 0x5F12, 0x8F73,
+	0x5F13, 0xB9AD, 0x5F14, 0x8F74, 0x5F15, 0xD2FD, 0x5F16, 0x8F75,	0x5F17, 0xB8A5, 0x5F18, 0xBAEB, 0x5F19, 0x8F76, 0x5F1A, 0x8F77,
+	0x5F1B, 0xB3DA, 0x5F1C, 0x8F78, 0x5F1D, 0x8F79, 0x5F1E, 0x8F7A,	0x5F1F, 0xB5DC, 0x5F20, 0xD5C5, 0x5F21, 0x8F7B, 0x5F22, 0x8F7C,
+	0x5F23, 0x8F7D, 0x5F24, 0x8F7E, 0x5F25, 0xC3D6, 0x5F26, 0xCFD2,	0x5F27, 0xBBA1, 0x5F28, 0x8F80, 0x5F29, 0xE5F3, 0x5F2A, 0xE5F2,
+	0x5F2B, 0x8F81, 0x5F2C, 0x8F82, 0x5F2D, 0xE5F4, 0x5F2E, 0x8F83,	0x5F2F, 0xCDE4, 0x5F30, 0x8F84, 0x5F31, 0xC8F5, 0x5F32, 0x8F85,
+	0x5F33, 0x8F86, 0x5F34, 0x8F87, 0x5F35, 0x8F88, 0x5F36, 0x8F89,	0x5F37, 0x8F8A, 0x5F38, 0x8F8B, 0x5F39, 0xB5AF, 0x5F3A, 0xC7BF,
+	0x5F3B, 0x8F8C, 0x5F3C, 0xE5F6, 0x5F3D, 0x8F8D, 0x5F3E, 0x8F8E,	0x5F3F, 0x8F8F, 0x5F40, 0xECB0, 0x5F41, 0x8F90, 0x5F42, 0x8F91,
+	0x5F43, 0x8F92, 0x5F44, 0x8F93, 0x5F45, 0x8F94, 0x5F46, 0x8F95,	0x5F47, 0x8F96, 0x5F48, 0x8F97, 0x5F49, 0x8F98, 0x5F4A, 0x8F99,
+	0x5F4B, 0x8F9A, 0x5F4C, 0x8F9B, 0x5F4D, 0x8F9C, 0x5F4E, 0x8F9D,	0x5F4F, 0x8F9E, 0x5F50, 0xE5E6, 0x5F51, 0x8F9F, 0x5F52, 0xB9E9,
+	0x5F53, 0xB5B1, 0x5F54, 0x8FA0, 0x5F55, 0xC2BC, 0x5F56, 0xE5E8,	0x5F57, 0xE5E7, 0x5F58, 0xE5E9, 0x5F59, 0x8FA1, 0x5F5A, 0x8FA2,
+	0x5F5B, 0x8FA3, 0x5F5C, 0x8FA4, 0x5F5D, 0xD2CD, 0x5F5E, 0x8FA5,	0x5F5F, 0x8FA6, 0x5F60, 0x8FA7, 0x5F61, 0xE1EA, 0x5F62, 0xD0CE,
+	0x5F63, 0x8FA8, 0x5F64, 0xCDAE, 0x5F65, 0x8FA9, 0x5F66, 0xD1E5,	0x5F67, 0x8FAA, 0x5F68, 0x8FAB, 0x5F69, 0xB2CA, 0x5F6A, 0xB1EB,
+	0x5F6B, 0x8FAC, 0x5F6C, 0xB1F2, 0x5F6D, 0xC5ED, 0x5F6E, 0x8FAD,	0x5F6F, 0x8FAE, 0x5F70, 0xD5C3, 0x5F71, 0xD3B0, 0x5F72, 0x8FAF,
+	0x5F73, 0xE1DC, 0x5F74, 0x8FB0, 0x5F75, 0x8FB1, 0x5F76, 0x8FB2,	0x5F77, 0xE1DD, 0x5F78, 0x8FB3, 0x5F79, 0xD2DB, 0x5F7A, 0x8FB4,
+	0x5F7B, 0xB3B9, 0x5F7C, 0xB1CB, 0x5F7D, 0x8FB5, 0x5F7E, 0x8FB6,	0x5F7F, 0x8FB7, 0x5F80, 0xCDF9, 0x5F81, 0xD5F7, 0x5F82, 0xE1DE,
+	0x5F83, 0x8FB8, 0x5F84, 0xBEB6, 0x5F85, 0xB4FD, 0x5F86, 0x8FB9,	0x5F87, 0xE1DF, 0x5F88, 0xBADC, 0x5F89, 0xE1E0, 0x5F8A, 0xBBB2,
+	0x5F8B, 0xC2C9, 0x5F8C, 0xE1E1, 0x5F8D, 0x8FBA, 0x5F8E, 0x8FBB,	0x5F8F, 0x8FBC, 0x5F90, 0xD0EC, 0x5F91, 0x8FBD, 0x5F92, 0xCDBD,
+	0x5F93, 0x8FBE, 0x5F94, 0x8FBF, 0x5F95, 0xE1E2, 0x5F96, 0x8FC0,	0x5F97, 0xB5C3, 0x5F98, 0xC5C7, 0x5F99, 0xE1E3, 0x5F9A, 0x8FC1,
+	0x5F9B, 0x8FC2, 0x5F9C, 0xE1E4, 0x5F9D, 0x8FC3, 0x5F9E, 0x8FC4,	0x5F9F, 0x8FC5, 0x5FA0, 0x8FC6, 0x5FA1, 0xD3F9, 0x5FA2, 0x8FC7,
+	0x5FA3, 0x8FC8, 0x5FA4, 0x8FC9, 0x5FA5, 0x8FCA, 0x5FA6, 0x8FCB,	0x5FA7, 0x8FCC, 0x5FA8, 0xE1E5, 0x5FA9, 0x8FCD, 0x5FAA, 0xD1AD,
+	0x5FAB, 0x8FCE, 0x5FAC, 0x8FCF, 0x5FAD, 0xE1E6, 0x5FAE, 0xCEA2,	0x5FAF, 0x8FD0, 0x5FB0, 0x8FD1, 0x5FB1, 0x8FD2, 0x5FB2, 0x8FD3,
+	0x5FB3, 0x8FD4, 0x5FB4, 0x8FD5, 0x5FB5, 0xE1E7, 0x5FB6, 0x8FD6,	0x5FB7, 0xB5C2, 0x5FB8, 0x8FD7, 0x5FB9, 0x8FD8, 0x5FBA, 0x8FD9,
+	0x5FBB, 0x8FDA, 0x5FBC, 0xE1E8, 0x5FBD, 0xBBD5, 0x5FBE, 0x8FDB,	0x5FBF, 0x8FDC, 0x5FC0, 0x8FDD, 0x5FC1, 0x8FDE, 0x5FC2, 0x8FDF,
+	0x5FC3, 0xD0C4, 0x5FC4, 0xE2E0, 0x5FC5, 0xB1D8, 0x5FC6, 0xD2E4,	0x5FC7, 0x8FE0, 0x5FC8, 0x8FE1, 0x5FC9, 0xE2E1, 0x5FCA, 0x8FE2,
+	0x5FCB, 0x8FE3, 0x5FCC, 0xBCC9, 0x5FCD, 0xC8CC, 0x5FCE, 0x8FE4,	0x5FCF, 0xE2E3, 0x5FD0, 0xECFE, 0x5FD1, 0xECFD, 0x5FD2, 0xDFAF,
+	0x5FD3, 0x8FE5, 0x5FD4, 0x8FE6, 0x5FD5, 0x8FE7, 0x5FD6, 0xE2E2,	0x5FD7, 0xD6BE, 0x5FD8, 0xCDFC, 0x5FD9, 0xC3A6, 0x5FDA, 0x8FE8,
+	0x5FDB, 0x8FE9, 0x5FDC, 0x8FEA, 0x5FDD, 0xE3C3, 0x5FDE, 0x8FEB,	0x5FDF, 0x8FEC, 0x5FE0, 0xD6D2, 0x5FE1, 0xE2E7, 0x5FE2, 0x8FED,
+	0x5FE3, 0x8FEE, 0x5FE4, 0xE2E8, 0x5FE5, 0x8FEF, 0x5FE6, 0x8FF0,	0x5FE7, 0xD3C7, 0x5FE8, 0x8FF1, 0x5FE9, 0x8FF2, 0x5FEA, 0xE2EC,
+	0x5FEB, 0xBFEC, 0x5FEC, 0x8FF3, 0x5FED, 0xE2ED, 0x5FEE, 0xE2E5,	0x5FEF, 0x8FF4, 0x5FF0, 0x8FF5, 0x5FF1, 0xB3C0, 0x5FF2, 0x8FF6,
+	0x5FF3, 0x8FF7, 0x5FF4, 0x8FF8, 0x5FF5, 0xC4EE, 0x5FF6, 0x8FF9,	0x5FF7, 0x8FFA, 0x5FF8, 0xE2EE, 0x5FF9, 0x8FFB, 0x5FFA, 0x8FFC,
+	0x5FFB, 0xD0C3, 0x5FFC, 0x8FFD, 0x5FFD, 0xBAF6, 0x5FFE, 0xE2E9,	0x5FFF, 0xB7DE, 0x6000, 0xBBB3, 0x6001, 0xCCAC, 0x6002, 0xCBCB,
+	0x6003, 0xE2E4, 0x6004, 0xE2E6, 0x6005, 0xE2EA, 0x6006, 0xE2EB,	0x6007, 0x8FFE, 0x6008, 0x9040, 0x6009, 0x9041, 0x600A, 0xE2F7,
+	0x600B, 0x9042, 0x600C, 0x9043, 0x600D, 0xE2F4, 0x600E, 0xD4F5,	0x600F, 0xE2F3, 0x6010, 0x9044, 0x6011, 0x9045, 0x6012, 0xC5AD,
+	0x6013, 0x9046, 0x6014, 0xD5FA, 0x6015, 0xC5C2, 0x6016, 0xB2C0,	0x6017, 0x9047, 0x6018, 0x9048, 0x6019, 0xE2EF, 0x601A, 0x9049,
+	0x601B, 0xE2F2, 0x601C, 0xC1AF, 0x601D, 0xCBBC, 0x601E, 0x904A,	0x601F, 0x904B, 0x6020, 0xB5A1, 0x6021, 0xE2F9, 0x6022, 0x904C,
+	0x6023, 0x904D, 0x6024, 0x904E, 0x6025, 0xBCB1, 0x6026, 0xE2F1,	0x6027, 0xD0D4, 0x6028, 0xD4B9, 0x6029, 0xE2F5, 0x602A, 0xB9D6,
+	0x602B, 0xE2F6, 0x602C, 0x904F, 0x602D, 0x9050, 0x602E, 0x9051,	0x602F, 0xC7D3, 0x6030, 0x9052, 0x6031, 0x9053, 0x6032, 0x9054,
+	0x6033, 0x9055, 0x6034, 0x9056, 0x6035, 0xE2F0, 0x6036, 0x9057,	0x6037, 0x9058, 0x6038, 0x9059, 0x6039, 0x905A, 0x603A, 0x905B,
+	0x603B, 0xD7DC, 0x603C, 0xEDA1, 0x603D, 0x905C, 0x603E, 0x905D,	0x603F, 0xE2F8, 0x6040, 0x905E, 0x6041, 0xEDA5, 0x6042, 0xE2FE,
+	0x6043, 0xCAD1, 0x6044, 0x905F, 0x6045, 0x9060, 0x6046, 0x9061,	0x6047, 0x9062, 0x6048, 0x9063, 0x6049, 0x9064, 0x604A, 0x9065,
+	0x604B, 0xC1B5, 0x604C, 0x9066, 0x604D, 0xBBD0, 0x604E, 0x9067,	0x604F, 0x9068, 0x6050, 0xBFD6, 0x6051, 0x9069, 0x6052, 0xBAE3,
+	0x6053, 0x906A, 0x6054, 0x906B, 0x6055, 0xCBA1, 0x6056, 0x906C,	0x6057, 0x906D, 0x6058, 0x906E, 0x6059, 0xEDA6, 0x605A, 0xEDA3,
+	0x605B, 0x906F, 0x605C, 0x9070, 0x605D, 0xEDA2, 0x605E, 0x9071,	0x605F, 0x9072, 0x6060, 0x9073, 0x6061, 0x9074, 0x6062, 0xBBD6,
+	0x6063, 0xEDA7, 0x6064, 0xD0F4, 0x6065, 0x9075, 0x6066, 0x9076,	0x6067, 0xEDA4, 0x6068, 0xBADE, 0x6069, 0xB6F7, 0x606A, 0xE3A1,
+	0x606B, 0xB6B2, 0x606C, 0xCCF1, 0x606D, 0xB9A7, 0x606E, 0x9077,	0x606F, 0xCFA2, 0x6070, 0xC7A1, 0x6071, 0x9078, 0x6072, 0x9079,
+	0x6073, 0xBFD2, 0x6074, 0x907A, 0x6075, 0x907B, 0x6076, 0xB6F1,	0x6077, 0x907C, 0x6078, 0xE2FA, 0x6079, 0xE2FB, 0x607A, 0xE2FD,
+	0x607B, 0xE2FC, 0x607C, 0xC4D5, 0x607D, 0xE3A2, 0x607E, 0x907D,	0x607F, 0xD3C1, 0x6080, 0x907E, 0x6081, 0x9080, 0x6082, 0x9081,
+	0x6083, 0xE3A7, 0x6084, 0xC7C4, 0x6085, 0x9082, 0x6086, 0x9083,	0x6087, 0x9084, 0x6088, 0x9085, 0x6089, 0xCFA4, 0x608A, 0x9086,
+	0x608B, 0x9087, 0x608C, 0xE3A9, 0x608D, 0xBAB7, 0x608E, 0x9088,	0x608F, 0x9089, 0x6090, 0x908A, 0x6091, 0x908B, 0x6092, 0xE3A8,
+	0x6093, 0x908C, 0x6094, 0xBBDA, 0x6095, 0x908D, 0x6096, 0xE3A3,	0x6097, 0x908E, 0x6098, 0x908F, 0x6099, 0x9090, 0x609A, 0xE3A4,
+	0x609B, 0xE3AA, 0x609C, 0x9091, 0x609D, 0xE3A6, 0x609E, 0x9092,	0x609F, 0xCEF2, 0x60A0, 0xD3C6, 0x60A1, 0x9093, 0x60A2, 0x9094,
+	0x60A3, 0xBBBC, 0x60A4, 0x9095, 0x60A5, 0x9096, 0x60A6, 0xD4C3,	0x60A7, 0x9097, 0x60A8, 0xC4FA, 0x60A9, 0x9098, 0x60AA, 0x9099,
+	0x60AB, 0xEDA8, 0x60AC, 0xD0FC, 0x60AD, 0xE3A5, 0x60AE, 0x909A,	0x60AF, 0xC3F5, 0x60B0, 0x909B, 0x60B1, 0xE3AD, 0x60B2, 0xB1AF,
+	0x60B3, 0x909C, 0x60B4, 0xE3B2, 0x60B5, 0x909D, 0x60B6, 0x909E,	0x60B7, 0x909F, 0x60B8, 0xBCC2, 0x60B9, 0x90A0, 0x60BA, 0x90A1,
+	0x60BB, 0xE3AC, 0x60BC, 0xB5BF, 0x60BD, 0x90A2, 0x60BE, 0x90A3,	0x60BF, 0x90A4, 0x60C0, 0x90A5, 0x60C1, 0x90A6, 0x60C2, 0x90A7,
+	0x60C3, 0x90A8, 0x60C4, 0x90A9, 0x60C5, 0xC7E9, 0x60C6, 0xE3B0,	0x60C7, 0x90AA, 0x60C8, 0x90AB, 0x60C9, 0x90AC, 0x60CA, 0xBEAA,
+	0x60CB, 0xCDEF, 0x60CC, 0x90AD, 0x60CD, 0x90AE, 0x60CE, 0x90AF,	0x60CF, 0x90B0, 0x60D0, 0x90B1, 0x60D1, 0xBBF3, 0x60D2, 0x90B2,
+	0x60D3, 0x90B3, 0x60D4, 0x90B4, 0x60D5, 0xCCE8, 0x60D6, 0x90B5,	0x60D7, 0x90B6, 0x60D8, 0xE3AF, 0x60D9, 0x90B7, 0x60DA, 0xE3B1,
+	0x60DB, 0x90B8, 0x60DC, 0xCFA7, 0x60DD, 0xE3AE, 0x60DE, 0x90B9,	0x60DF, 0xCEA9, 0x60E0, 0xBBDD, 0x60E1, 0x90BA, 0x60E2, 0x90BB,
+	0x60E3, 0x90BC, 0x60E4, 0x90BD, 0x60E5, 0x90BE, 0x60E6, 0xB5EB,	0x60E7, 0xBEE5, 0x60E8, 0xB2D2, 0x60E9, 0xB3CD, 0x60EA, 0x90BF,
+	0x60EB, 0xB1B9, 0x60EC, 0xE3AB, 0x60ED, 0xB2D1, 0x60EE, 0xB5AC,	0x60EF, 0xB9DF, 0x60F0, 0xB6E8, 0x60F1, 0x90C0, 0x60F2, 0x90C1,
+	0x60F3, 0xCFEB, 0x60F4, 0xE3B7, 0x60F5, 0x90C2, 0x60F6, 0xBBCC,	0x60F7, 0x90C3, 0x60F8, 0x90C4, 0x60F9, 0xC8C7, 0x60FA, 0xD0CA,
+	0x60FB, 0x90C5, 0x60FC, 0x90C6, 0x60FD, 0x90C7, 0x60FE, 0x90C8,	0x60FF, 0x90C9, 0x6100, 0xE3B8, 0x6101, 0xB3EE, 0x6102, 0x90CA,
+	0x6103, 0x90CB, 0x6104, 0x90CC, 0x6105, 0x90CD, 0x6106, 0xEDA9,	0x6107, 0x90CE, 0x6108, 0xD3FA, 0x6109, 0xD3E4, 0x610A, 0x90CF,
+	0x610B, 0x90D0, 0x610C, 0x90D1, 0x610D, 0xEDAA, 0x610E, 0xE3B9,	0x610F, 0xD2E2, 0x6110, 0x90D2, 0x6111, 0x90D3, 0x6112, 0x90D4,
+	0x6113, 0x90D5, 0x6114, 0x90D6, 0x6115, 0xE3B5, 0x6116, 0x90D7,	0x6117, 0x90D8, 0x6118, 0x90D9, 0x6119, 0x90DA, 0x611A, 0xD3DE,
+	0x611B, 0x90DB, 0x611C, 0x90DC, 0x611D, 0x90DD, 0x611E, 0x90DE,	0x611F, 0xB8D0, 0x6120, 0xE3B3, 0x6121, 0x90DF, 0x6122, 0x90E0,
+	0x6123, 0xE3B6, 0x6124, 0xB7DF, 0x6125, 0x90E1, 0x6126, 0xE3B4,	0x6127, 0xC0A2, 0x6128, 0x90E2, 0x6129, 0x90E3, 0x612A, 0x90E4,
+	0x612B, 0xE3BA, 0x612C, 0x90E5, 0x612D, 0x90E6, 0x612E, 0x90E7,	0x612F, 0x90E8, 0x6130, 0x90E9, 0x6131, 0x90EA, 0x6132, 0x90EB,
+	0x6133, 0x90EC, 0x6134, 0x90ED, 0x6135, 0x90EE, 0x6136, 0x90EF,	0x6137, 0x90F0, 0x6138, 0x90F1, 0x6139, 0x90F2, 0x613A, 0x90F3,
+	0x613B, 0x90F4, 0x613C, 0x90F5, 0x613D, 0x90F6, 0x613E, 0x90F7,	0x613F, 0xD4B8, 0x6140, 0x90F8, 0x6141, 0x90F9, 0x6142, 0x90FA,
+	0x6143, 0x90FB, 0x6144, 0x90FC, 0x6145, 0x90FD, 0x6146, 0x90FE,	0x6147, 0x9140, 0x6148, 0xB4C8, 0x6149, 0x9141, 0x614A, 0xE3BB,
+	0x614B, 0x9142, 0x614C, 0xBBC5, 0x614D, 0x9143, 0x614E, 0xC9F7,	0x614F, 0x9144, 0x6150, 0x9145, 0x6151, 0xC9E5, 0x6152, 0x9146,
+	0x6153, 0x9147, 0x6154, 0x9148, 0x6155, 0xC4BD, 0x6156, 0x9149,	0x6157, 0x914A, 0x6158, 0x914B, 0x6159, 0x914C, 0x615A, 0x914D,
+	0x615B, 0x914E, 0x615C, 0x914F, 0x615D, 0xEDAB, 0x615E, 0x9150,	0x615F, 0x9151, 0x6160, 0x9152, 0x6161, 0x9153, 0x6162, 0xC2FD,
+	0x6163, 0x9154, 0x6164, 0x9155, 0x6165, 0x9156, 0x6166, 0x9157,	0x6167, 0xBBDB, 0x6168, 0xBFAE, 0x6169, 0x9158, 0x616A, 0x9159,
+	0x616B, 0x915A, 0x616C, 0x915B, 0x616D, 0x915C, 0x616E, 0x915D,	0x616F, 0x915E, 0x6170, 0xCEBF, 0x6171, 0x915F, 0x6172, 0x9160,
+	0x6173, 0x9161, 0x6174, 0x9162, 0x6175, 0xE3BC, 0x6176, 0x9163,	0x6177, 0xBFB6, 0x6178, 0x9164, 0x6179, 0x9165, 0x617A, 0x9166,
+	0x617B, 0x9167, 0x617C, 0x9168, 0x617D, 0x9169, 0x617E, 0x916A,	0x617F, 0x916B, 0x6180, 0x916C, 0x6181, 0x916D, 0x6182, 0x916E,
+	0x6183, 0x916F, 0x6184, 0x9170, 0x6185, 0x9171, 0x6186, 0x9172,	0x6187, 0x9173, 0x6188, 0x9174, 0x6189, 0x9175, 0x618A, 0x9176,
+	0x618B, 0xB1EF, 0x618C, 0x9177, 0x618D, 0x9178, 0x618E, 0xD4F7,	0x618F, 0x9179, 0x6190, 0x917A, 0x6191, 0x917B, 0x6192, 0x917C,
+	0x6193, 0x917D, 0x6194, 0xE3BE, 0x6195, 0x917E, 0x6196, 0x9180,	0x6197, 0x9181, 0x6198, 0x9182, 0x6199, 0x9183, 0x619A, 0x9184,
+	0x619B, 0x9185, 0x619C, 0x9186, 0x619D, 0xEDAD, 0x619E, 0x9187,	0x619F, 0x9188, 0x61A0, 0x9189, 0x61A1, 0x918A, 0x61A2, 0x918B,
+	0x61A3, 0x918C, 0x61A4, 0x918D, 0x61A5, 0x918E, 0x61A6, 0x918F,	0x61A7, 0xE3BF, 0x61A8, 0xBAA9, 0x61A9, 0xEDAC, 0x61AA, 0x9190,
+	0x61AB, 0x9191, 0x61AC, 0xE3BD, 0x61AD, 0x9192, 0x61AE, 0x9193,	0x61AF, 0x9194, 0x61B0, 0x9195, 0x61B1, 0x9196, 0x61B2, 0x9197,
+	0x61B3, 0x9198, 0x61B4, 0x9199, 0x61B5, 0x919A, 0x61B6, 0x919B,	0x61B7, 0xE3C0, 0x61B8, 0x919C, 0x61B9, 0x919D, 0x61BA, 0x919E,
+	0x61BB, 0x919F, 0x61BC, 0x91A0, 0x61BD, 0x91A1, 0x61BE, 0xBAB6,	0x61BF, 0x91A2, 0x61C0, 0x91A3, 0x61C1, 0x91A4, 0x61C2, 0xB6AE,
+	0x61C3, 0x91A5, 0x61C4, 0x91A6, 0x61C5, 0x91A7, 0x61C6, 0x91A8,	0x61C7, 0x91A9, 0x61C8, 0xD0B8, 0x61C9, 0x91AA, 0x61CA, 0xB0C3,
+	0x61CB, 0xEDAE, 0x61CC, 0x91AB, 0x61CD, 0x91AC, 0x61CE, 0x91AD,	0x61CF, 0x91AE, 0x61D0, 0x91AF, 0x61D1, 0xEDAF, 0x61D2, 0xC0C1,
+	0x61D3, 0x91B0, 0x61D4, 0xE3C1, 0x61D5, 0x91B1, 0x61D6, 0x91B2,	0x61D7, 0x91B3, 0x61D8, 0x91B4, 0x61D9, 0x91B5, 0x61DA, 0x91B6,
+	0x61DB, 0x91B7, 0x61DC, 0x91B8, 0x61DD, 0x91B9, 0x61DE, 0x91BA,	0x61DF, 0x91BB, 0x61E0, 0x91BC, 0x61E1, 0x91BD, 0x61E2, 0x91BE,
+	0x61E3, 0x91BF, 0x61E4, 0x91C0, 0x61E5, 0x91C1, 0x61E6, 0xC5B3,	0x61E7, 0x91C2, 0x61E8, 0x91C3, 0x61E9, 0x91C4, 0x61EA, 0x91C5,
+	0x61EB, 0x91C6, 0x61EC, 0x91C7, 0x61ED, 0x91C8, 0x61EE, 0x91C9,	0x61EF, 0x91CA, 0x61F0, 0x91CB, 0x61F1, 0x91CC, 0x61F2, 0x91CD,
+	0x61F3, 0x91CE, 0x61F4, 0x91CF, 0x61F5, 0xE3C2, 0x61F6, 0x91D0,	0x61F7, 0x91D1, 0x61F8, 0x91D2, 0x61F9, 0x91D3, 0x61FA, 0x91D4,
+	0x61FB, 0x91D5, 0x61FC, 0x91D6, 0x61FD, 0x91D7, 0x61FE, 0x91D8,	0x61FF, 0xDCB2, 0x6200, 0x91D9, 0x6201, 0x91DA, 0x6202, 0x91DB,
+	0x6203, 0x91DC, 0x6204, 0x91DD, 0x6205, 0x91DE, 0x6206, 0xEDB0,	0x6207, 0x91DF, 0x6208, 0xB8EA, 0x6209, 0x91E0, 0x620A, 0xCEEC,
+	0x620B, 0xEAA7, 0x620C, 0xD0E7, 0x620D, 0xCAF9, 0x620E, 0xC8D6,	0x620F, 0xCFB7, 0x6210, 0xB3C9, 0x6211, 0xCED2, 0x6212, 0xBDE4,
+	0x6213, 0x91E1, 0x6214, 0x91E2, 0x6215, 0xE3DE, 0x6216, 0xBBF2,	0x6217, 0xEAA8, 0x6218, 0xD5BD, 0x6219, 0x91E3, 0x621A, 0xC6DD,
+	0x621B, 0xEAA9, 0x621C, 0x91E4, 0x621D, 0x91E5, 0x621E, 0x91E6,	0x621F, 0xEAAA, 0x6220, 0x91E7, 0x6221, 0xEAAC, 0x6222, 0xEAAB,
+	0x6223, 0x91E8, 0x6224, 0xEAAE, 0x6225, 0xEAAD, 0x6226, 0x91E9,	0x6227, 0x91EA, 0x6228, 0x91EB, 0x6229, 0x91EC, 0x622A, 0xBDD8,
+	0x622B, 0x91ED, 0x622C, 0xEAAF, 0x622D, 0x91EE, 0x622E, 0xC2BE,	0x622F, 0x91EF, 0x6230, 0x91F0, 0x6231, 0x91F1, 0x6232, 0x91F2,
+	0x6233, 0xB4C1, 0x6234, 0xB4F7, 0x6235, 0x91F3, 0x6236, 0x91F4,	0x6237, 0xBBA7, 0x6238, 0x91F5, 0x6239, 0x91F6, 0x623A, 0x91F7,
+	0x623B, 0x91F8, 0x623C, 0x91F9, 0x623D, 0xECE6, 0x623E, 0xECE5,	0x623F, 0xB7BF, 0x6240, 0xCBF9, 0x6241, 0xB1E2, 0x6242, 0x91FA,
+	0x6243, 0xECE7, 0x6244, 0x91FB, 0x6245, 0x91FC, 0x6246, 0x91FD,	0x6247, 0xC9C8, 0x6248, 0xECE8, 0x6249, 0xECE9, 0x624A, 0x91FE,
+	0x624B, 0xCAD6, 0x624C, 0xDED0, 0x624D, 0xB2C5, 0x624E, 0xD4FA,	0x624F, 0x9240, 0x6250, 0x9241, 0x6251, 0xC6CB, 0x6252, 0xB0C7,
+	0x6253, 0xB4F2, 0x6254, 0xC8D3, 0x6255, 0x9242, 0x6256, 0x9243,	0x6257, 0x9244, 0x6258, 0xCDD0, 0x6259, 0x9245, 0x625A, 0x9246,
+	0x625B, 0xBFB8, 0x625C, 0x9247, 0x625D, 0x9248, 0x625E, 0x9249,	0x625F, 0x924A, 0x6260, 0x924B, 0x6261, 0x924C, 0x6262, 0x924D,
+	0x6263, 0xBFDB, 0x6264, 0x924E, 0x6265, 0x924F, 0x6266, 0xC7A4,	0x6267, 0xD6B4, 0x6268, 0x9250, 0x6269, 0xC0A9, 0x626A, 0xDED1,
+	0x626B, 0xC9A8, 0x626C, 0xD1EF, 0x626D, 0xC5A4, 0x626E, 0xB0E7,	0x626F, 0xB3B6, 0x6270, 0xC8C5, 0x6271, 0x9251, 0x6272, 0x9252,
+	0x6273, 0xB0E2, 0x6274, 0x9253, 0x6275, 0x9254, 0x6276, 0xB7F6,	0x6277, 0x9255, 0x6278, 0x9256, 0x6279, 0xC5FA, 0x627A, 0x9257,
+	0x627B, 0x9258, 0x627C, 0xB6F3, 0x627D, 0x9259, 0x627E, 0xD5D2,	0x627F, 0xB3D0, 0x6280, 0xBCBC, 0x6281, 0x925A, 0x6282, 0x925B,
+	0x6283, 0x925C, 0x6284, 0xB3AD, 0x6285, 0x925D, 0x6286, 0x925E,	0x6287, 0x925F, 0x6288, 0x9260, 0x6289, 0xBEF1, 0x628A, 0xB0D1,
+	0x628B, 0x9261, 0x628C, 0x9262, 0x628D, 0x9263, 0x628E, 0x9264,	0x628F, 0x9265, 0x6290, 0x9266, 0x6291, 0xD2D6, 0x6292, 0xCAE3,
+	0x6293, 0xD7A5, 0x6294, 0x9267, 0x6295, 0xCDB6, 0x6296, 0xB6B6,	0x6297, 0xBFB9, 0x6298, 0xD5DB, 0x6299, 0x9268, 0x629A, 0xB8A7,
+	0x629B, 0xC5D7, 0x629C, 0x9269, 0x629D, 0x926A, 0x629E, 0x926B,	0x629F, 0xDED2, 0x62A0, 0xBFD9, 0x62A1, 0xC2D5, 0x62A2, 0xC7C0,
+	0x62A3, 0x926C, 0x62A4, 0xBBA4, 0x62A5, 0xB1A8, 0x62A6, 0x926D,	0x62A7, 0x926E, 0x62A8, 0xC5EA, 0x62A9, 0x926F, 0x62AA, 0x9270,
+	0x62AB, 0xC5FB, 0x62AC, 0xCCA7, 0x62AD, 0x9271, 0x62AE, 0x9272,	0x62AF, 0x9273, 0x62B0, 0x9274, 0x62B1, 0xB1A7, 0x62B2, 0x9275,
+	0x62B3, 0x9276, 0x62B4, 0x9277, 0x62B5, 0xB5D6, 0x62B6, 0x9278,	0x62B7, 0x9279, 0x62B8, 0x927A, 0x62B9, 0xC4A8, 0x62BA, 0x927B,
+	0x62BB, 0xDED3, 0x62BC, 0xD1BA, 0x62BD, 0xB3E9, 0x62BE, 0x927C,	0x62BF, 0xC3F2, 0x62C0, 0x927D, 0x62C1, 0x927E, 0x62C2, 0xB7F7,
+	0x62C3, 0x9280, 0x62C4, 0xD6F4, 0x62C5, 0xB5A3, 0x62C6, 0xB2F0,	0x62C7, 0xC4B4, 0x62C8, 0xC4E9, 0x62C9, 0xC0AD, 0x62CA, 0xDED4,
+	0x62CB, 0x9281, 0x62CC, 0xB0E8, 0x62CD, 0xC5C4, 0x62CE, 0xC1E0,	0x62CF, 0x9282, 0x62D0, 0xB9D5, 0x62D1, 0x9283, 0x62D2, 0xBEDC,
+	0x62D3, 0xCDD8, 0x62D4, 0xB0CE, 0x62D5, 0x9284, 0x62D6, 0xCDCF,	0x62D7, 0xDED6, 0x62D8, 0xBED0, 0x62D9, 0xD7BE, 0x62DA, 0xDED5,
+	0x62DB, 0xD5D0, 0x62DC, 0xB0DD, 0x62DD, 0x9285, 0x62DE, 0x9286,	0x62DF, 0xC4E2, 0x62E0, 0x9287, 0x62E1, 0x9288, 0x62E2, 0xC2A3,
+	0x62E3, 0xBCF0, 0x62E4, 0x9289, 0x62E5, 0xD3B5, 0x62E6, 0xC0B9,	0x62E7, 0xC5A1, 0x62E8, 0xB2A6, 0x62E9, 0xD4F1, 0x62EA, 0x928A,
+	0x62EB, 0x928B, 0x62EC, 0xC0A8, 0x62ED, 0xCAC3, 0x62EE, 0xDED7,	0x62EF, 0xD5FC, 0x62F0, 0x928C, 0x62F1, 0xB9B0, 0x62F2, 0x928D,
+	0x62F3, 0xC8AD, 0x62F4, 0xCBA9, 0x62F5, 0x928E, 0x62F6, 0xDED9,	0x62F7, 0xBFBD, 0x62F8, 0x928F, 0x62F9, 0x9290, 0x62FA, 0x9291,
+	0x62FB, 0x9292, 0x62FC, 0xC6B4, 0x62FD, 0xD7A7, 0x62FE, 0xCAB0,	0x62FF, 0xC4C3, 0x6300, 0x9293, 0x6301, 0xB3D6, 0x6302, 0xB9D2,
+	0x6303, 0x9294, 0x6304, 0x9295, 0x6305, 0x9296, 0x6306, 0x9297,	0x6307, 0xD6B8, 0x6308, 0xEAFC, 0x6309, 0xB0B4, 0x630A, 0x9298,
+	0x630B, 0x9299, 0x630C, 0x929A, 0x630D, 0x929B, 0x630E, 0xBFE6,	0x630F, 0x929C, 0x6310, 0x929D, 0x6311, 0xCCF4, 0x6312, 0x929E,
+	0x6313, 0x929F, 0x6314, 0x92A0, 0x6315, 0x92A1, 0x6316, 0xCDDA,	0x6317, 0x92A2, 0x6318, 0x92A3, 0x6319, 0x92A4, 0x631A, 0xD6BF,
+	0x631B, 0xC2CE, 0x631C, 0x92A5, 0x631D, 0xCECE, 0x631E, 0xCCA2,	0x631F, 0xD0AE, 0x6320, 0xC4D3, 0x6321, 0xB5B2, 0x6322, 0xDED8,
+	0x6323, 0xD5F5, 0x6324, 0xBCB7, 0x6325, 0xBBD3, 0x6326, 0x92A6,	0x6327, 0x92A7, 0x6328, 0xB0A4, 0x6329, 0x92A8, 0x632A, 0xC5B2,
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+	0x6B83, 0xD1EA, 0x6B84, 0xE9E5, 0x6B85, 0x9A7D, 0x6B86, 0xB4F9,	0x6B87, 0xE9E4, 0x6B88, 0x9A7E, 0x6B89, 0xD1B3, 0x6B8A, 0xCAE2,
+	0x6B8B, 0xB2D0, 0x6B8C, 0x9A80, 0x6B8D, 0xE9E8, 0x6B8E, 0x9A81,	0x6B8F, 0x9A82, 0x6B90, 0x9A83, 0x6B91, 0x9A84, 0x6B92, 0xE9E6,
+	0x6B93, 0xE9E7, 0x6B94, 0x9A85, 0x6B95, 0x9A86, 0x6B96, 0xD6B3,	0x6B97, 0x9A87, 0x6B98, 0x9A88, 0x6B99, 0x9A89, 0x6B9A, 0xE9E9,
+	0x6B9B, 0xE9EA, 0x6B9C, 0x9A8A, 0x6B9D, 0x9A8B, 0x6B9E, 0x9A8C,	0x6B9F, 0x9A8D, 0x6BA0, 0x9A8E, 0x6BA1, 0xE9EB, 0x6BA2, 0x9A8F,
+	0x6BA3, 0x9A90, 0x6BA4, 0x9A91, 0x6BA5, 0x9A92, 0x6BA6, 0x9A93,	0x6BA7, 0x9A94, 0x6BA8, 0x9A95, 0x6BA9, 0x9A96, 0x6BAA, 0xE9EC,
+	0x6BAB, 0x9A97, 0x6BAC, 0x9A98, 0x6BAD, 0x9A99, 0x6BAE, 0x9A9A,	0x6BAF, 0x9A9B, 0x6BB0, 0x9A9C, 0x6BB1, 0x9A9D, 0x6BB2, 0x9A9E,
+	0x6BB3, 0xECAF, 0x6BB4, 0xC5B9, 0x6BB5, 0xB6CE, 0x6BB6, 0x9A9F,	0x6BB7, 0xD2F3, 0x6BB8, 0x9AA0, 0x6BB9, 0x9AA1, 0x6BBA, 0x9AA2,
+	0x6BBB, 0x9AA3, 0x6BBC, 0x9AA4, 0x6BBD, 0x9AA5, 0x6BBE, 0x9AA6,	0x6BBF, 0xB5EE, 0x6BC0, 0x9AA7, 0x6BC1, 0xBBD9, 0x6BC2, 0xECB1,
+	0x6BC3, 0x9AA8, 0x6BC4, 0x9AA9, 0x6BC5, 0xD2E3, 0x6BC6, 0x9AAA,	0x6BC7, 0x9AAB, 0x6BC8, 0x9AAC, 0x6BC9, 0x9AAD, 0x6BCA, 0x9AAE,
+	0x6BCB, 0xCEE3, 0x6BCC, 0x9AAF, 0x6BCD, 0xC4B8, 0x6BCE, 0x9AB0,	0x6BCF, 0xC3BF, 0x6BD0, 0x9AB1, 0x6BD1, 0x9AB2, 0x6BD2, 0xB6BE,
+	0x6BD3, 0xD8B9, 0x6BD4, 0xB1C8, 0x6BD5, 0xB1CF, 0x6BD6, 0xB1D1,	0x6BD7, 0xC5FE, 0x6BD8, 0x9AB3, 0x6BD9, 0xB1D0, 0x6BDA, 0x9AB4,
+	0x6BDB, 0xC3AB, 0x6BDC, 0x9AB5, 0x6BDD, 0x9AB6, 0x6BDE, 0x9AB7,	0x6BDF, 0x9AB8, 0x6BE0, 0x9AB9, 0x6BE1, 0xD5B1, 0x6BE2, 0x9ABA,
+	0x6BE3, 0x9ABB, 0x6BE4, 0x9ABC, 0x6BE5, 0x9ABD, 0x6BE6, 0x9ABE,	0x6BE7, 0x9ABF, 0x6BE8, 0x9AC0, 0x6BE9, 0x9AC1, 0x6BEA, 0xEBA4,
+	0x6BEB, 0xBAC1, 0x6BEC, 0x9AC2, 0x6BED, 0x9AC3, 0x6BEE, 0x9AC4,	0x6BEF, 0xCCBA, 0x6BF0, 0x9AC5, 0x6BF1, 0x9AC6, 0x6BF2, 0x9AC7,
+	0x6BF3, 0xEBA5, 0x6BF4, 0x9AC8, 0x6BF5, 0xEBA7, 0x6BF6, 0x9AC9,	0x6BF7, 0x9ACA, 0x6BF8, 0x9ACB, 0x6BF9, 0xEBA8, 0x6BFA, 0x9ACC,
+	0x6BFB, 0x9ACD, 0x6BFC, 0x9ACE, 0x6BFD, 0xEBA6, 0x6BFE, 0x9ACF,	0x6BFF, 0x9AD0, 0x6C00, 0x9AD1, 0x6C01, 0x9AD2, 0x6C02, 0x9AD3,
+	0x6C03, 0x9AD4, 0x6C04, 0x9AD5, 0x6C05, 0xEBA9, 0x6C06, 0xEBAB,	0x6C07, 0xEBAA, 0x6C08, 0x9AD6, 0x6C09, 0x9AD7, 0x6C0A, 0x9AD8,
+	0x6C0B, 0x9AD9, 0x6C0C, 0x9ADA, 0x6C0D, 0xEBAC, 0x6C0E, 0x9ADB,	0x6C0F, 0xCACF, 0x6C10, 0xD8B5, 0x6C11, 0xC3F1, 0x6C12, 0x9ADC,
+	0x6C13, 0xC3A5, 0x6C14, 0xC6F8, 0x6C15, 0xEBAD, 0x6C16, 0xC4CA,	0x6C17, 0x9ADD, 0x6C18, 0xEBAE, 0x6C19, 0xEBAF, 0x6C1A, 0xEBB0,
+	0x6C1B, 0xB7D5, 0x6C1C, 0x9ADE, 0x6C1D, 0x9ADF, 0x6C1E, 0x9AE0,	0x6C1F, 0xB7FA, 0x6C20, 0x9AE1, 0x6C21, 0xEBB1, 0x6C22, 0xC7E2,
+	0x6C23, 0x9AE2, 0x6C24, 0xEBB3, 0x6C25, 0x9AE3, 0x6C26, 0xBAA4,	0x6C27, 0xD1F5, 0x6C28, 0xB0B1, 0x6C29, 0xEBB2, 0x6C2A, 0xEBB4,
+	0x6C2B, 0x9AE4, 0x6C2C, 0x9AE5, 0x6C2D, 0x9AE6, 0x6C2E, 0xB5AA,	0x6C2F, 0xC2C8, 0x6C30, 0xC7E8, 0x6C31, 0x9AE7, 0x6C32, 0xEBB5,
+	0x6C33, 0x9AE8, 0x6C34, 0xCBAE, 0x6C35, 0xE3DF, 0x6C36, 0x9AE9,	0x6C37, 0x9AEA, 0x6C38, 0xD3C0, 0x6C39, 0x9AEB, 0x6C3A, 0x9AEC,
+	0x6C3B, 0x9AED, 0x6C3C, 0x9AEE, 0x6C3D, 0xD9DB, 0x6C3E, 0x9AEF,	0x6C3F, 0x9AF0, 0x6C40, 0xCDA1, 0x6C41, 0xD6AD, 0x6C42, 0xC7F3,
+	0x6C43, 0x9AF1, 0x6C44, 0x9AF2, 0x6C45, 0x9AF3, 0x6C46, 0xD9E0,	0x6C47, 0xBBE3, 0x6C48, 0x9AF4, 0x6C49, 0xBABA, 0x6C4A, 0xE3E2,
+	0x6C4B, 0x9AF5, 0x6C4C, 0x9AF6, 0x6C4D, 0x9AF7, 0x6C4E, 0x9AF8,	0x6C4F, 0x9AF9, 0x6C50, 0xCFAB, 0x6C51, 0x9AFA, 0x6C52, 0x9AFB,
+	0x6C53, 0x9AFC, 0x6C54, 0xE3E0, 0x6C55, 0xC9C7, 0x6C56, 0x9AFD,	0x6C57, 0xBAB9, 0x6C58, 0x9AFE, 0x6C59, 0x9B40, 0x6C5A, 0x9B41,
+	0x6C5B, 0xD1B4, 0x6C5C, 0xE3E1, 0x6C5D, 0xC8EA, 0x6C5E, 0xB9AF,	0x6C5F, 0xBDAD, 0x6C60, 0xB3D8, 0x6C61, 0xCEDB, 0x6C62, 0x9B42,
+	0x6C63, 0x9B43, 0x6C64, 0xCCC0, 0x6C65, 0x9B44, 0x6C66, 0x9B45,	0x6C67, 0x9B46, 0x6C68, 0xE3E8, 0x6C69, 0xE3E9, 0x6C6A, 0xCDF4,
+	0x6C6B, 0x9B47, 0x6C6C, 0x9B48, 0x6C6D, 0x9B49, 0x6C6E, 0x9B4A,	0x6C6F, 0x9B4B, 0x6C70, 0xCCAD, 0x6C71, 0x9B4C, 0x6C72, 0xBCB3,
+	0x6C73, 0x9B4D, 0x6C74, 0xE3EA, 0x6C75, 0x9B4E, 0x6C76, 0xE3EB,	0x6C77, 0x9B4F, 0x6C78, 0x9B50, 0x6C79, 0xD0DA, 0x6C7A, 0x9B51,
+	0x6C7B, 0x9B52, 0x6C7C, 0x9B53, 0x6C7D, 0xC6FB, 0x6C7E, 0xB7DA,	0x6C7F, 0x9B54, 0x6C80, 0x9B55, 0x6C81, 0xC7DF, 0x6C82, 0xD2CA,
+	0x6C83, 0xCED6, 0x6C84, 0x9B56, 0x6C85, 0xE3E4, 0x6C86, 0xE3EC,	0x6C87, 0x9B57, 0x6C88, 0xC9F2, 0x6C89, 0xB3C1, 0x6C8A, 0x9B58,
+	0x6C8B, 0x9B59, 0x6C8C, 0xE3E7, 0x6C8D, 0x9B5A, 0x6C8E, 0x9B5B,	0x6C8F, 0xC6E3, 0x6C90, 0xE3E5, 0x6C91, 0x9B5C, 0x6C92, 0x9B5D,
+	0x6C93, 0xEDB3, 0x6C94, 0xE3E6, 0x6C95, 0x9B5E, 0x6C96, 0x9B5F,	0x6C97, 0x9B60, 0x6C98, 0x9B61, 0x6C99, 0xC9B3, 0x6C9A, 0x9B62,
+	0x6C9B, 0xC5E6, 0x6C9C, 0x9B63, 0x6C9D, 0x9B64, 0x6C9E, 0x9B65,	0x6C9F, 0xB9B5, 0x6CA0, 0x9B66, 0x6CA1, 0xC3BB, 0x6CA2, 0x9B67,
+	0x6CA3, 0xE3E3, 0x6CA4, 0xC5BD, 0x6CA5, 0xC1A4, 0x6CA6, 0xC2D9,	0x6CA7, 0xB2D7, 0x6CA8, 0x9B68, 0x6CA9, 0xE3ED, 0x6CAA, 0xBBA6,
+	0x6CAB, 0xC4AD, 0x6CAC, 0x9B69, 0x6CAD, 0xE3F0, 0x6CAE, 0xBEDA,	0x6CAF, 0x9B6A, 0x6CB0, 0x9B6B, 0x6CB1, 0xE3FB, 0x6CB2, 0xE3F5,
+	0x6CB3, 0xBAD3, 0x6CB4, 0x9B6C, 0x6CB5, 0x9B6D, 0x6CB6, 0x9B6E,	0x6CB7, 0x9B6F, 0x6CB8, 0xB7D0, 0x6CB9, 0xD3CD, 0x6CBA, 0x9B70,
+	0x6CBB, 0xD6CE, 0x6CBC, 0xD5D3, 0x6CBD, 0xB9C1, 0x6CBE, 0xD5B4,	0x6CBF, 0xD1D8, 0x6CC0, 0x9B71, 0x6CC1, 0x9B72, 0x6CC2, 0x9B73,
+	0x6CC3, 0x9B74, 0x6CC4, 0xD0B9, 0x6CC5, 0xC7F6, 0x6CC6, 0x9B75,	0x6CC7, 0x9B76, 0x6CC8, 0x9B77, 0x6CC9, 0xC8AA, 0x6CCA, 0xB2B4,
+	0x6CCB, 0x9B78, 0x6CCC, 0xC3DA, 0x6CCD, 0x9B79, 0x6CCE, 0x9B7A,	0x6CCF, 0x9B7B, 0x6CD0, 0xE3EE, 0x6CD1, 0x9B7C, 0x6CD2, 0x9B7D,
+	0x6CD3, 0xE3FC, 0x6CD4, 0xE3EF, 0x6CD5, 0xB7A8, 0x6CD6, 0xE3F7,	0x6CD7, 0xE3F4, 0x6CD8, 0x9B7E, 0x6CD9, 0x9B80, 0x6CDA, 0x9B81,
+	0x6CDB, 0xB7BA, 0x6CDC, 0x9B82, 0x6CDD, 0x9B83, 0x6CDE, 0xC5A2,	0x6CDF, 0x9B84, 0x6CE0, 0xE3F6, 0x6CE1, 0xC5DD, 0x6CE2, 0xB2A8,
+	0x6CE3, 0xC6FC, 0x6CE4, 0x9B85, 0x6CE5, 0xC4E0, 0x6CE6, 0x9B86,	0x6CE7, 0x9B87, 0x6CE8, 0xD7A2, 0x6CE9, 0x9B88, 0x6CEA, 0xC0E1,
+	0x6CEB, 0xE3F9, 0x6CEC, 0x9B89, 0x6CED, 0x9B8A, 0x6CEE, 0xE3FA,	0x6CEF, 0xE3FD, 0x6CF0, 0xCCA9, 0x6CF1, 0xE3F3, 0x6CF2, 0x9B8B,
+	0x6CF3, 0xD3BE, 0x6CF4, 0x9B8C, 0x6CF5, 0xB1C3, 0x6CF6, 0xEDB4,	0x6CF7, 0xE3F1, 0x6CF8, 0xE3F2, 0x6CF9, 0x9B8D, 0x6CFA, 0xE3F8,
+	0x6CFB, 0xD0BA, 0x6CFC, 0xC6C3, 0x6CFD, 0xD4F3, 0x6CFE, 0xE3FE,	0x6CFF, 0x9B8E, 0x6D00, 0x9B8F, 0x6D01, 0xBDE0, 0x6D02, 0x9B90,
+	0x6D03, 0x9B91, 0x6D04, 0xE4A7, 0x6D05, 0x9B92, 0x6D06, 0x9B93,	0x6D07, 0xE4A6, 0x6D08, 0x9B94, 0x6D09, 0x9B95, 0x6D0A, 0x9B96,
+	0x6D0B, 0xD1F3, 0x6D0C, 0xE4A3, 0x6D0D, 0x9B97, 0x6D0E, 0xE4A9,	0x6D0F, 0x9B98, 0x6D10, 0x9B99, 0x6D11, 0x9B9A, 0x6D12, 0xC8F7,
+	0x6D13, 0x9B9B, 0x6D14, 0x9B9C, 0x6D15, 0x9B9D, 0x6D16, 0x9B9E,	0x6D17, 0xCFB4, 0x6D18, 0x9B9F, 0x6D19, 0xE4A8, 0x6D1A, 0xE4AE,
+	0x6D1B, 0xC2E5, 0x6D1C, 0x9BA0, 0x6D1D, 0x9BA1, 0x6D1E, 0xB6B4,	0x6D1F, 0x9BA2, 0x6D20, 0x9BA3, 0x6D21, 0x9BA4, 0x6D22, 0x9BA5,
+	0x6D23, 0x9BA6, 0x6D24, 0x9BA7, 0x6D25, 0xBDF2, 0x6D26, 0x9BA8,	0x6D27, 0xE4A2, 0x6D28, 0x9BA9, 0x6D29, 0x9BAA, 0x6D2A, 0xBAE9,
+	0x6D2B, 0xE4AA, 0x6D2C, 0x9BAB, 0x6D2D, 0x9BAC, 0x6D2E, 0xE4AC,	0x6D2F, 0x9BAD, 0x6D30, 0x9BAE, 0x6D31, 0xB6FD, 0x6D32, 0xD6DE,
+	0x6D33, 0xE4B2, 0x6D34, 0x9BAF, 0x6D35, 0xE4AD, 0x6D36, 0x9BB0,	0x6D37, 0x9BB1, 0x6D38, 0x9BB2, 0x6D39, 0xE4A1, 0x6D3A, 0x9BB3,
+	0x6D3B, 0xBBEE, 0x6D3C, 0xCDDD, 0x6D3D, 0xC7A2, 0x6D3E, 0xC5C9,	0x6D3F, 0x9BB4, 0x6D40, 0x9BB5, 0x6D41, 0xC1F7, 0x6D42, 0x9BB6,
+	0x6D43, 0xE4A4, 0x6D44, 0x9BB7, 0x6D45, 0xC7B3, 0x6D46, 0xBDAC,	0x6D47, 0xBDBD, 0x6D48, 0xE4A5, 0x6D49, 0x9BB8, 0x6D4A, 0xD7C7,
+	0x6D4B, 0xB2E2, 0x6D4C, 0x9BB9, 0x6D4D, 0xE4AB, 0x6D4E, 0xBCC3,	0x6D4F, 0xE4AF, 0x6D50, 0x9BBA, 0x6D51, 0xBBEB, 0x6D52, 0xE4B0,
+	0x6D53, 0xC5A8, 0x6D54, 0xE4B1, 0x6D55, 0x9BBB, 0x6D56, 0x9BBC,	0x6D57, 0x9BBD, 0x6D58, 0x9BBE, 0x6D59, 0xD5E3, 0x6D5A, 0xBFA3,
+	0x6D5B, 0x9BBF, 0x6D5C, 0xE4BA, 0x6D5D, 0x9BC0, 0x6D5E, 0xE4B7,	0x6D5F, 0x9BC1, 0x6D60, 0xE4BB, 0x6D61, 0x9BC2, 0x6D62, 0x9BC3,
+	0x6D63, 0xE4BD, 0x6D64, 0x9BC4, 0x6D65, 0x9BC5, 0x6D66, 0xC6D6,	0x6D67, 0x9BC6, 0x6D68, 0x9BC7, 0x6D69, 0xBAC6, 0x6D6A, 0xC0CB,
+	0x6D6B, 0x9BC8, 0x6D6C, 0x9BC9, 0x6D6D, 0x9BCA, 0x6D6E, 0xB8A1,	0x6D6F, 0xE4B4, 0x6D70, 0x9BCB, 0x6D71, 0x9BCC, 0x6D72, 0x9BCD,
+	0x6D73, 0x9BCE, 0x6D74, 0xD4A1, 0x6D75, 0x9BCF, 0x6D76, 0x9BD0,	0x6D77, 0xBAA3, 0x6D78, 0xBDFE, 0x6D79, 0x9BD1, 0x6D7A, 0x9BD2,
+	0x6D7B, 0x9BD3, 0x6D7C, 0xE4BC, 0x6D7D, 0x9BD4, 0x6D7E, 0x9BD5,	0x6D7F, 0x9BD6, 0x6D80, 0x9BD7, 0x6D81, 0x9BD8, 0x6D82, 0xCDBF,
+	0x6D83, 0x9BD9, 0x6D84, 0x9BDA, 0x6D85, 0xC4F9, 0x6D86, 0x9BDB,	0x6D87, 0x9BDC, 0x6D88, 0xCFFB, 0x6D89, 0xC9E6, 0x6D8A, 0x9BDD,
+	0x6D8B, 0x9BDE, 0x6D8C, 0xD3BF, 0x6D8D, 0x9BDF, 0x6D8E, 0xCFD1,	0x6D8F, 0x9BE0, 0x6D90, 0x9BE1, 0x6D91, 0xE4B3, 0x6D92, 0x9BE2,
+	0x6D93, 0xE4B8, 0x6D94, 0xE4B9, 0x6D95, 0xCCE9, 0x6D96, 0x9BE3,	0x6D97, 0x9BE4, 0x6D98, 0x9BE5, 0x6D99, 0x9BE6, 0x6D9A, 0x9BE7,
+	0x6D9B, 0xCCCE, 0x6D9C, 0x9BE8, 0x6D9D, 0xC0D4, 0x6D9E, 0xE4B5,	0x6D9F, 0xC1B0, 0x6DA0, 0xE4B6, 0x6DA1, 0xCED0, 0x6DA2, 0x9BE9,
+	0x6DA3, 0xBBC1, 0x6DA4, 0xB5D3, 0x6DA5, 0x9BEA, 0x6DA6, 0xC8F3,	0x6DA7, 0xBDA7, 0x6DA8, 0xD5C7, 0x6DA9, 0xC9AC, 0x6DAA, 0xB8A2,
+	0x6DAB, 0xE4CA, 0x6DAC, 0x9BEB, 0x6DAD, 0x9BEC, 0x6DAE, 0xE4CC,	0x6DAF, 0xD1C4, 0x6DB0, 0x9BED, 0x6DB1, 0x9BEE, 0x6DB2, 0xD2BA,
+	0x6DB3, 0x9BEF, 0x6DB4, 0x9BF0, 0x6DB5, 0xBAAD, 0x6DB6, 0x9BF1,	0x6DB7, 0x9BF2, 0x6DB8, 0xBAD4, 0x6DB9, 0x9BF3, 0x6DBA, 0x9BF4,
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+	0x75AB, 0xD2DF, 0x75AC, 0xF0DF, 0x75AD, 0xAF53, 0x75AE, 0xB4AF,	0x75AF, 0xB7E8, 0x75B0, 0xF0E6, 0x75B1, 0xF0E5, 0x75B2, 0xC6A3,
+	0x75B3, 0xF0E1, 0x75B4, 0xF0E2, 0x75B5, 0xB4C3, 0x75B6, 0xAF54,	0x75B7, 0xAF55, 0x75B8, 0xF0E3, 0x75B9, 0xD5EE, 0x75BA, 0xAF56,
+	0x75BB, 0xAF57, 0x75BC, 0xCCDB, 0x75BD, 0xBED2, 0x75BE, 0xBCB2,	0x75BF, 0xAF58, 0x75C0, 0xAF59, 0x75C1, 0xAF5A, 0x75C2, 0xF0E8,
+	0x75C3, 0xF0E7, 0x75C4, 0xF0E4, 0x75C5, 0xB2A1, 0x75C6, 0xAF5B,	0x75C7, 0xD6A2, 0x75C8, 0xD3B8, 0x75C9, 0xBEB7, 0x75CA, 0xC8AC,
+	0x75CB, 0xAF5C, 0x75CC, 0xAF5D, 0x75CD, 0xF0EA, 0x75CE, 0xAF5E,	0x75CF, 0xAF5F, 0x75D0, 0xAF60, 0x75D1, 0xAF61, 0x75D2, 0xD1F7,
+	0x75D3, 0xAF62, 0x75D4, 0xD6CC, 0x75D5, 0xBADB, 0x75D6, 0xF0E9,	0x75D7, 0xAF63, 0x75D8, 0xB6BB, 0x75D9, 0xAF64, 0x75DA, 0xAF65,
+	0x75DB, 0xCDB4, 0x75DC, 0xAF66, 0x75DD, 0xAF67, 0x75DE, 0xC6A6,	0x75DF, 0xAF68, 0x75E0, 0xAF69, 0x75E1, 0xAF6A, 0x75E2, 0xC1A1,
+	0x75E3, 0xF0EB, 0x75E4, 0xF0EE, 0x75E5, 0xAF6B, 0x75E6, 0xF0ED,	0x75E7, 0xF0F0, 0x75E8, 0xF0EC, 0x75E9, 0xAF6C, 0x75EA, 0xBBBE,
+	0x75EB, 0xF0EF, 0x75EC, 0xAF6D, 0x75ED, 0xAF6E, 0x75EE, 0xAF6F,	0x75EF, 0xAF70, 0x75F0, 0xCCB5, 0x75F1, 0xF0F2, 0x75F2, 0xAF71,
+	0x75F3, 0xAF72, 0x75F4, 0xB3D5, 0x75F5, 0xAF73, 0x75F6, 0xAF74,	0x75F7, 0xAF75, 0x75F8, 0xAF76, 0x75F9, 0xB1D4, 0x75FA, 0xAF77,
+	0x75FB, 0xAF78, 0x75FC, 0xF0F3, 0x75FD, 0xAF79, 0x75FE, 0xAF7A,	0x75FF, 0xF0F4, 0x7600, 0xF0F6, 0x7601, 0xB4E1, 0x7602, 0xAF7B,
+	0x7603, 0xF0F1, 0x7604, 0xAF7C, 0x7605, 0xF0F7, 0x7606, 0xAF7D,	0x7607, 0xAF7E, 0x7608, 0xAF80, 0x7609, 0xAF81, 0x760A, 0xF0FA,
+	0x760B, 0xAF82, 0x760C, 0xF0F8, 0x760D, 0xAF83, 0x760E, 0xAF84,	0x760F, 0xAF85, 0x7610, 0xF0F5, 0x7611, 0xAF86, 0x7612, 0xAF87,
+	0x7613, 0xAF88, 0x7614, 0xAF89, 0x7615, 0xF0FD, 0x7616, 0xAF8A,	0x7617, 0xF0F9, 0x7618, 0xF0FC, 0x7619, 0xF0FE, 0x761A, 0xAF8B,
+	0x761B, 0xF1A1, 0x761C, 0xAF8C, 0x761D, 0xAF8D, 0x761E, 0xAF8E,	0x761F, 0xCEC1, 0x7620, 0xF1A4, 0x7621, 0xAF8F, 0x7622, 0xF1A3,
+	0x7623, 0xAF90, 0x7624, 0xC1F6, 0x7625, 0xF0FB, 0x7626, 0xCADD,	0x7627, 0xAF91, 0x7628, 0xAF92, 0x7629, 0xB4F1, 0x762A, 0xB1F1,
+	0x762B, 0xCCB1, 0x762C, 0xAF93, 0x762D, 0xF1A6, 0x762E, 0xAF94,	0x762F, 0xAF95, 0x7630, 0xF1A7, 0x7631, 0xAF96, 0x7632, 0xAF97,
+	0x7633, 0xF1AC, 0x7634, 0xD5CE, 0x7635, 0xF1A9, 0x7636, 0xAF98,	0x7637, 0xAF99, 0x7638, 0xC8B3, 0x7639, 0xAF9A, 0x763A, 0xAF9B,
+	0x763B, 0xAF9C, 0x763C, 0xF1A2, 0x763D, 0xAF9D, 0x763E, 0xF1AB,	0x763F, 0xF1A8, 0x7640, 0xF1A5, 0x7641, 0xAF9E, 0x7642, 0xAF9F,
+	0x7643, 0xF1AA, 0x7644, 0xAFA0, 0x7645, 0xB040, 0x7646, 0xB041,	0x7647, 0xB042, 0x7648, 0xB043, 0x7649, 0xB044, 0x764A, 0xB045,
+	0x764B, 0xB046, 0x764C, 0xB0A9, 0x764D, 0xF1AD, 0x764E, 0xB047,	0x764F, 0xB048, 0x7650, 0xB049, 0x7651, 0xB04A, 0x7652, 0xB04B,
+	0x7653, 0xB04C, 0x7654, 0xF1AF, 0x7655, 0xB04D, 0x7656, 0xF1B1,	0x7657, 0xB04E, 0x7658, 0xB04F, 0x7659, 0xB050, 0x765A, 0xB051,
+	0x765B, 0xB052, 0x765C, 0xF1B0, 0x765D, 0xB053, 0x765E, 0xF1AE,	0x765F, 0xB054, 0x7660, 0xB055, 0x7661, 0xB056, 0x7662, 0xB057,
+	0x7663, 0xD1A2, 0x7664, 0xB058, 0x7665, 0xB059, 0x7666, 0xB05A,	0x7667, 0xB05B, 0x7668, 0xB05C, 0x7669, 0xB05D, 0x766A, 0xB05E,
+	0x766B, 0xF1B2, 0x766C, 0xB05F, 0x766D, 0xB060, 0x766E, 0xB061,	0x766F, 0xF1B3, 0x7670, 0xB062, 0x7671, 0xB063, 0x7672, 0xB064,
+	0x7673, 0xB065, 0x7674, 0xB066, 0x7675, 0xB067, 0x7676, 0xB068,	0x7677, 0xB069, 0x7678, 0xB9EF, 0x7679, 0xB06A, 0x767A, 0xB06B,
+	0x767B, 0xB5C7, 0x767C, 0xB06C, 0x767D, 0xB0D7, 0x767E, 0xB0D9,	0x767F, 0xB06D, 0x7680, 0xB06E, 0x7681, 0xB06F, 0x7682, 0xD4ED,
+	0x7683, 0xB070, 0x7684, 0xB5C4, 0x7685, 0xB071, 0x7686, 0xBDD4,	0x7687, 0xBBCA, 0x7688, 0xF0A7, 0x7689, 0xB072, 0x768A, 0xB073,
+	0x768B, 0xB8DE, 0x768C, 0xB074, 0x768D, 0xB075, 0x768E, 0xF0A8,	0x768F, 0xB076, 0x7690, 0xB077, 0x7691, 0xB0A8, 0x7692, 0xB078,
+	0x7693, 0xF0A9, 0x7694, 0xB079, 0x7695, 0xB07A, 0x7696, 0xCDEE,	0x7697, 0xB07B, 0x7698, 0xB07C, 0x7699, 0xF0AA, 0x769A, 0xB07D,
+	0x769B, 0xB07E, 0x769C, 0xB080, 0x769D, 0xB081, 0x769E, 0xB082,	0x769F, 0xB083, 0x76A0, 0xB084, 0x76A1, 0xB085, 0x76A2, 0xB086,
+	0x76A3, 0xB087, 0x76A4, 0xF0AB, 0x76A5, 0xB088, 0x76A6, 0xB089,	0x76A7, 0xB08A, 0x76A8, 0xB08B, 0x76A9, 0xB08C, 0x76AA, 0xB08D,
+	0x76AB, 0xB08E, 0x76AC, 0xB08F, 0x76AD, 0xB090, 0x76AE, 0xC6A4,	0x76AF, 0xB091, 0x76B0, 0xB092, 0x76B1, 0xD6E5, 0x76B2, 0xF1E4,
+	0x76B3, 0xB093, 0x76B4, 0xF1E5, 0x76B5, 0xB094, 0x76B6, 0xB095,	0x76B7, 0xB096, 0x76B8, 0xB097, 0x76B9, 0xB098, 0x76BA, 0xB099,
+	0x76BB, 0xB09A, 0x76BC, 0xB09B, 0x76BD, 0xB09C, 0x76BE, 0xB09D,	0x76BF, 0xC3F3, 0x76C0, 0xB09E, 0x76C1, 0xB09F, 0x76C2, 0xD3DB,
+	0x76C3, 0xB0A0, 0x76C4, 0xB140, 0x76C5, 0xD6D1, 0x76C6, 0xC5E8,	0x76C7, 0xB141, 0x76C8, 0xD3AF, 0x76C9, 0xB142, 0x76CA, 0xD2E6,
+	0x76CB, 0xB143, 0x76CC, 0xB144, 0x76CD, 0xEEC1, 0x76CE, 0xB0BB,	0x76CF, 0xD5B5, 0x76D0, 0xD1CE, 0x76D1, 0xBCE0, 0x76D2, 0xBAD0,
+	0x76D3, 0xB145, 0x76D4, 0xBFF8, 0x76D5, 0xB146, 0x76D6, 0xB8C7,	0x76D7, 0xB5C1, 0x76D8, 0xC5CC, 0x76D9, 0xB147, 0x76DA, 0xB148,
+	0x76DB, 0xCAA2, 0x76DC, 0xB149, 0x76DD, 0xB14A, 0x76DE, 0xB14B,	0x76DF, 0xC3CB, 0x76E0, 0xB14C, 0x76E1, 0xB14D, 0x76E2, 0xB14E,
+	0x76E3, 0xB14F, 0x76E4, 0xB150, 0x76E5, 0xEEC2, 0x76E6, 0xB151,	0x76E7, 0xB152, 0x76E8, 0xB153, 0x76E9, 0xB154, 0x76EA, 0xB155,
+	0x76EB, 0xB156, 0x76EC, 0xB157, 0x76ED, 0xB158, 0x76EE, 0xC4BF,	0x76EF, 0xB6A2, 0x76F0, 0xB159, 0x76F1, 0xEDEC, 0x76F2, 0xC3A4,
+	0x76F3, 0xB15A, 0x76F4, 0xD6B1, 0x76F5, 0xB15B, 0x76F6, 0xB15C,	0x76F7, 0xB15D, 0x76F8, 0xCFE0, 0x76F9, 0xEDEF, 0x76FA, 0xB15E,
+	0x76FB, 0xB15F, 0x76FC, 0xC5CE, 0x76FD, 0xB160, 0x76FE, 0xB6DC,	0x76FF, 0xB161, 0x7700, 0xB162, 0x7701, 0xCAA1, 0x7702, 0xB163,
+	0x7703, 0xB164, 0x7704, 0xEDED, 0x7705, 0xB165, 0x7706, 0xB166,	0x7707, 0xEDF0, 0x7708, 0xEDF1, 0x7709, 0xC3BC, 0x770A, 0xB167,
+	0x770B, 0xBFB4, 0x770C, 0xB168, 0x770D, 0xEDEE, 0x770E, 0xB169,	0x770F, 0xB16A, 0x7710, 0xB16B, 0x7711, 0xB16C, 0x7712, 0xB16D,
+	0x7713, 0xB16E, 0x7714, 0xB16F, 0x7715, 0xB170, 0x7716, 0xB171,	0x7717, 0xB172, 0x7718, 0xB173, 0x7719, 0xEDF4, 0x771A, 0xEDF2,
+	0x771B, 0xB174, 0x771C, 0xB175, 0x771D, 0xB176, 0x771E, 0xB177,	0x771F, 0xD5E6, 0x7720, 0xC3DF, 0x7721, 0xB178, 0x7722, 0xEDF3,
+	0x7723, 0xB179, 0x7724, 0xB17A, 0x7725, 0xB17B, 0x7726, 0xEDF6,	0x7727, 0xB17C, 0x7728, 0xD5A3, 0x7729, 0xD1A3, 0x772A, 0xB17D,
+	0x772B, 0xB17E, 0x772C, 0xB180, 0x772D, 0xEDF5, 0x772E, 0xB181,	0x772F, 0xC3D0, 0x7730, 0xB182, 0x7731, 0xB183, 0x7732, 0xB184,
+	0x7733, 0xB185, 0x7734, 0xB186, 0x7735, 0xEDF7, 0x7736, 0xBFF4,	0x7737, 0xBEEC, 0x7738, 0xEDF8, 0x7739, 0xB187, 0x773A, 0xCCF7,
+	0x773B, 0xB188, 0x773C, 0xD1DB, 0x773D, 0xB189, 0x773E, 0xB18A,	0x773F, 0xB18B, 0x7740, 0xD7C5, 0x7741, 0xD5F6, 0x7742, 0xB18C,
+	0x7743, 0xEDFC, 0x7744, 0xB18D, 0x7745, 0xB18E, 0x7746, 0xB18F,	0x7747, 0xEDFB, 0x7748, 0xB190, 0x7749, 0xB191, 0x774A, 0xB192,
+	0x774B, 0xB193, 0x774C, 0xB194, 0x774D, 0xB195, 0x774E, 0xB196,	0x774F, 0xB197, 0x7750, 0xEDF9, 0x7751, 0xEDFA, 0x7752, 0xB198,
+	0x7753, 0xB199, 0x7754, 0xB19A, 0x7755, 0xB19B, 0x7756, 0xB19C,	0x7757, 0xB19D, 0x7758, 0xB19E, 0x7759, 0xB19F, 0x775A, 0xEDFD,
+	0x775B, 0xBEA6, 0x775C, 0xB1A0, 0x775D, 0xB240, 0x775E, 0xB241,	0x775F, 0xB242, 0x7760, 0xB243, 0x7761, 0xCBAF, 0x7762, 0xEEA1,
+	0x7763, 0xB6BD, 0x7764, 0xB244, 0x7765, 0xEEA2, 0x7766, 0xC4C0,	0x7767, 0xB245, 0x7768, 0xEDFE, 0x7769, 0xB246, 0x776A, 0xB247,
+	0x776B, 0xBDDE, 0x776C, 0xB2C7, 0x776D, 0xB248, 0x776E, 0xB249,	0x776F, 0xB24A, 0x7770, 0xB24B, 0x7771, 0xB24C, 0x7772, 0xB24D,
+	0x7773, 0xB24E, 0x7774, 0xB24F, 0x7775, 0xB250, 0x7776, 0xB251,	0x7777, 0xB252, 0x7778, 0xB253, 0x7779, 0xB6C3, 0x777A, 0xB254,
+	0x777B, 0xB255, 0x777C, 0xB256, 0x777D, 0xEEA5, 0x777E, 0xD8BA,	0x777F, 0xEEA3, 0x7780, 0xEEA6, 0x7781, 0xB257, 0x7782, 0xB258,
+	0x7783, 0xB259, 0x7784, 0xC3E9, 0x7785, 0xB3F2, 0x7786, 0xB25A,	0x7787, 0xB25B, 0x7788, 0xB25C, 0x7789, 0xB25D, 0x778A, 0xB25E,
+	0x778B, 0xB25F, 0x778C, 0xEEA7, 0x778D, 0xEEA4, 0x778E, 0xCFB9,	0x778F, 0xB260, 0x7790, 0xB261, 0x7791, 0xEEA8, 0x7792, 0xC2F7,
+	0x7793, 0xB262, 0x7794, 0xB263, 0x7795, 0xB264, 0x7796, 0xB265,	0x7797, 0xB266, 0x7798, 0xB267, 0x7799, 0xB268, 0x779A, 0xB269,
+	0x779B, 0xB26A, 0x779C, 0xB26B, 0x779D, 0xB26C, 0x779E, 0xB26D,	0x779F, 0xEEA9, 0x77A0, 0xEEAA, 0x77A1, 0xB26E, 0x77A2, 0xDEAB,
+	0x77A3, 0xB26F, 0x77A4, 0xB270, 0x77A5, 0xC6B3, 0x77A6, 0xB271,	0x77A7, 0xC7C6, 0x77A8, 0xB272, 0x77A9, 0xD6F5, 0x77AA, 0xB5C9,
+	0x77AB, 0xB273, 0x77AC, 0xCBB2, 0x77AD, 0xB274, 0x77AE, 0xB275,	0x77AF, 0xB276, 0x77B0, 0xEEAB, 0x77B1, 0xB277, 0x77B2, 0xB278,
+	0x77B3, 0xCDAB, 0x77B4, 0xB279, 0x77B5, 0xEEAC, 0x77B6, 0xB27A,	0x77B7, 0xB27B, 0x77B8, 0xB27C, 0x77B9, 0xB27D, 0x77BA, 0xB27E,
+	0x77BB, 0xD5B0, 0x77BC, 0xB280, 0x77BD, 0xEEAD, 0x77BE, 0xB281,	0x77BF, 0xF6C4, 0x77C0, 0xB282, 0x77C1, 0xB283, 0x77C2, 0xB284,
+	0x77C3, 0xB285, 0x77C4, 0xB286, 0x77C5, 0xB287, 0x77C6, 0xB288,	0x77C7, 0xB289, 0x77C8, 0xB28A, 0x77C9, 0xB28B, 0x77CA, 0xB28C,
+	0x77CB, 0xB28D, 0x77CC, 0xB28E, 0x77CD, 0xDBC7, 0x77CE, 0xB28F,	0x77CF, 0xB290, 0x77D0, 0xB291, 0x77D1, 0xB292, 0x77D2, 0xB293,
+	0x77D3, 0xB294, 0x77D4, 0xB295, 0x77D5, 0xB296, 0x77D6, 0xB297,	0x77D7, 0xB4A3, 0x77D8, 0xB298, 0x77D9, 0xB299, 0x77DA, 0xB29A,
+	0x77DB, 0xC3AC, 0x77DC, 0xF1E6, 0x77DD, 0xB29B, 0x77DE, 0xB29C,	0x77DF, 0xB29D, 0x77E0, 0xB29E, 0x77E1, 0xB29F, 0x77E2, 0xCAB8,
+	0x77E3, 0xD2D3, 0x77E4, 0xB2A0, 0x77E5, 0xD6AA, 0x77E6, 0xB340,	0x77E7, 0xEFF2, 0x77E8, 0xB341, 0x77E9, 0xBED8, 0x77EA, 0xB342,
+	0x77EB, 0xBDC3, 0x77EC, 0xEFF3, 0x77ED, 0xB6CC, 0x77EE, 0xB0AB,	0x77EF, 0xB343, 0x77F0, 0xB344, 0x77F1, 0xB345, 0x77F2, 0xB346,
+	0x77F3, 0xCAAF, 0x77F4, 0xB347, 0x77F5, 0xB348, 0x77F6, 0xEDB6,	0x77F7, 0xB349, 0x77F8, 0xEDB7, 0x77F9, 0xB34A, 0x77FA, 0xB34B,
+	0x77FB, 0xB34C, 0x77FC, 0xB34D, 0x77FD, 0xCEF9, 0x77FE, 0xB7AF,	0x77FF, 0xBFF3, 0x7800, 0xEDB8, 0x7801, 0xC2EB, 0x7802, 0xC9B0,
+	0x7803, 0xB34E, 0x7804, 0xB34F, 0x7805, 0xB350, 0x7806, 0xB351,	0x7807, 0xB352, 0x7808, 0xB353, 0x7809, 0xEDB9, 0x780A, 0xB354,
+	0x780B, 0xB355, 0x780C, 0xC6F6, 0x780D, 0xBFB3, 0x780E, 0xB356,	0x780F, 0xB357, 0x7810, 0xB358, 0x7811, 0xEDBC, 0x7812, 0xC5F8,
+	0x7813, 0xB359, 0x7814, 0xD1D0, 0x7815, 0xB35A, 0x7816, 0xD7A9,	0x7817, 0xEDBA, 0x7818, 0xEDBB, 0x7819, 0xB35B, 0x781A, 0xD1E2,
+	0x781B, 0xB35C, 0x781C, 0xEDBF, 0x781D, 0xEDC0, 0x781E, 0xB35D,	0x781F, 0xEDC4, 0x7820, 0xB35E, 0x7821, 0xB35F, 0x7822, 0xB360,
+	0x7823, 0xEDC8, 0x7824, 0xB361, 0x7825, 0xEDC6, 0x7826, 0xEDCE,	0x7827, 0xD5E8, 0x7828, 0xB362, 0x7829, 0xEDC9, 0x782A, 0xB363,
+	0x782B, 0xB364, 0x782C, 0xEDC7, 0x782D, 0xEDBE, 0x782E, 0xB365,	0x782F, 0xB366, 0x7830, 0xC5E9, 0x7831, 0xB367, 0x7832, 0xB368,
+	0x7833, 0xB369, 0x7834, 0xC6C6, 0x7835, 0xB36A, 0x7836, 0xB36B,	0x7837, 0xC9E9, 0x7838, 0xD4D2, 0x7839, 0xEDC1, 0x783A, 0xEDC2,
+	0x783B, 0xEDC3, 0x783C, 0xEDC5, 0x783D, 0xB36C, 0x783E, 0xC0F9,	0x783F, 0xB36D, 0x7840, 0xB4A1, 0x7841, 0xB36E, 0x7842, 0xB36F,
+	0x7843, 0xB370, 0x7844, 0xB371, 0x7845, 0xB9E8, 0x7846, 0xB372,	0x7847, 0xEDD0, 0x7848, 0xB373, 0x7849, 0xB374, 0x784A, 0xB375,
+	0x784B, 0xB376, 0x784C, 0xEDD1, 0x784D, 0xB377, 0x784E, 0xEDCA,	0x784F, 0xB378, 0x7850, 0xEDCF, 0x7851, 0xB379, 0x7852, 0xCEF8,
+	0x7853, 0xB37A, 0x7854, 0xB37B, 0x7855, 0xCBB6, 0x7856, 0xEDCC,	0x7857, 0xEDCD, 0x7858, 0xB37C, 0x7859, 0xB37D, 0x785A, 0xB37E,
+	0x785B, 0xB380, 0x785C, 0xB381, 0x785D, 0xCFF5, 0x785E, 0xB382,	0x785F, 0xB383, 0x7860, 0xB384, 0x7861, 0xB385, 0x7862, 0xB386,
+	0x7863, 0xB387, 0x7864, 0xB388, 0x7865, 0xB389, 0x7866, 0xB38A,	0x7867, 0xB38B, 0x7868, 0xB38C, 0x7869, 0xB38D, 0x786A, 0xEDD2,
+	0x786B, 0xC1F2, 0x786C, 0xD3B2, 0x786D, 0xEDCB, 0x786E, 0xC8B7,	0x786F, 0xB38E, 0x7870, 0xB38F, 0x7871, 0xB390, 0x7872, 0xB391,
+	0x7873, 0xB392, 0x7874, 0xB393, 0x7875, 0xB394, 0x7876, 0xB395,	0x7877, 0xBCEF, 0x7878, 0xB396, 0x7879, 0xB397, 0x787A, 0xB398,
+	0x787B, 0xB399, 0x787C, 0xC5F0, 0x787D, 0xB39A, 0x787E, 0xB39B,	0x787F, 0xB39C, 0x7880, 0xB39D, 0x7881, 0xB39E, 0x7882, 0xB39F,
+	0x7883, 0xB3A0, 0x7884, 0xB440, 0x7885, 0xB441, 0x7886, 0xB442,	0x7887, 0xEDD6, 0x7888, 0xB443, 0x7889, 0xB5EF, 0x788A, 0xB444,
+	0x788B, 0xB445, 0x788C, 0xC2B5, 0x788D, 0xB0AD, 0x788E, 0xCBE9,	0x788F, 0xB446, 0x7890, 0xB447, 0x7891, 0xB1AE, 0x7892, 0xB448,
+	0x7893, 0xEDD4, 0x7894, 0xB449, 0x7895, 0xB44A, 0x7896, 0xB44B,	0x7897, 0xCDEB, 0x7898, 0xB5E2, 0x7899, 0xB44C, 0x789A, 0xEDD5,
+	0x789B, 0xEDD3, 0x789C, 0xEDD7, 0x789D, 0xB44D, 0x789E, 0xB44E,	0x789F, 0xB5FA, 0x78A0, 0xB44F, 0x78A1, 0xEDD8, 0x78A2, 0xB450,
+	0x78A3, 0xEDD9, 0x78A4, 0xB451, 0x78A5, 0xEDDC, 0x78A6, 0xB452,	0x78A7, 0xB1CC, 0x78A8, 0xB453, 0x78A9, 0xB454, 0x78AA, 0xB455,
+	0x78AB, 0xB456, 0x78AC, 0xB457, 0x78AD, 0xB458, 0x78AE, 0xB459,	0x78AF, 0xB45A, 0x78B0, 0xC5F6, 0x78B1, 0xBCEE, 0x78B2, 0xEDDA,
+	0x78B3, 0xCCBC, 0x78B4, 0xB2EA, 0x78B5, 0xB45B, 0x78B6, 0xB45C,	0x78B7, 0xB45D, 0x78B8, 0xB45E, 0x78B9, 0xEDDB, 0x78BA, 0xB45F,
+	0x78BB, 0xB460, 0x78BC, 0xB461, 0x78BD, 0xB462, 0x78BE, 0xC4EB,	0x78BF, 0xB463, 0x78C0, 0xB464, 0x78C1, 0xB4C5, 0x78C2, 0xB465,
+	0x78C3, 0xB466, 0x78C4, 0xB467, 0x78C5, 0xB0F5, 0x78C6, 0xB468,	0x78C7, 0xB469, 0x78C8, 0xB46A, 0x78C9, 0xEDDF, 0x78CA, 0xC0DA,
+	0x78CB, 0xB4E8, 0x78CC, 0xB46B, 0x78CD, 0xB46C, 0x78CE, 0xB46D,	0x78CF, 0xB46E, 0x78D0, 0xC5CD, 0x78D1, 0xB46F, 0x78D2, 0xB470,
+	0x78D3, 0xB471, 0x78D4, 0xEDDD, 0x78D5, 0xBFC4, 0x78D6, 0xB472,	0x78D7, 0xB473, 0x78D8, 0xB474, 0x78D9, 0xEDDE, 0x78DA, 0xB475,
+	0x78DB, 0xB476, 0x78DC, 0xB477, 0x78DD, 0xB478, 0x78DE, 0xB479,	0x78DF, 0xB47A, 0x78E0, 0xB47B, 0x78E1, 0xB47C, 0x78E2, 0xB47D,
+	0x78E3, 0xB47E, 0x78E4, 0xB480, 0x78E5, 0xB481, 0x78E6, 0xB482,	0x78E7, 0xB483, 0x78E8, 0xC4A5, 0x78E9, 0xB484, 0x78EA, 0xB485,
+	0x78EB, 0xB486, 0x78EC, 0xEDE0, 0x78ED, 0xB487, 0x78EE, 0xB488,	0x78EF, 0xB489, 0x78F0, 0xB48A, 0x78F1, 0xB48B, 0x78F2, 0xEDE1,
+	0x78F3, 0xB48C, 0x78F4, 0xEDE3, 0x78F5, 0xB48D, 0x78F6, 0xB48E,	0x78F7, 0xC1D7, 0x78F8, 0xB48F, 0x78F9, 0xB490, 0x78FA, 0xBBC7,
+	0x78FB, 0xB491, 0x78FC, 0xB492, 0x78FD, 0xB493, 0x78FE, 0xB494,	0x78FF, 0xB495, 0x7900, 0xB496, 0x7901, 0xBDB8, 0x7902, 0xB497,
+	0x7903, 0xB498, 0x7904, 0xB499, 0x7905, 0xEDE2, 0x7906, 0xB49A,	0x7907, 0xB49B, 0x7908, 0xB49C, 0x7909, 0xB49D, 0x790A, 0xB49E,
+	0x790B, 0xB49F, 0x790C, 0xB4A0, 0x790D, 0xB540, 0x790E, 0xB541,	0x790F, 0xB542, 0x7910, 0xB543, 0x7911, 0xB544, 0x7912, 0xB545,
+	0x7913, 0xEDE4, 0x7914, 0xB546, 0x7915, 0xB547, 0x7916, 0xB548,	0x7917, 0xB549, 0x7918, 0xB54A, 0x7919, 0xB54B, 0x791A, 0xB54C,
+	0x791B, 0xB54D, 0x791C, 0xB54E, 0x791D, 0xB54F, 0x791E, 0xEDE6,	0x791F, 0xB550, 0x7920, 0xB551, 0x7921, 0xB552, 0x7922, 0xB553,
+	0x7923, 0xB554, 0x7924, 0xEDE5, 0x7925, 0xB555, 0x7926, 0xB556,	0x7927, 0xB557, 0x7928, 0xB558, 0x7929, 0xB559, 0x792A, 0xB55A,
+	0x792B, 0xB55B, 0x792C, 0xB55C, 0x792D, 0xB55D, 0x792E, 0xB55E,	0x792F, 0xB55F, 0x7930, 0xB560, 0x7931, 0xB561, 0x7932, 0xB562,
+	0x7933, 0xB563, 0x7934, 0xEDE7, 0x7935, 0xB564, 0x7936, 0xB565,	0x7937, 0xB566, 0x7938, 0xB567, 0x7939, 0xB568, 0x793A, 0xCABE,
+	0x793B, 0xECEA, 0x793C, 0xC0F1, 0x793D, 0xB569, 0x793E, 0xC9E7,	0x793F, 0xB56A, 0x7940, 0xECEB, 0x7941, 0xC6EE, 0x7942, 0xB56B,
+	0x7943, 0xB56C, 0x7944, 0xB56D, 0x7945, 0xB56E, 0x7946, 0xECEC,	0x7947, 0xB56F, 0x7948, 0xC6ED, 0x7949, 0xECED, 0x794A, 0xB570,
+	0x794B, 0xB571, 0x794C, 0xB572, 0x794D, 0xB573, 0x794E, 0xB574,	0x794F, 0xB575, 0x7950, 0xB576, 0x7951, 0xB577, 0x7952, 0xB578,
+	0x7953, 0xECF0, 0x7954, 0xB579, 0x7955, 0xB57A, 0x7956, 0xD7E6,	0x7957, 0xECF3, 0x7958, 0xB57B, 0x7959, 0xB57C, 0x795A, 0xECF1,
+	0x795B, 0xECEE, 0x795C, 0xECEF, 0x795D, 0xD7A3, 0x795E, 0xC9F1,	0x795F, 0xCBEE, 0x7960, 0xECF4, 0x7961, 0xB57D, 0x7962, 0xECF2,
+	0x7963, 0xB57E, 0x7964, 0xB580, 0x7965, 0xCFE9, 0x7966, 0xB581,	0x7967, 0xECF6, 0x7968, 0xC6B1, 0x7969, 0xB582, 0x796A, 0xB583,
+	0x796B, 0xB584, 0x796C, 0xB585, 0x796D, 0xBCC0, 0x796E, 0xB586,	0x796F, 0xECF5, 0x7970, 0xB587, 0x7971, 0xB588, 0x7972, 0xB589,
+	0x7973, 0xB58A, 0x7974, 0xB58B, 0x7975, 0xB58C, 0x7976, 0xB58D,	0x7977, 0xB5BB, 0x7978, 0xBBF6, 0x7979, 0xB58E, 0x797A, 0xECF7,
+	0x797B, 0xB58F, 0x797C, 0xB590, 0x797D, 0xB591, 0x797E, 0xB592,	0x797F, 0xB593, 0x7980, 0xD9F7, 0x7981, 0xBDFB, 0x7982, 0xB594,
+	0x7983, 0xB595, 0x7984, 0xC2BB, 0x7985, 0xECF8, 0x7986, 0xB596,	0x7987, 0xB597, 0x7988, 0xB598, 0x7989, 0xB599, 0x798A, 0xECF9,
+	0x798B, 0xB59A, 0x798C, 0xB59B, 0x798D, 0xB59C, 0x798E, 0xB59D,	0x798F, 0xB8A3, 0x7990, 0xB59E, 0x7991, 0xB59F, 0x7992, 0xB5A0,
+	0x7993, 0xB640, 0x7994, 0xB641, 0x7995, 0xB642, 0x7996, 0xB643,	0x7997, 0xB644, 0x7998, 0xB645, 0x7999, 0xB646, 0x799A, 0xECFA,
+	0x799B, 0xB647, 0x799C, 0xB648, 0x799D, 0xB649, 0x799E, 0xB64A,	0x799F, 0xB64B, 0x79A0, 0xB64C, 0x79A1, 0xB64D, 0x79A2, 0xB64E,
+	0x79A3, 0xB64F, 0x79A4, 0xB650, 0x79A5, 0xB651, 0x79A6, 0xB652,	0x79A7, 0xECFB, 0x79A8, 0xB653, 0x79A9, 0xB654, 0x79AA, 0xB655,
+	0x79AB, 0xB656, 0x79AC, 0xB657, 0x79AD, 0xB658, 0x79AE, 0xB659,	0x79AF, 0xB65A, 0x79B0, 0xB65B, 0x79B1, 0xB65C, 0x79B2, 0xB65D,
+	0x79B3, 0xECFC, 0x79B4, 0xB65E, 0x79B5, 0xB65F, 0x79B6, 0xB660,	0x79B7, 0xB661, 0x79B8, 0xB662, 0x79B9, 0xD3ED, 0x79BA, 0xD8AE,
+	0x79BB, 0xC0EB, 0x79BC, 0xB663, 0x79BD, 0xC7DD, 0x79BE, 0xBACC,	0x79BF, 0xB664, 0x79C0, 0xD0E3, 0x79C1, 0xCBBD, 0x79C2, 0xB665,
+	0x79C3, 0xCDBA, 0x79C4, 0xB666, 0x79C5, 0xB667, 0x79C6, 0xB8D1,	0x79C7, 0xB668, 0x79C8, 0xB669, 0x79C9, 0xB1FC, 0x79CA, 0xB66A,
+	0x79CB, 0xC7EF, 0x79CC, 0xB66B, 0x79CD, 0xD6D6, 0x79CE, 0xB66C,	0x79CF, 0xB66D, 0x79D0, 0xB66E, 0x79D1, 0xBFC6, 0x79D2, 0xC3EB,
+	0x79D3, 0xB66F, 0x79D4, 0xB670, 0x79D5, 0xEFF5, 0x79D6, 0xB671,	0x79D7, 0xB672, 0x79D8, 0xC3D8, 0x79D9, 0xB673, 0x79DA, 0xB674,
+	0x79DB, 0xB675, 0x79DC, 0xB676, 0x79DD, 0xB677, 0x79DE, 0xB678,	0x79DF, 0xD7E2, 0x79E0, 0xB679, 0x79E1, 0xB67A, 0x79E2, 0xB67B,
+	0x79E3, 0xEFF7, 0x79E4, 0xB3D3, 0x79E5, 0xB67C, 0x79E6, 0xC7D8,	0x79E7, 0xD1ED, 0x79E8, 0xB67D, 0x79E9, 0xD6C8, 0x79EA, 0xB67E,
+	0x79EB, 0xEFF8, 0x79EC, 0xB680, 0x79ED, 0xEFF6, 0x79EE, 0xB681,	0x79EF, 0xBBFD, 0x79F0, 0xB3C6, 0x79F1, 0xB682, 0x79F2, 0xB683,
+	0x79F3, 0xB684, 0x79F4, 0xB685, 0x79F5, 0xB686, 0x79F6, 0xB687,	0x79F7, 0xB688, 0x79F8, 0xBDD5, 0x79F9, 0xB689, 0x79FA, 0xB68A,
+	0x79FB, 0xD2C6, 0x79FC, 0xB68B, 0x79FD, 0xBBE0, 0x79FE, 0xB68C,	0x79FF, 0xB68D, 0x7A00, 0xCFA1, 0x7A01, 0xB68E, 0x7A02, 0xEFFC,
+	0x7A03, 0xEFFB, 0x7A04, 0xB68F, 0x7A05, 0xB690, 0x7A06, 0xEFF9,	0x7A07, 0xB691, 0x7A08, 0xB692, 0x7A09, 0xB693, 0x7A0A, 0xB694,
+	0x7A0B, 0xB3CC, 0x7A0C, 0xB695, 0x7A0D, 0xC9D4, 0x7A0E, 0xCBB0,	0x7A0F, 0xB696, 0x7A10, 0xB697, 0x7A11, 0xB698, 0x7A12, 0xB699,
+	0x7A13, 0xB69A, 0x7A14, 0xEFFE, 0x7A15, 0xB69B, 0x7A16, 0xB69C,	0x7A17, 0xB0DE, 0x7A18, 0xB69D, 0x7A19, 0xB69E, 0x7A1A, 0xD6C9,
+	0x7A1B, 0xB69F, 0x7A1C, 0xB6A0, 0x7A1D, 0xB740, 0x7A1E, 0xEFFD,	0x7A1F, 0xB741, 0x7A20, 0xB3ED, 0x7A21, 0xB742, 0x7A22, 0xB743,
+	0x7A23, 0xF6D5, 0x7A24, 0xB744, 0x7A25, 0xB745, 0x7A26, 0xB746,	0x7A27, 0xB747, 0x7A28, 0xB748, 0x7A29, 0xB749, 0x7A2A, 0xB74A,
+	0x7A2B, 0xB74B, 0x7A2C, 0xB74C, 0x7A2D, 0xB74D, 0x7A2E, 0xB74E,	0x7A2F, 0xB74F, 0x7A30, 0xB750, 0x7A31, 0xB751, 0x7A32, 0xB752,
+	0x7A33, 0xCEC8, 0x7A34, 0xB753, 0x7A35, 0xB754, 0x7A36, 0xB755,	0x7A37, 0xF0A2, 0x7A38, 0xB756, 0x7A39, 0xF0A1, 0x7A3A, 0xB757,
+	0x7A3B, 0xB5BE, 0x7A3C, 0xBCDA, 0x7A3D, 0xBBFC, 0x7A3E, 0xB758,	0x7A3F, 0xB8E5, 0x7A40, 0xB759, 0x7A41, 0xB75A, 0x7A42, 0xB75B,
+	0x7A43, 0xB75C, 0x7A44, 0xB75D, 0x7A45, 0xB75E, 0x7A46, 0xC4C2,	0x7A47, 0xB75F, 0x7A48, 0xB760, 0x7A49, 0xB761, 0x7A4A, 0xB762,
+	0x7A4B, 0xB763, 0x7A4C, 0xB764, 0x7A4D, 0xB765, 0x7A4E, 0xB766,	0x7A4F, 0xB767, 0x7A50, 0xB768, 0x7A51, 0xF0A3, 0x7A52, 0xB769,
+	0x7A53, 0xB76A, 0x7A54, 0xB76B, 0x7A55, 0xB76C, 0x7A56, 0xB76D,	0x7A57, 0xCBEB, 0x7A58, 0xB76E, 0x7A59, 0xB76F, 0x7A5A, 0xB770,
+	0x7A5B, 0xB771, 0x7A5C, 0xB772, 0x7A5D, 0xB773, 0x7A5E, 0xB774,	0x7A5F, 0xB775, 0x7A60, 0xB776, 0x7A61, 0xB777, 0x7A62, 0xB778,
+	0x7A63, 0xB779, 0x7A64, 0xB77A, 0x7A65, 0xB77B, 0x7A66, 0xB77C,	0x7A67, 0xB77D, 0x7A68, 0xB77E, 0x7A69, 0xB780, 0x7A6A, 0xB781,
+	0x7A6B, 0xB782, 0x7A6C, 0xB783, 0x7A6D, 0xB784, 0x7A6E, 0xB785,	0x7A6F, 0xB786, 0x7A70, 0xF0A6, 0x7A71, 0xB787, 0x7A72, 0xB788,
+	0x7A73, 0xB789, 0x7A74, 0xD1A8, 0x7A75, 0xB78A, 0x7A76, 0xBEBF,	0x7A77, 0xC7EE, 0x7A78, 0xF1B6, 0x7A79, 0xF1B7, 0x7A7A, 0xBFD5,
+	0x7A7B, 0xB78B, 0x7A7C, 0xB78C, 0x7A7D, 0xB78D, 0x7A7E, 0xB78E,	0x7A7F, 0xB4A9, 0x7A80, 0xF1B8, 0x7A81, 0xCDBB, 0x7A82, 0xB78F,
+	0x7A83, 0xC7D4, 0x7A84, 0xD5AD, 0x7A85, 0xB790, 0x7A86, 0xF1B9,	0x7A87, 0xB791, 0x7A88, 0xF1BA, 0x7A89, 0xB792, 0x7A8A, 0xB793,
+	0x7A8B, 0xB794, 0x7A8C, 0xB795, 0x7A8D, 0xC7CF, 0x7A8E, 0xB796,	0x7A8F, 0xB797, 0x7A90, 0xB798, 0x7A91, 0xD2A4, 0x7A92, 0xD6CF,
+	0x7A93, 0xB799, 0x7A94, 0xB79A, 0x7A95, 0xF1BB, 0x7A96, 0xBDD1,	0x7A97, 0xB4B0, 0x7A98, 0xBEBD, 0x7A99, 0xB79B, 0x7A9A, 0xB79C,
+	0x7A9B, 0xB79D, 0x7A9C, 0xB4DC, 0x7A9D, 0xCED1, 0x7A9E, 0xB79E,	0x7A9F, 0xBFDF, 0x7AA0, 0xF1BD, 0x7AA1, 0xB79F, 0x7AA2, 0xB7A0,
+	0x7AA3, 0xB840, 0x7AA4, 0xB841, 0x7AA5, 0xBFFA, 0x7AA6, 0xF1BC,	0x7AA7, 0xB842, 0x7AA8, 0xF1BF, 0x7AA9, 0xB843, 0x7AAA, 0xB844,
+	0x7AAB, 0xB845, 0x7AAC, 0xF1BE, 0x7AAD, 0xF1C0, 0x7AAE, 0xB846,	0x7AAF, 0xB847, 0x7AB0, 0xB848, 0x7AB1, 0xB849, 0x7AB2, 0xB84A,
+	0x7AB3, 0xF1C1, 0x7AB4, 0xB84B, 0x7AB5, 0xB84C, 0x7AB6, 0xB84D,	0x7AB7, 0xB84E, 0x7AB8, 0xB84F, 0x7AB9, 0xB850, 0x7ABA, 0xB851,
+	0x7ABB, 0xB852, 0x7ABC, 0xB853, 0x7ABD, 0xB854, 0x7ABE, 0xB855,	0x7ABF, 0xC1FE, 0x7AC0, 0xB856, 0x7AC1, 0xB857, 0x7AC2, 0xB858,
+	0x7AC3, 0xB859, 0x7AC4, 0xB85A, 0x7AC5, 0xB85B, 0x7AC6, 0xB85C,	0x7AC7, 0xB85D, 0x7AC8, 0xB85E, 0x7AC9, 0xB85F, 0x7ACA, 0xB860,
+	0x7ACB, 0xC1A2, 0x7ACC, 0xB861, 0x7ACD, 0xB862, 0x7ACE, 0xB863,	0x7ACF, 0xB864, 0x7AD0, 0xB865, 0x7AD1, 0xB866, 0x7AD2, 0xB867,
+	0x7AD3, 0xB868, 0x7AD4, 0xB869, 0x7AD5, 0xB86A, 0x7AD6, 0xCAFA,	0x7AD7, 0xB86B, 0x7AD8, 0xB86C, 0x7AD9, 0xD5BE, 0x7ADA, 0xB86D,
+	0x7ADB, 0xB86E, 0x7ADC, 0xB86F, 0x7ADD, 0xB870, 0x7ADE, 0xBEBA,	0x7ADF, 0xBEB9, 0x7AE0, 0xD5C2, 0x7AE1, 0xB871, 0x7AE2, 0xB872,
+	0x7AE3, 0xBFA2, 0x7AE4, 0xB873, 0x7AE5, 0xCDAF, 0x7AE6, 0xF1B5,	0x7AE7, 0xB874, 0x7AE8, 0xB875, 0x7AE9, 0xB876, 0x7AEA, 0xB877,
+	0x7AEB, 0xB878, 0x7AEC, 0xB879, 0x7AED, 0xBDDF, 0x7AEE, 0xB87A,	0x7AEF, 0xB6CB, 0x7AF0, 0xB87B, 0x7AF1, 0xB87C, 0x7AF2, 0xB87D,
+	0x7AF3, 0xB87E, 0x7AF4, 0xB880, 0x7AF5, 0xB881, 0x7AF6, 0xB882,	0x7AF7, 0xB883, 0x7AF8, 0xB884, 0x7AF9, 0xD6F1, 0x7AFA, 0xF3C3,
+	0x7AFB, 0xB885, 0x7AFC, 0xB886, 0x7AFD, 0xF3C4, 0x7AFE, 0xB887,	0x7AFF, 0xB8CD, 0x7B00, 0xB888, 0x7B01, 0xB889, 0x7B02, 0xB88A,
+	0x7B03, 0xF3C6, 0x7B04, 0xF3C7, 0x7B05, 0xB88B, 0x7B06, 0xB0CA,	0x7B07, 0xB88C, 0x7B08, 0xF3C5, 0x7B09, 0xB88D, 0x7B0A, 0xF3C9,
+	0x7B0B, 0xCBF1, 0x7B0C, 0xB88E, 0x7B0D, 0xB88F, 0x7B0E, 0xB890,	0x7B0F, 0xF3CB, 0x7B10, 0xB891, 0x7B11, 0xD0A6, 0x7B12, 0xB892,
+	0x7B13, 0xB893, 0x7B14, 0xB1CA, 0x7B15, 0xF3C8, 0x7B16, 0xB894,	0x7B17, 0xB895, 0x7B18, 0xB896, 0x7B19, 0xF3CF, 0x7B1A, 0xB897,
+	0x7B1B, 0xB5D1, 0x7B1C, 0xB898, 0x7B1D, 0xB899, 0x7B1E, 0xF3D7,	0x7B1F, 0xB89A, 0x7B20, 0xF3D2, 0x7B21, 0xB89B, 0x7B22, 0xB89C,
+	0x7B23, 0xB89D, 0x7B24, 0xF3D4, 0x7B25, 0xF3D3, 0x7B26, 0xB7FB,	0x7B27, 0xB89E, 0x7B28, 0xB1BF, 0x7B29, 0xB89F, 0x7B2A, 0xF3CE,
+	0x7B2B, 0xF3CA, 0x7B2C, 0xB5DA, 0x7B2D, 0xB8A0, 0x7B2E, 0xF3D0,	0x7B2F, 0xB940, 0x7B30, 0xB941, 0x7B31, 0xF3D1, 0x7B32, 0xB942,
+	0x7B33, 0xF3D5, 0x7B34, 0xB943, 0x7B35, 0xB944, 0x7B36, 0xB945,	0x7B37, 0xB946, 0x7B38, 0xF3CD, 0x7B39, 0xB947, 0x7B3A, 0xBCE3,
+	0x7B3B, 0xB948, 0x7B3C, 0xC1FD, 0x7B3D, 0xB949, 0x7B3E, 0xF3D6,	0x7B3F, 0xB94A, 0x7B40, 0xB94B, 0x7B41, 0xB94C, 0x7B42, 0xB94D,
+	0x7B43, 0xB94E, 0x7B44, 0xB94F, 0x7B45, 0xF3DA, 0x7B46, 0xB950,	0x7B47, 0xF3CC, 0x7B48, 0xB951, 0x7B49, 0xB5C8, 0x7B4A, 0xB952,
+	0x7B4B, 0xBDEE, 0x7B4C, 0xF3DC, 0x7B4D, 0xB953, 0x7B4E, 0xB954,	0x7B4F, 0xB7A4, 0x7B50, 0xBFF0, 0x7B51, 0xD6FE, 0x7B52, 0xCDB2,
+	0x7B53, 0xB955, 0x7B54, 0xB4F0, 0x7B55, 0xB956, 0x7B56, 0xB2DF,	0x7B57, 0xB957, 0x7B58, 0xF3D8, 0x7B59, 0xB958, 0x7B5A, 0xF3D9,
+	0x7B5B, 0xC9B8, 0x7B5C, 0xB959, 0x7B5D, 0xF3DD, 0x7B5E, 0xB95A,	0x7B5F, 0xB95B, 0x7B60, 0xF3DE, 0x7B61, 0xB95C, 0x7B62, 0xF3E1,
+	0x7B63, 0xB95D, 0x7B64, 0xB95E, 0x7B65, 0xB95F, 0x7B66, 0xB960,	0x7B67, 0xB961, 0x7B68, 0xB962, 0x7B69, 0xB963, 0x7B6A, 0xB964,
+	0x7B6B, 0xB965, 0x7B6C, 0xB966, 0x7B6D, 0xB967, 0x7B6E, 0xF3DF,	0x7B6F, 0xB968, 0x7B70, 0xB969, 0x7B71, 0xF3E3, 0x7B72, 0xF3E2,
+	0x7B73, 0xB96A, 0x7B74, 0xB96B, 0x7B75, 0xF3DB, 0x7B76, 0xB96C,	0x7B77, 0xBFEA, 0x7B78, 0xB96D, 0x7B79, 0xB3EF, 0x7B7A, 0xB96E,
+	0x7B7B, 0xF3E0, 0x7B7C, 0xB96F, 0x7B7D, 0xB970, 0x7B7E, 0xC7A9,	0x7B7F, 0xB971, 0x7B80, 0xBCF2, 0x7B81, 0xB972, 0x7B82, 0xB973,
+	0x7B83, 0xB974, 0x7B84, 0xB975, 0x7B85, 0xF3EB, 0x7B86, 0xB976,	0x7B87, 0xB977, 0x7B88, 0xB978, 0x7B89, 0xB979, 0x7B8A, 0xB97A,
+	0x7B8B, 0xB97B, 0x7B8C, 0xB97C, 0x7B8D, 0xB9BF, 0x7B8E, 0xB97D,	0x7B8F, 0xB97E, 0x7B90, 0xF3E4, 0x7B91, 0xB980, 0x7B92, 0xB981,
+	0x7B93, 0xB982, 0x7B94, 0xB2AD, 0x7B95, 0xBBFE, 0x7B96, 0xB983,	0x7B97, 0xCBE3, 0x7B98, 0xB984, 0x7B99, 0xB985, 0x7B9A, 0xB986,
+	0x7B9B, 0xB987, 0x7B9C, 0xF3ED, 0x7B9D, 0xF3E9, 0x7B9E, 0xB988,	0x7B9F, 0xB989, 0x7BA0, 0xB98A, 0x7BA1, 0xB9DC, 0x7BA2, 0xF3EE,
+	0x7BA3, 0xB98B, 0x7BA4, 0xB98C, 0x7BA5, 0xB98D, 0x7BA6, 0xF3E5,	0x7BA7, 0xF3E6, 0x7BA8, 0xF3EA, 0x7BA9, 0xC2E1, 0x7BAA, 0xF3EC,
+	0x7BAB, 0xF3EF, 0x7BAC, 0xF3E8, 0x7BAD, 0xBCFD, 0x7BAE, 0xB98E,	0x7BAF, 0xB98F, 0x7BB0, 0xB990, 0x7BB1, 0xCFE4, 0x7BB2, 0xB991,
+	0x7BB3, 0xB992, 0x7BB4, 0xF3F0, 0x7BB5, 0xB993, 0x7BB6, 0xB994,	0x7BB7, 0xB995, 0x7BB8, 0xF3E7, 0x7BB9, 0xB996, 0x7BBA, 0xB997,
+	0x7BBB, 0xB998, 0x7BBC, 0xB999, 0x7BBD, 0xB99A, 0x7BBE, 0xB99B,	0x7BBF, 0xB99C, 0x7BC0, 0xB99D, 0x7BC1, 0xF3F2, 0x7BC2, 0xB99E,
+	0x7BC3, 0xB99F, 0x7BC4, 0xB9A0, 0x7BC5, 0xBA40, 0x7BC6, 0xD7AD,	0x7BC7, 0xC6AA, 0x7BC8, 0xBA41, 0x7BC9, 0xBA42, 0x7BCA, 0xBA43,
+	0x7BCB, 0xBA44, 0x7BCC, 0xF3F3, 0x7BCD, 0xBA45, 0x7BCE, 0xBA46,	0x7BCF, 0xBA47, 0x7BD0, 0xBA48, 0x7BD1, 0xF3F1, 0x7BD2, 0xBA49,
+	0x7BD3, 0xC2A8, 0x7BD4, 0xBA4A, 0x7BD5, 0xBA4B, 0x7BD6, 0xBA4C,	0x7BD7, 0xBA4D, 0x7BD8, 0xBA4E, 0x7BD9, 0xB8DD, 0x7BDA, 0xF3F5,
+	0x7BDB, 0xBA4F, 0x7BDC, 0xBA50, 0x7BDD, 0xF3F4, 0x7BDE, 0xBA51,	0x7BDF, 0xBA52, 0x7BE0, 0xBA53, 0x7BE1, 0xB4DB, 0x7BE2, 0xBA54,
+	0x7BE3, 0xBA55, 0x7BE4, 0xBA56, 0x7BE5, 0xF3F6, 0x7BE6, 0xF3F7,	0x7BE7, 0xBA57, 0x7BE8, 0xBA58, 0x7BE9, 0xBA59, 0x7BEA, 0xF3F8,
+	0x7BEB, 0xBA5A, 0x7BEC, 0xBA5B, 0x7BED, 0xBA5C, 0x7BEE, 0xC0BA,	0x7BEF, 0xBA5D, 0x7BF0, 0xBA5E, 0x7BF1, 0xC0E9, 0x7BF2, 0xBA5F,
+	0x7BF3, 0xBA60, 0x7BF4, 0xBA61, 0x7BF5, 0xBA62, 0x7BF6, 0xBA63,	0x7BF7, 0xC5F1, 0x7BF8, 0xBA64, 0x7BF9, 0xBA65, 0x7BFA, 0xBA66,
+	0x7BFB, 0xBA67, 0x7BFC, 0xF3FB, 0x7BFD, 0xBA68, 0x7BFE, 0xF3FA,	0x7BFF, 0xBA69, 0x7C00, 0xBA6A, 0x7C01, 0xBA6B, 0x7C02, 0xBA6C,
+	0x7C03, 0xBA6D, 0x7C04, 0xBA6E, 0x7C05, 0xBA6F, 0x7C06, 0xBA70,	0x7C07, 0xB4D8, 0x7C08, 0xBA71, 0x7C09, 0xBA72, 0x7C0A, 0xBA73,
+	0x7C0B, 0xF3FE, 0x7C0C, 0xF3F9, 0x7C0D, 0xBA74, 0x7C0E, 0xBA75,	0x7C0F, 0xF3FC, 0x7C10, 0xBA76, 0x7C11, 0xBA77, 0x7C12, 0xBA78,
+	0x7C13, 0xBA79, 0x7C14, 0xBA7A, 0x7C15, 0xBA7B, 0x7C16, 0xF3FD,	0x7C17, 0xBA7C, 0x7C18, 0xBA7D, 0x7C19, 0xBA7E, 0x7C1A, 0xBA80,
+	0x7C1B, 0xBA81, 0x7C1C, 0xBA82, 0x7C1D, 0xBA83, 0x7C1E, 0xBA84,	0x7C1F, 0xF4A1, 0x7C20, 0xBA85, 0x7C21, 0xBA86, 0x7C22, 0xBA87,
+	0x7C23, 0xBA88, 0x7C24, 0xBA89, 0x7C25, 0xBA8A, 0x7C26, 0xF4A3,	0x7C27, 0xBBC9, 0x7C28, 0xBA8B, 0x7C29, 0xBA8C, 0x7C2A, 0xF4A2,
+	0x7C2B, 0xBA8D, 0x7C2C, 0xBA8E, 0x7C2D, 0xBA8F, 0x7C2E, 0xBA90,	0x7C2F, 0xBA91, 0x7C30, 0xBA92, 0x7C31, 0xBA93, 0x7C32, 0xBA94,
+	0x7C33, 0xBA95, 0x7C34, 0xBA96, 0x7C35, 0xBA97, 0x7C36, 0xBA98,	0x7C37, 0xBA99, 0x7C38, 0xF4A4, 0x7C39, 0xBA9A, 0x7C3A, 0xBA9B,
+	0x7C3B, 0xBA9C, 0x7C3C, 0xBA9D, 0x7C3D, 0xBA9E, 0x7C3E, 0xBA9F,	0x7C3F, 0xB2BE, 0x7C40, 0xF4A6, 0x7C41, 0xF4A5, 0x7C42, 0xBAA0,
+	0x7C43, 0xBB40, 0x7C44, 0xBB41, 0x7C45, 0xBB42, 0x7C46, 0xBB43,	0x7C47, 0xBB44, 0x7C48, 0xBB45, 0x7C49, 0xBB46, 0x7C4A, 0xBB47,
+	0x7C4B, 0xBB48, 0x7C4C, 0xBB49, 0x7C4D, 0xBCAE, 0x7C4E, 0xBB4A,	0x7C4F, 0xBB4B, 0x7C50, 0xBB4C, 0x7C51, 0xBB4D, 0x7C52, 0xBB4E,
+	0x7C53, 0xBB4F, 0x7C54, 0xBB50, 0x7C55, 0xBB51, 0x7C56, 0xBB52,	0x7C57, 0xBB53, 0x7C58, 0xBB54, 0x7C59, 0xBB55, 0x7C5A, 0xBB56,
+	0x7C5B, 0xBB57, 0x7C5C, 0xBB58, 0x7C5D, 0xBB59, 0x7C5E, 0xBB5A,	0x7C5F, 0xBB5B, 0x7C60, 0xBB5C, 0x7C61, 0xBB5D, 0x7C62, 0xBB5E,
+	0x7C63, 0xBB5F, 0x7C64, 0xBB60, 0x7C65, 0xBB61, 0x7C66, 0xBB62,	0x7C67, 0xBB63, 0x7C68, 0xBB64, 0x7C69, 0xBB65, 0x7C6A, 0xBB66,
+	0x7C6B, 0xBB67, 0x7C6C, 0xBB68, 0x7C6D, 0xBB69, 0x7C6E, 0xBB6A,	0x7C6F, 0xBB6B, 0x7C70, 0xBB6C, 0x7C71, 0xBB6D, 0x7C72, 0xBB6E,
+	0x7C73, 0xC3D7, 0x7C74, 0xD9E1, 0x7C75, 0xBB6F, 0x7C76, 0xBB70,	0x7C77, 0xBB71, 0x7C78, 0xBB72, 0x7C79, 0xBB73, 0x7C7A, 0xBB74,
+	0x7C7B, 0xC0E0, 0x7C7C, 0xF4CC, 0x7C7D, 0xD7D1, 0x7C7E, 0xBB75,	0x7C7F, 0xBB76, 0x7C80, 0xBB77, 0x7C81, 0xBB78, 0x7C82, 0xBB79,
+	0x7C83, 0xBB7A, 0x7C84, 0xBB7B, 0x7C85, 0xBB7C, 0x7C86, 0xBB7D,	0x7C87, 0xBB7E, 0x7C88, 0xBB80, 0x7C89, 0xB7DB, 0x7C8A, 0xBB81,
+	0x7C8B, 0xBB82, 0x7C8C, 0xBB83, 0x7C8D, 0xBB84, 0x7C8E, 0xBB85,	0x7C8F, 0xBB86, 0x7C90, 0xBB87, 0x7C91, 0xF4CE, 0x7C92, 0xC1A3,
+	0x7C93, 0xBB88, 0x7C94, 0xBB89, 0x7C95, 0xC6C9, 0x7C96, 0xBB8A,	0x7C97, 0xB4D6, 0x7C98, 0xD5B3, 0x7C99, 0xBB8B, 0x7C9A, 0xBB8C,
+	0x7C9B, 0xBB8D, 0x7C9C, 0xF4D0, 0x7C9D, 0xF4CF, 0x7C9E, 0xF4D1,	0x7C9F, 0xCBDA, 0x7CA0, 0xBB8E, 0x7CA1, 0xBB8F, 0x7CA2, 0xF4D2,
+	0x7CA3, 0xBB90, 0x7CA4, 0xD4C1, 0x7CA5, 0xD6E0, 0x7CA6, 0xBB91,	0x7CA7, 0xBB92, 0x7CA8, 0xBB93, 0x7CA9, 0xBB94, 0x7CAA, 0xB7E0,
+	0x7CAB, 0xBB95, 0x7CAC, 0xBB96, 0x7CAD, 0xBB97, 0x7CAE, 0xC1B8,	0x7CAF, 0xBB98, 0x7CB0, 0xBB99, 0x7CB1, 0xC1BB, 0x7CB2, 0xF4D3,
+	0x7CB3, 0xBEAC, 0x7CB4, 0xBB9A, 0x7CB5, 0xBB9B, 0x7CB6, 0xBB9C,	0x7CB7, 0xBB9D, 0x7CB8, 0xBB9E, 0x7CB9, 0xB4E2, 0x7CBA, 0xBB9F,
+	0x7CBB, 0xBBA0, 0x7CBC, 0xF4D4, 0x7CBD, 0xF4D5, 0x7CBE, 0xBEAB,	0x7CBF, 0xBC40, 0x7CC0, 0xBC41, 0x7CC1, 0xF4D6, 0x7CC2, 0xBC42,
+	0x7CC3, 0xBC43, 0x7CC4, 0xBC44, 0x7CC5, 0xF4DB, 0x7CC6, 0xBC45,	0x7CC7, 0xF4D7, 0x7CC8, 0xF4DA, 0x7CC9, 0xBC46, 0x7CCA, 0xBAFD,
+	0x7CCB, 0xBC47, 0x7CCC, 0xF4D8, 0x7CCD, 0xF4D9, 0x7CCE, 0xBC48,	0x7CCF, 0xBC49, 0x7CD0, 0xBC4A, 0x7CD1, 0xBC4B, 0x7CD2, 0xBC4C,
+	0x7CD3, 0xBC4D, 0x7CD4, 0xBC4E, 0x7CD5, 0xB8E2, 0x7CD6, 0xCCC7,	0x7CD7, 0xF4DC, 0x7CD8, 0xBC4F, 0x7CD9, 0xB2DA, 0x7CDA, 0xBC50,
+	0x7CDB, 0xBC51, 0x7CDC, 0xC3D3, 0x7CDD, 0xBC52, 0x7CDE, 0xBC53,	0x7CDF, 0xD4E3, 0x7CE0, 0xBFB7, 0x7CE1, 0xBC54, 0x7CE2, 0xBC55,
+	0x7CE3, 0xBC56, 0x7CE4, 0xBC57, 0x7CE5, 0xBC58, 0x7CE6, 0xBC59,	0x7CE7, 0xBC5A, 0x7CE8, 0xF4DD, 0x7CE9, 0xBC5B, 0x7CEA, 0xBC5C,
+	0x7CEB, 0xBC5D, 0x7CEC, 0xBC5E, 0x7CED, 0xBC5F, 0x7CEE, 0xBC60,	0x7CEF, 0xC5B4, 0x7CF0, 0xBC61, 0x7CF1, 0xBC62, 0x7CF2, 0xBC63,
+	0x7CF3, 0xBC64, 0x7CF4, 0xBC65, 0x7CF5, 0xBC66, 0x7CF6, 0xBC67,	0x7CF7, 0xBC68, 0x7CF8, 0xF4E9, 0x7CF9, 0xBC69, 0x7CFA, 0xBC6A,
+	0x7CFB, 0xCFB5, 0x7CFC, 0xBC6B, 0x7CFD, 0xBC6C, 0x7CFE, 0xBC6D,	0x7CFF, 0xBC6E, 0x7D00, 0xBC6F, 0x7D01, 0xBC70, 0x7D02, 0xBC71,
+	0x7D03, 0xBC72, 0x7D04, 0xBC73, 0x7D05, 0xBC74, 0x7D06, 0xBC75,	0x7D07, 0xBC76, 0x7D08, 0xBC77, 0x7D09, 0xBC78, 0x7D0A, 0xCEC9,
+	0x7D0B, 0xBC79, 0x7D0C, 0xBC7A, 0x7D0D, 0xBC7B, 0x7D0E, 0xBC7C,	0x7D0F, 0xBC7D, 0x7D10, 0xBC7E, 0x7D11, 0xBC80, 0x7D12, 0xBC81,
+	0x7D13, 0xBC82, 0x7D14, 0xBC83, 0x7D15, 0xBC84, 0x7D16, 0xBC85,	0x7D17, 0xBC86, 0x7D18, 0xBC87, 0x7D19, 0xBC88, 0x7D1A, 0xBC89,
+	0x7D1B, 0xBC8A, 0x7D1C, 0xBC8B, 0x7D1D, 0xBC8C, 0x7D1E, 0xBC8D,	0x7D1F, 0xBC8E, 0x7D20, 0xCBD8, 0x7D21, 0xBC8F, 0x7D22, 0xCBF7,
+	0x7D23, 0xBC90, 0x7D24, 0xBC91, 0x7D25, 0xBC92, 0x7D26, 0xBC93,	0x7D27, 0xBDF4, 0x7D28, 0xBC94, 0x7D29, 0xBC95, 0x7D2A, 0xBC96,
+	0x7D2B, 0xD7CF, 0x7D2C, 0xBC97, 0x7D2D, 0xBC98, 0x7D2E, 0xBC99,	0x7D2F, 0xC0DB, 0x7D30, 0xBC9A, 0x7D31, 0xBC9B, 0x7D32, 0xBC9C,
+	0x7D33, 0xBC9D, 0x7D34, 0xBC9E, 0x7D35, 0xBC9F, 0x7D36, 0xBCA0,	0x7D37, 0xBD40, 0x7D38, 0xBD41, 0x7D39, 0xBD42, 0x7D3A, 0xBD43,
+	0x7D3B, 0xBD44, 0x7D3C, 0xBD45, 0x7D3D, 0xBD46, 0x7D3E, 0xBD47,	0x7D3F, 0xBD48, 0x7D40, 0xBD49, 0x7D41, 0xBD4A, 0x7D42, 0xBD4B,
+	0x7D43, 0xBD4C, 0x7D44, 0xBD4D, 0x7D45, 0xBD4E, 0x7D46, 0xBD4F,	0x7D47, 0xBD50, 0x7D48, 0xBD51, 0x7D49, 0xBD52, 0x7D4A, 0xBD53,
+	0x7D4B, 0xBD54, 0x7D4C, 0xBD55, 0x7D4D, 0xBD56, 0x7D4E, 0xBD57,	0x7D4F, 0xBD58, 0x7D50, 0xBD59, 0x7D51, 0xBD5A, 0x7D52, 0xBD5B,
+	0x7D53, 0xBD5C, 0x7D54, 0xBD5D, 0x7D55, 0xBD5E, 0x7D56, 0xBD5F,	0x7D57, 0xBD60, 0x7D58, 0xBD61, 0x7D59, 0xBD62, 0x7D5A, 0xBD63,
+	0x7D5B, 0xBD64, 0x7D5C, 0xBD65, 0x7D5D, 0xBD66, 0x7D5E, 0xBD67,	0x7D5F, 0xBD68, 0x7D60, 0xBD69, 0x7D61, 0xBD6A, 0x7D62, 0xBD6B,
+	0x7D63, 0xBD6C, 0x7D64, 0xBD6D, 0x7D65, 0xBD6E, 0x7D66, 0xBD6F,	0x7D67, 0xBD70, 0x7D68, 0xBD71, 0x7D69, 0xBD72, 0x7D6A, 0xBD73,
+	0x7D6B, 0xBD74, 0x7D6C, 0xBD75, 0x7D6D, 0xBD76, 0x7D6E, 0xD0F5,	0x7D6F, 0xBD77, 0x7D70, 0xBD78, 0x7D71, 0xBD79, 0x7D72, 0xBD7A,
+	0x7D73, 0xBD7B, 0x7D74, 0xBD7C, 0x7D75, 0xBD7D, 0x7D76, 0xBD7E,	0x7D77, 0xF4EA, 0x7D78, 0xBD80, 0x7D79, 0xBD81, 0x7D7A, 0xBD82,
+	0x7D7B, 0xBD83, 0x7D7C, 0xBD84, 0x7D7D, 0xBD85, 0x7D7E, 0xBD86,	0x7D7F, 0xBD87, 0x7D80, 0xBD88, 0x7D81, 0xBD89, 0x7D82, 0xBD8A,
+	0x7D83, 0xBD8B, 0x7D84, 0xBD8C, 0x7D85, 0xBD8D, 0x7D86, 0xBD8E,	0x7D87, 0xBD8F, 0x7D88, 0xBD90, 0x7D89, 0xBD91, 0x7D8A, 0xBD92,
+	0x7D8B, 0xBD93, 0x7D8C, 0xBD94, 0x7D8D, 0xBD95, 0x7D8E, 0xBD96,	0x7D8F, 0xBD97, 0x7D90, 0xBD98, 0x7D91, 0xBD99, 0x7D92, 0xBD9A,
+	0x7D93, 0xBD9B, 0x7D94, 0xBD9C, 0x7D95, 0xBD9D, 0x7D96, 0xBD9E,	0x7D97, 0xBD9F, 0x7D98, 0xBDA0, 0x7D99, 0xBE40, 0x7D9A, 0xBE41,
+	0x7D9B, 0xBE42, 0x7D9C, 0xBE43, 0x7D9D, 0xBE44, 0x7D9E, 0xBE45,	0x7D9F, 0xBE46, 0x7DA0, 0xBE47, 0x7DA1, 0xBE48, 0x7DA2, 0xBE49,
+	0x7DA3, 0xBE4A, 0x7DA4, 0xBE4B, 0x7DA5, 0xBE4C, 0x7DA6, 0xF4EB,	0x7DA7, 0xBE4D, 0x7DA8, 0xBE4E, 0x7DA9, 0xBE4F, 0x7DAA, 0xBE50,
+	0x7DAB, 0xBE51, 0x7DAC, 0xBE52, 0x7DAD, 0xBE53, 0x7DAE, 0xF4EC,	0x7DAF, 0xBE54, 0x7DB0, 0xBE55, 0x7DB1, 0xBE56, 0x7DB2, 0xBE57,
+	0x7DB3, 0xBE58, 0x7DB4, 0xBE59, 0x7DB5, 0xBE5A, 0x7DB6, 0xBE5B,	0x7DB7, 0xBE5C, 0x7DB8, 0xBE5D, 0x7DB9, 0xBE5E, 0x7DBA, 0xBE5F,
+	0x7DBB, 0xBE60, 0x7DBC, 0xBE61, 0x7DBD, 0xBE62, 0x7DBE, 0xBE63,	0x7DBF, 0xBE64, 0x7DC0, 0xBE65, 0x7DC1, 0xBE66, 0x7DC2, 0xBE67,
+	0x7DC3, 0xBE68, 0x7DC4, 0xBE69, 0x7DC5, 0xBE6A, 0x7DC6, 0xBE6B,	0x7DC7, 0xBE6C, 0x7DC8, 0xBE6D, 0x7DC9, 0xBE6E, 0x7DCA, 0xBE6F,
+	0x7DCB, 0xBE70, 0x7DCC, 0xBE71, 0x7DCD, 0xBE72, 0x7DCE, 0xBE73,	0x7DCF, 0xBE74, 0x7DD0, 0xBE75, 0x7DD1, 0xBE76, 0x7DD2, 0xBE77,
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+	0x7DDB, 0xBE81, 0x7DDC, 0xBE82, 0x7DDD, 0xBE83, 0x7DDE, 0xBE84,	0x7DDF, 0xBE85, 0x7DE0, 0xBE86, 0x7DE1, 0xBE87, 0x7DE2, 0xBE88,
+	0x7DE3, 0xBE89, 0x7DE4, 0xBE8A, 0x7DE5, 0xBE8B, 0x7DE6, 0xBE8C,	0x7DE7, 0xBE8D, 0x7DE8, 0xBE8E, 0x7DE9, 0xBE8F, 0x7DEA, 0xBE90,
+	0x7DEB, 0xBE91, 0x7DEC, 0xBE92, 0x7DED, 0xBE93, 0x7DEE, 0xBE94,	0x7DEF, 0xBE95, 0x7DF0, 0xBE96, 0x7DF1, 0xBE97, 0x7DF2, 0xBE98,
+	0x7DF3, 0xBE99, 0x7DF4, 0xBE9A, 0x7DF5, 0xBE9B, 0x7DF6, 0xBE9C,	0x7DF7, 0xBE9D, 0x7DF8, 0xBE9E, 0x7DF9, 0xBE9F, 0x7DFA, 0xBEA0,
+	0x7DFB, 0xBF40, 0x7DFC, 0xBF41, 0x7DFD, 0xBF42, 0x7DFE, 0xBF43,	0x7DFF, 0xBF44, 0x7E00, 0xBF45, 0x7E01, 0xBF46, 0x7E02, 0xBF47,
+	0x7E03, 0xBF48, 0x7E04, 0xBF49, 0x7E05, 0xBF4A, 0x7E06, 0xBF4B,	0x7E07, 0xBF4C, 0x7E08, 0xBF4D, 0x7E09, 0xBF4E, 0x7E0A, 0xBF4F,
+	0x7E0B, 0xBF50, 0x7E0C, 0xBF51, 0x7E0D, 0xBF52, 0x7E0E, 0xBF53,	0x7E0F, 0xBF54, 0x7E10, 0xBF55, 0x7E11, 0xBF56, 0x7E12, 0xBF57,
+	0x7E13, 0xBF58, 0x7E14, 0xBF59, 0x7E15, 0xBF5A, 0x7E16, 0xBF5B,	0x7E17, 0xBF5C, 0x7E18, 0xBF5D, 0x7E19, 0xBF5E, 0x7E1A, 0xBF5F,
+	0x7E1B, 0xBF60, 0x7E1C, 0xBF61, 0x7E1D, 0xBF62, 0x7E1E, 0xBF63,	0x7E1F, 0xBF64, 0x7E20, 0xBF65, 0x7E21, 0xBF66, 0x7E22, 0xBF67,
+	0x7E23, 0xBF68, 0x7E24, 0xBF69, 0x7E25, 0xBF6A, 0x7E26, 0xBF6B,	0x7E27, 0xBF6C, 0x7E28, 0xBF6D, 0x7E29, 0xBF6E, 0x7E2A, 0xBF6F,
+	0x7E2B, 0xBF70, 0x7E2C, 0xBF71, 0x7E2D, 0xBF72, 0x7E2E, 0xBF73,	0x7E2F, 0xBF74, 0x7E30, 0xBF75, 0x7E31, 0xBF76, 0x7E32, 0xBF77,
+	0x7E33, 0xBF78, 0x7E34, 0xBF79, 0x7E35, 0xBF7A, 0x7E36, 0xBF7B,	0x7E37, 0xBF7C, 0x7E38, 0xBF7D, 0x7E39, 0xBF7E, 0x7E3A, 0xBF80,
+	0x7E3B, 0xF7E3, 0x7E3C, 0xBF81, 0x7E3D, 0xBF82, 0x7E3E, 0xBF83,	0x7E3F, 0xBF84, 0x7E40, 0xBF85, 0x7E41, 0xB7B1, 0x7E42, 0xBF86,
+	0x7E43, 0xBF87, 0x7E44, 0xBF88, 0x7E45, 0xBF89, 0x7E46, 0xBF8A,	0x7E47, 0xF4ED, 0x7E48, 0xBF8B, 0x7E49, 0xBF8C, 0x7E4A, 0xBF8D,
+	0x7E4B, 0xBF8E, 0x7E4C, 0xBF8F, 0x7E4D, 0xBF90, 0x7E4E, 0xBF91,	0x7E4F, 0xBF92, 0x7E50, 0xBF93, 0x7E51, 0xBF94, 0x7E52, 0xBF95,
+	0x7E53, 0xBF96, 0x7E54, 0xBF97, 0x7E55, 0xBF98, 0x7E56, 0xBF99,	0x7E57, 0xBF9A, 0x7E58, 0xBF9B, 0x7E59, 0xBF9C, 0x7E5A, 0xBF9D,
+	0x7E5B, 0xBF9E, 0x7E5C, 0xBF9F, 0x7E5D, 0xBFA0, 0x7E5E, 0xC040,	0x7E5F, 0xC041, 0x7E60, 0xC042, 0x7E61, 0xC043, 0x7E62, 0xC044,
+	0x7E63, 0xC045, 0x7E64, 0xC046, 0x7E65, 0xC047, 0x7E66, 0xC048,	0x7E67, 0xC049, 0x7E68, 0xC04A, 0x7E69, 0xC04B, 0x7E6A, 0xC04C,
+	0x7E6B, 0xC04D, 0x7E6C, 0xC04E, 0x7E6D, 0xC04F, 0x7E6E, 0xC050,	0x7E6F, 0xC051, 0x7E70, 0xC052, 0x7E71, 0xC053, 0x7E72, 0xC054,
+	0x7E73, 0xC055, 0x7E74, 0xC056, 0x7E75, 0xC057, 0x7E76, 0xC058,	0x7E77, 0xC059, 0x7E78, 0xC05A, 0x7E79, 0xC05B, 0x7E7A, 0xC05C,
+	0x7E7B, 0xC05D, 0x7E7C, 0xC05E, 0x7E7D, 0xC05F, 0x7E7E, 0xC060,	0x7E7F, 0xC061, 0x7E80, 0xC062, 0x7E81, 0xC063, 0x7E82, 0xD7EB,
+	0x7E83, 0xC064, 0x7E84, 0xC065, 0x7E85, 0xC066, 0x7E86, 0xC067,	0x7E87, 0xC068, 0x7E88, 0xC069, 0x7E89, 0xC06A, 0x7E8A, 0xC06B,
+	0x7E8B, 0xC06C, 0x7E8C, 0xC06D, 0x7E8D, 0xC06E, 0x7E8E, 0xC06F,	0x7E8F, 0xC070, 0x7E90, 0xC071, 0x7E91, 0xC072, 0x7E92, 0xC073,
+	0x7E93, 0xC074, 0x7E94, 0xC075, 0x7E95, 0xC076, 0x7E96, 0xC077,	0x7E97, 0xC078, 0x7E98, 0xC079, 0x7E99, 0xC07A, 0x7E9A, 0xC07B,
+	0x7E9B, 0xF4EE, 0x7E9C, 0xC07C, 0x7E9D, 0xC07D, 0x7E9E, 0xC07E,	0x7E9F, 0xE6F9, 0x7EA0, 0xBEC0, 0x7EA1, 0xE6FA, 0x7EA2, 0xBAEC,
+	0x7EA3, 0xE6FB, 0x7EA4, 0xCFCB, 0x7EA5, 0xE6FC, 0x7EA6, 0xD4BC,	0x7EA7, 0xBCB6, 0x7EA8, 0xE6FD, 0x7EA9, 0xE6FE, 0x7EAA, 0xBCCD,
+	0x7EAB, 0xC8D2, 0x7EAC, 0xCEB3, 0x7EAD, 0xE7A1, 0x7EAE, 0xC080,	0x7EAF, 0xB4BF, 0x7EB0, 0xE7A2, 0x7EB1, 0xC9B4, 0x7EB2, 0xB8D9,
+	0x7EB3, 0xC4C9, 0x7EB4, 0xC081, 0x7EB5, 0xD7DD, 0x7EB6, 0xC2DA,	0x7EB7, 0xB7D7, 0x7EB8, 0xD6BD, 0x7EB9, 0xCEC6, 0x7EBA, 0xB7C4,
+	0x7EBB, 0xC082, 0x7EBC, 0xC083, 0x7EBD, 0xC5A6, 0x7EBE, 0xE7A3,	0x7EBF, 0xCFDF, 0x7EC0, 0xE7A4, 0x7EC1, 0xE7A5, 0x7EC2, 0xE7A6,
+	0x7EC3, 0xC1B7, 0x7EC4, 0xD7E9, 0x7EC5, 0xC9F0, 0x7EC6, 0xCFB8,	0x7EC7, 0xD6AF, 0x7EC8, 0xD6D5, 0x7EC9, 0xE7A7, 0x7ECA, 0xB0ED,
+	0x7ECB, 0xE7A8, 0x7ECC, 0xE7A9, 0x7ECD, 0xC9DC, 0x7ECE, 0xD2EF,	0x7ECF, 0xBEAD, 0x7ED0, 0xE7AA, 0x7ED1, 0xB0F3, 0x7ED2, 0xC8DE,
+	0x7ED3, 0xBDE1, 0x7ED4, 0xE7AB, 0x7ED5, 0xC8C6, 0x7ED6, 0xC084,	0x7ED7, 0xE7AC, 0x7ED8, 0xBBE6, 0x7ED9, 0xB8F8, 0x7EDA, 0xD1A4,
+	0x7EDB, 0xE7AD, 0x7EDC, 0xC2E7, 0x7EDD, 0xBEF8, 0x7EDE, 0xBDCA,	0x7EDF, 0xCDB3, 0x7EE0, 0xE7AE, 0x7EE1, 0xE7AF, 0x7EE2, 0xBEEE,
+	0x7EE3, 0xD0E5, 0x7EE4, 0xC085, 0x7EE5, 0xCBE7, 0x7EE6, 0xCCD0,	0x7EE7, 0xBCCC, 0x7EE8, 0xE7B0, 0x7EE9, 0xBCA8, 0x7EEA, 0xD0F7,
+	0x7EEB, 0xE7B1, 0x7EEC, 0xC086, 0x7EED, 0xD0F8, 0x7EEE, 0xE7B2,	0x7EEF, 0xE7B3, 0x7EF0, 0xB4C2, 0x7EF1, 0xE7B4, 0x7EF2, 0xE7B5,
+	0x7EF3, 0xC9FE, 0x7EF4, 0xCEAC, 0x7EF5, 0xC3E0, 0x7EF6, 0xE7B7,	0x7EF7, 0xB1C1, 0x7EF8, 0xB3F1, 0x7EF9, 0xC087, 0x7EFA, 0xE7B8,
+	0x7EFB, 0xE7B9, 0x7EFC, 0xD7DB, 0x7EFD, 0xD5C0, 0x7EFE, 0xE7BA,	0x7EFF, 0xC2CC, 0x7F00, 0xD7BA, 0x7F01, 0xE7BB, 0x7F02, 0xE7BC,
+	0x7F03, 0xE7BD, 0x7F04, 0xBCEA, 0x7F05, 0xC3E5, 0x7F06, 0xC0C2,	0x7F07, 0xE7BE, 0x7F08, 0xE7BF, 0x7F09, 0xBCA9, 0x7F0A, 0xC088,
+	0x7F0B, 0xE7C0, 0x7F0C, 0xE7C1, 0x7F0D, 0xE7B6, 0x7F0E, 0xB6D0,	0x7F0F, 0xE7C2, 0x7F10, 0xC089, 0x7F11, 0xE7C3, 0x7F12, 0xE7C4,
+	0x7F13, 0xBBBA, 0x7F14, 0xB5DE, 0x7F15, 0xC2C6, 0x7F16, 0xB1E0,	0x7F17, 0xE7C5, 0x7F18, 0xD4B5, 0x7F19, 0xE7C6, 0x7F1A, 0xB8BF,
+	0x7F1B, 0xE7C8, 0x7F1C, 0xE7C7, 0x7F1D, 0xB7EC, 0x7F1E, 0xC08A,	0x7F1F, 0xE7C9, 0x7F20, 0xB2F8, 0x7F21, 0xE7CA, 0x7F22, 0xE7CB,
+	0x7F23, 0xE7CC, 0x7F24, 0xE7CD, 0x7F25, 0xE7CE, 0x7F26, 0xE7CF,	0x7F27, 0xE7D0, 0x7F28, 0xD3A7, 0x7F29, 0xCBF5, 0x7F2A, 0xE7D1,
+	0x7F2B, 0xE7D2, 0x7F2C, 0xE7D3, 0x7F2D, 0xE7D4, 0x7F2E, 0xC9C9,	0x7F2F, 0xE7D5, 0x7F30, 0xE7D6, 0x7F31, 0xE7D7, 0x7F32, 0xE7D8,
+	0x7F33, 0xE7D9, 0x7F34, 0xBDC9, 0x7F35, 0xE7DA, 0x7F36, 0xF3BE,	0x7F37, 0xC08B, 0x7F38, 0xB8D7, 0x7F39, 0xC08C, 0x7F3A, 0xC8B1,
+	0x7F3B, 0xC08D, 0x7F3C, 0xC08E, 0x7F3D, 0xC08F, 0x7F3E, 0xC090,	0x7F3F, 0xC091, 0x7F40, 0xC092, 0x7F41, 0xC093, 0x7F42, 0xF3BF,
+	0x7F43, 0xC094, 0x7F44, 0xF3C0, 0x7F45, 0xF3C1, 0x7F46, 0xC095,	0x7F47, 0xC096, 0x7F48, 0xC097, 0x7F49, 0xC098, 0x7F4A, 0xC099,
+	0x7F4B, 0xC09A, 0x7F4C, 0xC09B, 0x7F4D, 0xC09C, 0x7F4E, 0xC09D,	0x7F4F, 0xC09E, 0x7F50, 0xB9DE, 0x7F51, 0xCDF8, 0x7F52, 0xC09F,
+	0x7F53, 0xC0A0, 0x7F54, 0xD8E8, 0x7F55, 0xBAB1, 0x7F56, 0xC140,	0x7F57, 0xC2DE, 0x7F58, 0xEEB7, 0x7F59, 0xC141, 0x7F5A, 0xB7A3,
+	0x7F5B, 0xC142, 0x7F5C, 0xC143, 0x7F5D, 0xC144, 0x7F5E, 0xC145,	0x7F5F, 0xEEB9, 0x7F60, 0xC146, 0x7F61, 0xEEB8, 0x7F62, 0xB0D5,
+	0x7F63, 0xC147, 0x7F64, 0xC148, 0x7F65, 0xC149, 0x7F66, 0xC14A,	0x7F67, 0xC14B, 0x7F68, 0xEEBB, 0x7F69, 0xD5D6, 0x7F6A, 0xD7EF,
+	0x7F6B, 0xC14C, 0x7F6C, 0xC14D, 0x7F6D, 0xC14E, 0x7F6E, 0xD6C3,	0x7F6F, 0xC14F, 0x7F70, 0xC150, 0x7F71, 0xEEBD, 0x7F72, 0xCAF0,
+	0x7F73, 0xC151, 0x7F74, 0xEEBC, 0x7F75, 0xC152, 0x7F76, 0xC153,	0x7F77, 0xC154, 0x7F78, 0xC155, 0x7F79, 0xEEBE, 0x7F7A, 0xC156,
+	0x7F7B, 0xC157, 0x7F7C, 0xC158, 0x7F7D, 0xC159, 0x7F7E, 0xEEC0,	0x7F7F, 0xC15A, 0x7F80, 0xC15B, 0x7F81, 0xEEBF, 0x7F82, 0xC15C,
+	0x7F83, 0xC15D, 0x7F84, 0xC15E, 0x7F85, 0xC15F, 0x7F86, 0xC160,	0x7F87, 0xC161, 0x7F88, 0xC162, 0x7F89, 0xC163, 0x7F8A, 0xD1F2,
+	0x7F8B, 0xC164, 0x7F8C, 0xC7BC, 0x7F8D, 0xC165, 0x7F8E, 0xC3C0,	0x7F8F, 0xC166, 0x7F90, 0xC167, 0x7F91, 0xC168, 0x7F92, 0xC169,
+	0x7F93, 0xC16A, 0x7F94, 0xB8E1, 0x7F95, 0xC16B, 0x7F96, 0xC16C,	0x7F97, 0xC16D, 0x7F98, 0xC16E, 0x7F99, 0xC16F, 0x7F9A, 0xC1E7,
+	0x7F9B, 0xC170, 0x7F9C, 0xC171, 0x7F9D, 0xF4C6, 0x7F9E, 0xD0DF,	0x7F9F, 0xF4C7, 0x7FA0, 0xC172, 0x7FA1, 0xCFDB, 0x7FA2, 0xC173,
+	0x7FA3, 0xC174, 0x7FA4, 0xC8BA, 0x7FA5, 0xC175, 0x7FA6, 0xC176,	0x7FA7, 0xF4C8, 0x7FA8, 0xC177, 0x7FA9, 0xC178, 0x7FAA, 0xC179,
+	0x7FAB, 0xC17A, 0x7FAC, 0xC17B, 0x7FAD, 0xC17C, 0x7FAE, 0xC17D,	0x7FAF, 0xF4C9, 0x7FB0, 0xF4CA, 0x7FB1, 0xC17E, 0x7FB2, 0xF4CB,
+	0x7FB3, 0xC180, 0x7FB4, 0xC181, 0x7FB5, 0xC182, 0x7FB6, 0xC183,	0x7FB7, 0xC184, 0x7FB8, 0xD9FA, 0x7FB9, 0xB8FE, 0x7FBA, 0xC185,
+	0x7FBB, 0xC186, 0x7FBC, 0xE5F1, 0x7FBD, 0xD3F0, 0x7FBE, 0xC187,	0x7FBF, 0xF4E0, 0x7FC0, 0xC188, 0x7FC1, 0xCECC, 0x7FC2, 0xC189,
+	0x7FC3, 0xC18A, 0x7FC4, 0xC18B, 0x7FC5, 0xB3E1, 0x7FC6, 0xC18C,	0x7FC7, 0xC18D, 0x7FC8, 0xC18E, 0x7FC9, 0xC18F, 0x7FCA, 0xF1B4,
+	0x7FCB, 0xC190, 0x7FCC, 0xD2EE, 0x7FCD, 0xC191, 0x7FCE, 0xF4E1,	0x7FCF, 0xC192, 0x7FD0, 0xC193, 0x7FD1, 0xC194, 0x7FD2, 0xC195,
+	0x7FD3, 0xC196, 0x7FD4, 0xCFE8, 0x7FD5, 0xF4E2, 0x7FD6, 0xC197,	0x7FD7, 0xC198, 0x7FD8, 0xC7CC, 0x7FD9, 0xC199, 0x7FDA, 0xC19A,
+	0x7FDB, 0xC19B, 0x7FDC, 0xC19C, 0x7FDD, 0xC19D, 0x7FDE, 0xC19E,	0x7FDF, 0xB5D4, 0x7FE0, 0xB4E4, 0x7FE1, 0xF4E4, 0x7FE2, 0xC19F,
+	0x7FE3, 0xC1A0, 0x7FE4, 0xC240, 0x7FE5, 0xF4E3, 0x7FE6, 0xF4E5,	0x7FE7, 0xC241, 0x7FE8, 0xC242, 0x7FE9, 0xF4E6, 0x7FEA, 0xC243,
+	0x7FEB, 0xC244, 0x7FEC, 0xC245, 0x7FED, 0xC246, 0x7FEE, 0xF4E7,	0x7FEF, 0xC247, 0x7FF0, 0xBAB2, 0x7FF1, 0xB0BF, 0x7FF2, 0xC248,
+	0x7FF3, 0xF4E8, 0x7FF4, 0xC249, 0x7FF5, 0xC24A, 0x7FF6, 0xC24B,	0x7FF7, 0xC24C, 0x7FF8, 0xC24D, 0x7FF9, 0xC24E, 0x7FFA, 0xC24F,
+	0x7FFB, 0xB7AD, 0x7FFC, 0xD2ED, 0x7FFD, 0xC250, 0x7FFE, 0xC251,	0x7FFF, 0xC252, 0x8000, 0xD2AB, 0x8001, 0xC0CF, 0x8002, 0xC253,
+	0x8003, 0xBFBC, 0x8004, 0xEBA3, 0x8005, 0xD5DF, 0x8006, 0xEAC8,	0x8007, 0xC254, 0x8008, 0xC255, 0x8009, 0xC256, 0x800A, 0xC257,
+	0x800B, 0xF1F3, 0x800C, 0xB6F8, 0x800D, 0xCBA3, 0x800E, 0xC258,	0x800F, 0xC259, 0x8010, 0xC4CD, 0x8011, 0xC25A, 0x8012, 0xF1E7,
+	0x8013, 0xC25B, 0x8014, 0xF1E8, 0x8015, 0xB8FB, 0x8016, 0xF1E9,	0x8017, 0xBAC4, 0x8018, 0xD4C5, 0x8019, 0xB0D2, 0x801A, 0xC25C,
+	0x801B, 0xC25D, 0x801C, 0xF1EA, 0x801D, 0xC25E, 0x801E, 0xC25F,	0x801F, 0xC260, 0x8020, 0xF1EB, 0x8021, 0xC261, 0x8022, 0xF1EC,
+	0x8023, 0xC262, 0x8024, 0xC263, 0x8025, 0xF1ED, 0x8026, 0xF1EE,	0x8027, 0xF1EF, 0x8028, 0xF1F1, 0x8029, 0xF1F0, 0x802A, 0xC5D5,
+	0x802B, 0xC264, 0x802C, 0xC265, 0x802D, 0xC266, 0x802E, 0xC267,	0x802F, 0xC268, 0x8030, 0xC269, 0x8031, 0xF1F2, 0x8032, 0xC26A,
+	0x8033, 0xB6FA, 0x8034, 0xC26B, 0x8035, 0xF1F4, 0x8036, 0xD2AE,	0x8037, 0xDEC7, 0x8038, 0xCBCA, 0x8039, 0xC26C, 0x803A, 0xC26D,
+	0x803B, 0xB3DC, 0x803C, 0xC26E, 0x803D, 0xB5A2, 0x803E, 0xC26F,	0x803F, 0xB9A2, 0x8040, 0xC270, 0x8041, 0xC271, 0x8042, 0xC4F4,
+	0x8043, 0xF1F5, 0x8044, 0xC272, 0x8045, 0xC273, 0x8046, 0xF1F6,	0x8047, 0xC274, 0x8048, 0xC275, 0x8049, 0xC276, 0x804A, 0xC1C4,
+	0x804B, 0xC1FB, 0x804C, 0xD6B0, 0x804D, 0xF1F7, 0x804E, 0xC277,	0x804F, 0xC278, 0x8050, 0xC279, 0x8051, 0xC27A, 0x8052, 0xF1F8,
+	0x8053, 0xC27B, 0x8054, 0xC1AA, 0x8055, 0xC27C, 0x8056, 0xC27D,	0x8057, 0xC27E, 0x8058, 0xC6B8, 0x8059, 0xC280, 0x805A, 0xBEDB,
+	0x805B, 0xC281, 0x805C, 0xC282, 0x805D, 0xC283, 0x805E, 0xC284,	0x805F, 0xC285, 0x8060, 0xC286, 0x8061, 0xC287, 0x8062, 0xC288,
+	0x8063, 0xC289, 0x8064, 0xC28A, 0x8065, 0xC28B, 0x8066, 0xC28C,	0x8067, 0xC28D, 0x8068, 0xC28E, 0x8069, 0xF1F9, 0x806A, 0xB4CF,
+	0x806B, 0xC28F, 0x806C, 0xC290, 0x806D, 0xC291, 0x806E, 0xC292,	0x806F, 0xC293, 0x8070, 0xC294, 0x8071, 0xF1FA, 0x8072, 0xC295,
+	0x8073, 0xC296, 0x8074, 0xC297, 0x8075, 0xC298, 0x8076, 0xC299,	0x8077, 0xC29A, 0x8078, 0xC29B, 0x8079, 0xC29C, 0x807A, 0xC29D,
+	0x807B, 0xC29E, 0x807C, 0xC29F, 0x807D, 0xC2A0, 0x807E, 0xC340,	0x807F, 0xEDB2, 0x8080, 0xEDB1, 0x8081, 0xC341, 0x8082, 0xC342,
+	0x8083, 0xCBE0, 0x8084, 0xD2DE, 0x8085, 0xC343, 0x8086, 0xCBC1,	0x8087, 0xD5D8, 0x8088, 0xC344, 0x8089, 0xC8E2, 0x808A, 0xC345,
+	0x808B, 0xC0DF, 0x808C, 0xBCA1, 0x808D, 0xC346, 0x808E, 0xC347,	0x808F, 0xC348, 0x8090, 0xC349, 0x8091, 0xC34A, 0x8092, 0xC34B,
+	0x8093, 0xEBC1, 0x8094, 0xC34C, 0x8095, 0xC34D, 0x8096, 0xD0A4,	0x8097, 0xC34E, 0x8098, 0xD6E2, 0x8099, 0xC34F, 0x809A, 0xB6C7,
+	0x809B, 0xB8D8, 0x809C, 0xEBC0, 0x809D, 0xB8CE, 0x809E, 0xC350,	0x809F, 0xEBBF, 0x80A0, 0xB3A6, 0x80A1, 0xB9C9, 0x80A2, 0xD6AB,
+	0x80A3, 0xC351, 0x80A4, 0xB7F4, 0x80A5, 0xB7CA, 0x80A6, 0xC352,	0x80A7, 0xC353, 0x80A8, 0xC354, 0x80A9, 0xBCE7, 0x80AA, 0xB7BE,
+	0x80AB, 0xEBC6, 0x80AC, 0xC355, 0x80AD, 0xEBC7, 0x80AE, 0xB0B9,	0x80AF, 0xBFCF, 0x80B0, 0xC356, 0x80B1, 0xEBC5, 0x80B2, 0xD3FD,
+	0x80B3, 0xC357, 0x80B4, 0xEBC8, 0x80B5, 0xC358, 0x80B6, 0xC359,	0x80B7, 0xEBC9, 0x80B8, 0xC35A, 0x80B9, 0xC35B, 0x80BA, 0xB7CE,
+	0x80BB, 0xC35C, 0x80BC, 0xEBC2, 0x80BD, 0xEBC4, 0x80BE, 0xC9F6,	0x80BF, 0xD6D7, 0x80C0, 0xD5CD, 0x80C1, 0xD0B2, 0x80C2, 0xEBCF,
+	0x80C3, 0xCEB8, 0x80C4, 0xEBD0, 0x80C5, 0xC35D, 0x80C6, 0xB5A8,	0x80C7, 0xC35E, 0x80C8, 0xC35F, 0x80C9, 0xC360, 0x80CA, 0xC361,
+	0x80CB, 0xC362, 0x80CC, 0xB1B3, 0x80CD, 0xEBD2, 0x80CE, 0xCCA5,	0x80CF, 0xC363, 0x80D0, 0xC364, 0x80D1, 0xC365, 0x80D2, 0xC366,
+	0x80D3, 0xC367, 0x80D4, 0xC368, 0x80D5, 0xC369, 0x80D6, 0xC5D6,	0x80D7, 0xEBD3, 0x80D8, 0xC36A, 0x80D9, 0xEBD1, 0x80DA, 0xC5DF,
+	0x80DB, 0xEBCE, 0x80DC, 0xCAA4, 0x80DD, 0xEBD5, 0x80DE, 0xB0FB,	0x80DF, 0xC36B, 0x80E0, 0xC36C, 0x80E1, 0xBAFA, 0x80E2, 0xC36D,
+	0x80E3, 0xC36E, 0x80E4, 0xD8B7, 0x80E5, 0xF1E3, 0x80E6, 0xC36F,	0x80E7, 0xEBCA, 0x80E8, 0xEBCB, 0x80E9, 0xEBCC, 0x80EA, 0xEBCD,
+	0x80EB, 0xEBD6, 0x80EC, 0xE6C0, 0x80ED, 0xEBD9, 0x80EE, 0xC370,	0x80EF, 0xBFE8, 0x80F0, 0xD2C8, 0x80F1, 0xEBD7, 0x80F2, 0xEBDC,
+	0x80F3, 0xB8EC, 0x80F4, 0xEBD8, 0x80F5, 0xC371, 0x80F6, 0xBDBA,	0x80F7, 0xC372, 0x80F8, 0xD0D8, 0x80F9, 0xC373, 0x80FA, 0xB0B7,
+	0x80FB, 0xC374, 0x80FC, 0xEBDD, 0x80FD, 0xC4DC, 0x80FE, 0xC375,	0x80FF, 0xC376, 0x8100, 0xC377, 0x8101, 0xC378, 0x8102, 0xD6AC,
+	0x8103, 0xC379, 0x8104, 0xC37A, 0x8105, 0xC37B, 0x8106, 0xB4E0,	0x8107, 0xC37C, 0x8108, 0xC37D, 0x8109, 0xC2F6, 0x810A, 0xBCB9,
+	0x810B, 0xC37E, 0x810C, 0xC380, 0x810D, 0xEBDA, 0x810E, 0xEBDB,	0x810F, 0xD4E0, 0x8110, 0xC6EA, 0x8111, 0xC4D4, 0x8112, 0xEBDF,
+	0x8113, 0xC5A7, 0x8114, 0xD9F5, 0x8115, 0xC381, 0x8116, 0xB2B1,	0x8117, 0xC382, 0x8118, 0xEBE4, 0x8119, 0xC383, 0x811A, 0xBDC5,
+	0x811B, 0xC384, 0x811C, 0xC385, 0x811D, 0xC386, 0x811E, 0xEBE2,	0x811F, 0xC387, 0x8120, 0xC388, 0x8121, 0xC389, 0x8122, 0xC38A,
+	0x8123, 0xC38B, 0x8124, 0xC38C, 0x8125, 0xC38D, 0x8126, 0xC38E,	0x8127, 0xC38F, 0x8128, 0xC390, 0x8129, 0xC391, 0x812A, 0xC392,
+	0x812B, 0xC393, 0x812C, 0xEBE3, 0x812D, 0xC394, 0x812E, 0xC395,	0x812F, 0xB8AC, 0x8130, 0xC396, 0x8131, 0xCDD1, 0x8132, 0xEBE5,
+	0x8133, 0xC397, 0x8134, 0xC398, 0x8135, 0xC399, 0x8136, 0xEBE1,	0x8137, 0xC39A, 0x8138, 0xC1B3, 0x8139, 0xC39B, 0x813A, 0xC39C,
+	0x813B, 0xC39D, 0x813C, 0xC39E, 0x813D, 0xC39F, 0x813E, 0xC6A2,	0x813F, 0xC3A0, 0x8140, 0xC440, 0x8141, 0xC441, 0x8142, 0xC442,
+	0x8143, 0xC443, 0x8144, 0xC444, 0x8145, 0xC445, 0x8146, 0xCCF3,	0x8147, 0xC446, 0x8148, 0xEBE6, 0x8149, 0xC447, 0x814A, 0xC0B0,
+	0x814B, 0xD2B8, 0x814C, 0xEBE7, 0x814D, 0xC448, 0x814E, 0xC449,	0x814F, 0xC44A, 0x8150, 0xB8AF, 0x8151, 0xB8AD, 0x8152, 0xC44B,
+	0x8153, 0xEBE8, 0x8154, 0xC7BB, 0x8155, 0xCDF3, 0x8156, 0xC44C,	0x8157, 0xC44D, 0x8158, 0xC44E, 0x8159, 0xEBEA, 0x815A, 0xEBEB,
+	0x815B, 0xC44F, 0x815C, 0xC450, 0x815D, 0xC451, 0x815E, 0xC452,	0x815F, 0xC453, 0x8160, 0xEBED, 0x8161, 0xC454, 0x8162, 0xC455,
+	0x8163, 0xC456, 0x8164, 0xC457, 0x8165, 0xD0C8, 0x8166, 0xC458,	0x8167, 0xEBF2, 0x8168, 0xC459, 0x8169, 0xEBEE, 0x816A, 0xC45A,
+	0x816B, 0xC45B, 0x816C, 0xC45C, 0x816D, 0xEBF1, 0x816E, 0xC8F9,	0x816F, 0xC45D, 0x8170, 0xD1FC, 0x8171, 0xEBEC, 0x8172, 0xC45E,
+	0x8173, 0xC45F, 0x8174, 0xEBE9, 0x8175, 0xC460, 0x8176, 0xC461,	0x8177, 0xC462, 0x8178, 0xC463, 0x8179, 0xB8B9, 0x817A, 0xCFD9,
+	0x817B, 0xC4E5, 0x817C, 0xEBEF, 0x817D, 0xEBF0, 0x817E, 0xCCDA,	0x817F, 0xCDC8, 0x8180, 0xB0F2, 0x8181, 0xC464, 0x8182, 0xEBF6,
+	0x8183, 0xC465, 0x8184, 0xC466, 0x8185, 0xC467, 0x8186, 0xC468,	0x8187, 0xC469, 0x8188, 0xEBF5, 0x8189, 0xC46A, 0x818A, 0xB2B2,
+	0x818B, 0xC46B, 0x818C, 0xC46C, 0x818D, 0xC46D, 0x818E, 0xC46E,	0x818F, 0xB8E0, 0x8190, 0xC46F, 0x8191, 0xEBF7, 0x8192, 0xC470,
+	0x8193, 0xC471, 0x8194, 0xC472, 0x8195, 0xC473, 0x8196, 0xC474,	0x8197, 0xC475, 0x8198, 0xB1EC, 0x8199, 0xC476, 0x819A, 0xC477,
+	0x819B, 0xCCC5, 0x819C, 0xC4A4, 0x819D, 0xCFA5, 0x819E, 0xC478,	0x819F, 0xC479, 0x81A0, 0xC47A, 0x81A1, 0xC47B, 0x81A2, 0xC47C,
+	0x81A3, 0xEBF9, 0x81A4, 0xC47D, 0x81A5, 0xC47E, 0x81A6, 0xECA2,	0x81A7, 0xC480, 0x81A8, 0xC5F2, 0x81A9, 0xC481, 0x81AA, 0xEBFA,
+	0x81AB, 0xC482, 0x81AC, 0xC483, 0x81AD, 0xC484, 0x81AE, 0xC485,	0x81AF, 0xC486, 0x81B0, 0xC487, 0x81B1, 0xC488, 0x81B2, 0xC489,
+	0x81B3, 0xC9C5, 0x81B4, 0xC48A, 0x81B5, 0xC48B, 0x81B6, 0xC48C,	0x81B7, 0xC48D, 0x81B8, 0xC48E, 0x81B9, 0xC48F, 0x81BA, 0xE2DF,
+	0x81BB, 0xEBFE, 0x81BC, 0xC490, 0x81BD, 0xC491, 0x81BE, 0xC492,	0x81BF, 0xC493, 0x81C0, 0xCDCE, 0x81C1, 0xECA1, 0x81C2, 0xB1DB,
+	0x81C3, 0xD3B7, 0x81C4, 0xC494, 0x81C5, 0xC495, 0x81C6, 0xD2DC,	0x81C7, 0xC496, 0x81C8, 0xC497, 0x81C9, 0xC498, 0x81CA, 0xEBFD,
+	0x81CB, 0xC499, 0x81CC, 0xEBFB, 0x81CD, 0xC49A, 0x81CE, 0xC49B,	0x81CF, 0xC49C, 0x81D0, 0xC49D, 0x81D1, 0xC49E, 0x81D2, 0xC49F,
+	0x81D3, 0xC4A0, 0x81D4, 0xC540, 0x81D5, 0xC541, 0x81D6, 0xC542,	0x81D7, 0xC543, 0x81D8, 0xC544, 0x81D9, 0xC545, 0x81DA, 0xC546,
+	0x81DB, 0xC547, 0x81DC, 0xC548, 0x81DD, 0xC549, 0x81DE, 0xC54A,	0x81DF, 0xC54B, 0x81E0, 0xC54C, 0x81E1, 0xC54D, 0x81E2, 0xC54E,
+	0x81E3, 0xB3BC, 0x81E4, 0xC54F, 0x81E5, 0xC550, 0x81E6, 0xC551,	0x81E7, 0xEAB0, 0x81E8, 0xC552, 0x81E9, 0xC553, 0x81EA, 0xD7D4,
+	0x81EB, 0xC554, 0x81EC, 0xF4AB, 0x81ED, 0xB3F4, 0x81EE, 0xC555,	0x81EF, 0xC556, 0x81F0, 0xC557, 0x81F1, 0xC558, 0x81F2, 0xC559,
+	0x81F3, 0xD6C1, 0x81F4, 0xD6C2, 0x81F5, 0xC55A, 0x81F6, 0xC55B,	0x81F7, 0xC55C, 0x81F8, 0xC55D, 0x81F9, 0xC55E, 0x81FA, 0xC55F,
+	0x81FB, 0xD5E9, 0x81FC, 0xBECA, 0x81FD, 0xC560, 0x81FE, 0xF4A7,	0x81FF, 0xC561, 0x8200, 0xD2A8, 0x8201, 0xF4A8, 0x8202, 0xF4A9,
+	0x8203, 0xC562, 0x8204, 0xF4AA, 0x8205, 0xBECB, 0x8206, 0xD3DF,	0x8207, 0xC563, 0x8208, 0xC564, 0x8209, 0xC565, 0x820A, 0xC566,
+	0x820B, 0xC567, 0x820C, 0xC9E0, 0x820D, 0xC9E1, 0x820E, 0xC568,	0x820F, 0xC569, 0x8210, 0xF3C2, 0x8211, 0xC56A, 0x8212, 0xCAE6,
+	0x8213, 0xC56B, 0x8214, 0xCCF2, 0x8215, 0xC56C, 0x8216, 0xC56D,	0x8217, 0xC56E, 0x8218, 0xC56F, 0x8219, 0xC570, 0x821A, 0xC571,
+	0x821B, 0xE2B6, 0x821C, 0xCBB4, 0x821D, 0xC572, 0x821E, 0xCEE8,	0x821F, 0xD6DB, 0x8220, 0xC573, 0x8221, 0xF4AD, 0x8222, 0xF4AE,
+	0x8223, 0xF4AF, 0x8224, 0xC574, 0x8225, 0xC575, 0x8226, 0xC576,	0x8227, 0xC577, 0x8228, 0xF4B2, 0x8229, 0xC578, 0x822A, 0xBABD,
+	0x822B, 0xF4B3, 0x822C, 0xB0E3, 0x822D, 0xF4B0, 0x822E, 0xC579,	0x822F, 0xF4B1, 0x8230, 0xBDA2, 0x8231, 0xB2D5, 0x8232, 0xC57A,
+	0x8233, 0xF4B6, 0x8234, 0xF4B7, 0x8235, 0xB6E6, 0x8236, 0xB2B0,	0x8237, 0xCFCF, 0x8238, 0xF4B4, 0x8239, 0xB4AC, 0x823A, 0xC57B,
+	0x823B, 0xF4B5, 0x823C, 0xC57C, 0x823D, 0xC57D, 0x823E, 0xF4B8,	0x823F, 0xC57E, 0x8240, 0xC580, 0x8241, 0xC581, 0x8242, 0xC582,
+	0x8243, 0xC583, 0x8244, 0xF4B9, 0x8245, 0xC584, 0x8246, 0xC585,	0x8247, 0xCDA7, 0x8248, 0xC586, 0x8249, 0xF4BA, 0x824A, 0xC587,
+	0x824B, 0xF4BB, 0x824C, 0xC588, 0x824D, 0xC589, 0x824E, 0xC58A,	0x824F, 0xF4BC, 0x8250, 0xC58B, 0x8251, 0xC58C, 0x8252, 0xC58D,
+	0x8253, 0xC58E, 0x8254, 0xC58F, 0x8255, 0xC590, 0x8256, 0xC591,	0x8257, 0xC592, 0x8258, 0xCBD2, 0x8259, 0xC593, 0x825A, 0xF4BD,
+	0x825B, 0xC594, 0x825C, 0xC595, 0x825D, 0xC596, 0x825E, 0xC597,	0x825F, 0xF4BE, 0x8260, 0xC598, 0x8261, 0xC599, 0x8262, 0xC59A,
+	0x8263, 0xC59B, 0x8264, 0xC59C, 0x8265, 0xC59D, 0x8266, 0xC59E,	0x8267, 0xC59F, 0x8268, 0xF4BF, 0x8269, 0xC5A0, 0x826A, 0xC640,
+	0x826B, 0xC641, 0x826C, 0xC642, 0x826D, 0xC643, 0x826E, 0xF4DE,	0x826F, 0xC1BC, 0x8270, 0xBCE8, 0x8271, 0xC644, 0x8272, 0xC9AB,
+	0x8273, 0xD1DE, 0x8274, 0xE5F5, 0x8275, 0xC645, 0x8276, 0xC646,	0x8277, 0xC647, 0x8278, 0xC648, 0x8279, 0xDCB3, 0x827A, 0xD2D5,
+	0x827B, 0xC649, 0x827C, 0xC64A, 0x827D, 0xDCB4, 0x827E, 0xB0AC,	0x827F, 0xDCB5, 0x8280, 0xC64B, 0x8281, 0xC64C, 0x8282, 0xBDDA,
+	0x8283, 0xC64D, 0x8284, 0xDCB9, 0x8285, 0xC64E, 0x8286, 0xC64F,	0x8287, 0xC650, 0x8288, 0xD8C2, 0x8289, 0xC651, 0x828A, 0xDCB7,
+	0x828B, 0xD3F3, 0x828C, 0xC652, 0x828D, 0xC9D6, 0x828E, 0xDCBA,	0x828F, 0xDCB6, 0x8290, 0xC653, 0x8291, 0xDCBB, 0x8292, 0xC3A2,
+	0x8293, 0xC654, 0x8294, 0xC655, 0x8295, 0xC656, 0x8296, 0xC657,	0x8297, 0xDCBC, 0x8298, 0xDCC5, 0x8299, 0xDCBD, 0x829A, 0xC658,
+	0x829B, 0xC659, 0x829C, 0xCEDF, 0x829D, 0xD6A5, 0x829E, 0xC65A,	0x829F, 0xDCCF, 0x82A0, 0xC65B, 0x82A1, 0xDCCD, 0x82A2, 0xC65C,
+	0x82A3, 0xC65D, 0x82A4, 0xDCD2, 0x82A5, 0xBDE6, 0x82A6, 0xC2AB,	0x82A7, 0xC65E, 0x82A8, 0xDCB8, 0x82A9, 0xDCCB, 0x82AA, 0xDCCE,
+	0x82AB, 0xDCBE, 0x82AC, 0xB7D2, 0x82AD, 0xB0C5, 0x82AE, 0xDCC7,	0x82AF, 0xD0BE, 0x82B0, 0xDCC1, 0x82B1, 0xBBA8, 0x82B2, 0xC65F,
+	0x82B3, 0xB7BC, 0x82B4, 0xDCCC, 0x82B5, 0xC660, 0x82B6, 0xC661,	0x82B7, 0xDCC6, 0x82B8, 0xDCBF, 0x82B9, 0xC7DB, 0x82BA, 0xC662,
+	0x82BB, 0xC663, 0x82BC, 0xC664, 0x82BD, 0xD1BF, 0x82BE, 0xDCC0,	0x82BF, 0xC665, 0x82C0, 0xC666, 0x82C1, 0xDCCA, 0x82C2, 0xC667,
+	0x82C3, 0xC668, 0x82C4, 0xDCD0, 0x82C5, 0xC669, 0x82C6, 0xC66A,	0x82C7, 0xCEAD, 0x82C8, 0xDCC2, 0x82C9, 0xC66B, 0x82CA, 0xDCC3,
+	0x82CB, 0xDCC8, 0x82CC, 0xDCC9, 0x82CD, 0xB2D4, 0x82CE, 0xDCD1,	0x82CF, 0xCBD5, 0x82D0, 0xC66C, 0x82D1, 0xD4B7, 0x82D2, 0xDCDB,
+	0x82D3, 0xDCDF, 0x82D4, 0xCCA6, 0x82D5, 0xDCE6, 0x82D6, 0xC66D,	0x82D7, 0xC3E7, 0x82D8, 0xDCDC, 0x82D9, 0xC66E, 0x82DA, 0xC66F,
+	0x82DB, 0xBFC1, 0x82DC, 0xDCD9, 0x82DD, 0xC670, 0x82DE, 0xB0FA,	0x82DF, 0xB9B6, 0x82E0, 0xDCE5, 0x82E1, 0xDCD3, 0x82E2, 0xC671,
+	0x82E3, 0xDCC4, 0x82E4, 0xDCD6, 0x82E5, 0xC8F4, 0x82E6, 0xBFE0,	0x82E7, 0xC672, 0x82E8, 0xC673, 0x82E9, 0xC674, 0x82EA, 0xC675,
+	0x82EB, 0xC9BB, 0x82EC, 0xC676, 0x82ED, 0xC677, 0x82EE, 0xC678,	0x82EF, 0xB1BD, 0x82F0, 0xC679, 0x82F1, 0xD3A2, 0x82F2, 0xC67A,
+	0x82F3, 0xC67B, 0x82F4, 0xDCDA, 0x82F5, 0xC67C, 0x82F6, 0xC67D,	0x82F7, 0xDCD5, 0x82F8, 0xC67E, 0x82F9, 0xC6BB, 0x82FA, 0xC680,
+	0x82FB, 0xDCDE, 0x82FC, 0xC681, 0x82FD, 0xC682, 0x82FE, 0xC683,	0x82FF, 0xC684, 0x8300, 0xC685, 0x8301, 0xD7C2, 0x8302, 0xC3AF,
+	0x8303, 0xB7B6, 0x8304, 0xC7D1, 0x8305, 0xC3A9, 0x8306, 0xDCE2,	0x8307, 0xDCD8, 0x8308, 0xDCEB, 0x8309, 0xDCD4, 0x830A, 0xC686,
+	0x830B, 0xC687, 0x830C, 0xDCDD, 0x830D, 0xC688, 0x830E, 0xBEA5,	0x830F, 0xDCD7, 0x8310, 0xC689, 0x8311, 0xDCE0, 0x8312, 0xC68A,
+	0x8313, 0xC68B, 0x8314, 0xDCE3, 0x8315, 0xDCE4, 0x8316, 0xC68C,	0x8317, 0xDCF8, 0x8318, 0xC68D, 0x8319, 0xC68E, 0x831A, 0xDCE1,
+	0x831B, 0xDDA2, 0x831C, 0xDCE7, 0x831D, 0xC68F, 0x831E, 0xC690,	0x831F, 0xC691, 0x8320, 0xC692, 0x8321, 0xC693, 0x8322, 0xC694,
+	0x8323, 0xC695, 0x8324, 0xC696, 0x8325, 0xC697, 0x8326, 0xC698,	0x8327, 0xBCEB, 0x8328, 0xB4C4, 0x8329, 0xC699, 0x832A, 0xC69A,
+	0x832B, 0xC3A3, 0x832C, 0xB2E7, 0x832D, 0xDCFA, 0x832E, 0xC69B,	0x832F, 0xDCF2, 0x8330, 0xC69C, 0x8331, 0xDCEF, 0x8332, 0xC69D,
+	0x8333, 0xDCFC, 0x8334, 0xDCEE, 0x8335, 0xD2F0, 0x8336, 0xB2E8,	0x8337, 0xC69E, 0x8338, 0xC8D7, 0x8339, 0xC8E3, 0x833A, 0xDCFB,
+	0x833B, 0xC69F, 0x833C, 0xDCED, 0x833D, 0xC6A0, 0x833E, 0xC740,	0x833F, 0xC741, 0x8340, 0xDCF7, 0x8341, 0xC742, 0x8342, 0xC743,
+	0x8343, 0xDCF5, 0x8344, 0xC744, 0x8345, 0xC745, 0x8346, 0xBEA3,	0x8347, 0xDCF4, 0x8348, 0xC746, 0x8349, 0xB2DD, 0x834A, 0xC747,
+	0x834B, 0xC748, 0x834C, 0xC749, 0x834D, 0xC74A, 0x834E, 0xC74B,	0x834F, 0xDCF3, 0x8350, 0xBCF6, 0x8351, 0xDCE8, 0x8352, 0xBBC4,
+	0x8353, 0xC74C, 0x8354, 0xC0F3, 0x8355, 0xC74D, 0x8356, 0xC74E,	0x8357, 0xC74F, 0x8358, 0xC750, 0x8359, 0xC751, 0x835A, 0xBCD4,
+	0x835B, 0xDCE9, 0x835C, 0xDCEA, 0x835D, 0xC752, 0x835E, 0xDCF1,	0x835F, 0xDCF6, 0x8360, 0xDCF9, 0x8361, 0xB5B4, 0x8362, 0xC753,
+	0x8363, 0xC8D9, 0x8364, 0xBBE7, 0x8365, 0xDCFE, 0x8366, 0xDCFD,	0x8367, 0xD3AB, 0x8368, 0xDDA1, 0x8369, 0xDDA3, 0x836A, 0xDDA5,
+	0x836B, 0xD2F1, 0x836C, 0xDDA4, 0x836D, 0xDDA6, 0x836E, 0xDDA7,	0x836F, 0xD2A9, 0x8370, 0xC754, 0x8371, 0xC755, 0x8372, 0xC756,
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+	0x837B, 0xDDB6, 0x837C, 0xDDB1, 0x837D, 0xDDB4, 0x837E, 0xC75D,	0x837F, 0xC75E, 0x8380, 0xC75F, 0x8381, 0xC760, 0x8382, 0xC761,
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+	0x8393, 0xDDAE, 0x8394, 0xC76D, 0x8395, 0xC76E, 0x8396, 0xC76F,	0x8397, 0xC770, 0x8398, 0xDDB7, 0x8399, 0xC771, 0x839A, 0xC772,
+	0x839B, 0xDCF0, 0x839C, 0xDDAF, 0x839D, 0xC773, 0x839E, 0xDDB8,	0x839F, 0xC774, 0x83A0, 0xDDAC, 0x83A1, 0xC775, 0x83A2, 0xC776,
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+	0x83AB, 0xC4AA, 0x83AC, 0xC77C, 0x83AD, 0xC77D, 0x83AE, 0xC77E,	0x83AF, 0xC780, 0x83B0, 0xDDA8, 0x83B1, 0xC0B3, 0x83B2, 0xC1AB,
+	0x83B3, 0xDDAA, 0x83B4, 0xDDAB, 0x83B5, 0xC781, 0x83B6, 0xDDB2,	0x83B7, 0xBBF1, 0x83B8, 0xDDB5, 0x83B9, 0xD3A8, 0x83BA, 0xDDBA,
+	0x83BB, 0xC782, 0x83BC, 0xDDBB, 0x83BD, 0xC3A7, 0x83BE, 0xC783,	0x83BF, 0xC784, 0x83C0, 0xDDD2, 0x83C1, 0xDDBC, 0x83C2, 0xC785,
+	0x83C3, 0xC786, 0x83C4, 0xC787, 0x83C5, 0xDDD1, 0x83C6, 0xC788,	0x83C7, 0xB9BD, 0x83C8, 0xC789, 0x83C9, 0xC78A, 0x83CA, 0xBED5,
+	0x83CB, 0xC78B, 0x83CC, 0xBEFA, 0x83CD, 0xC78C, 0x83CE, 0xC78D,	0x83CF, 0xBACA, 0x83D0, 0xC78E, 0x83D1, 0xC78F, 0x83D2, 0xC790,
+	0x83D3, 0xC791, 0x83D4, 0xDDCA, 0x83D5, 0xC792, 0x83D6, 0xDDC5,	0x83D7, 0xC793, 0x83D8, 0xDDBF, 0x83D9, 0xC794, 0x83DA, 0xC795,
+	0x83DB, 0xC796, 0x83DC, 0xB2CB, 0x83DD, 0xDDC3, 0x83DE, 0xC797,	0x83DF, 0xDDCB, 0x83E0, 0xB2A4, 0x83E1, 0xDDD5, 0x83E2, 0xC798,
+	0x83E3, 0xC799, 0x83E4, 0xC79A, 0x83E5, 0xDDBE, 0x83E6, 0xC79B,	0x83E7, 0xC79C, 0x83E8, 0xC79D, 0x83E9, 0xC6D0, 0x83EA, 0xDDD0,
+	0x83EB, 0xC79E, 0x83EC, 0xC79F, 0x83ED, 0xC7A0, 0x83EE, 0xC840,	0x83EF, 0xC841, 0x83F0, 0xDDD4, 0x83F1, 0xC1E2, 0x83F2, 0xB7C6,
+	0x83F3, 0xC842, 0x83F4, 0xC843, 0x83F5, 0xC844, 0x83F6, 0xC845,	0x83F7, 0xC846, 0x83F8, 0xDDCE, 0x83F9, 0xDDCF, 0x83FA, 0xC847,
+	0x83FB, 0xC848, 0x83FC, 0xC849, 0x83FD, 0xDDC4, 0x83FE, 0xC84A,	0x83FF, 0xC84B, 0x8400, 0xC84C, 0x8401, 0xDDBD, 0x8402, 0xC84D,
+	0x8403, 0xDDCD, 0x8404, 0xCCD1, 0x8405, 0xC84E, 0x8406, 0xDDC9,	0x8407, 0xC84F, 0x8408, 0xC850, 0x8409, 0xC851, 0x840A, 0xC852,
+	0x840B, 0xDDC2, 0x840C, 0xC3C8, 0x840D, 0xC6BC, 0x840E, 0xCEAE,	0x840F, 0xDDCC, 0x8410, 0xC853, 0x8411, 0xDDC8, 0x8412, 0xC854,
+	0x8413, 0xC855, 0x8414, 0xC856, 0x8415, 0xC857, 0x8416, 0xC858,	0x8417, 0xC859, 0x8418, 0xDDC1, 0x8419, 0xC85A, 0x841A, 0xC85B,
+	0x841B, 0xC85C, 0x841C, 0xDDC6, 0x841D, 0xC2DC, 0x841E, 0xC85D,	0x841F, 0xC85E, 0x8420, 0xC85F, 0x8421, 0xC860, 0x8422, 0xC861,
+	0x8423, 0xC862, 0x8424, 0xD3A9, 0x8425, 0xD3AA, 0x8426, 0xDDD3,	0x8427, 0xCFF4, 0x8428, 0xC8F8, 0x8429, 0xC863, 0x842A, 0xC864,
+	0x842B, 0xC865, 0x842C, 0xC866, 0x842D, 0xC867, 0x842E, 0xC868,	0x842F, 0xC869, 0x8430, 0xC86A, 0x8431, 0xDDE6, 0x8432, 0xC86B,
+	0x8433, 0xC86C, 0x8434, 0xC86D, 0x8435, 0xC86E, 0x8436, 0xC86F,	0x8437, 0xC870, 0x8438, 0xDDC7, 0x8439, 0xC871, 0x843A, 0xC872,
+	0x843B, 0xC873, 0x843C, 0xDDE0, 0x843D, 0xC2E4, 0x843E, 0xC874,	0x843F, 0xC875, 0x8440, 0xC876, 0x8441, 0xC877, 0x8442, 0xC878,
+	0x8443, 0xC879, 0x8444, 0xC87A, 0x8445, 0xC87B, 0x8446, 0xDDE1,	0x8447, 0xC87C, 0x8448, 0xC87D, 0x8449, 0xC87E, 0x844A, 0xC880,
+	0x844B, 0xC881, 0x844C, 0xC882, 0x844D, 0xC883, 0x844E, 0xC884,	0x844F, 0xC885, 0x8450, 0xC886, 0x8451, 0xDDD7, 0x8452, 0xC887,
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+	0x845B, 0xB8F0, 0x845C, 0xDDD6, 0x845D, 0xC88D, 0x845E, 0xC88E,	0x845F, 0xC88F, 0x8460, 0xC890, 0x8461, 0xC6CF, 0x8462, 0xC891,
+	0x8463, 0xB6AD, 0x8464, 0xC892, 0x8465, 0xC893, 0x8466, 0xC894,	0x8467, 0xC895, 0x8468, 0xC896, 0x8469, 0xDDE2, 0x846A, 0xC897,
+	0x846B, 0xBAF9, 0x846C, 0xD4E1, 0x846D, 0xDDE7, 0x846E, 0xC898,	0x846F, 0xC899, 0x8470, 0xC89A, 0x8471, 0xB4D0, 0x8472, 0xC89B,
+	0x8473, 0xDDDA, 0x8474, 0xC89C, 0x8475, 0xBFFB, 0x8476, 0xDDE3,	0x8477, 0xC89D, 0x8478, 0xDDDF, 0x8479, 0xC89E, 0x847A, 0xDDDD,
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+	0x8483, 0xC945, 0x8484, 0xC946, 0x8485, 0xC947, 0x8486, 0xC948,	0x8487, 0xDDDB, 0x8488, 0xDDDC, 0x8489, 0xDDDE, 0x848A, 0xC949,
+	0x848B, 0xBDAF, 0x848C, 0xDDE4, 0x848D, 0xC94A, 0x848E, 0xDDE5,	0x848F, 0xC94B, 0x8490, 0xC94C, 0x8491, 0xC94D, 0x8492, 0xC94E,
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+	0x84AB, 0xC963, 0x84AC, 0xC964, 0x84AD, 0xC965, 0x84AE, 0xC966,	0x84AF, 0xD8E1, 0x84B0, 0xC967, 0x84B1, 0xC968, 0x84B2, 0xC6D1,
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+	0x8593, 0xCB4D, 0x8594, 0xCB4E, 0x8595, 0xCB4F, 0x8596, 0xCB50,	0x8597, 0xCB51, 0x8598, 0xCB52, 0x8599, 0xCB53, 0x859A, 0xCB54,
+	0x859B, 0xD1A6, 0x859C, 0xDEB5, 0x859D, 0xCB55, 0x859E, 0xCB56,	0x859F, 0xCB57, 0x85A0, 0xCB58, 0x85A1, 0xCB59, 0x85A2, 0xCB5A,
+	0x85A3, 0xCB5B, 0x85A4, 0xDEAF, 0x85A5, 0xCB5C, 0x85A6, 0xCB5D,	0x85A7, 0xCB5E, 0x85A8, 0xDEB0, 0x85A9, 0xCB5F, 0x85AA, 0xD0BD,
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+	0x85B3, 0xCB65, 0x85B4, 0xCB66, 0x85B5, 0xCB67, 0x85B6, 0xCB68,	0x85B7, 0xDEB8, 0x85B8, 0xCB69, 0x85B9, 0xDEB7, 0x85BA, 0xCB6A,
+	0x85BB, 0xCB6B, 0x85BC, 0xCB6C, 0x85BD, 0xCB6D, 0x85BE, 0xCB6E,	0x85BF, 0xCB6F, 0x85C0, 0xCB70, 0x85C1, 0xDEBB, 0x85C2, 0xCB71,
+	0x85C3, 0xCB72, 0x85C4, 0xCB73, 0x85C5, 0xCB74, 0x85C6, 0xCB75,	0x85C7, 0xCB76, 0x85C8, 0xCB77, 0x85C9, 0xBDE5, 0x85CA, 0xCB78,
+	0x85CB, 0xCB79, 0x85CC, 0xCB7A, 0x85CD, 0xCB7B, 0x85CE, 0xCB7C,	0x85CF, 0xB2D8, 0x85D0, 0xC3EA, 0x85D1, 0xCB7D, 0x85D2, 0xCB7E,
+	0x85D3, 0xDEBA, 0x85D4, 0xCB80, 0x85D5, 0xC5BA, 0x85D6, 0xCB81,	0x85D7, 0xCB82, 0x85D8, 0xCB83, 0x85D9, 0xCB84, 0x85DA, 0xCB85,
+	0x85DB, 0xCB86, 0x85DC, 0xDEBC, 0x85DD, 0xCB87, 0x85DE, 0xCB88,	0x85DF, 0xCB89, 0x85E0, 0xCB8A, 0x85E1, 0xCB8B, 0x85E2, 0xCB8C,
+	0x85E3, 0xCB8D, 0x85E4, 0xCCD9, 0x85E5, 0xCB8E, 0x85E6, 0xCB8F,	0x85E7, 0xCB90, 0x85E8, 0xCB91, 0x85E9, 0xB7AA, 0x85EA, 0xCB92,
+	0x85EB, 0xCB93, 0x85EC, 0xCB94, 0x85ED, 0xCB95, 0x85EE, 0xCB96,	0x85EF, 0xCB97, 0x85F0, 0xCB98, 0x85F1, 0xCB99, 0x85F2, 0xCB9A,
+	0x85F3, 0xCB9B, 0x85F4, 0xCB9C, 0x85F5, 0xCB9D, 0x85F6, 0xCB9E,	0x85F7, 0xCB9F, 0x85F8, 0xCBA0, 0x85F9, 0xCC40, 0x85FA, 0xCC41,
+	0x85FB, 0xD4E5, 0x85FC, 0xCC42, 0x85FD, 0xCC43, 0x85FE, 0xCC44,	0x85FF, 0xDEBD, 0x8600, 0xCC45, 0x8601, 0xCC46, 0x8602, 0xCC47,
+	0x8603, 0xCC48, 0x8604, 0xCC49, 0x8605, 0xDEBF, 0x8606, 0xCC4A,	0x8607, 0xCC4B, 0x8608, 0xCC4C, 0x8609, 0xCC4D, 0x860A, 0xCC4E,
+	0x860B, 0xCC4F, 0x860C, 0xCC50, 0x860D, 0xCC51, 0x860E, 0xCC52,	0x860F, 0xCC53, 0x8610, 0xCC54, 0x8611, 0xC4A2, 0x8612, 0xCC55,
+	0x8613, 0xCC56, 0x8614, 0xCC57, 0x8615, 0xCC58, 0x8616, 0xDEC1,	0x8617, 0xCC59, 0x8618, 0xCC5A, 0x8619, 0xCC5B, 0x861A, 0xCC5C,
+	0x861B, 0xCC5D, 0x861C, 0xCC5E, 0x861D, 0xCC5F, 0x861E, 0xCC60,	0x861F, 0xCC61, 0x8620, 0xCC62, 0x8621, 0xCC63, 0x8622, 0xCC64,
+	0x8623, 0xCC65, 0x8624, 0xCC66, 0x8625, 0xCC67, 0x8626, 0xCC68,	0x8627, 0xDEBE, 0x8628, 0xCC69, 0x8629, 0xDEC0, 0x862A, 0xCC6A,
+	0x862B, 0xCC6B, 0x862C, 0xCC6C, 0x862D, 0xCC6D, 0x862E, 0xCC6E,	0x862F, 0xCC6F, 0x8630, 0xCC70, 0x8631, 0xCC71, 0x8632, 0xCC72,
+	0x8633, 0xCC73, 0x8634, 0xCC74, 0x8635, 0xCC75, 0x8636, 0xCC76,	0x8637, 0xCC77, 0x8638, 0xD5BA, 0x8639, 0xCC78, 0x863A, 0xCC79,
+	0x863B, 0xCC7A, 0x863C, 0xDEC2, 0x863D, 0xCC7B, 0x863E, 0xCC7C,	0x863F, 0xCC7D, 0x8640, 0xCC7E, 0x8641, 0xCC80, 0x8642, 0xCC81,
+	0x8643, 0xCC82, 0x8644, 0xCC83, 0x8645, 0xCC84, 0x8646, 0xCC85,	0x8647, 0xCC86, 0x8648, 0xCC87, 0x8649, 0xCC88, 0x864A, 0xCC89,
+	0x864B, 0xCC8A, 0x864C, 0xCC8B, 0x864D, 0xF2AE, 0x864E, 0xBBA2,	0x864F, 0xC2B2, 0x8650, 0xC5B0, 0x8651, 0xC2C7, 0x8652, 0xCC8C,
+	0x8653, 0xCC8D, 0x8654, 0xF2AF, 0x8655, 0xCC8E, 0x8656, 0xCC8F,	0x8657, 0xCC90, 0x8658, 0xCC91, 0x8659, 0xCC92, 0x865A, 0xD0E9,
+	0x865B, 0xCC93, 0x865C, 0xCC94, 0x865D, 0xCC95, 0x865E, 0xD3DD,	0x865F, 0xCC96, 0x8660, 0xCC97, 0x8661, 0xCC98, 0x8662, 0xEBBD,
+	0x8663, 0xCC99, 0x8664, 0xCC9A, 0x8665, 0xCC9B, 0x8666, 0xCC9C,	0x8667, 0xCC9D, 0x8668, 0xCC9E, 0x8669, 0xCC9F, 0x866A, 0xCCA0,
+	0x866B, 0xB3E6, 0x866C, 0xF2B0, 0x866D, 0xCD40, 0x866E, 0xF2B1,	0x866F, 0xCD41, 0x8670, 0xCD42, 0x8671, 0xCAAD, 0x8672, 0xCD43,
+	0x8673, 0xCD44, 0x8674, 0xCD45, 0x8675, 0xCD46, 0x8676, 0xCD47,	0x8677, 0xCD48, 0x8678, 0xCD49, 0x8679, 0xBAE7, 0x867A, 0xF2B3,
+	0x867B, 0xF2B5, 0x867C, 0xF2B4, 0x867D, 0xCBE4, 0x867E, 0xCFBA,	0x867F, 0xF2B2, 0x8680, 0xCAB4, 0x8681, 0xD2CF, 0x8682, 0xC2EC,
+	0x8683, 0xCD4A, 0x8684, 0xCD4B, 0x8685, 0xCD4C, 0x8686, 0xCD4D,	0x8687, 0xCD4E, 0x8688, 0xCD4F, 0x8689, 0xCD50, 0x868A, 0xCEC3,
+	0x868B, 0xF2B8, 0x868C, 0xB0F6, 0x868D, 0xF2B7, 0x868E, 0xCD51,	0x868F, 0xCD52, 0x8690, 0xCD53, 0x8691, 0xCD54, 0x8692, 0xCD55,
+	0x8693, 0xF2BE, 0x8694, 0xCD56, 0x8695, 0xB2CF, 0x8696, 0xCD57,	0x8697, 0xCD58, 0x8698, 0xCD59, 0x8699, 0xCD5A, 0x869A, 0xCD5B,
+	0x869B, 0xCD5C, 0x869C, 0xD1C1, 0x869D, 0xF2BA, 0x869E, 0xCD5D,	0x869F, 0xCD5E, 0x86A0, 0xCD5F, 0x86A1, 0xCD60, 0x86A2, 0xCD61,
+	0x86A3, 0xF2BC, 0x86A4, 0xD4E9, 0x86A5, 0xCD62, 0x86A6, 0xCD63,	0x86A7, 0xF2BB, 0x86A8, 0xF2B6, 0x86A9, 0xF2BF, 0x86AA, 0xF2BD,
+	0x86AB, 0xCD64, 0x86AC, 0xF2B9, 0x86AD, 0xCD65, 0x86AE, 0xCD66,	0x86AF, 0xF2C7, 0x86B0, 0xF2C4, 0x86B1, 0xF2C6, 0x86B2, 0xCD67,
+	0x86B3, 0xCD68, 0x86B4, 0xF2CA, 0x86B5, 0xF2C2, 0x86B6, 0xF2C0,	0x86B7, 0xCD69, 0x86B8, 0xCD6A, 0x86B9, 0xCD6B, 0x86BA, 0xF2C5,
+	0x86BB, 0xCD6C, 0x86BC, 0xCD6D, 0x86BD, 0xCD6E, 0x86BE, 0xCD6F,	0x86BF, 0xCD70, 0x86C0, 0xD6FB, 0x86C1, 0xCD71, 0x86C2, 0xCD72,
+	0x86C3, 0xCD73, 0x86C4, 0xF2C1, 0x86C5, 0xCD74, 0x86C6, 0xC7F9,	0x86C7, 0xC9DF, 0x86C8, 0xCD75, 0x86C9, 0xF2C8, 0x86CA, 0xB9C6,
+	0x86CB, 0xB5B0, 0x86CC, 0xCD76, 0x86CD, 0xCD77, 0x86CE, 0xF2C3,	0x86CF, 0xF2C9, 0x86D0, 0xF2D0, 0x86D1, 0xF2D6, 0x86D2, 0xCD78,
+	0x86D3, 0xCD79, 0x86D4, 0xBBD7, 0x86D5, 0xCD7A, 0x86D6, 0xCD7B,	0x86D7, 0xCD7C, 0x86D8, 0xF2D5, 0x86D9, 0xCDDC, 0x86DA, 0xCD7D,
+	0x86DB, 0xD6EB, 0x86DC, 0xCD7E, 0x86DD, 0xCD80, 0x86DE, 0xF2D2,	0x86DF, 0xF2D4, 0x86E0, 0xCD81, 0x86E1, 0xCD82, 0x86E2, 0xCD83,
+	0x86E3, 0xCD84, 0x86E4, 0xB8F2, 0x86E5, 0xCD85, 0x86E6, 0xCD86,	0x86E7, 0xCD87, 0x86E8, 0xCD88, 0x86E9, 0xF2CB, 0x86EA, 0xCD89,
+	0x86EB, 0xCD8A, 0x86EC, 0xCD8B, 0x86ED, 0xF2CE, 0x86EE, 0xC2F9,	0x86EF, 0xCD8C, 0x86F0, 0xD5DD, 0x86F1, 0xF2CC, 0x86F2, 0xF2CD,
+	0x86F3, 0xF2CF, 0x86F4, 0xF2D3, 0x86F5, 0xCD8D, 0x86F6, 0xCD8E,	0x86F7, 0xCD8F, 0x86F8, 0xF2D9, 0x86F9, 0xD3BC, 0x86FA, 0xCD90,
+	0x86FB, 0xCD91, 0x86FC, 0xCD92, 0x86FD, 0xCD93, 0x86FE, 0xB6EA,	0x86FF, 0xCD94, 0x8700, 0xCAF1, 0x8701, 0xCD95, 0x8702, 0xB7E4,
+	0x8703, 0xF2D7, 0x8704, 0xCD96, 0x8705, 0xCD97, 0x8706, 0xCD98,	0x8707, 0xF2D8, 0x8708, 0xF2DA, 0x8709, 0xF2DD, 0x870A, 0xF2DB,
+	0x870B, 0xCD99, 0x870C, 0xCD9A, 0x870D, 0xF2DC, 0x870E, 0xCD9B,	0x870F, 0xCD9C, 0x8710, 0xCD9D, 0x8711, 0xCD9E, 0x8712, 0xD1D1,
+	0x8713, 0xF2D1, 0x8714, 0xCD9F, 0x8715, 0xCDC9, 0x8716, 0xCDA0,	0x8717, 0xCECF, 0x8718, 0xD6A9, 0x8719, 0xCE40, 0x871A, 0xF2E3,
+	0x871B, 0xCE41, 0x871C, 0xC3DB, 0x871D, 0xCE42, 0x871E, 0xF2E0,	0x871F, 0xCE43, 0x8720, 0xCE44, 0x8721, 0xC0AF, 0x8722, 0xF2EC,
+	0x8723, 0xF2DE, 0x8724, 0xCE45, 0x8725, 0xF2E1, 0x8726, 0xCE46,	0x8727, 0xCE47, 0x8728, 0xCE48, 0x8729, 0xF2E8, 0x872A, 0xCE49,
+	0x872B, 0xCE4A, 0x872C, 0xCE4B, 0x872D, 0xCE4C, 0x872E, 0xF2E2,	0x872F, 0xCE4D, 0x8730, 0xCE4E, 0x8731, 0xF2E7, 0x8732, 0xCE4F,
+	0x8733, 0xCE50, 0x8734, 0xF2E6, 0x8735, 0xCE51, 0x8736, 0xCE52,	0x8737, 0xF2E9, 0x8738, 0xCE53, 0x8739, 0xCE54, 0x873A, 0xCE55,
+	0x873B, 0xF2DF, 0x873C, 0xCE56, 0x873D, 0xCE57, 0x873E, 0xF2E4,	0x873F, 0xF2EA, 0x8740, 0xCE58, 0x8741, 0xCE59, 0x8742, 0xCE5A,
+	0x8743, 0xCE5B, 0x8744, 0xCE5C, 0x8745, 0xCE5D, 0x8746, 0xCE5E,	0x8747, 0xD3AC, 0x8748, 0xF2E5, 0x8749, 0xB2F5, 0x874A, 0xCE5F,
+	0x874B, 0xCE60, 0x874C, 0xF2F2, 0x874D, 0xCE61, 0x874E, 0xD0AB,	0x874F, 0xCE62, 0x8750, 0xCE63, 0x8751, 0xCE64, 0x8752, 0xCE65,
+	0x8753, 0xF2F5, 0x8754, 0xCE66, 0x8755, 0xCE67, 0x8756, 0xCE68,	0x8757, 0xBBC8, 0x8758, 0xCE69, 0x8759, 0xF2F9, 0x875A, 0xCE6A,
+	0x875B, 0xCE6B, 0x875C, 0xCE6C, 0x875D, 0xCE6D, 0x875E, 0xCE6E,	0x875F, 0xCE6F, 0x8760, 0xF2F0, 0x8761, 0xCE70, 0x8762, 0xCE71,
+	0x8763, 0xF2F6, 0x8764, 0xF2F8, 0x8765, 0xF2FA, 0x8766, 0xCE72,	0x8767, 0xCE73, 0x8768, 0xCE74, 0x8769, 0xCE75, 0x876A, 0xCE76,
+	0x876B, 0xCE77, 0x876C, 0xCE78, 0x876D, 0xCE79, 0x876E, 0xF2F3,	0x876F, 0xCE7A, 0x8770, 0xF2F1, 0x8771, 0xCE7B, 0x8772, 0xCE7C,
+	0x8773, 0xCE7D, 0x8774, 0xBAFB, 0x8775, 0xCE7E, 0x8776, 0xB5FB,	0x8777, 0xCE80, 0x8778, 0xCE81, 0x8779, 0xCE82, 0x877A, 0xCE83,
+	0x877B, 0xF2EF, 0x877C, 0xF2F7, 0x877D, 0xF2ED, 0x877E, 0xF2EE,	0x877F, 0xCE84, 0x8780, 0xCE85, 0x8781, 0xCE86, 0x8782, 0xF2EB,
+	0x8783, 0xF3A6, 0x8784, 0xCE87, 0x8785, 0xF3A3, 0x8786, 0xCE88,	0x8787, 0xCE89, 0x8788, 0xF3A2, 0x8789, 0xCE8A, 0x878A, 0xCE8B,
+	0x878B, 0xF2F4, 0x878C, 0xCE8C, 0x878D, 0xC8DA, 0x878E, 0xCE8D,	0x878F, 0xCE8E, 0x8790, 0xCE8F, 0x8791, 0xCE90, 0x8792, 0xCE91,
+	0x8793, 0xF2FB, 0x8794, 0xCE92, 0x8795, 0xCE93, 0x8796, 0xCE94,	0x8797, 0xF3A5, 0x8798, 0xCE95, 0x8799, 0xCE96, 0x879A, 0xCE97,
+	0x879B, 0xCE98, 0x879C, 0xCE99, 0x879D, 0xCE9A, 0x879E, 0xCE9B,	0x879F, 0xC3F8, 0x87A0, 0xCE9C, 0x87A1, 0xCE9D, 0x87A2, 0xCE9E,
+	0x87A3, 0xCE9F, 0x87A4, 0xCEA0, 0x87A5, 0xCF40, 0x87A6, 0xCF41,	0x87A7, 0xCF42, 0x87A8, 0xF2FD, 0x87A9, 0xCF43, 0x87AA, 0xCF44,
+	0x87AB, 0xF3A7, 0x87AC, 0xF3A9, 0x87AD, 0xF3A4, 0x87AE, 0xCF45,	0x87AF, 0xF2FC, 0x87B0, 0xCF46, 0x87B1, 0xCF47, 0x87B2, 0xCF48,
+	0x87B3, 0xF3AB, 0x87B4, 0xCF49, 0x87B5, 0xF3AA, 0x87B6, 0xCF4A,	0x87B7, 0xCF4B, 0x87B8, 0xCF4C, 0x87B9, 0xCF4D, 0x87BA, 0xC2DD,
+	0x87BB, 0xCF4E, 0x87BC, 0xCF4F, 0x87BD, 0xF3AE, 0x87BE, 0xCF50,	0x87BF, 0xCF51, 0x87C0, 0xF3B0, 0x87C1, 0xCF52, 0x87C2, 0xCF53,
+	0x87C3, 0xCF54, 0x87C4, 0xCF55, 0x87C5, 0xCF56, 0x87C6, 0xF3A1,	0x87C7, 0xCF57, 0x87C8, 0xCF58, 0x87C9, 0xCF59, 0x87CA, 0xF3B1,
+	0x87CB, 0xF3AC, 0x87CC, 0xCF5A, 0x87CD, 0xCF5B, 0x87CE, 0xCF5C,	0x87CF, 0xCF5D, 0x87D0, 0xCF5E, 0x87D1, 0xF3AF, 0x87D2, 0xF2FE,
+	0x87D3, 0xF3AD, 0x87D4, 0xCF5F, 0x87D5, 0xCF60, 0x87D6, 0xCF61,	0x87D7, 0xCF62, 0x87D8, 0xCF63, 0x87D9, 0xCF64, 0x87DA, 0xCF65,
+	0x87DB, 0xF3B2, 0x87DC, 0xCF66, 0x87DD, 0xCF67, 0x87DE, 0xCF68,	0x87DF, 0xCF69, 0x87E0, 0xF3B4, 0x87E1, 0xCF6A, 0x87E2, 0xCF6B,
+	0x87E3, 0xCF6C, 0x87E4, 0xCF6D, 0x87E5, 0xF3A8, 0x87E6, 0xCF6E,	0x87E7, 0xCF6F, 0x87E8, 0xCF70, 0x87E9, 0xCF71, 0x87EA, 0xF3B3,
+	0x87EB, 0xCF72, 0x87EC, 0xCF73, 0x87ED, 0xCF74, 0x87EE, 0xF3B5,	0x87EF, 0xCF75, 0x87F0, 0xCF76, 0x87F1, 0xCF77, 0x87F2, 0xCF78,
+	0x87F3, 0xCF79, 0x87F4, 0xCF7A, 0x87F5, 0xCF7B, 0x87F6, 0xCF7C,	0x87F7, 0xCF7D, 0x87F8, 0xCF7E, 0x87F9, 0xD0B7, 0x87FA, 0xCF80,
+	0x87FB, 0xCF81, 0x87FC, 0xCF82, 0x87FD, 0xCF83, 0x87FE, 0xF3B8,	0x87FF, 0xCF84, 0x8800, 0xCF85, 0x8801, 0xCF86, 0x8802, 0xCF87,
+	0x8803, 0xD9F9, 0x8804, 0xCF88, 0x8805, 0xCF89, 0x8806, 0xCF8A,	0x8807, 0xCF8B, 0x8808, 0xCF8C, 0x8809, 0xCF8D, 0x880A, 0xF3B9,
+	0x880B, 0xCF8E, 0x880C, 0xCF8F, 0x880D, 0xCF90, 0x880E, 0xCF91,	0x880F, 0xCF92, 0x8810, 0xCF93, 0x8811, 0xCF94, 0x8812, 0xCF95,
+	0x8813, 0xF3B7, 0x8814, 0xCF96, 0x8815, 0xC8E4, 0x8816, 0xF3B6,	0x8817, 0xCF97, 0x8818, 0xCF98, 0x8819, 0xCF99, 0x881A, 0xCF9A,
+	0x881B, 0xF3BA, 0x881C, 0xCF9B, 0x881D, 0xCF9C, 0x881E, 0xCF9D,	0x881F, 0xCF9E, 0x8820, 0xCF9F, 0x8821, 0xF3BB, 0x8822, 0xB4C0,
+	0x8823, 0xCFA0, 0x8824, 0xD040, 0x8825, 0xD041, 0x8826, 0xD042,	0x8827, 0xD043, 0x8828, 0xD044, 0x8829, 0xD045, 0x882A, 0xD046,
+	0x882B, 0xD047, 0x882C, 0xD048, 0x882D, 0xD049, 0x882E, 0xD04A,	0x882F, 0xD04B, 0x8830, 0xD04C, 0x8831, 0xD04D, 0x8832, 0xEEC3,
+	0x8833, 0xD04E, 0x8834, 0xD04F, 0x8835, 0xD050, 0x8836, 0xD051,	0x8837, 0xD052, 0x8838, 0xD053, 0x8839, 0xF3BC, 0x883A, 0xD054,
+	0x883B, 0xD055, 0x883C, 0xF3BD, 0x883D, 0xD056, 0x883E, 0xD057,	0x883F, 0xD058, 0x8840, 0xD1AA, 0x8841, 0xD059, 0x8842, 0xD05A,
+	0x8843, 0xD05B, 0x8844, 0xF4AC, 0x8845, 0xD0C6, 0x8846, 0xD05C,	0x8847, 0xD05D, 0x8848, 0xD05E, 0x8849, 0xD05F, 0x884A, 0xD060,
+	0x884B, 0xD061, 0x884C, 0xD0D0, 0x884D, 0xD1DC, 0x884E, 0xD062,	0x884F, 0xD063, 0x8850, 0xD064, 0x8851, 0xD065, 0x8852, 0xD066,
+	0x8853, 0xD067, 0x8854, 0xCFCE, 0x8855, 0xD068, 0x8856, 0xD069,	0x8857, 0xBDD6, 0x8858, 0xD06A, 0x8859, 0xD1C3, 0x885A, 0xD06B,
+	0x885B, 0xD06C, 0x885C, 0xD06D, 0x885D, 0xD06E, 0x885E, 0xD06F,	0x885F, 0xD070, 0x8860, 0xD071, 0x8861, 0xBAE2, 0x8862, 0xE1E9,
+	0x8863, 0xD2C2, 0x8864, 0xF1C2, 0x8865, 0xB2B9, 0x8866, 0xD072,	0x8867, 0xD073, 0x8868, 0xB1ED, 0x8869, 0xF1C3, 0x886A, 0xD074,
+	0x886B, 0xC9C0, 0x886C, 0xB3C4, 0x886D, 0xD075, 0x886E, 0xD9F2,	0x886F, 0xD076, 0x8870, 0xCBA5, 0x8871, 0xD077, 0x8872, 0xF1C4,
+	0x8873, 0xD078, 0x8874, 0xD079, 0x8875, 0xD07A, 0x8876, 0xD07B,	0x8877, 0xD6D4, 0x8878, 0xD07C, 0x8879, 0xD07D, 0x887A, 0xD07E,
+	0x887B, 0xD080, 0x887C, 0xD081, 0x887D, 0xF1C5, 0x887E, 0xF4C0,	0x887F, 0xF1C6, 0x8880, 0xD082, 0x8881, 0xD4AC, 0x8882, 0xF1C7,
+	0x8883, 0xD083, 0x8884, 0xB0C0, 0x8885, 0xF4C1, 0x8886, 0xD084,	0x8887, 0xD085, 0x8888, 0xF4C2, 0x8889, 0xD086, 0x888A, 0xD087,
+	0x888B, 0xB4FC, 0x888C, 0xD088, 0x888D, 0xC5DB, 0x888E, 0xD089,	0x888F, 0xD08A, 0x8890, 0xD08B, 0x8891, 0xD08C, 0x8892, 0xCCBB,
+	0x8893, 0xD08D, 0x8894, 0xD08E, 0x8895, 0xD08F, 0x8896, 0xD0E4,	0x8897, 0xD090, 0x8898, 0xD091, 0x8899, 0xD092, 0x889A, 0xD093,
+	0x889B, 0xD094, 0x889C, 0xCDE0, 0x889D, 0xD095, 0x889E, 0xD096,	0x889F, 0xD097, 0x88A0, 0xD098, 0x88A1, 0xD099, 0x88A2, 0xF1C8,
+	0x88A3, 0xD09A, 0x88A4, 0xD9F3, 0x88A5, 0xD09B, 0x88A6, 0xD09C,	0x88A7, 0xD09D, 0x88A8, 0xD09E, 0x88A9, 0xD09F, 0x88AA, 0xD0A0,
+	0x88AB, 0xB1BB, 0x88AC, 0xD140, 0x88AD, 0xCFAE, 0x88AE, 0xD141,	0x88AF, 0xD142, 0x88B0, 0xD143, 0x88B1, 0xB8A4, 0x88B2, 0xD144,
+	0x88B3, 0xD145, 0x88B4, 0xD146, 0x88B5, 0xD147, 0x88B6, 0xD148,	0x88B7, 0xF1CA, 0x88B8, 0xD149, 0x88B9, 0xD14A, 0x88BA, 0xD14B,
+	0x88BB, 0xD14C, 0x88BC, 0xF1CB, 0x88BD, 0xD14D, 0x88BE, 0xD14E,	0x88BF, 0xD14F, 0x88C0, 0xD150, 0x88C1, 0xB2C3, 0x88C2, 0xC1D1,
+	0x88C3, 0xD151, 0x88C4, 0xD152, 0x88C5, 0xD7B0, 0x88C6, 0xF1C9,	0x88C7, 0xD153, 0x88C8, 0xD154, 0x88C9, 0xF1CC, 0x88CA, 0xD155,
+	0x88CB, 0xD156, 0x88CC, 0xD157, 0x88CD, 0xD158, 0x88CE, 0xF1CE,	0x88CF, 0xD159, 0x88D0, 0xD15A, 0x88D1, 0xD15B, 0x88D2, 0xD9F6,
+	0x88D3, 0xD15C, 0x88D4, 0xD2E1, 0x88D5, 0xD4A3, 0x88D6, 0xD15D,	0x88D7, 0xD15E, 0x88D8, 0xF4C3, 0x88D9, 0xC8B9, 0x88DA, 0xD15F,
+	0x88DB, 0xD160, 0x88DC, 0xD161, 0x88DD, 0xD162, 0x88DE, 0xD163,	0x88DF, 0xF4C4, 0x88E0, 0xD164, 0x88E1, 0xD165, 0x88E2, 0xF1CD,
+	0x88E3, 0xF1CF, 0x88E4, 0xBFE3, 0x88E5, 0xF1D0, 0x88E6, 0xD166,	0x88E7, 0xD167, 0x88E8, 0xF1D4, 0x88E9, 0xD168, 0x88EA, 0xD169,
+	0x88EB, 0xD16A, 0x88EC, 0xD16B, 0x88ED, 0xD16C, 0x88EE, 0xD16D,	0x88EF, 0xD16E, 0x88F0, 0xF1D6, 0x88F1, 0xF1D1, 0x88F2, 0xD16F,
+	0x88F3, 0xC9D1, 0x88F4, 0xC5E1, 0x88F5, 0xD170, 0x88F6, 0xD171,	0x88F7, 0xD172, 0x88F8, 0xC2E3, 0x88F9, 0xB9FC, 0x88FA, 0xD173,
+	0x88FB, 0xD174, 0x88FC, 0xF1D3, 0x88FD, 0xD175, 0x88FE, 0xF1D5,	0x88FF, 0xD176, 0x8900, 0xD177, 0x8901, 0xD178, 0x8902, 0xB9D3,
+	0x8903, 0xD179, 0x8904, 0xD17A, 0x8905, 0xD17B, 0x8906, 0xD17C,	0x8907, 0xD17D, 0x8908, 0xD17E, 0x8909, 0xD180, 0x890A, 0xF1DB,
+	0x890B, 0xD181, 0x890C, 0xD182, 0x890D, 0xD183, 0x890E, 0xD184,	0x890F, 0xD185, 0x8910, 0xBAD6, 0x8911, 0xD186, 0x8912, 0xB0FD,
+	0x8913, 0xF1D9, 0x8914, 0xD187, 0x8915, 0xD188, 0x8916, 0xD189,	0x8917, 0xD18A, 0x8918, 0xD18B, 0x8919, 0xF1D8, 0x891A, 0xF1D2,
+	0x891B, 0xF1DA, 0x891C, 0xD18C, 0x891D, 0xD18D, 0x891E, 0xD18E,	0x891F, 0xD18F, 0x8920, 0xD190, 0x8921, 0xF1D7, 0x8922, 0xD191,
+	0x8923, 0xD192, 0x8924, 0xD193, 0x8925, 0xC8EC, 0x8926, 0xD194,	0x8927, 0xD195, 0x8928, 0xD196, 0x8929, 0xD197, 0x892A, 0xCDCA,
+	0x892B, 0xF1DD, 0x892C, 0xD198, 0x892D, 0xD199, 0x892E, 0xD19A,	0x892F, 0xD19B, 0x8930, 0xE5BD, 0x8931, 0xD19C, 0x8932, 0xD19D,
+	0x8933, 0xD19E, 0x8934, 0xF1DC, 0x8935, 0xD19F, 0x8936, 0xF1DE,	0x8937, 0xD1A0, 0x8938, 0xD240, 0x8939, 0xD241, 0x893A, 0xD242,
+	0x893B, 0xD243, 0x893C, 0xD244, 0x893D, 0xD245, 0x893E, 0xD246,	0x893F, 0xD247, 0x8940, 0xD248, 0x8941, 0xF1DF, 0x8942, 0xD249,
+	0x8943, 0xD24A, 0x8944, 0xCFE5, 0x8945, 0xD24B, 0x8946, 0xD24C,	0x8947, 0xD24D, 0x8948, 0xD24E, 0x8949, 0xD24F, 0x894A, 0xD250,
+	0x894B, 0xD251, 0x894C, 0xD252, 0x894D, 0xD253, 0x894E, 0xD254,	0x894F, 0xD255, 0x8950, 0xD256, 0x8951, 0xD257, 0x8952, 0xD258,
+	0x8953, 0xD259, 0x8954, 0xD25A, 0x8955, 0xD25B, 0x8956, 0xD25C,	0x8957, 0xD25D, 0x8958, 0xD25E, 0x8959, 0xD25F, 0x895A, 0xD260,
+	0x895B, 0xD261, 0x895C, 0xD262, 0x895D, 0xD263, 0x895E, 0xF4C5,	0x895F, 0xBDF3, 0x8960, 0xD264, 0x8961, 0xD265, 0x8962, 0xD266,
+	0x8963, 0xD267, 0x8964, 0xD268, 0x8965, 0xD269, 0x8966, 0xF1E0,	0x8967, 0xD26A, 0x8968, 0xD26B, 0x8969, 0xD26C, 0x896A, 0xD26D,
+	0x896B, 0xD26E, 0x896C, 0xD26F, 0x896D, 0xD270, 0x896E, 0xD271,	0x896F, 0xD272, 0x8970, 0xD273, 0x8971, 0xD274, 0x8972, 0xD275,
+	0x8973, 0xD276, 0x8974, 0xD277, 0x8975, 0xD278, 0x8976, 0xD279,	0x8977, 0xD27A, 0x8978, 0xD27B, 0x8979, 0xD27C, 0x897A, 0xD27D,
+	0x897B, 0xF1E1, 0x897C, 0xD27E, 0x897D, 0xD280, 0x897E, 0xD281,	0x897F, 0xCEF7, 0x8980, 0xD282, 0x8981, 0xD2AA, 0x8982, 0xD283,
+	0x8983, 0xF1FB, 0x8984, 0xD284, 0x8985, 0xD285, 0x8986, 0xB8B2,	0x8987, 0xD286, 0x8988, 0xD287, 0x8989, 0xD288, 0x898A, 0xD289,
+	0x898B, 0xD28A, 0x898C, 0xD28B, 0x898D, 0xD28C, 0x898E, 0xD28D,	0x898F, 0xD28E, 0x8990, 0xD28F, 0x8991, 0xD290, 0x8992, 0xD291,
+	0x8993, 0xD292, 0x8994, 0xD293, 0x8995, 0xD294, 0x8996, 0xD295,	0x8997, 0xD296, 0x8998, 0xD297, 0x8999, 0xD298, 0x899A, 0xD299,
+	0x899B, 0xD29A, 0x899C, 0xD29B, 0x899D, 0xD29C, 0x899E, 0xD29D,	0x899F, 0xD29E, 0x89A0, 0xD29F, 0x89A1, 0xD2A0, 0x89A2, 0xD340,
+	0x89A3, 0xD341, 0x89A4, 0xD342, 0x89A5, 0xD343, 0x89A6, 0xD344,	0x89A7, 0xD345, 0x89A8, 0xD346, 0x89A9, 0xD347, 0x89AA, 0xD348,
+	0x89AB, 0xD349, 0x89AC, 0xD34A, 0x89AD, 0xD34B, 0x89AE, 0xD34C,	0x89AF, 0xD34D, 0x89B0, 0xD34E, 0x89B1, 0xD34F, 0x89B2, 0xD350,
+	0x89B3, 0xD351, 0x89B4, 0xD352, 0x89B5, 0xD353, 0x89B6, 0xD354,	0x89B7, 0xD355, 0x89B8, 0xD356, 0x89B9, 0xD357, 0x89BA, 0xD358,
+	0x89BB, 0xD359, 0x89BC, 0xD35A, 0x89BD, 0xD35B, 0x89BE, 0xD35C,	0x89BF, 0xD35D, 0x89C0, 0xD35E, 0x89C1, 0xBCFB, 0x89C2, 0xB9DB,
+	0x89C3, 0xD35F, 0x89C4, 0xB9E6, 0x89C5, 0xC3D9, 0x89C6, 0xCAD3,	0x89C7, 0xEAE8, 0x89C8, 0xC0C0, 0x89C9, 0xBEF5, 0x89CA, 0xEAE9,
+	0x89CB, 0xEAEA, 0x89CC, 0xEAEB, 0x89CD, 0xD360, 0x89CE, 0xEAEC,	0x89CF, 0xEAED, 0x89D0, 0xEAEE, 0x89D1, 0xEAEF, 0x89D2, 0xBDC7,
+	0x89D3, 0xD361, 0x89D4, 0xD362, 0x89D5, 0xD363, 0x89D6, 0xF5FB,	0x89D7, 0xD364, 0x89D8, 0xD365, 0x89D9, 0xD366, 0x89DA, 0xF5FD,
+	0x89DB, 0xD367, 0x89DC, 0xF5FE, 0x89DD, 0xD368, 0x89DE, 0xF5FC,	0x89DF, 0xD369, 0x89E0, 0xD36A, 0x89E1, 0xD36B, 0x89E2, 0xD36C,
+	0x89E3, 0xBDE2, 0x89E4, 0xD36D, 0x89E5, 0xF6A1, 0x89E6, 0xB4A5,	0x89E7, 0xD36E, 0x89E8, 0xD36F, 0x89E9, 0xD370, 0x89EA, 0xD371,
+	0x89EB, 0xF6A2, 0x89EC, 0xD372, 0x89ED, 0xD373, 0x89EE, 0xD374,	0x89EF, 0xF6A3, 0x89F0, 0xD375, 0x89F1, 0xD376, 0x89F2, 0xD377,
+	0x89F3, 0xECB2, 0x89F4, 0xD378, 0x89F5, 0xD379, 0x89F6, 0xD37A,	0x89F7, 0xD37B, 0x89F8, 0xD37C, 0x89F9, 0xD37D, 0x89FA, 0xD37E,
+	0x89FB, 0xD380, 0x89FC, 0xD381, 0x89FD, 0xD382, 0x89FE, 0xD383,	0x89FF, 0xD384, 0x8A00, 0xD1D4, 0x8A01, 0xD385, 0x8A02, 0xD386,
+	0x8A03, 0xD387, 0x8A04, 0xD388, 0x8A05, 0xD389, 0x8A06, 0xD38A,	0x8A07, 0xD9EA, 0x8A08, 0xD38B, 0x8A09, 0xD38C, 0x8A0A, 0xD38D,
+	0x8A0B, 0xD38E, 0x8A0C, 0xD38F, 0x8A0D, 0xD390, 0x8A0E, 0xD391,	0x8A0F, 0xD392, 0x8A10, 0xD393, 0x8A11, 0xD394, 0x8A12, 0xD395,
+	0x8A13, 0xD396, 0x8A14, 0xD397, 0x8A15, 0xD398, 0x8A16, 0xD399,	0x8A17, 0xD39A, 0x8A18, 0xD39B, 0x8A19, 0xD39C, 0x8A1A, 0xD39D,
+	0x8A1B, 0xD39E, 0x8A1C, 0xD39F, 0x8A1D, 0xD3A0, 0x8A1E, 0xD440,	0x8A1F, 0xD441, 0x8A20, 0xD442, 0x8A21, 0xD443, 0x8A22, 0xD444,
+	0x8A23, 0xD445, 0x8A24, 0xD446, 0x8A25, 0xD447, 0x8A26, 0xD448,	0x8A27, 0xD449, 0x8A28, 0xD44A, 0x8A29, 0xD44B, 0x8A2A, 0xD44C,
+	0x8A2B, 0xD44D, 0x8A2C, 0xD44E, 0x8A2D, 0xD44F, 0x8A2E, 0xD450,	0x8A2F, 0xD451, 0x8A30, 0xD452, 0x8A31, 0xD453, 0x8A32, 0xD454,
+	0x8A33, 0xD455, 0x8A34, 0xD456, 0x8A35, 0xD457, 0x8A36, 0xD458,	0x8A37, 0xD459, 0x8A38, 0xD45A, 0x8A39, 0xD45B, 0x8A3A, 0xD45C,
+	0x8A3B, 0xD45D, 0x8A3C, 0xD45E, 0x8A3D, 0xD45F, 0x8A3E, 0xF6A4,	0x8A3F, 0xD460, 0x8A40, 0xD461, 0x8A41, 0xD462, 0x8A42, 0xD463,
+	0x8A43, 0xD464, 0x8A44, 0xD465, 0x8A45, 0xD466, 0x8A46, 0xD467,	0x8A47, 0xD468, 0x8A48, 0xEEBA, 0x8A49, 0xD469, 0x8A4A, 0xD46A,
+	0x8A4B, 0xD46B, 0x8A4C, 0xD46C, 0x8A4D, 0xD46D, 0x8A4E, 0xD46E,	0x8A4F, 0xD46F, 0x8A50, 0xD470, 0x8A51, 0xD471, 0x8A52, 0xD472,
+	0x8A53, 0xD473, 0x8A54, 0xD474, 0x8A55, 0xD475, 0x8A56, 0xD476,	0x8A57, 0xD477, 0x8A58, 0xD478, 0x8A59, 0xD479, 0x8A5A, 0xD47A,
+	0x8A5B, 0xD47B, 0x8A5C, 0xD47C, 0x8A5D, 0xD47D, 0x8A5E, 0xD47E,	0x8A5F, 0xD480, 0x8A60, 0xD481, 0x8A61, 0xD482, 0x8A62, 0xD483,
+	0x8A63, 0xD484, 0x8A64, 0xD485, 0x8A65, 0xD486, 0x8A66, 0xD487,	0x8A67, 0xD488, 0x8A68, 0xD489, 0x8A69, 0xD48A, 0x8A6A, 0xD48B,
+	0x8A6B, 0xD48C, 0x8A6C, 0xD48D, 0x8A6D, 0xD48E, 0x8A6E, 0xD48F,	0x8A6F, 0xD490, 0x8A70, 0xD491, 0x8A71, 0xD492, 0x8A72, 0xD493,
+	0x8A73, 0xD494, 0x8A74, 0xD495, 0x8A75, 0xD496, 0x8A76, 0xD497,	0x8A77, 0xD498, 0x8A78, 0xD499, 0x8A79, 0xD5B2, 0x8A7A, 0xD49A,
+	0x8A7B, 0xD49B, 0x8A7C, 0xD49C, 0x8A7D, 0xD49D, 0x8A7E, 0xD49E,	0x8A7F, 0xD49F, 0x8A80, 0xD4A0, 0x8A81, 0xD540, 0x8A82, 0xD541,
+	0x8A83, 0xD542, 0x8A84, 0xD543, 0x8A85, 0xD544, 0x8A86, 0xD545,	0x8A87, 0xD546, 0x8A88, 0xD547, 0x8A89, 0xD3FE, 0x8A8A, 0xCCDC,
+	0x8A8B, 0xD548, 0x8A8C, 0xD549, 0x8A8D, 0xD54A, 0x8A8E, 0xD54B,	0x8A8F, 0xD54C, 0x8A90, 0xD54D, 0x8A91, 0xD54E, 0x8A92, 0xD54F,
+	0x8A93, 0xCAC4, 0x8A94, 0xD550, 0x8A95, 0xD551, 0x8A96, 0xD552,	0x8A97, 0xD553, 0x8A98, 0xD554, 0x8A99, 0xD555, 0x8A9A, 0xD556,
+	0x8A9B, 0xD557, 0x8A9C, 0xD558, 0x8A9D, 0xD559, 0x8A9E, 0xD55A,	0x8A9F, 0xD55B, 0x8AA0, 0xD55C, 0x8AA1, 0xD55D, 0x8AA2, 0xD55E,
+	0x8AA3, 0xD55F, 0x8AA4, 0xD560, 0x8AA5, 0xD561, 0x8AA6, 0xD562,	0x8AA7, 0xD563, 0x8AA8, 0xD564, 0x8AA9, 0xD565, 0x8AAA, 0xD566,
+	0x8AAB, 0xD567, 0x8AAC, 0xD568, 0x8AAD, 0xD569, 0x8AAE, 0xD56A,	0x8AAF, 0xD56B, 0x8AB0, 0xD56C, 0x8AB1, 0xD56D, 0x8AB2, 0xD56E,
+	0x8AB3, 0xD56F, 0x8AB4, 0xD570, 0x8AB5, 0xD571, 0x8AB6, 0xD572,	0x8AB7, 0xD573, 0x8AB8, 0xD574, 0x8AB9, 0xD575, 0x8ABA, 0xD576,
+	0x8ABB, 0xD577, 0x8ABC, 0xD578, 0x8ABD, 0xD579, 0x8ABE, 0xD57A,	0x8ABF, 0xD57B, 0x8AC0, 0xD57C, 0x8AC1, 0xD57D, 0x8AC2, 0xD57E,
+	0x8AC3, 0xD580, 0x8AC4, 0xD581, 0x8AC5, 0xD582, 0x8AC6, 0xD583,	0x8AC7, 0xD584, 0x8AC8, 0xD585, 0x8AC9, 0xD586, 0x8ACA, 0xD587,
+	0x8ACB, 0xD588, 0x8ACC, 0xD589, 0x8ACD, 0xD58A, 0x8ACE, 0xD58B,	0x8ACF, 0xD58C, 0x8AD0, 0xD58D, 0x8AD1, 0xD58E, 0x8AD2, 0xD58F,
+	0x8AD3, 0xD590, 0x8AD4, 0xD591, 0x8AD5, 0xD592, 0x8AD6, 0xD593,	0x8AD7, 0xD594, 0x8AD8, 0xD595, 0x8AD9, 0xD596, 0x8ADA, 0xD597,
+	0x8ADB, 0xD598, 0x8ADC, 0xD599, 0x8ADD, 0xD59A, 0x8ADE, 0xD59B,	0x8ADF, 0xD59C, 0x8AE0, 0xD59D, 0x8AE1, 0xD59E, 0x8AE2, 0xD59F,
+	0x8AE3, 0xD5A0, 0x8AE4, 0xD640, 0x8AE5, 0xD641, 0x8AE6, 0xD642,	0x8AE7, 0xD643, 0x8AE8, 0xD644, 0x8AE9, 0xD645, 0x8AEA, 0xD646,
+	0x8AEB, 0xD647, 0x8AEC, 0xD648, 0x8AED, 0xD649, 0x8AEE, 0xD64A,	0x8AEF, 0xD64B, 0x8AF0, 0xD64C, 0x8AF1, 0xD64D, 0x8AF2, 0xD64E,
+	0x8AF3, 0xD64F, 0x8AF4, 0xD650, 0x8AF5, 0xD651, 0x8AF6, 0xD652,	0x8AF7, 0xD653, 0x8AF8, 0xD654, 0x8AF9, 0xD655, 0x8AFA, 0xD656,
+	0x8AFB, 0xD657, 0x8AFC, 0xD658, 0x8AFD, 0xD659, 0x8AFE, 0xD65A,	0x8AFF, 0xD65B, 0x8B00, 0xD65C, 0x8B01, 0xD65D, 0x8B02, 0xD65E,
+	0x8B03, 0xD65F, 0x8B04, 0xD660, 0x8B05, 0xD661, 0x8B06, 0xD662,	0x8B07, 0xE5C0, 0x8B08, 0xD663, 0x8B09, 0xD664, 0x8B0A, 0xD665,
+	0x8B0B, 0xD666, 0x8B0C, 0xD667, 0x8B0D, 0xD668, 0x8B0E, 0xD669,	0x8B0F, 0xD66A, 0x8B10, 0xD66B, 0x8B11, 0xD66C, 0x8B12, 0xD66D,
+	0x8B13, 0xD66E, 0x8B14, 0xD66F, 0x8B15, 0xD670, 0x8B16, 0xD671,	0x8B17, 0xD672, 0x8B18, 0xD673, 0x8B19, 0xD674, 0x8B1A, 0xD675,
+	0x8B1B, 0xD676, 0x8B1C, 0xD677, 0x8B1D, 0xD678, 0x8B1E, 0xD679,	0x8B1F, 0xD67A, 0x8B20, 0xD67B, 0x8B21, 0xD67C, 0x8B22, 0xD67D,
+	0x8B23, 0xD67E, 0x8B24, 0xD680, 0x8B25, 0xD681, 0x8B26, 0xF6A5,	0x8B27, 0xD682, 0x8B28, 0xD683, 0x8B29, 0xD684, 0x8B2A, 0xD685,
+	0x8B2B, 0xD686, 0x8B2C, 0xD687, 0x8B2D, 0xD688, 0x8B2E, 0xD689,	0x8B2F, 0xD68A, 0x8B30, 0xD68B, 0x8B31, 0xD68C, 0x8B32, 0xD68D,
+	0x8B33, 0xD68E, 0x8B34, 0xD68F, 0x8B35, 0xD690, 0x8B36, 0xD691,	0x8B37, 0xD692, 0x8B38, 0xD693, 0x8B39, 0xD694, 0x8B3A, 0xD695,
+	0x8B3B, 0xD696, 0x8B3C, 0xD697, 0x8B3D, 0xD698, 0x8B3E, 0xD699,	0x8B3F, 0xD69A, 0x8B40, 0xD69B, 0x8B41, 0xD69C, 0x8B42, 0xD69D,
+	0x8B43, 0xD69E, 0x8B44, 0xD69F, 0x8B45, 0xD6A0, 0x8B46, 0xD740,	0x8B47, 0xD741, 0x8B48, 0xD742, 0x8B49, 0xD743, 0x8B4A, 0xD744,
+	0x8B4B, 0xD745, 0x8B4C, 0xD746, 0x8B4D, 0xD747, 0x8B4E, 0xD748,	0x8B4F, 0xD749, 0x8B50, 0xD74A, 0x8B51, 0xD74B, 0x8B52, 0xD74C,
+	0x8B53, 0xD74D, 0x8B54, 0xD74E, 0x8B55, 0xD74F, 0x8B56, 0xD750,	0x8B57, 0xD751, 0x8B58, 0xD752, 0x8B59, 0xD753, 0x8B5A, 0xD754,
+	0x8B5B, 0xD755, 0x8B5C, 0xD756, 0x8B5D, 0xD757, 0x8B5E, 0xD758,	0x8B5F, 0xD759, 0x8B60, 0xD75A, 0x8B61, 0xD75B, 0x8B62, 0xD75C,
+	0x8B63, 0xD75D, 0x8B64, 0xD75E, 0x8B65, 0xD75F, 0x8B66, 0xBEAF,	0x8B67, 0xD760, 0x8B68, 0xD761, 0x8B69, 0xD762, 0x8B6A, 0xD763,
+	0x8B6B, 0xD764, 0x8B6C, 0xC6A9, 0x8B6D, 0xD765, 0x8B6E, 0xD766,	0x8B6F, 0xD767, 0x8B70, 0xD768, 0x8B71, 0xD769, 0x8B72, 0xD76A,
+	0x8B73, 0xD76B, 0x8B74, 0xD76C, 0x8B75, 0xD76D, 0x8B76, 0xD76E,	0x8B77, 0xD76F, 0x8B78, 0xD770, 0x8B79, 0xD771, 0x8B7A, 0xD772,
+	0x8B7B, 0xD773, 0x8B7C, 0xD774, 0x8B7D, 0xD775, 0x8B7E, 0xD776,	0x8B7F, 0xD777, 0x8B80, 0xD778, 0x8B81, 0xD779, 0x8B82, 0xD77A,
+	0x8B83, 0xD77B, 0x8B84, 0xD77C, 0x8B85, 0xD77D, 0x8B86, 0xD77E,	0x8B87, 0xD780, 0x8B88, 0xD781, 0x8B89, 0xD782, 0x8B8A, 0xD783,
+	0x8B8B, 0xD784, 0x8B8C, 0xD785, 0x8B8D, 0xD786, 0x8B8E, 0xD787,	0x8B8F, 0xD788, 0x8B90, 0xD789, 0x8B91, 0xD78A, 0x8B92, 0xD78B,
+	0x8B93, 0xD78C, 0x8B94, 0xD78D, 0x8B95, 0xD78E, 0x8B96, 0xD78F,	0x8B97, 0xD790, 0x8B98, 0xD791, 0x8B99, 0xD792, 0x8B9A, 0xD793,
+	0x8B9B, 0xD794, 0x8B9C, 0xD795, 0x8B9D, 0xD796, 0x8B9E, 0xD797,	0x8B9F, 0xD798, 0x8BA0, 0xDAA5, 0x8BA1, 0xBCC6, 0x8BA2, 0xB6A9,
+	0x8BA3, 0xB8BC, 0x8BA4, 0xC8CF, 0x8BA5, 0xBCA5, 0x8BA6, 0xDAA6,	0x8BA7, 0xDAA7, 0x8BA8, 0xCCD6, 0x8BA9, 0xC8C3, 0x8BAA, 0xDAA8,
+	0x8BAB, 0xC6FD, 0x8BAC, 0xD799, 0x8BAD, 0xD1B5, 0x8BAE, 0xD2E9,	0x8BAF, 0xD1B6, 0x8BB0, 0xBCC7, 0x8BB1, 0xD79A, 0x8BB2, 0xBDB2,
+	0x8BB3, 0xBBE4, 0x8BB4, 0xDAA9, 0x8BB5, 0xDAAA, 0x8BB6, 0xD1C8,	0x8BB7, 0xDAAB, 0x8BB8, 0xD0ED, 0x8BB9, 0xB6EF, 0x8BBA, 0xC2DB,
+	0x8BBB, 0xD79B, 0x8BBC, 0xCBCF, 0x8BBD, 0xB7ED, 0x8BBE, 0xC9E8,	0x8BBF, 0xB7C3, 0x8BC0, 0xBEF7, 0x8BC1, 0xD6A4, 0x8BC2, 0xDAAC,
+	0x8BC3, 0xDAAD, 0x8BC4, 0xC6C0, 0x8BC5, 0xD7E7, 0x8BC6, 0xCAB6,	0x8BC7, 0xD79C, 0x8BC8, 0xD5A9, 0x8BC9, 0xCBDF, 0x8BCA, 0xD5EF,
+	0x8BCB, 0xDAAE, 0x8BCC, 0xD6DF, 0x8BCD, 0xB4CA, 0x8BCE, 0xDAB0,	0x8BCF, 0xDAAF, 0x8BD0, 0xD79D, 0x8BD1, 0xD2EB, 0x8BD2, 0xDAB1,
+	0x8BD3, 0xDAB2, 0x8BD4, 0xDAB3, 0x8BD5, 0xCAD4, 0x8BD6, 0xDAB4,	0x8BD7, 0xCAAB, 0x8BD8, 0xDAB5, 0x8BD9, 0xDAB6, 0x8BDA, 0xB3CF,
+	0x8BDB, 0xD6EF, 0x8BDC, 0xDAB7, 0x8BDD, 0xBBB0, 0x8BDE, 0xB5AE,	0x8BDF, 0xDAB8, 0x8BE0, 0xDAB9, 0x8BE1, 0xB9EE, 0x8BE2, 0xD1AF,
+	0x8BE3, 0xD2E8, 0x8BE4, 0xDABA, 0x8BE5, 0xB8C3, 0x8BE6, 0xCFEA,	0x8BE7, 0xB2EF, 0x8BE8, 0xDABB, 0x8BE9, 0xDABC, 0x8BEA, 0xD79E,
+	0x8BEB, 0xBDEB, 0x8BEC, 0xCEDC, 0x8BED, 0xD3EF, 0x8BEE, 0xDABD,	0x8BEF, 0xCEF3, 0x8BF0, 0xDABE, 0x8BF1, 0xD3D5, 0x8BF2, 0xBBE5,
+	0x8BF3, 0xDABF, 0x8BF4, 0xCBB5, 0x8BF5, 0xCBD0, 0x8BF6, 0xDAC0,	0x8BF7, 0xC7EB, 0x8BF8, 0xD6EE, 0x8BF9, 0xDAC1, 0x8BFA, 0xC5B5,
+	0x8BFB, 0xB6C1, 0x8BFC, 0xDAC2, 0x8BFD, 0xB7CC, 0x8BFE, 0xBFCE,	0x8BFF, 0xDAC3, 0x8C00, 0xDAC4, 0x8C01, 0xCBAD, 0x8C02, 0xDAC5,
+	0x8C03, 0xB5F7, 0x8C04, 0xDAC6, 0x8C05, 0xC1C2, 0x8C06, 0xD7BB,	0x8C07, 0xDAC7, 0x8C08, 0xCCB8, 0x8C09, 0xD79F, 0x8C0A, 0xD2EA,
+	0x8C0B, 0xC4B1, 0x8C0C, 0xDAC8, 0x8C0D, 0xB5FD, 0x8C0E, 0xBBD1,	0x8C0F, 0xDAC9, 0x8C10, 0xD0B3, 0x8C11, 0xDACA, 0x8C12, 0xDACB,
+	0x8C13, 0xCEBD, 0x8C14, 0xDACC, 0x8C15, 0xDACD, 0x8C16, 0xDACE,	0x8C17, 0xB2F7, 0x8C18, 0xDAD1, 0x8C19, 0xDACF, 0x8C1A, 0xD1E8,
+	0x8C1B, 0xDAD0, 0x8C1C, 0xC3D5, 0x8C1D, 0xDAD2, 0x8C1E, 0xD7A0,	0x8C1F, 0xDAD3, 0x8C20, 0xDAD4, 0x8C21, 0xDAD5, 0x8C22, 0xD0BB,
+	0x8C23, 0xD2A5, 0x8C24, 0xB0F9, 0x8C25, 0xDAD6, 0x8C26, 0xC7AB,	0x8C27, 0xDAD7, 0x8C28, 0xBDF7, 0x8C29, 0xC3A1, 0x8C2A, 0xDAD8,
+	0x8C2B, 0xDAD9, 0x8C2C, 0xC3FD, 0x8C2D, 0xCCB7, 0x8C2E, 0xDADA,	0x8C2F, 0xDADB, 0x8C30, 0xC0BE, 0x8C31, 0xC6D7, 0x8C32, 0xDADC,
+	0x8C33, 0xDADD, 0x8C34, 0xC7B4, 0x8C35, 0xDADE, 0x8C36, 0xDADF,	0x8C37, 0xB9C8, 0x8C38, 0xD840, 0x8C39, 0xD841, 0x8C3A, 0xD842,
+	0x8C3B, 0xD843, 0x8C3C, 0xD844, 0x8C3D, 0xD845, 0x8C3E, 0xD846,	0x8C3F, 0xD847, 0x8C40, 0xD848, 0x8C41, 0xBBED, 0x8C42, 0xD849,
+	0x8C43, 0xD84A, 0x8C44, 0xD84B, 0x8C45, 0xD84C, 0x8C46, 0xB6B9,	0x8C47, 0xF4F8, 0x8C48, 0xD84D, 0x8C49, 0xF4F9, 0x8C4A, 0xD84E,
+	0x8C4B, 0xD84F, 0x8C4C, 0xCDE3, 0x8C4D, 0xD850, 0x8C4E, 0xD851,	0x8C4F, 0xD852, 0x8C50, 0xD853, 0x8C51, 0xD854, 0x8C52, 0xD855,
+	0x8C53, 0xD856, 0x8C54, 0xD857, 0x8C55, 0xF5B9, 0x8C56, 0xD858,	0x8C57, 0xD859, 0x8C58, 0xD85A, 0x8C59, 0xD85B, 0x8C5A, 0xEBE0,
+	0x8C5B, 0xD85C, 0x8C5C, 0xD85D, 0x8C5D, 0xD85E, 0x8C5E, 0xD85F,	0x8C5F, 0xD860, 0x8C60, 0xD861, 0x8C61, 0xCFF3, 0x8C62, 0xBBBF,
+	0x8C63, 0xD862, 0x8C64, 0xD863, 0x8C65, 0xD864, 0x8C66, 0xD865,	0x8C67, 0xD866, 0x8C68, 0xD867, 0x8C69, 0xD868, 0x8C6A, 0xBAC0,
+	0x8C6B, 0xD4A5, 0x8C6C, 0xD869, 0x8C6D, 0xD86A, 0x8C6E, 0xD86B,	0x8C6F, 0xD86C, 0x8C70, 0xD86D, 0x8C71, 0xD86E, 0x8C72, 0xD86F,
+	0x8C73, 0xE1D9, 0x8C74, 0xD870, 0x8C75, 0xD871, 0x8C76, 0xD872,	0x8C77, 0xD873, 0x8C78, 0xF5F4, 0x8C79, 0xB1AA, 0x8C7A, 0xB2F2,
+	0x8C7B, 0xD874, 0x8C7C, 0xD875, 0x8C7D, 0xD876, 0x8C7E, 0xD877,	0x8C7F, 0xD878, 0x8C80, 0xD879, 0x8C81, 0xD87A, 0x8C82, 0xF5F5,
+	0x8C83, 0xD87B, 0x8C84, 0xD87C, 0x8C85, 0xF5F7, 0x8C86, 0xD87D,	0x8C87, 0xD87E, 0x8C88, 0xD880, 0x8C89, 0xBAD1, 0x8C8A, 0xF5F6,
+	0x8C8B, 0xD881, 0x8C8C, 0xC3B2, 0x8C8D, 0xD882, 0x8C8E, 0xD883,	0x8C8F, 0xD884, 0x8C90, 0xD885, 0x8C91, 0xD886, 0x8C92, 0xD887,
+	0x8C93, 0xD888, 0x8C94, 0xF5F9, 0x8C95, 0xD889, 0x8C96, 0xD88A,	0x8C97, 0xD88B, 0x8C98, 0xF5F8, 0x8C99, 0xD88C, 0x8C9A, 0xD88D,
+	0x8C9B, 0xD88E, 0x8C9C, 0xD88F, 0x8C9D, 0xD890, 0x8C9E, 0xD891,	0x8C9F, 0xD892, 0x8CA0, 0xD893, 0x8CA1, 0xD894, 0x8CA2, 0xD895,
+	0x8CA3, 0xD896, 0x8CA4, 0xD897, 0x8CA5, 0xD898, 0x8CA6, 0xD899,	0x8CA7, 0xD89A, 0x8CA8, 0xD89B, 0x8CA9, 0xD89C, 0x8CAA, 0xD89D,
+	0x8CAB, 0xD89E, 0x8CAC, 0xD89F, 0x8CAD, 0xD8A0, 0x8CAE, 0xD940,	0x8CAF, 0xD941, 0x8CB0, 0xD942, 0x8CB1, 0xD943, 0x8CB2, 0xD944,
+	0x8CB3, 0xD945, 0x8CB4, 0xD946, 0x8CB5, 0xD947, 0x8CB6, 0xD948,	0x8CB7, 0xD949, 0x8CB8, 0xD94A, 0x8CB9, 0xD94B, 0x8CBA, 0xD94C,
+	0x8CBB, 0xD94D, 0x8CBC, 0xD94E, 0x8CBD, 0xD94F, 0x8CBE, 0xD950,	0x8CBF, 0xD951, 0x8CC0, 0xD952, 0x8CC1, 0xD953, 0x8CC2, 0xD954,
+	0x8CC3, 0xD955, 0x8CC4, 0xD956, 0x8CC5, 0xD957, 0x8CC6, 0xD958,	0x8CC7, 0xD959, 0x8CC8, 0xD95A, 0x8CC9, 0xD95B, 0x8CCA, 0xD95C,
+	0x8CCB, 0xD95D, 0x8CCC, 0xD95E, 0x8CCD, 0xD95F, 0x8CCE, 0xD960,	0x8CCF, 0xD961, 0x8CD0, 0xD962, 0x8CD1, 0xD963, 0x8CD2, 0xD964,
+	0x8CD3, 0xD965, 0x8CD4, 0xD966, 0x8CD5, 0xD967, 0x8CD6, 0xD968,	0x8CD7, 0xD969, 0x8CD8, 0xD96A, 0x8CD9, 0xD96B, 0x8CDA, 0xD96C,
+	0x8CDB, 0xD96D, 0x8CDC, 0xD96E, 0x8CDD, 0xD96F, 0x8CDE, 0xD970,	0x8CDF, 0xD971, 0x8CE0, 0xD972, 0x8CE1, 0xD973, 0x8CE2, 0xD974,
+	0x8CE3, 0xD975, 0x8CE4, 0xD976, 0x8CE5, 0xD977, 0x8CE6, 0xD978,	0x8CE7, 0xD979, 0x8CE8, 0xD97A, 0x8CE9, 0xD97B, 0x8CEA, 0xD97C,
+	0x8CEB, 0xD97D, 0x8CEC, 0xD97E, 0x8CED, 0xD980, 0x8CEE, 0xD981,	0x8CEF, 0xD982, 0x8CF0, 0xD983, 0x8CF1, 0xD984, 0x8CF2, 0xD985,
+	0x8CF3, 0xD986, 0x8CF4, 0xD987, 0x8CF5, 0xD988, 0x8CF6, 0xD989,	0x8CF7, 0xD98A, 0x8CF8, 0xD98B, 0x8CF9, 0xD98C, 0x8CFA, 0xD98D,
+	0x8CFB, 0xD98E, 0x8CFC, 0xD98F, 0x8CFD, 0xD990, 0x8CFE, 0xD991,	0x8CFF, 0xD992, 0x8D00, 0xD993, 0x8D01, 0xD994, 0x8D02, 0xD995,
+	0x8D03, 0xD996, 0x8D04, 0xD997, 0x8D05, 0xD998, 0x8D06, 0xD999,	0x8D07, 0xD99A, 0x8D08, 0xD99B, 0x8D09, 0xD99C, 0x8D0A, 0xD99D,
+	0x8D0B, 0xD99E, 0x8D0C, 0xD99F, 0x8D0D, 0xD9A0, 0x8D0E, 0xDA40,	0x8D0F, 0xDA41, 0x8D10, 0xDA42, 0x8D11, 0xDA43, 0x8D12, 0xDA44,
+	0x8D13, 0xDA45, 0x8D14, 0xDA46, 0x8D15, 0xDA47, 0x8D16, 0xDA48,	0x8D17, 0xDA49, 0x8D18, 0xDA4A, 0x8D19, 0xDA4B, 0x8D1A, 0xDA4C,
+	0x8D1B, 0xDA4D, 0x8D1C, 0xDA4E, 0x8D1D, 0xB1B4, 0x8D1E, 0xD5EA,	0x8D1F, 0xB8BA, 0x8D20, 0xDA4F, 0x8D21, 0xB9B1, 0x8D22, 0xB2C6,
+	0x8D23, 0xD4F0, 0x8D24, 0xCFCD, 0x8D25, 0xB0DC, 0x8D26, 0xD5CB,	0x8D27, 0xBBF5, 0x8D28, 0xD6CA, 0x8D29, 0xB7B7, 0x8D2A, 0xCCB0,
+	0x8D2B, 0xC6B6, 0x8D2C, 0xB1E1, 0x8D2D, 0xB9BA, 0x8D2E, 0xD6FC,	0x8D2F, 0xB9E1, 0x8D30, 0xB7A1, 0x8D31, 0xBCFA, 0x8D32, 0xEADA,
+	0x8D33, 0xEADB, 0x8D34, 0xCCF9, 0x8D35, 0xB9F3, 0x8D36, 0xEADC,	0x8D37, 0xB4FB, 0x8D38, 0xC3B3, 0x8D39, 0xB7D1, 0x8D3A, 0xBAD8,
+	0x8D3B, 0xEADD, 0x8D3C, 0xD4F4, 0x8D3D, 0xEADE, 0x8D3E, 0xBCD6,	0x8D3F, 0xBBDF, 0x8D40, 0xEADF, 0x8D41, 0xC1DE, 0x8D42, 0xC2B8,
+	0x8D43, 0xD4DF, 0x8D44, 0xD7CA, 0x8D45, 0xEAE0, 0x8D46, 0xEAE1,	0x8D47, 0xEAE4, 0x8D48, 0xEAE2, 0x8D49, 0xEAE3, 0x8D4A, 0xC9DE,
+	0x8D4B, 0xB8B3, 0x8D4C, 0xB6C4, 0x8D4D, 0xEAE5, 0x8D4E, 0xCAEA,	0x8D4F, 0xC9CD, 0x8D50, 0xB4CD, 0x8D51, 0xDA50, 0x8D52, 0xDA51,
+	0x8D53, 0xE2D9, 0x8D54, 0xC5E2, 0x8D55, 0xEAE6, 0x8D56, 0xC0B5,	0x8D57, 0xDA52, 0x8D58, 0xD7B8, 0x8D59, 0xEAE7, 0x8D5A, 0xD7AC,
+	0x8D5B, 0xC8FC, 0x8D5C, 0xD8D3, 0x8D5D, 0xD8CD, 0x8D5E, 0xD4DE,	0x8D5F, 0xDA53, 0x8D60, 0xD4F9, 0x8D61, 0xC9C4, 0x8D62, 0xD3AE,
+	0x8D63, 0xB8D3, 0x8D64, 0xB3E0, 0x8D65, 0xDA54, 0x8D66, 0xC9E2,	0x8D67, 0xF4F6, 0x8D68, 0xDA55, 0x8D69, 0xDA56, 0x8D6A, 0xDA57,
+	0x8D6B, 0xBAD5, 0x8D6C, 0xDA58, 0x8D6D, 0xF4F7, 0x8D6E, 0xDA59,	0x8D6F, 0xDA5A, 0x8D70, 0xD7DF, 0x8D71, 0xDA5B, 0x8D72, 0xDA5C,
+	0x8D73, 0xF4F1, 0x8D74, 0xB8B0, 0x8D75, 0xD5D4, 0x8D76, 0xB8CF,	0x8D77, 0xC6F0, 0x8D78, 0xDA5D, 0x8D79, 0xDA5E, 0x8D7A, 0xDA5F,
+	0x8D7B, 0xDA60, 0x8D7C, 0xDA61, 0x8D7D, 0xDA62, 0x8D7E, 0xDA63,	0x8D7F, 0xDA64, 0x8D80, 0xDA65, 0x8D81, 0xB3C3, 0x8D82, 0xDA66,
+	0x8D83, 0xDA67, 0x8D84, 0xF4F2, 0x8D85, 0xB3AC, 0x8D86, 0xDA68,	0x8D87, 0xDA69, 0x8D88, 0xDA6A, 0x8D89, 0xDA6B, 0x8D8A, 0xD4BD,
+	0x8D8B, 0xC7F7, 0x8D8C, 0xDA6C, 0x8D8D, 0xDA6D, 0x8D8E, 0xDA6E,	0x8D8F, 0xDA6F, 0x8D90, 0xDA70, 0x8D91, 0xF4F4, 0x8D92, 0xDA71,
+	0x8D93, 0xDA72, 0x8D94, 0xF4F3, 0x8D95, 0xDA73, 0x8D96, 0xDA74,	0x8D97, 0xDA75, 0x8D98, 0xDA76, 0x8D99, 0xDA77, 0x8D9A, 0xDA78,
+	0x8D9B, 0xDA79, 0x8D9C, 0xDA7A, 0x8D9D, 0xDA7B, 0x8D9E, 0xDA7C,	0x8D9F, 0xCCCB, 0x8DA0, 0xDA7D, 0x8DA1, 0xDA7E, 0x8DA2, 0xDA80,
+	0x8DA3, 0xC8A4, 0x8DA4, 0xDA81, 0x8DA5, 0xDA82, 0x8DA6, 0xDA83,	0x8DA7, 0xDA84, 0x8DA8, 0xDA85, 0x8DA9, 0xDA86, 0x8DAA, 0xDA87,
+	0x8DAB, 0xDA88, 0x8DAC, 0xDA89, 0x8DAD, 0xDA8A, 0x8DAE, 0xDA8B,	0x8DAF, 0xDA8C, 0x8DB0, 0xDA8D, 0x8DB1, 0xF4F5, 0x8DB2, 0xDA8E,
+	0x8DB3, 0xD7E3, 0x8DB4, 0xC5BF, 0x8DB5, 0xF5C0, 0x8DB6, 0xDA8F,	0x8DB7, 0xDA90, 0x8DB8, 0xF5BB, 0x8DB9, 0xDA91, 0x8DBA, 0xF5C3,
+	0x8DBB, 0xDA92, 0x8DBC, 0xF5C2, 0x8DBD, 0xDA93, 0x8DBE, 0xD6BA,	0x8DBF, 0xF5C1, 0x8DC0, 0xDA94, 0x8DC1, 0xDA95, 0x8DC2, 0xDA96,
+	0x8DC3, 0xD4BE, 0x8DC4, 0xF5C4, 0x8DC5, 0xDA97, 0x8DC6, 0xF5CC,	0x8DC7, 0xDA98, 0x8DC8, 0xDA99, 0x8DC9, 0xDA9A, 0x8DCA, 0xDA9B,
+	0x8DCB, 0xB0CF, 0x8DCC, 0xB5F8, 0x8DCD, 0xDA9C, 0x8DCE, 0xF5C9,	0x8DCF, 0xF5CA, 0x8DD0, 0xDA9D, 0x8DD1, 0xC5DC, 0x8DD2, 0xDA9E,
+	0x8DD3, 0xDA9F, 0x8DD4, 0xDAA0, 0x8DD5, 0xDB40, 0x8DD6, 0xF5C5,	0x8DD7, 0xF5C6, 0x8DD8, 0xDB41, 0x8DD9, 0xDB42, 0x8DDA, 0xF5C7,
+	0x8DDB, 0xF5CB, 0x8DDC, 0xDB43, 0x8DDD, 0xBEE0, 0x8DDE, 0xF5C8,	0x8DDF, 0xB8FA, 0x8DE0, 0xDB44, 0x8DE1, 0xDB45, 0x8DE2, 0xDB46,
+	0x8DE3, 0xF5D0, 0x8DE4, 0xF5D3, 0x8DE5, 0xDB47, 0x8DE6, 0xDB48,	0x8DE7, 0xDB49, 0x8DE8, 0xBFE7, 0x8DE9, 0xDB4A, 0x8DEA, 0xB9F2,
+	0x8DEB, 0xF5BC, 0x8DEC, 0xF5CD, 0x8DED, 0xDB4B, 0x8DEE, 0xDB4C,	0x8DEF, 0xC2B7, 0x8DF0, 0xDB4D, 0x8DF1, 0xDB4E, 0x8DF2, 0xDB4F,
+	0x8DF3, 0xCCF8, 0x8DF4, 0xDB50, 0x8DF5, 0xBCF9, 0x8DF6, 0xDB51,	0x8DF7, 0xF5CE, 0x8DF8, 0xF5CF, 0x8DF9, 0xF5D1, 0x8DFA, 0xB6E5,
+	0x8DFB, 0xF5D2, 0x8DFC, 0xDB52, 0x8DFD, 0xF5D5, 0x8DFE, 0xDB53,	0x8DFF, 0xDB54, 0x8E00, 0xDB55, 0x8E01, 0xDB56, 0x8E02, 0xDB57,
+	0x8E03, 0xDB58, 0x8E04, 0xDB59, 0x8E05, 0xF5BD, 0x8E06, 0xDB5A,	0x8E07, 0xDB5B, 0x8E08, 0xDB5C, 0x8E09, 0xF5D4, 0x8E0A, 0xD3BB,
+	0x8E0B, 0xDB5D, 0x8E0C, 0xB3EC, 0x8E0D, 0xDB5E, 0x8E0E, 0xDB5F,	0x8E0F, 0xCCA4, 0x8E10, 0xDB60, 0x8E11, 0xDB61, 0x8E12, 0xDB62,
+	0x8E13, 0xDB63, 0x8E14, 0xF5D6, 0x8E15, 0xDB64, 0x8E16, 0xDB65,	0x8E17, 0xDB66, 0x8E18, 0xDB67, 0x8E19, 0xDB68, 0x8E1A, 0xDB69,
+	0x8E1B, 0xDB6A, 0x8E1C, 0xDB6B, 0x8E1D, 0xF5D7, 0x8E1E, 0xBEE1,	0x8E1F, 0xF5D8, 0x8E20, 0xDB6C, 0x8E21, 0xDB6D, 0x8E22, 0xCCDF,
+	0x8E23, 0xF5DB, 0x8E24, 0xDB6E, 0x8E25, 0xDB6F, 0x8E26, 0xDB70,	0x8E27, 0xDB71, 0x8E28, 0xDB72, 0x8E29, 0xB2C8, 0x8E2A, 0xD7D9,
+	0x8E2B, 0xDB73, 0x8E2C, 0xF5D9, 0x8E2D, 0xDB74, 0x8E2E, 0xF5DA,	0x8E2F, 0xF5DC, 0x8E30, 0xDB75, 0x8E31, 0xF5E2, 0x8E32, 0xDB76,
+	0x8E33, 0xDB77, 0x8E34, 0xDB78, 0x8E35, 0xF5E0, 0x8E36, 0xDB79,	0x8E37, 0xDB7A, 0x8E38, 0xDB7B, 0x8E39, 0xF5DF, 0x8E3A, 0xF5DD,
+	0x8E3B, 0xDB7C, 0x8E3C, 0xDB7D, 0x8E3D, 0xF5E1, 0x8E3E, 0xDB7E,	0x8E3F, 0xDB80, 0x8E40, 0xF5DE, 0x8E41, 0xF5E4, 0x8E42, 0xF5E5,
+	0x8E43, 0xDB81, 0x8E44, 0xCCE3, 0x8E45, 0xDB82, 0x8E46, 0xDB83,	0x8E47, 0xE5BF, 0x8E48, 0xB5B8, 0x8E49, 0xF5E3, 0x8E4A, 0xF5E8,
+	0x8E4B, 0xCCA3, 0x8E4C, 0xDB84, 0x8E4D, 0xDB85, 0x8E4E, 0xDB86,	0x8E4F, 0xDB87, 0x8E50, 0xDB88, 0x8E51, 0xF5E6, 0x8E52, 0xF5E7,
+	0x8E53, 0xDB89, 0x8E54, 0xDB8A, 0x8E55, 0xDB8B, 0x8E56, 0xDB8C,	0x8E57, 0xDB8D, 0x8E58, 0xDB8E, 0x8E59, 0xF5BE, 0x8E5A, 0xDB8F,
+	0x8E5B, 0xDB90, 0x8E5C, 0xDB91, 0x8E5D, 0xDB92, 0x8E5E, 0xDB93,	0x8E5F, 0xDB94, 0x8E60, 0xDB95, 0x8E61, 0xDB96, 0x8E62, 0xDB97,
+	0x8E63, 0xDB98, 0x8E64, 0xDB99, 0x8E65, 0xDB9A, 0x8E66, 0xB1C4,	0x8E67, 0xDB9B, 0x8E68, 0xDB9C, 0x8E69, 0xF5BF, 0x8E6A, 0xDB9D,
+	0x8E6B, 0xDB9E, 0x8E6C, 0xB5C5, 0x8E6D, 0xB2E4, 0x8E6E, 0xDB9F,	0x8E6F, 0xF5EC, 0x8E70, 0xF5E9, 0x8E71, 0xDBA0, 0x8E72, 0xB6D7,
+	0x8E73, 0xDC40, 0x8E74, 0xF5ED, 0x8E75, 0xDC41, 0x8E76, 0xF5EA,	0x8E77, 0xDC42, 0x8E78, 0xDC43, 0x8E79, 0xDC44, 0x8E7A, 0xDC45,
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+	0x9123, 0xDBB5, 0x9124, 0xE084, 0x9125, 0xE085, 0x9126, 0xE086,	0x9127, 0xE087, 0x9128, 0xE088, 0x9129, 0xE089, 0x912A, 0xE08A,
+	0x912B, 0xE08B, 0x912C, 0xE08C, 0x912D, 0xE08D, 0x912E, 0xE08E,	0x912F, 0xDBB7, 0x9130, 0xE08F, 0x9131, 0xDBB6, 0x9132, 0xE090,
+	0x9133, 0xE091, 0x9134, 0xE092, 0x9135, 0xE093, 0x9136, 0xE094,	0x9137, 0xE095, 0x9138, 0xE096, 0x9139, 0xDBB8, 0x913A, 0xE097,
+	0x913B, 0xE098, 0x913C, 0xE099, 0x913D, 0xE09A, 0x913E, 0xE09B,	0x913F, 0xE09C, 0x9140, 0xE09D, 0x9141, 0xE09E, 0x9142, 0xE09F,
+	0x9143, 0xDBB9, 0x9144, 0xE0A0, 0x9145, 0xE140, 0x9146, 0xDBBA,	0x9147, 0xE141, 0x9148, 0xE142, 0x9149, 0xD3CF, 0x914A, 0xF4FA,
+	0x914B, 0xC7F5, 0x914C, 0xD7C3, 0x914D, 0xC5E4, 0x914E, 0xF4FC,	0x914F, 0xF4FD, 0x9150, 0xF4FB, 0x9151, 0xE143, 0x9152, 0xBEC6,
+	0x9153, 0xE144, 0x9154, 0xE145, 0x9155, 0xE146, 0x9156, 0xE147,	0x9157, 0xD0EF, 0x9158, 0xE148, 0x9159, 0xE149, 0x915A, 0xB7D3,
+	0x915B, 0xE14A, 0x915C, 0xE14B, 0x915D, 0xD4CD, 0x915E, 0xCCAA,	0x915F, 0xE14C, 0x9160, 0xE14D, 0x9161, 0xF5A2, 0x9162, 0xF5A1,
+	0x9163, 0xBAA8, 0x9164, 0xF4FE, 0x9165, 0xCBD6, 0x9166, 0xE14E,	0x9167, 0xE14F, 0x9168, 0xE150, 0x9169, 0xF5A4, 0x916A, 0xC0D2,
+	0x916B, 0xE151, 0x916C, 0xB3EA, 0x916D, 0xE152, 0x916E, 0xCDAA,	0x916F, 0xF5A5, 0x9170, 0xF5A3, 0x9171, 0xBDB4, 0x9172, 0xF5A8,
+	0x9173, 0xE153, 0x9174, 0xF5A9, 0x9175, 0xBDCD, 0x9176, 0xC3B8,	0x9177, 0xBFE1, 0x9178, 0xCBE1, 0x9179, 0xF5AA, 0x917A, 0xE154,
+	0x917B, 0xE155, 0x917C, 0xE156, 0x917D, 0xF5A6, 0x917E, 0xF5A7,	0x917F, 0xC4F0, 0x9180, 0xE157, 0x9181, 0xE158, 0x9182, 0xE159,
+	0x9183, 0xE15A, 0x9184, 0xE15B, 0x9185, 0xF5AC, 0x9186, 0xE15C,	0x9187, 0xB4BC, 0x9188, 0xE15D, 0x9189, 0xD7ED, 0x918A, 0xE15E,
+	0x918B, 0xB4D7, 0x918C, 0xF5AB, 0x918D, 0xF5AE, 0x918E, 0xE15F,	0x918F, 0xE160, 0x9190, 0xF5AD, 0x9191, 0xF5AF, 0x9192, 0xD0D1,
+	0x9193, 0xE161, 0x9194, 0xE162, 0x9195, 0xE163, 0x9196, 0xE164,	0x9197, 0xE165, 0x9198, 0xE166, 0x9199, 0xE167, 0x919A, 0xC3D1,
+	0x919B, 0xC8A9, 0x919C, 0xE168, 0x919D, 0xE169, 0x919E, 0xE16A,	0x919F, 0xE16B, 0x91A0, 0xE16C, 0x91A1, 0xE16D, 0x91A2, 0xF5B0,
+	0x91A3, 0xF5B1, 0x91A4, 0xE16E, 0x91A5, 0xE16F, 0x91A6, 0xE170,	0x91A7, 0xE171, 0x91A8, 0xE172, 0x91A9, 0xE173, 0x91AA, 0xF5B2,
+	0x91AB, 0xE174, 0x91AC, 0xE175, 0x91AD, 0xF5B3, 0x91AE, 0xF5B4,	0x91AF, 0xF5B5, 0x91B0, 0xE176, 0x91B1, 0xE177, 0x91B2, 0xE178,
+	0x91B3, 0xE179, 0x91B4, 0xF5B7, 0x91B5, 0xF5B6, 0x91B6, 0xE17A,	0x91B7, 0xE17B, 0x91B8, 0xE17C, 0x91B9, 0xE17D, 0x91BA, 0xF5B8,
+	0x91BB, 0xE17E, 0x91BC, 0xE180, 0x91BD, 0xE181, 0x91BE, 0xE182,	0x91BF, 0xE183, 0x91C0, 0xE184, 0x91C1, 0xE185, 0x91C2, 0xE186,
+	0x91C3, 0xE187, 0x91C4, 0xE188, 0x91C5, 0xE189, 0x91C6, 0xE18A,	0x91C7, 0xB2C9, 0x91C8, 0xE18B, 0x91C9, 0xD3D4, 0x91CA, 0xCACD,
+	0x91CB, 0xE18C, 0x91CC, 0xC0EF, 0x91CD, 0xD6D8, 0x91CE, 0xD2B0,	0x91CF, 0xC1BF, 0x91D0, 0xE18D, 0x91D1, 0xBDF0, 0x91D2, 0xE18E,
+	0x91D3, 0xE18F, 0x91D4, 0xE190, 0x91D5, 0xE191, 0x91D6, 0xE192,	0x91D7, 0xE193, 0x91D8, 0xE194, 0x91D9, 0xE195, 0x91DA, 0xE196,
+	0x91DB, 0xE197, 0x91DC, 0xB8AA, 0x91DD, 0xE198, 0x91DE, 0xE199,	0x91DF, 0xE19A, 0x91E0, 0xE19B, 0x91E1, 0xE19C, 0x91E2, 0xE19D,
+	0x91E3, 0xE19E, 0x91E4, 0xE19F, 0x91E5, 0xE1A0, 0x91E6, 0xE240,	0x91E7, 0xE241, 0x91E8, 0xE242, 0x91E9, 0xE243, 0x91EA, 0xE244,
+	0x91EB, 0xE245, 0x91EC, 0xE246, 0x91ED, 0xE247, 0x91EE, 0xE248,	0x91EF, 0xE249, 0x91F0, 0xE24A, 0x91F1, 0xE24B, 0x91F2, 0xE24C,
+	0x91F3, 0xE24D, 0x91F4, 0xE24E, 0x91F5, 0xE24F, 0x91F6, 0xE250,	0x91F7, 0xE251, 0x91F8, 0xE252, 0x91F9, 0xE253, 0x91FA, 0xE254,
+	0x91FB, 0xE255, 0x91FC, 0xE256, 0x91FD, 0xE257, 0x91FE, 0xE258,	0x91FF, 0xE259, 0x9200, 0xE25A, 0x9201, 0xE25B, 0x9202, 0xE25C,
+	0x9203, 0xE25D, 0x9204, 0xE25E, 0x9205, 0xE25F, 0x9206, 0xE260,	0x9207, 0xE261, 0x9208, 0xE262, 0x9209, 0xE263, 0x920A, 0xE264,
+	0x920B, 0xE265, 0x920C, 0xE266, 0x920D, 0xE267, 0x920E, 0xE268,	0x920F, 0xE269, 0x9210, 0xE26A, 0x9211, 0xE26B, 0x9212, 0xE26C,
+	0x9213, 0xE26D, 0x9214, 0xE26E, 0x9215, 0xE26F, 0x9216, 0xE270,	0x9217, 0xE271, 0x9218, 0xE272, 0x9219, 0xE273, 0x921A, 0xE274,
+	0x921B, 0xE275, 0x921C, 0xE276, 0x921D, 0xE277, 0x921E, 0xE278,	0x921F, 0xE279, 0x9220, 0xE27A, 0x9221, 0xE27B, 0x9222, 0xE27C,
+	0x9223, 0xE27D, 0x9224, 0xE27E, 0x9225, 0xE280, 0x9226, 0xE281,	0x9227, 0xE282, 0x9228, 0xE283, 0x9229, 0xE284, 0x922A, 0xE285,
+	0x922B, 0xE286, 0x922C, 0xE287, 0x922D, 0xE288, 0x922E, 0xE289,	0x922F, 0xE28A, 0x9230, 0xE28B, 0x9231, 0xE28C, 0x9232, 0xE28D,
+	0x9233, 0xE28E, 0x9234, 0xE28F, 0x9235, 0xE290, 0x9236, 0xE291,	0x9237, 0xE292, 0x9238, 0xE293, 0x9239, 0xE294, 0x923A, 0xE295,
+	0x923B, 0xE296, 0x923C, 0xE297, 0x923D, 0xE298, 0x923E, 0xE299,	0x923F, 0xE29A, 0x9240, 0xE29B, 0x9241, 0xE29C, 0x9242, 0xE29D,
+	0x9243, 0xE29E, 0x9244, 0xE29F, 0x9245, 0xE2A0, 0x9246, 0xE340,	0x9247, 0xE341, 0x9248, 0xE342, 0x9249, 0xE343, 0x924A, 0xE344,
+	0x924B, 0xE345, 0x924C, 0xE346, 0x924D, 0xE347, 0x924E, 0xE348,	0x924F, 0xE349, 0x9250, 0xE34A, 0x9251, 0xE34B, 0x9252, 0xE34C,
+	0x9253, 0xE34D, 0x9254, 0xE34E, 0x9255, 0xE34F, 0x9256, 0xE350,	0x9257, 0xE351, 0x9258, 0xE352, 0x9259, 0xE353, 0x925A, 0xE354,
+	0x925B, 0xE355, 0x925C, 0xE356, 0x925D, 0xE357, 0x925E, 0xE358,	0x925F, 0xE359, 0x9260, 0xE35A, 0x9261, 0xE35B, 0x9262, 0xE35C,
+	0x9263, 0xE35D, 0x9264, 0xE35E, 0x9265, 0xE35F, 0x9266, 0xE360,	0x9267, 0xE361, 0x9268, 0xE362, 0x9269, 0xE363, 0x926A, 0xE364,
+	0x926B, 0xE365, 0x926C, 0xE366, 0x926D, 0xE367, 0x926E, 0xE368,	0x926F, 0xE369, 0x9270, 0xE36A, 0x9271, 0xE36B, 0x9272, 0xE36C,
+	0x9273, 0xE36D, 0x9274, 0xBCF8, 0x9275, 0xE36E, 0x9276, 0xE36F,	0x9277, 0xE370, 0x9278, 0xE371, 0x9279, 0xE372, 0x927A, 0xE373,
+	0x927B, 0xE374, 0x927C, 0xE375, 0x927D, 0xE376, 0x927E, 0xE377,	0x927F, 0xE378, 0x9280, 0xE379, 0x9281, 0xE37A, 0x9282, 0xE37B,
+	0x9283, 0xE37C, 0x9284, 0xE37D, 0x9285, 0xE37E, 0x9286, 0xE380,	0x9287, 0xE381, 0x9288, 0xE382, 0x9289, 0xE383, 0x928A, 0xE384,
+	0x928B, 0xE385, 0x928C, 0xE386, 0x928D, 0xE387, 0x928E, 0xF6C6,	0x928F, 0xE388, 0x9290, 0xE389, 0x9291, 0xE38A, 0x9292, 0xE38B,
+	0x9293, 0xE38C, 0x9294, 0xE38D, 0x9295, 0xE38E, 0x9296, 0xE38F,	0x9297, 0xE390, 0x9298, 0xE391, 0x9299, 0xE392, 0x929A, 0xE393,
+	0x929B, 0xE394, 0x929C, 0xE395, 0x929D, 0xE396, 0x929E, 0xE397,	0x929F, 0xE398, 0x92A0, 0xE399, 0x92A1, 0xE39A, 0x92A2, 0xE39B,
+	0x92A3, 0xE39C, 0x92A4, 0xE39D, 0x92A5, 0xE39E, 0x92A6, 0xE39F,	0x92A7, 0xE3A0, 0x92A8, 0xE440, 0x92A9, 0xE441, 0x92AA, 0xE442,
+	0x92AB, 0xE443, 0x92AC, 0xE444, 0x92AD, 0xE445, 0x92AE, 0xF6C7,	0x92AF, 0xE446, 0x92B0, 0xE447, 0x92B1, 0xE448, 0x92B2, 0xE449,
+	0x92B3, 0xE44A, 0x92B4, 0xE44B, 0x92B5, 0xE44C, 0x92B6, 0xE44D,	0x92B7, 0xE44E, 0x92B8, 0xE44F, 0x92B9, 0xE450, 0x92BA, 0xE451,
+	0x92BB, 0xE452, 0x92BC, 0xE453, 0x92BD, 0xE454, 0x92BE, 0xE455,	0x92BF, 0xE456, 0x92C0, 0xE457, 0x92C1, 0xE458, 0x92C2, 0xE459,
+	0x92C3, 0xE45A, 0x92C4, 0xE45B, 0x92C5, 0xE45C, 0x92C6, 0xE45D,	0x92C7, 0xE45E, 0x92C8, 0xF6C8, 0x92C9, 0xE45F, 0x92CA, 0xE460,
+	0x92CB, 0xE461, 0x92CC, 0xE462, 0x92CD, 0xE463, 0x92CE, 0xE464,	0x92CF, 0xE465, 0x92D0, 0xE466, 0x92D1, 0xE467, 0x92D2, 0xE468,
+	0x92D3, 0xE469, 0x92D4, 0xE46A, 0x92D5, 0xE46B, 0x92D6, 0xE46C,	0x92D7, 0xE46D, 0x92D8, 0xE46E, 0x92D9, 0xE46F, 0x92DA, 0xE470,
+	0x92DB, 0xE471, 0x92DC, 0xE472, 0x92DD, 0xE473, 0x92DE, 0xE474,	0x92DF, 0xE475, 0x92E0, 0xE476, 0x92E1, 0xE477, 0x92E2, 0xE478,
+	0x92E3, 0xE479, 0x92E4, 0xE47A, 0x92E5, 0xE47B, 0x92E6, 0xE47C,	0x92E7, 0xE47D, 0x92E8, 0xE47E, 0x92E9, 0xE480, 0x92EA, 0xE481,
+	0x92EB, 0xE482, 0x92EC, 0xE483, 0x92ED, 0xE484, 0x92EE, 0xE485,	0x92EF, 0xE486, 0x92F0, 0xE487, 0x92F1, 0xE488, 0x92F2, 0xE489,
+	0x92F3, 0xE48A, 0x92F4, 0xE48B, 0x92F5, 0xE48C, 0x92F6, 0xE48D,	0x92F7, 0xE48E, 0x92F8, 0xE48F, 0x92F9, 0xE490, 0x92FA, 0xE491,
+	0x92FB, 0xE492, 0x92FC, 0xE493, 0x92FD, 0xE494, 0x92FE, 0xE495,	0x92FF, 0xE496, 0x9300, 0xE497, 0x9301, 0xE498, 0x9302, 0xE499,
+	0x9303, 0xE49A, 0x9304, 0xE49B, 0x9305, 0xE49C, 0x9306, 0xE49D,	0x9307, 0xE49E, 0x9308, 0xE49F, 0x9309, 0xE4A0, 0x930A, 0xE540,
+	0x930B, 0xE541, 0x930C, 0xE542, 0x930D, 0xE543, 0x930E, 0xE544,	0x930F, 0xE545, 0x9310, 0xE546, 0x9311, 0xE547, 0x9312, 0xE548,
+	0x9313, 0xE549, 0x9314, 0xE54A, 0x9315, 0xE54B, 0x9316, 0xE54C,	0x9317, 0xE54D, 0x9318, 0xE54E, 0x9319, 0xE54F, 0x931A, 0xE550,
+	0x931B, 0xE551, 0x931C, 0xE552, 0x931D, 0xE553, 0x931E, 0xE554,	0x931F, 0xE555, 0x9320, 0xE556, 0x9321, 0xE557, 0x9322, 0xE558,
+	0x9323, 0xE559, 0x9324, 0xE55A, 0x9325, 0xE55B, 0x9326, 0xE55C,	0x9327, 0xE55D, 0x9328, 0xE55E, 0x9329, 0xE55F, 0x932A, 0xE560,
+	0x932B, 0xE561, 0x932C, 0xE562, 0x932D, 0xE563, 0x932E, 0xE564,	0x932F, 0xE565, 0x9330, 0xE566, 0x9331, 0xE567, 0x9332, 0xE568,
+	0x9333, 0xE569, 0x9334, 0xE56A, 0x9335, 0xE56B, 0x9336, 0xE56C,	0x9337, 0xE56D, 0x9338, 0xE56E, 0x9339, 0xE56F, 0x933A, 0xE570,
+	0x933B, 0xE571, 0x933C, 0xE572, 0x933D, 0xE573, 0x933E, 0xF6C9,	0x933F, 0xE574, 0x9340, 0xE575, 0x9341, 0xE576, 0x9342, 0xE577,
+	0x9343, 0xE578, 0x9344, 0xE579, 0x9345, 0xE57A, 0x9346, 0xE57B,	0x9347, 0xE57C, 0x9348, 0xE57D, 0x9349, 0xE57E, 0x934A, 0xE580,
+	0x934B, 0xE581, 0x934C, 0xE582, 0x934D, 0xE583, 0x934E, 0xE584,	0x934F, 0xE585, 0x9350, 0xE586, 0x9351, 0xE587, 0x9352, 0xE588,
+	0x9353, 0xE589, 0x9354, 0xE58A, 0x9355, 0xE58B, 0x9356, 0xE58C,	0x9357, 0xE58D, 0x9358, 0xE58E, 0x9359, 0xE58F, 0x935A, 0xE590,
+	0x935B, 0xE591, 0x935C, 0xE592, 0x935D, 0xE593, 0x935E, 0xE594,	0x935F, 0xE595, 0x9360, 0xE596, 0x9361, 0xE597, 0x9362, 0xE598,
+	0x9363, 0xE599, 0x9364, 0xE59A, 0x9365, 0xE59B, 0x9366, 0xE59C,	0x9367, 0xE59D, 0x9368, 0xE59E, 0x9369, 0xE59F, 0x936A, 0xF6CA,
+	0x936B, 0xE5A0, 0x936C, 0xE640, 0x936D, 0xE641, 0x936E, 0xE642,	0x936F, 0xE643, 0x9370, 0xE644, 0x9371, 0xE645, 0x9372, 0xE646,
+	0x9373, 0xE647, 0x9374, 0xE648, 0x9375, 0xE649, 0x9376, 0xE64A,	0x9377, 0xE64B, 0x9378, 0xE64C, 0x9379, 0xE64D, 0x937A, 0xE64E,
+	0x937B, 0xE64F, 0x937C, 0xE650, 0x937D, 0xE651, 0x937E, 0xE652,	0x937F, 0xE653, 0x9380, 0xE654, 0x9381, 0xE655, 0x9382, 0xE656,
+	0x9383, 0xE657, 0x9384, 0xE658, 0x9385, 0xE659, 0x9386, 0xE65A,	0x9387, 0xE65B, 0x9388, 0xE65C, 0x9389, 0xE65D, 0x938A, 0xE65E,
+	0x938B, 0xE65F, 0x938C, 0xE660, 0x938D, 0xE661, 0x938E, 0xE662,	0x938F, 0xF6CC, 0x9390, 0xE663, 0x9391, 0xE664, 0x9392, 0xE665,
+	0x9393, 0xE666, 0x9394, 0xE667, 0x9395, 0xE668, 0x9396, 0xE669,	0x9397, 0xE66A, 0x9398, 0xE66B, 0x9399, 0xE66C, 0x939A, 0xE66D,
+	0x939B, 0xE66E, 0x939C, 0xE66F, 0x939D, 0xE670, 0x939E, 0xE671,	0x939F, 0xE672, 0x93A0, 0xE673, 0x93A1, 0xE674, 0x93A2, 0xE675,
+	0x93A3, 0xE676, 0x93A4, 0xE677, 0x93A5, 0xE678, 0x93A6, 0xE679,	0x93A7, 0xE67A, 0x93A8, 0xE67B, 0x93A9, 0xE67C, 0x93AA, 0xE67D,
+	0x93AB, 0xE67E, 0x93AC, 0xE680, 0x93AD, 0xE681, 0x93AE, 0xE682,	0x93AF, 0xE683, 0x93B0, 0xE684, 0x93B1, 0xE685, 0x93B2, 0xE686,
+	0x93B3, 0xE687, 0x93B4, 0xE688, 0x93B5, 0xE689, 0x93B6, 0xE68A,	0x93B7, 0xE68B, 0x93B8, 0xE68C, 0x93B9, 0xE68D, 0x93BA, 0xE68E,
+	0x93BB, 0xE68F, 0x93BC, 0xE690, 0x93BD, 0xE691, 0x93BE, 0xE692,	0x93BF, 0xE693, 0x93C0, 0xE694, 0x93C1, 0xE695, 0x93C2, 0xE696,
+	0x93C3, 0xE697, 0x93C4, 0xE698, 0x93C5, 0xE699, 0x93C6, 0xE69A,	0x93C7, 0xE69B, 0x93C8, 0xE69C, 0x93C9, 0xE69D, 0x93CA, 0xF6CB,
+	0x93CB, 0xE69E, 0x93CC, 0xE69F, 0x93CD, 0xE6A0, 0x93CE, 0xE740,	0x93CF, 0xE741, 0x93D0, 0xE742, 0x93D1, 0xE743, 0x93D2, 0xE744,
+	0x93D3, 0xE745, 0x93D4, 0xE746, 0x93D5, 0xE747, 0x93D6, 0xF7E9,	0x93D7, 0xE748, 0x93D8, 0xE749, 0x93D9, 0xE74A, 0x93DA, 0xE74B,
+	0x93DB, 0xE74C, 0x93DC, 0xE74D, 0x93DD, 0xE74E, 0x93DE, 0xE74F,	0x93DF, 0xE750, 0x93E0, 0xE751, 0x93E1, 0xE752, 0x93E2, 0xE753,
+	0x93E3, 0xE754, 0x93E4, 0xE755, 0x93E5, 0xE756, 0x93E6, 0xE757,	0x93E7, 0xE758, 0x93E8, 0xE759, 0x93E9, 0xE75A, 0x93EA, 0xE75B,
+	0x93EB, 0xE75C, 0x93EC, 0xE75D, 0x93ED, 0xE75E, 0x93EE, 0xE75F,	0x93EF, 0xE760, 0x93F0, 0xE761, 0x93F1, 0xE762, 0x93F2, 0xE763,
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+	0x999B, 0xF143, 0x999C, 0xF144, 0x999D, 0xF145, 0x999E, 0xF146,	0x999F, 0xF147, 0x99A0, 0xF148, 0x99A1, 0xF149, 0x99A2, 0xF14A,
+	0x99A3, 0xF14B, 0x99A4, 0xF14C, 0x99A5, 0xF0A5, 0x99A6, 0xF14D,	0x99A7, 0xF14E, 0x99A8, 0xDCB0, 0x99A9, 0xF14F, 0x99AA, 0xF150,
+	0x99AB, 0xF151, 0x99AC, 0xF152, 0x99AD, 0xF153, 0x99AE, 0xF154,	0x99AF, 0xF155, 0x99B0, 0xF156, 0x99B1, 0xF157, 0x99B2, 0xF158,
+	0x99B3, 0xF159, 0x99B4, 0xF15A, 0x99B5, 0xF15B, 0x99B6, 0xF15C,	0x99B7, 0xF15D, 0x99B8, 0xF15E, 0x99B9, 0xF15F, 0x99BA, 0xF160,
+	0x99BB, 0xF161, 0x99BC, 0xF162, 0x99BD, 0xF163, 0x99BE, 0xF164,	0x99BF, 0xF165, 0x99C0, 0xF166, 0x99C1, 0xF167, 0x99C2, 0xF168,
+	0x99C3, 0xF169, 0x99C4, 0xF16A, 0x99C5, 0xF16B, 0x99C6, 0xF16C,	0x99C7, 0xF16D, 0x99C8, 0xF16E, 0x99C9, 0xF16F, 0x99CA, 0xF170,
+	0x99CB, 0xF171, 0x99CC, 0xF172, 0x99CD, 0xF173, 0x99CE, 0xF174,	0x99CF, 0xF175, 0x99D0, 0xF176, 0x99D1, 0xF177, 0x99D2, 0xF178,
+	0x99D3, 0xF179, 0x99D4, 0xF17A, 0x99D5, 0xF17B, 0x99D6, 0xF17C,	0x99D7, 0xF17D, 0x99D8, 0xF17E, 0x99D9, 0xF180, 0x99DA, 0xF181,
+	0x99DB, 0xF182, 0x99DC, 0xF183, 0x99DD, 0xF184, 0x99DE, 0xF185,	0x99DF, 0xF186, 0x99E0, 0xF187, 0x99E1, 0xF188, 0x99E2, 0xF189,
+	0x99E3, 0xF18A, 0x99E4, 0xF18B, 0x99E5, 0xF18C, 0x99E6, 0xF18D,	0x99E7, 0xF18E, 0x99E8, 0xF18F, 0x99E9, 0xF190, 0x99EA, 0xF191,
+	0x99EB, 0xF192, 0x99EC, 0xF193, 0x99ED, 0xF194, 0x99EE, 0xF195,	0x99EF, 0xF196, 0x99F0, 0xF197, 0x99F1, 0xF198, 0x99F2, 0xF199,
+	0x99F3, 0xF19A, 0x99F4, 0xF19B, 0x99F5, 0xF19C, 0x99F6, 0xF19D,	0x99F7, 0xF19E, 0x99F8, 0xF19F, 0x99F9, 0xF1A0, 0x99FA, 0xF240,
+	0x99FB, 0xF241, 0x99FC, 0xF242, 0x99FD, 0xF243, 0x99FE, 0xF244,	0x99FF, 0xF245, 0x9A00, 0xF246, 0x9A01, 0xF247, 0x9A02, 0xF248,
+	0x9A03, 0xF249, 0x9A04, 0xF24A, 0x9A05, 0xF24B, 0x9A06, 0xF24C,	0x9A07, 0xF24D, 0x9A08, 0xF24E, 0x9A09, 0xF24F, 0x9A0A, 0xF250,
+	0x9A0B, 0xF251, 0x9A0C, 0xF252, 0x9A0D, 0xF253, 0x9A0E, 0xF254,	0x9A0F, 0xF255, 0x9A10, 0xF256, 0x9A11, 0xF257, 0x9A12, 0xF258,
+	0x9A13, 0xF259, 0x9A14, 0xF25A, 0x9A15, 0xF25B, 0x9A16, 0xF25C,	0x9A17, 0xF25D, 0x9A18, 0xF25E, 0x9A19, 0xF25F, 0x9A1A, 0xF260,
+	0x9A1B, 0xF261, 0x9A1C, 0xF262, 0x9A1D, 0xF263, 0x9A1E, 0xF264,	0x9A1F, 0xF265, 0x9A20, 0xF266, 0x9A21, 0xF267, 0x9A22, 0xF268,
+	0x9A23, 0xF269, 0x9A24, 0xF26A, 0x9A25, 0xF26B, 0x9A26, 0xF26C,	0x9A27, 0xF26D, 0x9A28, 0xF26E, 0x9A29, 0xF26F, 0x9A2A, 0xF270,
+	0x9A2B, 0xF271, 0x9A2C, 0xF272, 0x9A2D, 0xF273, 0x9A2E, 0xF274,	0x9A2F, 0xF275, 0x9A30, 0xF276, 0x9A31, 0xF277, 0x9A32, 0xF278,
+	0x9A33, 0xF279, 0x9A34, 0xF27A, 0x9A35, 0xF27B, 0x9A36, 0xF27C,	0x9A37, 0xF27D, 0x9A38, 0xF27E, 0x9A39, 0xF280, 0x9A3A, 0xF281,
+	0x9A3B, 0xF282, 0x9A3C, 0xF283, 0x9A3D, 0xF284, 0x9A3E, 0xF285,	0x9A3F, 0xF286, 0x9A40, 0xF287, 0x9A41, 0xF288, 0x9A42, 0xF289,
+	0x9A43, 0xF28A, 0x9A44, 0xF28B, 0x9A45, 0xF28C, 0x9A46, 0xF28D,	0x9A47, 0xF28E, 0x9A48, 0xF28F, 0x9A49, 0xF290, 0x9A4A, 0xF291,
+	0x9A4B, 0xF292, 0x9A4C, 0xF293, 0x9A4D, 0xF294, 0x9A4E, 0xF295,	0x9A4F, 0xF296, 0x9A50, 0xF297, 0x9A51, 0xF298, 0x9A52, 0xF299,
+	0x9A53, 0xF29A, 0x9A54, 0xF29B, 0x9A55, 0xF29C, 0x9A56, 0xF29D,	0x9A57, 0xF29E, 0x9A58, 0xF29F, 0x9A59, 0xF2A0, 0x9A5A, 0xF340,
+	0x9A5B, 0xF341, 0x9A5C, 0xF342, 0x9A5D, 0xF343, 0x9A5E, 0xF344,	0x9A5F, 0xF345, 0x9A60, 0xF346, 0x9A61, 0xF347, 0x9A62, 0xF348,
+	0x9A63, 0xF349, 0x9A64, 0xF34A, 0x9A65, 0xF34B, 0x9A66, 0xF34C,	0x9A67, 0xF34D, 0x9A68, 0xF34E, 0x9A69, 0xF34F, 0x9A6A, 0xF350,
+	0x9A6B, 0xF351, 0x9A6C, 0xC2ED, 0x9A6D, 0xD4A6, 0x9A6E, 0xCDD4,	0x9A6F, 0xD1B1, 0x9A70, 0xB3DB, 0x9A71, 0xC7FD, 0x9A72, 0xF352,
+	0x9A73, 0xB2B5, 0x9A74, 0xC2BF, 0x9A75, 0xE6E0, 0x9A76, 0xCABB,	0x9A77, 0xE6E1, 0x9A78, 0xE6E2, 0x9A79, 0xBED4, 0x9A7A, 0xE6E3,
+	0x9A7B, 0xD7A4, 0x9A7C, 0xCDD5, 0x9A7D, 0xE6E5, 0x9A7E, 0xBCDD,	0x9A7F, 0xE6E4, 0x9A80, 0xE6E6, 0x9A81, 0xE6E7, 0x9A82, 0xC2EE,
+	0x9A83, 0xF353, 0x9A84, 0xBDBE, 0x9A85, 0xE6E8, 0x9A86, 0xC2E6,	0x9A87, 0xBAA7, 0x9A88, 0xE6E9, 0x9A89, 0xF354, 0x9A8A, 0xE6EA,
+	0x9A8B, 0xB3D2, 0x9A8C, 0xD1E9, 0x9A8D, 0xF355, 0x9A8E, 0xF356,	0x9A8F, 0xBFA5, 0x9A90, 0xE6EB, 0x9A91, 0xC6EF, 0x9A92, 0xE6EC,
+	0x9A93, 0xE6ED, 0x9A94, 0xF357, 0x9A95, 0xF358, 0x9A96, 0xE6EE,	0x9A97, 0xC6AD, 0x9A98, 0xE6EF, 0x9A99, 0xF359, 0x9A9A, 0xC9A7,
+	0x9A9B, 0xE6F0, 0x9A9C, 0xE6F1, 0x9A9D, 0xE6F2, 0x9A9E, 0xE5B9,	0x9A9F, 0xE6F3, 0x9AA0, 0xE6F4, 0x9AA1, 0xC2E2, 0x9AA2, 0xE6F5,
+	0x9AA3, 0xE6F6, 0x9AA4, 0xD6E8, 0x9AA5, 0xE6F7, 0x9AA6, 0xF35A,	0x9AA7, 0xE6F8, 0x9AA8, 0xB9C7, 0x9AA9, 0xF35B, 0x9AAA, 0xF35C,
+	0x9AAB, 0xF35D, 0x9AAC, 0xF35E, 0x9AAD, 0xF35F, 0x9AAE, 0xF360,	0x9AAF, 0xF361, 0x9AB0, 0xF7BB, 0x9AB1, 0xF7BA, 0x9AB2, 0xF362,
+	0x9AB3, 0xF363, 0x9AB4, 0xF364, 0x9AB5, 0xF365, 0x9AB6, 0xF7BE,	0x9AB7, 0xF7BC, 0x9AB8, 0xBAA1, 0x9AB9, 0xF366, 0x9ABA, 0xF7BF,
+	0x9ABB, 0xF367, 0x9ABC, 0xF7C0, 0x9ABD, 0xF368, 0x9ABE, 0xF369,	0x9ABF, 0xF36A, 0x9AC0, 0xF7C2, 0x9AC1, 0xF7C1, 0x9AC2, 0xF7C4,
+	0x9AC3, 0xF36B, 0x9AC4, 0xF36C, 0x9AC5, 0xF7C3, 0x9AC6, 0xF36D,	0x9AC7, 0xF36E, 0x9AC8, 0xF36F, 0x9AC9, 0xF370, 0x9ACA, 0xF371,
+	0x9ACB, 0xF7C5, 0x9ACC, 0xF7C6, 0x9ACD, 0xF372, 0x9ACE, 0xF373,	0x9ACF, 0xF374, 0x9AD0, 0xF375, 0x9AD1, 0xF7C7, 0x9AD2, 0xF376,
+	0x9AD3, 0xCBE8, 0x9AD4, 0xF377, 0x9AD5, 0xF378, 0x9AD6, 0xF379,	0x9AD7, 0xF37A, 0x9AD8, 0xB8DF, 0x9AD9, 0xF37B, 0x9ADA, 0xF37C,
+	0x9ADB, 0xF37D, 0x9ADC, 0xF37E, 0x9ADD, 0xF380, 0x9ADE, 0xF381,	0x9ADF, 0xF7D4, 0x9AE0, 0xF382, 0x9AE1, 0xF7D5, 0x9AE2, 0xF383,
+	0x9AE3, 0xF384, 0x9AE4, 0xF385, 0x9AE5, 0xF386, 0x9AE6, 0xF7D6,	0x9AE7, 0xF387, 0x9AE8, 0xF388, 0x9AE9, 0xF389, 0x9AEA, 0xF38A,
+	0x9AEB, 0xF7D8, 0x9AEC, 0xF38B, 0x9AED, 0xF7DA, 0x9AEE, 0xF38C,	0x9AEF, 0xF7D7, 0x9AF0, 0xF38D, 0x9AF1, 0xF38E, 0x9AF2, 0xF38F,
+	0x9AF3, 0xF390, 0x9AF4, 0xF391, 0x9AF5, 0xF392, 0x9AF6, 0xF393,	0x9AF7, 0xF394, 0x9AF8, 0xF395, 0x9AF9, 0xF7DB, 0x9AFA, 0xF396,
+	0x9AFB, 0xF7D9, 0x9AFC, 0xF397, 0x9AFD, 0xF398, 0x9AFE, 0xF399,	0x9AFF, 0xF39A, 0x9B00, 0xF39B, 0x9B01, 0xF39C, 0x9B02, 0xF39D,
+	0x9B03, 0xD7D7, 0x9B04, 0xF39E, 0x9B05, 0xF39F, 0x9B06, 0xF3A0,	0x9B07, 0xF440, 0x9B08, 0xF7DC, 0x9B09, 0xF441, 0x9B0A, 0xF442,
+	0x9B0B, 0xF443, 0x9B0C, 0xF444, 0x9B0D, 0xF445, 0x9B0E, 0xF446,	0x9B0F, 0xF7DD, 0x9B10, 0xF447, 0x9B11, 0xF448, 0x9B12, 0xF449,
+	0x9B13, 0xF7DE, 0x9B14, 0xF44A, 0x9B15, 0xF44B, 0x9B16, 0xF44C,	0x9B17, 0xF44D, 0x9B18, 0xF44E, 0x9B19, 0xF44F, 0x9B1A, 0xF450,
+	0x9B1B, 0xF451, 0x9B1C, 0xF452, 0x9B1D, 0xF453, 0x9B1E, 0xF454,	0x9B1F, 0xF7DF, 0x9B20, 0xF455, 0x9B21, 0xF456, 0x9B22, 0xF457,
+	0x9B23, 0xF7E0, 0x9B24, 0xF458, 0x9B25, 0xF459, 0x9B26, 0xF45A,	0x9B27, 0xF45B, 0x9B28, 0xF45C, 0x9B29, 0xF45D, 0x9B2A, 0xF45E,
+	0x9B2B, 0xF45F, 0x9B2C, 0xF460, 0x9B2D, 0xF461, 0x9B2E, 0xF462,	0x9B2F, 0xDBCB, 0x9B30, 0xF463, 0x9B31, 0xF464, 0x9B32, 0xD8AA,
+	0x9B33, 0xF465, 0x9B34, 0xF466, 0x9B35, 0xF467, 0x9B36, 0xF468,	0x9B37, 0xF469, 0x9B38, 0xF46A, 0x9B39, 0xF46B, 0x9B3A, 0xF46C,
+	0x9B3B, 0xE5F7, 0x9B3C, 0xB9ED, 0x9B3D, 0xF46D, 0x9B3E, 0xF46E,	0x9B3F, 0xF46F, 0x9B40, 0xF470, 0x9B41, 0xBFFD, 0x9B42, 0xBBEA,
+	0x9B43, 0xF7C9, 0x9B44, 0xC6C7, 0x9B45, 0xF7C8, 0x9B46, 0xF471,	0x9B47, 0xF7CA, 0x9B48, 0xF7CC, 0x9B49, 0xF7CB, 0x9B4A, 0xF472,
+	0x9B4B, 0xF473, 0x9B4C, 0xF474, 0x9B4D, 0xF7CD, 0x9B4E, 0xF475,	0x9B4F, 0xCEBA, 0x9B50, 0xF476, 0x9B51, 0xF7CE, 0x9B52, 0xF477,
+	0x9B53, 0xF478, 0x9B54, 0xC4A7, 0x9B55, 0xF479, 0x9B56, 0xF47A,	0x9B57, 0xF47B, 0x9B58, 0xF47C, 0x9B59, 0xF47D, 0x9B5A, 0xF47E,
+	0x9B5B, 0xF480, 0x9B5C, 0xF481, 0x9B5D, 0xF482, 0x9B5E, 0xF483,	0x9B5F, 0xF484, 0x9B60, 0xF485, 0x9B61, 0xF486, 0x9B62, 0xF487,
+	0x9B63, 0xF488, 0x9B64, 0xF489, 0x9B65, 0xF48A, 0x9B66, 0xF48B,	0x9B67, 0xF48C, 0x9B68, 0xF48D, 0x9B69, 0xF48E, 0x9B6A, 0xF48F,
+	0x9B6B, 0xF490, 0x9B6C, 0xF491, 0x9B6D, 0xF492, 0x9B6E, 0xF493,	0x9B6F, 0xF494, 0x9B70, 0xF495, 0x9B71, 0xF496, 0x9B72, 0xF497,
+	0x9B73, 0xF498, 0x9B74, 0xF499, 0x9B75, 0xF49A, 0x9B76, 0xF49B,	0x9B77, 0xF49C, 0x9B78, 0xF49D, 0x9B79, 0xF49E, 0x9B7A, 0xF49F,
+	0x9B7B, 0xF4A0, 0x9B7C, 0xF540, 0x9B7D, 0xF541, 0x9B7E, 0xF542,	0x9B7F, 0xF543, 0x9B80, 0xF544, 0x9B81, 0xF545, 0x9B82, 0xF546,
+	0x9B83, 0xF547, 0x9B84, 0xF548, 0x9B85, 0xF549, 0x9B86, 0xF54A,	0x9B87, 0xF54B, 0x9B88, 0xF54C, 0x9B89, 0xF54D, 0x9B8A, 0xF54E,
+	0x9B8B, 0xF54F, 0x9B8C, 0xF550, 0x9B8D, 0xF551, 0x9B8E, 0xF552,	0x9B8F, 0xF553, 0x9B90, 0xF554, 0x9B91, 0xF555, 0x9B92, 0xF556,
+	0x9B93, 0xF557, 0x9B94, 0xF558, 0x9B95, 0xF559, 0x9B96, 0xF55A,	0x9B97, 0xF55B, 0x9B98, 0xF55C, 0x9B99, 0xF55D, 0x9B9A, 0xF55E,
+	0x9B9B, 0xF55F, 0x9B9C, 0xF560, 0x9B9D, 0xF561, 0x9B9E, 0xF562,	0x9B9F, 0xF563, 0x9BA0, 0xF564, 0x9BA1, 0xF565, 0x9BA2, 0xF566,
+	0x9BA3, 0xF567, 0x9BA4, 0xF568, 0x9BA5, 0xF569, 0x9BA6, 0xF56A,	0x9BA7, 0xF56B, 0x9BA8, 0xF56C, 0x9BA9, 0xF56D, 0x9BAA, 0xF56E,
+	0x9BAB, 0xF56F, 0x9BAC, 0xF570, 0x9BAD, 0xF571, 0x9BAE, 0xF572,	0x9BAF, 0xF573, 0x9BB0, 0xF574, 0x9BB1, 0xF575, 0x9BB2, 0xF576,
+	0x9BB3, 0xF577, 0x9BB4, 0xF578, 0x9BB5, 0xF579, 0x9BB6, 0xF57A,	0x9BB7, 0xF57B, 0x9BB8, 0xF57C, 0x9BB9, 0xF57D, 0x9BBA, 0xF57E,
+	0x9BBB, 0xF580, 0x9BBC, 0xF581, 0x9BBD, 0xF582, 0x9BBE, 0xF583,	0x9BBF, 0xF584, 0x9BC0, 0xF585, 0x9BC1, 0xF586, 0x9BC2, 0xF587,
+	0x9BC3, 0xF588, 0x9BC4, 0xF589, 0x9BC5, 0xF58A, 0x9BC6, 0xF58B,	0x9BC7, 0xF58C, 0x9BC8, 0xF58D, 0x9BC9, 0xF58E, 0x9BCA, 0xF58F,
+	0x9BCB, 0xF590, 0x9BCC, 0xF591, 0x9BCD, 0xF592, 0x9BCE, 0xF593,	0x9BCF, 0xF594, 0x9BD0, 0xF595, 0x9BD1, 0xF596, 0x9BD2, 0xF597,
+	0x9BD3, 0xF598, 0x9BD4, 0xF599, 0x9BD5, 0xF59A, 0x9BD6, 0xF59B,	0x9BD7, 0xF59C, 0x9BD8, 0xF59D, 0x9BD9, 0xF59E, 0x9BDA, 0xF59F,
+	0x9BDB, 0xF5A0, 0x9BDC, 0xF640, 0x9BDD, 0xF641, 0x9BDE, 0xF642,	0x9BDF, 0xF643, 0x9BE0, 0xF644, 0x9BE1, 0xF645, 0x9BE2, 0xF646,
+	0x9BE3, 0xF647, 0x9BE4, 0xF648, 0x9BE5, 0xF649, 0x9BE6, 0xF64A,	0x9BE7, 0xF64B, 0x9BE8, 0xF64C, 0x9BE9, 0xF64D, 0x9BEA, 0xF64E,
+	0x9BEB, 0xF64F, 0x9BEC, 0xF650, 0x9BED, 0xF651, 0x9BEE, 0xF652,	0x9BEF, 0xF653, 0x9BF0, 0xF654, 0x9BF1, 0xF655, 0x9BF2, 0xF656,
+	0x9BF3, 0xF657, 0x9BF4, 0xF658, 0x9BF5, 0xF659, 0x9BF6, 0xF65A,	0x9BF7, 0xF65B, 0x9BF8, 0xF65C, 0x9BF9, 0xF65D, 0x9BFA, 0xF65E,
+	0x9BFB, 0xF65F, 0x9BFC, 0xF660, 0x9BFD, 0xF661, 0x9BFE, 0xF662,	0x9BFF, 0xF663, 0x9C00, 0xF664, 0x9C01, 0xF665, 0x9C02, 0xF666,
+	0x9C03, 0xF667, 0x9C04, 0xF668, 0x9C05, 0xF669, 0x9C06, 0xF66A,	0x9C07, 0xF66B, 0x9C08, 0xF66C, 0x9C09, 0xF66D, 0x9C0A, 0xF66E,
+	0x9C0B, 0xF66F, 0x9C0C, 0xF670, 0x9C0D, 0xF671, 0x9C0E, 0xF672,	0x9C0F, 0xF673, 0x9C10, 0xF674, 0x9C11, 0xF675, 0x9C12, 0xF676,
+	0x9C13, 0xF677, 0x9C14, 0xF678, 0x9C15, 0xF679, 0x9C16, 0xF67A,	0x9C17, 0xF67B, 0x9C18, 0xF67C, 0x9C19, 0xF67D, 0x9C1A, 0xF67E,
+	0x9C1B, 0xF680, 0x9C1C, 0xF681, 0x9C1D, 0xF682, 0x9C1E, 0xF683,	0x9C1F, 0xF684, 0x9C20, 0xF685, 0x9C21, 0xF686, 0x9C22, 0xF687,
+	0x9C23, 0xF688, 0x9C24, 0xF689, 0x9C25, 0xF68A, 0x9C26, 0xF68B,	0x9C27, 0xF68C, 0x9C28, 0xF68D, 0x9C29, 0xF68E, 0x9C2A, 0xF68F,
+	0x9C2B, 0xF690, 0x9C2C, 0xF691, 0x9C2D, 0xF692, 0x9C2E, 0xF693,	0x9C2F, 0xF694, 0x9C30, 0xF695, 0x9C31, 0xF696, 0x9C32, 0xF697,
+	0x9C33, 0xF698, 0x9C34, 0xF699, 0x9C35, 0xF69A, 0x9C36, 0xF69B,	0x9C37, 0xF69C, 0x9C38, 0xF69D, 0x9C39, 0xF69E, 0x9C3A, 0xF69F,
+	0x9C3B, 0xF6A0, 0x9C3C, 0xF740, 0x9C3D, 0xF741, 0x9C3E, 0xF742,	0x9C3F, 0xF743, 0x9C40, 0xF744, 0x9C41, 0xF745, 0x9C42, 0xF746,
+	0x9C43, 0xF747, 0x9C44, 0xF748, 0x9C45, 0xF749, 0x9C46, 0xF74A,	0x9C47, 0xF74B, 0x9C48, 0xF74C, 0x9C49, 0xF74D, 0x9C4A, 0xF74E,
+	0x9C4B, 0xF74F, 0x9C4C, 0xF750, 0x9C4D, 0xF751, 0x9C4E, 0xF752,	0x9C4F, 0xF753, 0x9C50, 0xF754, 0x9C51, 0xF755, 0x9C52, 0xF756,
+	0x9C53, 0xF757, 0x9C54, 0xF758, 0x9C55, 0xF759, 0x9C56, 0xF75A,	0x9C57, 0xF75B, 0x9C58, 0xF75C, 0x9C59, 0xF75D, 0x9C5A, 0xF75E,
+	0x9C5B, 0xF75F, 0x9C5C, 0xF760, 0x9C5D, 0xF761, 0x9C5E, 0xF762,	0x9C5F, 0xF763, 0x9C60, 0xF764, 0x9C61, 0xF765, 0x9C62, 0xF766,
+	0x9C63, 0xF767, 0x9C64, 0xF768, 0x9C65, 0xF769, 0x9C66, 0xF76A,	0x9C67, 0xF76B, 0x9C68, 0xF76C, 0x9C69, 0xF76D, 0x9C6A, 0xF76E,
+	0x9C6B, 0xF76F, 0x9C6C, 0xF770, 0x9C6D, 0xF771, 0x9C6E, 0xF772,	0x9C6F, 0xF773, 0x9C70, 0xF774, 0x9C71, 0xF775, 0x9C72, 0xF776,
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+	0x9C7B, 0xF780, 0x9C7C, 0xD3E3, 0x9C7D, 0xF781, 0x9C7E, 0xF782,	0x9C7F, 0xF6CF, 0x9C80, 0xF783, 0x9C81, 0xC2B3, 0x9C82, 0xF6D0,
+	0x9C83, 0xF784, 0x9C84, 0xF785, 0x9C85, 0xF6D1, 0x9C86, 0xF6D2,	0x9C87, 0xF6D3, 0x9C88, 0xF6D4, 0x9C89, 0xF786, 0x9C8A, 0xF787,
+	0x9C8B, 0xF6D6, 0x9C8C, 0xF788, 0x9C8D, 0xB1AB, 0x9C8E, 0xF6D7,	0x9C8F, 0xF789, 0x9C90, 0xF6D8, 0x9C91, 0xF6D9, 0x9C92, 0xF6DA,
+	0x9C93, 0xF78A, 0x9C94, 0xF6DB, 0x9C95, 0xF6DC, 0x9C96, 0xF78B,	0x9C97, 0xF78C, 0x9C98, 0xF78D, 0x9C99, 0xF78E, 0x9C9A, 0xF6DD,
+	0x9C9B, 0xF6DE, 0x9C9C, 0xCFCA, 0x9C9D, 0xF78F, 0x9C9E, 0xF6DF,	0x9C9F, 0xF6E0, 0x9CA0, 0xF6E1, 0x9CA1, 0xF6E2, 0x9CA2, 0xF6E3,
+	0x9CA3, 0xF6E4, 0x9CA4, 0xC0F0, 0x9CA5, 0xF6E5, 0x9CA6, 0xF6E6,	0x9CA7, 0xF6E7, 0x9CA8, 0xF6E8, 0x9CA9, 0xF6E9, 0x9CAA, 0xF790,
+	0x9CAB, 0xF6EA, 0x9CAC, 0xF791, 0x9CAD, 0xF6EB, 0x9CAE, 0xF6EC,	0x9CAF, 0xF792, 0x9CB0, 0xF6ED, 0x9CB1, 0xF6EE, 0x9CB2, 0xF6EF,
+	0x9CB3, 0xF6F0, 0x9CB4, 0xF6F1, 0x9CB5, 0xF6F2, 0x9CB6, 0xF6F3,	0x9CB7, 0xF6F4, 0x9CB8, 0xBEA8, 0x9CB9, 0xF793, 0x9CBA, 0xF6F5,
+	0x9CBB, 0xF6F6, 0x9CBC, 0xF6F7, 0x9CBD, 0xF6F8, 0x9CBE, 0xF794,	0x9CBF, 0xF795, 0x9CC0, 0xF796, 0x9CC1, 0xF797, 0x9CC2, 0xF798,
+	0x9CC3, 0xC8FA, 0x9CC4, 0xF6F9, 0x9CC5, 0xF6FA, 0x9CC6, 0xF6FB,	0x9CC7, 0xF6FC, 0x9CC8, 0xF799, 0x9CC9, 0xF79A, 0x9CCA, 0xF6FD,
+	0x9CCB, 0xF6FE, 0x9CCC, 0xF7A1, 0x9CCD, 0xF7A2, 0x9CCE, 0xF7A3,	0x9CCF, 0xF7A4, 0x9CD0, 0xF7A5, 0x9CD1, 0xF79B, 0x9CD2, 0xF79C,
+	0x9CD3, 0xF7A6, 0x9CD4, 0xF7A7, 0x9CD5, 0xF7A8, 0x9CD6, 0xB1EE,	0x9CD7, 0xF7A9, 0x9CD8, 0xF7AA, 0x9CD9, 0xF7AB, 0x9CDA, 0xF79D,
+	0x9CDB, 0xF79E, 0x9CDC, 0xF7AC, 0x9CDD, 0xF7AD, 0x9CDE, 0xC1DB,	0x9CDF, 0xF7AE, 0x9CE0, 0xF79F, 0x9CE1, 0xF7A0, 0x9CE2, 0xF7AF,
+	0x9CE3, 0xF840, 0x9CE4, 0xF841, 0x9CE5, 0xF842, 0x9CE6, 0xF843,	0x9CE7, 0xF844, 0x9CE8, 0xF845, 0x9CE9, 0xF846, 0x9CEA, 0xF847,
+	0x9CEB, 0xF848, 0x9CEC, 0xF849, 0x9CED, 0xF84A, 0x9CEE, 0xF84B,	0x9CEF, 0xF84C, 0x9CF0, 0xF84D, 0x9CF1, 0xF84E, 0x9CF2, 0xF84F,
+	0x9CF3, 0xF850, 0x9CF4, 0xF851, 0x9CF5, 0xF852, 0x9CF6, 0xF853,	0x9CF7, 0xF854, 0x9CF8, 0xF855, 0x9CF9, 0xF856, 0x9CFA, 0xF857,
+	0x9CFB, 0xF858, 0x9CFC, 0xF859, 0x9CFD, 0xF85A, 0x9CFE, 0xF85B,	0x9CFF, 0xF85C, 0x9D00, 0xF85D, 0x9D01, 0xF85E, 0x9D02, 0xF85F,
+	0x9D03, 0xF860, 0x9D04, 0xF861, 0x9D05, 0xF862, 0x9D06, 0xF863,	0x9D07, 0xF864, 0x9D08, 0xF865, 0x9D09, 0xF866, 0x9D0A, 0xF867,
+	0x9D0B, 0xF868, 0x9D0C, 0xF869, 0x9D0D, 0xF86A, 0x9D0E, 0xF86B,	0x9D0F, 0xF86C, 0x9D10, 0xF86D, 0x9D11, 0xF86E, 0x9D12, 0xF86F,
+	0x9D13, 0xF870, 0x9D14, 0xF871, 0x9D15, 0xF872, 0x9D16, 0xF873,	0x9D17, 0xF874, 0x9D18, 0xF875, 0x9D19, 0xF876, 0x9D1A, 0xF877,
+	0x9D1B, 0xF878, 0x9D1C, 0xF879, 0x9D1D, 0xF87A, 0x9D1E, 0xF87B,	0x9D1F, 0xF87C, 0x9D20, 0xF87D, 0x9D21, 0xF87E, 0x9D22, 0xF880,
+	0x9D23, 0xF881, 0x9D24, 0xF882, 0x9D25, 0xF883, 0x9D26, 0xF884,	0x9D27, 0xF885, 0x9D28, 0xF886, 0x9D29, 0xF887, 0x9D2A, 0xF888,
+	0x9D2B, 0xF889, 0x9D2C, 0xF88A, 0x9D2D, 0xF88B, 0x9D2E, 0xF88C,	0x9D2F, 0xF88D, 0x9D30, 0xF88E, 0x9D31, 0xF88F, 0x9D32, 0xF890,
+	0x9D33, 0xF891, 0x9D34, 0xF892, 0x9D35, 0xF893, 0x9D36, 0xF894,	0x9D37, 0xF895, 0x9D38, 0xF896, 0x9D39, 0xF897, 0x9D3A, 0xF898,
+	0x9D3B, 0xF899, 0x9D3C, 0xF89A, 0x9D3D, 0xF89B, 0x9D3E, 0xF89C,	0x9D3F, 0xF89D, 0x9D40, 0xF89E, 0x9D41, 0xF89F, 0x9D42, 0xF8A0,
+	0x9D43, 0xF940, 0x9D44, 0xF941, 0x9D45, 0xF942, 0x9D46, 0xF943,	0x9D47, 0xF944, 0x9D48, 0xF945, 0x9D49, 0xF946, 0x9D4A, 0xF947,
+	0x9D4B, 0xF948, 0x9D4C, 0xF949, 0x9D4D, 0xF94A, 0x9D4E, 0xF94B,	0x9D4F, 0xF94C, 0x9D50, 0xF94D, 0x9D51, 0xF94E, 0x9D52, 0xF94F,
+	0x9D53, 0xF950, 0x9D54, 0xF951, 0x9D55, 0xF952, 0x9D56, 0xF953,	0x9D57, 0xF954, 0x9D58, 0xF955, 0x9D59, 0xF956, 0x9D5A, 0xF957,
+	0x9D5B, 0xF958, 0x9D5C, 0xF959, 0x9D5D, 0xF95A, 0x9D5E, 0xF95B,	0x9D5F, 0xF95C, 0x9D60, 0xF95D, 0x9D61, 0xF95E, 0x9D62, 0xF95F,
+	0x9D63, 0xF960, 0x9D64, 0xF961, 0x9D65, 0xF962, 0x9D66, 0xF963,	0x9D67, 0xF964, 0x9D68, 0xF965, 0x9D69, 0xF966, 0x9D6A, 0xF967,
+	0x9D6B, 0xF968, 0x9D6C, 0xF969, 0x9D6D, 0xF96A, 0x9D6E, 0xF96B,	0x9D6F, 0xF96C, 0x9D70, 0xF96D, 0x9D71, 0xF96E, 0x9D72, 0xF96F,
+	0x9D73, 0xF970, 0x9D74, 0xF971, 0x9D75, 0xF972, 0x9D76, 0xF973,	0x9D77, 0xF974, 0x9D78, 0xF975, 0x9D79, 0xF976, 0x9D7A, 0xF977,
+	0x9D7B, 0xF978, 0x9D7C, 0xF979, 0x9D7D, 0xF97A, 0x9D7E, 0xF97B,	0x9D7F, 0xF97C, 0x9D80, 0xF97D, 0x9D81, 0xF97E, 0x9D82, 0xF980,
+	0x9D83, 0xF981, 0x9D84, 0xF982, 0x9D85, 0xF983, 0x9D86, 0xF984,	0x9D87, 0xF985, 0x9D88, 0xF986, 0x9D89, 0xF987, 0x9D8A, 0xF988,
+	0x9D8B, 0xF989, 0x9D8C, 0xF98A, 0x9D8D, 0xF98B, 0x9D8E, 0xF98C,	0x9D8F, 0xF98D, 0x9D90, 0xF98E, 0x9D91, 0xF98F, 0x9D92, 0xF990,
+	0x9D93, 0xF991, 0x9D94, 0xF992, 0x9D95, 0xF993, 0x9D96, 0xF994,	0x9D97, 0xF995, 0x9D98, 0xF996, 0x9D99, 0xF997, 0x9D9A, 0xF998,
+	0x9D9B, 0xF999, 0x9D9C, 0xF99A, 0x9D9D, 0xF99B, 0x9D9E, 0xF99C,	0x9D9F, 0xF99D, 0x9DA0, 0xF99E, 0x9DA1, 0xF99F, 0x9DA2, 0xF9A0,
+	0x9DA3, 0xFA40, 0x9DA4, 0xFA41, 0x9DA5, 0xFA42, 0x9DA6, 0xFA43,	0x9DA7, 0xFA44, 0x9DA8, 0xFA45, 0x9DA9, 0xFA46, 0x9DAA, 0xFA47,
+	0x9DAB, 0xFA48, 0x9DAC, 0xFA49, 0x9DAD, 0xFA4A, 0x9DAE, 0xFA4B,	0x9DAF, 0xFA4C, 0x9DB0, 0xFA4D, 0x9DB1, 0xFA4E, 0x9DB2, 0xFA4F,
+	0x9DB3, 0xFA50, 0x9DB4, 0xFA51, 0x9DB5, 0xFA52, 0x9DB6, 0xFA53,	0x9DB7, 0xFA54, 0x9DB8, 0xFA55, 0x9DB9, 0xFA56, 0x9DBA, 0xFA57,
+	0x9DBB, 0xFA58, 0x9DBC, 0xFA59, 0x9DBD, 0xFA5A, 0x9DBE, 0xFA5B,	0x9DBF, 0xFA5C, 0x9DC0, 0xFA5D, 0x9DC1, 0xFA5E, 0x9DC2, 0xFA5F,
+	0x9DC3, 0xFA60, 0x9DC4, 0xFA61, 0x9DC5, 0xFA62, 0x9DC6, 0xFA63,	0x9DC7, 0xFA64, 0x9DC8, 0xFA65, 0x9DC9, 0xFA66, 0x9DCA, 0xFA67,
+	0x9DCB, 0xFA68, 0x9DCC, 0xFA69, 0x9DCD, 0xFA6A, 0x9DCE, 0xFA6B,	0x9DCF, 0xFA6C, 0x9DD0, 0xFA6D, 0x9DD1, 0xFA6E, 0x9DD2, 0xFA6F,
+	0x9DD3, 0xFA70, 0x9DD4, 0xFA71, 0x9DD5, 0xFA72, 0x9DD6, 0xFA73,	0x9DD7, 0xFA74, 0x9DD8, 0xFA75, 0x9DD9, 0xFA76, 0x9DDA, 0xFA77,
+	0x9DDB, 0xFA78, 0x9DDC, 0xFA79, 0x9DDD, 0xFA7A, 0x9DDE, 0xFA7B,	0x9DDF, 0xFA7C, 0x9DE0, 0xFA7D, 0x9DE1, 0xFA7E, 0x9DE2, 0xFA80,
+	0x9DE3, 0xFA81, 0x9DE4, 0xFA82, 0x9DE5, 0xFA83, 0x9DE6, 0xFA84,	0x9DE7, 0xFA85, 0x9DE8, 0xFA86, 0x9DE9, 0xFA87, 0x9DEA, 0xFA88,
+	0x9DEB, 0xFA89, 0x9DEC, 0xFA8A, 0x9DED, 0xFA8B, 0x9DEE, 0xFA8C,	0x9DEF, 0xFA8D, 0x9DF0, 0xFA8E, 0x9DF1, 0xFA8F, 0x9DF2, 0xFA90,
+	0x9DF3, 0xFA91, 0x9DF4, 0xFA92, 0x9DF5, 0xFA93, 0x9DF6, 0xFA94,	0x9DF7, 0xFA95, 0x9DF8, 0xFA96, 0x9DF9, 0xFA97, 0x9DFA, 0xFA98,
+	0x9DFB, 0xFA99, 0x9DFC, 0xFA9A, 0x9DFD, 0xFA9B, 0x9DFE, 0xFA9C,	0x9DFF, 0xFA9D, 0x9E00, 0xFA9E, 0x9E01, 0xFA9F, 0x9E02, 0xFAA0,
+	0x9E03, 0xFB40, 0x9E04, 0xFB41, 0x9E05, 0xFB42, 0x9E06, 0xFB43,	0x9E07, 0xFB44, 0x9E08, 0xFB45, 0x9E09, 0xFB46, 0x9E0A, 0xFB47,
+	0x9E0B, 0xFB48, 0x9E0C, 0xFB49, 0x9E0D, 0xFB4A, 0x9E0E, 0xFB4B,	0x9E0F, 0xFB4C, 0x9E10, 0xFB4D, 0x9E11, 0xFB4E, 0x9E12, 0xFB4F,
+	0x9E13, 0xFB50, 0x9E14, 0xFB51, 0x9E15, 0xFB52, 0x9E16, 0xFB53,	0x9E17, 0xFB54, 0x9E18, 0xFB55, 0x9E19, 0xFB56, 0x9E1A, 0xFB57,
+	0x9E1B, 0xFB58, 0x9E1C, 0xFB59, 0x9E1D, 0xFB5A, 0x9E1E, 0xFB5B,	0x9E1F, 0xC4F1, 0x9E20, 0xF0AF, 0x9E21, 0xBCA6, 0x9E22, 0xF0B0,
+	0x9E23, 0xC3F9, 0x9E24, 0xFB5C, 0x9E25, 0xC5B8, 0x9E26, 0xD1BB,	0x9E27, 0xFB5D, 0x9E28, 0xF0B1, 0x9E29, 0xF0B2, 0x9E2A, 0xF0B3,
+	0x9E2B, 0xF0B4, 0x9E2C, 0xF0B5, 0x9E2D, 0xD1BC, 0x9E2E, 0xFB5E,	0x9E2F, 0xD1EC, 0x9E30, 0xFB5F, 0x9E31, 0xF0B7, 0x9E32, 0xF0B6,
+	0x9E33, 0xD4A7, 0x9E34, 0xFB60, 0x9E35, 0xCDD2, 0x9E36, 0xF0B8,	0x9E37, 0xF0BA, 0x9E38, 0xF0B9, 0x9E39, 0xF0BB, 0x9E3A, 0xF0BC,
+	0x9E3B, 0xFB61, 0x9E3C, 0xFB62, 0x9E3D, 0xB8EB, 0x9E3E, 0xF0BD,	0x9E3F, 0xBAE8, 0x9E40, 0xFB63, 0x9E41, 0xF0BE, 0x9E42, 0xF0BF,
+	0x9E43, 0xBEE9, 0x9E44, 0xF0C0, 0x9E45, 0xB6EC, 0x9E46, 0xF0C1,	0x9E47, 0xF0C2, 0x9E48, 0xF0C3, 0x9E49, 0xF0C4, 0x9E4A, 0xC8B5,
+	0x9E4B, 0xF0C5, 0x9E4C, 0xF0C6, 0x9E4D, 0xFB64, 0x9E4E, 0xF0C7,	0x9E4F, 0xC5F4, 0x9E50, 0xFB65, 0x9E51, 0xF0C8, 0x9E52, 0xFB66,
+	0x9E53, 0xFB67, 0x9E54, 0xFB68, 0x9E55, 0xF0C9, 0x9E56, 0xFB69,	0x9E57, 0xF0CA, 0x9E58, 0xF7BD, 0x9E59, 0xFB6A, 0x9E5A, 0xF0CB,
+	0x9E5B, 0xF0CC, 0x9E5C, 0xF0CD, 0x9E5D, 0xFB6B, 0x9E5E, 0xF0CE,	0x9E5F, 0xFB6C, 0x9E60, 0xFB6D, 0x9E61, 0xFB6E, 0x9E62, 0xFB6F,
+	0x9E63, 0xF0CF, 0x9E64, 0xBAD7, 0x9E65, 0xFB70, 0x9E66, 0xF0D0,	0x9E67, 0xF0D1, 0x9E68, 0xF0D2, 0x9E69, 0xF0D3, 0x9E6A, 0xF0D4,
+	0x9E6B, 0xF0D5, 0x9E6C, 0xF0D6, 0x9E6D, 0xF0D8, 0x9E6E, 0xFB71,	0x9E6F, 0xFB72, 0x9E70, 0xD3A5, 0x9E71, 0xF0D7, 0x9E72, 0xFB73,
+	0x9E73, 0xF0D9, 0x9E74, 0xFB74, 0x9E75, 0xFB75, 0x9E76, 0xFB76,	0x9E77, 0xFB77, 0x9E78, 0xFB78, 0x9E79, 0xFB79, 0x9E7A, 0xFB7A,
+	0x9E7B, 0xFB7B, 0x9E7C, 0xFB7C, 0x9E7D, 0xFB7D, 0x9E7E, 0xF5BA,	0x9E7F, 0xC2B9, 0x9E80, 0xFB7E, 0x9E81, 0xFB80, 0x9E82, 0xF7E4,
+	0x9E83, 0xFB81, 0x9E84, 0xFB82, 0x9E85, 0xFB83, 0x9E86, 0xFB84,	0x9E87, 0xF7E5, 0x9E88, 0xF7E6, 0x9E89, 0xFB85, 0x9E8A, 0xFB86,
+	0x9E8B, 0xF7E7, 0x9E8C, 0xFB87, 0x9E8D, 0xFB88, 0x9E8E, 0xFB89,	0x9E8F, 0xFB8A, 0x9E90, 0xFB8B, 0x9E91, 0xFB8C, 0x9E92, 0xF7E8,
+	0x9E93, 0xC2B4, 0x9E94, 0xFB8D, 0x9E95, 0xFB8E, 0x9E96, 0xFB8F,	0x9E97, 0xFB90, 0x9E98, 0xFB91, 0x9E99, 0xFB92, 0x9E9A, 0xFB93,
+	0x9E9B, 0xFB94, 0x9E9C, 0xFB95, 0x9E9D, 0xF7EA, 0x9E9E, 0xFB96,	0x9E9F, 0xF7EB, 0x9EA0, 0xFB97, 0x9EA1, 0xFB98, 0x9EA2, 0xFB99,
+	0x9EA3, 0xFB9A, 0x9EA4, 0xFB9B, 0x9EA5, 0xFB9C, 0x9EA6, 0xC2F3,	0x9EA7, 0xFB9D, 0x9EA8, 0xFB9E, 0x9EA9, 0xFB9F, 0x9EAA, 0xFBA0,
+	0x9EAB, 0xFC40, 0x9EAC, 0xFC41, 0x9EAD, 0xFC42, 0x9EAE, 0xFC43,	0x9EAF, 0xFC44, 0x9EB0, 0xFC45, 0x9EB1, 0xFC46, 0x9EB2, 0xFC47,
+	0x9EB3, 0xFC48, 0x9EB4, 0xF4F0, 0x9EB5, 0xFC49, 0x9EB6, 0xFC4A,	0x9EB7, 0xFC4B, 0x9EB8, 0xF4EF, 0x9EB9, 0xFC4C, 0x9EBA, 0xFC4D,
+	0x9EBB, 0xC2E9, 0x9EBC, 0xFC4E, 0x9EBD, 0xF7E1, 0x9EBE, 0xF7E2,	0x9EBF, 0xFC4F, 0x9EC0, 0xFC50, 0x9EC1, 0xFC51, 0x9EC2, 0xFC52,
+	0x9EC3, 0xFC53, 0x9EC4, 0xBBC6, 0x9EC5, 0xFC54, 0x9EC6, 0xFC55,	0x9EC7, 0xFC56, 0x9EC8, 0xFC57, 0x9EC9, 0xD9E4, 0x9ECA, 0xFC58,
+	0x9ECB, 0xFC59, 0x9ECC, 0xFC5A, 0x9ECD, 0xCAF2, 0x9ECE, 0xC0E8,	0x9ECF, 0xF0A4, 0x9ED0, 0xFC5B, 0x9ED1, 0xBADA, 0x9ED2, 0xFC5C,
+	0x9ED3, 0xFC5D, 0x9ED4, 0xC7AD, 0x9ED5, 0xFC5E, 0x9ED6, 0xFC5F,	0x9ED7, 0xFC60, 0x9ED8, 0xC4AC, 0x9ED9, 0xFC61, 0x9EDA, 0xFC62,
+	0x9EDB, 0xF7EC, 0x9EDC, 0xF7ED, 0x9EDD, 0xF7EE, 0x9EDE, 0xFC63,	0x9EDF, 0xF7F0, 0x9EE0, 0xF7EF, 0x9EE1, 0xFC64, 0x9EE2, 0xF7F1,
+	0x9EE3, 0xFC65, 0x9EE4, 0xFC66, 0x9EE5, 0xF7F4, 0x9EE6, 0xFC67,	0x9EE7, 0xF7F3, 0x9EE8, 0xFC68, 0x9EE9, 0xF7F2, 0x9EEA, 0xF7F5,
+	0x9EEB, 0xFC69, 0x9EEC, 0xFC6A, 0x9EED, 0xFC6B, 0x9EEE, 0xFC6C,	0x9EEF, 0xF7F6, 0x9EF0, 0xFC6D, 0x9EF1, 0xFC6E, 0x9EF2, 0xFC6F,
+	0x9EF3, 0xFC70, 0x9EF4, 0xFC71, 0x9EF5, 0xFC72, 0x9EF6, 0xFC73,	0x9EF7, 0xFC74, 0x9EF8, 0xFC75, 0x9EF9, 0xEDE9, 0x9EFA, 0xFC76,
+	0x9EFB, 0xEDEA, 0x9EFC, 0xEDEB, 0x9EFD, 0xFC77, 0x9EFE, 0xF6BC,	0x9EFF, 0xFC78, 0x9F00, 0xFC79, 0x9F01, 0xFC7A, 0x9F02, 0xFC7B,
+	0x9F03, 0xFC7C, 0x9F04, 0xFC7D, 0x9F05, 0xFC7E, 0x9F06, 0xFC80,	0x9F07, 0xFC81, 0x9F08, 0xFC82, 0x9F09, 0xFC83, 0x9F0A, 0xFC84,
+	0x9F0B, 0xF6BD, 0x9F0C, 0xFC85, 0x9F0D, 0xF6BE, 0x9F0E, 0xB6A6,	0x9F0F, 0xFC86, 0x9F10, 0xD8BE, 0x9F11, 0xFC87, 0x9F12, 0xFC88,
+	0x9F13, 0xB9C4, 0x9F14, 0xFC89, 0x9F15, 0xFC8A, 0x9F16, 0xFC8B,	0x9F17, 0xD8BB, 0x9F18, 0xFC8C, 0x9F19, 0xDCB1, 0x9F1A, 0xFC8D,
+	0x9F1B, 0xFC8E, 0x9F1C, 0xFC8F, 0x9F1D, 0xFC90, 0x9F1E, 0xFC91,	0x9F1F, 0xFC92, 0x9F20, 0xCAF3, 0x9F21, 0xFC93, 0x9F22, 0xF7F7,
+	0x9F23, 0xFC94, 0x9F24, 0xFC95, 0x9F25, 0xFC96, 0x9F26, 0xFC97,	0x9F27, 0xFC98, 0x9F28, 0xFC99, 0x9F29, 0xFC9A, 0x9F2A, 0xFC9B,
+	0x9F2B, 0xFC9C, 0x9F2C, 0xF7F8, 0x9F2D, 0xFC9D, 0x9F2E, 0xFC9E,	0x9F2F, 0xF7F9, 0x9F30, 0xFC9F, 0x9F31, 0xFCA0, 0x9F32, 0xFD40,
+	0x9F33, 0xFD41, 0x9F34, 0xFD42, 0x9F35, 0xFD43, 0x9F36, 0xFD44,	0x9F37, 0xF7FB, 0x9F38, 0xFD45, 0x9F39, 0xF7FA, 0x9F3A, 0xFD46,
+	0x9F3B, 0xB1C7, 0x9F3C, 0xFD47, 0x9F3D, 0xF7FC, 0x9F3E, 0xF7FD,	0x9F3F, 0xFD48, 0x9F40, 0xFD49, 0x9F41, 0xFD4A, 0x9F42, 0xFD4B,
+	0x9F43, 0xFD4C, 0x9F44, 0xF7FE, 0x9F45, 0xFD4D, 0x9F46, 0xFD4E,	0x9F47, 0xFD4F, 0x9F48, 0xFD50, 0x9F49, 0xFD51, 0x9F4A, 0xFD52,
+	0x9F4B, 0xFD53, 0x9F4C, 0xFD54, 0x9F4D, 0xFD55, 0x9F4E, 0xFD56,	0x9F4F, 0xFD57, 0x9F50, 0xC6EB, 0x9F51, 0xECB4, 0x9F52, 0xFD58,
+	0x9F53, 0xFD59, 0x9F54, 0xFD5A, 0x9F55, 0xFD5B, 0x9F56, 0xFD5C,	0x9F57, 0xFD5D, 0x9F58, 0xFD5E, 0x9F59, 0xFD5F, 0x9F5A, 0xFD60,
+	0x9F5B, 0xFD61, 0x9F5C, 0xFD62, 0x9F5D, 0xFD63, 0x9F5E, 0xFD64,	0x9F5F, 0xFD65, 0x9F60, 0xFD66, 0x9F61, 0xFD67, 0x9F62, 0xFD68,
+	0x9F63, 0xFD69, 0x9F64, 0xFD6A, 0x9F65, 0xFD6B, 0x9F66, 0xFD6C,	0x9F67, 0xFD6D, 0x9F68, 0xFD6E, 0x9F69, 0xFD6F, 0x9F6A, 0xFD70,
+	0x9F6B, 0xFD71, 0x9F6C, 0xFD72, 0x9F6D, 0xFD73, 0x9F6E, 0xFD74,	0x9F6F, 0xFD75, 0x9F70, 0xFD76, 0x9F71, 0xFD77, 0x9F72, 0xFD78,
+	0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C,	0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81,
+	0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85,	0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87,
+	0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6,	0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA,
+	0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89,	0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D,
+	0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91,	0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8,
+	0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96,	0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98,
+	0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C,	0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0,
+	0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43,	0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47,
+	0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B,	0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F,
+	0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5,	0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1,
+	0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF,	0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5,
+	0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB,	0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B,
+	0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F,	0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973,
+	0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977,	0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B,
+	0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980,	0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984,
+	0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988,	0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7,
+	0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8,	0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+	0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0,	0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+	0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8,	0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+	0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0,	0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+	0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8,	0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+	0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0,	0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+	0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8,	0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC,
+	0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0,	0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+	0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8,	0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+	0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0,	0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+	0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8,	0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+	0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA,	0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4,
+	0, 0
+};
+
+static const WCHAR oem2uni936[] = {	/* GBK --> Unicode pairs */
+	0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05,	0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17,
+	0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23,	0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F,
+	0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37,	0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42,
+	0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51,	0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B,
+	0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65,	0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B,
+	0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F,	0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76,
+	0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A,	0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F,
+	0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83,	0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A,
+	0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99,	0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3,
+	0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1,	0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8,
+	0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE,	0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0,
+	0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC,	0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7,
+	0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF,	0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9,
+	0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00,	0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05,
+	0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B,	0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14,
+	0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D,	0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29,
+	0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31,	0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39,
+	0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40,	0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45,
+	0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A,	0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54,
+	0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66,	0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D,
+	0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75,	0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A,
+	0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82,	0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A,
+	0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92,	0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98,
+	0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E,	0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4,
+	0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1,	0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6,
+	0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA,	0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE,
+	0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6,	0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB,
+	0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3,	0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9,
+	0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4,	0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC,
+	0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5,	0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB,
+	0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000,	0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004,
+	0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008,	0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E,
+	0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015,	0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D,
+	0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023,	0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F,
+	0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033,	0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037,
+	0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D,	0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042,
+	0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049,	0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050,
+	0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054,	0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059,
+	0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F,	0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063,
+	0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068,	0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D,
+	0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071,	0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075,
+	0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C,	0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083,
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+	0x9EDA, 0x70A1, 0x9EDB, 0x70A2, 0x9EDC, 0x70A3, 0x9EDD, 0x70A4,	0x9EDE, 0x70A5, 0x9EDF, 0x70A6, 0x9EE0, 0x70A7, 0x9EE1, 0x70A8,
+	0x9EE2, 0x70A9, 0x9EE3, 0x70AA, 0x9EE4, 0x70B0, 0x9EE5, 0x70B2,	0x9EE6, 0x70B4, 0x9EE7, 0x70B5, 0x9EE8, 0x70B6, 0x9EE9, 0x70BA,
+	0x9EEA, 0x70BE, 0x9EEB, 0x70BF, 0x9EEC, 0x70C4, 0x9EED, 0x70C5,	0x9EEE, 0x70C6, 0x9EEF, 0x70C7, 0x9EF0, 0x70C9, 0x9EF1, 0x70CB,
+	0x9EF2, 0x70CC, 0x9EF3, 0x70CD, 0x9EF4, 0x70CE, 0x9EF5, 0x70CF,	0x9EF6, 0x70D0, 0x9EF7, 0x70D1, 0x9EF8, 0x70D2, 0x9EF9, 0x70D3,
+	0x9EFA, 0x70D4, 0x9EFB, 0x70D5, 0x9EFC, 0x70D6, 0x9EFD, 0x70D7,	0x9EFE, 0x70DA, 0x9F40, 0x70DC, 0x9F41, 0x70DD, 0x9F42, 0x70DE,
+	0x9F43, 0x70E0, 0x9F44, 0x70E1, 0x9F45, 0x70E2, 0x9F46, 0x70E3,	0x9F47, 0x70E5, 0x9F48, 0x70EA, 0x9F49, 0x70EE, 0x9F4A, 0x70F0,
+	0x9F4B, 0x70F1, 0x9F4C, 0x70F2, 0x9F4D, 0x70F3, 0x9F4E, 0x70F4,	0x9F4F, 0x70F5, 0x9F50, 0x70F6, 0x9F51, 0x70F8, 0x9F52, 0x70FA,
+	0x9F53, 0x70FB, 0x9F54, 0x70FC, 0x9F55, 0x70FE, 0x9F56, 0x70FF,	0x9F57, 0x7100, 0x9F58, 0x7101, 0x9F59, 0x7102, 0x9F5A, 0x7103,
+	0x9F5B, 0x7104, 0x9F5C, 0x7105, 0x9F5D, 0x7106, 0x9F5E, 0x7107,	0x9F5F, 0x7108, 0x9F60, 0x710B, 0x9F61, 0x710C, 0x9F62, 0x710D,
+	0x9F63, 0x710E, 0x9F64, 0x710F, 0x9F65, 0x7111, 0x9F66, 0x7112,	0x9F67, 0x7114, 0x9F68, 0x7117, 0x9F69, 0x711B, 0x9F6A, 0x711C,
+	0x9F6B, 0x711D, 0x9F6C, 0x711E, 0x9F6D, 0x711F, 0x9F6E, 0x7120,	0x9F6F, 0x7121, 0x9F70, 0x7122, 0x9F71, 0x7123, 0x9F72, 0x7124,
+	0x9F73, 0x7125, 0x9F74, 0x7127, 0x9F75, 0x7128, 0x9F76, 0x7129,	0x9F77, 0x712A, 0x9F78, 0x712B, 0x9F79, 0x712C, 0x9F7A, 0x712D,
+	0x9F7B, 0x712E, 0x9F7C, 0x7132, 0x9F7D, 0x7133, 0x9F7E, 0x7134,	0x9F80, 0x7135, 0x9F81, 0x7137, 0x9F82, 0x7138, 0x9F83, 0x7139,
+	0x9F84, 0x713A, 0x9F85, 0x713B, 0x9F86, 0x713C, 0x9F87, 0x713D,	0x9F88, 0x713E, 0x9F89, 0x713F, 0x9F8A, 0x7140, 0x9F8B, 0x7141,
+	0x9F8C, 0x7142, 0x9F8D, 0x7143, 0x9F8E, 0x7144, 0x9F8F, 0x7146,	0x9F90, 0x7147, 0x9F91, 0x7148, 0x9F92, 0x7149, 0x9F93, 0x714B,
+	0x9F94, 0x714D, 0x9F95, 0x714F, 0x9F96, 0x7150, 0x9F97, 0x7151,	0x9F98, 0x7152, 0x9F99, 0x7153, 0x9F9A, 0x7154, 0x9F9B, 0x7155,
+	0x9F9C, 0x7156, 0x9F9D, 0x7157, 0x9F9E, 0x7158, 0x9F9F, 0x7159,	0x9FA0, 0x715A, 0x9FA1, 0x715B, 0x9FA2, 0x715D, 0x9FA3, 0x715F,
+	0x9FA4, 0x7160, 0x9FA5, 0x7161, 0x9FA6, 0x7162, 0x9FA7, 0x7163,	0x9FA8, 0x7165, 0x9FA9, 0x7169, 0x9FAA, 0x716A, 0x9FAB, 0x716B,
+	0x9FAC, 0x716C, 0x9FAD, 0x716D, 0x9FAE, 0x716F, 0x9FAF, 0x7170,	0x9FB0, 0x7171, 0x9FB1, 0x7174, 0x9FB2, 0x7175, 0x9FB3, 0x7176,
+	0x9FB4, 0x7177, 0x9FB5, 0x7179, 0x9FB6, 0x717B, 0x9FB7, 0x717C,	0x9FB8, 0x717E, 0x9FB9, 0x717F, 0x9FBA, 0x7180, 0x9FBB, 0x7181,
+	0x9FBC, 0x7182, 0x9FBD, 0x7183, 0x9FBE, 0x7185, 0x9FBF, 0x7186,	0x9FC0, 0x7187, 0x9FC1, 0x7188, 0x9FC2, 0x7189, 0x9FC3, 0x718B,
+	0x9FC4, 0x718C, 0x9FC5, 0x718D, 0x9FC6, 0x718E, 0x9FC7, 0x7190,	0x9FC8, 0x7191, 0x9FC9, 0x7192, 0x9FCA, 0x7193, 0x9FCB, 0x7195,
+	0x9FCC, 0x7196, 0x9FCD, 0x7197, 0x9FCE, 0x719A, 0x9FCF, 0x719B,	0x9FD0, 0x719C, 0x9FD1, 0x719D, 0x9FD2, 0x719E, 0x9FD3, 0x71A1,
+	0x9FD4, 0x71A2, 0x9FD5, 0x71A3, 0x9FD6, 0x71A4, 0x9FD7, 0x71A5,	0x9FD8, 0x71A6, 0x9FD9, 0x71A7, 0x9FDA, 0x71A9, 0x9FDB, 0x71AA,
+	0x9FDC, 0x71AB, 0x9FDD, 0x71AD, 0x9FDE, 0x71AE, 0x9FDF, 0x71AF,	0x9FE0, 0x71B0, 0x9FE1, 0x71B1, 0x9FE2, 0x71B2, 0x9FE3, 0x71B4,
+	0x9FE4, 0x71B6, 0x9FE5, 0x71B7, 0x9FE6, 0x71B8, 0x9FE7, 0x71BA,	0x9FE8, 0x71BB, 0x9FE9, 0x71BC, 0x9FEA, 0x71BD, 0x9FEB, 0x71BE,
+	0x9FEC, 0x71BF, 0x9FED, 0x71C0, 0x9FEE, 0x71C1, 0x9FEF, 0x71C2,	0x9FF0, 0x71C4, 0x9FF1, 0x71C5, 0x9FF2, 0x71C6, 0x9FF3, 0x71C7,
+	0x9FF4, 0x71C8, 0x9FF5, 0x71C9, 0x9FF6, 0x71CA, 0x9FF7, 0x71CB,	0x9FF8, 0x71CC, 0x9FF9, 0x71CD, 0x9FFA, 0x71CF, 0x9FFB, 0x71D0,
+	0x9FFC, 0x71D1, 0x9FFD, 0x71D2, 0x9FFE, 0x71D3, 0xA040, 0x71D6,	0xA041, 0x71D7, 0xA042, 0x71D8, 0xA043, 0x71D9, 0xA044, 0x71DA,
+	0xA045, 0x71DB, 0xA046, 0x71DC, 0xA047, 0x71DD, 0xA048, 0x71DE,	0xA049, 0x71DF, 0xA04A, 0x71E1, 0xA04B, 0x71E2, 0xA04C, 0x71E3,
+	0xA04D, 0x71E4, 0xA04E, 0x71E6, 0xA04F, 0x71E8, 0xA050, 0x71E9,	0xA051, 0x71EA, 0xA052, 0x71EB, 0xA053, 0x71EC, 0xA054, 0x71ED,
+	0xA055, 0x71EF, 0xA056, 0x71F0, 0xA057, 0x71F1, 0xA058, 0x71F2,	0xA059, 0x71F3, 0xA05A, 0x71F4, 0xA05B, 0x71F5, 0xA05C, 0x71F6,
+	0xA05D, 0x71F7, 0xA05E, 0x71F8, 0xA05F, 0x71FA, 0xA060, 0x71FB,	0xA061, 0x71FC, 0xA062, 0x71FD, 0xA063, 0x71FE, 0xA064, 0x71FF,
+	0xA065, 0x7200, 0xA066, 0x7201, 0xA067, 0x7202, 0xA068, 0x7203,	0xA069, 0x7204, 0xA06A, 0x7205, 0xA06B, 0x7207, 0xA06C, 0x7208,
+	0xA06D, 0x7209, 0xA06E, 0x720A, 0xA06F, 0x720B, 0xA070, 0x720C,	0xA071, 0x720D, 0xA072, 0x720E, 0xA073, 0x720F, 0xA074, 0x7210,
+	0xA075, 0x7211, 0xA076, 0x7212, 0xA077, 0x7213, 0xA078, 0x7214,	0xA079, 0x7215, 0xA07A, 0x7216, 0xA07B, 0x7217, 0xA07C, 0x7218,
+	0xA07D, 0x7219, 0xA07E, 0x721A, 0xA080, 0x721B, 0xA081, 0x721C,	0xA082, 0x721E, 0xA083, 0x721F, 0xA084, 0x7220, 0xA085, 0x7221,
+	0xA086, 0x7222, 0xA087, 0x7223, 0xA088, 0x7224, 0xA089, 0x7225,	0xA08A, 0x7226, 0xA08B, 0x7227, 0xA08C, 0x7229, 0xA08D, 0x722B,
+	0xA08E, 0x722D, 0xA08F, 0x722E, 0xA090, 0x722F, 0xA091, 0x7232,	0xA092, 0x7233, 0xA093, 0x7234, 0xA094, 0x723A, 0xA095, 0x723C,
+	0xA096, 0x723E, 0xA097, 0x7240, 0xA098, 0x7241, 0xA099, 0x7242,	0xA09A, 0x7243, 0xA09B, 0x7244, 0xA09C, 0x7245, 0xA09D, 0x7246,
+	0xA09E, 0x7249, 0xA09F, 0x724A, 0xA0A0, 0x724B, 0xA0A1, 0x724E,	0xA0A2, 0x724F, 0xA0A3, 0x7250, 0xA0A4, 0x7251, 0xA0A5, 0x7253,
+	0xA0A6, 0x7254, 0xA0A7, 0x7255, 0xA0A8, 0x7257, 0xA0A9, 0x7258,	0xA0AA, 0x725A, 0xA0AB, 0x725C, 0xA0AC, 0x725E, 0xA0AD, 0x7260,
+	0xA0AE, 0x7263, 0xA0AF, 0x7264, 0xA0B0, 0x7265, 0xA0B1, 0x7268,	0xA0B2, 0x726A, 0xA0B3, 0x726B, 0xA0B4, 0x726C, 0xA0B5, 0x726D,
+	0xA0B6, 0x7270, 0xA0B7, 0x7271, 0xA0B8, 0x7273, 0xA0B9, 0x7274,	0xA0BA, 0x7276, 0xA0BB, 0x7277, 0xA0BC, 0x7278, 0xA0BD, 0x727B,
+	0xA0BE, 0x727C, 0xA0BF, 0x727D, 0xA0C0, 0x7282, 0xA0C1, 0x7283,	0xA0C2, 0x7285, 0xA0C3, 0x7286, 0xA0C4, 0x7287, 0xA0C5, 0x7288,
+	0xA0C6, 0x7289, 0xA0C7, 0x728C, 0xA0C8, 0x728E, 0xA0C9, 0x7290,	0xA0CA, 0x7291, 0xA0CB, 0x7293, 0xA0CC, 0x7294, 0xA0CD, 0x7295,
+	0xA0CE, 0x7296, 0xA0CF, 0x7297, 0xA0D0, 0x7298, 0xA0D1, 0x7299,	0xA0D2, 0x729A, 0xA0D3, 0x729B, 0xA0D4, 0x729C, 0xA0D5, 0x729D,
+	0xA0D6, 0x729E, 0xA0D7, 0x72A0, 0xA0D8, 0x72A1, 0xA0D9, 0x72A2,	0xA0DA, 0x72A3, 0xA0DB, 0x72A4, 0xA0DC, 0x72A5, 0xA0DD, 0x72A6,
+	0xA0DE, 0x72A7, 0xA0DF, 0x72A8, 0xA0E0, 0x72A9, 0xA0E1, 0x72AA,	0xA0E2, 0x72AB, 0xA0E3, 0x72AE, 0xA0E4, 0x72B1, 0xA0E5, 0x72B2,
+	0xA0E6, 0x72B3, 0xA0E7, 0x72B5, 0xA0E8, 0x72BA, 0xA0E9, 0x72BB,	0xA0EA, 0x72BC, 0xA0EB, 0x72BD, 0xA0EC, 0x72BE, 0xA0ED, 0x72BF,
+	0xA0EE, 0x72C0, 0xA0EF, 0x72C5, 0xA0F0, 0x72C6, 0xA0F1, 0x72C7,	0xA0F2, 0x72C9, 0xA0F3, 0x72CA, 0xA0F4, 0x72CB, 0xA0F5, 0x72CC,
+	0xA0F6, 0x72CF, 0xA0F7, 0x72D1, 0xA0F8, 0x72D3, 0xA0F9, 0x72D4,	0xA0FA, 0x72D5, 0xA0FB, 0x72D6, 0xA0FC, 0x72D8, 0xA0FD, 0x72DA,
+	0xA0FE, 0x72DB, 0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002,	0xA1A4, 0x00B7, 0xA1A5, 0x02C9, 0xA1A6, 0x02C7, 0xA1A7, 0x00A8,
+	0xA1A8, 0x3003, 0xA1A9, 0x3005, 0xA1AA, 0x2014, 0xA1AB, 0xFF5E,	0xA1AC, 0x2016, 0xA1AD, 0x2026, 0xA1AE, 0x2018, 0xA1AF, 0x2019,
+	0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015,	0xA1B4, 0x3008, 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B,
+	0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F,	0xA1BC, 0x3016, 0xA1BD, 0x3017, 0xA1BE, 0x3010, 0xA1BF, 0x3011,
+	0xA1C0, 0x00B1, 0xA1C1, 0x00D7, 0xA1C2, 0x00F7, 0xA1C3, 0x2236,	0xA1C4, 0x2227, 0xA1C5, 0x2228, 0xA1C6, 0x2211, 0xA1C7, 0x220F,
+	0xA1C8, 0x222A, 0xA1C9, 0x2229, 0xA1CA, 0x2208, 0xA1CB, 0x2237,	0xA1CC, 0x221A, 0xA1CD, 0x22A5, 0xA1CE, 0x2225, 0xA1CF, 0x2220,
+	0xA1D0, 0x2312, 0xA1D1, 0x2299, 0xA1D2, 0x222B, 0xA1D3, 0x222E,	0xA1D4, 0x2261, 0xA1D5, 0x224C, 0xA1D6, 0x2248, 0xA1D7, 0x223D,
+	0xA1D8, 0x221D, 0xA1D9, 0x2260, 0xA1DA, 0x226E, 0xA1DB, 0x226F,	0xA1DC, 0x2264, 0xA1DD, 0x2265, 0xA1DE, 0x221E, 0xA1DF, 0x2235,
+	0xA1E0, 0x2234, 0xA1E1, 0x2642, 0xA1E2, 0x2640, 0xA1E3, 0x00B0,	0xA1E4, 0x2032, 0xA1E5, 0x2033, 0xA1E6, 0x2103, 0xA1E7, 0xFF04,
+	0xA1E8, 0x00A4, 0xA1E9, 0xFFE0, 0xA1EA, 0xFFE1, 0xA1EB, 0x2030,	0xA1EC, 0x00A7, 0xA1ED, 0x2116, 0xA1EE, 0x2606, 0xA1EF, 0x2605,
+	0xA1F0, 0x25CB, 0xA1F1, 0x25CF, 0xA1F2, 0x25CE, 0xA1F3, 0x25C7,	0xA1F4, 0x25C6, 0xA1F5, 0x25A1, 0xA1F6, 0x25A0, 0xA1F7, 0x25B3,
+	0xA1F8, 0x25B2, 0xA1F9, 0x203B, 0xA1FA, 0x2192, 0xA1FB, 0x2190,	0xA1FC, 0x2191, 0xA1FD, 0x2193, 0xA1FE, 0x3013, 0xA2A1, 0x2170,
+	0xA2A2, 0x2171, 0xA2A3, 0x2172, 0xA2A4, 0x2173, 0xA2A5, 0x2174,	0xA2A6, 0x2175, 0xA2A7, 0x2176, 0xA2A8, 0x2177, 0xA2A9, 0x2178,
+	0xA2AA, 0x2179, 0xA2B1, 0x2488, 0xA2B2, 0x2489, 0xA2B3, 0x248A,	0xA2B4, 0x248B, 0xA2B5, 0x248C, 0xA2B6, 0x248D, 0xA2B7, 0x248E,
+	0xA2B8, 0x248F, 0xA2B9, 0x2490, 0xA2BA, 0x2491, 0xA2BB, 0x2492,	0xA2BC, 0x2493, 0xA2BD, 0x2494, 0xA2BE, 0x2495, 0xA2BF, 0x2496,
+	0xA2C0, 0x2497, 0xA2C1, 0x2498, 0xA2C2, 0x2499, 0xA2C3, 0x249A,	0xA2C4, 0x249B, 0xA2C5, 0x2474, 0xA2C6, 0x2475, 0xA2C7, 0x2476,
+	0xA2C8, 0x2477, 0xA2C9, 0x2478, 0xA2CA, 0x2479, 0xA2CB, 0x247A,	0xA2CC, 0x247B, 0xA2CD, 0x247C, 0xA2CE, 0x247D, 0xA2CF, 0x247E,
+	0xA2D0, 0x247F, 0xA2D1, 0x2480, 0xA2D2, 0x2481, 0xA2D3, 0x2482,	0xA2D4, 0x2483, 0xA2D5, 0x2484, 0xA2D6, 0x2485, 0xA2D7, 0x2486,
+	0xA2D8, 0x2487, 0xA2D9, 0x2460, 0xA2DA, 0x2461, 0xA2DB, 0x2462,	0xA2DC, 0x2463, 0xA2DD, 0x2464, 0xA2DE, 0x2465, 0xA2DF, 0x2466,
+	0xA2E0, 0x2467, 0xA2E1, 0x2468, 0xA2E2, 0x2469, 0xA2E5, 0x3220,	0xA2E6, 0x3221, 0xA2E7, 0x3222, 0xA2E8, 0x3223, 0xA2E9, 0x3224,
+	0xA2EA, 0x3225, 0xA2EB, 0x3226, 0xA2EC, 0x3227, 0xA2ED, 0x3228,	0xA2EE, 0x3229, 0xA2F1, 0x2160, 0xA2F2, 0x2161, 0xA2F3, 0x2162,
+	0xA2F4, 0x2163, 0xA2F5, 0x2164, 0xA2F6, 0x2165, 0xA2F7, 0x2166,	0xA2F8, 0x2167, 0xA2F9, 0x2168, 0xA2FA, 0x2169, 0xA2FB, 0x216A,
+	0xA2FC, 0x216B, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03,	0xA3A4, 0xFFE5, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+	0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B,	0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+	0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13,	0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+	0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B,	0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+	0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23,	0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+	0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B,	0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+	0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33,	0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+	0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B,	0xA3DC, 0xFF3C, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+	0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43,	0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+	0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B,	0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+	0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53,	0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+	0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B,	0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA4A1, 0x3041,
+	0xA4A2, 0x3042, 0xA4A3, 0x3043, 0xA4A4, 0x3044, 0xA4A5, 0x3045,	0xA4A6, 0x3046, 0xA4A7, 0x3047, 0xA4A8, 0x3048, 0xA4A9, 0x3049,
+	0xA4AA, 0x304A, 0xA4AB, 0x304B, 0xA4AC, 0x304C, 0xA4AD, 0x304D,	0xA4AE, 0x304E, 0xA4AF, 0x304F, 0xA4B0, 0x3050, 0xA4B1, 0x3051,
+	0xA4B2, 0x3052, 0xA4B3, 0x3053, 0xA4B4, 0x3054, 0xA4B5, 0x3055,	0xA4B6, 0x3056, 0xA4B7, 0x3057, 0xA4B8, 0x3058, 0xA4B9, 0x3059,
+	0xA4BA, 0x305A, 0xA4BB, 0x305B, 0xA4BC, 0x305C, 0xA4BD, 0x305D,	0xA4BE, 0x305E, 0xA4BF, 0x305F, 0xA4C0, 0x3060, 0xA4C1, 0x3061,
+	0xA4C2, 0x3062, 0xA4C3, 0x3063, 0xA4C4, 0x3064, 0xA4C5, 0x3065,	0xA4C6, 0x3066, 0xA4C7, 0x3067, 0xA4C8, 0x3068, 0xA4C9, 0x3069,
+	0xA4CA, 0x306A, 0xA4CB, 0x306B, 0xA4CC, 0x306C, 0xA4CD, 0x306D,	0xA4CE, 0x306E, 0xA4CF, 0x306F, 0xA4D0, 0x3070, 0xA4D1, 0x3071,
+	0xA4D2, 0x3072, 0xA4D3, 0x3073, 0xA4D4, 0x3074, 0xA4D5, 0x3075,	0xA4D6, 0x3076, 0xA4D7, 0x3077, 0xA4D8, 0x3078, 0xA4D9, 0x3079,
+	0xA4DA, 0x307A, 0xA4DB, 0x307B, 0xA4DC, 0x307C, 0xA4DD, 0x307D,	0xA4DE, 0x307E, 0xA4DF, 0x307F, 0xA4E0, 0x3080, 0xA4E1, 0x3081,
+	0xA4E2, 0x3082, 0xA4E3, 0x3083, 0xA4E4, 0x3084, 0xA4E5, 0x3085,	0xA4E6, 0x3086, 0xA4E7, 0x3087, 0xA4E8, 0x3088, 0xA4E9, 0x3089,
+	0xA4EA, 0x308A, 0xA4EB, 0x308B, 0xA4EC, 0x308C, 0xA4ED, 0x308D,	0xA4EE, 0x308E, 0xA4EF, 0x308F, 0xA4F0, 0x3090, 0xA4F1, 0x3091,
+	0xA4F2, 0x3092, 0xA4F3, 0x3093, 0xA5A1, 0x30A1, 0xA5A2, 0x30A2,	0xA5A3, 0x30A3, 0xA5A4, 0x30A4, 0xA5A5, 0x30A5, 0xA5A6, 0x30A6,
+	0xA5A7, 0x30A7, 0xA5A8, 0x30A8, 0xA5A9, 0x30A9, 0xA5AA, 0x30AA,	0xA5AB, 0x30AB, 0xA5AC, 0x30AC, 0xA5AD, 0x30AD, 0xA5AE, 0x30AE,
+	0xA5AF, 0x30AF, 0xA5B0, 0x30B0, 0xA5B1, 0x30B1, 0xA5B2, 0x30B2,	0xA5B3, 0x30B3, 0xA5B4, 0x30B4, 0xA5B5, 0x30B5, 0xA5B6, 0x30B6,
+	0xA5B7, 0x30B7, 0xA5B8, 0x30B8, 0xA5B9, 0x30B9, 0xA5BA, 0x30BA,	0xA5BB, 0x30BB, 0xA5BC, 0x30BC, 0xA5BD, 0x30BD, 0xA5BE, 0x30BE,
+	0xA5BF, 0x30BF, 0xA5C0, 0x30C0, 0xA5C1, 0x30C1, 0xA5C2, 0x30C2,	0xA5C3, 0x30C3, 0xA5C4, 0x30C4, 0xA5C5, 0x30C5, 0xA5C6, 0x30C6,
+	0xA5C7, 0x30C7, 0xA5C8, 0x30C8, 0xA5C9, 0x30C9, 0xA5CA, 0x30CA,	0xA5CB, 0x30CB, 0xA5CC, 0x30CC, 0xA5CD, 0x30CD, 0xA5CE, 0x30CE,
+	0xA5CF, 0x30CF, 0xA5D0, 0x30D0, 0xA5D1, 0x30D1, 0xA5D2, 0x30D2,	0xA5D3, 0x30D3, 0xA5D4, 0x30D4, 0xA5D5, 0x30D5, 0xA5D6, 0x30D6,
+	0xA5D7, 0x30D7, 0xA5D8, 0x30D8, 0xA5D9, 0x30D9, 0xA5DA, 0x30DA,	0xA5DB, 0x30DB, 0xA5DC, 0x30DC, 0xA5DD, 0x30DD, 0xA5DE, 0x30DE,
+	0xA5DF, 0x30DF, 0xA5E0, 0x30E0, 0xA5E1, 0x30E1, 0xA5E2, 0x30E2,	0xA5E3, 0x30E3, 0xA5E4, 0x30E4, 0xA5E5, 0x30E5, 0xA5E6, 0x30E6,
+	0xA5E7, 0x30E7, 0xA5E8, 0x30E8, 0xA5E9, 0x30E9, 0xA5EA, 0x30EA,	0xA5EB, 0x30EB, 0xA5EC, 0x30EC, 0xA5ED, 0x30ED, 0xA5EE, 0x30EE,
+	0xA5EF, 0x30EF, 0xA5F0, 0x30F0, 0xA5F1, 0x30F1, 0xA5F2, 0x30F2,	0xA5F3, 0x30F3, 0xA5F4, 0x30F4, 0xA5F5, 0x30F5, 0xA5F6, 0x30F6,
+	0xA6A1, 0x0391, 0xA6A2, 0x0392, 0xA6A3, 0x0393, 0xA6A4, 0x0394,	0xA6A5, 0x0395, 0xA6A6, 0x0396, 0xA6A7, 0x0397, 0xA6A8, 0x0398,
+	0xA6A9, 0x0399, 0xA6AA, 0x039A, 0xA6AB, 0x039B, 0xA6AC, 0x039C,	0xA6AD, 0x039D, 0xA6AE, 0x039E, 0xA6AF, 0x039F, 0xA6B0, 0x03A0,
+	0xA6B1, 0x03A1, 0xA6B2, 0x03A3, 0xA6B3, 0x03A4, 0xA6B4, 0x03A5,	0xA6B5, 0x03A6, 0xA6B6, 0x03A7, 0xA6B7, 0x03A8, 0xA6B8, 0x03A9,
+	0xA6C1, 0x03B1, 0xA6C2, 0x03B2, 0xA6C3, 0x03B3, 0xA6C4, 0x03B4,	0xA6C5, 0x03B5, 0xA6C6, 0x03B6, 0xA6C7, 0x03B7, 0xA6C8, 0x03B8,
+	0xA6C9, 0x03B9, 0xA6CA, 0x03BA, 0xA6CB, 0x03BB, 0xA6CC, 0x03BC,	0xA6CD, 0x03BD, 0xA6CE, 0x03BE, 0xA6CF, 0x03BF, 0xA6D0, 0x03C0,
+	0xA6D1, 0x03C1, 0xA6D2, 0x03C3, 0xA6D3, 0x03C4, 0xA6D4, 0x03C5,	0xA6D5, 0x03C6, 0xA6D6, 0x03C7, 0xA6D7, 0x03C8, 0xA6D8, 0x03C9,
+	0xA6E0, 0xFE35, 0xA6E1, 0xFE36, 0xA6E2, 0xFE39, 0xA6E3, 0xFE3A,	0xA6E4, 0xFE3F, 0xA6E5, 0xFE40, 0xA6E6, 0xFE3D, 0xA6E7, 0xFE3E,
+	0xA6E8, 0xFE41, 0xA6E9, 0xFE42, 0xA6EA, 0xFE43, 0xA6EB, 0xFE44,	0xA6EE, 0xFE3B, 0xA6EF, 0xFE3C, 0xA6F0, 0xFE37, 0xA6F1, 0xFE38,
+	0xA6F2, 0xFE31, 0xA6F4, 0xFE33, 0xA6F5, 0xFE34, 0xA7A1, 0x0410,	0xA7A2, 0x0411, 0xA7A3, 0x0412, 0xA7A4, 0x0413, 0xA7A5, 0x0414,
+	0xA7A6, 0x0415, 0xA7A7, 0x0401, 0xA7A8, 0x0416, 0xA7A9, 0x0417,	0xA7AA, 0x0418, 0xA7AB, 0x0419, 0xA7AC, 0x041A, 0xA7AD, 0x041B,
+	0xA7AE, 0x041C, 0xA7AF, 0x041D, 0xA7B0, 0x041E, 0xA7B1, 0x041F,	0xA7B2, 0x0420, 0xA7B3, 0x0421, 0xA7B4, 0x0422, 0xA7B5, 0x0423,
+	0xA7B6, 0x0424, 0xA7B7, 0x0425, 0xA7B8, 0x0426, 0xA7B9, 0x0427,	0xA7BA, 0x0428, 0xA7BB, 0x0429, 0xA7BC, 0x042A, 0xA7BD, 0x042B,
+	0xA7BE, 0x042C, 0xA7BF, 0x042D, 0xA7C0, 0x042E, 0xA7C1, 0x042F,	0xA7D1, 0x0430, 0xA7D2, 0x0431, 0xA7D3, 0x0432, 0xA7D4, 0x0433,
+	0xA7D5, 0x0434, 0xA7D6, 0x0435, 0xA7D7, 0x0451, 0xA7D8, 0x0436,	0xA7D9, 0x0437, 0xA7DA, 0x0438, 0xA7DB, 0x0439, 0xA7DC, 0x043A,
+	0xA7DD, 0x043B, 0xA7DE, 0x043C, 0xA7DF, 0x043D, 0xA7E0, 0x043E,	0xA7E1, 0x043F, 0xA7E2, 0x0440, 0xA7E3, 0x0441, 0xA7E4, 0x0442,
+	0xA7E5, 0x0443, 0xA7E6, 0x0444, 0xA7E7, 0x0445, 0xA7E8, 0x0446,	0xA7E9, 0x0447, 0xA7EA, 0x0448, 0xA7EB, 0x0449, 0xA7EC, 0x044A,
+	0xA7ED, 0x044B, 0xA7EE, 0x044C, 0xA7EF, 0x044D, 0xA7F0, 0x044E,	0xA7F1, 0x044F, 0xA840, 0x02CA, 0xA841, 0x02CB, 0xA842, 0x02D9,
+	0xA843, 0x2013, 0xA844, 0x2015, 0xA845, 0x2025, 0xA846, 0x2035,	0xA847, 0x2105, 0xA848, 0x2109, 0xA849, 0x2196, 0xA84A, 0x2197,
+	0xA84B, 0x2198, 0xA84C, 0x2199, 0xA84D, 0x2215, 0xA84E, 0x221F,	0xA84F, 0x2223, 0xA850, 0x2252, 0xA851, 0x2266, 0xA852, 0x2267,
+	0xA853, 0x22BF, 0xA854, 0x2550, 0xA855, 0x2551, 0xA856, 0x2552,	0xA857, 0x2553, 0xA858, 0x2554, 0xA859, 0x2555, 0xA85A, 0x2556,
+	0xA85B, 0x2557, 0xA85C, 0x2558, 0xA85D, 0x2559, 0xA85E, 0x255A,	0xA85F, 0x255B, 0xA860, 0x255C, 0xA861, 0x255D, 0xA862, 0x255E,
+	0xA863, 0x255F, 0xA864, 0x2560, 0xA865, 0x2561, 0xA866, 0x2562,	0xA867, 0x2563, 0xA868, 0x2564, 0xA869, 0x2565, 0xA86A, 0x2566,
+	0xA86B, 0x2567, 0xA86C, 0x2568, 0xA86D, 0x2569, 0xA86E, 0x256A,	0xA86F, 0x256B, 0xA870, 0x256C, 0xA871, 0x256D, 0xA872, 0x256E,
+	0xA873, 0x256F, 0xA874, 0x2570, 0xA875, 0x2571, 0xA876, 0x2572,	0xA877, 0x2573, 0xA878, 0x2581, 0xA879, 0x2582, 0xA87A, 0x2583,
+	0xA87B, 0x2584, 0xA87C, 0x2585, 0xA87D, 0x2586, 0xA87E, 0x2587,	0xA880, 0x2588, 0xA881, 0x2589, 0xA882, 0x258A, 0xA883, 0x258B,
+	0xA884, 0x258C, 0xA885, 0x258D, 0xA886, 0x258E, 0xA887, 0x258F,	0xA888, 0x2593, 0xA889, 0x2594, 0xA88A, 0x2595, 0xA88B, 0x25BC,
+	0xA88C, 0x25BD, 0xA88D, 0x25E2, 0xA88E, 0x25E3, 0xA88F, 0x25E4,	0xA890, 0x25E5, 0xA891, 0x2609, 0xA892, 0x2295, 0xA893, 0x3012,
+	0xA894, 0x301D, 0xA895, 0x301E, 0xA8A1, 0x0101, 0xA8A2, 0x00E1,	0xA8A3, 0x01CE, 0xA8A4, 0x00E0, 0xA8A5, 0x0113, 0xA8A6, 0x00E9,
+	0xA8A7, 0x011B, 0xA8A8, 0x00E8, 0xA8A9, 0x012B, 0xA8AA, 0x00ED,	0xA8AB, 0x01D0, 0xA8AC, 0x00EC, 0xA8AD, 0x014D, 0xA8AE, 0x00F3,
+	0xA8AF, 0x01D2, 0xA8B0, 0x00F2, 0xA8B1, 0x016B, 0xA8B2, 0x00FA,	0xA8B3, 0x01D4, 0xA8B4, 0x00F9, 0xA8B5, 0x01D6, 0xA8B6, 0x01D8,
+	0xA8B7, 0x01DA, 0xA8B8, 0x01DC, 0xA8B9, 0x00FC, 0xA8BA, 0x00EA,	0xA8BB, 0x0251, 0xA8BD, 0x0144, 0xA8BE, 0x0148, 0xA8C0, 0x0261,
+	0xA8C5, 0x3105, 0xA8C6, 0x3106, 0xA8C7, 0x3107, 0xA8C8, 0x3108,	0xA8C9, 0x3109, 0xA8CA, 0x310A, 0xA8CB, 0x310B, 0xA8CC, 0x310C,
+	0xA8CD, 0x310D, 0xA8CE, 0x310E, 0xA8CF, 0x310F, 0xA8D0, 0x3110,	0xA8D1, 0x3111, 0xA8D2, 0x3112, 0xA8D3, 0x3113, 0xA8D4, 0x3114,
+	0xA8D5, 0x3115, 0xA8D6, 0x3116, 0xA8D7, 0x3117, 0xA8D8, 0x3118,	0xA8D9, 0x3119, 0xA8DA, 0x311A, 0xA8DB, 0x311B, 0xA8DC, 0x311C,
+	0xA8DD, 0x311D, 0xA8DE, 0x311E, 0xA8DF, 0x311F, 0xA8E0, 0x3120,	0xA8E1, 0x3121, 0xA8E2, 0x3122, 0xA8E3, 0x3123, 0xA8E4, 0x3124,
+	0xA8E5, 0x3125, 0xA8E6, 0x3126, 0xA8E7, 0x3127, 0xA8E8, 0x3128,	0xA8E9, 0x3129, 0xA940, 0x3021, 0xA941, 0x3022, 0xA942, 0x3023,
+	0xA943, 0x3024, 0xA944, 0x3025, 0xA945, 0x3026, 0xA946, 0x3027,	0xA947, 0x3028, 0xA948, 0x3029, 0xA949, 0x32A3, 0xA94A, 0x338E,
+	0xA94B, 0x338F, 0xA94C, 0x339C, 0xA94D, 0x339D, 0xA94E, 0x339E,	0xA94F, 0x33A1, 0xA950, 0x33C4, 0xA951, 0x33CE, 0xA952, 0x33D1,
+	0xA953, 0x33D2, 0xA954, 0x33D5, 0xA955, 0xFE30, 0xA956, 0xFFE2,	0xA957, 0xFFE4, 0xA959, 0x2121, 0xA95A, 0x3231, 0xA95C, 0x2010,
+	0xA960, 0x30FC, 0xA961, 0x309B, 0xA962, 0x309C, 0xA963, 0x30FD,	0xA964, 0x30FE, 0xA965, 0x3006, 0xA966, 0x309D, 0xA967, 0x309E,
+	0xA968, 0xFE49, 0xA969, 0xFE4A, 0xA96A, 0xFE4B, 0xA96B, 0xFE4C,	0xA96C, 0xFE4D, 0xA96D, 0xFE4E, 0xA96E, 0xFE4F, 0xA96F, 0xFE50,
+	0xA970, 0xFE51, 0xA971, 0xFE52, 0xA972, 0xFE54, 0xA973, 0xFE55,	0xA974, 0xFE56, 0xA975, 0xFE57, 0xA976, 0xFE59, 0xA977, 0xFE5A,
+	0xA978, 0xFE5B, 0xA979, 0xFE5C, 0xA97A, 0xFE5D, 0xA97B, 0xFE5E,	0xA97C, 0xFE5F, 0xA97D, 0xFE60, 0xA97E, 0xFE61, 0xA980, 0xFE62,
+	0xA981, 0xFE63, 0xA982, 0xFE64, 0xA983, 0xFE65, 0xA984, 0xFE66,	0xA985, 0xFE68, 0xA986, 0xFE69, 0xA987, 0xFE6A, 0xA988, 0xFE6B,
+	0xA996, 0x3007, 0xA9A4, 0x2500, 0xA9A5, 0x2501, 0xA9A6, 0x2502,	0xA9A7, 0x2503, 0xA9A8, 0x2504, 0xA9A9, 0x2505, 0xA9AA, 0x2506,
+	0xA9AB, 0x2507, 0xA9AC, 0x2508, 0xA9AD, 0x2509, 0xA9AE, 0x250A,	0xA9AF, 0x250B, 0xA9B0, 0x250C, 0xA9B1, 0x250D, 0xA9B2, 0x250E,
+	0xA9B3, 0x250F, 0xA9B4, 0x2510, 0xA9B5, 0x2511, 0xA9B6, 0x2512,	0xA9B7, 0x2513, 0xA9B8, 0x2514, 0xA9B9, 0x2515, 0xA9BA, 0x2516,
+	0xA9BB, 0x2517, 0xA9BC, 0x2518, 0xA9BD, 0x2519, 0xA9BE, 0x251A,	0xA9BF, 0x251B, 0xA9C0, 0x251C, 0xA9C1, 0x251D, 0xA9C2, 0x251E,
+	0xA9C3, 0x251F, 0xA9C4, 0x2520, 0xA9C5, 0x2521, 0xA9C6, 0x2522,	0xA9C7, 0x2523, 0xA9C8, 0x2524, 0xA9C9, 0x2525, 0xA9CA, 0x2526,
+	0xA9CB, 0x2527, 0xA9CC, 0x2528, 0xA9CD, 0x2529, 0xA9CE, 0x252A,	0xA9CF, 0x252B, 0xA9D0, 0x252C, 0xA9D1, 0x252D, 0xA9D2, 0x252E,
+	0xA9D3, 0x252F, 0xA9D4, 0x2530, 0xA9D5, 0x2531, 0xA9D6, 0x2532,	0xA9D7, 0x2533, 0xA9D8, 0x2534, 0xA9D9, 0x2535, 0xA9DA, 0x2536,
+	0xA9DB, 0x2537, 0xA9DC, 0x2538, 0xA9DD, 0x2539, 0xA9DE, 0x253A,	0xA9DF, 0x253B, 0xA9E0, 0x253C, 0xA9E1, 0x253D, 0xA9E2, 0x253E,
+	0xA9E3, 0x253F, 0xA9E4, 0x2540, 0xA9E5, 0x2541, 0xA9E6, 0x2542,	0xA9E7, 0x2543, 0xA9E8, 0x2544, 0xA9E9, 0x2545, 0xA9EA, 0x2546,
+	0xA9EB, 0x2547, 0xA9EC, 0x2548, 0xA9ED, 0x2549, 0xA9EE, 0x254A,	0xA9EF, 0x254B, 0xAA40, 0x72DC, 0xAA41, 0x72DD, 0xAA42, 0x72DF,
+	0xAA43, 0x72E2, 0xAA44, 0x72E3, 0xAA45, 0x72E4, 0xAA46, 0x72E5,	0xAA47, 0x72E6, 0xAA48, 0x72E7, 0xAA49, 0x72EA, 0xAA4A, 0x72EB,
+	0xAA4B, 0x72F5, 0xAA4C, 0x72F6, 0xAA4D, 0x72F9, 0xAA4E, 0x72FD,	0xAA4F, 0x72FE, 0xAA50, 0x72FF, 0xAA51, 0x7300, 0xAA52, 0x7302,
+	0xAA53, 0x7304, 0xAA54, 0x7305, 0xAA55, 0x7306, 0xAA56, 0x7307,	0xAA57, 0x7308, 0xAA58, 0x7309, 0xAA59, 0x730B, 0xAA5A, 0x730C,
+	0xAA5B, 0x730D, 0xAA5C, 0x730F, 0xAA5D, 0x7310, 0xAA5E, 0x7311,	0xAA5F, 0x7312, 0xAA60, 0x7314, 0xAA61, 0x7318, 0xAA62, 0x7319,
+	0xAA63, 0x731A, 0xAA64, 0x731F, 0xAA65, 0x7320, 0xAA66, 0x7323,	0xAA67, 0x7324, 0xAA68, 0x7326, 0xAA69, 0x7327, 0xAA6A, 0x7328,
+	0xAA6B, 0x732D, 0xAA6C, 0x732F, 0xAA6D, 0x7330, 0xAA6E, 0x7332,	0xAA6F, 0x7333, 0xAA70, 0x7335, 0xAA71, 0x7336, 0xAA72, 0x733A,
+	0xAA73, 0x733B, 0xAA74, 0x733C, 0xAA75, 0x733D, 0xAA76, 0x7340,	0xAA77, 0x7341, 0xAA78, 0x7342, 0xAA79, 0x7343, 0xAA7A, 0x7344,
+	0xAA7B, 0x7345, 0xAA7C, 0x7346, 0xAA7D, 0x7347, 0xAA7E, 0x7348,	0xAA80, 0x7349, 0xAA81, 0x734A, 0xAA82, 0x734B, 0xAA83, 0x734C,
+	0xAA84, 0x734E, 0xAA85, 0x734F, 0xAA86, 0x7351, 0xAA87, 0x7353,	0xAA88, 0x7354, 0xAA89, 0x7355, 0xAA8A, 0x7356, 0xAA8B, 0x7358,
+	0xAA8C, 0x7359, 0xAA8D, 0x735A, 0xAA8E, 0x735B, 0xAA8F, 0x735C,	0xAA90, 0x735D, 0xAA91, 0x735E, 0xAA92, 0x735F, 0xAA93, 0x7361,
+	0xAA94, 0x7362, 0xAA95, 0x7363, 0xAA96, 0x7364, 0xAA97, 0x7365,	0xAA98, 0x7366, 0xAA99, 0x7367, 0xAA9A, 0x7368, 0xAA9B, 0x7369,
+	0xAA9C, 0x736A, 0xAA9D, 0x736B, 0xAA9E, 0x736E, 0xAA9F, 0x7370,	0xAAA0, 0x7371, 0xAB40, 0x7372, 0xAB41, 0x7373, 0xAB42, 0x7374,
+	0xAB43, 0x7375, 0xAB44, 0x7376, 0xAB45, 0x7377, 0xAB46, 0x7378,	0xAB47, 0x7379, 0xAB48, 0x737A, 0xAB49, 0x737B, 0xAB4A, 0x737C,
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+	0xB17D, 0x772A, 0xB17E, 0x772B, 0xB180, 0x772C, 0xB181, 0x772E,	0xB182, 0x7730, 0xB183, 0x7731, 0xB184, 0x7732, 0xB185, 0x7733,
+	0xB186, 0x7734, 0xB187, 0x7739, 0xB188, 0x773B, 0xB189, 0x773D,	0xB18A, 0x773E, 0xB18B, 0x773F, 0xB18C, 0x7742, 0xB18D, 0x7744,
+	0xB18E, 0x7745, 0xB18F, 0x7746, 0xB190, 0x7748, 0xB191, 0x7749,	0xB192, 0x774A, 0xB193, 0x774B, 0xB194, 0x774C, 0xB195, 0x774D,
+	0xB196, 0x774E, 0xB197, 0x774F, 0xB198, 0x7752, 0xB199, 0x7753,	0xB19A, 0x7754, 0xB19B, 0x7755, 0xB19C, 0x7756, 0xB19D, 0x7757,
+	0xB19E, 0x7758, 0xB19F, 0x7759, 0xB1A0, 0x775C, 0xB1A1, 0x8584,	0xB1A2, 0x96F9, 0xB1A3, 0x4FDD, 0xB1A4, 0x5821, 0xB1A5, 0x9971,
+	0xB1A6, 0x5B9D, 0xB1A7, 0x62B1, 0xB1A8, 0x62A5, 0xB1A9, 0x66B4,	0xB1AA, 0x8C79, 0xB1AB, 0x9C8D, 0xB1AC, 0x7206, 0xB1AD, 0x676F,
+	0xB1AE, 0x7891, 0xB1AF, 0x60B2, 0xB1B0, 0x5351, 0xB1B1, 0x5317,	0xB1B2, 0x8F88, 0xB1B3, 0x80CC, 0xB1B4, 0x8D1D, 0xB1B5, 0x94A1,
+	0xB1B6, 0x500D, 0xB1B7, 0x72C8, 0xB1B8, 0x5907, 0xB1B9, 0x60EB,	0xB1BA, 0x7119, 0xB1BB, 0x88AB, 0xB1BC, 0x5954, 0xB1BD, 0x82EF,
+	0xB1BE, 0x672C, 0xB1BF, 0x7B28, 0xB1C0, 0x5D29, 0xB1C1, 0x7EF7,	0xB1C2, 0x752D, 0xB1C3, 0x6CF5, 0xB1C4, 0x8E66, 0xB1C5, 0x8FF8,
+	0xB1C6, 0x903C, 0xB1C7, 0x9F3B, 0xB1C8, 0x6BD4, 0xB1C9, 0x9119,	0xB1CA, 0x7B14, 0xB1CB, 0x5F7C, 0xB1CC, 0x78A7, 0xB1CD, 0x84D6,
+	0xB1CE, 0x853D, 0xB1CF, 0x6BD5, 0xB1D0, 0x6BD9, 0xB1D1, 0x6BD6,	0xB1D2, 0x5E01, 0xB1D3, 0x5E87, 0xB1D4, 0x75F9, 0xB1D5, 0x95ED,
+	0xB1D6, 0x655D, 0xB1D7, 0x5F0A, 0xB1D8, 0x5FC5, 0xB1D9, 0x8F9F,	0xB1DA, 0x58C1, 0xB1DB, 0x81C2, 0xB1DC, 0x907F, 0xB1DD, 0x965B,
+	0xB1DE, 0x97AD, 0xB1DF, 0x8FB9, 0xB1E0, 0x7F16, 0xB1E1, 0x8D2C,	0xB1E2, 0x6241, 0xB1E3, 0x4FBF, 0xB1E4, 0x53D8, 0xB1E5, 0x535E,
+	0xB1E6, 0x8FA8, 0xB1E7, 0x8FA9, 0xB1E8, 0x8FAB, 0xB1E9, 0x904D,	0xB1EA, 0x6807, 0xB1EB, 0x5F6A, 0xB1EC, 0x8198, 0xB1ED, 0x8868,
+	0xB1EE, 0x9CD6, 0xB1EF, 0x618B, 0xB1F0, 0x522B, 0xB1F1, 0x762A,	0xB1F2, 0x5F6C, 0xB1F3, 0x658C, 0xB1F4, 0x6FD2, 0xB1F5, 0x6EE8,
+	0xB1F6, 0x5BBE, 0xB1F7, 0x6448, 0xB1F8, 0x5175, 0xB1F9, 0x51B0,	0xB1FA, 0x67C4, 0xB1FB, 0x4E19, 0xB1FC, 0x79C9, 0xB1FD, 0x997C,
+	0xB1FE, 0x70B3, 0xB240, 0x775D, 0xB241, 0x775E, 0xB242, 0x775F,	0xB243, 0x7760, 0xB244, 0x7764, 0xB245, 0x7767, 0xB246, 0x7769,
+	0xB247, 0x776A, 0xB248, 0x776D, 0xB249, 0x776E, 0xB24A, 0x776F,	0xB24B, 0x7770, 0xB24C, 0x7771, 0xB24D, 0x7772, 0xB24E, 0x7773,
+	0xB24F, 0x7774, 0xB250, 0x7775, 0xB251, 0x7776, 0xB252, 0x7777,	0xB253, 0x7778, 0xB254, 0x777A, 0xB255, 0x777B, 0xB256, 0x777C,
+	0xB257, 0x7781, 0xB258, 0x7782, 0xB259, 0x7783, 0xB25A, 0x7786,	0xB25B, 0x7787, 0xB25C, 0x7788, 0xB25D, 0x7789, 0xB25E, 0x778A,
+	0xB25F, 0x778B, 0xB260, 0x778F, 0xB261, 0x7790, 0xB262, 0x7793,	0xB263, 0x7794, 0xB264, 0x7795, 0xB265, 0x7796, 0xB266, 0x7797,
+	0xB267, 0x7798, 0xB268, 0x7799, 0xB269, 0x779A, 0xB26A, 0x779B,	0xB26B, 0x779C, 0xB26C, 0x779D, 0xB26D, 0x779E, 0xB26E, 0x77A1,
+	0xB26F, 0x77A3, 0xB270, 0x77A4, 0xB271, 0x77A6, 0xB272, 0x77A8,	0xB273, 0x77AB, 0xB274, 0x77AD, 0xB275, 0x77AE, 0xB276, 0x77AF,
+	0xB277, 0x77B1, 0xB278, 0x77B2, 0xB279, 0x77B4, 0xB27A, 0x77B6,	0xB27B, 0x77B7, 0xB27C, 0x77B8, 0xB27D, 0x77B9, 0xB27E, 0x77BA,
+	0xB280, 0x77BC, 0xB281, 0x77BE, 0xB282, 0x77C0, 0xB283, 0x77C1,	0xB284, 0x77C2, 0xB285, 0x77C3, 0xB286, 0x77C4, 0xB287, 0x77C5,
+	0xB288, 0x77C6, 0xB289, 0x77C7, 0xB28A, 0x77C8, 0xB28B, 0x77C9,	0xB28C, 0x77CA, 0xB28D, 0x77CB, 0xB28E, 0x77CC, 0xB28F, 0x77CE,
+	0xB290, 0x77CF, 0xB291, 0x77D0, 0xB292, 0x77D1, 0xB293, 0x77D2,	0xB294, 0x77D3, 0xB295, 0x77D4, 0xB296, 0x77D5, 0xB297, 0x77D6,
+	0xB298, 0x77D8, 0xB299, 0x77D9, 0xB29A, 0x77DA, 0xB29B, 0x77DD,	0xB29C, 0x77DE, 0xB29D, 0x77DF, 0xB29E, 0x77E0, 0xB29F, 0x77E1,
+	0xB2A0, 0x77E4, 0xB2A1, 0x75C5, 0xB2A2, 0x5E76, 0xB2A3, 0x73BB,	0xB2A4, 0x83E0, 0xB2A5, 0x64AD, 0xB2A6, 0x62E8, 0xB2A7, 0x94B5,
+	0xB2A8, 0x6CE2, 0xB2A9, 0x535A, 0xB2AA, 0x52C3, 0xB2AB, 0x640F,	0xB2AC, 0x94C2, 0xB2AD, 0x7B94, 0xB2AE, 0x4F2F, 0xB2AF, 0x5E1B,
+	0xB2B0, 0x8236, 0xB2B1, 0x8116, 0xB2B2, 0x818A, 0xB2B3, 0x6E24,	0xB2B4, 0x6CCA, 0xB2B5, 0x9A73, 0xB2B6, 0x6355, 0xB2B7, 0x535C,
+	0xB2B8, 0x54FA, 0xB2B9, 0x8865, 0xB2BA, 0x57E0, 0xB2BB, 0x4E0D,	0xB2BC, 0x5E03, 0xB2BD, 0x6B65, 0xB2BE, 0x7C3F, 0xB2BF, 0x90E8,
+	0xB2C0, 0x6016, 0xB2C1, 0x64E6, 0xB2C2, 0x731C, 0xB2C3, 0x88C1,	0xB2C4, 0x6750, 0xB2C5, 0x624D, 0xB2C6, 0x8D22, 0xB2C7, 0x776C,
+	0xB2C8, 0x8E29, 0xB2C9, 0x91C7, 0xB2CA, 0x5F69, 0xB2CB, 0x83DC,	0xB2CC, 0x8521, 0xB2CD, 0x9910, 0xB2CE, 0x53C2, 0xB2CF, 0x8695,
+	0xB2D0, 0x6B8B, 0xB2D1, 0x60ED, 0xB2D2, 0x60E8, 0xB2D3, 0x707F,	0xB2D4, 0x82CD, 0xB2D5, 0x8231, 0xB2D6, 0x4ED3, 0xB2D7, 0x6CA7,
+	0xB2D8, 0x85CF, 0xB2D9, 0x64CD, 0xB2DA, 0x7CD9, 0xB2DB, 0x69FD,	0xB2DC, 0x66F9, 0xB2DD, 0x8349, 0xB2DE, 0x5395, 0xB2DF, 0x7B56,
+	0xB2E0, 0x4FA7, 0xB2E1, 0x518C, 0xB2E2, 0x6D4B, 0xB2E3, 0x5C42,	0xB2E4, 0x8E6D, 0xB2E5, 0x63D2, 0xB2E6, 0x53C9, 0xB2E7, 0x832C,
+	0xB2E8, 0x8336, 0xB2E9, 0x67E5, 0xB2EA, 0x78B4, 0xB2EB, 0x643D,	0xB2EC, 0x5BDF, 0xB2ED, 0x5C94, 0xB2EE, 0x5DEE, 0xB2EF, 0x8BE7,
+	0xB2F0, 0x62C6, 0xB2F1, 0x67F4, 0xB2F2, 0x8C7A, 0xB2F3, 0x6400,	0xB2F4, 0x63BA, 0xB2F5, 0x8749, 0xB2F6, 0x998B, 0xB2F7, 0x8C17,
+	0xB2F8, 0x7F20, 0xB2F9, 0x94F2, 0xB2FA, 0x4EA7, 0xB2FB, 0x9610,	0xB2FC, 0x98A4, 0xB2FD, 0x660C, 0xB2FE, 0x7316, 0xB340, 0x77E6,
+	0xB341, 0x77E8, 0xB342, 0x77EA, 0xB343, 0x77EF, 0xB344, 0x77F0,	0xB345, 0x77F1, 0xB346, 0x77F2, 0xB347, 0x77F4, 0xB348, 0x77F5,
+	0xB349, 0x77F7, 0xB34A, 0x77F9, 0xB34B, 0x77FA, 0xB34C, 0x77FB,	0xB34D, 0x77FC, 0xB34E, 0x7803, 0xB34F, 0x7804, 0xB350, 0x7805,
+	0xB351, 0x7806, 0xB352, 0x7807, 0xB353, 0x7808, 0xB354, 0x780A,	0xB355, 0x780B, 0xB356, 0x780E, 0xB357, 0x780F, 0xB358, 0x7810,
+	0xB359, 0x7813, 0xB35A, 0x7815, 0xB35B, 0x7819, 0xB35C, 0x781B,	0xB35D, 0x781E, 0xB35E, 0x7820, 0xB35F, 0x7821, 0xB360, 0x7822,
+	0xB361, 0x7824, 0xB362, 0x7828, 0xB363, 0x782A, 0xB364, 0x782B,	0xB365, 0x782E, 0xB366, 0x782F, 0xB367, 0x7831, 0xB368, 0x7832,
+	0xB369, 0x7833, 0xB36A, 0x7835, 0xB36B, 0x7836, 0xB36C, 0x783D,	0xB36D, 0x783F, 0xB36E, 0x7841, 0xB36F, 0x7842, 0xB370, 0x7843,
+	0xB371, 0x7844, 0xB372, 0x7846, 0xB373, 0x7848, 0xB374, 0x7849,	0xB375, 0x784A, 0xB376, 0x784B, 0xB377, 0x784D, 0xB378, 0x784F,
+	0xB379, 0x7851, 0xB37A, 0x7853, 0xB37B, 0x7854, 0xB37C, 0x7858,	0xB37D, 0x7859, 0xB37E, 0x785A, 0xB380, 0x785B, 0xB381, 0x785C,
+	0xB382, 0x785E, 0xB383, 0x785F, 0xB384, 0x7860, 0xB385, 0x7861,	0xB386, 0x7862, 0xB387, 0x7863, 0xB388, 0x7864, 0xB389, 0x7865,
+	0xB38A, 0x7866, 0xB38B, 0x7867, 0xB38C, 0x7868, 0xB38D, 0x7869,	0xB38E, 0x786F, 0xB38F, 0x7870, 0xB390, 0x7871, 0xB391, 0x7872,
+	0xB392, 0x7873, 0xB393, 0x7874, 0xB394, 0x7875, 0xB395, 0x7876,	0xB396, 0x7878, 0xB397, 0x7879, 0xB398, 0x787A, 0xB399, 0x787B,
+	0xB39A, 0x787D, 0xB39B, 0x787E, 0xB39C, 0x787F, 0xB39D, 0x7880,	0xB39E, 0x7881, 0xB39F, 0x7882, 0xB3A0, 0x7883, 0xB3A1, 0x573A,
+	0xB3A2, 0x5C1D, 0xB3A3, 0x5E38, 0xB3A4, 0x957F, 0xB3A5, 0x507F,	0xB3A6, 0x80A0, 0xB3A7, 0x5382, 0xB3A8, 0x655E, 0xB3A9, 0x7545,
+	0xB3AA, 0x5531, 0xB3AB, 0x5021, 0xB3AC, 0x8D85, 0xB3AD, 0x6284,	0xB3AE, 0x949E, 0xB3AF, 0x671D, 0xB3B0, 0x5632, 0xB3B1, 0x6F6E,
+	0xB3B2, 0x5DE2, 0xB3B3, 0x5435, 0xB3B4, 0x7092, 0xB3B5, 0x8F66,	0xB3B6, 0x626F, 0xB3B7, 0x64A4, 0xB3B8, 0x63A3, 0xB3B9, 0x5F7B,
+	0xB3BA, 0x6F88, 0xB3BB, 0x90F4, 0xB3BC, 0x81E3, 0xB3BD, 0x8FB0,	0xB3BE, 0x5C18, 0xB3BF, 0x6668, 0xB3C0, 0x5FF1, 0xB3C1, 0x6C89,
+	0xB3C2, 0x9648, 0xB3C3, 0x8D81, 0xB3C4, 0x886C, 0xB3C5, 0x6491,	0xB3C6, 0x79F0, 0xB3C7, 0x57CE, 0xB3C8, 0x6A59, 0xB3C9, 0x6210,
+	0xB3CA, 0x5448, 0xB3CB, 0x4E58, 0xB3CC, 0x7A0B, 0xB3CD, 0x60E9,	0xB3CE, 0x6F84, 0xB3CF, 0x8BDA, 0xB3D0, 0x627F, 0xB3D1, 0x901E,
+	0xB3D2, 0x9A8B, 0xB3D3, 0x79E4, 0xB3D4, 0x5403, 0xB3D5, 0x75F4,	0xB3D6, 0x6301, 0xB3D7, 0x5319, 0xB3D8, 0x6C60, 0xB3D9, 0x8FDF,
+	0xB3DA, 0x5F1B, 0xB3DB, 0x9A70, 0xB3DC, 0x803B, 0xB3DD, 0x9F7F,	0xB3DE, 0x4F88, 0xB3DF, 0x5C3A, 0xB3E0, 0x8D64, 0xB3E1, 0x7FC5,
+	0xB3E2, 0x65A5, 0xB3E3, 0x70BD, 0xB3E4, 0x5145, 0xB3E5, 0x51B2,	0xB3E6, 0x866B, 0xB3E7, 0x5D07, 0xB3E8, 0x5BA0, 0xB3E9, 0x62BD,
+	0xB3EA, 0x916C, 0xB3EB, 0x7574, 0xB3EC, 0x8E0C, 0xB3ED, 0x7A20,	0xB3EE, 0x6101, 0xB3EF, 0x7B79, 0xB3F0, 0x4EC7, 0xB3F1, 0x7EF8,
+	0xB3F2, 0x7785, 0xB3F3, 0x4E11, 0xB3F4, 0x81ED, 0xB3F5, 0x521D,	0xB3F6, 0x51FA, 0xB3F7, 0x6A71, 0xB3F8, 0x53A8, 0xB3F9, 0x8E87,
+	0xB3FA, 0x9504, 0xB3FB, 0x96CF, 0xB3FC, 0x6EC1, 0xB3FD, 0x9664,	0xB3FE, 0x695A, 0xB440, 0x7884, 0xB441, 0x7885, 0xB442, 0x7886,
+	0xB443, 0x7888, 0xB444, 0x788A, 0xB445, 0x788B, 0xB446, 0x788F,	0xB447, 0x7890, 0xB448, 0x7892, 0xB449, 0x7894, 0xB44A, 0x7895,
+	0xB44B, 0x7896, 0xB44C, 0x7899, 0xB44D, 0x789D, 0xB44E, 0x789E,	0xB44F, 0x78A0, 0xB450, 0x78A2, 0xB451, 0x78A4, 0xB452, 0x78A6,
+	0xB453, 0x78A8, 0xB454, 0x78A9, 0xB455, 0x78AA, 0xB456, 0x78AB,	0xB457, 0x78AC, 0xB458, 0x78AD, 0xB459, 0x78AE, 0xB45A, 0x78AF,
+	0xB45B, 0x78B5, 0xB45C, 0x78B6, 0xB45D, 0x78B7, 0xB45E, 0x78B8,	0xB45F, 0x78BA, 0xB460, 0x78BB, 0xB461, 0x78BC, 0xB462, 0x78BD,
+	0xB463, 0x78BF, 0xB464, 0x78C0, 0xB465, 0x78C2, 0xB466, 0x78C3,	0xB467, 0x78C4, 0xB468, 0x78C6, 0xB469, 0x78C7, 0xB46A, 0x78C8,
+	0xB46B, 0x78CC, 0xB46C, 0x78CD, 0xB46D, 0x78CE, 0xB46E, 0x78CF,	0xB46F, 0x78D1, 0xB470, 0x78D2, 0xB471, 0x78D3, 0xB472, 0x78D6,
+	0xB473, 0x78D7, 0xB474, 0x78D8, 0xB475, 0x78DA, 0xB476, 0x78DB,	0xB477, 0x78DC, 0xB478, 0x78DD, 0xB479, 0x78DE, 0xB47A, 0x78DF,
+	0xB47B, 0x78E0, 0xB47C, 0x78E1, 0xB47D, 0x78E2, 0xB47E, 0x78E3,	0xB480, 0x78E4, 0xB481, 0x78E5, 0xB482, 0x78E6, 0xB483, 0x78E7,
+	0xB484, 0x78E9, 0xB485, 0x78EA, 0xB486, 0x78EB, 0xB487, 0x78ED,	0xB488, 0x78EE, 0xB489, 0x78EF, 0xB48A, 0x78F0, 0xB48B, 0x78F1,
+	0xB48C, 0x78F3, 0xB48D, 0x78F5, 0xB48E, 0x78F6, 0xB48F, 0x78F8,	0xB490, 0x78F9, 0xB491, 0x78FB, 0xB492, 0x78FC, 0xB493, 0x78FD,
+	0xB494, 0x78FE, 0xB495, 0x78FF, 0xB496, 0x7900, 0xB497, 0x7902,	0xB498, 0x7903, 0xB499, 0x7904, 0xB49A, 0x7906, 0xB49B, 0x7907,
+	0xB49C, 0x7908, 0xB49D, 0x7909, 0xB49E, 0x790A, 0xB49F, 0x790B,	0xB4A0, 0x790C, 0xB4A1, 0x7840, 0xB4A2, 0x50A8, 0xB4A3, 0x77D7,
+	0xB4A4, 0x6410, 0xB4A5, 0x89E6, 0xB4A6, 0x5904, 0xB4A7, 0x63E3,	0xB4A8, 0x5DDD, 0xB4A9, 0x7A7F, 0xB4AA, 0x693D, 0xB4AB, 0x4F20,
+	0xB4AC, 0x8239, 0xB4AD, 0x5598, 0xB4AE, 0x4E32, 0xB4AF, 0x75AE,	0xB4B0, 0x7A97, 0xB4B1, 0x5E62, 0xB4B2, 0x5E8A, 0xB4B3, 0x95EF,
+	0xB4B4, 0x521B, 0xB4B5, 0x5439, 0xB4B6, 0x708A, 0xB4B7, 0x6376,	0xB4B8, 0x9524, 0xB4B9, 0x5782, 0xB4BA, 0x6625, 0xB4BB, 0x693F,
+	0xB4BC, 0x9187, 0xB4BD, 0x5507, 0xB4BE, 0x6DF3, 0xB4BF, 0x7EAF,	0xB4C0, 0x8822, 0xB4C1, 0x6233, 0xB4C2, 0x7EF0, 0xB4C3, 0x75B5,
+	0xB4C4, 0x8328, 0xB4C5, 0x78C1, 0xB4C6, 0x96CC, 0xB4C7, 0x8F9E,	0xB4C8, 0x6148, 0xB4C9, 0x74F7, 0xB4CA, 0x8BCD, 0xB4CB, 0x6B64,
+	0xB4CC, 0x523A, 0xB4CD, 0x8D50, 0xB4CE, 0x6B21, 0xB4CF, 0x806A,	0xB4D0, 0x8471, 0xB4D1, 0x56F1, 0xB4D2, 0x5306, 0xB4D3, 0x4ECE,
+	0xB4D4, 0x4E1B, 0xB4D5, 0x51D1, 0xB4D6, 0x7C97, 0xB4D7, 0x918B,	0xB4D8, 0x7C07, 0xB4D9, 0x4FC3, 0xB4DA, 0x8E7F, 0xB4DB, 0x7BE1,
+	0xB4DC, 0x7A9C, 0xB4DD, 0x6467, 0xB4DE, 0x5D14, 0xB4DF, 0x50AC,	0xB4E0, 0x8106, 0xB4E1, 0x7601, 0xB4E2, 0x7CB9, 0xB4E3, 0x6DEC,
+	0xB4E4, 0x7FE0, 0xB4E5, 0x6751, 0xB4E6, 0x5B58, 0xB4E7, 0x5BF8,	0xB4E8, 0x78CB, 0xB4E9, 0x64AE, 0xB4EA, 0x6413, 0xB4EB, 0x63AA,
+	0xB4EC, 0x632B, 0xB4ED, 0x9519, 0xB4EE, 0x642D, 0xB4EF, 0x8FBE,	0xB4F0, 0x7B54, 0xB4F1, 0x7629, 0xB4F2, 0x6253, 0xB4F3, 0x5927,
+	0xB4F4, 0x5446, 0xB4F5, 0x6B79, 0xB4F6, 0x50A3, 0xB4F7, 0x6234,	0xB4F8, 0x5E26, 0xB4F9, 0x6B86, 0xB4FA, 0x4EE3, 0xB4FB, 0x8D37,
+	0xB4FC, 0x888B, 0xB4FD, 0x5F85, 0xB4FE, 0x902E, 0xB540, 0x790D,	0xB541, 0x790E, 0xB542, 0x790F, 0xB543, 0x7910, 0xB544, 0x7911,
+	0xB545, 0x7912, 0xB546, 0x7914, 0xB547, 0x7915, 0xB548, 0x7916,	0xB549, 0x7917, 0xB54A, 0x7918, 0xB54B, 0x7919, 0xB54C, 0x791A,
+	0xB54D, 0x791B, 0xB54E, 0x791C, 0xB54F, 0x791D, 0xB550, 0x791F,	0xB551, 0x7920, 0xB552, 0x7921, 0xB553, 0x7922, 0xB554, 0x7923,
+	0xB555, 0x7925, 0xB556, 0x7926, 0xB557, 0x7927, 0xB558, 0x7928,	0xB559, 0x7929, 0xB55A, 0x792A, 0xB55B, 0x792B, 0xB55C, 0x792C,
+	0xB55D, 0x792D, 0xB55E, 0x792E, 0xB55F, 0x792F, 0xB560, 0x7930,	0xB561, 0x7931, 0xB562, 0x7932, 0xB563, 0x7933, 0xB564, 0x7935,
+	0xB565, 0x7936, 0xB566, 0x7937, 0xB567, 0x7938, 0xB568, 0x7939,	0xB569, 0x793D, 0xB56A, 0x793F, 0xB56B, 0x7942, 0xB56C, 0x7943,
+	0xB56D, 0x7944, 0xB56E, 0x7945, 0xB56F, 0x7947, 0xB570, 0x794A,	0xB571, 0x794B, 0xB572, 0x794C, 0xB573, 0x794D, 0xB574, 0x794E,
+	0xB575, 0x794F, 0xB576, 0x7950, 0xB577, 0x7951, 0xB578, 0x7952,	0xB579, 0x7954, 0xB57A, 0x7955, 0xB57B, 0x7958, 0xB57C, 0x7959,
+	0xB57D, 0x7961, 0xB57E, 0x7963, 0xB580, 0x7964, 0xB581, 0x7966,	0xB582, 0x7969, 0xB583, 0x796A, 0xB584, 0x796B, 0xB585, 0x796C,
+	0xB586, 0x796E, 0xB587, 0x7970, 0xB588, 0x7971, 0xB589, 0x7972,	0xB58A, 0x7973, 0xB58B, 0x7974, 0xB58C, 0x7975, 0xB58D, 0x7976,
+	0xB58E, 0x7979, 0xB58F, 0x797B, 0xB590, 0x797C, 0xB591, 0x797D,	0xB592, 0x797E, 0xB593, 0x797F, 0xB594, 0x7982, 0xB595, 0x7983,
+	0xB596, 0x7986, 0xB597, 0x7987, 0xB598, 0x7988, 0xB599, 0x7989,	0xB59A, 0x798B, 0xB59B, 0x798C, 0xB59C, 0x798D, 0xB59D, 0x798E,
+	0xB59E, 0x7990, 0xB59F, 0x7991, 0xB5A0, 0x7992, 0xB5A1, 0x6020,	0xB5A2, 0x803D, 0xB5A3, 0x62C5, 0xB5A4, 0x4E39, 0xB5A5, 0x5355,
+	0xB5A6, 0x90F8, 0xB5A7, 0x63B8, 0xB5A8, 0x80C6, 0xB5A9, 0x65E6,	0xB5AA, 0x6C2E, 0xB5AB, 0x4F46, 0xB5AC, 0x60EE, 0xB5AD, 0x6DE1,
+	0xB5AE, 0x8BDE, 0xB5AF, 0x5F39, 0xB5B0, 0x86CB, 0xB5B1, 0x5F53,	0xB5B2, 0x6321, 0xB5B3, 0x515A, 0xB5B4, 0x8361, 0xB5B5, 0x6863,
+	0xB5B6, 0x5200, 0xB5B7, 0x6363, 0xB5B8, 0x8E48, 0xB5B9, 0x5012,	0xB5BA, 0x5C9B, 0xB5BB, 0x7977, 0xB5BC, 0x5BFC, 0xB5BD, 0x5230,
+	0xB5BE, 0x7A3B, 0xB5BF, 0x60BC, 0xB5C0, 0x9053, 0xB5C1, 0x76D7,	0xB5C2, 0x5FB7, 0xB5C3, 0x5F97, 0xB5C4, 0x7684, 0xB5C5, 0x8E6C,
+	0xB5C6, 0x706F, 0xB5C7, 0x767B, 0xB5C8, 0x7B49, 0xB5C9, 0x77AA,	0xB5CA, 0x51F3, 0xB5CB, 0x9093, 0xB5CC, 0x5824, 0xB5CD, 0x4F4E,
+	0xB5CE, 0x6EF4, 0xB5CF, 0x8FEA, 0xB5D0, 0x654C, 0xB5D1, 0x7B1B,	0xB5D2, 0x72C4, 0xB5D3, 0x6DA4, 0xB5D4, 0x7FDF, 0xB5D5, 0x5AE1,
+	0xB5D6, 0x62B5, 0xB5D7, 0x5E95, 0xB5D8, 0x5730, 0xB5D9, 0x8482,	0xB5DA, 0x7B2C, 0xB5DB, 0x5E1D, 0xB5DC, 0x5F1F, 0xB5DD, 0x9012,
+	0xB5DE, 0x7F14, 0xB5DF, 0x98A0, 0xB5E0, 0x6382, 0xB5E1, 0x6EC7,	0xB5E2, 0x7898, 0xB5E3, 0x70B9, 0xB5E4, 0x5178, 0xB5E5, 0x975B,
+	0xB5E6, 0x57AB, 0xB5E7, 0x7535, 0xB5E8, 0x4F43, 0xB5E9, 0x7538,	0xB5EA, 0x5E97, 0xB5EB, 0x60E6, 0xB5EC, 0x5960, 0xB5ED, 0x6DC0,
+	0xB5EE, 0x6BBF, 0xB5EF, 0x7889, 0xB5F0, 0x53FC, 0xB5F1, 0x96D5,	0xB5F2, 0x51CB, 0xB5F3, 0x5201, 0xB5F4, 0x6389, 0xB5F5, 0x540A,
+	0xB5F6, 0x9493, 0xB5F7, 0x8C03, 0xB5F8, 0x8DCC, 0xB5F9, 0x7239,	0xB5FA, 0x789F, 0xB5FB, 0x8776, 0xB5FC, 0x8FED, 0xB5FD, 0x8C0D,
+	0xB5FE, 0x53E0, 0xB640, 0x7993, 0xB641, 0x7994, 0xB642, 0x7995,	0xB643, 0x7996, 0xB644, 0x7997, 0xB645, 0x7998, 0xB646, 0x7999,
+	0xB647, 0x799B, 0xB648, 0x799C, 0xB649, 0x799D, 0xB64A, 0x799E,	0xB64B, 0x799F, 0xB64C, 0x79A0, 0xB64D, 0x79A1, 0xB64E, 0x79A2,
+	0xB64F, 0x79A3, 0xB650, 0x79A4, 0xB651, 0x79A5, 0xB652, 0x79A6,	0xB653, 0x79A8, 0xB654, 0x79A9, 0xB655, 0x79AA, 0xB656, 0x79AB,
+	0xB657, 0x79AC, 0xB658, 0x79AD, 0xB659, 0x79AE, 0xB65A, 0x79AF,	0xB65B, 0x79B0, 0xB65C, 0x79B1, 0xB65D, 0x79B2, 0xB65E, 0x79B4,
+	0xB65F, 0x79B5, 0xB660, 0x79B6, 0xB661, 0x79B7, 0xB662, 0x79B8,	0xB663, 0x79BC, 0xB664, 0x79BF, 0xB665, 0x79C2, 0xB666, 0x79C4,
+	0xB667, 0x79C5, 0xB668, 0x79C7, 0xB669, 0x79C8, 0xB66A, 0x79CA,	0xB66B, 0x79CC, 0xB66C, 0x79CE, 0xB66D, 0x79CF, 0xB66E, 0x79D0,
+	0xB66F, 0x79D3, 0xB670, 0x79D4, 0xB671, 0x79D6, 0xB672, 0x79D7,	0xB673, 0x79D9, 0xB674, 0x79DA, 0xB675, 0x79DB, 0xB676, 0x79DC,
+	0xB677, 0x79DD, 0xB678, 0x79DE, 0xB679, 0x79E0, 0xB67A, 0x79E1,	0xB67B, 0x79E2, 0xB67C, 0x79E5, 0xB67D, 0x79E8, 0xB67E, 0x79EA,
+	0xB680, 0x79EC, 0xB681, 0x79EE, 0xB682, 0x79F1, 0xB683, 0x79F2,	0xB684, 0x79F3, 0xB685, 0x79F4, 0xB686, 0x79F5, 0xB687, 0x79F6,
+	0xB688, 0x79F7, 0xB689, 0x79F9, 0xB68A, 0x79FA, 0xB68B, 0x79FC,	0xB68C, 0x79FE, 0xB68D, 0x79FF, 0xB68E, 0x7A01, 0xB68F, 0x7A04,
+	0xB690, 0x7A05, 0xB691, 0x7A07, 0xB692, 0x7A08, 0xB693, 0x7A09,	0xB694, 0x7A0A, 0xB695, 0x7A0C, 0xB696, 0x7A0F, 0xB697, 0x7A10,
+	0xB698, 0x7A11, 0xB699, 0x7A12, 0xB69A, 0x7A13, 0xB69B, 0x7A15,	0xB69C, 0x7A16, 0xB69D, 0x7A18, 0xB69E, 0x7A19, 0xB69F, 0x7A1B,
+	0xB6A0, 0x7A1C, 0xB6A1, 0x4E01, 0xB6A2, 0x76EF, 0xB6A3, 0x53EE,	0xB6A4, 0x9489, 0xB6A5, 0x9876, 0xB6A6, 0x9F0E, 0xB6A7, 0x952D,
+	0xB6A8, 0x5B9A, 0xB6A9, 0x8BA2, 0xB6AA, 0x4E22, 0xB6AB, 0x4E1C,	0xB6AC, 0x51AC, 0xB6AD, 0x8463, 0xB6AE, 0x61C2, 0xB6AF, 0x52A8,
+	0xB6B0, 0x680B, 0xB6B1, 0x4F97, 0xB6B2, 0x606B, 0xB6B3, 0x51BB,	0xB6B4, 0x6D1E, 0xB6B5, 0x515C, 0xB6B6, 0x6296, 0xB6B7, 0x6597,
+	0xB6B8, 0x9661, 0xB6B9, 0x8C46, 0xB6BA, 0x9017, 0xB6BB, 0x75D8,	0xB6BC, 0x90FD, 0xB6BD, 0x7763, 0xB6BE, 0x6BD2, 0xB6BF, 0x728A,
+	0xB6C0, 0x72EC, 0xB6C1, 0x8BFB, 0xB6C2, 0x5835, 0xB6C3, 0x7779,	0xB6C4, 0x8D4C, 0xB6C5, 0x675C, 0xB6C6, 0x9540, 0xB6C7, 0x809A,
+	0xB6C8, 0x5EA6, 0xB6C9, 0x6E21, 0xB6CA, 0x5992, 0xB6CB, 0x7AEF,	0xB6CC, 0x77ED, 0xB6CD, 0x953B, 0xB6CE, 0x6BB5, 0xB6CF, 0x65AD,
+	0xB6D0, 0x7F0E, 0xB6D1, 0x5806, 0xB6D2, 0x5151, 0xB6D3, 0x961F,	0xB6D4, 0x5BF9, 0xB6D5, 0x58A9, 0xB6D6, 0x5428, 0xB6D7, 0x8E72,
+	0xB6D8, 0x6566, 0xB6D9, 0x987F, 0xB6DA, 0x56E4, 0xB6DB, 0x949D,	0xB6DC, 0x76FE, 0xB6DD, 0x9041, 0xB6DE, 0x6387, 0xB6DF, 0x54C6,
+	0xB6E0, 0x591A, 0xB6E1, 0x593A, 0xB6E2, 0x579B, 0xB6E3, 0x8EB2,	0xB6E4, 0x6735, 0xB6E5, 0x8DFA, 0xB6E6, 0x8235, 0xB6E7, 0x5241,
+	0xB6E8, 0x60F0, 0xB6E9, 0x5815, 0xB6EA, 0x86FE, 0xB6EB, 0x5CE8,	0xB6EC, 0x9E45, 0xB6ED, 0x4FC4, 0xB6EE, 0x989D, 0xB6EF, 0x8BB9,
+	0xB6F0, 0x5A25, 0xB6F1, 0x6076, 0xB6F2, 0x5384, 0xB6F3, 0x627C,	0xB6F4, 0x904F, 0xB6F5, 0x9102, 0xB6F6, 0x997F, 0xB6F7, 0x6069,
+	0xB6F8, 0x800C, 0xB6F9, 0x513F, 0xB6FA, 0x8033, 0xB6FB, 0x5C14,	0xB6FC, 0x9975, 0xB6FD, 0x6D31, 0xB6FE, 0x4E8C, 0xB740, 0x7A1D,
+	0xB741, 0x7A1F, 0xB742, 0x7A21, 0xB743, 0x7A22, 0xB744, 0x7A24,	0xB745, 0x7A25, 0xB746, 0x7A26, 0xB747, 0x7A27, 0xB748, 0x7A28,
+	0xB749, 0x7A29, 0xB74A, 0x7A2A, 0xB74B, 0x7A2B, 0xB74C, 0x7A2C,	0xB74D, 0x7A2D, 0xB74E, 0x7A2E, 0xB74F, 0x7A2F, 0xB750, 0x7A30,
+	0xB751, 0x7A31, 0xB752, 0x7A32, 0xB753, 0x7A34, 0xB754, 0x7A35,	0xB755, 0x7A36, 0xB756, 0x7A38, 0xB757, 0x7A3A, 0xB758, 0x7A3E,
+	0xB759, 0x7A40, 0xB75A, 0x7A41, 0xB75B, 0x7A42, 0xB75C, 0x7A43,	0xB75D, 0x7A44, 0xB75E, 0x7A45, 0xB75F, 0x7A47, 0xB760, 0x7A48,
+	0xB761, 0x7A49, 0xB762, 0x7A4A, 0xB763, 0x7A4B, 0xB764, 0x7A4C,	0xB765, 0x7A4D, 0xB766, 0x7A4E, 0xB767, 0x7A4F, 0xB768, 0x7A50,
+	0xB769, 0x7A52, 0xB76A, 0x7A53, 0xB76B, 0x7A54, 0xB76C, 0x7A55,	0xB76D, 0x7A56, 0xB76E, 0x7A58, 0xB76F, 0x7A59, 0xB770, 0x7A5A,
+	0xB771, 0x7A5B, 0xB772, 0x7A5C, 0xB773, 0x7A5D, 0xB774, 0x7A5E,	0xB775, 0x7A5F, 0xB776, 0x7A60, 0xB777, 0x7A61, 0xB778, 0x7A62,
+	0xB779, 0x7A63, 0xB77A, 0x7A64, 0xB77B, 0x7A65, 0xB77C, 0x7A66,	0xB77D, 0x7A67, 0xB77E, 0x7A68, 0xB780, 0x7A69, 0xB781, 0x7A6A,
+	0xB782, 0x7A6B, 0xB783, 0x7A6C, 0xB784, 0x7A6D, 0xB785, 0x7A6E,	0xB786, 0x7A6F, 0xB787, 0x7A71, 0xB788, 0x7A72, 0xB789, 0x7A73,
+	0xB78A, 0x7A75, 0xB78B, 0x7A7B, 0xB78C, 0x7A7C, 0xB78D, 0x7A7D,	0xB78E, 0x7A7E, 0xB78F, 0x7A82, 0xB790, 0x7A85, 0xB791, 0x7A87,
+	0xB792, 0x7A89, 0xB793, 0x7A8A, 0xB794, 0x7A8B, 0xB795, 0x7A8C,	0xB796, 0x7A8E, 0xB797, 0x7A8F, 0xB798, 0x7A90, 0xB799, 0x7A93,
+	0xB79A, 0x7A94, 0xB79B, 0x7A99, 0xB79C, 0x7A9A, 0xB79D, 0x7A9B,	0xB79E, 0x7A9E, 0xB79F, 0x7AA1, 0xB7A0, 0x7AA2, 0xB7A1, 0x8D30,
+	0xB7A2, 0x53D1, 0xB7A3, 0x7F5A, 0xB7A4, 0x7B4F, 0xB7A5, 0x4F10,	0xB7A6, 0x4E4F, 0xB7A7, 0x9600, 0xB7A8, 0x6CD5, 0xB7A9, 0x73D0,
+	0xB7AA, 0x85E9, 0xB7AB, 0x5E06, 0xB7AC, 0x756A, 0xB7AD, 0x7FFB,	0xB7AE, 0x6A0A, 0xB7AF, 0x77FE, 0xB7B0, 0x9492, 0xB7B1, 0x7E41,
+	0xB7B2, 0x51E1, 0xB7B3, 0x70E6, 0xB7B4, 0x53CD, 0xB7B5, 0x8FD4,	0xB7B6, 0x8303, 0xB7B7, 0x8D29, 0xB7B8, 0x72AF, 0xB7B9, 0x996D,
+	0xB7BA, 0x6CDB, 0xB7BB, 0x574A, 0xB7BC, 0x82B3, 0xB7BD, 0x65B9,	0xB7BE, 0x80AA, 0xB7BF, 0x623F, 0xB7C0, 0x9632, 0xB7C1, 0x59A8,
+	0xB7C2, 0x4EFF, 0xB7C3, 0x8BBF, 0xB7C4, 0x7EBA, 0xB7C5, 0x653E,	0xB7C6, 0x83F2, 0xB7C7, 0x975E, 0xB7C8, 0x5561, 0xB7C9, 0x98DE,
+	0xB7CA, 0x80A5, 0xB7CB, 0x532A, 0xB7CC, 0x8BFD, 0xB7CD, 0x5420,	0xB7CE, 0x80BA, 0xB7CF, 0x5E9F, 0xB7D0, 0x6CB8, 0xB7D1, 0x8D39,
+	0xB7D2, 0x82AC, 0xB7D3, 0x915A, 0xB7D4, 0x5429, 0xB7D5, 0x6C1B,	0xB7D6, 0x5206, 0xB7D7, 0x7EB7, 0xB7D8, 0x575F, 0xB7D9, 0x711A,
+	0xB7DA, 0x6C7E, 0xB7DB, 0x7C89, 0xB7DC, 0x594B, 0xB7DD, 0x4EFD,	0xB7DE, 0x5FFF, 0xB7DF, 0x6124, 0xB7E0, 0x7CAA, 0xB7E1, 0x4E30,
+	0xB7E2, 0x5C01, 0xB7E3, 0x67AB, 0xB7E4, 0x8702, 0xB7E5, 0x5CF0,	0xB7E6, 0x950B, 0xB7E7, 0x98CE, 0xB7E8, 0x75AF, 0xB7E9, 0x70FD,
+	0xB7EA, 0x9022, 0xB7EB, 0x51AF, 0xB7EC, 0x7F1D, 0xB7ED, 0x8BBD,	0xB7EE, 0x5949, 0xB7EF, 0x51E4, 0xB7F0, 0x4F5B, 0xB7F1, 0x5426,
+	0xB7F2, 0x592B, 0xB7F3, 0x6577, 0xB7F4, 0x80A4, 0xB7F5, 0x5B75,	0xB7F6, 0x6276, 0xB7F7, 0x62C2, 0xB7F8, 0x8F90, 0xB7F9, 0x5E45,
+	0xB7FA, 0x6C1F, 0xB7FB, 0x7B26, 0xB7FC, 0x4F0F, 0xB7FD, 0x4FD8,	0xB7FE, 0x670D, 0xB840, 0x7AA3, 0xB841, 0x7AA4, 0xB842, 0x7AA7,
+	0xB843, 0x7AA9, 0xB844, 0x7AAA, 0xB845, 0x7AAB, 0xB846, 0x7AAE,	0xB847, 0x7AAF, 0xB848, 0x7AB0, 0xB849, 0x7AB1, 0xB84A, 0x7AB2,
+	0xB84B, 0x7AB4, 0xB84C, 0x7AB5, 0xB84D, 0x7AB6, 0xB84E, 0x7AB7,	0xB84F, 0x7AB8, 0xB850, 0x7AB9, 0xB851, 0x7ABA, 0xB852, 0x7ABB,
+	0xB853, 0x7ABC, 0xB854, 0x7ABD, 0xB855, 0x7ABE, 0xB856, 0x7AC0,	0xB857, 0x7AC1, 0xB858, 0x7AC2, 0xB859, 0x7AC3, 0xB85A, 0x7AC4,
+	0xB85B, 0x7AC5, 0xB85C, 0x7AC6, 0xB85D, 0x7AC7, 0xB85E, 0x7AC8,	0xB85F, 0x7AC9, 0xB860, 0x7ACA, 0xB861, 0x7ACC, 0xB862, 0x7ACD,
+	0xB863, 0x7ACE, 0xB864, 0x7ACF, 0xB865, 0x7AD0, 0xB866, 0x7AD1,	0xB867, 0x7AD2, 0xB868, 0x7AD3, 0xB869, 0x7AD4, 0xB86A, 0x7AD5,
+	0xB86B, 0x7AD7, 0xB86C, 0x7AD8, 0xB86D, 0x7ADA, 0xB86E, 0x7ADB,	0xB86F, 0x7ADC, 0xB870, 0x7ADD, 0xB871, 0x7AE1, 0xB872, 0x7AE2,
+	0xB873, 0x7AE4, 0xB874, 0x7AE7, 0xB875, 0x7AE8, 0xB876, 0x7AE9,	0xB877, 0x7AEA, 0xB878, 0x7AEB, 0xB879, 0x7AEC, 0xB87A, 0x7AEE,
+	0xB87B, 0x7AF0, 0xB87C, 0x7AF1, 0xB87D, 0x7AF2, 0xB87E, 0x7AF3,	0xB880, 0x7AF4, 0xB881, 0x7AF5, 0xB882, 0x7AF6, 0xB883, 0x7AF7,
+	0xB884, 0x7AF8, 0xB885, 0x7AFB, 0xB886, 0x7AFC, 0xB887, 0x7AFE,	0xB888, 0x7B00, 0xB889, 0x7B01, 0xB88A, 0x7B02, 0xB88B, 0x7B05,
+	0xB88C, 0x7B07, 0xB88D, 0x7B09, 0xB88E, 0x7B0C, 0xB88F, 0x7B0D,	0xB890, 0x7B0E, 0xB891, 0x7B10, 0xB892, 0x7B12, 0xB893, 0x7B13,
+	0xB894, 0x7B16, 0xB895, 0x7B17, 0xB896, 0x7B18, 0xB897, 0x7B1A,	0xB898, 0x7B1C, 0xB899, 0x7B1D, 0xB89A, 0x7B1F, 0xB89B, 0x7B21,
+	0xB89C, 0x7B22, 0xB89D, 0x7B23, 0xB89E, 0x7B27, 0xB89F, 0x7B29,	0xB8A0, 0x7B2D, 0xB8A1, 0x6D6E, 0xB8A2, 0x6DAA, 0xB8A3, 0x798F,
+	0xB8A4, 0x88B1, 0xB8A5, 0x5F17, 0xB8A6, 0x752B, 0xB8A7, 0x629A,	0xB8A8, 0x8F85, 0xB8A9, 0x4FEF, 0xB8AA, 0x91DC, 0xB8AB, 0x65A7,
+	0xB8AC, 0x812F, 0xB8AD, 0x8151, 0xB8AE, 0x5E9C, 0xB8AF, 0x8150,	0xB8B0, 0x8D74, 0xB8B1, 0x526F, 0xB8B2, 0x8986, 0xB8B3, 0x8D4B,
+	0xB8B4, 0x590D, 0xB8B5, 0x5085, 0xB8B6, 0x4ED8, 0xB8B7, 0x961C,	0xB8B8, 0x7236, 0xB8B9, 0x8179, 0xB8BA, 0x8D1F, 0xB8BB, 0x5BCC,
+	0xB8BC, 0x8BA3, 0xB8BD, 0x9644, 0xB8BE, 0x5987, 0xB8BF, 0x7F1A,	0xB8C0, 0x5490, 0xB8C1, 0x5676, 0xB8C2, 0x560E, 0xB8C3, 0x8BE5,
+	0xB8C4, 0x6539, 0xB8C5, 0x6982, 0xB8C6, 0x9499, 0xB8C7, 0x76D6,	0xB8C8, 0x6E89, 0xB8C9, 0x5E72, 0xB8CA, 0x7518, 0xB8CB, 0x6746,
+	0xB8CC, 0x67D1, 0xB8CD, 0x7AFF, 0xB8CE, 0x809D, 0xB8CF, 0x8D76,	0xB8D0, 0x611F, 0xB8D1, 0x79C6, 0xB8D2, 0x6562, 0xB8D3, 0x8D63,
+	0xB8D4, 0x5188, 0xB8D5, 0x521A, 0xB8D6, 0x94A2, 0xB8D7, 0x7F38,	0xB8D8, 0x809B, 0xB8D9, 0x7EB2, 0xB8DA, 0x5C97, 0xB8DB, 0x6E2F,
+	0xB8DC, 0x6760, 0xB8DD, 0x7BD9, 0xB8DE, 0x768B, 0xB8DF, 0x9AD8,	0xB8E0, 0x818F, 0xB8E1, 0x7F94, 0xB8E2, 0x7CD5, 0xB8E3, 0x641E,
+	0xB8E4, 0x9550, 0xB8E5, 0x7A3F, 0xB8E6, 0x544A, 0xB8E7, 0x54E5,	0xB8E8, 0x6B4C, 0xB8E9, 0x6401, 0xB8EA, 0x6208, 0xB8EB, 0x9E3D,
+	0xB8EC, 0x80F3, 0xB8ED, 0x7599, 0xB8EE, 0x5272, 0xB8EF, 0x9769,	0xB8F0, 0x845B, 0xB8F1, 0x683C, 0xB8F2, 0x86E4, 0xB8F3, 0x9601,
+	0xB8F4, 0x9694, 0xB8F5, 0x94EC, 0xB8F6, 0x4E2A, 0xB8F7, 0x5404,	0xB8F8, 0x7ED9, 0xB8F9, 0x6839, 0xB8FA, 0x8DDF, 0xB8FB, 0x8015,
+	0xB8FC, 0x66F4, 0xB8FD, 0x5E9A, 0xB8FE, 0x7FB9, 0xB940, 0x7B2F,	0xB941, 0x7B30, 0xB942, 0x7B32, 0xB943, 0x7B34, 0xB944, 0x7B35,
+	0xB945, 0x7B36, 0xB946, 0x7B37, 0xB947, 0x7B39, 0xB948, 0x7B3B,	0xB949, 0x7B3D, 0xB94A, 0x7B3F, 0xB94B, 0x7B40, 0xB94C, 0x7B41,
+	0xB94D, 0x7B42, 0xB94E, 0x7B43, 0xB94F, 0x7B44, 0xB950, 0x7B46,	0xB951, 0x7B48, 0xB952, 0x7B4A, 0xB953, 0x7B4D, 0xB954, 0x7B4E,
+	0xB955, 0x7B53, 0xB956, 0x7B55, 0xB957, 0x7B57, 0xB958, 0x7B59,	0xB959, 0x7B5C, 0xB95A, 0x7B5E, 0xB95B, 0x7B5F, 0xB95C, 0x7B61,
+	0xB95D, 0x7B63, 0xB95E, 0x7B64, 0xB95F, 0x7B65, 0xB960, 0x7B66,	0xB961, 0x7B67, 0xB962, 0x7B68, 0xB963, 0x7B69, 0xB964, 0x7B6A,
+	0xB965, 0x7B6B, 0xB966, 0x7B6C, 0xB967, 0x7B6D, 0xB968, 0x7B6F,	0xB969, 0x7B70, 0xB96A, 0x7B73, 0xB96B, 0x7B74, 0xB96C, 0x7B76,
+	0xB96D, 0x7B78, 0xB96E, 0x7B7A, 0xB96F, 0x7B7C, 0xB970, 0x7B7D,	0xB971, 0x7B7F, 0xB972, 0x7B81, 0xB973, 0x7B82, 0xB974, 0x7B83,
+	0xB975, 0x7B84, 0xB976, 0x7B86, 0xB977, 0x7B87, 0xB978, 0x7B88,	0xB979, 0x7B89, 0xB97A, 0x7B8A, 0xB97B, 0x7B8B, 0xB97C, 0x7B8C,
+	0xB97D, 0x7B8E, 0xB97E, 0x7B8F, 0xB980, 0x7B91, 0xB981, 0x7B92,	0xB982, 0x7B93, 0xB983, 0x7B96, 0xB984, 0x7B98, 0xB985, 0x7B99,
+	0xB986, 0x7B9A, 0xB987, 0x7B9B, 0xB988, 0x7B9E, 0xB989, 0x7B9F,	0xB98A, 0x7BA0, 0xB98B, 0x7BA3, 0xB98C, 0x7BA4, 0xB98D, 0x7BA5,
+	0xB98E, 0x7BAE, 0xB98F, 0x7BAF, 0xB990, 0x7BB0, 0xB991, 0x7BB2,	0xB992, 0x7BB3, 0xB993, 0x7BB5, 0xB994, 0x7BB6, 0xB995, 0x7BB7,
+	0xB996, 0x7BB9, 0xB997, 0x7BBA, 0xB998, 0x7BBB, 0xB999, 0x7BBC,	0xB99A, 0x7BBD, 0xB99B, 0x7BBE, 0xB99C, 0x7BBF, 0xB99D, 0x7BC0,
+	0xB99E, 0x7BC2, 0xB99F, 0x7BC3, 0xB9A0, 0x7BC4, 0xB9A1, 0x57C2,	0xB9A2, 0x803F, 0xB9A3, 0x6897, 0xB9A4, 0x5DE5, 0xB9A5, 0x653B,
+	0xB9A6, 0x529F, 0xB9A7, 0x606D, 0xB9A8, 0x9F9A, 0xB9A9, 0x4F9B,	0xB9AA, 0x8EAC, 0xB9AB, 0x516C, 0xB9AC, 0x5BAB, 0xB9AD, 0x5F13,
+	0xB9AE, 0x5DE9, 0xB9AF, 0x6C5E, 0xB9B0, 0x62F1, 0xB9B1, 0x8D21,	0xB9B2, 0x5171, 0xB9B3, 0x94A9, 0xB9B4, 0x52FE, 0xB9B5, 0x6C9F,
+	0xB9B6, 0x82DF, 0xB9B7, 0x72D7, 0xB9B8, 0x57A2, 0xB9B9, 0x6784,	0xB9BA, 0x8D2D, 0xB9BB, 0x591F, 0xB9BC, 0x8F9C, 0xB9BD, 0x83C7,
+	0xB9BE, 0x5495, 0xB9BF, 0x7B8D, 0xB9C0, 0x4F30, 0xB9C1, 0x6CBD,	0xB9C2, 0x5B64, 0xB9C3, 0x59D1, 0xB9C4, 0x9F13, 0xB9C5, 0x53E4,
+	0xB9C6, 0x86CA, 0xB9C7, 0x9AA8, 0xB9C8, 0x8C37, 0xB9C9, 0x80A1,	0xB9CA, 0x6545, 0xB9CB, 0x987E, 0xB9CC, 0x56FA, 0xB9CD, 0x96C7,
+	0xB9CE, 0x522E, 0xB9CF, 0x74DC, 0xB9D0, 0x5250, 0xB9D1, 0x5BE1,	0xB9D2, 0x6302, 0xB9D3, 0x8902, 0xB9D4, 0x4E56, 0xB9D5, 0x62D0,
+	0xB9D6, 0x602A, 0xB9D7, 0x68FA, 0xB9D8, 0x5173, 0xB9D9, 0x5B98,	0xB9DA, 0x51A0, 0xB9DB, 0x89C2, 0xB9DC, 0x7BA1, 0xB9DD, 0x9986,
+	0xB9DE, 0x7F50, 0xB9DF, 0x60EF, 0xB9E0, 0x704C, 0xB9E1, 0x8D2F,	0xB9E2, 0x5149, 0xB9E3, 0x5E7F, 0xB9E4, 0x901B, 0xB9E5, 0x7470,
+	0xB9E6, 0x89C4, 0xB9E7, 0x572D, 0xB9E8, 0x7845, 0xB9E9, 0x5F52,	0xB9EA, 0x9F9F, 0xB9EB, 0x95FA, 0xB9EC, 0x8F68, 0xB9ED, 0x9B3C,
+	0xB9EE, 0x8BE1, 0xB9EF, 0x7678, 0xB9F0, 0x6842, 0xB9F1, 0x67DC,	0xB9F2, 0x8DEA, 0xB9F3, 0x8D35, 0xB9F4, 0x523D, 0xB9F5, 0x8F8A,
+	0xB9F6, 0x6EDA, 0xB9F7, 0x68CD, 0xB9F8, 0x9505, 0xB9F9, 0x90ED,	0xB9FA, 0x56FD, 0xB9FB, 0x679C, 0xB9FC, 0x88F9, 0xB9FD, 0x8FC7,
+	0xB9FE, 0x54C8, 0xBA40, 0x7BC5, 0xBA41, 0x7BC8, 0xBA42, 0x7BC9,	0xBA43, 0x7BCA, 0xBA44, 0x7BCB, 0xBA45, 0x7BCD, 0xBA46, 0x7BCE,
+	0xBA47, 0x7BCF, 0xBA48, 0x7BD0, 0xBA49, 0x7BD2, 0xBA4A, 0x7BD4,	0xBA4B, 0x7BD5, 0xBA4C, 0x7BD6, 0xBA4D, 0x7BD7, 0xBA4E, 0x7BD8,
+	0xBA4F, 0x7BDB, 0xBA50, 0x7BDC, 0xBA51, 0x7BDE, 0xBA52, 0x7BDF,	0xBA53, 0x7BE0, 0xBA54, 0x7BE2, 0xBA55, 0x7BE3, 0xBA56, 0x7BE4,
+	0xBA57, 0x7BE7, 0xBA58, 0x7BE8, 0xBA59, 0x7BE9, 0xBA5A, 0x7BEB,	0xBA5B, 0x7BEC, 0xBA5C, 0x7BED, 0xBA5D, 0x7BEF, 0xBA5E, 0x7BF0,
+	0xBA5F, 0x7BF2, 0xBA60, 0x7BF3, 0xBA61, 0x7BF4, 0xBA62, 0x7BF5,	0xBA63, 0x7BF6, 0xBA64, 0x7BF8, 0xBA65, 0x7BF9, 0xBA66, 0x7BFA,
+	0xBA67, 0x7BFB, 0xBA68, 0x7BFD, 0xBA69, 0x7BFF, 0xBA6A, 0x7C00,	0xBA6B, 0x7C01, 0xBA6C, 0x7C02, 0xBA6D, 0x7C03, 0xBA6E, 0x7C04,
+	0xBA6F, 0x7C05, 0xBA70, 0x7C06, 0xBA71, 0x7C08, 0xBA72, 0x7C09,	0xBA73, 0x7C0A, 0xBA74, 0x7C0D, 0xBA75, 0x7C0E, 0xBA76, 0x7C10,
+	0xBA77, 0x7C11, 0xBA78, 0x7C12, 0xBA79, 0x7C13, 0xBA7A, 0x7C14,	0xBA7B, 0x7C15, 0xBA7C, 0x7C17, 0xBA7D, 0x7C18, 0xBA7E, 0x7C19,
+	0xBA80, 0x7C1A, 0xBA81, 0x7C1B, 0xBA82, 0x7C1C, 0xBA83, 0x7C1D,	0xBA84, 0x7C1E, 0xBA85, 0x7C20, 0xBA86, 0x7C21, 0xBA87, 0x7C22,
+	0xBA88, 0x7C23, 0xBA89, 0x7C24, 0xBA8A, 0x7C25, 0xBA8B, 0x7C28,	0xBA8C, 0x7C29, 0xBA8D, 0x7C2B, 0xBA8E, 0x7C2C, 0xBA8F, 0x7C2D,
+	0xBA90, 0x7C2E, 0xBA91, 0x7C2F, 0xBA92, 0x7C30, 0xBA93, 0x7C31,	0xBA94, 0x7C32, 0xBA95, 0x7C33, 0xBA96, 0x7C34, 0xBA97, 0x7C35,
+	0xBA98, 0x7C36, 0xBA99, 0x7C37, 0xBA9A, 0x7C39, 0xBA9B, 0x7C3A,	0xBA9C, 0x7C3B, 0xBA9D, 0x7C3C, 0xBA9E, 0x7C3D, 0xBA9F, 0x7C3E,
+	0xBAA0, 0x7C42, 0xBAA1, 0x9AB8, 0xBAA2, 0x5B69, 0xBAA3, 0x6D77,	0xBAA4, 0x6C26, 0xBAA5, 0x4EA5, 0xBAA6, 0x5BB3, 0xBAA7, 0x9A87,
+	0xBAA8, 0x9163, 0xBAA9, 0x61A8, 0xBAAA, 0x90AF, 0xBAAB, 0x97E9,	0xBAAC, 0x542B, 0xBAAD, 0x6DB5, 0xBAAE, 0x5BD2, 0xBAAF, 0x51FD,
+	0xBAB0, 0x558A, 0xBAB1, 0x7F55, 0xBAB2, 0x7FF0, 0xBAB3, 0x64BC,	0xBAB4, 0x634D, 0xBAB5, 0x65F1, 0xBAB6, 0x61BE, 0xBAB7, 0x608D,
+	0xBAB8, 0x710A, 0xBAB9, 0x6C57, 0xBABA, 0x6C49, 0xBABB, 0x592F,	0xBABC, 0x676D, 0xBABD, 0x822A, 0xBABE, 0x58D5, 0xBABF, 0x568E,
+	0xBAC0, 0x8C6A, 0xBAC1, 0x6BEB, 0xBAC2, 0x90DD, 0xBAC3, 0x597D,	0xBAC4, 0x8017, 0xBAC5, 0x53F7, 0xBAC6, 0x6D69, 0xBAC7, 0x5475,
+	0xBAC8, 0x559D, 0xBAC9, 0x8377, 0xBACA, 0x83CF, 0xBACB, 0x6838,	0xBACC, 0x79BE, 0xBACD, 0x548C, 0xBACE, 0x4F55, 0xBACF, 0x5408,
+	0xBAD0, 0x76D2, 0xBAD1, 0x8C89, 0xBAD2, 0x9602, 0xBAD3, 0x6CB3,	0xBAD4, 0x6DB8, 0xBAD5, 0x8D6B, 0xBAD6, 0x8910, 0xBAD7, 0x9E64,
+	0xBAD8, 0x8D3A, 0xBAD9, 0x563F, 0xBADA, 0x9ED1, 0xBADB, 0x75D5,	0xBADC, 0x5F88, 0xBADD, 0x72E0, 0xBADE, 0x6068, 0xBADF, 0x54FC,
+	0xBAE0, 0x4EA8, 0xBAE1, 0x6A2A, 0xBAE2, 0x8861, 0xBAE3, 0x6052,	0xBAE4, 0x8F70, 0xBAE5, 0x54C4, 0xBAE6, 0x70D8, 0xBAE7, 0x8679,
+	0xBAE8, 0x9E3F, 0xBAE9, 0x6D2A, 0xBAEA, 0x5B8F, 0xBAEB, 0x5F18,	0xBAEC, 0x7EA2, 0xBAED, 0x5589, 0xBAEE, 0x4FAF, 0xBAEF, 0x7334,
+	0xBAF0, 0x543C, 0xBAF1, 0x539A, 0xBAF2, 0x5019, 0xBAF3, 0x540E,	0xBAF4, 0x547C, 0xBAF5, 0x4E4E, 0xBAF6, 0x5FFD, 0xBAF7, 0x745A,
+	0xBAF8, 0x58F6, 0xBAF9, 0x846B, 0xBAFA, 0x80E1, 0xBAFB, 0x8774,	0xBAFC, 0x72D0, 0xBAFD, 0x7CCA, 0xBAFE, 0x6E56, 0xBB40, 0x7C43,
+	0xBB41, 0x7C44, 0xBB42, 0x7C45, 0xBB43, 0x7C46, 0xBB44, 0x7C47,	0xBB45, 0x7C48, 0xBB46, 0x7C49, 0xBB47, 0x7C4A, 0xBB48, 0x7C4B,
+	0xBB49, 0x7C4C, 0xBB4A, 0x7C4E, 0xBB4B, 0x7C4F, 0xBB4C, 0x7C50,	0xBB4D, 0x7C51, 0xBB4E, 0x7C52, 0xBB4F, 0x7C53, 0xBB50, 0x7C54,
+	0xBB51, 0x7C55, 0xBB52, 0x7C56, 0xBB53, 0x7C57, 0xBB54, 0x7C58,	0xBB55, 0x7C59, 0xBB56, 0x7C5A, 0xBB57, 0x7C5B, 0xBB58, 0x7C5C,
+	0xBB59, 0x7C5D, 0xBB5A, 0x7C5E, 0xBB5B, 0x7C5F, 0xBB5C, 0x7C60,	0xBB5D, 0x7C61, 0xBB5E, 0x7C62, 0xBB5F, 0x7C63, 0xBB60, 0x7C64,
+	0xBB61, 0x7C65, 0xBB62, 0x7C66, 0xBB63, 0x7C67, 0xBB64, 0x7C68,	0xBB65, 0x7C69, 0xBB66, 0x7C6A, 0xBB67, 0x7C6B, 0xBB68, 0x7C6C,
+	0xBB69, 0x7C6D, 0xBB6A, 0x7C6E, 0xBB6B, 0x7C6F, 0xBB6C, 0x7C70,	0xBB6D, 0x7C71, 0xBB6E, 0x7C72, 0xBB6F, 0x7C75, 0xBB70, 0x7C76,
+	0xBB71, 0x7C77, 0xBB72, 0x7C78, 0xBB73, 0x7C79, 0xBB74, 0x7C7A,	0xBB75, 0x7C7E, 0xBB76, 0x7C7F, 0xBB77, 0x7C80, 0xBB78, 0x7C81,
+	0xBB79, 0x7C82, 0xBB7A, 0x7C83, 0xBB7B, 0x7C84, 0xBB7C, 0x7C85,	0xBB7D, 0x7C86, 0xBB7E, 0x7C87, 0xBB80, 0x7C88, 0xBB81, 0x7C8A,
+	0xBB82, 0x7C8B, 0xBB83, 0x7C8C, 0xBB84, 0x7C8D, 0xBB85, 0x7C8E,	0xBB86, 0x7C8F, 0xBB87, 0x7C90, 0xBB88, 0x7C93, 0xBB89, 0x7C94,
+	0xBB8A, 0x7C96, 0xBB8B, 0x7C99, 0xBB8C, 0x7C9A, 0xBB8D, 0x7C9B,	0xBB8E, 0x7CA0, 0xBB8F, 0x7CA1, 0xBB90, 0x7CA3, 0xBB91, 0x7CA6,
+	0xBB92, 0x7CA7, 0xBB93, 0x7CA8, 0xBB94, 0x7CA9, 0xBB95, 0x7CAB,	0xBB96, 0x7CAC, 0xBB97, 0x7CAD, 0xBB98, 0x7CAF, 0xBB99, 0x7CB0,
+	0xBB9A, 0x7CB4, 0xBB9B, 0x7CB5, 0xBB9C, 0x7CB6, 0xBB9D, 0x7CB7,	0xBB9E, 0x7CB8, 0xBB9F, 0x7CBA, 0xBBA0, 0x7CBB, 0xBBA1, 0x5F27,
+	0xBBA2, 0x864E, 0xBBA3, 0x552C, 0xBBA4, 0x62A4, 0xBBA5, 0x4E92,	0xBBA6, 0x6CAA, 0xBBA7, 0x6237, 0xBBA8, 0x82B1, 0xBBA9, 0x54D7,
+	0xBBAA, 0x534E, 0xBBAB, 0x733E, 0xBBAC, 0x6ED1, 0xBBAD, 0x753B,	0xBBAE, 0x5212, 0xBBAF, 0x5316, 0xBBB0, 0x8BDD, 0xBBB1, 0x69D0,
+	0xBBB2, 0x5F8A, 0xBBB3, 0x6000, 0xBBB4, 0x6DEE, 0xBBB5, 0x574F,	0xBBB6, 0x6B22, 0xBBB7, 0x73AF, 0xBBB8, 0x6853, 0xBBB9, 0x8FD8,
+	0xBBBA, 0x7F13, 0xBBBB, 0x6362, 0xBBBC, 0x60A3, 0xBBBD, 0x5524,	0xBBBE, 0x75EA, 0xBBBF, 0x8C62, 0xBBC0, 0x7115, 0xBBC1, 0x6DA3,
+	0xBBC2, 0x5BA6, 0xBBC3, 0x5E7B, 0xBBC4, 0x8352, 0xBBC5, 0x614C,	0xBBC6, 0x9EC4, 0xBBC7, 0x78FA, 0xBBC8, 0x8757, 0xBBC9, 0x7C27,
+	0xBBCA, 0x7687, 0xBBCB, 0x51F0, 0xBBCC, 0x60F6, 0xBBCD, 0x714C,	0xBBCE, 0x6643, 0xBBCF, 0x5E4C, 0xBBD0, 0x604D, 0xBBD1, 0x8C0E,
+	0xBBD2, 0x7070, 0xBBD3, 0x6325, 0xBBD4, 0x8F89, 0xBBD5, 0x5FBD,	0xBBD6, 0x6062, 0xBBD7, 0x86D4, 0xBBD8, 0x56DE, 0xBBD9, 0x6BC1,
+	0xBBDA, 0x6094, 0xBBDB, 0x6167, 0xBBDC, 0x5349, 0xBBDD, 0x60E0,	0xBBDE, 0x6666, 0xBBDF, 0x8D3F, 0xBBE0, 0x79FD, 0xBBE1, 0x4F1A,
+	0xBBE2, 0x70E9, 0xBBE3, 0x6C47, 0xBBE4, 0x8BB3, 0xBBE5, 0x8BF2,	0xBBE6, 0x7ED8, 0xBBE7, 0x8364, 0xBBE8, 0x660F, 0xBBE9, 0x5A5A,
+	0xBBEA, 0x9B42, 0xBBEB, 0x6D51, 0xBBEC, 0x6DF7, 0xBBED, 0x8C41,	0xBBEE, 0x6D3B, 0xBBEF, 0x4F19, 0xBBF0, 0x706B, 0xBBF1, 0x83B7,
+	0xBBF2, 0x6216, 0xBBF3, 0x60D1, 0xBBF4, 0x970D, 0xBBF5, 0x8D27,	0xBBF6, 0x7978, 0xBBF7, 0x51FB, 0xBBF8, 0x573E, 0xBBF9, 0x57FA,
+	0xBBFA, 0x673A, 0xBBFB, 0x7578, 0xBBFC, 0x7A3D, 0xBBFD, 0x79EF,	0xBBFE, 0x7B95, 0xBC40, 0x7CBF, 0xBC41, 0x7CC0, 0xBC42, 0x7CC2,
+	0xBC43, 0x7CC3, 0xBC44, 0x7CC4, 0xBC45, 0x7CC6, 0xBC46, 0x7CC9,	0xBC47, 0x7CCB, 0xBC48, 0x7CCE, 0xBC49, 0x7CCF, 0xBC4A, 0x7CD0,
+	0xBC4B, 0x7CD1, 0xBC4C, 0x7CD2, 0xBC4D, 0x7CD3, 0xBC4E, 0x7CD4,	0xBC4F, 0x7CD8, 0xBC50, 0x7CDA, 0xBC51, 0x7CDB, 0xBC52, 0x7CDD,
+	0xBC53, 0x7CDE, 0xBC54, 0x7CE1, 0xBC55, 0x7CE2, 0xBC56, 0x7CE3,	0xBC57, 0x7CE4, 0xBC58, 0x7CE5, 0xBC59, 0x7CE6, 0xBC5A, 0x7CE7,
+	0xBC5B, 0x7CE9, 0xBC5C, 0x7CEA, 0xBC5D, 0x7CEB, 0xBC5E, 0x7CEC,	0xBC5F, 0x7CED, 0xBC60, 0x7CEE, 0xBC61, 0x7CF0, 0xBC62, 0x7CF1,
+	0xBC63, 0x7CF2, 0xBC64, 0x7CF3, 0xBC65, 0x7CF4, 0xBC66, 0x7CF5,	0xBC67, 0x7CF6, 0xBC68, 0x7CF7, 0xBC69, 0x7CF9, 0xBC6A, 0x7CFA,
+	0xBC6B, 0x7CFC, 0xBC6C, 0x7CFD, 0xBC6D, 0x7CFE, 0xBC6E, 0x7CFF,	0xBC6F, 0x7D00, 0xBC70, 0x7D01, 0xBC71, 0x7D02, 0xBC72, 0x7D03,
+	0xBC73, 0x7D04, 0xBC74, 0x7D05, 0xBC75, 0x7D06, 0xBC76, 0x7D07,	0xBC77, 0x7D08, 0xBC78, 0x7D09, 0xBC79, 0x7D0B, 0xBC7A, 0x7D0C,
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+	0xBC84, 0x7D15, 0xBC85, 0x7D16, 0xBC86, 0x7D17, 0xBC87, 0x7D18,	0xBC88, 0x7D19, 0xBC89, 0x7D1A, 0xBC8A, 0x7D1B, 0xBC8B, 0x7D1C,
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+	0xBFE2, 0x5E93, 0xBFE3, 0x88E4, 0xBFE4, 0x5938, 0xBFE5, 0x57AE,	0xBFE6, 0x630E, 0xBFE7, 0x8DE8, 0xBFE8, 0x80EF, 0xBFE9, 0x5757,
+	0xBFEA, 0x7B77, 0xBFEB, 0x4FA9, 0xBFEC, 0x5FEB, 0xBFED, 0x5BBD,	0xBFEE, 0x6B3E, 0xBFEF, 0x5321, 0xBFF0, 0x7B50, 0xBFF1, 0x72C2,
+	0xBFF2, 0x6846, 0xBFF3, 0x77FF, 0xBFF4, 0x7736, 0xBFF5, 0x65F7,	0xBFF6, 0x51B5, 0xBFF7, 0x4E8F, 0xBFF8, 0x76D4, 0xBFF9, 0x5CBF,
+	0xBFFA, 0x7AA5, 0xBFFB, 0x8475, 0xBFFC, 0x594E, 0xBFFD, 0x9B41,	0xBFFE, 0x5080, 0xC040, 0x7E5E, 0xC041, 0x7E5F, 0xC042, 0x7E60,
+	0xC043, 0x7E61, 0xC044, 0x7E62, 0xC045, 0x7E63, 0xC046, 0x7E64,	0xC047, 0x7E65, 0xC048, 0x7E66, 0xC049, 0x7E67, 0xC04A, 0x7E68,
+	0xC04B, 0x7E69, 0xC04C, 0x7E6A, 0xC04D, 0x7E6B, 0xC04E, 0x7E6C,	0xC04F, 0x7E6D, 0xC050, 0x7E6E, 0xC051, 0x7E6F, 0xC052, 0x7E70,
+	0xC053, 0x7E71, 0xC054, 0x7E72, 0xC055, 0x7E73, 0xC056, 0x7E74,	0xC057, 0x7E75, 0xC058, 0x7E76, 0xC059, 0x7E77, 0xC05A, 0x7E78,
+	0xC05B, 0x7E79, 0xC05C, 0x7E7A, 0xC05D, 0x7E7B, 0xC05E, 0x7E7C,	0xC05F, 0x7E7D, 0xC060, 0x7E7E, 0xC061, 0x7E7F, 0xC062, 0x7E80,
+	0xC063, 0x7E81, 0xC064, 0x7E83, 0xC065, 0x7E84, 0xC066, 0x7E85,	0xC067, 0x7E86, 0xC068, 0x7E87, 0xC069, 0x7E88, 0xC06A, 0x7E89,
+	0xC06B, 0x7E8A, 0xC06C, 0x7E8B, 0xC06D, 0x7E8C, 0xC06E, 0x7E8D,	0xC06F, 0x7E8E, 0xC070, 0x7E8F, 0xC071, 0x7E90, 0xC072, 0x7E91,
+	0xC073, 0x7E92, 0xC074, 0x7E93, 0xC075, 0x7E94, 0xC076, 0x7E95,	0xC077, 0x7E96, 0xC078, 0x7E97, 0xC079, 0x7E98, 0xC07A, 0x7E99,
+	0xC07B, 0x7E9A, 0xC07C, 0x7E9C, 0xC07D, 0x7E9D, 0xC07E, 0x7E9E,	0xC080, 0x7EAE, 0xC081, 0x7EB4, 0xC082, 0x7EBB, 0xC083, 0x7EBC,
+	0xC084, 0x7ED6, 0xC085, 0x7EE4, 0xC086, 0x7EEC, 0xC087, 0x7EF9,	0xC088, 0x7F0A, 0xC089, 0x7F10, 0xC08A, 0x7F1E, 0xC08B, 0x7F37,
+	0xC08C, 0x7F39, 0xC08D, 0x7F3B, 0xC08E, 0x7F3C, 0xC08F, 0x7F3D,	0xC090, 0x7F3E, 0xC091, 0x7F3F, 0xC092, 0x7F40, 0xC093, 0x7F41,
+	0xC094, 0x7F43, 0xC095, 0x7F46, 0xC096, 0x7F47, 0xC097, 0x7F48,	0xC098, 0x7F49, 0xC099, 0x7F4A, 0xC09A, 0x7F4B, 0xC09B, 0x7F4C,
+	0xC09C, 0x7F4D, 0xC09D, 0x7F4E, 0xC09E, 0x7F4F, 0xC09F, 0x7F52,	0xC0A0, 0x7F53, 0xC0A1, 0x9988, 0xC0A2, 0x6127, 0xC0A3, 0x6E83,
+	0xC0A4, 0x5764, 0xC0A5, 0x6606, 0xC0A6, 0x6346, 0xC0A7, 0x56F0,	0xC0A8, 0x62EC, 0xC0A9, 0x6269, 0xC0AA, 0x5ED3, 0xC0AB, 0x9614,
+	0xC0AC, 0x5783, 0xC0AD, 0x62C9, 0xC0AE, 0x5587, 0xC0AF, 0x8721,	0xC0B0, 0x814A, 0xC0B1, 0x8FA3, 0xC0B2, 0x5566, 0xC0B3, 0x83B1,
+	0xC0B4, 0x6765, 0xC0B5, 0x8D56, 0xC0B6, 0x84DD, 0xC0B7, 0x5A6A,	0xC0B8, 0x680F, 0xC0B9, 0x62E6, 0xC0BA, 0x7BEE, 0xC0BB, 0x9611,
+	0xC0BC, 0x5170, 0xC0BD, 0x6F9C, 0xC0BE, 0x8C30, 0xC0BF, 0x63FD,	0xC0C0, 0x89C8, 0xC0C1, 0x61D2, 0xC0C2, 0x7F06, 0xC0C3, 0x70C2,
+	0xC0C4, 0x6EE5, 0xC0C5, 0x7405, 0xC0C6, 0x6994, 0xC0C7, 0x72FC,	0xC0C8, 0x5ECA, 0xC0C9, 0x90CE, 0xC0CA, 0x6717, 0xC0CB, 0x6D6A,
+	0xC0CC, 0x635E, 0xC0CD, 0x52B3, 0xC0CE, 0x7262, 0xC0CF, 0x8001,	0xC0D0, 0x4F6C, 0xC0D1, 0x59E5, 0xC0D2, 0x916A, 0xC0D3, 0x70D9,
+	0xC0D4, 0x6D9D, 0xC0D5, 0x52D2, 0xC0D6, 0x4E50, 0xC0D7, 0x96F7,	0xC0D8, 0x956D, 0xC0D9, 0x857E, 0xC0DA, 0x78CA, 0xC0DB, 0x7D2F,
+	0xC0DC, 0x5121, 0xC0DD, 0x5792, 0xC0DE, 0x64C2, 0xC0DF, 0x808B,	0xC0E0, 0x7C7B, 0xC0E1, 0x6CEA, 0xC0E2, 0x68F1, 0xC0E3, 0x695E,
+	0xC0E4, 0x51B7, 0xC0E5, 0x5398, 0xC0E6, 0x68A8, 0xC0E7, 0x7281,	0xC0E8, 0x9ECE, 0xC0E9, 0x7BF1, 0xC0EA, 0x72F8, 0xC0EB, 0x79BB,
+	0xC0EC, 0x6F13, 0xC0ED, 0x7406, 0xC0EE, 0x674E, 0xC0EF, 0x91CC,	0xC0F0, 0x9CA4, 0xC0F1, 0x793C, 0xC0F2, 0x8389, 0xC0F3, 0x8354,
+	0xC0F4, 0x540F, 0xC0F5, 0x6817, 0xC0F6, 0x4E3D, 0xC0F7, 0x5389,	0xC0F8, 0x52B1, 0xC0F9, 0x783E, 0xC0FA, 0x5386, 0xC0FB, 0x5229,
+	0xC0FC, 0x5088, 0xC0FD, 0x4F8B, 0xC0FE, 0x4FD0, 0xC140, 0x7F56,	0xC141, 0x7F59, 0xC142, 0x7F5B, 0xC143, 0x7F5C, 0xC144, 0x7F5D,
+	0xC145, 0x7F5E, 0xC146, 0x7F60, 0xC147, 0x7F63, 0xC148, 0x7F64,	0xC149, 0x7F65, 0xC14A, 0x7F66, 0xC14B, 0x7F67, 0xC14C, 0x7F6B,
+	0xC14D, 0x7F6C, 0xC14E, 0x7F6D, 0xC14F, 0x7F6F, 0xC150, 0x7F70,	0xC151, 0x7F73, 0xC152, 0x7F75, 0xC153, 0x7F76, 0xC154, 0x7F77,
+	0xC155, 0x7F78, 0xC156, 0x7F7A, 0xC157, 0x7F7B, 0xC158, 0x7F7C,	0xC159, 0x7F7D, 0xC15A, 0x7F7F, 0xC15B, 0x7F80, 0xC15C, 0x7F82,
+	0xC15D, 0x7F83, 0xC15E, 0x7F84, 0xC15F, 0x7F85, 0xC160, 0x7F86,	0xC161, 0x7F87, 0xC162, 0x7F88, 0xC163, 0x7F89, 0xC164, 0x7F8B,
+	0xC165, 0x7F8D, 0xC166, 0x7F8F, 0xC167, 0x7F90, 0xC168, 0x7F91,	0xC169, 0x7F92, 0xC16A, 0x7F93, 0xC16B, 0x7F95, 0xC16C, 0x7F96,
+	0xC16D, 0x7F97, 0xC16E, 0x7F98, 0xC16F, 0x7F99, 0xC170, 0x7F9B,	0xC171, 0x7F9C, 0xC172, 0x7FA0, 0xC173, 0x7FA2, 0xC174, 0x7FA3,
+	0xC175, 0x7FA5, 0xC176, 0x7FA6, 0xC177, 0x7FA8, 0xC178, 0x7FA9,	0xC179, 0x7FAA, 0xC17A, 0x7FAB, 0xC17B, 0x7FAC, 0xC17C, 0x7FAD,
+	0xC17D, 0x7FAE, 0xC17E, 0x7FB1, 0xC180, 0x7FB3, 0xC181, 0x7FB4,	0xC182, 0x7FB5, 0xC183, 0x7FB6, 0xC184, 0x7FB7, 0xC185, 0x7FBA,
+	0xC186, 0x7FBB, 0xC187, 0x7FBE, 0xC188, 0x7FC0, 0xC189, 0x7FC2,	0xC18A, 0x7FC3, 0xC18B, 0x7FC4, 0xC18C, 0x7FC6, 0xC18D, 0x7FC7,
+	0xC18E, 0x7FC8, 0xC18F, 0x7FC9, 0xC190, 0x7FCB, 0xC191, 0x7FCD,	0xC192, 0x7FCF, 0xC193, 0x7FD0, 0xC194, 0x7FD1, 0xC195, 0x7FD2,
+	0xC196, 0x7FD3, 0xC197, 0x7FD6, 0xC198, 0x7FD7, 0xC199, 0x7FD9,	0xC19A, 0x7FDA, 0xC19B, 0x7FDB, 0xC19C, 0x7FDC, 0xC19D, 0x7FDD,
+	0xC19E, 0x7FDE, 0xC19F, 0x7FE2, 0xC1A0, 0x7FE3, 0xC1A1, 0x75E2,	0xC1A2, 0x7ACB, 0xC1A3, 0x7C92, 0xC1A4, 0x6CA5, 0xC1A5, 0x96B6,
+	0xC1A6, 0x529B, 0xC1A7, 0x7483, 0xC1A8, 0x54E9, 0xC1A9, 0x4FE9,	0xC1AA, 0x8054, 0xC1AB, 0x83B2, 0xC1AC, 0x8FDE, 0xC1AD, 0x9570,
+	0xC1AE, 0x5EC9, 0xC1AF, 0x601C, 0xC1B0, 0x6D9F, 0xC1B1, 0x5E18,	0xC1B2, 0x655B, 0xC1B3, 0x8138, 0xC1B4, 0x94FE, 0xC1B5, 0x604B,
+	0xC1B6, 0x70BC, 0xC1B7, 0x7EC3, 0xC1B8, 0x7CAE, 0xC1B9, 0x51C9,	0xC1BA, 0x6881, 0xC1BB, 0x7CB1, 0xC1BC, 0x826F, 0xC1BD, 0x4E24,
+	0xC1BE, 0x8F86, 0xC1BF, 0x91CF, 0xC1C0, 0x667E, 0xC1C1, 0x4EAE,	0xC1C2, 0x8C05, 0xC1C3, 0x64A9, 0xC1C4, 0x804A, 0xC1C5, 0x50DA,
+	0xC1C6, 0x7597, 0xC1C7, 0x71CE, 0xC1C8, 0x5BE5, 0xC1C9, 0x8FBD,	0xC1CA, 0x6F66, 0xC1CB, 0x4E86, 0xC1CC, 0x6482, 0xC1CD, 0x9563,
+	0xC1CE, 0x5ED6, 0xC1CF, 0x6599, 0xC1D0, 0x5217, 0xC1D1, 0x88C2,	0xC1D2, 0x70C8, 0xC1D3, 0x52A3, 0xC1D4, 0x730E, 0xC1D5, 0x7433,
+	0xC1D6, 0x6797, 0xC1D7, 0x78F7, 0xC1D8, 0x9716, 0xC1D9, 0x4E34,	0xC1DA, 0x90BB, 0xC1DB, 0x9CDE, 0xC1DC, 0x6DCB, 0xC1DD, 0x51DB,
+	0xC1DE, 0x8D41, 0xC1DF, 0x541D, 0xC1E0, 0x62CE, 0xC1E1, 0x73B2,	0xC1E2, 0x83F1, 0xC1E3, 0x96F6, 0xC1E4, 0x9F84, 0xC1E5, 0x94C3,
+	0xC1E6, 0x4F36, 0xC1E7, 0x7F9A, 0xC1E8, 0x51CC, 0xC1E9, 0x7075,	0xC1EA, 0x9675, 0xC1EB, 0x5CAD, 0xC1EC, 0x9886, 0xC1ED, 0x53E6,
+	0xC1EE, 0x4EE4, 0xC1EF, 0x6E9C, 0xC1F0, 0x7409, 0xC1F1, 0x69B4,	0xC1F2, 0x786B, 0xC1F3, 0x998F, 0xC1F4, 0x7559, 0xC1F5, 0x5218,
+	0xC1F6, 0x7624, 0xC1F7, 0x6D41, 0xC1F8, 0x67F3, 0xC1F9, 0x516D,	0xC1FA, 0x9F99, 0xC1FB, 0x804B, 0xC1FC, 0x5499, 0xC1FD, 0x7B3C,
+	0xC1FE, 0x7ABF, 0xC240, 0x7FE4, 0xC241, 0x7FE7, 0xC242, 0x7FE8,	0xC243, 0x7FEA, 0xC244, 0x7FEB, 0xC245, 0x7FEC, 0xC246, 0x7FED,
+	0xC247, 0x7FEF, 0xC248, 0x7FF2, 0xC249, 0x7FF4, 0xC24A, 0x7FF5,	0xC24B, 0x7FF6, 0xC24C, 0x7FF7, 0xC24D, 0x7FF8, 0xC24E, 0x7FF9,
+	0xC24F, 0x7FFA, 0xC250, 0x7FFD, 0xC251, 0x7FFE, 0xC252, 0x7FFF,	0xC253, 0x8002, 0xC254, 0x8007, 0xC255, 0x8008, 0xC256, 0x8009,
+	0xC257, 0x800A, 0xC258, 0x800E, 0xC259, 0x800F, 0xC25A, 0x8011,	0xC25B, 0x8013, 0xC25C, 0x801A, 0xC25D, 0x801B, 0xC25E, 0x801D,
+	0xC25F, 0x801E, 0xC260, 0x801F, 0xC261, 0x8021, 0xC262, 0x8023,	0xC263, 0x8024, 0xC264, 0x802B, 0xC265, 0x802C, 0xC266, 0x802D,
+	0xC267, 0x802E, 0xC268, 0x802F, 0xC269, 0x8030, 0xC26A, 0x8032,	0xC26B, 0x8034, 0xC26C, 0x8039, 0xC26D, 0x803A, 0xC26E, 0x803C,
+	0xC26F, 0x803E, 0xC270, 0x8040, 0xC271, 0x8041, 0xC272, 0x8044,	0xC273, 0x8045, 0xC274, 0x8047, 0xC275, 0x8048, 0xC276, 0x8049,
+	0xC277, 0x804E, 0xC278, 0x804F, 0xC279, 0x8050, 0xC27A, 0x8051,	0xC27B, 0x8053, 0xC27C, 0x8055, 0xC27D, 0x8056, 0xC27E, 0x8057,
+	0xC280, 0x8059, 0xC281, 0x805B, 0xC282, 0x805C, 0xC283, 0x805D,	0xC284, 0x805E, 0xC285, 0x805F, 0xC286, 0x8060, 0xC287, 0x8061,
+	0xC288, 0x8062, 0xC289, 0x8063, 0xC28A, 0x8064, 0xC28B, 0x8065,	0xC28C, 0x8066, 0xC28D, 0x8067, 0xC28E, 0x8068, 0xC28F, 0x806B,
+	0xC290, 0x806C, 0xC291, 0x806D, 0xC292, 0x806E, 0xC293, 0x806F,	0xC294, 0x8070, 0xC295, 0x8072, 0xC296, 0x8073, 0xC297, 0x8074,
+	0xC298, 0x8075, 0xC299, 0x8076, 0xC29A, 0x8077, 0xC29B, 0x8078,	0xC29C, 0x8079, 0xC29D, 0x807A, 0xC29E, 0x807B, 0xC29F, 0x807C,
+	0xC2A0, 0x807D, 0xC2A1, 0x9686, 0xC2A2, 0x5784, 0xC2A3, 0x62E2,	0xC2A4, 0x9647, 0xC2A5, 0x697C, 0xC2A6, 0x5A04, 0xC2A7, 0x6402,
+	0xC2A8, 0x7BD3, 0xC2A9, 0x6F0F, 0xC2AA, 0x964B, 0xC2AB, 0x82A6,	0xC2AC, 0x5362, 0xC2AD, 0x9885, 0xC2AE, 0x5E90, 0xC2AF, 0x7089,
+	0xC2B0, 0x63B3, 0xC2B1, 0x5364, 0xC2B2, 0x864F, 0xC2B3, 0x9C81,	0xC2B4, 0x9E93, 0xC2B5, 0x788C, 0xC2B6, 0x9732, 0xC2B7, 0x8DEF,
+	0xC2B8, 0x8D42, 0xC2B9, 0x9E7F, 0xC2BA, 0x6F5E, 0xC2BB, 0x7984,	0xC2BC, 0x5F55, 0xC2BD, 0x9646, 0xC2BE, 0x622E, 0xC2BF, 0x9A74,
+	0xC2C0, 0x5415, 0xC2C1, 0x94DD, 0xC2C2, 0x4FA3, 0xC2C3, 0x65C5,	0xC2C4, 0x5C65, 0xC2C5, 0x5C61, 0xC2C6, 0x7F15, 0xC2C7, 0x8651,
+	0xC2C8, 0x6C2F, 0xC2C9, 0x5F8B, 0xC2CA, 0x7387, 0xC2CB, 0x6EE4,	0xC2CC, 0x7EFF, 0xC2CD, 0x5CE6, 0xC2CE, 0x631B, 0xC2CF, 0x5B6A,
+	0xC2D0, 0x6EE6, 0xC2D1, 0x5375, 0xC2D2, 0x4E71, 0xC2D3, 0x63A0,	0xC2D4, 0x7565, 0xC2D5, 0x62A1, 0xC2D6, 0x8F6E, 0xC2D7, 0x4F26,
+	0xC2D8, 0x4ED1, 0xC2D9, 0x6CA6, 0xC2DA, 0x7EB6, 0xC2DB, 0x8BBA,	0xC2DC, 0x841D, 0xC2DD, 0x87BA, 0xC2DE, 0x7F57, 0xC2DF, 0x903B,
+	0xC2E0, 0x9523, 0xC2E1, 0x7BA9, 0xC2E2, 0x9AA1, 0xC2E3, 0x88F8,	0xC2E4, 0x843D, 0xC2E5, 0x6D1B, 0xC2E6, 0x9A86, 0xC2E7, 0x7EDC,
+	0xC2E8, 0x5988, 0xC2E9, 0x9EBB, 0xC2EA, 0x739B, 0xC2EB, 0x7801,	0xC2EC, 0x8682, 0xC2ED, 0x9A6C, 0xC2EE, 0x9A82, 0xC2EF, 0x561B,
+	0xC2F0, 0x5417, 0xC2F1, 0x57CB, 0xC2F2, 0x4E70, 0xC2F3, 0x9EA6,	0xC2F4, 0x5356, 0xC2F5, 0x8FC8, 0xC2F6, 0x8109, 0xC2F7, 0x7792,
+	0xC2F8, 0x9992, 0xC2F9, 0x86EE, 0xC2FA, 0x6EE1, 0xC2FB, 0x8513,	0xC2FC, 0x66FC, 0xC2FD, 0x6162, 0xC2FE, 0x6F2B, 0xC340, 0x807E,
+	0xC341, 0x8081, 0xC342, 0x8082, 0xC343, 0x8085, 0xC344, 0x8088,	0xC345, 0x808A, 0xC346, 0x808D, 0xC347, 0x808E, 0xC348, 0x808F,
+	0xC349, 0x8090, 0xC34A, 0x8091, 0xC34B, 0x8092, 0xC34C, 0x8094,	0xC34D, 0x8095, 0xC34E, 0x8097, 0xC34F, 0x8099, 0xC350, 0x809E,
+	0xC351, 0x80A3, 0xC352, 0x80A6, 0xC353, 0x80A7, 0xC354, 0x80A8,	0xC355, 0x80AC, 0xC356, 0x80B0, 0xC357, 0x80B3, 0xC358, 0x80B5,
+	0xC359, 0x80B6, 0xC35A, 0x80B8, 0xC35B, 0x80B9, 0xC35C, 0x80BB,	0xC35D, 0x80C5, 0xC35E, 0x80C7, 0xC35F, 0x80C8, 0xC360, 0x80C9,
+	0xC361, 0x80CA, 0xC362, 0x80CB, 0xC363, 0x80CF, 0xC364, 0x80D0,	0xC365, 0x80D1, 0xC366, 0x80D2, 0xC367, 0x80D3, 0xC368, 0x80D4,
+	0xC369, 0x80D5, 0xC36A, 0x80D8, 0xC36B, 0x80DF, 0xC36C, 0x80E0,	0xC36D, 0x80E2, 0xC36E, 0x80E3, 0xC36F, 0x80E6, 0xC370, 0x80EE,
+	0xC371, 0x80F5, 0xC372, 0x80F7, 0xC373, 0x80F9, 0xC374, 0x80FB,	0xC375, 0x80FE, 0xC376, 0x80FF, 0xC377, 0x8100, 0xC378, 0x8101,
+	0xC379, 0x8103, 0xC37A, 0x8104, 0xC37B, 0x8105, 0xC37C, 0x8107,	0xC37D, 0x8108, 0xC37E, 0x810B, 0xC380, 0x810C, 0xC381, 0x8115,
+	0xC382, 0x8117, 0xC383, 0x8119, 0xC384, 0x811B, 0xC385, 0x811C,	0xC386, 0x811D, 0xC387, 0x811F, 0xC388, 0x8120, 0xC389, 0x8121,
+	0xC38A, 0x8122, 0xC38B, 0x8123, 0xC38C, 0x8124, 0xC38D, 0x8125,	0xC38E, 0x8126, 0xC38F, 0x8127, 0xC390, 0x8128, 0xC391, 0x8129,
+	0xC392, 0x812A, 0xC393, 0x812B, 0xC394, 0x812D, 0xC395, 0x812E,	0xC396, 0x8130, 0xC397, 0x8133, 0xC398, 0x8134, 0xC399, 0x8135,
+	0xC39A, 0x8137, 0xC39B, 0x8139, 0xC39C, 0x813A, 0xC39D, 0x813B,	0xC39E, 0x813C, 0xC39F, 0x813D, 0xC3A0, 0x813F, 0xC3A1, 0x8C29,
+	0xC3A2, 0x8292, 0xC3A3, 0x832B, 0xC3A4, 0x76F2, 0xC3A5, 0x6C13,	0xC3A6, 0x5FD9, 0xC3A7, 0x83BD, 0xC3A8, 0x732B, 0xC3A9, 0x8305,
+	0xC3AA, 0x951A, 0xC3AB, 0x6BDB, 0xC3AC, 0x77DB, 0xC3AD, 0x94C6,	0xC3AE, 0x536F, 0xC3AF, 0x8302, 0xC3B0, 0x5192, 0xC3B1, 0x5E3D,
+	0xC3B2, 0x8C8C, 0xC3B3, 0x8D38, 0xC3B4, 0x4E48, 0xC3B5, 0x73AB,	0xC3B6, 0x679A, 0xC3B7, 0x6885, 0xC3B8, 0x9176, 0xC3B9, 0x9709,
+	0xC3BA, 0x7164, 0xC3BB, 0x6CA1, 0xC3BC, 0x7709, 0xC3BD, 0x5A92,	0xC3BE, 0x9541, 0xC3BF, 0x6BCF, 0xC3C0, 0x7F8E, 0xC3C1, 0x6627,
+	0xC3C2, 0x5BD0, 0xC3C3, 0x59B9, 0xC3C4, 0x5A9A, 0xC3C5, 0x95E8,	0xC3C6, 0x95F7, 0xC3C7, 0x4EEC, 0xC3C8, 0x840C, 0xC3C9, 0x8499,
+	0xC3CA, 0x6AAC, 0xC3CB, 0x76DF, 0xC3CC, 0x9530, 0xC3CD, 0x731B,	0xC3CE, 0x68A6, 0xC3CF, 0x5B5F, 0xC3D0, 0x772F, 0xC3D1, 0x919A,
+	0xC3D2, 0x9761, 0xC3D3, 0x7CDC, 0xC3D4, 0x8FF7, 0xC3D5, 0x8C1C,	0xC3D6, 0x5F25, 0xC3D7, 0x7C73, 0xC3D8, 0x79D8, 0xC3D9, 0x89C5,
+	0xC3DA, 0x6CCC, 0xC3DB, 0x871C, 0xC3DC, 0x5BC6, 0xC3DD, 0x5E42,	0xC3DE, 0x68C9, 0xC3DF, 0x7720, 0xC3E0, 0x7EF5, 0xC3E1, 0x5195,
+	0xC3E2, 0x514D, 0xC3E3, 0x52C9, 0xC3E4, 0x5A29, 0xC3E5, 0x7F05,	0xC3E6, 0x9762, 0xC3E7, 0x82D7, 0xC3E8, 0x63CF, 0xC3E9, 0x7784,
+	0xC3EA, 0x85D0, 0xC3EB, 0x79D2, 0xC3EC, 0x6E3A, 0xC3ED, 0x5E99,	0xC3EE, 0x5999, 0xC3EF, 0x8511, 0xC3F0, 0x706D, 0xC3F1, 0x6C11,
+	0xC3F2, 0x62BF, 0xC3F3, 0x76BF, 0xC3F4, 0x654F, 0xC3F5, 0x60AF,	0xC3F6, 0x95FD, 0xC3F7, 0x660E, 0xC3F8, 0x879F, 0xC3F9, 0x9E23,
+	0xC3FA, 0x94ED, 0xC3FB, 0x540D, 0xC3FC, 0x547D, 0xC3FD, 0x8C2C,	0xC3FE, 0x6478, 0xC440, 0x8140, 0xC441, 0x8141, 0xC442, 0x8142,
+	0xC443, 0x8143, 0xC444, 0x8144, 0xC445, 0x8145, 0xC446, 0x8147,	0xC447, 0x8149, 0xC448, 0x814D, 0xC449, 0x814E, 0xC44A, 0x814F,
+	0xC44B, 0x8152, 0xC44C, 0x8156, 0xC44D, 0x8157, 0xC44E, 0x8158,	0xC44F, 0x815B, 0xC450, 0x815C, 0xC451, 0x815D, 0xC452, 0x815E,
+	0xC453, 0x815F, 0xC454, 0x8161, 0xC455, 0x8162, 0xC456, 0x8163,	0xC457, 0x8164, 0xC458, 0x8166, 0xC459, 0x8168, 0xC45A, 0x816A,
+	0xC45B, 0x816B, 0xC45C, 0x816C, 0xC45D, 0x816F, 0xC45E, 0x8172,	0xC45F, 0x8173, 0xC460, 0x8175, 0xC461, 0x8176, 0xC462, 0x8177,
+	0xC463, 0x8178, 0xC464, 0x8181, 0xC465, 0x8183, 0xC466, 0x8184,	0xC467, 0x8185, 0xC468, 0x8186, 0xC469, 0x8187, 0xC46A, 0x8189,
+	0xC46B, 0x818B, 0xC46C, 0x818C, 0xC46D, 0x818D, 0xC46E, 0x818E,	0xC46F, 0x8190, 0xC470, 0x8192, 0xC471, 0x8193, 0xC472, 0x8194,
+	0xC473, 0x8195, 0xC474, 0x8196, 0xC475, 0x8197, 0xC476, 0x8199,	0xC477, 0x819A, 0xC478, 0x819E, 0xC479, 0x819F, 0xC47A, 0x81A0,
+	0xC47B, 0x81A1, 0xC47C, 0x81A2, 0xC47D, 0x81A4, 0xC47E, 0x81A5,	0xC480, 0x81A7, 0xC481, 0x81A9, 0xC482, 0x81AB, 0xC483, 0x81AC,
+	0xC484, 0x81AD, 0xC485, 0x81AE, 0xC486, 0x81AF, 0xC487, 0x81B0,	0xC488, 0x81B1, 0xC489, 0x81B2, 0xC48A, 0x81B4, 0xC48B, 0x81B5,
+	0xC48C, 0x81B6, 0xC48D, 0x81B7, 0xC48E, 0x81B8, 0xC48F, 0x81B9,	0xC490, 0x81BC, 0xC491, 0x81BD, 0xC492, 0x81BE, 0xC493, 0x81BF,
+	0xC494, 0x81C4, 0xC495, 0x81C5, 0xC496, 0x81C7, 0xC497, 0x81C8,	0xC498, 0x81C9, 0xC499, 0x81CB, 0xC49A, 0x81CD, 0xC49B, 0x81CE,
+	0xC49C, 0x81CF, 0xC49D, 0x81D0, 0xC49E, 0x81D1, 0xC49F, 0x81D2,	0xC4A0, 0x81D3, 0xC4A1, 0x6479, 0xC4A2, 0x8611, 0xC4A3, 0x6A21,
+	0xC4A4, 0x819C, 0xC4A5, 0x78E8, 0xC4A6, 0x6469, 0xC4A7, 0x9B54,	0xC4A8, 0x62B9, 0xC4A9, 0x672B, 0xC4AA, 0x83AB, 0xC4AB, 0x58A8,
+	0xC4AC, 0x9ED8, 0xC4AD, 0x6CAB, 0xC4AE, 0x6F20, 0xC4AF, 0x5BDE,	0xC4B0, 0x964C, 0xC4B1, 0x8C0B, 0xC4B2, 0x725F, 0xC4B3, 0x67D0,
+	0xC4B4, 0x62C7, 0xC4B5, 0x7261, 0xC4B6, 0x4EA9, 0xC4B7, 0x59C6,	0xC4B8, 0x6BCD, 0xC4B9, 0x5893, 0xC4BA, 0x66AE, 0xC4BB, 0x5E55,
+	0xC4BC, 0x52DF, 0xC4BD, 0x6155, 0xC4BE, 0x6728, 0xC4BF, 0x76EE,	0xC4C0, 0x7766, 0xC4C1, 0x7267, 0xC4C2, 0x7A46, 0xC4C3, 0x62FF,
+	0xC4C4, 0x54EA, 0xC4C5, 0x5450, 0xC4C6, 0x94A0, 0xC4C7, 0x90A3,	0xC4C8, 0x5A1C, 0xC4C9, 0x7EB3, 0xC4CA, 0x6C16, 0xC4CB, 0x4E43,
+	0xC4CC, 0x5976, 0xC4CD, 0x8010, 0xC4CE, 0x5948, 0xC4CF, 0x5357,	0xC4D0, 0x7537, 0xC4D1, 0x96BE, 0xC4D2, 0x56CA, 0xC4D3, 0x6320,
+	0xC4D4, 0x8111, 0xC4D5, 0x607C, 0xC4D6, 0x95F9, 0xC4D7, 0x6DD6,	0xC4D8, 0x5462, 0xC4D9, 0x9981, 0xC4DA, 0x5185, 0xC4DB, 0x5AE9,
+	0xC4DC, 0x80FD, 0xC4DD, 0x59AE, 0xC4DE, 0x9713, 0xC4DF, 0x502A,	0xC4E0, 0x6CE5, 0xC4E1, 0x5C3C, 0xC4E2, 0x62DF, 0xC4E3, 0x4F60,
+	0xC4E4, 0x533F, 0xC4E5, 0x817B, 0xC4E6, 0x9006, 0xC4E7, 0x6EBA,	0xC4E8, 0x852B, 0xC4E9, 0x62C8, 0xC4EA, 0x5E74, 0xC4EB, 0x78BE,
+	0xC4EC, 0x64B5, 0xC4ED, 0x637B, 0xC4EE, 0x5FF5, 0xC4EF, 0x5A18,	0xC4F0, 0x917F, 0xC4F1, 0x9E1F, 0xC4F2, 0x5C3F, 0xC4F3, 0x634F,
+	0xC4F4, 0x8042, 0xC4F5, 0x5B7D, 0xC4F6, 0x556E, 0xC4F7, 0x954A,	0xC4F8, 0x954D, 0xC4F9, 0x6D85, 0xC4FA, 0x60A8, 0xC4FB, 0x67E0,
+	0xC4FC, 0x72DE, 0xC4FD, 0x51DD, 0xC4FE, 0x5B81, 0xC540, 0x81D4,	0xC541, 0x81D5, 0xC542, 0x81D6, 0xC543, 0x81D7, 0xC544, 0x81D8,
+	0xC545, 0x81D9, 0xC546, 0x81DA, 0xC547, 0x81DB, 0xC548, 0x81DC,	0xC549, 0x81DD, 0xC54A, 0x81DE, 0xC54B, 0x81DF, 0xC54C, 0x81E0,
+	0xC54D, 0x81E1, 0xC54E, 0x81E2, 0xC54F, 0x81E4, 0xC550, 0x81E5,	0xC551, 0x81E6, 0xC552, 0x81E8, 0xC553, 0x81E9, 0xC554, 0x81EB,
+	0xC555, 0x81EE, 0xC556, 0x81EF, 0xC557, 0x81F0, 0xC558, 0x81F1,	0xC559, 0x81F2, 0xC55A, 0x81F5, 0xC55B, 0x81F6, 0xC55C, 0x81F7,
+	0xC55D, 0x81F8, 0xC55E, 0x81F9, 0xC55F, 0x81FA, 0xC560, 0x81FD,	0xC561, 0x81FF, 0xC562, 0x8203, 0xC563, 0x8207, 0xC564, 0x8208,
+	0xC565, 0x8209, 0xC566, 0x820A, 0xC567, 0x820B, 0xC568, 0x820E,	0xC569, 0x820F, 0xC56A, 0x8211, 0xC56B, 0x8213, 0xC56C, 0x8215,
+	0xC56D, 0x8216, 0xC56E, 0x8217, 0xC56F, 0x8218, 0xC570, 0x8219,	0xC571, 0x821A, 0xC572, 0x821D, 0xC573, 0x8220, 0xC574, 0x8224,
+	0xC575, 0x8225, 0xC576, 0x8226, 0xC577, 0x8227, 0xC578, 0x8229,	0xC579, 0x822E, 0xC57A, 0x8232, 0xC57B, 0x823A, 0xC57C, 0x823C,
+	0xC57D, 0x823D, 0xC57E, 0x823F, 0xC580, 0x8240, 0xC581, 0x8241,	0xC582, 0x8242, 0xC583, 0x8243, 0xC584, 0x8245, 0xC585, 0x8246,
+	0xC586, 0x8248, 0xC587, 0x824A, 0xC588, 0x824C, 0xC589, 0x824D,	0xC58A, 0x824E, 0xC58B, 0x8250, 0xC58C, 0x8251, 0xC58D, 0x8252,
+	0xC58E, 0x8253, 0xC58F, 0x8254, 0xC590, 0x8255, 0xC591, 0x8256,	0xC592, 0x8257, 0xC593, 0x8259, 0xC594, 0x825B, 0xC595, 0x825C,
+	0xC596, 0x825D, 0xC597, 0x825E, 0xC598, 0x8260, 0xC599, 0x8261,	0xC59A, 0x8262, 0xC59B, 0x8263, 0xC59C, 0x8264, 0xC59D, 0x8265,
+	0xC59E, 0x8266, 0xC59F, 0x8267, 0xC5A0, 0x8269, 0xC5A1, 0x62E7,	0xC5A2, 0x6CDE, 0xC5A3, 0x725B, 0xC5A4, 0x626D, 0xC5A5, 0x94AE,
+	0xC5A6, 0x7EBD, 0xC5A7, 0x8113, 0xC5A8, 0x6D53, 0xC5A9, 0x519C,	0xC5AA, 0x5F04, 0xC5AB, 0x5974, 0xC5AC, 0x52AA, 0xC5AD, 0x6012,
+	0xC5AE, 0x5973, 0xC5AF, 0x6696, 0xC5B0, 0x8650, 0xC5B1, 0x759F,	0xC5B2, 0x632A, 0xC5B3, 0x61E6, 0xC5B4, 0x7CEF, 0xC5B5, 0x8BFA,
+	0xC5B6, 0x54E6, 0xC5B7, 0x6B27, 0xC5B8, 0x9E25, 0xC5B9, 0x6BB4,	0xC5BA, 0x85D5, 0xC5BB, 0x5455, 0xC5BC, 0x5076, 0xC5BD, 0x6CA4,
+	0xC5BE, 0x556A, 0xC5BF, 0x8DB4, 0xC5C0, 0x722C, 0xC5C1, 0x5E15,	0xC5C2, 0x6015, 0xC5C3, 0x7436, 0xC5C4, 0x62CD, 0xC5C5, 0x6392,
+	0xC5C6, 0x724C, 0xC5C7, 0x5F98, 0xC5C8, 0x6E43, 0xC5C9, 0x6D3E,	0xC5CA, 0x6500, 0xC5CB, 0x6F58, 0xC5CC, 0x76D8, 0xC5CD, 0x78D0,
+	0xC5CE, 0x76FC, 0xC5CF, 0x7554, 0xC5D0, 0x5224, 0xC5D1, 0x53DB,	0xC5D2, 0x4E53, 0xC5D3, 0x5E9E, 0xC5D4, 0x65C1, 0xC5D5, 0x802A,
+	0xC5D6, 0x80D6, 0xC5D7, 0x629B, 0xC5D8, 0x5486, 0xC5D9, 0x5228,	0xC5DA, 0x70AE, 0xC5DB, 0x888D, 0xC5DC, 0x8DD1, 0xC5DD, 0x6CE1,
+	0xC5DE, 0x5478, 0xC5DF, 0x80DA, 0xC5E0, 0x57F9, 0xC5E1, 0x88F4,	0xC5E2, 0x8D54, 0xC5E3, 0x966A, 0xC5E4, 0x914D, 0xC5E5, 0x4F69,
+	0xC5E6, 0x6C9B, 0xC5E7, 0x55B7, 0xC5E8, 0x76C6, 0xC5E9, 0x7830,	0xC5EA, 0x62A8, 0xC5EB, 0x70F9, 0xC5EC, 0x6F8E, 0xC5ED, 0x5F6D,
+	0xC5EE, 0x84EC, 0xC5EF, 0x68DA, 0xC5F0, 0x787C, 0xC5F1, 0x7BF7,	0xC5F2, 0x81A8, 0xC5F3, 0x670B, 0xC5F4, 0x9E4F, 0xC5F5, 0x6367,
+	0xC5F6, 0x78B0, 0xC5F7, 0x576F, 0xC5F8, 0x7812, 0xC5F9, 0x9739,	0xC5FA, 0x6279, 0xC5FB, 0x62AB, 0xC5FC, 0x5288, 0xC5FD, 0x7435,
+	0xC5FE, 0x6BD7, 0xC640, 0x826A, 0xC641, 0x826B, 0xC642, 0x826C,	0xC643, 0x826D, 0xC644, 0x8271, 0xC645, 0x8275, 0xC646, 0x8276,
+	0xC647, 0x8277, 0xC648, 0x8278, 0xC649, 0x827B, 0xC64A, 0x827C,	0xC64B, 0x8280, 0xC64C, 0x8281, 0xC64D, 0x8283, 0xC64E, 0x8285,
+	0xC64F, 0x8286, 0xC650, 0x8287, 0xC651, 0x8289, 0xC652, 0x828C,	0xC653, 0x8290, 0xC654, 0x8293, 0xC655, 0x8294, 0xC656, 0x8295,
+	0xC657, 0x8296, 0xC658, 0x829A, 0xC659, 0x829B, 0xC65A, 0x829E,	0xC65B, 0x82A0, 0xC65C, 0x82A2, 0xC65D, 0x82A3, 0xC65E, 0x82A7,
+	0xC65F, 0x82B2, 0xC660, 0x82B5, 0xC661, 0x82B6, 0xC662, 0x82BA,	0xC663, 0x82BB, 0xC664, 0x82BC, 0xC665, 0x82BF, 0xC666, 0x82C0,
+	0xC667, 0x82C2, 0xC668, 0x82C3, 0xC669, 0x82C5, 0xC66A, 0x82C6,	0xC66B, 0x82C9, 0xC66C, 0x82D0, 0xC66D, 0x82D6, 0xC66E, 0x82D9,
+	0xC66F, 0x82DA, 0xC670, 0x82DD, 0xC671, 0x82E2, 0xC672, 0x82E7,	0xC673, 0x82E8, 0xC674, 0x82E9, 0xC675, 0x82EA, 0xC676, 0x82EC,
+	0xC677, 0x82ED, 0xC678, 0x82EE, 0xC679, 0x82F0, 0xC67A, 0x82F2,	0xC67B, 0x82F3, 0xC67C, 0x82F5, 0xC67D, 0x82F6, 0xC67E, 0x82F8,
+	0xC680, 0x82FA, 0xC681, 0x82FC, 0xC682, 0x82FD, 0xC683, 0x82FE,	0xC684, 0x82FF, 0xC685, 0x8300, 0xC686, 0x830A, 0xC687, 0x830B,
+	0xC688, 0x830D, 0xC689, 0x8310, 0xC68A, 0x8312, 0xC68B, 0x8313,	0xC68C, 0x8316, 0xC68D, 0x8318, 0xC68E, 0x8319, 0xC68F, 0x831D,
+	0xC690, 0x831E, 0xC691, 0x831F, 0xC692, 0x8320, 0xC693, 0x8321,	0xC694, 0x8322, 0xC695, 0x8323, 0xC696, 0x8324, 0xC697, 0x8325,
+	0xC698, 0x8326, 0xC699, 0x8329, 0xC69A, 0x832A, 0xC69B, 0x832E,	0xC69C, 0x8330, 0xC69D, 0x8332, 0xC69E, 0x8337, 0xC69F, 0x833B,
+	0xC6A0, 0x833D, 0xC6A1, 0x5564, 0xC6A2, 0x813E, 0xC6A3, 0x75B2,	0xC6A4, 0x76AE, 0xC6A5, 0x5339, 0xC6A6, 0x75DE, 0xC6A7, 0x50FB,
+	0xC6A8, 0x5C41, 0xC6A9, 0x8B6C, 0xC6AA, 0x7BC7, 0xC6AB, 0x504F,	0xC6AC, 0x7247, 0xC6AD, 0x9A97, 0xC6AE, 0x98D8, 0xC6AF, 0x6F02,
+	0xC6B0, 0x74E2, 0xC6B1, 0x7968, 0xC6B2, 0x6487, 0xC6B3, 0x77A5,	0xC6B4, 0x62FC, 0xC6B5, 0x9891, 0xC6B6, 0x8D2B, 0xC6B7, 0x54C1,
+	0xC6B8, 0x8058, 0xC6B9, 0x4E52, 0xC6BA, 0x576A, 0xC6BB, 0x82F9,	0xC6BC, 0x840D, 0xC6BD, 0x5E73, 0xC6BE, 0x51ED, 0xC6BF, 0x74F6,
+	0xC6C0, 0x8BC4, 0xC6C1, 0x5C4F, 0xC6C2, 0x5761, 0xC6C3, 0x6CFC,	0xC6C4, 0x9887, 0xC6C5, 0x5A46, 0xC6C6, 0x7834, 0xC6C7, 0x9B44,
+	0xC6C8, 0x8FEB, 0xC6C9, 0x7C95, 0xC6CA, 0x5256, 0xC6CB, 0x6251,	0xC6CC, 0x94FA, 0xC6CD, 0x4EC6, 0xC6CE, 0x8386, 0xC6CF, 0x8461,
+	0xC6D0, 0x83E9, 0xC6D1, 0x84B2, 0xC6D2, 0x57D4, 0xC6D3, 0x6734,	0xC6D4, 0x5703, 0xC6D5, 0x666E, 0xC6D6, 0x6D66, 0xC6D7, 0x8C31,
+	0xC6D8, 0x66DD, 0xC6D9, 0x7011, 0xC6DA, 0x671F, 0xC6DB, 0x6B3A,	0xC6DC, 0x6816, 0xC6DD, 0x621A, 0xC6DE, 0x59BB, 0xC6DF, 0x4E03,
+	0xC6E0, 0x51C4, 0xC6E1, 0x6F06, 0xC6E2, 0x67D2, 0xC6E3, 0x6C8F,	0xC6E4, 0x5176, 0xC6E5, 0x68CB, 0xC6E6, 0x5947, 0xC6E7, 0x6B67,
+	0xC6E8, 0x7566, 0xC6E9, 0x5D0E, 0xC6EA, 0x8110, 0xC6EB, 0x9F50,	0xC6EC, 0x65D7, 0xC6ED, 0x7948, 0xC6EE, 0x7941, 0xC6EF, 0x9A91,
+	0xC6F0, 0x8D77, 0xC6F1, 0x5C82, 0xC6F2, 0x4E5E, 0xC6F3, 0x4F01,	0xC6F4, 0x542F, 0xC6F5, 0x5951, 0xC6F6, 0x780C, 0xC6F7, 0x5668,
+	0xC6F8, 0x6C14, 0xC6F9, 0x8FC4, 0xC6FA, 0x5F03, 0xC6FB, 0x6C7D,	0xC6FC, 0x6CE3, 0xC6FD, 0x8BAB, 0xC6FE, 0x6390, 0xC740, 0x833E,
+	0xC741, 0x833F, 0xC742, 0x8341, 0xC743, 0x8342, 0xC744, 0x8344,	0xC745, 0x8345, 0xC746, 0x8348, 0xC747, 0x834A, 0xC748, 0x834B,
+	0xC749, 0x834C, 0xC74A, 0x834D, 0xC74B, 0x834E, 0xC74C, 0x8353,	0xC74D, 0x8355, 0xC74E, 0x8356, 0xC74F, 0x8357, 0xC750, 0x8358,
+	0xC751, 0x8359, 0xC752, 0x835D, 0xC753, 0x8362, 0xC754, 0x8370,	0xC755, 0x8371, 0xC756, 0x8372, 0xC757, 0x8373, 0xC758, 0x8374,
+	0xC759, 0x8375, 0xC75A, 0x8376, 0xC75B, 0x8379, 0xC75C, 0x837A,	0xC75D, 0x837E, 0xC75E, 0x837F, 0xC75F, 0x8380, 0xC760, 0x8381,
+	0xC761, 0x8382, 0xC762, 0x8383, 0xC763, 0x8384, 0xC764, 0x8387,	0xC765, 0x8388, 0xC766, 0x838A, 0xC767, 0x838B, 0xC768, 0x838C,
+	0xC769, 0x838D, 0xC76A, 0x838F, 0xC76B, 0x8390, 0xC76C, 0x8391,	0xC76D, 0x8394, 0xC76E, 0x8395, 0xC76F, 0x8396, 0xC770, 0x8397,
+	0xC771, 0x8399, 0xC772, 0x839A, 0xC773, 0x839D, 0xC774, 0x839F,	0xC775, 0x83A1, 0xC776, 0x83A2, 0xC777, 0x83A3, 0xC778, 0x83A4,
+	0xC779, 0x83A5, 0xC77A, 0x83A6, 0xC77B, 0x83A7, 0xC77C, 0x83AC,	0xC77D, 0x83AD, 0xC77E, 0x83AE, 0xC780, 0x83AF, 0xC781, 0x83B5,
+	0xC782, 0x83BB, 0xC783, 0x83BE, 0xC784, 0x83BF, 0xC785, 0x83C2,	0xC786, 0x83C3, 0xC787, 0x83C4, 0xC788, 0x83C6, 0xC789, 0x83C8,
+	0xC78A, 0x83C9, 0xC78B, 0x83CB, 0xC78C, 0x83CD, 0xC78D, 0x83CE,	0xC78E, 0x83D0, 0xC78F, 0x83D1, 0xC790, 0x83D2, 0xC791, 0x83D3,
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+	0xC79A, 0x83E4, 0xC79B, 0x83E6, 0xC79C, 0x83E7, 0xC79D, 0x83E8,	0xC79E, 0x83EB, 0xC79F, 0x83EC, 0xC7A0, 0x83ED, 0xC7A1, 0x6070,
+	0xC7A2, 0x6D3D, 0xC7A3, 0x7275, 0xC7A4, 0x6266, 0xC7A5, 0x948E,	0xC7A6, 0x94C5, 0xC7A7, 0x5343, 0xC7A8, 0x8FC1, 0xC7A9, 0x7B7E,
+	0xC7AA, 0x4EDF, 0xC7AB, 0x8C26, 0xC7AC, 0x4E7E, 0xC7AD, 0x9ED4,	0xC7AE, 0x94B1, 0xC7AF, 0x94B3, 0xC7B0, 0x524D, 0xC7B1, 0x6F5C,
+	0xC7B2, 0x9063, 0xC7B3, 0x6D45, 0xC7B4, 0x8C34, 0xC7B5, 0x5811,	0xC7B6, 0x5D4C, 0xC7B7, 0x6B20, 0xC7B8, 0x6B49, 0xC7B9, 0x67AA,
+	0xC7BA, 0x545B, 0xC7BB, 0x8154, 0xC7BC, 0x7F8C, 0xC7BD, 0x5899,	0xC7BE, 0x8537, 0xC7BF, 0x5F3A, 0xC7C0, 0x62A2, 0xC7C1, 0x6A47,
+	0xC7C2, 0x9539, 0xC7C3, 0x6572, 0xC7C4, 0x6084, 0xC7C5, 0x6865,	0xC7C6, 0x77A7, 0xC7C7, 0x4E54, 0xC7C8, 0x4FA8, 0xC7C9, 0x5DE7,
+	0xC7CA, 0x9798, 0xC7CB, 0x64AC, 0xC7CC, 0x7FD8, 0xC7CD, 0x5CED,	0xC7CE, 0x4FCF, 0xC7CF, 0x7A8D, 0xC7D0, 0x5207, 0xC7D1, 0x8304,
+	0xC7D2, 0x4E14, 0xC7D3, 0x602F, 0xC7D4, 0x7A83, 0xC7D5, 0x94A6,	0xC7D6, 0x4FB5, 0xC7D7, 0x4EB2, 0xC7D8, 0x79E6, 0xC7D9, 0x7434,
+	0xC7DA, 0x52E4, 0xC7DB, 0x82B9, 0xC7DC, 0x64D2, 0xC7DD, 0x79BD,	0xC7DE, 0x5BDD, 0xC7DF, 0x6C81, 0xC7E0, 0x9752, 0xC7E1, 0x8F7B,
+	0xC7E2, 0x6C22, 0xC7E3, 0x503E, 0xC7E4, 0x537F, 0xC7E5, 0x6E05,	0xC7E6, 0x64CE, 0xC7E7, 0x6674, 0xC7E8, 0x6C30, 0xC7E9, 0x60C5,
+	0xC7EA, 0x9877, 0xC7EB, 0x8BF7, 0xC7EC, 0x5E86, 0xC7ED, 0x743C,	0xC7EE, 0x7A77, 0xC7EF, 0x79CB, 0xC7F0, 0x4E18, 0xC7F1, 0x90B1,
+	0xC7F2, 0x7403, 0xC7F3, 0x6C42, 0xC7F4, 0x56DA, 0xC7F5, 0x914B,	0xC7F6, 0x6CC5, 0xC7F7, 0x8D8B, 0xC7F8, 0x533A, 0xC7F9, 0x86C6,
+	0xC7FA, 0x66F2, 0xC7FB, 0x8EAF, 0xC7FC, 0x5C48, 0xC7FD, 0x9A71,	0xC7FE, 0x6E20, 0xC840, 0x83EE, 0xC841, 0x83EF, 0xC842, 0x83F3,
+	0xC843, 0x83F4, 0xC844, 0x83F5, 0xC845, 0x83F6, 0xC846, 0x83F7,	0xC847, 0x83FA, 0xC848, 0x83FB, 0xC849, 0x83FC, 0xC84A, 0x83FE,
+	0xC84B, 0x83FF, 0xC84C, 0x8400, 0xC84D, 0x8402, 0xC84E, 0x8405,	0xC84F, 0x8407, 0xC850, 0x8408, 0xC851, 0x8409, 0xC852, 0x840A,
+	0xC853, 0x8410, 0xC854, 0x8412, 0xC855, 0x8413, 0xC856, 0x8414,	0xC857, 0x8415, 0xC858, 0x8416, 0xC859, 0x8417, 0xC85A, 0x8419,
+	0xC85B, 0x841A, 0xC85C, 0x841B, 0xC85D, 0x841E, 0xC85E, 0x841F,	0xC85F, 0x8420, 0xC860, 0x8421, 0xC861, 0x8422, 0xC862, 0x8423,
+	0xC863, 0x8429, 0xC864, 0x842A, 0xC865, 0x842B, 0xC866, 0x842C,	0xC867, 0x842D, 0xC868, 0x842E, 0xC869, 0x842F, 0xC86A, 0x8430,
+	0xC86B, 0x8432, 0xC86C, 0x8433, 0xC86D, 0x8434, 0xC86E, 0x8435,	0xC86F, 0x8436, 0xC870, 0x8437, 0xC871, 0x8439, 0xC872, 0x843A,
+	0xC873, 0x843B, 0xC874, 0x843E, 0xC875, 0x843F, 0xC876, 0x8440,	0xC877, 0x8441, 0xC878, 0x8442, 0xC879, 0x8443, 0xC87A, 0x8444,
+	0xC87B, 0x8445, 0xC87C, 0x8447, 0xC87D, 0x8448, 0xC87E, 0x8449,	0xC880, 0x844A, 0xC881, 0x844B, 0xC882, 0x844C, 0xC883, 0x844D,
+	0xC884, 0x844E, 0xC885, 0x844F, 0xC886, 0x8450, 0xC887, 0x8452,	0xC888, 0x8453, 0xC889, 0x8454, 0xC88A, 0x8455, 0xC88B, 0x8456,
+	0xC88C, 0x8458, 0xC88D, 0x845D, 0xC88E, 0x845E, 0xC88F, 0x845F,	0xC890, 0x8460, 0xC891, 0x8462, 0xC892, 0x8464, 0xC893, 0x8465,
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+	0xC89C, 0x8474, 0xC89D, 0x8477, 0xC89E, 0x8479, 0xC89F, 0x847B,	0xC8A0, 0x847C, 0xC8A1, 0x53D6, 0xC8A2, 0x5A36, 0xC8A3, 0x9F8B,
+	0xC8A4, 0x8DA3, 0xC8A5, 0x53BB, 0xC8A6, 0x5708, 0xC8A7, 0x98A7,	0xC8A8, 0x6743, 0xC8A9, 0x919B, 0xC8AA, 0x6CC9, 0xC8AB, 0x5168,
+	0xC8AC, 0x75CA, 0xC8AD, 0x62F3, 0xC8AE, 0x72AC, 0xC8AF, 0x5238,	0xC8B0, 0x529D, 0xC8B1, 0x7F3A, 0xC8B2, 0x7094, 0xC8B3, 0x7638,
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+	0xC8BC, 0x71C3, 0xC8BD, 0x5189, 0xC8BE, 0x67D3, 0xC8BF, 0x74E4,	0xC8C0, 0x58E4, 0xC8C1, 0x6518, 0xC8C2, 0x56B7, 0xC8C3, 0x8BA9,
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+	0xC986, 0x84E1, 0xC987, 0x84E2, 0xC988, 0x84E4, 0xC989, 0x84E7,	0xC98A, 0x84E8, 0xC98B, 0x84E9, 0xC98C, 0x84EA, 0xC98D, 0x84EB,
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+	0xC9B6, 0x5565, 0xC9B7, 0x715E, 0xC9B8, 0x7B5B, 0xC9B9, 0x6652,	0xC9BA, 0x73CA, 0xC9BB, 0x82EB, 0xC9BC, 0x6749, 0xC9BD, 0x5C71,
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+	0xC9CE, 0x664C, 0xC9CF, 0x4E0A, 0xC9D0, 0x5C1A, 0xC9D1, 0x88F3,	0xC9D2, 0x68A2, 0xC9D3, 0x634E, 0xC9D4, 0x7A0D, 0xC9D5, 0x70E7,
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+	0xC9E6, 0x6D89, 0xC9E7, 0x793E, 0xC9E8, 0x8BBE, 0xC9E9, 0x7837,	0xC9EA, 0x7533, 0xC9EB, 0x547B, 0xC9EC, 0x4F38, 0xC9ED, 0x8EAB,
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+	0xCA80, 0x8557, 0xCA81, 0x8558, 0xCA82, 0x855A, 0xCA83, 0x855B,	0xCA84, 0x855C, 0xCA85, 0x855D, 0xCA86, 0x855F, 0xCA87, 0x8560,
+	0xCA88, 0x8561, 0xCA89, 0x8562, 0xCA8A, 0x8563, 0xCA8B, 0x8565,	0xCA8C, 0x8566, 0xCA8D, 0x8567, 0xCA8E, 0x8569, 0xCA8F, 0x856A,
+	0xCA90, 0x856B, 0xCA91, 0x856C, 0xCA92, 0x856D, 0xCA93, 0x856E,	0xCA94, 0x856F, 0xCA95, 0x8570, 0xCA96, 0x8571, 0xCA97, 0x8573,
+	0xCA98, 0x8575, 0xCA99, 0x8576, 0xCA9A, 0x8577, 0xCA9B, 0x8578,	0xCA9C, 0x857C, 0xCA9D, 0x857D, 0xCA9E, 0x857F, 0xCA9F, 0x8580,
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+	0xCAB0, 0x62FE, 0xCAB1, 0x65F6, 0xCAB2, 0x4EC0, 0xCAB3, 0x98DF,	0xCAB4, 0x8680, 0xCAB5, 0x5B9E, 0xCAB6, 0x8BC6, 0xCAB7, 0x53F2,
+	0xCAB8, 0x77E2, 0xCAB9, 0x4F7F, 0xCABA, 0x5C4E, 0xCABB, 0x9A76,	0xCABC, 0x59CB, 0xCABD, 0x5F0F, 0xCABE, 0x793A, 0xCABF, 0x58EB,
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+	0xCAD8, 0x5B88, 0xCAD9, 0x5BFF, 0xCADA, 0x6388, 0xCADB, 0x552E,	0xCADC, 0x53D7, 0xCADD, 0x7626, 0xCADE, 0x517D, 0xCADF, 0x852C,
+	0xCAE0, 0x67A2, 0xCAE1, 0x68B3, 0xCAE2, 0x6B8A, 0xCAE3, 0x6292,	0xCAE4, 0x8F93, 0xCAE5, 0x53D4, 0xCAE6, 0x8212, 0xCAE7, 0x6DD1,
+	0xCAE8, 0x758F, 0xCAE9, 0x4E66, 0xCAEA, 0x8D4E, 0xCAEB, 0x5B70,	0xCAEC, 0x719F, 0xCAED, 0x85AF, 0xCAEE, 0x6691, 0xCAEF, 0x66D9,
+	0xCAF0, 0x7F72, 0xCAF1, 0x8700, 0xCAF2, 0x9ECD, 0xCAF3, 0x9F20,	0xCAF4, 0x5C5E, 0xCAF5, 0x672F, 0xCAF6, 0x8FF0, 0xCAF7, 0x6811,
+	0xCAF8, 0x675F, 0xCAF9, 0x620D, 0xCAFA, 0x7AD6, 0xCAFB, 0x5885,	0xCAFC, 0x5EB6, 0xCAFD, 0x6570, 0xCAFE, 0x6F31, 0xCB40, 0x8582,
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+	0xCED0, 0x6DA1, 0xCED1, 0x7A9D, 0xCED2, 0x6211, 0xCED3, 0x65A1,	0xCED4, 0x5367, 0xCED5, 0x63E1, 0xCED6, 0x6C83, 0xCED7, 0x5DEB,
+	0xCED8, 0x545C, 0xCED9, 0x94A8, 0xCEDA, 0x4E4C, 0xCEDB, 0x6C61,	0xCEDC, 0x8BEC, 0xCEDD, 0x5C4B, 0xCEDE, 0x65E0, 0xCEDF, 0x829C,
+	0xCEE0, 0x68A7, 0xCEE1, 0x543E, 0xCEE2, 0x5434, 0xCEE3, 0x6BCB,	0xCEE4, 0x6B66, 0xCEE5, 0x4E94, 0xCEE6, 0x6342, 0xCEE7, 0x5348,
+	0xCEE8, 0x821E, 0xCEE9, 0x4F0D, 0xCEEA, 0x4FAE, 0xCEEB, 0x575E,	0xCEEC, 0x620A, 0xCEED, 0x96FE, 0xCEEE, 0x6664, 0xCEEF, 0x7269,
+	0xCEF0, 0x52FF, 0xCEF1, 0x52A1, 0xCEF2, 0x609F, 0xCEF3, 0x8BEF,	0xCEF4, 0x6614, 0xCEF5, 0x7199, 0xCEF6, 0x6790, 0xCEF7, 0x897F,
+	0xCEF8, 0x7852, 0xCEF9, 0x77FD, 0xCEFA, 0x6670, 0xCEFB, 0x563B,	0xCEFC, 0x5438, 0xCEFD, 0x9521, 0xCEFE, 0x727A, 0xCF40, 0x87A5,
+	0xCF41, 0x87A6, 0xCF42, 0x87A7, 0xCF43, 0x87A9, 0xCF44, 0x87AA,	0xCF45, 0x87AE, 0xCF46, 0x87B0, 0xCF47, 0x87B1, 0xCF48, 0x87B2,
+	0xCF49, 0x87B4, 0xCF4A, 0x87B6, 0xCF4B, 0x87B7, 0xCF4C, 0x87B8,	0xCF4D, 0x87B9, 0xCF4E, 0x87BB, 0xCF4F, 0x87BC, 0xCF50, 0x87BE,
+	0xCF51, 0x87BF, 0xCF52, 0x87C1, 0xCF53, 0x87C2, 0xCF54, 0x87C3,	0xCF55, 0x87C4, 0xCF56, 0x87C5, 0xCF57, 0x87C7, 0xCF58, 0x87C8,
+	0xCF59, 0x87C9, 0xCF5A, 0x87CC, 0xCF5B, 0x87CD, 0xCF5C, 0x87CE,	0xCF5D, 0x87CF, 0xCF5E, 0x87D0, 0xCF5F, 0x87D4, 0xCF60, 0x87D5,
+	0xCF61, 0x87D6, 0xCF62, 0x87D7, 0xCF63, 0x87D8, 0xCF64, 0x87D9,	0xCF65, 0x87DA, 0xCF66, 0x87DC, 0xCF67, 0x87DD, 0xCF68, 0x87DE,
+	0xCF69, 0x87DF, 0xCF6A, 0x87E1, 0xCF6B, 0x87E2, 0xCF6C, 0x87E3,	0xCF6D, 0x87E4, 0xCF6E, 0x87E6, 0xCF6F, 0x87E7, 0xCF70, 0x87E8,
+	0xCF71, 0x87E9, 0xCF72, 0x87EB, 0xCF73, 0x87EC, 0xCF74, 0x87ED,	0xCF75, 0x87EF, 0xCF76, 0x87F0, 0xCF77, 0x87F1, 0xCF78, 0x87F2,
+	0xCF79, 0x87F3, 0xCF7A, 0x87F4, 0xCF7B, 0x87F5, 0xCF7C, 0x87F6,	0xCF7D, 0x87F7, 0xCF7E, 0x87F8, 0xCF80, 0x87FA, 0xCF81, 0x87FB,
+	0xCF82, 0x87FC, 0xCF83, 0x87FD, 0xCF84, 0x87FF, 0xCF85, 0x8800,	0xCF86, 0x8801, 0xCF87, 0x8802, 0xCF88, 0x8804, 0xCF89, 0x8805,
+	0xCF8A, 0x8806, 0xCF8B, 0x8807, 0xCF8C, 0x8808, 0xCF8D, 0x8809,	0xCF8E, 0x880B, 0xCF8F, 0x880C, 0xCF90, 0x880D, 0xCF91, 0x880E,
+	0xCF92, 0x880F, 0xCF93, 0x8810, 0xCF94, 0x8811, 0xCF95, 0x8812,	0xCF96, 0x8814, 0xCF97, 0x8817, 0xCF98, 0x8818, 0xCF99, 0x8819,
+	0xCF9A, 0x881A, 0xCF9B, 0x881C, 0xCF9C, 0x881D, 0xCF9D, 0x881E,	0xCF9E, 0x881F, 0xCF9F, 0x8820, 0xCFA0, 0x8823, 0xCFA1, 0x7A00,
+	0xCFA2, 0x606F, 0xCFA3, 0x5E0C, 0xCFA4, 0x6089, 0xCFA5, 0x819D,	0xCFA6, 0x5915, 0xCFA7, 0x60DC, 0xCFA8, 0x7184, 0xCFA9, 0x70EF,
+	0xCFAA, 0x6EAA, 0xCFAB, 0x6C50, 0xCFAC, 0x7280, 0xCFAD, 0x6A84,	0xCFAE, 0x88AD, 0xCFAF, 0x5E2D, 0xCFB0, 0x4E60, 0xCFB1, 0x5AB3,
+	0xCFB2, 0x559C, 0xCFB3, 0x94E3, 0xCFB4, 0x6D17, 0xCFB5, 0x7CFB,	0xCFB6, 0x9699, 0xCFB7, 0x620F, 0xCFB8, 0x7EC6, 0xCFB9, 0x778E,
+	0xCFBA, 0x867E, 0xCFBB, 0x5323, 0xCFBC, 0x971E, 0xCFBD, 0x8F96,	0xCFBE, 0x6687, 0xCFBF, 0x5CE1, 0xCFC0, 0x4FA0, 0xCFC1, 0x72ED,
+	0xCFC2, 0x4E0B, 0xCFC3, 0x53A6, 0xCFC4, 0x590F, 0xCFC5, 0x5413,	0xCFC6, 0x6380, 0xCFC7, 0x9528, 0xCFC8, 0x5148, 0xCFC9, 0x4ED9,
+	0xCFCA, 0x9C9C, 0xCFCB, 0x7EA4, 0xCFCC, 0x54B8, 0xCFCD, 0x8D24,	0xCFCE, 0x8854, 0xCFCF, 0x8237, 0xCFD0, 0x95F2, 0xCFD1, 0x6D8E,
+	0xCFD2, 0x5F26, 0xCFD3, 0x5ACC, 0xCFD4, 0x663E, 0xCFD5, 0x9669,	0xCFD6, 0x73B0, 0xCFD7, 0x732E, 0xCFD8, 0x53BF, 0xCFD9, 0x817A,
+	0xCFDA, 0x9985, 0xCFDB, 0x7FA1, 0xCFDC, 0x5BAA, 0xCFDD, 0x9677,	0xCFDE, 0x9650, 0xCFDF, 0x7EBF, 0xCFE0, 0x76F8, 0xCFE1, 0x53A2,
+	0xCFE2, 0x9576, 0xCFE3, 0x9999, 0xCFE4, 0x7BB1, 0xCFE5, 0x8944,	0xCFE6, 0x6E58, 0xCFE7, 0x4E61, 0xCFE8, 0x7FD4, 0xCFE9, 0x7965,
+	0xCFEA, 0x8BE6, 0xCFEB, 0x60F3, 0xCFEC, 0x54CD, 0xCFED, 0x4EAB,	0xCFEE, 0x9879, 0xCFEF, 0x5DF7, 0xCFF0, 0x6A61, 0xCFF1, 0x50CF,
+	0xCFF2, 0x5411, 0xCFF3, 0x8C61, 0xCFF4, 0x8427, 0xCFF5, 0x785D,	0xCFF6, 0x9704, 0xCFF7, 0x524A, 0xCFF8, 0x54EE, 0xCFF9, 0x56A3,
+	0xCFFA, 0x9500, 0xCFFB, 0x6D88, 0xCFFC, 0x5BB5, 0xCFFD, 0x6DC6,	0xCFFE, 0x6653, 0xD040, 0x8824, 0xD041, 0x8825, 0xD042, 0x8826,
+	0xD043, 0x8827, 0xD044, 0x8828, 0xD045, 0x8829, 0xD046, 0x882A,	0xD047, 0x882B, 0xD048, 0x882C, 0xD049, 0x882D, 0xD04A, 0x882E,
+	0xD04B, 0x882F, 0xD04C, 0x8830, 0xD04D, 0x8831, 0xD04E, 0x8833,	0xD04F, 0x8834, 0xD050, 0x8835, 0xD051, 0x8836, 0xD052, 0x8837,
+	0xD053, 0x8838, 0xD054, 0x883A, 0xD055, 0x883B, 0xD056, 0x883D,	0xD057, 0x883E, 0xD058, 0x883F, 0xD059, 0x8841, 0xD05A, 0x8842,
+	0xD05B, 0x8843, 0xD05C, 0x8846, 0xD05D, 0x8847, 0xD05E, 0x8848,	0xD05F, 0x8849, 0xD060, 0x884A, 0xD061, 0x884B, 0xD062, 0x884E,
+	0xD063, 0x884F, 0xD064, 0x8850, 0xD065, 0x8851, 0xD066, 0x8852,	0xD067, 0x8853, 0xD068, 0x8855, 0xD069, 0x8856, 0xD06A, 0x8858,
+	0xD06B, 0x885A, 0xD06C, 0x885B, 0xD06D, 0x885C, 0xD06E, 0x885D,	0xD06F, 0x885E, 0xD070, 0x885F, 0xD071, 0x8860, 0xD072, 0x8866,
+	0xD073, 0x8867, 0xD074, 0x886A, 0xD075, 0x886D, 0xD076, 0x886F,	0xD077, 0x8871, 0xD078, 0x8873, 0xD079, 0x8874, 0xD07A, 0x8875,
+	0xD07B, 0x8876, 0xD07C, 0x8878, 0xD07D, 0x8879, 0xD07E, 0x887A,	0xD080, 0x887B, 0xD081, 0x887C, 0xD082, 0x8880, 0xD083, 0x8883,
+	0xD084, 0x8886, 0xD085, 0x8887, 0xD086, 0x8889, 0xD087, 0x888A,	0xD088, 0x888C, 0xD089, 0x888E, 0xD08A, 0x888F, 0xD08B, 0x8890,
+	0xD08C, 0x8891, 0xD08D, 0x8893, 0xD08E, 0x8894, 0xD08F, 0x8895,	0xD090, 0x8897, 0xD091, 0x8898, 0xD092, 0x8899, 0xD093, 0x889A,
+	0xD094, 0x889B, 0xD095, 0x889D, 0xD096, 0x889E, 0xD097, 0x889F,	0xD098, 0x88A0, 0xD099, 0x88A1, 0xD09A, 0x88A3, 0xD09B, 0x88A5,
+	0xD09C, 0x88A6, 0xD09D, 0x88A7, 0xD09E, 0x88A8, 0xD09F, 0x88A9,	0xD0A0, 0x88AA, 0xD0A1, 0x5C0F, 0xD0A2, 0x5B5D, 0xD0A3, 0x6821,
+	0xD0A4, 0x8096, 0xD0A5, 0x5578, 0xD0A6, 0x7B11, 0xD0A7, 0x6548,	0xD0A8, 0x6954, 0xD0A9, 0x4E9B, 0xD0AA, 0x6B47, 0xD0AB, 0x874E,
+	0xD0AC, 0x978B, 0xD0AD, 0x534F, 0xD0AE, 0x631F, 0xD0AF, 0x643A,	0xD0B0, 0x90AA, 0xD0B1, 0x659C, 0xD0B2, 0x80C1, 0xD0B3, 0x8C10,
+	0xD0B4, 0x5199, 0xD0B5, 0x68B0, 0xD0B6, 0x5378, 0xD0B7, 0x87F9,	0xD0B8, 0x61C8, 0xD0B9, 0x6CC4, 0xD0BA, 0x6CFB, 0xD0BB, 0x8C22,
+	0xD0BC, 0x5C51, 0xD0BD, 0x85AA, 0xD0BE, 0x82AF, 0xD0BF, 0x950C,	0xD0C0, 0x6B23, 0xD0C1, 0x8F9B, 0xD0C2, 0x65B0, 0xD0C3, 0x5FFB,
+	0xD0C4, 0x5FC3, 0xD0C5, 0x4FE1, 0xD0C6, 0x8845, 0xD0C7, 0x661F,	0xD0C8, 0x8165, 0xD0C9, 0x7329, 0xD0CA, 0x60FA, 0xD0CB, 0x5174,
+	0xD0CC, 0x5211, 0xD0CD, 0x578B, 0xD0CE, 0x5F62, 0xD0CF, 0x90A2,	0xD0D0, 0x884C, 0xD0D1, 0x9192, 0xD0D2, 0x5E78, 0xD0D3, 0x674F,
+	0xD0D4, 0x6027, 0xD0D5, 0x59D3, 0xD0D6, 0x5144, 0xD0D7, 0x51F6,	0xD0D8, 0x80F8, 0xD0D9, 0x5308, 0xD0DA, 0x6C79, 0xD0DB, 0x96C4,
+	0xD0DC, 0x718A, 0xD0DD, 0x4F11, 0xD0DE, 0x4FEE, 0xD0DF, 0x7F9E,	0xD0E0, 0x673D, 0xD0E1, 0x55C5, 0xD0E2, 0x9508, 0xD0E3, 0x79C0,
+	0xD0E4, 0x8896, 0xD0E5, 0x7EE3, 0xD0E6, 0x589F, 0xD0E7, 0x620C,	0xD0E8, 0x9700, 0xD0E9, 0x865A, 0xD0EA, 0x5618, 0xD0EB, 0x987B,
+	0xD0EC, 0x5F90, 0xD0ED, 0x8BB8, 0xD0EE, 0x84C4, 0xD0EF, 0x9157,	0xD0F0, 0x53D9, 0xD0F1, 0x65ED, 0xD0F2, 0x5E8F, 0xD0F3, 0x755C,
+	0xD0F4, 0x6064, 0xD0F5, 0x7D6E, 0xD0F6, 0x5A7F, 0xD0F7, 0x7EEA,	0xD0F8, 0x7EED, 0xD0F9, 0x8F69, 0xD0FA, 0x55A7, 0xD0FB, 0x5BA3,
+	0xD0FC, 0x60AC, 0xD0FD, 0x65CB, 0xD0FE, 0x7384, 0xD140, 0x88AC,	0xD141, 0x88AE, 0xD142, 0x88AF, 0xD143, 0x88B0, 0xD144, 0x88B2,
+	0xD145, 0x88B3, 0xD146, 0x88B4, 0xD147, 0x88B5, 0xD148, 0x88B6,	0xD149, 0x88B8, 0xD14A, 0x88B9, 0xD14B, 0x88BA, 0xD14C, 0x88BB,
+	0xD14D, 0x88BD, 0xD14E, 0x88BE, 0xD14F, 0x88BF, 0xD150, 0x88C0,	0xD151, 0x88C3, 0xD152, 0x88C4, 0xD153, 0x88C7, 0xD154, 0x88C8,
+	0xD155, 0x88CA, 0xD156, 0x88CB, 0xD157, 0x88CC, 0xD158, 0x88CD,	0xD159, 0x88CF, 0xD15A, 0x88D0, 0xD15B, 0x88D1, 0xD15C, 0x88D3,
+	0xD15D, 0x88D6, 0xD15E, 0x88D7, 0xD15F, 0x88DA, 0xD160, 0x88DB,	0xD161, 0x88DC, 0xD162, 0x88DD, 0xD163, 0x88DE, 0xD164, 0x88E0,
+	0xD165, 0x88E1, 0xD166, 0x88E6, 0xD167, 0x88E7, 0xD168, 0x88E9,	0xD169, 0x88EA, 0xD16A, 0x88EB, 0xD16B, 0x88EC, 0xD16C, 0x88ED,
+	0xD16D, 0x88EE, 0xD16E, 0x88EF, 0xD16F, 0x88F2, 0xD170, 0x88F5,	0xD171, 0x88F6, 0xD172, 0x88F7, 0xD173, 0x88FA, 0xD174, 0x88FB,
+	0xD175, 0x88FD, 0xD176, 0x88FF, 0xD177, 0x8900, 0xD178, 0x8901,	0xD179, 0x8903, 0xD17A, 0x8904, 0xD17B, 0x8905, 0xD17C, 0x8906,
+	0xD17D, 0x8907, 0xD17E, 0x8908, 0xD180, 0x8909, 0xD181, 0x890B,	0xD182, 0x890C, 0xD183, 0x890D, 0xD184, 0x890E, 0xD185, 0x890F,
+	0xD186, 0x8911, 0xD187, 0x8914, 0xD188, 0x8915, 0xD189, 0x8916,	0xD18A, 0x8917, 0xD18B, 0x8918, 0xD18C, 0x891C, 0xD18D, 0x891D,
+	0xD18E, 0x891E, 0xD18F, 0x891F, 0xD190, 0x8920, 0xD191, 0x8922,	0xD192, 0x8923, 0xD193, 0x8924, 0xD194, 0x8926, 0xD195, 0x8927,
+	0xD196, 0x8928, 0xD197, 0x8929, 0xD198, 0x892C, 0xD199, 0x892D,	0xD19A, 0x892E, 0xD19B, 0x892F, 0xD19C, 0x8931, 0xD19D, 0x8932,
+	0xD19E, 0x8933, 0xD19F, 0x8935, 0xD1A0, 0x8937, 0xD1A1, 0x9009,	0xD1A2, 0x7663, 0xD1A3, 0x7729, 0xD1A4, 0x7EDA, 0xD1A5, 0x9774,
+	0xD1A6, 0x859B, 0xD1A7, 0x5B66, 0xD1A8, 0x7A74, 0xD1A9, 0x96EA,	0xD1AA, 0x8840, 0xD1AB, 0x52CB, 0xD1AC, 0x718F, 0xD1AD, 0x5FAA,
+	0xD1AE, 0x65EC, 0xD1AF, 0x8BE2, 0xD1B0, 0x5BFB, 0xD1B1, 0x9A6F,	0xD1B2, 0x5DE1, 0xD1B3, 0x6B89, 0xD1B4, 0x6C5B, 0xD1B5, 0x8BAD,
+	0xD1B6, 0x8BAF, 0xD1B7, 0x900A, 0xD1B8, 0x8FC5, 0xD1B9, 0x538B,	0xD1BA, 0x62BC, 0xD1BB, 0x9E26, 0xD1BC, 0x9E2D, 0xD1BD, 0x5440,
+	0xD1BE, 0x4E2B, 0xD1BF, 0x82BD, 0xD1C0, 0x7259, 0xD1C1, 0x869C,	0xD1C2, 0x5D16, 0xD1C3, 0x8859, 0xD1C4, 0x6DAF, 0xD1C5, 0x96C5,
+	0xD1C6, 0x54D1, 0xD1C7, 0x4E9A, 0xD1C8, 0x8BB6, 0xD1C9, 0x7109,	0xD1CA, 0x54BD, 0xD1CB, 0x9609, 0xD1CC, 0x70DF, 0xD1CD, 0x6DF9,
+	0xD1CE, 0x76D0, 0xD1CF, 0x4E25, 0xD1D0, 0x7814, 0xD1D1, 0x8712,	0xD1D2, 0x5CA9, 0xD1D3, 0x5EF6, 0xD1D4, 0x8A00, 0xD1D5, 0x989C,
+	0xD1D6, 0x960E, 0xD1D7, 0x708E, 0xD1D8, 0x6CBF, 0xD1D9, 0x5944,	0xD1DA, 0x63A9, 0xD1DB, 0x773C, 0xD1DC, 0x884D, 0xD1DD, 0x6F14,
+	0xD1DE, 0x8273, 0xD1DF, 0x5830, 0xD1E0, 0x71D5, 0xD1E1, 0x538C,	0xD1E2, 0x781A, 0xD1E3, 0x96C1, 0xD1E4, 0x5501, 0xD1E5, 0x5F66,
+	0xD1E6, 0x7130, 0xD1E7, 0x5BB4, 0xD1E8, 0x8C1A, 0xD1E9, 0x9A8C,	0xD1EA, 0x6B83, 0xD1EB, 0x592E, 0xD1EC, 0x9E2F, 0xD1ED, 0x79E7,
+	0xD1EE, 0x6768, 0xD1EF, 0x626C, 0xD1F0, 0x4F6F, 0xD1F1, 0x75A1,	0xD1F2, 0x7F8A, 0xD1F3, 0x6D0B, 0xD1F4, 0x9633, 0xD1F5, 0x6C27,
+	0xD1F6, 0x4EF0, 0xD1F7, 0x75D2, 0xD1F8, 0x517B, 0xD1F9, 0x6837,	0xD1FA, 0x6F3E, 0xD1FB, 0x9080, 0xD1FC, 0x8170, 0xD1FD, 0x5996,
+	0xD1FE, 0x7476, 0xD240, 0x8938, 0xD241, 0x8939, 0xD242, 0x893A,	0xD243, 0x893B, 0xD244, 0x893C, 0xD245, 0x893D, 0xD246, 0x893E,
+	0xD247, 0x893F, 0xD248, 0x8940, 0xD249, 0x8942, 0xD24A, 0x8943,	0xD24B, 0x8945, 0xD24C, 0x8946, 0xD24D, 0x8947, 0xD24E, 0x8948,
+	0xD24F, 0x8949, 0xD250, 0x894A, 0xD251, 0x894B, 0xD252, 0x894C,	0xD253, 0x894D, 0xD254, 0x894E, 0xD255, 0x894F, 0xD256, 0x8950,
+	0xD257, 0x8951, 0xD258, 0x8952, 0xD259, 0x8953, 0xD25A, 0x8954,	0xD25B, 0x8955, 0xD25C, 0x8956, 0xD25D, 0x8957, 0xD25E, 0x8958,
+	0xD25F, 0x8959, 0xD260, 0x895A, 0xD261, 0x895B, 0xD262, 0x895C,	0xD263, 0x895D, 0xD264, 0x8960, 0xD265, 0x8961, 0xD266, 0x8962,
+	0xD267, 0x8963, 0xD268, 0x8964, 0xD269, 0x8965, 0xD26A, 0x8967,	0xD26B, 0x8968, 0xD26C, 0x8969, 0xD26D, 0x896A, 0xD26E, 0x896B,
+	0xD26F, 0x896C, 0xD270, 0x896D, 0xD271, 0x896E, 0xD272, 0x896F,	0xD273, 0x8970, 0xD274, 0x8971, 0xD275, 0x8972, 0xD276, 0x8973,
+	0xD277, 0x8974, 0xD278, 0x8975, 0xD279, 0x8976, 0xD27A, 0x8977,	0xD27B, 0x8978, 0xD27C, 0x8979, 0xD27D, 0x897A, 0xD27E, 0x897C,
+	0xD280, 0x897D, 0xD281, 0x897E, 0xD282, 0x8980, 0xD283, 0x8982,	0xD284, 0x8984, 0xD285, 0x8985, 0xD286, 0x8987, 0xD287, 0x8988,
+	0xD288, 0x8989, 0xD289, 0x898A, 0xD28A, 0x898B, 0xD28B, 0x898C,	0xD28C, 0x898D, 0xD28D, 0x898E, 0xD28E, 0x898F, 0xD28F, 0x8990,
+	0xD290, 0x8991, 0xD291, 0x8992, 0xD292, 0x8993, 0xD293, 0x8994,	0xD294, 0x8995, 0xD295, 0x8996, 0xD296, 0x8997, 0xD297, 0x8998,
+	0xD298, 0x8999, 0xD299, 0x899A, 0xD29A, 0x899B, 0xD29B, 0x899C,	0xD29C, 0x899D, 0xD29D, 0x899E, 0xD29E, 0x899F, 0xD29F, 0x89A0,
+	0xD2A0, 0x89A1, 0xD2A1, 0x6447, 0xD2A2, 0x5C27, 0xD2A3, 0x9065,	0xD2A4, 0x7A91, 0xD2A5, 0x8C23, 0xD2A6, 0x59DA, 0xD2A7, 0x54AC,
+	0xD2A8, 0x8200, 0xD2A9, 0x836F, 0xD2AA, 0x8981, 0xD2AB, 0x8000,	0xD2AC, 0x6930, 0xD2AD, 0x564E, 0xD2AE, 0x8036, 0xD2AF, 0x7237,
+	0xD2B0, 0x91CE, 0xD2B1, 0x51B6, 0xD2B2, 0x4E5F, 0xD2B3, 0x9875,	0xD2B4, 0x6396, 0xD2B5, 0x4E1A, 0xD2B6, 0x53F6, 0xD2B7, 0x66F3,
+	0xD2B8, 0x814B, 0xD2B9, 0x591C, 0xD2BA, 0x6DB2, 0xD2BB, 0x4E00,	0xD2BC, 0x58F9, 0xD2BD, 0x533B, 0xD2BE, 0x63D6, 0xD2BF, 0x94F1,
+	0xD2C0, 0x4F9D, 0xD2C1, 0x4F0A, 0xD2C2, 0x8863, 0xD2C3, 0x9890,	0xD2C4, 0x5937, 0xD2C5, 0x9057, 0xD2C6, 0x79FB, 0xD2C7, 0x4EEA,
+	0xD2C8, 0x80F0, 0xD2C9, 0x7591, 0xD2CA, 0x6C82, 0xD2CB, 0x5B9C,	0xD2CC, 0x59E8, 0xD2CD, 0x5F5D, 0xD2CE, 0x6905, 0xD2CF, 0x8681,
+	0xD2D0, 0x501A, 0xD2D1, 0x5DF2, 0xD2D2, 0x4E59, 0xD2D3, 0x77E3,	0xD2D4, 0x4EE5, 0xD2D5, 0x827A, 0xD2D6, 0x6291, 0xD2D7, 0x6613,
+	0xD2D8, 0x9091, 0xD2D9, 0x5C79, 0xD2DA, 0x4EBF, 0xD2DB, 0x5F79,	0xD2DC, 0x81C6, 0xD2DD, 0x9038, 0xD2DE, 0x8084, 0xD2DF, 0x75AB,
+	0xD2E0, 0x4EA6, 0xD2E1, 0x88D4, 0xD2E2, 0x610F, 0xD2E3, 0x6BC5,	0xD2E4, 0x5FC6, 0xD2E5, 0x4E49, 0xD2E6, 0x76CA, 0xD2E7, 0x6EA2,
+	0xD2E8, 0x8BE3, 0xD2E9, 0x8BAE, 0xD2EA, 0x8C0A, 0xD2EB, 0x8BD1,	0xD2EC, 0x5F02, 0xD2ED, 0x7FFC, 0xD2EE, 0x7FCC, 0xD2EF, 0x7ECE,
+	0xD2F0, 0x8335, 0xD2F1, 0x836B, 0xD2F2, 0x56E0, 0xD2F3, 0x6BB7,	0xD2F4, 0x97F3, 0xD2F5, 0x9634, 0xD2F6, 0x59FB, 0xD2F7, 0x541F,
+	0xD2F8, 0x94F6, 0xD2F9, 0x6DEB, 0xD2FA, 0x5BC5, 0xD2FB, 0x996E,	0xD2FC, 0x5C39, 0xD2FD, 0x5F15, 0xD2FE, 0x9690, 0xD340, 0x89A2,
+	0xD341, 0x89A3, 0xD342, 0x89A4, 0xD343, 0x89A5, 0xD344, 0x89A6,	0xD345, 0x89A7, 0xD346, 0x89A8, 0xD347, 0x89A9, 0xD348, 0x89AA,
+	0xD349, 0x89AB, 0xD34A, 0x89AC, 0xD34B, 0x89AD, 0xD34C, 0x89AE,	0xD34D, 0x89AF, 0xD34E, 0x89B0, 0xD34F, 0x89B1, 0xD350, 0x89B2,
+	0xD351, 0x89B3, 0xD352, 0x89B4, 0xD353, 0x89B5, 0xD354, 0x89B6,	0xD355, 0x89B7, 0xD356, 0x89B8, 0xD357, 0x89B9, 0xD358, 0x89BA,
+	0xD359, 0x89BB, 0xD35A, 0x89BC, 0xD35B, 0x89BD, 0xD35C, 0x89BE,	0xD35D, 0x89BF, 0xD35E, 0x89C0, 0xD35F, 0x89C3, 0xD360, 0x89CD,
+	0xD361, 0x89D3, 0xD362, 0x89D4, 0xD363, 0x89D5, 0xD364, 0x89D7,	0xD365, 0x89D8, 0xD366, 0x89D9, 0xD367, 0x89DB, 0xD368, 0x89DD,
+	0xD369, 0x89DF, 0xD36A, 0x89E0, 0xD36B, 0x89E1, 0xD36C, 0x89E2,	0xD36D, 0x89E4, 0xD36E, 0x89E7, 0xD36F, 0x89E8, 0xD370, 0x89E9,
+	0xD371, 0x89EA, 0xD372, 0x89EC, 0xD373, 0x89ED, 0xD374, 0x89EE,	0xD375, 0x89F0, 0xD376, 0x89F1, 0xD377, 0x89F2, 0xD378, 0x89F4,
+	0xD379, 0x89F5, 0xD37A, 0x89F6, 0xD37B, 0x89F7, 0xD37C, 0x89F8,	0xD37D, 0x89F9, 0xD37E, 0x89FA, 0xD380, 0x89FB, 0xD381, 0x89FC,
+	0xD382, 0x89FD, 0xD383, 0x89FE, 0xD384, 0x89FF, 0xD385, 0x8A01,	0xD386, 0x8A02, 0xD387, 0x8A03, 0xD388, 0x8A04, 0xD389, 0x8A05,
+	0xD38A, 0x8A06, 0xD38B, 0x8A08, 0xD38C, 0x8A09, 0xD38D, 0x8A0A,	0xD38E, 0x8A0B, 0xD38F, 0x8A0C, 0xD390, 0x8A0D, 0xD391, 0x8A0E,
+	0xD392, 0x8A0F, 0xD393, 0x8A10, 0xD394, 0x8A11, 0xD395, 0x8A12,	0xD396, 0x8A13, 0xD397, 0x8A14, 0xD398, 0x8A15, 0xD399, 0x8A16,
+	0xD39A, 0x8A17, 0xD39B, 0x8A18, 0xD39C, 0x8A19, 0xD39D, 0x8A1A,	0xD39E, 0x8A1B, 0xD39F, 0x8A1C, 0xD3A0, 0x8A1D, 0xD3A1, 0x5370,
+	0xD3A2, 0x82F1, 0xD3A3, 0x6A31, 0xD3A4, 0x5A74, 0xD3A5, 0x9E70,	0xD3A6, 0x5E94, 0xD3A7, 0x7F28, 0xD3A8, 0x83B9, 0xD3A9, 0x8424,
+	0xD3AA, 0x8425, 0xD3AB, 0x8367, 0xD3AC, 0x8747, 0xD3AD, 0x8FCE,	0xD3AE, 0x8D62, 0xD3AF, 0x76C8, 0xD3B0, 0x5F71, 0xD3B1, 0x9896,
+	0xD3B2, 0x786C, 0xD3B3, 0x6620, 0xD3B4, 0x54DF, 0xD3B5, 0x62E5,	0xD3B6, 0x4F63, 0xD3B7, 0x81C3, 0xD3B8, 0x75C8, 0xD3B9, 0x5EB8,
+	0xD3BA, 0x96CD, 0xD3BB, 0x8E0A, 0xD3BC, 0x86F9, 0xD3BD, 0x548F,	0xD3BE, 0x6CF3, 0xD3BF, 0x6D8C, 0xD3C0, 0x6C38, 0xD3C1, 0x607F,
+	0xD3C2, 0x52C7, 0xD3C3, 0x7528, 0xD3C4, 0x5E7D, 0xD3C5, 0x4F18,	0xD3C6, 0x60A0, 0xD3C7, 0x5FE7, 0xD3C8, 0x5C24, 0xD3C9, 0x7531,
+	0xD3CA, 0x90AE, 0xD3CB, 0x94C0, 0xD3CC, 0x72B9, 0xD3CD, 0x6CB9,	0xD3CE, 0x6E38, 0xD3CF, 0x9149, 0xD3D0, 0x6709, 0xD3D1, 0x53CB,
+	0xD3D2, 0x53F3, 0xD3D3, 0x4F51, 0xD3D4, 0x91C9, 0xD3D5, 0x8BF1,	0xD3D6, 0x53C8, 0xD3D7, 0x5E7C, 0xD3D8, 0x8FC2, 0xD3D9, 0x6DE4,
+	0xD3DA, 0x4E8E, 0xD3DB, 0x76C2, 0xD3DC, 0x6986, 0xD3DD, 0x865E,	0xD3DE, 0x611A, 0xD3DF, 0x8206, 0xD3E0, 0x4F59, 0xD3E1, 0x4FDE,
+	0xD3E2, 0x903E, 0xD3E3, 0x9C7C, 0xD3E4, 0x6109, 0xD3E5, 0x6E1D,	0xD3E6, 0x6E14, 0xD3E7, 0x9685, 0xD3E8, 0x4E88, 0xD3E9, 0x5A31,
+	0xD3EA, 0x96E8, 0xD3EB, 0x4E0E, 0xD3EC, 0x5C7F, 0xD3ED, 0x79B9,	0xD3EE, 0x5B87, 0xD3EF, 0x8BED, 0xD3F0, 0x7FBD, 0xD3F1, 0x7389,
+	0xD3F2, 0x57DF, 0xD3F3, 0x828B, 0xD3F4, 0x90C1, 0xD3F5, 0x5401,	0xD3F6, 0x9047, 0xD3F7, 0x55BB, 0xD3F8, 0x5CEA, 0xD3F9, 0x5FA1,
+	0xD3FA, 0x6108, 0xD3FB, 0x6B32, 0xD3FC, 0x72F1, 0xD3FD, 0x80B2,	0xD3FE, 0x8A89, 0xD440, 0x8A1E, 0xD441, 0x8A1F, 0xD442, 0x8A20,
+	0xD443, 0x8A21, 0xD444, 0x8A22, 0xD445, 0x8A23, 0xD446, 0x8A24,	0xD447, 0x8A25, 0xD448, 0x8A26, 0xD449, 0x8A27, 0xD44A, 0x8A28,
+	0xD44B, 0x8A29, 0xD44C, 0x8A2A, 0xD44D, 0x8A2B, 0xD44E, 0x8A2C,	0xD44F, 0x8A2D, 0xD450, 0x8A2E, 0xD451, 0x8A2F, 0xD452, 0x8A30,
+	0xD453, 0x8A31, 0xD454, 0x8A32, 0xD455, 0x8A33, 0xD456, 0x8A34,	0xD457, 0x8A35, 0xD458, 0x8A36, 0xD459, 0x8A37, 0xD45A, 0x8A38,
+	0xD45B, 0x8A39, 0xD45C, 0x8A3A, 0xD45D, 0x8A3B, 0xD45E, 0x8A3C,	0xD45F, 0x8A3D, 0xD460, 0x8A3F, 0xD461, 0x8A40, 0xD462, 0x8A41,
+	0xD463, 0x8A42, 0xD464, 0x8A43, 0xD465, 0x8A44, 0xD466, 0x8A45,	0xD467, 0x8A46, 0xD468, 0x8A47, 0xD469, 0x8A49, 0xD46A, 0x8A4A,
+	0xD46B, 0x8A4B, 0xD46C, 0x8A4C, 0xD46D, 0x8A4D, 0xD46E, 0x8A4E,	0xD46F, 0x8A4F, 0xD470, 0x8A50, 0xD471, 0x8A51, 0xD472, 0x8A52,
+	0xD473, 0x8A53, 0xD474, 0x8A54, 0xD475, 0x8A55, 0xD476, 0x8A56,	0xD477, 0x8A57, 0xD478, 0x8A58, 0xD479, 0x8A59, 0xD47A, 0x8A5A,
+	0xD47B, 0x8A5B, 0xD47C, 0x8A5C, 0xD47D, 0x8A5D, 0xD47E, 0x8A5E,	0xD480, 0x8A5F, 0xD481, 0x8A60, 0xD482, 0x8A61, 0xD483, 0x8A62,
+	0xD484, 0x8A63, 0xD485, 0x8A64, 0xD486, 0x8A65, 0xD487, 0x8A66,	0xD488, 0x8A67, 0xD489, 0x8A68, 0xD48A, 0x8A69, 0xD48B, 0x8A6A,
+	0xD48C, 0x8A6B, 0xD48D, 0x8A6C, 0xD48E, 0x8A6D, 0xD48F, 0x8A6E,	0xD490, 0x8A6F, 0xD491, 0x8A70, 0xD492, 0x8A71, 0xD493, 0x8A72,
+	0xD494, 0x8A73, 0xD495, 0x8A74, 0xD496, 0x8A75, 0xD497, 0x8A76,	0xD498, 0x8A77, 0xD499, 0x8A78, 0xD49A, 0x8A7A, 0xD49B, 0x8A7B,
+	0xD49C, 0x8A7C, 0xD49D, 0x8A7D, 0xD49E, 0x8A7E, 0xD49F, 0x8A7F,	0xD4A0, 0x8A80, 0xD4A1, 0x6D74, 0xD4A2, 0x5BD3, 0xD4A3, 0x88D5,
+	0xD4A4, 0x9884, 0xD4A5, 0x8C6B, 0xD4A6, 0x9A6D, 0xD4A7, 0x9E33,	0xD4A8, 0x6E0A, 0xD4A9, 0x51A4, 0xD4AA, 0x5143, 0xD4AB, 0x57A3,
+	0xD4AC, 0x8881, 0xD4AD, 0x539F, 0xD4AE, 0x63F4, 0xD4AF, 0x8F95,	0xD4B0, 0x56ED, 0xD4B1, 0x5458, 0xD4B2, 0x5706, 0xD4B3, 0x733F,
+	0xD4B4, 0x6E90, 0xD4B5, 0x7F18, 0xD4B6, 0x8FDC, 0xD4B7, 0x82D1,	0xD4B8, 0x613F, 0xD4B9, 0x6028, 0xD4BA, 0x9662, 0xD4BB, 0x66F0,
+	0xD4BC, 0x7EA6, 0xD4BD, 0x8D8A, 0xD4BE, 0x8DC3, 0xD4BF, 0x94A5,	0xD4C0, 0x5CB3, 0xD4C1, 0x7CA4, 0xD4C2, 0x6708, 0xD4C3, 0x60A6,
+	0xD4C4, 0x9605, 0xD4C5, 0x8018, 0xD4C6, 0x4E91, 0xD4C7, 0x90E7,	0xD4C8, 0x5300, 0xD4C9, 0x9668, 0xD4CA, 0x5141, 0xD4CB, 0x8FD0,
+	0xD4CC, 0x8574, 0xD4CD, 0x915D, 0xD4CE, 0x6655, 0xD4CF, 0x97F5,	0xD4D0, 0x5B55, 0xD4D1, 0x531D, 0xD4D2, 0x7838, 0xD4D3, 0x6742,
+	0xD4D4, 0x683D, 0xD4D5, 0x54C9, 0xD4D6, 0x707E, 0xD4D7, 0x5BB0,	0xD4D8, 0x8F7D, 0xD4D9, 0x518D, 0xD4DA, 0x5728, 0xD4DB, 0x54B1,
+	0xD4DC, 0x6512, 0xD4DD, 0x6682, 0xD4DE, 0x8D5E, 0xD4DF, 0x8D43,	0xD4E0, 0x810F, 0xD4E1, 0x846C, 0xD4E2, 0x906D, 0xD4E3, 0x7CDF,
+	0xD4E4, 0x51FF, 0xD4E5, 0x85FB, 0xD4E6, 0x67A3, 0xD4E7, 0x65E9,	0xD4E8, 0x6FA1, 0xD4E9, 0x86A4, 0xD4EA, 0x8E81, 0xD4EB, 0x566A,
+	0xD4EC, 0x9020, 0xD4ED, 0x7682, 0xD4EE, 0x7076, 0xD4EF, 0x71E5,	0xD4F0, 0x8D23, 0xD4F1, 0x62E9, 0xD4F2, 0x5219, 0xD4F3, 0x6CFD,
+	0xD4F4, 0x8D3C, 0xD4F5, 0x600E, 0xD4F6, 0x589E, 0xD4F7, 0x618E,	0xD4F8, 0x66FE, 0xD4F9, 0x8D60, 0xD4FA, 0x624E, 0xD4FB, 0x55B3,
+	0xD4FC, 0x6E23, 0xD4FD, 0x672D, 0xD4FE, 0x8F67, 0xD540, 0x8A81,	0xD541, 0x8A82, 0xD542, 0x8A83, 0xD543, 0x8A84, 0xD544, 0x8A85,
+	0xD545, 0x8A86, 0xD546, 0x8A87, 0xD547, 0x8A88, 0xD548, 0x8A8B,	0xD549, 0x8A8C, 0xD54A, 0x8A8D, 0xD54B, 0x8A8E, 0xD54C, 0x8A8F,
+	0xD54D, 0x8A90, 0xD54E, 0x8A91, 0xD54F, 0x8A92, 0xD550, 0x8A94,	0xD551, 0x8A95, 0xD552, 0x8A96, 0xD553, 0x8A97, 0xD554, 0x8A98,
+	0xD555, 0x8A99, 0xD556, 0x8A9A, 0xD557, 0x8A9B, 0xD558, 0x8A9C,	0xD559, 0x8A9D, 0xD55A, 0x8A9E, 0xD55B, 0x8A9F, 0xD55C, 0x8AA0,
+	0xD55D, 0x8AA1, 0xD55E, 0x8AA2, 0xD55F, 0x8AA3, 0xD560, 0x8AA4,	0xD561, 0x8AA5, 0xD562, 0x8AA6, 0xD563, 0x8AA7, 0xD564, 0x8AA8,
+	0xD565, 0x8AA9, 0xD566, 0x8AAA, 0xD567, 0x8AAB, 0xD568, 0x8AAC,	0xD569, 0x8AAD, 0xD56A, 0x8AAE, 0xD56B, 0x8AAF, 0xD56C, 0x8AB0,
+	0xD56D, 0x8AB1, 0xD56E, 0x8AB2, 0xD56F, 0x8AB3, 0xD570, 0x8AB4,	0xD571, 0x8AB5, 0xD572, 0x8AB6, 0xD573, 0x8AB7, 0xD574, 0x8AB8,
+	0xD575, 0x8AB9, 0xD576, 0x8ABA, 0xD577, 0x8ABB, 0xD578, 0x8ABC,	0xD579, 0x8ABD, 0xD57A, 0x8ABE, 0xD57B, 0x8ABF, 0xD57C, 0x8AC0,
+	0xD57D, 0x8AC1, 0xD57E, 0x8AC2, 0xD580, 0x8AC3, 0xD581, 0x8AC4,	0xD582, 0x8AC5, 0xD583, 0x8AC6, 0xD584, 0x8AC7, 0xD585, 0x8AC8,
+	0xD586, 0x8AC9, 0xD587, 0x8ACA, 0xD588, 0x8ACB, 0xD589, 0x8ACC,	0xD58A, 0x8ACD, 0xD58B, 0x8ACE, 0xD58C, 0x8ACF, 0xD58D, 0x8AD0,
+	0xD58E, 0x8AD1, 0xD58F, 0x8AD2, 0xD590, 0x8AD3, 0xD591, 0x8AD4,	0xD592, 0x8AD5, 0xD593, 0x8AD6, 0xD594, 0x8AD7, 0xD595, 0x8AD8,
+	0xD596, 0x8AD9, 0xD597, 0x8ADA, 0xD598, 0x8ADB, 0xD599, 0x8ADC,	0xD59A, 0x8ADD, 0xD59B, 0x8ADE, 0xD59C, 0x8ADF, 0xD59D, 0x8AE0,
+	0xD59E, 0x8AE1, 0xD59F, 0x8AE2, 0xD5A0, 0x8AE3, 0xD5A1, 0x94E1,	0xD5A2, 0x95F8, 0xD5A3, 0x7728, 0xD5A4, 0x6805, 0xD5A5, 0x69A8,
+	0xD5A6, 0x548B, 0xD5A7, 0x4E4D, 0xD5A8, 0x70B8, 0xD5A9, 0x8BC8,	0xD5AA, 0x6458, 0xD5AB, 0x658B, 0xD5AC, 0x5B85, 0xD5AD, 0x7A84,
+	0xD5AE, 0x503A, 0xD5AF, 0x5BE8, 0xD5B0, 0x77BB, 0xD5B1, 0x6BE1,	0xD5B2, 0x8A79, 0xD5B3, 0x7C98, 0xD5B4, 0x6CBE, 0xD5B5, 0x76CF,
+	0xD5B6, 0x65A9, 0xD5B7, 0x8F97, 0xD5B8, 0x5D2D, 0xD5B9, 0x5C55,	0xD5BA, 0x8638, 0xD5BB, 0x6808, 0xD5BC, 0x5360, 0xD5BD, 0x6218,
+	0xD5BE, 0x7AD9, 0xD5BF, 0x6E5B, 0xD5C0, 0x7EFD, 0xD5C1, 0x6A1F,	0xD5C2, 0x7AE0, 0xD5C3, 0x5F70, 0xD5C4, 0x6F33, 0xD5C5, 0x5F20,
+	0xD5C6, 0x638C, 0xD5C7, 0x6DA8, 0xD5C8, 0x6756, 0xD5C9, 0x4E08,	0xD5CA, 0x5E10, 0xD5CB, 0x8D26, 0xD5CC, 0x4ED7, 0xD5CD, 0x80C0,
+	0xD5CE, 0x7634, 0xD5CF, 0x969C, 0xD5D0, 0x62DB, 0xD5D1, 0x662D,	0xD5D2, 0x627E, 0xD5D3, 0x6CBC, 0xD5D4, 0x8D75, 0xD5D5, 0x7167,
+	0xD5D6, 0x7F69, 0xD5D7, 0x5146, 0xD5D8, 0x8087, 0xD5D9, 0x53EC,	0xD5DA, 0x906E, 0xD5DB, 0x6298, 0xD5DC, 0x54F2, 0xD5DD, 0x86F0,
+	0xD5DE, 0x8F99, 0xD5DF, 0x8005, 0xD5E0, 0x9517, 0xD5E1, 0x8517,	0xD5E2, 0x8FD9, 0xD5E3, 0x6D59, 0xD5E4, 0x73CD, 0xD5E5, 0x659F,
+	0xD5E6, 0x771F, 0xD5E7, 0x7504, 0xD5E8, 0x7827, 0xD5E9, 0x81FB,	0xD5EA, 0x8D1E, 0xD5EB, 0x9488, 0xD5EC, 0x4FA6, 0xD5ED, 0x6795,
+	0xD5EE, 0x75B9, 0xD5EF, 0x8BCA, 0xD5F0, 0x9707, 0xD5F1, 0x632F,	0xD5F2, 0x9547, 0xD5F3, 0x9635, 0xD5F4, 0x84B8, 0xD5F5, 0x6323,
+	0xD5F6, 0x7741, 0xD5F7, 0x5F81, 0xD5F8, 0x72F0, 0xD5F9, 0x4E89,	0xD5FA, 0x6014, 0xD5FB, 0x6574, 0xD5FC, 0x62EF, 0xD5FD, 0x6B63,
+	0xD5FE, 0x653F, 0xD640, 0x8AE4, 0xD641, 0x8AE5, 0xD642, 0x8AE6,	0xD643, 0x8AE7, 0xD644, 0x8AE8, 0xD645, 0x8AE9, 0xD646, 0x8AEA,
+	0xD647, 0x8AEB, 0xD648, 0x8AEC, 0xD649, 0x8AED, 0xD64A, 0x8AEE,	0xD64B, 0x8AEF, 0xD64C, 0x8AF0, 0xD64D, 0x8AF1, 0xD64E, 0x8AF2,
+	0xD64F, 0x8AF3, 0xD650, 0x8AF4, 0xD651, 0x8AF5, 0xD652, 0x8AF6,	0xD653, 0x8AF7, 0xD654, 0x8AF8, 0xD655, 0x8AF9, 0xD656, 0x8AFA,
+	0xD657, 0x8AFB, 0xD658, 0x8AFC, 0xD659, 0x8AFD, 0xD65A, 0x8AFE,	0xD65B, 0x8AFF, 0xD65C, 0x8B00, 0xD65D, 0x8B01, 0xD65E, 0x8B02,
+	0xD65F, 0x8B03, 0xD660, 0x8B04, 0xD661, 0x8B05, 0xD662, 0x8B06,	0xD663, 0x8B08, 0xD664, 0x8B09, 0xD665, 0x8B0A, 0xD666, 0x8B0B,
+	0xD667, 0x8B0C, 0xD668, 0x8B0D, 0xD669, 0x8B0E, 0xD66A, 0x8B0F,	0xD66B, 0x8B10, 0xD66C, 0x8B11, 0xD66D, 0x8B12, 0xD66E, 0x8B13,
+	0xD66F, 0x8B14, 0xD670, 0x8B15, 0xD671, 0x8B16, 0xD672, 0x8B17,	0xD673, 0x8B18, 0xD674, 0x8B19, 0xD675, 0x8B1A, 0xD676, 0x8B1B,
+	0xD677, 0x8B1C, 0xD678, 0x8B1D, 0xD679, 0x8B1E, 0xD67A, 0x8B1F,	0xD67B, 0x8B20, 0xD67C, 0x8B21, 0xD67D, 0x8B22, 0xD67E, 0x8B23,
+	0xD680, 0x8B24, 0xD681, 0x8B25, 0xD682, 0x8B27, 0xD683, 0x8B28,	0xD684, 0x8B29, 0xD685, 0x8B2A, 0xD686, 0x8B2B, 0xD687, 0x8B2C,
+	0xD688, 0x8B2D, 0xD689, 0x8B2E, 0xD68A, 0x8B2F, 0xD68B, 0x8B30,	0xD68C, 0x8B31, 0xD68D, 0x8B32, 0xD68E, 0x8B33, 0xD68F, 0x8B34,
+	0xD690, 0x8B35, 0xD691, 0x8B36, 0xD692, 0x8B37, 0xD693, 0x8B38,	0xD694, 0x8B39, 0xD695, 0x8B3A, 0xD696, 0x8B3B, 0xD697, 0x8B3C,
+	0xD698, 0x8B3D, 0xD699, 0x8B3E, 0xD69A, 0x8B3F, 0xD69B, 0x8B40,	0xD69C, 0x8B41, 0xD69D, 0x8B42, 0xD69E, 0x8B43, 0xD69F, 0x8B44,
+	0xD6A0, 0x8B45, 0xD6A1, 0x5E27, 0xD6A2, 0x75C7, 0xD6A3, 0x90D1,	0xD6A4, 0x8BC1, 0xD6A5, 0x829D, 0xD6A6, 0x679D, 0xD6A7, 0x652F,
+	0xD6A8, 0x5431, 0xD6A9, 0x8718, 0xD6AA, 0x77E5, 0xD6AB, 0x80A2,	0xD6AC, 0x8102, 0xD6AD, 0x6C41, 0xD6AE, 0x4E4B, 0xD6AF, 0x7EC7,
+	0xD6B0, 0x804C, 0xD6B1, 0x76F4, 0xD6B2, 0x690D, 0xD6B3, 0x6B96,	0xD6B4, 0x6267, 0xD6B5, 0x503C, 0xD6B6, 0x4F84, 0xD6B7, 0x5740,
+	0xD6B8, 0x6307, 0xD6B9, 0x6B62, 0xD6BA, 0x8DBE, 0xD6BB, 0x53EA,	0xD6BC, 0x65E8, 0xD6BD, 0x7EB8, 0xD6BE, 0x5FD7, 0xD6BF, 0x631A,
+	0xD6C0, 0x63B7, 0xD6C1, 0x81F3, 0xD6C2, 0x81F4, 0xD6C3, 0x7F6E,	0xD6C4, 0x5E1C, 0xD6C5, 0x5CD9, 0xD6C6, 0x5236, 0xD6C7, 0x667A,
+	0xD6C8, 0x79E9, 0xD6C9, 0x7A1A, 0xD6CA, 0x8D28, 0xD6CB, 0x7099,	0xD6CC, 0x75D4, 0xD6CD, 0x6EDE, 0xD6CE, 0x6CBB, 0xD6CF, 0x7A92,
+	0xD6D0, 0x4E2D, 0xD6D1, 0x76C5, 0xD6D2, 0x5FE0, 0xD6D3, 0x949F,	0xD6D4, 0x8877, 0xD6D5, 0x7EC8, 0xD6D6, 0x79CD, 0xD6D7, 0x80BF,
+	0xD6D8, 0x91CD, 0xD6D9, 0x4EF2, 0xD6DA, 0x4F17, 0xD6DB, 0x821F,	0xD6DC, 0x5468, 0xD6DD, 0x5DDE, 0xD6DE, 0x6D32, 0xD6DF, 0x8BCC,
+	0xD6E0, 0x7CA5, 0xD6E1, 0x8F74, 0xD6E2, 0x8098, 0xD6E3, 0x5E1A,	0xD6E4, 0x5492, 0xD6E5, 0x76B1, 0xD6E6, 0x5B99, 0xD6E7, 0x663C,
+	0xD6E8, 0x9AA4, 0xD6E9, 0x73E0, 0xD6EA, 0x682A, 0xD6EB, 0x86DB,	0xD6EC, 0x6731, 0xD6ED, 0x732A, 0xD6EE, 0x8BF8, 0xD6EF, 0x8BDB,
+	0xD6F0, 0x9010, 0xD6F1, 0x7AF9, 0xD6F2, 0x70DB, 0xD6F3, 0x716E,	0xD6F4, 0x62C4, 0xD6F5, 0x77A9, 0xD6F6, 0x5631, 0xD6F7, 0x4E3B,
+	0xD6F8, 0x8457, 0xD6F9, 0x67F1, 0xD6FA, 0x52A9, 0xD6FB, 0x86C0,	0xD6FC, 0x8D2E, 0xD6FD, 0x94F8, 0xD6FE, 0x7B51, 0xD740, 0x8B46,
+	0xD741, 0x8B47, 0xD742, 0x8B48, 0xD743, 0x8B49, 0xD744, 0x8B4A,	0xD745, 0x8B4B, 0xD746, 0x8B4C, 0xD747, 0x8B4D, 0xD748, 0x8B4E,
+	0xD749, 0x8B4F, 0xD74A, 0x8B50, 0xD74B, 0x8B51, 0xD74C, 0x8B52,	0xD74D, 0x8B53, 0xD74E, 0x8B54, 0xD74F, 0x8B55, 0xD750, 0x8B56,
+	0xD751, 0x8B57, 0xD752, 0x8B58, 0xD753, 0x8B59, 0xD754, 0x8B5A,	0xD755, 0x8B5B, 0xD756, 0x8B5C, 0xD757, 0x8B5D, 0xD758, 0x8B5E,
+	0xD759, 0x8B5F, 0xD75A, 0x8B60, 0xD75B, 0x8B61, 0xD75C, 0x8B62,	0xD75D, 0x8B63, 0xD75E, 0x8B64, 0xD75F, 0x8B65, 0xD760, 0x8B67,
+	0xD761, 0x8B68, 0xD762, 0x8B69, 0xD763, 0x8B6A, 0xD764, 0x8B6B,	0xD765, 0x8B6D, 0xD766, 0x8B6E, 0xD767, 0x8B6F, 0xD768, 0x8B70,
+	0xD769, 0x8B71, 0xD76A, 0x8B72, 0xD76B, 0x8B73, 0xD76C, 0x8B74,	0xD76D, 0x8B75, 0xD76E, 0x8B76, 0xD76F, 0x8B77, 0xD770, 0x8B78,
+	0xD771, 0x8B79, 0xD772, 0x8B7A, 0xD773, 0x8B7B, 0xD774, 0x8B7C,	0xD775, 0x8B7D, 0xD776, 0x8B7E, 0xD777, 0x8B7F, 0xD778, 0x8B80,
+	0xD779, 0x8B81, 0xD77A, 0x8B82, 0xD77B, 0x8B83, 0xD77C, 0x8B84,	0xD77D, 0x8B85, 0xD77E, 0x8B86, 0xD780, 0x8B87, 0xD781, 0x8B88,
+	0xD782, 0x8B89, 0xD783, 0x8B8A, 0xD784, 0x8B8B, 0xD785, 0x8B8C,	0xD786, 0x8B8D, 0xD787, 0x8B8E, 0xD788, 0x8B8F, 0xD789, 0x8B90,
+	0xD78A, 0x8B91, 0xD78B, 0x8B92, 0xD78C, 0x8B93, 0xD78D, 0x8B94,	0xD78E, 0x8B95, 0xD78F, 0x8B96, 0xD790, 0x8B97, 0xD791, 0x8B98,
+	0xD792, 0x8B99, 0xD793, 0x8B9A, 0xD794, 0x8B9B, 0xD795, 0x8B9C,	0xD796, 0x8B9D, 0xD797, 0x8B9E, 0xD798, 0x8B9F, 0xD799, 0x8BAC,
+	0xD79A, 0x8BB1, 0xD79B, 0x8BBB, 0xD79C, 0x8BC7, 0xD79D, 0x8BD0,	0xD79E, 0x8BEA, 0xD79F, 0x8C09, 0xD7A0, 0x8C1E, 0xD7A1, 0x4F4F,
+	0xD7A2, 0x6CE8, 0xD7A3, 0x795D, 0xD7A4, 0x9A7B, 0xD7A5, 0x6293,	0xD7A6, 0x722A, 0xD7A7, 0x62FD, 0xD7A8, 0x4E13, 0xD7A9, 0x7816,
+	0xD7AA, 0x8F6C, 0xD7AB, 0x64B0, 0xD7AC, 0x8D5A, 0xD7AD, 0x7BC6,	0xD7AE, 0x6869, 0xD7AF, 0x5E84, 0xD7B0, 0x88C5, 0xD7B1, 0x5986,
+	0xD7B2, 0x649E, 0xD7B3, 0x58EE, 0xD7B4, 0x72B6, 0xD7B5, 0x690E,	0xD7B6, 0x9525, 0xD7B7, 0x8FFD, 0xD7B8, 0x8D58, 0xD7B9, 0x5760,
+	0xD7BA, 0x7F00, 0xD7BB, 0x8C06, 0xD7BC, 0x51C6, 0xD7BD, 0x6349,	0xD7BE, 0x62D9, 0xD7BF, 0x5353, 0xD7C0, 0x684C, 0xD7C1, 0x7422,
+	0xD7C2, 0x8301, 0xD7C3, 0x914C, 0xD7C4, 0x5544, 0xD7C5, 0x7740,	0xD7C6, 0x707C, 0xD7C7, 0x6D4A, 0xD7C8, 0x5179, 0xD7C9, 0x54A8,
+	0xD7CA, 0x8D44, 0xD7CB, 0x59FF, 0xD7CC, 0x6ECB, 0xD7CD, 0x6DC4,	0xD7CE, 0x5B5C, 0xD7CF, 0x7D2B, 0xD7D0, 0x4ED4, 0xD7D1, 0x7C7D,
+	0xD7D2, 0x6ED3, 0xD7D3, 0x5B50, 0xD7D4, 0x81EA, 0xD7D5, 0x6E0D,	0xD7D6, 0x5B57, 0xD7D7, 0x9B03, 0xD7D8, 0x68D5, 0xD7D9, 0x8E2A,
+	0xD7DA, 0x5B97, 0xD7DB, 0x7EFC, 0xD7DC, 0x603B, 0xD7DD, 0x7EB5,	0xD7DE, 0x90B9, 0xD7DF, 0x8D70, 0xD7E0, 0x594F, 0xD7E1, 0x63CD,
+	0xD7E2, 0x79DF, 0xD7E3, 0x8DB3, 0xD7E4, 0x5352, 0xD7E5, 0x65CF,	0xD7E6, 0x7956, 0xD7E7, 0x8BC5, 0xD7E8, 0x963B, 0xD7E9, 0x7EC4,
+	0xD7EA, 0x94BB, 0xD7EB, 0x7E82, 0xD7EC, 0x5634, 0xD7ED, 0x9189,	0xD7EE, 0x6700, 0xD7EF, 0x7F6A, 0xD7F0, 0x5C0A, 0xD7F1, 0x9075,
+	0xD7F2, 0x6628, 0xD7F3, 0x5DE6, 0xD7F4, 0x4F50, 0xD7F5, 0x67DE,	0xD7F6, 0x505A, 0xD7F7, 0x4F5C, 0xD7F8, 0x5750, 0xD7F9, 0x5EA7,
+	0xD840, 0x8C38, 0xD841, 0x8C39, 0xD842, 0x8C3A, 0xD843, 0x8C3B,	0xD844, 0x8C3C, 0xD845, 0x8C3D, 0xD846, 0x8C3E, 0xD847, 0x8C3F,
+	0xD848, 0x8C40, 0xD849, 0x8C42, 0xD84A, 0x8C43, 0xD84B, 0x8C44,	0xD84C, 0x8C45, 0xD84D, 0x8C48, 0xD84E, 0x8C4A, 0xD84F, 0x8C4B,
+	0xD850, 0x8C4D, 0xD851, 0x8C4E, 0xD852, 0x8C4F, 0xD853, 0x8C50,	0xD854, 0x8C51, 0xD855, 0x8C52, 0xD856, 0x8C53, 0xD857, 0x8C54,
+	0xD858, 0x8C56, 0xD859, 0x8C57, 0xD85A, 0x8C58, 0xD85B, 0x8C59,	0xD85C, 0x8C5B, 0xD85D, 0x8C5C, 0xD85E, 0x8C5D, 0xD85F, 0x8C5E,
+	0xD860, 0x8C5F, 0xD861, 0x8C60, 0xD862, 0x8C63, 0xD863, 0x8C64,	0xD864, 0x8C65, 0xD865, 0x8C66, 0xD866, 0x8C67, 0xD867, 0x8C68,
+	0xD868, 0x8C69, 0xD869, 0x8C6C, 0xD86A, 0x8C6D, 0xD86B, 0x8C6E,	0xD86C, 0x8C6F, 0xD86D, 0x8C70, 0xD86E, 0x8C71, 0xD86F, 0x8C72,
+	0xD870, 0x8C74, 0xD871, 0x8C75, 0xD872, 0x8C76, 0xD873, 0x8C77,	0xD874, 0x8C7B, 0xD875, 0x8C7C, 0xD876, 0x8C7D, 0xD877, 0x8C7E,
+	0xD878, 0x8C7F, 0xD879, 0x8C80, 0xD87A, 0x8C81, 0xD87B, 0x8C83,	0xD87C, 0x8C84, 0xD87D, 0x8C86, 0xD87E, 0x8C87, 0xD880, 0x8C88,
+	0xD881, 0x8C8B, 0xD882, 0x8C8D, 0xD883, 0x8C8E, 0xD884, 0x8C8F,	0xD885, 0x8C90, 0xD886, 0x8C91, 0xD887, 0x8C92, 0xD888, 0x8C93,
+	0xD889, 0x8C95, 0xD88A, 0x8C96, 0xD88B, 0x8C97, 0xD88C, 0x8C99,	0xD88D, 0x8C9A, 0xD88E, 0x8C9B, 0xD88F, 0x8C9C, 0xD890, 0x8C9D,
+	0xD891, 0x8C9E, 0xD892, 0x8C9F, 0xD893, 0x8CA0, 0xD894, 0x8CA1,	0xD895, 0x8CA2, 0xD896, 0x8CA3, 0xD897, 0x8CA4, 0xD898, 0x8CA5,
+	0xD899, 0x8CA6, 0xD89A, 0x8CA7, 0xD89B, 0x8CA8, 0xD89C, 0x8CA9,	0xD89D, 0x8CAA, 0xD89E, 0x8CAB, 0xD89F, 0x8CAC, 0xD8A0, 0x8CAD,
+	0xD8A1, 0x4E8D, 0xD8A2, 0x4E0C, 0xD8A3, 0x5140, 0xD8A4, 0x4E10,	0xD8A5, 0x5EFF, 0xD8A6, 0x5345, 0xD8A7, 0x4E15, 0xD8A8, 0x4E98,
+	0xD8A9, 0x4E1E, 0xD8AA, 0x9B32, 0xD8AB, 0x5B6C, 0xD8AC, 0x5669,	0xD8AD, 0x4E28, 0xD8AE, 0x79BA, 0xD8AF, 0x4E3F, 0xD8B0, 0x5315,
+	0xD8B1, 0x4E47, 0xD8B2, 0x592D, 0xD8B3, 0x723B, 0xD8B4, 0x536E,	0xD8B5, 0x6C10, 0xD8B6, 0x56DF, 0xD8B7, 0x80E4, 0xD8B8, 0x9997,
+	0xD8B9, 0x6BD3, 0xD8BA, 0x777E, 0xD8BB, 0x9F17, 0xD8BC, 0x4E36,	0xD8BD, 0x4E9F, 0xD8BE, 0x9F10, 0xD8BF, 0x4E5C, 0xD8C0, 0x4E69,
+	0xD8C1, 0x4E93, 0xD8C2, 0x8288, 0xD8C3, 0x5B5B, 0xD8C4, 0x556C,	0xD8C5, 0x560F, 0xD8C6, 0x4EC4, 0xD8C7, 0x538D, 0xD8C8, 0x539D,
+	0xD8C9, 0x53A3, 0xD8CA, 0x53A5, 0xD8CB, 0x53AE, 0xD8CC, 0x9765,	0xD8CD, 0x8D5D, 0xD8CE, 0x531A, 0xD8CF, 0x53F5, 0xD8D0, 0x5326,
+	0xD8D1, 0x532E, 0xD8D2, 0x533E, 0xD8D3, 0x8D5C, 0xD8D4, 0x5366,	0xD8D5, 0x5363, 0xD8D6, 0x5202, 0xD8D7, 0x5208, 0xD8D8, 0x520E,
+	0xD8D9, 0x522D, 0xD8DA, 0x5233, 0xD8DB, 0x523F, 0xD8DC, 0x5240,	0xD8DD, 0x524C, 0xD8DE, 0x525E, 0xD8DF, 0x5261, 0xD8E0, 0x525C,
+	0xD8E1, 0x84AF, 0xD8E2, 0x527D, 0xD8E3, 0x5282, 0xD8E4, 0x5281,	0xD8E5, 0x5290, 0xD8E6, 0x5293, 0xD8E7, 0x5182, 0xD8E8, 0x7F54,
+	0xD8E9, 0x4EBB, 0xD8EA, 0x4EC3, 0xD8EB, 0x4EC9, 0xD8EC, 0x4EC2,	0xD8ED, 0x4EE8, 0xD8EE, 0x4EE1, 0xD8EF, 0x4EEB, 0xD8F0, 0x4EDE,
+	0xD8F1, 0x4F1B, 0xD8F2, 0x4EF3, 0xD8F3, 0x4F22, 0xD8F4, 0x4F64,	0xD8F5, 0x4EF5, 0xD8F6, 0x4F25, 0xD8F7, 0x4F27, 0xD8F8, 0x4F09,
+	0xD8F9, 0x4F2B, 0xD8FA, 0x4F5E, 0xD8FB, 0x4F67, 0xD8FC, 0x6538,	0xD8FD, 0x4F5A, 0xD8FE, 0x4F5D, 0xD940, 0x8CAE, 0xD941, 0x8CAF,
+	0xD942, 0x8CB0, 0xD943, 0x8CB1, 0xD944, 0x8CB2, 0xD945, 0x8CB3,	0xD946, 0x8CB4, 0xD947, 0x8CB5, 0xD948, 0x8CB6, 0xD949, 0x8CB7,
+	0xD94A, 0x8CB8, 0xD94B, 0x8CB9, 0xD94C, 0x8CBA, 0xD94D, 0x8CBB,	0xD94E, 0x8CBC, 0xD94F, 0x8CBD, 0xD950, 0x8CBE, 0xD951, 0x8CBF,
+	0xD952, 0x8CC0, 0xD953, 0x8CC1, 0xD954, 0x8CC2, 0xD955, 0x8CC3,	0xD956, 0x8CC4, 0xD957, 0x8CC5, 0xD958, 0x8CC6, 0xD959, 0x8CC7,
+	0xD95A, 0x8CC8, 0xD95B, 0x8CC9, 0xD95C, 0x8CCA, 0xD95D, 0x8CCB,	0xD95E, 0x8CCC, 0xD95F, 0x8CCD, 0xD960, 0x8CCE, 0xD961, 0x8CCF,
+	0xD962, 0x8CD0, 0xD963, 0x8CD1, 0xD964, 0x8CD2, 0xD965, 0x8CD3,	0xD966, 0x8CD4, 0xD967, 0x8CD5, 0xD968, 0x8CD6, 0xD969, 0x8CD7,
+	0xD96A, 0x8CD8, 0xD96B, 0x8CD9, 0xD96C, 0x8CDA, 0xD96D, 0x8CDB,	0xD96E, 0x8CDC, 0xD96F, 0x8CDD, 0xD970, 0x8CDE, 0xD971, 0x8CDF,
+	0xD972, 0x8CE0, 0xD973, 0x8CE1, 0xD974, 0x8CE2, 0xD975, 0x8CE3,	0xD976, 0x8CE4, 0xD977, 0x8CE5, 0xD978, 0x8CE6, 0xD979, 0x8CE7,
+	0xD97A, 0x8CE8, 0xD97B, 0x8CE9, 0xD97C, 0x8CEA, 0xD97D, 0x8CEB,	0xD97E, 0x8CEC, 0xD980, 0x8CED, 0xD981, 0x8CEE, 0xD982, 0x8CEF,
+	0xD983, 0x8CF0, 0xD984, 0x8CF1, 0xD985, 0x8CF2, 0xD986, 0x8CF3,	0xD987, 0x8CF4, 0xD988, 0x8CF5, 0xD989, 0x8CF6, 0xD98A, 0x8CF7,
+	0xD98B, 0x8CF8, 0xD98C, 0x8CF9, 0xD98D, 0x8CFA, 0xD98E, 0x8CFB,	0xD98F, 0x8CFC, 0xD990, 0x8CFD, 0xD991, 0x8CFE, 0xD992, 0x8CFF,
+	0xD993, 0x8D00, 0xD994, 0x8D01, 0xD995, 0x8D02, 0xD996, 0x8D03,	0xD997, 0x8D04, 0xD998, 0x8D05, 0xD999, 0x8D06, 0xD99A, 0x8D07,
+	0xD99B, 0x8D08, 0xD99C, 0x8D09, 0xD99D, 0x8D0A, 0xD99E, 0x8D0B,	0xD99F, 0x8D0C, 0xD9A0, 0x8D0D, 0xD9A1, 0x4F5F, 0xD9A2, 0x4F57,
+	0xD9A3, 0x4F32, 0xD9A4, 0x4F3D, 0xD9A5, 0x4F76, 0xD9A6, 0x4F74,	0xD9A7, 0x4F91, 0xD9A8, 0x4F89, 0xD9A9, 0x4F83, 0xD9AA, 0x4F8F,
+	0xD9AB, 0x4F7E, 0xD9AC, 0x4F7B, 0xD9AD, 0x4FAA, 0xD9AE, 0x4F7C,	0xD9AF, 0x4FAC, 0xD9B0, 0x4F94, 0xD9B1, 0x4FE6, 0xD9B2, 0x4FE8,
+	0xD9B3, 0x4FEA, 0xD9B4, 0x4FC5, 0xD9B5, 0x4FDA, 0xD9B6, 0x4FE3,	0xD9B7, 0x4FDC, 0xD9B8, 0x4FD1, 0xD9B9, 0x4FDF, 0xD9BA, 0x4FF8,
+	0xD9BB, 0x5029, 0xD9BC, 0x504C, 0xD9BD, 0x4FF3, 0xD9BE, 0x502C,	0xD9BF, 0x500F, 0xD9C0, 0x502E, 0xD9C1, 0x502D, 0xD9C2, 0x4FFE,
+	0xD9C3, 0x501C, 0xD9C4, 0x500C, 0xD9C5, 0x5025, 0xD9C6, 0x5028,	0xD9C7, 0x507E, 0xD9C8, 0x5043, 0xD9C9, 0x5055, 0xD9CA, 0x5048,
+	0xD9CB, 0x504E, 0xD9CC, 0x506C, 0xD9CD, 0x507B, 0xD9CE, 0x50A5,	0xD9CF, 0x50A7, 0xD9D0, 0x50A9, 0xD9D1, 0x50BA, 0xD9D2, 0x50D6,
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+	0xE0F1, 0x56EB, 0xE0F2, 0x56F9, 0xE0F3, 0x56FF, 0xE0F4, 0x5704,	0xE0F5, 0x570A, 0xE0F6, 0x5709, 0xE0F7, 0x571C, 0xE0F8, 0x5E0F,
+	0xE0F9, 0x5E19, 0xE0FA, 0x5E14, 0xE0FB, 0x5E11, 0xE0FC, 0x5E31,	0xE0FD, 0x5E3B, 0xE0FE, 0x5E3C, 0xE140, 0x9145, 0xE141, 0x9147,
+	0xE142, 0x9148, 0xE143, 0x9151, 0xE144, 0x9153, 0xE145, 0x9154,	0xE146, 0x9155, 0xE147, 0x9156, 0xE148, 0x9158, 0xE149, 0x9159,
+	0xE14A, 0x915B, 0xE14B, 0x915C, 0xE14C, 0x915F, 0xE14D, 0x9160,	0xE14E, 0x9166, 0xE14F, 0x9167, 0xE150, 0x9168, 0xE151, 0x916B,
+	0xE152, 0x916D, 0xE153, 0x9173, 0xE154, 0x917A, 0xE155, 0x917B,	0xE156, 0x917C, 0xE157, 0x9180, 0xE158, 0x9181, 0xE159, 0x9182,
+	0xE15A, 0x9183, 0xE15B, 0x9184, 0xE15C, 0x9186, 0xE15D, 0x9188,	0xE15E, 0x918A, 0xE15F, 0x918E, 0xE160, 0x918F, 0xE161, 0x9193,
+	0xE162, 0x9194, 0xE163, 0x9195, 0xE164, 0x9196, 0xE165, 0x9197,	0xE166, 0x9198, 0xE167, 0x9199, 0xE168, 0x919C, 0xE169, 0x919D,
+	0xE16A, 0x919E, 0xE16B, 0x919F, 0xE16C, 0x91A0, 0xE16D, 0x91A1,	0xE16E, 0x91A4, 0xE16F, 0x91A5, 0xE170, 0x91A6, 0xE171, 0x91A7,
+	0xE172, 0x91A8, 0xE173, 0x91A9, 0xE174, 0x91AB, 0xE175, 0x91AC,	0xE176, 0x91B0, 0xE177, 0x91B1, 0xE178, 0x91B2, 0xE179, 0x91B3,
+	0xE17A, 0x91B6, 0xE17B, 0x91B7, 0xE17C, 0x91B8, 0xE17D, 0x91B9,	0xE17E, 0x91BB, 0xE180, 0x91BC, 0xE181, 0x91BD, 0xE182, 0x91BE,
+	0xE183, 0x91BF, 0xE184, 0x91C0, 0xE185, 0x91C1, 0xE186, 0x91C2,	0xE187, 0x91C3, 0xE188, 0x91C4, 0xE189, 0x91C5, 0xE18A, 0x91C6,
+	0xE18B, 0x91C8, 0xE18C, 0x91CB, 0xE18D, 0x91D0, 0xE18E, 0x91D2,	0xE18F, 0x91D3, 0xE190, 0x91D4, 0xE191, 0x91D5, 0xE192, 0x91D6,
+	0xE193, 0x91D7, 0xE194, 0x91D8, 0xE195, 0x91D9, 0xE196, 0x91DA,	0xE197, 0x91DB, 0xE198, 0x91DD, 0xE199, 0x91DE, 0xE19A, 0x91DF,
+	0xE19B, 0x91E0, 0xE19C, 0x91E1, 0xE19D, 0x91E2, 0xE19E, 0x91E3,	0xE19F, 0x91E4, 0xE1A0, 0x91E5, 0xE1A1, 0x5E37, 0xE1A2, 0x5E44,
+	0xE1A3, 0x5E54, 0xE1A4, 0x5E5B, 0xE1A5, 0x5E5E, 0xE1A6, 0x5E61,	0xE1A7, 0x5C8C, 0xE1A8, 0x5C7A, 0xE1A9, 0x5C8D, 0xE1AA, 0x5C90,
+	0xE1AB, 0x5C96, 0xE1AC, 0x5C88, 0xE1AD, 0x5C98, 0xE1AE, 0x5C99,	0xE1AF, 0x5C91, 0xE1B0, 0x5C9A, 0xE1B1, 0x5C9C, 0xE1B2, 0x5CB5,
+	0xE1B3, 0x5CA2, 0xE1B4, 0x5CBD, 0xE1B5, 0x5CAC, 0xE1B6, 0x5CAB,	0xE1B7, 0x5CB1, 0xE1B8, 0x5CA3, 0xE1B9, 0x5CC1, 0xE1BA, 0x5CB7,
+	0xE1BB, 0x5CC4, 0xE1BC, 0x5CD2, 0xE1BD, 0x5CE4, 0xE1BE, 0x5CCB,	0xE1BF, 0x5CE5, 0xE1C0, 0x5D02, 0xE1C1, 0x5D03, 0xE1C2, 0x5D27,
+	0xE1C3, 0x5D26, 0xE1C4, 0x5D2E, 0xE1C5, 0x5D24, 0xE1C6, 0x5D1E,	0xE1C7, 0x5D06, 0xE1C8, 0x5D1B, 0xE1C9, 0x5D58, 0xE1CA, 0x5D3E,
+	0xE1CB, 0x5D34, 0xE1CC, 0x5D3D, 0xE1CD, 0x5D6C, 0xE1CE, 0x5D5B,	0xE1CF, 0x5D6F, 0xE1D0, 0x5D5D, 0xE1D1, 0x5D6B, 0xE1D2, 0x5D4B,
+	0xE1D3, 0x5D4A, 0xE1D4, 0x5D69, 0xE1D5, 0x5D74, 0xE1D6, 0x5D82,	0xE1D7, 0x5D99, 0xE1D8, 0x5D9D, 0xE1D9, 0x8C73, 0xE1DA, 0x5DB7,
+	0xE1DB, 0x5DC5, 0xE1DC, 0x5F73, 0xE1DD, 0x5F77, 0xE1DE, 0x5F82,	0xE1DF, 0x5F87, 0xE1E0, 0x5F89, 0xE1E1, 0x5F8C, 0xE1E2, 0x5F95,
+	0xE1E3, 0x5F99, 0xE1E4, 0x5F9C, 0xE1E5, 0x5FA8, 0xE1E6, 0x5FAD,	0xE1E7, 0x5FB5, 0xE1E8, 0x5FBC, 0xE1E9, 0x8862, 0xE1EA, 0x5F61,
+	0xE1EB, 0x72AD, 0xE1EC, 0x72B0, 0xE1ED, 0x72B4, 0xE1EE, 0x72B7,	0xE1EF, 0x72B8, 0xE1F0, 0x72C3, 0xE1F1, 0x72C1, 0xE1F2, 0x72CE,
+	0xE1F3, 0x72CD, 0xE1F4, 0x72D2, 0xE1F5, 0x72E8, 0xE1F6, 0x72EF,	0xE1F7, 0x72E9, 0xE1F8, 0x72F2, 0xE1F9, 0x72F4, 0xE1FA, 0x72F7,
+	0xE1FB, 0x7301, 0xE1FC, 0x72F3, 0xE1FD, 0x7303, 0xE1FE, 0x72FA,	0xE240, 0x91E6, 0xE241, 0x91E7, 0xE242, 0x91E8, 0xE243, 0x91E9,
+	0xE244, 0x91EA, 0xE245, 0x91EB, 0xE246, 0x91EC, 0xE247, 0x91ED,	0xE248, 0x91EE, 0xE249, 0x91EF, 0xE24A, 0x91F0, 0xE24B, 0x91F1,
+	0xE24C, 0x91F2, 0xE24D, 0x91F3, 0xE24E, 0x91F4, 0xE24F, 0x91F5,	0xE250, 0x91F6, 0xE251, 0x91F7, 0xE252, 0x91F8, 0xE253, 0x91F9,
+	0xE254, 0x91FA, 0xE255, 0x91FB, 0xE256, 0x91FC, 0xE257, 0x91FD,	0xE258, 0x91FE, 0xE259, 0x91FF, 0xE25A, 0x9200, 0xE25B, 0x9201,
+	0xE25C, 0x9202, 0xE25D, 0x9203, 0xE25E, 0x9204, 0xE25F, 0x9205,	0xE260, 0x9206, 0xE261, 0x9207, 0xE262, 0x9208, 0xE263, 0x9209,
+	0xE264, 0x920A, 0xE265, 0x920B, 0xE266, 0x920C, 0xE267, 0x920D,	0xE268, 0x920E, 0xE269, 0x920F, 0xE26A, 0x9210, 0xE26B, 0x9211,
+	0xE26C, 0x9212, 0xE26D, 0x9213, 0xE26E, 0x9214, 0xE26F, 0x9215,	0xE270, 0x9216, 0xE271, 0x9217, 0xE272, 0x9218, 0xE273, 0x9219,
+	0xE274, 0x921A, 0xE275, 0x921B, 0xE276, 0x921C, 0xE277, 0x921D,	0xE278, 0x921E, 0xE279, 0x921F, 0xE27A, 0x9220, 0xE27B, 0x9221,
+	0xE27C, 0x9222, 0xE27D, 0x9223, 0xE27E, 0x9224, 0xE280, 0x9225,	0xE281, 0x9226, 0xE282, 0x9227, 0xE283, 0x9228, 0xE284, 0x9229,
+	0xE285, 0x922A, 0xE286, 0x922B, 0xE287, 0x922C, 0xE288, 0x922D,	0xE289, 0x922E, 0xE28A, 0x922F, 0xE28B, 0x9230, 0xE28C, 0x9231,
+	0xE28D, 0x9232, 0xE28E, 0x9233, 0xE28F, 0x9234, 0xE290, 0x9235,	0xE291, 0x9236, 0xE292, 0x9237, 0xE293, 0x9238, 0xE294, 0x9239,
+	0xE295, 0x923A, 0xE296, 0x923B, 0xE297, 0x923C, 0xE298, 0x923D,	0xE299, 0x923E, 0xE29A, 0x923F, 0xE29B, 0x9240, 0xE29C, 0x9241,
+	0xE29D, 0x9242, 0xE29E, 0x9243, 0xE29F, 0x9244, 0xE2A0, 0x9245,	0xE2A1, 0x72FB, 0xE2A2, 0x7317, 0xE2A3, 0x7313, 0xE2A4, 0x7321,
+	0xE2A5, 0x730A, 0xE2A6, 0x731E, 0xE2A7, 0x731D, 0xE2A8, 0x7315,	0xE2A9, 0x7322, 0xE2AA, 0x7339, 0xE2AB, 0x7325, 0xE2AC, 0x732C,
+	0xE2AD, 0x7338, 0xE2AE, 0x7331, 0xE2AF, 0x7350, 0xE2B0, 0x734D,	0xE2B1, 0x7357, 0xE2B2, 0x7360, 0xE2B3, 0x736C, 0xE2B4, 0x736F,
+	0xE2B5, 0x737E, 0xE2B6, 0x821B, 0xE2B7, 0x5925, 0xE2B8, 0x98E7,	0xE2B9, 0x5924, 0xE2BA, 0x5902, 0xE2BB, 0x9963, 0xE2BC, 0x9967,
+	0xE2BD, 0x9968, 0xE2BE, 0x9969, 0xE2BF, 0x996A, 0xE2C0, 0x996B,	0xE2C1, 0x996C, 0xE2C2, 0x9974, 0xE2C3, 0x9977, 0xE2C4, 0x997D,
+	0xE2C5, 0x9980, 0xE2C6, 0x9984, 0xE2C7, 0x9987, 0xE2C8, 0x998A,	0xE2C9, 0x998D, 0xE2CA, 0x9990, 0xE2CB, 0x9991, 0xE2CC, 0x9993,
+	0xE2CD, 0x9994, 0xE2CE, 0x9995, 0xE2CF, 0x5E80, 0xE2D0, 0x5E91,	0xE2D1, 0x5E8B, 0xE2D2, 0x5E96, 0xE2D3, 0x5EA5, 0xE2D4, 0x5EA0,
+	0xE2D5, 0x5EB9, 0xE2D6, 0x5EB5, 0xE2D7, 0x5EBE, 0xE2D8, 0x5EB3,	0xE2D9, 0x8D53, 0xE2DA, 0x5ED2, 0xE2DB, 0x5ED1, 0xE2DC, 0x5EDB,
+	0xE2DD, 0x5EE8, 0xE2DE, 0x5EEA, 0xE2DF, 0x81BA, 0xE2E0, 0x5FC4,	0xE2E1, 0x5FC9, 0xE2E2, 0x5FD6, 0xE2E3, 0x5FCF, 0xE2E4, 0x6003,
+	0xE2E5, 0x5FEE, 0xE2E6, 0x6004, 0xE2E7, 0x5FE1, 0xE2E8, 0x5FE4,	0xE2E9, 0x5FFE, 0xE2EA, 0x6005, 0xE2EB, 0x6006, 0xE2EC, 0x5FEA,
+	0xE2ED, 0x5FED, 0xE2EE, 0x5FF8, 0xE2EF, 0x6019, 0xE2F0, 0x6035,	0xE2F1, 0x6026, 0xE2F2, 0x601B, 0xE2F3, 0x600F, 0xE2F4, 0x600D,
+	0xE2F5, 0x6029, 0xE2F6, 0x602B, 0xE2F7, 0x600A, 0xE2F8, 0x603F,	0xE2F9, 0x6021, 0xE2FA, 0x6078, 0xE2FB, 0x6079, 0xE2FC, 0x607B,
+	0xE2FD, 0x607A, 0xE2FE, 0x6042, 0xE340, 0x9246, 0xE341, 0x9247,	0xE342, 0x9248, 0xE343, 0x9249, 0xE344, 0x924A, 0xE345, 0x924B,
+	0xE346, 0x924C, 0xE347, 0x924D, 0xE348, 0x924E, 0xE349, 0x924F,	0xE34A, 0x9250, 0xE34B, 0x9251, 0xE34C, 0x9252, 0xE34D, 0x9253,
+	0xE34E, 0x9254, 0xE34F, 0x9255, 0xE350, 0x9256, 0xE351, 0x9257,	0xE352, 0x9258, 0xE353, 0x9259, 0xE354, 0x925A, 0xE355, 0x925B,
+	0xE356, 0x925C, 0xE357, 0x925D, 0xE358, 0x925E, 0xE359, 0x925F,	0xE35A, 0x9260, 0xE35B, 0x9261, 0xE35C, 0x9262, 0xE35D, 0x9263,
+	0xE35E, 0x9264, 0xE35F, 0x9265, 0xE360, 0x9266, 0xE361, 0x9267,	0xE362, 0x9268, 0xE363, 0x9269, 0xE364, 0x926A, 0xE365, 0x926B,
+	0xE366, 0x926C, 0xE367, 0x926D, 0xE368, 0x926E, 0xE369, 0x926F,	0xE36A, 0x9270, 0xE36B, 0x9271, 0xE36C, 0x9272, 0xE36D, 0x9273,
+	0xE36E, 0x9275, 0xE36F, 0x9276, 0xE370, 0x9277, 0xE371, 0x9278,	0xE372, 0x9279, 0xE373, 0x927A, 0xE374, 0x927B, 0xE375, 0x927C,
+	0xE376, 0x927D, 0xE377, 0x927E, 0xE378, 0x927F, 0xE379, 0x9280,	0xE37A, 0x9281, 0xE37B, 0x9282, 0xE37C, 0x9283, 0xE37D, 0x9284,
+	0xE37E, 0x9285, 0xE380, 0x9286, 0xE381, 0x9287, 0xE382, 0x9288,	0xE383, 0x9289, 0xE384, 0x928A, 0xE385, 0x928B, 0xE386, 0x928C,
+	0xE387, 0x928D, 0xE388, 0x928F, 0xE389, 0x9290, 0xE38A, 0x9291,	0xE38B, 0x9292, 0xE38C, 0x9293, 0xE38D, 0x9294, 0xE38E, 0x9295,
+	0xE38F, 0x9296, 0xE390, 0x9297, 0xE391, 0x9298, 0xE392, 0x9299,	0xE393, 0x929A, 0xE394, 0x929B, 0xE395, 0x929C, 0xE396, 0x929D,
+	0xE397, 0x929E, 0xE398, 0x929F, 0xE399, 0x92A0, 0xE39A, 0x92A1,	0xE39B, 0x92A2, 0xE39C, 0x92A3, 0xE39D, 0x92A4, 0xE39E, 0x92A5,
+	0xE39F, 0x92A6, 0xE3A0, 0x92A7, 0xE3A1, 0x606A, 0xE3A2, 0x607D,	0xE3A3, 0x6096, 0xE3A4, 0x609A, 0xE3A5, 0x60AD, 0xE3A6, 0x609D,
+	0xE3A7, 0x6083, 0xE3A8, 0x6092, 0xE3A9, 0x608C, 0xE3AA, 0x609B,	0xE3AB, 0x60EC, 0xE3AC, 0x60BB, 0xE3AD, 0x60B1, 0xE3AE, 0x60DD,
+	0xE3AF, 0x60D8, 0xE3B0, 0x60C6, 0xE3B1, 0x60DA, 0xE3B2, 0x60B4,	0xE3B3, 0x6120, 0xE3B4, 0x6126, 0xE3B5, 0x6115, 0xE3B6, 0x6123,
+	0xE3B7, 0x60F4, 0xE3B8, 0x6100, 0xE3B9, 0x610E, 0xE3BA, 0x612B,	0xE3BB, 0x614A, 0xE3BC, 0x6175, 0xE3BD, 0x61AC, 0xE3BE, 0x6194,
+	0xE3BF, 0x61A7, 0xE3C0, 0x61B7, 0xE3C1, 0x61D4, 0xE3C2, 0x61F5,	0xE3C3, 0x5FDD, 0xE3C4, 0x96B3, 0xE3C5, 0x95E9, 0xE3C6, 0x95EB,
+	0xE3C7, 0x95F1, 0xE3C8, 0x95F3, 0xE3C9, 0x95F5, 0xE3CA, 0x95F6,	0xE3CB, 0x95FC, 0xE3CC, 0x95FE, 0xE3CD, 0x9603, 0xE3CE, 0x9604,
+	0xE3CF, 0x9606, 0xE3D0, 0x9608, 0xE3D1, 0x960A, 0xE3D2, 0x960B,	0xE3D3, 0x960C, 0xE3D4, 0x960D, 0xE3D5, 0x960F, 0xE3D6, 0x9612,
+	0xE3D7, 0x9615, 0xE3D8, 0x9616, 0xE3D9, 0x9617, 0xE3DA, 0x9619,	0xE3DB, 0x961A, 0xE3DC, 0x4E2C, 0xE3DD, 0x723F, 0xE3DE, 0x6215,
+	0xE3DF, 0x6C35, 0xE3E0, 0x6C54, 0xE3E1, 0x6C5C, 0xE3E2, 0x6C4A,	0xE3E3, 0x6CA3, 0xE3E4, 0x6C85, 0xE3E5, 0x6C90, 0xE3E6, 0x6C94,
+	0xE3E7, 0x6C8C, 0xE3E8, 0x6C68, 0xE3E9, 0x6C69, 0xE3EA, 0x6C74,	0xE3EB, 0x6C76, 0xE3EC, 0x6C86, 0xE3ED, 0x6CA9, 0xE3EE, 0x6CD0,
+	0xE3EF, 0x6CD4, 0xE3F0, 0x6CAD, 0xE3F1, 0x6CF7, 0xE3F2, 0x6CF8,	0xE3F3, 0x6CF1, 0xE3F4, 0x6CD7, 0xE3F5, 0x6CB2, 0xE3F6, 0x6CE0,
+	0xE3F7, 0x6CD6, 0xE3F8, 0x6CFA, 0xE3F9, 0x6CEB, 0xE3FA, 0x6CEE,	0xE3FB, 0x6CB1, 0xE3FC, 0x6CD3, 0xE3FD, 0x6CEF, 0xE3FE, 0x6CFE,
+	0xE440, 0x92A8, 0xE441, 0x92A9, 0xE442, 0x92AA, 0xE443, 0x92AB,	0xE444, 0x92AC, 0xE445, 0x92AD, 0xE446, 0x92AF, 0xE447, 0x92B0,
+	0xE448, 0x92B1, 0xE449, 0x92B2, 0xE44A, 0x92B3, 0xE44B, 0x92B4,	0xE44C, 0x92B5, 0xE44D, 0x92B6, 0xE44E, 0x92B7, 0xE44F, 0x92B8,
+	0xE450, 0x92B9, 0xE451, 0x92BA, 0xE452, 0x92BB, 0xE453, 0x92BC,	0xE454, 0x92BD, 0xE455, 0x92BE, 0xE456, 0x92BF, 0xE457, 0x92C0,
+	0xE458, 0x92C1, 0xE459, 0x92C2, 0xE45A, 0x92C3, 0xE45B, 0x92C4,	0xE45C, 0x92C5, 0xE45D, 0x92C6, 0xE45E, 0x92C7, 0xE45F, 0x92C9,
+	0xE460, 0x92CA, 0xE461, 0x92CB, 0xE462, 0x92CC, 0xE463, 0x92CD,	0xE464, 0x92CE, 0xE465, 0x92CF, 0xE466, 0x92D0, 0xE467, 0x92D1,
+	0xE468, 0x92D2, 0xE469, 0x92D3, 0xE46A, 0x92D4, 0xE46B, 0x92D5,	0xE46C, 0x92D6, 0xE46D, 0x92D7, 0xE46E, 0x92D8, 0xE46F, 0x92D9,
+	0xE470, 0x92DA, 0xE471, 0x92DB, 0xE472, 0x92DC, 0xE473, 0x92DD,	0xE474, 0x92DE, 0xE475, 0x92DF, 0xE476, 0x92E0, 0xE477, 0x92E1,
+	0xE478, 0x92E2, 0xE479, 0x92E3, 0xE47A, 0x92E4, 0xE47B, 0x92E5,	0xE47C, 0x92E6, 0xE47D, 0x92E7, 0xE47E, 0x92E8, 0xE480, 0x92E9,
+	0xE481, 0x92EA, 0xE482, 0x92EB, 0xE483, 0x92EC, 0xE484, 0x92ED,	0xE485, 0x92EE, 0xE486, 0x92EF, 0xE487, 0x92F0, 0xE488, 0x92F1,
+	0xE489, 0x92F2, 0xE48A, 0x92F3, 0xE48B, 0x92F4, 0xE48C, 0x92F5,	0xE48D, 0x92F6, 0xE48E, 0x92F7, 0xE48F, 0x92F8, 0xE490, 0x92F9,
+	0xE491, 0x92FA, 0xE492, 0x92FB, 0xE493, 0x92FC, 0xE494, 0x92FD,	0xE495, 0x92FE, 0xE496, 0x92FF, 0xE497, 0x9300, 0xE498, 0x9301,
+	0xE499, 0x9302, 0xE49A, 0x9303, 0xE49B, 0x9304, 0xE49C, 0x9305,	0xE49D, 0x9306, 0xE49E, 0x9307, 0xE49F, 0x9308, 0xE4A0, 0x9309,
+	0xE4A1, 0x6D39, 0xE4A2, 0x6D27, 0xE4A3, 0x6D0C, 0xE4A4, 0x6D43,	0xE4A5, 0x6D48, 0xE4A6, 0x6D07, 0xE4A7, 0x6D04, 0xE4A8, 0x6D19,
+	0xE4A9, 0x6D0E, 0xE4AA, 0x6D2B, 0xE4AB, 0x6D4D, 0xE4AC, 0x6D2E,	0xE4AD, 0x6D35, 0xE4AE, 0x6D1A, 0xE4AF, 0x6D4F, 0xE4B0, 0x6D52,
+	0xE4B1, 0x6D54, 0xE4B2, 0x6D33, 0xE4B3, 0x6D91, 0xE4B4, 0x6D6F,	0xE4B5, 0x6D9E, 0xE4B6, 0x6DA0, 0xE4B7, 0x6D5E, 0xE4B8, 0x6D93,
+	0xE4B9, 0x6D94, 0xE4BA, 0x6D5C, 0xE4BB, 0x6D60, 0xE4BC, 0x6D7C,	0xE4BD, 0x6D63, 0xE4BE, 0x6E1A, 0xE4BF, 0x6DC7, 0xE4C0, 0x6DC5,
+	0xE4C1, 0x6DDE, 0xE4C2, 0x6E0E, 0xE4C3, 0x6DBF, 0xE4C4, 0x6DE0,	0xE4C5, 0x6E11, 0xE4C6, 0x6DE6, 0xE4C7, 0x6DDD, 0xE4C8, 0x6DD9,
+	0xE4C9, 0x6E16, 0xE4CA, 0x6DAB, 0xE4CB, 0x6E0C, 0xE4CC, 0x6DAE,	0xE4CD, 0x6E2B, 0xE4CE, 0x6E6E, 0xE4CF, 0x6E4E, 0xE4D0, 0x6E6B,
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+	0xE4E9, 0x6E9F, 0xE4EA, 0x6F62, 0xE4EB, 0x6F46, 0xE4EC, 0x6F47,	0xE4ED, 0x6F24, 0xE4EE, 0x6F15, 0xE4EF, 0x6EF9, 0xE4F0, 0x6F2F,
+	0xE4F1, 0x6F36, 0xE4F2, 0x6F4B, 0xE4F3, 0x6F74, 0xE4F4, 0x6F2A,	0xE4F5, 0x6F09, 0xE4F6, 0x6F29, 0xE4F7, 0x6F89, 0xE4F8, 0x6F8D,
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+	0xE5AB, 0x701A, 0xE5AC, 0x7023, 0xE5AD, 0x701B, 0xE5AE, 0x7039,	0xE5AF, 0x7035, 0xE5B0, 0x704F, 0xE5B1, 0x705E, 0xE5B2, 0x5B80,
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+	0xE5BB, 0x5BE4, 0xE5BC, 0x5BEE, 0xE5BD, 0x8930, 0xE5BE, 0x5BF0,	0xE5BF, 0x8E47, 0xE5C0, 0x8B07, 0xE5C1, 0x8FB6, 0xE5C2, 0x8FD3,
+	0xE5C3, 0x8FD5, 0xE5C4, 0x8FE5, 0xE5C5, 0x8FEE, 0xE5C6, 0x8FE4,	0xE5C7, 0x8FE9, 0xE5C8, 0x8FE6, 0xE5C9, 0x8FF3, 0xE5CA, 0x8FE8,
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+	0xE7CF, 0x7F26, 0xE7D0, 0x7F27, 0xE7D1, 0x7F2A, 0xE7D2, 0x7F2B,	0xE7D3, 0x7F2C, 0xE7D4, 0x7F2D, 0xE7D5, 0x7F2F, 0xE7D6, 0x7F30,
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+	0xE7F7, 0x742A, 0xE7F8, 0x745B, 0xE7F9, 0x7426, 0xE7FA, 0x7425,	0xE7FB, 0x7428, 0xE7FC, 0x7430, 0xE7FD, 0x742E, 0xE7FE, 0x742C,
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+	0xE848, 0x9437, 0xE849, 0x9438, 0xE84A, 0x9439, 0xE84B, 0x943A,	0xE84C, 0x943B, 0xE84D, 0x943C, 0xE84E, 0x943D, 0xE84F, 0x943F,
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+	0xEFCF, 0x9535, 0xEFD0, 0x9544, 0xEFD1, 0x9545, 0xEFD2, 0x9546,	0xEFD3, 0x9549, 0xEFD4, 0x954C, 0xEFD5, 0x954E, 0xEFD6, 0x954F,
+	0xEFD7, 0x9552, 0xEFD8, 0x9553, 0xEFD9, 0x9554, 0xEFDA, 0x9556,	0xEFDB, 0x9557, 0xEFDC, 0x9558, 0xEFDD, 0x9559, 0xEFDE, 0x955B,
+	0xEFDF, 0x955E, 0xEFE0, 0x955F, 0xEFE1, 0x955D, 0xEFE2, 0x9561,	0xEFE3, 0x9562, 0xEFE4, 0x9564, 0xEFE5, 0x9565, 0xEFE6, 0x9566,
+	0xEFE7, 0x9567, 0xEFE8, 0x9568, 0xEFE9, 0x9569, 0xEFEA, 0x956A,	0xEFEB, 0x956B, 0xEFEC, 0x956C, 0xEFED, 0x956F, 0xEFEE, 0x9571,
+	0xEFEF, 0x9572, 0xEFF0, 0x9573, 0xEFF1, 0x953A, 0xEFF2, 0x77E7,	0xEFF3, 0x77EC, 0xEFF4, 0x96C9, 0xEFF5, 0x79D5, 0xEFF6, 0x79ED,
+	0xEFF7, 0x79E3, 0xEFF8, 0x79EB, 0xEFF9, 0x7A06, 0xEFFA, 0x5D47,	0xEFFB, 0x7A03, 0xEFFC, 0x7A02, 0xEFFD, 0x7A1E, 0xEFFE, 0x7A14,
+	0xF040, 0x9908, 0xF041, 0x9909, 0xF042, 0x990A, 0xF043, 0x990B,	0xF044, 0x990C, 0xF045, 0x990E, 0xF046, 0x990F, 0xF047, 0x9911,
+	0xF048, 0x9912, 0xF049, 0x9913, 0xF04A, 0x9914, 0xF04B, 0x9915,	0xF04C, 0x9916, 0xF04D, 0x9917, 0xF04E, 0x9918, 0xF04F, 0x9919,
+	0xF050, 0x991A, 0xF051, 0x991B, 0xF052, 0x991C, 0xF053, 0x991D,	0xF054, 0x991E, 0xF055, 0x991F, 0xF056, 0x9920, 0xF057, 0x9921,
+	0xF058, 0x9922, 0xF059, 0x9923, 0xF05A, 0x9924, 0xF05B, 0x9925,	0xF05C, 0x9926, 0xF05D, 0x9927, 0xF05E, 0x9928, 0xF05F, 0x9929,
+	0xF060, 0x992A, 0xF061, 0x992B, 0xF062, 0x992C, 0xF063, 0x992D,	0xF064, 0x992F, 0xF065, 0x9930, 0xF066, 0x9931, 0xF067, 0x9932,
+	0xF068, 0x9933, 0xF069, 0x9934, 0xF06A, 0x9935, 0xF06B, 0x9936,	0xF06C, 0x9937, 0xF06D, 0x9938, 0xF06E, 0x9939, 0xF06F, 0x993A,
+	0xF070, 0x993B, 0xF071, 0x993C, 0xF072, 0x993D, 0xF073, 0x993E,	0xF074, 0x993F, 0xF075, 0x9940, 0xF076, 0x9941, 0xF077, 0x9942,
+	0xF078, 0x9943, 0xF079, 0x9944, 0xF07A, 0x9945, 0xF07B, 0x9946,	0xF07C, 0x9947, 0xF07D, 0x9948, 0xF07E, 0x9949, 0xF080, 0x994A,
+	0xF081, 0x994B, 0xF082, 0x994C, 0xF083, 0x994D, 0xF084, 0x994E,	0xF085, 0x994F, 0xF086, 0x9950, 0xF087, 0x9951, 0xF088, 0x9952,
+	0xF089, 0x9953, 0xF08A, 0x9956, 0xF08B, 0x9957, 0xF08C, 0x9958,	0xF08D, 0x9959, 0xF08E, 0x995A, 0xF08F, 0x995B, 0xF090, 0x995C,
+	0xF091, 0x995D, 0xF092, 0x995E, 0xF093, 0x995F, 0xF094, 0x9960,	0xF095, 0x9961, 0xF096, 0x9962, 0xF097, 0x9964, 0xF098, 0x9966,
+	0xF099, 0x9973, 0xF09A, 0x9978, 0xF09B, 0x9979, 0xF09C, 0x997B,	0xF09D, 0x997E, 0xF09E, 0x9982, 0xF09F, 0x9983, 0xF0A0, 0x9989,
+	0xF0A1, 0x7A39, 0xF0A2, 0x7A37, 0xF0A3, 0x7A51, 0xF0A4, 0x9ECF,	0xF0A5, 0x99A5, 0xF0A6, 0x7A70, 0xF0A7, 0x7688, 0xF0A8, 0x768E,
+	0xF0A9, 0x7693, 0xF0AA, 0x7699, 0xF0AB, 0x76A4, 0xF0AC, 0x74DE,	0xF0AD, 0x74E0, 0xF0AE, 0x752C, 0xF0AF, 0x9E20, 0xF0B0, 0x9E22,
+	0xF0B1, 0x9E28, 0xF0B2, 0x9E29, 0xF0B3, 0x9E2A, 0xF0B4, 0x9E2B,	0xF0B5, 0x9E2C, 0xF0B6, 0x9E32, 0xF0B7, 0x9E31, 0xF0B8, 0x9E36,
+	0xF0B9, 0x9E38, 0xF0BA, 0x9E37, 0xF0BB, 0x9E39, 0xF0BC, 0x9E3A,	0xF0BD, 0x9E3E, 0xF0BE, 0x9E41, 0xF0BF, 0x9E42, 0xF0C0, 0x9E44,
+	0xF0C1, 0x9E46, 0xF0C2, 0x9E47, 0xF0C3, 0x9E48, 0xF0C4, 0x9E49,	0xF0C5, 0x9E4B, 0xF0C6, 0x9E4C, 0xF0C7, 0x9E4E, 0xF0C8, 0x9E51,
+	0xF0C9, 0x9E55, 0xF0CA, 0x9E57, 0xF0CB, 0x9E5A, 0xF0CC, 0x9E5B,	0xF0CD, 0x9E5C, 0xF0CE, 0x9E5E, 0xF0CF, 0x9E63, 0xF0D0, 0x9E66,
+	0xF0D1, 0x9E67, 0xF0D2, 0x9E68, 0xF0D3, 0x9E69, 0xF0D4, 0x9E6A,	0xF0D5, 0x9E6B, 0xF0D6, 0x9E6C, 0xF0D7, 0x9E71, 0xF0D8, 0x9E6D,
+	0xF0D9, 0x9E73, 0xF0DA, 0x7592, 0xF0DB, 0x7594, 0xF0DC, 0x7596,	0xF0DD, 0x75A0, 0xF0DE, 0x759D, 0xF0DF, 0x75AC, 0xF0E0, 0x75A3,
+	0xF0E1, 0x75B3, 0xF0E2, 0x75B4, 0xF0E3, 0x75B8, 0xF0E4, 0x75C4,	0xF0E5, 0x75B1, 0xF0E6, 0x75B0, 0xF0E7, 0x75C3, 0xF0E8, 0x75C2,
+	0xF0E9, 0x75D6, 0xF0EA, 0x75CD, 0xF0EB, 0x75E3, 0xF0EC, 0x75E8,	0xF0ED, 0x75E6, 0xF0EE, 0x75E4, 0xF0EF, 0x75EB, 0xF0F0, 0x75E7,
+	0xF0F1, 0x7603, 0xF0F2, 0x75F1, 0xF0F3, 0x75FC, 0xF0F4, 0x75FF,	0xF0F5, 0x7610, 0xF0F6, 0x7600, 0xF0F7, 0x7605, 0xF0F8, 0x760C,
+	0xF0F9, 0x7617, 0xF0FA, 0x760A, 0xF0FB, 0x7625, 0xF0FC, 0x7618,	0xF0FD, 0x7615, 0xF0FE, 0x7619, 0xF140, 0x998C, 0xF141, 0x998E,
+	0xF142, 0x999A, 0xF143, 0x999B, 0xF144, 0x999C, 0xF145, 0x999D,	0xF146, 0x999E, 0xF147, 0x999F, 0xF148, 0x99A0, 0xF149, 0x99A1,
+	0xF14A, 0x99A2, 0xF14B, 0x99A3, 0xF14C, 0x99A4, 0xF14D, 0x99A6,	0xF14E, 0x99A7, 0xF14F, 0x99A9, 0xF150, 0x99AA, 0xF151, 0x99AB,
+	0xF152, 0x99AC, 0xF153, 0x99AD, 0xF154, 0x99AE, 0xF155, 0x99AF,	0xF156, 0x99B0, 0xF157, 0x99B1, 0xF158, 0x99B2, 0xF159, 0x99B3,
+	0xF15A, 0x99B4, 0xF15B, 0x99B5, 0xF15C, 0x99B6, 0xF15D, 0x99B7,	0xF15E, 0x99B8, 0xF15F, 0x99B9, 0xF160, 0x99BA, 0xF161, 0x99BB,
+	0xF162, 0x99BC, 0xF163, 0x99BD, 0xF164, 0x99BE, 0xF165, 0x99BF,	0xF166, 0x99C0, 0xF167, 0x99C1, 0xF168, 0x99C2, 0xF169, 0x99C3,
+	0xF16A, 0x99C4, 0xF16B, 0x99C5, 0xF16C, 0x99C6, 0xF16D, 0x99C7,	0xF16E, 0x99C8, 0xF16F, 0x99C9, 0xF170, 0x99CA, 0xF171, 0x99CB,
+	0xF172, 0x99CC, 0xF173, 0x99CD, 0xF174, 0x99CE, 0xF175, 0x99CF,	0xF176, 0x99D0, 0xF177, 0x99D1, 0xF178, 0x99D2, 0xF179, 0x99D3,
+	0xF17A, 0x99D4, 0xF17B, 0x99D5, 0xF17C, 0x99D6, 0xF17D, 0x99D7,	0xF17E, 0x99D8, 0xF180, 0x99D9, 0xF181, 0x99DA, 0xF182, 0x99DB,
+	0xF183, 0x99DC, 0xF184, 0x99DD, 0xF185, 0x99DE, 0xF186, 0x99DF,	0xF187, 0x99E0, 0xF188, 0x99E1, 0xF189, 0x99E2, 0xF18A, 0x99E3,
+	0xF18B, 0x99E4, 0xF18C, 0x99E5, 0xF18D, 0x99E6, 0xF18E, 0x99E7,	0xF18F, 0x99E8, 0xF190, 0x99E9, 0xF191, 0x99EA, 0xF192, 0x99EB,
+	0xF193, 0x99EC, 0xF194, 0x99ED, 0xF195, 0x99EE, 0xF196, 0x99EF,	0xF197, 0x99F0, 0xF198, 0x99F1, 0xF199, 0x99F2, 0xF19A, 0x99F3,
+	0xF19B, 0x99F4, 0xF19C, 0x99F5, 0xF19D, 0x99F6, 0xF19E, 0x99F7,	0xF19F, 0x99F8, 0xF1A0, 0x99F9, 0xF1A1, 0x761B, 0xF1A2, 0x763C,
+	0xF1A3, 0x7622, 0xF1A4, 0x7620, 0xF1A5, 0x7640, 0xF1A6, 0x762D,	0xF1A7, 0x7630, 0xF1A8, 0x763F, 0xF1A9, 0x7635, 0xF1AA, 0x7643,
+	0xF1AB, 0x763E, 0xF1AC, 0x7633, 0xF1AD, 0x764D, 0xF1AE, 0x765E,	0xF1AF, 0x7654, 0xF1B0, 0x765C, 0xF1B1, 0x7656, 0xF1B2, 0x766B,
+	0xF1B3, 0x766F, 0xF1B4, 0x7FCA, 0xF1B5, 0x7AE6, 0xF1B6, 0x7A78,	0xF1B7, 0x7A79, 0xF1B8, 0x7A80, 0xF1B9, 0x7A86, 0xF1BA, 0x7A88,
+	0xF1BB, 0x7A95, 0xF1BC, 0x7AA6, 0xF1BD, 0x7AA0, 0xF1BE, 0x7AAC,	0xF1BF, 0x7AA8, 0xF1C0, 0x7AAD, 0xF1C1, 0x7AB3, 0xF1C2, 0x8864,
+	0xF1C3, 0x8869, 0xF1C4, 0x8872, 0xF1C5, 0x887D, 0xF1C6, 0x887F,	0xF1C7, 0x8882, 0xF1C8, 0x88A2, 0xF1C9, 0x88C6, 0xF1CA, 0x88B7,
+	0xF1CB, 0x88BC, 0xF1CC, 0x88C9, 0xF1CD, 0x88E2, 0xF1CE, 0x88CE,	0xF1CF, 0x88E3, 0xF1D0, 0x88E5, 0xF1D1, 0x88F1, 0xF1D2, 0x891A,
+	0xF1D3, 0x88FC, 0xF1D4, 0x88E8, 0xF1D5, 0x88FE, 0xF1D6, 0x88F0,	0xF1D7, 0x8921, 0xF1D8, 0x8919, 0xF1D9, 0x8913, 0xF1DA, 0x891B,
+	0xF1DB, 0x890A, 0xF1DC, 0x8934, 0xF1DD, 0x892B, 0xF1DE, 0x8936,	0xF1DF, 0x8941, 0xF1E0, 0x8966, 0xF1E1, 0x897B, 0xF1E2, 0x758B,
+	0xF1E3, 0x80E5, 0xF1E4, 0x76B2, 0xF1E5, 0x76B4, 0xF1E6, 0x77DC,	0xF1E7, 0x8012, 0xF1E8, 0x8014, 0xF1E9, 0x8016, 0xF1EA, 0x801C,
+	0xF1EB, 0x8020, 0xF1EC, 0x8022, 0xF1ED, 0x8025, 0xF1EE, 0x8026,	0xF1EF, 0x8027, 0xF1F0, 0x8029, 0xF1F1, 0x8028, 0xF1F2, 0x8031,
+	0xF1F3, 0x800B, 0xF1F4, 0x8035, 0xF1F5, 0x8043, 0xF1F6, 0x8046,	0xF1F7, 0x804D, 0xF1F8, 0x8052, 0xF1F9, 0x8069, 0xF1FA, 0x8071,
+	0xF1FB, 0x8983, 0xF1FC, 0x9878, 0xF1FD, 0x9880, 0xF1FE, 0x9883,	0xF240, 0x99FA, 0xF241, 0x99FB, 0xF242, 0x99FC, 0xF243, 0x99FD,
+	0xF244, 0x99FE, 0xF245, 0x99FF, 0xF246, 0x9A00, 0xF247, 0x9A01,	0xF248, 0x9A02, 0xF249, 0x9A03, 0xF24A, 0x9A04, 0xF24B, 0x9A05,
+	0xF24C, 0x9A06, 0xF24D, 0x9A07, 0xF24E, 0x9A08, 0xF24F, 0x9A09,	0xF250, 0x9A0A, 0xF251, 0x9A0B, 0xF252, 0x9A0C, 0xF253, 0x9A0D,
+	0xF254, 0x9A0E, 0xF255, 0x9A0F, 0xF256, 0x9A10, 0xF257, 0x9A11,	0xF258, 0x9A12, 0xF259, 0x9A13, 0xF25A, 0x9A14, 0xF25B, 0x9A15,
+	0xF25C, 0x9A16, 0xF25D, 0x9A17, 0xF25E, 0x9A18, 0xF25F, 0x9A19,	0xF260, 0x9A1A, 0xF261, 0x9A1B, 0xF262, 0x9A1C, 0xF263, 0x9A1D,
+	0xF264, 0x9A1E, 0xF265, 0x9A1F, 0xF266, 0x9A20, 0xF267, 0x9A21,	0xF268, 0x9A22, 0xF269, 0x9A23, 0xF26A, 0x9A24, 0xF26B, 0x9A25,
+	0xF26C, 0x9A26, 0xF26D, 0x9A27, 0xF26E, 0x9A28, 0xF26F, 0x9A29,	0xF270, 0x9A2A, 0xF271, 0x9A2B, 0xF272, 0x9A2C, 0xF273, 0x9A2D,
+	0xF274, 0x9A2E, 0xF275, 0x9A2F, 0xF276, 0x9A30, 0xF277, 0x9A31,	0xF278, 0x9A32, 0xF279, 0x9A33, 0xF27A, 0x9A34, 0xF27B, 0x9A35,
+	0xF27C, 0x9A36, 0xF27D, 0x9A37, 0xF27E, 0x9A38, 0xF280, 0x9A39,	0xF281, 0x9A3A, 0xF282, 0x9A3B, 0xF283, 0x9A3C, 0xF284, 0x9A3D,
+	0xF285, 0x9A3E, 0xF286, 0x9A3F, 0xF287, 0x9A40, 0xF288, 0x9A41,	0xF289, 0x9A42, 0xF28A, 0x9A43, 0xF28B, 0x9A44, 0xF28C, 0x9A45,
+	0xF28D, 0x9A46, 0xF28E, 0x9A47, 0xF28F, 0x9A48, 0xF290, 0x9A49,	0xF291, 0x9A4A, 0xF292, 0x9A4B, 0xF293, 0x9A4C, 0xF294, 0x9A4D,
+	0xF295, 0x9A4E, 0xF296, 0x9A4F, 0xF297, 0x9A50, 0xF298, 0x9A51,	0xF299, 0x9A52, 0xF29A, 0x9A53, 0xF29B, 0x9A54, 0xF29C, 0x9A55,
+	0xF29D, 0x9A56, 0xF29E, 0x9A57, 0xF29F, 0x9A58, 0xF2A0, 0x9A59,	0xF2A1, 0x9889, 0xF2A2, 0x988C, 0xF2A3, 0x988D, 0xF2A4, 0x988F,
+	0xF2A5, 0x9894, 0xF2A6, 0x989A, 0xF2A7, 0x989B, 0xF2A8, 0x989E,	0xF2A9, 0x989F, 0xF2AA, 0x98A1, 0xF2AB, 0x98A2, 0xF2AC, 0x98A5,
+	0xF2AD, 0x98A6, 0xF2AE, 0x864D, 0xF2AF, 0x8654, 0xF2B0, 0x866C,	0xF2B1, 0x866E, 0xF2B2, 0x867F, 0xF2B3, 0x867A, 0xF2B4, 0x867C,
+	0xF2B5, 0x867B, 0xF2B6, 0x86A8, 0xF2B7, 0x868D, 0xF2B8, 0x868B,	0xF2B9, 0x86AC, 0xF2BA, 0x869D, 0xF2BB, 0x86A7, 0xF2BC, 0x86A3,
+	0xF2BD, 0x86AA, 0xF2BE, 0x8693, 0xF2BF, 0x86A9, 0xF2C0, 0x86B6,	0xF2C1, 0x86C4, 0xF2C2, 0x86B5, 0xF2C3, 0x86CE, 0xF2C4, 0x86B0,
+	0xF2C5, 0x86BA, 0xF2C6, 0x86B1, 0xF2C7, 0x86AF, 0xF2C8, 0x86C9,	0xF2C9, 0x86CF, 0xF2CA, 0x86B4, 0xF2CB, 0x86E9, 0xF2CC, 0x86F1,
+	0xF2CD, 0x86F2, 0xF2CE, 0x86ED, 0xF2CF, 0x86F3, 0xF2D0, 0x86D0,	0xF2D1, 0x8713, 0xF2D2, 0x86DE, 0xF2D3, 0x86F4, 0xF2D4, 0x86DF,
+	0xF2D5, 0x86D8, 0xF2D6, 0x86D1, 0xF2D7, 0x8703, 0xF2D8, 0x8707,	0xF2D9, 0x86F8, 0xF2DA, 0x8708, 0xF2DB, 0x870A, 0xF2DC, 0x870D,
+	0xF2DD, 0x8709, 0xF2DE, 0x8723, 0xF2DF, 0x873B, 0xF2E0, 0x871E,	0xF2E1, 0x8725, 0xF2E2, 0x872E, 0xF2E3, 0x871A, 0xF2E4, 0x873E,
+	0xF2E5, 0x8748, 0xF2E6, 0x8734, 0xF2E7, 0x8731, 0xF2E8, 0x8729,	0xF2E9, 0x8737, 0xF2EA, 0x873F, 0xF2EB, 0x8782, 0xF2EC, 0x8722,
+	0xF2ED, 0x877D, 0xF2EE, 0x877E, 0xF2EF, 0x877B, 0xF2F0, 0x8760,	0xF2F1, 0x8770, 0xF2F2, 0x874C, 0xF2F3, 0x876E, 0xF2F4, 0x878B,
+	0xF2F5, 0x8753, 0xF2F6, 0x8763, 0xF2F7, 0x877C, 0xF2F8, 0x8764,	0xF2F9, 0x8759, 0xF2FA, 0x8765, 0xF2FB, 0x8793, 0xF2FC, 0x87AF,
+	0xF2FD, 0x87A8, 0xF2FE, 0x87D2, 0xF340, 0x9A5A, 0xF341, 0x9A5B,	0xF342, 0x9A5C, 0xF343, 0x9A5D, 0xF344, 0x9A5E, 0xF345, 0x9A5F,
+	0xF346, 0x9A60, 0xF347, 0x9A61, 0xF348, 0x9A62, 0xF349, 0x9A63,	0xF34A, 0x9A64, 0xF34B, 0x9A65, 0xF34C, 0x9A66, 0xF34D, 0x9A67,
+	0xF34E, 0x9A68, 0xF34F, 0x9A69, 0xF350, 0x9A6A, 0xF351, 0x9A6B,	0xF352, 0x9A72, 0xF353, 0x9A83, 0xF354, 0x9A89, 0xF355, 0x9A8D,
+	0xF356, 0x9A8E, 0xF357, 0x9A94, 0xF358, 0x9A95, 0xF359, 0x9A99,	0xF35A, 0x9AA6, 0xF35B, 0x9AA9, 0xF35C, 0x9AAA, 0xF35D, 0x9AAB,
+	0xF35E, 0x9AAC, 0xF35F, 0x9AAD, 0xF360, 0x9AAE, 0xF361, 0x9AAF,	0xF362, 0x9AB2, 0xF363, 0x9AB3, 0xF364, 0x9AB4, 0xF365, 0x9AB5,
+	0xF366, 0x9AB9, 0xF367, 0x9ABB, 0xF368, 0x9ABD, 0xF369, 0x9ABE,	0xF36A, 0x9ABF, 0xF36B, 0x9AC3, 0xF36C, 0x9AC4, 0xF36D, 0x9AC6,
+	0xF36E, 0x9AC7, 0xF36F, 0x9AC8, 0xF370, 0x9AC9, 0xF371, 0x9ACA,	0xF372, 0x9ACD, 0xF373, 0x9ACE, 0xF374, 0x9ACF, 0xF375, 0x9AD0,
+	0xF376, 0x9AD2, 0xF377, 0x9AD4, 0xF378, 0x9AD5, 0xF379, 0x9AD6,	0xF37A, 0x9AD7, 0xF37B, 0x9AD9, 0xF37C, 0x9ADA, 0xF37D, 0x9ADB,
+	0xF37E, 0x9ADC, 0xF380, 0x9ADD, 0xF381, 0x9ADE, 0xF382, 0x9AE0,	0xF383, 0x9AE2, 0xF384, 0x9AE3, 0xF385, 0x9AE4, 0xF386, 0x9AE5,
+	0xF387, 0x9AE7, 0xF388, 0x9AE8, 0xF389, 0x9AE9, 0xF38A, 0x9AEA,	0xF38B, 0x9AEC, 0xF38C, 0x9AEE, 0xF38D, 0x9AF0, 0xF38E, 0x9AF1,
+	0xF38F, 0x9AF2, 0xF390, 0x9AF3, 0xF391, 0x9AF4, 0xF392, 0x9AF5,	0xF393, 0x9AF6, 0xF394, 0x9AF7, 0xF395, 0x9AF8, 0xF396, 0x9AFA,
+	0xF397, 0x9AFC, 0xF398, 0x9AFD, 0xF399, 0x9AFE, 0xF39A, 0x9AFF,	0xF39B, 0x9B00, 0xF39C, 0x9B01, 0xF39D, 0x9B02, 0xF39E, 0x9B04,
+	0xF39F, 0x9B05, 0xF3A0, 0x9B06, 0xF3A1, 0x87C6, 0xF3A2, 0x8788,	0xF3A3, 0x8785, 0xF3A4, 0x87AD, 0xF3A5, 0x8797, 0xF3A6, 0x8783,
+	0xF3A7, 0x87AB, 0xF3A8, 0x87E5, 0xF3A9, 0x87AC, 0xF3AA, 0x87B5,	0xF3AB, 0x87B3, 0xF3AC, 0x87CB, 0xF3AD, 0x87D3, 0xF3AE, 0x87BD,
+	0xF3AF, 0x87D1, 0xF3B0, 0x87C0, 0xF3B1, 0x87CA, 0xF3B2, 0x87DB,	0xF3B3, 0x87EA, 0xF3B4, 0x87E0, 0xF3B5, 0x87EE, 0xF3B6, 0x8816,
+	0xF3B7, 0x8813, 0xF3B8, 0x87FE, 0xF3B9, 0x880A, 0xF3BA, 0x881B,	0xF3BB, 0x8821, 0xF3BC, 0x8839, 0xF3BD, 0x883C, 0xF3BE, 0x7F36,
+	0xF3BF, 0x7F42, 0xF3C0, 0x7F44, 0xF3C1, 0x7F45, 0xF3C2, 0x8210,	0xF3C3, 0x7AFA, 0xF3C4, 0x7AFD, 0xF3C5, 0x7B08, 0xF3C6, 0x7B03,
+	0xF3C7, 0x7B04, 0xF3C8, 0x7B15, 0xF3C9, 0x7B0A, 0xF3CA, 0x7B2B,	0xF3CB, 0x7B0F, 0xF3CC, 0x7B47, 0xF3CD, 0x7B38, 0xF3CE, 0x7B2A,
+	0xF3CF, 0x7B19, 0xF3D0, 0x7B2E, 0xF3D1, 0x7B31, 0xF3D2, 0x7B20,	0xF3D3, 0x7B25, 0xF3D4, 0x7B24, 0xF3D5, 0x7B33, 0xF3D6, 0x7B3E,
+	0xF3D7, 0x7B1E, 0xF3D8, 0x7B58, 0xF3D9, 0x7B5A, 0xF3DA, 0x7B45,	0xF3DB, 0x7B75, 0xF3DC, 0x7B4C, 0xF3DD, 0x7B5D, 0xF3DE, 0x7B60,
+	0xF3DF, 0x7B6E, 0xF3E0, 0x7B7B, 0xF3E1, 0x7B62, 0xF3E2, 0x7B72,	0xF3E3, 0x7B71, 0xF3E4, 0x7B90, 0xF3E5, 0x7BA6, 0xF3E6, 0x7BA7,
+	0xF3E7, 0x7BB8, 0xF3E8, 0x7BAC, 0xF3E9, 0x7B9D, 0xF3EA, 0x7BA8,	0xF3EB, 0x7B85, 0xF3EC, 0x7BAA, 0xF3ED, 0x7B9C, 0xF3EE, 0x7BA2,
+	0xF3EF, 0x7BAB, 0xF3F0, 0x7BB4, 0xF3F1, 0x7BD1, 0xF3F2, 0x7BC1,	0xF3F3, 0x7BCC, 0xF3F4, 0x7BDD, 0xF3F5, 0x7BDA, 0xF3F6, 0x7BE5,
+	0xF3F7, 0x7BE6, 0xF3F8, 0x7BEA, 0xF3F9, 0x7C0C, 0xF3FA, 0x7BFE,	0xF3FB, 0x7BFC, 0xF3FC, 0x7C0F, 0xF3FD, 0x7C16, 0xF3FE, 0x7C0B,
+	0xF440, 0x9B07, 0xF441, 0x9B09, 0xF442, 0x9B0A, 0xF443, 0x9B0B,	0xF444, 0x9B0C, 0xF445, 0x9B0D, 0xF446, 0x9B0E, 0xF447, 0x9B10,
+	0xF448, 0x9B11, 0xF449, 0x9B12, 0xF44A, 0x9B14, 0xF44B, 0x9B15,	0xF44C, 0x9B16, 0xF44D, 0x9B17, 0xF44E, 0x9B18, 0xF44F, 0x9B19,
+	0xF450, 0x9B1A, 0xF451, 0x9B1B, 0xF452, 0x9B1C, 0xF453, 0x9B1D,	0xF454, 0x9B1E, 0xF455, 0x9B20, 0xF456, 0x9B21, 0xF457, 0x9B22,
+	0xF458, 0x9B24, 0xF459, 0x9B25, 0xF45A, 0x9B26, 0xF45B, 0x9B27,	0xF45C, 0x9B28, 0xF45D, 0x9B29, 0xF45E, 0x9B2A, 0xF45F, 0x9B2B,
+	0xF460, 0x9B2C, 0xF461, 0x9B2D, 0xF462, 0x9B2E, 0xF463, 0x9B30,	0xF464, 0x9B31, 0xF465, 0x9B33, 0xF466, 0x9B34, 0xF467, 0x9B35,
+	0xF468, 0x9B36, 0xF469, 0x9B37, 0xF46A, 0x9B38, 0xF46B, 0x9B39,	0xF46C, 0x9B3A, 0xF46D, 0x9B3D, 0xF46E, 0x9B3E, 0xF46F, 0x9B3F,
+	0xF470, 0x9B40, 0xF471, 0x9B46, 0xF472, 0x9B4A, 0xF473, 0x9B4B,	0xF474, 0x9B4C, 0xF475, 0x9B4E, 0xF476, 0x9B50, 0xF477, 0x9B52,
+	0xF478, 0x9B53, 0xF479, 0x9B55, 0xF47A, 0x9B56, 0xF47B, 0x9B57,	0xF47C, 0x9B58, 0xF47D, 0x9B59, 0xF47E, 0x9B5A, 0xF480, 0x9B5B,
+	0xF481, 0x9B5C, 0xF482, 0x9B5D, 0xF483, 0x9B5E, 0xF484, 0x9B5F,	0xF485, 0x9B60, 0xF486, 0x9B61, 0xF487, 0x9B62, 0xF488, 0x9B63,
+	0xF489, 0x9B64, 0xF48A, 0x9B65, 0xF48B, 0x9B66, 0xF48C, 0x9B67,	0xF48D, 0x9B68, 0xF48E, 0x9B69, 0xF48F, 0x9B6A, 0xF490, 0x9B6B,
+	0xF491, 0x9B6C, 0xF492, 0x9B6D, 0xF493, 0x9B6E, 0xF494, 0x9B6F,	0xF495, 0x9B70, 0xF496, 0x9B71, 0xF497, 0x9B72, 0xF498, 0x9B73,
+	0xF499, 0x9B74, 0xF49A, 0x9B75, 0xF49B, 0x9B76, 0xF49C, 0x9B77,	0xF49D, 0x9B78, 0xF49E, 0x9B79, 0xF49F, 0x9B7A, 0xF4A0, 0x9B7B,
+	0xF4A1, 0x7C1F, 0xF4A2, 0x7C2A, 0xF4A3, 0x7C26, 0xF4A4, 0x7C38,	0xF4A5, 0x7C41, 0xF4A6, 0x7C40, 0xF4A7, 0x81FE, 0xF4A8, 0x8201,
+	0xF4A9, 0x8202, 0xF4AA, 0x8204, 0xF4AB, 0x81EC, 0xF4AC, 0x8844,	0xF4AD, 0x8221, 0xF4AE, 0x8222, 0xF4AF, 0x8223, 0xF4B0, 0x822D,
+	0xF4B1, 0x822F, 0xF4B2, 0x8228, 0xF4B3, 0x822B, 0xF4B4, 0x8238,	0xF4B5, 0x823B, 0xF4B6, 0x8233, 0xF4B7, 0x8234, 0xF4B8, 0x823E,
+	0xF4B9, 0x8244, 0xF4BA, 0x8249, 0xF4BB, 0x824B, 0xF4BC, 0x824F,	0xF4BD, 0x825A, 0xF4BE, 0x825F, 0xF4BF, 0x8268, 0xF4C0, 0x887E,
+	0xF4C1, 0x8885, 0xF4C2, 0x8888, 0xF4C3, 0x88D8, 0xF4C4, 0x88DF,	0xF4C5, 0x895E, 0xF4C6, 0x7F9D, 0xF4C7, 0x7F9F, 0xF4C8, 0x7FA7,
+	0xF4C9, 0x7FAF, 0xF4CA, 0x7FB0, 0xF4CB, 0x7FB2, 0xF4CC, 0x7C7C,	0xF4CD, 0x6549, 0xF4CE, 0x7C91, 0xF4CF, 0x7C9D, 0xF4D0, 0x7C9C,
+	0xF4D1, 0x7C9E, 0xF4D2, 0x7CA2, 0xF4D3, 0x7CB2, 0xF4D4, 0x7CBC,	0xF4D5, 0x7CBD, 0xF4D6, 0x7CC1, 0xF4D7, 0x7CC7, 0xF4D8, 0x7CCC,
+	0xF4D9, 0x7CCD, 0xF4DA, 0x7CC8, 0xF4DB, 0x7CC5, 0xF4DC, 0x7CD7,	0xF4DD, 0x7CE8, 0xF4DE, 0x826E, 0xF4DF, 0x66A8, 0xF4E0, 0x7FBF,
+	0xF4E1, 0x7FCE, 0xF4E2, 0x7FD5, 0xF4E3, 0x7FE5, 0xF4E4, 0x7FE1,	0xF4E5, 0x7FE6, 0xF4E6, 0x7FE9, 0xF4E7, 0x7FEE, 0xF4E8, 0x7FF3,
+	0xF4E9, 0x7CF8, 0xF4EA, 0x7D77, 0xF4EB, 0x7DA6, 0xF4EC, 0x7DAE,	0xF4ED, 0x7E47, 0xF4EE, 0x7E9B, 0xF4EF, 0x9EB8, 0xF4F0, 0x9EB4,
+	0xF4F1, 0x8D73, 0xF4F2, 0x8D84, 0xF4F3, 0x8D94, 0xF4F4, 0x8D91,	0xF4F5, 0x8DB1, 0xF4F6, 0x8D67, 0xF4F7, 0x8D6D, 0xF4F8, 0x8C47,
+	0xF4F9, 0x8C49, 0xF4FA, 0x914A, 0xF4FB, 0x9150, 0xF4FC, 0x914E,	0xF4FD, 0x914F, 0xF4FE, 0x9164, 0xF540, 0x9B7C, 0xF541, 0x9B7D,
+	0xF542, 0x9B7E, 0xF543, 0x9B7F, 0xF544, 0x9B80, 0xF545, 0x9B81,	0xF546, 0x9B82, 0xF547, 0x9B83, 0xF548, 0x9B84, 0xF549, 0x9B85,
+	0xF54A, 0x9B86, 0xF54B, 0x9B87, 0xF54C, 0x9B88, 0xF54D, 0x9B89,	0xF54E, 0x9B8A, 0xF54F, 0x9B8B, 0xF550, 0x9B8C, 0xF551, 0x9B8D,
+	0xF552, 0x9B8E, 0xF553, 0x9B8F, 0xF554, 0x9B90, 0xF555, 0x9B91,	0xF556, 0x9B92, 0xF557, 0x9B93, 0xF558, 0x9B94, 0xF559, 0x9B95,
+	0xF55A, 0x9B96, 0xF55B, 0x9B97, 0xF55C, 0x9B98, 0xF55D, 0x9B99,	0xF55E, 0x9B9A, 0xF55F, 0x9B9B, 0xF560, 0x9B9C, 0xF561, 0x9B9D,
+	0xF562, 0x9B9E, 0xF563, 0x9B9F, 0xF564, 0x9BA0, 0xF565, 0x9BA1,	0xF566, 0x9BA2, 0xF567, 0x9BA3, 0xF568, 0x9BA4, 0xF569, 0x9BA5,
+	0xF56A, 0x9BA6, 0xF56B, 0x9BA7, 0xF56C, 0x9BA8, 0xF56D, 0x9BA9,	0xF56E, 0x9BAA, 0xF56F, 0x9BAB, 0xF570, 0x9BAC, 0xF571, 0x9BAD,
+	0xF572, 0x9BAE, 0xF573, 0x9BAF, 0xF574, 0x9BB0, 0xF575, 0x9BB1,	0xF576, 0x9BB2, 0xF577, 0x9BB3, 0xF578, 0x9BB4, 0xF579, 0x9BB5,
+	0xF57A, 0x9BB6, 0xF57B, 0x9BB7, 0xF57C, 0x9BB8, 0xF57D, 0x9BB9,	0xF57E, 0x9BBA, 0xF580, 0x9BBB, 0xF581, 0x9BBC, 0xF582, 0x9BBD,
+	0xF583, 0x9BBE, 0xF584, 0x9BBF, 0xF585, 0x9BC0, 0xF586, 0x9BC1,	0xF587, 0x9BC2, 0xF588, 0x9BC3, 0xF589, 0x9BC4, 0xF58A, 0x9BC5,
+	0xF58B, 0x9BC6, 0xF58C, 0x9BC7, 0xF58D, 0x9BC8, 0xF58E, 0x9BC9,	0xF58F, 0x9BCA, 0xF590, 0x9BCB, 0xF591, 0x9BCC, 0xF592, 0x9BCD,
+	0xF593, 0x9BCE, 0xF594, 0x9BCF, 0xF595, 0x9BD0, 0xF596, 0x9BD1,	0xF597, 0x9BD2, 0xF598, 0x9BD3, 0xF599, 0x9BD4, 0xF59A, 0x9BD5,
+	0xF59B, 0x9BD6, 0xF59C, 0x9BD7, 0xF59D, 0x9BD8, 0xF59E, 0x9BD9,	0xF59F, 0x9BDA, 0xF5A0, 0x9BDB, 0xF5A1, 0x9162, 0xF5A2, 0x9161,
+	0xF5A3, 0x9170, 0xF5A4, 0x9169, 0xF5A5, 0x916F, 0xF5A6, 0x917D,	0xF5A7, 0x917E, 0xF5A8, 0x9172, 0xF5A9, 0x9174, 0xF5AA, 0x9179,
+	0xF5AB, 0x918C, 0xF5AC, 0x9185, 0xF5AD, 0x9190, 0xF5AE, 0x918D,	0xF5AF, 0x9191, 0xF5B0, 0x91A2, 0xF5B1, 0x91A3, 0xF5B2, 0x91AA,
+	0xF5B3, 0x91AD, 0xF5B4, 0x91AE, 0xF5B5, 0x91AF, 0xF5B6, 0x91B5,	0xF5B7, 0x91B4, 0xF5B8, 0x91BA, 0xF5B9, 0x8C55, 0xF5BA, 0x9E7E,
+	0xF5BB, 0x8DB8, 0xF5BC, 0x8DEB, 0xF5BD, 0x8E05, 0xF5BE, 0x8E59,	0xF5BF, 0x8E69, 0xF5C0, 0x8DB5, 0xF5C1, 0x8DBF, 0xF5C2, 0x8DBC,
+	0xF5C3, 0x8DBA, 0xF5C4, 0x8DC4, 0xF5C5, 0x8DD6, 0xF5C6, 0x8DD7,	0xF5C7, 0x8DDA, 0xF5C8, 0x8DDE, 0xF5C9, 0x8DCE, 0xF5CA, 0x8DCF,
+	0xF5CB, 0x8DDB, 0xF5CC, 0x8DC6, 0xF5CD, 0x8DEC, 0xF5CE, 0x8DF7,	0xF5CF, 0x8DF8, 0xF5D0, 0x8DE3, 0xF5D1, 0x8DF9, 0xF5D2, 0x8DFB,
+	0xF5D3, 0x8DE4, 0xF5D4, 0x8E09, 0xF5D5, 0x8DFD, 0xF5D6, 0x8E14,	0xF5D7, 0x8E1D, 0xF5D8, 0x8E1F, 0xF5D9, 0x8E2C, 0xF5DA, 0x8E2E,
+	0xF5DB, 0x8E23, 0xF5DC, 0x8E2F, 0xF5DD, 0x8E3A, 0xF5DE, 0x8E40,	0xF5DF, 0x8E39, 0xF5E0, 0x8E35, 0xF5E1, 0x8E3D, 0xF5E2, 0x8E31,
+	0xF5E3, 0x8E49, 0xF5E4, 0x8E41, 0xF5E5, 0x8E42, 0xF5E6, 0x8E51,	0xF5E7, 0x8E52, 0xF5E8, 0x8E4A, 0xF5E9, 0x8E70, 0xF5EA, 0x8E76,
+	0xF5EB, 0x8E7C, 0xF5EC, 0x8E6F, 0xF5ED, 0x8E74, 0xF5EE, 0x8E85,	0xF5EF, 0x8E8F, 0xF5F0, 0x8E94, 0xF5F1, 0x8E90, 0xF5F2, 0x8E9C,
+	0xF5F3, 0x8E9E, 0xF5F4, 0x8C78, 0xF5F5, 0x8C82, 0xF5F6, 0x8C8A,	0xF5F7, 0x8C85, 0xF5F8, 0x8C98, 0xF5F9, 0x8C94, 0xF5FA, 0x659B,
+	0xF5FB, 0x89D6, 0xF5FC, 0x89DE, 0xF5FD, 0x89DA, 0xF5FE, 0x89DC,	0xF640, 0x9BDC, 0xF641, 0x9BDD, 0xF642, 0x9BDE, 0xF643, 0x9BDF,
+	0xF644, 0x9BE0, 0xF645, 0x9BE1, 0xF646, 0x9BE2, 0xF647, 0x9BE3,	0xF648, 0x9BE4, 0xF649, 0x9BE5, 0xF64A, 0x9BE6, 0xF64B, 0x9BE7,
+	0xF64C, 0x9BE8, 0xF64D, 0x9BE9, 0xF64E, 0x9BEA, 0xF64F, 0x9BEB,	0xF650, 0x9BEC, 0xF651, 0x9BED, 0xF652, 0x9BEE, 0xF653, 0x9BEF,
+	0xF654, 0x9BF0, 0xF655, 0x9BF1, 0xF656, 0x9BF2, 0xF657, 0x9BF3,	0xF658, 0x9BF4, 0xF659, 0x9BF5, 0xF65A, 0x9BF6, 0xF65B, 0x9BF7,
+	0xF65C, 0x9BF8, 0xF65D, 0x9BF9, 0xF65E, 0x9BFA, 0xF65F, 0x9BFB,	0xF660, 0x9BFC, 0xF661, 0x9BFD, 0xF662, 0x9BFE, 0xF663, 0x9BFF,
+	0xF664, 0x9C00, 0xF665, 0x9C01, 0xF666, 0x9C02, 0xF667, 0x9C03,	0xF668, 0x9C04, 0xF669, 0x9C05, 0xF66A, 0x9C06, 0xF66B, 0x9C07,
+	0xF66C, 0x9C08, 0xF66D, 0x9C09, 0xF66E, 0x9C0A, 0xF66F, 0x9C0B,	0xF670, 0x9C0C, 0xF671, 0x9C0D, 0xF672, 0x9C0E, 0xF673, 0x9C0F,
+	0xF674, 0x9C10, 0xF675, 0x9C11, 0xF676, 0x9C12, 0xF677, 0x9C13,	0xF678, 0x9C14, 0xF679, 0x9C15, 0xF67A, 0x9C16, 0xF67B, 0x9C17,
+	0xF67C, 0x9C18, 0xF67D, 0x9C19, 0xF67E, 0x9C1A, 0xF680, 0x9C1B,	0xF681, 0x9C1C, 0xF682, 0x9C1D, 0xF683, 0x9C1E, 0xF684, 0x9C1F,
+	0xF685, 0x9C20, 0xF686, 0x9C21, 0xF687, 0x9C22, 0xF688, 0x9C23,	0xF689, 0x9C24, 0xF68A, 0x9C25, 0xF68B, 0x9C26, 0xF68C, 0x9C27,
+	0xF68D, 0x9C28, 0xF68E, 0x9C29, 0xF68F, 0x9C2A, 0xF690, 0x9C2B,	0xF691, 0x9C2C, 0xF692, 0x9C2D, 0xF693, 0x9C2E, 0xF694, 0x9C2F,
+	0xF695, 0x9C30, 0xF696, 0x9C31, 0xF697, 0x9C32, 0xF698, 0x9C33,	0xF699, 0x9C34, 0xF69A, 0x9C35, 0xF69B, 0x9C36, 0xF69C, 0x9C37,
+	0xF69D, 0x9C38, 0xF69E, 0x9C39, 0xF69F, 0x9C3A, 0xF6A0, 0x9C3B,	0xF6A1, 0x89E5, 0xF6A2, 0x89EB, 0xF6A3, 0x89EF, 0xF6A4, 0x8A3E,
+	0xF6A5, 0x8B26, 0xF6A6, 0x9753, 0xF6A7, 0x96E9, 0xF6A8, 0x96F3,	0xF6A9, 0x96EF, 0xF6AA, 0x9706, 0xF6AB, 0x9701, 0xF6AC, 0x9708,
+	0xF6AD, 0x970F, 0xF6AE, 0x970E, 0xF6AF, 0x972A, 0xF6B0, 0x972D,	0xF6B1, 0x9730, 0xF6B2, 0x973E, 0xF6B3, 0x9F80, 0xF6B4, 0x9F83,
+	0xF6B5, 0x9F85, 0xF6B6, 0x9F86, 0xF6B7, 0x9F87, 0xF6B8, 0x9F88,	0xF6B9, 0x9F89, 0xF6BA, 0x9F8A, 0xF6BB, 0x9F8C, 0xF6BC, 0x9EFE,
+	0xF6BD, 0x9F0B, 0xF6BE, 0x9F0D, 0xF6BF, 0x96B9, 0xF6C0, 0x96BC,	0xF6C1, 0x96BD, 0xF6C2, 0x96CE, 0xF6C3, 0x96D2, 0xF6C4, 0x77BF,
+	0xF6C5, 0x96E0, 0xF6C6, 0x928E, 0xF6C7, 0x92AE, 0xF6C8, 0x92C8,	0xF6C9, 0x933E, 0xF6CA, 0x936A, 0xF6CB, 0x93CA, 0xF6CC, 0x938F,
+	0xF6CD, 0x943E, 0xF6CE, 0x946B, 0xF6CF, 0x9C7F, 0xF6D0, 0x9C82,	0xF6D1, 0x9C85, 0xF6D2, 0x9C86, 0xF6D3, 0x9C87, 0xF6D4, 0x9C88,
+	0xF6D5, 0x7A23, 0xF6D6, 0x9C8B, 0xF6D7, 0x9C8E, 0xF6D8, 0x9C90,	0xF6D9, 0x9C91, 0xF6DA, 0x9C92, 0xF6DB, 0x9C94, 0xF6DC, 0x9C95,
+	0xF6DD, 0x9C9A, 0xF6DE, 0x9C9B, 0xF6DF, 0x9C9E, 0xF6E0, 0x9C9F,	0xF6E1, 0x9CA0, 0xF6E2, 0x9CA1, 0xF6E3, 0x9CA2, 0xF6E4, 0x9CA3,
+	0xF6E5, 0x9CA5, 0xF6E6, 0x9CA6, 0xF6E7, 0x9CA7, 0xF6E8, 0x9CA8,	0xF6E9, 0x9CA9, 0xF6EA, 0x9CAB, 0xF6EB, 0x9CAD, 0xF6EC, 0x9CAE,
+	0xF6ED, 0x9CB0, 0xF6EE, 0x9CB1, 0xF6EF, 0x9CB2, 0xF6F0, 0x9CB3,	0xF6F1, 0x9CB4, 0xF6F2, 0x9CB5, 0xF6F3, 0x9CB6, 0xF6F4, 0x9CB7,
+	0xF6F5, 0x9CBA, 0xF6F6, 0x9CBB, 0xF6F7, 0x9CBC, 0xF6F8, 0x9CBD,	0xF6F9, 0x9CC4, 0xF6FA, 0x9CC5, 0xF6FB, 0x9CC6, 0xF6FC, 0x9CC7,
+	0xF6FD, 0x9CCA, 0xF6FE, 0x9CCB, 0xF740, 0x9C3C, 0xF741, 0x9C3D,	0xF742, 0x9C3E, 0xF743, 0x9C3F, 0xF744, 0x9C40, 0xF745, 0x9C41,
+	0xF746, 0x9C42, 0xF747, 0x9C43, 0xF748, 0x9C44, 0xF749, 0x9C45,	0xF74A, 0x9C46, 0xF74B, 0x9C47, 0xF74C, 0x9C48, 0xF74D, 0x9C49,
+	0xF74E, 0x9C4A, 0xF74F, 0x9C4B, 0xF750, 0x9C4C, 0xF751, 0x9C4D,	0xF752, 0x9C4E, 0xF753, 0x9C4F, 0xF754, 0x9C50, 0xF755, 0x9C51,
+	0xF756, 0x9C52, 0xF757, 0x9C53, 0xF758, 0x9C54, 0xF759, 0x9C55,	0xF75A, 0x9C56, 0xF75B, 0x9C57, 0xF75C, 0x9C58, 0xF75D, 0x9C59,
+	0xF75E, 0x9C5A, 0xF75F, 0x9C5B, 0xF760, 0x9C5C, 0xF761, 0x9C5D,	0xF762, 0x9C5E, 0xF763, 0x9C5F, 0xF764, 0x9C60, 0xF765, 0x9C61,
+	0xF766, 0x9C62, 0xF767, 0x9C63, 0xF768, 0x9C64, 0xF769, 0x9C65,	0xF76A, 0x9C66, 0xF76B, 0x9C67, 0xF76C, 0x9C68, 0xF76D, 0x9C69,
+	0xF76E, 0x9C6A, 0xF76F, 0x9C6B, 0xF770, 0x9C6C, 0xF771, 0x9C6D,	0xF772, 0x9C6E, 0xF773, 0x9C6F, 0xF774, 0x9C70, 0xF775, 0x9C71,
+	0xF776, 0x9C72, 0xF777, 0x9C73, 0xF778, 0x9C74, 0xF779, 0x9C75,	0xF77A, 0x9C76, 0xF77B, 0x9C77, 0xF77C, 0x9C78, 0xF77D, 0x9C79,
+	0xF77E, 0x9C7A, 0xF780, 0x9C7B, 0xF781, 0x9C7D, 0xF782, 0x9C7E,	0xF783, 0x9C80, 0xF784, 0x9C83, 0xF785, 0x9C84, 0xF786, 0x9C89,
+	0xF787, 0x9C8A, 0xF788, 0x9C8C, 0xF789, 0x9C8F, 0xF78A, 0x9C93,	0xF78B, 0x9C96, 0xF78C, 0x9C97, 0xF78D, 0x9C98, 0xF78E, 0x9C99,
+	0xF78F, 0x9C9D, 0xF790, 0x9CAA, 0xF791, 0x9CAC, 0xF792, 0x9CAF,	0xF793, 0x9CB9, 0xF794, 0x9CBE, 0xF795, 0x9CBF, 0xF796, 0x9CC0,
+	0xF797, 0x9CC1, 0xF798, 0x9CC2, 0xF799, 0x9CC8, 0xF79A, 0x9CC9,	0xF79B, 0x9CD1, 0xF79C, 0x9CD2, 0xF79D, 0x9CDA, 0xF79E, 0x9CDB,
+	0xF79F, 0x9CE0, 0xF7A0, 0x9CE1, 0xF7A1, 0x9CCC, 0xF7A2, 0x9CCD,	0xF7A3, 0x9CCE, 0xF7A4, 0x9CCF, 0xF7A5, 0x9CD0, 0xF7A6, 0x9CD3,
+	0xF7A7, 0x9CD4, 0xF7A8, 0x9CD5, 0xF7A9, 0x9CD7, 0xF7AA, 0x9CD8,	0xF7AB, 0x9CD9, 0xF7AC, 0x9CDC, 0xF7AD, 0x9CDD, 0xF7AE, 0x9CDF,
+	0xF7AF, 0x9CE2, 0xF7B0, 0x977C, 0xF7B1, 0x9785, 0xF7B2, 0x9791,	0xF7B3, 0x9792, 0xF7B4, 0x9794, 0xF7B5, 0x97AF, 0xF7B6, 0x97AB,
+	0xF7B7, 0x97A3, 0xF7B8, 0x97B2, 0xF7B9, 0x97B4, 0xF7BA, 0x9AB1,	0xF7BB, 0x9AB0, 0xF7BC, 0x9AB7, 0xF7BD, 0x9E58, 0xF7BE, 0x9AB6,
+	0xF7BF, 0x9ABA, 0xF7C0, 0x9ABC, 0xF7C1, 0x9AC1, 0xF7C2, 0x9AC0,	0xF7C3, 0x9AC5, 0xF7C4, 0x9AC2, 0xF7C5, 0x9ACB, 0xF7C6, 0x9ACC,
+	0xF7C7, 0x9AD1, 0xF7C8, 0x9B45, 0xF7C9, 0x9B43, 0xF7CA, 0x9B47,	0xF7CB, 0x9B49, 0xF7CC, 0x9B48, 0xF7CD, 0x9B4D, 0xF7CE, 0x9B51,
+	0xF7CF, 0x98E8, 0xF7D0, 0x990D, 0xF7D1, 0x992E, 0xF7D2, 0x9955,	0xF7D3, 0x9954, 0xF7D4, 0x9ADF, 0xF7D5, 0x9AE1, 0xF7D6, 0x9AE6,
+	0xF7D7, 0x9AEF, 0xF7D8, 0x9AEB, 0xF7D9, 0x9AFB, 0xF7DA, 0x9AED,	0xF7DB, 0x9AF9, 0xF7DC, 0x9B08, 0xF7DD, 0x9B0F, 0xF7DE, 0x9B13,
+	0xF7DF, 0x9B1F, 0xF7E0, 0x9B23, 0xF7E1, 0x9EBD, 0xF7E2, 0x9EBE,	0xF7E3, 0x7E3B, 0xF7E4, 0x9E82, 0xF7E5, 0x9E87, 0xF7E6, 0x9E88,
+	0xF7E7, 0x9E8B, 0xF7E8, 0x9E92, 0xF7E9, 0x93D6, 0xF7EA, 0x9E9D,	0xF7EB, 0x9E9F, 0xF7EC, 0x9EDB, 0xF7ED, 0x9EDC, 0xF7EE, 0x9EDD,
+	0xF7EF, 0x9EE0, 0xF7F0, 0x9EDF, 0xF7F1, 0x9EE2, 0xF7F2, 0x9EE9,	0xF7F3, 0x9EE7, 0xF7F4, 0x9EE5, 0xF7F5, 0x9EEA, 0xF7F6, 0x9EEF,
+	0xF7F7, 0x9F22, 0xF7F8, 0x9F2C, 0xF7F9, 0x9F2F, 0xF7FA, 0x9F39,	0xF7FB, 0x9F37, 0xF7FC, 0x9F3D, 0xF7FD, 0x9F3E, 0xF7FE, 0x9F44,
+	0xF840, 0x9CE3, 0xF841, 0x9CE4, 0xF842, 0x9CE5, 0xF843, 0x9CE6,	0xF844, 0x9CE7, 0xF845, 0x9CE8, 0xF846, 0x9CE9, 0xF847, 0x9CEA,
+	0xF848, 0x9CEB, 0xF849, 0x9CEC, 0xF84A, 0x9CED, 0xF84B, 0x9CEE,	0xF84C, 0x9CEF, 0xF84D, 0x9CF0, 0xF84E, 0x9CF1, 0xF84F, 0x9CF2,
+	0xF850, 0x9CF3, 0xF851, 0x9CF4, 0xF852, 0x9CF5, 0xF853, 0x9CF6,	0xF854, 0x9CF7, 0xF855, 0x9CF8, 0xF856, 0x9CF9, 0xF857, 0x9CFA,
+	0xF858, 0x9CFB, 0xF859, 0x9CFC, 0xF85A, 0x9CFD, 0xF85B, 0x9CFE,	0xF85C, 0x9CFF, 0xF85D, 0x9D00, 0xF85E, 0x9D01, 0xF85F, 0x9D02,
+	0xF860, 0x9D03, 0xF861, 0x9D04, 0xF862, 0x9D05, 0xF863, 0x9D06,	0xF864, 0x9D07, 0xF865, 0x9D08, 0xF866, 0x9D09, 0xF867, 0x9D0A,
+	0xF868, 0x9D0B, 0xF869, 0x9D0C, 0xF86A, 0x9D0D, 0xF86B, 0x9D0E,	0xF86C, 0x9D0F, 0xF86D, 0x9D10, 0xF86E, 0x9D11, 0xF86F, 0x9D12,
+	0xF870, 0x9D13, 0xF871, 0x9D14, 0xF872, 0x9D15, 0xF873, 0x9D16,	0xF874, 0x9D17, 0xF875, 0x9D18, 0xF876, 0x9D19, 0xF877, 0x9D1A,
+	0xF878, 0x9D1B, 0xF879, 0x9D1C, 0xF87A, 0x9D1D, 0xF87B, 0x9D1E,	0xF87C, 0x9D1F, 0xF87D, 0x9D20, 0xF87E, 0x9D21, 0xF880, 0x9D22,
+	0xF881, 0x9D23, 0xF882, 0x9D24, 0xF883, 0x9D25, 0xF884, 0x9D26,	0xF885, 0x9D27, 0xF886, 0x9D28, 0xF887, 0x9D29, 0xF888, 0x9D2A,
+	0xF889, 0x9D2B, 0xF88A, 0x9D2C, 0xF88B, 0x9D2D, 0xF88C, 0x9D2E,	0xF88D, 0x9D2F, 0xF88E, 0x9D30, 0xF88F, 0x9D31, 0xF890, 0x9D32,
+	0xF891, 0x9D33, 0xF892, 0x9D34, 0xF893, 0x9D35, 0xF894, 0x9D36,	0xF895, 0x9D37, 0xF896, 0x9D38, 0xF897, 0x9D39, 0xF898, 0x9D3A,
+	0xF899, 0x9D3B, 0xF89A, 0x9D3C, 0xF89B, 0x9D3D, 0xF89C, 0x9D3E,	0xF89D, 0x9D3F, 0xF89E, 0x9D40, 0xF89F, 0x9D41, 0xF8A0, 0x9D42,
+	0xF940, 0x9D43, 0xF941, 0x9D44, 0xF942, 0x9D45, 0xF943, 0x9D46,	0xF944, 0x9D47, 0xF945, 0x9D48, 0xF946, 0x9D49, 0xF947, 0x9D4A,
+	0xF948, 0x9D4B, 0xF949, 0x9D4C, 0xF94A, 0x9D4D, 0xF94B, 0x9D4E,	0xF94C, 0x9D4F, 0xF94D, 0x9D50, 0xF94E, 0x9D51, 0xF94F, 0x9D52,
+	0xF950, 0x9D53, 0xF951, 0x9D54, 0xF952, 0x9D55, 0xF953, 0x9D56,	0xF954, 0x9D57, 0xF955, 0x9D58, 0xF956, 0x9D59, 0xF957, 0x9D5A,
+	0xF958, 0x9D5B, 0xF959, 0x9D5C, 0xF95A, 0x9D5D, 0xF95B, 0x9D5E,	0xF95C, 0x9D5F, 0xF95D, 0x9D60, 0xF95E, 0x9D61, 0xF95F, 0x9D62,
+	0xF960, 0x9D63, 0xF961, 0x9D64, 0xF962, 0x9D65, 0xF963, 0x9D66,	0xF964, 0x9D67, 0xF965, 0x9D68, 0xF966, 0x9D69, 0xF967, 0x9D6A,
+	0xF968, 0x9D6B, 0xF969, 0x9D6C, 0xF96A, 0x9D6D, 0xF96B, 0x9D6E,	0xF96C, 0x9D6F, 0xF96D, 0x9D70, 0xF96E, 0x9D71, 0xF96F, 0x9D72,
+	0xF970, 0x9D73, 0xF971, 0x9D74, 0xF972, 0x9D75, 0xF973, 0x9D76,	0xF974, 0x9D77, 0xF975, 0x9D78, 0xF976, 0x9D79, 0xF977, 0x9D7A,
+	0xF978, 0x9D7B, 0xF979, 0x9D7C, 0xF97A, 0x9D7D, 0xF97B, 0x9D7E,	0xF97C, 0x9D7F, 0xF97D, 0x9D80, 0xF97E, 0x9D81, 0xF980, 0x9D82,
+	0xF981, 0x9D83, 0xF982, 0x9D84, 0xF983, 0x9D85, 0xF984, 0x9D86,	0xF985, 0x9D87, 0xF986, 0x9D88, 0xF987, 0x9D89, 0xF988, 0x9D8A,
+	0xF989, 0x9D8B, 0xF98A, 0x9D8C, 0xF98B, 0x9D8D, 0xF98C, 0x9D8E,	0xF98D, 0x9D8F, 0xF98E, 0x9D90, 0xF98F, 0x9D91, 0xF990, 0x9D92,
+	0xF991, 0x9D93, 0xF992, 0x9D94, 0xF993, 0x9D95, 0xF994, 0x9D96,	0xF995, 0x9D97, 0xF996, 0x9D98, 0xF997, 0x9D99, 0xF998, 0x9D9A,
+	0xF999, 0x9D9B, 0xF99A, 0x9D9C, 0xF99B, 0x9D9D, 0xF99C, 0x9D9E,	0xF99D, 0x9D9F, 0xF99E, 0x9DA0, 0xF99F, 0x9DA1, 0xF9A0, 0x9DA2,
+	0xFA40, 0x9DA3, 0xFA41, 0x9DA4, 0xFA42, 0x9DA5, 0xFA43, 0x9DA6,	0xFA44, 0x9DA7, 0xFA45, 0x9DA8, 0xFA46, 0x9DA9, 0xFA47, 0x9DAA,
+	0xFA48, 0x9DAB, 0xFA49, 0x9DAC, 0xFA4A, 0x9DAD, 0xFA4B, 0x9DAE,	0xFA4C, 0x9DAF, 0xFA4D, 0x9DB0, 0xFA4E, 0x9DB1, 0xFA4F, 0x9DB2,
+	0xFA50, 0x9DB3, 0xFA51, 0x9DB4, 0xFA52, 0x9DB5, 0xFA53, 0x9DB6,	0xFA54, 0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA,
+	0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE,	0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2,
+	0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6,	0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA,
+	0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE,	0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2,
+	0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6,	0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA,
+	0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE,	0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2,
+	0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6,	0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA,
+	0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE,	0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2,
+	0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6,	0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA,
+	0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE,	0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02,
+	0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06,	0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A,
+	0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E,	0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12,
+	0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16,	0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A,
+	0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E,	0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30,
+	0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40,	0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53,
+	0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D,	0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62,
+	0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72,	0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77,
+	0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B,	0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81,
+	0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86,	0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D,
+	0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91,	0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97,
+	0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B,	0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1,
+	0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5,	0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA,
+	0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE,	0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2,
+	0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7,	0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF,
+	0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3,	0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8,
+	0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0,	0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6,
+	0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE,	0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6,
+	0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED,	0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2,
+	0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6,	0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD,
+	0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02,	0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06,
+	0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A,	0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12,
+	0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18,	0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D,
+	0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23,	0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27,
+	0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B,	0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31,
+	0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35,	0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C,
+	0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42,	0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47,
+	0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B,	0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F,
+	0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55,	0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59,
+	0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D,	0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61,
+	0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65,	0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69,
+	0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D,	0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71,
+	0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75,	0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79,
+	0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D,	0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D,
+	0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91,	0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95,
+	0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C,	0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2,
+	0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C,	0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1,
+	0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F,	0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18,
+	0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23,	0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29,
+	0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0	/* Korean */
+static const WCHAR uni2oem949[] = {	/* Unicode --> Korean pairs */
+	0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7,	0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6,
+	0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5,	0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6,
+	0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA,	0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF,
+	0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1,	0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD,
+	0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5,	0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8,
+	0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0,	0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB,
+	0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0,	0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD,
+	0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3,	0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7,
+	0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB,	0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF,
+	0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3,	0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7,
+	0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3,	0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7,
+	0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB,	0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF,
+	0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3,	0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7,
+	0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2,	0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6,
+	0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB,	0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF,
+	0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3,	0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7,
+	0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB,	0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF,
+	0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2,	0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6,
+	0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB,	0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF,
+	0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3,	0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7,
+	0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB,	0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF,
+	0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA,	0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1,
+	0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6,	0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8,
+	0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC,	0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9,
+	0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5,	0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7,
+	0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD,	0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2,
+	0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6,	0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1,
+	0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5,	0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9,
+	0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6,	0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8,
+	0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1,	0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4,
+	0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3,	0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4,
+	0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD,	0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3,
+	0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD,	0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5,
+	0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED,	0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7,
+	0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7,	0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB,
+	0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF,	0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3,
+	0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8,	0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC,
+	0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0,	0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4,
+	0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF,	0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3,
+	0x24A3, 0xA9D4, 0x24A4, 0xA9D5, 0x24A5, 0xA9D6, 0x24A6, 0xA9D7,	0x24A7, 0xA9D8, 0x24A8, 0xA9D9, 0x24A9, 0xA9DA, 0x24AA, 0xA9DB,
+	0x24AB, 0xA9DC, 0x24AC, 0xA9DD, 0x24AD, 0xA9DE, 0x24AE, 0xA9DF,	0x24AF, 0xA9E0, 0x24B0, 0xA9E1, 0x24B1, 0xA9E2, 0x24B2, 0xA9E3,
+	0x24B3, 0xA9E4, 0x24B4, 0xA9E5, 0x24B5, 0xA9E6, 0x24D0, 0xA8CD,	0x24D1, 0xA8CE, 0x24D2, 0xA8CF, 0x24D3, 0xA8D0, 0x24D4, 0xA8D1,
+	0x24D5, 0xA8D2, 0x24D6, 0xA8D3, 0x24D7, 0xA8D4, 0x24D8, 0xA8D5,	0x24D9, 0xA8D6, 0x24DA, 0xA8D7, 0x24DB, 0xA8D8, 0x24DC, 0xA8D9,
+	0x24DD, 0xA8DA, 0x24DE, 0xA8DB, 0x24DF, 0xA8DC, 0x24E0, 0xA8DD,	0x24E1, 0xA8DE, 0x24E2, 0xA8DF, 0x24E3, 0xA8E0, 0x24E4, 0xA8E1,
+	0x24E5, 0xA8E2, 0x24E6, 0xA8E3, 0x24E7, 0xA8E4, 0x24E8, 0xA8E5,	0x24E9, 0xA8E6, 0x2500, 0xA6A1, 0x2501, 0xA6AC, 0x2502, 0xA6A2,
+	0x2503, 0xA6AD, 0x250C, 0xA6A3, 0x250D, 0xA6C8, 0x250E, 0xA6C7,	0x250F, 0xA6AE, 0x2510, 0xA6A4, 0x2511, 0xA6C2, 0x2512, 0xA6C1,
+	0x2513, 0xA6AF, 0x2514, 0xA6A6, 0x2515, 0xA6C6, 0x2516, 0xA6C5,	0x2517, 0xA6B1, 0x2518, 0xA6A5, 0x2519, 0xA6C4, 0x251A, 0xA6C3,
+	0x251B, 0xA6B0, 0x251C, 0xA6A7, 0x251D, 0xA6BC, 0x251E, 0xA6C9,	0x251F, 0xA6CA, 0x2520, 0xA6B7, 0x2521, 0xA6CB, 0x2522, 0xA6CC,
+	0x2523, 0xA6B2, 0x2524, 0xA6A9, 0x2525, 0xA6BE, 0x2526, 0xA6CD,	0x2527, 0xA6CE, 0x2528, 0xA6B9, 0x2529, 0xA6CF, 0x252A, 0xA6D0,
+	0x252B, 0xA6B4, 0x252C, 0xA6A8, 0x252D, 0xA6D1, 0x252E, 0xA6D2,	0x252F, 0xA6B8, 0x2530, 0xA6BD, 0x2531, 0xA6D3, 0x2532, 0xA6D4,
+	0x2533, 0xA6B3, 0x2534, 0xA6AA, 0x2535, 0xA6D5, 0x2536, 0xA6D6,	0x2537, 0xA6BA, 0x2538, 0xA6BF, 0x2539, 0xA6D7, 0x253A, 0xA6D8,
+	0x253B, 0xA6B5, 0x253C, 0xA6AB, 0x253D, 0xA6D9, 0x253E, 0xA6DA,	0x253F, 0xA6BB, 0x2540, 0xA6DB, 0x2541, 0xA6DC, 0x2542, 0xA6C0,
+	0x2543, 0xA6DD, 0x2544, 0xA6DE, 0x2545, 0xA6DF, 0x2546, 0xA6E0,	0x2547, 0xA6E1, 0x2548, 0xA6E2, 0x2549, 0xA6E3, 0x254A, 0xA6E4,
+	0x254B, 0xA6B6, 0x2592, 0xA2C6, 0x25A0, 0xA1E1, 0x25A1, 0xA1E0,	0x25A3, 0xA2C3, 0x25A4, 0xA2C7, 0x25A5, 0xA2C8, 0x25A6, 0xA2CB,
+	0x25A7, 0xA2CA, 0x25A8, 0xA2C9, 0x25A9, 0xA2CC, 0x25B2, 0xA1E3,	0x25B3, 0xA1E2, 0x25B6, 0xA2BA, 0x25B7, 0xA2B9, 0x25BC, 0xA1E5,
+	0x25BD, 0xA1E4, 0x25C0, 0xA2B8, 0x25C1, 0xA2B7, 0x25C6, 0xA1DF,	0x25C7, 0xA1DE, 0x25C8, 0xA2C2, 0x25CB, 0xA1DB, 0x25CE, 0xA1DD,
+	0x25CF, 0xA1DC, 0x25D0, 0xA2C4, 0x25D1, 0xA2C5, 0x2605, 0xA1DA,	0x2606, 0xA1D9, 0x260E, 0xA2CF, 0x260F, 0xA2CE, 0x261C, 0xA2D0,
+	0x261E, 0xA2D1, 0x2640, 0xA1CF, 0x2642, 0xA1CE, 0x2660, 0xA2BC,	0x2661, 0xA2BD, 0x2663, 0xA2C0, 0x2664, 0xA2BB, 0x2665, 0xA2BE,
+	0x2667, 0xA2BF, 0x2668, 0xA2CD, 0x2669, 0xA2DB, 0x266A, 0xA2DC,	0x266C, 0xA2DD, 0x266D, 0xA2DA, 0x3000, 0xA1A1, 0x3001, 0xA1A2,
+	0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3008, 0xA1B4, 0x3009, 0xA1B5,	0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9,
+	0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BC, 0x3011, 0xA1BD,	0x3013, 0xA1EB, 0x3014, 0xA1B2, 0x3015, 0xA1B3, 0x3041, 0xAAA1,
+	0x3042, 0xAAA2, 0x3043, 0xAAA3, 0x3044, 0xAAA4, 0x3045, 0xAAA5,	0x3046, 0xAAA6, 0x3047, 0xAAA7, 0x3048, 0xAAA8, 0x3049, 0xAAA9,
+	0x304A, 0xAAAA, 0x304B, 0xAAAB, 0x304C, 0xAAAC, 0x304D, 0xAAAD,	0x304E, 0xAAAE, 0x304F, 0xAAAF, 0x3050, 0xAAB0, 0x3051, 0xAAB1,
+	0x3052, 0xAAB2, 0x3053, 0xAAB3, 0x3054, 0xAAB4, 0x3055, 0xAAB5,	0x3056, 0xAAB6, 0x3057, 0xAAB7, 0x3058, 0xAAB8, 0x3059, 0xAAB9,
+	0x305A, 0xAABA, 0x305B, 0xAABB, 0x305C, 0xAABC, 0x305D, 0xAABD,	0x305E, 0xAABE, 0x305F, 0xAABF, 0x3060, 0xAAC0, 0x3061, 0xAAC1,
+	0x3062, 0xAAC2, 0x3063, 0xAAC3, 0x3064, 0xAAC4, 0x3065, 0xAAC5,	0x3066, 0xAAC6, 0x3067, 0xAAC7, 0x3068, 0xAAC8, 0x3069, 0xAAC9,
+	0x306A, 0xAACA, 0x306B, 0xAACB, 0x306C, 0xAACC, 0x306D, 0xAACD,	0x306E, 0xAACE, 0x306F, 0xAACF, 0x3070, 0xAAD0, 0x3071, 0xAAD1,
+	0x3072, 0xAAD2, 0x3073, 0xAAD3, 0x3074, 0xAAD4, 0x3075, 0xAAD5,	0x3076, 0xAAD6, 0x3077, 0xAAD7, 0x3078, 0xAAD8, 0x3079, 0xAAD9,
+	0x307A, 0xAADA, 0x307B, 0xAADB, 0x307C, 0xAADC, 0x307D, 0xAADD,	0x307E, 0xAADE, 0x307F, 0xAADF, 0x3080, 0xAAE0, 0x3081, 0xAAE1,
+	0x3082, 0xAAE2, 0x3083, 0xAAE3, 0x3084, 0xAAE4, 0x3085, 0xAAE5,	0x3086, 0xAAE6, 0x3087, 0xAAE7, 0x3088, 0xAAE8, 0x3089, 0xAAE9,
+	0x308A, 0xAAEA, 0x308B, 0xAAEB, 0x308C, 0xAAEC, 0x308D, 0xAAED,	0x308E, 0xAAEE, 0x308F, 0xAAEF, 0x3090, 0xAAF0, 0x3091, 0xAAF1,
+	0x3092, 0xAAF2, 0x3093, 0xAAF3, 0x30A1, 0xABA1, 0x30A2, 0xABA2,	0x30A3, 0xABA3, 0x30A4, 0xABA4, 0x30A5, 0xABA5, 0x30A6, 0xABA6,
+	0x30A7, 0xABA7, 0x30A8, 0xABA8, 0x30A9, 0xABA9, 0x30AA, 0xABAA,	0x30AB, 0xABAB, 0x30AC, 0xABAC, 0x30AD, 0xABAD, 0x30AE, 0xABAE,
+	0x30AF, 0xABAF, 0x30B0, 0xABB0, 0x30B1, 0xABB1, 0x30B2, 0xABB2,	0x30B3, 0xABB3, 0x30B4, 0xABB4, 0x30B5, 0xABB5, 0x30B6, 0xABB6,
+	0x30B7, 0xABB7, 0x30B8, 0xABB8, 0x30B9, 0xABB9, 0x30BA, 0xABBA,	0x30BB, 0xABBB, 0x30BC, 0xABBC, 0x30BD, 0xABBD, 0x30BE, 0xABBE,
+	0x30BF, 0xABBF, 0x30C0, 0xABC0, 0x30C1, 0xABC1, 0x30C2, 0xABC2,	0x30C3, 0xABC3, 0x30C4, 0xABC4, 0x30C5, 0xABC5, 0x30C6, 0xABC6,
+	0x30C7, 0xABC7, 0x30C8, 0xABC8, 0x30C9, 0xABC9, 0x30CA, 0xABCA,	0x30CB, 0xABCB, 0x30CC, 0xABCC, 0x30CD, 0xABCD, 0x30CE, 0xABCE,
+	0x30CF, 0xABCF, 0x30D0, 0xABD0, 0x30D1, 0xABD1, 0x30D2, 0xABD2,	0x30D3, 0xABD3, 0x30D4, 0xABD4, 0x30D5, 0xABD5, 0x30D6, 0xABD6,
+	0x30D7, 0xABD7, 0x30D8, 0xABD8, 0x30D9, 0xABD9, 0x30DA, 0xABDA,	0x30DB, 0xABDB, 0x30DC, 0xABDC, 0x30DD, 0xABDD, 0x30DE, 0xABDE,
+	0x30DF, 0xABDF, 0x30E0, 0xABE0, 0x30E1, 0xABE1, 0x30E2, 0xABE2,	0x30E3, 0xABE3, 0x30E4, 0xABE4, 0x30E5, 0xABE5, 0x30E6, 0xABE6,
+	0x30E7, 0xABE7, 0x30E8, 0xABE8, 0x30E9, 0xABE9, 0x30EA, 0xABEA,	0x30EB, 0xABEB, 0x30EC, 0xABEC, 0x30ED, 0xABED, 0x30EE, 0xABEE,
+	0x30EF, 0xABEF, 0x30F0, 0xABF0, 0x30F1, 0xABF1, 0x30F2, 0xABF2,	0x30F3, 0xABF3, 0x30F4, 0xABF4, 0x30F5, 0xABF5, 0x30F6, 0xABF6,
+	0x3131, 0xA4A1, 0x3132, 0xA4A2, 0x3133, 0xA4A3, 0x3134, 0xA4A4,	0x3135, 0xA4A5, 0x3136, 0xA4A6, 0x3137, 0xA4A7, 0x3138, 0xA4A8,
+	0x3139, 0xA4A9, 0x313A, 0xA4AA, 0x313B, 0xA4AB, 0x313C, 0xA4AC,	0x313D, 0xA4AD, 0x313E, 0xA4AE, 0x313F, 0xA4AF, 0x3140, 0xA4B0,
+	0x3141, 0xA4B1, 0x3142, 0xA4B2, 0x3143, 0xA4B3, 0x3144, 0xA4B4,	0x3145, 0xA4B5, 0x3146, 0xA4B6, 0x3147, 0xA4B7, 0x3148, 0xA4B8,
+	0x3149, 0xA4B9, 0x314A, 0xA4BA, 0x314B, 0xA4BB, 0x314C, 0xA4BC,	0x314D, 0xA4BD, 0x314E, 0xA4BE, 0x314F, 0xA4BF, 0x3150, 0xA4C0,
+	0x3151, 0xA4C1, 0x3152, 0xA4C2, 0x3153, 0xA4C3, 0x3154, 0xA4C4,	0x3155, 0xA4C5, 0x3156, 0xA4C6, 0x3157, 0xA4C7, 0x3158, 0xA4C8,
+	0x3159, 0xA4C9, 0x315A, 0xA4CA, 0x315B, 0xA4CB, 0x315C, 0xA4CC,	0x315D, 0xA4CD, 0x315E, 0xA4CE, 0x315F, 0xA4CF, 0x3160, 0xA4D0,
+	0x3161, 0xA4D1, 0x3162, 0xA4D2, 0x3163, 0xA4D3, 0x3164, 0xA4D4,	0x3165, 0xA4D5, 0x3166, 0xA4D6, 0x3167, 0xA4D7, 0x3168, 0xA4D8,
+	0x3169, 0xA4D9, 0x316A, 0xA4DA, 0x316B, 0xA4DB, 0x316C, 0xA4DC,	0x316D, 0xA4DD, 0x316E, 0xA4DE, 0x316F, 0xA4DF, 0x3170, 0xA4E0,
+	0x3171, 0xA4E1, 0x3172, 0xA4E2, 0x3173, 0xA4E3, 0x3174, 0xA4E4,	0x3175, 0xA4E5, 0x3176, 0xA4E6, 0x3177, 0xA4E7, 0x3178, 0xA4E8,
+	0x3179, 0xA4E9, 0x317A, 0xA4EA, 0x317B, 0xA4EB, 0x317C, 0xA4EC,	0x317D, 0xA4ED, 0x317E, 0xA4EE, 0x317F, 0xA4EF, 0x3180, 0xA4F0,
+	0x3181, 0xA4F1, 0x3182, 0xA4F2, 0x3183, 0xA4F3, 0x3184, 0xA4F4,	0x3185, 0xA4F5, 0x3186, 0xA4F6, 0x3187, 0xA4F7, 0x3188, 0xA4F8,
+	0x3189, 0xA4F9, 0x318A, 0xA4FA, 0x318B, 0xA4FB, 0x318C, 0xA4FC,	0x318D, 0xA4FD, 0x318E, 0xA4FE, 0x3200, 0xA9B1, 0x3201, 0xA9B2,
+	0x3202, 0xA9B3, 0x3203, 0xA9B4, 0x3204, 0xA9B5, 0x3205, 0xA9B6,	0x3206, 0xA9B7, 0x3207, 0xA9B8, 0x3208, 0xA9B9, 0x3209, 0xA9BA,
+	0x320A, 0xA9BB, 0x320B, 0xA9BC, 0x320C, 0xA9BD, 0x320D, 0xA9BE,	0x320E, 0xA9BF, 0x320F, 0xA9C0, 0x3210, 0xA9C1, 0x3211, 0xA9C2,
+	0x3212, 0xA9C3, 0x3213, 0xA9C4, 0x3214, 0xA9C5, 0x3215, 0xA9C6,	0x3216, 0xA9C7, 0x3217, 0xA9C8, 0x3218, 0xA9C9, 0x3219, 0xA9CA,
+	0x321A, 0xA9CB, 0x321B, 0xA9CC, 0x321C, 0xA2DF, 0x3260, 0xA8B1,	0x3261, 0xA8B2, 0x3262, 0xA8B3, 0x3263, 0xA8B4, 0x3264, 0xA8B5,
+	0x3265, 0xA8B6, 0x3266, 0xA8B7, 0x3267, 0xA8B8, 0x3268, 0xA8B9,	0x3269, 0xA8BA, 0x326A, 0xA8BB, 0x326B, 0xA8BC, 0x326C, 0xA8BD,
+	0x326D, 0xA8BE, 0x326E, 0xA8BF, 0x326F, 0xA8C0, 0x3270, 0xA8C1,	0x3271, 0xA8C2, 0x3272, 0xA8C3, 0x3273, 0xA8C4, 0x3274, 0xA8C5,
+	0x3275, 0xA8C6, 0x3276, 0xA8C7, 0x3277, 0xA8C8, 0x3278, 0xA8C9,	0x3279, 0xA8CA, 0x327A, 0xA8CB, 0x327B, 0xA8CC, 0x327F, 0xA2DE,
+	0x3380, 0xA7C9, 0x3381, 0xA7CA, 0x3382, 0xA7CB, 0x3383, 0xA7CC,	0x3384, 0xA7CD, 0x3388, 0xA7BA, 0x3389, 0xA7BB, 0x338A, 0xA7DC,
+	0x338B, 0xA7DD, 0x338C, 0xA7DE, 0x338D, 0xA7B6, 0x338E, 0xA7B7,	0x338F, 0xA7B8, 0x3390, 0xA7D4, 0x3391, 0xA7D5, 0x3392, 0xA7D6,
+	0x3393, 0xA7D7, 0x3394, 0xA7D8, 0x3395, 0xA7A1, 0x3396, 0xA7A2,	0x3397, 0xA7A3, 0x3398, 0xA7A5, 0x3399, 0xA7AB, 0x339A, 0xA7AC,
+	0x339B, 0xA7AD, 0x339C, 0xA7AE, 0x339D, 0xA7AF, 0x339E, 0xA7B0,	0x339F, 0xA7B1, 0x33A0, 0xA7B2, 0x33A1, 0xA7B3, 0x33A2, 0xA7B4,
+	0x33A3, 0xA7A7, 0x33A4, 0xA7A8, 0x33A5, 0xA7A9, 0x33A6, 0xA7AA,	0x33A7, 0xA7BD, 0x33A8, 0xA7BE, 0x33A9, 0xA7E5, 0x33AA, 0xA7E6,
+	0x33AB, 0xA7E7, 0x33AC, 0xA7E8, 0x33AD, 0xA7E1, 0x33AE, 0xA7E2,	0x33AF, 0xA7E3, 0x33B0, 0xA7BF, 0x33B1, 0xA7C0, 0x33B2, 0xA7C1,
+	0x33B3, 0xA7C2, 0x33B4, 0xA7C3, 0x33B5, 0xA7C4, 0x33B6, 0xA7C5,	0x33B7, 0xA7C6, 0x33B8, 0xA7C7, 0x33B9, 0xA7C8, 0x33BA, 0xA7CE,
+	0x33BB, 0xA7CF, 0x33BC, 0xA7D0, 0x33BD, 0xA7D1, 0x33BE, 0xA7D2,	0x33BF, 0xA7D3, 0x33C0, 0xA7DA, 0x33C1, 0xA7DB, 0x33C2, 0xA2E3,
+	0x33C3, 0xA7EC, 0x33C4, 0xA7A6, 0x33C5, 0xA7E0, 0x33C6, 0xA7EF,	0x33C7, 0xA2E1, 0x33C8, 0xA7BC, 0x33C9, 0xA7ED, 0x33CA, 0xA7B5,
+	0x33CF, 0xA7B9, 0x33D0, 0xA7EA, 0x33D3, 0xA7EB, 0x33D6, 0xA7DF,	0x33D8, 0xA2E4, 0x33DB, 0xA7E4, 0x33DC, 0xA7EE, 0x33DD, 0xA7E9,
+	0x4E00, 0xECE9, 0x4E01, 0xEFCB, 0x4E03, 0xF6D2, 0x4E07, 0xD8B2,	0x4E08, 0xEDDB, 0x4E09, 0xDFB2, 0x4E0A, 0xDFBE, 0x4E0B, 0xF9BB,
+	0x4E0D, 0xDCF4, 0x4E11, 0xF5E4, 0x4E14, 0xF3A6, 0x4E15, 0xDDE0,	0x4E16, 0xE1A6, 0x4E18, 0xCEF8, 0x4E19, 0xDCB0, 0x4E1E, 0xE3AA,
+	0x4E2D, 0xF1E9, 0x4E32, 0xCDFA, 0x4E38, 0xFCAF, 0x4E39, 0xD3A1,	0x4E3B, 0xF1AB, 0x4E42, 0xE7D1, 0x4E43, 0xD2AC, 0x4E45, 0xCEF9,
+	0x4E4B, 0xF1FD, 0x4E4D, 0xDEBF, 0x4E4E, 0xFBBA, 0x4E4F, 0xF9B9,	0x4E56, 0xCED2, 0x4E58, 0xE3AB, 0x4E59, 0xEBE0, 0x4E5D, 0xCEFA,
+	0x4E5E, 0xCBF7, 0x4E5F, 0xE5A5, 0x4E6B, 0xCAE1, 0x4E6D, 0xD4CC,	0x4E73, 0xEAE1, 0x4E76, 0xDCE3, 0x4E77, 0xDFAD, 0x4E7E, 0xCBEB,
+	0x4E82, 0xD5AF, 0x4E86, 0xD6F5, 0x4E88, 0xE5F8, 0x4E8B, 0xDEC0,	0x4E8C, 0xECA3, 0x4E8E, 0xE9CD, 0x4E90, 0xEAA7, 0x4E91, 0xE9F6,
+	0x4E92, 0xFBBB, 0x4E94, 0xE7E9, 0x4E95, 0xEFCC, 0x4E98, 0xD0E6,	0x4E9B, 0xDEC1, 0x4E9E, 0xE4AC, 0x4EA1, 0xD8CC, 0x4EA2, 0xF9F1,
+	0x4EA4, 0xCEDF, 0x4EA5, 0xFAA4, 0x4EA6, 0xE6B2, 0x4EA8, 0xFAFB,	0x4EAB, 0xFABD, 0x4EAC, 0xCCC8, 0x4EAD, 0xEFCD, 0x4EAE, 0xD5D5,
+	0x4EB6, 0xD3A2, 0x4EBA, 0xECD1, 0x4EC0, 0xE4A7, 0x4EC1, 0xECD2,	0x4EC4, 0xF6B1, 0x4EC7, 0xCEFB, 0x4ECA, 0xD0D1, 0x4ECB, 0xCBBF,
+	0x4ECD, 0xEDA4, 0x4ED4, 0xEDA8, 0x4ED5, 0xDEC2, 0x4ED6, 0xF6E2,	0x4ED7, 0xEDDC, 0x4ED8, 0xDCF5, 0x4ED9, 0xE0B9, 0x4EDD, 0xD4CE,
+	0x4EDF, 0xF4B5, 0x4EE3, 0xD3DB, 0x4EE4, 0xD6B5, 0x4EE5, 0xECA4,	0x4EF0, 0xE4E6, 0x4EF2, 0xF1EA, 0x4EF6, 0xCBEC, 0x4EF7, 0xCBC0,
+	0x4EFB, 0xECF2, 0x4F01, 0xD0EA, 0x4F09, 0xF9F2, 0x4F0A, 0xECA5,	0x4F0B, 0xD0DF, 0x4F0D, 0xE7EA, 0x4F0E, 0xD0EB, 0x4F0F, 0xDCD1,
+	0x4F10, 0xDBE9, 0x4F11, 0xFDCC, 0x4F2F, 0xDBD7, 0x4F34, 0xDAE1,	0x4F36, 0xD6B6, 0x4F38, 0xE3DF, 0x4F3A, 0xDEC3, 0x4F3C, 0xDEC4,
+	0x4F3D, 0xCAA1, 0x4F43, 0xEEEC, 0x4F46, 0xD3A3, 0x4F47, 0xEEB7,	0x4F48, 0xF8CF, 0x4F4D, 0xEAC8, 0x4F4E, 0xEEB8, 0x4F4F, 0xF1AC,
+	0x4F50, 0xF1A5, 0x4F51, 0xE9CE, 0x4F55, 0xF9BC, 0x4F59, 0xE5F9,	0x4F5A, 0xECEA, 0x4F5B, 0xDDD6, 0x4F5C, 0xEDC2, 0x4F69, 0xF8A5,
+	0x4F6F, 0xE5BA, 0x4F70, 0xDBD8, 0x4F73, 0xCAA2, 0x4F76, 0xD1CD,	0x4F7A, 0xEEED, 0x4F7E, 0xECEB, 0x4F7F, 0xDEC5, 0x4F81, 0xE3E0,
+	0x4F83, 0xCAC9, 0x4F84, 0xF2E9, 0x4F86, 0xD5CE, 0x4F88, 0xF6B6,	0x4F8A, 0xCEC2, 0x4F8B, 0xD6C7, 0x4F8D, 0xE3B4, 0x4F8F, 0xF1AD,
+	0x4F91, 0xEAE2, 0x4F96, 0xD7C2, 0x4F98, 0xF3A7, 0x4F9B, 0xCDEA,	0x4F9D, 0xEBEE, 0x4FAE, 0xD9B2, 0x4FAF, 0xFDA5, 0x4FB5, 0xF6D5,
+	0x4FB6, 0xD5E2, 0x4FBF, 0xF8B5, 0x4FC2, 0xCCF5, 0x4FC3, 0xF5B5,	0x4FC4, 0xE4AD, 0x4FC9, 0xE7EB, 0x4FCA, 0xF1D5, 0x4FCE, 0xF0BB,
+	0x4FD1, 0xE9B5, 0x4FD3, 0xCCC9, 0x4FD4, 0xFAD5, 0x4FD7, 0xE1D4,	0x4FDA, 0xD7D6, 0x4FDD, 0xDCC1, 0x4FDF, 0xDEC6, 0x4FE0, 0xFAEF,
+	0x4FE1, 0xE3E1, 0x4FEE, 0xE1F3, 0x4FEF, 0xDCF6, 0x4FF1, 0xCEFC,	0x4FF3, 0xDBC4, 0x4FF5, 0xF8F1, 0x4FF8, 0xDCE4, 0x4FFA, 0xE5EF,
+	0x5002, 0xDCB1, 0x5006, 0xD5D6, 0x5009, 0xF3DA, 0x500B, 0xCBC1,	0x500D, 0xDBC3, 0x5011, 0xD9FA, 0x5012, 0xD3EE, 0x5016, 0xFAB8,
+	0x5019, 0xFDA6, 0x501A, 0xEBEF, 0x501C, 0xF4A6, 0x501E, 0xCCCA,	0x501F, 0xF3A8, 0x5021, 0xF3DB, 0x5023, 0xDBA7, 0x5024, 0xF6B7,
+	0x5026, 0xCFE6, 0x5027, 0xF0F2, 0x5028, 0xCBDA, 0x502A, 0xE7D2,	0x502B, 0xD7C3, 0x502C, 0xF6F0, 0x502D, 0xE8DE, 0x503B, 0xE5A6,
+	0x5043, 0xE5E7, 0x5047, 0xCAA3, 0x5048, 0xCCA7, 0x5049, 0xEAC9,	0x504F, 0xF8B6, 0x5055, 0xFAA5, 0x505A, 0xF1AE, 0x505C, 0xEFCE,
+	0x5065, 0xCBED, 0x5074, 0xF6B0, 0x5075, 0xEFCF, 0x5076, 0xE9CF,	0x5078, 0xF7DE, 0x5080, 0xCED3, 0x5085, 0xDCF7, 0x508D, 0xDBA8,
+	0x5091, 0xCBF8, 0x5098, 0xDFA1, 0x5099, 0xDDE1, 0x50AC, 0xF5CA,	0x50AD, 0xE9B6, 0x50B2, 0xE7EC, 0x50B3, 0xEEEE, 0x50B5, 0xF3F0,
+	0x50B7, 0xDFBF, 0x50BE, 0xCCCB, 0x50C5, 0xD0C1, 0x50C9, 0xF4D2,	0x50CA, 0xE0BA, 0x50CF, 0xDFC0, 0x50D1, 0xCEE0, 0x50D5, 0xDCD2,
+	0x50D6, 0xFDEA, 0x50DA, 0xD6F6, 0x50DE, 0xEACA, 0x50E5, 0xE8E9,	0x50E7, 0xE3AC, 0x50ED, 0xF3D0, 0x50F9, 0xCAA4, 0x50FB, 0xDBF8,
+	0x50FF, 0xDEC7, 0x5100, 0xEBF0, 0x5101, 0xF1D6, 0x5104, 0xE5E2,	0x5106, 0xCCCC, 0x5109, 0xCBFB, 0x5112, 0xEAE3, 0x511F, 0xDFC1,
+	0x5121, 0xD6ED, 0x512A, 0xE9D0, 0x5132, 0xEEB9, 0x5137, 0xD5E3,	0x513A, 0xD1D3, 0x513C, 0xE5F0, 0x5140, 0xE8B4, 0x5141, 0xEBC3,
+	0x5143, 0xEAAA, 0x5144, 0xFAFC, 0x5145, 0xF5F6, 0x5146, 0xF0BC,	0x5147, 0xFDD4, 0x5148, 0xE0BB, 0x5149, 0xCEC3, 0x514B, 0xD0BA,
+	0x514C, 0xF7BA, 0x514D, 0xD8F3, 0x514E, 0xF7CD, 0x5152, 0xE4AE,	0x515C, 0xD4DF, 0x5162, 0xD0E7, 0x5165, 0xECFD, 0x5167, 0xD2AE,
+	0x5168, 0xEEEF, 0x5169, 0xD5D7, 0x516A, 0xEAE4, 0x516B, 0xF8A2,	0x516C, 0xCDEB, 0x516D, 0xD7BF, 0x516E, 0xFBB1, 0x5171, 0xCDEC,
+	0x5175, 0xDCB2, 0x5176, 0xD0EC, 0x5177, 0xCEFD, 0x5178, 0xEEF0,	0x517C, 0xCCC2, 0x5180, 0xD0ED, 0x5186, 0xE5F7, 0x518A, 0xF3FC,
+	0x518D, 0xEEA2, 0x5192, 0xD9B3, 0x5195, 0xD8F4, 0x5197, 0xE9B7,	0x51A0, 0xCEAE, 0x51A5, 0xD9A2, 0x51AA, 0xD8F1, 0x51AC, 0xD4CF,
+	0x51B6, 0xE5A7, 0x51B7, 0xD5D2, 0x51BD, 0xD6A9, 0x51C4, 0xF4A2,	0x51C6, 0xF1D7, 0x51C9, 0xD5D8, 0x51CB, 0xF0BD, 0x51CC, 0xD7D0,
+	0x51CD, 0xD4D0, 0x51DC, 0xD7CF, 0x51DD, 0xEBEA, 0x51DE, 0xFDEB,	0x51E1, 0xDBED, 0x51F0, 0xFCC5, 0x51F1, 0xCBC2, 0x51F6, 0xFDD5,
+	0x51F8, 0xF4C8, 0x51F9, 0xE8EA, 0x51FA, 0xF5F3, 0x51FD, 0xF9DE,	0x5200, 0xD3EF, 0x5203, 0xECD3, 0x5206, 0xDDC2, 0x5207, 0xEFB7,
+	0x5208, 0xE7D4, 0x520A, 0xCACA, 0x520E, 0xD9FB, 0x5211, 0xFAFD,	0x5217, 0xD6AA, 0x521D, 0xF4F8, 0x5224, 0xF7F7, 0x5225, 0xDCAC,
+	0x5229, 0xD7D7, 0x522A, 0xDFA2, 0x522E, 0xCEBE, 0x5230, 0xD3F0,	0x5236, 0xF0A4, 0x5237, 0xE1EC, 0x5238, 0xCFE7, 0x5239, 0xF3CB,
+	0x523A, 0xEDA9, 0x523B, 0xCABE, 0x5243, 0xF4EF, 0x5247, 0xF6CE,	0x524A, 0xDEFB, 0x524B, 0xD0BB, 0x524C, 0xD5B7, 0x524D, 0xEEF1,
+	0x5254, 0xF4A8, 0x5256, 0xDCF8, 0x525B, 0xCBA7, 0x525D, 0xDACE,	0x5261, 0xE0E6, 0x5269, 0xEDA5, 0x526A, 0xEEF2, 0x526F, 0xDCF9,
+	0x5272, 0xF9DC, 0x5275, 0xF3DC, 0x527D, 0xF8F2, 0x527F, 0xF4F9,	0x5283, 0xFCF1, 0x5287, 0xD0BC, 0x5288, 0xDBF9, 0x5289, 0xD7B1,
+	0x528D, 0xCBFC, 0x5291, 0xF0A5, 0x5292, 0xCBFD, 0x529B, 0xD5F4,	0x529F, 0xCDED, 0x52A0, 0xCAA5, 0x52A3, 0xD6AB, 0x52A4, 0xD0C2,
+	0x52A9, 0xF0BE, 0x52AA, 0xD2BD, 0x52AB, 0xCCA4, 0x52BE, 0xFAB6,	0x52C1, 0xCCCD, 0x52C3, 0xDAFA, 0x52C5, 0xF6CF, 0x52C7, 0xE9B8,
+	0x52C9, 0xD8F5, 0x52CD, 0xCCCE, 0x52D2, 0xD7CD, 0x52D5, 0xD4D1,	0x52D6, 0xE9ED, 0x52D8, 0xCAEB, 0x52D9, 0xD9E2, 0x52DB, 0xFDB2,
+	0x52DD, 0xE3AD, 0x52DE, 0xD6CC, 0x52DF, 0xD9B4, 0x52E2, 0xE1A7,	0x52E3, 0xEED3, 0x52E4, 0xD0C3, 0x52F3, 0xFDB3, 0x52F5, 0xD5E4,
+	0x52F8, 0xCFE8, 0x52FA, 0xEDC3, 0x52FB, 0xD0B2, 0x52FE, 0xCEFE,	0x52FF, 0xDAA8, 0x5305, 0xF8D0, 0x5308, 0xFDD6, 0x530D, 0xF8D1,
+	0x530F, 0xF8D2, 0x5310, 0xDCD3, 0x5315, 0xDDE2, 0x5316, 0xFBF9,	0x5317, 0xDDC1, 0x5319, 0xE3B5, 0x5320, 0xEDDD, 0x5321, 0xCEC4,
+	0x5323, 0xCBA1, 0x532A, 0xDDE3, 0x532F, 0xFCDD, 0x5339, 0xF9AF,	0x533F, 0xD2FB, 0x5340, 0xCFA1, 0x5341, 0xE4A8, 0x5343, 0xF4B6,
+	0x5344, 0xECFE, 0x5347, 0xE3AE, 0x5348, 0xE7ED, 0x5349, 0xFDC1,	0x534A, 0xDAE2, 0x534D, 0xD8B3, 0x5351, 0xDDE4, 0x5352, 0xF0EF,
+	0x5353, 0xF6F1, 0x5354, 0xFAF0, 0x5357, 0xD1F5, 0x535A, 0xDACF,	0x535C, 0xDCD4, 0x535E, 0xDCA6, 0x5360, 0xEFBF, 0x5366, 0xCECF,
+	0x5368, 0xE0D9, 0x536F, 0xD9D6, 0x5370, 0xECD4, 0x5371, 0xEACB,	0x5374, 0xCABF, 0x5375, 0xD5B0, 0x5377, 0xCFE9, 0x537D, 0xF1ED,
+	0x537F, 0xCCCF, 0x5384, 0xE4F8, 0x5393, 0xE4ED, 0x5398, 0xD7D8,	0x539A, 0xFDA7, 0x539F, 0xEAAB, 0x53A0, 0xF6B2, 0x53A5, 0xCFF0,
+	0x53A6, 0xF9BD, 0x53AD, 0xE6F4, 0x53BB, 0xCBDB, 0x53C3, 0xF3D1,	0x53C8, 0xE9D1, 0x53C9, 0xF3A9, 0x53CA, 0xD0E0, 0x53CB, 0xE9D2,
+	0x53CD, 0xDAE3, 0x53D4, 0xE2D2, 0x53D6, 0xF6A2, 0x53D7, 0xE1F4,	0x53DB, 0xDAE4, 0x53E1, 0xE7D5, 0x53E2, 0xF5BF, 0x53E3, 0xCFA2,
+	0x53E4, 0xCDAF, 0x53E5, 0xCFA3, 0x53E9, 0xCDB0, 0x53EA, 0xF1FE,	0x53EB, 0xD0A3, 0x53EC, 0xE1AF, 0x53ED, 0xF8A3, 0x53EF, 0xCAA6,
+	0x53F0, 0xF7BB, 0x53F1, 0xF2EA, 0x53F2, 0xDEC8, 0x53F3, 0xE9D3,	0x53F8, 0xDEC9, 0x5403, 0xFDDE, 0x5404, 0xCAC0, 0x5408, 0xF9EA,
+	0x5409, 0xD1CE, 0x540A, 0xEED4, 0x540C, 0xD4D2, 0x540D, 0xD9A3,	0x540E, 0xFDA8, 0x540F, 0xD7D9, 0x5410, 0xF7CE, 0x5411, 0xFABE,
+	0x541B, 0xCFD6, 0x541D, 0xD7F0, 0x541F, 0xEBE1, 0x5420, 0xF8C5,	0x5426, 0xDCFA, 0x5429, 0xDDC3, 0x542B, 0xF9DF, 0x5433, 0xE7EF,
+	0x5438, 0xFDE5, 0x5439, 0xF6A3, 0x543B, 0xD9FC, 0x543C, 0xFDA9,	0x543E, 0xE7EE, 0x5442, 0xD5E5, 0x5448, 0xEFD0, 0x544A, 0xCDB1,
+	0x5451, 0xF7A2, 0x5468, 0xF1B2, 0x546A, 0xF1B1, 0x5471, 0xCDB2,	0x5473, 0xDAAB, 0x5475, 0xCAA7, 0x547B, 0xE3E2, 0x547C, 0xFBBC,
+	0x547D, 0xD9A4, 0x5480, 0xEEBA, 0x5486, 0xF8D3, 0x548C, 0xFBFA,	0x548E, 0xCFA4, 0x5490, 0xDCFB, 0x54A4, 0xF6E3, 0x54A8, 0xEDAA,
+	0x54AB, 0xF2A1, 0x54AC, 0xCEE1, 0x54B3, 0xFAA6, 0x54B8, 0xF9E0,	0x54BD, 0xECD6, 0x54C0, 0xE4EE, 0x54C1, 0xF9A1, 0x54C4, 0xFBEF,
+	0x54C8, 0xF9EB, 0x54C9, 0xEEA3, 0x54E1, 0xEAAC, 0x54E5, 0xCAA8,	0x54E8, 0xF4FA, 0x54ED, 0xCDD6, 0x54EE, 0xFCF6, 0x54F2, 0xF4C9,
+	0x54FA, 0xF8D4, 0x5504, 0xF8A6, 0x5506, 0xDECA, 0x5507, 0xF2C6,	0x550E, 0xD7DA, 0x5510, 0xD3D0, 0x551C, 0xD8C5, 0x552F, 0xEAE6,
+	0x5531, 0xF3DD, 0x5535, 0xE4DA, 0x553E, 0xF6E4, 0x5544, 0xF6F2,	0x5546, 0xDFC2, 0x554F, 0xD9FD, 0x5553, 0xCCF6, 0x5556, 0xD3BA,
+	0x555E, 0xE4AF, 0x5563, 0xF9E1, 0x557C, 0xF0A6, 0x5580, 0xCBD3,	0x5584, 0xE0BC, 0x5586, 0xF4CA, 0x5587, 0xD4FA, 0x5589, 0xFDAA,
+	0x558A, 0xF9E2, 0x5598, 0xF4B7, 0x5599, 0xFDC2, 0x559A, 0xFCB0,	0x559C, 0xFDEC, 0x559D, 0xCAE2, 0x55A7, 0xFDBD, 0x55A9, 0xEAE7,
+	0x55AA, 0xDFC3, 0x55AB, 0xD1D2, 0x55AC, 0xCEE2, 0x55AE, 0xD3A4,	0x55C5, 0xFDAB, 0x55C7, 0xDFE0, 0x55D4, 0xF2C7, 0x55DA, 0xE7F0,
+	0x55DC, 0xD0EE, 0x55DF, 0xF3AA, 0x55E3, 0xDECB, 0x55E4, 0xF6B8,	0x55FD, 0xE1F5, 0x55FE, 0xF1B3, 0x5606, 0xF7A3, 0x5609, 0xCAA9,
+	0x5614, 0xCFA5, 0x5617, 0xDFC4, 0x562F, 0xE1B0, 0x5632, 0xF0BF,	0x5634, 0xF6A4, 0x5636, 0xE3B6, 0x5653, 0xFAC6, 0x5668, 0xD0EF,
+	0x566B, 0xFDED, 0x5674, 0xDDC4, 0x5686, 0xFCF7, 0x56A5, 0xE6BF,	0x56AC, 0xDEAD, 0x56AE, 0xFABF, 0x56B4, 0xE5F1, 0x56BC, 0xEDC4,
+	0x56CA, 0xD2A5, 0x56CD, 0xFDEE, 0x56D1, 0xF5B6, 0x56DA, 0xE1F6,	0x56DB, 0xDECC, 0x56DE, 0xFCDE, 0x56E0, 0xECD7, 0x56F0, 0xCDDD,
+	0x56F9, 0xD6B7, 0x56FA, 0xCDB3, 0x5703, 0xF8D5, 0x5704, 0xE5D8,	0x5708, 0xCFEA, 0x570B, 0xCFD0, 0x570D, 0xEACC, 0x5712, 0xEAAE,
+	0x5713, 0xEAAD, 0x5716, 0xD3F1, 0x5718, 0xD3A5, 0x571F, 0xF7CF,	0x5728, 0xEEA4, 0x572D, 0xD0A4, 0x5730, 0xF2A2, 0x573B, 0xD0F0,
+	0x5740, 0xF2A3, 0x5742, 0xF7F8, 0x5747, 0xD0B3, 0x574A, 0xDBA9,	0x574D, 0xD3BB, 0x574E, 0xCAEC, 0x5750, 0xF1A6, 0x5751, 0xCBD5,
+	0x5761, 0xF7E7, 0x5764, 0xCDDE, 0x5766, 0xF7A4, 0x576A, 0xF8C0,	0x576E, 0xD3DD, 0x5770, 0xCCD0, 0x5775, 0xCFA6, 0x577C, 0xF6F3,
+	0x5782, 0xE1F7, 0x5788, 0xD3DC, 0x578B, 0xFAFE, 0x5793, 0xFAA7,	0x57A0, 0xEBD9, 0x57A2, 0xCFA7, 0x57A3, 0xEAAF, 0x57C3, 0xE4EF,
+	0x57C7, 0xE9B9, 0x57C8, 0xF1D8, 0x57CB, 0xD8D8, 0x57CE, 0xE0F2,	0x57DF, 0xE6B4, 0x57E0, 0xDCFC, 0x57F0, 0xF3F1, 0x57F4, 0xE3D0,
+	0x57F7, 0xF2FB, 0x57F9, 0xDBC6, 0x57FA, 0xD0F1, 0x57FC, 0xD0F2,	0x5800, 0xCFDC, 0x5802, 0xD3D1, 0x5805, 0xCCB1, 0x5806, 0xF7D8,
+	0x5808, 0xCBA8, 0x5809, 0xEBBC, 0x580A, 0xE4BE, 0x581E, 0xF4DC,	0x5821, 0xDCC2, 0x5824, 0xF0A7, 0x5827, 0xE6C0, 0x582A, 0xCAED,
+	0x582F, 0xE8EB, 0x5830, 0xE5E8, 0x5831, 0xDCC3, 0x5834, 0xEDDE,	0x5835, 0xD3F2, 0x583A, 0xCCF7, 0x584A, 0xCED4, 0x584B, 0xE7AB,
+	0x584F, 0xCBC3, 0x5851, 0xE1B1, 0x5854, 0xF7B2, 0x5857, 0xD3F3,	0x5858, 0xD3D2, 0x585A, 0xF5C0, 0x585E, 0xDFDD, 0x5861, 0xEEF3,
+	0x5862, 0xE7F1, 0x5864, 0xFDB4, 0x5875, 0xF2C8, 0x5879, 0xF3D2,	0x587C, 0xEEF4, 0x587E, 0xE2D3, 0x5883, 0xCCD1, 0x5885, 0xDFEA,
+	0x5889, 0xE9BA, 0x5893, 0xD9D7, 0x589C, 0xF5CD, 0x589E, 0xF1F2,	0x589F, 0xFAC7, 0x58A8, 0xD9F8, 0x58A9, 0xD4C2, 0x58AE, 0xF6E5,
+	0x58B3, 0xDDC5, 0x58BA, 0xE7F2, 0x58BB, 0xEDDF, 0x58BE, 0xCACB,	0x58C1, 0xDBFA, 0x58C5, 0xE8B5, 0x58C7, 0xD3A6, 0x58CE, 0xFDB5,
+	0x58D1, 0xF9C9, 0x58D3, 0xE4E2, 0x58D5, 0xFBBD, 0x58D8, 0xD7A4,	0x58D9, 0xCEC5, 0x58DE, 0xCED5, 0x58DF, 0xD6E6, 0x58E4, 0xE5BD,
+	0x58EB, 0xDECD, 0x58EC, 0xECF3, 0x58EF, 0xEDE0, 0x58F9, 0xECEC,	0x58FA, 0xFBBE, 0x58FB, 0xDFEB, 0x58FD, 0xE1F8, 0x590F, 0xF9BE,
+	0x5914, 0xD0F3, 0x5915, 0xE0AA, 0x5916, 0xE8E2, 0x5919, 0xE2D4,	0x591A, 0xD2FD, 0x591C, 0xE5A8, 0x5922, 0xD9D3, 0x5927, 0xD3DE,
+	0x5929, 0xF4B8, 0x592A, 0xF7BC, 0x592B, 0xDCFD, 0x592D, 0xE8EC,	0x592E, 0xE4E7, 0x5931, 0xE3F7, 0x5937, 0xECA8, 0x593E, 0xFAF1,
+	0x5944, 0xE5F2, 0x5947, 0xD0F4, 0x5948, 0xD2AF, 0x5949, 0xDCE5,	0x594E, 0xD0A5, 0x594F, 0xF1B4, 0x5950, 0xFCB1, 0x5951, 0xCCF8,
+	0x5954, 0xDDC6, 0x5955, 0xFAD1, 0x5957, 0xF7DF, 0x595A, 0xFAA8,	0x5960, 0xEEF5, 0x5962, 0xDECE, 0x5967, 0xE7F3, 0x596A, 0xF7AC,
+	0x596B, 0xEBC4, 0x596C, 0xEDE1, 0x596D, 0xE0AB, 0x596E, 0xDDC7,	0x5973, 0xD2B3, 0x5974, 0xD2BF, 0x5978, 0xCACC, 0x597D, 0xFBBF,
+	0x5982, 0xE5FD, 0x5983, 0xDDE5, 0x5984, 0xD8CD, 0x598A, 0xECF4,	0x5993, 0xD0F5, 0x5996, 0xE8ED, 0x5997, 0xD0D2, 0x5999, 0xD9D8,
+	0x59A5, 0xF6E6, 0x59A8, 0xDBAA, 0x59AC, 0xF7E0, 0x59B9, 0xD8D9,	0x59BB, 0xF4A3, 0x59BE, 0xF4DD, 0x59C3, 0xEFD1, 0x59C6, 0xD9B5,
+	0x59C9, 0xEDAB, 0x59CB, 0xE3B7, 0x59D0, 0xEEBB, 0x59D1, 0xCDB4,	0x59D3, 0xE0F3, 0x59D4, 0xEACD, 0x59D9, 0xECF5, 0x59DA, 0xE8EE,
+	0x59DC, 0xCBA9, 0x59DD, 0xF1AF, 0x59E6, 0xCACD, 0x59E8, 0xECA9,	0x59EA, 0xF2EB, 0x59EC, 0xFDEF, 0x59EE, 0xF9F3, 0x59F8, 0xE6C1,
+	0x59FB, 0xECD8, 0x59FF, 0xEDAC, 0x5A01, 0xEACE, 0x5A03, 0xE8DF,	0x5A11, 0xDECF, 0x5A18, 0xD2A6, 0x5A1B, 0xE7F4, 0x5A1C, 0xD1D6,
+	0x5A1F, 0xE6C2, 0x5A20, 0xE3E3, 0x5A25, 0xE4B0, 0x5A29, 0xD8B4,	0x5A36, 0xF6A5, 0x5A3C, 0xF3DE, 0x5A41, 0xD7A5, 0x5A46, 0xF7E8,
+	0x5A49, 0xE8C6, 0x5A5A, 0xFBE6, 0x5A62, 0xDDE6, 0x5A66, 0xDCFE,	0x5A92, 0xD8DA, 0x5A9A, 0xDAAC, 0x5A9B, 0xEAB0, 0x5AA4, 0xE3B8,
+	0x5AC1, 0xCAAA, 0x5AC2, 0xE1F9, 0x5AC4, 0xEAB1, 0x5AC9, 0xF2EC,	0x5ACC, 0xFAEE, 0x5AE1, 0xEED5, 0x5AE6, 0xF9F4, 0x5AE9, 0xD2EC,
+	0x5B05, 0xFBFB, 0x5B09, 0xFDF0, 0x5B0B, 0xE0BD, 0x5B0C, 0xCEE3,	0x5B16, 0xF8C6, 0x5B2A, 0xDEAE, 0x5B40, 0xDFC5, 0x5B43, 0xE5BE,
+	0x5B50, 0xEDAD, 0x5B51, 0xFAEA, 0x5B54, 0xCDEE, 0x5B55, 0xEDA6,	0x5B57, 0xEDAE, 0x5B58, 0xF0ED, 0x5B5A, 0xDDA1, 0x5B5C, 0xEDAF,
+	0x5B5D, 0xFCF8, 0x5B5F, 0xD8EB, 0x5B63, 0xCCF9, 0x5B64, 0xCDB5,	0x5B69, 0xFAA9, 0x5B6B, 0xE1DD, 0x5B70, 0xE2D5, 0x5B71, 0xEDCF,
+	0x5B75, 0xDDA2, 0x5B78, 0xF9CA, 0x5B7A, 0xEAE8, 0x5B7C, 0xE5ED,	0x5B85, 0xD3EB, 0x5B87, 0xE9D4, 0x5B88, 0xE1FA, 0x5B89, 0xE4CC,
+	0x5B8B, 0xE1E4, 0x5B8C, 0xE8C7, 0x5B8F, 0xCEDB, 0x5B93, 0xDCD5,	0x5B95, 0xF7B5, 0x5B96, 0xFCF3, 0x5B97, 0xF0F3, 0x5B98, 0xCEAF,
+	0x5B99, 0xF1B5, 0x5B9A, 0xEFD2, 0x5B9B, 0xE8C8, 0x5B9C, 0xEBF1,	0x5BA2, 0xCBD4, 0x5BA3, 0xE0BE, 0x5BA4, 0xE3F8, 0x5BA5, 0xEAE9,
+	0x5BA6, 0xFCB2, 0x5BAC, 0xE0F4, 0x5BAE, 0xCFE0, 0x5BB0, 0xEEA5,	0x5BB3, 0xFAAA, 0x5BB4, 0xE6C3, 0x5BB5, 0xE1B2, 0x5BB6, 0xCAAB,
+	0x5BB8, 0xE3E4, 0x5BB9, 0xE9BB, 0x5BBF, 0xE2D6, 0x5BC0, 0xF3F2,	0x5BC2, 0xEED6, 0x5BC3, 0xEAB2, 0x5BC4, 0xD0F6, 0x5BC5, 0xECD9,
+	0x5BC6, 0xDACB, 0x5BC7, 0xCFA8, 0x5BCC, 0xDDA3, 0x5BD0, 0xD8DB,	0x5BD2, 0xF9CE, 0x5BD3, 0xE9D5, 0x5BD4, 0xE3D1, 0x5BD7, 0xD2BC,
+	0x5BDE, 0xD8AC, 0x5BDF, 0xF3CC, 0x5BE1, 0xCDFB, 0x5BE2, 0xF6D6,	0x5BE4, 0xE7F5, 0x5BE5, 0xE8EF, 0x5BE6, 0xE3F9, 0x5BE7, 0xD2BB,
+	0x5BE8, 0xF3F3, 0x5BE9, 0xE3FB, 0x5BEB, 0xDED0, 0x5BEC, 0xCEB0,	0x5BEE, 0xD6F7, 0x5BEF, 0xF1D9, 0x5BF5, 0xF5C1, 0x5BF6, 0xDCC4,
+	0x5BF8, 0xF5BB, 0x5BFA, 0xDED1, 0x5C01, 0xDCE6, 0x5C04, 0xDED2,	0x5C07, 0xEDE2, 0x5C08, 0xEEF6, 0x5C09, 0xEACF, 0x5C0A, 0xF0EE,
+	0x5C0B, 0xE3FC, 0x5C0D, 0xD3DF, 0x5C0E, 0xD3F4, 0x5C0F, 0xE1B3,	0x5C11, 0xE1B4, 0x5C16, 0xF4D3, 0x5C19, 0xDFC6, 0x5C24, 0xE9D6,
+	0x5C28, 0xDBAB, 0x5C31, 0xF6A6, 0x5C38, 0xE3B9, 0x5C39, 0xEBC5,	0x5C3A, 0xF4A9, 0x5C3B, 0xCDB6, 0x5C3C, 0xD2F9, 0x5C3E, 0xDAAD,
+	0x5C3F, 0xD2E3, 0x5C40, 0xCFD1, 0x5C45, 0xCBDC, 0x5C46, 0xCCFA,	0x5C48, 0xCFDD, 0x5C4B, 0xE8A9, 0x5C4D, 0xE3BB, 0x5C4E, 0xE3BA,
+	0x5C51, 0xE0DA, 0x5C55, 0xEEF7, 0x5C5B, 0xDCB3, 0x5C60, 0xD3F5,	0x5C62, 0xD7A6, 0x5C64, 0xF6B5, 0x5C65, 0xD7DB, 0x5C6C, 0xE1D5,
+	0x5C6F, 0xD4EA, 0x5C71, 0xDFA3, 0x5C79, 0xFDDF, 0x5C90, 0xD0F7,	0x5C91, 0xEDD4, 0x5CA1, 0xCBAA, 0x5CA9, 0xE4DB, 0x5CAB, 0xE1FB,
+	0x5CAC, 0xCBA2, 0x5CB1, 0xD3E0, 0x5CB3, 0xE4BF, 0x5CB5, 0xFBC0,	0x5CB7, 0xDABE, 0x5CB8, 0xE4CD, 0x5CBA, 0xD6B9, 0x5CBE, 0xEFC0,
+	0x5CC0, 0xE1FC, 0x5CD9, 0xF6B9, 0x5CE0, 0xDFC7, 0x5CE8, 0xE4B1,	0x5CEF, 0xDCE7, 0x5CF0, 0xDCE8, 0x5CF4, 0xFAD6, 0x5CF6, 0xD3F6,
+	0x5CFB, 0xF1DA, 0x5CFD, 0xFAF2, 0x5D07, 0xE2FD, 0x5D0D, 0xD5CF,	0x5D0E, 0xD0F8, 0x5D11, 0xCDDF, 0x5D14, 0xF5CB, 0x5D16, 0xE4F0,
+	0x5D17, 0xCBAB, 0x5D19, 0xD7C4, 0x5D27, 0xE2FE, 0x5D29, 0xDDDA,	0x5D4B, 0xDAAE, 0x5D4C, 0xCAEE, 0x5D50, 0xD5B9, 0x5D69, 0xE3A1,
+	0x5D6C, 0xE8E3, 0x5D6F, 0xF3AB, 0x5D87, 0xCFA9, 0x5D8B, 0xD3F7,	0x5D9D, 0xD4F1, 0x5DA0, 0xCEE4, 0x5DA2, 0xE8F2, 0x5DAA, 0xE5F5,
+	0x5DB8, 0xE7AE, 0x5DBA, 0xD6BA, 0x5DBC, 0xDFEC, 0x5DBD, 0xE4C0,	0x5DCD, 0xE8E4, 0x5DD2, 0xD8B5, 0x5DD6, 0xE4DC, 0x5DDD, 0xF4B9,
+	0x5DDE, 0xF1B6, 0x5DE1, 0xE2DE, 0x5DE2, 0xE1B5, 0x5DE5, 0xCDEF,	0x5DE6, 0xF1A7, 0x5DE7, 0xCEE5, 0x5DE8, 0xCBDD, 0x5DEB, 0xD9E3,
+	0x5DEE, 0xF3AC, 0x5DF1, 0xD0F9, 0x5DF2, 0xECAB, 0x5DF3, 0xDED3,	0x5DF4, 0xF7E9, 0x5DF7, 0xF9F5, 0x5DFD, 0xE1DE, 0x5DFE, 0xCBEE,
+	0x5E02, 0xE3BC, 0x5E03, 0xF8D6, 0x5E06, 0xDBEE, 0x5E0C, 0xFDF1,	0x5E11, 0xF7B6, 0x5E16, 0xF4DE, 0x5E19, 0xF2ED, 0x5E1B, 0xDBD9,
+	0x5E1D, 0xF0A8, 0x5E25, 0xE1FD, 0x5E2B, 0xDED4, 0x5E2D, 0xE0AC,	0x5E33, 0xEDE3, 0x5E36, 0xD3E1, 0x5E38, 0xDFC8, 0x5E3D, 0xD9B6,
+	0x5E3F, 0xFDAC, 0x5E40, 0xEFD3, 0x5E44, 0xE4C1, 0x5E45, 0xF8EB,	0x5E47, 0xDBAC, 0x5E4C, 0xFCC6, 0x5E55, 0xD8AD, 0x5E5F, 0xF6BA,
+	0x5E61, 0xDBDF, 0x5E62, 0xD3D3, 0x5E63, 0xF8C7, 0x5E72, 0xCACE,	0x5E73, 0xF8C1, 0x5E74, 0xD2B4, 0x5E77, 0xDCB4, 0x5E78, 0xFAB9,
+	0x5E79, 0xCACF, 0x5E7B, 0xFCB3, 0x5E7C, 0xEAEA, 0x5E7D, 0xEAEB,	0x5E7E, 0xD0FA, 0x5E84, 0xEDE4, 0x5E87, 0xDDE7, 0x5E8A, 0xDFC9,
+	0x5E8F, 0xDFED, 0x5E95, 0xEEBC, 0x5E97, 0xEFC1, 0x5E9A, 0xCCD2,	0x5E9C, 0xDDA4, 0x5EA0, 0xDFCA, 0x5EA6, 0xD3F8, 0x5EA7, 0xF1A8,
+	0x5EAB, 0xCDB7, 0x5EAD, 0xEFD4, 0x5EB5, 0xE4DD, 0x5EB6, 0xDFEE,	0x5EB7, 0xCBAC, 0x5EB8, 0xE9BC, 0x5EBE, 0xEAEC, 0x5EC2, 0xDFCB,
+	0x5EC8, 0xF9BF, 0x5EC9, 0xD6AF, 0x5ECA, 0xD5C6, 0x5ED0, 0xCFAA,	0x5ED3, 0xCEA9, 0x5ED6, 0xD6F8, 0x5EDA, 0xF1B7, 0x5EDB, 0xEEF8,
+	0x5EDF, 0xD9D9, 0x5EE0, 0xF3DF, 0x5EE2, 0xF8C8, 0x5EE3, 0xCEC6,	0x5EEC, 0xD5E6, 0x5EF3, 0xF4E6, 0x5EF6, 0xE6C5, 0x5EF7, 0xEFD5,
+	0x5EFA, 0xCBEF, 0x5EFB, 0xFCDF, 0x5F01, 0xDCA7, 0x5F04, 0xD6E7,	0x5F0A, 0xF8C9, 0x5F0F, 0xE3D2, 0x5F11, 0xE3BD, 0x5F13, 0xCFE1,
+	0x5F14, 0xF0C0, 0x5F15, 0xECDA, 0x5F17, 0xDDD7, 0x5F18, 0xFBF0,	0x5F1B, 0xECAC, 0x5F1F, 0xF0A9, 0x5F26, 0xFAD7, 0x5F27, 0xFBC1,
+	0x5F29, 0xD2C0, 0x5F31, 0xE5B0, 0x5F35, 0xEDE5, 0x5F3A, 0xCBAD,	0x5F3C, 0xF9B0, 0x5F48, 0xF7A5, 0x5F4A, 0xCBAE, 0x5F4C, 0xDAAF,
+	0x5F4E, 0xD8B6, 0x5F56, 0xD3A7, 0x5F57, 0xFBB2, 0x5F59, 0xFDC4,	0x5F5B, 0xECAD, 0x5F62, 0xFBA1, 0x5F66, 0xE5E9, 0x5F67, 0xE9EE,
+	0x5F69, 0xF3F4, 0x5F6A, 0xF8F3, 0x5F6B, 0xF0C1, 0x5F6C, 0xDEAF,	0x5F6D, 0xF8B0, 0x5F70, 0xF3E0, 0x5F71, 0xE7AF, 0x5F77, 0xDBAD,
+	0x5F79, 0xE6B5, 0x5F7C, 0xF9A8, 0x5F7F, 0xDDD8, 0x5F80, 0xE8D9,	0x5F81, 0xEFD6, 0x5F85, 0xD3E2, 0x5F87, 0xE2DF, 0x5F8A, 0xFCE0,
+	0x5F8B, 0xD7C8, 0x5F8C, 0xFDAD, 0x5F90, 0xDFEF, 0x5F91, 0xCCD3,	0x5F92, 0xD3F9, 0x5F97, 0xD4F0, 0x5F98, 0xDBC7, 0x5F99, 0xDED5,
+	0x5F9E, 0xF0F4, 0x5FA0, 0xD5D0, 0x5FA1, 0xE5D9, 0x5FA8, 0xFCC7,	0x5FA9, 0xDCD6, 0x5FAA, 0xE2E0, 0x5FAE, 0xDAB0, 0x5FB5, 0xF3A3,
+	0x5FB7, 0xD3EC, 0x5FB9, 0xF4CB, 0x5FBD, 0xFDC5, 0x5FC3, 0xE3FD,	0x5FC5, 0xF9B1, 0x5FCC, 0xD0FB, 0x5FCD, 0xECDB, 0x5FD6, 0xF5BC,
+	0x5FD7, 0xF2A4, 0x5FD8, 0xD8CE, 0x5FD9, 0xD8CF, 0x5FE0, 0xF5F7,	0x5FEB, 0xF6E1, 0x5FF5, 0xD2B7, 0x5FFD, 0xFBEC, 0x5FFF, 0xDDC8,
+	0x600F, 0xE4E8, 0x6012, 0xD2C1, 0x6016, 0xF8D7, 0x601C, 0xD6BB,	0x601D, 0xDED6, 0x6020, 0xF7BD, 0x6021, 0xECAE, 0x6025, 0xD0E1,
+	0x6027, 0xE0F5, 0x6028, 0xEAB3, 0x602A, 0xCED6, 0x602F, 0xCCA5,	0x6041, 0xECF6, 0x6042, 0xE2E1, 0x6043, 0xE3BE, 0x604D, 0xFCC8,
+	0x6050, 0xCDF0, 0x6052, 0xF9F6, 0x6055, 0xDFF0, 0x6059, 0xE5BF,	0x605D, 0xCEBF, 0x6062, 0xFCE1, 0x6063, 0xEDB0, 0x6064, 0xFDD1,
+	0x6065, 0xF6BB, 0x6068, 0xF9CF, 0x6069, 0xEBDA, 0x606A, 0xCAC1,	0x606C, 0xD2B8, 0x606D, 0xCDF1, 0x606F, 0xE3D3, 0x6070, 0xFDE6,
+	0x6085, 0xE6ED, 0x6089, 0xE3FA, 0x608C, 0xF0AA, 0x608D, 0xF9D0,	0x6094, 0xFCE2, 0x6096, 0xF8A7, 0x609A, 0xE1E5, 0x609B, 0xEEF9,
+	0x609F, 0xE7F6, 0x60A0, 0xEAED, 0x60A3, 0xFCB4, 0x60A4, 0xF5C2,	0x60A7, 0xD7DC, 0x60B0, 0xF0F5, 0x60B2, 0xDDE8, 0x60B3, 0xD3ED,
+	0x60B4, 0xF5FC, 0x60B6, 0xDABF, 0x60B8, 0xCCFB, 0x60BC, 0xD3FA,	0x60BD, 0xF4A4, 0x60C5, 0xEFD7, 0x60C7, 0xD4C3, 0x60D1, 0xFBE3,
+	0x60DA, 0xFBED, 0x60DC, 0xE0AD, 0x60DF, 0xEAEE, 0x60E0, 0xFBB3,	0x60E1, 0xE4C2, 0x60F0, 0xF6E7, 0x60F1, 0xD2DD, 0x60F3, 0xDFCC,
+	0x60F6, 0xFCC9, 0x60F9, 0xE5A9, 0x60FA, 0xE0F6, 0x60FB, 0xF6B3,	0x6101, 0xE1FE, 0x6106, 0xCBF0, 0x6108, 0xEAEF, 0x6109, 0xEAF0,
+	0x610D, 0xDAC0, 0x610E, 0xF8B4, 0x610F, 0xEBF2, 0x6115, 0xE4C3,	0x611A, 0xE9D7, 0x611B, 0xE4F1, 0x611F, 0xCAEF, 0x6127, 0xCED7,
+	0x6130, 0xFCCA, 0x6134, 0xF3E1, 0x6137, 0xCBC4, 0x613C, 0xE3E5,	0x613E, 0xCBC5, 0x613F, 0xEAB4, 0x6142, 0xE9BD, 0x6144, 0xD7C9,
+	0x6147, 0xEBDB, 0x6148, 0xEDB1, 0x614A, 0xCCC3, 0x614B, 0xF7BE,	0x614C, 0xFCCB, 0x6153, 0xF8F4, 0x6155, 0xD9B7, 0x6158, 0xF3D3,
+	0x6159, 0xF3D4, 0x615D, 0xF7E4, 0x615F, 0xF7D1, 0x6162, 0xD8B7,	0x6163, 0xCEB1, 0x6164, 0xCAC2, 0x6167, 0xFBB4, 0x6168, 0xCBC6,
+	0x616B, 0xF0F6, 0x616E, 0xD5E7, 0x6170, 0xEAD0, 0x6176, 0xCCD4,	0x6177, 0xCBAF, 0x617D, 0xF4AA, 0x617E, 0xE9AF, 0x6181, 0xF5C3,
+	0x6182, 0xE9D8, 0x618A, 0xDDE9, 0x618E, 0xF1F3, 0x6190, 0xD5FB,	0x6191, 0xDEBB, 0x6194, 0xF4FB, 0x6198, 0xFDF3, 0x6199, 0xFDF2,
+	0x619A, 0xF7A6, 0x61A4, 0xDDC9, 0x61A7, 0xD4D3, 0x61A9, 0xCCA8,	0x61AB, 0xDAC1, 0x61AC, 0xCCD5, 0x61AE, 0xD9E4, 0x61B2, 0xFACA,
+	0x61B6, 0xE5E3, 0x61BA, 0xD3BC, 0x61BE, 0xCAF0, 0x61C3, 0xD0C4,	0x61C7, 0xCAD0, 0x61C8, 0xFAAB, 0x61C9, 0xEBEB, 0x61CA, 0xE7F8,
+	0x61CB, 0xD9E5, 0x61E6, 0xD1D7, 0x61F2, 0xF3A4, 0x61F6, 0xD4FB,	0x61F7, 0xFCE3, 0x61F8, 0xFAD8, 0x61FA, 0xF3D5, 0x61FC, 0xCFAB,
+	0x61FF, 0xEBF3, 0x6200, 0xD5FC, 0x6207, 0xD3D4, 0x6208, 0xCDFC,	0x620A, 0xD9E6, 0x620C, 0xE2F9, 0x620D, 0xE2A1, 0x620E, 0xEBD4,
+	0x6210, 0xE0F7, 0x6211, 0xE4B2, 0x6212, 0xCCFC, 0x6216, 0xFBE4,	0x621A, 0xF4AB, 0x621F, 0xD0BD, 0x6221, 0xCAF1, 0x622A, 0xEFB8,
+	0x622E, 0xD7C0, 0x6230, 0xEEFA, 0x6231, 0xFDF4, 0x6234, 0xD3E3,	0x6236, 0xFBC2, 0x623E, 0xD5E8, 0x623F, 0xDBAE, 0x6240, 0xE1B6,
+	0x6241, 0xF8B7, 0x6247, 0xE0BF, 0x6248, 0xFBC3, 0x6249, 0xDDEA,	0x624B, 0xE2A2, 0x624D, 0xEEA6, 0x6253, 0xF6E8, 0x6258, 0xF6F5,
+	0x626E, 0xDDCA, 0x6271, 0xD0E2, 0x6276, 0xDDA6, 0x6279, 0xDDEB,	0x627C, 0xE4F9, 0x627F, 0xE3AF, 0x6280, 0xD0FC, 0x6284, 0xF4FC,
+	0x6289, 0xCCBC, 0x628A, 0xF7EA, 0x6291, 0xE5E4, 0x6292, 0xDFF1,	0x6295, 0xF7E1, 0x6297, 0xF9F7, 0x6298, 0xEFB9, 0x629B, 0xF8D8,
+	0x62AB, 0xF9A9, 0x62B1, 0xF8D9, 0x62B5, 0xEEBD, 0x62B9, 0xD8C6,	0x62BC, 0xE4E3, 0x62BD, 0xF5CE, 0x62C2, 0xDDD9, 0x62C7, 0xD9E7,
+	0x62C8, 0xD2B9, 0x62C9, 0xD5C3, 0x62CC, 0xDAE5, 0x62CD, 0xDAD0,	0x62CF, 0xD1D9, 0x62D0, 0xCED8, 0x62D2, 0xCBDE, 0x62D3, 0xF4AC,
+	0x62D4, 0xDAFB, 0x62D6, 0xF6E9, 0x62D7, 0xE8F3, 0x62D8, 0xCFAC,	0x62D9, 0xF0F0, 0x62DB, 0xF4FD, 0x62DC, 0xDBC8, 0x62EC, 0xCEC0,
+	0x62ED, 0xE3D4, 0x62EE, 0xD1CF, 0x62EF, 0xF1F5, 0x62F1, 0xCDF2,	0x62F3, 0xCFEB, 0x62F7, 0xCDB8, 0x62FE, 0xE3A6, 0x62FF, 0xD1DA,
+	0x6301, 0xF2A5, 0x6307, 0xF2A6, 0x6309, 0xE4CE, 0x6311, 0xD3FB,	0x632B, 0xF1A9, 0x632F, 0xF2C9, 0x633A, 0xEFD8, 0x633B, 0xE6C9,
+	0x633D, 0xD8B8, 0x633E, 0xFAF3, 0x6349, 0xF3B5, 0x634C, 0xF8A4,	0x634F, 0xD1F3, 0x6350, 0xE6C8, 0x6355, 0xF8DA, 0x6367, 0xDCE9,
+	0x6368, 0xDED7, 0x636E, 0xCBDF, 0x6372, 0xCFEC, 0x6377, 0xF4DF,	0x637A, 0xD1F4, 0x637B, 0xD2BA, 0x637F, 0xDFF2, 0x6383, 0xE1B7,
+	0x6388, 0xE2A3, 0x6389, 0xD3FC, 0x638C, 0xEDE6, 0x6392, 0xDBC9,	0x6396, 0xE4FA, 0x6398, 0xCFDE, 0x639B, 0xCED0, 0x63A0, 0xD5D3,
+	0x63A1, 0xF3F5, 0x63A2, 0xF7AE, 0x63A5, 0xEFC8, 0x63A7, 0xCDF3,	0x63A8, 0xF5CF, 0x63A9, 0xE5F3, 0x63AA, 0xF0C2, 0x63C0, 0xCAD1,
+	0x63C4, 0xEAF1, 0x63C6, 0xD0A6, 0x63CF, 0xD9DA, 0x63D0, 0xF0AB,	0x63D6, 0xEBE7, 0x63DA, 0xE5C0, 0x63DB, 0xFCB5, 0x63E1, 0xE4C4,
+	0x63ED, 0xCCA9, 0x63EE, 0xFDC6, 0x63F4, 0xEAB5, 0x63F6, 0xE5AA,	0x63F7, 0xDFBA, 0x640D, 0xE1DF, 0x640F, 0xDAD1, 0x6414, 0xE1B8,
+	0x6416, 0xE8F4, 0x6417, 0xD3FD, 0x641C, 0xE2A4, 0x6422, 0xF2CA,	0x642C, 0xDAE6, 0x642D, 0xF7B3, 0x643A, 0xFDCD, 0x643E, 0xF3B6,
+	0x6458, 0xEED7, 0x6460, 0xF5C4, 0x6469, 0xD8A4, 0x646F, 0xF2A7,	0x6478, 0xD9B8, 0x6479, 0xD9B9, 0x647A, 0xEFC9, 0x6488, 0xD6CE,
+	0x6491, 0xF7CB, 0x6492, 0xDFAE, 0x6493, 0xE8F5, 0x649A, 0xD2B5,	0x649E, 0xD3D5, 0x64A4, 0xF4CC, 0x64A5, 0xDAFC, 0x64AB, 0xD9E8,
+	0x64AD, 0xF7EB, 0x64AE, 0xF5C9, 0x64B0, 0xF3BC, 0x64B2, 0xDAD2,	0x64BB, 0xD3B5, 0x64C1, 0xE8B6, 0x64C4, 0xD6CF, 0x64C5, 0xF4BA,
+	0x64C7, 0xF7C9, 0x64CA, 0xCCAA, 0x64CD, 0xF0C3, 0x64CE, 0xCCD6,	0x64D2, 0xD0D3, 0x64D4, 0xD3BD, 0x64D8, 0xDBFB, 0x64DA, 0xCBE0,
+	0x64E1, 0xD3E4, 0x64E2, 0xF6F7, 0x64E5, 0xD5BA, 0x64E6, 0xF3CD,	0x64E7, 0xCBE1, 0x64EC, 0xEBF4, 0x64F2, 0xF4AD, 0x64F4, 0xFCAA,
+	0x64FA, 0xF7EC, 0x64FE, 0xE8F6, 0x6500, 0xDAE7, 0x6504, 0xF7CC,	0x6518, 0xE5C1, 0x651D, 0xE0EE, 0x6523, 0xD5FD, 0x652A, 0xCEE6,
+	0x652B, 0xFCAB, 0x652C, 0xD5BB, 0x652F, 0xF2A8, 0x6536, 0xE2A5,	0x6537, 0xCDB9, 0x6538, 0xEAF2, 0x6539, 0xCBC7, 0x653B, 0xCDF4,
+	0x653E, 0xDBAF, 0x653F, 0xEFD9, 0x6545, 0xCDBA, 0x6548, 0xFCF9,	0x654D, 0xDFF3, 0x654E, 0xCEE7, 0x654F, 0xDAC2, 0x6551, 0xCFAD,
+	0x6556, 0xE7F9, 0x6557, 0xF8A8, 0x655E, 0xF3E2, 0x6562, 0xCAF2,	0x6563, 0xDFA4, 0x6566, 0xD4C4, 0x656C, 0xCCD7, 0x656D, 0xE5C2,
+	0x6572, 0xCDBB, 0x6574, 0xEFDA, 0x6575, 0xEED8, 0x6577, 0xDDA7,	0x6578, 0xE2A6, 0x657E, 0xE0C0, 0x6582, 0xD6B0, 0x6583, 0xF8CA,
+	0x6585, 0xFCFA, 0x6587, 0xD9FE, 0x658C, 0xDEB0, 0x6590, 0xDDEC,	0x6591, 0xDAE8, 0x6597, 0xD4E0, 0x6599, 0xD6F9, 0x659B, 0xCDD7,
+	0x659C, 0xDED8, 0x659F, 0xF2F8, 0x65A1, 0xE4D6, 0x65A4, 0xD0C5,	0x65A5, 0xF4AE, 0x65A7, 0xDDA8, 0x65AB, 0xEDC5, 0x65AC, 0xF3D6,
+	0x65AF, 0xDED9, 0x65B0, 0xE3E6, 0x65B7, 0xD3A8, 0x65B9, 0xDBB0,	0x65BC, 0xE5DA, 0x65BD, 0xE3BF, 0x65C1, 0xDBB1, 0x65C5, 0xD5E9,
+	0x65CB, 0xE0C1, 0x65CC, 0xEFDB, 0x65CF, 0xF0E9, 0x65D2, 0xD7B2,	0x65D7, 0xD0FD, 0x65E0, 0xD9E9, 0x65E3, 0xD0FE, 0x65E5, 0xECED,
+	0x65E6, 0xD3A9, 0x65E8, 0xF2A9, 0x65E9, 0xF0C4, 0x65EC, 0xE2E2,	0x65ED, 0xE9EF, 0x65F1, 0xF9D1, 0x65F4, 0xE9D9, 0x65FA, 0xE8DA,
+	0x65FB, 0xDAC3, 0x65FC, 0xDAC4, 0x65FD, 0xD4C5, 0x65FF, 0xE7FA,	0x6606, 0xCDE0, 0x6607, 0xE3B0, 0x6609, 0xDBB2, 0x660A, 0xFBC4,
+	0x660C, 0xF3E3, 0x660E, 0xD9A5, 0x660F, 0xFBE7, 0x6610, 0xDDCB,	0x6611, 0xD0D4, 0x6613, 0xE6B6, 0x6614, 0xE0AE, 0x6615, 0xFDDA,
+	0x661E, 0xDCB5, 0x661F, 0xE0F8, 0x6620, 0xE7B1, 0x6625, 0xF5F0,	0x6627, 0xD8DC, 0x6628, 0xEDC6, 0x662D, 0xE1B9, 0x662F, 0xE3C0,
+	0x6630, 0xF9C0, 0x6631, 0xE9F0, 0x6634, 0xD9DB, 0x6636, 0xF3E4,	0x663A, 0xDCB6, 0x663B, 0xE4E9, 0x6641, 0xF0C5, 0x6642, 0xE3C1,
+	0x6643, 0xFCCC, 0x6644, 0xFCCD, 0x6649, 0xF2CB, 0x664B, 0xF2CC,	0x664F, 0xE4CF, 0x6659, 0xF1DB, 0x665B, 0xFAD9, 0x665D, 0xF1B8,
+	0x665E, 0xFDF5, 0x665F, 0xE0F9, 0x6664, 0xE7FB, 0x6665, 0xFCB7,	0x6666, 0xFCE4, 0x6667, 0xFBC5, 0x6668, 0xE3E7, 0x6669, 0xD8B9,
+	0x666B, 0xF6F8, 0x666E, 0xDCC5, 0x666F, 0xCCD8, 0x6673, 0xE0AF,	0x6674, 0xF4E7, 0x6676, 0xEFDC, 0x6677, 0xCFFC, 0x6678, 0xEFDD,
+	0x667A, 0xF2AA, 0x6684, 0xFDBE, 0x6687, 0xCAAC, 0x6688, 0xFDBB,	0x6689, 0xFDC7, 0x668E, 0xE7B2, 0x6690, 0xEAD1, 0x6691, 0xDFF4,
+	0x6696, 0xD1EC, 0x6697, 0xE4DE, 0x6698, 0xE5C3, 0x669D, 0xD9A6,	0x66A0, 0xCDBC, 0x66A2, 0xF3E5, 0x66AB, 0xEDD5, 0x66AE, 0xD9BA,
+	0x66B2, 0xEDE7, 0x66B3, 0xFBB5, 0x66B4, 0xF8EC, 0x66B9, 0xE0E7,	0x66BB, 0xCCD9, 0x66BE, 0xD4C6, 0x66C4, 0xE7A5, 0x66C6, 0xD5F5,
+	0x66C7, 0xD3BE, 0x66C9, 0xFCFB, 0x66D6, 0xE4F2, 0x66D9, 0xDFF5,	0x66DC, 0xE8F8, 0x66DD, 0xF8ED, 0x66E0, 0xCEC7, 0x66E6, 0xFDF6,
+	0x66F0, 0xE8D8, 0x66F2, 0xCDD8, 0x66F3, 0xE7D6, 0x66F4, 0xCCDA,	0x66F7, 0xCAE3, 0x66F8, 0xDFF6, 0x66F9, 0xF0C7, 0x66FA, 0xF0C6,
+	0x66FC, 0xD8BA, 0x66FE, 0xF1F4, 0x66FF, 0xF4F0, 0x6700, 0xF5CC,	0x6703, 0xFCE5, 0x6708, 0xEAC5, 0x6709, 0xEAF3, 0x670B, 0xDDDB,
+	0x670D, 0xDCD7, 0x6714, 0xDEFD, 0x6715, 0xF2F9, 0x6717, 0xD5C7,	0x671B, 0xD8D0, 0x671D, 0xF0C8, 0x671E, 0xD1A1, 0x671F, 0xD1A2,
+	0x6726, 0xD9D4, 0x6727, 0xD6E8, 0x6728, 0xD9CA, 0x672A, 0xDAB1,	0x672B, 0xD8C7, 0x672C, 0xDCE2, 0x672D, 0xF3CE, 0x672E, 0xF5F4,
+	0x6731, 0xF1B9, 0x6734, 0xDAD3, 0x6736, 0xF6EA, 0x673A, 0xCFF5,	0x673D, 0xFDAE, 0x6746, 0xCAD2, 0x6749, 0xDFB4, 0x674E, 0xD7DD,
+	0x674F, 0xFABA, 0x6750, 0xEEA7, 0x6751, 0xF5BD, 0x6753, 0xF8F5,	0x6756, 0xEDE8, 0x675C, 0xD4E1, 0x675E, 0xD1A3, 0x675F, 0xE1D6,
+	0x676D, 0xF9F8, 0x676F, 0xDBCA, 0x6770, 0xCBF9, 0x6771, 0xD4D4,	0x6773, 0xD9DC, 0x6775, 0xEEBE, 0x6777, 0xF7ED, 0x677B, 0xD2EE,
+	0x677E, 0xE1E6, 0x677F, 0xF7F9, 0x6787, 0xDDED, 0x6789, 0xE8DB,	0x678B, 0xDBB3, 0x678F, 0xD1F7, 0x6790, 0xE0B0, 0x6793, 0xD4E2,
+	0x6795, 0xF6D7, 0x6797, 0xD7F9, 0x679A, 0xD8DD, 0x679C, 0xCDFD,	0x679D, 0xF2AB, 0x67AF, 0xCDBD, 0x67B0, 0xF8C2, 0x67B3, 0xF2AC,
+	0x67B6, 0xCAAD, 0x67B7, 0xCAAE, 0x67B8, 0xCFAE, 0x67BE, 0xE3C2,	0x67C4, 0xDCB7, 0x67CF, 0xDBDA, 0x67D0, 0xD9BB, 0x67D1, 0xCAF3,
+	0x67D2, 0xF6D3, 0x67D3, 0xE6F8, 0x67D4, 0xEAF5, 0x67DA, 0xEAF6,	0x67DD, 0xF6F9, 0x67E9, 0xCFAF, 0x67EC, 0xCAD3, 0x67EF, 0xCAAF,
+	0x67F0, 0xD2B0, 0x67F1, 0xF1BA, 0x67F3, 0xD7B3, 0x67F4, 0xE3C3,	0x67F5, 0xF3FD, 0x67F6, 0xDEDA, 0x67FB, 0xDEDB, 0x67FE, 0xEFDE,
+	0x6812, 0xE2E3, 0x6813, 0xEEFB, 0x6816, 0xDFF7, 0x6817, 0xD7CA,	0x6821, 0xCEE8, 0x6822, 0xDBDB, 0x682A, 0xF1BB, 0x682F, 0xE9F1,
+	0x6838, 0xFAB7, 0x6839, 0xD0C6, 0x683C, 0xCCAB, 0x683D, 0xEEA8,	0x6840, 0xCBFA, 0x6841, 0xF9F9, 0x6842, 0xCCFD, 0x6843, 0xD3FE,
+	0x6848, 0xE4D0, 0x684E, 0xF2EE, 0x6850, 0xD4D5, 0x6851, 0xDFCD,	0x6853, 0xFCB8, 0x6854, 0xD1D0, 0x686D, 0xF2CD, 0x6876, 0xF7D2,
+	0x687F, 0xCAD4, 0x6881, 0xD5D9, 0x6885, 0xD8DE, 0x688F, 0xCDD9,	0x6893, 0xEEA9, 0x6894, 0xF6BC, 0x6897, 0xCCDB, 0x689D, 0xF0C9,
+	0x689F, 0xFCFC, 0x68A1, 0xE8C9, 0x68A2, 0xF4FE, 0x68A7, 0xE7FC,	0x68A8, 0xD7DE, 0x68AD, 0xDEDC, 0x68AF, 0xF0AC, 0x68B0, 0xCCFE,
+	0x68B1, 0xCDE1, 0x68B3, 0xE1BA, 0x68B5, 0xDBEF, 0x68B6, 0xDAB2,	0x68C4, 0xD1A5, 0x68C5, 0xDCB8, 0x68C9, 0xD8F6, 0x68CB, 0xD1A4,
+	0x68CD, 0xCDE2, 0x68D2, 0xDCEA, 0x68D5, 0xF0F7, 0x68D7, 0xF0CA,	0x68D8, 0xD0BE, 0x68DA, 0xDDDC, 0x68DF, 0xD4D6, 0x68E0, 0xD3D6,
+	0x68E7, 0xEDD0, 0x68E8, 0xCDA1, 0x68EE, 0xDFB5, 0x68F2, 0xDFF8,	0x68F9, 0xD4A1, 0x68FA, 0xCEB2, 0x6900, 0xE8CA, 0x6905, 0xEBF5,
+	0x690D, 0xE3D5, 0x690E, 0xF5D0, 0x6912, 0xF5A1, 0x6927, 0xD9A7,	0x6930, 0xE5AB, 0x693D, 0xE6CB, 0x693F, 0xF5F1, 0x694A, 0xE5C5,
+	0x6953, 0xF9A3, 0x6954, 0xE0DB, 0x6955, 0xF6EB, 0x6957, 0xCBF1,	0x6959, 0xD9EA, 0x695A, 0xF5A2, 0x695E, 0xD7D1, 0x6960, 0xD1F8,
+	0x6961, 0xEAF8, 0x6962, 0xEAF9, 0x6963, 0xDAB3, 0x6968, 0xEFDF,	0x696B, 0xF1EF, 0x696D, 0xE5F6, 0x696E, 0xEEBF, 0x696F, 0xE2E4,
+	0x6975, 0xD0BF, 0x6977, 0xFAAC, 0x6978, 0xF5D1, 0x6979, 0xE7B3,	0x6995, 0xE9BE, 0x699B, 0xF2CE, 0x699C, 0xDBB4, 0x69A5, 0xFCCE,
+	0x69A7, 0xDDEE, 0x69AE, 0xE7B4, 0x69B4, 0xD7B4, 0x69BB, 0xF7B4,	0x69C1, 0xCDBE, 0x69C3, 0xDAE9, 0x69CB, 0xCFB0, 0x69CC, 0xF7D9,
+	0x69CD, 0xF3E6, 0x69D0, 0xCED9, 0x69E8, 0xCEAA, 0x69EA, 0xCBC8,	0x69FB, 0xD0A7, 0x69FD, 0xF0CB, 0x69FF, 0xD0C7, 0x6A02, 0xE4C5,
+	0x6A0A, 0xDBE0, 0x6A11, 0xD5DA, 0x6A13, 0xD7A7, 0x6A17, 0xEEC0,	0x6A19, 0xF8F6, 0x6A1E, 0xF5D2, 0x6A1F, 0xEDE9, 0x6A21, 0xD9BC,
+	0x6A23, 0xE5C6, 0x6A35, 0xF5A3, 0x6A38, 0xDAD4, 0x6A39, 0xE2A7,	0x6A3A, 0xFBFC, 0x6A3D, 0xF1DC, 0x6A44, 0xCAF4, 0x6A48, 0xE8FA,
+	0x6A4B, 0xCEE9, 0x6A52, 0xE9F8, 0x6A53, 0xE2E5, 0x6A58, 0xD0B9,	0x6A59, 0xD4F2, 0x6A5F, 0xD1A6, 0x6A61, 0xDFCE, 0x6A6B, 0xFCF4,
+	0x6A80, 0xD3AA, 0x6A84, 0xCCAC, 0x6A89, 0xEFE0, 0x6A8D, 0xE5E5,	0x6A8E, 0xD0D5, 0x6A97, 0xDBFC, 0x6A9C, 0xFCE6, 0x6AA2, 0xCBFE,
+	0x6AA3, 0xEDEA, 0x6AB3, 0xDEB1, 0x6ABB, 0xF9E3, 0x6AC2, 0xD4A2,	0x6AC3, 0xCFF6, 0x6AD3, 0xD6D0, 0x6ADA, 0xD5EA, 0x6ADB, 0xF1EE,
+	0x6AF6, 0xFACB, 0x6AFB, 0xE5A1, 0x6B04, 0xD5B1, 0x6B0A, 0xCFED,	0x6B0C, 0xEDEB, 0x6B12, 0xD5B2, 0x6B16, 0xD5BC, 0x6B20, 0xFDE2,
+	0x6B21, 0xF3AD, 0x6B23, 0xFDDB, 0x6B32, 0xE9B0, 0x6B3A, 0xD1A7,	0x6B3D, 0xFDE3, 0x6B3E, 0xCEB3, 0x6B46, 0xFDE4, 0x6B47, 0xFACE,
+	0x6B4C, 0xCAB0, 0x6B4E, 0xF7A7, 0x6B50, 0xCFB1, 0x6B5F, 0xE6A2,	0x6B61, 0xFCB6, 0x6B62, 0xF2AD, 0x6B63, 0xEFE1, 0x6B64, 0xF3AE,
+	0x6B65, 0xDCC6, 0x6B66, 0xD9EB, 0x6B6A, 0xE8E0, 0x6B72, 0xE1A8,	0x6B77, 0xD5F6, 0x6B78, 0xCFFD, 0x6B7B, 0xDEDD, 0x6B7F, 0xD9D1,
+	0x6B83, 0xE4EA, 0x6B84, 0xF2CF, 0x6B86, 0xF7BF, 0x6B89, 0xE2E6,	0x6B8A, 0xE2A8, 0x6B96, 0xE3D6, 0x6B98, 0xEDD1, 0x6B9E, 0xE9F9,
+	0x6BAE, 0xD6B1, 0x6BAF, 0xDEB2, 0x6BB2, 0xE0E8, 0x6BB5, 0xD3AB,	0x6BB7, 0xEBDC, 0x6BBA, 0xDFAF, 0x6BBC, 0xCAC3, 0x6BBF, 0xEEFC,
+	0x6BC1, 0xFDC3, 0x6BC5, 0xEBF6, 0x6BC6, 0xCFB2, 0x6BCB, 0xD9EC,	0x6BCD, 0xD9BD, 0x6BCF, 0xD8DF, 0x6BD2, 0xD4B8, 0x6BD3, 0xEBBE,
+	0x6BD4, 0xDDEF, 0x6BD6, 0xDDF0, 0x6BD7, 0xDDF1, 0x6BD8, 0xDDF2,	0x6BDB, 0xD9BE, 0x6BEB, 0xFBC6, 0x6BEC, 0xCFB3, 0x6C08, 0xEEFD,
+	0x6C0F, 0xE4AB, 0x6C11, 0xDAC5, 0x6C13, 0xD8EC, 0x6C23, 0xD1A8,	0x6C34, 0xE2A9, 0x6C37, 0xDEBC, 0x6C38, 0xE7B5, 0x6C3E, 0xDBF0,
+	0x6C40, 0xEFE2, 0x6C41, 0xF1F0, 0x6C42, 0xCFB4, 0x6C4E, 0xDBF1,	0x6C50, 0xE0B1, 0x6C55, 0xDFA5, 0x6C57, 0xF9D2, 0x6C5A, 0xE7FD,
+	0x6C5D, 0xE6A3, 0x6C5E, 0xFBF1, 0x6C5F, 0xCBB0, 0x6C60, 0xF2AE,	0x6C68, 0xCDE7, 0x6C6A, 0xE8DC, 0x6C6D, 0xE7D7, 0x6C70, 0xF7C0,
+	0x6C72, 0xD0E3, 0x6C76, 0xDAA1, 0x6C7A, 0xCCBD, 0x6C7D, 0xD1A9,	0x6C7E, 0xDDCC, 0x6C81, 0xE3FE, 0x6C82, 0xD1AA, 0x6C83, 0xE8AA,
+	0x6C85, 0xEAB6, 0x6C86, 0xF9FA, 0x6C87, 0xE6CC, 0x6C88, 0xF6D8,	0x6C8C, 0xD4C7, 0x6C90, 0xD9CB, 0x6C92, 0xD9D2, 0x6C93, 0xD3CB,
+	0x6C94, 0xD8F7, 0x6C95, 0xDAA9, 0x6C96, 0xF5F8, 0x6C99, 0xDEDE,	0x6C9A, 0xF2AF, 0x6C9B, 0xF8A9, 0x6CAB, 0xD8C8, 0x6CAE, 0xEEC1,
+	0x6CB3, 0xF9C1, 0x6CB8, 0xDDF3, 0x6CB9, 0xEAFA, 0x6CBB, 0xF6BD,	0x6CBC, 0xE1BB, 0x6CBD, 0xCDBF, 0x6CBE, 0xF4D4, 0x6CBF, 0xE6CD,
+	0x6CC1, 0xFCCF, 0x6CC2, 0xFBA2, 0x6CC4, 0xE0DC, 0x6CC9, 0xF4BB,	0x6CCA, 0xDAD5, 0x6CCC, 0xF9B2, 0x6CD3, 0xFBF2, 0x6CD5, 0xDBF6,
+	0x6CD7, 0xDEDF, 0x6CDB, 0xDBF2, 0x6CE1, 0xF8DC, 0x6CE2, 0xF7EE,	0x6CE3, 0xEBE8, 0x6CE5, 0xD2FA, 0x6CE8, 0xF1BC, 0x6CEB, 0xFADA,
+	0x6CEE, 0xDAEA, 0x6CEF, 0xDAC6, 0x6CF0, 0xF7C1, 0x6CF3, 0xE7B6,	0x6D0B, 0xE5C7, 0x6D0C, 0xD6AC, 0x6D11, 0xDCC7, 0x6D17, 0xE1A9,
+	0x6D19, 0xE2AA, 0x6D1B, 0xD5A6, 0x6D1E, 0xD4D7, 0x6D25, 0xF2D0,	0x6D27, 0xEAFB, 0x6D29, 0xE0DD, 0x6D2A, 0xFBF3, 0x6D32, 0xF1BD,
+	0x6D35, 0xE2E7, 0x6D36, 0xFDD7, 0x6D38, 0xCEC8, 0x6D39, 0xEAB7,	0x6D3B, 0xFCC0, 0x6D3D, 0xFDE7, 0x6D3E, 0xF7EF, 0x6D41, 0xD7B5,
+	0x6D59, 0xEFBA, 0x6D5A, 0xF1DD, 0x6D5C, 0xDEB3, 0x6D63, 0xE8CB,	0x6D66, 0xF8DD, 0x6D69, 0xFBC7, 0x6D6A, 0xD5C8, 0x6D6C, 0xD7DF,
+	0x6D6E, 0xDDA9, 0x6D74, 0xE9B1, 0x6D77, 0xFAAD, 0x6D78, 0xF6D9,	0x6D79, 0xFAF4, 0x6D7F, 0xF8AA, 0x6D85, 0xE6EE, 0x6D87, 0xCCDC,
+	0x6D88, 0xE1BC, 0x6D89, 0xE0EF, 0x6D8C, 0xE9BF, 0x6D8D, 0xFCFD,	0x6D8E, 0xE6CE, 0x6D91, 0xE1D7, 0x6D93, 0xE6CF, 0x6D95, 0xF4F1,
+	0x6DAF, 0xE4F3, 0x6DB2, 0xE4FB, 0x6DB5, 0xF9E4, 0x6DC0, 0xEFE3,	0x6DC3, 0xCFEE, 0x6DC4, 0xF6BE, 0x6DC5, 0xE0B2, 0x6DC6, 0xFCFE,
+	0x6DC7, 0xD1AB, 0x6DCB, 0xD7FA, 0x6DCF, 0xFBC8, 0x6DD1, 0xE2D7,	0x6DD8, 0xD4A3, 0x6DD9, 0xF0F8, 0x6DDA, 0xD7A8, 0x6DDE, 0xE1E7,
+	0x6DE1, 0xD3BF, 0x6DE8, 0xEFE4, 0x6DEA, 0xD7C5, 0x6DEB, 0xEBE2,	0x6DEE, 0xFCE7, 0x6DF1, 0xE4A2, 0x6DF3, 0xE2E8, 0x6DF5, 0xE6D0,
+	0x6DF7, 0xFBE8, 0x6DF8, 0xF4E8, 0x6DF9, 0xE5F4, 0x6DFA, 0xF4BC,	0x6DFB, 0xF4D5, 0x6E17, 0xDFB6, 0x6E19, 0xFCB9, 0x6E1A, 0xEEC2,
+	0x6E1B, 0xCAF5, 0x6E1F, 0xEFE5, 0x6E20, 0xCBE2, 0x6E21, 0xD4A4,	0x6E23, 0xDEE0, 0x6E24, 0xDAFD, 0x6E25, 0xE4C6, 0x6E26, 0xE8BE,
+	0x6E2B, 0xE0DE, 0x6E2C, 0xF6B4, 0x6E2D, 0xEAD2, 0x6E2F, 0xF9FB,	0x6E32, 0xE0C2, 0x6E34, 0xCAE4, 0x6E36, 0xE7B7, 0x6E38, 0xEAFD,
+	0x6E3A, 0xD9DD, 0x6E3C, 0xDAB4, 0x6E3D, 0xEEAA, 0x6E3E, 0xFBE9,	0x6E43, 0xDBCB, 0x6E44, 0xDAB5, 0x6E4A, 0xF1BE, 0x6E4D, 0xD3AC,
+	0x6E56, 0xFBC9, 0x6E58, 0xDFCF, 0x6E5B, 0xD3C0, 0x6E5C, 0xE3D7,	0x6E5E, 0xEFE6, 0x6E5F, 0xFCD0, 0x6E67, 0xE9C0, 0x6E6B, 0xF5D3,
+	0x6E6E, 0xECDC, 0x6E6F, 0xF7B7, 0x6E72, 0xEAB8, 0x6E73, 0xD1F9,	0x6E7A, 0xDCC8, 0x6E90, 0xEAB9, 0x6E96, 0xF1DE, 0x6E9C, 0xD7B6,
+	0x6E9D, 0xCFB5, 0x6E9F, 0xD9A8, 0x6EA2, 0xECEE, 0x6EA5, 0xDDAA,	0x6EAA, 0xCDA2, 0x6EAB, 0xE8AE, 0x6EAF, 0xE1BD, 0x6EB1, 0xF2D1,
+	0x6EB6, 0xE9C1, 0x6EBA, 0xD2FC, 0x6EC2, 0xDBB5, 0x6EC4, 0xF3E7,	0x6EC5, 0xD8FE, 0x6EC9, 0xFCD1, 0x6ECB, 0xEDB2, 0x6ECC, 0xF4AF,
+	0x6ECE, 0xFBA3, 0x6ED1, 0xFCC1, 0x6ED3, 0xEEAB, 0x6ED4, 0xD4A5,	0x6EEF, 0xF4F2, 0x6EF4, 0xEED9, 0x6EF8, 0xFBCA, 0x6EFE, 0xCDE3,
+	0x6EFF, 0xD8BB, 0x6F01, 0xE5DB, 0x6F02, 0xF8F7, 0x6F06, 0xF6D4,	0x6F0F, 0xD7A9, 0x6F11, 0xCBC9, 0x6F14, 0xE6D1, 0x6F15, 0xF0CC,
+	0x6F20, 0xD8AE, 0x6F22, 0xF9D3, 0x6F23, 0xD5FE, 0x6F2B, 0xD8BC,	0x6F2C, 0xF2B0, 0x6F31, 0xE2AB, 0x6F32, 0xF3E8, 0x6F38, 0xEFC2,
+	0x6F3F, 0xEDEC, 0x6F41, 0xE7B8, 0x6F51, 0xDAFE, 0x6F54, 0xCCBE,	0x6F57, 0xF2FC, 0x6F58, 0xDAEB, 0x6F5A, 0xE2D8, 0x6F5B, 0xEDD6,
+	0x6F5E, 0xD6D1, 0x6F5F, 0xE0B3, 0x6F62, 0xFCD2, 0x6F64, 0xEBC8,	0x6F6D, 0xD3C1, 0x6F6E, 0xF0CD, 0x6F70, 0xCFF7, 0x6F7A, 0xEDD2,
+	0x6F7C, 0xD4D8, 0x6F7D, 0xDCC9, 0x6F7E, 0xD7F1, 0x6F81, 0xDFBB,	0x6F84, 0xF3A5, 0x6F88, 0xF4CD, 0x6F8D, 0xF1BF, 0x6F8E, 0xF8B1,
+	0x6F90, 0xE9FA, 0x6F94, 0xFBCB, 0x6F97, 0xCAD5, 0x6FA3, 0xF9D4,	0x6FA4, 0xF7CA, 0x6FA7, 0xD6C8, 0x6FAE, 0xFCE8, 0x6FAF, 0xF3BD,
+	0x6FB1, 0xEEFE, 0x6FB3, 0xE7FE, 0x6FB9, 0xD3C2, 0x6FBE, 0xD3B6,	0x6FC0, 0xCCAD, 0x6FC1, 0xF6FA, 0x6FC2, 0xD6B2, 0x6FC3, 0xD2D8,
+	0x6FCA, 0xE7D8, 0x6FD5, 0xE3A5, 0x6FDA, 0xE7B9, 0x6FDF, 0xF0AD,	0x6FE0, 0xFBCC, 0x6FE1, 0xEBA1, 0x6FE4, 0xD4A6, 0x6FE9, 0xFBCD,
+	0x6FEB, 0xD5BD, 0x6FEC, 0xF1DF, 0x6FEF, 0xF6FB, 0x6FF1, 0xDEB4,	0x6FFE, 0xD5EB, 0x7001, 0xE5C8, 0x7005, 0xFBA4, 0x7006, 0xD4B9,
+	0x7009, 0xDEE1, 0x700B, 0xE4A3, 0x700F, 0xD7B7, 0x7011, 0xF8EE,	0x7015, 0xDEB5, 0x7018, 0xD6D2, 0x701A, 0xF9D5, 0x701B, 0xE7BA,
+	0x701C, 0xEBD5, 0x701D, 0xD5F7, 0x701E, 0xEFE7, 0x701F, 0xE1BE,	0x7023, 0xFAAE, 0x7027, 0xD6E9, 0x7028, 0xD6EE, 0x702F, 0xE7BB,
+	0x7037, 0xECCB, 0x703E, 0xD5B3, 0x704C, 0xCEB4, 0x7050, 0xFBA5,	0x7051, 0xE1EE, 0x7058, 0xF7A8, 0x705D, 0xFBCE, 0x7063, 0xD8BD,
+	0x706B, 0xFBFD, 0x7070, 0xFCE9, 0x7078, 0xCFB6, 0x707C, 0xEDC7,	0x707D, 0xEEAC, 0x7085, 0xCCDD, 0x708A, 0xF6A7, 0x708E, 0xE6FA,
+	0x7092, 0xF5A4, 0x7098, 0xFDDC, 0x7099, 0xEDB3, 0x709A, 0xCEC9,	0x70A1, 0xEFE8, 0x70A4, 0xE1BF, 0x70AB, 0xFADB, 0x70AC, 0xCBE3,
+	0x70AD, 0xF7A9, 0x70AF, 0xFBA6, 0x70B3, 0xDCB9, 0x70B7, 0xF1C0,	0x70B8, 0xEDC8, 0x70B9, 0xEFC3, 0x70C8, 0xD6AD, 0x70CB, 0xFDCE,
+	0x70CF, 0xE8A1, 0x70D8, 0xFBF4, 0x70D9, 0xD5A7, 0x70DD, 0xF1F6,	0x70DF, 0xE6D3, 0x70F1, 0xCCDE, 0x70F9, 0xF8B2, 0x70FD, 0xDCEB,
+	0x7104, 0xFDB6, 0x7109, 0xE5EA, 0x710C, 0xF1E0, 0x7119, 0xDBCC,	0x711A, 0xDDCD, 0x711E, 0xD4C8, 0x7121, 0xD9ED, 0x7126, 0xF5A5,
+	0x7130, 0xE6FB, 0x7136, 0xE6D4, 0x7147, 0xFDC8, 0x7149, 0xD6A1,	0x714A, 0xFDBF, 0x714C, 0xFCD3, 0x714E, 0xEFA1, 0x7150, 0xE7BC,
+	0x7156, 0xD1EE, 0x7159, 0xE6D5, 0x715C, 0xE9F2, 0x715E, 0xDFB0,	0x7164, 0xD8E0, 0x7165, 0xFCBA, 0x7166, 0xFDAF, 0x7167, 0xF0CE,
+	0x7169, 0xDBE1, 0x716C, 0xE5C9, 0x716E, 0xEDB4, 0x717D, 0xE0C3,	0x7184, 0xE3D8, 0x7189, 0xE9FB, 0x718A, 0xEAA8, 0x718F, 0xFDB7,
+	0x7192, 0xFBA7, 0x7194, 0xE9C2, 0x7199, 0xFDF7, 0x719F, 0xE2D9,	0x71A2, 0xDCEC, 0x71AC, 0xE8A2, 0x71B1, 0xE6F0, 0x71B9, 0xFDF8,
+	0x71BA, 0xFDF9, 0x71BE, 0xF6BF, 0x71C1, 0xE7A7, 0x71C3, 0xE6D7,	0x71C8, 0xD4F3, 0x71C9, 0xD4C9, 0x71CE, 0xD6FA, 0x71D0, 0xD7F2,
+	0x71D2, 0xE1C0, 0x71D4, 0xDBE2, 0x71D5, 0xE6D8, 0x71DF, 0xE7BD,	0x71E5, 0xF0CF, 0x71E6, 0xF3BE, 0x71E7, 0xE2AC, 0x71ED, 0xF5B7,
+	0x71EE, 0xE0F0, 0x71FB, 0xFDB8, 0x71FC, 0xE3E8, 0x71FE, 0xD4A7,	0x71FF, 0xE8FC, 0x7200, 0xFAD2, 0x7206, 0xF8EF, 0x7210, 0xD6D3,
+	0x721B, 0xD5B4, 0x722A, 0xF0D0, 0x722C, 0xF7F0, 0x722D, 0xEEB3,	0x7230, 0xEABA, 0x7232, 0xEAD3, 0x7235, 0xEDC9, 0x7236, 0xDDAB,
+	0x723A, 0xE5AC, 0x723B, 0xFDA1, 0x723D, 0xDFD0, 0x723E, 0xECB3,	0x7240, 0xDFD1, 0x7246, 0xEDED, 0x7247, 0xF8B8, 0x7248, 0xF7FA,
+	0x724C, 0xF8AB, 0x7252, 0xF4E0, 0x7258, 0xD4BA, 0x7259, 0xE4B3,	0x725B, 0xE9DA, 0x725D, 0xDEB6, 0x725F, 0xD9BF, 0x7261, 0xD9C0,
+	0x7262, 0xD6EF, 0x7267, 0xD9CC, 0x7269, 0xDAAA, 0x7272, 0xDFE5,	0x7279, 0xF7E5, 0x727D, 0xCCB2, 0x7280, 0xDFF9, 0x7281, 0xD7E0,
+	0x72A2, 0xD4BB, 0x72A7, 0xFDFA, 0x72AC, 0xCCB3, 0x72AF, 0xDBF3,	0x72C0, 0xDFD2, 0x72C2, 0xCECA, 0x72C4, 0xEEDA, 0x72CE, 0xE4E4,
+	0x72D0, 0xFBCF, 0x72D7, 0xCFB7, 0x72D9, 0xEEC3, 0x72E1, 0xCEEA,	0x72E9, 0xE2AD, 0x72F8, 0xD7E1, 0x72F9, 0xFAF5, 0x72FC, 0xD5C9,
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+	0x7E09, 0xF2DB, 0x7E0A, 0xE4FC, 0x7E15, 0xE8B2, 0x7E1B, 0xDADA,	0x7E1D, 0xF2DC, 0x7E1E, 0xFBD6, 0x7E1F, 0xE9B2, 0x7E21, 0xEEAD,
+	0x7E23, 0xFAE3, 0x7E2B, 0xDCEE, 0x7E2E, 0xF5EA, 0x7E2F, 0xE6E0,	0x7E31, 0xF0FD, 0x7E37, 0xD7AC, 0x7E3D, 0xF5C5, 0x7E3E, 0xEEE0,
+	0x7E41, 0xDBE5, 0x7E43, 0xDDDE, 0x7E46, 0xD9F0, 0x7E47, 0xE9A3,	0x7E52, 0xF1F9, 0x7E54, 0xF2C4, 0x7E55, 0xE0CB, 0x7E5E, 0xE9A4,
+	0x7E61, 0xE2B9, 0x7E69, 0xE3B1, 0x7E6A, 0xFCEB, 0x7E6B, 0xCDA8,	0x7E6D, 0xCCB6, 0x7E70, 0xF0DB, 0x7E79, 0xE6BA, 0x7E7C, 0xCDA9,
+	0x7E82, 0xF3C3, 0x7E8C, 0xE1D9, 0x7E8F, 0xEFAB, 0x7E93, 0xE7C5,	0x7E96, 0xE0E9, 0x7E98, 0xF3C5, 0x7E9B, 0xD4C0, 0x7E9C, 0xD5BF,
+	0x7F36, 0xDDAE, 0x7F38, 0xF9FC, 0x7F3A, 0xCCC0, 0x7F4C, 0xE5A2,	0x7F50, 0xCEB8, 0x7F54, 0xD8D2, 0x7F55, 0xF9D6, 0x7F6A, 0xF1AA,
+	0x7F6B, 0xCED1, 0x7F6E, 0xF6C7, 0x7F70, 0xDBEB, 0x7F72, 0xDFFE,	0x7F75, 0xD8E1, 0x7F77, 0xF7F3, 0x7F79, 0xD7E7, 0x7F85, 0xD4FE,
+	0x7F88, 0xD1BC, 0x7F8A, 0xE5CF, 0x7F8C, 0xCBB6, 0x7F8E, 0xDAB8,	0x7F94, 0xCDC4, 0x7F9A, 0xD6BE, 0x7F9E, 0xE2BA, 0x7FA4, 0xCFD8,
+	0x7FA8, 0xE0CC, 0x7FA9, 0xEBF9, 0x7FB2, 0xFDFD, 0x7FB8, 0xD7E8,	0x7FB9, 0xCBD8, 0x7FBD, 0xE9E2, 0x7FC1, 0xE8BA, 0x7FC5, 0xE3C7,
+	0x7FCA, 0xECCD, 0x7FCC, 0xECCE, 0x7FCE, 0xD6BF, 0x7FD2, 0xE3A7,	0x7FD4, 0xDFD6, 0x7FD5, 0xFDE8, 0x7FDF, 0xEEE1, 0x7FE0, 0xF6A8,
+	0x7FE1, 0xDDFD, 0x7FE9, 0xF8BB, 0x7FEB, 0xE8D1, 0x7FF0, 0xF9D7,	0x7FF9, 0xCEEE, 0x7FFC, 0xECCF, 0x8000, 0xE9A5, 0x8001, 0xD6D5,
+	0x8003, 0xCDC5, 0x8005, 0xEDBA, 0x8006, 0xD1BD, 0x8009, 0xCFBE,	0x800C, 0xECBB, 0x8010, 0xD2B1, 0x8015, 0xCCE9, 0x8017, 0xD9C4,
+	0x8018, 0xE9FC, 0x802D, 0xD1BE, 0x8033, 0xECBC, 0x8036, 0xE5AD,	0x803D, 0xF7B0, 0x803F, 0xCCEA, 0x8043, 0xD3C4, 0x8046, 0xD6C0,
+	0x804A, 0xD6FD, 0x8056, 0xE1A1, 0x8058, 0xDEBD, 0x805A, 0xF6A9,	0x805E, 0xDAA4, 0x806F, 0xD6A4, 0x8070, 0xF5C6, 0x8072, 0xE1A2,
+	0x8073, 0xE9C6, 0x8077, 0xF2C5, 0x807D, 0xF4E9, 0x807E, 0xD6EC,	0x807F, 0xEBD3, 0x8084, 0xECBD, 0x8085, 0xE2DC, 0x8086, 0xDEEB,
+	0x8087, 0xF0DC, 0x8089, 0xEBBF, 0x808B, 0xD7CE, 0x808C, 0xD1BF,	0x8096, 0xF5AB, 0x809B, 0xF9FD, 0x809D, 0xCADC, 0x80A1, 0xCDC6,
+	0x80A2, 0xF2B6, 0x80A5, 0xDDFE, 0x80A9, 0xCCB7, 0x80AA, 0xDBB8,	0x80AF, 0xD0E9, 0x80B1, 0xCEDD, 0x80B2, 0xEBC0, 0x80B4, 0xFDA2,
+	0x80BA, 0xF8CB, 0x80C3, 0xEAD6, 0x80C4, 0xF1B0, 0x80CC, 0xDBCE,	0x80CE, 0xF7C3, 0x80DA, 0xDBCF, 0x80DB, 0xCBA4, 0x80DE, 0xF8E0,
+	0x80E1, 0xFBD7, 0x80E4, 0xEBCA, 0x80E5, 0xE0A1, 0x80F1, 0xCECD,	0x80F4, 0xD4DC, 0x80F8, 0xFDD8, 0x80FD, 0xD2F6, 0x8102, 0xF2B7,
+	0x8105, 0xFAF6, 0x8106, 0xF6AA, 0x8107, 0xFAF7, 0x8108, 0xD8E6,	0x810A, 0xF4B1, 0x8118, 0xE8D2, 0x811A, 0xCAC5, 0x811B, 0xCCEB,
+	0x8123, 0xE2EE, 0x8129, 0xE2BB, 0x812B, 0xF7AD, 0x812F, 0xF8E1,	0x8139, 0xF3EC, 0x813E, 0xDEA1, 0x814B, 0xE4FD, 0x814E, 0xE3EC,
+	0x8150, 0xDDAF, 0x8151, 0xDDB0, 0x8154, 0xCBB7, 0x8155, 0xE8D3,	0x8165, 0xE1A3, 0x8166, 0xD2E0, 0x816B, 0xF0FE, 0x8170, 0xE9A6,
+	0x8171, 0xCBF2, 0x8178, 0xEDF3, 0x8179, 0xDCD9, 0x817A, 0xE0CD,	0x817F, 0xF7DA, 0x8180, 0xDBB9, 0x8188, 0xCCAE, 0x818A, 0xDADB,
+	0x818F, 0xCDC7, 0x819A, 0xDDB1, 0x819C, 0xD8AF, 0x819D, 0xE3A3,	0x81A0, 0xCEEF, 0x81A3, 0xF2F3, 0x81A8, 0xF8B3, 0x81B3, 0xE0CE,
+	0x81B5, 0xF5FD, 0x81BA, 0xEBEC, 0x81BD, 0xD3C5, 0x81BE, 0xFCEC,	0x81BF, 0xD2DB, 0x81C0, 0xD4EB, 0x81C2, 0xDEA2, 0x81C6, 0xE5E6,
+	0x81CD, 0xF0B0, 0x81D8, 0xD5C4, 0x81DF, 0xEDF4, 0x81E3, 0xE3ED,	0x81E5, 0xE8C2, 0x81E7, 0xEDF5, 0x81E8, 0xD7FC, 0x81EA, 0xEDBB,
+	0x81ED, 0xF6AB, 0x81F3, 0xF2B8, 0x81F4, 0xF6C8, 0x81FA, 0xD3E6,	0x81FB, 0xF2DD, 0x81FC, 0xCFBF, 0x81FE, 0xEBAC, 0x8205, 0xCFC0,
+	0x8207, 0xE6A8, 0x8208, 0xFDE9, 0x820A, 0xCFC1, 0x820C, 0xE0DF,	0x820D, 0xDEEC, 0x8212, 0xE0A2, 0x821B, 0xF4BF, 0x821C, 0xE2EF,
+	0x821E, 0xD9F1, 0x821F, 0xF1C7, 0x8221, 0xCBB8, 0x822A, 0xF9FE,	0x822B, 0xDBBA, 0x822C, 0xDAF5, 0x8235, 0xF6EC, 0x8236, 0xDADC,
+	0x8237, 0xFAE4, 0x8239, 0xE0CF, 0x8240, 0xDDB2, 0x8245, 0xE6A9,	0x8247, 0xEFF3, 0x8259, 0xF3ED, 0x8264, 0xEBFA, 0x8266, 0xF9E6,
+	0x826E, 0xCADD, 0x826F, 0xD5DE, 0x8271, 0xCADE, 0x8272, 0xDFE4,	0x8276, 0xE6FD, 0x8278, 0xF5AC, 0x827E, 0xE4F5, 0x828B, 0xE9E3,
+	0x828D, 0xEDCB, 0x828E, 0xCFE4, 0x8292, 0xD8D3, 0x8299, 0xDDB3,	0x829A, 0xD4EC, 0x829D, 0xF2B9, 0x829F, 0xDFB7, 0x82A5, 0xCBCE,
+	0x82A6, 0xFBD8, 0x82A9, 0xD0D9, 0x82AC, 0xDDD2, 0x82AD, 0xF7F4,	0x82AE, 0xE7DC, 0x82AF, 0xE4A5, 0x82B1, 0xFCA3, 0x82B3, 0xDBBB,
+	0x82B7, 0xF2BA, 0x82B8, 0xE9FD, 0x82B9, 0xD0CA, 0x82BB, 0xF5D6,	0x82BC, 0xD9C5, 0x82BD, 0xE4B4, 0x82BF, 0xEDA7, 0x82D1, 0xEABD,
+	0x82D2, 0xE6FE, 0x82D4, 0xF7C4, 0x82D5, 0xF5AD, 0x82D7, 0xD9E0,	0x82DB, 0xCAB4, 0x82DE, 0xF8E2, 0x82DF, 0xCFC2, 0x82E1, 0xECBE,
+	0x82E5, 0xE5B4, 0x82E6, 0xCDC8, 0x82E7, 0xEEC8, 0x82F1, 0xE7C8,	0x82FD, 0xCDC9, 0x82FE, 0xF9B7, 0x8301, 0xF1E8, 0x8302, 0xD9F2,
+	0x8303, 0xDBF5, 0x8304, 0xCAB5, 0x8305, 0xD9C6, 0x8309, 0xD8C9,	0x8317, 0xD9AB, 0x8328, 0xEDBC, 0x832B, 0xD8D4, 0x832F, 0xDCDA,
+	0x8331, 0xE2BC, 0x8334, 0xFCED, 0x8335, 0xECE0, 0x8336, 0xD2FE,	0x8338, 0xE9C7, 0x8339, 0xE6AA, 0x8340, 0xE2F0, 0x8347, 0xFABB,
+	0x8349, 0xF5AE, 0x834A, 0xFBAA, 0x834F, 0xECFB, 0x8351, 0xECBF,	0x8352, 0xFCD8, 0x8373, 0xD4E5, 0x8377, 0xF9C3, 0x837B, 0xEEE2,
+	0x8389, 0xD7E9, 0x838A, 0xEDF6, 0x838E, 0xDEED, 0x8396, 0xCCEC,	0x8398, 0xE3EE, 0x839E, 0xE8D4, 0x83A2, 0xFAF8, 0x83A9, 0xDDB4,
+	0x83AA, 0xE4B5, 0x83AB, 0xD8B0, 0x83BD, 0xD8D5, 0x83C1, 0xF4EA,	0x83C5, 0xCEB9, 0x83C9, 0xD6E1, 0x83CA, 0xCFD2, 0x83CC, 0xD0B6,
+	0x83D3, 0xCEA2, 0x83D6, 0xF3EE, 0x83DC, 0xF3F8, 0x83E9, 0xDCCC,	0x83EB, 0xD0CB, 0x83EF, 0xFCA4, 0x83F0, 0xCDCA, 0x83F1, 0xD7D4,
+	0x83F2, 0xDEA3, 0x83F4, 0xE4E0, 0x83F9, 0xEEC9, 0x83FD, 0xE2DD,	0x8403, 0xF5FE, 0x8404, 0xD4AC, 0x840A, 0xD5D1, 0x840C, 0xD8F0,
+	0x840D, 0xF8C3, 0x840E, 0xEAD7, 0x8429, 0xF5D7, 0x842C, 0xD8BF,	0x8431, 0xFDC0, 0x8438, 0xEBAD, 0x843D, 0xD5AA, 0x8449, 0xE7A8,
+	0x8457, 0xEECA, 0x845B, 0xCAE7, 0x8461, 0xF8E3, 0x8463, 0xD4DD,	0x8466, 0xEAD8, 0x846B, 0xFBD9, 0x846C, 0xEDF7, 0x846F, 0xE5B5,
+	0x8475, 0xD0AD, 0x847A, 0xF1F1, 0x8490, 0xE2BD, 0x8494, 0xE3C8,	0x8499, 0xD9D5, 0x849C, 0xDFAA, 0x84A1, 0xDBBC, 0x84B2, 0xF8E4,
+	0x84B8, 0xF1FA, 0x84BB, 0xE5B6, 0x84BC, 0xF3EF, 0x84BF, 0xFBDA,	0x84C0, 0xE1E0, 0x84C2, 0xD9AC, 0x84C4, 0xF5EB, 0x84C6, 0xE0B6,
+	0x84C9, 0xE9C8, 0x84CB, 0xCBCF, 0x84CD, 0xE3C9, 0x84D1, 0xDEEE,	0x84DA, 0xE2BE, 0x84EC, 0xDCEF, 0x84EE, 0xD6A5, 0x84F4, 0xE2F1,
+	0x84FC, 0xD6FE, 0x8511, 0xD9A1, 0x8513, 0xD8C0, 0x8514, 0xDCDB,	0x8517, 0xEDBD, 0x8518, 0xDFB8, 0x851A, 0xEAA5, 0x851E, 0xD7AD,
+	0x8521, 0xF3F9, 0x8523, 0xEDF8, 0x8525, 0xF5C7, 0x852C, 0xE1CA,	0x852D, 0xEBE3, 0x852F, 0xF2DE, 0x853D, 0xF8CC, 0x853F, 0xEAD9,
+	0x8541, 0xD3C6, 0x8543, 0xDBE6, 0x8549, 0xF5AF, 0x854E, 0xCEF0,	0x8553, 0xE9FE, 0x8559, 0xFBB6, 0x8563, 0xE2F2, 0x8568, 0xCFF2,
+	0x8569, 0xF7B9, 0x856A, 0xD9F3, 0x856D, 0xE1CB, 0x8584, 0xDADD,	0x8587, 0xDAB9, 0x858F, 0xEBFB, 0x8591, 0xCBB9, 0x8594, 0xEDF9,
+	0x859B, 0xE0E0, 0x85A6, 0xF4C0, 0x85A8, 0xFDBC, 0x85A9, 0xDFB1,	0x85AA, 0xE3EF, 0x85AF, 0xE0A3, 0x85B0, 0xFDB9, 0x85BA, 0xF0B1,
+	0x85C1, 0xCDCB, 0x85C9, 0xEDBE, 0x85CD, 0xD5C0, 0x85CE, 0xE3F0,	0x85CF, 0xEDFA, 0x85D5, 0xE9E4, 0x85DC, 0xD5ED, 0x85DD, 0xE7DD,
+	0x85E4, 0xD4F6, 0x85E5, 0xE5B7, 0x85E9, 0xDBE7, 0x85EA, 0xE2BF,	0x85F7, 0xEECB, 0x85FA, 0xD7F4, 0x85FB, 0xF0DD, 0x85FF, 0xCEAB,
+	0x8602, 0xE7DE, 0x8606, 0xD6D6, 0x8607, 0xE1CC, 0x860A, 0xE8B3,	0x8616, 0xE5EE, 0x8617, 0xDCA2, 0x861A, 0xE0D0, 0x862D, 0xD5B5,
+	0x863F, 0xD5A1, 0x864E, 0xFBDB, 0x8650, 0xF9CB, 0x8654, 0xCBF3,	0x8655, 0xF4A5, 0x865B, 0xFAC8, 0x865C, 0xD6D7, 0x865E, 0xE9E5,
+	0x865F, 0xFBDC, 0x8667, 0xFDD0, 0x8679, 0xFBF6, 0x868A, 0xDAA5,	0x868C, 0xDBBD, 0x8693, 0xECE2, 0x86A3, 0xCDF7, 0x86A4, 0xF0DE,
+	0x86A9, 0xF6C9, 0x86C7, 0xDEEF, 0x86CB, 0xD3B1, 0x86D4, 0xFCEE,	0x86D9, 0xE8C3, 0x86DB, 0xF1C8, 0x86DF, 0xCEF1, 0x86E4, 0xF9ED,
+	0x86ED, 0xF2F4, 0x86FE, 0xE4B6, 0x8700, 0xF5B9, 0x8702, 0xDCF0,	0x8703, 0xE3F1, 0x8708, 0xE8A5, 0x8718, 0xF2BB, 0x871A, 0xDEA4,
+	0x871C, 0xDACC, 0x874E, 0xCAE9, 0x8755, 0xE3DA, 0x8757, 0xFCD9,	0x875F, 0xEADA, 0x8766, 0xF9C4, 0x8768, 0xE3A4, 0x8774, 0xFBDD,
+	0x8776, 0xEFCA, 0x8778, 0xE8C4, 0x8782, 0xD5CC, 0x878D, 0xEBD7,	0x879F, 0xD9AD, 0x87A2, 0xFBAB, 0x87B3, 0xD3D9, 0x87BA, 0xD5A2,
+	0x87C4, 0xF6DE, 0x87E0, 0xDAF6, 0x87EC, 0xE0D1, 0x87EF, 0xE9A8,	0x87F2, 0xF5F9, 0x87F9, 0xFAAF, 0x87FB, 0xEBFC, 0x87FE, 0xE0EA,
+	0x8805, 0xE3B2, 0x881F, 0xD5C5, 0x8822, 0xF1E3, 0x8823, 0xD5EE,	0x8831, 0xCDCC, 0x8836, 0xEDD9, 0x883B, 0xD8C1, 0x8840, 0xFAEC,
+	0x8846, 0xF1EB, 0x884C, 0xFABC, 0x884D, 0xE6E2, 0x8852, 0xFAE5,	0x8853, 0xE2FA, 0x8857, 0xCAB6, 0x8859, 0xE4B7, 0x885B, 0xEADB,
+	0x885D, 0xF5FA, 0x8861, 0xFBAC, 0x8862, 0xCFC3, 0x8863, 0xEBFD,	0x8868, 0xF8FA, 0x886B, 0xDFB9, 0x8870, 0xE1F1, 0x8872, 0xD2A4,
+	0x8877, 0xF5FB, 0x887E, 0xD0DA, 0x887F, 0xD0DB, 0x8881, 0xEABE,	0x8882, 0xD9B1, 0x8888, 0xCAB7, 0x888B, 0xD3E7, 0x888D, 0xF8E5,
+	0x8892, 0xD3B2, 0x8896, 0xE2C0, 0x8897, 0xF2DF, 0x889E, 0xCDE5,	0x88AB, 0xF9AC, 0x88B4, 0xCDCD, 0x88C1, 0xEEAE, 0x88C2, 0xD6AE,
+	0x88CF, 0xD7EA, 0x88D4, 0xE7E0, 0x88D5, 0xEBAE, 0x88D9, 0xCFD9,	0x88DC, 0xDCCD, 0x88DD, 0xEDFB, 0x88DF, 0xDEF0, 0x88E1, 0xD7EB,
+	0x88E8, 0xDEA5, 0x88F3, 0xDFD7, 0x88F4, 0xDBD0, 0x88F5, 0xDBD1,	0x88F8, 0xD5A3, 0x88FD, 0xF0B2, 0x8907, 0xDCDC, 0x8910, 0xCAE8,
+	0x8912, 0xF8E6, 0x8913, 0xDCCE, 0x8918, 0xEADC, 0x8919, 0xDBD2,	0x8925, 0xE9B3, 0x892A, 0xF7DB, 0x8936, 0xE3A8, 0x8938, 0xD7AE,
+	0x893B, 0xE0E1, 0x8941, 0xCBBA, 0x8944, 0xE5D1, 0x895F, 0xD0DC,	0x8964, 0xD5C1, 0x896A, 0xD8CA, 0x8972, 0xE3A9, 0x897F, 0xE0A4,
+	0x8981, 0xE9A9, 0x8983, 0xD3C7, 0x8986, 0xDCDD, 0x8987, 0xF8AE,	0x898B, 0xCCB8, 0x898F, 0xD0AE, 0x8993, 0xD8F2, 0x8996, 0xE3CA,
+	0x89A1, 0xCCAF, 0x89A9, 0xD4AD, 0x89AA, 0xF6D1, 0x89B2, 0xD0CC,	0x89BA, 0xCAC6, 0x89BD, 0xD5C2, 0x89C0, 0xCEBA, 0x89D2, 0xCAC7,
+	0x89E3, 0xFAB0, 0x89F4, 0xDFD8, 0x89F8, 0xF5BA, 0x8A00, 0xE5EB,	0x8A02, 0xEFF4, 0x8A03, 0xDDB5, 0x8A08, 0xCDAA, 0x8A0A, 0xE3F2,
+	0x8A0C, 0xFBF7, 0x8A0E, 0xF7D0, 0x8A13, 0xFDBA, 0x8A16, 0xFDE1,	0x8A17, 0xF6FE, 0x8A18, 0xD1C0, 0x8A1B, 0xE8C5, 0x8A1D, 0xE4B8,
+	0x8A1F, 0xE1E8, 0x8A23, 0xCCC1, 0x8A25, 0xD2ED, 0x8A2A, 0xDBBE,	0x8A2D, 0xE0E2, 0x8A31, 0xFAC9, 0x8A34, 0xE1CD, 0x8A36, 0xCAB8,
+	0x8A3A, 0xF2E0, 0x8A3B, 0xF1C9, 0x8A50, 0xDEF1, 0x8A54, 0xF0DF,	0x8A55, 0xF8C4, 0x8A5B, 0xEECC, 0x8A5E, 0xDEF2, 0x8A60, 0xE7C9,
+	0x8A62, 0xE2F3, 0x8A63, 0xE7E1, 0x8A66, 0xE3CB, 0x8A69, 0xE3CC,	0x8A6D, 0xCFF8, 0x8A6E, 0xEFAC, 0x8A70, 0xFDFE, 0x8A71, 0xFCA5,
+	0x8A72, 0xFAB1, 0x8A73, 0xDFD9, 0x8A75, 0xE0D2, 0x8A79, 0xF4DA,	0x8A85, 0xF1CA, 0x8A87, 0xCEA3, 0x8A8C, 0xF2BC, 0x8A8D, 0xECE3,
+	0x8A93, 0xE0A5, 0x8A95, 0xF7AB, 0x8A98, 0xEBAF, 0x8A9E, 0xE5DE,	0x8AA0, 0xE1A4, 0x8AA1, 0xCDAB, 0x8AA3, 0xD9F4, 0x8AA4, 0xE8A6,
+	0x8AA5, 0xCDCE, 0x8AA6, 0xE1E9, 0x8AA8, 0xFCEF, 0x8AAA, 0xE0E3,	0x8AB0, 0xE2C1, 0x8AB2, 0xCEA4, 0x8AB9, 0xDEA6, 0x8ABC, 0xEBFE,
+	0x8ABE, 0xEBDD, 0x8ABF, 0xF0E0, 0x8AC2, 0xF4DB, 0x8AC4, 0xE2F4,	0x8AC7, 0xD3C8, 0x8ACB, 0xF4EB, 0x8ACD, 0xEEB5, 0x8ACF, 0xF5D8,
+	0x8AD2, 0xD5DF, 0x8AD6, 0xD6E5, 0x8ADB, 0xEBB0, 0x8ADC, 0xF4E3,	0x8AE1, 0xE3CD, 0x8AE6, 0xF4F4, 0x8AE7, 0xFAB2, 0x8AEA, 0xEFF5,
+	0x8AEB, 0xCADF, 0x8AED, 0xEBB1, 0x8AEE, 0xEDBF, 0x8AF1, 0xFDC9,	0x8AF6, 0xE4A6, 0x8AF7, 0xF9A4, 0x8AF8, 0xF0B3, 0x8AFA, 0xE5EC,
+	0x8AFE, 0xD1E7, 0x8B00, 0xD9C7, 0x8B01, 0xE4D7, 0x8B02, 0xEADD,	0x8B04, 0xD4F7, 0x8B0E, 0xDABA, 0x8B10, 0xDACD, 0x8B14, 0xF9CC,
+	0x8B16, 0xE1DA, 0x8B17, 0xDBBF, 0x8B19, 0xCCC5, 0x8B1A, 0xECD0,	0x8B1B, 0xCBBB, 0x8B1D, 0xDEF3, 0x8B20, 0xE9AA, 0x8B28, 0xD9C8,
+	0x8B2B, 0xEEE3, 0x8B2C, 0xD7BD, 0x8B33, 0xCFC4, 0x8B39, 0xD0CD,	0x8B41, 0xFCA6, 0x8B49, 0xF1FB, 0x8B4E, 0xFDD2, 0x8B4F, 0xD1C1,
+	0x8B58, 0xE3DB, 0x8B5A, 0xD3C9, 0x8B5C, 0xDCCF, 0x8B66, 0xCCED,	0x8B6C, 0xDEA7, 0x8B6F, 0xE6BB, 0x8B70, 0xECA1, 0x8B74, 0xCCB9,
+	0x8B77, 0xFBDE, 0x8B7D, 0xE7E2, 0x8B80, 0xD4C1, 0x8B8A, 0xDCA8,	0x8B90, 0xE2C2, 0x8B92, 0xF3D8, 0x8B93, 0xE5D3, 0x8B96, 0xF3D9,
+	0x8B9A, 0xF3C6, 0x8C37, 0xCDDB, 0x8C3F, 0xCDAC, 0x8C41, 0xFCC3,	0x8C46, 0xD4E7, 0x8C48, 0xD1C2, 0x8C4A, 0xF9A5, 0x8C4C, 0xE8D5,
+	0x8C55, 0xE3CE, 0x8C5A, 0xD4CA, 0x8C61, 0xDFDA, 0x8C6A, 0xFBDF,	0x8C6B, 0xE7E3, 0x8C79, 0xF8FB, 0x8C7A, 0xE3CF, 0x8C82, 0xF5B0,
+	0x8C8A, 0xD8E7, 0x8C8C, 0xD9C9, 0x8C9D, 0xF8AF, 0x8C9E, 0xEFF6,	0x8CA0, 0xDDB6, 0x8CA1, 0xEEAF, 0x8CA2, 0xCDF8, 0x8CA7, 0xDEB8,
+	0x8CA8, 0xFCA7, 0x8CA9, 0xF7FC, 0x8CAA, 0xF7B1, 0x8CAB, 0xCEBB,	0x8CAC, 0xF4A1, 0x8CAF, 0xEECD, 0x8CB0, 0xE1AE, 0x8CB3, 0xECC3,
+	0x8CB4, 0xCFFE, 0x8CB6, 0xF8BF, 0x8CB7, 0xD8E2, 0x8CB8, 0xD3E8,	0x8CBB, 0xDEA8, 0x8CBC, 0xF4E4, 0x8CBD, 0xECC2, 0x8CBF, 0xD9F5,
+	0x8CC0, 0xF9C5, 0x8CC1, 0xDDD3, 0x8CC2, 0xD6F1, 0x8CC3, 0xECFC,	0x8CC4, 0xFCF0, 0x8CC7, 0xEDC0, 0x8CC8, 0xCAB9, 0x8CCA, 0xEEE4,
+	0x8CD1, 0xF2E1, 0x8CD3, 0xDEB9, 0x8CDA, 0xD6F2, 0x8CDC, 0xDEF4,	0x8CDE, 0xDFDB, 0x8CE0, 0xDBD3, 0x8CE2, 0xFAE7, 0x8CE3, 0xD8E3,
+	0x8CE4, 0xF4C1, 0x8CE6, 0xDDB7, 0x8CEA, 0xF2F5, 0x8CED, 0xD4AE,	0x8CF4, 0xD6F3, 0x8CFB, 0xDDB8, 0x8CFC, 0xCFC5, 0x8CFD, 0xDFDF,
+	0x8D04, 0xF2BE, 0x8D05, 0xF6A1, 0x8D07, 0xEBCB, 0x8D08, 0xF1FC,	0x8D0A, 0xF3C7, 0x8D0D, 0xE0EB, 0x8D13, 0xEDFC, 0x8D16, 0xE1DB,
+	0x8D64, 0xEEE5, 0x8D66, 0xDEF5, 0x8D6B, 0xFAD3, 0x8D70, 0xF1CB,	0x8D73, 0xD0AF, 0x8D74, 0xDDB9, 0x8D77, 0xD1C3, 0x8D85, 0xF5B1,
+	0x8D8A, 0xEAC6, 0x8D99, 0xF0E1, 0x8DA3, 0xF6AC, 0x8DA8, 0xF5D9,	0x8DB3, 0xF0EB, 0x8DBA, 0xDDBA, 0x8DBE, 0xF2BF, 0x8DC6, 0xF7C5,
+	0x8DCB, 0xDBA2, 0x8DCC, 0xF2F6, 0x8DCF, 0xCABA, 0x8DDB, 0xF7F5,	0x8DDD, 0xCBE5, 0x8DE1, 0xEEE6, 0x8DE3, 0xE0D3, 0x8DE8, 0xCEA5,
+	0x8DEF, 0xD6D8, 0x8DF3, 0xD4AF, 0x8E0A, 0xE9C9, 0x8E0F, 0xD3CE,	0x8E10, 0xF4C2, 0x8E1E, 0xCBE6, 0x8E2A, 0xF1A1, 0x8E30, 0xEBB2,
+	0x8E35, 0xF1A2, 0x8E42, 0xEBB3, 0x8E44, 0xF0B4, 0x8E47, 0xCBF4,	0x8E48, 0xD4B0, 0x8E49, 0xF3B2, 0x8E4A, 0xFBB7, 0x8E59, 0xF5EC,
+	0x8E5F, 0xEEE7, 0x8E60, 0xF4B2, 0x8E74, 0xF5ED, 0x8E76, 0xCFF3,	0x8E81, 0xF0E2, 0x8E87, 0xEECE, 0x8E8A, 0xF1CC, 0x8E8D, 0xE5B8,
+	0x8EAA, 0xD7F5, 0x8EAB, 0xE3F3, 0x8EAC, 0xCFE5, 0x8EC0, 0xCFC6,	0x8ECA, 0xF3B3, 0x8ECB, 0xE4D8, 0x8ECC, 0xCFF9, 0x8ECD, 0xCFDA,
+	0x8ED2, 0xFACD, 0x8EDF, 0xE6E3, 0x8EEB, 0xF2E2, 0x8EF8, 0xF5EE,	0x8EFB, 0xCABB, 0x8EFE, 0xE3DC, 0x8F03, 0xCEF2, 0x8F05, 0xD6D9,
+	0x8F09, 0xEEB0, 0x8F12, 0xF4E5, 0x8F13, 0xD8C2, 0x8F14, 0xDCD0,	0x8F15, 0xCCEE, 0x8F1B, 0xD5E0, 0x8F1C, 0xF6CA, 0x8F1D, 0xFDCA,
+	0x8F1E, 0xD8D6, 0x8F1F, 0xF4CF, 0x8F26, 0xD6A6, 0x8F27, 0xDCBE,	0x8F29, 0xDBD4, 0x8F2A, 0xD7C7, 0x8F2F, 0xF2FE, 0x8F33, 0xF1CD,
+	0x8F38, 0xE2C3, 0x8F39, 0xDCDE, 0x8F3B, 0xDCDF, 0x8F3E, 0xEFAD,	0x8F3F, 0xE6AB, 0x8F44, 0xF9DD, 0x8F45, 0xEABF, 0x8F49, 0xEFAE,
+	0x8F4D, 0xF4D0, 0x8F4E, 0xCEF3, 0x8F5D, 0xE6AC, 0x8F5F, 0xCEDE,	0x8F62, 0xD5F9, 0x8F9B, 0xE3F4, 0x8F9C, 0xCDD0, 0x8FA3, 0xD5B8,
+	0x8FA6, 0xF7FD, 0x8FA8, 0xDCA9, 0x8FAD, 0xDEF6, 0x8FAF, 0xDCAA,	0x8FB0, 0xF2E3, 0x8FB1, 0xE9B4, 0x8FB2, 0xD2DC, 0x8FC2, 0xE9E6,
+	0x8FC5, 0xE3F6, 0x8FCE, 0xE7CA, 0x8FD1, 0xD0CE, 0x8FD4, 0xDAF7,	0x8FE6, 0xCABC, 0x8FEA, 0xEEE8, 0x8FEB, 0xDADE, 0x8FED, 0xF2F7,
+	0x8FF0, 0xE2FB, 0x8FF2, 0xCCA6, 0x8FF7, 0xDABB, 0x8FF9, 0xEEE9,	0x8FFD, 0xF5DA, 0x9000, 0xF7DC, 0x9001, 0xE1EA, 0x9002, 0xCEC1,
+	0x9003, 0xD4B1, 0x9005, 0xFDB1, 0x9006, 0xE6BD, 0x9008, 0xFBAD,	0x900B, 0xF8E7, 0x900D, 0xE1CE, 0x900F, 0xF7E2, 0x9010, 0xF5EF,
+	0x9011, 0xCFC7, 0x9014, 0xD4B2, 0x9015, 0xCCEF, 0x9017, 0xD4E8,	0x9019, 0xEECF, 0x901A, 0xF7D7, 0x901D, 0xE0A6, 0x901E, 0xD6C1,
+	0x901F, 0xE1DC, 0x9020, 0xF0E3, 0x9021, 0xF1E4, 0x9022, 0xDCF1,	0x9023, 0xD6A7, 0x902E, 0xF4F5, 0x9031, 0xF1CE, 0x9032, 0xF2E4,
+	0x9035, 0xD0B0, 0x9038, 0xECEF, 0x903C, 0xF9BA, 0x903E, 0xEBB5,	0x9041, 0xD4ED, 0x9042, 0xE2C4, 0x9047, 0xE9E7, 0x904A, 0xEBB4,
+	0x904B, 0xEAA1, 0x904D, 0xF8BC, 0x904E, 0xCEA6, 0x9050, 0xF9C6,	0x9051, 0xFCDA, 0x9053, 0xD4B3, 0x9054, 0xD3B9, 0x9055, 0xEADE,
+	0x9059, 0xE9AB, 0x905C, 0xE1E1, 0x905D, 0xD3CF, 0x905E, 0xF4F6,	0x9060, 0xEAC0, 0x9061, 0xE1CF, 0x9063, 0xCCBA, 0x9069, 0xEEEA,
+	0x906D, 0xF0E4, 0x906E, 0xF3B4, 0x906F, 0xD4EE, 0x9072, 0xF2C0,	0x9075, 0xF1E5, 0x9077, 0xF4C3, 0x9078, 0xE0D4, 0x907A, 0xEBB6,
+	0x907C, 0xD7A1, 0x907D, 0xCBE8, 0x907F, 0xF9AD, 0x9080, 0xE9AD,	0x9081, 0xD8E4, 0x9082, 0xFAB3, 0x9083, 0xE2C5, 0x9084, 0xFCBD,
+	0x9087, 0xECC4, 0x9088, 0xD8B1, 0x908A, 0xDCAB, 0x908F, 0xD5A4,	0x9091, 0xEBE9, 0x9095, 0xE8BB, 0x9099, 0xD8D7, 0x90A2, 0xFBAE,
+	0x90A3, 0xD1E1, 0x90A6, 0xDBC0, 0x90A8, 0xF5BE, 0x90AA, 0xDEF7,	0x90AF, 0xCAFB, 0x90B0, 0xF7C6, 0x90B1, 0xCFC8, 0x90B5, 0xE1D0,
+	0x90B8, 0xEED0, 0x90C1, 0xE9F4, 0x90CA, 0xCEF4, 0x90DE, 0xD5CD,	0x90E1, 0xCFDB, 0x90E8, 0xDDBB, 0x90ED, 0xCEAC, 0x90F5, 0xE9E8,
+	0x90FD, 0xD4B4, 0x9102, 0xE4C7, 0x9112, 0xF5DB, 0x9115, 0xFAC1,	0x9119, 0xDEA9, 0x9127, 0xD4F8, 0x912D, 0xEFF7, 0x9132, 0xD3B3,
+	0x9149, 0xEBB7, 0x914A, 0xEFF8, 0x914B, 0xF5DC, 0x914C, 0xEDCC,	0x914D, 0xDBD5, 0x914E, 0xF1CF, 0x9152, 0xF1D0, 0x9162, 0xF5B2,
+	0x9169, 0xD9AE, 0x916A, 0xD5AC, 0x916C, 0xE2C6, 0x9175, 0xFDA3,	0x9177, 0xFBE5, 0x9178, 0xDFAB, 0x9187, 0xE2F5, 0x9189, 0xF6AD,
+	0x918B, 0xF5B3, 0x918D, 0xF0B5, 0x9192, 0xE1A5, 0x919C, 0xF5DD,	0x91AB, 0xECA2, 0x91AC, 0xEDFD, 0x91AE, 0xF5B4, 0x91AF, 0xFBB8,
+	0x91B1, 0xDBA3, 0x91B4, 0xD6CA, 0x91B5, 0xCBD9, 0x91C0, 0xE5D4,	0x91C7, 0xF3FA, 0x91C9, 0xEBB8, 0x91CB, 0xE0B7, 0x91CC, 0xD7EC,
+	0x91CD, 0xF1EC, 0x91CE, 0xE5AF, 0x91CF, 0xD5E1, 0x91D0, 0xD7ED,	0x91D1, 0xD1D1, 0x91D7, 0xE1F2, 0x91D8, 0xEFF9, 0x91DC, 0xDDBC,
+	0x91DD, 0xF6DC, 0x91E3, 0xF0E5, 0x91E7, 0xF4C4, 0x91EA, 0xE9E9,	0x91F5, 0xF3FB, 0x920D, 0xD4EF, 0x9210, 0xCCA2, 0x9211, 0xF7FE,
+	0x9212, 0xDFBC, 0x9217, 0xEBCD, 0x921E, 0xD0B7, 0x9234, 0xD6C2,	0x923A, 0xE8AD, 0x923F, 0xEFAF, 0x9240, 0xCBA5, 0x9245, 0xCBE9,
+	0x9249, 0xFAE8, 0x9257, 0xCCC6, 0x925B, 0xE6E7, 0x925E, 0xEAC7,	0x9262, 0xDBA4, 0x9264, 0xCFC9, 0x9265, 0xE2FC, 0x9266, 0xEFFA,
+	0x9280, 0xEBDE, 0x9283, 0xF5C8, 0x9285, 0xD4DE, 0x9291, 0xE0D5,	0x9293, 0xEFB0, 0x9296, 0xE2C7, 0x9298, 0xD9AF, 0x929C, 0xF9E7,
+	0x92B3, 0xE7E5, 0x92B6, 0xCFCA, 0x92B7, 0xE1D1, 0x92B9, 0xE2C8,	0x92CC, 0xEFFB, 0x92CF, 0xFAF9, 0x92D2, 0xDCF2, 0x92E4, 0xE0A7,
+	0x92EA, 0xF8E8, 0x92F8, 0xCBEA, 0x92FC, 0xCBBC, 0x9304, 0xD6E2,	0x9310, 0xF5DE, 0x9318, 0xF5DF, 0x931A, 0xEEB6, 0x931E, 0xE2F6,
+	0x931F, 0xD3CA, 0x9320, 0xEFFC, 0x9321, 0xD1C4, 0x9322, 0xEFB1,	0x9324, 0xD1C5, 0x9326, 0xD0DE, 0x9328, 0xD9E1, 0x932B, 0xE0B8,
+	0x932E, 0xCDD1, 0x932F, 0xF3B9, 0x9348, 0xE7CC, 0x934A, 0xD6A8,	0x934B, 0xCEA7, 0x934D, 0xD4B5, 0x9354, 0xE4C8, 0x935B, 0xD3B4,
+	0x936E, 0xEBB9, 0x9375, 0xCBF5, 0x937C, 0xF6DD, 0x937E, 0xF1A3,	0x938C, 0xCCC7, 0x9394, 0xE9CA, 0x9396, 0xE1F0, 0x939A, 0xF5E0,
+	0x93A3, 0xFBAF, 0x93A7, 0xCBD1, 0x93AC, 0xFBE0, 0x93AD, 0xF2E5,	0x93B0, 0xECF0, 0x93C3, 0xF0EC, 0x93D1, 0xEEEB, 0x93DE, 0xE9CB,
+	0x93E1, 0xCCF0, 0x93E4, 0xD7AF, 0x93F6, 0xF3A1, 0x9404, 0xFCF5,	0x9418, 0xF1A4, 0x9425, 0xE0D6, 0x942B, 0xEFB2, 0x9435, 0xF4D1,
+	0x9438, 0xF7A1, 0x9444, 0xF1D1, 0x9451, 0xCAFC, 0x9452, 0xCAFD,	0x945B, 0xCECE, 0x947D, 0xF3C8, 0x947F, 0xF3BA, 0x9577, 0xEDFE,
+	0x9580, 0xDAA6, 0x9583, 0xE0EC, 0x9589, 0xF8CD, 0x958B, 0xCBD2,	0x958F, 0xEBCE, 0x9591, 0xF9D8, 0x9592, 0xF9D9, 0x9593, 0xCAE0,
+	0x9594, 0xDACA, 0x9598, 0xCBA6, 0x95A3, 0xCAC8, 0x95A4, 0xF9EE,	0x95A5, 0xDBEC, 0x95A8, 0xD0B1, 0x95AD, 0xD5EF, 0x95B1, 0xE6F3,
+	0x95BB, 0xE7A2, 0x95BC, 0xE4D9, 0x95C7, 0xE4E1, 0x95CA, 0xFCC4,	0x95D4, 0xF9EF, 0x95D5, 0xCFF4, 0x95D6, 0xF7E6, 0x95DC, 0xCEBC,
+	0x95E1, 0xF4C5, 0x95E2, 0xDCA3, 0x961C, 0xDDBD, 0x9621, 0xF4C6,	0x962A, 0xF8A1, 0x962E, 0xE8D6, 0x9632, 0xDBC1, 0x963B, 0xF0E6,
+	0x963F, 0xE4B9, 0x9640, 0xF6ED, 0x9642, 0xF9AE, 0x9644, 0xDDBE,	0x964B, 0xD7B0, 0x964C, 0xD8E8, 0x964D, 0xCBBD, 0x9650, 0xF9DA,
+	0x965B, 0xF8CE, 0x965C, 0xF9F0, 0x965D, 0xE0ED, 0x965E, 0xE3B3,	0x965F, 0xF4B3, 0x9662, 0xEAC2, 0x9663, 0xF2E6, 0x9664, 0xF0B6,
+	0x966A, 0xDBD6, 0x9670, 0xEBE4, 0x9673, 0xF2E7, 0x9675, 0xD7D5,	0x9676, 0xD4B6, 0x9677, 0xF9E8, 0x9678, 0xD7C1, 0x967D, 0xE5D5,
+	0x9685, 0xE9EA, 0x9686, 0xD7CC, 0x968A, 0xD3E9, 0x968B, 0xE2C9,	0x968D, 0xFCDB, 0x968E, 0xCDAD, 0x9694, 0xCCB0, 0x9695, 0xEAA2,
+	0x9698, 0xE4F6, 0x9699, 0xD0C0, 0x969B, 0xF0B7, 0x969C, 0xEEA1,	0x96A3, 0xD7F6, 0x96A7, 0xE2CA, 0x96A8, 0xE2CB, 0x96AA, 0xFACF,
+	0x96B1, 0xEBDF, 0x96B7, 0xD6CB, 0x96BB, 0xF4B4, 0x96C0, 0xEDCD,	0x96C1, 0xE4D2, 0x96C4, 0xEAA9, 0x96C5, 0xE4BA, 0x96C6, 0xF3A2,
+	0x96C7, 0xCDD2, 0x96C9, 0xF6CB, 0x96CB, 0xF1E6, 0x96CC, 0xEDC1,	0x96CD, 0xE8BC, 0x96CE, 0xEED1, 0x96D5, 0xF0E7, 0x96D6, 0xE2CC,
+	0x96D9, 0xE4AA, 0x96DB, 0xF5E1, 0x96DC, 0xEDDA, 0x96E2, 0xD7EE,	0x96E3, 0xD1F1, 0x96E8, 0xE9EB, 0x96E9, 0xE9EC, 0x96EA, 0xE0E4,
+	0x96EF, 0xDAA7, 0x96F0, 0xDDD4, 0x96F2, 0xEAA3, 0x96F6, 0xD6C3,	0x96F7, 0xD6F4, 0x96F9, 0xDADF, 0x96FB, 0xEFB3, 0x9700, 0xE2CD,
+	0x9706, 0xEFFD, 0x9707, 0xF2E8, 0x9711, 0xEFC5, 0x9713, 0xE7E7,	0x9716, 0xD7FD, 0x9719, 0xE7CE, 0x971C, 0xDFDC, 0x971E, 0xF9C7,
+	0x9727, 0xD9F6, 0x9730, 0xDFAC, 0x9732, 0xD6DA, 0x9739, 0xDCA4,	0x973D, 0xF0B8, 0x9742, 0xD5FA, 0x9744, 0xE4F7, 0x9748, 0xD6C4,
+	0x9751, 0xF4EC, 0x9756, 0xEFFE, 0x975C, 0xF0A1, 0x975E, 0xDEAA,	0x9761, 0xDABC, 0x9762, 0xD8FC, 0x9769, 0xFAD4, 0x976D, 0xECE5,
+	0x9774, 0xFCA8, 0x9777, 0xECE6, 0x977A, 0xD8CB, 0x978B, 0xFBB9,	0x978D, 0xE4D3, 0x978F, 0xCDF9, 0x97A0, 0xCFD3, 0x97A8, 0xCAEA,
+	0x97AB, 0xCFD4, 0x97AD, 0xF8BD, 0x97C6, 0xF4C7, 0x97CB, 0xEADF,	0x97D3, 0xF9DB, 0x97DC, 0xD4B7, 0x97F3, 0xEBE5, 0x97F6, 0xE1D2,
+	0x97FB, 0xEAA4, 0x97FF, 0xFAC2, 0x9800, 0xFBE1, 0x9801, 0xFAED,	0x9802, 0xF0A2, 0x9803, 0xCCF1, 0x9805, 0xFAA3, 0x9806, 0xE2F7,
+	0x9808, 0xE2CE, 0x980A, 0xE9F5, 0x980C, 0xE1EB, 0x9810, 0xE7E8,	0x9811, 0xE8D7, 0x9812, 0xDAF8, 0x9813, 0xD4CB, 0x9817, 0xF7F6,
+	0x9818, 0xD6C5, 0x982D, 0xD4E9, 0x9830, 0xFAFA, 0x9838, 0xCCF2,	0x9839, 0xF7DD, 0x983B, 0xDEBA, 0x9846, 0xCEA8, 0x984C, 0xF0B9,
+	0x984D, 0xE4FE, 0x984E, 0xE4C9, 0x9854, 0xE4D4, 0x9858, 0xEAC3,	0x985A, 0xEFB4, 0x985E, 0xD7BE, 0x9865, 0xFBE2, 0x9867, 0xCDD3,
+	0x986B, 0xEFB5, 0x986F, 0xFAE9, 0x98A8, 0xF9A6, 0x98AF, 0xDFBD,	0x98B1, 0xF7C7, 0x98C4, 0xF8FD, 0x98C7, 0xF8FC, 0x98DB, 0xDEAB,
+	0x98DC, 0xDBE8, 0x98DF, 0xE3DD, 0x98E1, 0xE1E2, 0x98E2, 0xD1C6,	0x98ED, 0xF6D0, 0x98EE, 0xEBE6, 0x98EF, 0xDAF9, 0x98F4, 0xECC7,
+	0x98FC, 0xDEF8, 0x98FD, 0xF8E9, 0x98FE, 0xE3DE, 0x9903, 0xCEF5,	0x9909, 0xFAC3, 0x990A, 0xE5D7, 0x990C, 0xECC8, 0x9910, 0xF3C9,
+	0x9913, 0xE4BB, 0x9918, 0xE6AE, 0x991E, 0xEFB6, 0x9920, 0xDCBF,	0x9928, 0xCEBD, 0x9945, 0xD8C3, 0x9949, 0xD0CF, 0x994B, 0xCFFA,
+	0x994C, 0xF3CA, 0x994D, 0xE0D7, 0x9951, 0xD1C7, 0x9952, 0xE9AE,	0x9954, 0xE8BD, 0x9957, 0xFAC4, 0x9996, 0xE2CF, 0x9999, 0xFAC5,
+	0x999D, 0xF9B8, 0x99A5, 0xDCE0, 0x99A8, 0xFBB0, 0x99AC, 0xD8A9,	0x99AD, 0xE5DF, 0x99AE, 0xF9A7, 0x99B1, 0xF6EE, 0x99B3, 0xF6CC,
+	0x99B4, 0xE2F8, 0x99B9, 0xECF1, 0x99C1, 0xDAE0, 0x99D0, 0xF1D2,	0x99D1, 0xD2CC, 0x99D2, 0xCFCB, 0x99D5, 0xCABD, 0x99D9, 0xDDBF,
+	0x99DD, 0xF6EF, 0x99DF, 0xDEF9, 0x99ED, 0xFAB4, 0x99F1, 0xD5AD,	0x99FF, 0xF1E7, 0x9A01, 0xDEBE, 0x9A08, 0xDCC0, 0x9A0E, 0xD1C8,
+	0x9A0F, 0xD1C9, 0x9A19, 0xF8BE, 0x9A2B, 0xCBF6, 0x9A30, 0xD4F9,	0x9A36, 0xF5E2, 0x9A37, 0xE1D3, 0x9A40, 0xD8E9, 0x9A43, 0xF8FE,
+	0x9A45, 0xCFCC, 0x9A4D, 0xFDA4, 0x9A55, 0xCEF6, 0x9A57, 0xFAD0,	0x9A5A, 0xCCF3, 0x9A5B, 0xE6BE, 0x9A5F, 0xF6AE, 0x9A62, 0xD5F0,
+	0x9A65, 0xD1CA, 0x9A69, 0xFCBE, 0x9A6A, 0xD5F1, 0x9AA8, 0xCDE9,	0x9AB8, 0xFAB5, 0x9AD3, 0xE2D0, 0x9AD4, 0xF4F7, 0x9AD8, 0xCDD4,
+	0x9AE5, 0xE7A3, 0x9AEE, 0xDBA5, 0x9B1A, 0xE2D1, 0x9B27, 0xD7A2,	0x9B2A, 0xF7E3, 0x9B31, 0xEAA6, 0x9B3C, 0xD0A1, 0x9B41, 0xCEDA,
+	0x9B42, 0xFBEB, 0x9B43, 0xDBA6, 0x9B44, 0xDBDE, 0x9B45, 0xD8E5,	0x9B4F, 0xEAE0, 0x9B54, 0xD8AA, 0x9B5A, 0xE5E0, 0x9B6F, 0xD6DB,
+	0x9B8E, 0xEFC6, 0x9B91, 0xF8EA, 0x9B9F, 0xE4D5, 0x9BAB, 0xCEF7,	0x9BAE, 0xE0D8, 0x9BC9, 0xD7EF, 0x9BD6, 0xF4ED, 0x9BE4, 0xCDE6,
+	0x9BE8, 0xCCF4, 0x9C0D, 0xF5E3, 0x9C10, 0xE4CA, 0x9C12, 0xDCE1,	0x9C15, 0xF9C8, 0x9C25, 0xFCBF, 0x9C32, 0xE8A7, 0x9C3B, 0xD8C4,
+	0x9C47, 0xCBBE, 0x9C49, 0xDCAE, 0x9C57, 0xD7F7, 0x9CE5, 0xF0E8,	0x9CE7, 0xDDC0, 0x9CE9, 0xCFCD, 0x9CF3, 0xDCF3, 0x9CF4, 0xD9B0,
+	0x9CF6, 0xE6E9, 0x9D09, 0xE4BC, 0x9D1B, 0xEAC4, 0x9D26, 0xE4EC,	0x9D28, 0xE4E5, 0x9D3B, 0xFBF8, 0x9D51, 0xCCBB, 0x9D5D, 0xE4BD,
+	0x9D60, 0xCDDC, 0x9D61, 0xD9F7, 0x9D6C, 0xDDDF, 0x9D72, 0xEDCE,	0x9DA9, 0xD9D0, 0x9DAF, 0xE5A3, 0x9DB4, 0xF9CD, 0x9DC4, 0xCDAE,
+	0x9DD7, 0xCFCE, 0x9DF2, 0xF6AF, 0x9DF8, 0xFDD3, 0x9DF9, 0xEBED,	0x9DFA, 0xD6DC, 0x9E1A, 0xE5A4, 0x9E1E, 0xD5B6, 0x9E75, 0xD6DD,
+	0x9E79, 0xF9E9, 0x9E7D, 0xE7A4, 0x9E7F, 0xD6E3, 0x9E92, 0xD1CB,	0x9E93, 0xD6E4, 0x9E97, 0xD5F2, 0x9E9D, 0xDEFA, 0x9E9F, 0xD7F8,
+	0x9EA5, 0xD8EA, 0x9EB4, 0xCFD5, 0x9EB5, 0xD8FD, 0x9EBB, 0xD8AB,	0x9EBE, 0xFDCB, 0x9EC3, 0xFCDC, 0x9ECD, 0xE0A8, 0x9ECE, 0xD5F3,
+	0x9ED1, 0xFDD9, 0x9ED4, 0xCCA3, 0x9ED8, 0xD9F9, 0x9EDB, 0xD3EA,	0x9EDC, 0xF5F5, 0x9EDE, 0xEFC7, 0x9EE8, 0xD3DA, 0x9EF4, 0xDABD,
+	0x9F07, 0xE8A8, 0x9F08, 0xDCAF, 0x9F0E, 0xF0A3, 0x9F13, 0xCDD5,	0x9F20, 0xE0A9, 0x9F3B, 0xDEAC, 0x9F4A, 0xF0BA, 0x9F4B, 0xEEB1,
+	0x9F4E, 0xEEB2, 0x9F52, 0xF6CD, 0x9F5F, 0xEED2, 0x9F61, 0xD6C6,	0x9F67, 0xE0E5, 0x9F6A, 0xF3BB, 0x9F6C, 0xE5E1, 0x9F77, 0xE4CB,
+	0x9F8D, 0xD7A3, 0x9F90, 0xDBC2, 0x9F95, 0xCAFE, 0x9F9C, 0xCFCF,	0xAC00, 0xB0A1, 0xAC01, 0xB0A2, 0xAC02, 0x8141, 0xAC03, 0x8142,
+	0xAC04, 0xB0A3, 0xAC05, 0x8143, 0xAC06, 0x8144, 0xAC07, 0xB0A4,	0xAC08, 0xB0A5, 0xAC09, 0xB0A6, 0xAC0A, 0xB0A7, 0xAC0B, 0x8145,
+	0xAC0C, 0x8146, 0xAC0D, 0x8147, 0xAC0E, 0x8148, 0xAC0F, 0x8149,	0xAC10, 0xB0A8, 0xAC11, 0xB0A9, 0xAC12, 0xB0AA, 0xAC13, 0xB0AB,
+	0xAC14, 0xB0AC, 0xAC15, 0xB0AD, 0xAC16, 0xB0AE, 0xAC17, 0xB0AF,	0xAC18, 0x814A, 0xAC19, 0xB0B0, 0xAC1A, 0xB0B1, 0xAC1B, 0xB0B2,
+	0xAC1C, 0xB0B3, 0xAC1D, 0xB0B4, 0xAC1E, 0x814B, 0xAC1F, 0x814C,	0xAC20, 0xB0B5, 0xAC21, 0x814D, 0xAC22, 0x814E, 0xAC23, 0x814F,
+	0xAC24, 0xB0B6, 0xAC25, 0x8150, 0xAC26, 0x8151, 0xAC27, 0x8152,	0xAC28, 0x8153, 0xAC29, 0x8154, 0xAC2A, 0x8155, 0xAC2B, 0x8156,
+	0xAC2C, 0xB0B7, 0xAC2D, 0xB0B8, 0xAC2E, 0x8157, 0xAC2F, 0xB0B9,	0xAC30, 0xB0BA, 0xAC31, 0xB0BB, 0xAC32, 0x8158, 0xAC33, 0x8159,
+	0xAC34, 0x815A, 0xAC35, 0x8161, 0xAC36, 0x8162, 0xAC37, 0x8163,	0xAC38, 0xB0BC, 0xAC39, 0xB0BD, 0xAC3A, 0x8164, 0xAC3B, 0x8165,
+	0xAC3C, 0xB0BE, 0xAC3D, 0x8166, 0xAC3E, 0x8167, 0xAC3F, 0x8168,	0xAC40, 0xB0BF, 0xAC41, 0x8169, 0xAC42, 0x816A, 0xAC43, 0x816B,
+	0xAC44, 0x816C, 0xAC45, 0x816D, 0xAC46, 0x816E, 0xAC47, 0x816F,	0xAC48, 0x8170, 0xAC49, 0x8171, 0xAC4A, 0x8172, 0xAC4B, 0xB0C0,
+	0xAC4C, 0x8173, 0xAC4D, 0xB0C1, 0xAC4E, 0x8174, 0xAC4F, 0x8175,	0xAC50, 0x8176, 0xAC51, 0x8177, 0xAC52, 0x8178, 0xAC53, 0x8179,
+	0xAC54, 0xB0C2, 0xAC55, 0x817A, 0xAC56, 0x8181, 0xAC57, 0x8182,	0xAC58, 0xB0C3, 0xAC59, 0x8183, 0xAC5A, 0x8184, 0xAC5B, 0x8185,
+	0xAC5C, 0xB0C4, 0xAC5D, 0x8186, 0xAC5E, 0x8187, 0xAC5F, 0x8188,	0xAC60, 0x8189, 0xAC61, 0x818A, 0xAC62, 0x818B, 0xAC63, 0x818C,
+	0xAC64, 0x818D, 0xAC65, 0x818E, 0xAC66, 0x818F, 0xAC67, 0x8190,	0xAC68, 0x8191, 0xAC69, 0x8192, 0xAC6A, 0x8193, 0xAC6B, 0x8194,
+	0xAC6C, 0x8195, 0xAC6D, 0x8196, 0xAC6E, 0x8197, 0xAC6F, 0x8198,	0xAC70, 0xB0C5, 0xAC71, 0xB0C6, 0xAC72, 0x8199, 0xAC73, 0x819A,
+	0xAC74, 0xB0C7, 0xAC75, 0x819B, 0xAC76, 0x819C, 0xAC77, 0xB0C8,	0xAC78, 0xB0C9, 0xAC79, 0x819D, 0xAC7A, 0xB0CA, 0xAC7B, 0x819E,
+	0xAC7C, 0x819F, 0xAC7D, 0x81A0, 0xAC7E, 0x81A1, 0xAC7F, 0x81A2,	0xAC80, 0xB0CB, 0xAC81, 0xB0CC, 0xAC82, 0x81A3, 0xAC83, 0xB0CD,
+	0xAC84, 0xB0CE, 0xAC85, 0xB0CF, 0xAC86, 0xB0D0, 0xAC87, 0x81A4,	0xAC88, 0x81A5, 0xAC89, 0xB0D1, 0xAC8A, 0xB0D2, 0xAC8B, 0xB0D3,
+	0xAC8C, 0xB0D4, 0xAC8D, 0x81A6, 0xAC8E, 0x81A7, 0xAC8F, 0x81A8,	0xAC90, 0xB0D5, 0xAC91, 0x81A9, 0xAC92, 0x81AA, 0xAC93, 0x81AB,
+	0xAC94, 0xB0D6, 0xAC95, 0x81AC, 0xAC96, 0x81AD, 0xAC97, 0x81AE,	0xAC98, 0x81AF, 0xAC99, 0x81B0, 0xAC9A, 0x81B1, 0xAC9B, 0x81B2,
+	0xAC9C, 0xB0D7, 0xAC9D, 0xB0D8, 0xAC9E, 0x81B3, 0xAC9F, 0xB0D9,	0xACA0, 0xB0DA, 0xACA1, 0xB0DB, 0xACA2, 0x81B4, 0xACA3, 0x81B5,
+	0xACA4, 0x81B6, 0xACA5, 0x81B7, 0xACA6, 0x81B8, 0xACA7, 0x81B9,	0xACA8, 0xB0DC, 0xACA9, 0xB0DD, 0xACAA, 0xB0DE, 0xACAB, 0x81BA,
+	0xACAC, 0xB0DF, 0xACAD, 0x81BB, 0xACAE, 0x81BC, 0xACAF, 0xB0E0,	0xACB0, 0xB0E1, 0xACB1, 0x81BD, 0xACB2, 0x81BE, 0xACB3, 0x81BF,
+	0xACB4, 0x81C0, 0xACB5, 0x81C1, 0xACB6, 0x81C2, 0xACB7, 0x81C3,	0xACB8, 0xB0E2, 0xACB9, 0xB0E3, 0xACBA, 0x81C4, 0xACBB, 0xB0E4,
+	0xACBC, 0xB0E5, 0xACBD, 0xB0E6, 0xACBE, 0x81C5, 0xACBF, 0x81C6,	0xACC0, 0x81C7, 0xACC1, 0xB0E7, 0xACC2, 0x81C8, 0xACC3, 0x81C9,
+	0xACC4, 0xB0E8, 0xACC5, 0x81CA, 0xACC6, 0x81CB, 0xACC7, 0x81CC,	0xACC8, 0xB0E9, 0xACC9, 0x81CD, 0xACCA, 0x81CE, 0xACCB, 0x81CF,
+	0xACCC, 0xB0EA, 0xACCD, 0x81D0, 0xACCE, 0x81D1, 0xACCF, 0x81D2,	0xACD0, 0x81D3, 0xACD1, 0x81D4, 0xACD2, 0x81D5, 0xACD3, 0x81D6,
+	0xACD4, 0x81D7, 0xACD5, 0xB0EB, 0xACD6, 0x81D8, 0xACD7, 0xB0EC,	0xACD8, 0x81D9, 0xACD9, 0x81DA, 0xACDA, 0x81DB, 0xACDB, 0x81DC,
+	0xACDC, 0x81DD, 0xACDD, 0x81DE, 0xACDE, 0x81DF, 0xACDF, 0x81E0,	0xACE0, 0xB0ED, 0xACE1, 0xB0EE, 0xACE2, 0x81E1, 0xACE3, 0x81E2,
+	0xACE4, 0xB0EF, 0xACE5, 0x81E3, 0xACE6, 0x81E4, 0xACE7, 0xB0F0,	0xACE8, 0xB0F1, 0xACE9, 0x81E5, 0xACEA, 0xB0F2, 0xACEB, 0x81E6,
+	0xACEC, 0xB0F3, 0xACED, 0x81E7, 0xACEE, 0x81E8, 0xACEF, 0xB0F4,	0xACF0, 0xB0F5, 0xACF1, 0xB0F6, 0xACF2, 0x81E9, 0xACF3, 0xB0F7,
+	0xACF4, 0x81EA, 0xACF5, 0xB0F8, 0xACF6, 0xB0F9, 0xACF7, 0x81EB,	0xACF8, 0x81EC, 0xACF9, 0x81ED, 0xACFA, 0x81EE, 0xACFB, 0x81EF,
+	0xACFC, 0xB0FA, 0xACFD, 0xB0FB, 0xACFE, 0x81F0, 0xACFF, 0x81F1,	0xAD00, 0xB0FC, 0xAD01, 0x81F2, 0xAD02, 0x81F3, 0xAD03, 0x81F4,
+	0xAD04, 0xB0FD, 0xAD05, 0x81F5, 0xAD06, 0xB0FE, 0xAD07, 0x81F6,	0xAD08, 0x81F7, 0xAD09, 0x81F8, 0xAD0A, 0x81F9, 0xAD0B, 0x81FA,
+	0xAD0C, 0xB1A1, 0xAD0D, 0xB1A2, 0xAD0E, 0x81FB, 0xAD0F, 0xB1A3,	0xAD10, 0x81FC, 0xAD11, 0xB1A4, 0xAD12, 0x81FD, 0xAD13, 0x81FE,
+	0xAD14, 0x8241, 0xAD15, 0x8242, 0xAD16, 0x8243, 0xAD17, 0x8244,	0xAD18, 0xB1A5, 0xAD19, 0x8245, 0xAD1A, 0x8246, 0xAD1B, 0x8247,
+	0xAD1C, 0xB1A6, 0xAD1D, 0x8248, 0xAD1E, 0x8249, 0xAD1F, 0x824A,	0xAD20, 0xB1A7, 0xAD21, 0x824B, 0xAD22, 0x824C, 0xAD23, 0x824D,
+	0xAD24, 0x824E, 0xAD25, 0x824F, 0xAD26, 0x8250, 0xAD27, 0x8251,	0xAD28, 0x8252, 0xAD29, 0xB1A8, 0xAD2A, 0x8253, 0xAD2B, 0x8254,
+	0xAD2C, 0xB1A9, 0xAD2D, 0xB1AA, 0xAD2E, 0x8255, 0xAD2F, 0x8256,	0xAD30, 0x8257, 0xAD31, 0x8258, 0xAD32, 0x8259, 0xAD33, 0x825A,
+	0xAD34, 0xB1AB, 0xAD35, 0xB1AC, 0xAD36, 0x8261, 0xAD37, 0x8262,	0xAD38, 0xB1AD, 0xAD39, 0x8263, 0xAD3A, 0x8264, 0xAD3B, 0x8265,
+	0xAD3C, 0xB1AE, 0xAD3D, 0x8266, 0xAD3E, 0x8267, 0xAD3F, 0x8268,	0xAD40, 0x8269, 0xAD41, 0x826A, 0xAD42, 0x826B, 0xAD43, 0x826C,
+	0xAD44, 0xB1AF, 0xAD45, 0xB1B0, 0xAD46, 0x826D, 0xAD47, 0xB1B1,	0xAD48, 0x826E, 0xAD49, 0xB1B2, 0xAD4A, 0x826F, 0xAD4B, 0x8270,
+	0xAD4C, 0x8271, 0xAD4D, 0x8272, 0xAD4E, 0x8273, 0xAD4F, 0x8274,	0xAD50, 0xB1B3, 0xAD51, 0x8275, 0xAD52, 0x8276, 0xAD53, 0x8277,
+	0xAD54, 0xB1B4, 0xAD55, 0x8278, 0xAD56, 0x8279, 0xAD57, 0x827A,	0xAD58, 0xB1B5, 0xAD59, 0x8281, 0xAD5A, 0x8282, 0xAD5B, 0x8283,
+	0xAD5C, 0x8284, 0xAD5D, 0x8285, 0xAD5E, 0x8286, 0xAD5F, 0x8287,	0xAD60, 0x8288, 0xAD61, 0xB1B6, 0xAD62, 0x8289, 0xAD63, 0xB1B7,
+	0xAD64, 0x828A, 0xAD65, 0x828B, 0xAD66, 0x828C, 0xAD67, 0x828D,	0xAD68, 0x828E, 0xAD69, 0x828F, 0xAD6A, 0x8290, 0xAD6B, 0x8291,
+	0xAD6C, 0xB1B8, 0xAD6D, 0xB1B9, 0xAD6E, 0x8292, 0xAD6F, 0x8293,	0xAD70, 0xB1BA, 0xAD71, 0x8294, 0xAD72, 0x8295, 0xAD73, 0xB1BB,
+	0xAD74, 0xB1BC, 0xAD75, 0xB1BD, 0xAD76, 0xB1BE, 0xAD77, 0x8296,	0xAD78, 0x8297, 0xAD79, 0x8298, 0xAD7A, 0x8299, 0xAD7B, 0xB1BF,
+	0xAD7C, 0xB1C0, 0xAD7D, 0xB1C1, 0xAD7E, 0x829A, 0xAD7F, 0xB1C2,	0xAD80, 0x829B, 0xAD81, 0xB1C3, 0xAD82, 0xB1C4, 0xAD83, 0x829C,
+	0xAD84, 0x829D, 0xAD85, 0x829E, 0xAD86, 0x829F, 0xAD87, 0x82A0,	0xAD88, 0xB1C5, 0xAD89, 0xB1C6, 0xAD8A, 0x82A1, 0xAD8B, 0x82A2,
+	0xAD8C, 0xB1C7, 0xAD8D, 0x82A3, 0xAD8E, 0x82A4, 0xAD8F, 0x82A5,	0xAD90, 0xB1C8, 0xAD91, 0x82A6, 0xAD92, 0x82A7, 0xAD93, 0x82A8,
+	0xAD94, 0x82A9, 0xAD95, 0x82AA, 0xAD96, 0x82AB, 0xAD97, 0x82AC,	0xAD98, 0x82AD, 0xAD99, 0x82AE, 0xAD9A, 0x82AF, 0xAD9B, 0x82B0,
+	0xAD9C, 0xB1C9, 0xAD9D, 0xB1CA, 0xAD9E, 0x82B1, 0xAD9F, 0x82B2,	0xADA0, 0x82B3, 0xADA1, 0x82B4, 0xADA2, 0x82B5, 0xADA3, 0x82B6,
+	0xADA4, 0xB1CB, 0xADA5, 0x82B7, 0xADA6, 0x82B8, 0xADA7, 0x82B9,	0xADA8, 0x82BA, 0xADA9, 0x82BB, 0xADAA, 0x82BC, 0xADAB, 0x82BD,
+	0xADAC, 0x82BE, 0xADAD, 0x82BF, 0xADAE, 0x82C0, 0xADAF, 0x82C1,	0xADB0, 0x82C2, 0xADB1, 0x82C3, 0xADB2, 0x82C4, 0xADB3, 0x82C5,
+	0xADB4, 0x82C6, 0xADB5, 0x82C7, 0xADB6, 0x82C8, 0xADB7, 0xB1CC,	0xADB8, 0x82C9, 0xADB9, 0x82CA, 0xADBA, 0x82CB, 0xADBB, 0x82CC,
+	0xADBC, 0x82CD, 0xADBD, 0x82CE, 0xADBE, 0x82CF, 0xADBF, 0x82D0,	0xADC0, 0xB1CD, 0xADC1, 0xB1CE, 0xADC2, 0x82D1, 0xADC3, 0x82D2,
+	0xADC4, 0xB1CF, 0xADC5, 0x82D3, 0xADC6, 0x82D4, 0xADC7, 0x82D5,	0xADC8, 0xB1D0, 0xADC9, 0x82D6, 0xADCA, 0x82D7, 0xADCB, 0x82D8,
+	0xADCC, 0x82D9, 0xADCD, 0x82DA, 0xADCE, 0x82DB, 0xADCF, 0x82DC,	0xADD0, 0xB1D1, 0xADD1, 0xB1D2, 0xADD2, 0x82DD, 0xADD3, 0xB1D3,
+	0xADD4, 0x82DE, 0xADD5, 0x82DF, 0xADD6, 0x82E0, 0xADD7, 0x82E1,	0xADD8, 0x82E2, 0xADD9, 0x82E3, 0xADDA, 0x82E4, 0xADDB, 0x82E5,
+	0xADDC, 0xB1D4, 0xADDD, 0x82E6, 0xADDE, 0x82E7, 0xADDF, 0x82E8,	0xADE0, 0xB1D5, 0xADE1, 0x82E9, 0xADE2, 0x82EA, 0xADE3, 0x82EB,
+	0xADE4, 0xB1D6, 0xADE5, 0x82EC, 0xADE6, 0x82ED, 0xADE7, 0x82EE,	0xADE8, 0x82EF, 0xADE9, 0x82F0, 0xADEA, 0x82F1, 0xADEB, 0x82F2,
+	0xADEC, 0x82F3, 0xADED, 0x82F4, 0xADEE, 0x82F5, 0xADEF, 0x82F6,	0xADF0, 0x82F7, 0xADF1, 0x82F8, 0xADF2, 0x82F9, 0xADF3, 0x82FA,
+	0xADF4, 0x82FB, 0xADF5, 0x82FC, 0xADF6, 0x82FD, 0xADF7, 0x82FE,	0xADF8, 0xB1D7, 0xADF9, 0xB1D8, 0xADFA, 0x8341, 0xADFB, 0x8342,
+	0xADFC, 0xB1D9, 0xADFD, 0x8343, 0xADFE, 0x8344, 0xADFF, 0xB1DA,	0xAE00, 0xB1DB, 0xAE01, 0xB1DC, 0xAE02, 0x8345, 0xAE03, 0x8346,
+	0xAE04, 0x8347, 0xAE05, 0x8348, 0xAE06, 0x8349, 0xAE07, 0x834A,	0xAE08, 0xB1DD, 0xAE09, 0xB1DE, 0xAE0A, 0x834B, 0xAE0B, 0xB1DF,
+	0xAE0C, 0x834C, 0xAE0D, 0xB1E0, 0xAE0E, 0x834D, 0xAE0F, 0x834E,	0xAE10, 0x834F, 0xAE11, 0x8350, 0xAE12, 0x8351, 0xAE13, 0x8352,
+	0xAE14, 0xB1E1, 0xAE15, 0x8353, 0xAE16, 0x8354, 0xAE17, 0x8355,	0xAE18, 0x8356, 0xAE19, 0x8357, 0xAE1A, 0x8358, 0xAE1B, 0x8359,
+	0xAE1C, 0x835A, 0xAE1D, 0x8361, 0xAE1E, 0x8362, 0xAE1F, 0x8363,	0xAE20, 0x8364, 0xAE21, 0x8365, 0xAE22, 0x8366, 0xAE23, 0x8367,
+	0xAE24, 0x8368, 0xAE25, 0x8369, 0xAE26, 0x836A, 0xAE27, 0x836B,	0xAE28, 0x836C, 0xAE29, 0x836D, 0xAE2A, 0x836E, 0xAE2B, 0x836F,
+	0xAE2C, 0x8370, 0xAE2D, 0x8371, 0xAE2E, 0x8372, 0xAE2F, 0x8373,	0xAE30, 0xB1E2, 0xAE31, 0xB1E3, 0xAE32, 0x8374, 0xAE33, 0x8375,
+	0xAE34, 0xB1E4, 0xAE35, 0x8376, 0xAE36, 0x8377, 0xAE37, 0xB1E5,	0xAE38, 0xB1E6, 0xAE39, 0x8378, 0xAE3A, 0xB1E7, 0xAE3B, 0x8379,
+	0xAE3C, 0x837A, 0xAE3D, 0x8381, 0xAE3E, 0x8382, 0xAE3F, 0x8383,	0xAE40, 0xB1E8, 0xAE41, 0xB1E9, 0xAE42, 0x8384, 0xAE43, 0xB1EA,
+	0xAE44, 0x8385, 0xAE45, 0xB1EB, 0xAE46, 0xB1EC, 0xAE47, 0x8386,	0xAE48, 0x8387, 0xAE49, 0x8388, 0xAE4A, 0xB1ED, 0xAE4B, 0x8389,
+	0xAE4C, 0xB1EE, 0xAE4D, 0xB1EF, 0xAE4E, 0xB1F0, 0xAE4F, 0x838A,	0xAE50, 0xB1F1, 0xAE51, 0x838B, 0xAE52, 0x838C, 0xAE53, 0x838D,
+	0xAE54, 0xB1F2, 0xAE55, 0x838E, 0xAE56, 0xB1F3, 0xAE57, 0x838F,	0xAE58, 0x8390, 0xAE59, 0x8391, 0xAE5A, 0x8392, 0xAE5B, 0x8393,
+	0xAE5C, 0xB1F4, 0xAE5D, 0xB1F5, 0xAE5E, 0x8394, 0xAE5F, 0xB1F6,	0xAE60, 0xB1F7, 0xAE61, 0xB1F8, 0xAE62, 0x8395, 0xAE63, 0x8396,
+	0xAE64, 0x8397, 0xAE65, 0xB1F9, 0xAE66, 0x8398, 0xAE67, 0x8399,	0xAE68, 0xB1FA, 0xAE69, 0xB1FB, 0xAE6A, 0x839A, 0xAE6B, 0x839B,
+	0xAE6C, 0xB1FC, 0xAE6D, 0x839C, 0xAE6E, 0x839D, 0xAE6F, 0x839E,	0xAE70, 0xB1FD, 0xAE71, 0x839F, 0xAE72, 0x83A0, 0xAE73, 0x83A1,
+	0xAE74, 0x83A2, 0xAE75, 0x83A3, 0xAE76, 0x83A4, 0xAE77, 0x83A5,	0xAE78, 0xB1FE, 0xAE79, 0xB2A1, 0xAE7A, 0x83A6, 0xAE7B, 0xB2A2,
+	0xAE7C, 0xB2A3, 0xAE7D, 0xB2A4, 0xAE7E, 0x83A7, 0xAE7F, 0x83A8,	0xAE80, 0x83A9, 0xAE81, 0x83AA, 0xAE82, 0x83AB, 0xAE83, 0x83AC,
+	0xAE84, 0xB2A5, 0xAE85, 0xB2A6, 0xAE86, 0x83AD, 0xAE87, 0x83AE,	0xAE88, 0x83AF, 0xAE89, 0x83B0, 0xAE8A, 0x83B1, 0xAE8B, 0x83B2,
+	0xAE8C, 0xB2A7, 0xAE8D, 0x83B3, 0xAE8E, 0x83B4, 0xAE8F, 0x83B5,	0xAE90, 0x83B6, 0xAE91, 0x83B7, 0xAE92, 0x83B8, 0xAE93, 0x83B9,
+	0xAE94, 0x83BA, 0xAE95, 0x83BB, 0xAE96, 0x83BC, 0xAE97, 0x83BD,	0xAE98, 0x83BE, 0xAE99, 0x83BF, 0xAE9A, 0x83C0, 0xAE9B, 0x83C1,
+	0xAE9C, 0x83C2, 0xAE9D, 0x83C3, 0xAE9E, 0x83C4, 0xAE9F, 0x83C5,	0xAEA0, 0x83C6, 0xAEA1, 0x83C7, 0xAEA2, 0x83C8, 0xAEA3, 0x83C9,
+	0xAEA4, 0x83CA, 0xAEA5, 0x83CB, 0xAEA6, 0x83CC, 0xAEA7, 0x83CD,	0xAEA8, 0x83CE, 0xAEA9, 0x83CF, 0xAEAA, 0x83D0, 0xAEAB, 0x83D1,
+	0xAEAC, 0x83D2, 0xAEAD, 0x83D3, 0xAEAE, 0x83D4, 0xAEAF, 0x83D5,	0xAEB0, 0x83D6, 0xAEB1, 0x83D7, 0xAEB2, 0x83D8, 0xAEB3, 0x83D9,
+	0xAEB4, 0x83DA, 0xAEB5, 0x83DB, 0xAEB6, 0x83DC, 0xAEB7, 0x83DD,	0xAEB8, 0x83DE, 0xAEB9, 0x83DF, 0xAEBA, 0x83E0, 0xAEBB, 0x83E1,
+	0xAEBC, 0xB2A8, 0xAEBD, 0xB2A9, 0xAEBE, 0xB2AA, 0xAEBF, 0x83E2,	0xAEC0, 0xB2AB, 0xAEC1, 0x83E3, 0xAEC2, 0x83E4, 0xAEC3, 0x83E5,
+	0xAEC4, 0xB2AC, 0xAEC5, 0x83E6, 0xAEC6, 0x83E7, 0xAEC7, 0x83E8,	0xAEC8, 0x83E9, 0xAEC9, 0x83EA, 0xAECA, 0x83EB, 0xAECB, 0x83EC,
+	0xAECC, 0xB2AD, 0xAECD, 0xB2AE, 0xAECE, 0x83ED, 0xAECF, 0xB2AF,	0xAED0, 0xB2B0, 0xAED1, 0xB2B1, 0xAED2, 0x83EE, 0xAED3, 0x83EF,
+	0xAED4, 0x83F0, 0xAED5, 0x83F1, 0xAED6, 0x83F2, 0xAED7, 0x83F3,	0xAED8, 0xB2B2, 0xAED9, 0xB2B3, 0xAEDA, 0x83F4, 0xAEDB, 0x83F5,
+	0xAEDC, 0xB2B4, 0xAEDD, 0x83F6, 0xAEDE, 0x83F7, 0xAEDF, 0x83F8,	0xAEE0, 0x83F9, 0xAEE1, 0x83FA, 0xAEE2, 0x83FB, 0xAEE3, 0x83FC,
+	0xAEE4, 0x83FD, 0xAEE5, 0x83FE, 0xAEE6, 0x8441, 0xAEE7, 0x8442,	0xAEE8, 0xB2B5, 0xAEE9, 0x8443, 0xAEEA, 0x8444, 0xAEEB, 0xB2B6,
+	0xAEEC, 0x8445, 0xAEED, 0xB2B7, 0xAEEE, 0x8446, 0xAEEF, 0x8447,	0xAEF0, 0x8448, 0xAEF1, 0x8449, 0xAEF2, 0x844A, 0xAEF3, 0x844B,
+	0xAEF4, 0xB2B8, 0xAEF5, 0x844C, 0xAEF6, 0x844D, 0xAEF7, 0x844E,	0xAEF8, 0xB2B9, 0xAEF9, 0x844F, 0xAEFA, 0x8450, 0xAEFB, 0x8451,
+	0xAEFC, 0xB2BA, 0xAEFD, 0x8452, 0xAEFE, 0x8453, 0xAEFF, 0x8454,	0xAF00, 0x8455, 0xAF01, 0x8456, 0xAF02, 0x8457, 0xAF03, 0x8458,
+	0xAF04, 0x8459, 0xAF05, 0x845A, 0xAF06, 0x8461, 0xAF07, 0xB2BB,	0xAF08, 0xB2BC, 0xAF09, 0x8462, 0xAF0A, 0x8463, 0xAF0B, 0x8464,
+	0xAF0C, 0x8465, 0xAF0D, 0xB2BD, 0xAF0E, 0x8466, 0xAF0F, 0x8467,	0xAF10, 0xB2BE, 0xAF11, 0x8468, 0xAF12, 0x8469, 0xAF13, 0x846A,
+	0xAF14, 0x846B, 0xAF15, 0x846C, 0xAF16, 0x846D, 0xAF17, 0x846E,	0xAF18, 0x846F, 0xAF19, 0x8470, 0xAF1A, 0x8471, 0xAF1B, 0x8472,
+	0xAF1C, 0x8473, 0xAF1D, 0x8474, 0xAF1E, 0x8475, 0xAF1F, 0x8476,	0xAF20, 0x8477, 0xAF21, 0x8478, 0xAF22, 0x8479, 0xAF23, 0x847A,
+	0xAF24, 0x8481, 0xAF25, 0x8482, 0xAF26, 0x8483, 0xAF27, 0x8484,	0xAF28, 0x8485, 0xAF29, 0x8486, 0xAF2A, 0x8487, 0xAF2B, 0x8488,
+	0xAF2C, 0xB2BF, 0xAF2D, 0xB2C0, 0xAF2E, 0x8489, 0xAF2F, 0x848A,	0xAF30, 0xB2C1, 0xAF31, 0x848B, 0xAF32, 0xB2C2, 0xAF33, 0x848C,
+	0xAF34, 0xB2C3, 0xAF35, 0x848D, 0xAF36, 0x848E, 0xAF37, 0x848F,	0xAF38, 0x8490, 0xAF39, 0x8491, 0xAF3A, 0x8492, 0xAF3B, 0x8493,
+	0xAF3C, 0xB2C4, 0xAF3D, 0xB2C5, 0xAF3E, 0x8494, 0xAF3F, 0xB2C6,	0xAF40, 0x8495, 0xAF41, 0xB2C7, 0xAF42, 0xB2C8, 0xAF43, 0xB2C9,
+	0xAF44, 0x8496, 0xAF45, 0x8497, 0xAF46, 0x8498, 0xAF47, 0x8499,	0xAF48, 0xB2CA, 0xAF49, 0xB2CB, 0xAF4A, 0x849A, 0xAF4B, 0x849B,
+	0xAF4C, 0x849C, 0xAF4D, 0x849D, 0xAF4E, 0x849E, 0xAF4F, 0x849F,	0xAF50, 0xB2CC, 0xAF51, 0x84A0, 0xAF52, 0x84A1, 0xAF53, 0x84A2,
+	0xAF54, 0x84A3, 0xAF55, 0x84A4, 0xAF56, 0x84A5, 0xAF57, 0x84A6,	0xAF58, 0x84A7, 0xAF59, 0x84A8, 0xAF5A, 0x84A9, 0xAF5B, 0x84AA,
+	0xAF5C, 0xB2CD, 0xAF5D, 0xB2CE, 0xAF5E, 0x84AB, 0xAF5F, 0x84AC,	0xAF60, 0x84AD, 0xAF61, 0x84AE, 0xAF62, 0x84AF, 0xAF63, 0x84B0,
+	0xAF64, 0xB2CF, 0xAF65, 0xB2D0, 0xAF66, 0x84B1, 0xAF67, 0x84B2,	0xAF68, 0x84B3, 0xAF69, 0x84B4, 0xAF6A, 0x84B5, 0xAF6B, 0x84B6,
+	0xAF6C, 0x84B7, 0xAF6D, 0x84B8, 0xAF6E, 0x84B9, 0xAF6F, 0x84BA,	0xAF70, 0x84BB, 0xAF71, 0x84BC, 0xAF72, 0x84BD, 0xAF73, 0x84BE,
+	0xAF74, 0x84BF, 0xAF75, 0x84C0, 0xAF76, 0x84C1, 0xAF77, 0x84C2,	0xAF78, 0x84C3, 0xAF79, 0xB2D1, 0xAF7A, 0x84C4, 0xAF7B, 0x84C5,
+	0xAF7C, 0x84C6, 0xAF7D, 0x84C7, 0xAF7E, 0x84C8, 0xAF7F, 0x84C9,	0xAF80, 0xB2D2, 0xAF81, 0x84CA, 0xAF82, 0x84CB, 0xAF83, 0x84CC,
+	0xAF84, 0xB2D3, 0xAF85, 0x84CD, 0xAF86, 0x84CE, 0xAF87, 0x84CF,	0xAF88, 0xB2D4, 0xAF89, 0x84D0, 0xAF8A, 0x84D1, 0xAF8B, 0x84D2,
+	0xAF8C, 0x84D3, 0xAF8D, 0x84D4, 0xAF8E, 0x84D5, 0xAF8F, 0x84D6,	0xAF90, 0xB2D5, 0xAF91, 0xB2D6, 0xAF92, 0x84D7, 0xAF93, 0x84D8,
+	0xAF94, 0x84D9, 0xAF95, 0xB2D7, 0xAF96, 0x84DA, 0xAF97, 0x84DB,	0xAF98, 0x84DC, 0xAF99, 0x84DD, 0xAF9A, 0x84DE, 0xAF9B, 0x84DF,
+	0xAF9C, 0xB2D8, 0xAF9D, 0x84E0, 0xAF9E, 0x84E1, 0xAF9F, 0x84E2,	0xAFA0, 0x84E3, 0xAFA1, 0x84E4, 0xAFA2, 0x84E5, 0xAFA3, 0x84E6,
+	0xAFA4, 0x84E7, 0xAFA5, 0x84E8, 0xAFA6, 0x84E9, 0xAFA7, 0x84EA,	0xAFA8, 0x84EB, 0xAFA9, 0x84EC, 0xAFAA, 0x84ED, 0xAFAB, 0x84EE,
+	0xAFAC, 0x84EF, 0xAFAD, 0x84F0, 0xAFAE, 0x84F1, 0xAFAF, 0x84F2,	0xAFB0, 0x84F3, 0xAFB1, 0x84F4, 0xAFB2, 0x84F5, 0xAFB3, 0x84F6,
+	0xAFB4, 0x84F7, 0xAFB5, 0x84F8, 0xAFB6, 0x84F9, 0xAFB7, 0x84FA,	0xAFB8, 0xB2D9, 0xAFB9, 0xB2DA, 0xAFBA, 0x84FB, 0xAFBB, 0x84FC,
+	0xAFBC, 0xB2DB, 0xAFBD, 0x84FD, 0xAFBE, 0x84FE, 0xAFBF, 0x8541,	0xAFC0, 0xB2DC, 0xAFC1, 0x8542, 0xAFC2, 0x8543, 0xAFC3, 0x8544,
+	0xAFC4, 0x8545, 0xAFC5, 0x8546, 0xAFC6, 0x8547, 0xAFC7, 0xB2DD,	0xAFC8, 0xB2DE, 0xAFC9, 0xB2DF, 0xAFCA, 0x8548, 0xAFCB, 0xB2E0,
+	0xAFCC, 0x8549, 0xAFCD, 0xB2E1, 0xAFCE, 0xB2E2, 0xAFCF, 0x854A,	0xAFD0, 0x854B, 0xAFD1, 0x854C, 0xAFD2, 0x854D, 0xAFD3, 0x854E,
+	0xAFD4, 0xB2E3, 0xAFD5, 0x854F, 0xAFD6, 0x8550, 0xAFD7, 0x8551,	0xAFD8, 0x8552, 0xAFD9, 0x8553, 0xAFDA, 0x8554, 0xAFDB, 0x8555,
+	0xAFDC, 0xB2E4, 0xAFDD, 0x8556, 0xAFDE, 0x8557, 0xAFDF, 0x8558,	0xAFE0, 0x8559, 0xAFE1, 0x855A, 0xAFE2, 0x8561, 0xAFE3, 0x8562,
+	0xAFE4, 0x8563, 0xAFE5, 0x8564, 0xAFE6, 0x8565, 0xAFE7, 0x8566,	0xAFE8, 0xB2E5, 0xAFE9, 0xB2E6, 0xAFEA, 0x8567, 0xAFEB, 0x8568,
+	0xAFEC, 0x8569, 0xAFED, 0x856A, 0xAFEE, 0x856B, 0xAFEF, 0x856C,	0xAFF0, 0xB2E7, 0xAFF1, 0xB2E8, 0xAFF2, 0x856D, 0xAFF3, 0x856E,
+	0xAFF4, 0xB2E9, 0xAFF5, 0x856F, 0xAFF6, 0x8570, 0xAFF7, 0x8571,	0xAFF8, 0xB2EA, 0xAFF9, 0x8572, 0xAFFA, 0x8573, 0xAFFB, 0x8574,
+	0xAFFC, 0x8575, 0xAFFD, 0x8576, 0xAFFE, 0x8577, 0xAFFF, 0x8578,	0xB000, 0xB2EB, 0xB001, 0xB2EC, 0xB002, 0x8579, 0xB003, 0x857A,
+	0xB004, 0xB2ED, 0xB005, 0x8581, 0xB006, 0x8582, 0xB007, 0x8583,	0xB008, 0x8584, 0xB009, 0x8585, 0xB00A, 0x8586, 0xB00B, 0x8587,
+	0xB00C, 0xB2EE, 0xB00D, 0x8588, 0xB00E, 0x8589, 0xB00F, 0x858A,	0xB010, 0xB2EF, 0xB011, 0x858B, 0xB012, 0x858C, 0xB013, 0x858D,
+	0xB014, 0xB2F0, 0xB015, 0x858E, 0xB016, 0x858F, 0xB017, 0x8590,	0xB018, 0x8591, 0xB019, 0x8592, 0xB01A, 0x8593, 0xB01B, 0x8594,
+	0xB01C, 0xB2F1, 0xB01D, 0xB2F2, 0xB01E, 0x8595, 0xB01F, 0x8596,	0xB020, 0x8597, 0xB021, 0x8598, 0xB022, 0x8599, 0xB023, 0x859A,
+	0xB024, 0x859B, 0xB025, 0x859C, 0xB026, 0x859D, 0xB027, 0x859E,	0xB028, 0xB2F3, 0xB029, 0x859F, 0xB02A, 0x85A0, 0xB02B, 0x85A1,
+	0xB02C, 0x85A2, 0xB02D, 0x85A3, 0xB02E, 0x85A4, 0xB02F, 0x85A5,	0xB030, 0x85A6, 0xB031, 0x85A7, 0xB032, 0x85A8, 0xB033, 0x85A9,
+	0xB034, 0x85AA, 0xB035, 0x85AB, 0xB036, 0x85AC, 0xB037, 0x85AD,	0xB038, 0x85AE, 0xB039, 0x85AF, 0xB03A, 0x85B0, 0xB03B, 0x85B1,
+	0xB03C, 0x85B2, 0xB03D, 0x85B3, 0xB03E, 0x85B4, 0xB03F, 0x85B5,	0xB040, 0x85B6, 0xB041, 0x85B7, 0xB042, 0x85B8, 0xB043, 0x85B9,
+	0xB044, 0xB2F4, 0xB045, 0xB2F5, 0xB046, 0x85BA, 0xB047, 0x85BB,	0xB048, 0xB2F6, 0xB049, 0x85BC, 0xB04A, 0xB2F7, 0xB04B, 0x85BD,
+	0xB04C, 0xB2F8, 0xB04D, 0x85BE, 0xB04E, 0xB2F9, 0xB04F, 0x85BF,	0xB050, 0x85C0, 0xB051, 0x85C1, 0xB052, 0x85C2, 0xB053, 0xB2FA,
+	0xB054, 0xB2FB, 0xB055, 0xB2FC, 0xB056, 0x85C3, 0xB057, 0xB2FD,	0xB058, 0x85C4, 0xB059, 0xB2FE, 0xB05A, 0x85C5, 0xB05B, 0x85C6,
+	0xB05C, 0x85C7, 0xB05D, 0xB3A1, 0xB05E, 0x85C8, 0xB05F, 0x85C9,	0xB060, 0x85CA, 0xB061, 0x85CB, 0xB062, 0x85CC, 0xB063, 0x85CD,
+	0xB064, 0x85CE, 0xB065, 0x85CF, 0xB066, 0x85D0, 0xB067, 0x85D1,	0xB068, 0x85D2, 0xB069, 0x85D3, 0xB06A, 0x85D4, 0xB06B, 0x85D5,
+	0xB06C, 0x85D6, 0xB06D, 0x85D7, 0xB06E, 0x85D8, 0xB06F, 0x85D9,	0xB070, 0x85DA, 0xB071, 0x85DB, 0xB072, 0x85DC, 0xB073, 0x85DD,
+	0xB074, 0x85DE, 0xB075, 0x85DF, 0xB076, 0x85E0, 0xB077, 0x85E1,	0xB078, 0x85E2, 0xB079, 0x85E3, 0xB07A, 0x85E4, 0xB07B, 0x85E5,
+	0xB07C, 0xB3A2, 0xB07D, 0xB3A3, 0xB07E, 0x85E6, 0xB07F, 0x85E7,	0xB080, 0xB3A4, 0xB081, 0x85E8, 0xB082, 0x85E9, 0xB083, 0x85EA,
+	0xB084, 0xB3A5, 0xB085, 0x85EB, 0xB086, 0x85EC, 0xB087, 0x85ED,	0xB088, 0x85EE, 0xB089, 0x85EF, 0xB08A, 0x85F0, 0xB08B, 0x85F1,
+	0xB08C, 0xB3A6, 0xB08D, 0xB3A7, 0xB08E, 0x85F2, 0xB08F, 0xB3A8,	0xB090, 0x85F3, 0xB091, 0xB3A9, 0xB092, 0x85F4, 0xB093, 0x85F5,
+	0xB094, 0x85F6, 0xB095, 0x85F7, 0xB096, 0x85F8, 0xB097, 0x85F9,	0xB098, 0xB3AA, 0xB099, 0xB3AB, 0xB09A, 0xB3AC, 0xB09B, 0x85FA,
+	0xB09C, 0xB3AD, 0xB09D, 0x85FB, 0xB09E, 0x85FC, 0xB09F, 0xB3AE,	0xB0A0, 0xB3AF, 0xB0A1, 0xB3B0, 0xB0A2, 0xB3B1, 0xB0A3, 0x85FD,
+	0xB0A4, 0x85FE, 0xB0A5, 0x8641, 0xB0A6, 0x8642, 0xB0A7, 0x8643,	0xB0A8, 0xB3B2, 0xB0A9, 0xB3B3, 0xB0AA, 0x8644, 0xB0AB, 0xB3B4,
+	0xB0AC, 0xB3B5, 0xB0AD, 0xB3B6, 0xB0AE, 0xB3B7, 0xB0AF, 0xB3B8,	0xB0B0, 0x8645, 0xB0B1, 0xB3B9, 0xB0B2, 0x8646, 0xB0B3, 0xB3BA,
+	0xB0B4, 0xB3BB, 0xB0B5, 0xB3BC, 0xB0B6, 0x8647, 0xB0B7, 0x8648,	0xB0B8, 0xB3BD, 0xB0B9, 0x8649, 0xB0BA, 0x864A, 0xB0BB, 0x864B,
+	0xB0BC, 0xB3BE, 0xB0BD, 0x864C, 0xB0BE, 0x864D, 0xB0BF, 0x864E,	0xB0C0, 0x864F, 0xB0C1, 0x8650, 0xB0C2, 0x8651, 0xB0C3, 0x8652,
+	0xB0C4, 0xB3BF, 0xB0C5, 0xB3C0, 0xB0C6, 0x8653, 0xB0C7, 0xB3C1,	0xB0C8, 0xB3C2, 0xB0C9, 0xB3C3, 0xB0CA, 0x8654, 0xB0CB, 0x8655,
+	0xB0CC, 0x8656, 0xB0CD, 0x8657, 0xB0CE, 0x8658, 0xB0CF, 0x8659,	0xB0D0, 0xB3C4, 0xB0D1, 0xB3C5, 0xB0D2, 0x865A, 0xB0D3, 0x8661,
+	0xB0D4, 0xB3C6, 0xB0D5, 0x8662, 0xB0D6, 0x8663, 0xB0D7, 0x8664,	0xB0D8, 0xB3C7, 0xB0D9, 0x8665, 0xB0DA, 0x8666, 0xB0DB, 0x8667,
+	0xB0DC, 0x8668, 0xB0DD, 0x8669, 0xB0DE, 0x866A, 0xB0DF, 0x866B,	0xB0E0, 0xB3C8, 0xB0E1, 0x866C, 0xB0E2, 0x866D, 0xB0E3, 0x866E,
+	0xB0E4, 0x866F, 0xB0E5, 0xB3C9, 0xB0E6, 0x8670, 0xB0E7, 0x8671,	0xB0E8, 0x8672, 0xB0E9, 0x8673, 0xB0EA, 0x8674, 0xB0EB, 0x8675,
+	0xB0EC, 0x8676, 0xB0ED, 0x8677, 0xB0EE, 0x8678, 0xB0EF, 0x8679,	0xB0F0, 0x867A, 0xB0F1, 0x8681, 0xB0F2, 0x8682, 0xB0F3, 0x8683,
+	0xB0F4, 0x8684, 0xB0F5, 0x8685, 0xB0F6, 0x8686, 0xB0F7, 0x8687,	0xB0F8, 0x8688, 0xB0F9, 0x8689, 0xB0FA, 0x868A, 0xB0FB, 0x868B,
+	0xB0FC, 0x868C, 0xB0FD, 0x868D, 0xB0FE, 0x868E, 0xB0FF, 0x868F,	0xB100, 0x8690, 0xB101, 0x8691, 0xB102, 0x8692, 0xB103, 0x8693,
+	0xB104, 0x8694, 0xB105, 0x8695, 0xB106, 0x8696, 0xB107, 0x8697,	0xB108, 0xB3CA, 0xB109, 0xB3CB, 0xB10A, 0x8698, 0xB10B, 0xB3CC,
+	0xB10C, 0xB3CD, 0xB10D, 0x8699, 0xB10E, 0x869A, 0xB10F, 0x869B,	0xB110, 0xB3CE, 0xB111, 0x869C, 0xB112, 0xB3CF, 0xB113, 0xB3D0,
+	0xB114, 0x869D, 0xB115, 0x869E, 0xB116, 0x869F, 0xB117, 0x86A0,	0xB118, 0xB3D1, 0xB119, 0xB3D2, 0xB11A, 0x86A1, 0xB11B, 0xB3D3,
+	0xB11C, 0xB3D4, 0xB11D, 0xB3D5, 0xB11E, 0x86A2, 0xB11F, 0x86A3,	0xB120, 0x86A4, 0xB121, 0x86A5, 0xB122, 0x86A6, 0xB123, 0xB3D6,
+	0xB124, 0xB3D7, 0xB125, 0xB3D8, 0xB126, 0x86A7, 0xB127, 0x86A8,	0xB128, 0xB3D9, 0xB129, 0x86A9, 0xB12A, 0x86AA, 0xB12B, 0x86AB,
+	0xB12C, 0xB3DA, 0xB12D, 0x86AC, 0xB12E, 0x86AD, 0xB12F, 0x86AE,	0xB130, 0x86AF, 0xB131, 0x86B0, 0xB132, 0x86B1, 0xB133, 0x86B2,
+	0xB134, 0xB3DB, 0xB135, 0xB3DC, 0xB136, 0x86B3, 0xB137, 0xB3DD,	0xB138, 0xB3DE, 0xB139, 0xB3DF, 0xB13A, 0x86B4, 0xB13B, 0x86B5,
+	0xB13C, 0x86B6, 0xB13D, 0x86B7, 0xB13E, 0x86B8, 0xB13F, 0x86B9,	0xB140, 0xB3E0, 0xB141, 0xB3E1, 0xB142, 0x86BA, 0xB143, 0x86BB,
+	0xB144, 0xB3E2, 0xB145, 0x86BC, 0xB146, 0x86BD, 0xB147, 0x86BE,	0xB148, 0xB3E3, 0xB149, 0x86BF, 0xB14A, 0x86C0, 0xB14B, 0x86C1,
+	0xB14C, 0x86C2, 0xB14D, 0x86C3, 0xB14E, 0x86C4, 0xB14F, 0x86C5,	0xB150, 0xB3E4, 0xB151, 0xB3E5, 0xB152, 0x86C6, 0xB153, 0x86C7,
+	0xB154, 0xB3E6, 0xB155, 0xB3E7, 0xB156, 0x86C8, 0xB157, 0x86C9,	0xB158, 0xB3E8, 0xB159, 0x86CA, 0xB15A, 0x86CB, 0xB15B, 0x86CC,
+	0xB15C, 0xB3E9, 0xB15D, 0x86CD, 0xB15E, 0x86CE, 0xB15F, 0x86CF,	0xB160, 0xB3EA, 0xB161, 0x86D0, 0xB162, 0x86D1, 0xB163, 0x86D2,
+	0xB164, 0x86D3, 0xB165, 0x86D4, 0xB166, 0x86D5, 0xB167, 0x86D6,	0xB168, 0x86D7, 0xB169, 0x86D8, 0xB16A, 0x86D9, 0xB16B, 0x86DA,
+	0xB16C, 0x86DB, 0xB16D, 0x86DC, 0xB16E, 0x86DD, 0xB16F, 0x86DE,	0xB170, 0x86DF, 0xB171, 0x86E0, 0xB172, 0x86E1, 0xB173, 0x86E2,
+	0xB174, 0x86E3, 0xB175, 0x86E4, 0xB176, 0x86E5, 0xB177, 0x86E6,	0xB178, 0xB3EB, 0xB179, 0xB3EC, 0xB17A, 0x86E7, 0xB17B, 0x86E8,
+	0xB17C, 0xB3ED, 0xB17D, 0x86E9, 0xB17E, 0x86EA, 0xB17F, 0x86EB,	0xB180, 0xB3EE, 0xB181, 0x86EC, 0xB182, 0xB3EF, 0xB183, 0x86ED,
+	0xB184, 0x86EE, 0xB185, 0x86EF, 0xB186, 0x86F0, 0xB187, 0x86F1,	0xB188, 0xB3F0, 0xB189, 0xB3F1, 0xB18A, 0x86F2, 0xB18B, 0xB3F2,
+	0xB18C, 0x86F3, 0xB18D, 0xB3F3, 0xB18E, 0x86F4, 0xB18F, 0x86F5,	0xB190, 0x86F6, 0xB191, 0x86F7, 0xB192, 0xB3F4, 0xB193, 0xB3F5,
+	0xB194, 0xB3F6, 0xB195, 0x86F8, 0xB196, 0x86F9, 0xB197, 0x86FA,	0xB198, 0xB3F7, 0xB199, 0x86FB, 0xB19A, 0x86FC, 0xB19B, 0x86FD,
+	0xB19C, 0xB3F8, 0xB19D, 0x86FE, 0xB19E, 0x8741, 0xB19F, 0x8742,	0xB1A0, 0x8743, 0xB1A1, 0x8744, 0xB1A2, 0x8745, 0xB1A3, 0x8746,
+	0xB1A4, 0x8747, 0xB1A5, 0x8748, 0xB1A6, 0x8749, 0xB1A7, 0x874A,	0xB1A8, 0xB3F9, 0xB1A9, 0x874B, 0xB1AA, 0x874C, 0xB1AB, 0x874D,
+	0xB1AC, 0x874E, 0xB1AD, 0x874F, 0xB1AE, 0x8750, 0xB1AF, 0x8751,	0xB1B0, 0x8752, 0xB1B1, 0x8753, 0xB1B2, 0x8754, 0xB1B3, 0x8755,
+	0xB1B4, 0x8756, 0xB1B5, 0x8757, 0xB1B6, 0x8758, 0xB1B7, 0x8759,	0xB1B8, 0x875A, 0xB1B9, 0x8761, 0xB1BA, 0x8762, 0xB1BB, 0x8763,
+	0xB1BC, 0x8764, 0xB1BD, 0x8765, 0xB1BE, 0x8766, 0xB1BF, 0x8767,	0xB1C0, 0x8768, 0xB1C1, 0x8769, 0xB1C2, 0x876A, 0xB1C3, 0x876B,
+	0xB1C4, 0x876C, 0xB1C5, 0x876D, 0xB1C6, 0x876E, 0xB1C7, 0x876F,	0xB1C8, 0x8770, 0xB1C9, 0x8771, 0xB1CA, 0x8772, 0xB1CB, 0x8773,
+	0xB1CC, 0xB3FA, 0xB1CD, 0x8774, 0xB1CE, 0x8775, 0xB1CF, 0x8776,	0xB1D0, 0xB3FB, 0xB1D1, 0x8777, 0xB1D2, 0x8778, 0xB1D3, 0x8779,
+	0xB1D4, 0xB3FC, 0xB1D5, 0x877A, 0xB1D6, 0x8781, 0xB1D7, 0x8782,	0xB1D8, 0x8783, 0xB1D9, 0x8784, 0xB1DA, 0x8785, 0xB1DB, 0x8786,
+	0xB1DC, 0xB3FD, 0xB1DD, 0xB3FE, 0xB1DE, 0x8787, 0xB1DF, 0xB4A1,	0xB1E0, 0x8788, 0xB1E1, 0x8789, 0xB1E2, 0x878A, 0xB1E3, 0x878B,
+	0xB1E4, 0x878C, 0xB1E5, 0x878D, 0xB1E6, 0x878E, 0xB1E7, 0x878F,	0xB1E8, 0xB4A2, 0xB1E9, 0xB4A3, 0xB1EA, 0x8790, 0xB1EB, 0x8791,
+	0xB1EC, 0xB4A4, 0xB1ED, 0x8792, 0xB1EE, 0x8793, 0xB1EF, 0x8794,	0xB1F0, 0xB4A5, 0xB1F1, 0x8795, 0xB1F2, 0x8796, 0xB1F3, 0x8797,
+	0xB1F4, 0x8798, 0xB1F5, 0x8799, 0xB1F6, 0x879A, 0xB1F7, 0x879B,	0xB1F8, 0x879C, 0xB1F9, 0xB4A6, 0xB1FA, 0x879D, 0xB1FB, 0xB4A7,
+	0xB1FC, 0x879E, 0xB1FD, 0xB4A8, 0xB1FE, 0x879F, 0xB1FF, 0x87A0,	0xB200, 0x87A1, 0xB201, 0x87A2, 0xB202, 0x87A3, 0xB203, 0x87A4,
+	0xB204, 0xB4A9, 0xB205, 0xB4AA, 0xB206, 0x87A5, 0xB207, 0x87A6,	0xB208, 0xB4AB, 0xB209, 0x87A7, 0xB20A, 0x87A8, 0xB20B, 0xB4AC,
+	0xB20C, 0xB4AD, 0xB20D, 0x87A9, 0xB20E, 0x87AA, 0xB20F, 0x87AB,	0xB210, 0x87AC, 0xB211, 0x87AD, 0xB212, 0x87AE, 0xB213, 0x87AF,
+	0xB214, 0xB4AE, 0xB215, 0xB4AF, 0xB216, 0x87B0, 0xB217, 0xB4B0,	0xB218, 0x87B1, 0xB219, 0xB4B1, 0xB21A, 0x87B2, 0xB21B, 0x87B3,
+	0xB21C, 0x87B4, 0xB21D, 0x87B5, 0xB21E, 0x87B6, 0xB21F, 0x87B7,	0xB220, 0xB4B2, 0xB221, 0x87B8, 0xB222, 0x87B9, 0xB223, 0x87BA,
+	0xB224, 0x87BB, 0xB225, 0x87BC, 0xB226, 0x87BD, 0xB227, 0x87BE,	0xB228, 0x87BF, 0xB229, 0x87C0, 0xB22A, 0x87C1, 0xB22B, 0x87C2,
+	0xB22C, 0x87C3, 0xB22D, 0x87C4, 0xB22E, 0x87C5, 0xB22F, 0x87C6,	0xB230, 0x87C7, 0xB231, 0x87C8, 0xB232, 0x87C9, 0xB233, 0x87CA,
+	0xB234, 0xB4B3, 0xB235, 0x87CB, 0xB236, 0x87CC, 0xB237, 0x87CD,	0xB238, 0x87CE, 0xB239, 0x87CF, 0xB23A, 0x87D0, 0xB23B, 0x87D1,
+	0xB23C, 0xB4B4, 0xB23D, 0x87D2, 0xB23E, 0x87D3, 0xB23F, 0x87D4,	0xB240, 0x87D5, 0xB241, 0x87D6, 0xB242, 0x87D7, 0xB243, 0x87D8,
+	0xB244, 0x87D9, 0xB245, 0x87DA, 0xB246, 0x87DB, 0xB247, 0x87DC,	0xB248, 0x87DD, 0xB249, 0x87DE, 0xB24A, 0x87DF, 0xB24B, 0x87E0,
+	0xB24C, 0x87E1, 0xB24D, 0x87E2, 0xB24E, 0x87E3, 0xB24F, 0x87E4,	0xB250, 0x87E5, 0xB251, 0x87E6, 0xB252, 0x87E7, 0xB253, 0x87E8,
+	0xB254, 0x87E9, 0xB255, 0x87EA, 0xB256, 0x87EB, 0xB257, 0x87EC,	0xB258, 0xB4B5, 0xB259, 0x87ED, 0xB25A, 0x87EE, 0xB25B, 0x87EF,
+	0xB25C, 0xB4B6, 0xB25D, 0x87F0, 0xB25E, 0x87F1, 0xB25F, 0x87F2,	0xB260, 0xB4B7, 0xB261, 0x87F3, 0xB262, 0x87F4, 0xB263, 0x87F5,
+	0xB264, 0x87F6, 0xB265, 0x87F7, 0xB266, 0x87F8, 0xB267, 0x87F9,	0xB268, 0xB4B8, 0xB269, 0xB4B9, 0xB26A, 0x87FA, 0xB26B, 0x87FB,
+	0xB26C, 0x87FC, 0xB26D, 0x87FD, 0xB26E, 0x87FE, 0xB26F, 0x8841,	0xB270, 0x8842, 0xB271, 0x8843, 0xB272, 0x8844, 0xB273, 0x8845,
+	0xB274, 0xB4BA, 0xB275, 0xB4BB, 0xB276, 0x8846, 0xB277, 0x8847,	0xB278, 0x8848, 0xB279, 0x8849, 0xB27A, 0x884A, 0xB27B, 0x884B,
+	0xB27C, 0xB4BC, 0xB27D, 0x884C, 0xB27E, 0x884D, 0xB27F, 0x884E,	0xB280, 0x884F, 0xB281, 0x8850, 0xB282, 0x8851, 0xB283, 0x8852,
+	0xB284, 0xB4BD, 0xB285, 0xB4BE, 0xB286, 0x8853, 0xB287, 0x8854,	0xB288, 0x8855, 0xB289, 0xB4BF, 0xB28A, 0x8856, 0xB28B, 0x8857,
+	0xB28C, 0x8858, 0xB28D, 0x8859, 0xB28E, 0x885A, 0xB28F, 0x8861,	0xB290, 0xB4C0, 0xB291, 0xB4C1, 0xB292, 0x8862, 0xB293, 0x8863,
+	0xB294, 0xB4C2, 0xB295, 0x8864, 0xB296, 0x8865, 0xB297, 0x8866,	0xB298, 0xB4C3, 0xB299, 0xB4C4, 0xB29A, 0xB4C5, 0xB29B, 0x8867,
+	0xB29C, 0x8868, 0xB29D, 0x8869, 0xB29E, 0x886A, 0xB29F, 0x886B,	0xB2A0, 0xB4C6, 0xB2A1, 0xB4C7, 0xB2A2, 0x886C, 0xB2A3, 0xB4C8,
+	0xB2A4, 0x886D, 0xB2A5, 0xB4C9, 0xB2A6, 0xB4CA, 0xB2A7, 0x886E,	0xB2A8, 0x886F, 0xB2A9, 0x8870, 0xB2AA, 0xB4CB, 0xB2AB, 0x8871,
+	0xB2AC, 0xB4CC, 0xB2AD, 0x8872, 0xB2AE, 0x8873, 0xB2AF, 0x8874,	0xB2B0, 0xB4CD, 0xB2B1, 0x8875, 0xB2B2, 0x8876, 0xB2B3, 0x8877,
+	0xB2B4, 0xB4CE, 0xB2B5, 0x8878, 0xB2B6, 0x8879, 0xB2B7, 0x887A,	0xB2B8, 0x8881, 0xB2B9, 0x8882, 0xB2BA, 0x8883, 0xB2BB, 0x8884,
+	0xB2BC, 0x8885, 0xB2BD, 0x8886, 0xB2BE, 0x8887, 0xB2BF, 0x8888,	0xB2C0, 0x8889, 0xB2C1, 0x888A, 0xB2C2, 0x888B, 0xB2C3, 0x888C,
+	0xB2C4, 0x888D, 0xB2C5, 0x888E, 0xB2C6, 0x888F, 0xB2C7, 0x8890,	0xB2C8, 0xB4CF, 0xB2C9, 0xB4D0, 0xB2CA, 0x8891, 0xB2CB, 0x8892,
+	0xB2CC, 0xB4D1, 0xB2CD, 0x8893, 0xB2CE, 0x8894, 0xB2CF, 0x8895,	0xB2D0, 0xB4D2, 0xB2D1, 0x8896, 0xB2D2, 0xB4D3, 0xB2D3, 0x8897,
+	0xB2D4, 0x8898, 0xB2D5, 0x8899, 0xB2D6, 0x889A, 0xB2D7, 0x889B,	0xB2D8, 0xB4D4, 0xB2D9, 0xB4D5, 0xB2DA, 0x889C, 0xB2DB, 0xB4D6,
+	0xB2DC, 0x889D, 0xB2DD, 0xB4D7, 0xB2DE, 0x889E, 0xB2DF, 0x889F,	0xB2E0, 0x88A0, 0xB2E1, 0x88A1, 0xB2E2, 0xB4D8, 0xB2E3, 0x88A2,
+	0xB2E4, 0xB4D9, 0xB2E5, 0xB4DA, 0xB2E6, 0xB4DB, 0xB2E7, 0x88A3,	0xB2E8, 0xB4DC, 0xB2E9, 0x88A4, 0xB2EA, 0x88A5, 0xB2EB, 0xB4DD,
+	0xB2EC, 0xB4DE, 0xB2ED, 0xB4DF, 0xB2EE, 0xB4E0, 0xB2EF, 0xB4E1,	0xB2F0, 0x88A6, 0xB2F1, 0x88A7, 0xB2F2, 0x88A8, 0xB2F3, 0xB4E2,
+	0xB2F4, 0xB4E3, 0xB2F5, 0xB4E4, 0xB2F6, 0x88A9, 0xB2F7, 0xB4E5,	0xB2F8, 0xB4E6, 0xB2F9, 0xB4E7, 0xB2FA, 0xB4E8, 0xB2FB, 0xB4E9,
+	0xB2FC, 0x88AA, 0xB2FD, 0x88AB, 0xB2FE, 0x88AC, 0xB2FF, 0xB4EA,	0xB300, 0xB4EB, 0xB301, 0xB4EC, 0xB302, 0x88AD, 0xB303, 0x88AE,
+	0xB304, 0xB4ED, 0xB305, 0x88AF, 0xB306, 0x88B0, 0xB307, 0x88B1,	0xB308, 0xB4EE, 0xB309, 0x88B2, 0xB30A, 0x88B3, 0xB30B, 0x88B4,
+	0xB30C, 0x88B5, 0xB30D, 0x88B6, 0xB30E, 0x88B7, 0xB30F, 0x88B8,	0xB310, 0xB4EF, 0xB311, 0xB4F0, 0xB312, 0x88B9, 0xB313, 0xB4F1,
+	0xB314, 0xB4F2, 0xB315, 0xB4F3, 0xB316, 0x88BA, 0xB317, 0x88BB,	0xB318, 0x88BC, 0xB319, 0x88BD, 0xB31A, 0x88BE, 0xB31B, 0x88BF,
+	0xB31C, 0xB4F4, 0xB31D, 0x88C0, 0xB31E, 0x88C1, 0xB31F, 0x88C2,	0xB320, 0x88C3, 0xB321, 0x88C4, 0xB322, 0x88C5, 0xB323, 0x88C6,
+	0xB324, 0x88C7, 0xB325, 0x88C8, 0xB326, 0x88C9, 0xB327, 0x88CA,	0xB328, 0x88CB, 0xB329, 0x88CC, 0xB32A, 0x88CD, 0xB32B, 0x88CE,
+	0xB32C, 0x88CF, 0xB32D, 0x88D0, 0xB32E, 0x88D1, 0xB32F, 0x88D2,	0xB330, 0x88D3, 0xB331, 0x88D4, 0xB332, 0x88D5, 0xB333, 0x88D6,
+	0xB334, 0x88D7, 0xB335, 0x88D8, 0xB336, 0x88D9, 0xB337, 0x88DA,	0xB338, 0x88DB, 0xB339, 0x88DC, 0xB33A, 0x88DD, 0xB33B, 0x88DE,
+	0xB33C, 0x88DF, 0xB33D, 0x88E0, 0xB33E, 0x88E1, 0xB33F, 0x88E2,	0xB340, 0x88E3, 0xB341, 0x88E4, 0xB342, 0x88E5, 0xB343, 0x88E6,
+	0xB344, 0x88E7, 0xB345, 0x88E8, 0xB346, 0x88E9, 0xB347, 0x88EA,	0xB348, 0x88EB, 0xB349, 0x88EC, 0xB34A, 0x88ED, 0xB34B, 0x88EE,
+	0xB34C, 0x88EF, 0xB34D, 0x88F0, 0xB34E, 0x88F1, 0xB34F, 0x88F2,	0xB350, 0x88F3, 0xB351, 0x88F4, 0xB352, 0x88F5, 0xB353, 0x88F6,
+	0xB354, 0xB4F5, 0xB355, 0xB4F6, 0xB356, 0xB4F7, 0xB357, 0x88F7,	0xB358, 0xB4F8, 0xB359, 0x88F8, 0xB35A, 0x88F9, 0xB35B, 0xB4F9,
+	0xB35C, 0xB4FA, 0xB35D, 0x88FA, 0xB35E, 0xB4FB, 0xB35F, 0xB4FC,	0xB360, 0x88FB, 0xB361, 0x88FC, 0xB362, 0x88FD, 0xB363, 0x88FE,
+	0xB364, 0xB4FD, 0xB365, 0xB4FE, 0xB366, 0x8941, 0xB367, 0xB5A1,	0xB368, 0x8942, 0xB369, 0xB5A2, 0xB36A, 0x8943, 0xB36B, 0xB5A3,
+	0xB36C, 0x8944, 0xB36D, 0x8945, 0xB36E, 0xB5A4, 0xB36F, 0x8946,	0xB370, 0xB5A5, 0xB371, 0xB5A6, 0xB372, 0x8947, 0xB373, 0x8948,
+	0xB374, 0xB5A7, 0xB375, 0x8949, 0xB376, 0x894A, 0xB377, 0x894B,	0xB378, 0xB5A8, 0xB379, 0x894C, 0xB37A, 0x894D, 0xB37B, 0x894E,
+	0xB37C, 0x894F, 0xB37D, 0x8950, 0xB37E, 0x8951, 0xB37F, 0x8952,	0xB380, 0xB5A9, 0xB381, 0xB5AA, 0xB382, 0x8953, 0xB383, 0xB5AB,
+	0xB384, 0xB5AC, 0xB385, 0xB5AD, 0xB386, 0x8954, 0xB387, 0x8955,	0xB388, 0x8956, 0xB389, 0x8957, 0xB38A, 0x8958, 0xB38B, 0x8959,
+	0xB38C, 0xB5AE, 0xB38D, 0x895A, 0xB38E, 0x8961, 0xB38F, 0x8962,	0xB390, 0xB5AF, 0xB391, 0x8963, 0xB392, 0x8964, 0xB393, 0x8965,
+	0xB394, 0xB5B0, 0xB395, 0x8966, 0xB396, 0x8967, 0xB397, 0x8968,	0xB398, 0x8969, 0xB399, 0x896A, 0xB39A, 0x896B, 0xB39B, 0x896C,
+	0xB39C, 0x896D, 0xB39D, 0x896E, 0xB39E, 0x896F, 0xB39F, 0x8970,	0xB3A0, 0xB5B1, 0xB3A1, 0xB5B2, 0xB3A2, 0x8971, 0xB3A3, 0x8972,
+	0xB3A4, 0x8973, 0xB3A5, 0x8974, 0xB3A6, 0x8975, 0xB3A7, 0x8976,	0xB3A8, 0xB5B3, 0xB3A9, 0x8977, 0xB3AA, 0x8978, 0xB3AB, 0x8979,
+	0xB3AC, 0xB5B4, 0xB3AD, 0x897A, 0xB3AE, 0x8981, 0xB3AF, 0x8982,	0xB3B0, 0x8983, 0xB3B1, 0x8984, 0xB3B2, 0x8985, 0xB3B3, 0x8986,
+	0xB3B4, 0x8987, 0xB3B5, 0x8988, 0xB3B6, 0x8989, 0xB3B7, 0x898A,	0xB3B8, 0x898B, 0xB3B9, 0x898C, 0xB3BA, 0x898D, 0xB3BB, 0x898E,
+	0xB3BC, 0x898F, 0xB3BD, 0x8990, 0xB3BE, 0x8991, 0xB3BF, 0x8992,	0xB3C0, 0x8993, 0xB3C1, 0x8994, 0xB3C2, 0x8995, 0xB3C3, 0x8996,
+	0xB3C4, 0xB5B5, 0xB3C5, 0xB5B6, 0xB3C6, 0x8997, 0xB3C7, 0x8998,	0xB3C8, 0xB5B7, 0xB3C9, 0x8999, 0xB3CA, 0x899A, 0xB3CB, 0xB5B8,
+	0xB3CC, 0xB5B9, 0xB3CD, 0x899B, 0xB3CE, 0xB5BA, 0xB3CF, 0x899C,	0xB3D0, 0xB5BB, 0xB3D1, 0x899D, 0xB3D2, 0x899E, 0xB3D3, 0x899F,
+	0xB3D4, 0xB5BC, 0xB3D5, 0xB5BD, 0xB3D6, 0x89A0, 0xB3D7, 0xB5BE,	0xB3D8, 0x89A1, 0xB3D9, 0xB5BF, 0xB3DA, 0x89A2, 0xB3DB, 0xB5C0,
+	0xB3DC, 0x89A3, 0xB3DD, 0xB5C1, 0xB3DE, 0x89A4, 0xB3DF, 0x89A5,	0xB3E0, 0xB5C2, 0xB3E1, 0x89A6, 0xB3E2, 0x89A7, 0xB3E3, 0x89A8,
+	0xB3E4, 0xB5C3, 0xB3E5, 0x89A9, 0xB3E6, 0x89AA, 0xB3E7, 0x89AB,	0xB3E8, 0xB5C4, 0xB3E9, 0x89AC, 0xB3EA, 0x89AD, 0xB3EB, 0x89AE,
+	0xB3EC, 0x89AF, 0xB3ED, 0x89B0, 0xB3EE, 0x89B1, 0xB3EF, 0x89B2,	0xB3F0, 0x89B3, 0xB3F1, 0x89B4, 0xB3F2, 0x89B5, 0xB3F3, 0x89B6,
+	0xB3F4, 0x89B7, 0xB3F5, 0x89B8, 0xB3F6, 0x89B9, 0xB3F7, 0x89BA,	0xB3F8, 0x89BB, 0xB3F9, 0x89BC, 0xB3FA, 0x89BD, 0xB3FB, 0x89BE,
+	0xB3FC, 0xB5C5, 0xB3FD, 0x89BF, 0xB3FE, 0x89C0, 0xB3FF, 0x89C1,	0xB400, 0x89C2, 0xB401, 0x89C3, 0xB402, 0x89C4, 0xB403, 0x89C5,
+	0xB404, 0x89C6, 0xB405, 0x89C7, 0xB406, 0x89C8, 0xB407, 0x89C9,	0xB408, 0x89CA, 0xB409, 0x89CB, 0xB40A, 0x89CC, 0xB40B, 0x89CD,
+	0xB40C, 0x89CE, 0xB40D, 0x89CF, 0xB40E, 0x89D0, 0xB40F, 0x89D1,	0xB410, 0xB5C6, 0xB411, 0x89D2, 0xB412, 0x89D3, 0xB413, 0x89D4,
+	0xB414, 0x89D5, 0xB415, 0x89D6, 0xB416, 0x89D7, 0xB417, 0x89D8,	0xB418, 0xB5C7, 0xB419, 0x89D9, 0xB41A, 0x89DA, 0xB41B, 0x89DB,
+	0xB41C, 0xB5C8, 0xB41D, 0x89DC, 0xB41E, 0x89DD, 0xB41F, 0x89DE,	0xB420, 0xB5C9, 0xB421, 0x89DF, 0xB422, 0x89E0, 0xB423, 0x89E1,
+	0xB424, 0x89E2, 0xB425, 0x89E3, 0xB426, 0x89E4, 0xB427, 0x89E5,	0xB428, 0xB5CA, 0xB429, 0xB5CB, 0xB42A, 0x89E6, 0xB42B, 0xB5CC,
+	0xB42C, 0x89E7, 0xB42D, 0x89E8, 0xB42E, 0x89E9, 0xB42F, 0x89EA,	0xB430, 0x89EB, 0xB431, 0x89EC, 0xB432, 0x89ED, 0xB433, 0x89EE,
+	0xB434, 0xB5CD, 0xB435, 0x89EF, 0xB436, 0x89F0, 0xB437, 0x89F1,	0xB438, 0x89F2, 0xB439, 0x89F3, 0xB43A, 0x89F4, 0xB43B, 0x89F5,
+	0xB43C, 0x89F6, 0xB43D, 0x89F7, 0xB43E, 0x89F8, 0xB43F, 0x89F9,	0xB440, 0x89FA, 0xB441, 0x89FB, 0xB442, 0x89FC, 0xB443, 0x89FD,
+	0xB444, 0x89FE, 0xB445, 0x8A41, 0xB446, 0x8A42, 0xB447, 0x8A43,	0xB448, 0x8A44, 0xB449, 0x8A45, 0xB44A, 0x8A46, 0xB44B, 0x8A47,
+	0xB44C, 0x8A48, 0xB44D, 0x8A49, 0xB44E, 0x8A4A, 0xB44F, 0x8A4B,	0xB450, 0xB5CE, 0xB451, 0xB5CF, 0xB452, 0x8A4C, 0xB453, 0x8A4D,
+	0xB454, 0xB5D0, 0xB455, 0x8A4E, 0xB456, 0x8A4F, 0xB457, 0x8A50,	0xB458, 0xB5D1, 0xB459, 0x8A51, 0xB45A, 0x8A52, 0xB45B, 0x8A53,
+	0xB45C, 0x8A54, 0xB45D, 0x8A55, 0xB45E, 0x8A56, 0xB45F, 0x8A57,	0xB460, 0xB5D2, 0xB461, 0xB5D3, 0xB462, 0x8A58, 0xB463, 0xB5D4,
+	0xB464, 0x8A59, 0xB465, 0xB5D5, 0xB466, 0x8A5A, 0xB467, 0x8A61,	0xB468, 0x8A62, 0xB469, 0x8A63, 0xB46A, 0x8A64, 0xB46B, 0x8A65,
+	0xB46C, 0xB5D6, 0xB46D, 0x8A66, 0xB46E, 0x8A67, 0xB46F, 0x8A68,	0xB470, 0x8A69, 0xB471, 0x8A6A, 0xB472, 0x8A6B, 0xB473, 0x8A6C,
+	0xB474, 0x8A6D, 0xB475, 0x8A6E, 0xB476, 0x8A6F, 0xB477, 0x8A70,	0xB478, 0x8A71, 0xB479, 0x8A72, 0xB47A, 0x8A73, 0xB47B, 0x8A74,
+	0xB47C, 0x8A75, 0xB47D, 0x8A76, 0xB47E, 0x8A77, 0xB47F, 0x8A78,	0xB480, 0xB5D7, 0xB481, 0x8A79, 0xB482, 0x8A7A, 0xB483, 0x8A81,
+	0xB484, 0x8A82, 0xB485, 0x8A83, 0xB486, 0x8A84, 0xB487, 0x8A85,	0xB488, 0xB5D8, 0xB489, 0x8A86, 0xB48A, 0x8A87, 0xB48B, 0x8A88,
+	0xB48C, 0x8A89, 0xB48D, 0x8A8A, 0xB48E, 0x8A8B, 0xB48F, 0x8A8C,	0xB490, 0x8A8D, 0xB491, 0x8A8E, 0xB492, 0x8A8F, 0xB493, 0x8A90,
+	0xB494, 0x8A91, 0xB495, 0x8A92, 0xB496, 0x8A93, 0xB497, 0x8A94,	0xB498, 0x8A95, 0xB499, 0x8A96, 0xB49A, 0x8A97, 0xB49B, 0x8A98,
+	0xB49C, 0x8A99, 0xB49D, 0xB5D9, 0xB49E, 0x8A9A, 0xB49F, 0x8A9B,	0xB4A0, 0x8A9C, 0xB4A1, 0x8A9D, 0xB4A2, 0x8A9E, 0xB4A3, 0x8A9F,
+	0xB4A4, 0xB5DA, 0xB4A5, 0x8AA0, 0xB4A6, 0x8AA1, 0xB4A7, 0x8AA2,	0xB4A8, 0xB5DB, 0xB4A9, 0x8AA3, 0xB4AA, 0x8AA4, 0xB4AB, 0x8AA5,
+	0xB4AC, 0xB5DC, 0xB4AD, 0x8AA6, 0xB4AE, 0x8AA7, 0xB4AF, 0x8AA8,	0xB4B0, 0x8AA9, 0xB4B1, 0x8AAA, 0xB4B2, 0x8AAB, 0xB4B3, 0x8AAC,
+	0xB4B4, 0x8AAD, 0xB4B5, 0xB5DD, 0xB4B6, 0x8AAE, 0xB4B7, 0xB5DE,	0xB4B8, 0x8AAF, 0xB4B9, 0xB5DF, 0xB4BA, 0x8AB0, 0xB4BB, 0x8AB1,
+	0xB4BC, 0x8AB2, 0xB4BD, 0x8AB3, 0xB4BE, 0x8AB4, 0xB4BF, 0x8AB5,	0xB4C0, 0xB5E0, 0xB4C1, 0x8AB6, 0xB4C2, 0x8AB7, 0xB4C3, 0x8AB8,
+	0xB4C4, 0xB5E1, 0xB4C5, 0x8AB9, 0xB4C6, 0x8ABA, 0xB4C7, 0x8ABB,	0xB4C8, 0xB5E2, 0xB4C9, 0x8ABC, 0xB4CA, 0x8ABD, 0xB4CB, 0x8ABE,
+	0xB4CC, 0x8ABF, 0xB4CD, 0x8AC0, 0xB4CE, 0x8AC1, 0xB4CF, 0x8AC2,	0xB4D0, 0xB5E3, 0xB4D1, 0x8AC3, 0xB4D2, 0x8AC4, 0xB4D3, 0x8AC5,
+	0xB4D4, 0x8AC6, 0xB4D5, 0xB5E4, 0xB4D6, 0x8AC7, 0xB4D7, 0x8AC8,	0xB4D8, 0x8AC9, 0xB4D9, 0x8ACA, 0xB4DA, 0x8ACB, 0xB4DB, 0x8ACC,
+	0xB4DC, 0xB5E5, 0xB4DD, 0xB5E6, 0xB4DE, 0x8ACD, 0xB4DF, 0x8ACE,	0xB4E0, 0xB5E7, 0xB4E1, 0x8ACF, 0xB4E2, 0x8AD0, 0xB4E3, 0xB5E8,
+	0xB4E4, 0xB5E9, 0xB4E5, 0x8AD1, 0xB4E6, 0xB5EA, 0xB4E7, 0x8AD2,	0xB4E8, 0x8AD3, 0xB4E9, 0x8AD4, 0xB4EA, 0x8AD5, 0xB4EB, 0x8AD6,
+	0xB4EC, 0xB5EB, 0xB4ED, 0xB5EC, 0xB4EE, 0x8AD7, 0xB4EF, 0xB5ED,	0xB4F0, 0x8AD8, 0xB4F1, 0xB5EE, 0xB4F2, 0x8AD9, 0xB4F3, 0x8ADA,
+	0xB4F4, 0x8ADB, 0xB4F5, 0x8ADC, 0xB4F6, 0x8ADD, 0xB4F7, 0x8ADE,	0xB4F8, 0xB5EF, 0xB4F9, 0x8ADF, 0xB4FA, 0x8AE0, 0xB4FB, 0x8AE1,
+	0xB4FC, 0x8AE2, 0xB4FD, 0x8AE3, 0xB4FE, 0x8AE4, 0xB4FF, 0x8AE5,	0xB500, 0x8AE6, 0xB501, 0x8AE7, 0xB502, 0x8AE8, 0xB503, 0x8AE9,
+	0xB504, 0x8AEA, 0xB505, 0x8AEB, 0xB506, 0x8AEC, 0xB507, 0x8AED,	0xB508, 0x8AEE, 0xB509, 0x8AEF, 0xB50A, 0x8AF0, 0xB50B, 0x8AF1,
+	0xB50C, 0x8AF2, 0xB50D, 0x8AF3, 0xB50E, 0x8AF4, 0xB50F, 0x8AF5,	0xB510, 0x8AF6, 0xB511, 0x8AF7, 0xB512, 0x8AF8, 0xB513, 0x8AF9,
+	0xB514, 0xB5F0, 0xB515, 0xB5F1, 0xB516, 0x8AFA, 0xB517, 0x8AFB,	0xB518, 0xB5F2, 0xB519, 0x8AFC, 0xB51A, 0x8AFD, 0xB51B, 0xB5F3,
+	0xB51C, 0xB5F4, 0xB51D, 0x8AFE, 0xB51E, 0x8B41, 0xB51F, 0x8B42,	0xB520, 0x8B43, 0xB521, 0x8B44, 0xB522, 0x8B45, 0xB523, 0x8B46,
+	0xB524, 0xB5F5, 0xB525, 0xB5F6, 0xB526, 0x8B47, 0xB527, 0xB5F7,	0xB528, 0xB5F8, 0xB529, 0xB5F9, 0xB52A, 0xB5FA, 0xB52B, 0x8B48,
+	0xB52C, 0x8B49, 0xB52D, 0x8B4A, 0xB52E, 0x8B4B, 0xB52F, 0x8B4C,	0xB530, 0xB5FB, 0xB531, 0xB5FC, 0xB532, 0x8B4D, 0xB533, 0x8B4E,
+	0xB534, 0xB5FD, 0xB535, 0x8B4F, 0xB536, 0x8B50, 0xB537, 0x8B51,	0xB538, 0xB5FE, 0xB539, 0x8B52, 0xB53A, 0x8B53, 0xB53B, 0x8B54,
+	0xB53C, 0x8B55, 0xB53D, 0x8B56, 0xB53E, 0x8B57, 0xB53F, 0x8B58,	0xB540, 0xB6A1, 0xB541, 0xB6A2, 0xB542, 0x8B59, 0xB543, 0xB6A3,
+	0xB544, 0xB6A4, 0xB545, 0xB6A5, 0xB546, 0x8B5A, 0xB547, 0x8B61,	0xB548, 0x8B62, 0xB549, 0x8B63, 0xB54A, 0x8B64, 0xB54B, 0xB6A6,
+	0xB54C, 0xB6A7, 0xB54D, 0xB6A8, 0xB54E, 0x8B65, 0xB54F, 0x8B66,	0xB550, 0xB6A9, 0xB551, 0x8B67, 0xB552, 0x8B68, 0xB553, 0x8B69,
+	0xB554, 0xB6AA, 0xB555, 0x8B6A, 0xB556, 0x8B6B, 0xB557, 0x8B6C,	0xB558, 0x8B6D, 0xB559, 0x8B6E, 0xB55A, 0x8B6F, 0xB55B, 0x8B70,
+	0xB55C, 0xB6AB, 0xB55D, 0xB6AC, 0xB55E, 0x8B71, 0xB55F, 0xB6AD,	0xB560, 0xB6AE, 0xB561, 0xB6AF, 0xB562, 0x8B72, 0xB563, 0x8B73,
+	0xB564, 0x8B74, 0xB565, 0x8B75, 0xB566, 0x8B76, 0xB567, 0x8B77,	0xB568, 0x8B78, 0xB569, 0x8B79, 0xB56A, 0x8B7A, 0xB56B, 0x8B81,
+	0xB56C, 0x8B82, 0xB56D, 0x8B83, 0xB56E, 0x8B84, 0xB56F, 0x8B85,	0xB570, 0x8B86, 0xB571, 0x8B87, 0xB572, 0x8B88, 0xB573, 0x8B89,
+	0xB574, 0x8B8A, 0xB575, 0x8B8B, 0xB576, 0x8B8C, 0xB577, 0x8B8D,	0xB578, 0x8B8E, 0xB579, 0x8B8F, 0xB57A, 0x8B90, 0xB57B, 0x8B91,
+	0xB57C, 0x8B92, 0xB57D, 0x8B93, 0xB57E, 0x8B94, 0xB57F, 0x8B95,	0xB580, 0x8B96, 0xB581, 0x8B97, 0xB582, 0x8B98, 0xB583, 0x8B99,
+	0xB584, 0x8B9A, 0xB585, 0x8B9B, 0xB586, 0x8B9C, 0xB587, 0x8B9D,	0xB588, 0x8B9E, 0xB589, 0x8B9F, 0xB58A, 0x8BA0, 0xB58B, 0x8BA1,
+	0xB58C, 0x8BA2, 0xB58D, 0x8BA3, 0xB58E, 0x8BA4, 0xB58F, 0x8BA5,	0xB590, 0x8BA6, 0xB591, 0x8BA7, 0xB592, 0x8BA8, 0xB593, 0x8BA9,
+	0xB594, 0x8BAA, 0xB595, 0x8BAB, 0xB596, 0x8BAC, 0xB597, 0x8BAD,	0xB598, 0x8BAE, 0xB599, 0x8BAF, 0xB59A, 0x8BB0, 0xB59B, 0x8BB1,
+	0xB59C, 0x8BB2, 0xB59D, 0x8BB3, 0xB59E, 0x8BB4, 0xB59F, 0x8BB5,	0xB5A0, 0xB6B0, 0xB5A1, 0xB6B1, 0xB5A2, 0x8BB6, 0xB5A3, 0x8BB7,
+	0xB5A4, 0xB6B2, 0xB5A5, 0x8BB8, 0xB5A6, 0x8BB9, 0xB5A7, 0x8BBA,	0xB5A8, 0xB6B3, 0xB5A9, 0x8BBB, 0xB5AA, 0xB6B4, 0xB5AB, 0xB6B5,
+	0xB5AC, 0x8BBC, 0xB5AD, 0x8BBD, 0xB5AE, 0x8BBE, 0xB5AF, 0x8BBF,	0xB5B0, 0xB6B6, 0xB5B1, 0xB6B7, 0xB5B2, 0x8BC0, 0xB5B3, 0xB6B8,
+	0xB5B4, 0xB6B9, 0xB5B5, 0xB6BA, 0xB5B6, 0x8BC1, 0xB5B7, 0x8BC2,	0xB5B8, 0x8BC3, 0xB5B9, 0x8BC4, 0xB5BA, 0x8BC5, 0xB5BB, 0xB6BB,
+	0xB5BC, 0xB6BC, 0xB5BD, 0xB6BD, 0xB5BE, 0x8BC6, 0xB5BF, 0x8BC7,	0xB5C0, 0xB6BE, 0xB5C1, 0x8BC8, 0xB5C2, 0x8BC9, 0xB5C3, 0x8BCA,
+	0xB5C4, 0xB6BF, 0xB5C5, 0x8BCB, 0xB5C6, 0x8BCC, 0xB5C7, 0x8BCD,	0xB5C8, 0x8BCE, 0xB5C9, 0x8BCF, 0xB5CA, 0x8BD0, 0xB5CB, 0x8BD1,
+	0xB5CC, 0xB6C0, 0xB5CD, 0xB6C1, 0xB5CE, 0x8BD2, 0xB5CF, 0xB6C2,	0xB5D0, 0xB6C3, 0xB5D1, 0xB6C4, 0xB5D2, 0x8BD3, 0xB5D3, 0x8BD4,
+	0xB5D4, 0x8BD5, 0xB5D5, 0x8BD6, 0xB5D6, 0x8BD7, 0xB5D7, 0x8BD8,	0xB5D8, 0xB6C5, 0xB5D9, 0x8BD9, 0xB5DA, 0x8BDA, 0xB5DB, 0x8BDB,
+	0xB5DC, 0x8BDC, 0xB5DD, 0x8BDD, 0xB5DE, 0x8BDE, 0xB5DF, 0x8BDF,	0xB5E0, 0x8BE0, 0xB5E1, 0x8BE1, 0xB5E2, 0x8BE2, 0xB5E3, 0x8BE3,
+	0xB5E4, 0x8BE4, 0xB5E5, 0x8BE5, 0xB5E6, 0x8BE6, 0xB5E7, 0x8BE7,	0xB5E8, 0x8BE8, 0xB5E9, 0x8BE9, 0xB5EA, 0x8BEA, 0xB5EB, 0x8BEB,
+	0xB5EC, 0xB6C6, 0xB5ED, 0x8BEC, 0xB5EE, 0x8BED, 0xB5EF, 0x8BEE,	0xB5F0, 0x8BEF, 0xB5F1, 0x8BF0, 0xB5F2, 0x8BF1, 0xB5F3, 0x8BF2,
+	0xB5F4, 0x8BF3, 0xB5F5, 0x8BF4, 0xB5F6, 0x8BF5, 0xB5F7, 0x8BF6,	0xB5F8, 0x8BF7, 0xB5F9, 0x8BF8, 0xB5FA, 0x8BF9, 0xB5FB, 0x8BFA,
+	0xB5FC, 0x8BFB, 0xB5FD, 0x8BFC, 0xB5FE, 0x8BFD, 0xB5FF, 0x8BFE,	0xB600, 0x8C41, 0xB601, 0x8C42, 0xB602, 0x8C43, 0xB603, 0x8C44,
+	0xB604, 0x8C45, 0xB605, 0x8C46, 0xB606, 0x8C47, 0xB607, 0x8C48,	0xB608, 0x8C49, 0xB609, 0x8C4A, 0xB60A, 0x8C4B, 0xB60B, 0x8C4C,
+	0xB60C, 0x8C4D, 0xB60D, 0x8C4E, 0xB60E, 0x8C4F, 0xB60F, 0x8C50,	0xB610, 0xB6C7, 0xB611, 0xB6C8, 0xB612, 0x8C51, 0xB613, 0x8C52,
+	0xB614, 0xB6C9, 0xB615, 0x8C53, 0xB616, 0x8C54, 0xB617, 0x8C55,	0xB618, 0xB6CA, 0xB619, 0x8C56, 0xB61A, 0x8C57, 0xB61B, 0x8C58,
+	0xB61C, 0x8C59, 0xB61D, 0x8C5A, 0xB61E, 0x8C61, 0xB61F, 0x8C62,	0xB620, 0x8C63, 0xB621, 0x8C64, 0xB622, 0x8C65, 0xB623, 0x8C66,
+	0xB624, 0x8C67, 0xB625, 0xB6CB, 0xB626, 0x8C68, 0xB627, 0x8C69,	0xB628, 0x8C6A, 0xB629, 0x8C6B, 0xB62A, 0x8C6C, 0xB62B, 0x8C6D,
+	0xB62C, 0xB6CC, 0xB62D, 0x8C6E, 0xB62E, 0x8C6F, 0xB62F, 0x8C70,	0xB630, 0x8C71, 0xB631, 0x8C72, 0xB632, 0x8C73, 0xB633, 0x8C74,
+	0xB634, 0xB6CD, 0xB635, 0x8C75, 0xB636, 0x8C76, 0xB637, 0x8C77,	0xB638, 0x8C78, 0xB639, 0x8C79, 0xB63A, 0x8C7A, 0xB63B, 0x8C81,
+	0xB63C, 0x8C82, 0xB63D, 0x8C83, 0xB63E, 0x8C84, 0xB63F, 0x8C85,	0xB640, 0x8C86, 0xB641, 0x8C87, 0xB642, 0x8C88, 0xB643, 0x8C89,
+	0xB644, 0x8C8A, 0xB645, 0x8C8B, 0xB646, 0x8C8C, 0xB647, 0x8C8D,	0xB648, 0xB6CE, 0xB649, 0x8C8E, 0xB64A, 0x8C8F, 0xB64B, 0x8C90,
+	0xB64C, 0x8C91, 0xB64D, 0x8C92, 0xB64E, 0x8C93, 0xB64F, 0x8C94,	0xB650, 0x8C95, 0xB651, 0x8C96, 0xB652, 0x8C97, 0xB653, 0x8C98,
+	0xB654, 0x8C99, 0xB655, 0x8C9A, 0xB656, 0x8C9B, 0xB657, 0x8C9C,	0xB658, 0x8C9D, 0xB659, 0x8C9E, 0xB65A, 0x8C9F, 0xB65B, 0x8CA0,
+	0xB65C, 0x8CA1, 0xB65D, 0x8CA2, 0xB65E, 0x8CA3, 0xB65F, 0x8CA4,	0xB660, 0x8CA5, 0xB661, 0x8CA6, 0xB662, 0x8CA7, 0xB663, 0x8CA8,
+	0xB664, 0xB6CF, 0xB665, 0x8CA9, 0xB666, 0x8CAA, 0xB667, 0x8CAB,	0xB668, 0xB6D0, 0xB669, 0x8CAC, 0xB66A, 0x8CAD, 0xB66B, 0x8CAE,
+	0xB66C, 0x8CAF, 0xB66D, 0x8CB0, 0xB66E, 0x8CB1, 0xB66F, 0x8CB2,	0xB670, 0x8CB3, 0xB671, 0x8CB4, 0xB672, 0x8CB5, 0xB673, 0x8CB6,
+	0xB674, 0x8CB7, 0xB675, 0x8CB8, 0xB676, 0x8CB9, 0xB677, 0x8CBA,	0xB678, 0x8CBB, 0xB679, 0x8CBC, 0xB67A, 0x8CBD, 0xB67B, 0x8CBE,
+	0xB67C, 0x8CBF, 0xB67D, 0x8CC0, 0xB67E, 0x8CC1, 0xB67F, 0x8CC2,	0xB680, 0x8CC3, 0xB681, 0x8CC4, 0xB682, 0x8CC5, 0xB683, 0x8CC6,
+	0xB684, 0x8CC7, 0xB685, 0x8CC8, 0xB686, 0x8CC9, 0xB687, 0x8CCA,	0xB688, 0x8CCB, 0xB689, 0x8CCC, 0xB68A, 0x8CCD, 0xB68B, 0x8CCE,
+	0xB68C, 0x8CCF, 0xB68D, 0x8CD0, 0xB68E, 0x8CD1, 0xB68F, 0x8CD2,	0xB690, 0x8CD3, 0xB691, 0x8CD4, 0xB692, 0x8CD5, 0xB693, 0x8CD6,
+	0xB694, 0x8CD7, 0xB695, 0x8CD8, 0xB696, 0x8CD9, 0xB697, 0x8CDA,	0xB698, 0x8CDB, 0xB699, 0x8CDC, 0xB69A, 0x8CDD, 0xB69B, 0x8CDE,
+	0xB69C, 0xB6D1, 0xB69D, 0xB6D2, 0xB69E, 0x8CDF, 0xB69F, 0x8CE0,	0xB6A0, 0xB6D3, 0xB6A1, 0x8CE1, 0xB6A2, 0x8CE2, 0xB6A3, 0x8CE3,
+	0xB6A4, 0xB6D4, 0xB6A5, 0x8CE4, 0xB6A6, 0x8CE5, 0xB6A7, 0x8CE6,	0xB6A8, 0x8CE7, 0xB6A9, 0x8CE8, 0xB6AA, 0x8CE9, 0xB6AB, 0xB6D5,
+	0xB6AC, 0xB6D6, 0xB6AD, 0x8CEA, 0xB6AE, 0x8CEB, 0xB6AF, 0x8CEC,	0xB6B0, 0x8CED, 0xB6B1, 0xB6D7, 0xB6B2, 0x8CEE, 0xB6B3, 0x8CEF,
+	0xB6B4, 0x8CF0, 0xB6B5, 0x8CF1, 0xB6B6, 0x8CF2, 0xB6B7, 0x8CF3,	0xB6B8, 0x8CF4, 0xB6B9, 0x8CF5, 0xB6BA, 0x8CF6, 0xB6BB, 0x8CF7,
+	0xB6BC, 0x8CF8, 0xB6BD, 0x8CF9, 0xB6BE, 0x8CFA, 0xB6BF, 0x8CFB,	0xB6C0, 0x8CFC, 0xB6C1, 0x8CFD, 0xB6C2, 0x8CFE, 0xB6C3, 0x8D41,
+	0xB6C4, 0x8D42, 0xB6C5, 0x8D43, 0xB6C6, 0x8D44, 0xB6C7, 0x8D45,	0xB6C8, 0x8D46, 0xB6C9, 0x8D47, 0xB6CA, 0x8D48, 0xB6CB, 0x8D49,
+	0xB6CC, 0x8D4A, 0xB6CD, 0x8D4B, 0xB6CE, 0x8D4C, 0xB6CF, 0x8D4D,	0xB6D0, 0x8D4E, 0xB6D1, 0x8D4F, 0xB6D2, 0x8D50, 0xB6D3, 0x8D51,
+	0xB6D4, 0xB6D8, 0xB6D5, 0x8D52, 0xB6D6, 0x8D53, 0xB6D7, 0x8D54,	0xB6D8, 0x8D55, 0xB6D9, 0x8D56, 0xB6DA, 0x8D57, 0xB6DB, 0x8D58,
+	0xB6DC, 0x8D59, 0xB6DD, 0x8D5A, 0xB6DE, 0x8D61, 0xB6DF, 0x8D62,	0xB6E0, 0x8D63, 0xB6E1, 0x8D64, 0xB6E2, 0x8D65, 0xB6E3, 0x8D66,
+	0xB6E4, 0x8D67, 0xB6E5, 0x8D68, 0xB6E6, 0x8D69, 0xB6E7, 0x8D6A,	0xB6E8, 0x8D6B, 0xB6E9, 0x8D6C, 0xB6EA, 0x8D6D, 0xB6EB, 0x8D6E,
+	0xB6EC, 0x8D6F, 0xB6ED, 0x8D70, 0xB6EE, 0x8D71, 0xB6EF, 0x8D72,	0xB6F0, 0xB6D9, 0xB6F1, 0x8D73, 0xB6F2, 0x8D74, 0xB6F3, 0x8D75,
+	0xB6F4, 0xB6DA, 0xB6F5, 0x8D76, 0xB6F6, 0x8D77, 0xB6F7, 0x8D78,	0xB6F8, 0xB6DB, 0xB6F9, 0x8D79, 0xB6FA, 0x8D7A, 0xB6FB, 0x8D81,
+	0xB6FC, 0x8D82, 0xB6FD, 0x8D83, 0xB6FE, 0x8D84, 0xB6FF, 0x8D85,	0xB700, 0xB6DC, 0xB701, 0xB6DD, 0xB702, 0x8D86, 0xB703, 0x8D87,
+	0xB704, 0x8D88, 0xB705, 0xB6DE, 0xB706, 0x8D89, 0xB707, 0x8D8A,	0xB708, 0x8D8B, 0xB709, 0x8D8C, 0xB70A, 0x8D8D, 0xB70B, 0x8D8E,
+	0xB70C, 0x8D8F, 0xB70D, 0x8D90, 0xB70E, 0x8D91, 0xB70F, 0x8D92,	0xB710, 0x8D93, 0xB711, 0x8D94, 0xB712, 0x8D95, 0xB713, 0x8D96,
+	0xB714, 0x8D97, 0xB715, 0x8D98, 0xB716, 0x8D99, 0xB717, 0x8D9A,	0xB718, 0x8D9B, 0xB719, 0x8D9C, 0xB71A, 0x8D9D, 0xB71B, 0x8D9E,
+	0xB71C, 0x8D9F, 0xB71D, 0x8DA0, 0xB71E, 0x8DA1, 0xB71F, 0x8DA2,	0xB720, 0x8DA3, 0xB721, 0x8DA4, 0xB722, 0x8DA5, 0xB723, 0x8DA6,
+	0xB724, 0x8DA7, 0xB725, 0x8DA8, 0xB726, 0x8DA9, 0xB727, 0x8DAA,	0xB728, 0xB6DF, 0xB729, 0xB6E0, 0xB72A, 0x8DAB, 0xB72B, 0x8DAC,
+	0xB72C, 0xB6E1, 0xB72D, 0x8DAD, 0xB72E, 0x8DAE, 0xB72F, 0xB6E2,	0xB730, 0xB6E3, 0xB731, 0x8DAF, 0xB732, 0x8DB0, 0xB733, 0x8DB1,
+	0xB734, 0x8DB2, 0xB735, 0x8DB3, 0xB736, 0x8DB4, 0xB737, 0x8DB5,	0xB738, 0xB6E4, 0xB739, 0xB6E5, 0xB73A, 0x8DB6, 0xB73B, 0xB6E6,
+	0xB73C, 0x8DB7, 0xB73D, 0x8DB8, 0xB73E, 0x8DB9, 0xB73F, 0x8DBA,	0xB740, 0x8DBB, 0xB741, 0x8DBC, 0xB742, 0x8DBD, 0xB743, 0x8DBE,
+	0xB744, 0xB6E7, 0xB745, 0x8DBF, 0xB746, 0x8DC0, 0xB747, 0x8DC1,	0xB748, 0xB6E8, 0xB749, 0x8DC2, 0xB74A, 0x8DC3, 0xB74B, 0x8DC4,
+	0xB74C, 0xB6E9, 0xB74D, 0x8DC5, 0xB74E, 0x8DC6, 0xB74F, 0x8DC7,	0xB750, 0x8DC8, 0xB751, 0x8DC9, 0xB752, 0x8DCA, 0xB753, 0x8DCB,
+	0xB754, 0xB6EA, 0xB755, 0xB6EB, 0xB756, 0x8DCC, 0xB757, 0x8DCD,	0xB758, 0x8DCE, 0xB759, 0x8DCF, 0xB75A, 0x8DD0, 0xB75B, 0x8DD1,
+	0xB75C, 0x8DD2, 0xB75D, 0x8DD3, 0xB75E, 0x8DD4, 0xB75F, 0x8DD5,	0xB760, 0xB6EC, 0xB761, 0x8DD6, 0xB762, 0x8DD7, 0xB763, 0x8DD8,
+	0xB764, 0xB6ED, 0xB765, 0x8DD9, 0xB766, 0x8DDA, 0xB767, 0x8DDB,	0xB768, 0xB6EE, 0xB769, 0x8DDC, 0xB76A, 0x8DDD, 0xB76B, 0x8DDE,
+	0xB76C, 0x8DDF, 0xB76D, 0x8DE0, 0xB76E, 0x8DE1, 0xB76F, 0x8DE2,	0xB770, 0xB6EF, 0xB771, 0xB6F0, 0xB772, 0x8DE3, 0xB773, 0xB6F1,
+	0xB774, 0x8DE4, 0xB775, 0xB6F2, 0xB776, 0x8DE5, 0xB777, 0x8DE6,	0xB778, 0x8DE7, 0xB779, 0x8DE8, 0xB77A, 0x8DE9, 0xB77B, 0x8DEA,
+	0xB77C, 0xB6F3, 0xB77D, 0xB6F4, 0xB77E, 0x8DEB, 0xB77F, 0x8DEC,	0xB780, 0xB6F5, 0xB781, 0x8DED, 0xB782, 0x8DEE, 0xB783, 0x8DEF,
+	0xB784, 0xB6F6, 0xB785, 0x8DF0, 0xB786, 0x8DF1, 0xB787, 0x8DF2,	0xB788, 0x8DF3, 0xB789, 0x8DF4, 0xB78A, 0x8DF5, 0xB78B, 0x8DF6,
+	0xB78C, 0xB6F7, 0xB78D, 0xB6F8, 0xB78E, 0x8DF7, 0xB78F, 0xB6F9,	0xB790, 0xB6FA, 0xB791, 0xB6FB, 0xB792, 0xB6FC, 0xB793, 0x8DF8,
+	0xB794, 0x8DF9, 0xB795, 0x8DFA, 0xB796, 0xB6FD, 0xB797, 0xB6FE,	0xB798, 0xB7A1, 0xB799, 0xB7A2, 0xB79A, 0x8DFB, 0xB79B, 0x8DFC,
+	0xB79C, 0xB7A3, 0xB79D, 0x8DFD, 0xB79E, 0x8DFE, 0xB79F, 0x8E41,	0xB7A0, 0xB7A4, 0xB7A1, 0x8E42, 0xB7A2, 0x8E43, 0xB7A3, 0x8E44,
+	0xB7A4, 0x8E45, 0xB7A5, 0x8E46, 0xB7A6, 0x8E47, 0xB7A7, 0x8E48,	0xB7A8, 0xB7A5, 0xB7A9, 0xB7A6, 0xB7AA, 0x8E49, 0xB7AB, 0xB7A7,
+	0xB7AC, 0xB7A8, 0xB7AD, 0xB7A9, 0xB7AE, 0x8E4A, 0xB7AF, 0x8E4B,	0xB7B0, 0x8E4C, 0xB7B1, 0x8E4D, 0xB7B2, 0x8E4E, 0xB7B3, 0x8E4F,
+	0xB7B4, 0xB7AA, 0xB7B5, 0xB7AB, 0xB7B6, 0x8E50, 0xB7B7, 0x8E51,	0xB7B8, 0xB7AC, 0xB7B9, 0x8E52, 0xB7BA, 0x8E53, 0xB7BB, 0x8E54,
+	0xB7BC, 0x8E55, 0xB7BD, 0x8E56, 0xB7BE, 0x8E57, 0xB7BF, 0x8E58,	0xB7C0, 0x8E59, 0xB7C1, 0x8E5A, 0xB7C2, 0x8E61, 0xB7C3, 0x8E62,
+	0xB7C4, 0x8E63, 0xB7C5, 0x8E64, 0xB7C6, 0x8E65, 0xB7C7, 0xB7AD,	0xB7C8, 0x8E66, 0xB7C9, 0xB7AE, 0xB7CA, 0x8E67, 0xB7CB, 0x8E68,
+	0xB7CC, 0x8E69, 0xB7CD, 0x8E6A, 0xB7CE, 0x8E6B, 0xB7CF, 0x8E6C,	0xB7D0, 0x8E6D, 0xB7D1, 0x8E6E, 0xB7D2, 0x8E6F, 0xB7D3, 0x8E70,
+	0xB7D4, 0x8E71, 0xB7D5, 0x8E72, 0xB7D6, 0x8E73, 0xB7D7, 0x8E74,	0xB7D8, 0x8E75, 0xB7D9, 0x8E76, 0xB7DA, 0x8E77, 0xB7DB, 0x8E78,
+	0xB7DC, 0x8E79, 0xB7DD, 0x8E7A, 0xB7DE, 0x8E81, 0xB7DF, 0x8E82,	0xB7E0, 0x8E83, 0xB7E1, 0x8E84, 0xB7E2, 0x8E85, 0xB7E3, 0x8E86,
+	0xB7E4, 0x8E87, 0xB7E5, 0x8E88, 0xB7E6, 0x8E89, 0xB7E7, 0x8E8A,	0xB7E8, 0x8E8B, 0xB7E9, 0x8E8C, 0xB7EA, 0x8E8D, 0xB7EB, 0x8E8E,
+	0xB7EC, 0xB7AF, 0xB7ED, 0xB7B0, 0xB7EE, 0x8E8F, 0xB7EF, 0x8E90,	0xB7F0, 0xB7B1, 0xB7F1, 0x8E91, 0xB7F2, 0x8E92, 0xB7F3, 0x8E93,
+	0xB7F4, 0xB7B2, 0xB7F5, 0x8E94, 0xB7F6, 0x8E95, 0xB7F7, 0x8E96,	0xB7F8, 0x8E97, 0xB7F9, 0x8E98, 0xB7FA, 0x8E99, 0xB7FB, 0x8E9A,
+	0xB7FC, 0xB7B3, 0xB7FD, 0xB7B4, 0xB7FE, 0x8E9B, 0xB7FF, 0xB7B5,	0xB800, 0xB7B6, 0xB801, 0xB7B7, 0xB802, 0x8E9C, 0xB803, 0x8E9D,
+	0xB804, 0x8E9E, 0xB805, 0x8E9F, 0xB806, 0x8EA0, 0xB807, 0xB7B8,	0xB808, 0xB7B9, 0xB809, 0xB7BA, 0xB80A, 0x8EA1, 0xB80B, 0x8EA2,
+	0xB80C, 0xB7BB, 0xB80D, 0x8EA3, 0xB80E, 0x8EA4, 0xB80F, 0x8EA5,	0xB810, 0xB7BC, 0xB811, 0x8EA6, 0xB812, 0x8EA7, 0xB813, 0x8EA8,
+	0xB814, 0x8EA9, 0xB815, 0x8EAA, 0xB816, 0x8EAB, 0xB817, 0x8EAC,	0xB818, 0xB7BD, 0xB819, 0xB7BE, 0xB81A, 0x8EAD, 0xB81B, 0xB7BF,
+	0xB81C, 0x8EAE, 0xB81D, 0xB7C0, 0xB81E, 0x8EAF, 0xB81F, 0x8EB0,	0xB820, 0x8EB1, 0xB821, 0x8EB2, 0xB822, 0x8EB3, 0xB823, 0x8EB4,
+	0xB824, 0xB7C1, 0xB825, 0xB7C2, 0xB826, 0x8EB5, 0xB827, 0x8EB6,	0xB828, 0xB7C3, 0xB829, 0x8EB7, 0xB82A, 0x8EB8, 0xB82B, 0x8EB9,
+	0xB82C, 0xB7C4, 0xB82D, 0x8EBA, 0xB82E, 0x8EBB, 0xB82F, 0x8EBC,	0xB830, 0x8EBD, 0xB831, 0x8EBE, 0xB832, 0x8EBF, 0xB833, 0x8EC0,
+	0xB834, 0xB7C5, 0xB835, 0xB7C6, 0xB836, 0x8EC1, 0xB837, 0xB7C7,	0xB838, 0xB7C8, 0xB839, 0xB7C9, 0xB83A, 0x8EC2, 0xB83B, 0x8EC3,
+	0xB83C, 0x8EC4, 0xB83D, 0x8EC5, 0xB83E, 0x8EC6, 0xB83F, 0x8EC7,	0xB840, 0xB7CA, 0xB841, 0x8EC8, 0xB842, 0x8EC9, 0xB843, 0x8ECA,
+	0xB844, 0xB7CB, 0xB845, 0x8ECB, 0xB846, 0x8ECC, 0xB847, 0x8ECD,	0xB848, 0x8ECE, 0xB849, 0x8ECF, 0xB84A, 0x8ED0, 0xB84B, 0x8ED1,
+	0xB84C, 0x8ED2, 0xB84D, 0x8ED3, 0xB84E, 0x8ED4, 0xB84F, 0x8ED5,	0xB850, 0x8ED6, 0xB851, 0xB7CC, 0xB852, 0x8ED7, 0xB853, 0xB7CD,
+	0xB854, 0x8ED8, 0xB855, 0x8ED9, 0xB856, 0x8EDA, 0xB857, 0x8EDB,	0xB858, 0x8EDC, 0xB859, 0x8EDD, 0xB85A, 0x8EDE, 0xB85B, 0x8EDF,
+	0xB85C, 0xB7CE, 0xB85D, 0xB7CF, 0xB85E, 0x8EE0, 0xB85F, 0x8EE1,	0xB860, 0xB7D0, 0xB861, 0x8EE2, 0xB862, 0x8EE3, 0xB863, 0x8EE4,
+	0xB864, 0xB7D1, 0xB865, 0x8EE5, 0xB866, 0x8EE6, 0xB867, 0x8EE7,	0xB868, 0x8EE8, 0xB869, 0x8EE9, 0xB86A, 0x8EEA, 0xB86B, 0x8EEB,
+	0xB86C, 0xB7D2, 0xB86D, 0xB7D3, 0xB86E, 0x8EEC, 0xB86F, 0xB7D4,	0xB870, 0x8EED, 0xB871, 0xB7D5, 0xB872, 0x8EEE, 0xB873, 0x8EEF,
+	0xB874, 0x8EF0, 0xB875, 0x8EF1, 0xB876, 0x8EF2, 0xB877, 0x8EF3,	0xB878, 0xB7D6, 0xB879, 0x8EF4, 0xB87A, 0x8EF5, 0xB87B, 0x8EF6,
+	0xB87C, 0xB7D7, 0xB87D, 0x8EF7, 0xB87E, 0x8EF8, 0xB87F, 0x8EF9,	0xB880, 0x8EFA, 0xB881, 0x8EFB, 0xB882, 0x8EFC, 0xB883, 0x8EFD,
+	0xB884, 0x8EFE, 0xB885, 0x8F41, 0xB886, 0x8F42, 0xB887, 0x8F43,	0xB888, 0x8F44, 0xB889, 0x8F45, 0xB88A, 0x8F46, 0xB88B, 0x8F47,
+	0xB88C, 0x8F48, 0xB88D, 0xB7D8, 0xB88E, 0x8F49, 0xB88F, 0x8F4A,	0xB890, 0x8F4B, 0xB891, 0x8F4C, 0xB892, 0x8F4D, 0xB893, 0x8F4E,
+	0xB894, 0x8F4F, 0xB895, 0x8F50, 0xB896, 0x8F51, 0xB897, 0x8F52,	0xB898, 0x8F53, 0xB899, 0x8F54, 0xB89A, 0x8F55, 0xB89B, 0x8F56,
+	0xB89C, 0x8F57, 0xB89D, 0x8F58, 0xB89E, 0x8F59, 0xB89F, 0x8F5A,	0xB8A0, 0x8F61, 0xB8A1, 0x8F62, 0xB8A2, 0x8F63, 0xB8A3, 0x8F64,
+	0xB8A4, 0x8F65, 0xB8A5, 0x8F66, 0xB8A6, 0x8F67, 0xB8A7, 0x8F68,	0xB8A8, 0xB7D9, 0xB8A9, 0x8F69, 0xB8AA, 0x8F6A, 0xB8AB, 0x8F6B,
+	0xB8AC, 0x8F6C, 0xB8AD, 0x8F6D, 0xB8AE, 0x8F6E, 0xB8AF, 0x8F6F,	0xB8B0, 0xB7DA, 0xB8B1, 0x8F70, 0xB8B2, 0x8F71, 0xB8B3, 0x8F72,
+	0xB8B4, 0xB7DB, 0xB8B5, 0x8F73, 0xB8B6, 0x8F74, 0xB8B7, 0x8F75,	0xB8B8, 0xB7DC, 0xB8B9, 0x8F76, 0xB8BA, 0x8F77, 0xB8BB, 0x8F78,
+	0xB8BC, 0x8F79, 0xB8BD, 0x8F7A, 0xB8BE, 0x8F81, 0xB8BF, 0x8F82,	0xB8C0, 0xB7DD, 0xB8C1, 0xB7DE, 0xB8C2, 0x8F83, 0xB8C3, 0xB7DF,
+	0xB8C4, 0x8F84, 0xB8C5, 0xB7E0, 0xB8C6, 0x8F85, 0xB8C7, 0x8F86,	0xB8C8, 0x8F87, 0xB8C9, 0x8F88, 0xB8CA, 0x8F89, 0xB8CB, 0x8F8A,
+	0xB8CC, 0xB7E1, 0xB8CD, 0x8F8B, 0xB8CE, 0x8F8C, 0xB8CF, 0x8F8D,	0xB8D0, 0xB7E2, 0xB8D1, 0x8F8E, 0xB8D2, 0x8F8F, 0xB8D3, 0x8F90,
+	0xB8D4, 0xB7E3, 0xB8D5, 0x8F91, 0xB8D6, 0x8F92, 0xB8D7, 0x8F93,	0xB8D8, 0x8F94, 0xB8D9, 0x8F95, 0xB8DA, 0x8F96, 0xB8DB, 0x8F97,
+	0xB8DC, 0x8F98, 0xB8DD, 0xB7E4, 0xB8DE, 0x8F99, 0xB8DF, 0xB7E5,	0xB8E0, 0x8F9A, 0xB8E1, 0xB7E6, 0xB8E2, 0x8F9B, 0xB8E3, 0x8F9C,
+	0xB8E4, 0x8F9D, 0xB8E5, 0x8F9E, 0xB8E6, 0x8F9F, 0xB8E7, 0x8FA0,	0xB8E8, 0xB7E7, 0xB8E9, 0xB7E8, 0xB8EA, 0x8FA1, 0xB8EB, 0x8FA2,
+	0xB8EC, 0xB7E9, 0xB8ED, 0x8FA3, 0xB8EE, 0x8FA4, 0xB8EF, 0x8FA5,	0xB8F0, 0xB7EA, 0xB8F1, 0x8FA6, 0xB8F2, 0x8FA7, 0xB8F3, 0x8FA8,
+	0xB8F4, 0x8FA9, 0xB8F5, 0x8FAA, 0xB8F6, 0x8FAB, 0xB8F7, 0x8FAC,	0xB8F8, 0xB7EB, 0xB8F9, 0xB7EC, 0xB8FA, 0x8FAD, 0xB8FB, 0xB7ED,
+	0xB8FC, 0x8FAE, 0xB8FD, 0xB7EE, 0xB8FE, 0x8FAF, 0xB8FF, 0x8FB0,	0xB900, 0x8FB1, 0xB901, 0x8FB2, 0xB902, 0x8FB3, 0xB903, 0x8FB4,
+	0xB904, 0xB7EF, 0xB905, 0x8FB5, 0xB906, 0x8FB6, 0xB907, 0x8FB7,	0xB908, 0x8FB8, 0xB909, 0x8FB9, 0xB90A, 0x8FBA, 0xB90B, 0x8FBB,
+	0xB90C, 0x8FBC, 0xB90D, 0x8FBD, 0xB90E, 0x8FBE, 0xB90F, 0x8FBF,	0xB910, 0x8FC0, 0xB911, 0x8FC1, 0xB912, 0x8FC2, 0xB913, 0x8FC3,
+	0xB914, 0x8FC4, 0xB915, 0x8FC5, 0xB916, 0x8FC6, 0xB917, 0x8FC7,	0xB918, 0xB7F0, 0xB919, 0x8FC8, 0xB91A, 0x8FC9, 0xB91B, 0x8FCA,
+	0xB91C, 0x8FCB, 0xB91D, 0x8FCC, 0xB91E, 0x8FCD, 0xB91F, 0x8FCE,	0xB920, 0xB7F1, 0xB921, 0x8FCF, 0xB922, 0x8FD0, 0xB923, 0x8FD1,
+	0xB924, 0x8FD2, 0xB925, 0x8FD3, 0xB926, 0x8FD4, 0xB927, 0x8FD5,	0xB928, 0x8FD6, 0xB929, 0x8FD7, 0xB92A, 0x8FD8, 0xB92B, 0x8FD9,
+	0xB92C, 0x8FDA, 0xB92D, 0x8FDB, 0xB92E, 0x8FDC, 0xB92F, 0x8FDD,	0xB930, 0x8FDE, 0xB931, 0x8FDF, 0xB932, 0x8FE0, 0xB933, 0x8FE1,
+	0xB934, 0x8FE2, 0xB935, 0x8FE3, 0xB936, 0x8FE4, 0xB937, 0x8FE5,	0xB938, 0x8FE6, 0xB939, 0x8FE7, 0xB93A, 0x8FE8, 0xB93B, 0x8FE9,
+	0xB93C, 0xB7F2, 0xB93D, 0xB7F3, 0xB93E, 0x8FEA, 0xB93F, 0x8FEB,	0xB940, 0xB7F4, 0xB941, 0x8FEC, 0xB942, 0x8FED, 0xB943, 0x8FEE,
+	0xB944, 0xB7F5, 0xB945, 0x8FEF, 0xB946, 0x8FF0, 0xB947, 0x8FF1,	0xB948, 0x8FF2, 0xB949, 0x8FF3, 0xB94A, 0x8FF4, 0xB94B, 0x8FF5,
+	0xB94C, 0xB7F6, 0xB94D, 0x8FF6, 0xB94E, 0x8FF7, 0xB94F, 0xB7F7,	0xB950, 0x8FF8, 0xB951, 0xB7F8, 0xB952, 0x8FF9, 0xB953, 0x8FFA,
+	0xB954, 0x8FFB, 0xB955, 0x8FFC, 0xB956, 0x8FFD, 0xB957, 0x8FFE,	0xB958, 0xB7F9, 0xB959, 0xB7FA, 0xB95A, 0x9041, 0xB95B, 0x9042,
+	0xB95C, 0xB7FB, 0xB95D, 0x9043, 0xB95E, 0x9044, 0xB95F, 0x9045,	0xB960, 0xB7FC, 0xB961, 0x9046, 0xB962, 0x9047, 0xB963, 0x9048,
+	0xB964, 0x9049, 0xB965, 0x904A, 0xB966, 0x904B, 0xB967, 0x904C,	0xB968, 0xB7FD, 0xB969, 0xB7FE, 0xB96A, 0x904D, 0xB96B, 0xB8A1,
+	0xB96C, 0x904E, 0xB96D, 0xB8A2, 0xB96E, 0x904F, 0xB96F, 0x9050,	0xB970, 0x9051, 0xB971, 0x9052, 0xB972, 0x9053, 0xB973, 0x9054,
+	0xB974, 0xB8A3, 0xB975, 0xB8A4, 0xB976, 0x9055, 0xB977, 0x9056,	0xB978, 0xB8A5, 0xB979, 0x9057, 0xB97A, 0x9058, 0xB97B, 0x9059,
+	0xB97C, 0xB8A6, 0xB97D, 0x905A, 0xB97E, 0x9061, 0xB97F, 0x9062,	0xB980, 0x9063, 0xB981, 0x9064, 0xB982, 0x9065, 0xB983, 0x9066,
+	0xB984, 0xB8A7, 0xB985, 0xB8A8, 0xB986, 0x9067, 0xB987, 0xB8A9,	0xB988, 0x9068, 0xB989, 0xB8AA, 0xB98A, 0xB8AB, 0xB98B, 0x9069,
+	0xB98C, 0x906A, 0xB98D, 0xB8AC, 0xB98E, 0xB8AD, 0xB98F, 0x906B,	0xB990, 0x906C, 0xB991, 0x906D, 0xB992, 0x906E, 0xB993, 0x906F,
+	0xB994, 0x9070, 0xB995, 0x9071, 0xB996, 0x9072, 0xB997, 0x9073,	0xB998, 0x9074, 0xB999, 0x9075, 0xB99A, 0x9076, 0xB99B, 0x9077,
+	0xB99C, 0x9078, 0xB99D, 0x9079, 0xB99E, 0x907A, 0xB99F, 0x9081,	0xB9A0, 0x9082, 0xB9A1, 0x9083, 0xB9A2, 0x9084, 0xB9A3, 0x9085,
+	0xB9A4, 0x9086, 0xB9A5, 0x9087, 0xB9A6, 0x9088, 0xB9A7, 0x9089,	0xB9A8, 0x908A, 0xB9A9, 0x908B, 0xB9AA, 0x908C, 0xB9AB, 0x908D,
+	0xB9AC, 0xB8AE, 0xB9AD, 0xB8AF, 0xB9AE, 0x908E, 0xB9AF, 0x908F,	0xB9B0, 0xB8B0, 0xB9B1, 0x9090, 0xB9B2, 0x9091, 0xB9B3, 0x9092,
+	0xB9B4, 0xB8B1, 0xB9B5, 0x9093, 0xB9B6, 0x9094, 0xB9B7, 0x9095,	0xB9B8, 0x9096, 0xB9B9, 0x9097, 0xB9BA, 0x9098, 0xB9BB, 0x9099,
+	0xB9BC, 0xB8B2, 0xB9BD, 0xB8B3, 0xB9BE, 0x909A, 0xB9BF, 0xB8B4,	0xB9C0, 0x909B, 0xB9C1, 0xB8B5, 0xB9C2, 0x909C, 0xB9C3, 0x909D,
+	0xB9C4, 0x909E, 0xB9C5, 0x909F, 0xB9C6, 0x90A0, 0xB9C7, 0x90A1,	0xB9C8, 0xB8B6, 0xB9C9, 0xB8B7, 0xB9CA, 0x90A2, 0xB9CB, 0x90A3,
+	0xB9CC, 0xB8B8, 0xB9CD, 0x90A4, 0xB9CE, 0xB8B9, 0xB9CF, 0xB8BA,	0xB9D0, 0xB8BB, 0xB9D1, 0xB8BC, 0xB9D2, 0xB8BD, 0xB9D3, 0x90A5,
+	0xB9D4, 0x90A6, 0xB9D5, 0x90A7, 0xB9D6, 0x90A8, 0xB9D7, 0x90A9,	0xB9D8, 0xB8BE, 0xB9D9, 0xB8BF, 0xB9DA, 0x90AA, 0xB9DB, 0xB8C0,
+	0xB9DC, 0x90AB, 0xB9DD, 0xB8C1, 0xB9DE, 0xB8C2, 0xB9DF, 0x90AC,	0xB9E0, 0x90AD, 0xB9E1, 0xB8C3, 0xB9E2, 0x90AE, 0xB9E3, 0xB8C4,
+	0xB9E4, 0xB8C5, 0xB9E5, 0xB8C6, 0xB9E6, 0x90AF, 0xB9E7, 0x90B0,	0xB9E8, 0xB8C7, 0xB9E9, 0x90B1, 0xB9EA, 0x90B2, 0xB9EB, 0x90B3,
+	0xB9EC, 0xB8C8, 0xB9ED, 0x90B4, 0xB9EE, 0x90B5, 0xB9EF, 0x90B6,	0xB9F0, 0x90B7, 0xB9F1, 0x90B8, 0xB9F2, 0x90B9, 0xB9F3, 0x90BA,
+	0xB9F4, 0xB8C9, 0xB9F5, 0xB8CA, 0xB9F6, 0x90BB, 0xB9F7, 0xB8CB,	0xB9F8, 0xB8CC, 0xB9F9, 0xB8CD, 0xB9FA, 0xB8CE, 0xB9FB, 0x90BC,
+	0xB9FC, 0x90BD, 0xB9FD, 0x90BE, 0xB9FE, 0x90BF, 0xB9FF, 0x90C0,	0xBA00, 0xB8CF, 0xBA01, 0xB8D0, 0xBA02, 0x90C1, 0xBA03, 0x90C2,
+	0xBA04, 0x90C3, 0xBA05, 0x90C4, 0xBA06, 0x90C5, 0xBA07, 0x90C6,	0xBA08, 0xB8D1, 0xBA09, 0x90C7, 0xBA0A, 0x90C8, 0xBA0B, 0x90C9,
+	0xBA0C, 0x90CA, 0xBA0D, 0x90CB, 0xBA0E, 0x90CC, 0xBA0F, 0x90CD,	0xBA10, 0x90CE, 0xBA11, 0x90CF, 0xBA12, 0x90D0, 0xBA13, 0x90D1,
+	0xBA14, 0x90D2, 0xBA15, 0xB8D2, 0xBA16, 0x90D3, 0xBA17, 0x90D4,	0xBA18, 0x90D5, 0xBA19, 0x90D6, 0xBA1A, 0x90D7, 0xBA1B, 0x90D8,
+	0xBA1C, 0x90D9, 0xBA1D, 0x90DA, 0xBA1E, 0x90DB, 0xBA1F, 0x90DC,	0xBA20, 0x90DD, 0xBA21, 0x90DE, 0xBA22, 0x90DF, 0xBA23, 0x90E0,
+	0xBA24, 0x90E1, 0xBA25, 0x90E2, 0xBA26, 0x90E3, 0xBA27, 0x90E4,	0xBA28, 0x90E5, 0xBA29, 0x90E6, 0xBA2A, 0x90E7, 0xBA2B, 0x90E8,
+	0xBA2C, 0x90E9, 0xBA2D, 0x90EA, 0xBA2E, 0x90EB, 0xBA2F, 0x90EC,	0xBA30, 0x90ED, 0xBA31, 0x90EE, 0xBA32, 0x90EF, 0xBA33, 0x90F0,
+	0xBA34, 0x90F1, 0xBA35, 0x90F2, 0xBA36, 0x90F3, 0xBA37, 0x90F4,	0xBA38, 0xB8D3, 0xBA39, 0xB8D4, 0xBA3A, 0x90F5, 0xBA3B, 0x90F6,
+	0xBA3C, 0xB8D5, 0xBA3D, 0x90F7, 0xBA3E, 0x90F8, 0xBA3F, 0x90F9,	0xBA40, 0xB8D6, 0xBA41, 0x90FA, 0xBA42, 0xB8D7, 0xBA43, 0x90FB,
+	0xBA44, 0x90FC, 0xBA45, 0x90FD, 0xBA46, 0x90FE, 0xBA47, 0x9141,	0xBA48, 0xB8D8, 0xBA49, 0xB8D9, 0xBA4A, 0x9142, 0xBA4B, 0xB8DA,
+	0xBA4C, 0x9143, 0xBA4D, 0xB8DB, 0xBA4E, 0xB8DC, 0xBA4F, 0x9144,	0xBA50, 0x9145, 0xBA51, 0x9146, 0xBA52, 0x9147, 0xBA53, 0xB8DD,
+	0xBA54, 0xB8DE, 0xBA55, 0xB8DF, 0xBA56, 0x9148, 0xBA57, 0x9149,	0xBA58, 0xB8E0, 0xBA59, 0x914A, 0xBA5A, 0x914B, 0xBA5B, 0x914C,
+	0xBA5C, 0xB8E1, 0xBA5D, 0x914D, 0xBA5E, 0x914E, 0xBA5F, 0x914F,	0xBA60, 0x9150, 0xBA61, 0x9151, 0xBA62, 0x9152, 0xBA63, 0x9153,
+	0xBA64, 0xB8E2, 0xBA65, 0xB8E3, 0xBA66, 0x9154, 0xBA67, 0xB8E4,	0xBA68, 0xB8E5, 0xBA69, 0xB8E6, 0xBA6A, 0x9155, 0xBA6B, 0x9156,
+	0xBA6C, 0x9157, 0xBA6D, 0x9158, 0xBA6E, 0x9159, 0xBA6F, 0x915A,	0xBA70, 0xB8E7, 0xBA71, 0xB8E8, 0xBA72, 0x9161, 0xBA73, 0x9162,
+	0xBA74, 0xB8E9, 0xBA75, 0x9163, 0xBA76, 0x9164, 0xBA77, 0x9165,	0xBA78, 0xB8EA, 0xBA79, 0x9166, 0xBA7A, 0x9167, 0xBA7B, 0x9168,
+	0xBA7C, 0x9169, 0xBA7D, 0x916A, 0xBA7E, 0x916B, 0xBA7F, 0x916C,	0xBA80, 0x916D, 0xBA81, 0x916E, 0xBA82, 0x916F, 0xBA83, 0xB8EB,
+	0xBA84, 0xB8EC, 0xBA85, 0xB8ED, 0xBA86, 0x9170, 0xBA87, 0xB8EE,	0xBA88, 0x9171, 0xBA89, 0x9172, 0xBA8A, 0x9173, 0xBA8B, 0x9174,
+	0xBA8C, 0xB8EF, 0xBA8D, 0x9175, 0xBA8E, 0x9176, 0xBA8F, 0x9177,	0xBA90, 0x9178, 0xBA91, 0x9179, 0xBA92, 0x917A, 0xBA93, 0x9181,
+	0xBA94, 0x9182, 0xBA95, 0x9183, 0xBA96, 0x9184, 0xBA97, 0x9185,	0xBA98, 0x9186, 0xBA99, 0x9187, 0xBA9A, 0x9188, 0xBA9B, 0x9189,
+	0xBA9C, 0x918A, 0xBA9D, 0x918B, 0xBA9E, 0x918C, 0xBA9F, 0x918D,	0xBAA0, 0x918E, 0xBAA1, 0x918F, 0xBAA2, 0x9190, 0xBAA3, 0x9191,
+	0xBAA4, 0x9192, 0xBAA5, 0x9193, 0xBAA6, 0x9194, 0xBAA7, 0x9195,	0xBAA8, 0xB8F0, 0xBAA9, 0xB8F1, 0xBAAA, 0x9196, 0xBAAB, 0xB8F2,
+	0xBAAC, 0xB8F3, 0xBAAD, 0x9197, 0xBAAE, 0x9198, 0xBAAF, 0x9199,	0xBAB0, 0xB8F4, 0xBAB1, 0x919A, 0xBAB2, 0xB8F5, 0xBAB3, 0x919B,
+	0xBAB4, 0x919C, 0xBAB5, 0x919D, 0xBAB6, 0x919E, 0xBAB7, 0x919F,	0xBAB8, 0xB8F6, 0xBAB9, 0xB8F7, 0xBABA, 0x91A0, 0xBABB, 0xB8F8,
+	0xBABC, 0x91A1, 0xBABD, 0xB8F9, 0xBABE, 0x91A2, 0xBABF, 0x91A3,	0xBAC0, 0x91A4, 0xBAC1, 0x91A5, 0xBAC2, 0x91A6, 0xBAC3, 0x91A7,
+	0xBAC4, 0xB8FA, 0xBAC5, 0x91A8, 0xBAC6, 0x91A9, 0xBAC7, 0x91AA,	0xBAC8, 0xB8FB, 0xBAC9, 0x91AB, 0xBACA, 0x91AC, 0xBACB, 0x91AD,
+	0xBACC, 0x91AE, 0xBACD, 0x91AF, 0xBACE, 0x91B0, 0xBACF, 0x91B1,	0xBAD0, 0x91B2, 0xBAD1, 0x91B3, 0xBAD2, 0x91B4, 0xBAD3, 0x91B5,
+	0xBAD4, 0x91B6, 0xBAD5, 0x91B7, 0xBAD6, 0x91B8, 0xBAD7, 0x91B9,	0xBAD8, 0xB8FC, 0xBAD9, 0xB8FD, 0xBADA, 0x91BA, 0xBADB, 0x91BB,
+	0xBADC, 0x91BC, 0xBADD, 0x91BD, 0xBADE, 0x91BE, 0xBADF, 0x91BF,	0xBAE0, 0x91C0, 0xBAE1, 0x91C1, 0xBAE2, 0x91C2, 0xBAE3, 0x91C3,
+	0xBAE4, 0x91C4, 0xBAE5, 0x91C5, 0xBAE6, 0x91C6, 0xBAE7, 0x91C7,	0xBAE8, 0x91C8, 0xBAE9, 0x91C9, 0xBAEA, 0x91CA, 0xBAEB, 0x91CB,
+	0xBAEC, 0x91CC, 0xBAED, 0x91CD, 0xBAEE, 0x91CE, 0xBAEF, 0x91CF,	0xBAF0, 0x91D0, 0xBAF1, 0x91D1, 0xBAF2, 0x91D2, 0xBAF3, 0x91D3,
+	0xBAF4, 0x91D4, 0xBAF5, 0x91D5, 0xBAF6, 0x91D6, 0xBAF7, 0x91D7,	0xBAF8, 0x91D8, 0xBAF9, 0x91D9, 0xBAFA, 0x91DA, 0xBAFB, 0x91DB,
+	0xBAFC, 0xB8FE, 0xBAFD, 0x91DC, 0xBAFE, 0x91DD, 0xBAFF, 0x91DE,	0xBB00, 0xB9A1, 0xBB01, 0x91DF, 0xBB02, 0x91E0, 0xBB03, 0x91E1,
+	0xBB04, 0xB9A2, 0xBB05, 0x91E2, 0xBB06, 0x91E3, 0xBB07, 0x91E4,	0xBB08, 0x91E5, 0xBB09, 0x91E6, 0xBB0A, 0x91E7, 0xBB0B, 0x91E8,
+	0xBB0C, 0x91E9, 0xBB0D, 0xB9A3, 0xBB0E, 0x91EA, 0xBB0F, 0xB9A4,	0xBB10, 0x91EB, 0xBB11, 0xB9A5, 0xBB12, 0x91EC, 0xBB13, 0x91ED,
+	0xBB14, 0x91EE, 0xBB15, 0x91EF, 0xBB16, 0x91F0, 0xBB17, 0x91F1,	0xBB18, 0xB9A6, 0xBB19, 0x91F2, 0xBB1A, 0x91F3, 0xBB1B, 0x91F4,
+	0xBB1C, 0xB9A7, 0xBB1D, 0x91F5, 0xBB1E, 0x91F6, 0xBB1F, 0x91F7,	0xBB20, 0xB9A8, 0xBB21, 0x91F8, 0xBB22, 0x91F9, 0xBB23, 0x91FA,
+	0xBB24, 0x91FB, 0xBB25, 0x91FC, 0xBB26, 0x91FD, 0xBB27, 0x91FE,	0xBB28, 0x9241, 0xBB29, 0xB9A9, 0xBB2A, 0x9242, 0xBB2B, 0xB9AA,
+	0xBB2C, 0x9243, 0xBB2D, 0x9244, 0xBB2E, 0x9245, 0xBB2F, 0x9246,	0xBB30, 0x9247, 0xBB31, 0x9248, 0xBB32, 0x9249, 0xBB33, 0x924A,
+	0xBB34, 0xB9AB, 0xBB35, 0xB9AC, 0xBB36, 0xB9AD, 0xBB37, 0x924B,	0xBB38, 0xB9AE, 0xBB39, 0x924C, 0xBB3A, 0x924D, 0xBB3B, 0xB9AF,
+	0xBB3C, 0xB9B0, 0xBB3D, 0xB9B1, 0xBB3E, 0xB9B2, 0xBB3F, 0x924E,	0xBB40, 0x924F, 0xBB41, 0x9250, 0xBB42, 0x9251, 0xBB43, 0x9252,
+	0xBB44, 0xB9B3, 0xBB45, 0xB9B4, 0xBB46, 0x9253, 0xBB47, 0xB9B5,	0xBB48, 0x9254, 0xBB49, 0xB9B6, 0xBB4A, 0x9255, 0xBB4B, 0x9256,
+	0xBB4C, 0x9257, 0xBB4D, 0xB9B7, 0xBB4E, 0x9258, 0xBB4F, 0xB9B8,	0xBB50, 0xB9B9, 0xBB51, 0x9259, 0xBB52, 0x925A, 0xBB53, 0x9261,
+	0xBB54, 0xB9BA, 0xBB55, 0x9262, 0xBB56, 0x9263, 0xBB57, 0x9264,	0xBB58, 0xB9BB, 0xBB59, 0x9265, 0xBB5A, 0x9266, 0xBB5B, 0x9267,
+	0xBB5C, 0x9268, 0xBB5D, 0x9269, 0xBB5E, 0x926A, 0xBB5F, 0x926B,	0xBB60, 0x926C, 0xBB61, 0xB9BC, 0xBB62, 0x926D, 0xBB63, 0xB9BD,
+	0xBB64, 0x926E, 0xBB65, 0x926F, 0xBB66, 0x9270, 0xBB67, 0x9271,	0xBB68, 0x9272, 0xBB69, 0x9273, 0xBB6A, 0x9274, 0xBB6B, 0x9275,
+	0xBB6C, 0xB9BE, 0xBB6D, 0x9276, 0xBB6E, 0x9277, 0xBB6F, 0x9278,	0xBB70, 0x9279, 0xBB71, 0x927A, 0xBB72, 0x9281, 0xBB73, 0x9282,
+	0xBB74, 0x9283, 0xBB75, 0x9284, 0xBB76, 0x9285, 0xBB77, 0x9286,	0xBB78, 0x9287, 0xBB79, 0x9288, 0xBB7A, 0x9289, 0xBB7B, 0x928A,
+	0xBB7C, 0x928B, 0xBB7D, 0x928C, 0xBB7E, 0x928D, 0xBB7F, 0x928E,	0xBB80, 0x928F, 0xBB81, 0x9290, 0xBB82, 0x9291, 0xBB83, 0x9292,
+	0xBB84, 0x9293, 0xBB85, 0x9294, 0xBB86, 0x9295, 0xBB87, 0x9296,	0xBB88, 0xB9BF, 0xBB89, 0x9297, 0xBB8A, 0x9298, 0xBB8B, 0x9299,
+	0xBB8C, 0xB9C0, 0xBB8D, 0x929A, 0xBB8E, 0x929B, 0xBB8F, 0x929C,	0xBB90, 0xB9C1, 0xBB91, 0x929D, 0xBB92, 0x929E, 0xBB93, 0x929F,
+	0xBB94, 0x92A0, 0xBB95, 0x92A1, 0xBB96, 0x92A2, 0xBB97, 0x92A3,	0xBB98, 0x92A4, 0xBB99, 0x92A5, 0xBB9A, 0x92A6, 0xBB9B, 0x92A7,
+	0xBB9C, 0x92A8, 0xBB9D, 0x92A9, 0xBB9E, 0x92AA, 0xBB9F, 0x92AB,	0xBBA0, 0x92AC, 0xBBA1, 0x92AD, 0xBBA2, 0x92AE, 0xBBA3, 0x92AF,
+	0xBBA4, 0xB9C2, 0xBBA5, 0x92B0, 0xBBA6, 0x92B1, 0xBBA7, 0x92B2,	0xBBA8, 0xB9C3, 0xBBA9, 0x92B3, 0xBBAA, 0x92B4, 0xBBAB, 0x92B5,
+	0xBBAC, 0xB9C4, 0xBBAD, 0x92B6, 0xBBAE, 0x92B7, 0xBBAF, 0x92B8,	0xBBB0, 0x92B9, 0xBBB1, 0x92BA, 0xBBB2, 0x92BB, 0xBBB3, 0x92BC,
+	0xBBB4, 0xB9C5, 0xBBB5, 0x92BD, 0xBBB6, 0x92BE, 0xBBB7, 0xB9C6,	0xBBB8, 0x92BF, 0xBBB9, 0x92C0, 0xBBBA, 0x92C1, 0xBBBB, 0x92C2,
+	0xBBBC, 0x92C3, 0xBBBD, 0x92C4, 0xBBBE, 0x92C5, 0xBBBF, 0x92C6,	0xBBC0, 0xB9C7, 0xBBC1, 0x92C7, 0xBBC2, 0x92C8, 0xBBC3, 0x92C9,
+	0xBBC4, 0xB9C8, 0xBBC5, 0x92CA, 0xBBC6, 0x92CB, 0xBBC7, 0x92CC,	0xBBC8, 0xB9C9, 0xBBC9, 0x92CD, 0xBBCA, 0x92CE, 0xBBCB, 0x92CF,
+	0xBBCC, 0x92D0, 0xBBCD, 0x92D1, 0xBBCE, 0x92D2, 0xBBCF, 0x92D3,	0xBBD0, 0xB9CA, 0xBBD1, 0x92D4, 0xBBD2, 0x92D5, 0xBBD3, 0xB9CB,
+	0xBBD4, 0x92D6, 0xBBD5, 0x92D7, 0xBBD6, 0x92D8, 0xBBD7, 0x92D9,	0xBBD8, 0x92DA, 0xBBD9, 0x92DB, 0xBBDA, 0x92DC, 0xBBDB, 0x92DD,
+	0xBBDC, 0x92DE, 0xBBDD, 0x92DF, 0xBBDE, 0x92E0, 0xBBDF, 0x92E1,	0xBBE0, 0x92E2, 0xBBE1, 0x92E3, 0xBBE2, 0x92E4, 0xBBE3, 0x92E5,
+	0xBBE4, 0x92E6, 0xBBE5, 0x92E7, 0xBBE6, 0x92E8, 0xBBE7, 0x92E9,	0xBBE8, 0x92EA, 0xBBE9, 0x92EB, 0xBBEA, 0x92EC, 0xBBEB, 0x92ED,
+	0xBBEC, 0x92EE, 0xBBED, 0x92EF, 0xBBEE, 0x92F0, 0xBBEF, 0x92F1,	0xBBF0, 0x92F2, 0xBBF1, 0x92F3, 0xBBF2, 0x92F4, 0xBBF3, 0x92F5,
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+	0xBE9C, 0x95E4, 0xBE9D, 0x95E5, 0xBE9E, 0x95E6, 0xBE9F, 0x95E7,	0xBEA0, 0x95E8, 0xBEA1, 0x95E9, 0xBEA2, 0x95EA, 0xBEA3, 0x95EB,
+	0xBEA4, 0x95EC, 0xBEA5, 0x95ED, 0xBEA6, 0x95EE, 0xBEA7, 0x95EF,	0xBEA8, 0xBBB4, 0xBEA9, 0x95F0, 0xBEAA, 0x95F1, 0xBEAB, 0x95F2,
+	0xBEAC, 0x95F3, 0xBEAD, 0x95F4, 0xBEAE, 0x95F5, 0xBEAF, 0x95F6,	0xBEB0, 0x95F7, 0xBEB1, 0x95F8, 0xBEB2, 0x95F9, 0xBEB3, 0x95FA,
+	0xBEB4, 0x95FB, 0xBEB5, 0x95FC, 0xBEB6, 0x95FD, 0xBEB7, 0x95FE,	0xBEB8, 0x9641, 0xBEB9, 0x9642, 0xBEBA, 0x9643, 0xBEBB, 0x9644,
+	0xBEBC, 0x9645, 0xBEBD, 0x9646, 0xBEBE, 0x9647, 0xBEBF, 0x9648,	0xBEC0, 0x9649, 0xBEC1, 0x964A, 0xBEC2, 0x964B, 0xBEC3, 0x964C,
+	0xBEC4, 0x964D, 0xBEC5, 0x964E, 0xBEC6, 0x964F, 0xBEC7, 0x9650,	0xBEC8, 0x9651, 0xBEC9, 0x9652, 0xBECA, 0x9653, 0xBECB, 0x9654,
+	0xBECC, 0x9655, 0xBECD, 0x9656, 0xBECE, 0x9657, 0xBECF, 0x9658,	0xBED0, 0xBBB5, 0xBED1, 0xBBB6, 0xBED2, 0x9659, 0xBED3, 0x965A,
+	0xBED4, 0xBBB7, 0xBED5, 0x9661, 0xBED6, 0x9662, 0xBED7, 0xBBB8,	0xBED8, 0xBBB9, 0xBED9, 0x9663, 0xBEDA, 0x9664, 0xBEDB, 0x9665,
+	0xBEDC, 0x9666, 0xBEDD, 0x9667, 0xBEDE, 0x9668, 0xBEDF, 0x9669,	0xBEE0, 0xBBBA, 0xBEE1, 0x966A, 0xBEE2, 0x966B, 0xBEE3, 0xBBBB,
+	0xBEE4, 0xBBBC, 0xBEE5, 0xBBBD, 0xBEE6, 0x966C, 0xBEE7, 0x966D,	0xBEE8, 0x966E, 0xBEE9, 0x966F, 0xBEEA, 0x9670, 0xBEEB, 0x9671,
+	0xBEEC, 0xBBBE, 0xBEED, 0x9672, 0xBEEE, 0x9673, 0xBEEF, 0x9674,	0xBEF0, 0x9675, 0xBEF1, 0x9676, 0xBEF2, 0x9677, 0xBEF3, 0x9678,
+	0xBEF4, 0x9679, 0xBEF5, 0x967A, 0xBEF6, 0x9681, 0xBEF7, 0x9682,	0xBEF8, 0x9683, 0xBEF9, 0x9684, 0xBEFA, 0x9685, 0xBEFB, 0x9686,
+	0xBEFC, 0x9687, 0xBEFD, 0x9688, 0xBEFE, 0x9689, 0xBEFF, 0x968A,	0xBF00, 0x968B, 0xBF01, 0xBBBF, 0xBF02, 0x968C, 0xBF03, 0x968D,
+	0xBF04, 0x968E, 0xBF05, 0x968F, 0xBF06, 0x9690, 0xBF07, 0x9691,	0xBF08, 0xBBC0, 0xBF09, 0xBBC1, 0xBF0A, 0x9692, 0xBF0B, 0x9693,
+	0xBF0C, 0x9694, 0xBF0D, 0x9695, 0xBF0E, 0x9696, 0xBF0F, 0x9697,	0xBF10, 0x9698, 0xBF11, 0x9699, 0xBF12, 0x969A, 0xBF13, 0x969B,
+	0xBF14, 0x969C, 0xBF15, 0x969D, 0xBF16, 0x969E, 0xBF17, 0x969F,	0xBF18, 0xBBC2, 0xBF19, 0xBBC3, 0xBF1A, 0x96A0, 0xBF1B, 0xBBC4,
+	0xBF1C, 0xBBC5, 0xBF1D, 0xBBC6, 0xBF1E, 0x96A1, 0xBF1F, 0x96A2,	0xBF20, 0x96A3, 0xBF21, 0x96A4, 0xBF22, 0x96A5, 0xBF23, 0x96A6,
+	0xBF24, 0x96A7, 0xBF25, 0x96A8, 0xBF26, 0x96A9, 0xBF27, 0x96AA,	0xBF28, 0x96AB, 0xBF29, 0x96AC, 0xBF2A, 0x96AD, 0xBF2B, 0x96AE,
+	0xBF2C, 0x96AF, 0xBF2D, 0x96B0, 0xBF2E, 0x96B1, 0xBF2F, 0x96B2,	0xBF30, 0x96B3, 0xBF31, 0x96B4, 0xBF32, 0x96B5, 0xBF33, 0x96B6,
+	0xBF34, 0x96B7, 0xBF35, 0x96B8, 0xBF36, 0x96B9, 0xBF37, 0x96BA,	0xBF38, 0x96BB, 0xBF39, 0x96BC, 0xBF3A, 0x96BD, 0xBF3B, 0x96BE,
+	0xBF3C, 0x96BF, 0xBF3D, 0x96C0, 0xBF3E, 0x96C1, 0xBF3F, 0x96C2,	0xBF40, 0xBBC7, 0xBF41, 0xBBC8, 0xBF42, 0x96C3, 0xBF43, 0x96C4,
+	0xBF44, 0xBBC9, 0xBF45, 0x96C5, 0xBF46, 0x96C6, 0xBF47, 0x96C7,	0xBF48, 0xBBCA, 0xBF49, 0x96C8, 0xBF4A, 0x96C9, 0xBF4B, 0x96CA,
+	0xBF4C, 0x96CB, 0xBF4D, 0x96CC, 0xBF4E, 0x96CD, 0xBF4F, 0x96CE,	0xBF50, 0xBBCB, 0xBF51, 0xBBCC, 0xBF52, 0x96CF, 0xBF53, 0x96D0,
+	0xBF54, 0x96D1, 0xBF55, 0xBBCD, 0xBF56, 0x96D2, 0xBF57, 0x96D3,	0xBF58, 0x96D4, 0xBF59, 0x96D5, 0xBF5A, 0x96D6, 0xBF5B, 0x96D7,
+	0xBF5C, 0x96D8, 0xBF5D, 0x96D9, 0xBF5E, 0x96DA, 0xBF5F, 0x96DB,	0xBF60, 0x96DC, 0xBF61, 0x96DD, 0xBF62, 0x96DE, 0xBF63, 0x96DF,
+	0xBF64, 0x96E0, 0xBF65, 0x96E1, 0xBF66, 0x96E2, 0xBF67, 0x96E3,	0xBF68, 0x96E4, 0xBF69, 0x96E5, 0xBF6A, 0x96E6, 0xBF6B, 0x96E7,
+	0xBF6C, 0x96E8, 0xBF6D, 0x96E9, 0xBF6E, 0x96EA, 0xBF6F, 0x96EB,	0xBF70, 0x96EC, 0xBF71, 0x96ED, 0xBF72, 0x96EE, 0xBF73, 0x96EF,
+	0xBF74, 0x96F0, 0xBF75, 0x96F1, 0xBF76, 0x96F2, 0xBF77, 0x96F3,	0xBF78, 0x96F4, 0xBF79, 0x96F5, 0xBF7A, 0x96F6, 0xBF7B, 0x96F7,
+	0xBF7C, 0x96F8, 0xBF7D, 0x96F9, 0xBF7E, 0x96FA, 0xBF7F, 0x96FB,	0xBF80, 0x96FC, 0xBF81, 0x96FD, 0xBF82, 0x96FE, 0xBF83, 0x9741,
+	0xBF84, 0x9742, 0xBF85, 0x9743, 0xBF86, 0x9744, 0xBF87, 0x9745,	0xBF88, 0x9746, 0xBF89, 0x9747, 0xBF8A, 0x9748, 0xBF8B, 0x9749,
+	0xBF8C, 0x974A, 0xBF8D, 0x974B, 0xBF8E, 0x974C, 0xBF8F, 0x974D,	0xBF90, 0x974E, 0xBF91, 0x974F, 0xBF92, 0x9750, 0xBF93, 0x9751,
+	0xBF94, 0xBBCE, 0xBF95, 0x9752, 0xBF96, 0x9753, 0xBF97, 0x9754,	0xBF98, 0x9755, 0xBF99, 0x9756, 0xBF9A, 0x9757, 0xBF9B, 0x9758,
+	0xBF9C, 0x9759, 0xBF9D, 0x975A, 0xBF9E, 0x9761, 0xBF9F, 0x9762,	0xBFA0, 0x9763, 0xBFA1, 0x9764, 0xBFA2, 0x9765, 0xBFA3, 0x9766,
+	0xBFA4, 0x9767, 0xBFA5, 0x9768, 0xBFA6, 0x9769, 0xBFA7, 0x976A,	0xBFA8, 0x976B, 0xBFA9, 0x976C, 0xBFAA, 0x976D, 0xBFAB, 0x976E,
+	0xBFAC, 0x976F, 0xBFAD, 0x9770, 0xBFAE, 0x9771, 0xBFAF, 0x9772,	0xBFB0, 0xBBCF, 0xBFB1, 0x9773, 0xBFB2, 0x9774, 0xBFB3, 0x9775,
+	0xBFB4, 0x9776, 0xBFB5, 0x9777, 0xBFB6, 0x9778, 0xBFB7, 0x9779,	0xBFB8, 0x977A, 0xBFB9, 0x9781, 0xBFBA, 0x9782, 0xBFBB, 0x9783,
+	0xBFBC, 0x9784, 0xBFBD, 0x9785, 0xBFBE, 0x9786, 0xBFBF, 0x9787,	0xBFC0, 0x9788, 0xBFC1, 0x9789, 0xBFC2, 0x978A, 0xBFC3, 0x978B,
+	0xBFC4, 0x978C, 0xBFC5, 0xBBD0, 0xBFC6, 0x978D, 0xBFC7, 0x978E,	0xBFC8, 0x978F, 0xBFC9, 0x9790, 0xBFCA, 0x9791, 0xBFCB, 0x9792,
+	0xBFCC, 0xBBD1, 0xBFCD, 0xBBD2, 0xBFCE, 0x9793, 0xBFCF, 0x9794,	0xBFD0, 0xBBD3, 0xBFD1, 0x9795, 0xBFD2, 0x9796, 0xBFD3, 0x9797,
+	0xBFD4, 0xBBD4, 0xBFD5, 0x9798, 0xBFD6, 0x9799, 0xBFD7, 0x979A,	0xBFD8, 0x979B, 0xBFD9, 0x979C, 0xBFDA, 0x979D, 0xBFDB, 0x979E,
+	0xBFDC, 0xBBD5, 0xBFDD, 0x979F, 0xBFDE, 0x97A0, 0xBFDF, 0xBBD6,	0xBFE0, 0x97A1, 0xBFE1, 0xBBD7, 0xBFE2, 0x97A2, 0xBFE3, 0x97A3,
+	0xBFE4, 0x97A4, 0xBFE5, 0x97A5, 0xBFE6, 0x97A6, 0xBFE7, 0x97A7,	0xBFE8, 0x97A8, 0xBFE9, 0x97A9, 0xBFEA, 0x97AA, 0xBFEB, 0x97AB,
+	0xBFEC, 0x97AC, 0xBFED, 0x97AD, 0xBFEE, 0x97AE, 0xBFEF, 0x97AF,	0xBFF0, 0x97B0, 0xBFF1, 0x97B1, 0xBFF2, 0x97B2, 0xBFF3, 0x97B3,
+	0xBFF4, 0x97B4, 0xBFF5, 0x97B5, 0xBFF6, 0x97B6, 0xBFF7, 0x97B7,	0xBFF8, 0x97B8, 0xBFF9, 0x97B9, 0xBFFA, 0x97BA, 0xBFFB, 0x97BB,
+	0xBFFC, 0x97BC, 0xBFFD, 0x97BD, 0xBFFE, 0x97BE, 0xBFFF, 0x97BF,	0xC000, 0x97C0, 0xC001, 0x97C1, 0xC002, 0x97C2, 0xC003, 0x97C3,
+	0xC004, 0x97C4, 0xC005, 0x97C5, 0xC006, 0x97C6, 0xC007, 0x97C7,	0xC008, 0x97C8, 0xC009, 0x97C9, 0xC00A, 0x97CA, 0xC00B, 0x97CB,
+	0xC00C, 0x97CC, 0xC00D, 0x97CD, 0xC00E, 0x97CE, 0xC00F, 0x97CF,	0xC010, 0x97D0, 0xC011, 0x97D1, 0xC012, 0x97D2, 0xC013, 0x97D3,
+	0xC014, 0x97D4, 0xC015, 0x97D5, 0xC016, 0x97D6, 0xC017, 0x97D7,	0xC018, 0x97D8, 0xC019, 0x97D9, 0xC01A, 0x97DA, 0xC01B, 0x97DB,
+	0xC01C, 0x97DC, 0xC01D, 0x97DD, 0xC01E, 0x97DE, 0xC01F, 0x97DF,	0xC020, 0x97E0, 0xC021, 0x97E1, 0xC022, 0x97E2, 0xC023, 0x97E3,
+	0xC024, 0x97E4, 0xC025, 0x97E5, 0xC026, 0x97E6, 0xC027, 0x97E7,	0xC028, 0x97E8, 0xC029, 0x97E9, 0xC02A, 0x97EA, 0xC02B, 0x97EB,
+	0xC02C, 0x97EC, 0xC02D, 0x97ED, 0xC02E, 0x97EE, 0xC02F, 0x97EF,	0xC030, 0x97F0, 0xC031, 0x97F1, 0xC032, 0x97F2, 0xC033, 0x97F3,
+	0xC034, 0x97F4, 0xC035, 0x97F5, 0xC036, 0x97F6, 0xC037, 0x97F7,	0xC038, 0x97F8, 0xC039, 0x97F9, 0xC03A, 0x97FA, 0xC03B, 0x97FB,
+	0xC03C, 0xBBD8, 0xC03D, 0x97FC, 0xC03E, 0x97FD, 0xC03F, 0x97FE,	0xC040, 0x9841, 0xC041, 0x9842, 0xC042, 0x9843, 0xC043, 0x9844,
+	0xC044, 0x9845, 0xC045, 0x9846, 0xC046, 0x9847, 0xC047, 0x9848,	0xC048, 0x9849, 0xC049, 0x984A, 0xC04A, 0x984B, 0xC04B, 0x984C,
+	0xC04C, 0x984D, 0xC04D, 0x984E, 0xC04E, 0x984F, 0xC04F, 0x9850,	0xC050, 0x9851, 0xC051, 0xBBD9, 0xC052, 0x9852, 0xC053, 0x9853,
+	0xC054, 0x9854, 0xC055, 0x9855, 0xC056, 0x9856, 0xC057, 0x9857,	0xC058, 0xBBDA, 0xC059, 0x9858, 0xC05A, 0x9859, 0xC05B, 0x985A,
+	0xC05C, 0xBBDB, 0xC05D, 0x9861, 0xC05E, 0x9862, 0xC05F, 0x9863,	0xC060, 0xBBDC, 0xC061, 0x9864, 0xC062, 0x9865, 0xC063, 0x9866,
+	0xC064, 0x9867, 0xC065, 0x9868, 0xC066, 0x9869, 0xC067, 0x986A,	0xC068, 0xBBDD, 0xC069, 0xBBDE, 0xC06A, 0x986B, 0xC06B, 0x986C,
+	0xC06C, 0x986D, 0xC06D, 0x986E, 0xC06E, 0x986F, 0xC06F, 0x9870,	0xC070, 0x9871, 0xC071, 0x9872, 0xC072, 0x9873, 0xC073, 0x9874,
+	0xC074, 0x9875, 0xC075, 0x9876, 0xC076, 0x9877, 0xC077, 0x9878,	0xC078, 0x9879, 0xC079, 0x987A, 0xC07A, 0x9881, 0xC07B, 0x9882,
+	0xC07C, 0x9883, 0xC07D, 0x9884, 0xC07E, 0x9885, 0xC07F, 0x9886,	0xC080, 0x9887, 0xC081, 0x9888, 0xC082, 0x9889, 0xC083, 0x988A,
+	0xC084, 0x988B, 0xC085, 0x988C, 0xC086, 0x988D, 0xC087, 0x988E,	0xC088, 0x988F, 0xC089, 0x9890, 0xC08A, 0x9891, 0xC08B, 0x9892,
+	0xC08C, 0x9893, 0xC08D, 0x9894, 0xC08E, 0x9895, 0xC08F, 0x9896,	0xC090, 0xBBDF, 0xC091, 0xBBE0, 0xC092, 0x9897, 0xC093, 0x9898,
+	0xC094, 0xBBE1, 0xC095, 0x9899, 0xC096, 0x989A, 0xC097, 0x989B,	0xC098, 0xBBE2, 0xC099, 0x989C, 0xC09A, 0x989D, 0xC09B, 0x989E,
+	0xC09C, 0x989F, 0xC09D, 0x98A0, 0xC09E, 0x98A1, 0xC09F, 0x98A2,	0xC0A0, 0xBBE3, 0xC0A1, 0xBBE4, 0xC0A2, 0x98A3, 0xC0A3, 0xBBE5,
+	0xC0A4, 0x98A4, 0xC0A5, 0xBBE6, 0xC0A6, 0x98A5, 0xC0A7, 0x98A6,	0xC0A8, 0x98A7, 0xC0A9, 0x98A8, 0xC0AA, 0x98A9, 0xC0AB, 0x98AA,
+	0xC0AC, 0xBBE7, 0xC0AD, 0xBBE8, 0xC0AE, 0x98AB, 0xC0AF, 0xBBE9,	0xC0B0, 0xBBEA, 0xC0B1, 0x98AC, 0xC0B2, 0x98AD, 0xC0B3, 0xBBEB,
+	0xC0B4, 0xBBEC, 0xC0B5, 0xBBED, 0xC0B6, 0xBBEE, 0xC0B7, 0x98AE,	0xC0B8, 0x98AF, 0xC0B9, 0x98B0, 0xC0BA, 0x98B1, 0xC0BB, 0x98B2,
+	0xC0BC, 0xBBEF, 0xC0BD, 0xBBF0, 0xC0BE, 0x98B3, 0xC0BF, 0xBBF1,	0xC0C0, 0xBBF2, 0xC0C1, 0xBBF3, 0xC0C2, 0x98B4, 0xC0C3, 0x98B5,
+	0xC0C4, 0x98B6, 0xC0C5, 0xBBF4, 0xC0C6, 0x98B7, 0xC0C7, 0x98B8,	0xC0C8, 0xBBF5, 0xC0C9, 0xBBF6, 0xC0CA, 0x98B9, 0xC0CB, 0x98BA,
+	0xC0CC, 0xBBF7, 0xC0CD, 0x98BB, 0xC0CE, 0x98BC, 0xC0CF, 0x98BD,	0xC0D0, 0xBBF8, 0xC0D1, 0x98BE, 0xC0D2, 0x98BF, 0xC0D3, 0x98C0,
+	0xC0D4, 0x98C1, 0xC0D5, 0x98C2, 0xC0D6, 0x98C3, 0xC0D7, 0x98C4,	0xC0D8, 0xBBF9, 0xC0D9, 0xBBFA, 0xC0DA, 0x98C5, 0xC0DB, 0xBBFB,
+	0xC0DC, 0xBBFC, 0xC0DD, 0xBBFD, 0xC0DE, 0x98C6, 0xC0DF, 0x98C7,	0xC0E0, 0x98C8, 0xC0E1, 0x98C9, 0xC0E2, 0x98CA, 0xC0E3, 0x98CB,
+	0xC0E4, 0xBBFE, 0xC0E5, 0xBCA1, 0xC0E6, 0x98CC, 0xC0E7, 0x98CD,	0xC0E8, 0xBCA2, 0xC0E9, 0x98CE, 0xC0EA, 0x98CF, 0xC0EB, 0x98D0,
+	0xC0EC, 0xBCA3, 0xC0ED, 0x98D1, 0xC0EE, 0x98D2, 0xC0EF, 0x98D3,	0xC0F0, 0x98D4, 0xC0F1, 0x98D5, 0xC0F2, 0x98D6, 0xC0F3, 0x98D7,
+	0xC0F4, 0xBCA4, 0xC0F5, 0xBCA5, 0xC0F6, 0x98D8, 0xC0F7, 0xBCA6,	0xC0F8, 0x98D9, 0xC0F9, 0xBCA7, 0xC0FA, 0x98DA, 0xC0FB, 0x98DB,
+	0xC0FC, 0x98DC, 0xC0FD, 0x98DD, 0xC0FE, 0x98DE, 0xC0FF, 0x98DF,	0xC100, 0xBCA8, 0xC101, 0x98E0, 0xC102, 0x98E1, 0xC103, 0x98E2,
+	0xC104, 0xBCA9, 0xC105, 0x98E3, 0xC106, 0x98E4, 0xC107, 0x98E5,	0xC108, 0xBCAA, 0xC109, 0x98E6, 0xC10A, 0x98E7, 0xC10B, 0x98E8,
+	0xC10C, 0x98E9, 0xC10D, 0x98EA, 0xC10E, 0x98EB, 0xC10F, 0x98EC,	0xC110, 0xBCAB, 0xC111, 0x98ED, 0xC112, 0x98EE, 0xC113, 0x98EF,
+	0xC114, 0x98F0, 0xC115, 0xBCAC, 0xC116, 0x98F1, 0xC117, 0x98F2,	0xC118, 0x98F3, 0xC119, 0x98F4, 0xC11A, 0x98F5, 0xC11B, 0x98F6,
+	0xC11C, 0xBCAD, 0xC11D, 0xBCAE, 0xC11E, 0xBCAF, 0xC11F, 0xBCB0,	0xC120, 0xBCB1, 0xC121, 0x98F7, 0xC122, 0x98F8, 0xC123, 0xBCB2,
+	0xC124, 0xBCB3, 0xC125, 0x98F9, 0xC126, 0xBCB4, 0xC127, 0xBCB5,	0xC128, 0x98FA, 0xC129, 0x98FB, 0xC12A, 0x98FC, 0xC12B, 0x98FD,
+	0xC12C, 0xBCB6, 0xC12D, 0xBCB7, 0xC12E, 0x98FE, 0xC12F, 0xBCB8,	0xC130, 0xBCB9, 0xC131, 0xBCBA, 0xC132, 0x9941, 0xC133, 0x9942,
+	0xC134, 0x9943, 0xC135, 0x9944, 0xC136, 0xBCBB, 0xC137, 0x9945,	0xC138, 0xBCBC, 0xC139, 0xBCBD, 0xC13A, 0x9946, 0xC13B, 0x9947,
+	0xC13C, 0xBCBE, 0xC13D, 0x9948, 0xC13E, 0x9949, 0xC13F, 0x994A,	0xC140, 0xBCBF, 0xC141, 0x994B, 0xC142, 0x994C, 0xC143, 0x994D,
+	0xC144, 0x994E, 0xC145, 0x994F, 0xC146, 0x9950, 0xC147, 0x9951,	0xC148, 0xBCC0, 0xC149, 0xBCC1, 0xC14A, 0x9952, 0xC14B, 0xBCC2,
+	0xC14C, 0xBCC3, 0xC14D, 0xBCC4, 0xC14E, 0x9953, 0xC14F, 0x9954,	0xC150, 0x9955, 0xC151, 0x9956, 0xC152, 0x9957, 0xC153, 0x9958,
+	0xC154, 0xBCC5, 0xC155, 0xBCC6, 0xC156, 0x9959, 0xC157, 0x995A,	0xC158, 0xBCC7, 0xC159, 0x9961, 0xC15A, 0x9962, 0xC15B, 0x9963,
+	0xC15C, 0xBCC8, 0xC15D, 0x9964, 0xC15E, 0x9965, 0xC15F, 0x9966,	0xC160, 0x9967, 0xC161, 0x9968, 0xC162, 0x9969, 0xC163, 0x996A,
+	0xC164, 0xBCC9, 0xC165, 0xBCCA, 0xC166, 0x996B, 0xC167, 0xBCCB,	0xC168, 0xBCCC, 0xC169, 0xBCCD, 0xC16A, 0x996C, 0xC16B, 0x996D,
+	0xC16C, 0x996E, 0xC16D, 0x996F, 0xC16E, 0x9970, 0xC16F, 0x9971,	0xC170, 0xBCCE, 0xC171, 0x9972, 0xC172, 0x9973, 0xC173, 0x9974,
+	0xC174, 0xBCCF, 0xC175, 0x9975, 0xC176, 0x9976, 0xC177, 0x9977,	0xC178, 0xBCD0, 0xC179, 0x9978, 0xC17A, 0x9979, 0xC17B, 0x997A,
+	0xC17C, 0x9981, 0xC17D, 0x9982, 0xC17E, 0x9983, 0xC17F, 0x9984,	0xC180, 0x9985, 0xC181, 0x9986, 0xC182, 0x9987, 0xC183, 0x9988,
+	0xC184, 0x9989, 0xC185, 0xBCD1, 0xC186, 0x998A, 0xC187, 0x998B,	0xC188, 0x998C, 0xC189, 0x998D, 0xC18A, 0x998E, 0xC18B, 0x998F,
+	0xC18C, 0xBCD2, 0xC18D, 0xBCD3, 0xC18E, 0xBCD4, 0xC18F, 0x9990,	0xC190, 0xBCD5, 0xC191, 0x9991, 0xC192, 0x9992, 0xC193, 0x9993,
+	0xC194, 0xBCD6, 0xC195, 0x9994, 0xC196, 0xBCD7, 0xC197, 0x9995,	0xC198, 0x9996, 0xC199, 0x9997, 0xC19A, 0x9998, 0xC19B, 0x9999,
+	0xC19C, 0xBCD8, 0xC19D, 0xBCD9, 0xC19E, 0x999A, 0xC19F, 0xBCDA,	0xC1A0, 0x999B, 0xC1A1, 0xBCDB, 0xC1A2, 0x999C, 0xC1A3, 0x999D,
+	0xC1A4, 0x999E, 0xC1A5, 0xBCDC, 0xC1A6, 0x999F, 0xC1A7, 0x99A0,	0xC1A8, 0xBCDD, 0xC1A9, 0xBCDE, 0xC1AA, 0x99A1, 0xC1AB, 0x99A2,
+	0xC1AC, 0xBCDF, 0xC1AD, 0x99A3, 0xC1AE, 0x99A4, 0xC1AF, 0x99A5,	0xC1B0, 0xBCE0, 0xC1B1, 0x99A6, 0xC1B2, 0x99A7, 0xC1B3, 0x99A8,
+	0xC1B4, 0x99A9, 0xC1B5, 0x99AA, 0xC1B6, 0x99AB, 0xC1B7, 0x99AC,	0xC1B8, 0x99AD, 0xC1B9, 0x99AE, 0xC1BA, 0x99AF, 0xC1BB, 0x99B0,
+	0xC1BC, 0x99B1, 0xC1BD, 0xBCE1, 0xC1BE, 0x99B2, 0xC1BF, 0x99B3,	0xC1C0, 0x99B4, 0xC1C1, 0x99B5, 0xC1C2, 0x99B6, 0xC1C3, 0x99B7,
+	0xC1C4, 0xBCE2, 0xC1C5, 0x99B8, 0xC1C6, 0x99B9, 0xC1C7, 0x99BA,	0xC1C8, 0xBCE3, 0xC1C9, 0x99BB, 0xC1CA, 0x99BC, 0xC1CB, 0x99BD,
+	0xC1CC, 0xBCE4, 0xC1CD, 0x99BE, 0xC1CE, 0x99BF, 0xC1CF, 0x99C0,	0xC1D0, 0x99C1, 0xC1D1, 0x99C2, 0xC1D2, 0x99C3, 0xC1D3, 0x99C4,
+	0xC1D4, 0xBCE5, 0xC1D5, 0x99C5, 0xC1D6, 0x99C6, 0xC1D7, 0xBCE6,	0xC1D8, 0xBCE7, 0xC1D9, 0x99C7, 0xC1DA, 0x99C8, 0xC1DB, 0x99C9,
+	0xC1DC, 0x99CA, 0xC1DD, 0x99CB, 0xC1DE, 0x99CC, 0xC1DF, 0x99CD,	0xC1E0, 0xBCE8, 0xC1E1, 0x99CE, 0xC1E2, 0x99CF, 0xC1E3, 0x99D0,
+	0xC1E4, 0xBCE9, 0xC1E5, 0x99D1, 0xC1E6, 0x99D2, 0xC1E7, 0x99D3,	0xC1E8, 0xBCEA, 0xC1E9, 0x99D4, 0xC1EA, 0x99D5, 0xC1EB, 0x99D6,
+	0xC1EC, 0x99D7, 0xC1ED, 0x99D8, 0xC1EE, 0x99D9, 0xC1EF, 0x99DA,	0xC1F0, 0xBCEB, 0xC1F1, 0xBCEC, 0xC1F2, 0x99DB, 0xC1F3, 0xBCED,
+	0xC1F4, 0x99DC, 0xC1F5, 0x99DD, 0xC1F6, 0x99DE, 0xC1F7, 0x99DF,	0xC1F8, 0x99E0, 0xC1F9, 0x99E1, 0xC1FA, 0x99E2, 0xC1FB, 0x99E3,
+	0xC1FC, 0xBCEE, 0xC1FD, 0xBCEF, 0xC1FE, 0x99E4, 0xC1FF, 0x99E5,	0xC200, 0xBCF0, 0xC201, 0x99E6, 0xC202, 0x99E7, 0xC203, 0x99E8,
+	0xC204, 0xBCF1, 0xC205, 0x99E9, 0xC206, 0x99EA, 0xC207, 0x99EB,	0xC208, 0x99EC, 0xC209, 0x99ED, 0xC20A, 0x99EE, 0xC20B, 0x99EF,
+	0xC20C, 0xBCF2, 0xC20D, 0xBCF3, 0xC20E, 0x99F0, 0xC20F, 0xBCF4,	0xC210, 0x99F1, 0xC211, 0xBCF5, 0xC212, 0x99F2, 0xC213, 0x99F3,
+	0xC214, 0x99F4, 0xC215, 0x99F5, 0xC216, 0x99F6, 0xC217, 0x99F7,	0xC218, 0xBCF6, 0xC219, 0xBCF7, 0xC21A, 0x99F8, 0xC21B, 0x99F9,
+	0xC21C, 0xBCF8, 0xC21D, 0x99FA, 0xC21E, 0x99FB, 0xC21F, 0xBCF9,	0xC220, 0xBCFA, 0xC221, 0x99FC, 0xC222, 0x99FD, 0xC223, 0x99FE,
+	0xC224, 0x9A41, 0xC225, 0x9A42, 0xC226, 0x9A43, 0xC227, 0x9A44,	0xC228, 0xBCFB, 0xC229, 0xBCFC, 0xC22A, 0x9A45, 0xC22B, 0xBCFD,
+	0xC22C, 0x9A46, 0xC22D, 0xBCFE, 0xC22E, 0x9A47, 0xC22F, 0xBDA1,	0xC230, 0x9A48, 0xC231, 0xBDA2, 0xC232, 0xBDA3, 0xC233, 0x9A49,
+	0xC234, 0xBDA4, 0xC235, 0x9A4A, 0xC236, 0x9A4B, 0xC237, 0x9A4C,	0xC238, 0x9A4D, 0xC239, 0x9A4E, 0xC23A, 0x9A4F, 0xC23B, 0x9A50,
+	0xC23C, 0x9A51, 0xC23D, 0x9A52, 0xC23E, 0x9A53, 0xC23F, 0x9A54,	0xC240, 0x9A55, 0xC241, 0x9A56, 0xC242, 0x9A57, 0xC243, 0x9A58,
+	0xC244, 0x9A59, 0xC245, 0x9A5A, 0xC246, 0x9A61, 0xC247, 0x9A62,	0xC248, 0xBDA5, 0xC249, 0x9A63, 0xC24A, 0x9A64, 0xC24B, 0x9A65,
+	0xC24C, 0x9A66, 0xC24D, 0x9A67, 0xC24E, 0x9A68, 0xC24F, 0x9A69,	0xC250, 0xBDA6, 0xC251, 0xBDA7, 0xC252, 0x9A6A, 0xC253, 0x9A6B,
+	0xC254, 0xBDA8, 0xC255, 0x9A6C, 0xC256, 0x9A6D, 0xC257, 0x9A6E,	0xC258, 0xBDA9, 0xC259, 0x9A6F, 0xC25A, 0x9A70, 0xC25B, 0x9A71,
+	0xC25C, 0x9A72, 0xC25D, 0x9A73, 0xC25E, 0x9A74, 0xC25F, 0x9A75,	0xC260, 0xBDAA, 0xC261, 0x9A76, 0xC262, 0x9A77, 0xC263, 0x9A78,
+	0xC264, 0x9A79, 0xC265, 0xBDAB, 0xC266, 0x9A7A, 0xC267, 0x9A81,	0xC268, 0x9A82, 0xC269, 0x9A83, 0xC26A, 0x9A84, 0xC26B, 0x9A85,
+	0xC26C, 0xBDAC, 0xC26D, 0xBDAD, 0xC26E, 0x9A86, 0xC26F, 0x9A87,	0xC270, 0xBDAE, 0xC271, 0x9A88, 0xC272, 0x9A89, 0xC273, 0x9A8A,
+	0xC274, 0xBDAF, 0xC275, 0x9A8B, 0xC276, 0x9A8C, 0xC277, 0x9A8D,	0xC278, 0x9A8E, 0xC279, 0x9A8F, 0xC27A, 0x9A90, 0xC27B, 0x9A91,
+	0xC27C, 0xBDB0, 0xC27D, 0xBDB1, 0xC27E, 0x9A92, 0xC27F, 0xBDB2,	0xC280, 0x9A93, 0xC281, 0xBDB3, 0xC282, 0x9A94, 0xC283, 0x9A95,
+	0xC284, 0x9A96, 0xC285, 0x9A97, 0xC286, 0x9A98, 0xC287, 0x9A99,	0xC288, 0xBDB4, 0xC289, 0xBDB5, 0xC28A, 0x9A9A, 0xC28B, 0x9A9B,
+	0xC28C, 0x9A9C, 0xC28D, 0x9A9D, 0xC28E, 0x9A9E, 0xC28F, 0x9A9F,	0xC290, 0xBDB6, 0xC291, 0x9AA0, 0xC292, 0x9AA1, 0xC293, 0x9AA2,
+	0xC294, 0x9AA3, 0xC295, 0x9AA4, 0xC296, 0x9AA5, 0xC297, 0x9AA6,	0xC298, 0xBDB7, 0xC299, 0x9AA7, 0xC29A, 0x9AA8, 0xC29B, 0xBDB8,
+	0xC29C, 0x9AA9, 0xC29D, 0xBDB9, 0xC29E, 0x9AAA, 0xC29F, 0x9AAB,	0xC2A0, 0x9AAC, 0xC2A1, 0x9AAD, 0xC2A2, 0x9AAE, 0xC2A3, 0x9AAF,
+	0xC2A4, 0xBDBA, 0xC2A5, 0xBDBB, 0xC2A6, 0x9AB0, 0xC2A7, 0x9AB1,	0xC2A8, 0xBDBC, 0xC2A9, 0x9AB2, 0xC2AA, 0x9AB3, 0xC2AB, 0x9AB4,
+	0xC2AC, 0xBDBD, 0xC2AD, 0xBDBE, 0xC2AE, 0x9AB5, 0xC2AF, 0x9AB6,	0xC2B0, 0x9AB7, 0xC2B1, 0x9AB8, 0xC2B2, 0x9AB9, 0xC2B3, 0x9ABA,
+	0xC2B4, 0xBDBF, 0xC2B5, 0xBDC0, 0xC2B6, 0x9ABB, 0xC2B7, 0xBDC1,	0xC2B8, 0x9ABC, 0xC2B9, 0xBDC2, 0xC2BA, 0x9ABD, 0xC2BB, 0x9ABE,
+	0xC2BC, 0x9ABF, 0xC2BD, 0x9AC0, 0xC2BE, 0x9AC1, 0xC2BF, 0x9AC2,	0xC2C0, 0x9AC3, 0xC2C1, 0x9AC4, 0xC2C2, 0x9AC5, 0xC2C3, 0x9AC6,
+	0xC2C4, 0x9AC7, 0xC2C5, 0x9AC8, 0xC2C6, 0x9AC9, 0xC2C7, 0x9ACA,	0xC2C8, 0x9ACB, 0xC2C9, 0x9ACC, 0xC2CA, 0x9ACD, 0xC2CB, 0x9ACE,
+	0xC2CC, 0x9ACF, 0xC2CD, 0x9AD0, 0xC2CE, 0x9AD1, 0xC2CF, 0x9AD2,	0xC2D0, 0x9AD3, 0xC2D1, 0x9AD4, 0xC2D2, 0x9AD5, 0xC2D3, 0x9AD6,
+	0xC2D4, 0x9AD7, 0xC2D5, 0x9AD8, 0xC2D6, 0x9AD9, 0xC2D7, 0x9ADA,	0xC2D8, 0x9ADB, 0xC2D9, 0x9ADC, 0xC2DA, 0x9ADD, 0xC2DB, 0x9ADE,
+	0xC2DC, 0xBDC3, 0xC2DD, 0xBDC4, 0xC2DE, 0x9ADF, 0xC2DF, 0x9AE0,	0xC2E0, 0xBDC5, 0xC2E1, 0x9AE1, 0xC2E2, 0x9AE2, 0xC2E3, 0xBDC6,
+	0xC2E4, 0xBDC7, 0xC2E5, 0x9AE3, 0xC2E6, 0x9AE4, 0xC2E7, 0x9AE5,	0xC2E8, 0x9AE6, 0xC2E9, 0x9AE7, 0xC2EA, 0x9AE8, 0xC2EB, 0xBDC8,
+	0xC2EC, 0xBDC9, 0xC2ED, 0xBDCA, 0xC2EE, 0x9AE9, 0xC2EF, 0xBDCB,	0xC2F0, 0x9AEA, 0xC2F1, 0xBDCC, 0xC2F2, 0x9AEB, 0xC2F3, 0x9AEC,
+	0xC2F4, 0x9AED, 0xC2F5, 0x9AEE, 0xC2F6, 0xBDCD, 0xC2F7, 0x9AEF,	0xC2F8, 0xBDCE, 0xC2F9, 0xBDCF, 0xC2FA, 0x9AF0, 0xC2FB, 0xBDD0,
+	0xC2FC, 0xBDD1, 0xC2FD, 0x9AF1, 0xC2FE, 0x9AF2, 0xC2FF, 0x9AF3,	0xC300, 0xBDD2, 0xC301, 0x9AF4, 0xC302, 0x9AF5, 0xC303, 0x9AF6,
+	0xC304, 0x9AF7, 0xC305, 0x9AF8, 0xC306, 0x9AF9, 0xC307, 0x9AFA,	0xC308, 0xBDD3, 0xC309, 0xBDD4, 0xC30A, 0x9AFB, 0xC30B, 0x9AFC,
+	0xC30C, 0xBDD5, 0xC30D, 0xBDD6, 0xC30E, 0x9AFD, 0xC30F, 0x9AFE,	0xC310, 0x9B41, 0xC311, 0x9B42, 0xC312, 0x9B43, 0xC313, 0xBDD7,
+	0xC314, 0xBDD8, 0xC315, 0xBDD9, 0xC316, 0x9B44, 0xC317, 0x9B45,	0xC318, 0xBDDA, 0xC319, 0x9B46, 0xC31A, 0x9B47, 0xC31B, 0x9B48,
+	0xC31C, 0xBDDB, 0xC31D, 0x9B49, 0xC31E, 0x9B4A, 0xC31F, 0x9B4B,	0xC320, 0x9B4C, 0xC321, 0x9B4D, 0xC322, 0x9B4E, 0xC323, 0x9B4F,
+	0xC324, 0xBDDC, 0xC325, 0xBDDD, 0xC326, 0x9B50, 0xC327, 0x9B51,	0xC328, 0xBDDE, 0xC329, 0xBDDF, 0xC32A, 0x9B52, 0xC32B, 0x9B53,
+	0xC32C, 0x9B54, 0xC32D, 0x9B55, 0xC32E, 0x9B56, 0xC32F, 0x9B57,	0xC330, 0x9B58, 0xC331, 0x9B59, 0xC332, 0x9B5A, 0xC333, 0x9B61,
+	0xC334, 0x9B62, 0xC335, 0x9B63, 0xC336, 0x9B64, 0xC337, 0x9B65,	0xC338, 0x9B66, 0xC339, 0x9B67, 0xC33A, 0x9B68, 0xC33B, 0x9B69,
+	0xC33C, 0x9B6A, 0xC33D, 0x9B6B, 0xC33E, 0x9B6C, 0xC33F, 0x9B6D,	0xC340, 0x9B6E, 0xC341, 0x9B6F, 0xC342, 0x9B70, 0xC343, 0x9B71,
+	0xC344, 0x9B72, 0xC345, 0xBDE0, 0xC346, 0x9B73, 0xC347, 0x9B74,	0xC348, 0x9B75, 0xC349, 0x9B76, 0xC34A, 0x9B77, 0xC34B, 0x9B78,
+	0xC34C, 0x9B79, 0xC34D, 0x9B7A, 0xC34E, 0x9B81, 0xC34F, 0x9B82,	0xC350, 0x9B83, 0xC351, 0x9B84, 0xC352, 0x9B85, 0xC353, 0x9B86,
+	0xC354, 0x9B87, 0xC355, 0x9B88, 0xC356, 0x9B89, 0xC357, 0x9B8A,	0xC358, 0x9B8B, 0xC359, 0x9B8C, 0xC35A, 0x9B8D, 0xC35B, 0x9B8E,
+	0xC35C, 0x9B8F, 0xC35D, 0x9B90, 0xC35E, 0x9B91, 0xC35F, 0x9B92,	0xC360, 0x9B93, 0xC361, 0x9B94, 0xC362, 0x9B95, 0xC363, 0x9B96,
+	0xC364, 0x9B97, 0xC365, 0x9B98, 0xC366, 0x9B99, 0xC367, 0x9B9A,	0xC368, 0xBDE1, 0xC369, 0xBDE2, 0xC36A, 0x9B9B, 0xC36B, 0x9B9C,
+	0xC36C, 0xBDE3, 0xC36D, 0x9B9D, 0xC36E, 0x9B9E, 0xC36F, 0x9B9F,	0xC370, 0xBDE4, 0xC371, 0x9BA0, 0xC372, 0xBDE5, 0xC373, 0x9BA1,
+	0xC374, 0x9BA2, 0xC375, 0x9BA3, 0xC376, 0x9BA4, 0xC377, 0x9BA5,	0xC378, 0xBDE6, 0xC379, 0xBDE7, 0xC37A, 0x9BA6, 0xC37B, 0x9BA7,
+	0xC37C, 0xBDE8, 0xC37D, 0xBDE9, 0xC37E, 0x9BA8, 0xC37F, 0x9BA9,	0xC380, 0x9BAA, 0xC381, 0x9BAB, 0xC382, 0x9BAC, 0xC383, 0x9BAD,
+	0xC384, 0xBDEA, 0xC385, 0x9BAE, 0xC386, 0x9BAF, 0xC387, 0x9BB0,	0xC388, 0xBDEB, 0xC389, 0x9BB1, 0xC38A, 0x9BB2, 0xC38B, 0x9BB3,
+	0xC38C, 0xBDEC, 0xC38D, 0x9BB4, 0xC38E, 0x9BB5, 0xC38F, 0x9BB6,	0xC390, 0x9BB7, 0xC391, 0x9BB8, 0xC392, 0x9BB9, 0xC393, 0x9BBA,
+	0xC394, 0x9BBB, 0xC395, 0x9BBC, 0xC396, 0x9BBD, 0xC397, 0x9BBE,	0xC398, 0x9BBF, 0xC399, 0x9BC0, 0xC39A, 0x9BC1, 0xC39B, 0x9BC2,
+	0xC39C, 0x9BC3, 0xC39D, 0x9BC4, 0xC39E, 0x9BC5, 0xC39F, 0x9BC6,	0xC3A0, 0x9BC7, 0xC3A1, 0x9BC8, 0xC3A2, 0x9BC9, 0xC3A3, 0x9BCA,
+	0xC3A4, 0x9BCB, 0xC3A5, 0x9BCC, 0xC3A6, 0x9BCD, 0xC3A7, 0x9BCE,	0xC3A8, 0x9BCF, 0xC3A9, 0x9BD0, 0xC3AA, 0x9BD1, 0xC3AB, 0x9BD2,
+	0xC3AC, 0x9BD3, 0xC3AD, 0x9BD4, 0xC3AE, 0x9BD5, 0xC3AF, 0x9BD6,	0xC3B0, 0x9BD7, 0xC3B1, 0x9BD8, 0xC3B2, 0x9BD9, 0xC3B3, 0x9BDA,
+	0xC3B4, 0x9BDB, 0xC3B5, 0x9BDC, 0xC3B6, 0x9BDD, 0xC3B7, 0x9BDE,	0xC3B8, 0x9BDF, 0xC3B9, 0x9BE0, 0xC3BA, 0x9BE1, 0xC3BB, 0x9BE2,
+	0xC3BC, 0x9BE3, 0xC3BD, 0x9BE4, 0xC3BE, 0x9BE5, 0xC3BF, 0x9BE6,	0xC3C0, 0xBDED, 0xC3C1, 0x9BE7, 0xC3C2, 0x9BE8, 0xC3C3, 0x9BE9,
+	0xC3C4, 0x9BEA, 0xC3C5, 0x9BEB, 0xC3C6, 0x9BEC, 0xC3C7, 0x9BED,	0xC3C8, 0x9BEE, 0xC3C9, 0x9BEF, 0xC3CA, 0x9BF0, 0xC3CB, 0x9BF1,
+	0xC3CC, 0x9BF2, 0xC3CD, 0x9BF3, 0xC3CE, 0x9BF4, 0xC3CF, 0x9BF5,	0xC3D0, 0x9BF6, 0xC3D1, 0x9BF7, 0xC3D2, 0x9BF8, 0xC3D3, 0x9BF9,
+	0xC3D4, 0x9BFA, 0xC3D5, 0x9BFB, 0xC3D6, 0x9BFC, 0xC3D7, 0x9BFD,	0xC3D8, 0xBDEE, 0xC3D9, 0xBDEF, 0xC3DA, 0x9BFE, 0xC3DB, 0x9C41,
+	0xC3DC, 0xBDF0, 0xC3DD, 0x9C42, 0xC3DE, 0x9C43, 0xC3DF, 0xBDF1,	0xC3E0, 0xBDF2, 0xC3E1, 0x9C44, 0xC3E2, 0xBDF3, 0xC3E3, 0x9C45,
+	0xC3E4, 0x9C46, 0xC3E5, 0x9C47, 0xC3E6, 0x9C48, 0xC3E7, 0x9C49,	0xC3E8, 0xBDF4, 0xC3E9, 0xBDF5, 0xC3EA, 0x9C4A, 0xC3EB, 0x9C4B,
+	0xC3EC, 0x9C4C, 0xC3ED, 0xBDF6, 0xC3EE, 0x9C4D, 0xC3EF, 0x9C4E,	0xC3F0, 0x9C4F, 0xC3F1, 0x9C50, 0xC3F2, 0x9C51, 0xC3F3, 0x9C52,
+	0xC3F4, 0xBDF7, 0xC3F5, 0xBDF8, 0xC3F6, 0x9C53, 0xC3F7, 0x9C54,	0xC3F8, 0xBDF9, 0xC3F9, 0x9C55, 0xC3FA, 0x9C56, 0xC3FB, 0x9C57,
+	0xC3FC, 0x9C58, 0xC3FD, 0x9C59, 0xC3FE, 0x9C5A, 0xC3FF, 0x9C61,	0xC400, 0x9C62, 0xC401, 0x9C63, 0xC402, 0x9C64, 0xC403, 0x9C65,
+	0xC404, 0x9C66, 0xC405, 0x9C67, 0xC406, 0x9C68, 0xC407, 0x9C69,	0xC408, 0xBDFA, 0xC409, 0x9C6A, 0xC40A, 0x9C6B, 0xC40B, 0x9C6C,
+	0xC40C, 0x9C6D, 0xC40D, 0x9C6E, 0xC40E, 0x9C6F, 0xC40F, 0x9C70,	0xC410, 0xBDFB, 0xC411, 0x9C71, 0xC412, 0x9C72, 0xC413, 0x9C73,
+	0xC414, 0x9C74, 0xC415, 0x9C75, 0xC416, 0x9C76, 0xC417, 0x9C77,	0xC418, 0x9C78, 0xC419, 0x9C79, 0xC41A, 0x9C7A, 0xC41B, 0x9C81,
+	0xC41C, 0x9C82, 0xC41D, 0x9C83, 0xC41E, 0x9C84, 0xC41F, 0x9C85,	0xC420, 0x9C86, 0xC421, 0x9C87, 0xC422, 0x9C88, 0xC423, 0x9C89,
+	0xC424, 0xBDFC, 0xC425, 0x9C8A, 0xC426, 0x9C8B, 0xC427, 0x9C8C,	0xC428, 0x9C8D, 0xC429, 0x9C8E, 0xC42A, 0x9C8F, 0xC42B, 0x9C90,
+	0xC42C, 0xBDFD, 0xC42D, 0x9C91, 0xC42E, 0x9C92, 0xC42F, 0x9C93,	0xC430, 0xBDFE, 0xC431, 0x9C94, 0xC432, 0x9C95, 0xC433, 0x9C96,
+	0xC434, 0xBEA1, 0xC435, 0x9C97, 0xC436, 0x9C98, 0xC437, 0x9C99,	0xC438, 0x9C9A, 0xC439, 0x9C9B, 0xC43A, 0x9C9C, 0xC43B, 0x9C9D,
+	0xC43C, 0xBEA2, 0xC43D, 0xBEA3, 0xC43E, 0x9C9E, 0xC43F, 0x9C9F,	0xC440, 0x9CA0, 0xC441, 0x9CA1, 0xC442, 0x9CA2, 0xC443, 0x9CA3,
+	0xC444, 0x9CA4, 0xC445, 0x9CA5, 0xC446, 0x9CA6, 0xC447, 0x9CA7,	0xC448, 0xBEA4, 0xC449, 0x9CA8, 0xC44A, 0x9CA9, 0xC44B, 0x9CAA,
+	0xC44C, 0x9CAB, 0xC44D, 0x9CAC, 0xC44E, 0x9CAD, 0xC44F, 0x9CAE,	0xC450, 0x9CAF, 0xC451, 0x9CB0, 0xC452, 0x9CB1, 0xC453, 0x9CB2,
+	0xC454, 0x9CB3, 0xC455, 0x9CB4, 0xC456, 0x9CB5, 0xC457, 0x9CB6,	0xC458, 0x9CB7, 0xC459, 0x9CB8, 0xC45A, 0x9CB9, 0xC45B, 0x9CBA,
+	0xC45C, 0x9CBB, 0xC45D, 0x9CBC, 0xC45E, 0x9CBD, 0xC45F, 0x9CBE,	0xC460, 0x9CBF, 0xC461, 0x9CC0, 0xC462, 0x9CC1, 0xC463, 0x9CC2,
+	0xC464, 0xBEA5, 0xC465, 0xBEA6, 0xC466, 0x9CC3, 0xC467, 0x9CC4,	0xC468, 0xBEA7, 0xC469, 0x9CC5, 0xC46A, 0x9CC6, 0xC46B, 0x9CC7,
+	0xC46C, 0xBEA8, 0xC46D, 0x9CC8, 0xC46E, 0x9CC9, 0xC46F, 0x9CCA,	0xC470, 0x9CCB, 0xC471, 0x9CCC, 0xC472, 0x9CCD, 0xC473, 0x9CCE,
+	0xC474, 0xBEA9, 0xC475, 0xBEAA, 0xC476, 0x9CCF, 0xC477, 0x9CD0,	0xC478, 0x9CD1, 0xC479, 0xBEAB, 0xC47A, 0x9CD2, 0xC47B, 0x9CD3,
+	0xC47C, 0x9CD4, 0xC47D, 0x9CD5, 0xC47E, 0x9CD6, 0xC47F, 0x9CD7,	0xC480, 0xBEAC, 0xC481, 0x9CD8, 0xC482, 0x9CD9, 0xC483, 0x9CDA,
+	0xC484, 0x9CDB, 0xC485, 0x9CDC, 0xC486, 0x9CDD, 0xC487, 0x9CDE,	0xC488, 0x9CDF, 0xC489, 0x9CE0, 0xC48A, 0x9CE1, 0xC48B, 0x9CE2,
+	0xC48C, 0x9CE3, 0xC48D, 0x9CE4, 0xC48E, 0x9CE5, 0xC48F, 0x9CE6,	0xC490, 0x9CE7, 0xC491, 0x9CE8, 0xC492, 0x9CE9, 0xC493, 0x9CEA,
+	0xC494, 0xBEAD, 0xC495, 0x9CEB, 0xC496, 0x9CEC, 0xC497, 0x9CED,	0xC498, 0x9CEE, 0xC499, 0x9CEF, 0xC49A, 0x9CF0, 0xC49B, 0x9CF1,
+	0xC49C, 0xBEAE, 0xC49D, 0x9CF2, 0xC49E, 0x9CF3, 0xC49F, 0x9CF4,	0xC4A0, 0x9CF5, 0xC4A1, 0x9CF6, 0xC4A2, 0x9CF7, 0xC4A3, 0x9CF8,
+	0xC4A4, 0x9CF9, 0xC4A5, 0x9CFA, 0xC4A6, 0x9CFB, 0xC4A7, 0x9CFC,	0xC4A8, 0x9CFD, 0xC4A9, 0x9CFE, 0xC4AA, 0x9D41, 0xC4AB, 0x9D42,
+	0xC4AC, 0x9D43, 0xC4AD, 0x9D44, 0xC4AE, 0x9D45, 0xC4AF, 0x9D46,	0xC4B0, 0x9D47, 0xC4B1, 0x9D48, 0xC4B2, 0x9D49, 0xC4B3, 0x9D4A,
+	0xC4B4, 0x9D4B, 0xC4B5, 0x9D4C, 0xC4B6, 0x9D4D, 0xC4B7, 0x9D4E,	0xC4B8, 0xBEAF, 0xC4B9, 0x9D4F, 0xC4BA, 0x9D50, 0xC4BB, 0x9D51,
+	0xC4BC, 0xBEB0, 0xC4BD, 0x9D52, 0xC4BE, 0x9D53, 0xC4BF, 0x9D54,	0xC4C0, 0x9D55, 0xC4C1, 0x9D56, 0xC4C2, 0x9D57, 0xC4C3, 0x9D58,
+	0xC4C4, 0x9D59, 0xC4C5, 0x9D5A, 0xC4C6, 0x9D61, 0xC4C7, 0x9D62,	0xC4C8, 0x9D63, 0xC4C9, 0x9D64, 0xC4CA, 0x9D65, 0xC4CB, 0x9D66,
+	0xC4CC, 0x9D67, 0xC4CD, 0x9D68, 0xC4CE, 0x9D69, 0xC4CF, 0x9D6A,	0xC4D0, 0x9D6B, 0xC4D1, 0x9D6C, 0xC4D2, 0x9D6D, 0xC4D3, 0x9D6E,
+	0xC4D4, 0x9D6F, 0xC4D5, 0x9D70, 0xC4D6, 0x9D71, 0xC4D7, 0x9D72,	0xC4D8, 0x9D73, 0xC4D9, 0x9D74, 0xC4DA, 0x9D75, 0xC4DB, 0x9D76,
+	0xC4DC, 0x9D77, 0xC4DD, 0x9D78, 0xC4DE, 0x9D79, 0xC4DF, 0x9D7A,	0xC4E0, 0x9D81, 0xC4E1, 0x9D82, 0xC4E2, 0x9D83, 0xC4E3, 0x9D84,
+	0xC4E4, 0x9D85, 0xC4E5, 0x9D86, 0xC4E6, 0x9D87, 0xC4E7, 0x9D88,	0xC4E8, 0x9D89, 0xC4E9, 0xBEB1, 0xC4EA, 0x9D8A, 0xC4EB, 0x9D8B,
+	0xC4EC, 0x9D8C, 0xC4ED, 0x9D8D, 0xC4EE, 0x9D8E, 0xC4EF, 0x9D8F,	0xC4F0, 0xBEB2, 0xC4F1, 0xBEB3, 0xC4F2, 0x9D90, 0xC4F3, 0x9D91,
+	0xC4F4, 0xBEB4, 0xC4F5, 0x9D92, 0xC4F6, 0x9D93, 0xC4F7, 0x9D94,	0xC4F8, 0xBEB5, 0xC4F9, 0x9D95, 0xC4FA, 0xBEB6, 0xC4FB, 0x9D96,
+	0xC4FC, 0x9D97, 0xC4FD, 0x9D98, 0xC4FE, 0x9D99, 0xC4FF, 0xBEB7,	0xC500, 0xBEB8, 0xC501, 0xBEB9, 0xC502, 0x9D9A, 0xC503, 0x9D9B,
+	0xC504, 0x9D9C, 0xC505, 0x9D9D, 0xC506, 0x9D9E, 0xC507, 0x9D9F,	0xC508, 0x9DA0, 0xC509, 0x9DA1, 0xC50A, 0x9DA2, 0xC50B, 0x9DA3,
+	0xC50C, 0xBEBA, 0xC50D, 0x9DA4, 0xC50E, 0x9DA5, 0xC50F, 0x9DA6,	0xC510, 0xBEBB, 0xC511, 0x9DA7, 0xC512, 0x9DA8, 0xC513, 0x9DA9,
+	0xC514, 0xBEBC, 0xC515, 0x9DAA, 0xC516, 0x9DAB, 0xC517, 0x9DAC,	0xC518, 0x9DAD, 0xC519, 0x9DAE, 0xC51A, 0x9DAF, 0xC51B, 0x9DB0,
+	0xC51C, 0xBEBD, 0xC51D, 0x9DB1, 0xC51E, 0x9DB2, 0xC51F, 0x9DB3,	0xC520, 0x9DB4, 0xC521, 0x9DB5, 0xC522, 0x9DB6, 0xC523, 0x9DB7,
+	0xC524, 0x9DB8, 0xC525, 0x9DB9, 0xC526, 0x9DBA, 0xC527, 0x9DBB,	0xC528, 0xBEBE, 0xC529, 0xBEBF, 0xC52A, 0x9DBC, 0xC52B, 0x9DBD,
+	0xC52C, 0xBEC0, 0xC52D, 0x9DBE, 0xC52E, 0x9DBF, 0xC52F, 0x9DC0,	0xC530, 0xBEC1, 0xC531, 0x9DC1, 0xC532, 0x9DC2, 0xC533, 0x9DC3,
+	0xC534, 0x9DC4, 0xC535, 0x9DC5, 0xC536, 0x9DC6, 0xC537, 0x9DC7,	0xC538, 0xBEC2, 0xC539, 0xBEC3, 0xC53A, 0x9DC8, 0xC53B, 0xBEC4,
+	0xC53C, 0x9DC9, 0xC53D, 0xBEC5, 0xC53E, 0x9DCA, 0xC53F, 0x9DCB,	0xC540, 0x9DCC, 0xC541, 0x9DCD, 0xC542, 0x9DCE, 0xC543, 0x9DCF,
+	0xC544, 0xBEC6, 0xC545, 0xBEC7, 0xC546, 0x9DD0, 0xC547, 0x9DD1,	0xC548, 0xBEC8, 0xC549, 0xBEC9, 0xC54A, 0xBECA, 0xC54B, 0x9DD2,
+	0xC54C, 0xBECB, 0xC54D, 0xBECC, 0xC54E, 0xBECD, 0xC54F, 0x9DD3,	0xC550, 0x9DD4, 0xC551, 0x9DD5, 0xC552, 0x9DD6, 0xC553, 0xBECE,
+	0xC554, 0xBECF, 0xC555, 0xBED0, 0xC556, 0x9DD7, 0xC557, 0xBED1,	0xC558, 0xBED2, 0xC559, 0xBED3, 0xC55A, 0x9DD8, 0xC55B, 0x9DD9,
+	0xC55C, 0x9DDA, 0xC55D, 0xBED4, 0xC55E, 0xBED5, 0xC55F, 0x9DDB,	0xC560, 0xBED6, 0xC561, 0xBED7, 0xC562, 0x9DDC, 0xC563, 0x9DDD,
+	0xC564, 0xBED8, 0xC565, 0x9DDE, 0xC566, 0x9DDF, 0xC567, 0x9DE0,	0xC568, 0xBED9, 0xC569, 0x9DE1, 0xC56A, 0x9DE2, 0xC56B, 0x9DE3,
+	0xC56C, 0x9DE4, 0xC56D, 0x9DE5, 0xC56E, 0x9DE6, 0xC56F, 0x9DE7,	0xC570, 0xBEDA, 0xC571, 0xBEDB, 0xC572, 0x9DE8, 0xC573, 0xBEDC,
+	0xC574, 0xBEDD, 0xC575, 0xBEDE, 0xC576, 0x9DE9, 0xC577, 0x9DEA,	0xC578, 0x9DEB, 0xC579, 0x9DEC, 0xC57A, 0x9DED, 0xC57B, 0x9DEE,
+	0xC57C, 0xBEDF, 0xC57D, 0xBEE0, 0xC57E, 0x9DEF, 0xC57F, 0x9DF0,	0xC580, 0xBEE1, 0xC581, 0x9DF1, 0xC582, 0x9DF2, 0xC583, 0x9DF3,
+	0xC584, 0xBEE2, 0xC585, 0x9DF4, 0xC586, 0x9DF5, 0xC587, 0xBEE3,	0xC588, 0x9DF6, 0xC589, 0x9DF7, 0xC58A, 0x9DF8, 0xC58B, 0x9DF9,
+	0xC58C, 0xBEE4, 0xC58D, 0xBEE5, 0xC58E, 0x9DFA, 0xC58F, 0xBEE6,	0xC590, 0x9DFB, 0xC591, 0xBEE7, 0xC592, 0x9DFC, 0xC593, 0x9DFD,
+	0xC594, 0x9DFE, 0xC595, 0xBEE8, 0xC596, 0x9E41, 0xC597, 0xBEE9,	0xC598, 0xBEEA, 0xC599, 0x9E42, 0xC59A, 0x9E43, 0xC59B, 0x9E44,
+	0xC59C, 0xBEEB, 0xC59D, 0x9E45, 0xC59E, 0x9E46, 0xC59F, 0x9E47,	0xC5A0, 0xBEEC, 0xC5A1, 0x9E48, 0xC5A2, 0x9E49, 0xC5A3, 0x9E4A,
+	0xC5A4, 0x9E4B, 0xC5A5, 0x9E4C, 0xC5A6, 0x9E4D, 0xC5A7, 0x9E4E,	0xC5A8, 0x9E4F, 0xC5A9, 0xBEED, 0xC5AA, 0x9E50, 0xC5AB, 0x9E51,
+	0xC5AC, 0x9E52, 0xC5AD, 0x9E53, 0xC5AE, 0x9E54, 0xC5AF, 0x9E55,	0xC5B0, 0x9E56, 0xC5B1, 0x9E57, 0xC5B2, 0x9E58, 0xC5B3, 0x9E59,
+	0xC5B4, 0xBEEE, 0xC5B5, 0xBEEF, 0xC5B6, 0x9E5A, 0xC5B7, 0x9E61,	0xC5B8, 0xBEF0, 0xC5B9, 0xBEF1, 0xC5BA, 0x9E62, 0xC5BB, 0xBEF2,
+	0xC5BC, 0xBEF3, 0xC5BD, 0xBEF4, 0xC5BE, 0xBEF5, 0xC5BF, 0x9E63,	0xC5C0, 0x9E64, 0xC5C1, 0x9E65, 0xC5C2, 0x9E66, 0xC5C3, 0x9E67,
+	0xC5C4, 0xBEF6, 0xC5C5, 0xBEF7, 0xC5C6, 0xBEF8, 0xC5C7, 0xBEF9,	0xC5C8, 0xBEFA, 0xC5C9, 0xBEFB, 0xC5CA, 0xBEFC, 0xC5CB, 0x9E68,
+	0xC5CC, 0xBEFD, 0xC5CD, 0x9E69, 0xC5CE, 0xBEFE, 0xC5CF, 0x9E6A,	0xC5D0, 0xBFA1, 0xC5D1, 0xBFA2, 0xC5D2, 0x9E6B, 0xC5D3, 0x9E6C,
+	0xC5D4, 0xBFA3, 0xC5D5, 0x9E6D, 0xC5D6, 0x9E6E, 0xC5D7, 0x9E6F,	0xC5D8, 0xBFA4, 0xC5D9, 0x9E70, 0xC5DA, 0x9E71, 0xC5DB, 0x9E72,
+	0xC5DC, 0x9E73, 0xC5DD, 0x9E74, 0xC5DE, 0x9E75, 0xC5DF, 0x9E76,	0xC5E0, 0xBFA5, 0xC5E1, 0xBFA6, 0xC5E2, 0x9E77, 0xC5E3, 0xBFA7,
+	0xC5E4, 0x9E78, 0xC5E5, 0xBFA8, 0xC5E6, 0x9E79, 0xC5E7, 0x9E7A,	0xC5E8, 0x9E81, 0xC5E9, 0x9E82, 0xC5EA, 0x9E83, 0xC5EB, 0x9E84,
+	0xC5EC, 0xBFA9, 0xC5ED, 0xBFAA, 0xC5EE, 0xBFAB, 0xC5EF, 0x9E85,	0xC5F0, 0xBFAC, 0xC5F1, 0x9E86, 0xC5F2, 0x9E87, 0xC5F3, 0x9E88,
+	0xC5F4, 0xBFAD, 0xC5F5, 0x9E89, 0xC5F6, 0xBFAE, 0xC5F7, 0xBFAF,	0xC5F8, 0x9E8A, 0xC5F9, 0x9E8B, 0xC5FA, 0x9E8C, 0xC5FB, 0x9E8D,
+	0xC5FC, 0xBFB0, 0xC5FD, 0xBFB1, 0xC5FE, 0xBFB2, 0xC5FF, 0xBFB3,	0xC600, 0xBFB4, 0xC601, 0xBFB5, 0xC602, 0x9E8E, 0xC603, 0x9E8F,
+	0xC604, 0x9E90, 0xC605, 0xBFB6, 0xC606, 0xBFB7, 0xC607, 0xBFB8,	0xC608, 0xBFB9, 0xC609, 0x9E91, 0xC60A, 0x9E92, 0xC60B, 0x9E93,
+	0xC60C, 0xBFBA, 0xC60D, 0x9E94, 0xC60E, 0x9E95, 0xC60F, 0x9E96,	0xC610, 0xBFBB, 0xC611, 0x9E97, 0xC612, 0x9E98, 0xC613, 0x9E99,
+	0xC614, 0x9E9A, 0xC615, 0x9E9B, 0xC616, 0x9E9C, 0xC617, 0x9E9D,	0xC618, 0xBFBC, 0xC619, 0xBFBD, 0xC61A, 0x9E9E, 0xC61B, 0xBFBE,
+	0xC61C, 0xBFBF, 0xC61D, 0x9E9F, 0xC61E, 0x9EA0, 0xC61F, 0x9EA1,	0xC620, 0x9EA2, 0xC621, 0x9EA3, 0xC622, 0x9EA4, 0xC623, 0x9EA5,
+	0xC624, 0xBFC0, 0xC625, 0xBFC1, 0xC626, 0x9EA6, 0xC627, 0x9EA7,	0xC628, 0xBFC2, 0xC629, 0x9EA8, 0xC62A, 0x9EA9, 0xC62B, 0x9EAA,
+	0xC62C, 0xBFC3, 0xC62D, 0xBFC4, 0xC62E, 0xBFC5, 0xC62F, 0x9EAB,	0xC630, 0xBFC6, 0xC631, 0x9EAC, 0xC632, 0x9EAD, 0xC633, 0xBFC7,
+	0xC634, 0xBFC8, 0xC635, 0xBFC9, 0xC636, 0x9EAE, 0xC637, 0xBFCA,	0xC638, 0x9EAF, 0xC639, 0xBFCB, 0xC63A, 0x9EB0, 0xC63B, 0xBFCC,
+	0xC63C, 0x9EB1, 0xC63D, 0x9EB2, 0xC63E, 0x9EB3, 0xC63F, 0x9EB4,	0xC640, 0xBFCD, 0xC641, 0xBFCE, 0xC642, 0x9EB5, 0xC643, 0x9EB6,
+	0xC644, 0xBFCF, 0xC645, 0x9EB7, 0xC646, 0x9EB8, 0xC647, 0x9EB9,	0xC648, 0xBFD0, 0xC649, 0x9EBA, 0xC64A, 0x9EBB, 0xC64B, 0x9EBC,
+	0xC64C, 0x9EBD, 0xC64D, 0x9EBE, 0xC64E, 0x9EBF, 0xC64F, 0x9EC0,	0xC650, 0xBFD1, 0xC651, 0xBFD2, 0xC652, 0x9EC1, 0xC653, 0xBFD3,
+	0xC654, 0xBFD4, 0xC655, 0xBFD5, 0xC656, 0x9EC2, 0xC657, 0x9EC3,	0xC658, 0x9EC4, 0xC659, 0x9EC5, 0xC65A, 0x9EC6, 0xC65B, 0x9EC7,
+	0xC65C, 0xBFD6, 0xC65D, 0xBFD7, 0xC65E, 0x9EC8, 0xC65F, 0x9EC9,	0xC660, 0xBFD8, 0xC661, 0x9ECA, 0xC662, 0x9ECB, 0xC663, 0x9ECC,
+	0xC664, 0x9ECD, 0xC665, 0x9ECE, 0xC666, 0x9ECF, 0xC667, 0x9ED0,	0xC668, 0x9ED1, 0xC669, 0x9ED2, 0xC66A, 0x9ED3, 0xC66B, 0x9ED4,
+	0xC66C, 0xBFD9, 0xC66D, 0x9ED5, 0xC66E, 0x9ED6, 0xC66F, 0xBFDA,	0xC670, 0x9ED7, 0xC671, 0xBFDB, 0xC672, 0x9ED8, 0xC673, 0x9ED9,
+	0xC674, 0x9EDA, 0xC675, 0x9EDB, 0xC676, 0x9EDC, 0xC677, 0x9EDD,	0xC678, 0xBFDC, 0xC679, 0xBFDD, 0xC67A, 0x9EDE, 0xC67B, 0x9EDF,
+	0xC67C, 0xBFDE, 0xC67D, 0x9EE0, 0xC67E, 0x9EE1, 0xC67F, 0x9EE2,	0xC680, 0xBFDF, 0xC681, 0x9EE3, 0xC682, 0x9EE4, 0xC683, 0x9EE5,
+	0xC684, 0x9EE6, 0xC685, 0x9EE7, 0xC686, 0x9EE8, 0xC687, 0x9EE9,	0xC688, 0xBFE0, 0xC689, 0xBFE1, 0xC68A, 0x9EEA, 0xC68B, 0xBFE2,
+	0xC68C, 0x9EEB, 0xC68D, 0xBFE3, 0xC68E, 0x9EEC, 0xC68F, 0x9EED,	0xC690, 0x9EEE, 0xC691, 0x9EEF, 0xC692, 0x9EF0, 0xC693, 0x9EF1,
+	0xC694, 0xBFE4, 0xC695, 0xBFE5, 0xC696, 0x9EF2, 0xC697, 0x9EF3,	0xC698, 0xBFE6, 0xC699, 0x9EF4, 0xC69A, 0x9EF5, 0xC69B, 0x9EF6,
+	0xC69C, 0xBFE7, 0xC69D, 0x9EF7, 0xC69E, 0x9EF8, 0xC69F, 0x9EF9,	0xC6A0, 0x9EFA, 0xC6A1, 0x9EFB, 0xC6A2, 0x9EFC, 0xC6A3, 0x9EFD,
+	0xC6A4, 0xBFE8, 0xC6A5, 0xBFE9, 0xC6A6, 0x9EFE, 0xC6A7, 0xBFEA,	0xC6A8, 0x9F41, 0xC6A9, 0xBFEB, 0xC6AA, 0x9F42, 0xC6AB, 0x9F43,
+	0xC6AC, 0x9F44, 0xC6AD, 0x9F45, 0xC6AE, 0x9F46, 0xC6AF, 0x9F47,	0xC6B0, 0xBFEC, 0xC6B1, 0xBFED, 0xC6B2, 0x9F48, 0xC6B3, 0x9F49,
+	0xC6B4, 0xBFEE, 0xC6B5, 0x9F4A, 0xC6B6, 0x9F4B, 0xC6B7, 0x9F4C,	0xC6B8, 0xBFEF, 0xC6B9, 0xBFF0, 0xC6BA, 0xBFF1, 0xC6BB, 0x9F4D,
+	0xC6BC, 0x9F4E, 0xC6BD, 0x9F4F, 0xC6BE, 0x9F50, 0xC6BF, 0x9F51,	0xC6C0, 0xBFF2, 0xC6C1, 0xBFF3, 0xC6C2, 0x9F52, 0xC6C3, 0xBFF4,
+	0xC6C4, 0x9F53, 0xC6C5, 0xBFF5, 0xC6C6, 0x9F54, 0xC6C7, 0x9F55,	0xC6C8, 0x9F56, 0xC6C9, 0x9F57, 0xC6CA, 0x9F58, 0xC6CB, 0x9F59,
+	0xC6CC, 0xBFF6, 0xC6CD, 0xBFF7, 0xC6CE, 0x9F5A, 0xC6CF, 0x9F61,	0xC6D0, 0xBFF8, 0xC6D1, 0x9F62, 0xC6D2, 0x9F63, 0xC6D3, 0x9F64,
+	0xC6D4, 0xBFF9, 0xC6D5, 0x9F65, 0xC6D6, 0x9F66, 0xC6D7, 0x9F67,	0xC6D8, 0x9F68, 0xC6D9, 0x9F69, 0xC6DA, 0x9F6A, 0xC6DB, 0x9F6B,
+	0xC6DC, 0xBFFA, 0xC6DD, 0xBFFB, 0xC6DE, 0x9F6C, 0xC6DF, 0x9F6D,	0xC6E0, 0xBFFC, 0xC6E1, 0xBFFD, 0xC6E2, 0x9F6E, 0xC6E3, 0x9F6F,
+	0xC6E4, 0x9F70, 0xC6E5, 0x9F71, 0xC6E6, 0x9F72, 0xC6E7, 0x9F73,	0xC6E8, 0xBFFE, 0xC6E9, 0xC0A1, 0xC6EA, 0x9F74, 0xC6EB, 0x9F75,
+	0xC6EC, 0xC0A2, 0xC6ED, 0x9F76, 0xC6EE, 0x9F77, 0xC6EF, 0x9F78,	0xC6F0, 0xC0A3, 0xC6F1, 0x9F79, 0xC6F2, 0x9F7A, 0xC6F3, 0x9F81,
+	0xC6F4, 0x9F82, 0xC6F5, 0x9F83, 0xC6F6, 0x9F84, 0xC6F7, 0x9F85,	0xC6F8, 0xC0A4, 0xC6F9, 0xC0A5, 0xC6FA, 0x9F86, 0xC6FB, 0x9F87,
+	0xC6FC, 0x9F88, 0xC6FD, 0xC0A6, 0xC6FE, 0x9F89, 0xC6FF, 0x9F8A,	0xC700, 0x9F8B, 0xC701, 0x9F8C, 0xC702, 0x9F8D, 0xC703, 0x9F8E,
+	0xC704, 0xC0A7, 0xC705, 0xC0A8, 0xC706, 0x9F8F, 0xC707, 0x9F90,	0xC708, 0xC0A9, 0xC709, 0x9F91, 0xC70A, 0x9F92, 0xC70B, 0x9F93,
+	0xC70C, 0xC0AA, 0xC70D, 0x9F94, 0xC70E, 0x9F95, 0xC70F, 0x9F96,	0xC710, 0x9F97, 0xC711, 0x9F98, 0xC712, 0x9F99, 0xC713, 0x9F9A,
+	0xC714, 0xC0AB, 0xC715, 0xC0AC, 0xC716, 0x9F9B, 0xC717, 0xC0AD,	0xC718, 0x9F9C, 0xC719, 0xC0AE, 0xC71A, 0x9F9D, 0xC71B, 0x9F9E,
+	0xC71C, 0x9F9F, 0xC71D, 0x9FA0, 0xC71E, 0x9FA1, 0xC71F, 0x9FA2,	0xC720, 0xC0AF, 0xC721, 0xC0B0, 0xC722, 0x9FA3, 0xC723, 0x9FA4,
+	0xC724, 0xC0B1, 0xC725, 0x9FA5, 0xC726, 0x9FA6, 0xC727, 0x9FA7,	0xC728, 0xC0B2, 0xC729, 0x9FA8, 0xC72A, 0x9FA9, 0xC72B, 0x9FAA,
+	0xC72C, 0x9FAB, 0xC72D, 0x9FAC, 0xC72E, 0x9FAD, 0xC72F, 0x9FAE,	0xC730, 0xC0B3, 0xC731, 0xC0B4, 0xC732, 0x9FAF, 0xC733, 0xC0B5,
+	0xC734, 0x9FB0, 0xC735, 0xC0B6, 0xC736, 0x9FB1, 0xC737, 0xC0B7,	0xC738, 0x9FB2, 0xC739, 0x9FB3, 0xC73A, 0x9FB4, 0xC73B, 0x9FB5,
+	0xC73C, 0xC0B8, 0xC73D, 0xC0B9, 0xC73E, 0x9FB6, 0xC73F, 0x9FB7,	0xC740, 0xC0BA, 0xC741, 0x9FB8, 0xC742, 0x9FB9, 0xC743, 0x9FBA,
+	0xC744, 0xC0BB, 0xC745, 0x9FBB, 0xC746, 0x9FBC, 0xC747, 0x9FBD,	0xC748, 0x9FBE, 0xC749, 0x9FBF, 0xC74A, 0xC0BC, 0xC74B, 0x9FC0,
+	0xC74C, 0xC0BD, 0xC74D, 0xC0BE, 0xC74E, 0x9FC1, 0xC74F, 0xC0BF,	0xC750, 0x9FC2, 0xC751, 0xC0C0, 0xC752, 0xC0C1, 0xC753, 0xC0C2,
+	0xC754, 0xC0C3, 0xC755, 0xC0C4, 0xC756, 0xC0C5, 0xC757, 0xC0C6,	0xC758, 0xC0C7, 0xC759, 0x9FC3, 0xC75A, 0x9FC4, 0xC75B, 0x9FC5,
+	0xC75C, 0xC0C8, 0xC75D, 0x9FC6, 0xC75E, 0x9FC7, 0xC75F, 0x9FC8,	0xC760, 0xC0C9, 0xC761, 0x9FC9, 0xC762, 0x9FCA, 0xC763, 0x9FCB,
+	0xC764, 0x9FCC, 0xC765, 0x9FCD, 0xC766, 0x9FCE, 0xC767, 0x9FCF,	0xC768, 0xC0CA, 0xC769, 0x9FD0, 0xC76A, 0x9FD1, 0xC76B, 0xC0CB,
+	0xC76C, 0x9FD2, 0xC76D, 0x9FD3, 0xC76E, 0x9FD4, 0xC76F, 0x9FD5,	0xC770, 0x9FD6, 0xC771, 0x9FD7, 0xC772, 0x9FD8, 0xC773, 0x9FD9,
+	0xC774, 0xC0CC, 0xC775, 0xC0CD, 0xC776, 0x9FDA, 0xC777, 0x9FDB,	0xC778, 0xC0CE, 0xC779, 0x9FDC, 0xC77A, 0x9FDD, 0xC77B, 0x9FDE,
+	0xC77C, 0xC0CF, 0xC77D, 0xC0D0, 0xC77E, 0xC0D1, 0xC77F, 0x9FDF,	0xC780, 0x9FE0, 0xC781, 0x9FE1, 0xC782, 0x9FE2, 0xC783, 0xC0D2,
+	0xC784, 0xC0D3, 0xC785, 0xC0D4, 0xC786, 0x9FE3, 0xC787, 0xC0D5,	0xC788, 0xC0D6, 0xC789, 0xC0D7, 0xC78A, 0xC0D8, 0xC78B, 0x9FE4,
+	0xC78C, 0x9FE5, 0xC78D, 0x9FE6, 0xC78E, 0xC0D9, 0xC78F, 0x9FE7,	0xC790, 0xC0DA, 0xC791, 0xC0DB, 0xC792, 0x9FE8, 0xC793, 0x9FE9,
+	0xC794, 0xC0DC, 0xC795, 0x9FEA, 0xC796, 0xC0DD, 0xC797, 0xC0DE,	0xC798, 0xC0DF, 0xC799, 0x9FEB, 0xC79A, 0xC0E0, 0xC79B, 0x9FEC,
+	0xC79C, 0x9FED, 0xC79D, 0x9FEE, 0xC79E, 0x9FEF, 0xC79F, 0x9FF0,	0xC7A0, 0xC0E1, 0xC7A1, 0xC0E2, 0xC7A2, 0x9FF1, 0xC7A3, 0xC0E3,
+	0xC7A4, 0xC0E4, 0xC7A5, 0xC0E5, 0xC7A6, 0xC0E6, 0xC7A7, 0x9FF2,	0xC7A8, 0x9FF3, 0xC7A9, 0x9FF4, 0xC7AA, 0x9FF5, 0xC7AB, 0x9FF6,
+	0xC7AC, 0xC0E7, 0xC7AD, 0xC0E8, 0xC7AE, 0x9FF7, 0xC7AF, 0x9FF8,	0xC7B0, 0xC0E9, 0xC7B1, 0x9FF9, 0xC7B2, 0x9FFA, 0xC7B3, 0x9FFB,
+	0xC7B4, 0xC0EA, 0xC7B5, 0x9FFC, 0xC7B6, 0x9FFD, 0xC7B7, 0x9FFE,	0xC7B8, 0xA041, 0xC7B9, 0xA042, 0xC7BA, 0xA043, 0xC7BB, 0xA044,
+	0xC7BC, 0xC0EB, 0xC7BD, 0xC0EC, 0xC7BE, 0xA045, 0xC7BF, 0xC0ED,	0xC7C0, 0xC0EE, 0xC7C1, 0xC0EF, 0xC7C2, 0xA046, 0xC7C3, 0xA047,
+	0xC7C4, 0xA048, 0xC7C5, 0xA049, 0xC7C6, 0xA04A, 0xC7C7, 0xA04B,	0xC7C8, 0xC0F0, 0xC7C9, 0xC0F1, 0xC7CA, 0xA04C, 0xC7CB, 0xA04D,
+	0xC7CC, 0xC0F2, 0xC7CD, 0xA04E, 0xC7CE, 0xC0F3, 0xC7CF, 0xA04F,	0xC7D0, 0xC0F4, 0xC7D1, 0xA050, 0xC7D2, 0xA051, 0xC7D3, 0xA052,
+	0xC7D4, 0xA053, 0xC7D5, 0xA054, 0xC7D6, 0xA055, 0xC7D7, 0xA056,	0xC7D8, 0xC0F5, 0xC7D9, 0xA057, 0xC7DA, 0xA058, 0xC7DB, 0xA059,
+	0xC7DC, 0xA05A, 0xC7DD, 0xC0F6, 0xC7DE, 0xA061, 0xC7DF, 0xA062,	0xC7E0, 0xA063, 0xC7E1, 0xA064, 0xC7E2, 0xA065, 0xC7E3, 0xA066,
+	0xC7E4, 0xC0F7, 0xC7E5, 0xA067, 0xC7E6, 0xA068, 0xC7E7, 0xA069,	0xC7E8, 0xC0F8, 0xC7E9, 0xA06A, 0xC7EA, 0xA06B, 0xC7EB, 0xA06C,
+	0xC7EC, 0xC0F9, 0xC7ED, 0xA06D, 0xC7EE, 0xA06E, 0xC7EF, 0xA06F,	0xC7F0, 0xA070, 0xC7F1, 0xA071, 0xC7F2, 0xA072, 0xC7F3, 0xA073,
+	0xC7F4, 0xA074, 0xC7F5, 0xA075, 0xC7F6, 0xA076, 0xC7F7, 0xA077,	0xC7F8, 0xA078, 0xC7F9, 0xA079, 0xC7FA, 0xA07A, 0xC7FB, 0xA081,
+	0xC7FC, 0xA082, 0xC7FD, 0xA083, 0xC7FE, 0xA084, 0xC7FF, 0xA085,	0xC800, 0xC0FA, 0xC801, 0xC0FB, 0xC802, 0xA086, 0xC803, 0xA087,
+	0xC804, 0xC0FC, 0xC805, 0xA088, 0xC806, 0xA089, 0xC807, 0xA08A,	0xC808, 0xC0FD, 0xC809, 0xA08B, 0xC80A, 0xC0FE, 0xC80B, 0xA08C,
+	0xC80C, 0xA08D, 0xC80D, 0xA08E, 0xC80E, 0xA08F, 0xC80F, 0xA090,	0xC810, 0xC1A1, 0xC811, 0xC1A2, 0xC812, 0xA091, 0xC813, 0xC1A3,
+	0xC814, 0xA092, 0xC815, 0xC1A4, 0xC816, 0xC1A5, 0xC817, 0xA093,	0xC818, 0xA094, 0xC819, 0xA095, 0xC81A, 0xA096, 0xC81B, 0xA097,
+	0xC81C, 0xC1A6, 0xC81D, 0xC1A7, 0xC81E, 0xA098, 0xC81F, 0xA099,	0xC820, 0xC1A8, 0xC821, 0xA09A, 0xC822, 0xA09B, 0xC823, 0xA09C,
+	0xC824, 0xC1A9, 0xC825, 0xA09D, 0xC826, 0xA09E, 0xC827, 0xA09F,	0xC828, 0xA0A0, 0xC829, 0xA0A1, 0xC82A, 0xA0A2, 0xC82B, 0xA0A3,
+	0xC82C, 0xC1AA, 0xC82D, 0xC1AB, 0xC82E, 0xA0A4, 0xC82F, 0xC1AC,	0xC830, 0xA0A5, 0xC831, 0xC1AD, 0xC832, 0xA0A6, 0xC833, 0xA0A7,
+	0xC834, 0xA0A8, 0xC835, 0xA0A9, 0xC836, 0xA0AA, 0xC837, 0xA0AB,	0xC838, 0xC1AE, 0xC839, 0xA0AC, 0xC83A, 0xA0AD, 0xC83B, 0xA0AE,
+	0xC83C, 0xC1AF, 0xC83D, 0xA0AF, 0xC83E, 0xA0B0, 0xC83F, 0xA0B1,	0xC840, 0xC1B0, 0xC841, 0xA0B2, 0xC842, 0xA0B3, 0xC843, 0xA0B4,
+	0xC844, 0xA0B5, 0xC845, 0xA0B6, 0xC846, 0xA0B7, 0xC847, 0xA0B8,	0xC848, 0xC1B1, 0xC849, 0xC1B2, 0xC84A, 0xA0B9, 0xC84B, 0xA0BA,
+	0xC84C, 0xC1B3, 0xC84D, 0xC1B4, 0xC84E, 0xA0BB, 0xC84F, 0xA0BC,	0xC850, 0xA0BD, 0xC851, 0xA0BE, 0xC852, 0xA0BF, 0xC853, 0xA0C0,
+	0xC854, 0xC1B5, 0xC855, 0xA0C1, 0xC856, 0xA0C2, 0xC857, 0xA0C3,	0xC858, 0xA0C4, 0xC859, 0xA0C5, 0xC85A, 0xA0C6, 0xC85B, 0xA0C7,
+	0xC85C, 0xA0C8, 0xC85D, 0xA0C9, 0xC85E, 0xA0CA, 0xC85F, 0xA0CB,	0xC860, 0xA0CC, 0xC861, 0xA0CD, 0xC862, 0xA0CE, 0xC863, 0xA0CF,
+	0xC864, 0xA0D0, 0xC865, 0xA0D1, 0xC866, 0xA0D2, 0xC867, 0xA0D3,	0xC868, 0xA0D4, 0xC869, 0xA0D5, 0xC86A, 0xA0D6, 0xC86B, 0xA0D7,
+	0xC86C, 0xA0D8, 0xC86D, 0xA0D9, 0xC86E, 0xA0DA, 0xC86F, 0xA0DB,	0xC870, 0xC1B6, 0xC871, 0xC1B7, 0xC872, 0xA0DC, 0xC873, 0xA0DD,
+	0xC874, 0xC1B8, 0xC875, 0xA0DE, 0xC876, 0xA0DF, 0xC877, 0xA0E0,	0xC878, 0xC1B9, 0xC879, 0xA0E1, 0xC87A, 0xC1BA, 0xC87B, 0xA0E2,
+	0xC87C, 0xA0E3, 0xC87D, 0xA0E4, 0xC87E, 0xA0E5, 0xC87F, 0xA0E6,	0xC880, 0xC1BB, 0xC881, 0xC1BC, 0xC882, 0xA0E7, 0xC883, 0xC1BD,
+	0xC884, 0xA0E8, 0xC885, 0xC1BE, 0xC886, 0xC1BF, 0xC887, 0xC1C0,	0xC888, 0xA0E9, 0xC889, 0xA0EA, 0xC88A, 0xA0EB, 0xC88B, 0xC1C1,
+	0xC88C, 0xC1C2, 0xC88D, 0xC1C3, 0xC88E, 0xA0EC, 0xC88F, 0xA0ED,	0xC890, 0xA0EE, 0xC891, 0xA0EF, 0xC892, 0xA0F0, 0xC893, 0xA0F1,
+	0xC894, 0xC1C4, 0xC895, 0xA0F2, 0xC896, 0xA0F3, 0xC897, 0xA0F4,	0xC898, 0xA0F5, 0xC899, 0xA0F6, 0xC89A, 0xA0F7, 0xC89B, 0xA0F8,
+	0xC89C, 0xA0F9, 0xC89D, 0xC1C5, 0xC89E, 0xA0FA, 0xC89F, 0xC1C6,	0xC8A0, 0xA0FB, 0xC8A1, 0xC1C7, 0xC8A2, 0xA0FC, 0xC8A3, 0xA0FD,
+	0xC8A4, 0xA0FE, 0xC8A5, 0xA141, 0xC8A6, 0xA142, 0xC8A7, 0xA143,	0xC8A8, 0xC1C8, 0xC8A9, 0xA144, 0xC8AA, 0xA145, 0xC8AB, 0xA146,
+	0xC8AC, 0xA147, 0xC8AD, 0xA148, 0xC8AE, 0xA149, 0xC8AF, 0xA14A,	0xC8B0, 0xA14B, 0xC8B1, 0xA14C, 0xC8B2, 0xA14D, 0xC8B3, 0xA14E,
+	0xC8B4, 0xA14F, 0xC8B5, 0xA150, 0xC8B6, 0xA151, 0xC8B7, 0xA152,	0xC8B8, 0xA153, 0xC8B9, 0xA154, 0xC8BA, 0xA155, 0xC8BB, 0xA156,
+	0xC8BC, 0xC1C9, 0xC8BD, 0xC1CA, 0xC8BE, 0xA157, 0xC8BF, 0xA158,	0xC8C0, 0xA159, 0xC8C1, 0xA15A, 0xC8C2, 0xA161, 0xC8C3, 0xA162,
+	0xC8C4, 0xC1CB, 0xC8C5, 0xA163, 0xC8C6, 0xA164, 0xC8C7, 0xA165,	0xC8C8, 0xC1CC, 0xC8C9, 0xA166, 0xC8CA, 0xA167, 0xC8CB, 0xA168,
+	0xC8CC, 0xC1CD, 0xC8CD, 0xA169, 0xC8CE, 0xA16A, 0xC8CF, 0xA16B,	0xC8D0, 0xA16C, 0xC8D1, 0xA16D, 0xC8D2, 0xA16E, 0xC8D3, 0xA16F,
+	0xC8D4, 0xC1CE, 0xC8D5, 0xC1CF, 0xC8D6, 0xA170, 0xC8D7, 0xC1D0,	0xC8D8, 0xA171, 0xC8D9, 0xC1D1, 0xC8DA, 0xA172, 0xC8DB, 0xA173,
+	0xC8DC, 0xA174, 0xC8DD, 0xA175, 0xC8DE, 0xA176, 0xC8DF, 0xA177,	0xC8E0, 0xC1D2, 0xC8E1, 0xC1D3, 0xC8E2, 0xA178, 0xC8E3, 0xA179,
+	0xC8E4, 0xC1D4, 0xC8E5, 0xA17A, 0xC8E6, 0xA181, 0xC8E7, 0xA182,	0xC8E8, 0xA183, 0xC8E9, 0xA184, 0xC8EA, 0xA185, 0xC8EB, 0xA186,
+	0xC8EC, 0xA187, 0xC8ED, 0xA188, 0xC8EE, 0xA189, 0xC8EF, 0xA18A,	0xC8F0, 0xA18B, 0xC8F1, 0xA18C, 0xC8F2, 0xA18D, 0xC8F3, 0xA18E,
+	0xC8F4, 0xA18F, 0xC8F5, 0xC1D5, 0xC8F6, 0xA190, 0xC8F7, 0xA191,	0xC8F8, 0xA192, 0xC8F9, 0xA193, 0xC8FA, 0xA194, 0xC8FB, 0xA195,
+	0xC8FC, 0xC1D6, 0xC8FD, 0xC1D7, 0xC8FE, 0xA196, 0xC8FF, 0xA197,	0xC900, 0xC1D8, 0xC901, 0xA198, 0xC902, 0xA199, 0xC903, 0xA19A,
+	0xC904, 0xC1D9, 0xC905, 0xC1DA, 0xC906, 0xC1DB, 0xC907, 0xA19B,	0xC908, 0xA19C, 0xC909, 0xA19D, 0xC90A, 0xA19E, 0xC90B, 0xA19F,
+	0xC90C, 0xC1DC, 0xC90D, 0xC1DD, 0xC90E, 0xA1A0, 0xC90F, 0xC1DE,	0xC910, 0xA241, 0xC911, 0xC1DF, 0xC912, 0xA242, 0xC913, 0xA243,
+	0xC914, 0xA244, 0xC915, 0xA245, 0xC916, 0xA246, 0xC917, 0xA247,	0xC918, 0xC1E0, 0xC919, 0xA248, 0xC91A, 0xA249, 0xC91B, 0xA24A,
+	0xC91C, 0xA24B, 0xC91D, 0xA24C, 0xC91E, 0xA24D, 0xC91F, 0xA24E,	0xC920, 0xA24F, 0xC921, 0xA250, 0xC922, 0xA251, 0xC923, 0xA252,
+	0xC924, 0xA253, 0xC925, 0xA254, 0xC926, 0xA255, 0xC927, 0xA256,	0xC928, 0xA257, 0xC929, 0xA258, 0xC92A, 0xA259, 0xC92B, 0xA25A,
+	0xC92C, 0xC1E1, 0xC92D, 0xA261, 0xC92E, 0xA262, 0xC92F, 0xA263,	0xC930, 0xA264, 0xC931, 0xA265, 0xC932, 0xA266, 0xC933, 0xA267,
+	0xC934, 0xC1E2, 0xC935, 0xA268, 0xC936, 0xA269, 0xC937, 0xA26A,	0xC938, 0xA26B, 0xC939, 0xA26C, 0xC93A, 0xA26D, 0xC93B, 0xA26E,
+	0xC93C, 0xA26F, 0xC93D, 0xA270, 0xC93E, 0xA271, 0xC93F, 0xA272,	0xC940, 0xA273, 0xC941, 0xA274, 0xC942, 0xA275, 0xC943, 0xA276,
+	0xC944, 0xA277, 0xC945, 0xA278, 0xC946, 0xA279, 0xC947, 0xA27A,	0xC948, 0xA281, 0xC949, 0xA282, 0xC94A, 0xA283, 0xC94B, 0xA284,
+	0xC94C, 0xA285, 0xC94D, 0xA286, 0xC94E, 0xA287, 0xC94F, 0xA288,	0xC950, 0xC1E3, 0xC951, 0xC1E4, 0xC952, 0xA289, 0xC953, 0xA28A,
+	0xC954, 0xC1E5, 0xC955, 0xA28B, 0xC956, 0xA28C, 0xC957, 0xA28D,	0xC958, 0xC1E6, 0xC959, 0xA28E, 0xC95A, 0xA28F, 0xC95B, 0xA290,
+	0xC95C, 0xA291, 0xC95D, 0xA292, 0xC95E, 0xA293, 0xC95F, 0xA294,	0xC960, 0xC1E7, 0xC961, 0xC1E8, 0xC962, 0xA295, 0xC963, 0xC1E9,
+	0xC964, 0xA296, 0xC965, 0xA297, 0xC966, 0xA298, 0xC967, 0xA299,	0xC968, 0xA29A, 0xC969, 0xA29B, 0xC96A, 0xA29C, 0xC96B, 0xA29D,
+	0xC96C, 0xC1EA, 0xC96D, 0xA29E, 0xC96E, 0xA29F, 0xC96F, 0xA2A0,	0xC970, 0xC1EB, 0xC971, 0xA341, 0xC972, 0xA342, 0xC973, 0xA343,
+	0xC974, 0xC1EC, 0xC975, 0xA344, 0xC976, 0xA345, 0xC977, 0xA346,	0xC978, 0xA347, 0xC979, 0xA348, 0xC97A, 0xA349, 0xC97B, 0xA34A,
+	0xC97C, 0xC1ED, 0xC97D, 0xA34B, 0xC97E, 0xA34C, 0xC97F, 0xA34D,	0xC980, 0xA34E, 0xC981, 0xA34F, 0xC982, 0xA350, 0xC983, 0xA351,
+	0xC984, 0xA352, 0xC985, 0xA353, 0xC986, 0xA354, 0xC987, 0xA355,	0xC988, 0xC1EE, 0xC989, 0xC1EF, 0xC98A, 0xA356, 0xC98B, 0xA357,
+	0xC98C, 0xC1F0, 0xC98D, 0xA358, 0xC98E, 0xA359, 0xC98F, 0xA35A,	0xC990, 0xC1F1, 0xC991, 0xA361, 0xC992, 0xA362, 0xC993, 0xA363,
+	0xC994, 0xA364, 0xC995, 0xA365, 0xC996, 0xA366, 0xC997, 0xA367,	0xC998, 0xC1F2, 0xC999, 0xC1F3, 0xC99A, 0xA368, 0xC99B, 0xC1F4,
+	0xC99C, 0xA369, 0xC99D, 0xC1F5, 0xC99E, 0xA36A, 0xC99F, 0xA36B,	0xC9A0, 0xA36C, 0xC9A1, 0xA36D, 0xC9A2, 0xA36E, 0xC9A3, 0xA36F,
+	0xC9A4, 0xA370, 0xC9A5, 0xA371, 0xC9A6, 0xA372, 0xC9A7, 0xA373,	0xC9A8, 0xA374, 0xC9A9, 0xA375, 0xC9AA, 0xA376, 0xC9AB, 0xA377,
+	0xC9AC, 0xA378, 0xC9AD, 0xA379, 0xC9AE, 0xA37A, 0xC9AF, 0xA381,	0xC9B0, 0xA382, 0xC9B1, 0xA383, 0xC9B2, 0xA384, 0xC9B3, 0xA385,
+	0xC9B4, 0xA386, 0xC9B5, 0xA387, 0xC9B6, 0xA388, 0xC9B7, 0xA389,	0xC9B8, 0xA38A, 0xC9B9, 0xA38B, 0xC9BA, 0xA38C, 0xC9BB, 0xA38D,
+	0xC9BC, 0xA38E, 0xC9BD, 0xA38F, 0xC9BE, 0xA390, 0xC9BF, 0xA391,	0xC9C0, 0xC1F6, 0xC9C1, 0xC1F7, 0xC9C2, 0xA392, 0xC9C3, 0xA393,
+	0xC9C4, 0xC1F8, 0xC9C5, 0xA394, 0xC9C6, 0xA395, 0xC9C7, 0xC1F9,	0xC9C8, 0xC1FA, 0xC9C9, 0xA396, 0xC9CA, 0xC1FB, 0xC9CB, 0xA397,
+	0xC9CC, 0xA398, 0xC9CD, 0xA399, 0xC9CE, 0xA39A, 0xC9CF, 0xA39B,	0xC9D0, 0xC1FC, 0xC9D1, 0xC1FD, 0xC9D2, 0xA39C, 0xC9D3, 0xC1FE,
+	0xC9D4, 0xA39D, 0xC9D5, 0xC2A1, 0xC9D6, 0xC2A2, 0xC9D7, 0xA39E,	0xC9D8, 0xA39F, 0xC9D9, 0xC2A3, 0xC9DA, 0xC2A4, 0xC9DB, 0xA3A0,
+	0xC9DC, 0xC2A5, 0xC9DD, 0xC2A6, 0xC9DE, 0xA441, 0xC9DF, 0xA442,	0xC9E0, 0xC2A7, 0xC9E1, 0xA443, 0xC9E2, 0xC2A8, 0xC9E3, 0xA444,
+	0xC9E4, 0xC2A9, 0xC9E5, 0xA445, 0xC9E6, 0xA446, 0xC9E7, 0xC2AA,	0xC9E8, 0xA447, 0xC9E9, 0xA448, 0xC9EA, 0xA449, 0xC9EB, 0xA44A,
+	0xC9EC, 0xC2AB, 0xC9ED, 0xC2AC, 0xC9EE, 0xA44B, 0xC9EF, 0xC2AD,	0xC9F0, 0xC2AE, 0xC9F1, 0xC2AF, 0xC9F2, 0xA44C, 0xC9F3, 0xA44D,
+	0xC9F4, 0xA44E, 0xC9F5, 0xA44F, 0xC9F6, 0xA450, 0xC9F7, 0xA451,	0xC9F8, 0xC2B0, 0xC9F9, 0xC2B1, 0xC9FA, 0xA452, 0xC9FB, 0xA453,
+	0xC9FC, 0xC2B2, 0xC9FD, 0xA454, 0xC9FE, 0xA455, 0xC9FF, 0xA456,	0xCA00, 0xC2B3, 0xCA01, 0xA457, 0xCA02, 0xA458, 0xCA03, 0xA459,
+	0xCA04, 0xA45A, 0xCA05, 0xA461, 0xCA06, 0xA462, 0xCA07, 0xA463,	0xCA08, 0xC2B4, 0xCA09, 0xC2B5, 0xCA0A, 0xA464, 0xCA0B, 0xC2B6,
+	0xCA0C, 0xC2B7, 0xCA0D, 0xC2B8, 0xCA0E, 0xA465, 0xCA0F, 0xA466,	0xCA10, 0xA467, 0xCA11, 0xA468, 0xCA12, 0xA469, 0xCA13, 0xA46A,
+	0xCA14, 0xC2B9, 0xCA15, 0xA46B, 0xCA16, 0xA46C, 0xCA17, 0xA46D,	0xCA18, 0xC2BA, 0xCA19, 0xA46E, 0xCA1A, 0xA46F, 0xCA1B, 0xA470,
+	0xCA1C, 0xA471, 0xCA1D, 0xA472, 0xCA1E, 0xA473, 0xCA1F, 0xA474,	0xCA20, 0xA475, 0xCA21, 0xA476, 0xCA22, 0xA477, 0xCA23, 0xA478,
+	0xCA24, 0xA479, 0xCA25, 0xA47A, 0xCA26, 0xA481, 0xCA27, 0xA482,	0xCA28, 0xA483, 0xCA29, 0xC2BB, 0xCA2A, 0xA484, 0xCA2B, 0xA485,
+	0xCA2C, 0xA486, 0xCA2D, 0xA487, 0xCA2E, 0xA488, 0xCA2F, 0xA489,	0xCA30, 0xA48A, 0xCA31, 0xA48B, 0xCA32, 0xA48C, 0xCA33, 0xA48D,
+	0xCA34, 0xA48E, 0xCA35, 0xA48F, 0xCA36, 0xA490, 0xCA37, 0xA491,	0xCA38, 0xA492, 0xCA39, 0xA493, 0xCA3A, 0xA494, 0xCA3B, 0xA495,
+	0xCA3C, 0xA496, 0xCA3D, 0xA497, 0xCA3E, 0xA498, 0xCA3F, 0xA499,	0xCA40, 0xA49A, 0xCA41, 0xA49B, 0xCA42, 0xA49C, 0xCA43, 0xA49D,
+	0xCA44, 0xA49E, 0xCA45, 0xA49F, 0xCA46, 0xA4A0, 0xCA47, 0xA541,	0xCA48, 0xA542, 0xCA49, 0xA543, 0xCA4A, 0xA544, 0xCA4B, 0xA545,
+	0xCA4C, 0xC2BC, 0xCA4D, 0xC2BD, 0xCA4E, 0xA546, 0xCA4F, 0xA547,	0xCA50, 0xC2BE, 0xCA51, 0xA548, 0xCA52, 0xA549, 0xCA53, 0xA54A,
+	0xCA54, 0xC2BF, 0xCA55, 0xA54B, 0xCA56, 0xA54C, 0xCA57, 0xA54D,	0xCA58, 0xA54E, 0xCA59, 0xA54F, 0xCA5A, 0xA550, 0xCA5B, 0xA551,
+	0xCA5C, 0xC2C0, 0xCA5D, 0xC2C1, 0xCA5E, 0xA552, 0xCA5F, 0xC2C2,	0xCA60, 0xC2C3, 0xCA61, 0xC2C4, 0xCA62, 0xA553, 0xCA63, 0xA554,
+	0xCA64, 0xA555, 0xCA65, 0xA556, 0xCA66, 0xA557, 0xCA67, 0xA558,	0xCA68, 0xC2C5, 0xCA69, 0xA559, 0xCA6A, 0xA55A, 0xCA6B, 0xA561,
+	0xCA6C, 0xA562, 0xCA6D, 0xA563, 0xCA6E, 0xA564, 0xCA6F, 0xA565,	0xCA70, 0xA566, 0xCA71, 0xA567, 0xCA72, 0xA568, 0xCA73, 0xA569,
+	0xCA74, 0xA56A, 0xCA75, 0xA56B, 0xCA76, 0xA56C, 0xCA77, 0xA56D,	0xCA78, 0xA56E, 0xCA79, 0xA56F, 0xCA7A, 0xA570, 0xCA7B, 0xA571,
+	0xCA7C, 0xA572, 0xCA7D, 0xC2C6, 0xCA7E, 0xA573, 0xCA7F, 0xA574,	0xCA80, 0xA575, 0xCA81, 0xA576, 0xCA82, 0xA577, 0xCA83, 0xA578,
+	0xCA84, 0xC2C7, 0xCA85, 0xA579, 0xCA86, 0xA57A, 0xCA87, 0xA581,	0xCA88, 0xA582, 0xCA89, 0xA583, 0xCA8A, 0xA584, 0xCA8B, 0xA585,
+	0xCA8C, 0xA586, 0xCA8D, 0xA587, 0xCA8E, 0xA588, 0xCA8F, 0xA589,	0xCA90, 0xA58A, 0xCA91, 0xA58B, 0xCA92, 0xA58C, 0xCA93, 0xA58D,
+	0xCA94, 0xA58E, 0xCA95, 0xA58F, 0xCA96, 0xA590, 0xCA97, 0xA591,	0xCA98, 0xC2C8, 0xCA99, 0xA592, 0xCA9A, 0xA593, 0xCA9B, 0xA594,
+	0xCA9C, 0xA595, 0xCA9D, 0xA596, 0xCA9E, 0xA597, 0xCA9F, 0xA598,	0xCAA0, 0xA599, 0xCAA1, 0xA59A, 0xCAA2, 0xA59B, 0xCAA3, 0xA59C,
+	0xCAA4, 0xA59D, 0xCAA5, 0xA59E, 0xCAA6, 0xA59F, 0xCAA7, 0xA5A0,	0xCAA8, 0xA641, 0xCAA9, 0xA642, 0xCAAA, 0xA643, 0xCAAB, 0xA644,
+	0xCAAC, 0xA645, 0xCAAD, 0xA646, 0xCAAE, 0xA647, 0xCAAF, 0xA648,	0xCAB0, 0xA649, 0xCAB1, 0xA64A, 0xCAB2, 0xA64B, 0xCAB3, 0xA64C,
+	0xCAB4, 0xA64D, 0xCAB5, 0xA64E, 0xCAB6, 0xA64F, 0xCAB7, 0xA650,	0xCAB8, 0xA651, 0xCAB9, 0xA652, 0xCABA, 0xA653, 0xCABB, 0xA654,
+	0xCABC, 0xC2C9, 0xCABD, 0xC2CA, 0xCABE, 0xA655, 0xCABF, 0xA656,	0xCAC0, 0xC2CB, 0xCAC1, 0xA657, 0xCAC2, 0xA658, 0xCAC3, 0xA659,
+	0xCAC4, 0xC2CC, 0xCAC5, 0xA65A, 0xCAC6, 0xA661, 0xCAC7, 0xA662,	0xCAC8, 0xA663, 0xCAC9, 0xA664, 0xCACA, 0xA665, 0xCACB, 0xA666,
+	0xCACC, 0xC2CD, 0xCACD, 0xC2CE, 0xCACE, 0xA667, 0xCACF, 0xC2CF,	0xCAD0, 0xA668, 0xCAD1, 0xC2D0, 0xCAD2, 0xA669, 0xCAD3, 0xC2D1,
+	0xCAD4, 0xA66A, 0xCAD5, 0xA66B, 0xCAD6, 0xA66C, 0xCAD7, 0xA66D,	0xCAD8, 0xC2D2, 0xCAD9, 0xC2D3, 0xCADA, 0xA66E, 0xCADB, 0xA66F,
+	0xCADC, 0xA670, 0xCADD, 0xA671, 0xCADE, 0xA672, 0xCADF, 0xA673,	0xCAE0, 0xC2D4, 0xCAE1, 0xA674, 0xCAE2, 0xA675, 0xCAE3, 0xA676,
+	0xCAE4, 0xA677, 0xCAE5, 0xA678, 0xCAE6, 0xA679, 0xCAE7, 0xA67A,	0xCAE8, 0xA681, 0xCAE9, 0xA682, 0xCAEA, 0xA683, 0xCAEB, 0xA684,
+	0xCAEC, 0xC2D5, 0xCAED, 0xA685, 0xCAEE, 0xA686, 0xCAEF, 0xA687,	0xCAF0, 0xA688, 0xCAF1, 0xA689, 0xCAF2, 0xA68A, 0xCAF3, 0xA68B,
+	0xCAF4, 0xC2D6, 0xCAF5, 0xA68C, 0xCAF6, 0xA68D, 0xCAF7, 0xA68E,	0xCAF8, 0xA68F, 0xCAF9, 0xA690, 0xCAFA, 0xA691, 0xCAFB, 0xA692,
+	0xCAFC, 0xA693, 0xCAFD, 0xA694, 0xCAFE, 0xA695, 0xCAFF, 0xA696,	0xCB00, 0xA697, 0xCB01, 0xA698, 0xCB02, 0xA699, 0xCB03, 0xA69A,
+	0xCB04, 0xA69B, 0xCB05, 0xA69C, 0xCB06, 0xA69D, 0xCB07, 0xA69E,	0xCB08, 0xC2D7, 0xCB09, 0xA69F, 0xCB0A, 0xA6A0, 0xCB0B, 0xA741,
+	0xCB0C, 0xA742, 0xCB0D, 0xA743, 0xCB0E, 0xA744, 0xCB0F, 0xA745,	0xCB10, 0xC2D8, 0xCB11, 0xA746, 0xCB12, 0xA747, 0xCB13, 0xA748,
+	0xCB14, 0xC2D9, 0xCB15, 0xA749, 0xCB16, 0xA74A, 0xCB17, 0xA74B,	0xCB18, 0xC2DA, 0xCB19, 0xA74C, 0xCB1A, 0xA74D, 0xCB1B, 0xA74E,
+	0xCB1C, 0xA74F, 0xCB1D, 0xA750, 0xCB1E, 0xA751, 0xCB1F, 0xA752,	0xCB20, 0xC2DB, 0xCB21, 0xC2DC, 0xCB22, 0xA753, 0xCB23, 0xA754,
+	0xCB24, 0xA755, 0xCB25, 0xA756, 0xCB26, 0xA757, 0xCB27, 0xA758,	0xCB28, 0xA759, 0xCB29, 0xA75A, 0xCB2A, 0xA761, 0xCB2B, 0xA762,
+	0xCB2C, 0xA763, 0xCB2D, 0xA764, 0xCB2E, 0xA765, 0xCB2F, 0xA766,	0xCB30, 0xA767, 0xCB31, 0xA768, 0xCB32, 0xA769, 0xCB33, 0xA76A,
+	0xCB34, 0xA76B, 0xCB35, 0xA76C, 0xCB36, 0xA76D, 0xCB37, 0xA76E,	0xCB38, 0xA76F, 0xCB39, 0xA770, 0xCB3A, 0xA771, 0xCB3B, 0xA772,
+	0xCB3C, 0xA773, 0xCB3D, 0xA774, 0xCB3E, 0xA775, 0xCB3F, 0xA776,	0xCB40, 0xA777, 0xCB41, 0xC2DD, 0xCB42, 0xA778, 0xCB43, 0xA779,
+	0xCB44, 0xA77A, 0xCB45, 0xA781, 0xCB46, 0xA782, 0xCB47, 0xA783,	0xCB48, 0xC2DE, 0xCB49, 0xC2DF, 0xCB4A, 0xA784, 0xCB4B, 0xA785,
+	0xCB4C, 0xC2E0, 0xCB4D, 0xA786, 0xCB4E, 0xA787, 0xCB4F, 0xA788,	0xCB50, 0xC2E1, 0xCB51, 0xA789, 0xCB52, 0xA78A, 0xCB53, 0xA78B,
+	0xCB54, 0xA78C, 0xCB55, 0xA78D, 0xCB56, 0xA78E, 0xCB57, 0xA78F,	0xCB58, 0xC2E2, 0xCB59, 0xC2E3, 0xCB5A, 0xA790, 0xCB5B, 0xA791,
+	0xCB5C, 0xA792, 0xCB5D, 0xC2E4, 0xCB5E, 0xA793, 0xCB5F, 0xA794,	0xCB60, 0xA795, 0xCB61, 0xA796, 0xCB62, 0xA797, 0xCB63, 0xA798,
+	0xCB64, 0xC2E5, 0xCB65, 0xA799, 0xCB66, 0xA79A, 0xCB67, 0xA79B,	0xCB68, 0xA79C, 0xCB69, 0xA79D, 0xCB6A, 0xA79E, 0xCB6B, 0xA79F,
+	0xCB6C, 0xA7A0, 0xCB6D, 0xA841, 0xCB6E, 0xA842, 0xCB6F, 0xA843,	0xCB70, 0xA844, 0xCB71, 0xA845, 0xCB72, 0xA846, 0xCB73, 0xA847,
+	0xCB74, 0xA848, 0xCB75, 0xA849, 0xCB76, 0xA84A, 0xCB77, 0xA84B,	0xCB78, 0xC2E6, 0xCB79, 0xC2E7, 0xCB7A, 0xA84C, 0xCB7B, 0xA84D,
+	0xCB7C, 0xA84E, 0xCB7D, 0xA84F, 0xCB7E, 0xA850, 0xCB7F, 0xA851,	0xCB80, 0xA852, 0xCB81, 0xA853, 0xCB82, 0xA854, 0xCB83, 0xA855,
+	0xCB84, 0xA856, 0xCB85, 0xA857, 0xCB86, 0xA858, 0xCB87, 0xA859,	0xCB88, 0xA85A, 0xCB89, 0xA861, 0xCB8A, 0xA862, 0xCB8B, 0xA863,
+	0xCB8C, 0xA864, 0xCB8D, 0xA865, 0xCB8E, 0xA866, 0xCB8F, 0xA867,	0xCB90, 0xA868, 0xCB91, 0xA869, 0xCB92, 0xA86A, 0xCB93, 0xA86B,
+	0xCB94, 0xA86C, 0xCB95, 0xA86D, 0xCB96, 0xA86E, 0xCB97, 0xA86F,	0xCB98, 0xA870, 0xCB99, 0xA871, 0xCB9A, 0xA872, 0xCB9B, 0xA873,
+	0xCB9C, 0xC2E8, 0xCB9D, 0xA874, 0xCB9E, 0xA875, 0xCB9F, 0xA876,	0xCBA0, 0xA877, 0xCBA1, 0xA878, 0xCBA2, 0xA879, 0xCBA3, 0xA87A,
+	0xCBA4, 0xA881, 0xCBA5, 0xA882, 0xCBA6, 0xA883, 0xCBA7, 0xA884,	0xCBA8, 0xA885, 0xCBA9, 0xA886, 0xCBAA, 0xA887, 0xCBAB, 0xA888,
+	0xCBAC, 0xA889, 0xCBAD, 0xA88A, 0xCBAE, 0xA88B, 0xCBAF, 0xA88C,	0xCBB0, 0xA88D, 0xCBB1, 0xA88E, 0xCBB2, 0xA88F, 0xCBB3, 0xA890,
+	0xCBB4, 0xA891, 0xCBB5, 0xA892, 0xCBB6, 0xA893, 0xCBB7, 0xA894,	0xCBB8, 0xC2E9, 0xCBB9, 0xA895, 0xCBBA, 0xA896, 0xCBBB, 0xA897,
+	0xCBBC, 0xA898, 0xCBBD, 0xA899, 0xCBBE, 0xA89A, 0xCBBF, 0xA89B,	0xCBC0, 0xA89C, 0xCBC1, 0xA89D, 0xCBC2, 0xA89E, 0xCBC3, 0xA89F,
+	0xCBC4, 0xA8A0, 0xCBC5, 0xA941, 0xCBC6, 0xA942, 0xCBC7, 0xA943,	0xCBC8, 0xA944, 0xCBC9, 0xA945, 0xCBCA, 0xA946, 0xCBCB, 0xA947,
+	0xCBCC, 0xA948, 0xCBCD, 0xA949, 0xCBCE, 0xA94A, 0xCBCF, 0xA94B,	0xCBD0, 0xA94C, 0xCBD1, 0xA94D, 0xCBD2, 0xA94E, 0xCBD3, 0xA94F,
+	0xCBD4, 0xC2EA, 0xCBD5, 0xA950, 0xCBD6, 0xA951, 0xCBD7, 0xA952,	0xCBD8, 0xA953, 0xCBD9, 0xA954, 0xCBDA, 0xA955, 0xCBDB, 0xA956,
+	0xCBDC, 0xA957, 0xCBDD, 0xA958, 0xCBDE, 0xA959, 0xCBDF, 0xA95A,	0xCBE0, 0xA961, 0xCBE1, 0xA962, 0xCBE2, 0xA963, 0xCBE3, 0xA964,
+	0xCBE4, 0xC2EB, 0xCBE5, 0xA965, 0xCBE6, 0xA966, 0xCBE7, 0xC2EC,	0xCBE8, 0xA967, 0xCBE9, 0xC2ED, 0xCBEA, 0xA968, 0xCBEB, 0xA969,
+	0xCBEC, 0xA96A, 0xCBED, 0xA96B, 0xCBEE, 0xA96C, 0xCBEF, 0xA96D,	0xCBF0, 0xA96E, 0xCBF1, 0xA96F, 0xCBF2, 0xA970, 0xCBF3, 0xA971,
+	0xCBF4, 0xA972, 0xCBF5, 0xA973, 0xCBF6, 0xA974, 0xCBF7, 0xA975,	0xCBF8, 0xA976, 0xCBF9, 0xA977, 0xCBFA, 0xA978, 0xCBFB, 0xA979,
+	0xCBFC, 0xA97A, 0xCBFD, 0xA981, 0xCBFE, 0xA982, 0xCBFF, 0xA983,	0xCC00, 0xA984, 0xCC01, 0xA985, 0xCC02, 0xA986, 0xCC03, 0xA987,
+	0xCC04, 0xA988, 0xCC05, 0xA989, 0xCC06, 0xA98A, 0xCC07, 0xA98B,	0xCC08, 0xA98C, 0xCC09, 0xA98D, 0xCC0A, 0xA98E, 0xCC0B, 0xA98F,
+	0xCC0C, 0xC2EE, 0xCC0D, 0xC2EF, 0xCC0E, 0xA990, 0xCC0F, 0xA991,	0xCC10, 0xC2F0, 0xCC11, 0xA992, 0xCC12, 0xA993, 0xCC13, 0xA994,
+	0xCC14, 0xC2F1, 0xCC15, 0xA995, 0xCC16, 0xA996, 0xCC17, 0xA997,	0xCC18, 0xA998, 0xCC19, 0xA999, 0xCC1A, 0xA99A, 0xCC1B, 0xA99B,
+	0xCC1C, 0xC2F2, 0xCC1D, 0xC2F3, 0xCC1E, 0xA99C, 0xCC1F, 0xA99D,	0xCC20, 0xA99E, 0xCC21, 0xC2F4, 0xCC22, 0xC2F5, 0xCC23, 0xA99F,
+	0xCC24, 0xA9A0, 0xCC25, 0xAA41, 0xCC26, 0xAA42, 0xCC27, 0xC2F6,	0xCC28, 0xC2F7, 0xCC29, 0xC2F8, 0xCC2A, 0xAA43, 0xCC2B, 0xAA44,
+	0xCC2C, 0xC2F9, 0xCC2D, 0xAA45, 0xCC2E, 0xC2FA, 0xCC2F, 0xAA46,	0xCC30, 0xC2FB, 0xCC31, 0xAA47, 0xCC32, 0xAA48, 0xCC33, 0xAA49,
+	0xCC34, 0xAA4A, 0xCC35, 0xAA4B, 0xCC36, 0xAA4C, 0xCC37, 0xAA4D,	0xCC38, 0xC2FC, 0xCC39, 0xC2FD, 0xCC3A, 0xAA4E, 0xCC3B, 0xC2FE,
+	0xCC3C, 0xC3A1, 0xCC3D, 0xC3A2, 0xCC3E, 0xC3A3, 0xCC3F, 0xAA4F,	0xCC40, 0xAA50, 0xCC41, 0xAA51, 0xCC42, 0xAA52, 0xCC43, 0xAA53,
+	0xCC44, 0xC3A4, 0xCC45, 0xC3A5, 0xCC46, 0xAA54, 0xCC47, 0xAA55,	0xCC48, 0xC3A6, 0xCC49, 0xAA56, 0xCC4A, 0xAA57, 0xCC4B, 0xAA58,
+	0xCC4C, 0xC3A7, 0xCC4D, 0xAA59, 0xCC4E, 0xAA5A, 0xCC4F, 0xAA61,	0xCC50, 0xAA62, 0xCC51, 0xAA63, 0xCC52, 0xAA64, 0xCC53, 0xAA65,
+	0xCC54, 0xC3A8, 0xCC55, 0xC3A9, 0xCC56, 0xAA66, 0xCC57, 0xC3AA,	0xCC58, 0xC3AB, 0xCC59, 0xC3AC, 0xCC5A, 0xAA67, 0xCC5B, 0xAA68,
+	0xCC5C, 0xAA69, 0xCC5D, 0xAA6A, 0xCC5E, 0xAA6B, 0xCC5F, 0xAA6C,	0xCC60, 0xC3AD, 0xCC61, 0xAA6D, 0xCC62, 0xAA6E, 0xCC63, 0xAA6F,
+	0xCC64, 0xC3AE, 0xCC65, 0xAA70, 0xCC66, 0xC3AF, 0xCC67, 0xAA71,	0xCC68, 0xC3B0, 0xCC69, 0xAA72, 0xCC6A, 0xAA73, 0xCC6B, 0xAA74,
+	0xCC6C, 0xAA75, 0xCC6D, 0xAA76, 0xCC6E, 0xAA77, 0xCC6F, 0xAA78,	0xCC70, 0xC3B1, 0xCC71, 0xAA79, 0xCC72, 0xAA7A, 0xCC73, 0xAA81,
+	0xCC74, 0xAA82, 0xCC75, 0xC3B2, 0xCC76, 0xAA83, 0xCC77, 0xAA84,	0xCC78, 0xAA85, 0xCC79, 0xAA86, 0xCC7A, 0xAA87, 0xCC7B, 0xAA88,
+	0xCC7C, 0xAA89, 0xCC7D, 0xAA8A, 0xCC7E, 0xAA8B, 0xCC7F, 0xAA8C,	0xCC80, 0xAA8D, 0xCC81, 0xAA8E, 0xCC82, 0xAA8F, 0xCC83, 0xAA90,
+	0xCC84, 0xAA91, 0xCC85, 0xAA92, 0xCC86, 0xAA93, 0xCC87, 0xAA94,	0xCC88, 0xAA95, 0xCC89, 0xAA96, 0xCC8A, 0xAA97, 0xCC8B, 0xAA98,
+	0xCC8C, 0xAA99, 0xCC8D, 0xAA9A, 0xCC8E, 0xAA9B, 0xCC8F, 0xAA9C,	0xCC90, 0xAA9D, 0xCC91, 0xAA9E, 0xCC92, 0xAA9F, 0xCC93, 0xAAA0,
+	0xCC94, 0xAB41, 0xCC95, 0xAB42, 0xCC96, 0xAB43, 0xCC97, 0xAB44,	0xCC98, 0xC3B3, 0xCC99, 0xC3B4, 0xCC9A, 0xAB45, 0xCC9B, 0xAB46,
+	0xCC9C, 0xC3B5, 0xCC9D, 0xAB47, 0xCC9E, 0xAB48, 0xCC9F, 0xAB49,	0xCCA0, 0xC3B6, 0xCCA1, 0xAB4A, 0xCCA2, 0xAB4B, 0xCCA3, 0xAB4C,
+	0xCCA4, 0xAB4D, 0xCCA5, 0xAB4E, 0xCCA6, 0xAB4F, 0xCCA7, 0xAB50,	0xCCA8, 0xC3B7, 0xCCA9, 0xC3B8, 0xCCAA, 0xAB51, 0xCCAB, 0xC3B9,
+	0xCCAC, 0xC3BA, 0xCCAD, 0xC3BB, 0xCCAE, 0xAB52, 0xCCAF, 0xAB53,	0xCCB0, 0xAB54, 0xCCB1, 0xAB55, 0xCCB2, 0xAB56, 0xCCB3, 0xAB57,
+	0xCCB4, 0xC3BC, 0xCCB5, 0xC3BD, 0xCCB6, 0xAB58, 0xCCB7, 0xAB59,	0xCCB8, 0xC3BE, 0xCCB9, 0xAB5A, 0xCCBA, 0xAB61, 0xCCBB, 0xAB62,
+	0xCCBC, 0xC3BF, 0xCCBD, 0xAB63, 0xCCBE, 0xAB64, 0xCCBF, 0xAB65,	0xCCC0, 0xAB66, 0xCCC1, 0xAB67, 0xCCC2, 0xAB68, 0xCCC3, 0xAB69,
+	0xCCC4, 0xC3C0, 0xCCC5, 0xC3C1, 0xCCC6, 0xAB6A, 0xCCC7, 0xC3C2,	0xCCC8, 0xAB6B, 0xCCC9, 0xC3C3, 0xCCCA, 0xAB6C, 0xCCCB, 0xAB6D,
+	0xCCCC, 0xAB6E, 0xCCCD, 0xAB6F, 0xCCCE, 0xAB70, 0xCCCF, 0xAB71,	0xCCD0, 0xC3C4, 0xCCD1, 0xAB72, 0xCCD2, 0xAB73, 0xCCD3, 0xAB74,
+	0xCCD4, 0xC3C5, 0xCCD5, 0xAB75, 0xCCD6, 0xAB76, 0xCCD7, 0xAB77,	0xCCD8, 0xAB78, 0xCCD9, 0xAB79, 0xCCDA, 0xAB7A, 0xCCDB, 0xAB81,
+	0xCCDC, 0xAB82, 0xCCDD, 0xAB83, 0xCCDE, 0xAB84, 0xCCDF, 0xAB85,	0xCCE0, 0xAB86, 0xCCE1, 0xAB87, 0xCCE2, 0xAB88, 0xCCE3, 0xAB89,
+	0xCCE4, 0xC3C6, 0xCCE5, 0xAB8A, 0xCCE6, 0xAB8B, 0xCCE7, 0xAB8C,	0xCCE8, 0xAB8D, 0xCCE9, 0xAB8E, 0xCCEA, 0xAB8F, 0xCCEB, 0xAB90,
+	0xCCEC, 0xC3C7, 0xCCED, 0xAB91, 0xCCEE, 0xAB92, 0xCCEF, 0xAB93,	0xCCF0, 0xC3C8, 0xCCF1, 0xAB94, 0xCCF2, 0xAB95, 0xCCF3, 0xAB96,
+	0xCCF4, 0xAB97, 0xCCF5, 0xAB98, 0xCCF6, 0xAB99, 0xCCF7, 0xAB9A,	0xCCF8, 0xAB9B, 0xCCF9, 0xAB9C, 0xCCFA, 0xAB9D, 0xCCFB, 0xAB9E,
+	0xCCFC, 0xAB9F, 0xCCFD, 0xABA0, 0xCCFE, 0xAC41, 0xCCFF, 0xAC42,	0xCD00, 0xAC43, 0xCD01, 0xC3C9, 0xCD02, 0xAC44, 0xCD03, 0xAC45,
+	0xCD04, 0xAC46, 0xCD05, 0xAC47, 0xCD06, 0xAC48, 0xCD07, 0xAC49,	0xCD08, 0xC3CA, 0xCD09, 0xC3CB, 0xCD0A, 0xAC4A, 0xCD0B, 0xAC4B,
+	0xCD0C, 0xC3CC, 0xCD0D, 0xAC4C, 0xCD0E, 0xAC4D, 0xCD0F, 0xAC4E,	0xCD10, 0xC3CD, 0xCD11, 0xAC4F, 0xCD12, 0xAC50, 0xCD13, 0xAC51,
+	0xCD14, 0xAC52, 0xCD15, 0xAC53, 0xCD16, 0xAC54, 0xCD17, 0xAC55,	0xCD18, 0xC3CE, 0xCD19, 0xC3CF, 0xCD1A, 0xAC56, 0xCD1B, 0xC3D0,
+	0xCD1C, 0xAC57, 0xCD1D, 0xC3D1, 0xCD1E, 0xAC58, 0xCD1F, 0xAC59,	0xCD20, 0xAC5A, 0xCD21, 0xAC61, 0xCD22, 0xAC62, 0xCD23, 0xAC63,
+	0xCD24, 0xC3D2, 0xCD25, 0xAC64, 0xCD26, 0xAC65, 0xCD27, 0xAC66,	0xCD28, 0xC3D3, 0xCD29, 0xAC67, 0xCD2A, 0xAC68, 0xCD2B, 0xAC69,
+	0xCD2C, 0xC3D4, 0xCD2D, 0xAC6A, 0xCD2E, 0xAC6B, 0xCD2F, 0xAC6C,	0xCD30, 0xAC6D, 0xCD31, 0xAC6E, 0xCD32, 0xAC6F, 0xCD33, 0xAC70,
+	0xCD34, 0xAC71, 0xCD35, 0xAC72, 0xCD36, 0xAC73, 0xCD37, 0xAC74,	0xCD38, 0xAC75, 0xCD39, 0xC3D5, 0xCD3A, 0xAC76, 0xCD3B, 0xAC77,
+	0xCD3C, 0xAC78, 0xCD3D, 0xAC79, 0xCD3E, 0xAC7A, 0xCD3F, 0xAC81,	0xCD40, 0xAC82, 0xCD41, 0xAC83, 0xCD42, 0xAC84, 0xCD43, 0xAC85,
+	0xCD44, 0xAC86, 0xCD45, 0xAC87, 0xCD46, 0xAC88, 0xCD47, 0xAC89,	0xCD48, 0xAC8A, 0xCD49, 0xAC8B, 0xCD4A, 0xAC8C, 0xCD4B, 0xAC8D,
+	0xCD4C, 0xAC8E, 0xCD4D, 0xAC8F, 0xCD4E, 0xAC90, 0xCD4F, 0xAC91,	0xCD50, 0xAC92, 0xCD51, 0xAC93, 0xCD52, 0xAC94, 0xCD53, 0xAC95,
+	0xCD54, 0xAC96, 0xCD55, 0xAC97, 0xCD56, 0xAC98, 0xCD57, 0xAC99,	0xCD58, 0xAC9A, 0xCD59, 0xAC9B, 0xCD5A, 0xAC9C, 0xCD5B, 0xAC9D,
+	0xCD5C, 0xC3D6, 0xCD5D, 0xAC9E, 0xCD5E, 0xAC9F, 0xCD5F, 0xACA0,	0xCD60, 0xC3D7, 0xCD61, 0xAD41, 0xCD62, 0xAD42, 0xCD63, 0xAD43,
+	0xCD64, 0xC3D8, 0xCD65, 0xAD44, 0xCD66, 0xAD45, 0xCD67, 0xAD46,	0xCD68, 0xAD47, 0xCD69, 0xAD48, 0xCD6A, 0xAD49, 0xCD6B, 0xAD4A,
+	0xCD6C, 0xC3D9, 0xCD6D, 0xC3DA, 0xCD6E, 0xAD4B, 0xCD6F, 0xC3DB,	0xCD70, 0xAD4C, 0xCD71, 0xC3DC, 0xCD72, 0xAD4D, 0xCD73, 0xAD4E,
+	0xCD74, 0xAD4F, 0xCD75, 0xAD50, 0xCD76, 0xAD51, 0xCD77, 0xAD52,	0xCD78, 0xC3DD, 0xCD79, 0xAD53, 0xCD7A, 0xAD54, 0xCD7B, 0xAD55,
+	0xCD7C, 0xAD56, 0xCD7D, 0xAD57, 0xCD7E, 0xAD58, 0xCD7F, 0xAD59,	0xCD80, 0xAD5A, 0xCD81, 0xAD61, 0xCD82, 0xAD62, 0xCD83, 0xAD63,
+	0xCD84, 0xAD64, 0xCD85, 0xAD65, 0xCD86, 0xAD66, 0xCD87, 0xAD67,	0xCD88, 0xC3DE, 0xCD89, 0xAD68, 0xCD8A, 0xAD69, 0xCD8B, 0xAD6A,
+	0xCD8C, 0xAD6B, 0xCD8D, 0xAD6C, 0xCD8E, 0xAD6D, 0xCD8F, 0xAD6E,	0xCD90, 0xAD6F, 0xCD91, 0xAD70, 0xCD92, 0xAD71, 0xCD93, 0xAD72,
+	0xCD94, 0xC3DF, 0xCD95, 0xC3E0, 0xCD96, 0xAD73, 0xCD97, 0xAD74,	0xCD98, 0xC3E1, 0xCD99, 0xAD75, 0xCD9A, 0xAD76, 0xCD9B, 0xAD77,
+	0xCD9C, 0xC3E2, 0xCD9D, 0xAD78, 0xCD9E, 0xAD79, 0xCD9F, 0xAD7A,	0xCDA0, 0xAD81, 0xCDA1, 0xAD82, 0xCDA2, 0xAD83, 0xCDA3, 0xAD84,
+	0xCDA4, 0xC3E3, 0xCDA5, 0xC3E4, 0xCDA6, 0xAD85, 0xCDA7, 0xC3E5,	0xCDA8, 0xAD86, 0xCDA9, 0xC3E6, 0xCDAA, 0xAD87, 0xCDAB, 0xAD88,
+	0xCDAC, 0xAD89, 0xCDAD, 0xAD8A, 0xCDAE, 0xAD8B, 0xCDAF, 0xAD8C,	0xCDB0, 0xC3E7, 0xCDB1, 0xAD8D, 0xCDB2, 0xAD8E, 0xCDB3, 0xAD8F,
+	0xCDB4, 0xAD90, 0xCDB5, 0xAD91, 0xCDB6, 0xAD92, 0xCDB7, 0xAD93,	0xCDB8, 0xAD94, 0xCDB9, 0xAD95, 0xCDBA, 0xAD96, 0xCDBB, 0xAD97,
+	0xCDBC, 0xAD98, 0xCDBD, 0xAD99, 0xCDBE, 0xAD9A, 0xCDBF, 0xAD9B,	0xCDC0, 0xAD9C, 0xCDC1, 0xAD9D, 0xCDC2, 0xAD9E, 0xCDC3, 0xAD9F,
+	0xCDC4, 0xC3E8, 0xCDC5, 0xADA0, 0xCDC6, 0xAE41, 0xCDC7, 0xAE42,	0xCDC8, 0xAE43, 0xCDC9, 0xAE44, 0xCDCA, 0xAE45, 0xCDCB, 0xAE46,
+	0xCDCC, 0xC3E9, 0xCDCD, 0xAE47, 0xCDCE, 0xAE48, 0xCDCF, 0xAE49,	0xCDD0, 0xC3EA, 0xCDD1, 0xAE4A, 0xCDD2, 0xAE4B, 0xCDD3, 0xAE4C,
+	0xCDD4, 0xAE4D, 0xCDD5, 0xAE4E, 0xCDD6, 0xAE4F, 0xCDD7, 0xAE50,	0xCDD8, 0xAE51, 0xCDD9, 0xAE52, 0xCDDA, 0xAE53, 0xCDDB, 0xAE54,
+	0xCDDC, 0xAE55, 0xCDDD, 0xAE56, 0xCDDE, 0xAE57, 0xCDDF, 0xAE58,	0xCDE0, 0xAE59, 0xCDE1, 0xAE5A, 0xCDE2, 0xAE61, 0xCDE3, 0xAE62,
+	0xCDE4, 0xAE63, 0xCDE5, 0xAE64, 0xCDE6, 0xAE65, 0xCDE7, 0xAE66,	0xCDE8, 0xC3EB, 0xCDE9, 0xAE67, 0xCDEA, 0xAE68, 0xCDEB, 0xAE69,
+	0xCDEC, 0xC3EC, 0xCDED, 0xAE6A, 0xCDEE, 0xAE6B, 0xCDEF, 0xAE6C,	0xCDF0, 0xC3ED, 0xCDF1, 0xAE6D, 0xCDF2, 0xAE6E, 0xCDF3, 0xAE6F,
+	0xCDF4, 0xAE70, 0xCDF5, 0xAE71, 0xCDF6, 0xAE72, 0xCDF7, 0xAE73,	0xCDF8, 0xC3EE, 0xCDF9, 0xC3EF, 0xCDFA, 0xAE74, 0xCDFB, 0xC3F0,
+	0xCDFC, 0xAE75, 0xCDFD, 0xC3F1, 0xCDFE, 0xAE76, 0xCDFF, 0xAE77,	0xCE00, 0xAE78, 0xCE01, 0xAE79, 0xCE02, 0xAE7A, 0xCE03, 0xAE81,
+	0xCE04, 0xC3F2, 0xCE05, 0xAE82, 0xCE06, 0xAE83, 0xCE07, 0xAE84,	0xCE08, 0xC3F3, 0xCE09, 0xAE85, 0xCE0A, 0xAE86, 0xCE0B, 0xAE87,
+	0xCE0C, 0xC3F4, 0xCE0D, 0xAE88, 0xCE0E, 0xAE89, 0xCE0F, 0xAE8A,	0xCE10, 0xAE8B, 0xCE11, 0xAE8C, 0xCE12, 0xAE8D, 0xCE13, 0xAE8E,
+	0xCE14, 0xC3F5, 0xCE15, 0xAE8F, 0xCE16, 0xAE90, 0xCE17, 0xAE91,	0xCE18, 0xAE92, 0xCE19, 0xC3F6, 0xCE1A, 0xAE93, 0xCE1B, 0xAE94,
+	0xCE1C, 0xAE95, 0xCE1D, 0xAE96, 0xCE1E, 0xAE97, 0xCE1F, 0xAE98,	0xCE20, 0xC3F7, 0xCE21, 0xC3F8, 0xCE22, 0xAE99, 0xCE23, 0xAE9A,
+	0xCE24, 0xC3F9, 0xCE25, 0xAE9B, 0xCE26, 0xAE9C, 0xCE27, 0xAE9D,	0xCE28, 0xC3FA, 0xCE29, 0xAE9E, 0xCE2A, 0xAE9F, 0xCE2B, 0xAEA0,
+	0xCE2C, 0xAF41, 0xCE2D, 0xAF42, 0xCE2E, 0xAF43, 0xCE2F, 0xAF44,	0xCE30, 0xC3FB, 0xCE31, 0xC3FC, 0xCE32, 0xAF45, 0xCE33, 0xC3FD,
+	0xCE34, 0xAF46, 0xCE35, 0xC3FE, 0xCE36, 0xAF47, 0xCE37, 0xAF48,	0xCE38, 0xAF49, 0xCE39, 0xAF4A, 0xCE3A, 0xAF4B, 0xCE3B, 0xAF4C,
+	0xCE3C, 0xAF4D, 0xCE3D, 0xAF4E, 0xCE3E, 0xAF4F, 0xCE3F, 0xAF50,	0xCE40, 0xAF51, 0xCE41, 0xAF52, 0xCE42, 0xAF53, 0xCE43, 0xAF54,
+	0xCE44, 0xAF55, 0xCE45, 0xAF56, 0xCE46, 0xAF57, 0xCE47, 0xAF58,	0xCE48, 0xAF59, 0xCE49, 0xAF5A, 0xCE4A, 0xAF61, 0xCE4B, 0xAF62,
+	0xCE4C, 0xAF63, 0xCE4D, 0xAF64, 0xCE4E, 0xAF65, 0xCE4F, 0xAF66,	0xCE50, 0xAF67, 0xCE51, 0xAF68, 0xCE52, 0xAF69, 0xCE53, 0xAF6A,
+	0xCE54, 0xAF6B, 0xCE55, 0xAF6C, 0xCE56, 0xAF6D, 0xCE57, 0xAF6E,	0xCE58, 0xC4A1, 0xCE59, 0xC4A2, 0xCE5A, 0xAF6F, 0xCE5B, 0xAF70,
+	0xCE5C, 0xC4A3, 0xCE5D, 0xAF71, 0xCE5E, 0xAF72, 0xCE5F, 0xC4A4,	0xCE60, 0xC4A5, 0xCE61, 0xC4A6, 0xCE62, 0xAF73, 0xCE63, 0xAF74,
+	0xCE64, 0xAF75, 0xCE65, 0xAF76, 0xCE66, 0xAF77, 0xCE67, 0xAF78,	0xCE68, 0xC4A7, 0xCE69, 0xC4A8, 0xCE6A, 0xAF79, 0xCE6B, 0xC4A9,
+	0xCE6C, 0xAF7A, 0xCE6D, 0xC4AA, 0xCE6E, 0xAF81, 0xCE6F, 0xAF82,	0xCE70, 0xAF83, 0xCE71, 0xAF84, 0xCE72, 0xAF85, 0xCE73, 0xAF86,
+	0xCE74, 0xC4AB, 0xCE75, 0xC4AC, 0xCE76, 0xAF87, 0xCE77, 0xAF88,	0xCE78, 0xC4AD, 0xCE79, 0xAF89, 0xCE7A, 0xAF8A, 0xCE7B, 0xAF8B,
+	0xCE7C, 0xC4AE, 0xCE7D, 0xAF8C, 0xCE7E, 0xAF8D, 0xCE7F, 0xAF8E,	0xCE80, 0xAF8F, 0xCE81, 0xAF90, 0xCE82, 0xAF91, 0xCE83, 0xAF92,
+	0xCE84, 0xC4AF, 0xCE85, 0xC4B0, 0xCE86, 0xAF93, 0xCE87, 0xC4B1,	0xCE88, 0xAF94, 0xCE89, 0xC4B2, 0xCE8A, 0xAF95, 0xCE8B, 0xAF96,
+	0xCE8C, 0xAF97, 0xCE8D, 0xAF98, 0xCE8E, 0xAF99, 0xCE8F, 0xAF9A,	0xCE90, 0xC4B3, 0xCE91, 0xC4B4, 0xCE92, 0xAF9B, 0xCE93, 0xAF9C,
+	0xCE94, 0xC4B5, 0xCE95, 0xAF9D, 0xCE96, 0xAF9E, 0xCE97, 0xAF9F,	0xCE98, 0xC4B6, 0xCE99, 0xAFA0, 0xCE9A, 0xB041, 0xCE9B, 0xB042,
+	0xCE9C, 0xB043, 0xCE9D, 0xB044, 0xCE9E, 0xB045, 0xCE9F, 0xB046,	0xCEA0, 0xC4B7, 0xCEA1, 0xC4B8, 0xCEA2, 0xB047, 0xCEA3, 0xC4B9,
+	0xCEA4, 0xC4BA, 0xCEA5, 0xC4BB, 0xCEA6, 0xB048, 0xCEA7, 0xB049,	0xCEA8, 0xB04A, 0xCEA9, 0xB04B, 0xCEAA, 0xB04C, 0xCEAB, 0xB04D,
+	0xCEAC, 0xC4BC, 0xCEAD, 0xC4BD, 0xCEAE, 0xB04E, 0xCEAF, 0xB04F,	0xCEB0, 0xB050, 0xCEB1, 0xB051, 0xCEB2, 0xB052, 0xCEB3, 0xB053,
+	0xCEB4, 0xB054, 0xCEB5, 0xB055, 0xCEB6, 0xB056, 0xCEB7, 0xB057,	0xCEB8, 0xB058, 0xCEB9, 0xB059, 0xCEBA, 0xB05A, 0xCEBB, 0xB061,
+	0xCEBC, 0xB062, 0xCEBD, 0xB063, 0xCEBE, 0xB064, 0xCEBF, 0xB065,	0xCEC0, 0xB066, 0xCEC1, 0xC4BE, 0xCEC2, 0xB067, 0xCEC3, 0xB068,
+	0xCEC4, 0xB069, 0xCEC5, 0xB06A, 0xCEC6, 0xB06B, 0xCEC7, 0xB06C,	0xCEC8, 0xB06D, 0xCEC9, 0xB06E, 0xCECA, 0xB06F, 0xCECB, 0xB070,
+	0xCECC, 0xB071, 0xCECD, 0xB072, 0xCECE, 0xB073, 0xCECF, 0xB074,	0xCED0, 0xB075, 0xCED1, 0xB076, 0xCED2, 0xB077, 0xCED3, 0xB078,
+	0xCED4, 0xB079, 0xCED5, 0xB07A, 0xCED6, 0xB081, 0xCED7, 0xB082,	0xCED8, 0xB083, 0xCED9, 0xB084, 0xCEDA, 0xB085, 0xCEDB, 0xB086,
+	0xCEDC, 0xB087, 0xCEDD, 0xB088, 0xCEDE, 0xB089, 0xCEDF, 0xB08A,	0xCEE0, 0xB08B, 0xCEE1, 0xB08C, 0xCEE2, 0xB08D, 0xCEE3, 0xB08E,
+	0xCEE4, 0xC4BF, 0xCEE5, 0xC4C0, 0xCEE6, 0xB08F, 0xCEE7, 0xB090,	0xCEE8, 0xC4C1, 0xCEE9, 0xB091, 0xCEEA, 0xB092, 0xCEEB, 0xC4C2,
+	0xCEEC, 0xC4C3, 0xCEED, 0xB093, 0xCEEE, 0xB094, 0xCEEF, 0xB095,	0xCEF0, 0xB096, 0xCEF1, 0xB097, 0xCEF2, 0xB098, 0xCEF3, 0xB099,
+	0xCEF4, 0xC4C4, 0xCEF5, 0xC4C5, 0xCEF6, 0xB09A, 0xCEF7, 0xC4C6,	0xCEF8, 0xC4C7, 0xCEF9, 0xC4C8, 0xCEFA, 0xB09B, 0xCEFB, 0xB09C,
+	0xCEFC, 0xB09D, 0xCEFD, 0xB09E, 0xCEFE, 0xB09F, 0xCEFF, 0xB0A0,	0xCF00, 0xC4C9, 0xCF01, 0xC4CA, 0xCF02, 0xB141, 0xCF03, 0xB142,
+	0xCF04, 0xC4CB, 0xCF05, 0xB143, 0xCF06, 0xB144, 0xCF07, 0xB145,	0xCF08, 0xC4CC, 0xCF09, 0xB146, 0xCF0A, 0xB147, 0xCF0B, 0xB148,
+	0xCF0C, 0xB149, 0xCF0D, 0xB14A, 0xCF0E, 0xB14B, 0xCF0F, 0xB14C,	0xCF10, 0xC4CD, 0xCF11, 0xC4CE, 0xCF12, 0xB14D, 0xCF13, 0xC4CF,
+	0xCF14, 0xB14E, 0xCF15, 0xC4D0, 0xCF16, 0xB14F, 0xCF17, 0xB150,	0xCF18, 0xB151, 0xCF19, 0xB152, 0xCF1A, 0xB153, 0xCF1B, 0xB154,
+	0xCF1C, 0xC4D1, 0xCF1D, 0xB155, 0xCF1E, 0xB156, 0xCF1F, 0xB157,	0xCF20, 0xC4D2, 0xCF21, 0xB158, 0xCF22, 0xB159, 0xCF23, 0xB15A,
+	0xCF24, 0xC4D3, 0xCF25, 0xB161, 0xCF26, 0xB162, 0xCF27, 0xB163,	0xCF28, 0xB164, 0xCF29, 0xB165, 0xCF2A, 0xB166, 0xCF2B, 0xB167,
+	0xCF2C, 0xC4D4, 0xCF2D, 0xC4D5, 0xCF2E, 0xB168, 0xCF2F, 0xC4D6,	0xCF30, 0xC4D7, 0xCF31, 0xC4D8, 0xCF32, 0xB169, 0xCF33, 0xB16A,
+	0xCF34, 0xB16B, 0xCF35, 0xB16C, 0xCF36, 0xB16D, 0xCF37, 0xB16E,	0xCF38, 0xC4D9, 0xCF39, 0xB16F, 0xCF3A, 0xB170, 0xCF3B, 0xB171,
+	0xCF3C, 0xB172, 0xCF3D, 0xB173, 0xCF3E, 0xB174, 0xCF3F, 0xB175,	0xCF40, 0xB176, 0xCF41, 0xB177, 0xCF42, 0xB178, 0xCF43, 0xB179,
+	0xCF44, 0xB17A, 0xCF45, 0xB181, 0xCF46, 0xB182, 0xCF47, 0xB183,	0xCF48, 0xB184, 0xCF49, 0xB185, 0xCF4A, 0xB186, 0xCF4B, 0xB187,
+	0xCF4C, 0xB188, 0xCF4D, 0xB189, 0xCF4E, 0xB18A, 0xCF4F, 0xB18B,	0xCF50, 0xB18C, 0xCF51, 0xB18D, 0xCF52, 0xB18E, 0xCF53, 0xB18F,
+	0xCF54, 0xC4DA, 0xCF55, 0xC4DB, 0xCF56, 0xB190, 0xCF57, 0xB191,	0xCF58, 0xC4DC, 0xCF59, 0xB192, 0xCF5A, 0xB193, 0xCF5B, 0xB194,
+	0xCF5C, 0xC4DD, 0xCF5D, 0xB195, 0xCF5E, 0xB196, 0xCF5F, 0xB197,	0xCF60, 0xB198, 0xCF61, 0xB199, 0xCF62, 0xB19A, 0xCF63, 0xB19B,
+	0xCF64, 0xC4DE, 0xCF65, 0xC4DF, 0xCF66, 0xB19C, 0xCF67, 0xC4E0,	0xCF68, 0xB19D, 0xCF69, 0xC4E1, 0xCF6A, 0xB19E, 0xCF6B, 0xB19F,
+	0xCF6C, 0xB1A0, 0xCF6D, 0xB241, 0xCF6E, 0xB242, 0xCF6F, 0xB243,	0xCF70, 0xC4E2, 0xCF71, 0xC4E3, 0xCF72, 0xB244, 0xCF73, 0xB245,
+	0xCF74, 0xC4E4, 0xCF75, 0xB246, 0xCF76, 0xB247, 0xCF77, 0xB248,	0xCF78, 0xC4E5, 0xCF79, 0xB249, 0xCF7A, 0xB24A, 0xCF7B, 0xB24B,
+	0xCF7C, 0xB24C, 0xCF7D, 0xB24D, 0xCF7E, 0xB24E, 0xCF7F, 0xB24F,	0xCF80, 0xC4E6, 0xCF81, 0xB250, 0xCF82, 0xB251, 0xCF83, 0xB252,
+	0xCF84, 0xB253, 0xCF85, 0xC4E7, 0xCF86, 0xB254, 0xCF87, 0xB255,	0xCF88, 0xB256, 0xCF89, 0xB257, 0xCF8A, 0xB258, 0xCF8B, 0xB259,
+	0xCF8C, 0xC4E8, 0xCF8D, 0xB25A, 0xCF8E, 0xB261, 0xCF8F, 0xB262,	0xCF90, 0xB263, 0xCF91, 0xB264, 0xCF92, 0xB265, 0xCF93, 0xB266,
+	0xCF94, 0xB267, 0xCF95, 0xB268, 0xCF96, 0xB269, 0xCF97, 0xB26A,	0xCF98, 0xB26B, 0xCF99, 0xB26C, 0xCF9A, 0xB26D, 0xCF9B, 0xB26E,
+	0xCF9C, 0xB26F, 0xCF9D, 0xB270, 0xCF9E, 0xB271, 0xCF9F, 0xB272,	0xCFA0, 0xB273, 0xCFA1, 0xC4E9, 0xCFA2, 0xB274, 0xCFA3, 0xB275,
+	0xCFA4, 0xB276, 0xCFA5, 0xB277, 0xCFA6, 0xB278, 0xCFA7, 0xB279,	0xCFA8, 0xC4EA, 0xCFA9, 0xB27A, 0xCFAA, 0xB281, 0xCFAB, 0xB282,
+	0xCFAC, 0xB283, 0xCFAD, 0xB284, 0xCFAE, 0xB285, 0xCFAF, 0xB286,	0xCFB0, 0xC4EB, 0xCFB1, 0xB287, 0xCFB2, 0xB288, 0xCFB3, 0xB289,
+	0xCFB4, 0xB28A, 0xCFB5, 0xB28B, 0xCFB6, 0xB28C, 0xCFB7, 0xB28D,	0xCFB8, 0xB28E, 0xCFB9, 0xB28F, 0xCFBA, 0xB290, 0xCFBB, 0xB291,
+	0xCFBC, 0xB292, 0xCFBD, 0xB293, 0xCFBE, 0xB294, 0xCFBF, 0xB295,	0xCFC0, 0xB296, 0xCFC1, 0xB297, 0xCFC2, 0xB298, 0xCFC3, 0xB299,
+	0xCFC4, 0xC4EC, 0xCFC5, 0xB29A, 0xCFC6, 0xB29B, 0xCFC7, 0xB29C,	0xCFC8, 0xB29D, 0xCFC9, 0xB29E, 0xCFCA, 0xB29F, 0xCFCB, 0xB2A0,
+	0xCFCC, 0xB341, 0xCFCD, 0xB342, 0xCFCE, 0xB343, 0xCFCF, 0xB344,	0xCFD0, 0xB345, 0xCFD1, 0xB346, 0xCFD2, 0xB347, 0xCFD3, 0xB348,
+	0xCFD4, 0xB349, 0xCFD5, 0xB34A, 0xCFD6, 0xB34B, 0xCFD7, 0xB34C,	0xCFD8, 0xB34D, 0xCFD9, 0xB34E, 0xCFDA, 0xB34F, 0xCFDB, 0xB350,
+	0xCFDC, 0xB351, 0xCFDD, 0xB352, 0xCFDE, 0xB353, 0xCFDF, 0xB354,	0xCFE0, 0xC4ED, 0xCFE1, 0xC4EE, 0xCFE2, 0xB355, 0xCFE3, 0xB356,
+	0xCFE4, 0xC4EF, 0xCFE5, 0xB357, 0xCFE6, 0xB358, 0xCFE7, 0xB359,	0xCFE8, 0xC4F0, 0xCFE9, 0xB35A, 0xCFEA, 0xB361, 0xCFEB, 0xB362,
+	0xCFEC, 0xB363, 0xCFED, 0xB364, 0xCFEE, 0xB365, 0xCFEF, 0xB366,	0xCFF0, 0xC4F1, 0xCFF1, 0xC4F2, 0xCFF2, 0xB367, 0xCFF3, 0xC4F3,
+	0xCFF4, 0xB368, 0xCFF5, 0xC4F4, 0xCFF6, 0xB369, 0xCFF7, 0xB36A,	0xCFF8, 0xB36B, 0xCFF9, 0xB36C, 0xCFFA, 0xB36D, 0xCFFB, 0xB36E,
+	0xCFFC, 0xC4F5, 0xCFFD, 0xB36F, 0xCFFE, 0xB370, 0xCFFF, 0xB371,	0xD000, 0xC4F6, 0xD001, 0xB372, 0xD002, 0xB373, 0xD003, 0xB374,
+	0xD004, 0xC4F7, 0xD005, 0xB375, 0xD006, 0xB376, 0xD007, 0xB377,	0xD008, 0xB378, 0xD009, 0xB379, 0xD00A, 0xB37A, 0xD00B, 0xB381,
+	0xD00C, 0xB382, 0xD00D, 0xB383, 0xD00E, 0xB384, 0xD00F, 0xB385,	0xD010, 0xB386, 0xD011, 0xC4F8, 0xD012, 0xB387, 0xD013, 0xB388,
+	0xD014, 0xB389, 0xD015, 0xB38A, 0xD016, 0xB38B, 0xD017, 0xB38C,	0xD018, 0xC4F9, 0xD019, 0xB38D, 0xD01A, 0xB38E, 0xD01B, 0xB38F,
+	0xD01C, 0xB390, 0xD01D, 0xB391, 0xD01E, 0xB392, 0xD01F, 0xB393,	0xD020, 0xB394, 0xD021, 0xB395, 0xD022, 0xB396, 0xD023, 0xB397,
+	0xD024, 0xB398, 0xD025, 0xB399, 0xD026, 0xB39A, 0xD027, 0xB39B,	0xD028, 0xB39C, 0xD029, 0xB39D, 0xD02A, 0xB39E, 0xD02B, 0xB39F,
+	0xD02C, 0xB3A0, 0xD02D, 0xC4FA, 0xD02E, 0xB441, 0xD02F, 0xB442,	0xD030, 0xB443, 0xD031, 0xB444, 0xD032, 0xB445, 0xD033, 0xB446,
+	0xD034, 0xC4FB, 0xD035, 0xC4FC, 0xD036, 0xB447, 0xD037, 0xB448,	0xD038, 0xC4FD, 0xD039, 0xB449, 0xD03A, 0xB44A, 0xD03B, 0xB44B,
+	0xD03C, 0xC4FE, 0xD03D, 0xB44C, 0xD03E, 0xB44D, 0xD03F, 0xB44E,	0xD040, 0xB44F, 0xD041, 0xB450, 0xD042, 0xB451, 0xD043, 0xB452,
+	0xD044, 0xC5A1, 0xD045, 0xC5A2, 0xD046, 0xB453, 0xD047, 0xC5A3,	0xD048, 0xB454, 0xD049, 0xC5A4, 0xD04A, 0xB455, 0xD04B, 0xB456,
+	0xD04C, 0xB457, 0xD04D, 0xB458, 0xD04E, 0xB459, 0xD04F, 0xB45A,	0xD050, 0xC5A5, 0xD051, 0xB461, 0xD052, 0xB462, 0xD053, 0xB463,
+	0xD054, 0xC5A6, 0xD055, 0xB464, 0xD056, 0xB465, 0xD057, 0xB466,	0xD058, 0xC5A7, 0xD059, 0xB467, 0xD05A, 0xB468, 0xD05B, 0xB469,
+	0xD05C, 0xB46A, 0xD05D, 0xB46B, 0xD05E, 0xB46C, 0xD05F, 0xB46D,	0xD060, 0xC5A8, 0xD061, 0xB46E, 0xD062, 0xB46F, 0xD063, 0xB470,
+	0xD064, 0xB471, 0xD065, 0xB472, 0xD066, 0xB473, 0xD067, 0xB474,	0xD068, 0xB475, 0xD069, 0xB476, 0xD06A, 0xB477, 0xD06B, 0xB478,
+	0xD06C, 0xC5A9, 0xD06D, 0xC5AA, 0xD06E, 0xB479, 0xD06F, 0xB47A,	0xD070, 0xC5AB, 0xD071, 0xB481, 0xD072, 0xB482, 0xD073, 0xB483,
+	0xD074, 0xC5AC, 0xD075, 0xB484, 0xD076, 0xB485, 0xD077, 0xB486,	0xD078, 0xB487, 0xD079, 0xB488, 0xD07A, 0xB489, 0xD07B, 0xB48A,
+	0xD07C, 0xC5AD, 0xD07D, 0xC5AE, 0xD07E, 0xB48B, 0xD07F, 0xB48C,	0xD080, 0xB48D, 0xD081, 0xC5AF, 0xD082, 0xB48E, 0xD083, 0xB48F,
+	0xD084, 0xB490, 0xD085, 0xB491, 0xD086, 0xB492, 0xD087, 0xB493,	0xD088, 0xB494, 0xD089, 0xB495, 0xD08A, 0xB496, 0xD08B, 0xB497,
+	0xD08C, 0xB498, 0xD08D, 0xB499, 0xD08E, 0xB49A, 0xD08F, 0xB49B,	0xD090, 0xB49C, 0xD091, 0xB49D, 0xD092, 0xB49E, 0xD093, 0xB49F,
+	0xD094, 0xB4A0, 0xD095, 0xB541, 0xD096, 0xB542, 0xD097, 0xB543,	0xD098, 0xB544, 0xD099, 0xB545, 0xD09A, 0xB546, 0xD09B, 0xB547,
+	0xD09C, 0xB548, 0xD09D, 0xB549, 0xD09E, 0xB54A, 0xD09F, 0xB54B,	0xD0A0, 0xB54C, 0xD0A1, 0xB54D, 0xD0A2, 0xB54E, 0xD0A3, 0xB54F,
+	0xD0A4, 0xC5B0, 0xD0A5, 0xC5B1, 0xD0A6, 0xB550, 0xD0A7, 0xB551,	0xD0A8, 0xC5B2, 0xD0A9, 0xB552, 0xD0AA, 0xB553, 0xD0AB, 0xB554,
+	0xD0AC, 0xC5B3, 0xD0AD, 0xB555, 0xD0AE, 0xB556, 0xD0AF, 0xB557,	0xD0B0, 0xB558, 0xD0B1, 0xB559, 0xD0B2, 0xB55A, 0xD0B3, 0xB561,
+	0xD0B4, 0xC5B4, 0xD0B5, 0xC5B5, 0xD0B6, 0xB562, 0xD0B7, 0xC5B6,	0xD0B8, 0xB563, 0xD0B9, 0xC5B7, 0xD0BA, 0xB564, 0xD0BB, 0xB565,
+	0xD0BC, 0xB566, 0xD0BD, 0xB567, 0xD0BE, 0xB568, 0xD0BF, 0xB569,	0xD0C0, 0xC5B8, 0xD0C1, 0xC5B9, 0xD0C2, 0xB56A, 0xD0C3, 0xB56B,
+	0xD0C4, 0xC5BA, 0xD0C5, 0xB56C, 0xD0C6, 0xB56D, 0xD0C7, 0xB56E,	0xD0C8, 0xC5BB, 0xD0C9, 0xC5BC, 0xD0CA, 0xB56F, 0xD0CB, 0xB570,
+	0xD0CC, 0xB571, 0xD0CD, 0xB572, 0xD0CE, 0xB573, 0xD0CF, 0xB574,	0xD0D0, 0xC5BD, 0xD0D1, 0xC5BE, 0xD0D2, 0xB575, 0xD0D3, 0xC5BF,
+	0xD0D4, 0xC5C0, 0xD0D5, 0xC5C1, 0xD0D6, 0xB576, 0xD0D7, 0xB577,	0xD0D8, 0xB578, 0xD0D9, 0xB579, 0xD0DA, 0xB57A, 0xD0DB, 0xB581,
+	0xD0DC, 0xC5C2, 0xD0DD, 0xC5C3, 0xD0DE, 0xB582, 0xD0DF, 0xB583,	0xD0E0, 0xC5C4, 0xD0E1, 0xB584, 0xD0E2, 0xB585, 0xD0E3, 0xB586,
+	0xD0E4, 0xC5C5, 0xD0E5, 0xB587, 0xD0E6, 0xB588, 0xD0E7, 0xB589,	0xD0E8, 0xB58A, 0xD0E9, 0xB58B, 0xD0EA, 0xB58C, 0xD0EB, 0xB58D,
+	0xD0EC, 0xC5C6, 0xD0ED, 0xC5C7, 0xD0EE, 0xB58E, 0xD0EF, 0xC5C8,	0xD0F0, 0xC5C9, 0xD0F1, 0xC5CA, 0xD0F2, 0xB58F, 0xD0F3, 0xB590,
+	0xD0F4, 0xB591, 0xD0F5, 0xB592, 0xD0F6, 0xB593, 0xD0F7, 0xB594,	0xD0F8, 0xC5CB, 0xD0F9, 0xB595, 0xD0FA, 0xB596, 0xD0FB, 0xB597,
+	0xD0FC, 0xB598, 0xD0FD, 0xB599, 0xD0FE, 0xB59A, 0xD0FF, 0xB59B,	0xD100, 0xB59C, 0xD101, 0xB59D, 0xD102, 0xB59E, 0xD103, 0xB59F,
+	0xD104, 0xB5A0, 0xD105, 0xB641, 0xD106, 0xB642, 0xD107, 0xB643,	0xD108, 0xB644, 0xD109, 0xB645, 0xD10A, 0xB646, 0xD10B, 0xB647,
+	0xD10C, 0xB648, 0xD10D, 0xC5CC, 0xD10E, 0xB649, 0xD10F, 0xB64A,	0xD110, 0xB64B, 0xD111, 0xB64C, 0xD112, 0xB64D, 0xD113, 0xB64E,
+	0xD114, 0xB64F, 0xD115, 0xB650, 0xD116, 0xB651, 0xD117, 0xB652,	0xD118, 0xB653, 0xD119, 0xB654, 0xD11A, 0xB655, 0xD11B, 0xB656,
+	0xD11C, 0xB657, 0xD11D, 0xB658, 0xD11E, 0xB659, 0xD11F, 0xB65A,	0xD120, 0xB661, 0xD121, 0xB662, 0xD122, 0xB663, 0xD123, 0xB664,
+	0xD124, 0xB665, 0xD125, 0xB666, 0xD126, 0xB667, 0xD127, 0xB668,	0xD128, 0xB669, 0xD129, 0xB66A, 0xD12A, 0xB66B, 0xD12B, 0xB66C,
+	0xD12C, 0xB66D, 0xD12D, 0xB66E, 0xD12E, 0xB66F, 0xD12F, 0xB670,	0xD130, 0xC5CD, 0xD131, 0xC5CE, 0xD132, 0xB671, 0xD133, 0xB672,
+	0xD134, 0xC5CF, 0xD135, 0xB673, 0xD136, 0xB674, 0xD137, 0xB675,	0xD138, 0xC5D0, 0xD139, 0xB676, 0xD13A, 0xC5D1, 0xD13B, 0xB677,
+	0xD13C, 0xB678, 0xD13D, 0xB679, 0xD13E, 0xB67A, 0xD13F, 0xB681,	0xD140, 0xC5D2, 0xD141, 0xC5D3, 0xD142, 0xB682, 0xD143, 0xC5D4,
+	0xD144, 0xC5D5, 0xD145, 0xC5D6, 0xD146, 0xB683, 0xD147, 0xB684,	0xD148, 0xB685, 0xD149, 0xB686, 0xD14A, 0xB687, 0xD14B, 0xB688,
+	0xD14C, 0xC5D7, 0xD14D, 0xC5D8, 0xD14E, 0xB689, 0xD14F, 0xB68A,	0xD150, 0xC5D9, 0xD151, 0xB68B, 0xD152, 0xB68C, 0xD153, 0xB68D,
+	0xD154, 0xC5DA, 0xD155, 0xB68E, 0xD156, 0xB68F, 0xD157, 0xB690,	0xD158, 0xB691, 0xD159, 0xB692, 0xD15A, 0xB693, 0xD15B, 0xB694,
+	0xD15C, 0xC5DB, 0xD15D, 0xC5DC, 0xD15E, 0xB695, 0xD15F, 0xC5DD,	0xD160, 0xB696, 0xD161, 0xC5DE, 0xD162, 0xB697, 0xD163, 0xB698,
+	0xD164, 0xB699, 0xD165, 0xB69A, 0xD166, 0xB69B, 0xD167, 0xB69C,	0xD168, 0xC5DF, 0xD169, 0xB69D, 0xD16A, 0xB69E, 0xD16B, 0xB69F,
+	0xD16C, 0xC5E0, 0xD16D, 0xB6A0, 0xD16E, 0xB741, 0xD16F, 0xB742,	0xD170, 0xB743, 0xD171, 0xB744, 0xD172, 0xB745, 0xD173, 0xB746,
+	0xD174, 0xB747, 0xD175, 0xB748, 0xD176, 0xB749, 0xD177, 0xB74A,	0xD178, 0xB74B, 0xD179, 0xB74C, 0xD17A, 0xB74D, 0xD17B, 0xB74E,
+	0xD17C, 0xC5E1, 0xD17D, 0xB74F, 0xD17E, 0xB750, 0xD17F, 0xB751,	0xD180, 0xB752, 0xD181, 0xB753, 0xD182, 0xB754, 0xD183, 0xB755,
+	0xD184, 0xC5E2, 0xD185, 0xB756, 0xD186, 0xB757, 0xD187, 0xB758,	0xD188, 0xC5E3, 0xD189, 0xB759, 0xD18A, 0xB75A, 0xD18B, 0xB761,
+	0xD18C, 0xB762, 0xD18D, 0xB763, 0xD18E, 0xB764, 0xD18F, 0xB765,	0xD190, 0xB766, 0xD191, 0xB767, 0xD192, 0xB768, 0xD193, 0xB769,
+	0xD194, 0xB76A, 0xD195, 0xB76B, 0xD196, 0xB76C, 0xD197, 0xB76D,	0xD198, 0xB76E, 0xD199, 0xB76F, 0xD19A, 0xB770, 0xD19B, 0xB771,
+	0xD19C, 0xB772, 0xD19D, 0xB773, 0xD19E, 0xB774, 0xD19F, 0xB775,	0xD1A0, 0xC5E4, 0xD1A1, 0xC5E5, 0xD1A2, 0xB776, 0xD1A3, 0xB777,
+	0xD1A4, 0xC5E6, 0xD1A5, 0xB778, 0xD1A6, 0xB779, 0xD1A7, 0xB77A,	0xD1A8, 0xC5E7, 0xD1A9, 0xB781, 0xD1AA, 0xB782, 0xD1AB, 0xB783,
+	0xD1AC, 0xB784, 0xD1AD, 0xB785, 0xD1AE, 0xB786, 0xD1AF, 0xB787,	0xD1B0, 0xC5E8, 0xD1B1, 0xC5E9, 0xD1B2, 0xB788, 0xD1B3, 0xC5EA,
+	0xD1B4, 0xB789, 0xD1B5, 0xC5EB, 0xD1B6, 0xB78A, 0xD1B7, 0xB78B,	0xD1B8, 0xB78C, 0xD1B9, 0xB78D, 0xD1BA, 0xC5EC, 0xD1BB, 0xB78E,
+	0xD1BC, 0xC5ED, 0xD1BD, 0xB78F, 0xD1BE, 0xB790, 0xD1BF, 0xB791,	0xD1C0, 0xC5EE, 0xD1C1, 0xB792, 0xD1C2, 0xB793, 0xD1C3, 0xB794,
+	0xD1C4, 0xB795, 0xD1C5, 0xB796, 0xD1C6, 0xB797, 0xD1C7, 0xB798,	0xD1C8, 0xB799, 0xD1C9, 0xB79A, 0xD1CA, 0xB79B, 0xD1CB, 0xB79C,
+	0xD1CC, 0xB79D, 0xD1CD, 0xB79E, 0xD1CE, 0xB79F, 0xD1CF, 0xB7A0,	0xD1D0, 0xB841, 0xD1D1, 0xB842, 0xD1D2, 0xB843, 0xD1D3, 0xB844,
+	0xD1D4, 0xB845, 0xD1D5, 0xB846, 0xD1D6, 0xB847, 0xD1D7, 0xB848,	0xD1D8, 0xC5EF, 0xD1D9, 0xB849, 0xD1DA, 0xB84A, 0xD1DB, 0xB84B,
+	0xD1DC, 0xB84C, 0xD1DD, 0xB84D, 0xD1DE, 0xB84E, 0xD1DF, 0xB84F,	0xD1E0, 0xB850, 0xD1E1, 0xB851, 0xD1E2, 0xB852, 0xD1E3, 0xB853,
+	0xD1E4, 0xB854, 0xD1E5, 0xB855, 0xD1E6, 0xB856, 0xD1E7, 0xB857,	0xD1E8, 0xB858, 0xD1E9, 0xB859, 0xD1EA, 0xB85A, 0xD1EB, 0xB861,
+	0xD1EC, 0xB862, 0xD1ED, 0xB863, 0xD1EE, 0xB864, 0xD1EF, 0xB865,	0xD1F0, 0xB866, 0xD1F1, 0xB867, 0xD1F2, 0xB868, 0xD1F3, 0xB869,
+	0xD1F4, 0xC5F0, 0xD1F5, 0xB86A, 0xD1F6, 0xB86B, 0xD1F7, 0xB86C,	0xD1F8, 0xC5F1, 0xD1F9, 0xB86D, 0xD1FA, 0xB86E, 0xD1FB, 0xB86F,
+	0xD1FC, 0xB870, 0xD1FD, 0xB871, 0xD1FE, 0xB872, 0xD1FF, 0xB873,	0xD200, 0xB874, 0xD201, 0xB875, 0xD202, 0xB876, 0xD203, 0xB877,
+	0xD204, 0xB878, 0xD205, 0xB879, 0xD206, 0xB87A, 0xD207, 0xC5F2,	0xD208, 0xB881, 0xD209, 0xC5F3, 0xD20A, 0xB882, 0xD20B, 0xB883,
+	0xD20C, 0xB884, 0xD20D, 0xB885, 0xD20E, 0xB886, 0xD20F, 0xB887,	0xD210, 0xC5F4, 0xD211, 0xB888, 0xD212, 0xB889, 0xD213, 0xB88A,
+	0xD214, 0xB88B, 0xD215, 0xB88C, 0xD216, 0xB88D, 0xD217, 0xB88E,	0xD218, 0xB88F, 0xD219, 0xB890, 0xD21A, 0xB891, 0xD21B, 0xB892,
+	0xD21C, 0xB893, 0xD21D, 0xB894, 0xD21E, 0xB895, 0xD21F, 0xB896,	0xD220, 0xB897, 0xD221, 0xB898, 0xD222, 0xB899, 0xD223, 0xB89A,
+	0xD224, 0xB89B, 0xD225, 0xB89C, 0xD226, 0xB89D, 0xD227, 0xB89E,	0xD228, 0xB89F, 0xD229, 0xB8A0, 0xD22A, 0xB941, 0xD22B, 0xB942,
+	0xD22C, 0xC5F5, 0xD22D, 0xC5F6, 0xD22E, 0xB943, 0xD22F, 0xB944,	0xD230, 0xC5F7, 0xD231, 0xB945, 0xD232, 0xB946, 0xD233, 0xB947,
+	0xD234, 0xC5F8, 0xD235, 0xB948, 0xD236, 0xB949, 0xD237, 0xB94A,	0xD238, 0xB94B, 0xD239, 0xB94C, 0xD23A, 0xB94D, 0xD23B, 0xB94E,
+	0xD23C, 0xC5F9, 0xD23D, 0xC5FA, 0xD23E, 0xB94F, 0xD23F, 0xC5FB,	0xD240, 0xB950, 0xD241, 0xC5FC, 0xD242, 0xB951, 0xD243, 0xB952,
+	0xD244, 0xB953, 0xD245, 0xB954, 0xD246, 0xB955, 0xD247, 0xB956,	0xD248, 0xC5FD, 0xD249, 0xB957, 0xD24A, 0xB958, 0xD24B, 0xB959,
+	0xD24C, 0xB95A, 0xD24D, 0xB961, 0xD24E, 0xB962, 0xD24F, 0xB963,	0xD250, 0xB964, 0xD251, 0xB965, 0xD252, 0xB966, 0xD253, 0xB967,
+	0xD254, 0xB968, 0xD255, 0xB969, 0xD256, 0xB96A, 0xD257, 0xB96B,	0xD258, 0xB96C, 0xD259, 0xB96D, 0xD25A, 0xB96E, 0xD25B, 0xB96F,
+	0xD25C, 0xC5FE, 0xD25D, 0xB970, 0xD25E, 0xB971, 0xD25F, 0xB972,	0xD260, 0xB973, 0xD261, 0xB974, 0xD262, 0xB975, 0xD263, 0xB976,
+	0xD264, 0xC6A1, 0xD265, 0xB977, 0xD266, 0xB978, 0xD267, 0xB979,	0xD268, 0xB97A, 0xD269, 0xB981, 0xD26A, 0xB982, 0xD26B, 0xB983,
+	0xD26C, 0xB984, 0xD26D, 0xB985, 0xD26E, 0xB986, 0xD26F, 0xB987,	0xD270, 0xB988, 0xD271, 0xB989, 0xD272, 0xB98A, 0xD273, 0xB98B,
+	0xD274, 0xB98C, 0xD275, 0xB98D, 0xD276, 0xB98E, 0xD277, 0xB98F,	0xD278, 0xB990, 0xD279, 0xB991, 0xD27A, 0xB992, 0xD27B, 0xB993,
+	0xD27C, 0xB994, 0xD27D, 0xB995, 0xD27E, 0xB996, 0xD27F, 0xB997,	0xD280, 0xC6A2, 0xD281, 0xC6A3, 0xD282, 0xB998, 0xD283, 0xB999,
+	0xD284, 0xC6A4, 0xD285, 0xB99A, 0xD286, 0xB99B, 0xD287, 0xB99C,	0xD288, 0xC6A5, 0xD289, 0xB99D, 0xD28A, 0xB99E, 0xD28B, 0xB99F,
+	0xD28C, 0xB9A0, 0xD28D, 0xBA41, 0xD28E, 0xBA42, 0xD28F, 0xBA43,	0xD290, 0xC6A6, 0xD291, 0xC6A7, 0xD292, 0xBA44, 0xD293, 0xBA45,
+	0xD294, 0xBA46, 0xD295, 0xC6A8, 0xD296, 0xBA47, 0xD297, 0xBA48,	0xD298, 0xBA49, 0xD299, 0xBA4A, 0xD29A, 0xBA4B, 0xD29B, 0xBA4C,
+	0xD29C, 0xC6A9, 0xD29D, 0xBA4D, 0xD29E, 0xBA4E, 0xD29F, 0xBA4F,	0xD2A0, 0xC6AA, 0xD2A1, 0xBA50, 0xD2A2, 0xBA51, 0xD2A3, 0xBA52,
+	0xD2A4, 0xC6AB, 0xD2A5, 0xBA53, 0xD2A6, 0xBA54, 0xD2A7, 0xBA55,	0xD2A8, 0xBA56, 0xD2A9, 0xBA57, 0xD2AA, 0xBA58, 0xD2AB, 0xBA59,
+	0xD2AC, 0xC6AC, 0xD2AD, 0xBA5A, 0xD2AE, 0xBA61, 0xD2AF, 0xBA62,	0xD2B0, 0xBA63, 0xD2B1, 0xC6AD, 0xD2B2, 0xBA64, 0xD2B3, 0xBA65,
+	0xD2B4, 0xBA66, 0xD2B5, 0xBA67, 0xD2B6, 0xBA68, 0xD2B7, 0xBA69,	0xD2B8, 0xC6AE, 0xD2B9, 0xC6AF, 0xD2BA, 0xBA6A, 0xD2BB, 0xBA6B,
+	0xD2BC, 0xC6B0, 0xD2BD, 0xBA6C, 0xD2BE, 0xBA6D, 0xD2BF, 0xC6B1,	0xD2C0, 0xC6B2, 0xD2C1, 0xBA6E, 0xD2C2, 0xC6B3, 0xD2C3, 0xBA6F,
+	0xD2C4, 0xBA70, 0xD2C5, 0xBA71, 0xD2C6, 0xBA72, 0xD2C7, 0xBA73,	0xD2C8, 0xC6B4, 0xD2C9, 0xC6B5, 0xD2CA, 0xBA74, 0xD2CB, 0xC6B6,
+	0xD2CC, 0xBA75, 0xD2CD, 0xBA76, 0xD2CE, 0xBA77, 0xD2CF, 0xBA78,	0xD2D0, 0xBA79, 0xD2D1, 0xBA7A, 0xD2D2, 0xBA81, 0xD2D3, 0xBA82,
+	0xD2D4, 0xC6B7, 0xD2D5, 0xBA83, 0xD2D6, 0xBA84, 0xD2D7, 0xBA85,	0xD2D8, 0xC6B8, 0xD2D9, 0xBA86, 0xD2DA, 0xBA87, 0xD2DB, 0xBA88,
+	0xD2DC, 0xC6B9, 0xD2DD, 0xBA89, 0xD2DE, 0xBA8A, 0xD2DF, 0xBA8B,	0xD2E0, 0xBA8C, 0xD2E1, 0xBA8D, 0xD2E2, 0xBA8E, 0xD2E3, 0xBA8F,
+	0xD2E4, 0xC6BA, 0xD2E5, 0xC6BB, 0xD2E6, 0xBA90, 0xD2E7, 0xBA91,	0xD2E8, 0xBA92, 0xD2E9, 0xBA93, 0xD2EA, 0xBA94, 0xD2EB, 0xBA95,
+	0xD2EC, 0xBA96, 0xD2ED, 0xBA97, 0xD2EE, 0xBA98, 0xD2EF, 0xBA99,	0xD2F0, 0xC6BC, 0xD2F1, 0xC6BD, 0xD2F2, 0xBA9A, 0xD2F3, 0xBA9B,
+	0xD2F4, 0xC6BE, 0xD2F5, 0xBA9C, 0xD2F6, 0xBA9D, 0xD2F7, 0xBA9E,	0xD2F8, 0xC6BF, 0xD2F9, 0xBA9F, 0xD2FA, 0xBAA0, 0xD2FB, 0xBB41,
+	0xD2FC, 0xBB42, 0xD2FD, 0xBB43, 0xD2FE, 0xBB44, 0xD2FF, 0xBB45,	0xD300, 0xC6C0, 0xD301, 0xC6C1, 0xD302, 0xBB46, 0xD303, 0xC6C2,
+	0xD304, 0xBB47, 0xD305, 0xC6C3, 0xD306, 0xBB48, 0xD307, 0xBB49,	0xD308, 0xBB4A, 0xD309, 0xBB4B, 0xD30A, 0xBB4C, 0xD30B, 0xBB4D,
+	0xD30C, 0xC6C4, 0xD30D, 0xC6C5, 0xD30E, 0xC6C6, 0xD30F, 0xBB4E,	0xD310, 0xC6C7, 0xD311, 0xBB4F, 0xD312, 0xBB50, 0xD313, 0xBB51,
+	0xD314, 0xC6C8, 0xD315, 0xBB52, 0xD316, 0xC6C9, 0xD317, 0xBB53,	0xD318, 0xBB54, 0xD319, 0xBB55, 0xD31A, 0xBB56, 0xD31B, 0xBB57,
+	0xD31C, 0xC6CA, 0xD31D, 0xC6CB, 0xD31E, 0xBB58, 0xD31F, 0xC6CC,	0xD320, 0xC6CD, 0xD321, 0xC6CE, 0xD322, 0xBB59, 0xD323, 0xBB5A,
+	0xD324, 0xBB61, 0xD325, 0xC6CF, 0xD326, 0xBB62, 0xD327, 0xBB63,	0xD328, 0xC6D0, 0xD329, 0xC6D1, 0xD32A, 0xBB64, 0xD32B, 0xBB65,
+	0xD32C, 0xC6D2, 0xD32D, 0xBB66, 0xD32E, 0xBB67, 0xD32F, 0xBB68,	0xD330, 0xC6D3, 0xD331, 0xBB69, 0xD332, 0xBB6A, 0xD333, 0xBB6B,
+	0xD334, 0xBB6C, 0xD335, 0xBB6D, 0xD336, 0xBB6E, 0xD337, 0xBB6F,	0xD338, 0xC6D4, 0xD339, 0xC6D5, 0xD33A, 0xBB70, 0xD33B, 0xC6D6,
+	0xD33C, 0xC6D7, 0xD33D, 0xC6D8, 0xD33E, 0xBB71, 0xD33F, 0xBB72,	0xD340, 0xBB73, 0xD341, 0xBB74, 0xD342, 0xBB75, 0xD343, 0xBB76,
+	0xD344, 0xC6D9, 0xD345, 0xC6DA, 0xD346, 0xBB77, 0xD347, 0xBB78,	0xD348, 0xBB79, 0xD349, 0xBB7A, 0xD34A, 0xBB81, 0xD34B, 0xBB82,
+	0xD34C, 0xBB83, 0xD34D, 0xBB84, 0xD34E, 0xBB85, 0xD34F, 0xBB86,	0xD350, 0xBB87, 0xD351, 0xBB88, 0xD352, 0xBB89, 0xD353, 0xBB8A,
+	0xD354, 0xBB8B, 0xD355, 0xBB8C, 0xD356, 0xBB8D, 0xD357, 0xBB8E,	0xD358, 0xBB8F, 0xD359, 0xBB90, 0xD35A, 0xBB91, 0xD35B, 0xBB92,
+	0xD35C, 0xBB93, 0xD35D, 0xBB94, 0xD35E, 0xBB95, 0xD35F, 0xBB96,	0xD360, 0xBB97, 0xD361, 0xBB98, 0xD362, 0xBB99, 0xD363, 0xBB9A,
+	0xD364, 0xBB9B, 0xD365, 0xBB9C, 0xD366, 0xBB9D, 0xD367, 0xBB9E,	0xD368, 0xBB9F, 0xD369, 0xBBA0, 0xD36A, 0xBC41, 0xD36B, 0xBC42,
+	0xD36C, 0xBC43, 0xD36D, 0xBC44, 0xD36E, 0xBC45, 0xD36F, 0xBC46,	0xD370, 0xBC47, 0xD371, 0xBC48, 0xD372, 0xBC49, 0xD373, 0xBC4A,
+	0xD374, 0xBC4B, 0xD375, 0xBC4C, 0xD376, 0xBC4D, 0xD377, 0xBC4E,	0xD378, 0xBC4F, 0xD379, 0xBC50, 0xD37A, 0xBC51, 0xD37B, 0xBC52,
+	0xD37C, 0xC6DB, 0xD37D, 0xC6DC, 0xD37E, 0xBC53, 0xD37F, 0xBC54,	0xD380, 0xC6DD, 0xD381, 0xBC55, 0xD382, 0xBC56, 0xD383, 0xBC57,
+	0xD384, 0xC6DE, 0xD385, 0xBC58, 0xD386, 0xBC59, 0xD387, 0xBC5A,	0xD388, 0xBC61, 0xD389, 0xBC62, 0xD38A, 0xBC63, 0xD38B, 0xBC64,
+	0xD38C, 0xC6DF, 0xD38D, 0xC6E0, 0xD38E, 0xBC65, 0xD38F, 0xC6E1,	0xD390, 0xC6E2, 0xD391, 0xC6E3, 0xD392, 0xBC66, 0xD393, 0xBC67,
+	0xD394, 0xBC68, 0xD395, 0xBC69, 0xD396, 0xBC6A, 0xD397, 0xBC6B,	0xD398, 0xC6E4, 0xD399, 0xC6E5, 0xD39A, 0xBC6C, 0xD39B, 0xBC6D,
+	0xD39C, 0xC6E6, 0xD39D, 0xBC6E, 0xD39E, 0xBC6F, 0xD39F, 0xBC70,	0xD3A0, 0xC6E7, 0xD3A1, 0xBC71, 0xD3A2, 0xBC72, 0xD3A3, 0xBC73,
+	0xD3A4, 0xBC74, 0xD3A5, 0xBC75, 0xD3A6, 0xBC76, 0xD3A7, 0xBC77,	0xD3A8, 0xC6E8, 0xD3A9, 0xC6E9, 0xD3AA, 0xBC78, 0xD3AB, 0xC6EA,
+	0xD3AC, 0xBC79, 0xD3AD, 0xC6EB, 0xD3AE, 0xBC7A, 0xD3AF, 0xBC81,	0xD3B0, 0xBC82, 0xD3B1, 0xBC83, 0xD3B2, 0xBC84, 0xD3B3, 0xBC85,
+	0xD3B4, 0xC6EC, 0xD3B5, 0xBC86, 0xD3B6, 0xBC87, 0xD3B7, 0xBC88,	0xD3B8, 0xC6ED, 0xD3B9, 0xBC89, 0xD3BA, 0xBC8A, 0xD3BB, 0xBC8B,
+	0xD3BC, 0xC6EE, 0xD3BD, 0xBC8C, 0xD3BE, 0xBC8D, 0xD3BF, 0xBC8E,	0xD3C0, 0xBC8F, 0xD3C1, 0xBC90, 0xD3C2, 0xBC91, 0xD3C3, 0xBC92,
+	0xD3C4, 0xC6EF, 0xD3C5, 0xC6F0, 0xD3C6, 0xBC93, 0xD3C7, 0xBC94,	0xD3C8, 0xC6F1, 0xD3C9, 0xC6F2, 0xD3CA, 0xBC95, 0xD3CB, 0xBC96,
+	0xD3CC, 0xBC97, 0xD3CD, 0xBC98, 0xD3CE, 0xBC99, 0xD3CF, 0xBC9A,	0xD3D0, 0xC6F3, 0xD3D1, 0xBC9B, 0xD3D2, 0xBC9C, 0xD3D3, 0xBC9D,
+	0xD3D4, 0xBC9E, 0xD3D5, 0xBC9F, 0xD3D6, 0xBCA0, 0xD3D7, 0xBD41,	0xD3D8, 0xC6F4, 0xD3D9, 0xBD42, 0xD3DA, 0xBD43, 0xD3DB, 0xBD44,
+	0xD3DC, 0xBD45, 0xD3DD, 0xBD46, 0xD3DE, 0xBD47, 0xD3DF, 0xBD48,	0xD3E0, 0xBD49, 0xD3E1, 0xC6F5, 0xD3E2, 0xBD4A, 0xD3E3, 0xC6F6,
+	0xD3E4, 0xBD4B, 0xD3E5, 0xBD4C, 0xD3E6, 0xBD4D, 0xD3E7, 0xBD4E,	0xD3E8, 0xBD4F, 0xD3E9, 0xBD50, 0xD3EA, 0xBD51, 0xD3EB, 0xBD52,
+	0xD3EC, 0xC6F7, 0xD3ED, 0xC6F8, 0xD3EE, 0xBD53, 0xD3EF, 0xBD54,	0xD3F0, 0xC6F9, 0xD3F1, 0xBD55, 0xD3F2, 0xBD56, 0xD3F3, 0xBD57,
+	0xD3F4, 0xC6FA, 0xD3F5, 0xBD58, 0xD3F6, 0xBD59, 0xD3F7, 0xBD5A,	0xD3F8, 0xBD61, 0xD3F9, 0xBD62, 0xD3FA, 0xBD63, 0xD3FB, 0xBD64,
+	0xD3FC, 0xC6FB, 0xD3FD, 0xC6FC, 0xD3FE, 0xBD65, 0xD3FF, 0xC6FD,	0xD400, 0xBD66, 0xD401, 0xC6FE, 0xD402, 0xBD67, 0xD403, 0xBD68,
+	0xD404, 0xBD69, 0xD405, 0xBD6A, 0xD406, 0xBD6B, 0xD407, 0xBD6C,	0xD408, 0xC7A1, 0xD409, 0xBD6D, 0xD40A, 0xBD6E, 0xD40B, 0xBD6F,
+	0xD40C, 0xBD70, 0xD40D, 0xBD71, 0xD40E, 0xBD72, 0xD40F, 0xBD73,	0xD410, 0xBD74, 0xD411, 0xBD75, 0xD412, 0xBD76, 0xD413, 0xBD77,
+	0xD414, 0xBD78, 0xD415, 0xBD79, 0xD416, 0xBD7A, 0xD417, 0xBD81,	0xD418, 0xBD82, 0xD419, 0xBD83, 0xD41A, 0xBD84, 0xD41B, 0xBD85,
+	0xD41C, 0xBD86, 0xD41D, 0xC7A2, 0xD41E, 0xBD87, 0xD41F, 0xBD88,	0xD420, 0xBD89, 0xD421, 0xBD8A, 0xD422, 0xBD8B, 0xD423, 0xBD8C,
+	0xD424, 0xBD8D, 0xD425, 0xBD8E, 0xD426, 0xBD8F, 0xD427, 0xBD90,	0xD428, 0xBD91, 0xD429, 0xBD92, 0xD42A, 0xBD93, 0xD42B, 0xBD94,
+	0xD42C, 0xBD95, 0xD42D, 0xBD96, 0xD42E, 0xBD97, 0xD42F, 0xBD98,	0xD430, 0xBD99, 0xD431, 0xBD9A, 0xD432, 0xBD9B, 0xD433, 0xBD9C,
+	0xD434, 0xBD9D, 0xD435, 0xBD9E, 0xD436, 0xBD9F, 0xD437, 0xBDA0,	0xD438, 0xBE41, 0xD439, 0xBE42, 0xD43A, 0xBE43, 0xD43B, 0xBE44,
+	0xD43C, 0xBE45, 0xD43D, 0xBE46, 0xD43E, 0xBE47, 0xD43F, 0xBE48,	0xD440, 0xC7A3, 0xD441, 0xBE49, 0xD442, 0xBE4A, 0xD443, 0xBE4B,
+	0xD444, 0xC7A4, 0xD445, 0xBE4C, 0xD446, 0xBE4D, 0xD447, 0xBE4E,	0xD448, 0xBE4F, 0xD449, 0xBE50, 0xD44A, 0xBE51, 0xD44B, 0xBE52,
+	0xD44C, 0xBE53, 0xD44D, 0xBE54, 0xD44E, 0xBE55, 0xD44F, 0xBE56,	0xD450, 0xBE57, 0xD451, 0xBE58, 0xD452, 0xBE59, 0xD453, 0xBE5A,
+	0xD454, 0xBE61, 0xD455, 0xBE62, 0xD456, 0xBE63, 0xD457, 0xBE64,	0xD458, 0xBE65, 0xD459, 0xBE66, 0xD45A, 0xBE67, 0xD45B, 0xBE68,
+	0xD45C, 0xC7A5, 0xD45D, 0xBE69, 0xD45E, 0xBE6A, 0xD45F, 0xBE6B,	0xD460, 0xC7A6, 0xD461, 0xBE6C, 0xD462, 0xBE6D, 0xD463, 0xBE6E,
+	0xD464, 0xC7A7, 0xD465, 0xBE6F, 0xD466, 0xBE70, 0xD467, 0xBE71,	0xD468, 0xBE72, 0xD469, 0xBE73, 0xD46A, 0xBE74, 0xD46B, 0xBE75,
+	0xD46C, 0xBE76, 0xD46D, 0xC7A8, 0xD46E, 0xBE77, 0xD46F, 0xC7A9,	0xD470, 0xBE78, 0xD471, 0xBE79, 0xD472, 0xBE7A, 0xD473, 0xBE81,
+	0xD474, 0xBE82, 0xD475, 0xBE83, 0xD476, 0xBE84, 0xD477, 0xBE85,	0xD478, 0xC7AA, 0xD479, 0xC7AB, 0xD47A, 0xBE86, 0xD47B, 0xBE87,
+	0xD47C, 0xC7AC, 0xD47D, 0xBE88, 0xD47E, 0xBE89, 0xD47F, 0xC7AD,	0xD480, 0xC7AE, 0xD481, 0xBE8A, 0xD482, 0xC7AF, 0xD483, 0xBE8B,
+	0xD484, 0xBE8C, 0xD485, 0xBE8D, 0xD486, 0xBE8E, 0xD487, 0xBE8F,	0xD488, 0xC7B0, 0xD489, 0xC7B1, 0xD48A, 0xBE90, 0xD48B, 0xC7B2,
+	0xD48C, 0xBE91, 0xD48D, 0xC7B3, 0xD48E, 0xBE92, 0xD48F, 0xBE93,	0xD490, 0xBE94, 0xD491, 0xBE95, 0xD492, 0xBE96, 0xD493, 0xBE97,
+	0xD494, 0xC7B4, 0xD495, 0xBE98, 0xD496, 0xBE99, 0xD497, 0xBE9A,	0xD498, 0xBE9B, 0xD499, 0xBE9C, 0xD49A, 0xBE9D, 0xD49B, 0xBE9E,
+	0xD49C, 0xBE9F, 0xD49D, 0xBEA0, 0xD49E, 0xBF41, 0xD49F, 0xBF42,	0xD4A0, 0xBF43, 0xD4A1, 0xBF44, 0xD4A2, 0xBF45, 0xD4A3, 0xBF46,
+	0xD4A4, 0xBF47, 0xD4A5, 0xBF48, 0xD4A6, 0xBF49, 0xD4A7, 0xBF4A,	0xD4A8, 0xBF4B, 0xD4A9, 0xC7B5, 0xD4AA, 0xBF4C, 0xD4AB, 0xBF4D,
+	0xD4AC, 0xBF4E, 0xD4AD, 0xBF4F, 0xD4AE, 0xBF50, 0xD4AF, 0xBF51,	0xD4B0, 0xBF52, 0xD4B1, 0xBF53, 0xD4B2, 0xBF54, 0xD4B3, 0xBF55,
+	0xD4B4, 0xBF56, 0xD4B5, 0xBF57, 0xD4B6, 0xBF58, 0xD4B7, 0xBF59,	0xD4B8, 0xBF5A, 0xD4B9, 0xBF61, 0xD4BA, 0xBF62, 0xD4BB, 0xBF63,
+	0xD4BC, 0xBF64, 0xD4BD, 0xBF65, 0xD4BE, 0xBF66, 0xD4BF, 0xBF67,	0xD4C0, 0xBF68, 0xD4C1, 0xBF69, 0xD4C2, 0xBF6A, 0xD4C3, 0xBF6B,
+	0xD4C4, 0xBF6C, 0xD4C5, 0xBF6D, 0xD4C6, 0xBF6E, 0xD4C7, 0xBF6F,	0xD4C8, 0xBF70, 0xD4C9, 0xBF71, 0xD4CA, 0xBF72, 0xD4CB, 0xBF73,
+	0xD4CC, 0xC7B6, 0xD4CD, 0xBF74, 0xD4CE, 0xBF75, 0xD4CF, 0xBF76,	0xD4D0, 0xC7B7, 0xD4D1, 0xBF77, 0xD4D2, 0xBF78, 0xD4D3, 0xBF79,
+	0xD4D4, 0xC7B8, 0xD4D5, 0xBF7A, 0xD4D6, 0xBF81, 0xD4D7, 0xBF82,	0xD4D8, 0xBF83, 0xD4D9, 0xBF84, 0xD4DA, 0xBF85, 0xD4DB, 0xBF86,
+	0xD4DC, 0xC7B9, 0xD4DD, 0xBF87, 0xD4DE, 0xBF88, 0xD4DF, 0xC7BA,	0xD4E0, 0xBF89, 0xD4E1, 0xBF8A, 0xD4E2, 0xBF8B, 0xD4E3, 0xBF8C,
+	0xD4E4, 0xBF8D, 0xD4E5, 0xBF8E, 0xD4E6, 0xBF8F, 0xD4E7, 0xBF90,	0xD4E8, 0xC7BB, 0xD4E9, 0xBF91, 0xD4EA, 0xBF92, 0xD4EB, 0xBF93,
+	0xD4EC, 0xC7BC, 0xD4ED, 0xBF94, 0xD4EE, 0xBF95, 0xD4EF, 0xBF96,	0xD4F0, 0xC7BD, 0xD4F1, 0xBF97, 0xD4F2, 0xBF98, 0xD4F3, 0xBF99,
+	0xD4F4, 0xBF9A, 0xD4F5, 0xBF9B, 0xD4F6, 0xBF9C, 0xD4F7, 0xBF9D,	0xD4F8, 0xC7BE, 0xD4F9, 0xBF9E, 0xD4FA, 0xBF9F, 0xD4FB, 0xC7BF,
+	0xD4FC, 0xBFA0, 0xD4FD, 0xC7C0, 0xD4FE, 0xC041, 0xD4FF, 0xC042,	0xD500, 0xC043, 0xD501, 0xC044, 0xD502, 0xC045, 0xD503, 0xC046,
+	0xD504, 0xC7C1, 0xD505, 0xC047, 0xD506, 0xC048, 0xD507, 0xC049,	0xD508, 0xC7C2, 0xD509, 0xC04A, 0xD50A, 0xC04B, 0xD50B, 0xC04C,
+	0xD50C, 0xC7C3, 0xD50D, 0xC04D, 0xD50E, 0xC04E, 0xD50F, 0xC04F,	0xD510, 0xC050, 0xD511, 0xC051, 0xD512, 0xC052, 0xD513, 0xC053,
+	0xD514, 0xC7C4, 0xD515, 0xC7C5, 0xD516, 0xC054, 0xD517, 0xC7C6,	0xD518, 0xC055, 0xD519, 0xC056, 0xD51A, 0xC057, 0xD51B, 0xC058,
+	0xD51C, 0xC059, 0xD51D, 0xC05A, 0xD51E, 0xC061, 0xD51F, 0xC062,	0xD520, 0xC063, 0xD521, 0xC064, 0xD522, 0xC065, 0xD523, 0xC066,
+	0xD524, 0xC067, 0xD525, 0xC068, 0xD526, 0xC069, 0xD527, 0xC06A,	0xD528, 0xC06B, 0xD529, 0xC06C, 0xD52A, 0xC06D, 0xD52B, 0xC06E,
+	0xD52C, 0xC06F, 0xD52D, 0xC070, 0xD52E, 0xC071, 0xD52F, 0xC072,	0xD530, 0xC073, 0xD531, 0xC074, 0xD532, 0xC075, 0xD533, 0xC076,
+	0xD534, 0xC077, 0xD535, 0xC078, 0xD536, 0xC079, 0xD537, 0xC07A,	0xD538, 0xC081, 0xD539, 0xC082, 0xD53A, 0xC083, 0xD53B, 0xC084,
+	0xD53C, 0xC7C7, 0xD53D, 0xC7C8, 0xD53E, 0xC085, 0xD53F, 0xC086,	0xD540, 0xC7C9, 0xD541, 0xC087, 0xD542, 0xC088, 0xD543, 0xC089,
+	0xD544, 0xC7CA, 0xD545, 0xC08A, 0xD546, 0xC08B, 0xD547, 0xC08C,	0xD548, 0xC08D, 0xD549, 0xC08E, 0xD54A, 0xC08F, 0xD54B, 0xC090,
+	0xD54C, 0xC7CB, 0xD54D, 0xC7CC, 0xD54E, 0xC091, 0xD54F, 0xC7CD,	0xD550, 0xC092, 0xD551, 0xC7CE, 0xD552, 0xC093, 0xD553, 0xC094,
+	0xD554, 0xC095, 0xD555, 0xC096, 0xD556, 0xC097, 0xD557, 0xC098,	0xD558, 0xC7CF, 0xD559, 0xC7D0, 0xD55A, 0xC099, 0xD55B, 0xC09A,
+	0xD55C, 0xC7D1, 0xD55D, 0xC09B, 0xD55E, 0xC09C, 0xD55F, 0xC09D,	0xD560, 0xC7D2, 0xD561, 0xC09E, 0xD562, 0xC09F, 0xD563, 0xC0A0,
+	0xD564, 0xC141, 0xD565, 0xC7D3, 0xD566, 0xC142, 0xD567, 0xC143,	0xD568, 0xC7D4, 0xD569, 0xC7D5, 0xD56A, 0xC144, 0xD56B, 0xC7D6,
+	0xD56C, 0xC145, 0xD56D, 0xC7D7, 0xD56E, 0xC146, 0xD56F, 0xC147,	0xD570, 0xC148, 0xD571, 0xC149, 0xD572, 0xC14A, 0xD573, 0xC14B,
+	0xD574, 0xC7D8, 0xD575, 0xC7D9, 0xD576, 0xC14C, 0xD577, 0xC14D,	0xD578, 0xC7DA, 0xD579, 0xC14E, 0xD57A, 0xC14F, 0xD57B, 0xC150,
+	0xD57C, 0xC7DB, 0xD57D, 0xC151, 0xD57E, 0xC152, 0xD57F, 0xC153,	0xD580, 0xC154, 0xD581, 0xC155, 0xD582, 0xC156, 0xD583, 0xC157,
+	0xD584, 0xC7DC, 0xD585, 0xC7DD, 0xD586, 0xC158, 0xD587, 0xC7DE,	0xD588, 0xC7DF, 0xD589, 0xC7E0, 0xD58A, 0xC159, 0xD58B, 0xC15A,
+	0xD58C, 0xC161, 0xD58D, 0xC162, 0xD58E, 0xC163, 0xD58F, 0xC164,	0xD590, 0xC7E1, 0xD591, 0xC165, 0xD592, 0xC166, 0xD593, 0xC167,
+	0xD594, 0xC168, 0xD595, 0xC169, 0xD596, 0xC16A, 0xD597, 0xC16B,	0xD598, 0xC16C, 0xD599, 0xC16D, 0xD59A, 0xC16E, 0xD59B, 0xC16F,
+	0xD59C, 0xC170, 0xD59D, 0xC171, 0xD59E, 0xC172, 0xD59F, 0xC173,	0xD5A0, 0xC174, 0xD5A1, 0xC175, 0xD5A2, 0xC176, 0xD5A3, 0xC177,
+	0xD5A4, 0xC178, 0xD5A5, 0xC7E2, 0xD5A6, 0xC179, 0xD5A7, 0xC17A,	0xD5A8, 0xC181, 0xD5A9, 0xC182, 0xD5AA, 0xC183, 0xD5AB, 0xC184,
+	0xD5AC, 0xC185, 0xD5AD, 0xC186, 0xD5AE, 0xC187, 0xD5AF, 0xC188,	0xD5B0, 0xC189, 0xD5B1, 0xC18A, 0xD5B2, 0xC18B, 0xD5B3, 0xC18C,
+	0xD5B4, 0xC18D, 0xD5B5, 0xC18E, 0xD5B6, 0xC18F, 0xD5B7, 0xC190,	0xD5B8, 0xC191, 0xD5B9, 0xC192, 0xD5BA, 0xC193, 0xD5BB, 0xC194,
+	0xD5BC, 0xC195, 0xD5BD, 0xC196, 0xD5BE, 0xC197, 0xD5BF, 0xC198,	0xD5C0, 0xC199, 0xD5C1, 0xC19A, 0xD5C2, 0xC19B, 0xD5C3, 0xC19C,
+	0xD5C4, 0xC19D, 0xD5C5, 0xC19E, 0xD5C6, 0xC19F, 0xD5C7, 0xC1A0,	0xD5C8, 0xC7E3, 0xD5C9, 0xC7E4, 0xD5CA, 0xC241, 0xD5CB, 0xC242,
+	0xD5CC, 0xC7E5, 0xD5CD, 0xC243, 0xD5CE, 0xC244, 0xD5CF, 0xC245,	0xD5D0, 0xC7E6, 0xD5D1, 0xC246, 0xD5D2, 0xC7E7, 0xD5D3, 0xC247,
+	0xD5D4, 0xC248, 0xD5D5, 0xC249, 0xD5D6, 0xC24A, 0xD5D7, 0xC24B,	0xD5D8, 0xC7E8, 0xD5D9, 0xC7E9, 0xD5DA, 0xC24C, 0xD5DB, 0xC7EA,
+	0xD5DC, 0xC24D, 0xD5DD, 0xC7EB, 0xD5DE, 0xC24E, 0xD5DF, 0xC24F,	0xD5E0, 0xC250, 0xD5E1, 0xC251, 0xD5E2, 0xC252, 0xD5E3, 0xC253,
+	0xD5E4, 0xC7EC, 0xD5E5, 0xC7ED, 0xD5E6, 0xC254, 0xD5E7, 0xC255,	0xD5E8, 0xC7EE, 0xD5E9, 0xC256, 0xD5EA, 0xC257, 0xD5EB, 0xC258,
+	0xD5EC, 0xC7EF, 0xD5ED, 0xC259, 0xD5EE, 0xC25A, 0xD5EF, 0xC261,	0xD5F0, 0xC262, 0xD5F1, 0xC263, 0xD5F2, 0xC264, 0xD5F3, 0xC265,
+	0xD5F4, 0xC7F0, 0xD5F5, 0xC7F1, 0xD5F6, 0xC266, 0xD5F7, 0xC7F2,	0xD5F8, 0xC267, 0xD5F9, 0xC7F3, 0xD5FA, 0xC268, 0xD5FB, 0xC269,
+	0xD5FC, 0xC26A, 0xD5FD, 0xC26B, 0xD5FE, 0xC26C, 0xD5FF, 0xC26D,	0xD600, 0xC7F4, 0xD601, 0xC7F5, 0xD602, 0xC26E, 0xD603, 0xC26F,
+	0xD604, 0xC7F6, 0xD605, 0xC270, 0xD606, 0xC271, 0xD607, 0xC272,	0xD608, 0xC7F7, 0xD609, 0xC273, 0xD60A, 0xC274, 0xD60B, 0xC275,
+	0xD60C, 0xC276, 0xD60D, 0xC277, 0xD60E, 0xC278, 0xD60F, 0xC279,	0xD610, 0xC7F8, 0xD611, 0xC7F9, 0xD612, 0xC27A, 0xD613, 0xC7FA,
+	0xD614, 0xC7FB, 0xD615, 0xC7FC, 0xD616, 0xC281, 0xD617, 0xC282,	0xD618, 0xC283, 0xD619, 0xC284, 0xD61A, 0xC285, 0xD61B, 0xC286,
+	0xD61C, 0xC7FD, 0xD61D, 0xC287, 0xD61E, 0xC288, 0xD61F, 0xC289,	0xD620, 0xC7FE, 0xD621, 0xC28A, 0xD622, 0xC28B, 0xD623, 0xC28C,
+	0xD624, 0xC8A1, 0xD625, 0xC28D, 0xD626, 0xC28E, 0xD627, 0xC28F,	0xD628, 0xC290, 0xD629, 0xC291, 0xD62A, 0xC292, 0xD62B, 0xC293,
+	0xD62C, 0xC294, 0xD62D, 0xC8A2, 0xD62E, 0xC295, 0xD62F, 0xC296,	0xD630, 0xC297, 0xD631, 0xC298, 0xD632, 0xC299, 0xD633, 0xC29A,
+	0xD634, 0xC29B, 0xD635, 0xC29C, 0xD636, 0xC29D, 0xD637, 0xC29E,	0xD638, 0xC8A3, 0xD639, 0xC8A4, 0xD63A, 0xC29F, 0xD63B, 0xC2A0,
+	0xD63C, 0xC8A5, 0xD63D, 0xC341, 0xD63E, 0xC342, 0xD63F, 0xC343,	0xD640, 0xC8A6, 0xD641, 0xC344, 0xD642, 0xC345, 0xD643, 0xC346,
+	0xD644, 0xC347, 0xD645, 0xC8A7, 0xD646, 0xC348, 0xD647, 0xC349,	0xD648, 0xC8A8, 0xD649, 0xC8A9, 0xD64A, 0xC34A, 0xD64B, 0xC8AA,
+	0xD64C, 0xC34B, 0xD64D, 0xC8AB, 0xD64E, 0xC34C, 0xD64F, 0xC34D,	0xD650, 0xC34E, 0xD651, 0xC8AC, 0xD652, 0xC34F, 0xD653, 0xC350,
+	0xD654, 0xC8AD, 0xD655, 0xC8AE, 0xD656, 0xC351, 0xD657, 0xC352,	0xD658, 0xC8AF, 0xD659, 0xC353, 0xD65A, 0xC354, 0xD65B, 0xC355,
+	0xD65C, 0xC8B0, 0xD65D, 0xC356, 0xD65E, 0xC357, 0xD65F, 0xC358,	0xD660, 0xC359, 0xD661, 0xC35A, 0xD662, 0xC361, 0xD663, 0xC362,
+	0xD664, 0xC363, 0xD665, 0xC364, 0xD666, 0xC365, 0xD667, 0xC8B1,	0xD668, 0xC366, 0xD669, 0xC8B2, 0xD66A, 0xC367, 0xD66B, 0xC368,
+	0xD66C, 0xC369, 0xD66D, 0xC36A, 0xD66E, 0xC36B, 0xD66F, 0xC36C,	0xD670, 0xC8B3, 0xD671, 0xC8B4, 0xD672, 0xC36D, 0xD673, 0xC36E,
+	0xD674, 0xC8B5, 0xD675, 0xC36F, 0xD676, 0xC370, 0xD677, 0xC371,	0xD678, 0xC372, 0xD679, 0xC373, 0xD67A, 0xC374, 0xD67B, 0xC375,
+	0xD67C, 0xC376, 0xD67D, 0xC377, 0xD67E, 0xC378, 0xD67F, 0xC379,	0xD680, 0xC37A, 0xD681, 0xC381, 0xD682, 0xC382, 0xD683, 0xC8B6,
+	0xD684, 0xC383, 0xD685, 0xC8B7, 0xD686, 0xC384, 0xD687, 0xC385,	0xD688, 0xC386, 0xD689, 0xC387, 0xD68A, 0xC388, 0xD68B, 0xC389,
+	0xD68C, 0xC8B8, 0xD68D, 0xC8B9, 0xD68E, 0xC38A, 0xD68F, 0xC38B,	0xD690, 0xC8BA, 0xD691, 0xC38C, 0xD692, 0xC38D, 0xD693, 0xC38E,
+	0xD694, 0xC8BB, 0xD695, 0xC38F, 0xD696, 0xC390, 0xD697, 0xC391,	0xD698, 0xC392, 0xD699, 0xC393, 0xD69A, 0xC394, 0xD69B, 0xC395,
+	0xD69C, 0xC396, 0xD69D, 0xC8BC, 0xD69E, 0xC397, 0xD69F, 0xC8BD,	0xD6A0, 0xC398, 0xD6A1, 0xC8BE, 0xD6A2, 0xC399, 0xD6A3, 0xC39A,
+	0xD6A4, 0xC39B, 0xD6A5, 0xC39C, 0xD6A6, 0xC39D, 0xD6A7, 0xC39E,	0xD6A8, 0xC8BF, 0xD6A9, 0xC39F, 0xD6AA, 0xC3A0, 0xD6AB, 0xC441,
+	0xD6AC, 0xC8C0, 0xD6AD, 0xC442, 0xD6AE, 0xC443, 0xD6AF, 0xC444,	0xD6B0, 0xC8C1, 0xD6B1, 0xC445, 0xD6B2, 0xC446, 0xD6B3, 0xC447,
+	0xD6B4, 0xC448, 0xD6B5, 0xC449, 0xD6B6, 0xC44A, 0xD6B7, 0xC44B,	0xD6B8, 0xC44C, 0xD6B9, 0xC8C2, 0xD6BA, 0xC44D, 0xD6BB, 0xC8C3,
+	0xD6BC, 0xC44E, 0xD6BD, 0xC44F, 0xD6BE, 0xC450, 0xD6BF, 0xC451,	0xD6C0, 0xC452, 0xD6C1, 0xC453, 0xD6C2, 0xC454, 0xD6C3, 0xC455,
+	0xD6C4, 0xC8C4, 0xD6C5, 0xC8C5, 0xD6C6, 0xC456, 0xD6C7, 0xC457,	0xD6C8, 0xC8C6, 0xD6C9, 0xC458, 0xD6CA, 0xC459, 0xD6CB, 0xC45A,
+	0xD6CC, 0xC8C7, 0xD6CD, 0xC461, 0xD6CE, 0xC462, 0xD6CF, 0xC463,	0xD6D0, 0xC464, 0xD6D1, 0xC8C8, 0xD6D2, 0xC465, 0xD6D3, 0xC466,
+	0xD6D4, 0xC8C9, 0xD6D5, 0xC467, 0xD6D6, 0xC468, 0xD6D7, 0xC8CA,	0xD6D8, 0xC469, 0xD6D9, 0xC8CB, 0xD6DA, 0xC46A, 0xD6DB, 0xC46B,
+	0xD6DC, 0xC46C, 0xD6DD, 0xC46D, 0xD6DE, 0xC46E, 0xD6DF, 0xC46F,	0xD6E0, 0xC8CC, 0xD6E1, 0xC470, 0xD6E2, 0xC471, 0xD6E3, 0xC472,
+	0xD6E4, 0xC8CD, 0xD6E5, 0xC473, 0xD6E6, 0xC474, 0xD6E7, 0xC475,	0xD6E8, 0xC8CE, 0xD6E9, 0xC476, 0xD6EA, 0xC477, 0xD6EB, 0xC478,
+	0xD6EC, 0xC479, 0xD6ED, 0xC47A, 0xD6EE, 0xC481, 0xD6EF, 0xC482,	0xD6F0, 0xC8CF, 0xD6F1, 0xC483, 0xD6F2, 0xC484, 0xD6F3, 0xC485,
+	0xD6F4, 0xC486, 0xD6F5, 0xC8D0, 0xD6F6, 0xC487, 0xD6F7, 0xC488,	0xD6F8, 0xC489, 0xD6F9, 0xC48A, 0xD6FA, 0xC48B, 0xD6FB, 0xC48C,
+	0xD6FC, 0xC8D1, 0xD6FD, 0xC8D2, 0xD6FE, 0xC48D, 0xD6FF, 0xC48E,	0xD700, 0xC8D3, 0xD701, 0xC48F, 0xD702, 0xC490, 0xD703, 0xC491,
+	0xD704, 0xC8D4, 0xD705, 0xC492, 0xD706, 0xC493, 0xD707, 0xC494,	0xD708, 0xC495, 0xD709, 0xC496, 0xD70A, 0xC497, 0xD70B, 0xC498,
+	0xD70C, 0xC499, 0xD70D, 0xC49A, 0xD70E, 0xC49B, 0xD70F, 0xC49C,	0xD710, 0xC49D, 0xD711, 0xC8D5, 0xD712, 0xC49E, 0xD713, 0xC49F,
+	0xD714, 0xC4A0, 0xD715, 0xC541, 0xD716, 0xC542, 0xD717, 0xC543,	0xD718, 0xC8D6, 0xD719, 0xC8D7, 0xD71A, 0xC544, 0xD71B, 0xC545,
+	0xD71C, 0xC8D8, 0xD71D, 0xC546, 0xD71E, 0xC547, 0xD71F, 0xC548,	0xD720, 0xC8D9, 0xD721, 0xC549, 0xD722, 0xC54A, 0xD723, 0xC54B,
+	0xD724, 0xC54C, 0xD725, 0xC54D, 0xD726, 0xC54E, 0xD727, 0xC54F,	0xD728, 0xC8DA, 0xD729, 0xC8DB, 0xD72A, 0xC550, 0xD72B, 0xC8DC,
+	0xD72C, 0xC551, 0xD72D, 0xC8DD, 0xD72E, 0xC552, 0xD72F, 0xC553,	0xD730, 0xC554, 0xD731, 0xC555, 0xD732, 0xC556, 0xD733, 0xC557,
+	0xD734, 0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559,	0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562,
+	0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565,	0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569,
+	0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3,	0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E,
+	0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572,	0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574,
+	0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9,	0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577,
+	0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581,	0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE,
+	0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585,	0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588,
+	0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B,	0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E,
+	0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591,	0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595,
+	0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597,	0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A,
+	0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E,	0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0,
+	0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643,	0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646,
+	0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A,	0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD,
+	0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E,	0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652,
+	0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF,	0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2,
+	0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4,	0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC,
+	0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0,	0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5,
+	0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA,	0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0,
+	0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC,	0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3,
+	0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA,	0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE,
+	0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6,	0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA,
+	0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF,	0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3,
+	0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7,	0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF,
+	0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5,	0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9,
+	0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1,	0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5,
+	0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC,	0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8,
+	0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5,	0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5,
+	0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3,	0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD,
+	0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9,	0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9,
+	0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE,	0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA,
+	0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1,	0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF,
+	0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7,	0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6,
+	0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6,	0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1,
+	0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8,	0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF,
+	0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6,	0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6,
+	0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD,	0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6,
+	0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF,	0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4,
+	0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8,	0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9,
+	0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC,	0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5,
+	0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE,	0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA,
+	0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1,	0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC,
+	0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2,	0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA,
+	0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2,	0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0,
+	0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9,	0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE,
+	0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8,	0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1,
+	0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB,	0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7,
+	0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8,	0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0,
+	0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9,	0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4,
+	0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8,	0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+	0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0,	0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+	0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8,	0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+	0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0,	0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+	0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8,	0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+	0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0,	0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+	0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8,	0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC,
+	0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0,	0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+	0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8,	0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+	0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0,	0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+	0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8,	0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+	0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC,	0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC,
+	0, 0
+};
+
+static const WCHAR oem2uni949[] = {	/* Korean --> Unicode pairs */
+	0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06,	0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E,
+	0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F,	0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25,
+	0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29,	0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32,
+	0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36,	0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D,
+	0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42,	0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46,
+	0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A,	0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50,
+	0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55,	0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A,
+	0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F,	0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63,
+	0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67,	0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B,
+	0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F,	0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76,
+	0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D,	0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87,
+	0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F,	0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95,
+	0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99,	0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2,
+	0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6,	0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE,
+	0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4,	0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA,
+	0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2,	0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7,
+	0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD,	0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1,
+	0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6,	0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB,
+	0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF,	0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6,
+	0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE,	0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8,
+	0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE,	0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03,
+	0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09,	0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10,
+	0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15,	0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A,
+	0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F,	0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24,
+	0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28,	0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F,
+	0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33,	0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A,
+	0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F,	0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43,
+	0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B,	0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F,
+	0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55,	0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A,
+	0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E,	0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64,
+	0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68,	0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E,
+	0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77,	0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E,
+	0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85,	0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B,
+	0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91,	0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95,
+	0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99,	0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F,
+	0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3,	0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8,
+	0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC,	0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0,
+	0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4,	0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9,
+	0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 0xADBD,	0x82CF, 0xADBE, 0x82D0, 0xADBF, 0x82D1, 0xADC2, 0x82D2, 0xADC3,
+	0x82D3, 0xADC5, 0x82D4, 0xADC6, 0x82D5, 0xADC7, 0x82D6, 0xADC9,	0x82D7, 0xADCA, 0x82D8, 0xADCB, 0x82D9, 0xADCC, 0x82DA, 0xADCD,
+	0x82DB, 0xADCE, 0x82DC, 0xADCF, 0x82DD, 0xADD2, 0x82DE, 0xADD4,	0x82DF, 0xADD5, 0x82E0, 0xADD6, 0x82E1, 0xADD7, 0x82E2, 0xADD8,
+	0x82E3, 0xADD9, 0x82E4, 0xADDA, 0x82E5, 0xADDB, 0x82E6, 0xADDD,	0x82E7, 0xADDE, 0x82E8, 0xADDF, 0x82E9, 0xADE1, 0x82EA, 0xADE2,
+	0x82EB, 0xADE3, 0x82EC, 0xADE5, 0x82ED, 0xADE6, 0x82EE, 0xADE7,	0x82EF, 0xADE8, 0x82F0, 0xADE9, 0x82F1, 0xADEA, 0x82F2, 0xADEB,
+	0x82F3, 0xADEC, 0x82F4, 0xADED, 0x82F5, 0xADEE, 0x82F6, 0xADEF,	0x82F7, 0xADF0, 0x82F8, 0xADF1, 0x82F9, 0xADF2, 0x82FA, 0xADF3,
+	0x82FB, 0xADF4, 0x82FC, 0xADF5, 0x82FD, 0xADF6, 0x82FE, 0xADF7,	0x8341, 0xADFA, 0x8342, 0xADFB, 0x8343, 0xADFD, 0x8344, 0xADFE,
+	0x8345, 0xAE02, 0x8346, 0xAE03, 0x8347, 0xAE04, 0x8348, 0xAE05,	0x8349, 0xAE06, 0x834A, 0xAE07, 0x834B, 0xAE0A, 0x834C, 0xAE0C,
+	0x834D, 0xAE0E, 0x834E, 0xAE0F, 0x834F, 0xAE10, 0x8350, 0xAE11,	0x8351, 0xAE12, 0x8352, 0xAE13, 0x8353, 0xAE15, 0x8354, 0xAE16,
+	0x8355, 0xAE17, 0x8356, 0xAE18, 0x8357, 0xAE19, 0x8358, 0xAE1A,	0x8359, 0xAE1B, 0x835A, 0xAE1C, 0x8361, 0xAE1D, 0x8362, 0xAE1E,
+	0x8363, 0xAE1F, 0x8364, 0xAE20, 0x8365, 0xAE21, 0x8366, 0xAE22,	0x8367, 0xAE23, 0x8368, 0xAE24, 0x8369, 0xAE25, 0x836A, 0xAE26,
+	0x836B, 0xAE27, 0x836C, 0xAE28, 0x836D, 0xAE29, 0x836E, 0xAE2A,	0x836F, 0xAE2B, 0x8370, 0xAE2C, 0x8371, 0xAE2D, 0x8372, 0xAE2E,
+	0x8373, 0xAE2F, 0x8374, 0xAE32, 0x8375, 0xAE33, 0x8376, 0xAE35,	0x8377, 0xAE36, 0x8378, 0xAE39, 0x8379, 0xAE3B, 0x837A, 0xAE3C,
+	0x8381, 0xAE3D, 0x8382, 0xAE3E, 0x8383, 0xAE3F, 0x8384, 0xAE42,	0x8385, 0xAE44, 0x8386, 0xAE47, 0x8387, 0xAE48, 0x8388, 0xAE49,
+	0x8389, 0xAE4B, 0x838A, 0xAE4F, 0x838B, 0xAE51, 0x838C, 0xAE52,	0x838D, 0xAE53, 0x838E, 0xAE55, 0x838F, 0xAE57, 0x8390, 0xAE58,
+	0x8391, 0xAE59, 0x8392, 0xAE5A, 0x8393, 0xAE5B, 0x8394, 0xAE5E,	0x8395, 0xAE62, 0x8396, 0xAE63, 0x8397, 0xAE64, 0x8398, 0xAE66,
+	0x8399, 0xAE67, 0x839A, 0xAE6A, 0x839B, 0xAE6B, 0x839C, 0xAE6D,	0x839D, 0xAE6E, 0x839E, 0xAE6F, 0x839F, 0xAE71, 0x83A0, 0xAE72,
+	0x83A1, 0xAE73, 0x83A2, 0xAE74, 0x83A3, 0xAE75, 0x83A4, 0xAE76,	0x83A5, 0xAE77, 0x83A6, 0xAE7A, 0x83A7, 0xAE7E, 0x83A8, 0xAE7F,
+	0x83A9, 0xAE80, 0x83AA, 0xAE81, 0x83AB, 0xAE82, 0x83AC, 0xAE83,	0x83AD, 0xAE86, 0x83AE, 0xAE87, 0x83AF, 0xAE88, 0x83B0, 0xAE89,
+	0x83B1, 0xAE8A, 0x83B2, 0xAE8B, 0x83B3, 0xAE8D, 0x83B4, 0xAE8E,	0x83B5, 0xAE8F, 0x83B6, 0xAE90, 0x83B7, 0xAE91, 0x83B8, 0xAE92,
+	0x83B9, 0xAE93, 0x83BA, 0xAE94, 0x83BB, 0xAE95, 0x83BC, 0xAE96,	0x83BD, 0xAE97, 0x83BE, 0xAE98, 0x83BF, 0xAE99, 0x83C0, 0xAE9A,
+	0x83C1, 0xAE9B, 0x83C2, 0xAE9C, 0x83C3, 0xAE9D, 0x83C4, 0xAE9E,	0x83C5, 0xAE9F, 0x83C6, 0xAEA0, 0x83C7, 0xAEA1, 0x83C8, 0xAEA2,
+	0x83C9, 0xAEA3, 0x83CA, 0xAEA4, 0x83CB, 0xAEA5, 0x83CC, 0xAEA6,	0x83CD, 0xAEA7, 0x83CE, 0xAEA8, 0x83CF, 0xAEA9, 0x83D0, 0xAEAA,
+	0x83D1, 0xAEAB, 0x83D2, 0xAEAC, 0x83D3, 0xAEAD, 0x83D4, 0xAEAE,	0x83D5, 0xAEAF, 0x83D6, 0xAEB0, 0x83D7, 0xAEB1, 0x83D8, 0xAEB2,
+	0x83D9, 0xAEB3, 0x83DA, 0xAEB4, 0x83DB, 0xAEB5, 0x83DC, 0xAEB6,	0x83DD, 0xAEB7, 0x83DE, 0xAEB8, 0x83DF, 0xAEB9, 0x83E0, 0xAEBA,
+	0x83E1, 0xAEBB, 0x83E2, 0xAEBF, 0x83E3, 0xAEC1, 0x83E4, 0xAEC2,	0x83E5, 0xAEC3, 0x83E6, 0xAEC5, 0x83E7, 0xAEC6, 0x83E8, 0xAEC7,
+	0x83E9, 0xAEC8, 0x83EA, 0xAEC9, 0x83EB, 0xAECA, 0x83EC, 0xAECB,	0x83ED, 0xAECE, 0x83EE, 0xAED2, 0x83EF, 0xAED3, 0x83F0, 0xAED4,
+	0x83F1, 0xAED5, 0x83F2, 0xAED6, 0x83F3, 0xAED7, 0x83F4, 0xAEDA,	0x83F5, 0xAEDB, 0x83F6, 0xAEDD, 0x83F7, 0xAEDE, 0x83F8, 0xAEDF,
+	0x83F9, 0xAEE0, 0x83FA, 0xAEE1, 0x83FB, 0xAEE2, 0x83FC, 0xAEE3,	0x83FD, 0xAEE4, 0x83FE, 0xAEE5, 0x8441, 0xAEE6, 0x8442, 0xAEE7,
+	0x8443, 0xAEE9, 0x8444, 0xAEEA, 0x8445, 0xAEEC, 0x8446, 0xAEEE,	0x8447, 0xAEEF, 0x8448, 0xAEF0, 0x8449, 0xAEF1, 0x844A, 0xAEF2,
+	0x844B, 0xAEF3, 0x844C, 0xAEF5, 0x844D, 0xAEF6, 0x844E, 0xAEF7,	0x844F, 0xAEF9, 0x8450, 0xAEFA, 0x8451, 0xAEFB, 0x8452, 0xAEFD,
+	0x8453, 0xAEFE, 0x8454, 0xAEFF, 0x8455, 0xAF00, 0x8456, 0xAF01,	0x8457, 0xAF02, 0x8458, 0xAF03, 0x8459, 0xAF04, 0x845A, 0xAF05,
+	0x8461, 0xAF06, 0x8462, 0xAF09, 0x8463, 0xAF0A, 0x8464, 0xAF0B,	0x8465, 0xAF0C, 0x8466, 0xAF0E, 0x8467, 0xAF0F, 0x8468, 0xAF11,
+	0x8469, 0xAF12, 0x846A, 0xAF13, 0x846B, 0xAF14, 0x846C, 0xAF15,	0x846D, 0xAF16, 0x846E, 0xAF17, 0x846F, 0xAF18, 0x8470, 0xAF19,
+	0x8471, 0xAF1A, 0x8472, 0xAF1B, 0x8473, 0xAF1C, 0x8474, 0xAF1D,	0x8475, 0xAF1E, 0x8476, 0xAF1F, 0x8477, 0xAF20, 0x8478, 0xAF21,
+	0x8479, 0xAF22, 0x847A, 0xAF23, 0x8481, 0xAF24, 0x8482, 0xAF25,	0x8483, 0xAF26, 0x8484, 0xAF27, 0x8485, 0xAF28, 0x8486, 0xAF29,
+	0x8487, 0xAF2A, 0x8488, 0xAF2B, 0x8489, 0xAF2E, 0x848A, 0xAF2F,	0x848B, 0xAF31, 0x848C, 0xAF33, 0x848D, 0xAF35, 0x848E, 0xAF36,
+	0x848F, 0xAF37, 0x8490, 0xAF38, 0x8491, 0xAF39, 0x8492, 0xAF3A,	0x8493, 0xAF3B, 0x8494, 0xAF3E, 0x8495, 0xAF40, 0x8496, 0xAF44,
+	0x8497, 0xAF45, 0x8498, 0xAF46, 0x8499, 0xAF47, 0x849A, 0xAF4A,	0x849B, 0xAF4B, 0x849C, 0xAF4C, 0x849D, 0xAF4D, 0x849E, 0xAF4E,
+	0x849F, 0xAF4F, 0x84A0, 0xAF51, 0x84A1, 0xAF52, 0x84A2, 0xAF53,	0x84A3, 0xAF54, 0x84A4, 0xAF55, 0x84A5, 0xAF56, 0x84A6, 0xAF57,
+	0x84A7, 0xAF58, 0x84A8, 0xAF59, 0x84A9, 0xAF5A, 0x84AA, 0xAF5B,	0x84AB, 0xAF5E, 0x84AC, 0xAF5F, 0x84AD, 0xAF60, 0x84AE, 0xAF61,
+	0x84AF, 0xAF62, 0x84B0, 0xAF63, 0x84B1, 0xAF66, 0x84B2, 0xAF67,	0x84B3, 0xAF68, 0x84B4, 0xAF69, 0x84B5, 0xAF6A, 0x84B6, 0xAF6B,
+	0x84B7, 0xAF6C, 0x84B8, 0xAF6D, 0x84B9, 0xAF6E, 0x84BA, 0xAF6F,	0x84BB, 0xAF70, 0x84BC, 0xAF71, 0x84BD, 0xAF72, 0x84BE, 0xAF73,
+	0x84BF, 0xAF74, 0x84C0, 0xAF75, 0x84C1, 0xAF76, 0x84C2, 0xAF77,	0x84C3, 0xAF78, 0x84C4, 0xAF7A, 0x84C5, 0xAF7B, 0x84C6, 0xAF7C,
+	0x84C7, 0xAF7D, 0x84C8, 0xAF7E, 0x84C9, 0xAF7F, 0x84CA, 0xAF81,	0x84CB, 0xAF82, 0x84CC, 0xAF83, 0x84CD, 0xAF85, 0x84CE, 0xAF86,
+	0x84CF, 0xAF87, 0x84D0, 0xAF89, 0x84D1, 0xAF8A, 0x84D2, 0xAF8B,	0x84D3, 0xAF8C, 0x84D4, 0xAF8D, 0x84D5, 0xAF8E, 0x84D6, 0xAF8F,
+	0x84D7, 0xAF92, 0x84D8, 0xAF93, 0x84D9, 0xAF94, 0x84DA, 0xAF96,	0x84DB, 0xAF97, 0x84DC, 0xAF98, 0x84DD, 0xAF99, 0x84DE, 0xAF9A,
+	0x84DF, 0xAF9B, 0x84E0, 0xAF9D, 0x84E1, 0xAF9E, 0x84E2, 0xAF9F,	0x84E3, 0xAFA0, 0x84E4, 0xAFA1, 0x84E5, 0xAFA2, 0x84E6, 0xAFA3,
+	0x84E7, 0xAFA4, 0x84E8, 0xAFA5, 0x84E9, 0xAFA6, 0x84EA, 0xAFA7,	0x84EB, 0xAFA8, 0x84EC, 0xAFA9, 0x84ED, 0xAFAA, 0x84EE, 0xAFAB,
+	0x84EF, 0xAFAC, 0x84F0, 0xAFAD, 0x84F1, 0xAFAE, 0x84F2, 0xAFAF,	0x84F3, 0xAFB0, 0x84F4, 0xAFB1, 0x84F5, 0xAFB2, 0x84F6, 0xAFB3,
+	0x84F7, 0xAFB4, 0x84F8, 0xAFB5, 0x84F9, 0xAFB6, 0x84FA, 0xAFB7,	0x84FB, 0xAFBA, 0x84FC, 0xAFBB, 0x84FD, 0xAFBD, 0x84FE, 0xAFBE,
+	0x8541, 0xAFBF, 0x8542, 0xAFC1, 0x8543, 0xAFC2, 0x8544, 0xAFC3,	0x8545, 0xAFC4, 0x8546, 0xAFC5, 0x8547, 0xAFC6, 0x8548, 0xAFCA,
+	0x8549, 0xAFCC, 0x854A, 0xAFCF, 0x854B, 0xAFD0, 0x854C, 0xAFD1,	0x854D, 0xAFD2, 0x854E, 0xAFD3, 0x854F, 0xAFD5, 0x8550, 0xAFD6,
+	0x8551, 0xAFD7, 0x8552, 0xAFD8, 0x8553, 0xAFD9, 0x8554, 0xAFDA,	0x8555, 0xAFDB, 0x8556, 0xAFDD, 0x8557, 0xAFDE, 0x8558, 0xAFDF,
+	0x8559, 0xAFE0, 0x855A, 0xAFE1, 0x8561, 0xAFE2, 0x8562, 0xAFE3,	0x8563, 0xAFE4, 0x8564, 0xAFE5, 0x8565, 0xAFE6, 0x8566, 0xAFE7,
+	0x8567, 0xAFEA, 0x8568, 0xAFEB, 0x8569, 0xAFEC, 0x856A, 0xAFED,	0x856B, 0xAFEE, 0x856C, 0xAFEF, 0x856D, 0xAFF2, 0x856E, 0xAFF3,
+	0x856F, 0xAFF5, 0x8570, 0xAFF6, 0x8571, 0xAFF7, 0x8572, 0xAFF9,	0x8573, 0xAFFA, 0x8574, 0xAFFB, 0x8575, 0xAFFC, 0x8576, 0xAFFD,
+	0x8577, 0xAFFE, 0x8578, 0xAFFF, 0x8579, 0xB002, 0x857A, 0xB003,	0x8581, 0xB005, 0x8582, 0xB006, 0x8583, 0xB007, 0x8584, 0xB008,
+	0x8585, 0xB009, 0x8586, 0xB00A, 0x8587, 0xB00B, 0x8588, 0xB00D,	0x8589, 0xB00E, 0x858A, 0xB00F, 0x858B, 0xB011, 0x858C, 0xB012,
+	0x858D, 0xB013, 0x858E, 0xB015, 0x858F, 0xB016, 0x8590, 0xB017,	0x8591, 0xB018, 0x8592, 0xB019, 0x8593, 0xB01A, 0x8594, 0xB01B,
+	0x8595, 0xB01E, 0x8596, 0xB01F, 0x8597, 0xB020, 0x8598, 0xB021,	0x8599, 0xB022, 0x859A, 0xB023, 0x859B, 0xB024, 0x859C, 0xB025,
+	0x859D, 0xB026, 0x859E, 0xB027, 0x859F, 0xB029, 0x85A0, 0xB02A,	0x85A1, 0xB02B, 0x85A2, 0xB02C, 0x85A3, 0xB02D, 0x85A4, 0xB02E,
+	0x85A5, 0xB02F, 0x85A6, 0xB030, 0x85A7, 0xB031, 0x85A8, 0xB032,	0x85A9, 0xB033, 0x85AA, 0xB034, 0x85AB, 0xB035, 0x85AC, 0xB036,
+	0x85AD, 0xB037, 0x85AE, 0xB038, 0x85AF, 0xB039, 0x85B0, 0xB03A,	0x85B1, 0xB03B, 0x85B2, 0xB03C, 0x85B3, 0xB03D, 0x85B4, 0xB03E,
+	0x85B5, 0xB03F, 0x85B6, 0xB040, 0x85B7, 0xB041, 0x85B8, 0xB042,	0x85B9, 0xB043, 0x85BA, 0xB046, 0x85BB, 0xB047, 0x85BC, 0xB049,
+	0x85BD, 0xB04B, 0x85BE, 0xB04D, 0x85BF, 0xB04F, 0x85C0, 0xB050,	0x85C1, 0xB051, 0x85C2, 0xB052, 0x85C3, 0xB056, 0x85C4, 0xB058,
+	0x85C5, 0xB05A, 0x85C6, 0xB05B, 0x85C7, 0xB05C, 0x85C8, 0xB05E,	0x85C9, 0xB05F, 0x85CA, 0xB060, 0x85CB, 0xB061, 0x85CC, 0xB062,
+	0x85CD, 0xB063, 0x85CE, 0xB064, 0x85CF, 0xB065, 0x85D0, 0xB066,	0x85D1, 0xB067, 0x85D2, 0xB068, 0x85D3, 0xB069, 0x85D4, 0xB06A,
+	0x85D5, 0xB06B, 0x85D6, 0xB06C, 0x85D7, 0xB06D, 0x85D8, 0xB06E,	0x85D9, 0xB06F, 0x85DA, 0xB070, 0x85DB, 0xB071, 0x85DC, 0xB072,
+	0x85DD, 0xB073, 0x85DE, 0xB074, 0x85DF, 0xB075, 0x85E0, 0xB076,	0x85E1, 0xB077, 0x85E2, 0xB078, 0x85E3, 0xB079, 0x85E4, 0xB07A,
+	0x85E5, 0xB07B, 0x85E6, 0xB07E, 0x85E7, 0xB07F, 0x85E8, 0xB081,	0x85E9, 0xB082, 0x85EA, 0xB083, 0x85EB, 0xB085, 0x85EC, 0xB086,
+	0x85ED, 0xB087, 0x85EE, 0xB088, 0x85EF, 0xB089, 0x85F0, 0xB08A,	0x85F1, 0xB08B, 0x85F2, 0xB08E, 0x85F3, 0xB090, 0x85F4, 0xB092,
+	0x85F5, 0xB093, 0x85F6, 0xB094, 0x85F7, 0xB095, 0x85F8, 0xB096,	0x85F9, 0xB097, 0x85FA, 0xB09B, 0x85FB, 0xB09D, 0x85FC, 0xB09E,
+	0x85FD, 0xB0A3, 0x85FE, 0xB0A4, 0x8641, 0xB0A5, 0x8642, 0xB0A6,	0x8643, 0xB0A7, 0x8644, 0xB0AA, 0x8645, 0xB0B0, 0x8646, 0xB0B2,
+	0x8647, 0xB0B6, 0x8648, 0xB0B7, 0x8649, 0xB0B9, 0x864A, 0xB0BA,	0x864B, 0xB0BB, 0x864C, 0xB0BD, 0x864D, 0xB0BE, 0x864E, 0xB0BF,
+	0x864F, 0xB0C0, 0x8650, 0xB0C1, 0x8651, 0xB0C2, 0x8652, 0xB0C3,	0x8653, 0xB0C6, 0x8654, 0xB0CA, 0x8655, 0xB0CB, 0x8656, 0xB0CC,
+	0x8657, 0xB0CD, 0x8658, 0xB0CE, 0x8659, 0xB0CF, 0x865A, 0xB0D2,	0x8661, 0xB0D3, 0x8662, 0xB0D5, 0x8663, 0xB0D6, 0x8664, 0xB0D7,
+	0x8665, 0xB0D9, 0x8666, 0xB0DA, 0x8667, 0xB0DB, 0x8668, 0xB0DC,	0x8669, 0xB0DD, 0x866A, 0xB0DE, 0x866B, 0xB0DF, 0x866C, 0xB0E1,
+	0x866D, 0xB0E2, 0x866E, 0xB0E3, 0x866F, 0xB0E4, 0x8670, 0xB0E6,	0x8671, 0xB0E7, 0x8672, 0xB0E8, 0x8673, 0xB0E9, 0x8674, 0xB0EA,
+	0x8675, 0xB0EB, 0x8676, 0xB0EC, 0x8677, 0xB0ED, 0x8678, 0xB0EE,	0x8679, 0xB0EF, 0x867A, 0xB0F0, 0x8681, 0xB0F1, 0x8682, 0xB0F2,
+	0x8683, 0xB0F3, 0x8684, 0xB0F4, 0x8685, 0xB0F5, 0x8686, 0xB0F6,	0x8687, 0xB0F7, 0x8688, 0xB0F8, 0x8689, 0xB0F9, 0x868A, 0xB0FA,
+	0x868B, 0xB0FB, 0x868C, 0xB0FC, 0x868D, 0xB0FD, 0x868E, 0xB0FE,	0x868F, 0xB0FF, 0x8690, 0xB100, 0x8691, 0xB101, 0x8692, 0xB102,
+	0x8693, 0xB103, 0x8694, 0xB104, 0x8695, 0xB105, 0x8696, 0xB106,	0x8697, 0xB107, 0x8698, 0xB10A, 0x8699, 0xB10D, 0x869A, 0xB10E,
+	0x869B, 0xB10F, 0x869C, 0xB111, 0x869D, 0xB114, 0x869E, 0xB115,	0x869F, 0xB116, 0x86A0, 0xB117, 0x86A1, 0xB11A, 0x86A2, 0xB11E,
+	0x86A3, 0xB11F, 0x86A4, 0xB120, 0x86A5, 0xB121, 0x86A6, 0xB122,	0x86A7, 0xB126, 0x86A8, 0xB127, 0x86A9, 0xB129, 0x86AA, 0xB12A,
+	0x86AB, 0xB12B, 0x86AC, 0xB12D, 0x86AD, 0xB12E, 0x86AE, 0xB12F,	0x86AF, 0xB130, 0x86B0, 0xB131, 0x86B1, 0xB132, 0x86B2, 0xB133,
+	0x86B3, 0xB136, 0x86B4, 0xB13A, 0x86B5, 0xB13B, 0x86B6, 0xB13C,	0x86B7, 0xB13D, 0x86B8, 0xB13E, 0x86B9, 0xB13F, 0x86BA, 0xB142,
+	0x86BB, 0xB143, 0x86BC, 0xB145, 0x86BD, 0xB146, 0x86BE, 0xB147,	0x86BF, 0xB149, 0x86C0, 0xB14A, 0x86C1, 0xB14B, 0x86C2, 0xB14C,
+	0x86C3, 0xB14D, 0x86C4, 0xB14E, 0x86C5, 0xB14F, 0x86C6, 0xB152,	0x86C7, 0xB153, 0x86C8, 0xB156, 0x86C9, 0xB157, 0x86CA, 0xB159,
+	0x86CB, 0xB15A, 0x86CC, 0xB15B, 0x86CD, 0xB15D, 0x86CE, 0xB15E,	0x86CF, 0xB15F, 0x86D0, 0xB161, 0x86D1, 0xB162, 0x86D2, 0xB163,
+	0x86D3, 0xB164, 0x86D4, 0xB165, 0x86D5, 0xB166, 0x86D6, 0xB167,	0x86D7, 0xB168, 0x86D8, 0xB169, 0x86D9, 0xB16A, 0x86DA, 0xB16B,
+	0x86DB, 0xB16C, 0x86DC, 0xB16D, 0x86DD, 0xB16E, 0x86DE, 0xB16F,	0x86DF, 0xB170, 0x86E0, 0xB171, 0x86E1, 0xB172, 0x86E2, 0xB173,
+	0x86E3, 0xB174, 0x86E4, 0xB175, 0x86E5, 0xB176, 0x86E6, 0xB177,	0x86E7, 0xB17A, 0x86E8, 0xB17B, 0x86E9, 0xB17D, 0x86EA, 0xB17E,
+	0x86EB, 0xB17F, 0x86EC, 0xB181, 0x86ED, 0xB183, 0x86EE, 0xB184,	0x86EF, 0xB185, 0x86F0, 0xB186, 0x86F1, 0xB187, 0x86F2, 0xB18A,
+	0x86F3, 0xB18C, 0x86F4, 0xB18E, 0x86F5, 0xB18F, 0x86F6, 0xB190,	0x86F7, 0xB191, 0x86F8, 0xB195, 0x86F9, 0xB196, 0x86FA, 0xB197,
+	0x86FB, 0xB199, 0x86FC, 0xB19A, 0x86FD, 0xB19B, 0x86FE, 0xB19D,	0x8741, 0xB19E, 0x8742, 0xB19F, 0x8743, 0xB1A0, 0x8744, 0xB1A1,
+	0x8745, 0xB1A2, 0x8746, 0xB1A3, 0x8747, 0xB1A4, 0x8748, 0xB1A5,	0x8749, 0xB1A6, 0x874A, 0xB1A7, 0x874B, 0xB1A9, 0x874C, 0xB1AA,
+	0x874D, 0xB1AB, 0x874E, 0xB1AC, 0x874F, 0xB1AD, 0x8750, 0xB1AE,	0x8751, 0xB1AF, 0x8752, 0xB1B0, 0x8753, 0xB1B1, 0x8754, 0xB1B2,
+	0x8755, 0xB1B3, 0x8756, 0xB1B4, 0x8757, 0xB1B5, 0x8758, 0xB1B6,	0x8759, 0xB1B7, 0x875A, 0xB1B8, 0x8761, 0xB1B9, 0x8762, 0xB1BA,
+	0x8763, 0xB1BB, 0x8764, 0xB1BC, 0x8765, 0xB1BD, 0x8766, 0xB1BE,	0x8767, 0xB1BF, 0x8768, 0xB1C0, 0x8769, 0xB1C1, 0x876A, 0xB1C2,
+	0x876B, 0xB1C3, 0x876C, 0xB1C4, 0x876D, 0xB1C5, 0x876E, 0xB1C6,	0x876F, 0xB1C7, 0x8770, 0xB1C8, 0x8771, 0xB1C9, 0x8772, 0xB1CA,
+	0x8773, 0xB1CB, 0x8774, 0xB1CD, 0x8775, 0xB1CE, 0x8776, 0xB1CF,	0x8777, 0xB1D1, 0x8778, 0xB1D2, 0x8779, 0xB1D3, 0x877A, 0xB1D5,
+	0x8781, 0xB1D6, 0x8782, 0xB1D7, 0x8783, 0xB1D8, 0x8784, 0xB1D9,	0x8785, 0xB1DA, 0x8786, 0xB1DB, 0x8787, 0xB1DE, 0x8788, 0xB1E0,
+	0x8789, 0xB1E1, 0x878A, 0xB1E2, 0x878B, 0xB1E3, 0x878C, 0xB1E4,	0x878D, 0xB1E5, 0x878E, 0xB1E6, 0x878F, 0xB1E7, 0x8790, 0xB1EA,
+	0x8791, 0xB1EB, 0x8792, 0xB1ED, 0x8793, 0xB1EE, 0x8794, 0xB1EF,	0x8795, 0xB1F1, 0x8796, 0xB1F2, 0x8797, 0xB1F3, 0x8798, 0xB1F4,
+	0x8799, 0xB1F5, 0x879A, 0xB1F6, 0x879B, 0xB1F7, 0x879C, 0xB1F8,	0x879D, 0xB1FA, 0x879E, 0xB1FC, 0x879F, 0xB1FE, 0x87A0, 0xB1FF,
+	0x87A1, 0xB200, 0x87A2, 0xB201, 0x87A3, 0xB202, 0x87A4, 0xB203,	0x87A5, 0xB206, 0x87A6, 0xB207, 0x87A7, 0xB209, 0x87A8, 0xB20A,
+	0x87A9, 0xB20D, 0x87AA, 0xB20E, 0x87AB, 0xB20F, 0x87AC, 0xB210,	0x87AD, 0xB211, 0x87AE, 0xB212, 0x87AF, 0xB213, 0x87B0, 0xB216,
+	0x87B1, 0xB218, 0x87B2, 0xB21A, 0x87B3, 0xB21B, 0x87B4, 0xB21C,	0x87B5, 0xB21D, 0x87B6, 0xB21E, 0x87B7, 0xB21F, 0x87B8, 0xB221,
+	0x87B9, 0xB222, 0x87BA, 0xB223, 0x87BB, 0xB224, 0x87BC, 0xB225,	0x87BD, 0xB226, 0x87BE, 0xB227, 0x87BF, 0xB228, 0x87C0, 0xB229,
+	0x87C1, 0xB22A, 0x87C2, 0xB22B, 0x87C3, 0xB22C, 0x87C4, 0xB22D,	0x87C5, 0xB22E, 0x87C6, 0xB22F, 0x87C7, 0xB230, 0x87C8, 0xB231,
+	0x87C9, 0xB232, 0x87CA, 0xB233, 0x87CB, 0xB235, 0x87CC, 0xB236,	0x87CD, 0xB237, 0x87CE, 0xB238, 0x87CF, 0xB239, 0x87D0, 0xB23A,
+	0x87D1, 0xB23B, 0x87D2, 0xB23D, 0x87D3, 0xB23E, 0x87D4, 0xB23F,	0x87D5, 0xB240, 0x87D6, 0xB241, 0x87D7, 0xB242, 0x87D8, 0xB243,
+	0x87D9, 0xB244, 0x87DA, 0xB245, 0x87DB, 0xB246, 0x87DC, 0xB247,	0x87DD, 0xB248, 0x87DE, 0xB249, 0x87DF, 0xB24A, 0x87E0, 0xB24B,
+	0x87E1, 0xB24C, 0x87E2, 0xB24D, 0x87E3, 0xB24E, 0x87E4, 0xB24F,	0x87E5, 0xB250, 0x87E6, 0xB251, 0x87E7, 0xB252, 0x87E8, 0xB253,
+	0x87E9, 0xB254, 0x87EA, 0xB255, 0x87EB, 0xB256, 0x87EC, 0xB257,	0x87ED, 0xB259, 0x87EE, 0xB25A, 0x87EF, 0xB25B, 0x87F0, 0xB25D,
+	0x87F1, 0xB25E, 0x87F2, 0xB25F, 0x87F3, 0xB261, 0x87F4, 0xB262,	0x87F5, 0xB263, 0x87F6, 0xB264, 0x87F7, 0xB265, 0x87F8, 0xB266,
+	0x87F9, 0xB267, 0x87FA, 0xB26A, 0x87FB, 0xB26B, 0x87FC, 0xB26C,	0x87FD, 0xB26D, 0x87FE, 0xB26E, 0x8841, 0xB26F, 0x8842, 0xB270,
+	0x8843, 0xB271, 0x8844, 0xB272, 0x8845, 0xB273, 0x8846, 0xB276,	0x8847, 0xB277, 0x8848, 0xB278, 0x8849, 0xB279, 0x884A, 0xB27A,
+	0x884B, 0xB27B, 0x884C, 0xB27D, 0x884D, 0xB27E, 0x884E, 0xB27F,	0x884F, 0xB280, 0x8850, 0xB281, 0x8851, 0xB282, 0x8852, 0xB283,
+	0x8853, 0xB286, 0x8854, 0xB287, 0x8855, 0xB288, 0x8856, 0xB28A,	0x8857, 0xB28B, 0x8858, 0xB28C, 0x8859, 0xB28D, 0x885A, 0xB28E,
+	0x8861, 0xB28F, 0x8862, 0xB292, 0x8863, 0xB293, 0x8864, 0xB295,	0x8865, 0xB296, 0x8866, 0xB297, 0x8867, 0xB29B, 0x8868, 0xB29C,
+	0x8869, 0xB29D, 0x886A, 0xB29E, 0x886B, 0xB29F, 0x886C, 0xB2A2,	0x886D, 0xB2A4, 0x886E, 0xB2A7, 0x886F, 0xB2A8, 0x8870, 0xB2A9,
+	0x8871, 0xB2AB, 0x8872, 0xB2AD, 0x8873, 0xB2AE, 0x8874, 0xB2AF,	0x8875, 0xB2B1, 0x8876, 0xB2B2, 0x8877, 0xB2B3, 0x8878, 0xB2B5,
+	0x8879, 0xB2B6, 0x887A, 0xB2B7, 0x8881, 0xB2B8, 0x8882, 0xB2B9,	0x8883, 0xB2BA, 0x8884, 0xB2BB, 0x8885, 0xB2BC, 0x8886, 0xB2BD,
+	0x8887, 0xB2BE, 0x8888, 0xB2BF, 0x8889, 0xB2C0, 0x888A, 0xB2C1,	0x888B, 0xB2C2, 0x888C, 0xB2C3, 0x888D, 0xB2C4, 0x888E, 0xB2C5,
+	0x888F, 0xB2C6, 0x8890, 0xB2C7, 0x8891, 0xB2CA, 0x8892, 0xB2CB,	0x8893, 0xB2CD, 0x8894, 0xB2CE, 0x8895, 0xB2CF, 0x8896, 0xB2D1,
+	0x8897, 0xB2D3, 0x8898, 0xB2D4, 0x8899, 0xB2D5, 0x889A, 0xB2D6,	0x889B, 0xB2D7, 0x889C, 0xB2DA, 0x889D, 0xB2DC, 0x889E, 0xB2DE,
+	0x889F, 0xB2DF, 0x88A0, 0xB2E0, 0x88A1, 0xB2E1, 0x88A2, 0xB2E3,	0x88A3, 0xB2E7, 0x88A4, 0xB2E9, 0x88A5, 0xB2EA, 0x88A6, 0xB2F0,
+	0x88A7, 0xB2F1, 0x88A8, 0xB2F2, 0x88A9, 0xB2F6, 0x88AA, 0xB2FC,	0x88AB, 0xB2FD, 0x88AC, 0xB2FE, 0x88AD, 0xB302, 0x88AE, 0xB303,
+	0x88AF, 0xB305, 0x88B0, 0xB306, 0x88B1, 0xB307, 0x88B2, 0xB309,	0x88B3, 0xB30A, 0x88B4, 0xB30B, 0x88B5, 0xB30C, 0x88B6, 0xB30D,
+	0x88B7, 0xB30E, 0x88B8, 0xB30F, 0x88B9, 0xB312, 0x88BA, 0xB316,	0x88BB, 0xB317, 0x88BC, 0xB318, 0x88BD, 0xB319, 0x88BE, 0xB31A,
+	0x88BF, 0xB31B, 0x88C0, 0xB31D, 0x88C1, 0xB31E, 0x88C2, 0xB31F,	0x88C3, 0xB320, 0x88C4, 0xB321, 0x88C5, 0xB322, 0x88C6, 0xB323,
+	0x88C7, 0xB324, 0x88C8, 0xB325, 0x88C9, 0xB326, 0x88CA, 0xB327,	0x88CB, 0xB328, 0x88CC, 0xB329, 0x88CD, 0xB32A, 0x88CE, 0xB32B,
+	0x88CF, 0xB32C, 0x88D0, 0xB32D, 0x88D1, 0xB32E, 0x88D2, 0xB32F,	0x88D3, 0xB330, 0x88D4, 0xB331, 0x88D5, 0xB332, 0x88D6, 0xB333,
+	0x88D7, 0xB334, 0x88D8, 0xB335, 0x88D9, 0xB336, 0x88DA, 0xB337,	0x88DB, 0xB338, 0x88DC, 0xB339, 0x88DD, 0xB33A, 0x88DE, 0xB33B,
+	0x88DF, 0xB33C, 0x88E0, 0xB33D, 0x88E1, 0xB33E, 0x88E2, 0xB33F,	0x88E3, 0xB340, 0x88E4, 0xB341, 0x88E5, 0xB342, 0x88E6, 0xB343,
+	0x88E7, 0xB344, 0x88E8, 0xB345, 0x88E9, 0xB346, 0x88EA, 0xB347,	0x88EB, 0xB348, 0x88EC, 0xB349, 0x88ED, 0xB34A, 0x88EE, 0xB34B,
+	0x88EF, 0xB34C, 0x88F0, 0xB34D, 0x88F1, 0xB34E, 0x88F2, 0xB34F,	0x88F3, 0xB350, 0x88F4, 0xB351, 0x88F5, 0xB352, 0x88F6, 0xB353,
+	0x88F7, 0xB357, 0x88F8, 0xB359, 0x88F9, 0xB35A, 0x88FA, 0xB35D,	0x88FB, 0xB360, 0x88FC, 0xB361, 0x88FD, 0xB362, 0x88FE, 0xB363,
+	0x8941, 0xB366, 0x8942, 0xB368, 0x8943, 0xB36A, 0x8944, 0xB36C,	0x8945, 0xB36D, 0x8946, 0xB36F, 0x8947, 0xB372, 0x8948, 0xB373,
+	0x8949, 0xB375, 0x894A, 0xB376, 0x894B, 0xB377, 0x894C, 0xB379,	0x894D, 0xB37A, 0x894E, 0xB37B, 0x894F, 0xB37C, 0x8950, 0xB37D,
+	0x8951, 0xB37E, 0x8952, 0xB37F, 0x8953, 0xB382, 0x8954, 0xB386,	0x8955, 0xB387, 0x8956, 0xB388, 0x8957, 0xB389, 0x8958, 0xB38A,
+	0x8959, 0xB38B, 0x895A, 0xB38D, 0x8961, 0xB38E, 0x8962, 0xB38F,	0x8963, 0xB391, 0x8964, 0xB392, 0x8965, 0xB393, 0x8966, 0xB395,
+	0x8967, 0xB396, 0x8968, 0xB397, 0x8969, 0xB398, 0x896A, 0xB399,	0x896B, 0xB39A, 0x896C, 0xB39B, 0x896D, 0xB39C, 0x896E, 0xB39D,
+	0x896F, 0xB39E, 0x8970, 0xB39F, 0x8971, 0xB3A2, 0x8972, 0xB3A3,	0x8973, 0xB3A4, 0x8974, 0xB3A5, 0x8975, 0xB3A6, 0x8976, 0xB3A7,
+	0x8977, 0xB3A9, 0x8978, 0xB3AA, 0x8979, 0xB3AB, 0x897A, 0xB3AD,	0x8981, 0xB3AE, 0x8982, 0xB3AF, 0x8983, 0xB3B0, 0x8984, 0xB3B1,
+	0x8985, 0xB3B2, 0x8986, 0xB3B3, 0x8987, 0xB3B4, 0x8988, 0xB3B5,	0x8989, 0xB3B6, 0x898A, 0xB3B7, 0x898B, 0xB3B8, 0x898C, 0xB3B9,
+	0x898D, 0xB3BA, 0x898E, 0xB3BB, 0x898F, 0xB3BC, 0x8990, 0xB3BD,	0x8991, 0xB3BE, 0x8992, 0xB3BF, 0x8993, 0xB3C0, 0x8994, 0xB3C1,
+	0x8995, 0xB3C2, 0x8996, 0xB3C3, 0x8997, 0xB3C6, 0x8998, 0xB3C7,	0x8999, 0xB3C9, 0x899A, 0xB3CA, 0x899B, 0xB3CD, 0x899C, 0xB3CF,
+	0x899D, 0xB3D1, 0x899E, 0xB3D2, 0x899F, 0xB3D3, 0x89A0, 0xB3D6,	0x89A1, 0xB3D8, 0x89A2, 0xB3DA, 0x89A3, 0xB3DC, 0x89A4, 0xB3DE,
+	0x89A5, 0xB3DF, 0x89A6, 0xB3E1, 0x89A7, 0xB3E2, 0x89A8, 0xB3E3,	0x89A9, 0xB3E5, 0x89AA, 0xB3E6, 0x89AB, 0xB3E7, 0x89AC, 0xB3E9,
+	0x89AD, 0xB3EA, 0x89AE, 0xB3EB, 0x89AF, 0xB3EC, 0x89B0, 0xB3ED,	0x89B1, 0xB3EE, 0x89B2, 0xB3EF, 0x89B3, 0xB3F0, 0x89B4, 0xB3F1,
+	0x89B5, 0xB3F2, 0x89B6, 0xB3F3, 0x89B7, 0xB3F4, 0x89B8, 0xB3F5,	0x89B9, 0xB3F6, 0x89BA, 0xB3F7, 0x89BB, 0xB3F8, 0x89BC, 0xB3F9,
+	0x89BD, 0xB3FA, 0x89BE, 0xB3FB, 0x89BF, 0xB3FD, 0x89C0, 0xB3FE,	0x89C1, 0xB3FF, 0x89C2, 0xB400, 0x89C3, 0xB401, 0x89C4, 0xB402,
+	0x89C5, 0xB403, 0x89C6, 0xB404, 0x89C7, 0xB405, 0x89C8, 0xB406,	0x89C9, 0xB407, 0x89CA, 0xB408, 0x89CB, 0xB409, 0x89CC, 0xB40A,
+	0x89CD, 0xB40B, 0x89CE, 0xB40C, 0x89CF, 0xB40D, 0x89D0, 0xB40E,	0x89D1, 0xB40F, 0x89D2, 0xB411, 0x89D3, 0xB412, 0x89D4, 0xB413,
+	0x89D5, 0xB414, 0x89D6, 0xB415, 0x89D7, 0xB416, 0x89D8, 0xB417,	0x89D9, 0xB419, 0x89DA, 0xB41A, 0x89DB, 0xB41B, 0x89DC, 0xB41D,
+	0x89DD, 0xB41E, 0x89DE, 0xB41F, 0x89DF, 0xB421, 0x89E0, 0xB422,	0x89E1, 0xB423, 0x89E2, 0xB424, 0x89E3, 0xB425, 0x89E4, 0xB426,
+	0x89E5, 0xB427, 0x89E6, 0xB42A, 0x89E7, 0xB42C, 0x89E8, 0xB42D,	0x89E9, 0xB42E, 0x89EA, 0xB42F, 0x89EB, 0xB430, 0x89EC, 0xB431,
+	0x89ED, 0xB432, 0x89EE, 0xB433, 0x89EF, 0xB435, 0x89F0, 0xB436,	0x89F1, 0xB437, 0x89F2, 0xB438, 0x89F3, 0xB439, 0x89F4, 0xB43A,
+	0x89F5, 0xB43B, 0x89F6, 0xB43C, 0x89F7, 0xB43D, 0x89F8, 0xB43E,	0x89F9, 0xB43F, 0x89FA, 0xB440, 0x89FB, 0xB441, 0x89FC, 0xB442,
+	0x89FD, 0xB443, 0x89FE, 0xB444, 0x8A41, 0xB445, 0x8A42, 0xB446,	0x8A43, 0xB447, 0x8A44, 0xB448, 0x8A45, 0xB449, 0x8A46, 0xB44A,
+	0x8A47, 0xB44B, 0x8A48, 0xB44C, 0x8A49, 0xB44D, 0x8A4A, 0xB44E,	0x8A4B, 0xB44F, 0x8A4C, 0xB452, 0x8A4D, 0xB453, 0x8A4E, 0xB455,
+	0x8A4F, 0xB456, 0x8A50, 0xB457, 0x8A51, 0xB459, 0x8A52, 0xB45A,	0x8A53, 0xB45B, 0x8A54, 0xB45C, 0x8A55, 0xB45D, 0x8A56, 0xB45E,
+	0x8A57, 0xB45F, 0x8A58, 0xB462, 0x8A59, 0xB464, 0x8A5A, 0xB466,	0x8A61, 0xB467, 0x8A62, 0xB468, 0x8A63, 0xB469, 0x8A64, 0xB46A,
+	0x8A65, 0xB46B, 0x8A66, 0xB46D, 0x8A67, 0xB46E, 0x8A68, 0xB46F,	0x8A69, 0xB470, 0x8A6A, 0xB471, 0x8A6B, 0xB472, 0x8A6C, 0xB473,
+	0x8A6D, 0xB474, 0x8A6E, 0xB475, 0x8A6F, 0xB476, 0x8A70, 0xB477,	0x8A71, 0xB478, 0x8A72, 0xB479, 0x8A73, 0xB47A, 0x8A74, 0xB47B,
+	0x8A75, 0xB47C, 0x8A76, 0xB47D, 0x8A77, 0xB47E, 0x8A78, 0xB47F,	0x8A79, 0xB481, 0x8A7A, 0xB482, 0x8A81, 0xB483, 0x8A82, 0xB484,
+	0x8A83, 0xB485, 0x8A84, 0xB486, 0x8A85, 0xB487, 0x8A86, 0xB489,	0x8A87, 0xB48A, 0x8A88, 0xB48B, 0x8A89, 0xB48C, 0x8A8A, 0xB48D,
+	0x8A8B, 0xB48E, 0x8A8C, 0xB48F, 0x8A8D, 0xB490, 0x8A8E, 0xB491,	0x8A8F, 0xB492, 0x8A90, 0xB493, 0x8A91, 0xB494, 0x8A92, 0xB495,
+	0x8A93, 0xB496, 0x8A94, 0xB497, 0x8A95, 0xB498, 0x8A96, 0xB499,	0x8A97, 0xB49A, 0x8A98, 0xB49B, 0x8A99, 0xB49C, 0x8A9A, 0xB49E,
+	0x8A9B, 0xB49F, 0x8A9C, 0xB4A0, 0x8A9D, 0xB4A1, 0x8A9E, 0xB4A2,	0x8A9F, 0xB4A3, 0x8AA0, 0xB4A5, 0x8AA1, 0xB4A6, 0x8AA2, 0xB4A7,
+	0x8AA3, 0xB4A9, 0x8AA4, 0xB4AA, 0x8AA5, 0xB4AB, 0x8AA6, 0xB4AD,	0x8AA7, 0xB4AE, 0x8AA8, 0xB4AF, 0x8AA9, 0xB4B0, 0x8AAA, 0xB4B1,
+	0x8AAB, 0xB4B2, 0x8AAC, 0xB4B3, 0x8AAD, 0xB4B4, 0x8AAE, 0xB4B6,	0x8AAF, 0xB4B8, 0x8AB0, 0xB4BA, 0x8AB1, 0xB4BB, 0x8AB2, 0xB4BC,
+	0x8AB3, 0xB4BD, 0x8AB4, 0xB4BE, 0x8AB5, 0xB4BF, 0x8AB6, 0xB4C1,	0x8AB7, 0xB4C2, 0x8AB8, 0xB4C3, 0x8AB9, 0xB4C5, 0x8ABA, 0xB4C6,
+	0x8ABB, 0xB4C7, 0x8ABC, 0xB4C9, 0x8ABD, 0xB4CA, 0x8ABE, 0xB4CB,	0x8ABF, 0xB4CC, 0x8AC0, 0xB4CD, 0x8AC1, 0xB4CE, 0x8AC2, 0xB4CF,
+	0x8AC3, 0xB4D1, 0x8AC4, 0xB4D2, 0x8AC5, 0xB4D3, 0x8AC6, 0xB4D4,	0x8AC7, 0xB4D6, 0x8AC8, 0xB4D7, 0x8AC9, 0xB4D8, 0x8ACA, 0xB4D9,
+	0x8ACB, 0xB4DA, 0x8ACC, 0xB4DB, 0x8ACD, 0xB4DE, 0x8ACE, 0xB4DF,	0x8ACF, 0xB4E1, 0x8AD0, 0xB4E2, 0x8AD1, 0xB4E5, 0x8AD2, 0xB4E7,
+	0x8AD3, 0xB4E8, 0x8AD4, 0xB4E9, 0x8AD5, 0xB4EA, 0x8AD6, 0xB4EB,	0x8AD7, 0xB4EE, 0x8AD8, 0xB4F0, 0x8AD9, 0xB4F2, 0x8ADA, 0xB4F3,
+	0x8ADB, 0xB4F4, 0x8ADC, 0xB4F5, 0x8ADD, 0xB4F6, 0x8ADE, 0xB4F7,	0x8ADF, 0xB4F9, 0x8AE0, 0xB4FA, 0x8AE1, 0xB4FB, 0x8AE2, 0xB4FC,
+	0x8AE3, 0xB4FD, 0x8AE4, 0xB4FE, 0x8AE5, 0xB4FF, 0x8AE6, 0xB500,	0x8AE7, 0xB501, 0x8AE8, 0xB502, 0x8AE9, 0xB503, 0x8AEA, 0xB504,
+	0x8AEB, 0xB505, 0x8AEC, 0xB506, 0x8AED, 0xB507, 0x8AEE, 0xB508,	0x8AEF, 0xB509, 0x8AF0, 0xB50A, 0x8AF1, 0xB50B, 0x8AF2, 0xB50C,
+	0x8AF3, 0xB50D, 0x8AF4, 0xB50E, 0x8AF5, 0xB50F, 0x8AF6, 0xB510,	0x8AF7, 0xB511, 0x8AF8, 0xB512, 0x8AF9, 0xB513, 0x8AFA, 0xB516,
+	0x8AFB, 0xB517, 0x8AFC, 0xB519, 0x8AFD, 0xB51A, 0x8AFE, 0xB51D,	0x8B41, 0xB51E, 0x8B42, 0xB51F, 0x8B43, 0xB520, 0x8B44, 0xB521,
+	0x8B45, 0xB522, 0x8B46, 0xB523, 0x8B47, 0xB526, 0x8B48, 0xB52B,	0x8B49, 0xB52C, 0x8B4A, 0xB52D, 0x8B4B, 0xB52E, 0x8B4C, 0xB52F,
+	0x8B4D, 0xB532, 0x8B4E, 0xB533, 0x8B4F, 0xB535, 0x8B50, 0xB536,	0x8B51, 0xB537, 0x8B52, 0xB539, 0x8B53, 0xB53A, 0x8B54, 0xB53B,
+	0x8B55, 0xB53C, 0x8B56, 0xB53D, 0x8B57, 0xB53E, 0x8B58, 0xB53F,	0x8B59, 0xB542, 0x8B5A, 0xB546, 0x8B61, 0xB547, 0x8B62, 0xB548,
+	0x8B63, 0xB549, 0x8B64, 0xB54A, 0x8B65, 0xB54E, 0x8B66, 0xB54F,	0x8B67, 0xB551, 0x8B68, 0xB552, 0x8B69, 0xB553, 0x8B6A, 0xB555,
+	0x8B6B, 0xB556, 0x8B6C, 0xB557, 0x8B6D, 0xB558, 0x8B6E, 0xB559,	0x8B6F, 0xB55A, 0x8B70, 0xB55B, 0x8B71, 0xB55E, 0x8B72, 0xB562,
+	0x8B73, 0xB563, 0x8B74, 0xB564, 0x8B75, 0xB565, 0x8B76, 0xB566,	0x8B77, 0xB567, 0x8B78, 0xB568, 0x8B79, 0xB569, 0x8B7A, 0xB56A,
+	0x8B81, 0xB56B, 0x8B82, 0xB56C, 0x8B83, 0xB56D, 0x8B84, 0xB56E,	0x8B85, 0xB56F, 0x8B86, 0xB570, 0x8B87, 0xB571, 0x8B88, 0xB572,
+	0x8B89, 0xB573, 0x8B8A, 0xB574, 0x8B8B, 0xB575, 0x8B8C, 0xB576,	0x8B8D, 0xB577, 0x8B8E, 0xB578, 0x8B8F, 0xB579, 0x8B90, 0xB57A,
+	0x8B91, 0xB57B, 0x8B92, 0xB57C, 0x8B93, 0xB57D, 0x8B94, 0xB57E,	0x8B95, 0xB57F, 0x8B96, 0xB580, 0x8B97, 0xB581, 0x8B98, 0xB582,
+	0x8B99, 0xB583, 0x8B9A, 0xB584, 0x8B9B, 0xB585, 0x8B9C, 0xB586,	0x8B9D, 0xB587, 0x8B9E, 0xB588, 0x8B9F, 0xB589, 0x8BA0, 0xB58A,
+	0x8BA1, 0xB58B, 0x8BA2, 0xB58C, 0x8BA3, 0xB58D, 0x8BA4, 0xB58E,	0x8BA5, 0xB58F, 0x8BA6, 0xB590, 0x8BA7, 0xB591, 0x8BA8, 0xB592,
+	0x8BA9, 0xB593, 0x8BAA, 0xB594, 0x8BAB, 0xB595, 0x8BAC, 0xB596,	0x8BAD, 0xB597, 0x8BAE, 0xB598, 0x8BAF, 0xB599, 0x8BB0, 0xB59A,
+	0x8BB1, 0xB59B, 0x8BB2, 0xB59C, 0x8BB3, 0xB59D, 0x8BB4, 0xB59E,	0x8BB5, 0xB59F, 0x8BB6, 0xB5A2, 0x8BB7, 0xB5A3, 0x8BB8, 0xB5A5,
+	0x8BB9, 0xB5A6, 0x8BBA, 0xB5A7, 0x8BBB, 0xB5A9, 0x8BBC, 0xB5AC,	0x8BBD, 0xB5AD, 0x8BBE, 0xB5AE, 0x8BBF, 0xB5AF, 0x8BC0, 0xB5B2,
+	0x8BC1, 0xB5B6, 0x8BC2, 0xB5B7, 0x8BC3, 0xB5B8, 0x8BC4, 0xB5B9,	0x8BC5, 0xB5BA, 0x8BC6, 0xB5BE, 0x8BC7, 0xB5BF, 0x8BC8, 0xB5C1,
+	0x8BC9, 0xB5C2, 0x8BCA, 0xB5C3, 0x8BCB, 0xB5C5, 0x8BCC, 0xB5C6,	0x8BCD, 0xB5C7, 0x8BCE, 0xB5C8, 0x8BCF, 0xB5C9, 0x8BD0, 0xB5CA,
+	0x8BD1, 0xB5CB, 0x8BD2, 0xB5CE, 0x8BD3, 0xB5D2, 0x8BD4, 0xB5D3,	0x8BD5, 0xB5D4, 0x8BD6, 0xB5D5, 0x8BD7, 0xB5D6, 0x8BD8, 0xB5D7,
+	0x8BD9, 0xB5D9, 0x8BDA, 0xB5DA, 0x8BDB, 0xB5DB, 0x8BDC, 0xB5DC,	0x8BDD, 0xB5DD, 0x8BDE, 0xB5DE, 0x8BDF, 0xB5DF, 0x8BE0, 0xB5E0,
+	0x8BE1, 0xB5E1, 0x8BE2, 0xB5E2, 0x8BE3, 0xB5E3, 0x8BE4, 0xB5E4,	0x8BE5, 0xB5E5, 0x8BE6, 0xB5E6, 0x8BE7, 0xB5E7, 0x8BE8, 0xB5E8,
+	0x8BE9, 0xB5E9, 0x8BEA, 0xB5EA, 0x8BEB, 0xB5EB, 0x8BEC, 0xB5ED,	0x8BED, 0xB5EE, 0x8BEE, 0xB5EF, 0x8BEF, 0xB5F0, 0x8BF0, 0xB5F1,
+	0x8BF1, 0xB5F2, 0x8BF2, 0xB5F3, 0x8BF3, 0xB5F4, 0x8BF4, 0xB5F5,	0x8BF5, 0xB5F6, 0x8BF6, 0xB5F7, 0x8BF7, 0xB5F8, 0x8BF8, 0xB5F9,
+	0x8BF9, 0xB5FA, 0x8BFA, 0xB5FB, 0x8BFB, 0xB5FC, 0x8BFC, 0xB5FD,	0x8BFD, 0xB5FE, 0x8BFE, 0xB5FF, 0x8C41, 0xB600, 0x8C42, 0xB601,
+	0x8C43, 0xB602, 0x8C44, 0xB603, 0x8C45, 0xB604, 0x8C46, 0xB605,	0x8C47, 0xB606, 0x8C48, 0xB607, 0x8C49, 0xB608, 0x8C4A, 0xB609,
+	0x8C4B, 0xB60A, 0x8C4C, 0xB60B, 0x8C4D, 0xB60C, 0x8C4E, 0xB60D,	0x8C4F, 0xB60E, 0x8C50, 0xB60F, 0x8C51, 0xB612, 0x8C52, 0xB613,
+	0x8C53, 0xB615, 0x8C54, 0xB616, 0x8C55, 0xB617, 0x8C56, 0xB619,	0x8C57, 0xB61A, 0x8C58, 0xB61B, 0x8C59, 0xB61C, 0x8C5A, 0xB61D,
+	0x8C61, 0xB61E, 0x8C62, 0xB61F, 0x8C63, 0xB620, 0x8C64, 0xB621,	0x8C65, 0xB622, 0x8C66, 0xB623, 0x8C67, 0xB624, 0x8C68, 0xB626,
+	0x8C69, 0xB627, 0x8C6A, 0xB628, 0x8C6B, 0xB629, 0x8C6C, 0xB62A,	0x8C6D, 0xB62B, 0x8C6E, 0xB62D, 0x8C6F, 0xB62E, 0x8C70, 0xB62F,
+	0x8C71, 0xB630, 0x8C72, 0xB631, 0x8C73, 0xB632, 0x8C74, 0xB633,	0x8C75, 0xB635, 0x8C76, 0xB636, 0x8C77, 0xB637, 0x8C78, 0xB638,
+	0x8C79, 0xB639, 0x8C7A, 0xB63A, 0x8C81, 0xB63B, 0x8C82, 0xB63C,	0x8C83, 0xB63D, 0x8C84, 0xB63E, 0x8C85, 0xB63F, 0x8C86, 0xB640,
+	0x8C87, 0xB641, 0x8C88, 0xB642, 0x8C89, 0xB643, 0x8C8A, 0xB644,	0x8C8B, 0xB645, 0x8C8C, 0xB646, 0x8C8D, 0xB647, 0x8C8E, 0xB649,
+	0x8C8F, 0xB64A, 0x8C90, 0xB64B, 0x8C91, 0xB64C, 0x8C92, 0xB64D,	0x8C93, 0xB64E, 0x8C94, 0xB64F, 0x8C95, 0xB650, 0x8C96, 0xB651,
+	0x8C97, 0xB652, 0x8C98, 0xB653, 0x8C99, 0xB654, 0x8C9A, 0xB655,	0x8C9B, 0xB656, 0x8C9C, 0xB657, 0x8C9D, 0xB658, 0x8C9E, 0xB659,
+	0x8C9F, 0xB65A, 0x8CA0, 0xB65B, 0x8CA1, 0xB65C, 0x8CA2, 0xB65D,	0x8CA3, 0xB65E, 0x8CA4, 0xB65F, 0x8CA5, 0xB660, 0x8CA6, 0xB661,
+	0x8CA7, 0xB662, 0x8CA8, 0xB663, 0x8CA9, 0xB665, 0x8CAA, 0xB666,	0x8CAB, 0xB667, 0x8CAC, 0xB669, 0x8CAD, 0xB66A, 0x8CAE, 0xB66B,
+	0x8CAF, 0xB66C, 0x8CB0, 0xB66D, 0x8CB1, 0xB66E, 0x8CB2, 0xB66F,	0x8CB3, 0xB670, 0x8CB4, 0xB671, 0x8CB5, 0xB672, 0x8CB6, 0xB673,
+	0x8CB7, 0xB674, 0x8CB8, 0xB675, 0x8CB9, 0xB676, 0x8CBA, 0xB677,	0x8CBB, 0xB678, 0x8CBC, 0xB679, 0x8CBD, 0xB67A, 0x8CBE, 0xB67B,
+	0x8CBF, 0xB67C, 0x8CC0, 0xB67D, 0x8CC1, 0xB67E, 0x8CC2, 0xB67F,	0x8CC3, 0xB680, 0x8CC4, 0xB681, 0x8CC5, 0xB682, 0x8CC6, 0xB683,
+	0x8CC7, 0xB684, 0x8CC8, 0xB685, 0x8CC9, 0xB686, 0x8CCA, 0xB687,	0x8CCB, 0xB688, 0x8CCC, 0xB689, 0x8CCD, 0xB68A, 0x8CCE, 0xB68B,
+	0x8CCF, 0xB68C, 0x8CD0, 0xB68D, 0x8CD1, 0xB68E, 0x8CD2, 0xB68F,	0x8CD3, 0xB690, 0x8CD4, 0xB691, 0x8CD5, 0xB692, 0x8CD6, 0xB693,
+	0x8CD7, 0xB694, 0x8CD8, 0xB695, 0x8CD9, 0xB696, 0x8CDA, 0xB697,	0x8CDB, 0xB698, 0x8CDC, 0xB699, 0x8CDD, 0xB69A, 0x8CDE, 0xB69B,
+	0x8CDF, 0xB69E, 0x8CE0, 0xB69F, 0x8CE1, 0xB6A1, 0x8CE2, 0xB6A2,	0x8CE3, 0xB6A3, 0x8CE4, 0xB6A5, 0x8CE5, 0xB6A6, 0x8CE6, 0xB6A7,
+	0x8CE7, 0xB6A8, 0x8CE8, 0xB6A9, 0x8CE9, 0xB6AA, 0x8CEA, 0xB6AD,	0x8CEB, 0xB6AE, 0x8CEC, 0xB6AF, 0x8CED, 0xB6B0, 0x8CEE, 0xB6B2,
+	0x8CEF, 0xB6B3, 0x8CF0, 0xB6B4, 0x8CF1, 0xB6B5, 0x8CF2, 0xB6B6,	0x8CF3, 0xB6B7, 0x8CF4, 0xB6B8, 0x8CF5, 0xB6B9, 0x8CF6, 0xB6BA,
+	0x8CF7, 0xB6BB, 0x8CF8, 0xB6BC, 0x8CF9, 0xB6BD, 0x8CFA, 0xB6BE,	0x8CFB, 0xB6BF, 0x8CFC, 0xB6C0, 0x8CFD, 0xB6C1, 0x8CFE, 0xB6C2,
+	0x8D41, 0xB6C3, 0x8D42, 0xB6C4, 0x8D43, 0xB6C5, 0x8D44, 0xB6C6,	0x8D45, 0xB6C7, 0x8D46, 0xB6C8, 0x8D47, 0xB6C9, 0x8D48, 0xB6CA,
+	0x8D49, 0xB6CB, 0x8D4A, 0xB6CC, 0x8D4B, 0xB6CD, 0x8D4C, 0xB6CE,	0x8D4D, 0xB6CF, 0x8D4E, 0xB6D0, 0x8D4F, 0xB6D1, 0x8D50, 0xB6D2,
+	0x8D51, 0xB6D3, 0x8D52, 0xB6D5, 0x8D53, 0xB6D6, 0x8D54, 0xB6D7,	0x8D55, 0xB6D8, 0x8D56, 0xB6D9, 0x8D57, 0xB6DA, 0x8D58, 0xB6DB,
+	0x8D59, 0xB6DC, 0x8D5A, 0xB6DD, 0x8D61, 0xB6DE, 0x8D62, 0xB6DF,	0x8D63, 0xB6E0, 0x8D64, 0xB6E1, 0x8D65, 0xB6E2, 0x8D66, 0xB6E3,
+	0x8D67, 0xB6E4, 0x8D68, 0xB6E5, 0x8D69, 0xB6E6, 0x8D6A, 0xB6E7,	0x8D6B, 0xB6E8, 0x8D6C, 0xB6E9, 0x8D6D, 0xB6EA, 0x8D6E, 0xB6EB,
+	0x8D6F, 0xB6EC, 0x8D70, 0xB6ED, 0x8D71, 0xB6EE, 0x8D72, 0xB6EF,	0x8D73, 0xB6F1, 0x8D74, 0xB6F2, 0x8D75, 0xB6F3, 0x8D76, 0xB6F5,
+	0x8D77, 0xB6F6, 0x8D78, 0xB6F7, 0x8D79, 0xB6F9, 0x8D7A, 0xB6FA,	0x8D81, 0xB6FB, 0x8D82, 0xB6FC, 0x8D83, 0xB6FD, 0x8D84, 0xB6FE,
+	0x8D85, 0xB6FF, 0x8D86, 0xB702, 0x8D87, 0xB703, 0x8D88, 0xB704,	0x8D89, 0xB706, 0x8D8A, 0xB707, 0x8D8B, 0xB708, 0x8D8C, 0xB709,
+	0x8D8D, 0xB70A, 0x8D8E, 0xB70B, 0x8D8F, 0xB70C, 0x8D90, 0xB70D,	0x8D91, 0xB70E, 0x8D92, 0xB70F, 0x8D93, 0xB710, 0x8D94, 0xB711,
+	0x8D95, 0xB712, 0x8D96, 0xB713, 0x8D97, 0xB714, 0x8D98, 0xB715,	0x8D99, 0xB716, 0x8D9A, 0xB717, 0x8D9B, 0xB718, 0x8D9C, 0xB719,
+	0x8D9D, 0xB71A, 0x8D9E, 0xB71B, 0x8D9F, 0xB71C, 0x8DA0, 0xB71D,	0x8DA1, 0xB71E, 0x8DA2, 0xB71F, 0x8DA3, 0xB720, 0x8DA4, 0xB721,
+	0x8DA5, 0xB722, 0x8DA6, 0xB723, 0x8DA7, 0xB724, 0x8DA8, 0xB725,	0x8DA9, 0xB726, 0x8DAA, 0xB727, 0x8DAB, 0xB72A, 0x8DAC, 0xB72B,
+	0x8DAD, 0xB72D, 0x8DAE, 0xB72E, 0x8DAF, 0xB731, 0x8DB0, 0xB732,	0x8DB1, 0xB733, 0x8DB2, 0xB734, 0x8DB3, 0xB735, 0x8DB4, 0xB736,
+	0x8DB5, 0xB737, 0x8DB6, 0xB73A, 0x8DB7, 0xB73C, 0x8DB8, 0xB73D,	0x8DB9, 0xB73E, 0x8DBA, 0xB73F, 0x8DBB, 0xB740, 0x8DBC, 0xB741,
+	0x8DBD, 0xB742, 0x8DBE, 0xB743, 0x8DBF, 0xB745, 0x8DC0, 0xB746,	0x8DC1, 0xB747, 0x8DC2, 0xB749, 0x8DC3, 0xB74A, 0x8DC4, 0xB74B,
+	0x8DC5, 0xB74D, 0x8DC6, 0xB74E, 0x8DC7, 0xB74F, 0x8DC8, 0xB750,	0x8DC9, 0xB751, 0x8DCA, 0xB752, 0x8DCB, 0xB753, 0x8DCC, 0xB756,
+	0x8DCD, 0xB757, 0x8DCE, 0xB758, 0x8DCF, 0xB759, 0x8DD0, 0xB75A,	0x8DD1, 0xB75B, 0x8DD2, 0xB75C, 0x8DD3, 0xB75D, 0x8DD4, 0xB75E,
+	0x8DD5, 0xB75F, 0x8DD6, 0xB761, 0x8DD7, 0xB762, 0x8DD8, 0xB763,	0x8DD9, 0xB765, 0x8DDA, 0xB766, 0x8DDB, 0xB767, 0x8DDC, 0xB769,
+	0x8DDD, 0xB76A, 0x8DDE, 0xB76B, 0x8DDF, 0xB76C, 0x8DE0, 0xB76D,	0x8DE1, 0xB76E, 0x8DE2, 0xB76F, 0x8DE3, 0xB772, 0x8DE4, 0xB774,
+	0x8DE5, 0xB776, 0x8DE6, 0xB777, 0x8DE7, 0xB778, 0x8DE8, 0xB779,	0x8DE9, 0xB77A, 0x8DEA, 0xB77B, 0x8DEB, 0xB77E, 0x8DEC, 0xB77F,
+	0x8DED, 0xB781, 0x8DEE, 0xB782, 0x8DEF, 0xB783, 0x8DF0, 0xB785,	0x8DF1, 0xB786, 0x8DF2, 0xB787, 0x8DF3, 0xB788, 0x8DF4, 0xB789,
+	0x8DF5, 0xB78A, 0x8DF6, 0xB78B, 0x8DF7, 0xB78E, 0x8DF8, 0xB793,	0x8DF9, 0xB794, 0x8DFA, 0xB795, 0x8DFB, 0xB79A, 0x8DFC, 0xB79B,
+	0x8DFD, 0xB79D, 0x8DFE, 0xB79E, 0x8E41, 0xB79F, 0x8E42, 0xB7A1,	0x8E43, 0xB7A2, 0x8E44, 0xB7A3, 0x8E45, 0xB7A4, 0x8E46, 0xB7A5,
+	0x8E47, 0xB7A6, 0x8E48, 0xB7A7, 0x8E49, 0xB7AA, 0x8E4A, 0xB7AE,	0x8E4B, 0xB7AF, 0x8E4C, 0xB7B0, 0x8E4D, 0xB7B1, 0x8E4E, 0xB7B2,
+	0x8E4F, 0xB7B3, 0x8E50, 0xB7B6, 0x8E51, 0xB7B7, 0x8E52, 0xB7B9,	0x8E53, 0xB7BA, 0x8E54, 0xB7BB, 0x8E55, 0xB7BC, 0x8E56, 0xB7BD,
+	0x8E57, 0xB7BE, 0x8E58, 0xB7BF, 0x8E59, 0xB7C0, 0x8E5A, 0xB7C1,	0x8E61, 0xB7C2, 0x8E62, 0xB7C3, 0x8E63, 0xB7C4, 0x8E64, 0xB7C5,
+	0x8E65, 0xB7C6, 0x8E66, 0xB7C8, 0x8E67, 0xB7CA, 0x8E68, 0xB7CB,	0x8E69, 0xB7CC, 0x8E6A, 0xB7CD, 0x8E6B, 0xB7CE, 0x8E6C, 0xB7CF,
+	0x8E6D, 0xB7D0, 0x8E6E, 0xB7D1, 0x8E6F, 0xB7D2, 0x8E70, 0xB7D3,	0x8E71, 0xB7D4, 0x8E72, 0xB7D5, 0x8E73, 0xB7D6, 0x8E74, 0xB7D7,
+	0x8E75, 0xB7D8, 0x8E76, 0xB7D9, 0x8E77, 0xB7DA, 0x8E78, 0xB7DB,	0x8E79, 0xB7DC, 0x8E7A, 0xB7DD, 0x8E81, 0xB7DE, 0x8E82, 0xB7DF,
+	0x8E83, 0xB7E0, 0x8E84, 0xB7E1, 0x8E85, 0xB7E2, 0x8E86, 0xB7E3,	0x8E87, 0xB7E4, 0x8E88, 0xB7E5, 0x8E89, 0xB7E6, 0x8E8A, 0xB7E7,
+	0x8E8B, 0xB7E8, 0x8E8C, 0xB7E9, 0x8E8D, 0xB7EA, 0x8E8E, 0xB7EB,	0x8E8F, 0xB7EE, 0x8E90, 0xB7EF, 0x8E91, 0xB7F1, 0x8E92, 0xB7F2,
+	0x8E93, 0xB7F3, 0x8E94, 0xB7F5, 0x8E95, 0xB7F6, 0x8E96, 0xB7F7,	0x8E97, 0xB7F8, 0x8E98, 0xB7F9, 0x8E99, 0xB7FA, 0x8E9A, 0xB7FB,
+	0x8E9B, 0xB7FE, 0x8E9C, 0xB802, 0x8E9D, 0xB803, 0x8E9E, 0xB804,	0x8E9F, 0xB805, 0x8EA0, 0xB806, 0x8EA1, 0xB80A, 0x8EA2, 0xB80B,
+	0x8EA3, 0xB80D, 0x8EA4, 0xB80E, 0x8EA5, 0xB80F, 0x8EA6, 0xB811,	0x8EA7, 0xB812, 0x8EA8, 0xB813, 0x8EA9, 0xB814, 0x8EAA, 0xB815,
+	0x8EAB, 0xB816, 0x8EAC, 0xB817, 0x8EAD, 0xB81A, 0x8EAE, 0xB81C,	0x8EAF, 0xB81E, 0x8EB0, 0xB81F, 0x8EB1, 0xB820, 0x8EB2, 0xB821,
+	0x8EB3, 0xB822, 0x8EB4, 0xB823, 0x8EB5, 0xB826, 0x8EB6, 0xB827,	0x8EB7, 0xB829, 0x8EB8, 0xB82A, 0x8EB9, 0xB82B, 0x8EBA, 0xB82D,
+	0x8EBB, 0xB82E, 0x8EBC, 0xB82F, 0x8EBD, 0xB830, 0x8EBE, 0xB831,	0x8EBF, 0xB832, 0x8EC0, 0xB833, 0x8EC1, 0xB836, 0x8EC2, 0xB83A,
+	0x8EC3, 0xB83B, 0x8EC4, 0xB83C, 0x8EC5, 0xB83D, 0x8EC6, 0xB83E,	0x8EC7, 0xB83F, 0x8EC8, 0xB841, 0x8EC9, 0xB842, 0x8ECA, 0xB843,
+	0x8ECB, 0xB845, 0x8ECC, 0xB846, 0x8ECD, 0xB847, 0x8ECE, 0xB848,	0x8ECF, 0xB849, 0x8ED0, 0xB84A, 0x8ED1, 0xB84B, 0x8ED2, 0xB84C,
+	0x8ED3, 0xB84D, 0x8ED4, 0xB84E, 0x8ED5, 0xB84F, 0x8ED6, 0xB850,	0x8ED7, 0xB852, 0x8ED8, 0xB854, 0x8ED9, 0xB855, 0x8EDA, 0xB856,
+	0x8EDB, 0xB857, 0x8EDC, 0xB858, 0x8EDD, 0xB859, 0x8EDE, 0xB85A,	0x8EDF, 0xB85B, 0x8EE0, 0xB85E, 0x8EE1, 0xB85F, 0x8EE2, 0xB861,
+	0x8EE3, 0xB862, 0x8EE4, 0xB863, 0x8EE5, 0xB865, 0x8EE6, 0xB866,	0x8EE7, 0xB867, 0x8EE8, 0xB868, 0x8EE9, 0xB869, 0x8EEA, 0xB86A,
+	0x8EEB, 0xB86B, 0x8EEC, 0xB86E, 0x8EED, 0xB870, 0x8EEE, 0xB872,	0x8EEF, 0xB873, 0x8EF0, 0xB874, 0x8EF1, 0xB875, 0x8EF2, 0xB876,
+	0x8EF3, 0xB877, 0x8EF4, 0xB879, 0x8EF5, 0xB87A, 0x8EF6, 0xB87B,	0x8EF7, 0xB87D, 0x8EF8, 0xB87E, 0x8EF9, 0xB87F, 0x8EFA, 0xB880,
+	0x8EFB, 0xB881, 0x8EFC, 0xB882, 0x8EFD, 0xB883, 0x8EFE, 0xB884,	0x8F41, 0xB885, 0x8F42, 0xB886, 0x8F43, 0xB887, 0x8F44, 0xB888,
+	0x8F45, 0xB889, 0x8F46, 0xB88A, 0x8F47, 0xB88B, 0x8F48, 0xB88C,	0x8F49, 0xB88E, 0x8F4A, 0xB88F, 0x8F4B, 0xB890, 0x8F4C, 0xB891,
+	0x8F4D, 0xB892, 0x8F4E, 0xB893, 0x8F4F, 0xB894, 0x8F50, 0xB895,	0x8F51, 0xB896, 0x8F52, 0xB897, 0x8F53, 0xB898, 0x8F54, 0xB899,
+	0x8F55, 0xB89A, 0x8F56, 0xB89B, 0x8F57, 0xB89C, 0x8F58, 0xB89D,	0x8F59, 0xB89E, 0x8F5A, 0xB89F, 0x8F61, 0xB8A0, 0x8F62, 0xB8A1,
+	0x8F63, 0xB8A2, 0x8F64, 0xB8A3, 0x8F65, 0xB8A4, 0x8F66, 0xB8A5,	0x8F67, 0xB8A6, 0x8F68, 0xB8A7, 0x8F69, 0xB8A9, 0x8F6A, 0xB8AA,
+	0x8F6B, 0xB8AB, 0x8F6C, 0xB8AC, 0x8F6D, 0xB8AD, 0x8F6E, 0xB8AE,	0x8F6F, 0xB8AF, 0x8F70, 0xB8B1, 0x8F71, 0xB8B2, 0x8F72, 0xB8B3,
+	0x8F73, 0xB8B5, 0x8F74, 0xB8B6, 0x8F75, 0xB8B7, 0x8F76, 0xB8B9,	0x8F77, 0xB8BA, 0x8F78, 0xB8BB, 0x8F79, 0xB8BC, 0x8F7A, 0xB8BD,
+	0x8F81, 0xB8BE, 0x8F82, 0xB8BF, 0x8F83, 0xB8C2, 0x8F84, 0xB8C4,	0x8F85, 0xB8C6, 0x8F86, 0xB8C7, 0x8F87, 0xB8C8, 0x8F88, 0xB8C9,
+	0x8F89, 0xB8CA, 0x8F8A, 0xB8CB, 0x8F8B, 0xB8CD, 0x8F8C, 0xB8CE,	0x8F8D, 0xB8CF, 0x8F8E, 0xB8D1, 0x8F8F, 0xB8D2, 0x8F90, 0xB8D3,
+	0x8F91, 0xB8D5, 0x8F92, 0xB8D6, 0x8F93, 0xB8D7, 0x8F94, 0xB8D8,	0x8F95, 0xB8D9, 0x8F96, 0xB8DA, 0x8F97, 0xB8DB, 0x8F98, 0xB8DC,
+	0x8F99, 0xB8DE, 0x8F9A, 0xB8E0, 0x8F9B, 0xB8E2, 0x8F9C, 0xB8E3,	0x8F9D, 0xB8E4, 0x8F9E, 0xB8E5, 0x8F9F, 0xB8E6, 0x8FA0, 0xB8E7,
+	0x8FA1, 0xB8EA, 0x8FA2, 0xB8EB, 0x8FA3, 0xB8ED, 0x8FA4, 0xB8EE,	0x8FA5, 0xB8EF, 0x8FA6, 0xB8F1, 0x8FA7, 0xB8F2, 0x8FA8, 0xB8F3,
+	0x8FA9, 0xB8F4, 0x8FAA, 0xB8F5, 0x8FAB, 0xB8F6, 0x8FAC, 0xB8F7,	0x8FAD, 0xB8FA, 0x8FAE, 0xB8FC, 0x8FAF, 0xB8FE, 0x8FB0, 0xB8FF,
+	0x8FB1, 0xB900, 0x8FB2, 0xB901, 0x8FB3, 0xB902, 0x8FB4, 0xB903,	0x8FB5, 0xB905, 0x8FB6, 0xB906, 0x8FB7, 0xB907, 0x8FB8, 0xB908,
+	0x8FB9, 0xB909, 0x8FBA, 0xB90A, 0x8FBB, 0xB90B, 0x8FBC, 0xB90C,	0x8FBD, 0xB90D, 0x8FBE, 0xB90E, 0x8FBF, 0xB90F, 0x8FC0, 0xB910,
+	0x8FC1, 0xB911, 0x8FC2, 0xB912, 0x8FC3, 0xB913, 0x8FC4, 0xB914,	0x8FC5, 0xB915, 0x8FC6, 0xB916, 0x8FC7, 0xB917, 0x8FC8, 0xB919,
+	0x8FC9, 0xB91A, 0x8FCA, 0xB91B, 0x8FCB, 0xB91C, 0x8FCC, 0xB91D,	0x8FCD, 0xB91E, 0x8FCE, 0xB91F, 0x8FCF, 0xB921, 0x8FD0, 0xB922,
+	0x8FD1, 0xB923, 0x8FD2, 0xB924, 0x8FD3, 0xB925, 0x8FD4, 0xB926,	0x8FD5, 0xB927, 0x8FD6, 0xB928, 0x8FD7, 0xB929, 0x8FD8, 0xB92A,
+	0x8FD9, 0xB92B, 0x8FDA, 0xB92C, 0x8FDB, 0xB92D, 0x8FDC, 0xB92E,	0x8FDD, 0xB92F, 0x8FDE, 0xB930, 0x8FDF, 0xB931, 0x8FE0, 0xB932,
+	0x8FE1, 0xB933, 0x8FE2, 0xB934, 0x8FE3, 0xB935, 0x8FE4, 0xB936,	0x8FE5, 0xB937, 0x8FE6, 0xB938, 0x8FE7, 0xB939, 0x8FE8, 0xB93A,
+	0x8FE9, 0xB93B, 0x8FEA, 0xB93E, 0x8FEB, 0xB93F, 0x8FEC, 0xB941,	0x8FED, 0xB942, 0x8FEE, 0xB943, 0x8FEF, 0xB945, 0x8FF0, 0xB946,
+	0x8FF1, 0xB947, 0x8FF2, 0xB948, 0x8FF3, 0xB949, 0x8FF4, 0xB94A,	0x8FF5, 0xB94B, 0x8FF6, 0xB94D, 0x8FF7, 0xB94E, 0x8FF8, 0xB950,
+	0x8FF9, 0xB952, 0x8FFA, 0xB953, 0x8FFB, 0xB954, 0x8FFC, 0xB955,	0x8FFD, 0xB956, 0x8FFE, 0xB957, 0x9041, 0xB95A, 0x9042, 0xB95B,
+	0x9043, 0xB95D, 0x9044, 0xB95E, 0x9045, 0xB95F, 0x9046, 0xB961,	0x9047, 0xB962, 0x9048, 0xB963, 0x9049, 0xB964, 0x904A, 0xB965,
+	0x904B, 0xB966, 0x904C, 0xB967, 0x904D, 0xB96A, 0x904E, 0xB96C,	0x904F, 0xB96E, 0x9050, 0xB96F, 0x9051, 0xB970, 0x9052, 0xB971,
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+	0x9843, 0xC042, 0x9844, 0xC043, 0x9845, 0xC044, 0x9846, 0xC045,	0x9847, 0xC046, 0x9848, 0xC047, 0x9849, 0xC048, 0x984A, 0xC049,
+	0x984B, 0xC04A, 0x984C, 0xC04B, 0x984D, 0xC04C, 0x984E, 0xC04D,	0x984F, 0xC04E, 0x9850, 0xC04F, 0x9851, 0xC050, 0x9852, 0xC052,
+	0x9853, 0xC053, 0x9854, 0xC054, 0x9855, 0xC055, 0x9856, 0xC056,	0x9857, 0xC057, 0x9858, 0xC059, 0x9859, 0xC05A, 0x985A, 0xC05B,
+	0x9861, 0xC05D, 0x9862, 0xC05E, 0x9863, 0xC05F, 0x9864, 0xC061,	0x9865, 0xC062, 0x9866, 0xC063, 0x9867, 0xC064, 0x9868, 0xC065,
+	0x9869, 0xC066, 0x986A, 0xC067, 0x986B, 0xC06A, 0x986C, 0xC06B,	0x986D, 0xC06C, 0x986E, 0xC06D, 0x986F, 0xC06E, 0x9870, 0xC06F,
+	0x9871, 0xC070, 0x9872, 0xC071, 0x9873, 0xC072, 0x9874, 0xC073,	0x9875, 0xC074, 0x9876, 0xC075, 0x9877, 0xC076, 0x9878, 0xC077,
+	0x9879, 0xC078, 0x987A, 0xC079, 0x9881, 0xC07A, 0x9882, 0xC07B,	0x9883, 0xC07C, 0x9884, 0xC07D, 0x9885, 0xC07E, 0x9886, 0xC07F,
+	0x9887, 0xC080, 0x9888, 0xC081, 0x9889, 0xC082, 0x988A, 0xC083,	0x988B, 0xC084, 0x988C, 0xC085, 0x988D, 0xC086, 0x988E, 0xC087,
+	0x988F, 0xC088, 0x9890, 0xC089, 0x9891, 0xC08A, 0x9892, 0xC08B,	0x9893, 0xC08C, 0x9894, 0xC08D, 0x9895, 0xC08E, 0x9896, 0xC08F,
+	0x9897, 0xC092, 0x9898, 0xC093, 0x9899, 0xC095, 0x989A, 0xC096,	0x989B, 0xC097, 0x989C, 0xC099, 0x989D, 0xC09A, 0x989E, 0xC09B,
+	0x989F, 0xC09C, 0x98A0, 0xC09D, 0x98A1, 0xC09E, 0x98A2, 0xC09F,	0x98A3, 0xC0A2, 0x98A4, 0xC0A4, 0x98A5, 0xC0A6, 0x98A6, 0xC0A7,
+	0x98A7, 0xC0A8, 0x98A8, 0xC0A9, 0x98A9, 0xC0AA, 0x98AA, 0xC0AB,	0x98AB, 0xC0AE, 0x98AC, 0xC0B1, 0x98AD, 0xC0B2, 0x98AE, 0xC0B7,
+	0x98AF, 0xC0B8, 0x98B0, 0xC0B9, 0x98B1, 0xC0BA, 0x98B2, 0xC0BB,	0x98B3, 0xC0BE, 0x98B4, 0xC0C2, 0x98B5, 0xC0C3, 0x98B6, 0xC0C4,
+	0x98B7, 0xC0C6, 0x98B8, 0xC0C7, 0x98B9, 0xC0CA, 0x98BA, 0xC0CB,	0x98BB, 0xC0CD, 0x98BC, 0xC0CE, 0x98BD, 0xC0CF, 0x98BE, 0xC0D1,
+	0x98BF, 0xC0D2, 0x98C0, 0xC0D3, 0x98C1, 0xC0D4, 0x98C2, 0xC0D5,	0x98C3, 0xC0D6, 0x98C4, 0xC0D7, 0x98C5, 0xC0DA, 0x98C6, 0xC0DE,
+	0x98C7, 0xC0DF, 0x98C8, 0xC0E0, 0x98C9, 0xC0E1, 0x98CA, 0xC0E2,	0x98CB, 0xC0E3, 0x98CC, 0xC0E6, 0x98CD, 0xC0E7, 0x98CE, 0xC0E9,
+	0x98CF, 0xC0EA, 0x98D0, 0xC0EB, 0x98D1, 0xC0ED, 0x98D2, 0xC0EE,	0x98D3, 0xC0EF, 0x98D4, 0xC0F0, 0x98D5, 0xC0F1, 0x98D6, 0xC0F2,
+	0x98D7, 0xC0F3, 0x98D8, 0xC0F6, 0x98D9, 0xC0F8, 0x98DA, 0xC0FA,	0x98DB, 0xC0FB, 0x98DC, 0xC0FC, 0x98DD, 0xC0FD, 0x98DE, 0xC0FE,
+	0x98DF, 0xC0FF, 0x98E0, 0xC101, 0x98E1, 0xC102, 0x98E2, 0xC103,	0x98E3, 0xC105, 0x98E4, 0xC106, 0x98E5, 0xC107, 0x98E6, 0xC109,
+	0x98E7, 0xC10A, 0x98E8, 0xC10B, 0x98E9, 0xC10C, 0x98EA, 0xC10D,	0x98EB, 0xC10E, 0x98EC, 0xC10F, 0x98ED, 0xC111, 0x98EE, 0xC112,
+	0x98EF, 0xC113, 0x98F0, 0xC114, 0x98F1, 0xC116, 0x98F2, 0xC117,	0x98F3, 0xC118, 0x98F4, 0xC119, 0x98F5, 0xC11A, 0x98F6, 0xC11B,
+	0x98F7, 0xC121, 0x98F8, 0xC122, 0x98F9, 0xC125, 0x98FA, 0xC128,	0x98FB, 0xC129, 0x98FC, 0xC12A, 0x98FD, 0xC12B, 0x98FE, 0xC12E,
+	0x9941, 0xC132, 0x9942, 0xC133, 0x9943, 0xC134, 0x9944, 0xC135,	0x9945, 0xC137, 0x9946, 0xC13A, 0x9947, 0xC13B, 0x9948, 0xC13D,
+	0x9949, 0xC13E, 0x994A, 0xC13F, 0x994B, 0xC141, 0x994C, 0xC142,	0x994D, 0xC143, 0x994E, 0xC144, 0x994F, 0xC145, 0x9950, 0xC146,
+	0x9951, 0xC147, 0x9952, 0xC14A, 0x9953, 0xC14E, 0x9954, 0xC14F,	0x9955, 0xC150, 0x9956, 0xC151, 0x9957, 0xC152, 0x9958, 0xC153,
+	0x9959, 0xC156, 0x995A, 0xC157, 0x9961, 0xC159, 0x9962, 0xC15A,	0x9963, 0xC15B, 0x9964, 0xC15D, 0x9965, 0xC15E, 0x9966, 0xC15F,
+	0x9967, 0xC160, 0x9968, 0xC161, 0x9969, 0xC162, 0x996A, 0xC163,	0x996B, 0xC166, 0x996C, 0xC16A, 0x996D, 0xC16B, 0x996E, 0xC16C,
+	0x996F, 0xC16D, 0x9970, 0xC16E, 0x9971, 0xC16F, 0x9972, 0xC171,	0x9973, 0xC172, 0x9974, 0xC173, 0x9975, 0xC175, 0x9976, 0xC176,
+	0x9977, 0xC177, 0x9978, 0xC179, 0x9979, 0xC17A, 0x997A, 0xC17B,	0x9981, 0xC17C, 0x9982, 0xC17D, 0x9983, 0xC17E, 0x9984, 0xC17F,
+	0x9985, 0xC180, 0x9986, 0xC181, 0x9987, 0xC182, 0x9988, 0xC183,	0x9989, 0xC184, 0x998A, 0xC186, 0x998B, 0xC187, 0x998C, 0xC188,
+	0x998D, 0xC189, 0x998E, 0xC18A, 0x998F, 0xC18B, 0x9990, 0xC18F,	0x9991, 0xC191, 0x9992, 0xC192, 0x9993, 0xC193, 0x9994, 0xC195,
+	0x9995, 0xC197, 0x9996, 0xC198, 0x9997, 0xC199, 0x9998, 0xC19A,	0x9999, 0xC19B, 0x999A, 0xC19E, 0x999B, 0xC1A0, 0x999C, 0xC1A2,
+	0x999D, 0xC1A3, 0x999E, 0xC1A4, 0x999F, 0xC1A6, 0x99A0, 0xC1A7,	0x99A1, 0xC1AA, 0x99A2, 0xC1AB, 0x99A3, 0xC1AD, 0x99A4, 0xC1AE,
+	0x99A5, 0xC1AF, 0x99A6, 0xC1B1, 0x99A7, 0xC1B2, 0x99A8, 0xC1B3,	0x99A9, 0xC1B4, 0x99AA, 0xC1B5, 0x99AB, 0xC1B6, 0x99AC, 0xC1B7,
+	0x99AD, 0xC1B8, 0x99AE, 0xC1B9, 0x99AF, 0xC1BA, 0x99B0, 0xC1BB,	0x99B1, 0xC1BC, 0x99B2, 0xC1BE, 0x99B3, 0xC1BF, 0x99B4, 0xC1C0,
+	0x99B5, 0xC1C1, 0x99B6, 0xC1C2, 0x99B7, 0xC1C3, 0x99B8, 0xC1C5,	0x99B9, 0xC1C6, 0x99BA, 0xC1C7, 0x99BB, 0xC1C9, 0x99BC, 0xC1CA,
+	0x99BD, 0xC1CB, 0x99BE, 0xC1CD, 0x99BF, 0xC1CE, 0x99C0, 0xC1CF,	0x99C1, 0xC1D0, 0x99C2, 0xC1D1, 0x99C3, 0xC1D2, 0x99C4, 0xC1D3,
+	0x99C5, 0xC1D5, 0x99C6, 0xC1D6, 0x99C7, 0xC1D9, 0x99C8, 0xC1DA,	0x99C9, 0xC1DB, 0x99CA, 0xC1DC, 0x99CB, 0xC1DD, 0x99CC, 0xC1DE,
+	0x99CD, 0xC1DF, 0x99CE, 0xC1E1, 0x99CF, 0xC1E2, 0x99D0, 0xC1E3,	0x99D1, 0xC1E5, 0x99D2, 0xC1E6, 0x99D3, 0xC1E7, 0x99D4, 0xC1E9,
+	0x99D5, 0xC1EA, 0x99D6, 0xC1EB, 0x99D7, 0xC1EC, 0x99D8, 0xC1ED,	0x99D9, 0xC1EE, 0x99DA, 0xC1EF, 0x99DB, 0xC1F2, 0x99DC, 0xC1F4,
+	0x99DD, 0xC1F5, 0x99DE, 0xC1F6, 0x99DF, 0xC1F7, 0x99E0, 0xC1F8,	0x99E1, 0xC1F9, 0x99E2, 0xC1FA, 0x99E3, 0xC1FB, 0x99E4, 0xC1FE,
+	0x99E5, 0xC1FF, 0x99E6, 0xC201, 0x99E7, 0xC202, 0x99E8, 0xC203,	0x99E9, 0xC205, 0x99EA, 0xC206, 0x99EB, 0xC207, 0x99EC, 0xC208,
+	0x99ED, 0xC209, 0x99EE, 0xC20A, 0x99EF, 0xC20B, 0x99F0, 0xC20E,	0x99F1, 0xC210, 0x99F2, 0xC212, 0x99F3, 0xC213, 0x99F4, 0xC214,
+	0x99F5, 0xC215, 0x99F6, 0xC216, 0x99F7, 0xC217, 0x99F8, 0xC21A,	0x99F9, 0xC21B, 0x99FA, 0xC21D, 0x99FB, 0xC21E, 0x99FC, 0xC221,
+	0x99FD, 0xC222, 0x99FE, 0xC223, 0x9A41, 0xC224, 0x9A42, 0xC225,	0x9A43, 0xC226, 0x9A44, 0xC227, 0x9A45, 0xC22A, 0x9A46, 0xC22C,
+	0x9A47, 0xC22E, 0x9A48, 0xC230, 0x9A49, 0xC233, 0x9A4A, 0xC235,	0x9A4B, 0xC236, 0x9A4C, 0xC237, 0x9A4D, 0xC238, 0x9A4E, 0xC239,
+	0x9A4F, 0xC23A, 0x9A50, 0xC23B, 0x9A51, 0xC23C, 0x9A52, 0xC23D,	0x9A53, 0xC23E, 0x9A54, 0xC23F, 0x9A55, 0xC240, 0x9A56, 0xC241,
+	0x9A57, 0xC242, 0x9A58, 0xC243, 0x9A59, 0xC244, 0x9A5A, 0xC245,	0x9A61, 0xC246, 0x9A62, 0xC247, 0x9A63, 0xC249, 0x9A64, 0xC24A,
+	0x9A65, 0xC24B, 0x9A66, 0xC24C, 0x9A67, 0xC24D, 0x9A68, 0xC24E,	0x9A69, 0xC24F, 0x9A6A, 0xC252, 0x9A6B, 0xC253, 0x9A6C, 0xC255,
+	0x9A6D, 0xC256, 0x9A6E, 0xC257, 0x9A6F, 0xC259, 0x9A70, 0xC25A,	0x9A71, 0xC25B, 0x9A72, 0xC25C, 0x9A73, 0xC25D, 0x9A74, 0xC25E,
+	0x9A75, 0xC25F, 0x9A76, 0xC261, 0x9A77, 0xC262, 0x9A78, 0xC263,	0x9A79, 0xC264, 0x9A7A, 0xC266, 0x9A81, 0xC267, 0x9A82, 0xC268,
+	0x9A83, 0xC269, 0x9A84, 0xC26A, 0x9A85, 0xC26B, 0x9A86, 0xC26E,	0x9A87, 0xC26F, 0x9A88, 0xC271, 0x9A89, 0xC272, 0x9A8A, 0xC273,
+	0x9A8B, 0xC275, 0x9A8C, 0xC276, 0x9A8D, 0xC277, 0x9A8E, 0xC278,	0x9A8F, 0xC279, 0x9A90, 0xC27A, 0x9A91, 0xC27B, 0x9A92, 0xC27E,
+	0x9A93, 0xC280, 0x9A94, 0xC282, 0x9A95, 0xC283, 0x9A96, 0xC284,	0x9A97, 0xC285, 0x9A98, 0xC286, 0x9A99, 0xC287, 0x9A9A, 0xC28A,
+	0x9A9B, 0xC28B, 0x9A9C, 0xC28C, 0x9A9D, 0xC28D, 0x9A9E, 0xC28E,	0x9A9F, 0xC28F, 0x9AA0, 0xC291, 0x9AA1, 0xC292, 0x9AA2, 0xC293,
+	0x9AA3, 0xC294, 0x9AA4, 0xC295, 0x9AA5, 0xC296, 0x9AA6, 0xC297,	0x9AA7, 0xC299, 0x9AA8, 0xC29A, 0x9AA9, 0xC29C, 0x9AAA, 0xC29E,
+	0x9AAB, 0xC29F, 0x9AAC, 0xC2A0, 0x9AAD, 0xC2A1, 0x9AAE, 0xC2A2,	0x9AAF, 0xC2A3, 0x9AB0, 0xC2A6, 0x9AB1, 0xC2A7, 0x9AB2, 0xC2A9,
+	0x9AB3, 0xC2AA, 0x9AB4, 0xC2AB, 0x9AB5, 0xC2AE, 0x9AB6, 0xC2AF,	0x9AB7, 0xC2B0, 0x9AB8, 0xC2B1, 0x9AB9, 0xC2B2, 0x9ABA, 0xC2B3,
+	0x9ABB, 0xC2B6, 0x9ABC, 0xC2B8, 0x9ABD, 0xC2BA, 0x9ABE, 0xC2BB,	0x9ABF, 0xC2BC, 0x9AC0, 0xC2BD, 0x9AC1, 0xC2BE, 0x9AC2, 0xC2BF,
+	0x9AC3, 0xC2C0, 0x9AC4, 0xC2C1, 0x9AC5, 0xC2C2, 0x9AC6, 0xC2C3,	0x9AC7, 0xC2C4, 0x9AC8, 0xC2C5, 0x9AC9, 0xC2C6, 0x9ACA, 0xC2C7,
+	0x9ACB, 0xC2C8, 0x9ACC, 0xC2C9, 0x9ACD, 0xC2CA, 0x9ACE, 0xC2CB,	0x9ACF, 0xC2CC, 0x9AD0, 0xC2CD, 0x9AD1, 0xC2CE, 0x9AD2, 0xC2CF,
+	0x9AD3, 0xC2D0, 0x9AD4, 0xC2D1, 0x9AD5, 0xC2D2, 0x9AD6, 0xC2D3,	0x9AD7, 0xC2D4, 0x9AD8, 0xC2D5, 0x9AD9, 0xC2D6, 0x9ADA, 0xC2D7,
+	0x9ADB, 0xC2D8, 0x9ADC, 0xC2D9, 0x9ADD, 0xC2DA, 0x9ADE, 0xC2DB,	0x9ADF, 0xC2DE, 0x9AE0, 0xC2DF, 0x9AE1, 0xC2E1, 0x9AE2, 0xC2E2,
+	0x9AE3, 0xC2E5, 0x9AE4, 0xC2E6, 0x9AE5, 0xC2E7, 0x9AE6, 0xC2E8,	0x9AE7, 0xC2E9, 0x9AE8, 0xC2EA, 0x9AE9, 0xC2EE, 0x9AEA, 0xC2F0,
+	0x9AEB, 0xC2F2, 0x9AEC, 0xC2F3, 0x9AED, 0xC2F4, 0x9AEE, 0xC2F5,	0x9AEF, 0xC2F7, 0x9AF0, 0xC2FA, 0x9AF1, 0xC2FD, 0x9AF2, 0xC2FE,
+	0x9AF3, 0xC2FF, 0x9AF4, 0xC301, 0x9AF5, 0xC302, 0x9AF6, 0xC303,	0x9AF7, 0xC304, 0x9AF8, 0xC305, 0x9AF9, 0xC306, 0x9AFA, 0xC307,
+	0x9AFB, 0xC30A, 0x9AFC, 0xC30B, 0x9AFD, 0xC30E, 0x9AFE, 0xC30F,	0x9B41, 0xC310, 0x9B42, 0xC311, 0x9B43, 0xC312, 0x9B44, 0xC316,
+	0x9B45, 0xC317, 0x9B46, 0xC319, 0x9B47, 0xC31A, 0x9B48, 0xC31B,	0x9B49, 0xC31D, 0x9B4A, 0xC31E, 0x9B4B, 0xC31F, 0x9B4C, 0xC320,
+	0x9B4D, 0xC321, 0x9B4E, 0xC322, 0x9B4F, 0xC323, 0x9B50, 0xC326,	0x9B51, 0xC327, 0x9B52, 0xC32A, 0x9B53, 0xC32B, 0x9B54, 0xC32C,
+	0x9B55, 0xC32D, 0x9B56, 0xC32E, 0x9B57, 0xC32F, 0x9B58, 0xC330,	0x9B59, 0xC331, 0x9B5A, 0xC332, 0x9B61, 0xC333, 0x9B62, 0xC334,
+	0x9B63, 0xC335, 0x9B64, 0xC336, 0x9B65, 0xC337, 0x9B66, 0xC338,	0x9B67, 0xC339, 0x9B68, 0xC33A, 0x9B69, 0xC33B, 0x9B6A, 0xC33C,
+	0x9B6B, 0xC33D, 0x9B6C, 0xC33E, 0x9B6D, 0xC33F, 0x9B6E, 0xC340,	0x9B6F, 0xC341, 0x9B70, 0xC342, 0x9B71, 0xC343, 0x9B72, 0xC344,
+	0x9B73, 0xC346, 0x9B74, 0xC347, 0x9B75, 0xC348, 0x9B76, 0xC349,	0x9B77, 0xC34A, 0x9B78, 0xC34B, 0x9B79, 0xC34C, 0x9B7A, 0xC34D,
+	0x9B81, 0xC34E, 0x9B82, 0xC34F, 0x9B83, 0xC350, 0x9B84, 0xC351,	0x9B85, 0xC352, 0x9B86, 0xC353, 0x9B87, 0xC354, 0x9B88, 0xC355,
+	0x9B89, 0xC356, 0x9B8A, 0xC357, 0x9B8B, 0xC358, 0x9B8C, 0xC359,	0x9B8D, 0xC35A, 0x9B8E, 0xC35B, 0x9B8F, 0xC35C, 0x9B90, 0xC35D,
+	0x9B91, 0xC35E, 0x9B92, 0xC35F, 0x9B93, 0xC360, 0x9B94, 0xC361,	0x9B95, 0xC362, 0x9B96, 0xC363, 0x9B97, 0xC364, 0x9B98, 0xC365,
+	0x9B99, 0xC366, 0x9B9A, 0xC367, 0x9B9B, 0xC36A, 0x9B9C, 0xC36B,	0x9B9D, 0xC36D, 0x9B9E, 0xC36E, 0x9B9F, 0xC36F, 0x9BA0, 0xC371,
+	0x9BA1, 0xC373, 0x9BA2, 0xC374, 0x9BA3, 0xC375, 0x9BA4, 0xC376,	0x9BA5, 0xC377, 0x9BA6, 0xC37A, 0x9BA7, 0xC37B, 0x9BA8, 0xC37E,
+	0x9BA9, 0xC37F, 0x9BAA, 0xC380, 0x9BAB, 0xC381, 0x9BAC, 0xC382,	0x9BAD, 0xC383, 0x9BAE, 0xC385, 0x9BAF, 0xC386, 0x9BB0, 0xC387,
+	0x9BB1, 0xC389, 0x9BB2, 0xC38A, 0x9BB3, 0xC38B, 0x9BB4, 0xC38D,	0x9BB5, 0xC38E, 0x9BB6, 0xC38F, 0x9BB7, 0xC390, 0x9BB8, 0xC391,
+	0x9BB9, 0xC392, 0x9BBA, 0xC393, 0x9BBB, 0xC394, 0x9BBC, 0xC395,	0x9BBD, 0xC396, 0x9BBE, 0xC397, 0x9BBF, 0xC398, 0x9BC0, 0xC399,
+	0x9BC1, 0xC39A, 0x9BC2, 0xC39B, 0x9BC3, 0xC39C, 0x9BC4, 0xC39D,	0x9BC5, 0xC39E, 0x9BC6, 0xC39F, 0x9BC7, 0xC3A0, 0x9BC8, 0xC3A1,
+	0x9BC9, 0xC3A2, 0x9BCA, 0xC3A3, 0x9BCB, 0xC3A4, 0x9BCC, 0xC3A5,	0x9BCD, 0xC3A6, 0x9BCE, 0xC3A7, 0x9BCF, 0xC3A8, 0x9BD0, 0xC3A9,
+	0x9BD1, 0xC3AA, 0x9BD2, 0xC3AB, 0x9BD3, 0xC3AC, 0x9BD4, 0xC3AD,	0x9BD5, 0xC3AE, 0x9BD6, 0xC3AF, 0x9BD7, 0xC3B0, 0x9BD8, 0xC3B1,
+	0x9BD9, 0xC3B2, 0x9BDA, 0xC3B3, 0x9BDB, 0xC3B4, 0x9BDC, 0xC3B5,	0x9BDD, 0xC3B6, 0x9BDE, 0xC3B7, 0x9BDF, 0xC3B8, 0x9BE0, 0xC3B9,
+	0x9BE1, 0xC3BA, 0x9BE2, 0xC3BB, 0x9BE3, 0xC3BC, 0x9BE4, 0xC3BD,	0x9BE5, 0xC3BE, 0x9BE6, 0xC3BF, 0x9BE7, 0xC3C1, 0x9BE8, 0xC3C2,
+	0x9BE9, 0xC3C3, 0x9BEA, 0xC3C4, 0x9BEB, 0xC3C5, 0x9BEC, 0xC3C6,	0x9BED, 0xC3C7, 0x9BEE, 0xC3C8, 0x9BEF, 0xC3C9, 0x9BF0, 0xC3CA,
+	0x9BF1, 0xC3CB, 0x9BF2, 0xC3CC, 0x9BF3, 0xC3CD, 0x9BF4, 0xC3CE,	0x9BF5, 0xC3CF, 0x9BF6, 0xC3D0, 0x9BF7, 0xC3D1, 0x9BF8, 0xC3D2,
+	0x9BF9, 0xC3D3, 0x9BFA, 0xC3D4, 0x9BFB, 0xC3D5, 0x9BFC, 0xC3D6,	0x9BFD, 0xC3D7, 0x9BFE, 0xC3DA, 0x9C41, 0xC3DB, 0x9C42, 0xC3DD,
+	0x9C43, 0xC3DE, 0x9C44, 0xC3E1, 0x9C45, 0xC3E3, 0x9C46, 0xC3E4,	0x9C47, 0xC3E5, 0x9C48, 0xC3E6, 0x9C49, 0xC3E7, 0x9C4A, 0xC3EA,
+	0x9C4B, 0xC3EB, 0x9C4C, 0xC3EC, 0x9C4D, 0xC3EE, 0x9C4E, 0xC3EF,	0x9C4F, 0xC3F0, 0x9C50, 0xC3F1, 0x9C51, 0xC3F2, 0x9C52, 0xC3F3,
+	0x9C53, 0xC3F6, 0x9C54, 0xC3F7, 0x9C55, 0xC3F9, 0x9C56, 0xC3FA,	0x9C57, 0xC3FB, 0x9C58, 0xC3FC, 0x9C59, 0xC3FD, 0x9C5A, 0xC3FE,
+	0x9C61, 0xC3FF, 0x9C62, 0xC400, 0x9C63, 0xC401, 0x9C64, 0xC402,	0x9C65, 0xC403, 0x9C66, 0xC404, 0x9C67, 0xC405, 0x9C68, 0xC406,
+	0x9C69, 0xC407, 0x9C6A, 0xC409, 0x9C6B, 0xC40A, 0x9C6C, 0xC40B,	0x9C6D, 0xC40C, 0x9C6E, 0xC40D, 0x9C6F, 0xC40E, 0x9C70, 0xC40F,
+	0x9C71, 0xC411, 0x9C72, 0xC412, 0x9C73, 0xC413, 0x9C74, 0xC414,	0x9C75, 0xC415, 0x9C76, 0xC416, 0x9C77, 0xC417, 0x9C78, 0xC418,
+	0x9C79, 0xC419, 0x9C7A, 0xC41A, 0x9C81, 0xC41B, 0x9C82, 0xC41C,	0x9C83, 0xC41D, 0x9C84, 0xC41E, 0x9C85, 0xC41F, 0x9C86, 0xC420,
+	0x9C87, 0xC421, 0x9C88, 0xC422, 0x9C89, 0xC423, 0x9C8A, 0xC425,	0x9C8B, 0xC426, 0x9C8C, 0xC427, 0x9C8D, 0xC428, 0x9C8E, 0xC429,
+	0x9C8F, 0xC42A, 0x9C90, 0xC42B, 0x9C91, 0xC42D, 0x9C92, 0xC42E,	0x9C93, 0xC42F, 0x9C94, 0xC431, 0x9C95, 0xC432, 0x9C96, 0xC433,
+	0x9C97, 0xC435, 0x9C98, 0xC436, 0x9C99, 0xC437, 0x9C9A, 0xC438,	0x9C9B, 0xC439, 0x9C9C, 0xC43A, 0x9C9D, 0xC43B, 0x9C9E, 0xC43E,
+	0x9C9F, 0xC43F, 0x9CA0, 0xC440, 0x9CA1, 0xC441, 0x9CA2, 0xC442,	0x9CA3, 0xC443, 0x9CA4, 0xC444, 0x9CA5, 0xC445, 0x9CA6, 0xC446,
+	0x9CA7, 0xC447, 0x9CA8, 0xC449, 0x9CA9, 0xC44A, 0x9CAA, 0xC44B,	0x9CAB, 0xC44C, 0x9CAC, 0xC44D, 0x9CAD, 0xC44E, 0x9CAE, 0xC44F,
+	0x9CAF, 0xC450, 0x9CB0, 0xC451, 0x9CB1, 0xC452, 0x9CB2, 0xC453,	0x9CB3, 0xC454, 0x9CB4, 0xC455, 0x9CB5, 0xC456, 0x9CB6, 0xC457,
+	0x9CB7, 0xC458, 0x9CB8, 0xC459, 0x9CB9, 0xC45A, 0x9CBA, 0xC45B,	0x9CBB, 0xC45C, 0x9CBC, 0xC45D, 0x9CBD, 0xC45E, 0x9CBE, 0xC45F,
+	0x9CBF, 0xC460, 0x9CC0, 0xC461, 0x9CC1, 0xC462, 0x9CC2, 0xC463,	0x9CC3, 0xC466, 0x9CC4, 0xC467, 0x9CC5, 0xC469, 0x9CC6, 0xC46A,
+	0x9CC7, 0xC46B, 0x9CC8, 0xC46D, 0x9CC9, 0xC46E, 0x9CCA, 0xC46F,	0x9CCB, 0xC470, 0x9CCC, 0xC471, 0x9CCD, 0xC472, 0x9CCE, 0xC473,
+	0x9CCF, 0xC476, 0x9CD0, 0xC477, 0x9CD1, 0xC478, 0x9CD2, 0xC47A,	0x9CD3, 0xC47B, 0x9CD4, 0xC47C, 0x9CD5, 0xC47D, 0x9CD6, 0xC47E,
+	0x9CD7, 0xC47F, 0x9CD8, 0xC481, 0x9CD9, 0xC482, 0x9CDA, 0xC483,	0x9CDB, 0xC484, 0x9CDC, 0xC485, 0x9CDD, 0xC486, 0x9CDE, 0xC487,
+	0x9CDF, 0xC488, 0x9CE0, 0xC489, 0x9CE1, 0xC48A, 0x9CE2, 0xC48B,	0x9CE3, 0xC48C, 0x9CE4, 0xC48D, 0x9CE5, 0xC48E, 0x9CE6, 0xC48F,
+	0x9CE7, 0xC490, 0x9CE8, 0xC491, 0x9CE9, 0xC492, 0x9CEA, 0xC493,	0x9CEB, 0xC495, 0x9CEC, 0xC496, 0x9CED, 0xC497, 0x9CEE, 0xC498,
+	0x9CEF, 0xC499, 0x9CF0, 0xC49A, 0x9CF1, 0xC49B, 0x9CF2, 0xC49D,	0x9CF3, 0xC49E, 0x9CF4, 0xC49F, 0x9CF5, 0xC4A0, 0x9CF6, 0xC4A1,
+	0x9CF7, 0xC4A2, 0x9CF8, 0xC4A3, 0x9CF9, 0xC4A4, 0x9CFA, 0xC4A5,	0x9CFB, 0xC4A6, 0x9CFC, 0xC4A7, 0x9CFD, 0xC4A8, 0x9CFE, 0xC4A9,
+	0x9D41, 0xC4AA, 0x9D42, 0xC4AB, 0x9D43, 0xC4AC, 0x9D44, 0xC4AD,	0x9D45, 0xC4AE, 0x9D46, 0xC4AF, 0x9D47, 0xC4B0, 0x9D48, 0xC4B1,
+	0x9D49, 0xC4B2, 0x9D4A, 0xC4B3, 0x9D4B, 0xC4B4, 0x9D4C, 0xC4B5,	0x9D4D, 0xC4B6, 0x9D4E, 0xC4B7, 0x9D4F, 0xC4B9, 0x9D50, 0xC4BA,
+	0x9D51, 0xC4BB, 0x9D52, 0xC4BD, 0x9D53, 0xC4BE, 0x9D54, 0xC4BF,	0x9D55, 0xC4C0, 0x9D56, 0xC4C1, 0x9D57, 0xC4C2, 0x9D58, 0xC4C3,
+	0x9D59, 0xC4C4, 0x9D5A, 0xC4C5, 0x9D61, 0xC4C6, 0x9D62, 0xC4C7,	0x9D63, 0xC4C8, 0x9D64, 0xC4C9, 0x9D65, 0xC4CA, 0x9D66, 0xC4CB,
+	0x9D67, 0xC4CC, 0x9D68, 0xC4CD, 0x9D69, 0xC4CE, 0x9D6A, 0xC4CF,	0x9D6B, 0xC4D0, 0x9D6C, 0xC4D1, 0x9D6D, 0xC4D2, 0x9D6E, 0xC4D3,
+	0x9D6F, 0xC4D4, 0x9D70, 0xC4D5, 0x9D71, 0xC4D6, 0x9D72, 0xC4D7,	0x9D73, 0xC4D8, 0x9D74, 0xC4D9, 0x9D75, 0xC4DA, 0x9D76, 0xC4DB,
+	0x9D77, 0xC4DC, 0x9D78, 0xC4DD, 0x9D79, 0xC4DE, 0x9D7A, 0xC4DF,	0x9D81, 0xC4E0, 0x9D82, 0xC4E1, 0x9D83, 0xC4E2, 0x9D84, 0xC4E3,
+	0x9D85, 0xC4E4, 0x9D86, 0xC4E5, 0x9D87, 0xC4E6, 0x9D88, 0xC4E7,	0x9D89, 0xC4E8, 0x9D8A, 0xC4EA, 0x9D8B, 0xC4EB, 0x9D8C, 0xC4EC,
+	0x9D8D, 0xC4ED, 0x9D8E, 0xC4EE, 0x9D8F, 0xC4EF, 0x9D90, 0xC4F2,	0x9D91, 0xC4F3, 0x9D92, 0xC4F5, 0x9D93, 0xC4F6, 0x9D94, 0xC4F7,
+	0x9D95, 0xC4F9, 0x9D96, 0xC4FB, 0x9D97, 0xC4FC, 0x9D98, 0xC4FD,	0x9D99, 0xC4FE, 0x9D9A, 0xC502, 0x9D9B, 0xC503, 0x9D9C, 0xC504,
+	0x9D9D, 0xC505, 0x9D9E, 0xC506, 0x9D9F, 0xC507, 0x9DA0, 0xC508,	0x9DA1, 0xC509, 0x9DA2, 0xC50A, 0x9DA3, 0xC50B, 0x9DA4, 0xC50D,
+	0x9DA5, 0xC50E, 0x9DA6, 0xC50F, 0x9DA7, 0xC511, 0x9DA8, 0xC512,	0x9DA9, 0xC513, 0x9DAA, 0xC515, 0x9DAB, 0xC516, 0x9DAC, 0xC517,
+	0x9DAD, 0xC518, 0x9DAE, 0xC519, 0x9DAF, 0xC51A, 0x9DB0, 0xC51B,	0x9DB1, 0xC51D, 0x9DB2, 0xC51E, 0x9DB3, 0xC51F, 0x9DB4, 0xC520,
+	0x9DB5, 0xC521, 0x9DB6, 0xC522, 0x9DB7, 0xC523, 0x9DB8, 0xC524,	0x9DB9, 0xC525, 0x9DBA, 0xC526, 0x9DBB, 0xC527, 0x9DBC, 0xC52A,
+	0x9DBD, 0xC52B, 0x9DBE, 0xC52D, 0x9DBF, 0xC52E, 0x9DC0, 0xC52F,	0x9DC1, 0xC531, 0x9DC2, 0xC532, 0x9DC3, 0xC533, 0x9DC4, 0xC534,
+	0x9DC5, 0xC535, 0x9DC6, 0xC536, 0x9DC7, 0xC537, 0x9DC8, 0xC53A,	0x9DC9, 0xC53C, 0x9DCA, 0xC53E, 0x9DCB, 0xC53F, 0x9DCC, 0xC540,
+	0x9DCD, 0xC541, 0x9DCE, 0xC542, 0x9DCF, 0xC543, 0x9DD0, 0xC546,	0x9DD1, 0xC547, 0x9DD2, 0xC54B, 0x9DD3, 0xC54F, 0x9DD4, 0xC550,
+	0x9DD5, 0xC551, 0x9DD6, 0xC552, 0x9DD7, 0xC556, 0x9DD8, 0xC55A,	0x9DD9, 0xC55B, 0x9DDA, 0xC55C, 0x9DDB, 0xC55F, 0x9DDC, 0xC562,
+	0x9DDD, 0xC563, 0x9DDE, 0xC565, 0x9DDF, 0xC566, 0x9DE0, 0xC567,	0x9DE1, 0xC569, 0x9DE2, 0xC56A, 0x9DE3, 0xC56B, 0x9DE4, 0xC56C,
+	0x9DE5, 0xC56D, 0x9DE6, 0xC56E, 0x9DE7, 0xC56F, 0x9DE8, 0xC572,	0x9DE9, 0xC576, 0x9DEA, 0xC577, 0x9DEB, 0xC578, 0x9DEC, 0xC579,
+	0x9DED, 0xC57A, 0x9DEE, 0xC57B, 0x9DEF, 0xC57E, 0x9DF0, 0xC57F,	0x9DF1, 0xC581, 0x9DF2, 0xC582, 0x9DF3, 0xC583, 0x9DF4, 0xC585,
+	0x9DF5, 0xC586, 0x9DF6, 0xC588, 0x9DF7, 0xC589, 0x9DF8, 0xC58A,	0x9DF9, 0xC58B, 0x9DFA, 0xC58E, 0x9DFB, 0xC590, 0x9DFC, 0xC592,
+	0x9DFD, 0xC593, 0x9DFE, 0xC594, 0x9E41, 0xC596, 0x9E42, 0xC599,	0x9E43, 0xC59A, 0x9E44, 0xC59B, 0x9E45, 0xC59D, 0x9E46, 0xC59E,
+	0x9E47, 0xC59F, 0x9E48, 0xC5A1, 0x9E49, 0xC5A2, 0x9E4A, 0xC5A3,	0x9E4B, 0xC5A4, 0x9E4C, 0xC5A5, 0x9E4D, 0xC5A6, 0x9E4E, 0xC5A7,
+	0x9E4F, 0xC5A8, 0x9E50, 0xC5AA, 0x9E51, 0xC5AB, 0x9E52, 0xC5AC,	0x9E53, 0xC5AD, 0x9E54, 0xC5AE, 0x9E55, 0xC5AF, 0x9E56, 0xC5B0,
+	0x9E57, 0xC5B1, 0x9E58, 0xC5B2, 0x9E59, 0xC5B3, 0x9E5A, 0xC5B6,	0x9E61, 0xC5B7, 0x9E62, 0xC5BA, 0x9E63, 0xC5BF, 0x9E64, 0xC5C0,
+	0x9E65, 0xC5C1, 0x9E66, 0xC5C2, 0x9E67, 0xC5C3, 0x9E68, 0xC5CB,	0x9E69, 0xC5CD, 0x9E6A, 0xC5CF, 0x9E6B, 0xC5D2, 0x9E6C, 0xC5D3,
+	0x9E6D, 0xC5D5, 0x9E6E, 0xC5D6, 0x9E6F, 0xC5D7, 0x9E70, 0xC5D9,	0x9E71, 0xC5DA, 0x9E72, 0xC5DB, 0x9E73, 0xC5DC, 0x9E74, 0xC5DD,
+	0x9E75, 0xC5DE, 0x9E76, 0xC5DF, 0x9E77, 0xC5E2, 0x9E78, 0xC5E4,	0x9E79, 0xC5E6, 0x9E7A, 0xC5E7, 0x9E81, 0xC5E8, 0x9E82, 0xC5E9,
+	0x9E83, 0xC5EA, 0x9E84, 0xC5EB, 0x9E85, 0xC5EF, 0x9E86, 0xC5F1,	0x9E87, 0xC5F2, 0x9E88, 0xC5F3, 0x9E89, 0xC5F5, 0x9E8A, 0xC5F8,
+	0x9E8B, 0xC5F9, 0x9E8C, 0xC5FA, 0x9E8D, 0xC5FB, 0x9E8E, 0xC602,	0x9E8F, 0xC603, 0x9E90, 0xC604, 0x9E91, 0xC609, 0x9E92, 0xC60A,
+	0x9E93, 0xC60B, 0x9E94, 0xC60D, 0x9E95, 0xC60E, 0x9E96, 0xC60F,	0x9E97, 0xC611, 0x9E98, 0xC612, 0x9E99, 0xC613, 0x9E9A, 0xC614,
+	0x9E9B, 0xC615, 0x9E9C, 0xC616, 0x9E9D, 0xC617, 0x9E9E, 0xC61A,	0x9E9F, 0xC61D, 0x9EA0, 0xC61E, 0x9EA1, 0xC61F, 0x9EA2, 0xC620,
+	0x9EA3, 0xC621, 0x9EA4, 0xC622, 0x9EA5, 0xC623, 0x9EA6, 0xC626,	0x9EA7, 0xC627, 0x9EA8, 0xC629, 0x9EA9, 0xC62A, 0x9EAA, 0xC62B,
+	0x9EAB, 0xC62F, 0x9EAC, 0xC631, 0x9EAD, 0xC632, 0x9EAE, 0xC636,	0x9EAF, 0xC638, 0x9EB0, 0xC63A, 0x9EB1, 0xC63C, 0x9EB2, 0xC63D,
+	0x9EB3, 0xC63E, 0x9EB4, 0xC63F, 0x9EB5, 0xC642, 0x9EB6, 0xC643,	0x9EB7, 0xC645, 0x9EB8, 0xC646, 0x9EB9, 0xC647, 0x9EBA, 0xC649,
+	0x9EBB, 0xC64A, 0x9EBC, 0xC64B, 0x9EBD, 0xC64C, 0x9EBE, 0xC64D,	0x9EBF, 0xC64E, 0x9EC0, 0xC64F, 0x9EC1, 0xC652, 0x9EC2, 0xC656,
+	0x9EC3, 0xC657, 0x9EC4, 0xC658, 0x9EC5, 0xC659, 0x9EC6, 0xC65A,	0x9EC7, 0xC65B, 0x9EC8, 0xC65E, 0x9EC9, 0xC65F, 0x9ECA, 0xC661,
+	0x9ECB, 0xC662, 0x9ECC, 0xC663, 0x9ECD, 0xC664, 0x9ECE, 0xC665,	0x9ECF, 0xC666, 0x9ED0, 0xC667, 0x9ED1, 0xC668, 0x9ED2, 0xC669,
+	0x9ED3, 0xC66A, 0x9ED4, 0xC66B, 0x9ED5, 0xC66D, 0x9ED6, 0xC66E,	0x9ED7, 0xC670, 0x9ED8, 0xC672, 0x9ED9, 0xC673, 0x9EDA, 0xC674,
+	0x9EDB, 0xC675, 0x9EDC, 0xC676, 0x9EDD, 0xC677, 0x9EDE, 0xC67A,	0x9EDF, 0xC67B, 0x9EE0, 0xC67D, 0x9EE1, 0xC67E, 0x9EE2, 0xC67F,
+	0x9EE3, 0xC681, 0x9EE4, 0xC682, 0x9EE5, 0xC683, 0x9EE6, 0xC684,	0x9EE7, 0xC685, 0x9EE8, 0xC686, 0x9EE9, 0xC687, 0x9EEA, 0xC68A,
+	0x9EEB, 0xC68C, 0x9EEC, 0xC68E, 0x9EED, 0xC68F, 0x9EEE, 0xC690,	0x9EEF, 0xC691, 0x9EF0, 0xC692, 0x9EF1, 0xC693, 0x9EF2, 0xC696,
+	0x9EF3, 0xC697, 0x9EF4, 0xC699, 0x9EF5, 0xC69A, 0x9EF6, 0xC69B,	0x9EF7, 0xC69D, 0x9EF8, 0xC69E, 0x9EF9, 0xC69F, 0x9EFA, 0xC6A0,
+	0x9EFB, 0xC6A1, 0x9EFC, 0xC6A2, 0x9EFD, 0xC6A3, 0x9EFE, 0xC6A6,	0x9F41, 0xC6A8, 0x9F42, 0xC6AA, 0x9F43, 0xC6AB, 0x9F44, 0xC6AC,
+	0x9F45, 0xC6AD, 0x9F46, 0xC6AE, 0x9F47, 0xC6AF, 0x9F48, 0xC6B2,	0x9F49, 0xC6B3, 0x9F4A, 0xC6B5, 0x9F4B, 0xC6B6, 0x9F4C, 0xC6B7,
+	0x9F4D, 0xC6BB, 0x9F4E, 0xC6BC, 0x9F4F, 0xC6BD, 0x9F50, 0xC6BE,	0x9F51, 0xC6BF, 0x9F52, 0xC6C2, 0x9F53, 0xC6C4, 0x9F54, 0xC6C6,
+	0x9F55, 0xC6C7, 0x9F56, 0xC6C8, 0x9F57, 0xC6C9, 0x9F58, 0xC6CA,	0x9F59, 0xC6CB, 0x9F5A, 0xC6CE, 0x9F61, 0xC6CF, 0x9F62, 0xC6D1,
+	0x9F63, 0xC6D2, 0x9F64, 0xC6D3, 0x9F65, 0xC6D5, 0x9F66, 0xC6D6,	0x9F67, 0xC6D7, 0x9F68, 0xC6D8, 0x9F69, 0xC6D9, 0x9F6A, 0xC6DA,
+	0x9F6B, 0xC6DB, 0x9F6C, 0xC6DE, 0x9F6D, 0xC6DF, 0x9F6E, 0xC6E2,	0x9F6F, 0xC6E3, 0x9F70, 0xC6E4, 0x9F71, 0xC6E5, 0x9F72, 0xC6E6,
+	0x9F73, 0xC6E7, 0x9F74, 0xC6EA, 0x9F75, 0xC6EB, 0x9F76, 0xC6ED,	0x9F77, 0xC6EE, 0x9F78, 0xC6EF, 0x9F79, 0xC6F1, 0x9F7A, 0xC6F2,
+	0x9F81, 0xC6F3, 0x9F82, 0xC6F4, 0x9F83, 0xC6F5, 0x9F84, 0xC6F6,	0x9F85, 0xC6F7, 0x9F86, 0xC6FA, 0x9F87, 0xC6FB, 0x9F88, 0xC6FC,
+	0x9F89, 0xC6FE, 0x9F8A, 0xC6FF, 0x9F8B, 0xC700, 0x9F8C, 0xC701,	0x9F8D, 0xC702, 0x9F8E, 0xC703, 0x9F8F, 0xC706, 0x9F90, 0xC707,
+	0x9F91, 0xC709, 0x9F92, 0xC70A, 0x9F93, 0xC70B, 0x9F94, 0xC70D,	0x9F95, 0xC70E, 0x9F96, 0xC70F, 0x9F97, 0xC710, 0x9F98, 0xC711,
+	0x9F99, 0xC712, 0x9F9A, 0xC713, 0x9F9B, 0xC716, 0x9F9C, 0xC718,	0x9F9D, 0xC71A, 0x9F9E, 0xC71B, 0x9F9F, 0xC71C, 0x9FA0, 0xC71D,
+	0x9FA1, 0xC71E, 0x9FA2, 0xC71F, 0x9FA3, 0xC722, 0x9FA4, 0xC723,	0x9FA5, 0xC725, 0x9FA6, 0xC726, 0x9FA7, 0xC727, 0x9FA8, 0xC729,
+	0x9FA9, 0xC72A, 0x9FAA, 0xC72B, 0x9FAB, 0xC72C, 0x9FAC, 0xC72D,	0x9FAD, 0xC72E, 0x9FAE, 0xC72F, 0x9FAF, 0xC732, 0x9FB0, 0xC734,
+	0x9FB1, 0xC736, 0x9FB2, 0xC738, 0x9FB3, 0xC739, 0x9FB4, 0xC73A,	0x9FB5, 0xC73B, 0x9FB6, 0xC73E, 0x9FB7, 0xC73F, 0x9FB8, 0xC741,
+	0x9FB9, 0xC742, 0x9FBA, 0xC743, 0x9FBB, 0xC745, 0x9FBC, 0xC746,	0x9FBD, 0xC747, 0x9FBE, 0xC748, 0x9FBF, 0xC749, 0x9FC0, 0xC74B,
+	0x9FC1, 0xC74E, 0x9FC2, 0xC750, 0x9FC3, 0xC759, 0x9FC4, 0xC75A,	0x9FC5, 0xC75B, 0x9FC6, 0xC75D, 0x9FC7, 0xC75E, 0x9FC8, 0xC75F,
+	0x9FC9, 0xC761, 0x9FCA, 0xC762, 0x9FCB, 0xC763, 0x9FCC, 0xC764,	0x9FCD, 0xC765, 0x9FCE, 0xC766, 0x9FCF, 0xC767, 0x9FD0, 0xC769,
+	0x9FD1, 0xC76A, 0x9FD2, 0xC76C, 0x9FD3, 0xC76D, 0x9FD4, 0xC76E,	0x9FD5, 0xC76F, 0x9FD6, 0xC770, 0x9FD7, 0xC771, 0x9FD8, 0xC772,
+	0x9FD9, 0xC773, 0x9FDA, 0xC776, 0x9FDB, 0xC777, 0x9FDC, 0xC779,	0x9FDD, 0xC77A, 0x9FDE, 0xC77B, 0x9FDF, 0xC77F, 0x9FE0, 0xC780,
+	0x9FE1, 0xC781, 0x9FE2, 0xC782, 0x9FE3, 0xC786, 0x9FE4, 0xC78B,	0x9FE5, 0xC78C, 0x9FE6, 0xC78D, 0x9FE7, 0xC78F, 0x9FE8, 0xC792,
+	0x9FE9, 0xC793, 0x9FEA, 0xC795, 0x9FEB, 0xC799, 0x9FEC, 0xC79B,	0x9FED, 0xC79C, 0x9FEE, 0xC79D, 0x9FEF, 0xC79E, 0x9FF0, 0xC79F,
+	0x9FF1, 0xC7A2, 0x9FF2, 0xC7A7, 0x9FF3, 0xC7A8, 0x9FF4, 0xC7A9,	0x9FF5, 0xC7AA, 0x9FF6, 0xC7AB, 0x9FF7, 0xC7AE, 0x9FF8, 0xC7AF,
+	0x9FF9, 0xC7B1, 0x9FFA, 0xC7B2, 0x9FFB, 0xC7B3, 0x9FFC, 0xC7B5,	0x9FFD, 0xC7B6, 0x9FFE, 0xC7B7, 0xA041, 0xC7B8, 0xA042, 0xC7B9,
+	0xA043, 0xC7BA, 0xA044, 0xC7BB, 0xA045, 0xC7BE, 0xA046, 0xC7C2,	0xA047, 0xC7C3, 0xA048, 0xC7C4, 0xA049, 0xC7C5, 0xA04A, 0xC7C6,
+	0xA04B, 0xC7C7, 0xA04C, 0xC7CA, 0xA04D, 0xC7CB, 0xA04E, 0xC7CD,	0xA04F, 0xC7CF, 0xA050, 0xC7D1, 0xA051, 0xC7D2, 0xA052, 0xC7D3,
+	0xA053, 0xC7D4, 0xA054, 0xC7D5, 0xA055, 0xC7D6, 0xA056, 0xC7D7,	0xA057, 0xC7D9, 0xA058, 0xC7DA, 0xA059, 0xC7DB, 0xA05A, 0xC7DC,
+	0xA061, 0xC7DE, 0xA062, 0xC7DF, 0xA063, 0xC7E0, 0xA064, 0xC7E1,	0xA065, 0xC7E2, 0xA066, 0xC7E3, 0xA067, 0xC7E5, 0xA068, 0xC7E6,
+	0xA069, 0xC7E7, 0xA06A, 0xC7E9, 0xA06B, 0xC7EA, 0xA06C, 0xC7EB,	0xA06D, 0xC7ED, 0xA06E, 0xC7EE, 0xA06F, 0xC7EF, 0xA070, 0xC7F0,
+	0xA071, 0xC7F1, 0xA072, 0xC7F2, 0xA073, 0xC7F3, 0xA074, 0xC7F4,	0xA075, 0xC7F5, 0xA076, 0xC7F6, 0xA077, 0xC7F7, 0xA078, 0xC7F8,
+	0xA079, 0xC7F9, 0xA07A, 0xC7FA, 0xA081, 0xC7FB, 0xA082, 0xC7FC,	0xA083, 0xC7FD, 0xA084, 0xC7FE, 0xA085, 0xC7FF, 0xA086, 0xC802,
+	0xA087, 0xC803, 0xA088, 0xC805, 0xA089, 0xC806, 0xA08A, 0xC807,	0xA08B, 0xC809, 0xA08C, 0xC80B, 0xA08D, 0xC80C, 0xA08E, 0xC80D,
+	0xA08F, 0xC80E, 0xA090, 0xC80F, 0xA091, 0xC812, 0xA092, 0xC814,	0xA093, 0xC817, 0xA094, 0xC818, 0xA095, 0xC819, 0xA096, 0xC81A,
+	0xA097, 0xC81B, 0xA098, 0xC81E, 0xA099, 0xC81F, 0xA09A, 0xC821,	0xA09B, 0xC822, 0xA09C, 0xC823, 0xA09D, 0xC825, 0xA09E, 0xC826,
+	0xA09F, 0xC827, 0xA0A0, 0xC828, 0xA0A1, 0xC829, 0xA0A2, 0xC82A,	0xA0A3, 0xC82B, 0xA0A4, 0xC82E, 0xA0A5, 0xC830, 0xA0A6, 0xC832,
+	0xA0A7, 0xC833, 0xA0A8, 0xC834, 0xA0A9, 0xC835, 0xA0AA, 0xC836,	0xA0AB, 0xC837, 0xA0AC, 0xC839, 0xA0AD, 0xC83A, 0xA0AE, 0xC83B,
+	0xA0AF, 0xC83D, 0xA0B0, 0xC83E, 0xA0B1, 0xC83F, 0xA0B2, 0xC841,	0xA0B3, 0xC842, 0xA0B4, 0xC843, 0xA0B5, 0xC844, 0xA0B6, 0xC845,
+	0xA0B7, 0xC846, 0xA0B8, 0xC847, 0xA0B9, 0xC84A, 0xA0BA, 0xC84B,	0xA0BB, 0xC84E, 0xA0BC, 0xC84F, 0xA0BD, 0xC850, 0xA0BE, 0xC851,
+	0xA0BF, 0xC852, 0xA0C0, 0xC853, 0xA0C1, 0xC855, 0xA0C2, 0xC856,	0xA0C3, 0xC857, 0xA0C4, 0xC858, 0xA0C5, 0xC859, 0xA0C6, 0xC85A,
+	0xA0C7, 0xC85B, 0xA0C8, 0xC85C, 0xA0C9, 0xC85D, 0xA0CA, 0xC85E,	0xA0CB, 0xC85F, 0xA0CC, 0xC860, 0xA0CD, 0xC861, 0xA0CE, 0xC862,
+	0xA0CF, 0xC863, 0xA0D0, 0xC864, 0xA0D1, 0xC865, 0xA0D2, 0xC866,	0xA0D3, 0xC867, 0xA0D4, 0xC868, 0xA0D5, 0xC869, 0xA0D6, 0xC86A,
+	0xA0D7, 0xC86B, 0xA0D8, 0xC86C, 0xA0D9, 0xC86D, 0xA0DA, 0xC86E,	0xA0DB, 0xC86F, 0xA0DC, 0xC872, 0xA0DD, 0xC873, 0xA0DE, 0xC875,
+	0xA0DF, 0xC876, 0xA0E0, 0xC877, 0xA0E1, 0xC879, 0xA0E2, 0xC87B,	0xA0E3, 0xC87C, 0xA0E4, 0xC87D, 0xA0E5, 0xC87E, 0xA0E6, 0xC87F,
+	0xA0E7, 0xC882, 0xA0E8, 0xC884, 0xA0E9, 0xC888, 0xA0EA, 0xC889,	0xA0EB, 0xC88A, 0xA0EC, 0xC88E, 0xA0ED, 0xC88F, 0xA0EE, 0xC890,
+	0xA0EF, 0xC891, 0xA0F0, 0xC892, 0xA0F1, 0xC893, 0xA0F2, 0xC895,	0xA0F3, 0xC896, 0xA0F4, 0xC897, 0xA0F5, 0xC898, 0xA0F6, 0xC899,
+	0xA0F7, 0xC89A, 0xA0F8, 0xC89B, 0xA0F9, 0xC89C, 0xA0FA, 0xC89E,	0xA0FB, 0xC8A0, 0xA0FC, 0xC8A2, 0xA0FD, 0xC8A3, 0xA0FE, 0xC8A4,
+	0xA141, 0xC8A5, 0xA142, 0xC8A6, 0xA143, 0xC8A7, 0xA144, 0xC8A9,	0xA145, 0xC8AA, 0xA146, 0xC8AB, 0xA147, 0xC8AC, 0xA148, 0xC8AD,
+	0xA149, 0xC8AE, 0xA14A, 0xC8AF, 0xA14B, 0xC8B0, 0xA14C, 0xC8B1,	0xA14D, 0xC8B2, 0xA14E, 0xC8B3, 0xA14F, 0xC8B4, 0xA150, 0xC8B5,
+	0xA151, 0xC8B6, 0xA152, 0xC8B7, 0xA153, 0xC8B8, 0xA154, 0xC8B9,	0xA155, 0xC8BA, 0xA156, 0xC8BB, 0xA157, 0xC8BE, 0xA158, 0xC8BF,
+	0xA159, 0xC8C0, 0xA15A, 0xC8C1, 0xA161, 0xC8C2, 0xA162, 0xC8C3,	0xA163, 0xC8C5, 0xA164, 0xC8C6, 0xA165, 0xC8C7, 0xA166, 0xC8C9,
+	0xA167, 0xC8CA, 0xA168, 0xC8CB, 0xA169, 0xC8CD, 0xA16A, 0xC8CE,	0xA16B, 0xC8CF, 0xA16C, 0xC8D0, 0xA16D, 0xC8D1, 0xA16E, 0xC8D2,
+	0xA16F, 0xC8D3, 0xA170, 0xC8D6, 0xA171, 0xC8D8, 0xA172, 0xC8DA,	0xA173, 0xC8DB, 0xA174, 0xC8DC, 0xA175, 0xC8DD, 0xA176, 0xC8DE,
+	0xA177, 0xC8DF, 0xA178, 0xC8E2, 0xA179, 0xC8E3, 0xA17A, 0xC8E5,	0xA181, 0xC8E6, 0xA182, 0xC8E7, 0xA183, 0xC8E8, 0xA184, 0xC8E9,
+	0xA185, 0xC8EA, 0xA186, 0xC8EB, 0xA187, 0xC8EC, 0xA188, 0xC8ED,	0xA189, 0xC8EE, 0xA18A, 0xC8EF, 0xA18B, 0xC8F0, 0xA18C, 0xC8F1,
+	0xA18D, 0xC8F2, 0xA18E, 0xC8F3, 0xA18F, 0xC8F4, 0xA190, 0xC8F6,	0xA191, 0xC8F7, 0xA192, 0xC8F8, 0xA193, 0xC8F9, 0xA194, 0xC8FA,
+	0xA195, 0xC8FB, 0xA196, 0xC8FE, 0xA197, 0xC8FF, 0xA198, 0xC901,	0xA199, 0xC902, 0xA19A, 0xC903, 0xA19B, 0xC907, 0xA19C, 0xC908,
+	0xA19D, 0xC909, 0xA19E, 0xC90A, 0xA19F, 0xC90B, 0xA1A0, 0xC90E,	0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002, 0xA1A4, 0x00B7,
+	0xA1A5, 0x2025, 0xA1A6, 0x2026, 0xA1A7, 0x00A8, 0xA1A8, 0x3003,	0xA1A9, 0x00AD, 0xA1AA, 0x2015, 0xA1AB, 0x2225, 0xA1AC, 0xFF3C,
+	0xA1AD, 0x223C, 0xA1AE, 0x2018, 0xA1AF, 0x2019, 0xA1B0, 0x201C,	0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, 0xA1B4, 0x3008,
+	0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B, 0xA1B8, 0x300C,	0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, 0xA1BC, 0x3010,
+	0xA1BD, 0x3011, 0xA1BE, 0x00B1, 0xA1BF, 0x00D7, 0xA1C0, 0x00F7,	0xA1C1, 0x2260, 0xA1C2, 0x2264, 0xA1C3, 0x2265, 0xA1C4, 0x221E,
+	0xA1C5, 0x2234, 0xA1C6, 0x00B0, 0xA1C7, 0x2032, 0xA1C8, 0x2033,	0xA1C9, 0x2103, 0xA1CA, 0x212B, 0xA1CB, 0xFFE0, 0xA1CC, 0xFFE1,
+	0xA1CD, 0xFFE5, 0xA1CE, 0x2642, 0xA1CF, 0x2640, 0xA1D0, 0x2220,	0xA1D1, 0x22A5, 0xA1D2, 0x2312, 0xA1D3, 0x2202, 0xA1D4, 0x2207,
+	0xA1D5, 0x2261, 0xA1D6, 0x2252, 0xA1D7, 0x00A7, 0xA1D8, 0x203B,	0xA1D9, 0x2606, 0xA1DA, 0x2605, 0xA1DB, 0x25CB, 0xA1DC, 0x25CF,
+	0xA1DD, 0x25CE, 0xA1DE, 0x25C7, 0xA1DF, 0x25C6, 0xA1E0, 0x25A1,	0xA1E1, 0x25A0, 0xA1E2, 0x25B3, 0xA1E3, 0x25B2, 0xA1E4, 0x25BD,
+	0xA1E5, 0x25BC, 0xA1E6, 0x2192, 0xA1E7, 0x2190, 0xA1E8, 0x2191,	0xA1E9, 0x2193, 0xA1EA, 0x2194, 0xA1EB, 0x3013, 0xA1EC, 0x226A,
+	0xA1ED, 0x226B, 0xA1EE, 0x221A, 0xA1EF, 0x223D, 0xA1F0, 0x221D,	0xA1F1, 0x2235, 0xA1F2, 0x222B, 0xA1F3, 0x222C, 0xA1F4, 0x2208,
+	0xA1F5, 0x220B, 0xA1F6, 0x2286, 0xA1F7, 0x2287, 0xA1F8, 0x2282,	0xA1F9, 0x2283, 0xA1FA, 0x222A, 0xA1FB, 0x2229, 0xA1FC, 0x2227,
+	0xA1FD, 0x2228, 0xA1FE, 0xFFE2, 0xA241, 0xC910, 0xA242, 0xC912,	0xA243, 0xC913, 0xA244, 0xC914, 0xA245, 0xC915, 0xA246, 0xC916,
+	0xA247, 0xC917, 0xA248, 0xC919, 0xA249, 0xC91A, 0xA24A, 0xC91B,	0xA24B, 0xC91C, 0xA24C, 0xC91D, 0xA24D, 0xC91E, 0xA24E, 0xC91F,
+	0xA24F, 0xC920, 0xA250, 0xC921, 0xA251, 0xC922, 0xA252, 0xC923,	0xA253, 0xC924, 0xA254, 0xC925, 0xA255, 0xC926, 0xA256, 0xC927,
+	0xA257, 0xC928, 0xA258, 0xC929, 0xA259, 0xC92A, 0xA25A, 0xC92B,	0xA261, 0xC92D, 0xA262, 0xC92E, 0xA263, 0xC92F, 0xA264, 0xC930,
+	0xA265, 0xC931, 0xA266, 0xC932, 0xA267, 0xC933, 0xA268, 0xC935,	0xA269, 0xC936, 0xA26A, 0xC937, 0xA26B, 0xC938, 0xA26C, 0xC939,
+	0xA26D, 0xC93A, 0xA26E, 0xC93B, 0xA26F, 0xC93C, 0xA270, 0xC93D,	0xA271, 0xC93E, 0xA272, 0xC93F, 0xA273, 0xC940, 0xA274, 0xC941,
+	0xA275, 0xC942, 0xA276, 0xC943, 0xA277, 0xC944, 0xA278, 0xC945,	0xA279, 0xC946, 0xA27A, 0xC947, 0xA281, 0xC948, 0xA282, 0xC949,
+	0xA283, 0xC94A, 0xA284, 0xC94B, 0xA285, 0xC94C, 0xA286, 0xC94D,	0xA287, 0xC94E, 0xA288, 0xC94F, 0xA289, 0xC952, 0xA28A, 0xC953,
+	0xA28B, 0xC955, 0xA28C, 0xC956, 0xA28D, 0xC957, 0xA28E, 0xC959,	0xA28F, 0xC95A, 0xA290, 0xC95B, 0xA291, 0xC95C, 0xA292, 0xC95D,
+	0xA293, 0xC95E, 0xA294, 0xC95F, 0xA295, 0xC962, 0xA296, 0xC964,	0xA297, 0xC965, 0xA298, 0xC966, 0xA299, 0xC967, 0xA29A, 0xC968,
+	0xA29B, 0xC969, 0xA29C, 0xC96A, 0xA29D, 0xC96B, 0xA29E, 0xC96D,	0xA29F, 0xC96E, 0xA2A0, 0xC96F, 0xA2A1, 0x21D2, 0xA2A2, 0x21D4,
+	0xA2A3, 0x2200, 0xA2A4, 0x2203, 0xA2A5, 0x00B4, 0xA2A6, 0xFF5E,	0xA2A7, 0x02C7, 0xA2A8, 0x02D8, 0xA2A9, 0x02DD, 0xA2AA, 0x02DA,
+	0xA2AB, 0x02D9, 0xA2AC, 0x00B8, 0xA2AD, 0x02DB, 0xA2AE, 0x00A1,	0xA2AF, 0x00BF, 0xA2B0, 0x02D0, 0xA2B1, 0x222E, 0xA2B2, 0x2211,
+	0xA2B3, 0x220F, 0xA2B4, 0x00A4, 0xA2B5, 0x2109, 0xA2B6, 0x2030,	0xA2B7, 0x25C1, 0xA2B8, 0x25C0, 0xA2B9, 0x25B7, 0xA2BA, 0x25B6,
+	0xA2BB, 0x2664, 0xA2BC, 0x2660, 0xA2BD, 0x2661, 0xA2BE, 0x2665,	0xA2BF, 0x2667, 0xA2C0, 0x2663, 0xA2C1, 0x2299, 0xA2C2, 0x25C8,
+	0xA2C3, 0x25A3, 0xA2C4, 0x25D0, 0xA2C5, 0x25D1, 0xA2C6, 0x2592,	0xA2C7, 0x25A4, 0xA2C8, 0x25A5, 0xA2C9, 0x25A8, 0xA2CA, 0x25A7,
+	0xA2CB, 0x25A6, 0xA2CC, 0x25A9, 0xA2CD, 0x2668, 0xA2CE, 0x260F,	0xA2CF, 0x260E, 0xA2D0, 0x261C, 0xA2D1, 0x261E, 0xA2D2, 0x00B6,
+	0xA2D3, 0x2020, 0xA2D4, 0x2021, 0xA2D5, 0x2195, 0xA2D6, 0x2197,	0xA2D7, 0x2199, 0xA2D8, 0x2196, 0xA2D9, 0x2198, 0xA2DA, 0x266D,
+	0xA2DB, 0x2669, 0xA2DC, 0x266A, 0xA2DD, 0x266C, 0xA2DE, 0x327F,	0xA2DF, 0x321C, 0xA2E0, 0x2116, 0xA2E1, 0x33C7, 0xA2E2, 0x2122,
+	0xA2E3, 0x33C2, 0xA2E4, 0x33D8, 0xA2E5, 0x2121, 0xA2E6, 0x20AC,	0xA2E7, 0x00AE, 0xA341, 0xC971, 0xA342, 0xC972, 0xA343, 0xC973,
+	0xA344, 0xC975, 0xA345, 0xC976, 0xA346, 0xC977, 0xA347, 0xC978,	0xA348, 0xC979, 0xA349, 0xC97A, 0xA34A, 0xC97B, 0xA34B, 0xC97D,
+	0xA34C, 0xC97E, 0xA34D, 0xC97F, 0xA34E, 0xC980, 0xA34F, 0xC981,	0xA350, 0xC982, 0xA351, 0xC983, 0xA352, 0xC984, 0xA353, 0xC985,
+	0xA354, 0xC986, 0xA355, 0xC987, 0xA356, 0xC98A, 0xA357, 0xC98B,	0xA358, 0xC98D, 0xA359, 0xC98E, 0xA35A, 0xC98F, 0xA361, 0xC991,
+	0xA362, 0xC992, 0xA363, 0xC993, 0xA364, 0xC994, 0xA365, 0xC995,	0xA366, 0xC996, 0xA367, 0xC997, 0xA368, 0xC99A, 0xA369, 0xC99C,
+	0xA36A, 0xC99E, 0xA36B, 0xC99F, 0xA36C, 0xC9A0, 0xA36D, 0xC9A1,	0xA36E, 0xC9A2, 0xA36F, 0xC9A3, 0xA370, 0xC9A4, 0xA371, 0xC9A5,
+	0xA372, 0xC9A6, 0xA373, 0xC9A7, 0xA374, 0xC9A8, 0xA375, 0xC9A9,	0xA376, 0xC9AA, 0xA377, 0xC9AB, 0xA378, 0xC9AC, 0xA379, 0xC9AD,
+	0xA37A, 0xC9AE, 0xA381, 0xC9AF, 0xA382, 0xC9B0, 0xA383, 0xC9B1,	0xA384, 0xC9B2, 0xA385, 0xC9B3, 0xA386, 0xC9B4, 0xA387, 0xC9B5,
+	0xA388, 0xC9B6, 0xA389, 0xC9B7, 0xA38A, 0xC9B8, 0xA38B, 0xC9B9,	0xA38C, 0xC9BA, 0xA38D, 0xC9BB, 0xA38E, 0xC9BC, 0xA38F, 0xC9BD,
+	0xA390, 0xC9BE, 0xA391, 0xC9BF, 0xA392, 0xC9C2, 0xA393, 0xC9C3,	0xA394, 0xC9C5, 0xA395, 0xC9C6, 0xA396, 0xC9C9, 0xA397, 0xC9CB,
+	0xA398, 0xC9CC, 0xA399, 0xC9CD, 0xA39A, 0xC9CE, 0xA39B, 0xC9CF,	0xA39C, 0xC9D2, 0xA39D, 0xC9D4, 0xA39E, 0xC9D7, 0xA39F, 0xC9D8,
+	0xA3A0, 0xC9DB, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03,	0xA3A4, 0xFF04, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+	0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B,	0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+	0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13,	0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+	0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B,	0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+	0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23,	0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+	0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B,	0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+	0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33,	0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+	0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B,	0xA3DC, 0xFFE6, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+	0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43,	0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+	0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B,	0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+	0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53,	0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+	0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B,	0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA441, 0xC9DE,
+	0xA442, 0xC9DF, 0xA443, 0xC9E1, 0xA444, 0xC9E3, 0xA445, 0xC9E5,	0xA446, 0xC9E6, 0xA447, 0xC9E8, 0xA448, 0xC9E9, 0xA449, 0xC9EA,
+	0xA44A, 0xC9EB, 0xA44B, 0xC9EE, 0xA44C, 0xC9F2, 0xA44D, 0xC9F3,	0xA44E, 0xC9F4, 0xA44F, 0xC9F5, 0xA450, 0xC9F6, 0xA451, 0xC9F7,
+	0xA452, 0xC9FA, 0xA453, 0xC9FB, 0xA454, 0xC9FD, 0xA455, 0xC9FE,	0xA456, 0xC9FF, 0xA457, 0xCA01, 0xA458, 0xCA02, 0xA459, 0xCA03,
+	0xA45A, 0xCA04, 0xA461, 0xCA05, 0xA462, 0xCA06, 0xA463, 0xCA07,	0xA464, 0xCA0A, 0xA465, 0xCA0E, 0xA466, 0xCA0F, 0xA467, 0xCA10,
+	0xA468, 0xCA11, 0xA469, 0xCA12, 0xA46A, 0xCA13, 0xA46B, 0xCA15,	0xA46C, 0xCA16, 0xA46D, 0xCA17, 0xA46E, 0xCA19, 0xA46F, 0xCA1A,
+	0xA470, 0xCA1B, 0xA471, 0xCA1C, 0xA472, 0xCA1D, 0xA473, 0xCA1E,	0xA474, 0xCA1F, 0xA475, 0xCA20, 0xA476, 0xCA21, 0xA477, 0xCA22,
+	0xA478, 0xCA23, 0xA479, 0xCA24, 0xA47A, 0xCA25, 0xA481, 0xCA26,	0xA482, 0xCA27, 0xA483, 0xCA28, 0xA484, 0xCA2A, 0xA485, 0xCA2B,
+	0xA486, 0xCA2C, 0xA487, 0xCA2D, 0xA488, 0xCA2E, 0xA489, 0xCA2F,	0xA48A, 0xCA30, 0xA48B, 0xCA31, 0xA48C, 0xCA32, 0xA48D, 0xCA33,
+	0xA48E, 0xCA34, 0xA48F, 0xCA35, 0xA490, 0xCA36, 0xA491, 0xCA37,	0xA492, 0xCA38, 0xA493, 0xCA39, 0xA494, 0xCA3A, 0xA495, 0xCA3B,
+	0xA496, 0xCA3C, 0xA497, 0xCA3D, 0xA498, 0xCA3E, 0xA499, 0xCA3F,	0xA49A, 0xCA40, 0xA49B, 0xCA41, 0xA49C, 0xCA42, 0xA49D, 0xCA43,
+	0xA49E, 0xCA44, 0xA49F, 0xCA45, 0xA4A0, 0xCA46, 0xA4A1, 0x3131,	0xA4A2, 0x3132, 0xA4A3, 0x3133, 0xA4A4, 0x3134, 0xA4A5, 0x3135,
+	0xA4A6, 0x3136, 0xA4A7, 0x3137, 0xA4A8, 0x3138, 0xA4A9, 0x3139,	0xA4AA, 0x313A, 0xA4AB, 0x313B, 0xA4AC, 0x313C, 0xA4AD, 0x313D,
+	0xA4AE, 0x313E, 0xA4AF, 0x313F, 0xA4B0, 0x3140, 0xA4B1, 0x3141,	0xA4B2, 0x3142, 0xA4B3, 0x3143, 0xA4B4, 0x3144, 0xA4B5, 0x3145,
+	0xA4B6, 0x3146, 0xA4B7, 0x3147, 0xA4B8, 0x3148, 0xA4B9, 0x3149,	0xA4BA, 0x314A, 0xA4BB, 0x314B, 0xA4BC, 0x314C, 0xA4BD, 0x314D,
+	0xA4BE, 0x314E, 0xA4BF, 0x314F, 0xA4C0, 0x3150, 0xA4C1, 0x3151,	0xA4C2, 0x3152, 0xA4C3, 0x3153, 0xA4C4, 0x3154, 0xA4C5, 0x3155,
+	0xA4C6, 0x3156, 0xA4C7, 0x3157, 0xA4C8, 0x3158, 0xA4C9, 0x3159,	0xA4CA, 0x315A, 0xA4CB, 0x315B, 0xA4CC, 0x315C, 0xA4CD, 0x315D,
+	0xA4CE, 0x315E, 0xA4CF, 0x315F, 0xA4D0, 0x3160, 0xA4D1, 0x3161,	0xA4D2, 0x3162, 0xA4D3, 0x3163, 0xA4D4, 0x3164, 0xA4D5, 0x3165,
+	0xA4D6, 0x3166, 0xA4D7, 0x3167, 0xA4D8, 0x3168, 0xA4D9, 0x3169,	0xA4DA, 0x316A, 0xA4DB, 0x316B, 0xA4DC, 0x316C, 0xA4DD, 0x316D,
+	0xA4DE, 0x316E, 0xA4DF, 0x316F, 0xA4E0, 0x3170, 0xA4E1, 0x3171,	0xA4E2, 0x3172, 0xA4E3, 0x3173, 0xA4E4, 0x3174, 0xA4E5, 0x3175,
+	0xA4E6, 0x3176, 0xA4E7, 0x3177, 0xA4E8, 0x3178, 0xA4E9, 0x3179,	0xA4EA, 0x317A, 0xA4EB, 0x317B, 0xA4EC, 0x317C, 0xA4ED, 0x317D,
+	0xA4EE, 0x317E, 0xA4EF, 0x317F, 0xA4F0, 0x3180, 0xA4F1, 0x3181,	0xA4F2, 0x3182, 0xA4F3, 0x3183, 0xA4F4, 0x3184, 0xA4F5, 0x3185,
+	0xA4F6, 0x3186, 0xA4F7, 0x3187, 0xA4F8, 0x3188, 0xA4F9, 0x3189,	0xA4FA, 0x318A, 0xA4FB, 0x318B, 0xA4FC, 0x318C, 0xA4FD, 0x318D,
+	0xA4FE, 0x318E, 0xA541, 0xCA47, 0xA542, 0xCA48, 0xA543, 0xCA49,	0xA544, 0xCA4A, 0xA545, 0xCA4B, 0xA546, 0xCA4E, 0xA547, 0xCA4F,
+	0xA548, 0xCA51, 0xA549, 0xCA52, 0xA54A, 0xCA53, 0xA54B, 0xCA55,	0xA54C, 0xCA56, 0xA54D, 0xCA57, 0xA54E, 0xCA58, 0xA54F, 0xCA59,
+	0xA550, 0xCA5A, 0xA551, 0xCA5B, 0xA552, 0xCA5E, 0xA553, 0xCA62,	0xA554, 0xCA63, 0xA555, 0xCA64, 0xA556, 0xCA65, 0xA557, 0xCA66,
+	0xA558, 0xCA67, 0xA559, 0xCA69, 0xA55A, 0xCA6A, 0xA561, 0xCA6B,	0xA562, 0xCA6C, 0xA563, 0xCA6D, 0xA564, 0xCA6E, 0xA565, 0xCA6F,
+	0xA566, 0xCA70, 0xA567, 0xCA71, 0xA568, 0xCA72, 0xA569, 0xCA73,	0xA56A, 0xCA74, 0xA56B, 0xCA75, 0xA56C, 0xCA76, 0xA56D, 0xCA77,
+	0xA56E, 0xCA78, 0xA56F, 0xCA79, 0xA570, 0xCA7A, 0xA571, 0xCA7B,	0xA572, 0xCA7C, 0xA573, 0xCA7E, 0xA574, 0xCA7F, 0xA575, 0xCA80,
+	0xA576, 0xCA81, 0xA577, 0xCA82, 0xA578, 0xCA83, 0xA579, 0xCA85,	0xA57A, 0xCA86, 0xA581, 0xCA87, 0xA582, 0xCA88, 0xA583, 0xCA89,
+	0xA584, 0xCA8A, 0xA585, 0xCA8B, 0xA586, 0xCA8C, 0xA587, 0xCA8D,	0xA588, 0xCA8E, 0xA589, 0xCA8F, 0xA58A, 0xCA90, 0xA58B, 0xCA91,
+	0xA58C, 0xCA92, 0xA58D, 0xCA93, 0xA58E, 0xCA94, 0xA58F, 0xCA95,	0xA590, 0xCA96, 0xA591, 0xCA97, 0xA592, 0xCA99, 0xA593, 0xCA9A,
+	0xA594, 0xCA9B, 0xA595, 0xCA9C, 0xA596, 0xCA9D, 0xA597, 0xCA9E,	0xA598, 0xCA9F, 0xA599, 0xCAA0, 0xA59A, 0xCAA1, 0xA59B, 0xCAA2,
+	0xA59C, 0xCAA3, 0xA59D, 0xCAA4, 0xA59E, 0xCAA5, 0xA59F, 0xCAA6,	0xA5A0, 0xCAA7, 0xA5A1, 0x2170, 0xA5A2, 0x2171, 0xA5A3, 0x2172,
+	0xA5A4, 0x2173, 0xA5A5, 0x2174, 0xA5A6, 0x2175, 0xA5A7, 0x2176,	0xA5A8, 0x2177, 0xA5A9, 0x2178, 0xA5AA, 0x2179, 0xA5B0, 0x2160,
+	0xA5B1, 0x2161, 0xA5B2, 0x2162, 0xA5B3, 0x2163, 0xA5B4, 0x2164,	0xA5B5, 0x2165, 0xA5B6, 0x2166, 0xA5B7, 0x2167, 0xA5B8, 0x2168,
+	0xA5B9, 0x2169, 0xA5C1, 0x0391, 0xA5C2, 0x0392, 0xA5C3, 0x0393,	0xA5C4, 0x0394, 0xA5C5, 0x0395, 0xA5C6, 0x0396, 0xA5C7, 0x0397,
+	0xA5C8, 0x0398, 0xA5C9, 0x0399, 0xA5CA, 0x039A, 0xA5CB, 0x039B,	0xA5CC, 0x039C, 0xA5CD, 0x039D, 0xA5CE, 0x039E, 0xA5CF, 0x039F,
+	0xA5D0, 0x03A0, 0xA5D1, 0x03A1, 0xA5D2, 0x03A3, 0xA5D3, 0x03A4,	0xA5D4, 0x03A5, 0xA5D5, 0x03A6, 0xA5D6, 0x03A7, 0xA5D7, 0x03A8,
+	0xA5D8, 0x03A9, 0xA5E1, 0x03B1, 0xA5E2, 0x03B2, 0xA5E3, 0x03B3,	0xA5E4, 0x03B4, 0xA5E5, 0x03B5, 0xA5E6, 0x03B6, 0xA5E7, 0x03B7,
+	0xA5E8, 0x03B8, 0xA5E9, 0x03B9, 0xA5EA, 0x03BA, 0xA5EB, 0x03BB,	0xA5EC, 0x03BC, 0xA5ED, 0x03BD, 0xA5EE, 0x03BE, 0xA5EF, 0x03BF,
+	0xA5F0, 0x03C0, 0xA5F1, 0x03C1, 0xA5F2, 0x03C3, 0xA5F3, 0x03C4,	0xA5F4, 0x03C5, 0xA5F5, 0x03C6, 0xA5F6, 0x03C7, 0xA5F7, 0x03C8,
+	0xA5F8, 0x03C9, 0xA641, 0xCAA8, 0xA642, 0xCAA9, 0xA643, 0xCAAA,	0xA644, 0xCAAB, 0xA645, 0xCAAC, 0xA646, 0xCAAD, 0xA647, 0xCAAE,
+	0xA648, 0xCAAF, 0xA649, 0xCAB0, 0xA64A, 0xCAB1, 0xA64B, 0xCAB2,	0xA64C, 0xCAB3, 0xA64D, 0xCAB4, 0xA64E, 0xCAB5, 0xA64F, 0xCAB6,
+	0xA650, 0xCAB7, 0xA651, 0xCAB8, 0xA652, 0xCAB9, 0xA653, 0xCABA,	0xA654, 0xCABB, 0xA655, 0xCABE, 0xA656, 0xCABF, 0xA657, 0xCAC1,
+	0xA658, 0xCAC2, 0xA659, 0xCAC3, 0xA65A, 0xCAC5, 0xA661, 0xCAC6,	0xA662, 0xCAC7, 0xA663, 0xCAC8, 0xA664, 0xCAC9, 0xA665, 0xCACA,
+	0xA666, 0xCACB, 0xA667, 0xCACE, 0xA668, 0xCAD0, 0xA669, 0xCAD2,	0xA66A, 0xCAD4, 0xA66B, 0xCAD5, 0xA66C, 0xCAD6, 0xA66D, 0xCAD7,
+	0xA66E, 0xCADA, 0xA66F, 0xCADB, 0xA670, 0xCADC, 0xA671, 0xCADD,	0xA672, 0xCADE, 0xA673, 0xCADF, 0xA674, 0xCAE1, 0xA675, 0xCAE2,
+	0xA676, 0xCAE3, 0xA677, 0xCAE4, 0xA678, 0xCAE5, 0xA679, 0xCAE6,	0xA67A, 0xCAE7, 0xA681, 0xCAE8, 0xA682, 0xCAE9, 0xA683, 0xCAEA,
+	0xA684, 0xCAEB, 0xA685, 0xCAED, 0xA686, 0xCAEE, 0xA687, 0xCAEF,	0xA688, 0xCAF0, 0xA689, 0xCAF1, 0xA68A, 0xCAF2, 0xA68B, 0xCAF3,
+	0xA68C, 0xCAF5, 0xA68D, 0xCAF6, 0xA68E, 0xCAF7, 0xA68F, 0xCAF8,	0xA690, 0xCAF9, 0xA691, 0xCAFA, 0xA692, 0xCAFB, 0xA693, 0xCAFC,
+	0xA694, 0xCAFD, 0xA695, 0xCAFE, 0xA696, 0xCAFF, 0xA697, 0xCB00,	0xA698, 0xCB01, 0xA699, 0xCB02, 0xA69A, 0xCB03, 0xA69B, 0xCB04,
+	0xA69C, 0xCB05, 0xA69D, 0xCB06, 0xA69E, 0xCB07, 0xA69F, 0xCB09,	0xA6A0, 0xCB0A, 0xA6A1, 0x2500, 0xA6A2, 0x2502, 0xA6A3, 0x250C,
+	0xA6A4, 0x2510, 0xA6A5, 0x2518, 0xA6A6, 0x2514, 0xA6A7, 0x251C,	0xA6A8, 0x252C, 0xA6A9, 0x2524, 0xA6AA, 0x2534, 0xA6AB, 0x253C,
+	0xA6AC, 0x2501, 0xA6AD, 0x2503, 0xA6AE, 0x250F, 0xA6AF, 0x2513,	0xA6B0, 0x251B, 0xA6B1, 0x2517, 0xA6B2, 0x2523, 0xA6B3, 0x2533,
+	0xA6B4, 0x252B, 0xA6B5, 0x253B, 0xA6B6, 0x254B, 0xA6B7, 0x2520,	0xA6B8, 0x252F, 0xA6B9, 0x2528, 0xA6BA, 0x2537, 0xA6BB, 0x253F,
+	0xA6BC, 0x251D, 0xA6BD, 0x2530, 0xA6BE, 0x2525, 0xA6BF, 0x2538,	0xA6C0, 0x2542, 0xA6C1, 0x2512, 0xA6C2, 0x2511, 0xA6C3, 0x251A,
+	0xA6C4, 0x2519, 0xA6C5, 0x2516, 0xA6C6, 0x2515, 0xA6C7, 0x250E,	0xA6C8, 0x250D, 0xA6C9, 0x251E, 0xA6CA, 0x251F, 0xA6CB, 0x2521,
+	0xA6CC, 0x2522, 0xA6CD, 0x2526, 0xA6CE, 0x2527, 0xA6CF, 0x2529,	0xA6D0, 0x252A, 0xA6D1, 0x252D, 0xA6D2, 0x252E, 0xA6D3, 0x2531,
+	0xA6D4, 0x2532, 0xA6D5, 0x2535, 0xA6D6, 0x2536, 0xA6D7, 0x2539,	0xA6D8, 0x253A, 0xA6D9, 0x253D, 0xA6DA, 0x253E, 0xA6DB, 0x2540,
+	0xA6DC, 0x2541, 0xA6DD, 0x2543, 0xA6DE, 0x2544, 0xA6DF, 0x2545,	0xA6E0, 0x2546, 0xA6E1, 0x2547, 0xA6E2, 0x2548, 0xA6E3, 0x2549,
+	0xA6E4, 0x254A, 0xA741, 0xCB0B, 0xA742, 0xCB0C, 0xA743, 0xCB0D,	0xA744, 0xCB0E, 0xA745, 0xCB0F, 0xA746, 0xCB11, 0xA747, 0xCB12,
+	0xA748, 0xCB13, 0xA749, 0xCB15, 0xA74A, 0xCB16, 0xA74B, 0xCB17,	0xA74C, 0xCB19, 0xA74D, 0xCB1A, 0xA74E, 0xCB1B, 0xA74F, 0xCB1C,
+	0xA750, 0xCB1D, 0xA751, 0xCB1E, 0xA752, 0xCB1F, 0xA753, 0xCB22,	0xA754, 0xCB23, 0xA755, 0xCB24, 0xA756, 0xCB25, 0xA757, 0xCB26,
+	0xA758, 0xCB27, 0xA759, 0xCB28, 0xA75A, 0xCB29, 0xA761, 0xCB2A,	0xA762, 0xCB2B, 0xA763, 0xCB2C, 0xA764, 0xCB2D, 0xA765, 0xCB2E,
+	0xA766, 0xCB2F, 0xA767, 0xCB30, 0xA768, 0xCB31, 0xA769, 0xCB32,	0xA76A, 0xCB33, 0xA76B, 0xCB34, 0xA76C, 0xCB35, 0xA76D, 0xCB36,
+	0xA76E, 0xCB37, 0xA76F, 0xCB38, 0xA770, 0xCB39, 0xA771, 0xCB3A,	0xA772, 0xCB3B, 0xA773, 0xCB3C, 0xA774, 0xCB3D, 0xA775, 0xCB3E,
+	0xA776, 0xCB3F, 0xA777, 0xCB40, 0xA778, 0xCB42, 0xA779, 0xCB43,	0xA77A, 0xCB44, 0xA781, 0xCB45, 0xA782, 0xCB46, 0xA783, 0xCB47,
+	0xA784, 0xCB4A, 0xA785, 0xCB4B, 0xA786, 0xCB4D, 0xA787, 0xCB4E,	0xA788, 0xCB4F, 0xA789, 0xCB51, 0xA78A, 0xCB52, 0xA78B, 0xCB53,
+	0xA78C, 0xCB54, 0xA78D, 0xCB55, 0xA78E, 0xCB56, 0xA78F, 0xCB57,	0xA790, 0xCB5A, 0xA791, 0xCB5B, 0xA792, 0xCB5C, 0xA793, 0xCB5E,
+	0xA794, 0xCB5F, 0xA795, 0xCB60, 0xA796, 0xCB61, 0xA797, 0xCB62,	0xA798, 0xCB63, 0xA799, 0xCB65, 0xA79A, 0xCB66, 0xA79B, 0xCB67,
+	0xA79C, 0xCB68, 0xA79D, 0xCB69, 0xA79E, 0xCB6A, 0xA79F, 0xCB6B,	0xA7A0, 0xCB6C, 0xA7A1, 0x3395, 0xA7A2, 0x3396, 0xA7A3, 0x3397,
+	0xA7A4, 0x2113, 0xA7A5, 0x3398, 0xA7A6, 0x33C4, 0xA7A7, 0x33A3,	0xA7A8, 0x33A4, 0xA7A9, 0x33A5, 0xA7AA, 0x33A6, 0xA7AB, 0x3399,
+	0xA7AC, 0x339A, 0xA7AD, 0x339B, 0xA7AE, 0x339C, 0xA7AF, 0x339D,	0xA7B0, 0x339E, 0xA7B1, 0x339F, 0xA7B2, 0x33A0, 0xA7B3, 0x33A1,
+	0xA7B4, 0x33A2, 0xA7B5, 0x33CA, 0xA7B6, 0x338D, 0xA7B7, 0x338E,	0xA7B8, 0x338F, 0xA7B9, 0x33CF, 0xA7BA, 0x3388, 0xA7BB, 0x3389,
+	0xA7BC, 0x33C8, 0xA7BD, 0x33A7, 0xA7BE, 0x33A8, 0xA7BF, 0x33B0,	0xA7C0, 0x33B1, 0xA7C1, 0x33B2, 0xA7C2, 0x33B3, 0xA7C3, 0x33B4,
+	0xA7C4, 0x33B5, 0xA7C5, 0x33B6, 0xA7C6, 0x33B7, 0xA7C7, 0x33B8,	0xA7C8, 0x33B9, 0xA7C9, 0x3380, 0xA7CA, 0x3381, 0xA7CB, 0x3382,
+	0xA7CC, 0x3383, 0xA7CD, 0x3384, 0xA7CE, 0x33BA, 0xA7CF, 0x33BB,	0xA7D0, 0x33BC, 0xA7D1, 0x33BD, 0xA7D2, 0x33BE, 0xA7D3, 0x33BF,
+	0xA7D4, 0x3390, 0xA7D5, 0x3391, 0xA7D6, 0x3392, 0xA7D7, 0x3393,	0xA7D8, 0x3394, 0xA7D9, 0x2126, 0xA7DA, 0x33C0, 0xA7DB, 0x33C1,
+	0xA7DC, 0x338A, 0xA7DD, 0x338B, 0xA7DE, 0x338C, 0xA7DF, 0x33D6,	0xA7E0, 0x33C5, 0xA7E1, 0x33AD, 0xA7E2, 0x33AE, 0xA7E3, 0x33AF,
+	0xA7E4, 0x33DB, 0xA7E5, 0x33A9, 0xA7E6, 0x33AA, 0xA7E7, 0x33AB,	0xA7E8, 0x33AC, 0xA7E9, 0x33DD, 0xA7EA, 0x33D0, 0xA7EB, 0x33D3,
+	0xA7EC, 0x33C3, 0xA7ED, 0x33C9, 0xA7EE, 0x33DC, 0xA7EF, 0x33C6,	0xA841, 0xCB6D, 0xA842, 0xCB6E, 0xA843, 0xCB6F, 0xA844, 0xCB70,
+	0xA845, 0xCB71, 0xA846, 0xCB72, 0xA847, 0xCB73, 0xA848, 0xCB74,	0xA849, 0xCB75, 0xA84A, 0xCB76, 0xA84B, 0xCB77, 0xA84C, 0xCB7A,
+	0xA84D, 0xCB7B, 0xA84E, 0xCB7C, 0xA84F, 0xCB7D, 0xA850, 0xCB7E,	0xA851, 0xCB7F, 0xA852, 0xCB80, 0xA853, 0xCB81, 0xA854, 0xCB82,
+	0xA855, 0xCB83, 0xA856, 0xCB84, 0xA857, 0xCB85, 0xA858, 0xCB86,	0xA859, 0xCB87, 0xA85A, 0xCB88, 0xA861, 0xCB89, 0xA862, 0xCB8A,
+	0xA863, 0xCB8B, 0xA864, 0xCB8C, 0xA865, 0xCB8D, 0xA866, 0xCB8E,	0xA867, 0xCB8F, 0xA868, 0xCB90, 0xA869, 0xCB91, 0xA86A, 0xCB92,
+	0xA86B, 0xCB93, 0xA86C, 0xCB94, 0xA86D, 0xCB95, 0xA86E, 0xCB96,	0xA86F, 0xCB97, 0xA870, 0xCB98, 0xA871, 0xCB99, 0xA872, 0xCB9A,
+	0xA873, 0xCB9B, 0xA874, 0xCB9D, 0xA875, 0xCB9E, 0xA876, 0xCB9F,	0xA877, 0xCBA0, 0xA878, 0xCBA1, 0xA879, 0xCBA2, 0xA87A, 0xCBA3,
+	0xA881, 0xCBA4, 0xA882, 0xCBA5, 0xA883, 0xCBA6, 0xA884, 0xCBA7,	0xA885, 0xCBA8, 0xA886, 0xCBA9, 0xA887, 0xCBAA, 0xA888, 0xCBAB,
+	0xA889, 0xCBAC, 0xA88A, 0xCBAD, 0xA88B, 0xCBAE, 0xA88C, 0xCBAF,	0xA88D, 0xCBB0, 0xA88E, 0xCBB1, 0xA88F, 0xCBB2, 0xA890, 0xCBB3,
+	0xA891, 0xCBB4, 0xA892, 0xCBB5, 0xA893, 0xCBB6, 0xA894, 0xCBB7,	0xA895, 0xCBB9, 0xA896, 0xCBBA, 0xA897, 0xCBBB, 0xA898, 0xCBBC,
+	0xA899, 0xCBBD, 0xA89A, 0xCBBE, 0xA89B, 0xCBBF, 0xA89C, 0xCBC0,	0xA89D, 0xCBC1, 0xA89E, 0xCBC2, 0xA89F, 0xCBC3, 0xA8A0, 0xCBC4,
+	0xA8A1, 0x00C6, 0xA8A2, 0x00D0, 0xA8A3, 0x00AA, 0xA8A4, 0x0126,	0xA8A6, 0x0132, 0xA8A8, 0x013F, 0xA8A9, 0x0141, 0xA8AA, 0x00D8,
+	0xA8AB, 0x0152, 0xA8AC, 0x00BA, 0xA8AD, 0x00DE, 0xA8AE, 0x0166,	0xA8AF, 0x014A, 0xA8B1, 0x3260, 0xA8B2, 0x3261, 0xA8B3, 0x3262,
+	0xA8B4, 0x3263, 0xA8B5, 0x3264, 0xA8B6, 0x3265, 0xA8B7, 0x3266,	0xA8B8, 0x3267, 0xA8B9, 0x3268, 0xA8BA, 0x3269, 0xA8BB, 0x326A,
+	0xA8BC, 0x326B, 0xA8BD, 0x326C, 0xA8BE, 0x326D, 0xA8BF, 0x326E,	0xA8C0, 0x326F, 0xA8C1, 0x3270, 0xA8C2, 0x3271, 0xA8C3, 0x3272,
+	0xA8C4, 0x3273, 0xA8C5, 0x3274, 0xA8C6, 0x3275, 0xA8C7, 0x3276,	0xA8C8, 0x3277, 0xA8C9, 0x3278, 0xA8CA, 0x3279, 0xA8CB, 0x327A,
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+	0xACDE, 0x043C, 0xACDF, 0x043D, 0xACE0, 0x043E, 0xACE1, 0x043F,	0xACE2, 0x0440, 0xACE3, 0x0441, 0xACE4, 0x0442, 0xACE5, 0x0443,
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+	0xACEE, 0x044C, 0xACEF, 0x044D, 0xACF0, 0x044E, 0xACF1, 0x044F,	0xAD41, 0xCD61, 0xAD42, 0xCD62, 0xAD43, 0xCD63, 0xAD44, 0xCD65,
+	0xAD45, 0xCD66, 0xAD46, 0xCD67, 0xAD47, 0xCD68, 0xAD48, 0xCD69,	0xAD49, 0xCD6A, 0xAD4A, 0xCD6B, 0xAD4B, 0xCD6E, 0xAD4C, 0xCD70,
+	0xAD4D, 0xCD72, 0xAD4E, 0xCD73, 0xAD4F, 0xCD74, 0xAD50, 0xCD75,	0xAD51, 0xCD76, 0xAD52, 0xCD77, 0xAD53, 0xCD79, 0xAD54, 0xCD7A,
+	0xAD55, 0xCD7B, 0xAD56, 0xCD7C, 0xAD57, 0xCD7D, 0xAD58, 0xCD7E,	0xAD59, 0xCD7F, 0xAD5A, 0xCD80, 0xAD61, 0xCD81, 0xAD62, 0xCD82,
+	0xAD63, 0xCD83, 0xAD64, 0xCD84, 0xAD65, 0xCD85, 0xAD66, 0xCD86,	0xAD67, 0xCD87, 0xAD68, 0xCD89, 0xAD69, 0xCD8A, 0xAD6A, 0xCD8B,
+	0xAD6B, 0xCD8C, 0xAD6C, 0xCD8D, 0xAD6D, 0xCD8E, 0xAD6E, 0xCD8F,	0xAD6F, 0xCD90, 0xAD70, 0xCD91, 0xAD71, 0xCD92, 0xAD72, 0xCD93,
+	0xAD73, 0xCD96, 0xAD74, 0xCD97, 0xAD75, 0xCD99, 0xAD76, 0xCD9A,	0xAD77, 0xCD9B, 0xAD78, 0xCD9D, 0xAD79, 0xCD9E, 0xAD7A, 0xCD9F,
+	0xAD81, 0xCDA0, 0xAD82, 0xCDA1, 0xAD83, 0xCDA2, 0xAD84, 0xCDA3,	0xAD85, 0xCDA6, 0xAD86, 0xCDA8, 0xAD87, 0xCDAA, 0xAD88, 0xCDAB,
+	0xAD89, 0xCDAC, 0xAD8A, 0xCDAD, 0xAD8B, 0xCDAE, 0xAD8C, 0xCDAF,	0xAD8D, 0xCDB1, 0xAD8E, 0xCDB2, 0xAD8F, 0xCDB3, 0xAD90, 0xCDB4,
+	0xAD91, 0xCDB5, 0xAD92, 0xCDB6, 0xAD93, 0xCDB7, 0xAD94, 0xCDB8,	0xAD95, 0xCDB9, 0xAD96, 0xCDBA, 0xAD97, 0xCDBB, 0xAD98, 0xCDBC,
+	0xAD99, 0xCDBD, 0xAD9A, 0xCDBE, 0xAD9B, 0xCDBF, 0xAD9C, 0xCDC0,	0xAD9D, 0xCDC1, 0xAD9E, 0xCDC2, 0xAD9F, 0xCDC3, 0xADA0, 0xCDC5,
+	0xAE41, 0xCDC6, 0xAE42, 0xCDC7, 0xAE43, 0xCDC8, 0xAE44, 0xCDC9,	0xAE45, 0xCDCA, 0xAE46, 0xCDCB, 0xAE47, 0xCDCD, 0xAE48, 0xCDCE,
+	0xAE49, 0xCDCF, 0xAE4A, 0xCDD1, 0xAE4B, 0xCDD2, 0xAE4C, 0xCDD3,	0xAE4D, 0xCDD4, 0xAE4E, 0xCDD5, 0xAE4F, 0xCDD6, 0xAE50, 0xCDD7,
+	0xAE51, 0xCDD8, 0xAE52, 0xCDD9, 0xAE53, 0xCDDA, 0xAE54, 0xCDDB,	0xAE55, 0xCDDC, 0xAE56, 0xCDDD, 0xAE57, 0xCDDE, 0xAE58, 0xCDDF,
+	0xAE59, 0xCDE0, 0xAE5A, 0xCDE1, 0xAE61, 0xCDE2, 0xAE62, 0xCDE3,	0xAE63, 0xCDE4, 0xAE64, 0xCDE5, 0xAE65, 0xCDE6, 0xAE66, 0xCDE7,
+	0xAE67, 0xCDE9, 0xAE68, 0xCDEA, 0xAE69, 0xCDEB, 0xAE6A, 0xCDED,	0xAE6B, 0xCDEE, 0xAE6C, 0xCDEF, 0xAE6D, 0xCDF1, 0xAE6E, 0xCDF2,
+	0xAE6F, 0xCDF3, 0xAE70, 0xCDF4, 0xAE71, 0xCDF5, 0xAE72, 0xCDF6,	0xAE73, 0xCDF7, 0xAE74, 0xCDFA, 0xAE75, 0xCDFC, 0xAE76, 0xCDFE,
+	0xAE77, 0xCDFF, 0xAE78, 0xCE00, 0xAE79, 0xCE01, 0xAE7A, 0xCE02,	0xAE81, 0xCE03, 0xAE82, 0xCE05, 0xAE83, 0xCE06, 0xAE84, 0xCE07,
+	0xAE85, 0xCE09, 0xAE86, 0xCE0A, 0xAE87, 0xCE0B, 0xAE88, 0xCE0D,	0xAE89, 0xCE0E, 0xAE8A, 0xCE0F, 0xAE8B, 0xCE10, 0xAE8C, 0xCE11,
+	0xAE8D, 0xCE12, 0xAE8E, 0xCE13, 0xAE8F, 0xCE15, 0xAE90, 0xCE16,	0xAE91, 0xCE17, 0xAE92, 0xCE18, 0xAE93, 0xCE1A, 0xAE94, 0xCE1B,
+	0xAE95, 0xCE1C, 0xAE96, 0xCE1D, 0xAE97, 0xCE1E, 0xAE98, 0xCE1F,	0xAE99, 0xCE22, 0xAE9A, 0xCE23, 0xAE9B, 0xCE25, 0xAE9C, 0xCE26,
+	0xAE9D, 0xCE27, 0xAE9E, 0xCE29, 0xAE9F, 0xCE2A, 0xAEA0, 0xCE2B,	0xAF41, 0xCE2C, 0xAF42, 0xCE2D, 0xAF43, 0xCE2E, 0xAF44, 0xCE2F,
+	0xAF45, 0xCE32, 0xAF46, 0xCE34, 0xAF47, 0xCE36, 0xAF48, 0xCE37,	0xAF49, 0xCE38, 0xAF4A, 0xCE39, 0xAF4B, 0xCE3A, 0xAF4C, 0xCE3B,
+	0xAF4D, 0xCE3C, 0xAF4E, 0xCE3D, 0xAF4F, 0xCE3E, 0xAF50, 0xCE3F,	0xAF51, 0xCE40, 0xAF52, 0xCE41, 0xAF53, 0xCE42, 0xAF54, 0xCE43,
+	0xAF55, 0xCE44, 0xAF56, 0xCE45, 0xAF57, 0xCE46, 0xAF58, 0xCE47,	0xAF59, 0xCE48, 0xAF5A, 0xCE49, 0xAF61, 0xCE4A, 0xAF62, 0xCE4B,
+	0xAF63, 0xCE4C, 0xAF64, 0xCE4D, 0xAF65, 0xCE4E, 0xAF66, 0xCE4F,	0xAF67, 0xCE50, 0xAF68, 0xCE51, 0xAF69, 0xCE52, 0xAF6A, 0xCE53,
+	0xAF6B, 0xCE54, 0xAF6C, 0xCE55, 0xAF6D, 0xCE56, 0xAF6E, 0xCE57,	0xAF6F, 0xCE5A, 0xAF70, 0xCE5B, 0xAF71, 0xCE5D, 0xAF72, 0xCE5E,
+	0xAF73, 0xCE62, 0xAF74, 0xCE63, 0xAF75, 0xCE64, 0xAF76, 0xCE65,	0xAF77, 0xCE66, 0xAF78, 0xCE67, 0xAF79, 0xCE6A, 0xAF7A, 0xCE6C,
+	0xAF81, 0xCE6E, 0xAF82, 0xCE6F, 0xAF83, 0xCE70, 0xAF84, 0xCE71,	0xAF85, 0xCE72, 0xAF86, 0xCE73, 0xAF87, 0xCE76, 0xAF88, 0xCE77,
+	0xAF89, 0xCE79, 0xAF8A, 0xCE7A, 0xAF8B, 0xCE7B, 0xAF8C, 0xCE7D,	0xAF8D, 0xCE7E, 0xAF8E, 0xCE7F, 0xAF8F, 0xCE80, 0xAF90, 0xCE81,
+	0xAF91, 0xCE82, 0xAF92, 0xCE83, 0xAF93, 0xCE86, 0xAF94, 0xCE88,	0xAF95, 0xCE8A, 0xAF96, 0xCE8B, 0xAF97, 0xCE8C, 0xAF98, 0xCE8D,
+	0xAF99, 0xCE8E, 0xAF9A, 0xCE8F, 0xAF9B, 0xCE92, 0xAF9C, 0xCE93,	0xAF9D, 0xCE95, 0xAF9E, 0xCE96, 0xAF9F, 0xCE97, 0xAFA0, 0xCE99,
+	0xB041, 0xCE9A, 0xB042, 0xCE9B, 0xB043, 0xCE9C, 0xB044, 0xCE9D,	0xB045, 0xCE9E, 0xB046, 0xCE9F, 0xB047, 0xCEA2, 0xB048, 0xCEA6,
+	0xB049, 0xCEA7, 0xB04A, 0xCEA8, 0xB04B, 0xCEA9, 0xB04C, 0xCEAA,	0xB04D, 0xCEAB, 0xB04E, 0xCEAE, 0xB04F, 0xCEAF, 0xB050, 0xCEB0,
+	0xB051, 0xCEB1, 0xB052, 0xCEB2, 0xB053, 0xCEB3, 0xB054, 0xCEB4,	0xB055, 0xCEB5, 0xB056, 0xCEB6, 0xB057, 0xCEB7, 0xB058, 0xCEB8,
+	0xB059, 0xCEB9, 0xB05A, 0xCEBA, 0xB061, 0xCEBB, 0xB062, 0xCEBC,	0xB063, 0xCEBD, 0xB064, 0xCEBE, 0xB065, 0xCEBF, 0xB066, 0xCEC0,
+	0xB067, 0xCEC2, 0xB068, 0xCEC3, 0xB069, 0xCEC4, 0xB06A, 0xCEC5,	0xB06B, 0xCEC6, 0xB06C, 0xCEC7, 0xB06D, 0xCEC8, 0xB06E, 0xCEC9,
+	0xB06F, 0xCECA, 0xB070, 0xCECB, 0xB071, 0xCECC, 0xB072, 0xCECD,	0xB073, 0xCECE, 0xB074, 0xCECF, 0xB075, 0xCED0, 0xB076, 0xCED1,
+	0xB077, 0xCED2, 0xB078, 0xCED3, 0xB079, 0xCED4, 0xB07A, 0xCED5,	0xB081, 0xCED6, 0xB082, 0xCED7, 0xB083, 0xCED8, 0xB084, 0xCED9,
+	0xB085, 0xCEDA, 0xB086, 0xCEDB, 0xB087, 0xCEDC, 0xB088, 0xCEDD,	0xB089, 0xCEDE, 0xB08A, 0xCEDF, 0xB08B, 0xCEE0, 0xB08C, 0xCEE1,
+	0xB08D, 0xCEE2, 0xB08E, 0xCEE3, 0xB08F, 0xCEE6, 0xB090, 0xCEE7,	0xB091, 0xCEE9, 0xB092, 0xCEEA, 0xB093, 0xCEED, 0xB094, 0xCEEE,
+	0xB095, 0xCEEF, 0xB096, 0xCEF0, 0xB097, 0xCEF1, 0xB098, 0xCEF2,	0xB099, 0xCEF3, 0xB09A, 0xCEF6, 0xB09B, 0xCEFA, 0xB09C, 0xCEFB,
+	0xB09D, 0xCEFC, 0xB09E, 0xCEFD, 0xB09F, 0xCEFE, 0xB0A0, 0xCEFF,	0xB0A1, 0xAC00, 0xB0A2, 0xAC01, 0xB0A3, 0xAC04, 0xB0A4, 0xAC07,
+	0xB0A5, 0xAC08, 0xB0A6, 0xAC09, 0xB0A7, 0xAC0A, 0xB0A8, 0xAC10,	0xB0A9, 0xAC11, 0xB0AA, 0xAC12, 0xB0AB, 0xAC13, 0xB0AC, 0xAC14,
+	0xB0AD, 0xAC15, 0xB0AE, 0xAC16, 0xB0AF, 0xAC17, 0xB0B0, 0xAC19,	0xB0B1, 0xAC1A, 0xB0B2, 0xAC1B, 0xB0B3, 0xAC1C, 0xB0B4, 0xAC1D,
+	0xB0B5, 0xAC20, 0xB0B6, 0xAC24, 0xB0B7, 0xAC2C, 0xB0B8, 0xAC2D,	0xB0B9, 0xAC2F, 0xB0BA, 0xAC30, 0xB0BB, 0xAC31, 0xB0BC, 0xAC38,
+	0xB0BD, 0xAC39, 0xB0BE, 0xAC3C, 0xB0BF, 0xAC40, 0xB0C0, 0xAC4B,	0xB0C1, 0xAC4D, 0xB0C2, 0xAC54, 0xB0C3, 0xAC58, 0xB0C4, 0xAC5C,
+	0xB0C5, 0xAC70, 0xB0C6, 0xAC71, 0xB0C7, 0xAC74, 0xB0C8, 0xAC77,	0xB0C9, 0xAC78, 0xB0CA, 0xAC7A, 0xB0CB, 0xAC80, 0xB0CC, 0xAC81,
+	0xB0CD, 0xAC83, 0xB0CE, 0xAC84, 0xB0CF, 0xAC85, 0xB0D0, 0xAC86,	0xB0D1, 0xAC89, 0xB0D2, 0xAC8A, 0xB0D3, 0xAC8B, 0xB0D4, 0xAC8C,
+	0xB0D5, 0xAC90, 0xB0D6, 0xAC94, 0xB0D7, 0xAC9C, 0xB0D8, 0xAC9D,	0xB0D9, 0xAC9F, 0xB0DA, 0xACA0, 0xB0DB, 0xACA1, 0xB0DC, 0xACA8,
+	0xB0DD, 0xACA9, 0xB0DE, 0xACAA, 0xB0DF, 0xACAC, 0xB0E0, 0xACAF,	0xB0E1, 0xACB0, 0xB0E2, 0xACB8, 0xB0E3, 0xACB9, 0xB0E4, 0xACBB,
+	0xB0E5, 0xACBC, 0xB0E6, 0xACBD, 0xB0E7, 0xACC1, 0xB0E8, 0xACC4,	0xB0E9, 0xACC8, 0xB0EA, 0xACCC, 0xB0EB, 0xACD5, 0xB0EC, 0xACD7,
+	0xB0ED, 0xACE0, 0xB0EE, 0xACE1, 0xB0EF, 0xACE4, 0xB0F0, 0xACE7,	0xB0F1, 0xACE8, 0xB0F2, 0xACEA, 0xB0F3, 0xACEC, 0xB0F4, 0xACEF,
+	0xB0F5, 0xACF0, 0xB0F6, 0xACF1, 0xB0F7, 0xACF3, 0xB0F8, 0xACF5,	0xB0F9, 0xACF6, 0xB0FA, 0xACFC, 0xB0FB, 0xACFD, 0xB0FC, 0xAD00,
+	0xB0FD, 0xAD04, 0xB0FE, 0xAD06, 0xB141, 0xCF02, 0xB142, 0xCF03,	0xB143, 0xCF05, 0xB144, 0xCF06, 0xB145, 0xCF07, 0xB146, 0xCF09,
+	0xB147, 0xCF0A, 0xB148, 0xCF0B, 0xB149, 0xCF0C, 0xB14A, 0xCF0D,	0xB14B, 0xCF0E, 0xB14C, 0xCF0F, 0xB14D, 0xCF12, 0xB14E, 0xCF14,
+	0xB14F, 0xCF16, 0xB150, 0xCF17, 0xB151, 0xCF18, 0xB152, 0xCF19,	0xB153, 0xCF1A, 0xB154, 0xCF1B, 0xB155, 0xCF1D, 0xB156, 0xCF1E,
+	0xB157, 0xCF1F, 0xB158, 0xCF21, 0xB159, 0xCF22, 0xB15A, 0xCF23,	0xB161, 0xCF25, 0xB162, 0xCF26, 0xB163, 0xCF27, 0xB164, 0xCF28,
+	0xB165, 0xCF29, 0xB166, 0xCF2A, 0xB167, 0xCF2B, 0xB168, 0xCF2E,	0xB169, 0xCF32, 0xB16A, 0xCF33, 0xB16B, 0xCF34, 0xB16C, 0xCF35,
+	0xB16D, 0xCF36, 0xB16E, 0xCF37, 0xB16F, 0xCF39, 0xB170, 0xCF3A,	0xB171, 0xCF3B, 0xB172, 0xCF3C, 0xB173, 0xCF3D, 0xB174, 0xCF3E,
+	0xB175, 0xCF3F, 0xB176, 0xCF40, 0xB177, 0xCF41, 0xB178, 0xCF42,	0xB179, 0xCF43, 0xB17A, 0xCF44, 0xB181, 0xCF45, 0xB182, 0xCF46,
+	0xB183, 0xCF47, 0xB184, 0xCF48, 0xB185, 0xCF49, 0xB186, 0xCF4A,	0xB187, 0xCF4B, 0xB188, 0xCF4C, 0xB189, 0xCF4D, 0xB18A, 0xCF4E,
+	0xB18B, 0xCF4F, 0xB18C, 0xCF50, 0xB18D, 0xCF51, 0xB18E, 0xCF52,	0xB18F, 0xCF53, 0xB190, 0xCF56, 0xB191, 0xCF57, 0xB192, 0xCF59,
+	0xB193, 0xCF5A, 0xB194, 0xCF5B, 0xB195, 0xCF5D, 0xB196, 0xCF5E,	0xB197, 0xCF5F, 0xB198, 0xCF60, 0xB199, 0xCF61, 0xB19A, 0xCF62,
+	0xB19B, 0xCF63, 0xB19C, 0xCF66, 0xB19D, 0xCF68, 0xB19E, 0xCF6A,	0xB19F, 0xCF6B, 0xB1A0, 0xCF6C, 0xB1A1, 0xAD0C, 0xB1A2, 0xAD0D,
+	0xB1A3, 0xAD0F, 0xB1A4, 0xAD11, 0xB1A5, 0xAD18, 0xB1A6, 0xAD1C,	0xB1A7, 0xAD20, 0xB1A8, 0xAD29, 0xB1A9, 0xAD2C, 0xB1AA, 0xAD2D,
+	0xB1AB, 0xAD34, 0xB1AC, 0xAD35, 0xB1AD, 0xAD38, 0xB1AE, 0xAD3C,	0xB1AF, 0xAD44, 0xB1B0, 0xAD45, 0xB1B1, 0xAD47, 0xB1B2, 0xAD49,
+	0xB1B3, 0xAD50, 0xB1B4, 0xAD54, 0xB1B5, 0xAD58, 0xB1B6, 0xAD61,	0xB1B7, 0xAD63, 0xB1B8, 0xAD6C, 0xB1B9, 0xAD6D, 0xB1BA, 0xAD70,
+	0xB1BB, 0xAD73, 0xB1BC, 0xAD74, 0xB1BD, 0xAD75, 0xB1BE, 0xAD76,	0xB1BF, 0xAD7B, 0xB1C0, 0xAD7C, 0xB1C1, 0xAD7D, 0xB1C2, 0xAD7F,
+	0xB1C3, 0xAD81, 0xB1C4, 0xAD82, 0xB1C5, 0xAD88, 0xB1C6, 0xAD89,	0xB1C7, 0xAD8C, 0xB1C8, 0xAD90, 0xB1C9, 0xAD9C, 0xB1CA, 0xAD9D,
+	0xB1CB, 0xADA4, 0xB1CC, 0xADB7, 0xB1CD, 0xADC0, 0xB1CE, 0xADC1,	0xB1CF, 0xADC4, 0xB1D0, 0xADC8, 0xB1D1, 0xADD0, 0xB1D2, 0xADD1,
+	0xB1D3, 0xADD3, 0xB1D4, 0xADDC, 0xB1D5, 0xADE0, 0xB1D6, 0xADE4,	0xB1D7, 0xADF8, 0xB1D8, 0xADF9, 0xB1D9, 0xADFC, 0xB1DA, 0xADFF,
+	0xB1DB, 0xAE00, 0xB1DC, 0xAE01, 0xB1DD, 0xAE08, 0xB1DE, 0xAE09,	0xB1DF, 0xAE0B, 0xB1E0, 0xAE0D, 0xB1E1, 0xAE14, 0xB1E2, 0xAE30,
+	0xB1E3, 0xAE31, 0xB1E4, 0xAE34, 0xB1E5, 0xAE37, 0xB1E6, 0xAE38,	0xB1E7, 0xAE3A, 0xB1E8, 0xAE40, 0xB1E9, 0xAE41, 0xB1EA, 0xAE43,
+	0xB1EB, 0xAE45, 0xB1EC, 0xAE46, 0xB1ED, 0xAE4A, 0xB1EE, 0xAE4C,	0xB1EF, 0xAE4D, 0xB1F0, 0xAE4E, 0xB1F1, 0xAE50, 0xB1F2, 0xAE54,
+	0xB1F3, 0xAE56, 0xB1F4, 0xAE5C, 0xB1F5, 0xAE5D, 0xB1F6, 0xAE5F,	0xB1F7, 0xAE60, 0xB1F8, 0xAE61, 0xB1F9, 0xAE65, 0xB1FA, 0xAE68,
+	0xB1FB, 0xAE69, 0xB1FC, 0xAE6C, 0xB1FD, 0xAE70, 0xB1FE, 0xAE78,	0xB241, 0xCF6D, 0xB242, 0xCF6E, 0xB243, 0xCF6F, 0xB244, 0xCF72,
+	0xB245, 0xCF73, 0xB246, 0xCF75, 0xB247, 0xCF76, 0xB248, 0xCF77,	0xB249, 0xCF79, 0xB24A, 0xCF7A, 0xB24B, 0xCF7B, 0xB24C, 0xCF7C,
+	0xB24D, 0xCF7D, 0xB24E, 0xCF7E, 0xB24F, 0xCF7F, 0xB250, 0xCF81,	0xB251, 0xCF82, 0xB252, 0xCF83, 0xB253, 0xCF84, 0xB254, 0xCF86,
+	0xB255, 0xCF87, 0xB256, 0xCF88, 0xB257, 0xCF89, 0xB258, 0xCF8A,	0xB259, 0xCF8B, 0xB25A, 0xCF8D, 0xB261, 0xCF8E, 0xB262, 0xCF8F,
+	0xB263, 0xCF90, 0xB264, 0xCF91, 0xB265, 0xCF92, 0xB266, 0xCF93,	0xB267, 0xCF94, 0xB268, 0xCF95, 0xB269, 0xCF96, 0xB26A, 0xCF97,
+	0xB26B, 0xCF98, 0xB26C, 0xCF99, 0xB26D, 0xCF9A, 0xB26E, 0xCF9B,	0xB26F, 0xCF9C, 0xB270, 0xCF9D, 0xB271, 0xCF9E, 0xB272, 0xCF9F,
+	0xB273, 0xCFA0, 0xB274, 0xCFA2, 0xB275, 0xCFA3, 0xB276, 0xCFA4,	0xB277, 0xCFA5, 0xB278, 0xCFA6, 0xB279, 0xCFA7, 0xB27A, 0xCFA9,
+	0xB281, 0xCFAA, 0xB282, 0xCFAB, 0xB283, 0xCFAC, 0xB284, 0xCFAD,	0xB285, 0xCFAE, 0xB286, 0xCFAF, 0xB287, 0xCFB1, 0xB288, 0xCFB2,
+	0xB289, 0xCFB3, 0xB28A, 0xCFB4, 0xB28B, 0xCFB5, 0xB28C, 0xCFB6,	0xB28D, 0xCFB7, 0xB28E, 0xCFB8, 0xB28F, 0xCFB9, 0xB290, 0xCFBA,
+	0xB291, 0xCFBB, 0xB292, 0xCFBC, 0xB293, 0xCFBD, 0xB294, 0xCFBE,	0xB295, 0xCFBF, 0xB296, 0xCFC0, 0xB297, 0xCFC1, 0xB298, 0xCFC2,
+	0xB299, 0xCFC3, 0xB29A, 0xCFC5, 0xB29B, 0xCFC6, 0xB29C, 0xCFC7,	0xB29D, 0xCFC8, 0xB29E, 0xCFC9, 0xB29F, 0xCFCA, 0xB2A0, 0xCFCB,
+	0xB2A1, 0xAE79, 0xB2A2, 0xAE7B, 0xB2A3, 0xAE7C, 0xB2A4, 0xAE7D,	0xB2A5, 0xAE84, 0xB2A6, 0xAE85, 0xB2A7, 0xAE8C, 0xB2A8, 0xAEBC,
+	0xB2A9, 0xAEBD, 0xB2AA, 0xAEBE, 0xB2AB, 0xAEC0, 0xB2AC, 0xAEC4,	0xB2AD, 0xAECC, 0xB2AE, 0xAECD, 0xB2AF, 0xAECF, 0xB2B0, 0xAED0,
+	0xB2B1, 0xAED1, 0xB2B2, 0xAED8, 0xB2B3, 0xAED9, 0xB2B4, 0xAEDC,	0xB2B5, 0xAEE8, 0xB2B6, 0xAEEB, 0xB2B7, 0xAEED, 0xB2B8, 0xAEF4,
+	0xB2B9, 0xAEF8, 0xB2BA, 0xAEFC, 0xB2BB, 0xAF07, 0xB2BC, 0xAF08,	0xB2BD, 0xAF0D, 0xB2BE, 0xAF10, 0xB2BF, 0xAF2C, 0xB2C0, 0xAF2D,
+	0xB2C1, 0xAF30, 0xB2C2, 0xAF32, 0xB2C3, 0xAF34, 0xB2C4, 0xAF3C,	0xB2C5, 0xAF3D, 0xB2C6, 0xAF3F, 0xB2C7, 0xAF41, 0xB2C8, 0xAF42,
+	0xB2C9, 0xAF43, 0xB2CA, 0xAF48, 0xB2CB, 0xAF49, 0xB2CC, 0xAF50,	0xB2CD, 0xAF5C, 0xB2CE, 0xAF5D, 0xB2CF, 0xAF64, 0xB2D0, 0xAF65,
+	0xB2D1, 0xAF79, 0xB2D2, 0xAF80, 0xB2D3, 0xAF84, 0xB2D4, 0xAF88,	0xB2D5, 0xAF90, 0xB2D6, 0xAF91, 0xB2D7, 0xAF95, 0xB2D8, 0xAF9C,
+	0xB2D9, 0xAFB8, 0xB2DA, 0xAFB9, 0xB2DB, 0xAFBC, 0xB2DC, 0xAFC0,	0xB2DD, 0xAFC7, 0xB2DE, 0xAFC8, 0xB2DF, 0xAFC9, 0xB2E0, 0xAFCB,
+	0xB2E1, 0xAFCD, 0xB2E2, 0xAFCE, 0xB2E3, 0xAFD4, 0xB2E4, 0xAFDC,	0xB2E5, 0xAFE8, 0xB2E6, 0xAFE9, 0xB2E7, 0xAFF0, 0xB2E8, 0xAFF1,
+	0xB2E9, 0xAFF4, 0xB2EA, 0xAFF8, 0xB2EB, 0xB000, 0xB2EC, 0xB001,	0xB2ED, 0xB004, 0xB2EE, 0xB00C, 0xB2EF, 0xB010, 0xB2F0, 0xB014,
+	0xB2F1, 0xB01C, 0xB2F2, 0xB01D, 0xB2F3, 0xB028, 0xB2F4, 0xB044,	0xB2F5, 0xB045, 0xB2F6, 0xB048, 0xB2F7, 0xB04A, 0xB2F8, 0xB04C,
+	0xB2F9, 0xB04E, 0xB2FA, 0xB053, 0xB2FB, 0xB054, 0xB2FC, 0xB055,	0xB2FD, 0xB057, 0xB2FE, 0xB059, 0xB341, 0xCFCC, 0xB342, 0xCFCD,
+	0xB343, 0xCFCE, 0xB344, 0xCFCF, 0xB345, 0xCFD0, 0xB346, 0xCFD1,	0xB347, 0xCFD2, 0xB348, 0xCFD3, 0xB349, 0xCFD4, 0xB34A, 0xCFD5,
+	0xB34B, 0xCFD6, 0xB34C, 0xCFD7, 0xB34D, 0xCFD8, 0xB34E, 0xCFD9,	0xB34F, 0xCFDA, 0xB350, 0xCFDB, 0xB351, 0xCFDC, 0xB352, 0xCFDD,
+	0xB353, 0xCFDE, 0xB354, 0xCFDF, 0xB355, 0xCFE2, 0xB356, 0xCFE3,	0xB357, 0xCFE5, 0xB358, 0xCFE6, 0xB359, 0xCFE7, 0xB35A, 0xCFE9,
+	0xB361, 0xCFEA, 0xB362, 0xCFEB, 0xB363, 0xCFEC, 0xB364, 0xCFED,	0xB365, 0xCFEE, 0xB366, 0xCFEF, 0xB367, 0xCFF2, 0xB368, 0xCFF4,
+	0xB369, 0xCFF6, 0xB36A, 0xCFF7, 0xB36B, 0xCFF8, 0xB36C, 0xCFF9,	0xB36D, 0xCFFA, 0xB36E, 0xCFFB, 0xB36F, 0xCFFD, 0xB370, 0xCFFE,
+	0xB371, 0xCFFF, 0xB372, 0xD001, 0xB373, 0xD002, 0xB374, 0xD003,	0xB375, 0xD005, 0xB376, 0xD006, 0xB377, 0xD007, 0xB378, 0xD008,
+	0xB379, 0xD009, 0xB37A, 0xD00A, 0xB381, 0xD00B, 0xB382, 0xD00C,	0xB383, 0xD00D, 0xB384, 0xD00E, 0xB385, 0xD00F, 0xB386, 0xD010,
+	0xB387, 0xD012, 0xB388, 0xD013, 0xB389, 0xD014, 0xB38A, 0xD015,	0xB38B, 0xD016, 0xB38C, 0xD017, 0xB38D, 0xD019, 0xB38E, 0xD01A,
+	0xB38F, 0xD01B, 0xB390, 0xD01C, 0xB391, 0xD01D, 0xB392, 0xD01E,	0xB393, 0xD01F, 0xB394, 0xD020, 0xB395, 0xD021, 0xB396, 0xD022,
+	0xB397, 0xD023, 0xB398, 0xD024, 0xB399, 0xD025, 0xB39A, 0xD026,	0xB39B, 0xD027, 0xB39C, 0xD028, 0xB39D, 0xD029, 0xB39E, 0xD02A,
+	0xB39F, 0xD02B, 0xB3A0, 0xD02C, 0xB3A1, 0xB05D, 0xB3A2, 0xB07C,	0xB3A3, 0xB07D, 0xB3A4, 0xB080, 0xB3A5, 0xB084, 0xB3A6, 0xB08C,
+	0xB3A7, 0xB08D, 0xB3A8, 0xB08F, 0xB3A9, 0xB091, 0xB3AA, 0xB098,	0xB3AB, 0xB099, 0xB3AC, 0xB09A, 0xB3AD, 0xB09C, 0xB3AE, 0xB09F,
+	0xB3AF, 0xB0A0, 0xB3B0, 0xB0A1, 0xB3B1, 0xB0A2, 0xB3B2, 0xB0A8,	0xB3B3, 0xB0A9, 0xB3B4, 0xB0AB, 0xB3B5, 0xB0AC, 0xB3B6, 0xB0AD,
+	0xB3B7, 0xB0AE, 0xB3B8, 0xB0AF, 0xB3B9, 0xB0B1, 0xB3BA, 0xB0B3,	0xB3BB, 0xB0B4, 0xB3BC, 0xB0B5, 0xB3BD, 0xB0B8, 0xB3BE, 0xB0BC,
+	0xB3BF, 0xB0C4, 0xB3C0, 0xB0C5, 0xB3C1, 0xB0C7, 0xB3C2, 0xB0C8,	0xB3C3, 0xB0C9, 0xB3C4, 0xB0D0, 0xB3C5, 0xB0D1, 0xB3C6, 0xB0D4,
+	0xB3C7, 0xB0D8, 0xB3C8, 0xB0E0, 0xB3C9, 0xB0E5, 0xB3CA, 0xB108,	0xB3CB, 0xB109, 0xB3CC, 0xB10B, 0xB3CD, 0xB10C, 0xB3CE, 0xB110,
+	0xB3CF, 0xB112, 0xB3D0, 0xB113, 0xB3D1, 0xB118, 0xB3D2, 0xB119,	0xB3D3, 0xB11B, 0xB3D4, 0xB11C, 0xB3D5, 0xB11D, 0xB3D6, 0xB123,
+	0xB3D7, 0xB124, 0xB3D8, 0xB125, 0xB3D9, 0xB128, 0xB3DA, 0xB12C,	0xB3DB, 0xB134, 0xB3DC, 0xB135, 0xB3DD, 0xB137, 0xB3DE, 0xB138,
+	0xB3DF, 0xB139, 0xB3E0, 0xB140, 0xB3E1, 0xB141, 0xB3E2, 0xB144,	0xB3E3, 0xB148, 0xB3E4, 0xB150, 0xB3E5, 0xB151, 0xB3E6, 0xB154,
+	0xB3E7, 0xB155, 0xB3E8, 0xB158, 0xB3E9, 0xB15C, 0xB3EA, 0xB160,	0xB3EB, 0xB178, 0xB3EC, 0xB179, 0xB3ED, 0xB17C, 0xB3EE, 0xB180,
+	0xB3EF, 0xB182, 0xB3F0, 0xB188, 0xB3F1, 0xB189, 0xB3F2, 0xB18B,	0xB3F3, 0xB18D, 0xB3F4, 0xB192, 0xB3F5, 0xB193, 0xB3F6, 0xB194,
+	0xB3F7, 0xB198, 0xB3F8, 0xB19C, 0xB3F9, 0xB1A8, 0xB3FA, 0xB1CC,	0xB3FB, 0xB1D0, 0xB3FC, 0xB1D4, 0xB3FD, 0xB1DC, 0xB3FE, 0xB1DD,
+	0xB441, 0xD02E, 0xB442, 0xD02F, 0xB443, 0xD030, 0xB444, 0xD031,	0xB445, 0xD032, 0xB446, 0xD033, 0xB447, 0xD036, 0xB448, 0xD037,
+	0xB449, 0xD039, 0xB44A, 0xD03A, 0xB44B, 0xD03B, 0xB44C, 0xD03D,	0xB44D, 0xD03E, 0xB44E, 0xD03F, 0xB44F, 0xD040, 0xB450, 0xD041,
+	0xB451, 0xD042, 0xB452, 0xD043, 0xB453, 0xD046, 0xB454, 0xD048,	0xB455, 0xD04A, 0xB456, 0xD04B, 0xB457, 0xD04C, 0xB458, 0xD04D,
+	0xB459, 0xD04E, 0xB45A, 0xD04F, 0xB461, 0xD051, 0xB462, 0xD052,	0xB463, 0xD053, 0xB464, 0xD055, 0xB465, 0xD056, 0xB466, 0xD057,
+	0xB467, 0xD059, 0xB468, 0xD05A, 0xB469, 0xD05B, 0xB46A, 0xD05C,	0xB46B, 0xD05D, 0xB46C, 0xD05E, 0xB46D, 0xD05F, 0xB46E, 0xD061,
+	0xB46F, 0xD062, 0xB470, 0xD063, 0xB471, 0xD064, 0xB472, 0xD065,	0xB473, 0xD066, 0xB474, 0xD067, 0xB475, 0xD068, 0xB476, 0xD069,
+	0xB477, 0xD06A, 0xB478, 0xD06B, 0xB479, 0xD06E, 0xB47A, 0xD06F,	0xB481, 0xD071, 0xB482, 0xD072, 0xB483, 0xD073, 0xB484, 0xD075,
+	0xB485, 0xD076, 0xB486, 0xD077, 0xB487, 0xD078, 0xB488, 0xD079,	0xB489, 0xD07A, 0xB48A, 0xD07B, 0xB48B, 0xD07E, 0xB48C, 0xD07F,
+	0xB48D, 0xD080, 0xB48E, 0xD082, 0xB48F, 0xD083, 0xB490, 0xD084,	0xB491, 0xD085, 0xB492, 0xD086, 0xB493, 0xD087, 0xB494, 0xD088,
+	0xB495, 0xD089, 0xB496, 0xD08A, 0xB497, 0xD08B, 0xB498, 0xD08C,	0xB499, 0xD08D, 0xB49A, 0xD08E, 0xB49B, 0xD08F, 0xB49C, 0xD090,
+	0xB49D, 0xD091, 0xB49E, 0xD092, 0xB49F, 0xD093, 0xB4A0, 0xD094,	0xB4A1, 0xB1DF, 0xB4A2, 0xB1E8, 0xB4A3, 0xB1E9, 0xB4A4, 0xB1EC,
+	0xB4A5, 0xB1F0, 0xB4A6, 0xB1F9, 0xB4A7, 0xB1FB, 0xB4A8, 0xB1FD,	0xB4A9, 0xB204, 0xB4AA, 0xB205, 0xB4AB, 0xB208, 0xB4AC, 0xB20B,
+	0xB4AD, 0xB20C, 0xB4AE, 0xB214, 0xB4AF, 0xB215, 0xB4B0, 0xB217,	0xB4B1, 0xB219, 0xB4B2, 0xB220, 0xB4B3, 0xB234, 0xB4B4, 0xB23C,
+	0xB4B5, 0xB258, 0xB4B6, 0xB25C, 0xB4B7, 0xB260, 0xB4B8, 0xB268,	0xB4B9, 0xB269, 0xB4BA, 0xB274, 0xB4BB, 0xB275, 0xB4BC, 0xB27C,
+	0xB4BD, 0xB284, 0xB4BE, 0xB285, 0xB4BF, 0xB289, 0xB4C0, 0xB290,	0xB4C1, 0xB291, 0xB4C2, 0xB294, 0xB4C3, 0xB298, 0xB4C4, 0xB299,
+	0xB4C5, 0xB29A, 0xB4C6, 0xB2A0, 0xB4C7, 0xB2A1, 0xB4C8, 0xB2A3,	0xB4C9, 0xB2A5, 0xB4CA, 0xB2A6, 0xB4CB, 0xB2AA, 0xB4CC, 0xB2AC,
+	0xB4CD, 0xB2B0, 0xB4CE, 0xB2B4, 0xB4CF, 0xB2C8, 0xB4D0, 0xB2C9,	0xB4D1, 0xB2CC, 0xB4D2, 0xB2D0, 0xB4D3, 0xB2D2, 0xB4D4, 0xB2D8,
+	0xB4D5, 0xB2D9, 0xB4D6, 0xB2DB, 0xB4D7, 0xB2DD, 0xB4D8, 0xB2E2,	0xB4D9, 0xB2E4, 0xB4DA, 0xB2E5, 0xB4DB, 0xB2E6, 0xB4DC, 0xB2E8,
+	0xB4DD, 0xB2EB, 0xB4DE, 0xB2EC, 0xB4DF, 0xB2ED, 0xB4E0, 0xB2EE,	0xB4E1, 0xB2EF, 0xB4E2, 0xB2F3, 0xB4E3, 0xB2F4, 0xB4E4, 0xB2F5,
+	0xB4E5, 0xB2F7, 0xB4E6, 0xB2F8, 0xB4E7, 0xB2F9, 0xB4E8, 0xB2FA,	0xB4E9, 0xB2FB, 0xB4EA, 0xB2FF, 0xB4EB, 0xB300, 0xB4EC, 0xB301,
+	0xB4ED, 0xB304, 0xB4EE, 0xB308, 0xB4EF, 0xB310, 0xB4F0, 0xB311,	0xB4F1, 0xB313, 0xB4F2, 0xB314, 0xB4F3, 0xB315, 0xB4F4, 0xB31C,
+	0xB4F5, 0xB354, 0xB4F6, 0xB355, 0xB4F7, 0xB356, 0xB4F8, 0xB358,	0xB4F9, 0xB35B, 0xB4FA, 0xB35C, 0xB4FB, 0xB35E, 0xB4FC, 0xB35F,
+	0xB4FD, 0xB364, 0xB4FE, 0xB365, 0xB541, 0xD095, 0xB542, 0xD096,	0xB543, 0xD097, 0xB544, 0xD098, 0xB545, 0xD099, 0xB546, 0xD09A,
+	0xB547, 0xD09B, 0xB548, 0xD09C, 0xB549, 0xD09D, 0xB54A, 0xD09E,	0xB54B, 0xD09F, 0xB54C, 0xD0A0, 0xB54D, 0xD0A1, 0xB54E, 0xD0A2,
+	0xB54F, 0xD0A3, 0xB550, 0xD0A6, 0xB551, 0xD0A7, 0xB552, 0xD0A9,	0xB553, 0xD0AA, 0xB554, 0xD0AB, 0xB555, 0xD0AD, 0xB556, 0xD0AE,
+	0xB557, 0xD0AF, 0xB558, 0xD0B0, 0xB559, 0xD0B1, 0xB55A, 0xD0B2,	0xB561, 0xD0B3, 0xB562, 0xD0B6, 0xB563, 0xD0B8, 0xB564, 0xD0BA,
+	0xB565, 0xD0BB, 0xB566, 0xD0BC, 0xB567, 0xD0BD, 0xB568, 0xD0BE,	0xB569, 0xD0BF, 0xB56A, 0xD0C2, 0xB56B, 0xD0C3, 0xB56C, 0xD0C5,
+	0xB56D, 0xD0C6, 0xB56E, 0xD0C7, 0xB56F, 0xD0CA, 0xB570, 0xD0CB,	0xB571, 0xD0CC, 0xB572, 0xD0CD, 0xB573, 0xD0CE, 0xB574, 0xD0CF,
+	0xB575, 0xD0D2, 0xB576, 0xD0D6, 0xB577, 0xD0D7, 0xB578, 0xD0D8,	0xB579, 0xD0D9, 0xB57A, 0xD0DA, 0xB581, 0xD0DB, 0xB582, 0xD0DE,
+	0xB583, 0xD0DF, 0xB584, 0xD0E1, 0xB585, 0xD0E2, 0xB586, 0xD0E3,	0xB587, 0xD0E5, 0xB588, 0xD0E6, 0xB589, 0xD0E7, 0xB58A, 0xD0E8,
+	0xB58B, 0xD0E9, 0xB58C, 0xD0EA, 0xB58D, 0xD0EB, 0xB58E, 0xD0EE,	0xB58F, 0xD0F2, 0xB590, 0xD0F3, 0xB591, 0xD0F4, 0xB592, 0xD0F5,
+	0xB593, 0xD0F6, 0xB594, 0xD0F7, 0xB595, 0xD0F9, 0xB596, 0xD0FA,	0xB597, 0xD0FB, 0xB598, 0xD0FC, 0xB599, 0xD0FD, 0xB59A, 0xD0FE,
+	0xB59B, 0xD0FF, 0xB59C, 0xD100, 0xB59D, 0xD101, 0xB59E, 0xD102,	0xB59F, 0xD103, 0xB5A0, 0xD104, 0xB5A1, 0xB367, 0xB5A2, 0xB369,
+	0xB5A3, 0xB36B, 0xB5A4, 0xB36E, 0xB5A5, 0xB370, 0xB5A6, 0xB371,	0xB5A7, 0xB374, 0xB5A8, 0xB378, 0xB5A9, 0xB380, 0xB5AA, 0xB381,
+	0xB5AB, 0xB383, 0xB5AC, 0xB384, 0xB5AD, 0xB385, 0xB5AE, 0xB38C,	0xB5AF, 0xB390, 0xB5B0, 0xB394, 0xB5B1, 0xB3A0, 0xB5B2, 0xB3A1,
+	0xB5B3, 0xB3A8, 0xB5B4, 0xB3AC, 0xB5B5, 0xB3C4, 0xB5B6, 0xB3C5,	0xB5B7, 0xB3C8, 0xB5B8, 0xB3CB, 0xB5B9, 0xB3CC, 0xB5BA, 0xB3CE,
+	0xB5BB, 0xB3D0, 0xB5BC, 0xB3D4, 0xB5BD, 0xB3D5, 0xB5BE, 0xB3D7,	0xB5BF, 0xB3D9, 0xB5C0, 0xB3DB, 0xB5C1, 0xB3DD, 0xB5C2, 0xB3E0,
+	0xB5C3, 0xB3E4, 0xB5C4, 0xB3E8, 0xB5C5, 0xB3FC, 0xB5C6, 0xB410,	0xB5C7, 0xB418, 0xB5C8, 0xB41C, 0xB5C9, 0xB420, 0xB5CA, 0xB428,
+	0xB5CB, 0xB429, 0xB5CC, 0xB42B, 0xB5CD, 0xB434, 0xB5CE, 0xB450,	0xB5CF, 0xB451, 0xB5D0, 0xB454, 0xB5D1, 0xB458, 0xB5D2, 0xB460,
+	0xB5D3, 0xB461, 0xB5D4, 0xB463, 0xB5D5, 0xB465, 0xB5D6, 0xB46C,	0xB5D7, 0xB480, 0xB5D8, 0xB488, 0xB5D9, 0xB49D, 0xB5DA, 0xB4A4,
+	0xB5DB, 0xB4A8, 0xB5DC, 0xB4AC, 0xB5DD, 0xB4B5, 0xB5DE, 0xB4B7,	0xB5DF, 0xB4B9, 0xB5E0, 0xB4C0, 0xB5E1, 0xB4C4, 0xB5E2, 0xB4C8,
+	0xB5E3, 0xB4D0, 0xB5E4, 0xB4D5, 0xB5E5, 0xB4DC, 0xB5E6, 0xB4DD,	0xB5E7, 0xB4E0, 0xB5E8, 0xB4E3, 0xB5E9, 0xB4E4, 0xB5EA, 0xB4E6,
+	0xB5EB, 0xB4EC, 0xB5EC, 0xB4ED, 0xB5ED, 0xB4EF, 0xB5EE, 0xB4F1,	0xB5EF, 0xB4F8, 0xB5F0, 0xB514, 0xB5F1, 0xB515, 0xB5F2, 0xB518,
+	0xB5F3, 0xB51B, 0xB5F4, 0xB51C, 0xB5F5, 0xB524, 0xB5F6, 0xB525,	0xB5F7, 0xB527, 0xB5F8, 0xB528, 0xB5F9, 0xB529, 0xB5FA, 0xB52A,
+	0xB5FB, 0xB530, 0xB5FC, 0xB531, 0xB5FD, 0xB534, 0xB5FE, 0xB538,	0xB641, 0xD105, 0xB642, 0xD106, 0xB643, 0xD107, 0xB644, 0xD108,
+	0xB645, 0xD109, 0xB646, 0xD10A, 0xB647, 0xD10B, 0xB648, 0xD10C,	0xB649, 0xD10E, 0xB64A, 0xD10F, 0xB64B, 0xD110, 0xB64C, 0xD111,
+	0xB64D, 0xD112, 0xB64E, 0xD113, 0xB64F, 0xD114, 0xB650, 0xD115,	0xB651, 0xD116, 0xB652, 0xD117, 0xB653, 0xD118, 0xB654, 0xD119,
+	0xB655, 0xD11A, 0xB656, 0xD11B, 0xB657, 0xD11C, 0xB658, 0xD11D,	0xB659, 0xD11E, 0xB65A, 0xD11F, 0xB661, 0xD120, 0xB662, 0xD121,
+	0xB663, 0xD122, 0xB664, 0xD123, 0xB665, 0xD124, 0xB666, 0xD125,	0xB667, 0xD126, 0xB668, 0xD127, 0xB669, 0xD128, 0xB66A, 0xD129,
+	0xB66B, 0xD12A, 0xB66C, 0xD12B, 0xB66D, 0xD12C, 0xB66E, 0xD12D,	0xB66F, 0xD12E, 0xB670, 0xD12F, 0xB671, 0xD132, 0xB672, 0xD133,
+	0xB673, 0xD135, 0xB674, 0xD136, 0xB675, 0xD137, 0xB676, 0xD139,	0xB677, 0xD13B, 0xB678, 0xD13C, 0xB679, 0xD13D, 0xB67A, 0xD13E,
+	0xB681, 0xD13F, 0xB682, 0xD142, 0xB683, 0xD146, 0xB684, 0xD147,	0xB685, 0xD148, 0xB686, 0xD149, 0xB687, 0xD14A, 0xB688, 0xD14B,
+	0xB689, 0xD14E, 0xB68A, 0xD14F, 0xB68B, 0xD151, 0xB68C, 0xD152,	0xB68D, 0xD153, 0xB68E, 0xD155, 0xB68F, 0xD156, 0xB690, 0xD157,
+	0xB691, 0xD158, 0xB692, 0xD159, 0xB693, 0xD15A, 0xB694, 0xD15B,	0xB695, 0xD15E, 0xB696, 0xD160, 0xB697, 0xD162, 0xB698, 0xD163,
+	0xB699, 0xD164, 0xB69A, 0xD165, 0xB69B, 0xD166, 0xB69C, 0xD167,	0xB69D, 0xD169, 0xB69E, 0xD16A, 0xB69F, 0xD16B, 0xB6A0, 0xD16D,
+	0xB6A1, 0xB540, 0xB6A2, 0xB541, 0xB6A3, 0xB543, 0xB6A4, 0xB544,	0xB6A5, 0xB545, 0xB6A6, 0xB54B, 0xB6A7, 0xB54C, 0xB6A8, 0xB54D,
+	0xB6A9, 0xB550, 0xB6AA, 0xB554, 0xB6AB, 0xB55C, 0xB6AC, 0xB55D,	0xB6AD, 0xB55F, 0xB6AE, 0xB560, 0xB6AF, 0xB561, 0xB6B0, 0xB5A0,
+	0xB6B1, 0xB5A1, 0xB6B2, 0xB5A4, 0xB6B3, 0xB5A8, 0xB6B4, 0xB5AA,	0xB6B5, 0xB5AB, 0xB6B6, 0xB5B0, 0xB6B7, 0xB5B1, 0xB6B8, 0xB5B3,
+	0xB6B9, 0xB5B4, 0xB6BA, 0xB5B5, 0xB6BB, 0xB5BB, 0xB6BC, 0xB5BC,	0xB6BD, 0xB5BD, 0xB6BE, 0xB5C0, 0xB6BF, 0xB5C4, 0xB6C0, 0xB5CC,
+	0xB6C1, 0xB5CD, 0xB6C2, 0xB5CF, 0xB6C3, 0xB5D0, 0xB6C4, 0xB5D1,	0xB6C5, 0xB5D8, 0xB6C6, 0xB5EC, 0xB6C7, 0xB610, 0xB6C8, 0xB611,
+	0xB6C9, 0xB614, 0xB6CA, 0xB618, 0xB6CB, 0xB625, 0xB6CC, 0xB62C,	0xB6CD, 0xB634, 0xB6CE, 0xB648, 0xB6CF, 0xB664, 0xB6D0, 0xB668,
+	0xB6D1, 0xB69C, 0xB6D2, 0xB69D, 0xB6D3, 0xB6A0, 0xB6D4, 0xB6A4,	0xB6D5, 0xB6AB, 0xB6D6, 0xB6AC, 0xB6D7, 0xB6B1, 0xB6D8, 0xB6D4,
+	0xB6D9, 0xB6F0, 0xB6DA, 0xB6F4, 0xB6DB, 0xB6F8, 0xB6DC, 0xB700,	0xB6DD, 0xB701, 0xB6DE, 0xB705, 0xB6DF, 0xB728, 0xB6E0, 0xB729,
+	0xB6E1, 0xB72C, 0xB6E2, 0xB72F, 0xB6E3, 0xB730, 0xB6E4, 0xB738,	0xB6E5, 0xB739, 0xB6E6, 0xB73B, 0xB6E7, 0xB744, 0xB6E8, 0xB748,
+	0xB6E9, 0xB74C, 0xB6EA, 0xB754, 0xB6EB, 0xB755, 0xB6EC, 0xB760,	0xB6ED, 0xB764, 0xB6EE, 0xB768, 0xB6EF, 0xB770, 0xB6F0, 0xB771,
+	0xB6F1, 0xB773, 0xB6F2, 0xB775, 0xB6F3, 0xB77C, 0xB6F4, 0xB77D,	0xB6F5, 0xB780, 0xB6F6, 0xB784, 0xB6F7, 0xB78C, 0xB6F8, 0xB78D,
+	0xB6F9, 0xB78F, 0xB6FA, 0xB790, 0xB6FB, 0xB791, 0xB6FC, 0xB792,	0xB6FD, 0xB796, 0xB6FE, 0xB797, 0xB741, 0xD16E, 0xB742, 0xD16F,
+	0xB743, 0xD170, 0xB744, 0xD171, 0xB745, 0xD172, 0xB746, 0xD173,	0xB747, 0xD174, 0xB748, 0xD175, 0xB749, 0xD176, 0xB74A, 0xD177,
+	0xB74B, 0xD178, 0xB74C, 0xD179, 0xB74D, 0xD17A, 0xB74E, 0xD17B,	0xB74F, 0xD17D, 0xB750, 0xD17E, 0xB751, 0xD17F, 0xB752, 0xD180,
+	0xB753, 0xD181, 0xB754, 0xD182, 0xB755, 0xD183, 0xB756, 0xD185,	0xB757, 0xD186, 0xB758, 0xD187, 0xB759, 0xD189, 0xB75A, 0xD18A,
+	0xB761, 0xD18B, 0xB762, 0xD18C, 0xB763, 0xD18D, 0xB764, 0xD18E,	0xB765, 0xD18F, 0xB766, 0xD190, 0xB767, 0xD191, 0xB768, 0xD192,
+	0xB769, 0xD193, 0xB76A, 0xD194, 0xB76B, 0xD195, 0xB76C, 0xD196,	0xB76D, 0xD197, 0xB76E, 0xD198, 0xB76F, 0xD199, 0xB770, 0xD19A,
+	0xB771, 0xD19B, 0xB772, 0xD19C, 0xB773, 0xD19D, 0xB774, 0xD19E,	0xB775, 0xD19F, 0xB776, 0xD1A2, 0xB777, 0xD1A3, 0xB778, 0xD1A5,
+	0xB779, 0xD1A6, 0xB77A, 0xD1A7, 0xB781, 0xD1A9, 0xB782, 0xD1AA,	0xB783, 0xD1AB, 0xB784, 0xD1AC, 0xB785, 0xD1AD, 0xB786, 0xD1AE,
+	0xB787, 0xD1AF, 0xB788, 0xD1B2, 0xB789, 0xD1B4, 0xB78A, 0xD1B6,	0xB78B, 0xD1B7, 0xB78C, 0xD1B8, 0xB78D, 0xD1B9, 0xB78E, 0xD1BB,
+	0xB78F, 0xD1BD, 0xB790, 0xD1BE, 0xB791, 0xD1BF, 0xB792, 0xD1C1,	0xB793, 0xD1C2, 0xB794, 0xD1C3, 0xB795, 0xD1C4, 0xB796, 0xD1C5,
+	0xB797, 0xD1C6, 0xB798, 0xD1C7, 0xB799, 0xD1C8, 0xB79A, 0xD1C9,	0xB79B, 0xD1CA, 0xB79C, 0xD1CB, 0xB79D, 0xD1CC, 0xB79E, 0xD1CD,
+	0xB79F, 0xD1CE, 0xB7A0, 0xD1CF, 0xB7A1, 0xB798, 0xB7A2, 0xB799,	0xB7A3, 0xB79C, 0xB7A4, 0xB7A0, 0xB7A5, 0xB7A8, 0xB7A6, 0xB7A9,
+	0xB7A7, 0xB7AB, 0xB7A8, 0xB7AC, 0xB7A9, 0xB7AD, 0xB7AA, 0xB7B4,	0xB7AB, 0xB7B5, 0xB7AC, 0xB7B8, 0xB7AD, 0xB7C7, 0xB7AE, 0xB7C9,
+	0xB7AF, 0xB7EC, 0xB7B0, 0xB7ED, 0xB7B1, 0xB7F0, 0xB7B2, 0xB7F4,	0xB7B3, 0xB7FC, 0xB7B4, 0xB7FD, 0xB7B5, 0xB7FF, 0xB7B6, 0xB800,
+	0xB7B7, 0xB801, 0xB7B8, 0xB807, 0xB7B9, 0xB808, 0xB7BA, 0xB809,	0xB7BB, 0xB80C, 0xB7BC, 0xB810, 0xB7BD, 0xB818, 0xB7BE, 0xB819,
+	0xB7BF, 0xB81B, 0xB7C0, 0xB81D, 0xB7C1, 0xB824, 0xB7C2, 0xB825,	0xB7C3, 0xB828, 0xB7C4, 0xB82C, 0xB7C5, 0xB834, 0xB7C6, 0xB835,
+	0xB7C7, 0xB837, 0xB7C8, 0xB838, 0xB7C9, 0xB839, 0xB7CA, 0xB840,	0xB7CB, 0xB844, 0xB7CC, 0xB851, 0xB7CD, 0xB853, 0xB7CE, 0xB85C,
+	0xB7CF, 0xB85D, 0xB7D0, 0xB860, 0xB7D1, 0xB864, 0xB7D2, 0xB86C,	0xB7D3, 0xB86D, 0xB7D4, 0xB86F, 0xB7D5, 0xB871, 0xB7D6, 0xB878,
+	0xB7D7, 0xB87C, 0xB7D8, 0xB88D, 0xB7D9, 0xB8A8, 0xB7DA, 0xB8B0,	0xB7DB, 0xB8B4, 0xB7DC, 0xB8B8, 0xB7DD, 0xB8C0, 0xB7DE, 0xB8C1,
+	0xB7DF, 0xB8C3, 0xB7E0, 0xB8C5, 0xB7E1, 0xB8CC, 0xB7E2, 0xB8D0,	0xB7E3, 0xB8D4, 0xB7E4, 0xB8DD, 0xB7E5, 0xB8DF, 0xB7E6, 0xB8E1,
+	0xB7E7, 0xB8E8, 0xB7E8, 0xB8E9, 0xB7E9, 0xB8EC, 0xB7EA, 0xB8F0,	0xB7EB, 0xB8F8, 0xB7EC, 0xB8F9, 0xB7ED, 0xB8FB, 0xB7EE, 0xB8FD,
+	0xB7EF, 0xB904, 0xB7F0, 0xB918, 0xB7F1, 0xB920, 0xB7F2, 0xB93C,	0xB7F3, 0xB93D, 0xB7F4, 0xB940, 0xB7F5, 0xB944, 0xB7F6, 0xB94C,
+	0xB7F7, 0xB94F, 0xB7F8, 0xB951, 0xB7F9, 0xB958, 0xB7FA, 0xB959,	0xB7FB, 0xB95C, 0xB7FC, 0xB960, 0xB7FD, 0xB968, 0xB7FE, 0xB969,
+	0xB841, 0xD1D0, 0xB842, 0xD1D1, 0xB843, 0xD1D2, 0xB844, 0xD1D3,	0xB845, 0xD1D4, 0xB846, 0xD1D5, 0xB847, 0xD1D6, 0xB848, 0xD1D7,
+	0xB849, 0xD1D9, 0xB84A, 0xD1DA, 0xB84B, 0xD1DB, 0xB84C, 0xD1DC,	0xB84D, 0xD1DD, 0xB84E, 0xD1DE, 0xB84F, 0xD1DF, 0xB850, 0xD1E0,
+	0xB851, 0xD1E1, 0xB852, 0xD1E2, 0xB853, 0xD1E3, 0xB854, 0xD1E4,	0xB855, 0xD1E5, 0xB856, 0xD1E6, 0xB857, 0xD1E7, 0xB858, 0xD1E8,
+	0xB859, 0xD1E9, 0xB85A, 0xD1EA, 0xB861, 0xD1EB, 0xB862, 0xD1EC,	0xB863, 0xD1ED, 0xB864, 0xD1EE, 0xB865, 0xD1EF, 0xB866, 0xD1F0,
+	0xB867, 0xD1F1, 0xB868, 0xD1F2, 0xB869, 0xD1F3, 0xB86A, 0xD1F5,	0xB86B, 0xD1F6, 0xB86C, 0xD1F7, 0xB86D, 0xD1F9, 0xB86E, 0xD1FA,
+	0xB86F, 0xD1FB, 0xB870, 0xD1FC, 0xB871, 0xD1FD, 0xB872, 0xD1FE,	0xB873, 0xD1FF, 0xB874, 0xD200, 0xB875, 0xD201, 0xB876, 0xD202,
+	0xB877, 0xD203, 0xB878, 0xD204, 0xB879, 0xD205, 0xB87A, 0xD206,	0xB881, 0xD208, 0xB882, 0xD20A, 0xB883, 0xD20B, 0xB884, 0xD20C,
+	0xB885, 0xD20D, 0xB886, 0xD20E, 0xB887, 0xD20F, 0xB888, 0xD211,	0xB889, 0xD212, 0xB88A, 0xD213, 0xB88B, 0xD214, 0xB88C, 0xD215,
+	0xB88D, 0xD216, 0xB88E, 0xD217, 0xB88F, 0xD218, 0xB890, 0xD219,	0xB891, 0xD21A, 0xB892, 0xD21B, 0xB893, 0xD21C, 0xB894, 0xD21D,
+	0xB895, 0xD21E, 0xB896, 0xD21F, 0xB897, 0xD220, 0xB898, 0xD221,	0xB899, 0xD222, 0xB89A, 0xD223, 0xB89B, 0xD224, 0xB89C, 0xD225,
+	0xB89D, 0xD226, 0xB89E, 0xD227, 0xB89F, 0xD228, 0xB8A0, 0xD229,	0xB8A1, 0xB96B, 0xB8A2, 0xB96D, 0xB8A3, 0xB974, 0xB8A4, 0xB975,
+	0xB8A5, 0xB978, 0xB8A6, 0xB97C, 0xB8A7, 0xB984, 0xB8A8, 0xB985,	0xB8A9, 0xB987, 0xB8AA, 0xB989, 0xB8AB, 0xB98A, 0xB8AC, 0xB98D,
+	0xB8AD, 0xB98E, 0xB8AE, 0xB9AC, 0xB8AF, 0xB9AD, 0xB8B0, 0xB9B0,	0xB8B1, 0xB9B4, 0xB8B2, 0xB9BC, 0xB8B3, 0xB9BD, 0xB8B4, 0xB9BF,
+	0xB8B5, 0xB9C1, 0xB8B6, 0xB9C8, 0xB8B7, 0xB9C9, 0xB8B8, 0xB9CC,	0xB8B9, 0xB9CE, 0xB8BA, 0xB9CF, 0xB8BB, 0xB9D0, 0xB8BC, 0xB9D1,
+	0xB8BD, 0xB9D2, 0xB8BE, 0xB9D8, 0xB8BF, 0xB9D9, 0xB8C0, 0xB9DB,	0xB8C1, 0xB9DD, 0xB8C2, 0xB9DE, 0xB8C3, 0xB9E1, 0xB8C4, 0xB9E3,
+	0xB8C5, 0xB9E4, 0xB8C6, 0xB9E5, 0xB8C7, 0xB9E8, 0xB8C8, 0xB9EC,	0xB8C9, 0xB9F4, 0xB8CA, 0xB9F5, 0xB8CB, 0xB9F7, 0xB8CC, 0xB9F8,
+	0xB8CD, 0xB9F9, 0xB8CE, 0xB9FA, 0xB8CF, 0xBA00, 0xB8D0, 0xBA01,	0xB8D1, 0xBA08, 0xB8D2, 0xBA15, 0xB8D3, 0xBA38, 0xB8D4, 0xBA39,
+	0xB8D5, 0xBA3C, 0xB8D6, 0xBA40, 0xB8D7, 0xBA42, 0xB8D8, 0xBA48,	0xB8D9, 0xBA49, 0xB8DA, 0xBA4B, 0xB8DB, 0xBA4D, 0xB8DC, 0xBA4E,
+	0xB8DD, 0xBA53, 0xB8DE, 0xBA54, 0xB8DF, 0xBA55, 0xB8E0, 0xBA58,	0xB8E1, 0xBA5C, 0xB8E2, 0xBA64, 0xB8E3, 0xBA65, 0xB8E4, 0xBA67,
+	0xB8E5, 0xBA68, 0xB8E6, 0xBA69, 0xB8E7, 0xBA70, 0xB8E8, 0xBA71,	0xB8E9, 0xBA74, 0xB8EA, 0xBA78, 0xB8EB, 0xBA83, 0xB8EC, 0xBA84,
+	0xB8ED, 0xBA85, 0xB8EE, 0xBA87, 0xB8EF, 0xBA8C, 0xB8F0, 0xBAA8,	0xB8F1, 0xBAA9, 0xB8F2, 0xBAAB, 0xB8F3, 0xBAAC, 0xB8F4, 0xBAB0,
+	0xB8F5, 0xBAB2, 0xB8F6, 0xBAB8, 0xB8F7, 0xBAB9, 0xB8F8, 0xBABB,	0xB8F9, 0xBABD, 0xB8FA, 0xBAC4, 0xB8FB, 0xBAC8, 0xB8FC, 0xBAD8,
+	0xB8FD, 0xBAD9, 0xB8FE, 0xBAFC, 0xB941, 0xD22A, 0xB942, 0xD22B,	0xB943, 0xD22E, 0xB944, 0xD22F, 0xB945, 0xD231, 0xB946, 0xD232,
+	0xB947, 0xD233, 0xB948, 0xD235, 0xB949, 0xD236, 0xB94A, 0xD237,	0xB94B, 0xD238, 0xB94C, 0xD239, 0xB94D, 0xD23A, 0xB94E, 0xD23B,
+	0xB94F, 0xD23E, 0xB950, 0xD240, 0xB951, 0xD242, 0xB952, 0xD243,	0xB953, 0xD244, 0xB954, 0xD245, 0xB955, 0xD246, 0xB956, 0xD247,
+	0xB957, 0xD249, 0xB958, 0xD24A, 0xB959, 0xD24B, 0xB95A, 0xD24C,	0xB961, 0xD24D, 0xB962, 0xD24E, 0xB963, 0xD24F, 0xB964, 0xD250,
+	0xB965, 0xD251, 0xB966, 0xD252, 0xB967, 0xD253, 0xB968, 0xD254,	0xB969, 0xD255, 0xB96A, 0xD256, 0xB96B, 0xD257, 0xB96C, 0xD258,
+	0xB96D, 0xD259, 0xB96E, 0xD25A, 0xB96F, 0xD25B, 0xB970, 0xD25D,	0xB971, 0xD25E, 0xB972, 0xD25F, 0xB973, 0xD260, 0xB974, 0xD261,
+	0xB975, 0xD262, 0xB976, 0xD263, 0xB977, 0xD265, 0xB978, 0xD266,	0xB979, 0xD267, 0xB97A, 0xD268, 0xB981, 0xD269, 0xB982, 0xD26A,
+	0xB983, 0xD26B, 0xB984, 0xD26C, 0xB985, 0xD26D, 0xB986, 0xD26E,	0xB987, 0xD26F, 0xB988, 0xD270, 0xB989, 0xD271, 0xB98A, 0xD272,
+	0xB98B, 0xD273, 0xB98C, 0xD274, 0xB98D, 0xD275, 0xB98E, 0xD276,	0xB98F, 0xD277, 0xB990, 0xD278, 0xB991, 0xD279, 0xB992, 0xD27A,
+	0xB993, 0xD27B, 0xB994, 0xD27C, 0xB995, 0xD27D, 0xB996, 0xD27E,	0xB997, 0xD27F, 0xB998, 0xD282, 0xB999, 0xD283, 0xB99A, 0xD285,
+	0xB99B, 0xD286, 0xB99C, 0xD287, 0xB99D, 0xD289, 0xB99E, 0xD28A,	0xB99F, 0xD28B, 0xB9A0, 0xD28C, 0xB9A1, 0xBB00, 0xB9A2, 0xBB04,
+	0xB9A3, 0xBB0D, 0xB9A4, 0xBB0F, 0xB9A5, 0xBB11, 0xB9A6, 0xBB18,	0xB9A7, 0xBB1C, 0xB9A8, 0xBB20, 0xB9A9, 0xBB29, 0xB9AA, 0xBB2B,
+	0xB9AB, 0xBB34, 0xB9AC, 0xBB35, 0xB9AD, 0xBB36, 0xB9AE, 0xBB38,	0xB9AF, 0xBB3B, 0xB9B0, 0xBB3C, 0xB9B1, 0xBB3D, 0xB9B2, 0xBB3E,
+	0xB9B3, 0xBB44, 0xB9B4, 0xBB45, 0xB9B5, 0xBB47, 0xB9B6, 0xBB49,	0xB9B7, 0xBB4D, 0xB9B8, 0xBB4F, 0xB9B9, 0xBB50, 0xB9BA, 0xBB54,
+	0xB9BB, 0xBB58, 0xB9BC, 0xBB61, 0xB9BD, 0xBB63, 0xB9BE, 0xBB6C,	0xB9BF, 0xBB88, 0xB9C0, 0xBB8C, 0xB9C1, 0xBB90, 0xB9C2, 0xBBA4,
+	0xB9C3, 0xBBA8, 0xB9C4, 0xBBAC, 0xB9C5, 0xBBB4, 0xB9C6, 0xBBB7,	0xB9C7, 0xBBC0, 0xB9C8, 0xBBC4, 0xB9C9, 0xBBC8, 0xB9CA, 0xBBD0,
+	0xB9CB, 0xBBD3, 0xB9CC, 0xBBF8, 0xB9CD, 0xBBF9, 0xB9CE, 0xBBFC,	0xB9CF, 0xBBFF, 0xB9D0, 0xBC00, 0xB9D1, 0xBC02, 0xB9D2, 0xBC08,
+	0xB9D3, 0xBC09, 0xB9D4, 0xBC0B, 0xB9D5, 0xBC0C, 0xB9D6, 0xBC0D,	0xB9D7, 0xBC0F, 0xB9D8, 0xBC11, 0xB9D9, 0xBC14, 0xB9DA, 0xBC15,
+	0xB9DB, 0xBC16, 0xB9DC, 0xBC17, 0xB9DD, 0xBC18, 0xB9DE, 0xBC1B,	0xB9DF, 0xBC1C, 0xB9E0, 0xBC1D, 0xB9E1, 0xBC1E, 0xB9E2, 0xBC1F,
+	0xB9E3, 0xBC24, 0xB9E4, 0xBC25, 0xB9E5, 0xBC27, 0xB9E6, 0xBC29,	0xB9E7, 0xBC2D, 0xB9E8, 0xBC30, 0xB9E9, 0xBC31, 0xB9EA, 0xBC34,
+	0xB9EB, 0xBC38, 0xB9EC, 0xBC40, 0xB9ED, 0xBC41, 0xB9EE, 0xBC43,	0xB9EF, 0xBC44, 0xB9F0, 0xBC45, 0xB9F1, 0xBC49, 0xB9F2, 0xBC4C,
+	0xB9F3, 0xBC4D, 0xB9F4, 0xBC50, 0xB9F5, 0xBC5D, 0xB9F6, 0xBC84,	0xB9F7, 0xBC85, 0xB9F8, 0xBC88, 0xB9F9, 0xBC8B, 0xB9FA, 0xBC8C,
+	0xB9FB, 0xBC8E, 0xB9FC, 0xBC94, 0xB9FD, 0xBC95, 0xB9FE, 0xBC97,	0xBA41, 0xD28D, 0xBA42, 0xD28E, 0xBA43, 0xD28F, 0xBA44, 0xD292,
+	0xBA45, 0xD293, 0xBA46, 0xD294, 0xBA47, 0xD296, 0xBA48, 0xD297,	0xBA49, 0xD298, 0xBA4A, 0xD299, 0xBA4B, 0xD29A, 0xBA4C, 0xD29B,
+	0xBA4D, 0xD29D, 0xBA4E, 0xD29E, 0xBA4F, 0xD29F, 0xBA50, 0xD2A1,	0xBA51, 0xD2A2, 0xBA52, 0xD2A3, 0xBA53, 0xD2A5, 0xBA54, 0xD2A6,
+	0xBA55, 0xD2A7, 0xBA56, 0xD2A8, 0xBA57, 0xD2A9, 0xBA58, 0xD2AA,	0xBA59, 0xD2AB, 0xBA5A, 0xD2AD, 0xBA61, 0xD2AE, 0xBA62, 0xD2AF,
+	0xBA63, 0xD2B0, 0xBA64, 0xD2B2, 0xBA65, 0xD2B3, 0xBA66, 0xD2B4,	0xBA67, 0xD2B5, 0xBA68, 0xD2B6, 0xBA69, 0xD2B7, 0xBA6A, 0xD2BA,
+	0xBA6B, 0xD2BB, 0xBA6C, 0xD2BD, 0xBA6D, 0xD2BE, 0xBA6E, 0xD2C1,	0xBA6F, 0xD2C3, 0xBA70, 0xD2C4, 0xBA71, 0xD2C5, 0xBA72, 0xD2C6,
+	0xBA73, 0xD2C7, 0xBA74, 0xD2CA, 0xBA75, 0xD2CC, 0xBA76, 0xD2CD,	0xBA77, 0xD2CE, 0xBA78, 0xD2CF, 0xBA79, 0xD2D0, 0xBA7A, 0xD2D1,
+	0xBA81, 0xD2D2, 0xBA82, 0xD2D3, 0xBA83, 0xD2D5, 0xBA84, 0xD2D6,	0xBA85, 0xD2D7, 0xBA86, 0xD2D9, 0xBA87, 0xD2DA, 0xBA88, 0xD2DB,
+	0xBA89, 0xD2DD, 0xBA8A, 0xD2DE, 0xBA8B, 0xD2DF, 0xBA8C, 0xD2E0,	0xBA8D, 0xD2E1, 0xBA8E, 0xD2E2, 0xBA8F, 0xD2E3, 0xBA90, 0xD2E6,
+	0xBA91, 0xD2E7, 0xBA92, 0xD2E8, 0xBA93, 0xD2E9, 0xBA94, 0xD2EA,	0xBA95, 0xD2EB, 0xBA96, 0xD2EC, 0xBA97, 0xD2ED, 0xBA98, 0xD2EE,
+	0xBA99, 0xD2EF, 0xBA9A, 0xD2F2, 0xBA9B, 0xD2F3, 0xBA9C, 0xD2F5,	0xBA9D, 0xD2F6, 0xBA9E, 0xD2F7, 0xBA9F, 0xD2F9, 0xBAA0, 0xD2FA,
+	0xBAA1, 0xBC99, 0xBAA2, 0xBC9A, 0xBAA3, 0xBCA0, 0xBAA4, 0xBCA1,	0xBAA5, 0xBCA4, 0xBAA6, 0xBCA7, 0xBAA7, 0xBCA8, 0xBAA8, 0xBCB0,
+	0xBAA9, 0xBCB1, 0xBAAA, 0xBCB3, 0xBAAB, 0xBCB4, 0xBAAC, 0xBCB5,	0xBAAD, 0xBCBC, 0xBAAE, 0xBCBD, 0xBAAF, 0xBCC0, 0xBAB0, 0xBCC4,
+	0xBAB1, 0xBCCD, 0xBAB2, 0xBCCF, 0xBAB3, 0xBCD0, 0xBAB4, 0xBCD1,	0xBAB5, 0xBCD5, 0xBAB6, 0xBCD8, 0xBAB7, 0xBCDC, 0xBAB8, 0xBCF4,
+	0xBAB9, 0xBCF5, 0xBABA, 0xBCF6, 0xBABB, 0xBCF8, 0xBABC, 0xBCFC,	0xBABD, 0xBD04, 0xBABE, 0xBD05, 0xBABF, 0xBD07, 0xBAC0, 0xBD09,
+	0xBAC1, 0xBD10, 0xBAC2, 0xBD14, 0xBAC3, 0xBD24, 0xBAC4, 0xBD2C,	0xBAC5, 0xBD40, 0xBAC6, 0xBD48, 0xBAC7, 0xBD49, 0xBAC8, 0xBD4C,
+	0xBAC9, 0xBD50, 0xBACA, 0xBD58, 0xBACB, 0xBD59, 0xBACC, 0xBD64,	0xBACD, 0xBD68, 0xBACE, 0xBD80, 0xBACF, 0xBD81, 0xBAD0, 0xBD84,
+	0xBAD1, 0xBD87, 0xBAD2, 0xBD88, 0xBAD3, 0xBD89, 0xBAD4, 0xBD8A,	0xBAD5, 0xBD90, 0xBAD6, 0xBD91, 0xBAD7, 0xBD93, 0xBAD8, 0xBD95,
+	0xBAD9, 0xBD99, 0xBADA, 0xBD9A, 0xBADB, 0xBD9C, 0xBADC, 0xBDA4,	0xBADD, 0xBDB0, 0xBADE, 0xBDB8, 0xBADF, 0xBDD4, 0xBAE0, 0xBDD5,
+	0xBAE1, 0xBDD8, 0xBAE2, 0xBDDC, 0xBAE3, 0xBDE9, 0xBAE4, 0xBDF0,	0xBAE5, 0xBDF4, 0xBAE6, 0xBDF8, 0xBAE7, 0xBE00, 0xBAE8, 0xBE03,
+	0xBAE9, 0xBE05, 0xBAEA, 0xBE0C, 0xBAEB, 0xBE0D, 0xBAEC, 0xBE10,	0xBAED, 0xBE14, 0xBAEE, 0xBE1C, 0xBAEF, 0xBE1D, 0xBAF0, 0xBE1F,
+	0xBAF1, 0xBE44, 0xBAF2, 0xBE45, 0xBAF3, 0xBE48, 0xBAF4, 0xBE4C,	0xBAF5, 0xBE4E, 0xBAF6, 0xBE54, 0xBAF7, 0xBE55, 0xBAF8, 0xBE57,
+	0xBAF9, 0xBE59, 0xBAFA, 0xBE5A, 0xBAFB, 0xBE5B, 0xBAFC, 0xBE60,	0xBAFD, 0xBE61, 0xBAFE, 0xBE64, 0xBB41, 0xD2FB, 0xBB42, 0xD2FC,
+	0xBB43, 0xD2FD, 0xBB44, 0xD2FE, 0xBB45, 0xD2FF, 0xBB46, 0xD302,	0xBB47, 0xD304, 0xBB48, 0xD306, 0xBB49, 0xD307, 0xBB4A, 0xD308,
+	0xBB4B, 0xD309, 0xBB4C, 0xD30A, 0xBB4D, 0xD30B, 0xBB4E, 0xD30F,	0xBB4F, 0xD311, 0xBB50, 0xD312, 0xBB51, 0xD313, 0xBB52, 0xD315,
+	0xBB53, 0xD317, 0xBB54, 0xD318, 0xBB55, 0xD319, 0xBB56, 0xD31A,	0xBB57, 0xD31B, 0xBB58, 0xD31E, 0xBB59, 0xD322, 0xBB5A, 0xD323,
+	0xBB61, 0xD324, 0xBB62, 0xD326, 0xBB63, 0xD327, 0xBB64, 0xD32A,	0xBB65, 0xD32B, 0xBB66, 0xD32D, 0xBB67, 0xD32E, 0xBB68, 0xD32F,
+	0xBB69, 0xD331, 0xBB6A, 0xD332, 0xBB6B, 0xD333, 0xBB6C, 0xD334,	0xBB6D, 0xD335, 0xBB6E, 0xD336, 0xBB6F, 0xD337, 0xBB70, 0xD33A,
+	0xBB71, 0xD33E, 0xBB72, 0xD33F, 0xBB73, 0xD340, 0xBB74, 0xD341,	0xBB75, 0xD342, 0xBB76, 0xD343, 0xBB77, 0xD346, 0xBB78, 0xD347,
+	0xBB79, 0xD348, 0xBB7A, 0xD349, 0xBB81, 0xD34A, 0xBB82, 0xD34B,	0xBB83, 0xD34C, 0xBB84, 0xD34D, 0xBB85, 0xD34E, 0xBB86, 0xD34F,
+	0xBB87, 0xD350, 0xBB88, 0xD351, 0xBB89, 0xD352, 0xBB8A, 0xD353,	0xBB8B, 0xD354, 0xBB8C, 0xD355, 0xBB8D, 0xD356, 0xBB8E, 0xD357,
+	0xBB8F, 0xD358, 0xBB90, 0xD359, 0xBB91, 0xD35A, 0xBB92, 0xD35B,	0xBB93, 0xD35C, 0xBB94, 0xD35D, 0xBB95, 0xD35E, 0xBB96, 0xD35F,
+	0xBB97, 0xD360, 0xBB98, 0xD361, 0xBB99, 0xD362, 0xBB9A, 0xD363,	0xBB9B, 0xD364, 0xBB9C, 0xD365, 0xBB9D, 0xD366, 0xBB9E, 0xD367,
+	0xBB9F, 0xD368, 0xBBA0, 0xD369, 0xBBA1, 0xBE68, 0xBBA2, 0xBE6A,	0xBBA3, 0xBE70, 0xBBA4, 0xBE71, 0xBBA5, 0xBE73, 0xBBA6, 0xBE74,
+	0xBBA7, 0xBE75, 0xBBA8, 0xBE7B, 0xBBA9, 0xBE7C, 0xBBAA, 0xBE7D,	0xBBAB, 0xBE80, 0xBBAC, 0xBE84, 0xBBAD, 0xBE8C, 0xBBAE, 0xBE8D,
+	0xBBAF, 0xBE8F, 0xBBB0, 0xBE90, 0xBBB1, 0xBE91, 0xBBB2, 0xBE98,	0xBBB3, 0xBE99, 0xBBB4, 0xBEA8, 0xBBB5, 0xBED0, 0xBBB6, 0xBED1,
+	0xBBB7, 0xBED4, 0xBBB8, 0xBED7, 0xBBB9, 0xBED8, 0xBBBA, 0xBEE0,	0xBBBB, 0xBEE3, 0xBBBC, 0xBEE4, 0xBBBD, 0xBEE5, 0xBBBE, 0xBEEC,
+	0xBBBF, 0xBF01, 0xBBC0, 0xBF08, 0xBBC1, 0xBF09, 0xBBC2, 0xBF18,	0xBBC3, 0xBF19, 0xBBC4, 0xBF1B, 0xBBC5, 0xBF1C, 0xBBC6, 0xBF1D,
+	0xBBC7, 0xBF40, 0xBBC8, 0xBF41, 0xBBC9, 0xBF44, 0xBBCA, 0xBF48,	0xBBCB, 0xBF50, 0xBBCC, 0xBF51, 0xBBCD, 0xBF55, 0xBBCE, 0xBF94,
+	0xBBCF, 0xBFB0, 0xBBD0, 0xBFC5, 0xBBD1, 0xBFCC, 0xBBD2, 0xBFCD,	0xBBD3, 0xBFD0, 0xBBD4, 0xBFD4, 0xBBD5, 0xBFDC, 0xBBD6, 0xBFDF,
+	0xBBD7, 0xBFE1, 0xBBD8, 0xC03C, 0xBBD9, 0xC051, 0xBBDA, 0xC058,	0xBBDB, 0xC05C, 0xBBDC, 0xC060, 0xBBDD, 0xC068, 0xBBDE, 0xC069,
+	0xBBDF, 0xC090, 0xBBE0, 0xC091, 0xBBE1, 0xC094, 0xBBE2, 0xC098,	0xBBE3, 0xC0A0, 0xBBE4, 0xC0A1, 0xBBE5, 0xC0A3, 0xBBE6, 0xC0A5,
+	0xBBE7, 0xC0AC, 0xBBE8, 0xC0AD, 0xBBE9, 0xC0AF, 0xBBEA, 0xC0B0,	0xBBEB, 0xC0B3, 0xBBEC, 0xC0B4, 0xBBED, 0xC0B5, 0xBBEE, 0xC0B6,
+	0xBBEF, 0xC0BC, 0xBBF0, 0xC0BD, 0xBBF1, 0xC0BF, 0xBBF2, 0xC0C0,	0xBBF3, 0xC0C1, 0xBBF4, 0xC0C5, 0xBBF5, 0xC0C8, 0xBBF6, 0xC0C9,
+	0xBBF7, 0xC0CC, 0xBBF8, 0xC0D0, 0xBBF9, 0xC0D8, 0xBBFA, 0xC0D9,	0xBBFB, 0xC0DB, 0xBBFC, 0xC0DC, 0xBBFD, 0xC0DD, 0xBBFE, 0xC0E4,
+	0xBC41, 0xD36A, 0xBC42, 0xD36B, 0xBC43, 0xD36C, 0xBC44, 0xD36D,	0xBC45, 0xD36E, 0xBC46, 0xD36F, 0xBC47, 0xD370, 0xBC48, 0xD371,
+	0xBC49, 0xD372, 0xBC4A, 0xD373, 0xBC4B, 0xD374, 0xBC4C, 0xD375,	0xBC4D, 0xD376, 0xBC4E, 0xD377, 0xBC4F, 0xD378, 0xBC50, 0xD379,
+	0xBC51, 0xD37A, 0xBC52, 0xD37B, 0xBC53, 0xD37E, 0xBC54, 0xD37F,	0xBC55, 0xD381, 0xBC56, 0xD382, 0xBC57, 0xD383, 0xBC58, 0xD385,
+	0xBC59, 0xD386, 0xBC5A, 0xD387, 0xBC61, 0xD388, 0xBC62, 0xD389,	0xBC63, 0xD38A, 0xBC64, 0xD38B, 0xBC65, 0xD38E, 0xBC66, 0xD392,
+	0xBC67, 0xD393, 0xBC68, 0xD394, 0xBC69, 0xD395, 0xBC6A, 0xD396,	0xBC6B, 0xD397, 0xBC6C, 0xD39A, 0xBC6D, 0xD39B, 0xBC6E, 0xD39D,
+	0xBC6F, 0xD39E, 0xBC70, 0xD39F, 0xBC71, 0xD3A1, 0xBC72, 0xD3A2,	0xBC73, 0xD3A3, 0xBC74, 0xD3A4, 0xBC75, 0xD3A5, 0xBC76, 0xD3A6,
+	0xBC77, 0xD3A7, 0xBC78, 0xD3AA, 0xBC79, 0xD3AC, 0xBC7A, 0xD3AE,	0xBC81, 0xD3AF, 0xBC82, 0xD3B0, 0xBC83, 0xD3B1, 0xBC84, 0xD3B2,
+	0xBC85, 0xD3B3, 0xBC86, 0xD3B5, 0xBC87, 0xD3B6, 0xBC88, 0xD3B7,	0xBC89, 0xD3B9, 0xBC8A, 0xD3BA, 0xBC8B, 0xD3BB, 0xBC8C, 0xD3BD,
+	0xBC8D, 0xD3BE, 0xBC8E, 0xD3BF, 0xBC8F, 0xD3C0, 0xBC90, 0xD3C1,	0xBC91, 0xD3C2, 0xBC92, 0xD3C3, 0xBC93, 0xD3C6, 0xBC94, 0xD3C7,
+	0xBC95, 0xD3CA, 0xBC96, 0xD3CB, 0xBC97, 0xD3CC, 0xBC98, 0xD3CD,	0xBC99, 0xD3CE, 0xBC9A, 0xD3CF, 0xBC9B, 0xD3D1, 0xBC9C, 0xD3D2,
+	0xBC9D, 0xD3D3, 0xBC9E, 0xD3D4, 0xBC9F, 0xD3D5, 0xBCA0, 0xD3D6,	0xBCA1, 0xC0E5, 0xBCA2, 0xC0E8, 0xBCA3, 0xC0EC, 0xBCA4, 0xC0F4,
+	0xBCA5, 0xC0F5, 0xBCA6, 0xC0F7, 0xBCA7, 0xC0F9, 0xBCA8, 0xC100,	0xBCA9, 0xC104, 0xBCAA, 0xC108, 0xBCAB, 0xC110, 0xBCAC, 0xC115,
+	0xBCAD, 0xC11C, 0xBCAE, 0xC11D, 0xBCAF, 0xC11E, 0xBCB0, 0xC11F,	0xBCB1, 0xC120, 0xBCB2, 0xC123, 0xBCB3, 0xC124, 0xBCB4, 0xC126,
+	0xBCB5, 0xC127, 0xBCB6, 0xC12C, 0xBCB7, 0xC12D, 0xBCB8, 0xC12F,	0xBCB9, 0xC130, 0xBCBA, 0xC131, 0xBCBB, 0xC136, 0xBCBC, 0xC138,
+	0xBCBD, 0xC139, 0xBCBE, 0xC13C, 0xBCBF, 0xC140, 0xBCC0, 0xC148,	0xBCC1, 0xC149, 0xBCC2, 0xC14B, 0xBCC3, 0xC14C, 0xBCC4, 0xC14D,
+	0xBCC5, 0xC154, 0xBCC6, 0xC155, 0xBCC7, 0xC158, 0xBCC8, 0xC15C,	0xBCC9, 0xC164, 0xBCCA, 0xC165, 0xBCCB, 0xC167, 0xBCCC, 0xC168,
+	0xBCCD, 0xC169, 0xBCCE, 0xC170, 0xBCCF, 0xC174, 0xBCD0, 0xC178,	0xBCD1, 0xC185, 0xBCD2, 0xC18C, 0xBCD3, 0xC18D, 0xBCD4, 0xC18E,
+	0xBCD5, 0xC190, 0xBCD6, 0xC194, 0xBCD7, 0xC196, 0xBCD8, 0xC19C,	0xBCD9, 0xC19D, 0xBCDA, 0xC19F, 0xBCDB, 0xC1A1, 0xBCDC, 0xC1A5,
+	0xBCDD, 0xC1A8, 0xBCDE, 0xC1A9, 0xBCDF, 0xC1AC, 0xBCE0, 0xC1B0,	0xBCE1, 0xC1BD, 0xBCE2, 0xC1C4, 0xBCE3, 0xC1C8, 0xBCE4, 0xC1CC,
+	0xBCE5, 0xC1D4, 0xBCE6, 0xC1D7, 0xBCE7, 0xC1D8, 0xBCE8, 0xC1E0,	0xBCE9, 0xC1E4, 0xBCEA, 0xC1E8, 0xBCEB, 0xC1F0, 0xBCEC, 0xC1F1,
+	0xBCED, 0xC1F3, 0xBCEE, 0xC1FC, 0xBCEF, 0xC1FD, 0xBCF0, 0xC200,	0xBCF1, 0xC204, 0xBCF2, 0xC20C, 0xBCF3, 0xC20D, 0xBCF4, 0xC20F,
+	0xBCF5, 0xC211, 0xBCF6, 0xC218, 0xBCF7, 0xC219, 0xBCF8, 0xC21C,	0xBCF9, 0xC21F, 0xBCFA, 0xC220, 0xBCFB, 0xC228, 0xBCFC, 0xC229,
+	0xBCFD, 0xC22B, 0xBCFE, 0xC22D, 0xBD41, 0xD3D7, 0xBD42, 0xD3D9,	0xBD43, 0xD3DA, 0xBD44, 0xD3DB, 0xBD45, 0xD3DC, 0xBD46, 0xD3DD,
+	0xBD47, 0xD3DE, 0xBD48, 0xD3DF, 0xBD49, 0xD3E0, 0xBD4A, 0xD3E2,	0xBD4B, 0xD3E4, 0xBD4C, 0xD3E5, 0xBD4D, 0xD3E6, 0xBD4E, 0xD3E7,
+	0xBD4F, 0xD3E8, 0xBD50, 0xD3E9, 0xBD51, 0xD3EA, 0xBD52, 0xD3EB,	0xBD53, 0xD3EE, 0xBD54, 0xD3EF, 0xBD55, 0xD3F1, 0xBD56, 0xD3F2,
+	0xBD57, 0xD3F3, 0xBD58, 0xD3F5, 0xBD59, 0xD3F6, 0xBD5A, 0xD3F7,	0xBD61, 0xD3F8, 0xBD62, 0xD3F9, 0xBD63, 0xD3FA, 0xBD64, 0xD3FB,
+	0xBD65, 0xD3FE, 0xBD66, 0xD400, 0xBD67, 0xD402, 0xBD68, 0xD403,	0xBD69, 0xD404, 0xBD6A, 0xD405, 0xBD6B, 0xD406, 0xBD6C, 0xD407,
+	0xBD6D, 0xD409, 0xBD6E, 0xD40A, 0xBD6F, 0xD40B, 0xBD70, 0xD40C,	0xBD71, 0xD40D, 0xBD72, 0xD40E, 0xBD73, 0xD40F, 0xBD74, 0xD410,
+	0xBD75, 0xD411, 0xBD76, 0xD412, 0xBD77, 0xD413, 0xBD78, 0xD414,	0xBD79, 0xD415, 0xBD7A, 0xD416, 0xBD81, 0xD417, 0xBD82, 0xD418,
+	0xBD83, 0xD419, 0xBD84, 0xD41A, 0xBD85, 0xD41B, 0xBD86, 0xD41C,	0xBD87, 0xD41E, 0xBD88, 0xD41F, 0xBD89, 0xD420, 0xBD8A, 0xD421,
+	0xBD8B, 0xD422, 0xBD8C, 0xD423, 0xBD8D, 0xD424, 0xBD8E, 0xD425,	0xBD8F, 0xD426, 0xBD90, 0xD427, 0xBD91, 0xD428, 0xBD92, 0xD429,
+	0xBD93, 0xD42A, 0xBD94, 0xD42B, 0xBD95, 0xD42C, 0xBD96, 0xD42D,	0xBD97, 0xD42E, 0xBD98, 0xD42F, 0xBD99, 0xD430, 0xBD9A, 0xD431,
+	0xBD9B, 0xD432, 0xBD9C, 0xD433, 0xBD9D, 0xD434, 0xBD9E, 0xD435,	0xBD9F, 0xD436, 0xBDA0, 0xD437, 0xBDA1, 0xC22F, 0xBDA2, 0xC231,
+	0xBDA3, 0xC232, 0xBDA4, 0xC234, 0xBDA5, 0xC248, 0xBDA6, 0xC250,	0xBDA7, 0xC251, 0xBDA8, 0xC254, 0xBDA9, 0xC258, 0xBDAA, 0xC260,
+	0xBDAB, 0xC265, 0xBDAC, 0xC26C, 0xBDAD, 0xC26D, 0xBDAE, 0xC270,	0xBDAF, 0xC274, 0xBDB0, 0xC27C, 0xBDB1, 0xC27D, 0xBDB2, 0xC27F,
+	0xBDB3, 0xC281, 0xBDB4, 0xC288, 0xBDB5, 0xC289, 0xBDB6, 0xC290,	0xBDB7, 0xC298, 0xBDB8, 0xC29B, 0xBDB9, 0xC29D, 0xBDBA, 0xC2A4,
+	0xBDBB, 0xC2A5, 0xBDBC, 0xC2A8, 0xBDBD, 0xC2AC, 0xBDBE, 0xC2AD,	0xBDBF, 0xC2B4, 0xBDC0, 0xC2B5, 0xBDC1, 0xC2B7, 0xBDC2, 0xC2B9,
+	0xBDC3, 0xC2DC, 0xBDC4, 0xC2DD, 0xBDC5, 0xC2E0, 0xBDC6, 0xC2E3,	0xBDC7, 0xC2E4, 0xBDC8, 0xC2EB, 0xBDC9, 0xC2EC, 0xBDCA, 0xC2ED,
+	0xBDCB, 0xC2EF, 0xBDCC, 0xC2F1, 0xBDCD, 0xC2F6, 0xBDCE, 0xC2F8,	0xBDCF, 0xC2F9, 0xBDD0, 0xC2FB, 0xBDD1, 0xC2FC, 0xBDD2, 0xC300,
+	0xBDD3, 0xC308, 0xBDD4, 0xC309, 0xBDD5, 0xC30C, 0xBDD6, 0xC30D,	0xBDD7, 0xC313, 0xBDD8, 0xC314, 0xBDD9, 0xC315, 0xBDDA, 0xC318,
+	0xBDDB, 0xC31C, 0xBDDC, 0xC324, 0xBDDD, 0xC325, 0xBDDE, 0xC328,	0xBDDF, 0xC329, 0xBDE0, 0xC345, 0xBDE1, 0xC368, 0xBDE2, 0xC369,
+	0xBDE3, 0xC36C, 0xBDE4, 0xC370, 0xBDE5, 0xC372, 0xBDE6, 0xC378,	0xBDE7, 0xC379, 0xBDE8, 0xC37C, 0xBDE9, 0xC37D, 0xBDEA, 0xC384,
+	0xBDEB, 0xC388, 0xBDEC, 0xC38C, 0xBDED, 0xC3C0, 0xBDEE, 0xC3D8,	0xBDEF, 0xC3D9, 0xBDF0, 0xC3DC, 0xBDF1, 0xC3DF, 0xBDF2, 0xC3E0,
+	0xBDF3, 0xC3E2, 0xBDF4, 0xC3E8, 0xBDF5, 0xC3E9, 0xBDF6, 0xC3ED,	0xBDF7, 0xC3F4, 0xBDF8, 0xC3F5, 0xBDF9, 0xC3F8, 0xBDFA, 0xC408,
+	0xBDFB, 0xC410, 0xBDFC, 0xC424, 0xBDFD, 0xC42C, 0xBDFE, 0xC430,	0xBE41, 0xD438, 0xBE42, 0xD439, 0xBE43, 0xD43A, 0xBE44, 0xD43B,
+	0xBE45, 0xD43C, 0xBE46, 0xD43D, 0xBE47, 0xD43E, 0xBE48, 0xD43F,	0xBE49, 0xD441, 0xBE4A, 0xD442, 0xBE4B, 0xD443, 0xBE4C, 0xD445,
+	0xBE4D, 0xD446, 0xBE4E, 0xD447, 0xBE4F, 0xD448, 0xBE50, 0xD449,	0xBE51, 0xD44A, 0xBE52, 0xD44B, 0xBE53, 0xD44C, 0xBE54, 0xD44D,
+	0xBE55, 0xD44E, 0xBE56, 0xD44F, 0xBE57, 0xD450, 0xBE58, 0xD451,	0xBE59, 0xD452, 0xBE5A, 0xD453, 0xBE61, 0xD454, 0xBE62, 0xD455,
+	0xBE63, 0xD456, 0xBE64, 0xD457, 0xBE65, 0xD458, 0xBE66, 0xD459,	0xBE67, 0xD45A, 0xBE68, 0xD45B, 0xBE69, 0xD45D, 0xBE6A, 0xD45E,
+	0xBE6B, 0xD45F, 0xBE6C, 0xD461, 0xBE6D, 0xD462, 0xBE6E, 0xD463,	0xBE6F, 0xD465, 0xBE70, 0xD466, 0xBE71, 0xD467, 0xBE72, 0xD468,
+	0xBE73, 0xD469, 0xBE74, 0xD46A, 0xBE75, 0xD46B, 0xBE76, 0xD46C,	0xBE77, 0xD46E, 0xBE78, 0xD470, 0xBE79, 0xD471, 0xBE7A, 0xD472,
+	0xBE81, 0xD473, 0xBE82, 0xD474, 0xBE83, 0xD475, 0xBE84, 0xD476,	0xBE85, 0xD477, 0xBE86, 0xD47A, 0xBE87, 0xD47B, 0xBE88, 0xD47D,
+	0xBE89, 0xD47E, 0xBE8A, 0xD481, 0xBE8B, 0xD483, 0xBE8C, 0xD484,	0xBE8D, 0xD485, 0xBE8E, 0xD486, 0xBE8F, 0xD487, 0xBE90, 0xD48A,
+	0xBE91, 0xD48C, 0xBE92, 0xD48E, 0xBE93, 0xD48F, 0xBE94, 0xD490,	0xBE95, 0xD491, 0xBE96, 0xD492, 0xBE97, 0xD493, 0xBE98, 0xD495,
+	0xBE99, 0xD496, 0xBE9A, 0xD497, 0xBE9B, 0xD498, 0xBE9C, 0xD499,	0xBE9D, 0xD49A, 0xBE9E, 0xD49B, 0xBE9F, 0xD49C, 0xBEA0, 0xD49D,
+	0xBEA1, 0xC434, 0xBEA2, 0xC43C, 0xBEA3, 0xC43D, 0xBEA4, 0xC448,	0xBEA5, 0xC464, 0xBEA6, 0xC465, 0xBEA7, 0xC468, 0xBEA8, 0xC46C,
+	0xBEA9, 0xC474, 0xBEAA, 0xC475, 0xBEAB, 0xC479, 0xBEAC, 0xC480,	0xBEAD, 0xC494, 0xBEAE, 0xC49C, 0xBEAF, 0xC4B8, 0xBEB0, 0xC4BC,
+	0xBEB1, 0xC4E9, 0xBEB2, 0xC4F0, 0xBEB3, 0xC4F1, 0xBEB4, 0xC4F4,	0xBEB5, 0xC4F8, 0xBEB6, 0xC4FA, 0xBEB7, 0xC4FF, 0xBEB8, 0xC500,
+	0xBEB9, 0xC501, 0xBEBA, 0xC50C, 0xBEBB, 0xC510, 0xBEBC, 0xC514,	0xBEBD, 0xC51C, 0xBEBE, 0xC528, 0xBEBF, 0xC529, 0xBEC0, 0xC52C,
+	0xBEC1, 0xC530, 0xBEC2, 0xC538, 0xBEC3, 0xC539, 0xBEC4, 0xC53B,	0xBEC5, 0xC53D, 0xBEC6, 0xC544, 0xBEC7, 0xC545, 0xBEC8, 0xC548,
+	0xBEC9, 0xC549, 0xBECA, 0xC54A, 0xBECB, 0xC54C, 0xBECC, 0xC54D,	0xBECD, 0xC54E, 0xBECE, 0xC553, 0xBECF, 0xC554, 0xBED0, 0xC555,
+	0xBED1, 0xC557, 0xBED2, 0xC558, 0xBED3, 0xC559, 0xBED4, 0xC55D,	0xBED5, 0xC55E, 0xBED6, 0xC560, 0xBED7, 0xC561, 0xBED8, 0xC564,
+	0xBED9, 0xC568, 0xBEDA, 0xC570, 0xBEDB, 0xC571, 0xBEDC, 0xC573,	0xBEDD, 0xC574, 0xBEDE, 0xC575, 0xBEDF, 0xC57C, 0xBEE0, 0xC57D,
+	0xBEE1, 0xC580, 0xBEE2, 0xC584, 0xBEE3, 0xC587, 0xBEE4, 0xC58C,	0xBEE5, 0xC58D, 0xBEE6, 0xC58F, 0xBEE7, 0xC591, 0xBEE8, 0xC595,
+	0xBEE9, 0xC597, 0xBEEA, 0xC598, 0xBEEB, 0xC59C, 0xBEEC, 0xC5A0,	0xBEED, 0xC5A9, 0xBEEE, 0xC5B4, 0xBEEF, 0xC5B5, 0xBEF0, 0xC5B8,
+	0xBEF1, 0xC5B9, 0xBEF2, 0xC5BB, 0xBEF3, 0xC5BC, 0xBEF4, 0xC5BD,	0xBEF5, 0xC5BE, 0xBEF6, 0xC5C4, 0xBEF7, 0xC5C5, 0xBEF8, 0xC5C6,
+	0xBEF9, 0xC5C7, 0xBEFA, 0xC5C8, 0xBEFB, 0xC5C9, 0xBEFC, 0xC5CA,	0xBEFD, 0xC5CC, 0xBEFE, 0xC5CE, 0xBF41, 0xD49E, 0xBF42, 0xD49F,
+	0xBF43, 0xD4A0, 0xBF44, 0xD4A1, 0xBF45, 0xD4A2, 0xBF46, 0xD4A3,	0xBF47, 0xD4A4, 0xBF48, 0xD4A5, 0xBF49, 0xD4A6, 0xBF4A, 0xD4A7,
+	0xBF4B, 0xD4A8, 0xBF4C, 0xD4AA, 0xBF4D, 0xD4AB, 0xBF4E, 0xD4AC,	0xBF4F, 0xD4AD, 0xBF50, 0xD4AE, 0xBF51, 0xD4AF, 0xBF52, 0xD4B0,
+	0xBF53, 0xD4B1, 0xBF54, 0xD4B2, 0xBF55, 0xD4B3, 0xBF56, 0xD4B4,	0xBF57, 0xD4B5, 0xBF58, 0xD4B6, 0xBF59, 0xD4B7, 0xBF5A, 0xD4B8,
+	0xBF61, 0xD4B9, 0xBF62, 0xD4BA, 0xBF63, 0xD4BB, 0xBF64, 0xD4BC,	0xBF65, 0xD4BD, 0xBF66, 0xD4BE, 0xBF67, 0xD4BF, 0xBF68, 0xD4C0,
+	0xBF69, 0xD4C1, 0xBF6A, 0xD4C2, 0xBF6B, 0xD4C3, 0xBF6C, 0xD4C4,	0xBF6D, 0xD4C5, 0xBF6E, 0xD4C6, 0xBF6F, 0xD4C7, 0xBF70, 0xD4C8,
+	0xBF71, 0xD4C9, 0xBF72, 0xD4CA, 0xBF73, 0xD4CB, 0xBF74, 0xD4CD,	0xBF75, 0xD4CE, 0xBF76, 0xD4CF, 0xBF77, 0xD4D1, 0xBF78, 0xD4D2,
+	0xBF79, 0xD4D3, 0xBF7A, 0xD4D5, 0xBF81, 0xD4D6, 0xBF82, 0xD4D7,	0xBF83, 0xD4D8, 0xBF84, 0xD4D9, 0xBF85, 0xD4DA, 0xBF86, 0xD4DB,
+	0xBF87, 0xD4DD, 0xBF88, 0xD4DE, 0xBF89, 0xD4E0, 0xBF8A, 0xD4E1,	0xBF8B, 0xD4E2, 0xBF8C, 0xD4E3, 0xBF8D, 0xD4E4, 0xBF8E, 0xD4E5,
+	0xBF8F, 0xD4E6, 0xBF90, 0xD4E7, 0xBF91, 0xD4E9, 0xBF92, 0xD4EA,	0xBF93, 0xD4EB, 0xBF94, 0xD4ED, 0xBF95, 0xD4EE, 0xBF96, 0xD4EF,
+	0xBF97, 0xD4F1, 0xBF98, 0xD4F2, 0xBF99, 0xD4F3, 0xBF9A, 0xD4F4,	0xBF9B, 0xD4F5, 0xBF9C, 0xD4F6, 0xBF9D, 0xD4F7, 0xBF9E, 0xD4F9,
+	0xBF9F, 0xD4FA, 0xBFA0, 0xD4FC, 0xBFA1, 0xC5D0, 0xBFA2, 0xC5D1,	0xBFA3, 0xC5D4, 0xBFA4, 0xC5D8, 0xBFA5, 0xC5E0, 0xBFA6, 0xC5E1,
+	0xBFA7, 0xC5E3, 0xBFA8, 0xC5E5, 0xBFA9, 0xC5EC, 0xBFAA, 0xC5ED,	0xBFAB, 0xC5EE, 0xBFAC, 0xC5F0, 0xBFAD, 0xC5F4, 0xBFAE, 0xC5F6,
+	0xBFAF, 0xC5F7, 0xBFB0, 0xC5FC, 0xBFB1, 0xC5FD, 0xBFB2, 0xC5FE,	0xBFB3, 0xC5FF, 0xBFB4, 0xC600, 0xBFB5, 0xC601, 0xBFB6, 0xC605,
+	0xBFB7, 0xC606, 0xBFB8, 0xC607, 0xBFB9, 0xC608, 0xBFBA, 0xC60C,	0xBFBB, 0xC610, 0xBFBC, 0xC618, 0xBFBD, 0xC619, 0xBFBE, 0xC61B,
+	0xBFBF, 0xC61C, 0xBFC0, 0xC624, 0xBFC1, 0xC625, 0xBFC2, 0xC628,	0xBFC3, 0xC62C, 0xBFC4, 0xC62D, 0xBFC5, 0xC62E, 0xBFC6, 0xC630,
+	0xBFC7, 0xC633, 0xBFC8, 0xC634, 0xBFC9, 0xC635, 0xBFCA, 0xC637,	0xBFCB, 0xC639, 0xBFCC, 0xC63B, 0xBFCD, 0xC640, 0xBFCE, 0xC641,
+	0xBFCF, 0xC644, 0xBFD0, 0xC648, 0xBFD1, 0xC650, 0xBFD2, 0xC651,	0xBFD3, 0xC653, 0xBFD4, 0xC654, 0xBFD5, 0xC655, 0xBFD6, 0xC65C,
+	0xBFD7, 0xC65D, 0xBFD8, 0xC660, 0xBFD9, 0xC66C, 0xBFDA, 0xC66F,	0xBFDB, 0xC671, 0xBFDC, 0xC678, 0xBFDD, 0xC679, 0xBFDE, 0xC67C,
+	0xBFDF, 0xC680, 0xBFE0, 0xC688, 0xBFE1, 0xC689, 0xBFE2, 0xC68B,	0xBFE3, 0xC68D, 0xBFE4, 0xC694, 0xBFE5, 0xC695, 0xBFE6, 0xC698,
+	0xBFE7, 0xC69C, 0xBFE8, 0xC6A4, 0xBFE9, 0xC6A5, 0xBFEA, 0xC6A7,	0xBFEB, 0xC6A9, 0xBFEC, 0xC6B0, 0xBFED, 0xC6B1, 0xBFEE, 0xC6B4,
+	0xBFEF, 0xC6B8, 0xBFF0, 0xC6B9, 0xBFF1, 0xC6BA, 0xBFF2, 0xC6C0,	0xBFF3, 0xC6C1, 0xBFF4, 0xC6C3, 0xBFF5, 0xC6C5, 0xBFF6, 0xC6CC,
+	0xBFF7, 0xC6CD, 0xBFF8, 0xC6D0, 0xBFF9, 0xC6D4, 0xBFFA, 0xC6DC,	0xBFFB, 0xC6DD, 0xBFFC, 0xC6E0, 0xBFFD, 0xC6E1, 0xBFFE, 0xC6E8,
+	0xC041, 0xD4FE, 0xC042, 0xD4FF, 0xC043, 0xD500, 0xC044, 0xD501,	0xC045, 0xD502, 0xC046, 0xD503, 0xC047, 0xD505, 0xC048, 0xD506,
+	0xC049, 0xD507, 0xC04A, 0xD509, 0xC04B, 0xD50A, 0xC04C, 0xD50B,	0xC04D, 0xD50D, 0xC04E, 0xD50E, 0xC04F, 0xD50F, 0xC050, 0xD510,
+	0xC051, 0xD511, 0xC052, 0xD512, 0xC053, 0xD513, 0xC054, 0xD516,	0xC055, 0xD518, 0xC056, 0xD519, 0xC057, 0xD51A, 0xC058, 0xD51B,
+	0xC059, 0xD51C, 0xC05A, 0xD51D, 0xC061, 0xD51E, 0xC062, 0xD51F,	0xC063, 0xD520, 0xC064, 0xD521, 0xC065, 0xD522, 0xC066, 0xD523,
+	0xC067, 0xD524, 0xC068, 0xD525, 0xC069, 0xD526, 0xC06A, 0xD527,	0xC06B, 0xD528, 0xC06C, 0xD529, 0xC06D, 0xD52A, 0xC06E, 0xD52B,
+	0xC06F, 0xD52C, 0xC070, 0xD52D, 0xC071, 0xD52E, 0xC072, 0xD52F,	0xC073, 0xD530, 0xC074, 0xD531, 0xC075, 0xD532, 0xC076, 0xD533,
+	0xC077, 0xD534, 0xC078, 0xD535, 0xC079, 0xD536, 0xC07A, 0xD537,	0xC081, 0xD538, 0xC082, 0xD539, 0xC083, 0xD53A, 0xC084, 0xD53B,
+	0xC085, 0xD53E, 0xC086, 0xD53F, 0xC087, 0xD541, 0xC088, 0xD542,	0xC089, 0xD543, 0xC08A, 0xD545, 0xC08B, 0xD546, 0xC08C, 0xD547,
+	0xC08D, 0xD548, 0xC08E, 0xD549, 0xC08F, 0xD54A, 0xC090, 0xD54B,	0xC091, 0xD54E, 0xC092, 0xD550, 0xC093, 0xD552, 0xC094, 0xD553,
+	0xC095, 0xD554, 0xC096, 0xD555, 0xC097, 0xD556, 0xC098, 0xD557,	0xC099, 0xD55A, 0xC09A, 0xD55B, 0xC09B, 0xD55D, 0xC09C, 0xD55E,
+	0xC09D, 0xD55F, 0xC09E, 0xD561, 0xC09F, 0xD562, 0xC0A0, 0xD563,	0xC0A1, 0xC6E9, 0xC0A2, 0xC6EC, 0xC0A3, 0xC6F0, 0xC0A4, 0xC6F8,
+	0xC0A5, 0xC6F9, 0xC0A6, 0xC6FD, 0xC0A7, 0xC704, 0xC0A8, 0xC705,	0xC0A9, 0xC708, 0xC0AA, 0xC70C, 0xC0AB, 0xC714, 0xC0AC, 0xC715,
+	0xC0AD, 0xC717, 0xC0AE, 0xC719, 0xC0AF, 0xC720, 0xC0B0, 0xC721,	0xC0B1, 0xC724, 0xC0B2, 0xC728, 0xC0B3, 0xC730, 0xC0B4, 0xC731,
+	0xC0B5, 0xC733, 0xC0B6, 0xC735, 0xC0B7, 0xC737, 0xC0B8, 0xC73C,	0xC0B9, 0xC73D, 0xC0BA, 0xC740, 0xC0BB, 0xC744, 0xC0BC, 0xC74A,
+	0xC0BD, 0xC74C, 0xC0BE, 0xC74D, 0xC0BF, 0xC74F, 0xC0C0, 0xC751,	0xC0C1, 0xC752, 0xC0C2, 0xC753, 0xC0C3, 0xC754, 0xC0C4, 0xC755,
+	0xC0C5, 0xC756, 0xC0C6, 0xC757, 0xC0C7, 0xC758, 0xC0C8, 0xC75C,	0xC0C9, 0xC760, 0xC0CA, 0xC768, 0xC0CB, 0xC76B, 0xC0CC, 0xC774,
+	0xC0CD, 0xC775, 0xC0CE, 0xC778, 0xC0CF, 0xC77C, 0xC0D0, 0xC77D,	0xC0D1, 0xC77E, 0xC0D2, 0xC783, 0xC0D3, 0xC784, 0xC0D4, 0xC785,
+	0xC0D5, 0xC787, 0xC0D6, 0xC788, 0xC0D7, 0xC789, 0xC0D8, 0xC78A,	0xC0D9, 0xC78E, 0xC0DA, 0xC790, 0xC0DB, 0xC791, 0xC0DC, 0xC794,
+	0xC0DD, 0xC796, 0xC0DE, 0xC797, 0xC0DF, 0xC798, 0xC0E0, 0xC79A,	0xC0E1, 0xC7A0, 0xC0E2, 0xC7A1, 0xC0E3, 0xC7A3, 0xC0E4, 0xC7A4,
+	0xC0E5, 0xC7A5, 0xC0E6, 0xC7A6, 0xC0E7, 0xC7AC, 0xC0E8, 0xC7AD,	0xC0E9, 0xC7B0, 0xC0EA, 0xC7B4, 0xC0EB, 0xC7BC, 0xC0EC, 0xC7BD,
+	0xC0ED, 0xC7BF, 0xC0EE, 0xC7C0, 0xC0EF, 0xC7C1, 0xC0F0, 0xC7C8,	0xC0F1, 0xC7C9, 0xC0F2, 0xC7CC, 0xC0F3, 0xC7CE, 0xC0F4, 0xC7D0,
+	0xC0F5, 0xC7D8, 0xC0F6, 0xC7DD, 0xC0F7, 0xC7E4, 0xC0F8, 0xC7E8,	0xC0F9, 0xC7EC, 0xC0FA, 0xC800, 0xC0FB, 0xC801, 0xC0FC, 0xC804,
+	0xC0FD, 0xC808, 0xC0FE, 0xC80A, 0xC141, 0xD564, 0xC142, 0xD566,	0xC143, 0xD567, 0xC144, 0xD56A, 0xC145, 0xD56C, 0xC146, 0xD56E,
+	0xC147, 0xD56F, 0xC148, 0xD570, 0xC149, 0xD571, 0xC14A, 0xD572,	0xC14B, 0xD573, 0xC14C, 0xD576, 0xC14D, 0xD577, 0xC14E, 0xD579,
+	0xC14F, 0xD57A, 0xC150, 0xD57B, 0xC151, 0xD57D, 0xC152, 0xD57E,	0xC153, 0xD57F, 0xC154, 0xD580, 0xC155, 0xD581, 0xC156, 0xD582,
+	0xC157, 0xD583, 0xC158, 0xD586, 0xC159, 0xD58A, 0xC15A, 0xD58B,	0xC161, 0xD58C, 0xC162, 0xD58D, 0xC163, 0xD58E, 0xC164, 0xD58F,
+	0xC165, 0xD591, 0xC166, 0xD592, 0xC167, 0xD593, 0xC168, 0xD594,	0xC169, 0xD595, 0xC16A, 0xD596, 0xC16B, 0xD597, 0xC16C, 0xD598,
+	0xC16D, 0xD599, 0xC16E, 0xD59A, 0xC16F, 0xD59B, 0xC170, 0xD59C,	0xC171, 0xD59D, 0xC172, 0xD59E, 0xC173, 0xD59F, 0xC174, 0xD5A0,
+	0xC175, 0xD5A1, 0xC176, 0xD5A2, 0xC177, 0xD5A3, 0xC178, 0xD5A4,	0xC179, 0xD5A6, 0xC17A, 0xD5A7, 0xC181, 0xD5A8, 0xC182, 0xD5A9,
+	0xC183, 0xD5AA, 0xC184, 0xD5AB, 0xC185, 0xD5AC, 0xC186, 0xD5AD,	0xC187, 0xD5AE, 0xC188, 0xD5AF, 0xC189, 0xD5B0, 0xC18A, 0xD5B1,
+	0xC18B, 0xD5B2, 0xC18C, 0xD5B3, 0xC18D, 0xD5B4, 0xC18E, 0xD5B5,	0xC18F, 0xD5B6, 0xC190, 0xD5B7, 0xC191, 0xD5B8, 0xC192, 0xD5B9,
+	0xC193, 0xD5BA, 0xC194, 0xD5BB, 0xC195, 0xD5BC, 0xC196, 0xD5BD,	0xC197, 0xD5BE, 0xC198, 0xD5BF, 0xC199, 0xD5C0, 0xC19A, 0xD5C1,
+	0xC19B, 0xD5C2, 0xC19C, 0xD5C3, 0xC19D, 0xD5C4, 0xC19E, 0xD5C5,	0xC19F, 0xD5C6, 0xC1A0, 0xD5C7, 0xC1A1, 0xC810, 0xC1A2, 0xC811,
+	0xC1A3, 0xC813, 0xC1A4, 0xC815, 0xC1A5, 0xC816, 0xC1A6, 0xC81C,	0xC1A7, 0xC81D, 0xC1A8, 0xC820, 0xC1A9, 0xC824, 0xC1AA, 0xC82C,
+	0xC1AB, 0xC82D, 0xC1AC, 0xC82F, 0xC1AD, 0xC831, 0xC1AE, 0xC838,	0xC1AF, 0xC83C, 0xC1B0, 0xC840, 0xC1B1, 0xC848, 0xC1B2, 0xC849,
+	0xC1B3, 0xC84C, 0xC1B4, 0xC84D, 0xC1B5, 0xC854, 0xC1B6, 0xC870,	0xC1B7, 0xC871, 0xC1B8, 0xC874, 0xC1B9, 0xC878, 0xC1BA, 0xC87A,
+	0xC1BB, 0xC880, 0xC1BC, 0xC881, 0xC1BD, 0xC883, 0xC1BE, 0xC885,	0xC1BF, 0xC886, 0xC1C0, 0xC887, 0xC1C1, 0xC88B, 0xC1C2, 0xC88C,
+	0xC1C3, 0xC88D, 0xC1C4, 0xC894, 0xC1C5, 0xC89D, 0xC1C6, 0xC89F,	0xC1C7, 0xC8A1, 0xC1C8, 0xC8A8, 0xC1C9, 0xC8BC, 0xC1CA, 0xC8BD,
+	0xC1CB, 0xC8C4, 0xC1CC, 0xC8C8, 0xC1CD, 0xC8CC, 0xC1CE, 0xC8D4,	0xC1CF, 0xC8D5, 0xC1D0, 0xC8D7, 0xC1D1, 0xC8D9, 0xC1D2, 0xC8E0,
+	0xC1D3, 0xC8E1, 0xC1D4, 0xC8E4, 0xC1D5, 0xC8F5, 0xC1D6, 0xC8FC,	0xC1D7, 0xC8FD, 0xC1D8, 0xC900, 0xC1D9, 0xC904, 0xC1DA, 0xC905,
+	0xC1DB, 0xC906, 0xC1DC, 0xC90C, 0xC1DD, 0xC90D, 0xC1DE, 0xC90F,	0xC1DF, 0xC911, 0xC1E0, 0xC918, 0xC1E1, 0xC92C, 0xC1E2, 0xC934,
+	0xC1E3, 0xC950, 0xC1E4, 0xC951, 0xC1E5, 0xC954, 0xC1E6, 0xC958,	0xC1E7, 0xC960, 0xC1E8, 0xC961, 0xC1E9, 0xC963, 0xC1EA, 0xC96C,
+	0xC1EB, 0xC970, 0xC1EC, 0xC974, 0xC1ED, 0xC97C, 0xC1EE, 0xC988,	0xC1EF, 0xC989, 0xC1F0, 0xC98C, 0xC1F1, 0xC990, 0xC1F2, 0xC998,
+	0xC1F3, 0xC999, 0xC1F4, 0xC99B, 0xC1F5, 0xC99D, 0xC1F6, 0xC9C0,	0xC1F7, 0xC9C1, 0xC1F8, 0xC9C4, 0xC1F9, 0xC9C7, 0xC1FA, 0xC9C8,
+	0xC1FB, 0xC9CA, 0xC1FC, 0xC9D0, 0xC1FD, 0xC9D1, 0xC1FE, 0xC9D3,	0xC241, 0xD5CA, 0xC242, 0xD5CB, 0xC243, 0xD5CD, 0xC244, 0xD5CE,
+	0xC245, 0xD5CF, 0xC246, 0xD5D1, 0xC247, 0xD5D3, 0xC248, 0xD5D4,	0xC249, 0xD5D5, 0xC24A, 0xD5D6, 0xC24B, 0xD5D7, 0xC24C, 0xD5DA,
+	0xC24D, 0xD5DC, 0xC24E, 0xD5DE, 0xC24F, 0xD5DF, 0xC250, 0xD5E0,	0xC251, 0xD5E1, 0xC252, 0xD5E2, 0xC253, 0xD5E3, 0xC254, 0xD5E6,
+	0xC255, 0xD5E7, 0xC256, 0xD5E9, 0xC257, 0xD5EA, 0xC258, 0xD5EB,	0xC259, 0xD5ED, 0xC25A, 0xD5EE, 0xC261, 0xD5EF, 0xC262, 0xD5F0,
+	0xC263, 0xD5F1, 0xC264, 0xD5F2, 0xC265, 0xD5F3, 0xC266, 0xD5F6,	0xC267, 0xD5F8, 0xC268, 0xD5FA, 0xC269, 0xD5FB, 0xC26A, 0xD5FC,
+	0xC26B, 0xD5FD, 0xC26C, 0xD5FE, 0xC26D, 0xD5FF, 0xC26E, 0xD602,	0xC26F, 0xD603, 0xC270, 0xD605, 0xC271, 0xD606, 0xC272, 0xD607,
+	0xC273, 0xD609, 0xC274, 0xD60A, 0xC275, 0xD60B, 0xC276, 0xD60C,	0xC277, 0xD60D, 0xC278, 0xD60E, 0xC279, 0xD60F, 0xC27A, 0xD612,
+	0xC281, 0xD616, 0xC282, 0xD617, 0xC283, 0xD618, 0xC284, 0xD619,	0xC285, 0xD61A, 0xC286, 0xD61B, 0xC287, 0xD61D, 0xC288, 0xD61E,
+	0xC289, 0xD61F, 0xC28A, 0xD621, 0xC28B, 0xD622, 0xC28C, 0xD623,	0xC28D, 0xD625, 0xC28E, 0xD626, 0xC28F, 0xD627, 0xC290, 0xD628,
+	0xC291, 0xD629, 0xC292, 0xD62A, 0xC293, 0xD62B, 0xC294, 0xD62C,	0xC295, 0xD62E, 0xC296, 0xD62F, 0xC297, 0xD630, 0xC298, 0xD631,
+	0xC299, 0xD632, 0xC29A, 0xD633, 0xC29B, 0xD634, 0xC29C, 0xD635,	0xC29D, 0xD636, 0xC29E, 0xD637, 0xC29F, 0xD63A, 0xC2A0, 0xD63B,
+	0xC2A1, 0xC9D5, 0xC2A2, 0xC9D6, 0xC2A3, 0xC9D9, 0xC2A4, 0xC9DA,	0xC2A5, 0xC9DC, 0xC2A6, 0xC9DD, 0xC2A7, 0xC9E0, 0xC2A8, 0xC9E2,
+	0xC2A9, 0xC9E4, 0xC2AA, 0xC9E7, 0xC2AB, 0xC9EC, 0xC2AC, 0xC9ED,	0xC2AD, 0xC9EF, 0xC2AE, 0xC9F0, 0xC2AF, 0xC9F1, 0xC2B0, 0xC9F8,
+	0xC2B1, 0xC9F9, 0xC2B2, 0xC9FC, 0xC2B3, 0xCA00, 0xC2B4, 0xCA08,	0xC2B5, 0xCA09, 0xC2B6, 0xCA0B, 0xC2B7, 0xCA0C, 0xC2B8, 0xCA0D,
+	0xC2B9, 0xCA14, 0xC2BA, 0xCA18, 0xC2BB, 0xCA29, 0xC2BC, 0xCA4C,	0xC2BD, 0xCA4D, 0xC2BE, 0xCA50, 0xC2BF, 0xCA54, 0xC2C0, 0xCA5C,
+	0xC2C1, 0xCA5D, 0xC2C2, 0xCA5F, 0xC2C3, 0xCA60, 0xC2C4, 0xCA61,	0xC2C5, 0xCA68, 0xC2C6, 0xCA7D, 0xC2C7, 0xCA84, 0xC2C8, 0xCA98,
+	0xC2C9, 0xCABC, 0xC2CA, 0xCABD, 0xC2CB, 0xCAC0, 0xC2CC, 0xCAC4,	0xC2CD, 0xCACC, 0xC2CE, 0xCACD, 0xC2CF, 0xCACF, 0xC2D0, 0xCAD1,
+	0xC2D1, 0xCAD3, 0xC2D2, 0xCAD8, 0xC2D3, 0xCAD9, 0xC2D4, 0xCAE0,	0xC2D5, 0xCAEC, 0xC2D6, 0xCAF4, 0xC2D7, 0xCB08, 0xC2D8, 0xCB10,
+	0xC2D9, 0xCB14, 0xC2DA, 0xCB18, 0xC2DB, 0xCB20, 0xC2DC, 0xCB21,	0xC2DD, 0xCB41, 0xC2DE, 0xCB48, 0xC2DF, 0xCB49, 0xC2E0, 0xCB4C,
+	0xC2E1, 0xCB50, 0xC2E2, 0xCB58, 0xC2E3, 0xCB59, 0xC2E4, 0xCB5D,	0xC2E5, 0xCB64, 0xC2E6, 0xCB78, 0xC2E7, 0xCB79, 0xC2E8, 0xCB9C,
+	0xC2E9, 0xCBB8, 0xC2EA, 0xCBD4, 0xC2EB, 0xCBE4, 0xC2EC, 0xCBE7,	0xC2ED, 0xCBE9, 0xC2EE, 0xCC0C, 0xC2EF, 0xCC0D, 0xC2F0, 0xCC10,
+	0xC2F1, 0xCC14, 0xC2F2, 0xCC1C, 0xC2F3, 0xCC1D, 0xC2F4, 0xCC21,	0xC2F5, 0xCC22, 0xC2F6, 0xCC27, 0xC2F7, 0xCC28, 0xC2F8, 0xCC29,
+	0xC2F9, 0xCC2C, 0xC2FA, 0xCC2E, 0xC2FB, 0xCC30, 0xC2FC, 0xCC38,	0xC2FD, 0xCC39, 0xC2FE, 0xCC3B, 0xC341, 0xD63D, 0xC342, 0xD63E,
+	0xC343, 0xD63F, 0xC344, 0xD641, 0xC345, 0xD642, 0xC346, 0xD643,	0xC347, 0xD644, 0xC348, 0xD646, 0xC349, 0xD647, 0xC34A, 0xD64A,
+	0xC34B, 0xD64C, 0xC34C, 0xD64E, 0xC34D, 0xD64F, 0xC34E, 0xD650,	0xC34F, 0xD652, 0xC350, 0xD653, 0xC351, 0xD656, 0xC352, 0xD657,
+	0xC353, 0xD659, 0xC354, 0xD65A, 0xC355, 0xD65B, 0xC356, 0xD65D,	0xC357, 0xD65E, 0xC358, 0xD65F, 0xC359, 0xD660, 0xC35A, 0xD661,
+	0xC361, 0xD662, 0xC362, 0xD663, 0xC363, 0xD664, 0xC364, 0xD665,	0xC365, 0xD666, 0xC366, 0xD668, 0xC367, 0xD66A, 0xC368, 0xD66B,
+	0xC369, 0xD66C, 0xC36A, 0xD66D, 0xC36B, 0xD66E, 0xC36C, 0xD66F,	0xC36D, 0xD672, 0xC36E, 0xD673, 0xC36F, 0xD675, 0xC370, 0xD676,
+	0xC371, 0xD677, 0xC372, 0xD678, 0xC373, 0xD679, 0xC374, 0xD67A,	0xC375, 0xD67B, 0xC376, 0xD67C, 0xC377, 0xD67D, 0xC378, 0xD67E,
+	0xC379, 0xD67F, 0xC37A, 0xD680, 0xC381, 0xD681, 0xC382, 0xD682,	0xC383, 0xD684, 0xC384, 0xD686, 0xC385, 0xD687, 0xC386, 0xD688,
+	0xC387, 0xD689, 0xC388, 0xD68A, 0xC389, 0xD68B, 0xC38A, 0xD68E,	0xC38B, 0xD68F, 0xC38C, 0xD691, 0xC38D, 0xD692, 0xC38E, 0xD693,
+	0xC38F, 0xD695, 0xC390, 0xD696, 0xC391, 0xD697, 0xC392, 0xD698,	0xC393, 0xD699, 0xC394, 0xD69A, 0xC395, 0xD69B, 0xC396, 0xD69C,
+	0xC397, 0xD69E, 0xC398, 0xD6A0, 0xC399, 0xD6A2, 0xC39A, 0xD6A3,	0xC39B, 0xD6A4, 0xC39C, 0xD6A5, 0xC39D, 0xD6A6, 0xC39E, 0xD6A7,
+	0xC39F, 0xD6A9, 0xC3A0, 0xD6AA, 0xC3A1, 0xCC3C, 0xC3A2, 0xCC3D,	0xC3A3, 0xCC3E, 0xC3A4, 0xCC44, 0xC3A5, 0xCC45, 0xC3A6, 0xCC48,
+	0xC3A7, 0xCC4C, 0xC3A8, 0xCC54, 0xC3A9, 0xCC55, 0xC3AA, 0xCC57,	0xC3AB, 0xCC58, 0xC3AC, 0xCC59, 0xC3AD, 0xCC60, 0xC3AE, 0xCC64,
+	0xC3AF, 0xCC66, 0xC3B0, 0xCC68, 0xC3B1, 0xCC70, 0xC3B2, 0xCC75,	0xC3B3, 0xCC98, 0xC3B4, 0xCC99, 0xC3B5, 0xCC9C, 0xC3B6, 0xCCA0,
+	0xC3B7, 0xCCA8, 0xC3B8, 0xCCA9, 0xC3B9, 0xCCAB, 0xC3BA, 0xCCAC,	0xC3BB, 0xCCAD, 0xC3BC, 0xCCB4, 0xC3BD, 0xCCB5, 0xC3BE, 0xCCB8,
+	0xC3BF, 0xCCBC, 0xC3C0, 0xCCC4, 0xC3C1, 0xCCC5, 0xC3C2, 0xCCC7,	0xC3C3, 0xCCC9, 0xC3C4, 0xCCD0, 0xC3C5, 0xCCD4, 0xC3C6, 0xCCE4,
+	0xC3C7, 0xCCEC, 0xC3C8, 0xCCF0, 0xC3C9, 0xCD01, 0xC3CA, 0xCD08,	0xC3CB, 0xCD09, 0xC3CC, 0xCD0C, 0xC3CD, 0xCD10, 0xC3CE, 0xCD18,
+	0xC3CF, 0xCD19, 0xC3D0, 0xCD1B, 0xC3D1, 0xCD1D, 0xC3D2, 0xCD24,	0xC3D3, 0xCD28, 0xC3D4, 0xCD2C, 0xC3D5, 0xCD39, 0xC3D6, 0xCD5C,
+	0xC3D7, 0xCD60, 0xC3D8, 0xCD64, 0xC3D9, 0xCD6C, 0xC3DA, 0xCD6D,	0xC3DB, 0xCD6F, 0xC3DC, 0xCD71, 0xC3DD, 0xCD78, 0xC3DE, 0xCD88,
+	0xC3DF, 0xCD94, 0xC3E0, 0xCD95, 0xC3E1, 0xCD98, 0xC3E2, 0xCD9C,	0xC3E3, 0xCDA4, 0xC3E4, 0xCDA5, 0xC3E5, 0xCDA7, 0xC3E6, 0xCDA9,
+	0xC3E7, 0xCDB0, 0xC3E8, 0xCDC4, 0xC3E9, 0xCDCC, 0xC3EA, 0xCDD0,	0xC3EB, 0xCDE8, 0xC3EC, 0xCDEC, 0xC3ED, 0xCDF0, 0xC3EE, 0xCDF8,
+	0xC3EF, 0xCDF9, 0xC3F0, 0xCDFB, 0xC3F1, 0xCDFD, 0xC3F2, 0xCE04,	0xC3F3, 0xCE08, 0xC3F4, 0xCE0C, 0xC3F5, 0xCE14, 0xC3F6, 0xCE19,
+	0xC3F7, 0xCE20, 0xC3F8, 0xCE21, 0xC3F9, 0xCE24, 0xC3FA, 0xCE28,	0xC3FB, 0xCE30, 0xC3FC, 0xCE31, 0xC3FD, 0xCE33, 0xC3FE, 0xCE35,
+	0xC441, 0xD6AB, 0xC442, 0xD6AD, 0xC443, 0xD6AE, 0xC444, 0xD6AF,	0xC445, 0xD6B1, 0xC446, 0xD6B2, 0xC447, 0xD6B3, 0xC448, 0xD6B4,
+	0xC449, 0xD6B5, 0xC44A, 0xD6B6, 0xC44B, 0xD6B7, 0xC44C, 0xD6B8,	0xC44D, 0xD6BA, 0xC44E, 0xD6BC, 0xC44F, 0xD6BD, 0xC450, 0xD6BE,
+	0xC451, 0xD6BF, 0xC452, 0xD6C0, 0xC453, 0xD6C1, 0xC454, 0xD6C2,	0xC455, 0xD6C3, 0xC456, 0xD6C6, 0xC457, 0xD6C7, 0xC458, 0xD6C9,
+	0xC459, 0xD6CA, 0xC45A, 0xD6CB, 0xC461, 0xD6CD, 0xC462, 0xD6CE,	0xC463, 0xD6CF, 0xC464, 0xD6D0, 0xC465, 0xD6D2, 0xC466, 0xD6D3,
+	0xC467, 0xD6D5, 0xC468, 0xD6D6, 0xC469, 0xD6D8, 0xC46A, 0xD6DA,	0xC46B, 0xD6DB, 0xC46C, 0xD6DC, 0xC46D, 0xD6DD, 0xC46E, 0xD6DE,
+	0xC46F, 0xD6DF, 0xC470, 0xD6E1, 0xC471, 0xD6E2, 0xC472, 0xD6E3,	0xC473, 0xD6E5, 0xC474, 0xD6E6, 0xC475, 0xD6E7, 0xC476, 0xD6E9,
+	0xC477, 0xD6EA, 0xC478, 0xD6EB, 0xC479, 0xD6EC, 0xC47A, 0xD6ED,	0xC481, 0xD6EE, 0xC482, 0xD6EF, 0xC483, 0xD6F1, 0xC484, 0xD6F2,
+	0xC485, 0xD6F3, 0xC486, 0xD6F4, 0xC487, 0xD6F6, 0xC488, 0xD6F7,	0xC489, 0xD6F8, 0xC48A, 0xD6F9, 0xC48B, 0xD6FA, 0xC48C, 0xD6FB,
+	0xC48D, 0xD6FE, 0xC48E, 0xD6FF, 0xC48F, 0xD701, 0xC490, 0xD702,	0xC491, 0xD703, 0xC492, 0xD705, 0xC493, 0xD706, 0xC494, 0xD707,
+	0xC495, 0xD708, 0xC496, 0xD709, 0xC497, 0xD70A, 0xC498, 0xD70B,	0xC499, 0xD70C, 0xC49A, 0xD70D, 0xC49B, 0xD70E, 0xC49C, 0xD70F,
+	0xC49D, 0xD710, 0xC49E, 0xD712, 0xC49F, 0xD713, 0xC4A0, 0xD714,	0xC4A1, 0xCE58, 0xC4A2, 0xCE59, 0xC4A3, 0xCE5C, 0xC4A4, 0xCE5F,
+	0xC4A5, 0xCE60, 0xC4A6, 0xCE61, 0xC4A7, 0xCE68, 0xC4A8, 0xCE69,	0xC4A9, 0xCE6B, 0xC4AA, 0xCE6D, 0xC4AB, 0xCE74, 0xC4AC, 0xCE75,
+	0xC4AD, 0xCE78, 0xC4AE, 0xCE7C, 0xC4AF, 0xCE84, 0xC4B0, 0xCE85,	0xC4B1, 0xCE87, 0xC4B2, 0xCE89, 0xC4B3, 0xCE90, 0xC4B4, 0xCE91,
+	0xC4B5, 0xCE94, 0xC4B6, 0xCE98, 0xC4B7, 0xCEA0, 0xC4B8, 0xCEA1,	0xC4B9, 0xCEA3, 0xC4BA, 0xCEA4, 0xC4BB, 0xCEA5, 0xC4BC, 0xCEAC,
+	0xC4BD, 0xCEAD, 0xC4BE, 0xCEC1, 0xC4BF, 0xCEE4, 0xC4C0, 0xCEE5,	0xC4C1, 0xCEE8, 0xC4C2, 0xCEEB, 0xC4C3, 0xCEEC, 0xC4C4, 0xCEF4,
+	0xC4C5, 0xCEF5, 0xC4C6, 0xCEF7, 0xC4C7, 0xCEF8, 0xC4C8, 0xCEF9,	0xC4C9, 0xCF00, 0xC4CA, 0xCF01, 0xC4CB, 0xCF04, 0xC4CC, 0xCF08,
+	0xC4CD, 0xCF10, 0xC4CE, 0xCF11, 0xC4CF, 0xCF13, 0xC4D0, 0xCF15,	0xC4D1, 0xCF1C, 0xC4D2, 0xCF20, 0xC4D3, 0xCF24, 0xC4D4, 0xCF2C,
+	0xC4D5, 0xCF2D, 0xC4D6, 0xCF2F, 0xC4D7, 0xCF30, 0xC4D8, 0xCF31,	0xC4D9, 0xCF38, 0xC4DA, 0xCF54, 0xC4DB, 0xCF55, 0xC4DC, 0xCF58,
+	0xC4DD, 0xCF5C, 0xC4DE, 0xCF64, 0xC4DF, 0xCF65, 0xC4E0, 0xCF67,	0xC4E1, 0xCF69, 0xC4E2, 0xCF70, 0xC4E3, 0xCF71, 0xC4E4, 0xCF74,
+	0xC4E5, 0xCF78, 0xC4E6, 0xCF80, 0xC4E7, 0xCF85, 0xC4E8, 0xCF8C,	0xC4E9, 0xCFA1, 0xC4EA, 0xCFA8, 0xC4EB, 0xCFB0, 0xC4EC, 0xCFC4,
+	0xC4ED, 0xCFE0, 0xC4EE, 0xCFE1, 0xC4EF, 0xCFE4, 0xC4F0, 0xCFE8,	0xC4F1, 0xCFF0, 0xC4F2, 0xCFF1, 0xC4F3, 0xCFF3, 0xC4F4, 0xCFF5,
+	0xC4F5, 0xCFFC, 0xC4F6, 0xD000, 0xC4F7, 0xD004, 0xC4F8, 0xD011,	0xC4F9, 0xD018, 0xC4FA, 0xD02D, 0xC4FB, 0xD034, 0xC4FC, 0xD035,
+	0xC4FD, 0xD038, 0xC4FE, 0xD03C, 0xC541, 0xD715, 0xC542, 0xD716,	0xC543, 0xD717, 0xC544, 0xD71A, 0xC545, 0xD71B, 0xC546, 0xD71D,
+	0xC547, 0xD71E, 0xC548, 0xD71F, 0xC549, 0xD721, 0xC54A, 0xD722,	0xC54B, 0xD723, 0xC54C, 0xD724, 0xC54D, 0xD725, 0xC54E, 0xD726,
+	0xC54F, 0xD727, 0xC550, 0xD72A, 0xC551, 0xD72C, 0xC552, 0xD72E,	0xC553, 0xD72F, 0xC554, 0xD730, 0xC555, 0xD731, 0xC556, 0xD732,
+	0xC557, 0xD733, 0xC558, 0xD736, 0xC559, 0xD737, 0xC55A, 0xD739,	0xC561, 0xD73A, 0xC562, 0xD73B, 0xC563, 0xD73D, 0xC564, 0xD73E,
+	0xC565, 0xD73F, 0xC566, 0xD740, 0xC567, 0xD741, 0xC568, 0xD742,	0xC569, 0xD743, 0xC56A, 0xD745, 0xC56B, 0xD746, 0xC56C, 0xD748,
+	0xC56D, 0xD74A, 0xC56E, 0xD74B, 0xC56F, 0xD74C, 0xC570, 0xD74D,	0xC571, 0xD74E, 0xC572, 0xD74F, 0xC573, 0xD752, 0xC574, 0xD753,
+	0xC575, 0xD755, 0xC576, 0xD75A, 0xC577, 0xD75B, 0xC578, 0xD75C,	0xC579, 0xD75D, 0xC57A, 0xD75E, 0xC581, 0xD75F, 0xC582, 0xD762,
+	0xC583, 0xD764, 0xC584, 0xD766, 0xC585, 0xD767, 0xC586, 0xD768,	0xC587, 0xD76A, 0xC588, 0xD76B, 0xC589, 0xD76D, 0xC58A, 0xD76E,
+	0xC58B, 0xD76F, 0xC58C, 0xD771, 0xC58D, 0xD772, 0xC58E, 0xD773,	0xC58F, 0xD775, 0xC590, 0xD776, 0xC591, 0xD777, 0xC592, 0xD778,
+	0xC593, 0xD779, 0xC594, 0xD77A, 0xC595, 0xD77B, 0xC596, 0xD77E,	0xC597, 0xD77F, 0xC598, 0xD780, 0xC599, 0xD782, 0xC59A, 0xD783,
+	0xC59B, 0xD784, 0xC59C, 0xD785, 0xC59D, 0xD786, 0xC59E, 0xD787,	0xC59F, 0xD78A, 0xC5A0, 0xD78B, 0xC5A1, 0xD044, 0xC5A2, 0xD045,
+	0xC5A3, 0xD047, 0xC5A4, 0xD049, 0xC5A5, 0xD050, 0xC5A6, 0xD054,	0xC5A7, 0xD058, 0xC5A8, 0xD060, 0xC5A9, 0xD06C, 0xC5AA, 0xD06D,
+	0xC5AB, 0xD070, 0xC5AC, 0xD074, 0xC5AD, 0xD07C, 0xC5AE, 0xD07D,	0xC5AF, 0xD081, 0xC5B0, 0xD0A4, 0xC5B1, 0xD0A5, 0xC5B2, 0xD0A8,
+	0xC5B3, 0xD0AC, 0xC5B4, 0xD0B4, 0xC5B5, 0xD0B5, 0xC5B6, 0xD0B7,	0xC5B7, 0xD0B9, 0xC5B8, 0xD0C0, 0xC5B9, 0xD0C1, 0xC5BA, 0xD0C4,
+	0xC5BB, 0xD0C8, 0xC5BC, 0xD0C9, 0xC5BD, 0xD0D0, 0xC5BE, 0xD0D1,	0xC5BF, 0xD0D3, 0xC5C0, 0xD0D4, 0xC5C1, 0xD0D5, 0xC5C2, 0xD0DC,
+	0xC5C3, 0xD0DD, 0xC5C4, 0xD0E0, 0xC5C5, 0xD0E4, 0xC5C6, 0xD0EC,	0xC5C7, 0xD0ED, 0xC5C8, 0xD0EF, 0xC5C9, 0xD0F0, 0xC5CA, 0xD0F1,
+	0xC5CB, 0xD0F8, 0xC5CC, 0xD10D, 0xC5CD, 0xD130, 0xC5CE, 0xD131,	0xC5CF, 0xD134, 0xC5D0, 0xD138, 0xC5D1, 0xD13A, 0xC5D2, 0xD140,
+	0xC5D3, 0xD141, 0xC5D4, 0xD143, 0xC5D5, 0xD144, 0xC5D6, 0xD145,	0xC5D7, 0xD14C, 0xC5D8, 0xD14D, 0xC5D9, 0xD150, 0xC5DA, 0xD154,
+	0xC5DB, 0xD15C, 0xC5DC, 0xD15D, 0xC5DD, 0xD15F, 0xC5DE, 0xD161,	0xC5DF, 0xD168, 0xC5E0, 0xD16C, 0xC5E1, 0xD17C, 0xC5E2, 0xD184,
+	0xC5E3, 0xD188, 0xC5E4, 0xD1A0, 0xC5E5, 0xD1A1, 0xC5E6, 0xD1A4,	0xC5E7, 0xD1A8, 0xC5E8, 0xD1B0, 0xC5E9, 0xD1B1, 0xC5EA, 0xD1B3,
+	0xC5EB, 0xD1B5, 0xC5EC, 0xD1BA, 0xC5ED, 0xD1BC, 0xC5EE, 0xD1C0,	0xC5EF, 0xD1D8, 0xC5F0, 0xD1F4, 0xC5F1, 0xD1F8, 0xC5F2, 0xD207,
+	0xC5F3, 0xD209, 0xC5F4, 0xD210, 0xC5F5, 0xD22C, 0xC5F6, 0xD22D,	0xC5F7, 0xD230, 0xC5F8, 0xD234, 0xC5F9, 0xD23C, 0xC5FA, 0xD23D,
+	0xC5FB, 0xD23F, 0xC5FC, 0xD241, 0xC5FD, 0xD248, 0xC5FE, 0xD25C,	0xC641, 0xD78D, 0xC642, 0xD78E, 0xC643, 0xD78F, 0xC644, 0xD791,
+	0xC645, 0xD792, 0xC646, 0xD793, 0xC647, 0xD794, 0xC648, 0xD795,	0xC649, 0xD796, 0xC64A, 0xD797, 0xC64B, 0xD79A, 0xC64C, 0xD79C,
+	0xC64D, 0xD79E, 0xC64E, 0xD79F, 0xC64F, 0xD7A0, 0xC650, 0xD7A1,	0xC651, 0xD7A2, 0xC652, 0xD7A3, 0xC6A1, 0xD264, 0xC6A2, 0xD280,
+	0xC6A3, 0xD281, 0xC6A4, 0xD284, 0xC6A5, 0xD288, 0xC6A6, 0xD290,	0xC6A7, 0xD291, 0xC6A8, 0xD295, 0xC6A9, 0xD29C, 0xC6AA, 0xD2A0,
+	0xC6AB, 0xD2A4, 0xC6AC, 0xD2AC, 0xC6AD, 0xD2B1, 0xC6AE, 0xD2B8,	0xC6AF, 0xD2B9, 0xC6B0, 0xD2BC, 0xC6B1, 0xD2BF, 0xC6B2, 0xD2C0,
+	0xC6B3, 0xD2C2, 0xC6B4, 0xD2C8, 0xC6B5, 0xD2C9, 0xC6B6, 0xD2CB,	0xC6B7, 0xD2D4, 0xC6B8, 0xD2D8, 0xC6B9, 0xD2DC, 0xC6BA, 0xD2E4,
+	0xC6BB, 0xD2E5, 0xC6BC, 0xD2F0, 0xC6BD, 0xD2F1, 0xC6BE, 0xD2F4,	0xC6BF, 0xD2F8, 0xC6C0, 0xD300, 0xC6C1, 0xD301, 0xC6C2, 0xD303,
+	0xC6C3, 0xD305, 0xC6C4, 0xD30C, 0xC6C5, 0xD30D, 0xC6C6, 0xD30E,	0xC6C7, 0xD310, 0xC6C8, 0xD314, 0xC6C9, 0xD316, 0xC6CA, 0xD31C,
+	0xC6CB, 0xD31D, 0xC6CC, 0xD31F, 0xC6CD, 0xD320, 0xC6CE, 0xD321,	0xC6CF, 0xD325, 0xC6D0, 0xD328, 0xC6D1, 0xD329, 0xC6D2, 0xD32C,
+	0xC6D3, 0xD330, 0xC6D4, 0xD338, 0xC6D5, 0xD339, 0xC6D6, 0xD33B,	0xC6D7, 0xD33C, 0xC6D8, 0xD33D, 0xC6D9, 0xD344, 0xC6DA, 0xD345,
+	0xC6DB, 0xD37C, 0xC6DC, 0xD37D, 0xC6DD, 0xD380, 0xC6DE, 0xD384,	0xC6DF, 0xD38C, 0xC6E0, 0xD38D, 0xC6E1, 0xD38F, 0xC6E2, 0xD390,
+	0xC6E3, 0xD391, 0xC6E4, 0xD398, 0xC6E5, 0xD399, 0xC6E6, 0xD39C,	0xC6E7, 0xD3A0, 0xC6E8, 0xD3A8, 0xC6E9, 0xD3A9, 0xC6EA, 0xD3AB,
+	0xC6EB, 0xD3AD, 0xC6EC, 0xD3B4, 0xC6ED, 0xD3B8, 0xC6EE, 0xD3BC,	0xC6EF, 0xD3C4, 0xC6F0, 0xD3C5, 0xC6F1, 0xD3C8, 0xC6F2, 0xD3C9,
+	0xC6F3, 0xD3D0, 0xC6F4, 0xD3D8, 0xC6F5, 0xD3E1, 0xC6F6, 0xD3E3,	0xC6F7, 0xD3EC, 0xC6F8, 0xD3ED, 0xC6F9, 0xD3F0, 0xC6FA, 0xD3F4,
+	0xC6FB, 0xD3FC, 0xC6FC, 0xD3FD, 0xC6FD, 0xD3FF, 0xC6FE, 0xD401,	0xC7A1, 0xD408, 0xC7A2, 0xD41D, 0xC7A3, 0xD440, 0xC7A4, 0xD444,
+	0xC7A5, 0xD45C, 0xC7A6, 0xD460, 0xC7A7, 0xD464, 0xC7A8, 0xD46D,	0xC7A9, 0xD46F, 0xC7AA, 0xD478, 0xC7AB, 0xD479, 0xC7AC, 0xD47C,
+	0xC7AD, 0xD47F, 0xC7AE, 0xD480, 0xC7AF, 0xD482, 0xC7B0, 0xD488,	0xC7B1, 0xD489, 0xC7B2, 0xD48B, 0xC7B3, 0xD48D, 0xC7B4, 0xD494,
+	0xC7B5, 0xD4A9, 0xC7B6, 0xD4CC, 0xC7B7, 0xD4D0, 0xC7B8, 0xD4D4,	0xC7B9, 0xD4DC, 0xC7BA, 0xD4DF, 0xC7BB, 0xD4E8, 0xC7BC, 0xD4EC,
+	0xC7BD, 0xD4F0, 0xC7BE, 0xD4F8, 0xC7BF, 0xD4FB, 0xC7C0, 0xD4FD,	0xC7C1, 0xD504, 0xC7C2, 0xD508, 0xC7C3, 0xD50C, 0xC7C4, 0xD514,
+	0xC7C5, 0xD515, 0xC7C6, 0xD517, 0xC7C7, 0xD53C, 0xC7C8, 0xD53D,	0xC7C9, 0xD540, 0xC7CA, 0xD544, 0xC7CB, 0xD54C, 0xC7CC, 0xD54D,
+	0xC7CD, 0xD54F, 0xC7CE, 0xD551, 0xC7CF, 0xD558, 0xC7D0, 0xD559,	0xC7D1, 0xD55C, 0xC7D2, 0xD560, 0xC7D3, 0xD565, 0xC7D4, 0xD568,
+	0xC7D5, 0xD569, 0xC7D6, 0xD56B, 0xC7D7, 0xD56D, 0xC7D8, 0xD574,	0xC7D9, 0xD575, 0xC7DA, 0xD578, 0xC7DB, 0xD57C, 0xC7DC, 0xD584,
+	0xC7DD, 0xD585, 0xC7DE, 0xD587, 0xC7DF, 0xD588, 0xC7E0, 0xD589,	0xC7E1, 0xD590, 0xC7E2, 0xD5A5, 0xC7E3, 0xD5C8, 0xC7E4, 0xD5C9,
+	0xC7E5, 0xD5CC, 0xC7E6, 0xD5D0, 0xC7E7, 0xD5D2, 0xC7E8, 0xD5D8,	0xC7E9, 0xD5D9, 0xC7EA, 0xD5DB, 0xC7EB, 0xD5DD, 0xC7EC, 0xD5E4,
+	0xC7ED, 0xD5E5, 0xC7EE, 0xD5E8, 0xC7EF, 0xD5EC, 0xC7F0, 0xD5F4,	0xC7F1, 0xD5F5, 0xC7F2, 0xD5F7, 0xC7F3, 0xD5F9, 0xC7F4, 0xD600,
+	0xC7F5, 0xD601, 0xC7F6, 0xD604, 0xC7F7, 0xD608, 0xC7F8, 0xD610,	0xC7F9, 0xD611, 0xC7FA, 0xD613, 0xC7FB, 0xD614, 0xC7FC, 0xD615,
+	0xC7FD, 0xD61C, 0xC7FE, 0xD620, 0xC8A1, 0xD624, 0xC8A2, 0xD62D,	0xC8A3, 0xD638, 0xC8A4, 0xD639, 0xC8A5, 0xD63C, 0xC8A6, 0xD640,
+	0xC8A7, 0xD645, 0xC8A8, 0xD648, 0xC8A9, 0xD649, 0xC8AA, 0xD64B,	0xC8AB, 0xD64D, 0xC8AC, 0xD651, 0xC8AD, 0xD654, 0xC8AE, 0xD655,
+	0xC8AF, 0xD658, 0xC8B0, 0xD65C, 0xC8B1, 0xD667, 0xC8B2, 0xD669,	0xC8B3, 0xD670, 0xC8B4, 0xD671, 0xC8B5, 0xD674, 0xC8B6, 0xD683,
+	0xC8B7, 0xD685, 0xC8B8, 0xD68C, 0xC8B9, 0xD68D, 0xC8BA, 0xD690,	0xC8BB, 0xD694, 0xC8BC, 0xD69D, 0xC8BD, 0xD69F, 0xC8BE, 0xD6A1,
+	0xC8BF, 0xD6A8, 0xC8C0, 0xD6AC, 0xC8C1, 0xD6B0, 0xC8C2, 0xD6B9,	0xC8C3, 0xD6BB, 0xC8C4, 0xD6C4, 0xC8C5, 0xD6C5, 0xC8C6, 0xD6C8,
+	0xC8C7, 0xD6CC, 0xC8C8, 0xD6D1, 0xC8C9, 0xD6D4, 0xC8CA, 0xD6D7,	0xC8CB, 0xD6D9, 0xC8CC, 0xD6E0, 0xC8CD, 0xD6E4, 0xC8CE, 0xD6E8,
+	0xC8CF, 0xD6F0, 0xC8D0, 0xD6F5, 0xC8D1, 0xD6FC, 0xC8D2, 0xD6FD,	0xC8D3, 0xD700, 0xC8D4, 0xD704, 0xC8D5, 0xD711, 0xC8D6, 0xD718,
+	0xC8D7, 0xD719, 0xC8D8, 0xD71C, 0xC8D9, 0xD720, 0xC8DA, 0xD728,	0xC8DB, 0xD729, 0xC8DC, 0xD72B, 0xC8DD, 0xD72D, 0xC8DE, 0xD734,
+	0xC8DF, 0xD735, 0xC8E0, 0xD738, 0xC8E1, 0xD73C, 0xC8E2, 0xD744,	0xC8E3, 0xD747, 0xC8E4, 0xD749, 0xC8E5, 0xD750, 0xC8E6, 0xD751,
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+	0xD0F5, 0x5993, 0xD0F6, 0x5BC4, 0xD0F7, 0x5C90, 0xD0F8, 0x5D0E,	0xD0F9, 0x5DF1, 0xD0FA, 0x5E7E, 0xD0FB, 0x5FCC, 0xD0FC, 0x6280,
+	0xD0FD, 0x65D7, 0xD0FE, 0x65E3, 0xD1A1, 0x671E, 0xD1A2, 0x671F,	0xD1A3, 0x675E, 0xD1A4, 0x68CB, 0xD1A5, 0x68C4, 0xD1A6, 0x6A5F,
+	0xD1A7, 0x6B3A, 0xD1A8, 0x6C23, 0xD1A9, 0x6C7D, 0xD1AA, 0x6C82,	0xD1AB, 0x6DC7, 0xD1AC, 0x7398, 0xD1AD, 0x7426, 0xD1AE, 0x742A,
+	0xD1AF, 0x7482, 0xD1B0, 0x74A3, 0xD1B1, 0x7578, 0xD1B2, 0x757F,	0xD1B3, 0x7881, 0xD1B4, 0x78EF, 0xD1B5, 0x7941, 0xD1B6, 0x7947,
+	0xD1B7, 0x7948, 0xD1B8, 0x797A, 0xD1B9, 0x7B95, 0xD1BA, 0x7D00,	0xD1BB, 0x7DBA, 0xD1BC, 0x7F88, 0xD1BD, 0x8006, 0xD1BE, 0x802D,
+	0xD1BF, 0x808C, 0xD1C0, 0x8A18, 0xD1C1, 0x8B4F, 0xD1C2, 0x8C48,	0xD1C3, 0x8D77, 0xD1C4, 0x9321, 0xD1C5, 0x9324, 0xD1C6, 0x98E2,
+	0xD1C7, 0x9951, 0xD1C8, 0x9A0E, 0xD1C9, 0x9A0F, 0xD1CA, 0x9A65,	0xD1CB, 0x9E92, 0xD1CC, 0x7DCA, 0xD1CD, 0x4F76, 0xD1CE, 0x5409,
+	0xD1CF, 0x62EE, 0xD1D0, 0x6854, 0xD1D1, 0x91D1, 0xD1D2, 0x55AB,	0xD1D3, 0x513A, 0xD1D4, 0xF90B, 0xD1D5, 0xF90C, 0xD1D6, 0x5A1C,
+	0xD1D7, 0x61E6, 0xD1D8, 0xF90D, 0xD1D9, 0x62CF, 0xD1DA, 0x62FF,	0xD1DB, 0xF90E, 0xD1DC, 0xF90F, 0xD1DD, 0xF910, 0xD1DE, 0xF911,
+	0xD1DF, 0xF912, 0xD1E0, 0xF913, 0xD1E1, 0x90A3, 0xD1E2, 0xF914,	0xD1E3, 0xF915, 0xD1E4, 0xF916, 0xD1E5, 0xF917, 0xD1E6, 0xF918,
+	0xD1E7, 0x8AFE, 0xD1E8, 0xF919, 0xD1E9, 0xF91A, 0xD1EA, 0xF91B,	0xD1EB, 0xF91C, 0xD1EC, 0x6696, 0xD1ED, 0xF91D, 0xD1EE, 0x7156,
+	0xD1EF, 0xF91E, 0xD1F0, 0xF91F, 0xD1F1, 0x96E3, 0xD1F2, 0xF920,	0xD1F3, 0x634F, 0xD1F4, 0x637A, 0xD1F5, 0x5357, 0xD1F6, 0xF921,
+	0xD1F7, 0x678F, 0xD1F8, 0x6960, 0xD1F9, 0x6E73, 0xD1FA, 0xF922,	0xD1FB, 0x7537, 0xD1FC, 0xF923, 0xD1FD, 0xF924, 0xD1FE, 0xF925,
+	0xD2A1, 0x7D0D, 0xD2A2, 0xF926, 0xD2A3, 0xF927, 0xD2A4, 0x8872,	0xD2A5, 0x56CA, 0xD2A6, 0x5A18, 0xD2A7, 0xF928, 0xD2A8, 0xF929,
+	0xD2A9, 0xF92A, 0xD2AA, 0xF92B, 0xD2AB, 0xF92C, 0xD2AC, 0x4E43,	0xD2AD, 0xF92D, 0xD2AE, 0x5167, 0xD2AF, 0x5948, 0xD2B0, 0x67F0,
+	0xD2B1, 0x8010, 0xD2B2, 0xF92E, 0xD2B3, 0x5973, 0xD2B4, 0x5E74,	0xD2B5, 0x649A, 0xD2B6, 0x79CA, 0xD2B7, 0x5FF5, 0xD2B8, 0x606C,
+	0xD2B9, 0x62C8, 0xD2BA, 0x637B, 0xD2BB, 0x5BE7, 0xD2BC, 0x5BD7,	0xD2BD, 0x52AA, 0xD2BE, 0xF92F, 0xD2BF, 0x5974, 0xD2C0, 0x5F29,
+	0xD2C1, 0x6012, 0xD2C2, 0xF930, 0xD2C3, 0xF931, 0xD2C4, 0xF932,	0xD2C5, 0x7459, 0xD2C6, 0xF933, 0xD2C7, 0xF934, 0xD2C8, 0xF935,
+	0xD2C9, 0xF936, 0xD2CA, 0xF937, 0xD2CB, 0xF938, 0xD2CC, 0x99D1,	0xD2CD, 0xF939, 0xD2CE, 0xF93A, 0xD2CF, 0xF93B, 0xD2D0, 0xF93C,
+	0xD2D1, 0xF93D, 0xD2D2, 0xF93E, 0xD2D3, 0xF93F, 0xD2D4, 0xF940,	0xD2D5, 0xF941, 0xD2D6, 0xF942, 0xD2D7, 0xF943, 0xD2D8, 0x6FC3,
+	0xD2D9, 0xF944, 0xD2DA, 0xF945, 0xD2DB, 0x81BF, 0xD2DC, 0x8FB2,	0xD2DD, 0x60F1, 0xD2DE, 0xF946, 0xD2DF, 0xF947, 0xD2E0, 0x8166,
+	0xD2E1, 0xF948, 0xD2E2, 0xF949, 0xD2E3, 0x5C3F, 0xD2E4, 0xF94A,	0xD2E5, 0xF94B, 0xD2E6, 0xF94C, 0xD2E7, 0xF94D, 0xD2E8, 0xF94E,
+	0xD2E9, 0xF94F, 0xD2EA, 0xF950, 0xD2EB, 0xF951, 0xD2EC, 0x5AE9,	0xD2ED, 0x8A25, 0xD2EE, 0x677B, 0xD2EF, 0x7D10, 0xD2F0, 0xF952,
+	0xD2F1, 0xF953, 0xD2F2, 0xF954, 0xD2F3, 0xF955, 0xD2F4, 0xF956,	0xD2F5, 0xF957, 0xD2F6, 0x80FD, 0xD2F7, 0xF958, 0xD2F8, 0xF959,
+	0xD2F9, 0x5C3C, 0xD2FA, 0x6CE5, 0xD2FB, 0x533F, 0xD2FC, 0x6EBA,	0xD2FD, 0x591A, 0xD2FE, 0x8336, 0xD3A1, 0x4E39, 0xD3A2, 0x4EB6,
+	0xD3A3, 0x4F46, 0xD3A4, 0x55AE, 0xD3A5, 0x5718, 0xD3A6, 0x58C7,	0xD3A7, 0x5F56, 0xD3A8, 0x65B7, 0xD3A9, 0x65E6, 0xD3AA, 0x6A80,
+	0xD3AB, 0x6BB5, 0xD3AC, 0x6E4D, 0xD3AD, 0x77ED, 0xD3AE, 0x7AEF,	0xD3AF, 0x7C1E, 0xD3B0, 0x7DDE, 0xD3B1, 0x86CB, 0xD3B2, 0x8892,
+	0xD3B3, 0x9132, 0xD3B4, 0x935B, 0xD3B5, 0x64BB, 0xD3B6, 0x6FBE,	0xD3B7, 0x737A, 0xD3B8, 0x75B8, 0xD3B9, 0x9054, 0xD3BA, 0x5556,
+	0xD3BB, 0x574D, 0xD3BC, 0x61BA, 0xD3BD, 0x64D4, 0xD3BE, 0x66C7,	0xD3BF, 0x6DE1, 0xD3C0, 0x6E5B, 0xD3C1, 0x6F6D, 0xD3C2, 0x6FB9,
+	0xD3C3, 0x75F0, 0xD3C4, 0x8043, 0xD3C5, 0x81BD, 0xD3C6, 0x8541,	0xD3C7, 0x8983, 0xD3C8, 0x8AC7, 0xD3C9, 0x8B5A, 0xD3CA, 0x931F,
+	0xD3CB, 0x6C93, 0xD3CC, 0x7553, 0xD3CD, 0x7B54, 0xD3CE, 0x8E0F,	0xD3CF, 0x905D, 0xD3D0, 0x5510, 0xD3D1, 0x5802, 0xD3D2, 0x5858,
+	0xD3D3, 0x5E62, 0xD3D4, 0x6207, 0xD3D5, 0x649E, 0xD3D6, 0x68E0,	0xD3D7, 0x7576, 0xD3D8, 0x7CD6, 0xD3D9, 0x87B3, 0xD3DA, 0x9EE8,
+	0xD3DB, 0x4EE3, 0xD3DC, 0x5788, 0xD3DD, 0x576E, 0xD3DE, 0x5927,	0xD3DF, 0x5C0D, 0xD3E0, 0x5CB1, 0xD3E1, 0x5E36, 0xD3E2, 0x5F85,
+	0xD3E3, 0x6234, 0xD3E4, 0x64E1, 0xD3E5, 0x73B3, 0xD3E6, 0x81FA,	0xD3E7, 0x888B, 0xD3E8, 0x8CB8, 0xD3E9, 0x968A, 0xD3EA, 0x9EDB,
+	0xD3EB, 0x5B85, 0xD3EC, 0x5FB7, 0xD3ED, 0x60B3, 0xD3EE, 0x5012,	0xD3EF, 0x5200, 0xD3F0, 0x5230, 0xD3F1, 0x5716, 0xD3F2, 0x5835,
+	0xD3F3, 0x5857, 0xD3F4, 0x5C0E, 0xD3F5, 0x5C60, 0xD3F6, 0x5CF6,	0xD3F7, 0x5D8B, 0xD3F8, 0x5EA6, 0xD3F9, 0x5F92, 0xD3FA, 0x60BC,
+	0xD3FB, 0x6311, 0xD3FC, 0x6389, 0xD3FD, 0x6417, 0xD3FE, 0x6843,	0xD4A1, 0x68F9, 0xD4A2, 0x6AC2, 0xD4A3, 0x6DD8, 0xD4A4, 0x6E21,
+	0xD4A5, 0x6ED4, 0xD4A6, 0x6FE4, 0xD4A7, 0x71FE, 0xD4A8, 0x76DC,	0xD4A9, 0x7779, 0xD4AA, 0x79B1, 0xD4AB, 0x7A3B, 0xD4AC, 0x8404,
+	0xD4AD, 0x89A9, 0xD4AE, 0x8CED, 0xD4AF, 0x8DF3, 0xD4B0, 0x8E48,	0xD4B1, 0x9003, 0xD4B2, 0x9014, 0xD4B3, 0x9053, 0xD4B4, 0x90FD,
+	0xD4B5, 0x934D, 0xD4B6, 0x9676, 0xD4B7, 0x97DC, 0xD4B8, 0x6BD2,	0xD4B9, 0x7006, 0xD4BA, 0x7258, 0xD4BB, 0x72A2, 0xD4BC, 0x7368,
+	0xD4BD, 0x7763, 0xD4BE, 0x79BF, 0xD4BF, 0x7BE4, 0xD4C0, 0x7E9B,	0xD4C1, 0x8B80, 0xD4C2, 0x58A9, 0xD4C3, 0x60C7, 0xD4C4, 0x6566,
+	0xD4C5, 0x65FD, 0xD4C6, 0x66BE, 0xD4C7, 0x6C8C, 0xD4C8, 0x711E,	0xD4C9, 0x71C9, 0xD4CA, 0x8C5A, 0xD4CB, 0x9813, 0xD4CC, 0x4E6D,
+	0xD4CD, 0x7A81, 0xD4CE, 0x4EDD, 0xD4CF, 0x51AC, 0xD4D0, 0x51CD,	0xD4D1, 0x52D5, 0xD4D2, 0x540C, 0xD4D3, 0x61A7, 0xD4D4, 0x6771,
+	0xD4D5, 0x6850, 0xD4D6, 0x68DF, 0xD4D7, 0x6D1E, 0xD4D8, 0x6F7C,	0xD4D9, 0x75BC, 0xD4DA, 0x77B3, 0xD4DB, 0x7AE5, 0xD4DC, 0x80F4,
+	0xD4DD, 0x8463, 0xD4DE, 0x9285, 0xD4DF, 0x515C, 0xD4E0, 0x6597,	0xD4E1, 0x675C, 0xD4E2, 0x6793, 0xD4E3, 0x75D8, 0xD4E4, 0x7AC7,
+	0xD4E5, 0x8373, 0xD4E6, 0xF95A, 0xD4E7, 0x8C46, 0xD4E8, 0x9017,	0xD4E9, 0x982D, 0xD4EA, 0x5C6F, 0xD4EB, 0x81C0, 0xD4EC, 0x829A,
+	0xD4ED, 0x9041, 0xD4EE, 0x906F, 0xD4EF, 0x920D, 0xD4F0, 0x5F97,	0xD4F1, 0x5D9D, 0xD4F2, 0x6A59, 0xD4F3, 0x71C8, 0xD4F4, 0x767B,
+	0xD4F5, 0x7B49, 0xD4F6, 0x85E4, 0xD4F7, 0x8B04, 0xD4F8, 0x9127,	0xD4F9, 0x9A30, 0xD4FA, 0x5587, 0xD4FB, 0x61F6, 0xD4FC, 0xF95B,
+	0xD4FD, 0x7669, 0xD4FE, 0x7F85, 0xD5A1, 0x863F, 0xD5A2, 0x87BA,	0xD5A3, 0x88F8, 0xD5A4, 0x908F, 0xD5A5, 0xF95C, 0xD5A6, 0x6D1B,
+	0xD5A7, 0x70D9, 0xD5A8, 0x73DE, 0xD5A9, 0x7D61, 0xD5AA, 0x843D,	0xD5AB, 0xF95D, 0xD5AC, 0x916A, 0xD5AD, 0x99F1, 0xD5AE, 0xF95E,
+	0xD5AF, 0x4E82, 0xD5B0, 0x5375, 0xD5B1, 0x6B04, 0xD5B2, 0x6B12,	0xD5B3, 0x703E, 0xD5B4, 0x721B, 0xD5B5, 0x862D, 0xD5B6, 0x9E1E,
+	0xD5B7, 0x524C, 0xD5B8, 0x8FA3, 0xD5B9, 0x5D50, 0xD5BA, 0x64E5,	0xD5BB, 0x652C, 0xD5BC, 0x6B16, 0xD5BD, 0x6FEB, 0xD5BE, 0x7C43,
+	0xD5BF, 0x7E9C, 0xD5C0, 0x85CD, 0xD5C1, 0x8964, 0xD5C2, 0x89BD,	0xD5C3, 0x62C9, 0xD5C4, 0x81D8, 0xD5C5, 0x881F, 0xD5C6, 0x5ECA,
+	0xD5C7, 0x6717, 0xD5C8, 0x6D6A, 0xD5C9, 0x72FC, 0xD5CA, 0x7405,	0xD5CB, 0x746F, 0xD5CC, 0x8782, 0xD5CD, 0x90DE, 0xD5CE, 0x4F86,
+	0xD5CF, 0x5D0D, 0xD5D0, 0x5FA0, 0xD5D1, 0x840A, 0xD5D2, 0x51B7,	0xD5D3, 0x63A0, 0xD5D4, 0x7565, 0xD5D5, 0x4EAE, 0xD5D6, 0x5006,
+	0xD5D7, 0x5169, 0xD5D8, 0x51C9, 0xD5D9, 0x6881, 0xD5DA, 0x6A11,	0xD5DB, 0x7CAE, 0xD5DC, 0x7CB1, 0xD5DD, 0x7CE7, 0xD5DE, 0x826F,
+	0xD5DF, 0x8AD2, 0xD5E0, 0x8F1B, 0xD5E1, 0x91CF, 0xD5E2, 0x4FB6,	0xD5E3, 0x5137, 0xD5E4, 0x52F5, 0xD5E5, 0x5442, 0xD5E6, 0x5EEC,
+	0xD5E7, 0x616E, 0xD5E8, 0x623E, 0xD5E9, 0x65C5, 0xD5EA, 0x6ADA,	0xD5EB, 0x6FFE, 0xD5EC, 0x792A, 0xD5ED, 0x85DC, 0xD5EE, 0x8823,
+	0xD5EF, 0x95AD, 0xD5F0, 0x9A62, 0xD5F1, 0x9A6A, 0xD5F2, 0x9E97,	0xD5F3, 0x9ECE, 0xD5F4, 0x529B, 0xD5F5, 0x66C6, 0xD5F6, 0x6B77,
+	0xD5F7, 0x701D, 0xD5F8, 0x792B, 0xD5F9, 0x8F62, 0xD5FA, 0x9742,	0xD5FB, 0x6190, 0xD5FC, 0x6200, 0xD5FD, 0x6523, 0xD5FE, 0x6F23,
+	0xD6A1, 0x7149, 0xD6A2, 0x7489, 0xD6A3, 0x7DF4, 0xD6A4, 0x806F,	0xD6A5, 0x84EE, 0xD6A6, 0x8F26, 0xD6A7, 0x9023, 0xD6A8, 0x934A,
+	0xD6A9, 0x51BD, 0xD6AA, 0x5217, 0xD6AB, 0x52A3, 0xD6AC, 0x6D0C,	0xD6AD, 0x70C8, 0xD6AE, 0x88C2, 0xD6AF, 0x5EC9, 0xD6B0, 0x6582,
+	0xD6B1, 0x6BAE, 0xD6B2, 0x6FC2, 0xD6B3, 0x7C3E, 0xD6B4, 0x7375,	0xD6B5, 0x4EE4, 0xD6B6, 0x4F36, 0xD6B7, 0x56F9, 0xD6B8, 0xF95F,
+	0xD6B9, 0x5CBA, 0xD6BA, 0x5DBA, 0xD6BB, 0x601C, 0xD6BC, 0x73B2,	0xD6BD, 0x7B2D, 0xD6BE, 0x7F9A, 0xD6BF, 0x7FCE, 0xD6C0, 0x8046,
+	0xD6C1, 0x901E, 0xD6C2, 0x9234, 0xD6C3, 0x96F6, 0xD6C4, 0x9748,	0xD6C5, 0x9818, 0xD6C6, 0x9F61, 0xD6C7, 0x4F8B, 0xD6C8, 0x6FA7,
+	0xD6C9, 0x79AE, 0xD6CA, 0x91B4, 0xD6CB, 0x96B7, 0xD6CC, 0x52DE,	0xD6CD, 0xF960, 0xD6CE, 0x6488, 0xD6CF, 0x64C4, 0xD6D0, 0x6AD3,
+	0xD6D1, 0x6F5E, 0xD6D2, 0x7018, 0xD6D3, 0x7210, 0xD6D4, 0x76E7,	0xD6D5, 0x8001, 0xD6D6, 0x8606, 0xD6D7, 0x865C, 0xD6D8, 0x8DEF,
+	0xD6D9, 0x8F05, 0xD6DA, 0x9732, 0xD6DB, 0x9B6F, 0xD6DC, 0x9DFA,	0xD6DD, 0x9E75, 0xD6DE, 0x788C, 0xD6DF, 0x797F, 0xD6E0, 0x7DA0,
+	0xD6E1, 0x83C9, 0xD6E2, 0x9304, 0xD6E3, 0x9E7F, 0xD6E4, 0x9E93,	0xD6E5, 0x8AD6, 0xD6E6, 0x58DF, 0xD6E7, 0x5F04, 0xD6E8, 0x6727,
+	0xD6E9, 0x7027, 0xD6EA, 0x74CF, 0xD6EB, 0x7C60, 0xD6EC, 0x807E,	0xD6ED, 0x5121, 0xD6EE, 0x7028, 0xD6EF, 0x7262, 0xD6F0, 0x78CA,
+	0xD6F1, 0x8CC2, 0xD6F2, 0x8CDA, 0xD6F3, 0x8CF4, 0xD6F4, 0x96F7,	0xD6F5, 0x4E86, 0xD6F6, 0x50DA, 0xD6F7, 0x5BEE, 0xD6F8, 0x5ED6,
+	0xD6F9, 0x6599, 0xD6FA, 0x71CE, 0xD6FB, 0x7642, 0xD6FC, 0x77AD,	0xD6FD, 0x804A, 0xD6FE, 0x84FC, 0xD7A1, 0x907C, 0xD7A2, 0x9B27,
+	0xD7A3, 0x9F8D, 0xD7A4, 0x58D8, 0xD7A5, 0x5A41, 0xD7A6, 0x5C62,	0xD7A7, 0x6A13, 0xD7A8, 0x6DDA, 0xD7A9, 0x6F0F, 0xD7AA, 0x763B,
+	0xD7AB, 0x7D2F, 0xD7AC, 0x7E37, 0xD7AD, 0x851E, 0xD7AE, 0x8938,	0xD7AF, 0x93E4, 0xD7B0, 0x964B, 0xD7B1, 0x5289, 0xD7B2, 0x65D2,
+	0xD7B3, 0x67F3, 0xD7B4, 0x69B4, 0xD7B5, 0x6D41, 0xD7B6, 0x6E9C,	0xD7B7, 0x700F, 0xD7B8, 0x7409, 0xD7B9, 0x7460, 0xD7BA, 0x7559,
+	0xD7BB, 0x7624, 0xD7BC, 0x786B, 0xD7BD, 0x8B2C, 0xD7BE, 0x985E,	0xD7BF, 0x516D, 0xD7C0, 0x622E, 0xD7C1, 0x9678, 0xD7C2, 0x4F96,
+	0xD7C3, 0x502B, 0xD7C4, 0x5D19, 0xD7C5, 0x6DEA, 0xD7C6, 0x7DB8,	0xD7C7, 0x8F2A, 0xD7C8, 0x5F8B, 0xD7C9, 0x6144, 0xD7CA, 0x6817,
+	0xD7CB, 0xF961, 0xD7CC, 0x9686, 0xD7CD, 0x52D2, 0xD7CE, 0x808B,	0xD7CF, 0x51DC, 0xD7D0, 0x51CC, 0xD7D1, 0x695E, 0xD7D2, 0x7A1C,
+	0xD7D3, 0x7DBE, 0xD7D4, 0x83F1, 0xD7D5, 0x9675, 0xD7D6, 0x4FDA,	0xD7D7, 0x5229, 0xD7D8, 0x5398, 0xD7D9, 0x540F, 0xD7DA, 0x550E,
+	0xD7DB, 0x5C65, 0xD7DC, 0x60A7, 0xD7DD, 0x674E, 0xD7DE, 0x68A8,	0xD7DF, 0x6D6C, 0xD7E0, 0x7281, 0xD7E1, 0x72F8, 0xD7E2, 0x7406,
+	0xD7E3, 0x7483, 0xD7E4, 0xF962, 0xD7E5, 0x75E2, 0xD7E6, 0x7C6C,	0xD7E7, 0x7F79, 0xD7E8, 0x7FB8, 0xD7E9, 0x8389, 0xD7EA, 0x88CF,
+	0xD7EB, 0x88E1, 0xD7EC, 0x91CC, 0xD7ED, 0x91D0, 0xD7EE, 0x96E2,	0xD7EF, 0x9BC9, 0xD7F0, 0x541D, 0xD7F1, 0x6F7E, 0xD7F2, 0x71D0,
+	0xD7F3, 0x7498, 0xD7F4, 0x85FA, 0xD7F5, 0x8EAA, 0xD7F6, 0x96A3,	0xD7F7, 0x9C57, 0xD7F8, 0x9E9F, 0xD7F9, 0x6797, 0xD7FA, 0x6DCB,
+	0xD7FB, 0x7433, 0xD7FC, 0x81E8, 0xD7FD, 0x9716, 0xD7FE, 0x782C,	0xD8A1, 0x7ACB, 0xD8A2, 0x7B20, 0xD8A3, 0x7C92, 0xD8A4, 0x6469,
+	0xD8A5, 0x746A, 0xD8A6, 0x75F2, 0xD8A7, 0x78BC, 0xD8A8, 0x78E8,	0xD8A9, 0x99AC, 0xD8AA, 0x9B54, 0xD8AB, 0x9EBB, 0xD8AC, 0x5BDE,
+	0xD8AD, 0x5E55, 0xD8AE, 0x6F20, 0xD8AF, 0x819C, 0xD8B0, 0x83AB,	0xD8B1, 0x9088, 0xD8B2, 0x4E07, 0xD8B3, 0x534D, 0xD8B4, 0x5A29,
+	0xD8B5, 0x5DD2, 0xD8B6, 0x5F4E, 0xD8B7, 0x6162, 0xD8B8, 0x633D,	0xD8B9, 0x6669, 0xD8BA, 0x66FC, 0xD8BB, 0x6EFF, 0xD8BC, 0x6F2B,
+	0xD8BD, 0x7063, 0xD8BE, 0x779E, 0xD8BF, 0x842C, 0xD8C0, 0x8513,	0xD8C1, 0x883B, 0xD8C2, 0x8F13, 0xD8C3, 0x9945, 0xD8C4, 0x9C3B,
+	0xD8C5, 0x551C, 0xD8C6, 0x62B9, 0xD8C7, 0x672B, 0xD8C8, 0x6CAB,	0xD8C9, 0x8309, 0xD8CA, 0x896A, 0xD8CB, 0x977A, 0xD8CC, 0x4EA1,
+	0xD8CD, 0x5984, 0xD8CE, 0x5FD8, 0xD8CF, 0x5FD9, 0xD8D0, 0x671B,	0xD8D1, 0x7DB2, 0xD8D2, 0x7F54, 0xD8D3, 0x8292, 0xD8D4, 0x832B,
+	0xD8D5, 0x83BD, 0xD8D6, 0x8F1E, 0xD8D7, 0x9099, 0xD8D8, 0x57CB,	0xD8D9, 0x59B9, 0xD8DA, 0x5A92, 0xD8DB, 0x5BD0, 0xD8DC, 0x6627,
+	0xD8DD, 0x679A, 0xD8DE, 0x6885, 0xD8DF, 0x6BCF, 0xD8E0, 0x7164,	0xD8E1, 0x7F75, 0xD8E2, 0x8CB7, 0xD8E3, 0x8CE3, 0xD8E4, 0x9081,
+	0xD8E5, 0x9B45, 0xD8E6, 0x8108, 0xD8E7, 0x8C8A, 0xD8E8, 0x964C,	0xD8E9, 0x9A40, 0xD8EA, 0x9EA5, 0xD8EB, 0x5B5F, 0xD8EC, 0x6C13,
+	0xD8ED, 0x731B, 0xD8EE, 0x76F2, 0xD8EF, 0x76DF, 0xD8F0, 0x840C,	0xD8F1, 0x51AA, 0xD8F2, 0x8993, 0xD8F3, 0x514D, 0xD8F4, 0x5195,
+	0xD8F5, 0x52C9, 0xD8F6, 0x68C9, 0xD8F7, 0x6C94, 0xD8F8, 0x7704,	0xD8F9, 0x7720, 0xD8FA, 0x7DBF, 0xD8FB, 0x7DEC, 0xD8FC, 0x9762,
+	0xD8FD, 0x9EB5, 0xD8FE, 0x6EC5, 0xD9A1, 0x8511, 0xD9A2, 0x51A5,	0xD9A3, 0x540D, 0xD9A4, 0x547D, 0xD9A5, 0x660E, 0xD9A6, 0x669D,
+	0xD9A7, 0x6927, 0xD9A8, 0x6E9F, 0xD9A9, 0x76BF, 0xD9AA, 0x7791,	0xD9AB, 0x8317, 0xD9AC, 0x84C2, 0xD9AD, 0x879F, 0xD9AE, 0x9169,
+	0xD9AF, 0x9298, 0xD9B0, 0x9CF4, 0xD9B1, 0x8882, 0xD9B2, 0x4FAE,	0xD9B3, 0x5192, 0xD9B4, 0x52DF, 0xD9B5, 0x59C6, 0xD9B6, 0x5E3D,
+	0xD9B7, 0x6155, 0xD9B8, 0x6478, 0xD9B9, 0x6479, 0xD9BA, 0x66AE,	0xD9BB, 0x67D0, 0xD9BC, 0x6A21, 0xD9BD, 0x6BCD, 0xD9BE, 0x6BDB,
+	0xD9BF, 0x725F, 0xD9C0, 0x7261, 0xD9C1, 0x7441, 0xD9C2, 0x7738,	0xD9C3, 0x77DB, 0xD9C4, 0x8017, 0xD9C5, 0x82BC, 0xD9C6, 0x8305,
+	0xD9C7, 0x8B00, 0xD9C8, 0x8B28, 0xD9C9, 0x8C8C, 0xD9CA, 0x6728,	0xD9CB, 0x6C90, 0xD9CC, 0x7267, 0xD9CD, 0x76EE, 0xD9CE, 0x7766,
+	0xD9CF, 0x7A46, 0xD9D0, 0x9DA9, 0xD9D1, 0x6B7F, 0xD9D2, 0x6C92,	0xD9D3, 0x5922, 0xD9D4, 0x6726, 0xD9D5, 0x8499, 0xD9D6, 0x536F,
+	0xD9D7, 0x5893, 0xD9D8, 0x5999, 0xD9D9, 0x5EDF, 0xD9DA, 0x63CF,	0xD9DB, 0x6634, 0xD9DC, 0x6773, 0xD9DD, 0x6E3A, 0xD9DE, 0x732B,
+	0xD9DF, 0x7AD7, 0xD9E0, 0x82D7, 0xD9E1, 0x9328, 0xD9E2, 0x52D9,	0xD9E3, 0x5DEB, 0xD9E4, 0x61AE, 0xD9E5, 0x61CB, 0xD9E6, 0x620A,
+	0xD9E7, 0x62C7, 0xD9E8, 0x64AB, 0xD9E9, 0x65E0, 0xD9EA, 0x6959,	0xD9EB, 0x6B66, 0xD9EC, 0x6BCB, 0xD9ED, 0x7121, 0xD9EE, 0x73F7,
+	0xD9EF, 0x755D, 0xD9F0, 0x7E46, 0xD9F1, 0x821E, 0xD9F2, 0x8302,	0xD9F3, 0x856A, 0xD9F4, 0x8AA3, 0xD9F5, 0x8CBF, 0xD9F6, 0x9727,
+	0xD9F7, 0x9D61, 0xD9F8, 0x58A8, 0xD9F9, 0x9ED8, 0xD9FA, 0x5011,	0xD9FB, 0x520E, 0xD9FC, 0x543B, 0xD9FD, 0x554F, 0xD9FE, 0x6587,
+	0xDAA1, 0x6C76, 0xDAA2, 0x7D0A, 0xDAA3, 0x7D0B, 0xDAA4, 0x805E,	0xDAA5, 0x868A, 0xDAA6, 0x9580, 0xDAA7, 0x96EF, 0xDAA8, 0x52FF,
+	0xDAA9, 0x6C95, 0xDAAA, 0x7269, 0xDAAB, 0x5473, 0xDAAC, 0x5A9A,	0xDAAD, 0x5C3E, 0xDAAE, 0x5D4B, 0xDAAF, 0x5F4C, 0xDAB0, 0x5FAE,
+	0xDAB1, 0x672A, 0xDAB2, 0x68B6, 0xDAB3, 0x6963, 0xDAB4, 0x6E3C,	0xDAB5, 0x6E44, 0xDAB6, 0x7709, 0xDAB7, 0x7C73, 0xDAB8, 0x7F8E,
+	0xDAB9, 0x8587, 0xDABA, 0x8B0E, 0xDABB, 0x8FF7, 0xDABC, 0x9761,	0xDABD, 0x9EF4, 0xDABE, 0x5CB7, 0xDABF, 0x60B6, 0xDAC0, 0x610D,
+	0xDAC1, 0x61AB, 0xDAC2, 0x654F, 0xDAC3, 0x65FB, 0xDAC4, 0x65FC,	0xDAC5, 0x6C11, 0xDAC6, 0x6CEF, 0xDAC7, 0x739F, 0xDAC8, 0x73C9,
+	0xDAC9, 0x7DE1, 0xDACA, 0x9594, 0xDACB, 0x5BC6, 0xDACC, 0x871C,	0xDACD, 0x8B10, 0xDACE, 0x525D, 0xDACF, 0x535A, 0xDAD0, 0x62CD,
+	0xDAD1, 0x640F, 0xDAD2, 0x64B2, 0xDAD3, 0x6734, 0xDAD4, 0x6A38,	0xDAD5, 0x6CCA, 0xDAD6, 0x73C0, 0xDAD7, 0x749E, 0xDAD8, 0x7B94,
+	0xDAD9, 0x7C95, 0xDADA, 0x7E1B, 0xDADB, 0x818A, 0xDADC, 0x8236,	0xDADD, 0x8584, 0xDADE, 0x8FEB, 0xDADF, 0x96F9, 0xDAE0, 0x99C1,
+	0xDAE1, 0x4F34, 0xDAE2, 0x534A, 0xDAE3, 0x53CD, 0xDAE4, 0x53DB,	0xDAE5, 0x62CC, 0xDAE6, 0x642C, 0xDAE7, 0x6500, 0xDAE8, 0x6591,
+	0xDAE9, 0x69C3, 0xDAEA, 0x6CEE, 0xDAEB, 0x6F58, 0xDAEC, 0x73ED,	0xDAED, 0x7554, 0xDAEE, 0x7622, 0xDAEF, 0x76E4, 0xDAF0, 0x76FC,
+	0xDAF1, 0x78D0, 0xDAF2, 0x78FB, 0xDAF3, 0x792C, 0xDAF4, 0x7D46,	0xDAF5, 0x822C, 0xDAF6, 0x87E0, 0xDAF7, 0x8FD4, 0xDAF8, 0x9812,
+	0xDAF9, 0x98EF, 0xDAFA, 0x52C3, 0xDAFB, 0x62D4, 0xDAFC, 0x64A5,	0xDAFD, 0x6E24, 0xDAFE, 0x6F51, 0xDBA1, 0x767C, 0xDBA2, 0x8DCB,
+	0xDBA3, 0x91B1, 0xDBA4, 0x9262, 0xDBA5, 0x9AEE, 0xDBA6, 0x9B43,	0xDBA7, 0x5023, 0xDBA8, 0x508D, 0xDBA9, 0x574A, 0xDBAA, 0x59A8,
+	0xDBAB, 0x5C28, 0xDBAC, 0x5E47, 0xDBAD, 0x5F77, 0xDBAE, 0x623F,	0xDBAF, 0x653E, 0xDBB0, 0x65B9, 0xDBB1, 0x65C1, 0xDBB2, 0x6609,
+	0xDBB3, 0x678B, 0xDBB4, 0x699C, 0xDBB5, 0x6EC2, 0xDBB6, 0x78C5,	0xDBB7, 0x7D21, 0xDBB8, 0x80AA, 0xDBB9, 0x8180, 0xDBBA, 0x822B,
+	0xDBBB, 0x82B3, 0xDBBC, 0x84A1, 0xDBBD, 0x868C, 0xDBBE, 0x8A2A,	0xDBBF, 0x8B17, 0xDBC0, 0x90A6, 0xDBC1, 0x9632, 0xDBC2, 0x9F90,
+	0xDBC3, 0x500D, 0xDBC4, 0x4FF3, 0xDBC5, 0xF963, 0xDBC6, 0x57F9,	0xDBC7, 0x5F98, 0xDBC8, 0x62DC, 0xDBC9, 0x6392, 0xDBCA, 0x676F,
+	0xDBCB, 0x6E43, 0xDBCC, 0x7119, 0xDBCD, 0x76C3, 0xDBCE, 0x80CC,	0xDBCF, 0x80DA, 0xDBD0, 0x88F4, 0xDBD1, 0x88F5, 0xDBD2, 0x8919,
+	0xDBD3, 0x8CE0, 0xDBD4, 0x8F29, 0xDBD5, 0x914D, 0xDBD6, 0x966A,	0xDBD7, 0x4F2F, 0xDBD8, 0x4F70, 0xDBD9, 0x5E1B, 0xDBDA, 0x67CF,
+	0xDBDB, 0x6822, 0xDBDC, 0x767D, 0xDBDD, 0x767E, 0xDBDE, 0x9B44,	0xDBDF, 0x5E61, 0xDBE0, 0x6A0A, 0xDBE1, 0x7169, 0xDBE2, 0x71D4,
+	0xDBE3, 0x756A, 0xDBE4, 0xF964, 0xDBE5, 0x7E41, 0xDBE6, 0x8543,	0xDBE7, 0x85E9, 0xDBE8, 0x98DC, 0xDBE9, 0x4F10, 0xDBEA, 0x7B4F,
+	0xDBEB, 0x7F70, 0xDBEC, 0x95A5, 0xDBED, 0x51E1, 0xDBEE, 0x5E06,	0xDBEF, 0x68B5, 0xDBF0, 0x6C3E, 0xDBF1, 0x6C4E, 0xDBF2, 0x6CDB,
+	0xDBF3, 0x72AF, 0xDBF4, 0x7BC4, 0xDBF5, 0x8303, 0xDBF6, 0x6CD5,	0xDBF7, 0x743A, 0xDBF8, 0x50FB, 0xDBF9, 0x5288, 0xDBFA, 0x58C1,
+	0xDBFB, 0x64D8, 0xDBFC, 0x6A97, 0xDBFD, 0x74A7, 0xDBFE, 0x7656,	0xDCA1, 0x78A7, 0xDCA2, 0x8617, 0xDCA3, 0x95E2, 0xDCA4, 0x9739,
+	0xDCA5, 0xF965, 0xDCA6, 0x535E, 0xDCA7, 0x5F01, 0xDCA8, 0x8B8A,	0xDCA9, 0x8FA8, 0xDCAA, 0x8FAF, 0xDCAB, 0x908A, 0xDCAC, 0x5225,
+	0xDCAD, 0x77A5, 0xDCAE, 0x9C49, 0xDCAF, 0x9F08, 0xDCB0, 0x4E19,	0xDCB1, 0x5002, 0xDCB2, 0x5175, 0xDCB3, 0x5C5B, 0xDCB4, 0x5E77,
+	0xDCB5, 0x661E, 0xDCB6, 0x663A, 0xDCB7, 0x67C4, 0xDCB8, 0x68C5,	0xDCB9, 0x70B3, 0xDCBA, 0x7501, 0xDCBB, 0x75C5, 0xDCBC, 0x79C9,
+	0xDCBD, 0x7ADD, 0xDCBE, 0x8F27, 0xDCBF, 0x9920, 0xDCC0, 0x9A08,	0xDCC1, 0x4FDD, 0xDCC2, 0x5821, 0xDCC3, 0x5831, 0xDCC4, 0x5BF6,
+	0xDCC5, 0x666E, 0xDCC6, 0x6B65, 0xDCC7, 0x6D11, 0xDCC8, 0x6E7A,	0xDCC9, 0x6F7D, 0xDCCA, 0x73E4, 0xDCCB, 0x752B, 0xDCCC, 0x83E9,
+	0xDCCD, 0x88DC, 0xDCCE, 0x8913, 0xDCCF, 0x8B5C, 0xDCD0, 0x8F14,	0xDCD1, 0x4F0F, 0xDCD2, 0x50D5, 0xDCD3, 0x5310, 0xDCD4, 0x535C,
+	0xDCD5, 0x5B93, 0xDCD6, 0x5FA9, 0xDCD7, 0x670D, 0xDCD8, 0x798F,	0xDCD9, 0x8179, 0xDCDA, 0x832F, 0xDCDB, 0x8514, 0xDCDC, 0x8907,
+	0xDCDD, 0x8986, 0xDCDE, 0x8F39, 0xDCDF, 0x8F3B, 0xDCE0, 0x99A5,	0xDCE1, 0x9C12, 0xDCE2, 0x672C, 0xDCE3, 0x4E76, 0xDCE4, 0x4FF8,
+	0xDCE5, 0x5949, 0xDCE6, 0x5C01, 0xDCE7, 0x5CEF, 0xDCE8, 0x5CF0,	0xDCE9, 0x6367, 0xDCEA, 0x68D2, 0xDCEB, 0x70FD, 0xDCEC, 0x71A2,
+	0xDCED, 0x742B, 0xDCEE, 0x7E2B, 0xDCEF, 0x84EC, 0xDCF0, 0x8702,	0xDCF1, 0x9022, 0xDCF2, 0x92D2, 0xDCF3, 0x9CF3, 0xDCF4, 0x4E0D,
+	0xDCF5, 0x4ED8, 0xDCF6, 0x4FEF, 0xDCF7, 0x5085, 0xDCF8, 0x5256,	0xDCF9, 0x526F, 0xDCFA, 0x5426, 0xDCFB, 0x5490, 0xDCFC, 0x57E0,
+	0xDCFD, 0x592B, 0xDCFE, 0x5A66, 0xDDA1, 0x5B5A, 0xDDA2, 0x5B75,	0xDDA3, 0x5BCC, 0xDDA4, 0x5E9C, 0xDDA5, 0xF966, 0xDDA6, 0x6276,
+	0xDDA7, 0x6577, 0xDDA8, 0x65A7, 0xDDA9, 0x6D6E, 0xDDAA, 0x6EA5,	0xDDAB, 0x7236, 0xDDAC, 0x7B26, 0xDDAD, 0x7C3F, 0xDDAE, 0x7F36,
+	0xDDAF, 0x8150, 0xDDB0, 0x8151, 0xDDB1, 0x819A, 0xDDB2, 0x8240,	0xDDB3, 0x8299, 0xDDB4, 0x83A9, 0xDDB5, 0x8A03, 0xDDB6, 0x8CA0,
+	0xDDB7, 0x8CE6, 0xDDB8, 0x8CFB, 0xDDB9, 0x8D74, 0xDDBA, 0x8DBA,	0xDDBB, 0x90E8, 0xDDBC, 0x91DC, 0xDDBD, 0x961C, 0xDDBE, 0x9644,
+	0xDDBF, 0x99D9, 0xDDC0, 0x9CE7, 0xDDC1, 0x5317, 0xDDC2, 0x5206,	0xDDC3, 0x5429, 0xDDC4, 0x5674, 0xDDC5, 0x58B3, 0xDDC6, 0x5954,
+	0xDDC7, 0x596E, 0xDDC8, 0x5FFF, 0xDDC9, 0x61A4, 0xDDCA, 0x626E,	0xDDCB, 0x6610, 0xDDCC, 0x6C7E, 0xDDCD, 0x711A, 0xDDCE, 0x76C6,
+	0xDDCF, 0x7C89, 0xDDD0, 0x7CDE, 0xDDD1, 0x7D1B, 0xDDD2, 0x82AC,	0xDDD3, 0x8CC1, 0xDDD4, 0x96F0, 0xDDD5, 0xF967, 0xDDD6, 0x4F5B,
+	0xDDD7, 0x5F17, 0xDDD8, 0x5F7F, 0xDDD9, 0x62C2, 0xDDDA, 0x5D29,	0xDDDB, 0x670B, 0xDDDC, 0x68DA, 0xDDDD, 0x787C, 0xDDDE, 0x7E43,
+	0xDDDF, 0x9D6C, 0xDDE0, 0x4E15, 0xDDE1, 0x5099, 0xDDE2, 0x5315,	0xDDE3, 0x532A, 0xDDE4, 0x5351, 0xDDE5, 0x5983, 0xDDE6, 0x5A62,
+	0xDDE7, 0x5E87, 0xDDE8, 0x60B2, 0xDDE9, 0x618A, 0xDDEA, 0x6249,	0xDDEB, 0x6279, 0xDDEC, 0x6590, 0xDDED, 0x6787, 0xDDEE, 0x69A7,
+	0xDDEF, 0x6BD4, 0xDDF0, 0x6BD6, 0xDDF1, 0x6BD7, 0xDDF2, 0x6BD8,	0xDDF3, 0x6CB8, 0xDDF4, 0xF968, 0xDDF5, 0x7435, 0xDDF6, 0x75FA,
+	0xDDF7, 0x7812, 0xDDF8, 0x7891, 0xDDF9, 0x79D5, 0xDDFA, 0x79D8,	0xDDFB, 0x7C83, 0xDDFC, 0x7DCB, 0xDDFD, 0x7FE1, 0xDDFE, 0x80A5,
+	0xDEA1, 0x813E, 0xDEA2, 0x81C2, 0xDEA3, 0x83F2, 0xDEA4, 0x871A,	0xDEA5, 0x88E8, 0xDEA6, 0x8AB9, 0xDEA7, 0x8B6C, 0xDEA8, 0x8CBB,
+	0xDEA9, 0x9119, 0xDEAA, 0x975E, 0xDEAB, 0x98DB, 0xDEAC, 0x9F3B,	0xDEAD, 0x56AC, 0xDEAE, 0x5B2A, 0xDEAF, 0x5F6C, 0xDEB0, 0x658C,
+	0xDEB1, 0x6AB3, 0xDEB2, 0x6BAF, 0xDEB3, 0x6D5C, 0xDEB4, 0x6FF1,	0xDEB5, 0x7015, 0xDEB6, 0x725D, 0xDEB7, 0x73AD, 0xDEB8, 0x8CA7,
+	0xDEB9, 0x8CD3, 0xDEBA, 0x983B, 0xDEBB, 0x6191, 0xDEBC, 0x6C37,	0xDEBD, 0x8058, 0xDEBE, 0x9A01, 0xDEBF, 0x4E4D, 0xDEC0, 0x4E8B,
+	0xDEC1, 0x4E9B, 0xDEC2, 0x4ED5, 0xDEC3, 0x4F3A, 0xDEC4, 0x4F3C,	0xDEC5, 0x4F7F, 0xDEC6, 0x4FDF, 0xDEC7, 0x50FF, 0xDEC8, 0x53F2,
+	0xDEC9, 0x53F8, 0xDECA, 0x5506, 0xDECB, 0x55E3, 0xDECC, 0x56DB,	0xDECD, 0x58EB, 0xDECE, 0x5962, 0xDECF, 0x5A11, 0xDED0, 0x5BEB,
+	0xDED1, 0x5BFA, 0xDED2, 0x5C04, 0xDED3, 0x5DF3, 0xDED4, 0x5E2B,	0xDED5, 0x5F99, 0xDED6, 0x601D, 0xDED7, 0x6368, 0xDED8, 0x659C,
+	0xDED9, 0x65AF, 0xDEDA, 0x67F6, 0xDEDB, 0x67FB, 0xDEDC, 0x68AD,	0xDEDD, 0x6B7B, 0xDEDE, 0x6C99, 0xDEDF, 0x6CD7, 0xDEE0, 0x6E23,
+	0xDEE1, 0x7009, 0xDEE2, 0x7345, 0xDEE3, 0x7802, 0xDEE4, 0x793E,	0xDEE5, 0x7940, 0xDEE6, 0x7960, 0xDEE7, 0x79C1, 0xDEE8, 0x7BE9,
+	0xDEE9, 0x7D17, 0xDEEA, 0x7D72, 0xDEEB, 0x8086, 0xDEEC, 0x820D,	0xDEED, 0x838E, 0xDEEE, 0x84D1, 0xDEEF, 0x86C7, 0xDEF0, 0x88DF,
+	0xDEF1, 0x8A50, 0xDEF2, 0x8A5E, 0xDEF3, 0x8B1D, 0xDEF4, 0x8CDC,	0xDEF5, 0x8D66, 0xDEF6, 0x8FAD, 0xDEF7, 0x90AA, 0xDEF8, 0x98FC,
+	0xDEF9, 0x99DF, 0xDEFA, 0x9E9D, 0xDEFB, 0x524A, 0xDEFC, 0xF969,	0xDEFD, 0x6714, 0xDEFE, 0xF96A, 0xDFA1, 0x5098, 0xDFA2, 0x522A,
+	0xDFA3, 0x5C71, 0xDFA4, 0x6563, 0xDFA5, 0x6C55, 0xDFA6, 0x73CA,	0xDFA7, 0x7523, 0xDFA8, 0x759D, 0xDFA9, 0x7B97, 0xDFAA, 0x849C,
+	0xDFAB, 0x9178, 0xDFAC, 0x9730, 0xDFAD, 0x4E77, 0xDFAE, 0x6492,	0xDFAF, 0x6BBA, 0xDFB0, 0x715E, 0xDFB1, 0x85A9, 0xDFB2, 0x4E09,
+	0xDFB3, 0xF96B, 0xDFB4, 0x6749, 0xDFB5, 0x68EE, 0xDFB6, 0x6E17,	0xDFB7, 0x829F, 0xDFB8, 0x8518, 0xDFB9, 0x886B, 0xDFBA, 0x63F7,
+	0xDFBB, 0x6F81, 0xDFBC, 0x9212, 0xDFBD, 0x98AF, 0xDFBE, 0x4E0A,	0xDFBF, 0x50B7, 0xDFC0, 0x50CF, 0xDFC1, 0x511F, 0xDFC2, 0x5546,
+	0xDFC3, 0x55AA, 0xDFC4, 0x5617, 0xDFC5, 0x5B40, 0xDFC6, 0x5C19,	0xDFC7, 0x5CE0, 0xDFC8, 0x5E38, 0xDFC9, 0x5E8A, 0xDFCA, 0x5EA0,
+	0xDFCB, 0x5EC2, 0xDFCC, 0x60F3, 0xDFCD, 0x6851, 0xDFCE, 0x6A61,	0xDFCF, 0x6E58, 0xDFD0, 0x723D, 0xDFD1, 0x7240, 0xDFD2, 0x72C0,
+	0xDFD3, 0x76F8, 0xDFD4, 0x7965, 0xDFD5, 0x7BB1, 0xDFD6, 0x7FD4,	0xDFD7, 0x88F3, 0xDFD8, 0x89F4, 0xDFD9, 0x8A73, 0xDFDA, 0x8C61,
+	0xDFDB, 0x8CDE, 0xDFDC, 0x971C, 0xDFDD, 0x585E, 0xDFDE, 0x74BD,	0xDFDF, 0x8CFD, 0xDFE0, 0x55C7, 0xDFE1, 0xF96C, 0xDFE2, 0x7A61,
+	0xDFE3, 0x7D22, 0xDFE4, 0x8272, 0xDFE5, 0x7272, 0xDFE6, 0x751F,	0xDFE7, 0x7525, 0xDFE8, 0xF96D, 0xDFE9, 0x7B19, 0xDFEA, 0x5885,
+	0xDFEB, 0x58FB, 0xDFEC, 0x5DBC, 0xDFED, 0x5E8F, 0xDFEE, 0x5EB6,	0xDFEF, 0x5F90, 0xDFF0, 0x6055, 0xDFF1, 0x6292, 0xDFF2, 0x637F,
+	0xDFF3, 0x654D, 0xDFF4, 0x6691, 0xDFF5, 0x66D9, 0xDFF6, 0x66F8,	0xDFF7, 0x6816, 0xDFF8, 0x68F2, 0xDFF9, 0x7280, 0xDFFA, 0x745E,
+	0xDFFB, 0x7B6E, 0xDFFC, 0x7D6E, 0xDFFD, 0x7DD6, 0xDFFE, 0x7F72,	0xE0A1, 0x80E5, 0xE0A2, 0x8212, 0xE0A3, 0x85AF, 0xE0A4, 0x897F,
+	0xE0A5, 0x8A93, 0xE0A6, 0x901D, 0xE0A7, 0x92E4, 0xE0A8, 0x9ECD,	0xE0A9, 0x9F20, 0xE0AA, 0x5915, 0xE0AB, 0x596D, 0xE0AC, 0x5E2D,
+	0xE0AD, 0x60DC, 0xE0AE, 0x6614, 0xE0AF, 0x6673, 0xE0B0, 0x6790,	0xE0B1, 0x6C50, 0xE0B2, 0x6DC5, 0xE0B3, 0x6F5F, 0xE0B4, 0x77F3,
+	0xE0B5, 0x78A9, 0xE0B6, 0x84C6, 0xE0B7, 0x91CB, 0xE0B8, 0x932B,	0xE0B9, 0x4ED9, 0xE0BA, 0x50CA, 0xE0BB, 0x5148, 0xE0BC, 0x5584,
+	0xE0BD, 0x5B0B, 0xE0BE, 0x5BA3, 0xE0BF, 0x6247, 0xE0C0, 0x657E,	0xE0C1, 0x65CB, 0xE0C2, 0x6E32, 0xE0C3, 0x717D, 0xE0C4, 0x7401,
+	0xE0C5, 0x7444, 0xE0C6, 0x7487, 0xE0C7, 0x74BF, 0xE0C8, 0x766C,	0xE0C9, 0x79AA, 0xE0CA, 0x7DDA, 0xE0CB, 0x7E55, 0xE0CC, 0x7FA8,
+	0xE0CD, 0x817A, 0xE0CE, 0x81B3, 0xE0CF, 0x8239, 0xE0D0, 0x861A,	0xE0D1, 0x87EC, 0xE0D2, 0x8A75, 0xE0D3, 0x8DE3, 0xE0D4, 0x9078,
+	0xE0D5, 0x9291, 0xE0D6, 0x9425, 0xE0D7, 0x994D, 0xE0D8, 0x9BAE,	0xE0D9, 0x5368, 0xE0DA, 0x5C51, 0xE0DB, 0x6954, 0xE0DC, 0x6CC4,
+	0xE0DD, 0x6D29, 0xE0DE, 0x6E2B, 0xE0DF, 0x820C, 0xE0E0, 0x859B,	0xE0E1, 0x893B, 0xE0E2, 0x8A2D, 0xE0E3, 0x8AAA, 0xE0E4, 0x96EA,
+	0xE0E5, 0x9F67, 0xE0E6, 0x5261, 0xE0E7, 0x66B9, 0xE0E8, 0x6BB2,	0xE0E9, 0x7E96, 0xE0EA, 0x87FE, 0xE0EB, 0x8D0D, 0xE0EC, 0x9583,
+	0xE0ED, 0x965D, 0xE0EE, 0x651D, 0xE0EF, 0x6D89, 0xE0F0, 0x71EE,	0xE0F1, 0xF96E, 0xE0F2, 0x57CE, 0xE0F3, 0x59D3, 0xE0F4, 0x5BAC,
+	0xE0F5, 0x6027, 0xE0F6, 0x60FA, 0xE0F7, 0x6210, 0xE0F8, 0x661F,	0xE0F9, 0x665F, 0xE0FA, 0x7329, 0xE0FB, 0x73F9, 0xE0FC, 0x76DB,
+	0xE0FD, 0x7701, 0xE0FE, 0x7B6C, 0xE1A1, 0x8056, 0xE1A2, 0x8072,	0xE1A3, 0x8165, 0xE1A4, 0x8AA0, 0xE1A5, 0x9192, 0xE1A6, 0x4E16,
+	0xE1A7, 0x52E2, 0xE1A8, 0x6B72, 0xE1A9, 0x6D17, 0xE1AA, 0x7A05,	0xE1AB, 0x7B39, 0xE1AC, 0x7D30, 0xE1AD, 0xF96F, 0xE1AE, 0x8CB0,
+	0xE1AF, 0x53EC, 0xE1B0, 0x562F, 0xE1B1, 0x5851, 0xE1B2, 0x5BB5,	0xE1B3, 0x5C0F, 0xE1B4, 0x5C11, 0xE1B5, 0x5DE2, 0xE1B6, 0x6240,
+	0xE1B7, 0x6383, 0xE1B8, 0x6414, 0xE1B9, 0x662D, 0xE1BA, 0x68B3,	0xE1BB, 0x6CBC, 0xE1BC, 0x6D88, 0xE1BD, 0x6EAF, 0xE1BE, 0x701F,
+	0xE1BF, 0x70A4, 0xE1C0, 0x71D2, 0xE1C1, 0x7526, 0xE1C2, 0x758F,	0xE1C3, 0x758E, 0xE1C4, 0x7619, 0xE1C5, 0x7B11, 0xE1C6, 0x7BE0,
+	0xE1C7, 0x7C2B, 0xE1C8, 0x7D20, 0xE1C9, 0x7D39, 0xE1CA, 0x852C,	0xE1CB, 0x856D, 0xE1CC, 0x8607, 0xE1CD, 0x8A34, 0xE1CE, 0x900D,
+	0xE1CF, 0x9061, 0xE1D0, 0x90B5, 0xE1D1, 0x92B7, 0xE1D2, 0x97F6,	0xE1D3, 0x9A37, 0xE1D4, 0x4FD7, 0xE1D5, 0x5C6C, 0xE1D6, 0x675F,
+	0xE1D7, 0x6D91, 0xE1D8, 0x7C9F, 0xE1D9, 0x7E8C, 0xE1DA, 0x8B16,	0xE1DB, 0x8D16, 0xE1DC, 0x901F, 0xE1DD, 0x5B6B, 0xE1DE, 0x5DFD,
+	0xE1DF, 0x640D, 0xE1E0, 0x84C0, 0xE1E1, 0x905C, 0xE1E2, 0x98E1,	0xE1E3, 0x7387, 0xE1E4, 0x5B8B, 0xE1E5, 0x609A, 0xE1E6, 0x677E,
+	0xE1E7, 0x6DDE, 0xE1E8, 0x8A1F, 0xE1E9, 0x8AA6, 0xE1EA, 0x9001,	0xE1EB, 0x980C, 0xE1EC, 0x5237, 0xE1ED, 0xF970, 0xE1EE, 0x7051,
+	0xE1EF, 0x788E, 0xE1F0, 0x9396, 0xE1F1, 0x8870, 0xE1F2, 0x91D7,	0xE1F3, 0x4FEE, 0xE1F4, 0x53D7, 0xE1F5, 0x55FD, 0xE1F6, 0x56DA,
+	0xE1F7, 0x5782, 0xE1F8, 0x58FD, 0xE1F9, 0x5AC2, 0xE1FA, 0x5B88,	0xE1FB, 0x5CAB, 0xE1FC, 0x5CC0, 0xE1FD, 0x5E25, 0xE1FE, 0x6101,
+	0xE2A1, 0x620D, 0xE2A2, 0x624B, 0xE2A3, 0x6388, 0xE2A4, 0x641C,	0xE2A5, 0x6536, 0xE2A6, 0x6578, 0xE2A7, 0x6A39, 0xE2A8, 0x6B8A,
+	0xE2A9, 0x6C34, 0xE2AA, 0x6D19, 0xE2AB, 0x6F31, 0xE2AC, 0x71E7,	0xE2AD, 0x72E9, 0xE2AE, 0x7378, 0xE2AF, 0x7407, 0xE2B0, 0x74B2,
+	0xE2B1, 0x7626, 0xE2B2, 0x7761, 0xE2B3, 0x79C0, 0xE2B4, 0x7A57,	0xE2B5, 0x7AEA, 0xE2B6, 0x7CB9, 0xE2B7, 0x7D8F, 0xE2B8, 0x7DAC,
+	0xE2B9, 0x7E61, 0xE2BA, 0x7F9E, 0xE2BB, 0x8129, 0xE2BC, 0x8331,	0xE2BD, 0x8490, 0xE2BE, 0x84DA, 0xE2BF, 0x85EA, 0xE2C0, 0x8896,
+	0xE2C1, 0x8AB0, 0xE2C2, 0x8B90, 0xE2C3, 0x8F38, 0xE2C4, 0x9042,	0xE2C5, 0x9083, 0xE2C6, 0x916C, 0xE2C7, 0x9296, 0xE2C8, 0x92B9,
+	0xE2C9, 0x968B, 0xE2CA, 0x96A7, 0xE2CB, 0x96A8, 0xE2CC, 0x96D6,	0xE2CD, 0x9700, 0xE2CE, 0x9808, 0xE2CF, 0x9996, 0xE2D0, 0x9AD3,
+	0xE2D1, 0x9B1A, 0xE2D2, 0x53D4, 0xE2D3, 0x587E, 0xE2D4, 0x5919,	0xE2D5, 0x5B70, 0xE2D6, 0x5BBF, 0xE2D7, 0x6DD1, 0xE2D8, 0x6F5A,
+	0xE2D9, 0x719F, 0xE2DA, 0x7421, 0xE2DB, 0x74B9, 0xE2DC, 0x8085,	0xE2DD, 0x83FD, 0xE2DE, 0x5DE1, 0xE2DF, 0x5F87, 0xE2E0, 0x5FAA,
+	0xE2E1, 0x6042, 0xE2E2, 0x65EC, 0xE2E3, 0x6812, 0xE2E4, 0x696F,	0xE2E5, 0x6A53, 0xE2E6, 0x6B89, 0xE2E7, 0x6D35, 0xE2E8, 0x6DF3,
+	0xE2E9, 0x73E3, 0xE2EA, 0x76FE, 0xE2EB, 0x77AC, 0xE2EC, 0x7B4D,	0xE2ED, 0x7D14, 0xE2EE, 0x8123, 0xE2EF, 0x821C, 0xE2F0, 0x8340,
+	0xE2F1, 0x84F4, 0xE2F2, 0x8563, 0xE2F3, 0x8A62, 0xE2F4, 0x8AC4,	0xE2F5, 0x9187, 0xE2F6, 0x931E, 0xE2F7, 0x9806, 0xE2F8, 0x99B4,
+	0xE2F9, 0x620C, 0xE2FA, 0x8853, 0xE2FB, 0x8FF0, 0xE2FC, 0x9265,	0xE2FD, 0x5D07, 0xE2FE, 0x5D27, 0xE3A1, 0x5D69, 0xE3A2, 0x745F,
+	0xE3A3, 0x819D, 0xE3A4, 0x8768, 0xE3A5, 0x6FD5, 0xE3A6, 0x62FE,	0xE3A7, 0x7FD2, 0xE3A8, 0x8936, 0xE3A9, 0x8972, 0xE3AA, 0x4E1E,
+	0xE3AB, 0x4E58, 0xE3AC, 0x50E7, 0xE3AD, 0x52DD, 0xE3AE, 0x5347,	0xE3AF, 0x627F, 0xE3B0, 0x6607, 0xE3B1, 0x7E69, 0xE3B2, 0x8805,
+	0xE3B3, 0x965E, 0xE3B4, 0x4F8D, 0xE3B5, 0x5319, 0xE3B6, 0x5636,	0xE3B7, 0x59CB, 0xE3B8, 0x5AA4, 0xE3B9, 0x5C38, 0xE3BA, 0x5C4E,
+	0xE3BB, 0x5C4D, 0xE3BC, 0x5E02, 0xE3BD, 0x5F11, 0xE3BE, 0x6043,	0xE3BF, 0x65BD, 0xE3C0, 0x662F, 0xE3C1, 0x6642, 0xE3C2, 0x67BE,
+	0xE3C3, 0x67F4, 0xE3C4, 0x731C, 0xE3C5, 0x77E2, 0xE3C6, 0x793A,	0xE3C7, 0x7FC5, 0xE3C8, 0x8494, 0xE3C9, 0x84CD, 0xE3CA, 0x8996,
+	0xE3CB, 0x8A66, 0xE3CC, 0x8A69, 0xE3CD, 0x8AE1, 0xE3CE, 0x8C55,	0xE3CF, 0x8C7A, 0xE3D0, 0x57F4, 0xE3D1, 0x5BD4, 0xE3D2, 0x5F0F,
+	0xE3D3, 0x606F, 0xE3D4, 0x62ED, 0xE3D5, 0x690D, 0xE3D6, 0x6B96,	0xE3D7, 0x6E5C, 0xE3D8, 0x7184, 0xE3D9, 0x7BD2, 0xE3DA, 0x8755,
+	0xE3DB, 0x8B58, 0xE3DC, 0x8EFE, 0xE3DD, 0x98DF, 0xE3DE, 0x98FE,	0xE3DF, 0x4F38, 0xE3E0, 0x4F81, 0xE3E1, 0x4FE1, 0xE3E2, 0x547B,
+	0xE3E3, 0x5A20, 0xE3E4, 0x5BB8, 0xE3E5, 0x613C, 0xE3E6, 0x65B0,	0xE3E7, 0x6668, 0xE3E8, 0x71FC, 0xE3E9, 0x7533, 0xE3EA, 0x795E,
+	0xE3EB, 0x7D33, 0xE3EC, 0x814E, 0xE3ED, 0x81E3, 0xE3EE, 0x8398,	0xE3EF, 0x85AA, 0xE3F0, 0x85CE, 0xE3F1, 0x8703, 0xE3F2, 0x8A0A,
+	0xE3F3, 0x8EAB, 0xE3F4, 0x8F9B, 0xE3F5, 0xF971, 0xE3F6, 0x8FC5,	0xE3F7, 0x5931, 0xE3F8, 0x5BA4, 0xE3F9, 0x5BE6, 0xE3FA, 0x6089,
+	0xE3FB, 0x5BE9, 0xE3FC, 0x5C0B, 0xE3FD, 0x5FC3, 0xE3FE, 0x6C81,	0xE4A1, 0xF972, 0xE4A2, 0x6DF1, 0xE4A3, 0x700B, 0xE4A4, 0x751A,
+	0xE4A5, 0x82AF, 0xE4A6, 0x8AF6, 0xE4A7, 0x4EC0, 0xE4A8, 0x5341,	0xE4A9, 0xF973, 0xE4AA, 0x96D9, 0xE4AB, 0x6C0F, 0xE4AC, 0x4E9E,
+	0xE4AD, 0x4FC4, 0xE4AE, 0x5152, 0xE4AF, 0x555E, 0xE4B0, 0x5A25,	0xE4B1, 0x5CE8, 0xE4B2, 0x6211, 0xE4B3, 0x7259, 0xE4B4, 0x82BD,
+	0xE4B5, 0x83AA, 0xE4B6, 0x86FE, 0xE4B7, 0x8859, 0xE4B8, 0x8A1D,	0xE4B9, 0x963F, 0xE4BA, 0x96C5, 0xE4BB, 0x9913, 0xE4BC, 0x9D09,
+	0xE4BD, 0x9D5D, 0xE4BE, 0x580A, 0xE4BF, 0x5CB3, 0xE4C0, 0x5DBD,	0xE4C1, 0x5E44, 0xE4C2, 0x60E1, 0xE4C3, 0x6115, 0xE4C4, 0x63E1,
+	0xE4C5, 0x6A02, 0xE4C6, 0x6E25, 0xE4C7, 0x9102, 0xE4C8, 0x9354,	0xE4C9, 0x984E, 0xE4CA, 0x9C10, 0xE4CB, 0x9F77, 0xE4CC, 0x5B89,
+	0xE4CD, 0x5CB8, 0xE4CE, 0x6309, 0xE4CF, 0x664F, 0xE4D0, 0x6848,	0xE4D1, 0x773C, 0xE4D2, 0x96C1, 0xE4D3, 0x978D, 0xE4D4, 0x9854,
+	0xE4D5, 0x9B9F, 0xE4D6, 0x65A1, 0xE4D7, 0x8B01, 0xE4D8, 0x8ECB,	0xE4D9, 0x95BC, 0xE4DA, 0x5535, 0xE4DB, 0x5CA9, 0xE4DC, 0x5DD6,
+	0xE4DD, 0x5EB5, 0xE4DE, 0x6697, 0xE4DF, 0x764C, 0xE4E0, 0x83F4,	0xE4E1, 0x95C7, 0xE4E2, 0x58D3, 0xE4E3, 0x62BC, 0xE4E4, 0x72CE,
+	0xE4E5, 0x9D28, 0xE4E6, 0x4EF0, 0xE4E7, 0x592E, 0xE4E8, 0x600F,	0xE4E9, 0x663B, 0xE4EA, 0x6B83, 0xE4EB, 0x79E7, 0xE4EC, 0x9D26,
+	0xE4ED, 0x5393, 0xE4EE, 0x54C0, 0xE4EF, 0x57C3, 0xE4F0, 0x5D16,	0xE4F1, 0x611B, 0xE4F2, 0x66D6, 0xE4F3, 0x6DAF, 0xE4F4, 0x788D,
+	0xE4F5, 0x827E, 0xE4F6, 0x9698, 0xE4F7, 0x9744, 0xE4F8, 0x5384,	0xE4F9, 0x627C, 0xE4FA, 0x6396, 0xE4FB, 0x6DB2, 0xE4FC, 0x7E0A,
+	0xE4FD, 0x814B, 0xE4FE, 0x984D, 0xE5A1, 0x6AFB, 0xE5A2, 0x7F4C,	0xE5A3, 0x9DAF, 0xE5A4, 0x9E1A, 0xE5A5, 0x4E5F, 0xE5A6, 0x503B,
+	0xE5A7, 0x51B6, 0xE5A8, 0x591C, 0xE5A9, 0x60F9, 0xE5AA, 0x63F6,	0xE5AB, 0x6930, 0xE5AC, 0x723A, 0xE5AD, 0x8036, 0xE5AE, 0xF974,
+	0xE5AF, 0x91CE, 0xE5B0, 0x5F31, 0xE5B1, 0xF975, 0xE5B2, 0xF976,	0xE5B3, 0x7D04, 0xE5B4, 0x82E5, 0xE5B5, 0x846F, 0xE5B6, 0x84BB,
+	0xE5B7, 0x85E5, 0xE5B8, 0x8E8D, 0xE5B9, 0xF977, 0xE5BA, 0x4F6F,	0xE5BB, 0xF978, 0xE5BC, 0xF979, 0xE5BD, 0x58E4, 0xE5BE, 0x5B43,
+	0xE5BF, 0x6059, 0xE5C0, 0x63DA, 0xE5C1, 0x6518, 0xE5C2, 0x656D,	0xE5C3, 0x6698, 0xE5C4, 0xF97A, 0xE5C5, 0x694A, 0xE5C6, 0x6A23,
+	0xE5C7, 0x6D0B, 0xE5C8, 0x7001, 0xE5C9, 0x716C, 0xE5CA, 0x75D2,	0xE5CB, 0x760D, 0xE5CC, 0x79B3, 0xE5CD, 0x7A70, 0xE5CE, 0xF97B,
+	0xE5CF, 0x7F8A, 0xE5D0, 0xF97C, 0xE5D1, 0x8944, 0xE5D2, 0xF97D,	0xE5D3, 0x8B93, 0xE5D4, 0x91C0, 0xE5D5, 0x967D, 0xE5D6, 0xF97E,
+	0xE5D7, 0x990A, 0xE5D8, 0x5704, 0xE5D9, 0x5FA1, 0xE5DA, 0x65BC,	0xE5DB, 0x6F01, 0xE5DC, 0x7600, 0xE5DD, 0x79A6, 0xE5DE, 0x8A9E,
+	0xE5DF, 0x99AD, 0xE5E0, 0x9B5A, 0xE5E1, 0x9F6C, 0xE5E2, 0x5104,	0xE5E3, 0x61B6, 0xE5E4, 0x6291, 0xE5E5, 0x6A8D, 0xE5E6, 0x81C6,
+	0xE5E7, 0x5043, 0xE5E8, 0x5830, 0xE5E9, 0x5F66, 0xE5EA, 0x7109,	0xE5EB, 0x8A00, 0xE5EC, 0x8AFA, 0xE5ED, 0x5B7C, 0xE5EE, 0x8616,
+	0xE5EF, 0x4FFA, 0xE5F0, 0x513C, 0xE5F1, 0x56B4, 0xE5F2, 0x5944,	0xE5F3, 0x63A9, 0xE5F4, 0x6DF9, 0xE5F5, 0x5DAA, 0xE5F6, 0x696D,
+	0xE5F7, 0x5186, 0xE5F8, 0x4E88, 0xE5F9, 0x4F59, 0xE5FA, 0xF97F,	0xE5FB, 0xF980, 0xE5FC, 0xF981, 0xE5FD, 0x5982, 0xE5FE, 0xF982,
+	0xE6A1, 0xF983, 0xE6A2, 0x6B5F, 0xE6A3, 0x6C5D, 0xE6A4, 0xF984,	0xE6A5, 0x74B5, 0xE6A6, 0x7916, 0xE6A7, 0xF985, 0xE6A8, 0x8207,
+	0xE6A9, 0x8245, 0xE6AA, 0x8339, 0xE6AB, 0x8F3F, 0xE6AC, 0x8F5D,	0xE6AD, 0xF986, 0xE6AE, 0x9918, 0xE6AF, 0xF987, 0xE6B0, 0xF988,
+	0xE6B1, 0xF989, 0xE6B2, 0x4EA6, 0xE6B3, 0xF98A, 0xE6B4, 0x57DF,	0xE6B5, 0x5F79, 0xE6B6, 0x6613, 0xE6B7, 0xF98B, 0xE6B8, 0xF98C,
+	0xE6B9, 0x75AB, 0xE6BA, 0x7E79, 0xE6BB, 0x8B6F, 0xE6BC, 0xF98D,	0xE6BD, 0x9006, 0xE6BE, 0x9A5B, 0xE6BF, 0x56A5, 0xE6C0, 0x5827,
+	0xE6C1, 0x59F8, 0xE6C2, 0x5A1F, 0xE6C3, 0x5BB4, 0xE6C4, 0xF98E,	0xE6C5, 0x5EF6, 0xE6C6, 0xF98F, 0xE6C7, 0xF990, 0xE6C8, 0x6350,
+	0xE6C9, 0x633B, 0xE6CA, 0xF991, 0xE6CB, 0x693D, 0xE6CC, 0x6C87,	0xE6CD, 0x6CBF, 0xE6CE, 0x6D8E, 0xE6CF, 0x6D93, 0xE6D0, 0x6DF5,
+	0xE6D1, 0x6F14, 0xE6D2, 0xF992, 0xE6D3, 0x70DF, 0xE6D4, 0x7136,	0xE6D5, 0x7159, 0xE6D6, 0xF993, 0xE6D7, 0x71C3, 0xE6D8, 0x71D5,
+	0xE6D9, 0xF994, 0xE6DA, 0x784F, 0xE6DB, 0x786F, 0xE6DC, 0xF995,	0xE6DD, 0x7B75, 0xE6DE, 0x7DE3, 0xE6DF, 0xF996, 0xE6E0, 0x7E2F,
+	0xE6E1, 0xF997, 0xE6E2, 0x884D, 0xE6E3, 0x8EDF, 0xE6E4, 0xF998,	0xE6E5, 0xF999, 0xE6E6, 0xF99A, 0xE6E7, 0x925B, 0xE6E8, 0xF99B,
+	0xE6E9, 0x9CF6, 0xE6EA, 0xF99C, 0xE6EB, 0xF99D, 0xE6EC, 0xF99E,	0xE6ED, 0x6085, 0xE6EE, 0x6D85, 0xE6EF, 0xF99F, 0xE6F0, 0x71B1,
+	0xE6F1, 0xF9A0, 0xE6F2, 0xF9A1, 0xE6F3, 0x95B1, 0xE6F4, 0x53AD,	0xE6F5, 0xF9A2, 0xE6F6, 0xF9A3, 0xE6F7, 0xF9A4, 0xE6F8, 0x67D3,
+	0xE6F9, 0xF9A5, 0xE6FA, 0x708E, 0xE6FB, 0x7130, 0xE6FC, 0x7430,	0xE6FD, 0x8276, 0xE6FE, 0x82D2, 0xE7A1, 0xF9A6, 0xE7A2, 0x95BB,
+	0xE7A3, 0x9AE5, 0xE7A4, 0x9E7D, 0xE7A5, 0x66C4, 0xE7A6, 0xF9A7,	0xE7A7, 0x71C1, 0xE7A8, 0x8449, 0xE7A9, 0xF9A8, 0xE7AA, 0xF9A9,
+	0xE7AB, 0x584B, 0xE7AC, 0xF9AA, 0xE7AD, 0xF9AB, 0xE7AE, 0x5DB8,	0xE7AF, 0x5F71, 0xE7B0, 0xF9AC, 0xE7B1, 0x6620, 0xE7B2, 0x668E,
+	0xE7B3, 0x6979, 0xE7B4, 0x69AE, 0xE7B5, 0x6C38, 0xE7B6, 0x6CF3,	0xE7B7, 0x6E36, 0xE7B8, 0x6F41, 0xE7B9, 0x6FDA, 0xE7BA, 0x701B,
+	0xE7BB, 0x702F, 0xE7BC, 0x7150, 0xE7BD, 0x71DF, 0xE7BE, 0x7370,	0xE7BF, 0xF9AD, 0xE7C0, 0x745B, 0xE7C1, 0xF9AE, 0xE7C2, 0x74D4,
+	0xE7C3, 0x76C8, 0xE7C4, 0x7A4E, 0xE7C5, 0x7E93, 0xE7C6, 0xF9AF,	0xE7C7, 0xF9B0, 0xE7C8, 0x82F1, 0xE7C9, 0x8A60, 0xE7CA, 0x8FCE,
+	0xE7CB, 0xF9B1, 0xE7CC, 0x9348, 0xE7CD, 0xF9B2, 0xE7CE, 0x9719,	0xE7CF, 0xF9B3, 0xE7D0, 0xF9B4, 0xE7D1, 0x4E42, 0xE7D2, 0x502A,
+	0xE7D3, 0xF9B5, 0xE7D4, 0x5208, 0xE7D5, 0x53E1, 0xE7D6, 0x66F3,	0xE7D7, 0x6C6D, 0xE7D8, 0x6FCA, 0xE7D9, 0x730A, 0xE7DA, 0x777F,
+	0xE7DB, 0x7A62, 0xE7DC, 0x82AE, 0xE7DD, 0x85DD, 0xE7DE, 0x8602,	0xE7DF, 0xF9B6, 0xE7E0, 0x88D4, 0xE7E1, 0x8A63, 0xE7E2, 0x8B7D,
+	0xE7E3, 0x8C6B, 0xE7E4, 0xF9B7, 0xE7E5, 0x92B3, 0xE7E6, 0xF9B8,	0xE7E7, 0x9713, 0xE7E8, 0x9810, 0xE7E9, 0x4E94, 0xE7EA, 0x4F0D,
+	0xE7EB, 0x4FC9, 0xE7EC, 0x50B2, 0xE7ED, 0x5348, 0xE7EE, 0x543E,	0xE7EF, 0x5433, 0xE7F0, 0x55DA, 0xE7F1, 0x5862, 0xE7F2, 0x58BA,
+	0xE7F3, 0x5967, 0xE7F4, 0x5A1B, 0xE7F5, 0x5BE4, 0xE7F6, 0x609F,	0xE7F7, 0xF9B9, 0xE7F8, 0x61CA, 0xE7F9, 0x6556, 0xE7FA, 0x65FF,
+	0xE7FB, 0x6664, 0xE7FC, 0x68A7, 0xE7FD, 0x6C5A, 0xE7FE, 0x6FB3,	0xE8A1, 0x70CF, 0xE8A2, 0x71AC, 0xE8A3, 0x7352, 0xE8A4, 0x7B7D,
+	0xE8A5, 0x8708, 0xE8A6, 0x8AA4, 0xE8A7, 0x9C32, 0xE8A8, 0x9F07,	0xE8A9, 0x5C4B, 0xE8AA, 0x6C83, 0xE8AB, 0x7344, 0xE8AC, 0x7389,
+	0xE8AD, 0x923A, 0xE8AE, 0x6EAB, 0xE8AF, 0x7465, 0xE8B0, 0x761F,	0xE8B1, 0x7A69, 0xE8B2, 0x7E15, 0xE8B3, 0x860A, 0xE8B4, 0x5140,
+	0xE8B5, 0x58C5, 0xE8B6, 0x64C1, 0xE8B7, 0x74EE, 0xE8B8, 0x7515,	0xE8B9, 0x7670, 0xE8BA, 0x7FC1, 0xE8BB, 0x9095, 0xE8BC, 0x96CD,
+	0xE8BD, 0x9954, 0xE8BE, 0x6E26, 0xE8BF, 0x74E6, 0xE8C0, 0x7AA9,	0xE8C1, 0x7AAA, 0xE8C2, 0x81E5, 0xE8C3, 0x86D9, 0xE8C4, 0x8778,
+	0xE8C5, 0x8A1B, 0xE8C6, 0x5A49, 0xE8C7, 0x5B8C, 0xE8C8, 0x5B9B,	0xE8C9, 0x68A1, 0xE8CA, 0x6900, 0xE8CB, 0x6D63, 0xE8CC, 0x73A9,
+	0xE8CD, 0x7413, 0xE8CE, 0x742C, 0xE8CF, 0x7897, 0xE8D0, 0x7DE9,	0xE8D1, 0x7FEB, 0xE8D2, 0x8118, 0xE8D3, 0x8155, 0xE8D4, 0x839E,
+	0xE8D5, 0x8C4C, 0xE8D6, 0x962E, 0xE8D7, 0x9811, 0xE8D8, 0x66F0,	0xE8D9, 0x5F80, 0xE8DA, 0x65FA, 0xE8DB, 0x6789, 0xE8DC, 0x6C6A,
+	0xE8DD, 0x738B, 0xE8DE, 0x502D, 0xE8DF, 0x5A03, 0xE8E0, 0x6B6A,	0xE8E1, 0x77EE, 0xE8E2, 0x5916, 0xE8E3, 0x5D6C, 0xE8E4, 0x5DCD,
+	0xE8E5, 0x7325, 0xE8E6, 0x754F, 0xE8E7, 0xF9BA, 0xE8E8, 0xF9BB,	0xE8E9, 0x50E5, 0xE8EA, 0x51F9, 0xE8EB, 0x582F, 0xE8EC, 0x592D,
+	0xE8ED, 0x5996, 0xE8EE, 0x59DA, 0xE8EF, 0x5BE5, 0xE8F0, 0xF9BC,	0xE8F1, 0xF9BD, 0xE8F2, 0x5DA2, 0xE8F3, 0x62D7, 0xE8F4, 0x6416,
+	0xE8F5, 0x6493, 0xE8F6, 0x64FE, 0xE8F7, 0xF9BE, 0xE8F8, 0x66DC,	0xE8F9, 0xF9BF, 0xE8FA, 0x6A48, 0xE8FB, 0xF9C0, 0xE8FC, 0x71FF,
+	0xE8FD, 0x7464, 0xE8FE, 0xF9C1, 0xE9A1, 0x7A88, 0xE9A2, 0x7AAF,	0xE9A3, 0x7E47, 0xE9A4, 0x7E5E, 0xE9A5, 0x8000, 0xE9A6, 0x8170,
+	0xE9A7, 0xF9C2, 0xE9A8, 0x87EF, 0xE9A9, 0x8981, 0xE9AA, 0x8B20,	0xE9AB, 0x9059, 0xE9AC, 0xF9C3, 0xE9AD, 0x9080, 0xE9AE, 0x9952,
+	0xE9AF, 0x617E, 0xE9B0, 0x6B32, 0xE9B1, 0x6D74, 0xE9B2, 0x7E1F,	0xE9B3, 0x8925, 0xE9B4, 0x8FB1, 0xE9B5, 0x4FD1, 0xE9B6, 0x50AD,
+	0xE9B7, 0x5197, 0xE9B8, 0x52C7, 0xE9B9, 0x57C7, 0xE9BA, 0x5889,	0xE9BB, 0x5BB9, 0xE9BC, 0x5EB8, 0xE9BD, 0x6142, 0xE9BE, 0x6995,
+	0xE9BF, 0x6D8C, 0xE9C0, 0x6E67, 0xE9C1, 0x6EB6, 0xE9C2, 0x7194,	0xE9C3, 0x7462, 0xE9C4, 0x7528, 0xE9C5, 0x752C, 0xE9C6, 0x8073,
+	0xE9C7, 0x8338, 0xE9C8, 0x84C9, 0xE9C9, 0x8E0A, 0xE9CA, 0x9394,	0xE9CB, 0x93DE, 0xE9CC, 0xF9C4, 0xE9CD, 0x4E8E, 0xE9CE, 0x4F51,
+	0xE9CF, 0x5076, 0xE9D0, 0x512A, 0xE9D1, 0x53C8, 0xE9D2, 0x53CB,	0xE9D3, 0x53F3, 0xE9D4, 0x5B87, 0xE9D5, 0x5BD3, 0xE9D6, 0x5C24,
+	0xE9D7, 0x611A, 0xE9D8, 0x6182, 0xE9D9, 0x65F4, 0xE9DA, 0x725B,	0xE9DB, 0x7397, 0xE9DC, 0x7440, 0xE9DD, 0x76C2, 0xE9DE, 0x7950,
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+	0xE9E7, 0x9047, 0xE9E8, 0x90F5, 0xE9E9, 0x91EA, 0xE9EA, 0x9685,	0xE9EB, 0x96E8, 0xE9EC, 0x96E9, 0xE9ED, 0x52D6, 0xE9EE, 0x5F67,
+	0xE9EF, 0x65ED, 0xE9F0, 0x6631, 0xE9F1, 0x682F, 0xE9F2, 0x715C,	0xE9F3, 0x7A36, 0xE9F4, 0x90C1, 0xE9F5, 0x980A, 0xE9F6, 0x4E91,
+	0xE9F7, 0xF9C5, 0xE9F8, 0x6A52, 0xE9F9, 0x6B9E, 0xE9FA, 0x6F90,	0xE9FB, 0x7189, 0xE9FC, 0x8018, 0xE9FD, 0x82B8, 0xE9FE, 0x8553,
+	0xEAA1, 0x904B, 0xEAA2, 0x9695, 0xEAA3, 0x96F2, 0xEAA4, 0x97FB,	0xEAA5, 0x851A, 0xEAA6, 0x9B31, 0xEAA7, 0x4E90, 0xEAA8, 0x718A,
+	0xEAA9, 0x96C4, 0xEAAA, 0x5143, 0xEAAB, 0x539F, 0xEAAC, 0x54E1,	0xEAAD, 0x5713, 0xEAAE, 0x5712, 0xEAAF, 0x57A3, 0xEAB0, 0x5A9B,
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+	0xEAC9, 0x5049, 0xEACA, 0x50DE, 0xEACB, 0x5371, 0xEACC, 0x570D,	0xEACD, 0x59D4, 0xEACE, 0x5A01, 0xEACF, 0x5C09, 0xEAD0, 0x6170,
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+	0xEAE9, 0x5BA5, 0xEAEA, 0x5E7C, 0xEAEB, 0x5E7D, 0xEAEC, 0x5EBE,	0xEAED, 0x60A0, 0xEAEE, 0x60DF, 0xEAEF, 0x6108, 0xEAF0, 0x6109,
+	0xEAF1, 0x63C4, 0xEAF2, 0x6538, 0xEAF3, 0x6709, 0xEAF4, 0xF9C8,	0xEAF5, 0x67D4, 0xEAF6, 0x67DA, 0xEAF7, 0xF9C9, 0xEAF8, 0x6961,
+	0xEAF9, 0x6962, 0xEAFA, 0x6CB9, 0xEAFB, 0x6D27, 0xEAFC, 0xF9CA,	0xEAFD, 0x6E38, 0xEAFE, 0xF9CB, 0xEBA1, 0x6FE1, 0xEBA2, 0x7336,
+	0xEBA3, 0x7337, 0xEBA4, 0xF9CC, 0xEBA5, 0x745C, 0xEBA6, 0x7531,	0xEBA7, 0xF9CD, 0xEBA8, 0x7652, 0xEBA9, 0xF9CE, 0xEBAA, 0xF9CF,
+	0xEBAB, 0x7DAD, 0xEBAC, 0x81FE, 0xEBAD, 0x8438, 0xEBAE, 0x88D5,	0xEBAF, 0x8A98, 0xEBB0, 0x8ADB, 0xEBB1, 0x8AED, 0xEBB2, 0x8E30,
+	0xEBB3, 0x8E42, 0xEBB4, 0x904A, 0xEBB5, 0x903E, 0xEBB6, 0x907A,	0xEBB7, 0x9149, 0xEBB8, 0x91C9, 0xEBB9, 0x936E, 0xEBBA, 0xF9D0,
+	0xEBBB, 0xF9D1, 0xEBBC, 0x5809, 0xEBBD, 0xF9D2, 0xEBBE, 0x6BD3,	0xEBBF, 0x8089, 0xEBC0, 0x80B2, 0xEBC1, 0xF9D3, 0xEBC2, 0xF9D4,
+	0xEBC3, 0x5141, 0xEBC4, 0x596B, 0xEBC5, 0x5C39, 0xEBC6, 0xF9D5,	0xEBC7, 0xF9D6, 0xEBC8, 0x6F64, 0xEBC9, 0x73A7, 0xEBCA, 0x80E4,
+	0xEBCB, 0x8D07, 0xEBCC, 0xF9D7, 0xEBCD, 0x9217, 0xEBCE, 0x958F,	0xEBCF, 0xF9D8, 0xEBD0, 0xF9D9, 0xEBD1, 0xF9DA, 0xEBD2, 0xF9DB,
+	0xEBD3, 0x807F, 0xEBD4, 0x620E, 0xEBD5, 0x701C, 0xEBD6, 0x7D68,	0xEBD7, 0x878D, 0xEBD8, 0xF9DC, 0xEBD9, 0x57A0, 0xEBDA, 0x6069,
+	0xEBDB, 0x6147, 0xEBDC, 0x6BB7, 0xEBDD, 0x8ABE, 0xEBDE, 0x9280,	0xEBDF, 0x96B1, 0xEBE0, 0x4E59, 0xEBE1, 0x541F, 0xEBE2, 0x6DEB,
+	0xEBE3, 0x852D, 0xEBE4, 0x9670, 0xEBE5, 0x97F3, 0xEBE6, 0x98EE,	0xEBE7, 0x63D6, 0xEBE8, 0x6CE3, 0xEBE9, 0x9091, 0xEBEA, 0x51DD,
+	0xEBEB, 0x61C9, 0xEBEC, 0x81BA, 0xEBED, 0x9DF9, 0xEBEE, 0x4F9D,	0xEBEF, 0x501A, 0xEBF0, 0x5100, 0xEBF1, 0x5B9C, 0xEBF2, 0x610F,
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+	0xEBFB, 0x858F, 0xEBFC, 0x87FB, 0xEBFD, 0x8863, 0xEBFE, 0x8ABC,	0xECA1, 0x8B70, 0xECA2, 0x91AB, 0xECA3, 0x4E8C, 0xECA4, 0x4EE5,
+	0xECA5, 0x4F0A, 0xECA6, 0xF9DD, 0xECA7, 0xF9DE, 0xECA8, 0x5937,	0xECA9, 0x59E8, 0xECAA, 0xF9DF, 0xECAB, 0x5DF2, 0xECAC, 0x5F1B,
+	0xECAD, 0x5F5B, 0xECAE, 0x6021, 0xECAF, 0xF9E0, 0xECB0, 0xF9E1,	0xECB1, 0xF9E2, 0xECB2, 0xF9E3, 0xECB3, 0x723E, 0xECB4, 0x73E5,
+	0xECB5, 0xF9E4, 0xECB6, 0x7570, 0xECB7, 0x75CD, 0xECB8, 0xF9E5,	0xECB9, 0x79FB, 0xECBA, 0xF9E6, 0xECBB, 0x800C, 0xECBC, 0x8033,
+	0xECBD, 0x8084, 0xECBE, 0x82E1, 0xECBF, 0x8351, 0xECC0, 0xF9E7,	0xECC1, 0xF9E8, 0xECC2, 0x8CBD, 0xECC3, 0x8CB3, 0xECC4, 0x9087,
+	0xECC5, 0xF9E9, 0xECC6, 0xF9EA, 0xECC7, 0x98F4, 0xECC8, 0x990C,	0xECC9, 0xF9EB, 0xECCA, 0xF9EC, 0xECCB, 0x7037, 0xECCC, 0x76CA,
+	0xECCD, 0x7FCA, 0xECCE, 0x7FCC, 0xECCF, 0x7FFC, 0xECD0, 0x8B1A,	0xECD1, 0x4EBA, 0xECD2, 0x4EC1, 0xECD3, 0x5203, 0xECD4, 0x5370,
+	0xECD5, 0xF9ED, 0xECD6, 0x54BD, 0xECD7, 0x56E0, 0xECD8, 0x59FB,	0xECD9, 0x5BC5, 0xECDA, 0x5F15, 0xECDB, 0x5FCD, 0xECDC, 0x6E6E,
+	0xECDD, 0xF9EE, 0xECDE, 0xF9EF, 0xECDF, 0x7D6A, 0xECE0, 0x8335,	0xECE1, 0xF9F0, 0xECE2, 0x8693, 0xECE3, 0x8A8D, 0xECE4, 0xF9F1,
+	0xECE5, 0x976D, 0xECE6, 0x9777, 0xECE7, 0xF9F2, 0xECE8, 0xF9F3,	0xECE9, 0x4E00, 0xECEA, 0x4F5A, 0xECEB, 0x4F7E, 0xECEC, 0x58F9,
+	0xECED, 0x65E5, 0xECEE, 0x6EA2, 0xECEF, 0x9038, 0xECF0, 0x93B0,	0xECF1, 0x99B9, 0xECF2, 0x4EFB, 0xECF3, 0x58EC, 0xECF4, 0x598A,
+	0xECF5, 0x59D9, 0xECF6, 0x6041, 0xECF7, 0xF9F4, 0xECF8, 0xF9F5,	0xECF9, 0x7A14, 0xECFA, 0xF9F6, 0xECFB, 0x834F, 0xECFC, 0x8CC3,
+	0xECFD, 0x5165, 0xECFE, 0x5344, 0xEDA1, 0xF9F7, 0xEDA2, 0xF9F8,	0xEDA3, 0xF9F9, 0xEDA4, 0x4ECD, 0xEDA5, 0x5269, 0xEDA6, 0x5B55,
+	0xEDA7, 0x82BF, 0xEDA8, 0x4ED4, 0xEDA9, 0x523A, 0xEDAA, 0x54A8,	0xEDAB, 0x59C9, 0xEDAC, 0x59FF, 0xEDAD, 0x5B50, 0xEDAE, 0x5B57,
+	0xEDAF, 0x5B5C, 0xEDB0, 0x6063, 0xEDB1, 0x6148, 0xEDB2, 0x6ECB,	0xEDB3, 0x7099, 0xEDB4, 0x716E, 0xEDB5, 0x7386, 0xEDB6, 0x74F7,
+	0xEDB7, 0x75B5, 0xEDB8, 0x78C1, 0xEDB9, 0x7D2B, 0xEDBA, 0x8005,	0xEDBB, 0x81EA, 0xEDBC, 0x8328, 0xEDBD, 0x8517, 0xEDBE, 0x85C9,
+	0xEDBF, 0x8AEE, 0xEDC0, 0x8CC7, 0xEDC1, 0x96CC, 0xEDC2, 0x4F5C,	0xEDC3, 0x52FA, 0xEDC4, 0x56BC, 0xEDC5, 0x65AB, 0xEDC6, 0x6628,
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+	0xEDCF, 0x5B71, 0xEDD0, 0x68E7, 0xEDD1, 0x6B98, 0xEDD2, 0x6F7A,	0xEDD3, 0x76DE, 0xEDD4, 0x5C91, 0xEDD5, 0x66AB, 0xEDD6, 0x6F5B,
+	0xEDD7, 0x7BB4, 0xEDD8, 0x7C2A, 0xEDD9, 0x8836, 0xEDDA, 0x96DC,	0xEDDB, 0x4E08, 0xEDDC, 0x4ED7, 0xEDDD, 0x5320, 0xEDDE, 0x5834,
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+	0xEDE7, 0x66B2, 0xEDE8, 0x6756, 0xEDE9, 0x6A1F, 0xEDEA, 0x6AA3,	0xEDEB, 0x6B0C, 0xEDEC, 0x6F3F, 0xEDED, 0x7246, 0xEDEE, 0xF9FA,
+	0xEDEF, 0x7350, 0xEDF0, 0x748B, 0xEDF1, 0x7AE0, 0xEDF2, 0x7CA7,	0xEDF3, 0x8178, 0xEDF4, 0x81DF, 0xEDF5, 0x81E7, 0xEDF6, 0x838A,
+	0xEDF7, 0x846C, 0xEDF8, 0x8523, 0xEDF9, 0x8594, 0xEDFA, 0x85CF,	0xEDFB, 0x88DD, 0xEDFC, 0x8D13, 0xEDFD, 0x91AC, 0xEDFE, 0x9577,
+	0xEEA1, 0x969C, 0xEEA2, 0x518D, 0xEEA3, 0x54C9, 0xEEA4, 0x5728,	0xEEA5, 0x5BB0, 0xEEA6, 0x624D, 0xEEA7, 0x6750, 0xEEA8, 0x683D,
+	0xEEA9, 0x6893, 0xEEAA, 0x6E3D, 0xEEAB, 0x6ED3, 0xEEAC, 0x707D,	0xEEAD, 0x7E21, 0xEEAE, 0x88C1, 0xEEAF, 0x8CA1, 0xEEB0, 0x8F09,
+	0xEEB1, 0x9F4B, 0xEEB2, 0x9F4E, 0xEEB3, 0x722D, 0xEEB4, 0x7B8F,	0xEEB5, 0x8ACD, 0xEEB6, 0x931A, 0xEEB7, 0x4F47, 0xEEB8, 0x4F4E,
+	0xEEB9, 0x5132, 0xEEBA, 0x5480, 0xEEBB, 0x59D0, 0xEEBC, 0x5E95,	0xEEBD, 0x62B5, 0xEEBE, 0x6775, 0xEEBF, 0x696E, 0xEEC0, 0x6A17,
+	0xEEC1, 0x6CAE, 0xEEC2, 0x6E1A, 0xEEC3, 0x72D9, 0xEEC4, 0x732A,	0xEEC5, 0x75BD, 0xEEC6, 0x7BB8, 0xEEC7, 0x7D35, 0xEEC8, 0x82E7,
+	0xEEC9, 0x83F9, 0xEECA, 0x8457, 0xEECB, 0x85F7, 0xEECC, 0x8A5B,	0xEECD, 0x8CAF, 0xEECE, 0x8E87, 0xEECF, 0x9019, 0xEED0, 0x90B8,
+	0xEED1, 0x96CE, 0xEED2, 0x9F5F, 0xEED3, 0x52E3, 0xEED4, 0x540A,	0xEED5, 0x5AE1, 0xEED6, 0x5BC2, 0xEED7, 0x6458, 0xEED8, 0x6575,
+	0xEED9, 0x6EF4, 0xEEDA, 0x72C4, 0xEEDB, 0xF9FB, 0xEEDC, 0x7684,	0xEEDD, 0x7A4D, 0xEEDE, 0x7B1B, 0xEEDF, 0x7C4D, 0xEEE0, 0x7E3E,
+	0xEEE1, 0x7FDF, 0xEEE2, 0x837B, 0xEEE3, 0x8B2B, 0xEEE4, 0x8CCA,	0xEEE5, 0x8D64, 0xEEE6, 0x8DE1, 0xEEE7, 0x8E5F, 0xEEE8, 0x8FEA,
+	0xEEE9, 0x8FF9, 0xEEEA, 0x9069, 0xEEEB, 0x93D1, 0xEEEC, 0x4F43,	0xEEED, 0x4F7A, 0xEEEE, 0x50B3, 0xEEEF, 0x5168, 0xEEF0, 0x5178,
+	0xEEF1, 0x524D, 0xEEF2, 0x526A, 0xEEF3, 0x5861, 0xEEF4, 0x587C,	0xEEF5, 0x5960, 0xEEF6, 0x5C08, 0xEEF7, 0x5C55, 0xEEF8, 0x5EDB,
+	0xEEF9, 0x609B, 0xEEFA, 0x6230, 0xEEFB, 0x6813, 0xEEFC, 0x6BBF,	0xEEFD, 0x6C08, 0xEEFE, 0x6FB1, 0xEFA1, 0x714E, 0xEFA2, 0x7420,
+	0xEFA3, 0x7530, 0xEFA4, 0x7538, 0xEFA5, 0x7551, 0xEFA6, 0x7672,	0xEFA7, 0x7B4C, 0xEFA8, 0x7B8B, 0xEFA9, 0x7BAD, 0xEFAA, 0x7BC6,
+	0xEFAB, 0x7E8F, 0xEFAC, 0x8A6E, 0xEFAD, 0x8F3E, 0xEFAE, 0x8F49,	0xEFAF, 0x923F, 0xEFB0, 0x9293, 0xEFB1, 0x9322, 0xEFB2, 0x942B,
+	0xEFB3, 0x96FB, 0xEFB4, 0x985A, 0xEFB5, 0x986B, 0xEFB6, 0x991E,	0xEFB7, 0x5207, 0xEFB8, 0x622A, 0xEFB9, 0x6298, 0xEFBA, 0x6D59,
+	0xEFBB, 0x7664, 0xEFBC, 0x7ACA, 0xEFBD, 0x7BC0, 0xEFBE, 0x7D76,	0xEFBF, 0x5360, 0xEFC0, 0x5CBE, 0xEFC1, 0x5E97, 0xEFC2, 0x6F38,
+	0xEFC3, 0x70B9, 0xEFC4, 0x7C98, 0xEFC5, 0x9711, 0xEFC6, 0x9B8E,	0xEFC7, 0x9EDE, 0xEFC8, 0x63A5, 0xEFC9, 0x647A, 0xEFCA, 0x8776,
+	0xEFCB, 0x4E01, 0xEFCC, 0x4E95, 0xEFCD, 0x4EAD, 0xEFCE, 0x505C,	0xEFCF, 0x5075, 0xEFD0, 0x5448, 0xEFD1, 0x59C3, 0xEFD2, 0x5B9A,
+	0xEFD3, 0x5E40, 0xEFD4, 0x5EAD, 0xEFD5, 0x5EF7, 0xEFD6, 0x5F81,	0xEFD7, 0x60C5, 0xEFD8, 0x633A, 0xEFD9, 0x653F, 0xEFDA, 0x6574,
+	0xEFDB, 0x65CC, 0xEFDC, 0x6676, 0xEFDD, 0x6678, 0xEFDE, 0x67FE,	0xEFDF, 0x6968, 0xEFE0, 0x6A89, 0xEFE1, 0x6B63, 0xEFE2, 0x6C40,
+	0xEFE3, 0x6DC0, 0xEFE4, 0x6DE8, 0xEFE5, 0x6E1F, 0xEFE6, 0x6E5E,	0xEFE7, 0x701E, 0xEFE8, 0x70A1, 0xEFE9, 0x738E, 0xEFEA, 0x73FD,
+	0xEFEB, 0x753A, 0xEFEC, 0x775B, 0xEFED, 0x7887, 0xEFEE, 0x798E,	0xEFEF, 0x7A0B, 0xEFF0, 0x7A7D, 0xEFF1, 0x7CBE, 0xEFF2, 0x7D8E,
+	0xEFF3, 0x8247, 0xEFF4, 0x8A02, 0xEFF5, 0x8AEA, 0xEFF6, 0x8C9E,	0xEFF7, 0x912D, 0xEFF8, 0x914A, 0xEFF9, 0x91D8, 0xEFFA, 0x9266,
+	0xEFFB, 0x92CC, 0xEFFC, 0x9320, 0xEFFD, 0x9706, 0xEFFE, 0x9756,	0xF0A1, 0x975C, 0xF0A2, 0x9802, 0xF0A3, 0x9F0E, 0xF0A4, 0x5236,
+	0xF0A5, 0x5291, 0xF0A6, 0x557C, 0xF0A7, 0x5824, 0xF0A8, 0x5E1D,	0xF0A9, 0x5F1F, 0xF0AA, 0x608C, 0xF0AB, 0x63D0, 0xF0AC, 0x68AF,
+	0xF0AD, 0x6FDF, 0xF0AE, 0x796D, 0xF0AF, 0x7B2C, 0xF0B0, 0x81CD,	0xF0B1, 0x85BA, 0xF0B2, 0x88FD, 0xF0B3, 0x8AF8, 0xF0B4, 0x8E44,
+	0xF0B5, 0x918D, 0xF0B6, 0x9664, 0xF0B7, 0x969B, 0xF0B8, 0x973D,	0xF0B9, 0x984C, 0xF0BA, 0x9F4A, 0xF0BB, 0x4FCE, 0xF0BC, 0x5146,
+	0xF0BD, 0x51CB, 0xF0BE, 0x52A9, 0xF0BF, 0x5632, 0xF0C0, 0x5F14,	0xF0C1, 0x5F6B, 0xF0C2, 0x63AA, 0xF0C3, 0x64CD, 0xF0C4, 0x65E9,
+	0xF0C5, 0x6641, 0xF0C6, 0x66FA, 0xF0C7, 0x66F9, 0xF0C8, 0x671D,	0xF0C9, 0x689D, 0xF0CA, 0x68D7, 0xF0CB, 0x69FD, 0xF0CC, 0x6F15,
+	0xF0CD, 0x6F6E, 0xF0CE, 0x7167, 0xF0CF, 0x71E5, 0xF0D0, 0x722A,	0xF0D1, 0x74AA, 0xF0D2, 0x773A, 0xF0D3, 0x7956, 0xF0D4, 0x795A,
+	0xF0D5, 0x79DF, 0xF0D6, 0x7A20, 0xF0D7, 0x7A95, 0xF0D8, 0x7C97,	0xF0D9, 0x7CDF, 0xF0DA, 0x7D44, 0xF0DB, 0x7E70, 0xF0DC, 0x8087,
+	0xF0DD, 0x85FB, 0xF0DE, 0x86A4, 0xF0DF, 0x8A54, 0xF0E0, 0x8ABF,	0xF0E1, 0x8D99, 0xF0E2, 0x8E81, 0xF0E3, 0x9020, 0xF0E4, 0x906D,
+	0xF0E5, 0x91E3, 0xF0E6, 0x963B, 0xF0E7, 0x96D5, 0xF0E8, 0x9CE5,	0xF0E9, 0x65CF, 0xF0EA, 0x7C07, 0xF0EB, 0x8DB3, 0xF0EC, 0x93C3,
+	0xF0ED, 0x5B58, 0xF0EE, 0x5C0A, 0xF0EF, 0x5352, 0xF0F0, 0x62D9,	0xF0F1, 0x731D, 0xF0F2, 0x5027, 0xF0F3, 0x5B97, 0xF0F4, 0x5F9E,
+	0xF0F5, 0x60B0, 0xF0F6, 0x616B, 0xF0F7, 0x68D5, 0xF0F8, 0x6DD9,	0xF0F9, 0x742E, 0xF0FA, 0x7A2E, 0xF0FB, 0x7D42, 0xF0FC, 0x7D9C,
+	0xF0FD, 0x7E31, 0xF0FE, 0x816B, 0xF1A1, 0x8E2A, 0xF1A2, 0x8E35,	0xF1A3, 0x937E, 0xF1A4, 0x9418, 0xF1A5, 0x4F50, 0xF1A6, 0x5750,
+	0xF1A7, 0x5DE6, 0xF1A8, 0x5EA7, 0xF1A9, 0x632B, 0xF1AA, 0x7F6A,	0xF1AB, 0x4E3B, 0xF1AC, 0x4F4F, 0xF1AD, 0x4F8F, 0xF1AE, 0x505A,
+	0xF1AF, 0x59DD, 0xF1B0, 0x80C4, 0xF1B1, 0x546A, 0xF1B2, 0x5468,	0xF1B3, 0x55FE, 0xF1B4, 0x594F, 0xF1B5, 0x5B99, 0xF1B6, 0x5DDE,
+	0xF1B7, 0x5EDA, 0xF1B8, 0x665D, 0xF1B9, 0x6731, 0xF1BA, 0x67F1,	0xF1BB, 0x682A, 0xF1BC, 0x6CE8, 0xF1BD, 0x6D32, 0xF1BE, 0x6E4A,
+	0xF1BF, 0x6F8D, 0xF1C0, 0x70B7, 0xF1C1, 0x73E0, 0xF1C2, 0x7587,	0xF1C3, 0x7C4C, 0xF1C4, 0x7D02, 0xF1C5, 0x7D2C, 0xF1C6, 0x7DA2,
+	0xF1C7, 0x821F, 0xF1C8, 0x86DB, 0xF1C9, 0x8A3B, 0xF1CA, 0x8A85,	0xF1CB, 0x8D70, 0xF1CC, 0x8E8A, 0xF1CD, 0x8F33, 0xF1CE, 0x9031,
+	0xF1CF, 0x914E, 0xF1D0, 0x9152, 0xF1D1, 0x9444, 0xF1D2, 0x99D0,	0xF1D3, 0x7AF9, 0xF1D4, 0x7CA5, 0xF1D5, 0x4FCA, 0xF1D6, 0x5101,
+	0xF1D7, 0x51C6, 0xF1D8, 0x57C8, 0xF1D9, 0x5BEF, 0xF1DA, 0x5CFB,	0xF1DB, 0x6659, 0xF1DC, 0x6A3D, 0xF1DD, 0x6D5A, 0xF1DE, 0x6E96,
+	0xF1DF, 0x6FEC, 0xF1E0, 0x710C, 0xF1E1, 0x756F, 0xF1E2, 0x7AE3,	0xF1E3, 0x8822, 0xF1E4, 0x9021, 0xF1E5, 0x9075, 0xF1E6, 0x96CB,
+	0xF1E7, 0x99FF, 0xF1E8, 0x8301, 0xF1E9, 0x4E2D, 0xF1EA, 0x4EF2,	0xF1EB, 0x8846, 0xF1EC, 0x91CD, 0xF1ED, 0x537D, 0xF1EE, 0x6ADB,
+	0xF1EF, 0x696B, 0xF1F0, 0x6C41, 0xF1F1, 0x847A, 0xF1F2, 0x589E,	0xF1F3, 0x618E, 0xF1F4, 0x66FE, 0xF1F5, 0x62EF, 0xF1F6, 0x70DD,
+	0xF1F7, 0x7511, 0xF1F8, 0x75C7, 0xF1F9, 0x7E52, 0xF1FA, 0x84B8,	0xF1FB, 0x8B49, 0xF1FC, 0x8D08, 0xF1FD, 0x4E4B, 0xF1FE, 0x53EA,
+	0xF2A1, 0x54AB, 0xF2A2, 0x5730, 0xF2A3, 0x5740, 0xF2A4, 0x5FD7,	0xF2A5, 0x6301, 0xF2A6, 0x6307, 0xF2A7, 0x646F, 0xF2A8, 0x652F,
+	0xF2A9, 0x65E8, 0xF2AA, 0x667A, 0xF2AB, 0x679D, 0xF2AC, 0x67B3,	0xF2AD, 0x6B62, 0xF2AE, 0x6C60, 0xF2AF, 0x6C9A, 0xF2B0, 0x6F2C,
+	0xF2B1, 0x77E5, 0xF2B2, 0x7825, 0xF2B3, 0x7949, 0xF2B4, 0x7957,	0xF2B5, 0x7D19, 0xF2B6, 0x80A2, 0xF2B7, 0x8102, 0xF2B8, 0x81F3,
+	0xF2B9, 0x829D, 0xF2BA, 0x82B7, 0xF2BB, 0x8718, 0xF2BC, 0x8A8C,	0xF2BD, 0xF9FC, 0xF2BE, 0x8D04, 0xF2BF, 0x8DBE, 0xF2C0, 0x9072,
+	0xF2C1, 0x76F4, 0xF2C2, 0x7A19, 0xF2C3, 0x7A37, 0xF2C4, 0x7E54,	0xF2C5, 0x8077, 0xF2C6, 0x5507, 0xF2C7, 0x55D4, 0xF2C8, 0x5875,
+	0xF2C9, 0x632F, 0xF2CA, 0x6422, 0xF2CB, 0x6649, 0xF2CC, 0x664B,	0xF2CD, 0x686D, 0xF2CE, 0x699B, 0xF2CF, 0x6B84, 0xF2D0, 0x6D25,
+	0xF2D1, 0x6EB1, 0xF2D2, 0x73CD, 0xF2D3, 0x7468, 0xF2D4, 0x74A1,	0xF2D5, 0x755B, 0xF2D6, 0x75B9, 0xF2D7, 0x76E1, 0xF2D8, 0x771E,
+	0xF2D9, 0x778B, 0xF2DA, 0x79E6, 0xF2DB, 0x7E09, 0xF2DC, 0x7E1D,	0xF2DD, 0x81FB, 0xF2DE, 0x852F, 0xF2DF, 0x8897, 0xF2E0, 0x8A3A,
+	0xF2E1, 0x8CD1, 0xF2E2, 0x8EEB, 0xF2E3, 0x8FB0, 0xF2E4, 0x9032,	0xF2E5, 0x93AD, 0xF2E6, 0x9663, 0xF2E7, 0x9673, 0xF2E8, 0x9707,
+	0xF2E9, 0x4F84, 0xF2EA, 0x53F1, 0xF2EB, 0x59EA, 0xF2EC, 0x5AC9,	0xF2ED, 0x5E19, 0xF2EE, 0x684E, 0xF2EF, 0x74C6, 0xF2F0, 0x75BE,
+	0xF2F1, 0x79E9, 0xF2F2, 0x7A92, 0xF2F3, 0x81A3, 0xF2F4, 0x86ED,	0xF2F5, 0x8CEA, 0xF2F6, 0x8DCC, 0xF2F7, 0x8FED, 0xF2F8, 0x659F,
+	0xF2F9, 0x6715, 0xF2FA, 0xF9FD, 0xF2FB, 0x57F7, 0xF2FC, 0x6F57,	0xF2FD, 0x7DDD, 0xF2FE, 0x8F2F, 0xF3A1, 0x93F6, 0xF3A2, 0x96C6,
+	0xF3A3, 0x5FB5, 0xF3A4, 0x61F2, 0xF3A5, 0x6F84, 0xF3A6, 0x4E14,	0xF3A7, 0x4F98, 0xF3A8, 0x501F, 0xF3A9, 0x53C9, 0xF3AA, 0x55DF,
+	0xF3AB, 0x5D6F, 0xF3AC, 0x5DEE, 0xF3AD, 0x6B21, 0xF3AE, 0x6B64,	0xF3AF, 0x78CB, 0xF3B0, 0x7B9A, 0xF3B1, 0xF9FE, 0xF3B2, 0x8E49,
+	0xF3B3, 0x8ECA, 0xF3B4, 0x906E, 0xF3B5, 0x6349, 0xF3B6, 0x643E,	0xF3B7, 0x7740, 0xF3B8, 0x7A84, 0xF3B9, 0x932F, 0xF3BA, 0x947F,
+	0xF3BB, 0x9F6A, 0xF3BC, 0x64B0, 0xF3BD, 0x6FAF, 0xF3BE, 0x71E6,	0xF3BF, 0x74A8, 0xF3C0, 0x74DA, 0xF3C1, 0x7AC4, 0xF3C2, 0x7C12,
+	0xF3C3, 0x7E82, 0xF3C4, 0x7CB2, 0xF3C5, 0x7E98, 0xF3C6, 0x8B9A,	0xF3C7, 0x8D0A, 0xF3C8, 0x947D, 0xF3C9, 0x9910, 0xF3CA, 0x994C,
+	0xF3CB, 0x5239, 0xF3CC, 0x5BDF, 0xF3CD, 0x64E6, 0xF3CE, 0x672D,	0xF3CF, 0x7D2E, 0xF3D0, 0x50ED, 0xF3D1, 0x53C3, 0xF3D2, 0x5879,
+	0xF3D3, 0x6158, 0xF3D4, 0x6159, 0xF3D5, 0x61FA, 0xF3D6, 0x65AC,	0xF3D7, 0x7AD9, 0xF3D8, 0x8B92, 0xF3D9, 0x8B96, 0xF3DA, 0x5009,
+	0xF3DB, 0x5021, 0xF3DC, 0x5275, 0xF3DD, 0x5531, 0xF3DE, 0x5A3C,	0xF3DF, 0x5EE0, 0xF3E0, 0x5F70, 0xF3E1, 0x6134, 0xF3E2, 0x655E,
+	0xF3E3, 0x660C, 0xF3E4, 0x6636, 0xF3E5, 0x66A2, 0xF3E6, 0x69CD,	0xF3E7, 0x6EC4, 0xF3E8, 0x6F32, 0xF3E9, 0x7316, 0xF3EA, 0x7621,
+	0xF3EB, 0x7A93, 0xF3EC, 0x8139, 0xF3ED, 0x8259, 0xF3EE, 0x83D6,	0xF3EF, 0x84BC, 0xF3F0, 0x50B5, 0xF3F1, 0x57F0, 0xF3F2, 0x5BC0,
+	0xF3F3, 0x5BE8, 0xF3F4, 0x5F69, 0xF3F5, 0x63A1, 0xF3F6, 0x7826,	0xF3F7, 0x7DB5, 0xF3F8, 0x83DC, 0xF3F9, 0x8521, 0xF3FA, 0x91C7,
+	0xF3FB, 0x91F5, 0xF3FC, 0x518A, 0xF3FD, 0x67F5, 0xF3FE, 0x7B56,	0xF4A1, 0x8CAC, 0xF4A2, 0x51C4, 0xF4A3, 0x59BB, 0xF4A4, 0x60BD,
+	0xF4A5, 0x8655, 0xF4A6, 0x501C, 0xF4A7, 0xF9FF, 0xF4A8, 0x5254,	0xF4A9, 0x5C3A, 0xF4AA, 0x617D, 0xF4AB, 0x621A, 0xF4AC, 0x62D3,
+	0xF4AD, 0x64F2, 0xF4AE, 0x65A5, 0xF4AF, 0x6ECC, 0xF4B0, 0x7620,	0xF4B1, 0x810A, 0xF4B2, 0x8E60, 0xF4B3, 0x965F, 0xF4B4, 0x96BB,
+	0xF4B5, 0x4EDF, 0xF4B6, 0x5343, 0xF4B7, 0x5598, 0xF4B8, 0x5929,	0xF4B9, 0x5DDD, 0xF4BA, 0x64C5, 0xF4BB, 0x6CC9, 0xF4BC, 0x6DFA,
+	0xF4BD, 0x7394, 0xF4BE, 0x7A7F, 0xF4BF, 0x821B, 0xF4C0, 0x85A6,	0xF4C1, 0x8CE4, 0xF4C2, 0x8E10, 0xF4C3, 0x9077, 0xF4C4, 0x91E7,
+	0xF4C5, 0x95E1, 0xF4C6, 0x9621, 0xF4C7, 0x97C6, 0xF4C8, 0x51F8,	0xF4C9, 0x54F2, 0xF4CA, 0x5586, 0xF4CB, 0x5FB9, 0xF4CC, 0x64A4,
+	0xF4CD, 0x6F88, 0xF4CE, 0x7DB4, 0xF4CF, 0x8F1F, 0xF4D0, 0x8F4D,	0xF4D1, 0x9435, 0xF4D2, 0x50C9, 0xF4D3, 0x5C16, 0xF4D4, 0x6CBE,
+	0xF4D5, 0x6DFB, 0xF4D6, 0x751B, 0xF4D7, 0x77BB, 0xF4D8, 0x7C3D,	0xF4D9, 0x7C64, 0xF4DA, 0x8A79, 0xF4DB, 0x8AC2, 0xF4DC, 0x581E,
+	0xF4DD, 0x59BE, 0xF4DE, 0x5E16, 0xF4DF, 0x6377, 0xF4E0, 0x7252,	0xF4E1, 0x758A, 0xF4E2, 0x776B, 0xF4E3, 0x8ADC, 0xF4E4, 0x8CBC,
+	0xF4E5, 0x8F12, 0xF4E6, 0x5EF3, 0xF4E7, 0x6674, 0xF4E8, 0x6DF8,	0xF4E9, 0x807D, 0xF4EA, 0x83C1, 0xF4EB, 0x8ACB, 0xF4EC, 0x9751,
+	0xF4ED, 0x9BD6, 0xF4EE, 0xFA00, 0xF4EF, 0x5243, 0xF4F0, 0x66FF,	0xF4F1, 0x6D95, 0xF4F2, 0x6EEF, 0xF4F3, 0x7DE0, 0xF4F4, 0x8AE6,
+	0xF4F5, 0x902E, 0xF4F6, 0x905E, 0xF4F7, 0x9AD4, 0xF4F8, 0x521D,	0xF4F9, 0x527F, 0xF4FA, 0x54E8, 0xF4FB, 0x6194, 0xF4FC, 0x6284,
+	0xF4FD, 0x62DB, 0xF4FE, 0x68A2, 0xF5A1, 0x6912, 0xF5A2, 0x695A,	0xF5A3, 0x6A35, 0xF5A4, 0x7092, 0xF5A5, 0x7126, 0xF5A6, 0x785D,
+	0xF5A7, 0x7901, 0xF5A8, 0x790E, 0xF5A9, 0x79D2, 0xF5AA, 0x7A0D,	0xF5AB, 0x8096, 0xF5AC, 0x8278, 0xF5AD, 0x82D5, 0xF5AE, 0x8349,
+	0xF5AF, 0x8549, 0xF5B0, 0x8C82, 0xF5B1, 0x8D85, 0xF5B2, 0x9162,	0xF5B3, 0x918B, 0xF5B4, 0x91AE, 0xF5B5, 0x4FC3, 0xF5B6, 0x56D1,
+	0xF5B7, 0x71ED, 0xF5B8, 0x77D7, 0xF5B9, 0x8700, 0xF5BA, 0x89F8,	0xF5BB, 0x5BF8, 0xF5BC, 0x5FD6, 0xF5BD, 0x6751, 0xF5BE, 0x90A8,
+	0xF5BF, 0x53E2, 0xF5C0, 0x585A, 0xF5C1, 0x5BF5, 0xF5C2, 0x60A4,	0xF5C3, 0x6181, 0xF5C4, 0x6460, 0xF5C5, 0x7E3D, 0xF5C6, 0x8070,
+	0xF5C7, 0x8525, 0xF5C8, 0x9283, 0xF5C9, 0x64AE, 0xF5CA, 0x50AC,	0xF5CB, 0x5D14, 0xF5CC, 0x6700, 0xF5CD, 0x589C, 0xF5CE, 0x62BD,
+	0xF5CF, 0x63A8, 0xF5D0, 0x690E, 0xF5D1, 0x6978, 0xF5D2, 0x6A1E,	0xF5D3, 0x6E6B, 0xF5D4, 0x76BA, 0xF5D5, 0x79CB, 0xF5D6, 0x82BB,
+	0xF5D7, 0x8429, 0xF5D8, 0x8ACF, 0xF5D9, 0x8DA8, 0xF5DA, 0x8FFD,	0xF5DB, 0x9112, 0xF5DC, 0x914B, 0xF5DD, 0x919C, 0xF5DE, 0x9310,
+	0xF5DF, 0x9318, 0xF5E0, 0x939A, 0xF5E1, 0x96DB, 0xF5E2, 0x9A36,	0xF5E3, 0x9C0D, 0xF5E4, 0x4E11, 0xF5E5, 0x755C, 0xF5E6, 0x795D,
+	0xF5E7, 0x7AFA, 0xF5E8, 0x7B51, 0xF5E9, 0x7BC9, 0xF5EA, 0x7E2E,	0xF5EB, 0x84C4, 0xF5EC, 0x8E59, 0xF5ED, 0x8E74, 0xF5EE, 0x8EF8,
+	0xF5EF, 0x9010, 0xF5F0, 0x6625, 0xF5F1, 0x693F, 0xF5F2, 0x7443,	0xF5F3, 0x51FA, 0xF5F4, 0x672E, 0xF5F5, 0x9EDC, 0xF5F6, 0x5145,
+	0xF5F7, 0x5FE0, 0xF5F8, 0x6C96, 0xF5F9, 0x87F2, 0xF5FA, 0x885D,	0xF5FB, 0x8877, 0xF5FC, 0x60B4, 0xF5FD, 0x81B5, 0xF5FE, 0x8403,
+	0xF6A1, 0x8D05, 0xF6A2, 0x53D6, 0xF6A3, 0x5439, 0xF6A4, 0x5634,	0xF6A5, 0x5A36, 0xF6A6, 0x5C31, 0xF6A7, 0x708A, 0xF6A8, 0x7FE0,
+	0xF6A9, 0x805A, 0xF6AA, 0x8106, 0xF6AB, 0x81ED, 0xF6AC, 0x8DA3,	0xF6AD, 0x9189, 0xF6AE, 0x9A5F, 0xF6AF, 0x9DF2, 0xF6B0, 0x5074,
+	0xF6B1, 0x4EC4, 0xF6B2, 0x53A0, 0xF6B3, 0x60FB, 0xF6B4, 0x6E2C,	0xF6B5, 0x5C64, 0xF6B6, 0x4F88, 0xF6B7, 0x5024, 0xF6B8, 0x55E4,
+	0xF6B9, 0x5CD9, 0xF6BA, 0x5E5F, 0xF6BB, 0x6065, 0xF6BC, 0x6894,	0xF6BD, 0x6CBB, 0xF6BE, 0x6DC4, 0xF6BF, 0x71BE, 0xF6C0, 0x75D4,
+	0xF6C1, 0x75F4, 0xF6C2, 0x7661, 0xF6C3, 0x7A1A, 0xF6C4, 0x7A49,	0xF6C5, 0x7DC7, 0xF6C6, 0x7DFB, 0xF6C7, 0x7F6E, 0xF6C8, 0x81F4,
+	0xF6C9, 0x86A9, 0xF6CA, 0x8F1C, 0xF6CB, 0x96C9, 0xF6CC, 0x99B3,	0xF6CD, 0x9F52, 0xF6CE, 0x5247, 0xF6CF, 0x52C5, 0xF6D0, 0x98ED,
+	0xF6D1, 0x89AA, 0xF6D2, 0x4E03, 0xF6D3, 0x67D2, 0xF6D4, 0x6F06,	0xF6D5, 0x4FB5, 0xF6D6, 0x5BE2, 0xF6D7, 0x6795, 0xF6D8, 0x6C88,
+	0xF6D9, 0x6D78, 0xF6DA, 0x741B, 0xF6DB, 0x7827, 0xF6DC, 0x91DD,	0xF6DD, 0x937C, 0xF6DE, 0x87C4, 0xF6DF, 0x79E4, 0xF6E0, 0x7A31,
+	0xF6E1, 0x5FEB, 0xF6E2, 0x4ED6, 0xF6E3, 0x54A4, 0xF6E4, 0x553E,	0xF6E5, 0x58AE, 0xF6E6, 0x59A5, 0xF6E7, 0x60F0, 0xF6E8, 0x6253,
+	0xF6E9, 0x62D6, 0xF6EA, 0x6736, 0xF6EB, 0x6955, 0xF6EC, 0x8235,	0xF6ED, 0x9640, 0xF6EE, 0x99B1, 0xF6EF, 0x99DD, 0xF6F0, 0x502C,
+	0xF6F1, 0x5353, 0xF6F2, 0x5544, 0xF6F3, 0x577C, 0xF6F4, 0xFA01,	0xF6F5, 0x6258, 0xF6F6, 0xFA02, 0xF6F7, 0x64E2, 0xF6F8, 0x666B,
+	0xF6F9, 0x67DD, 0xF6FA, 0x6FC1, 0xF6FB, 0x6FEF, 0xF6FC, 0x7422,	0xF6FD, 0x7438, 0xF6FE, 0x8A17, 0xF7A1, 0x9438, 0xF7A2, 0x5451,
+	0xF7A3, 0x5606, 0xF7A4, 0x5766, 0xF7A5, 0x5F48, 0xF7A6, 0x619A,	0xF7A7, 0x6B4E, 0xF7A8, 0x7058, 0xF7A9, 0x70AD, 0xF7AA, 0x7DBB,
+	0xF7AB, 0x8A95, 0xF7AC, 0x596A, 0xF7AD, 0x812B, 0xF7AE, 0x63A2,	0xF7AF, 0x7708, 0xF7B0, 0x803D, 0xF7B1, 0x8CAA, 0xF7B2, 0x5854,
+	0xF7B3, 0x642D, 0xF7B4, 0x69BB, 0xF7B5, 0x5B95, 0xF7B6, 0x5E11,	0xF7B7, 0x6E6F, 0xF7B8, 0xFA03, 0xF7B9, 0x8569, 0xF7BA, 0x514C,
+	0xF7BB, 0x53F0, 0xF7BC, 0x592A, 0xF7BD, 0x6020, 0xF7BE, 0x614B,	0xF7BF, 0x6B86, 0xF7C0, 0x6C70, 0xF7C1, 0x6CF0, 0xF7C2, 0x7B1E,
+	0xF7C3, 0x80CE, 0xF7C4, 0x82D4, 0xF7C5, 0x8DC6, 0xF7C6, 0x90B0,	0xF7C7, 0x98B1, 0xF7C8, 0xFA04, 0xF7C9, 0x64C7, 0xF7CA, 0x6FA4,
+	0xF7CB, 0x6491, 0xF7CC, 0x6504, 0xF7CD, 0x514E, 0xF7CE, 0x5410,	0xF7CF, 0x571F, 0xF7D0, 0x8A0E, 0xF7D1, 0x615F, 0xF7D2, 0x6876,
+	0xF7D3, 0xFA05, 0xF7D4, 0x75DB, 0xF7D5, 0x7B52, 0xF7D6, 0x7D71,	0xF7D7, 0x901A, 0xF7D8, 0x5806, 0xF7D9, 0x69CC, 0xF7DA, 0x817F,
+	0xF7DB, 0x892A, 0xF7DC, 0x9000, 0xF7DD, 0x9839, 0xF7DE, 0x5078,	0xF7DF, 0x5957, 0xF7E0, 0x59AC, 0xF7E1, 0x6295, 0xF7E2, 0x900F,
+	0xF7E3, 0x9B2A, 0xF7E4, 0x615D, 0xF7E5, 0x7279, 0xF7E6, 0x95D6,	0xF7E7, 0x5761, 0xF7E8, 0x5A46, 0xF7E9, 0x5DF4, 0xF7EA, 0x628A,
+	0xF7EB, 0x64AD, 0xF7EC, 0x64FA, 0xF7ED, 0x6777, 0xF7EE, 0x6CE2,	0xF7EF, 0x6D3E, 0xF7F0, 0x722C, 0xF7F1, 0x7436, 0xF7F2, 0x7834,
+	0xF7F3, 0x7F77, 0xF7F4, 0x82AD, 0xF7F5, 0x8DDB, 0xF7F6, 0x9817,	0xF7F7, 0x5224, 0xF7F8, 0x5742, 0xF7F9, 0x677F, 0xF7FA, 0x7248,
+	0xF7FB, 0x74E3, 0xF7FC, 0x8CA9, 0xF7FD, 0x8FA6, 0xF7FE, 0x9211,	0xF8A1, 0x962A, 0xF8A2, 0x516B, 0xF8A3, 0x53ED, 0xF8A4, 0x634C,
+	0xF8A5, 0x4F69, 0xF8A6, 0x5504, 0xF8A7, 0x6096, 0xF8A8, 0x6557,	0xF8A9, 0x6C9B, 0xF8AA, 0x6D7F, 0xF8AB, 0x724C, 0xF8AC, 0x72FD,
+	0xF8AD, 0x7A17, 0xF8AE, 0x8987, 0xF8AF, 0x8C9D, 0xF8B0, 0x5F6D,	0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E,
+	0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247,	0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D,
+	0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A,	0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55,
+	0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2,	0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D,
+	0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305,	0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA,
+	0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B,	0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1,
+	0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE,	0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2,
+	0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA,	0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4,
+	0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07,	0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153,
+	0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2,	0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7,
+	0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F,	0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8,
+	0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2,	0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642,
+	0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC,	0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46,
+	0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C,	0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F,
+	0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455,	0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050,
+	0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78,	0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2,
+	0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57,	0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55,
+	0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650,	0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD,
+	0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A,	0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266,
+	0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408,	0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4,
+	0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09,	0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052,
+	0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86,	0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A,
+	0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5,	0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A,
+	0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977,	0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3,
+	0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED,	0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016,
+	0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C,	0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6,
+	0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957,	0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B,
+	0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B,	0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57,
+	0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769,	0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8,
+	0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384,	0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D,
+	0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237,	0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249,
+	0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840,	0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354,
+	0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79,	0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2,
+	0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144,	0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2,
+	0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF,	0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A,
+	0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2,	0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57,
+	0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559,	0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E,
+	0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA,	0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236,
+	0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB,	0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8,
+	0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D,	0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0,
+	0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E,	0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF,
+	0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77,	0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865,
+	0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A,	0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F,
+	0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F,	0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3,
+	0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679,	0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C,
+	0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575,	0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF,
+	0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774,	0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA,
+	0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A,	0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3,
+	0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853,	0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08,
+	0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B,	0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA,
+	0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D,	0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643,
+	0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F,	0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C,
+	0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352,	0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3,
+	0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A,	0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666,
+	0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE,	0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE,
+	0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4,	0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B,
+	0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D,	0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F,
+	0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4,	0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019,
+	0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589,	0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D,
+	0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB,	0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104,
+	0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13,	0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684,
+	0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599,	0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE,
+	0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D,	0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB,
+	0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E,	0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308,
+	0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615,	0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403,
+	0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20,	0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070,
+	0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6,	0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD,
+	0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199,	0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6,
+	0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7,	0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70,
+	0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0	/* Traditional Chinese */
+static const WCHAR uni2oem950[] = {	/* Unicode --> Big5 pairs */
+	0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3,	0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE,
+	0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5,	0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346,
+	0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A,	0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E,
+	0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352,	0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356,
+	0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A,	0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E,
+	0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362,	0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366,
+	0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A,	0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E,
+	0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372,	0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5,
+	0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C,	0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB,
+	0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1,	0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB,
+	0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF,	0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6,
+	0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8,	0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241,
+	0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7,	0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5,
+	0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE,	0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8,
+	0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6,	0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A,
+	0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275,	0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271,
+	0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6,	0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1,
+	0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3,	0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5,
+	0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7,	0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7,
+	0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6,	0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3,
+	0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1,	0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2,
+	0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE,	0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264,
+	0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268,	0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E,
+	0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A,	0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD,
+	0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF,	0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3,
+	0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9,	0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8,
+	0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142,	0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172,
+	0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176,	0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A,
+	0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9,	0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5,
+	0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9,	0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375,
+	0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379,	0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D,
+	0x310F, 0xA37E, 0x3110, 0xA3A1, 0x3111, 0xA3A2, 0x3112, 0xA3A3,	0x3113, 0xA3A4, 0x3114, 0xA3A5, 0x3115, 0xA3A6, 0x3116, 0xA3A7,
+	0x3117, 0xA3A8, 0x3118, 0xA3A9, 0x3119, 0xA3AA, 0x311A, 0xA3AB,	0x311B, 0xA3AC, 0x311C, 0xA3AD, 0x311D, 0xA3AE, 0x311E, 0xA3AF,
+	0x311F, 0xA3B0, 0x3120, 0xA3B1, 0x3121, 0xA3B2, 0x3122, 0xA3B3,	0x3123, 0xA3B4, 0x3124, 0xA3B5, 0x3125, 0xA3B6, 0x3126, 0xA3B7,
+	0x3127, 0xA3B8, 0x3128, 0xA3B9, 0x3129, 0xA3BA, 0x32A3, 0xA1C0,	0x338E, 0xA255, 0x338F, 0xA256, 0x339C, 0xA250, 0x339D, 0xA251,
+	0x339E, 0xA252, 0x33A1, 0xA254, 0x33C4, 0xA257, 0x33CE, 0xA253,	0x33D1, 0xA1EB, 0x33D2, 0xA1EA, 0x33D5, 0xA24F, 0x4E00, 0xA440,
+	0x4E01, 0xA442, 0x4E03, 0xA443, 0x4E07, 0xC945, 0x4E08, 0xA456,	0x4E09, 0xA454, 0x4E0A, 0xA457, 0x4E0B, 0xA455, 0x4E0C, 0xC946,
+	0x4E0D, 0xA4A3, 0x4E0E, 0xC94F, 0x4E0F, 0xC94D, 0x4E10, 0xA4A2,	0x4E11, 0xA4A1, 0x4E14, 0xA542, 0x4E15, 0xA541, 0x4E16, 0xA540,
+	0x4E18, 0xA543, 0x4E19, 0xA4FE, 0x4E1E, 0xA5E0, 0x4E1F, 0xA5E1,	0x4E26, 0xA8C3, 0x4E2B, 0xA458, 0x4E2D, 0xA4A4, 0x4E2E, 0xC950,
+	0x4E30, 0xA4A5, 0x4E31, 0xC963, 0x4E32, 0xA6EA, 0x4E33, 0xCBB1,	0x4E38, 0xA459, 0x4E39, 0xA4A6, 0x4E3B, 0xA544, 0x4E3C, 0xC964,
+	0x4E42, 0xC940, 0x4E43, 0xA444, 0x4E45, 0xA45B, 0x4E47, 0xC947,	0x4E48, 0xA45C, 0x4E4B, 0xA4A7, 0x4E4D, 0xA545, 0x4E4E, 0xA547,
+	0x4E4F, 0xA546, 0x4E52, 0xA5E2, 0x4E53, 0xA5E3, 0x4E56, 0xA8C4,	0x4E58, 0xADBC, 0x4E59, 0xA441, 0x4E5C, 0xC941, 0x4E5D, 0xA445,
+	0x4E5E, 0xA45E, 0x4E5F, 0xA45D, 0x4E69, 0xA5E4, 0x4E73, 0xA8C5,	0x4E7E, 0xB0AE, 0x4E7F, 0xD44B, 0x4E82, 0xB6C3, 0x4E83, 0xDCB1,
+	0x4E84, 0xDCB2, 0x4E86, 0xA446, 0x4E88, 0xA4A9, 0x4E8B, 0xA8C6,	0x4E8C, 0xA447, 0x4E8D, 0xC948, 0x4E8E, 0xA45F, 0x4E91, 0xA4AA,
+	0x4E92, 0xA4AC, 0x4E93, 0xC951, 0x4E94, 0xA4AD, 0x4E95, 0xA4AB,	0x4E99, 0xA5E5, 0x4E9B, 0xA8C7, 0x4E9E, 0xA8C8, 0x4E9F, 0xAB45,
+	0x4EA1, 0xA460, 0x4EA2, 0xA4AE, 0x4EA4, 0xA5E6, 0x4EA5, 0xA5E8,	0x4EA6, 0xA5E7, 0x4EA8, 0xA6EB, 0x4EAB, 0xA8C9, 0x4EAC, 0xA8CA,
+	0x4EAD, 0xAB46, 0x4EAE, 0xAB47, 0x4EB3, 0xADBD, 0x4EB6, 0xDCB3,	0x4EB9, 0xF6D6, 0x4EBA, 0xA448, 0x4EC0, 0xA4B0, 0x4EC1, 0xA4AF,
+	0x4EC2, 0xC952, 0x4EC3, 0xA4B1, 0x4EC4, 0xA4B7, 0x4EC6, 0xA4B2,	0x4EC7, 0xA4B3, 0x4EC8, 0xC954, 0x4EC9, 0xC953, 0x4ECA, 0xA4B5,
+	0x4ECB, 0xA4B6, 0x4ECD, 0xA4B4, 0x4ED4, 0xA54A, 0x4ED5, 0xA54B,	0x4ED6, 0xA54C, 0x4ED7, 0xA54D, 0x4ED8, 0xA549, 0x4ED9, 0xA550,
+	0x4EDA, 0xC96A, 0x4EDC, 0xC966, 0x4EDD, 0xC969, 0x4EDE, 0xA551,	0x4EDF, 0xA561, 0x4EE1, 0xC968, 0x4EE3, 0xA54E, 0x4EE4, 0xA54F,
+	0x4EE5, 0xA548, 0x4EE8, 0xC965, 0x4EE9, 0xC967, 0x4EF0, 0xA5F5,	0x4EF1, 0xC9B0, 0x4EF2, 0xA5F2, 0x4EF3, 0xA5F6, 0x4EF4, 0xC9BA,
+	0x4EF5, 0xC9AE, 0x4EF6, 0xA5F3, 0x4EF7, 0xC9B2, 0x4EFB, 0xA5F4,	0x4EFD, 0xA5F7, 0x4EFF, 0xA5E9, 0x4F00, 0xC9B1, 0x4F01, 0xA5F8,
+	0x4F02, 0xC9B5, 0x4F04, 0xC9B9, 0x4F05, 0xC9B6, 0x4F08, 0xC9B3,	0x4F09, 0xA5EA, 0x4F0A, 0xA5EC, 0x4F0B, 0xA5F9, 0x4F0D, 0xA5EE,
+	0x4F0E, 0xC9AB, 0x4F0F, 0xA5F1, 0x4F10, 0xA5EF, 0x4F11, 0xA5F0,	0x4F12, 0xC9BB, 0x4F13, 0xC9B8, 0x4F14, 0xC9AF, 0x4F15, 0xA5ED,
+	0x4F18, 0xC9AC, 0x4F19, 0xA5EB, 0x4F1D, 0xC9B4, 0x4F22, 0xC9B7,	0x4F2C, 0xC9AD, 0x4F2D, 0xCA66, 0x4F2F, 0xA742, 0x4F30, 0xA6F4,
+	0x4F33, 0xCA67, 0x4F34, 0xA6F1, 0x4F36, 0xA744, 0x4F38, 0xA6F9,	0x4F3A, 0xA6F8, 0x4F3B, 0xCA5B, 0x4F3C, 0xA6FC, 0x4F3D, 0xA6F7,
+	0x4F3E, 0xCA60, 0x4F3F, 0xCA68, 0x4F41, 0xCA64, 0x4F43, 0xA6FA,	0x4F46, 0xA6FD, 0x4F47, 0xA6EE, 0x4F48, 0xA747, 0x4F49, 0xCA5D,
+	0x4F4C, 0xCBBD, 0x4F4D, 0xA6EC, 0x4F4E, 0xA743, 0x4F4F, 0xA6ED,	0x4F50, 0xA6F5, 0x4F51, 0xA6F6, 0x4F52, 0xCA62, 0x4F53, 0xCA5E,
+	0x4F54, 0xA6FB, 0x4F55, 0xA6F3, 0x4F56, 0xCA5A, 0x4F57, 0xA6EF,	0x4F58, 0xCA65, 0x4F59, 0xA745, 0x4F5A, 0xA748, 0x4F5B, 0xA6F2,
+	0x4F5C, 0xA740, 0x4F5D, 0xA746, 0x4F5E, 0xA6F0, 0x4F5F, 0xCA63,	0x4F60, 0xA741, 0x4F61, 0xCA69, 0x4F62, 0xCA5C, 0x4F63, 0xA6FE,
+	0x4F64, 0xCA5F, 0x4F67, 0xCA61, 0x4F69, 0xA8D8, 0x4F6A, 0xCBBF,	0x4F6B, 0xCBCB, 0x4F6C, 0xA8D0, 0x4F6E, 0xCBCC, 0x4F6F, 0xA8CB,
+	0x4F70, 0xA8D5, 0x4F73, 0xA8CE, 0x4F74, 0xCBB9, 0x4F75, 0xA8D6,	0x4F76, 0xCBB8, 0x4F77, 0xCBBC, 0x4F78, 0xCBC3, 0x4F79, 0xCBC1,
+	0x4F7A, 0xA8DE, 0x4F7B, 0xA8D9, 0x4F7C, 0xCBB3, 0x4F7D, 0xCBB5,	0x4F7E, 0xA8DB, 0x4F7F, 0xA8CF, 0x4F80, 0xCBB6, 0x4F81, 0xCBC2,
+	0x4F82, 0xCBC9, 0x4F83, 0xA8D4, 0x4F84, 0xCBBB, 0x4F85, 0xCBB4,	0x4F86, 0xA8D3, 0x4F87, 0xCBB7, 0x4F88, 0xA8D7, 0x4F89, 0xCBBA,
+	0x4F8B, 0xA8D2, 0x4F8D, 0xA8CD, 0x4F8F, 0xA8DC, 0x4F90, 0xCBC4,	0x4F91, 0xA8DD, 0x4F92, 0xCBC8, 0x4F94, 0xCBC6, 0x4F95, 0xCBCA,
+	0x4F96, 0xA8DA, 0x4F97, 0xCBBE, 0x4F98, 0xCBB2, 0x4F9A, 0xCBC0,	0x4F9B, 0xA8D1, 0x4F9C, 0xCBC5, 0x4F9D, 0xA8CC, 0x4F9E, 0xCBC7,
+	0x4FAE, 0xAB56, 0x4FAF, 0xAB4A, 0x4FB2, 0xCDE0, 0x4FB3, 0xCDE8,	0x4FB5, 0xAB49, 0x4FB6, 0xAB51, 0x4FB7, 0xAB5D, 0x4FB9, 0xCDEE,
+	0x4FBA, 0xCDEC, 0x4FBB, 0xCDE7, 0x4FBF, 0xAB4B, 0x4FC0, 0xCDED,	0x4FC1, 0xCDE3, 0x4FC2, 0xAB59, 0x4FC3, 0xAB50, 0x4FC4, 0xAB58,
+	0x4FC5, 0xCDDE, 0x4FC7, 0xCDEA, 0x4FC9, 0xCDE1, 0x4FCA, 0xAB54,	0x4FCB, 0xCDE2, 0x4FCD, 0xCDDD, 0x4FCE, 0xAB5B, 0x4FCF, 0xAB4E,
+	0x4FD0, 0xAB57, 0x4FD1, 0xAB4D, 0x4FD3, 0xCDDF, 0x4FD4, 0xCDE4,	0x4FD6, 0xCDEB, 0x4FD7, 0xAB55, 0x4FD8, 0xAB52, 0x4FD9, 0xCDE6,
+	0x4FDA, 0xAB5A, 0x4FDB, 0xCDE9, 0x4FDC, 0xCDE5, 0x4FDD, 0xAB4F,	0x4FDE, 0xAB5C, 0x4FDF, 0xAB53, 0x4FE0, 0xAB4C, 0x4FE1, 0xAB48,
+	0x4FEC, 0xCDEF, 0x4FEE, 0xADD7, 0x4FEF, 0xADC1, 0x4FF1, 0xADD1,	0x4FF3, 0xADD6, 0x4FF4, 0xD0D0, 0x4FF5, 0xD0CF, 0x4FF6, 0xD0D4,
+	0x4FF7, 0xD0D5, 0x4FF8, 0xADC4, 0x4FFA, 0xADCD, 0x4FFE, 0xADDA,	0x5000, 0xADCE, 0x5005, 0xD0C9, 0x5006, 0xADC7, 0x5007, 0xD0CA,
+	0x5009, 0xADDC, 0x500B, 0xADD3, 0x500C, 0xADBE, 0x500D, 0xADBF,	0x500E, 0xD0DD, 0x500F, 0xB0BF, 0x5011, 0xADCC, 0x5012, 0xADCB,
+	0x5013, 0xD0CB, 0x5014, 0xADCF, 0x5015, 0xD45B, 0x5016, 0xADC6,	0x5017, 0xD0D6, 0x5018, 0xADD5, 0x5019, 0xADD4, 0x501A, 0xADCA,
+	0x501B, 0xD0CE, 0x501C, 0xD0D7, 0x501E, 0xD0C8, 0x501F, 0xADC9,	0x5020, 0xD0D8, 0x5021, 0xADD2, 0x5022, 0xD0CC, 0x5023, 0xADC0,
+	0x5025, 0xADC3, 0x5026, 0xADC2, 0x5027, 0xD0D9, 0x5028, 0xADD0,	0x5029, 0xADC5, 0x502A, 0xADD9, 0x502B, 0xADDB, 0x502C, 0xD0D3,
+	0x502D, 0xADD8, 0x502F, 0xD0DB, 0x5030, 0xD0CD, 0x5031, 0xD0DC,	0x5033, 0xD0D1, 0x5035, 0xD0DA, 0x5037, 0xD0D2, 0x503C, 0xADC8,
+	0x5040, 0xD463, 0x5041, 0xD457, 0x5043, 0xB0B3, 0x5045, 0xD45C,	0x5046, 0xD462, 0x5047, 0xB0B2, 0x5048, 0xD455, 0x5049, 0xB0B6,
+	0x504A, 0xD459, 0x504B, 0xD452, 0x504C, 0xB0B4, 0x504D, 0xD456,	0x504E, 0xB0B9, 0x504F, 0xB0BE, 0x5051, 0xD467, 0x5053, 0xD451,
+	0x5055, 0xB0BA, 0x5057, 0xD466, 0x505A, 0xB0B5, 0x505B, 0xD458,	0x505C, 0xB0B1, 0x505D, 0xD453, 0x505E, 0xD44F, 0x505F, 0xD45D,
+	0x5060, 0xD450, 0x5061, 0xD44E, 0x5062, 0xD45A, 0x5063, 0xD460,	0x5064, 0xD461, 0x5065, 0xB0B7, 0x5068, 0xD85B, 0x5069, 0xD45E,
+	0x506A, 0xD44D, 0x506B, 0xD45F, 0x506D, 0xB0C1, 0x506E, 0xD464,	0x506F, 0xB0C0, 0x5070, 0xD44C, 0x5072, 0xD454, 0x5073, 0xD465,
+	0x5074, 0xB0BC, 0x5075, 0xB0BB, 0x5076, 0xB0B8, 0x5077, 0xB0BD,	0x507A, 0xB0AF, 0x507D, 0xB0B0, 0x5080, 0xB3C8, 0x5082, 0xD85E,
+	0x5083, 0xD857, 0x5085, 0xB3C5, 0x5087, 0xD85F, 0x508B, 0xD855,	0x508C, 0xD858, 0x508D, 0xB3C4, 0x508E, 0xD859, 0x5091, 0xB3C7,
+	0x5092, 0xD85D, 0x5094, 0xD853, 0x5095, 0xD852, 0x5096, 0xB3C9,	0x5098, 0xB3CA, 0x5099, 0xB3C6, 0x509A, 0xB3CB, 0x509B, 0xD851,
+	0x509C, 0xD85C, 0x509D, 0xD85A, 0x509E, 0xD854, 0x50A2, 0xB3C3,	0x50A3, 0xD856, 0x50AC, 0xB6CA, 0x50AD, 0xB6C4, 0x50AE, 0xDCB7,
+	0x50AF, 0xB6CD, 0x50B0, 0xDCBD, 0x50B1, 0xDCC0, 0x50B2, 0xB6C6,	0x50B3, 0xB6C7, 0x50B4, 0xDCBA, 0x50B5, 0xB6C5, 0x50B6, 0xDCC3,
+	0x50B7, 0xB6CB, 0x50B8, 0xDCC4, 0x50BA, 0xDCBF, 0x50BB, 0xB6CC,	0x50BD, 0xDCB4, 0x50BE, 0xB6C9, 0x50BF, 0xDCB5, 0x50C1, 0xDCBE,
+	0x50C2, 0xDCBC, 0x50C4, 0xDCB8, 0x50C5, 0xB6C8, 0x50C6, 0xDCB6,	0x50C7, 0xB6CE, 0x50C8, 0xDCBB, 0x50C9, 0xDCC2, 0x50CA, 0xDCB9,
+	0x50CB, 0xDCC1, 0x50CE, 0xB9B6, 0x50CF, 0xB9B3, 0x50D1, 0xB9B4,	0x50D3, 0xE0F9, 0x50D4, 0xE0F1, 0x50D5, 0xB9B2, 0x50D6, 0xB9AF,
+	0x50D7, 0xE0F2, 0x50DA, 0xB9B1, 0x50DB, 0xE0F5, 0x50DD, 0xE0F7,	0x50E0, 0xE0FE, 0x50E3, 0xE0FD, 0x50E4, 0xE0F8, 0x50E5, 0xB9AE,
+	0x50E6, 0xE0F0, 0x50E7, 0xB9AC, 0x50E8, 0xE0F3, 0x50E9, 0xB9B7,	0x50EA, 0xE0F6, 0x50EC, 0xE0FA, 0x50ED, 0xB9B0, 0x50EE, 0xB9AD,
+	0x50EF, 0xE0FC, 0x50F0, 0xE0FB, 0x50F1, 0xB9B5, 0x50F3, 0xE0F4,	0x50F5, 0xBBF8, 0x50F6, 0xE4EC, 0x50F8, 0xE4E9, 0x50F9, 0xBBF9,
+	0x50FB, 0xBBF7, 0x50FD, 0xE4F0, 0x50FE, 0xE4ED, 0x50FF, 0xE4E6,	0x5100, 0xBBF6, 0x5102, 0xBBFA, 0x5103, 0xE4E7, 0x5104, 0xBBF5,
+	0x5105, 0xBBFD, 0x5106, 0xE4EA, 0x5107, 0xE4EB, 0x5108, 0xBBFB,	0x5109, 0xBBFC, 0x510A, 0xE4F1, 0x510B, 0xE4EE, 0x510C, 0xE4EF,
+	0x5110, 0xBEAA, 0x5111, 0xE8F8, 0x5112, 0xBEA7, 0x5113, 0xE8F5,	0x5114, 0xBEA9, 0x5115, 0xBEAB, 0x5117, 0xE8F6, 0x5118, 0xBEA8,
+	0x511A, 0xE8F7, 0x511C, 0xE8F4, 0x511F, 0xC076, 0x5120, 0xECBD,	0x5121, 0xC077, 0x5122, 0xECBB, 0x5124, 0xECBC, 0x5125, 0xECBA,
+	0x5126, 0xECB9, 0x5129, 0xECBE, 0x512A, 0xC075, 0x512D, 0xEFB8,	0x512E, 0xEFB9, 0x5130, 0xE4E8, 0x5131, 0xEFB7, 0x5132, 0xC078,
+	0x5133, 0xC35F, 0x5134, 0xF1EB, 0x5135, 0xF1EC, 0x5137, 0xC4D7,	0x5138, 0xC4D8, 0x5139, 0xF5C1, 0x513A, 0xF5C0, 0x513B, 0xC56C,
+	0x513C, 0xC56B, 0x513D, 0xF7D0, 0x513F, 0xA449, 0x5140, 0xA461,	0x5141, 0xA4B9, 0x5143, 0xA4B8, 0x5144, 0xA553, 0x5145, 0xA552,
+	0x5146, 0xA5FC, 0x5147, 0xA5FB, 0x5148, 0xA5FD, 0x5149, 0xA5FA,	0x514B, 0xA74A, 0x514C, 0xA749, 0x514D, 0xA74B, 0x5152, 0xA8E0,
+	0x5154, 0xA8DF, 0x5155, 0xA8E1, 0x5157, 0xAB5E, 0x5159, 0xA259,	0x515A, 0xD0DE, 0x515B, 0xA25A, 0x515C, 0xB0C2, 0x515D, 0xA25C,
+	0x515E, 0xA25B, 0x515F, 0xD860, 0x5161, 0xA25D, 0x5162, 0xB9B8,	0x5163, 0xA25E, 0x5165, 0xA44A, 0x5167, 0xA4BA, 0x5168, 0xA5FE,
+	0x5169, 0xA8E2, 0x516B, 0xA44B, 0x516C, 0xA4BD, 0x516D, 0xA4BB,	0x516E, 0xA4BC, 0x5171, 0xA640, 0x5175, 0xA74C, 0x5176, 0xA8E4,
+	0x5177, 0xA8E3, 0x5178, 0xA8E5, 0x517C, 0xADDD, 0x5180, 0xBEAC,	0x5187, 0xC94E, 0x5189, 0xA554, 0x518A, 0xA555, 0x518D, 0xA641,
+	0x518F, 0xCA6A, 0x5191, 0xAB60, 0x5192, 0xAB5F, 0x5193, 0xD0E0,	0x5194, 0xD0DF, 0x5195, 0xB0C3, 0x5197, 0xA4BE, 0x5198, 0xC955,
+	0x519E, 0xCBCD, 0x51A0, 0xAB61, 0x51A2, 0xADE0, 0x51A4, 0xADDE,	0x51A5, 0xADDF, 0x51AA, 0xBEAD, 0x51AC, 0xA556, 0x51B0, 0xA642,
+	0x51B1, 0xC9BC, 0x51B6, 0xA74D, 0x51B7, 0xA74E, 0x51B9, 0xCA6B,	0x51BC, 0xCBCE, 0x51BD, 0xA8E6, 0x51BE, 0xCBCF, 0x51C4, 0xD0E2,
+	0x51C5, 0xD0E3, 0x51C6, 0xADE3, 0x51C8, 0xD0E4, 0x51CA, 0xD0E1,	0x51CB, 0xADE4, 0x51CC, 0xADE2, 0x51CD, 0xADE1, 0x51CE, 0xD0E5,
+	0x51D0, 0xD468, 0x51D4, 0xD861, 0x51D7, 0xDCC5, 0x51D8, 0xE140,	0x51DC, 0xBBFE, 0x51DD, 0xBEAE, 0x51DE, 0xE8F9, 0x51E0, 0xA44C,
+	0x51E1, 0xA45A, 0x51F0, 0xB0C4, 0x51F1, 0xB3CD, 0x51F3, 0xB9B9,	0x51F5, 0xC942, 0x51F6, 0xA4BF, 0x51F8, 0xA559, 0x51F9, 0xA557,
+	0x51FA, 0xA558, 0x51FD, 0xA8E7, 0x5200, 0xA44D, 0x5201, 0xA44E,	0x5203, 0xA462, 0x5206, 0xA4C0, 0x5207, 0xA4C1, 0x5208, 0xA4C2,
+	0x5209, 0xC9BE, 0x520A, 0xA55A, 0x520C, 0xC96B, 0x520E, 0xA646,	0x5210, 0xC9BF, 0x5211, 0xA644, 0x5212, 0xA645, 0x5213, 0xC9BD,
+	0x5216, 0xA647, 0x5217, 0xA643, 0x521C, 0xCA6C, 0x521D, 0xAAEC,	0x521E, 0xCA6D, 0x5221, 0xCA6E, 0x5224, 0xA750, 0x5225, 0xA74F,
+	0x5228, 0xA753, 0x5229, 0xA751, 0x522A, 0xA752, 0x522E, 0xA8ED,	0x5230, 0xA8EC, 0x5231, 0xCBD4, 0x5232, 0xCBD1, 0x5233, 0xCBD2,
+	0x5235, 0xCBD0, 0x5236, 0xA8EE, 0x5237, 0xA8EA, 0x5238, 0xA8E9,	0x523A, 0xA8EB, 0x523B, 0xA8E8, 0x5241, 0xA8EF, 0x5243, 0xAB63,
+	0x5244, 0xCDF0, 0x5246, 0xCBD3, 0x5247, 0xAB68, 0x5249, 0xCDF1,	0x524A, 0xAB64, 0x524B, 0xAB67, 0x524C, 0xAB66, 0x524D, 0xAB65,
+	0x524E, 0xAB62, 0x5252, 0xD0E8, 0x5254, 0xADE7, 0x5255, 0xD0EB,	0x5256, 0xADE5, 0x525A, 0xD0E7, 0x525B, 0xADE8, 0x525C, 0xADE6,
+	0x525D, 0xADE9, 0x525E, 0xD0E9, 0x525F, 0xD0EA, 0x5261, 0xD0E6,	0x5262, 0xD0EC, 0x5269, 0xB3D1, 0x526A, 0xB0C5, 0x526B, 0xD469,
+	0x526C, 0xD46B, 0x526D, 0xD46A, 0x526E, 0xD46C, 0x526F, 0xB0C6,	0x5272, 0xB3CE, 0x5274, 0xB3CF, 0x5275, 0xB3D0, 0x5277, 0xB6D0,
+	0x5278, 0xDCC7, 0x527A, 0xDCC6, 0x527B, 0xDCC8, 0x527C, 0xDCC9,	0x527D, 0xB6D1, 0x527F, 0xB6CF, 0x5280, 0xE141, 0x5281, 0xE142,
+	0x5282, 0xB9BB, 0x5283, 0xB9BA, 0x5284, 0xE35A, 0x5287, 0xBC40,	0x5288, 0xBC41, 0x5289, 0xBC42, 0x528A, 0xBC44, 0x528B, 0xE4F2,
+	0x528C, 0xE4F3, 0x528D, 0xBC43, 0x5291, 0xBEAF, 0x5293, 0xBEB0,	0x5296, 0xF1ED, 0x5297, 0xF5C3, 0x5298, 0xF5C2, 0x5299, 0xF7D1,
+	0x529B, 0xA44F, 0x529F, 0xA55C, 0x52A0, 0xA55B, 0x52A3, 0xA648,	0x52A6, 0xC9C0, 0x52A9, 0xA755, 0x52AA, 0xA756, 0x52AB, 0xA754,
+	0x52AC, 0xA757, 0x52AD, 0xCA6F, 0x52AE, 0xCA70, 0x52BB, 0xA8F1,	0x52BC, 0xCBD5, 0x52BE, 0xA8F0, 0x52C0, 0xCDF2, 0x52C1, 0xAB6C,
+	0x52C2, 0xCDF3, 0x52C3, 0xAB6B, 0x52C7, 0xAB69, 0x52C9, 0xAB6A,	0x52CD, 0xD0ED, 0x52D2, 0xB0C7, 0x52D3, 0xD46E, 0x52D5, 0xB0CA,
+	0x52D6, 0xD46D, 0x52D7, 0xB1E5, 0x52D8, 0xB0C9, 0x52D9, 0xB0C8,	0x52DB, 0xB3D4, 0x52DD, 0xB3D3, 0x52DE, 0xB3D2, 0x52DF, 0xB6D2,
+	0x52E2, 0xB6D5, 0x52E3, 0xB6D6, 0x52E4, 0xB6D4, 0x52E6, 0xB6D3,	0x52E9, 0xE143, 0x52EB, 0xE144, 0x52EF, 0xE4F5, 0x52F0, 0xBC45,
+	0x52F1, 0xE4F4, 0x52F3, 0xBEB1, 0x52F4, 0xECBF, 0x52F5, 0xC079,	0x52F7, 0xF1EE, 0x52F8, 0xC455, 0x52FA, 0xA463, 0x52FB, 0xA4C3,
+	0x52FC, 0xC956, 0x52FE, 0xA4C4, 0x52FF, 0xA4C5, 0x5305, 0xA55D,	0x5306, 0xA55E, 0x5308, 0xA649, 0x5309, 0xCA71, 0x530A, 0xCBD6,
+	0x530B, 0xCBD7, 0x530D, 0xAB6D, 0x530E, 0xD0EE, 0x530F, 0xB0CC,	0x5310, 0xB0CB, 0x5311, 0xD863, 0x5312, 0xD862, 0x5315, 0xA450,
+	0x5316, 0xA4C6, 0x5317, 0xA55F, 0x5319, 0xB0CD, 0x531A, 0xC943,	0x531C, 0xC96C, 0x531D, 0xA560, 0x531F, 0xC9C2, 0x5320, 0xA64B,
+	0x5321, 0xA64A, 0x5322, 0xC9C1, 0x5323, 0xA758, 0x532A, 0xADEA,	0x532D, 0xD46F, 0x532F, 0xB6D7, 0x5330, 0xE145, 0x5331, 0xB9BC,
+	0x5334, 0xE8FA, 0x5337, 0xF3FD, 0x5339, 0xA4C7, 0x533C, 0xCBD8,	0x533D, 0xCDF4, 0x533E, 0xB0D0, 0x533F, 0xB0CE, 0x5340, 0xB0CF,
+	0x5341, 0xA2CC, 0x5341, 0xA451, 0x5343, 0xA464, 0x5344, 0xA2CD,	0x5345, 0xA2CE, 0x5345, 0xA4CA, 0x5347, 0xA4C9, 0x5348, 0xA4C8,
+	0x5349, 0xA563, 0x534A, 0xA562, 0x534C, 0xC96D, 0x534D, 0xC9C3,	0x5351, 0xA8F5, 0x5352, 0xA8F2, 0x5353, 0xA8F4, 0x5354, 0xA8F3,
+	0x5357, 0xAB6E, 0x535A, 0xB3D5, 0x535C, 0xA452, 0x535E, 0xA4CB,	0x5360, 0xA565, 0x5361, 0xA564, 0x5363, 0xCA72, 0x5366, 0xA8F6,
+	0x536C, 0xC957, 0x536E, 0xA567, 0x536F, 0xA566, 0x5370, 0xA64C,	0x5371, 0xA64D, 0x5372, 0xCA73, 0x5373, 0xA759, 0x5375, 0xA75A,
+	0x5377, 0xA8F7, 0x5378, 0xA8F8, 0x5379, 0xA8F9, 0x537B, 0xAB6F,	0x537C, 0xCDF5, 0x537F, 0xADEB, 0x5382, 0xC944, 0x5384, 0xA4CC,
+	0x538A, 0xC9C4, 0x538E, 0xCA74, 0x538F, 0xCA75, 0x5392, 0xCBD9,	0x5394, 0xCBDA, 0x5396, 0xCDF7, 0x5397, 0xCDF6, 0x5398, 0xCDF9,
+	0x5399, 0xCDF8, 0x539A, 0xAB70, 0x539C, 0xD470, 0x539D, 0xADED,	0x539E, 0xD0EF, 0x539F, 0xADEC, 0x53A4, 0xD864, 0x53A5, 0xB3D6,
+	0x53A7, 0xD865, 0x53AC, 0xE146, 0x53AD, 0xB9BD, 0x53B2, 0xBC46,	0x53B4, 0xF1EF, 0x53B9, 0xC958, 0x53BB, 0xA568, 0x53C3, 0xB0D1,
+	0x53C8, 0xA453, 0x53C9, 0xA465, 0x53CA, 0xA4CE, 0x53CB, 0xA4CD,	0x53CD, 0xA4CF, 0x53D4, 0xA8FB, 0x53D6, 0xA8FA, 0x53D7, 0xA8FC,
+	0x53DB, 0xAB71, 0x53DF, 0xADEE, 0x53E1, 0xE8FB, 0x53E2, 0xC24F,	0x53E3, 0xA466, 0x53E4, 0xA56A, 0x53E5, 0xA579, 0x53E6, 0xA574,
+	0x53E8, 0xA56F, 0x53E9, 0xA56E, 0x53EA, 0xA575, 0x53EB, 0xA573,	0x53EC, 0xA56C, 0x53ED, 0xA57A, 0x53EE, 0xA56D, 0x53EF, 0xA569,
+	0x53F0, 0xA578, 0x53F1, 0xA577, 0x53F2, 0xA576, 0x53F3, 0xA56B,	0x53F5, 0xA572, 0x53F8, 0xA571, 0x53FB, 0xA57B, 0x53FC, 0xA570,
+	0x5401, 0xA653, 0x5403, 0xA659, 0x5404, 0xA655, 0x5406, 0xA65B,	0x5407, 0xC9C5, 0x5408, 0xA658, 0x5409, 0xA64E, 0x540A, 0xA651,
+	0x540B, 0xA654, 0x540C, 0xA650, 0x540D, 0xA657, 0x540E, 0xA65A,	0x540F, 0xA64F, 0x5410, 0xA652, 0x5411, 0xA656, 0x5412, 0xA65C,
+	0x5418, 0xCA7E, 0x5419, 0xCA7B, 0x541B, 0xA767, 0x541C, 0xCA7C,	0x541D, 0xA75B, 0x541E, 0xA75D, 0x541F, 0xA775, 0x5420, 0xA770,
+	0x5424, 0xCAA5, 0x5425, 0xCA7D, 0x5426, 0xA75F, 0x5427, 0xA761,	0x5428, 0xCAA4, 0x5429, 0xA768, 0x542A, 0xCA78, 0x542B, 0xA774,
+	0x542C, 0xA776, 0x542D, 0xA75C, 0x542E, 0xA76D, 0x5430, 0xCA76,	0x5431, 0xA773, 0x5433, 0xA764, 0x5435, 0xA76E, 0x5436, 0xA76F,
+	0x5437, 0xCA77, 0x5438, 0xA76C, 0x5439, 0xA76A, 0x543B, 0xA76B,	0x543C, 0xA771, 0x543D, 0xCAA1, 0x543E, 0xA75E, 0x5440, 0xA772,
+	0x5441, 0xCAA3, 0x5442, 0xA766, 0x5443, 0xA763, 0x5445, 0xCA7A,	0x5446, 0xA762, 0x5447, 0xCAA6, 0x5448, 0xA765, 0x544A, 0xA769,
+	0x544E, 0xA760, 0x544F, 0xCAA2, 0x5454, 0xCA79, 0x5460, 0xCBEB,	0x5461, 0xCBEA, 0x5462, 0xA94F, 0x5463, 0xCBED, 0x5464, 0xCBEF,
+	0x5465, 0xCBE4, 0x5466, 0xCBE7, 0x5467, 0xCBEE, 0x5468, 0xA950,	0x546B, 0xCBE1, 0x546C, 0xCBE5, 0x546F, 0xCBE9, 0x5470, 0xCE49,
+	0x5471, 0xA94B, 0x5472, 0xCE4D, 0x5473, 0xA8FD, 0x5474, 0xCBE6,	0x5475, 0xA8FE, 0x5476, 0xA94C, 0x5477, 0xA945, 0x5478, 0xA941,
+	0x547A, 0xCBE2, 0x547B, 0xA944, 0x547C, 0xA949, 0x547D, 0xA952,	0x547E, 0xCBE3, 0x547F, 0xCBDC, 0x5480, 0xA943, 0x5481, 0xCBDD,
+	0x5482, 0xCBDF, 0x5484, 0xA946, 0x5486, 0xA948, 0x5487, 0xCBDB,	0x5488, 0xCBE0, 0x548B, 0xA951, 0x548C, 0xA94D, 0x548D, 0xCBE8,
+	0x548E, 0xA953, 0x5490, 0xA94A, 0x5491, 0xCBDE, 0x5492, 0xA947,	0x5495, 0xA942, 0x5496, 0xA940, 0x5498, 0xCBEC, 0x549A, 0xA94E,
+	0x54A0, 0xCE48, 0x54A1, 0xCDFB, 0x54A2, 0xCE4B, 0x54A5, 0xCDFD,	0x54A6, 0xAB78, 0x54A7, 0xABA8, 0x54A8, 0xAB74, 0x54A9, 0xABA7,
+	0x54AA, 0xAB7D, 0x54AB, 0xABA4, 0x54AC, 0xAB72, 0x54AD, 0xCDFC,	0x54AE, 0xCE43, 0x54AF, 0xABA3, 0x54B0, 0xCE4F, 0x54B1, 0xABA5,
+	0x54B3, 0xAB79, 0x54B6, 0xCE45, 0x54B7, 0xCE42, 0x54B8, 0xAB77,	0x54BA, 0xCDFA, 0x54BB, 0xABA6, 0x54BC, 0xCE4A, 0x54BD, 0xAB7C,
+	0x54BE, 0xCE4C, 0x54BF, 0xABA9, 0x54C0, 0xAB73, 0x54C1, 0xAB7E,	0x54C2, 0xAB7B, 0x54C3, 0xCE40, 0x54C4, 0xABA1, 0x54C5, 0xCE46,
+	0x54C6, 0xCE47, 0x54C7, 0xAB7A, 0x54C8, 0xABA2, 0x54C9, 0xAB76,	0x54CE, 0xAB75, 0x54CF, 0xCDFE, 0x54D6, 0xCE44, 0x54DE, 0xCE4E,
+	0x54E0, 0xD144, 0x54E1, 0xADFB, 0x54E2, 0xD0F1, 0x54E4, 0xD0F6,	0x54E5, 0xADF4, 0x54E6, 0xAE40, 0x54E7, 0xD0F4, 0x54E8, 0xADEF,
+	0x54E9, 0xADF9, 0x54EA, 0xADFE, 0x54EB, 0xD0FB, 0x54ED, 0xADFA,	0x54EE, 0xADFD, 0x54F1, 0xD0FE, 0x54F2, 0xADF5, 0x54F3, 0xD0F5,
+	0x54F7, 0xD142, 0x54F8, 0xD143, 0x54FA, 0xADF7, 0x54FB, 0xD141,	0x54FC, 0xADF3, 0x54FD, 0xAE43, 0x54FF, 0xD0F8, 0x5501, 0xADF1,
+	0x5503, 0xD146, 0x5504, 0xD0F9, 0x5505, 0xD0FD, 0x5506, 0xADF6,	0x5507, 0xAE42, 0x5508, 0xD0FA, 0x5509, 0xADFC, 0x550A, 0xD140,
+	0x550B, 0xD147, 0x550C, 0xD4A1, 0x550E, 0xD145, 0x550F, 0xAE44,	0x5510, 0xADF0, 0x5511, 0xD0FC, 0x5512, 0xD0F3, 0x5514, 0xADF8,
+	0x5517, 0xD0F2, 0x551A, 0xD0F7, 0x5526, 0xD0F0, 0x5527, 0xAE41,	0x552A, 0xD477, 0x552C, 0xB0E4, 0x552D, 0xD4A7, 0x552E, 0xB0E2,
+	0x552F, 0xB0DF, 0x5530, 0xD47C, 0x5531, 0xB0DB, 0x5532, 0xD4A2,	0x5533, 0xB0E6, 0x5534, 0xD476, 0x5535, 0xD47B, 0x5536, 0xD47A,
+	0x5537, 0xADF2, 0x5538, 0xB0E1, 0x5539, 0xD4A5, 0x553B, 0xD4A8,	0x553C, 0xD473, 0x553E, 0xB3E8, 0x5540, 0xD4A9, 0x5541, 0xB0E7,
+	0x5543, 0xB0D9, 0x5544, 0xB0D6, 0x5545, 0xD47E, 0x5546, 0xB0D3,	0x5548, 0xD4A6, 0x554A, 0xB0DA, 0x554B, 0xD4AA, 0x554D, 0xD474,
+	0x554E, 0xD4A4, 0x554F, 0xB0DD, 0x5550, 0xD475, 0x5551, 0xD478,	0x5552, 0xD47D, 0x5555, 0xB0DE, 0x5556, 0xB0DC, 0x5557, 0xB0E8,
+	0x555C, 0xB0E3, 0x555E, 0xB0D7, 0x555F, 0xB1D2, 0x5561, 0xB0D8,	0x5562, 0xD479, 0x5563, 0xB0E5, 0x5564, 0xB0E0, 0x5565, 0xD4A3,
+	0x5566, 0xB0D5, 0x556A, 0xB0D4, 0x5575, 0xD471, 0x5576, 0xD472,	0x5577, 0xD86A, 0x557B, 0xB3D7, 0x557C, 0xB3DA, 0x557D, 0xD875,
+	0x557E, 0xB3EE, 0x557F, 0xD878, 0x5580, 0xB3D8, 0x5581, 0xD871,	0x5582, 0xB3DE, 0x5583, 0xB3E4, 0x5584, 0xB5BD, 0x5587, 0xB3E2,
+	0x5588, 0xD86E, 0x5589, 0xB3EF, 0x558A, 0xB3DB, 0x558B, 0xB3E3,	0x558C, 0xD876, 0x558D, 0xDCD7, 0x558E, 0xD87B, 0x558F, 0xD86F,
+	0x5591, 0xD866, 0x5592, 0xD873, 0x5593, 0xD86D, 0x5594, 0xB3E1,	0x5595, 0xD879, 0x5598, 0xB3DD, 0x5599, 0xB3F1, 0x559A, 0xB3EA,
+	0x559C, 0xB3DF, 0x559D, 0xB3DC, 0x559F, 0xB3E7, 0x55A1, 0xD87A,	0x55A2, 0xD86C, 0x55A3, 0xD872, 0x55A4, 0xD874, 0x55A5, 0xD868,
+	0x55A6, 0xD877, 0x55A7, 0xB3D9, 0x55A8, 0xD867, 0x55AA, 0xB3E0,	0x55AB, 0xB3F0, 0x55AC, 0xB3EC, 0x55AD, 0xD869, 0x55AE, 0xB3E6,
+	0x55B1, 0xB3ED, 0x55B2, 0xB3E9, 0x55B3, 0xB3E5, 0x55B5, 0xD870,	0x55BB, 0xB3EB, 0x55BF, 0xDCD5, 0x55C0, 0xDCD1, 0x55C2, 0xDCE0,
+	0x55C3, 0xDCCA, 0x55C4, 0xDCD3, 0x55C5, 0xB6E5, 0x55C6, 0xB6E6,	0x55C7, 0xB6DE, 0x55C8, 0xDCDC, 0x55C9, 0xB6E8, 0x55CA, 0xDCCF,
+	0x55CB, 0xDCCE, 0x55CC, 0xDCCC, 0x55CD, 0xDCDE, 0x55CE, 0xB6DC,	0x55CF, 0xDCD8, 0x55D0, 0xDCCD, 0x55D1, 0xB6DF, 0x55D2, 0xDCD6,
+	0x55D3, 0xB6DA, 0x55D4, 0xDCD2, 0x55D5, 0xDCD9, 0x55D6, 0xDCDB,	0x55D9, 0xDCDF, 0x55DA, 0xB6E3, 0x55DB, 0xDCCB, 0x55DC, 0xB6DD,
+	0x55DD, 0xDCD0, 0x55DF, 0xB6D8, 0x55E1, 0xB6E4, 0x55E2, 0xDCDA,	0x55E3, 0xB6E0, 0x55E4, 0xB6E1, 0x55E5, 0xB6E7, 0x55E6, 0xB6DB,
+	0x55E7, 0xA25F, 0x55E8, 0xB6D9, 0x55E9, 0xDCD4, 0x55EF, 0xB6E2,	0x55F2, 0xDCDD, 0x55F6, 0xB9CD, 0x55F7, 0xB9C8, 0x55F9, 0xE155,
+	0x55FA, 0xE151, 0x55FC, 0xE14B, 0x55FD, 0xB9C2, 0x55FE, 0xB9BE,	0x55FF, 0xE154, 0x5600, 0xB9BF, 0x5601, 0xE14E, 0x5602, 0xE150,
+	0x5604, 0xE153, 0x5606, 0xB9C4, 0x5608, 0xB9CB, 0x5609, 0xB9C5,	0x560C, 0xE149, 0x560D, 0xB9C6, 0x560E, 0xB9C7, 0x560F, 0xE14C,
+	0x5610, 0xB9CC, 0x5612, 0xE14A, 0x5613, 0xE14F, 0x5614, 0xB9C3,	0x5615, 0xE148, 0x5616, 0xB9C9, 0x5617, 0xB9C1, 0x561B, 0xB9C0,
+	0x561C, 0xE14D, 0x561D, 0xE152, 0x561F, 0xB9CA, 0x5627, 0xE147,	0x5629, 0xBC4D, 0x562A, 0xE547, 0x562C, 0xE544, 0x562E, 0xBC47,
+	0x562F, 0xBC53, 0x5630, 0xBC54, 0x5632, 0xBC4A, 0x5633, 0xE542,	0x5634, 0xBC4C, 0x5635, 0xE4F9, 0x5636, 0xBC52, 0x5638, 0xE546,
+	0x5639, 0xBC49, 0x563A, 0xE548, 0x563B, 0xBC48, 0x563D, 0xE543,	0x563E, 0xE545, 0x563F, 0xBC4B, 0x5640, 0xE541, 0x5641, 0xE4FA,
+	0x5642, 0xE4F7, 0x5645, 0xD86B, 0x5646, 0xE4FD, 0x5648, 0xE4F6,	0x5649, 0xE4FC, 0x564A, 0xE4FB, 0x564C, 0xE4F8, 0x564E, 0xBC4F,
+	0x5653, 0xBC4E, 0x5657, 0xBC50, 0x5658, 0xE4FE, 0x5659, 0xBEB2,	0x565A, 0xE540, 0x565E, 0xE945, 0x5660, 0xE8FD, 0x5662, 0xBEBE,
+	0x5663, 0xE942, 0x5664, 0xBEB6, 0x5665, 0xBEBA, 0x5666, 0xE941,	0x5668, 0xBEB9, 0x5669, 0xBEB5, 0x566A, 0xBEB8, 0x566B, 0xBEB3,
+	0x566C, 0xBEBD, 0x566D, 0xE943, 0x566E, 0xE8FE, 0x566F, 0xBEBC,	0x5670, 0xE8FC, 0x5671, 0xBEBB, 0x5672, 0xE944, 0x5673, 0xE940,
+	0x5674, 0xBC51, 0x5676, 0xBEBF, 0x5677, 0xE946, 0x5678, 0xBEB7,	0x5679, 0xBEB4, 0x567E, 0xECC6, 0x567F, 0xECC8, 0x5680, 0xC07B,
+	0x5681, 0xECC9, 0x5682, 0xECC7, 0x5683, 0xECC5, 0x5684, 0xECC4,	0x5685, 0xC07D, 0x5686, 0xECC3, 0x5687, 0xC07E, 0x568C, 0xECC1,
+	0x568D, 0xECC2, 0x568E, 0xC07A, 0x568F, 0xC0A1, 0x5690, 0xC07C,	0x5693, 0xECC0, 0x5695, 0xC250, 0x5697, 0xEFBC, 0x5698, 0xEFBA,
+	0x5699, 0xEFBF, 0x569A, 0xEFBD, 0x569C, 0xEFBB, 0x569D, 0xEFBE,	0x56A5, 0xC360, 0x56A6, 0xF1F2, 0x56A7, 0xF1F3, 0x56A8, 0xC456,
+	0x56AA, 0xF1F4, 0x56AB, 0xF1F0, 0x56AC, 0xF1F5, 0x56AD, 0xF1F1,	0x56AE, 0xC251, 0x56B2, 0xF3FE, 0x56B3, 0xF441, 0x56B4, 0xC459,
+	0x56B5, 0xF440, 0x56B6, 0xC458, 0x56B7, 0xC457, 0x56BC, 0xC45A,	0x56BD, 0xF5C5, 0x56BE, 0xF5C6, 0x56C0, 0xC4DA, 0x56C1, 0xC4D9,
+	0x56C2, 0xC4DB, 0x56C3, 0xF5C4, 0x56C5, 0xF6D8, 0x56C6, 0xF6D7,	0x56C8, 0xC56D, 0x56C9, 0xC56F, 0x56CA, 0xC56E, 0x56CB, 0xF6D9,
+	0x56CC, 0xC5C8, 0x56CD, 0xF8A6, 0x56D1, 0xC5F1, 0x56D3, 0xF8A5,	0x56D4, 0xF8EE, 0x56D7, 0xC949, 0x56DA, 0xA57D, 0x56DB, 0xA57C,
+	0x56DD, 0xA65F, 0x56DE, 0xA65E, 0x56DF, 0xC9C7, 0x56E0, 0xA65D,	0x56E1, 0xC9C6, 0x56E4, 0xA779, 0x56E5, 0xCAA9, 0x56E7, 0xCAA8,
+	0x56EA, 0xA777, 0x56EB, 0xA77A, 0x56EE, 0xCAA7, 0x56F0, 0xA778,	0x56F7, 0xCBF0, 0x56F9, 0xCBF1, 0x56FA, 0xA954, 0x56FF, 0xABAA,
+	0x5701, 0xD148, 0x5702, 0xD149, 0x5703, 0xAE45, 0x5704, 0xAE46,	0x5707, 0xD4AC, 0x5708, 0xB0E9, 0x5709, 0xB0EB, 0x570A, 0xD4AB,
+	0x570B, 0xB0EA, 0x570C, 0xD87C, 0x570D, 0xB3F2, 0x5712, 0xB6E9,	0x5713, 0xB6EA, 0x5714, 0xDCE1, 0x5716, 0xB9CF, 0x5718, 0xB9CE,
+	0x571A, 0xE549, 0x571B, 0xE948, 0x571C, 0xE947, 0x571E, 0xF96B,	0x571F, 0xA467, 0x5720, 0xC959, 0x5722, 0xC96E, 0x5723, 0xC96F,
+	0x5728, 0xA662, 0x5729, 0xA666, 0x572A, 0xC9C9, 0x572C, 0xA664,	0x572D, 0xA663, 0x572E, 0xC9C8, 0x572F, 0xA665, 0x5730, 0xA661,
+	0x5733, 0xA660, 0x5734, 0xC9CA, 0x573B, 0xA7A6, 0x573E, 0xA7A3,	0x5740, 0xA77D, 0x5741, 0xCAAA, 0x5745, 0xCAAB, 0x5747, 0xA7A1,
+	0x5749, 0xCAAD, 0x574A, 0xA77B, 0x574B, 0xCAAE, 0x574C, 0xCAAC,	0x574D, 0xA77E, 0x574E, 0xA7A2, 0x574F, 0xA7A5, 0x5750, 0xA7A4,
+	0x5751, 0xA77C, 0x5752, 0xCAAF, 0x5761, 0xA959, 0x5762, 0xCBFE,	0x5764, 0xA95B, 0x5766, 0xA95A, 0x5768, 0xCC40, 0x5769, 0xA958,
+	0x576A, 0xA957, 0x576B, 0xCBF5, 0x576D, 0xCBF4, 0x576F, 0xCBF2,	0x5770, 0xCBF7, 0x5771, 0xCBF6, 0x5772, 0xCBF3, 0x5773, 0xCBFC,
+	0x5774, 0xCBFD, 0x5775, 0xCBFA, 0x5776, 0xCBF8, 0x5777, 0xA956,	0x577B, 0xCBFB, 0x577C, 0xA95C, 0x577D, 0xCC41, 0x5780, 0xCBF9,
+	0x5782, 0xABAB, 0x5783, 0xA955, 0x578B, 0xABAC, 0x578C, 0xCE54,	0x578F, 0xCE5A, 0x5793, 0xABB2, 0x5794, 0xCE58, 0x5795, 0xCE5E,
+	0x5797, 0xCE55, 0x5798, 0xCE59, 0x5799, 0xCE5B, 0x579A, 0xCE5D,	0x579B, 0xCE57, 0x579D, 0xCE56, 0x579E, 0xCE51, 0x579F, 0xCE52,
+	0x57A0, 0xABAD, 0x57A2, 0xABAF, 0x57A3, 0xABAE, 0x57A4, 0xCE53,	0x57A5, 0xCE5C, 0x57AE, 0xABB1, 0x57B5, 0xCE50, 0x57B6, 0xD153,
+	0x57B8, 0xD152, 0x57B9, 0xD157, 0x57BA, 0xD14E, 0x57BC, 0xD151,	0x57BD, 0xD150, 0x57BF, 0xD154, 0x57C1, 0xD158, 0x57C2, 0xAE47,
+	0x57C3, 0xAE4A, 0x57C6, 0xD14F, 0x57C7, 0xD155, 0x57CB, 0xAE49,	0x57CC, 0xD14A, 0x57CE, 0xABB0, 0x57CF, 0xD4BA, 0x57D0, 0xD156,
+	0x57D2, 0xD14D, 0x57D4, 0xAE48, 0x57D5, 0xD14C, 0x57DC, 0xD4B1,	0x57DF, 0xB0EC, 0x57E0, 0xB0F0, 0x57E1, 0xD4C1, 0x57E2, 0xD4AF,
+	0x57E3, 0xD4BD, 0x57E4, 0xB0F1, 0x57E5, 0xD4BF, 0x57E7, 0xD4C5,	0x57E9, 0xD4C9, 0x57EC, 0xD4C0, 0x57ED, 0xD4B4, 0x57EE, 0xD4BC,
+	0x57F0, 0xD4CA, 0x57F1, 0xD4C8, 0x57F2, 0xD4BE, 0x57F3, 0xD4B9,	0x57F4, 0xD4B2, 0x57F5, 0xD8A6, 0x57F6, 0xD4B0, 0x57F7, 0xB0F5,
+	0x57F8, 0xD4B7, 0x57F9, 0xB0F6, 0x57FA, 0xB0F2, 0x57FB, 0xD4AD,	0x57FC, 0xD4C3, 0x57FD, 0xD4B5, 0x5800, 0xD4B3, 0x5801, 0xD4C6,
+	0x5802, 0xB0F3, 0x5804, 0xD4CC, 0x5805, 0xB0ED, 0x5806, 0xB0EF,	0x5807, 0xD4BB, 0x5808, 0xD4B6, 0x5809, 0xAE4B, 0x580A, 0xB0EE,
+	0x580B, 0xD4B8, 0x580C, 0xD4C7, 0x580D, 0xD4CB, 0x580E, 0xD4C2,	0x5810, 0xD4C4, 0x5814, 0xD4AE, 0x5819, 0xD8A1, 0x581B, 0xD8AA,
+	0x581C, 0xD8A9, 0x581D, 0xB3FA, 0x581E, 0xD8A2, 0x5820, 0xB3FB,	0x5821, 0xB3F9, 0x5823, 0xD8A4, 0x5824, 0xB3F6, 0x5825, 0xD8A8,
+	0x5827, 0xD8A3, 0x5828, 0xD8A5, 0x5829, 0xD87D, 0x582A, 0xB3F4,	0x582C, 0xD8B2, 0x582D, 0xD8B1, 0x582E, 0xD8AE, 0x582F, 0xB3F3,
+	0x5830, 0xB3F7, 0x5831, 0xB3F8, 0x5832, 0xD14B, 0x5833, 0xD8AB,	0x5834, 0xB3F5, 0x5835, 0xB0F4, 0x5836, 0xD8AD, 0x5837, 0xD87E,
+	0x5838, 0xD8B0, 0x5839, 0xD8AF, 0x583B, 0xD8B3, 0x583D, 0xDCEF,	0x583F, 0xD8AC, 0x5848, 0xD8A7, 0x5849, 0xDCE7, 0x584A, 0xB6F4,
+	0x584B, 0xB6F7, 0x584C, 0xB6F2, 0x584D, 0xDCE6, 0x584E, 0xDCEA,	0x584F, 0xDCE5, 0x5851, 0xB6EC, 0x5852, 0xB6F6, 0x5853, 0xDCE2,
+	0x5854, 0xB6F0, 0x5855, 0xDCE9, 0x5857, 0xB6EE, 0x5858, 0xB6ED,	0x5859, 0xDCEC, 0x585A, 0xB6EF, 0x585B, 0xDCEE, 0x585D, 0xDCEB,
+	0x585E, 0xB6EB, 0x5862, 0xB6F5, 0x5863, 0xDCF0, 0x5864, 0xDCE4,	0x5865, 0xDCED, 0x5868, 0xDCE3, 0x586B, 0xB6F1, 0x586D, 0xB6F3,
+	0x586F, 0xDCE8, 0x5871, 0xDCF1, 0x5874, 0xE15D, 0x5875, 0xB9D0,	0x5876, 0xE163, 0x5879, 0xB9D5, 0x587A, 0xE15F, 0x587B, 0xE166,
+	0x587C, 0xE157, 0x587D, 0xB9D7, 0x587E, 0xB9D1, 0x587F, 0xE15C,	0x5880, 0xBC55, 0x5881, 0xE15B, 0x5882, 0xE164, 0x5883, 0xB9D2,
+	0x5885, 0xB9D6, 0x5886, 0xE15A, 0x5887, 0xE160, 0x5888, 0xE165,	0x5889, 0xE156, 0x588A, 0xB9D4, 0x588B, 0xE15E, 0x588E, 0xE162,
+	0x588F, 0xE168, 0x5890, 0xE158, 0x5891, 0xE161, 0x5893, 0xB9D3,	0x5894, 0xE167, 0x5898, 0xE159, 0x589C, 0xBC59, 0x589D, 0xE54B,
+	0x589E, 0xBC57, 0x589F, 0xBC56, 0x58A0, 0xE54D, 0x58A1, 0xE552,	0x58A3, 0xE54E, 0x58A5, 0xE551, 0x58A6, 0xBC5C, 0x58A8, 0xBEA5,
+	0x58A9, 0xBC5B, 0x58AB, 0xE54A, 0x58AC, 0xE550, 0x58AE, 0xBC5A,	0x58AF, 0xE54F, 0x58B1, 0xE54C, 0x58B3, 0xBC58, 0x58BA, 0xE94D,
+	0x58BB, 0xF9D9, 0x58BC, 0xE94F, 0x58BD, 0xE94A, 0x58BE, 0xBEC1,	0x58BF, 0xE94C, 0x58C1, 0xBEC0, 0x58C2, 0xE94E, 0x58C5, 0xBEC3,
+	0x58C6, 0xE950, 0x58C7, 0xBEC2, 0x58C8, 0xE949, 0x58C9, 0xE94B,	0x58CE, 0xC0A5, 0x58CF, 0xECCC, 0x58D1, 0xC0A4, 0x58D2, 0xECCD,
+	0x58D3, 0xC0A3, 0x58D4, 0xECCB, 0x58D5, 0xC0A2, 0x58D6, 0xECCA,	0x58D8, 0xC253, 0x58D9, 0xC252, 0x58DA, 0xF1F6, 0x58DB, 0xF1F8,
+	0x58DD, 0xF1F7, 0x58DE, 0xC361, 0x58DF, 0xC362, 0x58E2, 0xC363,	0x58E3, 0xF442, 0x58E4, 0xC45B, 0x58E7, 0xF7D3, 0x58E8, 0xF7D2,
+	0x58E9, 0xC5F2, 0x58EB, 0xA468, 0x58EC, 0xA4D0, 0x58EF, 0xA7A7,	0x58F4, 0xCE5F, 0x58F9, 0xB3FC, 0x58FA, 0xB3FD, 0x58FC, 0xDCF2,
+	0x58FD, 0xB9D8, 0x58FE, 0xE169, 0x58FF, 0xE553, 0x5903, 0xC95A,	0x5906, 0xCAB0, 0x590C, 0xCC42, 0x590D, 0xCE60, 0x590E, 0xD159,
+	0x590F, 0xAE4C, 0x5912, 0xF1F9, 0x5914, 0xC4DC, 0x5915, 0xA469,	0x5916, 0xA57E, 0x5917, 0xC970, 0x5919, 0xA667, 0x591A, 0xA668,
+	0x591C, 0xA95D, 0x5920, 0xB0F7, 0x5922, 0xB9DA, 0x5924, 0xB9DB,	0x5925, 0xB9D9, 0x5927, 0xA46A, 0x5929, 0xA4D1, 0x592A, 0xA4D3,
+	0x592B, 0xA4D2, 0x592C, 0xC95B, 0x592D, 0xA4D4, 0x592E, 0xA5A1,	0x592F, 0xC971, 0x5931, 0xA5A2, 0x5937, 0xA669, 0x5938, 0xA66A,
+	0x593C, 0xC9CB, 0x593E, 0xA7A8, 0x5940, 0xCAB1, 0x5944, 0xA961,	0x5945, 0xCC43, 0x5947, 0xA95F, 0x5948, 0xA960, 0x5949, 0xA95E,
+	0x594A, 0xD15A, 0x594E, 0xABB6, 0x594F, 0xABB5, 0x5950, 0xABB7,	0x5951, 0xABB4, 0x5953, 0xCE61, 0x5954, 0xA962, 0x5955, 0xABB3,
+	0x5957, 0xAE4D, 0x5958, 0xAE4E, 0x595A, 0xAE4F, 0x595C, 0xD4CD,	0x5960, 0xB3FE, 0x5961, 0xD8B4, 0x5962, 0xB0F8, 0x5967, 0xB6F8,
+	0x5969, 0xB9DD, 0x596A, 0xB9DC, 0x596B, 0xE16A, 0x596D, 0xBC5D,	0x596E, 0xBEC4, 0x5970, 0xEFC0, 0x5971, 0xF6DA, 0x5972, 0xF7D4,
+	0x5973, 0xA46B, 0x5974, 0xA5A3, 0x5976, 0xA5A4, 0x5977, 0xC9D1,	0x5978, 0xA66C, 0x5979, 0xA66F, 0x597B, 0xC9CF, 0x597C, 0xC9CD,
+	0x597D, 0xA66E, 0x597E, 0xC9D0, 0x597F, 0xC9D2, 0x5980, 0xC9CC,	0x5981, 0xA671, 0x5982, 0xA670, 0x5983, 0xA66D, 0x5984, 0xA66B,
+	0x5985, 0xC9CE, 0x598A, 0xA7B3, 0x598D, 0xA7B0, 0x598E, 0xCAB6,	0x598F, 0xCAB9, 0x5990, 0xCAB8, 0x5992, 0xA7AA, 0x5993, 0xA7B2,
+	0x5996, 0xA7AF, 0x5997, 0xCAB5, 0x5998, 0xCAB3, 0x5999, 0xA7AE,	0x599D, 0xA7A9, 0x599E, 0xA7AC, 0x59A0, 0xCAB4, 0x59A1, 0xCABB,
+	0x59A2, 0xCAB7, 0x59A3, 0xA7AD, 0x59A4, 0xA7B1, 0x59A5, 0xA7B4,	0x59A6, 0xCAB2, 0x59A7, 0xCABA, 0x59A8, 0xA7AB, 0x59AE, 0xA967,
+	0x59AF, 0xA96F, 0x59B1, 0xCC4F, 0x59B2, 0xCC48, 0x59B3, 0xA970,	0x59B4, 0xCC53, 0x59B5, 0xCC44, 0x59B6, 0xCC4B, 0x59B9, 0xA966,
+	0x59BA, 0xCC45, 0x59BB, 0xA964, 0x59BC, 0xCC4C, 0x59BD, 0xCC50,	0x59BE, 0xA963, 0x59C0, 0xCC51, 0x59C1, 0xCC4A, 0x59C3, 0xCC4D,
+	0x59C5, 0xA972, 0x59C6, 0xA969, 0x59C7, 0xCC54, 0x59C8, 0xCC52,	0x59CA, 0xA96E, 0x59CB, 0xA96C, 0x59CC, 0xCC49, 0x59CD, 0xA96B,
+	0x59CE, 0xCC47, 0x59CF, 0xCC46, 0x59D0, 0xA96A, 0x59D1, 0xA968,	0x59D2, 0xA971, 0x59D3, 0xA96D, 0x59D4, 0xA965, 0x59D6, 0xCC4E,
+	0x59D8, 0xABB9, 0x59DA, 0xABC0, 0x59DB, 0xCE6F, 0x59DC, 0xABB8,	0x59DD, 0xCE67, 0x59DE, 0xCE63, 0x59E0, 0xCE73, 0x59E1, 0xCE62,
+	0x59E3, 0xABBB, 0x59E4, 0xCE6C, 0x59E5, 0xABBE, 0x59E6, 0xABC1,	0x59E8, 0xABBC, 0x59E9, 0xCE70, 0x59EA, 0xABBF, 0x59EC, 0xAE56,
+	0x59ED, 0xCE76, 0x59EE, 0xCE64, 0x59F1, 0xCE66, 0x59F2, 0xCE6D,	0x59F3, 0xCE71, 0x59F4, 0xCE75, 0x59F5, 0xCE72, 0x59F6, 0xCE6B,
+	0x59F7, 0xCE6E, 0x59FA, 0xCE68, 0x59FB, 0xABC3, 0x59FC, 0xCE6A,	0x59FD, 0xCE69, 0x59FE, 0xCE74, 0x59FF, 0xABBA, 0x5A00, 0xCE65,
+	0x5A01, 0xABC2, 0x5A03, 0xABBD, 0x5A09, 0xAE5C, 0x5A0A, 0xD162,	0x5A0C, 0xAE5B, 0x5A0F, 0xD160, 0x5A11, 0xAE50, 0x5A13, 0xAE55,
+	0x5A15, 0xD15F, 0x5A16, 0xD15C, 0x5A17, 0xD161, 0x5A18, 0xAE51,	0x5A19, 0xD15B, 0x5A1B, 0xAE54, 0x5A1C, 0xAE52, 0x5A1E, 0xD163,
+	0x5A1F, 0xAE53, 0x5A20, 0xAE57, 0x5A23, 0xAE58, 0x5A25, 0xAE5A,	0x5A29, 0xAE59, 0x5A2D, 0xD15D, 0x5A2E, 0xD15E, 0x5A33, 0xD164,
+	0x5A35, 0xD4D4, 0x5A36, 0xB0F9, 0x5A37, 0xD8C2, 0x5A38, 0xD4D3,	0x5A39, 0xD4E6, 0x5A3C, 0xB140, 0x5A3E, 0xD4E4, 0x5A40, 0xB0FE,
+	0x5A41, 0xB0FA, 0x5A42, 0xD4ED, 0x5A43, 0xD4DD, 0x5A44, 0xD4E0,	0x5A46, 0xB143, 0x5A47, 0xD4EA, 0x5A48, 0xD4E2, 0x5A49, 0xB0FB,
+	0x5A4A, 0xB144, 0x5A4C, 0xD4E7, 0x5A4D, 0xD4E5, 0x5A50, 0xD4D6,	0x5A51, 0xD4EB, 0x5A52, 0xD4DF, 0x5A53, 0xD4DA, 0x5A55, 0xD4D0,
+	0x5A56, 0xD4EC, 0x5A57, 0xD4DC, 0x5A58, 0xD4CF, 0x5A5A, 0xB142,	0x5A5B, 0xD4E1, 0x5A5C, 0xD4EE, 0x5A5D, 0xD4DE, 0x5A5E, 0xD4D2,
+	0x5A5F, 0xD4D7, 0x5A60, 0xD4CE, 0x5A62, 0xB141, 0x5A64, 0xD4DB,	0x5A65, 0xD4D8, 0x5A66, 0xB0FC, 0x5A67, 0xD4D1, 0x5A69, 0xD4E9,
+	0x5A6A, 0xB0FD, 0x5A6C, 0xD4D9, 0x5A6D, 0xD4D5, 0x5A70, 0xD4E8,	0x5A77, 0xB440, 0x5A78, 0xD8BB, 0x5A7A, 0xD8B8, 0x5A7B, 0xD8C9,
+	0x5A7C, 0xD8BD, 0x5A7D, 0xD8CA, 0x5A7F, 0xB442, 0x5A83, 0xD8C6,	0x5A84, 0xD8C3, 0x5A8A, 0xD8C4, 0x5A8B, 0xD8C7, 0x5A8C, 0xD8CB,
+	0x5A8E, 0xD4E3, 0x5A8F, 0xD8CD, 0x5A90, 0xDD47, 0x5A92, 0xB443,	0x5A93, 0xD8CE, 0x5A94, 0xD8B6, 0x5A95, 0xD8C0, 0x5A97, 0xD8C5,
+	0x5A9A, 0xB441, 0x5A9B, 0xB444, 0x5A9C, 0xD8CC, 0x5A9D, 0xD8CF,	0x5A9E, 0xD8BA, 0x5A9F, 0xD8B7, 0x5AA2, 0xD8B9, 0x5AA5, 0xD8BE,
+	0x5AA6, 0xD8BC, 0x5AA7, 0xB445, 0x5AA9, 0xD8C8, 0x5AAC, 0xD8BF,	0x5AAE, 0xD8C1, 0x5AAF, 0xD8B5, 0x5AB0, 0xDCFA, 0x5AB1, 0xDCF8,
+	0x5AB2, 0xB742, 0x5AB3, 0xB740, 0x5AB4, 0xDD43, 0x5AB5, 0xDCF9,	0x5AB6, 0xDD44, 0x5AB7, 0xDD40, 0x5AB8, 0xDCF7, 0x5AB9, 0xDD46,
+	0x5ABA, 0xDCF6, 0x5ABB, 0xDCFD, 0x5ABC, 0xB6FE, 0x5ABD, 0xB6FD,	0x5ABE, 0xB6FC, 0x5ABF, 0xDCFB, 0x5AC0, 0xDD41, 0x5AC1, 0xB6F9,
+	0x5AC2, 0xB741, 0x5AC4, 0xDCF4, 0x5AC6, 0xDCFE, 0x5AC7, 0xDCF3,	0x5AC8, 0xDCFC, 0x5AC9, 0xB6FA, 0x5ACA, 0xDD42, 0x5ACB, 0xDCF5,
+	0x5ACC, 0xB6FB, 0x5ACD, 0xDD45, 0x5AD5, 0xE16E, 0x5AD6, 0xB9E2,	0x5AD7, 0xB9E1, 0x5AD8, 0xB9E3, 0x5AD9, 0xE17A, 0x5ADA, 0xE170,
+	0x5ADB, 0xE176, 0x5ADC, 0xE16B, 0x5ADD, 0xE179, 0x5ADE, 0xE178,	0x5ADF, 0xE17C, 0x5AE0, 0xE175, 0x5AE1, 0xB9DE, 0x5AE2, 0xE174,
+	0x5AE3, 0xB9E4, 0x5AE5, 0xE16D, 0x5AE6, 0xB9DF, 0x5AE8, 0xE17B,	0x5AE9, 0xB9E0, 0x5AEA, 0xE16F, 0x5AEB, 0xE172, 0x5AEC, 0xE177,
+	0x5AED, 0xE171, 0x5AEE, 0xE16C, 0x5AF3, 0xE173, 0x5AF4, 0xE555,	0x5AF5, 0xBC61, 0x5AF6, 0xE558, 0x5AF7, 0xE557, 0x5AF8, 0xE55A,
+	0x5AF9, 0xE55C, 0x5AFA, 0xF9DC, 0x5AFB, 0xBC5F, 0x5AFD, 0xE556,	0x5AFF, 0xE554, 0x5B01, 0xE55D, 0x5B02, 0xE55B, 0x5B03, 0xE559,
+	0x5B05, 0xE55F, 0x5B07, 0xE55E, 0x5B08, 0xBC63, 0x5B09, 0xBC5E,	0x5B0B, 0xBC60, 0x5B0C, 0xBC62, 0x5B0F, 0xE560, 0x5B10, 0xE957,
+	0x5B13, 0xE956, 0x5B14, 0xE955, 0x5B16, 0xE958, 0x5B17, 0xE951,	0x5B19, 0xE952, 0x5B1A, 0xE95A, 0x5B1B, 0xE953, 0x5B1D, 0xBEC5,
+	0x5B1E, 0xE95C, 0x5B20, 0xE95B, 0x5B21, 0xE954, 0x5B23, 0xECD1,	0x5B24, 0xC0A8, 0x5B25, 0xECCF, 0x5B26, 0xECD4, 0x5B27, 0xECD3,
+	0x5B28, 0xE959, 0x5B2A, 0xC0A7, 0x5B2C, 0xECD2, 0x5B2D, 0xECCE,	0x5B2E, 0xECD6, 0x5B2F, 0xECD5, 0x5B30, 0xC0A6, 0x5B32, 0xECD0,
+	0x5B34, 0xBEC6, 0x5B38, 0xC254, 0x5B3C, 0xEFC1, 0x5B3D, 0xF1FA,	0x5B3E, 0xF1FB, 0x5B3F, 0xF1FC, 0x5B40, 0xC45C, 0x5B43, 0xC45D,
+	0x5B45, 0xF443, 0x5B47, 0xF5C8, 0x5B48, 0xF5C7, 0x5B4B, 0xF6DB,	0x5B4C, 0xF6DC, 0x5B4D, 0xF7D5, 0x5B4E, 0xF8A7, 0x5B50, 0xA46C,
+	0x5B51, 0xA46D, 0x5B53, 0xA46E, 0x5B54, 0xA4D5, 0x5B55, 0xA5A5,	0x5B56, 0xC9D3, 0x5B57, 0xA672, 0x5B58, 0xA673, 0x5B5A, 0xA7B7,
+	0x5B5B, 0xA7B8, 0x5B5C, 0xA7B6, 0x5B5D, 0xA7B5, 0x5B5F, 0xA973,	0x5B62, 0xCC55, 0x5B63, 0xA975, 0x5B64, 0xA974, 0x5B65, 0xCC56,
+	0x5B69, 0xABC4, 0x5B6B, 0xAE5D, 0x5B6C, 0xD165, 0x5B6E, 0xD4F0,	0x5B70, 0xB145, 0x5B71, 0xB447, 0x5B72, 0xD4EF, 0x5B73, 0xB446,
+	0x5B75, 0xB9E5, 0x5B77, 0xE17D, 0x5B78, 0xBEC7, 0x5B7A, 0xC0A9,	0x5B7B, 0xECD7, 0x5B7D, 0xC45E, 0x5B7F, 0xC570, 0x5B81, 0xC972,
+	0x5B83, 0xA5A6, 0x5B84, 0xC973, 0x5B85, 0xA676, 0x5B87, 0xA674,	0x5B88, 0xA675, 0x5B89, 0xA677, 0x5B8B, 0xA7BA, 0x5B8C, 0xA7B9,
+	0x5B8E, 0xCABC, 0x5B8F, 0xA7BB, 0x5B92, 0xCABD, 0x5B93, 0xCC57,	0x5B95, 0xCC58, 0x5B97, 0xA976, 0x5B98, 0xA978, 0x5B99, 0xA97A,
+	0x5B9A, 0xA977, 0x5B9B, 0xA97B, 0x5B9C, 0xA979, 0x5BA2, 0xABC8,	0x5BA3, 0xABC5, 0x5BA4, 0xABC7, 0x5BA5, 0xABC9, 0x5BA6, 0xABC6,
+	0x5BA7, 0xD166, 0x5BA8, 0xCE77, 0x5BAC, 0xD168, 0x5BAD, 0xD167,	0x5BAE, 0xAE63, 0x5BB0, 0xAE5F, 0x5BB3, 0xAE60, 0x5BB4, 0xAE62,
+	0x5BB5, 0xAE64, 0x5BB6, 0xAE61, 0x5BB8, 0xAE66, 0x5BB9, 0xAE65,	0x5BBF, 0xB14A, 0x5BC0, 0xD4F2, 0x5BC1, 0xD4F1, 0x5BC2, 0xB149,
+	0x5BC4, 0xB148, 0x5BC5, 0xB147, 0x5BC6, 0xB14B, 0x5BC7, 0xB146,	0x5BCA, 0xD8D5, 0x5BCB, 0xD8D2, 0x5BCC, 0xB449, 0x5BCD, 0xD8D1,
+	0x5BCE, 0xD8D6, 0x5BD0, 0xB44B, 0x5BD1, 0xD8D4, 0x5BD2, 0xB448,	0x5BD3, 0xB44A, 0x5BD4, 0xD8D3, 0x5BD6, 0xDD48, 0x5BD8, 0xDD49,
+	0x5BD9, 0xDD4A, 0x5BDE, 0xB9E6, 0x5BDF, 0xB9EE, 0x5BE0, 0xE17E,	0x5BE1, 0xB9E8, 0x5BE2, 0xB9EC, 0x5BE3, 0xE1A1, 0x5BE4, 0xB9ED,
+	0x5BE5, 0xB9E9, 0x5BE6, 0xB9EA, 0x5BE7, 0xB9E7, 0x5BE8, 0xB9EB,	0x5BE9, 0xBC66, 0x5BEA, 0xD8D0, 0x5BEB, 0xBC67, 0x5BEC, 0xBC65,
+	0x5BEE, 0xBC64, 0x5BEF, 0xE95D, 0x5BF0, 0xBEC8, 0x5BF1, 0xECD8,	0x5BF2, 0xECD9, 0x5BF5, 0xC364, 0x5BF6, 0xC45F, 0x5BF8, 0xA46F,
+	0x5BFA, 0xA678, 0x5C01, 0xABCA, 0x5C03, 0xD169, 0x5C04, 0xAE67,	0x5C07, 0xB14E, 0x5C08, 0xB14D, 0x5C09, 0xB14C, 0x5C0A, 0xB44C,
+	0x5C0B, 0xB44D, 0x5C0C, 0xD8D7, 0x5C0D, 0xB9EF, 0x5C0E, 0xBEC9,	0x5C0F, 0xA470, 0x5C10, 0xC95C, 0x5C11, 0xA4D6, 0x5C12, 0xC974,
+	0x5C15, 0xC9D4, 0x5C16, 0xA679, 0x5C1A, 0xA97C, 0x5C1F, 0xDD4B,	0x5C22, 0xA471, 0x5C24, 0xA4D7, 0x5C25, 0xC9D5, 0x5C28, 0xCABE,
+	0x5C2A, 0xCABF, 0x5C2C, 0xA7BC, 0x5C30, 0xD8D8, 0x5C31, 0xB44E,	0x5C33, 0xDD4C, 0x5C37, 0xC0AA, 0x5C38, 0xA472, 0x5C39, 0xA4A8,
+	0x5C3A, 0xA4D8, 0x5C3B, 0xC975, 0x5C3C, 0xA5A7, 0x5C3E, 0xA7C0,	0x5C3F, 0xA7BF, 0x5C40, 0xA7BD, 0x5C41, 0xA7BE, 0x5C44, 0xCC59,
+	0x5C45, 0xA97E, 0x5C46, 0xA9A1, 0x5C47, 0xCC5A, 0x5C48, 0xA97D,	0x5C4B, 0xABCE, 0x5C4C, 0xCE78, 0x5C4D, 0xABCD, 0x5C4E, 0xABCB,
+	0x5C4F, 0xABCC, 0x5C50, 0xAE6A, 0x5C51, 0xAE68, 0x5C54, 0xD16B,	0x5C55, 0xAE69, 0x5C56, 0xD16A, 0x5C58, 0xAE5E, 0x5C59, 0xD4F3,
+	0x5C5C, 0xB150, 0x5C5D, 0xB151, 0x5C60, 0xB14F, 0x5C62, 0xB9F0,	0x5C63, 0xE1A2, 0x5C64, 0xBC68, 0x5C65, 0xBC69, 0x5C67, 0xE561,
+	0x5C68, 0xC0AB, 0x5C69, 0xEFC2, 0x5C6A, 0xEFC3, 0x5C6C, 0xC4DD,	0x5C6D, 0xF8A8, 0x5C6E, 0xC94B, 0x5C6F, 0xA4D9, 0x5C71, 0xA473,
+	0x5C73, 0xC977, 0x5C74, 0xC976, 0x5C79, 0xA67A, 0x5C7A, 0xC9D7,	0x5C7B, 0xC9D8, 0x5C7C, 0xC9D6, 0x5C7E, 0xC9D9, 0x5C86, 0xCAC7,
+	0x5C88, 0xCAC2, 0x5C89, 0xCAC4, 0x5C8A, 0xCAC6, 0x5C8B, 0xCAC3,	0x5C8C, 0xA7C4, 0x5C8D, 0xCAC0, 0x5C8F, 0xCAC1, 0x5C90, 0xA7C1,
+	0x5C91, 0xA7C2, 0x5C92, 0xCAC5, 0x5C93, 0xCAC8, 0x5C94, 0xA7C3,	0x5C95, 0xCAC9, 0x5C9D, 0xCC68, 0x5C9F, 0xCC62, 0x5CA0, 0xCC5D,
+	0x5CA1, 0xA9A3, 0x5CA2, 0xCC65, 0x5CA3, 0xCC63, 0x5CA4, 0xCC5C,	0x5CA5, 0xCC69, 0x5CA6, 0xCC6C, 0x5CA7, 0xCC67, 0x5CA8, 0xCC60,
+	0x5CA9, 0xA9A5, 0x5CAA, 0xCC66, 0x5CAB, 0xA9A6, 0x5CAC, 0xCC61,	0x5CAD, 0xCC64, 0x5CAE, 0xCC5B, 0x5CAF, 0xCC5F, 0x5CB0, 0xCC6B,
+	0x5CB1, 0xA9A7, 0x5CB3, 0xA9A8, 0x5CB5, 0xCC5E, 0x5CB6, 0xCC6A,	0x5CB7, 0xA9A2, 0x5CB8, 0xA9A4, 0x5CC6, 0xCEAB, 0x5CC7, 0xCEA4,
+	0x5CC8, 0xCEAA, 0x5CC9, 0xCEA3, 0x5CCA, 0xCEA5, 0x5CCB, 0xCE7D,	0x5CCC, 0xCE7B, 0x5CCE, 0xCEAC, 0x5CCF, 0xCEA9, 0x5CD0, 0xCE79,
+	0x5CD2, 0xABD0, 0x5CD3, 0xCEA7, 0x5CD4, 0xCEA8, 0x5CD6, 0xCEA6,	0x5CD7, 0xCE7C, 0x5CD8, 0xCE7A, 0x5CD9, 0xABCF, 0x5CDA, 0xCEA2,
+	0x5CDB, 0xCE7E, 0x5CDE, 0xCEA1, 0x5CDF, 0xCEAD, 0x5CE8, 0xAE6F,	0x5CEA, 0xAE6E, 0x5CEC, 0xD16C, 0x5CED, 0xAE6B, 0x5CEE, 0xD16E,
+	0x5CF0, 0xAE70, 0x5CF1, 0xD16F, 0x5CF4, 0xAE73, 0x5CF6, 0xAE71,	0x5CF7, 0xD170, 0x5CF8, 0xCEAE, 0x5CF9, 0xD172, 0x5CFB, 0xAE6D,
+	0x5CFD, 0xAE6C, 0x5CFF, 0xD16D, 0x5D00, 0xD171, 0x5D01, 0xAE72,	0x5D06, 0xB153, 0x5D07, 0xB152, 0x5D0B, 0xD4F5, 0x5D0C, 0xD4F9,
+	0x5D0D, 0xD4FB, 0x5D0E, 0xB154, 0x5D0F, 0xD4FE, 0x5D11, 0xB158,	0x5D12, 0xD541, 0x5D14, 0xB15A, 0x5D16, 0xB156, 0x5D17, 0xB15E,
+	0x5D19, 0xB15B, 0x5D1A, 0xD4F7, 0x5D1B, 0xB155, 0x5D1D, 0xD4F6,	0x5D1E, 0xD4F4, 0x5D1F, 0xD543, 0x5D20, 0xD4F8, 0x5D22, 0xB157,
+	0x5D23, 0xD542, 0x5D24, 0xB15C, 0x5D25, 0xD4FD, 0x5D26, 0xD4FC,	0x5D27, 0xB15D, 0x5D28, 0xD4FA, 0x5D29, 0xB159, 0x5D2E, 0xD544,
+	0x5D30, 0xD540, 0x5D31, 0xD8E7, 0x5D32, 0xD8EE, 0x5D33, 0xD8E3,	0x5D34, 0xB451, 0x5D35, 0xD8DF, 0x5D36, 0xD8EF, 0x5D37, 0xD8D9,
+	0x5D38, 0xD8EC, 0x5D39, 0xD8EA, 0x5D3A, 0xD8E4, 0x5D3C, 0xD8ED,	0x5D3D, 0xD8E6, 0x5D3F, 0xD8DE, 0x5D40, 0xD8F0, 0x5D41, 0xD8DC,
+	0x5D42, 0xD8E9, 0x5D43, 0xD8DA, 0x5D45, 0xD8F1, 0x5D47, 0xB452,	0x5D49, 0xD8EB, 0x5D4A, 0xDD4F, 0x5D4B, 0xD8DD, 0x5D4C, 0xB44F,
+	0x5D4E, 0xD8E1, 0x5D50, 0xB450, 0x5D51, 0xD8E0, 0x5D52, 0xD8E5,	0x5D55, 0xD8E2, 0x5D59, 0xD8E8, 0x5D5E, 0xDD53, 0x5D62, 0xDD56,
+	0x5D63, 0xDD4E, 0x5D65, 0xDD50, 0x5D67, 0xDD55, 0x5D68, 0xDD54,	0x5D69, 0xB743, 0x5D6B, 0xD8DB, 0x5D6C, 0xDD52, 0x5D6F, 0xB744,
+	0x5D71, 0xDD4D, 0x5D72, 0xDD51, 0x5D77, 0xE1A9, 0x5D79, 0xE1B0,	0x5D7A, 0xE1A7, 0x5D7C, 0xE1AE, 0x5D7D, 0xE1A5, 0x5D7E, 0xE1AD,
+	0x5D7F, 0xE1B1, 0x5D80, 0xE1A4, 0x5D81, 0xE1A8, 0x5D82, 0xE1A3,	0x5D84, 0xB9F1, 0x5D86, 0xE1A6, 0x5D87, 0xB9F2, 0x5D88, 0xE1AC,
+	0x5D89, 0xE1AB, 0x5D8A, 0xE1AA, 0x5D8D, 0xE1AF, 0x5D92, 0xE565,	0x5D93, 0xE567, 0x5D94, 0xBC6B, 0x5D95, 0xE568, 0x5D97, 0xE563,
+	0x5D99, 0xE562, 0x5D9A, 0xE56C, 0x5D9C, 0xE56A, 0x5D9D, 0xBC6A,	0x5D9E, 0xE56D, 0x5D9F, 0xE564, 0x5DA0, 0xE569, 0x5DA1, 0xE56B,
+	0x5DA2, 0xE566, 0x5DA7, 0xE961, 0x5DA8, 0xE966, 0x5DA9, 0xE960,	0x5DAA, 0xE965, 0x5DAC, 0xE95E, 0x5DAD, 0xE968, 0x5DAE, 0xE964,
+	0x5DAF, 0xE969, 0x5DB0, 0xE963, 0x5DB1, 0xE95F, 0x5DB2, 0xE967,	0x5DB4, 0xE96A, 0x5DB5, 0xE962, 0x5DB7, 0xECDA, 0x5DB8, 0xC0AF,
+	0x5DBA, 0xC0AD, 0x5DBC, 0xC0AC, 0x5DBD, 0xC0AE, 0x5DC0, 0xEFC4,	0x5DC2, 0xF172, 0x5DC3, 0xF1FD, 0x5DC6, 0xF444, 0x5DC7, 0xF445,
+	0x5DC9, 0xC460, 0x5DCB, 0xF5C9, 0x5DCD, 0xC4DE, 0x5DCF, 0xF5CA,	0x5DD1, 0xF6DE, 0x5DD2, 0xC572, 0x5DD4, 0xC571, 0x5DD5, 0xF6DD,
+	0x5DD6, 0xC5C9, 0x5DD8, 0xF7D6, 0x5DDD, 0xA474, 0x5DDE, 0xA67B,	0x5DDF, 0xC9DA, 0x5DE0, 0xCACA, 0x5DE1, 0xA8B5, 0x5DE2, 0xB15F,
+	0x5DE5, 0xA475, 0x5DE6, 0xA5AA, 0x5DE7, 0xA5A9, 0x5DE8, 0xA5A8,	0x5DEB, 0xA7C5, 0x5DEE, 0xAE74, 0x5DF0, 0xDD57, 0x5DF1, 0xA476,
+	0x5DF2, 0xA477, 0x5DF3, 0xA478, 0x5DF4, 0xA4DA, 0x5DF7, 0xABD1,	0x5DF9, 0xCEAF, 0x5DFD, 0xB453, 0x5DFE, 0xA479, 0x5DFF, 0xC95D,
+	0x5E02, 0xA5AB, 0x5E03, 0xA5AC, 0x5E04, 0xC978, 0x5E06, 0xA67C,	0x5E0A, 0xCACB, 0x5E0C, 0xA7C6, 0x5E0E, 0xCACC, 0x5E11, 0xA9AE,
+	0x5E14, 0xCC6E, 0x5E15, 0xA9AC, 0x5E16, 0xA9AB, 0x5E17, 0xCC6D,	0x5E18, 0xA9A9, 0x5E19, 0xCC6F, 0x5E1A, 0xA9AA, 0x5E1B, 0xA9AD,
+	0x5E1D, 0xABD2, 0x5E1F, 0xABD4, 0x5E20, 0xCEB3, 0x5E21, 0xCEB0,	0x5E22, 0xCEB1, 0x5E23, 0xCEB2, 0x5E24, 0xCEB4, 0x5E25, 0xABD3,
+	0x5E28, 0xD174, 0x5E29, 0xD173, 0x5E2B, 0xAE76, 0x5E2D, 0xAE75,	0x5E33, 0xB162, 0x5E34, 0xD546, 0x5E36, 0xB161, 0x5E37, 0xB163,
+	0x5E38, 0xB160, 0x5E3D, 0xB455, 0x5E3E, 0xD545, 0x5E40, 0xB456,	0x5E41, 0xD8F3, 0x5E43, 0xB457, 0x5E44, 0xD8F2, 0x5E45, 0xB454,
+	0x5E4A, 0xDD5A, 0x5E4B, 0xDD5C, 0x5E4C, 0xB745, 0x5E4D, 0xDD5B,	0x5E4E, 0xDD59, 0x5E4F, 0xDD58, 0x5E53, 0xE1B4, 0x5E54, 0xB9F7,
+	0x5E55, 0xB9F5, 0x5E57, 0xB9F6, 0x5E58, 0xE1B2, 0x5E59, 0xE1B3,	0x5E5B, 0xB9F3, 0x5E5C, 0xE571, 0x5E5D, 0xE56F, 0x5E5F, 0xBC6D,
+	0x5E60, 0xE570, 0x5E61, 0xBC6E, 0x5E62, 0xBC6C, 0x5E63, 0xB9F4,	0x5E66, 0xE96D, 0x5E67, 0xE96B, 0x5E68, 0xE96C, 0x5E69, 0xE56E,
+	0x5E6A, 0xECDC, 0x5E6B, 0xC0B0, 0x5E6C, 0xECDB, 0x5E6D, 0xEFC5,	0x5E6E, 0xEFC6, 0x5E6F, 0xE96E, 0x5E70, 0xF1FE, 0x5E72, 0xA47A,
+	0x5E73, 0xA5AD, 0x5E74, 0xA67E, 0x5E75, 0xC9DB, 0x5E76, 0xA67D,	0x5E78, 0xA9AF, 0x5E79, 0xB746, 0x5E7B, 0xA4DB, 0x5E7C, 0xA5AE,
+	0x5E7D, 0xABD5, 0x5E7E, 0xB458, 0x5E80, 0xC979, 0x5E82, 0xC97A,	0x5E84, 0xC9DC, 0x5E87, 0xA7C8, 0x5E88, 0xCAD0, 0x5E89, 0xCACE,
+	0x5E8A, 0xA7C9, 0x5E8B, 0xCACD, 0x5E8C, 0xCACF, 0x5E8D, 0xCAD1,	0x5E8F, 0xA7C7, 0x5E95, 0xA9B3, 0x5E96, 0xA9B4, 0x5E97, 0xA9B1,
+	0x5E9A, 0xA9B0, 0x5E9B, 0xCEB8, 0x5E9C, 0xA9B2, 0x5EA0, 0xABD6,	0x5EA2, 0xCEB7, 0x5EA3, 0xCEB9, 0x5EA4, 0xCEB6, 0x5EA5, 0xCEBA,
+	0x5EA6, 0xABD7, 0x5EA7, 0xAE79, 0x5EA8, 0xD175, 0x5EAA, 0xD177,	0x5EAB, 0xAE77, 0x5EAC, 0xD178, 0x5EAD, 0xAE78, 0x5EAE, 0xD176,
+	0x5EB0, 0xCEB5, 0x5EB1, 0xD547, 0x5EB2, 0xD54A, 0x5EB3, 0xD54B,	0x5EB4, 0xD548, 0x5EB5, 0xB167, 0x5EB6, 0xB166, 0x5EB7, 0xB164,
+	0x5EB8, 0xB165, 0x5EB9, 0xD549, 0x5EBE, 0xB168, 0x5EC1, 0xB45A,	0x5EC2, 0xB45B, 0x5EC4, 0xB45C, 0x5EC5, 0xDD5D, 0x5EC6, 0xDD5F,
+	0x5EC7, 0xDD61, 0x5EC8, 0xB748, 0x5EC9, 0xB747, 0x5ECA, 0xB459,	0x5ECB, 0xDD60, 0x5ECC, 0xDD5E, 0x5ECE, 0xE1B8, 0x5ED1, 0xE1B6,
+	0x5ED2, 0xE1BC, 0x5ED3, 0xB9F8, 0x5ED4, 0xE1BD, 0x5ED5, 0xE1BA,	0x5ED6, 0xB9F9, 0x5ED7, 0xE1B7, 0x5ED8, 0xE1B5, 0x5ED9, 0xE1BB,
+	0x5EDA, 0xBC70, 0x5EDB, 0xE573, 0x5EDC, 0xE1B9, 0x5EDD, 0xBC72,	0x5EDE, 0xE574, 0x5EDF, 0xBC71, 0x5EE0, 0xBC74, 0x5EE1, 0xE575,
+	0x5EE2, 0xBC6F, 0x5EE3, 0xBC73, 0x5EE5, 0xE973, 0x5EE6, 0xE971,	0x5EE7, 0xE970, 0x5EE8, 0xE972, 0x5EE9, 0xE96F, 0x5EEC, 0xC366,
+	0x5EEE, 0xF446, 0x5EEF, 0xF447, 0x5EF1, 0xF5CB, 0x5EF2, 0xF6DF,	0x5EF3, 0xC655, 0x5EF6, 0xA9B5, 0x5EF7, 0xA7CA, 0x5EFA, 0xABD8,
+	0x5EFE, 0xA47B, 0x5EFF, 0xA4DC, 0x5F01, 0xA5AF, 0x5F02, 0xC9DD,	0x5F04, 0xA7CB, 0x5F05, 0xCAD2, 0x5F07, 0xCEBB, 0x5F08, 0xABD9,
+	0x5F0A, 0xB9FA, 0x5F0B, 0xA47C, 0x5F0F, 0xA6A1, 0x5F12, 0xB749,	0x5F13, 0xA47D, 0x5F14, 0xA4DD, 0x5F15, 0xA4DE, 0x5F17, 0xA5B1,
+	0x5F18, 0xA5B0, 0x5F1A, 0xC9DE, 0x5F1B, 0xA6A2, 0x5F1D, 0xCAD3,	0x5F1F, 0xA7CC, 0x5F22, 0xCC71, 0x5F23, 0xCC72, 0x5F24, 0xCC73,
+	0x5F26, 0xA9B6, 0x5F27, 0xA9B7, 0x5F28, 0xCC70, 0x5F29, 0xA9B8,	0x5F2D, 0xABDA, 0x5F2E, 0xCEBC, 0x5F30, 0xD17A, 0x5F31, 0xAE7A,
+	0x5F33, 0xD179, 0x5F35, 0xB169, 0x5F36, 0xD54C, 0x5F37, 0xB16A,	0x5F38, 0xD54D, 0x5F3C, 0xB45D, 0x5F40, 0xDD62, 0x5F43, 0xE1BF,
+	0x5F44, 0xE1BE, 0x5F46, 0xB9FB, 0x5F48, 0xBC75, 0x5F49, 0xE576,	0x5F4A, 0xBECA, 0x5F4B, 0xE974, 0x5F4C, 0xC0B1, 0x5F4E, 0xC573,
+	0x5F4F, 0xF7D8, 0x5F54, 0xCC74, 0x5F56, 0xCEBD, 0x5F57, 0xB16B,	0x5F58, 0xD8F4, 0x5F59, 0xB74A, 0x5F5D, 0xC255, 0x5F62, 0xA7CE,
+	0x5F64, 0xA7CD, 0x5F65, 0xABDB, 0x5F67, 0xD17B, 0x5F69, 0xB16D,	0x5F6A, 0xB343, 0x5F6B, 0xB16E, 0x5F6C, 0xB16C, 0x5F6D, 0xB45E,
+	0x5F6F, 0xE1C0, 0x5F70, 0xB9FC, 0x5F71, 0xBC76, 0x5F73, 0xC94C,	0x5F74, 0xC9DF, 0x5F76, 0xCAD5, 0x5F77, 0xA7CF, 0x5F78, 0xCAD4,
+	0x5F79, 0xA7D0, 0x5F7C, 0xA9BC, 0x5F7D, 0xCC77, 0x5F7E, 0xCC76,	0x5F7F, 0xA9BB, 0x5F80, 0xA9B9, 0x5F81, 0xA9BA, 0x5F82, 0xCC75,
+	0x5F85, 0xABDD, 0x5F86, 0xCEBE, 0x5F87, 0xABE0, 0x5F88, 0xABDC,	0x5F89, 0xABE2, 0x5F8A, 0xABDE, 0x5F8B, 0xABDF, 0x5F8C, 0xABE1,
+	0x5F90, 0xAE7D, 0x5F91, 0xAE7C, 0x5F92, 0xAE7B, 0x5F96, 0xD54F,	0x5F97, 0xB16F, 0x5F98, 0xB172, 0x5F99, 0xB170, 0x5F9B, 0xD54E,
+	0x5F9C, 0xB175, 0x5F9E, 0xB171, 0x5F9F, 0xD550, 0x5FA0, 0xB174,	0x5FA1, 0xB173, 0x5FA5, 0xD8F6, 0x5FA6, 0xD8F5, 0x5FA8, 0xB461,
+	0x5FA9, 0xB45F, 0x5FAA, 0xB460, 0x5FAB, 0xD8F7, 0x5FAC, 0xB74B,	0x5FAD, 0xDD64, 0x5FAE, 0xB74C, 0x5FAF, 0xDD63, 0x5FB2, 0xE577,
+	0x5FB5, 0xBC78, 0x5FB6, 0xE1C1, 0x5FB7, 0xBC77, 0x5FB9, 0xB9FD,	0x5FBB, 0xECDE, 0x5FBC, 0xE975, 0x5FBD, 0xC0B2, 0x5FBE, 0xECDD,
+	0x5FBF, 0xF240, 0x5FC0, 0xF448, 0x5FC1, 0xF449, 0x5FC3, 0xA4DF,	0x5FC5, 0xA5B2, 0x5FC9, 0xC97B, 0x5FCC, 0xA7D2, 0x5FCD, 0xA7D4,
+	0x5FCF, 0xC9E2, 0x5FD0, 0xCAD8, 0x5FD1, 0xCAD7, 0x5FD2, 0xCAD6,	0x5FD4, 0xC9E1, 0x5FD5, 0xC9E0, 0x5FD6, 0xA6A4, 0x5FD7, 0xA7D3,
+	0x5FD8, 0xA7D1, 0x5FD9, 0xA6A3, 0x5FDD, 0xA9BD, 0x5FDE, 0xCC78,	0x5FE0, 0xA9BE, 0x5FE1, 0xCADD, 0x5FE3, 0xCADF, 0x5FE4, 0xCADE,
+	0x5FE5, 0xCC79, 0x5FE8, 0xCADA, 0x5FEA, 0xA7D8, 0x5FEB, 0xA7D6,	0x5FED, 0xCAD9, 0x5FEE, 0xCADB, 0x5FEF, 0xCAE1, 0x5FF1, 0xA7D5,
+	0x5FF3, 0xCADC, 0x5FF4, 0xCAE5, 0x5FF5, 0xA9C0, 0x5FF7, 0xCAE2,	0x5FF8, 0xA7D7, 0x5FFA, 0xCAE0, 0x5FFB, 0xCAE3, 0x5FFD, 0xA9BF,
+	0x5FFF, 0xA9C1, 0x6000, 0xCAE4, 0x6009, 0xCCAF, 0x600A, 0xCCA2,	0x600B, 0xCC7E, 0x600C, 0xCCAE, 0x600D, 0xCCA9, 0x600E, 0xABE7,
+	0x600F, 0xA9C2, 0x6010, 0xCCAA, 0x6011, 0xCCAD, 0x6012, 0xABE3,	0x6013, 0xCCAC, 0x6014, 0xA9C3, 0x6015, 0xA9C8, 0x6016, 0xA9C6,
+	0x6017, 0xCCA3, 0x6019, 0xCC7C, 0x601A, 0xCCA5, 0x601B, 0xA9CD,	0x601C, 0xCCB0, 0x601D, 0xABE4, 0x601E, 0xCCA6, 0x6020, 0xABE5,
+	0x6021, 0xA9C9, 0x6022, 0xCCA8, 0x6024, 0xCECD, 0x6025, 0xABE6,	0x6026, 0xCC7B, 0x6027, 0xA9CA, 0x6028, 0xABE8, 0x6029, 0xA9CB,
+	0x602A, 0xA9C7, 0x602B, 0xA9CC, 0x602C, 0xCCA7, 0x602D, 0xCC7A,	0x602E, 0xCCAB, 0x602F, 0xA9C4, 0x6032, 0xCC7D, 0x6033, 0xCCA4,
+	0x6034, 0xCCA1, 0x6035, 0xA9C5, 0x6037, 0xCEBF, 0x6039, 0xCEC0,	0x6040, 0xCECA, 0x6041, 0xD1A1, 0x6042, 0xCECB, 0x6043, 0xABEE,
+	0x6044, 0xCECE, 0x6045, 0xCEC4, 0x6046, 0xABED, 0x6047, 0xCEC6,	0x6049, 0xCEC7, 0x604C, 0xCEC9, 0x604D, 0xABE9, 0x6050, 0xAEA3,
+	0x6052, 0xF9DA, 0x6053, 0xCEC5, 0x6054, 0xCEC1, 0x6055, 0xAEA4,	0x6058, 0xCECF, 0x6059, 0xAE7E, 0x605A, 0xD17D, 0x605B, 0xCEC8,
+	0x605D, 0xD17C, 0x605E, 0xCEC3, 0x605F, 0xCECC, 0x6062, 0xABEC,	0x6063, 0xAEA1, 0x6064, 0xABF2, 0x6065, 0xAEA2, 0x6066, 0xCED0,
+	0x6067, 0xD17E, 0x6068, 0xABEB, 0x6069, 0xAEA6, 0x606A, 0xABF1,	0x606B, 0xABF0, 0x606C, 0xABEF, 0x606D, 0xAEA5, 0x606E, 0xCED1,
+	0x606F, 0xAEA7, 0x6070, 0xABEA, 0x6072, 0xCEC2, 0x607F, 0xB176,	0x6080, 0xD1A4, 0x6081, 0xD1A6, 0x6083, 0xD1A8, 0x6084, 0xAEA8,
+	0x6085, 0xAEAE, 0x6086, 0xD553, 0x6087, 0xD1AC, 0x6088, 0xD1A3,	0x6089, 0xB178, 0x608A, 0xD551, 0x608C, 0xAEAD, 0x608D, 0xAEAB,
+	0x608E, 0xD1AE, 0x6090, 0xD552, 0x6092, 0xD1A5, 0x6094, 0xAEAC,	0x6095, 0xD1A9, 0x6096, 0xAEAF, 0x6097, 0xD1AB, 0x609A, 0xAEAA,
+	0x609B, 0xD1AA, 0x609C, 0xD1AD, 0x609D, 0xD1A7, 0x609F, 0xAEA9,	0x60A0, 0xB179, 0x60A2, 0xD1A2, 0x60A3, 0xB177, 0x60A8, 0xB17A,
+	0x60B0, 0xD555, 0x60B1, 0xD55E, 0x60B2, 0xB464, 0x60B4, 0xB17C,	0x60B5, 0xB1A3, 0x60B6, 0xB465, 0x60B7, 0xD560, 0x60B8, 0xB1AA,
+	0x60B9, 0xD8F9, 0x60BA, 0xD556, 0x60BB, 0xB1A2, 0x60BC, 0xB1A5,	0x60BD, 0xB17E, 0x60BE, 0xD554, 0x60BF, 0xD562, 0x60C0, 0xD565,
+	0x60C1, 0xD949, 0x60C3, 0xD563, 0x60C4, 0xD8FD, 0x60C5, 0xB1A1,	0x60C6, 0xB1A8, 0x60C7, 0xB1AC, 0x60C8, 0xD55D, 0x60C9, 0xD8F8,
+	0x60CA, 0xD561, 0x60CB, 0xB17B, 0x60CC, 0xD8FA, 0x60CD, 0xD564,	0x60CE, 0xD8FC, 0x60CF, 0xD559, 0x60D1, 0xB462, 0x60D3, 0xD557,
+	0x60D4, 0xD558, 0x60D5, 0xB1A7, 0x60D8, 0xB1A6, 0x60D9, 0xD55B,	0x60DA, 0xB1AB, 0x60DB, 0xD55F, 0x60DC, 0xB1A4, 0x60DD, 0xD55C,
+	0x60DF, 0xB1A9, 0x60E0, 0xB466, 0x60E1, 0xB463, 0x60E2, 0xD8FB,	0x60E4, 0xD55A, 0x60E6, 0xB17D, 0x60F0, 0xB46B, 0x60F1, 0xB46F,
+	0x60F2, 0xD940, 0x60F3, 0xB751, 0x60F4, 0xB46D, 0x60F5, 0xD944,	0x60F6, 0xB471, 0x60F7, 0xDD65, 0x60F8, 0xD946, 0x60F9, 0xB753,
+	0x60FA, 0xB469, 0x60FB, 0xB46C, 0x60FC, 0xD947, 0x60FE, 0xD948,	0x60FF, 0xD94E, 0x6100, 0xB473, 0x6101, 0xB754, 0x6103, 0xD94A,
+	0x6104, 0xD94F, 0x6105, 0xD943, 0x6106, 0xB75E, 0x6108, 0xB755,	0x6109, 0xB472, 0x610A, 0xD941, 0x610B, 0xD950, 0x610D, 0xB75D,
+	0x610E, 0xB470, 0x610F, 0xB74E, 0x6110, 0xD94D, 0x6112, 0xB474,	0x6113, 0xD945, 0x6114, 0xD8FE, 0x6115, 0xB46A, 0x6116, 0xD942,
+	0x6118, 0xD94B, 0x611A, 0xB74D, 0x611B, 0xB752, 0x611C, 0xB467,	0x611D, 0xD94C, 0x611F, 0xB750, 0x6123, 0xB468, 0x6127, 0xB75C,
+	0x6128, 0xE1C3, 0x6129, 0xDD70, 0x612B, 0xDD68, 0x612C, 0xE1C2,	0x612E, 0xDD6C, 0x612F, 0xDD6E, 0x6132, 0xDD6B, 0x6134, 0xB75B,
+	0x6136, 0xDD6A, 0x6137, 0xB75F, 0x613B, 0xE1D2, 0x613E, 0xB75A,	0x613F, 0xBA40, 0x6140, 0xDD71, 0x6141, 0xE1C4, 0x6144, 0xB758,
+	0x6145, 0xDD69, 0x6146, 0xDD6D, 0x6147, 0xB9FE, 0x6148, 0xB74F,	0x6149, 0xDD66, 0x614A, 0xDD67, 0x614B, 0xBA41, 0x614C, 0xB757,
+	0x614D, 0xB759, 0x614E, 0xB756, 0x614F, 0xDD6F, 0x6152, 0xE1C8,	0x6153, 0xE1C9, 0x6154, 0xE1CE, 0x6155, 0xBC7D, 0x6156, 0xE1D5,
+	0x6158, 0xBA47, 0x615A, 0xBA46, 0x615B, 0xE1D0, 0x615D, 0xBC7C,	0x615E, 0xE1C5, 0x615F, 0xBA45, 0x6161, 0xE1D4, 0x6162, 0xBA43,
+	0x6163, 0xBA44, 0x6165, 0xE1D1, 0x6166, 0xE5AA, 0x6167, 0xBC7A,	0x6168, 0xB46E, 0x616A, 0xE1D3, 0x616B, 0xBCA3, 0x616C, 0xE1CB,
+	0x616E, 0xBC7B, 0x6170, 0xBCA2, 0x6171, 0xE1C6, 0x6172, 0xE1CA,	0x6173, 0xE1C7, 0x6174, 0xE1CD, 0x6175, 0xBA48, 0x6176, 0xBC79,
+	0x6177, 0xBA42, 0x6179, 0xE57A, 0x617A, 0xE1CF, 0x617C, 0xBCA1,	0x617E, 0xBCA4, 0x6180, 0xE1CC, 0x6182, 0xBC7E, 0x6183, 0xE579,
+	0x6189, 0xE57E, 0x618A, 0xBECE, 0x618B, 0xE578, 0x618C, 0xE9A3,	0x618D, 0xE5A9, 0x618E, 0xBCA8, 0x6190, 0xBCA6, 0x6191, 0xBECC,
+	0x6192, 0xE5A6, 0x6193, 0xE5A2, 0x6194, 0xBCAC, 0x6196, 0xE978,	0x619A, 0xBCAA, 0x619B, 0xE5A1, 0x619D, 0xE976, 0x619F, 0xE5A5,
+	0x61A1, 0xE5A8, 0x61A2, 0xE57D, 0x61A4, 0xBCAB, 0x61A7, 0xBCA5,	0x61A8, 0xE977, 0x61A9, 0xBECD, 0x61AA, 0xE5A7, 0x61AB, 0xBCA7,
+	0x61AC, 0xBCA9, 0x61AD, 0xE5A4, 0x61AE, 0xBCAD, 0x61AF, 0xE5A3,	0x61B0, 0xE57C, 0x61B1, 0xE57B, 0x61B2, 0xBECB, 0x61B3, 0xE5AB,
+	0x61B4, 0xE97A, 0x61B5, 0xECE0, 0x61B6, 0xBED0, 0x61B8, 0xE9A2,	0x61BA, 0xE97E, 0x61BC, 0xECE1, 0x61BE, 0xBED1, 0x61BF, 0xE9A1,
+	0x61C1, 0xE97C, 0x61C2, 0xC0B4, 0x61C3, 0xECDF, 0x61C5, 0xE979,	0x61C6, 0xE97B, 0x61C7, 0xC0B5, 0x61C8, 0xBED3, 0x61C9, 0xC0B3,
+	0x61CA, 0xBED2, 0x61CB, 0xC0B7, 0x61CC, 0xE97D, 0x61CD, 0xBECF,	0x61D6, 0xEFCF, 0x61D8, 0xEFC7, 0x61DE, 0xECE7, 0x61DF, 0xEFC8,
+	0x61E0, 0xECE3, 0x61E3, 0xC256, 0x61E4, 0xECE5, 0x61E5, 0xECE4,	0x61E6, 0xC0B6, 0x61E7, 0xECE2, 0x61E8, 0xECE6, 0x61E9, 0xEFD0,
+	0x61EA, 0xEFCC, 0x61EB, 0xEFCE, 0x61ED, 0xEFC9, 0x61EE, 0xEFCA,	0x61F0, 0xEFCD, 0x61F1, 0xEFCB, 0x61F2, 0xC367, 0x61F5, 0xC36A,
+	0x61F6, 0xC369, 0x61F7, 0xC368, 0x61F8, 0xC461, 0x61F9, 0xF44A,	0x61FA, 0xC462, 0x61FB, 0xF241, 0x61FC, 0xC4DF, 0x61FD, 0xF5CC,
+	0x61FE, 0xC4E0, 0x61FF, 0xC574, 0x6200, 0xC5CA, 0x6201, 0xF7D9,	0x6203, 0xF7DA, 0x6204, 0xF7DB, 0x6207, 0xF9BA, 0x6208, 0xA4E0,
+	0x6209, 0xC97C, 0x620A, 0xA5B3, 0x620C, 0xA6A6, 0x620D, 0xA6A7,	0x620E, 0xA6A5, 0x6210, 0xA6A8, 0x6211, 0xA7DA, 0x6212, 0xA7D9,
+	0x6214, 0xCCB1, 0x6215, 0xA9CF, 0x6216, 0xA9CE, 0x6219, 0xD1AF,	0x621A, 0xB1AD, 0x621B, 0xB1AE, 0x621F, 0xB475, 0x6220, 0xDD72,
+	0x6221, 0xB760, 0x6222, 0xB761, 0x6223, 0xDD74, 0x6224, 0xDD76,	0x6225, 0xDD75, 0x6227, 0xE1D7, 0x6229, 0xE1D6, 0x622A, 0xBA49,
+	0x622B, 0xE1D8, 0x622D, 0xE5AC, 0x622E, 0xBCAE, 0x6230, 0xBED4,	0x6232, 0xC0B8, 0x6233, 0xC257, 0x6234, 0xC0B9, 0x6236, 0xA4E1,
+	0x623A, 0xCAE6, 0x623D, 0xCCB2, 0x623E, 0xA9D1, 0x623F, 0xA9D0,	0x6240, 0xA9D2, 0x6241, 0xABF3, 0x6242, 0xCED2, 0x6243, 0xCED3,
+	0x6246, 0xD1B0, 0x6247, 0xAEB0, 0x6248, 0xB1AF, 0x6249, 0xB476,	0x624A, 0xD951, 0x624B, 0xA4E2, 0x624D, 0xA47E, 0x624E, 0xA4E3,
+	0x6250, 0xC97D, 0x6251, 0xA5B7, 0x6252, 0xA5B6, 0x6253, 0xA5B4,	0x6254, 0xA5B5, 0x6258, 0xA6AB, 0x6259, 0xC9E9, 0x625A, 0xC9EB,
+	0x625B, 0xA6AA, 0x625C, 0xC9E3, 0x625E, 0xC9E4, 0x6260, 0xC9EA,	0x6261, 0xC9E6, 0x6262, 0xC9E8, 0x6263, 0xA6A9, 0x6264, 0xC9E5,
+	0x6265, 0xC9EC, 0x6266, 0xC9E7, 0x626D, 0xA7E1, 0x626E, 0xA7EA,	0x626F, 0xA7E8, 0x6270, 0xCAF0, 0x6271, 0xCAED, 0x6272, 0xCAF5,
+	0x6273, 0xA7E6, 0x6274, 0xCAF6, 0x6276, 0xA7DF, 0x6277, 0xCAF3,	0x6279, 0xA7E5, 0x627A, 0xCAEF, 0x627B, 0xCAEE, 0x627C, 0xA7E3,
+	0x627D, 0xCAF4, 0x627E, 0xA7E4, 0x627F, 0xA9D3, 0x6280, 0xA7DE,	0x6281, 0xCAF1, 0x6283, 0xCAE7, 0x6284, 0xA7DB, 0x6286, 0xA7EE,
+	0x6287, 0xCAEC, 0x6288, 0xCAF2, 0x6289, 0xA7E0, 0x628A, 0xA7E2,	0x628C, 0xCAE8, 0x628E, 0xCAE9, 0x628F, 0xCAEA, 0x6291, 0xA7ED,
+	0x6292, 0xA7E7, 0x6293, 0xA7EC, 0x6294, 0xCAEB, 0x6295, 0xA7EB,	0x6296, 0xA7DD, 0x6297, 0xA7DC, 0x6298, 0xA7E9, 0x62A8, 0xA9E1,
+	0x62A9, 0xCCBE, 0x62AA, 0xCCB7, 0x62AB, 0xA9DC, 0x62AC, 0xA9EF,	0x62AD, 0xCCB3, 0x62AE, 0xCCBA, 0x62AF, 0xCCBC, 0x62B0, 0xCCBF,
+	0x62B1, 0xA9EA, 0x62B3, 0xCCBB, 0x62B4, 0xCCB4, 0x62B5, 0xA9E8,	0x62B6, 0xCCB8, 0x62B8, 0xCCC0, 0x62B9, 0xA9D9, 0x62BB, 0xCCBD,
+	0x62BC, 0xA9E3, 0x62BD, 0xA9E2, 0x62BE, 0xCCB6, 0x62BF, 0xA9D7,	0x62C2, 0xA9D8, 0x62C4, 0xA9D6, 0x62C6, 0xA9EE, 0x62C7, 0xA9E6,
+	0x62C8, 0xA9E0, 0x62C9, 0xA9D4, 0x62CA, 0xCCB9, 0x62CB, 0xA9DF,	0x62CC, 0xA9D5, 0x62CD, 0xA9E7, 0x62CE, 0xA9F0, 0x62CF, 0xCED4,
+	0x62D0, 0xA9E4, 0x62D1, 0xCCB5, 0x62D2, 0xA9DA, 0x62D3, 0xA9DD,	0x62D4, 0xA9DE, 0x62D6, 0xA9EC, 0x62D7, 0xA9ED, 0x62D8, 0xA9EB,
+	0x62D9, 0xA9E5, 0x62DA, 0xA9E9, 0x62DB, 0xA9DB, 0x62DC, 0xABF4,	0x62EB, 0xCEDA, 0x62EC, 0xAC41, 0x62ED, 0xABF8, 0x62EE, 0xABFA,
+	0x62EF, 0xAC40, 0x62F0, 0xCEE6, 0x62F1, 0xABFD, 0x62F2, 0xD1B1,	0x62F3, 0xAEB1, 0x62F4, 0xAC43, 0x62F5, 0xCED7, 0x62F6, 0xCEDF,
+	0x62F7, 0xABFE, 0x62F8, 0xCEDE, 0x62F9, 0xCEDB, 0x62FA, 0xCEE3,	0x62FB, 0xCEE5, 0x62FC, 0xABF7, 0x62FD, 0xABFB, 0x62FE, 0xAC42,
+	0x62FF, 0xAEB3, 0x6300, 0xCEE0, 0x6301, 0xABF9, 0x6302, 0xAC45,	0x6303, 0xCED9, 0x6307, 0xABFC, 0x6308, 0xAEB2, 0x6309, 0xABF6,
+	0x630B, 0xCED6, 0x630C, 0xCEDD, 0x630D, 0xCED5, 0x630E, 0xCED8,	0x630F, 0xCEDC, 0x6310, 0xD1B2, 0x6311, 0xAC44, 0x6313, 0xCEE1,
+	0x6314, 0xCEE2, 0x6315, 0xCEE4, 0x6316, 0xABF5, 0x6328, 0xAEC1,	0x6329, 0xD1BE, 0x632A, 0xAEBF, 0x632B, 0xAEC0, 0x632C, 0xD1B4,
+	0x632D, 0xD1C4, 0x632F, 0xAEB6, 0x6332, 0xD566, 0x6333, 0xD1C6,	0x6334, 0xD1C0, 0x6336, 0xD1B7, 0x6338, 0xD1C9, 0x6339, 0xD1BA,
+	0x633A, 0xAEBC, 0x633B, 0xD57D, 0x633C, 0xD1BD, 0x633D, 0xAEBE,	0x633E, 0xAEB5, 0x6340, 0xD1CB, 0x6341, 0xD1BF, 0x6342, 0xAEB8,
+	0x6343, 0xD1B8, 0x6344, 0xD1B5, 0x6345, 0xD1B6, 0x6346, 0xAEB9,	0x6347, 0xD1C5, 0x6348, 0xD1CC, 0x6349, 0xAEBB, 0x634A, 0xD1BC,
+	0x634B, 0xD1BB, 0x634C, 0xAEC3, 0x634D, 0xAEC2, 0x634E, 0xAEB4,	0x634F, 0xAEBA, 0x6350, 0xAEBD, 0x6351, 0xD1C8, 0x6354, 0xD1C2,
+	0x6355, 0xAEB7, 0x6356, 0xD1B3, 0x6357, 0xD1CA, 0x6358, 0xD1C1,	0x6359, 0xD1C3, 0x635A, 0xD1C7, 0x6365, 0xD567, 0x6367, 0xB1B7,
+	0x6368, 0xB1CB, 0x6369, 0xB1CA, 0x636B, 0xB1BF, 0x636D, 0xD579,	0x636E, 0xD575, 0x636F, 0xD572, 0x6370, 0xD5A6, 0x6371, 0xB1BA,
+	0x6372, 0xB1B2, 0x6375, 0xD577, 0x6376, 0xB4A8, 0x6377, 0xB1B6,	0x6378, 0xD5A1, 0x637A, 0xB1CC, 0x637B, 0xB1C9, 0x637C, 0xD57B,
+	0x637D, 0xD56A, 0x6380, 0xB1C8, 0x6381, 0xD5A3, 0x6382, 0xD569,	0x6383, 0xB1BD, 0x6384, 0xB1C1, 0x6385, 0xD5A2, 0x6387, 0xD573,
+	0x6388, 0xB1C2, 0x6389, 0xB1BC, 0x638A, 0xD568, 0x638C, 0xB478,	0x638D, 0xD5A5, 0x638E, 0xD571, 0x638F, 0xB1C7, 0x6390, 0xD574,
+	0x6391, 0xD5A4, 0x6392, 0xB1C6, 0x6394, 0xD952, 0x6396, 0xB1B3,	0x6397, 0xD56F, 0x6398, 0xB1B8, 0x6399, 0xB1C3, 0x639B, 0xB1BE,
+	0x639C, 0xD578, 0x639D, 0xD56E, 0x639E, 0xD56C, 0x639F, 0xD57E,	0x63A0, 0xB1B0, 0x63A1, 0xB1C4, 0x63A2, 0xB1B4, 0x63A3, 0xB477,
+	0x63A4, 0xD57C, 0x63A5, 0xB1B5, 0x63A7, 0xB1B1, 0x63A8, 0xB1C0,	0x63A9, 0xB1BB, 0x63AA, 0xB1B9, 0x63AB, 0xD570, 0x63AC, 0xB1C5,
+	0x63AD, 0xD56D, 0x63AE, 0xD57A, 0x63AF, 0xD576, 0x63B0, 0xD954,	0x63B1, 0xD953, 0x63BD, 0xD56B, 0x63BE, 0xD964, 0x63C0, 0xB47A,
+	0x63C2, 0xD96A, 0x63C3, 0xD959, 0x63C4, 0xD967, 0x63C5, 0xDD77,	0x63C6, 0xB47D, 0x63C7, 0xD96B, 0x63C8, 0xD96E, 0x63C9, 0xB47C,
+	0x63CA, 0xD95C, 0x63CB, 0xD96D, 0x63CC, 0xD96C, 0x63CD, 0xB47E,	0x63CE, 0xD955, 0x63CF, 0xB479, 0x63D0, 0xB4A3, 0x63D2, 0xB4A1,
+	0x63D3, 0xD969, 0x63D5, 0xD95F, 0x63D6, 0xB4A5, 0x63D7, 0xD970,	0x63D8, 0xD968, 0x63D9, 0xD971, 0x63DA, 0xB4AD, 0x63DB, 0xB4AB,
+	0x63DC, 0xD966, 0x63DD, 0xD965, 0x63DF, 0xD963, 0x63E0, 0xD95D,	0x63E1, 0xB4A4, 0x63E3, 0xB4A2, 0x63E4, 0xD1B9, 0x63E5, 0xD956,
+	0x63E7, 0xDDB7, 0x63E8, 0xD957, 0x63E9, 0xB47B, 0x63EA, 0xB4AA,	0x63EB, 0xDD79, 0x63ED, 0xB4A6, 0x63EE, 0xB4A7, 0x63EF, 0xD958,
+	0x63F0, 0xD96F, 0x63F1, 0xDD78, 0x63F2, 0xD960, 0x63F3, 0xD95B,	0x63F4, 0xB4A9, 0x63F5, 0xD961, 0x63F6, 0xD95E, 0x63F9, 0xB4AE,
+	0x6406, 0xB770, 0x6409, 0xDD7C, 0x640A, 0xDDB1, 0x640B, 0xDDB6,	0x640C, 0xDDAA, 0x640D, 0xB76C, 0x640E, 0xDDBB, 0x640F, 0xB769,
+	0x6410, 0xDD7A, 0x6412, 0xDD7B, 0x6413, 0xB762, 0x6414, 0xB76B,	0x6415, 0xDDA4, 0x6416, 0xB76E, 0x6417, 0xB76F, 0x6418, 0xDDA5,
+	0x641A, 0xDDB2, 0x641B, 0xDDB8, 0x641C, 0xB76A, 0x641E, 0xB764,	0x641F, 0xDDA3, 0x6420, 0xDD7D, 0x6421, 0xDDBA, 0x6422, 0xDDA8,
+	0x6423, 0xDDA9, 0x6424, 0xDD7E, 0x6425, 0xDDB4, 0x6426, 0xDDAB,	0x6427, 0xDDB5, 0x6428, 0xDDAD, 0x642A, 0xB765, 0x642B, 0xE1D9,
+	0x642C, 0xB768, 0x642D, 0xB766, 0x642E, 0xDDB9, 0x642F, 0xDDB0,	0x6430, 0xDDAC, 0x6433, 0xDDA1, 0x6434, 0xBA53, 0x6435, 0xDDAF,
+	0x6436, 0xB76D, 0x6437, 0xDDA7, 0x6439, 0xDDA6, 0x643D, 0xB767,	0x643E, 0xB763, 0x643F, 0xE1EE, 0x6440, 0xDDB3, 0x6441, 0xDDAE,
+	0x6443, 0xDDA2, 0x644B, 0xE1E9, 0x644D, 0xE1DA, 0x644E, 0xE1E5,	0x6450, 0xE1EC, 0x6451, 0xBA51, 0x6452, 0xB4AC, 0x6453, 0xE1EA,
+	0x6454, 0xBA4C, 0x6458, 0xBA4B, 0x6459, 0xE1F1, 0x645B, 0xE1DB,	0x645C, 0xE1E8, 0x645D, 0xE1DC, 0x645E, 0xE1E7, 0x645F, 0xBA4F,
+	0x6460, 0xE1EB, 0x6461, 0xD962, 0x6465, 0xE1F2, 0x6466, 0xE1E3,	0x6467, 0xBA52, 0x6468, 0xE5BA, 0x6469, 0xBCAF, 0x646B, 0xE1F0,
+	0x646C, 0xE1EF, 0x646D, 0xBA54, 0x646E, 0xE5AD, 0x646F, 0xBCB0,	0x6470, 0xE5AE, 0x6472, 0xE1DF, 0x6473, 0xE1E0, 0x6474, 0xE1DD,
+	0x6475, 0xE1E2, 0x6476, 0xE1DE, 0x6477, 0xE1F3, 0x6478, 0xBA4E,	0x6479, 0xBCB1, 0x647A, 0xBA50, 0x647B, 0xBA55, 0x647D, 0xE1E1,
+	0x647F, 0xE1ED, 0x6482, 0xE1E6, 0x6485, 0xE5B1, 0x6487, 0xBA4A,	0x6488, 0xBCB4, 0x6489, 0xE9AA, 0x648A, 0xE5B6, 0x648B, 0xE5B5,
+	0x648C, 0xE5B7, 0x648F, 0xE5B4, 0x6490, 0xBCB5, 0x6492, 0xBCBB,	0x6493, 0xBCB8, 0x6495, 0xBCB9, 0x6496, 0xE5AF, 0x6497, 0xE5B2,
+	0x6498, 0xE5BC, 0x6499, 0xBCC1, 0x649A, 0xBCBF, 0x649C, 0xE5B3,	0x649D, 0xD95A, 0x649E, 0xBCB2, 0x649F, 0xE5B9, 0x64A0, 0xE5B0,
+	0x64A2, 0xBCC2, 0x64A3, 0xE5B8, 0x64A4, 0xBA4D, 0x64A5, 0xBCB7,	0x64A6, 0xE1E4, 0x64A9, 0xBCBA, 0x64AB, 0xBCBE, 0x64AC, 0xBCC0,
+	0x64AD, 0xBCBD, 0x64AE, 0xBCBC, 0x64B0, 0xBCB6, 0x64B1, 0xE5BB,	0x64B2, 0xBCB3, 0x64B3, 0xBCC3, 0x64BB, 0xBED8, 0x64BC, 0xBED9,
+	0x64BD, 0xE9A9, 0x64BE, 0xBEE2, 0x64BF, 0xBEDF, 0x64C1, 0xBED6,	0x64C2, 0xBEDD, 0x64C3, 0xE9AB, 0x64C4, 0xBEDB, 0x64C5, 0xBED5,
+	0x64C7, 0xBEDC, 0x64C9, 0xE9A8, 0x64CA, 0xC0BB, 0x64CB, 0xBED7,	0x64CD, 0xBEDE, 0x64CE, 0xC0BA, 0x64CF, 0xE9A7, 0x64D0, 0xE9A6,
+	0x64D2, 0xBEE0, 0x64D4, 0xBEE1, 0x64D6, 0xE9A5, 0x64D7, 0xE9A4,	0x64D8, 0xC0BC, 0x64D9, 0xE9AE, 0x64DA, 0xBEDA, 0x64DB, 0xE9AC,
+	0x64E0, 0xC0BD, 0x64E2, 0xC0C2, 0x64E3, 0xECEA, 0x64E4, 0xECEC,	0x64E6, 0xC0BF, 0x64E8, 0xECED, 0x64E9, 0xECE9, 0x64EB, 0xECEB,
+	0x64EC, 0xC0C0, 0x64ED, 0xC0C3, 0x64EF, 0xECE8, 0x64F0, 0xC0BE,	0x64F1, 0xC0C1, 0x64F2, 0xC259, 0x64F3, 0xE9AD, 0x64F4, 0xC258,
+	0x64F7, 0xC25E, 0x64F8, 0xEFD4, 0x64FA, 0xC25C, 0x64FB, 0xC25D,	0x64FC, 0xEFD7, 0x64FD, 0xEFD3, 0x64FE, 0xC25A, 0x64FF, 0xEFD1,
+	0x6500, 0xC36B, 0x6501, 0xEFD5, 0x6503, 0xEFD6, 0x6504, 0xEFD2,	0x6506, 0xC25B, 0x6507, 0xF242, 0x6509, 0xF245, 0x650C, 0xF246,
+	0x650D, 0xF244, 0x650E, 0xF247, 0x650F, 0xC36C, 0x6510, 0xF243,	0x6513, 0xF44E, 0x6514, 0xC464, 0x6515, 0xF44D, 0x6516, 0xF44C,
+	0x6517, 0xF44B, 0x6518, 0xC463, 0x6519, 0xC465, 0x651B, 0xF5CD,	0x651C, 0xC4E2, 0x651D, 0xC4E1, 0x6520, 0xF6E1, 0x6521, 0xF6E0,
+	0x6522, 0xF6E3, 0x6523, 0xC5CB, 0x6524, 0xC575, 0x6525, 0xF7DD,	0x6526, 0xF6E2, 0x6529, 0xF7DC, 0x652A, 0xC5CD, 0x652B, 0xC5CC,
+	0x652C, 0xC5F3, 0x652D, 0xF8A9, 0x652E, 0xF8EF, 0x652F, 0xA4E4,	0x6532, 0xD972, 0x6533, 0xE9AF, 0x6536, 0xA6AC, 0x6537, 0xCAF7,
+	0x6538, 0xA7F1, 0x6539, 0xA7EF, 0x653B, 0xA7F0, 0x653D, 0xCCC1,	0x653E, 0xA9F1, 0x653F, 0xAC46, 0x6541, 0xCEE7, 0x6543, 0xCEE8,
+	0x6545, 0xAC47, 0x6546, 0xD1CE, 0x6548, 0xAEC4, 0x6549, 0xAEC5,	0x654A, 0xD1CD, 0x654F, 0xB1D3, 0x6551, 0xB1CF, 0x6553, 0xD5A7,
+	0x6554, 0xB1D6, 0x6555, 0xB1D5, 0x6556, 0xB1CE, 0x6557, 0xB1D1,	0x6558, 0xB1D4, 0x6559, 0xB1D0, 0x655C, 0xD976, 0x655D, 0xB1CD,
+	0x655E, 0xB4AF, 0x6562, 0xB4B1, 0x6563, 0xB4B2, 0x6564, 0xD975,	0x6565, 0xD978, 0x6566, 0xB4B0, 0x6567, 0xD973, 0x6568, 0xD977,
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+	0x69B5, 0xE260, 0x69B6, 0xE1FD, 0x69B7, 0xBA65, 0x69B9, 0xE253,	0x69BB, 0xBA66, 0x69BC, 0xE245, 0x69BD, 0xE250, 0x69BE, 0xE24C,
+	0x69BF, 0xE24E, 0x69C1, 0xBA60, 0x69C2, 0xE25F, 0x69C3, 0xBA6E,	0x69C4, 0xE24F, 0x69C6, 0xE262, 0x69C9, 0xE1FE, 0x69CA, 0xE254,
+	0x69CB, 0xBA63, 0x69CC, 0xBA6C, 0x69CD, 0xBA6A, 0x69CE, 0xE241,	0x69CF, 0xE256, 0x69D0, 0xBA69, 0x69D3, 0xBA62, 0x69D4, 0xE252,
+	0x69D9, 0xE25C, 0x69E2, 0xE5D5, 0x69E4, 0xE5D1, 0x69E5, 0xE5CD,	0x69E6, 0xE5E1, 0x69E7, 0xE5DE, 0x69E8, 0xBCCD, 0x69EB, 0xE5E5,
+	0x69EC, 0xE5D4, 0x69ED, 0xBCD8, 0x69EE, 0xE5DB, 0x69F1, 0xE5D0,	0x69F2, 0xE5DA, 0x69F3, 0xBCD5, 0x69F4, 0xE5EE, 0x69F6, 0xE5EB,
+	0x69F7, 0xE5DD, 0x69F8, 0xE5CE, 0x69FB, 0xE5E2, 0x69FC, 0xE5E4,	0x69FD, 0xBCD1, 0x69FE, 0xE5D8, 0x69FF, 0xE5D3, 0x6A00, 0xE5CA,
+	0x6A01, 0xBCCE, 0x6A02, 0xBCD6, 0x6A04, 0xE5E7, 0x6A05, 0xBCD7,	0x6A06, 0xE5CB, 0x6A07, 0xE5ED, 0x6A08, 0xE5E0, 0x6A09, 0xE5E6,
+	0x6A0A, 0xBCD4, 0x6A0D, 0xE5E3, 0x6A0F, 0xE5EA, 0x6A11, 0xBCD9,	0x6A13, 0xBCD3, 0x6A14, 0xE5DC, 0x6A15, 0xE5CF, 0x6A16, 0xE5EF,
+	0x6A17, 0xE5CC, 0x6A18, 0xE5E8, 0x6A19, 0xBCD0, 0x6A1B, 0xE5D6,	0x6A1D, 0xE5D7, 0x6A1E, 0xBCCF, 0x6A1F, 0xBCCC, 0x6A20, 0xE5D2,
+	0x6A21, 0xBCD2, 0x6A23, 0xBCCB, 0x6A25, 0xE5E9, 0x6A26, 0xE5EC,	0x6A27, 0xE5D9, 0x6A28, 0xE9CA, 0x6A32, 0xE9C2, 0x6A34, 0xE9BE,
+	0x6A35, 0xBEF6, 0x6A38, 0xBEEB, 0x6A39, 0xBEF0, 0x6A3A, 0xBEEC,	0x6A3B, 0xE9CC, 0x6A3C, 0xE9D7, 0x6A3D, 0xBEEA, 0x6A3E, 0xE9C4,
+	0x6A3F, 0xE9CD, 0x6A40, 0xE5DF, 0x6A41, 0xE9CE, 0x6A44, 0xBEF1,	0x6A46, 0xE9DD, 0x6A47, 0xBEF5, 0x6A48, 0xBEF8, 0x6A49, 0xE9C0,
+	0x6A4B, 0xBEF4, 0x6A4D, 0xE9DB, 0x6A4E, 0xE9DC, 0x6A4F, 0xE9D2,	0x6A50, 0xE9D1, 0x6A51, 0xE9C9, 0x6A54, 0xE9D3, 0x6A55, 0xE9DA,
+	0x6A56, 0xE9D9, 0x6A58, 0xBEEF, 0x6A59, 0xBEED, 0x6A5A, 0xE9CB,	0x6A5B, 0xE9C8, 0x6A5D, 0xE9C5, 0x6A5E, 0xE9D8, 0x6A5F, 0xBEF7,
+	0x6A60, 0xE9D6, 0x6A61, 0xBEF3, 0x6A62, 0xBEF2, 0x6A64, 0xE9D0,	0x6A66, 0xE9BF, 0x6A67, 0xE9C1, 0x6A68, 0xE9C3, 0x6A69, 0xE9D5,
+	0x6A6A, 0xE9CF, 0x6A6B, 0xBEEE, 0x6A6D, 0xE9C6, 0x6A6F, 0xE9D4,	0x6A76, 0xE9C7, 0x6A7E, 0xC0CF, 0x6A7F, 0xED45, 0x6A80, 0xC0C8,
+	0x6A81, 0xECF5, 0x6A83, 0xED41, 0x6A84, 0xC0CA, 0x6A85, 0xED48,	0x6A87, 0xECFC, 0x6A89, 0xECF7, 0x6A8C, 0xED49, 0x6A8D, 0xECF3,
+	0x6A8E, 0xECFE, 0x6A90, 0xC0D1, 0x6A91, 0xED44, 0x6A92, 0xED4A,	0x6A93, 0xECFD, 0x6A94, 0xC0C9, 0x6A95, 0xED40, 0x6A96, 0xECF4,
+	0x6A97, 0xC0D0, 0x6A9A, 0xED47, 0x6A9B, 0xECF9, 0x6A9C, 0xC0CC,	0x6A9E, 0xECFB, 0x6A9F, 0xECF8, 0x6AA0, 0xC0D2, 0x6AA1, 0xECFA,
+	0x6AA2, 0xC0CB, 0x6AA3, 0xC0CE, 0x6AA4, 0xED43, 0x6AA5, 0xECF6,	0x6AA6, 0xED46, 0x6AA8, 0xED42, 0x6AAC, 0xC263, 0x6AAD, 0xEFE7,
+	0x6AAE, 0xC268, 0x6AAF, 0xC269, 0x6AB3, 0xC262, 0x6AB4, 0xEFE6,	0x6AB6, 0xEFE3, 0x6AB7, 0xEFE4, 0x6AB8, 0xC266, 0x6AB9, 0xEFDE,
+	0x6ABA, 0xEFE2, 0x6ABB, 0xC265, 0x6ABD, 0xEFDF, 0x6AC2, 0xC267,	0x6AC3, 0xC264, 0x6AC5, 0xEFDD, 0x6AC6, 0xEFE1, 0x6AC7, 0xEFE5,
+	0x6ACB, 0xF251, 0x6ACC, 0xF24E, 0x6ACD, 0xF257, 0x6ACF, 0xF256,	0x6AD0, 0xF254, 0x6AD1, 0xF24F, 0x6AD3, 0xC372, 0x6AD9, 0xF250,
+	0x6ADA, 0xC371, 0x6ADB, 0xC0CD, 0x6ADC, 0xF253, 0x6ADD, 0xC370,	0x6ADE, 0xF258, 0x6ADF, 0xF252, 0x6AE0, 0xF24D, 0x6AE1, 0xEFE0,
+	0x6AE5, 0xC36F, 0x6AE7, 0xF24C, 0x6AE8, 0xF456, 0x6AEA, 0xF455,	0x6AEB, 0xF255, 0x6AEC, 0xC468, 0x6AEE, 0xF459, 0x6AEF, 0xF45A,
+	0x6AF0, 0xF454, 0x6AF1, 0xF458, 0x6AF3, 0xF453, 0x6AF8, 0xF5D1,	0x6AF9, 0xF457, 0x6AFA, 0xC4E7, 0x6AFB, 0xC4E5, 0x6AFC, 0xF5CF,
+	0x6B00, 0xF5D2, 0x6B02, 0xF5CE, 0x6B03, 0xF5D0, 0x6B04, 0xC4E6,	0x6B08, 0xF6E5, 0x6B09, 0xF6E6, 0x6B0A, 0xC576, 0x6B0B, 0xF6E4,
+	0x6B0F, 0xF7E2, 0x6B10, 0xC5CF, 0x6B11, 0xF7E0, 0x6B12, 0xF7E1,	0x6B13, 0xF8AC, 0x6B16, 0xC656, 0x6B17, 0xF8F3, 0x6B18, 0xF8F1,
+	0x6B19, 0xF8F2, 0x6B1A, 0xF8F4, 0x6B1E, 0xF9BB, 0x6B20, 0xA4ED,	0x6B21, 0xA6B8, 0x6B23, 0xAA59, 0x6B25, 0xCCE9, 0x6B28, 0xCF64,
+	0x6B2C, 0xD1F5, 0x6B2D, 0xD1F7, 0x6B2F, 0xD1F6, 0x6B31, 0xD1F8,	0x6B32, 0xB1FD, 0x6B33, 0xD5D7, 0x6B34, 0xD1F9, 0x6B36, 0xD5D6,
+	0x6B37, 0xD5D8, 0x6B38, 0xD5D9, 0x6B39, 0xD9DA, 0x6B3A, 0xB4DB,	0x6B3B, 0xD9DB, 0x6B3C, 0xD9DD, 0x6B3D, 0xB4DC, 0x6B3E, 0xB4DA,
+	0x6B3F, 0xD9DC, 0x6B41, 0xDDFA, 0x6B42, 0xDDF8, 0x6B43, 0xDDF7,	0x6B45, 0xDDF6, 0x6B46, 0xDDF5, 0x6B47, 0xB7B2, 0x6B48, 0xDDF9,
+	0x6B49, 0xBA70, 0x6B4A, 0xE263, 0x6B4B, 0xE265, 0x6B4C, 0xBA71,	0x6B4D, 0xE264, 0x6B4E, 0xBCDB, 0x6B50, 0xBCDA, 0x6B51, 0xE5F0,
+	0x6B54, 0xE9DF, 0x6B55, 0xE9DE, 0x6B56, 0xE9E0, 0x6B59, 0xBEF9,	0x6B5B, 0xED4B, 0x6B5C, 0xC0D3, 0x6B5E, 0xEFE8, 0x6B5F, 0xC26A,
+	0x6B60, 0xF259, 0x6B61, 0xC577, 0x6B62, 0xA4EE, 0x6B63, 0xA5BF,	0x6B64, 0xA6B9, 0x6B65, 0xA842, 0x6B66, 0xAA5A, 0x6B67, 0xAA5B,
+	0x6B6A, 0xAC6E, 0x6B6D, 0xD1FA, 0x6B72, 0xB7B3, 0x6B76, 0xE6D1,	0x6B77, 0xBEFA, 0x6B78, 0xC26B, 0x6B79, 0xA4EF, 0x6B7B, 0xA6BA,
+	0x6B7E, 0xCCEB, 0x6B7F, 0xAA5C, 0x6B80, 0xCCEA, 0x6B82, 0xCF65,	0x6B83, 0xAC6F, 0x6B84, 0xCF66, 0x6B86, 0xAC70, 0x6B88, 0xD1FC,
+	0x6B89, 0xAEEE, 0x6B8A, 0xAEED, 0x6B8C, 0xD5DE, 0x6B8D, 0xD5DC,	0x6B8E, 0xD5DD, 0x6B8F, 0xD5DB, 0x6B91, 0xD5DA, 0x6B94, 0xD9DE,
+	0x6B95, 0xD9E1, 0x6B96, 0xB4DE, 0x6B97, 0xD9DF, 0x6B98, 0xB4DD,	0x6B99, 0xD9E0, 0x6B9B, 0xDDFB, 0x6B9E, 0xE266, 0x6B9F, 0xE267,
+	0x6BA0, 0xE268, 0x6BA2, 0xE5F3, 0x6BA3, 0xE5F2, 0x6BA4, 0xBCDC,	0x6BA5, 0xE5F1, 0x6BA6, 0xE5F4, 0x6BA7, 0xE9E1, 0x6BAA, 0xE9E2,
+	0x6BAB, 0xE9E3, 0x6BAD, 0xED4C, 0x6BAE, 0xC0D4, 0x6BAF, 0xC26C,	0x6BB0, 0xF25A, 0x6BB2, 0xC4E8, 0x6BB3, 0xC95F, 0x6BB5, 0xAC71,
+	0x6BB6, 0xCF67, 0x6BB7, 0xAEEF, 0x6BBA, 0xB1FE, 0x6BBC, 0xB4DF,	0x6BBD, 0xD9E2, 0x6BBF, 0xB7B5, 0x6BC0, 0xB7B4, 0x6BC3, 0xE269,
+	0x6BC4, 0xE26A, 0x6BC5, 0xBCDD, 0x6BC6, 0xBCDE, 0x6BC7, 0xE9E5,	0x6BC8, 0xE9E4, 0x6BC9, 0xEFE9, 0x6BCA, 0xF7E3, 0x6BCB, 0xA4F0,
+	0x6BCC, 0xC960, 0x6BCD, 0xA5C0, 0x6BCF, 0xA843, 0x6BD0, 0xCB48,	0x6BD2, 0xAC72, 0x6BD3, 0xB7B6, 0x6BD4, 0xA4F1, 0x6BD6, 0xCF68,
+	0x6BD7, 0xAC73, 0x6BD8, 0xCF69, 0x6BDA, 0xC0D5, 0x6BDB, 0xA4F2,	0x6BDE, 0xCCEC, 0x6BE0, 0xCF6A, 0x6BE2, 0xD242, 0x6BE3, 0xD241,
+	0x6BE4, 0xD1FE, 0x6BE6, 0xD1FD, 0x6BE7, 0xD243, 0x6BE8, 0xD240,	0x6BEB, 0xB240, 0x6BEC, 0xB241, 0x6BEF, 0xB4E0, 0x6BF0, 0xD9E3,
+	0x6BF2, 0xD9E4, 0x6BF3, 0xD9E5, 0x6BF7, 0xDE41, 0x6BF8, 0xDE42,	0x6BF9, 0xDE40, 0x6BFB, 0xDDFD, 0x6BFC, 0xDDFE, 0x6BFD, 0xB7B7,
+	0x6BFE, 0xE26B, 0x6BFF, 0xE5F7, 0x6C00, 0xE5F6, 0x6C01, 0xE5F5,	0x6C02, 0xE5F8, 0x6C03, 0xE9E7, 0x6C04, 0xE9E6, 0x6C05, 0xBEFB,
+	0x6C06, 0xE9E8, 0x6C08, 0xC0D6, 0x6C09, 0xED4D, 0x6C0B, 0xEFEA,	0x6C0C, 0xF25B, 0x6C0D, 0xF6E7, 0x6C0F, 0xA4F3, 0x6C10, 0xA5C2,
+	0x6C11, 0xA5C1, 0x6C13, 0xAA5D, 0x6C14, 0xC961, 0x6C15, 0xC97E,	0x6C16, 0xA6BB, 0x6C18, 0xC9F7, 0x6C19, 0xCB49, 0x6C1A, 0xCB4A,
+	0x6C1B, 0xAA5E, 0x6C1D, 0xCCED, 0x6C1F, 0xAC74, 0x6C20, 0xCF6B,	0x6C21, 0xCF6C, 0x6C23, 0xAEF0, 0x6C24, 0xAEF4, 0x6C25, 0xD244,
+	0x6C26, 0xAEF3, 0x6C27, 0xAEF1, 0x6C28, 0xAEF2, 0x6C2A, 0xD5DF,	0x6C2B, 0xB242, 0x6C2C, 0xB4E3, 0x6C2E, 0xB4E1, 0x6C2F, 0xB4E2,
+	0x6C30, 0xD9E6, 0x6C33, 0xBA72, 0x6C34, 0xA4F4, 0x6C36, 0xC9A1,	0x6C38, 0xA5C3, 0x6C3B, 0xC9A4, 0x6C3E, 0xA5C6, 0x6C3F, 0xC9A3,
+	0x6C40, 0xA5C5, 0x6C41, 0xA5C4, 0x6C42, 0xA844, 0x6C43, 0xC9A2,	0x6C46, 0xC9F8, 0x6C4A, 0xC9FC, 0x6C4B, 0xC9FE, 0x6C4C, 0xCA40,
+	0x6C4D, 0xA6C5, 0x6C4E, 0xA6C6, 0x6C4F, 0xC9FB, 0x6C50, 0xA6C1,	0x6C52, 0xC9F9, 0x6C54, 0xC9FD, 0x6C55, 0xA6C2, 0x6C57, 0xA6BD,
+	0x6C59, 0xA6BE, 0x6C5B, 0xA6C4, 0x6C5C, 0xC9FA, 0x6C5D, 0xA6BC,	0x6C5E, 0xA845, 0x6C5F, 0xA6BF, 0x6C60, 0xA6C0, 0x6C61, 0xA6C3,
+	0x6C65, 0xCB5B, 0x6C66, 0xCB59, 0x6C67, 0xCB4C, 0x6C68, 0xA851,	0x6C69, 0xCB53, 0x6C6A, 0xA84C, 0x6C6B, 0xCB4D, 0x6C6D, 0xCB55,
+	0x6C6F, 0xCB52, 0x6C70, 0xA84F, 0x6C71, 0xCB51, 0x6C72, 0xA856,	0x6C73, 0xCB5A, 0x6C74, 0xA858, 0x6C76, 0xA85A, 0x6C78, 0xCB4B,
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+	0x6C8C, 0xA850, 0x6C8D, 0xA85B, 0x6C8E, 0xCB5D, 0x6C8F, 0xCB50,	0x6C90, 0xA84E, 0x6C92, 0xA853, 0x6C93, 0xCCEE, 0x6C94, 0xA85C,
+	0x6C95, 0xCB57, 0x6C96, 0xA852, 0x6C98, 0xA85D, 0x6C99, 0xA846,	0x6C9A, 0xCB54, 0x6C9B, 0xA84B, 0x6C9C, 0xCB58, 0x6C9D, 0xCD44,
+	0x6CAB, 0xAA6A, 0x6CAC, 0xAA7A, 0x6CAD, 0xCCF5, 0x6CAE, 0xAA71,	0x6CB0, 0xCD4B, 0x6CB1, 0xAA62, 0x6CB3, 0xAA65, 0x6CB4, 0xCD42,
+	0x6CB6, 0xCCF3, 0x6CB7, 0xCCF7, 0x6CB8, 0xAA6D, 0x6CB9, 0xAA6F,	0x6CBA, 0xCCFA, 0x6CBB, 0xAA76, 0x6CBC, 0xAA68, 0x6CBD, 0xAA66,
+	0x6CBE, 0xAA67, 0x6CBF, 0xAA75, 0x6CC0, 0xCD47, 0x6CC1, 0xAA70,	0x6CC2, 0xCCF9, 0x6CC3, 0xCCFB, 0x6CC4, 0xAA6E, 0x6CC5, 0xAA73,
+	0x6CC6, 0xCCFC, 0x6CC7, 0xCD4A, 0x6CC9, 0xAC75, 0x6CCA, 0xAA79,	0x6CCC, 0xAA63, 0x6CCD, 0xCD49, 0x6CCF, 0xCD4D, 0x6CD0, 0xCCF8,
+	0x6CD1, 0xCD4F, 0x6CD2, 0xCD40, 0x6CD3, 0xAA6C, 0x6CD4, 0xCCF4,	0x6CD5, 0xAA6B, 0x6CD6, 0xAA7D, 0x6CD7, 0xAA72, 0x6CD9, 0xCCF2,
+	0x6CDA, 0xCF75, 0x6CDB, 0xAA78, 0x6CDC, 0xAA7C, 0x6CDD, 0xCD41,	0x6CDE, 0xCD46, 0x6CE0, 0xAA7E, 0x6CE1, 0xAA77, 0x6CE2, 0xAA69,
+	0x6CE3, 0xAA5F, 0x6CE5, 0xAA64, 0x6CE7, 0xCCF6, 0x6CE8, 0xAA60,	0x6CE9, 0xCD4E, 0x6CEB, 0xCCF0, 0x6CEC, 0xCCEF, 0x6CED, 0xCCFD,
+	0x6CEE, 0xCCF1, 0x6CEF, 0xAA7B, 0x6CF0, 0xAEF5, 0x6CF1, 0xAA74,	0x6CF2, 0xCCFE, 0x6CF3, 0xAA61, 0x6CF5, 0xACA6, 0x6CF9, 0xCD4C,
+	0x6D00, 0xCF7C, 0x6D01, 0xCFA1, 0x6D03, 0xCFA4, 0x6D04, 0xCF77,	0x6D07, 0xCFA7, 0x6D08, 0xCFAA, 0x6D09, 0xCFAC, 0x6D0A, 0xCF74,
+	0x6D0B, 0xAC76, 0x6D0C, 0xAC7B, 0x6D0D, 0xD249, 0x6D0E, 0xACAD,	0x6D0F, 0xCFA5, 0x6D10, 0xCFAD, 0x6D11, 0xCF7B, 0x6D12, 0xCF73,
+	0x6D16, 0xD264, 0x6D17, 0xAC7E, 0x6D18, 0xCFA2, 0x6D19, 0xCF78,	0x6D1A, 0xCF7A, 0x6D1B, 0xACA5, 0x6D1D, 0xCF7D, 0x6D1E, 0xAC7D,
+	0x6D1F, 0xCF70, 0x6D20, 0xCFA8, 0x6D22, 0xCFAB, 0x6D25, 0xAC7A,	0x6D27, 0xACA8, 0x6D28, 0xCF6D, 0x6D29, 0xACAA, 0x6D2A, 0xAC78,
+	0x6D2B, 0xACAE, 0x6D2C, 0xCFA9, 0x6D2D, 0xCF6F, 0x6D2E, 0xACAB,	0x6D2F, 0xD25E, 0x6D30, 0xCD48, 0x6D31, 0xAC7C, 0x6D32, 0xAC77,
+	0x6D33, 0xCF76, 0x6D34, 0xCF6E, 0x6D35, 0xACAC, 0x6D36, 0xACA4,	0x6D37, 0xCFA3, 0x6D38, 0xACA9, 0x6D39, 0xACA7, 0x6D3A, 0xCF79,
+	0x6D3B, 0xACA1, 0x6D3C, 0xCF71, 0x6D3D, 0xACA2, 0x6D3E, 0xACA3,	0x6D3F, 0xCF72, 0x6D40, 0xCFA6, 0x6D41, 0xAC79, 0x6D42, 0xCF7E,
+	0x6D58, 0xD24C, 0x6D59, 0xAEFD, 0x6D5A, 0xAF43, 0x6D5E, 0xD255,	0x6D5F, 0xD25B, 0x6D60, 0xD257, 0x6D61, 0xD24A, 0x6D62, 0xD24D,
+	0x6D63, 0xD246, 0x6D64, 0xD247, 0x6D65, 0xAF4A, 0x6D66, 0xAEFA,	0x6D67, 0xD256, 0x6D68, 0xD25F, 0x6D69, 0xAF45, 0x6D6A, 0xAEF6,
+	0x6D6C, 0xAF40, 0x6D6D, 0xD24E, 0x6D6E, 0xAF42, 0x6D6F, 0xD24F,	0x6D70, 0xD259, 0x6D74, 0xAF44, 0x6D75, 0xD268, 0x6D76, 0xD248,
+	0x6D77, 0xAEFC, 0x6D78, 0xAEFB, 0x6D79, 0xAF48, 0x6D7A, 0xD245,	0x6D7B, 0xD266, 0x6D7C, 0xD25A, 0x6D7D, 0xD267, 0x6D7E, 0xD261,
+	0x6D7F, 0xD253, 0x6D80, 0xD262, 0x6D82, 0xD25C, 0x6D83, 0xD265,	0x6D84, 0xD263, 0x6D85, 0xAF49, 0x6D86, 0xD254, 0x6D87, 0xAEF9,
+	0x6D88, 0xAEF8, 0x6D89, 0xAF41, 0x6D8A, 0xAF47, 0x6D8B, 0xD260,	0x6D8C, 0xAF46, 0x6D8D, 0xD251, 0x6D8E, 0xB243, 0x6D90, 0xD269,
+	0x6D91, 0xD250, 0x6D92, 0xD24B, 0x6D93, 0xAEFE, 0x6D94, 0xAF4B,	0x6D95, 0xAEF7, 0x6D97, 0xD258, 0x6D98, 0xD25D, 0x6DAA, 0xB265,
+	0x6DAB, 0xD5E1, 0x6DAC, 0xD5E5, 0x6DAE, 0xB252, 0x6DAF, 0xB250,	0x6DB2, 0xB247, 0x6DB3, 0xD5E3, 0x6DB4, 0xD5E2, 0x6DB5, 0xB25B,
+	0x6DB7, 0xD5E8, 0x6DB8, 0xB255, 0x6DBA, 0xD5FA, 0x6DBB, 0xD647,	0x6DBC, 0xB244, 0x6DBD, 0xD5F7, 0x6DBE, 0xD5F0, 0x6DBF, 0xB267,
+	0x6DC0, 0xD5E0, 0x6DC2, 0xD5FC, 0x6DC4, 0xB264, 0x6DC5, 0xB258,	0x6DC6, 0xB263, 0x6DC7, 0xB24E, 0x6DC8, 0xD5EC, 0x6DC9, 0xD5FE,
+	0x6DCA, 0xD5F6, 0x6DCB, 0xB24F, 0x6DCC, 0xB249, 0x6DCD, 0xD645,	0x6DCF, 0xD5FD, 0x6DD0, 0xD640, 0x6DD1, 0xB251, 0x6DD2, 0xB259,
+	0x6DD3, 0xD642, 0x6DD4, 0xD5EA, 0x6DD5, 0xD5FB, 0x6DD6, 0xD5EF,	0x6DD7, 0xD644, 0x6DD8, 0xB25E, 0x6DD9, 0xB246, 0x6DDA, 0xB25C,
+	0x6DDB, 0xD5F4, 0x6DDC, 0xD5F2, 0x6DDD, 0xD5F3, 0x6DDE, 0xB253,	0x6DDF, 0xD5EE, 0x6DE0, 0xD5ED, 0x6DE1, 0xB248, 0x6DE2, 0xD5E7,
+	0x6DE3, 0xD646, 0x6DE4, 0xB24A, 0x6DE5, 0xD5F1, 0x6DE6, 0xB268,	0x6DE8, 0xB262, 0x6DE9, 0xD5E6, 0x6DEA, 0xB25F, 0x6DEB, 0xB25D,
+	0x6DEC, 0xB266, 0x6DED, 0xD5F8, 0x6DEE, 0xB261, 0x6DEF, 0xD252,	0x6DF0, 0xD5F9, 0x6DF1, 0xB260, 0x6DF2, 0xD641, 0x6DF3, 0xB245,
+	0x6DF4, 0xD5F5, 0x6DF5, 0xB257, 0x6DF6, 0xD5E9, 0x6DF7, 0xB256,	0x6DF9, 0xB254, 0x6DFA, 0xB24C, 0x6DFB, 0xB24B, 0x6DFC, 0xD9E7,
+	0x6DFD, 0xD643, 0x6E00, 0xD5EB, 0x6E03, 0xD9FC, 0x6E05, 0xB24D,	0x6E19, 0xB541, 0x6E1A, 0xB25A, 0x6E1B, 0xB4EE, 0x6E1C, 0xD9F6,
+	0x6E1D, 0xB4FC, 0x6E1F, 0xD9EA, 0x6E20, 0xB4EB, 0x6E21, 0xB4E7,	0x6E22, 0xDA49, 0x6E23, 0xB4ED, 0x6E24, 0xB4F1, 0x6E25, 0xB4EC,
+	0x6E26, 0xB4F5, 0x6E27, 0xDA4D, 0x6E28, 0xDA44, 0x6E2B, 0xD9F1,	0x6E2C, 0xB4FA, 0x6E2D, 0xB4F4, 0x6E2E, 0xD9FD, 0x6E2F, 0xB4E4,
+	0x6E30, 0xDA4A, 0x6E31, 0xDA43, 0x6E32, 0xB4E8, 0x6E33, 0xD9F7,	0x6E34, 0xB4F7, 0x6E35, 0xDA55, 0x6E36, 0xDA56, 0x6E38, 0xB4E5,
+	0x6E39, 0xDA48, 0x6E3A, 0xB4F9, 0x6E3B, 0xD9FB, 0x6E3C, 0xD9ED,	0x6E3D, 0xD9EE, 0x6E3E, 0xB4FD, 0x6E3F, 0xD9F2, 0x6E40, 0xD9F9,
+	0x6E41, 0xD9F3, 0x6E43, 0xB4FB, 0x6E44, 0xB544, 0x6E45, 0xD9EF,	0x6E46, 0xD9E8, 0x6E47, 0xD9E9, 0x6E49, 0xD9EB, 0x6E4A, 0xB4EA,
+	0x6E4B, 0xD9F8, 0x6E4D, 0xB4F8, 0x6E4E, 0xB542, 0x6E51, 0xD9FA,	0x6E52, 0xDA53, 0x6E53, 0xDA4B, 0x6E54, 0xB4E6, 0x6E55, 0xDA51,
+	0x6E56, 0xB4F2, 0x6E58, 0xB4F0, 0x6E5A, 0xDA57, 0x6E5B, 0xB4EF,	0x6E5C, 0xDA41, 0x6E5D, 0xD9F4, 0x6E5E, 0xD9FE, 0x6E5F, 0xB547,
+	0x6E60, 0xDA45, 0x6E61, 0xDA42, 0x6E62, 0xD9F0, 0x6E63, 0xB543,	0x6E64, 0xDA4F, 0x6E65, 0xDA4C, 0x6E66, 0xDA54, 0x6E67, 0xB4E9,
+	0x6E68, 0xDA40, 0x6E69, 0xB546, 0x6E6B, 0xDA47, 0x6E6E, 0xB4F3,	0x6E6F, 0xB4F6, 0x6E71, 0xDA46, 0x6E72, 0xB545, 0x6E73, 0xD9F5,
+	0x6E74, 0xD5E4, 0x6E77, 0xDA50, 0x6E78, 0xDA4E, 0x6E79, 0xDA52,	0x6E88, 0xD9EC, 0x6E89, 0xB540, 0x6E8D, 0xDE61, 0x6E8E, 0xDE60,
+	0x6E8F, 0xDE46, 0x6E90, 0xB7BD, 0x6E92, 0xDE5F, 0x6E93, 0xDE49,	0x6E94, 0xDE4A, 0x6E96, 0xB7C7, 0x6E97, 0xDE68, 0x6E98, 0xB7C2,
+	0x6E99, 0xDE5E, 0x6E9B, 0xDE43, 0x6E9C, 0xB7C8, 0x6E9D, 0xB7BE,	0x6E9E, 0xDE52, 0x6E9F, 0xDE48, 0x6EA0, 0xDE4B, 0x6EA1, 0xDE63,
+	0x6EA2, 0xB7B8, 0x6EA3, 0xDE6A, 0x6EA4, 0xDE62, 0x6EA5, 0xB7C1,	0x6EA6, 0xDE57, 0x6EA7, 0xB7CC, 0x6EAA, 0xB7CB, 0x6EAB, 0xB7C5,
+	0x6EAE, 0xDE69, 0x6EAF, 0xB7B9, 0x6EB0, 0xDE55, 0x6EB1, 0xDE4C,	0x6EB2, 0xDE59, 0x6EB3, 0xDE65, 0x6EB4, 0xB7CD, 0x6EB6, 0xB7BB,
+	0x6EB7, 0xDE54, 0x6EB9, 0xDE4D, 0x6EBA, 0xB7C4, 0x6EBC, 0xB7C3,	0x6EBD, 0xDE50, 0x6EBE, 0xDE5A, 0x6EBF, 0xDE64, 0x6EC0, 0xDE47,
+	0x6EC1, 0xDE51, 0x6EC2, 0xB7BC, 0x6EC3, 0xDE5B, 0x6EC4, 0xB7C9,	0x6EC5, 0xB7C0, 0x6EC6, 0xDE4E, 0x6EC7, 0xB7BF, 0x6EC8, 0xDE45,
+	0x6EC9, 0xDE53, 0x6ECA, 0xDE67, 0x6ECB, 0xB4FE, 0x6ECC, 0xBAB0,	0x6ECD, 0xDE56, 0x6ECE, 0xE26C, 0x6ECF, 0xDE58, 0x6ED0, 0xDE66,
+	0x6ED1, 0xB7C6, 0x6ED2, 0xDE4F, 0x6ED3, 0xB7BA, 0x6ED4, 0xB7CA,	0x6ED5, 0xBCF0, 0x6ED6, 0xDE44, 0x6ED8, 0xDE5D, 0x6EDC, 0xDE5C,
+	0x6EEB, 0xE2AA, 0x6EEC, 0xBAAD, 0x6EED, 0xE27D, 0x6EEE, 0xE2A4,	0x6EEF, 0xBAA2, 0x6EF1, 0xE26E, 0x6EF2, 0xBAAF, 0x6EF4, 0xBA77,
+	0x6EF5, 0xE26D, 0x6EF6, 0xE2B0, 0x6EF7, 0xBAB1, 0x6EF8, 0xE271,	0x6EF9, 0xE2A3, 0x6EFB, 0xE273, 0x6EFC, 0xE2B3, 0x6EFD, 0xE2AF,
+	0x6EFE, 0xBA75, 0x6EFF, 0xBAA1, 0x6F00, 0xE653, 0x6F01, 0xBAAE,	0x6F02, 0xBA7D, 0x6F03, 0xE26F, 0x6F05, 0xE2AE, 0x6F06, 0xBAA3,
+	0x6F07, 0xE2AB, 0x6F08, 0xE2B8, 0x6F09, 0xE275, 0x6F0A, 0xE27E,	0x6F0D, 0xE2B6, 0x6F0E, 0xE2AC, 0x6F0F, 0xBA7C, 0x6F12, 0xE27C,
+	0x6F13, 0xBA76, 0x6F14, 0xBA74, 0x6F15, 0xBAA8, 0x6F18, 0xE27A,	0x6F19, 0xE277, 0x6F1A, 0xE278, 0x6F1C, 0xE2B2, 0x6F1E, 0xE2B7,
+	0x6F1F, 0xE2B5, 0x6F20, 0xBA7A, 0x6F21, 0xE2B9, 0x6F22, 0xBA7E,	0x6F23, 0xBAA7, 0x6F25, 0xE270, 0x6F26, 0xE5FA, 0x6F27, 0xE279,
+	0x6F29, 0xBA78, 0x6F2A, 0xBAAC, 0x6F2B, 0xBAA9, 0x6F2C, 0xBA7B,	0x6F2D, 0xE2A5, 0x6F2E, 0xE274, 0x6F2F, 0xBAAA, 0x6F30, 0xE2A7,
+	0x6F31, 0xBAA4, 0x6F32, 0xBAA6, 0x6F33, 0xBA73, 0x6F35, 0xE2A9,	0x6F36, 0xE2A1, 0x6F37, 0xE272, 0x6F38, 0xBAA5, 0x6F39, 0xE2B1,
+	0x6F3A, 0xE2B4, 0x6F3B, 0xE27B, 0x6F3C, 0xE2A8, 0x6F3E, 0xBA79,	0x6F3F, 0xBCDF, 0x6F40, 0xE2A6, 0x6F41, 0xE5F9, 0x6F43, 0xE2AD,
+	0x6F4E, 0xE276, 0x6F4F, 0xE644, 0x6F50, 0xE64E, 0x6F51, 0xBCE2,	0x6F52, 0xE64D, 0x6F53, 0xE659, 0x6F54, 0xBCE4, 0x6F55, 0xE64B,
+	0x6F57, 0xE64F, 0x6F58, 0xBCEF, 0x6F5A, 0xE646, 0x6F5B, 0xBCE7,	0x6F5D, 0xE652, 0x6F5E, 0xE9F0, 0x6F5F, 0xBCF3, 0x6F60, 0xBCF2,
+	0x6F61, 0xE654, 0x6F62, 0xE643, 0x6F63, 0xE65E, 0x6F64, 0xBCED,	0x6F66, 0xBCE3, 0x6F67, 0xE657, 0x6F69, 0xE65B, 0x6F6A, 0xE660,
+	0x6F6B, 0xE655, 0x6F6C, 0xE649, 0x6F6D, 0xBCE6, 0x6F6E, 0xBCE9,	0x6F6F, 0xBCF1, 0x6F70, 0xBCEC, 0x6F72, 0xE64C, 0x6F73, 0xE2A2,
+	0x6F76, 0xE648, 0x6F77, 0xE65F, 0x6F78, 0xBCE8, 0x6F7A, 0xBCEB,	0x6F7B, 0xE661, 0x6F7C, 0xBCE0, 0x6F7D, 0xE656, 0x6F7E, 0xE5FB,
+	0x6F7F, 0xE65C, 0x6F80, 0xC0DF, 0x6F82, 0xE64A, 0x6F84, 0xBCE1,	0x6F85, 0xE645, 0x6F86, 0xBCE5, 0x6F87, 0xE5FC, 0x6F88, 0xBAAB,
+	0x6F89, 0xE641, 0x6F8B, 0xE65A, 0x6F8C, 0xE642, 0x6F8D, 0xE640,	0x6F8E, 0xBCEA, 0x6F90, 0xE658, 0x6F92, 0xE5FE, 0x6F93, 0xE651,
+	0x6F94, 0xE650, 0x6F95, 0xE65D, 0x6F96, 0xE647, 0x6F97, 0xBCEE,	0x6F9E, 0xE9F3, 0x6FA0, 0xBF49, 0x6FA1, 0xBEFE, 0x6FA2, 0xEA40,
+	0x6FA3, 0xE9EB, 0x6FA4, 0xBF41, 0x6FA5, 0xE9F7, 0x6FA6, 0xBF48,	0x6FA7, 0xBF43, 0x6FA8, 0xE9F5, 0x6FA9, 0xED4F, 0x6FAA, 0xE9FB,
+	0x6FAB, 0xEA42, 0x6FAC, 0xE9FA, 0x6FAD, 0xE9E9, 0x6FAE, 0xE9F8,	0x6FAF, 0xEA44, 0x6FB0, 0xEA46, 0x6FB1, 0xBEFD, 0x6FB2, 0xEA45,
+	0x6FB3, 0xBF44, 0x6FB4, 0xBF4A, 0x6FB6, 0xBF47, 0x6FB8, 0xE9FE,	0x6FB9, 0xBF46, 0x6FBA, 0xE9F9, 0x6FBC, 0xE9ED, 0x6FBD, 0xE9F2,
+	0x6FBF, 0xE9FD, 0x6FC0, 0xBF45, 0x6FC1, 0xBF42, 0x6FC2, 0xBEFC,	0x6FC3, 0xBF40, 0x6FC4, 0xE9F1, 0x6FC6, 0xE5FD, 0x6FC7, 0xE9EC,
+	0x6FC8, 0xE9EF, 0x6FC9, 0xEA41, 0x6FCA, 0xE9F4, 0x6FCB, 0xE9EA,	0x6FCC, 0xED4E, 0x6FCD, 0xEA43, 0x6FCE, 0xE9EE, 0x6FCF, 0xE9FC,
+	0x6FD4, 0xED51, 0x6FD5, 0xC0E3, 0x6FD8, 0xC0D7, 0x6FDB, 0xC0DB,	0x6FDC, 0xED53, 0x6FDD, 0xED59, 0x6FDE, 0xED57, 0x6FDF, 0xC0D9,
+	0x6FE0, 0xC0DA, 0x6FE1, 0xC0E1, 0x6FE2, 0xED5A, 0x6FE3, 0xED52,	0x6FE4, 0xC0DC, 0x6FE6, 0xED56, 0x6FE7, 0xED55, 0x6FE8, 0xED5B,
+	0x6FE9, 0xC0E2, 0x6FEB, 0xC0DD, 0x6FEC, 0xC0E0, 0x6FED, 0xED54,	0x6FEE, 0xC0E4, 0x6FEF, 0xC0DE, 0x6FF0, 0xC0E5, 0x6FF1, 0xC0D8,
+	0x6FF2, 0xED58, 0x6FF4, 0xED50, 0x6FF7, 0xEFF7, 0x6FFA, 0xC271,	0x6FFB, 0xEFF4, 0x6FFC, 0xEFF6, 0x6FFE, 0xC26F, 0x6FFF, 0xEFF2,
+	0x7000, 0xEFF3, 0x7001, 0xEFEE, 0x7004, 0xE9F6, 0x7005, 0xEFEF,	0x7006, 0xC270, 0x7007, 0xEFEB, 0x7009, 0xC26D, 0x700A, 0xEFF8,
+	0x700B, 0xC26E, 0x700C, 0xEFEC, 0x700D, 0xEFED, 0x700E, 0xEFF1,	0x700F, 0xC273, 0x7011, 0xC272, 0x7014, 0xEFF0, 0x7015, 0xC378,
+	0x7016, 0xF25F, 0x7017, 0xF265, 0x7018, 0xC379, 0x7019, 0xF25C,	0x701A, 0xC376, 0x701B, 0xC373, 0x701C, 0xF267, 0x701D, 0xC377,
+	0x701F, 0xC374, 0x7020, 0xF25E, 0x7021, 0xF261, 0x7022, 0xF262,	0x7023, 0xF263, 0x7024, 0xF266, 0x7026, 0xEFF5, 0x7027, 0xF25D,
+	0x7028, 0xC375, 0x7029, 0xF264, 0x702A, 0xF268, 0x702B, 0xF260,	0x702F, 0xF45D, 0x7030, 0xC46A, 0x7031, 0xF460, 0x7032, 0xC46B,
+	0x7033, 0xF468, 0x7034, 0xF45F, 0x7035, 0xF45C, 0x7037, 0xF45E,	0x7038, 0xF462, 0x7039, 0xF465, 0x703A, 0xF464, 0x703B, 0xF467,
+	0x703C, 0xF45B, 0x703E, 0xC469, 0x703F, 0xF463, 0x7040, 0xF466,	0x7041, 0xF469, 0x7042, 0xF461, 0x7043, 0xF5D3, 0x7044, 0xF5D4,
+	0x7045, 0xF5D8, 0x7046, 0xF5D9, 0x7048, 0xF5D6, 0x7049, 0xF5D7,	0x704A, 0xF5D5, 0x704C, 0xC4E9, 0x7051, 0xC578, 0x7052, 0xF6EB,
+	0x7055, 0xF6E8, 0x7056, 0xF6E9, 0x7057, 0xF6EA, 0x7058, 0xC579,	0x705A, 0xF7E5, 0x705B, 0xF7E4, 0x705D, 0xF8AF, 0x705E, 0xC5F4,
+	0x705F, 0xF8AD, 0x7060, 0xF8B0, 0x7061, 0xF8AE, 0x7062, 0xF8F5,	0x7063, 0xC657, 0x7064, 0xC665, 0x7065, 0xF9A3, 0x7066, 0xF96C,
+	0x7068, 0xF9A2, 0x7069, 0xF9D0, 0x706A, 0xF9D1, 0x706B, 0xA4F5,	0x7070, 0xA6C7, 0x7071, 0xCA41, 0x7074, 0xCB5E, 0x7076, 0xA85F,
+	0x7078, 0xA862, 0x707A, 0xCB5F, 0x707C, 0xA860, 0x707D, 0xA861,	0x7082, 0xCD58, 0x7083, 0xCD5A, 0x7084, 0xCD55, 0x7085, 0xCD52,
+	0x7086, 0xCD54, 0x708A, 0xAAA4, 0x708E, 0xAAA2, 0x7091, 0xCD56,	0x7092, 0xAAA3, 0x7093, 0xCD53, 0x7094, 0xCD50, 0x7095, 0xAAA1,
+	0x7096, 0xCD57, 0x7098, 0xCD51, 0x7099, 0xAAA5, 0x709A, 0xCD59,	0x709F, 0xCFAF, 0x70A1, 0xCFB3, 0x70A4, 0xACB7, 0x70A9, 0xCFB6,
+	0x70AB, 0xACAF, 0x70AC, 0xACB2, 0x70AD, 0xACB4, 0x70AE, 0xACB6,	0x70AF, 0xACB3, 0x70B0, 0xCFB2, 0x70B1, 0xCFB1, 0x70B3, 0xACB1,
+	0x70B4, 0xCFB4, 0x70B5, 0xCFB5, 0x70B7, 0xCFAE, 0x70B8, 0xACB5,	0x70BA, 0xACB0, 0x70BE, 0xCFB0, 0x70C5, 0xD277, 0x70C6, 0xD278,
+	0x70C7, 0xD279, 0x70C8, 0xAF50, 0x70CA, 0xAF4C, 0x70CB, 0xD26E,	0x70CD, 0xD276, 0x70CE, 0xD27B, 0x70CF, 0xAF51, 0x70D1, 0xD26C,
+	0x70D2, 0xD272, 0x70D3, 0xD26B, 0x70D4, 0xD275, 0x70D7, 0xD271,	0x70D8, 0xAF4D, 0x70D9, 0xAF4F, 0x70DA, 0xD27A, 0x70DC, 0xD26A,
+	0x70DD, 0xD26D, 0x70DE, 0xD273, 0x70E0, 0xD274, 0x70E1, 0xD27C,	0x70E2, 0xD270, 0x70E4, 0xAF4E, 0x70EF, 0xB26D, 0x70F0, 0xD64E,
+	0x70F3, 0xD650, 0x70F4, 0xD64C, 0x70F6, 0xD658, 0x70F7, 0xD64A,	0x70F8, 0xD657, 0x70F9, 0xB269, 0x70FA, 0xD648, 0x70FB, 0xDA5B,
+	0x70FC, 0xD652, 0x70FD, 0xB26C, 0x70FF, 0xD653, 0x7100, 0xD656,	0x7102, 0xD65A, 0x7104, 0xD64F, 0x7106, 0xD654, 0x7109, 0xB26A,
+	0x710A, 0xB26B, 0x710B, 0xD659, 0x710C, 0xD64D, 0x710D, 0xD649,	0x710E, 0xD65B, 0x7110, 0xD651, 0x7113, 0xD655, 0x7117, 0xD64B,
+	0x7119, 0xB548, 0x711A, 0xB549, 0x711B, 0xDA65, 0x711C, 0xB54F,	0x711E, 0xDA59, 0x711F, 0xDA62, 0x7120, 0xDA58, 0x7121, 0xB54C,
+	0x7122, 0xDA60, 0x7123, 0xDA5E, 0x7125, 0xDA5F, 0x7126, 0xB54A,	0x7128, 0xDA63, 0x712E, 0xDA5C, 0x712F, 0xDA5A, 0x7130, 0xB54B,
+	0x7131, 0xDA5D, 0x7132, 0xDA61, 0x7136, 0xB54D, 0x713A, 0xDA64,	0x7141, 0xDE70, 0x7142, 0xDE77, 0x7143, 0xDE79, 0x7144, 0xDEA1,
+	0x7146, 0xB7DA, 0x7147, 0xDE6B, 0x7149, 0xB7D2, 0x714B, 0xDE7A,	0x714C, 0xB7D7, 0x714D, 0xDEA2, 0x714E, 0xB7CE, 0x7150, 0xDE7D,
+	0x7152, 0xDE6D, 0x7153, 0xDE7E, 0x7154, 0xDE6C, 0x7156, 0xB7DC,	0x7158, 0xDE78, 0x7159, 0xB7CF, 0x715A, 0xDEA3, 0x715C, 0xB7D4,
+	0x715D, 0xDE71, 0x715E, 0xB7D9, 0x715F, 0xDE7C, 0x7160, 0xDE6F,	0x7161, 0xDE76, 0x7162, 0xDE72, 0x7163, 0xDE6E, 0x7164, 0xB7D1,
+	0x7165, 0xB7D8, 0x7166, 0xB7D6, 0x7167, 0xB7D3, 0x7168, 0xB7DB,	0x7169, 0xB7D0, 0x716A, 0xDE75, 0x716C, 0xB7D5, 0x716E, 0xB54E,
+	0x7170, 0xDE7B, 0x7172, 0xDE73, 0x7178, 0xDE74, 0x717B, 0xE2C1,	0x717D, 0xBAB4, 0x7180, 0xE2BD, 0x7181, 0xE2C3, 0x7182, 0xE2BF,
+	0x7184, 0xBAB6, 0x7185, 0xE2BE, 0x7186, 0xE2C2, 0x7187, 0xE2BA,	0x7189, 0xE2BC, 0x718A, 0xBAB5, 0x718F, 0xE2C0, 0x7190, 0xE2BB,
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+	0x75CD, 0xB2AD, 0x75CE, 0xD67C, 0x75CF, 0xD67E, 0x75D0, 0xD6A4,	0x75D1, 0xD6A3, 0x75D2, 0xD67D, 0x75D4, 0xB2A9, 0x75D5, 0xB2AA,
+	0x75D7, 0xDAB6, 0x75D8, 0xB56B, 0x75D9, 0xB56A, 0x75DA, 0xDAB0,	0x75DB, 0xB568, 0x75DD, 0xDAB3, 0x75DE, 0xB56C, 0x75DF, 0xDAB4,
+	0x75E0, 0xB56D, 0x75E1, 0xDAB1, 0x75E2, 0xB567, 0x75E3, 0xB569,	0x75E4, 0xDAB5, 0x75E6, 0xDAB2, 0x75E7, 0xDAAF, 0x75ED, 0xDED2,
+	0x75EF, 0xDEC7, 0x75F0, 0xB7F0, 0x75F1, 0xB7F3, 0x75F2, 0xB7F2,	0x75F3, 0xB7F7, 0x75F4, 0xB7F6, 0x75F5, 0xDED3, 0x75F6, 0xDED1,
+	0x75F7, 0xDECA, 0x75F8, 0xDECE, 0x75F9, 0xDECD, 0x75FA, 0xB7F4,	0x75FB, 0xDED0, 0x75FC, 0xDECC, 0x75FD, 0xDED4, 0x75FE, 0xDECB,
+	0x75FF, 0xB7F5, 0x7600, 0xB7EF, 0x7601, 0xB7F1, 0x7603, 0xDEC9,	0x7608, 0xE2DB, 0x7609, 0xBAC7, 0x760A, 0xE2DF, 0x760B, 0xBAC6,
+	0x760C, 0xE2DC, 0x760D, 0xBAC5, 0x760F, 0xDEC8, 0x7610, 0xDECF,	0x7611, 0xE2DE, 0x7613, 0xBAC8, 0x7614, 0xE2E0, 0x7615, 0xE2DD,
+	0x7616, 0xE2DA, 0x7619, 0xE6B1, 0x761A, 0xE6B5, 0x761B, 0xE6B7,	0x761C, 0xE6B3, 0x761D, 0xE6B2, 0x761E, 0xE6B0, 0x761F, 0xBD45,
+	0x7620, 0xBD43, 0x7621, 0xBD48, 0x7622, 0xBD49, 0x7623, 0xE6B4,	0x7624, 0xBD46, 0x7625, 0xE6AF, 0x7626, 0xBD47, 0x7627, 0xBAC4,
+	0x7628, 0xE6B6, 0x7629, 0xBD44, 0x762D, 0xEA6C, 0x762F, 0xEA6B,	0x7630, 0xEA73, 0x7631, 0xEA6D, 0x7632, 0xEA72, 0x7633, 0xEA6F,
+	0x7634, 0xBF60, 0x7635, 0xEA71, 0x7638, 0xBF61, 0x763A, 0xBF62,	0x763C, 0xEA70, 0x763D, 0xEA6E, 0x7642, 0xC0F8, 0x7643, 0xED74,
+	0x7646, 0xC0F7, 0x7647, 0xED77, 0x7648, 0xED75, 0x7649, 0xED76,	0x764C, 0xC0F9, 0x7650, 0xF04D, 0x7652, 0xC2A1, 0x7653, 0xF04E,
+	0x7656, 0xC27D, 0x7657, 0xF04F, 0x7658, 0xC27E, 0x7659, 0xF04C,	0x765A, 0xF050, 0x765C, 0xF04A, 0x765F, 0xC3A7, 0x7660, 0xF278,
+	0x7661, 0xC3A8, 0x7662, 0xC46F, 0x7664, 0xF04B, 0x7665, 0xC470,	0x7669, 0xC4EE, 0x766A, 0xF5DF, 0x766C, 0xC57E, 0x766D, 0xF6F4,
+	0x766E, 0xC57D, 0x7670, 0xF7EA, 0x7671, 0xC5F5, 0x7672, 0xC5F6,	0x7675, 0xF9CC, 0x7678, 0xACD1, 0x7679, 0xCFDE, 0x767B, 0xB56E,
+	0x767C, 0xB56F, 0x767D, 0xA5D5, 0x767E, 0xA6CA, 0x767F, 0xCA47,	0x7681, 0xCB71, 0x7682, 0xA86D, 0x7684, 0xAABA, 0x7686, 0xACD2,
+	0x7687, 0xACD3, 0x7688, 0xACD4, 0x7689, 0xD6A6, 0x768A, 0xD2CB,	0x768B, 0xAF6F, 0x768E, 0xB2AE, 0x768F, 0xD6A5, 0x7692, 0xDAB8,
+	0x7693, 0xB571, 0x7695, 0xDAB7, 0x7696, 0xB570, 0x7699, 0xDED5,	0x769A, 0xBD4A, 0x769B, 0xE6BB, 0x769C, 0xE6B8, 0x769D, 0xE6B9,
+	0x769E, 0xE6BA, 0x76A4, 0xED78, 0x76A6, 0xF051, 0x76AA, 0xF471,	0x76AB, 0xF470, 0x76AD, 0xF6F5, 0x76AE, 0xA5D6, 0x76AF, 0xCD75,
+	0x76B0, 0xAF70, 0x76B4, 0xB572, 0x76B5, 0xDED6, 0x76B8, 0xE2E1,	0x76BA, 0xBD4B, 0x76BB, 0xEA74, 0x76BD, 0xF052, 0x76BE, 0xF472,
+	0x76BF, 0xA5D7, 0x76C2, 0xAABB, 0x76C3, 0xACD7, 0x76C4, 0xCFDF,	0x76C5, 0xACD8, 0x76C6, 0xACD6, 0x76C8, 0xACD5, 0x76C9, 0xD2CC,
+	0x76CA, 0xAF71, 0x76CD, 0xAF72, 0x76CE, 0xAF73, 0x76D2, 0xB2B0,	0x76D3, 0xD6A7, 0x76D4, 0xB2AF, 0x76DA, 0xDAB9, 0x76DB, 0xB2B1,
+	0x76DC, 0xB573, 0x76DD, 0xDED7, 0x76DE, 0xB7F8, 0x76DF, 0xB7F9,	0x76E1, 0xBAC9, 0x76E3, 0xBACA, 0x76E4, 0xBD4C, 0x76E5, 0xBF64,
+	0x76E6, 0xEA75, 0x76E7, 0xBF63, 0x76E9, 0xED79, 0x76EA, 0xC0FA,	0x76EC, 0xF053, 0x76ED, 0xF473, 0x76EE, 0xA5D8, 0x76EF, 0xA86E,
+	0x76F0, 0xCD78, 0x76F1, 0xCD77, 0x76F2, 0xAABC, 0x76F3, 0xCD76,	0x76F4, 0xAABD, 0x76F5, 0xCD79, 0x76F7, 0xCFE5, 0x76F8, 0xACDB,
+	0x76F9, 0xACDA, 0x76FA, 0xCFE7, 0x76FB, 0xCFE6, 0x76FC, 0xACDF,	0x76FE, 0xACDE, 0x7701, 0xACD9, 0x7703, 0xCFE1, 0x7704, 0xCFE2,
+	0x7705, 0xCFE3, 0x7707, 0xACE0, 0x7708, 0xCFE0, 0x7709, 0xACDC,	0x770A, 0xCFE4, 0x770B, 0xACDD, 0x7710, 0xD2CF, 0x7711, 0xD2D3,
+	0x7712, 0xD2D1, 0x7713, 0xD2D0, 0x7715, 0xD2D4, 0x7719, 0xD2D5,	0x771A, 0xD2D6, 0x771B, 0xD2CE, 0x771D, 0xD2CD, 0x771F, 0xAF75,
+	0x7720, 0xAF76, 0x7722, 0xD2D7, 0x7723, 0xD2D2, 0x7725, 0xD6B0,	0x7727, 0xD2D8, 0x7728, 0xAF77, 0x7729, 0xAF74, 0x772D, 0xD6AA,
+	0x772F, 0xD6A9, 0x7731, 0xD6AB, 0x7732, 0xD6AC, 0x7733, 0xD6AE,	0x7734, 0xD6AD, 0x7735, 0xD6B2, 0x7736, 0xB2B5, 0x7737, 0xB2B2,
+	0x7738, 0xB2B6, 0x7739, 0xD6A8, 0x773A, 0xB2B7, 0x773B, 0xD6B1,	0x773C, 0xB2B4, 0x773D, 0xD6AF, 0x773E, 0xB2B3, 0x7744, 0xDABC,
+	0x7745, 0xDABE, 0x7746, 0xDABA, 0x7747, 0xDABB, 0x774A, 0xDABF,	0x774B, 0xDAC1, 0x774C, 0xDAC2, 0x774D, 0xDABD, 0x774E, 0xDAC0,
+	0x774F, 0xB574, 0x7752, 0xDEDB, 0x7754, 0xDEE0, 0x7755, 0xDED8,	0x7756, 0xDEDC, 0x7759, 0xDEE1, 0x775A, 0xDEDD, 0x775B, 0xB7FA,
+	0x775C, 0xB843, 0x775E, 0xB7FD, 0x775F, 0xDED9, 0x7760, 0xDEDA,	0x7761, 0xBACE, 0x7762, 0xB846, 0x7763, 0xB7FE, 0x7765, 0xB844,
+	0x7766, 0xB7FC, 0x7767, 0xDEDF, 0x7768, 0xB845, 0x7769, 0xDEDE,	0x776A, 0xB841, 0x776B, 0xB7FB, 0x776C, 0xB842, 0x776D, 0xDEE2,
+	0x776E, 0xE2E6, 0x776F, 0xE2E8, 0x7779, 0xB840, 0x777C, 0xE2E3,	0x777D, 0xBACC, 0x777E, 0xE2E9, 0x777F, 0xBACD, 0x7780, 0xE2E7,
+	0x7781, 0xE2E2, 0x7782, 0xE2E5, 0x7783, 0xE2EA, 0x7784, 0xBACB,	0x7785, 0xE2E4, 0x7787, 0xBD4E, 0x7788, 0xE6BF, 0x7789, 0xE6BE,
+	0x778B, 0xBD51, 0x778C, 0xBD4F, 0x778D, 0xE6BC, 0x778E, 0xBD4D,	0x778F, 0xE6BD, 0x7791, 0xBD50, 0x7795, 0xEA7D, 0x7797, 0xEAA1,
+	0x7799, 0xEA7E, 0x779A, 0xEA76, 0x779B, 0xEA7A, 0x779C, 0xEA79,	0x779D, 0xEA77, 0x779E, 0xBF66, 0x779F, 0xBF67, 0x77A0, 0xBF65,
+	0x77A1, 0xEA78, 0x77A2, 0xEA7B, 0x77A3, 0xEA7C, 0x77A5, 0xBF68,	0x77A7, 0xC140, 0x77A8, 0xEDA3, 0x77AA, 0xC0FC, 0x77AB, 0xED7B,
+	0x77AC, 0xC0FE, 0x77AD, 0xC141, 0x77B0, 0xC0FD, 0x77B1, 0xEDA2,	0x77B2, 0xED7C, 0x77B3, 0xC0FB, 0x77B4, 0xEDA1, 0x77B5, 0xED7A,
+	0x77B6, 0xED7E, 0x77B7, 0xED7D, 0x77BA, 0xF055, 0x77BB, 0xC2A4,	0x77BC, 0xC2A5, 0x77BD, 0xC2A2, 0x77BF, 0xC2A3, 0x77C2, 0xF054,
+	0x77C4, 0xF27B, 0x77C7, 0xC3A9, 0x77C9, 0xF279, 0x77CA, 0xF27A,	0x77CC, 0xF474, 0x77CD, 0xF477, 0x77CE, 0xF475, 0x77CF, 0xF476,
+	0x77D0, 0xF5E0, 0x77D3, 0xC4EF, 0x77D4, 0xF7EB, 0x77D5, 0xF8B4,	0x77D7, 0xC5F7, 0x77D8, 0xF8F8, 0x77D9, 0xF8F9, 0x77DA, 0xC666,
+	0x77DB, 0xA5D9, 0x77DC, 0xACE1, 0x77DE, 0xDAC3, 0x77E0, 0xDEE3,	0x77E2, 0xA5DA, 0x77E3, 0xA86F, 0x77E5, 0xAABE, 0x77E7, 0xCFE8,
+	0x77E8, 0xCFE9, 0x77E9, 0xAF78, 0x77EC, 0xDAC4, 0x77ED, 0xB575,	0x77EE, 0xB847, 0x77EF, 0xC142, 0x77F0, 0xEDA4, 0x77F1, 0xF27C,
+	0x77F2, 0xF478, 0x77F3, 0xA5DB, 0x77F7, 0xCDA1, 0x77F8, 0xCD7A,	0x77F9, 0xCD7C, 0x77FA, 0xCD7E, 0x77FB, 0xCD7D, 0x77FC, 0xCD7B,
+	0x77FD, 0xAABF, 0x7802, 0xACE2, 0x7803, 0xCFF2, 0x7805, 0xCFED,	0x7806, 0xCFEA, 0x7809, 0xCFF1, 0x780C, 0xACE4, 0x780D, 0xACE5,
+	0x780E, 0xCFF0, 0x780F, 0xCFEF, 0x7810, 0xCFEE, 0x7811, 0xCFEB,	0x7812, 0xCFEC, 0x7813, 0xCFF3, 0x7814, 0xACE3, 0x781D, 0xAF7C,
+	0x781F, 0xAFA4, 0x7820, 0xAFA3, 0x7821, 0xD2E1, 0x7822, 0xD2DB,	0x7823, 0xD2D9, 0x7825, 0xAFA1, 0x7826, 0xD6B9, 0x7827, 0xAF7A,
+	0x7828, 0xD2DE, 0x7829, 0xD2E2, 0x782A, 0xD2E4, 0x782B, 0xD2E0,	0x782C, 0xD2DA, 0x782D, 0xAFA2, 0x782E, 0xD2DF, 0x782F, 0xD2DD,
+	0x7830, 0xAF79, 0x7831, 0xD2E5, 0x7832, 0xAFA5, 0x7833, 0xD2E3,	0x7834, 0xAF7D, 0x7835, 0xD2DC, 0x7837, 0xAF7E, 0x7838, 0xAF7B,
+	0x7843, 0xB2B9, 0x7845, 0xD6BA, 0x7848, 0xD6B3, 0x7849, 0xD6B5,	0x784A, 0xD6B7, 0x784C, 0xD6B8, 0x784D, 0xD6B6, 0x784E, 0xB2BA,
+	0x7850, 0xD6BB, 0x7852, 0xD6B4, 0x785C, 0xDAC8, 0x785D, 0xB576,	0x785E, 0xDAD0, 0x7860, 0xDAC5, 0x7862, 0xDAD1, 0x7864, 0xDAC6,
+	0x7865, 0xDAC7, 0x7868, 0xDACF, 0x7869, 0xDACE, 0x786A, 0xDACB,	0x786B, 0xB2B8, 0x786C, 0xB577, 0x786D, 0xDAC9, 0x786E, 0xDACC,
+	0x786F, 0xB578, 0x7870, 0xDACD, 0x7871, 0xDACA, 0x7879, 0xDEEE,	0x787B, 0xDEF2, 0x787C, 0xB84E, 0x787E, 0xE2F0, 0x787F, 0xB851,
+	0x7880, 0xDEF0, 0x7881, 0xF9D6, 0x7883, 0xDEED, 0x7884, 0xDEE8,	0x7885, 0xDEEA, 0x7886, 0xDEEB, 0x7887, 0xDEE4, 0x7889, 0xB84D,
+	0x788C, 0xB84C, 0x788E, 0xB848, 0x788F, 0xDEE7, 0x7891, 0xB84F,	0x7893, 0xB850, 0x7894, 0xDEE6, 0x7895, 0xDEE9, 0x7896, 0xDEF1,
+	0x7897, 0xB84A, 0x7898, 0xB84B, 0x7899, 0xDEEF, 0x789A, 0xDEE5,	0x789E, 0xE2F2, 0x789F, 0xBAD0, 0x78A0, 0xE2F4, 0x78A1, 0xDEEC,
+	0x78A2, 0xE2F6, 0x78A3, 0xBAD4, 0x78A4, 0xE2F7, 0x78A5, 0xE2F3,	0x78A7, 0xBAD1, 0x78A8, 0xE2EF, 0x78A9, 0xBAD3, 0x78AA, 0xE2EC,
+	0x78AB, 0xE2F1, 0x78AC, 0xE2F5, 0x78AD, 0xE2EE, 0x78B0, 0xB849,	0x78B2, 0xE2EB, 0x78B3, 0xBAD2, 0x78B4, 0xE2ED, 0x78BA, 0xBD54,
+	0x78BB, 0xE6C1, 0x78BC, 0xBD58, 0x78BE, 0xBD56, 0x78C1, 0xBACF,	0x78C3, 0xE6C8, 0x78C4, 0xE6C9, 0x78C5, 0xBD53, 0x78C8, 0xE6C7,
+	0x78C9, 0xE6CA, 0x78CA, 0xBD55, 0x78CB, 0xBD52, 0x78CC, 0xE6C3,	0x78CD, 0xE6C0, 0x78CE, 0xE6C5, 0x78CF, 0xE6C2, 0x78D0, 0xBD59,
+	0x78D1, 0xE6C4, 0x78D4, 0xE6C6, 0x78D5, 0xBD57, 0x78DA, 0xBF6A,	0x78DB, 0xEAA8, 0x78DD, 0xEAA2, 0x78DE, 0xEAA6, 0x78DF, 0xEAAC,
+	0x78E0, 0xEAAD, 0x78E1, 0xEAA9, 0x78E2, 0xEAAA, 0x78E3, 0xEAA7,	0x78E5, 0xEAA4, 0x78E7, 0xBF6C, 0x78E8, 0xBF69, 0x78E9, 0xEAA3,
+	0x78EA, 0xEAA5, 0x78EC, 0xBF6B, 0x78ED, 0xEAAB, 0x78EF, 0xC146,	0x78F2, 0xEDAA, 0x78F3, 0xEDA5, 0x78F4, 0xC145, 0x78F7, 0xC143,
+	0x78F9, 0xEDAC, 0x78FA, 0xC144, 0x78FB, 0xEDA8, 0x78FC, 0xEDA9,	0x78FD, 0xEDA6, 0x78FE, 0xEDAD, 0x78FF, 0xF056, 0x7901, 0xC147,
+	0x7902, 0xEDA7, 0x7904, 0xEDAE, 0x7905, 0xEDAB, 0x7909, 0xF05A,	0x790C, 0xF057, 0x790E, 0xC2A6, 0x7910, 0xF05B, 0x7911, 0xF05D,
+	0x7912, 0xF05C, 0x7913, 0xF058, 0x7914, 0xF059, 0x7917, 0xF2A3,	0x7919, 0xC3AA, 0x791B, 0xF27E, 0x791C, 0xF2A2, 0x791D, 0xF27D,
+	0x791E, 0xF2A4, 0x7921, 0xF2A1, 0x7923, 0xF47A, 0x7924, 0xF47D,	0x7925, 0xF479, 0x7926, 0xC471, 0x7927, 0xF47B, 0x7928, 0xF47C,
+	0x7929, 0xF47E, 0x792A, 0xC472, 0x792B, 0xC474, 0x792C, 0xC473,	0x792D, 0xF5E1, 0x792F, 0xF5E3, 0x7931, 0xF5E2, 0x7935, 0xF6F6,
+	0x7938, 0xF8B5, 0x7939, 0xF8FA, 0x793A, 0xA5DC, 0x793D, 0xCB72,	0x793E, 0xAAC0, 0x793F, 0xCDA3, 0x7940, 0xAAC1, 0x7941, 0xAAC2,
+	0x7942, 0xCDA2, 0x7944, 0xCFF8, 0x7945, 0xCFF7, 0x7946, 0xACE6,	0x7947, 0xACE9, 0x7948, 0xACE8, 0x7949, 0xACE7, 0x794A, 0xCFF4,
+	0x794B, 0xCFF6, 0x794C, 0xCFF5, 0x794F, 0xD2E8, 0x7950, 0xAFA7,	0x7951, 0xD2EC, 0x7952, 0xD2EB, 0x7953, 0xD2EA, 0x7954, 0xD2E6,
+	0x7955, 0xAFA6, 0x7956, 0xAFAA, 0x7957, 0xAFAD, 0x795A, 0xAFAE,	0x795B, 0xD2E7, 0x795C, 0xD2E9, 0x795D, 0xAFAC, 0x795E, 0xAFAB,
+	0x795F, 0xAFA9, 0x7960, 0xAFA8, 0x7961, 0xD6C2, 0x7963, 0xD6C0,	0x7964, 0xD6BC, 0x7965, 0xB2BB, 0x7967, 0xD6BD, 0x7968, 0xB2BC,
+	0x7969, 0xD6BE, 0x796A, 0xD6BF, 0x796B, 0xD6C1, 0x796D, 0xB2BD,	0x7970, 0xDAD5, 0x7972, 0xDAD4, 0x7973, 0xDAD3, 0x7974, 0xDAD2,
+	0x7979, 0xDEF6, 0x797A, 0xB852, 0x797C, 0xDEF3, 0x797D, 0xDEF5,	0x797F, 0xB853, 0x7981, 0xB854, 0x7982, 0xDEF4, 0x7988, 0xE341,
+	0x798A, 0xE2F9, 0x798B, 0xE2FA, 0x798D, 0xBAD7, 0x798E, 0xBAD5,	0x798F, 0xBAD6, 0x7990, 0xE343, 0x7992, 0xE342, 0x7993, 0xE2FE,
+	0x7994, 0xE2FD, 0x7995, 0xE2FC, 0x7996, 0xE2FB, 0x7997, 0xE340,	0x7998, 0xE2F8, 0x799A, 0xE6CB, 0x799B, 0xE6D0, 0x799C, 0xE6CE,
+	0x79A0, 0xE6CD, 0x79A1, 0xE6CC, 0x79A2, 0xE6CF, 0x79A4, 0xEAAE,	0x79A6, 0xBF6D, 0x79A7, 0xC148, 0x79A8, 0xEDB0, 0x79AA, 0xC149,
+	0x79AB, 0xEDAF, 0x79AC, 0xF05F, 0x79AD, 0xF05E, 0x79AE, 0xC2A7,	0x79B0, 0xF2A5, 0x79B1, 0xC3AB, 0x79B2, 0xF4A1, 0x79B3, 0xC5A1,
+	0x79B4, 0xF6F7, 0x79B6, 0xF8B7, 0x79B7, 0xF8B6, 0x79B8, 0xC9A8,	0x79B9, 0xACEA, 0x79BA, 0xACEB, 0x79BB, 0xD6C3, 0x79BD, 0xB856,
+	0x79BE, 0xA5DD, 0x79BF, 0xA872, 0x79C0, 0xA871, 0x79C1, 0xA870,	0x79C5, 0xCDA4, 0x79C8, 0xAAC4, 0x79C9, 0xAAC3, 0x79CB, 0xACEE,
+	0x79CD, 0xCFFA, 0x79CE, 0xCFFD, 0x79CF, 0xCFFB, 0x79D1, 0xACEC,	0x79D2, 0xACED, 0x79D5, 0xCFF9, 0x79D6, 0xCFFC, 0x79D8, 0xAFB5,
+	0x79DC, 0xD2F3, 0x79DD, 0xD2F5, 0x79DE, 0xD2F4, 0x79DF, 0xAFB2,	0x79E0, 0xD2EF, 0x79E3, 0xAFB0, 0x79E4, 0xAFAF, 0x79E6, 0xAFB3,
+	0x79E7, 0xAFB1, 0x79E9, 0xAFB4, 0x79EA, 0xD2F2, 0x79EB, 0xD2ED,	0x79EC, 0xD2EE, 0x79ED, 0xD2F1, 0x79EE, 0xD2F0, 0x79F6, 0xD6C6,
+	0x79F7, 0xD6C7, 0x79F8, 0xD6C5, 0x79FA, 0xD6C4, 0x79FB, 0xB2BE,	0x7A00, 0xB57D, 0x7A02, 0xDAD6, 0x7A03, 0xDAD8, 0x7A04, 0xDADA,
+	0x7A05, 0xB57C, 0x7A08, 0xB57A, 0x7A0A, 0xDAD7, 0x7A0B, 0xB57B,	0x7A0C, 0xDAD9, 0x7A0D, 0xB579, 0x7A10, 0xDF41, 0x7A11, 0xDEF7,
+	0x7A12, 0xDEFA, 0x7A13, 0xDEFE, 0x7A14, 0xB85A, 0x7A15, 0xDEFC,	0x7A17, 0xDEFB, 0x7A18, 0xDEF8, 0x7A19, 0xDEF9, 0x7A1A, 0xB858,
+	0x7A1B, 0xDF40, 0x7A1C, 0xB857, 0x7A1E, 0xB85C, 0x7A1F, 0xB85B,	0x7A20, 0xB859, 0x7A22, 0xDEFD, 0x7A26, 0xE349, 0x7A28, 0xE348,
+	0x7A2B, 0xE344, 0x7A2E, 0xBAD8, 0x7A2F, 0xE347, 0x7A30, 0xE346,	0x7A31, 0xBAD9, 0x7A37, 0xBD5E, 0x7A39, 0xE6D2, 0x7A3B, 0xBD5F,
+	0x7A3C, 0xBD5B, 0x7A3D, 0xBD5D, 0x7A3F, 0xBD5A, 0x7A40, 0xBD5C,	0x7A44, 0xEAAF, 0x7A46, 0xBF70, 0x7A47, 0xEAB1, 0x7A48, 0xEAB0,
+	0x7A4A, 0xE345, 0x7A4B, 0xBF72, 0x7A4C, 0xBF71, 0x7A4D, 0xBF6E,	0x7A4E, 0xBF6F, 0x7A54, 0xEDB5, 0x7A56, 0xEDB3, 0x7A57, 0xC14A,
+	0x7A58, 0xEDB4, 0x7A5A, 0xEDB6, 0x7A5B, 0xEDB2, 0x7A5C, 0xEDB1,	0x7A5F, 0xF060, 0x7A60, 0xC2AA, 0x7A61, 0xC2A8, 0x7A62, 0xC2A9,
+	0x7A67, 0xF2A6, 0x7A68, 0xF2A7, 0x7A69, 0xC3AD, 0x7A6B, 0xC3AC,	0x7A6C, 0xF4A3, 0x7A6D, 0xF4A4, 0x7A6E, 0xF4A2, 0x7A70, 0xF6F8,
+	0x7A71, 0xF6F9, 0x7A74, 0xA5DE, 0x7A75, 0xCA48, 0x7A76, 0xA873,	0x7A78, 0xCDA5, 0x7A79, 0xAAC6, 0x7A7A, 0xAAC5, 0x7A7B, 0xCDA6,
+	0x7A7E, 0xD040, 0x7A7F, 0xACEF, 0x7A80, 0xCFFE, 0x7A81, 0xACF0,	0x7A84, 0xAFB6, 0x7A85, 0xD2F8, 0x7A86, 0xD2F6, 0x7A87, 0xD2FC,
+	0x7A88, 0xAFB7, 0x7A89, 0xD2F7, 0x7A8A, 0xD2FB, 0x7A8B, 0xD2F9,	0x7A8C, 0xD2FA, 0x7A8F, 0xD6C8, 0x7A90, 0xD6CA, 0x7A92, 0xB2BF,
+	0x7A94, 0xD6C9, 0x7A95, 0xB2C0, 0x7A96, 0xB5A2, 0x7A97, 0xB5A1,	0x7A98, 0xB57E, 0x7A99, 0xDADB, 0x7A9E, 0xDF44, 0x7A9F, 0xB85D,
+	0x7AA0, 0xB85E, 0x7AA2, 0xDF43, 0x7AA3, 0xDF42, 0x7AA8, 0xE34A,	0x7AA9, 0xBADB, 0x7AAA, 0xBADA, 0x7AAB, 0xE34B, 0x7AAC, 0xE34C,
+	0x7AAE, 0xBD61, 0x7AAF, 0xBD60, 0x7AB1, 0xEAB5, 0x7AB2, 0xE6D3,	0x7AB3, 0xE6D5, 0x7AB4, 0xE6D4, 0x7AB5, 0xEAB4, 0x7AB6, 0xEAB2,
+	0x7AB7, 0xEAB6, 0x7AB8, 0xEAB3, 0x7ABA, 0xBF73, 0x7ABE, 0xEDB7,	0x7ABF, 0xC14B, 0x7AC0, 0xEDB8, 0x7AC1, 0xEDB9, 0x7AC4, 0xC2AB,
+	0x7AC5, 0xC2AC, 0x7AC7, 0xC475, 0x7ACA, 0xC5D1, 0x7ACB, 0xA5DF,	0x7AD1, 0xD041, 0x7AD8, 0xD2FD, 0x7AD9, 0xAFB8, 0x7ADF, 0xB3BA,
+	0x7AE0, 0xB3B9, 0x7AE3, 0xB5A4, 0x7AE4, 0xDADD, 0x7AE5, 0xB5A3,	0x7AE6, 0xDADC, 0x7AEB, 0xDF45, 0x7AED, 0xBADC, 0x7AEE, 0xE34D,
+	0x7AEF, 0xBADD, 0x7AF6, 0xC476, 0x7AF7, 0xF4A5, 0x7AF9, 0xA6CB,	0x7AFA, 0xAAC7, 0x7AFB, 0xCDA7, 0x7AFD, 0xACF2, 0x7AFF, 0xACF1,
+	0x7B00, 0xD042, 0x7B01, 0xD043, 0x7B04, 0xD340, 0x7B05, 0xD342,	0x7B06, 0xAFB9, 0x7B08, 0xD344, 0x7B09, 0xD347, 0x7B0A, 0xD345,
+	0x7B0E, 0xD346, 0x7B0F, 0xD343, 0x7B10, 0xD2FE, 0x7B11, 0xAFBA,	0x7B12, 0xD348, 0x7B13, 0xD341, 0x7B18, 0xD6D3, 0x7B19, 0xB2C6,
+	0x7B1A, 0xD6DC, 0x7B1B, 0xB2C3, 0x7B1D, 0xD6D5, 0x7B1E, 0xB2C7,	0x7B20, 0xB2C1, 0x7B22, 0xD6D0, 0x7B23, 0xD6DD, 0x7B24, 0xD6D1,
+	0x7B25, 0xD6CE, 0x7B26, 0xB2C5, 0x7B28, 0xB2C2, 0x7B2A, 0xD6D4,	0x7B2B, 0xD6D7, 0x7B2C, 0xB2C4, 0x7B2D, 0xD6D8, 0x7B2E, 0xB2C8,
+	0x7B2F, 0xD6D9, 0x7B30, 0xD6CF, 0x7B31, 0xD6D6, 0x7B32, 0xD6DA,	0x7B33, 0xD6D2, 0x7B34, 0xD6CD, 0x7B35, 0xD6CB, 0x7B38, 0xD6DB,
+	0x7B3B, 0xDADF, 0x7B40, 0xDAE4, 0x7B44, 0xDAE0, 0x7B45, 0xDAE6,	0x7B46, 0xB5A7, 0x7B47, 0xD6CC, 0x7B48, 0xDAE1, 0x7B49, 0xB5A5,
+	0x7B4A, 0xDADE, 0x7B4B, 0xB5AC, 0x7B4C, 0xDAE2, 0x7B4D, 0xB5AB,	0x7B4E, 0xDAE3, 0x7B4F, 0xB5AD, 0x7B50, 0xB5A8, 0x7B51, 0xB5AE,
+	0x7B52, 0xB5A9, 0x7B54, 0xB5AA, 0x7B56, 0xB5A6, 0x7B58, 0xDAE5,	0x7B60, 0xB861, 0x7B61, 0xDF50, 0x7B63, 0xDF53, 0x7B64, 0xDF47,
+	0x7B65, 0xDF4C, 0x7B66, 0xDF46, 0x7B67, 0xB863, 0x7B69, 0xDF4A,	0x7B6D, 0xDF48, 0x7B6E, 0xB862, 0x7B70, 0xDF4F, 0x7B71, 0xDF4E,
+	0x7B72, 0xDF4B, 0x7B73, 0xDF4D, 0x7B74, 0xDF49, 0x7B75, 0xBAE1,	0x7B76, 0xDF52, 0x7B77, 0xB85F, 0x7B78, 0xDF51, 0x7B82, 0xE35D,
+	0x7B84, 0xBAE8, 0x7B85, 0xE358, 0x7B87, 0xBAE7, 0x7B88, 0xE34E,	0x7B8A, 0xE350, 0x7B8B, 0xBAE0, 0x7B8C, 0xE355, 0x7B8D, 0xE354,
+	0x7B8E, 0xE357, 0x7B8F, 0xBAE5, 0x7B90, 0xE352, 0x7B91, 0xE351,	0x7B94, 0xBAE4, 0x7B95, 0xBADF, 0x7B96, 0xE353, 0x7B97, 0xBAE2,
+	0x7B98, 0xE359, 0x7B99, 0xE35B, 0x7B9B, 0xE356, 0x7B9C, 0xE34F,	0x7B9D, 0xBAE3, 0x7BA0, 0xBD69, 0x7BA1, 0xBADE, 0x7BA4, 0xE35C,
+	0x7BAC, 0xE6D9, 0x7BAD, 0xBD62, 0x7BAF, 0xE6DB, 0x7BB1, 0xBD63,	0x7BB4, 0xBD65, 0x7BB5, 0xE6DE, 0x7BB7, 0xE6D6, 0x7BB8, 0xBAE6,
+	0x7BB9, 0xE6DC, 0x7BBE, 0xE6D8, 0x7BC0, 0xB860, 0x7BC1, 0xBD68,	0x7BC4, 0xBD64, 0x7BC6, 0xBD66, 0x7BC7, 0xBD67, 0x7BC9, 0xBF76,
+	0x7BCA, 0xE6DD, 0x7BCB, 0xE6D7, 0x7BCC, 0xBD6A, 0x7BCE, 0xE6DA,	0x7BD4, 0xEAC0, 0x7BD5, 0xEABB, 0x7BD8, 0xEAC5, 0x7BD9, 0xBF74,
+	0x7BDA, 0xEABD, 0x7BDB, 0xBF78, 0x7BDC, 0xEAC3, 0x7BDD, 0xEABA,	0x7BDE, 0xEAB7, 0x7BDF, 0xEAC6, 0x7BE0, 0xC151, 0x7BE1, 0xBF79,
+	0x7BE2, 0xEAC2, 0x7BE3, 0xEAB8, 0x7BE4, 0xBF77, 0x7BE5, 0xEABC,	0x7BE6, 0xBF7B, 0x7BE7, 0xEAB9, 0x7BE8, 0xEABE, 0x7BE9, 0xBF7A,
+	0x7BEA, 0xEAC1, 0x7BEB, 0xEAC4, 0x7BF0, 0xEDCB, 0x7BF1, 0xEDCC,	0x7BF2, 0xEDBC, 0x7BF3, 0xEDC3, 0x7BF4, 0xEDC1, 0x7BF7, 0xC14F,
+	0x7BF8, 0xEDC8, 0x7BF9, 0xEABF, 0x7BFB, 0xEDBF, 0x7BFD, 0xEDC9,	0x7BFE, 0xC14E, 0x7BFF, 0xEDBE, 0x7C00, 0xEDBD, 0x7C01, 0xEDC7,
+	0x7C02, 0xEDC4, 0x7C03, 0xEDC6, 0x7C05, 0xEDBA, 0x7C06, 0xEDCA,	0x7C07, 0xC14C, 0x7C09, 0xEDC5, 0x7C0A, 0xEDCE, 0x7C0B, 0xEDC2,
+	0x7C0C, 0xC150, 0x7C0D, 0xC14D, 0x7C0E, 0xEDC0, 0x7C0F, 0xEDBB,	0x7C10, 0xEDCD, 0x7C11, 0xBF75, 0x7C19, 0xF063, 0x7C1C, 0xF061,
+	0x7C1D, 0xF067, 0x7C1E, 0xC2B0, 0x7C1F, 0xF065, 0x7C20, 0xF064,	0x7C21, 0xC2B2, 0x7C22, 0xF06A, 0x7C23, 0xC2B1, 0x7C25, 0xF06B,
+	0x7C26, 0xF068, 0x7C27, 0xC2AE, 0x7C28, 0xF069, 0x7C29, 0xF062,	0x7C2A, 0xC2AF, 0x7C2B, 0xC2AD, 0x7C2C, 0xF2AB, 0x7C2D, 0xF066,
+	0x7C30, 0xF06C, 0x7C33, 0xF2A8, 0x7C37, 0xC3B2, 0x7C38, 0xC3B0,	0x7C39, 0xF2AA, 0x7C3B, 0xF2AC, 0x7C3C, 0xF2A9, 0x7C3D, 0xC3B1,
+	0x7C3E, 0xC3AE, 0x7C3F, 0xC3AF, 0x7C40, 0xC3B3, 0x7C43, 0xC478,	0x7C45, 0xF4AA, 0x7C47, 0xF4A9, 0x7C48, 0xF4A7, 0x7C49, 0xF4A6,
+	0x7C4A, 0xF4A8, 0x7C4C, 0xC477, 0x7C4D, 0xC479, 0x7C50, 0xC4F0,	0x7C53, 0xF5E5, 0x7C54, 0xF5E4, 0x7C57, 0xF6FA, 0x7C59, 0xF6FC,
+	0x7C5A, 0xF6FE, 0x7C5B, 0xF6FD, 0x7C5C, 0xF6FB, 0x7C5F, 0xC5A3,	0x7C60, 0xC5A2, 0x7C63, 0xC5D3, 0x7C64, 0xC5D2, 0x7C65, 0xC5D4,
+	0x7C66, 0xF7ED, 0x7C67, 0xF7EC, 0x7C69, 0xF8FB, 0x7C6A, 0xF8B8,	0x7C6B, 0xF8FC, 0x7C6C, 0xC658, 0x7C6E, 0xC659, 0x7C6F, 0xF96D,
+	0x7C72, 0xC67E, 0x7C73, 0xA6CC, 0x7C75, 0xCDA8, 0x7C78, 0xD045,	0x7C79, 0xD046, 0x7C7A, 0xD044, 0x7C7D, 0xACF3, 0x7C7F, 0xD047,
+	0x7C80, 0xD048, 0x7C81, 0xD049, 0x7C84, 0xD349, 0x7C85, 0xD34F,	0x7C88, 0xD34D, 0x7C89, 0xAFBB, 0x7C8A, 0xD34B, 0x7C8C, 0xD34C,
+	0x7C8D, 0xD34E, 0x7C91, 0xD34A, 0x7C92, 0xB2C9, 0x7C94, 0xD6DE,	0x7C95, 0xB2CB, 0x7C96, 0xD6E0, 0x7C97, 0xB2CA, 0x7C98, 0xD6DF,
+	0x7C9E, 0xDAE8, 0x7C9F, 0xB5AF, 0x7CA1, 0xDAEA, 0x7CA2, 0xDAE7,	0x7CA3, 0xD6E1, 0x7CA5, 0xB5B0, 0x7CA7, 0xF9DB, 0x7CA8, 0xDAE9,
+	0x7CAF, 0xDF56, 0x7CB1, 0xB864, 0x7CB2, 0xDF54, 0x7CB3, 0xB865,	0x7CB4, 0xDF55, 0x7CB5, 0xB866, 0x7CB9, 0xBAE9, 0x7CBA, 0xE361,
+	0x7CBB, 0xE35E, 0x7CBC, 0xE360, 0x7CBD, 0xBAEA, 0x7CBE, 0xBAEB,	0x7CBF, 0xE35F, 0x7CC5, 0xE6DF, 0x7CC8, 0xE6E0, 0x7CCA, 0xBD6B,
+	0x7CCB, 0xE6E2, 0x7CCC, 0xE6E1, 0x7CCE, 0xA261, 0x7CD0, 0xEACA,	0x7CD1, 0xEACB, 0x7CD2, 0xEAC7, 0x7CD4, 0xEAC8, 0x7CD5, 0xBF7C,
+	0x7CD6, 0xBF7D, 0x7CD7, 0xEAC9, 0x7CD9, 0xC157, 0x7CDC, 0xC153,	0x7CDD, 0xC158, 0x7CDE, 0xC154, 0x7CDF, 0xC156, 0x7CE0, 0xC152,
+	0x7CE2, 0xC155, 0x7CE7, 0xC2B3, 0x7CE8, 0xEDCF, 0x7CEA, 0xF2AE,	0x7CEC, 0xF2AD, 0x7CEE, 0xF4AB, 0x7CEF, 0xC47A, 0x7CF0, 0xC47B,
+	0x7CF1, 0xF741, 0x7CF2, 0xF5E6, 0x7CF4, 0xF740, 0x7CF6, 0xF8FD,	0x7CF7, 0xF9A4, 0x7CF8, 0xA6CD, 0x7CFB, 0xA874, 0x7CFD, 0xCDA9,
+	0x7CFE, 0xAAC8, 0x7D00, 0xACF6, 0x7D01, 0xD04C, 0x7D02, 0xACF4,	0x7D03, 0xD04A, 0x7D04, 0xACF9, 0x7D05, 0xACF5, 0x7D06, 0xACFA,
+	0x7D07, 0xACF8, 0x7D08, 0xD04B, 0x7D09, 0xACF7, 0x7D0A, 0xAFBF,	0x7D0B, 0xAFBE, 0x7D0C, 0xD35A, 0x7D0D, 0xAFC7, 0x7D0E, 0xD353,
+	0x7D0F, 0xD359, 0x7D10, 0xAFC3, 0x7D11, 0xD352, 0x7D12, 0xD358,	0x7D13, 0xD356, 0x7D14, 0xAFC2, 0x7D15, 0xAFC4, 0x7D16, 0xD355,
+	0x7D17, 0xAFBD, 0x7D18, 0xD354, 0x7D19, 0xAFC8, 0x7D1A, 0xAFC5,	0x7D1B, 0xAFC9, 0x7D1C, 0xAFC6, 0x7D1D, 0xD351, 0x7D1E, 0xD350,
+	0x7D1F, 0xD357, 0x7D20, 0xAFC0, 0x7D21, 0xAFBC, 0x7D22, 0xAFC1,	0x7D28, 0xD6F0, 0x7D29, 0xD6E9, 0x7D2B, 0xB5B5, 0x7D2C, 0xD6E8,
+	0x7D2E, 0xB2CF, 0x7D2F, 0xB2D6, 0x7D30, 0xB2D3, 0x7D31, 0xB2D9,	0x7D32, 0xB2D8, 0x7D33, 0xB2D4, 0x7D35, 0xD6E2, 0x7D36, 0xD6E5,
+	0x7D38, 0xD6E4, 0x7D39, 0xB2D0, 0x7D3A, 0xD6E6, 0x7D3B, 0xD6EF,	0x7D3C, 0xB2D1, 0x7D3D, 0xD6E3, 0x7D3E, 0xD6EC, 0x7D3F, 0xD6ED,
+	0x7D40, 0xB2D2, 0x7D41, 0xD6EA, 0x7D42, 0xB2D7, 0x7D43, 0xB2CD,	0x7D44, 0xB2D5, 0x7D45, 0xD6E7, 0x7D46, 0xB2CC, 0x7D47, 0xD6EB,
+	0x7D4A, 0xD6EE, 0x7D4E, 0xDAFB, 0x7D4F, 0xDAF2, 0x7D50, 0xB5B2,	0x7D51, 0xDAF9, 0x7D52, 0xDAF6, 0x7D53, 0xDAEE, 0x7D54, 0xDAF7,
+	0x7D55, 0xB5B4, 0x7D56, 0xDAEF, 0x7D58, 0xDAEB, 0x7D5B, 0xB86C,	0x7D5C, 0xDAF4, 0x7D5E, 0xB5B1, 0x7D5F, 0xDAFA, 0x7D61, 0xB5B8,
+	0x7D62, 0xB5BA, 0x7D63, 0xDAED, 0x7D66, 0xB5B9, 0x7D67, 0xDAF0,	0x7D68, 0xB5B3, 0x7D69, 0xDAF8, 0x7D6A, 0xDAF1, 0x7D6B, 0xDAF5,
+	0x7D6D, 0xDAF3, 0x7D6E, 0xB5B6, 0x7D6F, 0xDAEC, 0x7D70, 0xB5BB,	0x7D71, 0xB2CE, 0x7D72, 0xB5B7, 0x7D73, 0xB5BC, 0x7D79, 0xB868,
+	0x7D7A, 0xDF5D, 0x7D7B, 0xDF5F, 0x7D7C, 0xDF61, 0x7D7D, 0xDF65,	0x7D7F, 0xDF5B, 0x7D80, 0xDF59, 0x7D81, 0xB86A, 0x7D83, 0xDF60,
+	0x7D84, 0xDF64, 0x7D85, 0xDF5C, 0x7D86, 0xDF58, 0x7D88, 0xDF57,	0x7D8C, 0xDF62, 0x7D8D, 0xDF5A, 0x7D8E, 0xDF5E, 0x7D8F, 0xB86B,
+	0x7D91, 0xB869, 0x7D92, 0xDF66, 0x7D93, 0xB867, 0x7D94, 0xDF63,	0x7D96, 0xE372, 0x7D9C, 0xBAEE, 0x7D9D, 0xE36A, 0x7D9E, 0xBD78,
+	0x7D9F, 0xE374, 0x7DA0, 0xBAF1, 0x7DA1, 0xE378, 0x7DA2, 0xBAF7,	0x7DA3, 0xE365, 0x7DA6, 0xE375, 0x7DA7, 0xE362, 0x7DA9, 0xE377,
+	0x7DAA, 0xE366, 0x7DAC, 0xBAFE, 0x7DAD, 0xBAFB, 0x7DAE, 0xE376,	0x7DAF, 0xE370, 0x7DB0, 0xBAED, 0x7DB1, 0xBAF5, 0x7DB2, 0xBAF4,
+	0x7DB4, 0xBAF3, 0x7DB5, 0xBAF9, 0x7DB7, 0xE363, 0x7DB8, 0xBAFA,	0x7DB9, 0xE371, 0x7DBA, 0xBAF6, 0x7DBB, 0xBAEC, 0x7DBC, 0xE373,
+	0x7DBD, 0xBAEF, 0x7DBE, 0xBAF0, 0x7DBF, 0xBAF8, 0x7DC0, 0xE368,	0x7DC1, 0xE367, 0x7DC2, 0xE364, 0x7DC4, 0xE36C, 0x7DC5, 0xE369,
+	0x7DC6, 0xE36D, 0x7DC7, 0xBAFD, 0x7DC9, 0xE379, 0x7DCA, 0xBAF2,	0x7DCB, 0xE36E, 0x7DCC, 0xE36F, 0x7DCE, 0xE36B, 0x7DD2, 0xBAFC,
+	0x7DD7, 0xE6E7, 0x7DD8, 0xBD70, 0x7DD9, 0xBD79, 0x7DDA, 0xBD75,	0x7DDB, 0xE6E4, 0x7DDD, 0xBD72, 0x7DDE, 0xBD76, 0x7DDF, 0xE6F0,
+	0x7DE0, 0xBD6C, 0x7DE1, 0xE6E8, 0x7DE3, 0xBD74, 0x7DE6, 0xE6EB,	0x7DE7, 0xE6E6, 0x7DE8, 0xBD73, 0x7DE9, 0xBD77, 0x7DEA, 0xE6E5,
+	0x7DEC, 0xBD71, 0x7DEE, 0xE6EF, 0x7DEF, 0xBD6E, 0x7DF0, 0xE6EE,	0x7DF1, 0xE6ED, 0x7DF2, 0xBD7A, 0x7DF3, 0xE572, 0x7DF4, 0xBD6D,
+	0x7DF6, 0xE6EC, 0x7DF7, 0xE6E3, 0x7DF9, 0xBD7B, 0x7DFA, 0xE6EA,	0x7DFB, 0xBD6F, 0x7E03, 0xE6E9, 0x7E08, 0xBFA2, 0x7E09, 0xBFA7,
+	0x7E0A, 0xBF7E, 0x7E0B, 0xEAD8, 0x7E0C, 0xEACF, 0x7E0D, 0xEADB,	0x7E0E, 0xEAD3, 0x7E0F, 0xEAD9, 0x7E10, 0xBFA8, 0x7E11, 0xBFA1,
+	0x7E12, 0xEACC, 0x7E13, 0xEAD2, 0x7E14, 0xEADC, 0x7E15, 0xEAD5,	0x7E16, 0xEADA, 0x7E17, 0xEACE, 0x7E1A, 0xEAD6, 0x7E1B, 0xBFA3,
+	0x7E1C, 0xEAD4, 0x7E1D, 0xBFA6, 0x7E1E, 0xBFA5, 0x7E1F, 0xEAD0,	0x7E20, 0xEAD1, 0x7E21, 0xEACD, 0x7E22, 0xEAD7, 0x7E23, 0xBFA4,
+	0x7E24, 0xEADE, 0x7E25, 0xEADD, 0x7E29, 0xEDDA, 0x7E2A, 0xEDD6,	0x7E2B, 0xC15F, 0x7E2D, 0xEDD0, 0x7E2E, 0xC159, 0x7E2F, 0xC169,
+	0x7E30, 0xEDDC, 0x7E31, 0xC161, 0x7E32, 0xC15D, 0x7E33, 0xEDD3,	0x7E34, 0xC164, 0x7E35, 0xC167, 0x7E36, 0xEDDE, 0x7E37, 0xC15C,
+	0x7E38, 0xEDD5, 0x7E39, 0xC165, 0x7E3A, 0xEDE0, 0x7E3B, 0xEDDD,	0x7E3C, 0xEDD1, 0x7E3D, 0xC160, 0x7E3E, 0xC15A, 0x7E3F, 0xC168,
+	0x7E40, 0xEDD8, 0x7E41, 0xC163, 0x7E42, 0xEDD2, 0x7E43, 0xC15E,	0x7E44, 0xEDDF, 0x7E45, 0xC162, 0x7E46, 0xC15B, 0x7E47, 0xEDD9,
+	0x7E48, 0xC166, 0x7E49, 0xEDD7, 0x7E4C, 0xEDDB, 0x7E50, 0xF06E,	0x7E51, 0xF074, 0x7E52, 0xC2B9, 0x7E53, 0xF077, 0x7E54, 0xC2B4,
+	0x7E55, 0xC2B5, 0x7E56, 0xF06F, 0x7E57, 0xF076, 0x7E58, 0xF071,	0x7E59, 0xC2BA, 0x7E5A, 0xC2B7, 0x7E5C, 0xF06D, 0x7E5E, 0xC2B6,
+	0x7E5F, 0xF073, 0x7E60, 0xF075, 0x7E61, 0xC2B8, 0x7E62, 0xF072,	0x7E63, 0xF070, 0x7E68, 0xF2B8, 0x7E69, 0xC3B7, 0x7E6A, 0xC3B8,
+	0x7E6B, 0xC3B4, 0x7E6D, 0xC3B5, 0x7E6F, 0xF2B4, 0x7E70, 0xF2B2,	0x7E72, 0xF2B6, 0x7E73, 0xC3BA, 0x7E74, 0xF2B7, 0x7E75, 0xF2B0,
+	0x7E76, 0xF2AF, 0x7E77, 0xF2B3, 0x7E78, 0xF2B1, 0x7E79, 0xC3B6,	0x7E7A, 0xF2B5, 0x7E7B, 0xF4AC, 0x7E7C, 0xC47E, 0x7E7D, 0xC47D,
+	0x7E7E, 0xF4AD, 0x7E80, 0xF4AF, 0x7E81, 0xF4AE, 0x7E82, 0xC4A1,	0x7E86, 0xF5EB, 0x7E87, 0xF5E8, 0x7E88, 0xF5E9, 0x7E8A, 0xF5E7,
+	0x7E8B, 0xF5EA, 0x7E8C, 0xC4F2, 0x7E8D, 0xF5EC, 0x7E8F, 0xC4F1,	0x7E91, 0xF742, 0x7E93, 0xC5D5, 0x7E94, 0xC5D7, 0x7E95, 0xF7EE,
+	0x7E96, 0xC5D6, 0x7E97, 0xF8B9, 0x7E98, 0xF940, 0x7E99, 0xF942,	0x7E9A, 0xF8FE, 0x7E9B, 0xF941, 0x7E9C, 0xC66C, 0x7F36, 0xA6CE,
+	0x7F38, 0xACFB, 0x7F39, 0xD26F, 0x7F3A, 0xAFCA, 0x7F3D, 0xB2DA,	0x7F3E, 0xDAFC, 0x7F3F, 0xDAFD, 0x7F43, 0xEADF, 0x7F44, 0xC16A,
+	0x7F45, 0xEDE1, 0x7F48, 0xC2BB, 0x7F4A, 0xF2BA, 0x7F4B, 0xF2B9,	0x7F4C, 0xC4A2, 0x7F4D, 0xF5ED, 0x7F4F, 0xF743, 0x7F50, 0xC5F8,
+	0x7F51, 0xCA49, 0x7F54, 0xAAC9, 0x7F55, 0xA875, 0x7F58, 0xD04D,	0x7F5B, 0xD360, 0x7F5C, 0xD35B, 0x7F5D, 0xD35F, 0x7F5E, 0xD35D,
+	0x7F5F, 0xAFCB, 0x7F60, 0xD35E, 0x7F61, 0xD35C, 0x7F63, 0xD6F1,	0x7F65, 0xDAFE, 0x7F66, 0xDB40, 0x7F67, 0xDF69, 0x7F68, 0xDF6A,
+	0x7F69, 0xB86E, 0x7F6A, 0xB86F, 0x7F6B, 0xDF68, 0x7F6C, 0xDF6B,	0x7F6D, 0xDF67, 0x7F6E, 0xB86D, 0x7F70, 0xBB40, 0x7F72, 0xB870,
+	0x7F73, 0xE37A, 0x7F75, 0xBD7C, 0x7F76, 0xE6F1, 0x7F77, 0xBD7D,	0x7F79, 0xBFA9, 0x7F7A, 0xEAE2, 0x7F7B, 0xEAE0, 0x7F7C, 0xEAE1,
+	0x7F7D, 0xEDE4, 0x7F7E, 0xEDE3, 0x7F7F, 0xEDE2, 0x7F83, 0xF2BB,	0x7F85, 0xC3B9, 0x7F86, 0xF2BC, 0x7F87, 0xF744, 0x7F88, 0xC5F9,
+	0x7F89, 0xF8BA, 0x7F8A, 0xA6CF, 0x7F8B, 0xAACB, 0x7F8C, 0xAACA,	0x7F8D, 0xD04F, 0x7F8E, 0xACFC, 0x7F91, 0xD04E, 0x7F92, 0xD362,
+	0x7F94, 0xAFCC, 0x7F95, 0xD6F2, 0x7F96, 0xD361, 0x7F9A, 0xB2DC,	0x7F9B, 0xD6F5, 0x7F9C, 0xD6F3, 0x7F9D, 0xD6F4, 0x7F9E, 0xB2DB,
+	0x7FA0, 0xDB42, 0x7FA1, 0xDB43, 0x7FA2, 0xDB41, 0x7FA4, 0xB873,	0x7FA5, 0xDF6D, 0x7FA6, 0xDF6C, 0x7FA7, 0xDF6E, 0x7FA8, 0xB872,
+	0x7FA9, 0xB871, 0x7FAC, 0xE6F2, 0x7FAD, 0xE6F4, 0x7FAF, 0xBD7E,	0x7FB0, 0xE6F3, 0x7FB1, 0xEAE3, 0x7FB2, 0xBFAA, 0x7FB3, 0xF079,
+	0x7FB5, 0xF078, 0x7FB6, 0xC3BB, 0x7FB7, 0xF2BD, 0x7FB8, 0xC3BD,	0x7FB9, 0xC3BC, 0x7FBA, 0xF4B0, 0x7FBB, 0xF5EE, 0x7FBC, 0xC4F3,
+	0x7FBD, 0xA6D0, 0x7FBE, 0xD050, 0x7FBF, 0xACFD, 0x7FC0, 0xD365,	0x7FC1, 0xAFCE, 0x7FC2, 0xD364, 0x7FC3, 0xD363, 0x7FC5, 0xAFCD,
+	0x7FC7, 0xD6FB, 0x7FC9, 0xD6FD, 0x7FCA, 0xD6F6, 0x7FCB, 0xD6F7,	0x7FCC, 0xB2DD, 0x7FCD, 0xD6F8, 0x7FCE, 0xB2DE, 0x7FCF, 0xD6FC,
+	0x7FD0, 0xD6F9, 0x7FD1, 0xD6FA, 0x7FD2, 0xB2DF, 0x7FD4, 0xB5BE,	0x7FD5, 0xB5BF, 0x7FD7, 0xDB44, 0x7FDB, 0xDF6F, 0x7FDC, 0xDF70,
+	0x7FDE, 0xE37E, 0x7FDF, 0xBB43, 0x7FE0, 0xBB41, 0x7FE1, 0xBB42,	0x7FE2, 0xE37B, 0x7FE3, 0xE37C, 0x7FE5, 0xE37D, 0x7FE6, 0xE6F9,
+	0x7FE8, 0xE6FA, 0x7FE9, 0xBDA1, 0x7FEA, 0xE6F7, 0x7FEB, 0xE6F6,	0x7FEC, 0xE6F8, 0x7FED, 0xE6F5, 0x7FEE, 0xBFAD, 0x7FEF, 0xEAE4,
+	0x7FF0, 0xBFAB, 0x7FF1, 0xBFAC, 0x7FF2, 0xEDE6, 0x7FF3, 0xC16B,	0x7FF4, 0xEDE5, 0x7FF5, 0xEFA8, 0x7FF7, 0xF07A, 0x7FF8, 0xF07B,
+	0x7FF9, 0xC2BC, 0x7FFB, 0xC2BD, 0x7FFC, 0xC16C, 0x7FFD, 0xF2BE,	0x7FFE, 0xF2BF, 0x7FFF, 0xF4B1, 0x8000, 0xC4A3, 0x8001, 0xA6D1,
+	0x8003, 0xA6D2, 0x8004, 0xACFE, 0x8005, 0xAACC, 0x8006, 0xAFCF,	0x8007, 0xD051, 0x800B, 0xB5C0, 0x800C, 0xA6D3, 0x800D, 0xAD41,
+	0x800E, 0xD052, 0x800F, 0xD053, 0x8010, 0xAD40, 0x8011, 0xAD42,	0x8012, 0xA6D4, 0x8014, 0xD054, 0x8015, 0xAFD1, 0x8016, 0xD366,
+	0x8017, 0xAFD3, 0x8018, 0xAFD0, 0x8019, 0xAFD2, 0x801B, 0xD741,	0x801C, 0xB2E0, 0x801E, 0xD740, 0x801F, 0xD6FE, 0x8021, 0xDF71,
+	0x8024, 0xE3A1, 0x8026, 0xBDA2, 0x8028, 0xBFAE, 0x8029, 0xEAE6,	0x802A, 0xEAE5, 0x802C, 0xEDE7, 0x8030, 0xF5EF, 0x8033, 0xA6D5,
+	0x8034, 0xCB73, 0x8035, 0xCDAA, 0x8036, 0xAD43, 0x8037, 0xD055,	0x8039, 0xD368, 0x803D, 0xAFD4, 0x803E, 0xD367, 0x803F, 0xAFD5,
+	0x8043, 0xD743, 0x8046, 0xB2E2, 0x8047, 0xD742, 0x8048, 0xD744,	0x804A, 0xB2E1, 0x804F, 0xDB46, 0x8050, 0xDB47, 0x8051, 0xDB45,
+	0x8052, 0xB5C1, 0x8056, 0xB874, 0x8058, 0xB875, 0x805A, 0xBB45,	0x805C, 0xE3A3, 0x805D, 0xE3A2, 0x805E, 0xBB44, 0x8064, 0xE6FB,
+	0x8067, 0xE6FC, 0x806C, 0xEAE7, 0x806F, 0xC170, 0x8070, 0xC16F,	0x8071, 0xC16D, 0x8072, 0xC16E, 0x8073, 0xC171, 0x8075, 0xF07C,
+	0x8076, 0xC2BF, 0x8077, 0xC2BE, 0x8078, 0xF2C0, 0x8079, 0xF4B2,	0x807D, 0xC5A5, 0x807E, 0xC5A4, 0x807F, 0xA6D6, 0x8082, 0xD1FB,
+	0x8084, 0xB877, 0x8085, 0xB5C2, 0x8086, 0xB876, 0x8087, 0xBB46,	0x8089, 0xA6D7, 0x808A, 0xC9A9, 0x808B, 0xA6D8, 0x808C, 0xA6D9,
+	0x808F, 0xCDAB, 0x8090, 0xCB76, 0x8092, 0xCB77, 0x8093, 0xA877,	0x8095, 0xCB74, 0x8096, 0xA876, 0x8098, 0xA879, 0x8099, 0xCB75,
+	0x809A, 0xA87B, 0x809B, 0xA87A, 0x809C, 0xCB78, 0x809D, 0xA878,	0x80A1, 0xAAD1, 0x80A2, 0xAACF, 0x80A3, 0xCDAD, 0x80A5, 0xAACE,
+	0x80A9, 0xAAD3, 0x80AA, 0xAAD5, 0x80AB, 0xAAD2, 0x80AD, 0xCDB0,	0x80AE, 0xCDAC, 0x80AF, 0xAAD6, 0x80B1, 0xAAD0, 0x80B2, 0xA87C,
+	0x80B4, 0xAAD4, 0x80B5, 0xCDAF, 0x80B8, 0xCDAE, 0x80BA, 0xAACD,	0x80C2, 0xD05B, 0x80C3, 0xAD47, 0x80C4, 0xAD48, 0x80C5, 0xD05D,
+	0x80C7, 0xD057, 0x80C8, 0xD05A, 0x80C9, 0xD063, 0x80CA, 0xD061,	0x80CC, 0xAD49, 0x80CD, 0xD067, 0x80CE, 0xAD4C, 0x80CF, 0xD064,
+	0x80D0, 0xD05C, 0x80D1, 0xD059, 0x80D4, 0xDB49, 0x80D5, 0xD062,	0x80D6, 0xAD44, 0x80D7, 0xD065, 0x80D8, 0xD056, 0x80D9, 0xD05F,
+	0x80DA, 0xAD46, 0x80DB, 0xAD4B, 0x80DC, 0xD060, 0x80DD, 0xAD4F,	0x80DE, 0xAD4D, 0x80E0, 0xD058, 0x80E1, 0xAD4A, 0x80E3, 0xD05E,
+	0x80E4, 0xAD4E, 0x80E5, 0xAD45, 0x80E6, 0xD066, 0x80ED, 0xAFDA,	0x80EF, 0xAFE3, 0x80F0, 0xAFD8, 0x80F1, 0xAFD6, 0x80F2, 0xD36A,
+	0x80F3, 0xAFDE, 0x80F4, 0xAFDB, 0x80F5, 0xD36C, 0x80F8, 0xAFDD,	0x80F9, 0xD36B, 0x80FA, 0xD369, 0x80FB, 0xD36E, 0x80FC, 0xAFE2,
+	0x80FD, 0xAFE0, 0x80FE, 0xDB48, 0x8100, 0xD36F, 0x8101, 0xD36D,	0x8102, 0xAFD7, 0x8105, 0xAFD9, 0x8106, 0xAFDC, 0x8108, 0xAFDF,
+	0x810A, 0xAFE1, 0x8115, 0xD74E, 0x8116, 0xB2E4, 0x8118, 0xD745,	0x8119, 0xD747, 0x811B, 0xD748, 0x811D, 0xD750, 0x811E, 0xD74C,
+	0x811F, 0xD74A, 0x8121, 0xD74D, 0x8122, 0xD751, 0x8123, 0xB2E5,	0x8124, 0xB2E9, 0x8125, 0xD746, 0x8127, 0xD74F, 0x8129, 0xB2E7,
+	0x812B, 0xB2E6, 0x812C, 0xD74B, 0x812D, 0xD749, 0x812F, 0xB2E3,	0x8130, 0xB2E8, 0x8139, 0xB5C8, 0x813A, 0xDB51, 0x813D, 0xDB4F,
+	0x813E, 0xB5CA, 0x8143, 0xDB4A, 0x8144, 0xDFA1, 0x8146, 0xB5C9,	0x8147, 0xDB4E, 0x814A, 0xDB4B, 0x814B, 0xB5C5, 0x814C, 0xB5CB,
+	0x814D, 0xDB50, 0x814E, 0xB5C7, 0x814F, 0xDB4D, 0x8150, 0xBB47,	0x8151, 0xB5C6, 0x8152, 0xDB4C, 0x8153, 0xB5CC, 0x8154, 0xB5C4,
+	0x8155, 0xB5C3, 0x815B, 0xDF77, 0x815C, 0xDF75, 0x815E, 0xDF7B,	0x8160, 0xDF73, 0x8161, 0xDFA2, 0x8162, 0xDF78, 0x8164, 0xDF72,
+	0x8165, 0xB87B, 0x8166, 0xB8A3, 0x8167, 0xDF7D, 0x8169, 0xDF76,	0x816B, 0xB87E, 0x816E, 0xB87C, 0x816F, 0xDF7E, 0x8170, 0xB879,
+	0x8171, 0xB878, 0x8172, 0xDF79, 0x8173, 0xB87D, 0x8174, 0xB5CD,	0x8176, 0xDF7C, 0x8177, 0xDF74, 0x8178, 0xB87A, 0x8179, 0xB8A1,
+	0x817A, 0xB8A2, 0x817F, 0xBB4C, 0x8180, 0xBB48, 0x8182, 0xBB4D,	0x8183, 0xE3A6, 0x8186, 0xE3A5, 0x8187, 0xE3A7, 0x8188, 0xBB4A,
+	0x8189, 0xE3A4, 0x818A, 0xBB4B, 0x818B, 0xE3AA, 0x818C, 0xE3A9,	0x818D, 0xE3A8, 0x818F, 0xBB49, 0x8195, 0xE741, 0x8197, 0xE744,
+	0x8198, 0xBDA8, 0x8199, 0xE743, 0x819A, 0xBDA7, 0x819B, 0xBDA3,	0x819C, 0xBDA4, 0x819D, 0xBDA5, 0x819E, 0xE740, 0x819F, 0xE6FE,
+	0x81A0, 0xBDA6, 0x81A2, 0xE742, 0x81A3, 0xE6FD, 0x81A6, 0xEAE9,	0x81A7, 0xEAF3, 0x81A8, 0xBFB1, 0x81A9, 0xBFB0, 0x81AB, 0xEAED,
+	0x81AC, 0xEAEF, 0x81AE, 0xEAEA, 0x81B0, 0xEAEE, 0x81B1, 0xEAE8,	0x81B2, 0xEAF1, 0x81B3, 0xBFAF, 0x81B4, 0xEAF0, 0x81B5, 0xEAEC,
+	0x81B7, 0xEAF2, 0x81B9, 0xEAEB, 0x81BA, 0xC174, 0x81BB, 0xEDE8,	0x81BC, 0xEDEE, 0x81BD, 0xC178, 0x81BE, 0xC17A, 0x81BF, 0xC177,
+	0x81C0, 0xC176, 0x81C2, 0xC175, 0x81C3, 0xC173, 0x81C4, 0xEDE9,	0x81C5, 0xEDEC, 0x81C6, 0xC172, 0x81C7, 0xEDED, 0x81C9, 0xC179,
+	0x81CA, 0xEDEB, 0x81CC, 0xEDEA, 0x81CD, 0xC2C0, 0x81CF, 0xC2C1,	0x81D0, 0xF0A1, 0x81D1, 0xF07D, 0x81D2, 0xF07E, 0x81D5, 0xF2C2,
+	0x81D7, 0xF2C1, 0x81D8, 0xC3BE, 0x81D9, 0xF4B4, 0x81DA, 0xC4A4,	0x81DB, 0xF4B3, 0x81DD, 0xF5F0, 0x81DE, 0xF745, 0x81DF, 0xC5A6,
+	0x81E0, 0xF943, 0x81E1, 0xF944, 0x81E2, 0xC5D8, 0x81E3, 0xA6DA,	0x81E5, 0xAAD7, 0x81E6, 0xDB52, 0x81E7, 0xBB4E, 0x81E8, 0xC17B,
+	0x81E9, 0xEDEF, 0x81EA, 0xA6DB, 0x81EC, 0xAFE5, 0x81ED, 0xAFE4,	0x81EE, 0xDB53, 0x81F2, 0xEAF4, 0x81F3, 0xA6DC, 0x81F4, 0xAD50,
+	0x81F7, 0xDB54, 0x81F8, 0xDB55, 0x81F9, 0xDB56, 0x81FA, 0xBB4F,	0x81FB, 0xBFB2, 0x81FC, 0xA6DD, 0x81FE, 0xAAD8, 0x81FF, 0xD068,
+	0x8200, 0xAFE6, 0x8201, 0xD370, 0x8202, 0xB2EA, 0x8204, 0xDB57,	0x8205, 0xB8A4, 0x8207, 0xBB50, 0x8208, 0xBFB3, 0x8209, 0xC17C,
+	0x820A, 0xC2C2, 0x820B, 0xF4B5, 0x820C, 0xA6DE, 0x820D, 0xAAD9,	0x8210, 0xAFE7, 0x8211, 0xD752, 0x8212, 0xB5CE, 0x8214, 0xBB51,
+	0x8215, 0xE3AB, 0x8216, 0xE745, 0x821B, 0xA6DF, 0x821C, 0xB5CF,	0x821D, 0xDFA3, 0x821E, 0xBB52, 0x821F, 0xA6E0, 0x8220, 0xCDB1,
+	0x8221, 0xD069, 0x8222, 0xAD51, 0x8225, 0xD372, 0x8228, 0xAFEA,	0x822A, 0xAFE8, 0x822B, 0xAFE9, 0x822C, 0xAFEB, 0x822F, 0xD371,
+	0x8232, 0xD757, 0x8233, 0xD754, 0x8234, 0xD756, 0x8235, 0xB2EB,	0x8236, 0xB2ED, 0x8237, 0xB2EC, 0x8238, 0xD753, 0x8239, 0xB2EE,
+	0x823A, 0xD755, 0x823C, 0xDB58, 0x823D, 0xDB59, 0x823F, 0xDB5A,	0x8240, 0xDFA6, 0x8242, 0xDFA7, 0x8244, 0xDFA5, 0x8245, 0xDFA8,
+	0x8247, 0xB8A5, 0x8249, 0xDFA4, 0x824B, 0xBB53, 0x824E, 0xE74A,	0x824F, 0xE746, 0x8250, 0xE749, 0x8251, 0xE74B, 0x8252, 0xE748,
+	0x8253, 0xE747, 0x8255, 0xEAF5, 0x8256, 0xEAF6, 0x8257, 0xEAF7,	0x8258, 0xBFB4, 0x8259, 0xBFB5, 0x825A, 0xEDF1, 0x825B, 0xEDF0,
+	0x825C, 0xEDF2, 0x825E, 0xF0A3, 0x825F, 0xF0A2, 0x8261, 0xF2C4,	0x8263, 0xF2C5, 0x8264, 0xF2C3, 0x8266, 0xC4A5, 0x8268, 0xF4B6,
+	0x8269, 0xF4B7, 0x826B, 0xF746, 0x826C, 0xF7EF, 0x826D, 0xF8BB,	0x826E, 0xA6E1, 0x826F, 0xA87D, 0x8271, 0xC17D, 0x8272, 0xA6E2,
+	0x8274, 0xD758, 0x8275, 0xDB5B, 0x8277, 0xC641, 0x8278, 0xCA4A,	0x827C, 0xCA4B, 0x827D, 0xCA4D, 0x827E, 0xA6E3, 0x827F, 0xCA4E,
+	0x8280, 0xCA4C, 0x8283, 0xCBA2, 0x8284, 0xCBA3, 0x8285, 0xCB7B,	0x828A, 0xCBA1, 0x828B, 0xA8A1, 0x828D, 0xA8A2, 0x828E, 0xCB7C,
+	0x828F, 0xCB7A, 0x8290, 0xCB79, 0x8291, 0xCB7D, 0x8292, 0xA87E,	0x8293, 0xCB7E, 0x8294, 0xD06A, 0x8298, 0xCDB6, 0x8299, 0xAADC,
+	0x829A, 0xCDB5, 0x829B, 0xCDB7, 0x829D, 0xAADB, 0x829E, 0xCDBC,	0x829F, 0xAADF, 0x82A0, 0xCDB2, 0x82A1, 0xCDC0, 0x82A2, 0xCDC6,
+	0x82A3, 0xAAE6, 0x82A4, 0xCDC3, 0x82A5, 0xAAE3, 0x82A7, 0xCDB9,	0x82A8, 0xCDBF, 0x82A9, 0xCDC1, 0x82AB, 0xCDB4, 0x82AC, 0xAAE2,
+	0x82AD, 0xAADD, 0x82AE, 0xCDBA, 0x82AF, 0xAAE4, 0x82B0, 0xAAE7,	0x82B1, 0xAAE1, 0x82B3, 0xAADA, 0x82B4, 0xCDBE, 0x82B5, 0xCDB8,
+	0x82B6, 0xCDC5, 0x82B7, 0xAAE9, 0x82B8, 0xAAE5, 0x82B9, 0xAAE0,	0x82BA, 0xCDBD, 0x82BB, 0xAFEC, 0x82BC, 0xCDBB, 0x82BD, 0xAADE,
+	0x82BE, 0xAAE8, 0x82C0, 0xCDB3, 0x82C2, 0xCDC2, 0x82C3, 0xCDC4,	0x82D1, 0xAD62, 0x82D2, 0xAD5C, 0x82D3, 0xAD64, 0x82D4, 0xAD61,
+	0x82D5, 0xD071, 0x82D6, 0xD074, 0x82D7, 0xAD5D, 0x82D9, 0xD06B,	0x82DB, 0xAD56, 0x82DC, 0xAD60, 0x82DE, 0xAD63, 0x82DF, 0xAD65,
+	0x82E0, 0xD0A2, 0x82E1, 0xD077, 0x82E3, 0xAD55, 0x82E4, 0xD0A1,	0x82E5, 0xAD59, 0x82E6, 0xAD57, 0x82E7, 0xAD52, 0x82E8, 0xD06F,
+	0x82EA, 0xD07E, 0x82EB, 0xD073, 0x82EC, 0xD076, 0x82ED, 0xD0A5,	0x82EF, 0xAD66, 0x82F0, 0xD07D, 0x82F1, 0xAD5E, 0x82F2, 0xD078,
+	0x82F3, 0xD0A4, 0x82F4, 0xD075, 0x82F5, 0xD079, 0x82F6, 0xD07C,	0x82F9, 0xD06D, 0x82FA, 0xD0A3, 0x82FB, 0xD07B, 0x82FE, 0xD06C,
+	0x8300, 0xD070, 0x8301, 0xAD5F, 0x8302, 0xAD5A, 0x8303, 0xAD53,	0x8304, 0xAD58, 0x8305, 0xAD54, 0x8306, 0xAD67, 0x8307, 0xD06E,
+	0x8308, 0xD3A5, 0x8309, 0xAD5B, 0x830C, 0xD07A, 0x830D, 0xCE41,	0x8316, 0xD3A8, 0x8317, 0xAFFA, 0x8319, 0xD376, 0x831B, 0xD3A3,
+	0x831C, 0xD37D, 0x831E, 0xD3B2, 0x8320, 0xD3AA, 0x8322, 0xD37E,	0x8324, 0xD3A9, 0x8325, 0xD378, 0x8326, 0xD37C, 0x8327, 0xD3B5,
+	0x8328, 0xAFFD, 0x8329, 0xD3AD, 0x832A, 0xD3A4, 0x832B, 0xAFED,	0x832C, 0xD3B3, 0x832D, 0xD374, 0x832F, 0xD3AC, 0x8331, 0xAFFC,
+	0x8332, 0xAFF7, 0x8333, 0xD373, 0x8334, 0xAFF5, 0x8335, 0xAFF4,	0x8336, 0xAFF9, 0x8337, 0xD3AB, 0x8338, 0xAFF1, 0x8339, 0xAFF8,
+	0x833A, 0xD072, 0x833B, 0xDB5C, 0x833C, 0xD3A6, 0x833F, 0xD37A,	0x8340, 0xAFFB, 0x8341, 0xD37B, 0x8342, 0xD3A1, 0x8343, 0xAFFE,
+	0x8344, 0xD375, 0x8345, 0xD3AF, 0x8347, 0xD3AE, 0x8348, 0xD3B6,	0x8349, 0xAFF3, 0x834A, 0xAFF0, 0x834B, 0xD3B4, 0x834C, 0xD3B0,
+	0x834D, 0xD3A7, 0x834E, 0xD3A2, 0x834F, 0xAFF6, 0x8350, 0xAFF2,	0x8351, 0xD377, 0x8352, 0xAFEE, 0x8353, 0xD3B1, 0x8354, 0xAFEF,
+	0x8356, 0xD379, 0x8373, 0xD75E, 0x8374, 0xD760, 0x8375, 0xD765,	0x8376, 0xD779, 0x8377, 0xB2FC, 0x8378, 0xB2F2, 0x837A, 0xD75D,
+	0x837B, 0xB2FD, 0x837C, 0xB2FE, 0x837D, 0xD768, 0x837E, 0xD76F,	0x837F, 0xD775, 0x8381, 0xD762, 0x8383, 0xD769, 0x8386, 0xB340,
+	0x8387, 0xD777, 0x8388, 0xD772, 0x8389, 0xB2FA, 0x838A, 0xB2F8,	0x838B, 0xD76E, 0x838C, 0xD76A, 0x838D, 0xD75C, 0x838E, 0xB2EF,
+	0x838F, 0xD761, 0x8390, 0xD759, 0x8392, 0xB2F7, 0x8393, 0xB2F9,	0x8394, 0xD766, 0x8395, 0xD763, 0x8396, 0xB2F4, 0x8397, 0xD773,
+	0x8398, 0xB2F1, 0x8399, 0xD764, 0x839A, 0xD77A, 0x839B, 0xD76C,	0x839D, 0xD76B, 0x839E, 0xB2F0, 0x83A0, 0xB2FB, 0x83A2, 0xB2F3,
+	0x83A3, 0xD75A, 0x83A4, 0xD75F, 0x83A5, 0xD770, 0x83A6, 0xD776,	0x83A7, 0xB341, 0x83A8, 0xD75B, 0x83A9, 0xD767, 0x83AA, 0xD76D,
+	0x83AB, 0xB2F6, 0x83AE, 0xD778, 0x83AF, 0xD771, 0x83B0, 0xD774,	0x83BD, 0xB2F5, 0x83BF, 0xDB6C, 0x83C0, 0xDB60, 0x83C1, 0xB5D7,
+	0x83C2, 0xDB7D, 0x83C3, 0xDBA7, 0x83C4, 0xDBAA, 0x83C5, 0xB5D5,	0x83C6, 0xDB68, 0x83C7, 0xDBA3, 0x83C8, 0xDB69, 0x83C9, 0xDB77,
+	0x83CA, 0xB5E2, 0x83CB, 0xDB73, 0x83CC, 0xB5DF, 0x83CE, 0xDB74,	0x83CF, 0xDB5D, 0x83D1, 0xDBA4, 0x83D4, 0xB5E8, 0x83D5, 0xDBA1,
+	0x83D6, 0xDB75, 0x83D7, 0xDBAC, 0x83D8, 0xDB70, 0x83D9, 0xDFC8,	0x83DB, 0xDBAF, 0x83DC, 0xB5E6, 0x83DD, 0xDB6E, 0x83DE, 0xDB7A,
+	0x83DF, 0xB5E9, 0x83E0, 0xB5D4, 0x83E1, 0xDB72, 0x83E2, 0xDBAD,	0x83E3, 0xDB6B, 0x83E4, 0xDB64, 0x83E5, 0xDB6F, 0x83E7, 0xDB63,
+	0x83E8, 0xDB61, 0x83E9, 0xB5D0, 0x83EA, 0xDBA5, 0x83EB, 0xDB6A,	0x83EC, 0xDBA8, 0x83EE, 0xDBA9, 0x83EF, 0xB5D8, 0x83F0, 0xB5DD,
+	0x83F1, 0xB5D9, 0x83F2, 0xB5E1, 0x83F3, 0xDB7E, 0x83F4, 0xB5DA,	0x83F5, 0xDB76, 0x83F6, 0xDB66, 0x83F8, 0xB5D2, 0x83F9, 0xDB5E,
+	0x83FA, 0xDBA2, 0x83FB, 0xDBAB, 0x83FC, 0xDB65, 0x83FD, 0xB5E0,	0x83FE, 0xDBB0, 0x83FF, 0xDB71, 0x8401, 0xDB6D, 0x8403, 0xB5D1,
+	0x8404, 0xB5E5, 0x8406, 0xDB7C, 0x8407, 0xB5E7, 0x8409, 0xDB78,	0x840A, 0xB5DC, 0x840B, 0xB5D6, 0x840C, 0xB5DE, 0x840D, 0xB5D3,
+	0x840E, 0xB5E4, 0x840F, 0xDB79, 0x8410, 0xDB67, 0x8411, 0xDB7B,	0x8412, 0xDB62, 0x8413, 0xDBA6, 0x841B, 0xDBAE, 0x8423, 0xDB5F,
+	0x8429, 0xDFC7, 0x842B, 0xDFDD, 0x842C, 0xB855, 0x842D, 0xDFCC,	0x842F, 0xDFCA, 0x8430, 0xDFB5, 0x8431, 0xB8A9, 0x8432, 0xDFC5,
+	0x8433, 0xDFD9, 0x8434, 0xDFC1, 0x8435, 0xB8B1, 0x8436, 0xDFD8,	0x8437, 0xDFBF, 0x8438, 0xB5E3, 0x8439, 0xDFCF, 0x843A, 0xDFC0,
+	0x843B, 0xDFD6, 0x843C, 0xB8B0, 0x843D, 0xB8A8, 0x843F, 0xDFAA,	0x8440, 0xDFB2, 0x8442, 0xDFCB, 0x8443, 0xDFC3, 0x8444, 0xDFDC,
+	0x8445, 0xDFC6, 0x8446, 0xB8B6, 0x8447, 0xDFD7, 0x8449, 0xB8AD,	0x844B, 0xDFC9, 0x844C, 0xDFD1, 0x844D, 0xDFB6, 0x844E, 0xDFD0,
+	0x8450, 0xDFE1, 0x8451, 0xDFB1, 0x8452, 0xDFD2, 0x8454, 0xDFDF,	0x8456, 0xDFAB, 0x8457, 0xB5DB, 0x8459, 0xDFB9, 0x845A, 0xDFB8,
+	0x845B, 0xB8AF, 0x845D, 0xDFBC, 0x845E, 0xDFBE, 0x845F, 0xDFCD,	0x8460, 0xDFDE, 0x8461, 0xB8B2, 0x8463, 0xB8B3, 0x8465, 0xDFB0,
+	0x8466, 0xB8AB, 0x8467, 0xDFB4, 0x8468, 0xDFDA, 0x8469, 0xB8B4,	0x846B, 0xB8AC, 0x846C, 0xB8AE, 0x846D, 0xB8B5, 0x846E, 0xDFE0,
+	0x846F, 0xDFD3, 0x8470, 0xDFCE, 0x8473, 0xDFBB, 0x8474, 0xDFBA,	0x8475, 0xB8AA, 0x8476, 0xDFAC, 0x8477, 0xB8A7, 0x8478, 0xDFC4,
+	0x8479, 0xDFAD, 0x847A, 0xDFC2, 0x847D, 0xDFB7, 0x847E, 0xDFDB,	0x8482, 0xB8A6, 0x8486, 0xDFB3, 0x848D, 0xDFAF, 0x848E, 0xDFD5,
+	0x848F, 0xDFAE, 0x8490, 0xBB60, 0x8491, 0xE3D3, 0x8494, 0xE3C2,	0x8497, 0xE3AC, 0x8498, 0xE3CA, 0x8499, 0xBB58, 0x849A, 0xE3BB,
+	0x849B, 0xE3C5, 0x849C, 0xBB5B, 0x849D, 0xE3BE, 0x849E, 0xBB59,	0x849F, 0xE3AF, 0x84A0, 0xE3CD, 0x84A1, 0xE3AE, 0x84A2, 0xE3C1,
+	0x84A4, 0xE3AD, 0x84A7, 0xE3BF, 0x84A8, 0xE3C8, 0x84A9, 0xE3C6,	0x84AA, 0xE3BA, 0x84AB, 0xE3B5, 0x84AC, 0xE3B3, 0x84AE, 0xE3B4,
+	0x84AF, 0xE3C7, 0x84B0, 0xE3D2, 0x84B1, 0xE3BC, 0x84B2, 0xBB5A,	0x84B4, 0xE3B7, 0x84B6, 0xE3CB, 0x84B8, 0xBB5D, 0x84B9, 0xE3B6,
+	0x84BA, 0xE3B0, 0x84BB, 0xE3C0, 0x84BC, 0xBB61, 0x84BF, 0xBB55,	0x84C0, 0xBB5E, 0x84C1, 0xE3B8, 0x84C2, 0xE3B2, 0x84C4, 0xBB57,
+	0x84C5, 0xDFD4, 0x84C6, 0xBB56, 0x84C7, 0xE3C3, 0x84C9, 0xBB54,	0x84CA, 0xBB63, 0x84CB, 0xBB5C, 0x84CC, 0xE3C4, 0x84CD, 0xE3B9,
+	0x84CE, 0xE3B1, 0x84CF, 0xE3CC, 0x84D0, 0xE3BD, 0x84D1, 0xBB62,	0x84D2, 0xE3D0, 0x84D3, 0xBB5F, 0x84D4, 0xE3CF, 0x84D6, 0xE3C9,
+	0x84D7, 0xE3CE, 0x84DB, 0xE3D1, 0x84E7, 0xE773, 0x84E8, 0xE774,	0x84E9, 0xE767, 0x84EA, 0xE766, 0x84EB, 0xE762, 0x84EC, 0xBDB4,
+	0x84EE, 0xBDAC, 0x84EF, 0xE776, 0x84F0, 0xE775, 0x84F1, 0xDFA9,	0x84F2, 0xE75F, 0x84F3, 0xE763, 0x84F4, 0xE75D, 0x84F6, 0xE770,
+	0x84F7, 0xE761, 0x84F9, 0xE777, 0x84FA, 0xE75A, 0x84FB, 0xE758,	0x84FC, 0xE764, 0x84FD, 0xE76E, 0x84FE, 0xE769, 0x84FF, 0xBDB6,
+	0x8500, 0xE74F, 0x8502, 0xE76D, 0x8506, 0xBDB7, 0x8507, 0xDFBD,	0x8508, 0xE75B, 0x8509, 0xE752, 0x850A, 0xE755, 0x850B, 0xE77B,
+	0x850C, 0xE75C, 0x850D, 0xE753, 0x850E, 0xE751, 0x850F, 0xE74E,	0x8511, 0xBDB0, 0x8512, 0xE765, 0x8513, 0xBDAF, 0x8514, 0xBDB3,
+	0x8515, 0xE760, 0x8516, 0xE768, 0x8517, 0xBDA9, 0x8518, 0xE778,	0x8519, 0xE77C, 0x851A, 0xBDAB, 0x851C, 0xE757, 0x851D, 0xE76B,
+	0x851E, 0xE76F, 0x851F, 0xE754, 0x8520, 0xE779, 0x8521, 0xBDB2,	0x8523, 0xBDB1, 0x8524, 0xE74C, 0x8525, 0xBDB5, 0x8526, 0xE772,
+	0x8527, 0xE756, 0x8528, 0xE76A, 0x8529, 0xE750, 0x852A, 0xE75E,	0x852B, 0xE759, 0x852C, 0xBDAD, 0x852D, 0xBDAE, 0x852E, 0xE76C,
+	0x852F, 0xE77D, 0x8530, 0xE77A, 0x8531, 0xE771, 0x853B, 0xE74D,	0x853D, 0xBDAA, 0x853E, 0xEB49, 0x8540, 0xEB40, 0x8541, 0xEB43,
+	0x8543, 0xBFBB, 0x8544, 0xEB45, 0x8545, 0xEAF9, 0x8546, 0xEB41,	0x8547, 0xEB47, 0x8548, 0xBFB8, 0x8549, 0xBFBC, 0x854A, 0xBFB6,
+	0x854D, 0xEAFB, 0x854E, 0xEB4C, 0x8551, 0xEB46, 0x8553, 0xEAFC,	0x8554, 0xEB55, 0x8555, 0xEB4F, 0x8556, 0xEAF8, 0x8557, 0xEE46,
+	0x8558, 0xEAFE, 0x8559, 0xBFB7, 0x855B, 0xEB4A, 0x855D, 0xEB54,	0x855E, 0xBFBF, 0x8560, 0xEB51, 0x8561, 0xEAFD, 0x8562, 0xEB44,
+	0x8563, 0xEB48, 0x8564, 0xEB42, 0x8565, 0xEB56, 0x8566, 0xEB53,	0x8567, 0xEB50, 0x8568, 0xBFB9, 0x8569, 0xBFBA, 0x856A, 0xBFBE,
+	0x856B, 0xEAFA, 0x856C, 0xEB57, 0x856D, 0xBFBD, 0x856E, 0xEB4D,	0x8571, 0xEB4B, 0x8575, 0xEB4E, 0x8576, 0xEE53, 0x8577, 0xEE40,
+	0x8578, 0xEE45, 0x8579, 0xEE52, 0x857A, 0xEE44, 0x857B, 0xEDFB,	0x857C, 0xEE41, 0x857E, 0xC1A2, 0x8580, 0xEDF4, 0x8581, 0xEE4D,
+	0x8582, 0xEE4F, 0x8583, 0xEDF3, 0x8584, 0xC1A1, 0x8585, 0xEE51,	0x8586, 0xEE49, 0x8587, 0xC1A8, 0x8588, 0xEE50, 0x8589, 0xEE42,
+	0x858A, 0xC1AA, 0x858B, 0xEDF9, 0x858C, 0xEB52, 0x858D, 0xEE4A,	0x858E, 0xEE47, 0x858F, 0xEDF5, 0x8590, 0xEE55, 0x8591, 0xC1A4,
+	0x8594, 0xC1A5, 0x8595, 0xEDF7, 0x8596, 0xEE48, 0x8598, 0xEE54,	0x8599, 0xEE4B, 0x859A, 0xEDFD, 0x859B, 0xC1A7, 0x859C, 0xC1A3,
+	0x859D, 0xEE4C, 0x859E, 0xEDFE, 0x859F, 0xEE56, 0x85A0, 0xEDF8,	0x85A1, 0xEE43, 0x85A2, 0xEE4E, 0x85A3, 0xEDFA, 0x85A4, 0xEDFC,
+	0x85A6, 0xC2CB, 0x85A7, 0xEDF6, 0x85A8, 0xC1A9, 0x85A9, 0xC2C4,	0x85AA, 0xC17E, 0x85AF, 0xC1A6, 0x85B0, 0xC2C8, 0x85B1, 0xF0B3,
+	0x85B3, 0xF0A9, 0x85B4, 0xF0A4, 0x85B5, 0xF0AA, 0x85B6, 0xF0B4,	0x85B7, 0xF0B8, 0x85B8, 0xF0B7, 0x85B9, 0xC2CA, 0x85BA, 0xC2C9,
+	0x85BD, 0xF0AB, 0x85BE, 0xF0B9, 0x85BF, 0xF0AE, 0x85C0, 0xF0A6,	0x85C2, 0xF0A8, 0x85C3, 0xF0A7, 0x85C4, 0xF0AD, 0x85C5, 0xF0B2,
+	0x85C6, 0xF0A5, 0x85C7, 0xF0AC, 0x85C8, 0xF0B1, 0x85C9, 0xC2C7,	0x85CB, 0xF0AF, 0x85CD, 0xC2C5, 0x85CE, 0xF0B0, 0x85CF, 0xC2C3,
+	0x85D0, 0xC2C6, 0x85D1, 0xF2D5, 0x85D2, 0xF0B5, 0x85D5, 0xC3C2,	0x85D7, 0xF2CD, 0x85D8, 0xF2D1, 0x85D9, 0xF2C9, 0x85DA, 0xF2CC,
+	0x85DC, 0xF2D4, 0x85DD, 0xC3C0, 0x85DE, 0xF2D9, 0x85DF, 0xF2D2,	0x85E1, 0xF2CA, 0x85E2, 0xF2DA, 0x85E3, 0xF2D3, 0x85E4, 0xC3C3,
+	0x85E5, 0xC3C4, 0x85E6, 0xF2D7, 0x85E8, 0xF2CB, 0x85E9, 0xC3BF,	0x85EA, 0xC3C1, 0x85EB, 0xF2C6, 0x85EC, 0xF2CE, 0x85ED, 0xF2C8,
+	0x85EF, 0xF2D8, 0x85F0, 0xF2D6, 0x85F1, 0xF2C7, 0x85F2, 0xF2CF,	0x85F6, 0xF4BE, 0x85F7, 0xC3C5, 0x85F8, 0xF2D0, 0x85F9, 0xC4A7,
+	0x85FA, 0xC4A9, 0x85FB, 0xC4A6, 0x85FD, 0xF4C3, 0x85FE, 0xF4BB,	0x85FF, 0xF4B9, 0x8600, 0xF4BD, 0x8601, 0xF4BA, 0x8604, 0xF4BF,
+	0x8605, 0xF4C1, 0x8606, 0xC4AA, 0x8607, 0xC4AC, 0x8609, 0xF4C0,	0x860A, 0xC4AD, 0x860B, 0xC4AB, 0x860C, 0xF4C2, 0x8611, 0xC4A8,
+	0x8617, 0xC4F4, 0x8618, 0xF5F1, 0x8619, 0xF5F7, 0x861A, 0xC4F6,	0x861B, 0xF4BC, 0x861C, 0xF5F6, 0x861E, 0xF5FD, 0x861F, 0xF5F4,
+	0x8620, 0xF5FB, 0x8621, 0xF5FA, 0x8622, 0xF4B8, 0x8623, 0xF5F5,	0x8624, 0xF0B6, 0x8625, 0xF5FE, 0x8626, 0xF5F3, 0x8627, 0xF5F8,
+	0x8629, 0xF5FC, 0x862A, 0xF5F2, 0x862C, 0xF74A, 0x862D, 0xC4F5,	0x862E, 0xF5F9, 0x8631, 0xF7F4, 0x8632, 0xF74B, 0x8633, 0xF749,
+	0x8634, 0xF747, 0x8635, 0xF748, 0x8636, 0xF74C, 0x8638, 0xC5D9,	0x8639, 0xF7F2, 0x863A, 0xF7F0, 0x863B, 0xF7F5, 0x863C, 0xF7F3,
+	0x863E, 0xF7F6, 0x863F, 0xC5DA, 0x8640, 0xF7F1, 0x8643, 0xF8BC,	0x8646, 0xF945, 0x8647, 0xF946, 0x8648, 0xF947, 0x864B, 0xF9C7,
+	0x864C, 0xF9BD, 0x864D, 0xCA4F, 0x864E, 0xAAEA, 0x8650, 0xAD68,	0x8652, 0xD3B8, 0x8653, 0xD3B7, 0x8654, 0xB040, 0x8655, 0xB342,
+	0x8656, 0xD77C, 0x8659, 0xD77B, 0x865B, 0xB5EA, 0x865C, 0xB8B8,	0x865E, 0xB8B7, 0x865F, 0xB8B9, 0x8661, 0xE3D4, 0x8662, 0xE77E,
+	0x8663, 0xEB58, 0x8664, 0xEB5A, 0x8665, 0xEB59, 0x8667, 0xC1AB,	0x8668, 0xEE57, 0x8669, 0xF0BA, 0x866A, 0xF9A5, 0x866B, 0xA6E4,
+	0x866D, 0xCDC9, 0x866E, 0xCDCA, 0x866F, 0xCDC8, 0x8670, 0xCDC7,	0x8671, 0xAAEB, 0x8673, 0xD0A9, 0x8674, 0xD0A7, 0x8677, 0xD0A6,
+	0x8679, 0xAD69, 0x867A, 0xAD6B, 0x867B, 0xAD6A, 0x867C, 0xD0A8,	0x8685, 0xD3C4, 0x8686, 0xD3C1, 0x8687, 0xD3BF, 0x868A, 0xB041,
+	0x868B, 0xD3C2, 0x868C, 0xB046, 0x868D, 0xD3BC, 0x868E, 0xD3CB,	0x8690, 0xD3CD, 0x8691, 0xD3BD, 0x8693, 0xB043, 0x8694, 0xD3CE,
+	0x8695, 0xD3C9, 0x8696, 0xD3BB, 0x8697, 0xD3C0, 0x8698, 0xD3CA,	0x8699, 0xD3C6, 0x869A, 0xD3C3, 0x869C, 0xB048, 0x869D, 0xD3CC,
+	0x869E, 0xD3BE, 0x86A1, 0xD3C7, 0x86A2, 0xD3B9, 0x86A3, 0xB047,	0x86A4, 0xB044, 0x86A5, 0xD3C5, 0x86A7, 0xD3C8, 0x86A8, 0xD3BA,
+	0x86A9, 0xB045, 0x86AA, 0xB042, 0x86AF, 0xB34C, 0x86B0, 0xD7A5,	0x86B1, 0xB34B, 0x86B3, 0xD7A8, 0x86B4, 0xD7AB, 0x86B5, 0xB348,
+	0x86B6, 0xB346, 0x86B7, 0xD77E, 0x86B8, 0xD7A9, 0x86B9, 0xD7A7,	0x86BA, 0xD7A4, 0x86BB, 0xD7AC, 0x86BC, 0xD7AD, 0x86BD, 0xD7AF,
+	0x86BE, 0xD7B0, 0x86BF, 0xD77D, 0x86C0, 0xB345, 0x86C1, 0xD7A2,	0x86C2, 0xD7A1, 0x86C3, 0xD7AE, 0x86C4, 0xB347, 0x86C5, 0xD7A3,
+	0x86C6, 0xB349, 0x86C7, 0xB344, 0x86C8, 0xD7A6, 0x86C9, 0xB34D,	0x86CB, 0xB34A, 0x86CC, 0xD7AA, 0x86D0, 0xB5F1, 0x86D1, 0xDBBF,
+	0x86D3, 0xDBB4, 0x86D4, 0xB5EE, 0x86D6, 0xDFE7, 0x86D7, 0xDBBD,	0x86D8, 0xDBB1, 0x86D9, 0xB5EC, 0x86DA, 0xDBB6, 0x86DB, 0xB5EF,
+	0x86DC, 0xDBBA, 0x86DD, 0xDBB8, 0x86DE, 0xB5F2, 0x86DF, 0xB5EB,	0x86E2, 0xDBB2, 0x86E3, 0xDBB5, 0x86E4, 0xB5F0, 0x86E6, 0xDBB3,
+	0x86E8, 0xDBBE, 0x86E9, 0xDBBC, 0x86EA, 0xDBB7, 0x86EB, 0xDBB9,	0x86EC, 0xDBBB, 0x86ED, 0xB5ED, 0x86F5, 0xDFE8, 0x86F6, 0xDFEE,
+	0x86F7, 0xDFE4, 0x86F8, 0xDFEA, 0x86F9, 0xB8BA, 0x86FA, 0xDFE6,	0x86FB, 0xB8C0, 0x86FE, 0xB8BF, 0x8700, 0xB8BE, 0x8701, 0xDFED,
+	0x8702, 0xB8C1, 0x8703, 0xB8C2, 0x8704, 0xDFE3, 0x8705, 0xDFF0,	0x8706, 0xB8C3, 0x8707, 0xB8BD, 0x8708, 0xB8BC, 0x8709, 0xDFEC,
+	0x870A, 0xB8C4, 0x870B, 0xDFE2, 0x870C, 0xDFE5, 0x870D, 0xDFEF,	0x870E, 0xDFEB, 0x8711, 0xE3F4, 0x8712, 0xE3E9, 0x8713, 0xB8BB,
+	0x8718, 0xBB6A, 0x8719, 0xE3DD, 0x871A, 0xE3F2, 0x871B, 0xE3DE,	0x871C, 0xBB65, 0x871E, 0xE3DB, 0x8720, 0xE3E4, 0x8721, 0xE3DC,
+	0x8722, 0xBB67, 0x8723, 0xE3D6, 0x8724, 0xE3F1, 0x8725, 0xBB68,	0x8726, 0xE3EE, 0x8727, 0xE3EF, 0x8728, 0xE3D7, 0x8729, 0xBB6D,
+	0x872A, 0xE3E6, 0x872C, 0xE3E0, 0x872D, 0xE3E7, 0x872E, 0xE3DA,	0x8730, 0xE3F3, 0x8731, 0xE3EB, 0x8732, 0xE3E5, 0x8733, 0xE3D5,
+	0x8734, 0xBB69, 0x8735, 0xE3EC, 0x8737, 0xBB6C, 0x8738, 0xE3F0,	0x873A, 0xE3EA, 0x873B, 0xBB66, 0x873C, 0xE3E8, 0x873E, 0xE3E2,
+	0x873F, 0xBB64, 0x8740, 0xE3D9, 0x8741, 0xE3E1, 0x8742, 0xE3ED,	0x8743, 0xE3DF, 0x8746, 0xE3E3, 0x874C, 0xBDC1, 0x874D, 0xDFE9,
+	0x874E, 0xE7B2, 0x874F, 0xE7BB, 0x8750, 0xE7B1, 0x8751, 0xE7AD,	0x8752, 0xE7AA, 0x8753, 0xBDC2, 0x8754, 0xE7A8, 0x8755, 0xBB6B,
+	0x8756, 0xE7A1, 0x8757, 0xBDC0, 0x8758, 0xE7A7, 0x8759, 0xBDBF,	0x875A, 0xE7AC, 0x875B, 0xE7A9, 0x875C, 0xE7B9, 0x875D, 0xE7B4,
+	0x875E, 0xE7AE, 0x875F, 0xE7B3, 0x8760, 0xBDBB, 0x8761, 0xE7AB,	0x8762, 0xE7BE, 0x8763, 0xE7A2, 0x8764, 0xE7A3, 0x8765, 0xE7BA,
+	0x8766, 0xBDBC, 0x8767, 0xE7BF, 0x8768, 0xBDBE, 0x8769, 0xE7C0,	0x876A, 0xE7B0, 0x876B, 0xE3D8, 0x876C, 0xE7B6, 0x876D, 0xE7AF,
+	0x876E, 0xE7B8, 0x876F, 0xE7B5, 0x8773, 0xE7A6, 0x8774, 0xBDB9,	0x8775, 0xE7BD, 0x8776, 0xBDBA, 0x8777, 0xE7A4, 0x8778, 0xBDBD,
+	0x8779, 0xEB64, 0x877A, 0xE7B7, 0x877B, 0xE7BC, 0x8781, 0xEB61,	0x8782, 0xBDB8, 0x8783, 0xBFC0, 0x8784, 0xEB6B, 0x8785, 0xEB67,
+	0x8787, 0xEB65, 0x8788, 0xEB60, 0x8789, 0xEB6F, 0x878D, 0xBFC4,	0x878F, 0xEB5C, 0x8790, 0xEB68, 0x8791, 0xEB69, 0x8792, 0xEB5F,
+	0x8793, 0xEB5E, 0x8794, 0xEB6C, 0x8796, 0xEB62, 0x8797, 0xEB5D,	0x8798, 0xEB63, 0x879A, 0xEB6E, 0x879B, 0xEB5B, 0x879C, 0xEB6D,
+	0x879D, 0xEB6A, 0x879E, 0xBFC2, 0x879F, 0xBFC1, 0x87A2, 0xBFC3,	0x87A3, 0xEB66, 0x87A4, 0xF0CB, 0x87AA, 0xEE59, 0x87AB, 0xC1B1,
+	0x87AC, 0xEE5D, 0x87AD, 0xEE5A, 0x87AE, 0xEE61, 0x87AF, 0xEE67,	0x87B0, 0xEE5C, 0x87B2, 0xEE70, 0x87B3, 0xC1AE, 0x87B4, 0xEE6A,
+	0x87B5, 0xEE5F, 0x87B6, 0xEE6B, 0x87B7, 0xEE66, 0x87B8, 0xEE6D,	0x87B9, 0xEE5E, 0x87BA, 0xC1B3, 0x87BB, 0xC1B2, 0x87BC, 0xEE60,
+	0x87BD, 0xEE6E, 0x87BE, 0xEE58, 0x87BF, 0xEE6C, 0x87C0, 0xC1AC,	0x87C2, 0xEE64, 0x87C3, 0xEE63, 0x87C4, 0xEE68, 0x87C5, 0xEE5B,
+	0x87C6, 0xC1B0, 0x87C8, 0xC1B4, 0x87C9, 0xEE62, 0x87CA, 0xEE69,	0x87CB, 0xC1B5, 0x87CC, 0xEE65, 0x87D1, 0xC1AD, 0x87D2, 0xC1AF,
+	0x87D3, 0xF0C7, 0x87D4, 0xF0C5, 0x87D7, 0xF0CC, 0x87D8, 0xF0C9,	0x87D9, 0xF0CD, 0x87DB, 0xF0BE, 0x87DC, 0xF0C6, 0x87DD, 0xF0D1,
+	0x87DE, 0xEE6F, 0x87DF, 0xF0C2, 0x87E0, 0xC2CF, 0x87E1, 0xE7A5,	0x87E2, 0xF0BD, 0x87E3, 0xF0CA, 0x87E4, 0xF0C4, 0x87E5, 0xF0C1,
+	0x87E6, 0xF0BC, 0x87E7, 0xF0BB, 0x87E8, 0xF0D0, 0x87EA, 0xF0C0,	0x87EB, 0xF0BF, 0x87EC, 0xC2CD, 0x87ED, 0xF0C8, 0x87EF, 0xC2CC,
+	0x87F2, 0xC2CE, 0x87F3, 0xF0C3, 0x87F4, 0xF0CF, 0x87F6, 0xF2DE,	0x87F7, 0xF2DF, 0x87F9, 0xC3C9, 0x87FA, 0xF2DC, 0x87FB, 0xC3C6,
+	0x87FC, 0xF2E4, 0x87FE, 0xC3CA, 0x87FF, 0xF2E6, 0x8800, 0xF2DB,	0x8801, 0xF0CE, 0x8802, 0xF2E8, 0x8803, 0xF2DD, 0x8805, 0xC3C7,
+	0x8806, 0xF2E3, 0x8808, 0xF2E5, 0x8809, 0xF2E0, 0x880A, 0xF2E7,	0x880B, 0xF2E2, 0x880C, 0xF2E1, 0x880D, 0xC3C8, 0x8810, 0xF4C5,
+	0x8811, 0xF4C6, 0x8813, 0xF4C8, 0x8814, 0xC4AE, 0x8815, 0xC4AF,	0x8816, 0xF4C9, 0x8817, 0xF4C7, 0x8819, 0xF4C4, 0x881B, 0xF642,
+	0x881C, 0xF645, 0x881D, 0xF641, 0x881F, 0xC4FA, 0x8820, 0xF643,	0x8821, 0xC4F9, 0x8822, 0xC4F8, 0x8823, 0xC4F7, 0x8824, 0xF644,
+	0x8825, 0xF751, 0x8826, 0xF74F, 0x8828, 0xF74E, 0x8829, 0xF640,	0x882A, 0xF750, 0x882B, 0xF646, 0x882C, 0xF74D, 0x882E, 0xF7F9,
+	0x882F, 0xF7D7, 0x8830, 0xF7F7, 0x8831, 0xC5DB, 0x8832, 0xF7F8,	0x8833, 0xF7FA, 0x8835, 0xF8BF, 0x8836, 0xC5FA, 0x8837, 0xF8BE,
+	0x8838, 0xF8BD, 0x8839, 0xC5FB, 0x883B, 0xC65A, 0x883C, 0xF96E,	0x883D, 0xF9A7, 0x883E, 0xF9A6, 0x883F, 0xF9A8, 0x8840, 0xA6E5,
+	0x8841, 0xD0AA, 0x8843, 0xD3CF, 0x8844, 0xD3D0, 0x8848, 0xDBC0,	0x884A, 0xF647, 0x884B, 0xF8C0, 0x884C, 0xA6E6, 0x884D, 0xAD6C,
+	0x884E, 0xD0AB, 0x8852, 0xD7B1, 0x8853, 0xB34E, 0x8855, 0xDBC2,	0x8856, 0xDBC1, 0x8857, 0xB5F3, 0x8859, 0xB8C5, 0x885A, 0xE7C1,
+	0x885B, 0xBDC3, 0x885D, 0xBDC4, 0x8861, 0xBFC5, 0x8862, 0xC5FC,	0x8863, 0xA6E7, 0x8867, 0xD0AC, 0x8868, 0xAAED, 0x8869, 0xD0AE,
+	0x886A, 0xD0AD, 0x886B, 0xAD6D, 0x886D, 0xD3D1, 0x886F, 0xD3D8,	0x8870, 0xB049, 0x8871, 0xD3D6, 0x8872, 0xD3D4, 0x8874, 0xD3DB,
+	0x8875, 0xD3D2, 0x8876, 0xD3D3, 0x8877, 0xB04A, 0x8879, 0xB04E,	0x887C, 0xD3DC, 0x887D, 0xB04D, 0x887E, 0xD3DA, 0x887F, 0xD3D7,
+	0x8880, 0xD3D5, 0x8881, 0xB04B, 0x8882, 0xB04C, 0x8883, 0xD3D9,	0x8888, 0xB350, 0x8889, 0xD7B2, 0x888B, 0xB355, 0x888C, 0xD7C2,
+	0x888D, 0xB354, 0x888E, 0xD7C4, 0x8891, 0xD7B8, 0x8892, 0xB352,	0x8893, 0xD7C3, 0x8895, 0xD7B3, 0x8896, 0xB353, 0x8897, 0xD7BF,
+	0x8898, 0xD7BB, 0x8899, 0xD7BD, 0x889A, 0xD7B7, 0x889B, 0xD7BE,	0x889E, 0xB34F, 0x889F, 0xD7BA, 0x88A1, 0xD7B9, 0x88A2, 0xD7B5,
+	0x88A4, 0xD7C0, 0x88A7, 0xD7BC, 0x88A8, 0xD7B4, 0x88AA, 0xD7B6,	0x88AB, 0xB351, 0x88AC, 0xD7C1, 0x88B1, 0xB5F6, 0x88B2, 0xDBCD,
+	0x88B6, 0xDBC9, 0x88B7, 0xDBCB, 0x88B8, 0xDBC6, 0x88B9, 0xDBC5,	0x88BA, 0xDBC3, 0x88BC, 0xDBCA, 0x88BD, 0xDBCC, 0x88BE, 0xDBC8,
+	0x88C0, 0xDBC7, 0x88C1, 0xB5F4, 0x88C2, 0xB5F5, 0x88C9, 0xDBCF,	0x88CA, 0xB8CD, 0x88CB, 0xDFF2, 0x88CC, 0xDFF8, 0x88CD, 0xDFF3,
+	0x88CE, 0xDFF4, 0x88CF, 0xF9D8, 0x88D0, 0xDFF9, 0x88D2, 0xB8CF,	0x88D4, 0xB8C7, 0x88D5, 0xB8CE, 0x88D6, 0xDFF1, 0x88D7, 0xDBC4,
+	0x88D8, 0xB8CA, 0x88D9, 0xB8C8, 0x88DA, 0xDFF7, 0x88DB, 0xDFF6,	0x88DC, 0xB8C9, 0x88DD, 0xB8CB, 0x88DE, 0xDFF5, 0x88DF, 0xB8C6,
+	0x88E1, 0xB8CC, 0x88E7, 0xE3F6, 0x88E8, 0xBB74, 0x88EB, 0xE442,	0x88EC, 0xE441, 0x88EE, 0xE3FB, 0x88EF, 0xBB76, 0x88F0, 0xE440,
+	0x88F1, 0xE3F7, 0x88F2, 0xE3F8, 0x88F3, 0xBB6E, 0x88F4, 0xBB70,	0x88F6, 0xE3FD, 0x88F7, 0xE3F5, 0x88F8, 0xBB72, 0x88F9, 0xBB71,
+	0x88FA, 0xE3F9, 0x88FB, 0xE3FE, 0x88FC, 0xE3FC, 0x88FD, 0xBB73,	0x88FE, 0xE3FA, 0x8901, 0xDBCE, 0x8902, 0xBB6F, 0x8905, 0xE7C2,
+	0x8906, 0xE7C9, 0x8907, 0xBDC6, 0x8909, 0xE7CD, 0x890A, 0xBDCA,	0x890B, 0xE7C5, 0x890C, 0xE7C3, 0x890E, 0xE7CC, 0x8910, 0xBDC5,
+	0x8911, 0xE7CB, 0x8912, 0xBDC7, 0x8913, 0xBDC8, 0x8914, 0xE7C4,	0x8915, 0xBDC9, 0x8916, 0xE7CA, 0x8917, 0xE7C6, 0x8918, 0xE7C7,
+	0x8919, 0xE7C8, 0x891A, 0xBB75, 0x891E, 0xEB70, 0x891F, 0xEB7C,	0x8921, 0xBFCA, 0x8922, 0xEB77, 0x8923, 0xEB79, 0x8925, 0xBFC8,
+	0x8926, 0xEB71, 0x8927, 0xEB75, 0x8929, 0xEB78, 0x892A, 0xBFC6,	0x892B, 0xBFC9, 0x892C, 0xEB7B, 0x892D, 0xEB73, 0x892E, 0xEB74,
+	0x892F, 0xEB7A, 0x8930, 0xEB72, 0x8931, 0xEB76, 0x8932, 0xBFC7,	0x8933, 0xEE72, 0x8935, 0xEE71, 0x8936, 0xC1B7, 0x8937, 0xEE77,
+	0x8938, 0xC1B9, 0x893B, 0xC1B6, 0x893C, 0xEE73, 0x893D, 0xC1BA,	0x893E, 0xEE74, 0x8941, 0xEE75, 0x8942, 0xEE78, 0x8944, 0xC1B8,
+	0x8946, 0xF0D6, 0x8949, 0xF0D9, 0x894B, 0xF0D3, 0x894C, 0xF0D5,	0x894F, 0xF0D4, 0x8950, 0xF0D7, 0x8951, 0xF0D8, 0x8952, 0xEE76,
+	0x8953, 0xF0D2, 0x8956, 0xC3CD, 0x8957, 0xF2EC, 0x8958, 0xF2EF,	0x8959, 0xF2F1, 0x895A, 0xF2EA, 0x895B, 0xF2EB, 0x895C, 0xF2EE,
+	0x895D, 0xF2F0, 0x895E, 0xC3CE, 0x895F, 0xC3CC, 0x8960, 0xC3CB,	0x8961, 0xF2ED, 0x8962, 0xF2E9, 0x8963, 0xF4CA, 0x8964, 0xC4B0,
+	0x8966, 0xF4CB, 0x8969, 0xF649, 0x896A, 0xC4FB, 0x896B, 0xF64B,	0x896C, 0xC4FC, 0x896D, 0xF648, 0x896E, 0xF64A, 0x896F, 0xC5A8,
+	0x8971, 0xF752, 0x8972, 0xC5A7, 0x8973, 0xF7FD, 0x8974, 0xF7FC,	0x8976, 0xF7FB, 0x8979, 0xF948, 0x897A, 0xF949, 0x897B, 0xF94B,
+	0x897C, 0xF94A, 0x897E, 0xCA50, 0x897F, 0xA6E8, 0x8981, 0xAD6E,	0x8982, 0xD7C5, 0x8983, 0xB5F7, 0x8985, 0xDFFA, 0x8986, 0xC2D0,
+	0x8988, 0xF2F2, 0x898B, 0xA8A3, 0x898F, 0xB357, 0x8993, 0xB356,	0x8995, 0xDBD0, 0x8996, 0xB5F8, 0x8997, 0xDBD2, 0x8998, 0xDBD1,
+	0x899B, 0xDFFB, 0x899C, 0xB8D0, 0x899D, 0xE443, 0x899E, 0xE446,	0x899F, 0xE445, 0x89A1, 0xE444, 0x89A2, 0xE7CE, 0x89A3, 0xE7D0,
+	0x89A4, 0xE7CF, 0x89A6, 0xBFCC, 0x89AA, 0xBFCB, 0x89AC, 0xC1BB,	0x89AD, 0xEE79, 0x89AE, 0xEE7B, 0x89AF, 0xEE7A, 0x89B2, 0xC2D1,
+	0x89B6, 0xF2F4, 0x89B7, 0xF2F3, 0x89B9, 0xF4CC, 0x89BA, 0xC4B1,	0x89BD, 0xC4FD, 0x89BE, 0xF754, 0x89BF, 0xF753, 0x89C0, 0xC65B,
+	0x89D2, 0xA8A4, 0x89D3, 0xD0AF, 0x89D4, 0xAD6F, 0x89D5, 0xD7C8,	0x89D6, 0xD7C6, 0x89D9, 0xD7C7, 0x89DA, 0xDBD4, 0x89DB, 0xDBD5,
+	0x89DC, 0xE043, 0x89DD, 0xDBD3, 0x89DF, 0xDFFC, 0x89E0, 0xE041,	0x89E1, 0xE040, 0x89E2, 0xE042, 0x89E3, 0xB8D1, 0x89E4, 0xDFFE,
+	0x89E5, 0xDFFD, 0x89E6, 0xE044, 0x89E8, 0xE449, 0x89E9, 0xE447,	0x89EB, 0xE448, 0x89EC, 0xE7D3, 0x89ED, 0xE7D1, 0x89F0, 0xE7D2,
+	0x89F1, 0xEB7D, 0x89F2, 0xEE7C, 0x89F3, 0xEE7D, 0x89F4, 0xC2D2,	0x89F6, 0xF2F5, 0x89F7, 0xF4CD, 0x89F8, 0xC4B2, 0x89FA, 0xF64C,
+	0x89FB, 0xF755, 0x89FC, 0xC5A9, 0x89FE, 0xF7FE, 0x89FF, 0xF94C,	0x8A00, 0xA8A5, 0x8A02, 0xAD71, 0x8A03, 0xAD72, 0x8A04, 0xD0B0,
+	0x8A07, 0xD0B1, 0x8A08, 0xAD70, 0x8A0A, 0xB054, 0x8A0C, 0xB052,	0x8A0E, 0xB051, 0x8A0F, 0xB058, 0x8A10, 0xB050, 0x8A11, 0xB059,
+	0x8A12, 0xD3DD, 0x8A13, 0xB056, 0x8A15, 0xB053, 0x8A16, 0xB057,	0x8A17, 0xB055, 0x8A18, 0xB04F, 0x8A1B, 0xB35F, 0x8A1D, 0xB359,
+	0x8A1E, 0xD7CC, 0x8A1F, 0xB35E, 0x8A22, 0xB360, 0x8A23, 0xB35A,	0x8A25, 0xB35B, 0x8A27, 0xD7CA, 0x8A2A, 0xB358, 0x8A2C, 0xD7CB,
+	0x8A2D, 0xB35D, 0x8A30, 0xD7C9, 0x8A31, 0xB35C, 0x8A34, 0xB644,	0x8A36, 0xB646, 0x8A39, 0xDBD8, 0x8A3A, 0xB645, 0x8A3B, 0xB5F9,
+	0x8A3C, 0xB5FD, 0x8A3E, 0xB8E4, 0x8A3F, 0xE049, 0x8A40, 0xDBDA,	0x8A41, 0xB5FE, 0x8A44, 0xDBDD, 0x8A45, 0xDBDE, 0x8A46, 0xB643,
+	0x8A48, 0xDBE0, 0x8A4A, 0xDBE2, 0x8A4C, 0xDBE3, 0x8A4D, 0xDBD7,	0x8A4E, 0xDBD6, 0x8A4F, 0xDBE4, 0x8A50, 0xB642, 0x8A51, 0xDBE1,
+	0x8A52, 0xDBDF, 0x8A54, 0xB640, 0x8A55, 0xB5FB, 0x8A56, 0xB647,	0x8A57, 0xDBDB, 0x8A58, 0xDBDC, 0x8A59, 0xDBD9, 0x8A5B, 0xB641,
+	0x8A5E, 0xB5FC, 0x8A60, 0xB5FA, 0x8A61, 0xE048, 0x8A62, 0xB8DF,	0x8A63, 0xB8DA, 0x8A66, 0xB8D5, 0x8A68, 0xB8E5, 0x8A69, 0xB8D6,
+	0x8A6B, 0xB8D2, 0x8A6C, 0xB8E1, 0x8A6D, 0xB8DE, 0x8A6E, 0xB8E0,	0x8A70, 0xB8D7, 0x8A71, 0xB8DC, 0x8A72, 0xB8D3, 0x8A73, 0xB8D4,
+	0x8A74, 0xE050, 0x8A75, 0xE04D, 0x8A76, 0xE045, 0x8A77, 0xE04A,	0x8A79, 0xB8E2, 0x8A7A, 0xE051, 0x8A7B, 0xB8E3, 0x8A7C, 0xB8D9,
+	0x8A7F, 0xE047, 0x8A81, 0xE04F, 0x8A82, 0xE04B, 0x8A83, 0xE04E,	0x8A84, 0xE04C, 0x8A85, 0xB8DD, 0x8A86, 0xE046, 0x8A87, 0xB8D8,
+	0x8A8B, 0xE44C, 0x8A8C, 0xBB78, 0x8A8D, 0xBB7B, 0x8A8F, 0xE44E,	0x8A91, 0xBBA5, 0x8A92, 0xE44D, 0x8A93, 0xBB7D, 0x8A95, 0xBDCF,
+	0x8A96, 0xE44F, 0x8A98, 0xBBA4, 0x8A99, 0xE44B, 0x8A9A, 0xBBA6,	0x8A9E, 0xBB79, 0x8AA0, 0xB8DB, 0x8AA1, 0xBB7C, 0x8AA3, 0xBB7A,
+	0x8AA4, 0xBB7E, 0x8AA5, 0xBBA2, 0x8AA6, 0xBB77, 0x8AA7, 0xBBA7,	0x8AA8, 0xBBA3, 0x8AAA, 0xBBA1, 0x8AAB, 0xE44A, 0x8AB0, 0xBDD6,
+	0x8AB2, 0xBDD2, 0x8AB6, 0xBDD9, 0x8AB8, 0xE7D6, 0x8AB9, 0xBDDA,	0x8ABA, 0xE7E2, 0x8ABB, 0xE7DB, 0x8ABC, 0xBDCB, 0x8ABD, 0xE7E3,
+	0x8ABE, 0xE7DD, 0x8ABF, 0xBDD5, 0x8AC0, 0xE7DE, 0x8AC2, 0xBDD4,	0x8AC3, 0xE7E1, 0x8AC4, 0xBDCE, 0x8AC5, 0xE7DF, 0x8AC6, 0xE7D5,
+	0x8AC7, 0xBDCD, 0x8AC8, 0xEBAA, 0x8AC9, 0xBDD3, 0x8ACB, 0xBDD0,	0x8ACD, 0xBDD8, 0x8ACF, 0xE7D4, 0x8AD1, 0xE7D8, 0x8AD2, 0xBDCC,
+	0x8AD3, 0xE7D7, 0x8AD4, 0xE7D9, 0x8AD5, 0xE7DA, 0x8AD6, 0xBDD7,	0x8AD7, 0xE7DC, 0x8AD8, 0xE7E0, 0x8AD9, 0xE7E4, 0x8ADB, 0xBDDB,
+	0x8ADC, 0xBFD2, 0x8ADD, 0xEBA5, 0x8ADE, 0xEBAB, 0x8ADF, 0xEBA8,	0x8AE0, 0xEB7E, 0x8AE1, 0xEBAC, 0x8AE2, 0xEBA1, 0x8AE4, 0xEBA7,
+	0x8AE6, 0xBFCD, 0x8AE7, 0xBFD3, 0x8AE8, 0xEBAD, 0x8AEB, 0xBFCF,	0x8AED, 0xBFD9, 0x8AEE, 0xBFD4, 0x8AEF, 0xEBAF, 0x8AF0, 0xEBA9,
+	0x8AF1, 0xBFD0, 0x8AF2, 0xEBA2, 0x8AF3, 0xBFDA, 0x8AF4, 0xEBA3,	0x8AF5, 0xEBA4, 0x8AF6, 0xBFDB, 0x8AF7, 0xBFD8, 0x8AF8, 0xBDD1,
+	0x8AFA, 0xBFCE, 0x8AFB, 0xEBB0, 0x8AFC, 0xBFDC, 0x8AFE, 0xBFD5,	0x8AFF, 0xEBAE, 0x8B00, 0xBFD1, 0x8B01, 0xBFD6, 0x8B02, 0xBFD7,
+	0x8B04, 0xC1C3, 0x8B05, 0xEEA4, 0x8B06, 0xEEAD, 0x8B07, 0xEEAA,	0x8B08, 0xEEAC, 0x8B0A, 0xC1C0, 0x8B0B, 0xEEA5, 0x8B0D, 0xEEAB,
+	0x8B0E, 0xC1BC, 0x8B0F, 0xEEA7, 0x8B10, 0xC1C4, 0x8B11, 0xEEA3,	0x8B12, 0xEEA8, 0x8B13, 0xEEAF, 0x8B14, 0xEBA6, 0x8B15, 0xEEA9,
+	0x8B16, 0xEEA2, 0x8B17, 0xC1BD, 0x8B18, 0xEEA1, 0x8B19, 0xC1BE,	0x8B1A, 0xEEB0, 0x8B1B, 0xC1BF, 0x8B1C, 0xEEAE, 0x8B1D, 0xC1C2,
+	0x8B1E, 0xEE7E, 0x8B20, 0xC1C1, 0x8B22, 0xEEA6, 0x8B23, 0xF0DC,	0x8B24, 0xF0EA, 0x8B25, 0xF0E5, 0x8B26, 0xF0E7, 0x8B27, 0xF0DB,
+	0x8B28, 0xC2D3, 0x8B2A, 0xF0DA, 0x8B2B, 0xC2D6, 0x8B2C, 0xC2D5,	0x8B2E, 0xF0E9, 0x8B2F, 0xF0E1, 0x8B30, 0xF0DE, 0x8B31, 0xF0E4,
+	0x8B33, 0xF0DD, 0x8B35, 0xF0DF, 0x8B36, 0xF0E8, 0x8B37, 0xF0E6,	0x8B39, 0xC2D4, 0x8B3A, 0xF0ED, 0x8B3B, 0xF0EB, 0x8B3C, 0xF0E2,
+	0x8B3D, 0xF0EC, 0x8B3E, 0xF0E3, 0x8B40, 0xF2F9, 0x8B41, 0xC3CF,	0x8B42, 0xF341, 0x8B45, 0xF64F, 0x8B46, 0xC3D6, 0x8B47, 0xF0E0,
+	0x8B48, 0xF2F7, 0x8B49, 0xC3D2, 0x8B4A, 0xF2F8, 0x8B4B, 0xF2FD,	0x8B4E, 0xC3D4, 0x8B4F, 0xC3D5, 0x8B50, 0xF2F6, 0x8B51, 0xF340,
+	0x8B52, 0xF342, 0x8B53, 0xF2FA, 0x8B54, 0xF2FC, 0x8B55, 0xF2FE,	0x8B56, 0xF2FB, 0x8B57, 0xF343, 0x8B58, 0xC3D1, 0x8B59, 0xC3D7,
+	0x8B5A, 0xC3D3, 0x8B5C, 0xC3D0, 0x8B5D, 0xF4D0, 0x8B5F, 0xC4B7,	0x8B60, 0xF4CE, 0x8B63, 0xF4D2, 0x8B65, 0xF4D3, 0x8B66, 0xC4B5,
+	0x8B67, 0xF4D4, 0x8B68, 0xF4D1, 0x8B6A, 0xF4CF, 0x8B6B, 0xC4B8,	0x8B6C, 0xC4B4, 0x8B6D, 0xF4D5, 0x8B6F, 0xC4B6, 0x8B70, 0xC4B3,
+	0x8B74, 0xC4FE, 0x8B77, 0xC540, 0x8B78, 0xF64E, 0x8B79, 0xF64D,	0x8B7A, 0xF650, 0x8B7B, 0xF651, 0x8B7D, 0xC541, 0x8B7E, 0xF756,
+	0x8B7F, 0xF75B, 0x8B80, 0xC5AA, 0x8B82, 0xF758, 0x8B84, 0xF757,	0x8B85, 0xF75A, 0x8B86, 0xF759, 0x8B88, 0xF843, 0x8B8A, 0xC5DC,
+	0x8B8B, 0xF842, 0x8B8C, 0xF840, 0x8B8E, 0xF841, 0x8B92, 0xC5FE,	0x8B93, 0xC5FD, 0x8B94, 0xF8C1, 0x8B95, 0xF8C2, 0x8B96, 0xC640,
+	0x8B98, 0xF94D, 0x8B99, 0xF94E, 0x8B9A, 0xC667, 0x8B9C, 0xC66D,	0x8B9E, 0xF9A9, 0x8B9F, 0xF9C8, 0x8C37, 0xA8A6, 0x8C39, 0xD7CD,
+	0x8C3B, 0xD7CE, 0x8C3C, 0xE052, 0x8C3D, 0xE450, 0x8C3E, 0xE7E5,	0x8C3F, 0xC1C6, 0x8C41, 0xC1C5, 0x8C42, 0xF0EE, 0x8C43, 0xF344,
+	0x8C45, 0xF844, 0x8C46, 0xA8A7, 0x8C47, 0xD3DE, 0x8C48, 0xB05A,	0x8C49, 0xB361, 0x8C4A, 0xE054, 0x8C4B, 0xE053, 0x8C4C, 0xBDDC,
+	0x8C4D, 0xE7E6, 0x8C4E, 0xBDDD, 0x8C4F, 0xEEB1, 0x8C50, 0xC2D7,	0x8C54, 0xC676, 0x8C55, 0xA8A8, 0x8C56, 0xCDCB, 0x8C57, 0xD3DF,
+	0x8C5A, 0xB362, 0x8C5C, 0xD7CF, 0x8C5D, 0xD7D0, 0x8C5F, 0xDBE5,	0x8C61, 0xB648, 0x8C62, 0xB8E6, 0x8C64, 0xE056, 0x8C65, 0xE055,
+	0x8C66, 0xE057, 0x8C68, 0xE451, 0x8C69, 0xE452, 0x8C6A, 0xBBA8,	0x8C6B, 0xBFDD, 0x8C6C, 0xBDDE, 0x8C6D, 0xBFDE, 0x8C6F, 0xEEB5,
+	0x8C70, 0xEEB2, 0x8C71, 0xEEB4, 0x8C72, 0xEEB3, 0x8C73, 0xC1C7,	0x8C75, 0xF0EF, 0x8C76, 0xF346, 0x8C77, 0xF345, 0x8C78, 0xCBA4,
+	0x8C79, 0xB05C, 0x8C7A, 0xB05B, 0x8C7B, 0xD3E0, 0x8C7D, 0xD7D1,	0x8C80, 0xDBE7, 0x8C81, 0xDBE6, 0x8C82, 0xB649, 0x8C84, 0xE059,
+	0x8C85, 0xE05A, 0x8C86, 0xE058, 0x8C89, 0xB8E8, 0x8C8A, 0xB8E7,	0x8C8C, 0xBBAA, 0x8C8D, 0xBBA9, 0x8C8F, 0xE7E7, 0x8C90, 0xEBB3,
+	0x8C91, 0xEBB1, 0x8C92, 0xEBB2, 0x8C93, 0xBFDF, 0x8C94, 0xEEB7,	0x8C95, 0xEEB6, 0x8C97, 0xF0F2, 0x8C98, 0xF0F1, 0x8C99, 0xF0F0,
+	0x8C9A, 0xF347, 0x8C9C, 0xF9AA, 0x8C9D, 0xA8A9, 0x8C9E, 0xAD73,	0x8CA0, 0xAD74, 0x8CA1, 0xB05D, 0x8CA2, 0xB05E, 0x8CA3, 0xD3E2,
+	0x8CA4, 0xD3E1, 0x8CA5, 0xD7D2, 0x8CA7, 0xB368, 0x8CA8, 0xB366,	0x8CA9, 0xB363, 0x8CAA, 0xB367, 0x8CAB, 0xB365, 0x8CAC, 0xB364,
+	0x8CAF, 0xB64A, 0x8CB0, 0xDBEA, 0x8CB2, 0xB8ED, 0x8CB3, 0xB64C,	0x8CB4, 0xB651, 0x8CB5, 0xDBEC, 0x8CB6, 0xB653, 0x8CB7, 0xB652,
+	0x8CB8, 0xB655, 0x8CB9, 0xDBEB, 0x8CBA, 0xDBE8, 0x8CBB, 0xB64F,	0x8CBC, 0xB64B, 0x8CBD, 0xB64D, 0x8CBE, 0xDBE9, 0x8CBF, 0xB654,
+	0x8CC0, 0xB650, 0x8CC1, 0xB64E, 0x8CC2, 0xB8EF, 0x8CC3, 0xB8EE,	0x8CC4, 0xB8EC, 0x8CC5, 0xB8F0, 0x8CC7, 0xB8EA, 0x8CC8, 0xB8EB,
+	0x8CCA, 0xB8E9, 0x8CCC, 0xE05B, 0x8CCF, 0xE454, 0x8CD1, 0xBBAC,	0x8CD2, 0xBBAD, 0x8CD3, 0xBBAB, 0x8CD5, 0xE453, 0x8CD7, 0xE455,
+	0x8CD9, 0xE7EA, 0x8CDA, 0xE7EC, 0x8CDC, 0xBDE7, 0x8CDD, 0xE7ED,	0x8CDE, 0xBDE0, 0x8CDF, 0xE7E9, 0x8CE0, 0xBDDF, 0x8CE1, 0xBDE9,
+	0x8CE2, 0xBDE5, 0x8CE3, 0xBDE6, 0x8CE4, 0xBDE2, 0x8CE5, 0xE7E8,	0x8CE6, 0xBDE1, 0x8CE7, 0xE7EE, 0x8CE8, 0xE7EB, 0x8CEA, 0xBDE8,
+	0x8CEC, 0xBDE3, 0x8CED, 0xBDE4, 0x8CEE, 0xEBB5, 0x8CF0, 0xEBB7,	0x8CF1, 0xEBB6, 0x8CF3, 0xEBB8, 0x8CF4, 0xBFE0, 0x8CF5, 0xEBB4,
+	0x8CF8, 0xC1CB, 0x8CF9, 0xEEB8, 0x8CFA, 0xC1C8, 0x8CFB, 0xC1CC,	0x8CFC, 0xC1CA, 0x8CFD, 0xC1C9, 0x8CFE, 0xF0F3, 0x8D00, 0xF0F6,
+	0x8D02, 0xF0F5, 0x8D04, 0xF0F4, 0x8D05, 0xC2D8, 0x8D06, 0xF348,	0x8D07, 0xF349, 0x8D08, 0xC3D8, 0x8D09, 0xF34A, 0x8D0A, 0xC3D9,
+	0x8D0D, 0xC4BA, 0x8D0F, 0xC4B9, 0x8D10, 0xF652, 0x8D13, 0xC542,	0x8D14, 0xF653, 0x8D15, 0xF75C, 0x8D16, 0xC5AB, 0x8D17, 0xC5AC,
+	0x8D19, 0xF845, 0x8D1B, 0xC642, 0x8D64, 0xA8AA, 0x8D66, 0xB36A,	0x8D67, 0xB369, 0x8D68, 0xE05C, 0x8D69, 0xE05D, 0x8D6B, 0xBBAE,
+	0x8D6C, 0xEBB9, 0x8D6D, 0xBDEA, 0x8D6E, 0xEBBA, 0x8D6F, 0xEEB9,	0x8D70, 0xA8AB, 0x8D72, 0xD0B2, 0x8D73, 0xAD76, 0x8D74, 0xAD75,
+	0x8D76, 0xD3E3, 0x8D77, 0xB05F, 0x8D78, 0xD3E4, 0x8D79, 0xD7D5,	0x8D7B, 0xD7D4, 0x8D7D, 0xD7D3, 0x8D80, 0xDBEE, 0x8D81, 0xB658,
+	0x8D84, 0xDBED, 0x8D85, 0xB657, 0x8D89, 0xDBEF, 0x8D8A, 0xB656,	0x8D8C, 0xE05F, 0x8D8D, 0xE062, 0x8D8E, 0xE060, 0x8D8F, 0xE061,
+	0x8D90, 0xE065, 0x8D91, 0xE05E, 0x8D92, 0xE066, 0x8D93, 0xE063,	0x8D94, 0xE064, 0x8D95, 0xBBB0, 0x8D96, 0xE456, 0x8D99, 0xBBAF,
+	0x8D9B, 0xE7F2, 0x8D9C, 0xE7F0, 0x8D9F, 0xBDEB, 0x8DA0, 0xE7EF,	0x8DA1, 0xE7F1, 0x8DA3, 0xBDEC, 0x8DA5, 0xEBBB, 0x8DA7, 0xEBBC,
+	0x8DA8, 0xC1CD, 0x8DAA, 0xF34C, 0x8DAB, 0xF34E, 0x8DAC, 0xF34B,	0x8DAD, 0xF34D, 0x8DAE, 0xF4D6, 0x8DAF, 0xF654, 0x8DB2, 0xF96F,
+	0x8DB3, 0xA8AC, 0x8DB4, 0xAD77, 0x8DB5, 0xD3E5, 0x8DB6, 0xD3E7,	0x8DB7, 0xD3E6, 0x8DB9, 0xD7D8, 0x8DBA, 0xB36C, 0x8DBC, 0xD7D6,
+	0x8DBE, 0xB36B, 0x8DBF, 0xD7D9, 0x8DC1, 0xD7DA, 0x8DC2, 0xD7D7,	0x8DC5, 0xDBFB, 0x8DC6, 0xB660, 0x8DC7, 0xDBF3, 0x8DC8, 0xDBF9,
+	0x8DCB, 0xB65B, 0x8DCC, 0xB65E, 0x8DCD, 0xDBF2, 0x8DCE, 0xB659,	0x8DCF, 0xDBF6, 0x8DD0, 0xE06C, 0x8DD1, 0xB65D, 0x8DD3, 0xDBF1,
+	0x8DD5, 0xDBF7, 0x8DD6, 0xDBF4, 0x8DD7, 0xDBFA, 0x8DD8, 0xDBF0,	0x8DD9, 0xDBF8, 0x8DDA, 0xB65C, 0x8DDB, 0xB65F, 0x8DDC, 0xDBF5,
+	0x8DDD, 0xB65A, 0x8DDF, 0xB8F2, 0x8DE0, 0xE068, 0x8DE1, 0xB8F1,	0x8DE2, 0xE06F, 0x8DE3, 0xE06E, 0x8DE4, 0xB8F8, 0x8DE6, 0xB8F9,
+	0x8DE7, 0xE070, 0x8DE8, 0xB8F3, 0x8DE9, 0xE06D, 0x8DEA, 0xB8F7,	0x8DEB, 0xE072, 0x8DEC, 0xE069, 0x8DEE, 0xE06B, 0x8DEF, 0xB8F4,
+	0x8DF0, 0xE067, 0x8DF1, 0xE06A, 0x8DF2, 0xE071, 0x8DF3, 0xB8F5,	0x8DF4, 0xE073, 0x8DFA, 0xB8F6, 0x8DFC, 0xBBB1, 0x8DFD, 0xE45B,
+	0x8DFE, 0xE461, 0x8DFF, 0xE459, 0x8E00, 0xE462, 0x8E02, 0xE458,	0x8E03, 0xE45D, 0x8E04, 0xE463, 0x8E05, 0xE460, 0x8E06, 0xE45F,
+	0x8E07, 0xE45E, 0x8E09, 0xE457, 0x8E0A, 0xE45C, 0x8E0D, 0xE45A,	0x8E0F, 0xBDF1, 0x8E10, 0xBDEE, 0x8E11, 0xE7FB, 0x8E12, 0xE841,
+	0x8E13, 0xE843, 0x8E14, 0xE840, 0x8E15, 0xE7F8, 0x8E16, 0xE7FA,	0x8E17, 0xE845, 0x8E18, 0xE842, 0x8E19, 0xE7FC, 0x8E1A, 0xE846,
+	0x8E1B, 0xE7F9, 0x8E1C, 0xE844, 0x8E1D, 0xBDEF, 0x8E1E, 0xBDF5,	0x8E1F, 0xBDF3, 0x8E20, 0xE7F3, 0x8E21, 0xBDF4, 0x8E22, 0xBDF0,
+	0x8E23, 0xE7F4, 0x8E24, 0xE7F6, 0x8E25, 0xE7F5, 0x8E26, 0xE7FD,	0x8E27, 0xE7FE, 0x8E29, 0xBDF2, 0x8E2B, 0xBDED, 0x8E2E, 0xE7F7,
+	0x8E30, 0xEBC6, 0x8E31, 0xBFE2, 0x8E33, 0xEBBD, 0x8E34, 0xBFE3,	0x8E35, 0xBFE6, 0x8E36, 0xEBC2, 0x8E38, 0xEBBF, 0x8E39, 0xBFE5,
+	0x8E3C, 0xEBC3, 0x8E3D, 0xEBC4, 0x8E3E, 0xEBBE, 0x8E3F, 0xEBC7,	0x8E40, 0xEBC0, 0x8E41, 0xEBC5, 0x8E42, 0xBFE4, 0x8E44, 0xBFE1,
+	0x8E45, 0xEBC1, 0x8E47, 0xEEBF, 0x8E48, 0xC1D0, 0x8E49, 0xC1CE,	0x8E4A, 0xC1D1, 0x8E4B, 0xC1CF, 0x8E4C, 0xEEBE, 0x8E4D, 0xEEBB,
+	0x8E4E, 0xEEBA, 0x8E50, 0xEEBD, 0x8E53, 0xEEBC, 0x8E54, 0xF145,	0x8E55, 0xC2DE, 0x8E56, 0xF0FB, 0x8E57, 0xF0FA, 0x8E59, 0xC2D9,
+	0x8E5A, 0xF141, 0x8E5B, 0xF140, 0x8E5C, 0xF0F7, 0x8E5D, 0xF143,	0x8E5E, 0xF0FC, 0x8E5F, 0xC2DD, 0x8E60, 0xF0F9, 0x8E61, 0xF142,
+	0x8E62, 0xF0F8, 0x8E63, 0xC2DA, 0x8E64, 0xC2DC, 0x8E65, 0xF0FD,	0x8E66, 0xC2DB, 0x8E67, 0xF0FE, 0x8E69, 0xF144, 0x8E6A, 0xF352,
+	0x8E6C, 0xC3DE, 0x8E6D, 0xF34F, 0x8E6F, 0xF353, 0x8E72, 0xC3DB,	0x8E73, 0xF351, 0x8E74, 0xC3E0, 0x8E76, 0xC3DD, 0x8E78, 0xF350,
+	0x8E7A, 0xC3DF, 0x8E7B, 0xF354, 0x8E7C, 0xC3DA, 0x8E81, 0xC4BC,	0x8E82, 0xC4BE, 0x8E84, 0xF4D9, 0x8E85, 0xC4BD, 0x8E86, 0xF4D7,
+	0x8E87, 0xC3DC, 0x8E88, 0xF4D8, 0x8E89, 0xC4BB, 0x8E8A, 0xC543,	0x8E8B, 0xC545, 0x8E8C, 0xF656, 0x8E8D, 0xC544, 0x8E8E, 0xF655,
+	0x8E90, 0xF761, 0x8E91, 0xC5AD, 0x8E92, 0xF760, 0x8E93, 0xC5AE,	0x8E94, 0xF75E, 0x8E95, 0xF75D, 0x8E96, 0xF762, 0x8E97, 0xF763,
+	0x8E98, 0xF846, 0x8E9A, 0xF75F, 0x8E9D, 0xF8C6, 0x8E9E, 0xF8C3,	0x8E9F, 0xF8C4, 0x8EA0, 0xF8C5, 0x8EA1, 0xC65C, 0x8EA3, 0xF951,
+	0x8EA4, 0xF950, 0x8EA5, 0xF94F, 0x8EA6, 0xF970, 0x8EA8, 0xF9BE,	0x8EA9, 0xF9AB, 0x8EAA, 0xC66E, 0x8EAB, 0xA8AD, 0x8EAC, 0xB060,
+	0x8EB2, 0xB8FA, 0x8EBA, 0xBDF6, 0x8EBD, 0xEBC8, 0x8EC0, 0xC2DF,	0x8EC2, 0xF355, 0x8EC9, 0xF9AC, 0x8ECA, 0xA8AE, 0x8ECB, 0xAAEE,
+	0x8ECC, 0xAD79, 0x8ECD, 0xAD78, 0x8ECF, 0xB063, 0x8ED1, 0xD3E8,	0x8ED2, 0xB061, 0x8ED3, 0xD3E9, 0x8ED4, 0xB062, 0x8ED7, 0xD7DF,
+	0x8ED8, 0xD7DB, 0x8EDB, 0xB36D, 0x8EDC, 0xD7DE, 0x8EDD, 0xD7DD,	0x8EDE, 0xD7DC, 0x8EDF, 0xB36E, 0x8EE0, 0xD7E0, 0x8EE1, 0xD7E1,
+	0x8EE5, 0xDC43, 0x8EE6, 0xDC41, 0x8EE7, 0xDC45, 0x8EE8, 0xDC46,	0x8EE9, 0xDC4C, 0x8EEB, 0xDC48, 0x8EEC, 0xDC4A, 0x8EEE, 0xDC42,
+	0x8EEF, 0xDBFC, 0x8EF1, 0xDC49, 0x8EF4, 0xDC4B, 0x8EF5, 0xDC44,	0x8EF6, 0xDC47, 0x8EF7, 0xDBFD, 0x8EF8, 0xB662, 0x8EF9, 0xDC40,
+	0x8EFA, 0xDBFE, 0x8EFB, 0xB661, 0x8EFC, 0xB663, 0x8EFE, 0xB8FD,	0x8EFF, 0xE075, 0x8F00, 0xE077, 0x8F01, 0xE076, 0x8F02, 0xE07B,
+	0x8F03, 0xB8FB, 0x8F05, 0xE078, 0x8F06, 0xE074, 0x8F07, 0xE079,	0x8F08, 0xE07A, 0x8F09, 0xB8FC, 0x8F0A, 0xB8FE, 0x8F0B, 0xE07C,
+	0x8F0D, 0xE467, 0x8F0E, 0xE466, 0x8F10, 0xE464, 0x8F11, 0xE465,	0x8F12, 0xBBB3, 0x8F13, 0xBBB5, 0x8F14, 0xBBB2, 0x8F15, 0xBBB4,
+	0x8F16, 0xE84D, 0x8F17, 0xE84E, 0x8F18, 0xE849, 0x8F1A, 0xE84A,	0x8F1B, 0xBDF8, 0x8F1C, 0xBDFD, 0x8F1D, 0xBDF7, 0x8F1E, 0xBDFE,
+	0x8F1F, 0xBDF9, 0x8F20, 0xE84B, 0x8F23, 0xE84C, 0x8F24, 0xE848,	0x8F25, 0xBE40, 0x8F26, 0xBDFB, 0x8F29, 0xBDFA, 0x8F2A, 0xBDFC,
+	0x8F2C, 0xE847, 0x8F2E, 0xEBCA, 0x8F2F, 0xBFE8, 0x8F32, 0xEBCC,	0x8F33, 0xBFEA, 0x8F34, 0xEBCF, 0x8F35, 0xEBCB, 0x8F36, 0xEBC9,
+	0x8F37, 0xEBCE, 0x8F38, 0xBFE9, 0x8F39, 0xEBCD, 0x8F3B, 0xBFE7,	0x8F3E, 0xC1D3, 0x8F3F, 0xC1D6, 0x8F40, 0xEEC1, 0x8F42, 0xC1D4,
+	0x8F43, 0xEEC0, 0x8F44, 0xC1D2, 0x8F45, 0xC1D5, 0x8F46, 0xF146,	0x8F47, 0xF147, 0x8F48, 0xF148, 0x8F49, 0xC2E0, 0x8F4B, 0xF149,
+	0x8F4D, 0xC2E1, 0x8F4E, 0xC3E2, 0x8F4F, 0xF358, 0x8F50, 0xF359,	0x8F51, 0xF357, 0x8F52, 0xF356, 0x8F53, 0xF35A, 0x8F54, 0xC3E1,
+	0x8F55, 0xF4DD, 0x8F56, 0xF4DB, 0x8F57, 0xF4DC, 0x8F58, 0xF4DE,	0x8F59, 0xF4DA, 0x8F5A, 0xF4DF, 0x8F5B, 0xF658, 0x8F5D, 0xF659,
+	0x8F5E, 0xF657, 0x8F5F, 0xC546, 0x8F60, 0xF764, 0x8F61, 0xC5AF,	0x8F62, 0xF765, 0x8F63, 0xF848, 0x8F64, 0xF847, 0x8F9B, 0xA8AF,
+	0x8F9C, 0xB664, 0x8F9F, 0xB940, 0x8FA3, 0xBBB6, 0x8FA6, 0xBFEC,	0x8FA8, 0xBFEB, 0x8FAD, 0xC3E3, 0x8FAE, 0xC47C, 0x8FAF, 0xC547,
+	0x8FB0, 0xA8B0, 0x8FB1, 0xB064, 0x8FB2, 0xB941, 0x8FB4, 0xF35B,	0x8FBF, 0xCBA6, 0x8FC2, 0xA8B1, 0x8FC4, 0xA8B4, 0x8FC5, 0xA8B3,
+	0x8FC6, 0xA8B2, 0x8FC9, 0xCBA5, 0x8FCB, 0xCDCD, 0x8FCD, 0xCDCF,	0x8FCE, 0xAAEF, 0x8FD1, 0xAAF1, 0x8FD2, 0xCDCC, 0x8FD3, 0xCDCE,
+	0x8FD4, 0xAAF0, 0x8FD5, 0xCDD1, 0x8FD6, 0xCDD0, 0x8FD7, 0xCDD2,	0x8FE0, 0xD0B6, 0x8FE1, 0xD0B4, 0x8FE2, 0xAD7C, 0x8FE3, 0xD0B3,
+	0x8FE4, 0xADA3, 0x8FE5, 0xAD7E, 0x8FE6, 0xAD7B, 0x8FE8, 0xADA4,	0x8FEA, 0xAD7D, 0x8FEB, 0xADA2, 0x8FED, 0xADA1, 0x8FEE, 0xD0B5,
+	0x8FF0, 0xAD7A, 0x8FF4, 0xB06A, 0x8FF5, 0xD3EB, 0x8FF6, 0xD3F1,	0x8FF7, 0xB067, 0x8FF8, 0xB06E, 0x8FFA, 0xB069, 0x8FFB, 0xD3EE,
+	0x8FFC, 0xD3F0, 0x8FFD, 0xB06C, 0x8FFE, 0xD3EA, 0x8FFF, 0xD3ED,	0x9000, 0xB068, 0x9001, 0xB065, 0x9002, 0xD3EC, 0x9003, 0xB06B,
+	0x9004, 0xD3EF, 0x9005, 0xB06D, 0x9006, 0xB066, 0x900B, 0xD7E3,	0x900C, 0xD7E6, 0x900D, 0xB370, 0x900F, 0xB37A, 0x9010, 0xB376,
+	0x9011, 0xD7E4, 0x9014, 0xB37E, 0x9015, 0xB377, 0x9016, 0xB37C,	0x9017, 0xB372, 0x9019, 0xB36F, 0x901A, 0xB371, 0x901B, 0xB37D,
+	0x901C, 0xD7E5, 0x901D, 0xB375, 0x901E, 0xB378, 0x901F, 0xB374,	0x9020, 0xB379, 0x9021, 0xD7E7, 0x9022, 0xB37B, 0x9023, 0xB373,
+	0x9024, 0xD7E2, 0x902D, 0xDC4D, 0x902E, 0xB665, 0x902F, 0xDC4F,	0x9031, 0xB667, 0x9032, 0xB669, 0x9034, 0xDC4E, 0x9035, 0xB666,
+	0x9036, 0xB66A, 0x9038, 0xB668, 0x903C, 0xB947, 0x903D, 0xE0A3,	0x903E, 0xB94F, 0x903F, 0xE07E, 0x9041, 0xB950, 0x9042, 0xB945,
+	0x9044, 0xE0A1, 0x9047, 0xB94A, 0x9049, 0xE0A2, 0x904A, 0xB943,	0x904B, 0xB942, 0x904D, 0xB94D, 0x904E, 0xB94C, 0x904F, 0xB94B,
+	0x9050, 0xB949, 0x9051, 0xB94E, 0x9052, 0xE07D, 0x9053, 0xB944,	0x9054, 0xB946, 0x9055, 0xB948, 0x9058, 0xBBB8, 0x9059, 0xBBBB,
+	0x905B, 0xBBBF, 0x905C, 0xBBB9, 0x905D, 0xBBBE, 0x905E, 0xBBBC,	0x9060, 0xBBB7, 0x9062, 0xBBBD, 0x9063, 0xBBBA, 0x9067, 0xE852,
+	0x9068, 0xBE43, 0x9069, 0xBE41, 0x906B, 0xE853, 0x906D, 0xBE44,	0x906E, 0xBE42, 0x906F, 0xE851, 0x9070, 0xE850, 0x9072, 0xBFF0,
+	0x9073, 0xE84F, 0x9074, 0xBFEE, 0x9075, 0xBFED, 0x9076, 0xEBD0,	0x9077, 0xBE45, 0x9078, 0xBFEF, 0x9079, 0xEBD1, 0x907A, 0xBFF2,
+	0x907B, 0xEBD2, 0x907C, 0xBFF1, 0x907D, 0xC1D8, 0x907E, 0xEEC3,	0x907F, 0xC1D7, 0x9080, 0xC1DC, 0x9081, 0xC1DA, 0x9082, 0xC1DB,
+	0x9083, 0xC2E3, 0x9084, 0xC1D9, 0x9085, 0xEEC2, 0x9086, 0xEBD3,	0x9087, 0xC2E2, 0x9088, 0xC2E4, 0x908A, 0xC3E4, 0x908B, 0xC3E5,
+	0x908D, 0xF4E0, 0x908F, 0xC5DE, 0x9090, 0xC5DD, 0x9091, 0xA8B6,	0x9094, 0xCA55, 0x9095, 0xB06F, 0x9097, 0xCA52, 0x9098, 0xCA53,
+	0x9099, 0xCA51, 0x909B, 0xCA54, 0x909E, 0xCBAA, 0x909F, 0xCBA7,	0x90A0, 0xCBAC, 0x90A1, 0xCBA8, 0x90A2, 0xA8B7, 0x90A3, 0xA8BA,
+	0x90A5, 0xCBA9, 0x90A6, 0xA8B9, 0x90A7, 0xCBAB, 0x90AA, 0xA8B8,	0x90AF, 0xCDD5, 0x90B0, 0xCDD7, 0x90B1, 0xAAF4, 0x90B2, 0xCDD3,
+	0x90B3, 0xCDD6, 0x90B4, 0xCDD4, 0x90B5, 0xAAF2, 0x90B6, 0xAAF5,	0x90B8, 0xAAF3, 0x90BD, 0xD0B8, 0x90BE, 0xD0BC, 0x90BF, 0xD0B9,
+	0x90C1, 0xADA7, 0x90C3, 0xADA8, 0x90C5, 0xD0BB, 0x90C7, 0xD0BD,	0x90C8, 0xD0BF, 0x90CA, 0xADA5, 0x90CB, 0xD0BE, 0x90CE, 0xADA6,
+	0x90D4, 0xD7EE, 0x90D5, 0xD0BA, 0x90D6, 0xD3F2, 0x90D7, 0xD3FB,	0x90D8, 0xD3F9, 0x90D9, 0xD3F4, 0x90DA, 0xD3F5, 0x90DB, 0xD3FA,
+	0x90DC, 0xD3FC, 0x90DD, 0xB071, 0x90DF, 0xD3F7, 0x90E0, 0xD3F3,	0x90E1, 0xB070, 0x90E2, 0xB072, 0x90E3, 0xD3F6, 0x90E4, 0xD3FD,
+	0x90E5, 0xD3F8, 0x90E8, 0xB3A1, 0x90E9, 0xD7F1, 0x90EA, 0xD7E9,	0x90EB, 0xD7EF, 0x90EC, 0xD7F0, 0x90ED, 0xB3A2, 0x90EF, 0xD7E8,
+	0x90F0, 0xD7EA, 0x90F1, 0xD0B7, 0x90F2, 0xD7EC, 0x90F3, 0xD7ED,	0x90F4, 0xD7EB, 0x90F5, 0xB66C, 0x90F9, 0xDC56, 0x90FA, 0xEBD4,
+	0x90FB, 0xDC57, 0x90FC, 0xDC54, 0x90FD, 0xB3A3, 0x90FE, 0xB66E,	0x90FF, 0xDC53, 0x9100, 0xDC59, 0x9101, 0xDC58, 0x9102, 0xB66B,
+	0x9103, 0xDC5C, 0x9104, 0xDC52, 0x9105, 0xDC5B, 0x9106, 0xDC50,	0x9107, 0xDC5A, 0x9108, 0xDC55, 0x9109, 0xB66D, 0x910B, 0xE0AA,
+	0x910D, 0xE0A5, 0x910E, 0xE0AB, 0x910F, 0xE0A6, 0x9110, 0xE0A4,	0x9111, 0xE0A7, 0x9112, 0xB951, 0x9114, 0xE0A9, 0x9116, 0xE0A8,
+	0x9117, 0xB952, 0x9118, 0xBBC1, 0x9119, 0xBBC0, 0x911A, 0xE46E,	0x911B, 0xE471, 0x911C, 0xE469, 0x911D, 0xE46D, 0x911E, 0xBBC2,
+	0x911F, 0xE46C, 0x9120, 0xE46A, 0x9121, 0xE470, 0x9122, 0xE46B,	0x9123, 0xE468, 0x9124, 0xE46F, 0x9126, 0xE859, 0x9127, 0xBE48,
+	0x9128, 0xF14A, 0x9129, 0xE856, 0x912A, 0xE857, 0x912B, 0xE855,	0x912C, 0xDC51, 0x912D, 0xBE47, 0x912E, 0xE85A, 0x912F, 0xE854,
+	0x9130, 0xBE46, 0x9131, 0xBE49, 0x9132, 0xE858, 0x9133, 0xEBD5,	0x9134, 0xBFF3, 0x9135, 0xEBD6, 0x9136, 0xEBD7, 0x9138, 0xEEC4,
+	0x9139, 0xC1DD, 0x913A, 0xF14B, 0x913B, 0xF14C, 0x913E, 0xF14D,	0x913F, 0xF35D, 0x9140, 0xF35C, 0x9141, 0xF4E2, 0x9143, 0xF4E1,
+	0x9144, 0xF65B, 0x9145, 0xF65C, 0x9146, 0xF65A, 0x9147, 0xF766,	0x9148, 0xC5B0, 0x9149, 0xA8BB, 0x914A, 0xADAA, 0x914B, 0xADA9,
+	0x914C, 0xB075, 0x914D, 0xB074, 0x914E, 0xD440, 0x914F, 0xD441,	0x9150, 0xD3FE, 0x9152, 0xB073, 0x9153, 0xD7F5, 0x9155, 0xD7F6,
+	0x9156, 0xD7F2, 0x9157, 0xB3A4, 0x9158, 0xD7F3, 0x915A, 0xD7F4,	0x915F, 0xDC5F, 0x9160, 0xDC61, 0x9161, 0xDC5D, 0x9162, 0xDC60,
+	0x9163, 0xB66F, 0x9164, 0xDC5E, 0x9165, 0xB670, 0x9168, 0xDD73,	0x9169, 0xB955, 0x916A, 0xB954, 0x916C, 0xB953, 0x916E, 0xE0AC,
+	0x916F, 0xE0AD, 0x9172, 0xE473, 0x9173, 0xE475, 0x9174, 0xBBC6,	0x9175, 0xBBC3, 0x9177, 0xBBC5, 0x9178, 0xBBC4, 0x9179, 0xE474,
+	0x917A, 0xE472, 0x9180, 0xE861, 0x9181, 0xE85E, 0x9182, 0xE85F,	0x9183, 0xBE4D, 0x9184, 0xE860, 0x9185, 0xE85B, 0x9186, 0xE85C,
+	0x9187, 0xBE4A, 0x9189, 0xBE4B, 0x918A, 0xE85D, 0x918B, 0xBE4C,	0x918D, 0xEBDB, 0x918F, 0xEBDC, 0x9190, 0xEBD9, 0x9191, 0xEBDA,
+	0x9192, 0xBFF4, 0x9193, 0xEBD8, 0x9199, 0xEEC8, 0x919A, 0xEEC5,	0x919B, 0xEEC7, 0x919C, 0xC1E0, 0x919D, 0xEECB, 0x919E, 0xC1DF,
+	0x919F, 0xEEC9, 0x91A0, 0xEECC, 0x91A1, 0xEECA, 0x91A2, 0xEEC6,	0x91A3, 0xC1DE, 0x91A5, 0xF14F, 0x91A7, 0xF150, 0x91A8, 0xF14E,
+	0x91AA, 0xF152, 0x91AB, 0xC2E5, 0x91AC, 0xC2E6, 0x91AD, 0xF35F,	0x91AE, 0xC3E7, 0x91AF, 0xF151, 0x91B0, 0xF35E, 0x91B1, 0xC3E6,
+	0x91B2, 0xF4E5, 0x91B3, 0xF4E6, 0x91B4, 0xC4BF, 0x91B5, 0xF4E4,	0x91B7, 0xF4E3, 0x91B9, 0xF65D, 0x91BA, 0xC548, 0x91BC, 0xF849,
+	0x91BD, 0xF8C8, 0x91BE, 0xF8C7, 0x91C0, 0xC643, 0x91C1, 0xC65D,	0x91C2, 0xF8C9, 0x91C3, 0xF971, 0x91C5, 0xC66F, 0x91C6, 0xA8BC,
+	0x91C7, 0xAAF6, 0x91C9, 0xB956, 0x91CB, 0xC4C0, 0x91CC, 0xA8BD,	0x91CD, 0xADAB, 0x91CE, 0xB3A5, 0x91CF, 0xB671, 0x91D0, 0xC2E7,
+	0x91D1, 0xAAF7, 0x91D3, 0xD0C1, 0x91D4, 0xD0C0, 0x91D5, 0xD442,	0x91D7, 0xB078, 0x91D8, 0xB076, 0x91D9, 0xB07A, 0x91DA, 0xD444,
+	0x91DC, 0xB079, 0x91DD, 0xB077, 0x91E2, 0xD443, 0x91E3, 0xB3A8,	0x91E4, 0xD7FC, 0x91E6, 0xB3A7, 0x91E7, 0xB3A9, 0x91E8, 0xD842,
+	0x91E9, 0xB3AB, 0x91EA, 0xD7FE, 0x91EB, 0xD840, 0x91EC, 0xD7F7,	0x91ED, 0xB3AA, 0x91EE, 0xD843, 0x91F1, 0xD7F9, 0x91F3, 0xD7FA,
+	0x91F4, 0xD7F8, 0x91F5, 0xB3A6, 0x91F7, 0xD841, 0x91F8, 0xD7FB,	0x91F9, 0xD7FD, 0x91FD, 0xDC6D, 0x91FF, 0xDC6C, 0x9200, 0xDC6A,
+	0x9201, 0xDC62, 0x9202, 0xDC71, 0x9203, 0xDC65, 0x9204, 0xDC6F,	0x9205, 0xDC76, 0x9206, 0xDC6E, 0x9207, 0xB679, 0x9209, 0xB675,
+	0x920A, 0xDC63, 0x920C, 0xDC69, 0x920D, 0xB677, 0x920F, 0xDC68,	0x9210, 0xB678, 0x9211, 0xB67A, 0x9212, 0xDC6B, 0x9214, 0xB672,
+	0x9215, 0xB673, 0x9216, 0xDC77, 0x9217, 0xDC75, 0x9219, 0xDC74,	0x921A, 0xDC66, 0x921C, 0xDC72, 0x921E, 0xB676, 0x9223, 0xB674,
+	0x9224, 0xDC73, 0x9225, 0xDC64, 0x9226, 0xDC67, 0x9227, 0xDC70,	0x922D, 0xE4BA, 0x922E, 0xE0B7, 0x9230, 0xE0B0, 0x9231, 0xE0C3,
+	0x9232, 0xE0CC, 0x9233, 0xE0B3, 0x9234, 0xB961, 0x9236, 0xE0C0,	0x9237, 0xB957, 0x9238, 0xB959, 0x9239, 0xB965, 0x923A, 0xE0B1,
+	0x923D, 0xB95A, 0x923E, 0xB95C, 0x923F, 0xB966, 0x9240, 0xB95B,	0x9245, 0xB964, 0x9246, 0xE0B9, 0x9248, 0xE0AE, 0x9249, 0xB962,
+	0x924A, 0xE0B8, 0x924B, 0xB95E, 0x924C, 0xE0CA, 0x924D, 0xB963,	0x924E, 0xE0C8, 0x924F, 0xE0BC, 0x9250, 0xE0C6, 0x9251, 0xB960,
+	0x9252, 0xE0AF, 0x9253, 0xE0C9, 0x9254, 0xE0C4, 0x9256, 0xE0CB,	0x9257, 0xB958, 0x925A, 0xB967, 0x925B, 0xB95D, 0x925E, 0xE0B5,
+	0x9260, 0xE0BD, 0x9261, 0xE0C1, 0x9263, 0xE0C5, 0x9264, 0xB95F,	0x9265, 0xE0B4, 0x9266, 0xE0B2, 0x9267, 0xE0BE, 0x926C, 0xE0BB,
+	0x926D, 0xE0BA, 0x926F, 0xE0BF, 0x9270, 0xE0C2, 0x9272, 0xE0C7,	0x9276, 0xE478, 0x9278, 0xBBC7, 0x9279, 0xE4A4, 0x927A, 0xE47A,
+	0x927B, 0xBBCC, 0x927C, 0xBBD0, 0x927D, 0xE4AD, 0x927E, 0xE4B5,	0x927F, 0xE4A6, 0x9280, 0xBBC8, 0x9282, 0xE4AA, 0x9283, 0xE0B6,
+	0x9285, 0xBBC9, 0x9286, 0xE4B1, 0x9287, 0xE4B6, 0x9288, 0xE4AE,	0x928A, 0xE4B0, 0x928B, 0xE4B9, 0x928C, 0xE4B2, 0x928D, 0xE47E,
+	0x928E, 0xE4A9, 0x9291, 0xBBD1, 0x9293, 0xBBCD, 0x9294, 0xE47C,	0x9295, 0xE4AB, 0x9296, 0xBBCB, 0x9297, 0xE4A5, 0x9298, 0xBBCA,
+	0x9299, 0xE4B3, 0x929A, 0xE4A2, 0x929B, 0xE479, 0x929C, 0xBBCE,	0x929D, 0xE4B8, 0x92A0, 0xE47B, 0x92A1, 0xE4AF, 0x92A2, 0xE4AC,
+	0x92A3, 0xE4A7, 0x92A4, 0xE477, 0x92A5, 0xE476, 0x92A6, 0xE4A1,	0x92A7, 0xE4B4, 0x92A8, 0xBBCF, 0x92A9, 0xE4B7, 0x92AA, 0xE47D,
+	0x92AB, 0xE4A3, 0x92AC, 0xBE52, 0x92B2, 0xBE5A, 0x92B3, 0xBE55,	0x92B4, 0xE8A4, 0x92B5, 0xE8A1, 0x92B6, 0xE867, 0x92B7, 0xBE50,
+	0x92B9, 0xF9D7, 0x92BB, 0xBE4F, 0x92BC, 0xBE56, 0x92C0, 0xE865,	0x92C1, 0xBE54, 0x92C2, 0xE871, 0x92C3, 0xE863, 0x92C4, 0xE864,
+	0x92C5, 0xBE4E, 0x92C6, 0xE8A3, 0x92C7, 0xBE58, 0x92C8, 0xE874,	0x92C9, 0xE879, 0x92CA, 0xE873, 0x92CB, 0xEBEE, 0x92CC, 0xE86F,
+	0x92CD, 0xE877, 0x92CE, 0xE875, 0x92CF, 0xE868, 0x92D0, 0xE862,	0x92D1, 0xE87D, 0x92D2, 0xBE57, 0x92D3, 0xE87E, 0x92D5, 0xE878,
+	0x92D7, 0xE86D, 0x92D8, 0xE86B, 0x92D9, 0xE866, 0x92DD, 0xE86E,	0x92DE, 0xE87B, 0x92DF, 0xE86A, 0x92E0, 0xE87A, 0x92E1, 0xE8A2,
+	0x92E4, 0xBE53, 0x92E6, 0xE876, 0x92E7, 0xE87C, 0x92E8, 0xE872,	0x92E9, 0xE86C, 0x92EA, 0xBE51, 0x92EE, 0xE4A8, 0x92EF, 0xE870,
+	0x92F0, 0xBE59, 0x92F1, 0xE869, 0x92F7, 0xEBF4, 0x92F8, 0xBFF7,	0x92F9, 0xEBF3, 0x92FA, 0xEBF0, 0x92FB, 0xEC44, 0x92FC, 0xBFFB,
+	0x92FE, 0xEC41, 0x92FF, 0xEBF8, 0x9300, 0xEC43, 0x9301, 0xEBE9,	0x9302, 0xEBF6, 0x9304, 0xBFFD, 0x9306, 0xEBE1, 0x9308, 0xEBDF,
+	0x9309, 0xEC42, 0x930B, 0xEC40, 0x930C, 0xEBFE, 0x930D, 0xEBED,	0x930E, 0xEBEC, 0x930F, 0xEBE2, 0x9310, 0xC040, 0x9312, 0xEBE8,
+	0x9313, 0xEBF2, 0x9314, 0xEBFD, 0x9315, 0xC043, 0x9316, 0xEC45,	0x9318, 0xC1E8, 0x9319, 0xC045, 0x931A, 0xBFFE, 0x931B, 0xEBE6,
+	0x931D, 0xEBEF, 0x931E, 0xEBDE, 0x931F, 0xEBE0, 0x9320, 0xBFF5,	0x9321, 0xC042, 0x9322, 0xBFFA, 0x9323, 0xEBE7, 0x9324, 0xEBF7,
+	0x9325, 0xEBF1, 0x9326, 0xC041, 0x9327, 0xEBDD, 0x9328, 0xC1E3,	0x9329, 0xEBF9, 0x932A, 0xEBFC, 0x932B, 0xBFFC, 0x932D, 0xEBEB,
+	0x932E, 0xC044, 0x932F, 0xBFF9, 0x9333, 0xBFF8, 0x9334, 0xEBF5,	0x9335, 0xEBFB, 0x9336, 0xBFF6, 0x9338, 0xEBE4, 0x9339, 0xEBFA,
+	0x933C, 0xEBE5, 0x9346, 0xEBEA, 0x9347, 0xEED2, 0x9349, 0xEED7,	0x934A, 0xC1E5, 0x934B, 0xC1E7, 0x934C, 0xEEDD, 0x934D, 0xC1E1,
+	0x934E, 0xEEEC, 0x934F, 0xEEE3, 0x9350, 0xEED8, 0x9351, 0xEED9,	0x9352, 0xEEE2, 0x9354, 0xC1EE, 0x9355, 0xEEE1, 0x9356, 0xEED1,
+	0x9357, 0xEEE0, 0x9358, 0xEED4, 0x9359, 0xEEED, 0x935A, 0xC1ED,	0x935B, 0xC1EB, 0x935C, 0xEED5, 0x935E, 0xEEE8, 0x9360, 0xEEDA,
+	0x9361, 0xEEE7, 0x9363, 0xEEE9, 0x9364, 0xEED0, 0x9365, 0xC1E6,	0x9367, 0xEEEA, 0x936A, 0xEEDE, 0x936C, 0xC1EA, 0x936D, 0xEEDB,
+	0x9370, 0xC1EC, 0x9371, 0xEEE4, 0x9375, 0xC1E4, 0x9376, 0xEED6,	0x9377, 0xEEE5, 0x9379, 0xEEDF, 0x937A, 0xEBE3, 0x937B, 0xEEE6,
+	0x937C, 0xEED3, 0x937E, 0xC1E9, 0x9380, 0xEEEB, 0x9382, 0xC1E2,	0x9383, 0xEECE, 0x9388, 0xF160, 0x9389, 0xF159, 0x938A, 0xC2E9,
+	0x938C, 0xF154, 0x938D, 0xF163, 0x938E, 0xF15B, 0x938F, 0xEEDC,	0x9391, 0xF165, 0x9392, 0xF155, 0x9394, 0xC2E8, 0x9395, 0xF15F,
+	0x9396, 0xC2EA, 0x9397, 0xC2F2, 0x9398, 0xC2F0, 0x9399, 0xF161,	0x939A, 0xC2F1, 0x939B, 0xF157, 0x939D, 0xF158, 0x939E, 0xF15D,
+	0x939F, 0xF162, 0x93A1, 0xEECD, 0x93A2, 0xC2EB, 0x93A3, 0xF16A,	0x93A4, 0xF167, 0x93A5, 0xF16B, 0x93A6, 0xF15E, 0x93A7, 0xF15A,
+	0x93A8, 0xF168, 0x93A9, 0xF36A, 0x93AA, 0xF15C, 0x93AC, 0xC2EE,	0x93AE, 0xC2ED, 0x93AF, 0xEECF, 0x93B0, 0xC2EF, 0x93B1, 0xF164,
+	0x93B2, 0xF166, 0x93B3, 0xC2EC, 0x93B4, 0xF169, 0x93B5, 0xF153,	0x93B7, 0xF156, 0x93C0, 0xF373, 0x93C2, 0xF363, 0x93C3, 0xC3EB,
+	0x93C4, 0xF371, 0x93C7, 0xF361, 0x93C8, 0xC3EC, 0x93CA, 0xF36C,	0x93CC, 0xF368, 0x93CD, 0xC3F1, 0x93CE, 0xF372, 0x93CF, 0xF362,
+	0x93D0, 0xF365, 0x93D1, 0xC3E9, 0x93D2, 0xF374, 0x93D4, 0xF36D,	0x93D5, 0xF370, 0x93D6, 0xC3EF, 0x93D7, 0xC3F4, 0x93D8, 0xC3F2,
+	0x93D9, 0xF369, 0x93DA, 0xF364, 0x93DC, 0xC3ED, 0x93DD, 0xC3EE,	0x93DE, 0xF360, 0x93DF, 0xC3EA, 0x93E1, 0xC3E8, 0x93E2, 0xC3F0,
+	0x93E3, 0xF36F, 0x93E4, 0xC3F3, 0x93E6, 0xF36B, 0x93E7, 0xF375,	0x93E8, 0xC3F5, 0x93EC, 0xF367, 0x93EE, 0xF36E, 0x93F5, 0xF4F3,
+	0x93F6, 0xF542, 0x93F7, 0xF4F5, 0x93F8, 0xF4FC, 0x93F9, 0xF366,	0x93FA, 0xF4FA, 0x93FB, 0xF4E9, 0x93FC, 0xF540, 0x93FD, 0xC4C3,
+	0x93FE, 0xF4ED, 0x93FF, 0xF4FE, 0x9400, 0xF4F4, 0x9403, 0xC4C2,	0x9406, 0xF544, 0x9407, 0xF4F6, 0x9409, 0xF4FB, 0x940A, 0xF4FD,
+	0x940B, 0xF4E7, 0x940C, 0xF541, 0x940D, 0xF4F2, 0x940E, 0xF4F7,	0x940F, 0xF4EB, 0x9410, 0xF4EF, 0x9411, 0xF543, 0x9412, 0xF4F9,
+	0x9413, 0xF4E8, 0x9414, 0xF4EC, 0x9415, 0xF4EE, 0x9416, 0xF4F8,	0x9418, 0xC4C1, 0x9419, 0xF4F1, 0x9420, 0xF4EA, 0x9428, 0xF4F0,
+	0x9429, 0xF661, 0x942A, 0xF666, 0x942B, 0xC54F, 0x942C, 0xF668,	0x942E, 0xC549, 0x9430, 0xF664, 0x9431, 0xF66A, 0x9432, 0xC54E,
+	0x9433, 0xC54A, 0x9435, 0xC54B, 0x9436, 0xF660, 0x9437, 0xF667,	0x9438, 0xC54D, 0x9439, 0xF665, 0x943A, 0xC54C, 0x943B, 0xF65F,
+	0x943C, 0xF663, 0x943D, 0xF662, 0x943F, 0xF65E, 0x9440, 0xF669,	0x9444, 0xC5B1, 0x9445, 0xF76D, 0x9446, 0xF770, 0x9447, 0xF76C,
+	0x9448, 0xF76E, 0x9449, 0xF76F, 0x944A, 0xF769, 0x944B, 0xF76A,	0x944C, 0xF767, 0x944F, 0xF76B, 0x9450, 0xF768, 0x9451, 0xC5B2,
+	0x9452, 0xC5B3, 0x9455, 0xF84B, 0x9457, 0xF84D, 0x945D, 0xF84C,	0x945E, 0xF84E, 0x9460, 0xC5E0, 0x9462, 0xF84A, 0x9463, 0xC5DF,
+	0x9464, 0xC5E1, 0x9468, 0xF8CB, 0x9469, 0xF8CC, 0x946A, 0xC644,	0x946B, 0xF8CA, 0x946D, 0xF953, 0x946E, 0xF952, 0x946F, 0xF954,
+	0x9470, 0xC65F, 0x9471, 0xF955, 0x9472, 0xC65E, 0x9473, 0xF956,	0x9474, 0xF972, 0x9475, 0xF975, 0x9476, 0xF974, 0x9477, 0xC668,
+	0x9478, 0xF973, 0x947C, 0xC672, 0x947D, 0xC670, 0x947E, 0xC671,	0x947F, 0xC677, 0x9480, 0xF9C0, 0x9481, 0xF9C1, 0x9482, 0xF9BF,
+	0x9483, 0xF9C9, 0x9577, 0xAAF8, 0x957A, 0xD844, 0x957B, 0xDC78,	0x957C, 0xE8A5, 0x957D, 0xF376, 0x9580, 0xAAF9, 0x9582, 0xADAC,
+	0x9583, 0xB07B, 0x9586, 0xD845, 0x9588, 0xD846, 0x9589, 0xB3AC,	0x958B, 0xB67D, 0x958C, 0xDC7A, 0x958D, 0xDC79, 0x958E, 0xB6A3,
+	0x958F, 0xB67C, 0x9590, 0xDC7B, 0x9591, 0xB67E, 0x9592, 0xB6A2,	0x9593, 0xB6A1, 0x9594, 0xB67B, 0x9598, 0xB968, 0x959B, 0xE0D0,
+	0x959C, 0xE0CE, 0x959E, 0xE0CF, 0x959F, 0xE0CD, 0x95A1, 0xBBD2,	0x95A3, 0xBBD5, 0x95A4, 0xBBD7, 0x95A5, 0xBBD6, 0x95A8, 0xBBD3,
+	0x95A9, 0xBBD4, 0x95AB, 0xE8A7, 0x95AC, 0xE8A6, 0x95AD, 0xBE5B,	0x95AE, 0xE8A8, 0x95B0, 0xE8A9, 0x95B1, 0xBE5C, 0x95B5, 0xEC4D,
+	0x95B6, 0xEC4B, 0x95B7, 0xEEF3, 0x95B9, 0xEC49, 0x95BA, 0xEC4A,	0x95BB, 0xC046, 0x95BC, 0xEC46, 0x95BD, 0xEC4E, 0x95BE, 0xEC48,
+	0x95BF, 0xEC4C, 0x95C0, 0xEEEF, 0x95C3, 0xEEF1, 0x95C5, 0xEEF2,	0x95C6, 0xC1F3, 0x95C7, 0xEEEE, 0x95C8, 0xC1F2, 0x95C9, 0xEEF0,
+	0x95CA, 0xC1EF, 0x95CB, 0xC1F0, 0x95CC, 0xC1F1, 0x95CD, 0xEC47,	0x95D0, 0xC2F5, 0x95D1, 0xF16E, 0x95D2, 0xF16C, 0x95D3, 0xF16D,
+	0x95D4, 0xC2F3, 0x95D5, 0xC2F6, 0x95D6, 0xC2F4, 0x95DA, 0xF377,	0x95DB, 0xF378, 0x95DC, 0xC3F6, 0x95DE, 0xF545, 0x95DF, 0xF547,
+	0x95E0, 0xF546, 0x95E1, 0xC4C4, 0x95E2, 0xC550, 0x95E3, 0xF66D,	0x95E4, 0xF66C, 0x95E5, 0xF66B, 0x961C, 0xAAFA, 0x961E, 0xC9AA,
+	0x9620, 0xCA58, 0x9621, 0xA6E9, 0x9622, 0xCA56, 0x9623, 0xCA59,	0x9624, 0xCA57, 0x9628, 0xCBAE, 0x962A, 0xA8C1, 0x962C, 0xA8C2,
+	0x962D, 0xCBB0, 0x962E, 0xA8BF, 0x962F, 0xCBAF, 0x9630, 0xCBAD,	0x9631, 0xA8C0, 0x9632, 0xA8BE, 0x9639, 0xCDD8, 0x963A, 0xCDDB,
+	0x963B, 0xAAFD, 0x963C, 0xCDDA, 0x963D, 0xCDD9, 0x963F, 0xAAFC,	0x9640, 0xAAFB, 0x9642, 0xAB40, 0x9643, 0xCDDC, 0x9644, 0xAAFE,
+	0x964A, 0xD0C6, 0x964B, 0xADAE, 0x964C, 0xADAF, 0x964D, 0xADB0,	0x964E, 0xD0C7, 0x964F, 0xD0C3, 0x9650, 0xADAD, 0x9651, 0xD0C4,
+	0x9653, 0xD0C5, 0x9654, 0xD0C2, 0x9658, 0xB0A4, 0x965B, 0xB0A1,	0x965C, 0xD445, 0x965D, 0xB0A2, 0x965E, 0xB0A5, 0x965F, 0xD446,
+	0x9661, 0xB07E, 0x9662, 0xB07C, 0x9663, 0xB07D, 0x9664, 0xB0A3,	0x966A, 0xB3AD, 0x966B, 0xD849, 0x966C, 0xB3B5, 0x966D, 0xD848,
+	0x966F, 0xD84B, 0x9670, 0xB3B1, 0x9671, 0xD84A, 0x9672, 0xB6AB,	0x9673, 0xB3AF, 0x9674, 0xB3B2, 0x9675, 0xB3AE, 0x9676, 0xB3B3,
+	0x9677, 0xB3B4, 0x9678, 0xB3B0, 0x967C, 0xD847, 0x967D, 0xB6A7,	0x967E, 0xDC7D, 0x9680, 0xDCA3, 0x9683, 0xDCA2, 0x9684, 0xB6AC,
+	0x9685, 0xB6A8, 0x9686, 0xB6A9, 0x9687, 0xDC7C, 0x9688, 0xDC7E,	0x9689, 0xDCA1, 0x968A, 0xB6A4, 0x968B, 0xB6A6, 0x968D, 0xB6AA,
+	0x968E, 0xB6A5, 0x9691, 0xE0D3, 0x9692, 0xE0D1, 0x9693, 0xE0D2,	0x9694, 0xB96A, 0x9695, 0xB96B, 0x9697, 0xE0D4, 0x9698, 0xB969,
+	0x9699, 0xBBD8, 0x969B, 0xBBDA, 0x969C, 0xBBD9, 0x969E, 0xE4BB,	0x96A1, 0xE4BC, 0x96A2, 0xE8AB, 0x96A4, 0xE8AA, 0x96A7, 0xC047,
+	0x96A8, 0xC048, 0x96A9, 0xEC4F, 0x96AA, 0xC049, 0x96AC, 0xEEF6,	0x96AE, 0xEEF4, 0x96B0, 0xEEF5, 0x96B1, 0xC1F4, 0x96B3, 0xF16F,
+	0x96B4, 0xC3F7, 0x96B8, 0xC1F5, 0x96B9, 0xAB41, 0x96BB, 0xB0A6,	0x96BC, 0xD447, 0x96BF, 0xD84C, 0x96C0, 0xB3B6, 0x96C1, 0xB6AD,
+	0x96C2, 0xDCA4, 0x96C3, 0xDCA6, 0x96C4, 0xB6AF, 0x96C5, 0xB6AE,	0x96C6, 0xB6B0, 0x96C7, 0xB6B1, 0x96C8, 0xDCA5, 0x96C9, 0xB96E,
+	0x96CA, 0xB96F, 0x96CB, 0xB96D, 0x96CC, 0xBBDB, 0x96CD, 0xB96C,	0x96CE, 0xE0D5, 0x96D2, 0xBBDC, 0x96D3, 0xE8AC, 0x96D4, 0xEC50,
+	0x96D5, 0xC04A, 0x96D6, 0xC1F6, 0x96D7, 0xF170, 0x96D8, 0xF174,	0x96D9, 0xC2F9, 0x96DA, 0xF171, 0x96DB, 0xC2FA, 0x96DC, 0xC2F8,
+	0x96DD, 0xF175, 0x96DE, 0xC2FB, 0x96DF, 0xF173, 0x96E1, 0xF379,	0x96E2, 0xC2F7, 0x96E3, 0xC3F8, 0x96E5, 0xF8CD, 0x96E8, 0xAB42,
+	0x96E9, 0xB3B8, 0x96EA, 0xB3B7, 0x96EF, 0xB6B2, 0x96F0, 0xDCA8,	0x96F1, 0xDCA7, 0x96F2, 0xB6B3, 0x96F5, 0xE0D9, 0x96F6, 0xB973,
+	0x96F7, 0xB970, 0x96F8, 0xE0D8, 0x96F9, 0xB972, 0x96FA, 0xE0D6,	0x96FB, 0xB971, 0x96FD, 0xE0D7, 0x96FF, 0xE4BD, 0x9700, 0xBBDD,
+	0x9702, 0xE8AF, 0x9704, 0xBE5D, 0x9705, 0xE8AD, 0x9706, 0xBE5E,	0x9707, 0xBE5F, 0x9708, 0xE8AE, 0x9709, 0xBE60, 0x970B, 0xEC51,
+	0x970D, 0xC04E, 0x970E, 0xC04B, 0x970F, 0xC050, 0x9710, 0xEC53,	0x9711, 0xC04C, 0x9712, 0xEC52, 0x9713, 0xC04F, 0x9716, 0xC04D,
+	0x9718, 0xEEF9, 0x9719, 0xEEFB, 0x971C, 0xC1F7, 0x971D, 0xEEFA,	0x971E, 0xC1F8, 0x971F, 0xEEF8, 0x9720, 0xEEF7, 0x9722, 0xF177,
+	0x9723, 0xF176, 0x9724, 0xC2FC, 0x9725, 0xF178, 0x9726, 0xF37E,	0x9727, 0xC3FA, 0x9728, 0xF37D, 0x9729, 0xF37A, 0x972A, 0xC3F9,
+	0x972B, 0xF37B, 0x972C, 0xF37C, 0x972E, 0xF548, 0x972F, 0xF549,	0x9730, 0xC4C5, 0x9732, 0xC553, 0x9735, 0xF66E, 0x9738, 0xC551,
+	0x9739, 0xC552, 0x973A, 0xF66F, 0x973D, 0xC5B4, 0x973E, 0xC5B5,	0x973F, 0xF771, 0x9742, 0xC645, 0x9743, 0xF8CF, 0x9744, 0xC647,
+	0x9746, 0xF8CE, 0x9747, 0xF8D0, 0x9748, 0xC646, 0x9749, 0xF957,	0x974B, 0xF9AD, 0x9752, 0xAB43, 0x9756, 0xB974, 0x9758, 0xE4BE,
+	0x975A, 0xE8B0, 0x975B, 0xC051, 0x975C, 0xC052, 0x975E, 0xAB44,	0x9760, 0xBE61, 0x9761, 0xC3FB, 0x9762, 0xADB1, 0x9766, 0xC053,
+	0x9768, 0xC5E2, 0x9769, 0xADB2, 0x976A, 0xD84D, 0x976C, 0xDCA9,	0x976E, 0xDCAB, 0x9770, 0xDCAA, 0x9772, 0xE0DD, 0x9773, 0xE0DA,
+	0x9774, 0xB975, 0x9776, 0xB976, 0x9777, 0xE0DB, 0x9778, 0xE0DC,	0x977A, 0xE4C0, 0x977B, 0xE4C5, 0x977C, 0xBBDE, 0x977D, 0xE4BF,
+	0x977E, 0xE4C1, 0x977F, 0xE4C8, 0x9780, 0xE4C3, 0x9781, 0xE4C7,	0x9782, 0xE4C4, 0x9783, 0xE4C2, 0x9784, 0xE4C6, 0x9785, 0xBBDF,
+	0x9788, 0xE8B3, 0x978A, 0xE8B1, 0x978B, 0xBE63, 0x978D, 0xBE62,	0x978E, 0xE8B2, 0x978F, 0xBE64, 0x9794, 0xEC56, 0x9797, 0xEC55,
+	0x9798, 0xC054, 0x9799, 0xEC54, 0x979A, 0xEEFC, 0x979C, 0xEEFE,	0x979D, 0xEF41, 0x979E, 0xEF40, 0x97A0, 0xC1F9, 0x97A1, 0xEEFD,
+	0x97A2, 0xF1A1, 0x97A3, 0xC2FD, 0x97A4, 0xF17D, 0x97A5, 0xF1A2,	0x97A6, 0xC2FE, 0x97A8, 0xF17B, 0x97AA, 0xF17E, 0x97AB, 0xF17C,
+	0x97AC, 0xF179, 0x97AD, 0xC340, 0x97AE, 0xF17A, 0x97B3, 0xF3A1,	0x97B6, 0xF3A3, 0x97B7, 0xF3A2, 0x97B9, 0xF54A, 0x97BB, 0xF54B,
+	0x97BF, 0xF670, 0x97C1, 0xC5B7, 0x97C3, 0xC5B6, 0x97C4, 0xF84F,	0x97C5, 0xF850, 0x97C6, 0xC648, 0x97C7, 0xF8D1, 0x97C9, 0xC669,
+	0x97CB, 0xADB3, 0x97CC, 0xB6B4, 0x97CD, 0xE4CA, 0x97CE, 0xE4C9,	0x97CF, 0xE8B5, 0x97D0, 0xE8B4, 0x97D3, 0xC1FA, 0x97D4, 0xEF43,
+	0x97D5, 0xEF42, 0x97D6, 0xF1A5, 0x97D7, 0xF1A3, 0x97D8, 0xF1A6,	0x97D9, 0xF1A4, 0x97DC, 0xC3FC, 0x97DD, 0xF3A4, 0x97DE, 0xF3A5,
+	0x97DF, 0xF3A6, 0x97E1, 0xF671, 0x97E3, 0xF772, 0x97E5, 0xF8D2,	0x97ED, 0xADB4, 0x97F0, 0xEC57, 0x97F1, 0xEF44, 0x97F3, 0xADB5,
+	0x97F6, 0xBBE0, 0x97F8, 0xEC58, 0x97F9, 0xC341, 0x97FA, 0xF1A7,	0x97FB, 0xC3FD, 0x97FD, 0xF54C, 0x97FE, 0xF54D, 0x97FF, 0xC554,
+	0x9800, 0xF851, 0x9801, 0xADB6, 0x9802, 0xB3BB, 0x9803, 0xB3BC,	0x9804, 0xD84E, 0x9805, 0xB6B5, 0x9806, 0xB6B6, 0x9807, 0xDCAC,
+	0x9808, 0xB6B7, 0x980A, 0xB97A, 0x980C, 0xB97C, 0x980D, 0xE0DF,	0x980E, 0xE0E0, 0x980F, 0xE0DE, 0x9810, 0xB977, 0x9811, 0xB978,
+	0x9812, 0xB97B, 0x9813, 0xB979, 0x9816, 0xE4CB, 0x9817, 0xBBE1,	0x9818, 0xBBE2, 0x981B, 0xE8BC, 0x981C, 0xBE67, 0x981D, 0xE8B7,
+	0x981E, 0xE8B6, 0x9820, 0xE8BB, 0x9821, 0xBE65, 0x9824, 0xC05B,	0x9826, 0xE8B8, 0x9827, 0xE8BD, 0x9828, 0xE8BA, 0x9829, 0xE8B9,
+	0x982B, 0xBE66, 0x982D, 0xC059, 0x982F, 0xEC5A, 0x9830, 0xC055,	0x9832, 0xEC5B, 0x9835, 0xEC59, 0x9837, 0xC058, 0x9838, 0xC056,
+	0x9839, 0xC05A, 0x983B, 0xC057, 0x9841, 0xEF45, 0x9843, 0xEF4A,	0x9844, 0xEF46, 0x9845, 0xEF49, 0x9846, 0xC1FB, 0x9848, 0xEDD4,
+	0x9849, 0xEF48, 0x984A, 0xEF47, 0x984C, 0xC344, 0x984D, 0xC342,	0x984E, 0xC345, 0x984F, 0xC343, 0x9850, 0xF1A8, 0x9851, 0xF1A9,
+	0x9852, 0xF1AA, 0x9853, 0xC346, 0x9857, 0xF3AA, 0x9858, 0xC440,	0x9859, 0xF3A8, 0x985B, 0xC441, 0x985C, 0xF3A7, 0x985D, 0xF3A9,
+	0x985E, 0xC3FE, 0x985F, 0xF551, 0x9860, 0xF54E, 0x9862, 0xF54F,	0x9863, 0xF550, 0x9864, 0xF672, 0x9865, 0xC556, 0x9867, 0xC555,
+	0x9869, 0xF774, 0x986A, 0xF773, 0x986B, 0xC5B8, 0x986F, 0xC5E3,	0x9870, 0xC649, 0x9871, 0xC660, 0x9872, 0xF958, 0x9873, 0xF9AE,
+	0x9874, 0xF9AF, 0x98A8, 0xADB7, 0x98A9, 0xDCAD, 0x98AC, 0xE0E1,	0x98AD, 0xE4CC, 0x98AE, 0xE4CD, 0x98AF, 0xBBE3, 0x98B1, 0xBBE4,
+	0x98B2, 0xE8BE, 0x98B3, 0xBE68, 0x98B6, 0xC1FC, 0x98B8, 0xF1AB,	0x98BA, 0xC347, 0x98BB, 0xF3AD, 0x98BC, 0xC442, 0x98BD, 0xF3AC,
+	0x98BE, 0xF3AE, 0x98BF, 0xF3AB, 0x98C0, 0xF675, 0x98C1, 0xF552,	0x98C2, 0xF553, 0x98C4, 0xC4C6, 0x98C6, 0xF674, 0x98C9, 0xF673,
+	0x98CB, 0xF775, 0x98CC, 0xF9B0, 0x98DB, 0xADB8, 0x98DF, 0xADB9,	0x98E2, 0xB0A7, 0x98E3, 0xD448, 0x98E5, 0xD84F, 0x98E7, 0xB6B8,
+	0x98E9, 0xB6BB, 0x98EA, 0xB6B9, 0x98EB, 0xDCAE, 0x98ED, 0xB6BD,	0x98EF, 0xB6BA, 0x98F2, 0xB6BC, 0x98F4, 0xB97E, 0x98F6, 0xE0E2,
+	0x98F9, 0xE0E3, 0x98FA, 0xE8C0, 0x98FC, 0xB97D, 0x98FD, 0xB9A1,	0x98FE, 0xB9A2, 0x9900, 0xE4CF, 0x9902, 0xE4CE, 0x9903, 0xBBE5,
+	0x9905, 0xBBE6, 0x9907, 0xE4D0, 0x9908, 0xE8BF, 0x9909, 0xBBE8,	0x990A, 0xBE69, 0x990C, 0xBBE7, 0x9910, 0xC05C, 0x9911, 0xE8C1,
+	0x9912, 0xBE6B, 0x9913, 0xBE6A, 0x9914, 0xE8C2, 0x9915, 0xE8C5,	0x9916, 0xE8C3, 0x9917, 0xE8C4, 0x9918, 0xBE6C, 0x991A, 0xC061,
+	0x991B, 0xC05F, 0x991E, 0xC05E, 0x991F, 0xEC5D, 0x9921, 0xC060,	0x9924, 0xEC5C, 0x9925, 0xEF4B, 0x9927, 0xEC5E, 0x9928, 0xC05D,
+	0x9929, 0xEC5F, 0x992A, 0xEF4E, 0x992B, 0xEF4C, 0x992C, 0xEF4D,	0x992D, 0xEF52, 0x992E, 0xC34B, 0x992F, 0xEF51, 0x9930, 0xEF54,
+	0x9931, 0xEF53, 0x9932, 0xEF50, 0x9933, 0xEF4F, 0x9935, 0xC1FD,	0x993A, 0xF1AE, 0x993C, 0xF1AD, 0x993D, 0xC34A, 0x993E, 0xC348,
+	0x993F, 0xC349, 0x9941, 0xF1AC, 0x9943, 0xF3B1, 0x9945, 0xC443,	0x9947, 0xF3B0, 0x9948, 0xF3AF, 0x9949, 0xC444, 0x994B, 0xF558,
+	0x994C, 0xF557, 0x994E, 0xF555, 0x9950, 0xF554, 0x9951, 0xC4C8,	0x9952, 0xC4C7, 0x9953, 0xF559, 0x9954, 0xF776, 0x9955, 0xC5B9,
+	0x9956, 0xF677, 0x9957, 0xC557, 0x9958, 0xF676, 0x9959, 0xF556,	0x995B, 0xF777, 0x995C, 0xC5E4, 0x995E, 0xC661, 0x995F, 0xF959,
+	0x9961, 0xF9B1, 0x9996, 0xADBA, 0x9997, 0xD850, 0x9998, 0xEF55,	0x9999, 0xADBB, 0x999C, 0xE4D2, 0x999D, 0xE4D1, 0x999E, 0xEC60,
+	0x99A1, 0xEF57, 0x99A3, 0xEF56, 0x99A5, 0xC34C, 0x99A6, 0xF3B2,	0x99A7, 0xF3B3, 0x99A8, 0xC4C9, 0x99AB, 0xF9B2, 0x99AC, 0xB0A8,
+	0x99AD, 0xB6BF, 0x99AE, 0xB6BE, 0x99AF, 0xE0E4, 0x99B0, 0xE0E6,	0x99B1, 0xB9A4, 0x99B2, 0xE0E5, 0x99B3, 0xB9A3, 0x99B4, 0xB9A5,
+	0x99B5, 0xE0E7, 0x99B9, 0xE4D4, 0x99BA, 0xE4D6, 0x99BB, 0xE4D5,	0x99BD, 0xE4D8, 0x99C1, 0xBBE9, 0x99C2, 0xE4D7, 0x99C3, 0xE4D3,
+	0x99C7, 0xE4D9, 0x99C9, 0xE8CC, 0x99CB, 0xE8CF, 0x99CC, 0xE8D1,	0x99CD, 0xE8C7, 0x99CE, 0xE8CB, 0x99CF, 0xE8C8, 0x99D0, 0xBE6E,
+	0x99D1, 0xBE71, 0x99D2, 0xBE73, 0x99D3, 0xE8C9, 0x99D4, 0xE8CA,	0x99D5, 0xBE72, 0x99D6, 0xE8CD, 0x99D7, 0xE8D0, 0x99D8, 0xE8CE,
+	0x99D9, 0xBE74, 0x99DB, 0xBE70, 0x99DC, 0xE8C6, 0x99DD, 0xBE6D,	0x99DF, 0xBE6F, 0x99E2, 0xC063, 0x99E3, 0xEC66, 0x99E4, 0xEC64,
+	0x99E5, 0xEC63, 0x99E7, 0xEC69, 0x99E9, 0xEC68, 0x99EA, 0xEC67,	0x99EC, 0xEC62, 0x99ED, 0xC062, 0x99EE, 0xEC61, 0x99F0, 0xEC65,
+	0x99F1, 0xC064, 0x99F4, 0xEF5A, 0x99F6, 0xEF5E, 0x99F7, 0xEF5B,	0x99F8, 0xEF5D, 0x99F9, 0xEF5C, 0x99FA, 0xEF59, 0x99FB, 0xEF5F,
+	0x99FC, 0xEF62, 0x99FD, 0xEF60, 0x99FE, 0xEF61, 0x99FF, 0xC240,	0x9A01, 0xC1FE, 0x9A02, 0xEF58, 0x9A03, 0xEF63, 0x9A04, 0xF1B3,
+	0x9A05, 0xF1B6, 0x9A06, 0xF1B8, 0x9A07, 0xF1B7, 0x9A09, 0xF1B1,	0x9A0A, 0xF1B5, 0x9A0B, 0xF1B0, 0x9A0D, 0xF1B2, 0x9A0E, 0xC34D,
+	0x9A0F, 0xF1AF, 0x9A11, 0xF1B4, 0x9A14, 0xF3C0, 0x9A15, 0xF3B5,	0x9A16, 0xC445, 0x9A19, 0xC446, 0x9A1A, 0xF3B4, 0x9A1B, 0xF3B9,
+	0x9A1C, 0xF3BF, 0x9A1D, 0xF3B7, 0x9A1E, 0xF3BE, 0x9A20, 0xF3BB,	0x9A22, 0xF3BA, 0x9A23, 0xF3BD, 0x9A24, 0xF3B8, 0x9A25, 0xF3B6,
+	0x9A27, 0xF3BC, 0x9A29, 0xF560, 0x9A2A, 0xF55E, 0x9A2B, 0xC4CA,	0x9A2C, 0xF55D, 0x9A2D, 0xF563, 0x9A2E, 0xF561, 0x9A30, 0xC4CB,
+	0x9A31, 0xF55C, 0x9A32, 0xF55A, 0x9A34, 0xF55B, 0x9A35, 0xC4CD,	0x9A36, 0xF55F, 0x9A37, 0xC4CC, 0x9A38, 0xF562, 0x9A39, 0xF678,
+	0x9A3A, 0xF67E, 0x9A3D, 0xF679, 0x9A3E, 0xC55B, 0x9A3F, 0xF6A1,	0x9A40, 0xC55A, 0x9A41, 0xF67D, 0x9A42, 0xF67C, 0x9A43, 0xC559,
+	0x9A44, 0xF67B, 0x9A45, 0xC558, 0x9A46, 0xF67A, 0x9A48, 0xF77D,	0x9A49, 0xF7A1, 0x9A4A, 0xF77E, 0x9A4C, 0xF77B, 0x9A4D, 0xC5BB,
+	0x9A4E, 0xF778, 0x9A4F, 0xF77C, 0x9A50, 0xF7A3, 0x9A52, 0xF7A2,	0x9A53, 0xF779, 0x9A54, 0xF77A, 0x9A55, 0xC5BA, 0x9A56, 0xF852,
+	0x9A57, 0xC5E7, 0x9A59, 0xF853, 0x9A5A, 0xC5E5, 0x9A5B, 0xC5E6,	0x9A5E, 0xF8D3, 0x9A5F, 0xC64A, 0x9A60, 0xF976, 0x9A62, 0xC66A,
+	0x9A64, 0xF9B3, 0x9A65, 0xC66B, 0x9A66, 0xF9B4, 0x9A67, 0xF9B5,	0x9A68, 0xF9C3, 0x9A69, 0xF9C2, 0x9A6A, 0xC67A, 0x9A6B, 0xF9CD,
+	0x9AA8, 0xB0A9, 0x9AAB, 0xE0E9, 0x9AAD, 0xE0E8, 0x9AAF, 0xBBEA,	0x9AB0, 0xBBEB, 0x9AB1, 0xE4DA, 0x9AB3, 0xE8D2, 0x9AB4, 0xEC6C,
+	0x9AB7, 0xBE75, 0x9AB8, 0xC065, 0x9AB9, 0xEC6A, 0x9ABB, 0xEC6D,	0x9ABC, 0xC066, 0x9ABE, 0xEF64, 0x9ABF, 0xEC6B, 0x9AC0, 0xF1B9,
+	0x9AC1, 0xC34E, 0x9AC2, 0xF3C1, 0x9AC6, 0xF566, 0x9AC7, 0xF564,	0x9ACA, 0xF565, 0x9ACD, 0xF6A2, 0x9ACF, 0xC55C, 0x9AD0, 0xF7A4,
+	0x9AD1, 0xC5EA, 0x9AD2, 0xC5BC, 0x9AD3, 0xC5E8, 0x9AD4, 0xC5E9,	0x9AD5, 0xF8D4, 0x9AD6, 0xC662, 0x9AD8, 0xB0AA, 0x9ADC, 0xF1BA,
+	0x9ADF, 0xD449, 0x9AE1, 0xB9A6, 0x9AE3, 0xE4DB, 0x9AE6, 0xBBEC,	0x9AE7, 0xE4DC, 0x9AEB, 0xE8D4, 0x9AEC, 0xE8D3, 0x9AED, 0xC068,
+	0x9AEE, 0xBE76, 0x9AEF, 0xBE77, 0x9AF1, 0xE8D7, 0x9AF2, 0xE8D6,	0x9AF3, 0xE8D5, 0x9AF6, 0xEC6E, 0x9AF7, 0xEC71, 0x9AF9, 0xEC70,
+	0x9AFA, 0xEC6F, 0x9AFB, 0xC067, 0x9AFC, 0xEF68, 0x9AFD, 0xEF66,	0x9AFE, 0xEF65, 0x9B01, 0xEF67, 0x9B03, 0xC34F, 0x9B04, 0xF1BC,
+	0x9B05, 0xF1BD, 0x9B06, 0xC350, 0x9B08, 0xF1BB, 0x9B0A, 0xF3C3,	0x9B0B, 0xF3C2, 0x9B0C, 0xF3C5, 0x9B0D, 0xC447, 0x9B0E, 0xF3C4,
+	0x9B10, 0xF567, 0x9B11, 0xF569, 0x9B12, 0xF568, 0x9B15, 0xF6A3,	0x9B16, 0xF6A6, 0x9B17, 0xF6A4, 0x9B18, 0xF6A5, 0x9B19, 0xF7A5,
+	0x9B1A, 0xC5BD, 0x9B1E, 0xF854, 0x9B1F, 0xF855, 0x9B20, 0xF856,	0x9B22, 0xC64B, 0x9B23, 0xC663, 0x9B24, 0xF9B6, 0x9B25, 0xB0AB,
+	0x9B27, 0xBE78, 0x9B28, 0xC069, 0x9B29, 0xF1BE, 0x9B2B, 0xF7A6,	0x9B2E, 0xF9C4, 0x9B2F, 0xD44A, 0x9B31, 0xC67B, 0x9B32, 0xB0AC,
+	0x9B33, 0xEC72, 0x9B35, 0xF1BF, 0x9B37, 0xF3C6, 0x9B3A, 0xF6A7,	0x9B3B, 0xF7A7, 0x9B3C, 0xB0AD, 0x9B3E, 0xE4DD, 0x9B3F, 0xE4DE,
+	0x9B41, 0xBBED, 0x9B42, 0xBBEE, 0x9B43, 0xE8D9, 0x9B44, 0xBE7A,	0x9B45, 0xBE79, 0x9B46, 0xE8D8, 0x9B48, 0xEF69, 0x9B4A, 0xF1C0,
+	0x9B4B, 0xF1C2, 0x9B4C, 0xF1C1, 0x9B4D, 0xC353, 0x9B4E, 0xC352,	0x9B4F, 0xC351, 0x9B51, 0xC55E, 0x9B52, 0xF6A8, 0x9B54, 0xC55D,
+	0x9B55, 0xF7A9, 0x9B56, 0xF7A8, 0x9B58, 0xC64C, 0x9B59, 0xF8D5,	0x9B5A, 0xB3BD, 0x9B5B, 0xE0EA, 0x9B5F, 0xE4E1, 0x9B60, 0xE4DF,
+	0x9B61, 0xE4E0, 0x9B64, 0xE8E2, 0x9B66, 0xE8DD, 0x9B67, 0xE8DA,	0x9B68, 0xE8E1, 0x9B6C, 0xE8E3, 0x9B6F, 0xBE7C, 0x9B70, 0xE8E0,
+	0x9B71, 0xE8DC, 0x9B74, 0xE8DB, 0x9B75, 0xE8DF, 0x9B76, 0xE8DE,	0x9B77, 0xBE7B, 0x9B7A, 0xEC7D, 0x9B7B, 0xEC78, 0x9B7C, 0xEC76,
+	0x9B7D, 0xECA1, 0x9B7E, 0xEC77, 0x9B80, 0xEC73, 0x9B82, 0xEC79,	0x9B85, 0xEC74, 0x9B86, 0xEF72, 0x9B87, 0xEC75, 0x9B88, 0xECA2,
+	0x9B90, 0xEC7C, 0x9B91, 0xC06A, 0x9B92, 0xEC7B, 0x9B93, 0xEC7A,	0x9B95, 0xEC7E, 0x9B9A, 0xEF6A, 0x9B9B, 0xEF6D, 0x9B9E, 0xEF6C,
+	0x9BA0, 0xEF74, 0x9BA1, 0xEF6F, 0x9BA2, 0xEF73, 0x9BA4, 0xEF71,	0x9BA5, 0xEF70, 0x9BA6, 0xEF6E, 0x9BA8, 0xEF6B, 0x9BAA, 0xC243,
+	0x9BAB, 0xC242, 0x9BAD, 0xC244, 0x9BAE, 0xC241, 0x9BAF, 0xEF75,	0x9BB5, 0xF1C8, 0x9BB6, 0xF1CB, 0x9BB8, 0xF1C9, 0x9BB9, 0xF1CD,
+	0x9BBD, 0xF1CE, 0x9BBF, 0xF1C6, 0x9BC0, 0xC358, 0x9BC1, 0xF1C7,	0x9BC3, 0xF1C5, 0x9BC4, 0xF1CC, 0x9BC6, 0xF1C4, 0x9BC7, 0xF1C3,
+	0x9BC8, 0xC357, 0x9BC9, 0xC355, 0x9BCA, 0xC354, 0x9BD3, 0xF1CA,	0x9BD4, 0xF3CF, 0x9BD5, 0xF3D5, 0x9BD6, 0xC44A, 0x9BD7, 0xF3D0,
+	0x9BD9, 0xF3D3, 0x9BDA, 0xF3D7, 0x9BDB, 0xC44B, 0x9BDC, 0xF3D2,	0x9BDE, 0xF3CA, 0x9BE0, 0xF3C9, 0x9BE1, 0xF3D6, 0x9BE2, 0xF3CD,
+	0x9BE4, 0xF3CB, 0x9BE5, 0xF3D4, 0x9BE6, 0xF3CC, 0x9BE7, 0xC449,	0x9BE8, 0xC448, 0x9BEA, 0xF3C7, 0x9BEB, 0xF3C8, 0x9BEC, 0xF3D1,
+	0x9BF0, 0xF3CE, 0x9BF7, 0xF56C, 0x9BF8, 0xF56F, 0x9BFD, 0xC356,	0x9C05, 0xF56D, 0x9C06, 0xF573, 0x9C07, 0xF571, 0x9C08, 0xF56B,
+	0x9C09, 0xF576, 0x9C0B, 0xF56A, 0x9C0D, 0xC4CF, 0x9C0E, 0xF572,	0x9C12, 0xF56E, 0x9C13, 0xC4CE, 0x9C14, 0xF575, 0x9C17, 0xF574,
+	0x9C1C, 0xF6AB, 0x9C1D, 0xF6AA, 0x9C21, 0xF6B1, 0x9C23, 0xF6AD,	0x9C24, 0xF6B0, 0x9C25, 0xC560, 0x9C28, 0xF6AE, 0x9C29, 0xF6AF,
+	0x9C2B, 0xF6A9, 0x9C2C, 0xF6AC, 0x9C2D, 0xC55F, 0x9C31, 0xC5BF,	0x9C32, 0xF7B4, 0x9C33, 0xF7AF, 0x9C34, 0xF7B3, 0x9C36, 0xF7B6,
+	0x9C37, 0xF7B2, 0x9C39, 0xF7AE, 0x9C3B, 0xC5C1, 0x9C3C, 0xF7B1,	0x9C3D, 0xF7B5, 0x9C3E, 0xC5C0, 0x9C3F, 0xF7AC, 0x9C40, 0xF570,
+	0x9C41, 0xF7B0, 0x9C44, 0xF7AD, 0x9C46, 0xF7AA, 0x9C48, 0xF7AB,	0x9C49, 0xC5BE, 0x9C4A, 0xF85A, 0x9C4B, 0xF85C, 0x9C4C, 0xF85F,
+	0x9C4D, 0xF85B, 0x9C4E, 0xF860, 0x9C50, 0xF859, 0x9C52, 0xF857,	0x9C54, 0xC5EB, 0x9C55, 0xF85D, 0x9C56, 0xC5ED, 0x9C57, 0xC5EC,
+	0x9C58, 0xF858, 0x9C59, 0xF85E, 0x9C5E, 0xF8DA, 0x9C5F, 0xC64D,	0x9C60, 0xF8DB, 0x9C62, 0xF8D9, 0x9C63, 0xF8D6, 0x9C66, 0xF8D8,
+	0x9C67, 0xF8D7, 0x9C68, 0xF95A, 0x9C6D, 0xF95C, 0x9C6E, 0xF95B,	0x9C71, 0xF979, 0x9C73, 0xF978, 0x9C74, 0xF977, 0x9C75, 0xF97A,
+	0x9C77, 0xC673, 0x9C78, 0xC674, 0x9C79, 0xF9CA, 0x9C7A, 0xF9CE,	0x9CE5, 0xB3BE, 0x9CE6, 0xDCAF, 0x9CE7, 0xE0ED, 0x9CE9, 0xB9A7,
+	0x9CEA, 0xE0EB, 0x9CED, 0xE0EC, 0x9CF1, 0xE4E2, 0x9CF2, 0xE4E3,	0x9CF3, 0xBBF1, 0x9CF4, 0xBBEF, 0x9CF5, 0xE4E4, 0x9CF6, 0xBBF0,
+	0x9CF7, 0xE8E8, 0x9CF9, 0xE8EB, 0x9CFA, 0xE8E5, 0x9CFB, 0xE8EC,	0x9CFC, 0xE8E4, 0x9CFD, 0xE8E6, 0x9CFF, 0xE8E7, 0x9D00, 0xE8EA,
+	0x9D03, 0xBEA1, 0x9D04, 0xE8EF, 0x9D05, 0xE8EE, 0x9D06, 0xBE7D,	0x9D07, 0xE8E9, 0x9D08, 0xE8ED, 0x9D09, 0xBE7E, 0x9D10, 0xECAC,
+	0x9D12, 0xC06F, 0x9D14, 0xECA7, 0x9D15, 0xC06B, 0x9D17, 0xECA4,	0x9D18, 0xECAA, 0x9D19, 0xECAD, 0x9D1B, 0xC070, 0x9D1D, 0xECA9,
+	0x9D1E, 0xECA6, 0x9D1F, 0xECAE, 0x9D20, 0xECA5, 0x9D22, 0xECAB,	0x9D23, 0xC06C, 0x9D25, 0xECA3, 0x9D26, 0xC06D, 0x9D28, 0xC06E,
+	0x9D29, 0xECA8, 0x9D2D, 0xEFA9, 0x9D2E, 0xEF7A, 0x9D2F, 0xEF7B,	0x9D30, 0xEF7E, 0x9D31, 0xEF7C, 0x9D33, 0xEF76, 0x9D36, 0xEF79,
+	0x9D37, 0xEFA5, 0x9D38, 0xEF7D, 0x9D3B, 0xC245, 0x9D3D, 0xEFA7,	0x9D3E, 0xEFA4, 0x9D3F, 0xC246, 0x9D40, 0xEFA6, 0x9D41, 0xEF77,
+	0x9D42, 0xEFA2, 0x9D43, 0xEFA3, 0x9D45, 0xEFA1, 0x9D4A, 0xF1D2,	0x9D4B, 0xF1D4, 0x9D4C, 0xF1D7, 0x9D4F, 0xF1D1, 0x9D51, 0xC359,
+	0x9D52, 0xF1D9, 0x9D53, 0xF1D0, 0x9D54, 0xF1DA, 0x9D56, 0xF1D6,	0x9D57, 0xF1D8, 0x9D58, 0xF1DC, 0x9D59, 0xF1D5, 0x9D5A, 0xF1DD,
+	0x9D5B, 0xF1D3, 0x9D5C, 0xF1CF, 0x9D5D, 0xC35A, 0x9D5F, 0xF1DB,	0x9D60, 0xC35B, 0x9D61, 0xC44D, 0x9D67, 0xEF78, 0x9D68, 0xF3F1,
+	0x9D69, 0xF3E8, 0x9D6A, 0xC44F, 0x9D6B, 0xF3E4, 0x9D6C, 0xC450,	0x9D6F, 0xF3ED, 0x9D70, 0xF3E7, 0x9D71, 0xF3DD, 0x9D72, 0xC44E,
+	0x9D73, 0xF3EA, 0x9D74, 0xF3E5, 0x9D75, 0xF3E6, 0x9D77, 0xF3D8,	0x9D78, 0xF3DF, 0x9D79, 0xF3EE, 0x9D7B, 0xF3EB, 0x9D7D, 0xF3E3,
+	0x9D7F, 0xF3EF, 0x9D80, 0xF3DE, 0x9D81, 0xF3D9, 0x9D82, 0xF3EC,	0x9D84, 0xF3DB, 0x9D85, 0xF3E9, 0x9D86, 0xF3E0, 0x9D87, 0xF3F0,
+	0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1,	0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2,
+	0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578,	0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A,
+	0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6,	0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF,
+	0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4,	0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3,
+	0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD,	0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF,
+	0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9,	0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB,
+	0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7,	0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE,
+	0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8,	0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3,
+	0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7,	0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF,
+	0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867,	0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0,
+	0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A,	0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871,
+	0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862,	0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861,
+	0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2,	0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7,
+	0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4,	0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F,
+	0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B,	0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678,
+	0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF,	0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651,
+	0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0,	0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB,
+	0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC,	0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453,
+	0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3,	0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF,
+	0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1,	0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2,
+	0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7,	0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3,
+	0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE,	0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248,
+	0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072,	0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF,
+	0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249,	0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4,
+	0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB,	0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8,
+	0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964,	0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6,
+	0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1,	0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652,
+	0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2,	0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D,
+	0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0,	0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB,
+	0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4,	0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5,
+	0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3,	0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA,
+	0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B,	0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D,
+	0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D,	0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4,
+	0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9,	0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5,
+	0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC,	0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD,
+	0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6,	0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569,
+	0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5,	0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1,
+	0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED,	0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969,
+	0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365,	0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE,
+	0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF,	0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A,
+	0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F,	0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167,
+	0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F,	0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177,
+	0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6,	0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8,
+	0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E,	0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153,
+	0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1,	0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC,
+	0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF,	0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242,
+	0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149,	0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE,
+	0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF,	0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE,
+	0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2,	0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6,
+	0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146,	0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148,
+	0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1,	0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5,
+	0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9,	0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD,
+	0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1,	0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5,
+	0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240,	0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB,
+	0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF,	0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3,
+	0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7,	0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB,
+	0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340,	0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161,
+	0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246,	0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0
+};
+
+static const WCHAR oem2uni950[] = {	/* Big5 --> Unicode pairs */
+	0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002,	0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A,
+	0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026,	0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52,
+	0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56,	0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31,
+	0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34,	0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35,
+	0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37,	0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39,
+	0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B,	0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D,
+	0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F,	0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41,
+	0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43,	0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B,
+	0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018,	0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D,
+	0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03,	0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7,
+	0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3,	0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605,
+	0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0,	0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105,
+	0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD,	0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E,
+	0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60,	0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7,
+	0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C,	0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267,
+	0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261,	0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65,
+	0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A,	0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF,
+	0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E,	0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642,
+	0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193,	0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197,
+	0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223,	0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68,
+	0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0,	0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103,
+	0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B,	0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E,
+	0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F,	0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B,
+	0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163,	0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581,
+	0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585,	0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F,
+	0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B,	0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534,
+	0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594,	0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C,
+	0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D,	0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550,
+	0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2,	0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571,
+	0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11,	0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15,
+	0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19,	0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163,
+	0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167,	0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022,
+	0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026,	0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341,
+	0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22,	0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26,
+	0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A,	0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E,
+	0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32,	0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36,
+	0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A,	0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44,
+	0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48,	0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C,
+	0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50,	0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54,
+	0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58,	0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392,
+	0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396,	0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A,
+	0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E,	0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3,
+	0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7,	0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2,
+	0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6,	0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA,
+	0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE,	0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3,
+	0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7,	0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106,
+	0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A,	0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E,
+	0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112,	0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116,
+	0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A,	0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E,
+	0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122,	0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126,
+	0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9,	0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB,
+	0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01,	0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86,
+	0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165,	0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201,
+	0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C,	0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08,
+	0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1,	0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E,
+	0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203,	0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3,
+	0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927,	0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53,
+	0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38,	0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1,
+	0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72,	0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D,
+	0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D,	0xA4A5, 0x4E30, 0xA4A6, 0x4E39, 0xA4A7, 0x4E4B, 0xA4A8, 0x5C39,
+	0xA4A9, 0x4E88, 0xA4AA, 0x4E91, 0xA4AB, 0x4E95, 0xA4AC, 0x4E92,	0xA4AD, 0x4E94, 0xA4AE, 0x4EA2, 0xA4AF, 0x4EC1, 0xA4B0, 0x4EC0,
+	0xA4B1, 0x4EC3, 0xA4B2, 0x4EC6, 0xA4B3, 0x4EC7, 0xA4B4, 0x4ECD,	0xA4B5, 0x4ECA, 0xA4B6, 0x4ECB, 0xA4B7, 0x4EC4, 0xA4B8, 0x5143,
+	0xA4B9, 0x5141, 0xA4BA, 0x5167, 0xA4BB, 0x516D, 0xA4BC, 0x516E,	0xA4BD, 0x516C, 0xA4BE, 0x5197, 0xA4BF, 0x51F6, 0xA4C0, 0x5206,
+	0xA4C1, 0x5207, 0xA4C2, 0x5208, 0xA4C3, 0x52FB, 0xA4C4, 0x52FE,	0xA4C5, 0x52FF, 0xA4C6, 0x5316, 0xA4C7, 0x5339, 0xA4C8, 0x5348,
+	0xA4C9, 0x5347, 0xA4CA, 0x5345, 0xA4CB, 0x535E, 0xA4CC, 0x5384,	0xA4CD, 0x53CB, 0xA4CE, 0x53CA, 0xA4CF, 0x53CD, 0xA4D0, 0x58EC,
+	0xA4D1, 0x5929, 0xA4D2, 0x592B, 0xA4D3, 0x592A, 0xA4D4, 0x592D,	0xA4D5, 0x5B54, 0xA4D6, 0x5C11, 0xA4D7, 0x5C24, 0xA4D8, 0x5C3A,
+	0xA4D9, 0x5C6F, 0xA4DA, 0x5DF4, 0xA4DB, 0x5E7B, 0xA4DC, 0x5EFF,	0xA4DD, 0x5F14, 0xA4DE, 0x5F15, 0xA4DF, 0x5FC3, 0xA4E0, 0x6208,
+	0xA4E1, 0x6236, 0xA4E2, 0x624B, 0xA4E3, 0x624E, 0xA4E4, 0x652F,	0xA4E5, 0x6587, 0xA4E6, 0x6597, 0xA4E7, 0x65A4, 0xA4E8, 0x65B9,
+	0xA4E9, 0x65E5, 0xA4EA, 0x66F0, 0xA4EB, 0x6708, 0xA4EC, 0x6728,	0xA4ED, 0x6B20, 0xA4EE, 0x6B62, 0xA4EF, 0x6B79, 0xA4F0, 0x6BCB,
+	0xA4F1, 0x6BD4, 0xA4F2, 0x6BDB, 0xA4F3, 0x6C0F, 0xA4F4, 0x6C34,	0xA4F5, 0x706B, 0xA4F6, 0x722A, 0xA4F7, 0x7236, 0xA4F8, 0x723B,
+	0xA4F9, 0x7247, 0xA4FA, 0x7259, 0xA4FB, 0x725B, 0xA4FC, 0x72AC,	0xA4FD, 0x738B, 0xA4FE, 0x4E19, 0xA540, 0x4E16, 0xA541, 0x4E15,
+	0xA542, 0x4E14, 0xA543, 0x4E18, 0xA544, 0x4E3B, 0xA545, 0x4E4D,	0xA546, 0x4E4F, 0xA547, 0x4E4E, 0xA548, 0x4EE5, 0xA549, 0x4ED8,
+	0xA54A, 0x4ED4, 0xA54B, 0x4ED5, 0xA54C, 0x4ED6, 0xA54D, 0x4ED7,	0xA54E, 0x4EE3, 0xA54F, 0x4EE4, 0xA550, 0x4ED9, 0xA551, 0x4EDE,
+	0xA552, 0x5145, 0xA553, 0x5144, 0xA554, 0x5189, 0xA555, 0x518A,	0xA556, 0x51AC, 0xA557, 0x51F9, 0xA558, 0x51FA, 0xA559, 0x51F8,
+	0xA55A, 0x520A, 0xA55B, 0x52A0, 0xA55C, 0x529F, 0xA55D, 0x5305,	0xA55E, 0x5306, 0xA55F, 0x5317, 0xA560, 0x531D, 0xA561, 0x4EDF,
+	0xA562, 0x534A, 0xA563, 0x5349, 0xA564, 0x5361, 0xA565, 0x5360,	0xA566, 0x536F, 0xA567, 0x536E, 0xA568, 0x53BB, 0xA569, 0x53EF,
+	0xA56A, 0x53E4, 0xA56B, 0x53F3, 0xA56C, 0x53EC, 0xA56D, 0x53EE,	0xA56E, 0x53E9, 0xA56F, 0x53E8, 0xA570, 0x53FC, 0xA571, 0x53F8,
+	0xA572, 0x53F5, 0xA573, 0x53EB, 0xA574, 0x53E6, 0xA575, 0x53EA,	0xA576, 0x53F2, 0xA577, 0x53F1, 0xA578, 0x53F0, 0xA579, 0x53E5,
+	0xA57A, 0x53ED, 0xA57B, 0x53FB, 0xA57C, 0x56DB, 0xA57D, 0x56DA,	0xA57E, 0x5916, 0xA5A1, 0x592E, 0xA5A2, 0x5931, 0xA5A3, 0x5974,
+	0xA5A4, 0x5976, 0xA5A5, 0x5B55, 0xA5A6, 0x5B83, 0xA5A7, 0x5C3C,	0xA5A8, 0x5DE8, 0xA5A9, 0x5DE7, 0xA5AA, 0x5DE6, 0xA5AB, 0x5E02,
+	0xA5AC, 0x5E03, 0xA5AD, 0x5E73, 0xA5AE, 0x5E7C, 0xA5AF, 0x5F01,	0xA5B0, 0x5F18, 0xA5B1, 0x5F17, 0xA5B2, 0x5FC5, 0xA5B3, 0x620A,
+	0xA5B4, 0x6253, 0xA5B5, 0x6254, 0xA5B6, 0x6252, 0xA5B7, 0x6251,	0xA5B8, 0x65A5, 0xA5B9, 0x65E6, 0xA5BA, 0x672E, 0xA5BB, 0x672C,
+	0xA5BC, 0x672A, 0xA5BD, 0x672B, 0xA5BE, 0x672D, 0xA5BF, 0x6B63,	0xA5C0, 0x6BCD, 0xA5C1, 0x6C11, 0xA5C2, 0x6C10, 0xA5C3, 0x6C38,
+	0xA5C4, 0x6C41, 0xA5C5, 0x6C40, 0xA5C6, 0x6C3E, 0xA5C7, 0x72AF,	0xA5C8, 0x7384, 0xA5C9, 0x7389, 0xA5CA, 0x74DC, 0xA5CB, 0x74E6,
+	0xA5CC, 0x7518, 0xA5CD, 0x751F, 0xA5CE, 0x7528, 0xA5CF, 0x7529,	0xA5D0, 0x7530, 0xA5D1, 0x7531, 0xA5D2, 0x7532, 0xA5D3, 0x7533,
+	0xA5D4, 0x758B, 0xA5D5, 0x767D, 0xA5D6, 0x76AE, 0xA5D7, 0x76BF,	0xA5D8, 0x76EE, 0xA5D9, 0x77DB, 0xA5DA, 0x77E2, 0xA5DB, 0x77F3,
+	0xA5DC, 0x793A, 0xA5DD, 0x79BE, 0xA5DE, 0x7A74, 0xA5DF, 0x7ACB,	0xA5E0, 0x4E1E, 0xA5E1, 0x4E1F, 0xA5E2, 0x4E52, 0xA5E3, 0x4E53,
+	0xA5E4, 0x4E69, 0xA5E5, 0x4E99, 0xA5E6, 0x4EA4, 0xA5E7, 0x4EA6,	0xA5E8, 0x4EA5, 0xA5E9, 0x4EFF, 0xA5EA, 0x4F09, 0xA5EB, 0x4F19,
+	0xA5EC, 0x4F0A, 0xA5ED, 0x4F15, 0xA5EE, 0x4F0D, 0xA5EF, 0x4F10,	0xA5F0, 0x4F11, 0xA5F1, 0x4F0F, 0xA5F2, 0x4EF2, 0xA5F3, 0x4EF6,
+	0xA5F4, 0x4EFB, 0xA5F5, 0x4EF0, 0xA5F6, 0x4EF3, 0xA5F7, 0x4EFD,	0xA5F8, 0x4F01, 0xA5F9, 0x4F0B, 0xA5FA, 0x5149, 0xA5FB, 0x5147,
+	0xA5FC, 0x5146, 0xA5FD, 0x5148, 0xA5FE, 0x5168, 0xA640, 0x5171,	0xA641, 0x518D, 0xA642, 0x51B0, 0xA643, 0x5217, 0xA644, 0x5211,
+	0xA645, 0x5212, 0xA646, 0x520E, 0xA647, 0x5216, 0xA648, 0x52A3,	0xA649, 0x5308, 0xA64A, 0x5321, 0xA64B, 0x5320, 0xA64C, 0x5370,
+	0xA64D, 0x5371, 0xA64E, 0x5409, 0xA64F, 0x540F, 0xA650, 0x540C,	0xA651, 0x540A, 0xA652, 0x5410, 0xA653, 0x5401, 0xA654, 0x540B,
+	0xA655, 0x5404, 0xA656, 0x5411, 0xA657, 0x540D, 0xA658, 0x5408,	0xA659, 0x5403, 0xA65A, 0x540E, 0xA65B, 0x5406, 0xA65C, 0x5412,
+	0xA65D, 0x56E0, 0xA65E, 0x56DE, 0xA65F, 0x56DD, 0xA660, 0x5733,	0xA661, 0x5730, 0xA662, 0x5728, 0xA663, 0x572D, 0xA664, 0x572C,
+	0xA665, 0x572F, 0xA666, 0x5729, 0xA667, 0x5919, 0xA668, 0x591A,	0xA669, 0x5937, 0xA66A, 0x5938, 0xA66B, 0x5984, 0xA66C, 0x5978,
+	0xA66D, 0x5983, 0xA66E, 0x597D, 0xA66F, 0x5979, 0xA670, 0x5982,	0xA671, 0x5981, 0xA672, 0x5B57, 0xA673, 0x5B58, 0xA674, 0x5B87,
+	0xA675, 0x5B88, 0xA676, 0x5B85, 0xA677, 0x5B89, 0xA678, 0x5BFA,	0xA679, 0x5C16, 0xA67A, 0x5C79, 0xA67B, 0x5DDE, 0xA67C, 0x5E06,
+	0xA67D, 0x5E76, 0xA67E, 0x5E74, 0xA6A1, 0x5F0F, 0xA6A2, 0x5F1B,	0xA6A3, 0x5FD9, 0xA6A4, 0x5FD6, 0xA6A5, 0x620E, 0xA6A6, 0x620C,
+	0xA6A7, 0x620D, 0xA6A8, 0x6210, 0xA6A9, 0x6263, 0xA6AA, 0x625B,	0xA6AB, 0x6258, 0xA6AC, 0x6536, 0xA6AD, 0x65E9, 0xA6AE, 0x65E8,
+	0xA6AF, 0x65EC, 0xA6B0, 0x65ED, 0xA6B1, 0x66F2, 0xA6B2, 0x66F3,	0xA6B3, 0x6709, 0xA6B4, 0x673D, 0xA6B5, 0x6734, 0xA6B6, 0x6731,
+	0xA6B7, 0x6735, 0xA6B8, 0x6B21, 0xA6B9, 0x6B64, 0xA6BA, 0x6B7B,	0xA6BB, 0x6C16, 0xA6BC, 0x6C5D, 0xA6BD, 0x6C57, 0xA6BE, 0x6C59,
+	0xA6BF, 0x6C5F, 0xA6C0, 0x6C60, 0xA6C1, 0x6C50, 0xA6C2, 0x6C55,	0xA6C3, 0x6C61, 0xA6C4, 0x6C5B, 0xA6C5, 0x6C4D, 0xA6C6, 0x6C4E,
+	0xA6C7, 0x7070, 0xA6C8, 0x725F, 0xA6C9, 0x725D, 0xA6CA, 0x767E,	0xA6CB, 0x7AF9, 0xA6CC, 0x7C73, 0xA6CD, 0x7CF8, 0xA6CE, 0x7F36,
+	0xA6CF, 0x7F8A, 0xA6D0, 0x7FBD, 0xA6D1, 0x8001, 0xA6D2, 0x8003,	0xA6D3, 0x800C, 0xA6D4, 0x8012, 0xA6D5, 0x8033, 0xA6D6, 0x807F,
+	0xA6D7, 0x8089, 0xA6D8, 0x808B, 0xA6D9, 0x808C, 0xA6DA, 0x81E3,	0xA6DB, 0x81EA, 0xA6DC, 0x81F3, 0xA6DD, 0x81FC, 0xA6DE, 0x820C,
+	0xA6DF, 0x821B, 0xA6E0, 0x821F, 0xA6E1, 0x826E, 0xA6E2, 0x8272,	0xA6E3, 0x827E, 0xA6E4, 0x866B, 0xA6E5, 0x8840, 0xA6E6, 0x884C,
+	0xA6E7, 0x8863, 0xA6E8, 0x897F, 0xA6E9, 0x9621, 0xA6EA, 0x4E32,	0xA6EB, 0x4EA8, 0xA6EC, 0x4F4D, 0xA6ED, 0x4F4F, 0xA6EE, 0x4F47,
+	0xA6EF, 0x4F57, 0xA6F0, 0x4F5E, 0xA6F1, 0x4F34, 0xA6F2, 0x4F5B,	0xA6F3, 0x4F55, 0xA6F4, 0x4F30, 0xA6F5, 0x4F50, 0xA6F6, 0x4F51,
+	0xA6F7, 0x4F3D, 0xA6F8, 0x4F3A, 0xA6F9, 0x4F38, 0xA6FA, 0x4F43,	0xA6FB, 0x4F54, 0xA6FC, 0x4F3C, 0xA6FD, 0x4F46, 0xA6FE, 0x4F63,
+	0xA740, 0x4F5C, 0xA741, 0x4F60, 0xA742, 0x4F2F, 0xA743, 0x4F4E,	0xA744, 0x4F36, 0xA745, 0x4F59, 0xA746, 0x4F5D, 0xA747, 0x4F48,
+	0xA748, 0x4F5A, 0xA749, 0x514C, 0xA74A, 0x514B, 0xA74B, 0x514D,	0xA74C, 0x5175, 0xA74D, 0x51B6, 0xA74E, 0x51B7, 0xA74F, 0x5225,
+	0xA750, 0x5224, 0xA751, 0x5229, 0xA752, 0x522A, 0xA753, 0x5228,	0xA754, 0x52AB, 0xA755, 0x52A9, 0xA756, 0x52AA, 0xA757, 0x52AC,
+	0xA758, 0x5323, 0xA759, 0x5373, 0xA75A, 0x5375, 0xA75B, 0x541D,	0xA75C, 0x542D, 0xA75D, 0x541E, 0xA75E, 0x543E, 0xA75F, 0x5426,
+	0xA760, 0x544E, 0xA761, 0x5427, 0xA762, 0x5446, 0xA763, 0x5443,	0xA764, 0x5433, 0xA765, 0x5448, 0xA766, 0x5442, 0xA767, 0x541B,
+	0xA768, 0x5429, 0xA769, 0x544A, 0xA76A, 0x5439, 0xA76B, 0x543B,	0xA76C, 0x5438, 0xA76D, 0x542E, 0xA76E, 0x5435, 0xA76F, 0x5436,
+	0xA770, 0x5420, 0xA771, 0x543C, 0xA772, 0x5440, 0xA773, 0x5431,	0xA774, 0x542B, 0xA775, 0x541F, 0xA776, 0x542C, 0xA777, 0x56EA,
+	0xA778, 0x56F0, 0xA779, 0x56E4, 0xA77A, 0x56EB, 0xA77B, 0x574A,	0xA77C, 0x5751, 0xA77D, 0x5740, 0xA77E, 0x574D, 0xA7A1, 0x5747,
+	0xA7A2, 0x574E, 0xA7A3, 0x573E, 0xA7A4, 0x5750, 0xA7A5, 0x574F,	0xA7A6, 0x573B, 0xA7A7, 0x58EF, 0xA7A8, 0x593E, 0xA7A9, 0x599D,
+	0xA7AA, 0x5992, 0xA7AB, 0x59A8, 0xA7AC, 0x599E, 0xA7AD, 0x59A3,	0xA7AE, 0x5999, 0xA7AF, 0x5996, 0xA7B0, 0x598D, 0xA7B1, 0x59A4,
+	0xA7B2, 0x5993, 0xA7B3, 0x598A, 0xA7B4, 0x59A5, 0xA7B5, 0x5B5D,	0xA7B6, 0x5B5C, 0xA7B7, 0x5B5A, 0xA7B8, 0x5B5B, 0xA7B9, 0x5B8C,
+	0xA7BA, 0x5B8B, 0xA7BB, 0x5B8F, 0xA7BC, 0x5C2C, 0xA7BD, 0x5C40,	0xA7BE, 0x5C41, 0xA7BF, 0x5C3F, 0xA7C0, 0x5C3E, 0xA7C1, 0x5C90,
+	0xA7C2, 0x5C91, 0xA7C3, 0x5C94, 0xA7C4, 0x5C8C, 0xA7C5, 0x5DEB,	0xA7C6, 0x5E0C, 0xA7C7, 0x5E8F, 0xA7C8, 0x5E87, 0xA7C9, 0x5E8A,
+	0xA7CA, 0x5EF7, 0xA7CB, 0x5F04, 0xA7CC, 0x5F1F, 0xA7CD, 0x5F64,	0xA7CE, 0x5F62, 0xA7CF, 0x5F77, 0xA7D0, 0x5F79, 0xA7D1, 0x5FD8,
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+	0xB0A5, 0x965E, 0xB0A6, 0x96BB, 0xB0A7, 0x98E2, 0xB0A8, 0x99AC,	0xB0A9, 0x9AA8, 0xB0AA, 0x9AD8, 0xB0AB, 0x9B25, 0xB0AC, 0x9B32,
+	0xB0AD, 0x9B3C, 0xB0AE, 0x4E7E, 0xB0AF, 0x507A, 0xB0B0, 0x507D,	0xB0B1, 0x505C, 0xB0B2, 0x5047, 0xB0B3, 0x5043, 0xB0B4, 0x504C,
+	0xB0B5, 0x505A, 0xB0B6, 0x5049, 0xB0B7, 0x5065, 0xB0B8, 0x5076,	0xB0B9, 0x504E, 0xB0BA, 0x5055, 0xB0BB, 0x5075, 0xB0BC, 0x5074,
+	0xB0BD, 0x5077, 0xB0BE, 0x504F, 0xB0BF, 0x500F, 0xB0C0, 0x506F,	0xB0C1, 0x506D, 0xB0C2, 0x515C, 0xB0C3, 0x5195, 0xB0C4, 0x51F0,
+	0xB0C5, 0x526A, 0xB0C6, 0x526F, 0xB0C7, 0x52D2, 0xB0C8, 0x52D9,	0xB0C9, 0x52D8, 0xB0CA, 0x52D5, 0xB0CB, 0x5310, 0xB0CC, 0x530F,
+	0xB0CD, 0x5319, 0xB0CE, 0x533F, 0xB0CF, 0x5340, 0xB0D0, 0x533E,	0xB0D1, 0x53C3, 0xB0D2, 0x66FC, 0xB0D3, 0x5546, 0xB0D4, 0x556A,
+	0xB0D5, 0x5566, 0xB0D6, 0x5544, 0xB0D7, 0x555E, 0xB0D8, 0x5561,	0xB0D9, 0x5543, 0xB0DA, 0x554A, 0xB0DB, 0x5531, 0xB0DC, 0x5556,
+	0xB0DD, 0x554F, 0xB0DE, 0x5555, 0xB0DF, 0x552F, 0xB0E0, 0x5564,	0xB0E1, 0x5538, 0xB0E2, 0x552E, 0xB0E3, 0x555C, 0xB0E4, 0x552C,
+	0xB0E5, 0x5563, 0xB0E6, 0x5533, 0xB0E7, 0x5541, 0xB0E8, 0x5557,	0xB0E9, 0x5708, 0xB0EA, 0x570B, 0xB0EB, 0x5709, 0xB0EC, 0x57DF,
+	0xB0ED, 0x5805, 0xB0EE, 0x580A, 0xB0EF, 0x5806, 0xB0F0, 0x57E0,	0xB0F1, 0x57E4, 0xB0F2, 0x57FA, 0xB0F3, 0x5802, 0xB0F4, 0x5835,
+	0xB0F5, 0x57F7, 0xB0F6, 0x57F9, 0xB0F7, 0x5920, 0xB0F8, 0x5962,	0xB0F9, 0x5A36, 0xB0FA, 0x5A41, 0xB0FB, 0x5A49, 0xB0FC, 0x5A66,
+	0xB0FD, 0x5A6A, 0xB0FE, 0x5A40, 0xB140, 0x5A3C, 0xB141, 0x5A62,	0xB142, 0x5A5A, 0xB143, 0x5A46, 0xB144, 0x5A4A, 0xB145, 0x5B70,
+	0xB146, 0x5BC7, 0xB147, 0x5BC5, 0xB148, 0x5BC4, 0xB149, 0x5BC2,	0xB14A, 0x5BBF, 0xB14B, 0x5BC6, 0xB14C, 0x5C09, 0xB14D, 0x5C08,
+	0xB14E, 0x5C07, 0xB14F, 0x5C60, 0xB150, 0x5C5C, 0xB151, 0x5C5D,	0xB152, 0x5D07, 0xB153, 0x5D06, 0xB154, 0x5D0E, 0xB155, 0x5D1B,
+	0xB156, 0x5D16, 0xB157, 0x5D22, 0xB158, 0x5D11, 0xB159, 0x5D29,	0xB15A, 0x5D14, 0xB15B, 0x5D19, 0xB15C, 0x5D24, 0xB15D, 0x5D27,
+	0xB15E, 0x5D17, 0xB15F, 0x5DE2, 0xB160, 0x5E38, 0xB161, 0x5E36,	0xB162, 0x5E33, 0xB163, 0x5E37, 0xB164, 0x5EB7, 0xB165, 0x5EB8,
+	0xB166, 0x5EB6, 0xB167, 0x5EB5, 0xB168, 0x5EBE, 0xB169, 0x5F35,	0xB16A, 0x5F37, 0xB16B, 0x5F57, 0xB16C, 0x5F6C, 0xB16D, 0x5F69,
+	0xB16E, 0x5F6B, 0xB16F, 0x5F97, 0xB170, 0x5F99, 0xB171, 0x5F9E,	0xB172, 0x5F98, 0xB173, 0x5FA1, 0xB174, 0x5FA0, 0xB175, 0x5F9C,
+	0xB176, 0x607F, 0xB177, 0x60A3, 0xB178, 0x6089, 0xB179, 0x60A0,	0xB17A, 0x60A8, 0xB17B, 0x60CB, 0xB17C, 0x60B4, 0xB17D, 0x60E6,
+	0xB17E, 0x60BD, 0xB1A1, 0x60C5, 0xB1A2, 0x60BB, 0xB1A3, 0x60B5,	0xB1A4, 0x60DC, 0xB1A5, 0x60BC, 0xB1A6, 0x60D8, 0xB1A7, 0x60D5,
+	0xB1A8, 0x60C6, 0xB1A9, 0x60DF, 0xB1AA, 0x60B8, 0xB1AB, 0x60DA,	0xB1AC, 0x60C7, 0xB1AD, 0x621A, 0xB1AE, 0x621B, 0xB1AF, 0x6248,
+	0xB1B0, 0x63A0, 0xB1B1, 0x63A7, 0xB1B2, 0x6372, 0xB1B3, 0x6396,	0xB1B4, 0x63A2, 0xB1B5, 0x63A5, 0xB1B6, 0x6377, 0xB1B7, 0x6367,
+	0xB1B8, 0x6398, 0xB1B9, 0x63AA, 0xB1BA, 0x6371, 0xB1BB, 0x63A9,	0xB1BC, 0x6389, 0xB1BD, 0x6383, 0xB1BE, 0x639B, 0xB1BF, 0x636B,
+	0xB1C0, 0x63A8, 0xB1C1, 0x6384, 0xB1C2, 0x6388, 0xB1C3, 0x6399,	0xB1C4, 0x63A1, 0xB1C5, 0x63AC, 0xB1C6, 0x6392, 0xB1C7, 0x638F,
+	0xB1C8, 0x6380, 0xB1C9, 0x637B, 0xB1CA, 0x6369, 0xB1CB, 0x6368,	0xB1CC, 0x637A, 0xB1CD, 0x655D, 0xB1CE, 0x6556, 0xB1CF, 0x6551,
+	0xB1D0, 0x6559, 0xB1D1, 0x6557, 0xB1D2, 0x555F, 0xB1D3, 0x654F,	0xB1D4, 0x6558, 0xB1D5, 0x6555, 0xB1D6, 0x6554, 0xB1D7, 0x659C,
+	0xB1D8, 0x659B, 0xB1D9, 0x65AC, 0xB1DA, 0x65CF, 0xB1DB, 0x65CB,	0xB1DC, 0x65CC, 0xB1DD, 0x65CE, 0xB1DE, 0x665D, 0xB1DF, 0x665A,
+	0xB1E0, 0x6664, 0xB1E1, 0x6668, 0xB1E2, 0x6666, 0xB1E3, 0x665E,	0xB1E4, 0x66F9, 0xB1E5, 0x52D7, 0xB1E6, 0x671B, 0xB1E7, 0x6881,
+	0xB1E8, 0x68AF, 0xB1E9, 0x68A2, 0xB1EA, 0x6893, 0xB1EB, 0x68B5,	0xB1EC, 0x687F, 0xB1ED, 0x6876, 0xB1EE, 0x68B1, 0xB1EF, 0x68A7,
+	0xB1F0, 0x6897, 0xB1F1, 0x68B0, 0xB1F2, 0x6883, 0xB1F3, 0x68C4,	0xB1F4, 0x68AD, 0xB1F5, 0x6886, 0xB1F6, 0x6885, 0xB1F7, 0x6894,
+	0xB1F8, 0x689D, 0xB1F9, 0x68A8, 0xB1FA, 0x689F, 0xB1FB, 0x68A1,	0xB1FC, 0x6882, 0xB1FD, 0x6B32, 0xB1FE, 0x6BBA, 0xB240, 0x6BEB,
+	0xB241, 0x6BEC, 0xB242, 0x6C2B, 0xB243, 0x6D8E, 0xB244, 0x6DBC,	0xB245, 0x6DF3, 0xB246, 0x6DD9, 0xB247, 0x6DB2, 0xB248, 0x6DE1,
+	0xB249, 0x6DCC, 0xB24A, 0x6DE4, 0xB24B, 0x6DFB, 0xB24C, 0x6DFA,	0xB24D, 0x6E05, 0xB24E, 0x6DC7, 0xB24F, 0x6DCB, 0xB250, 0x6DAF,
+	0xB251, 0x6DD1, 0xB252, 0x6DAE, 0xB253, 0x6DDE, 0xB254, 0x6DF9,	0xB255, 0x6DB8, 0xB256, 0x6DF7, 0xB257, 0x6DF5, 0xB258, 0x6DC5,
+	0xB259, 0x6DD2, 0xB25A, 0x6E1A, 0xB25B, 0x6DB5, 0xB25C, 0x6DDA,	0xB25D, 0x6DEB, 0xB25E, 0x6DD8, 0xB25F, 0x6DEA, 0xB260, 0x6DF1,
+	0xB261, 0x6DEE, 0xB262, 0x6DE8, 0xB263, 0x6DC6, 0xB264, 0x6DC4,	0xB265, 0x6DAA, 0xB266, 0x6DEC, 0xB267, 0x6DBF, 0xB268, 0x6DE6,
+	0xB269, 0x70F9, 0xB26A, 0x7109, 0xB26B, 0x710A, 0xB26C, 0x70FD,	0xB26D, 0x70EF, 0xB26E, 0x723D, 0xB26F, 0x727D, 0xB270, 0x7281,
+	0xB271, 0x731C, 0xB272, 0x731B, 0xB273, 0x7316, 0xB274, 0x7313,	0xB275, 0x7319, 0xB276, 0x7387, 0xB277, 0x7405, 0xB278, 0x740A,
+	0xB279, 0x7403, 0xB27A, 0x7406, 0xB27B, 0x73FE, 0xB27C, 0x740D,	0xB27D, 0x74E0, 0xB27E, 0x74F6, 0xB2A1, 0x74F7, 0xB2A2, 0x751C,
+	0xB2A3, 0x7522, 0xB2A4, 0x7565, 0xB2A5, 0x7566, 0xB2A6, 0x7562,	0xB2A7, 0x7570, 0xB2A8, 0x758F, 0xB2A9, 0x75D4, 0xB2AA, 0x75D5,
+	0xB2AB, 0x75B5, 0xB2AC, 0x75CA, 0xB2AD, 0x75CD, 0xB2AE, 0x768E,	0xB2AF, 0x76D4, 0xB2B0, 0x76D2, 0xB2B1, 0x76DB, 0xB2B2, 0x7737,
+	0xB2B3, 0x773E, 0xB2B4, 0x773C, 0xB2B5, 0x7736, 0xB2B6, 0x7738,	0xB2B7, 0x773A, 0xB2B8, 0x786B, 0xB2B9, 0x7843, 0xB2BA, 0x784E,
+	0xB2BB, 0x7965, 0xB2BC, 0x7968, 0xB2BD, 0x796D, 0xB2BE, 0x79FB,	0xB2BF, 0x7A92, 0xB2C0, 0x7A95, 0xB2C1, 0x7B20, 0xB2C2, 0x7B28,
+	0xB2C3, 0x7B1B, 0xB2C4, 0x7B2C, 0xB2C5, 0x7B26, 0xB2C6, 0x7B19,	0xB2C7, 0x7B1E, 0xB2C8, 0x7B2E, 0xB2C9, 0x7C92, 0xB2CA, 0x7C97,
+	0xB2CB, 0x7C95, 0xB2CC, 0x7D46, 0xB2CD, 0x7D43, 0xB2CE, 0x7D71,	0xB2CF, 0x7D2E, 0xB2D0, 0x7D39, 0xB2D1, 0x7D3C, 0xB2D2, 0x7D40,
+	0xB2D3, 0x7D30, 0xB2D4, 0x7D33, 0xB2D5, 0x7D44, 0xB2D6, 0x7D2F,	0xB2D7, 0x7D42, 0xB2D8, 0x7D32, 0xB2D9, 0x7D31, 0xB2DA, 0x7F3D,
+	0xB2DB, 0x7F9E, 0xB2DC, 0x7F9A, 0xB2DD, 0x7FCC, 0xB2DE, 0x7FCE,	0xB2DF, 0x7FD2, 0xB2E0, 0x801C, 0xB2E1, 0x804A, 0xB2E2, 0x8046,
+	0xB2E3, 0x812F, 0xB2E4, 0x8116, 0xB2E5, 0x8123, 0xB2E6, 0x812B,	0xB2E7, 0x8129, 0xB2E8, 0x8130, 0xB2E9, 0x8124, 0xB2EA, 0x8202,
+	0xB2EB, 0x8235, 0xB2EC, 0x8237, 0xB2ED, 0x8236, 0xB2EE, 0x8239,	0xB2EF, 0x838E, 0xB2F0, 0x839E, 0xB2F1, 0x8398, 0xB2F2, 0x8378,
+	0xB2F3, 0x83A2, 0xB2F4, 0x8396, 0xB2F5, 0x83BD, 0xB2F6, 0x83AB,	0xB2F7, 0x8392, 0xB2F8, 0x838A, 0xB2F9, 0x8393, 0xB2FA, 0x8389,
+	0xB2FB, 0x83A0, 0xB2FC, 0x8377, 0xB2FD, 0x837B, 0xB2FE, 0x837C,	0xB340, 0x8386, 0xB341, 0x83A7, 0xB342, 0x8655, 0xB343, 0x5F6A,
+	0xB344, 0x86C7, 0xB345, 0x86C0, 0xB346, 0x86B6, 0xB347, 0x86C4,	0xB348, 0x86B5, 0xB349, 0x86C6, 0xB34A, 0x86CB, 0xB34B, 0x86B1,
+	0xB34C, 0x86AF, 0xB34D, 0x86C9, 0xB34E, 0x8853, 0xB34F, 0x889E,	0xB350, 0x8888, 0xB351, 0x88AB, 0xB352, 0x8892, 0xB353, 0x8896,
+	0xB354, 0x888D, 0xB355, 0x888B, 0xB356, 0x8993, 0xB357, 0x898F,	0xB358, 0x8A2A, 0xB359, 0x8A1D, 0xB35A, 0x8A23, 0xB35B, 0x8A25,
+	0xB35C, 0x8A31, 0xB35D, 0x8A2D, 0xB35E, 0x8A1F, 0xB35F, 0x8A1B,	0xB360, 0x8A22, 0xB361, 0x8C49, 0xB362, 0x8C5A, 0xB363, 0x8CA9,
+	0xB364, 0x8CAC, 0xB365, 0x8CAB, 0xB366, 0x8CA8, 0xB367, 0x8CAA,	0xB368, 0x8CA7, 0xB369, 0x8D67, 0xB36A, 0x8D66, 0xB36B, 0x8DBE,
+	0xB36C, 0x8DBA, 0xB36D, 0x8EDB, 0xB36E, 0x8EDF, 0xB36F, 0x9019,	0xB370, 0x900D, 0xB371, 0x901A, 0xB372, 0x9017, 0xB373, 0x9023,
+	0xB374, 0x901F, 0xB375, 0x901D, 0xB376, 0x9010, 0xB377, 0x9015,	0xB378, 0x901E, 0xB379, 0x9020, 0xB37A, 0x900F, 0xB37B, 0x9022,
+	0xB37C, 0x9016, 0xB37D, 0x901B, 0xB37E, 0x9014, 0xB3A1, 0x90E8,	0xB3A2, 0x90ED, 0xB3A3, 0x90FD, 0xB3A4, 0x9157, 0xB3A5, 0x91CE,
+	0xB3A6, 0x91F5, 0xB3A7, 0x91E6, 0xB3A8, 0x91E3, 0xB3A9, 0x91E7,	0xB3AA, 0x91ED, 0xB3AB, 0x91E9, 0xB3AC, 0x9589, 0xB3AD, 0x966A,
+	0xB3AE, 0x9675, 0xB3AF, 0x9673, 0xB3B0, 0x9678, 0xB3B1, 0x9670,	0xB3B2, 0x9674, 0xB3B3, 0x9676, 0xB3B4, 0x9677, 0xB3B5, 0x966C,
+	0xB3B6, 0x96C0, 0xB3B7, 0x96EA, 0xB3B8, 0x96E9, 0xB3B9, 0x7AE0,	0xB3BA, 0x7ADF, 0xB3BB, 0x9802, 0xB3BC, 0x9803, 0xB3BD, 0x9B5A,
+	0xB3BE, 0x9CE5, 0xB3BF, 0x9E75, 0xB3C0, 0x9E7F, 0xB3C1, 0x9EA5,	0xB3C2, 0x9EBB, 0xB3C3, 0x50A2, 0xB3C4, 0x508D, 0xB3C5, 0x5085,
+	0xB3C6, 0x5099, 0xB3C7, 0x5091, 0xB3C8, 0x5080, 0xB3C9, 0x5096,	0xB3CA, 0x5098, 0xB3CB, 0x509A, 0xB3CC, 0x6700, 0xB3CD, 0x51F1,
+	0xB3CE, 0x5272, 0xB3CF, 0x5274, 0xB3D0, 0x5275, 0xB3D1, 0x5269,	0xB3D2, 0x52DE, 0xB3D3, 0x52DD, 0xB3D4, 0x52DB, 0xB3D5, 0x535A,
+	0xB3D6, 0x53A5, 0xB3D7, 0x557B, 0xB3D8, 0x5580, 0xB3D9, 0x55A7,	0xB3DA, 0x557C, 0xB3DB, 0x558A, 0xB3DC, 0x559D, 0xB3DD, 0x5598,
+	0xB3DE, 0x5582, 0xB3DF, 0x559C, 0xB3E0, 0x55AA, 0xB3E1, 0x5594,	0xB3E2, 0x5587, 0xB3E3, 0x558B, 0xB3E4, 0x5583, 0xB3E5, 0x55B3,
+	0xB3E6, 0x55AE, 0xB3E7, 0x559F, 0xB3E8, 0x553E, 0xB3E9, 0x55B2,	0xB3EA, 0x559A, 0xB3EB, 0x55BB, 0xB3EC, 0x55AC, 0xB3ED, 0x55B1,
+	0xB3EE, 0x557E, 0xB3EF, 0x5589, 0xB3F0, 0x55AB, 0xB3F1, 0x5599,	0xB3F2, 0x570D, 0xB3F3, 0x582F, 0xB3F4, 0x582A, 0xB3F5, 0x5834,
+	0xB3F6, 0x5824, 0xB3F7, 0x5830, 0xB3F8, 0x5831, 0xB3F9, 0x5821,	0xB3FA, 0x581D, 0xB3FB, 0x5820, 0xB3FC, 0x58F9, 0xB3FD, 0x58FA,
+	0xB3FE, 0x5960, 0xB440, 0x5A77, 0xB441, 0x5A9A, 0xB442, 0x5A7F,	0xB443, 0x5A92, 0xB444, 0x5A9B, 0xB445, 0x5AA7, 0xB446, 0x5B73,
+	0xB447, 0x5B71, 0xB448, 0x5BD2, 0xB449, 0x5BCC, 0xB44A, 0x5BD3,	0xB44B, 0x5BD0, 0xB44C, 0x5C0A, 0xB44D, 0x5C0B, 0xB44E, 0x5C31,
+	0xB44F, 0x5D4C, 0xB450, 0x5D50, 0xB451, 0x5D34, 0xB452, 0x5D47,	0xB453, 0x5DFD, 0xB454, 0x5E45, 0xB455, 0x5E3D, 0xB456, 0x5E40,
+	0xB457, 0x5E43, 0xB458, 0x5E7E, 0xB459, 0x5ECA, 0xB45A, 0x5EC1,	0xB45B, 0x5EC2, 0xB45C, 0x5EC4, 0xB45D, 0x5F3C, 0xB45E, 0x5F6D,
+	0xB45F, 0x5FA9, 0xB460, 0x5FAA, 0xB461, 0x5FA8, 0xB462, 0x60D1,	0xB463, 0x60E1, 0xB464, 0x60B2, 0xB465, 0x60B6, 0xB466, 0x60E0,
+	0xB467, 0x611C, 0xB468, 0x6123, 0xB469, 0x60FA, 0xB46A, 0x6115,	0xB46B, 0x60F0, 0xB46C, 0x60FB, 0xB46D, 0x60F4, 0xB46E, 0x6168,
+	0xB46F, 0x60F1, 0xB470, 0x610E, 0xB471, 0x60F6, 0xB472, 0x6109,	0xB473, 0x6100, 0xB474, 0x6112, 0xB475, 0x621F, 0xB476, 0x6249,
+	0xB477, 0x63A3, 0xB478, 0x638C, 0xB479, 0x63CF, 0xB47A, 0x63C0,	0xB47B, 0x63E9, 0xB47C, 0x63C9, 0xB47D, 0x63C6, 0xB47E, 0x63CD,
+	0xB4A1, 0x63D2, 0xB4A2, 0x63E3, 0xB4A3, 0x63D0, 0xB4A4, 0x63E1,	0xB4A5, 0x63D6, 0xB4A6, 0x63ED, 0xB4A7, 0x63EE, 0xB4A8, 0x6376,
+	0xB4A9, 0x63F4, 0xB4AA, 0x63EA, 0xB4AB, 0x63DB, 0xB4AC, 0x6452,	0xB4AD, 0x63DA, 0xB4AE, 0x63F9, 0xB4AF, 0x655E, 0xB4B0, 0x6566,
+	0xB4B1, 0x6562, 0xB4B2, 0x6563, 0xB4B3, 0x6591, 0xB4B4, 0x6590,	0xB4B5, 0x65AF, 0xB4B6, 0x666E, 0xB4B7, 0x6670, 0xB4B8, 0x6674,
+	0xB4B9, 0x6676, 0xB4BA, 0x666F, 0xB4BB, 0x6691, 0xB4BC, 0x667A,	0xB4BD, 0x667E, 0xB4BE, 0x6677, 0xB4BF, 0x66FE, 0xB4C0, 0x66FF,
+	0xB4C1, 0x671F, 0xB4C2, 0x671D, 0xB4C3, 0x68FA, 0xB4C4, 0x68D5,	0xB4C5, 0x68E0, 0xB4C6, 0x68D8, 0xB4C7, 0x68D7, 0xB4C8, 0x6905,
+	0xB4C9, 0x68DF, 0xB4CA, 0x68F5, 0xB4CB, 0x68EE, 0xB4CC, 0x68E7,	0xB4CD, 0x68F9, 0xB4CE, 0x68D2, 0xB4CF, 0x68F2, 0xB4D0, 0x68E3,
+	0xB4D1, 0x68CB, 0xB4D2, 0x68CD, 0xB4D3, 0x690D, 0xB4D4, 0x6912,	0xB4D5, 0x690E, 0xB4D6, 0x68C9, 0xB4D7, 0x68DA, 0xB4D8, 0x696E,
+	0xB4D9, 0x68FB, 0xB4DA, 0x6B3E, 0xB4DB, 0x6B3A, 0xB4DC, 0x6B3D,	0xB4DD, 0x6B98, 0xB4DE, 0x6B96, 0xB4DF, 0x6BBC, 0xB4E0, 0x6BEF,
+	0xB4E1, 0x6C2E, 0xB4E2, 0x6C2F, 0xB4E3, 0x6C2C, 0xB4E4, 0x6E2F,	0xB4E5, 0x6E38, 0xB4E6, 0x6E54, 0xB4E7, 0x6E21, 0xB4E8, 0x6E32,
+	0xB4E9, 0x6E67, 0xB4EA, 0x6E4A, 0xB4EB, 0x6E20, 0xB4EC, 0x6E25,	0xB4ED, 0x6E23, 0xB4EE, 0x6E1B, 0xB4EF, 0x6E5B, 0xB4F0, 0x6E58,
+	0xB4F1, 0x6E24, 0xB4F2, 0x6E56, 0xB4F3, 0x6E6E, 0xB4F4, 0x6E2D,	0xB4F5, 0x6E26, 0xB4F6, 0x6E6F, 0xB4F7, 0x6E34, 0xB4F8, 0x6E4D,
+	0xB4F9, 0x6E3A, 0xB4FA, 0x6E2C, 0xB4FB, 0x6E43, 0xB4FC, 0x6E1D,	0xB4FD, 0x6E3E, 0xB4FE, 0x6ECB, 0xB540, 0x6E89, 0xB541, 0x6E19,
+	0xB542, 0x6E4E, 0xB543, 0x6E63, 0xB544, 0x6E44, 0xB545, 0x6E72,	0xB546, 0x6E69, 0xB547, 0x6E5F, 0xB548, 0x7119, 0xB549, 0x711A,
+	0xB54A, 0x7126, 0xB54B, 0x7130, 0xB54C, 0x7121, 0xB54D, 0x7136,	0xB54E, 0x716E, 0xB54F, 0x711C, 0xB550, 0x724C, 0xB551, 0x7284,
+	0xB552, 0x7280, 0xB553, 0x7336, 0xB554, 0x7325, 0xB555, 0x7334,	0xB556, 0x7329, 0xB557, 0x743A, 0xB558, 0x742A, 0xB559, 0x7433,
+	0xB55A, 0x7422, 0xB55B, 0x7425, 0xB55C, 0x7435, 0xB55D, 0x7436,	0xB55E, 0x7434, 0xB55F, 0x742F, 0xB560, 0x741B, 0xB561, 0x7426,
+	0xB562, 0x7428, 0xB563, 0x7525, 0xB564, 0x7526, 0xB565, 0x756B,	0xB566, 0x756A, 0xB567, 0x75E2, 0xB568, 0x75DB, 0xB569, 0x75E3,
+	0xB56A, 0x75D9, 0xB56B, 0x75D8, 0xB56C, 0x75DE, 0xB56D, 0x75E0,	0xB56E, 0x767B, 0xB56F, 0x767C, 0xB570, 0x7696, 0xB571, 0x7693,
+	0xB572, 0x76B4, 0xB573, 0x76DC, 0xB574, 0x774F, 0xB575, 0x77ED,	0xB576, 0x785D, 0xB577, 0x786C, 0xB578, 0x786F, 0xB579, 0x7A0D,
+	0xB57A, 0x7A08, 0xB57B, 0x7A0B, 0xB57C, 0x7A05, 0xB57D, 0x7A00,	0xB57E, 0x7A98, 0xB5A1, 0x7A97, 0xB5A2, 0x7A96, 0xB5A3, 0x7AE5,
+	0xB5A4, 0x7AE3, 0xB5A5, 0x7B49, 0xB5A6, 0x7B56, 0xB5A7, 0x7B46,	0xB5A8, 0x7B50, 0xB5A9, 0x7B52, 0xB5AA, 0x7B54, 0xB5AB, 0x7B4D,
+	0xB5AC, 0x7B4B, 0xB5AD, 0x7B4F, 0xB5AE, 0x7B51, 0xB5AF, 0x7C9F,	0xB5B0, 0x7CA5, 0xB5B1, 0x7D5E, 0xB5B2, 0x7D50, 0xB5B3, 0x7D68,
+	0xB5B4, 0x7D55, 0xB5B5, 0x7D2B, 0xB5B6, 0x7D6E, 0xB5B7, 0x7D72,	0xB5B8, 0x7D61, 0xB5B9, 0x7D66, 0xB5BA, 0x7D62, 0xB5BB, 0x7D70,
+	0xB5BC, 0x7D73, 0xB5BD, 0x5584, 0xB5BE, 0x7FD4, 0xB5BF, 0x7FD5,	0xB5C0, 0x800B, 0xB5C1, 0x8052, 0xB5C2, 0x8085, 0xB5C3, 0x8155,
+	0xB5C4, 0x8154, 0xB5C5, 0x814B, 0xB5C6, 0x8151, 0xB5C7, 0x814E,	0xB5C8, 0x8139, 0xB5C9, 0x8146, 0xB5CA, 0x813E, 0xB5CB, 0x814C,
+	0xB5CC, 0x8153, 0xB5CD, 0x8174, 0xB5CE, 0x8212, 0xB5CF, 0x821C,	0xB5D0, 0x83E9, 0xB5D1, 0x8403, 0xB5D2, 0x83F8, 0xB5D3, 0x840D,
+	0xB5D4, 0x83E0, 0xB5D5, 0x83C5, 0xB5D6, 0x840B, 0xB5D7, 0x83C1,	0xB5D8, 0x83EF, 0xB5D9, 0x83F1, 0xB5DA, 0x83F4, 0xB5DB, 0x8457,
+	0xB5DC, 0x840A, 0xB5DD, 0x83F0, 0xB5DE, 0x840C, 0xB5DF, 0x83CC,	0xB5E0, 0x83FD, 0xB5E1, 0x83F2, 0xB5E2, 0x83CA, 0xB5E3, 0x8438,
+	0xB5E4, 0x840E, 0xB5E5, 0x8404, 0xB5E6, 0x83DC, 0xB5E7, 0x8407,	0xB5E8, 0x83D4, 0xB5E9, 0x83DF, 0xB5EA, 0x865B, 0xB5EB, 0x86DF,
+	0xB5EC, 0x86D9, 0xB5ED, 0x86ED, 0xB5EE, 0x86D4, 0xB5EF, 0x86DB,	0xB5F0, 0x86E4, 0xB5F1, 0x86D0, 0xB5F2, 0x86DE, 0xB5F3, 0x8857,
+	0xB5F4, 0x88C1, 0xB5F5, 0x88C2, 0xB5F6, 0x88B1, 0xB5F7, 0x8983,	0xB5F8, 0x8996, 0xB5F9, 0x8A3B, 0xB5FA, 0x8A60, 0xB5FB, 0x8A55,
+	0xB5FC, 0x8A5E, 0xB5FD, 0x8A3C, 0xB5FE, 0x8A41, 0xB640, 0x8A54,	0xB641, 0x8A5B, 0xB642, 0x8A50, 0xB643, 0x8A46, 0xB644, 0x8A34,
+	0xB645, 0x8A3A, 0xB646, 0x8A36, 0xB647, 0x8A56, 0xB648, 0x8C61,	0xB649, 0x8C82, 0xB64A, 0x8CAF, 0xB64B, 0x8CBC, 0xB64C, 0x8CB3,
+	0xB64D, 0x8CBD, 0xB64E, 0x8CC1, 0xB64F, 0x8CBB, 0xB650, 0x8CC0,	0xB651, 0x8CB4, 0xB652, 0x8CB7, 0xB653, 0x8CB6, 0xB654, 0x8CBF,
+	0xB655, 0x8CB8, 0xB656, 0x8D8A, 0xB657, 0x8D85, 0xB658, 0x8D81,	0xB659, 0x8DCE, 0xB65A, 0x8DDD, 0xB65B, 0x8DCB, 0xB65C, 0x8DDA,
+	0xB65D, 0x8DD1, 0xB65E, 0x8DCC, 0xB65F, 0x8DDB, 0xB660, 0x8DC6,	0xB661, 0x8EFB, 0xB662, 0x8EF8, 0xB663, 0x8EFC, 0xB664, 0x8F9C,
+	0xB665, 0x902E, 0xB666, 0x9035, 0xB667, 0x9031, 0xB668, 0x9038,	0xB669, 0x9032, 0xB66A, 0x9036, 0xB66B, 0x9102, 0xB66C, 0x90F5,
+	0xB66D, 0x9109, 0xB66E, 0x90FE, 0xB66F, 0x9163, 0xB670, 0x9165,	0xB671, 0x91CF, 0xB672, 0x9214, 0xB673, 0x9215, 0xB674, 0x9223,
+	0xB675, 0x9209, 0xB676, 0x921E, 0xB677, 0x920D, 0xB678, 0x9210,	0xB679, 0x9207, 0xB67A, 0x9211, 0xB67B, 0x9594, 0xB67C, 0x958F,
+	0xB67D, 0x958B, 0xB67E, 0x9591, 0xB6A1, 0x9593, 0xB6A2, 0x9592,	0xB6A3, 0x958E, 0xB6A4, 0x968A, 0xB6A5, 0x968E, 0xB6A6, 0x968B,
+	0xB6A7, 0x967D, 0xB6A8, 0x9685, 0xB6A9, 0x9686, 0xB6AA, 0x968D,	0xB6AB, 0x9672, 0xB6AC, 0x9684, 0xB6AD, 0x96C1, 0xB6AE, 0x96C5,
+	0xB6AF, 0x96C4, 0xB6B0, 0x96C6, 0xB6B1, 0x96C7, 0xB6B2, 0x96EF,	0xB6B3, 0x96F2, 0xB6B4, 0x97CC, 0xB6B5, 0x9805, 0xB6B6, 0x9806,
+	0xB6B7, 0x9808, 0xB6B8, 0x98E7, 0xB6B9, 0x98EA, 0xB6BA, 0x98EF,	0xB6BB, 0x98E9, 0xB6BC, 0x98F2, 0xB6BD, 0x98ED, 0xB6BE, 0x99AE,
+	0xB6BF, 0x99AD, 0xB6C0, 0x9EC3, 0xB6C1, 0x9ECD, 0xB6C2, 0x9ED1,	0xB6C3, 0x4E82, 0xB6C4, 0x50AD, 0xB6C5, 0x50B5, 0xB6C6, 0x50B2,
+	0xB6C7, 0x50B3, 0xB6C8, 0x50C5, 0xB6C9, 0x50BE, 0xB6CA, 0x50AC,	0xB6CB, 0x50B7, 0xB6CC, 0x50BB, 0xB6CD, 0x50AF, 0xB6CE, 0x50C7,
+	0xB6CF, 0x527F, 0xB6D0, 0x5277, 0xB6D1, 0x527D, 0xB6D2, 0x52DF,	0xB6D3, 0x52E6, 0xB6D4, 0x52E4, 0xB6D5, 0x52E2, 0xB6D6, 0x52E3,
+	0xB6D7, 0x532F, 0xB6D8, 0x55DF, 0xB6D9, 0x55E8, 0xB6DA, 0x55D3,	0xB6DB, 0x55E6, 0xB6DC, 0x55CE, 0xB6DD, 0x55DC, 0xB6DE, 0x55C7,
+	0xB6DF, 0x55D1, 0xB6E0, 0x55E3, 0xB6E1, 0x55E4, 0xB6E2, 0x55EF,	0xB6E3, 0x55DA, 0xB6E4, 0x55E1, 0xB6E5, 0x55C5, 0xB6E6, 0x55C6,
+	0xB6E7, 0x55E5, 0xB6E8, 0x55C9, 0xB6E9, 0x5712, 0xB6EA, 0x5713,	0xB6EB, 0x585E, 0xB6EC, 0x5851, 0xB6ED, 0x5858, 0xB6EE, 0x5857,
+	0xB6EF, 0x585A, 0xB6F0, 0x5854, 0xB6F1, 0x586B, 0xB6F2, 0x584C,	0xB6F3, 0x586D, 0xB6F4, 0x584A, 0xB6F5, 0x5862, 0xB6F6, 0x5852,
+	0xB6F7, 0x584B, 0xB6F8, 0x5967, 0xB6F9, 0x5AC1, 0xB6FA, 0x5AC9,	0xB6FB, 0x5ACC, 0xB6FC, 0x5ABE, 0xB6FD, 0x5ABD, 0xB6FE, 0x5ABC,
+	0xB740, 0x5AB3, 0xB741, 0x5AC2, 0xB742, 0x5AB2, 0xB743, 0x5D69,	0xB744, 0x5D6F, 0xB745, 0x5E4C, 0xB746, 0x5E79, 0xB747, 0x5EC9,
+	0xB748, 0x5EC8, 0xB749, 0x5F12, 0xB74A, 0x5F59, 0xB74B, 0x5FAC,	0xB74C, 0x5FAE, 0xB74D, 0x611A, 0xB74E, 0x610F, 0xB74F, 0x6148,
+	0xB750, 0x611F, 0xB751, 0x60F3, 0xB752, 0x611B, 0xB753, 0x60F9,	0xB754, 0x6101, 0xB755, 0x6108, 0xB756, 0x614E, 0xB757, 0x614C,
+	0xB758, 0x6144, 0xB759, 0x614D, 0xB75A, 0x613E, 0xB75B, 0x6134,	0xB75C, 0x6127, 0xB75D, 0x610D, 0xB75E, 0x6106, 0xB75F, 0x6137,
+	0xB760, 0x6221, 0xB761, 0x6222, 0xB762, 0x6413, 0xB763, 0x643E,	0xB764, 0x641E, 0xB765, 0x642A, 0xB766, 0x642D, 0xB767, 0x643D,
+	0xB768, 0x642C, 0xB769, 0x640F, 0xB76A, 0x641C, 0xB76B, 0x6414,	0xB76C, 0x640D, 0xB76D, 0x6436, 0xB76E, 0x6416, 0xB76F, 0x6417,
+	0xB770, 0x6406, 0xB771, 0x656C, 0xB772, 0x659F, 0xB773, 0x65B0,	0xB774, 0x6697, 0xB775, 0x6689, 0xB776, 0x6687, 0xB777, 0x6688,
+	0xB778, 0x6696, 0xB779, 0x6684, 0xB77A, 0x6698, 0xB77B, 0x668D,	0xB77C, 0x6703, 0xB77D, 0x6994, 0xB77E, 0x696D, 0xB7A1, 0x695A,
+	0xB7A2, 0x6977, 0xB7A3, 0x6960, 0xB7A4, 0x6954, 0xB7A5, 0x6975,	0xB7A6, 0x6930, 0xB7A7, 0x6982, 0xB7A8, 0x694A, 0xB7A9, 0x6968,
+	0xB7AA, 0x696B, 0xB7AB, 0x695E, 0xB7AC, 0x6953, 0xB7AD, 0x6979,	0xB7AE, 0x6986, 0xB7AF, 0x695D, 0xB7B0, 0x6963, 0xB7B1, 0x695B,
+	0xB7B2, 0x6B47, 0xB7B3, 0x6B72, 0xB7B4, 0x6BC0, 0xB7B5, 0x6BBF,	0xB7B6, 0x6BD3, 0xB7B7, 0x6BFD, 0xB7B8, 0x6EA2, 0xB7B9, 0x6EAF,
+	0xB7BA, 0x6ED3, 0xB7BB, 0x6EB6, 0xB7BC, 0x6EC2, 0xB7BD, 0x6E90,	0xB7BE, 0x6E9D, 0xB7BF, 0x6EC7, 0xB7C0, 0x6EC5, 0xB7C1, 0x6EA5,
+	0xB7C2, 0x6E98, 0xB7C3, 0x6EBC, 0xB7C4, 0x6EBA, 0xB7C5, 0x6EAB,	0xB7C6, 0x6ED1, 0xB7C7, 0x6E96, 0xB7C8, 0x6E9C, 0xB7C9, 0x6EC4,
+	0xB7CA, 0x6ED4, 0xB7CB, 0x6EAA, 0xB7CC, 0x6EA7, 0xB7CD, 0x6EB4,	0xB7CE, 0x714E, 0xB7CF, 0x7159, 0xB7D0, 0x7169, 0xB7D1, 0x7164,
+	0xB7D2, 0x7149, 0xB7D3, 0x7167, 0xB7D4, 0x715C, 0xB7D5, 0x716C,	0xB7D6, 0x7166, 0xB7D7, 0x714C, 0xB7D8, 0x7165, 0xB7D9, 0x715E,
+	0xB7DA, 0x7146, 0xB7DB, 0x7168, 0xB7DC, 0x7156, 0xB7DD, 0x723A,	0xB7DE, 0x7252, 0xB7DF, 0x7337, 0xB7E0, 0x7345, 0xB7E1, 0x733F,
+	0xB7E2, 0x733E, 0xB7E3, 0x746F, 0xB7E4, 0x745A, 0xB7E5, 0x7455,	0xB7E6, 0x745F, 0xB7E7, 0x745E, 0xB7E8, 0x7441, 0xB7E9, 0x743F,
+	0xB7EA, 0x7459, 0xB7EB, 0x745B, 0xB7EC, 0x745C, 0xB7ED, 0x7576,	0xB7EE, 0x7578, 0xB7EF, 0x7600, 0xB7F0, 0x75F0, 0xB7F1, 0x7601,
+	0xB7F2, 0x75F2, 0xB7F3, 0x75F1, 0xB7F4, 0x75FA, 0xB7F5, 0x75FF,	0xB7F6, 0x75F4, 0xB7F7, 0x75F3, 0xB7F8, 0x76DE, 0xB7F9, 0x76DF,
+	0xB7FA, 0x775B, 0xB7FB, 0x776B, 0xB7FC, 0x7766, 0xB7FD, 0x775E,	0xB7FE, 0x7763, 0xB840, 0x7779, 0xB841, 0x776A, 0xB842, 0x776C,
+	0xB843, 0x775C, 0xB844, 0x7765, 0xB845, 0x7768, 0xB846, 0x7762,	0xB847, 0x77EE, 0xB848, 0x788E, 0xB849, 0x78B0, 0xB84A, 0x7897,
+	0xB84B, 0x7898, 0xB84C, 0x788C, 0xB84D, 0x7889, 0xB84E, 0x787C,	0xB84F, 0x7891, 0xB850, 0x7893, 0xB851, 0x787F, 0xB852, 0x797A,
+	0xB853, 0x797F, 0xB854, 0x7981, 0xB855, 0x842C, 0xB856, 0x79BD,	0xB857, 0x7A1C, 0xB858, 0x7A1A, 0xB859, 0x7A20, 0xB85A, 0x7A14,
+	0xB85B, 0x7A1F, 0xB85C, 0x7A1E, 0xB85D, 0x7A9F, 0xB85E, 0x7AA0,	0xB85F, 0x7B77, 0xB860, 0x7BC0, 0xB861, 0x7B60, 0xB862, 0x7B6E,
+	0xB863, 0x7B67, 0xB864, 0x7CB1, 0xB865, 0x7CB3, 0xB866, 0x7CB5,	0xB867, 0x7D93, 0xB868, 0x7D79, 0xB869, 0x7D91, 0xB86A, 0x7D81,
+	0xB86B, 0x7D8F, 0xB86C, 0x7D5B, 0xB86D, 0x7F6E, 0xB86E, 0x7F69,	0xB86F, 0x7F6A, 0xB870, 0x7F72, 0xB871, 0x7FA9, 0xB872, 0x7FA8,
+	0xB873, 0x7FA4, 0xB874, 0x8056, 0xB875, 0x8058, 0xB876, 0x8086,	0xB877, 0x8084, 0xB878, 0x8171, 0xB879, 0x8170, 0xB87A, 0x8178,
+	0xB87B, 0x8165, 0xB87C, 0x816E, 0xB87D, 0x8173, 0xB87E, 0x816B,	0xB8A1, 0x8179, 0xB8A2, 0x817A, 0xB8A3, 0x8166, 0xB8A4, 0x8205,
+	0xB8A5, 0x8247, 0xB8A6, 0x8482, 0xB8A7, 0x8477, 0xB8A8, 0x843D,	0xB8A9, 0x8431, 0xB8AA, 0x8475, 0xB8AB, 0x8466, 0xB8AC, 0x846B,
+	0xB8AD, 0x8449, 0xB8AE, 0x846C, 0xB8AF, 0x845B, 0xB8B0, 0x843C,	0xB8B1, 0x8435, 0xB8B2, 0x8461, 0xB8B3, 0x8463, 0xB8B4, 0x8469,
+	0xB8B5, 0x846D, 0xB8B6, 0x8446, 0xB8B7, 0x865E, 0xB8B8, 0x865C,	0xB8B9, 0x865F, 0xB8BA, 0x86F9, 0xB8BB, 0x8713, 0xB8BC, 0x8708,
+	0xB8BD, 0x8707, 0xB8BE, 0x8700, 0xB8BF, 0x86FE, 0xB8C0, 0x86FB,	0xB8C1, 0x8702, 0xB8C2, 0x8703, 0xB8C3, 0x8706, 0xB8C4, 0x870A,
+	0xB8C5, 0x8859, 0xB8C6, 0x88DF, 0xB8C7, 0x88D4, 0xB8C8, 0x88D9,	0xB8C9, 0x88DC, 0xB8CA, 0x88D8, 0xB8CB, 0x88DD, 0xB8CC, 0x88E1,
+	0xB8CD, 0x88CA, 0xB8CE, 0x88D5, 0xB8CF, 0x88D2, 0xB8D0, 0x899C,	0xB8D1, 0x89E3, 0xB8D2, 0x8A6B, 0xB8D3, 0x8A72, 0xB8D4, 0x8A73,
+	0xB8D5, 0x8A66, 0xB8D6, 0x8A69, 0xB8D7, 0x8A70, 0xB8D8, 0x8A87,	0xB8D9, 0x8A7C, 0xB8DA, 0x8A63, 0xB8DB, 0x8AA0, 0xB8DC, 0x8A71,
+	0xB8DD, 0x8A85, 0xB8DE, 0x8A6D, 0xB8DF, 0x8A62, 0xB8E0, 0x8A6E,	0xB8E1, 0x8A6C, 0xB8E2, 0x8A79, 0xB8E3, 0x8A7B, 0xB8E4, 0x8A3E,
+	0xB8E5, 0x8A68, 0xB8E6, 0x8C62, 0xB8E7, 0x8C8A, 0xB8E8, 0x8C89,	0xB8E9, 0x8CCA, 0xB8EA, 0x8CC7, 0xB8EB, 0x8CC8, 0xB8EC, 0x8CC4,
+	0xB8ED, 0x8CB2, 0xB8EE, 0x8CC3, 0xB8EF, 0x8CC2, 0xB8F0, 0x8CC5,	0xB8F1, 0x8DE1, 0xB8F2, 0x8DDF, 0xB8F3, 0x8DE8, 0xB8F4, 0x8DEF,
+	0xB8F5, 0x8DF3, 0xB8F6, 0x8DFA, 0xB8F7, 0x8DEA, 0xB8F8, 0x8DE4,	0xB8F9, 0x8DE6, 0xB8FA, 0x8EB2, 0xB8FB, 0x8F03, 0xB8FC, 0x8F09,
+	0xB8FD, 0x8EFE, 0xB8FE, 0x8F0A, 0xB940, 0x8F9F, 0xB941, 0x8FB2,	0xB942, 0x904B, 0xB943, 0x904A, 0xB944, 0x9053, 0xB945, 0x9042,
+	0xB946, 0x9054, 0xB947, 0x903C, 0xB948, 0x9055, 0xB949, 0x9050,	0xB94A, 0x9047, 0xB94B, 0x904F, 0xB94C, 0x904E, 0xB94D, 0x904D,
+	0xB94E, 0x9051, 0xB94F, 0x903E, 0xB950, 0x9041, 0xB951, 0x9112,	0xB952, 0x9117, 0xB953, 0x916C, 0xB954, 0x916A, 0xB955, 0x9169,
+	0xB956, 0x91C9, 0xB957, 0x9237, 0xB958, 0x9257, 0xB959, 0x9238,	0xB95A, 0x923D, 0xB95B, 0x9240, 0xB95C, 0x923E, 0xB95D, 0x925B,
+	0xB95E, 0x924B, 0xB95F, 0x9264, 0xB960, 0x9251, 0xB961, 0x9234,	0xB962, 0x9249, 0xB963, 0x924D, 0xB964, 0x9245, 0xB965, 0x9239,
+	0xB966, 0x923F, 0xB967, 0x925A, 0xB968, 0x9598, 0xB969, 0x9698,	0xB96A, 0x9694, 0xB96B, 0x9695, 0xB96C, 0x96CD, 0xB96D, 0x96CB,
+	0xB96E, 0x96C9, 0xB96F, 0x96CA, 0xB970, 0x96F7, 0xB971, 0x96FB,	0xB972, 0x96F9, 0xB973, 0x96F6, 0xB974, 0x9756, 0xB975, 0x9774,
+	0xB976, 0x9776, 0xB977, 0x9810, 0xB978, 0x9811, 0xB979, 0x9813,	0xB97A, 0x980A, 0xB97B, 0x9812, 0xB97C, 0x980C, 0xB97D, 0x98FC,
+	0xB97E, 0x98F4, 0xB9A1, 0x98FD, 0xB9A2, 0x98FE, 0xB9A3, 0x99B3,	0xB9A4, 0x99B1, 0xB9A5, 0x99B4, 0xB9A6, 0x9AE1, 0xB9A7, 0x9CE9,
+	0xB9A8, 0x9E82, 0xB9A9, 0x9F0E, 0xB9AA, 0x9F13, 0xB9AB, 0x9F20,	0xB9AC, 0x50E7, 0xB9AD, 0x50EE, 0xB9AE, 0x50E5, 0xB9AF, 0x50D6,
+	0xB9B0, 0x50ED, 0xB9B1, 0x50DA, 0xB9B2, 0x50D5, 0xB9B3, 0x50CF,	0xB9B4, 0x50D1, 0xB9B5, 0x50F1, 0xB9B6, 0x50CE, 0xB9B7, 0x50E9,
+	0xB9B8, 0x5162, 0xB9B9, 0x51F3, 0xB9BA, 0x5283, 0xB9BB, 0x5282,	0xB9BC, 0x5331, 0xB9BD, 0x53AD, 0xB9BE, 0x55FE, 0xB9BF, 0x5600,
+	0xB9C0, 0x561B, 0xB9C1, 0x5617, 0xB9C2, 0x55FD, 0xB9C3, 0x5614,	0xB9C4, 0x5606, 0xB9C5, 0x5609, 0xB9C6, 0x560D, 0xB9C7, 0x560E,
+	0xB9C8, 0x55F7, 0xB9C9, 0x5616, 0xB9CA, 0x561F, 0xB9CB, 0x5608,	0xB9CC, 0x5610, 0xB9CD, 0x55F6, 0xB9CE, 0x5718, 0xB9CF, 0x5716,
+	0xB9D0, 0x5875, 0xB9D1, 0x587E, 0xB9D2, 0x5883, 0xB9D3, 0x5893,	0xB9D4, 0x588A, 0xB9D5, 0x5879, 0xB9D6, 0x5885, 0xB9D7, 0x587D,
+	0xB9D8, 0x58FD, 0xB9D9, 0x5925, 0xB9DA, 0x5922, 0xB9DB, 0x5924,	0xB9DC, 0x596A, 0xB9DD, 0x5969, 0xB9DE, 0x5AE1, 0xB9DF, 0x5AE6,
+	0xB9E0, 0x5AE9, 0xB9E1, 0x5AD7, 0xB9E2, 0x5AD6, 0xB9E3, 0x5AD8,	0xB9E4, 0x5AE3, 0xB9E5, 0x5B75, 0xB9E6, 0x5BDE, 0xB9E7, 0x5BE7,
+	0xB9E8, 0x5BE1, 0xB9E9, 0x5BE5, 0xB9EA, 0x5BE6, 0xB9EB, 0x5BE8,	0xB9EC, 0x5BE2, 0xB9ED, 0x5BE4, 0xB9EE, 0x5BDF, 0xB9EF, 0x5C0D,
+	0xB9F0, 0x5C62, 0xB9F1, 0x5D84, 0xB9F2, 0x5D87, 0xB9F3, 0x5E5B,	0xB9F4, 0x5E63, 0xB9F5, 0x5E55, 0xB9F6, 0x5E57, 0xB9F7, 0x5E54,
+	0xB9F8, 0x5ED3, 0xB9F9, 0x5ED6, 0xB9FA, 0x5F0A, 0xB9FB, 0x5F46,	0xB9FC, 0x5F70, 0xB9FD, 0x5FB9, 0xB9FE, 0x6147, 0xBA40, 0x613F,
+	0xBA41, 0x614B, 0xBA42, 0x6177, 0xBA43, 0x6162, 0xBA44, 0x6163,	0xBA45, 0x615F, 0xBA46, 0x615A, 0xBA47, 0x6158, 0xBA48, 0x6175,
+	0xBA49, 0x622A, 0xBA4A, 0x6487, 0xBA4B, 0x6458, 0xBA4C, 0x6454,	0xBA4D, 0x64A4, 0xBA4E, 0x6478, 0xBA4F, 0x645F, 0xBA50, 0x647A,
+	0xBA51, 0x6451, 0xBA52, 0x6467, 0xBA53, 0x6434, 0xBA54, 0x646D,	0xBA55, 0x647B, 0xBA56, 0x6572, 0xBA57, 0x65A1, 0xBA58, 0x65D7,
+	0xBA59, 0x65D6, 0xBA5A, 0x66A2, 0xBA5B, 0x66A8, 0xBA5C, 0x669D,	0xBA5D, 0x699C, 0xBA5E, 0x69A8, 0xBA5F, 0x6995, 0xBA60, 0x69C1,
+	0xBA61, 0x69AE, 0xBA62, 0x69D3, 0xBA63, 0x69CB, 0xBA64, 0x699B,	0xBA65, 0x69B7, 0xBA66, 0x69BB, 0xBA67, 0x69AB, 0xBA68, 0x69B4,
+	0xBA69, 0x69D0, 0xBA6A, 0x69CD, 0xBA6B, 0x69AD, 0xBA6C, 0x69CC,	0xBA6D, 0x69A6, 0xBA6E, 0x69C3, 0xBA6F, 0x69A3, 0xBA70, 0x6B49,
+	0xBA71, 0x6B4C, 0xBA72, 0x6C33, 0xBA73, 0x6F33, 0xBA74, 0x6F14,	0xBA75, 0x6EFE, 0xBA76, 0x6F13, 0xBA77, 0x6EF4, 0xBA78, 0x6F29,
+	0xBA79, 0x6F3E, 0xBA7A, 0x6F20, 0xBA7B, 0x6F2C, 0xBA7C, 0x6F0F,	0xBA7D, 0x6F02, 0xBA7E, 0x6F22, 0xBAA1, 0x6EFF, 0xBAA2, 0x6EEF,
+	0xBAA3, 0x6F06, 0xBAA4, 0x6F31, 0xBAA5, 0x6F38, 0xBAA6, 0x6F32,	0xBAA7, 0x6F23, 0xBAA8, 0x6F15, 0xBAA9, 0x6F2B, 0xBAAA, 0x6F2F,
+	0xBAAB, 0x6F88, 0xBAAC, 0x6F2A, 0xBAAD, 0x6EEC, 0xBAAE, 0x6F01,	0xBAAF, 0x6EF2, 0xBAB0, 0x6ECC, 0xBAB1, 0x6EF7, 0xBAB2, 0x7194,
+	0xBAB3, 0x7199, 0xBAB4, 0x717D, 0xBAB5, 0x718A, 0xBAB6, 0x7184,	0xBAB7, 0x7192, 0xBAB8, 0x723E, 0xBAB9, 0x7292, 0xBABA, 0x7296,
+	0xBABB, 0x7344, 0xBABC, 0x7350, 0xBABD, 0x7464, 0xBABE, 0x7463,	0xBABF, 0x746A, 0xBAC0, 0x7470, 0xBAC1, 0x746D, 0xBAC2, 0x7504,
+	0xBAC3, 0x7591, 0xBAC4, 0x7627, 0xBAC5, 0x760D, 0xBAC6, 0x760B,	0xBAC7, 0x7609, 0xBAC8, 0x7613, 0xBAC9, 0x76E1, 0xBACA, 0x76E3,
+	0xBACB, 0x7784, 0xBACC, 0x777D, 0xBACD, 0x777F, 0xBACE, 0x7761,	0xBACF, 0x78C1, 0xBAD0, 0x789F, 0xBAD1, 0x78A7, 0xBAD2, 0x78B3,
+	0xBAD3, 0x78A9, 0xBAD4, 0x78A3, 0xBAD5, 0x798E, 0xBAD6, 0x798F,	0xBAD7, 0x798D, 0xBAD8, 0x7A2E, 0xBAD9, 0x7A31, 0xBADA, 0x7AAA,
+	0xBADB, 0x7AA9, 0xBADC, 0x7AED, 0xBADD, 0x7AEF, 0xBADE, 0x7BA1,	0xBADF, 0x7B95, 0xBAE0, 0x7B8B, 0xBAE1, 0x7B75, 0xBAE2, 0x7B97,
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+	0xBAEB, 0x7CBE, 0xBAEC, 0x7DBB, 0xBAED, 0x7DB0, 0xBAEE, 0x7D9C,	0xBAEF, 0x7DBD, 0xBAF0, 0x7DBE, 0xBAF1, 0x7DA0, 0xBAF2, 0x7DCA,
+	0xBAF3, 0x7DB4, 0xBAF4, 0x7DB2, 0xBAF5, 0x7DB1, 0xBAF6, 0x7DBA,	0xBAF7, 0x7DA2, 0xBAF8, 0x7DBF, 0xBAF9, 0x7DB5, 0xBAFA, 0x7DB8,
+	0xBAFB, 0x7DAD, 0xBAFC, 0x7DD2, 0xBAFD, 0x7DC7, 0xBAFE, 0x7DAC,	0xBB40, 0x7F70, 0xBB41, 0x7FE0, 0xBB42, 0x7FE1, 0xBB43, 0x7FDF,
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+	0xBB4C, 0x817F, 0xBB4D, 0x8182, 0xBB4E, 0x81E7, 0xBB4F, 0x81FA,	0xBB50, 0x8207, 0xBB51, 0x8214, 0xBB52, 0x821E, 0xBB53, 0x824B,
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+	0xBB7C, 0x8AA1, 0xBB7D, 0x8A93, 0xBB7E, 0x8AA4, 0xBBA1, 0x8AAA,	0xBBA2, 0x8AA5, 0xBBA3, 0x8AA8, 0xBBA4, 0x8A98, 0xBBA5, 0x8A91,
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+	0xBBAE, 0x8D6B, 0xBBAF, 0x8D99, 0xBBB0, 0x8D95, 0xBBB1, 0x8DFC,	0xBBB2, 0x8F14, 0xBBB3, 0x8F12, 0xBBB4, 0x8F15, 0xBBB5, 0x8F13,
+	0xBBB6, 0x8FA3, 0xBBB7, 0x9060, 0xBBB8, 0x9058, 0xBBB9, 0x905C,	0xBBBA, 0x9063, 0xBBBB, 0x9059, 0xBBBC, 0x905E, 0xBBBD, 0x9062,
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+	0xBBC6, 0x9174, 0xBBC7, 0x9278, 0xBBC8, 0x9280, 0xBBC9, 0x9285,	0xBBCA, 0x9298, 0xBBCB, 0x9296, 0xBBCC, 0x927B, 0xBBCD, 0x9293,
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+	0xBBD6, 0x95A5, 0xBBD7, 0x95A4, 0xBBD8, 0x9699, 0xBBD9, 0x969C,	0xBBDA, 0x969B, 0xBBDB, 0x96CC, 0xBBDC, 0x96D2, 0xBBDD, 0x9700,
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+	0xBBEE, 0x9B42, 0xBBEF, 0x9CF4, 0xBBF0, 0x9CF6, 0xBBF1, 0x9CF3,	0xBBF2, 0x9EBC, 0xBBF3, 0x9F3B, 0xBBF4, 0x9F4A, 0xBBF5, 0x5104,
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+	0xBCA9, 0x61AC, 0xBCAA, 0x619A, 0xBCAB, 0x61A4, 0xBCAC, 0x6194,	0xBCAD, 0x61AE, 0xBCAE, 0x622E, 0xBCAF, 0x6469, 0xBCB0, 0x646F,
+	0xBCB1, 0x6479, 0xBCB2, 0x649E, 0xBCB3, 0x64B2, 0xBCB4, 0x6488,	0xBCB5, 0x6490, 0xBCB6, 0x64B0, 0xBCB7, 0x64A5, 0xBCB8, 0x6493,
+	0xBCB9, 0x6495, 0xBCBA, 0x64A9, 0xBCBB, 0x6492, 0xBCBC, 0x64AE,	0xBCBD, 0x64AD, 0xBCBE, 0x64AB, 0xBCBF, 0x649A, 0xBCC0, 0x64AC,
+	0xBCC1, 0x6499, 0xBCC2, 0x64A2, 0xBCC3, 0x64B3, 0xBCC4, 0x6575,	0xBCC5, 0x6577, 0xBCC6, 0x6578, 0xBCC7, 0x66AE, 0xBCC8, 0x66AB,
+	0xBCC9, 0x66B4, 0xBCCA, 0x66B1, 0xBCCB, 0x6A23, 0xBCCC, 0x6A1F,	0xBCCD, 0x69E8, 0xBCCE, 0x6A01, 0xBCCF, 0x6A1E, 0xBCD0, 0x6A19,
+	0xBCD1, 0x69FD, 0xBCD2, 0x6A21, 0xBCD3, 0x6A13, 0xBCD4, 0x6A0A,	0xBCD5, 0x69F3, 0xBCD6, 0x6A02, 0xBCD7, 0x6A05, 0xBCD8, 0x69ED,
+	0xBCD9, 0x6A11, 0xBCDA, 0x6B50, 0xBCDB, 0x6B4E, 0xBCDC, 0x6BA4,	0xBCDD, 0x6BC5, 0xBCDE, 0x6BC6, 0xBCDF, 0x6F3F, 0xBCE0, 0x6F7C,
+	0xBCE1, 0x6F84, 0xBCE2, 0x6F51, 0xBCE3, 0x6F66, 0xBCE4, 0x6F54,	0xBCE5, 0x6F86, 0xBCE6, 0x6F6D, 0xBCE7, 0x6F5B, 0xBCE8, 0x6F78,
+	0xBCE9, 0x6F6E, 0xBCEA, 0x6F8E, 0xBCEB, 0x6F7A, 0xBCEC, 0x6F70,	0xBCED, 0x6F64, 0xBCEE, 0x6F97, 0xBCEF, 0x6F58, 0xBCF0, 0x6ED5,
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+	0xBCF9, 0x729B, 0xBCFA, 0x734E, 0xBCFB, 0x7357, 0xBCFC, 0x7469,	0xBCFD, 0x748B, 0xBCFE, 0x7483, 0xBD40, 0x747E, 0xBD41, 0x7480,
+	0xBD42, 0x757F, 0xBD43, 0x7620, 0xBD44, 0x7629, 0xBD45, 0x761F,	0xBD46, 0x7624, 0xBD47, 0x7626, 0xBD48, 0x7621, 0xBD49, 0x7622,
+	0xBD4A, 0x769A, 0xBD4B, 0x76BA, 0xBD4C, 0x76E4, 0xBD4D, 0x778E,	0xBD4E, 0x7787, 0xBD4F, 0x778C, 0xBD50, 0x7791, 0xBD51, 0x778B,
+	0xBD52, 0x78CB, 0xBD53, 0x78C5, 0xBD54, 0x78BA, 0xBD55, 0x78CA,	0xBD56, 0x78BE, 0xBD57, 0x78D5, 0xBD58, 0x78BC, 0xBD59, 0x78D0,
+	0xBD5A, 0x7A3F, 0xBD5B, 0x7A3C, 0xBD5C, 0x7A40, 0xBD5D, 0x7A3D,	0xBD5E, 0x7A37, 0xBD5F, 0x7A3B, 0xBD60, 0x7AAF, 0xBD61, 0x7AAE,
+	0xBD62, 0x7BAD, 0xBD63, 0x7BB1, 0xBD64, 0x7BC4, 0xBD65, 0x7BB4,	0xBD66, 0x7BC6, 0xBD67, 0x7BC7, 0xBD68, 0x7BC1, 0xBD69, 0x7BA0,
+	0xBD6A, 0x7BCC, 0xBD6B, 0x7CCA, 0xBD6C, 0x7DE0, 0xBD6D, 0x7DF4,	0xBD6E, 0x7DEF, 0xBD6F, 0x7DFB, 0xBD70, 0x7DD8, 0xBD71, 0x7DEC,
+	0xBD72, 0x7DDD, 0xBD73, 0x7DE8, 0xBD74, 0x7DE3, 0xBD75, 0x7DDA,	0xBD76, 0x7DDE, 0xBD77, 0x7DE9, 0xBD78, 0x7D9E, 0xBD79, 0x7DD9,
+	0xBD7A, 0x7DF2, 0xBD7B, 0x7DF9, 0xBD7C, 0x7F75, 0xBD7D, 0x7F77,	0xBD7E, 0x7FAF, 0xBDA1, 0x7FE9, 0xBDA2, 0x8026, 0xBDA3, 0x819B,
+	0xBDA4, 0x819C, 0xBDA5, 0x819D, 0xBDA6, 0x81A0, 0xBDA7, 0x819A,	0xBDA8, 0x8198, 0xBDA9, 0x8517, 0xBDAA, 0x853D, 0xBDAB, 0x851A,
+	0xBDAC, 0x84EE, 0xBDAD, 0x852C, 0xBDAE, 0x852D, 0xBDAF, 0x8513,	0xBDB0, 0x8511, 0xBDB1, 0x8523, 0xBDB2, 0x8521, 0xBDB3, 0x8514,
+	0xBDB4, 0x84EC, 0xBDB5, 0x8525, 0xBDB6, 0x84FF, 0xBDB7, 0x8506,	0xBDB8, 0x8782, 0xBDB9, 0x8774, 0xBDBA, 0x8776, 0xBDBB, 0x8760,
+	0xBDBC, 0x8766, 0xBDBD, 0x8778, 0xBDBE, 0x8768, 0xBDBF, 0x8759,	0xBDC0, 0x8757, 0xBDC1, 0x874C, 0xBDC2, 0x8753, 0xBDC3, 0x885B,
+	0xBDC4, 0x885D, 0xBDC5, 0x8910, 0xBDC6, 0x8907, 0xBDC7, 0x8912,	0xBDC8, 0x8913, 0xBDC9, 0x8915, 0xBDCA, 0x890A, 0xBDCB, 0x8ABC,
+	0xBDCC, 0x8AD2, 0xBDCD, 0x8AC7, 0xBDCE, 0x8AC4, 0xBDCF, 0x8A95,	0xBDD0, 0x8ACB, 0xBDD1, 0x8AF8, 0xBDD2, 0x8AB2, 0xBDD3, 0x8AC9,
+	0xBDD4, 0x8AC2, 0xBDD5, 0x8ABF, 0xBDD6, 0x8AB0, 0xBDD7, 0x8AD6,	0xBDD8, 0x8ACD, 0xBDD9, 0x8AB6, 0xBDDA, 0x8AB9, 0xBDDB, 0x8ADB,
+	0xBDDC, 0x8C4C, 0xBDDD, 0x8C4E, 0xBDDE, 0x8C6C, 0xBDDF, 0x8CE0,	0xBDE0, 0x8CDE, 0xBDE1, 0x8CE6, 0xBDE2, 0x8CE4, 0xBDE3, 0x8CEC,
+	0xBDE4, 0x8CED, 0xBDE5, 0x8CE2, 0xBDE6, 0x8CE3, 0xBDE7, 0x8CDC,	0xBDE8, 0x8CEA, 0xBDE9, 0x8CE1, 0xBDEA, 0x8D6D, 0xBDEB, 0x8D9F,
+	0xBDEC, 0x8DA3, 0xBDED, 0x8E2B, 0xBDEE, 0x8E10, 0xBDEF, 0x8E1D,	0xBDF0, 0x8E22, 0xBDF1, 0x8E0F, 0xBDF2, 0x8E29, 0xBDF3, 0x8E1F,
+	0xBDF4, 0x8E21, 0xBDF5, 0x8E1E, 0xBDF6, 0x8EBA, 0xBDF7, 0x8F1D,	0xBDF8, 0x8F1B, 0xBDF9, 0x8F1F, 0xBDFA, 0x8F29, 0xBDFB, 0x8F26,
+	0xBDFC, 0x8F2A, 0xBDFD, 0x8F1C, 0xBDFE, 0x8F1E, 0xBE40, 0x8F25,	0xBE41, 0x9069, 0xBE42, 0x906E, 0xBE43, 0x9068, 0xBE44, 0x906D,
+	0xBE45, 0x9077, 0xBE46, 0x9130, 0xBE47, 0x912D, 0xBE48, 0x9127,	0xBE49, 0x9131, 0xBE4A, 0x9187, 0xBE4B, 0x9189, 0xBE4C, 0x918B,
+	0xBE4D, 0x9183, 0xBE4E, 0x92C5, 0xBE4F, 0x92BB, 0xBE50, 0x92B7,	0xBE51, 0x92EA, 0xBE52, 0x92AC, 0xBE53, 0x92E4, 0xBE54, 0x92C1,
+	0xBE55, 0x92B3, 0xBE56, 0x92BC, 0xBE57, 0x92D2, 0xBE58, 0x92C7,	0xBE59, 0x92F0, 0xBE5A, 0x92B2, 0xBE5B, 0x95AD, 0xBE5C, 0x95B1,
+	0xBE5D, 0x9704, 0xBE5E, 0x9706, 0xBE5F, 0x9707, 0xBE60, 0x9709,	0xBE61, 0x9760, 0xBE62, 0x978D, 0xBE63, 0x978B, 0xBE64, 0x978F,
+	0xBE65, 0x9821, 0xBE66, 0x982B, 0xBE67, 0x981C, 0xBE68, 0x98B3,	0xBE69, 0x990A, 0xBE6A, 0x9913, 0xBE6B, 0x9912, 0xBE6C, 0x9918,
+	0xBE6D, 0x99DD, 0xBE6E, 0x99D0, 0xBE6F, 0x99DF, 0xBE70, 0x99DB,	0xBE71, 0x99D1, 0xBE72, 0x99D5, 0xBE73, 0x99D2, 0xBE74, 0x99D9,
+	0xBE75, 0x9AB7, 0xBE76, 0x9AEE, 0xBE77, 0x9AEF, 0xBE78, 0x9B27,	0xBE79, 0x9B45, 0xBE7A, 0x9B44, 0xBE7B, 0x9B77, 0xBE7C, 0x9B6F,
+	0xBE7D, 0x9D06, 0xBE7E, 0x9D09, 0xBEA1, 0x9D03, 0xBEA2, 0x9EA9,	0xBEA3, 0x9EBE, 0xBEA4, 0x9ECE, 0xBEA5, 0x58A8, 0xBEA6, 0x9F52,
+	0xBEA7, 0x5112, 0xBEA8, 0x5118, 0xBEA9, 0x5114, 0xBEAA, 0x5110,	0xBEAB, 0x5115, 0xBEAC, 0x5180, 0xBEAD, 0x51AA, 0xBEAE, 0x51DD,
+	0xBEAF, 0x5291, 0xBEB0, 0x5293, 0xBEB1, 0x52F3, 0xBEB2, 0x5659,	0xBEB3, 0x566B, 0xBEB4, 0x5679, 0xBEB5, 0x5669, 0xBEB6, 0x5664,
+	0xBEB7, 0x5678, 0xBEB8, 0x566A, 0xBEB9, 0x5668, 0xBEBA, 0x5665,	0xBEBB, 0x5671, 0xBEBC, 0x566F, 0xBEBD, 0x566C, 0xBEBE, 0x5662,
+	0xBEBF, 0x5676, 0xBEC0, 0x58C1, 0xBEC1, 0x58BE, 0xBEC2, 0x58C7,	0xBEC3, 0x58C5, 0xBEC4, 0x596E, 0xBEC5, 0x5B1D, 0xBEC6, 0x5B34,
+	0xBEC7, 0x5B78, 0xBEC8, 0x5BF0, 0xBEC9, 0x5C0E, 0xBECA, 0x5F4A,	0xBECB, 0x61B2, 0xBECC, 0x6191, 0xBECD, 0x61A9, 0xBECE, 0x618A,
+	0xBECF, 0x61CD, 0xBED0, 0x61B6, 0xBED1, 0x61BE, 0xBED2, 0x61CA,	0xBED3, 0x61C8, 0xBED4, 0x6230, 0xBED5, 0x64C5, 0xBED6, 0x64C1,
+	0xBED7, 0x64CB, 0xBED8, 0x64BB, 0xBED9, 0x64BC, 0xBEDA, 0x64DA,	0xBEDB, 0x64C4, 0xBEDC, 0x64C7, 0xBEDD, 0x64C2, 0xBEDE, 0x64CD,
+	0xBEDF, 0x64BF, 0xBEE0, 0x64D2, 0xBEE1, 0x64D4, 0xBEE2, 0x64BE,	0xBEE3, 0x6574, 0xBEE4, 0x66C6, 0xBEE5, 0x66C9, 0xBEE6, 0x66B9,
+	0xBEE7, 0x66C4, 0xBEE8, 0x66C7, 0xBEE9, 0x66B8, 0xBEEA, 0x6A3D,	0xBEEB, 0x6A38, 0xBEEC, 0x6A3A, 0xBEED, 0x6A59, 0xBEEE, 0x6A6B,
+	0xBEEF, 0x6A58, 0xBEF0, 0x6A39, 0xBEF1, 0x6A44, 0xBEF2, 0x6A62,	0xBEF3, 0x6A61, 0xBEF4, 0x6A4B, 0xBEF5, 0x6A47, 0xBEF6, 0x6A35,
+	0xBEF7, 0x6A5F, 0xBEF8, 0x6A48, 0xBEF9, 0x6B59, 0xBEFA, 0x6B77,	0xBEFB, 0x6C05, 0xBEFC, 0x6FC2, 0xBEFD, 0x6FB1, 0xBEFE, 0x6FA1,
+	0xBF40, 0x6FC3, 0xBF41, 0x6FA4, 0xBF42, 0x6FC1, 0xBF43, 0x6FA7,	0xBF44, 0x6FB3, 0xBF45, 0x6FC0, 0xBF46, 0x6FB9, 0xBF47, 0x6FB6,
+	0xBF48, 0x6FA6, 0xBF49, 0x6FA0, 0xBF4A, 0x6FB4, 0xBF4B, 0x71BE,	0xBF4C, 0x71C9, 0xBF4D, 0x71D0, 0xBF4E, 0x71D2, 0xBF4F, 0x71C8,
+	0xBF50, 0x71D5, 0xBF51, 0x71B9, 0xBF52, 0x71CE, 0xBF53, 0x71D9,	0xBF54, 0x71DC, 0xBF55, 0x71C3, 0xBF56, 0x71C4, 0xBF57, 0x7368,
+	0xBF58, 0x749C, 0xBF59, 0x74A3, 0xBF5A, 0x7498, 0xBF5B, 0x749F,	0xBF5C, 0x749E, 0xBF5D, 0x74E2, 0xBF5E, 0x750C, 0xBF5F, 0x750D,
+	0xBF60, 0x7634, 0xBF61, 0x7638, 0xBF62, 0x763A, 0xBF63, 0x76E7,	0xBF64, 0x76E5, 0xBF65, 0x77A0, 0xBF66, 0x779E, 0xBF67, 0x779F,
+	0xBF68, 0x77A5, 0xBF69, 0x78E8, 0xBF6A, 0x78DA, 0xBF6B, 0x78EC,	0xBF6C, 0x78E7, 0xBF6D, 0x79A6, 0xBF6E, 0x7A4D, 0xBF6F, 0x7A4E,
+	0xBF70, 0x7A46, 0xBF71, 0x7A4C, 0xBF72, 0x7A4B, 0xBF73, 0x7ABA,	0xBF74, 0x7BD9, 0xBF75, 0x7C11, 0xBF76, 0x7BC9, 0xBF77, 0x7BE4,
+	0xBF78, 0x7BDB, 0xBF79, 0x7BE1, 0xBF7A, 0x7BE9, 0xBF7B, 0x7BE6,	0xBF7C, 0x7CD5, 0xBF7D, 0x7CD6, 0xBF7E, 0x7E0A, 0xBFA1, 0x7E11,
+	0xBFA2, 0x7E08, 0xBFA3, 0x7E1B, 0xBFA4, 0x7E23, 0xBFA5, 0x7E1E,	0xBFA6, 0x7E1D, 0xBFA7, 0x7E09, 0xBFA8, 0x7E10, 0xBFA9, 0x7F79,
+	0xBFAA, 0x7FB2, 0xBFAB, 0x7FF0, 0xBFAC, 0x7FF1, 0xBFAD, 0x7FEE,	0xBFAE, 0x8028, 0xBFAF, 0x81B3, 0xBFB0, 0x81A9, 0xBFB1, 0x81A8,
+	0xBFB2, 0x81FB, 0xBFB3, 0x8208, 0xBFB4, 0x8258, 0xBFB5, 0x8259,	0xBFB6, 0x854A, 0xBFB7, 0x8559, 0xBFB8, 0x8548, 0xBFB9, 0x8568,
+	0xBFBA, 0x8569, 0xBFBB, 0x8543, 0xBFBC, 0x8549, 0xBFBD, 0x856D,	0xBFBE, 0x856A, 0xBFBF, 0x855E, 0xBFC0, 0x8783, 0xBFC1, 0x879F,
+	0xBFC2, 0x879E, 0xBFC3, 0x87A2, 0xBFC4, 0x878D, 0xBFC5, 0x8861,	0xBFC6, 0x892A, 0xBFC7, 0x8932, 0xBFC8, 0x8925, 0xBFC9, 0x892B,
+	0xBFCA, 0x8921, 0xBFCB, 0x89AA, 0xBFCC, 0x89A6, 0xBFCD, 0x8AE6,	0xBFCE, 0x8AFA, 0xBFCF, 0x8AEB, 0xBFD0, 0x8AF1, 0xBFD1, 0x8B00,
+	0xBFD2, 0x8ADC, 0xBFD3, 0x8AE7, 0xBFD4, 0x8AEE, 0xBFD5, 0x8AFE,	0xBFD6, 0x8B01, 0xBFD7, 0x8B02, 0xBFD8, 0x8AF7, 0xBFD9, 0x8AED,
+	0xBFDA, 0x8AF3, 0xBFDB, 0x8AF6, 0xBFDC, 0x8AFC, 0xBFDD, 0x8C6B,	0xBFDE, 0x8C6D, 0xBFDF, 0x8C93, 0xBFE0, 0x8CF4, 0xBFE1, 0x8E44,
+	0xBFE2, 0x8E31, 0xBFE3, 0x8E34, 0xBFE4, 0x8E42, 0xBFE5, 0x8E39,	0xBFE6, 0x8E35, 0xBFE7, 0x8F3B, 0xBFE8, 0x8F2F, 0xBFE9, 0x8F38,
+	0xBFEA, 0x8F33, 0xBFEB, 0x8FA8, 0xBFEC, 0x8FA6, 0xBFED, 0x9075,	0xBFEE, 0x9074, 0xBFEF, 0x9078, 0xBFF0, 0x9072, 0xBFF1, 0x907C,
+	0xBFF2, 0x907A, 0xBFF3, 0x9134, 0xBFF4, 0x9192, 0xBFF5, 0x9320,	0xBFF6, 0x9336, 0xBFF7, 0x92F8, 0xBFF8, 0x9333, 0xBFF9, 0x932F,
+	0xBFFA, 0x9322, 0xBFFB, 0x92FC, 0xBFFC, 0x932B, 0xBFFD, 0x9304,	0xBFFE, 0x931A, 0xC040, 0x9310, 0xC041, 0x9326, 0xC042, 0x9321,
+	0xC043, 0x9315, 0xC044, 0x932E, 0xC045, 0x9319, 0xC046, 0x95BB,	0xC047, 0x96A7, 0xC048, 0x96A8, 0xC049, 0x96AA, 0xC04A, 0x96D5,
+	0xC04B, 0x970E, 0xC04C, 0x9711, 0xC04D, 0x9716, 0xC04E, 0x970D,	0xC04F, 0x9713, 0xC050, 0x970F, 0xC051, 0x975B, 0xC052, 0x975C,
+	0xC053, 0x9766, 0xC054, 0x9798, 0xC055, 0x9830, 0xC056, 0x9838,	0xC057, 0x983B, 0xC058, 0x9837, 0xC059, 0x982D, 0xC05A, 0x9839,
+	0xC05B, 0x9824, 0xC05C, 0x9910, 0xC05D, 0x9928, 0xC05E, 0x991E,	0xC05F, 0x991B, 0xC060, 0x9921, 0xC061, 0x991A, 0xC062, 0x99ED,
+	0xC063, 0x99E2, 0xC064, 0x99F1, 0xC065, 0x9AB8, 0xC066, 0x9ABC,	0xC067, 0x9AFB, 0xC068, 0x9AED, 0xC069, 0x9B28, 0xC06A, 0x9B91,
+	0xC06B, 0x9D15, 0xC06C, 0x9D23, 0xC06D, 0x9D26, 0xC06E, 0x9D28,	0xC06F, 0x9D12, 0xC070, 0x9D1B, 0xC071, 0x9ED8, 0xC072, 0x9ED4,
+	0xC073, 0x9F8D, 0xC074, 0x9F9C, 0xC075, 0x512A, 0xC076, 0x511F,	0xC077, 0x5121, 0xC078, 0x5132, 0xC079, 0x52F5, 0xC07A, 0x568E,
+	0xC07B, 0x5680, 0xC07C, 0x5690, 0xC07D, 0x5685, 0xC07E, 0x5687,	0xC0A1, 0x568F, 0xC0A2, 0x58D5, 0xC0A3, 0x58D3, 0xC0A4, 0x58D1,
+	0xC0A5, 0x58CE, 0xC0A6, 0x5B30, 0xC0A7, 0x5B2A, 0xC0A8, 0x5B24,	0xC0A9, 0x5B7A, 0xC0AA, 0x5C37, 0xC0AB, 0x5C68, 0xC0AC, 0x5DBC,
+	0xC0AD, 0x5DBA, 0xC0AE, 0x5DBD, 0xC0AF, 0x5DB8, 0xC0B0, 0x5E6B,	0xC0B1, 0x5F4C, 0xC0B2, 0x5FBD, 0xC0B3, 0x61C9, 0xC0B4, 0x61C2,
+	0xC0B5, 0x61C7, 0xC0B6, 0x61E6, 0xC0B7, 0x61CB, 0xC0B8, 0x6232,	0xC0B9, 0x6234, 0xC0BA, 0x64CE, 0xC0BB, 0x64CA, 0xC0BC, 0x64D8,
+	0xC0BD, 0x64E0, 0xC0BE, 0x64F0, 0xC0BF, 0x64E6, 0xC0C0, 0x64EC,	0xC0C1, 0x64F1, 0xC0C2, 0x64E2, 0xC0C3, 0x64ED, 0xC0C4, 0x6582,
+	0xC0C5, 0x6583, 0xC0C6, 0x66D9, 0xC0C7, 0x66D6, 0xC0C8, 0x6A80,	0xC0C9, 0x6A94, 0xC0CA, 0x6A84, 0xC0CB, 0x6AA2, 0xC0CC, 0x6A9C,
+	0xC0CD, 0x6ADB, 0xC0CE, 0x6AA3, 0xC0CF, 0x6A7E, 0xC0D0, 0x6A97,	0xC0D1, 0x6A90, 0xC0D2, 0x6AA0, 0xC0D3, 0x6B5C, 0xC0D4, 0x6BAE,
+	0xC0D5, 0x6BDA, 0xC0D6, 0x6C08, 0xC0D7, 0x6FD8, 0xC0D8, 0x6FF1,	0xC0D9, 0x6FDF, 0xC0DA, 0x6FE0, 0xC0DB, 0x6FDB, 0xC0DC, 0x6FE4,
+	0xC0DD, 0x6FEB, 0xC0DE, 0x6FEF, 0xC0DF, 0x6F80, 0xC0E0, 0x6FEC,	0xC0E1, 0x6FE1, 0xC0E2, 0x6FE9, 0xC0E3, 0x6FD5, 0xC0E4, 0x6FEE,
+	0xC0E5, 0x6FF0, 0xC0E6, 0x71E7, 0xC0E7, 0x71DF, 0xC0E8, 0x71EE,	0xC0E9, 0x71E6, 0xC0EA, 0x71E5, 0xC0EB, 0x71ED, 0xC0EC, 0x71EC,
+	0xC0ED, 0x71F4, 0xC0EE, 0x71E0, 0xC0EF, 0x7235, 0xC0F0, 0x7246,	0xC0F1, 0x7370, 0xC0F2, 0x7372, 0xC0F3, 0x74A9, 0xC0F4, 0x74B0,
+	0xC0F5, 0x74A6, 0xC0F6, 0x74A8, 0xC0F7, 0x7646, 0xC0F8, 0x7642,	0xC0F9, 0x764C, 0xC0FA, 0x76EA, 0xC0FB, 0x77B3, 0xC0FC, 0x77AA,
+	0xC0FD, 0x77B0, 0xC0FE, 0x77AC, 0xC140, 0x77A7, 0xC141, 0x77AD,	0xC142, 0x77EF, 0xC143, 0x78F7, 0xC144, 0x78FA, 0xC145, 0x78F4,
+	0xC146, 0x78EF, 0xC147, 0x7901, 0xC148, 0x79A7, 0xC149, 0x79AA,	0xC14A, 0x7A57, 0xC14B, 0x7ABF, 0xC14C, 0x7C07, 0xC14D, 0x7C0D,
+	0xC14E, 0x7BFE, 0xC14F, 0x7BF7, 0xC150, 0x7C0C, 0xC151, 0x7BE0,	0xC152, 0x7CE0, 0xC153, 0x7CDC, 0xC154, 0x7CDE, 0xC155, 0x7CE2,
+	0xC156, 0x7CDF, 0xC157, 0x7CD9, 0xC158, 0x7CDD, 0xC159, 0x7E2E,	0xC15A, 0x7E3E, 0xC15B, 0x7E46, 0xC15C, 0x7E37, 0xC15D, 0x7E32,
+	0xC15E, 0x7E43, 0xC15F, 0x7E2B, 0xC160, 0x7E3D, 0xC161, 0x7E31,	0xC162, 0x7E45, 0xC163, 0x7E41, 0xC164, 0x7E34, 0xC165, 0x7E39,
+	0xC166, 0x7E48, 0xC167, 0x7E35, 0xC168, 0x7E3F, 0xC169, 0x7E2F,	0xC16A, 0x7F44, 0xC16B, 0x7FF3, 0xC16C, 0x7FFC, 0xC16D, 0x8071,
+	0xC16E, 0x8072, 0xC16F, 0x8070, 0xC170, 0x806F, 0xC171, 0x8073,	0xC172, 0x81C6, 0xC173, 0x81C3, 0xC174, 0x81BA, 0xC175, 0x81C2,
+	0xC176, 0x81C0, 0xC177, 0x81BF, 0xC178, 0x81BD, 0xC179, 0x81C9,	0xC17A, 0x81BE, 0xC17B, 0x81E8, 0xC17C, 0x8209, 0xC17D, 0x8271,
+	0xC17E, 0x85AA, 0xC1A1, 0x8584, 0xC1A2, 0x857E, 0xC1A3, 0x859C,	0xC1A4, 0x8591, 0xC1A5, 0x8594, 0xC1A6, 0x85AF, 0xC1A7, 0x859B,
+	0xC1A8, 0x8587, 0xC1A9, 0x85A8, 0xC1AA, 0x858A, 0xC1AB, 0x8667,	0xC1AC, 0x87C0, 0xC1AD, 0x87D1, 0xC1AE, 0x87B3, 0xC1AF, 0x87D2,
+	0xC1B0, 0x87C6, 0xC1B1, 0x87AB, 0xC1B2, 0x87BB, 0xC1B3, 0x87BA,	0xC1B4, 0x87C8, 0xC1B5, 0x87CB, 0xC1B6, 0x893B, 0xC1B7, 0x8936,
+	0xC1B8, 0x8944, 0xC1B9, 0x8938, 0xC1BA, 0x893D, 0xC1BB, 0x89AC,	0xC1BC, 0x8B0E, 0xC1BD, 0x8B17, 0xC1BE, 0x8B19, 0xC1BF, 0x8B1B,
+	0xC1C0, 0x8B0A, 0xC1C1, 0x8B20, 0xC1C2, 0x8B1D, 0xC1C3, 0x8B04,	0xC1C4, 0x8B10, 0xC1C5, 0x8C41, 0xC1C6, 0x8C3F, 0xC1C7, 0x8C73,
+	0xC1C8, 0x8CFA, 0xC1C9, 0x8CFD, 0xC1CA, 0x8CFC, 0xC1CB, 0x8CF8,	0xC1CC, 0x8CFB, 0xC1CD, 0x8DA8, 0xC1CE, 0x8E49, 0xC1CF, 0x8E4B,
+	0xC1D0, 0x8E48, 0xC1D1, 0x8E4A, 0xC1D2, 0x8F44, 0xC1D3, 0x8F3E,	0xC1D4, 0x8F42, 0xC1D5, 0x8F45, 0xC1D6, 0x8F3F, 0xC1D7, 0x907F,
+	0xC1D8, 0x907D, 0xC1D9, 0x9084, 0xC1DA, 0x9081, 0xC1DB, 0x9082,	0xC1DC, 0x9080, 0xC1DD, 0x9139, 0xC1DE, 0x91A3, 0xC1DF, 0x919E,
+	0xC1E0, 0x919C, 0xC1E1, 0x934D, 0xC1E2, 0x9382, 0xC1E3, 0x9328,	0xC1E4, 0x9375, 0xC1E5, 0x934A, 0xC1E6, 0x9365, 0xC1E7, 0x934B,
+	0xC1E8, 0x9318, 0xC1E9, 0x937E, 0xC1EA, 0x936C, 0xC1EB, 0x935B,	0xC1EC, 0x9370, 0xC1ED, 0x935A, 0xC1EE, 0x9354, 0xC1EF, 0x95CA,
+	0xC1F0, 0x95CB, 0xC1F1, 0x95CC, 0xC1F2, 0x95C8, 0xC1F3, 0x95C6,	0xC1F4, 0x96B1, 0xC1F5, 0x96B8, 0xC1F6, 0x96D6, 0xC1F7, 0x971C,
+	0xC1F8, 0x971E, 0xC1F9, 0x97A0, 0xC1FA, 0x97D3, 0xC1FB, 0x9846,	0xC1FC, 0x98B6, 0xC1FD, 0x9935, 0xC1FE, 0x9A01, 0xC240, 0x99FF,
+	0xC241, 0x9BAE, 0xC242, 0x9BAB, 0xC243, 0x9BAA, 0xC244, 0x9BAD,	0xC245, 0x9D3B, 0xC246, 0x9D3F, 0xC247, 0x9E8B, 0xC248, 0x9ECF,
+	0xC249, 0x9EDE, 0xC24A, 0x9EDC, 0xC24B, 0x9EDD, 0xC24C, 0x9EDB,	0xC24D, 0x9F3E, 0xC24E, 0x9F4B, 0xC24F, 0x53E2, 0xC250, 0x5695,
+	0xC251, 0x56AE, 0xC252, 0x58D9, 0xC253, 0x58D8, 0xC254, 0x5B38,	0xC255, 0x5F5D, 0xC256, 0x61E3, 0xC257, 0x6233, 0xC258, 0x64F4,
+	0xC259, 0x64F2, 0xC25A, 0x64FE, 0xC25B, 0x6506, 0xC25C, 0x64FA,	0xC25D, 0x64FB, 0xC25E, 0x64F7, 0xC25F, 0x65B7, 0xC260, 0x66DC,
+	0xC261, 0x6726, 0xC262, 0x6AB3, 0xC263, 0x6AAC, 0xC264, 0x6AC3,	0xC265, 0x6ABB, 0xC266, 0x6AB8, 0xC267, 0x6AC2, 0xC268, 0x6AAE,
+	0xC269, 0x6AAF, 0xC26A, 0x6B5F, 0xC26B, 0x6B78, 0xC26C, 0x6BAF,	0xC26D, 0x7009, 0xC26E, 0x700B, 0xC26F, 0x6FFE, 0xC270, 0x7006,
+	0xC271, 0x6FFA, 0xC272, 0x7011, 0xC273, 0x700F, 0xC274, 0x71FB,	0xC275, 0x71FC, 0xC276, 0x71FE, 0xC277, 0x71F8, 0xC278, 0x7377,
+	0xC279, 0x7375, 0xC27A, 0x74A7, 0xC27B, 0x74BF, 0xC27C, 0x7515,	0xC27D, 0x7656, 0xC27E, 0x7658, 0xC2A1, 0x7652, 0xC2A2, 0x77BD,
+	0xC2A3, 0x77BF, 0xC2A4, 0x77BB, 0xC2A5, 0x77BC, 0xC2A6, 0x790E,	0xC2A7, 0x79AE, 0xC2A8, 0x7A61, 0xC2A9, 0x7A62, 0xC2AA, 0x7A60,
+	0xC2AB, 0x7AC4, 0xC2AC, 0x7AC5, 0xC2AD, 0x7C2B, 0xC2AE, 0x7C27,	0xC2AF, 0x7C2A, 0xC2B0, 0x7C1E, 0xC2B1, 0x7C23, 0xC2B2, 0x7C21,
+	0xC2B3, 0x7CE7, 0xC2B4, 0x7E54, 0xC2B5, 0x7E55, 0xC2B6, 0x7E5E,	0xC2B7, 0x7E5A, 0xC2B8, 0x7E61, 0xC2B9, 0x7E52, 0xC2BA, 0x7E59,
+	0xC2BB, 0x7F48, 0xC2BC, 0x7FF9, 0xC2BD, 0x7FFB, 0xC2BE, 0x8077,	0xC2BF, 0x8076, 0xC2C0, 0x81CD, 0xC2C1, 0x81CF, 0xC2C2, 0x820A,
+	0xC2C3, 0x85CF, 0xC2C4, 0x85A9, 0xC2C5, 0x85CD, 0xC2C6, 0x85D0,	0xC2C7, 0x85C9, 0xC2C8, 0x85B0, 0xC2C9, 0x85BA, 0xC2CA, 0x85B9,
+	0xC2CB, 0x85A6, 0xC2CC, 0x87EF, 0xC2CD, 0x87EC, 0xC2CE, 0x87F2,	0xC2CF, 0x87E0, 0xC2D0, 0x8986, 0xC2D1, 0x89B2, 0xC2D2, 0x89F4,
+	0xC2D3, 0x8B28, 0xC2D4, 0x8B39, 0xC2D5, 0x8B2C, 0xC2D6, 0x8B2B,	0xC2D7, 0x8C50, 0xC2D8, 0x8D05, 0xC2D9, 0x8E59, 0xC2DA, 0x8E63,
+	0xC2DB, 0x8E66, 0xC2DC, 0x8E64, 0xC2DD, 0x8E5F, 0xC2DE, 0x8E55,	0xC2DF, 0x8EC0, 0xC2E0, 0x8F49, 0xC2E1, 0x8F4D, 0xC2E2, 0x9087,
+	0xC2E3, 0x9083, 0xC2E4, 0x9088, 0xC2E5, 0x91AB, 0xC2E6, 0x91AC,	0xC2E7, 0x91D0, 0xC2E8, 0x9394, 0xC2E9, 0x938A, 0xC2EA, 0x9396,
+	0xC2EB, 0x93A2, 0xC2EC, 0x93B3, 0xC2ED, 0x93AE, 0xC2EE, 0x93AC,	0xC2EF, 0x93B0, 0xC2F0, 0x9398, 0xC2F1, 0x939A, 0xC2F2, 0x9397,
+	0xC2F3, 0x95D4, 0xC2F4, 0x95D6, 0xC2F5, 0x95D0, 0xC2F6, 0x95D5,	0xC2F7, 0x96E2, 0xC2F8, 0x96DC, 0xC2F9, 0x96D9, 0xC2FA, 0x96DB,
+	0xC2FB, 0x96DE, 0xC2FC, 0x9724, 0xC2FD, 0x97A3, 0xC2FE, 0x97A6,	0xC340, 0x97AD, 0xC341, 0x97F9, 0xC342, 0x984D, 0xC343, 0x984F,
+	0xC344, 0x984C, 0xC345, 0x984E, 0xC346, 0x9853, 0xC347, 0x98BA,	0xC348, 0x993E, 0xC349, 0x993F, 0xC34A, 0x993D, 0xC34B, 0x992E,
+	0xC34C, 0x99A5, 0xC34D, 0x9A0E, 0xC34E, 0x9AC1, 0xC34F, 0x9B03,	0xC350, 0x9B06, 0xC351, 0x9B4F, 0xC352, 0x9B4E, 0xC353, 0x9B4D,
+	0xC354, 0x9BCA, 0xC355, 0x9BC9, 0xC356, 0x9BFD, 0xC357, 0x9BC8,	0xC358, 0x9BC0, 0xC359, 0x9D51, 0xC35A, 0x9D5D, 0xC35B, 0x9D60,
+	0xC35C, 0x9EE0, 0xC35D, 0x9F15, 0xC35E, 0x9F2C, 0xC35F, 0x5133,	0xC360, 0x56A5, 0xC361, 0x58DE, 0xC362, 0x58DF, 0xC363, 0x58E2,
+	0xC364, 0x5BF5, 0xC365, 0x9F90, 0xC366, 0x5EEC, 0xC367, 0x61F2,	0xC368, 0x61F7, 0xC369, 0x61F6, 0xC36A, 0x61F5, 0xC36B, 0x6500,
+	0xC36C, 0x650F, 0xC36D, 0x66E0, 0xC36E, 0x66DD, 0xC36F, 0x6AE5,	0xC370, 0x6ADD, 0xC371, 0x6ADA, 0xC372, 0x6AD3, 0xC373, 0x701B,
+	0xC374, 0x701F, 0xC375, 0x7028, 0xC376, 0x701A, 0xC377, 0x701D,	0xC378, 0x7015, 0xC379, 0x7018, 0xC37A, 0x7206, 0xC37B, 0x720D,
+	0xC37C, 0x7258, 0xC37D, 0x72A2, 0xC37E, 0x7378, 0xC3A1, 0x737A,	0xC3A2, 0x74BD, 0xC3A3, 0x74CA, 0xC3A4, 0x74E3, 0xC3A5, 0x7587,
+	0xC3A6, 0x7586, 0xC3A7, 0x765F, 0xC3A8, 0x7661, 0xC3A9, 0x77C7,	0xC3AA, 0x7919, 0xC3AB, 0x79B1, 0xC3AC, 0x7A6B, 0xC3AD, 0x7A69,
+	0xC3AE, 0x7C3E, 0xC3AF, 0x7C3F, 0xC3B0, 0x7C38, 0xC3B1, 0x7C3D,	0xC3B2, 0x7C37, 0xC3B3, 0x7C40, 0xC3B4, 0x7E6B, 0xC3B5, 0x7E6D,
+	0xC3B6, 0x7E79, 0xC3B7, 0x7E69, 0xC3B8, 0x7E6A, 0xC3B9, 0x7F85,	0xC3BA, 0x7E73, 0xC3BB, 0x7FB6, 0xC3BC, 0x7FB9, 0xC3BD, 0x7FB8,
+	0xC3BE, 0x81D8, 0xC3BF, 0x85E9, 0xC3C0, 0x85DD, 0xC3C1, 0x85EA,	0xC3C2, 0x85D5, 0xC3C3, 0x85E4, 0xC3C4, 0x85E5, 0xC3C5, 0x85F7,
+	0xC3C6, 0x87FB, 0xC3C7, 0x8805, 0xC3C8, 0x880D, 0xC3C9, 0x87F9,	0xC3CA, 0x87FE, 0xC3CB, 0x8960, 0xC3CC, 0x895F, 0xC3CD, 0x8956,
+	0xC3CE, 0x895E, 0xC3CF, 0x8B41, 0xC3D0, 0x8B5C, 0xC3D1, 0x8B58,	0xC3D2, 0x8B49, 0xC3D3, 0x8B5A, 0xC3D4, 0x8B4E, 0xC3D5, 0x8B4F,
+	0xC3D6, 0x8B46, 0xC3D7, 0x8B59, 0xC3D8, 0x8D08, 0xC3D9, 0x8D0A,	0xC3DA, 0x8E7C, 0xC3DB, 0x8E72, 0xC3DC, 0x8E87, 0xC3DD, 0x8E76,
+	0xC3DE, 0x8E6C, 0xC3DF, 0x8E7A, 0xC3E0, 0x8E74, 0xC3E1, 0x8F54,	0xC3E2, 0x8F4E, 0xC3E3, 0x8FAD, 0xC3E4, 0x908A, 0xC3E5, 0x908B,
+	0xC3E6, 0x91B1, 0xC3E7, 0x91AE, 0xC3E8, 0x93E1, 0xC3E9, 0x93D1,	0xC3EA, 0x93DF, 0xC3EB, 0x93C3, 0xC3EC, 0x93C8, 0xC3ED, 0x93DC,
+	0xC3EE, 0x93DD, 0xC3EF, 0x93D6, 0xC3F0, 0x93E2, 0xC3F1, 0x93CD,	0xC3F2, 0x93D8, 0xC3F3, 0x93E4, 0xC3F4, 0x93D7, 0xC3F5, 0x93E8,
+	0xC3F6, 0x95DC, 0xC3F7, 0x96B4, 0xC3F8, 0x96E3, 0xC3F9, 0x972A,	0xC3FA, 0x9727, 0xC3FB, 0x9761, 0xC3FC, 0x97DC, 0xC3FD, 0x97FB,
+	0xC3FE, 0x985E, 0xC440, 0x9858, 0xC441, 0x985B, 0xC442, 0x98BC,	0xC443, 0x9945, 0xC444, 0x9949, 0xC445, 0x9A16, 0xC446, 0x9A19,
+	0xC447, 0x9B0D, 0xC448, 0x9BE8, 0xC449, 0x9BE7, 0xC44A, 0x9BD6,	0xC44B, 0x9BDB, 0xC44C, 0x9D89, 0xC44D, 0x9D61, 0xC44E, 0x9D72,
+	0xC44F, 0x9D6A, 0xC450, 0x9D6C, 0xC451, 0x9E92, 0xC452, 0x9E97,	0xC453, 0x9E93, 0xC454, 0x9EB4, 0xC455, 0x52F8, 0xC456, 0x56A8,
+	0xC457, 0x56B7, 0xC458, 0x56B6, 0xC459, 0x56B4, 0xC45A, 0x56BC,	0xC45B, 0x58E4, 0xC45C, 0x5B40, 0xC45D, 0x5B43, 0xC45E, 0x5B7D,
+	0xC45F, 0x5BF6, 0xC460, 0x5DC9, 0xC461, 0x61F8, 0xC462, 0x61FA,	0xC463, 0x6518, 0xC464, 0x6514, 0xC465, 0x6519, 0xC466, 0x66E6,
+	0xC467, 0x6727, 0xC468, 0x6AEC, 0xC469, 0x703E, 0xC46A, 0x7030,	0xC46B, 0x7032, 0xC46C, 0x7210, 0xC46D, 0x737B, 0xC46E, 0x74CF,
+	0xC46F, 0x7662, 0xC470, 0x7665, 0xC471, 0x7926, 0xC472, 0x792A,	0xC473, 0x792C, 0xC474, 0x792B, 0xC475, 0x7AC7, 0xC476, 0x7AF6,
+	0xC477, 0x7C4C, 0xC478, 0x7C43, 0xC479, 0x7C4D, 0xC47A, 0x7CEF,	0xC47B, 0x7CF0, 0xC47C, 0x8FAE, 0xC47D, 0x7E7D, 0xC47E, 0x7E7C,
+	0xC4A1, 0x7E82, 0xC4A2, 0x7F4C, 0xC4A3, 0x8000, 0xC4A4, 0x81DA,	0xC4A5, 0x8266, 0xC4A6, 0x85FB, 0xC4A7, 0x85F9, 0xC4A8, 0x8611,
+	0xC4A9, 0x85FA, 0xC4AA, 0x8606, 0xC4AB, 0x860B, 0xC4AC, 0x8607,	0xC4AD, 0x860A, 0xC4AE, 0x8814, 0xC4AF, 0x8815, 0xC4B0, 0x8964,
+	0xC4B1, 0x89BA, 0xC4B2, 0x89F8, 0xC4B3, 0x8B70, 0xC4B4, 0x8B6C,	0xC4B5, 0x8B66, 0xC4B6, 0x8B6F, 0xC4B7, 0x8B5F, 0xC4B8, 0x8B6B,
+	0xC4B9, 0x8D0F, 0xC4BA, 0x8D0D, 0xC4BB, 0x8E89, 0xC4BC, 0x8E81,	0xC4BD, 0x8E85, 0xC4BE, 0x8E82, 0xC4BF, 0x91B4, 0xC4C0, 0x91CB,
+	0xC4C1, 0x9418, 0xC4C2, 0x9403, 0xC4C3, 0x93FD, 0xC4C4, 0x95E1,	0xC4C5, 0x9730, 0xC4C6, 0x98C4, 0xC4C7, 0x9952, 0xC4C8, 0x9951,
+	0xC4C9, 0x99A8, 0xC4CA, 0x9A2B, 0xC4CB, 0x9A30, 0xC4CC, 0x9A37,	0xC4CD, 0x9A35, 0xC4CE, 0x9C13, 0xC4CF, 0x9C0D, 0xC4D0, 0x9E79,
+	0xC4D1, 0x9EB5, 0xC4D2, 0x9EE8, 0xC4D3, 0x9F2F, 0xC4D4, 0x9F5F,	0xC4D5, 0x9F63, 0xC4D6, 0x9F61, 0xC4D7, 0x5137, 0xC4D8, 0x5138,
+	0xC4D9, 0x56C1, 0xC4DA, 0x56C0, 0xC4DB, 0x56C2, 0xC4DC, 0x5914,	0xC4DD, 0x5C6C, 0xC4DE, 0x5DCD, 0xC4DF, 0x61FC, 0xC4E0, 0x61FE,
+	0xC4E1, 0x651D, 0xC4E2, 0x651C, 0xC4E3, 0x6595, 0xC4E4, 0x66E9,	0xC4E5, 0x6AFB, 0xC4E6, 0x6B04, 0xC4E7, 0x6AFA, 0xC4E8, 0x6BB2,
+	0xC4E9, 0x704C, 0xC4EA, 0x721B, 0xC4EB, 0x72A7, 0xC4EC, 0x74D6,	0xC4ED, 0x74D4, 0xC4EE, 0x7669, 0xC4EF, 0x77D3, 0xC4F0, 0x7C50,
+	0xC4F1, 0x7E8F, 0xC4F2, 0x7E8C, 0xC4F3, 0x7FBC, 0xC4F4, 0x8617,	0xC4F5, 0x862D, 0xC4F6, 0x861A, 0xC4F7, 0x8823, 0xC4F8, 0x8822,
+	0xC4F9, 0x8821, 0xC4FA, 0x881F, 0xC4FB, 0x896A, 0xC4FC, 0x896C,	0xC4FD, 0x89BD, 0xC4FE, 0x8B74, 0xC540, 0x8B77, 0xC541, 0x8B7D,
+	0xC542, 0x8D13, 0xC543, 0x8E8A, 0xC544, 0x8E8D, 0xC545, 0x8E8B,	0xC546, 0x8F5F, 0xC547, 0x8FAF, 0xC548, 0x91BA, 0xC549, 0x942E,
+	0xC54A, 0x9433, 0xC54B, 0x9435, 0xC54C, 0x943A, 0xC54D, 0x9438,	0xC54E, 0x9432, 0xC54F, 0x942B, 0xC550, 0x95E2, 0xC551, 0x9738,
+	0xC552, 0x9739, 0xC553, 0x9732, 0xC554, 0x97FF, 0xC555, 0x9867,	0xC556, 0x9865, 0xC557, 0x9957, 0xC558, 0x9A45, 0xC559, 0x9A43,
+	0xC55A, 0x9A40, 0xC55B, 0x9A3E, 0xC55C, 0x9ACF, 0xC55D, 0x9B54,	0xC55E, 0x9B51, 0xC55F, 0x9C2D, 0xC560, 0x9C25, 0xC561, 0x9DAF,
+	0xC562, 0x9DB4, 0xC563, 0x9DC2, 0xC564, 0x9DB8, 0xC565, 0x9E9D,	0xC566, 0x9EEF, 0xC567, 0x9F19, 0xC568, 0x9F5C, 0xC569, 0x9F66,
+	0xC56A, 0x9F67, 0xC56B, 0x513C, 0xC56C, 0x513B, 0xC56D, 0x56C8,	0xC56E, 0x56CA, 0xC56F, 0x56C9, 0xC570, 0x5B7F, 0xC571, 0x5DD4,
+	0xC572, 0x5DD2, 0xC573, 0x5F4E, 0xC574, 0x61FF, 0xC575, 0x6524,	0xC576, 0x6B0A, 0xC577, 0x6B61, 0xC578, 0x7051, 0xC579, 0x7058,
+	0xC57A, 0x7380, 0xC57B, 0x74E4, 0xC57C, 0x758A, 0xC57D, 0x766E,	0xC57E, 0x766C, 0xC5A1, 0x79B3, 0xC5A2, 0x7C60, 0xC5A3, 0x7C5F,
+	0xC5A4, 0x807E, 0xC5A5, 0x807D, 0xC5A6, 0x81DF, 0xC5A7, 0x8972,	0xC5A8, 0x896F, 0xC5A9, 0x89FC, 0xC5AA, 0x8B80, 0xC5AB, 0x8D16,
+	0xC5AC, 0x8D17, 0xC5AD, 0x8E91, 0xC5AE, 0x8E93, 0xC5AF, 0x8F61,	0xC5B0, 0x9148, 0xC5B1, 0x9444, 0xC5B2, 0x9451, 0xC5B3, 0x9452,
+	0xC5B4, 0x973D, 0xC5B5, 0x973E, 0xC5B6, 0x97C3, 0xC5B7, 0x97C1,	0xC5B8, 0x986B, 0xC5B9, 0x9955, 0xC5BA, 0x9A55, 0xC5BB, 0x9A4D,
+	0xC5BC, 0x9AD2, 0xC5BD, 0x9B1A, 0xC5BE, 0x9C49, 0xC5BF, 0x9C31,	0xC5C0, 0x9C3E, 0xC5C1, 0x9C3B, 0xC5C2, 0x9DD3, 0xC5C3, 0x9DD7,
+	0xC5C4, 0x9F34, 0xC5C5, 0x9F6C, 0xC5C6, 0x9F6A, 0xC5C7, 0x9F94,	0xC5C8, 0x56CC, 0xC5C9, 0x5DD6, 0xC5CA, 0x6200, 0xC5CB, 0x6523,
+	0xC5CC, 0x652B, 0xC5CD, 0x652A, 0xC5CE, 0x66EC, 0xC5CF, 0x6B10,	0xC5D0, 0x74DA, 0xC5D1, 0x7ACA, 0xC5D2, 0x7C64, 0xC5D3, 0x7C63,
+	0xC5D4, 0x7C65, 0xC5D5, 0x7E93, 0xC5D6, 0x7E96, 0xC5D7, 0x7E94,	0xC5D8, 0x81E2, 0xC5D9, 0x8638, 0xC5DA, 0x863F, 0xC5DB, 0x8831,
+	0xC5DC, 0x8B8A, 0xC5DD, 0x9090, 0xC5DE, 0x908F, 0xC5DF, 0x9463,	0xC5E0, 0x9460, 0xC5E1, 0x9464, 0xC5E2, 0x9768, 0xC5E3, 0x986F,
+	0xC5E4, 0x995C, 0xC5E5, 0x9A5A, 0xC5E6, 0x9A5B, 0xC5E7, 0x9A57,	0xC5E8, 0x9AD3, 0xC5E9, 0x9AD4, 0xC5EA, 0x9AD1, 0xC5EB, 0x9C54,
+	0xC5EC, 0x9C57, 0xC5ED, 0x9C56, 0xC5EE, 0x9DE5, 0xC5EF, 0x9E9F,	0xC5F0, 0x9EF4, 0xC5F1, 0x56D1, 0xC5F2, 0x58E9, 0xC5F3, 0x652C,
+	0xC5F4, 0x705E, 0xC5F5, 0x7671, 0xC5F6, 0x7672, 0xC5F7, 0x77D7,	0xC5F8, 0x7F50, 0xC5F9, 0x7F88, 0xC5FA, 0x8836, 0xC5FB, 0x8839,
+	0xC5FC, 0x8862, 0xC5FD, 0x8B93, 0xC5FE, 0x8B92, 0xC640, 0x8B96,	0xC641, 0x8277, 0xC642, 0x8D1B, 0xC643, 0x91C0, 0xC644, 0x946A,
+	0xC645, 0x9742, 0xC646, 0x9748, 0xC647, 0x9744, 0xC648, 0x97C6,	0xC649, 0x9870, 0xC64A, 0x9A5F, 0xC64B, 0x9B22, 0xC64C, 0x9B58,
+	0xC64D, 0x9C5F, 0xC64E, 0x9DF9, 0xC64F, 0x9DFA, 0xC650, 0x9E7C,	0xC651, 0x9E7D, 0xC652, 0x9F07, 0xC653, 0x9F77, 0xC654, 0x9F72,
+	0xC655, 0x5EF3, 0xC656, 0x6B16, 0xC657, 0x7063, 0xC658, 0x7C6C,	0xC659, 0x7C6E, 0xC65A, 0x883B, 0xC65B, 0x89C0, 0xC65C, 0x8EA1,
+	0xC65D, 0x91C1, 0xC65E, 0x9472, 0xC65F, 0x9470, 0xC660, 0x9871,	0xC661, 0x995E, 0xC662, 0x9AD6, 0xC663, 0x9B23, 0xC664, 0x9ECC,
+	0xC665, 0x7064, 0xC666, 0x77DA, 0xC667, 0x8B9A, 0xC668, 0x9477,	0xC669, 0x97C9, 0xC66A, 0x9A62, 0xC66B, 0x9A65, 0xC66C, 0x7E9C,
+	0xC66D, 0x8B9C, 0xC66E, 0x8EAA, 0xC66F, 0x91C5, 0xC670, 0x947D,	0xC671, 0x947E, 0xC672, 0x947C, 0xC673, 0x9C77, 0xC674, 0x9C78,
+	0xC675, 0x9EF7, 0xC676, 0x8C54, 0xC677, 0x947F, 0xC678, 0x9E1A,	0xC679, 0x7228, 0xC67A, 0x9A6A, 0xC67B, 0x9B31, 0xC67C, 0x9E1B,
+	0xC67D, 0x9E1E, 0xC67E, 0x7C72, 0xC940, 0x4E42, 0xC941, 0x4E5C,	0xC942, 0x51F5, 0xC943, 0x531A, 0xC944, 0x5382, 0xC945, 0x4E07,
+	0xC946, 0x4E0C, 0xC947, 0x4E47, 0xC948, 0x4E8D, 0xC949, 0x56D7,	0xC94A, 0xFA0C, 0xC94B, 0x5C6E, 0xC94C, 0x5F73, 0xC94D, 0x4E0F,
+	0xC94E, 0x5187, 0xC94F, 0x4E0E, 0xC950, 0x4E2E, 0xC951, 0x4E93,	0xC952, 0x4EC2, 0xC953, 0x4EC9, 0xC954, 0x4EC8, 0xC955, 0x5198,
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+	0xC95E, 0x65E1, 0xC95F, 0x6BB3, 0xC960, 0x6BCC, 0xC961, 0x6C14,	0xC962, 0x723F, 0xC963, 0x4E31, 0xC964, 0x4E3C, 0xC965, 0x4EE8,
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+	0xCDBC, 0x829E, 0xCDBD, 0x82BA, 0xCDBE, 0x82B4, 0xCDBF, 0x82A8,	0xCDC0, 0x82A1, 0xCDC1, 0x82A9, 0xCDC2, 0x82C2, 0xCDC3, 0x82A4,
+	0xCDC4, 0x82C3, 0xCDC5, 0x82B6, 0xCDC6, 0x82A2, 0xCDC7, 0x8670,	0xCDC8, 0x866F, 0xCDC9, 0x866D, 0xCDCA, 0x866E, 0xCDCB, 0x8C56,
+	0xCDCC, 0x8FD2, 0xCDCD, 0x8FCB, 0xCDCE, 0x8FD3, 0xCDCF, 0x8FCD,	0xCDD0, 0x8FD6, 0xCDD1, 0x8FD5, 0xCDD2, 0x8FD7, 0xCDD3, 0x90B2,
+	0xCDD4, 0x90B4, 0xCDD5, 0x90AF, 0xCDD6, 0x90B3, 0xCDD7, 0x90B0,	0xCDD8, 0x9639, 0xCDD9, 0x963D, 0xCDDA, 0x963C, 0xCDDB, 0x963A,
+	0xCDDC, 0x9643, 0xCDDD, 0x4FCD, 0xCDDE, 0x4FC5, 0xCDDF, 0x4FD3,	0xCDE0, 0x4FB2, 0xCDE1, 0x4FC9, 0xCDE2, 0x4FCB, 0xCDE3, 0x4FC1,
+	0xCDE4, 0x4FD4, 0xCDE5, 0x4FDC, 0xCDE6, 0x4FD9, 0xCDE7, 0x4FBB,	0xCDE8, 0x4FB3, 0xCDE9, 0x4FDB, 0xCDEA, 0x4FC7, 0xCDEB, 0x4FD6,
+	0xCDEC, 0x4FBA, 0xCDED, 0x4FC0, 0xCDEE, 0x4FB9, 0xCDEF, 0x4FEC,	0xCDF0, 0x5244, 0xCDF1, 0x5249, 0xCDF2, 0x52C0, 0xCDF3, 0x52C2,
+	0xCDF4, 0x533D, 0xCDF5, 0x537C, 0xCDF6, 0x5397, 0xCDF7, 0x5396,	0xCDF8, 0x5399, 0xCDF9, 0x5398, 0xCDFA, 0x54BA, 0xCDFB, 0x54A1,
+	0xCDFC, 0x54AD, 0xCDFD, 0x54A5, 0xCDFE, 0x54CF, 0xCE40, 0x54C3,	0xCE41, 0x830D, 0xCE42, 0x54B7, 0xCE43, 0x54AE, 0xCE44, 0x54D6,
+	0xCE45, 0x54B6, 0xCE46, 0x54C5, 0xCE47, 0x54C6, 0xCE48, 0x54A0,	0xCE49, 0x5470, 0xCE4A, 0x54BC, 0xCE4B, 0x54A2, 0xCE4C, 0x54BE,
+	0xCE4D, 0x5472, 0xCE4E, 0x54DE, 0xCE4F, 0x54B0, 0xCE50, 0x57B5,	0xCE51, 0x579E, 0xCE52, 0x579F, 0xCE53, 0x57A4, 0xCE54, 0x578C,
+	0xCE55, 0x5797, 0xCE56, 0x579D, 0xCE57, 0x579B, 0xCE58, 0x5794,	0xCE59, 0x5798, 0xCE5A, 0x578F, 0xCE5B, 0x5799, 0xCE5C, 0x57A5,
+	0xCE5D, 0x579A, 0xCE5E, 0x5795, 0xCE5F, 0x58F4, 0xCE60, 0x590D,	0xCE61, 0x5953, 0xCE62, 0x59E1, 0xCE63, 0x59DE, 0xCE64, 0x59EE,
+	0xCE65, 0x5A00, 0xCE66, 0x59F1, 0xCE67, 0x59DD, 0xCE68, 0x59FA,	0xCE69, 0x59FD, 0xCE6A, 0x59FC, 0xCE6B, 0x59F6, 0xCE6C, 0x59E4,
+	0xCE6D, 0x59F2, 0xCE6E, 0x59F7, 0xCE6F, 0x59DB, 0xCE70, 0x59E9,	0xCE71, 0x59F3, 0xCE72, 0x59F5, 0xCE73, 0x59E0, 0xCE74, 0x59FE,
+	0xCE75, 0x59F4, 0xCE76, 0x59ED, 0xCE77, 0x5BA8, 0xCE78, 0x5C4C,	0xCE79, 0x5CD0, 0xCE7A, 0x5CD8, 0xCE7B, 0x5CCC, 0xCE7C, 0x5CD7,
+	0xCE7D, 0x5CCB, 0xCE7E, 0x5CDB, 0xCEA1, 0x5CDE, 0xCEA2, 0x5CDA,	0xCEA3, 0x5CC9, 0xCEA4, 0x5CC7, 0xCEA5, 0x5CCA, 0xCEA6, 0x5CD6,
+	0xCEA7, 0x5CD3, 0xCEA8, 0x5CD4, 0xCEA9, 0x5CCF, 0xCEAA, 0x5CC8,	0xCEAB, 0x5CC6, 0xCEAC, 0x5CCE, 0xCEAD, 0x5CDF, 0xCEAE, 0x5CF8,
+	0xCEAF, 0x5DF9, 0xCEB0, 0x5E21, 0xCEB1, 0x5E22, 0xCEB2, 0x5E23,	0xCEB3, 0x5E20, 0xCEB4, 0x5E24, 0xCEB5, 0x5EB0, 0xCEB6, 0x5EA4,
+	0xCEB7, 0x5EA2, 0xCEB8, 0x5E9B, 0xCEB9, 0x5EA3, 0xCEBA, 0x5EA5,	0xCEBB, 0x5F07, 0xCEBC, 0x5F2E, 0xCEBD, 0x5F56, 0xCEBE, 0x5F86,
+	0xCEBF, 0x6037, 0xCEC0, 0x6039, 0xCEC1, 0x6054, 0xCEC2, 0x6072,	0xCEC3, 0x605E, 0xCEC4, 0x6045, 0xCEC5, 0x6053, 0xCEC6, 0x6047,
+	0xCEC7, 0x6049, 0xCEC8, 0x605B, 0xCEC9, 0x604C, 0xCECA, 0x6040,	0xCECB, 0x6042, 0xCECC, 0x605F, 0xCECD, 0x6024, 0xCECE, 0x6044,
+	0xCECF, 0x6058, 0xCED0, 0x6066, 0xCED1, 0x606E, 0xCED2, 0x6242,	0xCED3, 0x6243, 0xCED4, 0x62CF, 0xCED5, 0x630D, 0xCED6, 0x630B,
+	0xCED7, 0x62F5, 0xCED8, 0x630E, 0xCED9, 0x6303, 0xCEDA, 0x62EB,	0xCEDB, 0x62F9, 0xCEDC, 0x630F, 0xCEDD, 0x630C, 0xCEDE, 0x62F8,
+	0xCEDF, 0x62F6, 0xCEE0, 0x6300, 0xCEE1, 0x6313, 0xCEE2, 0x6314,	0xCEE3, 0x62FA, 0xCEE4, 0x6315, 0xCEE5, 0x62FB, 0xCEE6, 0x62F0,
+	0xCEE7, 0x6541, 0xCEE8, 0x6543, 0xCEE9, 0x65AA, 0xCEEA, 0x65BF,	0xCEEB, 0x6636, 0xCEEC, 0x6621, 0xCEED, 0x6632, 0xCEEE, 0x6635,
+	0xCEEF, 0x661C, 0xCEF0, 0x6626, 0xCEF1, 0x6622, 0xCEF2, 0x6633,	0xCEF3, 0x662B, 0xCEF4, 0x663A, 0xCEF5, 0x661D, 0xCEF6, 0x6634,
+	0xCEF7, 0x6639, 0xCEF8, 0x662E, 0xCEF9, 0x670F, 0xCEFA, 0x6710,	0xCEFB, 0x67C1, 0xCEFC, 0x67F2, 0xCEFD, 0x67C8, 0xCEFE, 0x67BA,
+	0xCF40, 0x67DC, 0xCF41, 0x67BB, 0xCF42, 0x67F8, 0xCF43, 0x67D8,	0xCF44, 0x67C0, 0xCF45, 0x67B7, 0xCF46, 0x67C5, 0xCF47, 0x67EB,
+	0xCF48, 0x67E4, 0xCF49, 0x67DF, 0xCF4A, 0x67B5, 0xCF4B, 0x67CD,	0xCF4C, 0x67B3, 0xCF4D, 0x67F7, 0xCF4E, 0x67F6, 0xCF4F, 0x67EE,
+	0xCF50, 0x67E3, 0xCF51, 0x67C2, 0xCF52, 0x67B9, 0xCF53, 0x67CE,	0xCF54, 0x67E7, 0xCF55, 0x67F0, 0xCF56, 0x67B2, 0xCF57, 0x67FC,
+	0xCF58, 0x67C6, 0xCF59, 0x67ED, 0xCF5A, 0x67CC, 0xCF5B, 0x67AE,	0xCF5C, 0x67E6, 0xCF5D, 0x67DB, 0xCF5E, 0x67FA, 0xCF5F, 0x67C9,
+	0xCF60, 0x67CA, 0xCF61, 0x67C3, 0xCF62, 0x67EA, 0xCF63, 0x67CB,	0xCF64, 0x6B28, 0xCF65, 0x6B82, 0xCF66, 0x6B84, 0xCF67, 0x6BB6,
+	0xCF68, 0x6BD6, 0xCF69, 0x6BD8, 0xCF6A, 0x6BE0, 0xCF6B, 0x6C20,	0xCF6C, 0x6C21, 0xCF6D, 0x6D28, 0xCF6E, 0x6D34, 0xCF6F, 0x6D2D,
+	0xCF70, 0x6D1F, 0xCF71, 0x6D3C, 0xCF72, 0x6D3F, 0xCF73, 0x6D12,	0xCF74, 0x6D0A, 0xCF75, 0x6CDA, 0xCF76, 0x6D33, 0xCF77, 0x6D04,
+	0xCF78, 0x6D19, 0xCF79, 0x6D3A, 0xCF7A, 0x6D1A, 0xCF7B, 0x6D11,	0xCF7C, 0x6D00, 0xCF7D, 0x6D1D, 0xCF7E, 0x6D42, 0xCFA1, 0x6D01,
+	0xCFA2, 0x6D18, 0xCFA3, 0x6D37, 0xCFA4, 0x6D03, 0xCFA5, 0x6D0F,	0xCFA6, 0x6D40, 0xCFA7, 0x6D07, 0xCFA8, 0x6D20, 0xCFA9, 0x6D2C,
+	0xCFAA, 0x6D08, 0xCFAB, 0x6D22, 0xCFAC, 0x6D09, 0xCFAD, 0x6D10,	0xCFAE, 0x70B7, 0xCFAF, 0x709F, 0xCFB0, 0x70BE, 0xCFB1, 0x70B1,
+	0xCFB2, 0x70B0, 0xCFB3, 0x70A1, 0xCFB4, 0x70B4, 0xCFB5, 0x70B5,	0xCFB6, 0x70A9, 0xCFB7, 0x7241, 0xCFB8, 0x7249, 0xCFB9, 0x724A,
+	0xCFBA, 0x726C, 0xCFBB, 0x7270, 0xCFBC, 0x7273, 0xCFBD, 0x726E,	0xCFBE, 0x72CA, 0xCFBF, 0x72E4, 0xCFC0, 0x72E8, 0xCFC1, 0x72EB,
+	0xCFC2, 0x72DF, 0xCFC3, 0x72EA, 0xCFC4, 0x72E6, 0xCFC5, 0x72E3,	0xCFC6, 0x7385, 0xCFC7, 0x73CC, 0xCFC8, 0x73C2, 0xCFC9, 0x73C8,
+	0xCFCA, 0x73C5, 0xCFCB, 0x73B9, 0xCFCC, 0x73B6, 0xCFCD, 0x73B5,	0xCFCE, 0x73B4, 0xCFCF, 0x73EB, 0xCFD0, 0x73BF, 0xCFD1, 0x73C7,
+	0xCFD2, 0x73BE, 0xCFD3, 0x73C3, 0xCFD4, 0x73C6, 0xCFD5, 0x73B8,	0xCFD6, 0x73CB, 0xCFD7, 0x74EC, 0xCFD8, 0x74EE, 0xCFD9, 0x752E,
+	0xCFDA, 0x7547, 0xCFDB, 0x7548, 0xCFDC, 0x75A7, 0xCFDD, 0x75AA,	0xCFDE, 0x7679, 0xCFDF, 0x76C4, 0xCFE0, 0x7708, 0xCFE1, 0x7703,
+	0xCFE2, 0x7704, 0xCFE3, 0x7705, 0xCFE4, 0x770A, 0xCFE5, 0x76F7,	0xCFE6, 0x76FB, 0xCFE7, 0x76FA, 0xCFE8, 0x77E7, 0xCFE9, 0x77E8,
+	0xCFEA, 0x7806, 0xCFEB, 0x7811, 0xCFEC, 0x7812, 0xCFED, 0x7805,	0xCFEE, 0x7810, 0xCFEF, 0x780F, 0xCFF0, 0x780E, 0xCFF1, 0x7809,
+	0xCFF2, 0x7803, 0xCFF3, 0x7813, 0xCFF4, 0x794A, 0xCFF5, 0x794C,	0xCFF6, 0x794B, 0xCFF7, 0x7945, 0xCFF8, 0x7944, 0xCFF9, 0x79D5,
+	0xCFFA, 0x79CD, 0xCFFB, 0x79CF, 0xCFFC, 0x79D6, 0xCFFD, 0x79CE,	0xCFFE, 0x7A80, 0xD040, 0x7A7E, 0xD041, 0x7AD1, 0xD042, 0x7B00,
+	0xD043, 0x7B01, 0xD044, 0x7C7A, 0xD045, 0x7C78, 0xD046, 0x7C79,	0xD047, 0x7C7F, 0xD048, 0x7C80, 0xD049, 0x7C81, 0xD04A, 0x7D03,
+	0xD04B, 0x7D08, 0xD04C, 0x7D01, 0xD04D, 0x7F58, 0xD04E, 0x7F91,	0xD04F, 0x7F8D, 0xD050, 0x7FBE, 0xD051, 0x8007, 0xD052, 0x800E,
+	0xD053, 0x800F, 0xD054, 0x8014, 0xD055, 0x8037, 0xD056, 0x80D8,	0xD057, 0x80C7, 0xD058, 0x80E0, 0xD059, 0x80D1, 0xD05A, 0x80C8,
+	0xD05B, 0x80C2, 0xD05C, 0x80D0, 0xD05D, 0x80C5, 0xD05E, 0x80E3,	0xD05F, 0x80D9, 0xD060, 0x80DC, 0xD061, 0x80CA, 0xD062, 0x80D5,
+	0xD063, 0x80C9, 0xD064, 0x80CF, 0xD065, 0x80D7, 0xD066, 0x80E6,	0xD067, 0x80CD, 0xD068, 0x81FF, 0xD069, 0x8221, 0xD06A, 0x8294,
+	0xD06B, 0x82D9, 0xD06C, 0x82FE, 0xD06D, 0x82F9, 0xD06E, 0x8307,	0xD06F, 0x82E8, 0xD070, 0x8300, 0xD071, 0x82D5, 0xD072, 0x833A,
+	0xD073, 0x82EB, 0xD074, 0x82D6, 0xD075, 0x82F4, 0xD076, 0x82EC,	0xD077, 0x82E1, 0xD078, 0x82F2, 0xD079, 0x82F5, 0xD07A, 0x830C,
+	0xD07B, 0x82FB, 0xD07C, 0x82F6, 0xD07D, 0x82F0, 0xD07E, 0x82EA,	0xD0A1, 0x82E4, 0xD0A2, 0x82E0, 0xD0A3, 0x82FA, 0xD0A4, 0x82F3,
+	0xD0A5, 0x82ED, 0xD0A6, 0x8677, 0xD0A7, 0x8674, 0xD0A8, 0x867C,	0xD0A9, 0x8673, 0xD0AA, 0x8841, 0xD0AB, 0x884E, 0xD0AC, 0x8867,
+	0xD0AD, 0x886A, 0xD0AE, 0x8869, 0xD0AF, 0x89D3, 0xD0B0, 0x8A04,	0xD0B1, 0x8A07, 0xD0B2, 0x8D72, 0xD0B3, 0x8FE3, 0xD0B4, 0x8FE1,
+	0xD0B5, 0x8FEE, 0xD0B6, 0x8FE0, 0xD0B7, 0x90F1, 0xD0B8, 0x90BD,	0xD0B9, 0x90BF, 0xD0BA, 0x90D5, 0xD0BB, 0x90C5, 0xD0BC, 0x90BE,
+	0xD0BD, 0x90C7, 0xD0BE, 0x90CB, 0xD0BF, 0x90C8, 0xD0C0, 0x91D4,	0xD0C1, 0x91D3, 0xD0C2, 0x9654, 0xD0C3, 0x964F, 0xD0C4, 0x9651,
+	0xD0C5, 0x9653, 0xD0C6, 0x964A, 0xD0C7, 0x964E, 0xD0C8, 0x501E,	0xD0C9, 0x5005, 0xD0CA, 0x5007, 0xD0CB, 0x5013, 0xD0CC, 0x5022,
+	0xD0CD, 0x5030, 0xD0CE, 0x501B, 0xD0CF, 0x4FF5, 0xD0D0, 0x4FF4,	0xD0D1, 0x5033, 0xD0D2, 0x5037, 0xD0D3, 0x502C, 0xD0D4, 0x4FF6,
+	0xD0D5, 0x4FF7, 0xD0D6, 0x5017, 0xD0D7, 0x501C, 0xD0D8, 0x5020,	0xD0D9, 0x5027, 0xD0DA, 0x5035, 0xD0DB, 0x502F, 0xD0DC, 0x5031,
+	0xD0DD, 0x500E, 0xD0DE, 0x515A, 0xD0DF, 0x5194, 0xD0E0, 0x5193,	0xD0E1, 0x51CA, 0xD0E2, 0x51C4, 0xD0E3, 0x51C5, 0xD0E4, 0x51C8,
+	0xD0E5, 0x51CE, 0xD0E6, 0x5261, 0xD0E7, 0x525A, 0xD0E8, 0x5252,	0xD0E9, 0x525E, 0xD0EA, 0x525F, 0xD0EB, 0x5255, 0xD0EC, 0x5262,
+	0xD0ED, 0x52CD, 0xD0EE, 0x530E, 0xD0EF, 0x539E, 0xD0F0, 0x5526,	0xD0F1, 0x54E2, 0xD0F2, 0x5517, 0xD0F3, 0x5512, 0xD0F4, 0x54E7,
+	0xD0F5, 0x54F3, 0xD0F6, 0x54E4, 0xD0F7, 0x551A, 0xD0F8, 0x54FF,	0xD0F9, 0x5504, 0xD0FA, 0x5508, 0xD0FB, 0x54EB, 0xD0FC, 0x5511,
+	0xD0FD, 0x5505, 0xD0FE, 0x54F1, 0xD140, 0x550A, 0xD141, 0x54FB,	0xD142, 0x54F7, 0xD143, 0x54F8, 0xD144, 0x54E0, 0xD145, 0x550E,
+	0xD146, 0x5503, 0xD147, 0x550B, 0xD148, 0x5701, 0xD149, 0x5702,	0xD14A, 0x57CC, 0xD14B, 0x5832, 0xD14C, 0x57D5, 0xD14D, 0x57D2,
+	0xD14E, 0x57BA, 0xD14F, 0x57C6, 0xD150, 0x57BD, 0xD151, 0x57BC,	0xD152, 0x57B8, 0xD153, 0x57B6, 0xD154, 0x57BF, 0xD155, 0x57C7,
+	0xD156, 0x57D0, 0xD157, 0x57B9, 0xD158, 0x57C1, 0xD159, 0x590E,	0xD15A, 0x594A, 0xD15B, 0x5A19, 0xD15C, 0x5A16, 0xD15D, 0x5A2D,
+	0xD15E, 0x5A2E, 0xD15F, 0x5A15, 0xD160, 0x5A0F, 0xD161, 0x5A17,	0xD162, 0x5A0A, 0xD163, 0x5A1E, 0xD164, 0x5A33, 0xD165, 0x5B6C,
+	0xD166, 0x5BA7, 0xD167, 0x5BAD, 0xD168, 0x5BAC, 0xD169, 0x5C03,	0xD16A, 0x5C56, 0xD16B, 0x5C54, 0xD16C, 0x5CEC, 0xD16D, 0x5CFF,
+	0xD16E, 0x5CEE, 0xD16F, 0x5CF1, 0xD170, 0x5CF7, 0xD171, 0x5D00,	0xD172, 0x5CF9, 0xD173, 0x5E29, 0xD174, 0x5E28, 0xD175, 0x5EA8,
+	0xD176, 0x5EAE, 0xD177, 0x5EAA, 0xD178, 0x5EAC, 0xD179, 0x5F33,	0xD17A, 0x5F30, 0xD17B, 0x5F67, 0xD17C, 0x605D, 0xD17D, 0x605A,
+	0xD17E, 0x6067, 0xD1A1, 0x6041, 0xD1A2, 0x60A2, 0xD1A3, 0x6088,	0xD1A4, 0x6080, 0xD1A5, 0x6092, 0xD1A6, 0x6081, 0xD1A7, 0x609D,
+	0xD1A8, 0x6083, 0xD1A9, 0x6095, 0xD1AA, 0x609B, 0xD1AB, 0x6097,	0xD1AC, 0x6087, 0xD1AD, 0x609C, 0xD1AE, 0x608E, 0xD1AF, 0x6219,
+	0xD1B0, 0x6246, 0xD1B1, 0x62F2, 0xD1B2, 0x6310, 0xD1B3, 0x6356,	0xD1B4, 0x632C, 0xD1B5, 0x6344, 0xD1B6, 0x6345, 0xD1B7, 0x6336,
+	0xD1B8, 0x6343, 0xD1B9, 0x63E4, 0xD1BA, 0x6339, 0xD1BB, 0x634B,	0xD1BC, 0x634A, 0xD1BD, 0x633C, 0xD1BE, 0x6329, 0xD1BF, 0x6341,
+	0xD1C0, 0x6334, 0xD1C1, 0x6358, 0xD1C2, 0x6354, 0xD1C3, 0x6359,	0xD1C4, 0x632D, 0xD1C5, 0x6347, 0xD1C6, 0x6333, 0xD1C7, 0x635A,
+	0xD1C8, 0x6351, 0xD1C9, 0x6338, 0xD1CA, 0x6357, 0xD1CB, 0x6340,	0xD1CC, 0x6348, 0xD1CD, 0x654A, 0xD1CE, 0x6546, 0xD1CF, 0x65C6,
+	0xD1D0, 0x65C3, 0xD1D1, 0x65C4, 0xD1D2, 0x65C2, 0xD1D3, 0x664A,	0xD1D4, 0x665F, 0xD1D5, 0x6647, 0xD1D6, 0x6651, 0xD1D7, 0x6712,
+	0xD1D8, 0x6713, 0xD1D9, 0x681F, 0xD1DA, 0x681A, 0xD1DB, 0x6849,	0xD1DC, 0x6832, 0xD1DD, 0x6833, 0xD1DE, 0x683B, 0xD1DF, 0x684B,
+	0xD1E0, 0x684F, 0xD1E1, 0x6816, 0xD1E2, 0x6831, 0xD1E3, 0x681C,	0xD1E4, 0x6835, 0xD1E5, 0x682B, 0xD1E6, 0x682D, 0xD1E7, 0x682F,
+	0xD1E8, 0x684E, 0xD1E9, 0x6844, 0xD1EA, 0x6834, 0xD1EB, 0x681D,	0xD1EC, 0x6812, 0xD1ED, 0x6814, 0xD1EE, 0x6826, 0xD1EF, 0x6828,
+	0xD1F0, 0x682E, 0xD1F1, 0x684D, 0xD1F2, 0x683A, 0xD1F3, 0x6825,	0xD1F4, 0x6820, 0xD1F5, 0x6B2C, 0xD1F6, 0x6B2F, 0xD1F7, 0x6B2D,
+	0xD1F8, 0x6B31, 0xD1F9, 0x6B34, 0xD1FA, 0x6B6D, 0xD1FB, 0x8082,	0xD1FC, 0x6B88, 0xD1FD, 0x6BE6, 0xD1FE, 0x6BE4, 0xD240, 0x6BE8,
+	0xD241, 0x6BE3, 0xD242, 0x6BE2, 0xD243, 0x6BE7, 0xD244, 0x6C25,	0xD245, 0x6D7A, 0xD246, 0x6D63, 0xD247, 0x6D64, 0xD248, 0x6D76,
+	0xD249, 0x6D0D, 0xD24A, 0x6D61, 0xD24B, 0x6D92, 0xD24C, 0x6D58,	0xD24D, 0x6D62, 0xD24E, 0x6D6D, 0xD24F, 0x6D6F, 0xD250, 0x6D91,
+	0xD251, 0x6D8D, 0xD252, 0x6DEF, 0xD253, 0x6D7F, 0xD254, 0x6D86,	0xD255, 0x6D5E, 0xD256, 0x6D67, 0xD257, 0x6D60, 0xD258, 0x6D97,
+	0xD259, 0x6D70, 0xD25A, 0x6D7C, 0xD25B, 0x6D5F, 0xD25C, 0x6D82,	0xD25D, 0x6D98, 0xD25E, 0x6D2F, 0xD25F, 0x6D68, 0xD260, 0x6D8B,
+	0xD261, 0x6D7E, 0xD262, 0x6D80, 0xD263, 0x6D84, 0xD264, 0x6D16,	0xD265, 0x6D83, 0xD266, 0x6D7B, 0xD267, 0x6D7D, 0xD268, 0x6D75,
+	0xD269, 0x6D90, 0xD26A, 0x70DC, 0xD26B, 0x70D3, 0xD26C, 0x70D1,	0xD26D, 0x70DD, 0xD26E, 0x70CB, 0xD26F, 0x7F39, 0xD270, 0x70E2,
+	0xD271, 0x70D7, 0xD272, 0x70D2, 0xD273, 0x70DE, 0xD274, 0x70E0,	0xD275, 0x70D4, 0xD276, 0x70CD, 0xD277, 0x70C5, 0xD278, 0x70C6,
+	0xD279, 0x70C7, 0xD27A, 0x70DA, 0xD27B, 0x70CE, 0xD27C, 0x70E1,	0xD27D, 0x7242, 0xD27E, 0x7278, 0xD2A1, 0x7277, 0xD2A2, 0x7276,
+	0xD2A3, 0x7300, 0xD2A4, 0x72FA, 0xD2A5, 0x72F4, 0xD2A6, 0x72FE,	0xD2A7, 0x72F6, 0xD2A8, 0x72F3, 0xD2A9, 0x72FB, 0xD2AA, 0x7301,
+	0xD2AB, 0x73D3, 0xD2AC, 0x73D9, 0xD2AD, 0x73E5, 0xD2AE, 0x73D6,	0xD2AF, 0x73BC, 0xD2B0, 0x73E7, 0xD2B1, 0x73E3, 0xD2B2, 0x73E9,
+	0xD2B3, 0x73DC, 0xD2B4, 0x73D2, 0xD2B5, 0x73DB, 0xD2B6, 0x73D4,	0xD2B7, 0x73DD, 0xD2B8, 0x73DA, 0xD2B9, 0x73D7, 0xD2BA, 0x73D8,
+	0xD2BB, 0x73E8, 0xD2BC, 0x74DE, 0xD2BD, 0x74DF, 0xD2BE, 0x74F4,	0xD2BF, 0x74F5, 0xD2C0, 0x7521, 0xD2C1, 0x755B, 0xD2C2, 0x755F,
+	0xD2C3, 0x75B0, 0xD2C4, 0x75C1, 0xD2C5, 0x75BB, 0xD2C6, 0x75C4,	0xD2C7, 0x75C0, 0xD2C8, 0x75BF, 0xD2C9, 0x75B6, 0xD2CA, 0x75BA,
+	0xD2CB, 0x768A, 0xD2CC, 0x76C9, 0xD2CD, 0x771D, 0xD2CE, 0x771B,	0xD2CF, 0x7710, 0xD2D0, 0x7713, 0xD2D1, 0x7712, 0xD2D2, 0x7723,
+	0xD2D3, 0x7711, 0xD2D4, 0x7715, 0xD2D5, 0x7719, 0xD2D6, 0x771A,	0xD2D7, 0x7722, 0xD2D8, 0x7727, 0xD2D9, 0x7823, 0xD2DA, 0x782C,
+	0xD2DB, 0x7822, 0xD2DC, 0x7835, 0xD2DD, 0x782F, 0xD2DE, 0x7828,	0xD2DF, 0x782E, 0xD2E0, 0x782B, 0xD2E1, 0x7821, 0xD2E2, 0x7829,
+	0xD2E3, 0x7833, 0xD2E4, 0x782A, 0xD2E5, 0x7831, 0xD2E6, 0x7954,	0xD2E7, 0x795B, 0xD2E8, 0x794F, 0xD2E9, 0x795C, 0xD2EA, 0x7953,
+	0xD2EB, 0x7952, 0xD2EC, 0x7951, 0xD2ED, 0x79EB, 0xD2EE, 0x79EC,	0xD2EF, 0x79E0, 0xD2F0, 0x79EE, 0xD2F1, 0x79ED, 0xD2F2, 0x79EA,
+	0xD2F3, 0x79DC, 0xD2F4, 0x79DE, 0xD2F5, 0x79DD, 0xD2F6, 0x7A86,	0xD2F7, 0x7A89, 0xD2F8, 0x7A85, 0xD2F9, 0x7A8B, 0xD2FA, 0x7A8C,
+	0xD2FB, 0x7A8A, 0xD2FC, 0x7A87, 0xD2FD, 0x7AD8, 0xD2FE, 0x7B10,	0xD340, 0x7B04, 0xD341, 0x7B13, 0xD342, 0x7B05, 0xD343, 0x7B0F,
+	0xD344, 0x7B08, 0xD345, 0x7B0A, 0xD346, 0x7B0E, 0xD347, 0x7B09,	0xD348, 0x7B12, 0xD349, 0x7C84, 0xD34A, 0x7C91, 0xD34B, 0x7C8A,
+	0xD34C, 0x7C8C, 0xD34D, 0x7C88, 0xD34E, 0x7C8D, 0xD34F, 0x7C85,	0xD350, 0x7D1E, 0xD351, 0x7D1D, 0xD352, 0x7D11, 0xD353, 0x7D0E,
+	0xD354, 0x7D18, 0xD355, 0x7D16, 0xD356, 0x7D13, 0xD357, 0x7D1F,	0xD358, 0x7D12, 0xD359, 0x7D0F, 0xD35A, 0x7D0C, 0xD35B, 0x7F5C,
+	0xD35C, 0x7F61, 0xD35D, 0x7F5E, 0xD35E, 0x7F60, 0xD35F, 0x7F5D,	0xD360, 0x7F5B, 0xD361, 0x7F96, 0xD362, 0x7F92, 0xD363, 0x7FC3,
+	0xD364, 0x7FC2, 0xD365, 0x7FC0, 0xD366, 0x8016, 0xD367, 0x803E,	0xD368, 0x8039, 0xD369, 0x80FA, 0xD36A, 0x80F2, 0xD36B, 0x80F9,
+	0xD36C, 0x80F5, 0xD36D, 0x8101, 0xD36E, 0x80FB, 0xD36F, 0x8100,	0xD370, 0x8201, 0xD371, 0x822F, 0xD372, 0x8225, 0xD373, 0x8333,
+	0xD374, 0x832D, 0xD375, 0x8344, 0xD376, 0x8319, 0xD377, 0x8351,	0xD378, 0x8325, 0xD379, 0x8356, 0xD37A, 0x833F, 0xD37B, 0x8341,
+	0xD37C, 0x8326, 0xD37D, 0x831C, 0xD37E, 0x8322, 0xD3A1, 0x8342,	0xD3A2, 0x834E, 0xD3A3, 0x831B, 0xD3A4, 0x832A, 0xD3A5, 0x8308,
+	0xD3A6, 0x833C, 0xD3A7, 0x834D, 0xD3A8, 0x8316, 0xD3A9, 0x8324,	0xD3AA, 0x8320, 0xD3AB, 0x8337, 0xD3AC, 0x832F, 0xD3AD, 0x8329,
+	0xD3AE, 0x8347, 0xD3AF, 0x8345, 0xD3B0, 0x834C, 0xD3B1, 0x8353,	0xD3B2, 0x831E, 0xD3B3, 0x832C, 0xD3B4, 0x834B, 0xD3B5, 0x8327,
+	0xD3B6, 0x8348, 0xD3B7, 0x8653, 0xD3B8, 0x8652, 0xD3B9, 0x86A2,	0xD3BA, 0x86A8, 0xD3BB, 0x8696, 0xD3BC, 0x868D, 0xD3BD, 0x8691,
+	0xD3BE, 0x869E, 0xD3BF, 0x8687, 0xD3C0, 0x8697, 0xD3C1, 0x8686,	0xD3C2, 0x868B, 0xD3C3, 0x869A, 0xD3C4, 0x8685, 0xD3C5, 0x86A5,
+	0xD3C6, 0x8699, 0xD3C7, 0x86A1, 0xD3C8, 0x86A7, 0xD3C9, 0x8695,	0xD3CA, 0x8698, 0xD3CB, 0x868E, 0xD3CC, 0x869D, 0xD3CD, 0x8690,
+	0xD3CE, 0x8694, 0xD3CF, 0x8843, 0xD3D0, 0x8844, 0xD3D1, 0x886D,	0xD3D2, 0x8875, 0xD3D3, 0x8876, 0xD3D4, 0x8872, 0xD3D5, 0x8880,
+	0xD3D6, 0x8871, 0xD3D7, 0x887F, 0xD3D8, 0x886F, 0xD3D9, 0x8883,	0xD3DA, 0x887E, 0xD3DB, 0x8874, 0xD3DC, 0x887C, 0xD3DD, 0x8A12,
+	0xD3DE, 0x8C47, 0xD3DF, 0x8C57, 0xD3E0, 0x8C7B, 0xD3E1, 0x8CA4,	0xD3E2, 0x8CA3, 0xD3E3, 0x8D76, 0xD3E4, 0x8D78, 0xD3E5, 0x8DB5,
+	0xD3E6, 0x8DB7, 0xD3E7, 0x8DB6, 0xD3E8, 0x8ED1, 0xD3E9, 0x8ED3,	0xD3EA, 0x8FFE, 0xD3EB, 0x8FF5, 0xD3EC, 0x9002, 0xD3ED, 0x8FFF,
+	0xD3EE, 0x8FFB, 0xD3EF, 0x9004, 0xD3F0, 0x8FFC, 0xD3F1, 0x8FF6,	0xD3F2, 0x90D6, 0xD3F3, 0x90E0, 0xD3F4, 0x90D9, 0xD3F5, 0x90DA,
+	0xD3F6, 0x90E3, 0xD3F7, 0x90DF, 0xD3F8, 0x90E5, 0xD3F9, 0x90D8,	0xD3FA, 0x90DB, 0xD3FB, 0x90D7, 0xD3FC, 0x90DC, 0xD3FD, 0x90E4,
+	0xD3FE, 0x9150, 0xD440, 0x914E, 0xD441, 0x914F, 0xD442, 0x91D5,	0xD443, 0x91E2, 0xD444, 0x91DA, 0xD445, 0x965C, 0xD446, 0x965F,
+	0xD447, 0x96BC, 0xD448, 0x98E3, 0xD449, 0x9ADF, 0xD44A, 0x9B2F,	0xD44B, 0x4E7F, 0xD44C, 0x5070, 0xD44D, 0x506A, 0xD44E, 0x5061,
+	0xD44F, 0x505E, 0xD450, 0x5060, 0xD451, 0x5053, 0xD452, 0x504B,	0xD453, 0x505D, 0xD454, 0x5072, 0xD455, 0x5048, 0xD456, 0x504D,
+	0xD457, 0x5041, 0xD458, 0x505B, 0xD459, 0x504A, 0xD45A, 0x5062,	0xD45B, 0x5015, 0xD45C, 0x5045, 0xD45D, 0x505F, 0xD45E, 0x5069,
+	0xD45F, 0x506B, 0xD460, 0x5063, 0xD461, 0x5064, 0xD462, 0x5046,	0xD463, 0x5040, 0xD464, 0x506E, 0xD465, 0x5073, 0xD466, 0x5057,
+	0xD467, 0x5051, 0xD468, 0x51D0, 0xD469, 0x526B, 0xD46A, 0x526D,	0xD46B, 0x526C, 0xD46C, 0x526E, 0xD46D, 0x52D6, 0xD46E, 0x52D3,
+	0xD46F, 0x532D, 0xD470, 0x539C, 0xD471, 0x5575, 0xD472, 0x5576,	0xD473, 0x553C, 0xD474, 0x554D, 0xD475, 0x5550, 0xD476, 0x5534,
+	0xD477, 0x552A, 0xD478, 0x5551, 0xD479, 0x5562, 0xD47A, 0x5536,	0xD47B, 0x5535, 0xD47C, 0x5530, 0xD47D, 0x5552, 0xD47E, 0x5545,
+	0xD4A1, 0x550C, 0xD4A2, 0x5532, 0xD4A3, 0x5565, 0xD4A4, 0x554E,	0xD4A5, 0x5539, 0xD4A6, 0x5548, 0xD4A7, 0x552D, 0xD4A8, 0x553B,
+	0xD4A9, 0x5540, 0xD4AA, 0x554B, 0xD4AB, 0x570A, 0xD4AC, 0x5707,	0xD4AD, 0x57FB, 0xD4AE, 0x5814, 0xD4AF, 0x57E2, 0xD4B0, 0x57F6,
+	0xD4B1, 0x57DC, 0xD4B2, 0x57F4, 0xD4B3, 0x5800, 0xD4B4, 0x57ED,	0xD4B5, 0x57FD, 0xD4B6, 0x5808, 0xD4B7, 0x57F8, 0xD4B8, 0x580B,
+	0xD4B9, 0x57F3, 0xD4BA, 0x57CF, 0xD4BB, 0x5807, 0xD4BC, 0x57EE,	0xD4BD, 0x57E3, 0xD4BE, 0x57F2, 0xD4BF, 0x57E5, 0xD4C0, 0x57EC,
+	0xD4C1, 0x57E1, 0xD4C2, 0x580E, 0xD4C3, 0x57FC, 0xD4C4, 0x5810,	0xD4C5, 0x57E7, 0xD4C6, 0x5801, 0xD4C7, 0x580C, 0xD4C8, 0x57F1,
+	0xD4C9, 0x57E9, 0xD4CA, 0x57F0, 0xD4CB, 0x580D, 0xD4CC, 0x5804,	0xD4CD, 0x595C, 0xD4CE, 0x5A60, 0xD4CF, 0x5A58, 0xD4D0, 0x5A55,
+	0xD4D1, 0x5A67, 0xD4D2, 0x5A5E, 0xD4D3, 0x5A38, 0xD4D4, 0x5A35,	0xD4D5, 0x5A6D, 0xD4D6, 0x5A50, 0xD4D7, 0x5A5F, 0xD4D8, 0x5A65,
+	0xD4D9, 0x5A6C, 0xD4DA, 0x5A53, 0xD4DB, 0x5A64, 0xD4DC, 0x5A57,	0xD4DD, 0x5A43, 0xD4DE, 0x5A5D, 0xD4DF, 0x5A52, 0xD4E0, 0x5A44,
+	0xD4E1, 0x5A5B, 0xD4E2, 0x5A48, 0xD4E3, 0x5A8E, 0xD4E4, 0x5A3E,	0xD4E5, 0x5A4D, 0xD4E6, 0x5A39, 0xD4E7, 0x5A4C, 0xD4E8, 0x5A70,
+	0xD4E9, 0x5A69, 0xD4EA, 0x5A47, 0xD4EB, 0x5A51, 0xD4EC, 0x5A56,	0xD4ED, 0x5A42, 0xD4EE, 0x5A5C, 0xD4EF, 0x5B72, 0xD4F0, 0x5B6E,
+	0xD4F1, 0x5BC1, 0xD4F2, 0x5BC0, 0xD4F3, 0x5C59, 0xD4F4, 0x5D1E,	0xD4F5, 0x5D0B, 0xD4F6, 0x5D1D, 0xD4F7, 0x5D1A, 0xD4F8, 0x5D20,
+	0xD4F9, 0x5D0C, 0xD4FA, 0x5D28, 0xD4FB, 0x5D0D, 0xD4FC, 0x5D26,	0xD4FD, 0x5D25, 0xD4FE, 0x5D0F, 0xD540, 0x5D30, 0xD541, 0x5D12,
+	0xD542, 0x5D23, 0xD543, 0x5D1F, 0xD544, 0x5D2E, 0xD545, 0x5E3E,	0xD546, 0x5E34, 0xD547, 0x5EB1, 0xD548, 0x5EB4, 0xD549, 0x5EB9,
+	0xD54A, 0x5EB2, 0xD54B, 0x5EB3, 0xD54C, 0x5F36, 0xD54D, 0x5F38,	0xD54E, 0x5F9B, 0xD54F, 0x5F96, 0xD550, 0x5F9F, 0xD551, 0x608A,
+	0xD552, 0x6090, 0xD553, 0x6086, 0xD554, 0x60BE, 0xD555, 0x60B0,	0xD556, 0x60BA, 0xD557, 0x60D3, 0xD558, 0x60D4, 0xD559, 0x60CF,
+	0xD55A, 0x60E4, 0xD55B, 0x60D9, 0xD55C, 0x60DD, 0xD55D, 0x60C8,	0xD55E, 0x60B1, 0xD55F, 0x60DB, 0xD560, 0x60B7, 0xD561, 0x60CA,
+	0xD562, 0x60BF, 0xD563, 0x60C3, 0xD564, 0x60CD, 0xD565, 0x60C0,	0xD566, 0x6332, 0xD567, 0x6365, 0xD568, 0x638A, 0xD569, 0x6382,
+	0xD56A, 0x637D, 0xD56B, 0x63BD, 0xD56C, 0x639E, 0xD56D, 0x63AD,	0xD56E, 0x639D, 0xD56F, 0x6397, 0xD570, 0x63AB, 0xD571, 0x638E,
+	0xD572, 0x636F, 0xD573, 0x6387, 0xD574, 0x6390, 0xD575, 0x636E,	0xD576, 0x63AF, 0xD577, 0x6375, 0xD578, 0x639C, 0xD579, 0x636D,
+	0xD57A, 0x63AE, 0xD57B, 0x637C, 0xD57C, 0x63A4, 0xD57D, 0x633B,	0xD57E, 0x639F, 0xD5A1, 0x6378, 0xD5A2, 0x6385, 0xD5A3, 0x6381,
+	0xD5A4, 0x6391, 0xD5A5, 0x638D, 0xD5A6, 0x6370, 0xD5A7, 0x6553,	0xD5A8, 0x65CD, 0xD5A9, 0x6665, 0xD5AA, 0x6661, 0xD5AB, 0x665B,
+	0xD5AC, 0x6659, 0xD5AD, 0x665C, 0xD5AE, 0x6662, 0xD5AF, 0x6718,	0xD5B0, 0x6879, 0xD5B1, 0x6887, 0xD5B2, 0x6890, 0xD5B3, 0x689C,
+	0xD5B4, 0x686D, 0xD5B5, 0x686E, 0xD5B6, 0x68AE, 0xD5B7, 0x68AB,	0xD5B8, 0x6956, 0xD5B9, 0x686F, 0xD5BA, 0x68A3, 0xD5BB, 0x68AC,
+	0xD5BC, 0x68A9, 0xD5BD, 0x6875, 0xD5BE, 0x6874, 0xD5BF, 0x68B2,	0xD5C0, 0x688F, 0xD5C1, 0x6877, 0xD5C2, 0x6892, 0xD5C3, 0x687C,
+	0xD5C4, 0x686B, 0xD5C5, 0x6872, 0xD5C6, 0x68AA, 0xD5C7, 0x6880,	0xD5C8, 0x6871, 0xD5C9, 0x687E, 0xD5CA, 0x689B, 0xD5CB, 0x6896,
+	0xD5CC, 0x688B, 0xD5CD, 0x68A0, 0xD5CE, 0x6889, 0xD5CF, 0x68A4,	0xD5D0, 0x6878, 0xD5D1, 0x687B, 0xD5D2, 0x6891, 0xD5D3, 0x688C,
+	0xD5D4, 0x688A, 0xD5D5, 0x687D, 0xD5D6, 0x6B36, 0xD5D7, 0x6B33,	0xD5D8, 0x6B37, 0xD5D9, 0x6B38, 0xD5DA, 0x6B91, 0xD5DB, 0x6B8F,
+	0xD5DC, 0x6B8D, 0xD5DD, 0x6B8E, 0xD5DE, 0x6B8C, 0xD5DF, 0x6C2A,	0xD5E0, 0x6DC0, 0xD5E1, 0x6DAB, 0xD5E2, 0x6DB4, 0xD5E3, 0x6DB3,
+	0xD5E4, 0x6E74, 0xD5E5, 0x6DAC, 0xD5E6, 0x6DE9, 0xD5E7, 0x6DE2,	0xD5E8, 0x6DB7, 0xD5E9, 0x6DF6, 0xD5EA, 0x6DD4, 0xD5EB, 0x6E00,
+	0xD5EC, 0x6DC8, 0xD5ED, 0x6DE0, 0xD5EE, 0x6DDF, 0xD5EF, 0x6DD6,	0xD5F0, 0x6DBE, 0xD5F1, 0x6DE5, 0xD5F2, 0x6DDC, 0xD5F3, 0x6DDD,
+	0xD5F4, 0x6DDB, 0xD5F5, 0x6DF4, 0xD5F6, 0x6DCA, 0xD5F7, 0x6DBD,	0xD5F8, 0x6DED, 0xD5F9, 0x6DF0, 0xD5FA, 0x6DBA, 0xD5FB, 0x6DD5,
+	0xD5FC, 0x6DC2, 0xD5FD, 0x6DCF, 0xD5FE, 0x6DC9, 0xD640, 0x6DD0,	0xD641, 0x6DF2, 0xD642, 0x6DD3, 0xD643, 0x6DFD, 0xD644, 0x6DD7,
+	0xD645, 0x6DCD, 0xD646, 0x6DE3, 0xD647, 0x6DBB, 0xD648, 0x70FA,	0xD649, 0x710D, 0xD64A, 0x70F7, 0xD64B, 0x7117, 0xD64C, 0x70F4,
+	0xD64D, 0x710C, 0xD64E, 0x70F0, 0xD64F, 0x7104, 0xD650, 0x70F3,	0xD651, 0x7110, 0xD652, 0x70FC, 0xD653, 0x70FF, 0xD654, 0x7106,
+	0xD655, 0x7113, 0xD656, 0x7100, 0xD657, 0x70F8, 0xD658, 0x70F6,	0xD659, 0x710B, 0xD65A, 0x7102, 0xD65B, 0x710E, 0xD65C, 0x727E,
+	0xD65D, 0x727B, 0xD65E, 0x727C, 0xD65F, 0x727F, 0xD660, 0x731D,	0xD661, 0x7317, 0xD662, 0x7307, 0xD663, 0x7311, 0xD664, 0x7318,
+	0xD665, 0x730A, 0xD666, 0x7308, 0xD667, 0x72FF, 0xD668, 0x730F,	0xD669, 0x731E, 0xD66A, 0x7388, 0xD66B, 0x73F6, 0xD66C, 0x73F8,
+	0xD66D, 0x73F5, 0xD66E, 0x7404, 0xD66F, 0x7401, 0xD670, 0x73FD,	0xD671, 0x7407, 0xD672, 0x7400, 0xD673, 0x73FA, 0xD674, 0x73FC,
+	0xD675, 0x73FF, 0xD676, 0x740C, 0xD677, 0x740B, 0xD678, 0x73F4,	0xD679, 0x7408, 0xD67A, 0x7564, 0xD67B, 0x7563, 0xD67C, 0x75CE,
+	0xD67D, 0x75D2, 0xD67E, 0x75CF, 0xD6A1, 0x75CB, 0xD6A2, 0x75CC,	0xD6A3, 0x75D1, 0xD6A4, 0x75D0, 0xD6A5, 0x768F, 0xD6A6, 0x7689,
+	0xD6A7, 0x76D3, 0xD6A8, 0x7739, 0xD6A9, 0x772F, 0xD6AA, 0x772D,	0xD6AB, 0x7731, 0xD6AC, 0x7732, 0xD6AD, 0x7734, 0xD6AE, 0x7733,
+	0xD6AF, 0x773D, 0xD6B0, 0x7725, 0xD6B1, 0x773B, 0xD6B2, 0x7735,	0xD6B3, 0x7848, 0xD6B4, 0x7852, 0xD6B5, 0x7849, 0xD6B6, 0x784D,
+	0xD6B7, 0x784A, 0xD6B8, 0x784C, 0xD6B9, 0x7826, 0xD6BA, 0x7845,	0xD6BB, 0x7850, 0xD6BC, 0x7964, 0xD6BD, 0x7967, 0xD6BE, 0x7969,
+	0xD6BF, 0x796A, 0xD6C0, 0x7963, 0xD6C1, 0x796B, 0xD6C2, 0x7961,	0xD6C3, 0x79BB, 0xD6C4, 0x79FA, 0xD6C5, 0x79F8, 0xD6C6, 0x79F6,
+	0xD6C7, 0x79F7, 0xD6C8, 0x7A8F, 0xD6C9, 0x7A94, 0xD6CA, 0x7A90,	0xD6CB, 0x7B35, 0xD6CC, 0x7B47, 0xD6CD, 0x7B34, 0xD6CE, 0x7B25,
+	0xD6CF, 0x7B30, 0xD6D0, 0x7B22, 0xD6D1, 0x7B24, 0xD6D2, 0x7B33,	0xD6D3, 0x7B18, 0xD6D4, 0x7B2A, 0xD6D5, 0x7B1D, 0xD6D6, 0x7B31,
+	0xD6D7, 0x7B2B, 0xD6D8, 0x7B2D, 0xD6D9, 0x7B2F, 0xD6DA, 0x7B32,	0xD6DB, 0x7B38, 0xD6DC, 0x7B1A, 0xD6DD, 0x7B23, 0xD6DE, 0x7C94,
+	0xD6DF, 0x7C98, 0xD6E0, 0x7C96, 0xD6E1, 0x7CA3, 0xD6E2, 0x7D35,	0xD6E3, 0x7D3D, 0xD6E4, 0x7D38, 0xD6E5, 0x7D36, 0xD6E6, 0x7D3A,
+	0xD6E7, 0x7D45, 0xD6E8, 0x7D2C, 0xD6E9, 0x7D29, 0xD6EA, 0x7D41,	0xD6EB, 0x7D47, 0xD6EC, 0x7D3E, 0xD6ED, 0x7D3F, 0xD6EE, 0x7D4A,
+	0xD6EF, 0x7D3B, 0xD6F0, 0x7D28, 0xD6F1, 0x7F63, 0xD6F2, 0x7F95,	0xD6F3, 0x7F9C, 0xD6F4, 0x7F9D, 0xD6F5, 0x7F9B, 0xD6F6, 0x7FCA,
+	0xD6F7, 0x7FCB, 0xD6F8, 0x7FCD, 0xD6F9, 0x7FD0, 0xD6FA, 0x7FD1,	0xD6FB, 0x7FC7, 0xD6FC, 0x7FCF, 0xD6FD, 0x7FC9, 0xD6FE, 0x801F,
+	0xD740, 0x801E, 0xD741, 0x801B, 0xD742, 0x8047, 0xD743, 0x8043,	0xD744, 0x8048, 0xD745, 0x8118, 0xD746, 0x8125, 0xD747, 0x8119,
+	0xD748, 0x811B, 0xD749, 0x812D, 0xD74A, 0x811F, 0xD74B, 0x812C,	0xD74C, 0x811E, 0xD74D, 0x8121, 0xD74E, 0x8115, 0xD74F, 0x8127,
+	0xD750, 0x811D, 0xD751, 0x8122, 0xD752, 0x8211, 0xD753, 0x8238,	0xD754, 0x8233, 0xD755, 0x823A, 0xD756, 0x8234, 0xD757, 0x8232,
+	0xD758, 0x8274, 0xD759, 0x8390, 0xD75A, 0x83A3, 0xD75B, 0x83A8,	0xD75C, 0x838D, 0xD75D, 0x837A, 0xD75E, 0x8373, 0xD75F, 0x83A4,
+	0xD760, 0x8374, 0xD761, 0x838F, 0xD762, 0x8381, 0xD763, 0x8395,	0xD764, 0x8399, 0xD765, 0x8375, 0xD766, 0x8394, 0xD767, 0x83A9,
+	0xD768, 0x837D, 0xD769, 0x8383, 0xD76A, 0x838C, 0xD76B, 0x839D,	0xD76C, 0x839B, 0xD76D, 0x83AA, 0xD76E, 0x838B, 0xD76F, 0x837E,
+	0xD770, 0x83A5, 0xD771, 0x83AF, 0xD772, 0x8388, 0xD773, 0x8397,	0xD774, 0x83B0, 0xD775, 0x837F, 0xD776, 0x83A6, 0xD777, 0x8387,
+	0xD778, 0x83AE, 0xD779, 0x8376, 0xD77A, 0x839A, 0xD77B, 0x8659,	0xD77C, 0x8656, 0xD77D, 0x86BF, 0xD77E, 0x86B7, 0xD7A1, 0x86C2,
+	0xD7A2, 0x86C1, 0xD7A3, 0x86C5, 0xD7A4, 0x86BA, 0xD7A5, 0x86B0,	0xD7A6, 0x86C8, 0xD7A7, 0x86B9, 0xD7A8, 0x86B3, 0xD7A9, 0x86B8,
+	0xD7AA, 0x86CC, 0xD7AB, 0x86B4, 0xD7AC, 0x86BB, 0xD7AD, 0x86BC,	0xD7AE, 0x86C3, 0xD7AF, 0x86BD, 0xD7B0, 0x86BE, 0xD7B1, 0x8852,
+	0xD7B2, 0x8889, 0xD7B3, 0x8895, 0xD7B4, 0x88A8, 0xD7B5, 0x88A2,	0xD7B6, 0x88AA, 0xD7B7, 0x889A, 0xD7B8, 0x8891, 0xD7B9, 0x88A1,
+	0xD7BA, 0x889F, 0xD7BB, 0x8898, 0xD7BC, 0x88A7, 0xD7BD, 0x8899,	0xD7BE, 0x889B, 0xD7BF, 0x8897, 0xD7C0, 0x88A4, 0xD7C1, 0x88AC,
+	0xD7C2, 0x888C, 0xD7C3, 0x8893, 0xD7C4, 0x888E, 0xD7C5, 0x8982,	0xD7C6, 0x89D6, 0xD7C7, 0x89D9, 0xD7C8, 0x89D5, 0xD7C9, 0x8A30,
+	0xD7CA, 0x8A27, 0xD7CB, 0x8A2C, 0xD7CC, 0x8A1E, 0xD7CD, 0x8C39,	0xD7CE, 0x8C3B, 0xD7CF, 0x8C5C, 0xD7D0, 0x8C5D, 0xD7D1, 0x8C7D,
+	0xD7D2, 0x8CA5, 0xD7D3, 0x8D7D, 0xD7D4, 0x8D7B, 0xD7D5, 0x8D79,	0xD7D6, 0x8DBC, 0xD7D7, 0x8DC2, 0xD7D8, 0x8DB9, 0xD7D9, 0x8DBF,
+	0xD7DA, 0x8DC1, 0xD7DB, 0x8ED8, 0xD7DC, 0x8EDE, 0xD7DD, 0x8EDD,	0xD7DE, 0x8EDC, 0xD7DF, 0x8ED7, 0xD7E0, 0x8EE0, 0xD7E1, 0x8EE1,
+	0xD7E2, 0x9024, 0xD7E3, 0x900B, 0xD7E4, 0x9011, 0xD7E5, 0x901C,	0xD7E6, 0x900C, 0xD7E7, 0x9021, 0xD7E8, 0x90EF, 0xD7E9, 0x90EA,
+	0xD7EA, 0x90F0, 0xD7EB, 0x90F4, 0xD7EC, 0x90F2, 0xD7ED, 0x90F3,	0xD7EE, 0x90D4, 0xD7EF, 0x90EB, 0xD7F0, 0x90EC, 0xD7F1, 0x90E9,
+	0xD7F2, 0x9156, 0xD7F3, 0x9158, 0xD7F4, 0x915A, 0xD7F5, 0x9153,	0xD7F6, 0x9155, 0xD7F7, 0x91EC, 0xD7F8, 0x91F4, 0xD7F9, 0x91F1,
+	0xD7FA, 0x91F3, 0xD7FB, 0x91F8, 0xD7FC, 0x91E4, 0xD7FD, 0x91F9,	0xD7FE, 0x91EA, 0xD840, 0x91EB, 0xD841, 0x91F7, 0xD842, 0x91E8,
+	0xD843, 0x91EE, 0xD844, 0x957A, 0xD845, 0x9586, 0xD846, 0x9588,	0xD847, 0x967C, 0xD848, 0x966D, 0xD849, 0x966B, 0xD84A, 0x9671,
+	0xD84B, 0x966F, 0xD84C, 0x96BF, 0xD84D, 0x976A, 0xD84E, 0x9804,	0xD84F, 0x98E5, 0xD850, 0x9997, 0xD851, 0x509B, 0xD852, 0x5095,
+	0xD853, 0x5094, 0xD854, 0x509E, 0xD855, 0x508B, 0xD856, 0x50A3,	0xD857, 0x5083, 0xD858, 0x508C, 0xD859, 0x508E, 0xD85A, 0x509D,
+	0xD85B, 0x5068, 0xD85C, 0x509C, 0xD85D, 0x5092, 0xD85E, 0x5082,	0xD85F, 0x5087, 0xD860, 0x515F, 0xD861, 0x51D4, 0xD862, 0x5312,
+	0xD863, 0x5311, 0xD864, 0x53A4, 0xD865, 0x53A7, 0xD866, 0x5591,	0xD867, 0x55A8, 0xD868, 0x55A5, 0xD869, 0x55AD, 0xD86A, 0x5577,
+	0xD86B, 0x5645, 0xD86C, 0x55A2, 0xD86D, 0x5593, 0xD86E, 0x5588,	0xD86F, 0x558F, 0xD870, 0x55B5, 0xD871, 0x5581, 0xD872, 0x55A3,
+	0xD873, 0x5592, 0xD874, 0x55A4, 0xD875, 0x557D, 0xD876, 0x558C,	0xD877, 0x55A6, 0xD878, 0x557F, 0xD879, 0x5595, 0xD87A, 0x55A1,
+	0xD87B, 0x558E, 0xD87C, 0x570C, 0xD87D, 0x5829, 0xD87E, 0x5837,	0xD8A1, 0x5819, 0xD8A2, 0x581E, 0xD8A3, 0x5827, 0xD8A4, 0x5823,
+	0xD8A5, 0x5828, 0xD8A6, 0x57F5, 0xD8A7, 0x5848, 0xD8A8, 0x5825,	0xD8A9, 0x581C, 0xD8AA, 0x581B, 0xD8AB, 0x5833, 0xD8AC, 0x583F,
+	0xD8AD, 0x5836, 0xD8AE, 0x582E, 0xD8AF, 0x5839, 0xD8B0, 0x5838,	0xD8B1, 0x582D, 0xD8B2, 0x582C, 0xD8B3, 0x583B, 0xD8B4, 0x5961,
+	0xD8B5, 0x5AAF, 0xD8B6, 0x5A94, 0xD8B7, 0x5A9F, 0xD8B8, 0x5A7A,	0xD8B9, 0x5AA2, 0xD8BA, 0x5A9E, 0xD8BB, 0x5A78, 0xD8BC, 0x5AA6,
+	0xD8BD, 0x5A7C, 0xD8BE, 0x5AA5, 0xD8BF, 0x5AAC, 0xD8C0, 0x5A95,	0xD8C1, 0x5AAE, 0xD8C2, 0x5A37, 0xD8C3, 0x5A84, 0xD8C4, 0x5A8A,
+	0xD8C5, 0x5A97, 0xD8C6, 0x5A83, 0xD8C7, 0x5A8B, 0xD8C8, 0x5AA9,	0xD8C9, 0x5A7B, 0xD8CA, 0x5A7D, 0xD8CB, 0x5A8C, 0xD8CC, 0x5A9C,
+	0xD8CD, 0x5A8F, 0xD8CE, 0x5A93, 0xD8CF, 0x5A9D, 0xD8D0, 0x5BEA,	0xD8D1, 0x5BCD, 0xD8D2, 0x5BCB, 0xD8D3, 0x5BD4, 0xD8D4, 0x5BD1,
+	0xD8D5, 0x5BCA, 0xD8D6, 0x5BCE, 0xD8D7, 0x5C0C, 0xD8D8, 0x5C30,	0xD8D9, 0x5D37, 0xD8DA, 0x5D43, 0xD8DB, 0x5D6B, 0xD8DC, 0x5D41,
+	0xD8DD, 0x5D4B, 0xD8DE, 0x5D3F, 0xD8DF, 0x5D35, 0xD8E0, 0x5D51,	0xD8E1, 0x5D4E, 0xD8E2, 0x5D55, 0xD8E3, 0x5D33, 0xD8E4, 0x5D3A,
+	0xD8E5, 0x5D52, 0xD8E6, 0x5D3D, 0xD8E7, 0x5D31, 0xD8E8, 0x5D59,	0xD8E9, 0x5D42, 0xD8EA, 0x5D39, 0xD8EB, 0x5D49, 0xD8EC, 0x5D38,
+	0xD8ED, 0x5D3C, 0xD8EE, 0x5D32, 0xD8EF, 0x5D36, 0xD8F0, 0x5D40,	0xD8F1, 0x5D45, 0xD8F2, 0x5E44, 0xD8F3, 0x5E41, 0xD8F4, 0x5F58,
+	0xD8F5, 0x5FA6, 0xD8F6, 0x5FA5, 0xD8F7, 0x5FAB, 0xD8F8, 0x60C9,	0xD8F9, 0x60B9, 0xD8FA, 0x60CC, 0xD8FB, 0x60E2, 0xD8FC, 0x60CE,
+	0xD8FD, 0x60C4, 0xD8FE, 0x6114, 0xD940, 0x60F2, 0xD941, 0x610A,	0xD942, 0x6116, 0xD943, 0x6105, 0xD944, 0x60F5, 0xD945, 0x6113,
+	0xD946, 0x60F8, 0xD947, 0x60FC, 0xD948, 0x60FE, 0xD949, 0x60C1,	0xD94A, 0x6103, 0xD94B, 0x6118, 0xD94C, 0x611D, 0xD94D, 0x6110,
+	0xD94E, 0x60FF, 0xD94F, 0x6104, 0xD950, 0x610B, 0xD951, 0x624A,	0xD952, 0x6394, 0xD953, 0x63B1, 0xD954, 0x63B0, 0xD955, 0x63CE,
+	0xD956, 0x63E5, 0xD957, 0x63E8, 0xD958, 0x63EF, 0xD959, 0x63C3,	0xD95A, 0x649D, 0xD95B, 0x63F3, 0xD95C, 0x63CA, 0xD95D, 0x63E0,
+	0xD95E, 0x63F6, 0xD95F, 0x63D5, 0xD960, 0x63F2, 0xD961, 0x63F5,	0xD962, 0x6461, 0xD963, 0x63DF, 0xD964, 0x63BE, 0xD965, 0x63DD,
+	0xD966, 0x63DC, 0xD967, 0x63C4, 0xD968, 0x63D8, 0xD969, 0x63D3,	0xD96A, 0x63C2, 0xD96B, 0x63C7, 0xD96C, 0x63CC, 0xD96D, 0x63CB,
+	0xD96E, 0x63C8, 0xD96F, 0x63F0, 0xD970, 0x63D7, 0xD971, 0x63D9,	0xD972, 0x6532, 0xD973, 0x6567, 0xD974, 0x656A, 0xD975, 0x6564,
+	0xD976, 0x655C, 0xD977, 0x6568, 0xD978, 0x6565, 0xD979, 0x658C,	0xD97A, 0x659D, 0xD97B, 0x659E, 0xD97C, 0x65AE, 0xD97D, 0x65D0,
+	0xD97E, 0x65D2, 0xD9A1, 0x667C, 0xD9A2, 0x666C, 0xD9A3, 0x667B,	0xD9A4, 0x6680, 0xD9A5, 0x6671, 0xD9A6, 0x6679, 0xD9A7, 0x666A,
+	0xD9A8, 0x6672, 0xD9A9, 0x6701, 0xD9AA, 0x690C, 0xD9AB, 0x68D3,	0xD9AC, 0x6904, 0xD9AD, 0x68DC, 0xD9AE, 0x692A, 0xD9AF, 0x68EC,
+	0xD9B0, 0x68EA, 0xD9B1, 0x68F1, 0xD9B2, 0x690F, 0xD9B3, 0x68D6,	0xD9B4, 0x68F7, 0xD9B5, 0x68EB, 0xD9B6, 0x68E4, 0xD9B7, 0x68F6,
+	0xD9B8, 0x6913, 0xD9B9, 0x6910, 0xD9BA, 0x68F3, 0xD9BB, 0x68E1,	0xD9BC, 0x6907, 0xD9BD, 0x68CC, 0xD9BE, 0x6908, 0xD9BF, 0x6970,
+	0xD9C0, 0x68B4, 0xD9C1, 0x6911, 0xD9C2, 0x68EF, 0xD9C3, 0x68C6,	0xD9C4, 0x6914, 0xD9C5, 0x68F8, 0xD9C6, 0x68D0, 0xD9C7, 0x68FD,
+	0xD9C8, 0x68FC, 0xD9C9, 0x68E8, 0xD9CA, 0x690B, 0xD9CB, 0x690A,	0xD9CC, 0x6917, 0xD9CD, 0x68CE, 0xD9CE, 0x68C8, 0xD9CF, 0x68DD,
+	0xD9D0, 0x68DE, 0xD9D1, 0x68E6, 0xD9D2, 0x68F4, 0xD9D3, 0x68D1,	0xD9D4, 0x6906, 0xD9D5, 0x68D4, 0xD9D6, 0x68E9, 0xD9D7, 0x6915,
+	0xD9D8, 0x6925, 0xD9D9, 0x68C7, 0xD9DA, 0x6B39, 0xD9DB, 0x6B3B,	0xD9DC, 0x6B3F, 0xD9DD, 0x6B3C, 0xD9DE, 0x6B94, 0xD9DF, 0x6B97,
+	0xD9E0, 0x6B99, 0xD9E1, 0x6B95, 0xD9E2, 0x6BBD, 0xD9E3, 0x6BF0,	0xD9E4, 0x6BF2, 0xD9E5, 0x6BF3, 0xD9E6, 0x6C30, 0xD9E7, 0x6DFC,
+	0xD9E8, 0x6E46, 0xD9E9, 0x6E47, 0xD9EA, 0x6E1F, 0xD9EB, 0x6E49,	0xD9EC, 0x6E88, 0xD9ED, 0x6E3C, 0xD9EE, 0x6E3D, 0xD9EF, 0x6E45,
+	0xD9F0, 0x6E62, 0xD9F1, 0x6E2B, 0xD9F2, 0x6E3F, 0xD9F3, 0x6E41,	0xD9F4, 0x6E5D, 0xD9F5, 0x6E73, 0xD9F6, 0x6E1C, 0xD9F7, 0x6E33,
+	0xD9F8, 0x6E4B, 0xD9F9, 0x6E40, 0xD9FA, 0x6E51, 0xD9FB, 0x6E3B,	0xD9FC, 0x6E03, 0xD9FD, 0x6E2E, 0xD9FE, 0x6E5E, 0xDA40, 0x6E68,
+	0xDA41, 0x6E5C, 0xDA42, 0x6E61, 0xDA43, 0x6E31, 0xDA44, 0x6E28,	0xDA45, 0x6E60, 0xDA46, 0x6E71, 0xDA47, 0x6E6B, 0xDA48, 0x6E39,
+	0xDA49, 0x6E22, 0xDA4A, 0x6E30, 0xDA4B, 0x6E53, 0xDA4C, 0x6E65,	0xDA4D, 0x6E27, 0xDA4E, 0x6E78, 0xDA4F, 0x6E64, 0xDA50, 0x6E77,
+	0xDA51, 0x6E55, 0xDA52, 0x6E79, 0xDA53, 0x6E52, 0xDA54, 0x6E66,	0xDA55, 0x6E35, 0xDA56, 0x6E36, 0xDA57, 0x6E5A, 0xDA58, 0x7120,
+	0xDA59, 0x711E, 0xDA5A, 0x712F, 0xDA5B, 0x70FB, 0xDA5C, 0x712E,	0xDA5D, 0x7131, 0xDA5E, 0x7123, 0xDA5F, 0x7125, 0xDA60, 0x7122,
+	0xDA61, 0x7132, 0xDA62, 0x711F, 0xDA63, 0x7128, 0xDA64, 0x713A,	0xDA65, 0x711B, 0xDA66, 0x724B, 0xDA67, 0x725A, 0xDA68, 0x7288,
+	0xDA69, 0x7289, 0xDA6A, 0x7286, 0xDA6B, 0x7285, 0xDA6C, 0x728B,	0xDA6D, 0x7312, 0xDA6E, 0x730B, 0xDA6F, 0x7330, 0xDA70, 0x7322,
+	0xDA71, 0x7331, 0xDA72, 0x7333, 0xDA73, 0x7327, 0xDA74, 0x7332,	0xDA75, 0x732D, 0xDA76, 0x7326, 0xDA77, 0x7323, 0xDA78, 0x7335,
+	0xDA79, 0x730C, 0xDA7A, 0x742E, 0xDA7B, 0x742C, 0xDA7C, 0x7430,	0xDA7D, 0x742B, 0xDA7E, 0x7416, 0xDAA1, 0x741A, 0xDAA2, 0x7421,
+	0xDAA3, 0x742D, 0xDAA4, 0x7431, 0xDAA5, 0x7424, 0xDAA6, 0x7423,	0xDAA7, 0x741D, 0xDAA8, 0x7429, 0xDAA9, 0x7420, 0xDAAA, 0x7432,
+	0xDAAB, 0x74FB, 0xDAAC, 0x752F, 0xDAAD, 0x756F, 0xDAAE, 0x756C,	0xDAAF, 0x75E7, 0xDAB0, 0x75DA, 0xDAB1, 0x75E1, 0xDAB2, 0x75E6,
+	0xDAB3, 0x75DD, 0xDAB4, 0x75DF, 0xDAB5, 0x75E4, 0xDAB6, 0x75D7,	0xDAB7, 0x7695, 0xDAB8, 0x7692, 0xDAB9, 0x76DA, 0xDABA, 0x7746,
+	0xDABB, 0x7747, 0xDABC, 0x7744, 0xDABD, 0x774D, 0xDABE, 0x7745,	0xDABF, 0x774A, 0xDAC0, 0x774E, 0xDAC1, 0x774B, 0xDAC2, 0x774C,
+	0xDAC3, 0x77DE, 0xDAC4, 0x77EC, 0xDAC5, 0x7860, 0xDAC6, 0x7864,	0xDAC7, 0x7865, 0xDAC8, 0x785C, 0xDAC9, 0x786D, 0xDACA, 0x7871,
+	0xDACB, 0x786A, 0xDACC, 0x786E, 0xDACD, 0x7870, 0xDACE, 0x7869,	0xDACF, 0x7868, 0xDAD0, 0x785E, 0xDAD1, 0x7862, 0xDAD2, 0x7974,
+	0xDAD3, 0x7973, 0xDAD4, 0x7972, 0xDAD5, 0x7970, 0xDAD6, 0x7A02,	0xDAD7, 0x7A0A, 0xDAD8, 0x7A03, 0xDAD9, 0x7A0C, 0xDADA, 0x7A04,
+	0xDADB, 0x7A99, 0xDADC, 0x7AE6, 0xDADD, 0x7AE4, 0xDADE, 0x7B4A,	0xDADF, 0x7B3B, 0xDAE0, 0x7B44, 0xDAE1, 0x7B48, 0xDAE2, 0x7B4C,
+	0xDAE3, 0x7B4E, 0xDAE4, 0x7B40, 0xDAE5, 0x7B58, 0xDAE6, 0x7B45,	0xDAE7, 0x7CA2, 0xDAE8, 0x7C9E, 0xDAE9, 0x7CA8, 0xDAEA, 0x7CA1,
+	0xDAEB, 0x7D58, 0xDAEC, 0x7D6F, 0xDAED, 0x7D63, 0xDAEE, 0x7D53,	0xDAEF, 0x7D56, 0xDAF0, 0x7D67, 0xDAF1, 0x7D6A, 0xDAF2, 0x7D4F,
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+	0xDF78, 0x8162, 0xDF79, 0x8172, 0xDF7A, 0x6721, 0xDF7B, 0x815E,	0xDF7C, 0x8176, 0xDF7D, 0x8167, 0xDF7E, 0x816F, 0xDFA1, 0x8144,
+	0xDFA2, 0x8161, 0xDFA3, 0x821D, 0xDFA4, 0x8249, 0xDFA5, 0x8244,	0xDFA6, 0x8240, 0xDFA7, 0x8242, 0xDFA8, 0x8245, 0xDFA9, 0x84F1,
+	0xDFAA, 0x843F, 0xDFAB, 0x8456, 0xDFAC, 0x8476, 0xDFAD, 0x8479,	0xDFAE, 0x848F, 0xDFAF, 0x848D, 0xDFB0, 0x8465, 0xDFB1, 0x8451,
+	0xDFB2, 0x8440, 0xDFB3, 0x8486, 0xDFB4, 0x8467, 0xDFB5, 0x8430,	0xDFB6, 0x844D, 0xDFB7, 0x847D, 0xDFB8, 0x845A, 0xDFB9, 0x8459,
+	0xDFBA, 0x8474, 0xDFBB, 0x8473, 0xDFBC, 0x845D, 0xDFBD, 0x8507,	0xDFBE, 0x845E, 0xDFBF, 0x8437, 0xDFC0, 0x843A, 0xDFC1, 0x8434,
+	0xDFC2, 0x847A, 0xDFC3, 0x8443, 0xDFC4, 0x8478, 0xDFC5, 0x8432,	0xDFC6, 0x8445, 0xDFC7, 0x8429, 0xDFC8, 0x83D9, 0xDFC9, 0x844B,
+	0xDFCA, 0x842F, 0xDFCB, 0x8442, 0xDFCC, 0x842D, 0xDFCD, 0x845F,	0xDFCE, 0x8470, 0xDFCF, 0x8439, 0xDFD0, 0x844E, 0xDFD1, 0x844C,
+	0xDFD2, 0x8452, 0xDFD3, 0x846F, 0xDFD4, 0x84C5, 0xDFD5, 0x848E,	0xDFD6, 0x843B, 0xDFD7, 0x8447, 0xDFD8, 0x8436, 0xDFD9, 0x8433,
+	0xDFDA, 0x8468, 0xDFDB, 0x847E, 0xDFDC, 0x8444, 0xDFDD, 0x842B,	0xDFDE, 0x8460, 0xDFDF, 0x8454, 0xDFE0, 0x846E, 0xDFE1, 0x8450,
+	0xDFE2, 0x870B, 0xDFE3, 0x8704, 0xDFE4, 0x86F7, 0xDFE5, 0x870C,	0xDFE6, 0x86FA, 0xDFE7, 0x86D6, 0xDFE8, 0x86F5, 0xDFE9, 0x874D,
+	0xDFEA, 0x86F8, 0xDFEB, 0x870E, 0xDFEC, 0x8709, 0xDFED, 0x8701,	0xDFEE, 0x86F6, 0xDFEF, 0x870D, 0xDFF0, 0x8705, 0xDFF1, 0x88D6,
+	0xDFF2, 0x88CB, 0xDFF3, 0x88CD, 0xDFF4, 0x88CE, 0xDFF5, 0x88DE,	0xDFF6, 0x88DB, 0xDFF7, 0x88DA, 0xDFF8, 0x88CC, 0xDFF9, 0x88D0,
+	0xDFFA, 0x8985, 0xDFFB, 0x899B, 0xDFFC, 0x89DF, 0xDFFD, 0x89E5,	0xDFFE, 0x89E4, 0xE040, 0x89E1, 0xE041, 0x89E0, 0xE042, 0x89E2,
+	0xE043, 0x89DC, 0xE044, 0x89E6, 0xE045, 0x8A76, 0xE046, 0x8A86,	0xE047, 0x8A7F, 0xE048, 0x8A61, 0xE049, 0x8A3F, 0xE04A, 0x8A77,
+	0xE04B, 0x8A82, 0xE04C, 0x8A84, 0xE04D, 0x8A75, 0xE04E, 0x8A83,	0xE04F, 0x8A81, 0xE050, 0x8A74, 0xE051, 0x8A7A, 0xE052, 0x8C3C,
+	0xE053, 0x8C4B, 0xE054, 0x8C4A, 0xE055, 0x8C65, 0xE056, 0x8C64,	0xE057, 0x8C66, 0xE058, 0x8C86, 0xE059, 0x8C84, 0xE05A, 0x8C85,
+	0xE05B, 0x8CCC, 0xE05C, 0x8D68, 0xE05D, 0x8D69, 0xE05E, 0x8D91,	0xE05F, 0x8D8C, 0xE060, 0x8D8E, 0xE061, 0x8D8F, 0xE062, 0x8D8D,
+	0xE063, 0x8D93, 0xE064, 0x8D94, 0xE065, 0x8D90, 0xE066, 0x8D92,	0xE067, 0x8DF0, 0xE068, 0x8DE0, 0xE069, 0x8DEC, 0xE06A, 0x8DF1,
+	0xE06B, 0x8DEE, 0xE06C, 0x8DD0, 0xE06D, 0x8DE9, 0xE06E, 0x8DE3,	0xE06F, 0x8DE2, 0xE070, 0x8DE7, 0xE071, 0x8DF2, 0xE072, 0x8DEB,
+	0xE073, 0x8DF4, 0xE074, 0x8F06, 0xE075, 0x8EFF, 0xE076, 0x8F01,	0xE077, 0x8F00, 0xE078, 0x8F05, 0xE079, 0x8F07, 0xE07A, 0x8F08,
+	0xE07B, 0x8F02, 0xE07C, 0x8F0B, 0xE07D, 0x9052, 0xE07E, 0x903F,	0xE0A1, 0x9044, 0xE0A2, 0x9049, 0xE0A3, 0x903D, 0xE0A4, 0x9110,
+	0xE0A5, 0x910D, 0xE0A6, 0x910F, 0xE0A7, 0x9111, 0xE0A8, 0x9116,	0xE0A9, 0x9114, 0xE0AA, 0x910B, 0xE0AB, 0x910E, 0xE0AC, 0x916E,
+	0xE0AD, 0x916F, 0xE0AE, 0x9248, 0xE0AF, 0x9252, 0xE0B0, 0x9230,	0xE0B1, 0x923A, 0xE0B2, 0x9266, 0xE0B3, 0x9233, 0xE0B4, 0x9265,
+	0xE0B5, 0x925E, 0xE0B6, 0x9283, 0xE0B7, 0x922E, 0xE0B8, 0x924A,	0xE0B9, 0x9246, 0xE0BA, 0x926D, 0xE0BB, 0x926C, 0xE0BC, 0x924F,
+	0xE0BD, 0x9260, 0xE0BE, 0x9267, 0xE0BF, 0x926F, 0xE0C0, 0x9236,	0xE0C1, 0x9261, 0xE0C2, 0x9270, 0xE0C3, 0x9231, 0xE0C4, 0x9254,
+	0xE0C5, 0x9263, 0xE0C6, 0x9250, 0xE0C7, 0x9272, 0xE0C8, 0x924E,	0xE0C9, 0x9253, 0xE0CA, 0x924C, 0xE0CB, 0x9256, 0xE0CC, 0x9232,
+	0xE0CD, 0x959F, 0xE0CE, 0x959C, 0xE0CF, 0x959E, 0xE0D0, 0x959B,	0xE0D1, 0x9692, 0xE0D2, 0x9693, 0xE0D3, 0x9691, 0xE0D4, 0x9697,
+	0xE0D5, 0x96CE, 0xE0D6, 0x96FA, 0xE0D7, 0x96FD, 0xE0D8, 0x96F8,	0xE0D9, 0x96F5, 0xE0DA, 0x9773, 0xE0DB, 0x9777, 0xE0DC, 0x9778,
+	0xE0DD, 0x9772, 0xE0DE, 0x980F, 0xE0DF, 0x980D, 0xE0E0, 0x980E,	0xE0E1, 0x98AC, 0xE0E2, 0x98F6, 0xE0E3, 0x98F9, 0xE0E4, 0x99AF,
+	0xE0E5, 0x99B2, 0xE0E6, 0x99B0, 0xE0E7, 0x99B5, 0xE0E8, 0x9AAD,	0xE0E9, 0x9AAB, 0xE0EA, 0x9B5B, 0xE0EB, 0x9CEA, 0xE0EC, 0x9CED,
+	0xE0ED, 0x9CE7, 0xE0EE, 0x9E80, 0xE0EF, 0x9EFD, 0xE0F0, 0x50E6,	0xE0F1, 0x50D4, 0xE0F2, 0x50D7, 0xE0F3, 0x50E8, 0xE0F4, 0x50F3,
+	0xE0F5, 0x50DB, 0xE0F6, 0x50EA, 0xE0F7, 0x50DD, 0xE0F8, 0x50E4,	0xE0F9, 0x50D3, 0xE0FA, 0x50EC, 0xE0FB, 0x50F0, 0xE0FC, 0x50EF,
+	0xE0FD, 0x50E3, 0xE0FE, 0x50E0, 0xE140, 0x51D8, 0xE141, 0x5280,	0xE142, 0x5281, 0xE143, 0x52E9, 0xE144, 0x52EB, 0xE145, 0x5330,
+	0xE146, 0x53AC, 0xE147, 0x5627, 0xE148, 0x5615, 0xE149, 0x560C,	0xE14A, 0x5612, 0xE14B, 0x55FC, 0xE14C, 0x560F, 0xE14D, 0x561C,
+	0xE14E, 0x5601, 0xE14F, 0x5613, 0xE150, 0x5602, 0xE151, 0x55FA,	0xE152, 0x561D, 0xE153, 0x5604, 0xE154, 0x55FF, 0xE155, 0x55F9,
+	0xE156, 0x5889, 0xE157, 0x587C, 0xE158, 0x5890, 0xE159, 0x5898,	0xE15A, 0x5886, 0xE15B, 0x5881, 0xE15C, 0x587F, 0xE15D, 0x5874,
+	0xE15E, 0x588B, 0xE15F, 0x587A, 0xE160, 0x5887, 0xE161, 0x5891,	0xE162, 0x588E, 0xE163, 0x5876, 0xE164, 0x5882, 0xE165, 0x5888,
+	0xE166, 0x587B, 0xE167, 0x5894, 0xE168, 0x588F, 0xE169, 0x58FE,	0xE16A, 0x596B, 0xE16B, 0x5ADC, 0xE16C, 0x5AEE, 0xE16D, 0x5AE5,
+	0xE16E, 0x5AD5, 0xE16F, 0x5AEA, 0xE170, 0x5ADA, 0xE171, 0x5AED,	0xE172, 0x5AEB, 0xE173, 0x5AF3, 0xE174, 0x5AE2, 0xE175, 0x5AE0,
+	0xE176, 0x5ADB, 0xE177, 0x5AEC, 0xE178, 0x5ADE, 0xE179, 0x5ADD,	0xE17A, 0x5AD9, 0xE17B, 0x5AE8, 0xE17C, 0x5ADF, 0xE17D, 0x5B77,
+	0xE17E, 0x5BE0, 0xE1A1, 0x5BE3, 0xE1A2, 0x5C63, 0xE1A3, 0x5D82,	0xE1A4, 0x5D80, 0xE1A5, 0x5D7D, 0xE1A6, 0x5D86, 0xE1A7, 0x5D7A,
+	0xE1A8, 0x5D81, 0xE1A9, 0x5D77, 0xE1AA, 0x5D8A, 0xE1AB, 0x5D89,	0xE1AC, 0x5D88, 0xE1AD, 0x5D7E, 0xE1AE, 0x5D7C, 0xE1AF, 0x5D8D,
+	0xE1B0, 0x5D79, 0xE1B1, 0x5D7F, 0xE1B2, 0x5E58, 0xE1B3, 0x5E59,	0xE1B4, 0x5E53, 0xE1B5, 0x5ED8, 0xE1B6, 0x5ED1, 0xE1B7, 0x5ED7,
+	0xE1B8, 0x5ECE, 0xE1B9, 0x5EDC, 0xE1BA, 0x5ED5, 0xE1BB, 0x5ED9,	0xE1BC, 0x5ED2, 0xE1BD, 0x5ED4, 0xE1BE, 0x5F44, 0xE1BF, 0x5F43,
+	0xE1C0, 0x5F6F, 0xE1C1, 0x5FB6, 0xE1C2, 0x612C, 0xE1C3, 0x6128,	0xE1C4, 0x6141, 0xE1C5, 0x615E, 0xE1C6, 0x6171, 0xE1C7, 0x6173,
+	0xE1C8, 0x6152, 0xE1C9, 0x6153, 0xE1CA, 0x6172, 0xE1CB, 0x616C,	0xE1CC, 0x6180, 0xE1CD, 0x6174, 0xE1CE, 0x6154, 0xE1CF, 0x617A,
+	0xE1D0, 0x615B, 0xE1D1, 0x6165, 0xE1D2, 0x613B, 0xE1D3, 0x616A,	0xE1D4, 0x6161, 0xE1D5, 0x6156, 0xE1D6, 0x6229, 0xE1D7, 0x6227,
+	0xE1D8, 0x622B, 0xE1D9, 0x642B, 0xE1DA, 0x644D, 0xE1DB, 0x645B,	0xE1DC, 0x645D, 0xE1DD, 0x6474, 0xE1DE, 0x6476, 0xE1DF, 0x6472,
+	0xE1E0, 0x6473, 0xE1E1, 0x647D, 0xE1E2, 0x6475, 0xE1E3, 0x6466,	0xE1E4, 0x64A6, 0xE1E5, 0x644E, 0xE1E6, 0x6482, 0xE1E7, 0x645E,
+	0xE1E8, 0x645C, 0xE1E9, 0x644B, 0xE1EA, 0x6453, 0xE1EB, 0x6460,	0xE1EC, 0x6450, 0xE1ED, 0x647F, 0xE1EE, 0x643F, 0xE1EF, 0x646C,
+	0xE1F0, 0x646B, 0xE1F1, 0x6459, 0xE1F2, 0x6465, 0xE1F3, 0x6477,	0xE1F4, 0x6573, 0xE1F5, 0x65A0, 0xE1F6, 0x66A1, 0xE1F7, 0x66A0,
+	0xE1F8, 0x669F, 0xE1F9, 0x6705, 0xE1FA, 0x6704, 0xE1FB, 0x6722,	0xE1FC, 0x69B1, 0xE1FD, 0x69B6, 0xE1FE, 0x69C9, 0xE240, 0x69A0,
+	0xE241, 0x69CE, 0xE242, 0x6996, 0xE243, 0x69B0, 0xE244, 0x69AC,	0xE245, 0x69BC, 0xE246, 0x6991, 0xE247, 0x6999, 0xE248, 0x698E,
+	0xE249, 0x69A7, 0xE24A, 0x698D, 0xE24B, 0x69A9, 0xE24C, 0x69BE,	0xE24D, 0x69AF, 0xE24E, 0x69BF, 0xE24F, 0x69C4, 0xE250, 0x69BD,
+	0xE251, 0x69A4, 0xE252, 0x69D4, 0xE253, 0x69B9, 0xE254, 0x69CA,	0xE255, 0x699A, 0xE256, 0x69CF, 0xE257, 0x69B3, 0xE258, 0x6993,
+	0xE259, 0x69AA, 0xE25A, 0x69A1, 0xE25B, 0x699E, 0xE25C, 0x69D9,	0xE25D, 0x6997, 0xE25E, 0x6990, 0xE25F, 0x69C2, 0xE260, 0x69B5,
+	0xE261, 0x69A5, 0xE262, 0x69C6, 0xE263, 0x6B4A, 0xE264, 0x6B4D,	0xE265, 0x6B4B, 0xE266, 0x6B9E, 0xE267, 0x6B9F, 0xE268, 0x6BA0,
+	0xE269, 0x6BC3, 0xE26A, 0x6BC4, 0xE26B, 0x6BFE, 0xE26C, 0x6ECE,	0xE26D, 0x6EF5, 0xE26E, 0x6EF1, 0xE26F, 0x6F03, 0xE270, 0x6F25,
+	0xE271, 0x6EF8, 0xE272, 0x6F37, 0xE273, 0x6EFB, 0xE274, 0x6F2E,	0xE275, 0x6F09, 0xE276, 0x6F4E, 0xE277, 0x6F19, 0xE278, 0x6F1A,
+	0xE279, 0x6F27, 0xE27A, 0x6F18, 0xE27B, 0x6F3B, 0xE27C, 0x6F12,	0xE27D, 0x6EED, 0xE27E, 0x6F0A, 0xE2A1, 0x6F36, 0xE2A2, 0x6F73,
+	0xE2A3, 0x6EF9, 0xE2A4, 0x6EEE, 0xE2A5, 0x6F2D, 0xE2A6, 0x6F40,	0xE2A7, 0x6F30, 0xE2A8, 0x6F3C, 0xE2A9, 0x6F35, 0xE2AA, 0x6EEB,
+	0xE2AB, 0x6F07, 0xE2AC, 0x6F0E, 0xE2AD, 0x6F43, 0xE2AE, 0x6F05,	0xE2AF, 0x6EFD, 0xE2B0, 0x6EF6, 0xE2B1, 0x6F39, 0xE2B2, 0x6F1C,
+	0xE2B3, 0x6EFC, 0xE2B4, 0x6F3A, 0xE2B5, 0x6F1F, 0xE2B6, 0x6F0D,	0xE2B7, 0x6F1E, 0xE2B8, 0x6F08, 0xE2B9, 0x6F21, 0xE2BA, 0x7187,
+	0xE2BB, 0x7190, 0xE2BC, 0x7189, 0xE2BD, 0x7180, 0xE2BE, 0x7185,	0xE2BF, 0x7182, 0xE2C0, 0x718F, 0xE2C1, 0x717B, 0xE2C2, 0x7186,
+	0xE2C3, 0x7181, 0xE2C4, 0x7197, 0xE2C5, 0x7244, 0xE2C6, 0x7253,	0xE2C7, 0x7297, 0xE2C8, 0x7295, 0xE2C9, 0x7293, 0xE2CA, 0x7343,
+	0xE2CB, 0x734D, 0xE2CC, 0x7351, 0xE2CD, 0x734C, 0xE2CE, 0x7462,	0xE2CF, 0x7473, 0xE2D0, 0x7471, 0xE2D1, 0x7475, 0xE2D2, 0x7472,
+	0xE2D3, 0x7467, 0xE2D4, 0x746E, 0xE2D5, 0x7500, 0xE2D6, 0x7502,	0xE2D7, 0x7503, 0xE2D8, 0x757D, 0xE2D9, 0x7590, 0xE2DA, 0x7616,
+	0xE2DB, 0x7608, 0xE2DC, 0x760C, 0xE2DD, 0x7615, 0xE2DE, 0x7611,	0xE2DF, 0x760A, 0xE2E0, 0x7614, 0xE2E1, 0x76B8, 0xE2E2, 0x7781,
+	0xE2E3, 0x777C, 0xE2E4, 0x7785, 0xE2E5, 0x7782, 0xE2E6, 0x776E,	0xE2E7, 0x7780, 0xE2E8, 0x776F, 0xE2E9, 0x777E, 0xE2EA, 0x7783,
+	0xE2EB, 0x78B2, 0xE2EC, 0x78AA, 0xE2ED, 0x78B4, 0xE2EE, 0x78AD,	0xE2EF, 0x78A8, 0xE2F0, 0x787E, 0xE2F1, 0x78AB, 0xE2F2, 0x789E,
+	0xE2F3, 0x78A5, 0xE2F4, 0x78A0, 0xE2F5, 0x78AC, 0xE2F6, 0x78A2,	0xE2F7, 0x78A4, 0xE2F8, 0x7998, 0xE2F9, 0x798A, 0xE2FA, 0x798B,
+	0xE2FB, 0x7996, 0xE2FC, 0x7995, 0xE2FD, 0x7994, 0xE2FE, 0x7993,	0xE340, 0x7997, 0xE341, 0x7988, 0xE342, 0x7992, 0xE343, 0x7990,
+	0xE344, 0x7A2B, 0xE345, 0x7A4A, 0xE346, 0x7A30, 0xE347, 0x7A2F,	0xE348, 0x7A28, 0xE349, 0x7A26, 0xE34A, 0x7AA8, 0xE34B, 0x7AAB,
+	0xE34C, 0x7AAC, 0xE34D, 0x7AEE, 0xE34E, 0x7B88, 0xE34F, 0x7B9C,	0xE350, 0x7B8A, 0xE351, 0x7B91, 0xE352, 0x7B90, 0xE353, 0x7B96,
+	0xE354, 0x7B8D, 0xE355, 0x7B8C, 0xE356, 0x7B9B, 0xE357, 0x7B8E,	0xE358, 0x7B85, 0xE359, 0x7B98, 0xE35A, 0x5284, 0xE35B, 0x7B99,
+	0xE35C, 0x7BA4, 0xE35D, 0x7B82, 0xE35E, 0x7CBB, 0xE35F, 0x7CBF,	0xE360, 0x7CBC, 0xE361, 0x7CBA, 0xE362, 0x7DA7, 0xE363, 0x7DB7,
+	0xE364, 0x7DC2, 0xE365, 0x7DA3, 0xE366, 0x7DAA, 0xE367, 0x7DC1,	0xE368, 0x7DC0, 0xE369, 0x7DC5, 0xE36A, 0x7D9D, 0xE36B, 0x7DCE,
+	0xE36C, 0x7DC4, 0xE36D, 0x7DC6, 0xE36E, 0x7DCB, 0xE36F, 0x7DCC,	0xE370, 0x7DAF, 0xE371, 0x7DB9, 0xE372, 0x7D96, 0xE373, 0x7DBC,
+	0xE374, 0x7D9F, 0xE375, 0x7DA6, 0xE376, 0x7DAE, 0xE377, 0x7DA9,	0xE378, 0x7DA1, 0xE379, 0x7DC9, 0xE37A, 0x7F73, 0xE37B, 0x7FE2,
+	0xE37C, 0x7FE3, 0xE37D, 0x7FE5, 0xE37E, 0x7FDE, 0xE3A1, 0x8024,	0xE3A2, 0x805D, 0xE3A3, 0x805C, 0xE3A4, 0x8189, 0xE3A5, 0x8186,
+	0xE3A6, 0x8183, 0xE3A7, 0x8187, 0xE3A8, 0x818D, 0xE3A9, 0x818C,	0xE3AA, 0x818B, 0xE3AB, 0x8215, 0xE3AC, 0x8497, 0xE3AD, 0x84A4,
+	0xE3AE, 0x84A1, 0xE3AF, 0x849F, 0xE3B0, 0x84BA, 0xE3B1, 0x84CE,	0xE3B2, 0x84C2, 0xE3B3, 0x84AC, 0xE3B4, 0x84AE, 0xE3B5, 0x84AB,
+	0xE3B6, 0x84B9, 0xE3B7, 0x84B4, 0xE3B8, 0x84C1, 0xE3B9, 0x84CD,	0xE3BA, 0x84AA, 0xE3BB, 0x849A, 0xE3BC, 0x84B1, 0xE3BD, 0x84D0,
+	0xE3BE, 0x849D, 0xE3BF, 0x84A7, 0xE3C0, 0x84BB, 0xE3C1, 0x84A2,	0xE3C2, 0x8494, 0xE3C3, 0x84C7, 0xE3C4, 0x84CC, 0xE3C5, 0x849B,
+	0xE3C6, 0x84A9, 0xE3C7, 0x84AF, 0xE3C8, 0x84A8, 0xE3C9, 0x84D6,	0xE3CA, 0x8498, 0xE3CB, 0x84B6, 0xE3CC, 0x84CF, 0xE3CD, 0x84A0,
+	0xE3CE, 0x84D7, 0xE3CF, 0x84D4, 0xE3D0, 0x84D2, 0xE3D1, 0x84DB,	0xE3D2, 0x84B0, 0xE3D3, 0x8491, 0xE3D4, 0x8661, 0xE3D5, 0x8733,
+	0xE3D6, 0x8723, 0xE3D7, 0x8728, 0xE3D8, 0x876B, 0xE3D9, 0x8740,	0xE3DA, 0x872E, 0xE3DB, 0x871E, 0xE3DC, 0x8721, 0xE3DD, 0x8719,
+	0xE3DE, 0x871B, 0xE3DF, 0x8743, 0xE3E0, 0x872C, 0xE3E1, 0x8741,	0xE3E2, 0x873E, 0xE3E3, 0x8746, 0xE3E4, 0x8720, 0xE3E5, 0x8732,
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+	0xE3F6, 0x88E7, 0xE3F7, 0x88F1, 0xE3F8, 0x88F2, 0xE3F9, 0x88FA,	0xE3FA, 0x88FE, 0xE3FB, 0x88EE, 0xE3FC, 0x88FC, 0xE3FD, 0x88F6,
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+	0xE44F, 0x8A96, 0xE450, 0x8C3D, 0xE451, 0x8C68, 0xE452, 0x8C69,	0xE453, 0x8CD5, 0xE454, 0x8CCF, 0xE455, 0x8CD7, 0xE456, 0x8D96,
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+	0xE4A1, 0x92A6, 0xE4A2, 0x929A, 0xE4A3, 0x92AB, 0xE4A4, 0x9279,	0xE4A5, 0x9297, 0xE4A6, 0x927F, 0xE4A7, 0x92A3, 0xE4A8, 0x92EE,
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+	0xE4B1, 0x9286, 0xE4B2, 0x928C, 0xE4B3, 0x9299, 0xE4B4, 0x92A7,	0xE4B5, 0x927E, 0xE4B6, 0x9287, 0xE4B7, 0x92A9, 0xE4B8, 0x929D,
+	0xE4B9, 0x928B, 0xE4BA, 0x922D, 0xE4BB, 0x969E, 0xE4BC, 0x96A1,	0xE4BD, 0x96FF, 0xE4BE, 0x9758, 0xE4BF, 0x977D, 0xE4C0, 0x977A,
+	0xE4C1, 0x977E, 0xE4C2, 0x9783, 0xE4C3, 0x9780, 0xE4C4, 0x9782,	0xE4C5, 0x977B, 0xE4C6, 0x9784, 0xE4C7, 0x9781, 0xE4C8, 0x977F,
+	0xE4C9, 0x97CE, 0xE4CA, 0x97CD, 0xE4CB, 0x9816, 0xE4CC, 0x98AD,	0xE4CD, 0x98AE, 0xE4CE, 0x9902, 0xE4CF, 0x9900, 0xE4D0, 0x9907,
+	0xE4D1, 0x999D, 0xE4D2, 0x999C, 0xE4D3, 0x99C3, 0xE4D4, 0x99B9,	0xE4D5, 0x99BB, 0xE4D6, 0x99BA, 0xE4D7, 0x99C2, 0xE4D8, 0x99BD,
+	0xE4D9, 0x99C7, 0xE4DA, 0x9AB1, 0xE4DB, 0x9AE3, 0xE4DC, 0x9AE7,	0xE4DD, 0x9B3E, 0xE4DE, 0x9B3F, 0xE4DF, 0x9B60, 0xE4E0, 0x9B61,
+	0xE4E1, 0x9B5F, 0xE4E2, 0x9CF1, 0xE4E3, 0x9CF2, 0xE4E4, 0x9CF5,	0xE4E5, 0x9EA7, 0xE4E6, 0x50FF, 0xE4E7, 0x5103, 0xE4E8, 0x5130,
+	0xE4E9, 0x50F8, 0xE4EA, 0x5106, 0xE4EB, 0x5107, 0xE4EC, 0x50F6,	0xE4ED, 0x50FE, 0xE4EE, 0x510B, 0xE4EF, 0x510C, 0xE4F0, 0x50FD,
+	0xE4F1, 0x510A, 0xE4F2, 0x528B, 0xE4F3, 0x528C, 0xE4F4, 0x52F1,	0xE4F5, 0x52EF, 0xE4F6, 0x5648, 0xE4F7, 0x5642, 0xE4F8, 0x564C,
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+	0xE562, 0x5D99, 0xE563, 0x5D97, 0xE564, 0x5D9F, 0xE565, 0x5D92,	0xE566, 0x5DA2, 0xE567, 0x5D93, 0xE568, 0x5D95, 0xE569, 0x5DA0,
+	0xE56A, 0x5D9C, 0xE56B, 0x5DA1, 0xE56C, 0x5D9A, 0xE56D, 0x5D9E,	0xE56E, 0x5E69, 0xE56F, 0x5E5D, 0xE570, 0x5E60, 0xE571, 0x5E5C,
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+	0xE7B2, 0x874E, 0xE7B3, 0x875F, 0xE7B4, 0x875D, 0xE7B5, 0x876F,	0xE7B6, 0x876C, 0xE7B7, 0x877A, 0xE7B8, 0x876E, 0xE7B9, 0x875C,
+	0xE7BA, 0x8765, 0xE7BB, 0x874F, 0xE7BC, 0x877B, 0xE7BD, 0x8775,	0xE7BE, 0x8762, 0xE7BF, 0x8767, 0xE7C0, 0x8769, 0xE7C1, 0x885A,
+	0xE7C2, 0x8905, 0xE7C3, 0x890C, 0xE7C4, 0x8914, 0xE7C5, 0x890B,	0xE7C6, 0x8917, 0xE7C7, 0x8918, 0xE7C8, 0x8919, 0xE7C9, 0x8906,
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+	0xE7DA, 0x8AD5, 0xE7DB, 0x8ABB, 0xE7DC, 0x8AD7, 0xE7DD, 0x8ABE,	0xE7DE, 0x8AC0, 0xE7DF, 0x8AC5, 0xE7E0, 0x8AD8, 0xE7E1, 0x8AC3,
+	0xE7E2, 0x8ABA, 0xE7E3, 0x8ABD, 0xE7E4, 0x8AD9, 0xE7E5, 0x8C3E,	0xE7E6, 0x8C4D, 0xE7E7, 0x8C8F, 0xE7E8, 0x8CE5, 0xE7E9, 0x8CDF,
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+	0xF0F5, 0x8D02, 0xF0F6, 0x8D00, 0xF0F7, 0x8E5C, 0xF0F8, 0x8E62,	0xF0F9, 0x8E60, 0xF0FA, 0x8E57, 0xF0FB, 0x8E56, 0xF0FC, 0x8E5E,
+	0xF0FD, 0x8E65, 0xF0FE, 0x8E67, 0xF140, 0x8E5B, 0xF141, 0x8E5A,	0xF142, 0x8E61, 0xF143, 0x8E5D, 0xF144, 0x8E69, 0xF145, 0x8E54,
+	0xF146, 0x8F46, 0xF147, 0x8F47, 0xF148, 0x8F48, 0xF149, 0x8F4B,	0xF14A, 0x9128, 0xF14B, 0x913A, 0xF14C, 0x913B, 0xF14D, 0x913E,
+	0xF14E, 0x91A8, 0xF14F, 0x91A5, 0xF150, 0x91A7, 0xF151, 0x91AF,	0xF152, 0x91AA, 0xF153, 0x93B5, 0xF154, 0x938C, 0xF155, 0x9392,
+	0xF156, 0x93B7, 0xF157, 0x939B, 0xF158, 0x939D, 0xF159, 0x9389,	0xF15A, 0x93A7, 0xF15B, 0x938E, 0xF15C, 0x93AA, 0xF15D, 0x939E,
+	0xF15E, 0x93A6, 0xF15F, 0x9395, 0xF160, 0x9388, 0xF161, 0x9399,	0xF162, 0x939F, 0xF163, 0x938D, 0xF164, 0x93B1, 0xF165, 0x9391,
+	0xF166, 0x93B2, 0xF167, 0x93A4, 0xF168, 0x93A8, 0xF169, 0x93B4,	0xF16A, 0x93A3, 0xF16B, 0x93A5, 0xF16C, 0x95D2, 0xF16D, 0x95D3,
+	0xF16E, 0x95D1, 0xF16F, 0x96B3, 0xF170, 0x96D7, 0xF171, 0x96DA,	0xF172, 0x5DC2, 0xF173, 0x96DF, 0xF174, 0x96D8, 0xF175, 0x96DD,
+	0xF176, 0x9723, 0xF177, 0x9722, 0xF178, 0x9725, 0xF179, 0x97AC,	0xF17A, 0x97AE, 0xF17B, 0x97A8, 0xF17C, 0x97AB, 0xF17D, 0x97A4,
+	0xF17E, 0x97AA, 0xF1A1, 0x97A2, 0xF1A2, 0x97A5, 0xF1A3, 0x97D7,	0xF1A4, 0x97D9, 0xF1A5, 0x97D6, 0xF1A6, 0x97D8, 0xF1A7, 0x97FA,
+	0xF1A8, 0x9850, 0xF1A9, 0x9851, 0xF1AA, 0x9852, 0xF1AB, 0x98B8,	0xF1AC, 0x9941, 0xF1AD, 0x993C, 0xF1AE, 0x993A, 0xF1AF, 0x9A0F,
+	0xF1B0, 0x9A0B, 0xF1B1, 0x9A09, 0xF1B2, 0x9A0D, 0xF1B3, 0x9A04,	0xF1B4, 0x9A11, 0xF1B5, 0x9A0A, 0xF1B6, 0x9A05, 0xF1B7, 0x9A07,
+	0xF1B8, 0x9A06, 0xF1B9, 0x9AC0, 0xF1BA, 0x9ADC, 0xF1BB, 0x9B08,	0xF1BC, 0x9B04, 0xF1BD, 0x9B05, 0xF1BE, 0x9B29, 0xF1BF, 0x9B35,
+	0xF1C0, 0x9B4A, 0xF1C1, 0x9B4C, 0xF1C2, 0x9B4B, 0xF1C3, 0x9BC7,	0xF1C4, 0x9BC6, 0xF1C5, 0x9BC3, 0xF1C6, 0x9BBF, 0xF1C7, 0x9BC1,
+	0xF1C8, 0x9BB5, 0xF1C9, 0x9BB8, 0xF1CA, 0x9BD3, 0xF1CB, 0x9BB6,	0xF1CC, 0x9BC4, 0xF1CD, 0x9BB9, 0xF1CE, 0x9BBD, 0xF1CF, 0x9D5C,
+	0xF1D0, 0x9D53, 0xF1D1, 0x9D4F, 0xF1D2, 0x9D4A, 0xF1D3, 0x9D5B,	0xF1D4, 0x9D4B, 0xF1D5, 0x9D59, 0xF1D6, 0x9D56, 0xF1D7, 0x9D4C,
+	0xF1D8, 0x9D57, 0xF1D9, 0x9D52, 0xF1DA, 0x9D54, 0xF1DB, 0x9D5F,	0xF1DC, 0x9D58, 0xF1DD, 0x9D5A, 0xF1DE, 0x9E8E, 0xF1DF, 0x9E8C,
+	0xF1E0, 0x9EDF, 0xF1E1, 0x9F01, 0xF1E2, 0x9F00, 0xF1E3, 0x9F16,	0xF1E4, 0x9F25, 0xF1E5, 0x9F2B, 0xF1E6, 0x9F2A, 0xF1E7, 0x9F29,
+	0xF1E8, 0x9F28, 0xF1E9, 0x9F4C, 0xF1EA, 0x9F55, 0xF1EB, 0x5134,	0xF1EC, 0x5135, 0xF1ED, 0x5296, 0xF1EE, 0x52F7, 0xF1EF, 0x53B4,
+	0xF1F0, 0x56AB, 0xF1F1, 0x56AD, 0xF1F2, 0x56A6, 0xF1F3, 0x56A7,	0xF1F4, 0x56AA, 0xF1F5, 0x56AC, 0xF1F6, 0x58DA, 0xF1F7, 0x58DD,
+	0xF1F8, 0x58DB, 0xF1F9, 0x5912, 0xF1FA, 0x5B3D, 0xF1FB, 0x5B3E,	0xF1FC, 0x5B3F, 0xF1FD, 0x5DC3, 0xF1FE, 0x5E70, 0xF240, 0x5FBF,
+	0xF241, 0x61FB, 0xF242, 0x6507, 0xF243, 0x6510, 0xF244, 0x650D,	0xF245, 0x6509, 0xF246, 0x650C, 0xF247, 0x650E, 0xF248, 0x6584,
+	0xF249, 0x65DE, 0xF24A, 0x65DD, 0xF24B, 0x66DE, 0xF24C, 0x6AE7,	0xF24D, 0x6AE0, 0xF24E, 0x6ACC, 0xF24F, 0x6AD1, 0xF250, 0x6AD9,
+	0xF251, 0x6ACB, 0xF252, 0x6ADF, 0xF253, 0x6ADC, 0xF254, 0x6AD0,	0xF255, 0x6AEB, 0xF256, 0x6ACF, 0xF257, 0x6ACD, 0xF258, 0x6ADE,
+	0xF259, 0x6B60, 0xF25A, 0x6BB0, 0xF25B, 0x6C0C, 0xF25C, 0x7019,	0xF25D, 0x7027, 0xF25E, 0x7020, 0xF25F, 0x7016, 0xF260, 0x702B,
+	0xF261, 0x7021, 0xF262, 0x7022, 0xF263, 0x7023, 0xF264, 0x7029,	0xF265, 0x7017, 0xF266, 0x7024, 0xF267, 0x701C, 0xF268, 0x702A,
+	0xF269, 0x720C, 0xF26A, 0x720A, 0xF26B, 0x7207, 0xF26C, 0x7202,	0xF26D, 0x7205, 0xF26E, 0x72A5, 0xF26F, 0x72A6, 0xF270, 0x72A4,
+	0xF271, 0x72A3, 0xF272, 0x72A1, 0xF273, 0x74CB, 0xF274, 0x74C5,	0xF275, 0x74B7, 0xF276, 0x74C3, 0xF277, 0x7516, 0xF278, 0x7660,
+	0xF279, 0x77C9, 0xF27A, 0x77CA, 0xF27B, 0x77C4, 0xF27C, 0x77F1,	0xF27D, 0x791D, 0xF27E, 0x791B, 0xF2A1, 0x7921, 0xF2A2, 0x791C,
+	0xF2A3, 0x7917, 0xF2A4, 0x791E, 0xF2A5, 0x79B0, 0xF2A6, 0x7A67,	0xF2A7, 0x7A68, 0xF2A8, 0x7C33, 0xF2A9, 0x7C3C, 0xF2AA, 0x7C39,
+	0xF2AB, 0x7C2C, 0xF2AC, 0x7C3B, 0xF2AD, 0x7CEC, 0xF2AE, 0x7CEA,	0xF2AF, 0x7E76, 0xF2B0, 0x7E75, 0xF2B1, 0x7E78, 0xF2B2, 0x7E70,
+	0xF2B3, 0x7E77, 0xF2B4, 0x7E6F, 0xF2B5, 0x7E7A, 0xF2B6, 0x7E72,	0xF2B7, 0x7E74, 0xF2B8, 0x7E68, 0xF2B9, 0x7F4B, 0xF2BA, 0x7F4A,
+	0xF2BB, 0x7F83, 0xF2BC, 0x7F86, 0xF2BD, 0x7FB7, 0xF2BE, 0x7FFD,	0xF2BF, 0x7FFE, 0xF2C0, 0x8078, 0xF2C1, 0x81D7, 0xF2C2, 0x81D5,
+	0xF2C3, 0x8264, 0xF2C4, 0x8261, 0xF2C5, 0x8263, 0xF2C6, 0x85EB,	0xF2C7, 0x85F1, 0xF2C8, 0x85ED, 0xF2C9, 0x85D9, 0xF2CA, 0x85E1,
+	0xF2CB, 0x85E8, 0xF2CC, 0x85DA, 0xF2CD, 0x85D7, 0xF2CE, 0x85EC,	0xF2CF, 0x85F2, 0xF2D0, 0x85F8, 0xF2D1, 0x85D8, 0xF2D2, 0x85DF,
+	0xF2D3, 0x85E3, 0xF2D4, 0x85DC, 0xF2D5, 0x85D1, 0xF2D6, 0x85F0,	0xF2D7, 0x85E6, 0xF2D8, 0x85EF, 0xF2D9, 0x85DE, 0xF2DA, 0x85E2,
+	0xF2DB, 0x8800, 0xF2DC, 0x87FA, 0xF2DD, 0x8803, 0xF2DE, 0x87F6,	0xF2DF, 0x87F7, 0xF2E0, 0x8809, 0xF2E1, 0x880C, 0xF2E2, 0x880B,
+	0xF2E3, 0x8806, 0xF2E4, 0x87FC, 0xF2E5, 0x8808, 0xF2E6, 0x87FF,	0xF2E7, 0x880A, 0xF2E8, 0x8802, 0xF2E9, 0x8962, 0xF2EA, 0x895A,
+	0xF2EB, 0x895B, 0xF2EC, 0x8957, 0xF2ED, 0x8961, 0xF2EE, 0x895C,	0xF2EF, 0x8958, 0xF2F0, 0x895D, 0xF2F1, 0x8959, 0xF2F2, 0x8988,
+	0xF2F3, 0x89B7, 0xF2F4, 0x89B6, 0xF2F5, 0x89F6, 0xF2F6, 0x8B50,	0xF2F7, 0x8B48, 0xF2F8, 0x8B4A, 0xF2F9, 0x8B40, 0xF2FA, 0x8B53,
+	0xF2FB, 0x8B56, 0xF2FC, 0x8B54, 0xF2FD, 0x8B4B, 0xF2FE, 0x8B55,	0xF340, 0x8B51, 0xF341, 0x8B42, 0xF342, 0x8B52, 0xF343, 0x8B57,
+	0xF344, 0x8C43, 0xF345, 0x8C77, 0xF346, 0x8C76, 0xF347, 0x8C9A,	0xF348, 0x8D06, 0xF349, 0x8D07, 0xF34A, 0x8D09, 0xF34B, 0x8DAC,
+	0xF34C, 0x8DAA, 0xF34D, 0x8DAD, 0xF34E, 0x8DAB, 0xF34F, 0x8E6D,	0xF350, 0x8E78, 0xF351, 0x8E73, 0xF352, 0x8E6A, 0xF353, 0x8E6F,
+	0xF354, 0x8E7B, 0xF355, 0x8EC2, 0xF356, 0x8F52, 0xF357, 0x8F51,	0xF358, 0x8F4F, 0xF359, 0x8F50, 0xF35A, 0x8F53, 0xF35B, 0x8FB4,
+	0xF35C, 0x9140, 0xF35D, 0x913F, 0xF35E, 0x91B0, 0xF35F, 0x91AD,	0xF360, 0x93DE, 0xF361, 0x93C7, 0xF362, 0x93CF, 0xF363, 0x93C2,
+	0xF364, 0x93DA, 0xF365, 0x93D0, 0xF366, 0x93F9, 0xF367, 0x93EC,	0xF368, 0x93CC, 0xF369, 0x93D9, 0xF36A, 0x93A9, 0xF36B, 0x93E6,
+	0xF36C, 0x93CA, 0xF36D, 0x93D4, 0xF36E, 0x93EE, 0xF36F, 0x93E3,	0xF370, 0x93D5, 0xF371, 0x93C4, 0xF372, 0x93CE, 0xF373, 0x93C0,
+	0xF374, 0x93D2, 0xF375, 0x93E7, 0xF376, 0x957D, 0xF377, 0x95DA,	0xF378, 0x95DB, 0xF379, 0x96E1, 0xF37A, 0x9729, 0xF37B, 0x972B,
+	0xF37C, 0x972C, 0xF37D, 0x9728, 0xF37E, 0x9726, 0xF3A1, 0x97B3,	0xF3A2, 0x97B7, 0xF3A3, 0x97B6, 0xF3A4, 0x97DD, 0xF3A5, 0x97DE,
+	0xF3A6, 0x97DF, 0xF3A7, 0x985C, 0xF3A8, 0x9859, 0xF3A9, 0x985D,	0xF3AA, 0x9857, 0xF3AB, 0x98BF, 0xF3AC, 0x98BD, 0xF3AD, 0x98BB,
+	0xF3AE, 0x98BE, 0xF3AF, 0x9948, 0xF3B0, 0x9947, 0xF3B1, 0x9943,	0xF3B2, 0x99A6, 0xF3B3, 0x99A7, 0xF3B4, 0x9A1A, 0xF3B5, 0x9A15,
+	0xF3B6, 0x9A25, 0xF3B7, 0x9A1D, 0xF3B8, 0x9A24, 0xF3B9, 0x9A1B,	0xF3BA, 0x9A22, 0xF3BB, 0x9A20, 0xF3BC, 0x9A27, 0xF3BD, 0x9A23,
+	0xF3BE, 0x9A1E, 0xF3BF, 0x9A1C, 0xF3C0, 0x9A14, 0xF3C1, 0x9AC2,	0xF3C2, 0x9B0B, 0xF3C3, 0x9B0A, 0xF3C4, 0x9B0E, 0xF3C5, 0x9B0C,
+	0xF3C6, 0x9B37, 0xF3C7, 0x9BEA, 0xF3C8, 0x9BEB, 0xF3C9, 0x9BE0,	0xF3CA, 0x9BDE, 0xF3CB, 0x9BE4, 0xF3CC, 0x9BE6, 0xF3CD, 0x9BE2,
+	0xF3CE, 0x9BF0, 0xF3CF, 0x9BD4, 0xF3D0, 0x9BD7, 0xF3D1, 0x9BEC,	0xF3D2, 0x9BDC, 0xF3D3, 0x9BD9, 0xF3D4, 0x9BE5, 0xF3D5, 0x9BD5,
+	0xF3D6, 0x9BE1, 0xF3D7, 0x9BDA, 0xF3D8, 0x9D77, 0xF3D9, 0x9D81,	0xF3DA, 0x9D8A, 0xF3DB, 0x9D84, 0xF3DC, 0x9D88, 0xF3DD, 0x9D71,
+	0xF3DE, 0x9D80, 0xF3DF, 0x9D78, 0xF3E0, 0x9D86, 0xF3E1, 0x9D8B,	0xF3E2, 0x9D8C, 0xF3E3, 0x9D7D, 0xF3E4, 0x9D6B, 0xF3E5, 0x9D74,
+	0xF3E6, 0x9D75, 0xF3E7, 0x9D70, 0xF3E8, 0x9D69, 0xF3E9, 0x9D85,	0xF3EA, 0x9D73, 0xF3EB, 0x9D7B, 0xF3EC, 0x9D82, 0xF3ED, 0x9D6F,
+	0xF3EE, 0x9D79, 0xF3EF, 0x9D7F, 0xF3F0, 0x9D87, 0xF3F1, 0x9D68,	0xF3F2, 0x9E94, 0xF3F3, 0x9E91, 0xF3F4, 0x9EC0, 0xF3F5, 0x9EFC,
+	0xF3F6, 0x9F2D, 0xF3F7, 0x9F40, 0xF3F8, 0x9F41, 0xF3F9, 0x9F4D,	0xF3FA, 0x9F56, 0xF3FB, 0x9F57, 0xF3FC, 0x9F58, 0xF3FD, 0x5337,
+	0xF3FE, 0x56B2, 0xF440, 0x56B5, 0xF441, 0x56B3, 0xF442, 0x58E3,	0xF443, 0x5B45, 0xF444, 0x5DC6, 0xF445, 0x5DC7, 0xF446, 0x5EEE,
+	0xF447, 0x5EEF, 0xF448, 0x5FC0, 0xF449, 0x5FC1, 0xF44A, 0x61F9,	0xF44B, 0x6517, 0xF44C, 0x6516, 0xF44D, 0x6515, 0xF44E, 0x6513,
+	0xF44F, 0x65DF, 0xF450, 0x66E8, 0xF451, 0x66E3, 0xF452, 0x66E4,	0xF453, 0x6AF3, 0xF454, 0x6AF0, 0xF455, 0x6AEA, 0xF456, 0x6AE8,
+	0xF457, 0x6AF9, 0xF458, 0x6AF1, 0xF459, 0x6AEE, 0xF45A, 0x6AEF,	0xF45B, 0x703C, 0xF45C, 0x7035, 0xF45D, 0x702F, 0xF45E, 0x7037,
+	0xF45F, 0x7034, 0xF460, 0x7031, 0xF461, 0x7042, 0xF462, 0x7038,	0xF463, 0x703F, 0xF464, 0x703A, 0xF465, 0x7039, 0xF466, 0x7040,
+	0xF467, 0x703B, 0xF468, 0x7033, 0xF469, 0x7041, 0xF46A, 0x7213,	0xF46B, 0x7214, 0xF46C, 0x72A8, 0xF46D, 0x737D, 0xF46E, 0x737C,
+	0xF46F, 0x74BA, 0xF470, 0x76AB, 0xF471, 0x76AA, 0xF472, 0x76BE,	0xF473, 0x76ED, 0xF474, 0x77CC, 0xF475, 0x77CE, 0xF476, 0x77CF,
+	0xF477, 0x77CD, 0xF478, 0x77F2, 0xF479, 0x7925, 0xF47A, 0x7923,	0xF47B, 0x7927, 0xF47C, 0x7928, 0xF47D, 0x7924, 0xF47E, 0x7929,
+	0xF4A1, 0x79B2, 0xF4A2, 0x7A6E, 0xF4A3, 0x7A6C, 0xF4A4, 0x7A6D,	0xF4A5, 0x7AF7, 0xF4A6, 0x7C49, 0xF4A7, 0x7C48, 0xF4A8, 0x7C4A,
+	0xF4A9, 0x7C47, 0xF4AA, 0x7C45, 0xF4AB, 0x7CEE, 0xF4AC, 0x7E7B,	0xF4AD, 0x7E7E, 0xF4AE, 0x7E81, 0xF4AF, 0x7E80, 0xF4B0, 0x7FBA,
+	0xF4B1, 0x7FFF, 0xF4B2, 0x8079, 0xF4B3, 0x81DB, 0xF4B4, 0x81D9,	0xF4B5, 0x820B, 0xF4B6, 0x8268, 0xF4B7, 0x8269, 0xF4B8, 0x8622,
+	0xF4B9, 0x85FF, 0xF4BA, 0x8601, 0xF4BB, 0x85FE, 0xF4BC, 0x861B,	0xF4BD, 0x8600, 0xF4BE, 0x85F6, 0xF4BF, 0x8604, 0xF4C0, 0x8609,
+	0xF4C1, 0x8605, 0xF4C2, 0x860C, 0xF4C3, 0x85FD, 0xF4C4, 0x8819,	0xF4C5, 0x8810, 0xF4C6, 0x8811, 0xF4C7, 0x8817, 0xF4C8, 0x8813,
+	0xF4C9, 0x8816, 0xF4CA, 0x8963, 0xF4CB, 0x8966, 0xF4CC, 0x89B9,	0xF4CD, 0x89F7, 0xF4CE, 0x8B60, 0xF4CF, 0x8B6A, 0xF4D0, 0x8B5D,
+	0xF4D1, 0x8B68, 0xF4D2, 0x8B63, 0xF4D3, 0x8B65, 0xF4D4, 0x8B67,	0xF4D5, 0x8B6D, 0xF4D6, 0x8DAE, 0xF4D7, 0x8E86, 0xF4D8, 0x8E88,
+	0xF4D9, 0x8E84, 0xF4DA, 0x8F59, 0xF4DB, 0x8F56, 0xF4DC, 0x8F57,	0xF4DD, 0x8F55, 0xF4DE, 0x8F58, 0xF4DF, 0x8F5A, 0xF4E0, 0x908D,
+	0xF4E1, 0x9143, 0xF4E2, 0x9141, 0xF4E3, 0x91B7, 0xF4E4, 0x91B5,	0xF4E5, 0x91B2, 0xF4E6, 0x91B3, 0xF4E7, 0x940B, 0xF4E8, 0x9413,
+	0xF4E9, 0x93FB, 0xF4EA, 0x9420, 0xF4EB, 0x940F, 0xF4EC, 0x9414,	0xF4ED, 0x93FE, 0xF4EE, 0x9415, 0xF4EF, 0x9410, 0xF4F0, 0x9428,
+	0xF4F1, 0x9419, 0xF4F2, 0x940D, 0xF4F3, 0x93F5, 0xF4F4, 0x9400,	0xF4F5, 0x93F7, 0xF4F6, 0x9407, 0xF4F7, 0x940E, 0xF4F8, 0x9416,
+	0xF4F9, 0x9412, 0xF4FA, 0x93FA, 0xF4FB, 0x9409, 0xF4FC, 0x93F8,	0xF4FD, 0x940A, 0xF4FE, 0x93FF, 0xF540, 0x93FC, 0xF541, 0x940C,
+	0xF542, 0x93F6, 0xF543, 0x9411, 0xF544, 0x9406, 0xF545, 0x95DE,	0xF546, 0x95E0, 0xF547, 0x95DF, 0xF548, 0x972E, 0xF549, 0x972F,
+	0xF54A, 0x97B9, 0xF54B, 0x97BB, 0xF54C, 0x97FD, 0xF54D, 0x97FE,	0xF54E, 0x9860, 0xF54F, 0x9862, 0xF550, 0x9863, 0xF551, 0x985F,
+	0xF552, 0x98C1, 0xF553, 0x98C2, 0xF554, 0x9950, 0xF555, 0x994E,	0xF556, 0x9959, 0xF557, 0x994C, 0xF558, 0x994B, 0xF559, 0x9953,
+	0xF55A, 0x9A32, 0xF55B, 0x9A34, 0xF55C, 0x9A31, 0xF55D, 0x9A2C,	0xF55E, 0x9A2A, 0xF55F, 0x9A36, 0xF560, 0x9A29, 0xF561, 0x9A2E,
+	0xF562, 0x9A38, 0xF563, 0x9A2D, 0xF564, 0x9AC7, 0xF565, 0x9ACA,	0xF566, 0x9AC6, 0xF567, 0x9B10, 0xF568, 0x9B12, 0xF569, 0x9B11,
+	0xF56A, 0x9C0B, 0xF56B, 0x9C08, 0xF56C, 0x9BF7, 0xF56D, 0x9C05,	0xF56E, 0x9C12, 0xF56F, 0x9BF8, 0xF570, 0x9C40, 0xF571, 0x9C07,
+	0xF572, 0x9C0E, 0xF573, 0x9C06, 0xF574, 0x9C17, 0xF575, 0x9C14,	0xF576, 0x9C09, 0xF577, 0x9D9F, 0xF578, 0x9D99, 0xF579, 0x9DA4,
+	0xF57A, 0x9D9D, 0xF57B, 0x9D92, 0xF57C, 0x9D98, 0xF57D, 0x9D90,	0xF57E, 0x9D9B, 0xF5A1, 0x9DA0, 0xF5A2, 0x9D94, 0xF5A3, 0x9D9C,
+	0xF5A4, 0x9DAA, 0xF5A5, 0x9D97, 0xF5A6, 0x9DA1, 0xF5A7, 0x9D9A,	0xF5A8, 0x9DA2, 0xF5A9, 0x9DA8, 0xF5AA, 0x9D9E, 0xF5AB, 0x9DA3,
+	0xF5AC, 0x9DBF, 0xF5AD, 0x9DA9, 0xF5AE, 0x9D96, 0xF5AF, 0x9DA6,	0xF5B0, 0x9DA7, 0xF5B1, 0x9E99, 0xF5B2, 0x9E9B, 0xF5B3, 0x9E9A,
+	0xF5B4, 0x9EE5, 0xF5B5, 0x9EE4, 0xF5B6, 0x9EE7, 0xF5B7, 0x9EE6,	0xF5B8, 0x9F30, 0xF5B9, 0x9F2E, 0xF5BA, 0x9F5B, 0xF5BB, 0x9F60,
+	0xF5BC, 0x9F5E, 0xF5BD, 0x9F5D, 0xF5BE, 0x9F59, 0xF5BF, 0x9F91,	0xF5C0, 0x513A, 0xF5C1, 0x5139, 0xF5C2, 0x5298, 0xF5C3, 0x5297,
+	0xF5C4, 0x56C3, 0xF5C5, 0x56BD, 0xF5C6, 0x56BE, 0xF5C7, 0x5B48,	0xF5C8, 0x5B47, 0xF5C9, 0x5DCB, 0xF5CA, 0x5DCF, 0xF5CB, 0x5EF1,
+	0xF5CC, 0x61FD, 0xF5CD, 0x651B, 0xF5CE, 0x6B02, 0xF5CF, 0x6AFC,	0xF5D0, 0x6B03, 0xF5D1, 0x6AF8, 0xF5D2, 0x6B00, 0xF5D3, 0x7043,
+	0xF5D4, 0x7044, 0xF5D5, 0x704A, 0xF5D6, 0x7048, 0xF5D7, 0x7049,	0xF5D8, 0x7045, 0xF5D9, 0x7046, 0xF5DA, 0x721D, 0xF5DB, 0x721A,
+	0xF5DC, 0x7219, 0xF5DD, 0x737E, 0xF5DE, 0x7517, 0xF5DF, 0x766A,	0xF5E0, 0x77D0, 0xF5E1, 0x792D, 0xF5E2, 0x7931, 0xF5E3, 0x792F,
+	0xF5E4, 0x7C54, 0xF5E5, 0x7C53, 0xF5E6, 0x7CF2, 0xF5E7, 0x7E8A,	0xF5E8, 0x7E87, 0xF5E9, 0x7E88, 0xF5EA, 0x7E8B, 0xF5EB, 0x7E86,
+	0xF5EC, 0x7E8D, 0xF5ED, 0x7F4D, 0xF5EE, 0x7FBB, 0xF5EF, 0x8030,	0xF5F0, 0x81DD, 0xF5F1, 0x8618, 0xF5F2, 0x862A, 0xF5F3, 0x8626,
+	0xF5F4, 0x861F, 0xF5F5, 0x8623, 0xF5F6, 0x861C, 0xF5F7, 0x8619,	0xF5F8, 0x8627, 0xF5F9, 0x862E, 0xF5FA, 0x8621, 0xF5FB, 0x8620,
+	0xF5FC, 0x8629, 0xF5FD, 0x861E, 0xF5FE, 0x8625, 0xF640, 0x8829,	0xF641, 0x881D, 0xF642, 0x881B, 0xF643, 0x8820, 0xF644, 0x8824,
+	0xF645, 0x881C, 0xF646, 0x882B, 0xF647, 0x884A, 0xF648, 0x896D,	0xF649, 0x8969, 0xF64A, 0x896E, 0xF64B, 0x896B, 0xF64C, 0x89FA,
+	0xF64D, 0x8B79, 0xF64E, 0x8B78, 0xF64F, 0x8B45, 0xF650, 0x8B7A,	0xF651, 0x8B7B, 0xF652, 0x8D10, 0xF653, 0x8D14, 0xF654, 0x8DAF,
+	0xF655, 0x8E8E, 0xF656, 0x8E8C, 0xF657, 0x8F5E, 0xF658, 0x8F5B,	0xF659, 0x8F5D, 0xF65A, 0x9146, 0xF65B, 0x9144, 0xF65C, 0x9145,
+	0xF65D, 0x91B9, 0xF65E, 0x943F, 0xF65F, 0x943B, 0xF660, 0x9436,	0xF661, 0x9429, 0xF662, 0x943D, 0xF663, 0x943C, 0xF664, 0x9430,
+	0xF665, 0x9439, 0xF666, 0x942A, 0xF667, 0x9437, 0xF668, 0x942C,	0xF669, 0x9440, 0xF66A, 0x9431, 0xF66B, 0x95E5, 0xF66C, 0x95E4,
+	0xF66D, 0x95E3, 0xF66E, 0x9735, 0xF66F, 0x973A, 0xF670, 0x97BF,	0xF671, 0x97E1, 0xF672, 0x9864, 0xF673, 0x98C9, 0xF674, 0x98C6,
+	0xF675, 0x98C0, 0xF676, 0x9958, 0xF677, 0x9956, 0xF678, 0x9A39,	0xF679, 0x9A3D, 0xF67A, 0x9A46, 0xF67B, 0x9A44, 0xF67C, 0x9A42,
+	0xF67D, 0x9A41, 0xF67E, 0x9A3A, 0xF6A1, 0x9A3F, 0xF6A2, 0x9ACD,	0xF6A3, 0x9B15, 0xF6A4, 0x9B17, 0xF6A5, 0x9B18, 0xF6A6, 0x9B16,
+	0xF6A7, 0x9B3A, 0xF6A8, 0x9B52, 0xF6A9, 0x9C2B, 0xF6AA, 0x9C1D,	0xF6AB, 0x9C1C, 0xF6AC, 0x9C2C, 0xF6AD, 0x9C23, 0xF6AE, 0x9C28,
+	0xF6AF, 0x9C29, 0xF6B0, 0x9C24, 0xF6B1, 0x9C21, 0xF6B2, 0x9DB7,	0xF6B3, 0x9DB6, 0xF6B4, 0x9DBC, 0xF6B5, 0x9DC1, 0xF6B6, 0x9DC7,
+	0xF6B7, 0x9DCA, 0xF6B8, 0x9DCF, 0xF6B9, 0x9DBE, 0xF6BA, 0x9DC5,	0xF6BB, 0x9DC3, 0xF6BC, 0x9DBB, 0xF6BD, 0x9DB5, 0xF6BE, 0x9DCE,
+	0xF6BF, 0x9DB9, 0xF6C0, 0x9DBA, 0xF6C1, 0x9DAC, 0xF6C2, 0x9DC8,	0xF6C3, 0x9DB1, 0xF6C4, 0x9DAD, 0xF6C5, 0x9DCC, 0xF6C6, 0x9DB3,
+	0xF6C7, 0x9DCD, 0xF6C8, 0x9DB2, 0xF6C9, 0x9E7A, 0xF6CA, 0x9E9C,	0xF6CB, 0x9EEB, 0xF6CC, 0x9EEE, 0xF6CD, 0x9EED, 0xF6CE, 0x9F1B,
+	0xF6CF, 0x9F18, 0xF6D0, 0x9F1A, 0xF6D1, 0x9F31, 0xF6D2, 0x9F4E,	0xF6D3, 0x9F65, 0xF6D4, 0x9F64, 0xF6D5, 0x9F92, 0xF6D6, 0x4EB9,
+	0xF6D7, 0x56C6, 0xF6D8, 0x56C5, 0xF6D9, 0x56CB, 0xF6DA, 0x5971,	0xF6DB, 0x5B4B, 0xF6DC, 0x5B4C, 0xF6DD, 0x5DD5, 0xF6DE, 0x5DD1,
+	0xF6DF, 0x5EF2, 0xF6E0, 0x6521, 0xF6E1, 0x6520, 0xF6E2, 0x6526,	0xF6E3, 0x6522, 0xF6E4, 0x6B0B, 0xF6E5, 0x6B08, 0xF6E6, 0x6B09,
+	0xF6E7, 0x6C0D, 0xF6E8, 0x7055, 0xF6E9, 0x7056, 0xF6EA, 0x7057,	0xF6EB, 0x7052, 0xF6EC, 0x721E, 0xF6ED, 0x721F, 0xF6EE, 0x72A9,
+	0xF6EF, 0x737F, 0xF6F0, 0x74D8, 0xF6F1, 0x74D5, 0xF6F2, 0x74D9,	0xF6F3, 0x74D7, 0xF6F4, 0x766D, 0xF6F5, 0x76AD, 0xF6F6, 0x7935,
+	0xF6F7, 0x79B4, 0xF6F8, 0x7A70, 0xF6F9, 0x7A71, 0xF6FA, 0x7C57,	0xF6FB, 0x7C5C, 0xF6FC, 0x7C59, 0xF6FD, 0x7C5B, 0xF6FE, 0x7C5A,
+	0xF740, 0x7CF4, 0xF741, 0x7CF1, 0xF742, 0x7E91, 0xF743, 0x7F4F,	0xF744, 0x7F87, 0xF745, 0x81DE, 0xF746, 0x826B, 0xF747, 0x8634,
+	0xF748, 0x8635, 0xF749, 0x8633, 0xF74A, 0x862C, 0xF74B, 0x8632,	0xF74C, 0x8636, 0xF74D, 0x882C, 0xF74E, 0x8828, 0xF74F, 0x8826,
+	0xF750, 0x882A, 0xF751, 0x8825, 0xF752, 0x8971, 0xF753, 0x89BF,	0xF754, 0x89BE, 0xF755, 0x89FB, 0xF756, 0x8B7E, 0xF757, 0x8B84,
+	0xF758, 0x8B82, 0xF759, 0x8B86, 0xF75A, 0x8B85, 0xF75B, 0x8B7F,	0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A,
+	0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97,	0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C,
+	0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F,	0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449,
+	0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A,	0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B,
+	0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C,	0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49,
+	0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19,	0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55,
+	0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44,	0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C,
+	0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D,	0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE,
+	0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC,	0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9,
+	0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5,	0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35,
+	0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B,	0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299,
+	0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D,	0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201,
+	0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525,	0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12,
+	0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A,	0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383,
+	0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66,	0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640,
+	0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B,	0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E,
+	0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973,	0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B,
+	0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98,	0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462,
+	0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E,	0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56,
+	0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20,	0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A,
+	0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59,	0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7,
+	0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8,	0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE,
+	0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2,	0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8,
+	0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2,	0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38,
+	0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F,	0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F,
+	0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D,	0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13,
+	0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060,	0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5,
+	0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A,	0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643,
+	0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B,	0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F,
+	0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD,	0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469,
+	0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747,	0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5,
+	0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66,	0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02,
+	0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06,	0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09,
+	0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0,	0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75,
+	0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8,	0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A,
+	0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8,	0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B,
+	0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B,	0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646,
+	0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A,	0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98,
+	0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3,	0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471,
+	0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F,	0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B,
+	0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12,	0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09,
+	0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A,	0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F,
+	0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3,	0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475,
+	0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71,	0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6,
+	0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065,	0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D,
+	0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9,	0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874,
+	0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64,	0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15,
+	0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E,	0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482,
+	0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68,	0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B,
+	0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7,	0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D,
+	0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E,	0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9,
+	0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7,	0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557,
+	0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A,	0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564,
+	0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561,	0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553,
+	0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B,	0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C,
+	0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E,	0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0
+static const WCHAR uc437[] = {	/*  CP437(U.S.) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0
+static const WCHAR uc720[] = {	/*  CP720(Arabic) to Unicode conversion table */
+	0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+	0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0
+static const WCHAR uc737[] = {	/*  CP737(Greek) to Unicode conversion table */
+	0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+	0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+	0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+	0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0
+static const WCHAR uc771[] = {	/*  CP771(KBL) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0
+static const WCHAR uc775[] = {	/*  CP775(Baltic) to Unicode conversion table */
+	0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+	0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+	0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+	0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0
+static const WCHAR uc850[] = {	/*  CP850(Latin 1) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0
+static const WCHAR uc852[] = {	/*  CP852(Latin 2) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+	0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+	0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0
+static const WCHAR uc855[] = {	/*  CP855(Cyrillic) to Unicode conversion table */
+	0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+	0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+	0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+	0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+	0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0
+static const WCHAR uc857[] = {	/*  CP857(Turkish) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0
+static const WCHAR uc860[] = {	/*  CP860(Portuguese) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2,
+	0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0
+static const WCHAR uc861[] = {	/*  CP861(Icelandic) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0
+static const WCHAR uc862[] = {	/*  CP862(Hebrew) to Unicode conversion table */
+	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0
+static const WCHAR uc863[] = {	/*  CP863(Canadian French) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0,
+	0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192,
+	0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0
+static const WCHAR uc864[] = {	/*  CP864(Arabic) to Unicode conversion table */
+	0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518,
+	0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000,
+	0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5,
+	0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F,
+	0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9,
+	0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9,
+	0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1,
+	0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000
+};
+#endif
+#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0
+static const WCHAR uc865[] = {	/*  CP865(Nordic) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0
+static const WCHAR uc866[] = {	/*  CP866(Russian) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0
+static const WCHAR uc869[] = {	/*  CP869(Greek 2) to Unicode conversion table */
+	0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389,
+	0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF,
+	0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3,
+	0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580,
+	0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384,
+	0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0
+};
+#endif
+
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Static Code Page Configuration with   */
+/* SBCS Fixed Code Page                                                   */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	WCHAR c = 0;
+	const WCHAR* p = CVTBL(uc, FF_CODE_PAGE);
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000 && cp == FF_CODE_PAGE) {	/* Is it in BMP and valid code page? */
+			for (c = 0; c < 0x80 && uni != p[c]; c++) ;
+			c = (c + 0x80) & 0xFF;
+		}
+	}
+
+	return c;
+}
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	WCHAR c = 0;
+	const WCHAR* p = CVTBL(uc, FF_CODE_PAGE);
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		if (cp == FF_CODE_PAGE) {	/* Is it a valid code page? */
+			if (oem < 0x100) c = p[oem - 0x80];
+		}
+	}
+
+	return c;
+}
+
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Static Code Page Configuration with   */
+/* DBCS Fixed Code Page                                                   */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE >= 900
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0, uc;
+	UINT i = 0, n, li, hi;
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000 && cp == FF_CODE_PAGE) {	/* Is it in BMP and valid code page? */
+			uc = (WCHAR)uni;
+			p = CVTBL(uni2oem, FF_CODE_PAGE);
+			hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1;
+			li = 0;
+			for (n = 16; n; n--) {
+				i = li + (hi - li) / 2;
+				if (uc == p[i * 2]) break;
+				if (uc > p[i * 2]) {
+					li = i;
+				} else {
+					hi = i;
+				}
+			}
+			if (n != 0) c = p[i * 2 + 1];
+		}
+	}
+
+	return c;
+}
+
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0;
+	UINT i = 0, n, li, hi;
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		if (cp == FF_CODE_PAGE) {	/* Is it valid code page? */
+			p = CVTBL(oem2uni, FF_CODE_PAGE);
+			hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1;
+			li = 0;
+			for (n = 16; n; n--) {
+				i = li + (hi - li) / 2;
+				if (oem == p[i * 2]) break;
+				if (oem > p[i * 2]) {
+					li = i;
+				} else {
+					hi = i;
+				}
+			}
+			if (n != 0) c = p[i * 2 + 1];
+		}
+	}
+
+	return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Dynamic Code Page Configuration       */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 0
+
+static const WORD cp_code[]          = {  437,   720,   737,   771,   775,   850,   852,   855,   857,   860,   861,   862,   863,   864,   865,   866,   869, 0};
+static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0};
+
+
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0, uc;
+	UINT i, n, li, hi;
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000) { /* Is it in BMP? */
+			uc = (WCHAR)uni;
+			p = 0;
+			if (cp < 900) {	/* SBCS */
+				for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ;		/* Get conversion table */
+				p = cp_table[i];
+				if (p) {	/* Is it valid code page ? */
+					for (c = 0; c < 0x80 && uc != p[c]; c++) ;	/* Find OEM code in the table */
+					c = (c + 0x80) & 0xFF;
+				}
+			} else {	/* DBCS */
+				switch (cp) {	/* Get conversion table */
+				case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break;
+				case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break;
+				case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break;
+				case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break;
+				}
+				if (p) {	/* Is it valid code page? */
+					li = 0;
+					for (n = 16; n; n--) {	/* Find OEM code */
+						i = li + (hi - li) / 2;
+						if (uc == p[i * 2]) break;
+						if (uc > p[i * 2]) {
+							li = i;
+						} else {
+							hi = i;
+						}
+					}
+					if (n != 0) c = p[i * 2 + 1];
+				}
+			}
+		}
+	}
+
+	return c;
+}
+
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted (DBC if >=0x100) */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0;
+	UINT i, n, li, hi;
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		p = 0;
+		if (cp < 900) {	/* SBCS */
+			for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ;		/* Get table */
+			p = cp_table[i];
+			if (p) {	/* Is it a valid CP ? */
+				if (oem < 0x100) c = p[oem - 0x80];
+			}
+		} else {	/* DBCS */
+			switch (cp) {
+			case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break;
+			case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break;
+			case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break;
+			case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break;
+			}
+			if (p) {
+				li = 0;
+				for (n = 16; n; n--) {
+					i = li + (hi - li) / 2;
+					if (oem == p[i * 2]) break;
+					if (oem > p[i * 2]) {
+						li = i;
+					} else {
+						hi = i;
+					}
+				}
+				if (n != 0) c = p[i * 2 + 1];
+			}
+		}
+	}
+
+	return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* Unicode Up-case Conversion                                             */
+/*------------------------------------------------------------------------*/
+
+DWORD ff_wtoupper (	/* Returns up-converted code point */
+	DWORD uni		/* Unicode code point to be up-converted */
+)
+{
+	const WORD* p;
+	WORD uc, bc, nc, cmd;
+	static const WORD cvt1[] = {	/* Compressed up conversion table for U+0000 - U+0FFF */
+		/* Basic Latin */
+		0x0061,0x031A,
+		/* Latin-1 Supplement */
+		0x00E0,0x0317,
+		0x00F8,0x0307,
+		0x00FF,0x0001,0x0178,
+		/* Latin Extended-A */
+		0x0100,0x0130,
+		0x0132,0x0106,
+		0x0139,0x0110,
+		0x014A,0x012E,
+		0x0179,0x0106,
+		/* Latin Extended-B */
+		0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA,
+		0x01CD,0x0110,
+		0x01DD,0x0001,0x018E,
+		0x01DE,0x0112,
+		0x01F3,0x0003,0x01F1,0x01F4,0x01F4,
+		0x01F8,0x0128,
+		0x0222,0x0112,
+		0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241,
+		0x0246,0x010A,
+		/* IPA Extensions */
+		0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7,
+		/* Greek, Coptic */
+		0x037B,0x0003,0x03FD,0x03FE,0x03FF,
+		0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A,
+		0x03B1,0x0311,
+		0x03C2,0x0002,0x03A3,0x03A3,
+		0x03C4,0x0308,
+		0x03CC,0x0003,0x038C,0x038E,0x038F,
+		0x03D8,0x0118,
+		0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA,
+		/* Cyrillic */
+		0x0430,0x0320,
+		0x0450,0x0710,
+		0x0460,0x0122,
+		0x048A,0x0136,
+		0x04C1,0x010E,
+		0x04CF,0x0001,0x04C0,
+		0x04D0,0x0144,
+		/* Armenian */
+		0x0561,0x0426,
+
+		0x0000	/* EOT */
+	};
+	static const WORD cvt2[] = {	/* Compressed up conversion table for U+1000 - U+FFFF */
+		/* Phonetic Extensions */
+		0x1D7D,0x0001,0x2C63,
+		/* Latin Extended Additional */
+		0x1E00,0x0196,
+		0x1EA0,0x015A,
+		/* Greek Extended */
+		0x1F00,0x0608,
+		0x1F10,0x0606,
+		0x1F20,0x0608,
+		0x1F30,0x0608,
+		0x1F40,0x0606,
+		0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F,
+		0x1F60,0x0608,
+		0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB,
+		0x1F80,0x0608,
+		0x1F90,0x0608,
+		0x1FA0,0x0608,
+		0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC,
+		0x1FCC,0x0001,0x1FC3,
+		0x1FD0,0x0602,
+		0x1FE0,0x0602,
+		0x1FE5,0x0001,0x1FEC,
+		0x1FF3,0x0001,0x1FFC,
+		/* Letterlike Symbols */
+		0x214E,0x0001,0x2132,
+		/* Number forms */
+		0x2170,0x0210,
+		0x2184,0x0001,0x2183,
+		/* Enclosed Alphanumerics */
+		0x24D0,0x051A,
+		0x2C30,0x042F,
+		/* Latin Extended-C */
+		0x2C60,0x0102,
+		0x2C67,0x0106, 0x2C75,0x0102,
+		/* Coptic */
+		0x2C80,0x0164,
+		/* Georgian Supplement */
+		0x2D00,0x0826,
+		/* Full-width */
+		0xFF41,0x031A,
+
+		0x0000	/* EOT */
+	};
+
+
+	if (uni < 0x10000) {	/* Is it in BMP? */
+		uc = (WORD)uni;
+		p = uc < 0x1000 ? cvt1 : cvt2;
+		for (;;) {
+			bc = *p++;								/* Get the block base */
+			if (bc == 0 || uc < bc) break;			/* Not matched? */
+			nc = *p++; cmd = nc >> 8; nc &= 0xFF;	/* Get processing command and block size */
+			if (uc < bc + nc) {	/* In the block? */
+				switch (cmd) {
+				case 0:	uc = p[uc - bc]; break;		/* Table conversion */
+				case 1:	uc -= (uc - bc) & 1; break;	/* Case pairs */
+				case 2: uc -= 16; break;			/* Shift -16 */
+				case 3:	uc -= 32; break;			/* Shift -32 */
+				case 4:	uc -= 48; break;			/* Shift -48 */
+				case 5:	uc -= 26; break;			/* Shift -26 */
+				case 6:	uc += 8; break;				/* Shift +8 */
+				case 7: uc -= 80; break;			/* Shift -80 */
+				case 8:	uc -= 0x1C60; break;		/* Shift -0x1C60 */
+				}
+				break;
+			}
+			if (cmd == 0) p += nc;	/* Skip table if needed */
+		}
+		uni = uc;
+	}
+
+	return uni;
+}
+
+
+#endif /* #if FF_USE_LFN != 0 */
diff --git a/MCUME_pico2/ffconf.h b/MCUME_pico2/ffconf.h
new file mode 100644
index 0000000..2e86af1
--- /dev/null
+++ b/MCUME_pico2/ffconf.h
@@ -0,0 +1,296 @@
+/*---------------------------------------------------------------------------/
+/  Configurations of FatFs Module
+/---------------------------------------------------------------------------*/
+
+#define FFCONF_DEF	80286	/* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_READONLY	0
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE	0
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: Basic functions are fully enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+
+#define FF_USE_FIND		1
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+
+#define FF_USE_MKFS		0
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FASTSEEK	1
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND	0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_CHMOD	0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL	0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD	0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_STRFUNC	1
+#define FF_PRINT_LLI	1
+#define FF_PRINT_FLOAT	1
+#define FF_STRF_ENCODE	3
+/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/   0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect.
+/   1: Enable without LF-CRLF conversion.
+/   2: Enable with LF-CRLF conversion.
+/
+/  FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2
+/  makes f_printf() support floating point argument. These features want C99 or later.
+/  When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character
+/  encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE
+/  to be read/written via those functions.
+/
+/   0: ANSI/OEM in current CP
+/   1: Unicode in UTF-16LE
+/   2: Unicode in UTF-16BE
+/   3: Unicode in UTF-8
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE	932
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect code page setting can cause a file open failure.
+/
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+/     0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#define FF_USE_LFN		1
+#define FF_MAX_LFN		255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/   0: Disable LFN. FF_MAX_LFN has no effect.
+/   1: Enable LFN with static  working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/  requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/  additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/  The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/  be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
+/  specification.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE	0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/   0: ANSI/OEM in current CP (TCHAR = char)
+/   1: Unicode in UTF-16 (TCHAR = WCHAR)
+/   2: Unicode in UTF-8 (TCHAR = char)
+/   3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/  Also behavior of string I/O functions will be affected by this option.
+/  When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF		255
+#define FF_SFN_BUF		12
+/* This set of options defines size of file name members in the FILINFO structure
+/  which is used to read out directory items. These values should be suffcient for
+/  the file names to read. The maximum possible length of the read file name depends
+/  on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_FS_RPATH		0
+/* This option configures support for relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_VOLUMES		2
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID	0
+#define FF_VOLUME_STRS		"RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/  When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/  number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/  logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/  characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/  compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/  not defined, a user defined volume string table is needed as:
+/
+/  const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+*/
+
+
+#define FF_MULTI_PARTITION	0
+/* This option switches support for multiple volumes on the physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When this function is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  function will be available. */
+
+
+#define FF_MIN_SS		512
+#define FF_MAX_SS		512
+/* This set of options configures the range of sector size to be supported. (512,
+/  1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/  harddisk, but a larger value may be required for on-board flash memory and some
+/  type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/  for variable sector size mode and disk_ioctl() function needs to implement
+/  GET_SECTOR_SIZE command. */
+
+
+#define FF_LBA64		0
+/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
+/  To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
+
+
+#define FF_MIN_GPT		0x10000000
+/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
+/  f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
+
+
+#define FF_USE_TRIM		0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY		0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#define FF_FS_EXFAT		1
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/  To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
+/  Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC	1
+#define FF_NORTC_MON	1
+#define FF_NORTC_MDAY	1
+#define FF_NORTC_YEAR	2022
+/* The option FF_FS_NORTC switches timestamp feature. If the system does not have
+/  an RTC or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable the
+/  timestamp feature. Every object modified by FatFs will have a fixed timestamp
+/  defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/  To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to read current time form real-time clock. FF_NORTC_MON,
+/  FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/  These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_NOFSINFO	0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at the first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+#define FF_FS_LOCK		0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+
+#define FF_FS_REENTRANT	0
+#define FF_FS_TIMEOUT	1000
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this featuer.
+/
+/   0: Disable re-entrancy. FF_FS_TIMEOUT have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_mutex_create(), ff_mutex_delete(), ff_mutex_take() and ff_mutex_give()
+/      function, must be added to the project. Samples are available in ffsystem.c.
+/
+/  The FF_FS_TIMEOUT defines timeout period in unit of O/S time tick.
+*/
+
+
+
+/*--- End of configuration options ---*/
diff --git a/MCUME_pico2/flash/flash_t.c b/MCUME_pico2/flash/flash_t.c
new file mode 100644
index 0000000..88342fe
--- /dev/null
+++ b/MCUME_pico2/flash/flash_t.c
@@ -0,0 +1,66 @@
+/*
+  RP2350 flash driver
+*/
+
+#include "flash_t.h"
+
+#include "hardware/flash.h"
+#include "hardware/sync.h"
+#include "emuapi.h"
+
+
+unsigned char * flash_start = (unsigned char *)(XIP_BASE + HW_FLASH_STORAGE_BASE);
+unsigned char * flash_end = (unsigned char *)(XIP_BASE + HW_FLASH_STORAGE_TOP);
+
+static uint8_t cache[FLASH_SECTOR_SIZE];
+
+int flash_load(const char * filename) 
+{
+  uint32_t offset = HW_FLASH_STORAGE_BASE;
+  int n;
+  int size = 0;
+  emu_printf("flash_load...");
+  int f = emu_FileOpen(filename,"r+b");
+  if (f) {
+    while ( (offset < (HW_FLASH_STORAGE_TOP-FLASH_SECTOR_SIZE)) && (n = emu_FileRead(cache,FLASH_SECTOR_SIZE,f) ) ) {
+      //memcpy(cache, (unsigned char *)offset, n);
+      uint32_t ints = save_and_disable_interrupts();   
+      flash_range_erase(offset, FLASH_SECTOR_SIZE);
+      flash_range_program(offset, (const uint8_t *)&cache[0], FLASH_SECTOR_SIZE);
+      restore_interrupts(ints);      
+      emu_printi(n);
+      emu_printi(offset);          
+      //uint8_t * pt = (uint8_t*)(XIP_BASE + offset);
+      //emu_printi(pt[0]);
+      //emu_printi(pt[1]);
+      //emu_printi(pt[2]);
+      //emu_printi(pt[3]);
+      offset += FLASH_SECTOR_SIZE;
+      size += n;          
+    }
+    emu_FileClose(f);
+    emu_printf("flash_load OK.");    
+  }
+
+  return size;
+}
+
+int flash_verify(unsigned char * buf, int size)
+{
+  unsigned char * datapt = (unsigned char *)(XIP_BASE + HW_FLASH_STORAGE_BASE);
+  emu_printf("flash_verify...");
+  int count = size;
+  while (count++ < size) {
+    if (*datapt != *buf) {
+      emu_printf("mismatch at ");
+      emu_printi(count);
+      emu_printi(*datapt);
+      emu_printi(*buf);
+      return 1;
+    }  
+    datapt++;
+    buf++; 
+  }  
+  emu_printf("flash_verify OK.");
+  return 0;
+}
\ No newline at end of file
diff --git a/MCUME_pico2/flash/flash_t.h b/MCUME_pico2/flash/flash_t.h
new file mode 100644
index 0000000..92daa95
--- /dev/null
+++ b/MCUME_pico2/flash/flash_t.h
@@ -0,0 +1,37 @@
+/*
+  RP2350 flash driver
+*/
+
+#ifndef _FLASH_T_H_
+#define _FLASH_T_H_
+
+
+#include "pico.h"
+#include "pico/stdlib.h"
+#include "platform_config.h"
+
+#define FLASH_SECTOR_SIZE       4096 
+#define HW_FLASH_STORAGE_TOP   (0x400000) // Pico2 = 4MB flash
+#ifdef FLASH_STORE_START
+#define HW_FLASH_STORAGE_BASE  (FLASH_STORE_START)
+#else
+#define HW_FLASH_STORAGE_BASE  (0x200000) // Start at 2MB default
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+extern unsigned char * flash_start;
+extern unsigned char * flash_end;
+extern int flash_load(const char * filename);
+extern int flash_verify(unsigned char * buf,int size);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/MCUME_pico2/pico20/IC.cpp b/MCUME_pico2/pico20/IC.cpp
new file mode 100644
index 0000000..3687bef
--- /dev/null
+++ b/MCUME_pico2/pico20/IC.cpp
@@ -0,0 +1,21 @@
+#include "IC.h"
+
+IC::IC() : cycles(0) {
+
+}
+
+IC::~IC() {
+
+}
+
+uint32_t IC::getCycles() {
+	return this->cycles;
+}
+
+uint32_t IC::getClockSpeed() {
+	return this->clockSpeed;
+}
+
+void IC::setClockSpeed(uint32_t clock) {
+	this->clockSpeed = clock;
+}
\ No newline at end of file
diff --git a/MCUME_pico2/pico20/IC.h b/MCUME_pico2/pico20/IC.h
new file mode 100644
index 0000000..9bc0766
--- /dev/null
+++ b/MCUME_pico2/pico20/IC.h
@@ -0,0 +1,28 @@
+#ifndef _H_IC
+#define _H_IC
+
+#include <stdint.h>
+
+/*
+Simple base class for integrated circuits.
+*/
+class IC {
+public:
+	IC();
+	~IC();
+
+	// Getters
+	uint32_t getCycles();
+	uint32_t getClockSpeed();
+
+	// Setters
+	void setClockSpeed(uint32_t clock);
+protected:
+	// Derived classes handle incrementing this counter
+	uint32_t cycles;
+
+	// Determines the maximum frequenzy an IC can operate in hertz
+	uint32_t clockSpeed;
+};
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico20/MOS6502Memory.h b/MCUME_pico2/pico20/MOS6502Memory.h
new file mode 100644
index 0000000..71a274e
--- /dev/null
+++ b/MCUME_pico2/pico20/MOS6502Memory.h
@@ -0,0 +1,20 @@
+#ifndef _H_MOS6502MEMORY
+#define _H_MOS6502MEMORY
+
+#include <stdint.h>
+
+extern uint8_t vicmemory[];
+
+
+#define readWord(location) (vicmemory[location])
+#define writeWord(location,value) {vicmemory[location]=value;}
+//extern  uint8_t readWord( uint16_t location);
+//extern  void writeWord( uint16_t location, uint8_t value);
+
+#define silentReadWord(location) (vicmemory[location])
+#define silentWriteWord(location,value) {vicmemory[location]=value;}
+#define silentReadDWord(location) (vicmemory[location] | vicmemory[location + 1] << 8)
+#define silentWriteDWord(location,value) {vicmemory[location]=uint8_t(value & 0xFF); vicmemory[location + 1]=(uint8_t)((value >> 8) & 0xFF);}
+
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico20/MOS6522.cpp b/MCUME_pico2/pico20/MOS6522.cpp
new file mode 100644
index 0000000..39510d0
--- /dev/null
+++ b/MCUME_pico2/pico20/MOS6522.cpp
@@ -0,0 +1,183 @@
+#include "MOS6522.h"
+#include "MOS6502Memory.h"
+
+MOS6522::MOS6522() : IC()
+					, keyPressed(0)
+					, shiftPressed(false)
+					, cbmPressed(false) {
+	// Set clock speed
+	this->setClockSpeed(2000000);
+}
+
+MOS6522::~MOS6522() {
+
+}
+
+
+void MOS6522::setCpu(mos6502 *omos6502) {
+	this->omos6502 = omos6502;
+}
+
+void MOS6522::setKeyPressed(uint16_t key) {
+	/* Store high byte first 
+		= 0x9120 << 8 | 0x9121
+	*/
+	keyPressed = key;
+}
+
+void MOS6522::setShiftPressed(bool state) {
+	this->shiftPressed = state;
+}
+
+void MOS6522::setCbmPressed(bool state) {
+	this->cbmPressed = state;
+}
+
+void MOS6522::setJoyStickPressed(Vic20JoyStickButton button, bool state) {
+	this->joyStick[button] = state;
+}
+
+void MOS6522::initialize() {
+	// Clear joystick memory
+	writeWord(0x9111, 0xFF);
+}
+
+void MOS6522::tick() {
+	// Tick timer cycle
+	this->tickTimers();
+
+	// Handle input in this cycle
+	this->joy1Input();
+	this->joy2Input();
+	this->keyboardInput();
+
+	// Increment cycles counter
+	this->cycles += 1;
+}
+
+
+void MOS6522::joy1Input() {
+	// Handle joystick input on VIA1
+	uint8_t via1PortAValue = silentReadWord(via1PORTA);
+    via1PortAValue |= 0x3c;
+	if (joyStick[Vic20JoyStickButton::Fire]) {
+		via1PortAValue &= ~0x20;
+	}
+
+	if (joyStick[Vic20JoyStickButton::Up]) {
+		via1PortAValue &= ~0x04;
+	}
+
+	if (joyStick[Vic20JoyStickButton::Down]) {
+		via1PortAValue &= ~0x08;
+	}
+
+	if (joyStick[Vic20JoyStickButton::Left]) {
+		via1PortAValue &= ~0x10;
+	}
+	silentWriteWord(via1PORTA, via1PortAValue);
+	silentWriteWord(via1PORTAMIRROR, via1PortAValue);
+}
+
+void MOS6522::joy2Input() {
+	uint8_t via2PortBValue = silentReadWord(this->via2PORTB);	
+	// If this bit is input, set it to default value, else leave it as it is so it won't mess up keyboard input
+	if (!(silentReadWord(via2PortBDDR) & 0x80)) {
+		via2PortBValue |= 0x80;
+	}
+	// Joystick RIGHT ison VIA 2 
+	if (joyStick[Vic20JoyStickButton::Right]) {
+		via2PortBValue &= ~0x80;
+	}
+	silentWriteWord(via2PORTB, via2PortBValue);
+}
+
+void MOS6522::keyboardInput() {
+	uint8_t via2PortAValue = silentReadWord(this->via2PORTA);
+	uint8_t via2PortBValue = silentReadWord(this->via2PORTB);	
+
+	// Get row and column of key press
+	uint8_t column = (keyPressed >> 8) & 0xFF; // output
+	uint8_t row = keyPressed & 0xFF; //input
+
+	// Check whether keyboard should be scanned
+	if (via2PortBValue == 0) {
+		// If port b is 0 then the vic is asking whether any keys are pressed on the keyboard
+		via2PortAValue = keyPressed == 0 ? 0xFF : row;
+	}
+	else {
+		// Return keyboard row depending on column state
+		via2PortAValue = (via2PortBValue == column ? (row == 0 ? 0xFF : row) : 0xFF);
+	}
+
+	if ((via2PortBValue == 0xF7) && shiftPressed) {
+		// Return row of shift key
+		via2PortAValue = 0xFD & (keyPressed == 0 ? 0xFF : (column == 0xF7 ? row : 0xFF));
+	} else if (via2PortBValue == 0xDF && cbmPressed) {
+		// Return row of cbm key
+		via2PortAValue = 0xFE & (keyPressed == 0 ? 0xFF : (column == 0xDF ? row : 0xFF));
+	}
+
+	silentWriteWord(this->via2PORTA, via2PortAValue);
+	silentWriteWord(this->via2PORTAMIRROR, via2PortAValue);	
+}
+
+void MOS6522::tickTimers() {
+	// Grab values of timer related registers
+	uint8_t interruptEnable = readWord(this->irqEnableAddress);
+	uint8_t interruptFlags = readWord(this->irqFlagsAddress);
+
+	// Get timer values
+	uint16_t timer1 = silentReadDWord(this->via2timer1DAddress);
+	uint16_t timer2 = silentReadDWord(this->via1timer2DAddress);
+	// If timer1 is active, decrement it
+	if (timer1 > 0) {
+		silentWriteDWord(this->via2timer1DAddress, --timer1);
+	}
+	if (timer1 == 0) {
+		// Set interrupt flag
+		interruptFlags |= 0x40;
+		silentWriteWord(this->irqFlagsAddress, interruptFlags);
+	}
+
+	// If timer2 is active and no latch, decrement it
+	if (silentReadWord(this->via2timer2HighByteLatch) != 0) {
+		if (timer2 > 0) {
+			silentWriteDWord(this->via1timer2DAddress, --timer2);
+		}
+		if (timer2 == 0) {
+			// Reset high byte latch
+			silentWriteDWord(this->via1timer2DAddress, silentReadDWord(this->via2timer2LowByteLatch));
+			silentWriteDWord(this->via2timer2HighByteLatch, 0);
+			// Set interrupt flag
+			interruptFlags |= 0x20;
+			silentWriteWord(this->irqFlagsAddress, interruptFlags);
+		}
+	}
+
+	// Check if an interrupt request exists in the system
+	if (interruptFlags & interruptEnable & 0x7F) {
+		// Send an interrupt request to the cpu
+		//if (omos6502->interrupt()) {
+		if (omos6502->IRQ()) {
+			uint8_t auxControl = readWord(this->auxControlAddress);
+			// Post interrupt operation
+			if (interruptFlags & 0x40) {
+				// Determine what to do with timer based on auxiliary control register
+				if (auxControl & 0x40) {
+					// Continuous interrupt
+					silentWriteDWord(this->via2timer1DAddress, silentReadDWord(this->via2timer1LowByteLatch));
+				}
+				// Reset interrupt flag
+				interruptFlags  &= ~0x40;
+				silentWriteWord(irqFlagsAddress, interruptFlags);
+			}
+
+			if (interruptFlags & 0x20) {
+				// Reset interrupt flag
+				interruptFlags  &= ~0x20;
+				silentWriteWord(irqFlagsAddress, interruptFlags);
+			}
+		}
+	}
+}
diff --git a/MCUME_pico2/pico20/MOS6522.h b/MCUME_pico2/pico20/MOS6522.h
new file mode 100644
index 0000000..4d0437f
--- /dev/null
+++ b/MCUME_pico2/pico20/MOS6522.h
@@ -0,0 +1,101 @@
+#ifndef _H_MOS6522
+#define _H_MOS6522
+
+#include "IC.h"
+#include "mos6502.h"
+
+/*
+Notes,
+This single object will serve as emulation 
+for both VIA chips in the VIC-20.
+
+References,
+http://vic-20.appspot.com/docs/viausage.txt
+http://vic-20.appspot.com/docs/vickey.txt
+*/
+class MOS6522 : public IC {
+public:
+	MOS6522();
+	~MOS6522();
+
+	// Joystick 
+	enum Vic20JoyStickButton { Fire = 0, Up = 1, Down = 2, Left = 3, Right = 4 };
+
+	// Via joystick interface
+	void setJoyStickPressed(Vic20JoyStickButton button, bool state);
+
+	// Via 2 Keyboard interface
+	void setKeyPressed(uint16_t key);
+	void setShiftPressed(bool state);
+	void setCbmPressed(bool state);
+
+	// Interface
+	void tick();
+	// Organize operations into separate methods for cleaner code
+	void tickTimers();
+	void joy1Input();
+	void joy2Input();
+	void keyboardInput();	
+	void setCpu(mos6502 *omos6502);
+	void initialize();
+
+private:
+
+	// Cpu reference
+	mos6502 *omos6502;
+
+	// Via 1 & 2 Joystick
+	bool joyStick[5];
+
+	// Via 2 Keyboard 
+	uint16_t keyPressed;
+	bool shiftPressed;
+	bool cbmPressed; 
+
+	// VIA 1 Joystick addresses
+	static const uint16_t via1PORTB = 0x9110;
+	static const uint16_t via1PORTA = 0x9111;
+	static const uint16_t via1PORTAMIRROR = 0x911F;
+
+    // Port A
+	static const uint8_t joyStickUpBit = 0x2;
+	static const uint8_t joyStickDownBit = 0x4;
+	static const uint8_t joyStickLeftBit = 0x8;
+	static const uint8_t joyStickFireBit = 0x10;
+
+	// VIA 1 ddrs
+	static const uint16_t via1PortBDDR = 0x9112;
+	static const uint16_t via1PortADDR = 0x9113;
+
+	// VIA 1 Timer
+	static const uint16_t via1timer2DAddress = 0x9118; 	//and 0x9119
+
+
+	// Via 2 Keyboard addresses + joystick right
+	static const uint16_t via2PORTB = 0x9120;
+	static const uint16_t via2PORTA = 0x9121;
+	static const uint16_t via2PORTAMIRROR = 0x912F;
+    
+    // Port B
+	static const uint8_t joyStickRightBit = 0x80;
+
+	// VIA 2 ddrs
+	static const uint16_t via2PortBDDR = 0x9122; 
+	static const uint16_t via2PortADDR = 0x9123;
+
+	// VIA 2 Timer
+	static const uint16_t via2timer1LowByteLatch = 0x9124;
+	static const uint16_t via2timer1HighByteLatch = 0x9125;
+	static const uint16_t via2timer1DAddress = 0x9126;	//and 0x9127
+	static const uint16_t via2timer2LowByteLatch = 0x9128;
+	static const uint16_t via2timer2HighByteLatch = 0x9129;
+
+
+
+	// Via 2 Registers
+	static const uint16_t auxControlAddress = 0x912B;
+	static const uint16_t irqFlagsAddress = 0x912D;
+	static const uint16_t irqEnableAddress = 0x912E;
+};
+
+#endif
diff --git a/MCUME_pico2/pico20/MOS6561.cpp b/MCUME_pico2/pico20/MOS6561.cpp
new file mode 100644
index 0000000..54941a4
--- /dev/null
+++ b/MCUME_pico2/pico20/MOS6561.cpp
@@ -0,0 +1,321 @@
+#include "MOS6561.h"
+
+extern "C" {
+#include "emuapi.h"
+#include "platform_config.h"
+}
+
+#include "pico_dsp.h"
+typedef uint16_t Pixel;
+
+#define WIN_W TFT_WIDTH
+#define WIN_H TFT_HEIGHT
+
+
+// definitions for easy access to registers
+#define REG_COLPAGE_BASE      (0x9400) // 0x9400+0x200 = 0x9600 unexpanded
+
+#define REG_SCRPAGE_LO        ((readWord(0x9002) & 0x80)<< 2) // 0x0200
+#define REG_COLPAGE_LO        ((readWord(0x9002) & 0x80)<< 2) // 0x0200
+#define REG_NB_COLUMNS        (readWord(0x9002) & 0x7F)
+
+#define REG_RASTER_LO_RD      (0x9003) // 0x80 >> 7
+#define REG_DOUBLE_HEIGHT     (readWord(0x9003) & 0x01)
+#define REG_NB_ROWS           ((readWord(0x9003) & 0x7E) >> 1) //x2 => 46
+
+#define REG_RASTER_HI_RD      (0x9004) // << 1 // 1E00 unexpanded?
+
+#define REG_CHRMAP_PT         (readWord(0x9005) & 0x0F)
+#define REG_SCRPAGE_HIGH      ((readWord(0x9005) & 0xF0) << 6) // 0x2C00
+
+#define REG_AUXILIARY_COLOUR  ((readWord(0x900E) & 0xF0) >> 4)
+#define REG_BORDER_COLOUR     (readWord(0x900F) & 0x7)
+#define REG_BACKGROUND_COLOUR ((readWord(0x900F) & 0xF0) >> 4)
+
+#define REG_HORI_OFFSET       ((readWord(0x9000) & 0x7F) 
+#define REG_VERT_OFFSET       ((readWord(0x9001) & 0xFF) 
+
+// C  R  H  V
+// 16 16 +6 +16
+// 22 23 0  0
+// 24 28 -3 -9
+// 25 30 -3 -12
+// 27 33 -5 -19
+
+
+static Pixel vicPalette[16];
+static uint16_t remap[16] = {
+  0x8000,
+  0x8400,
+  0x8800,
+  0x8c00,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x0000,
+  0x1000,
+  0x1400,
+  0x1800,
+  0x1c00
+};
+
+static Pixel linebuf[WIN_W];
+
+MOS6561::MOS6561() : IC(), curRow(0), frameReady(true) {
+	// Set clock speed
+	this->setClockSpeed(1108000);
+}
+
+MOS6561::~MOS6561() {
+}
+
+void MOS6561::initialize() {
+	// Initialize VIC palette
+	vicPalette[0] = RGBVAL16(0, 0, 0);
+	vicPalette[1] = RGBVAL16(255, 255, 255);
+	vicPalette[2] = RGBVAL16((182), (31), (33));
+	vicPalette[3] = RGBVAL16((77), (240), (255));
+	vicPalette[4] = RGBVAL16((180), (63), (255));
+	vicPalette[5] = RGBVAL16((68), (226), (55));
+	vicPalette[6] = RGBVAL16((15), (87), (247));
+	vicPalette[7] = RGBVAL16((220), (215), (27));
+	vicPalette[8] = RGBVAL16((202), (84), (0));
+	vicPalette[9] = RGBVAL16((233), (176), (114));
+	vicPalette[10] = RGBVAL16((231), (146), (147));
+	vicPalette[11] = RGBVAL16((154), (247), (253)); 
+	vicPalette[12] = RGBVAL16((224), (159), (255));
+	vicPalette[13] = RGBVAL16((143), (228), (147));
+	vicPalette[14] = RGBVAL16((130), (144), (255));
+	vicPalette[15] = RGBVAL16((229), (222), (133));
+}
+
+
+void MOS6561::renderBorder(uint16_t raster){
+	if (raster < WIN_H) {
+		Pixel  bcol = vicPalette[REG_BORDER_COLOUR];
+		Pixel * dst = &linebuf[0];
+		for (int x=0; x < WIN_W; x++) {
+		  *dst++ = bcol;
+		}
+		emu_DrawLine16(&linebuf[0], WIN_W, WIN_H, raster);
+	}
+}
+
+
+void MOS6561::renderLine(uint16_t raster, uint16_t row, uint8_t rowHeight, uint8_t chrLine) {
+	int curRow = row;
+	int nbRow = REG_NB_ROWS;
+
+	if ( (rowHeight == 16) && (nbRow >= 23) ) {
+		curRow = curRow/2;
+		nbRow = nbRow/2;    
+	}
+
+	if (raster < WIN_H) 
+	{
+		int nbCol = REG_NB_COLUMNS;
+		int bWidth = (WIN_W - nbCol*8)/2;
+		#define bakcol 0
+		#define borcol 1
+		#define forcol 2
+		#define auxcol 3
+		Pixel cols[4];
+		uint16_t screenPage = (REG_SCRPAGE_HIGH & ~0x2000) + REG_SCRPAGE_LO;
+		uint8_t * charPointer = &vicmemory[screenPage + (curRow * nbCol)];
+		uint16_t colourPage = REG_COLPAGE_BASE + REG_COLPAGE_LO;
+		uint8_t * colPointer = &vicmemory[colourPage + (curRow * nbCol)];
+
+		cols[borcol] = vicPalette[REG_BORDER_COLOUR];
+		cols[bakcol] = vicPalette[REG_BACKGROUND_COLOUR];
+
+		// Border Left
+		Pixel * dst = &linebuf[0];
+		for (int x=0; x < bWidth; x++) {
+		  *dst++ = cols[borcol];
+		}
+
+		uint16_t chardefbase = remap[REG_CHRMAP_PT];
+		for (int x = 0; x < nbCol; x +=1) 
+		{
+			uint16_t charpt = chardefbase + charPointer[x]*rowHeight + chrLine;
+			if ( (charpt > 0x2000) && (charpt < 0x3000) )
+			  charpt += 0x6000;
+		  uint8_t characterByte = vicmemory[charpt];
+		  uint8_t colour = colPointer[x] & 0x7;
+		  uint8_t multiColour = colPointer[x] & 0x8;
+		  cols[forcol] = vicPalette[colour];	  
+		  if (!multiColour) {
+			Pixel * dest = dst;
+			for (int a = 0; a < 8; a++) {
+			  if ((characterByte << a) & 0x80) {
+				*dest++ = cols[forcol];
+			  }
+			  else {
+				*dest++ = cols[bakcol];
+			  }
+			}
+		  }
+		  else {
+			Pixel * dest = dst;
+			cols[auxcol] = vicPalette[REG_AUXILIARY_COLOUR];	  
+			for (int a = 0; a < 8; a += 2) {
+				// Set colour
+				Pixel col = cols[((characterByte << a) & 0xC0) >> 6];
+				*dest++ = col;
+				*dest++ = col;
+			}
+		  }
+		  dst +=8;
+		}
+
+		// Border Right
+		for (int x=0; x < bWidth; x++) {
+		  *dst++ = cols[borcol];
+		} 
+		emu_DrawLine16(&linebuf[0], WIN_W, 1, raster);     
+	}  
+}
+  
+void MOS6561::renderRow(uint16_t raster, uint16_t row, uint8_t rowHeight) 
+{
+	int curRow = row;
+	int nbRow = REG_NB_ROWS;
+
+	//printf("rows %d of %d, cols=%d, rowHeight:%d\n", curRow, nbRow, nbCol, rowHeight);
+
+	if ( (rowHeight == 16) && (nbRow >= 23) ) {
+		curRow = curRow/2;
+		nbRow = nbRow/2;    
+	}
+
+	if ((raster+curRow*rowHeight) < WIN_H) 
+	{
+		int nbCol = REG_NB_COLUMNS;
+		int bWidth = (WIN_W - nbCol*8)/2;
+		#define bakcol 0
+		#define borcol 1
+		#define forcol 2
+		#define auxcol 3
+		Pixel cols[4];
+		uint16_t screenPage = (REG_SCRPAGE_HIGH & ~0x2000) + REG_SCRPAGE_LO;
+		uint8_t * charPointer = &vicmemory[screenPage + (curRow * nbCol)];
+		uint16_t colourPage = REG_COLPAGE_BASE + REG_COLPAGE_LO;
+		uint8_t * colPointer = &vicmemory[colourPage + (curRow * nbCol)];
+
+		cols[borcol] = vicPalette[REG_BORDER_COLOUR];
+		cols[bakcol] = vicPalette[REG_BACKGROUND_COLOUR];
+
+		for (int line=0; line < rowHeight; line++) {
+			// Border Left
+			Pixel *  dst = &linebuf[0];
+			for (int x=0; x < bWidth; x++) {
+			  *dst++ = cols[borcol];
+			}
+
+			uint16_t chardefbase = remap[REG_CHRMAP_PT];
+			for (int x = 0; x < nbCol; x +=1) 
+			{
+				uint16_t charpt = chardefbase + charPointer[x]*rowHeight + line;
+				if ( (charpt > 0x2000) && (charpt < 0x3000) )
+				  charpt += 0x6000;
+			  uint8_t characterByte = vicmemory[charpt];
+			  uint8_t colour = colPointer[x] & 0x7;
+			  uint8_t multiColour = colPointer[x] & 0x8;
+			  cols[forcol] = vicPalette[colour];	  
+			  if (!multiColour) {
+					Pixel * dest = dst;
+					for (int a = 0; a < 8; a++) {
+					  if ((characterByte << a) & 0x80) {
+							*dest++ = cols[forcol];
+					  }
+					  else {
+							*dest++ = cols[bakcol];
+					  }
+					}
+			  }
+			  else {
+					Pixel * dest = dst;
+					cols[auxcol] = vicPalette[REG_AUXILIARY_COLOUR];	  
+					for (int a = 0; a < 8; a += 2) {
+						// Set colour
+						Pixel col = cols[((characterByte << a) & 0xC0) >> 6];
+						*dest++ = col;
+						*dest++ = col;
+					}
+			  }
+			  dst +=8;
+			}
+
+			// Border Right
+			for (int x=0; x < bWidth; x++) {
+			  *dst++ = cols[borcol];
+			}
+			emu_DrawLine16(&linebuf[0], WIN_W, 1, curRow*rowHeight+line+raster);      
+		}
+	}  
+}
+
+
+void MOS6561::renderFrame() {
+	this->frameReady = false;
+}
+
+bool MOS6561::isFrameReady() {
+	return this->frameReady;
+}
+
+
+void MOS6561::tick(int nbcycles) {
+	// Increment raster counter 
+	uint16_t raster = readWord(REG_RASTER_HI_RD) << 1 | readWord(REG_RASTER_LO_RD) >> 7;
+	if (cycles % cyclesPerScanline == 0) {
+		uint8_t rowHeight = (REG_DOUBLE_HEIGHT?16:8);
+		if (raster <= lastScanline) {
+			raster += 1;
+		}
+		else {
+			raster = 0;	
+			visScanlines = REG_NB_ROWS * rowHeight;
+			if ( (rowHeight == 16) && (REG_NB_ROWS >= 23) ) {
+				visScanlines = REG_NB_ROWS * 8;
+			}
+			firstVisibleScanline = (WIN_H-visScanlines)/2;
+		}
+		writeWord(REG_RASTER_LO_RD, (raster & 0x1) << 7 | (readWord(REG_RASTER_LO_RD) & 0x7F));
+		writeWord(REG_RASTER_HI_RD, raster >> 1);
+	
+		if (visScanlines) {
+			if (raster < firstVisibleScanline) {
+				renderBorder(raster);
+			}
+			// If not blanking, update screen
+			else if (raster >= firstVisibleScanline && raster < (firstVisibleScanline+visScanlines)) {
+				// Update video  
+				uint8_t chrLine = (raster-firstVisibleScanline) % rowHeight;
+				//renderLine(raster, this->curRow, rowHeight, chrLine);
+				if (chrLine == rowHeight-1) {				
+					renderRow(firstVisibleScanline, this->curRow, rowHeight);
+					this->curRow++;
+					// End of screen reached
+					if (this->curRow >= REG_NB_ROWS) {
+						this->curRow = 0;
+						frameReady = true;
+					}
+				}
+			}
+			else {
+				renderBorder(raster);
+			}
+		}
+	}
+
+	// Increment cycle counter
+	this->cycles += nbcycles;
+}
+
+
+
diff --git a/MCUME_pico2/pico20/MOS6561.h b/MCUME_pico2/pico20/MOS6561.h
new file mode 100644
index 0000000..03bb781
--- /dev/null
+++ b/MCUME_pico2/pico20/MOS6561.h
@@ -0,0 +1,51 @@
+#ifndef _H_MOS6561
+#define	_H_MOS6561
+
+#include <stdint.h>
+
+#include "IC.h"
+#include "MOS6502Memory.h"
+
+/*
+References, 
+http://vic-20.appspot.com/docs/6561.txt
+http://vic-20.appspot.com/docs/vicregs.txt
+http://vic-20.appspot.com/docs/6561help.txt
+*/
+
+class MOS6561 : public IC {
+public:
+	MOS6561();
+	~MOS6561();
+
+	// Interface
+	void tick(int cycles);
+	void initialize();
+
+	// Getters, mostly depend on memory
+	bool isFrameReady();
+	void renderFrame();
+	void renderBorder(uint16_t raster);
+	void renderRow(uint16_t raster, uint16_t row, uint8_t rowHeight);
+	void renderLine(uint16_t raster, uint16_t row, uint8_t rowHeight, uint8_t chrLine);
+private:
+	// Used as counters
+	uint8_t curRow;
+	uint16_t firstVisibleScanline;
+	uint16_t visScanlines;
+
+	// Determines if a full frame has been drawn
+	bool frameReady;
+	
+	static const uint16_t lastScanline = 312;
+public:
+	static const int cyclesPerScanline = 71;
+	
+	static const uint16_t Audio1Register = 0x900A;
+	static const uint16_t Audio2Register = 0x900B;
+	static const uint16_t Audio3Register = 0x900C;
+	static const uint16_t Audio4Register = 0x900D;
+	static const uint16_t AudioVolRegister = 0x900E;
+};
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico20/basicrom.h b/MCUME_pico2/pico20/basicrom.h
new file mode 100755
index 0000000..10ac1d2
--- /dev/null
+++ b/MCUME_pico2/pico20/basicrom.h
@@ -0,0 +1,514 @@
+const unsigned char basicrom[8192] = {
+0x78,0xE3,0x67,0xE4,0x43,0x42,0x4D,0x42,0x41,0x53,0x49,0x43,0x30,0xC8,0x41,0xC7,
+0x1D,0xCD,0xF7,0xC8,0xA4,0xCB,0xBE,0xCB,0x80,0xD0,0x05,0xCC,0xA4,0xC9,0x9F,0xC8,
+0x70,0xC8,0x27,0xC9,0x1C,0xC8,0x82,0xC8,0xD1,0xC8,0x3A,0xC9,0x2E,0xC8,0x4A,0xC9,
+0x2C,0xD8,0x64,0xE1,0x52,0xE1,0x61,0xE1,0xB2,0xD3,0x23,0xD8,0x7F,0xCA,0x9F,0xCA,
+0x56,0xC8,0x9B,0xC6,0x5D,0xC6,0x85,0xCA,0x26,0xE1,0xBA,0xE1,0xC3,0xE1,0x7A,0xCB,
+0x41,0xC6,0x39,0xDC,0xCC,0xDC,0x58,0xDC,0x00,0x00,0x7D,0xD3,0x9E,0xD3,0x71,0xDF,
+0x94,0xE0,0xEA,0xD9,0xED,0xDF,0x61,0xE2,0x68,0xE2,0xB1,0xE2,0x0B,0xE3,0x0D,0xD8,
+0x7C,0xD7,0x65,0xD4,0xAD,0xD7,0x8B,0xD7,0xEC,0xD6,0x00,0xD7,0x2C,0xD7,0x37,0xD7,
+0x79,0x69,0xD8,0x79,0x52,0xD8,0x7B,0x2A,0xDA,0x7B,0x11,0xDB,0x7F,0x7A,0xDF,0x50,
+0xE8,0xCF,0x46,0xE5,0xCF,0x7D,0xB3,0xDF,0x5A,0xD3,0xCE,0x64,0x15,0xD0,0x45,0x4E,
+0xC4,0x46,0x4F,0xD2,0x4E,0x45,0x58,0xD4,0x44,0x41,0x54,0xC1,0x49,0x4E,0x50,0x55,
+0x54,0xA3,0x49,0x4E,0x50,0x55,0xD4,0x44,0x49,0xCD,0x52,0x45,0x41,0xC4,0x4C,0x45,
+0xD4,0x47,0x4F,0x54,0xCF,0x52,0x55,0xCE,0x49,0xC6,0x52,0x45,0x53,0x54,0x4F,0x52,
+0xC5,0x47,0x4F,0x53,0x55,0xC2,0x52,0x45,0x54,0x55,0x52,0xCE,0x52,0x45,0xCD,0x53,
+0x54,0x4F,0xD0,0x4F,0xCE,0x57,0x41,0x49,0xD4,0x4C,0x4F,0x41,0xC4,0x53,0x41,0x56,
+0xC5,0x56,0x45,0x52,0x49,0x46,0xD9,0x44,0x45,0xC6,0x50,0x4F,0x4B,0xC5,0x50,0x52,
+0x49,0x4E,0x54,0xA3,0x50,0x52,0x49,0x4E,0xD4,0x43,0x4F,0x4E,0xD4,0x4C,0x49,0x53,
+0xD4,0x43,0x4C,0xD2,0x43,0x4D,0xC4,0x53,0x59,0xD3,0x4F,0x50,0x45,0xCE,0x43,0x4C,
+0x4F,0x53,0xC5,0x47,0x45,0xD4,0x4E,0x45,0xD7,0x54,0x41,0x42,0xA8,0x54,0xCF,0x46,
+0xCE,0x53,0x50,0x43,0xA8,0x54,0x48,0x45,0xCE,0x4E,0x4F,0xD4,0x53,0x54,0x45,0xD0,
+0xAB,0xAD,0xAA,0xAF,0xDE,0x41,0x4E,0xC4,0x4F,0xD2,0xBE,0xBD,0xBC,0x53,0x47,0xCE,
+0x49,0x4E,0xD4,0x41,0x42,0xD3,0x55,0x53,0xD2,0x46,0x52,0xC5,0x50,0x4F,0xD3,0x53,
+0x51,0xD2,0x52,0x4E,0xC4,0x4C,0x4F,0xC7,0x45,0x58,0xD0,0x43,0x4F,0xD3,0x53,0x49,
+0xCE,0x54,0x41,0xCE,0x41,0x54,0xCE,0x50,0x45,0x45,0xCB,0x4C,0x45,0xCE,0x53,0x54,
+0x52,0xA4,0x56,0x41,0xCC,0x41,0x53,0xC3,0x43,0x48,0x52,0xA4,0x4C,0x45,0x46,0x54,
+0xA4,0x52,0x49,0x47,0x48,0x54,0xA4,0x4D,0x49,0x44,0xA4,0x47,0xCF,0x00,0x54,0x4F,
+0x4F,0x20,0x4D,0x41,0x4E,0x59,0x20,0x46,0x49,0x4C,0x45,0xD3,0x46,0x49,0x4C,0x45,
+0x20,0x4F,0x50,0x45,0xCE,0x46,0x49,0x4C,0x45,0x20,0x4E,0x4F,0x54,0x20,0x4F,0x50,
+0x45,0xCE,0x46,0x49,0x4C,0x45,0x20,0x4E,0x4F,0x54,0x20,0x46,0x4F,0x55,0x4E,0xC4,
+0x44,0x45,0x56,0x49,0x43,0x45,0x20,0x4E,0x4F,0x54,0x20,0x50,0x52,0x45,0x53,0x45,
+0x4E,0xD4,0x4E,0x4F,0x54,0x20,0x49,0x4E,0x50,0x55,0x54,0x20,0x46,0x49,0x4C,0xC5,
+0x4E,0x4F,0x54,0x20,0x4F,0x55,0x54,0x50,0x55,0x54,0x20,0x46,0x49,0x4C,0xC5,0x4D,
+0x49,0x53,0x53,0x49,0x4E,0x47,0x20,0x46,0x49,0x4C,0x45,0x20,0x4E,0x41,0x4D,0xC5,
+0x49,0x4C,0x4C,0x45,0x47,0x41,0x4C,0x20,0x44,0x45,0x56,0x49,0x43,0x45,0x20,0x4E,
+0x55,0x4D,0x42,0x45,0xD2,0x4E,0x45,0x58,0x54,0x20,0x57,0x49,0x54,0x48,0x4F,0x55,
+0x54,0x20,0x46,0x4F,0xD2,0x53,0x59,0x4E,0x54,0x41,0xD8,0x52,0x45,0x54,0x55,0x52,
+0x4E,0x20,0x57,0x49,0x54,0x48,0x4F,0x55,0x54,0x20,0x47,0x4F,0x53,0x55,0xC2,0x4F,
+0x55,0x54,0x20,0x4F,0x46,0x20,0x44,0x41,0x54,0xC1,0x49,0x4C,0x4C,0x45,0x47,0x41,
+0x4C,0x20,0x51,0x55,0x41,0x4E,0x54,0x49,0x54,0xD9,0x4F,0x56,0x45,0x52,0x46,0x4C,
+0x4F,0xD7,0x4F,0x55,0x54,0x20,0x4F,0x46,0x20,0x4D,0x45,0x4D,0x4F,0x52,0xD9,0x55,
+0x4E,0x44,0x45,0x46,0x27,0x44,0x20,0x53,0x54,0x41,0x54,0x45,0x4D,0x45,0x4E,0xD4,
+0x42,0x41,0x44,0x20,0x53,0x55,0x42,0x53,0x43,0x52,0x49,0x50,0xD4,0x52,0x45,0x44,
+0x49,0x4D,0x27,0x44,0x20,0x41,0x52,0x52,0x41,0xD9,0x44,0x49,0x56,0x49,0x53,0x49,
+0x4F,0x4E,0x20,0x42,0x59,0x20,0x5A,0x45,0x52,0xCF,0x49,0x4C,0x4C,0x45,0x47,0x41,
+0x4C,0x20,0x44,0x49,0x52,0x45,0x43,0xD4,0x54,0x59,0x50,0x45,0x20,0x4D,0x49,0x53,
+0x4D,0x41,0x54,0x43,0xC8,0x53,0x54,0x52,0x49,0x4E,0x47,0x20,0x54,0x4F,0x4F,0x20,
+0x4C,0x4F,0x4E,0xC7,0x46,0x49,0x4C,0x45,0x20,0x44,0x41,0x54,0xC1,0x46,0x4F,0x52,
+0x4D,0x55,0x4C,0x41,0x20,0x54,0x4F,0x4F,0x20,0x43,0x4F,0x4D,0x50,0x4C,0x45,0xD8,
+0x43,0x41,0x4E,0x27,0x54,0x20,0x43,0x4F,0x4E,0x54,0x49,0x4E,0x55,0xC5,0x55,0x4E,
+0x44,0x45,0x46,0x27,0x44,0x20,0x46,0x55,0x4E,0x43,0x54,0x49,0x4F,0xCE,0x56,0x45,
+0x52,0x49,0x46,0xD9,0x4C,0x4F,0x41,0xC4,0x9E,0xC1,0xAC,0xC1,0xB5,0xC1,0xC2,0xC1,
+0xD0,0xC1,0xE2,0xC1,0xF0,0xC1,0xFF,0xC1,0x10,0xC2,0x25,0xC2,0x35,0xC2,0x3B,0xC2,
+0x4F,0xC2,0x5A,0xC2,0x6A,0xC2,0x72,0xC2,0x7F,0xC2,0x90,0xC2,0x9D,0xC2,0xAA,0xC2,
+0xBA,0xC2,0xC8,0xC2,0xD5,0xC2,0xE4,0xC2,0xED,0xC2,0x00,0xC3,0x0E,0xC3,0x1E,0xC3,
+0x24,0xC3,0x83,0xC3,0x0D,0x4F,0x4B,0x0D,0x00,0x0D,0x20,0x45,0x52,0x52,0x4F,0x52,
+0x00,0x20,0x49,0x4E,0x20,0x00,0x0D,0x0A,0x52,0x45,0x41,0x44,0x59,0x2E,0x0D,0x0A,
+0x00,0x0D,0x0A,0x42,0x52,0x45,0x41,0x4B,0x00,0xA0,0xBA,0xE8,0xE8,0xE8,0xE8,0xBD,
+0x01,0x01,0xC9,0x81,0xD0,0x21,0xA5,0x4A,0xD0,0x0A,0xBD,0x02,0x01,0x85,0x49,0xBD,
+0x03,0x01,0x85,0x4A,0xDD,0x03,0x01,0xD0,0x07,0xA5,0x49,0xDD,0x02,0x01,0xF0,0x07,
+0x8A,0x18,0x69,0x12,0xAA,0xD0,0xD8,0x60,0x20,0x08,0xC4,0x85,0x31,0x84,0x32,0x38,
+0xA5,0x5A,0xE5,0x5F,0x85,0x22,0xA8,0xA5,0x5B,0xE5,0x60,0xAA,0xE8,0x98,0xF0,0x23,
+0xA5,0x5A,0x38,0xE5,0x22,0x85,0x5A,0xB0,0x03,0xC6,0x5B,0x38,0xA5,0x58,0xE5,0x22,
+0x85,0x58,0xB0,0x08,0xC6,0x59,0x90,0x04,0xB1,0x5A,0x91,0x58,0x88,0xD0,0xF9,0xB1,
+0x5A,0x91,0x58,0xC6,0x5B,0xC6,0x59,0xCA,0xD0,0xF2,0x60,0x0A,0x69,0x3E,0xB0,0x35,
+0x85,0x22,0xBA,0xE4,0x22,0x90,0x2E,0x60,0xC4,0x34,0x90,0x28,0xD0,0x04,0xC5,0x33,
+0x90,0x22,0x48,0xA2,0x09,0x98,0x48,0xB5,0x57,0xCA,0x10,0xFA,0x20,0x26,0xD5,0xA2,
+0xF7,0x68,0x95,0x61,0xE8,0x30,0xFA,0x68,0xA8,0x68,0xC4,0x34,0x90,0x06,0xD0,0x05,
+0xC5,0x33,0xB0,0x01,0x60,0xA2,0x10,0x6C,0x00,0x03,0x8A,0x0A,0xAA,0xBD,0x26,0xC3,
+0x85,0x22,0xBD,0x27,0xC3,0x85,0x23,0x20,0xCC,0xFF,0xA9,0x00,0x85,0x13,0x20,0xD7,
+0xCA,0x20,0x45,0xCB,0xA0,0x00,0xB1,0x22,0x48,0x29,0x7F,0x20,0x47,0xCB,0xC8,0x68,
+0x10,0xF4,0x20,0x7A,0xC6,0xA9,0x69,0xA0,0xC3,0x20,0x1E,0xCB,0xA4,0x3A,0xC8,0xF0,
+0x03,0x20,0xC2,0xDD,0xA9,0x76,0xA0,0xC3,0x20,0x1E,0xCB,0xA9,0x80,0x20,0x90,0xFF,
+0x6C,0x02,0x03,0x20,0x60,0xC5,0x86,0x7A,0x84,0x7B,0x20,0x73,0x00,0xAA,0xF0,0xF0,
+0xA2,0xFF,0x86,0x3A,0x90,0x06,0x20,0x79,0xC5,0x4C,0xE1,0xC7,0x20,0x6B,0xC9,0x20,
+0x79,0xC5,0x84,0x0B,0x20,0x13,0xC6,0x90,0x44,0xA0,0x01,0xB1,0x5F,0x85,0x23,0xA5,
+0x2D,0x85,0x22,0xA5,0x60,0x85,0x25,0xA5,0x5F,0x88,0xF1,0x5F,0x18,0x65,0x2D,0x85,
+0x2D,0x85,0x24,0xA5,0x2E,0x69,0xFF,0x85,0x2E,0xE5,0x60,0xAA,0x38,0xA5,0x5F,0xE5,
+0x2D,0xA8,0xB0,0x03,0xE8,0xC6,0x25,0x18,0x65,0x22,0x90,0x03,0xC6,0x23,0x18,0xB1,
+0x22,0x91,0x24,0xC8,0xD0,0xF9,0xE6,0x23,0xE6,0x25,0xCA,0xD0,0xF2,0x20,0x59,0xC6,
+0x20,0x33,0xC5,0xAD,0x00,0x02,0xF0,0x88,0x18,0xA5,0x2D,0x85,0x5A,0x65,0x0B,0x85,
+0x58,0xA4,0x2E,0x84,0x5B,0x90,0x01,0xC8,0x84,0x59,0x20,0xB8,0xC3,0xA5,0x14,0xA4,
+0x15,0x8D,0xFE,0x01,0x8C,0xFF,0x01,0xA5,0x31,0xA4,0x32,0x85,0x2D,0x84,0x2E,0xA4,
+0x0B,0x88,0xB9,0xFC,0x01,0x91,0x5F,0x88,0x10,0xF8,0x20,0x59,0xC6,0x20,0x33,0xC5,
+0x4C,0x80,0xC4,0xA5,0x2B,0xA4,0x2C,0x85,0x22,0x84,0x23,0x18,0xA0,0x01,0xB1,0x22,
+0xF0,0x1D,0xA0,0x04,0xC8,0xB1,0x22,0xD0,0xFB,0xC8,0x98,0x65,0x22,0xAA,0xA0,0x00,
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+0x2A,0x90,0x09,0xE8,0x95,0x29,0xF0,0x32,0x10,0x34,0xA9,0x01,0x28,0xB0,0x0E,0x06,
+0x6D,0x26,0x6C,0x26,0x6B,0x26,0x6A,0xB0,0xE6,0x30,0xCE,0x10,0xE2,0xA8,0xA5,0x6D,
+0xE5,0x65,0x85,0x6D,0xA5,0x6C,0xE5,0x64,0x85,0x6C,0xA5,0x6B,0xE5,0x63,0x85,0x6B,
+0xA5,0x6A,0xE5,0x62,0x85,0x6A,0x98,0x4C,0x4F,0xDB,0xA9,0x40,0xD0,0xCE,0x0A,0x0A,
+0x0A,0x0A,0x0A,0x0A,0x85,0x70,0x28,0x4C,0x8F,0xDB,0xA2,0x14,0x4C,0x37,0xC4,0xA5,
+0x26,0x85,0x62,0xA5,0x27,0x85,0x63,0xA5,0x28,0x85,0x64,0xA5,0x29,0x85,0x65,0x4C,
+0xD7,0xD8,0x85,0x22,0x84,0x23,0xA0,0x04,0xB1,0x22,0x85,0x65,0x88,0xB1,0x22,0x85,
+0x64,0x88,0xB1,0x22,0x85,0x63,0x88,0xB1,0x22,0x85,0x66,0x09,0x80,0x85,0x62,0x88,
+0xB1,0x22,0x85,0x61,0x84,0x70,0x60,0xA2,0x5C,0x2C,0xA2,0x57,0xA0,0x00,0xF0,0x04,
+0xA6,0x49,0xA4,0x4A,0x20,0x1B,0xDC,0x86,0x22,0x84,0x23,0xA0,0x04,0xA5,0x65,0x91,
+0x22,0x88,0xA5,0x64,0x91,0x22,0x88,0xA5,0x63,0x91,0x22,0x88,0xA5,0x66,0x09,0x7F,
+0x25,0x62,0x91,0x22,0x88,0xA5,0x61,0x91,0x22,0x84,0x70,0x60,0xA5,0x6E,0x85,0x66,
+0xA2,0x05,0xB5,0x68,0x95,0x60,0xCA,0xD0,0xF9,0x86,0x70,0x60,0x20,0x1B,0xDC,0xA2,
+0x06,0xB5,0x60,0x95,0x68,0xCA,0xD0,0xF9,0x86,0x70,0x60,0xA5,0x61,0xF0,0xFB,0x06,
+0x70,0x90,0xF7,0x20,0x6F,0xD9,0xD0,0xF2,0x4C,0x38,0xD9,0xA5,0x61,0xF0,0x09,0xA5,
+0x66,0x2A,0xA9,0xFF,0xB0,0x02,0xA9,0x01,0x60,0x20,0x2B,0xDC,0x85,0x62,0xA9,0x00,
+0x85,0x63,0xA2,0x88,0xA5,0x62,0x49,0xFF,0x2A,0xA9,0x00,0x85,0x65,0x85,0x64,0x86,
+0x61,0x85,0x70,0x85,0x66,0x4C,0xD2,0xD8,0x46,0x66,0x60,0x85,0x24,0x84,0x25,0xA0,
+0x00,0xB1,0x24,0xC8,0xAA,0xF0,0xC4,0xB1,0x24,0x45,0x66,0x30,0xC2,0xE4,0x61,0xD0,
+0x21,0xB1,0x24,0x09,0x80,0xC5,0x62,0xD0,0x19,0xC8,0xB1,0x24,0xC5,0x63,0xD0,0x12,
+0xC8,0xB1,0x24,0xC5,0x64,0xD0,0x0B,0xC8,0xA9,0x7F,0xC5,0x70,0xB1,0x24,0xE5,0x65,
+0xF0,0x28,0xA5,0x66,0x90,0x02,0x49,0xFF,0x4C,0x31,0xDC,0xA5,0x61,0xF0,0x4A,0x38,
+0xE9,0xA0,0x24,0x66,0x10,0x09,0xAA,0xA9,0xFF,0x85,0x68,0x20,0x4D,0xD9,0x8A,0xA2,
+0x61,0xC9,0xF9,0x10,0x06,0x20,0x99,0xD9,0x84,0x68,0x60,0xA8,0xA5,0x66,0x29,0x80,
+0x46,0x62,0x05,0x62,0x85,0x62,0x20,0xB0,0xD9,0x84,0x68,0x60,0xA5,0x61,0xC9,0xA0,
+0xB0,0x20,0x20,0x9B,0xDC,0x84,0x70,0xA5,0x66,0x84,0x66,0x49,0x80,0x2A,0xA9,0xA0,
+0x85,0x61,0xA5,0x65,0x85,0x07,0x4C,0xD2,0xD8,0x85,0x62,0x85,0x63,0x85,0x64,0x85,
+0x65,0xA8,0x60,0xA0,0x00,0xA2,0x0A,0x94,0x5D,0xCA,0x10,0xFB,0x90,0x0F,0xC9,0x2D,
+0xD0,0x04,0x86,0x67,0xF0,0x04,0xC9,0x2B,0xD0,0x05,0x20,0x73,0x00,0x90,0x5B,0xC9,
+0x2E,0xF0,0x2E,0xC9,0x45,0xD0,0x30,0x20,0x73,0x00,0x90,0x17,0xC9,0xAB,0xF0,0x0E,
+0xC9,0x2D,0xF0,0x0A,0xC9,0xAA,0xF0,0x08,0xC9,0x2B,0xF0,0x04,0xD0,0x07,0x66,0x60,
+0x20,0x73,0x00,0x90,0x5C,0x24,0x60,0x10,0x0E,0xA9,0x00,0x38,0xE5,0x5E,0x4C,0x49,
+0xDD,0x66,0x5F,0x24,0x5F,0x50,0xC3,0xA5,0x5E,0x38,0xE5,0x5D,0x85,0x5E,0xF0,0x12,
+0x10,0x09,0x20,0xFE,0xDA,0xE6,0x5E,0xD0,0xF9,0xF0,0x07,0x20,0xE2,0xDA,0xC6,0x5E,
+0xD0,0xF9,0xA5,0x67,0x30,0x01,0x60,0x4C,0xB4,0xDF,0x48,0x24,0x5F,0x10,0x02,0xE6,
+0x5D,0x20,0xE2,0xDA,0x68,0x38,0xE9,0x30,0x20,0x7E,0xDD,0x4C,0x0A,0xDD,0x48,0x20,
+0x0C,0xDC,0x68,0x20,0x3C,0xDC,0xA5,0x6E,0x45,0x66,0x85,0x6F,0xA6,0x61,0x4C,0x6A,
+0xD8,0xA5,0x5E,0xC9,0x0A,0x90,0x09,0xA9,0x64,0x24,0x60,0x30,0x11,0x4C,0x7E,0xD9,
+0x0A,0x0A,0x18,0x65,0x5E,0x0A,0x18,0xA0,0x00,0x71,0x7A,0x38,0xE9,0x30,0x85,0x5E,
+0x4C,0x30,0xDD,0x9B,0x3E,0xBC,0x1F,0xFD,0x9E,0x6E,0x6B,0x27,0xFD,0x9E,0x6E,0x6B,
+0x28,0x00,0xA9,0x71,0xA0,0xC3,0x20,0xDA,0xDD,0xA5,0x3A,0xA6,0x39,0x85,0x62,0x86,
+0x63,0xA2,0x90,0x38,0x20,0x49,0xDC,0x20,0xDF,0xDD,0x4C,0x1E,0xCB,0xA0,0x01,0xA9,
+0x20,0x24,0x66,0x10,0x02,0xA9,0x2D,0x99,0xFF,0x00,0x85,0x66,0x84,0x71,0xC8,0xA9,
+0x30,0xA6,0x61,0xD0,0x03,0x4C,0x04,0xDF,0xA9,0x00,0xE0,0x80,0xF0,0x02,0xB0,0x09,
+0xA9,0xBD,0xA0,0xDD,0x20,0x28,0xDA,0xA9,0xF7,0x85,0x5D,0xA9,0xB8,0xA0,0xDD,0x20,
+0x5B,0xDC,0xF0,0x1E,0x10,0x12,0xA9,0xB3,0xA0,0xDD,0x20,0x5B,0xDC,0xF0,0x02,0x10,
+0x0E,0x20,0xE2,0xDA,0xC6,0x5D,0xD0,0xEE,0x20,0xFE,0xDA,0xE6,0x5D,0xD0,0xDC,0x20,
+0x49,0xD8,0x20,0x9B,0xDC,0xA2,0x01,0xA5,0x5D,0x18,0x69,0x0A,0x30,0x09,0xC9,0x0B,
+0xB0,0x06,0x69,0xFF,0xAA,0xA9,0x02,0x38,0xE9,0x02,0x85,0x5E,0x86,0x5D,0x8A,0xF0,
+0x02,0x10,0x13,0xA4,0x71,0xA9,0x2E,0xC8,0x99,0xFF,0x00,0x8A,0xF0,0x06,0xA9,0x30,
+0xC8,0x99,0xFF,0x00,0x84,0x71,0xA0,0x00,0xA2,0x80,0xA5,0x65,0x18,0x79,0x19,0xDF,
+0x85,0x65,0xA5,0x64,0x79,0x18,0xDF,0x85,0x64,0xA5,0x63,0x79,0x17,0xDF,0x85,0x63,
+0xA5,0x62,0x79,0x16,0xDF,0x85,0x62,0xE8,0xB0,0x04,0x10,0xDE,0x30,0x02,0x30,0xDA,
+0x8A,0x90,0x04,0x49,0xFF,0x69,0x0A,0x69,0x2F,0xC8,0xC8,0xC8,0xC8,0x84,0x47,0xA4,
+0x71,0xC8,0xAA,0x29,0x7F,0x99,0xFF,0x00,0xC6,0x5D,0xD0,0x06,0xA9,0x2E,0xC8,0x99,
+0xFF,0x00,0x84,0x71,0xA4,0x47,0x8A,0x49,0xFF,0x29,0x80,0xAA,0xC0,0x24,0xF0,0x04,
+0xC0,0x3C,0xD0,0xA6,0xA4,0x71,0xB9,0xFF,0x00,0x88,0xC9,0x30,0xF0,0xF8,0xC9,0x2E,
+0xF0,0x01,0xC8,0xA9,0x2B,0xA6,0x5E,0xF0,0x2E,0x10,0x08,0xA9,0x00,0x38,0xE5,0x5E,
+0xAA,0xA9,0x2D,0x99,0x01,0x01,0xA9,0x45,0x99,0x00,0x01,0x8A,0xA2,0x2F,0x38,0xE8,
+0xE9,0x0A,0xB0,0xFB,0x69,0x3A,0x99,0x03,0x01,0x8A,0x99,0x02,0x01,0xA9,0x00,0x99,
+0x04,0x01,0xF0,0x08,0x99,0xFF,0x00,0xA9,0x00,0x99,0x00,0x01,0xA9,0x00,0xA0,0x01,
+0x60,0x80,0x00,0x00,0x00,0x00,0xFA,0x0A,0x1F,0x00,0x00,0x98,0x96,0x80,0xFF,0xF0,
+0xBD,0xC0,0x00,0x01,0x86,0xA0,0xFF,0xFF,0xD8,0xF0,0x00,0x00,0x03,0xE8,0xFF,0xFF,
+0xFF,0x9C,0x00,0x00,0x00,0x0A,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF,0x0A,0x80,0x00,0x03,
+0x4B,0xC0,0xFF,0xFF,0x73,0x60,0x00,0x00,0x0E,0x10,0xFF,0xFF,0xFD,0xA8,0x00,0x00,
+0x00,0x3C,0xBF,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+0xAA,0x20,0x0C,0xDC,0xA9,0x11,0xA0,0xDF,0x20,0xA2,0xDB,0xF0,0x70,0xA5,0x69,0xD0,
+0x03,0x4C,0xF9,0xD8,0xA2,0x4E,0xA0,0x00,0x20,0xD4,0xDB,0xA5,0x6E,0x10,0x0F,0x20,
+0xCC,0xDC,0xA9,0x4E,0xA0,0x00,0x20,0x5B,0xDC,0xD0,0x03,0x98,0xA4,0x07,0x20,0xFE,
+0xDB,0x98,0x48,0x20,0xEA,0xD9,0xA9,0x4E,0xA0,0x00,0x20,0x28,0xDA,0x20,0xED,0xDF,
+0x68,0x4A,0x90,0x0A,0xA5,0x61,0xF0,0x06,0xA5,0x66,0x49,0xFF,0x85,0x66,0x60,0x81,
+0x38,0xAA,0x3B,0x29,0x07,0x71,0x34,0x58,0x3E,0x56,0x74,0x16,0x7E,0xB3,0x1B,0x77,
+0x2F,0xEE,0xE3,0x85,0x7A,0x1D,0x84,0x1C,0x2A,0x7C,0x63,0x59,0x58,0x0A,0x7E,0x75,
+0xFD,0xE7,0xC6,0x80,0x31,0x72,0x18,0x10,0x81,0x00,0x00,0x00,0x00,0xA9,0xBF,0xA0,
+0xDF,0x20,0x28,0xDA,0xA5,0x70,0x69,0x50,0x90,0x03,0x20,0x23,0xDC,0x85,0x56,0x20,
+};
diff --git a/MCUME_pico2/pico20/charrom.h b/MCUME_pico2/pico20/charrom.h
new file mode 100755
index 0000000..f34c540
--- /dev/null
+++ b/MCUME_pico2/pico20/charrom.h
@@ -0,0 +1,258 @@
+const unsigned char charrom[4096] = {
+0x1C,0x22,0x4A,0x56,0x4C,0x20,0x1E,0x00,0x18,0x24,0x42,0x7E,0x42,0x42,0x42,0x00,
+0x7C,0x22,0x22,0x3C,0x22,0x22,0x7C,0x00,0x1C,0x22,0x40,0x40,0x40,0x22,0x1C,0x00,
+0x78,0x24,0x22,0x22,0x22,0x24,0x78,0x00,0x7E,0x40,0x40,0x78,0x40,0x40,0x7E,0x00,
+0x7E,0x40,0x40,0x78,0x40,0x40,0x40,0x00,0x1C,0x22,0x40,0x4E,0x42,0x22,0x1C,0x00,
+0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x00,0x1C,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,
+0x0E,0x04,0x04,0x04,0x04,0x44,0x38,0x00,0x42,0x44,0x48,0x70,0x48,0x44,0x42,0x00,
+0x40,0x40,0x40,0x40,0x40,0x40,0x7E,0x00,0x42,0x66,0x5A,0x5A,0x42,0x42,0x42,0x00,
+0x42,0x62,0x52,0x4A,0x46,0x42,0x42,0x00,0x18,0x24,0x42,0x42,0x42,0x24,0x18,0x00,
+0x7C,0x42,0x42,0x7C,0x40,0x40,0x40,0x00,0x18,0x24,0x42,0x42,0x4A,0x24,0x1A,0x00,
+0x7C,0x42,0x42,0x7C,0x48,0x44,0x42,0x00,0x3C,0x42,0x40,0x3C,0x02,0x42,0x3C,0x00,
+0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,
+0x42,0x42,0x42,0x24,0x24,0x18,0x18,0x00,0x42,0x42,0x42,0x5A,0x5A,0x66,0x42,0x00,
+0x42,0x42,0x24,0x18,0x24,0x42,0x42,0x00,0x22,0x22,0x22,0x1C,0x08,0x08,0x08,0x00,
+0x7E,0x02,0x04,0x18,0x20,0x40,0x7E,0x00,0x3C,0x20,0x20,0x20,0x20,0x20,0x3C,0x00,
+0x0C,0x10,0x10,0x3C,0x10,0x70,0x6E,0x00,0x3C,0x04,0x04,0x04,0x04,0x04,0x3C,0x00,
+0x00,0x08,0x1C,0x2A,0x08,0x08,0x08,0x08,0x00,0x00,0x10,0x20,0x7F,0x20,0x10,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x00,0x00,0x08,0x00,
+0x24,0x24,0x24,0x00,0x00,0x00,0x00,0x00,0x24,0x24,0x7E,0x24,0x7E,0x24,0x24,0x00,
+0x08,0x1E,0x28,0x1C,0x0A,0x3C,0x08,0x00,0x00,0x62,0x64,0x08,0x10,0x26,0x46,0x00,
+0x30,0x48,0x48,0x30,0x4A,0x44,0x3A,0x00,0x04,0x08,0x10,0x00,0x00,0x00,0x00,0x00,
+0x04,0x08,0x10,0x10,0x10,0x08,0x04,0x00,0x20,0x10,0x08,0x08,0x08,0x10,0x20,0x00,
+0x08,0x2A,0x1C,0x3E,0x1C,0x2A,0x08,0x00,0x00,0x08,0x08,0x3E,0x08,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x10,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x02,0x04,0x08,0x10,0x20,0x40,0x00,
+0x3C,0x42,0x46,0x5A,0x62,0x42,0x3C,0x00,0x08,0x18,0x28,0x08,0x08,0x08,0x3E,0x00,
+0x3C,0x42,0x02,0x0C,0x30,0x40,0x7E,0x00,0x3C,0x42,0x02,0x1C,0x02,0x42,0x3C,0x00,
+0x04,0x0C,0x14,0x24,0x7E,0x04,0x04,0x00,0x7E,0x40,0x78,0x04,0x02,0x44,0x38,0x00,
+0x1C,0x20,0x40,0x7C,0x42,0x42,0x3C,0x00,0x7E,0x42,0x04,0x08,0x10,0x10,0x10,0x00,
+0x3C,0x42,0x42,0x3C,0x42,0x42,0x3C,0x00,0x3C,0x42,0x42,0x3E,0x02,0x04,0x38,0x00,
+0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x08,0x10,
+0x0E,0x18,0x30,0x60,0x30,0x18,0x0E,0x00,0x00,0x00,0x7E,0x00,0x7E,0x00,0x00,0x00,
+0x70,0x18,0x0C,0x06,0x0C,0x18,0x70,0x00,0x3C,0x42,0x02,0x0C,0x10,0x00,0x10,0x00,
+0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x08,0x1C,0x3E,0x7F,0x7F,0x1C,0x3E,0x00,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
+0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
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+0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x08,0x10,
+0x0E,0x18,0x30,0x60,0x30,0x18,0x0E,0x00,0x00,0x00,0x7E,0x00,0x7E,0x00,0x00,0x00,
+0x70,0x18,0x0C,0x06,0x0C,0x18,0x70,0x00,0x3C,0x42,0x02,0x0C,0x10,0x00,0x10,0x00,
+0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x18,0x24,0x42,0x7E,0x42,0x42,0x42,0x00,
+0x7C,0x22,0x22,0x3C,0x22,0x22,0x7C,0x00,0x1C,0x22,0x40,0x40,0x40,0x22,0x1C,0x00,
+0x78,0x24,0x22,0x22,0x22,0x24,0x78,0x00,0x7E,0x40,0x40,0x78,0x40,0x40,0x7E,0x00,
+0x7E,0x40,0x40,0x78,0x40,0x40,0x40,0x00,0x1C,0x22,0x40,0x4E,0x42,0x22,0x1C,0x00,
+0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x00,0x1C,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,
+0x0E,0x04,0x04,0x04,0x04,0x44,0x38,0x00,0x42,0x44,0x48,0x70,0x48,0x44,0x42,0x00,
+0x40,0x40,0x40,0x40,0x40,0x40,0x7E,0x00,0x42,0x66,0x5A,0x5A,0x42,0x42,0x42,0x00,
+0x42,0x62,0x52,0x4A,0x46,0x42,0x42,0x00,0x18,0x24,0x42,0x42,0x42,0x24,0x18,0x00,
+0x7C,0x42,0x42,0x7C,0x40,0x40,0x40,0x00,0x18,0x24,0x42,0x42,0x4A,0x24,0x1A,0x00,
+0x7C,0x42,0x42,0x7C,0x48,0x44,0x42,0x00,0x3C,0x42,0x40,0x3C,0x02,0x42,0x3C,0x00,
+0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,
+0x42,0x42,0x42,0x24,0x24,0x18,0x18,0x00,0x42,0x42,0x42,0x5A,0x5A,0x66,0x42,0x00,
+0x42,0x42,0x24,0x18,0x24,0x42,0x42,0x00,0x22,0x22,0x22,0x1C,0x08,0x08,0x08,0x00,
+0x7E,0x02,0x04,0x18,0x20,0x40,0x7E,0x00,0x08,0x08,0x08,0x08,0xFF,0x08,0x08,0x08,
+0xA0,0x50,0xA0,0x50,0xA0,0x50,0xA0,0x50,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0xCC,0xCC,0x33,0x33,0xCC,0xCC,0x33,0x33,0xCC,0x66,0x33,0x99,0xCC,0x66,0x33,0x99,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,
+0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
+0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x00,0x00,0x00,0x00,0xAA,0x55,0xAA,0x55,0x99,0x33,0x66,0xCC,0x99,0x33,0x66,0xCC,
+0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x08,0x08,0x08,0x08,0x0F,0x08,0x08,0x08,
+0x00,0x00,0x00,0x00,0x0F,0x0F,0x0F,0x0F,0x08,0x08,0x08,0x08,0x0F,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xF8,0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,
+0x00,0x00,0x00,0x00,0x0F,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xFF,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xFF,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xF8,0x08,0x08,0x08,
+0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,
+0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,
+0x01,0x02,0x44,0x48,0x50,0x60,0x40,0x00,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,
+0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0xF8,0x00,0x00,0x00,
+0xF0,0xF0,0xF0,0xF0,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0x0F,0x0F,0x0F,0x0F,
+0xE3,0xDD,0xB5,0xA9,0xB3,0xDF,0xE1,0xFF,0xFF,0xFF,0xC7,0xFB,0xC3,0xBB,0xC5,0xFF,
+0xBF,0xBF,0xA3,0x9D,0xBD,0x9D,0xA3,0xFF,0xFF,0xFF,0xC3,0xBD,0xBF,0xBD,0xC3,0xFF,
+0xFD,0xFD,0xC5,0xB9,0xBD,0xB9,0xC5,0xFF,0xFF,0xFF,0xC3,0xBD,0x81,0xBF,0xC3,0xFF,
+0xF3,0xED,0xEF,0x83,0xEF,0xEF,0xEF,0xFF,0xFF,0xFF,0xC5,0xB9,0xB9,0xC5,0xFD,0xC3,
+0xBF,0xBF,0xA3,0x9D,0xBD,0xBD,0xBD,0xFF,0xF7,0xFF,0xE7,0xF7,0xF7,0xF7,0xE3,0xFF,
+0xFB,0xFF,0xF3,0xFB,0xFB,0xFB,0xBB,0xC7,0xBF,0xBF,0xBB,0xB7,0xAF,0x97,0xBB,0xFF,
+0xE7,0xF7,0xF7,0xF7,0xF7,0xF7,0xE3,0xFF,0xFF,0xFF,0x89,0xB6,0xB6,0xB6,0xB6,0xFF,
+0xFF,0xFF,0xA3,0x9D,0xBD,0xBD,0xBD,0xFF,0xFF,0xFF,0xC3,0xBD,0xBD,0xBD,0xC3,0xFF,
+0xFF,0xFF,0xA3,0x9D,0x9D,0xA3,0xBF,0xBF,0xFF,0xFF,0xC5,0xB9,0xB9,0xC5,0xFD,0xFD,
+0xFF,0xFF,0xA3,0x9D,0xBF,0xBF,0xBF,0xFF,0xFF,0xFF,0xC1,0xBF,0xC3,0xFD,0x83,0xFF,
+0xEF,0xEF,0x83,0xEF,0xEF,0xED,0xF3,0xFF,0xFF,0xFF,0xBD,0xBD,0xBD,0xB9,0xC5,0xFF,
+0xFF,0xFF,0xBD,0xBD,0xBD,0xDB,0xE7,0xFF,0xFF,0xFF,0xBE,0xB6,0xB6,0xB6,0xC9,0xFF,
+0xFF,0xFF,0xBD,0xDB,0xE7,0xDB,0xBD,0xFF,0xFF,0xFF,0xBD,0xBD,0xB9,0xC5,0xFD,0xC3,
+0xFF,0xFF,0x81,0xFB,0xE7,0xDF,0x81,0xFF,0xC3,0xDF,0xDF,0xDF,0xDF,0xDF,0xC3,0xFF,
+0xF3,0xEF,0xEF,0xC3,0xEF,0x8F,0x91,0xFF,0xC3,0xFB,0xFB,0xFB,0xFB,0xFB,0xC3,0xFF,
+0xFF,0xF7,0xE3,0xD5,0xF7,0xF7,0xF7,0xF7,0xFF,0xFF,0xEF,0xDF,0x80,0xDF,0xEF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF7,0xF7,0xF7,0xF7,0xFF,0xFF,0xF7,0xFF,
+0xDB,0xDB,0xDB,0xFF,0xFF,0xFF,0xFF,0xFF,0xDB,0xDB,0x81,0xDB,0x81,0xDB,0xDB,0xFF,
+0xF7,0xE1,0xD7,0xE3,0xF5,0xC3,0xF7,0xFF,0xFF,0x9D,0x9B,0xF7,0xEF,0xD9,0xB9,0xFF,
+0xCF,0xB7,0xB7,0xCF,0xB5,0xBB,0xC5,0xFF,0xFB,0xF7,0xEF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFB,0xF7,0xEF,0xEF,0xEF,0xF7,0xFB,0xFF,0xDF,0xEF,0xF7,0xF7,0xF7,0xEF,0xDF,0xFF,
+0xF7,0xD5,0xE3,0xC1,0xE3,0xD5,0xF7,0xFF,0xFF,0xF7,0xF7,0xC1,0xF7,0xF7,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xF7,0xF7,0xEF,0xFF,0xFF,0xFF,0x81,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xE7,0xE7,0xFF,0xFF,0xFD,0xFB,0xF7,0xEF,0xDF,0xBF,0xFF,
+0xC3,0xBD,0xB9,0xA5,0x9D,0xBD,0xC3,0xFF,0xF7,0xE7,0xD7,0xF7,0xF7,0xF7,0xC1,0xFF,
+0xC3,0xBD,0xFD,0xF3,0xCF,0xBF,0x81,0xFF,0xC3,0xBD,0xFD,0xE3,0xFD,0xBD,0xC3,0xFF,
+0xFB,0xF3,0xEB,0xDB,0x81,0xFB,0xFB,0xFF,0x81,0xBF,0x87,0xFB,0xFD,0xBB,0xC7,0xFF,
+0xE3,0xDF,0xBF,0x83,0xBD,0xBD,0xC3,0xFF,0x81,0xBD,0xFB,0xF7,0xEF,0xEF,0xEF,0xFF,
+0xC3,0xBD,0xBD,0xC3,0xBD,0xBD,0xC3,0xFF,0xC3,0xBD,0xBD,0xC1,0xFD,0xFB,0xC7,0xFF,
+0xFF,0xFF,0xF7,0xFF,0xFF,0xF7,0xFF,0xFF,0xFF,0xFF,0xF7,0xFF,0xFF,0xF7,0xF7,0xEF,
+0xF1,0xE7,0xCF,0x9F,0xCF,0xE7,0xF1,0xFF,0xFF,0xFF,0x81,0xFF,0x81,0xFF,0xFF,0xFF,
+0x8F,0xE7,0xF3,0xF9,0xF3,0xE7,0x8F,0xFF,0xC3,0xBD,0xFD,0xF3,0xEF,0xFF,0xEF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0xE7,0xDB,0xBD,0x81,0xBD,0xBD,0xBD,0xFF,
+0x83,0xDD,0xDD,0xC3,0xDD,0xDD,0x83,0xFF,0xE3,0xDD,0xBF,0xBF,0xBF,0xDD,0xE3,0xFF,
+0x87,0xDB,0xDD,0xDD,0xDD,0xDB,0x87,0xFF,0x81,0xBF,0xBF,0x87,0xBF,0xBF,0x81,0xFF,
+0x81,0xBF,0xBF,0x87,0xBF,0xBF,0xBF,0xFF,0xE3,0xDD,0xBF,0xB1,0xBD,0xDD,0xE3,0xFF,
+0xBD,0xBD,0xBD,0x81,0xBD,0xBD,0xBD,0xFF,0xE3,0xF7,0xF7,0xF7,0xF7,0xF7,0xE3,0xFF,
+0xF1,0xFB,0xFB,0xFB,0xFB,0xBB,0xC7,0xFF,0xBD,0xBB,0xB7,0x8F,0xB7,0xBB,0xBD,0xFF,
+0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0x81,0xFF,0xBD,0x99,0xA5,0xA5,0xBD,0xBD,0xBD,0xFF,
+0xBD,0x9D,0xAD,0xB5,0xB9,0xBD,0xBD,0xFF,0xE7,0xDB,0xBD,0xBD,0xBD,0xDB,0xE7,0xFF,
+0x83,0xBD,0xBD,0x83,0xBF,0xBF,0xBF,0xFF,0xE7,0xDB,0xBD,0xBD,0xB5,0xDB,0xE5,0xFF,
+0x83,0xBD,0xBD,0x83,0xB7,0xBB,0xBD,0xFF,0xC3,0xBD,0xBF,0xC3,0xFD,0xBD,0xC3,0xFF,
+0xC1,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0xFF,0xBD,0xBD,0xBD,0xBD,0xBD,0xBD,0xC3,0xFF,
+0xBD,0xBD,0xBD,0xDB,0xDB,0xE7,0xE7,0xFF,0xBD,0xBD,0xBD,0xA5,0xA5,0x99,0xBD,0xFF,
+0xBD,0xBD,0xDB,0xE7,0xDB,0xBD,0xBD,0xFF,0xDD,0xDD,0xDD,0xE3,0xF7,0xF7,0xF7,0xFF,
+0x81,0xFD,0xFB,0xE7,0xDF,0xBF,0x81,0xFF,0xF7,0xF7,0xF7,0xF7,0x00,0xF7,0xF7,0xF7,
+0x5F,0xAF,0x5F,0xAF,0x5F,0xAF,0x5F,0xAF,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,
+0x33,0x33,0xCC,0xCC,0x33,0x33,0xCC,0xCC,0x33,0x99,0xCC,0x66,0x33,0x99,0xCC,0x66,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,
+0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0xFE,0xFE,0xFE,0xFE,0xFE,0xFE,0xFE,0xFE,
+0xFF,0xFF,0xFF,0xFF,0x55,0xAA,0x55,0xAA,0x66,0xCC,0x99,0x33,0x66,0xCC,0x99,0x33,
+0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xF7,0xF7,0xF7,0xF7,0xF0,0xF7,0xF7,0xF7,
+0xFF,0xFF,0xFF,0xFF,0xF0,0xF0,0xF0,0xF0,0xF7,0xF7,0xF7,0xF7,0xF0,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0x07,0xF7,0xF7,0xF7,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xF0,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0x00,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0x00,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0xF7,0x07,0xF7,0xF7,0xF7,
+0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+0xFE,0xFD,0xBB,0xB7,0xAF,0x9F,0xBF,0xFF,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,
+0xF0,0xF0,0xF0,0xF0,0xFF,0xFF,0xFF,0xFF,0xF7,0xF7,0xF7,0xF7,0x07,0xFF,0xFF,0xFF,
+0x0F,0x0F,0x0F,0x0F,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,0xF0,0xF0,0xF0,0xF0,
+};
diff --git a/MCUME_pico2/pico20/emucfg.h b/MCUME_pico2/pico20/emucfg.h
new file mode 100644
index 0000000..3d93805
--- /dev/null
+++ b/MCUME_pico2/pico20/emucfg.h
@@ -0,0 +1,94 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    V20 Emulator "
+#define ROMSDIR "v20"
+
+#define emu_Init(ROM) {v20_Init(); v20_Start(ROM);}
+#define emu_Step(x) { v20_Step(); }
+#define emu_Input(x) { v20_Input(x); }
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  '1','2','3','4','5','6','7','8','9','0',
+  'Q','W','E','R','T','Y','U','I','O','P',
+  'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M',0,' ',
+  0,0,0,0,150,152 // L R
+  };  
+
+const unsigned short key_map2[] = {
+  '!','@','#','$','%','&','\'','(',')','_',
+  0,0,0,'<','>',0,0,0,';','"',
+  0,0,0,0,0,'^','-','+','=',0x0D,
+  0,':',0,'?','\/','*',',','.',0,' ',
+  153,151,150,152,150,152 //U L R D L R
+  };  
+
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0, // function keys
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  153,151,150,152,150,152 //U L R D L R
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  'Q','W','E','R','T','Y','U','I','O','P',157,
+  0,'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M','.',' ',
+  0,0,0,0
+  };  
+
+#define keylables_map2_0 (char *)"1234567890 "
+#define keylables_map2_1 (char *)" !@#$%+&*- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  '1','2','3','4','5','6','7','8','9','0',0,
+  0, '!','@','#','$','%','+','&','*','-','\/',
+  0, '(',')','?','\/','"','<','>',',',':',
+  145,157,29,17 //U L R D
+  };  
+
+#define keylables_map3_0 (char *)"\x11\x12\x13\x14\x15\x16\x17\x18   "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"        ;= "
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,';','=',
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico20/kernalromn.h b/MCUME_pico2/pico20/kernalromn.h
new file mode 100644
index 0000000..fc6b7b9
--- /dev/null
+++ b/MCUME_pico2/pico20/kernalromn.h
@@ -0,0 +1,514 @@
+const unsigned char kernalrom[8192] = {
+0x0F,0xDC,0xA5,0x61,0xC9,0x88,0x90,0x03,0x20,0xD4,0xDA,0x20,0xCC,0xDC,0xA5,0x07,
+0x18,0x69,0x81,0xF0,0xF3,0x38,0xE9,0x01,0x48,0xA2,0x05,0xB5,0x69,0xB4,0x61,0x95,
+0x61,0x94,0x69,0xCA,0x10,0xF5,0xA5,0x56,0x85,0x70,0x20,0x53,0xD8,0x20,0xB4,0xDF,
+0xA9,0xC4,0xA0,0xDF,0x20,0x56,0xE0,0xA9,0x00,0x85,0x6F,0x68,0x20,0xB9,0xDA,0x60,
+0x85,0x71,0x84,0x72,0x20,0xCA,0xDB,0xA9,0x57,0x20,0x28,0xDA,0x20,0x5A,0xE0,0xA9,
+0x57,0xA0,0x00,0x4C,0x28,0xDA,0x85,0x71,0x84,0x72,0x20,0xC7,0xDB,0xB1,0x71,0x85,
+0x67,0xA4,0x71,0xC8,0x98,0xD0,0x02,0xE6,0x72,0x85,0x71,0xA4,0x72,0x20,0x28,0xDA,
+0xA5,0x71,0xA4,0x72,0x18,0x69,0x05,0x90,0x01,0xC8,0x85,0x71,0x84,0x72,0x20,0x67,
+0xD8,0xA9,0x5C,0xA0,0x00,0xC6,0x67,0xD0,0xE4,0x60,0x98,0x35,0x44,0x7A,0x00,0x68,
+0x28,0xB1,0x46,0x00,0x20,0x2B,0xDC,0x30,0x37,0xD0,0x20,0x20,0xF3,0xFF,0x86,0x22,
+0x84,0x23,0xA0,0x04,0xB1,0x22,0x85,0x62,0xC8,0xB1,0x22,0x85,0x64,0xA0,0x08,0xB1,
+0x22,0x85,0x63,0xC8,0xB1,0x22,0x85,0x65,0x4C,0xE0,0xE0,0xA9,0x8B,0xA0,0x00,0x20,
+0xA2,0xDB,0xA9,0x8A,0xA0,0xE0,0x20,0x28,0xDA,0xA9,0x8F,0xA0,0xE0,0x20,0x67,0xD8,
+0xA6,0x65,0xA5,0x62,0x85,0x65,0x86,0x62,0xA6,0x63,0xA5,0x64,0x85,0x63,0x86,0x64,
+0xA9,0x00,0x85,0x66,0xA5,0x61,0x85,0x70,0xA9,0x80,0x85,0x61,0x20,0xD7,0xD8,0xA2,
+0x8B,0xA0,0x00,0x4C,0xD4,0xDB,0xC9,0xF0,0xD0,0x07,0x84,0x38,0x86,0x37,0x4C,0x63,
+0xC6,0xAA,0xD0,0x02,0xA2,0x1E,0x4C,0x37,0xC4,0x20,0xD2,0xFF,0xB0,0xE8,0x60,0x20,
+0xCF,0xFF,0xB0,0xE2,0x60,0x20,0xC9,0xFF,0xB0,0xDC,0x60,0x20,0xC6,0xFF,0xB0,0xD6,
+0x60,0x20,0xE4,0xFF,0xB0,0xD0,0x60,0x20,0x8A,0xCD,0x20,0xF7,0xD7,0xA9,0xE1,0x48,
+0xA9,0x43,0x48,0xAD,0x0F,0x03,0x48,0xAD,0x0C,0x03,0xAE,0x0D,0x03,0xAC,0x0E,0x03,
+0x28,0x6C,0x14,0x00,0x08,0x8D,0x0C,0x03,0x8E,0x0D,0x03,0x8C,0x0E,0x03,0x68,0x8D,
+0x0F,0x03,0x60,0x20,0xD1,0xE1,0xA6,0x2D,0xA4,0x2E,0xA9,0x2B,0x20,0xD8,0xFF,0xB0,
+0x95,0x60,0xA9,0x01,0x2C,0xA9,0x00,0x85,0x0A,0x20,0xD1,0xE1,0xA5,0x0A,0xA6,0x2B,
+0xA4,0x2C,0x20,0xD5,0xFF,0xB0,0x57,0xA5,0x0A,0xF0,0x1A,0xA2,0x1C,0x20,0xB7,0xFF,
+0x29,0x10,0xF0,0x03,0x4C,0x37,0xC4,0xA5,0x7A,0xC9,0x02,0xF0,0x07,0xA9,0x64,0xA0,
+0xC3,0x4C,0x1E,0xCB,0x60,0x20,0xB7,0xFF,0x29,0xBF,0xF0,0x05,0xA2,0x1D,0x4C,0x37,
+0xC4,0xA5,0x7B,0xC9,0x02,0xD0,0x0E,0x86,0x2D,0x84,0x2E,0xA9,0x76,0xA0,0xC3,0x20,
+0x1E,0xCB,0x4C,0x2A,0xC5,0x20,0x8E,0xC6,0x4C,0x76,0xE4,0x20,0x16,0xE2,0x20,0xC0,
+0xFF,0xB0,0x0B,0x60,0x20,0x16,0xE2,0xA5,0x49,0x20,0xC3,0xFF,0x90,0xC6,0x4C,0xF6,
+0xE0,0xA9,0x00,0x20,0xBD,0xFF,0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x03,0xE2,
+0x20,0x54,0xE2,0x20,0x03,0xE2,0x20,0xFD,0xE1,0xA0,0x00,0x86,0x49,0x20,0xBA,0xFF,
+0x20,0x03,0xE2,0x20,0xFD,0xE1,0x8A,0xA8,0xA6,0x49,0x4C,0xBA,0xFF,0x20,0x0B,0xE2,
+0x4C,0x9E,0xD7,0x20,0x79,0x00,0xD0,0x02,0x68,0x68,0x60,0x20,0xFD,0xCE,0x20,0x79,
+0x00,0xD0,0xF7,0x4C,0x08,0xCF,0xA9,0x00,0x20,0xBD,0xFF,0x20,0x0E,0xE2,0x20,0x9E,
+0xD7,0x86,0x49,0x8A,0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x03,0xE2,0x20,0xFD,
+0xE1,0x86,0x4A,0xA0,0x00,0xA5,0x49,0xE0,0x03,0x90,0x01,0x88,0x20,0xBA,0xFF,0x20,
+0x03,0xE2,0x20,0xFD,0xE1,0x8A,0xA8,0xA6,0x4A,0xA5,0x49,0x20,0xBA,0xFF,0x20,0x03,
+0xE2,0x20,0x0B,0xE2,0x20,0x9E,0xCD,0x20,0xA3,0xD6,0xA6,0x22,0xA4,0x23,0x4C,0xBD,
+0xFF,0xA9,0xDD,0xA0,0xE2,0x20,0x67,0xD8,0x20,0x0C,0xDC,0xA9,0xE2,0xA0,0xE2,0xA6,
+0x6E,0x20,0x07,0xDB,0x20,0x0C,0xDC,0x20,0xCC,0xDC,0xA9,0x00,0x85,0x6F,0x20,0x53,
+0xD8,0xA9,0xE7,0xA0,0xE2,0x20,0x50,0xD8,0xA5,0x66,0x48,0x10,0x0D,0x20,0x49,0xD8,
+0xA5,0x66,0x30,0x09,0xA5,0x12,0x49,0xFF,0x85,0x12,0x20,0xB4,0xDF,0xA9,0xE7,0xA0,
+0xE2,0x20,0x67,0xD8,0x68,0x10,0x03,0x20,0xB4,0xDF,0xA9,0xEC,0xA0,0xE2,0x4C,0x40,
+0xE0,0x20,0xCA,0xDB,0xA9,0x00,0x85,0x12,0x20,0x68,0xE2,0xA2,0x4E,0xA0,0x00,0x20,
+0xF3,0xE0,0xA9,0x57,0xA0,0x00,0x20,0xA2,0xDB,0xA9,0x00,0x85,0x66,0xA5,0x12,0x20,
+0xD9,0xE2,0xA9,0x4E,0xA0,0x00,0x4C,0x0F,0xDB,0x48,0x4C,0x9A,0xE2,0x81,0x49,0x0F,
+0xDA,0xA2,0x83,0x49,0x0F,0xDA,0xA2,0x7F,0x00,0x00,0x00,0x00,0x05,0x84,0xE6,0x1A,
+0x2D,0x1B,0x86,0x28,0x07,0xFB,0xF8,0x87,0x99,0x68,0x89,0x01,0x87,0x23,0x35,0xDF,
+0xE1,0x86,0xA5,0x5D,0xE7,0x28,0x83,0x49,0x0F,0xDA,0xA2,0xA5,0x66,0x48,0x10,0x03,
+0x20,0xB4,0xDF,0xA5,0x61,0x48,0xC9,0x81,0x90,0x07,0xA9,0xBC,0xA0,0xD9,0x20,0x0F,
+0xDB,0xA9,0x3B,0xA0,0xE3,0x20,0x40,0xE0,0x68,0xC9,0x81,0x90,0x07,0xA9,0xDD,0xA0,
+0xE2,0x20,0x50,0xD8,0x68,0x10,0x03,0x4C,0xB4,0xDF,0x60,0x0B,0x76,0xB3,0x83,0xBD,
+0xD3,0x79,0x1E,0xF4,0xA6,0xF5,0x7B,0x83,0xFC,0xB0,0x10,0x7C,0x0C,0x1F,0x67,0xCA,
+0x7C,0xDE,0x53,0xCB,0xC1,0x7D,0x14,0x64,0x70,0x4C,0x7D,0xB7,0xEA,0x51,0x7A,0x7D,
+0x63,0x30,0x88,0x7E,0x7E,0x92,0x44,0x99,0x3A,0x7E,0x4C,0xCC,0x91,0xC7,0x7F,0xAA,
+0xAA,0xAA,0x13,0x81,0x00,0x00,0x00,0x00,0x20,0x5B,0xE4,0x20,0xA4,0xE3,0x20,0x04,
+0xE4,0xA2,0xFB,0x9A,0x4C,0x74,0xC4,0xE6,0x7A,0xD0,0x02,0xE6,0x7B,0xAD,0x60,0xEA,
+0xC9,0x3A,0xB0,0x0A,0xC9,0x20,0xF0,0xEF,0x38,0xE9,0x30,0x38,0xE9,0xD0,0x60,0x80,
+0x4F,0xC7,0x52,0x58,0xA9,0x4C,0x85,0x54,0x85,0x00,0xA9,0x48,0xA0,0xD2,0x85,0x01,
+0x84,0x02,0xA9,0x91,0xA0,0xD3,0x85,0x05,0x84,0x06,0xA9,0xAA,0xA0,0xD1,0x85,0x03,
+0x84,0x04,0xA2,0x1C,0xBD,0x87,0xE3,0x95,0x73,0xCA,0x10,0xF8,0xA9,0x03,0x85,0x53,
+0xA9,0x00,0x85,0x68,0x85,0x13,0x85,0x18,0xA2,0x01,0x8E,0xFD,0x01,0x8E,0xFC,0x01,
+0xA2,0x19,0x86,0x16,0x38,0x20,0x9C,0xFF,0x86,0x2B,0x84,0x2C,0x38,0x20,0x99,0xFF,
+0x86,0x37,0x84,0x38,0x86,0x33,0x84,0x34,0xA0,0x00,0x98,0x91,0x2B,0xE6,0x2B,0xD0,
+0x02,0xE6,0x2C,0x60,0xA5,0x2B,0xA4,0x2C,0x20,0x08,0xC4,0xA9,0x36,0xA0,0xE4,0x20,
+0x1E,0xCB,0xA5,0x37,0x38,0xE5,0x2B,0xAA,0xA5,0x38,0xE5,0x2C,0x20,0xCD,0xDD,0xA9,
+0x29,0xA0,0xE4,0x20,0x1E,0xCB,0x4C,0x44,0xC6,0x20,0x42,0x59,0x54,0x45,0x53,0x20,
+0x46,0x52,0x45,0x45,0x0D,0x00,0x93,0x2A,0x2A,0x2A,0x2A,0x20,0x43,0x42,0x4D,0x20,
+0x42,0x41,0x53,0x49,0x43,0x20,0x56,0x32,0x20,0x2A,0x2A,0x2A,0x2A,0x0D,0x00,0x3A,
+0xC4,0x83,0xC4,0x7C,0xC5,0x1A,0xC7,0xE4,0xC7,0x86,0xCE,0xA2,0x0B,0xBD,0x4F,0xE4,
+0x9D,0x00,0x03,0xCA,0x10,0xF7,0x60,0x20,0xCC,0xFF,0xA9,0x00,0x85,0x13,0x20,0x7A,
+0xC6,0x58,0x4C,0x74,0xC4,0x41,0x20,0x33,0xC5,0x4C,0x77,0xC6,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xAD,0x2C,0x91,0x29,0xDF,0x8D,0x2C,0x91,0x60,0xAD,0x2C,0x91,0x09,0x20,0x8D,0x2C,
+0x91,0x60,0xAD,0x1F,0x91,0xCD,0x1F,0x91,0xD0,0xF8,0x4A,0x60,0xA6,0xB9,0x4C,0x47,
+0xF6,0x8A,0xD0,0x08,0xA5,0xC3,0x85,0xAE,0xA5,0xC4,0x85,0xAF,0x4C,0x6A,0xF6,0x20,
+0xE3,0xF8,0x90,0x03,0x68,0xA9,0x00,0x4C,0x9E,0xF3,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xA2,0x10,0xA0,0x91,0x60,0xA2,0x16,0xA0,0x17,0x60,0xB0,0x07,0x86,0xD6,0x84,0xD3,
+0x20,0x87,0xE5,0xA6,0xD6,0xA4,0xD3,0x60,0x20,0xBB,0xE5,0xAD,0x88,0x02,0x29,0xFD,
+0x0A,0x0A,0x09,0x80,0x8D,0x05,0x90,0xAD,0x88,0x02,0x29,0x02,0xF0,0x08,0xA9,0x80,
+0x0D,0x02,0x90,0x8D,0x02,0x90,0xA9,0x00,0x8D,0x91,0x02,0x85,0xCF,0xA9,0xDC,0x8D,
+0x8F,0x02,0xA9,0xEB,0x8D,0x90,0x02,0xA9,0x0A,0x8D,0x89,0x02,0x8D,0x8C,0x02,0xA9,
+0x06,0x8D,0x86,0x02,0xA9,0x04,0x8D,0x8B,0x02,0xA9,0x0C,0x85,0xCD,0x85,0xCC,0xAD,
+0x88,0x02,0x09,0x80,0xA8,0xA9,0x00,0xAA,0x94,0xD9,0x18,0x69,0x16,0x90,0x01,0xC8,
+0xE8,0xE0,0x18,0xD0,0xF3,0xA9,0xFF,0x95,0xD9,0xA2,0x16,0x20,0x8D,0xEA,0xCA,0x10,
+0xFA,0xA0,0x00,0x84,0xD3,0x84,0xD6,0xA6,0xD6,0xA5,0xD3,0xB4,0xD9,0x30,0x08,0x18,
+0x69,0x16,0x85,0xD3,0xCA,0x10,0xF4,0xB5,0xD9,0x29,0x03,0x0D,0x88,0x02,0x85,0xD2,
+0xBD,0xFD,0xED,0x85,0xD1,0xA9,0x15,0xE8,0xB4,0xD9,0x30,0x06,0x18,0x69,0x16,0xE8,
+0x10,0xF6,0x85,0xD5,0x60,0x20,0xBB,0xE5,0x4C,0x81,0xE5,0xA9,0x03,0x85,0x9A,0xA9,
+0x00,0x85,0x99,0xA2,0x10,0xBD,0xE3,0xED,0x9D,0xFF,0x8F,0xCA,0xD0,0xF7,0x60,0xAC,
+0x77,0x02,0xA2,0x00,0xBD,0x78,0x02,0x9D,0x77,0x02,0xE8,0xE4,0xC6,0xD0,0xF5,0xC6,
+0xC6,0x98,0x58,0x18,0x60,0x20,0x42,0xE7,0xA5,0xC6,0x85,0xCC,0x8D,0x92,0x02,0xF0,
+0xF7,0x78,0xA5,0xCF,0xF0,0x0C,0xA5,0xCE,0xAE,0x87,0x02,0xA0,0x00,0x84,0xCF,0x20,
+0xA1,0xEA,0x20,0xCF,0xE5,0xC9,0x83,0xD0,0x10,0xA2,0x09,0x78,0x86,0xC6,0xBD,0xF3,
+0xED,0x9D,0x76,0x02,0xCA,0xD0,0xF7,0xF0,0xCF,0xC9,0x0D,0xD0,0xC8,0xA4,0xD5,0x84,
+0xD0,0xB1,0xD1,0xC9,0x20,0xD0,0x03,0x88,0xD0,0xF7,0xC8,0x84,0xC8,0xA0,0x00,0x8C,
+0x92,0x02,0x84,0xD3,0x84,0xD4,0xA5,0xC9,0x30,0x1D,0xA6,0xD6,0x20,0x19,0xE7,0xE4,
+0xC9,0xD0,0x14,0xD0,0x12,0xA5,0xCA,0x85,0xD3,0xC5,0xC8,0x90,0x0A,0xB0,0x42,0x98,
+0x48,0x8A,0x48,0xA5,0xD0,0xF0,0x91,0xA4,0xD3,0xB1,0xD1,0xEA,0xEA,0xEA,0xEA,0xEA,
+0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,0xEA,
+0xEA,0xEA,0x85,0xD7,0x29,0x3F,0x06,0xD7,0x24,0xD7,0x10,0x02,0x09,0x80,0x90,0x04,
+0xA6,0xD4,0xD0,0x04,0x70,0x02,0x09,0x40,0xE6,0xD3,0x20,0xB8,0xE6,0xC4,0xC8,0xD0,
+0x17,0xA9,0x00,0x85,0xD0,0xA9,0x0D,0xA6,0x99,0xE0,0x03,0xF0,0x06,0xA6,0x9A,0xE0,
+0x03,0xF0,0x03,0x20,0x42,0xE7,0xA9,0x0D,0x85,0xD7,0x68,0xAA,0x68,0xA8,0xA5,0xD7,
+0xC9,0xDE,0xD0,0x02,0xA9,0xFF,0x18,0x60,0xC9,0x22,0xD0,0x08,0xA5,0xD4,0x49,0x01,
+0x85,0xD4,0xA9,0x22,0x60,0x09,0x40,0xA6,0xC7,0xF0,0x02,0x09,0x80,0xA6,0xD8,0xF0,
+0x02,0xC6,0xD8,0xAE,0x86,0x02,0x20,0xA1,0xEA,0x20,0xEA,0xE6,0x68,0xA8,0xA5,0xD8,
+0xF0,0x02,0x46,0xD4,0x68,0xAA,0x68,0x18,0x58,0x60,0x20,0xFA,0xE8,0xE6,0xD3,0xA5,
+0xD5,0xC5,0xD3,0xB0,0x37,0xC9,0x57,0xF0,0x2A,0xAD,0x92,0x02,0xF0,0x03,0x4C,0xF0,
+0xE9,0xA6,0xD6,0xE0,0x17,0x90,0x07,0x20,0x75,0xE9,0xC6,0xD6,0xA6,0xD6,0x16,0xD9,
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+0x60,0x38,0xA5,0xAC,0xE5,0xAE,0xA5,0xAD,0xE5,0xAF,0x60,0xE6,0xAC,0xD0,0x02,0xE6,
+0xAD,0x60,0xA2,0xFF,0x78,0x9A,0xD8,0x20,0x3F,0xFD,0xD0,0x03,0x6C,0x00,0xA0,0x20,
+0x8D,0xFD,0x20,0x52,0xFD,0x20,0xF9,0xFD,0x20,0x18,0xE5,0x58,0x6C,0x00,0xC0,0xA2,
+0x05,0xBD,0x4C,0xFD,0xDD,0x03,0xA0,0xD0,0x03,0xCA,0xD0,0xF5,0x60,0x41,0x30,0xC3,
+0xC2,0xCD,0xA2,0x6D,0xA0,0xFD,0x18,0x86,0xC3,0x84,0xC4,0xA0,0x1F,0xB9,0x14,0x03,
+0xB0,0x02,0xB1,0xC3,0x91,0xC3,0x99,0x14,0x03,0x88,0x10,0xF1,0x60,0xBF,0xEA,0xD2,
+0xFE,0xAD,0xFE,0x0A,0xF4,0x4A,0xF3,0xC7,0xF2,0x09,0xF3,0xF3,0xF3,0x0E,0xF2,0x7A,
+0xF2,0x70,0xF7,0xF5,0xF1,0xEF,0xF3,0xD2,0xFE,0x49,0xF5,0x85,0xF6,0xA9,0x00,0xAA,
+0x95,0x00,0x9D,0x00,0x02,0x9D,0x00,0x03,0xE8,0xD0,0xF5,0xA2,0x3C,0xA0,0x03,0x86,
+0xB2,0x84,0xB3,0x85,0xC1,0x85,0x97,0x8D,0x81,0x02,0xA8,0xA9,0x04,0x85,0xC2,0xE6,
+0xC1,0xD0,0x02,0xE6,0xC2,0x20,0x91,0xFE,0xA5,0x97,0xF0,0x22,0xB0,0xF1,0xA4,0xC2,
+0xA6,0xC1,0xC0,0x20,0x90,0x25,0xC0,0x21,0xB0,0x08,0xA0,0x1E,0x8C,0x88,0x02,0x4C,
+0x7B,0xFE,0xA9,0x12,0x8D,0x82,0x02,0xA9,0x10,0x8D,0x88,0x02,0xD0,0xF1,0x90,0xCF,
+0xA5,0xC2,0x8D,0x82,0x02,0x85,0x97,0xC9,0x11,0x90,0xC4,0x20,0xC3,0xE5,0x4C,0xEB,
+0xFD,0xA8,0xFC,0x0B,0xFC,0xBF,0xEA,0x8E,0xF9,0xA9,0x7F,0x8D,0x1E,0x91,0x8D,0x2E,
+0x91,0xA9,0x40,0x8D,0x2B,0x91,0xA9,0x40,0x8D,0x1B,0x91,0xA9,0xFE,0x8D,0x1C,0x91,
+0xA9,0xDE,0x8D,0x2C,0x91,0xA2,0x00,0x8E,0x12,0x91,0xA2,0xFF,0x8E,0x22,0x91,0xA2,
+0x00,0x8E,0x23,0x91,0xA2,0x80,0x8E,0x13,0x91,0xA2,0x00,0x8E,0x1F,0x91,0x20,0x84,
+0xEF,0xA9,0x82,0x8D,0x1E,0x91,0x20,0x8D,0xEF,0xA9,0xC0,0x8D,0x2E,0x91,0xA9,0x89,
+0x8D,0x24,0x91,0xA9,0x42,0x8D,0x25,0x91,0x60,0x85,0xB7,0x86,0xBB,0x84,0xBC,0x60,
+0x85,0xB8,0x86,0xBA,0x84,0xB9,0x60,0xA5,0xBA,0xC9,0x02,0xD0,0x0B,0xAD,0x97,0x02,
+0xA9,0x00,0x8D,0x97,0x02,0x60,0x85,0x9D,0xA5,0x90,0x05,0x90,0x85,0x90,0x60,0x8D,
+0x85,0x02,0x60,0x90,0x06,0xAE,0x83,0x02,0xAC,0x84,0x02,0x8E,0x83,0x02,0x8C,0x84,
+0x02,0x60,0x90,0x06,0xAE,0x81,0x02,0xAC,0x82,0x02,0x8E,0x81,0x02,0x8C,0x82,0x02,
+0x60,0xB1,0xC1,0xAA,0xA9,0x55,0x91,0xC1,0xD1,0xC1,0xD0,0x08,0x6A,0x91,0xC1,0xD1,
+0xC1,0xD0,0x01,0xA9,0x18,0x8A,0x91,0xC1,0x60,0x78,0x6C,0x18,0x03,0x48,0x8A,0x48,
+0x98,0x48,0xAD,0x1D,0x91,0x10,0x48,0x2D,0x1E,0x91,0xAA,0x29,0x02,0xF0,0x1F,0x20,
+0x3F,0xFD,0xD0,0x03,0x6C,0x02,0xA0,0x2C,0x11,0x91,0x20,0x34,0xF7,0x20,0xE1,0xFF,
+0xD0,0x2D,0x20,0x52,0xFD,0x20,0xF9,0xFD,0x20,0x18,0xE5,0x6C,0x02,0xC0,0xAD,0x1E,
+0x91,0x09,0x80,0x48,0xA9,0x7F,0x8D,0x1E,0x91,0x8A,0x29,0x40,0xF0,0x14,0xA9,0xCE,
+0x05,0xB5,0x8D,0x1C,0x91,0xAD,0x14,0x91,0x68,0x8D,0x1E,0x91,0x20,0xA3,0xEF,0x4C,
+0x56,0xFF,0x8A,0x29,0x20,0xF0,0x25,0xAD,0x10,0x91,0x29,0x01,0x85,0xA7,0xAD,0x18,
+0x91,0xE9,0x16,0x6D,0x99,0x02,0x8D,0x18,0x91,0xAD,0x19,0x91,0x6D,0x9A,0x02,0x8D,
+0x19,0x91,0x68,0x8D,0x1E,0x91,0x20,0x36,0xF0,0x4C,0x56,0xFF,0x8A,0x29,0x10,0xF0,
+0x25,0xAD,0x93,0x02,0x29,0x0F,0xD0,0x00,0x0A,0xAA,0xBD,0x5A,0xFF,0x8D,0x18,0x91,
+0xBD,0x5B,0xFF,0x8D,0x19,0x91,0xAD,0x10,0x91,0x68,0x09,0x20,0x29,0xEF,0x8D,0x1E,
+0x91,0xAE,0x98,0x02,0x86,0xA8,0x68,0xA8,0x68,0xAA,0x68,0x40,0x92,0x27,0x40,0x1A,
+0xC6,0x11,0x74,0x0E,0xEE,0x0C,0x45,0x06,0xF1,0x02,0x46,0x01,0xB8,0x00,0x71,0x00,
+0x2A,0x00,0x48,0x8A,0x48,0x98,0x48,0xBA,0xBD,0x04,0x01,0x29,0x10,0xF0,0x03,0x6C,
+0x16,0x03,0x6C,0x14,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x4C,0x52,0xFD,0x4C,0x57,0xFD,
+0x4C,0x66,0xFE,0x4C,0xC0,0xEE,0x4C,0xCE,0xEE,0x4C,0x73,0xFE,0x4C,0x82,0xFE,0x4C,
+0x1E,0xEB,0x4C,0x6F,0xFE,0x4C,0x19,0xEF,0x4C,0xE4,0xEE,0x4C,0xF6,0xEE,0x4C,0x04,
+0xEF,0x4C,0x17,0xEE,0x4C,0x14,0xEE,0x4C,0x57,0xFE,0x4C,0x50,0xFE,0x4C,0x49,0xFE,
+0x6C,0x1A,0x03,0x6C,0x1C,0x03,0x6C,0x1E,0x03,0x6C,0x20,0x03,0x6C,0x22,0x03,0x6C,
+0x24,0x03,0x6C,0x26,0x03,0x4C,0x42,0xF5,0x4C,0x75,0xF6,0x4C,0x67,0xF7,0x4C,0x60,
+0xF7,0x6C,0x28,0x03,0x6C,0x2A,0x03,0x6C,0x2C,0x03,0x4C,0x34,0xF7,0x4C,0x05,0xE5,
+0x4C,0x0A,0xE5,0x4C,0x00,0xE5,0xFF,0xFF,0xFF,0xFF,0xA9,0xFE,0x22,0xFD,0x72,0xFF,
+};
diff --git a/MCUME_pico2/pico20/kernalromp.h b/MCUME_pico2/pico20/kernalromp.h
new file mode 100644
index 0000000..923ee0f
--- /dev/null
+++ b/MCUME_pico2/pico20/kernalromp.h
@@ -0,0 +1,514 @@
+const unsigned char kernalrom[8192] = {
+0x0F,0xDC,0xA5,0x61,0xC9,0x88,0x90,0x03,0x20,0xD4,0xDA,0x20,0xCC,0xDC,0xA5,0x07,
+0x18,0x69,0x81,0xF0,0xF3,0x38,0xE9,0x01,0x48,0xA2,0x05,0xB5,0x69,0xB4,0x61,0x95,
+0x61,0x94,0x69,0xCA,0x10,0xF5,0xA5,0x56,0x85,0x70,0x20,0x53,0xD8,0x20,0xB4,0xDF,
+0xA9,0xC4,0xA0,0xDF,0x20,0x56,0xE0,0xA9,0x00,0x85,0x6F,0x68,0x20,0xB9,0xDA,0x60,
+0x85,0x71,0x84,0x72,0x20,0xCA,0xDB,0xA9,0x57,0x20,0x28,0xDA,0x20,0x5A,0xE0,0xA9,
+0x57,0xA0,0x00,0x4C,0x28,0xDA,0x85,0x71,0x84,0x72,0x20,0xC7,0xDB,0xB1,0x71,0x85,
+0x67,0xA4,0x71,0xC8,0x98,0xD0,0x02,0xE6,0x72,0x85,0x71,0xA4,0x72,0x20,0x28,0xDA,
+0xA5,0x71,0xA4,0x72,0x18,0x69,0x05,0x90,0x01,0xC8,0x85,0x71,0x84,0x72,0x20,0x67,
+0xD8,0xA9,0x5C,0xA0,0x00,0xC6,0x67,0xD0,0xE4,0x60,0x98,0x35,0x44,0x7A,0x00,0x68,
+0x28,0xB1,0x46,0x00,0x20,0x2B,0xDC,0x30,0x37,0xD0,0x20,0x20,0xF3,0xFF,0x86,0x22,
+0x84,0x23,0xA0,0x04,0xB1,0x22,0x85,0x62,0xC8,0xB1,0x22,0x85,0x64,0xA0,0x08,0xB1,
+0x22,0x85,0x63,0xC8,0xB1,0x22,0x85,0x65,0x4C,0xE0,0xE0,0xA9,0x8B,0xA0,0x00,0x20,
+0xA2,0xDB,0xA9,0x8A,0xA0,0xE0,0x20,0x28,0xDA,0xA9,0x8F,0xA0,0xE0,0x20,0x67,0xD8,
+0xA6,0x65,0xA5,0x62,0x85,0x65,0x86,0x62,0xA6,0x63,0xA5,0x64,0x85,0x63,0x86,0x64,
+0xA9,0x00,0x85,0x66,0xA5,0x61,0x85,0x70,0xA9,0x80,0x85,0x61,0x20,0xD7,0xD8,0xA2,
+0x8B,0xA0,0x00,0x4C,0xD4,0xDB,0xC9,0xF0,0xD0,0x07,0x84,0x38,0x86,0x37,0x4C,0x63,
+0xC6,0xAA,0xD0,0x02,0xA2,0x1E,0x4C,0x37,0xC4,0x20,0xD2,0xFF,0xB0,0xE8,0x60,0x20,
+0xCF,0xFF,0xB0,0xE2,0x60,0x20,0xC9,0xFF,0xB0,0xDC,0x60,0x20,0xC6,0xFF,0xB0,0xD6,
+0x60,0x20,0xE4,0xFF,0xB0,0xD0,0x60,0x20,0x8A,0xCD,0x20,0xF7,0xD7,0xA9,0xE1,0x48,
+0xA9,0x43,0x48,0xAD,0x0F,0x03,0x48,0xAD,0x0C,0x03,0xAE,0x0D,0x03,0xAC,0x0E,0x03,
+0x28,0x6C,0x14,0x00,0x08,0x8D,0x0C,0x03,0x8E,0x0D,0x03,0x8C,0x0E,0x03,0x68,0x8D,
+0x0F,0x03,0x60,0x20,0xD1,0xE1,0xA6,0x2D,0xA4,0x2E,0xA9,0x2B,0x20,0xD8,0xFF,0xB0,
+0x95,0x60,0xA9,0x01,0x2C,0xA9,0x00,0x85,0x0A,0x20,0xD1,0xE1,0xA5,0x0A,0xA6,0x2B,
+0xA4,0x2C,0x20,0xD5,0xFF,0xB0,0x57,0xA5,0x0A,0xF0,0x1A,0xA2,0x1C,0x20,0xB7,0xFF,
+0x29,0x10,0xF0,0x03,0x4C,0x37,0xC4,0xA5,0x7A,0xC9,0x02,0xF0,0x07,0xA9,0x64,0xA0,
+0xC3,0x4C,0x1E,0xCB,0x60,0x20,0xB7,0xFF,0x29,0xBF,0xF0,0x05,0xA2,0x1D,0x4C,0x37,
+0xC4,0xA5,0x7B,0xC9,0x02,0xD0,0x0E,0x86,0x2D,0x84,0x2E,0xA9,0x76,0xA0,0xC3,0x20,
+0x1E,0xCB,0x4C,0x2A,0xC5,0x20,0x8E,0xC6,0x4C,0x76,0xE4,0x20,0x16,0xE2,0x20,0xC0,
+0xFF,0xB0,0x0B,0x60,0x20,0x16,0xE2,0xA5,0x49,0x20,0xC3,0xFF,0x90,0xC6,0x4C,0xF6,
+0xE0,0xA9,0x00,0x20,0xBD,0xFF,0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x03,0xE2,
+0x20,0x54,0xE2,0x20,0x03,0xE2,0x20,0xFD,0xE1,0xA0,0x00,0x86,0x49,0x20,0xBA,0xFF,
+0x20,0x03,0xE2,0x20,0xFD,0xE1,0x8A,0xA8,0xA6,0x49,0x4C,0xBA,0xFF,0x20,0x0B,0xE2,
+0x4C,0x9E,0xD7,0x20,0x79,0x00,0xD0,0x02,0x68,0x68,0x60,0x20,0xFD,0xCE,0x20,0x79,
+0x00,0xD0,0xF7,0x4C,0x08,0xCF,0xA9,0x00,0x20,0xBD,0xFF,0x20,0x0E,0xE2,0x20,0x9E,
+0xD7,0x86,0x49,0x8A,0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x03,0xE2,0x20,0xFD,
+0xE1,0x86,0x4A,0xA0,0x00,0xA5,0x49,0xE0,0x03,0x90,0x01,0x88,0x20,0xBA,0xFF,0x20,
+0x03,0xE2,0x20,0xFD,0xE1,0x8A,0xA8,0xA6,0x4A,0xA5,0x49,0x20,0xBA,0xFF,0x20,0x03,
+0xE2,0x20,0x0B,0xE2,0x20,0x9E,0xCD,0x20,0xA3,0xD6,0xA6,0x22,0xA4,0x23,0x4C,0xBD,
+0xFF,0xA9,0xDD,0xA0,0xE2,0x20,0x67,0xD8,0x20,0x0C,0xDC,0xA9,0xE2,0xA0,0xE2,0xA6,
+0x6E,0x20,0x07,0xDB,0x20,0x0C,0xDC,0x20,0xCC,0xDC,0xA9,0x00,0x85,0x6F,0x20,0x53,
+0xD8,0xA9,0xE7,0xA0,0xE2,0x20,0x50,0xD8,0xA5,0x66,0x48,0x10,0x0D,0x20,0x49,0xD8,
+0xA5,0x66,0x30,0x09,0xA5,0x12,0x49,0xFF,0x85,0x12,0x20,0xB4,0xDF,0xA9,0xE7,0xA0,
+0xE2,0x20,0x67,0xD8,0x68,0x10,0x03,0x20,0xB4,0xDF,0xA9,0xEC,0xA0,0xE2,0x4C,0x40,
+0xE0,0x20,0xCA,0xDB,0xA9,0x00,0x85,0x12,0x20,0x68,0xE2,0xA2,0x4E,0xA0,0x00,0x20,
+0xF3,0xE0,0xA9,0x57,0xA0,0x00,0x20,0xA2,0xDB,0xA9,0x00,0x85,0x66,0xA5,0x12,0x20,
+0xD9,0xE2,0xA9,0x4E,0xA0,0x00,0x4C,0x0F,0xDB,0x48,0x4C,0x9A,0xE2,0x81,0x49,0x0F,
+0xDA,0xA2,0x83,0x49,0x0F,0xDA,0xA2,0x7F,0x00,0x00,0x00,0x00,0x05,0x84,0xE6,0x1A,
+0x2D,0x1B,0x86,0x28,0x07,0xFB,0xF8,0x87,0x99,0x68,0x89,0x01,0x87,0x23,0x35,0xDF,
+0xE1,0x86,0xA5,0x5D,0xE7,0x28,0x83,0x49,0x0F,0xDA,0xA2,0xA5,0x66,0x48,0x10,0x03,
+0x20,0xB4,0xDF,0xA5,0x61,0x48,0xC9,0x81,0x90,0x07,0xA9,0xBC,0xA0,0xD9,0x20,0x0F,
+0xDB,0xA9,0x3B,0xA0,0xE3,0x20,0x40,0xE0,0x68,0xC9,0x81,0x90,0x07,0xA9,0xDD,0xA0,
+0xE2,0x20,0x50,0xD8,0x68,0x10,0x03,0x4C,0xB4,0xDF,0x60,0x0B,0x76,0xB3,0x83,0xBD,
+0xD3,0x79,0x1E,0xF4,0xA6,0xF5,0x7B,0x83,0xFC,0xB0,0x10,0x7C,0x0C,0x1F,0x67,0xCA,
+0x7C,0xDE,0x53,0xCB,0xC1,0x7D,0x14,0x64,0x70,0x4C,0x7D,0xB7,0xEA,0x51,0x7A,0x7D,
+0x63,0x30,0x88,0x7E,0x7E,0x92,0x44,0x99,0x3A,0x7E,0x4C,0xCC,0x91,0xC7,0x7F,0xAA,
+0xAA,0xAA,0x13,0x81,0x00,0x00,0x00,0x00,0x20,0x5B,0xE4,0x20,0xA4,0xE3,0x20,0x04,
+0xE4,0xA2,0xFB,0x9A,0x4C,0x74,0xC4,0xE6,0x7A,0xD0,0x02,0xE6,0x7B,0xAD,0x60,0xEA,
+0xC9,0x3A,0xB0,0x0A,0xC9,0x20,0xF0,0xEF,0x38,0xE9,0x30,0x38,0xE9,0xD0,0x60,0x80,
+0x4F,0xC7,0x52,0x58,0xA9,0x4C,0x85,0x54,0x85,0x00,0xA9,0x48,0xA0,0xD2,0x85,0x01,
+0x84,0x02,0xA9,0x91,0xA0,0xD3,0x85,0x05,0x84,0x06,0xA9,0xAA,0xA0,0xD1,0x85,0x03,
+0x84,0x04,0xA2,0x1C,0xBD,0x87,0xE3,0x95,0x73,0xCA,0x10,0xF8,0xA9,0x03,0x85,0x53,
+0xA9,0x00,0x85,0x68,0x85,0x13,0x85,0x18,0xA2,0x01,0x8E,0xFD,0x01,0x8E,0xFC,0x01,
+0xA2,0x19,0x86,0x16,0x38,0x20,0x9C,0xFF,0x86,0x2B,0x84,0x2C,0x38,0x20,0x99,0xFF,
+0x86,0x37,0x84,0x38,0x86,0x33,0x84,0x34,0xA0,0x00,0x98,0x91,0x2B,0xE6,0x2B,0xD0,
+0x02,0xE6,0x2C,0x60,0xA5,0x2B,0xA4,0x2C,0x20,0x08,0xC4,0xA9,0x36,0xA0,0xE4,0x20,
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+0x00,0x85,0xA4,0xA5,0xA3,0x10,0x30,0x30,0xC9,0xA2,0xA6,0x20,0x5D,0xF9,0xA5,0x9B,
+0xD0,0xC3,0x4C,0x56,0xFF,0xA5,0x92,0xF0,0x07,0x30,0x03,0xC6,0xB0,0x2C,0xE6,0xB0,
+0xA9,0x00,0x85,0x92,0xE4,0xD7,0xD0,0x0F,0x8A,0xD0,0xAA,0xA5,0xA9,0x30,0xC7,0xC9,
+0x10,0x90,0xC3,0x85,0x96,0xB0,0xBF,0x8A,0x45,0x9B,0x85,0x9B,0xA5,0xB4,0xF0,0xD2,
+0xC6,0xA3,0x30,0xC5,0x46,0xD7,0x66,0xBF,0xA2,0xDA,0x20,0x5D,0xF9,0x4C,0x56,0xFF,
+0xA5,0x96,0xF0,0x04,0xA5,0xB4,0xF0,0x04,0xA5,0xA3,0x10,0x85,0x46,0xB1,0xA9,0x93,
+0x38,0xE5,0xB1,0x65,0xB0,0x0A,0xAA,0x20,0x5D,0xF9,0xE6,0x9C,0xA5,0xB4,0xD0,0x11,
+0xA5,0x96,0xF0,0x26,0x85,0xA8,0xA9,0x00,0x85,0x96,0xA9,0xC0,0x8D,0x2E,0x91,0x85,
+0xB4,0xA5,0x96,0x85,0xB5,0xF0,0x09,0xA9,0x00,0x85,0xB4,0xA9,0x40,0x8D,0x2E,0x91,
+0xA5,0xBF,0x85,0xBD,0xA5,0xA8,0x05,0xA9,0x85,0xB6,0x4C,0x56,0xFF,0x20,0xDB,0xFB,
+0x85,0x9C,0xA2,0xDA,0x20,0x5D,0xF9,0xA5,0xBE,0xF0,0x02,0x85,0xA7,0xA9,0x0F,0x24,
+0xAA,0x10,0x17,0xA5,0xB5,0xD0,0x0C,0xA6,0xBE,0xCA,0xD0,0x0B,0xA9,0x08,0x20,0x6A,
+0xFE,0xD0,0x04,0xA9,0x00,0x85,0xAA,0x4C,0x56,0xFF,0x70,0x31,0xD0,0x18,0xA5,0xB5,
+0xD0,0xF5,0xA5,0xB6,0xD0,0xF1,0xA5,0xA7,0x4A,0xA5,0xBD,0x30,0x03,0x90,0x18,0x18,
+0xB0,0x15,0x29,0x0F,0x85,0xAA,0xC6,0xAA,0xD0,0xDD,0xA9,0x40,0x85,0xAA,0x20,0xD2,
+0xFB,0xA9,0x00,0x85,0xAB,0xF0,0xD0,0xA9,0x80,0x85,0xAA,0xD0,0xCA,0xA5,0xB5,0xF0,
+0x0A,0xA9,0x04,0x20,0x6A,0xFE,0xA9,0x00,0x4C,0x97,0xFB,0x20,0x11,0xFD,0x90,0x03,
+0x4C,0x95,0xFB,0xA6,0xA7,0xCA,0xF0,0x2D,0xA5,0x93,0xF0,0x0C,0xA0,0x00,0xA5,0xBD,
+0xD1,0xAC,0xF0,0x04,0xA9,0x01,0x85,0xB6,0xA5,0xB6,0xF0,0x4B,0xA2,0x3D,0xE4,0x9E,
+0x90,0x3E,0xA6,0x9E,0xA5,0xAD,0x9D,0x01,0x01,0xA5,0xAC,0x9D,0x00,0x01,0xE8,0xE8,
+0x86,0x9E,0x4C,0x87,0xFB,0xA6,0x9F,0xE4,0x9E,0xF0,0x35,0xA5,0xAC,0xDD,0x00,0x01,
+0xD0,0x2E,0xA5,0xAD,0xDD,0x01,0x01,0xD0,0x27,0xE6,0x9F,0xE6,0x9F,0xA5,0x93,0xF0,
+0x0B,0xA5,0xBD,0xA0,0x00,0xD1,0xAC,0xF0,0x17,0xC8,0x84,0xB6,0xA5,0xB6,0xF0,0x07,
+0xA9,0x10,0x20,0x6A,0xFE,0xD0,0x09,0xA5,0x93,0xD0,0x05,0xA8,0xA5,0xBD,0x91,0xAC,
+0x20,0x1B,0xFD,0xD0,0x3A,0xA9,0x80,0x85,0xAA,0xA6,0xBE,0xCA,0x30,0x02,0x86,0xBE,
+0xC6,0xA7,0xF0,0x08,0xA5,0x9E,0xD0,0x27,0x85,0xBE,0xF0,0x23,0x20,0xCF,0xFC,0x20,
+0xD2,0xFB,0xA0,0x00,0x84,0xAB,0xB1,0xAC,0x45,0xAB,0x85,0xAB,0x20,0x1B,0xFD,0x20,
+0x11,0xFD,0x90,0xF2,0xA5,0xAB,0x45,0xBD,0xF0,0x05,0xA9,0x20,0x20,0x6A,0xFE,0x4C,
+0x56,0xFF,0xA5,0xC2,0x85,0xAD,0xA5,0xC1,0x85,0xAC,0x60,0xA9,0x08,0x85,0xA3,0xA9,
+0x00,0x85,0xA4,0x85,0xA8,0x85,0x9B,0x85,0xA9,0x60,0xA5,0xBD,0x4A,0xA9,0x60,0x90,
+0x02,0xA9,0xB0,0xA2,0x00,0x8D,0x28,0x91,0x8E,0x29,0x91,0xAD,0x20,0x91,0x49,0x08,
+0x8D,0x20,0x91,0x29,0x08,0x60,0x38,0x66,0xAD,0x30,0x3C,0xA5,0xA8,0xD0,0x12,0xA9,
+0x10,0xA2,0x01,0x20,0xF5,0xFB,0xD0,0x2F,0xE6,0xA8,0xA5,0xAD,0x10,0x29,0x4C,0x95,
+0xFC,0xA5,0xA9,0xD0,0x09,0x20,0xF1,0xFB,0xD0,0x1D,0xE6,0xA9,0xD0,0x19,0x20,0xEA,
+0xFB,0xD0,0x14,0xA5,0xA4,0x49,0x01,0x85,0xA4,0xF0,0x0F,0xA5,0xBD,0x49,0x01,0x85,
+0xBD,0x29,0x01,0x45,0x9B,0x85,0x9B,0x4C,0x56,0xFF,0x46,0xBD,0xC6,0xA3,0xA5,0xA3,
+0xF0,0x3A,0x10,0xF3,0x20,0xDB,0xFB,0x58,0xA5,0xA5,0xF0,0x12,0xA2,0x00,0x86,0xD7,
+0xC6,0xA5,0xA6,0xBE,0xE0,0x02,0xD0,0x02,0x09,0x80,0x85,0xBD,0xD0,0xD9,0x20,0x11,
+0xFD,0x90,0x0A,0xD0,0x91,0xE6,0xAD,0xA5,0xD7,0x85,0xBD,0xB0,0xCA,0xA0,0x00,0xB1,
+0xAC,0x85,0xBD,0x45,0xD7,0x85,0xD7,0x20,0x1B,0xFD,0xD0,0xBB,0xA5,0x9B,0x49,0x01,
+0x85,0xBD,0x4C,0x56,0xFF,0xC6,0xBE,0xD0,0x03,0x20,0x08,0xFD,0xA9,0x50,0x85,0xA7,
+0xA2,0x08,0x78,0x20,0xFB,0xFC,0xD0,0xEA,0xA9,0x78,0x20,0xF3,0xFB,0xD0,0xE3,0xC6,
+0xA7,0xD0,0xDF,0x20,0xDB,0xFB,0xC6,0xAB,0x10,0xD8,0xA2,0x0A,0x20,0xFB,0xFC,0x58,
+0xE6,0xAB,0xA5,0xBE,0xF0,0x30,0x20,0xD2,0xFB,0xA2,0x09,0x86,0xA5,0xD0,0x85,0x08,
+0x78,0x20,0x08,0xFD,0xA9,0x7F,0x8D,0x2E,0x91,0xA9,0xF7,0x8D,0x20,0x91,0xA9,0x40,
+0x8D,0x2B,0x91,0x20,0x39,0xFE,0xAD,0xA0,0x02,0xF0,0x09,0x8D,0x15,0x03,0xAD,0x9F,
+0x02,0x8D,0x14,0x03,0x28,0x60,0x20,0xCF,0xFC,0xF0,0x97,0xBD,0xE9,0xFD,0x8D,0x14,
+0x03,0xBD,0xEA,0xFD,0x8D,0x15,0x03,0x60,0xAD,0x1C,0x91,0x09,0x0E,0x8D,0x1C,0x91,
+0x60,0x38,0xA5,0xAC,0xE5,0xAE,0xA5,0xAD,0xE5,0xAF,0x60,0xE6,0xAC,0xD0,0x02,0xE6,
+0xAD,0x60,0xA2,0xFF,0x78,0x9A,0xD8,0x20,0x3F,0xFD,0xD0,0x03,0x6C,0x00,0xA0,0x20,
+0x8D,0xFD,0x20,0x52,0xFD,0x20,0xF9,0xFD,0x20,0x18,0xE5,0x58,0x6C,0x00,0xC0,0xA2,
+0x05,0xBD,0x4C,0xFD,0xDD,0x03,0xA0,0xD0,0x03,0xCA,0xD0,0xF5,0x60,0x41,0x30,0xC3,
+0xC2,0xCD,0xA2,0x6D,0xA0,0xFD,0x18,0x86,0xC3,0x84,0xC4,0xA0,0x1F,0xB9,0x14,0x03,
+0xB0,0x02,0xB1,0xC3,0x91,0xC3,0x99,0x14,0x03,0x88,0x10,0xF1,0x60,0xBF,0xEA,0xD2,
+0xFE,0xAD,0xFE,0x0A,0xF4,0x4A,0xF3,0xC7,0xF2,0x09,0xF3,0xF3,0xF3,0x0E,0xF2,0x7A,
+0xF2,0x70,0xF7,0xF5,0xF1,0xEF,0xF3,0xD2,0xFE,0x49,0xF5,0x85,0xF6,0xA9,0x00,0xAA,
+0x95,0x00,0x9D,0x00,0x02,0x9D,0x00,0x03,0xE8,0xD0,0xF5,0xA2,0x3C,0xA0,0x03,0x86,
+0xB2,0x84,0xB3,0x85,0xC1,0x85,0x97,0x8D,0x81,0x02,0xA8,0xA9,0x04,0x85,0xC2,0xE6,
+0xC1,0xD0,0x02,0xE6,0xC2,0x20,0x91,0xFE,0xA5,0x97,0xF0,0x22,0xB0,0xF1,0xA4,0xC2,
+0xA6,0xC1,0xC0,0x20,0x90,0x25,0xC0,0x21,0xB0,0x08,0xA0,0x1E,0x8C,0x88,0x02,0x4C,
+0x7B,0xFE,0xA9,0x12,0x8D,0x82,0x02,0xA9,0x10,0x8D,0x88,0x02,0xD0,0xF1,0x90,0xCF,
+0xA5,0xC2,0x8D,0x82,0x02,0x85,0x97,0xC9,0x11,0x90,0xC4,0x20,0xC3,0xE5,0x4C,0xEB,
+0xFD,0xA8,0xFC,0x0B,0xFC,0xBF,0xEA,0x8E,0xF9,0xA9,0x7F,0x8D,0x1E,0x91,0x8D,0x2E,
+0x91,0xA9,0x40,0x8D,0x2B,0x91,0xA9,0x40,0x8D,0x1B,0x91,0xA9,0xFE,0x8D,0x1C,0x91,
+0xA9,0xDE,0x8D,0x2C,0x91,0xA2,0x00,0x8E,0x12,0x91,0xA2,0xFF,0x8E,0x22,0x91,0xA2,
+0x00,0x8E,0x23,0x91,0xA2,0x80,0x8E,0x13,0x91,0xA2,0x00,0x8E,0x1F,0x91,0x20,0x84,
+0xEF,0xA9,0x82,0x8D,0x1E,0x91,0x20,0x8D,0xEF,0xA9,0xC0,0x8D,0x2E,0x91,0xA9,0x26,
+0x8D,0x24,0x91,0xA9,0x48,0x8D,0x25,0x91,0x60,0x85,0xB7,0x86,0xBB,0x84,0xBC,0x60,
+0x85,0xB8,0x86,0xBA,0x84,0xB9,0x60,0xA5,0xBA,0xC9,0x02,0xD0,0x0B,0xAD,0x97,0x02,
+0xA9,0x00,0x8D,0x97,0x02,0x60,0x85,0x9D,0xA5,0x90,0x05,0x90,0x85,0x90,0x60,0x8D,
+0x85,0x02,0x60,0x90,0x06,0xAE,0x83,0x02,0xAC,0x84,0x02,0x8E,0x83,0x02,0x8C,0x84,
+0x02,0x60,0x90,0x06,0xAE,0x81,0x02,0xAC,0x82,0x02,0x8E,0x81,0x02,0x8C,0x82,0x02,
+0x60,0xB1,0xC1,0xAA,0xA9,0x55,0x91,0xC1,0xD1,0xC1,0xD0,0x08,0x6A,0x91,0xC1,0xD1,
+0xC1,0xD0,0x01,0xA9,0x18,0x8A,0x91,0xC1,0x60,0x78,0x6C,0x18,0x03,0x48,0x8A,0x48,
+0x98,0x48,0xAD,0x1D,0x91,0x10,0x48,0x2D,0x1E,0x91,0xAA,0x29,0x02,0xF0,0x1F,0x20,
+0x3F,0xFD,0xD0,0x03,0x6C,0x02,0xA0,0x2C,0x11,0x91,0x20,0x34,0xF7,0x20,0xE1,0xFF,
+0xD0,0x2D,0x20,0x52,0xFD,0x20,0xF9,0xFD,0x20,0x18,0xE5,0x6C,0x02,0xC0,0xAD,0x1E,
+0x91,0x09,0x80,0x48,0xA9,0x7F,0x8D,0x1E,0x91,0x8A,0x29,0x40,0xF0,0x14,0xA9,0xCE,
+0x05,0xB5,0x8D,0x1C,0x91,0xAD,0x14,0x91,0x68,0x8D,0x1E,0x91,0x20,0xA3,0xEF,0x4C,
+0x56,0xFF,0x8A,0x29,0x20,0xF0,0x25,0xAD,0x10,0x91,0x29,0x01,0x85,0xA7,0xAD,0x18,
+0x91,0xE9,0x16,0x6D,0x99,0x02,0x8D,0x18,0x91,0xAD,0x19,0x91,0x6D,0x9A,0x02,0x8D,
+0x19,0x91,0x68,0x8D,0x1E,0x91,0x20,0x36,0xF0,0x4C,0x56,0xFF,0x8A,0x29,0x10,0xF0,
+0x25,0xAD,0x93,0x02,0x29,0x0F,0xD0,0x00,0x0A,0xAA,0xBD,0x5A,0xFF,0x8D,0x18,0x91,
+0xBD,0x5B,0xFF,0x8D,0x19,0x91,0xAD,0x10,0x91,0x68,0x09,0x20,0x29,0xEF,0x8D,0x1E,
+0x91,0xAE,0x98,0x02,0x86,0xA8,0x68,0xA8,0x68,0xAA,0x68,0x40,0xE6,0x2A,0x78,0x1C,
+0x49,0x13,0xB1,0x0F,0x0A,0x0E,0xD3,0x06,0x38,0x03,0x6A,0x01,0xD0,0x00,0x83,0x00,
+0x36,0x00,0x48,0x8A,0x48,0x98,0x48,0xBA,0xBD,0x04,0x01,0x29,0x10,0xF0,0x03,0x6C,
+0x16,0x03,0x6C,0x14,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0x4C,0x52,0xFD,0x4C,0x57,0xFD,
+0x4C,0x66,0xFE,0x4C,0xC0,0xEE,0x4C,0xCE,0xEE,0x4C,0x73,0xFE,0x4C,0x82,0xFE,0x4C,
+0x1E,0xEB,0x4C,0x6F,0xFE,0x4C,0x19,0xEF,0x4C,0xE4,0xEE,0x4C,0xF6,0xEE,0x4C,0x04,
+0xEF,0x4C,0x17,0xEE,0x4C,0x14,0xEE,0x4C,0x57,0xFE,0x4C,0x50,0xFE,0x4C,0x49,0xFE,
+0x6C,0x1A,0x03,0x6C,0x1C,0x03,0x6C,0x1E,0x03,0x6C,0x20,0x03,0x6C,0x22,0x03,0x6C,
+0x24,0x03,0x6C,0x26,0x03,0x4C,0x42,0xF5,0x4C,0x75,0xF6,0x4C,0x67,0xF7,0x4C,0x60,
+0xF7,0x6C,0x28,0x03,0x6C,0x2A,0x03,0x6C,0x2C,0x03,0x4C,0x34,0xF7,0x4C,0x05,0xE5,
+0x4C,0x0A,0xE5,0x4C,0x00,0xE5,0xFF,0xFF,0xFF,0xFF,0xA9,0xFE,0x22,0xFD,0x72,0xFF,
+};
diff --git a/MCUME_pico2/pico20/keyboard_osd.h b/MCUME_pico2/pico20/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/pico20/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/pico20/mos6502.cpp b/MCUME_pico2/pico20/mos6502.cpp
new file mode 100644
index 0000000..f623a74
--- /dev/null
+++ b/MCUME_pico2/pico20/mos6502.cpp
@@ -0,0 +1,1478 @@
+#include "mos6502.h"
+#include "MOS6502Memory.h"
+
+	//BusRead Read;
+	//BusWrite Write;
+
+#define Read(location) readWord(location)
+#define Write(location,value) writeWord(location,value)
+
+
+mos6502::mos6502()
+{
+	//Write = (BusWrite)w;
+	//Read = (BusRead)r;
+	Instr instr;
+
+	// fill jump table with ILLEGALs
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_ILLEGAL;
+	for(int i = 0; i < 256; i++)
+	{
+		InstrTable[i] = instr;
+	}
+
+	// insert opcodes
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 2;
+	InstrTable[0x69] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 4;
+	InstrTable[0x6D] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 3;
+	InstrTable[0x65] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 6;
+	InstrTable[0x61] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 6;
+	InstrTable[0x71] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 4;
+	InstrTable[0x75] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 4;
+	InstrTable[0x7D] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_ADC;
+	instr.cycles = 4;
+	InstrTable[0x79] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 2;
+	InstrTable[0x29] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 4;
+	InstrTable[0x2D] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 3;
+	InstrTable[0x25] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 6;
+	InstrTable[0x21] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 5;
+	InstrTable[0x31] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 4;
+	InstrTable[0x35] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 4;
+	InstrTable[0x3D] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_AND;
+	instr.cycles = 4;
+	InstrTable[0x39] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_ASL;
+	instr.cycles = 6;
+	InstrTable[0x0E] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_ASL;
+	instr.cycles = 5;
+	InstrTable[0x06] = instr;
+	instr.addr = &mos6502::Addr_ACC;
+	instr.code = &mos6502::Op_ASL_ACC;
+	instr.cycles = 2;
+	InstrTable[0x0A] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_ASL;
+	instr.cycles = 6;
+	InstrTable[0x16] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_ASL;
+	instr.cycles = 7;
+	InstrTable[0x1E] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BCC;
+	instr.cycles = 2;
+	InstrTable[0x90] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BCS;
+	instr.cycles = 2;
+	InstrTable[0xB0] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BEQ;
+	instr.cycles = 2;
+	InstrTable[0xF0] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_BIT;
+	instr.cycles = 4;
+	InstrTable[0x2C] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_BIT;
+	instr.cycles = 3;
+	InstrTable[0x24] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BMI;
+	instr.cycles = 2;
+	InstrTable[0x30] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BNE;
+	instr.cycles = 2;
+	InstrTable[0xD0] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BPL;
+	instr.cycles = 2;
+	InstrTable[0x10] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_BRK;
+	instr.cycles = 7;
+	InstrTable[0x00] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BVC;
+	instr.cycles = 2;
+	InstrTable[0x50] = instr;
+
+	instr.addr = &mos6502::Addr_REL;
+	instr.code = &mos6502::Op_BVS;
+	instr.cycles = 2;
+	InstrTable[0x70] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_CLC;
+	instr.cycles = 2;
+	InstrTable[0x18] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_CLD;
+	instr.cycles = 2;
+	InstrTable[0xD8] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_CLI;
+	instr.cycles = 2;
+	InstrTable[0x58] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_CLV;
+	instr.cycles = 2;
+	InstrTable[0xB8] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 2;
+	InstrTable[0xC9] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 4;
+	InstrTable[0xCD] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 3;
+	InstrTable[0xC5] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 6;
+	InstrTable[0xC1] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 3;
+	InstrTable[0xD1] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 4;
+	InstrTable[0xD5] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 4;
+	InstrTable[0xDD] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_CMP;
+	instr.cycles = 4;
+	InstrTable[0xD9] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_CPX;
+	instr.cycles = 2;
+	InstrTable[0xE0] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_CPX;
+	instr.cycles = 4;
+	InstrTable[0xEC] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_CPX;
+	instr.cycles = 3;
+	InstrTable[0xE4] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_CPY;
+	instr.cycles = 2;
+	InstrTable[0xC0] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_CPY;
+	instr.cycles = 4;
+	InstrTable[0xCC] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_CPY;
+	instr.cycles = 3;
+	InstrTable[0xC4] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_DEC;
+	instr.cycles = 6;
+	InstrTable[0xCE] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_DEC;
+	instr.cycles = 5;
+	InstrTable[0xC6] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_DEC;
+	instr.cycles = 6;
+	InstrTable[0xD6] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_DEC;
+	instr.cycles = 7;
+	InstrTable[0xDE] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_DEX;
+	instr.cycles = 2;
+	InstrTable[0xCA] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_DEY;
+	instr.cycles = 2;
+	InstrTable[0x88] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 2;
+	InstrTable[0x49] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 4;
+	InstrTable[0x4D] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 3;
+	InstrTable[0x45] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 6;
+	InstrTable[0x41] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 5;
+	InstrTable[0x51] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 4;
+	InstrTable[0x55] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 4;
+	InstrTable[0x5D] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_EOR;
+	instr.cycles = 4;
+	InstrTable[0x59] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_INC;
+	instr.cycles = 6;
+	InstrTable[0xEE] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_INC;
+	instr.cycles = 5;
+	InstrTable[0xE6] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_INC;
+	instr.cycles = 6;
+	InstrTable[0xF6] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_INC;
+	instr.cycles = 7;
+	InstrTable[0xFE] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_INX;
+	instr.cycles = 2;
+	InstrTable[0xE8] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_INY;
+	instr.cycles = 2;
+	InstrTable[0xC8] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_JMP;
+	instr.cycles = 3;
+	InstrTable[0x4C] = instr;
+	instr.addr = &mos6502::Addr_ABI;
+	instr.code = &mos6502::Op_JMP;
+	instr.cycles = 5;
+	InstrTable[0x6C] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_JSR;
+	instr.cycles = 6;
+	InstrTable[0x20] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 2;
+	InstrTable[0xA9] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 4;
+	InstrTable[0xAD] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 3;
+	InstrTable[0xA5] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 6;
+	InstrTable[0xA1] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 5;
+	InstrTable[0xB1] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 4;
+	InstrTable[0xB5] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 4;
+	InstrTable[0xBD] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_LDA;
+	instr.cycles = 4;
+	InstrTable[0xB9] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_LDX;
+	instr.cycles = 2;
+	InstrTable[0xA2] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_LDX;
+	instr.cycles = 4;
+	InstrTable[0xAE] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_LDX;
+	instr.cycles = 3;
+	InstrTable[0xA6] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_LDX;
+	instr.cycles = 4;
+	InstrTable[0xBE] = instr;
+	instr.addr = &mos6502::Addr_ZEY;
+	instr.code = &mos6502::Op_LDX;
+	instr.cycles = 4;
+	InstrTable[0xB6] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_LDY;
+	instr.cycles = 2;
+	InstrTable[0xA0] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_LDY;
+	instr.cycles = 4;
+	InstrTable[0xAC] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_LDY;
+	instr.cycles = 3;
+	InstrTable[0xA4] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_LDY;
+	instr.cycles = 4;
+	InstrTable[0xB4] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_LDY;
+	instr.cycles = 4;
+	InstrTable[0xBC] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_LSR;
+	instr.cycles = 6;
+	InstrTable[0x4E] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_LSR;
+	instr.cycles = 5;
+	InstrTable[0x46] = instr;
+	instr.addr = &mos6502::Addr_ACC;
+	instr.code = &mos6502::Op_LSR_ACC;
+	instr.cycles = 2;
+	InstrTable[0x4A] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_LSR;
+	instr.cycles = 6;
+	InstrTable[0x56] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_LSR;
+	instr.cycles = 7;
+	InstrTable[0x5E] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_NOP;
+	instr.cycles = 2;
+	InstrTable[0xEA] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 2;
+	InstrTable[0x09] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 4;
+	InstrTable[0x0D] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 3;
+	InstrTable[0x05] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 6;
+	InstrTable[0x01] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 5;
+	InstrTable[0x11] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 4;
+	InstrTable[0x15] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 4;
+	InstrTable[0x1D] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_ORA;
+	instr.cycles = 4;
+	InstrTable[0x19] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_PHA;
+	instr.cycles = 3;
+	InstrTable[0x48] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_PHP;
+	instr.cycles = 3;
+	InstrTable[0x08] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_PLA;
+	instr.cycles = 4;
+	InstrTable[0x68] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_PLP;
+	instr.cycles = 4;
+	InstrTable[0x28] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_ROL;
+	instr.cycles = 6;
+	InstrTable[0x2E] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_ROL;
+	instr.cycles = 5;
+	InstrTable[0x26] = instr;
+	instr.addr = &mos6502::Addr_ACC;
+	instr.code = &mos6502::Op_ROL_ACC;
+	instr.cycles = 2;
+	InstrTable[0x2A] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_ROL;
+	instr.cycles = 6;
+	InstrTable[0x36] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_ROL;
+	instr.cycles = 7;
+	InstrTable[0x3E] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_ROR;
+	instr.cycles = 6;
+	InstrTable[0x6E] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_ROR;
+	instr.cycles = 5;
+	InstrTable[0x66] = instr;
+	instr.addr = &mos6502::Addr_ACC;
+	instr.code = &mos6502::Op_ROR_ACC;
+	instr.cycles = 2;
+	InstrTable[0x6A] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_ROR;
+	instr.cycles = 6;
+	InstrTable[0x76] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_ROR;
+	instr.cycles = 7;
+	InstrTable[0x7E] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_RTI;
+	instr.cycles = 6;
+	InstrTable[0x40] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_RTS;
+	instr.cycles = 6;
+	InstrTable[0x60] = instr;
+
+	instr.addr = &mos6502::Addr_IMM;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 2;
+	InstrTable[0xE9] = instr;
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 4;
+	InstrTable[0xED] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 3;
+	InstrTable[0xE5] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 6;
+	InstrTable[0xE1] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 5;
+	InstrTable[0xF1] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 4;
+	InstrTable[0xF5] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 4;
+	InstrTable[0xFD] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_SBC;
+	instr.cycles = 4;
+	InstrTable[0xF9] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_SEC;
+	instr.cycles = 2;
+	InstrTable[0x38] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_SED;
+	instr.cycles = 2;
+	InstrTable[0xF8] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_SEI;
+	instr.cycles = 2;
+	InstrTable[0x78] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 4;
+	InstrTable[0x8D] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 3;
+	InstrTable[0x85] = instr;
+	instr.addr = &mos6502::Addr_INX;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 6;
+	InstrTable[0x81] = instr;
+	instr.addr = &mos6502::Addr_INY;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 6;
+	InstrTable[0x91] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 4;
+	InstrTable[0x95] = instr;
+	instr.addr = &mos6502::Addr_ABX;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 5;
+	InstrTable[0x9D] = instr;
+	instr.addr = &mos6502::Addr_ABY;
+	instr.code = &mos6502::Op_STA;
+	instr.cycles = 5;
+	InstrTable[0x99] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_STX;
+	instr.cycles = 4;
+	InstrTable[0x8E] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_STX;
+	instr.cycles = 3;
+	InstrTable[0x86] = instr;
+	instr.addr = &mos6502::Addr_ZEY;
+	instr.code = &mos6502::Op_STX;
+	instr.cycles = 4;
+	InstrTable[0x96] = instr;
+
+	instr.addr = &mos6502::Addr_ABS;
+	instr.code = &mos6502::Op_STY;
+	instr.cycles = 4;
+	InstrTable[0x8C] = instr;
+	instr.addr = &mos6502::Addr_ZER;
+	instr.code = &mos6502::Op_STY;
+	instr.cycles = 3;
+	InstrTable[0x84] = instr;
+	instr.addr = &mos6502::Addr_ZEX;
+	instr.code = &mos6502::Op_STY;
+	instr.cycles = 4;
+	InstrTable[0x94] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TAX;
+	instr.cycles = 2;
+	InstrTable[0xAA] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TAY;
+	instr.cycles = 2;
+	InstrTable[0xA8] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TSX;
+	instr.cycles = 2;
+	InstrTable[0xBA] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TXA;
+	instr.cycles = 2;
+	InstrTable[0x8A] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TXS;
+	instr.cycles = 2;
+	InstrTable[0x9A] = instr;
+
+	instr.addr = &mos6502::Addr_IMP;
+	instr.code = &mos6502::Op_TYA;
+	instr.cycles = 2;
+	InstrTable[0x98] = instr;
+
+	return;
+}
+
+uint16_t mos6502::Addr_ACC()
+{
+	return 0; // not used
+}
+
+uint16_t mos6502::Addr_IMM()
+{
+	return pc++;
+}
+
+uint16_t mos6502::Addr_ABS()
+{
+	uint16_t addrL;
+	uint16_t addrH;
+	uint16_t addr;
+
+	addrL = Read(pc++);
+	addrH = Read(pc++);
+
+	addr = addrL + (addrH << 8);
+
+	return addr;
+}
+
+uint16_t mos6502::Addr_ZER()
+{
+	return Read(pc++);
+}
+
+uint16_t mos6502::Addr_IMP()
+{
+	return 0; // not used
+}
+
+uint16_t mos6502::Addr_REL()
+{
+	uint16_t offset;
+	uint16_t addr;
+
+	offset = (uint16_t)Read(pc++);
+	if (offset & 0x80) offset |= 0xFF00;
+	addr = pc + (int16_t)offset;
+	return addr;
+}
+
+uint16_t mos6502::Addr_ABI()
+{
+	uint16_t addrL;
+	uint16_t addrH;
+	uint16_t effL;
+	uint16_t effH;
+	uint16_t abs;
+	uint16_t addr;
+
+	addrL = Read(pc++);
+	addrH = Read(pc++);
+
+	abs = (addrH << 8) | addrL;
+
+	effL = Read(abs);
+
+#ifndef CMOS_INDIRECT_JMP_FIX
+	effH = Read((abs & 0xFF00) + ((abs + 1) & 0x00FF) );
+#else
+	effH = Read(abs + 1);
+#endif
+
+	addr = effL + 0x100 * effH;
+
+	return addr;
+}
+
+uint16_t mos6502::Addr_ZEX()
+{
+	uint16_t addr = (Read(pc++) + X) % 256;
+	return addr;
+}
+
+uint16_t mos6502::Addr_ZEY()
+{
+	uint16_t addr = (Read(pc++) + Y) % 256;
+	return addr;
+}
+
+uint16_t mos6502::Addr_ABX()
+{
+	uint16_t addr;
+	uint16_t addrL;
+	uint16_t addrH;
+
+	addrL = Read(pc++);
+	addrH = Read(pc++);
+
+	addr = addrL + (addrH << 8) + X;
+	return addr;
+}
+
+uint16_t mos6502::Addr_ABY()
+{
+	uint16_t addr;
+	uint16_t addrL;
+	uint16_t addrH;
+
+	addrL = Read(pc++);
+	addrH = Read(pc++);
+
+	addr = addrL + (addrH << 8) + Y;
+	return addr;
+}
+
+
+uint16_t mos6502::Addr_INX()
+{
+	uint16_t zeroL;
+	uint16_t zeroH;
+	uint16_t addr;
+
+	zeroL = (Read(pc++) + X) % 256;
+	zeroH = (zeroL + 1) % 256;
+	addr = Read(zeroL) + (Read(zeroH) << 8);
+
+	return addr;
+}
+
+uint16_t mos6502::Addr_INY()
+{
+	uint16_t zeroL;
+	uint16_t zeroH;
+	uint16_t addr;
+
+	zeroL = Read(pc++);
+	zeroH = (zeroL + 1) % 256;
+	addr = Read(zeroL) + (Read(zeroH) << 8) + Y;
+
+	return addr;
+}
+
+void mos6502::Reset()
+{
+	A = 0x00;
+	Y = 0x00;
+	X = 0x00;
+
+	pc = (Read(rstVectorH) << 8) + Read(rstVectorL); // load PC from reset vector
+
+	sp = 0xFD;
+
+	status |= CONSTANT;
+
+	illegalOpcode = false;
+
+	return;
+}
+
+void mos6502::StackPush(uint8_t byte)
+{
+	Write(0x0100 + sp, byte);
+	if(sp == 0x00) sp = 0xFF;
+	else sp--;
+}
+
+uint8_t mos6502::StackPop()
+{
+	if(sp == 0xFF) sp = 0x00;
+	else sp++;
+	return Read(0x0100 + sp);
+}
+
+int mos6502::IRQ()
+{
+	int retval = 0;
+	if(!IF_INTERRUPT())
+	{
+		SET_BREAK(0);
+		StackPush((pc >> 8) & 0xFF);
+		StackPush(pc & 0xFF);
+		StackPush(status);
+		SET_INTERRUPT(1);
+		pc = (Read(irqVectorH) << 8) + Read(irqVectorL);
+		retval = 1;
+	}
+	return retval;
+}
+
+void mos6502::NMI()
+{
+	SET_BREAK(0);
+	StackPush((pc >> 8) & 0xFF);
+	StackPush(pc & 0xFF);
+	StackPush(status);
+	SET_INTERRUPT(1);
+	pc = (Read(nmiVectorH) << 8) + Read(nmiVectorL);
+	return;
+}
+
+uint64_t mos6502::Run(
+	int32_t cyclesRemaining,
+	CycleMethod cycleMethod
+) {
+	uint8_t opcode;
+	Instr instr;
+	uint64_t cycleCount=0;
+
+	while(cyclesRemaining > 0 && !illegalOpcode)
+	{
+		// fetch
+		opcode = Read(pc++);
+
+		// decode
+		instr = InstrTable[opcode];
+
+		// execute
+		Exec(instr);
+		cycleCount += instr.cycles;
+		cyclesRemaining -=
+			cycleMethod == CYCLE_COUNT        ? instr.cycles
+			/* cycleMethod == INST_COUNT */   : 1;
+	}
+	return cycleCount;
+}
+
+void mos6502::Exec(Instr i)
+{
+	uint16_t src = (this->*i.addr)();
+	(this->*i.code)(src);
+}
+
+void mos6502::Op_ILLEGAL(uint16_t src)
+{
+	illegalOpcode = true;
+}
+
+
+void mos6502::Op_ADC(uint16_t src)
+{
+	uint8_t m = Read(src);
+	unsigned int tmp = m + A + (IF_CARRY() ? 1 : 0);
+	SET_ZERO(!(tmp & 0xFF));
+	if (IF_DECIMAL())
+	{
+		if (((A & 0xF) + (m & 0xF) + (IF_CARRY() ? 1 : 0)) > 9) tmp += 6;
+		SET_NEGATIVE(tmp & 0x80);
+		SET_OVERFLOW(!((A ^ m) & 0x80) && ((A ^ tmp) & 0x80));
+		if (tmp > 0x99)
+		{
+			tmp += 96;
+		}
+		SET_CARRY(tmp > 0x99);
+	}
+	else
+	{
+		SET_NEGATIVE(tmp & 0x80);
+		SET_OVERFLOW(!((A ^ m) & 0x80) && ((A ^ tmp) & 0x80));
+		SET_CARRY(tmp > 0xFF);
+	}
+
+	A = tmp & 0xFF;
+	return;
+}
+
+
+
+void mos6502::Op_AND(uint16_t src)
+{
+	uint8_t m = Read(src);
+	uint8_t res = m & A;
+	SET_NEGATIVE(res & 0x80);
+	SET_ZERO(!res);
+	A = res;
+	return;
+}
+
+
+void mos6502::Op_ASL(uint16_t src)
+{
+	uint8_t m = Read(src);
+	SET_CARRY(m & 0x80);
+	m <<= 1;
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Write(src, m);
+	return;
+}
+
+void mos6502::Op_ASL_ACC(uint16_t src)
+{
+	uint8_t m = A;
+	SET_CARRY(m & 0x80);
+	m <<= 1;
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+	return;
+}
+
+void mos6502::Op_BCC(uint16_t src)
+{
+	if (!IF_CARRY())
+	{
+		pc = src;
+	}
+	return;
+}
+
+
+void mos6502::Op_BCS(uint16_t src)
+{
+	if (IF_CARRY())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BEQ(uint16_t src)
+{
+	if (IF_ZERO())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BIT(uint16_t src)
+{
+	uint8_t m = Read(src);
+	uint8_t res = m & A;
+	SET_NEGATIVE(res & 0x80);
+	status = (status & 0x3F) | (uint8_t)(m & 0xC0);
+	SET_ZERO(!res);
+	return;
+}
+
+void mos6502::Op_BMI(uint16_t src)
+{
+	if (IF_NEGATIVE())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BNE(uint16_t src)
+{
+	if (!IF_ZERO())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BPL(uint16_t src)
+{
+	if (!IF_NEGATIVE())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BRK(uint16_t src)
+{
+	pc++;
+	StackPush((pc >> 8) & 0xFF);
+	StackPush(pc & 0xFF);
+	StackPush(status | BREAK);
+	SET_INTERRUPT(1);
+	pc = (Read(irqVectorH) << 8) + Read(irqVectorL);
+	return;
+}
+
+void mos6502::Op_BVC(uint16_t src)
+{
+	if (!IF_OVERFLOW())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_BVS(uint16_t src)
+{
+	if (IF_OVERFLOW())
+	{
+		pc = src;
+	}
+	return;
+}
+
+void mos6502::Op_CLC(uint16_t src)
+{
+	SET_CARRY(0);
+	return;
+}
+
+void mos6502::Op_CLD(uint16_t src)
+{
+	SET_DECIMAL(0);
+	return;
+}
+
+void mos6502::Op_CLI(uint16_t src)
+{
+	SET_INTERRUPT(0);
+	return;
+}
+
+void mos6502::Op_CLV(uint16_t src)
+{
+	SET_OVERFLOW(0);
+	return;
+}
+
+void mos6502::Op_CMP(uint16_t src)
+{
+	unsigned int tmp = A - Read(src);
+	SET_CARRY(tmp < 0x100);
+	SET_NEGATIVE(tmp & 0x80);
+	SET_ZERO(!(tmp & 0xFF));
+	return;
+}
+
+void mos6502::Op_CPX(uint16_t src)
+{
+	unsigned int tmp = X - Read(src);
+	SET_CARRY(tmp < 0x100);
+	SET_NEGATIVE(tmp & 0x80);
+	SET_ZERO(!(tmp & 0xFF));
+	return;
+}
+
+void mos6502::Op_CPY(uint16_t src)
+{
+	unsigned int tmp = Y - Read(src);
+	SET_CARRY(tmp < 0x100);
+	SET_NEGATIVE(tmp & 0x80);
+	SET_ZERO(!(tmp & 0xFF));
+	return;
+}
+
+void mos6502::Op_DEC(uint16_t src)
+{
+	uint8_t m = Read(src);
+	m = (m - 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Write(src, m);
+	return;
+}
+
+void mos6502::Op_DEX(uint16_t src)
+{
+	uint8_t m = X;
+	m = (m - 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	X = m;
+	return;
+}
+
+void mos6502::Op_DEY(uint16_t src)
+{
+	uint8_t m = Y;
+	m = (m - 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Y = m;
+	return;
+}
+
+void mos6502::Op_EOR(uint16_t src)
+{
+	uint8_t m = Read(src);
+	m = A ^ m;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+}
+
+void mos6502::Op_INC(uint16_t src)
+{
+	uint8_t m = Read(src);
+	m = (m + 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Write(src, m);
+}
+
+void mos6502::Op_INX(uint16_t src)
+{
+	uint8_t m = X;
+	m = (m + 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	X = m;
+}
+
+void mos6502::Op_INY(uint16_t src)
+{
+	uint8_t m = Y;
+	m = (m + 1) % 256;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Y = m;
+}
+
+void mos6502::Op_JMP(uint16_t src)
+{
+	pc = src;
+}
+
+void mos6502::Op_JSR(uint16_t src)
+{
+	pc--;
+	StackPush((pc >> 8) & 0xFF);
+	StackPush(pc & 0xFF);
+	pc = src;
+}
+
+void mos6502::Op_LDA(uint16_t src)
+{
+	uint8_t m = Read(src);
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+}
+
+void mos6502::Op_LDX(uint16_t src)
+{
+	uint8_t m = Read(src);
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	X = m;
+}
+
+void mos6502::Op_LDY(uint16_t src)
+{
+	uint8_t m = Read(src);
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Y = m;
+}
+
+void mos6502::Op_LSR(uint16_t src)
+{
+	uint8_t m = Read(src);
+	SET_CARRY(m & 0x01);
+	m >>= 1;
+	SET_NEGATIVE(0);
+	SET_ZERO(!m);
+	Write(src, m);
+}
+
+void mos6502::Op_LSR_ACC(uint16_t src)
+{
+	uint8_t m = A;
+	SET_CARRY(m & 0x01);
+	m >>= 1;
+	SET_NEGATIVE(0);
+	SET_ZERO(!m);
+	A = m;
+}
+
+void mos6502::Op_NOP(uint16_t src)
+{
+	return;
+}
+
+void mos6502::Op_ORA(uint16_t src)
+{
+	uint8_t m = Read(src);
+	m = A | m;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+}
+
+void mos6502::Op_PHA(uint16_t src)
+{
+	StackPush(A);
+	return;
+}
+
+void mos6502::Op_PHP(uint16_t src)
+{
+	StackPush(status | BREAK);
+	return;
+}
+
+void mos6502::Op_PLA(uint16_t src)
+{
+	A = StackPop();
+	SET_NEGATIVE(A & 0x80);
+	SET_ZERO(!A);
+	return;
+}
+
+void mos6502::Op_PLP(uint16_t src)
+{
+	status = StackPop();
+	SET_CONSTANT(1);
+	return;
+}
+
+void mos6502::Op_ROL(uint16_t src)
+{
+	uint16_t m = Read(src);
+	m <<= 1;
+	if (IF_CARRY()) m |= 0x01;
+	SET_CARRY(m > 0xFF);
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Write(src, m);
+	return;
+}
+
+void mos6502::Op_ROL_ACC(uint16_t src)
+{
+	uint16_t m = A;
+	m <<= 1;
+	if (IF_CARRY()) m |= 0x01;
+	SET_CARRY(m > 0xFF);
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+	return;
+}
+
+void mos6502::Op_ROR(uint16_t src)
+{
+	uint16_t m = Read(src);
+	if (IF_CARRY()) m |= 0x100;
+	SET_CARRY(m & 0x01);
+	m >>= 1;
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Write(src, m);
+	return;
+}
+
+void mos6502::Op_ROR_ACC(uint16_t src)
+{
+	uint16_t m = A;
+	if (IF_CARRY()) m |= 0x100;
+	SET_CARRY(m & 0x01);
+	m >>= 1;
+	m &= 0xFF;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+	return;
+}
+
+void mos6502::Op_RTI(uint16_t src)
+{
+	uint8_t lo, hi;
+
+	status = StackPop();
+
+	lo = StackPop();
+	hi = StackPop();
+
+	pc = (hi << 8) | lo;
+	return;
+}
+
+void mos6502::Op_RTS(uint16_t src)
+{
+	uint8_t lo, hi;
+
+	lo = StackPop();
+	hi = StackPop();
+
+	pc = ((hi << 8) | lo) + 1;
+	return;
+}
+
+void mos6502::Op_SBC(uint16_t src)
+{
+	uint8_t m = Read(src);
+	unsigned int tmp = A - m - (IF_CARRY() ? 0 : 1);
+	SET_NEGATIVE(tmp & 0x80);
+	SET_ZERO(!(tmp & 0xFF));
+	SET_OVERFLOW(((A ^ tmp) & 0x80) && ((A ^ m) & 0x80));
+
+	if (IF_DECIMAL())
+	{
+		if ( ((A & 0x0F) - (IF_CARRY() ? 0 : 1)) < (m & 0x0F)) tmp -= 6;
+		if (tmp > 0x99)
+		{
+			tmp -= 0x60;
+		}
+	}
+	SET_CARRY(tmp < 0x100);
+	A = (tmp & 0xFF);
+	return;
+}
+
+void mos6502::Op_SEC(uint16_t src)
+{
+	SET_CARRY(1);
+	return;
+}
+
+void mos6502::Op_SED(uint16_t src)
+{
+	SET_DECIMAL(1);
+	return;
+}
+
+void mos6502::Op_SEI(uint16_t src)
+{
+	SET_INTERRUPT(1);
+	return;
+}
+
+void mos6502::Op_STA(uint16_t src)
+{
+	Write(src, A);
+	return;
+}
+
+void mos6502::Op_STX(uint16_t src)
+{
+	Write(src, X);
+	return;
+}
+
+void mos6502::Op_STY(uint16_t src)
+{
+	Write(src, Y);
+	return;
+}
+
+void mos6502::Op_TAX(uint16_t src)
+{
+	uint8_t m = A;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	X = m;
+	return;
+}
+
+void mos6502::Op_TAY(uint16_t src)
+{
+	uint8_t m = A;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	Y = m;
+	return;
+}
+
+void mos6502::Op_TSX(uint16_t src)
+{
+	uint8_t m = sp;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	X = m;
+	return;
+}
+
+void mos6502::Op_TXA(uint16_t src)
+{
+	uint8_t m = X;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+	return;
+}
+
+void mos6502::Op_TXS(uint16_t src)
+{
+	sp = X;
+	return;
+}
+
+void mos6502::Op_TYA(uint16_t src)
+{
+	uint8_t m = Y;
+	SET_NEGATIVE(m & 0x80);
+	SET_ZERO(!m);
+	A = m;
+	return;
+}
diff --git a/MCUME_pico2/pico20/mos6502.h b/MCUME_pico2/pico20/mos6502.h
new file mode 100644
index 0000000..392d173
--- /dev/null
+++ b/MCUME_pico2/pico20/mos6502.h
@@ -0,0 +1,192 @@
+#ifndef _H_MOS6502
+#define _H_MOS6502
+
+//============================================================================
+// Name        : mos6502
+// Author      : Gianluca Ghettini
+// Version     : 1.0
+// Copyright   :
+// Description : A MOS 6502 CPU emulator written in C++
+//============================================================================
+
+#include <stdint.h>
+
+#define NEGATIVE  0x80
+#define OVERFLOW  0x40
+#define CONSTANT  0x20
+#define BREAK     0x10
+#define DECIMAL   0x08
+#define INTERRUPT 0x04
+#define ZERO      0x02
+#define CARRY     0x01
+
+#define SET_NEGATIVE(x) (x ? (status |= NEGATIVE) : (status &= (~NEGATIVE)) )
+#define SET_OVERFLOW(x) (x ? (status |= OVERFLOW) : (status &= (~OVERFLOW)) )
+#define SET_CONSTANT(x) (x ? (status |= CONSTANT) : (status &= (~CONSTANT)) )
+#define SET_BREAK(x) (x ? (status |= BREAK) : (status &= (~BREAK)) )
+#define SET_DECIMAL(x) (x ? (status |= DECIMAL) : (status &= (~DECIMAL)) )
+#define SET_INTERRUPT(x) (x ? (status |= INTERRUPT) : (status &= (~INTERRUPT)) )
+#define SET_ZERO(x) (x ? (status |= ZERO) : (status &= (~ZERO)) )
+#define SET_CARRY(x) (x ? (status |= CARRY) : (status &= (~CARRY)) )
+
+#define IF_NEGATIVE() ((status & NEGATIVE) ? true : false)
+#define IF_OVERFLOW() ((status & OVERFLOW) ? true : false)
+#define IF_CONSTANT() ((status & CONSTANT) ? true : false)
+#define IF_BREAK() ((status & BREAK) ? true : false)
+#define IF_DECIMAL() ((status & DECIMAL) ? true : false)
+#define IF_INTERRUPT() ((status & INTERRUPT) ? true : false)
+#define IF_ZERO() ((status & ZERO) ? true : false)
+#define IF_CARRY() ((status & CARRY) ? true : false)
+
+
+
+class mos6502
+{
+private:
+	// registers
+	uint8_t A; // accumulator
+	uint8_t X; // X-index
+	uint8_t Y; // Y-index
+
+	// stack pointer
+	uint8_t sp;
+
+	// program counter
+	uint16_t pc;
+
+	// status register
+	uint8_t status;
+
+	typedef void (mos6502::*CodeExec)(uint16_t);
+	typedef uint16_t (mos6502::*AddrExec)();
+
+	struct Instr
+	{
+		AddrExec addr;
+		CodeExec code;
+		uint8_t cycles;
+	};
+
+	Instr InstrTable[256];
+
+	void Exec(Instr i);
+
+	bool illegalOpcode;
+
+	// addressing modes
+	uint16_t Addr_ACC(); // ACCUMULATOR
+	uint16_t Addr_IMM(); // IMMEDIATE
+	uint16_t Addr_ABS(); // ABSOLUTE
+	uint16_t Addr_ZER(); // ZERO PAGE
+	uint16_t Addr_ZEX(); // INDEXED-X ZERO PAGE
+	uint16_t Addr_ZEY(); // INDEXED-Y ZERO PAGE
+	uint16_t Addr_ABX(); // INDEXED-X ABSOLUTE
+	uint16_t Addr_ABY(); // INDEXED-Y ABSOLUTE
+	uint16_t Addr_IMP(); // IMPLIED
+	uint16_t Addr_REL(); // RELATIVE
+	uint16_t Addr_INX(); // INDEXED-X INDIRECT
+	uint16_t Addr_INY(); // INDEXED-Y INDIRECT
+	uint16_t Addr_ABI(); // ABSOLUTE INDIRECT
+
+	// opcodes (grouped as per datasheet)
+	void Op_ADC(uint16_t src);
+	void Op_AND(uint16_t src);
+	void Op_ASL(uint16_t src); 	void Op_ASL_ACC(uint16_t src);
+	void Op_BCC(uint16_t src);
+	void Op_BCS(uint16_t src);
+
+	void Op_BEQ(uint16_t src);
+	void Op_BIT(uint16_t src);
+	void Op_BMI(uint16_t src);
+	void Op_BNE(uint16_t src);
+	void Op_BPL(uint16_t src);
+
+	void Op_BRK(uint16_t src);
+	void Op_BVC(uint16_t src);
+	void Op_BVS(uint16_t src);
+	void Op_CLC(uint16_t src);
+	void Op_CLD(uint16_t src);
+
+	void Op_CLI(uint16_t src);
+	void Op_CLV(uint16_t src);
+	void Op_CMP(uint16_t src);
+	void Op_CPX(uint16_t src);
+	void Op_CPY(uint16_t src);
+
+	void Op_DEC(uint16_t src);
+	void Op_DEX(uint16_t src);
+	void Op_DEY(uint16_t src);
+	void Op_EOR(uint16_t src);
+	void Op_INC(uint16_t src);
+
+	void Op_INX(uint16_t src);
+	void Op_INY(uint16_t src);
+	void Op_JMP(uint16_t src);
+	void Op_JSR(uint16_t src);
+	void Op_LDA(uint16_t src);
+
+	void Op_LDX(uint16_t src);
+	void Op_LDY(uint16_t src);
+	void Op_LSR(uint16_t src); 	void Op_LSR_ACC(uint16_t src);
+	void Op_NOP(uint16_t src);
+	void Op_ORA(uint16_t src);
+
+	void Op_PHA(uint16_t src);
+	void Op_PHP(uint16_t src);
+	void Op_PLA(uint16_t src);
+	void Op_PLP(uint16_t src);
+	void Op_ROL(uint16_t src); 	void Op_ROL_ACC(uint16_t src);
+
+	void Op_ROR(uint16_t src);	void Op_ROR_ACC(uint16_t src);
+	void Op_RTI(uint16_t src);
+	void Op_RTS(uint16_t src);
+	void Op_SBC(uint16_t src);
+	void Op_SEC(uint16_t src);
+	void Op_SED(uint16_t src);
+
+	void Op_SEI(uint16_t src);
+	void Op_STA(uint16_t src);
+	void Op_STX(uint16_t src);
+	void Op_STY(uint16_t src);
+	void Op_TAX(uint16_t src);
+
+	void Op_TAY(uint16_t src);
+	void Op_TSX(uint16_t src);
+	void Op_TXA(uint16_t src);
+	void Op_TXS(uint16_t src);
+	void Op_TYA(uint16_t src);
+
+	void Op_ILLEGAL(uint16_t src);
+
+	// IRQ, reset, NMI vectors
+	static const uint16_t irqVectorH = 0xFFFF;
+	static const uint16_t irqVectorL = 0xFFFE;
+	static const uint16_t rstVectorH = 0xFFFD;
+	static const uint16_t rstVectorL = 0xFFFC;
+	static const uint16_t nmiVectorH = 0xFFFB;
+	static const uint16_t nmiVectorL = 0xFFFA;
+
+	// read/write callbacks
+	//typedef void (*BusWrite)(uint16_t, uint8_t);
+	//typedef uint8_t (*BusRead)(uint16_t);
+	//BusRead Read;
+	//BusWrite Write;
+
+	// stack operations
+	inline void StackPush(uint8_t byte);
+	inline uint8_t StackPop();
+
+public:
+	enum CycleMethod {
+		INST_COUNT,
+		CYCLE_COUNT,
+	};
+	mos6502();
+	void NMI();
+	int IRQ();
+	void Reset();
+	uint64_t Run(
+		int32_t cycles,
+		CycleMethod cycleMethod = CYCLE_COUNT);
+};
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico20/pico20.cpp b/MCUME_pico2/pico20/pico20.cpp
new file mode 100644
index 0000000..1aab42c
--- /dev/null
+++ b/MCUME_pico2/pico20/pico20.cpp
@@ -0,0 +1,182 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+#include "hardware/gpio.h"
+#include "hardware/irq.h"
+#include "hardware/dma.h"
+#include "hardware/sync.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+#include "v20.h"
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);     
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+///    set_sys_clock_khz(240000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(15, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        //uint16_t bClick = emu_DebounceLocalKeys();
+        //emu_Input(bClick);  
+        emu_Step();      
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+#ifdef USE_VGA   
+    tft.waitSync();                   
+#else                      
+    volatile bool vb=vbl; 
+    while (vbl==vb) {};
+#endif
+}
+
+
+/*
+void emu_DrawLine(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+         tft.writeLine(width,height,line, VBuf, palette8);
+#else
+         tft.writeLine(width,height,line, VBuf, palette16);
+#endif      
+    }  
+}  
+
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
diff --git a/MCUME_pico2/pico20/program_config.h b/MCUME_pico2/pico20/program_config.h
new file mode 100644
index 0000000..91f04b3
--- /dev/null
+++ b/MCUME_pico2/pico20/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/pico20/v20.cpp b/MCUME_pico2/pico20/v20.cpp
new file mode 100644
index 0000000..9591bce
--- /dev/null
+++ b/MCUME_pico2/pico20/v20.cpp
@@ -0,0 +1,436 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+
+extern "C" {
+#include "emuapi.h"
+#include "platform_config.h"
+}
+#include "kbd.h"
+
+
+// Vic 20 emulation includes
+#include "mos6502.h"
+#include "MOS6561.h"
+#include "MOS6522.h"
+#include "MOS6502Memory.h"
+#include "kernalromp.h"
+#include "charrom.h"
+#include "basicrom.h"
+
+static mos6502 mos;
+static MOS6561 mos6561;
+static MOS6522 mos6522;
+uint8_t vicmemory[0x10000];;
+
+
+#define VIC20FREQBASE    65535
+
+/* noise magic */
+#define NSHIFT(v, n) (((v)<<(n))|((((v)>>(23-(n)))^(v>>(18-(n))))&((1<<(n))-1)))
+#define NVALUE(v) (noiseLSB[v&0xff]|noiseMID[(v>>8)&0xff]|noiseMSB[(v>>16)&0xff])
+#define NSEED 0x7ffff8
+
+/* Noise tables */
+#define NOISETABLESIZE 256
+static uint8_t noiseMSB[NOISETABLESIZE];
+static uint8_t noiseMID[NOISETABLESIZE];
+static uint8_t noiseLSB[NOISETABLESIZE];
+
+/* needed data for one voice */
+typedef struct voice_s
+{
+  /* counter value */
+  int    f;
+  /* counter step / sample */
+  int    fs;
+  /* noise shift register. Note! rv may be 0 to 15 shifts 'behind' the
+     real noise shift register value. Remaining shifts are done when
+     it is referenced */
+  int    rv;
+} voice_t;
+
+/* needed data for SID */
+struct sound_s
+{
+  /* number of voices */
+  voice_t    v[4];
+  /* 4-bit volume value */
+  uint8_t     vol;
+  /* internal constant used for sample rate dependent calculations */
+  int    speed1;
+};
+
+static sound_s psid;
+
+static void VIC_VOICE_HANDLE(int voice, int value, int shift)
+{
+  int div = 255 - value;
+  if (!div)
+    div = 127;
+  if (!(value & 0x80))
+    psid.v[voice].fs = 0;
+  else
+    psid.v[voice].fs = psid.speed1*VIC20FREQBASE*(1 << shift)/div;
+};
+
+
+void SND_Process(void * stream, int len) {
+  int   o0, o1, o2, o3;
+
+  short * sndbuf =  (short *)stream;
+  for (int i = 0; i < len/2; i++)
+  {
+    /* addfptrs */
+    psid.v[0].f += psid.v[0].fs;
+    psid.v[1].f += psid.v[1].fs;
+    psid.v[2].f += psid.v[2].fs;
+    psid.v[3].f += psid.v[3].fs;
+    /* noise */
+    if (psid.v[3].f < psid.v[3].fs)
+        psid.v[3].rv = NSHIFT(psid.v[3].rv, 16);
+    /* voices */
+    o0 = (psid.v[0].f & 0x80000000) >> 2;
+    o1 = (psid.v[1].f & 0x80000000) >> 2;
+    o2 = (psid.v[2].f & 0x80000000) >> 2;
+    o3 = (int)NVALUE(NSHIFT(psid.v[3].rv, psid.v[3].f >> 28)) << 22;
+    /* sample */
+    uint16_t s = ((int)((o0+o1+o2+o3)>>20)-0x800)*psid.vol;
+    *sndbuf++ =s;
+    *sndbuf++ =s;
+  } 
+}
+
+static char * strext(char * filepath) {
+  int str_len = strlen(filepath);
+  for (int i=0; i<str_len; i++) { 
+    if ( (filepath[i] == '.') && (i != (str_len-1) ) )  {
+      return &filepath[i+1];
+    }  
+  }
+  return filepath;
+}
+
+static void loadROM(char * filepath, uint16_t atMemoryLocation) {
+  uint16_t loadAddress;
+  uint16_t endAddress;
+  int lSize = emu_FileSize(filepath);
+  int f = emu_FileOpen(filepath, "r+b");
+  char * ext = strext(filepath);
+  if ( (ext[0] == 'p') ||  (ext[0] == 'P') ) {
+    unsigned char buffer[2];
+    emu_FileRead((char *)&buffer[0], 2, f);
+    loadAddress = buffer[0] | buffer[1] << 8;
+    endAddress = loadAddress + lSize-2;
+    emu_FileRead((char *)&vicmemory[loadAddress], lSize-2, f);
+  }
+  else {
+    switch (ext[0]) {
+      case '2':
+        loadAddress = 0x2000;
+        break;
+      case '4':
+        loadAddress = 0x4000;
+        break;
+      case '6':
+        loadAddress = 0x6000;
+        break;
+      case 'a':
+      case 'A':
+        loadAddress = 0xA000;
+        break;
+    }
+    endAddress = loadAddress + lSize;  
+    emu_FileRead((char *)&vicmemory[loadAddress], lSize, f);
+  }
+  emu_FileClose(f);
+  // Set basic memory pointers
+  
+  silentWriteDWord(0x2B, loadAddress);
+  silentWriteDWord(0x2D, loadAddress);
+  silentWriteDWord(0x2F, endAddress);
+  silentWriteDWord(0x31, endAddress);
+  silentWriteDWord(0x33, endAddress);
+  silentWriteDWord(0x37, 0xFFFF);
+  silentWriteDWord(0xAE, endAddress);
+  
+}
+
+
+/*VIC-20 KEYBOARD MATRIX
+
+In my implementation, n = 0xF7EF
+
+         (80      40      20      10      08      04      02      01)
+          7f      bf      df      ef      f7      fb      fd      fe
+__
+01  fe    2       q       CBM     Space   RunStop Control Lft_arr 1
+02  fd    4       e       s       z       Shift_L a       w       3
+04  fb    6       t       f       c       x       d       r       5
+08  f7    8       u       h       b       v       g       y       7
+10  ef    0       o       k       m       n       j       i       9
+20  df    -       @       :       .       ,       l       p       +
+40  bf    Home    Up_arr  =       Shift_R /       ;       *       GBP
+80  7f    F7      F5      F3      F1      Down    Right   Return  Del
+--
+*/
+
+const uint32_t ascii2scan[] = {
+ //0 1 2 3 4 5 6 7 8 9 A B C D E F
+   0,0,0,0,0,0,0,0,0,0,0xfd7f,0,0,0xfd7f,0,0, // return                          
+   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0xf7fe, //31:RUNSTOP
+   //sp    !       "       #       $       %       &       '       (       )       *       +       ,       -       .       / 
+   0xeffe ,0x1fefe,0x17ffe,0x1fefd,0x17ffd,0x1fefb,0xfebf,0x1fef7,0x17ff7,0x1feef,0xfdbf ,0xfedf ,0xf7df ,0x7fDf ,0xefdf ,0xf7bf,
+   //0     1       2       3       4       5       6       7       8       9       :       ;       <       =       >       ?
+   0x7fef ,0xfefe ,0x7ffe ,0xfefd ,0x7ffd ,0xfefb ,0x7ffb ,0xfef7 ,0x7ff7 ,0xfeef ,0xdfdf ,0xfbbf ,0x1f7df,0xdfbf ,0x1efdf,0x1f7bf,
+   //@     A       B       C       D       E       F       G       H       I       J       K       L       M       N       O
+   0xbfdf ,0xfbfd ,0xeff7 ,0xeffb ,0xfbfb ,0xbffd ,0xdffb ,0xfbf7 ,0xdff7 ,0xfdef ,0xfbef ,0xdfef ,0xfbdf ,0xefef ,0xf7ef ,0xbfef,
+   //P     Q       R       S       T       U       V       W       X       Y       Z       [       \       ]       ^       _  
+   0xfddf ,0xbffe ,0xfdfb ,0xdffd ,0xbffb ,0xbff7 ,0xf7f7 ,0xfdfd ,0xf7fb ,0xfdf7 ,0xeffd ,0x1dfdf,0xffff ,0x1fbbf,0 ,0,
+   //'     a       b       c       d       e       f       g       h       i       j       k       l       m       n       o
+   0      ,0xfbfd ,0xeff7 ,0xeffb ,0xfbfb ,0xbffd ,0xdffb ,0xfbf7 ,0xdff7 ,0xfdef ,0xfbef ,0xdfef ,0xfbdf ,0xefef ,0xf7ef ,0xbfef,
+   //p     q       r       s       t       u       v       w       x       y       z       {       |       }       ~       DEL  
+   0xfddf ,0xbffe ,0xfdfb ,0xdffd ,0xbffb ,0xbff7 ,0xf7f7 ,0xfdfd ,0xf7fb ,0xfdf7 ,0xeffd ,0,      0 ,     0,      0xfe7f  ,0x1fb7f,
+   //      f1      f2      f3      f4      f5      f6      f7     f8
+   0,      0xef7f, 0x1ef7f, 0xdf7f,0x1df7f,0xbf7f, 0x1bf7f,0x7f7f,0x17f7f,0,0,0,0,0,0,0,  // 128-143
+    //           150:right  left    down   up
+   0,0,0,0,0,0, 0xfb7f,      0x1fb7f, 0xf77f,  0x1f77f,0,0,0,0,0,0   // 144-159 
+};
+
+
+static int ik;
+static int ihk;   // I2C keyboard key
+static int iusbhk;// USB keyboard key
+
+static int pik=0;
+
+
+void v20_Input(int bClick) {
+  ihk = emu_ReadI2CKeyboard();
+  ik  = emu_GetPad(); 
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if ( (key >= KBD_KEY_F1) && (key <= KBD_KEY_F8) ) iusbhk = (key - KBD_KEY_F1) + 0x85; // 133
+  // Specific keys
+  //153,151,150,152,0x7F 31 //U L R D DEL ESC
+  else if (key == KBD_KEY_UP) iusbhk = 0x99; // 153
+  else if (key == KBD_KEY_LEFT) iusbhk = 0x97; // 151
+  else if (key == KBD_KEY_DOWN) iusbhk = 0x98; // 152
+  else if (key == KBD_KEY_RIGHT) iusbhk = 0x96; // 150
+  else if (key == KBD_KEY_BS) iusbhk = 0x7F; // 127
+  else if (key == KBD_KEY_ESC) iusbhk = 0x1F; // 31
+  else 
+    iusbhk = toupper(key);
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+void v20_Init(void)
+{
+
+  // Initialize emulation objects
+  mos.Reset();
+  mos6561.initialize();
+  mos6522.setCpu(&mos);
+  mos6522.initialize();
+
+  // clear memory
+  for(int i=0; i<sizeof(vicmemory); i++) {
+    vicmemory[i] = 0;
+  }
+  // load charrom
+  for(int i=0; i<4096; i++) {
+    vicmemory[0x8000+i] = charrom[i];
+  }
+  // load basic rom
+  for(int i=0; i<8192; i++) {
+    vicmemory[0xC000+i] = basicrom[i];
+  }
+  // load kernal rom
+  for(int i=0; i<8192; i++) {
+    vicmemory[0xE000+i] = kernalrom[i];
+  }
+
+
+#ifdef HAS_SND  
+  psid.speed1 = (1000000 << 8) / 22000;
+  psid.v[3].rv = NSEED;
+  for (int i = 0; i < NOISETABLESIZE; i++)
+  {
+    noiseLSB[i] = (((i>>(7-2))&0x04)|((i>>(4-1))&0x02)|((i>>(2-0))&0x01));
+    noiseMID[i] = (((i>>(13-8-4))&0x10)|((i<<(3-(11-8)))&0x08));
+    noiseMSB[i] = (((i<<(7-(22-16)))&0x80)|((i<<(6-(20-16)))&0x40)
+            |((i<<(5-(16-16)))&0x20));
+  }  
+  emu_sndInit();
+#endif  
+}
+
+
+
+void v20_Start(char * filename)
+{
+  loadROM(filename,0);
+
+  // Reset cpu
+  mos.Reset();
+
+  // Execute boot sequence before doing much else
+  mos.Run(20000);
+}
+
+void v20_Step(void)
+{
+  do  {    
+    // bind emulation to clock speed
+
+    // Cpu clock is four times less than 6561 clock
+    //int cpuCycles = mos.executeInstruction();
+    uint64_t cpuCycles = mos.Run(1);
+    mos6561.tick(1);
+    mos6522.tick();
+    //mos6522.tick();
+
+  /*
+  uint64_t cpuCycles = mos.Run(mos6561.cyclesPerScanline);
+    mos6561.tick(mos6561.cyclesPerScanline);
+    mos6522.tick();
+    mos6522.tick();
+    mos6522.tick();
+    mos6522.tick();
+    mos6522.tick();
+    mos6522.tick();
+    */
+
+  /*
+    // printf("cycles %d\n", cpuCycles);
+    while (cpuCycles) {
+      cpuCycles--;
+      mos6522.tick(); 
+  mos6522.tick();
+    } 
+  */
+
+  } while ((!mos6561.isFrameReady()));
+
+  // Swap buffers if frame ready
+  if (mos6561.isFrameReady()) {
+      mos6561.renderFrame();
+  }    
+
+  // Top basic
+  // Unexpanded
+  //vicmemory[55] = 0;
+  //vicmemory[56] = 0x1E;
+  // +3k
+  //vicmemory[55] = 0;
+  //vicmemory[56] = 0x1E;
+  // +8k
+  //vicmemory[55] = 0;
+  //vicmemory[56] = 0x40;
+  // +16k
+  //vicmemory[55] = 0;
+  //vicmemory[56] = 0x60;
+  // +24k
+  //vicmemory[55] = 0;
+  //vicmemory[56] = 0x80;
+  // Bottom basic ???
+  //vicmemory[51] = 0;
+  //vicmemory[52] = 0x1E;
+
+  emu_DrawVsync();
+
+  int hk=ihk;
+  if (iusbhk) hk = iusbhk;
+
+#if (defined(PICOMPUTER) || defined(PICOZX) || defined(PICOHYPERPET) )
+  if (hk) {
+    int scan = ascii2scan[hk];
+    if (scan & 0x10000) mos6522.setShiftPressed(true);
+    else mos6522.setShiftPressed(false);  
+    mos6522.setKeyPressed(scan & 0xffff);
+  }
+  else {
+    mos6522.setShiftPressed(false);  
+    mos6522.setKeyPressed(0);   
+  }
+#endif
+
+
+  int k=ik; 
+#if (defined(PICOMPUTER) || defined(PICOZX) || defined(PICOHYPERPET) )
+  // Ignore joypad if shift is pressed!!!
+//  if ( !(k & MASK_KEY_USER2) )
+  if ( hk == 0 )
+#endif
+  {
+    if ( !(pik & MASK_JOY2_BTN) && (k & MASK_JOY2_BTN) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Fire, true);
+    }
+    else if ( (pik & MASK_JOY2_BTN) && !(k & MASK_JOY2_BTN) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Fire, false);
+    } 
+    if ( !(pik & MASK_JOY2_UP) && (k & MASK_JOY2_UP) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Up, true);
+    }
+    else if ( (pik & MASK_JOY2_UP) && !(k & MASK_JOY2_UP) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Up, false);
+    } 
+    if ( !(pik & MASK_JOY2_DOWN) && (k & MASK_JOY2_DOWN) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Down, true);
+    }
+    else if ( (pik & MASK_JOY2_DOWN) && !(k & MASK_JOY2_DOWN) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Down, false);
+    } 
+    if ( !(pik & MASK_JOY2_RIGHT) && (k & MASK_JOY2_RIGHT) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Left, true);
+    }
+    else if ( (pik & MASK_JOY2_RIGHT) && !(k & MASK_JOY2_RIGHT) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Left, false);
+    } 
+    if ( !(pik & MASK_JOY2_LEFT) && (k & MASK_JOY2_LEFT) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Right, true);
+    }
+    else if ( (pik & MASK_JOY2_LEFT) && !(k & MASK_JOY2_LEFT) ) {
+      mos6522.setJoyStickPressed(MOS6522::Vic20JoyStickButton::Right, false);
+    } 
+  }  
+
+#if (defined(PICOMPUTER) || defined(PICOZX) || defined(PICOHYPERPET))
+#else
+  if ( !(pik & MASK_KEY_USER1) && (k & MASK_KEY_USER1) ) {
+    mos6522.setKeyPressed(0xEF7F);
+    mos6522.setShiftPressed(true);  
+  }
+  else if ( (pik & MASK_KEY_USER1) && !(k & MASK_KEY_USER1) ) {
+    mos6522.setShiftPressed(false);  
+    mos6522.setKeyPressed(0);
+  } 
+
+  if ( !(pik & MASK_KEY_USER2) && (k & MASK_KEY_USER2) ) {
+    mos6522.setShiftPressed(false);  
+    mos6522.setKeyPressed(ascii2scan['1']);
+  }
+  else if ( (pik & MASK_KEY_USER2) && !(k & MASK_KEY_USER2) ) {
+    mos6522.setShiftPressed(false);  
+    mos6522.setKeyPressed(0);
+  }
+#endif
+  pik = k;
+
+
+  VIC_VOICE_HANDLE(0, vicmemory[mos6561.Audio1Register], 0);
+  VIC_VOICE_HANDLE(1, vicmemory[mos6561.Audio2Register], 1);
+  VIC_VOICE_HANDLE(2, vicmemory[mos6561.Audio3Register], 2);
+  VIC_VOICE_HANDLE(3, vicmemory[mos6561.Audio4Register], 0);
+  int vol = (vicmemory[mos6561.AudioVolRegister] & 0x0f);
+  psid.vol = vol;
+}
+
+
+ 
diff --git a/MCUME_pico2/pico20/v20.h b/MCUME_pico2/pico20/v20.h
new file mode 100644
index 0000000..e0af4cf
--- /dev/null
+++ b/MCUME_pico2/pico20/v20.h
@@ -0,0 +1,5 @@
+extern void v20_Init(void);
+extern void v20_Step(void);
+extern void v20_Start(char * filename);
+extern void v20_Input(int key);
+
diff --git a/MCUME_pico2/pico64/.DS_Store b/MCUME_pico2/pico64/.DS_Store
new file mode 100644
index 0000000..88fa3ae
Binary files /dev/null and b/MCUME_pico2/pico64/.DS_Store differ
diff --git a/MCUME_pico2/pico64/IntervalTimer.h b/MCUME_pico2/pico64/IntervalTimer.h
new file mode 100755
index 0000000..740421e
--- /dev/null
+++ b/MCUME_pico2/pico64/IntervalTimer.h
@@ -0,0 +1,131 @@
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2017 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+ /*
+ 
+ Added :
+ 
+ - void setIntervalFast(float microseconds) 
+ - bool setInterval(float microseconds) 
+ 
+ F.B.
+ 
+ */
+ 
+#ifndef __INTERVALTIMERX_H__
+#define __INTERVALTIMERX_H__
+
+//#include "kinetis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+class MyIntervalTimer {
+private:
+	static const uint32_t MAX_PERIOD = UINT32_MAX / (F_BUS / 1000000.0);
+public:
+	MyIntervalTimer() {
+		//channel = NULL;
+		//nvic_priority = 128;
+	}
+	~MyIntervalTimer() {
+		end();
+	}
+	/*
+	bool begin(void (*funct)(), unsigned int microseconds) {
+		if (microseconds == 0 || microseconds > MAX_PERIOD) return false;
+		uint32_t cycles = (F_BUS / 1000000) * microseconds - 1;
+		if (cycles < 36) return false;
+		return beginCycles(funct, cycles);
+	}
+	bool begin(void (*funct)(), int microseconds) {
+		if (microseconds < 0) return false;
+		return begin(funct, (unsigned int)microseconds);
+	}
+	bool begin(void (*funct)(), unsigned long microseconds) {
+		return begin(funct, (unsigned int)microseconds);
+	}
+	bool begin(void (*funct)(), long microseconds) {
+		return begin(funct, (int)microseconds);
+	}
+	bool begin(void (*funct)(), float microseconds) {
+		if (microseconds <= 0 || microseconds > MAX_PERIOD) return false;
+		uint32_t cycles = (float)(F_BUS / 1000000) * microseconds - 0.5;
+		if (cycles < 36) return false;
+		return beginCycles(funct, cycles);
+	}
+	bool begin(void (*funct)(), double microseconds) {
+		return begin(funct, (float)microseconds);
+	}
+	*/
+	void setIntervalFast(float microseconds) { /*NEW*/
+		uint32_t cycles = (float)(F_BUS / 1000000) * microseconds - 0.5;
+		//channel->LDVAL = cycles;		
+	}	
+	/*
+	bool setInterval(float microseconds) { 
+		//if (!channel) return false;
+		if (microseconds <= 0 || microseconds > MAX_PERIOD) return false;		
+		setIntervalFast(microseconds);
+		return true;		
+	}
+	*/
+	void end() {};
+	/*
+	void priority(uint8_t n) {
+		nvic_priority = n;
+		if (channel) {
+			int index = channel - KINETISK_PIT_CHANNELS;
+			//NVIC_SET_PRIORITY(IRQ_PIT_CH0 + index, nvic_priority);
+		}
+	}
+	*/
+	//operator IRQ_NUMBER_t() {
+		/*
+		if (channel) {
+			int index = channel - KINETISK_PIT_CHANNELS;
+			return (IRQ_NUMBER_t)(IRQ_PIT_CH0 + index);
+		}
+		*/
+		//return (IRQ_NUMBER_t)NVIC_NUM_INTERRUPTS;
+	//}
+private:
+	//KINETISK_PIT_CHANNEL_t *channel;
+	//uint8_t nvic_priority;
+	bool beginCycles(void (*funct)(), uint32_t cycles);
+
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico64/Teensy64.h b/MCUME_pico2/pico64/Teensy64.h
new file mode 100644
index 0000000..59e710d
--- /dev/null
+++ b/MCUME_pico2/pico64/Teensy64.h
@@ -0,0 +1,116 @@
+/*
+  Copyright Frank Bösing, 2017
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+#ifndef Teensy64_h_
+#define Teensy64_h_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "pico/stdlib.h"
+
+#define F_CPU 140000000.0
+#define F_BUS 140000000.0
+
+
+#include "settings.h"
+
+#define VERSION "09"
+#define NTSC (!PAL)
+#define USBHOST (!PS2KEYBOARD)
+
+extern "C" {
+  #include "emuapi.h"
+}
+
+inline unsigned long millis() {
+    return (to_ms_since_boot(get_absolute_time ()));
+}
+
+void initMachine();
+void resetMachine() __attribute__ ((noreturn));
+void resetExternal();
+unsigned loadFile(const char *filename);
+
+
+#if PAL == 1
+#define CRYSTAL       	17734475.0f
+#define CLOCKSPEED      ( CRYSTAL / 18.0f) // 985248,61 Hz
+#define CYCLESPERRASTERLINE 63
+#define LINECNT         312 //Rasterlines
+#define VBLANK_FIRST    300
+#define VBLANK_LAST     15
+
+#else
+#define CRYSTAL       	14318180.0f
+#define CLOCKSPEED      ( CRYSTAL / 14.0f) // 1022727,14 Hz
+#define CYCLESPERRASTERLINE 64
+#define LINECNT       	263 //Rasterlines
+#define VBLANK_FIRST    13
+#define VBLANK_LAST     40
+#endif
+
+#define LINEFREQ      			(CLOCKSPEED / CYCLESPERRASTERLINE) //Hz
+#define REFRESHRATE       		(LINEFREQ / LINECNT) //Hz
+#define LINETIMER_DEFAULT_FREQ (1000000.0f/LINEFREQ)
+
+// Exact timing disabled!!! JMH
+//#define MCU_C64_RATIO   ((float)F_CPU / CLOCKSPEED) //MCU Cycles per C64 Cycle
+#define US_C64_CYCLE    (1000000.0f / CLOCKSPEED) // Duration (µs) of a C64 Cycle
+
+#define AUDIOSAMPLERATE     (LINEFREQ * 2)// (~32kHz)
+
+#define ISR_PRIORITY_RASTERLINE   255
+
+
+
+#if 0
+#define WRITE_ATN_CLK_DATA(value) { \
+    digitalWriteFast(PIN_SERIAL_ATN, (~value & 0x08));\//PTA13 IEC ATN 3
+digitalWriteFast(PIN_SERIAL_CLK, (~value & 0x10)); \ //PTA14 IEC CLK 4
+digitalWriteFast(PIN_SERIAL_DATA, (~value & 0x20)); \ //PTA15 IEC DATA 5
+}
+#define READ_CLK_DATA() \
+  ((digitalReadFast(PIN_SERIAL_CLK) << 6) | \
+   (digitalReadFast(PIN_SERIAL_DATA) << 7))
+
+#else
+#define WRITE_ATN_CLK_DATA(value) {}
+#define READ_CLK_DATA() (0)
+#endif
+
+#include "output_dac.h"
+#include "cpu.h"
+#endif
diff --git a/MCUME_pico2/pico64/c64.cpp b/MCUME_pico2/pico64/c64.cpp
new file mode 100644
index 0000000..9dadd15
--- /dev/null
+++ b/MCUME_pico2/pico64/c64.cpp
@@ -0,0 +1,423 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+#include <stdio.h>
+
+extern "C" {
+#include "emuapi.h"
+#include "platform_config.h"
+}
+#include "kbd.h"
+
+#include "Teensy64.h"
+#include <string.h>
+#include <ctype.h>
+
+#ifdef HAS_SND
+#include "reSID.h"
+AudioPlaySID playSID;
+#endif
+
+using namespace std;
+
+
+/* IRAM_ATTR */
+static void oneRasterLine(void) {
+  static unsigned short lc = 1;
+
+  while (true) {
+
+    cpu.lineStartTime = fbmicros(); //get_ccount();
+    cpu.lineCycles = cpu.lineCyclesAbs = 0;
+
+    if (!cpu.exactTiming) {
+      vic_do();
+    } else {
+      vic_do_simple();
+    }
+
+    if (--lc == 0) {
+      lc = LINEFREQ / 10; // 10Hz
+      cia1_checkRTCAlarm();
+      cia2_checkRTCAlarm();
+    }
+
+    //Switch "ExactTiming" Mode off after a while:
+    if (!cpu.exactTiming) break;
+    if ( (fbmicros() - cpu.exactTimingStartTime)*1000 >= EXACTTIMINGDURATION ) {
+      cpu_disableExactTiming();
+      break;
+    }
+  };
+
+}
+
+const uint32_t ascii2scan[] = {
+ //0 1 2 3 4 5 6 7 8 9 A B C D E F
+   0,0,0,0,0,0,0,0,0,0,0x28,0,0,0x28,0,0, // 0x0A: return
+   0x00,0x0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x29, //31:RUNSTOP
+   //sp  !       "     #     $      %      &      '     (        )   *    +    ,    -    .    / 
+   0x2c,0x201e,0x201f,0x2020,0x2021,0x2022,0x2023,0x2024,0x2025,0x2026,0x55,0x57,0x36,0x56,0x37,0x54,
+   //0  1    2    3    4    5    6    7    8    9    :    ;    <      =    >      ?
+   0x27,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x33,0x34,0x2036,0x32,0x2037,0x2054,
+   //@    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O
+   47,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,
+   //P  Q    R    S    T    U    V    W    X    Y    Z    [      \     ]     ^    _  
+   0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x2026,0x31,0x2027,0x00,0x00,
+    //'    a    b    c    d    e    f    g    h    i    j    k    l    m    n    o
+   0,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,
+   //p  w    r    s    t    u    v    w    x    y    z    {      |    } ~  DEL  
+   0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0,     0,   0,0x49,0x204f,
+    // 129:f1 f2      f3     f4      f5     f6      f7     f8 
+   0,  0x3a,  0x3b,   0x3c,  0x3d,   0x3e,  0x3f,   0x40,  0x41,0,0,0,0,0,0,0,  // 128-143
+    //           150:right  left    down   up
+   0,0,0,0,0,0, 0x4f,      0x204f, 0x51,  0x2051,0,0,0,0,0,0   // 144-159 
+};
+
+// we also use USB matrix for the moment
+static const uint8_t keymatrixmap[2][256] = {
+  //Rows:
+  // 0    1     2     3    4     5     6      7     8      9     A     B     C     D     E     F
+  { 0x00, 0x00, 0x00, 0x00, 0x02, 0x08, 0x04, 0x04, 0x02, 0x04, 0x08, 0x08, 0x10, 0x10, 0x10, 0x20, //0x00
+    0x10, 0x10, 0x10, 0x20, 0x80, 0x04, 0x02, 0x04, 0x08, 0x08, 0x02, 0x04, 0x08, 0x02, 0x80, 0x80, //0x10
+    0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x01, 0x80, 0x01, 0x00, 0x80, 0x00, 0x00, 0x20, //0x20
+    0x00, 0x00, 0x40, 0x20, 0x40, 0x00, 0x20, 0x20, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, //0x30
+    0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x80, 0x01, //0x40
+    0x00, 0x01, 0x00, 0x00, 0x40, 0x40, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x50
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x60
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x70
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x90
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xA0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xB0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xC0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xD0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xE0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x40, 0x02
+  }, //0xF0
+  //Columns:
+  // 0    1     2     3    4     5     6      7     8      9     A     B     C     D     E     F
+  { 0x00, 0x00, 0x00, 0x00, 0x04, 0x10, 0x10, 0x04, 0x40, 0x20, 0x04, 0x20, 0x02, 0x04, 0x20, 0x04, //0x00
+    0x10, 0x80, 0x40, 0x02, 0x40, 0x02, 0x20, 0x40, 0x40, 0x80, 0x02, 0x80, 0x02, 0x10, 0x01, 0x08, //0x10
+    0x01, 0x08, 0x01, 0x08, 0x01, 0x08, 0x01, 0x08, 0x02, 0x80, 0x01, 0x00, 0x10, 0x00, 0x00, 0x40, //0x20
+    0x00, 0x00, 0x20, 0x20, 0x04, 0x00, 0x80, 0x10, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, //0x30
+    0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x40, 0x00, 0x00, 0x02, 0x04, //0x40
+    0x00, 0x80, 0x00, 0x00, 0x80, 0x02, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x50
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x60
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x70
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x90
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xA0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xB0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xC0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xD0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0xE0
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, 0x10, 0x80
+  }
+}; //0xF0 
+
+
+struct {
+  union {
+    uint32_t kv;
+    struct {
+      uint8_t ke,   //Extratasten SHIFT, STRG, ALT...
+              kdummy,
+              k,    //Erste gedrückte Taste
+              k2;   //Zweite gedrückte Taste
+    };
+  };
+  uint32_t lastkv;
+  uint8_t shiftLock;
+} kbdData = {0, 0, 0};
+
+
+
+
+static void setKey(uint32_t k, bool pressed) {
+  if (pressed) {
+    kbdData.kv = (k << 16);
+    kbdData.ke = kbdData.k2;
+    kbdData.k2 = 0;
+  }
+  else
+  {
+    kbdData.kv = 0;       
+  }
+}
+
+static void pushStringToTextEntry(char * text) {
+    char c;
+    while ((c = *text++)) {
+        setKey(ascii2scan[c], true); 
+        sleep_ms(20);
+        setKey(ascii2scan[c], false); 
+        sleep_ms(20);
+    }
+}
+
+
+uint8_t cia1PORTA(void) {
+
+  uint8_t v;
+
+  v = ~cpu.cia1.R[0x02] | (cpu.cia1.R[0x00] & cpu.cia1.R[0x02]);
+  int keys = emu_GetPad();
+#ifndef PICOMPUTER
+  /*
+  if (oskbActive) keys = 0;
+  */
+#endif  
+  if (!cpu.swapJoysticks) {
+    if (keys & MASK_JOY2_BTN) v &= 0xEF;
+    if (keys & MASK_JOY2_UP) v &= 0xFE;
+    if (keys & MASK_JOY2_DOWN) v &= 0xFD;
+    if (keys & MASK_JOY2_RIGHT) v &= 0xFB;
+    if (keys & MASK_JOY2_LEFT) v &= 0xF7;
+  } else {
+    if (keys & MASK_JOY1_BTN) v &= 0xEF;
+    if (keys & MASK_JOY1_UP) v &= 0xFE;
+    if (keys & MASK_JOY1_DOWN) v &= 0xFD;
+    if (keys & MASK_JOY1_RIGHT) v &= 0xFB;
+    if (keys & MASK_JOY1_LEFT) v &= 0xF7;
+  }	
+
+
+  if (!kbdData.kv) return v; //Keine Taste gedrückt
+
+  uint8_t filter = ~cpu.cia1.R[0x01] & cpu.cia1.R[0x03];
+  
+  if (kbdData.k) {
+    if ( keymatrixmap[1][kbdData.k] & filter)  v &= ~keymatrixmap[0][kbdData.k];
+  }
+
+  if (kbdData.ke) {
+    if (kbdData.ke & 0x02) { //Shift-links
+      if ( keymatrixmap[1][0xff] & filter) v &= ~keymatrixmap[0][0xff];
+    }
+    if (kbdData.ke & 0x20) { //Shift-rechts
+      if ( keymatrixmap[1][0xfe] & filter) v &= ~keymatrixmap[0][0xfe];
+    }
+    if (kbdData.ke & 0x11) { //Control
+      if ( keymatrixmap[1][0xfd] & filter) v &= ~keymatrixmap[0][0xfd];
+    }
+    if (kbdData.ke & 0x88) { //Windows (=> Commodore)
+      if ( keymatrixmap[1][0xfc] & filter) v &= ~keymatrixmap[0][0xfc];
+    }
+  }
+ 
+  return v;
+}
+
+
+uint8_t cia1PORTB(void) {
+
+  uint8_t v;
+
+  v = ~cpu.cia1.R[0x03] | (cpu.cia1.R[0x00] & cpu.cia1.R[0x02]) ;
+  int keys = emu_GetPad();
+#ifndef PICOMPUTER
+  /*
+  if (oskbActive) keys = 0;
+  */
+#endif  
+  if (!cpu.swapJoysticks) {
+    if (keys & MASK_JOY1_BTN) v &= 0xEF;
+    if (keys & MASK_JOY1_UP) v &= 0xFE;
+    if (keys & MASK_JOY1_DOWN) v &= 0xFD;
+    if (keys & MASK_JOY1_RIGHT) v &= 0xFB;
+    if (keys & MASK_JOY1_LEFT) v &= 0xF7;
+  } else {
+    if (keys & MASK_JOY2_BTN) v &= 0xEF;
+    if (keys & MASK_JOY2_UP) v &= 0xFE;
+    if (keys & MASK_JOY2_DOWN) v &= 0xFD;
+    if (keys & MASK_JOY2_RIGHT) v &= 0xFB;
+    if (keys & MASK_JOY2_LEFT) v &= 0xF7;
+  }
+
+  if (!kbdData.kv) return v; //Keine Taste gedrückt
+
+  uint8_t filter = ~cpu.cia1.R[0x00] & cpu.cia1.R[0x02];
+
+  if (kbdData.k) {
+    if ( keymatrixmap[0][kbdData.k] & filter) v &= ~keymatrixmap[1][kbdData.k];
+  }
+
+  if (kbdData.ke) {
+    if (kbdData.ke & 0x02) { //Shift-links
+      if ( keymatrixmap[0][0xff] & filter) v &= ~keymatrixmap[1][0xff];
+    }
+    if (kbdData.ke & 0x20) { //Shift-rechts
+      if ( keymatrixmap[0][0xfe] & filter) v &= ~keymatrixmap[1][0xfe];
+    }
+    if (kbdData.ke & 0x11) { //Control
+      if ( keymatrixmap[0][0xfd] & filter) v &= ~keymatrixmap[1][0xfd];
+    }
+    if (kbdData.ke & 0x88) { //Windows (=> Commodore)
+      if ( keymatrixmap[0][0xfc] & filter) v &= ~keymatrixmap[1][0xfc];
+    }
+  }
+
+  return v;
+}
+
+
+void c64_Init(void)
+{
+  disableEventResponder();
+  resetPLA();
+  resetCia1();
+  resetCia2();
+  resetVic();
+  cpu_reset();
+#ifdef HAS_SND  
+  playSID.begin(SOUNDRATE,500);  
+  emu_sndInit();
+#endif  
+}
+
+
+void c64_Step(void)
+{
+	oneRasterLine();
+}
+
+void c64_Start(char * filename)
+{
+}
+
+
+static uint8_t nbkeys = 0;
+static uint8_t kcnt = 0;
+static bool toggle = true;
+
+static char * textseq;
+static char * textload = "LOAD\"\"\r\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tRUN\r";
+static char textkey[1];
+
+static bool res=false;
+static bool firsttime=true;
+static int  loadtimeout=100; //100*20ms;
+
+#ifndef PICOMPUTER
+/*
+#define OSKB_YPOS (240-16)
+
+static char * oskbtext1 = "FFFFFFFF  RD\"$ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+static char * oskbtext2 = "12345678  TL  ,.*     0123456789        ";
+static int oskbXPos = 10;
+static int oskbYPos = 0;
+
+#define OSKB_TEXT RGBVAL16(0, 0, 170)
+#define OSKB_BG   RGBVAL16(255, 255, 255)
+#define OSKB_HL   RGBVAL16(255, 255, 0)
+
+int emu_oskbActive(void) {
+  return (oskbActive?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    char sel[2]={0,0};
+    if (oskbActive) {
+      int fbwidth;
+      tft.get_frame_buffer_size(&fbwidth,NULL);       
+      tft.drawText((fbwidth-320)/2,OSKB_YPOS,oskbtext1,OSKB_TEXT,OSKB_BG,false);
+      tft.drawText((fbwidth-320)/2,OSKB_YPOS+8,oskbtext2,OSKB_TEXT,OSKB_BG,false);
+      sel[0]=(oskbYPos==0)?oskbtext1[oskbXPos]:oskbtext2[oskbXPos];
+      tft.drawText((fbwidth-320)/2+oskbXPos*8,OSKB_YPOS+8*oskbYPos,sel,OSKB_TEXT,OSKB_HL,false);
+    }
+    //skip += 1;
+    //skip &= VID_FRAME_SKIP;
+#ifdef USE_VGA
+    tft.waitSync(); 
+#endif    
+}
+*/
+#endif
+
+//#define DEBUG 1
+
+#ifdef DEBUG
+static const char * digits = "0123456789ABCDEF";
+static char buf[5] = {0,0,0,0,0};
+#endif
+
+static int iusbhk;// USB keyboard key
+
+void c64_Input(int bClick) {
+  if (nbkeys == 0) {
+    if (loadtimeout > 0) {
+      loadtimeout--; 
+    }
+    if ( (bClick & MASK_KEY_USER1) && !(emu_GetPad() & MASK_OSKB) ) {
+      if (loadtimeout == 0) {
+        if (firsttime) {
+          firsttime = false;
+          textseq = textload;
+          nbkeys = strlen(textseq);   
+          kcnt=0;
+        }
+        else {
+          cpu.swapJoysticks = !cpu.swapJoysticks;
+        }        
+      }
+    } 
+    else  
+    {
+      int hk = emu_ReadI2CKeyboard();
+      if (iusbhk) hk = iusbhk;
+      if ( (hk != 0) && (res == false) ) {
+#ifdef DEBUG        
+        buf[3] = 0;
+        buf[0] = digits[(hk>>8)&0xf];
+        buf[1] = digits[(hk>>4)&0xf];
+        buf[2] = digits[hk&0xf];        
+        tft.drawText(0,0,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+#endif
+        setKey(ascii2scan[hk],true);
+        res = true;
+      } 
+      else if (hk == 0){
+        setKey(ascii2scan[hk],false);
+        res = false;
+      }        
+    }
+  }
+  else {
+    char k = textseq[kcnt];
+    if (k != '\t') setKey(ascii2scan[k],toggle);
+    if (!toggle) {
+      kcnt++;
+      nbkeys--;
+      toggle = true;
+    }
+    else {
+      toggle = false; 
+    }
+  }
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if ( (key >= KBD_KEY_F1) && (key <= KBD_KEY_F8) ) iusbhk = (key - KBD_KEY_F1) + 0x85; // 133
+  // Specific keys
+  //153,151,150,152,0x7F 31 //U L R D DEL ESC
+  else if (key == KBD_KEY_UP) iusbhk = 0x99; // 153
+  else if (key == KBD_KEY_LEFT) iusbhk = 0x97; // 151
+  else if (key == KBD_KEY_DOWN) iusbhk = 0x98; // 152
+  else if (key == KBD_KEY_RIGHT) iusbhk = 0x96; // 150
+  else if (key == KBD_KEY_BS) iusbhk = 0x7F; // 127
+  else if (key == KBD_KEY_ESC) iusbhk = 0x1F; // 31
+  else
+    iusbhk = toupper(key);
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+#ifdef HAS_SND      
+void  SND_Process( void * stream, int len )
+{
+    playSID.update(SOUNDRATE, stream, len);
+}
+#endif  
diff --git a/MCUME_pico2/pico64/c64.h b/MCUME_pico2/pico64/c64.h
new file mode 100644
index 0000000..93525f4
--- /dev/null
+++ b/MCUME_pico2/pico64/c64.h
@@ -0,0 +1,5 @@
+extern void c64_Init(void);
+extern void c64_Step(void);
+extern void c64_Start(char * filename);
+extern void c64_Input(int key);
+
diff --git a/MCUME_pico2/pico64/cia1.cpp b/MCUME_pico2/pico64/cia1.cpp
new file mode 100755
index 0000000..9c4e749
--- /dev/null
+++ b/MCUME_pico2/pico64/cia1.cpp
@@ -0,0 +1,401 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#include "cpu.h"
+#include "cia1.h"
+#include <string.h>
+
+
+#define DEBUGCIA1 0
+#define RTCDEBUG 0
+
+#define decToBcd(x)	( ( (uint8_t) (x) / 10 * 16) | ((uint8_t) (x) % 10) )
+#define bcdToDec(x) ( ( (uint8_t) (x) / 16 * 10) | ((uint8_t) (x) % 16) )
+#define tod()		(cpu.cia1.TODfrozen?cpu.cia1.TODfrozenMillis:(int)((millis() - cpu.cia1.TOD) % 86400000l))
+
+void cia1_setAlarmTime() {
+	cpu.cia1.TODAlarm = (cpu.cia1.W[0x08] + cpu.cia1.W[0x09] * 10l + cpu.cia1.W[0x0A] * 600l + cpu.cia1.W[0x0B] * 36000l);
+}
+
+void cia1_write(uint32_t address, uint8_t value) {
+
+	address &= 0x0F;
+
+	switch (address) {
+		case 0x04 : {cpu.cia1.W[address] = value;} ;break; //Timer A LO
+		case 0x05 : {cpu.cia1.W[address] = value; if ((cpu.cia1.R[0x0E] & 0x01) == 0) cpu.cia1.R[address]=value; };break;//Timer A HI
+		case 0x06 : {cpu.cia1.W[address] = value;} ;break; //Timer B LO
+		case 0x07 : {cpu.cia1.W[address] = value; if ((cpu.cia1.R[0x0F] & 0x01) == 0) cpu.cia1.R[address]=value; };break; //Timer B HI
+
+		//RTC
+		case 0x08 : {
+					if ((cpu.cia1.R[0x0f] & 0x80)>0) {
+						value &= 0x0f;
+						cpu.cia1.W[address] = value;
+						cia1_setAlarmTime();
+
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set Alarm TENTH:");
+						Serial.println(value,HEX);
+						#endif
+
+					} else {
+						value &= 0x0f;
+						cpu.cia1.TODstopped=0;
+						//Translate set Time to TOD:
+						cpu.cia1.TOD = (int)(millis() % 86400000l) - (value * 100 + cpu.cia1.R[0x09] * 1000l + cpu.cia1.R[0x0A] * 60000l + cpu.cia1.R[0x0B] * 3600000l);
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set TENTH:");
+						Serial.println(value,HEX);
+						Serial.print("CIA 1 TOD (millis):");
+						Serial.println(cpu.cia1.TOD);
+						#endif
+					}
+					};
+					break; //TOD-Tenth
+		case 0x09 : {
+					if ((cpu.cia1.R[0x0f] & 0x80)>0) {
+						cpu.cia1.W[address] = bcdToDec(value);
+						cia1_setAlarmTime();
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set Alarm SEC:");
+						Serial.println(value,HEX);
+						#endif
+
+					} else {
+						cpu.cia1.R[address] = bcdToDec(value);
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set SEC:");
+						Serial.println(value,HEX);
+						#endif
+
+					}
+					};
+					break; //TOD-Secs
+		case 0x0A : {
+					if ((cpu.cia1.R[0x0f] & 0x80)>0) {
+						cpu.cia1.W[address] = bcdToDec(value);
+						cia1_setAlarmTime();
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set Alarm MIN:");
+						Serial.println(value,HEX);
+						#endif
+
+					} else {
+						cpu.cia1.R[address] = bcdToDec(value);
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set MIN:");
+						Serial.println(value,HEX);
+						#endif
+
+					}
+					};break; //TOD-Minutes
+		case 0x0B : {
+					if ((cpu.cia1.R[0x0f] & 0x80)>0) {
+						cpu.cia1.W[address] = bcdToDec(value & 0x1f) + (value & 0x80?12:0);
+						cia1_setAlarmTime();
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set Alarm HRS:");
+						Serial.println(value,HEX);
+						#endif
+
+					} else {
+						cpu.cia1.R[address] = bcdToDec(value & 0x1f) + (value & 0x80?12:0);
+						cpu.cia1.TODstopped=1;
+						#if RTCDEBUG
+						Serial.print("CIA 1 Set HRS:");
+						Serial.println(value,HEX);
+						#endif
+					}
+					};break; //TOD-Hours
+
+		case 0x0C : {
+					cpu.cia1.R[address] = value;
+					//Fake IRQ
+					cpu.cia1.R[0x0d] |= 8 | ((cpu.cia1.W[0x0d] & 0x08) << 4);
+					}
+					;break;
+		case 0x0D : {
+					if ((value & 0x80)>0) {
+						cpu.cia1.W[address] |= value & 0x1f;
+						//ggf IRQ triggern
+						if (cpu.cia1.R[address] & cpu.cia1.W[address] & 0x1f) {
+							cpu.cia1.R[address] |= 0x80;
+						};
+					} else {
+						cpu.cia1.W[address] &= ~value;
+					}
+
+					};
+					break;
+		case 0x0E : {cpu.cia1.R[address] = value & ~0x10;
+					 if ((value & 0x10)>0) { cpu.cia1.R16[0x04/2] = cpu.cia1.W16[0x04/2]; }
+					 };
+					 break;
+		case 0x0F : {cpu.cia1.R[address] = value & ~0x10; if ((value & 0x10)>0) { cpu.cia1.R16[0x06/2] = cpu.cia1.W16[0x06/2]; }};break;
+		default   : {cpu.cia1.R[address] = value;/*if (address ==0) {Serial.print(value);Serial.print(" ");}*/ } break;
+	}
+
+#if DEBUGCIA1
+	if (cpu.pc < 0xa000) Serial.printf("%x CIA1: W %x %x\n", cpu.pc, address, value);
+#endif
+}
+
+uint8_t cia1_read(uint32_t address) {
+uint8_t ret;
+
+	address &= 0x0F;
+
+	switch (address) {
+		case 0x00: {ret = cia1PORTA();};break;
+		case 0x01: {ret = cia1PORTB();};break;
+		//RTC
+		case 0x08: {
+					ret = tod() % 1000 / 10;
+					cpu.cia1.TODfrozen = 0;
+					};
+
+					#if RTCDEBUG
+					Serial.print("CIA 1 Read TENTH:");
+					Serial.println(ret,HEX);
+					#endif
+
+					break;	//Bit 0..3: Zehntelsekunden im BCD-Format ($0-$9) Bit 4..7: immer 0
+		case 0x09: {
+					ret = decToBcd(tod() / 1000 % 60);
+					};
+					//Serial.println( tod() / 100);
+					#if RTCDEBUG
+					Serial.print("CIA 1 Read SEC:");
+					Serial.println(ret,HEX);
+					#endif
+
+					break;				//Bit 0..3: Einersekunden im BCD-Format ($0-$9) Bit 4..6: Zehnersekunden im BCD-Format ($0-$5) Bit 7: immer 0
+		case 0x0A: {
+					ret = decToBcd(tod() / (1000 * 60) % 60);
+					};
+					#if RTCDEBUG
+					Serial.print("CIA 1 Read MIN:");
+					Serial.println(ret,HEX);
+					#endif
+
+					break;		//Bit 0..3: Einerminuten im BCD-Format( $0-$9) Bit 4..6: Zehnerminuten im BCD-Format ($0-$5) Bit 7: immer 0
+		case 0x0B: {
+					//Bit 0..3: Einerstunden im BCD-Format ($0-$9) Bit 4: Zehnerstunden im BCD-Format ($0-$1) // Bit 7: Unterscheidung AM/PM, 0=AM, 1=PM
+					//Lesen aus diesem Register friert alle TOD-Register ein (TOD läuft aber weiter), bis Register 8 (TOD 10THS) gelesen wird.
+					cpu.cia1.TODfrozen = 0;
+					cpu.cia1.TODfrozenMillis = tod();
+					cpu.cia1.TODfrozen = 1;
+				   	#if RTCDEBUG
+					Serial.print("CIA 1 FrozenMillis:");
+					Serial.println(cpu.cia1.TODfrozenMillis);
+					#endif
+					ret = cpu.cia1.TODfrozenMillis / (1000 * 3600) % 24;
+					if (ret>=12)
+						ret = 128 | decToBcd(ret - 12);
+					else
+						ret = decToBcd(ret);
+				    };
+				   	#if RTCDEBUG
+					Serial.print("CIA 1 Read HRS:");
+					Serial.println(ret,HEX);
+					#endif
+
+				   break;
+
+		case 0x0D: {ret = cpu.cia1.R[address] & 0x9f;
+					cpu.cia1.R[address]=0;
+					};
+					break;
+
+		default: ret = cpu.cia1.R[address];break;
+	}
+
+#if DEBUGCIA1
+	if (cpu.pc < 0xa000) Serial.printf("%x CIA1: R %x %x\n", cpu.pc, address, ret);
+#endif
+return ret;
+}
+
+#if 0
+void cia1_clock(int clk) {
+
+	uint32_t cnta, cntb, cra, crb;
+
+	//Timer A
+	cra = cpu.cia1.R[0x0e];
+	crb = cpu.cia1.R[0x0f];
+
+	if (( cra & 0x21) == 0x01) {
+		cnta = cpu.cia1.R[0x04] | cpu.cia1.R[0x05] << 8;
+		cnta -= clk;
+		if (cnta > 0xffff) { //Underflow
+			cnta = cpu.cia1.W[0x04] | cpu.cia1.W[0x05] << 8; // Reload Timer
+			if (cra & 0x08) { // One Shot
+				cpu.cia1.R[0x0e] &= 0xfe; //Stop timer
+			}
+
+			//Interrupt:
+			cpu.cia1.R[0x0d] |= 1 /*| (cpu.cia1.W[0x1a] & 0x01) */| ((cpu.cia1.W[0x0d] & 0x01) << 7);
+
+			if ((crb & 0x61)== 0x41) { //Timer B counts underflows of Timer A
+				cntb = cpu.cia1.R[0x06] | cpu.cia1.R[0x07] << 8;
+				cntb--;
+				if (cntb > 0xffff) { //underflow
+					cpu.cia1.R[0x04] = cnta;
+					cpu.cia1.R[0x05] = cnta >> 8;
+					goto underflow_b;
+				}
+			}
+		}
+
+		cpu.cia1.R[0x04] = cnta;
+		cpu.cia1.R[0x05] = cnta >> 8;
+
+	}
+
+	//Timer B
+	if (( crb & 0x61) == 0x01) {
+		cntb = cpu.cia1.R[0x06] | cpu.cia1.R[0x07] << 8;
+		cntb -= clk;
+		if (cntb > 0xffff) { //underflow
+underflow_b:
+			cntb = cpu.cia1.W[0x06] | cpu.cia1.W[0x07] << 8; // Reload Timer
+			if (crb & 0x08) { // One Shot
+				cpu.cia1.R[0x0f] &= 0xfe; //Stop timer
+			}
+
+			//Interrupt:
+			cpu.cia1.R[0x0d] |= 2 /*|  (cpu.cia1.W[0x1a] & 0x02) */ | ((cpu.cia1.W[0x0d] & 0x02) << 6);
+
+		}
+
+		cpu.cia1.R[0x06] = cntb;
+		cpu.cia1.R[0x07] = cntb >> 8;
+
+	}
+}
+#else
+
+void cia1_clock(int clk) {
+
+	int32_t t;
+	uint32_t regFEDC = cpu.cia1.R32[0x0C/4];
+
+	// TIMER A
+	//if (((cpu.cia1.R[0x0E] & 0x01)>0) && ((cpu.cia1.R[0x0E] & 0x20)==0)) {
+
+	//if ((regFEDC & 0x210000)==0x10000) {
+	if (((regFEDC>>16) & 0x21)==0x1) {
+		t = cpu.cia1.R16[0x04/2];
+
+		if (clk > t) { //underflow ?
+			t = cpu.cia1.W16[0x04/2] - (clk - t);
+			regFEDC |= 0x00000100;
+			if ((regFEDC & 0x00080000)) regFEDC &= 0xfffeffff; //One-Shot
+		}
+		else {
+			t-=clk;
+		}
+
+		cpu.cia1.R16[0x04/2] = t;
+	}
+
+
+	// TIMER B
+	//TODO : Prüfen ob das funktioniert
+	if ( regFEDC & 0x01000000 ) {
+		//uint16_t quelle = (cpu.cia1.R[0x0F]>>5) & 0x03;
+		if ((regFEDC & 0x60000000) == 0x40000000) {
+
+			if (regFEDC & 0x00000100) //unterlauf TimerA?
+				clk = 1;
+			else
+				goto tend;
+		}
+
+		t = cpu.cia1.R16[0x06/2];
+
+		if (clk > t) { //underflow ?
+			t = cpu.cia1.W16[0x06/2] - (clk - t);
+			regFEDC |= 0x00000200;
+			if ((regFEDC & 0x08000000)) regFEDC &= 0xfeffffff;
+		} else {
+			t -= clk;
+		}
+		cpu.cia1.R16[0x06/2] = t; //One-Shot
+
+	}
+
+tend:
+
+
+	// INTERRUPT ?
+	if ( regFEDC & cpu.cia1.W32[0x0C/4] & 0x0f00 ) {
+		regFEDC |= 0x8000;
+		cpu.cia1.R32[0x0C/4]=regFEDC;
+	}
+	else cpu.cia1.R32[0x0C/4]=regFEDC;
+}
+
+#endif
+
+void cia1_checkRTCAlarm() { // call @ 1/10 sec interval minimum
+
+	if ((int)(millis() - cpu.cia1.TOD) % 86400000l/100 == cpu.cia1.TODAlarm) {
+		//Serial.print("CIA1 RTC interrupt");
+		cpu.cia1.R[13] |= 0x4 | ((cpu.cia1.W[13] & 4) << 5);
+	}
+}
+
+void cia1FLAG(void) {
+	//Serial.println("CIA1 FLAG interrupt");
+	cpu.cia1.R[13] |= 0x10 | ((cpu.cia1.W[13] & 0x10) << 3);
+}
+
+void resetCia1(void) {
+	memset((uint8_t*)&cpu.cia1.R, 0, sizeof(cpu.cia1.R));
+	cpu.cia1.W[0x04] = cpu.cia1.R[0x04] = 0xff;
+	cpu.cia1.W[0x05] = cpu.cia1.R[0x05] = 0xff;
+	cpu.cia1.W[0x06] = cpu.cia1.R[0x06] = 0xff;
+	cpu.cia1.W[0x07] = cpu.cia1.R[0x07] = 0xff;
+
+	//FLAG pin CIA1 - Serial SRQ (input only)
+    //pinMode(PIN_SERIAL_SRQ, OUTPUT_OPENDRAIN);
+	//digitalWriteFast(PIN_SERIAL_SRQ, 1);
+	//attachInterrupt(digitalPinToInterrupt(PIN_SERIAL_SRQ), cia1FLAG, FALLING);
+}
+
+
diff --git a/MCUME_pico2/pico64/cia1.h b/MCUME_pico2/pico64/cia1.h
new file mode 100755
index 0000000..ec69047
--- /dev/null
+++ b/MCUME_pico2/pico64/cia1.h
@@ -0,0 +1,33 @@
+#ifndef Teensy64_cia1_h_
+#define Teensy64_cia1_h_
+
+struct tcia {
+	union {
+		uint8_t R[0x10];
+		uint16_t R16[0x10/2];
+		uint32_t R32[0x10/4];
+	};
+	union {
+		uint8_t W[0x10];
+		uint16_t W16[0x10/2];
+		uint32_t W32[0x10/4];
+	};
+	int32_t TOD;
+	int32_t TODfrozenMillis;
+	int32_t TODAlarm;
+	uint8_t TODstopped;
+	uint8_t TODfrozen;
+};
+
+
+void cia1_clock(int clk) __attribute__ ((hot));
+void cia1_checkRTCAlarm() __attribute__ ((hot));
+void cia1_write(uint32_t address, uint8_t value) __attribute__ ((hot));
+uint8_t cia1_read(uint32_t address) __attribute__ ((hot));
+
+void resetCia1(void);
+
+
+
+
+#endif
diff --git a/MCUME_pico2/pico64/cia2.cpp b/MCUME_pico2/pico64/cia2.cpp
new file mode 100755
index 0000000..db71d7d
--- /dev/null
+++ b/MCUME_pico2/pico64/cia2.cpp
@@ -0,0 +1,452 @@
+/*
+  Copyright Frank Bösing, 2017
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#include "cpu.h"
+#include "cia2.h"
+#include <string.h>
+
+#define DEBUGCIA2 0
+#define RTCDEBUG 0
+
+#define decToBcd(x)	( ( (uint8_t) (x) / 10 * 16) | ((uint8_t) (x) % 10) )
+#define bcdToDec(x) ( ( (uint8_t) (x) / 16 * 10) | ((uint8_t) (x) % 16) )
+#define tod()		(cpu.cia2.TODfrozen?cpu.cia2.TODfrozenMillis:(int)((millis() - cpu.cia2.TOD) % 86400000l))
+
+void cia2_setAlarmTime() {
+  cpu.cia2.TODAlarm = (cpu.cia2.W[0x08] + cpu.cia2.W[0x09] * 10l + cpu.cia2.W[0x0A] * 600l + cpu.cia2.W[0x0B] * 36000l);
+}
+
+void cia2_write(uint32_t address, uint8_t value) {
+
+  address &= 0x0F;
+
+  switch (address) {
+
+    case 0x00 : {
+      if ((~value & 0x38)) {
+        cpu_setExactTiming();
+      }
+
+	  WRITE_ATN_CLK_DATA(value);
+
+
+      cpu.vic.bank = ((~value) & 0x03) * 16384;
+      vic_adrchange();
+      cpu.cia2.R[address] = value;
+	  }
+      break;
+
+    case 0x01 :
+	   break;//Data PORTB
+
+    case 0x04 : {
+        cpu.cia2.W[address] = value;
+      }
+	  break; //Timer A LO
+    case 0x05 : {
+        cpu.cia2.W[address] = value;
+        if ((cpu.cia2.R[0x0E] & 0x01) == 0) cpu.cia2.R[address] = value;
+      }
+	  break; //Timer A HI
+    case 0x06 : {
+        cpu.cia2.W[address] = value;
+      }
+	  break; //Timer B LO
+    case 0x07 : {
+        cpu.cia2.W[address] = value;
+        if ((cpu.cia2.R[0x0F] & 0x01) == 0) cpu.cia2.R[address] = value;
+      }
+      break; //Timer B HI
+
+    //RTC
+    case 0x08 : {
+        if ((cpu.cia2.R[0x0f] & 0x80) > 0) {
+          value &= 0x0f;
+          cpu.cia2.W[address] = value;
+          cia2_setAlarmTime();
+
+#if RTCDEBUG
+          Serial.print("CIA 2 Set Alarm TENTH:");
+          Serial.println(value, HEX);
+#endif
+
+        } else {
+          value &= 0x0f;
+          cpu.cia2.TODstopped = 0;
+          //Translate set Time to TOD:
+          cpu.cia2.TOD = (int)(millis() % 86400000l) -
+						(value * 100 + cpu.cia2.R[0x09] * 1000l + cpu.cia2.R[0x0A] * 60000l + cpu.cia2.R[0x0B] * 3600000l);
+#if RTCDEBUG
+          Serial.print("CIA 2 Set TENTH:");
+          Serial.println(value, HEX);
+          Serial.print("CIA 2 TOD (millis):");
+          Serial.println(cpu.cia2.TOD);
+#endif
+        }
+      }
+      break; //TOD-Tenth
+    case 0x09 : {
+        if ((cpu.cia2.R[0x0f] & 0x80) > 0) {
+          cpu.cia2.W[address] = bcdToDec(value);
+          cia2_setAlarmTime();
+#if RTCDEBUG
+          Serial.print("CIA 2 Set Alarm SEC:");
+          Serial.println(value, HEX);
+#endif
+
+        } else {
+          cpu.cia2.R[address] = bcdToDec(value);
+#if RTCDEBUG
+          Serial.print("CIA 2 Set SEC:");
+          Serial.println(value, HEX);
+#endif
+
+        }
+      }
+      break; //TOD-Secs
+    case 0x0A : {
+        if ((cpu.cia2.R[0x0f] & 0x80) > 0) {
+          cpu.cia2.W[address] = bcdToDec(value);
+          cia2_setAlarmTime();
+#if RTCDEBUG
+          Serial.print("CIA 2 Set Alarm MIN:");
+          Serial.println(value, HEX);
+#endif
+
+        } else {
+          cpu.cia2.R[address] = bcdToDec(value);
+#if RTCDEBUG
+          Serial.print("CIA 2 Set MIN:");
+          Serial.println(value, HEX);
+#endif
+
+        }
+      }
+	  break; //TOD-Minutes
+    case 0x0B : {
+        if ((cpu.cia2.R[0x0f] & 0x80) > 0) {
+          cpu.cia2.W[address] = bcdToDec(value & 0x1f) + (value & 0x80 ? 12 : 0);
+          cia2_setAlarmTime();
+#if RTCDEBUG
+          Serial.print("CIA 2 Set Alarm HRS:");
+          Serial.println(value, HEX);
+#endif
+
+        } else {
+          cpu.cia2.R[address] = bcdToDec(value & 0x1f) + (value & 0x80 ? 12 : 0);
+          cpu.cia2.TODstopped = 1;
+#if RTCDEBUG
+          Serial.print("CIA 2 Set HRS:");
+          Serial.println(value, HEX);
+#endif
+        }
+      }
+	  break; //TOD-Hours
+    case 0x0C : {
+        cpu.cia2.R[address] = value;
+        //Fake IRQ
+        cpu.cia2.R[0x0d] |= 8 | ((cpu.cia2.W[0x0d] & 0x08) << 4);
+        cpu_nmi();
+      }
+      break;
+    case 0x0D : {
+        if ((value & 0x80) > 0) {
+          cpu.cia2.W[address] |= value & 0x1f;
+          //ggf NMItriggern
+          if (cpu.cia2.R[address] & cpu.cia2.W[address] & 0x1f) {
+            cpu.cia2.R[address] |= 0x80;
+            cpu_nmi();
+          };
+        } else {
+          cpu.cia2.W[address] &= ~value;
+        }
+      }
+      break;
+
+    case 0x0E : {
+        cpu.cia2.R[address] = value & ~0x10;
+        if ((value & 0x10) > 0) {
+          cpu.cia2.R16[0x04 / 2] = cpu.cia2.W16[0x04 / 2];
+        }
+      }
+      break;
+    case 0x0F : {
+        cpu.cia2.R[address] = value & ~0x10;
+        if ((value & 0x10) > 0) {
+          cpu.cia2.R16[0x06 / 2] = cpu.cia2.W16[0x06 / 2];
+        }
+      }
+	  break;
+    default : {
+        cpu.cia2.R[address] = value;/*if (address ==0) {Serial.print(value);Serial.print(" ");}*/
+      }
+	  break;
+  }
+
+#if DEBUGCIA2
+  Serial.printf("%x CIA2: W %x %x\n", cpu.pc, address, value);
+#endif
+}
+
+uint8_t cia2_read(uint32_t address) {
+  uint8_t ret;
+
+  address &= 0x0F;
+
+  switch (address) {
+
+    case 0x00 : {
+        ret = (cpu.cia2.R[address] & 0x3f) | READ_CLK_DATA();
+        if ((~ret & 0x3f)) {
+          cpu_setExactTiming();
+        }
+		
+        break;
+      }
+
+    //RTC
+    case 0x08: {
+        ret = tod() % 1000 / 10;
+        cpu.cia2.TODfrozen = 0;
+      };
+
+#if RTCDEBUG
+      Serial.print("CIA 2 Read TENTH:");
+      Serial.println(ret, HEX);
+#endif
+
+      break;  //Bit 0..3: Zehntelsekunden im BCD-Format ($0-$9) Bit 4..7: immer 0
+    case 0x09: {
+        ret = decToBcd(tod() / 1000 % 60);
+      };
+      //Serial.println( tod() / 100);
+#if RTCDEBUG
+      Serial.print("CIA 2 Read SEC:");
+      Serial.println(ret, HEX);
+#endif
+
+      break;        //Bit 0..3: Einersekunden im BCD-Format ($0-$9) Bit 4..6: Zehnersekunden im BCD-Format ($0-$5) Bit 7: immer 0
+    case 0x0A: {
+        ret = decToBcd(tod() / (1000 * 60) % 60);
+      };
+#if RTCDEBUG
+      Serial.print("CIA 2 Read MIN:");
+      Serial.println(ret, HEX);
+#endif
+
+      break;    //Bit 0..3: Einerminuten im BCD-Format( $0-$9) Bit 4..6: Zehnerminuten im BCD-Format ($0-$5) Bit 7: immer 0
+    case 0x0B: {
+        //Bit 0..3: Einerstunden im BCD-Format ($0-$9) Bit 4: Zehnerstunden im BCD-Format ($0-$1) // Bit 7: Unterscheidung AM/PM, 0=AM, 1=PM
+        //Lesen aus diesem Register friert alle TOD-Register ein (TOD läuft aber weiter), bis Register 8 (TOD 10THS) gelesen wird.
+        cpu.cia2.TODfrozen = 0;
+        cpu.cia2.TODfrozenMillis = tod();
+        cpu.cia2.TODfrozen = 1;
+#if RTCDEBUG
+        Serial.print("CIA 2 FrozenMillis:");
+        Serial.println(cpu.cia2.TODfrozenMillis);
+#endif
+        ret = cpu.cia2.TODfrozenMillis / (1000 * 3600) % 24;
+        if (ret >= 12)
+          ret = 128 | decToBcd(ret - 12);
+        else
+          ret = decToBcd(ret);
+      };
+#if RTCDEBUG
+      Serial.print("CIA 2 Read HRS:");
+      Serial.println(ret, HEX);
+#endif
+
+      break;
+
+    case 0x0D: {
+        ret = cpu.cia2.R[address] & 0x9f;
+        cpu.cia2.R[address] = 0;
+        cpu_clearNmi();
+      }; break;
+    default: ret = cpu.cia2.R[address]; break;
+  }
+
+#if DEBUGCIA2
+  Serial.printf("%x CIA2: R %x %x\n", cpu.pc, address, ret);
+#endif
+  return ret;
+}
+
+#if 0
+void cia2_clock(int clk) {
+
+  uint32_t cnta, cntb, cra, crb;
+
+  //Timer A
+  cra = cpu.cia2.R[0x0e];
+  crb = cpu.cia2.R[0x0f];
+
+  if (( cra & 0x21) == 0x01) {
+    cnta = cpu.cia2.R[0x04] | cpu.cia2.R[0x05] << 8;
+    cnta -= clk;
+    if (cnta > 0xffff) { //Underflow
+      cnta = cpu.cia2.W[0x04] | cpu.cia2.W[0x05] << 8; // Reload Timer
+      if (cra & 0x08) { // One Shot
+        cpu.cia2.R[0x0e] &= 0xfe; //Stop timer
+      }
+
+      //Interrupt:
+      cpu.cia2.R[0x0d] |= 1 | /* (cpu.cia2.W[0x0d] & 0x01) |*/ ((cpu.cia2.W[0x0d] & 0x01) << 7);
+
+      if ((crb & 0x61) == 0x41) { //Timer B counts underflows of Timer A
+        cntb = cpu.cia2.R[0x06] | cpu.cia2.R[0x07] << 8;
+        cntb--;
+        if (cntb > 0xffff) { //underflow
+          cpu.cia2.R[0x04] = cnta & 0x0f;
+          cpu.cia2.R[0x05] = cnta >> 8;
+          goto underflow_b;
+        }
+      }
+    }
+
+    cpu.cia2.R[0x04] = cnta & 0x0f;
+    cpu.cia2.R[0x05] = cnta >> 8;
+
+  }
+
+  //Timer B
+  if (( crb & 0x61) == 0x01) {
+    cntb = cpu.cia2.R[0x06] | cpu.cia2.R[0x07] << 8;
+    cntb -= clk;
+    if (cntb > 0xffff) { //underflow
+underflow_b:
+      cntb = cpu.cia2.W[0x06] | cpu.cia2.W[0x07] << 8; // Reload Timer
+      if (crb & 0x08) { // One Shot
+        cpu.cia2.R[0x0f] &= 0xfe; //Stop timer
+      }
+
+      //Interrupt:
+      cpu.cia2.R[0x0d] |= 2 | /*(cpu.cia2.W[0x0d] & 0x02) | */ ((cpu.cia2.W[0x0d] & 0x02) << 6);
+    }
+
+    cpu.cia2.R[0x06] = cntb & 0x0f;
+    cpu.cia2.R[0x07] = cntb >> 8;
+
+  }
+  if (cpu.cia2.R[0x0d] & 0x80) cpu_nmi();
+}
+
+#else
+
+void cia2_clock(int clk) {
+
+  int32_t t;
+  uint32_t regFEDC = cpu.cia2.R32[0x0C / 4];
+
+  // TIMER A
+  //if (((cpu.cia2.R[0x0E] & 0x01)>0) && ((cpu.cia2.R[0x0E] & 0x20)==0)) {
+  //if ((regFEDC & 0x210000)==0x10000) {
+  if (((regFEDC >> 16) & 0x21) == 0x1) {
+
+    t = cpu.cia2.R16[0x04 / 2];
+
+    if (clk > t) { //underflow
+      t = cpu.cia2.W16[0x04 / 2] - (clk - t); //neu
+      regFEDC |= 0x00000100;
+      if ((regFEDC & 0x00080000)) regFEDC &= 0xfffeffff;
+    }
+    else {
+      t -= clk;
+    }
+
+    cpu.cia2.R16[0x04 / 2] = t;
+  }
+
+
+  // TIMER B
+  //TODO : Prüfen ob das funktioniert
+  if ( regFEDC & 0x01000000 ) {
+    //uint16_t quelle = (cpu.cia2.R[0x0F]>>5) & 0x03;
+    if ((regFEDC & 0x60000000) == 0x40000000) {
+
+      if (regFEDC & 0x00000100) //unterlauf TimerA?
+        clk = 1;
+      else
+        goto tend;
+    }
+
+    t = cpu.cia2.R16[0x06 / 2];
+
+    if (clk > t) { //underflow
+      t = cpu.cia2.W16[0x06 / 2] - (clk - t); //Neu
+      regFEDC |= 0x00000200;
+      if ((regFEDC & 0x08000000)) regFEDC &= 0xfeffffff;
+    } else {
+      t -= clk;
+    }
+    cpu.cia2.R16[0x06 / 2] = t;
+
+  }
+
+tend:
+
+
+  // INTERRUPT ?
+  if ( regFEDC & cpu.cia2.W32[0x0C / 4] & 0x0f00 ) {
+    regFEDC |= 0x8000;
+    cpu.cia2.R32[0x0C / 4] = regFEDC;
+  }
+  cpu.cia2.R32[0x0C / 4] = regFEDC;
+}
+#endif
+
+void cia2_checkRTCAlarm() { // call every 1/10 sec minimum
+  if ((int)(millis() - cpu.cia2.TOD) % 86400000l / 100 == cpu.cia2.TODAlarm) {
+    // Serial.print("CIA2 RTC interrupt");
+    // Interrupt
+    cpu.cia2.R[0x0d] |= 0x4 | (cpu.cia2.W[0x0d] & 4) << 5;
+  }
+}
+
+void resetCia2(void) {
+  memset((uint8_t*)&cpu.cia2.R, 0, sizeof(cpu.cia2.R));
+  cpu.cia2.R[0x04] = 0xff;
+  cpu.cia2.R[0x05] = 0xff;
+  cpu.cia2.R[0x06] = 0xff;
+  cpu.cia2.R[0x07] = 0xff;
+
+  //pinMode(PIN_SERIAL_ATN, OUTPUT_OPENDRAIN);  //ATN OUT (CIA2 PA3 OUT)
+  //pinMode(PIN_SERIAL_CLK, OUTPUT_OPENDRAIN);  //CLK   (CIA2 PA6:IN PA4: OUT)
+  //pinMode(PIN_SERIAL_DATA, OUTPUT_OPENDRAIN); //DATA  (CIA2 PA7:IN PA5: OUT)
+  //digitalWriteFast(PIN_SERIAL_ATN, 1);
+  //digitalWriteFast(PIN_SERIAL_CLK, 1);
+  //digitalWriteFast(PIN_SERIAL_DATA, 1);
+
+}
diff --git a/MCUME_pico2/pico64/cia2.h b/MCUME_pico2/pico64/cia2.h
new file mode 100755
index 0000000..1c21cb5
--- /dev/null
+++ b/MCUME_pico2/pico64/cia2.h
@@ -0,0 +1,47 @@
+/*
+	Copyright Frank Bösing, 2017	
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+		
+*/
+
+#ifndef Teensy64_cia2_h_
+#define Teensy64_cia2_h_
+
+
+void cia2_clock(int clk) __attribute__ ((hot));
+void cia2_checkRTCAlarm() __attribute__ ((hot));
+void cia2_write(uint32_t address, uint8_t value) __attribute__ ((hot));
+uint8_t cia2_read(uint32_t address) __attribute__ ((hot));
+
+void resetCia2(void);
+
+#endif
diff --git a/MCUME_pico2/pico64/cpu.cpp b/MCUME_pico2/pico64/cpu.cpp
new file mode 100755
index 0000000..a12270f
--- /dev/null
+++ b/MCUME_pico2/pico64/cpu.cpp
@@ -0,0 +1,2717 @@
+/*
+    Copyright Mike Chambers, Frank Bösing, 2017
+    Parts of this file are based on "Fake6502 CPU emulator core v1.1" by Mike Chambers
+
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+/* Fake6502 CPU emulator core v1.1 *******************
+ * (c)2011 Mike Chambers (miker00lz@gmail.com)       *
+ *****************************************************
+ * LICENSE: This source code is released into the    *
+ * public domain, but if you use it please do give   *
+ * credit. I put a lot of effort into writing this!  *
+ *                                                   *
+ *****************************************************
+*/
+
+#include "cpu.h"
+
+#define FLAG_CARRY     0x01
+#define FLAG_ZERO      0x02
+#define FLAG_INTERRUPT 0x04
+#define FLAG_DECIMAL   0x08
+#define FLAG_BREAK     0x10
+#define FLAG_CONSTANT  0x20
+#define FLAG_OVERFLOW  0x40
+#define FLAG_SIGN      0x80
+
+//flag modifier macros
+#define setcarry() cpu.cpustatus |= FLAG_CARRY
+#define clearcarry() cpu.cpustatus &= (~FLAG_CARRY)
+#define setzero() cpu.cpustatus |= FLAG_ZERO
+#define clearzero() cpu.cpustatus &= (~FLAG_ZERO)
+#define setinterrupt() cpu.cpustatus |= FLAG_INTERRUPT
+#define clearinterrupt() cpu.cpustatus &= (~FLAG_INTERRUPT)
+#define setdecimal() cpu.cpustatus |= FLAG_DECIMAL
+#define cleardecimal() cpu.cpustatus &= (~FLAG_DECIMAL)
+#define setoverflow() cpu.cpustatus |= FLAG_OVERFLOW
+#define clearoverflow() cpu.cpustatus &= (~FLAG_OVERFLOW)
+#define setsign() cpu.cpustatus |= FLAG_SIGN
+#define clearsign() cpu.cpustatus &= (~FLAG_SIGN)
+
+
+//flag calculation macros
+#define zerocalc(n) { if ((n) & 0x00FF) clearzero(); else setzero(); }
+//#define signcalc(n) { if ((n) & 0x0080) setsign(); else clearsign(); }
+#define signcalc(n) { cpu.cpustatus =( cpu.cpustatus & 0x7f) | (n & 0x80); }
+#define carrycalc(n) { if ((n) & 0xFF00) setcarry(); else clearcarry(); }
+//#define carrycalc(n) {cpu.cpustatus =( cpu.cpustatus & 0xfe) | (n >> 8); }
+#define overflowcalc(n, m, o) { if (((n) ^ (uint16_t)(m)) & ((n) ^ (o)) & 0x0080) setoverflow(); else clearoverflow(); }
+
+#define saveaccum(n) cpu.a = (uint8_t)((n) & 0x00FF)
+
+#define UNSUPPORTED { printf("Unsupported Opcode\n"); while(1){;} }
+
+void logAddr(const uint32_t address, const uint8_t value, const uint8_t rw) {
+	if (rw) printf("Write "); else printf("Read ");
+	printf("0x%d=0x%d\n",address,value);
+
+}
+struct tcpu cpu;
+struct tio io;
+
+void reset6502();
+void cpu_nmi();
+static inline void cpu_irq();
+
+INLINEOP uint8_t read6502(const uint32_t address) __attribute__ ((hot));
+INLINEOP uint8_t read6502(const uint32_t address) {
+	return (*cpu.plamap_r)[address >> 8](address);
+}
+
+INLINEOP uint8_t read6502ZP(const uint32_t address) __attribute__ ((hot)); //Zeropage
+INLINEOP uint8_t read6502ZP(const uint32_t address) {
+	return cpu.RAM[address & 0xff];
+}
+
+/* Ein Schreibzugriff auf einen ROM-Bereich speichert das Byte im „darunterliegenden� RAM. */
+INLINEOP void write6502(const uint32_t address, const uint8_t value) __attribute__ ((hot));
+INLINEOP void write6502(const uint32_t address, const uint8_t value) {
+ (*cpu.plamap_w)[address>>8](address, value);
+}
+
+//a few general functions used by various other functions
+INLINEOP void push16(const uint16_t pushval) {
+    cpu.RAM[BASE_STACK + cpu.sp] = (pushval >> 8) & 0xFF;
+    cpu.RAM[BASE_STACK + ((cpu.sp - 1) & 0xFF)] = pushval & 0xFF;
+    cpu.sp -= 2;
+}
+
+INLINEOP uint16_t pull16() {
+    uint16_t temp16;
+    temp16 = cpu.RAM[BASE_STACK + ((cpu.sp + 1) & 0xFF)] | ((uint16_t)cpu.RAM[BASE_STACK + ((cpu.sp + 2) & 0xFF)] << 8);
+    cpu.sp += 2;
+    return(temp16);
+}
+
+INLINEOP void push8(uint8_t pushval) {
+  cpu.RAM[BASE_STACK + (cpu.sp--)] = pushval;
+
+}
+
+INLINEOP uint8_t pull8() {
+  return cpu.RAM[BASE_STACK + (++cpu.sp)];
+}
+
+/********************************************************************************************************************/
+/*addressing mode functions, calculates effective addresses                                                         */
+/********************************************************************************************************************/
+
+INLINEOP void imp() { //implied
+}
+
+INLINEOP void acc() { //accumulator
+}
+
+INLINEOP void imm() { //immediate
+  cpu.ea = cpu.pc++;
+}
+
+INLINEOP void zp() { //zero-page
+  cpu.ea = read6502(cpu.pc++) & 0xFF;
+}
+
+INLINEOP void zpx() { //zero-page,X
+	cpu.ea = (read6502(cpu.pc++) + cpu.x)  & 0xFF; //zero-page wraparound
+}
+
+INLINEOP void zpy() { //zero-page,Y
+	cpu.ea = (read6502(cpu.pc++) + cpu.y) & 0xFF; //zero-page wraparound
+}
+
+INLINEOP void rel() { //relative for branch ops (8-bit immediate value, sign-extended)
+	cpu.reladdr = read6502(cpu.pc++);
+	if (cpu.reladdr & 0x80) cpu.reladdr |= 0xFF00;
+}
+
+INLINEOP void abso() { //absolute
+	cpu.ea = read6502(cpu.pc) | (read6502(cpu.pc + 1) << 8);
+	cpu.pc += 2;
+}
+
+INLINEOP void absx() { //absolute,X
+	cpu.ea = (read6502(cpu.pc) | (read6502(cpu.pc + 1) << 8)) + cpu.x;
+	cpu.pc += 2;
+}
+
+INLINEOP void absx_t() { //absolute,X with extra cycle
+	uint16_t h = read6502(cpu.pc) + cpu.x;
+	if (h & 0x100) cpu.ticks += 1;
+	cpu.ea = h + (read6502(cpu.pc + 1) << 8);
+	cpu.pc += 2;
+}
+
+INLINEOP void absy() { //absolute,Y
+	cpu.ea = (read6502(cpu.pc) + (read6502(cpu.pc + 1) << 8)) + cpu.y;
+	cpu.pc += 2;
+}
+
+INLINEOP void absy_t() { //absolute,Y with extra cycle
+	uint16_t h = read6502(cpu.pc) + cpu.y;
+	if (h & 0x100) cpu.ticks += 1;
+	cpu.ea = h + (read6502(cpu.pc + 1) << 8);
+	cpu.pc += 2;
+}
+
+INLINEOP void ind() { //indirect
+	uint16_t eahelp, eahelp2;
+	eahelp = read6502(cpu.pc) | (read6502(cpu.pc + 1) << 8);
+	eahelp2 = (eahelp & 0xFF00) | ((eahelp + 1) & 0x00FF); //replicate 6502 page-boundary wraparound bug
+	cpu.ea = read6502(eahelp) | (read6502(eahelp2) << 8);
+	cpu.pc += 2;
+}
+
+INLINEOP void indx() { // (indirect,X)
+	uint32_t eahelp;
+	eahelp = (read6502(cpu.pc++) + cpu.x) & 0xFF; //zero-page wraparound for table pointer
+	cpu.ea = read6502ZP((uint8_t)eahelp) | (read6502ZP((uint8_t)(eahelp + 1)) << 8);
+}
+
+INLINEOP void indy() { // (zeropage indirect),Y
+	uint8_t zp = read6502(cpu.pc++);
+	cpu.ea = read6502ZP((uint16_t) zp++);
+	cpu.ea += (uint16_t) read6502ZP((uint16_t) zp) << 8;
+	cpu.ea += cpu.y;
+}
+
+INLINEOP void indy_t() { // (zeropage indirect),Y with extra cycle
+	uint8_t zp = read6502(cpu.pc++);
+	uint16_t h;
+	h = read6502ZP((uint16_t) zp++);
+	h += (uint16_t) read6502ZP((uint16_t) zp) << 8;
+	if (((h + cpu.y) & 0xff) != (h & 0xff)) cpu.ticks += 1;
+	cpu.ea = h + cpu.y;
+}
+
+INLINEOP uint32_t getvalue() __attribute__ ((hot));
+INLINEOP uint32_t getvalue() {
+	return read6502(cpu.ea);
+}
+
+INLINEOP uint32_t getvalueZP() __attribute__ ((hot));
+INLINEOP uint32_t getvalueZP() {
+	return read6502ZP(cpu.ea);
+}
+
+INLINEOP void putvalue(const uint8_t saveval)  __attribute__ ((hot));
+INLINEOP void putvalue(const uint8_t saveval) {
+	write6502(cpu.ea, saveval);
+}
+
+
+/********************************************************************************************************************/
+/* instruction handler functions                                          											*/
+/********************************************************************************************************************/
+
+/*
+Aliases used in other illegal opcode sources:
+
+SLO = ASO
+SRE = LSE
+ISC = ISB
+ALR = ASR
+SHX = A11 (A11 was a result of only having tested this one on adress $1000)
+SHY = A11
+LAS = LAR
+KIL = JAM, HLT
+*/
+
+#define SETFLAGS(data)                  \
+{                                       \
+  if (!(data))                          \
+    cpu.cpustatus = (cpu.cpustatus & ~FLAG_SIGN) | FLAG_ZERO; \
+  else                                  \
+    cpu.cpustatus = (cpu.cpustatus & ~(FLAG_SIGN|FLAG_ZERO)) | \
+    ((data) & FLAG_SIGN); \
+}
+
+
+INLINEOP void _adc(unsigned data) {
+	unsigned tempval = data;
+	unsigned temp;
+    if (cpu.cpustatus & FLAG_DECIMAL) {
+	  	temp = (cpu.a & 0x0f) + (tempval & 0x0f) + (cpu.cpustatus & FLAG_CARRY);
+		if (temp > 9) temp += 6;
+		if (temp <= 0x0f)
+			temp = (temp & 0xf) + (cpu.a & 0xf0) + (tempval & 0xf0);
+		else
+		    temp = (temp & 0xf) + (cpu.a & 0xf0) + (tempval & 0xf0) + 0x10;
+		if (!((cpu.a + tempval + (cpu.cpustatus & FLAG_CARRY)) & 0xff))
+			setzero();
+		else
+			clearzero();
+		signcalc(temp);
+		if (((cpu.a ^ temp) & 0x80) && !((cpu.a ^ tempval) & 0x80))
+			setoverflow();
+		else
+			clearoverflow();
+		if ((temp & 0x1f0) > 0x90) temp += 0x60;
+		if ((temp & 0xff0) > 0xf0)
+			setcarry();
+		else
+			clearcarry();
+	} else {
+        temp = tempval + cpu.a + (cpu.cpustatus & FLAG_CARRY);
+        SETFLAGS(temp & 0xff);
+        if (!((cpu.a ^ tempval) & 0x80) && ((cpu.a ^ temp) & 0x80))
+            setoverflow();
+        else
+            clearoverflow();
+        if (temp > 0xff)
+            setcarry();
+        else
+            clearcarry();
+    }
+	saveaccum(temp);
+}
+
+INLINEOP void _sbc(unsigned data) {
+	unsigned tempval = data;
+	unsigned temp;
+
+	temp = cpu.a - tempval - ((cpu.cpustatus & FLAG_CARRY) ^ FLAG_CARRY);
+
+    if (cpu.cpustatus & FLAG_DECIMAL) {
+		unsigned tempval2;
+	  	tempval2 = (cpu.a & 0x0f) - (tempval & 0x0f) - ((cpu.cpustatus & FLAG_CARRY) ^ FLAG_CARRY);
+		if (tempval2 & 0x10)
+			tempval2 = ((tempval2 - 6) & 0xf) | ((cpu.a & 0xf0) - (tempval & 0xf0) - 0x10);
+		else
+			tempval2 = (tempval2 & 0xf) | ((cpu.a & 0xf0) - (tempval & 0xf0));
+		if (tempval2 & 0x100)
+			tempval2 -= 0x60;
+		if (temp < 0x100)
+			setcarry();
+		else
+			clearcarry();
+		SETFLAGS(temp & 0xff);
+		if (((cpu.a ^ temp) & 0x80) && ((cpu.a ^ tempval) & 0x80))
+			setoverflow();
+		else
+			clearoverflow();
+		saveaccum(tempval2);
+	} else {
+		SETFLAGS(temp & 0xff);
+        if (temp < 0x100)
+			setcarry();
+		else
+			clearcarry();
+		if (((cpu.a ^ temp) & 0x80) && ((cpu.a ^ tempval) & 0x80))
+			 setoverflow();
+		else
+			clearoverflow();
+		saveaccum(temp);
+    }
+
+}
+
+INLINEOP void adc() {
+    unsigned data = getvalue();
+	_adc(data);
+}
+
+INLINEOP void adcZP() {
+	unsigned data = getvalueZP();
+	_adc(data);
+
+}
+
+INLINEOP void op_and() {
+	uint32_t result = cpu.a & getvalue();
+	zerocalc(result);
+	signcalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void op_andZP() {
+	uint32_t result = cpu.a & getvalueZP();
+	zerocalc(result);
+	signcalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void asl() {
+	uint32_t result = getvalue();
+	result <<=1;
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+	putvalue(result);
+}
+
+INLINEOP void aslZP() {
+	uint32_t result = getvalueZP();
+	result <<=1;
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+	putvalue(result);
+}
+
+INLINEOP void asla() {
+	uint32_t result = cpu.a << 1;
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void bcc() {
+	if ((cpu.cpustatus & FLAG_CARRY) == 0) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void bcs() {
+	if ((cpu.cpustatus & FLAG_CARRY) == FLAG_CARRY) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void beq() {
+	if ((cpu.cpustatus & FLAG_ZERO) == FLAG_ZERO) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void op_bit() {
+	 unsigned value = getvalue();
+	 cpu.cpustatus = (cpu.cpustatus & ~(FLAG_SIGN|FLAG_OVERFLOW)) | (value & (FLAG_SIGN|FLAG_OVERFLOW));
+	 if (!(value & cpu.a))
+			setzero();
+		else
+			clearzero();
+/*
+	uint32_t value = getvalue();
+	uint32_t result = (uint16_t)cpu.a & value;
+
+	zerocalc(result);
+	cpu.cpustatus = (cpu.cpustatus & 0x3F) | (uint8_t)(value & 0xC0);
+*/
+}
+
+INLINEOP void op_bitZP() {
+	unsigned value = getvalueZP();
+	cpu.cpustatus = (cpu.cpustatus & ~(FLAG_SIGN|FLAG_OVERFLOW)) | (value & (FLAG_SIGN|FLAG_OVERFLOW));
+	if (!(value & cpu.a))
+			setzero();
+		else
+			clearzero();
+}
+
+INLINEOP void bmi() {
+	if ((cpu.cpustatus & FLAG_SIGN) == FLAG_SIGN) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void bne() {
+	if ((cpu.cpustatus & FLAG_ZERO) == 0) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void bpl() {
+	if ((cpu.cpustatus & FLAG_SIGN) == 0) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void brk() {
+	cpu.pc++;
+	push16(cpu.pc); //push next instruction address onto stack
+	push8(cpu.cpustatus | FLAG_BREAK); //push CPU cpustatus to stack
+	setinterrupt(); //set interrupt flag
+	cpu.pc = read6502(0xFFFE) | (read6502(0xFFFF) << 8);
+}
+
+INLINEOP void bvc() {
+	if ((cpu.cpustatus & FLAG_OVERFLOW) == 0) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void bvs() {
+	if ((cpu.cpustatus & FLAG_OVERFLOW) == FLAG_OVERFLOW) {
+		uint32_t oldpc = cpu.pc;
+		cpu.pc += cpu.reladdr;
+		if ((oldpc & 0xFF00) != (cpu.pc & 0xFF00)) cpu.ticks += 2; //check if jump crossed a page boundary
+		else cpu.ticks++;
+	}
+}
+
+INLINEOP void clc() {
+	clearcarry();
+}
+
+INLINEOP void cld() {
+	cleardecimal();
+}
+
+INLINEOP void cli_() {
+	clearinterrupt();
+}
+
+INLINEOP void clv() {
+	clearoverflow();
+}
+
+INLINEOP void cmp() {
+	uint16_t value = getvalue();
+	uint32_t result = (uint16_t)cpu.a - value;
+
+	if (cpu.a >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.a == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void cmpZP() {
+	uint16_t value = getvalueZP();
+	uint32_t result = (uint16_t)cpu.a - value;
+
+	if (cpu.a >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.a == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void cpx() {
+	uint16_t value = getvalue();
+	uint16_t result = (uint16_t)cpu.x - value;
+
+	if (cpu.x >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.x == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void cpxZP() {
+	uint16_t value = getvalueZP();
+	uint16_t result = (uint16_t)cpu.x - value;
+
+	if (cpu.x >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.x == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void cpy() {
+	uint16_t value = getvalue();
+	uint16_t result = (uint16_t)cpu.y - value;
+
+	if (cpu.y >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.y == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void cpyZP() {
+	uint16_t value = getvalueZP();
+	uint16_t result = (uint16_t)cpu.y - value;
+
+	if (cpu.y >= (uint8_t)(value & 0x00FF)) setcarry();
+	else clearcarry();
+	if (cpu.y == (uint8_t)(value & 0x00FF)) setzero();
+	else clearzero();
+	signcalc(result);
+}
+
+INLINEOP void dec() {
+	uint32_t result = getvalue() - 1;
+
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void decZP() {
+	uint32_t result = getvalueZP() - 1;
+
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void dex() {
+	cpu.x--;
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void dey() {
+	cpu.y--;
+
+	zerocalc(cpu.y);
+	signcalc(cpu.y);
+}
+
+INLINEOP void eor() {
+	uint32_t result = cpu.a ^ getvalue();
+
+	zerocalc(result);
+	signcalc(result);
+
+	saveaccum(result);
+}
+
+INLINEOP void eorZP() {
+	uint32_t result = cpu.a ^ getvalueZP();
+
+	zerocalc(result);
+	signcalc(result);
+
+	saveaccum(result);
+}
+
+INLINEOP void inc() {
+	uint32_t result = getvalue() + 1;
+
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void incZP() {
+	uint32_t result = getvalueZP() + 1;
+
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void inx() {
+	cpu.x++;
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void iny() {
+	cpu.y++;
+
+	zerocalc(cpu.y);
+	signcalc(cpu.y);
+}
+
+INLINEOP void jmp() {
+	cpu.pc = cpu.ea;
+}
+
+INLINEOP void jsr() {
+	push16(cpu.pc - 1);
+	cpu.pc = cpu.ea;
+}
+
+INLINEOP void lda() {
+	cpu.a = getvalue();
+
+	zerocalc(cpu.a);
+	signcalc(cpu.a);
+}
+
+INLINEOP void ldaZP() {
+	cpu.a = getvalueZP();
+
+	zerocalc(cpu.a);
+	signcalc(cpu.a);
+}
+
+INLINEOP void ldx() {
+	cpu.x = getvalue();
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void ldxZP() {
+	cpu.x = getvalue();
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void ldy() {
+	cpu.y = getvalue();
+
+	zerocalc(cpu.y);
+	signcalc(cpu.y);
+}
+
+INLINEOP void ldyZP() {
+	cpu.y = getvalueZP();
+
+	zerocalc(cpu.y);
+	signcalc(cpu.y);
+}
+
+INLINEOP void lsr() {
+	uint32_t value = getvalue();
+	uint32_t result = value >> 1;
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	//clearsign();
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void lsrZP() {
+	uint32_t value = getvalue();
+	uint32_t result = value >> 1;
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	//clearsign();
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void lsra() {
+	uint8_t value = cpu.a;
+	uint8_t result = value >> 1;
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	//clearsign();
+	signcalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void ora() {
+
+	uint32_t result = cpu.a | getvalue();
+
+	zerocalc(result);
+	signcalc(result);
+
+	saveaccum(result);
+}
+
+INLINEOP void oraZP() {
+
+	uint32_t result = cpu.a | getvalueZP();
+
+	zerocalc(result);
+	signcalc(result);
+
+	saveaccum(result);
+}
+
+INLINEOP void pha() {
+	push8(cpu.a);
+}
+
+INLINEOP void php() {
+	push8(cpu.cpustatus | FLAG_BREAK);
+}
+
+INLINEOP void pla() {
+	cpu.a = pull8();
+
+	zerocalc(cpu.a);
+	signcalc(cpu.a);
+}
+
+INLINEOP void plp() {
+	cpu.cpustatus = (pull8() & 0xef) | FLAG_CONSTANT;
+}
+
+INLINEOP void rol() {
+	uint16_t value = getvalue();
+	uint16_t result = (value << 1) | (cpu.cpustatus & FLAG_CARRY);
+
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void rolZP() {
+	uint16_t value = getvalueZP();
+	uint16_t result = (value << 1) | (cpu.cpustatus & FLAG_CARRY);
+
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void rola() {
+	uint16_t value = cpu.a;
+	uint16_t result = (value << 1) | (cpu.cpustatus & FLAG_CARRY);
+
+	carrycalc(result);
+	zerocalc(result);
+	signcalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void ror() {
+	uint32_t value = getvalue();
+	uint16_t result = (value >> 1) | ((cpu.cpustatus & FLAG_CARRY) << 7);
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void rorZP() {
+	uint32_t value = getvalueZP();
+	uint16_t result = (value >> 1) | ((cpu.cpustatus & FLAG_CARRY) << 7);
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	signcalc(result);
+
+	putvalue(result);
+}
+
+INLINEOP void rora() {
+	uint32_t value = cpu.a;
+	uint16_t result = (value >> 1) | ((cpu.cpustatus & FLAG_CARRY) << 7);
+
+	if (value & 1) setcarry();
+	else clearcarry();
+	zerocalc(result);
+	signcalc(result);
+	saveaccum(result);
+}
+
+
+INLINEOP void rti() {
+	cpu.cpustatus = pull8();
+	cpu.pc = pull16();
+}
+
+INLINEOP void rts() {
+	cpu.pc = pull16() + 1;
+}
+
+INLINEOP void sbc() {
+    unsigned data = getvalue();
+	_sbc(data);
+}
+
+INLINEOP void sbcZP() {
+	 unsigned data = getvalueZP();
+	_sbc(data);
+}
+
+
+INLINEOP void sec() {
+	setcarry();
+}
+
+INLINEOP void sed() {
+	setdecimal();
+}
+
+INLINEOP void sei_() {
+	setinterrupt();
+}
+
+INLINEOP void sta() {
+	putvalue(cpu.a);
+}
+
+INLINEOP void stx() {
+	putvalue(cpu.x);
+}
+
+INLINEOP void sty() {
+	putvalue(cpu.y);
+}
+
+INLINEOP void tax() {
+	cpu.x = cpu.a;
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void tay() {
+	cpu.y = cpu.a;
+
+	zerocalc(cpu.y);
+	signcalc(cpu.y);
+}
+
+INLINEOP void tsx() {
+
+	cpu.x = cpu.sp;
+
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+
+}
+
+INLINEOP void txa() {
+	cpu.a = cpu.x;
+
+	zerocalc(cpu.a);
+	signcalc(cpu.a);
+}
+
+INLINEOP void txs() {
+	cpu.sp = cpu.x;
+}
+
+INLINEOP void tya() {
+	cpu.a = cpu.y;
+
+	zerocalc(cpu.a);
+	signcalc(cpu.a);
+}
+
+
+//undocumented instructions
+INLINEOP void lax() {
+	lda();
+	ldx();
+}
+
+INLINEOP void sax() {
+	sta();
+	stx();
+	putvalue(cpu.a & cpu.x);
+}
+
+INLINEOP void dcp() {
+	dec();
+	cmp();
+}
+
+INLINEOP void isb() {
+	inc();
+	sbc();
+}
+
+INLINEOP void slo() {
+	asl();
+	ora();
+}
+
+INLINEOP void rla() {
+	rol();
+	op_and();
+}
+
+INLINEOP void sre() {
+	lsr();
+	eor();
+}
+
+INLINEOP void rra() {
+	ror();
+	adc();
+}
+
+INLINEOP void alr() { // (FB)
+
+	uint32_t result = cpu.a & getvalue() ;
+
+	if (result & 1) setcarry();
+	else clearcarry();
+
+	result = result / 2;
+
+	clearsign();
+	zerocalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void arr() { //This one took me hours.. finally taken from VICE (FB)
+   uint32_t result;
+   result = cpu.a & getvalue();
+   if (!(cpu.cpustatus & FLAG_DECIMAL)) {
+		result >>= 1;
+		result |= ((cpu.cpustatus & FLAG_CARRY) << 7);
+		signcalc(result);
+		zerocalc(result);
+		if (result & 0x40) setcarry(); else clearcarry();
+		if ((result & 0x40) ^ ((result & 0x20)<<1)) setoverflow(); else clearoverflow();
+		saveaccum(result);
+   } else {
+		uint32_t t2 = result;
+		t2 >>= 1;
+		t2 |= ((cpu.cpustatus & FLAG_CARRY) << 7);
+		if (cpu.cpustatus & FLAG_CARRY) setsign(); else clearsign();
+		zerocalc(t2);
+		if ((t2 ^ result) & 0x40) setoverflow(); else clearoverflow();
+	    if (((result & 0xf) + (result & 0x1)) > 0x5) {
+                t2 = (t2 & 0xf0) | ((t2 + 0x6) & 0xf);
+        }
+        if (((result & 0xf0) + (result & 0x10)) > 0x50) {
+                t2 = (t2 & 0x0f) | ((t2 + 0x60) & 0xf0);
+                setcarry();
+        } else {
+                clearcarry();
+        }
+	   saveaccum(t2);
+   }
+
+}
+
+INLINEOP void xaa() { // AKA ANE
+	const uint32_t val = 0xee; // VICE uses 0xff - but this results in an error in the testsuite (FB)
+	uint32_t result = (cpu.a | val) & cpu.x & getvalue();
+	signcalc(result);
+	zerocalc(result);
+	saveaccum(result);
+}
+
+INLINEOP void lxa() {
+	const uint32_t val = 0xee;
+	uint32_t result = (cpu.a | val) & getvalue();
+	signcalc(result);
+	zerocalc(result);
+	cpu.x = result;
+	saveaccum(result);
+}
+
+INLINEOP void axs() { //aka SBX
+    uint32_t result = getvalue();
+    result = (cpu.a & cpu.x) - result;
+	cpu.x = result;
+	if (result < 0x100) setcarry(); else clearcarry();
+	zerocalc(cpu.x);
+	signcalc(cpu.x);
+}
+
+INLINEOP void ahx() { //todo (is unstable)
+	UNSUPPORTED
+}
+
+INLINEOP void anc() {
+	uint32_t result = cpu.a & getvalue();
+	signcalc(result)
+    zerocalc(result);
+	if (cpu.cpustatus & FLAG_SIGN) setcarry(); else clearcarry();
+    saveaccum(result);
+}
+
+INLINEOP void las() {
+	uint32_t result = cpu.sp & getvalue();
+	signcalc(result);
+	zerocalc(result);
+	cpu.sp = result;
+	cpu.x = result;
+	saveaccum(result);
+}
+
+/********************************************************************************************************************/
+/* OPCODES																																																					*/
+/********************************************************************************************************************/
+
+OPCODE void opKIL(void) {
+	printf("CPU JAM @ $%d\n",cpu.pc);
+	cpu_reset();
+}
+
+OPCODE void op0x0(void) {
+	cpu.ticks = 7;
+	imp();
+	brk();
+}
+
+OPCODE void op0x1(void) {
+	cpu.ticks = 6;
+	indx();
+	ora();
+}
+
+OPCODE void op0x3(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	slo();
+}
+
+OPCODE void op0x4(void) { //nop read zeropage
+	cpu.ticks = 3;
+	zp();
+}
+
+OPCODE void op0x5(void) {
+	cpu.ticks = 3;
+	zp();
+	oraZP();
+}
+
+OPCODE void op0x6(void) {
+	cpu.ticks = 5;
+	zp();
+	aslZP();
+}
+
+OPCODE void op0x7(void) { //undocumented SLO
+	cpu.ticks = 5;
+	zp();
+	slo();
+}
+
+OPCODE void op0x8(void) {
+	cpu.ticks = 3;
+	imp();
+	php();
+}
+
+OPCODE void op0x9(void) {
+	cpu.ticks = 2;
+	imm();
+	ora();
+}
+
+OPCODE void op0xA(void) {
+	cpu.ticks = 2;
+	//acc();
+	asla();
+}
+
+OPCODE void op0xB(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	anc();
+}
+
+OPCODE void op0xC(void) { //nop
+	cpu.ticks = 4;
+	abso();
+}
+
+OPCODE void op0xD(void) {
+	cpu.ticks = 4;
+	abso();
+	ora();
+}
+
+OPCODE void op0xE(void) {
+	cpu.ticks = 6;
+	abso();
+	asl();
+}
+
+OPCODE void op0xF(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	slo();
+}
+
+OPCODE void op0x10(void) {
+	cpu.ticks = 2;
+	rel();
+	bpl();
+}
+
+OPCODE void op0x11(void) {
+	cpu.ticks = 5;
+	indy_t();
+	ora();
+}
+
+OPCODE void op0x13(void) { //undocumented
+	cpu.ticks = 8;
+	indy();
+	slo();
+}
+
+OPCODE void op0x14(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0x15(void) {
+	cpu.ticks = 4;
+	zpx();
+	ora();
+}
+
+OPCODE void op0x16(void) {
+	cpu.ticks = 6;
+	zpx();
+	asl();
+}
+
+OPCODE void op0x17(void) { //undocumented
+	cpu.ticks = 6;
+	//zpy(); bug
+	zpx();
+	slo();
+}
+
+OPCODE void op0x18(void) {
+	cpu.ticks = 2;
+	imp();
+	clc();
+}
+
+OPCODE void op0x19(void) {
+	cpu.ticks = 4;
+	absy_t();
+	ora();
+}
+
+OPCODE void op0x1A(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0x1B(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	slo();
+}
+
+OPCODE void op0x1C(void) { //nop
+	cpu.ticks = 4;
+	 //();
+}
+
+OPCODE void op0x1D(void) {
+	cpu.ticks = 4;
+	absx_t();
+	ora();
+}
+
+OPCODE void op0x1E(void) {
+	cpu.ticks = 7;
+	absx();
+	asl();
+}
+
+
+OPCODE void op0x1F(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	slo();
+}
+
+OPCODE void op0x20(void) {
+	cpu.ticks = 6;
+	abso();
+	jsr();
+}
+
+OPCODE void op0x21(void) {
+	cpu.ticks = 6;
+	indx();
+	op_and();
+}
+
+OPCODE void op0x23(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	rla();
+}
+
+OPCODE void op0x24(void) {
+	cpu.ticks = 3;
+	zp();
+	op_bitZP();
+}
+
+OPCODE void op0x25(void) {
+	cpu.ticks = 3;
+	zp();
+	op_and();
+}
+
+OPCODE void op0x26(void) {
+	cpu.ticks = 5;
+	zp();
+	rolZP();
+}
+
+OPCODE void op0x27(void) { //undocumented
+	cpu.ticks = 5;
+	zp();
+	rla();
+}
+
+OPCODE void op0x28(void) {
+	cpu.ticks = 4;
+	imp();
+	plp();
+}
+
+OPCODE void op0x29(void) {
+	cpu.ticks = 2;
+	imm();
+	op_and();
+}
+
+OPCODE void op0x2A(void) {
+	cpu.ticks = 2;
+	//acc();
+	rola();
+}
+
+OPCODE void op0x2B(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	anc();
+}
+
+OPCODE void op0x2C(void) {
+	cpu.ticks = 4;
+	abso();
+	op_bit();
+}
+
+OPCODE void op0x2D(void) {
+	cpu.ticks = 4;
+	abso();
+	op_and();
+}
+
+OPCODE void op0x2E(void) {
+	cpu.ticks = 6;
+	abso();
+	rol();
+}
+
+OPCODE void op0x2F(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	rla();
+}
+
+OPCODE void op0x30(void) {
+	cpu.ticks = 2;
+	rel();
+	bmi();
+}
+
+OPCODE void op0x31(void) {
+	cpu.ticks = 5;
+	indy_t();
+	op_and();
+}
+
+OPCODE void op0x33(void) { //undocumented
+	cpu.ticks = 8;
+	indy();
+	rla();
+}
+
+OPCODE void op0x34(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0x35(void) {
+	cpu.ticks = 4;
+	zpx();
+	op_and();
+}
+
+OPCODE void op0x36(void) {
+	cpu.ticks = 6;
+	zpx();
+	rol();
+}
+
+OPCODE void op0x37(void) { //undocumented
+	cpu.ticks = 6;
+	zpx();
+	rla();
+}
+
+OPCODE void op0x38(void) {
+	cpu.ticks = 2;
+	imp();
+	sec();
+}
+
+OPCODE void op0x39(void) {
+	cpu.ticks = 4;
+	absy_t();
+	op_and();
+}
+
+OPCODE void op0x3A(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0x3B(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	rla();
+}
+
+OPCODE void op0x3C(void) { //nop
+	cpu.ticks = 4;
+	absx_t();
+}
+
+OPCODE void op0x3D(void) {
+	cpu.ticks = 4;
+	absx_t();
+	op_and();
+}
+
+OPCODE void op0x3E(void) {
+	cpu.ticks = 7;
+	absx();
+	rol();
+}
+
+OPCODE void op0x3F(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	rla();
+}
+
+OPCODE void op0x40(void) {
+	cpu.ticks = 6;
+	imp();
+	rti();
+}
+
+OPCODE void op0x41(void) {
+	cpu.ticks = 6;
+	indx();
+	eor();
+}
+
+OPCODE void op0x43(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	sre();
+}
+
+OPCODE void op0x44(void) { //nop
+	cpu.ticks = 3;
+	zp();
+}
+
+OPCODE void op0x45(void) {
+	cpu.ticks = 3;
+	zp();
+	eorZP();
+}
+
+OPCODE void op0x46(void) {
+	cpu.ticks = 5;
+	zp();
+	lsrZP();
+}
+
+OPCODE void op0x47(void) { //undocumented
+	cpu.ticks = 5;
+	zp();
+	sre();
+}
+
+OPCODE void op0x48(void) {
+	cpu.ticks = 3;
+	imp();
+	pha();
+}
+
+OPCODE void op0x49(void) {
+	cpu.ticks = 2;
+	imm();
+	eor();
+}
+
+OPCODE void op0x4A(void) {
+	cpu.ticks = 2;
+//	acc();
+	lsra();
+}
+
+OPCODE void op0x4B(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	alr();
+}
+
+OPCODE void op0x4C(void) {
+	cpu.ticks = 3;
+	abso();
+	jmp();
+}
+
+OPCODE void op0x4D(void) {
+	cpu.ticks = 4;
+	abso();
+	eor();
+}
+
+OPCODE void op0x4E(void) {
+	cpu.ticks = 6;
+	abso();
+	lsr();
+}
+
+OPCODE void op0x4F(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	sre();
+}
+
+OPCODE void op0x50(void) {
+	cpu.ticks = 2;
+	rel();
+	bvc();
+}
+
+OPCODE void op0x51(void) {
+	cpu.ticks = 5;
+	indy_t();
+	eor();
+}
+
+OPCODE void op0x53(void) { //undocumented
+	cpu.ticks = 8;
+	//zp(); BUG
+	indy();
+	sre();
+}
+
+OPCODE void op0x54(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0x55(void) {
+	cpu.ticks = 4;
+	zpx();
+	eor();
+}
+
+OPCODE void op0x56(void) {
+	cpu.ticks = 6;
+	zpx();
+	lsr();
+}
+
+OPCODE void op0x57(void) { //undocumented
+	cpu.ticks = 6;
+	zpx();
+	sre();
+}
+
+OPCODE void op0x58(void) {
+	cpu.ticks = 2;
+	imp();
+	cli_();
+}
+
+OPCODE void op0x59(void) {
+	cpu.ticks = 4;
+	absy_t();
+	eor();
+}
+
+OPCODE void op0x5A(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0x5B(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	sre();
+}
+
+OPCODE void op0x5C(void) { //nop
+	cpu.ticks = 4;
+	absx_t();
+}
+
+OPCODE void op0x5D(void) {
+	cpu.ticks = 4;
+	absx_t();
+	eor();
+}
+
+OPCODE void op0x5E(void) {
+	cpu.ticks = 7;
+	absx();
+	lsr();
+}
+
+OPCODE void op0x5F(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	sre();
+}
+
+OPCODE void op0x60(void) {
+	cpu.ticks = 6;
+	imp();
+	rts();
+}
+
+OPCODE void op0x61(void) {
+	cpu.ticks = 6;
+	indx();
+	adc();
+}
+
+OPCODE void op0x63(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	rra();
+}
+
+OPCODE void op0x64(void) {
+	cpu.ticks = 3;
+	zp();
+}
+
+OPCODE void op0x65(void) {
+	cpu.ticks = 3;
+	zp();
+	adcZP();
+}
+
+OPCODE void op0x66(void) {
+	cpu.ticks = 5;
+	zp();
+	rorZP();
+}
+
+OPCODE void op0x67(void) { //undocumented
+	cpu.ticks = 5;
+	zp();
+	rra();
+}
+
+OPCODE void op0x68(void) {
+	cpu.ticks = 4;
+	imp();
+	pla();
+}
+
+OPCODE void op0x69(void) {
+	cpu.ticks = 2;
+	imm();
+	adc();
+}
+
+OPCODE void op0x6A(void) {
+	cpu.ticks = 2;
+//	acc();
+	rora();
+}
+
+OPCODE void op0x6B(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	arr();
+}
+
+OPCODE void op0x6C(void) {
+	cpu.ticks = 5;
+	ind();
+	jmp();
+}
+
+OPCODE void op0x6D(void) {
+	cpu.ticks = 4;
+	abso();
+	adc();
+}
+
+OPCODE void op0x6E(void) {
+	cpu.ticks = 6;
+	abso();
+	ror();
+}
+
+OPCODE void op0x6F(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	rra();
+}
+
+OPCODE void op0x70(void) {
+	cpu.ticks = 2;
+	rel();
+	bvs();
+}
+
+OPCODE void op0x71(void) {
+	cpu.ticks = 5;
+	indy_t();
+	adc();
+}
+
+OPCODE void op0x73(void) { //undocumented
+	cpu.ticks = 8;
+	indy();
+	rra();
+}
+
+OPCODE void op0x74(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0x75(void) {
+	cpu.ticks = 4;
+	zpx();
+	adc();
+}
+
+OPCODE void op0x76(void) {
+	cpu.ticks = 6;
+	zpx();
+	ror();
+}
+
+OPCODE void op0x77(void) { //undocumented
+	cpu.ticks = 6;
+	zpx();
+	rra();
+}
+
+OPCODE void op0x78(void) {
+	cpu.ticks = 2;
+	imp();
+	sei_();
+}
+
+OPCODE void op0x79(void) {
+	cpu.ticks = 4;
+	absy_t();
+	adc();
+}
+
+OPCODE void op0x7A(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0x7B(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	rra();
+}
+
+OPCODE void op0x7C(void) { //nop
+	cpu.ticks = 4;
+	absx_t();
+}
+
+OPCODE void op0x7D(void) {
+	cpu.ticks = 4;
+	absx_t();
+	adc();
+}
+
+OPCODE void op0x7E(void) {
+	cpu.ticks = 7;
+	absx();
+	ror();
+}
+
+OPCODE void op0x7F(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	rra();
+}
+
+OPCODE void op0x80(void) { //nop
+	cpu.ticks = 2;
+	imm();
+}
+
+OPCODE void op0x81(void) {
+	cpu.ticks = 6;
+	indx();
+	sta();
+}
+
+OPCODE void op0x82(void) { //nop
+	cpu.ticks = 2;
+	imm();
+}
+
+OPCODE void op0x83(void) { //undocumented
+	cpu.ticks = 6;
+	indx();
+	sax();
+}
+
+OPCODE void op0x84(void) {
+	cpu.ticks = 3;
+	zp();
+	sty();
+}
+
+OPCODE void op0x85(void) {
+	cpu.ticks = 3;
+	zp();
+	sta();
+}
+
+OPCODE void op0x86(void) {
+	cpu.ticks = 3;
+	zp();
+	stx();
+}
+
+OPCODE void op0x87(void) { //undocumented
+	cpu.ticks = 3;
+	zp();
+	sax();
+}
+
+OPCODE void op0x88(void) {
+	cpu.ticks = 2;
+	imp();
+	dey();
+}
+
+OPCODE void op0x89(void) { //nop
+	cpu.ticks = 2;
+	imm();
+}
+
+OPCODE void op0x8A(void) {
+	cpu.ticks = 2;
+	imp();
+	txa();
+}
+
+OPCODE void op0x8B(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	xaa();
+}
+
+OPCODE void op0x8C(void) {
+	cpu.ticks = 4;
+	abso();
+	sty();
+}
+
+OPCODE void op0x8D(void) {
+	cpu.ticks = 4;
+	abso();
+	sta();
+}
+
+OPCODE void op0x8E(void) {
+	cpu.ticks = 4;
+	abso();
+	stx();
+}
+
+OPCODE void op0x8F(void) { //undocumented
+	cpu.ticks = 4;
+	abso();
+	sax();
+}
+
+OPCODE void op0x90(void) {
+	cpu.ticks = 2;
+	rel();
+	bcc();
+}
+
+OPCODE void op0x91(void) {
+	cpu.ticks = 6;
+	indy();
+	sta();
+}
+
+OPCODE void op0x93(void) { //undocumented
+	cpu.ticks = 6;
+	indy();
+	ahx();
+}
+
+OPCODE void op0x94(void) {
+	cpu.ticks = 4;
+	zpx();
+	sty();
+}
+
+OPCODE void op0x95(void) {
+	cpu.ticks = 4;
+	zpx();
+	sta();
+}
+
+OPCODE void op0x96(void) {
+	cpu.ticks = 4;
+	zpy();
+	stx();
+}
+
+OPCODE void op0x97(void) { //undocumented
+	cpu.ticks = 4;
+	zpy();
+	sax();
+}
+
+OPCODE void op0x98(void) {
+	cpu.ticks = 2;
+	imp();
+	tya();
+}
+
+OPCODE void op0x99(void) {
+	cpu.ticks = 5;
+	absy();
+	sta();
+}
+
+OPCODE void op0x9A(void) {
+	cpu.ticks = 2;
+	imp();
+	txs();
+}
+
+OPCODE void op0x9B(void) { //undocumented
+	cpu.ticks = 5;
+	absy();
+	//tas();
+	UNSUPPORTED;
+}
+
+OPCODE void op0x9C(void) { //undocumented
+	cpu.ticks = 5;
+	absy();
+	//shy();
+	UNSUPPORTED;
+}
+
+OPCODE void op0x9D(void) {
+	cpu.ticks = 5;
+	absx();
+	sta();
+}
+
+OPCODE void op0x9E(void) { //undocumented
+	cpu.ticks = 5;
+	absx();
+	//shx();
+}
+
+OPCODE void op0x9F(void) { //undocumented
+	cpu.ticks = 5;
+	absx();
+	ahx();
+}
+
+OPCODE void op0xA0(void) {
+	cpu.ticks = 2;
+	imm();
+	ldy();
+}
+
+OPCODE void op0xA1(void) {
+	cpu.ticks = 6;
+	indx();
+	lda();
+}
+
+OPCODE void op0xA2(void) {
+	cpu.ticks = 2;
+	imm();
+	ldx();
+}
+
+OPCODE void op0xA3(void) { //undocumented
+	cpu.ticks = 6;
+	indx();
+	lax();
+}
+
+OPCODE void op0xA4(void) {
+	cpu.ticks = 3;
+	zp();
+	ldyZP();
+}
+
+OPCODE void op0xA5(void) {
+	cpu.ticks = 3;
+	zp();
+	ldaZP();
+}
+
+OPCODE void op0xA6(void) {
+	cpu.ticks = 3;
+	zp();
+	ldxZP();
+}
+
+OPCODE void op0xA7(void) { //undocumented
+	cpu.ticks = 3;
+	zp();
+	lax();
+}
+
+OPCODE void op0xA8(void) {
+	cpu.ticks = 2;
+	imp();
+	tay();
+}
+
+OPCODE void op0xA9(void) {
+	cpu.ticks = 2;
+	imm();
+	lda();
+}
+
+OPCODE void op0xAA(void) {
+	cpu.ticks = 2;
+	imp();
+	tax();
+}
+
+OPCODE void op0xAB(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	lxa();
+}
+
+OPCODE void op0xAC(void) {
+	cpu.ticks = 4;
+	abso();
+	ldy();
+}
+
+OPCODE void op0xAD(void) {
+	cpu.ticks = 4;
+	abso();
+	lda();
+}
+
+OPCODE void op0xAE(void) {
+	cpu.ticks = 4;
+	abso();
+	ldx();
+}
+
+OPCODE void op0xAF(void) { //undocumented
+	cpu.ticks = 4;
+	abso();
+	lax();
+}
+
+OPCODE void op0xB0(void) {
+	cpu.ticks = 2;
+	rel();
+	bcs();
+}
+
+OPCODE void op0xB1(void) {
+	cpu.ticks = 5;
+	indy_t();
+	lda();
+}
+
+OPCODE void op0xB3(void) { //undocumented
+	cpu.ticks = 5;
+	indy_t();
+	lax();
+}
+
+OPCODE void op0xB4(void) {
+	cpu.ticks = 4;
+	zpx();
+	ldy();
+}
+
+OPCODE void op0xB5(void) {
+	cpu.ticks = 4;
+	zpx();
+	lda();
+}
+
+OPCODE void op0xB6(void) {
+	cpu.ticks = 4;
+	zpy();
+	ldx();
+}
+
+OPCODE void op0xB7(void) { //undocumented
+	cpu.ticks = 4;
+	zpy();
+	lax();
+}
+
+OPCODE void op0xB8(void) {
+	cpu.ticks = 2;
+	imp();
+	clv();
+}
+
+OPCODE void op0xB9(void) {
+	cpu.ticks = 4;
+	absy_t();
+	lda();
+}
+
+OPCODE void op0xBA(void) {
+	cpu.ticks = 2;
+	imp();
+	tsx();
+}
+
+OPCODE void op0xBB(void) { //undocumented
+	cpu.ticks = 4;
+	absy_t();
+	las();
+}
+
+OPCODE void op0xBC(void) {
+	cpu.ticks = 4;
+	absx_t();
+	ldy();
+}
+
+OPCODE void op0xBD(void) {
+	cpu.ticks = 4;
+	absx_t();
+	lda();
+}
+
+OPCODE void op0xBE(void) {
+	cpu.ticks = 4;
+	absy_t();
+	ldx();
+}
+
+OPCODE void op0xBF(void) { //undocumented
+	cpu.ticks = 4;
+	absy_t();
+	lax();
+}
+
+OPCODE void op0xC0(void) {
+	cpu.ticks = 2;
+	imm();
+	cpy();
+}
+
+OPCODE void op0xC1(void) {
+	cpu.ticks = 6;
+	indx();
+	cmp();
+}
+
+OPCODE void op0xC2(void) { //nop
+	cpu.ticks = 2;
+	imm();
+}
+
+OPCODE void op0xC3(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	dcp();
+}
+
+OPCODE void op0xC4(void) {
+	cpu.ticks = 3;
+	zp();
+	cpyZP();
+}
+
+OPCODE void op0xC5(void) {
+	cpu.ticks = 3;
+	zp();
+	cmpZP();
+}
+
+OPCODE void op0xC6(void) {
+	cpu.ticks = 5;
+	zp();
+	decZP();
+}
+
+OPCODE void op0xC7(void) { //undocumented
+	cpu.ticks = 5;
+	zp();
+	dcp();
+}
+
+OPCODE void op0xC8(void) {
+	cpu.ticks = 2;
+	imp();
+	iny();
+}
+
+OPCODE void op0xC9(void) {
+	cpu.ticks = 2;
+	imm();
+	cmp();
+}
+
+OPCODE void op0xCA(void) {
+	cpu.ticks = 2;
+	imp();
+	dex();
+}
+
+OPCODE void op0xCB(void) { //undocumented
+	cpu.ticks = 2;
+	imm();
+	axs();
+}
+
+OPCODE void op0xCC(void) {
+	cpu.ticks = 4;
+	abso();
+	cpy();
+}
+
+OPCODE void op0xCD(void) {
+	cpu.ticks = 4;
+	abso();
+	cmp();
+}
+
+OPCODE void op0xCE(void) {
+	cpu.ticks = 6;
+	abso();
+	dec();
+}
+
+OPCODE void op0xCF(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	dcp();
+}
+
+OPCODE void op0xD0(void) {
+	cpu.ticks = 2;
+	rel();
+	bne();
+}
+
+OPCODE void op0xD1(void) {
+	cpu.ticks = 5;
+	indy_t();
+	cmp();
+}
+
+OPCODE void op0xD3(void) { //undocumented
+	cpu.ticks = 8;
+	indy();
+	dcp();
+}
+
+OPCODE void op0xD4(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0xD5(void) {
+	cpu.ticks = 4;
+	zpx();
+	cmp();
+}
+
+OPCODE void op0xD6(void) {
+	cpu.ticks = 6;
+	zpx();
+	dec();
+}
+
+OPCODE void op0xD7(void) { //undocumented
+	cpu.ticks = 6;
+	zpx();
+	dcp();
+}
+
+OPCODE void op0xD8(void) {
+	cpu.ticks = 2;
+	imp();
+	cld();
+}
+
+OPCODE void op0xD9(void) {
+	cpu.ticks = 4;
+	absy_t();
+	cmp();
+}
+
+OPCODE void op0xDA(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0xDB(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	dcp();
+}
+
+OPCODE void op0xDC(void) { //nop
+	cpu.ticks = 4;
+	absx_t();
+}
+
+OPCODE void op0xDD(void) {
+	cpu.ticks = 4;
+	absx_t();
+	cmp();
+}
+
+OPCODE void op0xDE(void) {
+	cpu.ticks = 7;
+	absx();
+	dec();
+}
+
+OPCODE void op0xDF(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	dcp();
+}
+
+OPCODE void op0xE0(void) {
+	cpu.ticks = 2;
+	imm();
+	cpx();
+}
+
+OPCODE void op0xE1(void) {
+	cpu.ticks = 5;
+	indx();
+	sbc();
+}
+
+OPCODE void op0xE2(void) { //NOP
+	cpu.ticks = 2;
+	imm();
+}
+
+OPCODE void op0xE3(void) { //undocumented
+	cpu.ticks = 8;
+	indx();
+	isb();
+}
+
+OPCODE void op0xE4(void) {
+	cpu.ticks = 3;
+	zp();
+	cpxZP();
+}
+
+OPCODE void op0xE5(void) {
+	cpu.ticks = 3;
+	zp();
+	sbcZP();
+}
+
+OPCODE void op0xE6(void) {
+	cpu.ticks = 5;
+	zp();
+	incZP();
+}
+
+OPCODE void op0xE7(void) { //undocumented
+	cpu.ticks = 5;
+	zp();
+	isb();
+}
+
+OPCODE void op0xE8(void) {
+	cpu.ticks = 2;
+	imp();
+	inx();
+}
+
+OPCODE void op0xE9(void) {
+	cpu.ticks = 2;
+	imm();
+	sbc();
+}
+
+OPCODE void op0xEA(void) {
+	cpu.ticks = 2;
+}
+
+OPCODE void op0xEB(void) {
+	cpu.ticks = 2;
+	imm();
+	sbc();
+}
+
+OPCODE void op0xEC(void) {
+	cpu.ticks = 4;
+	abso();
+	cpx();
+}
+
+OPCODE void op0xED(void) {
+	cpu.ticks = 4;
+	abso();
+	sbc();
+}
+
+OPCODE void op0xEE(void) {
+	cpu.ticks = 6;
+	abso();
+	inc();
+}
+
+OPCODE void op0xEF(void) { //undocumented
+	cpu.ticks = 6;
+	abso();
+	isb();
+}
+
+OPCODE void op0xF0(void) {
+	cpu.ticks = 2;
+	rel();
+	beq();
+}
+
+OPCODE void op0xF1(void) {
+	cpu.ticks = 5;
+	indy_t();
+	sbc();
+}
+
+OPCODE void op0xF3(void) { //undocumented
+	cpu.ticks = 8;
+	indy();
+	isb();
+}
+
+OPCODE void op0xF4(void) { //nop
+	cpu.ticks = 4;
+	zpx();
+}
+
+OPCODE void op0xF5(void) {
+	cpu.ticks = 4;
+	zpx();
+	sbc();
+}
+
+OPCODE void op0xF6(void) {
+	cpu.ticks = 6;
+	zpx();
+	inc();
+}
+
+OPCODE void op0xF7(void) { //undocumented
+	cpu.ticks = 6;
+	zpx();
+	isb();
+}
+
+OPCODE void op0xF8(void) {
+	cpu.ticks = 2;
+	imp();
+	sed();
+}
+
+OPCODE void op0xF9(void) {
+	cpu.ticks = 4;
+	absy_t();
+	sbc();
+}
+
+OPCODE void op0xFA(void) { //nop
+	cpu.ticks = 2;
+}
+
+OPCODE void op0xFB(void) { //undocumented
+	cpu.ticks = 7;
+	absy();
+	isb();
+}
+
+OPCODE void op0xFC(void) { //nop
+	cpu.ticks = 4;
+	absx_t();
+}
+
+OPCODE void op0xFD(void) {
+	cpu.ticks = 4;
+	absx_t();
+	sbc();
+}
+
+OPCODE void op0xFE(void) {
+	cpu.ticks = 7;
+	absx();
+	inc();
+}
+
+OPCODE void op0xFF(void) { //undocumented
+	cpu.ticks = 7;
+	absx();
+	isb();
+}
+
+OPCODE void opPATCHD2(void) {
+#if APPLY_PATCHES
+	patchLOAD();
+#else
+	opKIL();
+#endif
+}
+
+OPCODE void opPATCHF2(void) {
+#if APPLY_PATCHES
+	patchSAVE();
+#else
+	opKIL();
+#endif
+}
+
+typedef void (*op_ptr_t)( void );
+
+static const op_ptr_t opcodetable[256] = {
+  /*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F */
+  /* 0  */    op0x0 , op0x1,  opKIL , op0x3,  op0x4 , op0x5,  op0x6,  op0x7,  op0x8,  op0x9,  op0xA,  op0xB , op0xC , op0xD , op0xE , op0xF,
+  /* 1  */    op0x10, op0x11, opKIL , op0x13, op0x14, op0x15, op0x16, op0x17, op0x18, op0x19, op0x1A, op0x1B, op0x1C, op0x1D, op0x1E, op0x1F,
+  /* 2  */    op0x20, op0x21, opKIL , op0x23, op0x24, op0x25, op0x26, op0x27, op0x28, op0x29, op0x2A, op0x2B, op0x2C, op0x2D, op0x2E, op0x2F,
+  /* 3  */    op0x30, op0x31, opKIL , op0x33, op0x34, op0x35, op0x36, op0x37, op0x38, op0x39, op0x3A, op0x3B, op0x3C, op0x3D, op0x3E, op0x3F,
+  /* 4  */    op0x40, op0x41, opKIL , op0x43, op0x44, op0x45, op0x46, op0x47, op0x48, op0x49, op0x4A, op0x4B, op0x4C, op0x4D, op0x4E, op0x4F,
+  /* 5  */    op0x50, op0x51, opKIL , op0x53, op0x54, op0x55, op0x56, op0x57, op0x58, op0x59, op0x5A, op0x5B, op0x5C, op0x5D, op0x5E, op0x5F,
+  /* 6  */    op0x60, op0x61, opKIL , op0x63, op0x64, op0x65, op0x66, op0x67, op0x68, op0x69, op0x6A, op0x6B, op0x6C, op0x6D, op0x6E, op0x6F,
+  /* 7  */    op0x70, op0x71, opKIL , op0x73, op0x74, op0x75, op0x76, op0x77, op0x78, op0x79, op0x7A, op0x7B, op0x7C, op0x7D, op0x7E, op0x7F,
+  /* 8  */    op0x80, op0x81, op0x82, op0x83, op0x84, op0x85, op0x86, op0x87, op0x88, op0x89, op0x8A, op0x8B, op0x8C, op0x8D, op0x8E, op0x8F,
+  /* 9  */    op0x90, op0x91, opKIL , op0x93, op0x94, op0x95, op0x96, op0x97, op0x98, op0x99, op0x9A, op0x9B, op0x9C, op0x9D, op0x9E, op0x9F,
+  /* A  */    op0xA0, op0xA1, op0xA2, op0xA3, op0xA4, op0xA5, op0xA6, op0xA7, op0xA8, op0xA9, op0xAA, op0xAB, op0xAC, op0xAD, op0xAE, op0xAF,
+  /* B  */    op0xB0, op0xB1, opKIL , op0xB3, op0xB4, op0xB5, op0xB6, op0xB7, op0xB8, op0xB9, op0xBA, op0xBB, op0xBC, op0xBD, op0xBE, op0xBF,
+  /* C  */    op0xC0, op0xC1, op0xC2, op0xC3, op0xC4, op0xC5, op0xC6, op0xC7, op0xC8, op0xC9, op0xCA, op0xCB, op0xCC, op0xCD, op0xCE, op0xCF,
+  /* D  */    op0xD0, op0xD1, opPATCHD2 , op0xD3, op0xD4, op0xD5, op0xD6, op0xD7, op0xD8, op0xD9, op0xDA, op0xDB, op0xDC, op0xDD, op0xDE, op0xDF,
+  /* E  */    op0xE0, op0xE1, op0xE2, op0xE3, op0xE4, op0xE5, op0xE6, op0xE7, op0xE8, op0xE9, op0xEA, op0xEB, op0xEC, op0xED, op0xEE, op0xEF,
+  /* F  */    op0xF0, op0xF1, opPATCHF2 , op0xF3, op0xF4, op0xF5, op0xF6, op0xF7, op0xF8, op0xF9, op0xFA, op0xFB, op0xFC, op0xFD, op0xFE, op0xFF
+};
+
+static const uint8_t cyclesTable[256] =
+{
+	7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6,  // $00
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7,  // $10
+	6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6,  // $20
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7,  // $30
+	6, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6,  // $40
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7,  // $50
+	6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6,  // $60
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7,  // $70
+	2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,  // $80
+	2, 6, 2, 6, 4, 4, 4, 4, 2, 5, 2, 5, 5, 5, 5, 5,  // $90
+	2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,  // $A0
+	2, 5, 2, 5, 4, 4, 4, 4, 2, 4, 2, 5, 4, 4, 4, 4,  // $B0
+	2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,  // $C0
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7,  // $D0
+	2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,  // $E0
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 5, 5, 7, 7   // $F0
+};
+
+static const uint8_t writeCycleTable[256] =
+{
+    3, 0, 0, 2, 0, 0, 2, 2, 1, 0, 0, 0, 0, 0, 2, 2, // $00
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2, // $10
+    2, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 2, 2, // $20
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2, // $30
+    0, 0, 0, 2, 0, 0, 2, 2, 1, 0, 0, 0, 0, 0, 2, 2, // $40
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2, // $50
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 2, 2, // $60
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2, // $70
+    0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, // $80
+    0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, // $90
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // $A0
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // $B0
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 2, 2, // $C0
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2, // $D0
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 2, 2, // $E0
+    0, 0, 0, 2, 0, 0, 2, 2, 0, 0, 0, 2, 0, 0, 2, 2  // $F0
+};
+
+
+void cpu_nmi() {
+  cpu.nmiLine = 1;
+  printf("nmiLine=1\n");
+}
+void cpu_clearNmi() {
+	cpu.nmi = 0;
+}
+
+void cpu_nmi_do() {
+	if (cpu.nmi) return;
+	cpu.nmi = 1;
+	cpu.nmiLine = 0;
+	push16(cpu.pc);
+	push8(cpu.cpustatus & ~FLAG_BREAK);
+	cpu.cpustatus |= FLAG_INTERRUPT;
+	cpu.pc = read6502(0xFFFA) | (read6502(0xFFFB) << 8);
+	cpu.ticks = 7;
+}
+
+static inline void cpu_irq() {
+  push16(cpu.pc);
+  push8(cpu.cpustatus & ~FLAG_BREAK);
+  cpu.cpustatus |= FLAG_INTERRUPT;
+  cpu.pc = read6502(0xFFFE) | (read6502(0xFFFF) << 8);
+  cpu.ticks = 7;
+}
+
+inline void cia_clock(void)  __attribute__((always_inline));
+
+void cia_clock(void) {
+	cia1_clock(1);
+	cia2_clock(1);
+}
+
+void cia_clockt(int ticks) {
+	cia1_clock(ticks);
+	cia2_clock(ticks);
+}
+
+void cpu_clock(int cycles) {
+static int c = 0;
+static int writeCycles = 0;
+	cpu.lineCyclesAbs += cycles;
+    c+=cycles;
+	while (c > 0) {
+
+			uint8_t opcode ;
+			cpu.ticks = 0;
+
+			//NMI
+
+			if (!cpu.nmi && ((cpu.cia2.R[0x0D] & 0x80) | cpu.nmiLine)) {
+				cpu_nmi_do();
+				goto noOpcode;
+			}
+
+		    if (!(cpu.cpustatus & FLAG_INTERRUPT)) {
+				if (((cpu.vic.R[0x19] | cpu.cia1.R[0x0D]) & 0x80)) {
+					cpu_irq();
+					goto noOpcode;
+				}
+			}
+
+			cpu.cpustatus |= FLAG_CONSTANT;
+			opcode = read6502(cpu.pc++);
+			opcodetable[opcode]();
+			writeCycles = writeCycleTable[opcode];
+noOpcode:
+
+			cia_clockt(cpu.ticks);
+			c-= cpu.ticks;
+			cpu.lineCycles += cpu.ticks;
+#define US_C64_CYCLE    (1000000.0f / CLOCKSPEED) // Duration (µs) of a C64 Cycle
+			if (cpu.exactTiming) {
+				uint32_t t = cpu.lineCycles * US_C64_CYCLE;
+				while (fbmicros() - cpu.lineStartTime < t){;}
+			}
+
+	};
+
+	return;
+}
+
+//Enable "ExactTiming" Mode
+void cpu_setExactTiming() {
+	if (!cpu.exactTiming) {
+		//enable exact timing
+		setAudioOff();
+		vic_displaySimpleModeScreen();
+
+	}
+	cpu.exactTiming = 1;
+	cpu.exactTimingStartTime = fbmicros();
+	//cpu.exactTiming = 0;
+}
+
+//Disable "ExactTiming" Mode
+void cpu_disableExactTiming() {
+    cpu.exactTiming = 0;
+    setAudioOn();
+}
+
+void cpu_reset() {
+  enableCycleCounter();
+  cpu.exactTiming = 0;
+  cpu.nmi = 0;
+  cpu.cpustatus = FLAG_CONSTANT;
+  cpu.pc = read6502(0xFFFC) | (read6502(0xFFFD) << 8);
+  cpu.sp = 0xFD;
+}
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/cpu.h b/MCUME_pico2/pico64/cpu.h
new file mode 100755
index 0000000..5c7f33f
--- /dev/null
+++ b/MCUME_pico2/pico64/cpu.h
@@ -0,0 +1,334 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#ifndef Teensy64_cpu_h_
+#define Teensy64_cpu_h_
+
+//#include <arm_math.h>
+
+
+#define INLINE 			static inline __attribute__((always_inline))
+#define INLINEOP 		static inline __attribute__((always_inline, flatten))
+#define OPCODE			static
+
+#define RAMSIZE 		65536	//Bytes
+
+
+#include "Teensy64.h"
+#include "roms.h"
+#include "patches.h"
+#include "timerutil.h"
+#include "pla.h"
+#include "vic.h"
+#include "keyboard.h"
+#include "cia1.h"
+#include "cia2.h"
+
+
+//#include <reSID.h>
+//extern AudioPlaySID  playSID;
+//extern AudioOutputAnalog audioout;
+
+#define BASE_STACK     0x100
+
+struct tio  {
+	uint32_t gpioa, gpiob, gpioc, gpiod, gpioe;
+}__attribute__((packed, aligned(4)));
+
+struct tcpu {
+  uint32_t exactTimingStartTime;
+  uint8_t exactTiming;
+
+  //6502 CPU registers
+  uint8_t sp, a, x, y, cpustatus;
+  uint8_t penaltyop, penaltyaddr;
+  uint8_t nmi;
+  uint16_t pc;
+
+  //helper variables
+  uint16_t reladdr;
+  uint16_t ea;
+
+  uint16_t lineCyclesAbs; //for debug
+  unsigned ticks;
+  unsigned lineCycles;
+  unsigned long lineStartTime;
+
+  r_rarr_ptr_t plamap_r; //Memory-Mapping read
+  w_rarr_ptr_t plamap_w; //Memory-Mapping write
+  uint8_t _exrom:1, _game:1;
+  uint8_t nmiLine;
+  uint8_t swapJoysticks;
+
+  tvic vic;
+  tcia cia1;
+  tcia cia2;
+
+  union {
+	uint8_t RAM[RAMSIZE];
+	uint16_t RAM16[RAMSIZE/2];
+	uint32_t RAM32[RAMSIZE/4];
+  };
+
+
+
+  uint8_t cartrigeLO[1]; //TODO
+  uint8_t cartrigeHI[1]; //TODO
+
+};
+
+extern struct tio io;
+extern struct tcpu cpu;
+
+void cpu_reset();
+void cpu_nmi();
+void cpu_clearNmi();
+void cpu_clock(int cycles);
+void cpu_setExactTiming();
+void cpu_disableExactTiming();
+
+void cia_clockt(int ticks);
+
+#define CORE_PIN0_PORT	io.gpiob
+#define CORE_PIN1_PORT	io.gpiob
+#define CORE_PIN2_PORT	io.gpiod
+#define CORE_PIN3_PORT	io.gpioa
+#define CORE_PIN4_PORT	io.gpioa
+#define CORE_PIN5_PORT	io.gpiod
+#define CORE_PIN6_PORT	io.gpiod
+#define CORE_PIN7_PORT	io.gpiod
+#define CORE_PIN8_PORT	io.gpiod
+#define CORE_PIN9_PORT	io.gpioc
+#define CORE_PIN10_PORT	io.gpioc
+#define CORE_PIN11_PORT	io.gpioc
+#define CORE_PIN12_PORT	io.gpioc
+#define CORE_PIN13_PORT	io.gpioc
+#define CORE_PIN14_PORT	io.gpiod
+#define CORE_PIN15_PORT	io.gpioc
+#define CORE_PIN16_PORT	io.gpiob
+#define CORE_PIN17_PORT	io.gpiob
+#define CORE_PIN18_PORT	io.gpiob
+#define CORE_PIN19_PORT	io.gpiob
+#define CORE_PIN20_PORT	io.gpiod
+#define CORE_PIN21_PORT	io.gpiod
+#define CORE_PIN22_PORT	io.gpioc
+#define CORE_PIN23_PORT	io.gpioc
+#define CORE_PIN24_PORT	io.gpioe
+#define CORE_PIN25_PORT	io.gpioa
+#define CORE_PIN26_PORT	io.gpioa
+#define CORE_PIN27_PORT	io.gpioa
+#define CORE_PIN28_PORT	io.gpioa
+#define CORE_PIN29_PORT	io.gpiob
+#define CORE_PIN30_PORT	io.gpiob
+#define CORE_PIN31_PORT	io.gpiob
+#define CORE_PIN32_PORT	io.gpiob
+#define CORE_PIN33_PORT	io.gpioe
+#define CORE_PIN34_PORT	io.gpioe
+#define CORE_PIN35_PORT	io.gpioc
+#define CORE_PIN36_PORT	io.gpioc
+#define CORE_PIN37_PORT	io.gpioc
+#define CORE_PIN38_PORT	io.gpioc
+#define CORE_PIN39_PORT	io.gpioa
+#define CORE_PIN40_PORT	io.gpioa
+#define CORE_PIN41_PORT	io.gpioa
+#define CORE_PIN42_PORT	io.gpioa
+#define CORE_PIN43_PORT	io.gpiob
+#define CORE_PIN44_PORT	io.gpiob
+#define CORE_PIN45_PORT	io.gpiob
+#define CORE_PIN46_PORT	io.gpiob
+#define CORE_PIN47_PORT	io.gpiod
+#define CORE_PIN48_PORT	io.gpiod
+#define CORE_PIN49_PORT	io.gpiob
+#define CORE_PIN50_PORT	io.gpiob
+#define CORE_PIN51_PORT	io.gpiod
+#define CORE_PIN52_PORT	io.gpiod
+#define CORE_PIN53_PORT	io.gpiod
+#define CORE_PIN54_PORT	io.gpiod
+#define CORE_PIN55_PORT	io.gpiod
+#define CORE_PIN56_PORT	io.gpioe
+#define CORE_PIN57_PORT	io.gpioe
+#define CORE_PIN58_PORT	io.gpioe
+#define CORE_PIN59_PORT	io.gpioe
+#define CORE_PIN60_PORT	io.gpioe
+#define CORE_PIN61_PORT	io.gpioe
+#define CORE_PIN62_PORT	io.gpioe
+#define CORE_PIN63_PORT	io.gpioe
+
+static inline uint8_t gpioRead(uint8_t pin) __attribute__((always_inline, unused));
+static inline uint8_t gpioRead(uint8_t pin)
+{
+	/*
+	if (__builtin_constant_p(pin)) {
+		if (pin == 0) {
+			return (CORE_PIN0_PORT & CORE_PIN0_BITMASK) ? 1 : 0;
+		} else if (pin == 1) {
+			return (CORE_PIN1_PORT & CORE_PIN1_BITMASK) ? 1 : 0;
+		} else if (pin == 2) {
+			return (CORE_PIN2_PORT & CORE_PIN2_BITMASK) ? 1 : 0;
+		} else if (pin == 3) {
+			return (CORE_PIN3_PORT & CORE_PIN3_BITMASK) ? 1 : 0;
+		} else if (pin == 4) {
+			return (CORE_PIN4_PORT & CORE_PIN4_BITMASK) ? 1 : 0;
+		} else if (pin == 5) {
+			return (CORE_PIN5_PORT & CORE_PIN5_BITMASK) ? 1 : 0;
+		} else if (pin == 6) {
+			return (CORE_PIN6_PORT & CORE_PIN6_BITMASK) ? 1 : 0;
+		} else if (pin == 7) {
+			return (CORE_PIN7_PORT & CORE_PIN7_BITMASK) ? 1 : 0;
+		} else if (pin == 8) {
+			return (CORE_PIN8_PORT & CORE_PIN8_BITMASK) ? 1 : 0;
+		} else if (pin == 9) {
+			return (CORE_PIN9_PORT & CORE_PIN9_BITMASK) ? 1 : 0;
+		} else if (pin == 10) {
+			return (CORE_PIN10_PORT & CORE_PIN10_BITMASK) ? 1 : 0;
+		} else if (pin == 11) {
+			return (CORE_PIN11_PORT & CORE_PIN11_BITMASK) ? 1 : 0;
+		} else if (pin == 12) {
+			return (CORE_PIN12_PORT & CORE_PIN12_BITMASK) ? 1 : 0;
+		} else if (pin == 13) {
+			return (CORE_PIN13_PORT & CORE_PIN13_BITMASK) ? 1 : 0;
+		} else if (pin == 14) {
+			return (CORE_PIN14_PORT & CORE_PIN14_BITMASK) ? 1 : 0;
+		} else if (pin == 15) {
+			return (CORE_PIN15_PORT & CORE_PIN15_BITMASK) ? 1 : 0;
+		} else if (pin == 16) {
+			return (CORE_PIN16_PORT & CORE_PIN16_BITMASK) ? 1 : 0;
+		} else if (pin == 17) {
+			return (CORE_PIN17_PORT & CORE_PIN17_BITMASK) ? 1 : 0;
+		} else if (pin == 18) {
+			return (CORE_PIN18_PORT & CORE_PIN18_BITMASK) ? 1 : 0;
+		} else if (pin == 19) {
+			return (CORE_PIN19_PORT & CORE_PIN19_BITMASK) ? 1 : 0;
+		} else if (pin == 20) {
+			return (CORE_PIN20_PORT & CORE_PIN20_BITMASK) ? 1 : 0;
+		} else if (pin == 21) {
+			return (CORE_PIN21_PORT & CORE_PIN21_BITMASK) ? 1 : 0;
+		} else if (pin == 22) {
+			return (CORE_PIN22_PORT & CORE_PIN22_BITMASK) ? 1 : 0;
+		} else if (pin == 23) {
+			return (CORE_PIN23_PORT & CORE_PIN23_BITMASK) ? 1 : 0;
+		} else if (pin == 24) {
+			return (CORE_PIN24_PORT & CORE_PIN24_BITMASK) ? 1 : 0;
+		} else if (pin == 25) {
+			return (CORE_PIN25_PORT & CORE_PIN25_BITMASK) ? 1 : 0;
+		} else if (pin == 26) {
+			return (CORE_PIN26_PORT & CORE_PIN26_BITMASK) ? 1 : 0;
+		} else if (pin == 27) {
+			return (CORE_PIN27_PORT & CORE_PIN27_BITMASK) ? 1 : 0;
+		} else if (pin == 28) {
+			return (CORE_PIN28_PORT & CORE_PIN28_BITMASK) ? 1 : 0;
+		} else if (pin == 29) {
+			return (CORE_PIN29_PORT & CORE_PIN29_BITMASK) ? 1 : 0;
+		} else if (pin == 30) {
+			return (CORE_PIN30_PORT & CORE_PIN30_BITMASK) ? 1 : 0;
+		} else if (pin == 31) {
+			return (CORE_PIN31_PORT & CORE_PIN31_BITMASK) ? 1 : 0;
+		} else if (pin == 32) {
+			return (CORE_PIN32_PORT & CORE_PIN32_BITMASK) ? 1 : 0;
+		} else if (pin == 33) {
+			return (CORE_PIN33_PORT & CORE_PIN33_BITMASK) ? 1 : 0;
+		} else if (pin == 34) {
+			return (CORE_PIN34_PORT & CORE_PIN34_BITMASK) ? 1 : 0;
+		} else if (pin == 35) {
+			return (CORE_PIN35_PORT & CORE_PIN35_BITMASK) ? 1 : 0;
+		} else if (pin == 36) {
+			return (CORE_PIN36_PORT & CORE_PIN36_BITMASK) ? 1 : 0;
+		} else if (pin == 37) {
+			return (CORE_PIN37_PORT & CORE_PIN37_BITMASK) ? 1 : 0;
+		} else if (pin == 38) {
+			return (CORE_PIN38_PORT & CORE_PIN38_BITMASK) ? 1 : 0;
+		} else if (pin == 39) {
+			return (CORE_PIN39_PORT & CORE_PIN39_BITMASK) ? 1 : 0;
+		} else if (pin == 40) {
+			return (CORE_PIN40_PORT & CORE_PIN40_BITMASK) ? 1 : 0;
+		} else if (pin == 41) {
+			return (CORE_PIN41_PORT & CORE_PIN41_BITMASK) ? 1 : 0;
+		} else if (pin == 42) {
+			return (CORE_PIN42_PORT & CORE_PIN42_BITMASK) ? 1 : 0;
+		} else if (pin == 43) {
+			return (CORE_PIN43_PORT & CORE_PIN43_BITMASK) ? 1 : 0;
+		} else if (pin == 44) {
+			return (CORE_PIN44_PORT & CORE_PIN44_BITMASK) ? 1 : 0;
+		} else if (pin == 45) {
+			return (CORE_PIN45_PORT & CORE_PIN45_BITMASK) ? 1 : 0;
+		} else if (pin == 46) {
+			return (CORE_PIN46_PORT & CORE_PIN46_BITMASK) ? 1 : 0;
+		} else if (pin == 47) {
+			return (CORE_PIN47_PORT & CORE_PIN47_BITMASK) ? 1 : 0;
+		} else if (pin == 48) {
+			return (CORE_PIN48_PORT & CORE_PIN48_BITMASK) ? 1 : 0;
+		} else if (pin == 49) {
+			return (CORE_PIN49_PORT & CORE_PIN49_BITMASK) ? 1 : 0;
+		} else if (pin == 50) {
+			return (CORE_PIN50_PORT & CORE_PIN50_BITMASK) ? 1 : 0;
+		} else if (pin == 51) {
+			return (CORE_PIN51_PORT & CORE_PIN51_BITMASK) ? 1 : 0;
+		} else if (pin == 52) {
+			return (CORE_PIN52_PORT & CORE_PIN52_BITMASK) ? 1 : 0;
+		} else if (pin == 53) {
+			return (CORE_PIN53_PORT & CORE_PIN53_BITMASK) ? 1 : 0;
+		} else if (pin == 54) {
+			return (CORE_PIN54_PORT & CORE_PIN54_BITMASK) ? 1 : 0;
+		} else if (pin == 55) {
+			return (CORE_PIN55_PORT & CORE_PIN55_BITMASK) ? 1 : 0;
+		} else if (pin == 56) {
+			return (CORE_PIN56_PORT & CORE_PIN56_BITMASK) ? 1 : 0;
+		} else if (pin == 57) {
+			return (CORE_PIN57_PORT & CORE_PIN57_BITMASK) ? 1 : 0;
+		} else if (pin == 58) {
+			return (CORE_PIN58_PORT & CORE_PIN58_BITMASK) ? 1 : 0;
+		} else if (pin == 59) {
+			return (CORE_PIN59_PORT & CORE_PIN59_BITMASK) ? 1 : 0;
+		} else if (pin == 60) {
+			return (CORE_PIN60_PORT & CORE_PIN60_BITMASK) ? 1 : 0;
+		} else if (pin == 61) {
+			return (CORE_PIN61_PORT & CORE_PIN61_BITMASK) ? 1 : 0;
+		} else if (pin == 62) {
+			return (CORE_PIN62_PORT & CORE_PIN62_BITMASK) ? 1 : 0;
+		} else if (pin == 63) {
+			return (CORE_PIN63_PORT & CORE_PIN63_BITMASK) ? 1 : 0;
+		} else {
+			return 0;
+		}
+	} else {
+		Serial.println("Warning: Pin# not constant");
+		return digitalRead(pin);
+	}
+	*/
+	return 0;
+
+}
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/emucfg.h b/MCUME_pico2/pico64/emucfg.h
new file mode 100644
index 0000000..5829db2
--- /dev/null
+++ b/MCUME_pico2/pico64/emucfg.h
@@ -0,0 +1,94 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    C64 Emulator "
+#define ROMSDIR "c64"
+
+#define emu_Init(ROM) {c64_Start(ROM); c64_Init(); }
+#define emu_Step(x) { c64_Step(); }
+#define emu_Input(x) { c64_Input(x); }
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  '1','2','3','4','5','6','7','8','9','0',
+  'Q','W','E','R','T','Y','U','I','O','P',
+  'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M',0,' ',
+  0,0,0,0,150,152 // L R
+  };  
+
+const unsigned short key_map2[] = {
+  '!','@','#','$','%','&','\'','(',')','_',
+  0,0,0,'<','>',0,0,0,';','"',
+  0,0,0,0,0,'^','-','+','=',0x0D,
+  0,':',0,'?','\/','*',',','.',0,' ',
+  153,151,150,152, //U L R D
+  };  
+
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0, // function keys
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  153,151,150,152, //U L R D
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  'Q','W','E','R','T','Y','U','I','O','P',157,
+  0,'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M','.',' ',
+  0,0,0,0
+  };  
+
+#define keylables_map2_0 (char *)"1234567890 "
+#define keylables_map2_1 (char *)" !@#$%+&*- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  '1','2','3','4','5','6','7','8','9','0',0,
+  0, '!','@','#','$','%','+','&','*','-','\/',
+  0, '(',')','?','\/','"','<','>',',',':',
+  145,157,29,17 //U L R D
+  };  
+
+#define keylables_map3_0 (char *)"\x11\x12\x13\x14\x15\x16\x17\x18   "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"        ;= "
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,';','=',
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico64/keyboard.h b/MCUME_pico2/pico64/keyboard.h
new file mode 100755
index 0000000..2c13ef3
--- /dev/null
+++ b/MCUME_pico2/pico64/keyboard.h
@@ -0,0 +1,49 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#ifndef Teensy64_keyboard_h_
+#define Teensy64_keyboard_h_
+
+void initKeyboard();
+void initJoysticks();
+
+void sendKey(char key);
+void sendString(const char * p);
+void do_sendString();//call in yield()
+
+uint8_t cia1PORTA(void);
+uint8_t cia1PORTB(void);
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/keyboard_osd.h b/MCUME_pico2/pico64/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/pico64/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/pico64/output_dac.h b/MCUME_pico2/pico64/output_dac.h
new file mode 100644
index 0000000..d868f94
--- /dev/null
+++ b/MCUME_pico2/pico64/output_dac.h
@@ -0,0 +1,52 @@
+/* Audio Library for Teensy 3.X
+ * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
+ *
+ * Development of this audio library was funded by PJRC.COM, LLC by sales of
+ * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
+ * open source software by purchasing Teensy or other PJRC products.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice, development funding notice, and this permission
+ * notice shall be included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef output_dac_h_
+#define output_dac_h_
+
+#include "reSID.h"
+extern AudioPlaySID playSID;
+
+
+class AudioOutputAnalog
+{
+public:
+	//AudioOutputAnalog(void) : AudioStream(1, inputQueueArray) { begin(); }
+	virtual void update(void);
+	void begin(void);
+	void analogReference(int ref);
+	//static DMAChannel dma;
+//private:
+	//static audio_block_t *block_left_1st;
+	//static audio_block_t *block_left_2nd;
+	static bool update_responsibility;
+	//audio_block_t *inputQueueArray[1];
+	static void isr(void);
+	static uint8_t volume;
+
+};
+
+#endif
diff --git a/MCUME_pico2/pico64/patches.cpp b/MCUME_pico2/pico64/patches.cpp
new file mode 100644
index 0000000..7079e5d
--- /dev/null
+++ b/MCUME_pico2/pico64/patches.cpp
@@ -0,0 +1,300 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#include "patches.h"
+#include "emuapi.h"
+#include "platform_config.h"
+
+
+#define DIRECTORY ROMSDIR + "/\0"
+
+static char filename[64];
+static char buffer[2];
+
+extern char * menuSelection(void);
+
+void patchLOAD(void) {
+
+int device;
+int secondaryAddress;
+uint16_t addr,size;
+
+	device = cpu.RAM[0xBA];
+	if (device != 1) {
+		//Jump to unpatched original address:
+		cpu.pc = rom_kernal[cpu.pc - 0xe000 + 1] * 256 + rom_kernal[cpu.pc - 0xe000];
+		return;
+	};
+
+
+#if XXX
+	if (cpu.RAM[cpu.RAM[0xBC] * 256 + cpu.RAM[0xBB]] == '$' && cpu.RAM[0xB7] == 1) {
+		//Directoy listing with LOAD "$"
+		printf("Listing of ");
+		printf(DIRECTORY);
+		printf("\n");
+		file = SD.open(DIRECTORY);
+		int blocks, start, len;
+		addr = cpu.RAM[0x2C] * 256 + cpu.RAM[0x2B];
+
+		/*first line of BASIC listing */
+		start = addr;
+		cpu.RAM[addr++] = (start + 30) & 0xff;
+		cpu.RAM[addr++] = (start + 30) >> 8;
+		blocks = 0;
+		cpu.RAM[addr++] = blocks & 0xff;
+		cpu.RAM[addr++] = blocks >> 8;
+
+		const char title[] = "\x12\"TEENSY64        \" FB " VERSION;
+		strcpy((char * )&cpu.RAM[addr], title);
+		addr = start + 30;
+
+		while (true) {
+			entry = file.openNextFile();
+			if (! entry) {
+				// no more files
+				break;
+			}
+			int offset;
+			if (!entry.isDirectory()) {
+
+				/* Listing to BASIC-RAM */
+				start = addr;
+				offset = 0;
+
+				//pointer to next line:
+				cpu.RAM[addr++] = (start + 32) & 0xff;
+				cpu.RAM[addr++] = (start + 32) >> 8;
+
+				//# of blocks
+				blocks = ceil((float)entry.size()/256.0f);
+				cpu.RAM[addr++] = blocks & 0xff;
+				cpu.RAM[addr++] = blocks >> 8;
+
+				if (blocks < 100)   { cpu.RAM[addr++] = ' '; offset++;}
+				if (blocks < 10)    { cpu.RAM[addr++] = ' '; offset++; }
+			 	cpu.RAM[addr++] = ' ';
+
+				//filename:
+				cpu.RAM[addr++] = '"';
+				char *s = (char * )&cpu.RAM[addr];
+				entry.getName(s, 17);
+				while(*s) {*s = toupper(*s); s++;}
+				//strcpy((char * )&cpu.RAM[addr], entry.name());
+				len = strlen((char * )&cpu.RAM[addr]);
+
+				if (len > 16) len = 16;
+				addr += len;
+				cpu.RAM[addr++] = '"';
+
+				//fill with space
+				while ((addr-start) < (32)) { cpu.RAM[addr++] = ' ';}
+
+				//display "PRG"
+				addr = start + 23 + offset;
+				cpu.RAM[addr++] = ' ';
+				cpu.RAM[addr++] = 'P';
+				cpu.RAM[addr++] = 'R';
+				cpu.RAM[addr++] = 'G';
+
+				//line-ending
+				cpu.RAM[start+31] = 0;
+				addr = start + 32;
+
+				/* Listing to serial console */
+				itoa (blocks,filename,10);
+				len = strlen(filename);
+				while (len < 4) { strcat(filename," "); len++; };
+				strcat(filename, "\"");
+				char nbuf[18] = {0};
+				entry.getName(nbuf, 17);
+				strcat(filename, nbuf);
+				//strcat(filename, entry.getName());
+				strcat(filename, "\"");
+				len = strlen(filename);
+				while (len < 18+4) { strcat(filename," "); len++; };
+				strcat(filename," PRG   ");
+				//printf(filename);
+
+			}
+			entry.close();
+		}
+		file.close();
+
+        /*add last line to BASIC listing*/
+		start = addr;
+		cpu.RAM[addr++] = (start + 32) & 0xff;
+		cpu.RAM[addr++] = (start + 32) >> 8;
+		//# of blocks. todo : determine free space on sd card
+		blocks = 65535;
+		cpu.RAM[addr++] = blocks & 0xff;
+		cpu.RAM[addr++] = blocks >> 8;
+		if (blocks < 100) { cpu.RAM[addr++] = ' ';}
+		if (blocks < 10)  { cpu.RAM[addr++] = ' ';}
+		const char blockfree[] = "BLOCKS FREE.";
+
+		strcpy((char * )&cpu.RAM[addr], blockfree);
+		len = strlen(blockfree);
+		addr += len;
+		while ((addr-start) < (32)) { cpu.RAM[addr++] = ' ';}
+		cpu.RAM[start+31] = 0;
+		cpu.RAM[start+32] = 0;
+		cpu.RAM[start+33] = 0;
+
+		cpu.y = 0x49; //Offset for "LOADING"
+		cpu.pc = 0xF12B; //Print and return
+		return;
+	} // end directory listing
+#endif
+
+	//$B7    : Length of file name or disk command
+	//$BB-$BC: Pointer to current file name or disk command
+  memset(filename,0,sizeof(filename));
+  if ( cpu.RAM[0xB7] == 0) {
+	strcpy(filename,menuSelection());
+  }
+  else {
+	strncpy(filename, (char*)&cpu.RAM[cpu.RAM[0xBC] * 256 + cpu.RAM[0xBB]], cpu.RAM[0xB7] );
+  }     
+	secondaryAddress = cpu.RAM[0xB9];
+
+  //Serial.println("loading");
+	//printf("%s,%d,%d:", filename, device, secondaryAddress);
+#ifdef EXTERNAL_SD  
+  tft.stopDMA();
+  //emu_resetSD();
+  tft.fillScreenNoDma( RGBVAL16(0x00,0x00,0x00) );
+#endif  
+	if (emu_FileOpen(filename, "r+b") == 0) {
+		//Serial.println("not found");
+		cpu.pc = 0xf530; //Jump to $F530
+#ifdef EXTERNAL_SD  
+    tft.startDMA(); 
+#endif  
+		return;
+	}
+
+	size = emu_FileSize(filename);
+	int f = emu_FileOpen(filename, "r+b");
+	emu_FileRead(buffer, 2, f);
+	addr = buffer[1] * 256 + buffer[0];
+	emu_FileRead((char*)&cpu.RAM[addr], size - 2, f);
+	emu_FileClose(f);
+
+	cpu.RAM[0xAF] = (addr + size - 2) & 0xff;
+	cpu.RAM[0xAE] = (addr + size - 2) / 256;
+
+	cpu.y = 0x49; //Offset for "LOADING"
+	cpu.pc = 0xF12B; //Print and return
+	emu_printf("loaded");
+#ifdef EXTERNAL_SD  
+  tft.startDMA(); 
+#endif
+	return;
+}
+
+void patchSAVE(void) {
+#ifdef XXX
+int device;
+int secondaryAddress;
+uint16_t addr,size;
+
+	//Serial.println("Patched SAVE");
+	device = cpu.RAM[0xBA];
+	if (device != 1) {
+		//Jump to unpatched original address:
+		cpu.pc = rom_kernal[cpu.pc - 0xe000 + 1] * 256 + rom_kernal[cpu.pc - 0xe000];
+		return;
+	};
+
+	if (!SDinitialized) {
+		cpu.pc = 0xF707; //Device not present error
+		//Serial.println("SD Card not initialized");
+		return;
+	}
+
+	if( !SD.exists(DIRECTORY) && SD.mkdir(DIRECTORY) ) {
+		cpu.pc = 0xF707; //Device not present error
+		//Serial.println("SD: Could not create " DIRECTORY);
+	}
+
+	//$B7    : Length of file name or disk command
+	//$BB-$BC: Pointer to current file name or disk command
+	memset(filename,0,sizeof(filename));
+	strcpy(filename, DIRECTORY);
+	strncat(filename, (char*)&cpu.RAM[cpu.RAM[0xBC] * 256 + cpu.RAM[0xBB]], cpu.RAM[0xB7] );
+
+	secondaryAddress = cpu.RAM[0xB9];
+
+	//Serial.print(filename);
+	//Serial.print(",");
+	//Serial.print(device);
+	//Serial.print(",");
+	//Serial.print(secondaryAddress);
+	//Serial.print(":");
+
+	addr = cpu.RAM[cpu.a + 1] * 256 + cpu.RAM[cpu.a];
+	size = (cpu.y * 256 + cpu.x) - addr;
+
+	buffer[0] = addr & 0xff;
+	buffer[1] = addr >> 8;
+
+	if (SD.exists(filename)) SD.remove(filename);
+	file = SD.open(filename, FILE_WRITE);
+	if (!file) {
+		//Serial.println ("not possible.");
+		cpu.pc = 0xf530; //Jump to $F530
+		return;
+	}
+	file.write(buffer, 2);
+	file.write(&cpu.RAM[addr], size);
+	file.close();
+
+	if (cpu.RAM[0x9D] & 128) {
+		uint16_t pushval = 0xF68D;
+		cpu.RAM[BASE_STACK + cpu.sp] = (pushval >> 8) & 0xFF;
+		cpu.RAM[BASE_STACK + ((cpu.sp - 1) & 0xFF)] = pushval & 0xFF;
+		cpu.sp -= 2;
+
+		cpu.y = 0x51;
+		cpu.pc = 0xF12F;
+	} else {
+		cpu.pc = 0xF68D;
+	}
+
+	//Serial.println("saved.");
+	return;
+#endif	
+}
diff --git a/MCUME_pico2/pico64/patches.h b/MCUME_pico2/pico64/patches.h
new file mode 100755
index 0000000..34a1646
--- /dev/null
+++ b/MCUME_pico2/pico64/patches.h
@@ -0,0 +1,44 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+#ifndef Teensy64_patches_h_
+#define Teensy64_patches_h_
+
+#include "cpu.h"
+#include "roms.h"
+
+void patchLOAD(void);
+void patchSAVE(void);
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/pico64.cpp b/MCUME_pico2/pico64/pico64.cpp
new file mode 100644
index 0000000..1c26af6
--- /dev/null
+++ b/MCUME_pico2/pico64/pico64.cpp
@@ -0,0 +1,175 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+#include "c64.h"
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);     
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        //uint16_t bClick = emu_DebounceLocalKeys();
+        //emu_Input(bClick);  
+        emu_Step();        
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+#ifdef USE_VGA   
+    //tft.waitSync();                   
+#else 
+    //volatile bool vb=vbl;
+    //while (vbl==vb) {};
+#endif
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
diff --git a/MCUME_pico2/pico64/pla.cpp b/MCUME_pico2/pico64/pla.cpp
new file mode 100644
index 0000000..7e1a970
--- /dev/null
+++ b/MCUME_pico2/pico64/pla.cpp
@@ -0,0 +1,1114 @@
+/*
+	Copyright Frank Bösing, 2017	
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+		
+*/
+
+#include <string.h>
+#include "roms.h"
+#include "cpu.h"
+
+#include "pla.h"
+#include "vic.h"
+#include "cia1.h"
+#include "cia2.h"
+
+
+extern CONSTROM rarray_t PLA_READ[8];
+extern CONSTROM warray_t PLA_WRITE[8];
+
+uint8_t r_ram(uint32_t address)		{ return cpu.RAM[address]; }
+uint8_t r_bas(uint32_t address)		{ return rom_basic[address & (sizeof(rom_basic)-1)]; } //BASIC ROM
+uint8_t r_ker(uint32_t address)		{ return rom_kernal[address & (sizeof(rom_kernal)-1)]; } //KERNAL ROM
+uint8_t r_chr(uint32_t address)		{ return rom_characters[address & (sizeof(rom_characters)-1)]; } //CHARACTER ROM
+uint8_t r_vic(uint32_t address)		{ return vic_read(address); }
+#ifdef HAS_SND      
+uint8_t r_sid(uint32_t address)		{ return playSID.getreg(address & 0x1F);}
+#else
+uint8_t r_sid(uint32_t address)		{ return 0;}
+#endif
+uint8_t r_col(uint32_t address)		{ return cpu.vic.COLORRAM[address & 0x3FF]; }
+uint8_t r_cia1(uint32_t address)	{ return cia1_read(address); }
+uint8_t r_cia2(uint32_t address)	{ return cia2_read(address); }
+uint8_t r_crtL(uint32_t address)	{ return cpu.cartrigeLO[address & 0x1fff]; } //Cartrige Low ($8000) 
+uint8_t r_crtH(uint32_t address)	{ return cpu.cartrigeHI[address & 0x1fff]; } 
+uint8_t r_nul(uint32_t address)		{ return 0;} //No RAM for Ultimax-cartrige
+uint8_t r_rnd(uint32_t address)		{ return 255;} //Random for $DE00-$DFFF
+
+void w_ram( uint32_t address, uint8_t value )	{ 
+    cpu.RAM[address ]=value; 
+}
+void w_ramz( uint32_t address, uint8_t value )	{ 
+	cpu.RAM[address]=value;  //zeropage
+	if (address==1) {	//6510 Port
+		value &= 0x07;
+		cpu.plamap_r = (rarray_t*)&PLA_READ[value];
+		cpu.plamap_w = (warray_t*)&PLA_WRITE[value];
+	  } 
+	} 
+void w_vic( uint32_t address, uint8_t value )	{ vic_write(address, value); }
+void w_col( uint32_t address, uint8_t value )	{ cpu.vic.COLORRAM[address & 0x3FF] = value & 0x0F;}
+#ifdef HAS_SND      
+void w_sid( uint32_t address, uint8_t value )	{ playSID.setreg(address & 0x1F, value); }
+#else
+void w_sid( uint32_t address, uint8_t value )	{ }
+#endif
+void w_cia1( uint32_t address, uint8_t value )	{ cia1_write(address, value); }
+void w_cia2( uint32_t address, uint8_t value )	{ cia2_write(address, value); }
+
+/*
+    LORAM (bit 0) can generally be thought of as a control line which banks
+  the 8K byte BASIC ROM in and out of the microprocessor address space.
+  Normally, this line is HIGH for BASIC operation. If this line is
+  programmed LOW, the BASIC ROM will disappear from the memory map and be
+  replaced by 8K bytes of RAM from $A000-$BFFF.
+
+    HIRAM (bit 1) can generally be thought of as a control line which banks
+  the 8K byte KERNAL ROM in and out of the microprocessor address space.
+  Normally, this line is HIGH for BASIC operation. If this line is
+  programmed LOW, the KERNAL ROM will disappear from the memory map and be
+  replaced by 8K bytes of RAM from $E000-$FFFF.
+
+    CHAREN (bit 2) is used only to bank the 4K byte character generator ROM
+  in or out of the microprocessor address space. From the processor point
+  of view, the character ROM occupies the same address space as the I/O
+  devices ($D000-$DFFF). When the CHAREN line is set to 1 (as is normal),
+  the I/O devices appear in the microprocessor address space, and the
+  character ROM is not accessable. When the CHAREN bit is cleared to 0, the
+  character ROM appears in the processor address space, and the I/O devices
+  are not accessible. (The microprocessor only needs to access the
+  character ROM when downloading the character set from ROM to RAM. Special
+  care is needed for this... see the section on PROGRAMMABLE CHARACTERS in
+  the GRAPHICS chapter). CHAREN can be overridden by other control lines in
+  certain memory configurations. CHAREN will have no effect on any memory
+  configuration without I/O devices. RAM will appear from $D000-$DFFF
+  instead.
+  */
+  
+  /*  
+       Bit+-------------+-----------+------------+
+       210| $8000-$BFFF |$D000-$DFFF|$E000-$FFFF |
+  +---+---+-------------+-----------+------------+
+  | 7 |111| Cart.+Basic |    I/O    | Kernal ROM |
+  +---+---+-------------+-----------+------------+
+  | 6 |110|     RAM     |    I/O    | Kernal ROM |
+  +---+---+-------------+-----------+------------+
+  | 5 |101|     RAM     |    I/O    |    RAM     |
+  +---+---+-------------+-----------+------------+
+  | 4 |100|     RAM     |    RAM    |    RAM     |
+  +---+---+-------------+-----------+------------+
+  | 3 |011| Cart.+Basic | Char. ROM | Kernal ROM |
+  +---+---+-------------+-----------+------------+
+  | 2 |010|     RAM     | Char. ROM | Kernal ROM |
+  +---+---+-------------+-----------+------------+
+  | 1 |001|     RAM     | Char. ROM |    RAM     |
+  +---+---+-------------+-----------+------------+
+  | 0 |000|     RAM     |    RAM    |    RAM     |
+  +---+---+-------------+-----------+------------+
+       |||
+ /CharEn|/LoRam
+        |
+      /HiRam
+ */	  
+
+CONSTROM 
+rarray_t PLA_READ[8] = {
+	//charen hiram loram
+	/* 000 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 001 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	
+    /* A0 */ //  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */ //  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 010 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 011 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 100 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 101 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+		
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 110 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 111 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker}
+};
+
+CONSTROM 
+warray_t PLA_WRITE[8] = {
+	/* 000 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram},
+	
+	/* 001 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram},	
+	
+	/* 010 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+    /* D0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,},	
+	
+	/* 011 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+    /* D0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,		
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,},	
+	
+	/* 100 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram},	
+	
+	/* 101 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_vic,  w_vic,  w_vic,  w_vic,  w_sid,  w_sid,  w_sid,  w_sid,  w_col,  w_col,  w_col,  w_col,  w_cia1, w_cia2, w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram},	
+	
+	/* 110 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_vic,  w_vic,  w_vic,  w_vic,  w_sid,  w_sid,  w_sid,  w_sid,  w_col,  w_col,  w_col,  w_col,  w_cia1, w_cia2, w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram},	
+	
+	/* 111 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {w_ramz, w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 10 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 20 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 30 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 40 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 50 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 60 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 70 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* 80 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* 90 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* A0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* B0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+
+	/* C0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* D0 */   w_vic,  w_vic,  w_vic,  w_vic,  w_sid,  w_sid,  w_sid,  w_sid,  w_col,  w_col,  w_col,  w_col,  w_cia1, w_cia2, w_ram,  w_ram,
+	/* E0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,
+	/* F0 */   w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram,  w_ram}	
+};
+
+/*
+Normal   8kB cartridge at $8000       (ROML):      GAME = 1, EXROM = 0
+Normal  16kB cartridge at $8000/$a000 (ROML,ROMH): GAME = 0, EXROM = 0
+Ultimax 16kB cartridge at $8000/$e000 (ROML,ROMH): GAME = 0, EXROM = 1
+*/
+
+CONSTROM 
+rarray_t PLA_READ_CARTRIGE_10[8] = { 
+	
+	//Normal   8kB cartridge at $8000       (ROML):      GAME = 1, EXROM = 0
+		
+	//charen hiram loram
+	/* 000 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 001 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 010 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 011 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 100 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 101 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 110 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 111 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker}
+};
+
+CONSTROM 
+rarray_t PLA_READ_CARTRIGE_00[8] = { //GAME = 0 EXROM = 0
+
+	//Normal  16kB cartridge at $8000/$a000 (ROML,ROMH): GAME = 0, EXROM = 0
+	
+	//charen hiram loram
+	/* 000 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 001 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 010 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* B0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 011 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* B0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  r_chr,  	//chr
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 100 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* B0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 101 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+	/* B0 */   r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,  r_bas,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* F0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram},
+
+	/* 110 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 90 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* A0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* B0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker},
+
+	/* 111 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 20 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 30 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 40 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 50 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 60 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 70 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* B0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+
+	/* C0 */   r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_ram,  r_ram,
+	/* E0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,
+	/* F0 */   r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker,  r_ker}
+};
+
+CONSTROM 
+rarray_t PLA_READ_CARTRIGE_01[8] = { 
+	
+	//Ultimax 16kB cartridge at $8000/$e000 (ROML,ROMH): GAME = 0, EXROM = 1
+		
+	//charen hiram loram
+	/* 000 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 001 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 010 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 011 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 100 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 101 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 110 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+
+	/* 111 */
+	/*        	0   	1   	2   	3   	4   	5   	6   	7   	8	   9   		A   	B   	C   	D   	E   	F*/
+	/* 00 */  {r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,  r_ram,
+	/* 10 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 20 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 30 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 40 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 50 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 60 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* 70 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* 80 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* 90 */   r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL, r_crtL,
+	/* A0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* B0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+
+	/* C0 */   r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,  r_nul,
+	/* D0 */   r_vic,  r_vic,  r_vic,  r_vic,  r_sid,  r_sid,  r_sid,  r_sid,  r_col,  r_col,  r_col,  r_col,  r_cia1, r_cia2, r_nul/*?*/,  r_nul/*?*/,
+	/* E0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH,
+	/* F0 */   r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH, r_crtH},
+};
+
+
+
+void resetPLA(void) {
+	
+	// Initialize RAM
+	unsigned i = 0;
+	const char pattern1 = 0x00;
+	const char pattern2 = 0xff;
+	const char patternLength = 0x40;
+	
+	while (i <= (sizeof(cpu.RAM) - patternLength * 2)) {
+		memset(&cpu.RAM[i], pattern1, patternLength);
+		i += patternLength;
+		memset(&cpu.RAM[i], pattern2, patternLength);
+		i += patternLength;
+	};
+
+	cpu.RAM[0] = 0x2F;
+	cpu.RAM[1] = 0x1F;	
+
+/* Cartriges : 
+Normal   8kB cartridge at $8000       (ROML):      GAME = 1, EXROM = 0
+Normal  16kB cartridge at $8000/$a000 (ROML,ROMH): GAME = 0, EXROM = 0
+Ultimax 16kB cartridge at $8000/$e000 (ROML,ROMH): GAME = 0, EXROM = 1
+*/
+#if 1 //No Cartrige
+    cpu._game = 1;
+	cpu._exrom = 1;
+#else //TODO...
+    cpu._game = 0;
+	cpu._exrom = 0;	
+#endif	
+
+	if (cpu._game == 1 && cpu._exrom==0) {
+		cpu.plamap_r = (rarray_t*)&PLA_READ_CARTRIGE_10[0x07];
+		cpu.plamap_w = (warray_t*)&PLA_WRITE[0x07];		
+	}
+	else 
+	if (cpu._game == 0 && cpu._exrom==0) {
+		cpu.plamap_r = (rarray_t*)&PLA_READ_CARTRIGE_00[0x07];
+		cpu.plamap_w = (warray_t*)&PLA_WRITE[0x07];		
+	}
+	else 
+	if (cpu._game == 0 && cpu._exrom==1) {
+		cpu.plamap_r = (rarray_t*)&PLA_READ_CARTRIGE_00[0x07];
+		cpu.plamap_w = (warray_t*)&PLA_WRITE[0x07];		
+	}	
+	else { //C64 without Cartridge
+		cpu.plamap_r = (rarray_t*)&PLA_READ[0x07];
+		cpu.plamap_w = (warray_t*)&PLA_WRITE[0x07];
+	}
+}
diff --git a/MCUME_pico2/pico64/pla.h b/MCUME_pico2/pico64/pla.h
new file mode 100755
index 0000000..2355787
--- /dev/null
+++ b/MCUME_pico2/pico64/pla.h
@@ -0,0 +1,66 @@
+/*
+Copyright Frank Bösing, 2017  
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+    
+*/
+
+#ifndef Teensy64_pla_h_
+#define Teensy64_pla_h_
+
+#define CONSTROM const
+
+#define MEM_BASIC_ROM 0xA000
+#define MEM_CHARSET_ROM 0xD000
+#define MEM_KERNAL_ROM  0xE000
+
+#define MEM_VIC     0xD000
+#define MEM_VICCOLOR  0xD800
+#define MEM_SID     0xD400
+#define MEM_CIA1    0xDC00
+#define MEM_CIA2    0xDD00
+
+//C64 Memory/Device access (PLA)
+
+/* READ */
+typedef uint8_t (*r_ptr_t)( uint32_t address ); //Funktionspointer auf uint8_t foo(uint16_t address);
+typedef r_ptr_t rarray_t[256];          //Array von Funktionspointern
+typedef rarray_t * r_rarr_ptr_t;        //Pointer auf Array von Funktionspointern
+
+/* WRITE */
+typedef void (*w_ptr_t)( uint32_t address, uint8_t value ); //Funktionspointer auf void foo( uint16_t address, uint8_t value );
+typedef w_ptr_t warray_t[256];                //Array von Funktionspointern
+typedef warray_t * w_rarr_ptr_t;              //Pointer auf Array von Funktionspointern
+
+
+void resetPLA(void);
+
+#endif
diff --git a/MCUME_pico2/pico64/program_config.h b/MCUME_pico2/pico64/program_config.h
new file mode 100644
index 0000000..91f04b3
--- /dev/null
+++ b/MCUME_pico2/pico64/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/pico64/reSID.cpp b/MCUME_pico2/pico64/reSID.cpp
new file mode 100644
index 0000000..59e71bd
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID.cpp
@@ -0,0 +1,58 @@
+/*
+	Arduino SID
+	Copyright (c) 2015 Frank Bösing
+	This library is free software: you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 3 of the License, or
+	(at your option) any later version.
+	This library is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+	You should have received a copy of the GNU General Public License
+	along with this library.  If not, see <http://www.gnu.org/licenses/>.
+	
+	Diese Bibliothek ist freie Software: Sie können es unter den Bedingungen
+	der GNU General Public License, wie von der Free Software Foundation,
+	Version 3 der Lizenz oder (nach Ihrer Wahl) jeder neueren
+	veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+	Diese Bibliothek wird in der Hoffnung, dass es nützlich sein wird, aber
+	OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+	Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+	Siehe die GNU General Public License für weitere Details.
+	Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+	Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+ */
+#include "reSID.h"
+#include <math.h>
+
+#define CLOCKFREQ 985248
+
+void AudioPlaySID::begin(float samplerate, int blocksize)
+{
+	sidptr = &sid;
+	this->reset();
+	sid.set_sampling_parameters(CLOCKFREQ, SAMPLE_FAST, samplerate); 
+	csdelta = round((float)CLOCKFREQ / ((float)samplerate / blocksize));
+	playing = true;
+}
+
+
+void AudioPlaySID::reset(void)
+{
+	sid.reset();
+}
+
+void AudioPlaySID::stop(void)
+{
+	playing = false;	
+}
+
+void AudioPlaySID::update(float samplerate, void * stream, int len) {
+	// only update if we're playing
+	if (!playing) return;
+
+	cycle_count delta_t = csdelta;
+	sidptr->clock(delta_t, (short int*)stream, len);
+}
diff --git a/MCUME_pico2/pico64/reSID.h b/MCUME_pico2/pico64/reSID.h
new file mode 100644
index 0000000..6f5a607
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID.h
@@ -0,0 +1,53 @@
+/*
+	Arduino SID
+	Copyright (c) 2015 Frank Bösing
+	This library is free software: you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 3 of the License, or
+	(at your option) any later version.
+	This library is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+	You should have received a copy of the GNU General Public License
+	along with this library.  If not, see <http://www.gnu.org/licenses/>.
+
+	Diese Bibliothek ist freie Software: Sie können es unter den Bedingungen
+	der GNU General Public License, wie von der Free Software Foundation,
+	Version 3 der Lizenz oder (nach Ihrer Wahl) jeder neueren
+	veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+	Diese Bibliothek wird in der Hoffnung, dass es nützlich sein wird, aber
+	OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+	Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+	Siehe die GNU General Public License für weitere Details.
+	Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+	Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+ */
+#include "reSID/sid.h"
+#include <stdint.h>
+
+#ifndef play_sid_h_
+#define play_sid_h_
+
+
+class AudioPlaySID
+{
+public:
+	AudioPlaySID(void) {  }
+	void begin(float samplerate, int blocksize);
+	inline void setreg(int ofs, int val) { sid.write(ofs, val); }
+	inline uint8_t getreg(int ofs) { return sid.read(ofs); }
+	void reset(void);
+	void stop(void);
+	void update(float samplerate, void * stream, int len);	
+	inline bool isPlaying(void) { return playing; }	
+private:
+	cycle_count csdelta;	
+	volatile bool playing;
+	SID sid;
+	SID* sidptr;
+};
+
+
+#endif
diff --git a/MCUME_pico2/pico64/reSID/.DS_Store b/MCUME_pico2/pico64/reSID/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/pico64/reSID/.DS_Store differ
diff --git a/MCUME_pico2/pico64/reSID/AUTHORS b/MCUME_pico2/pico64/reSID/AUTHORS
new file mode 100755
index 0000000..d22e33d
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/AUTHORS
@@ -0,0 +1,3 @@
+Authors of reSID.
+
+Dag Lem: Designed and programmed complete emulation engine.
diff --git a/MCUME_pico2/pico64/reSID/COPYING b/MCUME_pico2/pico64/reSID/COPYING
new file mode 100755
index 0000000..d60c31a
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
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+Foundation's software and to any other program whose authors commit to
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+
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+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
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+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
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+
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+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
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+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/MCUME_pico2/pico64/reSID/ChangeLog b/MCUME_pico2/pico64/reSID/ChangeLog
new file mode 100755
index 0000000..1c7aa47
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/ChangeLog
@@ -0,0 +1,313 @@
+2004-06-11  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.16 released.
+
+	* envelope.h (EnvelopeGenerator::clock): Corrected off-by-one
+	error in check for ADSR delay bug in delta_t cycle interface.
+
+	* filter.cc (Filter::set_chip_model): Initialize filter cutoff
+	mappings before call to set_chip_model.
+
+	* sid.cc (SID::set_sampling_parameters): Build shifted FIR tables
+	with samples according to the sampling frequency.
+	(SID::clock_resample_interpolate): New function; factorized linear
+	interpolation out from filter convolutions, and made convolutions
+	vectorizable.
+	(SID::clock_resample_fast): New function; single convolution, same
+	accuracy as with interpolation by using more filter tables.
+	(SID::State, SID::read_state, SID::write_state): Read and write
+	rate_counter_period and exponential_counter_period. Read sustain
+	value.
+
+2003-10-20  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.15 released.
+
+	* envelope.h (EnvelopeGenerator): Added public State enum.
+	(EnvelopeGenerator::clock): Rate counter is 15 bits, count
+	rate_period - 1 after wrapping from 0x8000 to 0 in ADSR delay bug.
+
+	* sid.cc, sid.h (SID::State): Added envelope_state.
+	(SID::State::write_state): Restore register 0x18.
+	(SID::set_sampling_parameters): Scale resampling filter to avoid
+	clipping.
+	(SID::clock_resample): Saturated arithmetics to avoid clipping.
+
+2002-12-31  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.14 released.
+
+	* envelope.h (EnvelopeGenerator::clock): Corrected one cycle error
+	in ADSR delay bug. Only load the exponential counter period at the
+	envelope counter values 255, 93, 54, 26, 14, 6, 0.
+	
+	* filter.cc (Filter::set_chip_model): Call set_w0() and set_Q() to
+	update filter settings.
+	(Filter::set_w0): Limit cutoff frequency for both 1 cycle and
+	delta_t cycle filter.
+
+	* filter.h (Filter::clock): Mix in external audio input.
+
+	* sid.cc, sid.h (SID::input): New function; accepts external audio
+	input sample.
+	
+	* spline.h (PointPlotter::operator ()): Clamp negative values to
+	zero.
+
+	* voice.cc, voice.h: Changed misleading name wave_DC to wave_zero.
+	
+	* wave.h (WaveformGenerator::clock): Corrected bug in check for
+	accumulator bit 19 in noise register shift.
+
+2002-01-19  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.13 released.
+
+	* configure.in: Replaced AC_TRY_COMPILER with AC_TRY_COMPILE,
+	removed AC_PROG_RANLIB.
+
+	* envelope.h (EnvelopeGenerator::clock): Reset rate_step on state
+	change.
+
+	* extfilt.cc (ExternalFilter::set_chip_model): New calculation of
+	maximum mixer DC level.
+
+	* filter.cc (Filter::set_chip_model): Moved calculation of
+	voice_DC to voice.cc, corrected calculation of mixer_DC.
+
+	* filter.h (Filter::output): Mixer output is not inverted.
+
+	* sid.cc (SID::set_chip_model): Call voice.set_chip_model instead
+	of voice.wave.set_chip_model.
+	
+	* voice.cc (Voice::Voice): Call set_chip_model.
+	(Voice::set_chip_model): New function; model both waveform D/A
+	converter and envelope multiplying D/A converter DC offsets.
+	
+	* voice.h (Voice::output): Add both waveform D/A converter and
+	envelope multiplying D/A converter DC offsets.
+	
+	* wave.h (WaveformGenerator::output____): Reverted to output
+	minimum wave level when no waveform is selected. The maximum and
+	minimum wave output levels are interchanged in C= Hacking Issue	#20.
+
+2001-10-20  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.12 released.
+
+	* envelope.cc, envelope.h, filter.cc, filter.h, wave.cc, wave.h:
+	Removed bool usage. This avoids unnecessary conversion to 1/0.
+
+	* filter.cc (Filter::set_chip_model): New function; selects voice
+	and mixer DC offsets and mapping from the FC registers to filter
+	cutoff frequency. The voice and mixer DC offsets for the MOS6581 are
+	calculated from	measurements made by Hársfalvi, Levente in
+	C= Hacking Issue #20.
+	(Filter::Filter): Call set_chip_model.
+	(Filter::f0_6581, Filter::f0_8580): Separate FC mapping tables.
+	(Filter::f0_points_6581, Filter::f0_points_8580): Separate FC mapping
+	points.
+
+	* extfilt.cc, extfilt.h (ExternalFilter::set_chip_model): New
+	function supporting separate DC correction for MOS6581 and MOS8580.
+	
+	* sid.cc, sid.h (SID::adjust_sampling_frequency): New function for
+	on-the-fly adjustment of sampling frequency.
+	(SID::clock_fast): Corrected sample calculation.
+	(SID::set_chip_model): Set filter chip model.
+	(SID::output): Added audio clipping.
+	(SID::clock, SID::clock_fast, SID::clock_interpolate,
+	SID::clock_resample): Added sample interleaving.
+
+	* spline.h (interpolate): Generalized to accept repeated points to
+	introduce points of non-differentiability and discontinuity.
+	
+	* wave.h (WaveformGenerator::output____): No selected waveform
+	yields maximum wave output level. This was found by Hársfalvi,
+	Levente in C= Hacking Issue #20.
+	(WaveformGenerator::clock): Optimized for speed (no division).
+
+2001-03-10  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.11 released.
+
+	* configure.in: Disable building of shared library by default.
+	Control inlining with RESID_INLINING (0 or 1) and RESID_INLINE
+	(blank or "inline").
+
+	* envelope.h, extfilt.h, filter.h, voice.h, wave.h: inline keyword
+	in both function declarations and function definitions.
+
+	* samp2src.pl: Beautified Perl code.
+	
+	* sid.h, sid.cc: Replaced voice variables with array. Removed
+	filter variables from SID::State.
+	(SID::clock): New audio sample generating interface. Three
+	clocking methods are available; clocking at output sample
+	frequency, clocking at cycle frequency with linear sample
+	interpolation, and clocking at cycle frequency with audio
+	resampling.
+	(SID::clock_fast, SID::clock_interpolate, SID::clock_resample):
+	New functions called by SID::clock.
+	(SID::set_sampling_parameters): New function to set up SID for
+	sample generation. The FIR table used in SID::clock_resample is
+	calculated here.
+	(SID::I0): 0th order modified Bessel function to calculate Kaiser
+	window.
+
+	* siddefs.h: Control inlining with RESID_INLINING (0 or 1) and
+	RESID_INLINE (blank or "inline"). Added enum sampling_method.
+	
+	* voice.h, voice.cc (Voice::set_sync_source): Moved setting of
+	sync source from constructor.
+	
+	* wave.h, wave.cc (WaveformGenerator::set_sync_source): Moved
+	setting of sync source from constructor.
+	
+2000-11-22  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.10 released.
+	
+	* configure.in, Makefile.am: Use libtool to build library. The
+	hack to "disable" install is removed.
+
+	* extfilt.h, filter.h: Moved filter stability code from sid.cc.
+
+	* sid.cc (SID::clock): Moved filter stability code to
+	extfilt.h/filter.h. Don't clock the rest of the chip more
+	frequently than necessary.
+
+	* wave.cc: Typecast for pedantic (and probably incorrect)
+	compilers.
+
+2000-05-18  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.9 released.
+	
+	* filter.h (Filter::output): The sum of the filter outputs is no
+	longer weighted.
+	
+1999-06-24  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.8 released.
+
+	* filter.h, filter.cc, wave.h, wave.cc: Typecasts for pedantic
+	compilers.
+
+	* filter.h (Filter::clock): Voice 3 is only silenced by voice3off
+	if it is not routed through the filter.
+	
+	* sid.cc (SID::State): Added constructor for proper initalization.
+
+	* spline.h: Inlined template functions to avoid problems at link
+	time with certain compilers.
+
+1999-02-25  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.7 released.
+
+	* configure.in: Check whether compiler supports bool.
+
+	* extfilt.h, extfilt.cc: Implementation of C64 filter, external to
+	the SID chip.
+
+	* filter.h (Filter::clock): Optimized filter routing using a switch.
+	(Filter::output): Optimized filter mixing using a switch, avoiding
+	integer division. Corrected sign of filtered output, which is
+	inverted compared to unfiltered output.
+	
+	* filter.cc (Filter::set_w0): Removed use of M_PI and math.h
+	functions. Use spline table to map fc to w0.
+	(Filter::fc_default): Return array of FC spline interpolation points.
+	(Filter::fc_plotter): Return FC spline plotter object.
+
+	* sid.h (SID::enable_external_filter): Enable/disable external
+	filter.
+	(SID::fc_default): Return array of FC spline interpolation points.
+	(SID::fc_plotter): Return FC spline plotter object.
+	(SID::State, SID::read_state, SID::write_state): Read and write
+	complete SID state.
+	
+	* sid.cc (SID::clock): Age bus value. Clock external filter.
+	(SID::enable_external_filter): Enable/disable external filter.
+	
+	* spline.h: Spline implementation. Used to specify mapping from
+	the FC register to filter cutoff frequency.
+
+1998-11-14  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.6 released.
+
+	* configure.in: Allow compilation in a separate directory.
+
+	* wave.h (WaveformGenerator::synchronize): Handle special case when a
+	sync source is synced itself on the same cycle as its MSB is set
+	high.
+
+	* sid.cc (SID::clock): Only clock on MSB on/off for hard sync.
+
+1998-09-06  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.5 released.
+
+	* version.cc (resid_version_string): Version string with C linkage.
+	
+	* wave.cc (WaveformGenerator::set_chip_model): Emulation of MOS8580
+	combined waveforms.
+
+1998-08-28  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.4 released.
+
+	* envelope.h (EnvelopeGenerator::clock): Count up to rate_period twice
+	during ADSR delay bug, and add one extra rate counter step.
+
+	* filter.cc (Filter::bsd_copysign): Renamed copysign function for
+	compilation on platforms where copysign is implemented as a macro.
+	
+1998-08-23  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.3 released.
+
+	* envelope.h (EnvelopeGenerator::clock): Handle ADSR boundary bug.
+	
+	* envelope.cc (EnvelopeGenerator::rate_counter_period,
+	EnvelopeGenerator::exponential_counter_period): Corrected counter
+	periods.
+
+	* filter.h (Filter::clock): Optimized for speed (division by shifting).
+	
+	* sid.h (SID::clock): New one-cycle optimized overload of the clock()
+	function.
+	
+	* wave.h (WaveformGenerator::output_P_T): Combined waveform
+	pulse+triangle indexing corrected.
+	(WaveformGenerator::output_P__): Check for test bit to handle
+	pulse+test bit samples.
+	(WaveformGenerator::output): Optimized for speed (inlining).
+
+1998-07-28  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.2 released.
+
+	* envelope.h (EnvelopeGenerator::clock): Start decay cycle immediately
+	at envelope counter 0xff. New sustain value is zero if the sustain
+	level is raised above the current envelope counter value.
+	(EnvelopeGenerator::step_envelope): Handle ADSR delay bug.
+	
+	* envelope.cc (EnvelopeGenerator::rate_counter_period,
+	EnvelopeGenerator::exponential_counter_period): Corrected counter
+	periods.
+	(EnvelopeGenerator::writeCONTROL_REG): Do not modify rate counter.
+
+	* filter.cc (Filter::set_Q): Constrain Q to keep filter stable.
+	
+	* sid.h (SID::read, SID::write, SID::bypass_filter): Simplified API
+	routing register access through the SID class.
+
+	* sid.cc (SID::output): Corrected variable-bit audio output return.
+	(SID::read, SID::write): Allow read of write only registers.
+
+1998-06-09  Dag Lem  <resid@nimrod.no>
+
+	* Version 0.1 released.
diff --git a/MCUME_pico2/pico64/reSID/INSTALL b/MCUME_pico2/pico64/reSID/INSTALL
new file mode 100755
index 0000000..54caf7c
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/INSTALL
@@ -0,0 +1,229 @@
+Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002 Free Software
+Foundation, Inc.
+
+   This file is free documentation; the Free Software Foundation gives
+unlimited permission to copy, distribute and modify it.
+
+Basic Installation
+==================
+
+   These are generic installation instructions.
+
+   The `configure' shell script attempts to guess correct values for
+various system-dependent variables used during compilation.  It uses
+those values to create a `Makefile' in each directory of the package.
+It may also create one or more `.h' files containing system-dependent
+definitions.  Finally, it creates a shell script `config.status' that
+you can run in the future to recreate the current configuration, and a
+file `config.log' containing compiler output (useful mainly for
+debugging `configure').
+
+   It can also use an optional file (typically called `config.cache'
+and enabled with `--cache-file=config.cache' or simply `-C') that saves
+the results of its tests to speed up reconfiguring.  (Caching is
+disabled by default to prevent problems with accidental use of stale
+cache files.)
+
+   If you need to do unusual things to compile the package, please try
+to figure out how `configure' could check whether to do them, and mail
+diffs or instructions to the address given in the `README' so they can
+be considered for the next release.  If you are using the cache, and at
+some point `config.cache' contains results you don't want to keep, you
+may remove or edit it.
+
+   The file `configure.ac' (or `configure.in') is used to create
+`configure' by a program called `autoconf'.  You only need
+`configure.ac' if you want to change it or regenerate `configure' using
+a newer version of `autoconf'.
+
+The simplest way to compile this package is:
+
+  1. `cd' to the directory containing the package's source code and type
+     `./configure' to configure the package for your system.  If you're
+     using `csh' on an old version of System V, you might need to type
+     `sh ./configure' instead to prevent `csh' from trying to execute
+     `configure' itself.
+
+     Running `configure' takes awhile.  While running, it prints some
+     messages telling which features it is checking for.
+
+  2. Type `make' to compile the package.
+
+  3. Optionally, type `make check' to run any self-tests that come with
+     the package.
+
+  4. Type `make install' to install the programs and any data files and
+     documentation.
+
+  5. You can remove the program binaries and object files from the
+     source code directory by typing `make clean'.  To also remove the
+     files that `configure' created (so you can compile the package for
+     a different kind of computer), type `make distclean'.  There is
+     also a `make maintainer-clean' target, but that is intended mainly
+     for the package's developers.  If you use it, you may have to get
+     all sorts of other programs in order to regenerate files that came
+     with the distribution.
+
+Compilers and Options
+=====================
+
+   Some systems require unusual options for compilation or linking that
+the `configure' script does not know about.  Run `./configure --help'
+for details on some of the pertinent environment variables.
+
+   You can give `configure' initial values for configuration parameters
+by setting variables in the command line or in the environment.  Here
+is an example:
+
+     ./configure CC=c89 CFLAGS=-O2 LIBS=-lposix
+
+   *Note Defining Variables::, for more details.
+
+Compiling For Multiple Architectures
+====================================
+
+   You can compile the package for more than one kind of computer at the
+same time, by placing the object files for each architecture in their
+own directory.  To do this, you must use a version of `make' that
+supports the `VPATH' variable, such as GNU `make'.  `cd' to the
+directory where you want the object files and executables to go and run
+the `configure' script.  `configure' automatically checks for the
+source code in the directory that `configure' is in and in `..'.
+
+   If you have to use a `make' that does not support the `VPATH'
+variable, you have to compile the package for one architecture at a
+time in the source code directory.  After you have installed the
+package for one architecture, use `make distclean' before reconfiguring
+for another architecture.
+
+Installation Names
+==================
+
+   By default, `make install' will install the package's files in
+`/usr/local/bin', `/usr/local/man', etc.  You can specify an
+installation prefix other than `/usr/local' by giving `configure' the
+option `--prefix=PATH'.
+
+   You can specify separate installation prefixes for
+architecture-specific files and architecture-independent files.  If you
+give `configure' the option `--exec-prefix=PATH', the package will use
+PATH as the prefix for installing programs and libraries.
+Documentation and other data files will still use the regular prefix.
+
+   In addition, if you use an unusual directory layout you can give
+options like `--bindir=PATH' to specify different values for particular
+kinds of files.  Run `configure --help' for a list of the directories
+you can set and what kinds of files go in them.
+
+   If the package supports it, you can cause programs to be installed
+with an extra prefix or suffix on their names by giving `configure' the
+option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
+
+Optional Features
+=================
+
+   Some packages pay attention to `--enable-FEATURE' options to
+`configure', where FEATURE indicates an optional part of the package.
+They may also pay attention to `--with-PACKAGE' options, where PACKAGE
+is something like `gnu-as' or `x' (for the X Window System).  The
+`README' should mention any `--enable-' and `--with-' options that the
+package recognizes.
+
+   For packages that use the X Window System, `configure' can usually
+find the X include and library files automatically, but if it doesn't,
+you can use the `configure' options `--x-includes=DIR' and
+`--x-libraries=DIR' to specify their locations.
+
+Specifying the System Type
+==========================
+
+   There may be some features `configure' cannot figure out
+automatically, but needs to determine by the type of machine the package
+will run on.  Usually, assuming the package is built to be run on the
+_same_ architectures, `configure' can figure that out, but if it prints
+a message saying it cannot guess the machine type, give it the
+`--build=TYPE' option.  TYPE can either be a short name for the system
+type, such as `sun4', or a canonical name which has the form:
+
+     CPU-COMPANY-SYSTEM
+
+where SYSTEM can have one of these forms:
+
+     OS KERNEL-OS
+
+   See the file `config.sub' for the possible values of each field.  If
+`config.sub' isn't included in this package, then this package doesn't
+need to know the machine type.
+
+   If you are _building_ compiler tools for cross-compiling, you should
+use the `--target=TYPE' option to select the type of system they will
+produce code for.
+
+   If you want to _use_ a cross compiler, that generates code for a
+platform different from the build platform, you should specify the
+"host" platform (i.e., that on which the generated programs will
+eventually be run) with `--host=TYPE'.
+
+Sharing Defaults
+================
+
+   If you want to set default values for `configure' scripts to share,
+you can create a site shell script called `config.site' that gives
+default values for variables like `CC', `cache_file', and `prefix'.
+`configure' looks for `PREFIX/share/config.site' if it exists, then
+`PREFIX/etc/config.site' if it exists.  Or, you can set the
+`CONFIG_SITE' environment variable to the location of the site script.
+A warning: not all `configure' scripts look for a site script.
+
+Defining Variables
+==================
+
+   Variables not defined in a site shell script can be set in the
+environment passed to `configure'.  However, some packages may run
+configure again during the build, and the customized values of these
+variables may be lost.  In order to avoid this problem, you should set
+them in the `configure' command line, using `VAR=value'.  For example:
+
+     ./configure CC=/usr/local2/bin/gcc
+
+will cause the specified gcc to be used as the C compiler (unless it is
+overridden in the site shell script).
+
+`configure' Invocation
+======================
+
+   `configure' recognizes the following options to control how it
+operates.
+
+`--help'
+`-h'
+     Print a summary of the options to `configure', and exit.
+
+`--version'
+`-V'
+     Print the version of Autoconf used to generate the `configure'
+     script, and exit.
+
+`--cache-file=FILE'
+     Enable the cache: use and save the results of the tests in FILE,
+     traditionally `config.cache'.  FILE defaults to `/dev/null' to
+     disable caching.
+
+`--config-cache'
+`-C'
+     Alias for `--cache-file=config.cache'.
+
+`--quiet'
+`--silent'
+`-q'
+     Do not print messages saying which checks are being made.  To
+     suppress all normal output, redirect it to `/dev/null' (any error
+     messages will still be shown).
+
+`--srcdir=DIR'
+     Look for the package's source code in directory DIR.  Usually
+     `configure' can determine that directory automatically.
+
+`configure' also accepts some other, not widely useful, options.  Run
+`configure --help' for more details.
+
diff --git a/MCUME_pico2/pico64/reSID/NEWS b/MCUME_pico2/pico64/reSID/NEWS
new file mode 100755
index 0000000..e0ff298
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/NEWS
@@ -0,0 +1,271 @@
+Changes in reSID version 0.16
+-----------------------------
+
+An off-by-one error in the emulation of the ADSR delay bug has been
+fixed in the fast version of the envelope clocking.
+
+An initialization bug in the Filter class which caused floating point
+exceptions on some platforms has been fixed.
+
+Missing fields have been added to SID::State for correct snapshots.
+
+By building shifted FIR tables with samples according to the sampling
+frequency, the resampling code dramatically reduces the computational
+effort in the filter convolutions, without any loss of accuracy. The
+filter convolutions are now also vectorizable on current hardware. The
+implementation builds on ideas by Laurent Ganier.
+
+The resampling code has been split into two functions, one using
+interpolation and a small set of shifted filter tables, and one using
+direct lookup and a large set of shifted filter tables. The accuracy
+is the same, the difference is that the direct lookup runs has the
+potential of running at almost twice the speed (depending on cache
+size and memory bandwidth) using approximately 16MB more memory. It is
+now possible to run high quality resampling in real time on quite
+modest hardware, provided that a vectorizing compiler is used.
+
+
+Changes in reSID version 0.15
+-----------------------------
+
+An error in the emulation of the ADSR delay bug has been fixed. When
+emulation of the ADSR delay bug was introduced in reSID 0.2, the delay
+was one cycle too long. One cycle was subtracted from the delay in
+reSID 0.4, however unfortunately one rate counter period was added as
+well, thus increasing the error. At the time there was no method to
+fully synchronize the CPU with envelope 3, so the measurements relied
+on averaging. Because of pipelining in the envelope logic the effects
+of a write are delayed, and this caused the test code to miss the
+target by exactly one rate counter period on a real SID. The current
+test code does achieve full synchronization with envelope 3, so this
+time the delay should be 100% correct. There are still side effects
+caused by pipelining which are not implemented in reSID, however these
+effects are not controllable without full synchronization with the
+envelope, something which is hard to achieve with envelope 3, and
+impossible with envelope 1 and 2.
+
+The envelope state (ADSR) has been added to the SID state, and the
+volume setting is now restored from the SID state.
+
+Filter scaling and clipping has been added to avoid sample overflows
+in the resampling filter.
+
+
+Changes in reSID version 0.14
+-----------------------------
+
+The SID external audio input is now emulated. This can be used e.g. to
+simulate the hack of connecting a resistor from EXT IN to GND to boost
+the sample volume on the MOS8580. Calling sid.input(-32768) makes the
+MOS8580 sound more or less like the MOS6581 with respect to samples.
+The interface could also be used to mix in an external audio signal,
+but note that to do this correctly you should really resample the
+audio signal to 1MHz first.
+
+The filter settings are now updated immediately when the chip model is
+changed. Earlier the filter cutoff frequency would not change until
+the FC registers were updated.
+
+A one cycle error in the fast version of the envelope clocking has
+been fixed. This bug was introduced in reSID 0.13 and could affect the
+ADSR delay emulation.
+
+The exponential counter period is now only loaded at the envelope
+counter values 255, 93, 54, 26, 14, 6, 0. The period can be different
+for the same envelope counter value, depending on whether the envelope
+has been rising (attack -> release) or sinking (decay/release).
+
+A bug in the fast version of the noise register shift routine has been
+corrected. This bug caused too low noise frequency in some cases.
+
+The filter cutoff frequency is limited to 16kHz to keep the filter stable.
+
+
+Changes in reSID version 0.13
+-----------------------------
+
+The internal DC levels of the MOS6581 have been double checked and
+corrected. The reason for the asymmetric scaling of the voice output
+has been found; there is a DC offset from the waveform D/A converter
+in addition to the DC offset from the envelope multiplying D/A
+converter. No selected waveform (N=P=S=T=0) yields minimum wave output
+level again.
+
+A bug in the fast version of the envelope clocking has been corrected.
+This bug could incorrectly invoke the ADSR delay emulation.
+
+
+Changes in reSID version 0.12
+-----------------------------
+
+A bug causing incorrect sample spacing in the new SAMPLE_FAST sample
+calculation has been corrected.
+
+Audio clipping has been added to guard against sample overflows.
+
+To support multi-channel sampling, sample interleaving has been added
+to the clock() interface.
+
+To support synchronization with an external timer, an interface for
+sample rate adjustment has been added.
+
+The internal DC levels have been corrected. No selected waveform
+(N=P=S=T=0) yields maximum wave output level. Furthermore, each voice
+in the MOS6581 independently contributes to the DC level in the mixer,
+and the mixer itself has a small DC offset as well. The MOS8580 has no
+DC offsets.
+
+The spline interpolation routine has been generalized to accept
+repeated points to introduce points of non-differentiability and
+discontinuity.
+
+A separate mapping from the FC registers to filter cutoff frequency
+has been included for the MOS8580, and the mapping for the MOS6581 has
+been refined.
+
+
+Changes in reSID version 0.11
+-----------------------------
+
+A new clock() interface has been added. This function generates audio
+samples into a buffer, greatly simplifying the task of writing driver
+code for reSID. It also facilitates more advanced audio sample
+generation, as described below.
+
+Three clocking methods are available: clocking at output sample
+frequency, clocking at cycle frequency with linear sample
+interpolation, and clocking at cycle frequency with audio resampling.
+
+Clocking at output sample frequency is fast, and yields acceptable
+sound quality, except for the SID combined waveforms, which have a
+very high frequency content.
+
+Clocking at cycle frequency with linear sample interpolation is
+approximately five to ten times slower at 44.1kHz sampling frequency,
+but the sound quality is improved because of the linear sample
+interpolation, and because some sampling noise is removed by the SID
+external filter, which attenuates signals above 16kHz.
+
+Finally, clocking at cycle frequency with audio resampling has a work
+rate which is independent of the sampling frequency; it is rather
+inversely proportional to the percentage of the bandwidth allocated
+to the filter transition band. This implies that e.g. with the
+transition band starting at ~ 20kHz, it is faster to generate 48kHz
+than 44.1kHz samples.
+
+Audio resampling is the theoretically correct method for sample
+generation, and delivers SID sound quality previously unheard of. This
+should make connoisseurs nod in appreciation, and for some time to
+come it could possibly also make people tear their hair over having to
+buy state of the art hardware to handle the obscene workload in real
+time. By trading off passband bandwidth for speed, real time
+processing is possible on current hardware. A 60% passband bandwidth
+is within the reach of reasonably fast machines, while maximum sound
+quality at 90% passband bandwidth, requiring four times the processing
+power, is not. Yet.
+
+
+Changes in reSID version 0.10
+-----------------------------
+
+Libtool is now used to build the library.
+
+To keep the filters stable it is necessary to clock them at above
+sample rate. The chip clocking code has been modified to only
+"overclock" the filters, not the whole chip. This yields a
+considerable speedup without noticeably lowering sound quality. Note
+that this is aimed at slow hardware, if possible the 1 cycle clock
+interface should be used to eliminate sampling noise.
+
+
+Changes in reSID version 0.9
+----------------------------
+
+The sum of the filter outputs is no longer weighted.
+
+
+Changes in reSID version 0.8
+----------------------------
+
+voice3off has no effect if voice 3 is routed through the filter.
+
+
+Changes in reSID version 0.7
+----------------------------
+
+The audio output filter in the C64, external to the SID chip, has been
+modeled.
+
+The mapping function between the FC register and filter cutoff frequency can
+now be specified with spline interpolation points. This facilitates
+interactive modification of the mapping function by graphical presentation of
+the interpolation curve. The implementation of this novel spline design is
+fast and general purpose, and should be well suited for use in other projects
+as well.
+
+Filtered output has been inverted compared to unfiltered output.
+
+Aging of the bus value obtained when reading write only registers has been
+partly implemented.
+
+To facilitate offline storage the complete state of SID can be read and
+written.
+
+
+Changes in reSID version 0.6
+----------------------------
+
+A special case in synchronization has been implemented.
+
+The Autoconf script is cleaned up to allow compilation in a separate directory.
+
+
+Changes in reSID version 0.5
+----------------------------
+
+Emulation of MOS8580 combined waveforms.
+
+Version string resid_version_string provided for e.g. Autoconf tests.
+The string has C linkage.
+
+
+Changes in reSID version 0.4
+----------------------------
+
+The implementation of the ADSR delay bug has been refined and should now be
+cycle exact.
+
+The patch for VICE has been removed since VICE 0.15 will include reSID support.
+
+
+Changes in reSID version 0.3
+----------------------------
+
+The reSID library has changed name from libmos6581.a to libresid.a
+
+The pulse+sawtooth combined waveform has been corrected.
+
+Pulse+test bit samples are implemented.
+
+The envelope rate periods have finally been exactly determined.
+
+A new SID bug, the ADSR boundary bug, has been discovered and implemented.
+This bug makes it possible to step from envelope level 0x00 to 0xff or from
+0xff to 0x00 in one step.
+
+One-cycle optimized overloads of the clock() functions have been implemented
+to facilitate sampling at 1MHz.
+
+The code has been further optimized for speed.
+
+
+Changes in reSID version 0.2
+----------------------------
+
+The implementation of the Envelope Generator has been rewritten to handle
+the infamous ADSR delay bug. All known envelope related bugs have been
+corrected.
+
+The maximum filter resonance is lowered to keep the filter stable.
+
+The reSID API has been simplified. Reading write only registers is allowed.
diff --git a/MCUME_pico2/pico64/reSID/README b/MCUME_pico2/pico64/reSID/README
new file mode 100755
index 0000000..79da519
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/README
@@ -0,0 +1,26 @@
+This is reSID, a reverse engineered software emulation of the MOS6581 SID
+(Sound Interface Device). This chip was used in the Commodore 64 computer.
+
+reSID is free software. See the file COPYING for copying permission.
+
+reSID is a C++ library containing a complete emulation of the SID chip.
+This library can be linked into programs emulating the MOS6510 MPU to
+play music made for the Commodore 64 computer. reSID has been successfully
+linked into VICE, a full-fledged Commodore 64 emulator, and SIDPLAY, a
+popular SID tune player. The VICE home page is:
+http://www.viceteam.org/
+A patch for SIDPLAY can be found on the SIDPLAY home page:
+http://www.geocities.com/SiliconValley/Lakes/5147/
+
+Various SID emulators exist, however reSID should still be of great
+interest to Commodore 64 nostalgics. The emulator engine is cycle-based,
+emulating the internal operations of the SID chip. SID's audio filter is
+modeled as an actual two-integrator-loop biquadratic filter circuit.
+The engine has been developed based on available information on SID, sampling
+of the OSC3 and ENV3 registers, filter theory, and meticulous testing.
+In short, a scientific approach has been taken to model the SID chip as
+accurately as possible.
+
+To our knowledge reSID is by far the most accurate SID emulator ever created.
+This comes at a price; what is considered a fairly fast CPU at the time of
+this writing is needed to run the emulator.
diff --git a/MCUME_pico2/pico64/reSID/THANKS b/MCUME_pico2/pico64/reSID/THANKS
new file mode 100755
index 0000000..824c682
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/THANKS
@@ -0,0 +1,87 @@
+reSID was written by Dag Lem.
+
+The project was started after reading an interview with Bob Yannes, the
+head engineer of the SID chip. This interview was made by Andreas Varga,
+with additional questions from Linus Walleij. The interview can be found on
+the SID Homepage:
+http://stud1.tuwien.ac.at/~e9426444/sidpage.html
+The reverse engineering of the SID chip would not have been possible without
+this interview.
+
+Also found on the SID Homepage is an examination of the SID noise waveform
+written by Asger Alstrup. This article was of great help in reverse
+engineering the complete algorithm for the noise waveform.
+
+Lars Haugseth has been invaluable in the testing of reSID.
+In a matter of hours after hearing about my project, he had completed a 6510
+disassembler in Perl. The importance of this was not evident to me until the
+next day when he had disassembled the music routine for "Outrun Remix" by
+Geir Tjelta, made some changes to it, reassembled, and produced a file
+containing 48K of SID register values.
+The first tests of reSID were run on this file.
+With an exceptional memory of Commodore 64 tunes Lars Haugseth has pointed
+out several errors in reSID that are now corrected.
+
+Morten Rollan and Kåre Gunnar Nesheim have provided interesting and insightful
+information regarding digital filters. Kåre Gunnar Nesheim has also kindly
+provided a 1901 monitor and a C64C from his private computer museum. His C64C
+was used to measure the MOS8580 filter cutoff characteristics.
+
+VICE has been an inspiration for this project, and testing of reSID has
+been greatly simplified by VICEs -sounddev dump option. Teemu Rantanen
+has written support for reSID in VICE, making it possible to choose at runtime
+between his excellent SID emulation and, given enough CPU power, the reSID
+emulator engine. Tibor Biczo, Andreas Boose, and André Fachat have provided
+combined waveform samples for 6581 R1, R3, R4, and 8580 R5 SID chips.
+The VICE home page is found at:
+http://www.viceteam.org/
+
+The author of SIDPLAY, Michael Schwendt, has implemented a patch to link
+libsidplay with reSID. Using his excellent tune player he has pointed out
+several bugs in reSID. He has also provided invaluable information related to
+the bugs as basis for further investigation. Most notably, the infamous ADSR
+delay bug, of which I was previously unaware, has finally been understood and
+is now correctly implemented in reSID. The SIDPLAY home page is found at:
+http://www.geocities.com/SiliconValley/Lakes/5147/
+
+A bug report from Daniel Lacasse led to the discovery of a previously unknown
+SID bug, the ADSR boundary bug.
+
+Anders Ødegård has explained aspects of analog electronics and audio
+equipment.
+
+Bob Yannes has patiently answered questions and has provided lots of
+technical information on the SID filter. Thank you Bob!
+
+Julius O. Smith III has provided much of the theoretical basis for the
+audio resampling with his "Digital Audio Resampling Home Page":
+http://www-ccrma.stanford.edu/~jos/resample/
+
+Hársfalvi, Levente has made a thorough investigation of the DC levels
+in the MOS6581 chip. His results are available in C= Hacking Issue #20,
+and form the basis of DC corrections in reSID. Levente found that each
+voice independently contributes to the DC level in the mixer. Note
+that some of the conclusions in the article are incorrect, as the
+maximum and minimum voice output levels are interchanged.
+
+The author of SIDPLAY2, Simon White, has given a lot of feedback on
+reSID. Most importantly he found and fixed a bug in the fast clock
+version of the ADSR emulation.
+
+Laurent Ovaert found and fixed a bug in the fast version of the noise
+register shift routine.
+
+Andreas Dehmel has reported all sorts of initialization and overflow
+errors.
+
+Laurent Ganier demonstrated two crucial techniques for vectorizable
+filter convolution in a patch. Firstly, he made the filter elements
+correspond to the sampling frequency, allowing the linear
+interpolation to be factorized out from the convolution. Secondly, he
+duplicated elements in the sample ring buffer, achieving contiguous
+storage of the samples. The current resampling implementation builds
+on these ideas, improving on them by using shifted filter tables for
+generalization and accuracy.
+
+Finally I would like to thank my business partner Stian W. Arnesen for
+putting up with all this nonsense.
diff --git a/MCUME_pico2/pico64/reSID/TODO b/MCUME_pico2/pico64/reSID/TODO
new file mode 100755
index 0000000..4527dfa
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/TODO
@@ -0,0 +1,8 @@
+* Determine the characteristics of the SID filter integrators. Spice
+  may perhaps be used to simulate the filter circuit.
+
+* Write documentation. Possibly a paper describing how SID was reverse
+  engineered.
+
+* Implement a SID tune player. A PSID player, VSID, is partly
+  implemented in VICE.
diff --git a/MCUME_pico2/pico64/reSID/envelope.cc b/MCUME_pico2/pico64/reSID/envelope.cc
new file mode 100755
index 0000000..cf29cb2
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/envelope.cc
@@ -0,0 +1,227 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __ENVELOPE_CC__
+#include "envelope.h"
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+EnvelopeGenerator::EnvelopeGenerator()
+{
+  reset();
+}
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void EnvelopeGenerator::reset()
+{
+  envelope_counter = 0;
+
+  attack = 0;
+  decay = 0;
+  sustain = 0;
+  release = 0;
+
+  gate = 0;
+
+  rate_counter = 0;
+  exponential_counter = 0;
+  exponential_counter_period = 1;
+
+  state = RELEASE;
+  rate_period = rate_counter_period[release];
+  hold_zero = true;
+}
+
+
+// Rate counter periods are calculated from the Envelope Rates table in
+// the Programmer's Reference Guide. The rate counter period is the number of
+// cycles between each increment of the envelope counter.
+// The rates have been verified by sampling ENV3. 
+//
+// The rate counter is a 16 bit register which is incremented each cycle.
+// When the counter reaches a specific comparison value, the envelope counter
+// is incremented (attack) or decremented (decay/release) and the
+// counter is zeroed.
+//
+// NB! Sampling ENV3 shows that the calculated values are not exact.
+// It may seem like most calculated values have been rounded (.5 is rounded
+// down) and 1 has beed added to the result. A possible explanation for this
+// is that the SID designers have used the calculated values directly
+// as rate counter comparison values, not considering a one cycle delay to
+// zero the counter. This would yield an actual period of comparison value + 1.
+//
+// The time of the first envelope count can not be exactly controlled, except
+// possibly by resetting the chip. Because of this we cannot do cycle exact
+// sampling and must devise another method to calculate the rate counter
+// periods.
+//
+// The exact rate counter periods can be determined e.g. by counting the number
+// of cycles from envelope level 1 to envelope level 129, and dividing the
+// number of cycles by 128. CIA1 timer A and B in linked mode can perform
+// the cycle count. This is the method used to find the rates below.
+//
+// To avoid the ADSR delay bug, sampling of ENV3 should be done using
+// sustain = release = 0. This ensures that the attack state will not lower
+// the current rate counter period.
+//
+// The ENV3 sampling code below yields a maximum timing error of 14 cycles.
+//     lda #$01
+// l1: cmp $d41c
+//     bne l1
+//     ...
+//     lda #$ff
+// l2: cmp $d41c
+//     bne l2
+//
+// This yields a maximum error for the calculated rate period of 14/128 cycles.
+// The described method is thus sufficient for exact calculation of the rate
+// periods.
+//
+const reg16 EnvelopeGenerator::rate_counter_period[] = {
+      9,  //   2ms*1.0MHz/256 =     7.81
+     32,  //   8ms*1.0MHz/256 =    31.25
+     63,  //  16ms*1.0MHz/256 =    62.50
+     95,  //  24ms*1.0MHz/256 =    93.75
+    149,  //  38ms*1.0MHz/256 =   148.44
+    220,  //  56ms*1.0MHz/256 =   218.75
+    267,  //  68ms*1.0MHz/256 =   265.63
+    313,  //  80ms*1.0MHz/256 =   312.50
+    392,  // 100ms*1.0MHz/256 =   390.63
+    977,  // 250ms*1.0MHz/256 =   976.56
+   1954,  // 500ms*1.0MHz/256 =  1953.13
+   3126,  // 800ms*1.0MHz/256 =  3125.00
+   3907,  //   1 s*1.0MHz/256 =  3906.25
+  11720,  //   3 s*1.0MHz/256 = 11718.75
+  19532,  //   5 s*1.0MHz/256 = 19531.25
+  31251   //   8 s*1.0MHz/256 = 31250.00
+};
+
+
+// For decay and release, the clock to the envelope counter is sequentially
+// divided by 1, 2, 4, 8, 16, 30, 1 to create a piece-wise linear approximation
+// of an exponential. The exponential counter period is loaded at the envelope
+// counter values 255, 93, 54, 26, 14, 6, 0. The period can be different for the
+// same envelope counter value, depending on whether the envelope has been
+// rising (attack -> release) or sinking (decay/release).
+//
+// Since it is not possible to reset the rate counter (the test bit has no
+// influence on the envelope generator whatsoever) a method must be devised to
+// do cycle exact sampling of ENV3 to do the investigation. This is possible
+// with knowledge of the rate period for A=0, found above.
+//
+// The CPU can be synchronized with ENV3 by first synchronizing with the rate
+// counter by setting A=0 and wait in a carefully timed loop for the envelope
+// counter _not_ to change for 9 cycles. We can then wait for a specific value
+// of ENV3 with another timed loop to fully synchronize with ENV3.
+//
+// At the first period when an exponential counter period larger than one
+// is used (decay or relase), one extra cycle is spent before the envelope is
+// decremented. The envelope output is then delayed one cycle until the state
+// is changed to attack. Now one cycle less will be spent before the envelope
+// is incremented, and the situation is normalized.
+// The delay is probably caused by the comparison with the exponential counter,
+// and does not seem to affect the rate counter. This has been verified by
+// timing 256 consecutive complete envelopes with A = D = R = 1, S = 0, using
+// CIA1 timer A and B in linked mode. If the rate counter is not affected the
+// period of each complete envelope is
+// (255 + 162*1 + 39*2 + 28*4 + 12*8 + 8*16 + 6*30)*32 = 756*32 = 32352
+// which corresponds exactly to the timed value divided by the number of
+// complete envelopes.
+// NB! This one cycle delay is not modeled.
+
+
+// From the sustain levels it follows that both the low and high 4 bits of the
+// envelope counter are compared to the 4-bit sustain value.
+// This has been verified by sampling ENV3.
+//
+const reg8 EnvelopeGenerator::sustain_level[] = {
+  0x00,
+  0x11,
+  0x22,
+  0x33,
+  0x44,
+  0x55,
+  0x66,
+  0x77,
+  0x88,
+  0x99,
+  0xaa,
+  0xbb,
+  0xcc,
+  0xdd,
+  0xee,
+  0xff,
+};
+
+
+// ----------------------------------------------------------------------------
+// Register functions.
+// ----------------------------------------------------------------------------
+void EnvelopeGenerator::writeCONTROL_REG(reg8 control)
+{
+  reg8 gate_next = control & 0x01;
+
+  // The rate counter is never reset, thus there will be a delay before the
+  // envelope counter starts counting up (attack) or down (release).
+
+  // Gate bit on: Start attack, decay, sustain.
+  if (!gate && gate_next) {
+    state = ATTACK;
+    rate_period = rate_counter_period[attack];
+
+    // Switching to attack state unlocks the zero freeze.
+    hold_zero = false;
+  }
+  // Gate bit off: Start release.
+  else if (gate && !gate_next) {
+    state = RELEASE;
+    rate_period = rate_counter_period[release];
+  }
+
+  gate = gate_next;
+}
+
+void EnvelopeGenerator::writeATTACK_DECAY(reg8 attack_decay)
+{
+  attack = (attack_decay >> 4) & 0x0f;
+  decay = attack_decay & 0x0f;
+  if (state == ATTACK) {
+    rate_period = rate_counter_period[attack];
+  }
+  else if (state == DECAY_SUSTAIN) {
+    rate_period = rate_counter_period[decay];
+  }
+}
+
+void EnvelopeGenerator::writeSUSTAIN_RELEASE(reg8 sustain_release)
+{
+  sustain = (sustain_release >> 4) & 0x0f;
+  release = sustain_release & 0x0f;
+  if (state == RELEASE) {
+    rate_period = rate_counter_period[release];
+  }
+}
+
+reg8 EnvelopeGenerator::readENV()
+{
+  return output();
+}
diff --git a/MCUME_pico2/pico64/reSID/envelope.h b/MCUME_pico2/pico64/reSID/envelope.h
new file mode 100755
index 0000000..0cdefd5
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/envelope.h
@@ -0,0 +1,305 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __ENVELOPE_H__
+#define __ENVELOPE_H__
+
+#include "siddefs.h"
+
+// ----------------------------------------------------------------------------
+// A 15 bit counter is used to implement the envelope rates, in effect
+// dividing the clock to the envelope counter by the currently selected rate
+// period.
+// In addition, another counter is used to implement the exponential envelope
+// decay, in effect further dividing the clock to the envelope counter.
+// The period of this counter is set to 1, 2, 4, 8, 16, 30 at the envelope
+// counter values 255, 93, 54, 26, 14, 6, respectively.
+// ----------------------------------------------------------------------------
+class RESID_API EnvelopeGenerator
+{
+public:
+  EnvelopeGenerator();
+
+  enum State { ATTACK, DECAY_SUSTAIN, RELEASE };
+
+  RESID_INLINE void clock();
+  RESID_INLINE void clock(cycle_count delta_t);
+  void reset();
+
+  void writeCONTROL_REG(reg8);
+  void writeATTACK_DECAY(reg8);
+  void writeSUSTAIN_RELEASE(reg8);
+  reg8 readENV();
+
+  // 8-bit envelope output.
+  RESID_INLINE reg8 output();
+
+protected:
+  reg16 rate_counter;
+  reg16 rate_period;
+  reg8 exponential_counter;
+  reg8 exponential_counter_period;
+  reg8 envelope_counter;
+  bool hold_zero;
+
+  reg4 attack;
+  reg4 decay;
+  reg4 sustain;
+  reg4 release;
+
+  reg8 gate;
+
+  State state;
+
+  // Lookup table to convert from attack, decay, or release value to rate
+  // counter period.
+  static const reg16 rate_counter_period[];
+
+  // The 16 selectable sustain levels.
+  static const reg8 sustain_level[];
+
+friend class SID;
+};
+
+
+// ----------------------------------------------------------------------------
+// Inline functions.
+// The following functions are defined inline because they are called every
+// time a sample is calculated.
+// ----------------------------------------------------------------------------
+
+#if RESID_INLINING || defined(__ENVELOPE_CC__)
+
+// ----------------------------------------------------------------------------
+// SID clocking - 1 cycle.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void EnvelopeGenerator::clock()
+{
+  // Check for ADSR delay bug.
+  // If the rate counter comparison value is set below the current value of the
+  // rate counter, the counter will continue counting up until it wraps around
+  // to zero at 2^15 = 0x8000, and then count rate_period - 1 before the
+  // envelope can finally be stepped.
+  // This has been verified by sampling ENV3.
+  //
+  if (++rate_counter & 0x8000) {
+    ++rate_counter &= 0x7fff;
+  }
+
+  if (rate_counter != rate_period) {
+    return;
+  }
+
+  rate_counter = 0;
+
+  // The first envelope step in the attack state also resets the exponential
+  // counter. This has been verified by sampling ENV3.
+  //
+  if (state == ATTACK || ++exponential_counter == exponential_counter_period)
+  {
+    exponential_counter = 0;
+
+    // Check whether the envelope counter is frozen at zero.
+    if (hold_zero) {
+      return;
+    }
+
+    switch (state) {
+    case ATTACK:
+      // The envelope counter can flip from 0xff to 0x00 by changing state to
+      // release, then to attack. The envelope counter is then frozen at
+      // zero; to unlock this situation the state must be changed to release,
+      // then to attack. This has been verified by sampling ENV3.
+      //
+      ++envelope_counter &= 0xff;
+      if (envelope_counter == 0xff) {
+	state = DECAY_SUSTAIN;
+	rate_period = rate_counter_period[decay];
+      }
+      break;
+    case DECAY_SUSTAIN:
+      if (envelope_counter != sustain_level[sustain]) {
+	--envelope_counter;
+      }
+      break;
+    case RELEASE:
+      // The envelope counter can flip from 0x00 to 0xff by changing state to
+      // attack, then to release. The envelope counter will then continue
+      // counting down in the release state.
+      // This has been verified by sampling ENV3.
+      // NB! The operation below requires two's complement integer.
+      //
+      --envelope_counter &= 0xff;
+      break;
+    }
+    
+    // Check for change of exponential counter period.
+    switch (envelope_counter) {
+    case 0xff:
+      exponential_counter_period = 1;
+      break;
+    case 0x5d:
+      exponential_counter_period = 2;
+      break;
+    case 0x36:
+      exponential_counter_period = 4;
+      break;
+    case 0x1a:
+      exponential_counter_period = 8;
+      break;
+    case 0x0e:
+      exponential_counter_period = 16;
+      break;
+    case 0x06:
+      exponential_counter_period = 30;
+      break;
+    case 0x00:
+      exponential_counter_period = 1;
+
+      // When the envelope counter is changed to zero, it is frozen at zero.
+      // This has been verified by sampling ENV3.
+      hold_zero = true;
+      break;
+    }
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking - delta_t cycles.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void EnvelopeGenerator::clock(cycle_count delta_t)
+{
+  // Check for ADSR delay bug.
+  // If the rate counter comparison value is set below the current value of the
+  // rate counter, the counter will continue counting up until it wraps around
+  // to zero at 2^15 = 0x8000, and then count rate_period - 1 before the
+  // envelope can finally be stepped.
+  // This has been verified by sampling ENV3.
+  //
+
+  // NB! This requires two's complement integer.
+  int rate_step = rate_period - rate_counter;
+  if (rate_step <= 0) {
+    rate_step += 0x7fff;
+  }
+
+  while (delta_t) {
+    if (delta_t < rate_step) {
+      rate_counter += delta_t;
+      if (rate_counter & 0x8000) {
+	++rate_counter &= 0x7fff;
+      }
+      return;
+    }
+
+    rate_counter = 0;
+    delta_t -= rate_step;
+
+    // The first envelope step in the attack state also resets the exponential
+    // counter. This has been verified by sampling ENV3.
+    //
+    if (state == ATTACK	|| ++exponential_counter == exponential_counter_period)
+    {
+      exponential_counter = 0;
+
+      // Check whether the envelope counter is frozen at zero.
+      if (hold_zero) {
+	rate_step = rate_period;
+	continue;
+      }
+
+      switch (state) {
+      case ATTACK:
+	// The envelope counter can flip from 0xff to 0x00 by changing state to
+	// release, then to attack. The envelope counter is then frozen at
+	// zero; to unlock this situation the state must be changed to release,
+	// then to attack. This has been verified by sampling ENV3.
+	//
+	++envelope_counter &= 0xff;
+	if (envelope_counter == 0xff) {
+	  state = DECAY_SUSTAIN;
+	  rate_period = rate_counter_period[decay];
+	}
+	break;
+      case DECAY_SUSTAIN:
+	if (envelope_counter != sustain_level[sustain]) {
+	  --envelope_counter;
+	}
+	break;
+      case RELEASE:
+	// The envelope counter can flip from 0x00 to 0xff by changing state to
+	// attack, then to release. The envelope counter will then continue
+	// counting down in the release state.
+	// This has been verified by sampling ENV3.
+	// NB! The operation below requires two's complement integer.
+	//
+	--envelope_counter &= 0xff;
+	break;
+      }
+
+      // Check for change of exponential counter period.
+      switch (envelope_counter) {
+      case 0xff:
+	exponential_counter_period = 1;
+	break;
+      case 0x5d:
+	exponential_counter_period = 2;
+	break;
+      case 0x36:
+	exponential_counter_period = 4;
+	break;
+      case 0x1a:
+	exponential_counter_period = 8;
+	break;
+      case 0x0e:
+	exponential_counter_period = 16;
+	break;
+      case 0x06:
+	exponential_counter_period = 30;
+	break;
+      case 0x00:
+	exponential_counter_period = 1;
+
+	// When the envelope counter is changed to zero, it is frozen at zero.
+	// This has been verified by sampling ENV3.
+	hold_zero = true;
+	break;
+      }
+    }
+
+    rate_step = rate_period;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Read the envelope generator output.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+reg8 EnvelopeGenerator::output()
+{
+  return envelope_counter;
+}
+
+#endif // RESID_INLINING || defined(__ENVELOPE_CC__)
+
+#endif // not __ENVELOPE_H__
diff --git a/MCUME_pico2/pico64/reSID/extfilt.cc b/MCUME_pico2/pico64/reSID/extfilt.cc
new file mode 100755
index 0000000..b875ee2
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/extfilt.cc
@@ -0,0 +1,79 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __EXTFILT_CC__
+#include "extfilt.h"
+
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+ExternalFilter::ExternalFilter()
+{
+  reset();
+  enable_filter(true);
+  set_chip_model(MOS6581);
+
+  // Low-pass:  R = 10kOhm, C = 1000pF; w0l = 1/RC = 1/(1e4*1e-9) = 100000
+  // High-pass: R =  1kOhm, C =   10uF; w0h = 1/RC = 1/(1e3*1e-5) =    100
+  // Multiply with 1.048576 to facilitate division by 1 000 000 by right-
+  // shifting 20 times (2 ^ 20 = 1048576).
+
+  w0lp = 104858;
+  w0hp = 105;
+}
+
+
+// ----------------------------------------------------------------------------
+// Enable filter.
+// ----------------------------------------------------------------------------
+void ExternalFilter::enable_filter(bool enable)
+{
+  enabled = enable;
+}
+
+
+// ----------------------------------------------------------------------------
+// Set chip model.
+// ----------------------------------------------------------------------------
+void ExternalFilter::set_chip_model(chip_model model)
+{
+  if (model == MOS6581) {
+    // Maximum mixer DC output level; to be removed if the external
+    // filter is turned off: ((wave DC + voice DC)*voices + mixer DC)*volume
+    // See voice.cc and filter.cc for an explanation of the values.
+    mixer_DC = ((((0x800 - 0x380) + 0x800)*0xff*3 - 0xfff*0xff/18) >> 7)*0x0f;
+  }
+  else {
+    // No DC offsets in the MOS8580.
+    mixer_DC = 0;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void ExternalFilter::reset()
+{
+  // State of filter.
+  Vlp = 0;
+  Vhp = 0;
+  Vo = 0;
+}
diff --git a/MCUME_pico2/pico64/reSID/extfilt.h b/MCUME_pico2/pico64/reSID/extfilt.h
new file mode 100755
index 0000000..ec09356
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/extfilt.h
@@ -0,0 +1,164 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __EXTFILT_H__
+#define __EXTFILT_H__
+
+#include "siddefs.h"
+
+// ----------------------------------------------------------------------------
+// The audio output stage in a Commodore 64 consists of two STC networks,
+// a low-pass filter with 3-dB frequency 16kHz followed by a high-pass
+// filter with 3-dB frequency 16Hz (the latter provided an audio equipment
+// input impedance of 1kOhm).
+// The STC networks are connected with a BJT supposedly meant to act as
+// a unity gain buffer, which is not really how it works. A more elaborate
+// model would include the BJT, however DC circuit analysis yields BJT
+// base-emitter and emitter-base impedances sufficiently low to produce
+// additional low-pass and high-pass 3dB-frequencies in the order of hundreds
+// of kHz. This calls for a sampling frequency of several MHz, which is far
+// too high for practical use.
+// ----------------------------------------------------------------------------
+class RESID_API ExternalFilter
+{
+public:
+  ExternalFilter();
+
+  void enable_filter(bool enable);
+  void set_chip_model(chip_model model);
+
+  RESID_INLINE void clock(sound_sample Vi);
+  RESID_INLINE void clock(cycle_count delta_t, sound_sample Vi);
+  void reset();
+
+  // Audio output (20 bits).
+  RESID_INLINE sound_sample output();
+
+protected:
+  // Filter enabled.
+  bool enabled;
+
+  // Maximum mixer DC offset.
+  sound_sample mixer_DC;
+
+  // State of filters.
+  sound_sample Vlp; // lowpass
+  sound_sample Vhp; // highpass
+  sound_sample Vo;
+
+  // Cutoff frequencies.
+  sound_sample w0lp;
+  sound_sample w0hp;
+
+friend class SID;
+};
+
+
+// ----------------------------------------------------------------------------
+// Inline functions.
+// The following functions are defined inline because they are called every
+// time a sample is calculated.
+// ----------------------------------------------------------------------------
+
+#if RESID_INLINING || defined(__EXTFILT_CC__)
+
+// ----------------------------------------------------------------------------
+// SID clocking - 1 cycle.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void ExternalFilter::clock(sound_sample Vi)
+{
+  // This is handy for testing.
+  if (!enabled) {
+    // Remove maximum DC level since there is no filter to do it.
+    Vlp = Vhp = 0;
+    Vo = Vi - mixer_DC;
+    return;
+  }
+
+  // delta_t is converted to seconds given a 1MHz clock by dividing
+  // with 1 000 000.
+
+  // Calculate filter outputs.
+  // Vo  = Vlp - Vhp;
+  // Vlp = Vlp + w0lp*(Vi - Vlp)*delta_t;
+  // Vhp = Vhp + w0hp*(Vlp - Vhp)*delta_t;
+
+  sound_sample dVlp = (w0lp >> 8)*(Vi - Vlp) >> 12;
+  sound_sample dVhp = w0hp*(Vlp - Vhp) >> 20;
+  Vo = Vlp - Vhp;
+  Vlp += dVlp;
+  Vhp += dVhp;
+}
+
+// ----------------------------------------------------------------------------
+// SID clocking - delta_t cycles.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void ExternalFilter::clock(cycle_count delta_t,
+			   sound_sample Vi)
+{
+  // This is handy for testing.
+  if (!enabled) {
+    // Remove maximum DC level since there is no filter to do it.
+    Vlp = Vhp = 0;
+    Vo = Vi - mixer_DC;
+    return;
+  }
+
+  // Maximum delta cycles for the external filter to work satisfactorily
+  // is approximately 8.
+  cycle_count delta_t_flt = 8;
+
+  while (delta_t) {
+    if (delta_t < delta_t_flt) {
+      delta_t_flt = delta_t;
+    }
+
+    // delta_t is converted to seconds given a 1MHz clock by dividing
+    // with 1 000 000.
+
+    // Calculate filter outputs.
+    // Vo  = Vlp - Vhp;
+    // Vlp = Vlp + w0lp*(Vi - Vlp)*delta_t;
+    // Vhp = Vhp + w0hp*(Vlp - Vhp)*delta_t;
+
+    sound_sample dVlp = (w0lp*delta_t_flt >> 8)*(Vi - Vlp) >> 12;
+    sound_sample dVhp = w0hp*delta_t_flt*(Vlp - Vhp) >> 20;
+    Vo = Vlp - Vhp;
+    Vlp += dVlp;
+    Vhp += dVhp;
+
+    delta_t -= delta_t_flt;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Audio output (19.5 bits).
+// ----------------------------------------------------------------------------
+RESID_INLINE
+sound_sample ExternalFilter::output()
+{
+  return Vo;
+}
+
+#endif // RESID_INLINING || defined(__EXTFILT_CC__)
+
+#endif // not __EXTFILT_H__
diff --git a/MCUME_pico2/pico64/reSID/filter.cc b/MCUME_pico2/pico64/reSID/filter.cc
new file mode 100755
index 0000000..11d2738
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/filter.cc
@@ -0,0 +1,319 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __FILTER_CC__
+#include "filter.h"
+
+// Maximum cutoff frequency is specified as
+// FCmax = 2.6e-5/C = 2.6e-5/2200e-12 = 11818.
+//
+// Measurements indicate a cutoff frequency range of approximately
+// 220Hz - 18kHz on a MOS6581 fitted with 470pF capacitors. The function
+// mapping FC to cutoff frequency has the shape of the tanh function, with
+// a discontinuity at FCHI = 0x80.
+// In contrast, the MOS8580 almost perfectly corresponds with the
+// specification of a linear mapping from 30Hz to 12kHz.
+// 
+// The mappings have been measured by feeding the SID with an external
+// signal since the chip itself is incapable of generating waveforms of
+// higher fundamental frequency than 4kHz. It is best to use the bandpass
+// output at full resonance to pick out the cutoff frequency at any given
+// FC setting.
+//
+// The mapping function is specified with spline interpolation points and
+// the function values are retrieved via table lookup.
+//
+// NB! Cutoff frequency characteristics may vary, we have modeled two
+// particular Commodore 64s.
+/*
+fc_point Filter::f0_points_6581[] =
+{
+  //  FC      f         FCHI FCLO
+  // ----------------------------
+  {    0,   220 },   // 0x00      - repeated end point
+  {    0,   220 },   // 0x00
+  {  128,   230 },   // 0x10
+  {  256,   250 },   // 0x20
+  {  384,   300 },   // 0x30
+  {  512,   420 },   // 0x40
+  {  640,   780 },   // 0x50
+  {  768,  1600 },   // 0x60
+  {  832,  2300 },   // 0x68
+  {  896,  3200 },   // 0x70
+  {  960,  4300 },   // 0x78
+  {  992,  5000 },   // 0x7c
+  { 1008,  5400 },   // 0x7e
+  { 1016,  5700 },   // 0x7f
+  { 1023,  6000 },   // 0x7f 0x07
+  { 1023,  6000 },   // 0x7f 0x07 - discontinuity
+  { 1024,  4600 },   // 0x80      -
+  { 1024,  4600 },   // 0x80
+  { 1032,  4800 },   // 0x81
+  { 1056,  5300 },   // 0x84
+  { 1088,  6000 },   // 0x88
+  { 1120,  6600 },   // 0x8c
+  { 1152,  7200 },   // 0x90
+  { 1280,  9500 },   // 0xa0
+  { 1408, 12000 },   // 0xb0
+  { 1536, 14500 },   // 0xc0
+  { 1664, 16000 },   // 0xd0
+  { 1792, 17100 },   // 0xe0
+  { 1920, 17700 },   // 0xf0
+  { 2047, 18000 },   // 0xff 0x07
+  { 2047, 18000 }    // 0xff 0x07 - repeated end point
+};
+
+fc_point Filter::f0_points_8580[] =
+{
+  //  FC      f         FCHI FCLO
+  // ----------------------------
+  {    0,     0 },   // 0x00      - repeated end point
+  {    0,     0 },   // 0x00
+  {  128,   800 },   // 0x10
+  {  256,  1600 },   // 0x20
+  {  384,  2500 },   // 0x30
+  {  512,  3300 },   // 0x40
+  {  640,  4100 },   // 0x50
+  {  768,  4800 },   // 0x60
+  {  896,  5600 },   // 0x70
+  { 1024,  6500 },   // 0x80
+  { 1152,  7500 },   // 0x90
+  { 1280,  8400 },   // 0xa0
+  { 1408,  9200 },   // 0xb0
+  { 1536,  9800 },   // 0xc0
+  { 1664, 10500 },   // 0xd0
+  { 1792, 11000 },   // 0xe0
+  { 1920, 11700 },   // 0xf0
+  { 2047, 12500 },   // 0xff 0x07
+  { 2047, 12500 }    // 0xff 0x07 - repeated end point
+};
+*/
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+Filter::Filter()
+{
+  fc = 0;
+
+  res = 0;
+
+  filt = 0;
+
+  voice3off = 0;
+
+  hp_bp_lp = 0;
+
+  vol = 0;
+
+  // State of filter.
+  Vhp = 0;
+  Vbp = 0;
+  Vlp = 0;
+  Vnf = 0;
+
+  enable_filter(true);
+/*
+  // Create mappings from FC to cutoff frequency.
+  interpolate(f0_points_6581, f0_points_6581
+	      + sizeof(f0_points_6581)/sizeof(*f0_points_6581) - 1,
+	      PointPlotter<sound_sample>(f0_6581), 1.0);
+  interpolate(f0_points_8580, f0_points_8580
+	      + sizeof(f0_points_8580)/sizeof(*f0_points_8580) - 1,
+	      PointPlotter<sound_sample>(f0_8580), 1.0);
+  set_chip_model(MOS6581);
+*/
+{//instead:
+      mixer_DC = -0xfff*0xff/18 >> 7;
+
+    //f0 = f0_6581;
+   // f0_points = f0_points_6581;   
+   // f0_count = sizeof(f0_points_6581)/sizeof(*f0_points_6581);
+    set_w0();
+    set_Q();
+}  
+}
+
+
+// ----------------------------------------------------------------------------
+// Enable filter.
+// ----------------------------------------------------------------------------
+void Filter::enable_filter(bool enable)
+{
+  enabled = enable;
+}
+
+
+// ----------------------------------------------------------------------------
+// Set chip model.
+// ----------------------------------------------------------------------------
+/*
+void Filter::set_chip_model(chip_model model)
+{
+  if (model == MOS6581) {
+    // The mixer has a small input DC offset. This is found as follows:
+    //
+    // The "zero" output level of the mixer measured on the SID audio
+    // output pin is 5.50V at zero volume, and 5.44 at full
+    // volume. This yields a DC offset of (5.44V - 5.50V) = -0.06V.
+    //
+    // The DC offset is thus -0.06V/1.05V ~ -1/18 of the dynamic range
+    // of one voice. See voice.cc for measurement of the dynamic
+    // range.
+
+    mixer_DC = -0xfff*0xff/18 >> 7;
+
+    f0 = f0_6581;
+    f0_points = f0_points_6581;
+    f0_count = sizeof(f0_points_6581)/sizeof(*f0_points_6581);
+  }
+  else {
+    // No DC offsets in the MOS8580.
+    mixer_DC = 0;
+
+    f0 = f0_8580;
+    f0_points = f0_points_8580;
+    f0_count = sizeof(f0_points_8580)/sizeof(*f0_points_8580);
+  }
+
+  set_w0();
+  set_Q();
+}
+*/
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void Filter::reset()
+{
+  fc = 0;
+
+  res = 0;
+
+  filt = 0;
+
+  voice3off = 0;
+
+  hp_bp_lp = 0;
+
+  vol = 0;
+
+  // State of filter.
+  Vhp = 0;
+  Vbp = 0;
+  Vlp = 0;
+  Vnf = 0;
+
+  set_w0();
+  set_Q();
+}
+
+
+// ----------------------------------------------------------------------------
+// Register functions.
+// ----------------------------------------------------------------------------
+void Filter::writeFC_LO(reg8 fc_lo)
+{
+  fc = (fc & 0x7f8) | (fc_lo & 0x007);
+  set_w0();
+}
+
+void Filter::writeFC_HI(reg8 fc_hi)
+{
+  fc = ((fc_hi << 3) & 0x7f8) | (fc & 0x007);
+  set_w0();
+}
+
+void Filter::writeRES_FILT(reg8 res_filt)
+{
+  res = (res_filt >> 4) & 0x0f;
+  set_Q();
+
+  filt = res_filt & 0x0f;
+}
+
+void Filter::writeMODE_VOL(reg8 mode_vol)
+{
+  voice3off = mode_vol & 0x80;
+
+  hp_bp_lp = (mode_vol >> 4) & 0x07;
+
+  vol = mode_vol & 0x0f;
+}
+
+// Set filter cutoff frequency.
+void Filter::set_w0()
+{
+  const double pi = 3.1415926535897932385;
+
+  // Multiply with 1.048576 to facilitate division by 1 000 000 by right-
+  // shifting 20 times (2 ^ 20 = 1048576).
+  w0 = static_cast<sound_sample>(2*pi*f0[fc]*1.048576);
+
+  // Limit f0 to 16kHz to keep 1 cycle filter stable.
+  const sound_sample w0_max_1 = static_cast<sound_sample>(2*pi*16000*1.048576);
+  w0_ceil_1 = w0 <= w0_max_1 ? w0 : w0_max_1;
+
+  // Limit f0 to 4kHz to keep delta_t cycle filter stable.
+  const sound_sample w0_max_dt = static_cast<sound_sample>(2*pi*4000*1.048576);
+  w0_ceil_dt = w0 <= w0_max_dt ? w0 : w0_max_dt;
+}
+
+// Set filter resonance.
+void Filter::set_Q()
+{
+  // Q is controlled linearly by res. Q has approximate range [0.707, 1.7].
+  // As resonance is increased, the filter must be clocked more often to keep
+  // stable.
+
+  // The coefficient 1024 is dispensed of later by right-shifting 10 times
+  // (2 ^ 10 = 1024).
+  _1024_div_Q = static_cast<sound_sample>(1024.0/(0.707 + 1.0*res/0x0f));
+}
+
+// ----------------------------------------------------------------------------
+// Spline functions.
+// ----------------------------------------------------------------------------
+
+// ----------------------------------------------------------------------------
+// Return the array of spline interpolation points used to map the FC register
+// to filter cutoff frequency.
+// ----------------------------------------------------------------------------
+/*
+void Filter::fc_default(const fc_point*& points, int& count)
+{
+  points = f0_points;
+  count = f0_count;
+}
+*/
+
+// ----------------------------------------------------------------------------
+// Given an array of interpolation points p with n points, the following
+// statement will specify a new FC mapping:
+//   interpolate(p, p + n - 1, filter.fc_plotter(), 1.0);
+// Note that the x range of the interpolation points *must* be [0, 2047],
+// and that additional end points *must* be present since the end points
+// are not interpolated.
+// ----------------------------------------------------------------------------
+/*
+PointPlotter<sound_sample> Filter::fc_plotter()
+{
+  return PointPlotter<sound_sample>(f0);
+}
+*/
diff --git a/MCUME_pico2/pico64/reSID/filter.h b/MCUME_pico2/pico64/reSID/filter.h
new file mode 100755
index 0000000..0d87c63
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/filter.h
@@ -0,0 +1,533 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __FILTER_H__
+#define __FILTER_H__
+
+#include "siddefs.h"
+//#include "spline.h"
+#include "filter6581.h"
+
+// ----------------------------------------------------------------------------
+// The SID filter is modeled with a two-integrator-loop biquadratic filter,
+// which has been confirmed by Bob Yannes to be the actual circuit used in
+// the SID chip.
+//
+// Measurements show that excellent emulation of the SID filter is achieved,
+// except when high resonance is combined with high sustain levels.
+// In this case the SID op-amps are performing less than ideally and are
+// causing some peculiar behavior of the SID filter. This however seems to
+// have more effect on the overall amplitude than on the color of the sound.
+//
+// The theory for the filter circuit can be found in "Microelectric Circuits"
+// by Adel S. Sedra and Kenneth C. Smith.
+// The circuit is modeled based on the explanation found there except that
+// an additional inverter is used in the feedback from the bandpass output,
+// allowing the summer op-amp to operate in single-ended mode. This yields
+// inverted filter outputs with levels independent of Q, which corresponds with
+// the results obtained from a real SID.
+//
+// We have been able to model the summer and the two integrators of the circuit
+// to form components of an IIR filter.
+// Vhp is the output of the summer, Vbp is the output of the first integrator,
+// and Vlp is the output of the second integrator in the filter circuit.
+//
+// According to Bob Yannes, the active stages of the SID filter are not really
+// op-amps. Rather, simple NMOS inverters are used. By biasing an inverter
+// into its region of quasi-linear operation using a feedback resistor from
+// input to output, a MOS inverter can be made to act like an op-amp for
+// small signals centered around the switching threshold.
+//
+// Qualified guesses at SID filter schematics are depicted below.
+//
+// SID filter
+// ----------
+// 
+//     -----------------------------------------------
+//    |                                               |
+//    |            ---Rq--                            |
+//    |           |       |                           |
+//    |  ------------<A]-----R1---------              |
+//    | |                               |             |
+//    | |                        ---C---|      ---C---|
+//    | |                       |       |     |       |
+//    |  --R1--    ---R1--      |---Rs--|     |---Rs--| 
+//    |        |  |       |     |       |     |       |
+//     ----R1--|-----[A>--|--R-----[A>--|--R-----[A>--|
+//             |          |             |             |
+// vi -----R1--           |             |             |
+// 
+//                       vhp           vbp           vlp
+// 
+// 
+// vi  - input voltage
+// vhp - highpass output
+// vbp - bandpass output
+// vlp - lowpass output
+// [A> - op-amp
+// R1  - summer resistor
+// Rq  - resistor array controlling resonance (4 resistors)
+// R   - NMOS FET voltage controlled resistor controlling cutoff frequency
+// Rs  - shunt resitor
+// C   - capacitor
+// 
+// 
+// 
+// SID integrator
+// --------------
+// 
+//                                   V+
+// 
+//                                   |
+//                                   |
+//                              -----|
+//                             |     |
+//                             | ||--
+//                              -||
+//                   ---C---     ||->
+//                  |       |        |
+//                  |---Rs-----------|---- vo
+//                  |                |
+//                  |            ||--
+// vi ----     -----|------------||
+//        |   ^     |            ||->
+//        |___|     |                |
+//        -----     |                |
+//          |       |                |
+//          |---R2--                 |
+//          |
+//          R1                       V-
+//          |
+//          |
+// 
+//          Vw
+//
+// ----------------------------------------------------------------------------
+class RESID_API Filter
+{
+public:
+  Filter();
+
+  void enable_filter(bool enable);
+  void set_chip_model(chip_model model);
+
+  RESID_INLINE
+  void clock(sound_sample voice1, sound_sample voice2, sound_sample voice3,
+	     sound_sample ext_in);
+  RESID_INLINE
+  void clock(cycle_count delta_t,
+  	     sound_sample voice1, sound_sample voice2, sound_sample voice3,
+	     sound_sample ext_in);
+  void reset();
+
+  // Write registers.
+  void writeFC_LO(reg8);
+  void writeFC_HI(reg8);
+  void writeRES_FILT(reg8);
+  void writeMODE_VOL(reg8);
+
+  // SID audio output (16 bits).
+  sound_sample output();
+
+  // Spline functions.
+  //void fc_default(const fc_point*& points, int& count);
+  //PointPlotter<sound_sample> fc_plotter();
+
+protected:
+  void set_w0();
+  void set_Q();
+
+  // Filter enabled.
+  bool enabled;
+
+  // Filter cutoff frequency.
+  reg12 fc;
+
+  // Filter resonance.
+  reg8 res;
+
+  // Selects which inputs to route through filter.
+  reg8 filt;
+
+  // Switch voice 3 off.
+  reg8 voice3off;
+
+  // Highpass, bandpass, and lowpass filter modes.
+  reg8 hp_bp_lp;
+
+  // Output master volume.
+  reg4 vol;
+
+  // Mixer DC offset.
+  sound_sample mixer_DC;
+
+  // State of filter.
+  sound_sample Vhp; // highpass
+  sound_sample Vbp; // bandpass
+  sound_sample Vlp; // lowpass
+  sound_sample Vnf; // not filtered
+
+  // Cutoff frequency, resonance.
+  sound_sample w0, w0_ceil_1, w0_ceil_dt;
+  sound_sample _1024_div_Q;
+
+  // Cutoff frequency tables.
+  // FC is an 11 bit register.
+  //sound_sample f0_6581[2048];
+  //sound_sample f0_8580[2048];
+  //sound_sample* f0;
+  const short* f0 = filter6581;
+  //static fc_point f0_points_6581[];
+  //static fc_point f0_points_8580[];
+  //fc_point* f0_points;
+  //int f0_count;
+
+friend class SID;
+};
+
+
+// ----------------------------------------------------------------------------
+// Inline functions.
+// The following functions are defined inline because they are called every
+// time a sample is calculated.
+// ----------------------------------------------------------------------------
+
+#if RESID_INLINING || defined(__FILTER_CC__)
+
+// ----------------------------------------------------------------------------
+// SID clocking - 1 cycle.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void Filter::clock(sound_sample voice1,
+		   sound_sample voice2,
+		   sound_sample voice3,
+		   sound_sample ext_in)
+{
+  // Scale each voice down from 20 to 13 bits.
+  voice1 >>= 7;
+  voice2 >>= 7;
+
+  // NB! Voice 3 is not silenced by voice3off if it is routed through
+  // the filter.
+  if (voice3off && !(filt & 0x04)) {
+    voice3 = 0;
+  }
+  else {
+    voice3 >>= 7;
+  }
+
+  ext_in >>= 7;
+
+  // This is handy for testing.
+  if (!enabled) {
+    Vnf = voice1 + voice2 + voice3 + ext_in;
+    Vhp = Vbp = Vlp = 0;
+    return;
+  }
+
+  // Route voices into or around filter.
+  // The code below is expanded to a switch for faster execution.
+  // (filt1 ? Vi : Vnf) += voice1;
+  // (filt2 ? Vi : Vnf) += voice2;
+  // (filt3 ? Vi : Vnf) += voice3;
+
+  sound_sample Vi;
+
+  switch (filt) {
+  default:
+  case 0x0:
+    Vi = 0;
+    Vnf = voice1 + voice2 + voice3 + ext_in;
+    break;
+  case 0x1:
+    Vi = voice1;
+    Vnf = voice2 + voice3 + ext_in;
+    break;
+  case 0x2:
+    Vi = voice2;
+    Vnf = voice1 + voice3 + ext_in;
+    break;
+  case 0x3:
+    Vi = voice1 + voice2;
+    Vnf = voice3 + ext_in;
+    break;
+  case 0x4:
+    Vi = voice3;
+    Vnf = voice1 + voice2 + ext_in;
+    break;
+  case 0x5:
+    Vi = voice1 + voice3;
+    Vnf = voice2 + ext_in;
+    break;
+  case 0x6:
+    Vi = voice2 + voice3;
+    Vnf = voice1 + ext_in;
+    break;
+  case 0x7:
+    Vi = voice1 + voice2 + voice3;
+    Vnf = ext_in;
+    break;
+  case 0x8:
+    Vi = ext_in;
+    Vnf = voice1 + voice2 + voice3;
+    break;
+  case 0x9:
+    Vi = voice1 + ext_in;
+    Vnf = voice2 + voice3;
+    break;
+  case 0xa:
+    Vi = voice2 + ext_in;
+    Vnf = voice1 + voice3;
+    break;
+  case 0xb:
+    Vi = voice1 + voice2 + ext_in;
+    Vnf = voice3;
+    break;
+  case 0xc:
+    Vi = voice3 + ext_in;
+    Vnf = voice1 + voice2;
+    break;
+  case 0xd:
+    Vi = voice1 + voice3 + ext_in;
+    Vnf = voice2;
+    break;
+  case 0xe:
+    Vi = voice2 + voice3 + ext_in;
+    Vnf = voice1;
+    break;
+  case 0xf:
+    Vi = voice1 + voice2 + voice3 + ext_in;
+    Vnf = 0;
+    break;
+  }
+    
+  // delta_t = 1 is converted to seconds given a 1MHz clock by dividing
+  // with 1 000 000.
+
+  // Calculate filter outputs.
+  // Vhp = Vbp/Q - Vlp - Vi;
+  // dVbp = -w0*Vhp*dt;
+  // dVlp = -w0*Vbp*dt;
+
+  sound_sample dVbp = (w0_ceil_1*Vhp >> 20);
+  sound_sample dVlp = (w0_ceil_1*Vbp >> 20);
+  Vbp -= dVbp;
+  Vlp -= dVlp;
+  Vhp = (Vbp*_1024_div_Q >> 10) - Vlp - Vi;
+}
+
+// ----------------------------------------------------------------------------
+// SID clocking - delta_t cycles.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void Filter::clock(cycle_count delta_t,
+		   sound_sample voice1,
+		   sound_sample voice2,
+		   sound_sample voice3,
+		   sound_sample ext_in)
+{
+  // Scale each voice down from 20 to 13 bits.
+  voice1 >>= 7;
+  voice2 >>= 7;
+
+  // NB! Voice 3 is not silenced by voice3off if it is routed through
+  // the filter.
+  if (voice3off && !(filt & 0x04)) {
+    voice3 = 0;
+  }
+  else {
+    voice3 >>= 7;
+  }
+
+  ext_in >>= 7;
+
+  // Enable filter on/off.
+  // This is not really part of SID, but is useful for testing.
+  // On slow CPUs it may be necessary to bypass the filter to lower the CPU
+  // load.
+  if (!enabled) {
+    Vnf = voice1 + voice2 + voice3 + ext_in;
+    Vhp = Vbp = Vlp = 0;
+    return;
+  }
+
+  // Route voices into or around filter.
+  // The code below is expanded to a switch for faster execution.
+  // (filt1 ? Vi : Vnf) += voice1;
+  // (filt2 ? Vi : Vnf) += voice2;
+  // (filt3 ? Vi : Vnf) += voice3;
+
+  sound_sample Vi;
+
+  switch (filt) {
+  default:
+  case 0x0:
+    Vi = 0;
+    Vnf = voice1 + voice2 + voice3 + ext_in;
+    break;
+  case 0x1:
+    Vi = voice1;
+    Vnf = voice2 + voice3 + ext_in;
+    break;
+  case 0x2:
+    Vi = voice2;
+    Vnf = voice1 + voice3 + ext_in;
+    break;
+  case 0x3:
+    Vi = voice1 + voice2;
+    Vnf = voice3 + ext_in;
+    break;
+  case 0x4:
+    Vi = voice3;
+    Vnf = voice1 + voice2 + ext_in;
+    break;
+  case 0x5:
+    Vi = voice1 + voice3;
+    Vnf = voice2 + ext_in;
+    break;
+  case 0x6:
+    Vi = voice2 + voice3;
+    Vnf = voice1 + ext_in;
+    break;
+  case 0x7:
+    Vi = voice1 + voice2 + voice3;
+    Vnf = ext_in;
+    break;
+  case 0x8:
+    Vi = ext_in;
+    Vnf = voice1 + voice2 + voice3;
+    break;
+  case 0x9:
+    Vi = voice1 + ext_in;
+    Vnf = voice2 + voice3;
+    break;
+  case 0xa:
+    Vi = voice2 + ext_in;
+    Vnf = voice1 + voice3;
+    break;
+  case 0xb:
+    Vi = voice1 + voice2 + ext_in;
+    Vnf = voice3;
+    break;
+  case 0xc:
+    Vi = voice3 + ext_in;
+    Vnf = voice1 + voice2;
+    break;
+  case 0xd:
+    Vi = voice1 + voice3 + ext_in;
+    Vnf = voice2;
+    break;
+  case 0xe:
+    Vi = voice2 + voice3 + ext_in;
+    Vnf = voice1;
+    break;
+  case 0xf:
+    Vi = voice1 + voice2 + voice3 + ext_in;
+    Vnf = 0;
+    break;
+  }
+
+  // Maximum delta cycles for the filter to work satisfactorily under current
+  // cutoff frequency and resonance constraints is approximately 8.
+  cycle_count delta_t_flt = 8;
+
+  while (delta_t) {
+    if (delta_t < delta_t_flt) {
+      delta_t_flt = delta_t;
+    }
+
+    // delta_t is converted to seconds given a 1MHz clock by dividing
+    // with 1 000 000. This is done in two operations to avoid integer
+    // multiplication overflow.
+
+    // Calculate filter outputs.
+    // Vhp = Vbp/Q - Vlp - Vi;
+    // dVbp = -w0*Vhp*dt;
+    // dVlp = -w0*Vbp*dt;
+    sound_sample w0_delta_t = w0_ceil_dt*delta_t_flt >> 6;
+
+    sound_sample dVbp = (w0_delta_t*Vhp >> 14);
+    sound_sample dVlp = (w0_delta_t*Vbp >> 14);
+    Vbp -= dVbp;
+    Vlp -= dVlp;
+    Vhp = (Vbp*_1024_div_Q >> 10) - Vlp - Vi;
+
+    delta_t -= delta_t_flt;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// SID audio output (20 bits).
+// ----------------------------------------------------------------------------
+RESID_INLINE
+sound_sample Filter::output()
+{
+  // This is handy for testing.
+  if (!enabled) {
+    return (Vnf + mixer_DC)*static_cast<sound_sample>(vol);
+  }
+
+  // Mix highpass, bandpass, and lowpass outputs. The sum is not
+  // weighted, this can be confirmed by sampling sound output for
+  // e.g. bandpass, lowpass, and bandpass+lowpass from a SID chip.
+
+  // The code below is expanded to a switch for faster execution.
+  // if (hp) Vf += Vhp;
+  // if (bp) Vf += Vbp;
+  // if (lp) Vf += Vlp;
+
+  sound_sample Vf;
+
+  switch (hp_bp_lp) {
+  default:
+  case 0x0:
+    Vf = 0;
+    break;
+  case 0x1:
+    Vf = Vlp;
+    break;
+  case 0x2:
+    Vf = Vbp;
+    break;
+  case 0x3:
+    Vf = Vlp + Vbp;
+    break;
+  case 0x4:
+    Vf = Vhp;
+    break;
+  case 0x5:
+    Vf = Vlp + Vhp;
+    break;
+  case 0x6:
+    Vf = Vbp + Vhp;
+    break;
+  case 0x7:
+    Vf = Vlp + Vbp + Vhp;
+    break;
+  }
+
+  // Sum non-filtered and filtered output.
+  // Multiply the sum with volume.
+  return (Vnf + Vf + mixer_DC)*static_cast<sound_sample>(vol);
+}
+
+#endif // RESID_INLINING || defined(__FILTER_CC__)
+
+#endif // not __FILTER_H__
diff --git a/MCUME_pico2/pico64/reSID/filter6581.h b/MCUME_pico2/pico64/reSID/filter6581.h
new file mode 100755
index 0000000..2f7f796
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/filter6581.h
@@ -0,0 +1,131 @@
+
+const short filter6581[] = {
+0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 0x00DC, 
+0x00DC, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 0x00DD, 
+0x00DD, 0x00DD, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 0x00DE, 
+0x00DE, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 0x00DF, 
+0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E0, 0x00E1, 0x00E1, 0x00E1, 
+0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E1, 0x00E2, 0x00E2, 0x00E2, 0x00E2, 0x00E2, 0x00E2, 0x00E2, 
+0x00E2, 0x00E2, 0x00E2, 0x00E2, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E3, 0x00E4, 0x00E4, 
+0x00E4, 0x00E4, 0x00E4, 0x00E4, 0x00E4, 0x00E4, 0x00E4, 0x00E4, 0x00E5, 0x00E5, 0x00E5, 0x00E5, 0x00E5, 0x00E5, 0x00E5, 0x00E5, 
+0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E6, 0x00E7, 0x00E7, 0x00E7, 0x00E7, 0x00E7, 0x00E7, 0x00E7, 
+0x00E7, 0x00E7, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E8, 0x00E9, 0x00E9, 0x00E9, 0x00E9, 0x00E9, 
+0x00E9, 0x00E9, 0x00E9, 0x00E9, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EA, 0x00EB, 0x00EB, 0x00EB, 
+0x00EB, 0x00EB, 0x00EB, 0x00EB, 0x00EB, 0x00EC, 0x00EC, 0x00EC, 0x00EC, 0x00EC, 0x00EC, 0x00EC, 0x00EC, 0x00ED, 0x00ED, 0x00ED, 
+0x00ED, 0x00ED, 0x00ED, 0x00ED, 0x00EE, 0x00EE, 0x00EE, 0x00EE, 0x00EE, 0x00EE, 0x00EE, 0x00EF, 0x00EF, 0x00EF, 0x00EF, 0x00EF, 
+0x00EF, 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F1, 0x00F1, 0x00F1, 0x00F1, 0x00F1, 0x00F1, 0x00F2, 0x00F2, 0x00F2, 
+0x00F2, 0x00F2, 0x00F3, 0x00F3, 0x00F3, 0x00F3, 0x00F3, 0x00F4, 0x00F4, 0x00F4, 0x00F4, 0x00F4, 0x00F5, 0x00F5, 0x00F5, 0x00F5, 
+0x00F5, 0x00F6, 0x00F6, 0x00F6, 0x00F6, 0x00F7, 0x00F7, 0x00F7, 0x00F7, 0x00F8, 0x00F8, 0x00F8, 0x00F8, 0x00F9, 0x00F9, 0x00F9, 
+0x00FA, 0x00FA, 0x00FA, 0x00FA, 0x00FB, 0x00FB, 0x00FB, 0x00FB, 0x00FC, 0x00FC, 0x00FC, 0x00FC, 0x00FD, 0x00FD, 0x00FD, 0x00FE, 
+0x00FE, 0x00FE, 0x00FE, 0x00FF, 0x00FF, 0x00FF, 0x00FF, 0x0100, 0x0100, 0x0100, 0x0101, 0x0101, 0x0101, 0x0101, 0x0102, 0x0102, 
+0x0102, 0x0103, 0x0103, 0x0103, 0x0103, 0x0104, 0x0104, 0x0104, 0x0105, 0x0105, 0x0105, 0x0105, 0x0106, 0x0106, 0x0106, 0x0107, 
+0x0107, 0x0107, 0x0108, 0x0108, 0x0108, 0x0109, 0x0109, 0x0109, 0x010A, 0x010A, 0x010A, 0x010B, 0x010B, 0x010B, 0x010C, 0x010C, 
+0x010C, 0x010D, 0x010D, 0x010D, 0x010E, 0x010E, 0x010E, 0x010F, 0x010F, 0x0110, 0x0110, 0x0110, 0x0111, 0x0111, 0x0111, 0x0112, 
+0x0112, 0x0113, 0x0113, 0x0114, 0x0114, 0x0114, 0x0115, 0x0115, 0x0116, 0x0116, 0x0117, 0x0117, 0x0117, 0x0118, 0x0118, 0x0119, 
+0x0119, 0x011A, 0x011A, 0x011B, 0x011B, 0x011C, 0x011C, 0x011D, 0x011D, 0x011E, 0x011E, 0x011F, 0x011F, 0x0120, 0x0121, 0x0121, 
+0x0122, 0x0122, 0x0123, 0x0123, 0x0124, 0x0125, 0x0125, 0x0126, 0x0126, 0x0127, 0x0128, 0x0128, 0x0129, 0x012A, 0x012A, 0x012B, 
+0x012C, 0x012C, 0x012D, 0x012D, 0x012E, 0x012F, 0x012F, 0x0130, 0x0131, 0x0131, 0x0132, 0x0132, 0x0133, 0x0134, 0x0134, 0x0135, 
+0x0136, 0x0136, 0x0137, 0x0137, 0x0138, 0x0138, 0x0139, 0x013A, 0x013A, 0x013B, 0x013B, 0x013C, 0x013D, 0x013D, 0x013E, 0x013E, 
+0x013F, 0x0140, 0x0140, 0x0141, 0x0141, 0x0142, 0x0143, 0x0143, 0x0144, 0x0144, 0x0145, 0x0146, 0x0146, 0x0147, 0x0148, 0x0148, 
+0x0149, 0x0149, 0x014A, 0x014B, 0x014B, 0x014C, 0x014D, 0x014E, 0x014E, 0x014F, 0x0150, 0x0150, 0x0151, 0x0152, 0x0153, 0x0153, 
+0x0154, 0x0155, 0x0156, 0x0156, 0x0157, 0x0158, 0x0159, 0x015A, 0x015B, 0x015B, 0x015C, 0x015D, 0x015E, 0x015F, 0x0160, 0x0161, 
+0x0162, 0x0163, 0x0164, 0x0165, 0x0166, 0x0167, 0x0168, 0x0169, 0x016A, 0x016B, 0x016C, 0x016D, 0x016E, 0x016F, 0x0171, 0x0172, 
+0x0173, 0x0174, 0x0175, 0x0177, 0x0178, 0x0179, 0x017A, 0x017C, 0x017D, 0x017F, 0x0180, 0x0181, 0x0183, 0x0184, 0x0186, 0x0187, 
+0x0189, 0x018A, 0x018C, 0x018D, 0x018F, 0x0190, 0x0192, 0x0194, 0x0195, 0x0197, 0x0199, 0x019A, 0x019C, 0x019E, 0x01A0, 0x01A2, 
+0x01A4, 0x01A5, 0x01A7, 0x01A9, 0x01AB, 0x01AD, 0x01AF, 0x01B1, 0x01B3, 0x01B4, 0x01B6, 0x01B8, 0x01BA, 0x01BC, 0x01BE, 0x01C0, 
+0x01C2, 0x01C4, 0x01C6, 0x01C8, 0x01CA, 0x01CC, 0x01CE, 0x01D0, 0x01D2, 0x01D4, 0x01D6, 0x01D8, 0x01DA, 0x01DC, 0x01DE, 0x01E0, 
+0x01E2, 0x01E4, 0x01E6, 0x01E8, 0x01EA, 0x01EC, 0x01EF, 0x01F1, 0x01F3, 0x01F5, 0x01F7, 0x01F9, 0x01FC, 0x01FE, 0x0200, 0x0202, 
+0x0205, 0x0207, 0x0209, 0x020C, 0x020E, 0x0210, 0x0213, 0x0215, 0x0218, 0x021A, 0x021D, 0x021F, 0x0222, 0x0224, 0x0227, 0x0229, 
+0x022C, 0x022E, 0x0231, 0x0234, 0x0236, 0x0239, 0x023C, 0x023E, 0x0241, 0x0244, 0x0247, 0x024A, 0x024D, 0x024F, 0x0252, 0x0255, 
+0x0258, 0x025B, 0x025E, 0x0261, 0x0264, 0x0267, 0x026B, 0x026E, 0x0271, 0x0274, 0x0277, 0x027B, 0x027E, 0x0281, 0x0285, 0x0288, 
+0x028C, 0x028F, 0x0292, 0x0296, 0x029A, 0x029D, 0x02A1, 0x02A4, 0x02A8, 0x02AC, 0x02B0, 0x02B3, 0x02B7, 0x02BB, 0x02BF, 0x02C3, 
+0x02C7, 0x02CB, 0x02CF, 0x02D3, 0x02D7, 0x02DB, 0x02DF, 0x02E4, 0x02E8, 0x02EC, 0x02F1, 0x02F5, 0x02F9, 0x02FE, 0x0302, 0x0307, 
+0x030C, 0x0310, 0x0315, 0x0319, 0x031E, 0x0323, 0x0328, 0x032D, 0x0331, 0x0336, 0x033B, 0x0340, 0x0345, 0x034A, 0x034F, 0x0354, 
+0x0359, 0x035E, 0x0364, 0x0369, 0x036E, 0x0373, 0x0379, 0x037E, 0x0383, 0x0389, 0x038E, 0x0393, 0x0399, 0x039E, 0x03A4, 0x03AA, 
+0x03AF, 0x03B5, 0x03BA, 0x03C0, 0x03C6, 0x03CB, 0x03D1, 0x03D7, 0x03DD, 0x03E3, 0x03E9, 0x03EE, 0x03F4, 0x03FA, 0x0400, 0x0406, 
+0x040C, 0x0412, 0x0418, 0x041F, 0x0425, 0x042B, 0x0431, 0x0437, 0x043E, 0x0444, 0x044A, 0x0451, 0x0457, 0x045D, 0x0464, 0x046A, 
+0x0471, 0x0477, 0x047E, 0x0484, 0x048B, 0x0491, 0x0498, 0x049F, 0x04A5, 0x04AC, 0x04B3, 0x04B9, 0x04C0, 0x04C7, 0x04CE, 0x04D5, 
+0x04DB, 0x04E2, 0x04E9, 0x04F0, 0x04F7, 0x04FE, 0x0505, 0x050C, 0x0513, 0x051A, 0x0521, 0x0529, 0x0530, 0x0537, 0x053E, 0x0545, 
+0x054D, 0x0554, 0x055B, 0x0562, 0x056A, 0x0571, 0x0578, 0x0580, 0x0587, 0x058F, 0x0596, 0x059E, 0x05A5, 0x05AD, 0x05B4, 0x05BC, 
+0x05C3, 0x05CB, 0x05D3, 0x05DA, 0x05E2, 0x05EA, 0x05F1, 0x05F9, 0x0601, 0x0609, 0x0610, 0x0618, 0x0620, 0x0628, 0x0630, 0x0638, 
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+0x4524, 0x4527, 0x452B, 0x452E, 0x4531, 0x4535, 0x4538, 0x453C, 0x453F, 0x4542, 0x4545, 0x4549, 0x454C, 0x454F, 0x4552, 0x4555, 
+0x4559, 0x455C, 0x455F, 0x4562, 0x4565, 0x4568, 0x456B, 0x456E, 0x4571, 0x4574, 0x4577, 0x4579, 0x457C, 0x457F, 0x4582, 0x4585, 
+0x4588, 0x458A, 0x458D, 0x4590, 0x4592, 0x4595, 0x4598, 0x459A, 0x459D, 0x45A0, 0x45A2, 0x45A5, 0x45A7, 0x45AA, 0x45AC, 0x45AF, 
+0x45B1, 0x45B4, 0x45B6, 0x45B8, 0x45BB, 0x45BD, 0x45C0, 0x45C2, 0x45C4, 0x45C7, 0x45C9, 0x45CB, 0x45CD, 0x45D0, 0x45D2, 0x45D4, 
+0x45D6, 0x45D9, 0x45DB, 0x45DD, 0x45DF, 0x45E1, 0x45E3, 0x45E6, 0x45E8, 0x45EA, 0x45EC, 0x45EE, 0x45F0, 0x45F2, 0x45F4, 0x45F6, 
+0x45F8, 0x45FA, 0x45FC, 0x45FE, 0x4600, 0x4602, 0x4604, 0x4606, 0x4608, 0x460A, 0x460C, 0x460E, 0x4610, 0x4612, 0x4614, 0x4615, 
+0x4617, 0x4619, 0x461B, 0x461D, 0x461F, 0x4621, 0x4622, 0x4624, 0x4626, 0x4628, 0x462A, 0x462C, 0x462D, 0x462F, 0x4631, 0x4633, 
+0x4635, 0x4637, 0x4638, 0x463A, 0x463C, 0x463E, 0x463F, 0x4641, 0x4643, 0x4645, 0x4647, 0x4648, 0x464A, 0x464C, 0x464E, 0x464F, 
+};
diff --git a/MCUME_pico2/pico64/reSID/pot.cc b/MCUME_pico2/pico64/reSID/pot.cc
new file mode 100755
index 0000000..b60b2ec
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/pot.cc
@@ -0,0 +1,26 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "pot.h"
+
+reg8 Potentiometer::readPOT()
+{
+  // NB! Not modeled.
+  return 0xff;
+}
diff --git a/MCUME_pico2/pico64/reSID/pot.h b/MCUME_pico2/pico64/reSID/pot.h
new file mode 100755
index 0000000..9156729
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/pot.h
@@ -0,0 +1,31 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __POT_H__
+#define __POT_H__
+
+#include "siddefs.h"
+
+class RESID_API Potentiometer
+{
+public:
+  reg8 readPOT();
+};
+
+#endif
diff --git a/MCUME_pico2/pico64/reSID/sid.cc b/MCUME_pico2/pico64/reSID/sid.cc
new file mode 100755
index 0000000..8f58baa
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/sid.cc
@@ -0,0 +1,1023 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "sid.h"
+#include <math.h>
+// JMH adapted hyperpetpico  
+#include "platform_config.h"
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+SID::SID()
+{
+  // Initialize pointers.
+  sample = 0;
+  fir = 0;
+
+  voice[0].set_sync_source(&voice[2]);
+  voice[1].set_sync_source(&voice[0]);
+  voice[2].set_sync_source(&voice[1]);
+
+  set_sampling_parameters(985248, SAMPLE_FAST, 44100);
+
+  bus_value = 0;
+  bus_value_ttl = 0;
+
+  ext_in = 0;
+}
+
+
+// ----------------------------------------------------------------------------
+// Destructor.
+// ----------------------------------------------------------------------------
+SID::~SID()
+{
+  delete[] sample;
+  delete[] fir;
+}
+
+
+// ----------------------------------------------------------------------------
+// Set chip model.
+// ----------------------------------------------------------------------------
+/*
+void SID::set_chip_model(chip_model model)
+{
+  for (int i = 0; i < 3; i++) {
+    voice[i].set_chip_model(model);
+  }
+
+  filter.set_chip_model(model);
+  extfilt.set_chip_model(model);
+}
+*/
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void SID::reset()
+{
+  for (int i = 0; i < 3; i++) {
+    voice[i].reset();
+  }
+  filter.reset();
+  extfilt.reset();
+
+  bus_value = 0;
+  bus_value_ttl = 0;
+}
+
+
+// ----------------------------------------------------------------------------
+// Write 16-bit sample to audio input.
+// NB! The caller is responsible for keeping the value within 16 bits.
+// Note that to mix in an external audio signal, the signal should be
+// resampled to 1MHz first to avoid sampling noise.
+// ----------------------------------------------------------------------------
+void SID::input(int sample)
+{
+  // Voice outputs are 20 bits. Scale up to match three voices in order
+  // to facilitate simulation of the MOS8580 "digi boost" hardware hack.
+  ext_in = (sample << 4)*3;
+}
+
+// ----------------------------------------------------------------------------
+// Read sample from audio output.
+// Both 16-bit and n-bit output is provided.
+// ----------------------------------------------------------------------------
+int SID::output()
+{
+// JMH adapted hyperpetpico  
+//  const int range = 1 << 16;
+  const int range = 1 << 8;
+  const int half = range >> 1;
+  int sample = extfilt.output()/((4095*255 >> 7)*3*15*2/range);
+  if (sample >= half) {
+    return half - 1;
+  }
+  if (sample < -half) {
+    return -half;
+  }
+  return sample;
+}
+
+int SID::output(int bits)
+{
+  const int range = 1 << bits;
+  const int half = range >> 1;
+  int sample = extfilt.output()/((4095*255 >> 7)*3*15*2/range);
+  if (sample >= half) {
+    return half - 1;
+  }
+  if (sample < -half) {
+    return -half;
+  }
+  return sample;
+}
+
+
+// ----------------------------------------------------------------------------
+// Read registers.
+//
+// Reading a write only register returns the last byte written to any SID
+// register. The individual bits in this value start to fade down towards
+// zero after a few cycles. All bits reach zero within approximately
+// $2000 - $4000 cycles.
+// It has been claimed that this fading happens in an orderly fashion, however
+// sampling of write only registers reveals that this is not the case.
+// NB! This is not correctly modeled.
+// The actual use of write only registers has largely been made in the belief
+// that all SID registers are readable. To support this belief the read
+// would have to be done immediately after a write to the same register
+// (remember that an intermediate write to another register would yield that
+// value instead). With this in mind we return the last value written to
+// any SID register for $2000 cycles without modeling the bit fading.
+// ----------------------------------------------------------------------------
+reg8 SID::read(reg8 offset)
+{
+  switch (offset) {
+  case 0x19:
+    return potx.readPOT();
+  case 0x1a:
+    return poty.readPOT();
+  case 0x1b:
+    return voice[2].wave.readOSC();
+  case 0x1c:
+    return voice[2].envelope.readENV();
+  default:
+    return bus_value;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Write registers.
+// ----------------------------------------------------------------------------
+void SID::write(reg8 offset, reg8 value)
+{
+  bus_value = value;
+  bus_value_ttl = 0x2000;
+
+  switch (offset) {
+  case 0x00:
+    voice[0].wave.writeFREQ_LO(value);
+    break;
+  case 0x01:
+    voice[0].wave.writeFREQ_HI(value);
+    break;
+  case 0x02:
+    voice[0].wave.writePW_LO(value);
+    break;
+  case 0x03:
+    voice[0].wave.writePW_HI(value);
+    break;
+  case 0x04:
+    voice[0].writeCONTROL_REG(value);
+    break;
+  case 0x05:
+    voice[0].envelope.writeATTACK_DECAY(value);
+    break;
+  case 0x06:
+    voice[0].envelope.writeSUSTAIN_RELEASE(value);
+    break;
+  case 0x07:
+    voice[1].wave.writeFREQ_LO(value);
+    break;
+  case 0x08:
+    voice[1].wave.writeFREQ_HI(value);
+    break;
+  case 0x09:
+    voice[1].wave.writePW_LO(value);
+    break;
+  case 0x0a:
+    voice[1].wave.writePW_HI(value);
+    break;
+  case 0x0b:
+    voice[1].writeCONTROL_REG(value);
+    break;
+  case 0x0c:
+    voice[1].envelope.writeATTACK_DECAY(value);
+    break;
+  case 0x0d:
+    voice[1].envelope.writeSUSTAIN_RELEASE(value);
+    break;
+  case 0x0e:
+    voice[2].wave.writeFREQ_LO(value);
+    break;
+  case 0x0f:
+    voice[2].wave.writeFREQ_HI(value);
+    break;
+  case 0x10:
+    voice[2].wave.writePW_LO(value);
+    break;
+  case 0x11:
+    voice[2].wave.writePW_HI(value);
+    break;
+  case 0x12:
+    voice[2].writeCONTROL_REG(value);
+    break;
+  case 0x13:
+    voice[2].envelope.writeATTACK_DECAY(value);
+    break;
+  case 0x14:
+    voice[2].envelope.writeSUSTAIN_RELEASE(value);
+    break;
+  case 0x15:
+    filter.writeFC_LO(value);
+    break;
+  case 0x16:
+    filter.writeFC_HI(value);
+    break;
+  case 0x17:
+    filter.writeRES_FILT(value);
+    break;
+  case 0x18:
+    filter.writeMODE_VOL(value);
+    break;
+  default:
+    break;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+SID::State::State()
+{
+  int i;
+
+  for (i = 0; i < 0x20; i++) {
+    sid_register[i] = 0;
+  }
+
+  bus_value = 0;
+  bus_value_ttl = 0;
+
+  for (i = 0; i < 3; i++) {
+    accumulator[i] = 0;
+    shift_register[i] = 0x7ffff8;
+    rate_counter[i] = 0;
+    rate_counter_period[i] = 9;
+    exponential_counter[i] = 0;
+    exponential_counter_period[i] = 1;
+    envelope_counter[i] = 0;
+    envelope_state[i] = EnvelopeGenerator::RELEASE;
+    hold_zero[i] = true;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Read state.
+// ----------------------------------------------------------------------------
+SID::State SID::read_state()
+{
+  State state;
+  int i, j;
+
+  for (i = 0, j = 0; i < 3; i++, j += 7) {
+    WaveformGenerator& wave = voice[i].wave;
+    EnvelopeGenerator& envelope = voice[i].envelope;
+    state.sid_register[j + 0] = wave.freq & 0xff;
+    state.sid_register[j + 1] = wave.freq >> 8;
+    state.sid_register[j + 2] = wave.pw & 0xff;
+    state.sid_register[j + 3] = wave.pw >> 8;
+    state.sid_register[j + 4] =
+      (wave.waveform << 4)
+      | (wave.test ? 0x08 : 0)
+      | (wave.ring_mod ? 0x04 : 0)
+      | (wave.sync ? 0x02 : 0)
+      | (envelope.gate ? 0x01 : 0);
+    state.sid_register[j + 5] = (envelope.attack << 4) | envelope.decay;
+    state.sid_register[j + 6] = (envelope.sustain << 4) | envelope.release;
+  }
+
+  state.sid_register[j++] = filter.fc & 0x007;
+  state.sid_register[j++] = filter.fc >> 3;
+  state.sid_register[j++] = (filter.res << 4) | filter.filt;
+  state.sid_register[j++] =
+    (filter.voice3off ? 0x80 : 0)
+    | (filter.hp_bp_lp << 4)
+    | filter.vol;
+
+  // These registers are superfluous, but included for completeness.
+  for (; j < 0x1d; j++) {
+    state.sid_register[j] = read(j);
+  }
+  for (; j < 0x20; j++) {
+    state.sid_register[j] = 0;
+  }
+
+  state.bus_value = bus_value;
+  state.bus_value_ttl = bus_value_ttl;
+
+  for (i = 0; i < 3; i++) {
+    state.accumulator[i] = voice[i].wave.accumulator;
+    state.shift_register[i] = voice[i].wave.shift_register;
+    state.rate_counter[i] = voice[i].envelope.rate_counter;
+    state.rate_counter_period[i] = voice[i].envelope.rate_period;
+    state.exponential_counter[i] = voice[i].envelope.exponential_counter;
+    state.exponential_counter_period[i] = voice[i].envelope.exponential_counter_period;
+    state.envelope_counter[i] = voice[i].envelope.envelope_counter;
+    state.envelope_state[i] = voice[i].envelope.state;
+    state.hold_zero[i] = voice[i].envelope.hold_zero;
+  }
+
+  return state;
+}
+
+
+// ----------------------------------------------------------------------------
+// Write state.
+// ----------------------------------------------------------------------------
+void SID::write_state(const State& state)
+{
+  int i;
+
+  for (i = 0; i <= 0x18; i++) {
+    write(i, state.sid_register[i]);
+  }
+
+  bus_value = state.bus_value;
+  bus_value_ttl = state.bus_value_ttl;
+
+  for (i = 0; i < 3; i++) {
+    voice[i].wave.accumulator = state.accumulator[i];
+    voice[i].wave.shift_register = state.shift_register[i];
+    voice[i].envelope.rate_counter = state.rate_counter[i];
+    voice[i].envelope.rate_period = state.rate_counter_period[i];
+    voice[i].envelope.exponential_counter = state.exponential_counter[i];
+    voice[i].envelope.exponential_counter_period = state.exponential_counter_period[i];
+    voice[i].envelope.envelope_counter = state.envelope_counter[i];
+    voice[i].envelope.state = state.envelope_state[i];
+    voice[i].envelope.hold_zero = state.hold_zero[i];
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Enable filter.
+// ----------------------------------------------------------------------------
+void SID::enable_filter(bool enable)
+{
+  filter.enable_filter(enable);
+}
+
+
+// ----------------------------------------------------------------------------
+// Enable external filter.
+// ----------------------------------------------------------------------------
+void SID::enable_external_filter(bool enable)
+{
+  extfilt.enable_filter(enable);
+}
+
+
+// ----------------------------------------------------------------------------
+// I0() computes the 0th order modified Bessel function of the first kind.
+// This function is originally from resample-1.5/filterkit.c by J. O. Smith.
+// ----------------------------------------------------------------------------
+double SID::I0(double x)
+{
+  // Max error acceptable in I0.
+  const double I0e = 1e-6;
+
+  double sum, u, halfx, temp;
+  int n;
+
+  sum = u = n = 1;
+  halfx = x/2.0;
+
+  do {
+    temp = halfx/n++;
+    u *= temp*temp;
+    sum += u;
+  } while (u >= I0e*sum);
+
+  return sum;
+}
+
+
+// ----------------------------------------------------------------------------
+// Setting of SID sampling parameters.
+//
+// Use a clock freqency of 985248Hz for PAL C64, 1022730Hz for NTSC C64.
+// The default end of passband frequency is pass_freq = 0.9*sample_freq/2
+// for sample frequencies up to ~ 44.1kHz, and 20kHz for higher sample
+// frequencies.
+//
+// For resampling, the ratio between the clock frequency and the sample
+// frequency is limited as follows:
+//   125*clock_freq/sample_freq < 16384
+// E.g. provided a clock frequency of ~ 1MHz, the sample frequency can not
+// be set lower than ~ 8kHz. A lower sample frequency would make the
+// resampling code overfill its 16k sample ring buffer.
+// 
+// The end of passband frequency is also limited:
+//   pass_freq <= 0.9*sample_freq/2
+
+// E.g. for a 44.1kHz sampling rate the end of passband frequency is limited
+// to slightly below 20kHz. This constraint ensures that the FIR table is
+// not overfilled.
+// ----------------------------------------------------------------------------
+bool SID::set_sampling_parameters(double clock_freq, sampling_method method,
+				  double sample_freq, double pass_freq,
+				  double filter_scale)
+{
+  // Check resampling constraints.
+  if (method == SAMPLE_RESAMPLE_INTERPOLATE || method == SAMPLE_RESAMPLE_FAST)
+  {
+    // Check whether the sample ring buffer would overfill.
+    if (FIR_N*clock_freq/sample_freq >= RINGSIZE) {
+      return false;
+    }
+
+    // The default passband limit is 0.9*sample_freq/2 for sample
+    // frequencies below ~ 44.1kHz, and 20kHz for higher sample frequencies.
+    if (pass_freq < 0) {
+      pass_freq = 20000;
+      if (2*pass_freq/sample_freq >= 0.9) {
+	pass_freq = 0.9*sample_freq/2;
+      }
+    }
+    // Check whether the FIR table would overfill.
+    else if (pass_freq > 0.9*sample_freq/2) {
+      return false;
+    }
+
+    // The filter scaling is only included to avoid clipping, so keep
+    // it sane.
+    if (filter_scale < 0.9 || filter_scale > 1.0) {
+      return false;
+    }
+  }
+
+  clock_frequency = clock_freq;
+  sampling = method;
+
+  cycles_per_sample =
+    cycle_count(clock_freq/sample_freq*(1 << FIXP_SHIFT) + 0.5);
+
+  sample_offset = 0;
+  sample_prev = 0;
+
+  // FIR initialization is only necessary for resampling.
+  if (method != SAMPLE_RESAMPLE_INTERPOLATE && method != SAMPLE_RESAMPLE_FAST)
+  {
+    delete[] sample;
+    delete[] fir;
+    sample = 0;
+    fir = 0;
+    return true;
+  }
+
+  const double pi = 3.1415926535897932385;
+
+  // 16 bits -> -96dB stopband attenuation.
+  const double A = -20*log10(1.0/(1 << 16));
+  // A fraction of the bandwidth is allocated to the transition band,
+  double dw = (1 - 2*pass_freq/sample_freq)*pi;
+  // The cutoff frequency is midway through the transition band.
+  double wc = (2*pass_freq/sample_freq + 1)*pi/2;
+
+  // For calculation of beta and N see the reference for the kaiserord
+  // function in the MATLAB Signal Processing Toolbox:
+  // http://www.mathworks.com/access/helpdesk/help/toolbox/signal/kaiserord.html
+  const double beta = 0.1102*(A - 8.7);
+  const double I0beta = I0(beta);
+
+  // The filter order will maximally be 124 with the current constraints.
+  // N >= (96.33 - 7.95)/(2.285*0.1*pi) -> N >= 123
+  // The filter order is equal to the number of zero crossings, i.e.
+  // it should be an even number (sinc is symmetric about x = 0).
+  int N = int((A - 7.95)/(2.285*dw) + 0.5);
+  N += N & 1;
+
+  double f_samples_per_cycle = sample_freq/clock_freq;
+  double f_cycles_per_sample = clock_freq/sample_freq;
+
+  // The filter length is equal to the filter order + 1.
+  // The filter length must be an odd number (sinc is symmetric about x = 0).
+  fir_N = int(N*f_cycles_per_sample) + 1;
+  fir_N |= 1;
+
+  // We clamp the filter table resolution to 2^n, making the fixpoint
+  // sample_offset a whole multiple of the filter table resolution.
+  int res = method == SAMPLE_RESAMPLE_INTERPOLATE ?
+    FIR_RES_INTERPOLATE : FIR_RES_FAST;
+  int n = (int)ceil(log(res/f_cycles_per_sample)/log(2));
+  fir_RES = 1 << n;
+
+  // Allocate memory for FIR tables.
+  delete[] fir;
+  fir = new short[fir_N*fir_RES];
+
+  // Calculate fir_RES FIR tables for linear interpolation.
+  for (int i = 0; i < fir_RES; i++) {
+    int fir_offset = i*fir_N + fir_N/2;
+    double j_offset = double(i)/fir_RES;
+    // Calculate FIR table. This is the sinc function, weighted by the
+    // Kaiser window.
+    for (int j = -fir_N/2; j <= fir_N/2; j++) {
+      double jx = j - j_offset;
+      double wt = wc*jx/f_cycles_per_sample;
+      double temp = jx/(fir_N/2);
+      double Kaiser =
+	fabs(temp) <= 1 ? I0(beta*sqrt(1 - temp*temp))/I0beta : 0;
+      double sincwt =
+	fabs(wt) >= 1e-6 ? sin(wt)/wt : 1;
+      double val =
+	(1 << FIR_SHIFT)*filter_scale*f_samples_per_cycle*wc/pi*sincwt*Kaiser;
+      fir[fir_offset + j] = short(val + 0.5);
+    }
+  }
+
+  // Allocate sample buffer.
+  if (!sample) {
+    sample = new short[RINGSIZE*2];
+  }
+  // Clear sample buffer.
+  for (int j = 0; j < RINGSIZE*2; j++) {
+    sample[j] = 0;
+  }
+  sample_index = 0;
+
+  return true;
+}
+
+
+// ----------------------------------------------------------------------------
+// Adjustment of SID sampling frequency.
+//
+// In some applications, e.g. a C64 emulator, it can be desirable to
+// synchronize sound with a timer source. This is supported by adjustment of
+// the SID sampling frequency.
+//
+// NB! Adjustment of the sampling frequency may lead to noticeable shifts in
+// frequency, and should only be used for interactive applications. Note also
+// that any adjustment of the sampling frequency will change the
+// characteristics of the resampling filter, since the filter is not rebuilt.
+// ----------------------------------------------------------------------------
+void SID::adjust_sampling_frequency(double sample_freq)
+{
+  cycles_per_sample =
+    cycle_count(clock_frequency/sample_freq*(1 << FIXP_SHIFT) + 0.5);
+}
+
+
+// ----------------------------------------------------------------------------
+// Return array of default spline interpolation points to map FC to
+// filter cutoff frequency.
+// ----------------------------------------------------------------------------
+/*
+void SID::fc_default(const fc_point*& points, int& count)
+{
+  filter.fc_default(points, count);
+}
+*/
+
+// ----------------------------------------------------------------------------
+// Return FC spline plotter object.
+// ----------------------------------------------------------------------------
+/*
+PointPlotter<sound_sample> SID::fc_plotter()
+{
+  return filter.fc_plotter();
+}
+*/
+
+// ----------------------------------------------------------------------------
+// SID clocking - 1 cycle.
+// ----------------------------------------------------------------------------
+void SID::clock()
+{
+  int i;
+
+  // Age bus value.
+  if (--bus_value_ttl <= 0) {
+    bus_value = 0;
+    bus_value_ttl = 0;
+  }
+
+  // Clock amplitude modulators.
+  for (i = 0; i < 3; i++) {
+    voice[i].envelope.clock();
+  }
+
+  // Clock oscillators.
+  for (i = 0; i < 3; i++) {
+    voice[i].wave.clock();
+  }
+
+  // Synchronize oscillators.
+  for (i = 0; i < 3; i++) {
+    voice[i].wave.synchronize();
+  }
+
+  // Clock filter.
+  filter.clock(voice[0].output(), voice[1].output(), voice[2].output(), ext_in);
+
+  // Clock external filter.
+  extfilt.clock(filter.output());
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking - delta_t cycles.
+// ----------------------------------------------------------------------------
+void SID::clock(cycle_count delta_t)
+{
+  int i;
+
+  if (delta_t <= 0) {
+    return;
+  }
+
+  // Age bus value.
+  bus_value_ttl -= delta_t;
+  if (bus_value_ttl <= 0) {
+    bus_value = 0;
+    bus_value_ttl = 0;
+  }
+
+  // Clock amplitude modulators.
+  for (i = 0; i < 3; i++) {
+    voice[i].envelope.clock(delta_t);
+  }
+
+  // Clock and synchronize oscillators.
+  // Loop until we reach the current cycle.
+  cycle_count delta_t_osc = delta_t;
+  while (delta_t_osc) {
+    cycle_count delta_t_min = delta_t_osc;
+
+    // Find minimum number of cycles to an oscillator accumulator MSB toggle.
+    // We have to clock on each MSB on / MSB off for hard sync to operate
+    // correctly.
+    for (i = 0; i < 3; i++) {
+      WaveformGenerator& wave = voice[i].wave;
+
+      // It is only necessary to clock on the MSB of an oscillator that is
+      // a sync source and has freq != 0.
+      if (!(wave.sync_dest->sync && wave.freq)) {
+	continue;
+      }
+
+      reg16 freq = wave.freq;
+      reg24 accumulator = wave.accumulator;
+
+      // Clock on MSB off if MSB is on, clock on MSB on if MSB is off.
+      reg24 delta_accumulator =
+	(accumulator & 0x800000 ? 0x1000000 : 0x800000) - accumulator;
+
+      cycle_count delta_t_next = delta_accumulator/freq;
+      if (delta_accumulator%freq) {
+	++delta_t_next;
+      }
+
+      if (delta_t_next < delta_t_min) {
+	delta_t_min = delta_t_next;
+      }
+    }
+
+    // Clock oscillators.
+    for (i = 0; i < 3; i++) {
+      voice[i].wave.clock(delta_t_min);
+    }
+
+    // Synchronize oscillators.
+    for (i = 0; i < 3; i++) {
+      voice[i].wave.synchronize();
+    }
+
+    delta_t_osc -= delta_t_min;
+  }
+
+  // Clock filter.
+  filter.clock(delta_t,
+	       voice[0].output(), voice[1].output(), voice[2].output(), ext_in);
+
+  // Clock external filter.
+  extfilt.clock(delta_t, filter.output());
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking with audio sampling.
+// Fixpoint arithmetics is used.
+//
+// The example below shows how to clock the SID a specified amount of cycles
+// while producing audio output:
+//
+// while (delta_t) {
+//   bufindex += sid.clock(delta_t, buf + bufindex, buflength - bufindex);
+//   write(dsp, buf, bufindex*2);
+//   bufindex = 0;
+// }
+// 
+// ----------------------------------------------------------------------------
+int SID::clock(cycle_count& delta_t, short* buf, int n, int interleave)
+{
+  switch (sampling) {
+  default:
+  case SAMPLE_FAST:
+    return clock_fast(delta_t, buf, n, interleave);
+  case SAMPLE_INTERPOLATE:
+    return clock_interpolate(delta_t, buf, n, interleave);
+  case SAMPLE_RESAMPLE_INTERPOLATE:
+    return clock_resample_interpolate(delta_t, buf, n, interleave);
+  case SAMPLE_RESAMPLE_FAST:
+    return clock_resample_fast(delta_t, buf, n, interleave);
+  }
+}
+
+// ----------------------------------------------------------------------------
+// SID clocking with audio sampling - delta clocking picking nearest sample.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+int SID::clock_fast(cycle_count& delta_t, short* buf, int n,
+		    int interleave)
+{
+  int s = 0;
+#ifdef AUDIO_8BIT
+  // JMH adapted for hyperpetpico
+  unsigned char * buf8 = (unsigned char *)buf;
+#endif
+
+  for (;;) {
+    cycle_count next_sample_offset = sample_offset + cycles_per_sample + (1 << (FIXP_SHIFT - 1));
+    cycle_count delta_t_sample = next_sample_offset >> FIXP_SHIFT;
+    if (delta_t_sample > delta_t) {
+      break;
+    }
+    if (s >= n) {
+      return s;
+    }
+    clock(delta_t_sample);
+    delta_t -= delta_t_sample;
+    sample_offset = (next_sample_offset & FIXP_MASK) - (1 << (FIXP_SHIFT - 1));
+    // JMH adapted for hyperpetpico
+#ifdef AUDIO_8BIT
+    buf8[s++] = output()+128;
+#else
+    buf[s++*interleave] = output()+128;
+#endif
+  }
+
+  clock(delta_t);
+  sample_offset -= delta_t << FIXP_SHIFT;
+  delta_t = 0;
+  return s;
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking with audio sampling - cycle based with linear sample
+// interpolation.
+//
+// Here the chip is clocked every cycle. This yields higher quality
+// sound since the samples are linearly interpolated, and since the
+// external filter attenuates frequencies above 16kHz, thus reducing
+// sampling noise.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+int SID::clock_interpolate(cycle_count& delta_t, short* buf, int n,
+			   int interleave)
+{
+  int s = 0;
+  int i;
+
+  for (;;) {
+    cycle_count next_sample_offset = sample_offset + cycles_per_sample;
+    cycle_count delta_t_sample = next_sample_offset >> FIXP_SHIFT;
+    if (delta_t_sample > delta_t) {
+      break;
+    }
+    if (s >= n) {
+      return s;
+    }
+    for (i = 0; i < delta_t_sample - 1; i++) {
+      clock();
+    }
+    if (i < delta_t_sample) {
+      sample_prev = output();
+      clock();
+    }
+
+    delta_t -= delta_t_sample;
+    sample_offset = next_sample_offset & FIXP_MASK;
+
+    short sample_now = output();
+    buf[s++*interleave] =
+      sample_prev + (sample_offset*(sample_now - sample_prev) >> FIXP_SHIFT);
+    sample_prev = sample_now;
+  }
+
+  for (i = 0; i < delta_t - 1; i++) {
+    clock();
+  }
+  if (i < delta_t) {
+    sample_prev = output();
+    clock();
+  }
+  sample_offset -= delta_t << FIXP_SHIFT;
+  delta_t = 0;
+  return s;
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking with audio sampling - cycle based with audio resampling.
+//
+// This is the theoretically correct (and computationally intensive) audio
+// sample generation. The samples are generated by resampling to the specified
+// sampling frequency. The work rate is inversely proportional to the
+// percentage of the bandwidth allocated to the filter transition band.
+//
+// This implementation is based on the paper "A Flexible Sampling-Rate
+// Conversion Method", by J. O. Smith and P. Gosset, or rather on the
+// expanded tutorial on the "Digital Audio Resampling Home Page":
+// http://www-ccrma.stanford.edu/~jos/resample/
+//
+// By building shifted FIR tables with samples according to the
+// sampling frequency, this implementation dramatically reduces the
+// computational effort in the filter convolutions, without any loss
+// of accuracy. The filter convolutions are also vectorizable on
+// current hardware.
+//
+// Further possible optimizations are:
+// * An equiripple filter design could yield a lower filter order, see
+//   http://www.mwrf.com/Articles/ArticleID/7229/7229.html
+// * The Convolution Theorem could be used to bring the complexity of
+//   convolution down from O(n*n) to O(n*log(n)) using the Fast Fourier
+//   Transform, see http://en.wikipedia.org/wiki/Convolution_theorem
+// * Simply resampling in two steps can also yield computational
+//   savings, since the transition band will be wider in the first step
+//   and the required filter order is thus lower in this step.
+//   Laurent Ganier has found the optimal intermediate sampling frequency
+//   to be (via derivation of sum of two steps):
+//     2 * pass_freq + sqrt [ 2 * pass_freq * orig_sample_freq
+//       * (dest_sample_freq - 2 * pass_freq) / dest_sample_freq ]
+//
+// NB! the result of right shifting negative numbers is really
+// implementation dependent in the C++ standard.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+int SID::clock_resample_interpolate(cycle_count& delta_t, short* buf, int n,
+				    int interleave)
+{
+  int s = 0;
+
+  for (;;) {
+    cycle_count next_sample_offset = sample_offset + cycles_per_sample;
+    cycle_count delta_t_sample = next_sample_offset >> FIXP_SHIFT;
+    if (delta_t_sample > delta_t) {
+      break;
+    }
+    if (s >= n) {
+      return s;
+    }
+    for (int i = 0; i < delta_t_sample; i++) {
+      clock();
+      sample[sample_index] = sample[sample_index + RINGSIZE] = output();
+      ++sample_index;
+      sample_index &= 0x3fff;
+    }
+    delta_t -= delta_t_sample;
+    sample_offset = next_sample_offset & FIXP_MASK;
+
+    int fir_offset = sample_offset*fir_RES >> FIXP_SHIFT;
+    int fir_offset_rmd = sample_offset*fir_RES & FIXP_MASK;
+    short* fir_start = fir + fir_offset*fir_N;
+    short* sample_start = sample + sample_index - fir_N + RINGSIZE;
+
+    // Convolution with filter impulse response.
+    int v1 = 0;
+    for (int j = 0; j < fir_N; j++) {
+      v1 += sample_start[j]*fir_start[j];
+    }
+
+    // Use next FIR table, wrap around to first FIR table using
+    // previous sample.
+    if (++fir_offset == fir_RES) {
+      fir_offset = 0;
+      --sample_start;
+    }
+    fir_start = fir + fir_offset*fir_N;
+
+    // Convolution with filter impulse response.
+    int v2 = 0;
+    for (int j = 0; j < fir_N; j++) {
+      v2 += sample_start[j]*fir_start[j];
+    }
+
+    // Linear interpolation.
+    // fir_offset_rmd is equal for all samples, it can thus be factorized out:
+    // sum(v1 + rmd*(v2 - v1)) = sum(v1) + rmd*(sum(v2) - sum(v1))
+    int v = v1 + (fir_offset_rmd*(v2 - v1) >> FIXP_SHIFT);
+
+    v >>= FIR_SHIFT;
+
+    // Saturated arithmetics to guard against 16 bit sample overflow.
+    const int half = 1 << 15;
+    if (v >= half) {
+      v = half - 1;
+    }
+    else if (v < -half) {
+      v = -half;
+    }
+
+    buf[s++*interleave] = v;
+  }
+
+  for (int i = 0; i < delta_t; i++) {
+    clock();
+    sample[sample_index] = sample[sample_index + RINGSIZE] = output();
+    ++sample_index;
+    sample_index &= 0x3fff;
+  }
+  sample_offset -= delta_t << FIXP_SHIFT;
+  delta_t = 0;
+  return s;
+}
+
+
+// ----------------------------------------------------------------------------
+// SID clocking with audio sampling - cycle based with audio resampling.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+int SID::clock_resample_fast(cycle_count& delta_t, short* buf, int n,
+			     int interleave)
+{
+  int s = 0;
+
+  for (;;) {
+    cycle_count next_sample_offset = sample_offset + cycles_per_sample;
+    cycle_count delta_t_sample = next_sample_offset >> FIXP_SHIFT;
+    if (delta_t_sample > delta_t) {
+      break;
+    }
+    if (s >= n) {
+      return s;
+    }
+    for (int i = 0; i < delta_t_sample; i++) {
+      clock();
+      sample[sample_index] = sample[sample_index + RINGSIZE] = output();
+      ++sample_index;
+      sample_index &= 0x3fff;
+    }
+    delta_t -= delta_t_sample;
+    sample_offset = next_sample_offset & FIXP_MASK;
+
+    int fir_offset = sample_offset*fir_RES >> FIXP_SHIFT;
+    short* fir_start = fir + fir_offset*fir_N;
+    short* sample_start = sample + sample_index - fir_N + RINGSIZE;
+
+    // Convolution with filter impulse response.
+    int v = 0;
+    for (int j = 0; j < fir_N; j++) {
+      v += sample_start[j]*fir_start[j];
+    }
+
+    v >>= FIR_SHIFT;
+
+    // Saturated arithmetics to guard against 16 bit sample overflow.
+    const int half = 1 << 15;
+    if (v >= half) {
+      v = half - 1;
+    }
+    else if (v < -half) {
+      v = -half;
+    }
+
+    buf[s++*interleave] = v;
+  }
+
+  for (int i = 0; i < delta_t; i++) {
+    clock();
+    sample[sample_index] = sample[sample_index + RINGSIZE] = output();
+    ++sample_index;
+    sample_index &= 0x3fff;
+  }
+  sample_offset -= delta_t << FIXP_SHIFT;
+  delta_t = 0;
+  return s;
+}
diff --git a/MCUME_pico2/pico64/reSID/sid.h b/MCUME_pico2/pico64/reSID/sid.h
new file mode 100755
index 0000000..c9cd6ca
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/sid.h
@@ -0,0 +1,146 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __SID_H__
+#define __SID_H__
+
+#include "siddefs.h"
+#include "voice.h"
+#include "filter.h"
+#include "extfilt.h"
+#include "pot.h"
+
+class RESID_API SID
+{
+public:
+  SID();
+  ~SID();
+
+  void set_chip_model(chip_model model);
+  void enable_filter(bool enable);
+  void enable_external_filter(bool enable);
+  bool set_sampling_parameters(double clock_freq, sampling_method method,
+			       double sample_freq, double pass_freq = -1,
+			       double filter_scale = 0.97);
+  void adjust_sampling_frequency(double sample_freq);
+
+  //void fc_default(const fc_point*& points, int& count);
+  //PointPlotter<sound_sample> fc_plotter();
+
+  void clock();
+  void clock(cycle_count delta_t);
+  int clock(cycle_count& delta_t, short* buf, int n, int interleave = 1);
+  void reset();
+  
+  // Read/write registers.
+  reg8 read(reg8 offset);
+  void write(reg8 offset, reg8 value);
+
+  // Read/write state.
+  class State
+  {
+  public:
+    State();
+
+    char sid_register[0x20];
+
+    reg8 bus_value;
+    cycle_count bus_value_ttl;
+
+    reg24 accumulator[3];
+    reg24 shift_register[3];
+    reg16 rate_counter[3];
+    reg16 rate_counter_period[3];
+    reg16 exponential_counter[3];
+    reg16 exponential_counter_period[3];
+    reg8 envelope_counter[3];
+    EnvelopeGenerator::State envelope_state[3];
+    bool hold_zero[3];
+  };
+    
+  State read_state();
+  void write_state(const State& state);
+
+  // 16-bit input (EXT IN).
+  void input(int sample);
+
+  // 16-bit output (AUDIO OUT).
+  int output();
+  // n-bit output.
+  int output(int bits);
+
+protected:
+  static double I0(double x);
+  RESID_INLINE int clock_fast(cycle_count& delta_t, short* buf, int n,
+			      int interleave);
+  RESID_INLINE int clock_interpolate(cycle_count& delta_t, short* buf, int n,
+				     int interleave);
+  RESID_INLINE int clock_resample_interpolate(cycle_count& delta_t, short* buf,
+					      int n, int interleave);
+  RESID_INLINE int clock_resample_fast(cycle_count& delta_t, short* buf,
+				       int n, int interleave);
+
+  Voice voice[3];
+  Filter filter;
+  ExternalFilter extfilt;
+  Potentiometer potx;
+  Potentiometer poty;
+
+  reg8 bus_value;
+  cycle_count bus_value_ttl;
+
+  double clock_frequency;
+
+  // External audio input.
+  int ext_in;
+
+  // Resampling constants.
+  // The error in interpolated lookup is bounded by 1.234/L^2,
+  // while the error in non-interpolated lookup is bounded by
+  // 0.7854/L + 0.4113/L^2, see
+  // http://www-ccrma.stanford.edu/~jos/resample/Choice_Table_Size.html
+  // For a resolution of 16 bits this yields L >= 285 and L >= 51473,
+  // respectively.
+  static const int FIR_N = 125;
+  static const int FIR_RES_INTERPOLATE = 285;
+  static const int FIR_RES_FAST = 51473;
+  static const int FIR_SHIFT = 15;
+  static const int RINGSIZE = 16384;
+
+  // Fixpoint constants (16.16 bits).
+  static const int FIXP_SHIFT = 16;
+  static const int FIXP_MASK = 0xffff;
+
+  // Sampling variables.
+  sampling_method sampling;
+  cycle_count cycles_per_sample;
+  cycle_count sample_offset;
+  int sample_index;
+  short sample_prev;
+  int fir_N;
+  int fir_RES;
+
+  // Ring buffer with overflow for contiguous storage of RINGSIZE samples.
+  short* sample;
+
+  // FIR_RES filter tables (FIR_N*FIR_RES).
+  short* fir;
+};
+
+#endif // not __SID_H__
diff --git a/MCUME_pico2/pico64/reSID/siddefs.h b/MCUME_pico2/pico64/reSID/siddefs.h
new file mode 100755
index 0000000..0990bcd
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/siddefs.h
@@ -0,0 +1,77 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 1999  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __SIDDEFS_H__
+#define __SIDDEFS_H__
+
+// Define bool, true, and false for C++ compilers that lack these keywords.
+#define RESID_HAVE_BOOL 1
+
+#if !RESID_HAVE_BOOL
+typedef int bool;
+const bool true = 1;
+const bool false = 0;
+#endif
+
+// We could have used the smallest possible data type for each SID register,
+// however this would give a slower engine because of data type conversions.
+// An int is assumed to be at least 32 bits (necessary in the types reg24,
+// cycle_count, and sound_sample). GNU does not support 16-bit machines
+// (GNU Coding Standards: Portability between CPUs), so this should be
+// a valid assumption.
+
+typedef unsigned int reg4;
+typedef unsigned int reg8;
+typedef unsigned int reg12;
+typedef unsigned int reg16;
+typedef unsigned int reg24;
+
+typedef int cycle_count;
+typedef int sound_sample;
+typedef sound_sample fc_point[2];
+
+enum chip_model { MOS6581, MOS8580 };
+
+enum sampling_method { SAMPLE_FAST, SAMPLE_INTERPOLATE,
+		       SAMPLE_RESAMPLE_INTERPOLATE, SAMPLE_RESAMPLE_FAST };
+
+extern "C"
+{
+#ifndef __VERSION_CC__
+extern const char* resid_version_string;
+#else
+const char* resid_version_string = VERSION;
+#endif
+}
+
+// Inlining on/off.
+#define RESID_INLINING 1
+#define RESID_INLINE inline
+
+#ifdef RESID_DLL
+#ifdef RESID_EXPORTS
+#define RESID_API __declspec(dllexport)
+#else
+#define RESID_API __declspec(dllimport)
+#endif // RESID_EXPORTS
+#else // !RESID_DLL
+#define RESID_API
+#endif // RESID_DLL
+
+#endif // not __SIDDEFS_H__
diff --git a/MCUME_pico2/pico64/reSID/spline.h b/MCUME_pico2/pico64/reSID/spline.h
new file mode 100755
index 0000000..93ba277
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/spline.h
@@ -0,0 +1,272 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __SPLINE_H__
+#define __SPLINE_H__
+
+// Our objective is to construct a smooth interpolating single-valued function
+// y = f(x).
+//
+// Catmull-Rom splines are widely used for interpolation, however these are
+// parametric curves [x(t) y(t) ...] and can not be used to directly calculate
+// y = f(x).
+// For a discussion of Catmull-Rom splines see Catmull, E., and R. Rom,
+// "A Class of Local Interpolating Splines", Computer Aided Geometric Design.
+//
+// Natural cubic splines are single-valued functions, and have been used in
+// several applications e.g. to specify gamma curves for image display.
+// These splines do not afford local control, and a set of linear equations
+// including all interpolation points must be solved before any point on the
+// curve can be calculated. The lack of local control makes the splines
+// more difficult to handle than e.g. Catmull-Rom splines, and real-time
+// interpolation of a stream of data points is not possible.
+// For a discussion of natural cubic splines, see e.g. Kreyszig, E., "Advanced
+// Engineering Mathematics".
+//
+// Our approach is to approximate the properties of Catmull-Rom splines for
+// piecewice cubic polynomials f(x) = ax^3 + bx^2 + cx + d as follows:
+// Each curve segment is specified by four interpolation points,
+// p0, p1, p2, p3.
+// The curve between p1 and p2 must interpolate both p1 and p2, and in addition
+//   f'(p1.x) = k1 = (p2.y - p0.y)/(p2.x - p0.x) and
+//   f'(p2.x) = k2 = (p3.y - p1.y)/(p3.x - p1.x).
+//
+// The constraints are expressed by the following system of linear equations
+//
+//   [ 1  xi    xi^2    xi^3 ]   [ d ]    [ yi ]
+//   [     1  2*xi    3*xi^2 ] * [ c ] =  [ ki ]
+//   [ 1  xj    xj^2    xj^3 ]   [ b ]    [ yj ]
+//   [     1  2*xj    3*xj^2 ]   [ a ]    [ kj ]
+//
+// Solving using Gaussian elimination and back substitution, setting
+// dy = yj - yi, dx = xj - xi, we get
+// 
+//   a = ((ki + kj) - 2*dy/dx)/(dx*dx);
+//   b = ((kj - ki)/dx - 3*(xi + xj)*a)/2;
+//   c = ki - (3*xi*a + 2*b)*xi;
+//   d = yi - ((xi*a + b)*xi + c)*xi;
+//
+// Having calculated the coefficients of the cubic polynomial we have the
+// choice of evaluation by brute force
+//
+//   for (x = x1; x <= x2; x += res) {
+//     y = ((a*x + b)*x + c)*x + d;
+//     plot(x, y);
+//   }
+//
+// or by forward differencing
+//
+//   y = ((a*x1 + b)*x1 + c)*x1 + d;
+//   dy = (3*a*(x1 + res) + 2*b)*x1*res + ((a*res + b)*res + c)*res;
+//   d2y = (6*a*(x1 + res) + 2*b)*res*res;
+//   d3y = 6*a*res*res*res;
+//     
+//   for (x = x1; x <= x2; x += res) {
+//     plot(x, y);
+//     y += dy; dy += d2y; d2y += d3y;
+//   }
+//
+// See Foley, Van Dam, Feiner, Hughes, "Computer Graphics, Principles and
+// Practice" for a discussion of forward differencing.
+//
+// If we have a set of interpolation points p0, ..., pn, we may specify
+// curve segments between p0 and p1, and between pn-1 and pn by using the
+// following constraints:
+//   f''(p0.x) = 0 and
+//   f''(pn.x) = 0.
+//
+// Substituting the results for a and b in
+//
+//   2*b + 6*a*xi = 0
+//
+// we get
+//
+//   ki = (3*dy/dx - kj)/2;
+//
+// or by substituting the results for a and b in
+//
+//   2*b + 6*a*xj = 0
+//
+// we get
+//
+//   kj = (3*dy/dx - ki)/2;
+//
+// Finally, if we have only two interpolation points, the cubic polynomial
+// will degenerate to a straight line if we set
+//
+//   ki = kj = dy/dx;
+//
+
+
+#if SPLINE_BRUTE_FORCE
+#define interpolate_segment interpolate_brute_force
+#else
+#define interpolate_segment interpolate_forward_difference
+#endif
+
+
+// ----------------------------------------------------------------------------
+// Calculation of coefficients.
+// ----------------------------------------------------------------------------
+inline
+void cubic_coefficients(double x1, double y1, double x2, double y2,
+			double k1, double k2,
+			double& a, double& b, double& c, double& d)
+{
+  double dx = x2 - x1, dy = y2 - y1;
+
+  a = ((k1 + k2) - 2*dy/dx)/(dx*dx);
+  b = ((k2 - k1)/dx - 3*(x1 + x2)*a)/2;
+  c = k1 - (3*x1*a + 2*b)*x1;
+  d = y1 - ((x1*a + b)*x1 + c)*x1;
+}
+
+// ----------------------------------------------------------------------------
+// Evaluation of cubic polynomial by brute force.
+// ----------------------------------------------------------------------------
+template<class PointPlotter>
+inline
+void interpolate_brute_force(double x1, double y1, double x2, double y2,
+			     double k1, double k2,
+			     PointPlotter plot, double res)
+{
+  double a, b, c, d;
+  cubic_coefficients(x1, y1, x2, y2, k1, k2, a, b, c, d);
+  
+  // Calculate each point.
+  for (double x = x1; x <= x2; x += res) {
+    double y = ((a*x + b)*x + c)*x + d;
+    plot(x, y);
+  }
+}
+
+// ----------------------------------------------------------------------------
+// Evaluation of cubic polynomial by forward differencing.
+// ----------------------------------------------------------------------------
+template<class PointPlotter>
+inline
+void interpolate_forward_difference(double x1, double y1, double x2, double y2,
+				    double k1, double k2,
+				    PointPlotter plot, double res)
+{
+  double a, b, c, d;
+  cubic_coefficients(x1, y1, x2, y2, k1, k2, a, b, c, d);
+  
+  double y = ((a*x1 + b)*x1 + c)*x1 + d;
+  double dy = (3*a*(x1 + res) + 2*b)*x1*res + ((a*res + b)*res + c)*res;
+  double d2y = (6*a*(x1 + res) + 2*b)*res*res;
+  double d3y = 6*a*res*res*res;
+    
+  // Calculate each point.
+  for (double x = x1; x <= x2; x += res) {
+    plot(x, y);
+    y += dy; dy += d2y; d2y += d3y;
+  }
+}
+
+template<class PointIter>
+inline
+double x(PointIter p)
+{
+  return (*p)[0];
+}
+
+template<class PointIter>
+inline
+double y(PointIter p)
+{
+  return (*p)[1];
+}
+
+// ----------------------------------------------------------------------------
+// Evaluation of complete interpolating function.
+// Note that since each curve segment is controlled by four points, the
+// end points will not be interpolated. If extra control points are not
+// desirable, the end points can simply be repeated to ensure interpolation.
+// Note also that points of non-differentiability and discontinuity can be
+// introduced by repeating points.
+// ----------------------------------------------------------------------------
+template<class PointIter, class PointPlotter>
+inline
+void interpolate(PointIter p0, PointIter pn, PointPlotter plot, double res)
+{
+  double k1, k2;
+
+  // Set up points for first curve segment.
+  PointIter p1 = p0; ++p1;
+  PointIter p2 = p1; ++p2;
+  PointIter p3 = p2; ++p3;
+
+  // Draw each curve segment.
+  for (; p2 != pn; ++p0, ++p1, ++p2, ++p3) {
+    // p1 and p2 equal; single point.
+    if (x(p1) == x(p2)) {
+      continue;
+    }
+    // Both end points repeated; straight line.
+    if (x(p0) == x(p1) && x(p2) == x(p3)) {
+      k1 = k2 = (y(p2) - y(p1))/(x(p2) - x(p1));
+    }
+    // p0 and p1 equal; use f''(x1) = 0.
+    else if (x(p0) == x(p1)) {
+      k2 = (y(p3) - y(p1))/(x(p3) - x(p1));
+      k1 = (3*(y(p2) - y(p1))/(x(p2) - x(p1)) - k2)/2;
+    }
+    // p2 and p3 equal; use f''(x2) = 0.
+    else if (x(p2) == x(p3)) {
+      k1 = (y(p2) - y(p0))/(x(p2) - x(p0));
+      k2 = (3*(y(p2) - y(p1))/(x(p2) - x(p1)) - k1)/2;
+    }
+    // Normal curve.
+    else {
+      k1 = (y(p2) - y(p0))/(x(p2) - x(p0));
+      k2 = (y(p3) - y(p1))/(x(p3) - x(p1));
+    }
+
+    interpolate_segment(x(p1), y(p1), x(p2), y(p2), k1, k2, plot, res);
+  }
+}
+
+// ----------------------------------------------------------------------------
+// Class for plotting integers into an array.
+// ----------------------------------------------------------------------------
+template<class F>
+class PointPlotter
+{
+ protected:
+  F* f;
+
+ public:
+  PointPlotter(F* arr) : f(arr)
+  {
+  }
+
+  void operator ()(double x, double y)
+  {
+    // Clamp negative values to zero.
+    if (y < 0) {
+      y = 0;
+    }
+
+    f[F(x)] = F(y);
+  }
+};
+
+
+#endif // not __SPLINE_H__
diff --git a/MCUME_pico2/pico64/reSID/version.cc b/MCUME_pico2/pico64/reSID/version.cc
new file mode 100755
index 0000000..3b61afd
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/version.cc
@@ -0,0 +1,21 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __VERSION_CC__
+#include "siddefs.h"
diff --git a/MCUME_pico2/pico64/reSID/voice.cc b/MCUME_pico2/pico64/reSID/voice.cc
new file mode 100755
index 0000000..b3466a8
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/voice.cc
@@ -0,0 +1,137 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __VOICE_CC__
+#include "voice.h"
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+Voice::Voice()
+{
+//  set_chip_model(MOS6581);
+  {//instead:
+  wave_zero = 0x380;
+  voice_DC = 0x800*0xff;
+  }
+}
+
+// ----------------------------------------------------------------------------
+// Set chip model.
+// ----------------------------------------------------------------------------
+/*
+void Voice::set_chip_model(chip_model model)
+{
+  wave.set_chip_model(model);
+
+  if (model == MOS6581) {
+    // The waveform D/A converter introduces a DC offset in the signal
+    // to the envelope multiplying D/A converter. The "zero" level of
+    // the waveform D/A converter can be found as follows:
+    //
+    // Measure the "zero" voltage of voice 3 on the SID audio output
+    // pin, routing only voice 3 to the mixer ($d417 = $0b, $d418 =
+    // $0f, all other registers zeroed).
+    //
+    // Then set the sustain level for voice 3 to maximum and search for
+    // the waveform output value yielding the same voltage as found
+    // above. This is done by trying out different waveform output
+    // values until the correct value is found, e.g. with the following
+    // program:
+    //
+    //	lda #$08
+    //	sta $d412
+    //	lda #$0b
+    //	sta $d417
+    //	lda #$0f
+    //	sta $d418
+    //	lda #$f0
+    //	sta $d414
+    //	lda #$21
+    //	sta $d412
+    //	lda #$01
+    //	sta $d40e
+    //
+    //	ldx #$00
+    //	lda #$38	; Tweak this to find the "zero" level
+    //l	cmp $d41b
+    //	bne l
+    //	stx $d40e	; Stop frequency counter - freeze waveform output
+    //	brk
+    //
+    // The waveform output range is 0x000 to 0xfff, so the "zero"
+    // level should ideally have been 0x800. In the measured chip, the
+    // waveform output "zero" level was found to be 0x380 (i.e. $d41b
+    // = 0x38) at 5.94V.
+
+    wave_zero = 0x380;
+
+    // The envelope multiplying D/A converter introduces another DC
+    // offset. This is isolated by the following measurements:
+    //
+    // * The "zero" output level of the mixer at full volume is 5.44V.
+    // * Routing one voice to the mixer at full volume yields
+    //     6.75V at maximum voice output (wave = 0xfff, sustain = 0xf)
+    //     5.94V at "zero" voice output  (wave = any,   sustain = 0x0)
+    //     5.70V at minimum voice output (wave = 0x000, sustain = 0xf)
+    // * The DC offset of one voice is (5.94V - 5.44V) = 0.50V
+    // * The dynamic range of one voice is |6.75V - 5.70V| = 1.05V
+    // * The DC offset is thus 0.50V/1.05V ~ 1/2 of the dynamic range.
+    //
+    // Note that by removing the DC offset, we get the following ranges for
+    // one voice:
+    //     y > 0: (6.75V - 5.44V) - 0.50V =  0.81V
+    //     y < 0: (5.70V - 5.44V) - 0.50V = -0.24V
+    // The scaling of the voice amplitude is not symmetric about y = 0;
+    // this follows from the DC level in the waveform output.
+
+    voice_DC = 0x800*0xff;
+  }
+  else {
+    // No DC offsets in the MOS8580.
+    wave_zero = 0x800;
+    voice_DC = 0;
+  }
+}
+*/
+// ----------------------------------------------------------------------------
+// Set sync source.
+// ----------------------------------------------------------------------------
+void Voice::set_sync_source(Voice* source)
+{
+  wave.set_sync_source(&source->wave);
+}
+
+// ----------------------------------------------------------------------------
+// Register functions.
+// ----------------------------------------------------------------------------
+void Voice::writeCONTROL_REG(reg8 control)
+{
+  wave.writeCONTROL_REG(control);
+  envelope.writeCONTROL_REG(control);
+}
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void Voice::reset()
+{
+  wave.reset();
+  envelope.reset();
+}
diff --git a/MCUME_pico2/pico64/reSID/voice.h b/MCUME_pico2/pico64/reSID/voice.h
new file mode 100755
index 0000000..f5f6bc8
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/voice.h
@@ -0,0 +1,77 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __VOICE_H__
+#define __VOICE_H__
+
+#include "siddefs.h"
+#include "wave.h"
+#include "envelope.h"
+
+class RESID_API Voice
+{
+public:
+  Voice();
+
+  void set_chip_model(chip_model model);
+  void set_sync_source(Voice*);
+  void reset();
+
+  void writeCONTROL_REG(reg8);
+
+  // Amplitude modulated waveform output.
+  // Range [-2048*255, 2047*255].
+  RESID_INLINE sound_sample output();
+
+protected:
+  WaveformGenerator wave;
+  EnvelopeGenerator envelope;
+
+  // Waveform D/A zero level.
+  sound_sample wave_zero;
+
+  // Multiplying D/A DC offset.
+  sound_sample voice_DC;
+
+friend class SID;
+};
+
+
+// ----------------------------------------------------------------------------
+// Inline functions.
+// The following function is defined inline because it is called every
+// time a sample is calculated.
+// ----------------------------------------------------------------------------
+
+#if RESID_INLINING || defined(__VOICE_CC__)
+
+// ----------------------------------------------------------------------------
+// Amplitude modulated waveform output.
+// Ideal range [-2048*255, 2047*255].
+// ----------------------------------------------------------------------------
+RESID_INLINE
+sound_sample Voice::output()
+{
+  // Multiply oscillator output with envelope output.
+  return (wave.output() - wave_zero)*envelope.output() + voice_DC;
+}
+
+#endif // RESID_INLINING || defined(__VOICE_CC__)
+
+#endif // not __VOICE_H__
diff --git a/MCUME_pico2/pico64/reSID/wave.cc b/MCUME_pico2/pico64/reSID/wave.cc
new file mode 100755
index 0000000..a7a5aa8
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave.cc
@@ -0,0 +1,150 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#define __WAVE_CC__
+#include "wave.h"
+
+// ----------------------------------------------------------------------------
+// Constructor.
+// ----------------------------------------------------------------------------
+WaveformGenerator::WaveformGenerator()
+{
+  sync_source = this;
+
+ // set_chip_model(MOS6581);
+ {//instead:
+  wave__ST = &wave6581__ST[0];
+  wave_P_T = &wave6581_P_T[0];
+  wave_PS_ = &wave6581_PS_[0];
+  wave_PST = &wave6581_PST[0];
+ }
+  reset();
+}
+
+
+// ----------------------------------------------------------------------------
+// Set sync source.
+// ----------------------------------------------------------------------------
+void WaveformGenerator::set_sync_source(WaveformGenerator* source)
+{
+  sync_source = source;
+  source->sync_dest = this;
+}
+
+
+// ----------------------------------------------------------------------------
+// Set chip model.
+// ----------------------------------------------------------------------------
+/*
+void WaveformGenerator::set_chip_model(chip_model model)
+{
+  if (model == MOS6581) {
+    wave__ST = wave6581__ST;
+    wave_P_T = wave6581_P_T;
+    wave_PS_ = wave6581_PS_;
+    wave_PST = wave6581_PST;
+  }
+  else {
+    wave__ST = wave8580__ST;
+    wave_P_T = wave8580_P_T;
+    wave_PS_ = wave8580_PS_;
+    wave_PST = wave8580_PST;
+  }
+}
+*/
+
+// ----------------------------------------------------------------------------
+// Register functions.
+// ----------------------------------------------------------------------------
+void WaveformGenerator::writeFREQ_LO(reg8 freq_lo)
+{
+  freq = (freq & 0xff00) | (freq_lo & 0x00ff);
+}
+
+void WaveformGenerator::writeFREQ_HI(reg8 freq_hi)
+{
+  freq = ((freq_hi << 8) & 0xff00) | (freq & 0x00ff);
+}
+
+void WaveformGenerator::writePW_LO(reg8 pw_lo)
+{
+  pw = (pw & 0xf00) | (pw_lo & 0x0ff);
+}
+
+void WaveformGenerator::writePW_HI(reg8 pw_hi)
+{
+  pw = ((pw_hi << 8) & 0xf00) | (pw & 0x0ff);
+}
+
+void WaveformGenerator::writeCONTROL_REG(reg8 control)
+{
+  waveform = (control >> 4) & 0x0f;
+  ring_mod = control & 0x04;
+  sync = control & 0x02;
+
+  reg8 test_next = control & 0x08;
+
+  // Test bit set.
+  // The accumulator and the shift register are both cleared.
+  // NB! The shift register is not really cleared immediately. It seems like
+  // the individual bits in the shift register start to fade down towards
+  // zero when test is set. All bits reach zero within approximately
+  // $2000 - $4000 cycles.
+  // This is not modeled. There should fortunately be little audible output
+  // from this peculiar behavior.
+  if (test_next) {
+    accumulator = 0;
+    shift_register = 0;
+  }
+  // Test bit cleared.
+  // The accumulator starts counting, and the shift register is reset to
+  // the value 0x7ffff8.
+  // NB! The shift register will not actually be set to this exact value if the
+  // shift register bits have not had time to fade to zero.
+  // This is not modeled.
+  else if (test) {
+    shift_register = 0x7ffff8;
+  }
+
+  test = test_next;
+
+  // The gate bit is handled by the EnvelopeGenerator.
+}
+
+reg8 WaveformGenerator::readOSC()
+{
+  return output() >> 4;
+}
+
+// ----------------------------------------------------------------------------
+// SID reset.
+// ----------------------------------------------------------------------------
+void WaveformGenerator::reset()
+{
+  accumulator = 0;
+  shift_register = 0x7ffff8;
+  freq = 0;
+  pw = 0;
+
+  test = 0;
+  ring_mod = 0;
+  sync = 0;
+
+  msb_rising = false;
+}
diff --git a/MCUME_pico2/pico64/reSID/wave.h b/MCUME_pico2/pico64/reSID/wave.h
new file mode 100755
index 0000000..65f2e1d
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave.h
@@ -0,0 +1,509 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#ifndef __WAVE_H__
+#define __WAVE_H__
+
+#include "siddefs.h"
+
+// ----------------------------------------------------------------------------
+// A 24 bit accumulator is the basis for waveform generation. FREQ is added to
+// the lower 16 bits of the accumulator each cycle.
+// The accumulator is set to zero when TEST is set, and starts counting
+// when TEST is cleared.
+// The noise waveform is taken from intermediate bits of a 23 bit shift
+// register. This register is clocked by bit 19 of the accumulator.
+// ----------------------------------------------------------------------------
+class RESID_API WaveformGenerator
+{
+public:
+  WaveformGenerator();
+
+  void set_sync_source(WaveformGenerator*);
+  void set_chip_model(chip_model model);
+
+  RESID_INLINE void clock();
+  RESID_INLINE void clock(cycle_count delta_t);
+  RESID_INLINE void synchronize();
+  void reset();
+
+  void writeFREQ_LO(reg8);
+  void writeFREQ_HI(reg8);
+  void writePW_LO(reg8);
+  void writePW_HI(reg8);
+  void writeCONTROL_REG(reg8);
+  reg8 readOSC();
+
+  // 12-bit waveform output.
+  RESID_INLINE reg12 output();
+
+protected:
+  const WaveformGenerator* sync_source;
+  WaveformGenerator* sync_dest;
+
+  // Tell whether the accumulator MSB was set high on this cycle.
+  bool msb_rising;
+
+  reg24 accumulator;
+  reg24 shift_register;
+
+  // Fout  = (Fn*Fclk/16777216)Hz
+  reg16 freq;
+  // PWout = (PWn/40.95)%
+  reg12 pw;
+
+  // The control register right-shifted 4 bits; used for output function
+  // table lookup.
+  reg8 waveform;
+
+  // The remaining control register bits.
+  reg8 test;
+  reg8 ring_mod;
+  reg8 sync;
+  // The gate bit is handled by the EnvelopeGenerator.
+
+  // 16 possible combinations of waveforms.
+  RESID_INLINE reg12 output____();
+  RESID_INLINE reg12 output___T();
+  RESID_INLINE reg12 output__S_();
+  RESID_INLINE reg12 output__ST();
+  RESID_INLINE reg12 output_P__();
+  RESID_INLINE reg12 output_P_T();
+  RESID_INLINE reg12 output_PS_();
+  RESID_INLINE reg12 output_PST();
+  RESID_INLINE reg12 outputN___();
+  RESID_INLINE reg12 outputN__T();
+  RESID_INLINE reg12 outputN_S_();
+  RESID_INLINE reg12 outputN_ST();
+  RESID_INLINE reg12 outputNP__();
+  RESID_INLINE reg12 outputNP_T();
+  RESID_INLINE reg12 outputNPS_();
+  RESID_INLINE reg12 outputNPST();
+
+  // Sample data for combinations of waveforms.
+  /*
+  static reg8 wave6581__ST[];
+  static reg8 wave6581_P_T[];
+  static reg8 wave6581_PS_[];
+  static reg8 wave6581_PST[];
+
+  static reg8 wave8580__ST[];
+  static reg8 wave8580_P_T[];
+  static reg8 wave8580_PS_[];
+  static reg8 wave8580_PST[];
+
+  reg8* wave__ST;
+  reg8* wave_P_T;
+  reg8* wave_PS_;
+  reg8* wave_PST;
+*/
+  const reg8* wave__ST;
+  const reg8* wave_P_T;
+  const reg8* wave_PS_;
+  const reg8* wave_PST;
+    
+friend class Voice;
+friend class SID;
+};
+
+
+// ----------------------------------------------------------------------------
+// Inline functions.
+// The following functions are defined inline because they are called every
+// time a sample is calculated.
+// ----------------------------------------------------------------------------
+
+#if RESID_INLINING || defined(__WAVE_CC__)
+
+// ----------------------------------------------------------------------------
+// SID clocking - 1 cycle.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void WaveformGenerator::clock()
+{
+  // No operation if test bit is set.
+  if (test) {
+    return;
+  }
+
+  reg24 accumulator_prev = accumulator;
+
+  // Calculate new accumulator value;
+  accumulator += freq;
+  accumulator &= 0xffffff;
+
+  // Check whether the MSB is set high. This is used for synchronization.
+  msb_rising = !(accumulator_prev & 0x800000) && (accumulator & 0x800000);
+
+  // Shift noise register once for each time accumulator bit 19 is set high.
+  if (!(accumulator_prev & 0x080000) && (accumulator & 0x080000)) {
+    reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1;
+    shift_register <<= 1;
+    shift_register &= 0x7fffff;
+    shift_register |= bit0;
+  }
+}
+
+// ----------------------------------------------------------------------------
+// SID clocking - delta_t cycles.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void WaveformGenerator::clock(cycle_count delta_t)
+{
+  // No operation if test bit is set.
+  if (test) {
+    return;
+  }
+
+  reg24 accumulator_prev = accumulator;
+
+  // Calculate new accumulator value;
+  reg24 delta_accumulator = delta_t*freq;
+  accumulator += delta_accumulator;
+  accumulator &= 0xffffff;
+
+  // Check whether the MSB is set high. This is used for synchronization.
+  msb_rising = !(accumulator_prev & 0x800000) && (accumulator & 0x800000);
+
+  // Shift noise register once for each time accumulator bit 19 is set high.
+  // Bit 19 is set high each time 2^20 (0x100000) is added to the accumulator.
+  reg24 shift_period = 0x100000;
+
+  while (delta_accumulator) {
+    if (delta_accumulator < shift_period) {
+      shift_period = delta_accumulator;
+      // Determine whether bit 19 is set on the last period.
+      // NB! Requires two's complement integer.
+      if (shift_period <= 0x080000) {
+	// Check for flip from 0 to 1.
+	if (((accumulator - shift_period) & 0x080000) || !(accumulator & 0x080000))
+	{
+	  break;
+	}
+      }
+      else {
+	// Check for flip from 0 (to 1 or via 1 to 0) or from 1 via 0 to 1.
+	if (((accumulator - shift_period) & 0x080000) && !(accumulator & 0x080000))
+	{
+	  break;
+	}
+      }
+    }
+
+    // Shift the noise/random register.
+    // NB! The shift is actually delayed 2 cycles, this is not modeled.
+    reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1;
+    shift_register <<= 1;
+    shift_register &= 0x7fffff;
+    shift_register |= bit0;
+
+    delta_accumulator -= shift_period;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Synchronize oscillators.
+// This must be done after all the oscillators have been clock()'ed since the
+// oscillators operate in parallel.
+// Note that the oscillators must be clocked exactly on the cycle when the
+// MSB is set high for hard sync to operate correctly. See SID::clock().
+// ----------------------------------------------------------------------------
+RESID_INLINE
+void WaveformGenerator::synchronize()
+{
+  // A special case occurs when a sync source is synced itself on the same
+  // cycle as when its MSB is set high. In this case the destination will
+  // not be synced. This has been verified by sampling OSC3.
+  if (msb_rising && sync_dest->sync && !(sync && sync_source->msb_rising)) {
+    sync_dest->accumulator = 0;
+  }
+}
+
+
+// ----------------------------------------------------------------------------
+// Output functions.
+// NB! The output from SID 8580 is delayed one cycle compared to SID 6581,
+// this is not modeled.
+// ----------------------------------------------------------------------------
+
+// No waveform:
+// Zero output.
+//
+RESID_INLINE
+reg12 WaveformGenerator::output____()
+{
+  return 0x000;
+}
+
+// Triangle:
+// The upper 12 bits of the accumulator are used.
+// The MSB is used to create the falling edge of the triangle by inverting
+// the lower 11 bits. The MSB is thrown away and the lower 11 bits are
+// left-shifted (half the resolution, full amplitude).
+// Ring modulation substitutes the MSB with MSB EOR sync_source MSB.
+//
+RESID_INLINE
+reg12 WaveformGenerator::output___T()
+{
+  reg24 msb = (ring_mod ? accumulator ^ sync_source->accumulator : accumulator)
+    & 0x800000;
+  return ((msb ? ~accumulator : accumulator) >> 11) & 0xfff;
+}
+
+// Sawtooth:
+// The output is identical to the upper 12 bits of the accumulator.
+//
+RESID_INLINE
+reg12 WaveformGenerator::output__S_()
+{
+  return accumulator >> 12;
+}
+
+// Pulse:
+// The upper 12 bits of the accumulator are used.
+// These bits are compared to the pulse width register by a 12 bit digital
+// comparator; output is either all one or all zero bits.
+// NB! The output is actually delayed one cycle after the compare.
+// This is not modeled.
+//
+// The test bit, when set to one, holds the pulse waveform output at 0xfff
+// regardless of the pulse width setting.
+//
+RESID_INLINE
+reg12 WaveformGenerator::output_P__()
+{
+  return (test || (accumulator >> 12) >= pw) ? 0xfff : 0x000;
+}
+
+// Noise:
+// The noise output is taken from intermediate bits of a 23-bit shift register
+// which is clocked by bit 19 of the accumulator.
+// NB! The output is actually delayed 2 cycles after bit 19 is set high.
+// This is not modeled.
+//
+// Operation: Calculate EOR result, shift register, set bit 0 = result.
+//
+//                        ----------------------->---------------------
+//                        |                                            |
+//                   ----EOR----                                       |
+//                   |         |                                       |
+//                   2 2 2 1 1 1 1 1 1 1 1 1 1                         |
+// Register bits:    2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---
+//                   |   |       |     |   |       |     |   |
+// OSC3 bits  :      7   6       5     4   3       2     1   0
+//
+// Since waveform output is 12 bits the output is left-shifted 4 times.
+//
+RESID_INLINE
+reg12 WaveformGenerator::outputN___()
+{
+  return
+    ((shift_register & 0x400000) >> 11) |
+    ((shift_register & 0x100000) >> 10) |
+    ((shift_register & 0x010000) >> 7) |
+    ((shift_register & 0x002000) >> 5) |
+    ((shift_register & 0x000800) >> 4) |
+    ((shift_register & 0x000080) >> 1) |
+    ((shift_register & 0x000010) << 1) |
+    ((shift_register & 0x000004) << 2);
+}
+
+// Combined waveforms:
+// By combining waveforms, the bits of each waveform are effectively short
+// circuited. A zero bit in one waveform will result in a zero output bit
+// (thus the infamous claim that the waveforms are AND'ed).
+// However, a zero bit in one waveform will also affect the neighboring bits
+// in the output. The reason for this has not been determined.
+//
+// Example:
+// 
+//             1 1
+// Bit #       1 0 9 8 7 6 5 4 3 2 1 0
+//             -----------------------
+// Sawtooth    0 0 0 1 1 1 1 1 1 0 0 0
+//
+// Triangle    0 0 1 1 1 1 1 1 0 0 0 0
+//
+// AND         0 0 0 1 1 1 1 1 0 0 0 0
+//
+// Output      0 0 0 0 1 1 1 0 0 0 0 0
+//
+//
+// This behavior would be quite difficult to model exactly, since the SID
+// in this case does not act as a digital state machine. Tests show that minor
+// (1 bit)  differences can actually occur in the output from otherwise
+// identical samples from OSC3 when waveforms are combined. To further
+// complicate the situation the output changes slightly with time (more
+// neighboring bits are successively set) when the 12-bit waveform
+// registers are kept unchanged.
+//
+// It is probably possible to come up with a valid model for the
+// behavior, however this would be far too slow for practical use since it
+// would have to be based on the mutual influence of individual bits.
+//
+// The output is instead approximated by using the upper bits of the
+// accumulator as an index to look up the combined output in a table
+// containing actual combined waveform samples from OSC3.
+// These samples are 8 bit, so 4 bits of waveform resolution is lost.
+// All OSC3 samples are taken with FREQ=0x1000, adding a 1 to the upper 12
+// bits of the accumulator each cycle for a sample period of 4096 cycles.
+//
+// Sawtooth+Triangle:
+// The sawtooth output is used to look up an OSC3 sample.
+// 
+// Pulse+Triangle:
+// The triangle output is right-shifted and used to look up an OSC3 sample.
+// The sample is output if the pulse output is on.
+// The reason for using the triangle output as the index is to handle ring
+// modulation. Only the first half of the sample is used, which should be OK
+// since the triangle waveform has half the resolution of the accumulator.
+// 
+// Pulse+Sawtooth:
+// The sawtooth output is used to look up an OSC3 sample.
+// The sample is output if the pulse output is on.
+//
+// Pulse+Sawtooth+Triangle:
+// The sawtooth output is used to look up an OSC3 sample.
+// The sample is output if the pulse output is on.
+// 
+RESID_INLINE
+reg12 WaveformGenerator::output__ST()
+{
+  return wave__ST[output__S_()] << 4;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::output_P_T()
+{
+  return (wave_P_T[output___T() >> 1] << 4) & output_P__();
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::output_PS_()
+{
+  return (wave_PS_[output__S_()] << 4) & output_P__();
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::output_PST()
+{
+  return (wave_PST[output__S_()] << 4) & output_P__();
+}
+
+// Combined waveforms including noise:
+// All waveform combinations including noise output zero after a few cycles.
+// NB! The effects of such combinations are not fully explored. It is claimed
+// that the shift register may be filled with zeroes and locked up, which
+// seems to be true.
+// We have not attempted to model this behavior, suffice to say that
+// there is very little audible output from waveform combinations including
+// noise. We hope that nobody is actually using it.
+//
+RESID_INLINE
+reg12 WaveformGenerator::outputN__T()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputN_S_()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputN_ST()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputNP__()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputNP_T()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputNPS_()
+{
+  return 0;
+}
+
+RESID_INLINE
+reg12 WaveformGenerator::outputNPST()
+{
+  return 0;
+}
+
+// ----------------------------------------------------------------------------
+// Select one of 16 possible combinations of waveforms.
+// ----------------------------------------------------------------------------
+RESID_INLINE
+reg12 WaveformGenerator::output()
+{
+  // It may seem cleaner to use an array of member functions to return
+  // waveform output; however a switch with inline functions is faster.
+
+  switch (waveform) {
+  default:
+  case 0x0:
+    return output____();
+  case 0x1:
+    return output___T();
+  case 0x2:
+    return output__S_();
+  case 0x3:
+    return output__ST();
+  case 0x4:
+    return output_P__();
+  case 0x5:
+    return output_P_T();
+  case 0x6:
+    return output_PS_();
+  case 0x7:
+    return output_PST();
+  case 0x8:
+    return outputN___();
+  case 0x9:
+    return outputN__T();
+  case 0xa:
+    return outputN_S_();
+  case 0xb:
+    return outputN_ST();
+  case 0xc:
+    return outputNP__();
+  case 0xd:
+    return outputNP_T();
+  case 0xe:
+    return outputNPS_();
+  case 0xf:
+    return outputNPST();
+  }
+}
+
+#endif // RESID_INLINING || defined(__WAVE_CC__)
+
+#endif // not __WAVE_H__
diff --git a/MCUME_pico2/pico64/reSID/wave6581_PST.cc b/MCUME_pico2/pico64/reSID/wave6581_PST.cc
new file mode 100755
index 0000000..8aba334
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave6581_PST.cc
@@ -0,0 +1,538 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "wave.h"
+
+//reg8 WaveformGenerator::wave6581_PST[] =
+const reg8 wave6581_PST[] =
+{
+/* 0x000: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x008: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x010: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x018: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x020: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x028: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x030: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x038: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x040: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x048: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x050: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x058: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x060: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x068: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x070: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x078: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x080: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x088: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x090: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x098: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x100: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x108: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x110: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x118: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x120: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x128: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x130: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x138: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x140: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x148: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x150: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x158: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x160: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x168: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x170: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x178: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x180: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x188: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x190: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x198: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x200: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x208: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x210: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x218: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x220: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x228: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x230: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x238: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x240: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x248: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x250: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x258: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x260: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x268: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x270: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x278: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x280: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x288: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x290: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x298: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x300: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x308: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x310: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x318: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x320: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x328: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x330: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x338: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x340: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x348: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x350: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x358: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x360: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x368: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x370: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x378: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x380: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x388: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x390: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x398: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
+/* 0x400: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x408: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x410: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x418: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x420: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x428: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x430: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x438: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x440: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x448: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x450: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x458: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x460: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x468: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x470: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x478: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x480: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x488: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x490: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x498: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x500: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x508: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x510: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x518: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x520: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x528: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x530: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x538: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x540: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x548: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x550: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x558: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x560: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x568: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x570: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x578: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x580: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x588: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x590: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x598: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x600: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x608: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x610: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x618: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x620: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x628: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x630: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x638: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x640: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x648: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x650: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x658: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x660: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x668: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x670: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x678: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x680: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x688: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x690: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x698: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x700: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x708: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x710: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x718: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x720: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x728: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x730: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x738: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x740: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x748: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x750: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x758: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x760: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x768: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x770: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x778: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x780: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x788: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x790: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x798: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+/* 0x7f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
+/* 0x7f8: */  0x00, 0x00, 0x00, 0x78, 0x78, 0x7e, 0x7f, 0x7f,
+/* 0x800: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x808: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x810: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x818: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x820: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x828: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x830: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x838: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x840: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x848: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x850: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x858: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x860: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x868: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x870: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x878: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x880: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x888: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x890: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x898: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x900: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x908: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x910: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x918: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x920: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x928: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x930: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x938: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x940: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x948: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x950: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x958: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x960: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x968: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x970: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x978: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x980: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x988: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x990: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x998: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
+/* 0xc00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+/* 0xff0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
+/* 0xff8: */  0x00, 0x00, 0x00, 0x78, 0x78, 0x7e, 0x7f, 0x7f,
+};
+
diff --git a/MCUME_pico2/pico64/reSID/wave6581_PS_.cc b/MCUME_pico2/pico64/reSID/wave6581_PS_.cc
new file mode 100755
index 0000000..0fb42ca
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave6581_PS_.cc
@@ -0,0 +1,538 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "wave.h"
+
+//reg8 WaveformGenerator::wave6581_PS_[] =
+const reg8 wave6581_PS_[] =
+{
+/* 0x000: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x008: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x010: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x018: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x020: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x028: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x030: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x038: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x040: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x048: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x050: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x058: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x060: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x068: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x070: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x078: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x080: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x088: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x090: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x098: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+/* 0x100: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x108: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x110: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x118: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x120: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x128: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x130: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x138: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x140: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x148: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x150: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x158: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x160: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x168: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x170: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x178: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x180: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x188: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x190: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x198: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x1c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1f,
+/* 0x200: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x208: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x210: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x218: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x220: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x228: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x230: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x238: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x240: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x248: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x250: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x258: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x260: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x268: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x270: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x278: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x280: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x288: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x290: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x298: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x2c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2f,
+/* 0x300: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x308: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x310: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x318: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x320: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x328: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x330: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x338: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x340: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x348: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x350: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x358: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x360: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x368: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x370: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x378: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37,
+/* 0x380: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x388: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x390: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x398: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b,
+/* 0x3c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3d,
+/* 0x3e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
+/* 0x3f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x3f,
+/* 0x3f8: */  0x00, 0x30, 0x38, 0x3f, 0x3e, 0x3f, 0x3f, 0x3f,
+/* 0x400: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x408: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x410: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x418: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x420: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x428: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x430: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x438: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x440: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x448: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x450: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x458: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x460: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x468: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x470: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x478: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x480: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x488: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x490: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x498: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4f,
+/* 0x500: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x508: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x510: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x518: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x520: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x528: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x530: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x538: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x540: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x548: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x550: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x558: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x560: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x568: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x570: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x578: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+/* 0x580: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x588: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x590: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x598: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b,
+/* 0x5c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5d,
+/* 0x5e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5e,
+/* 0x5f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x5f,
+/* 0x5f8: */  0x00, 0x40, 0x40, 0x5f, 0x5c, 0x5f, 0x5f, 0x5f,
+/* 0x600: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x608: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x610: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x618: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x620: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x628: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x630: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x638: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x640: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x648: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x650: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x658: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x660: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x668: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x670: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x678: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67,
+/* 0x680: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x688: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x690: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x698: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x6b,
+/* 0x6c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x6d,
+/* 0x6e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x6e8: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x40, 0x6e,
+/* 0x6f0: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x60, 0x60, 0x6f,
+/* 0x6f8: */  0x00, 0x60, 0x60, 0x6f, 0x60, 0x6f, 0x6f, 0x6f,
+/* 0x700: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x708: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x710: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x718: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x720: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x728: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x730: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x738: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x60, 0x73,
+/* 0x740: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x748: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x750: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x758: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x60, 0x60, 0x75,
+/* 0x760: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x768: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x76,
+/* 0x770: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x77,
+/* 0x778: */  0x00, 0x70, 0x70, 0x77, 0x70, 0x77, 0x77, 0x77,
+/* 0x780: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x788: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x790: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x798: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x79,
+/* 0x7a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x7a8: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x70, 0x70, 0x7a,
+/* 0x7b0: */  0x00, 0x00, 0x00, 0x70, 0x00, 0x70, 0x70, 0x7b,
+/* 0x7b8: */  0x40, 0x70, 0x70, 0x7b, 0x78, 0x7b, 0x7b, 0x7b,
+/* 0x7c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+/* 0x7c8: */  0x00, 0x00, 0x00, 0x70, 0x00, 0x70, 0x70, 0x7c,
+/* 0x7d0: */  0x00, 0x00, 0x00, 0x70, 0x40, 0x70, 0x70, 0x7d,
+/* 0x7d8: */  0x40, 0x70, 0x78, 0x7d, 0x78, 0x7d, 0x7d, 0x7d,
+/* 0x7e0: */  0x00, 0x40, 0x40, 0x78, 0x60, 0x78, 0x78, 0x7e,
+/* 0x7e8: */  0x60, 0x78, 0x78, 0x7e, 0x7c, 0x7e, 0x7e, 0x7e,
+/* 0x7f0: */  0x70, 0x7c, 0x7c, 0x7f, 0x7e, 0x7f, 0x7f, 0x7f,
+/* 0x7f8: */  0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+/* 0x800: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x808: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x810: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x818: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x820: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x828: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x830: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x838: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x840: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x848: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x850: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x858: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x860: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x868: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x870: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x878: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x880: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x888: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x890: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x898: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+/* 0x900: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x908: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x910: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x918: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x920: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x928: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x930: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x938: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x940: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x948: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x950: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x958: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x960: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x968: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x970: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x978: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x980: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x988: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x990: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x998: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0x9c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1f,
+/* 0xa00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0xa80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xac0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2f,
+/* 0xb00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37,
+/* 0xb80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b,
+/* 0xbc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3d,
+/* 0xbe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
+/* 0xbf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x3f,
+/* 0xbf8: */  0x00, 0x30, 0x38, 0x3f, 0x3e, 0x3f, 0x3f, 0x3f,
+/* 0xc00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+/* 0xc80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4f,
+/* 0xd00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x57,
+/* 0xd80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b,
+/* 0xdc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5d,
+/* 0xde0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5e,
+/* 0xdf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x5f,
+/* 0xdf8: */  0x00, 0x40, 0x40, 0x5f, 0x5c, 0x5f, 0x5f, 0x5f,
+/* 0xe00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67,
+/* 0xe80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x6b,
+/* 0xec0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x6d,
+/* 0xee0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xee8: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x40, 0x6e,
+/* 0xef0: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x60, 0x60, 0x6f,
+/* 0xef8: */  0x00, 0x60, 0x60, 0x6f, 0x60, 0x6f, 0x6f, 0x6f,
+/* 0xf00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xf20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xf30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xf38: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x60, 0x73,
+/* 0xf40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xf50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0xf58: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x60, 0x60, 0x75,
+/* 0xf60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0xf68: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x76,
+/* 0xf70: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x77,
+/* 0xf78: */  0x00, 0x70, 0x70, 0x77, 0x70, 0x77, 0x77, 0x77,
+/* 0xf80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0xf90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0xf98: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x79,
+/* 0xfa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0xfa8: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x70, 0x70, 0x7a,
+/* 0xfb0: */  0x00, 0x00, 0x00, 0x70, 0x00, 0x70, 0x70, 0x7b,
+/* 0xfb8: */  0x40, 0x70, 0x70, 0x7b, 0x78, 0x7b, 0x7b, 0x7b,
+/* 0xfc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+/* 0xfc8: */  0x00, 0x00, 0x00, 0x70, 0x00, 0x70, 0x70, 0x7c,
+/* 0xfd0: */  0x00, 0x00, 0x00, 0x70, 0x40, 0x70, 0x70, 0x7d,
+/* 0xfd8: */  0x40, 0x70, 0x78, 0x7d, 0x78, 0x7d, 0x7d, 0x7d,
+/* 0xfe0: */  0x00, 0x40, 0x40, 0x78, 0x60, 0x78, 0x78, 0x7e,
+/* 0xfe8: */  0x60, 0x78, 0x78, 0x7e, 0x7c, 0x7e, 0x7e, 0x7e,
+/* 0xff0: */  0x70, 0x7c, 0x7c, 0x7f, 0x7c, 0x7f, 0x7f, 0x7f,
+/* 0xff8: */  0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+};
+
diff --git a/MCUME_pico2/pico64/reSID/wave6581_P_T.cc b/MCUME_pico2/pico64/reSID/wave6581_P_T.cc
new file mode 100755
index 0000000..3042f33
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave6581_P_T.cc
@@ -0,0 +1,538 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "wave.h"
+
+//reg8 WaveformGenerator::wave6581_P_T[] =
+const reg8 wave6581_P_T[] =
+{
+/* 0x000: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x008: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x010: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x018: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x020: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x028: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x030: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x038: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x040: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x048: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x050: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x058: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x060: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x068: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x070: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x078: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x080: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x088: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x090: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x098: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x100: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x108: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x110: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x118: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x120: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x128: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x130: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x138: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x140: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x148: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x150: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x158: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x160: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x168: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x170: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x178: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x180: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x188: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x190: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x198: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x38, 0x3f,
+/* 0x200: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x208: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x210: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x218: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x220: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x228: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x230: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x238: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x240: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x248: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x250: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x258: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x260: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x268: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x270: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x278: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x280: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x288: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x290: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x298: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f8: */  0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x40, 0x5f,
+/* 0x300: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x308: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x310: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x318: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x320: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x328: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x330: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x338: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x340: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x348: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x350: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x358: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x360: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x368: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x370: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x378: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x60, 0x6f,
+/* 0x380: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x388: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x390: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x398: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+/* 0x3a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x3b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x3b8: */  0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x70, 0x77,
+/* 0x3c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x3d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+/* 0x3d8: */  0x00, 0x00, 0x00, 0x70, 0x40, 0x70, 0x70, 0x7b,
+/* 0x3e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x70,
+/* 0x3e8: */  0x00, 0x40, 0x40, 0x70, 0x60, 0x70, 0x78, 0x7d,
+/* 0x3f0: */  0x00, 0x40, 0x60, 0x78, 0x60, 0x78, 0x78, 0x7e,
+/* 0x3f8: */  0x70, 0x7c, 0x7c, 0x7f, 0x7e, 0x7f, 0x7f, 0x7f,
+/* 0x400: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x408: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x410: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x418: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x420: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x428: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x430: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x438: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x440: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x448: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x450: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x458: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x460: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x468: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x470: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x478: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x480: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x488: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x490: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x498: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x4c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x4e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x4f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x4f8: */  0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x9f,
+/* 0x500: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x508: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x510: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x518: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x520: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x528: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x530: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x538: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x540: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x548: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x550: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x558: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x560: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x568: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x570: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x578: */  0x00, 0x80, 0x80, 0x80, 0x80, 0xa0, 0xa0, 0xaf,
+/* 0x580: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x588: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x590: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x598: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x5a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80,
+/* 0x5b0: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xa0,
+/* 0x5b8: */  0x00, 0x80, 0x80, 0xa0, 0x80, 0xa0, 0xb0, 0xb7,
+/* 0x5c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x5c8: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xa0,
+/* 0x5d0: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xa0,
+/* 0x5d8: */  0x00, 0x80, 0x80, 0xa0, 0x80, 0xb0, 0xb0, 0xbb,
+/* 0x5e0: */  0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0xb0,
+/* 0x5e8: */  0x80, 0x80, 0x80, 0xb0, 0x80, 0xb0, 0xb8, 0xbd,
+/* 0x5f0: */  0x80, 0x80, 0x80, 0xb8, 0xa0, 0xb8, 0xb8, 0xbe,
+/* 0x5f8: */  0xa0, 0xb8, 0xbc, 0xbf, 0xbe, 0xbf, 0xbf, 0xbf,
+/* 0x600: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x608: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x610: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x618: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x620: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x628: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x630: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x638: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
+/* 0x640: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x648: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x650: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x658: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc0,
+/* 0x660: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x668: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xc0,
+/* 0x670: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xc0,
+/* 0x678: */  0x00, 0x80, 0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xcf,
+/* 0x680: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x688: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x690: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x698: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xc0,
+/* 0x6a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x6a8: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xc0,
+/* 0x6b0: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0xc0, 0xc0,
+/* 0x6b8: */  0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xd0, 0xd7,
+/* 0x6c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x6c8: */  0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0xc0, 0xc0,
+/* 0x6d0: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xc0,
+/* 0x6d8: */  0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xd0, 0xd0, 0xdb,
+/* 0x6e0: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xd0,
+/* 0x6e8: */  0x80, 0xc0, 0xc0, 0xd0, 0xc0, 0xd0, 0xd8, 0xdd,
+/* 0x6f0: */  0xc0, 0xc0, 0xc0, 0xd0, 0xc0, 0xd8, 0xd8, 0xde,
+/* 0x6f8: */  0xc0, 0xd8, 0xdc, 0xdf, 0xdc, 0xdf, 0xdf, 0xdf,
+/* 0x700: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x708: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x710: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x718: */  0x00, 0x00, 0x00, 0x80, 0x80, 0xc0, 0xc0, 0xe0,
+/* 0x720: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+/* 0x728: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xe0,
+/* 0x730: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xe0,
+/* 0x738: */  0x80, 0xc0, 0xc0, 0xe0, 0xc0, 0xe0, 0xe0, 0xe7,
+/* 0x740: */  0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x80, 0xc0,
+/* 0x748: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xe0,
+/* 0x750: */  0x00, 0x80, 0x80, 0xc0, 0x80, 0xc0, 0xc0, 0xe0,
+/* 0x758: */  0xc0, 0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xe0, 0xeb,
+/* 0x760: */  0x80, 0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xe0,
+/* 0x768: */  0xc0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xed,
+/* 0x770: */  0xc0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe8, 0xe8, 0xee,
+/* 0x778: */  0xe0, 0xe8, 0xec, 0xef, 0xec, 0xef, 0xef, 0xef,
+/* 0x780: */  0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0xc0,
+/* 0x788: */  0x80, 0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xf0,
+/* 0x790: */  0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xe0, 0xe0, 0xf0,
+/* 0x798: */  0xc0, 0xe0, 0xe0, 0xf0, 0xe0, 0xf0, 0xf0, 0xf3,
+/* 0x7a0: */  0x80, 0xc0, 0xc0, 0xe0, 0xc0, 0xe0, 0xe0, 0xf0,
+/* 0x7a8: */  0xc0, 0xe0, 0xe0, 0xf0, 0xe0, 0xf0, 0xf0, 0xf5,
+/* 0x7b0: */  0xe0, 0xe0, 0xe0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf6,
+/* 0x7b8: */  0xf0, 0xf0, 0xf4, 0xf7, 0xf4, 0xf7, 0xf7, 0xf7,
+/* 0x7c0: */  0xc0, 0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xe0, 0xf0,
+/* 0x7c8: */  0xe0, 0xe0, 0xe0, 0xf8, 0xf0, 0xf8, 0xf8, 0xf9,
+/* 0x7d0: */  0xe0, 0xf0, 0xf0, 0xf8, 0xf0, 0xf8, 0xf8, 0xfa,
+/* 0x7d8: */  0xf0, 0xf8, 0xf8, 0xfb, 0xf8, 0xfb, 0xfb, 0xfb,
+/* 0x7e0: */  0xe0, 0xf0, 0xf0, 0xf8, 0xf0, 0xf8, 0xfc, 0xfc,
+/* 0x7e8: */  0xf8, 0xfc, 0xfc, 0xfd, 0xfc, 0xfd, 0xfd, 0xfd,
+/* 0x7f0: */  0xf8, 0xfc, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
+/* 0x7f8: */  0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/* 0x800: */  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+/* 0x808: */  0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfc, 0xf8,
+/* 0x810: */  0xfd, 0xfd, 0xfd, 0xfc, 0xfd, 0xfc, 0xfc, 0xf8,
+/* 0x818: */  0xfc, 0xfc, 0xfc, 0xf0, 0xf8, 0xf0, 0xf0, 0xe0,
+/* 0x820: */  0xfb, 0xfb, 0xfb, 0xf8, 0xfb, 0xf8, 0xf8, 0xf0,
+/* 0x828: */  0xfa, 0xf8, 0xf8, 0xf0, 0xf8, 0xf0, 0xf0, 0xe0,
+/* 0x830: */  0xf9, 0xf8, 0xf8, 0xf0, 0xf8, 0xf0, 0xe0, 0xe0,
+/* 0x838: */  0xf0, 0xe0, 0xe0, 0xe0, 0xe0, 0xc0, 0xc0, 0xc0,
+/* 0x840: */  0xf7, 0xf7, 0xf7, 0xf4, 0xf7, 0xf4, 0xf0, 0xf0,
+/* 0x848: */  0xf6, 0xf0, 0xf0, 0xf0, 0xf0, 0xe0, 0xe0, 0xe0,
+/* 0x850: */  0xf5, 0xf0, 0xf0, 0xe0, 0xf0, 0xe0, 0xe0, 0xc0,
+/* 0x858: */  0xf0, 0xe0, 0xe0, 0xc0, 0xe0, 0xc0, 0xc0, 0x80,
+/* 0x860: */  0xf3, 0xf0, 0xf0, 0xe0, 0xf0, 0xe0, 0xe0, 0xc0,
+/* 0x868: */  0xf0, 0xe0, 0xe0, 0xc0, 0xc0, 0xc0, 0xc0, 0x80,
+/* 0x870: */  0xf0, 0xe0, 0xc0, 0xc0, 0xc0, 0xc0, 0x80, 0x80,
+/* 0x878: */  0xc0, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00,
+/* 0x880: */  0xef, 0xef, 0xef, 0xec, 0xef, 0xec, 0xe8, 0xe0,
+/* 0x888: */  0xee, 0xe8, 0xe8, 0xe0, 0xe0, 0xe0, 0xe0, 0xc0,
+/* 0x890: */  0xed, 0xe8, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xc0,
+/* 0x898: */  0xe0, 0xe0, 0xc0, 0xc0, 0xc0, 0xc0, 0x80, 0x80,
+/* 0x8a0: */  0xeb, 0xe0, 0xe0, 0xe0, 0xe0, 0xc0, 0xc0, 0xc0,
+/* 0x8a8: */  0xe0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x8b0: */  0xe0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x8b8: */  0xc0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x8c0: */  0xe7, 0xe0, 0xe0, 0xc0, 0xe0, 0xc0, 0xc0, 0x80,
+/* 0x8c8: */  0xe0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x8d0: */  0xe0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x8d8: */  0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e0: */  0xe0, 0xc0, 0xc0, 0x80, 0x80, 0x00, 0x00, 0x00,
+/* 0x8e8: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f0: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x900: */  0xdf, 0xdf, 0xdf, 0xdc, 0xdf, 0xdc, 0xd8, 0xc0,
+/* 0x908: */  0xde, 0xd8, 0xd8, 0xc0, 0xd8, 0xc0, 0xc0, 0xc0,
+/* 0x910: */  0xdd, 0xd8, 0xd0, 0xc0, 0xd0, 0xc0, 0xc0, 0x80,
+/* 0x918: */  0xd0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x920: */  0xdb, 0xd0, 0xd0, 0xc0, 0xc0, 0xc0, 0xc0, 0x80,
+/* 0x928: */  0xc0, 0xc0, 0xc0, 0x80, 0xc0, 0x80, 0x80, 0x00,
+/* 0x930: */  0xc0, 0xc0, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00,
+/* 0x938: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x940: */  0xd7, 0xd0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0x80,
+/* 0x948: */  0xc0, 0xc0, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x950: */  0xc0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x958: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x960: */  0xc0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x968: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x970: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x978: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x980: */  0xcf, 0xc0, 0xc0, 0xc0, 0xc0, 0x80, 0x80, 0x00,
+/* 0x988: */  0xc0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x990: */  0xc0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0x998: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a0: */  0xc0, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c0: */  0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa00: */  0xbf, 0xbf, 0xbf, 0xbe, 0xbf, 0xbc, 0xbc, 0xa0,
+/* 0xa08: */  0xbe, 0xbc, 0xb8, 0xa0, 0xb8, 0xa0, 0x80, 0x80,
+/* 0xa10: */  0xbd, 0xb8, 0xb0, 0x80, 0xb0, 0x80, 0x80, 0x80,
+/* 0xa18: */  0xb0, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00,
+/* 0xa20: */  0xbb, 0xb0, 0xb0, 0x80, 0xa0, 0x80, 0x80, 0x00,
+/* 0xa28: */  0xa0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0xa30: */  0xa0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0xa38: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa40: */  0xb7, 0xb0, 0xa0, 0x80, 0xa0, 0x80, 0x80, 0x00,
+/* 0xa48: */  0xa0, 0x80, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+/* 0xa50: */  0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa60: */  0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa80: */  0xaf, 0xa0, 0xa0, 0x80, 0x80, 0x80, 0x80, 0x00,
+/* 0xa88: */  0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa90: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa0: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac0: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb00: */  0x9f, 0x90, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00,
+/* 0xb08: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb10: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb20: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb40: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb80: */  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc00: */  0x7f, 0x7f, 0x7f, 0x7e, 0x7f, 0x7c, 0x7c, 0x70,
+/* 0xc08: */  0x7e, 0x7c, 0x78, 0x60, 0x78, 0x60, 0x60, 0x00,
+/* 0xc10: */  0x7d, 0x78, 0x78, 0x60, 0x70, 0x40, 0x40, 0x00,
+/* 0xc18: */  0x70, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc20: */  0x7b, 0x78, 0x70, 0x40, 0x70, 0x40, 0x00, 0x00,
+/* 0xc28: */  0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc30: */  0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc40: */  0x77, 0x70, 0x70, 0x00, 0x60, 0x00, 0x00, 0x00,
+/* 0xc48: */  0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc50: */  0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc60: */  0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc80: */  0x6f, 0x60, 0x60, 0x00, 0x60, 0x00, 0x00, 0x00,
+/* 0xc88: */  0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc90: */  0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd00: */  0x5f, 0x58, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00,
+/* 0xd08: */  0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe00: */  0x3f, 0x3c, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xff0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xff8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
diff --git a/MCUME_pico2/pico64/reSID/wave6581__ST.cc b/MCUME_pico2/pico64/reSID/wave6581__ST.cc
new file mode 100755
index 0000000..e634012
--- /dev/null
+++ b/MCUME_pico2/pico64/reSID/wave6581__ST.cc
@@ -0,0 +1,538 @@
+//  ---------------------------------------------------------------------------
+//  This file is part of reSID, a MOS6581 SID emulator engine.
+//  Copyright (C) 2004  Dag Lem <resid@nimrod.no>
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//  ---------------------------------------------------------------------------
+
+#include "wave.h"
+
+//reg8 WaveformGenerator::wave6581__ST[] =
+const reg8 wave6581__ST[] =
+{
+/* 0x000: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x008: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x010: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x018: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x020: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x028: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x030: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x038: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x040: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x048: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x050: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x058: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x060: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x068: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x070: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x078: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x080: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x088: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x090: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x098: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x0c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x0f8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0x100: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x108: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x110: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x118: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x120: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x128: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x130: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x138: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x140: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x148: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x150: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x158: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x160: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x168: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x170: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x178: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x180: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x188: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x190: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x198: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x1c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x1f8: */  0x0e, 0x0e, 0x0e, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f,
+/* 0x200: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x208: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x210: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x218: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x220: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x228: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x230: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x238: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x240: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x248: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x250: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x258: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x260: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x268: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x270: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x278: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x280: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x288: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x290: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x298: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x2c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0x300: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x308: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x310: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x318: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x320: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x328: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x330: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x338: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x340: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x348: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x350: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x358: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x360: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x368: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x370: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x378: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x380: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x388: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x390: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x398: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x3c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3f0: */  0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c,
+/* 0x3f8: */  0x1e, 0x1e, 0x1e, 0x1e, 0x1f, 0x1f, 0x3f, 0x3f,
+/* 0x400: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x408: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x410: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x418: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x420: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x428: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x430: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x438: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x440: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x448: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x450: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x458: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x460: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x468: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x470: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x478: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x480: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x488: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x490: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x498: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x4c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0x500: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x508: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x510: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x518: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x520: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x528: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x530: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x538: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x540: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x548: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x550: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x558: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x560: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x568: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x570: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x578: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x580: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x588: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x590: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x598: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x5c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5f8: */  0x0e, 0x0e, 0x0e, 0x0e, 0x0f, 0x0f, 0x0f, 0x1f,
+/* 0x600: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x608: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x610: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x618: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x620: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x628: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x630: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x638: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x640: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x648: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x650: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x658: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x660: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x668: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x670: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x678: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x680: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x688: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x690: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x698: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x6c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x6f8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0x700: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x708: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x710: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x718: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x720: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x728: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x730: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x738: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x740: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x748: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x750: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x758: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x760: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x768: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x770: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x778: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x780: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x788: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x790: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x798: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x7c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7e0: */  0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
+/* 0x7e8: */  0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
+/* 0x7f0: */  0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
+/* 0x7f8: */  0x3e, 0x3e, 0x3f, 0x3f, 0x7f, 0x7f, 0x7f, 0x7f,
+/* 0x800: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x808: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x810: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x818: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x820: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x828: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x830: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x838: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x840: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x848: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x850: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x858: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x860: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x868: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x870: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x878: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x880: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x888: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x890: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x898: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x8c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x8f8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0x900: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x908: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x910: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x918: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x920: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x928: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x930: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x938: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x940: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x948: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x950: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x958: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x960: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x968: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x970: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x978: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0x980: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x988: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x990: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x998: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9a8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9b8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0x9c0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9c8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9d8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9e8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x9f8: */  0x0e, 0x0e, 0x0e, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f,
+/* 0xa00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xa80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xa98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xab8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xac0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xac8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xad8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xae8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xaf8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0xb00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xb40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xb80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xb98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xba8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xbc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbe8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xbf0: */  0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c,
+/* 0xbf8: */  0x1e, 0x1e, 0x1e, 0x1e, 0x1f, 0x1f, 0x3f, 0x3f,
+/* 0xc00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xc80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xc98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xca8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xcc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xce8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xcf8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0xd00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xd40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xd80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xd98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xda8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xdc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xde8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xdf8: */  0x0e, 0x0e, 0x0e, 0x0e, 0x0f, 0x0f, 0x0f, 0x1f,
+/* 0xe00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xe80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xe98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xea8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xeb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xec0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xec8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xed8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xee8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xef8: */  0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07,
+/* 0xf00: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf08: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf10: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf18: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf20: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf28: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf30: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf38: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xf40: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf48: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf50: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf58: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf60: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf68: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf70: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf78: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
+/* 0xf80: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf88: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf90: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xf98: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfa8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfb8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+/* 0xfc0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfc8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd0: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfd8: */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0xfe0: */  0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
+/* 0xfe8: */  0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
+/* 0xff0: */  0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
+/* 0xff8: */  0x3e, 0x3e, 0x3f, 0x3f, 0x7f, 0x7f, 0x7f, 0x7f,
+};
+
diff --git a/MCUME_pico2/pico64/roms.cpp b/MCUME_pico2/pico64/roms.cpp
new file mode 100644
index 0000000..8347112
--- /dev/null
+++ b/MCUME_pico2/pico64/roms.cpp
@@ -0,0 +1,1899 @@
+#include <stdint.h>
+#include <stdio.h>
+#include "roms.h"
+
+#define PROGMEM
+/*
+bin2h basic.901226-01.bin -id=rom_basic > roms.h
+bin2h kernal.901227-03.bin -id=rom_kernal >> roms.h
+bin2h characters.901225-01.bin -id=rom_characters >> roms.h
+*/
+
+//file auto-generated from basic.901226-01.bin by bin2h.exe
+const size_t rom_basic_len = 8192;
+const unsigned char PROGMEM rom_basic[8192]=
+{
+	0x94,0xE3,0x7B,0xE3,0x43,0x42,0x4D,0x42,0x41,0x53,0x49,
+	0x43,0x30,0xA8,0x41,0xA7,0x1D,0xAD,0xF7,0xA8,0xA4,0xAB,
+	0xBE,0xAB,0x80,0xB0,0x05,0xAC,0xA4,0xA9,0x9F,0xA8,0x70,
+	0xA8,0x27,0xA9,0x1C,0xA8,0x82,0xA8,0xD1,0xA8,0x3A,0xA9,
+	0x2E,0xA8,0x4A,0xA9,0x2C,0xB8,0x67,0xE1,0x55,0xE1,0x64,
+	0xE1,0xB2,0xB3,0x23,0xB8,0x7F,0xAA,0x9F,0xAA,0x56,0xA8,
+	0x9B,0xA6,0x5D,0xA6,0x85,0xAA,0x29,0xE1,0xBD,0xE1,0xC6,
+	0xE1,0x7A,0xAB,0x41,0xA6,0x39,0xBC,0xCC,0xBC,0x58,0xBC,
+	0x10,0x03,0x7D,0xB3,0x9E,0xB3,0x71,0xBF,0x97,0xE0,0xEA,
+	0xB9,0xED,0xBF,0x64,0xE2,0x6B,0xE2,0xB4,0xE2,0x0E,0xE3,
+	0x0D,0xB8,0x7C,0xB7,0x65,0xB4,0xAD,0xB7,0x8B,0xB7,0xEC,
+	0xB6,0x00,0xB7,0x2C,0xB7,0x37,0xB7,0x79,0x69,0xB8,0x79,
+	0x52,0xB8,0x7B,0x2A,0xBA,0x7B,0x11,0xBB,0x7F,0x7A,0xBF,
+	0x50,0xE8,0xAF,0x46,0xE5,0xAF,0x7D,0xB3,0xBF,0x5A,0xD3,
+	0xAE,0x64,0x15,0xB0,0x45,0x4E,0xC4,0x46,0x4F,0xD2,0x4E,
+	0x45,0x58,0xD4,0x44,0x41,0x54,0xC1,0x49,0x4E,0x50,0x55,
+	0x54,0xA3,0x49,0x4E,0x50,0x55,0xD4,0x44,0x49,0xCD,0x52,
+	0x45,0x41,0xC4,0x4C,0x45,0xD4,0x47,0x4F,0x54,0xCF,0x52,
+	0x55,0xCE,0x49,0xC6,0x52,0x45,0x53,0x54,0x4F,0x52,0xC5,
+	0x47,0x4F,0x53,0x55,0xC2,0x52,0x45,0x54,0x55,0x52,0xCE,
+	0x52,0x45,0xCD,0x53,0x54,0x4F,0xD0,0x4F,0xCE,0x57,0x41,
+	0x49,0xD4,0x4C,0x4F,0x41,0xC4,0x53,0x41,0x56,0xC5,0x56,
+	0x45,0x52,0x49,0x46,0xD9,0x44,0x45,0xC6,0x50,0x4F,0x4B,
+	0xC5,0x50,0x52,0x49,0x4E,0x54,0xA3,0x50,0x52,0x49,0x4E,
+	0xD4,0x43,0x4F,0x4E,0xD4,0x4C,0x49,0x53,0xD4,0x43,0x4C,
+	0xD2,0x43,0x4D,0xC4,0x53,0x59,0xD3,0x4F,0x50,0x45,0xCE,
+	0x43,0x4C,0x4F,0x53,0xC5,0x47,0x45,0xD4,0x4E,0x45,0xD7,
+	0x54,0x41,0x42,0xA8,0x54,0xCF,0x46,0xCE,0x53,0x50,0x43,
+	0xA8,0x54,0x48,0x45,0xCE,0x4E,0x4F,0xD4,0x53,0x54,0x45,
+	0xD0,0xAB,0xAD,0xAA,0xAF,0xDE,0x41,0x4E,0xC4,0x4F,0xD2,
+	0xBE,0xBD,0xBC,0x53,0x47,0xCE,0x49,0x4E,0xD4,0x41,0x42,
+	0xD3,0x55,0x53,0xD2,0x46,0x52,0xC5,0x50,0x4F,0xD3,0x53,
+	0x51,0xD2,0x52,0x4E,0xC4,0x4C,0x4F,0xC7,0x45,0x58,0xD0,
+	0x43,0x4F,0xD3,0x53,0x49,0xCE,0x54,0x41,0xCE,0x41,0x54,
+	0xCE,0x50,0x45,0x45,0xCB,0x4C,0x45,0xCE,0x53,0x54,0x52,
+	0xA4,0x56,0x41,0xCC,0x41,0x53,0xC3,0x43,0x48,0x52,0xA4,
+	0x4C,0x45,0x46,0x54,0xA4,0x52,0x49,0x47,0x48,0x54,0xA4,
+	0x4D,0x49,0x44,0xA4,0x47,0xCF,0x00,0x54,0x4F,0x4F,0x20,
+	0x4D,0x41,0x4E,0x59,0x20,0x46,0x49,0x4C,0x45,0xD3,0x46,
+	0x49,0x4C,0x45,0x20,0x4F,0x50,0x45,0xCE,0x46,0x49,0x4C,
+	0x45,0x20,0x4E,0x4F,0x54,0x20,0x4F,0x50,0x45,0xCE,0x46,
+	0x49,0x4C,0x45,0x20,0x4E,0x4F,0x54,0x20,0x46,0x4F,0x55,
+	0x4E,0xC4,0x44,0x45,0x56,0x49,0x43,0x45,0x20,0x4E,0x4F,
+	0x54,0x20,0x50,0x52,0x45,0x53,0x45,0x4E,0xD4,0x4E,0x4F,
+	0x54,0x20,0x49,0x4E,0x50,0x55,0x54,0x20,0x46,0x49,0x4C,
+	0xC5,0x4E,0x4F,0x54,0x20,0x4F,0x55,0x54,0x50,0x55,0x54,
+	0x20,0x46,0x49,0x4C,0xC5,0x4D,0x49,0x53,0x53,0x49,0x4E,
+	0x47,0x20,0x46,0x49,0x4C,0x45,0x20,0x4E,0x41,0x4D,0xC5,
+	0x49,0x4C,0x4C,0x45,0x47,0x41,0x4C,0x20,0x44,0x45,0x56,
+	0x49,0x43,0x45,0x20,0x4E,0x55,0x4D,0x42,0x45,0xD2,0x4E,
+	0x45,0x58,0x54,0x20,0x57,0x49,0x54,0x48,0x4F,0x55,0x54,
+	0x20,0x46,0x4F,0xD2,0x53,0x59,0x4E,0x54,0x41,0xD8,0x52,
+	0x45,0x54,0x55,0x52,0x4E,0x20,0x57,0x49,0x54,0x48,0x4F,
+	0x55,0x54,0x20,0x47,0x4F,0x53,0x55,0xC2,0x4F,0x55,0x54,
+	0x20,0x4F,0x46,0x20,0x44,0x41,0x54,0xC1,0x49,0x4C,0x4C,
+	0x45,0x47,0x41,0x4C,0x20,0x51,0x55,0x41,0x4E,0x54,0x49,
+	0x54,0xD9,0x4F,0x56,0x45,0x52,0x46,0x4C,0x4F,0xD7,0x4F,
+	0x55,0x54,0x20,0x4F,0x46,0x20,0x4D,0x45,0x4D,0x4F,0x52,
+	0xD9,0x55,0x4E,0x44,0x45,0x46,0x27,0x44,0x20,0x53,0x54,
+	0x41,0x54,0x45,0x4D,0x45,0x4E,0xD4,0x42,0x41,0x44,0x20,
+	0x53,0x55,0x42,0x53,0x43,0x52,0x49,0x50,0xD4,0x52,0x45,
+	0x44,0x49,0x4D,0x27,0x44,0x20,0x41,0x52,0x52,0x41,0xD9,
+	0x44,0x49,0x56,0x49,0x53,0x49,0x4F,0x4E,0x20,0x42,0x59,
+	0x20,0x5A,0x45,0x52,0xCF,0x49,0x4C,0x4C,0x45,0x47,0x41,
+	0x4C,0x20,0x44,0x49,0x52,0x45,0x43,0xD4,0x54,0x59,0x50,
+	0x45,0x20,0x4D,0x49,0x53,0x4D,0x41,0x54,0x43,0xC8,0x53,
+	0x54,0x52,0x49,0x4E,0x47,0x20,0x54,0x4F,0x4F,0x20,0x4C,
+	0x4F,0x4E,0xC7,0x46,0x49,0x4C,0x45,0x20,0x44,0x41,0x54,
+	0xC1,0x46,0x4F,0x52,0x4D,0x55,0x4C,0x41,0x20,0x54,0x4F,
+	0x4F,0x20,0x43,0x4F,0x4D,0x50,0x4C,0x45,0xD8,0x43,0x41,
+	0x4E,0x27,0x54,0x20,0x43,0x4F,0x4E,0x54,0x49,0x4E,0x55,
+	0xC5,0x55,0x4E,0x44,0x45,0x46,0x27,0x44,0x20,0x46,0x55,
+	0x4E,0x43,0x54,0x49,0x4F,0xCE,0x56,0x45,0x52,0x49,0x46,
+	0xD9,0x4C,0x4F,0x41,0xC4,0x9E,0xA1,0xAC,0xA1,0xB5,0xA1,
+	0xC2,0xA1,0xD0,0xA1,0xE2,0xA1,0xF0,0xA1,0xFF,0xA1,0x10,
+	0xA2,0x25,0xA2,0x35,0xA2,0x3B,0xA2,0x4F,0xA2,0x5A,0xA2,
+	0x6A,0xA2,0x72,0xA2,0x7F,0xA2,0x90,0xA2,0x9D,0xA2,0xAA,
+	0xA2,0xBA,0xA2,0xC8,0xA2,0xD5,0xA2,0xE4,0xA2,0xED,0xA2,
+	0x00,0xA3,0x0E,0xA3,0x1E,0xA3,0x24,0xA3,0x83,0xA3,0x0D,
+	0x4F,0x4B,0x0D,0x00,0x20,0x20,0x45,0x52,0x52,0x4F,0x52,
+	0x00,0x20,0x49,0x4E,0x20,0x00,0x0D,0x0A,0x52,0x45,0x41,
+	0x44,0x59,0x2E,0x0D,0x0A,0x00,0x0D,0x0A,0x42,0x52,0x45,
+	0x41,0x4B,0x00,0xA0,0xBA,0xE8,0xE8,0xE8,0xE8,0xBD,0x01,
+	0x01,0xC9,0x81,0xD0,0x21,0xA5,0x4A,0xD0,0x0A,0xBD,0x02,
+	0x01,0x85,0x49,0xBD,0x03,0x01,0x85,0x4A,0xDD,0x03,0x01,
+	0xD0,0x07,0xA5,0x49,0xDD,0x02,0x01,0xF0,0x07,0x8A,0x18,
+	0x69,0x12,0xAA,0xD0,0xD8,0x60,0x20,0x08,0xA4,0x85,0x31,
+	0x84,0x32,0x38,0xA5,0x5A,0xE5,0x5F,0x85,0x22,0xA8,0xA5,
+	0x5B,0xE5,0x60,0xAA,0xE8,0x98,0xF0,0x23,0xA5,0x5A,0x38,
+	0xE5,0x22,0x85,0x5A,0xB0,0x03,0xC6,0x5B,0x38,0xA5,0x58,
+	0xE5,0x22,0x85,0x58,0xB0,0x08,0xC6,0x59,0x90,0x04,0xB1,
+	0x5A,0x91,0x58,0x88,0xD0,0xF9,0xB1,0x5A,0x91,0x58,0xC6,
+	0x5B,0xC6,0x59,0xCA,0xD0,0xF2,0x60,0x0A,0x69,0x3E,0xB0,
+	0x35,0x85,0x22,0xBA,0xE4,0x22,0x90,0x2E,0x60,0xC4,0x34,
+	0x90,0x28,0xD0,0x04,0xC5,0x33,0x90,0x22,0x48,0xA2,0x09,
+	0x98,0x48,0xB5,0x57,0xCA,0x10,0xFA,0x20,0x26,0xB5,0xA2,
+	0xF7,0x68,0x95,0x61,0xE8,0x30,0xFA,0x68,0xA8,0x68,0xC4,
+	0x34,0x90,0x06,0xD0,0x05,0xC5,0x33,0xB0,0x01,0x60,0xA2,
+	0x10,0x6C,0x00,0x03,0x8A,0x0A,0xAA,0xBD,0x26,0xA3,0x85,
+	0x22,0xBD,0x27,0xA3,0x85,0x23,0x20,0xCC,0xFF,0xA9,0x00,
+	0x85,0x13,0x20,0xD7,0xAA,0x20,0x45,0xAB,0xA0,0x00,0xB1,
+	0x22,0x48,0x29,0x7F,0x20,0x47,0xAB,0xC8,0x68,0x10,0xF4,
+	0x20,0x7A,0xA6,0xA9,0x69,0xA0,0xA3,0x20,0x1E,0xAB,0xA4,
+	0x3A,0xC8,0xF0,0x03,0x20,0xC2,0xBD,0xA9,0x76,0xA0,0xA3,
+	0x20,0x1E,0xAB,0xA9,0x80,0x20,0x90,0xFF,0x6C,0x02,0x03,
+	0x20,0x60,0xA5,0x86,0x7A,0x84,0x7B,0x20,0x73,0x00,0xAA,
+	0xF0,0xF0,0xA2,0xFF,0x86,0x3A,0x90,0x06,0x20,0x79,0xA5,
+	0x4C,0xE1,0xA7,0x20,0x6B,0xA9,0x20,0x79,0xA5,0x84,0x0B,
+	0x20,0x13,0xA6,0x90,0x44,0xA0,0x01,0xB1,0x5F,0x85,0x23,
+	0xA5,0x2D,0x85,0x22,0xA5,0x60,0x85,0x25,0xA5,0x5F,0x88,
+	0xF1,0x5F,0x18,0x65,0x2D,0x85,0x2D,0x85,0x24,0xA5,0x2E,
+	0x69,0xFF,0x85,0x2E,0xE5,0x60,0xAA,0x38,0xA5,0x5F,0xE5,
+	0x2D,0xA8,0xB0,0x03,0xE8,0xC6,0x25,0x18,0x65,0x22,0x90,
+	0x03,0xC6,0x23,0x18,0xB1,0x22,0x91,0x24,0xC8,0xD0,0xF9,
+	0xE6,0x23,0xE6,0x25,0xCA,0xD0,0xF2,0x20,0x59,0xA6,0x20,
+	0x33,0xA5,0xAD,0x00,0x02,0xF0,0x88,0x18,0xA5,0x2D,0x85,
+	0x5A,0x65,0x0B,0x85,0x58,0xA4,0x2E,0x84,0x5B,0x90,0x01,
+	0xC8,0x84,0x59,0x20,0xB8,0xA3,0xA5,0x14,0xA4,0x15,0x8D,
+	0xFE,0x01,0x8C,0xFF,0x01,0xA5,0x31,0xA4,0x32,0x85,0x2D,
+	0x84,0x2E,0xA4,0x0B,0x88,0xB9,0xFC,0x01,0x91,0x5F,0x88,
+	0x10,0xF8,0x20,0x59,0xA6,0x20,0x33,0xA5,0x4C,0x80,0xA4,
+	0xA5,0x2B,0xA4,0x2C,0x85,0x22,0x84,0x23,0x18,0xA0,0x01,
+	0xB1,0x22,0xF0,0x1D,0xA0,0x04,0xC8,0xB1,0x22,0xD0,0xFB,
+	0xC8,0x98,0x65,0x22,0xAA,0xA0,0x00,0x91,0x22,0xA5,0x23,
+	0x69,0x00,0xC8,0x91,0x22,0x86,0x22,0x85,0x23,0x90,0xDD,
+	0x60,0xA2,0x00,0x20,0x12,0xE1,0xC9,0x0D,0xF0,0x0D,0x9D,
+	0x00,0x02,0xE8,0xE0,0x59,0x90,0xF1,0xA2,0x17,0x4C,0x37,
+	0xA4,0x4C,0xCA,0xAA,0x6C,0x04,0x03,0xA6,0x7A,0xA0,0x04,
+	0x84,0x0F,0xBD,0x00,0x02,0x10,0x07,0xC9,0xFF,0xF0,0x3E,
+	0xE8,0xD0,0xF4,0xC9,0x20,0xF0,0x37,0x85,0x08,0xC9,0x22,
+	0xF0,0x56,0x24,0x0F,0x70,0x2D,0xC9,0x3F,0xD0,0x04,0xA9,
+	0x99,0xD0,0x25,0xC9,0x30,0x90,0x04,0xC9,0x3C,0x90,0x1D,
+	0x84,0x71,0xA0,0x00,0x84,0x0B,0x88,0x86,0x7A,0xCA,0xC8,
+	0xE8,0xBD,0x00,0x02,0x38,0xF9,0x9E,0xA0,0xF0,0xF5,0xC9,
+	0x80,0xD0,0x30,0x05,0x0B,0xA4,0x71,0xE8,0xC8,0x99,0xFB,
+	0x01,0xB9,0xFB,0x01,0xF0,0x36,0x38,0xE9,0x3A,0xF0,0x04,
+	0xC9,0x49,0xD0,0x02,0x85,0x0F,0x38,0xE9,0x55,0xD0,0x9F,
+	0x85,0x08,0xBD,0x00,0x02,0xF0,0xDF,0xC5,0x08,0xF0,0xDB,
+	0xC8,0x99,0xFB,0x01,0xE8,0xD0,0xF0,0xA6,0x7A,0xE6,0x0B,
+	0xC8,0xB9,0x9D,0xA0,0x10,0xFA,0xB9,0x9E,0xA0,0xD0,0xB4,
+	0xBD,0x00,0x02,0x10,0xBE,0x99,0xFD,0x01,0xC6,0x7B,0xA9,
+	0xFF,0x85,0x7A,0x60,0xA5,0x2B,0xA6,0x2C,0xA0,0x01,0x85,
+	0x5F,0x86,0x60,0xB1,0x5F,0xF0,0x1F,0xC8,0xC8,0xA5,0x15,
+	0xD1,0x5F,0x90,0x18,0xF0,0x03,0x88,0xD0,0x09,0xA5,0x14,
+	0x88,0xD1,0x5F,0x90,0x0C,0xF0,0x0A,0x88,0xB1,0x5F,0xAA,
+	0x88,0xB1,0x5F,0xB0,0xD7,0x18,0x60,0xD0,0xFD,0xA9,0x00,
+	0xA8,0x91,0x2B,0xC8,0x91,0x2B,0xA5,0x2B,0x18,0x69,0x02,
+	0x85,0x2D,0xA5,0x2C,0x69,0x00,0x85,0x2E,0x20,0x8E,0xA6,
+	0xA9,0x00,0xD0,0x2D,0x20,0xE7,0xFF,0xA5,0x37,0xA4,0x38,
+	0x85,0x33,0x84,0x34,0xA5,0x2D,0xA4,0x2E,0x85,0x2F,0x84,
+	0x30,0x85,0x31,0x84,0x32,0x20,0x1D,0xA8,0xA2,0x19,0x86,
+	0x16,0x68,0xA8,0x68,0xA2,0xFA,0x9A,0x48,0x98,0x48,0xA9,
+	0x00,0x85,0x3E,0x85,0x10,0x60,0x18,0xA5,0x2B,0x69,0xFF,
+	0x85,0x7A,0xA5,0x2C,0x69,0xFF,0x85,0x7B,0x60,0x90,0x06,
+	0xF0,0x04,0xC9,0xAB,0xD0,0xE9,0x20,0x6B,0xA9,0x20,0x13,
+	0xA6,0x20,0x79,0x00,0xF0,0x0C,0xC9,0xAB,0xD0,0x8E,0x20,
+	0x73,0x00,0x20,0x6B,0xA9,0xD0,0x86,0x68,0x68,0xA5,0x14,
+	0x05,0x15,0xD0,0x06,0xA9,0xFF,0x85,0x14,0x85,0x15,0xA0,
+	0x01,0x84,0x0F,0xB1,0x5F,0xF0,0x43,0x20,0x2C,0xA8,0x20,
+	0xD7,0xAA,0xC8,0xB1,0x5F,0xAA,0xC8,0xB1,0x5F,0xC5,0x15,
+	0xD0,0x04,0xE4,0x14,0xF0,0x02,0xB0,0x2C,0x84,0x49,0x20,
+	0xCD,0xBD,0xA9,0x20,0xA4,0x49,0x29,0x7F,0x20,0x47,0xAB,
+	0xC9,0x22,0xD0,0x06,0xA5,0x0F,0x49,0xFF,0x85,0x0F,0xC8,
+	0xF0,0x11,0xB1,0x5F,0xD0,0x10,0xA8,0xB1,0x5F,0xAA,0xC8,
+	0xB1,0x5F,0x86,0x5F,0x85,0x60,0xD0,0xB5,0x4C,0x86,0xE3,
+	0x6C,0x06,0x03,0x10,0xD7,0xC9,0xFF,0xF0,0xD3,0x24,0x0F,
+	0x30,0xCF,0x38,0xE9,0x7F,0xAA,0x84,0x49,0xA0,0xFF,0xCA,
+	0xF0,0x08,0xC8,0xB9,0x9E,0xA0,0x10,0xFA,0x30,0xF5,0xC8,
+	0xB9,0x9E,0xA0,0x30,0xB2,0x20,0x47,0xAB,0xD0,0xF5,0xA9,
+	0x80,0x85,0x10,0x20,0xA5,0xA9,0x20,0x8A,0xA3,0xD0,0x05,
+	0x8A,0x69,0x0F,0xAA,0x9A,0x68,0x68,0xA9,0x09,0x20,0xFB,
+	0xA3,0x20,0x06,0xA9,0x18,0x98,0x65,0x7A,0x48,0xA5,0x7B,
+	0x69,0x00,0x48,0xA5,0x3A,0x48,0xA5,0x39,0x48,0xA9,0xA4,
+	0x20,0xFF,0xAE,0x20,0x8D,0xAD,0x20,0x8A,0xAD,0xA5,0x66,
+	0x09,0x7F,0x25,0x62,0x85,0x62,0xA9,0x8B,0xA0,0xA7,0x85,
+	0x22,0x84,0x23,0x4C,0x43,0xAE,0xA9,0xBC,0xA0,0xB9,0x20,
+	0xA2,0xBB,0x20,0x79,0x00,0xC9,0xA9,0xD0,0x06,0x20,0x73,
+	0x00,0x20,0x8A,0xAD,0x20,0x2B,0xBC,0x20,0x38,0xAE,0xA5,
+	0x4A,0x48,0xA5,0x49,0x48,0xA9,0x81,0x48,0x20,0x2C,0xA8,
+	0xA5,0x7A,0xA4,0x7B,0xC0,0x02,0xEA,0xF0,0x04,0x85,0x3D,
+	0x84,0x3E,0xA0,0x00,0xB1,0x7A,0xD0,0x43,0xA0,0x02,0xB1,
+	0x7A,0x18,0xD0,0x03,0x4C,0x4B,0xA8,0xC8,0xB1,0x7A,0x85,
+	0x39,0xC8,0xB1,0x7A,0x85,0x3A,0x98,0x65,0x7A,0x85,0x7A,
+	0x90,0x02,0xE6,0x7B,0x6C,0x08,0x03,0x20,0x73,0x00,0x20,
+	0xED,0xA7,0x4C,0xAE,0xA7,0xF0,0x3C,0xE9,0x80,0x90,0x11,
+	0xC9,0x23,0xB0,0x17,0x0A,0xA8,0xB9,0x0D,0xA0,0x48,0xB9,
+	0x0C,0xA0,0x48,0x4C,0x73,0x00,0x4C,0xA5,0xA9,0xC9,0x3A,
+	0xF0,0xD6,0x4C,0x08,0xAF,0xC9,0x4B,0xD0,0xF9,0x20,0x73,
+	0x00,0xA9,0xA4,0x20,0xFF,0xAE,0x4C,0xA0,0xA8,0x38,0xA5,
+	0x2B,0xE9,0x01,0xA4,0x2C,0xB0,0x01,0x88,0x85,0x41,0x84,
+	0x42,0x60,0x20,0xE1,0xFF,0xB0,0x01,0x18,0xD0,0x3C,0xA5,
+	0x7A,0xA4,0x7B,0xA6,0x3A,0xE8,0xF0,0x0C,0x85,0x3D,0x84,
+	0x3E,0xA5,0x39,0xA4,0x3A,0x85,0x3B,0x84,0x3C,0x68,0x68,
+	0xA9,0x81,0xA0,0xA3,0x90,0x03,0x4C,0x69,0xA4,0x4C,0x86,
+	0xE3,0xD0,0x17,0xA2,0x1A,0xA4,0x3E,0xD0,0x03,0x4C,0x37,
+	0xA4,0xA5,0x3D,0x85,0x7A,0x84,0x7B,0xA5,0x3B,0xA4,0x3C,
+	0x85,0x39,0x84,0x3A,0x60,0x08,0xA9,0x00,0x20,0x90,0xFF,
+	0x28,0xD0,0x03,0x4C,0x59,0xA6,0x20,0x60,0xA6,0x4C,0x97,
+	0xA8,0xA9,0x03,0x20,0xFB,0xA3,0xA5,0x7B,0x48,0xA5,0x7A,
+	0x48,0xA5,0x3A,0x48,0xA5,0x39,0x48,0xA9,0x8D,0x48,0x20,
+	0x79,0x00,0x20,0xA0,0xA8,0x4C,0xAE,0xA7,0x20,0x6B,0xA9,
+	0x20,0x09,0xA9,0x38,0xA5,0x39,0xE5,0x14,0xA5,0x3A,0xE5,
+	0x15,0xB0,0x0B,0x98,0x38,0x65,0x7A,0xA6,0x7B,0x90,0x07,
+	0xE8,0xB0,0x04,0xA5,0x2B,0xA6,0x2C,0x20,0x17,0xA6,0x90,
+	0x1E,0xA5,0x5F,0xE9,0x01,0x85,0x7A,0xA5,0x60,0xE9,0x00,
+	0x85,0x7B,0x60,0xD0,0xFD,0xA9,0xFF,0x85,0x4A,0x20,0x8A,
+	0xA3,0x9A,0xC9,0x8D,0xF0,0x0B,0xA2,0x0C,0x2C,0xA2,0x11,
+	0x4C,0x37,0xA4,0x4C,0x08,0xAF,0x68,0x68,0x85,0x39,0x68,
+	0x85,0x3A,0x68,0x85,0x7A,0x68,0x85,0x7B,0x20,0x06,0xA9,
+	0x98,0x18,0x65,0x7A,0x85,0x7A,0x90,0x02,0xE6,0x7B,0x60,
+	0xA2,0x3A,0x2C,0xA2,0x00,0x86,0x07,0xA0,0x00,0x84,0x08,
+	0xA5,0x08,0xA6,0x07,0x85,0x07,0x86,0x08,0xB1,0x7A,0xF0,
+	0xE8,0xC5,0x08,0xF0,0xE4,0xC8,0xC9,0x22,0xD0,0xF3,0xF0,
+	0xE9,0x20,0x9E,0xAD,0x20,0x79,0x00,0xC9,0x89,0xF0,0x05,
+	0xA9,0xA7,0x20,0xFF,0xAE,0xA5,0x61,0xD0,0x05,0x20,0x09,
+	0xA9,0xF0,0xBB,0x20,0x79,0x00,0xB0,0x03,0x4C,0xA0,0xA8,
+	0x4C,0xED,0xA7,0x20,0x9E,0xB7,0x48,0xC9,0x8D,0xF0,0x04,
+	0xC9,0x89,0xD0,0x91,0xC6,0x65,0xD0,0x04,0x68,0x4C,0xEF,
+	0xA7,0x20,0x73,0x00,0x20,0x6B,0xA9,0xC9,0x2C,0xF0,0xEE,
+	0x68,0x60,0xA2,0x00,0x86,0x14,0x86,0x15,0xB0,0xF7,0xE9,
+	0x2F,0x85,0x07,0xA5,0x15,0x85,0x22,0xC9,0x19,0xB0,0xD4,
+	0xA5,0x14,0x0A,0x26,0x22,0x0A,0x26,0x22,0x65,0x14,0x85,
+	0x14,0xA5,0x22,0x65,0x15,0x85,0x15,0x06,0x14,0x26,0x15,
+	0xA5,0x14,0x65,0x07,0x85,0x14,0x90,0x02,0xE6,0x15,0x20,
+	0x73,0x00,0x4C,0x71,0xA9,0x20,0x8B,0xB0,0x85,0x49,0x84,
+	0x4A,0xA9,0xB2,0x20,0xFF,0xAE,0xA5,0x0E,0x48,0xA5,0x0D,
+	0x48,0x20,0x9E,0xAD,0x68,0x2A,0x20,0x90,0xAD,0xD0,0x18,
+	0x68,0x10,0x12,0x20,0x1B,0xBC,0x20,0xBF,0xB1,0xA0,0x00,
+	0xA5,0x64,0x91,0x49,0xC8,0xA5,0x65,0x91,0x49,0x60,0x4C,
+	0xD0,0xBB,0x68,0xA4,0x4A,0xC0,0xBF,0xD0,0x4C,0x20,0xA6,
+	0xB6,0xC9,0x06,0xD0,0x3D,0xA0,0x00,0x84,0x61,0x84,0x66,
+	0x84,0x71,0x20,0x1D,0xAA,0x20,0xE2,0xBA,0xE6,0x71,0xA4,
+	0x71,0x20,0x1D,0xAA,0x20,0x0C,0xBC,0xAA,0xF0,0x05,0xE8,
+	0x8A,0x20,0xED,0xBA,0xA4,0x71,0xC8,0xC0,0x06,0xD0,0xDF,
+	0x20,0xE2,0xBA,0x20,0x9B,0xBC,0xA6,0x64,0xA4,0x63,0xA5,
+	0x65,0x4C,0xDB,0xFF,0xB1,0x22,0x20,0x80,0x00,0x90,0x03,
+	0x4C,0x48,0xB2,0xE9,0x2F,0x4C,0x7E,0xBD,0xA0,0x02,0xB1,
+	0x64,0xC5,0x34,0x90,0x17,0xD0,0x07,0x88,0xB1,0x64,0xC5,
+	0x33,0x90,0x0E,0xA4,0x65,0xC4,0x2E,0x90,0x08,0xD0,0x0D,
+	0xA5,0x64,0xC5,0x2D,0xB0,0x07,0xA5,0x64,0xA4,0x65,0x4C,
+	0x68,0xAA,0xA0,0x00,0xB1,0x64,0x20,0x75,0xB4,0xA5,0x50,
+	0xA4,0x51,0x85,0x6F,0x84,0x70,0x20,0x7A,0xB6,0xA9,0x61,
+	0xA0,0x00,0x85,0x50,0x84,0x51,0x20,0xDB,0xB6,0xA0,0x00,
+	0xB1,0x50,0x91,0x49,0xC8,0xB1,0x50,0x91,0x49,0xC8,0xB1,
+	0x50,0x91,0x49,0x60,0x20,0x86,0xAA,0x4C,0xB5,0xAB,0x20,
+	0x9E,0xB7,0xF0,0x05,0xA9,0x2C,0x20,0xFF,0xAE,0x08,0x86,
+	0x13,0x20,0x18,0xE1,0x28,0x4C,0xA0,0xAA,0x20,0x21,0xAB,
+	0x20,0x79,0x00,0xF0,0x35,0xF0,0x43,0xC9,0xA3,0xF0,0x50,
+	0xC9,0xA6,0x18,0xF0,0x4B,0xC9,0x2C,0xF0,0x37,0xC9,0x3B,
+	0xF0,0x5E,0x20,0x9E,0xAD,0x24,0x0D,0x30,0xDE,0x20,0xDD,
+	0xBD,0x20,0x87,0xB4,0x20,0x21,0xAB,0x20,0x3B,0xAB,0xD0,
+	0xD3,0xA9,0x00,0x9D,0x00,0x02,0xA2,0xFF,0xA0,0x01,0xA5,
+	0x13,0xD0,0x10,0xA9,0x0D,0x20,0x47,0xAB,0x24,0x13,0x10,
+	0x05,0xA9,0x0A,0x20,0x47,0xAB,0x49,0xFF,0x60,0x38,0x20,
+	0xF0,0xFF,0x98,0x38,0xE9,0x0A,0xB0,0xFC,0x49,0xFF,0x69,
+	0x01,0xD0,0x16,0x08,0x38,0x20,0xF0,0xFF,0x84,0x09,0x20,
+	0x9B,0xB7,0xC9,0x29,0xD0,0x59,0x28,0x90,0x06,0x8A,0xE5,
+	0x09,0x90,0x05,0xAA,0xE8,0xCA,0xD0,0x06,0x20,0x73,0x00,
+	0x4C,0xA2,0xAA,0x20,0x3B,0xAB,0xD0,0xF2,0x20,0x87,0xB4,
+	0x20,0xA6,0xB6,0xAA,0xA0,0x00,0xE8,0xCA,0xF0,0xBC,0xB1,
+	0x22,0x20,0x47,0xAB,0xC8,0xC9,0x0D,0xD0,0xF3,0x20,0xE5,
+	0xAA,0x4C,0x28,0xAB,0xA5,0x13,0xF0,0x03,0xA9,0x20,0x2C,
+	0xA9,0x1D,0x2C,0xA9,0x3F,0x20,0x0C,0xE1,0x29,0xFF,0x60,
+	0xA5,0x11,0xF0,0x11,0x30,0x04,0xA0,0xFF,0xD0,0x04,0xA5,
+	0x3F,0xA4,0x40,0x85,0x39,0x84,0x3A,0x4C,0x08,0xAF,0xA5,
+	0x13,0xF0,0x05,0xA2,0x18,0x4C,0x37,0xA4,0xA9,0x0C,0xA0,
+	0xAD,0x20,0x1E,0xAB,0xA5,0x3D,0xA4,0x3E,0x85,0x7A,0x84,
+	0x7B,0x60,0x20,0xA6,0xB3,0xC9,0x23,0xD0,0x10,0x20,0x73,
+	0x00,0x20,0x9E,0xB7,0xA9,0x2C,0x20,0xFF,0xAE,0x86,0x13,
+	0x20,0x1E,0xE1,0xA2,0x01,0xA0,0x02,0xA9,0x00,0x8D,0x01,
+	0x02,0xA9,0x40,0x20,0x0F,0xAC,0xA6,0x13,0xD0,0x13,0x60,
+	0x20,0x9E,0xB7,0xA9,0x2C,0x20,0xFF,0xAE,0x86,0x13,0x20,
+	0x1E,0xE1,0x20,0xCE,0xAB,0xA5,0x13,0x20,0xCC,0xFF,0xA2,
+	0x00,0x86,0x13,0x60,0xC9,0x22,0xD0,0x0B,0x20,0xBD,0xAE,
+	0xA9,0x3B,0x20,0xFF,0xAE,0x20,0x21,0xAB,0x20,0xA6,0xB3,
+	0xA9,0x2C,0x8D,0xFF,0x01,0x20,0xF9,0xAB,0xA5,0x13,0xF0,
+	0x0D,0x20,0xB7,0xFF,0x29,0x02,0xF0,0x06,0x20,0xB5,0xAB,
+	0x4C,0xF8,0xA8,0xAD,0x00,0x02,0xD0,0x1E,0xA5,0x13,0xD0,
+	0xE3,0x20,0x06,0xA9,0x4C,0xFB,0xA8,0xA5,0x13,0xD0,0x06,
+	0x20,0x45,0xAB,0x20,0x3B,0xAB,0x4C,0x60,0xA5,0xA6,0x41,
+	0xA4,0x42,0xA9,0x98,0x2C,0xA9,0x00,0x85,0x11,0x86,0x43,
+	0x84,0x44,0x20,0x8B,0xB0,0x85,0x49,0x84,0x4A,0xA5,0x7A,
+	0xA4,0x7B,0x85,0x4B,0x84,0x4C,0xA6,0x43,0xA4,0x44,0x86,
+	0x7A,0x84,0x7B,0x20,0x79,0x00,0xD0,0x20,0x24,0x11,0x50,
+	0x0C,0x20,0x24,0xE1,0x8D,0x00,0x02,0xA2,0xFF,0xA0,0x01,
+	0xD0,0x0C,0x30,0x75,0xA5,0x13,0xD0,0x03,0x20,0x45,0xAB,
+	0x20,0xF9,0xAB,0x86,0x7A,0x84,0x7B,0x20,0x73,0x00,0x24,
+	0x0D,0x10,0x31,0x24,0x11,0x50,0x09,0xE8,0x86,0x7A,0xA9,
+	0x00,0x85,0x07,0xF0,0x0C,0x85,0x07,0xC9,0x22,0xF0,0x07,
+	0xA9,0x3A,0x85,0x07,0xA9,0x2C,0x18,0x85,0x08,0xA5,0x7A,
+	0xA4,0x7B,0x69,0x00,0x90,0x01,0xC8,0x20,0x8D,0xB4,0x20,
+	0xE2,0xB7,0x20,0xDA,0xA9,0x4C,0x91,0xAC,0x20,0xF3,0xBC,
+	0xA5,0x0E,0x20,0xC2,0xA9,0x20,0x79,0x00,0xF0,0x07,0xC9,
+	0x2C,0xF0,0x03,0x4C,0x4D,0xAB,0xA5,0x7A,0xA4,0x7B,0x85,
+	0x43,0x84,0x44,0xA5,0x4B,0xA4,0x4C,0x85,0x7A,0x84,0x7B,
+	0x20,0x79,0x00,0xF0,0x2D,0x20,0xFD,0xAE,0x4C,0x15,0xAC,
+	0x20,0x06,0xA9,0xC8,0xAA,0xD0,0x12,0xA2,0x0D,0xC8,0xB1,
+	0x7A,0xF0,0x6C,0xC8,0xB1,0x7A,0x85,0x3F,0xC8,0xB1,0x7A,
+	0xC8,0x85,0x40,0x20,0xFB,0xA8,0x20,0x79,0x00,0xAA,0xE0,
+	0x83,0xD0,0xDC,0x4C,0x51,0xAC,0xA5,0x43,0xA4,0x44,0xA6,
+	0x11,0x10,0x03,0x4C,0x27,0xA8,0xA0,0x00,0xB1,0x43,0xF0,
+	0x0B,0xA5,0x13,0xD0,0x07,0xA9,0xFC,0xA0,0xAC,0x4C,0x1E,
+	0xAB,0x60,0x3F,0x45,0x58,0x54,0x52,0x41,0x20,0x49,0x47,
+	0x4E,0x4F,0x52,0x45,0x44,0x0D,0x00,0x3F,0x52,0x45,0x44,
+	0x4F,0x20,0x46,0x52,0x4F,0x4D,0x20,0x53,0x54,0x41,0x52,
+	0x54,0x0D,0x00,0xD0,0x04,0xA0,0x00,0xF0,0x03,0x20,0x8B,
+	0xB0,0x85,0x49,0x84,0x4A,0x20,0x8A,0xA3,0xF0,0x05,0xA2,
+	0x0A,0x4C,0x37,0xA4,0x9A,0x8A,0x18,0x69,0x04,0x48,0x69,
+	0x06,0x85,0x24,0x68,0xA0,0x01,0x20,0xA2,0xBB,0xBA,0xBD,
+	0x09,0x01,0x85,0x66,0xA5,0x49,0xA4,0x4A,0x20,0x67,0xB8,
+	0x20,0xD0,0xBB,0xA0,0x01,0x20,0x5D,0xBC,0xBA,0x38,0xFD,
+	0x09,0x01,0xF0,0x17,0xBD,0x0F,0x01,0x85,0x39,0xBD,0x10,
+	0x01,0x85,0x3A,0xBD,0x12,0x01,0x85,0x7A,0xBD,0x11,0x01,
+	0x85,0x7B,0x4C,0xAE,0xA7,0x8A,0x69,0x11,0xAA,0x9A,0x20,
+	0x79,0x00,0xC9,0x2C,0xD0,0xF1,0x20,0x73,0x00,0x20,0x24,
+	0xAD,0x20,0x9E,0xAD,0x18,0x24,0x38,0x24,0x0D,0x30,0x03,
+	0xB0,0x03,0x60,0xB0,0xFD,0xA2,0x16,0x4C,0x37,0xA4,0xA6,
+	0x7A,0xD0,0x02,0xC6,0x7B,0xC6,0x7A,0xA2,0x00,0x24,0x48,
+	0x8A,0x48,0xA9,0x01,0x20,0xFB,0xA3,0x20,0x83,0xAE,0xA9,
+	0x00,0x85,0x4D,0x20,0x79,0x00,0x38,0xE9,0xB1,0x90,0x17,
+	0xC9,0x03,0xB0,0x13,0xC9,0x01,0x2A,0x49,0x01,0x45,0x4D,
+	0xC5,0x4D,0x90,0x61,0x85,0x4D,0x20,0x73,0x00,0x4C,0xBB,
+	0xAD,0xA6,0x4D,0xD0,0x2C,0xB0,0x7B,0x69,0x07,0x90,0x77,
+	0x65,0x0D,0xD0,0x03,0x4C,0x3D,0xB6,0x69,0xFF,0x85,0x22,
+	0x0A,0x65,0x22,0xA8,0x68,0xD9,0x80,0xA0,0xB0,0x67,0x20,
+	0x8D,0xAD,0x48,0x20,0x20,0xAE,0x68,0xA4,0x4B,0x10,0x17,
+	0xAA,0xF0,0x56,0xD0,0x5F,0x46,0x0D,0x8A,0x2A,0xA6,0x7A,
+	0xD0,0x02,0xC6,0x7B,0xC6,0x7A,0xA0,0x1B,0x85,0x4D,0xD0,
+	0xD7,0xD9,0x80,0xA0,0xB0,0x48,0x90,0xD9,0xB9,0x82,0xA0,
+	0x48,0xB9,0x81,0xA0,0x48,0x20,0x33,0xAE,0xA5,0x4D,0x4C,
+	0xA9,0xAD,0x4C,0x08,0xAF,0xA5,0x66,0xBE,0x80,0xA0,0xA8,
+	0x68,0x85,0x22,0xE6,0x22,0x68,0x85,0x23,0x98,0x48,0x20,
+	0x1B,0xBC,0xA5,0x65,0x48,0xA5,0x64,0x48,0xA5,0x63,0x48,
+	0xA5,0x62,0x48,0xA5,0x61,0x48,0x6C,0x22,0x00,0xA0,0xFF,
+	0x68,0xF0,0x23,0xC9,0x64,0xF0,0x03,0x20,0x8D,0xAD,0x84,
+	0x4B,0x68,0x4A,0x85,0x12,0x68,0x85,0x69,0x68,0x85,0x6A,
+	0x68,0x85,0x6B,0x68,0x85,0x6C,0x68,0x85,0x6D,0x68,0x85,
+	0x6E,0x45,0x66,0x85,0x6F,0xA5,0x61,0x60,0x6C,0x0A,0x03,
+	0xA9,0x00,0x85,0x0D,0x20,0x73,0x00,0xB0,0x03,0x4C,0xF3,
+	0xBC,0x20,0x13,0xB1,0x90,0x03,0x4C,0x28,0xAF,0xC9,0xFF,
+	0xD0,0x0F,0xA9,0xA8,0xA0,0xAE,0x20,0xA2,0xBB,0x4C,0x73,
+	0x00,0x82,0x49,0x0F,0xDA,0xA1,0xC9,0x2E,0xF0,0xDE,0xC9,
+	0xAB,0xF0,0x58,0xC9,0xAA,0xF0,0xD1,0xC9,0x22,0xD0,0x0F,
+	0xA5,0x7A,0xA4,0x7B,0x69,0x00,0x90,0x01,0xC8,0x20,0x87,
+	0xB4,0x4C,0xE2,0xB7,0xC9,0xA8,0xD0,0x13,0xA0,0x18,0xD0,
+	0x3B,0x20,0xBF,0xB1,0xA5,0x65,0x49,0xFF,0xA8,0xA5,0x64,
+	0x49,0xFF,0x4C,0x91,0xB3,0xC9,0xA5,0xD0,0x03,0x4C,0xF4,
+	0xB3,0xC9,0xB4,0x90,0x03,0x4C,0xA7,0xAF,0x20,0xFA,0xAE,
+	0x20,0x9E,0xAD,0xA9,0x29,0x2C,0xA9,0x28,0x2C,0xA9,0x2C,
+	0xA0,0x00,0xD1,0x7A,0xD0,0x03,0x4C,0x73,0x00,0xA2,0x0B,
+	0x4C,0x37,0xA4,0xA0,0x15,0x68,0x68,0x4C,0xFA,0xAD,0x38,
+	0xA5,0x64,0xE9,0x00,0xA5,0x65,0xE9,0xA0,0x90,0x08,0xA9,
+	0xA2,0xE5,0x64,0xA9,0xE3,0xE5,0x65,0x60,0x20,0x8B,0xB0,
+	0x85,0x64,0x84,0x65,0xA6,0x45,0xA4,0x46,0xA5,0x0D,0xF0,
+	0x26,0xA9,0x00,0x85,0x70,0x20,0x14,0xAF,0x90,0x1C,0xE0,
+	0x54,0xD0,0x18,0xC0,0xC9,0xD0,0x14,0x20,0x84,0xAF,0x84,
+	0x5E,0x88,0x84,0x71,0xA0,0x06,0x84,0x5D,0xA0,0x24,0x20,
+	0x68,0xBE,0x4C,0x6F,0xB4,0x60,0x24,0x0E,0x10,0x0D,0xA0,
+	0x00,0xB1,0x64,0xAA,0xC8,0xB1,0x64,0xA8,0x8A,0x4C,0x91,
+	0xB3,0x20,0x14,0xAF,0x90,0x2D,0xE0,0x54,0xD0,0x1B,0xC0,
+	0x49,0xD0,0x25,0x20,0x84,0xAF,0x98,0xA2,0xA0,0x4C,0x4F,
+	0xBC,0x20,0xDE,0xFF,0x86,0x64,0x84,0x63,0x85,0x65,0xA0,
+	0x00,0x84,0x62,0x60,0xE0,0x53,0xD0,0x0A,0xC0,0x54,0xD0,
+	0x06,0x20,0xB7,0xFF,0x4C,0x3C,0xBC,0xA5,0x64,0xA4,0x65,
+	0x4C,0xA2,0xBB,0x0A,0x48,0xAA,0x20,0x73,0x00,0xE0,0x8F,
+	0x90,0x20,0x20,0xFA,0xAE,0x20,0x9E,0xAD,0x20,0xFD,0xAE,
+	0x20,0x8F,0xAD,0x68,0xAA,0xA5,0x65,0x48,0xA5,0x64,0x48,
+	0x8A,0x48,0x20,0x9E,0xB7,0x68,0xA8,0x8A,0x48,0x4C,0xD6,
+	0xAF,0x20,0xF1,0xAE,0x68,0xA8,0xB9,0xEA,0x9F,0x85,0x55,
+	0xB9,0xEB,0x9F,0x85,0x56,0x20,0x54,0x00,0x4C,0x8D,0xAD,
+	0xA0,0xFF,0x2C,0xA0,0x00,0x84,0x0B,0x20,0xBF,0xB1,0xA5,
+	0x64,0x45,0x0B,0x85,0x07,0xA5,0x65,0x45,0x0B,0x85,0x08,
+	0x20,0xFC,0xBB,0x20,0xBF,0xB1,0xA5,0x65,0x45,0x0B,0x25,
+	0x08,0x45,0x0B,0xA8,0xA5,0x64,0x45,0x0B,0x25,0x07,0x45,
+	0x0B,0x4C,0x91,0xB3,0x20,0x90,0xAD,0xB0,0x13,0xA5,0x6E,
+	0x09,0x7F,0x25,0x6A,0x85,0x6A,0xA9,0x69,0xA0,0x00,0x20,
+	0x5B,0xBC,0xAA,0x4C,0x61,0xB0,0xA9,0x00,0x85,0x0D,0xC6,
+	0x4D,0x20,0xA6,0xB6,0x85,0x61,0x86,0x62,0x84,0x63,0xA5,
+	0x6C,0xA4,0x6D,0x20,0xAA,0xB6,0x86,0x6C,0x84,0x6D,0xAA,
+	0x38,0xE5,0x61,0xF0,0x08,0xA9,0x01,0x90,0x04,0xA6,0x61,
+	0xA9,0xFF,0x85,0x66,0xA0,0xFF,0xE8,0xC8,0xCA,0xD0,0x07,
+	0xA6,0x66,0x30,0x0F,0x18,0x90,0x0C,0xB1,0x6C,0xD1,0x62,
+	0xF0,0xEF,0xA2,0xFF,0xB0,0x02,0xA2,0x01,0xE8,0x8A,0x2A,
+	0x25,0x12,0xF0,0x02,0xA9,0xFF,0x4C,0x3C,0xBC,0x20,0xFD,
+	0xAE,0xAA,0x20,0x90,0xB0,0x20,0x79,0x00,0xD0,0xF4,0x60,
+	0xA2,0x00,0x20,0x79,0x00,0x86,0x0C,0x85,0x45,0x20,0x79,
+	0x00,0x20,0x13,0xB1,0xB0,0x03,0x4C,0x08,0xAF,0xA2,0x00,
+	0x86,0x0D,0x86,0x0E,0x20,0x73,0x00,0x90,0x05,0x20,0x13,
+	0xB1,0x90,0x0B,0xAA,0x20,0x73,0x00,0x90,0xFB,0x20,0x13,
+	0xB1,0xB0,0xF6,0xC9,0x24,0xD0,0x06,0xA9,0xFF,0x85,0x0D,
+	0xD0,0x10,0xC9,0x25,0xD0,0x13,0xA5,0x10,0xD0,0xD0,0xA9,
+	0x80,0x85,0x0E,0x05,0x45,0x85,0x45,0x8A,0x09,0x80,0xAA,
+	0x20,0x73,0x00,0x86,0x46,0x38,0x05,0x10,0xE9,0x28,0xD0,
+	0x03,0x4C,0xD1,0xB1,0xA0,0x00,0x84,0x10,0xA5,0x2D,0xA6,
+	0x2E,0x86,0x60,0x85,0x5F,0xE4,0x30,0xD0,0x04,0xC5,0x2F,
+	0xF0,0x22,0xA5,0x45,0xD1,0x5F,0xD0,0x08,0xA5,0x46,0xC8,
+	0xD1,0x5F,0xF0,0x7D,0x88,0x18,0xA5,0x5F,0x69,0x07,0x90,
+	0xE1,0xE8,0xD0,0xDC,0xC9,0x41,0x90,0x05,0xE9,0x5B,0x38,
+	0xE9,0xA5,0x60,0x68,0x48,0xC9,0x2A,0xD0,0x05,0xA9,0x13,
+	0xA0,0xBF,0x60,0xA5,0x45,0xA4,0x46,0xC9,0x54,0xD0,0x0B,
+	0xC0,0xC9,0xF0,0xEF,0xC0,0x49,0xD0,0x03,0x4C,0x08,0xAF,
+	0xC9,0x53,0xD0,0x04,0xC0,0x54,0xF0,0xF5,0xA5,0x2F,0xA4,
+	0x30,0x85,0x5F,0x84,0x60,0xA5,0x31,0xA4,0x32,0x85,0x5A,
+	0x84,0x5B,0x18,0x69,0x07,0x90,0x01,0xC8,0x85,0x58,0x84,
+	0x59,0x20,0xB8,0xA3,0xA5,0x58,0xA4,0x59,0xC8,0x85,0x2F,
+	0x84,0x30,0xA0,0x00,0xA5,0x45,0x91,0x5F,0xC8,0xA5,0x46,
+	0x91,0x5F,0xA9,0x00,0xC8,0x91,0x5F,0xC8,0x91,0x5F,0xC8,
+	0x91,0x5F,0xC8,0x91,0x5F,0xC8,0x91,0x5F,0xA5,0x5F,0x18,
+	0x69,0x02,0xA4,0x60,0x90,0x01,0xC8,0x85,0x47,0x84,0x48,
+	0x60,0xA5,0x0B,0x0A,0x69,0x05,0x65,0x5F,0xA4,0x60,0x90,
+	0x01,0xC8,0x85,0x58,0x84,0x59,0x60,0x90,0x80,0x00,0x00,
+	0x00,0x20,0xBF,0xB1,0xA5,0x64,0xA4,0x65,0x60,0x20,0x73,
+	0x00,0x20,0x9E,0xAD,0x20,0x8D,0xAD,0xA5,0x66,0x30,0x0D,
+	0xA5,0x61,0xC9,0x90,0x90,0x09,0xA9,0xA5,0xA0,0xB1,0x20,
+	0x5B,0xBC,0xD0,0x7A,0x4C,0x9B,0xBC,0xA5,0x0C,0x05,0x0E,
+	0x48,0xA5,0x0D,0x48,0xA0,0x00,0x98,0x48,0xA5,0x46,0x48,
+	0xA5,0x45,0x48,0x20,0xB2,0xB1,0x68,0x85,0x45,0x68,0x85,
+	0x46,0x68,0xA8,0xBA,0xBD,0x02,0x01,0x48,0xBD,0x01,0x01,
+	0x48,0xA5,0x64,0x9D,0x02,0x01,0xA5,0x65,0x9D,0x01,0x01,
+	0xC8,0x20,0x79,0x00,0xC9,0x2C,0xF0,0xD2,0x84,0x0B,0x20,
+	0xF7,0xAE,0x68,0x85,0x0D,0x68,0x85,0x0E,0x29,0x7F,0x85,
+	0x0C,0xA6,0x2F,0xA5,0x30,0x86,0x5F,0x85,0x60,0xC5,0x32,
+	0xD0,0x04,0xE4,0x31,0xF0,0x39,0xA0,0x00,0xB1,0x5F,0xC8,
+	0xC5,0x45,0xD0,0x06,0xA5,0x46,0xD1,0x5F,0xF0,0x16,0xC8,
+	0xB1,0x5F,0x18,0x65,0x5F,0xAA,0xC8,0xB1,0x5F,0x65,0x60,
+	0x90,0xD7,0xA2,0x12,0x2C,0xA2,0x0E,0x4C,0x37,0xA4,0xA2,
+	0x13,0xA5,0x0C,0xD0,0xF7,0x20,0x94,0xB1,0xA5,0x0B,0xA0,
+	0x04,0xD1,0x5F,0xD0,0xE7,0x4C,0xEA,0xB2,0x20,0x94,0xB1,
+	0x20,0x08,0xA4,0xA0,0x00,0x84,0x72,0xA2,0x05,0xA5,0x45,
+	0x91,0x5F,0x10,0x01,0xCA,0xC8,0xA5,0x46,0x91,0x5F,0x10,
+	0x02,0xCA,0xCA,0x86,0x71,0xA5,0x0B,0xC8,0xC8,0xC8,0x91,
+	0x5F,0xA2,0x0B,0xA9,0x00,0x24,0x0C,0x50,0x08,0x68,0x18,
+	0x69,0x01,0xAA,0x68,0x69,0x00,0xC8,0x91,0x5F,0xC8,0x8A,
+	0x91,0x5F,0x20,0x4C,0xB3,0x86,0x71,0x85,0x72,0xA4,0x22,
+	0xC6,0x0B,0xD0,0xDC,0x65,0x59,0xB0,0x5D,0x85,0x59,0xA8,
+	0x8A,0x65,0x58,0x90,0x03,0xC8,0xF0,0x52,0x20,0x08,0xA4,
+	0x85,0x31,0x84,0x32,0xA9,0x00,0xE6,0x72,0xA4,0x71,0xF0,
+	0x05,0x88,0x91,0x58,0xD0,0xFB,0xC6,0x59,0xC6,0x72,0xD0,
+	0xF5,0xE6,0x59,0x38,0xA5,0x31,0xE5,0x5F,0xA0,0x02,0x91,
+	0x5F,0xA5,0x32,0xC8,0xE5,0x60,0x91,0x5F,0xA5,0x0C,0xD0,
+	0x62,0xC8,0xB1,0x5F,0x85,0x0B,0xA9,0x00,0x85,0x71,0x85,
+	0x72,0xC8,0x68,0xAA,0x85,0x64,0x68,0x85,0x65,0xD1,0x5F,
+	0x90,0x0E,0xD0,0x06,0xC8,0x8A,0xD1,0x5F,0x90,0x07,0x4C,
+	0x45,0xB2,0x4C,0x35,0xA4,0xC8,0xA5,0x72,0x05,0x71,0x18,
+	0xF0,0x0A,0x20,0x4C,0xB3,0x8A,0x65,0x64,0xAA,0x98,0xA4,
+	0x22,0x65,0x65,0x86,0x71,0xC6,0x0B,0xD0,0xCA,0x85,0x72,
+	0xA2,0x05,0xA5,0x45,0x10,0x01,0xCA,0xA5,0x46,0x10,0x02,
+	0xCA,0xCA,0x86,0x28,0xA9,0x00,0x20,0x55,0xB3,0x8A,0x65,
+	0x58,0x85,0x47,0x98,0x65,0x59,0x85,0x48,0xA8,0xA5,0x47,
+	0x60,0x84,0x22,0xB1,0x5F,0x85,0x28,0x88,0xB1,0x5F,0x85,
+	0x29,0xA9,0x10,0x85,0x5D,0xA2,0x00,0xA0,0x00,0x8A,0x0A,
+	0xAA,0x98,0x2A,0xA8,0xB0,0xA4,0x06,0x71,0x26,0x72,0x90,
+	0x0B,0x18,0x8A,0x65,0x28,0xAA,0x98,0x65,0x29,0xA8,0xB0,
+	0x93,0xC6,0x5D,0xD0,0xE3,0x60,0xA5,0x0D,0xF0,0x03,0x20,
+	0xA6,0xB6,0x20,0x26,0xB5,0x38,0xA5,0x33,0xE5,0x31,0xA8,
+	0xA5,0x34,0xE5,0x32,0xA2,0x00,0x86,0x0D,0x85,0x62,0x84,
+	0x63,0xA2,0x90,0x4C,0x44,0xBC,0x38,0x20,0xF0,0xFF,0xA9,
+	0x00,0xF0,0xEB,0xA6,0x3A,0xE8,0xD0,0xA0,0xA2,0x15,0x2C,
+	0xA2,0x1B,0x4C,0x37,0xA4,0x20,0xE1,0xB3,0x20,0xA6,0xB3,
+	0x20,0xFA,0xAE,0xA9,0x80,0x85,0x10,0x20,0x8B,0xB0,0x20,
+	0x8D,0xAD,0x20,0xF7,0xAE,0xA9,0xB2,0x20,0xFF,0xAE,0x48,
+	0xA5,0x48,0x48,0xA5,0x47,0x48,0xA5,0x7B,0x48,0xA5,0x7A,
+	0x48,0x20,0xF8,0xA8,0x4C,0x4F,0xB4,0xA9,0xA5,0x20,0xFF,
+	0xAE,0x09,0x80,0x85,0x10,0x20,0x92,0xB0,0x85,0x4E,0x84,
+	0x4F,0x4C,0x8D,0xAD,0x20,0xE1,0xB3,0xA5,0x4F,0x48,0xA5,
+	0x4E,0x48,0x20,0xF1,0xAE,0x20,0x8D,0xAD,0x68,0x85,0x4E,
+	0x68,0x85,0x4F,0xA0,0x02,0xB1,0x4E,0x85,0x47,0xAA,0xC8,
+	0xB1,0x4E,0xF0,0x99,0x85,0x48,0xC8,0xB1,0x47,0x48,0x88,
+	0x10,0xFA,0xA4,0x48,0x20,0xD4,0xBB,0xA5,0x7B,0x48,0xA5,
+	0x7A,0x48,0xB1,0x4E,0x85,0x7A,0xC8,0xB1,0x4E,0x85,0x7B,
+	0xA5,0x48,0x48,0xA5,0x47,0x48,0x20,0x8A,0xAD,0x68,0x85,
+	0x4E,0x68,0x85,0x4F,0x20,0x79,0x00,0xF0,0x03,0x4C,0x08,
+	0xAF,0x68,0x85,0x7A,0x68,0x85,0x7B,0xA0,0x00,0x68,0x91,
+	0x4E,0x68,0xC8,0x91,0x4E,0x68,0xC8,0x91,0x4E,0x68,0xC8,
+	0x91,0x4E,0x68,0xC8,0x91,0x4E,0x60,0x20,0x8D,0xAD,0xA0,
+	0x00,0x20,0xDF,0xBD,0x68,0x68,0xA9,0xFF,0xA0,0x00,0xF0,
+	0x12,0xA6,0x64,0xA4,0x65,0x86,0x50,0x84,0x51,0x20,0xF4,
+	0xB4,0x86,0x62,0x84,0x63,0x85,0x61,0x60,0xA2,0x22,0x86,
+	0x07,0x86,0x08,0x85,0x6F,0x84,0x70,0x85,0x62,0x84,0x63,
+	0xA0,0xFF,0xC8,0xB1,0x6F,0xF0,0x0C,0xC5,0x07,0xF0,0x04,
+	0xC5,0x08,0xD0,0xF3,0xC9,0x22,0xF0,0x01,0x18,0x84,0x61,
+	0x98,0x65,0x6F,0x85,0x71,0xA6,0x70,0x90,0x01,0xE8,0x86,
+	0x72,0xA5,0x70,0xF0,0x04,0xC9,0x02,0xD0,0x0B,0x98,0x20,
+	0x75,0xB4,0xA6,0x6F,0xA4,0x70,0x20,0x88,0xB6,0xA6,0x16,
+	0xE0,0x22,0xD0,0x05,0xA2,0x19,0x4C,0x37,0xA4,0xA5,0x61,
+	0x95,0x00,0xA5,0x62,0x95,0x01,0xA5,0x63,0x95,0x02,0xA0,
+	0x00,0x86,0x64,0x84,0x65,0x84,0x70,0x88,0x84,0x0D,0x86,
+	0x17,0xE8,0xE8,0xE8,0x86,0x16,0x60,0x46,0x0F,0x48,0x49,
+	0xFF,0x38,0x65,0x33,0xA4,0x34,0xB0,0x01,0x88,0xC4,0x32,
+	0x90,0x11,0xD0,0x04,0xC5,0x31,0x90,0x0B,0x85,0x33,0x84,
+	0x34,0x85,0x35,0x84,0x36,0xAA,0x68,0x60,0xA2,0x10,0xA5,
+	0x0F,0x30,0xB6,0x20,0x26,0xB5,0xA9,0x80,0x85,0x0F,0x68,
+	0xD0,0xD0,0xA6,0x37,0xA5,0x38,0x86,0x33,0x85,0x34,0xA0,
+	0x00,0x84,0x4F,0x84,0x4E,0xA5,0x31,0xA6,0x32,0x85,0x5F,
+	0x86,0x60,0xA9,0x19,0xA2,0x00,0x85,0x22,0x86,0x23,0xC5,
+	0x16,0xF0,0x05,0x20,0xC7,0xB5,0xF0,0xF7,0xA9,0x07,0x85,
+	0x53,0xA5,0x2D,0xA6,0x2E,0x85,0x22,0x86,0x23,0xE4,0x30,
+	0xD0,0x04,0xC5,0x2F,0xF0,0x05,0x20,0xBD,0xB5,0xF0,0xF3,
+	0x85,0x58,0x86,0x59,0xA9,0x03,0x85,0x53,0xA5,0x58,0xA6,
+	0x59,0xE4,0x32,0xD0,0x07,0xC5,0x31,0xD0,0x03,0x4C,0x06,
+	0xB6,0x85,0x22,0x86,0x23,0xA0,0x00,0xB1,0x22,0xAA,0xC8,
+	0xB1,0x22,0x08,0xC8,0xB1,0x22,0x65,0x58,0x85,0x58,0xC8,
+	0xB1,0x22,0x65,0x59,0x85,0x59,0x28,0x10,0xD3,0x8A,0x30,
+	0xD0,0xC8,0xB1,0x22,0xA0,0x00,0x0A,0x69,0x05,0x65,0x22,
+	0x85,0x22,0x90,0x02,0xE6,0x23,0xA6,0x23,0xE4,0x59,0xD0,
+	0x04,0xC5,0x58,0xF0,0xBA,0x20,0xC7,0xB5,0xF0,0xF3,0xB1,
+	0x22,0x30,0x35,0xC8,0xB1,0x22,0x10,0x30,0xC8,0xB1,0x22,
+	0xF0,0x2B,0xC8,0xB1,0x22,0xAA,0xC8,0xB1,0x22,0xC5,0x34,
+	0x90,0x06,0xD0,0x1E,0xE4,0x33,0xB0,0x1A,0xC5,0x60,0x90,
+	0x16,0xD0,0x04,0xE4,0x5F,0x90,0x10,0x86,0x5F,0x85,0x60,
+	0xA5,0x22,0xA6,0x23,0x85,0x4E,0x86,0x4F,0xA5,0x53,0x85,
+	0x55,0xA5,0x53,0x18,0x65,0x22,0x85,0x22,0x90,0x02,0xE6,
+	0x23,0xA6,0x23,0xA0,0x00,0x60,0xA5,0x4F,0x05,0x4E,0xF0,
+	0xF5,0xA5,0x55,0x29,0x04,0x4A,0xA8,0x85,0x55,0xB1,0x4E,
+	0x65,0x5F,0x85,0x5A,0xA5,0x60,0x69,0x00,0x85,0x5B,0xA5,
+	0x33,0xA6,0x34,0x85,0x58,0x86,0x59,0x20,0xBF,0xA3,0xA4,
+	0x55,0xC8,0xA5,0x58,0x91,0x4E,0xAA,0xE6,0x59,0xA5,0x59,
+	0xC8,0x91,0x4E,0x4C,0x2A,0xB5,0xA5,0x65,0x48,0xA5,0x64,
+	0x48,0x20,0x83,0xAE,0x20,0x8F,0xAD,0x68,0x85,0x6F,0x68,
+	0x85,0x70,0xA0,0x00,0xB1,0x6F,0x18,0x71,0x64,0x90,0x05,
+	0xA2,0x17,0x4C,0x37,0xA4,0x20,0x75,0xB4,0x20,0x7A,0xB6,
+	0xA5,0x50,0xA4,0x51,0x20,0xAA,0xB6,0x20,0x8C,0xB6,0xA5,
+	0x6F,0xA4,0x70,0x20,0xAA,0xB6,0x20,0xCA,0xB4,0x4C,0xB8,
+	0xAD,0xA0,0x00,0xB1,0x6F,0x48,0xC8,0xB1,0x6F,0xAA,0xC8,
+	0xB1,0x6F,0xA8,0x68,0x86,0x22,0x84,0x23,0xA8,0xF0,0x0A,
+	0x48,0x88,0xB1,0x22,0x91,0x35,0x98,0xD0,0xF8,0x68,0x18,
+	0x65,0x35,0x85,0x35,0x90,0x02,0xE6,0x36,0x60,0x20,0x8F,
+	0xAD,0xA5,0x64,0xA4,0x65,0x85,0x22,0x84,0x23,0x20,0xDB,
+	0xB6,0x08,0xA0,0x00,0xB1,0x22,0x48,0xC8,0xB1,0x22,0xAA,
+	0xC8,0xB1,0x22,0xA8,0x68,0x28,0xD0,0x13,0xC4,0x34,0xD0,
+	0x0F,0xE4,0x33,0xD0,0x0B,0x48,0x18,0x65,0x33,0x85,0x33,
+	0x90,0x02,0xE6,0x34,0x68,0x86,0x22,0x84,0x23,0x60,0xC4,
+	0x18,0xD0,0x0C,0xC5,0x17,0xD0,0x08,0x85,0x16,0xE9,0x03,
+	0x85,0x17,0xA0,0x00,0x60,0x20,0xA1,0xB7,0x8A,0x48,0xA9,
+	0x01,0x20,0x7D,0xB4,0x68,0xA0,0x00,0x91,0x62,0x68,0x68,
+	0x4C,0xCA,0xB4,0x20,0x61,0xB7,0xD1,0x50,0x98,0x90,0x04,
+	0xB1,0x50,0xAA,0x98,0x48,0x8A,0x48,0x20,0x7D,0xB4,0xA5,
+	0x50,0xA4,0x51,0x20,0xAA,0xB6,0x68,0xA8,0x68,0x18,0x65,
+	0x22,0x85,0x22,0x90,0x02,0xE6,0x23,0x98,0x20,0x8C,0xB6,
+	0x4C,0xCA,0xB4,0x20,0x61,0xB7,0x18,0xF1,0x50,0x49,0xFF,
+	0x4C,0x06,0xB7,0xA9,0xFF,0x85,0x65,0x20,0x79,0x00,0xC9,
+	0x29,0xF0,0x06,0x20,0xFD,0xAE,0x20,0x9E,0xB7,0x20,0x61,
+	0xB7,0xF0,0x4B,0xCA,0x8A,0x48,0x18,0xA2,0x00,0xF1,0x50,
+	0xB0,0xB6,0x49,0xFF,0xC5,0x65,0x90,0xB1,0xA5,0x65,0xB0,
+	0xAD,0x20,0xF7,0xAE,0x68,0xA8,0x68,0x85,0x55,0x68,0x68,
+	0x68,0xAA,0x68,0x85,0x50,0x68,0x85,0x51,0xA5,0x55,0x48,
+	0x98,0x48,0xA0,0x00,0x8A,0x60,0x20,0x82,0xB7,0x4C,0xA2,
+	0xB3,0x20,0xA3,0xB6,0xA2,0x00,0x86,0x0D,0xA8,0x60,0x20,
+	0x82,0xB7,0xF0,0x08,0xA0,0x00,0xB1,0x22,0xA8,0x4C,0xA2,
+	0xB3,0x4C,0x48,0xB2,0x20,0x73,0x00,0x20,0x8A,0xAD,0x20,
+	0xB8,0xB1,0xA6,0x64,0xD0,0xF0,0xA6,0x65,0x4C,0x79,0x00,
+	0x20,0x82,0xB7,0xD0,0x03,0x4C,0xF7,0xB8,0xA6,0x7A,0xA4,
+	0x7B,0x86,0x71,0x84,0x72,0xA6,0x22,0x86,0x7A,0x18,0x65,
+	0x22,0x85,0x24,0xA6,0x23,0x86,0x7B,0x90,0x01,0xE8,0x86,
+	0x25,0xA0,0x00,0xB1,0x24,0x48,0x98,0x91,0x24,0x20,0x79,
+	0x00,0x20,0xF3,0xBC,0x68,0xA0,0x00,0x91,0x24,0xA6,0x71,
+	0xA4,0x72,0x86,0x7A,0x84,0x7B,0x60,0x20,0x8A,0xAD,0x20,
+	0xF7,0xB7,0x20,0xFD,0xAE,0x4C,0x9E,0xB7,0xA5,0x66,0x30,
+	0x9D,0xA5,0x61,0xC9,0x91,0xB0,0x97,0x20,0x9B,0xBC,0xA5,
+	0x64,0xA4,0x65,0x84,0x14,0x85,0x15,0x60,0xA5,0x15,0x48,
+	0xA5,0x14,0x48,0x20,0xF7,0xB7,0xA0,0x00,0xB1,0x14,0xA8,
+	0x68,0x85,0x14,0x68,0x85,0x15,0x4C,0xA2,0xB3,0x20,0xEB,
+	0xB7,0x8A,0xA0,0x00,0x91,0x14,0x60,0x20,0xEB,0xB7,0x86,
+	0x49,0xA2,0x00,0x20,0x79,0x00,0xF0,0x03,0x20,0xF1,0xB7,
+	0x86,0x4A,0xA0,0x00,0xB1,0x14,0x45,0x4A,0x25,0x49,0xF0,
+	0xF8,0x60,0xA9,0x11,0xA0,0xBF,0x4C,0x67,0xB8,0x20,0x8C,
+	0xBA,0xA5,0x66,0x49,0xFF,0x85,0x66,0x45,0x6E,0x85,0x6F,
+	0xA5,0x61,0x4C,0x6A,0xB8,0x20,0x99,0xB9,0x90,0x3C,0x20,
+	0x8C,0xBA,0xD0,0x03,0x4C,0xFC,0xBB,0xA6,0x70,0x86,0x56,
+	0xA2,0x69,0xA5,0x69,0xA8,0xF0,0xCE,0x38,0xE5,0x61,0xF0,
+	0x24,0x90,0x12,0x84,0x61,0xA4,0x6E,0x84,0x66,0x49,0xFF,
+	0x69,0x00,0xA0,0x00,0x84,0x56,0xA2,0x61,0xD0,0x04,0xA0,
+	0x00,0x84,0x70,0xC9,0xF9,0x30,0xC7,0xA8,0xA5,0x70,0x56,
+	0x01,0x20,0xB0,0xB9,0x24,0x6F,0x10,0x57,0xA0,0x61,0xE0,
+	0x69,0xF0,0x02,0xA0,0x69,0x38,0x49,0xFF,0x65,0x56,0x85,
+	0x70,0xB9,0x04,0x00,0xF5,0x04,0x85,0x65,0xB9,0x03,0x00,
+	0xF5,0x03,0x85,0x64,0xB9,0x02,0x00,0xF5,0x02,0x85,0x63,
+	0xB9,0x01,0x00,0xF5,0x01,0x85,0x62,0xB0,0x03,0x20,0x47,
+	0xB9,0xA0,0x00,0x98,0x18,0xA6,0x62,0xD0,0x4A,0xA6,0x63,
+	0x86,0x62,0xA6,0x64,0x86,0x63,0xA6,0x65,0x86,0x64,0xA6,
+	0x70,0x86,0x65,0x84,0x70,0x69,0x08,0xC9,0x20,0xD0,0xE4,
+	0xA9,0x00,0x85,0x61,0x85,0x66,0x60,0x65,0x56,0x85,0x70,
+	0xA5,0x65,0x65,0x6D,0x85,0x65,0xA5,0x64,0x65,0x6C,0x85,
+	0x64,0xA5,0x63,0x65,0x6B,0x85,0x63,0xA5,0x62,0x65,0x6A,
+	0x85,0x62,0x4C,0x36,0xB9,0x69,0x01,0x06,0x70,0x26,0x65,
+	0x26,0x64,0x26,0x63,0x26,0x62,0x10,0xF2,0x38,0xE5,0x61,
+	0xB0,0xC7,0x49,0xFF,0x69,0x01,0x85,0x61,0x90,0x0E,0xE6,
+	0x61,0xF0,0x42,0x66,0x62,0x66,0x63,0x66,0x64,0x66,0x65,
+	0x66,0x70,0x60,0xA5,0x66,0x49,0xFF,0x85,0x66,0xA5,0x62,
+	0x49,0xFF,0x85,0x62,0xA5,0x63,0x49,0xFF,0x85,0x63,0xA5,
+	0x64,0x49,0xFF,0x85,0x64,0xA5,0x65,0x49,0xFF,0x85,0x65,
+	0xA5,0x70,0x49,0xFF,0x85,0x70,0xE6,0x70,0xD0,0x0E,0xE6,
+	0x65,0xD0,0x0A,0xE6,0x64,0xD0,0x06,0xE6,0x63,0xD0,0x02,
+	0xE6,0x62,0x60,0xA2,0x0F,0x4C,0x37,0xA4,0xA2,0x25,0xB4,
+	0x04,0x84,0x70,0xB4,0x03,0x94,0x04,0xB4,0x02,0x94,0x03,
+	0xB4,0x01,0x94,0x02,0xA4,0x68,0x94,0x01,0x69,0x08,0x30,
+	0xE8,0xF0,0xE6,0xE9,0x08,0xA8,0xA5,0x70,0xB0,0x14,0x16,
+	0x01,0x90,0x02,0xF6,0x01,0x76,0x01,0x76,0x01,0x76,0x02,
+	0x76,0x03,0x76,0x04,0x6A,0xC8,0xD0,0xEC,0x18,0x60,0x81,
+	0x00,0x00,0x00,0x00,0x03,0x7F,0x5E,0x56,0xCB,0x79,0x80,
+	0x13,0x9B,0x0B,0x64,0x80,0x76,0x38,0x93,0x16,0x82,0x38,
+	0xAA,0x3B,0x20,0x80,0x35,0x04,0xF3,0x34,0x81,0x35,0x04,
+	0xF3,0x34,0x80,0x80,0x00,0x00,0x00,0x80,0x31,0x72,0x17,
+	0xF8,0x20,0x2B,0xBC,0xF0,0x02,0x10,0x03,0x4C,0x48,0xB2,
+	0xA5,0x61,0xE9,0x7F,0x48,0xA9,0x80,0x85,0x61,0xA9,0xD6,
+	0xA0,0xB9,0x20,0x67,0xB8,0xA9,0xDB,0xA0,0xB9,0x20,0x0F,
+	0xBB,0xA9,0xBC,0xA0,0xB9,0x20,0x50,0xB8,0xA9,0xC1,0xA0,
+	0xB9,0x20,0x43,0xE0,0xA9,0xE0,0xA0,0xB9,0x20,0x67,0xB8,
+	0x68,0x20,0x7E,0xBD,0xA9,0xE5,0xA0,0xB9,0x20,0x8C,0xBA,
+	0xD0,0x03,0x4C,0x8B,0xBA,0x20,0xB7,0xBA,0xA9,0x00,0x85,
+	0x26,0x85,0x27,0x85,0x28,0x85,0x29,0xA5,0x70,0x20,0x59,
+	0xBA,0xA5,0x65,0x20,0x59,0xBA,0xA5,0x64,0x20,0x59,0xBA,
+	0xA5,0x63,0x20,0x59,0xBA,0xA5,0x62,0x20,0x5E,0xBA,0x4C,
+	0x8F,0xBB,0xD0,0x03,0x4C,0x83,0xB9,0x4A,0x09,0x80,0xA8,
+	0x90,0x19,0x18,0xA5,0x29,0x65,0x6D,0x85,0x29,0xA5,0x28,
+	0x65,0x6C,0x85,0x28,0xA5,0x27,0x65,0x6B,0x85,0x27,0xA5,
+	0x26,0x65,0x6A,0x85,0x26,0x66,0x26,0x66,0x27,0x66,0x28,
+	0x66,0x29,0x66,0x70,0x98,0x4A,0xD0,0xD6,0x60,0x85,0x22,
+	0x84,0x23,0xA0,0x04,0xB1,0x22,0x85,0x6D,0x88,0xB1,0x22,
+	0x85,0x6C,0x88,0xB1,0x22,0x85,0x6B,0x88,0xB1,0x22,0x85,
+	0x6E,0x45,0x66,0x85,0x6F,0xA5,0x6E,0x09,0x80,0x85,0x6A,
+	0x88,0xB1,0x22,0x85,0x69,0xA5,0x61,0x60,0xA5,0x69,0xF0,
+	0x1F,0x18,0x65,0x61,0x90,0x04,0x30,0x1D,0x18,0x2C,0x10,
+	0x14,0x69,0x80,0x85,0x61,0xD0,0x03,0x4C,0xFB,0xB8,0xA5,
+	0x6F,0x85,0x66,0x60,0xA5,0x66,0x49,0xFF,0x30,0x05,0x68,
+	0x68,0x4C,0xF7,0xB8,0x4C,0x7E,0xB9,0x20,0x0C,0xBC,0xAA,
+	0xF0,0x10,0x18,0x69,0x02,0xB0,0xF2,0xA2,0x00,0x86,0x6F,
+	0x20,0x77,0xB8,0xE6,0x61,0xF0,0xE7,0x60,0x84,0x20,0x00,
+	0x00,0x00,0x20,0x0C,0xBC,0xA9,0xF9,0xA0,0xBA,0xA2,0x00,
+	0x86,0x6F,0x20,0xA2,0xBB,0x4C,0x12,0xBB,0x20,0x8C,0xBA,
+	0xF0,0x76,0x20,0x1B,0xBC,0xA9,0x00,0x38,0xE5,0x61,0x85,
+	0x61,0x20,0xB7,0xBA,0xE6,0x61,0xF0,0xBA,0xA2,0xFC,0xA9,
+	0x01,0xA4,0x6A,0xC4,0x62,0xD0,0x10,0xA4,0x6B,0xC4,0x63,
+	0xD0,0x0A,0xA4,0x6C,0xC4,0x64,0xD0,0x04,0xA4,0x6D,0xC4,
+	0x65,0x08,0x2A,0x90,0x09,0xE8,0x95,0x29,0xF0,0x32,0x10,
+	0x34,0xA9,0x01,0x28,0xB0,0x0E,0x06,0x6D,0x26,0x6C,0x26,
+	0x6B,0x26,0x6A,0xB0,0xE6,0x30,0xCE,0x10,0xE2,0xA8,0xA5,
+	0x6D,0xE5,0x65,0x85,0x6D,0xA5,0x6C,0xE5,0x64,0x85,0x6C,
+	0xA5,0x6B,0xE5,0x63,0x85,0x6B,0xA5,0x6A,0xE5,0x62,0x85,
+	0x6A,0x98,0x4C,0x4F,0xBB,0xA9,0x40,0xD0,0xCE,0x0A,0x0A,
+	0x0A,0x0A,0x0A,0x0A,0x85,0x70,0x28,0x4C,0x8F,0xBB,0xA2,
+	0x14,0x4C,0x37,0xA4,0xA5,0x26,0x85,0x62,0xA5,0x27,0x85,
+	0x63,0xA5,0x28,0x85,0x64,0xA5,0x29,0x85,0x65,0x4C,0xD7,
+	0xB8,0x85,0x22,0x84,0x23,0xA0,0x04,0xB1,0x22,0x85,0x65,
+	0x88,0xB1,0x22,0x85,0x64,0x88,0xB1,0x22,0x85,0x63,0x88,
+	0xB1,0x22,0x85,0x66,0x09,0x80,0x85,0x62,0x88,0xB1,0x22,
+	0x85,0x61,0x84,0x70,0x60,0xA2,0x5C,0x2C,0xA2,0x57,0xA0,
+	0x00,0xF0,0x04,0xA6,0x49,0xA4,0x4A,0x20,0x1B,0xBC,0x86,
+	0x22,0x84,0x23,0xA0,0x04,0xA5,0x65,0x91,0x22,0x88,0xA5,
+	0x64,0x91,0x22,0x88,0xA5,0x63,0x91,0x22,0x88,0xA5,0x66,
+	0x09,0x7F,0x25,0x62,0x91,0x22,0x88,0xA5,0x61,0x91,0x22,
+	0x84,0x70,0x60,0xA5,0x6E,0x85,0x66,0xA2,0x05,0xB5,0x68,
+	0x95,0x60,0xCA,0xD0,0xF9,0x86,0x70,0x60,0x20,0x1B,0xBC,
+	0xA2,0x06,0xB5,0x60,0x95,0x68,0xCA,0xD0,0xF9,0x86,0x70,
+	0x60,0xA5,0x61,0xF0,0xFB,0x06,0x70,0x90,0xF7,0x20,0x6F,
+	0xB9,0xD0,0xF2,0x4C,0x38,0xB9,0xA5,0x61,0xF0,0x09,0xA5,
+	0x66,0x2A,0xA9,0xFF,0xB0,0x02,0xA9,0x01,0x60,0x20,0x2B,
+	0xBC,0x85,0x62,0xA9,0x00,0x85,0x63,0xA2,0x88,0xA5,0x62,
+	0x49,0xFF,0x2A,0xA9,0x00,0x85,0x65,0x85,0x64,0x86,0x61,
+	0x85,0x70,0x85,0x66,0x4C,0xD2,0xB8,0x46,0x66,0x60,0x85,
+	0x24,0x84,0x25,0xA0,0x00,0xB1,0x24,0xC8,0xAA,0xF0,0xC4,
+	0xB1,0x24,0x45,0x66,0x30,0xC2,0xE4,0x61,0xD0,0x21,0xB1,
+	0x24,0x09,0x80,0xC5,0x62,0xD0,0x19,0xC8,0xB1,0x24,0xC5,
+	0x63,0xD0,0x12,0xC8,0xB1,0x24,0xC5,0x64,0xD0,0x0B,0xC8,
+	0xA9,0x7F,0xC5,0x70,0xB1,0x24,0xE5,0x65,0xF0,0x28,0xA5,
+	0x66,0x90,0x02,0x49,0xFF,0x4C,0x31,0xBC,0xA5,0x61,0xF0,
+	0x4A,0x38,0xE9,0xA0,0x24,0x66,0x10,0x09,0xAA,0xA9,0xFF,
+	0x85,0x68,0x20,0x4D,0xB9,0x8A,0xA2,0x61,0xC9,0xF9,0x10,
+	0x06,0x20,0x99,0xB9,0x84,0x68,0x60,0xA8,0xA5,0x66,0x29,
+	0x80,0x46,0x62,0x05,0x62,0x85,0x62,0x20,0xB0,0xB9,0x84,
+	0x68,0x60,0xA5,0x61,0xC9,0xA0,0xB0,0x20,0x20,0x9B,0xBC,
+	0x84,0x70,0xA5,0x66,0x84,0x66,0x49,0x80,0x2A,0xA9,0xA0,
+	0x85,0x61,0xA5,0x65,0x85,0x07,0x4C,0xD2,0xB8,0x85,0x62,
+	0x85,0x63,0x85,0x64,0x85,0x65,0xA8,0x60,0xA0,0x00,0xA2,
+	0x0A,0x94,0x5D,0xCA,0x10,0xFB,0x90,0x0F,0xC9,0x2D,0xD0,
+	0x04,0x86,0x67,0xF0,0x04,0xC9,0x2B,0xD0,0x05,0x20,0x73,
+	0x00,0x90,0x5B,0xC9,0x2E,0xF0,0x2E,0xC9,0x45,0xD0,0x30,
+	0x20,0x73,0x00,0x90,0x17,0xC9,0xAB,0xF0,0x0E,0xC9,0x2D,
+	0xF0,0x0A,0xC9,0xAA,0xF0,0x08,0xC9,0x2B,0xF0,0x04,0xD0,
+	0x07,0x66,0x60,0x20,0x73,0x00,0x90,0x5C,0x24,0x60,0x10,
+	0x0E,0xA9,0x00,0x38,0xE5,0x5E,0x4C,0x49,0xBD,0x66,0x5F,
+	0x24,0x5F,0x50,0xC3,0xA5,0x5E,0x38,0xE5,0x5D,0x85,0x5E,
+	0xF0,0x12,0x10,0x09,0x20,0xFE,0xBA,0xE6,0x5E,0xD0,0xF9,
+	0xF0,0x07,0x20,0xE2,0xBA,0xC6,0x5E,0xD0,0xF9,0xA5,0x67,
+	0x30,0x01,0x60,0x4C,0xB4,0xBF,0x48,0x24,0x5F,0x10,0x02,
+	0xE6,0x5D,0x20,0xE2,0xBA,0x68,0x38,0xE9,0x30,0x20,0x7E,
+	0xBD,0x4C,0x0A,0xBD,0x48,0x20,0x0C,0xBC,0x68,0x20,0x3C,
+	0xBC,0xA5,0x6E,0x45,0x66,0x85,0x6F,0xA6,0x61,0x4C,0x6A,
+	0xB8,0xA5,0x5E,0xC9,0x0A,0x90,0x09,0xA9,0x64,0x24,0x60,
+	0x30,0x11,0x4C,0x7E,0xB9,0x0A,0x0A,0x18,0x65,0x5E,0x0A,
+	0x18,0xA0,0x00,0x71,0x7A,0x38,0xE9,0x30,0x85,0x5E,0x4C,
+	0x30,0xBD,0x9B,0x3E,0xBC,0x1F,0xFD,0x9E,0x6E,0x6B,0x27,
+	0xFD,0x9E,0x6E,0x6B,0x28,0x00,0xA9,0x71,0xA0,0xA3,0x20,
+	0xDA,0xBD,0xA5,0x3A,0xA6,0x39,0x85,0x62,0x86,0x63,0xA2,
+	0x90,0x38,0x20,0x49,0xBC,0x20,0xDF,0xBD,0x4C,0x1E,0xAB,
+	0xA0,0x01,0xA9,0x20,0x24,0x66,0x10,0x02,0xA9,0x2D,0x99,
+	0xFF,0x00,0x85,0x66,0x84,0x71,0xC8,0xA9,0x30,0xA6,0x61,
+	0xD0,0x03,0x4C,0x04,0xBF,0xA9,0x00,0xE0,0x80,0xF0,0x02,
+	0xB0,0x09,0xA9,0xBD,0xA0,0xBD,0x20,0x28,0xBA,0xA9,0xF7,
+	0x85,0x5D,0xA9,0xB8,0xA0,0xBD,0x20,0x5B,0xBC,0xF0,0x1E,
+	0x10,0x12,0xA9,0xB3,0xA0,0xBD,0x20,0x5B,0xBC,0xF0,0x02,
+	0x10,0x0E,0x20,0xE2,0xBA,0xC6,0x5D,0xD0,0xEE,0x20,0xFE,
+	0xBA,0xE6,0x5D,0xD0,0xDC,0x20,0x49,0xB8,0x20,0x9B,0xBC,
+	0xA2,0x01,0xA5,0x5D,0x18,0x69,0x0A,0x30,0x09,0xC9,0x0B,
+	0xB0,0x06,0x69,0xFF,0xAA,0xA9,0x02,0x38,0xE9,0x02,0x85,
+	0x5E,0x86,0x5D,0x8A,0xF0,0x02,0x10,0x13,0xA4,0x71,0xA9,
+	0x2E,0xC8,0x99,0xFF,0x00,0x8A,0xF0,0x06,0xA9,0x30,0xC8,
+	0x99,0xFF,0x00,0x84,0x71,0xA0,0x00,0xA2,0x80,0xA5,0x65,
+	0x18,0x79,0x19,0xBF,0x85,0x65,0xA5,0x64,0x79,0x18,0xBF,
+	0x85,0x64,0xA5,0x63,0x79,0x17,0xBF,0x85,0x63,0xA5,0x62,
+	0x79,0x16,0xBF,0x85,0x62,0xE8,0xB0,0x04,0x10,0xDE,0x30,
+	0x02,0x30,0xDA,0x8A,0x90,0x04,0x49,0xFF,0x69,0x0A,0x69,
+	0x2F,0xC8,0xC8,0xC8,0xC8,0x84,0x47,0xA4,0x71,0xC8,0xAA,
+	0x29,0x7F,0x99,0xFF,0x00,0xC6,0x5D,0xD0,0x06,0xA9,0x2E,
+	0xC8,0x99,0xFF,0x00,0x84,0x71,0xA4,0x47,0x8A,0x49,0xFF,
+	0x29,0x80,0xAA,0xC0,0x24,0xF0,0x04,0xC0,0x3C,0xD0,0xA6,
+	0xA4,0x71,0xB9,0xFF,0x00,0x88,0xC9,0x30,0xF0,0xF8,0xC9,
+	0x2E,0xF0,0x01,0xC8,0xA9,0x2B,0xA6,0x5E,0xF0,0x2E,0x10,
+	0x08,0xA9,0x00,0x38,0xE5,0x5E,0xAA,0xA9,0x2D,0x99,0x01,
+	0x01,0xA9,0x45,0x99,0x00,0x01,0x8A,0xA2,0x2F,0x38,0xE8,
+	0xE9,0x0A,0xB0,0xFB,0x69,0x3A,0x99,0x03,0x01,0x8A,0x99,
+	0x02,0x01,0xA9,0x00,0x99,0x04,0x01,0xF0,0x08,0x99,0xFF,
+	0x00,0xA9,0x00,0x99,0x00,0x01,0xA9,0x00,0xA0,0x01,0x60,
+	0x80,0x00,0x00,0x00,0x00,0xFA,0x0A,0x1F,0x00,0x00,0x98,
+	0x96,0x80,0xFF,0xF0,0xBD,0xC0,0x00,0x01,0x86,0xA0,0xFF,
+	0xFF,0xD8,0xF0,0x00,0x00,0x03,0xE8,0xFF,0xFF,0xFF,0x9C,
+	0x00,0x00,0x00,0x0A,0xFF,0xFF,0xFF,0xFF,0xFF,0xDF,0x0A,
+	0x80,0x00,0x03,0x4B,0xC0,0xFF,0xFF,0x73,0x60,0x00,0x00,
+	0x0E,0x10,0xFF,0xFF,0xFD,0xA8,0x00,0x00,0x00,0x3C,0xEC,
+	0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+	0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+	0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0x20,0x0C,0xBC,
+	0xA9,0x11,0xA0,0xBF,0x20,0xA2,0xBB,0xF0,0x70,0xA5,0x69,
+	0xD0,0x03,0x4C,0xF9,0xB8,0xA2,0x4E,0xA0,0x00,0x20,0xD4,
+	0xBB,0xA5,0x6E,0x10,0x0F,0x20,0xCC,0xBC,0xA9,0x4E,0xA0,
+	0x00,0x20,0x5B,0xBC,0xD0,0x03,0x98,0xA4,0x07,0x20,0xFE,
+	0xBB,0x98,0x48,0x20,0xEA,0xB9,0xA9,0x4E,0xA0,0x00,0x20,
+	0x28,0xBA,0x20,0xED,0xBF,0x68,0x4A,0x90,0x0A,0xA5,0x61,
+	0xF0,0x06,0xA5,0x66,0x49,0xFF,0x85,0x66,0x60,0x81,0x38,
+	0xAA,0x3B,0x29,0x07,0x71,0x34,0x58,0x3E,0x56,0x74,0x16,
+	0x7E,0xB3,0x1B,0x77,0x2F,0xEE,0xE3,0x85,0x7A,0x1D,0x84,
+	0x1C,0x2A,0x7C,0x63,0x59,0x58,0x0A,0x7E,0x75,0xFD,0xE7,
+	0xC6,0x80,0x31,0x72,0x18,0x10,0x81,0x00,0x00,0x00,0x00,
+	0xA9,0xBF,0xA0,0xBF,0x20,0x28,0xBA,0xA5,0x70,0x69,0x50,
+	0x90,0x03,0x20,0x23,0xBC,0x4C,0x00,0xE0,
+};
+//file auto-generated from kernal.901227-03.bin by bin2h.exe
+const size_t rom_kernal_len = 8192;
+const unsigned char PROGMEM rom_kernal[8192]=
+{
+	0x85,0x56,0x20,0x0F,0xBC,0xA5,0x61,0xC9,0x88,0x90,0x03,
+	0x20,0xD4,0xBA,0x20,0xCC,0xBC,0xA5,0x07,0x18,0x69,0x81,
+	0xF0,0xF3,0x38,0xE9,0x01,0x48,0xA2,0x05,0xB5,0x69,0xB4,
+	0x61,0x95,0x61,0x94,0x69,0xCA,0x10,0xF5,0xA5,0x56,0x85,
+	0x70,0x20,0x53,0xB8,0x20,0xB4,0xBF,0xA9,0xC4,0xA0,0xBF,
+	0x20,0x59,0xE0,0xA9,0x00,0x85,0x6F,0x68,0x20,0xB9,0xBA,
+	0x60,0x85,0x71,0x84,0x72,0x20,0xCA,0xBB,0xA9,0x57,0x20,
+	0x28,0xBA,0x20,0x5D,0xE0,0xA9,0x57,0xA0,0x00,0x4C,0x28,
+	0xBA,0x85,0x71,0x84,0x72,0x20,0xC7,0xBB,0xB1,0x71,0x85,
+	0x67,0xA4,0x71,0xC8,0x98,0xD0,0x02,0xE6,0x72,0x85,0x71,
+	0xA4,0x72,0x20,0x28,0xBA,0xA5,0x71,0xA4,0x72,0x18,0x69,
+	0x05,0x90,0x01,0xC8,0x85,0x71,0x84,0x72,0x20,0x67,0xB8,
+	0xA9,0x5C,0xA0,0x00,0xC6,0x67,0xD0,0xE4,0x60,0x98,0x35,
+	0x44,0x7A,0x00,0x68,0x28,0xB1,0x46,0x00,0x20,0x2B,0xBC,
+	0x30,0x37,0xD0,0x20,0x20,0xF3,0xFF,0x86,0x22,0x84,0x23,
+	0xA0,0x04,0xB1,0x22,0x85,0x62,0xC8,0xB1,0x22,0x85,0x64,
+	0xA0,0x08,0xB1,0x22,0x85,0x63,0xC8,0xB1,0x22,0x85,0x65,
+	0x4C,0xE3,0xE0,0xA9,0x8B,0xA0,0x00,0x20,0xA2,0xBB,0xA9,
+	0x8D,0xA0,0xE0,0x20,0x28,0xBA,0xA9,0x92,0xA0,0xE0,0x20,
+	0x67,0xB8,0xA6,0x65,0xA5,0x62,0x85,0x65,0x86,0x62,0xA6,
+	0x63,0xA5,0x64,0x85,0x63,0x86,0x64,0xA9,0x00,0x85,0x66,
+	0xA5,0x61,0x85,0x70,0xA9,0x80,0x85,0x61,0x20,0xD7,0xB8,
+	0xA2,0x8B,0xA0,0x00,0x4C,0xD4,0xBB,0xC9,0xF0,0xD0,0x07,
+	0x84,0x38,0x86,0x37,0x4C,0x63,0xA6,0xAA,0xD0,0x02,0xA2,
+	0x1E,0x4C,0x37,0xA4,0x20,0xD2,0xFF,0xB0,0xE8,0x60,0x20,
+	0xCF,0xFF,0xB0,0xE2,0x60,0x20,0xAD,0xE4,0xB0,0xDC,0x60,
+	0x20,0xC6,0xFF,0xB0,0xD6,0x60,0x20,0xE4,0xFF,0xB0,0xD0,
+	0x60,0x20,0x8A,0xAD,0x20,0xF7,0xB7,0xA9,0xE1,0x48,0xA9,
+	0x46,0x48,0xAD,0x0F,0x03,0x48,0xAD,0x0C,0x03,0xAE,0x0D,
+	0x03,0xAC,0x0E,0x03,0x28,0x6C,0x14,0x00,0x08,0x8D,0x0C,
+	0x03,0x8E,0x0D,0x03,0x8C,0x0E,0x03,0x68,0x8D,0x0F,0x03,
+	0x60,0x20,0xD4,0xE1,0xA6,0x2D,0xA4,0x2E,0xA9,0x2B,0x20,
+	0xD8,0xFF,0xB0,0x95,0x60,0xA9,0x01,0x2C,0xA9,0x00,0x85,
+	0x0A,0x20,0xD4,0xE1,0xA5,0x0A,0xA6,0x2B,0xA4,0x2C,0x20,
+	0xD5,0xFF,0xB0,0x57,0xA5,0x0A,0xF0,0x17,0xA2,0x1C,0x20,
+	0xB7,0xFF,0x29,0x10,0xD0,0x17,0xA5,0x7A,0xC9,0x02,0xF0,
+	0x07,0xA9,0x64,0xA0,0xA3,0x4C,0x1E,0xAB,0x60,0x20,0xB7,
+	0xFF,0x29,0xBF,0xF0,0x05,0xA2,0x1D,0x4C,0x37,0xA4,0xA5,
+	0x7B,0xC9,0x02,0xD0,0x0E,0x86,0x2D,0x84,0x2E,0xA9,0x76,
+	0xA0,0xA3,0x20,0x1E,0xAB,0x4C,0x2A,0xA5,0x20,0x8E,0xA6,
+	0x20,0x33,0xA5,0x4C,0x77,0xA6,0x20,0x19,0xE2,0x20,0xC0,
+	0xFF,0xB0,0x0B,0x60,0x20,0x19,0xE2,0xA5,0x49,0x20,0xC3,
+	0xFF,0x90,0xC3,0x4C,0xF9,0xE0,0xA9,0x00,0x20,0xBD,0xFF,
+	0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x06,0xE2,0x20,
+	0x57,0xE2,0x20,0x06,0xE2,0x20,0x00,0xE2,0xA0,0x00,0x86,
+	0x49,0x20,0xBA,0xFF,0x20,0x06,0xE2,0x20,0x00,0xE2,0x8A,
+	0xA8,0xA6,0x49,0x4C,0xBA,0xFF,0x20,0x0E,0xE2,0x4C,0x9E,
+	0xB7,0x20,0x79,0x00,0xD0,0x02,0x68,0x68,0x60,0x20,0xFD,
+	0xAE,0x20,0x79,0x00,0xD0,0xF7,0x4C,0x08,0xAF,0xA9,0x00,
+	0x20,0xBD,0xFF,0x20,0x11,0xE2,0x20,0x9E,0xB7,0x86,0x49,
+	0x8A,0xA2,0x01,0xA0,0x00,0x20,0xBA,0xFF,0x20,0x06,0xE2,
+	0x20,0x00,0xE2,0x86,0x4A,0xA0,0x00,0xA5,0x49,0xE0,0x03,
+	0x90,0x01,0x88,0x20,0xBA,0xFF,0x20,0x06,0xE2,0x20,0x00,
+	0xE2,0x8A,0xA8,0xA6,0x4A,0xA5,0x49,0x20,0xBA,0xFF,0x20,
+	0x06,0xE2,0x20,0x0E,0xE2,0x20,0x9E,0xAD,0x20,0xA3,0xB6,
+	0xA6,0x22,0xA4,0x23,0x4C,0xBD,0xFF,0xA9,0xE0,0xA0,0xE2,
+	0x20,0x67,0xB8,0x20,0x0C,0xBC,0xA9,0xE5,0xA0,0xE2,0xA6,
+	0x6E,0x20,0x07,0xBB,0x20,0x0C,0xBC,0x20,0xCC,0xBC,0xA9,
+	0x00,0x85,0x6F,0x20,0x53,0xB8,0xA9,0xEA,0xA0,0xE2,0x20,
+	0x50,0xB8,0xA5,0x66,0x48,0x10,0x0D,0x20,0x49,0xB8,0xA5,
+	0x66,0x30,0x09,0xA5,0x12,0x49,0xFF,0x85,0x12,0x20,0xB4,
+	0xBF,0xA9,0xEA,0xA0,0xE2,0x20,0x67,0xB8,0x68,0x10,0x03,
+	0x20,0xB4,0xBF,0xA9,0xEF,0xA0,0xE2,0x4C,0x43,0xE0,0x20,
+	0xCA,0xBB,0xA9,0x00,0x85,0x12,0x20,0x6B,0xE2,0xA2,0x4E,
+	0xA0,0x00,0x20,0xF6,0xE0,0xA9,0x57,0xA0,0x00,0x20,0xA2,
+	0xBB,0xA9,0x00,0x85,0x66,0xA5,0x12,0x20,0xDC,0xE2,0xA9,
+	0x4E,0xA0,0x00,0x4C,0x0F,0xBB,0x48,0x4C,0x9D,0xE2,0x81,
+	0x49,0x0F,0xDA,0xA2,0x83,0x49,0x0F,0xDA,0xA2,0x7F,0x00,
+	0x00,0x00,0x00,0x05,0x84,0xE6,0x1A,0x2D,0x1B,0x86,0x28,
+	0x07,0xFB,0xF8,0x87,0x99,0x68,0x89,0x01,0x87,0x23,0x35,
+	0xDF,0xE1,0x86,0xA5,0x5D,0xE7,0x28,0x83,0x49,0x0F,0xDA,
+	0xA2,0xA5,0x66,0x48,0x10,0x03,0x20,0xB4,0xBF,0xA5,0x61,
+	0x48,0xC9,0x81,0x90,0x07,0xA9,0xBC,0xA0,0xB9,0x20,0x0F,
+	0xBB,0xA9,0x3E,0xA0,0xE3,0x20,0x43,0xE0,0x68,0xC9,0x81,
+	0x90,0x07,0xA9,0xE0,0xA0,0xE2,0x20,0x50,0xB8,0x68,0x10,
+	0x03,0x4C,0xB4,0xBF,0x60,0x0B,0x76,0xB3,0x83,0xBD,0xD3,
+	0x79,0x1E,0xF4,0xA6,0xF5,0x7B,0x83,0xFC,0xB0,0x10,0x7C,
+	0x0C,0x1F,0x67,0xCA,0x7C,0xDE,0x53,0xCB,0xC1,0x7D,0x14,
+	0x64,0x70,0x4C,0x7D,0xB7,0xEA,0x51,0x7A,0x7D,0x63,0x30,
+	0x88,0x7E,0x7E,0x92,0x44,0x99,0x3A,0x7E,0x4C,0xCC,0x91,
+	0xC7,0x7F,0xAA,0xAA,0xAA,0x13,0x81,0x00,0x00,0x00,0x00,
+	0x20,0xCC,0xFF,0xA9,0x00,0x85,0x13,0x20,0x7A,0xA6,0x58,
+	0xA2,0x80,0x6C,0x00,0x03,0x8A,0x30,0x03,0x4C,0x3A,0xA4,
+	0x4C,0x74,0xA4,0x20,0x53,0xE4,0x20,0xBF,0xE3,0x20,0x22,
+	0xE4,0xA2,0xFB,0x9A,0xD0,0xE4,0xE6,0x7A,0xD0,0x02,0xE6,
+	0x7B,0xAD,0x60,0xEA,0xC9,0x3A,0xB0,0x0A,0xC9,0x20,0xF0,
+	0xEF,0x38,0xE9,0x30,0x38,0xE9,0xD0,0x60,0x80,0x4F,0xC7,
+	0x52,0x58,0xA9,0x4C,0x85,0x54,0x8D,0x10,0x03,0xA9,0x48,
+	0xA0,0xB2,0x8D,0x11,0x03,0x8C,0x12,0x03,0xA9,0x91,0xA0,
+	0xB3,0x85,0x05,0x84,0x06,0xA9,0xAA,0xA0,0xB1,0x85,0x03,
+	0x84,0x04,0xA2,0x1C,0xBD,0xA2,0xE3,0x95,0x73,0xCA,0x10,
+	0xF8,0xA9,0x03,0x85,0x53,0xA9,0x00,0x85,0x68,0x85,0x13,
+	0x85,0x18,0xA2,0x01,0x8E,0xFD,0x01,0x8E,0xFC,0x01,0xA2,
+	0x19,0x86,0x16,0x38,0x20,0x9C,0xFF,0x86,0x2B,0x84,0x2C,
+	0x38,0x20,0x99,0xFF,0x86,0x37,0x84,0x38,0x86,0x33,0x84,
+	0x34,0xA0,0x00,0x98,0x91,0x2B,0xE6,0x2B,0xD0,0x02,0xE6,
+	0x2C,0x60,0xA5,0x2B,0xA4,0x2C,0x20,0x08,0xA4,0xA9,0x73,
+	0xA0,0xE4,0x20,0x1E,0xAB,0xA5,0x37,0x38,0xE5,0x2B,0xAA,
+	0xA5,0x38,0xE5,0x2C,0x20,0xCD,0xBD,0xA9,0x60,0xA0,0xE4,
+	0x20,0x1E,0xAB,0x4C,0x44,0xA6,0x8B,0xE3,0x83,0xA4,0x7C,
+	0xA5,0x1A,0xA7,0xE4,0xA7,0x86,0xAE,0xA2,0x0B,0xBD,0x47,
+	0xE4,0x9D,0x00,0x03,0xCA,0x10,0xF7,0x60,0x00,0x20,0x42,
+	0x41,0x53,0x49,0x43,0x20,0x42,0x59,0x54,0x45,0x53,0x20,
+	0x46,0x52,0x45,0x45,0x0D,0x00,0x93,0x0D,0x20,0x20,0x20,
+	0x20,0x2A,0x2A,0x2A,0x2A,0x20,0x43,0x4F,0x4D,0x4D,0x4F,
+	0x44,0x4F,0x52,0x45,0x20,0x36,0x34,0x20,0x42,0x41,0x53,
+	0x49,0x43,0x20,0x56,0x32,0x20,0x2A,0x2A,0x2A,0x2A,0x0D,
+	0x0D,0x20,0x36,0x34,0x4B,0x20,0x52,0x41,0x4D,0x20,0x53,
+	0x59,0x53,0x54,0x45,0x4D,0x20,0x20,0x00,0x81,0x48,0x20,
+	0xC9,0xFF,0xAA,0x68,0x90,0x01,0x8A,0x60,0xAA,0xAA,0xAA,
+	0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+	0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
+	0xAA,0xAA,0xAA,0x85,0xA9,0xA9,0x01,0x85,0xAB,0x60,0xAD,
+	0x86,0x02,0x91,0xF3,0x60,0x69,0x02,0xA4,0x91,0xC8,0xD0,
+	0x04,0xC5,0xA1,0xD0,0xF7,0x60,0x19,0x26,0x44,0x19,0x1A,
+	0x11,0xE8,0x0D,0x70,0x0C,0x06,0x06,0xD1,0x02,0x37,0x01,
+	0xAE,0x00,0x69,0x00,0xA2,0x00,0xA0,0xDC,0x60,0xA2,0x28,
+	0xA0,0x19,0x60,0xB0,0x07,0x86,0xD6,0x84,0xD3,0x20,0x6C,
+	0xE5,0xA6,0xD6,0xA4,0xD3,0x60,0x20,0xA0,0xE5,0xA9,0x00,
+	0x8D,0x91,0x02,0x85,0xCF,0xA9,0x48,0x8D,0x8F,0x02,0xA9,
+	0xEB,0x8D,0x90,0x02,0xA9,0x0A,0x8D,0x89,0x02,0x8D,0x8C,
+	0x02,0xA9,0x0E,0x8D,0x86,0x02,0xA9,0x04,0x8D,0x8B,0x02,
+	0xA9,0x0C,0x85,0xCD,0x85,0xCC,0xAD,0x88,0x02,0x09,0x80,
+	0xA8,0xA9,0x00,0xAA,0x94,0xD9,0x18,0x69,0x28,0x90,0x01,
+	0xC8,0xE8,0xE0,0x1A,0xD0,0xF3,0xA9,0xFF,0x95,0xD9,0xA2,
+	0x18,0x20,0xFF,0xE9,0xCA,0x10,0xFA,0xA0,0x00,0x84,0xD3,
+	0x84,0xD6,0xA6,0xD6,0xA5,0xD3,0xB4,0xD9,0x30,0x08,0x18,
+	0x69,0x28,0x85,0xD3,0xCA,0x10,0xF4,0x20,0xF0,0xE9,0xA9,
+	0x27,0xE8,0xB4,0xD9,0x30,0x06,0x18,0x69,0x28,0xE8,0x10,
+	0xF6,0x85,0xD5,0x4C,0x24,0xEA,0xE4,0xC9,0xF0,0x03,0x4C,
+	0xED,0xE6,0x60,0xEA,0x20,0xA0,0xE5,0x4C,0x66,0xE5,0xA9,
+	0x03,0x85,0x9A,0xA9,0x00,0x85,0x99,0xA2,0x2F,0xBD,0xB8,
+	0xEC,0x9D,0xFF,0xCF,0xCA,0xD0,0xF7,0x60,0xAC,0x77,0x02,
+	0xA2,0x00,0xBD,0x78,0x02,0x9D,0x77,0x02,0xE8,0xE4,0xC6,
+	0xD0,0xF5,0xC6,0xC6,0x98,0x58,0x18,0x60,0x20,0x16,0xE7,
+	0xA5,0xC6,0x85,0xCC,0x8D,0x92,0x02,0xF0,0xF7,0x78,0xA5,
+	0xCF,0xF0,0x0C,0xA5,0xCE,0xAE,0x87,0x02,0xA0,0x00,0x84,
+	0xCF,0x20,0x13,0xEA,0x20,0xB4,0xE5,0xC9,0x83,0xD0,0x10,
+	0xA2,0x09,0x78,0x86,0xC6,0xBD,0xE6,0xEC,0x9D,0x76,0x02,
+	0xCA,0xD0,0xF7,0xF0,0xCF,0xC9,0x0D,0xD0,0xC8,0xA4,0xD5,
+	0x84,0xD0,0xB1,0xD1,0xC9,0x20,0xD0,0x03,0x88,0xD0,0xF7,
+	0xC8,0x84,0xC8,0xA0,0x00,0x8C,0x92,0x02,0x84,0xD3,0x84,
+	0xD4,0xA5,0xC9,0x30,0x1B,0xA6,0xD6,0x20,0x91,0xE5,0xE4,
+	0xC9,0xD0,0x12,0xA5,0xCA,0x85,0xD3,0xC5,0xC8,0x90,0x0A,
+	0xB0,0x2B,0x98,0x48,0x8A,0x48,0xA5,0xD0,0xF0,0x93,0xA4,
+	0xD3,0xB1,0xD1,0x85,0xD7,0x29,0x3F,0x06,0xD7,0x24,0xD7,
+	0x10,0x02,0x09,0x80,0x90,0x04,0xA6,0xD4,0xD0,0x04,0x70,
+	0x02,0x09,0x40,0xE6,0xD3,0x20,0x84,0xE6,0xC4,0xC8,0xD0,
+	0x17,0xA9,0x00,0x85,0xD0,0xA9,0x0D,0xA6,0x99,0xE0,0x03,
+	0xF0,0x06,0xA6,0x9A,0xE0,0x03,0xF0,0x03,0x20,0x16,0xE7,
+	0xA9,0x0D,0x85,0xD7,0x68,0xAA,0x68,0xA8,0xA5,0xD7,0xC9,
+	0xDE,0xD0,0x02,0xA9,0xFF,0x18,0x60,0xC9,0x22,0xD0,0x08,
+	0xA5,0xD4,0x49,0x01,0x85,0xD4,0xA9,0x22,0x60,0x09,0x40,
+	0xA6,0xC7,0xF0,0x02,0x09,0x80,0xA6,0xD8,0xF0,0x02,0xC6,
+	0xD8,0xAE,0x86,0x02,0x20,0x13,0xEA,0x20,0xB6,0xE6,0x68,
+	0xA8,0xA5,0xD8,0xF0,0x02,0x46,0xD4,0x68,0xAA,0x68,0x18,
+	0x58,0x60,0x20,0xB3,0xE8,0xE6,0xD3,0xA5,0xD5,0xC5,0xD3,
+	0xB0,0x3F,0xC9,0x4F,0xF0,0x32,0xAD,0x92,0x02,0xF0,0x03,
+	0x4C,0x67,0xE9,0xA6,0xD6,0xE0,0x19,0x90,0x07,0x20,0xEA,
+	0xE8,0xC6,0xD6,0xA6,0xD6,0x16,0xD9,0x56,0xD9,0xE8,0xB5,
+	0xD9,0x09,0x80,0x95,0xD9,0xCA,0xA5,0xD5,0x18,0x69,0x28,
+	0x85,0xD5,0xB5,0xD9,0x30,0x03,0xCA,0xD0,0xF9,0x4C,0xF0,
+	0xE9,0xC6,0xD6,0x20,0x7C,0xE8,0xA9,0x00,0x85,0xD3,0x60,
+	0xA6,0xD6,0xD0,0x06,0x86,0xD3,0x68,0x68,0xD0,0x9D,0xCA,
+	0x86,0xD6,0x20,0x6C,0xE5,0xA4,0xD5,0x84,0xD3,0x60,0x48,
+	0x85,0xD7,0x8A,0x48,0x98,0x48,0xA9,0x00,0x85,0xD0,0xA4,
+	0xD3,0xA5,0xD7,0x10,0x03,0x4C,0xD4,0xE7,0xC9,0x0D,0xD0,
+	0x03,0x4C,0x91,0xE8,0xC9,0x20,0x90,0x10,0xC9,0x60,0x90,
+	0x04,0x29,0xDF,0xD0,0x02,0x29,0x3F,0x20,0x84,0xE6,0x4C,
+	0x93,0xE6,0xA6,0xD8,0xF0,0x03,0x4C,0x97,0xE6,0xC9,0x14,
+	0xD0,0x2E,0x98,0xD0,0x06,0x20,0x01,0xE7,0x4C,0x73,0xE7,
+	0x20,0xA1,0xE8,0x88,0x84,0xD3,0x20,0x24,0xEA,0xC8,0xB1,
+	0xD1,0x88,0x91,0xD1,0xC8,0xB1,0xF3,0x88,0x91,0xF3,0xC8,
+	0xC4,0xD5,0xD0,0xEF,0xA9,0x20,0x91,0xD1,0xAD,0x86,0x02,
+	0x91,0xF3,0x10,0x4D,0xA6,0xD4,0xF0,0x03,0x4C,0x97,0xE6,
+	0xC9,0x12,0xD0,0x02,0x85,0xC7,0xC9,0x13,0xD0,0x03,0x20,
+	0x66,0xE5,0xC9,0x1D,0xD0,0x17,0xC8,0x20,0xB3,0xE8,0x84,
+	0xD3,0x88,0xC4,0xD5,0x90,0x09,0xC6,0xD6,0x20,0x7C,0xE8,
+	0xA0,0x00,0x84,0xD3,0x4C,0xA8,0xE6,0xC9,0x11,0xD0,0x1D,
+	0x18,0x98,0x69,0x28,0xA8,0xE6,0xD6,0xC5,0xD5,0x90,0xEC,
+	0xF0,0xEA,0xC6,0xD6,0xE9,0x28,0x90,0x04,0x85,0xD3,0xD0,
+	0xF8,0x20,0x7C,0xE8,0x4C,0xA8,0xE6,0x20,0xCB,0xE8,0x4C,
+	0x44,0xEC,0x29,0x7F,0xC9,0x7F,0xD0,0x02,0xA9,0x5E,0xC9,
+	0x20,0x90,0x03,0x4C,0x91,0xE6,0xC9,0x0D,0xD0,0x03,0x4C,
+	0x91,0xE8,0xA6,0xD4,0xD0,0x3F,0xC9,0x14,0xD0,0x37,0xA4,
+	0xD5,0xB1,0xD1,0xC9,0x20,0xD0,0x04,0xC4,0xD3,0xD0,0x07,
+	0xC0,0x4F,0xF0,0x24,0x20,0x65,0xE9,0xA4,0xD5,0x20,0x24,
+	0xEA,0x88,0xB1,0xD1,0xC8,0x91,0xD1,0x88,0xB1,0xF3,0xC8,
+	0x91,0xF3,0x88,0xC4,0xD3,0xD0,0xEF,0xA9,0x20,0x91,0xD1,
+	0xAD,0x86,0x02,0x91,0xF3,0xE6,0xD8,0x4C,0xA8,0xE6,0xA6,
+	0xD8,0xF0,0x05,0x09,0x40,0x4C,0x97,0xE6,0xC9,0x11,0xD0,
+	0x16,0xA6,0xD6,0xF0,0x37,0xC6,0xD6,0xA5,0xD3,0x38,0xE9,
+	0x28,0x90,0x04,0x85,0xD3,0x10,0x2A,0x20,0x6C,0xE5,0xD0,
+	0x25,0xC9,0x12,0xD0,0x04,0xA9,0x00,0x85,0xC7,0xC9,0x1D,
+	0xD0,0x12,0x98,0xF0,0x09,0x20,0xA1,0xE8,0x88,0x84,0xD3,
+	0x4C,0xA8,0xE6,0x20,0x01,0xE7,0x4C,0xA8,0xE6,0xC9,0x13,
+	0xD0,0x06,0x20,0x44,0xE5,0x4C,0xA8,0xE6,0x09,0x80,0x20,
+	0xCB,0xE8,0x4C,0x4F,0xEC,0x46,0xC9,0xA6,0xD6,0xE8,0xE0,
+	0x19,0xD0,0x03,0x20,0xEA,0xE8,0xB5,0xD9,0x10,0xF4,0x86,
+	0xD6,0x4C,0x6C,0xE5,0xA2,0x00,0x86,0xD8,0x86,0xC7,0x86,
+	0xD4,0x86,0xD3,0x20,0x7C,0xE8,0x4C,0xA8,0xE6,0xA2,0x02,
+	0xA9,0x00,0xC5,0xD3,0xF0,0x07,0x18,0x69,0x28,0xCA,0xD0,
+	0xF6,0x60,0xC6,0xD6,0x60,0xA2,0x02,0xA9,0x27,0xC5,0xD3,
+	0xF0,0x07,0x18,0x69,0x28,0xCA,0xD0,0xF6,0x60,0xA6,0xD6,
+	0xE0,0x19,0xF0,0x02,0xE6,0xD6,0x60,0xA2,0x0F,0xDD,0xDA,
+	0xE8,0xF0,0x04,0xCA,0x10,0xF8,0x60,0x8E,0x86,0x02,0x60,
+	0x90,0x05,0x1C,0x9F,0x9C,0x1E,0x1F,0x9E,0x81,0x95,0x96,
+	0x97,0x98,0x99,0x9A,0x9B,0xA5,0xAC,0x48,0xA5,0xAD,0x48,
+	0xA5,0xAE,0x48,0xA5,0xAF,0x48,0xA2,0xFF,0xC6,0xD6,0xC6,
+	0xC9,0xCE,0xA5,0x02,0xE8,0x20,0xF0,0xE9,0xE0,0x18,0xB0,
+	0x0C,0xBD,0xF1,0xEC,0x85,0xAC,0xB5,0xDA,0x20,0xC8,0xE9,
+	0x30,0xEC,0x20,0xFF,0xE9,0xA2,0x00,0xB5,0xD9,0x29,0x7F,
+	0xB4,0xDA,0x10,0x02,0x09,0x80,0x95,0xD9,0xE8,0xE0,0x18,
+	0xD0,0xEF,0xA5,0xF1,0x09,0x80,0x85,0xF1,0xA5,0xD9,0x10,
+	0xC3,0xE6,0xD6,0xEE,0xA5,0x02,0xA9,0x7F,0x8D,0x00,0xDC,
+	0xAD,0x01,0xDC,0xC9,0xFB,0x08,0xA9,0x7F,0x8D,0x00,0xDC,
+	0x28,0xD0,0x0B,0xA0,0x00,0xEA,0xCA,0xD0,0xFC,0x88,0xD0,
+	0xF9,0x84,0xC6,0xA6,0xD6,0x68,0x85,0xAF,0x68,0x85,0xAE,
+	0x68,0x85,0xAD,0x68,0x85,0xAC,0x60,0xA6,0xD6,0xE8,0xB5,
+	0xD9,0x10,0xFB,0x8E,0xA5,0x02,0xE0,0x18,0xF0,0x0E,0x90,
+	0x0C,0x20,0xEA,0xE8,0xAE,0xA5,0x02,0xCA,0xC6,0xD6,0x4C,
+	0xDA,0xE6,0xA5,0xAC,0x48,0xA5,0xAD,0x48,0xA5,0xAE,0x48,
+	0xA5,0xAF,0x48,0xA2,0x19,0xCA,0x20,0xF0,0xE9,0xEC,0xA5,
+	0x02,0x90,0x0E,0xF0,0x0C,0xBD,0xEF,0xEC,0x85,0xAC,0xB5,
+	0xD8,0x20,0xC8,0xE9,0x30,0xE9,0x20,0xFF,0xE9,0xA2,0x17,
+	0xEC,0xA5,0x02,0x90,0x0F,0xB5,0xDA,0x29,0x7F,0xB4,0xD9,
+	0x10,0x02,0x09,0x80,0x95,0xDA,0xCA,0xD0,0xEC,0xAE,0xA5,
+	0x02,0x20,0xDA,0xE6,0x4C,0x58,0xE9,0x29,0x03,0x0D,0x88,
+	0x02,0x85,0xAD,0x20,0xE0,0xE9,0xA0,0x27,0xB1,0xAC,0x91,
+	0xD1,0xB1,0xAE,0x91,0xF3,0x88,0x10,0xF5,0x60,0x20,0x24,
+	0xEA,0xA5,0xAC,0x85,0xAE,0xA5,0xAD,0x29,0x03,0x09,0xD8,
+	0x85,0xAF,0x60,0xBD,0xF0,0xEC,0x85,0xD1,0xB5,0xD9,0x29,
+	0x03,0x0D,0x88,0x02,0x85,0xD2,0x60,0xA0,0x27,0x20,0xF0,
+	0xE9,0x20,0x24,0xEA,0x20,0xDA,0xE4,0xA9,0x20,0x91,0xD1,
+	0x88,0x10,0xF6,0x60,0xEA,0xA8,0xA9,0x02,0x85,0xCD,0x20,
+	0x24,0xEA,0x98,0xA4,0xD3,0x91,0xD1,0x8A,0x91,0xF3,0x60,
+	0xA5,0xD1,0x85,0xF3,0xA5,0xD2,0x29,0x03,0x09,0xD8,0x85,
+	0xF4,0x60,0x20,0xEA,0xFF,0xA5,0xCC,0xD0,0x29,0xC6,0xCD,
+	0xD0,0x25,0xA9,0x14,0x85,0xCD,0xA4,0xD3,0x46,0xCF,0xAE,
+	0x87,0x02,0xB1,0xD1,0xB0,0x11,0xE6,0xCF,0x85,0xCE,0x20,
+	0x24,0xEA,0xB1,0xF3,0x8D,0x87,0x02,0xAE,0x86,0x02,0xA5,
+	0xCE,0x49,0x80,0x20,0x1C,0xEA,0xA5,0x01,0x29,0x10,0xF0,
+	0x0A,0xA0,0x00,0x84,0xC0,0xA5,0x01,0x09,0x20,0xD0,0x08,
+	0xA5,0xC0,0xD0,0x06,0xA5,0x01,0x29,0x1F,0x85,0x01,0x20,
+	0x87,0xEA,0xAD,0x0D,0xDC,0x68,0xA8,0x68,0xAA,0x68,0x40,
+	0xA9,0x00,0x8D,0x8D,0x02,0xA0,0x40,0x84,0xCB,0x8D,0x00,
+	0xDC,0xAE,0x01,0xDC,0xE0,0xFF,0xF0,0x61,0xA8,0xA9,0x81,
+	0x85,0xF5,0xA9,0xEB,0x85,0xF6,0xA9,0xFE,0x8D,0x00,0xDC,
+	0xA2,0x08,0x48,0xAD,0x01,0xDC,0xCD,0x01,0xDC,0xD0,0xF8,
+	0x4A,0xB0,0x16,0x48,0xB1,0xF5,0xC9,0x05,0xB0,0x0C,0xC9,
+	0x03,0xF0,0x08,0x0D,0x8D,0x02,0x8D,0x8D,0x02,0x10,0x02,
+	0x84,0xCB,0x68,0xC8,0xC0,0x41,0xB0,0x0B,0xCA,0xD0,0xDF,
+	0x38,0x68,0x2A,0x8D,0x00,0xDC,0xD0,0xCC,0x68,0x6C,0x8F,
+	0x02,0xA4,0xCB,0xB1,0xF5,0xAA,0xC4,0xC5,0xF0,0x07,0xA0,
+	0x10,0x8C,0x8C,0x02,0xD0,0x36,0x29,0x7F,0x2C,0x8A,0x02,
+	0x30,0x16,0x70,0x49,0xC9,0x7F,0xF0,0x29,0xC9,0x14,0xF0,
+	0x0C,0xC9,0x20,0xF0,0x08,0xC9,0x1D,0xF0,0x04,0xC9,0x11,
+	0xD0,0x35,0xAC,0x8C,0x02,0xF0,0x05,0xCE,0x8C,0x02,0xD0,
+	0x2B,0xCE,0x8B,0x02,0xD0,0x26,0xA0,0x04,0x8C,0x8B,0x02,
+	0xA4,0xC6,0x88,0x10,0x1C,0xA4,0xCB,0x84,0xC5,0xAC,0x8D,
+	0x02,0x8C,0x8E,0x02,0xE0,0xFF,0xF0,0x0E,0x8A,0xA6,0xC6,
+	0xEC,0x89,0x02,0xB0,0x06,0x9D,0x77,0x02,0xE8,0x86,0xC6,
+	0xA9,0x7F,0x8D,0x00,0xDC,0x60,0xAD,0x8D,0x02,0xC9,0x03,
+	0xD0,0x15,0xCD,0x8E,0x02,0xF0,0xEE,0xAD,0x91,0x02,0x30,
+	0x1D,0xAD,0x18,0xD0,0x49,0x02,0x8D,0x18,0xD0,0x4C,0x76,
+	0xEB,0x0A,0xC9,0x08,0x90,0x02,0xA9,0x06,0xAA,0xBD,0x79,
+	0xEB,0x85,0xF5,0xBD,0x7A,0xEB,0x85,0xF6,0x4C,0xE0,0xEA,
+	0x81,0xEB,0xC2,0xEB,0x03,0xEC,0x78,0xEC,0x14,0x0D,0x1D,
+	0x88,0x85,0x86,0x87,0x11,0x33,0x57,0x41,0x34,0x5A,0x53,
+	0x45,0x01,0x35,0x52,0x44,0x36,0x43,0x46,0x54,0x58,0x37,
+	0x59,0x47,0x38,0x42,0x48,0x55,0x56,0x39,0x49,0x4A,0x30,
+	0x4D,0x4B,0x4F,0x4E,0x2B,0x50,0x4C,0x2D,0x2E,0x3A,0x40,
+	0x2C,0x5C,0x2A,0x3B,0x13,0x01,0x3D,0x5E,0x2F,0x31,0x5F,
+	0x04,0x32,0x20,0x02,0x51,0x03,0xFF,0x94,0x8D,0x9D,0x8C,
+	0x89,0x8A,0x8B,0x91,0x23,0xD7,0xC1,0x24,0xDA,0xD3,0xC5,
+	0x01,0x25,0xD2,0xC4,0x26,0xC3,0xC6,0xD4,0xD8,0x27,0xD9,
+	0xC7,0x28,0xC2,0xC8,0xD5,0xD6,0x29,0xC9,0xCA,0x30,0xCD,
+	0xCB,0xCF,0xCE,0xDB,0xD0,0xCC,0xDD,0x3E,0x5B,0xBA,0x3C,
+	0xA9,0xC0,0x5D,0x93,0x01,0x3D,0xDE,0x3F,0x21,0x5F,0x04,
+	0x22,0xA0,0x02,0xD1,0x83,0xFF,0x94,0x8D,0x9D,0x8C,0x89,
+	0x8A,0x8B,0x91,0x96,0xB3,0xB0,0x97,0xAD,0xAE,0xB1,0x01,
+	0x98,0xB2,0xAC,0x99,0xBC,0xBB,0xA3,0xBD,0x9A,0xB7,0xA5,
+	0x9B,0xBF,0xB4,0xB8,0xBE,0x29,0xA2,0xB5,0x30,0xA7,0xA1,
+	0xB9,0xAA,0xA6,0xAF,0xB6,0xDC,0x3E,0x5B,0xA4,0x3C,0xA8,
+	0xDF,0x5D,0x93,0x01,0x3D,0xDE,0x3F,0x81,0x5F,0x04,0x95,
+	0xA0,0x02,0xAB,0x83,0xFF,0xC9,0x0E,0xD0,0x07,0xAD,0x18,
+	0xD0,0x09,0x02,0xD0,0x09,0xC9,0x8E,0xD0,0x0B,0xAD,0x18,
+	0xD0,0x29,0xFD,0x8D,0x18,0xD0,0x4C,0xA8,0xE6,0xC9,0x08,
+	0xD0,0x07,0xA9,0x80,0x0D,0x91,0x02,0x30,0x09,0xC9,0x09,
+	0xD0,0xEE,0xA9,0x7F,0x2D,0x91,0x02,0x8D,0x91,0x02,0x4C,
+	0xA8,0xE6,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x1C,
+	0x17,0x01,0x9F,0x1A,0x13,0x05,0xFF,0x9C,0x12,0x04,0x1E,
+	0x03,0x06,0x14,0x18,0x1F,0x19,0x07,0x9E,0x02,0x08,0x15,
+	0x16,0x12,0x09,0x0A,0x92,0x0D,0x0B,0x0F,0x0E,0xFF,0x10,
+	0x0C,0xFF,0xFF,0x1B,0x00,0xFF,0x1C,0xFF,0x1D,0xFF,0xFF,
+	0x1F,0x1E,0xFF,0x90,0x06,0xFF,0x05,0xFF,0xFF,0x11,0xFF,
+	0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9B,0x37,0x00,0x00,
+	0x00,0x08,0x00,0x14,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0E,0x06,0x01,0x02,0x03,0x04,0x00,0x01,0x02,0x03,0x04,
+	0x05,0x06,0x07,0x4C,0x4F,0x41,0x44,0x0D,0x52,0x55,0x4E,
+	0x0D,0x00,0x28,0x50,0x78,0xA0,0xC8,0xF0,0x18,0x40,0x68,
+	0x90,0xB8,0xE0,0x08,0x30,0x58,0x80,0xA8,0xD0,0xF8,0x20,
+	0x48,0x70,0x98,0xC0,0x09,0x40,0x2C,0x09,0x20,0x20,0xA4,
+	0xF0,0x48,0x24,0x94,0x10,0x0A,0x38,0x66,0xA3,0x20,0x40,
+	0xED,0x46,0x94,0x46,0xA3,0x68,0x85,0x95,0x78,0x20,0x97,
+	0xEE,0xC9,0x3F,0xD0,0x03,0x20,0x85,0xEE,0xAD,0x00,0xDD,
+	0x09,0x08,0x8D,0x00,0xDD,0x78,0x20,0x8E,0xEE,0x20,0x97,
+	0xEE,0x20,0xB3,0xEE,0x78,0x20,0x97,0xEE,0x20,0xA9,0xEE,
+	0xB0,0x64,0x20,0x85,0xEE,0x24,0xA3,0x10,0x0A,0x20,0xA9,
+	0xEE,0x90,0xFB,0x20,0xA9,0xEE,0xB0,0xFB,0x20,0xA9,0xEE,
+	0x90,0xFB,0x20,0x8E,0xEE,0xA9,0x08,0x85,0xA5,0xAD,0x00,
+	0xDD,0xCD,0x00,0xDD,0xD0,0xF8,0x0A,0x90,0x3F,0x66,0x95,
+	0xB0,0x05,0x20,0xA0,0xEE,0xD0,0x03,0x20,0x97,0xEE,0x20,
+	0x85,0xEE,0xEA,0xEA,0xEA,0xEA,0xAD,0x00,0xDD,0x29,0xDF,
+	0x09,0x10,0x8D,0x00,0xDD,0xC6,0xA5,0xD0,0xD4,0xA9,0x04,
+	0x8D,0x07,0xDC,0xA9,0x19,0x8D,0x0F,0xDC,0xAD,0x0D,0xDC,
+	0xAD,0x0D,0xDC,0x29,0x02,0xD0,0x0A,0x20,0xA9,0xEE,0xB0,
+	0xF4,0x58,0x60,0xA9,0x80,0x2C,0xA9,0x03,0x20,0x1C,0xFE,
+	0x58,0x18,0x90,0x4A,0x85,0x95,0x20,0x36,0xED,0xAD,0x00,
+	0xDD,0x29,0xF7,0x8D,0x00,0xDD,0x60,0x85,0x95,0x20,0x36,
+	0xED,0x78,0x20,0xA0,0xEE,0x20,0xBE,0xED,0x20,0x85,0xEE,
+	0x20,0xA9,0xEE,0x30,0xFB,0x58,0x60,0x24,0x94,0x30,0x05,
+	0x38,0x66,0x94,0xD0,0x05,0x48,0x20,0x40,0xED,0x68,0x85,
+	0x95,0x18,0x60,0x78,0x20,0x8E,0xEE,0xAD,0x00,0xDD,0x09,
+	0x08,0x8D,0x00,0xDD,0xA9,0x5F,0x2C,0xA9,0x3F,0x20,0x11,
+	0xED,0x20,0xBE,0xED,0x8A,0xA2,0x0A,0xCA,0xD0,0xFD,0xAA,
+	0x20,0x85,0xEE,0x4C,0x97,0xEE,0x78,0xA9,0x00,0x85,0xA5,
+	0x20,0x85,0xEE,0x20,0xA9,0xEE,0x10,0xFB,0xA9,0x01,0x8D,
+	0x07,0xDC,0xA9,0x19,0x8D,0x0F,0xDC,0x20,0x97,0xEE,0xAD,
+	0x0D,0xDC,0xAD,0x0D,0xDC,0x29,0x02,0xD0,0x07,0x20,0xA9,
+	0xEE,0x30,0xF4,0x10,0x18,0xA5,0xA5,0xF0,0x05,0xA9,0x02,
+	0x4C,0xB2,0xED,0x20,0xA0,0xEE,0x20,0x85,0xEE,0xA9,0x40,
+	0x20,0x1C,0xFE,0xE6,0xA5,0xD0,0xCA,0xA9,0x08,0x85,0xA5,
+	0xAD,0x00,0xDD,0xCD,0x00,0xDD,0xD0,0xF8,0x0A,0x10,0xF5,
+	0x66,0xA4,0xAD,0x00,0xDD,0xCD,0x00,0xDD,0xD0,0xF8,0x0A,
+	0x30,0xF5,0xC6,0xA5,0xD0,0xE4,0x20,0xA0,0xEE,0x24,0x90,
+	0x50,0x03,0x20,0x06,0xEE,0xA5,0xA4,0x58,0x18,0x60,0xAD,
+	0x00,0xDD,0x29,0xEF,0x8D,0x00,0xDD,0x60,0xAD,0x00,0xDD,
+	0x09,0x10,0x8D,0x00,0xDD,0x60,0xAD,0x00,0xDD,0x29,0xDF,
+	0x8D,0x00,0xDD,0x60,0xAD,0x00,0xDD,0x09,0x20,0x8D,0x00,
+	0xDD,0x60,0xAD,0x00,0xDD,0xCD,0x00,0xDD,0xD0,0xF8,0x0A,
+	0x60,0x8A,0xA2,0xB8,0xCA,0xD0,0xFD,0xAA,0x60,0xA5,0xB4,
+	0xF0,0x47,0x30,0x3F,0x46,0xB6,0xA2,0x00,0x90,0x01,0xCA,
+	0x8A,0x45,0xBD,0x85,0xBD,0xC6,0xB4,0xF0,0x06,0x8A,0x29,
+	0x04,0x85,0xB5,0x60,0xA9,0x20,0x2C,0x94,0x02,0xF0,0x14,
+	0x30,0x1C,0x70,0x14,0xA5,0xBD,0xD0,0x01,0xCA,0xC6,0xB4,
+	0xAD,0x93,0x02,0x10,0xE3,0xC6,0xB4,0xD0,0xDF,0xE6,0xB4,
+	0xD0,0xF0,0xA5,0xBD,0xF0,0xED,0xD0,0xEA,0x70,0xE9,0x50,
+	0xE6,0xE6,0xB4,0xA2,0xFF,0xD0,0xCB,0xAD,0x94,0x02,0x4A,
+	0x90,0x07,0x2C,0x01,0xDD,0x10,0x1D,0x50,0x1E,0xA9,0x00,
+	0x85,0xBD,0x85,0xB5,0xAE,0x98,0x02,0x86,0xB4,0xAC,0x9D,
+	0x02,0xCC,0x9E,0x02,0xF0,0x13,0xB1,0xF9,0x85,0xB6,0xEE,
+	0x9D,0x02,0x60,0xA9,0x40,0x2C,0xA9,0x10,0x0D,0x97,0x02,
+	0x8D,0x97,0x02,0xA9,0x01,0x8D,0x0D,0xDD,0x4D,0xA1,0x02,
+	0x09,0x80,0x8D,0xA1,0x02,0x8D,0x0D,0xDD,0x60,0xA2,0x09,
+	0xA9,0x20,0x2C,0x93,0x02,0xF0,0x01,0xCA,0x50,0x02,0xCA,
+	0xCA,0x60,0xA6,0xA9,0xD0,0x33,0xC6,0xA8,0xF0,0x36,0x30,
+	0x0D,0xA5,0xA7,0x45,0xAB,0x85,0xAB,0x46,0xA7,0x66,0xAA,
+	0x60,0xC6,0xA8,0xA5,0xA7,0xF0,0x67,0xAD,0x93,0x02,0x0A,
+	0xA9,0x01,0x65,0xA8,0xD0,0xEF,0xA9,0x90,0x8D,0x0D,0xDD,
+	0x0D,0xA1,0x02,0x8D,0xA1,0x02,0x85,0xA9,0xA9,0x02,0x4C,
+	0x3B,0xEF,0xA5,0xA7,0xD0,0xEA,0x4C,0xD3,0xE4,0xAC,0x9B,
+	0x02,0xC8,0xCC,0x9C,0x02,0xF0,0x2A,0x8C,0x9B,0x02,0x88,
+	0xA5,0xAA,0xAE,0x98,0x02,0xE0,0x09,0xF0,0x04,0x4A,0xE8,
+	0xD0,0xF8,0x91,0xF7,0xA9,0x20,0x2C,0x94,0x02,0xF0,0xB4,
+	0x30,0xB1,0xA5,0xA7,0x45,0xAB,0xF0,0x03,0x70,0xA9,0x2C,
+	0x50,0xA6,0xA9,0x01,0x2C,0xA9,0x04,0x2C,0xA9,0x80,0x2C,
+	0xA9,0x02,0x0D,0x97,0x02,0x8D,0x97,0x02,0x4C,0x7E,0xEF,
+	0xA5,0xAA,0xD0,0xF1,0xF0,0xEC,0x85,0x9A,0xAD,0x94,0x02,
+	0x4A,0x90,0x29,0xA9,0x02,0x2C,0x01,0xDD,0x10,0x1D,0xD0,
+	0x20,0xAD,0xA1,0x02,0x29,0x02,0xD0,0xF9,0x2C,0x01,0xDD,
+	0x70,0xFB,0xAD,0x01,0xDD,0x09,0x02,0x8D,0x01,0xDD,0x2C,
+	0x01,0xDD,0x70,0x07,0x30,0xF9,0xA9,0x40,0x8D,0x97,0x02,
+	0x18,0x60,0x20,0x28,0xF0,0xAC,0x9E,0x02,0xC8,0xCC,0x9D,
+	0x02,0xF0,0xF4,0x8C,0x9E,0x02,0x88,0xA5,0x9E,0x91,0xF9,
+	0xAD,0xA1,0x02,0x4A,0xB0,0x1E,0xA9,0x10,0x8D,0x0E,0xDD,
+	0xAD,0x99,0x02,0x8D,0x04,0xDD,0xAD,0x9A,0x02,0x8D,0x05,
+	0xDD,0xA9,0x81,0x20,0x3B,0xEF,0x20,0x06,0xEF,0xA9,0x11,
+	0x8D,0x0E,0xDD,0x60,0x85,0x99,0xAD,0x94,0x02,0x4A,0x90,
+	0x28,0x29,0x08,0xF0,0x24,0xA9,0x02,0x2C,0x01,0xDD,0x10,
+	0xAD,0xF0,0x22,0xAD,0xA1,0x02,0x4A,0xB0,0xFA,0xAD,0x01,
+	0xDD,0x29,0xFD,0x8D,0x01,0xDD,0xAD,0x01,0xDD,0x29,0x04,
+	0xF0,0xF9,0xA9,0x90,0x18,0x4C,0x3B,0xEF,0xAD,0xA1,0x02,
+	0x29,0x12,0xF0,0xF3,0x18,0x60,0xAD,0x97,0x02,0xAC,0x9C,
+	0x02,0xCC,0x9B,0x02,0xF0,0x0B,0x29,0xF7,0x8D,0x97,0x02,
+	0xB1,0xF7,0xEE,0x9C,0x02,0x60,0x09,0x08,0x8D,0x97,0x02,
+	0xA9,0x00,0x60,0x48,0xAD,0xA1,0x02,0xF0,0x11,0xAD,0xA1,
+	0x02,0x29,0x03,0xD0,0xF9,0xA9,0x10,0x8D,0x0D,0xDD,0xA9,
+	0x00,0x8D,0xA1,0x02,0x68,0x60,0x0D,0x49,0x2F,0x4F,0x20,
+	0x45,0x52,0x52,0x4F,0x52,0x20,0xA3,0x0D,0x53,0x45,0x41,
+	0x52,0x43,0x48,0x49,0x4E,0x47,0xA0,0x46,0x4F,0x52,0xA0,
+	0x0D,0x50,0x52,0x45,0x53,0x53,0x20,0x50,0x4C,0x41,0x59,
+	0x20,0x4F,0x4E,0x20,0x54,0x41,0x50,0xC5,0x50,0x52,0x45,
+	0x53,0x53,0x20,0x52,0x45,0x43,0x4F,0x52,0x44,0x20,0x26,
+	0x20,0x50,0x4C,0x41,0x59,0x20,0x4F,0x4E,0x20,0x54,0x41,
+	0x50,0xC5,0x0D,0x4C,0x4F,0x41,0x44,0x49,0x4E,0xC7,0x0D,
+	0x53,0x41,0x56,0x49,0x4E,0x47,0xA0,0x0D,0x56,0x45,0x52,
+	0x49,0x46,0x59,0x49,0x4E,0xC7,0x0D,0x46,0x4F,0x55,0x4E,
+	0x44,0xA0,0x0D,0x4F,0x4B,0x8D,0x24,0x9D,0x10,0x0D,0xB9,
+	0xBD,0xF0,0x08,0x29,0x7F,0x20,0xD2,0xFF,0xC8,0x28,0x10,
+	0xF3,0x18,0x60,0xA5,0x99,0xD0,0x08,0xA5,0xC6,0xF0,0x0F,
+	0x78,0x4C,0xB4,0xE5,0xC9,0x02,0xD0,0x18,0x84,0x97,0x20,
+	0x86,0xF0,0xA4,0x97,0x18,0x60,0xA5,0x99,0xD0,0x0B,0xA5,
+	0xD3,0x85,0xCA,0xA5,0xD6,0x85,0xC9,0x4C,0x32,0xE6,0xC9,
+	0x03,0xD0,0x09,0x85,0xD0,0xA5,0xD5,0x85,0xC8,0x4C,0x32,
+	0xE6,0xB0,0x38,0xC9,0x02,0xF0,0x3F,0x86,0x97,0x20,0x99,
+	0xF1,0xB0,0x16,0x48,0x20,0x99,0xF1,0xB0,0x0D,0xD0,0x05,
+	0xA9,0x40,0x20,0x1C,0xFE,0xC6,0xA6,0xA6,0x97,0x68,0x60,
+	0xAA,0x68,0x8A,0xA6,0x97,0x60,0x20,0x0D,0xF8,0xD0,0x0B,
+	0x20,0x41,0xF8,0xB0,0x11,0xA9,0x00,0x85,0xA6,0xF0,0xF0,
+	0xB1,0xB2,0x18,0x60,0xA5,0x90,0xF0,0x04,0xA9,0x0D,0x18,
+	0x60,0x4C,0x13,0xEE,0x20,0x4E,0xF1,0xB0,0xF7,0xC9,0x00,
+	0xD0,0xF2,0xAD,0x97,0x02,0x29,0x60,0xD0,0xE9,0xF0,0xEE,
+	0x48,0xA5,0x9A,0xC9,0x03,0xD0,0x04,0x68,0x4C,0x16,0xE7,
+	0x90,0x04,0x68,0x4C,0xDD,0xED,0x4A,0x68,0x85,0x9E,0x8A,
+	0x48,0x98,0x48,0x90,0x23,0x20,0x0D,0xF8,0xD0,0x0E,0x20,
+	0x64,0xF8,0xB0,0x0E,0xA9,0x02,0xA0,0x00,0x91,0xB2,0xC8,
+	0x84,0xA6,0xA5,0x9E,0x91,0xB2,0x18,0x68,0xA8,0x68,0xAA,
+	0xA5,0x9E,0x90,0x02,0xA9,0x00,0x60,0x20,0x17,0xF0,0x4C,
+	0xFC,0xF1,0x20,0x0F,0xF3,0xF0,0x03,0x4C,0x01,0xF7,0x20,
+	0x1F,0xF3,0xA5,0xBA,0xF0,0x16,0xC9,0x03,0xF0,0x12,0xB0,
+	0x14,0xC9,0x02,0xD0,0x03,0x4C,0x4D,0xF0,0xA6,0xB9,0xE0,
+	0x60,0xF0,0x03,0x4C,0x0A,0xF7,0x85,0x99,0x18,0x60,0xAA,
+	0x20,0x09,0xED,0xA5,0xB9,0x10,0x06,0x20,0xCC,0xED,0x4C,
+	0x48,0xF2,0x20,0xC7,0xED,0x8A,0x24,0x90,0x10,0xE6,0x4C,
+	0x07,0xF7,0x20,0x0F,0xF3,0xF0,0x03,0x4C,0x01,0xF7,0x20,
+	0x1F,0xF3,0xA5,0xBA,0xD0,0x03,0x4C,0x0D,0xF7,0xC9,0x03,
+	0xF0,0x0F,0xB0,0x11,0xC9,0x02,0xD0,0x03,0x4C,0xE1,0xEF,
+	0xA6,0xB9,0xE0,0x60,0xF0,0xEA,0x85,0x9A,0x18,0x60,0xAA,
+	0x20,0x0C,0xED,0xA5,0xB9,0x10,0x05,0x20,0xBE,0xED,0xD0,
+	0x03,0x20,0xB9,0xED,0x8A,0x24,0x90,0x10,0xE7,0x4C,0x07,
+	0xF7,0x20,0x14,0xF3,0xF0,0x02,0x18,0x60,0x20,0x1F,0xF3,
+	0x8A,0x48,0xA5,0xBA,0xF0,0x50,0xC9,0x03,0xF0,0x4C,0xB0,
+	0x47,0xC9,0x02,0xD0,0x1D,0x68,0x20,0xF2,0xF2,0x20,0x83,
+	0xF4,0x20,0x27,0xFE,0xA5,0xF8,0xF0,0x01,0xC8,0xA5,0xFA,
+	0xF0,0x01,0xC8,0xA9,0x00,0x85,0xF8,0x85,0xFA,0x4C,0x7D,
+	0xF4,0xA5,0xB9,0x29,0x0F,0xF0,0x23,0x20,0xD0,0xF7,0xA9,
+	0x00,0x38,0x20,0xDD,0xF1,0x20,0x64,0xF8,0x90,0x04,0x68,
+	0xA9,0x00,0x60,0xA5,0xB9,0xC9,0x62,0xD0,0x0B,0xA9,0x05,
+	0x20,0x6A,0xF7,0x4C,0xF1,0xF2,0x20,0x42,0xF6,0x68,0xAA,
+	0xC6,0x98,0xE4,0x98,0xF0,0x14,0xA4,0x98,0xB9,0x59,0x02,
+	0x9D,0x59,0x02,0xB9,0x63,0x02,0x9D,0x63,0x02,0xB9,0x6D,
+	0x02,0x9D,0x6D,0x02,0x18,0x60,0xA9,0x00,0x85,0x90,0x8A,
+	0xA6,0x98,0xCA,0x30,0x15,0xDD,0x59,0x02,0xD0,0xF8,0x60,
+	0xBD,0x59,0x02,0x85,0xB8,0xBD,0x63,0x02,0x85,0xBA,0xBD,
+	0x6D,0x02,0x85,0xB9,0x60,0xA9,0x00,0x85,0x98,0xA2,0x03,
+	0xE4,0x9A,0xB0,0x03,0x20,0xFE,0xED,0xE4,0x99,0xB0,0x03,
+	0x20,0xEF,0xED,0x86,0x9A,0xA9,0x00,0x85,0x99,0x60,0xA6,
+	0xB8,0xD0,0x03,0x4C,0x0A,0xF7,0x20,0x0F,0xF3,0xD0,0x03,
+	0x4C,0xFE,0xF6,0xA6,0x98,0xE0,0x0A,0x90,0x03,0x4C,0xFB,
+	0xF6,0xE6,0x98,0xA5,0xB8,0x9D,0x59,0x02,0xA5,0xB9,0x09,
+	0x60,0x85,0xB9,0x9D,0x6D,0x02,0xA5,0xBA,0x9D,0x63,0x02,
+	0xF0,0x5A,0xC9,0x03,0xF0,0x56,0x90,0x05,0x20,0xD5,0xF3,
+	0x90,0x4F,0xC9,0x02,0xD0,0x03,0x4C,0x09,0xF4,0x20,0xD0,
+	0xF7,0xB0,0x03,0x4C,0x13,0xF7,0xA5,0xB9,0x29,0x0F,0xD0,
+	0x1F,0x20,0x17,0xF8,0xB0,0x36,0x20,0xAF,0xF5,0xA5,0xB7,
+	0xF0,0x0A,0x20,0xEA,0xF7,0x90,0x18,0xF0,0x28,0x4C,0x04,
+	0xF7,0x20,0x2C,0xF7,0xF0,0x20,0x90,0x0C,0xB0,0xF4,0x20,
+	0x38,0xF8,0xB0,0x17,0xA9,0x04,0x20,0x6A,0xF7,0xA9,0xBF,
+	0xA4,0xB9,0xC0,0x60,0xF0,0x07,0xA0,0x00,0xA9,0x02,0x91,
+	0xB2,0x98,0x85,0xA6,0x18,0x60,0xA5,0xB9,0x30,0xFA,0xA4,
+	0xB7,0xF0,0xF6,0xA9,0x00,0x85,0x90,0xA5,0xBA,0x20,0x0C,
+	0xED,0xA5,0xB9,0x09,0xF0,0x20,0xB9,0xED,0xA5,0x90,0x10,
+	0x05,0x68,0x68,0x4C,0x07,0xF7,0xA5,0xB7,0xF0,0x0C,0xA0,
+	0x00,0xB1,0xBB,0x20,0xDD,0xED,0xC8,0xC4,0xB7,0xD0,0xF6,
+	0x4C,0x54,0xF6,0x20,0x83,0xF4,0x8C,0x97,0x02,0xC4,0xB7,
+	0xF0,0x0A,0xB1,0xBB,0x99,0x93,0x02,0xC8,0xC0,0x04,0xD0,
+	0xF2,0x20,0x4A,0xEF,0x8E,0x98,0x02,0xAD,0x93,0x02,0x29,
+	0x0F,0xF0,0x1C,0x0A,0xAA,0xAD,0xA6,0x02,0xD0,0x09,0xBC,
+	0xC1,0xFE,0xBD,0xC0,0xFE,0x4C,0x40,0xF4,0xBC,0xEB,0xE4,
+	0xBD,0xEA,0xE4,0x8C,0x96,0x02,0x8D,0x95,0x02,0xAD,0x95,
+	0x02,0x0A,0x20,0x2E,0xFF,0xAD,0x94,0x02,0x4A,0x90,0x09,
+	0xAD,0x01,0xDD,0x0A,0xB0,0x03,0x20,0x0D,0xF0,0xAD,0x9B,
+	0x02,0x8D,0x9C,0x02,0xAD,0x9E,0x02,0x8D,0x9D,0x02,0x20,
+	0x27,0xFE,0xA5,0xF8,0xD0,0x05,0x88,0x84,0xF8,0x86,0xF7,
+	0xA5,0xFA,0xD0,0x05,0x88,0x84,0xFA,0x86,0xF9,0x38,0xA9,
+	0xF0,0x4C,0x2D,0xFE,0xA9,0x7F,0x8D,0x0D,0xDD,0xA9,0x06,
+	0x8D,0x03,0xDD,0x8D,0x01,0xDD,0xA9,0x04,0x0D,0x00,0xDD,
+	0x8D,0x00,0xDD,0xA0,0x00,0x8C,0xA1,0x02,0x60,0x86,0xC3,
+	0x84,0xC4,0x6C,0x30,0x03,0x85,0x93,0xA9,0x00,0x85,0x90,
+	0xA5,0xBA,0xD0,0x03,0x4C,0x13,0xF7,0xC9,0x03,0xF0,0xF9,
+	0x90,0x7B,0xA4,0xB7,0xD0,0x03,0x4C,0x10,0xF7,0xA6,0xB9,
+	0x20,0xAF,0xF5,0xA9,0x60,0x85,0xB9,0x20,0xD5,0xF3,0xA5,
+	0xBA,0x20,0x09,0xED,0xA5,0xB9,0x20,0xC7,0xED,0x20,0x13,
+	0xEE,0x85,0xAE,0xA5,0x90,0x4A,0x4A,0xB0,0x50,0x20,0x13,
+	0xEE,0x85,0xAF,0x8A,0xD0,0x08,0xA5,0xC3,0x85,0xAE,0xA5,
+	0xC4,0x85,0xAF,0x20,0xD2,0xF5,0xA9,0xFD,0x25,0x90,0x85,
+	0x90,0x20,0xE1,0xFF,0xD0,0x03,0x4C,0x33,0xF6,0x20,0x13,
+	0xEE,0xAA,0xA5,0x90,0x4A,0x4A,0xB0,0xE8,0x8A,0xA4,0x93,
+	0xF0,0x0C,0xA0,0x00,0xD1,0xAE,0xF0,0x08,0xA9,0x10,0x20,
+	0x1C,0xFE,0x2C,0x91,0xAE,0xE6,0xAE,0xD0,0x02,0xE6,0xAF,
+	0x24,0x90,0x50,0xCB,0x20,0xEF,0xED,0x20,0x42,0xF6,0x90,
+	0x79,0x4C,0x04,0xF7,0x4A,0xB0,0x03,0x4C,0x13,0xF7,0x20,
+	0xD0,0xF7,0xB0,0x03,0x4C,0x13,0xF7,0x20,0x17,0xF8,0xB0,
+	0x68,0x20,0xAF,0xF5,0xA5,0xB7,0xF0,0x09,0x20,0xEA,0xF7,
+	0x90,0x0B,0xF0,0x5A,0xB0,0xDA,0x20,0x2C,0xF7,0xF0,0x53,
+	0xB0,0xD3,0xA5,0x90,0x29,0x10,0x38,0xD0,0x4A,0xE0,0x01,
+	0xF0,0x11,0xE0,0x03,0xD0,0xDD,0xA0,0x01,0xB1,0xB2,0x85,
+	0xC3,0xC8,0xB1,0xB2,0x85,0xC4,0xB0,0x04,0xA5,0xB9,0xD0,
+	0xEF,0xA0,0x03,0xB1,0xB2,0xA0,0x01,0xF1,0xB2,0xAA,0xA0,
+	0x04,0xB1,0xB2,0xA0,0x02,0xF1,0xB2,0xA8,0x18,0x8A,0x65,
+	0xC3,0x85,0xAE,0x98,0x65,0xC4,0x85,0xAF,0xA5,0xC3,0x85,
+	0xC1,0xA5,0xC4,0x85,0xC2,0x20,0xD2,0xF5,0x20,0x4A,0xF8,
+	0x24,0x18,0xA6,0xAE,0xA4,0xAF,0x60,0xA5,0x9D,0x10,0x1E,
+	0xA0,0x0C,0x20,0x2F,0xF1,0xA5,0xB7,0xF0,0x15,0xA0,0x17,
+	0x20,0x2F,0xF1,0xA4,0xB7,0xF0,0x0C,0xA0,0x00,0xB1,0xBB,
+	0x20,0xD2,0xFF,0xC8,0xC4,0xB7,0xD0,0xF6,0x60,0xA0,0x49,
+	0xA5,0x93,0xF0,0x02,0xA0,0x59,0x4C,0x2B,0xF1,0x86,0xAE,
+	0x84,0xAF,0xAA,0xB5,0x00,0x85,0xC1,0xB5,0x01,0x85,0xC2,
+	0x6C,0x32,0x03,0xA5,0xBA,0xD0,0x03,0x4C,0x13,0xF7,0xC9,
+	0x03,0xF0,0xF9,0x90,0x5F,0xA9,0x61,0x85,0xB9,0xA4,0xB7,
+	0xD0,0x03,0x4C,0x10,0xF7,0x20,0xD5,0xF3,0x20,0x8F,0xF6,
+	0xA5,0xBA,0x20,0x0C,0xED,0xA5,0xB9,0x20,0xB9,0xED,0xA0,
+	0x00,0x20,0x8E,0xFB,0xA5,0xAC,0x20,0xDD,0xED,0xA5,0xAD,
+	0x20,0xDD,0xED,0x20,0xD1,0xFC,0xB0,0x16,0xB1,0xAC,0x20,
+	0xDD,0xED,0x20,0xE1,0xFF,0xD0,0x07,0x20,0x42,0xF6,0xA9,
+	0x00,0x38,0x60,0x20,0xDB,0xFC,0xD0,0xE5,0x20,0xFE,0xED,
+	0x24,0xB9,0x30,0x11,0xA5,0xBA,0x20,0x0C,0xED,0xA5,0xB9,
+	0x29,0xEF,0x09,0xE0,0x20,0xB9,0xED,0x20,0xFE,0xED,0x18,
+	0x60,0x4A,0xB0,0x03,0x4C,0x13,0xF7,0x20,0xD0,0xF7,0x90,
+	0x8D,0x20,0x38,0xF8,0xB0,0x25,0x20,0x8F,0xF6,0xA2,0x03,
+	0xA5,0xB9,0x29,0x01,0xD0,0x02,0xA2,0x01,0x8A,0x20,0x6A,
+	0xF7,0xB0,0x12,0x20,0x67,0xF8,0xB0,0x0D,0xA5,0xB9,0x29,
+	0x02,0xF0,0x06,0xA9,0x05,0x20,0x6A,0xF7,0x24,0x18,0x60,
+	0xA5,0x9D,0x10,0xFB,0xA0,0x51,0x20,0x2F,0xF1,0x4C,0xC1,
+	0xF5,0xA2,0x00,0xE6,0xA2,0xD0,0x06,0xE6,0xA1,0xD0,0x02,
+	0xE6,0xA0,0x38,0xA5,0xA2,0xE9,0x01,0xA5,0xA1,0xE9,0x1A,
+	0xA5,0xA0,0xE9,0x4F,0x90,0x06,0x86,0xA0,0x86,0xA1,0x86,
+	0xA2,0xAD,0x01,0xDC,0xCD,0x01,0xDC,0xD0,0xF8,0xAA,0x30,
+	0x13,0xA2,0xBD,0x8E,0x00,0xDC,0xAE,0x01,0xDC,0xEC,0x01,
+	0xDC,0xD0,0xF8,0x8D,0x00,0xDC,0xE8,0xD0,0x02,0x85,0x91,
+	0x60,0x78,0xA5,0xA2,0xA6,0xA1,0xA4,0xA0,0x78,0x85,0xA2,
+	0x86,0xA1,0x84,0xA0,0x58,0x60,0xA5,0x91,0xC9,0x7F,0xD0,
+	0x07,0x08,0x20,0xCC,0xFF,0x85,0xC6,0x28,0x60,0xA9,0x01,
+	0x2C,0xA9,0x02,0x2C,0xA9,0x03,0x2C,0xA9,0x04,0x2C,0xA9,
+	0x05,0x2C,0xA9,0x06,0x2C,0xA9,0x07,0x2C,0xA9,0x08,0x2C,
+	0xA9,0x09,0x48,0x20,0xCC,0xFF,0xA0,0x00,0x24,0x9D,0x50,
+	0x0A,0x20,0x2F,0xF1,0x68,0x48,0x09,0x30,0x20,0xD2,0xFF,
+	0x68,0x38,0x60,0xA5,0x93,0x48,0x20,0x41,0xF8,0x68,0x85,
+	0x93,0xB0,0x32,0xA0,0x00,0xB1,0xB2,0xC9,0x05,0xF0,0x2A,
+	0xC9,0x01,0xF0,0x08,0xC9,0x03,0xF0,0x04,0xC9,0x04,0xD0,
+	0xE1,0xAA,0x24,0x9D,0x10,0x17,0xA0,0x63,0x20,0x2F,0xF1,
+	0xA0,0x05,0xB1,0xB2,0x20,0xD2,0xFF,0xC8,0xC0,0x15,0xD0,
+	0xF6,0xA5,0xA1,0x20,0xE0,0xE4,0xEA,0x18,0x88,0x60,0x85,
+	0x9E,0x20,0xD0,0xF7,0x90,0x5E,0xA5,0xC2,0x48,0xA5,0xC1,
+	0x48,0xA5,0xAF,0x48,0xA5,0xAE,0x48,0xA0,0xBF,0xA9,0x20,
+	0x91,0xB2,0x88,0xD0,0xFB,0xA5,0x9E,0x91,0xB2,0xC8,0xA5,
+	0xC1,0x91,0xB2,0xC8,0xA5,0xC2,0x91,0xB2,0xC8,0xA5,0xAE,
+	0x91,0xB2,0xC8,0xA5,0xAF,0x91,0xB2,0xC8,0x84,0x9F,0xA0,
+	0x00,0x84,0x9E,0xA4,0x9E,0xC4,0xB7,0xF0,0x0C,0xB1,0xBB,
+	0xA4,0x9F,0x91,0xB2,0xE6,0x9E,0xE6,0x9F,0xD0,0xEE,0x20,
+	0xD7,0xF7,0xA9,0x69,0x85,0xAB,0x20,0x6B,0xF8,0xA8,0x68,
+	0x85,0xAE,0x68,0x85,0xAF,0x68,0x85,0xC1,0x68,0x85,0xC2,
+	0x98,0x60,0xA6,0xB2,0xA4,0xB3,0xC0,0x02,0x60,0x20,0xD0,
+	0xF7,0x8A,0x85,0xC1,0x18,0x69,0xC0,0x85,0xAE,0x98,0x85,
+	0xC2,0x69,0x00,0x85,0xAF,0x60,0x20,0x2C,0xF7,0xB0,0x1D,
+	0xA0,0x05,0x84,0x9F,0xA0,0x00,0x84,0x9E,0xC4,0xB7,0xF0,
+	0x10,0xB1,0xBB,0xA4,0x9F,0xD1,0xB2,0xD0,0xE7,0xE6,0x9E,
+	0xE6,0x9F,0xA4,0x9E,0xD0,0xEC,0x18,0x60,0x20,0xD0,0xF7,
+	0xE6,0xA6,0xA4,0xA6,0xC0,0xC0,0x60,0x20,0x2E,0xF8,0xF0,
+	0x1A,0xA0,0x1B,0x20,0x2F,0xF1,0x20,0xD0,0xF8,0x20,0x2E,
+	0xF8,0xD0,0xF8,0xA0,0x6A,0x4C,0x2F,0xF1,0xA9,0x10,0x24,
+	0x01,0xD0,0x02,0x24,0x01,0x18,0x60,0x20,0x2E,0xF8,0xF0,
+	0xF9,0xA0,0x2E,0xD0,0xDD,0xA9,0x00,0x85,0x90,0x85,0x93,
+	0x20,0xD7,0xF7,0x20,0x17,0xF8,0xB0,0x1F,0x78,0xA9,0x00,
+	0x85,0xAA,0x85,0xB4,0x85,0xB0,0x85,0x9E,0x85,0x9F,0x85,
+	0x9C,0xA9,0x90,0xA2,0x0E,0xD0,0x11,0x20,0xD7,0xF7,0xA9,
+	0x14,0x85,0xAB,0x20,0x38,0xF8,0xB0,0x6C,0x78,0xA9,0x82,
+	0xA2,0x08,0xA0,0x7F,0x8C,0x0D,0xDC,0x8D,0x0D,0xDC,0xAD,
+	0x0E,0xDC,0x09,0x19,0x8D,0x0F,0xDC,0x29,0x91,0x8D,0xA2,
+	0x02,0x20,0xA4,0xF0,0xAD,0x11,0xD0,0x29,0xEF,0x8D,0x11,
+	0xD0,0xAD,0x14,0x03,0x8D,0x9F,0x02,0xAD,0x15,0x03,0x8D,
+	0xA0,0x02,0x20,0xBD,0xFC,0xA9,0x02,0x85,0xBE,0x20,0x97,
+	0xFB,0xA5,0x01,0x29,0x1F,0x85,0x01,0x85,0xC0,0xA2,0xFF,
+	0xA0,0xFF,0x88,0xD0,0xFD,0xCA,0xD0,0xF8,0x58,0xAD,0xA0,
+	0x02,0xCD,0x15,0x03,0x18,0xF0,0x15,0x20,0xD0,0xF8,0x20,
+	0xBC,0xF6,0x4C,0xBE,0xF8,0x20,0xE1,0xFF,0x18,0xD0,0x0B,
+	0x20,0x93,0xFC,0x38,0x68,0x68,0xA9,0x00,0x8D,0xA0,0x02,
+	0x60,0x86,0xB1,0xA5,0xB0,0x0A,0x0A,0x18,0x65,0xB0,0x18,
+	0x65,0xB1,0x85,0xB1,0xA9,0x00,0x24,0xB0,0x30,0x01,0x2A,
+	0x06,0xB1,0x2A,0x06,0xB1,0x2A,0xAA,0xAD,0x06,0xDC,0xC9,
+	0x16,0x90,0xF9,0x65,0xB1,0x8D,0x04,0xDC,0x8A,0x6D,0x07,
+	0xDC,0x8D,0x05,0xDC,0xAD,0xA2,0x02,0x8D,0x0E,0xDC,0x8D,
+	0xA4,0x02,0xAD,0x0D,0xDC,0x29,0x10,0xF0,0x09,0xA9,0xF9,
+	0x48,0xA9,0x2A,0x48,0x4C,0x43,0xFF,0x58,0x60,0xAE,0x07,
+	0xDC,0xA0,0xFF,0x98,0xED,0x06,0xDC,0xEC,0x07,0xDC,0xD0,
+	0xF2,0x86,0xB1,0xAA,0x8C,0x06,0xDC,0x8C,0x07,0xDC,0xA9,
+	0x19,0x8D,0x0F,0xDC,0xAD,0x0D,0xDC,0x8D,0xA3,0x02,0x98,
+	0xE5,0xB1,0x86,0xB1,0x4A,0x66,0xB1,0x4A,0x66,0xB1,0xA5,
+	0xB0,0x18,0x69,0x3C,0xC5,0xB1,0xB0,0x4A,0xA6,0x9C,0xF0,
+	0x03,0x4C,0x60,0xFA,0xA6,0xA3,0x30,0x1B,0xA2,0x00,0x69,
+	0x30,0x65,0xB0,0xC5,0xB1,0xB0,0x1C,0xE8,0x69,0x26,0x65,
+	0xB0,0xC5,0xB1,0xB0,0x17,0x69,0x2C,0x65,0xB0,0xC5,0xB1,
+	0x90,0x03,0x4C,0x10,0xFA,0xA5,0xB4,0xF0,0x1D,0x85,0xA8,
+	0xD0,0x19,0xE6,0xA9,0xB0,0x02,0xC6,0xA9,0x38,0xE9,0x13,
+	0xE5,0xB1,0x65,0x92,0x85,0x92,0xA5,0xA4,0x49,0x01,0x85,
+	0xA4,0xF0,0x2B,0x86,0xD7,0xA5,0xB4,0xF0,0x22,0xAD,0xA3,
+	0x02,0x29,0x01,0xD0,0x05,0xAD,0xA4,0x02,0xD0,0x16,0xA9,
+	0x00,0x85,0xA4,0x8D,0xA4,0x02,0xA5,0xA3,0x10,0x30,0x30,
+	0xBF,0xA2,0xA6,0x20,0xE2,0xF8,0xA5,0x9B,0xD0,0xB9,0x4C,
+	0xBC,0xFE,0xA5,0x92,0xF0,0x07,0x30,0x03,0xC6,0xB0,0x2C,
+	0xE6,0xB0,0xA9,0x00,0x85,0x92,0xE4,0xD7,0xD0,0x0F,0x8A,
+	0xD0,0xA0,0xA5,0xA9,0x30,0xBD,0xC9,0x10,0x90,0xB9,0x85,
+	0x96,0xB0,0xB5,0x8A,0x45,0x9B,0x85,0x9B,0xA5,0xB4,0xF0,
+	0xD2,0xC6,0xA3,0x30,0xC5,0x46,0xD7,0x66,0xBF,0xA2,0xDA,
+	0x20,0xE2,0xF8,0x4C,0xBC,0xFE,0xA5,0x96,0xF0,0x04,0xA5,
+	0xB4,0xF0,0x07,0xA5,0xA3,0x30,0x03,0x4C,0x97,0xF9,0x46,
+	0xB1,0xA9,0x93,0x38,0xE5,0xB1,0x65,0xB0,0x0A,0xAA,0x20,
+	0xE2,0xF8,0xE6,0x9C,0xA5,0xB4,0xD0,0x11,0xA5,0x96,0xF0,
+	0x26,0x85,0xA8,0xA9,0x00,0x85,0x96,0xA9,0x81,0x8D,0x0D,
+	0xDC,0x85,0xB4,0xA5,0x96,0x85,0xB5,0xF0,0x09,0xA9,0x00,
+	0x85,0xB4,0xA9,0x01,0x8D,0x0D,0xDC,0xA5,0xBF,0x85,0xBD,
+	0xA5,0xA8,0x05,0xA9,0x85,0xB6,0x4C,0xBC,0xFE,0x20,0x97,
+	0xFB,0x85,0x9C,0xA2,0xDA,0x20,0xE2,0xF8,0xA5,0xBE,0xF0,
+	0x02,0x85,0xA7,0xA9,0x0F,0x24,0xAA,0x10,0x17,0xA5,0xB5,
+	0xD0,0x0C,0xA6,0xBE,0xCA,0xD0,0x0B,0xA9,0x08,0x20,0x1C,
+	0xFE,0xD0,0x04,0xA9,0x00,0x85,0xAA,0x4C,0xBC,0xFE,0x70,
+	0x31,0xD0,0x18,0xA5,0xB5,0xD0,0xF5,0xA5,0xB6,0xD0,0xF1,
+	0xA5,0xA7,0x4A,0xA5,0xBD,0x30,0x03,0x90,0x18,0x18,0xB0,
+	0x15,0x29,0x0F,0x85,0xAA,0xC6,0xAA,0xD0,0xDD,0xA9,0x40,
+	0x85,0xAA,0x20,0x8E,0xFB,0xA9,0x00,0x85,0xAB,0xF0,0xD0,
+	0xA9,0x80,0x85,0xAA,0xD0,0xCA,0xA5,0xB5,0xF0,0x0A,0xA9,
+	0x04,0x20,0x1C,0xFE,0xA9,0x00,0x4C,0x4A,0xFB,0x20,0xD1,
+	0xFC,0x90,0x03,0x4C,0x48,0xFB,0xA6,0xA7,0xCA,0xF0,0x2D,
+	0xA5,0x93,0xF0,0x0C,0xA0,0x00,0xA5,0xBD,0xD1,0xAC,0xF0,
+	0x04,0xA9,0x01,0x85,0xB6,0xA5,0xB6,0xF0,0x4B,0xA2,0x3D,
+	0xE4,0x9E,0x90,0x3E,0xA6,0x9E,0xA5,0xAD,0x9D,0x01,0x01,
+	0xA5,0xAC,0x9D,0x00,0x01,0xE8,0xE8,0x86,0x9E,0x4C,0x3A,
+	0xFB,0xA6,0x9F,0xE4,0x9E,0xF0,0x35,0xA5,0xAC,0xDD,0x00,
+	0x01,0xD0,0x2E,0xA5,0xAD,0xDD,0x01,0x01,0xD0,0x27,0xE6,
+	0x9F,0xE6,0x9F,0xA5,0x93,0xF0,0x0B,0xA5,0xBD,0xA0,0x00,
+	0xD1,0xAC,0xF0,0x17,0xC8,0x84,0xB6,0xA5,0xB6,0xF0,0x07,
+	0xA9,0x10,0x20,0x1C,0xFE,0xD0,0x09,0xA5,0x93,0xD0,0x05,
+	0xA8,0xA5,0xBD,0x91,0xAC,0x20,0xDB,0xFC,0xD0,0x43,0xA9,
+	0x80,0x85,0xAA,0x78,0xA2,0x01,0x8E,0x0D,0xDC,0xAE,0x0D,
+	0xDC,0xA6,0xBE,0xCA,0x30,0x02,0x86,0xBE,0xC6,0xA7,0xF0,
+	0x08,0xA5,0x9E,0xD0,0x27,0x85,0xBE,0xF0,0x23,0x20,0x93,
+	0xFC,0x20,0x8E,0xFB,0xA0,0x00,0x84,0xAB,0xB1,0xAC,0x45,
+	0xAB,0x85,0xAB,0x20,0xDB,0xFC,0x20,0xD1,0xFC,0x90,0xF2,
+	0xA5,0xAB,0x45,0xBD,0xF0,0x05,0xA9,0x20,0x20,0x1C,0xFE,
+	0x4C,0xBC,0xFE,0xA5,0xC2,0x85,0xAD,0xA5,0xC1,0x85,0xAC,
+	0x60,0xA9,0x08,0x85,0xA3,0xA9,0x00,0x85,0xA4,0x85,0xA8,
+	0x85,0x9B,0x85,0xA9,0x60,0xA5,0xBD,0x4A,0xA9,0x60,0x90,
+	0x02,0xA9,0xB0,0xA2,0x00,0x8D,0x06,0xDC,0x8E,0x07,0xDC,
+	0xAD,0x0D,0xDC,0xA9,0x19,0x8D,0x0F,0xDC,0xA5,0x01,0x49,
+	0x08,0x85,0x01,0x29,0x08,0x60,0x38,0x66,0xB6,0x30,0x3C,
+	0xA5,0xA8,0xD0,0x12,0xA9,0x10,0xA2,0x01,0x20,0xB1,0xFB,
+	0xD0,0x2F,0xE6,0xA8,0xA5,0xB6,0x10,0x29,0x4C,0x57,0xFC,
+	0xA5,0xA9,0xD0,0x09,0x20,0xAD,0xFB,0xD0,0x1D,0xE6,0xA9,
+	0xD0,0x19,0x20,0xA6,0xFB,0xD0,0x14,0xA5,0xA4,0x49,0x01,
+	0x85,0xA4,0xF0,0x0F,0xA5,0xBD,0x49,0x01,0x85,0xBD,0x29,
+	0x01,0x45,0x9B,0x85,0x9B,0x4C,0xBC,0xFE,0x46,0xBD,0xC6,
+	0xA3,0xA5,0xA3,0xF0,0x3A,0x10,0xF3,0x20,0x97,0xFB,0x58,
+	0xA5,0xA5,0xF0,0x12,0xA2,0x00,0x86,0xD7,0xC6,0xA5,0xA6,
+	0xBE,0xE0,0x02,0xD0,0x02,0x09,0x80,0x85,0xBD,0xD0,0xD9,
+	0x20,0xD1,0xFC,0x90,0x0A,0xD0,0x91,0xE6,0xAD,0xA5,0xD7,
+	0x85,0xBD,0xB0,0xCA,0xA0,0x00,0xB1,0xAC,0x85,0xBD,0x45,
+	0xD7,0x85,0xD7,0x20,0xDB,0xFC,0xD0,0xBB,0xA5,0x9B,0x49,
+	0x01,0x85,0xBD,0x4C,0xBC,0xFE,0xC6,0xBE,0xD0,0x03,0x20,
+	0xCA,0xFC,0xA9,0x50,0x85,0xA7,0xA2,0x08,0x78,0x20,0xBD,
+	0xFC,0xD0,0xEA,0xA9,0x78,0x20,0xAF,0xFB,0xD0,0xE3,0xC6,
+	0xA7,0xD0,0xDF,0x20,0x97,0xFB,0xC6,0xAB,0x10,0xD8,0xA2,
+	0x0A,0x20,0xBD,0xFC,0x58,0xE6,0xAB,0xA5,0xBE,0xF0,0x30,
+	0x20,0x8E,0xFB,0xA2,0x09,0x86,0xA5,0x86,0xB6,0xD0,0x83,
+	0x08,0x78,0xAD,0x11,0xD0,0x09,0x10,0x8D,0x11,0xD0,0x20,
+	0xCA,0xFC,0xA9,0x7F,0x8D,0x0D,0xDC,0x20,0xDD,0xFD,0xAD,
+	0xA0,0x02,0xF0,0x09,0x8D,0x15,0x03,0xAD,0x9F,0x02,0x8D,
+	0x14,0x03,0x28,0x60,0x20,0x93,0xFC,0xF0,0x97,0xBD,0x93,
+	0xFD,0x8D,0x14,0x03,0xBD,0x94,0xFD,0x8D,0x15,0x03,0x60,
+	0xA5,0x01,0x09,0x20,0x85,0x01,0x60,0x38,0xA5,0xAC,0xE5,
+	0xAE,0xA5,0xAD,0xE5,0xAF,0x60,0xE6,0xAC,0xD0,0x02,0xE6,
+	0xAD,0x60,0xA2,0xFF,0x78,0x9A,0xD8,0x20,0x02,0xFD,0xD0,
+	0x03,0x6C,0x00,0x80,0x8E,0x16,0xD0,0x20,0xA3,0xFD,0x20,
+	0x50,0xFD,0x20,0x15,0xFD,0x20,0x5B,0xFF,0x58,0x6C,0x00,
+	0xA0,0xA2,0x05,0xBD,0x0F,0xFD,0xDD,0x03,0x80,0xD0,0x03,
+	0xCA,0xD0,0xF5,0x60,0xC3,0xC2,0xCD,0x38,0x30,0xA2,0x30,
+	0xA0,0xFD,0x18,0x86,0xC3,0x84,0xC4,0xA0,0x1F,0xB9,0x14,
+	0x03,0xB0,0x02,0xB1,0xC3,0x91,0xC3,0x99,0x14,0x03,0x88,
+	0x10,0xF1,0x60,0x31,0xEA,0x66,0xFE,0x47,0xFE,0x4A,0xF3,
+	0x91,0xF2,0x0E,0xF2,0x50,0xF2,0x33,0xF3,0x57,0xF1,0xCA,
+	0xF1,0xED,0xF6,0x3E,0xF1,0x2F,0xF3,0x66,0xFE,0xA5,0xF4,
+	0xED,0xF5,0xA9,0x00,0xA8,0x99,0x02,0x00,0x99,0x00,0x02,
+	0x99,0x00,0x03,0xC8,0xD0,0xF4,0xA2,0x3C,0xA0,0x03,0x86,
+	0xB2,0x84,0xB3,0xA8,0xA9,0x03,0x85,0xC2,0xE6,0xC2,0xB1,
+	0xC1,0xAA,0xA9,0x55,0x91,0xC1,0xD1,0xC1,0xD0,0x0F,0x2A,
+	0x91,0xC1,0xD1,0xC1,0xD0,0x08,0x8A,0x91,0xC1,0xC8,0xD0,
+	0xE8,0xF0,0xE4,0x98,0xAA,0xA4,0xC2,0x18,0x20,0x2D,0xFE,
+	0xA9,0x08,0x8D,0x82,0x02,0xA9,0x04,0x8D,0x88,0x02,0x60,
+	0x6A,0xFC,0xCD,0xFB,0x31,0xEA,0x2C,0xF9,0xA9,0x7F,0x8D,
+	0x0D,0xDC,0x8D,0x0D,0xDD,0x8D,0x00,0xDC,0xA9,0x08,0x8D,
+	0x0E,0xDC,0x8D,0x0E,0xDD,0x8D,0x0F,0xDC,0x8D,0x0F,0xDD,
+	0xA2,0x00,0x8E,0x03,0xDC,0x8E,0x03,0xDD,0x8E,0x18,0xD4,
+	0xCA,0x8E,0x02,0xDC,0xA9,0x07,0x8D,0x00,0xDD,0xA9,0x3F,
+	0x8D,0x02,0xDD,0xA9,0xE7,0x85,0x01,0xA9,0x2F,0x85,0x00,
+	0xAD,0xA6,0x02,0xF0,0x0A,0xA9,0x25,0x8D,0x04,0xDC,0xA9,
+	0x40,0x4C,0xF3,0xFD,0xA9,0x95,0x8D,0x04,0xDC,0xA9,0x42,
+	0x8D,0x05,0xDC,0x4C,0x6E,0xFF,0x85,0xB7,0x86,0xBB,0x84,
+	0xBC,0x60,0x85,0xB8,0x86,0xBA,0x84,0xB9,0x60,0xA5,0xBA,
+	0xC9,0x02,0xD0,0x0D,0xAD,0x97,0x02,0x48,0xA9,0x00,0x8D,
+	0x97,0x02,0x68,0x60,0x85,0x9D,0xA5,0x90,0x05,0x90,0x85,
+	0x90,0x60,0x8D,0x85,0x02,0x60,0x90,0x06,0xAE,0x83,0x02,
+	0xAC,0x84,0x02,0x8E,0x83,0x02,0x8C,0x84,0x02,0x60,0x90,
+	0x06,0xAE,0x81,0x02,0xAC,0x82,0x02,0x8E,0x81,0x02,0x8C,
+	0x82,0x02,0x60,0x78,0x6C,0x18,0x03,0x48,0x8A,0x48,0x98,
+	0x48,0xA9,0x7F,0x8D,0x0D,0xDD,0xAC,0x0D,0xDD,0x30,0x1C,
+	0x20,0x02,0xFD,0xD0,0x03,0x6C,0x02,0x80,0x20,0xBC,0xF6,
+	0x20,0xE1,0xFF,0xD0,0x0C,0x20,0x15,0xFD,0x20,0xA3,0xFD,
+	0x20,0x18,0xE5,0x6C,0x02,0xA0,0x98,0x2D,0xA1,0x02,0xAA,
+	0x29,0x01,0xF0,0x28,0xAD,0x00,0xDD,0x29,0xFB,0x05,0xB5,
+	0x8D,0x00,0xDD,0xAD,0xA1,0x02,0x8D,0x0D,0xDD,0x8A,0x29,
+	0x12,0xF0,0x0D,0x29,0x02,0xF0,0x06,0x20,0xD6,0xFE,0x4C,
+	0x9D,0xFE,0x20,0x07,0xFF,0x20,0xBB,0xEE,0x4C,0xB6,0xFE,
+	0x8A,0x29,0x02,0xF0,0x06,0x20,0xD6,0xFE,0x4C,0xB6,0xFE,
+	0x8A,0x29,0x10,0xF0,0x03,0x20,0x07,0xFF,0xAD,0xA1,0x02,
+	0x8D,0x0D,0xDD,0x68,0xA8,0x68,0xAA,0x68,0x40,0xC1,0x27,
+	0x3E,0x1A,0xC5,0x11,0x74,0x0E,0xED,0x0C,0x45,0x06,0xF0,
+	0x02,0x46,0x01,0xB8,0x00,0x71,0x00,0xAD,0x01,0xDD,0x29,
+	0x01,0x85,0xA7,0xAD,0x06,0xDD,0xE9,0x1C,0x6D,0x99,0x02,
+	0x8D,0x06,0xDD,0xAD,0x07,0xDD,0x6D,0x9A,0x02,0x8D,0x07,
+	0xDD,0xA9,0x11,0x8D,0x0F,0xDD,0xAD,0xA1,0x02,0x8D,0x0D,
+	0xDD,0xA9,0xFF,0x8D,0x06,0xDD,0x8D,0x07,0xDD,0x4C,0x59,
+	0xEF,0xAD,0x95,0x02,0x8D,0x06,0xDD,0xAD,0x96,0x02,0x8D,
+	0x07,0xDD,0xA9,0x11,0x8D,0x0F,0xDD,0xA9,0x12,0x4D,0xA1,
+	0x02,0x8D,0xA1,0x02,0xA9,0xFF,0x8D,0x06,0xDD,0x8D,0x07,
+	0xDD,0xAE,0x98,0x02,0x86,0xA8,0x60,0xAA,0xAD,0x96,0x02,
+	0x2A,0xA8,0x8A,0x69,0xC8,0x8D,0x99,0x02,0x98,0x69,0x00,
+	0x8D,0x9A,0x02,0x60,0xEA,0xEA,0x08,0x68,0x29,0xEF,0x48,
+	0x48,0x8A,0x48,0x98,0x48,0xBA,0xBD,0x04,0x01,0x29,0x10,
+	0xF0,0x03,0x6C,0x16,0x03,0x6C,0x14,0x03,0x20,0x18,0xE5,
+	0xAD,0x12,0xD0,0xD0,0xFB,0xAD,0x19,0xD0,0x29,0x01,0x8D,
+	0xA6,0x02,0x4C,0xDD,0xFD,0xA9,0x81,0x8D,0x0D,0xDC,0xAD,
+	0x0E,0xDC,0x29,0x80,0x09,0x11,0x8D,0x0E,0xDC,0x4C,0x8E,
+	0xEE,0x03,0x4C,0x5B,0xFF,0x4C,0xA3,0xFD,0x4C,0x50,0xFD,
+	0x4C,0x15,0xFD,0x4C,0x1A,0xFD,0x4C,0x18,0xFE,0x4C,0xB9,
+	0xED,0x4C,0xC7,0xED,0x4C,0x25,0xFE,0x4C,0x34,0xFE,0x4C,
+	0x87,0xEA,0x4C,0x21,0xFE,0x4C,0x13,0xEE,0x4C,0xDD,0xED,
+	0x4C,0xEF,0xED,0x4C,0xFE,0xED,0x4C,0x0C,0xED,0x4C,0x09,
+	0xED,0x4C,0x07,0xFE,0x4C,0x00,0xFE,0x4C,0xF9,0xFD,0x6C,
+	0x1A,0x03,0x6C,0x1C,0x03,0x6C,0x1E,0x03,0x6C,0x20,0x03,
+	0x6C,0x22,0x03,0x6C,0x24,0x03,0x6C,0x26,0x03,
+	
+#if APPLY_PATCHES	
+	0xD2,0x9E,0xF4, /* PATCH LOAD */
+	0XF2,0xDD,0xF5, /* PATCH SAVE */
+#else	
+	0x4C,0x9E,0xF4, /* LOAD */
+    0x4C,0xDD,0xF5, /* SAVE */
+#endif
+	
+	0x4C,0xE4,0xF6,0x4C,0xDD,0xF6,0x6C,
+	0x28,0x03,0x6C,0x2A,0x03,0x6C,0x2C,0x03,0x4C,0x9B,0xF6,
+	0x4C,0x05,0xE5,0x4C,0x0A,0xE5,0x4C,0x00,0xE5,0x52,0x52,
+	0x42,0x59,0x43,0xFE,0xE2,0xFC,0x48,0xFF,
+};
+
+//file auto-generated from characters.901225-01.bin by bin2h.exe
+const size_t rom_characters_len = 4096;
+const unsigned char PROGMEM rom_characters[4096]=
+{
+	0x3C,0x66,0x6E,0x6E,0x60,0x62,0x3C,0x00,0x18,0x3C,0x66,
+	0x7E,0x66,0x66,0x66,0x00,0x7C,0x66,0x66,0x7C,0x66,0x66,
+	0x7C,0x00,0x3C,0x66,0x60,0x60,0x60,0x66,0x3C,0x00,0x78,
+	0x6C,0x66,0x66,0x66,0x6C,0x78,0x00,0x7E,0x60,0x60,0x78,
+	0x60,0x60,0x7E,0x00,0x7E,0x60,0x60,0x78,0x60,0x60,0x60,
+	0x00,0x3C,0x66,0x60,0x6E,0x66,0x66,0x3C,0x00,0x66,0x66,
+	0x66,0x7E,0x66,0x66,0x66,0x00,0x3C,0x18,0x18,0x18,0x18,
+	0x18,0x3C,0x00,0x1E,0x0C,0x0C,0x0C,0x0C,0x6C,0x38,0x00,
+	0x66,0x6C,0x78,0x70,0x78,0x6C,0x66,0x00,0x60,0x60,0x60,
+	0x60,0x60,0x60,0x7E,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,
+	0x63,0x00,0x66,0x76,0x7E,0x7E,0x6E,0x66,0x66,0x00,0x3C,
+	0x66,0x66,0x66,0x66,0x66,0x3C,0x00,0x7C,0x66,0x66,0x7C,
+	0x60,0x60,0x60,0x00,0x3C,0x66,0x66,0x66,0x66,0x3C,0x0E,
+	0x00,0x7C,0x66,0x66,0x7C,0x78,0x6C,0x66,0x00,0x3C,0x66,
+	0x60,0x3C,0x06,0x66,0x3C,0x00,0x7E,0x18,0x18,0x18,0x18,
+	0x18,0x18,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3C,0x00,
+	0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00,0x63,0x63,0x63,
+	0x6B,0x7F,0x77,0x63,0x00,0x66,0x66,0x3C,0x18,0x3C,0x66,
+	0x66,0x00,0x66,0x66,0x66,0x3C,0x18,0x18,0x18,0x00,0x7E,
+	0x06,0x0C,0x18,0x30,0x60,0x7E,0x00,0x3C,0x30,0x30,0x30,
+	0x30,0x30,0x3C,0x00,0x0C,0x12,0x30,0x7C,0x30,0x62,0xFC,
+	0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x18,
+	0x3C,0x7E,0x18,0x18,0x18,0x18,0x00,0x10,0x30,0x7F,0x7F,
+	0x30,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x18,0x18,0x18,0x18,0x00,0x00,0x18,0x00,0x66,0x66,0x66,
+	0x00,0x00,0x00,0x00,0x00,0x66,0x66,0xFF,0x66,0xFF,0x66,
+	0x66,0x00,0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00,0x62,
+	0x66,0x0C,0x18,0x30,0x66,0x46,0x00,0x3C,0x66,0x3C,0x38,
+	0x67,0x66,0x3F,0x00,0x06,0x0C,0x18,0x00,0x00,0x00,0x00,
+	0x00,0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00,0x30,0x18,
+	0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x66,0x3C,0xFF,0x3C,
+	0x66,0x00,0x00,0x00,0x18,0x18,0x7E,0x18,0x18,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30,0x00,0x00,0x00,
+	0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,
+	0x18,0x00,0x00,0x03,0x06,0x0C,0x18,0x30,0x60,0x00,0x3C,
+	0x66,0x6E,0x76,0x66,0x66,0x3C,0x00,0x18,0x18,0x38,0x18,
+	0x18,0x18,0x7E,0x00,0x3C,0x66,0x06,0x0C,0x30,0x60,0x7E,
+	0x00,0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00,0x06,0x0E,
+	0x1E,0x66,0x7F,0x06,0x06,0x00,0x7E,0x60,0x7C,0x06,0x06,
+	0x66,0x3C,0x00,0x3C,0x66,0x60,0x7C,0x66,0x66,0x3C,0x00,
+	0x7E,0x66,0x0C,0x18,0x18,0x18,0x18,0x00,0x3C,0x66,0x66,
+	0x3C,0x66,0x66,0x3C,0x00,0x3C,0x66,0x66,0x3E,0x06,0x66,
+	0x3C,0x00,0x00,0x00,0x18,0x00,0x00,0x18,0x00,0x00,0x00,
+	0x00,0x18,0x00,0x00,0x18,0x18,0x30,0x0E,0x18,0x30,0x60,
+	0x30,0x18,0x0E,0x00,0x00,0x00,0x7E,0x00,0x7E,0x00,0x00,
+	0x00,0x70,0x18,0x0C,0x06,0x0C,0x18,0x70,0x00,0x3C,0x66,
+	0x06,0x0C,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0xFF,0xFF,
+	0x00,0x00,0x00,0x08,0x1C,0x3E,0x7F,0x7F,0x1C,0x3E,0x00,
+	0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,
+	0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,
+	0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x30,0x30,0x30,0x30,
+	0x30,0x30,0x30,0x30,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,
+	0x0C,0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,
+	0x1C,0x0F,0x07,0x00,0x00,0x00,0x18,0x18,0x38,0xF0,0xE0,
+	0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xFF,0xFF,
+	0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x03,0x07,0x0E,
+	0x1C,0x38,0x70,0xE0,0xC0,0xFF,0xFF,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xFF,0xFF,0x03,0x03,0x03,0x03,0x03,0x03,0x00,
+	0x3C,0x7E,0x7E,0x7E,0x7E,0x3C,0x00,0x00,0x00,0x00,0x00,
+	0x00,0xFF,0xFF,0x00,0x36,0x7F,0x7F,0x7F,0x3E,0x1C,0x08,
+	0x00,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x00,0x00,
+	0x00,0x07,0x0F,0x1C,0x18,0x18,0xC3,0xE7,0x7E,0x3C,0x3C,
+	0x7E,0xE7,0xC3,0x00,0x3C,0x7E,0x66,0x66,0x7E,0x3C,0x00,
+	0x18,0x18,0x66,0x66,0x18,0x18,0x3C,0x00,0x06,0x06,0x06,
+	0x06,0x06,0x06,0x06,0x06,0x08,0x1C,0x3E,0x7F,0x3E,0x1C,
+	0x08,0x00,0x18,0x18,0x18,0xFF,0xFF,0x18,0x18,0x18,0xC0,
+	0xC0,0x30,0x30,0xC0,0xC0,0x30,0x30,0x18,0x18,0x18,0x18,
+	0x18,0x18,0x18,0x18,0x00,0x00,0x03,0x3E,0x76,0x36,0x36,
+	0x00,0xFF,0x7F,0x3F,0x1F,0x0F,0x07,0x03,0x01,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0xF0,
+	0xF0,0xF0,0xF0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0xFF,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xCC,0xCC,0x33,0x33,0xCC,0xCC,0x33,0x33,0x03,
+	0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x00,0x00,0x00,0x00,
+	0xCC,0xCC,0x33,0x33,0xFF,0xFE,0xFC,0xF8,0xF0,0xE0,0xC0,
+	0x80,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x18,0x18,
+	0x18,0x1F,0x1F,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x0F,
+	0x0F,0x0F,0x0F,0x18,0x18,0x18,0x1F,0x1F,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xF8,0xF8,0x18,0x18,0x18,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x1F,0x1F,0x18,
+	0x18,0x18,0x18,0x18,0x18,0xFF,0xFF,0x00,0x00,0x00,0x00,
+	0x00,0x00,0xFF,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,0xF8,
+	0xF8,0x18,0x18,0x18,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0x07,0x07,
+	0x07,0x07,0x07,0x07,0x07,0x07,0xFF,0xFF,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x03,0x03,0x03,
+	0x03,0x03,0x03,0xFF,0xFF,0x00,0x00,0x00,0x00,0xF0,0xF0,
+	0xF0,0xF0,0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,0x00,0x18,
+	0x18,0x18,0xF8,0xF8,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,
+	0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0x0F,0x0F,0x0F,
+	0x0F,0xC3,0x99,0x91,0x91,0x9F,0x99,0xC3,0xFF,0xE7,0xC3,
+	0x99,0x81,0x99,0x99,0x99,0xFF,0x83,0x99,0x99,0x83,0x99,
+	0x99,0x83,0xFF,0xC3,0x99,0x9F,0x9F,0x9F,0x99,0xC3,0xFF,
+	0x87,0x93,0x99,0x99,0x99,0x93,0x87,0xFF,0x81,0x9F,0x9F,
+	0x87,0x9F,0x9F,0x81,0xFF,0x81,0x9F,0x9F,0x87,0x9F,0x9F,
+	0x9F,0xFF,0xC3,0x99,0x9F,0x91,0x99,0x99,0xC3,0xFF,0x99,
+	0x99,0x99,0x81,0x99,0x99,0x99,0xFF,0xC3,0xE7,0xE7,0xE7,
+	0xE7,0xE7,0xC3,0xFF,0xE1,0xF3,0xF3,0xF3,0xF3,0x93,0xC7,
+	0xFF,0x99,0x93,0x87,0x8F,0x87,0x93,0x99,0xFF,0x9F,0x9F,
+	0x9F,0x9F,0x9F,0x9F,0x81,0xFF,0x9C,0x88,0x80,0x94,0x9C,
+	0x9C,0x9C,0xFF,0x99,0x89,0x81,0x81,0x91,0x99,0x99,0xFF,
+	0xC3,0x99,0x99,0x99,0x99,0x99,0xC3,0xFF,0x83,0x99,0x99,
+	0x83,0x9F,0x9F,0x9F,0xFF,0xC3,0x99,0x99,0x99,0x99,0xC3,
+	0xF1,0xFF,0x83,0x99,0x99,0x83,0x87,0x93,0x99,0xFF,0xC3,
+	0x99,0x9F,0xC3,0xF9,0x99,0xC3,0xFF,0x81,0xE7,0xE7,0xE7,
+	0xE7,0xE7,0xE7,0xFF,0x99,0x99,0x99,0x99,0x99,0x99,0xC3,
+	0xFF,0x99,0x99,0x99,0x99,0x99,0xC3,0xE7,0xFF,0x9C,0x9C,
+	0x9C,0x94,0x80,0x88,0x9C,0xFF,0x99,0x99,0xC3,0xE7,0xC3,
+	0x99,0x99,0xFF,0x99,0x99,0x99,0xC3,0xE7,0xE7,0xE7,0xFF,
+	0x81,0xF9,0xF3,0xE7,0xCF,0x9F,0x81,0xFF,0xC3,0xCF,0xCF,
+	0xCF,0xCF,0xCF,0xC3,0xFF,0xF3,0xED,0xCF,0x83,0xCF,0x9D,
+	0x03,0xFF,0xC3,0xF3,0xF3,0xF3,0xF3,0xF3,0xC3,0xFF,0xFF,
+	0xE7,0xC3,0x81,0xE7,0xE7,0xE7,0xE7,0xFF,0xEF,0xCF,0x80,
+	0x80,0xCF,0xEF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xE7,0xE7,0xE7,0xE7,0xFF,0xFF,0xE7,0xFF,0x99,0x99,
+	0x99,0xFF,0xFF,0xFF,0xFF,0xFF,0x99,0x99,0x00,0x99,0x00,
+	0x99,0x99,0xFF,0xE7,0xC1,0x9F,0xC3,0xF9,0x83,0xE7,0xFF,
+	0x9D,0x99,0xF3,0xE7,0xCF,0x99,0xB9,0xFF,0xC3,0x99,0xC3,
+	0xC7,0x98,0x99,0xC0,0xFF,0xF9,0xF3,0xE7,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xF3,0xE7,0xCF,0xCF,0xCF,0xE7,0xF3,0xFF,0xCF,
+	0xE7,0xF3,0xF3,0xF3,0xE7,0xCF,0xFF,0xFF,0x99,0xC3,0x00,
+	0xC3,0x99,0xFF,0xFF,0xFF,0xE7,0xE7,0x81,0xE7,0xE7,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE7,0xE7,0xCF,0xFF,0xFF,
+	0xFF,0x81,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xE7,0xE7,0xFF,0xFF,0xFC,0xF9,0xF3,0xE7,0xCF,0x9F,0xFF,
+	0xC3,0x99,0x91,0x89,0x99,0x99,0xC3,0xFF,0xE7,0xE7,0xC7,
+	0xE7,0xE7,0xE7,0x81,0xFF,0xC3,0x99,0xF9,0xF3,0xCF,0x9F,
+	0x81,0xFF,0xC3,0x99,0xF9,0xE3,0xF9,0x99,0xC3,0xFF,0xF9,
+	0xF1,0xE1,0x99,0x80,0xF9,0xF9,0xFF,0x81,0x9F,0x83,0xF9,
+	0xF9,0x99,0xC3,0xFF,0xC3,0x99,0x9F,0x83,0x99,0x99,0xC3,
+	0xFF,0x81,0x99,0xF3,0xE7,0xE7,0xE7,0xE7,0xFF,0xC3,0x99,
+	0x99,0xC3,0x99,0x99,0xC3,0xFF,0xC3,0x99,0x99,0xC1,0xF9,
+	0x99,0xC3,0xFF,0xFF,0xFF,0xE7,0xFF,0xFF,0xE7,0xFF,0xFF,
+	0xFF,0xFF,0xE7,0xFF,0xFF,0xE7,0xE7,0xCF,0xF1,0xE7,0xCF,
+	0x9F,0xCF,0xE7,0xF1,0xFF,0xFF,0xFF,0x81,0xFF,0x81,0xFF,
+	0xFF,0xFF,0x8F,0xE7,0xF3,0xF9,0xF3,0xE7,0x8F,0xFF,0xC3,
+	0x99,0xF9,0xF3,0xE7,0xFF,0xE7,0xFF,0xFF,0xFF,0xFF,0x00,
+	0x00,0xFF,0xFF,0xFF,0xF7,0xE3,0xC1,0x80,0x80,0xE3,0xC1,
+	0xFF,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xFF,0xFF,
+	0xFF,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0xCF,0xCF,0xCF,
+	0xCF,0xCF,0xCF,0xCF,0xCF,0xF3,0xF3,0xF3,0xF3,0xF3,0xF3,
+	0xF3,0xF3,0xFF,0xFF,0xFF,0x1F,0x0F,0xC7,0xE7,0xE7,0xE7,
+	0xE7,0xE3,0xF0,0xF8,0xFF,0xFF,0xFF,0xE7,0xE7,0xC7,0x0F,
+	0x1F,0xFF,0xFF,0xFF,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x00,
+	0x00,0x3F,0x1F,0x8F,0xC7,0xE3,0xF1,0xF8,0xFC,0xFC,0xF8,
+	0xF1,0xE3,0xC7,0x8F,0x1F,0x3F,0x00,0x00,0x3F,0x3F,0x3F,
+	0x3F,0x3F,0x3F,0x00,0x00,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,
+	0xFF,0xC3,0x81,0x81,0x81,0x81,0xC3,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0x00,0x00,0xFF,0xC9,0x80,0x80,0x80,0xC1,0xE3,
+	0xF7,0xFF,0x9F,0x9F,0x9F,0x9F,0x9F,0x9F,0x9F,0x9F,0xFF,
+	0xFF,0xFF,0xF8,0xF0,0xE3,0xE7,0xE7,0x3C,0x18,0x81,0xC3,
+	0xC3,0x81,0x18,0x3C,0xFF,0xC3,0x81,0x99,0x99,0x81,0xC3,
+	0xFF,0xE7,0xE7,0x99,0x99,0xE7,0xE7,0xC3,0xFF,0xF9,0xF9,
+	0xF9,0xF9,0xF9,0xF9,0xF9,0xF9,0xF7,0xE3,0xC1,0x80,0xC1,
+	0xE3,0xF7,0xFF,0xE7,0xE7,0xE7,0x00,0x00,0xE7,0xE7,0xE7,
+	0x3F,0x3F,0xCF,0xCF,0x3F,0x3F,0xCF,0xCF,0xE7,0xE7,0xE7,
+	0xE7,0xE7,0xE7,0xE7,0xE7,0xFF,0xFF,0xFC,0xC1,0x89,0xC9,
+	0xC9,0xFF,0x00,0x80,0xC0,0xE0,0xF0,0xF8,0xFC,0xFE,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,
+	0x0F,0x0F,0x0F,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+	0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x3F,0x3F,0x3F,0x3F,0x3F,
+	0x3F,0x3F,0x3F,0x33,0x33,0xCC,0xCC,0x33,0x33,0xCC,0xCC,
+	0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFF,0xFF,0xFF,
+	0xFF,0x33,0x33,0xCC,0xCC,0x00,0x01,0x03,0x07,0x0F,0x1F,
+	0x3F,0x7F,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xE7,
+	0xE7,0xE7,0xE0,0xE0,0xE7,0xE7,0xE7,0xFF,0xFF,0xFF,0xFF,
+	0xF0,0xF0,0xF0,0xF0,0xE7,0xE7,0xE7,0xE0,0xE0,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0x07,0x07,0xE7,0xE7,0xE7,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0xFF,0xE0,0xE0,
+	0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0x00,0x00,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0x00,0x00,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,
+	0x07,0x07,0xE7,0xE7,0xE7,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,
+	0x3F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0xF8,
+	0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,0x00,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0xFC,0xFC,
+	0xFC,0xFC,0xFC,0xFC,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x0F,
+	0x0F,0x0F,0x0F,0xF0,0xF0,0xF0,0xF0,0xFF,0xFF,0xFF,0xFF,
+	0xE7,0xE7,0xE7,0x07,0x07,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,
+	0x0F,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,0xF0,0xF0,
+	0xF0,0xF0,0x3C,0x66,0x6E,0x6E,0x60,0x62,0x3C,0x00,0x00,
+	0x00,0x3C,0x06,0x3E,0x66,0x3E,0x00,0x00,0x60,0x60,0x7C,
+	0x66,0x66,0x7C,0x00,0x00,0x00,0x3C,0x60,0x60,0x60,0x3C,
+	0x00,0x00,0x06,0x06,0x3E,0x66,0x66,0x3E,0x00,0x00,0x00,
+	0x3C,0x66,0x7E,0x60,0x3C,0x00,0x00,0x0E,0x18,0x3E,0x18,
+	0x18,0x18,0x00,0x00,0x00,0x3E,0x66,0x66,0x3E,0x06,0x7C,
+	0x00,0x60,0x60,0x7C,0x66,0x66,0x66,0x00,0x00,0x18,0x00,
+	0x38,0x18,0x18,0x3C,0x00,0x00,0x06,0x00,0x06,0x06,0x06,
+	0x06,0x3C,0x00,0x60,0x60,0x6C,0x78,0x6C,0x66,0x00,0x00,
+	0x38,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x66,0x7F,
+	0x7F,0x6B,0x63,0x00,0x00,0x00,0x7C,0x66,0x66,0x66,0x66,
+	0x00,0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00,0x00,0x00,
+	0x7C,0x66,0x66,0x7C,0x60,0x60,0x00,0x00,0x3E,0x66,0x66,
+	0x3E,0x06,0x06,0x00,0x00,0x7C,0x66,0x60,0x60,0x60,0x00,
+	0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00,0x00,0x18,0x7E,
+	0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x66,0x66,0x66,0x66,
+	0x3E,0x00,0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00,0x00,
+	0x00,0x63,0x6B,0x7F,0x3E,0x36,0x00,0x00,0x00,0x66,0x3C,
+	0x18,0x3C,0x66,0x00,0x00,0x00,0x66,0x66,0x66,0x3E,0x0C,
+	0x78,0x00,0x00,0x7E,0x0C,0x18,0x30,0x7E,0x00,0x3C,0x30,
+	0x30,0x30,0x30,0x30,0x3C,0x00,0x0C,0x12,0x30,0x7C,0x30,
+	0x62,0xFC,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,
+	0x00,0x18,0x3C,0x7E,0x18,0x18,0x18,0x18,0x00,0x10,0x30,
+	0x7F,0x7F,0x30,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x18,0x18,0x18,0x18,0x00,0x00,0x18,0x00,0x66,
+	0x66,0x66,0x00,0x00,0x00,0x00,0x00,0x66,0x66,0xFF,0x66,
+	0xFF,0x66,0x66,0x00,0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,
+	0x00,0x62,0x66,0x0C,0x18,0x30,0x66,0x46,0x00,0x3C,0x66,
+	0x3C,0x38,0x67,0x66,0x3F,0x00,0x06,0x0C,0x18,0x00,0x00,
+	0x00,0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00,
+	0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x66,0x3C,
+	0xFF,0x3C,0x66,0x00,0x00,0x00,0x18,0x18,0x7E,0x18,0x18,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30,0x00,
+	0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x18,0x18,0x00,0x00,0x03,0x06,0x0C,0x18,0x30,0x60,
+	0x00,0x3C,0x66,0x6E,0x76,0x66,0x66,0x3C,0x00,0x18,0x18,
+	0x38,0x18,0x18,0x18,0x7E,0x00,0x3C,0x66,0x06,0x0C,0x30,
+	0x60,0x7E,0x00,0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00,
+	0x06,0x0E,0x1E,0x66,0x7F,0x06,0x06,0x00,0x7E,0x60,0x7C,
+	0x06,0x06,0x66,0x3C,0x00,0x3C,0x66,0x60,0x7C,0x66,0x66,
+	0x3C,0x00,0x7E,0x66,0x0C,0x18,0x18,0x18,0x18,0x00,0x3C,
+	0x66,0x66,0x3C,0x66,0x66,0x3C,0x00,0x3C,0x66,0x66,0x3E,
+	0x06,0x66,0x3C,0x00,0x00,0x00,0x18,0x00,0x00,0x18,0x00,
+	0x00,0x00,0x00,0x18,0x00,0x00,0x18,0x18,0x30,0x0E,0x18,
+	0x30,0x60,0x30,0x18,0x0E,0x00,0x00,0x00,0x7E,0x00,0x7E,
+	0x00,0x00,0x00,0x70,0x18,0x0C,0x06,0x0C,0x18,0x70,0x00,
+	0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00,0x00,0x00,0x00,
+	0xFF,0xFF,0x00,0x00,0x00,0x18,0x3C,0x66,0x7E,0x66,0x66,
+	0x66,0x00,0x7C,0x66,0x66,0x7C,0x66,0x66,0x7C,0x00,0x3C,
+	0x66,0x60,0x60,0x60,0x66,0x3C,0x00,0x78,0x6C,0x66,0x66,
+	0x66,0x6C,0x78,0x00,0x7E,0x60,0x60,0x78,0x60,0x60,0x7E,
+	0x00,0x7E,0x60,0x60,0x78,0x60,0x60,0x60,0x00,0x3C,0x66,
+	0x60,0x6E,0x66,0x66,0x3C,0x00,0x66,0x66,0x66,0x7E,0x66,
+	0x66,0x66,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,
+	0x1E,0x0C,0x0C,0x0C,0x0C,0x6C,0x38,0x00,0x66,0x6C,0x78,
+	0x70,0x78,0x6C,0x66,0x00,0x60,0x60,0x60,0x60,0x60,0x60,
+	0x7E,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x00,0x66,
+	0x76,0x7E,0x7E,0x6E,0x66,0x66,0x00,0x3C,0x66,0x66,0x66,
+	0x66,0x66,0x3C,0x00,0x7C,0x66,0x66,0x7C,0x60,0x60,0x60,
+	0x00,0x3C,0x66,0x66,0x66,0x66,0x3C,0x0E,0x00,0x7C,0x66,
+	0x66,0x7C,0x78,0x6C,0x66,0x00,0x3C,0x66,0x60,0x3C,0x06,
+	0x66,0x3C,0x00,0x7E,0x18,0x18,0x18,0x18,0x18,0x18,0x00,
+	0x66,0x66,0x66,0x66,0x66,0x66,0x3C,0x00,0x66,0x66,0x66,
+	0x66,0x66,0x3C,0x18,0x00,0x63,0x63,0x63,0x6B,0x7F,0x77,
+	0x63,0x00,0x66,0x66,0x3C,0x18,0x3C,0x66,0x66,0x00,0x66,
+	0x66,0x66,0x3C,0x18,0x18,0x18,0x00,0x7E,0x06,0x0C,0x18,
+	0x30,0x60,0x7E,0x00,0x18,0x18,0x18,0xFF,0xFF,0x18,0x18,
+	0x18,0xC0,0xC0,0x30,0x30,0xC0,0xC0,0x30,0x30,0x18,0x18,
+	0x18,0x18,0x18,0x18,0x18,0x18,0x33,0x33,0xCC,0xCC,0x33,
+	0x33,0xCC,0xCC,0x33,0x99,0xCC,0x66,0x33,0x99,0xCC,0x66,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,
+	0xF0,0xF0,0xF0,0xF0,0xF0,0x00,0x00,0x00,0x00,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xC0,0xC0,0xCC,0xCC,0x33,0x33,0xCC,0xCC,0x33,
+	0x33,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x00,0x00,
+	0x00,0x00,0xCC,0xCC,0x33,0x33,0xCC,0x99,0x33,0x66,0xCC,
+	0x99,0x33,0x66,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,
+	0x18,0x18,0x18,0x1F,0x1F,0x18,0x18,0x18,0x00,0x00,0x00,
+	0x00,0x0F,0x0F,0x0F,0x0F,0x18,0x18,0x18,0x1F,0x1F,0x00,
+	0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x18,0x18,0x18,0x00,
+	0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x1F,
+	0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0xFF,0xFF,0x00,0x00,
+	0x00,0x00,0x00,0x00,0xFF,0xFF,0x18,0x18,0x18,0x18,0x18,
+	0x18,0xF8,0xF8,0x18,0x18,0x18,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xC0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,
+	0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0xFF,0xFF,0x00,
+	0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x01,
+	0x03,0x06,0x6C,0x78,0x70,0x60,0x00,0x00,0x00,0x00,0x00,
+	0xF0,0xF0,0xF0,0xF0,0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,
+	0x00,0x18,0x18,0x18,0xF8,0xF8,0x00,0x00,0x00,0xF0,0xF0,
+	0xF0,0xF0,0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0x0F,
+	0x0F,0x0F,0x0F,0xC3,0x99,0x91,0x91,0x9F,0x99,0xC3,0xFF,
+	0xFF,0xFF,0xC3,0xF9,0xC1,0x99,0xC1,0xFF,0xFF,0x9F,0x9F,
+	0x83,0x99,0x99,0x83,0xFF,0xFF,0xFF,0xC3,0x9F,0x9F,0x9F,
+	0xC3,0xFF,0xFF,0xF9,0xF9,0xC1,0x99,0x99,0xC1,0xFF,0xFF,
+	0xFF,0xC3,0x99,0x81,0x9F,0xC3,0xFF,0xFF,0xF1,0xE7,0xC1,
+	0xE7,0xE7,0xE7,0xFF,0xFF,0xFF,0xC1,0x99,0x99,0xC1,0xF9,
+	0x83,0xFF,0x9F,0x9F,0x83,0x99,0x99,0x99,0xFF,0xFF,0xE7,
+	0xFF,0xC7,0xE7,0xE7,0xC3,0xFF,0xFF,0xF9,0xFF,0xF9,0xF9,
+	0xF9,0xF9,0xC3,0xFF,0x9F,0x9F,0x93,0x87,0x93,0x99,0xFF,
+	0xFF,0xC7,0xE7,0xE7,0xE7,0xE7,0xC3,0xFF,0xFF,0xFF,0x99,
+	0x80,0x80,0x94,0x9C,0xFF,0xFF,0xFF,0x83,0x99,0x99,0x99,
+	0x99,0xFF,0xFF,0xFF,0xC3,0x99,0x99,0x99,0xC3,0xFF,0xFF,
+	0xFF,0x83,0x99,0x99,0x83,0x9F,0x9F,0xFF,0xFF,0xC1,0x99,
+	0x99,0xC1,0xF9,0xF9,0xFF,0xFF,0x83,0x99,0x9F,0x9F,0x9F,
+	0xFF,0xFF,0xFF,0xC1,0x9F,0xC3,0xF9,0x83,0xFF,0xFF,0xE7,
+	0x81,0xE7,0xE7,0xE7,0xF1,0xFF,0xFF,0xFF,0x99,0x99,0x99,
+	0x99,0xC1,0xFF,0xFF,0xFF,0x99,0x99,0x99,0xC3,0xE7,0xFF,
+	0xFF,0xFF,0x9C,0x94,0x80,0xC1,0xC9,0xFF,0xFF,0xFF,0x99,
+	0xC3,0xE7,0xC3,0x99,0xFF,0xFF,0xFF,0x99,0x99,0x99,0xC1,
+	0xF3,0x87,0xFF,0xFF,0x81,0xF3,0xE7,0xCF,0x81,0xFF,0xC3,
+	0xCF,0xCF,0xCF,0xCF,0xCF,0xC3,0xFF,0xF3,0xED,0xCF,0x83,
+	0xCF,0x9D,0x03,0xFF,0xC3,0xF3,0xF3,0xF3,0xF3,0xF3,0xC3,
+	0xFF,0xFF,0xE7,0xC3,0x81,0xE7,0xE7,0xE7,0xE7,0xFF,0xEF,
+	0xCF,0x80,0x80,0xCF,0xEF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xE7,0xE7,0xE7,0xE7,0xFF,0xFF,0xE7,0xFF,
+	0x99,0x99,0x99,0xFF,0xFF,0xFF,0xFF,0xFF,0x99,0x99,0x00,
+	0x99,0x00,0x99,0x99,0xFF,0xE7,0xC1,0x9F,0xC3,0xF9,0x83,
+	0xE7,0xFF,0x9D,0x99,0xF3,0xE7,0xCF,0x99,0xB9,0xFF,0xC3,
+	0x99,0xC3,0xC7,0x98,0x99,0xC0,0xFF,0xF9,0xF3,0xE7,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xF3,0xE7,0xCF,0xCF,0xCF,0xE7,0xF3,
+	0xFF,0xCF,0xE7,0xF3,0xF3,0xF3,0xE7,0xCF,0xFF,0xFF,0x99,
+	0xC3,0x00,0xC3,0x99,0xFF,0xFF,0xFF,0xE7,0xE7,0x81,0xE7,
+	0xE7,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE7,0xE7,0xCF,
+	0xFF,0xFF,0xFF,0x81,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xE7,0xE7,0xFF,0xFF,0xFC,0xF9,0xF3,0xE7,0xCF,
+	0x9F,0xFF,0xC3,0x99,0x91,0x89,0x99,0x99,0xC3,0xFF,0xE7,
+	0xE7,0xC7,0xE7,0xE7,0xE7,0x81,0xFF,0xC3,0x99,0xF9,0xF3,
+	0xCF,0x9F,0x81,0xFF,0xC3,0x99,0xF9,0xE3,0xF9,0x99,0xC3,
+	0xFF,0xF9,0xF1,0xE1,0x99,0x80,0xF9,0xF9,0xFF,0x81,0x9F,
+	0x83,0xF9,0xF9,0x99,0xC3,0xFF,0xC3,0x99,0x9F,0x83,0x99,
+	0x99,0xC3,0xFF,0x81,0x99,0xF3,0xE7,0xE7,0xE7,0xE7,0xFF,
+	0xC3,0x99,0x99,0xC3,0x99,0x99,0xC3,0xFF,0xC3,0x99,0x99,
+	0xC1,0xF9,0x99,0xC3,0xFF,0xFF,0xFF,0xE7,0xFF,0xFF,0xE7,
+	0xFF,0xFF,0xFF,0xFF,0xE7,0xFF,0xFF,0xE7,0xE7,0xCF,0xF1,
+	0xE7,0xCF,0x9F,0xCF,0xE7,0xF1,0xFF,0xFF,0xFF,0x81,0xFF,
+	0x81,0xFF,0xFF,0xFF,0x8F,0xE7,0xF3,0xF9,0xF3,0xE7,0x8F,
+	0xFF,0xC3,0x99,0xF9,0xF3,0xE7,0xFF,0xE7,0xFF,0xFF,0xFF,
+	0xFF,0x00,0x00,0xFF,0xFF,0xFF,0xE7,0xC3,0x99,0x81,0x99,
+	0x99,0x99,0xFF,0x83,0x99,0x99,0x83,0x99,0x99,0x83,0xFF,
+	0xC3,0x99,0x9F,0x9F,0x9F,0x99,0xC3,0xFF,0x87,0x93,0x99,
+	0x99,0x99,0x93,0x87,0xFF,0x81,0x9F,0x9F,0x87,0x9F,0x9F,
+	0x81,0xFF,0x81,0x9F,0x9F,0x87,0x9F,0x9F,0x9F,0xFF,0xC3,
+	0x99,0x9F,0x91,0x99,0x99,0xC3,0xFF,0x99,0x99,0x99,0x81,
+	0x99,0x99,0x99,0xFF,0xC3,0xE7,0xE7,0xE7,0xE7,0xE7,0xC3,
+	0xFF,0xE1,0xF3,0xF3,0xF3,0xF3,0x93,0xC7,0xFF,0x99,0x93,
+	0x87,0x8F,0x87,0x93,0x99,0xFF,0x9F,0x9F,0x9F,0x9F,0x9F,
+	0x9F,0x81,0xFF,0x9C,0x88,0x80,0x94,0x9C,0x9C,0x9C,0xFF,
+	0x99,0x89,0x81,0x81,0x91,0x99,0x99,0xFF,0xC3,0x99,0x99,
+	0x99,0x99,0x99,0xC3,0xFF,0x83,0x99,0x99,0x83,0x9F,0x9F,
+	0x9F,0xFF,0xC3,0x99,0x99,0x99,0x99,0xC3,0xF1,0xFF,0x83,
+	0x99,0x99,0x83,0x87,0x93,0x99,0xFF,0xC3,0x99,0x9F,0xC3,
+	0xF9,0x99,0xC3,0xFF,0x81,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,
+	0xFF,0x99,0x99,0x99,0x99,0x99,0x99,0xC3,0xFF,0x99,0x99,
+	0x99,0x99,0x99,0xC3,0xE7,0xFF,0x9C,0x9C,0x9C,0x94,0x80,
+	0x88,0x9C,0xFF,0x99,0x99,0xC3,0xE7,0xC3,0x99,0x99,0xFF,
+	0x99,0x99,0x99,0xC3,0xE7,0xE7,0xE7,0xFF,0x81,0xF9,0xF3,
+	0xE7,0xCF,0x9F,0x81,0xFF,0xE7,0xE7,0xE7,0x00,0x00,0xE7,
+	0xE7,0xE7,0x3F,0x3F,0xCF,0xCF,0x3F,0x3F,0xCF,0xCF,0xE7,
+	0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xCC,0xCC,0x33,0x33,
+	0xCC,0xCC,0x33,0x33,0xCC,0x66,0x33,0x99,0xCC,0x66,0x33,
+	0x99,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,
+	0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,
+	0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x3F,0x3F,0x3F,
+	0x3F,0x3F,0x3F,0x3F,0x3F,0x33,0x33,0xCC,0xCC,0x33,0x33,
+	0xCC,0xCC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFF,
+	0xFF,0xFF,0xFF,0x33,0x33,0xCC,0xCC,0x33,0x66,0xCC,0x99,
+	0x33,0x66,0xCC,0x99,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,
+	0xFC,0xE7,0xE7,0xE7,0xE0,0xE0,0xE7,0xE7,0xE7,0xFF,0xFF,
+	0xFF,0xFF,0xF0,0xF0,0xF0,0xF0,0xE7,0xE7,0xE7,0xE0,0xE0,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07,0x07,0xE7,0xE7,0xE7,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0xFF,
+	0xE0,0xE0,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0x00,0x00,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xE7,0xE7,0xE7,0xE7,
+	0xE7,0xE7,0x07,0x07,0xE7,0xE7,0xE7,0x3F,0x3F,0x3F,0x3F,
+	0x3F,0x3F,0x3F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	0x1F,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,0x00,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0xFF,0xFF,
+	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+	0xFE,0xFC,0xF9,0x93,0x87,0x8F,0x9F,0xFF,0xFF,0xFF,0xFF,
+	0xFF,0x0F,0x0F,0x0F,0x0F,0xF0,0xF0,0xF0,0xF0,0xFF,0xFF,
+	0xFF,0xFF,0xE7,0xE7,0xE7,0x07,0x07,0xFF,0xFF,0xFF,0x0F,
+	0x0F,0x0F,0x0F,0xFF,0xFF,0xFF,0xFF,0x0F,0x0F,0x0F,0x0F,
+	0xF0,0xF0,0xF0,0xF0,
+};
diff --git a/MCUME_pico2/pico64/roms.h b/MCUME_pico2/pico64/roms.h
new file mode 100755
index 0000000..5722277
--- /dev/null
+++ b/MCUME_pico2/pico64/roms.h
@@ -0,0 +1,10 @@
+#ifndef Teensy64_roms_h_
+#define Teensy64_roms_h_
+
+#define APPLY_PATCHES 1
+
+extern const unsigned char rom_basic[8192];
+extern const unsigned char rom_kernal[8192];
+extern const unsigned char rom_characters[4096];
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/settings.h b/MCUME_pico2/pico64/settings.h
new file mode 100755
index 0000000..014f245
--- /dev/null
+++ b/MCUME_pico2/pico64/settings.h
@@ -0,0 +1,62 @@
+/*
+  Copyright Frank Bösing, 2017
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#ifndef settings_h_
+#define settings_h_
+
+#ifndef VGA
+#define VGA 			0 	//use 0 for ILI9341 Display
+#endif
+
+#ifndef PS2KEYBOARD
+#define PS2KEYBOARD 	0	//Use 0 for USB-HOST
+#endif
+
+
+//Note: PAL/NTSC are EMULATED - This is not the real videomode!
+#ifndef PAL
+#define PAL           1 //use 0 for NTSC
+#endif
+
+#ifndef FASTBOOT
+#define FASTBOOT      1 //0 to disable fastboot
+#endif
+
+
+#define EXACTTIMINGDURATION 600ul //ms exact timing after IEC-BUS activity
+
+
+
+#endif
diff --git a/MCUME_pico2/pico64/sid.cpp b/MCUME_pico2/pico64/sid.cpp
new file mode 100644
index 0000000..6779dc3
--- /dev/null
+++ b/MCUME_pico2/pico64/sid.cpp
@@ -0,0 +1,49 @@
+/*
+	Arduino SID
+	Copyright (c) 2015 Frank Bösing
+	This library is free software: you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 3 of the License, or
+	(at your option) any later version.
+	This library is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+	You should have received a copy of the GNU General Public License
+	along with this library.  If not, see <http://www.gnu.org/licenses/>.
+
+	Diese Bibliothek ist freie Software: Sie können es unter den Bedingungen
+	der GNU General Public License, wie von der Free Software Foundation,
+	Version 3 der Lizenz oder (nach Ihrer Wahl) jeder neueren
+	veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+	Diese Bibliothek wird in der Hoffnung, dass es nützlich sein wird, aber
+	OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+	Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+	Siehe die GNU General Public License für weitere Details.
+	Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+	Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+ */
+
+#include "reSID/envelope.cc"
+#include "reSID/extfilt.cc"
+#include "reSID/filter.cc"
+#include "reSID/pot.cc"
+#include "reSID/version.cc"
+#include "reSID/voice.cc"
+
+
+#include "reSID/wave6581__ST.cc" 
+#include "reSID/wave6581_P_T.cc"
+#include "reSID/wave6581_PS_.cc"
+#include "reSID/wave6581_PST.cc"
+
+/*
+#include "reSID/wave8580__ST.cc" 
+#include "reSID/wave8580_P_T.cc"
+#include "reSID/wave8580_PS_.cc"
+#include "reSID/wave8580_PST.cc"
+*/
+#include "reSID/wave.cc"
+
+#include "reSID/sid.cc"
diff --git a/MCUME_pico2/pico64/timerutil.cpp b/MCUME_pico2/pico64/timerutil.cpp
new file mode 100755
index 0000000..600fc65
--- /dev/null
+++ b/MCUME_pico2/pico64/timerutil.cpp
@@ -0,0 +1,71 @@
+/*
+Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+#include <stdint.h>
+#include <stdio.h>
+#include "timerutil.h"
+
+//Attention, don't use WFI-instruction - the CPU does not count cycles during sleep
+void enableCycleCounter(void) {
+
+}
+
+extern "C" volatile uint32_t systick_millis_count;
+void mySystick_isr(void) { systick_millis_count++; }
+void myUnused_isr(void) {};
+
+void disableEventResponder(void) {
+}
+
+static float setDACFreq(float freq) {
+
+  return (float)0;
+}
+
+float setAudioSampleFreq(float freq) {
+  int f=0;
+  return f;
+}
+
+void setAudioOff(void) {
+
+}
+
+void setAudioOn(void) {
+
+}
+
+void listInterrupts() {
+
+}
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/timerutil.h b/MCUME_pico2/pico64/timerutil.h
new file mode 100755
index 0000000..a2aefde
--- /dev/null
+++ b/MCUME_pico2/pico64/timerutil.h
@@ -0,0 +1,63 @@
+/*
+Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#ifndef _UTIL_C64H_
+#define _UTIL_C64H_
+
+#include "Teensy64.h"
+
+
+//static inline unsigned get_ccount(void)
+//{
+//        //unsigned r;
+//        //asm volatile ("rsr %0, ccount" : "=r"(r));
+//        return (time_us_32());
+//}
+
+void disableEventResponder(void);
+
+void enableCycleCounter(void);
+inline unsigned fbmicros(void)  __attribute__((always_inline));
+
+//unsigned fbmicros(void) { return (get_ccount() * (1000000.0/F_CPU)); }
+unsigned fbmicros(void) { return (time_us_32()); }
+
+float setAudioSampleFreq(float freq);
+void setAudioOff(void);
+void setAudioOn(void);
+void listInterrupts();
+
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico64/vic.cpp b/MCUME_pico2/pico64/vic.cpp
new file mode 100644
index 0000000..56a0dc6
--- /dev/null
+++ b/MCUME_pico2/pico64/vic.cpp
@@ -0,0 +1,2155 @@
+/*
+  Copyright Frank Bösing, 2017
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+/*
+  TODOs:
+  - Fix Bugs..
+  - FLD  - (OK 08/17) test this more..
+  - Sprite Stretching (requires "MOBcounter")
+  - BA Signal -> CPU
+  - xFLI
+  - ...
+  - DMA Delay (?) - needs partial rewrite (idle - > badline in middle of line. Is the 3.6 fast enough??)
+  - optimize more
+*/
+
+
+#include "Teensy64.h"
+#include "vic.h"
+#include <string.h>
+#include <math.h>
+#include <stdlib.h>
+
+
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#define max(a, b) (((a) > (b)) ? (a) : (b)) 
+
+#define PALETTE(r,g,b) (RGBVAL16(r,g,b))  //(((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3))
+#include "vic_palette.h"
+
+
+
+#define BORDER      	        (240-200)/2
+#define SCREEN_HEIGHT         (200+2*BORDER)
+#define SCREEN_WIDTH          320
+//#define LINE_MEM_WIDTH        320
+#define FIRSTDISPLAYLINE      (  51 - BORDER )
+#define LASTDISPLAYLINE       ( 250 + BORDER )
+#define BORDER_LEFT           (400-320)/2
+#define BORDER_RIGHT          0
+
+typedef uint16_t tpixel;
+
+#define MAXCYCLESSPRITES0_2       3
+#define MAXCYCLESSPRITES3_7       5
+#define MAXCYCLESSPRITES    (MAXCYCLESSPRITES0_2 + MAXCYCLESSPRITES3_7)
+
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+inline __attribute__((always_inline))
+void fastFillLine(tpixel * p, const tpixel * pe, const uint16_t col, uint16_t * spl);
+inline __attribute__((always_inline))
+void fastFillLineNoSprites(tpixel * p, const tpixel * pe, const uint16_t col);
+
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+#define SPRITENUM(data) (1 << ((data >> 8) & 0x07))
+#define CHARSETPTR() cpu.vic.charsetPtr = cpu.vic.charsetPtrBase + cpu.vic.rc;
+#define CYCLES(x) {if (cpu.vic.badline) {cia_clockt(x);} else {cpu_clock(x);} }
+
+#define BADLINE(x) {if (cpu.vic.badline) { \
+      cpu.vic.lineMemChr[x] = cpu.RAM[cpu.vic.videomatrix + vc + x]; \
+	  cpu.vic.lineMemCol[x] = cpu.vic.COLORRAM[vc + x]; \
+	  cia1_clock(1); \
+	  cia2_clock(1); \
+    } else { \
+      cpu_clock(1); \
+    } \
+  };
+
+#define SPRITEORFIXEDCOLOR() \
+  sprite = *spl++; \
+  if (sprite) { \
+    *p++ = cpu.vic.palette[sprite & 0x0f]; \
+  } else { \
+    *p++ = col; \
+  }
+
+
+#if 0
+#define PRINTOVERFLOW   \
+  if (p>pe) { \
+    Serial.print("VIC overflow Mode "); \
+    Serial.println(mode); \
+  }
+
+#define PRINTOVERFLOWS  \
+  if (p>pe) { \
+    Serial.print("VIC overflow (Sprite) Mode ");  \
+    Serial.println(mode); \
+  }
+#else
+#define PRINTOVERFLOW
+#define PRINTOVERFLOWS
+#endif
+
+/*****************************************************************************************************/
+void mode0 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  // Standard-Textmodus(ECM/BMM/MCM=0/0/0)
+  /*
+    Standard-Textmodus (ECM / BMM / MCM = 0/0/0)
+    In diesem Modus (wie in allen Textmodi) liest der VIC aus der videomatrix 8-Bit-Zeichenzeiger,
+    die die Adresse der Punktmatrix des Zeichens im Zeichengenerator angibt. Damit ist ein Zeichensatz
+    von 256 Zeichen verfügbar, die jeweils aus 8×8 Pixeln bestehen, die in 8 aufeinanderfolgenden Bytes
+    im Zeichengenerator abgelegt sind. Mit den Bits VM10-13 und CB11-13 aus Register $d018 lassen sich
+    videomatrix und Zeichengenerator im Speicher verschieben. Im Standard-Textmodus entspricht jedes Bit
+    im Zeichengenerator direkt einem Pixel auf dem Bildschirm. Die Vordergrundfarbe ist für jedes Zeichen
+    im Farbnibble aus der videomatrix angegeben, die Hintergrundfarbe wird global durch Register $d021 festgelegt.
+
+    +----+----+----+----+----+----+----+----+
+    |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+    +----+----+----+----+----+----+----+----+
+    |         8 Pixel (1 Bit/Pixel)         |
+    |                                       |
+    | "0": Hintergrundfarbe 0 ($d021)       |
+    | "1": Farbe aus Bits 8-11 der c-Daten  |
+    +---------------------------------------+
+
+  */
+
+  uint8_t chr, pixel;
+  uint16_t fgcol;
+  uint16_t bgcol;
+  uint16_t  x = 0;
+
+  CHARSETPTR();
+
+  if (cpu.vic.lineHasSprites) {
+
+    do {
+
+      BADLINE(x);
+
+      chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+      fgcol = cpu.vic.lineMemCol[x];
+	  x++;
+      unsigned m = min(8, pe - p);
+      for (unsigned i = 0; i < m; i++) {
+        int sprite = *spl++;
+
+        if (sprite) {     // Sprite: Ja
+		  int spritenum = SPRITENUM(sprite);
+          int spritepixel = sprite & 0x0f;
+
+          if (sprite & 0x4000) {   // Sprite: Hinter Text  MDP = 1
+            if (chr & 0x80) {
+              cpu.vic.fgcollision |= spritenum;
+              pixel = fgcol;
+            } else {
+              pixel = spritepixel;
+            }
+          } else {            // Sprite: Vor Text //MDP = 0
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum;
+            pixel = spritepixel;
+          }
+        } else {            // Kein Sprite
+          pixel = (chr & 0x80) ? fgcol : cpu.vic.B0C;
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+        chr = chr << 1;
+
+      }
+    } while (p < pe);
+    PRINTOVERFLOWS
+  } else { //Keine Sprites
+
+    while (p < pe - 8) {
+
+      BADLINE(x)
+
+      chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+      fgcol = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+	  bgcol = cpu.vic.colors[1];
+      x++;
+
+      *p++ = (chr & 0x80) ? fgcol : bgcol;
+      *p++ = (chr & 0x40) ? fgcol : bgcol;
+      *p++ = (chr & 0x20) ? fgcol : bgcol;
+      *p++ = (chr & 0x10) ? fgcol : bgcol;
+      *p++ = (chr & 0x08) ? fgcol : bgcol;
+      *p++ = (chr & 0x04) ? fgcol : bgcol;
+      *p++ = (chr & 0x02) ? fgcol : bgcol;
+      *p++ = (chr & 0x01) ? fgcol : bgcol;
+
+    };
+
+    while (p < pe) {
+
+      BADLINE(x)
+
+      chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+      fgcol = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+	  bgcol = cpu.vic.colors[1];
+      x++;
+
+      *p++ = (chr & 0x80) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x40) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x20) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x10) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x08) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x04) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x02) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x01) ? fgcol : bgcol;
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+};
+
+/*****************************************************************************************************/
+void mode1 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+    Multicolor-Textmodus (ECM/BMM/MCM=0/0/1)
+    Dieser Modus ermöglicht es, auf Kosten der horizontalen Auflösung vierfarbige Zeichen darzustellen.
+    Ist Bit 11 der c-Daten Null, wird das Zeichen wie im Standard-Textmodus dargestellt, wobei aber nur die
+    Farben 0-7 für den Vordergrund zur Verfügung stehen. Ist Bit 11 gesetzt, bilden jeweils zwei horizontal
+    benachbarte Bits der Punktmatrix ein Pixel. Dadurch ist die Auflösung des Zeichens auf 4×8 reduziert
+    (die Pixel sind doppelt so breit, die Gesamtbreite der Zeichen ändert sich also nicht).
+    Interessant ist, daß nicht nur die Bitkombination „00�, sondern auch „01� für die Spritepriorität
+    und -kollisionserkennung zum "Hintergrund" gezählt wird.
+
+    +----+----+----+----+----+----+----+----+
+    |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+    +----+----+----+----+----+----+----+----+
+    |         8 Pixel (1 Bit/Pixel)         |
+    |                                       | MC-Flag = 0
+    | "0": Hintergrundfarbe 0 ($d021)       |
+    | "1": Farbe aus Bits 8-10 der c-Daten  |
+    +---------------------------------------+
+    |         4 Pixel (2 Bit/Pixel)         |
+    |                                       |
+    | "00": Hintergrundfarbe 0 ($d021)      | MC-Flag = 1
+    | "01": Hintergrundfarbe 1 ($d022)      |
+    | "10": Hintergrundfarbe 2 ($d023)      |
+    | "11": Farbe aus Bits 8-10 der c-Daten |
+    +---------------------------------------+
+
+  */
+
+  // POKE 53270,PEEK(53270) OR 16
+  // poke 53270,peek(53270) or 16
+
+  uint16_t bgcol, fgcol, pixel;
+  uint16_t colors[4];
+  uint8_t chr;
+  uint8_t x = 0;
+
+  CHARSETPTR();
+
+  if (cpu.vic.lineHasSprites) {
+
+    colors[0] = cpu.vic.B0C;
+
+    do {
+
+	  if (cpu.vic.idle) {
+		cpu_clock(1);
+		fgcol = colors[1] = colors[2] = colors[3] = 0;
+		chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+        fgcol = cpu.vic.lineMemCol[x];
+	    colors[1] = cpu.vic.R[0x22];
+        colors[2] = cpu.vic.R[0x23];
+        colors[3] = fgcol & 0x07;
+		chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+	  }
+
+      x++;
+
+      if ((fgcol & 0x08) == 0) { //Zeichen ist HIRES
+
+        unsigned m = min(8, pe - p);
+        for (unsigned i = 0; i < m; i++) {
+
+          int sprite = *spl++;
+
+          if (sprite) {     // Sprite: Ja
+
+            /*
+              Sprite-Prioritäten (Anzeige)
+              MDP = 1: Grafikhintergrund, Sprite, Vordergrund
+              MDP = 0: Grafikhintergrund, Vordergrund, Sprite
+
+              Kollision:
+              Eine Kollision zwischen Sprites und anderen Grafikdaten wird erkannt,
+              sobald beim Bildaufbau ein nicht transparentes Spritepixel und ein Vordergrundpixel ausgegeben wird.
+
+            */
+            int spritenum = SPRITENUM(sprite);
+            pixel = sprite & 0x0f; //Hintergrundgrafik
+            if (sprite & 0x4000) {   // MDP = 1
+              if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = colors[3];
+              }
+            } else {            // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+
+          } else {            // Kein Sprite
+            pixel = (chr >> 7) ? colors[3] : colors[0];
+          }
+
+          *p++ = cpu.vic.palette[pixel];
+
+          chr = chr << 1;
+        }
+
+      } else {//Zeichen ist MULTICOLOR
+
+        for (unsigned i = 0; i < 4; i++) {
+          if (p >= pe) break;
+          int c = (chr >> 6) & 0x03;
+          chr = chr << 2;
+
+          int sprite = *spl++;
+
+          if (sprite) {    // Sprite: Ja
+            int spritenum = SPRITENUM(sprite);
+			pixel = sprite & 0x0f; //Hintergrundgrafik
+            if (sprite & 0x4000) {  // MDP = 1
+
+              if (chr & 0x80) {  //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = colors[c];
+              }
+
+            } else {          // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+
+          } else { // Kein Sprite
+            pixel = colors[c];
+
+          }
+          *p++ = cpu.vic.palette[pixel];
+          if (p >= pe) break;
+
+          sprite = *spl++;
+
+          //Das gleiche nochmal für das nächste Pixel
+          if (sprite) {    // Sprite: Ja
+            int spritenum = SPRITENUM(sprite);
+			pixel =  sprite & 0x0f; //Hintergrundgrafik
+            if (sprite & 0x4000) {  // MDP = 1
+
+              if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = colors[c];
+              }
+            } else {          // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+          } else { // Kein Sprite
+            pixel = colors[c];
+          }
+          *p++ = cpu.vic.palette[pixel];
+
+        }
+
+      }
+
+    } while (p < pe);
+    PRINTOVERFLOWS
+  } else { //Keine Sprites
+
+    while (p < pe - 8) {
+
+	  int c;
+
+	  bgcol = cpu.vic.colors[1];
+	  colors[0] = bgcol;
+
+	  if (cpu.vic.idle) {
+		cpu_clock(1);
+		c = colors[1] = colors[2] = colors[3] = 0;
+		chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+
+	    colors[1] = cpu.vic.colors[2];
+  	    colors[2] = cpu.vic.colors[3];
+
+        chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+        c = cpu.vic.lineMemCol[x];
+	  }
+
+      x++;
+
+      if ((c & 0x08) == 0) { //Zeichen ist HIRES
+        fgcol = cpu.vic.palette[c & 0x07];
+        *p++ = (chr & 0x80) ? fgcol : bgcol;
+        *p++ = (chr & 0x40) ? fgcol : bgcol;
+        *p++ = (chr & 0x20) ? fgcol : bgcol;
+        *p++ = (chr & 0x10) ? fgcol : bgcol;
+        *p++ = (chr & 0x08) ? fgcol : bgcol;
+        *p++ = (chr & 0x04) ? fgcol : bgcol;
+        *p++ = (chr & 0x02) ? fgcol : bgcol;
+        *p++ = (chr & 0x01) ? fgcol : bgcol;
+      } else {//Zeichen ist MULTICOLOR
+
+        colors[3] = cpu.vic.palette[c & 0x07];
+        pixel = colors[(chr >> 6) & 0x03]; *p++ = pixel; *p++ = pixel;
+        pixel = colors[(chr >> 4) & 0x03]; *p++ = pixel; *p++ = pixel;
+        pixel = colors[(chr >> 2) & 0x03]; *p++ = pixel; *p++ = pixel;
+        pixel = colors[(chr     ) & 0x03]; *p++ = pixel; *p++ = pixel;
+      }
+
+    };
+
+    while (p < pe) {
+
+	  int c;
+
+	  bgcol = cpu.vic.colors[1];
+	  colors[0] = bgcol;
+
+	  if (cpu.vic.idle) {
+		cpu_clock(1);
+		c = colors[1] = colors[2] = colors[3] = 0;
+		chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+
+	    colors[1] = cpu.vic.colors[2];
+  	    colors[2] = cpu.vic.colors[3];
+
+        chr = cpu.vic.charsetPtr[cpu.vic.lineMemChr[x] * 8];
+        c = cpu.vic.lineMemCol[x];
+	  }
+
+      x++;
+
+      if ((c & 0x08) == 0) { //Zeichen ist HIRES
+        fgcol = cpu.vic.palette[c & 0x07];
+        *p++ = (chr & 0x80) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x40) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x20) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x10) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x08) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x04) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x02) ? fgcol : bgcol; if (p >= pe) break;
+        *p++ = (chr & 0x01) ? fgcol : bgcol;
+      } else {//Zeichen ist MULTICOLOR
+
+        colors[3] = cpu.vic.palette[c & 0x07];
+        pixel = colors[(chr >> 6) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+        pixel = colors[(chr >> 4) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+        pixel = colors[(chr >> 2) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+        pixel = colors[(chr     ) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel;
+      }
+
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+
+/*****************************************************************************************************/
+void mode2 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+     Standard-Bitmap-Modus (ECM / BMM / MCM = 0/1/0) ("HIRES")
+     In diesem Modus (wie in allen Bitmap-Modi) liest der VIC die Grafikdaten aus einer 320×200-Bitmap,
+     in der jedes Bit direkt einem Punkt auf dem Bildschirm entspricht. Die Daten aus der videomatrix
+     werden für die Farbinformation benutzt. Da die videomatrix weiterhin nur eine 40×25-Matrix ist,
+     können die Farben nur für Blöcke von 8×8 Pixeln individuell bestimmt werden (also eine Art YC-8:1-Format).
+     Da die Entwickler des VIC-II den Bitmap-Modus mit sowenig zusätzlichem Schaltungsaufwand wie möglich realisieren wollten
+     (der VIC-I hatte noch keinen Bitmap-Modus), ist die Bitmap etwas ungewöhnlich im Speicher abgelegt:
+     Im Gegensatz zu modernen Videochips, die die Bitmap linear aus dem Speicher lesen, bilden beim VIC jeweils 8 aufeinanderfolgende Bytes einen 8×8-Pixelblock
+     auf dem Bildschirm. Mit den Bits VM10-13 und CB13 aus Register $d018 lassen sich videomatrix und Bitmap im Speicher verschieben.
+     Im Standard-Bitmap-Modus entspricht jedes Bit in der Bitmap direkt einem Pixel auf dem Bildschirm.
+     Für jeden 8×8-Block können Vorder- und Hintergrundfarbe beliebig eingestellt werden.
+
+     +----+----+----+----+----+----+----+----+
+     |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+     +----+----+----+----+----+----+----+----+
+     |         8 Pixel (1 Bit/Pixel)         |
+     |                                       |
+     | "0": Farbe aus Bits 0-3 der c-Daten   |
+     | "1": Farbe aus Bits 4-7 der c-Daten   |
+     +---------------------------------------+
+
+
+     http://www.devili.iki.fi/Computers/Commodore/C64/Programmers_Reference/Chapter_3/page_127.html
+  */
+
+  uint8_t chr;
+  uint16_t fgcol, pixel;
+  uint16_t bgcol;
+  uint8_t x = 0;
+  uint8_t * bP = cpu.vic.bitmapPtr + vc * 8 + cpu.vic.rc;
+
+  if (cpu.vic.lineHasSprites) {
+    do {
+
+      BADLINE(x);
+
+      uint8_t t = cpu.vic.lineMemChr[x];
+      fgcol = t >> 4;
+      bgcol = t & 0x0f;
+      chr = bP[x * 8];
+
+      x++;
+
+      unsigned m = min(8, pe - p);
+      for (unsigned i = 0; i < m; i++) {
+
+        int sprite = *spl++;
+
+        chr = chr << 1;
+        if (sprite) {     // Sprite: Ja
+          /*
+             Sprite-Prioritäten (Anzeige)
+             MDP = 1: Grafikhintergrund, Sprite, Vordergrund
+             MDP = 0: Grafikhintergung, Vordergrund, Sprite
+
+             Kollision:
+             Eine Kollision zwischen Sprites und anderen Grafikdaten wird erkannt,
+             sobald beim Bildaufbau ein nicht transparentes Spritepixel und ein Vordergrundpixel ausgegeben wird.
+
+          */
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f; //Hintergrundgrafik
+          if (sprite & 0x4000) {   // MDP = 1
+            if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = fgcol;
+            }
+          } else {            // MDP = 0
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+          }
+
+        } else {            // Kein Sprite
+          pixel = (chr & 0x80) ? fgcol :cpu.vic.B0C;
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+
+      }
+    } while (p < pe);
+    PRINTOVERFLOWS
+  } else { //Keine Sprites
+
+    while (p < pe - 8) {
+      //color-ram not used!
+      BADLINE(x);
+
+      uint8_t t = cpu.vic.lineMemChr[x];
+      fgcol = cpu.vic.palette[t >> 4];
+      bgcol = cpu.vic.palette[t & 0x0f];
+      chr = bP[x * 8];
+      x++;
+
+      *p++ = (chr & 0x80) ? fgcol : bgcol;
+      *p++ = (chr & 0x40) ? fgcol : bgcol;
+      *p++ = (chr & 0x20) ? fgcol : bgcol;
+      *p++ = (chr & 0x10) ? fgcol : bgcol;
+      *p++ = (chr & 0x08) ? fgcol : bgcol;
+      *p++ = (chr & 0x04) ? fgcol : bgcol;
+      *p++ = (chr & 0x02) ? fgcol : bgcol;
+      *p++ = (chr & 0x01) ? fgcol : bgcol;
+    };
+    while (p < pe) {
+      //color-ram not used!
+      BADLINE(x);
+
+      uint8_t t = cpu.vic.lineMemChr[x];
+      fgcol = cpu.vic.palette[t >> 4];
+      bgcol = cpu.vic.palette[t & 0x0f];
+      chr = bP[x * 8];
+
+      x++;
+
+      *p++ = (chr & 0x80) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x40) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x20) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x10) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x08) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x04) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x02) ? fgcol : bgcol; if (p >= pe) break;
+      *p++ = (chr & 0x01) ? fgcol : bgcol;
+
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+/*****************************************************************************************************/
+void mode3 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+    Multicolor-Bitmap-Modus (ECM/BMM/MCM=0/1/1)
+
+    Ähnlich wie beim Multicolor-Textmodus bilden auch in diesem Modus jeweils
+    zwei benachbarte Bits ein (doppelt so breites) Pixel. Die Auflösung
+    reduziert sich damit auf 160×200 Pixel.
+
+    Genau wie beim Multicolor-Textmodus wird die Bitkombination "01" für die
+    Spritepriorität und -kollisionserkennung zum "Hintergrund" gezählt.
+
+    +----+----+----+----+----+----+----+----+
+    |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+    +----+----+----+----+----+----+----+----+
+    |         4 Pixel (2 Bit/Pixel)         |
+    |                                       |
+    | "00": Hintergrundfarbe 0 ($d021)      |
+    | "01": Farbe aus Bits 4-7 der c-Daten  |
+    | "10": Farbe aus Bits 0-3 der c-Daten  |
+    | "11": Farbe aus Bits 8-11 der c-Daten |
+    +---------------------------------------+
+
+    POKE 53265,PEEK(53625)OR 32: POKE 53270,PEEK(53270)OR 16
+  */
+  uint8_t * bP = cpu.vic.bitmapPtr + vc * 8 + cpu.vic.rc;
+  uint16_t colors[4];
+  uint16_t pixel;
+  uint8_t chr, x;
+
+  x = 0;
+
+  if (cpu.vic.lineHasSprites) {
+    colors[0] = cpu.vic.B0C;
+    do {
+
+	  if (cpu.vic.idle) {
+	    cpu_clock(1);
+	    colors[1] = colors[2] = colors[3] = 0;
+	    chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+        uint8_t t = cpu.vic.lineMemChr[x];
+        colors[1] = t >> 4;//10
+        colors[2] = t & 0x0f; //01
+        colors[3] = cpu.vic.lineMemCol[x];
+  	    chr = bP[x * 8];
+  	  };
+
+      x++;
+
+      for (unsigned i = 0; i < 4; i++) {
+        if (p >= pe) break;
+        uint32_t c = (chr >> 6) & 0x03;
+        chr = chr << 2;
+
+        int sprite = *spl++;
+
+        if (sprite) {    // Sprite: Ja
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f; //Hintergrundgrafik
+          if (sprite & 0x4000) {  // MDP = 1
+            if (c & 0x02) {  //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = colors[c];
+            }
+          } else {          // MDP = 0
+            if (c & 0x02) cpu.vic.fgcollision |= spritenum; //Vordergundpixel ist gesetzt
+          }
+        } else { // Kein Sprite
+          pixel = colors[c];
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+        if (p >= pe) break;
+
+        sprite = *spl++;
+
+        if (sprite) {    // Sprite: Ja
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f; //Hintergrundgrafik
+          if (sprite & 0x4000) {  // MDP = 1
+
+            if (c & 0x02) {  //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = colors[c];
+            }
+          } else {          // MDP = 0
+            if (c & 0x02) cpu.vic.fgcollision |= spritenum; //Vordergundpixel ist gesetzt
+          }
+        } else { // Kein Sprite
+          pixel = colors[c];
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+
+      }
+
+    } while (p < pe);
+    PRINTOVERFLOWS
+
+  } else { //Keine Sprites
+
+    while (p < pe - 8) {
+
+	  colors[0] = cpu.vic.colors[1];
+
+	  if (cpu.vic.idle) {
+	    cpu_clock(1);
+	    colors[1] = colors[2] = colors[3] = 0;
+	    chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+
+        uint8_t t = cpu.vic.lineMemChr[x];
+        colors[1] = cpu.vic.palette[t >> 4];//10
+        colors[2] = cpu.vic.palette[t & 0x0f]; //01
+        colors[3] = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+        chr = bP[x * 8];
+	  }
+
+      x++;
+      pixel = colors[(chr >> 6) & 0x03]; *p++ = pixel; *p++ = pixel;
+      pixel = colors[(chr >> 4) & 0x03]; *p++ = pixel; *p++ = pixel;
+      pixel = colors[(chr >> 2) & 0x03]; *p++ = pixel; *p++ = pixel;
+      pixel = colors[chr        & 0x03]; *p++ = pixel; *p++ = pixel;
+
+    };
+    while (p < pe) {
+
+	  colors[0] = cpu.vic.colors[1];
+
+	  if (cpu.vic.idle) {
+	    cpu_clock(1);
+	    colors[1] = colors[2] = colors[3] = 0;
+	    chr = cpu.RAM[cpu.vic.bank + 0x3fff];
+	  } else {
+        BADLINE(x);
+
+        uint8_t t = cpu.vic.lineMemChr[x];
+        colors[1] = cpu.vic.palette[t >> 4];//10
+        colors[2] = cpu.vic.palette[t & 0x0f]; //01
+        colors[3] = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+        chr = bP[x * 8];
+	  }
+
+      x++;
+      pixel = colors[(chr >> 6) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+      pixel = colors[(chr >> 4) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+      pixel = colors[(chr >> 2) & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel; if (p >= pe) break;
+      pixel = colors[chr        & 0x03]; *p++ = pixel; if (p >= pe) break; *p++ = pixel;
+
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+/*****************************************************************************************************/
+void mode4 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  //ECM-Textmodus (ECM/BMM/MCM=1/0/0)
+  /*
+    Dieser Textmodus entspricht dem Standard-Textmodus, erlaubt es aber, für
+    jedes einzelne Zeichen eine von vier Hintergrundfarben auszuwählen. Die
+    Auswahl geschieht über die oberen beiden Bits des Zeichenzeigers. Dadurch
+    reduziert sich der Zeichenvorrat allerdings von 256 auf 64 Zeichen.
+
+    +----+----+----+----+----+----+----+----+
+    |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+    +----+----+----+----+----+----+----+----+
+    |         8 Pixel (1 Bit/Pixel)         |
+    |                                       |
+    | "0": Je nach Bits 6/7 der c-Daten     |
+    |      00: Hintergrundfarbe 0 ($d021)   |
+    |      01: Hintergrundfarbe 1 ($d022)   |
+    |      10: Hintergrundfarbe 2 ($d023)   |
+    |      11: Hintergrundfarbe 3 ($d024)   |
+    | "1": Farbe aus Bits 8-11 der c-Daten  |
+    +---------------------------------------+
+  */
+  // https://www.c64-wiki.de/wiki/Hintergrundfarbe
+  // POKE 53265, PEEK(53265) OR 64:REM CURSOR BLINKT ROT abc
+
+  uint8_t chr, pixel;
+  uint16_t fgcol;
+  uint16_t bgcol;
+  uint8_t x = 0;
+
+  CHARSETPTR();
+  if (cpu.vic.lineHasSprites) {
+    do {
+
+      BADLINE(x);
+
+      uint32_t td = cpu.vic.lineMemChr[x];
+      bgcol = cpu.vic.R[0x21 + ((td >> 6) & 0x03)];
+      chr = cpu.vic.charsetPtr[(td & 0x3f) * 8];
+      fgcol = cpu.vic.lineMemCol[x];
+
+      x++;
+
+      unsigned m = min(8, pe - p);
+      for (unsigned i = 0; i < m; i++) {
+
+        int sprite = *spl++;
+
+        if (sprite) {     // Sprite: Ja
+          int spritenum = SPRITENUM(sprite);
+          if (sprite & 0x4000) {   // Sprite: Hinter Text
+            if (chr & 0x80) {
+              cpu.vic.fgcollision |= spritenum;
+              pixel = fgcol;
+            } else pixel = bgcol;
+          } else {              // Sprite: Vor Text
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum;
+            pixel = sprite & 0x0f;
+          }
+        } else {                // Kein Sprite
+          pixel = (chr & 0x80) ? fgcol : bgcol;
+        }
+
+        chr = chr << 1;
+        *p++ = cpu.vic.palette[pixel];
+      }
+    } while (p < pe);
+    PRINTOVERFLOWS
+  }
+  else //Keine Sprites
+    while (p < pe - 8) {
+
+      BADLINE(x);
+
+      uint32_t td = cpu.vic.lineMemChr[x];
+      bgcol = cpu.vic.palette[cpu.vic.R[0x21 + ((td >> 6) & 0x03)]];
+      chr = cpu.vic.charsetPtr[(td & 0x3f) * 8];
+      fgcol = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+      x++;
+
+      *p++ = (chr & 0x80) ? fgcol : bgcol;
+      *p++ = (chr & 0x40) ? fgcol : bgcol;
+      *p++ = (chr & 0x20) ? fgcol : bgcol;
+      *p++ = (chr & 0x10) ? fgcol : bgcol;
+      *p++ = (chr & 0x08) ? fgcol : bgcol;
+      *p++ = (chr & 0x04) ? fgcol : bgcol;
+      *p++ = (chr & 0x02) ? fgcol : bgcol;
+      *p++ = (chr & 0x01) ? fgcol : bgcol;
+
+    };
+  while (p < pe) {
+
+    BADLINE(x);
+
+    uint32_t td = cpu.vic.lineMemChr[x];
+    bgcol = cpu.vic.palette[cpu.vic.R[0x21 + ((td >> 6) & 0x03)]];
+    chr = cpu.vic.charsetPtr[(td & 0x3f) * 8];
+    fgcol = cpu.vic.palette[cpu.vic.lineMemCol[x]];
+
+    x++;
+
+    *p++ = (chr & 0x80) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x40) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x20) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x10) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x08) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x04) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x02) ? fgcol : bgcol; if (p >= pe) break;
+    *p++ = (chr & 0x01) ? fgcol : bgcol;
+
+  };
+  PRINTOVERFLOW
+  while (x<40) {BADLINE(x); x++;}
+}
+
+/*****************************************************************************************************/
+/* Ungültige Modi ************************************************************************************/
+/*****************************************************************************************************/
+
+void mode5 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+    Ungültiger Textmodus (ECM/BMM/MCM=1/0/1)
+
+    Das gleichzeitige Setzen der ECM- und MCM-Bits wählt keinen der
+    "offiziellen" Grafikmodi des VIC, sondern erzeugt nur schwarze Pixel.
+    Nichtsdestotrotz erzeugt der Grafikdatensequenzer auch in diesem Modus
+    intern gültige Grafikdaten, die die Spritekollisionserkennung triggern
+    können. Über den Umweg der Spritekollisionen kann man die erzeugten Daten
+    auch auslesen (sehen kann man nichts, das Bild ist schwarz). Man kann so
+    allerdings nur Vordergrund- und Hintergrundpixel unterscheiden, die
+    Farbinformation läßt sich aus den Spritekollisionen nicht gewinnen.
+
+    Die erzeugte Grafik entspricht der des Multicolor-Textmodus, allerdings ist
+    der Zeichenvorrat genau wie im ECM-Modus auf 64 Zeichen eingeschränkt.
+  */
+  CHARSETPTR();
+
+  uint8_t chr, pixel;
+  uint16_t fgcol;
+  uint8_t x = 0;
+
+  if (cpu.vic.lineHasSprites) {
+
+    do {
+
+      BADLINE(x);
+
+      chr = cpu.vic.charsetPtr[(cpu.vic.lineMemChr[x] & 0x3F) * 8];
+      fgcol = cpu.vic.lineMemCol[x];
+
+      x++;
+
+      if ((fgcol & 0x08) == 0) { //Zeichen ist HIRES
+
+        unsigned m = min(8, pe - p);
+        for (unsigned i = 0; i < m; i++) {
+
+          int sprite = *spl;
+		  *spl++ = 0;
+
+          if (sprite) {     // Sprite: Ja
+
+            /*
+              Sprite-Prioritäten (Anzeige)
+              MDP = 1: Grafikhintergrund, Sprite, Vordergrund
+              MDP = 0: Grafikhintergrund, Vordergrund, Sprite
+
+              Kollision:
+              Eine Kollision zwischen Sprites und anderen Grafikdaten wird erkannt,
+              sobald beim Bildaufbau ein nicht transparentes Spritepixel und ein Vordergrundpixel ausgegeben wird.
+
+            */
+            int spritenum = SPRITENUM(sprite);
+            pixel = sprite & 0x0f; //Hintergrundgrafik
+
+            if (sprite & 0x4000) {   // MDP = 1
+              if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = 0;
+              }
+            } else {            // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+
+          } else {            // Kein Sprite
+            pixel = 0;
+          }
+
+          *p++ = cpu.vic.palette[pixel];
+
+          chr = chr << 1;
+        }
+
+      } else {//Zeichen ist MULTICOLOR
+
+        for (unsigned i = 0; i < 4; i++) {
+          if (p >= pe) break;
+
+          chr = chr << 2;
+
+          int sprite = *spl;
+		  *spl++ = 0;
+
+          if (sprite) {    // Sprite: Ja
+            int spritenum = SPRITENUM(sprite);
+            pixel = sprite & 0x0f; //Hintergrundgrafik
+            if (sprite & 0x4000) {  // MDP = 1
+
+              if (chr & 0x80) {  //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = 0;
+              }
+            } else {          // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+
+          } else { // Kein Sprite
+            pixel = 0;
+
+          }
+          *p++ = cpu.vic.palette[pixel];
+          if (p >= pe) break;
+
+          sprite = *spl;
+		  *spl++ = 0;
+          //Das gleiche nochmal für das nächste Pixel
+          if (sprite) {    // Sprite: Ja
+            int spritenum = SPRITENUM(sprite);
+            pixel = sprite & 0x0f; //Hintergrundgrafik
+            if (sprite & 0x4000) {  // MDP = 1
+              if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+                cpu.vic.fgcollision |= spritenum;
+                pixel = 0;
+              }
+            } else {          // MDP = 0
+              if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+            }
+          } else { // Kein Sprite
+            pixel = 0;
+          }
+          *p++ = cpu.vic.palette[pixel];
+
+        }
+
+      }
+
+    } while (p < pe);
+    PRINTOVERFLOWS
+
+  } else { //Keine Sprites
+    //Farbe immer schwarz
+    const uint16_t bgcol = palette[0];
+    while (p < pe - 8) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+
+    };
+    while (p < pe) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol;
+
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+/*****************************************************************************************************/
+void mode6 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+    Ungültiger Bitmap-Modus 1 (ECM/BMM/MCM=1/1/0)
+
+    Dieser Modus erzeugt nur ebenfalls nur ein schwarzes Bild, die Pixel lassen
+    sich allerdings auch hier mit dem Spritekollisionstrick auslesen.
+
+    Der Aufbau der Grafik ist im Prinzip wie im Standard-Bitmap-Modus, aber die
+    Bits 9 und 10 der g-Adressen sind wegen dem gesetzten ECM-Bit immer Null,
+    entsprechend besteht auch die Grafik - grob gesagt - aus vier
+    "Abschnitten", die jeweils viermal wiederholt dargestellt werden.
+
+  */
+
+  uint8_t chr, pixel;
+  uint8_t x = 0;
+  uint8_t * bP = cpu.vic.bitmapPtr + vc * 8 + cpu.vic.rc;
+
+  if (cpu.vic.lineHasSprites) {
+
+    do {
+
+      BADLINE(x);
+
+      chr = bP[x * 8];
+
+      x++;
+
+      unsigned m = min(8, pe - p);
+      for (unsigned i = 0; i < m; i++) {
+
+        int sprite = *spl;
+        *spl++ = 0;
+
+        chr = chr << 1;
+        if (sprite) {     // Sprite: Ja
+          /*
+             Sprite-Prioritäten (Anzeige)
+             MDP = 1: Grafikhintergrund, Sprite, Vordergrund
+             MDP = 0: Grafikhintergung, Vordergrund, Sprite
+
+             Kollision:
+             Eine Kollision zwischen Sprites und anderen Grafikdaten wird erkannt,
+             sobald beim Bildaufbau ein nicht transparentes Spritepixel und ein Vordergrundpixel ausgegeben wird.
+
+          */
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f; //Hintergrundgrafik
+          if (sprite & 0x4000) {   // MDP = 1
+            if (chr & 0x80) { //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = 0;
+            }
+          } else {            // MDP = 0
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergrundpixel ist gesetzt
+          }
+
+        } else {            // Kein Sprite
+          pixel = 0;
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+
+      }
+
+    } while (p < pe);
+    PRINTOVERFLOWS
+
+  } else { //Keine Sprites
+    //Farbe immer schwarz
+    const uint16_t bgcol = palette[0];
+    while (p < pe - 8) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+
+    };
+    while (p < pe) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol;
+
+    };
+    PRINTOVERFLOW
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+/*****************************************************************************************************/
+void mode7 (tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc) {
+  /*
+    Ungültiger Bitmap-Modus 2 (ECM/BMM/MCM=1/1/1)
+
+    Der letzte ungültige Modus liefert auch ein schwarzes Bild, das sich jedoch
+    genauso mit Hilfe der Sprite-Grafik-Kollisionen "abtasten" läßt.
+
+    Der Aufbau der Grafik ist im Prinzip wie im Multicolor-Bitmap-Modus, aber
+    die Bits 9 und 10 der g-Adressen sind wegen dem gesetzten ECM-Bit immer
+    Null, was sich in der Darstellung genauso wie beim ersten ungültigen
+    Bitmap-Modus wiederspiegelt. Die Bitkombination "01" wird wie gewohnt zum
+    Hintergrund gezählt.
+
+  */
+
+  uint8_t chr;
+  uint8_t x = 0;
+  uint16_t pixel;
+  uint8_t * bP = cpu.vic.bitmapPtr + vc * 8 + cpu.vic.rc;
+
+  if (cpu.vic.lineHasSprites) {
+
+    do {
+
+      BADLINE(x);
+
+      chr = bP[x * 8];
+      x++;
+
+      for (unsigned i = 0; i < 4; i++) {
+        if (p >= pe) break;
+
+        chr = chr << 2;
+
+        int sprite = *spl;
+		*spl++ = 0;
+
+        if (sprite) {    // Sprite: Ja
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f;//Hintergrundgrafik
+          if (sprite & 0x4000) {  // MDP = 1
+
+            if (chr & 0x80) {  //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = 0;
+            }
+          } else {          // MDP = 0
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergundpixel ist gesetzt
+          }
+        } else { // Kein Sprite
+          pixel = 0;
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+        if (p >= pe) break;
+
+        sprite = *spl;
+        *spl++ = 0;
+
+        if (sprite) {    // Sprite: Ja
+          int spritenum = SPRITENUM(sprite);
+          pixel = sprite & 0x0f;//Hintergrundgrafik
+          if (sprite & 0x4000) {  // MDP = 1
+
+            if (chr & 0x80) {  //Vordergrundpixel ist gesetzt
+              cpu.vic.fgcollision |= spritenum;
+              pixel = 0;
+            }
+          } else {          // MDP = 0
+            if (chr & 0x80) cpu.vic.fgcollision |= spritenum; //Vordergundpixel ist gesetzt
+          }
+        } else { // Kein Sprite
+          pixel = 0;
+        }
+
+        *p++ = cpu.vic.palette[pixel];
+
+      }
+
+    } while (p < pe);
+    PRINTOVERFLOWS
+
+  } else { //Keine Sprites
+
+    const uint16_t bgcol = palette[0];
+    while (p < pe - 8) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+      *p++ = bgcol; *p++ = bgcol;
+
+    };
+    while (p < pe) {
+
+      BADLINE(x);
+      x++;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol; if (p >= pe) break;
+      *p++ = bgcol; if (p >= pe) break; *p++ = bgcol;
+
+    };
+    PRINTOVERFLOW
+
+  }
+  while (x<40) {BADLINE(x); x++;}
+}
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+typedef void (*modes_t)( tpixel *p, const tpixel *pe, uint16_t *spl, const uint16_t vc ); //Funktionspointer
+const modes_t modes[8] = {mode0, mode1, mode2, mode3, mode4, mode5, mode6, mode7};
+
+
+static tpixel linebuffer[SCREEN_WIDTH*2];
+
+void vic_do(void) {
+
+  uint16_t vc;
+  uint16_t xscroll;
+  tpixel *pe;
+  tpixel *p;
+  uint16_t *spl;
+  uint8_t mode;
+
+  /*****************************************************************************************************/
+  /* Linecounter ***************************************************************************************/
+  /*****************************************************************************************************/
+  /*
+    ?PEEK(678) NTSC =0
+    ?PEEK(678) PAL = 1
+  */
+
+  if ( cpu.vic.rasterLine >= LINECNT ) {
+    //reSID sound needs much time - too much to keep everything in sync and with stable refreshrate
+    //but it is not called very often, so most of the time, we have more time than needed.
+    //We can measure the time needed for a frame and calc a correction factor to speed things up.
+    unsigned long m = fbmicros();
+    cpu.vic.neededTime = (m - cpu.vic.timeStart);
+    cpu.vic.timeStart = m;
+    cpu.vic.lineClock.setIntervalFast(LINETIMER_DEFAULT_FREQ - ((float)cpu.vic.neededTime / (float)LINECNT - LINETIMER_DEFAULT_FREQ ));
+
+    cpu.vic.rasterLine = 0;
+    cpu.vic.vcbase = 0;
+    cpu.vic.denLatch = 0;
+    //if (cpu.vic.rasterLine == LINECNT) {
+      emu_DrawVsync();
+    //}    
+
+  } else  cpu.vic.rasterLine++;
+
+  int r = cpu.vic.rasterLine;
+
+  if (r == cpu.vic.intRasterLine )//Set Rasterline-Interrupt
+    cpu.vic.R[0x19] |= 1 | ((cpu.vic.R[0x1a] & 1) << 7);
+
+  /*****************************************************************************************************/
+  /* Badlines ******************************************************************************************/
+  /*****************************************************************************************************/
+  /*
+    Ein Bad-Line-Zustand liegt in einem beliebigen Taktzyklus vor, wenn an der
+    negativen Flanke von ø0 zu Beginn des Zyklus RASTER >= $30 und RASTER <=
+    $f7 und die unteren drei Bits von RASTER mit YSCROLL übereinstimmen und in
+    einem beliebigen Zyklus von Rasterzeile $30 das DEN-Bit gesetzt war.
+
+    (default 3)
+    yscroll : POKE 53265, PEEK(53265) AND 248 OR 1:POKE 1024,0
+    yscroll : poke 53265, peek(53265) and 248 or 1
+
+    DEN : POKE 53265, PEEK(53265) AND 224 Bildschirm aus
+
+    Die einzige Verwendung von YSCROLL ist der Vergleich mit r in der Badline
+
+  */
+
+  if (r == 0x30 ) cpu.vic.denLatch |= cpu.vic.DEN;
+
+  /* 3.7.2
+    2. In der ersten Phase von Zyklus 14 jeder Zeile wird VC mit VCBASE geladen
+     (VCBASE->VC) und VMLI gelöscht. Wenn zu diesem Zeitpunkt ein
+     Bad-Line-Zustand vorliegt, wird zusätzlich RC auf Null gesetzt.
+  */
+
+  vc = cpu.vic.vcbase;
+
+  cpu.vic.badline = (cpu.vic.denLatch && (r >= 0x30) && (r <= 0xf7) && ( (r & 0x07) == cpu.vic.YSCROLL));
+
+  if (cpu.vic.badline) {
+    cpu.vic.idle = 0;
+    cpu.vic.rc = 0;
+  }
+
+  /*****************************************************************************************************/
+  /*****************************************************************************************************/
+#if 1
+  {
+    int t = MAXCYCLESSPRITES3_7 - cpu.vic.spriteCycles3_7;
+    if (t > 0) cpu_clock(t);
+    if (cpu.vic.spriteCycles3_7 > 0) cia_clockt(cpu.vic.spriteCycles3_7);
+  }
+#endif
+
+   //HBlank:
+   cpu_clock(10);
+
+#ifdef ADDITIONALCYCLES
+  cpu_clock(ADDITIONALCYCLES);
+#endif
+
+  //cpu.vic.videomatrix =  cpu.vic.bank + (unsigned)(cpu.vic.R[0x18] & 0xf0) * 64;
+
+  /* Rand oben /unten **********************************************************************************/
+  /*
+    RSEL  Höhe des Anzeigefensters  Erste Zeile   Letzte Zeile
+    0 24 Textzeilen/192 Pixel 55 ($37)  246 ($f6) = 192 sichtbare Zeilen, der Rest ist Rand oder unsichtbar
+    1 25 Textzeilen/200 Pixel 51 ($33)  250 ($fa) = 200 sichtbare Zeilen, der Rest ist Rand oder unsichtbar
+  */
+
+  if (cpu.vic.borderFlag) {
+    int firstLine = (cpu.vic.RSEL) ? 0x33 : 0x37;
+    if ((cpu.vic.DEN) && (r == firstLine)) cpu.vic.borderFlag = false;
+  } else {
+    int lastLine = (cpu.vic.RSEL) ? 0xfb : 0xf7;
+    if (r == lastLine) cpu.vic.borderFlag = true;
+  }
+
+  if (r < FIRSTDISPLAYLINE || r > LASTDISPLAYLINE ) {
+    if (r == 0)
+      cpu_clock(CYCLESPERRASTERLINE - 10 - 2 - MAXCYCLESSPRITES - 1); // (minus hblank l + r)
+    else
+      cpu_clock(CYCLESPERRASTERLINE - 10 - 2 - MAXCYCLESSPRITES  );
+    goto noDisplayIncRC;
+  }
+
+  //max_x =  (!cpu.vic.CSEL) ? 40:38;
+  p = &linebuffer[0];
+  pe = p + SCREEN_WIDTH;
+  //Left Screenborder: Cycle 10
+  spl = &cpu.vic.spriteLine[24];
+  cpu_clock(6);
+
+
+  if (cpu.vic.borderFlag) {
+	cpu_clock(5);
+    fastFillLineNoSprites(p, pe + BORDER_RIGHT, cpu.vic.colors[0]);
+    goto noDisplayIncRC ;
+  }
+
+
+  /*****************************************************************************************************/
+  /* DISPLAY *******************************************************************************************/
+  /*****************************************************************************************************/
+
+
+  //max_x =  (!cpu.vic.CSEL) ? 40:38;
+  //X-Scrolling:
+
+  xscroll = cpu.vic.XSCROLL;
+
+  if (xscroll > 0) {
+    uint16_t col = cpu.vic.colors[0];
+
+    if (!cpu.vic.CSEL) {
+      cpu_clock(1);
+      uint16_t sprite;
+      for (int i = 0; i < xscroll; i++) {
+        SPRITEORFIXEDCOLOR();
+      }
+    } else {
+      spl += xscroll;
+      for (unsigned i = 0; i < xscroll; i++) {
+        *p++ = col;
+      }
+
+    }
+  }
+
+  /*****************************************************************************************************/
+  /*****************************************************************************************************/
+  /*****************************************************************************************************/
+
+
+  cpu.vic.fgcollision = 0;
+  mode = (cpu.vic.ECM << 2) | (cpu.vic.BMM << 1) | cpu.vic.MCM;
+
+  if ( !cpu.vic.idle)  {
+
+#if 0
+    static uint8_t omode = 99;
+    if (mode != omode) {
+      Serial.print("Graphicsmode:");
+      Serial.println(mode);
+      omode = mode;
+    }
+#endif
+
+    modes[mode](p, pe, spl, vc);
+    vc = (vc + 40) & 0x3ff;
+
+  } else {
+	  /*
+3.7.3.9. Idle-Zustand
+---------------------
+
+Im Idle-Zustand liest der VIC die Grafikdaten von Adresse $3fff (bzw. $39ff
+bei gesetztem ECM-Bit) und stellt sie im ausgewählten Grafikmodus dar,
+wobei aber die Videomatrix-Daten (normalerweise in den c-Zugriffen gelesen)
+nur aus "0"-Bits bestehen. Es wird also immer wiederholt das Byte an
+Adresse $3fff/$39ff ausgegeben.
+
+c-Zugriff
+
+ Es werden keine c-Zugriffe ausgeführt.
+
+ Daten
+
+ +----+----+----+----+----+----+----+----+----+----+----+----+
+ | 11 | 10 |  9 |  8 |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+
+ |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+
+
+g-Zugriff
+
+ Adressen (ECM=0)
+
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ | 13 | 12 | 11 | 10 |  9 |  8 |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+
+ Adressen (ECM=1)
+
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ | 13 | 12 | 11 | 10 |  9 |  8 |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ |  1 |  1 |  1 |  0 |  0 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |
+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+
+ Daten
+
+ +----+----+----+----+----+----+----+----+
+ |  7 |  6 |  5 |  4 |  3 |  2 |  1 |  0 |
+ +----+----+----+----+----+----+----+----+
+ |         8 Pixel (1 Bit/Pixel)         | Standard-Textmodus/
+ |                                       | Multicolor-Textmodus/
+ | "0": Hintergrundfarbe 0 ($d021)       | ECM-Textmodus
+ | "1": Schwarz                          |
+ +---------------------------------------+
+ |         8 Pixel (1 Bit/Pixel)         | Standard-Bitmap-Modus/
+ |                                       | Ungültiger Textmodus/
+ | "0": Schwarz (Hintergrund)            | Ungültiger Bitmap-Modus 1
+ | "1": Schwarz (Vordergrund)            |
+ +---------------------------------------+
+ |         4 Pixel (2 Bit/Pixel)         | Multicolor-Bitmap-Modus
+ |                                       |
+ | "00": Hintergrundfarbe 0 ($d021)      |
+ | "01": Schwarz (Hintergrund)           |
+ | "10": Schwarz (Vordergrund)           |
+ | "11": Schwarz (Vordergrund)           |
+ +---------------------------------------+
+ |         4 Pixel (2 Bit/Pixel)         | Ungültiger Bitmap-Modus 2
+ |                                       |
+ | "00": Schwarz (Hintergrund)           |
+ | "01": Schwarz (Hintergrund)           |
+ | "10": Schwarz (Vordergrund)           |
+ | "11": Schwarz (Vordergrund)           |
+ +---------------------------------------+
+*/ 
+	//Modes 1 & 3
+    if (mode == 1 || mode == 3) {
+		modes[mode](p, pe, spl, vc);
+    } else {//TODO: all other modes
+	fastFillLine(p, pe, cpu.vic.palette[0], spl);
+	}
+  }
+
+  /*
+    Bei den MBC- und MMC-Interrupts löst jeweils nur die erste Kollision einen
+    Interrupt aus (d.h. wenn die Kollisionsregister $d01e bzw. $d01f vor der
+    Kollision den Inhalt Null hatten). Um nach einer Kollision weitere
+    Interrupts auszulösen, muß das betreffende Register erst durch Auslesen
+    gelöscht werden.
+  */
+
+  if (cpu.vic.fgcollision) {
+    if (cpu.vic.MD == 0) {
+      cpu.vic.R[0x19] |= 2 | ( (cpu.vic.R[0x1a] & 2) << 6);
+    }
+    cpu.vic.MD |= cpu.vic.fgcollision;
+  }
+
+  /*****************************************************************************************************/
+
+  if (!cpu.vic.CSEL) {
+    cpu_clock(1);
+    uint16_t col = cpu.vic.colors[0];
+    p = &linebuffer[0]; // tft.getLineBuffer((r - FIRSTDISPLAYLINE));
+#if 0
+    // Sprites im Rand
+    uint16_t sprite;
+    uint16_t * spl;
+    spl = &cpu.vic.spriteLine[24 + xscroll];
+
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR()
+    SPRITEORFIXEDCOLOR() //7
+#else
+    //keine Sprites im Rand
+    *p++ = col; *p++ = col; *p++ = col; *p++ = col;
+    *p++ = col; *p++ = col; *p = col;
+
+#endif
+
+    //Rand rechts:
+    p = &linebuffer[SCREEN_WIDTH - 9 + BORDER_LEFT]; //tft.getLineBuffer((r - FIRSTDISPLAYLINE)) + SCREEN_WIDTH - 9 + BORDER_LEFT;
+    pe = p + 9;
+
+#if 0
+    // Sprites im Rand
+    spl = &cpu.vic.spriteLine[24 + SCREEN_WIDTH - 9 + xscroll];
+    while (p < pe) {
+      SPRITEORFIXEDCOLOR();
+    }
+#else
+    //keine Sprites im Rand
+    //while (p < pe) {
+    //  *p++ = col;
+    //}
+#endif
+
+
+
+  }
+
+  emu_DrawLine16(&linebuffer[0], SCREEN_WIDTH, SCREEN_HEIGHT, (r - FIRSTDISPLAYLINE));
+  memset(&linebuffer[0],0,SCREEN_WIDTH*2);
+
+
+
+
+//Rechter Rand nach CSEL, im Textbereich
+cpu_clock(5);
+
+
+noDisplayIncRC:
+  /* 3.7.2
+    5. In der ersten Phase von Zyklus 58 wird geprüft, ob RC=7 ist. Wenn ja,
+     geht die Videologik in den Idle-Zustand und VCBASE wird mit VC geladen
+     (VC->VCBASE). Ist die Videologik danach im Display-Zustand (liegt ein
+     Bad-Line-Zustand vor, ist dies immer der Fall), wird RC erhöht.
+  */
+
+  if (cpu.vic.rc == 7) {
+    cpu.vic.idle = 1;
+    cpu.vic.vcbase = vc;
+  }
+  //Ist dies richtig ??
+  if ((!cpu.vic.idle) || (cpu.vic.denLatch && (r >= 0x30) && (r <= 0xf7) && ( (r & 0x07) == cpu.vic.YSCROLL))) {
+    cpu.vic.rc = (cpu.vic.rc + 1) & 0x07;
+  }
+
+
+  /*****************************************************************************************************/
+  /* Sprites *******************************************************************************************/
+  /*****************************************************************************************************/
+
+  cpu.vic.spriteCycles0_2 = 0;
+  cpu.vic.spriteCycles3_7 = 0;
+
+  if (cpu.vic.lineHasSprites) {
+	cpu.vic.lineHasSprites = 0;
+    memset(cpu.vic.spriteLine, 0, sizeof(cpu.vic.spriteLine) );
+  }
+
+  uint32_t spriteYCheck = cpu.vic.R[0x15]; //Sprite enabled Register
+
+  if (spriteYCheck) {
+
+    unsigned short R17 = cpu.vic.R[0x17]; //Sprite-y-expansion
+    unsigned char collision = 0;
+    short lastSpriteNum = 0;
+
+    for (unsigned short i = 0; i < 8; i++) {
+      if (!spriteYCheck) break;
+
+      unsigned b = 1 << i;
+
+      if (spriteYCheck & b )  {
+        spriteYCheck &= ~b;
+        short y = cpu.vic.R[i * 2 + 1];
+
+        if ( (r >= y ) && //y-Position > Sprite-y ?
+             (((r < y + 21) && (~R17 & b )) || // ohne y-expansion
+              ((r < y + 2 * 21 ) && (R17 & b ))) ) //mit y-expansion
+        {
+
+          //Sprite Cycles
+          if (i < 3) {
+            if (!lastSpriteNum) cpu.vic.spriteCycles0_2 += 1;
+            cpu.vic.spriteCycles0_2 += 2;
+          } else {
+            if (!lastSpriteNum) cpu.vic.spriteCycles3_7 += 1;
+            cpu.vic.spriteCycles3_7 += 2;
+          }
+          lastSpriteNum = i;
+          //Sprite Cycles END
+
+
+          if (r < FIRSTDISPLAYLINE || r > LASTDISPLAYLINE ) continue;
+
+          uint16_t x =  (((cpu.vic.R[0x10] >> i) & 1) << 8) | cpu.vic.R[i * 2];
+          if (x >= SPRITE_MAX_X) continue;
+
+          unsigned short lineOfSprite = r - y;
+          if (R17 & b) lineOfSprite = lineOfSprite / 2; // Y-Expansion
+          unsigned short spriteadr = cpu.vic.bank | cpu.RAM[cpu.vic.videomatrix + (1024 - 8) + i] << 6 | (lineOfSprite * 3);
+          unsigned spriteData = ((unsigned)cpu.RAM[ spriteadr ] << 16) | ((unsigned)cpu.RAM[ spriteadr + 1 ] << 8) | ((unsigned)cpu.RAM[ spriteadr + 2 ]);
+
+          if (!spriteData) continue;
+          cpu.vic.lineHasSprites = 1;
+
+          uint16_t * slp = &cpu.vic.spriteLine[x]; //Sprite-Line-Pointer
+          unsigned short upperByte = ( 0x80 | ( (cpu.vic.MDP & b) ? 0x40 : 0 ) | i ) << 8; //Bit7 = Sprite "da", Bit 6 = Sprite-Priorität vor Grafik/Text, Bits 3..0 = Spritenummer
+
+          //Sprite in Spritezeile schreiben:
+          if ((cpu.vic.MMC & b) == 0) { // NO MULTICOLOR
+
+            uint16_t color = upperByte | cpu.vic.R[0x27 + i];
+
+            if ((cpu.vic.MXE & b) == 0) { // NO MULTICOLOR, NO SPRITE-EXPANSION
+
+              for (unsigned cnt = 0; (spriteData > 0) && (cnt < 24); cnt++) {
+                int c = (spriteData >> 23) & 0x01;
+                spriteData = (spriteData << 1);
+
+                if (c) {
+                  if (*slp == 0) *slp = color;
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                }
+                slp++;
+
+              }
+
+            } else {    // NO MULTICOLOR, SPRITE-EXPANSION
+
+              for (unsigned cnt = 0; (spriteData > 0) && (cnt < 24); cnt++) {
+                int c = (spriteData >> 23) & 0x01;
+                spriteData = (spriteData << 1);
+                //So wie oben, aber zwei gleiche Pixel
+
+                if (c) {
+                  if (*slp == 0) *slp = color;
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                  if (*slp == 0) *slp = color;
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                } else {
+                  slp += 2;
+                }
+
+              }
+            }
+
+
+
+          } else { // MULTICOLOR
+            /* Im Mehrfarbenmodus (Multicolor-Modus) bekommen alle Sprites zwei zusätzliche gemeinsame Farben.
+              Die horizontale Auflösung wird von 24 auf 12 halbiert, da bei der Sprite-Definition jeweils zwei Bits zusammengefasst werden.
+            */
+            uint16_t colors[4];
+            //colors[0] = 1; //dummy, color 0 is transparent
+            colors[1] = upperByte | cpu.vic.R[0x25];
+            colors[2] = upperByte | cpu.vic.R[0x27 + i];
+            colors[3] = upperByte | cpu.vic.R[0x26];
+
+            if ((cpu.vic.MXE & b) == 0) { // MULTICOLOR, NO SPRITE-EXPANSION
+              for (unsigned cnt = 0; (spriteData > 0) && (cnt < 24); cnt++) {
+                int c = (spriteData >> 22) & 0x03;
+                spriteData = (spriteData << 2);
+
+                if (c) {
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                } else {
+                  slp += 2;
+                }
+
+              }
+
+            } else {    // MULTICOLOR, SPRITE-EXPANSION
+              for (unsigned cnt = 0; (spriteData > 0) && (cnt < 24); cnt++) {
+                int c = (spriteData >> 22) & 0x03;
+                spriteData = (spriteData << 2);
+
+                //So wie oben, aber vier gleiche Pixel
+                if (c) {
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                  if (*slp == 0) *slp = colors[c];
+                  else collision |= b | (1 << ((*slp >> 8) & 0x07));
+                  slp++;
+                } else {
+                  slp += 4;
+                }
+
+              }
+
+            }
+          }
+
+        }
+        else lastSpriteNum = 0;
+      }
+
+    }
+
+    if (collision) {
+      if (cpu.vic.MM == 0) {
+        cpu.vic.R[0x19] |= 4 | ((cpu.vic.R[0x1a] & 4) << 5 );
+      }
+      cpu.vic.MM |= collision;
+    }
+
+  }
+  /*****************************************************************************************************/
+#if 0
+  {
+    int t = MAXCYCLESSPRITES0_2 - cpu.vic.spriteCycles0_2;
+    if (t > 0) cpu_clock(t);
+    if (cpu.vic.spriteCycles0_2 > 0) cia_clockt(cpu.vic.spriteCycles0_2);
+  }
+#endif
+
+   //HBlank:
+#if PAL
+   cpu_clock(2);
+#else
+   cpu_clock(3);
+#endif
+
+
+#if 0
+   if (cpu.vic.idle) {
+	   Serial.print("Cycles line ");
+	   Serial.print(r);
+	   Serial.print(": ");
+	   Serial.println(cpu.lineCyclesAbs);
+   }
+#endif
+
+
+  return;
+}
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+void fastFillLineNoSprites(tpixel * p, const tpixel * pe, const uint16_t col) {
+  int i = 0;
+
+  while (p < pe) {
+		*p++ = col;
+		i = (i + 1) & 0x07;
+		if (!i) CYCLES(1);
+  }
+
+
+}
+
+void fastFillLine(tpixel * p, const tpixel * pe, const uint16_t col, uint16_t *  spl) {
+  if (spl != NULL && cpu.vic.lineHasSprites) {
+	int i = 0;
+	uint16_t sprite;
+    while ( p < pe ) {
+		SPRITEORFIXEDCOLOR();
+		i = (i + 1) & 0x07;
+		if (!i) CYCLES(1);
+    };
+
+  } else {
+
+    fastFillLineNoSprites(p, pe, col);
+
+  }
+}
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+void vic_displaySimpleModeScreen(void) {
+}
+
+
+void vic_do_simple(void) {
+  uint16_t vc;
+  int cycles = 0;
+
+if ( cpu.vic.rasterLine >= LINECNT ) {
+
+    //reSID sound needs much time - too much to keep everything in sync and with stable refreshrate
+    //but it is not called very often, so most of the time, we have more time than needed.
+    //We can measure the time needed for a frame and calc a correction factor to speed things up.
+    unsigned long m = fbmicros();
+    cpu.vic.neededTime = (m - cpu.vic.timeStart);
+    cpu.vic.timeStart = m;
+    cpu.vic.lineClock.setIntervalFast(LINETIMER_DEFAULT_FREQ - ((float)cpu.vic.neededTime / (float)LINECNT - LINETIMER_DEFAULT_FREQ ));
+
+    cpu.vic.rasterLine = 0;
+    cpu.vic.vcbase = 0;
+    cpu.vic.denLatch = 0;
+
+  } else  {
+	  cpu.vic.rasterLine++;
+	  cpu_clock(1);
+	  cycles += 1;
+  }
+
+  int r = cpu.vic.rasterLine;
+
+  if (r == cpu.vic.intRasterLine )//Set Rasterline-Interrupt
+    cpu.vic.R[0x19] |= 1 | ((cpu.vic.R[0x1a] & 1) << 7);
+
+  cpu_clock(9);
+  cycles += 9;
+
+  if (r == 0x30 ) cpu.vic.denLatch |= cpu.vic.DEN;
+
+  vc = cpu.vic.vcbase;
+
+  cpu.vic.badline = (cpu.vic.denLatch && (r >= 0x30) && (r <= 0xf7) && ( (r & 0x07) == cpu.vic.YSCROLL));
+
+  if (cpu.vic.badline) {
+    cpu.vic.idle = 0;
+    cpu.vic.rc = 0;
+  }
+
+
+  /* Rand oben /unten **********************************************************************************/
+  /*
+    RSEL  Höhe des Anzeigefensters  Erste Zeile   Letzte Zeile
+    0 24 Textzeilen/192 Pixel 55 ($37)  246 ($f6) = 192 sichtbare Zeilen, der Rest ist Rand oder unsichtbar
+    1 25 Textzeilen/200 Pixel 51 ($33)  250 ($fa) = 200 sichtbare Zeilen, der Rest ist Rand oder unsichtbar
+  */
+
+  if (cpu.vic.borderFlag) {
+    int firstLine = (cpu.vic.RSEL) ? 0x33 : 0x37;
+    if ((cpu.vic.DEN) && (r == firstLine)) cpu.vic.borderFlag = false;
+  } else {
+    int lastLine = (cpu.vic.RSEL) ? 0xfb : 0xf7;
+    if (r == lastLine) cpu.vic.borderFlag = true;
+  }
+
+
+ //left screenborder
+ cpu_clock(6);
+ cycles += 6;
+
+ CYCLES(40);
+ cycles += 40;
+ vc += 40;
+
+ //right screenborder
+ cpu_clock(4); //1
+ cycles += 4;
+
+
+  if (cpu.vic.rc == 7) {
+    cpu.vic.idle = 1;
+    cpu.vic.vcbase = vc;
+  }
+  //Ist dies richtig ??
+  if ((!cpu.vic.idle) || (cpu.vic.denLatch && (r >= 0x30) && (r <= 0xf7) && ( (r & 0x07) == cpu.vic.YSCROLL))) {
+    cpu.vic.rc = (cpu.vic.rc + 1) & 0x07;
+  }
+
+  cpu_clock(3); //1
+ cycles += 3;
+
+ int cyclesleft = CYCLESPERRASTERLINE - cycles;
+ if (cyclesleft) cpu_clock(cyclesleft);
+
+}
+
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+void installPalette(void) {
+ memcpy(cpu.vic.palette, (void*)palette, sizeof(cpu.vic.palette));
+}
+
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+void vic_adrchange(void) {
+  uint8_t r18 = cpu.vic.R[0x18];
+  cpu.vic.videomatrix =  cpu.vic.bank + (unsigned)(r18 & 0xf0) * 64;
+
+  unsigned charsetAddr = r18 & 0x0e;
+  if  ((cpu.vic.bank & 0x4000) == 0) {
+    if (charsetAddr == 0x04) cpu.vic.charsetPtrBase =  ((uint8_t *)&rom_characters);
+    else if (charsetAddr == 0x06) cpu.vic.charsetPtrBase =  ((uint8_t *)&rom_characters) + 0x800;
+    else
+      cpu.vic.charsetPtrBase = &cpu.RAM[charsetAddr * 0x400 + cpu.vic.bank] ;
+  } else
+    cpu.vic.charsetPtrBase = &cpu.RAM[charsetAddr * 0x400 + cpu.vic.bank];
+
+  cpu.vic.bitmapPtr = (uint8_t*) &cpu.RAM[cpu.vic.bank | ((r18 & 0x08) * 0x400)];
+  if ((cpu.vic.R[0x11] & 0x60) == 0x60)  cpu.vic.bitmapPtr = (uint8_t*)((uintptr_t)cpu.vic.bitmapPtr & 0xf9ff);
+
+}
+/*****************************************************************************************************/
+void vic_write(uint32_t address, uint8_t value) {
+
+  address &= 0x3F;
+
+  switch (address) {
+    case 0x11 :
+    cpu.vic.R[address] = value;
+      cpu.vic.intRasterLine = (cpu.vic.intRasterLine & 0xff) | ((((uint16_t) value) << 1) & 0x100);
+      if (cpu.vic.rasterLine == 0x30 ) cpu.vic.denLatch |= value & 0x10;
+
+      cpu.vic.badline = (cpu.vic.denLatch && (cpu.vic.rasterLine >= 0x30) && (cpu.vic.rasterLine <= 0xf7) && ( (cpu.vic.rasterLine & 0x07) == (value & 0x07)));
+
+    if (cpu.vic.badline) {
+    cpu.vic.idle = 0;
+    }
+
+    vic_adrchange();
+
+      break;
+    case 0x12 :
+      cpu.vic.intRasterLine = (cpu.vic.intRasterLine & 0x100) | value;
+      cpu.vic.R[address] = value;
+      break;
+    case 0x18 :
+      cpu.vic.R[address] = value;
+      vic_adrchange();
+      break;
+    case 0x19 : //IRQs
+      cpu.vic.R[0x19] &= (~value & 0x0f);
+      break;
+    case 0x1A : //IRQ Mask
+      cpu.vic.R[address] = value & 0x0f;
+      break;
+    case 0x1e:
+    case 0x1f:
+      cpu.vic.R[address] = 0;
+      break;
+    case 0x20 ... 0x2E:
+      cpu.vic.R[address] = value & 0x0f;
+      cpu.vic.colors[address - 0x20] = cpu.vic.palette[value & 0x0f];
+      break;
+    case 0x2F ... 0x3F:
+      break;
+    default :
+      cpu.vic.R[address] = value;
+      break;
+  }
+
+  //#if DEBUGVIC
+#if 0
+  Serial.print("VIC ");
+  Serial.print(address, HEX);
+  Serial.print("=");
+  Serial.println(value, HEX);
+  //logAddr(address, value, 1);
+#endif
+}
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+uint8_t vic_read(uint32_t address) {
+  uint8_t ret;
+
+  address &= 0x3F;
+  switch (address) {
+
+    case 0x11:
+      ret = (cpu.vic.R[address] & 0x7F) | ((cpu.vic.rasterLine & 0x100) >> 1);
+      break;
+    case 0x12:
+      ret = cpu.vic.rasterLine;
+      break;
+    case 0x16:
+      ret = cpu.vic.R[address] | 0xC0;
+      break;
+    case 0x18:
+      ret = cpu.vic.R[address] | 0x01;
+      break;
+    case 0x19:
+      ret = cpu.vic.R[address] | 0x70;
+      break;
+    case 0x1a:
+      ret = cpu.vic.R[address] | 0xF0;
+      break;
+    case 0x1e:
+    case 0x1f:
+      ret = cpu.vic.R[address];
+      cpu.vic.R[address] = 0;
+      break;
+    case 0x20 ... 0x2E:
+      ret = cpu.vic.R[address] | 0xF0;
+      break;
+    case 0x2F ... 0x3F:
+      ret = 0xFF;
+      break;
+    default:
+      ret = cpu.vic.R[address];
+      break;
+  }
+
+#if DEBUGVIC
+  Serial.print("VIC ");
+  logAddr(address, ret, 0);
+#endif
+  return ret;
+}
+
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+/*****************************************************************************************************/
+
+void resetVic(void) {
+  enableCycleCounter();
+
+  cpu.vic.intRasterLine = 0;
+  cpu.vic.rasterLine = 0;
+  cpu.vic.lineHasSprites = 0;
+  memset(&cpu.RAM[0x400], 0, 1000);
+  memset(&cpu.vic, 0, sizeof(cpu.vic));
+  
+
+
+  installPalette();  
+
+  //http://dustlayer.com/vic-ii/2013/4/22/when-visibility-matters
+  cpu.vic.R[0x11] = 0x9B;
+  cpu.vic.R[0x16] = 0x08;
+  cpu.vic.R[0x18] = 0x14;
+  cpu.vic.R[0x19] = 0x0f;
+
+  for (unsigned i = 0; i < sizeof(cpu.vic.COLORRAM); i++)
+    cpu.vic.COLORRAM[i] = (rand() & 0x0F);
+
+  cpu.RAM[0x39FF] = 0x0;
+  cpu.RAM[0x3FFF] = 0x0;
+  cpu.RAM[0x39FF + 16384] = 0x0;
+  cpu.RAM[0x3FFF + 16384] = 0x0;
+  cpu.RAM[0x39FF + 32768] = 0x0;
+  cpu.RAM[0x3FFF + 32768] = 0x0;
+  cpu.RAM[0x39FF + 49152] = 0x0;
+  cpu.RAM[0x3FFF + 49152] = 0x0;
+
+  vic_adrchange();
+}
+
+
+/*
+  ?PEEK(678) NTSC =0
+  ?PEEK(678) PAL = 1
+  PRINT TIME$
+*/
+/*
+          Raster-  Takt-   sichtb.  sichtbare
+  VIC-II  System  zeilen   zyklen  Zeilen   Pixel/Zeile
+  -------------------------------------------------------
+  6569    PAL    312     63    284     403
+  6567R8  NTSC   263     65    235     418
+  6567R56A  NTSC   262   64    234     411
+*/
diff --git a/MCUME_pico2/pico64/vic.h b/MCUME_pico2/pico64/vic.h
new file mode 100755
index 0000000..b1b03ba
--- /dev/null
+++ b/MCUME_pico2/pico64/vic.h
@@ -0,0 +1,144 @@
+/*
+  Copyright Frank Bösing, 2017
+
+  This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+#ifndef Teensy64_vic_h_
+#define Teensy64_vic_h_
+
+#include "Teensy64.h"
+#include "IntervalTimer.h"
+
+
+
+#define SPRITE_MAX_X (320 + 24)
+
+/* for later use
+struct tsprite {
+  uint8_t MC; //Mob Data Counter
+  uint8_t MCBase; //Mob Data Counter Base
+  uint8_t MobYexpand; //Y-Epansion FlipFlop
+};
+*/
+
+struct tvic {
+  uint32_t timeStart, neededTime;
+  int intRasterLine; //Interruptsetting
+  int rasterLine;
+  uint16_t bank;
+  uint16_t vcbase;
+  uint8_t rc;
+
+  uint8_t borderFlag;  //Top-Bottom border flag
+  uint8_t borderFlagH; //Left-Right border flag
+  uint8_t idle;
+  uint8_t denLatch;
+  uint8_t badline;
+  uint8_t BAsignal;
+  uint8_t lineHasSprites;
+  int8_t spriteCycles0_2;
+  int8_t spriteCycles3_7;
+  int fgcollision;
+
+  uint8_t * charsetPtrBase;
+  uint8_t * charsetPtr;
+  uint8_t * bitmapPtr;
+  uint16_t videomatrix;
+
+  uint16_t colors[15]; // translated ([palette]) colors
+  uint16_t palette[16];
+
+  MyIntervalTimer lineClock;
+
+  union {
+    uint8_t R[0x40];
+    struct {
+      uint8_t M0X, M0Y, M1X, M1Y, M2X, M2Y, M3X, M3Y, M4X, M4Y, M5X, M5Y, M6X, M6Y, M7X, M7Y;
+      uint8_t MX8; // Sprite-X Bit 8 $D010
+      uint8_t YSCROLL: 3, RSEL: 1, DEN: 1, BMM: 1, ECM: 1, RST8: 1; // $D011
+      uint8_t RASTER; // Rasterline $D012
+      uint8_t LPX; // Lightpen X $D013
+      uint8_t LPY; // Lightpen Y $D014
+      uint8_t ME;  // Sprite Enable $D015
+      uint8_t XSCROLL: 3, CSEL: 1, MCM: 1, RES: 1, : 2; // $D016
+      uint8_t MYE; // Sprite Y-Expansion $D017
+      uint8_t : 1, CB: 3, VM: 4; // $D018
+      uint8_t IRST: 1, IMBC: 1, IMMC: 1, ILP: 1, : 3, IRQ: 1; // $D019
+      uint8_t ERST: 1, EMBC: 1, EMMC: 1, ELP: 1, : 4; // $D01A
+      uint8_t MDP; // Sprite-Daten-Priority $D01B
+      uint8_t MMC; // Sprite Multicolor $D01C
+      uint8_t MXE; // Sprite X-Expansion $D01D
+      uint8_t MM;  // Sprite-Sprite collision $D01E
+      uint8_t MD;  // Sprite-Data collision $D01F
+      uint8_t EC: 4, : 4; // Bordercolor $D020
+      uint8_t B0C: 4, : 4; // Backgroundcolor 0 $D021
+      uint8_t B1C: 4, : 4; // Backgroundcolor 1 $D022
+      uint8_t B2C: 4, : 4; // Backgroundcolor 2 $D023
+      uint8_t B3C: 4, : 4; // Backgroundcolor 3 $D024
+      uint8_t MM0: 4, : 4; // Sprite Multicolor 0 $D025
+      uint8_t MM1: 4, : 4; // Sprite Multicolor 1 $D026
+      uint8_t M0C: 4, : 4; // Spritecolor 0 $D027
+      uint8_t M1C: 4, : 4; // Spritecolor 1 $D028
+      uint8_t M2C: 4, : 4; // Spritecolor 2 $D029
+      uint8_t M3C: 4, : 4; // Spritecolor 3 $D02A
+      uint8_t M4C: 4, : 4; // Spritecolor 4 $D02B
+      uint8_t M5C: 4, : 4; // Spritecolor 5 $D02C
+      uint8_t M6C: 4, : 4; // Spritecolor 6 $D02D
+      uint8_t M7C: 4, : 4; // Spritecolor 7 $D02E
+    };
+  };
+
+  //tsprite spriteInfo[8];//todo
+  uint16_t spriteLine[SPRITE_MAX_X];
+
+  uint8_t lineMemChr[40];
+  uint8_t lineMemCol[40];
+  uint8_t COLORRAM[1024];
+
+};
+
+void vic_do(void);
+void vic_do_simple(void);
+void vic_displaySimpleModeScreen(void);
+
+void vic_write(uint32_t address, uint8_t value) ;
+uint8_t vic_read(uint32_t address);
+
+void vic_colorwrite(uint32_t address, uint8_t value);
+uint8_t vic_colorread(uint32_t address);
+
+void vic_adrchange(void);
+
+void resetVic(void);
+
+#endif
diff --git a/MCUME_pico2/pico64/vic_palette.h b/MCUME_pico2/pico64/vic_palette.h
new file mode 100755
index 0000000..bc7080d
--- /dev/null
+++ b/MCUME_pico2/pico64/vic_palette.h
@@ -0,0 +1,112 @@
+/*
+	Copyright Frank Bösing, 2017
+
+	This file is part of Teensy64.
+
+    Teensy64 is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    Teensy64 is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with Teensy64.  If not, see <http://www.gnu.org/licenses/>.
+
+    Diese Datei ist Teil von Teensy64.
+
+    Teensy64 ist Freie Software: Sie können es unter den Bedingungen
+    der GNU General Public License, wie von der Free Software Foundation,
+    Version 3 der Lizenz oder (nach Ihrer Wahl) jeder späteren
+    veröffentlichten Version, weiterverbreiten und/oder modifizieren.
+
+    Teensy64 wird in der Hoffnung, dass es nützlich sein wird, aber
+    OHNE JEDE GEWÄHRLEISTUNG, bereitgestellt; sogar ohne die implizite
+    Gewährleistung der MARKTFÄHIGKEIT oder EIGNUNG FÜR EINEN BESTIMMTEN ZWECK.
+    Siehe die GNU General Public License für weitere Details.
+
+    Sie sollten eine Kopie der GNU General Public License zusammen mit diesem
+    Programm erhalten haben. Wenn nicht, siehe <http://www.gnu.org/licenses/>.
+
+*/
+
+/* choose your "display"-type */
+
+#if 1 // color display (default)
+
+// MACROS moved to vic implementations
+
+#elif 0 // B&W TV for real retro feeling. Looks great (ILI 9341 only)
+#define PALETTE(r,g,b) ( ((((int)( 0.299f * r + 0.587f * g + 0.114f * b )) & 0xF8) << 8 ) | \
+						( (((int) ( 0.299f * r + 0.587f * g + 0.114f * b )) & 0xFC) << 3 ) | \
+						( (((int) ( 0.299f * r + 0.587f * g + 0.114f * b )) & 0xFF) >> 3 ))
+
+
+#elif 0 // green display (ILI 9341 only)
+#define PALETTE(r,g,b) ( ( 0 ) | \
+						( (((int) ( 0.299f * r + 0.587f * g + 0.114f * b )) & 0xFC) << 3 ) | \
+						( 0 ))
+// TODO: amber display
+#endif
+
+
+
+/* chose one of these palettes:
+   VGA is 256 colors only (rrrgggbb) , subtle differences might not be visible
+*/
+
+#if 1 // "Deekay" (default)
+static const uint16_t palette[16] = {
+	PALETTE(0x00,0x00,0x00), PALETTE(0xff,0xff,0xff), PALETTE(0x88,0x20,0x00), PALETTE(0x68,0xd0,0xa8), // black, white, red, cyan,
+	PALETTE(0xa8,0x38,0xa0), PALETTE(0x50,0xb8,0x18), PALETTE(0x18,0x10,0x90), PALETTE(0xf0,0xe8,0x58), // purple, green, blue, yellow
+	PALETTE(0xa0,0x48,0x00), PALETTE(0x47,0x2b,0x1b), PALETTE(0xc8,0x78,0x70), PALETTE(0x48,0x48,0x48), // orange, brown, lightred, grey1,
+	PALETTE(0x80,0x80,0x80), PALETTE(0x98,0xff,0x98), PALETTE(0x50,0x90,0xd0), PALETTE(0xb8,0xb8,0xb8)  // grey2, lightgreen, lightblue, grey3
+};
+
+#elif 0 // VICE vice.vpl
+static const uint16_t palette[16] = {
+	PALETTE(0x00,0x00,0x00), PALETTE(0xFD,0xFE,0xFC), PALETTE(0xBE,0x1a,0x24), PALETTE(0x30,0xe6,0xc6), // black, white, red, cyan,
+	PALETTE(0xb4,0x1a,0xe2), PALETTE(0x1f,0xd2,0x1e), PALETTE(0x21,0x1b,0xae), PALETTE(0xdf,0xf6,0x0a), // purple, green, blue, yellow
+	PALETTE(0xb8,0x41,0x04), PALETTE(0x6a,0x33,0x04), PALETTE(0xfe,0x4a,0x57), PALETTE(0x42,0x45,0x40), // orange, brown, lightred, grey1,
+	PALETTE(0x70,0x74,0x6f), PALETTE(0x59,0xfe,0x59), PALETTE(0x5f,0x53,0xfe), PALETTE(0xa4,0xa7,0xa2)  // grey2, lightgreen, lightblue, grey3
+};
+
+
+#elif 0 // "PEPTO" http://www.pepto.de/projects/colorvic/2001/
+static const uint16_t palette[16] = {
+  0x0000, 0xFFFF, 0x69A5, 0x7536, 0x69F0, 0x5C68, 0x314F, 0xBE2D,// black, white, red, cyan, purple, green, blue, yellow
+  0x6A64, 0x41C0, 0x9B2B, 0x4228, 0x6B6D, 0x9E90, 0x6AF6, 0x94B2 // orange, brown, lightred, grey1, grey2, lightgreen, lightblue, grey3
+};
+
+
+#elif 0 // "GODOT" http://www.godot64.de/german/hpalet.htm
+static const uint16_t palette[16] = {
+	PALETTE(0x00,0x00,0x00), PALETTE(0xff,0xff,0xff), PALETTE(0x88,0x00,0x00), PALETTE(0xaa,0xff,0xee), // black, white, red, cyan,
+	PALETTE(0xcc,0x44,0xcc), PALETTE(0x00,0xcc,0x55), PALETTE(0x00,0x00,0xaa), PALETTE(0xee,0xee,0x77), // purple, green, blue, yellow
+	PALETTE(0xdd,0x88,0x55), PALETTE(0x66,0x44,0x00), PALETTE(0xff,0x77,0x77), PALETTE(0x33,0x33,0x33), // orange, brown, lightred, grey1,
+	PALETTE(0x77,0x77,0x77), PALETTE(0xaa,0xff,0x66), PALETTE(0x00,0x88,0xff), PALETTE(0xbb,0xbb,0xbb)  // grey2, lightgreen, lightblue, grey3
+};
+
+
+#elif 0 // "FRODO"
+static const uint16_t palette[16] = {
+	PALETTE(0x00,0x00,0x00), PALETTE(0xff,0xff,0xff), PALETTE(0xcc,0x00,0x00), PALETTE(0x00,0xff,0xcc), // black, white, red, cyan,
+	PALETTE(0xff,0x00,0xff), PALETTE(0x00,0xcc,0x00), PALETTE(0x00,0x00,0xcc), PALETTE(0xff,0xff,0x00), // purple, green, blue, yellow
+	PALETTE(0xff,0x88,0x00), PALETTE(0x88,0x44,0x00), PALETTE(0xff,0x88,0x88), PALETTE(0x44,0x44,0x44), // orange, brown, lightred, grey1,
+	PALETTE(0x88,0x88,0x88), PALETTE(0x88,0xff,0x88), PALETTE(0x88,0x88,0xff), PALETTE(0xcc,0xcc,0xcc)  // grey2, lightgreen, lightblue, grey3
+};
+
+
+#elif 0 //RGB (full saturated colors - only good for testing)
+static const uint16_t palette[16] = {
+	PALETTE(0x00,0x00,0x00), PALETTE(0xff,0xff,0xff), PALETTE(0xff,0x00,0x00), PALETTE(0x00,0xff,0xff), // black, white, red, cyan,
+	PALETTE(0xff,0x00,0xff), PALETTE(0x00,0xff,0x00), PALETTE(0x00,0x00,0xff), PALETTE(0xff,0xff,0x00), // purple, green, blue, yellow
+	PALETTE(0xff,0x80,0x00), PALETTE(0x80,0x40,0x00), PALETTE(0xff,0x80,0x80), PALETTE(0x40,0x40,0x40), // orange, brown, lightred, grey1,
+	PALETTE(0x80,0x80,0x80), PALETTE(0x80,0xff,0x80), PALETTE(0x80,0x80,0xff), PALETTE(0xc0,0xc0,0xc0)  // grey2, lightgreen, lightblue, grey3
+};
+#endif
+
+#undef BW
diff --git a/MCUME_pico2/pico800/akey.h b/MCUME_pico2/pico800/akey.h
new file mode 100644
index 0000000..ee0e83a
--- /dev/null
+++ b/MCUME_pico2/pico800/akey.h
@@ -0,0 +1,240 @@
+#ifndef AKEY_H_
+#define AKEY_H_
+/* akey.h: Atari key codes */
+
+/* INPUT_key_code values */
+#define AKEY_NONE -1
+
+/* Special key codes. */
+#define AKEY_WARMSTART             -2
+#define AKEY_COLDSTART             -3
+#define AKEY_EXIT                  -4
+#define AKEY_BREAK                 -5
+#define AKEY_UI                    -7
+#define AKEY_SCREENSHOT            -8
+#define AKEY_SCREENSHOT_INTERLACE  -9
+#define AKEY_START                 -10
+#define AKEY_SELECT                -11
+#define AKEY_OPTION                -12
+#define AKEY_PBI_BB_MENU           -13
+#define AKEY_CX85_1                -14
+#define AKEY_CX85_2                -15
+#define AKEY_CX85_3                -16
+#define AKEY_CX85_4                -17
+#define AKEY_CX85_5                -18
+#define AKEY_CX85_6                -19
+#define AKEY_CX85_7                -20
+#define AKEY_CX85_8                -21
+#define AKEY_CX85_9                -22
+#define AKEY_CX85_0                -23
+#define AKEY_CX85_PERIOD           -24
+#define AKEY_CX85_MINUS            -25
+#define AKEY_CX85_PLUS_ENTER       -26
+#define AKEY_CX85_ESCAPE           -27
+#define AKEY_CX85_NO               -28
+#define AKEY_CX85_DELETE           -29
+#define AKEY_CX85_YES              -30
+#define AKEY_TURBO                 -31
+#ifdef USE_UI_BASIC_ONSCREEN_KEYBOARD
+#define AKEY_KEYB                  -32
+#endif
+#ifdef DIRECTX
+	/* special menu directives */
+	#define AKEY32_MENU_SAVE_CONFIG     -107
+	#define AKEY32_UI_MOUSE_CLICK       -108
+#endif
+
+#define AKEY_SHFT 0x40
+#define AKEY_CTRL 0x80
+#define AKEY_SHFTCTRL 0xc0
+
+#define AKEY_0 0x32
+#define AKEY_1 0x1f
+#define AKEY_2 0x1e
+#define AKEY_3 0x1a
+#define AKEY_4 0x18
+#define AKEY_5 0x1d
+#define AKEY_6 0x1b
+#define AKEY_7 0x33
+#define AKEY_8 0x35
+#define AKEY_9 0x30
+
+#define AKEY_CTRL_0 (AKEY_CTRL | AKEY_0)
+#define AKEY_CTRL_1 (AKEY_CTRL | AKEY_1)
+#define AKEY_CTRL_2 (AKEY_CTRL | AKEY_2)
+#define AKEY_CTRL_3 (AKEY_CTRL | AKEY_3)
+#define AKEY_CTRL_4 (AKEY_CTRL | AKEY_4)
+#define AKEY_CTRL_5 (AKEY_CTRL | AKEY_5)
+#define AKEY_CTRL_6 (AKEY_CTRL | AKEY_6)
+#define AKEY_CTRL_7 (AKEY_CTRL | AKEY_7)
+#define AKEY_CTRL_8 (AKEY_CTRL | AKEY_8)
+#define AKEY_CTRL_9 (AKEY_CTRL | AKEY_9)
+
+#define AKEY_a 0x3f
+#define AKEY_b 0x15
+#define AKEY_c 0x12
+#define AKEY_d 0x3a
+#define AKEY_e 0x2a
+#define AKEY_f 0x38
+#define AKEY_g 0x3d
+#define AKEY_h 0x39
+#define AKEY_i 0x0d
+#define AKEY_j 0x01
+#define AKEY_k 0x05
+#define AKEY_l 0x00
+#define AKEY_m 0x25
+#define AKEY_n 0x23
+#define AKEY_o 0x08
+#define AKEY_p 0x0a
+#define AKEY_q 0x2f
+#define AKEY_r 0x28
+#define AKEY_s 0x3e
+#define AKEY_t 0x2d
+#define AKEY_u 0x0b
+#define AKEY_v 0x10
+#define AKEY_w 0x2e
+#define AKEY_x 0x16
+#define AKEY_y 0x2b
+#define AKEY_z 0x17
+
+#define AKEY_A (AKEY_SHFT | AKEY_a)
+#define AKEY_B (AKEY_SHFT | AKEY_b)
+#define AKEY_C (AKEY_SHFT | AKEY_c)
+#define AKEY_D (AKEY_SHFT | AKEY_d)
+#define AKEY_E (AKEY_SHFT | AKEY_e)
+#define AKEY_F (AKEY_SHFT | AKEY_f)
+#define AKEY_G (AKEY_SHFT | AKEY_g)
+#define AKEY_H (AKEY_SHFT | AKEY_h)
+#define AKEY_I (AKEY_SHFT | AKEY_i)
+#define AKEY_J (AKEY_SHFT | AKEY_j)
+#define AKEY_K (AKEY_SHFT | AKEY_k)
+#define AKEY_L (AKEY_SHFT | AKEY_l)
+#define AKEY_M (AKEY_SHFT | AKEY_m)
+#define AKEY_N (AKEY_SHFT | AKEY_n)
+#define AKEY_O (AKEY_SHFT | AKEY_o)
+#define AKEY_P (AKEY_SHFT | AKEY_p)
+#define AKEY_Q (AKEY_SHFT | AKEY_q)
+#define AKEY_R (AKEY_SHFT | AKEY_r)
+#define AKEY_S (AKEY_SHFT | AKEY_s)
+#define AKEY_T (AKEY_SHFT | AKEY_t)
+#define AKEY_U (AKEY_SHFT | AKEY_u)
+#define AKEY_V (AKEY_SHFT | AKEY_v)
+#define AKEY_W (AKEY_SHFT | AKEY_w)
+#define AKEY_X (AKEY_SHFT | AKEY_x)
+#define AKEY_Y (AKEY_SHFT | AKEY_y)
+#define AKEY_Z (AKEY_SHFT | AKEY_z)
+
+#define AKEY_CTRL_a (AKEY_CTRL | AKEY_a)
+#define AKEY_CTRL_b (AKEY_CTRL | AKEY_b)
+#define AKEY_CTRL_c (AKEY_CTRL | AKEY_c)
+#define AKEY_CTRL_d (AKEY_CTRL | AKEY_d)
+#define AKEY_CTRL_e (AKEY_CTRL | AKEY_e)
+#define AKEY_CTRL_f (AKEY_CTRL | AKEY_f)
+#define AKEY_CTRL_g (AKEY_CTRL | AKEY_g)
+#define AKEY_CTRL_h (AKEY_CTRL | AKEY_h)
+#define AKEY_CTRL_i (AKEY_CTRL | AKEY_i)
+#define AKEY_CTRL_j (AKEY_CTRL | AKEY_j)
+#define AKEY_CTRL_k (AKEY_CTRL | AKEY_k)
+#define AKEY_CTRL_l (AKEY_CTRL | AKEY_l)
+#define AKEY_CTRL_m (AKEY_CTRL | AKEY_m)
+#define AKEY_CTRL_n (AKEY_CTRL | AKEY_n)
+#define AKEY_CTRL_o (AKEY_CTRL | AKEY_o)
+#define AKEY_CTRL_p (AKEY_CTRL | AKEY_p)
+#define AKEY_CTRL_q (AKEY_CTRL | AKEY_q)
+#define AKEY_CTRL_r (AKEY_CTRL | AKEY_r)
+#define AKEY_CTRL_s (AKEY_CTRL | AKEY_s)
+#define AKEY_CTRL_t (AKEY_CTRL | AKEY_t)
+#define AKEY_CTRL_u (AKEY_CTRL | AKEY_u)
+#define AKEY_CTRL_v (AKEY_CTRL | AKEY_v)
+#define AKEY_CTRL_w (AKEY_CTRL | AKEY_w)
+#define AKEY_CTRL_x (AKEY_CTRL | AKEY_x)
+#define AKEY_CTRL_y (AKEY_CTRL | AKEY_y)
+#define AKEY_CTRL_z (AKEY_CTRL | AKEY_z)
+
+#define AKEY_CTRL_A (AKEY_CTRL | AKEY_A)
+#define AKEY_CTRL_B (AKEY_CTRL | AKEY_B)
+#define AKEY_CTRL_C (AKEY_CTRL | AKEY_C)
+#define AKEY_CTRL_D (AKEY_CTRL | AKEY_D)
+#define AKEY_CTRL_E (AKEY_CTRL | AKEY_E)
+#define AKEY_CTRL_F (AKEY_CTRL | AKEY_F)
+#define AKEY_CTRL_G (AKEY_CTRL | AKEY_G)
+#define AKEY_CTRL_H (AKEY_CTRL | AKEY_H)
+#define AKEY_CTRL_I (AKEY_CTRL | AKEY_I)
+#define AKEY_CTRL_J (AKEY_CTRL | AKEY_J)
+#define AKEY_CTRL_K (AKEY_CTRL | AKEY_K)
+#define AKEY_CTRL_L (AKEY_CTRL | AKEY_L)
+#define AKEY_CTRL_M (AKEY_CTRL | AKEY_M)
+#define AKEY_CTRL_N (AKEY_CTRL | AKEY_N)
+#define AKEY_CTRL_O (AKEY_CTRL | AKEY_O)
+#define AKEY_CTRL_P (AKEY_CTRL | AKEY_P)
+#define AKEY_CTRL_Q (AKEY_CTRL | AKEY_Q)
+#define AKEY_CTRL_R (AKEY_CTRL | AKEY_R)
+#define AKEY_CTRL_S (AKEY_CTRL | AKEY_S)
+#define AKEY_CTRL_T (AKEY_CTRL | AKEY_T)
+#define AKEY_CTRL_U (AKEY_CTRL | AKEY_U)
+#define AKEY_CTRL_V (AKEY_CTRL | AKEY_V)
+#define AKEY_CTRL_W (AKEY_CTRL | AKEY_W)
+#define AKEY_CTRL_X (AKEY_CTRL | AKEY_X)
+#define AKEY_CTRL_Y (AKEY_CTRL | AKEY_Y)
+#define AKEY_CTRL_Z (AKEY_CTRL | AKEY_Z)
+
+#define AKEY_HELP 0x11
+#define AKEY_DOWN 93  //  0x8f
+#define AKEY_LEFT 94  //0x86
+#define AKEY_RIGHT 95 //0x87
+#define AKEY_UP 92 //0x8e
+#define AKEY_BACKSPACE 0x34
+#define AKEY_BACKSPACE 0x34
+#define AKEY_DELETE_CHAR 0xb4
+#define AKEY_DELETE_LINE 0x74
+#define AKEY_INSERT_CHAR 0xb7
+#define AKEY_INSERT_LINE 0x77
+#define AKEY_ESCAPE 0x1c
+#define AKEY_ATARI 0x27
+#define AKEY_CAPSLOCK 0x7c
+#define AKEY_CAPSTOGGLE 0x3c
+#define AKEY_TAB 0x2c
+#define AKEY_SETTAB 0x6c
+#define AKEY_CLRTAB 0xac
+#define AKEY_RETURN 0x0c
+#define AKEY_SPACE 0x21
+#define AKEY_EXCLAMATION 0x5f
+#define AKEY_DBLQUOTE 0x5e
+#define AKEY_HASH 0x5a
+#define AKEY_DOLLAR 0x58
+#define AKEY_PERCENT 0x5d
+#define AKEY_AMPERSAND 0x5b
+#define AKEY_QUOTE 0x73
+#define AKEY_AT 0x75
+#define AKEY_PARENLEFT 0x70
+#define AKEY_PARENRIGHT 0x72
+#define AKEY_LESS 0x36
+#define AKEY_GREATER 0x37
+#define AKEY_EQUAL 0x0f
+#define AKEY_QUESTION 0x66
+#define AKEY_MINUS 0x0e
+#define AKEY_PLUS 0x06
+#define AKEY_ASTERISK 0x07
+#define AKEY_SLASH 0x26
+#define AKEY_COLON 0x42
+#define AKEY_SEMICOLON 0x02
+#define AKEY_COMMA 0x20
+#define AKEY_FULLSTOP 0x22
+#define AKEY_UNDERSCORE 0x4e
+#define AKEY_BRACKETLEFT 0x60
+#define AKEY_BRACKETRIGHT 0x62
+#define AKEY_CIRCUMFLEX 0x47
+#define AKEY_BACKSLASH 0x46
+#define AKEY_BAR 0x4f
+#define AKEY_CLEAR (AKEY_SHFT | AKEY_LESS)
+#define AKEY_CARET (AKEY_SHFT | AKEY_ASTERISK)
+#define AKEY_F1 0x03
+#define AKEY_F2 0x04
+#define AKEY_F3	0x13
+#define AKEY_F4 0x14
+
+/* Following keys cannot be read with both shift and control pressed:
+   J K L ; + * Z X C V B F1 F2 F3 F4 HELP	 */
+
+
+#endif /* AKEY_H_ */
diff --git a/MCUME_pico2/pico800/antic.c b/MCUME_pico2/pico800/antic.c
new file mode 100644
index 0000000..843d3eb
--- /dev/null
+++ b/MCUME_pico2/pico800/antic.c
@@ -0,0 +1,4150 @@
+/*
+ * antic.c - ANTIC chip emulation
+ *
+ * Copyright (C) 1995-1998 David Firth
+ * Copyright (C) 1998-2008 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+
+#include <string.h>
+
+#include "antic.h"
+#include "cpu.h"
+#include "gtia.h"
+#include "memory.h"
+#include "pokey.h"
+
+#ifdef NEW_CYCLE_EXACT
+#include "cycle_map.h"
+#endif
+
+
+UWORD Screen_atari[ATARI_WIDTH / 2]; // = NULL;
+#define scrn_line 0 //(ATARI_WIDTH / 2)
+
+#define DRAWLINE() \
+    if ( (ANTIC_ypos > 8) && (ANTIC_ypos < 248)) { \
+      emu_DrawLinePal16((unsigned char *)&Screen_atari[32/sizeof(Screen_atari[0])], 320, 240, ANTIC_ypos-8); \
+    }
+
+
+#define LCHOP 3			/* do not build leftmost 0..3 characters in wide mode */
+#define RCHOP 3			/* do not build rightmost 0..3 characters in wide mode */
+    
+int ANTIC_break_ypos = 999;
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+static int gtia_bug_active = FALSE; /* The GTIA bug mode is active */
+#endif
+#ifdef NEW_CYCLE_EXACT
+static void draw_partial_scanline(int l,int r);
+static void update_scanline_chbase(void);
+static void update_scanline_invert(void);
+static void update_scanline_blank(void);
+const int *ANTIC_cpu2antic_ptr;
+const int *ANTIC_antic2cpu_ptr;
+int ANTIC_delayed_wsync = 0;
+static int dmactl_changed = 0;
+static UBYTE delayed_DMACTL;
+static int draw_antic_ptr_changed = 0;
+static UBYTE need_load;
+static int dmactl_bug_chdata;
+#endif /* NEW_CYCLE_EXACT */
+#ifndef NO_SIMPLE_PAL_BLENDING
+int ANTIC_pal_blending = 0;
+#endif /* NO_SIMPLE_PAL_BLENDING */
+
+/* Video memory access is hidden behind these macros. It allows to track dirty video memory
+   to improve video system performance */
+#ifdef DIRTYRECT
+
+static UWORD *scratchUWordPtr;
+static UWORD scratchUWord;
+static ULONG *scratchULongPtr;
+static ULONG scratchULong;
+static UBYTE *scratchUBytePtr;
+static UBYTE scratchUByte;
+
+
+#ifdef NODIRTYCOMPARE
+
+#define WRITE_VIDEO(ptr, val) \
+	do { \
+		scratchUWordPtr = (ptr); \
+		Screen_dirty[((ULONG) scratchUWordPtr - (ULONG) Screen_atari) >> 3] = 1; \
+		*scratchUWordPtr = (val); \
+	} while (0)
+#define WRITE_VIDEO_LONG(ptr, val) \
+	do { \
+		scratchULongPtr = (ptr); \
+		Screen_dirty[((ULONG) scratchULongPtr - (ULONG) Screen_atari) >> 3] = 1; \
+		*scratchULongPtr = (val); \
+	} while (0)
+#define WRITE_VIDEO_BYTE(ptr, val) \
+	do { \
+		scratchUBytePtr = (ptr); \
+		Screen_dirty[((ULONG) scratchUBytePtr - (ULONG) Screen_atari) >> 3] = 1; \
+		*scratchUBytePtr = (val); \
+	} while (0)
+#define FILL_VIDEO(ptr, val, size) \
+	do { \
+		scratchUBytePtr = (UBYTE*) (ptr); \
+		scratchULong = (ULONG) (size); \
+		memset(Screen_dirty + (((ULONG) scratchUBytePtr - (ULONG) Screen_atari) >> 3), 1, scratchULong >> 3); \
+		memset(scratchUBytePtr, (val), scratchULong); \
+	} while (0)
+
+#else /* NODIRTYCOMPARE not defined: */
+
+#define WRITE_VIDEO(ptr, val) \
+	do { \
+		scratchUWordPtr = (ptr); \
+		scratchUWord = (val); \
+		if (*scratchUWordPtr != scratchUWord) { \
+			Screen_dirty[((ULONG) scratchUWordPtr - (ULONG) Screen_atari) >> 3] = 1; \
+			*scratchUWordPtr = scratchUWord; \
+		} \
+	} while (0)
+#ifndef WORDS_UNALIGNED_OK
+#define WRITE_VIDEO_LONG(ptr, val) \
+	do { \
+		scratchULongPtr = (ptr); \
+		scratchULong = (val); \
+		if (*scratchULongPtr != scratchULong) { \
+			Screen_dirty[((ULONG) scratchULongPtr - (ULONG) Screen_atari) >> 3] = 1; \
+			*scratchULongPtr = scratchULong; \
+		} \
+	} while (0)
+#else
+#define WRITE_VIDEO_LONG(ptr, val) \
+	do { \
+		scratchULongPtr = (ptr); \
+		scratchULong = (val); \
+		if (*scratchULongPtr != scratchULong) { \
+			Screen_dirty[((ULONG) scratchULongPtr - (ULONG) Screen_atari) >> 3] = 1; \
+			Screen_dirty[((ULONG) scratchULongPtr - (ULONG) Screen_atari + 2) >> 3] = 1; \
+			*scratchULongPtr = scratchULong; \
+		} \
+	} while (0)
+#endif
+#define WRITE_VIDEO_BYTE(ptr, val) \
+	do { \
+		scratchUBytePtr = (ptr); \
+		scratchUByte = (val); \
+		if (*scratchUBytePtr != scratchUByte) { \
+			Screen_dirty[((ULONG) scratchUBytePtr - (ULONG) Screen_atari) >> 3] = 1; \
+			*scratchUBytePtr = scratchUByte; \
+		} \
+	} while (0)
+static UBYTE *scratchFillLimit;
+#define FILL_VIDEO(ptr, val, size) \
+	do { \
+		scratchUBytePtr = (UBYTE *) (ptr); \
+		scratchUByte = (UBYTE) (val); \
+		scratchFillLimit = scratchUBytePtr + (size); \
+		for (; scratchUBytePtr < scratchFillLimit; scratchUBytePtr++) { \
+			if (*scratchUBytePtr != scratchUByte) { \
+				Screen_dirty[((ULONG) scratchUBytePtr - (ULONG) Screen_atari) >> 3] = 1; \
+				*scratchUBytePtr = scratchUByte; \
+			} \
+		} \
+	} while (0)
+
+#endif /* NODIRTYCOMPARE */
+
+#else /* DIRTYRECT not defined: */
+
+#define WRITE_VIDEO(ptr, val) (*(ptr) = val)
+#define WRITE_VIDEO_LONG(ptr, val) (*(ptr) = val)
+#define WRITE_VIDEO_BYTE(ptr, val) (*(ptr) = val)
+#define FILL_VIDEO(ptr, val, size) memset(ptr, val, size)
+
+#endif /* DIRTYRECT */
+
+#define READ_VIDEO_LONG(ptr) (*(ptr))
+
+void ANTIC_VideoMemset(UBYTE *ptr, UBYTE val, ULONG size)
+{
+	FILL_VIDEO(ptr, val, size);
+}
+
+void ANTIC_VideoPutByte(UBYTE *ptr, UBYTE val)
+{
+	WRITE_VIDEO_BYTE(ptr, val);
+}
+
+
+/* Memory access helpers----------------------------------------------------- */
+/* Some optimizations result in unaligned 32-bit accesses. These macros have
+   been introduced for machines that don't allow unaligned memory accesses. */
+
+#ifdef DIRTYRECT
+/* STAT_UNALIGNED_WORDS doesn't work with DIRTYRECT */
+#define WRITE_VIDEO_LONG_UNALIGNED  WRITE_VIDEO_LONG
+#else
+#define WRITE_VIDEO_LONG_UNALIGNED(ptr, val)  UNALIGNED_PUT_LONG((ptr), (val), Screen_atari_write_long_stat)
+#endif
+
+#ifdef WORDS_UNALIGNED_OK
+#define IS_ZERO_ULONG(x) (! UNALIGNED_GET_LONG(x, pm_scanline_read_long_stat))
+#define DO_GTIA_BYTE(p, l, x) { \
+		WRITE_VIDEO_LONG_UNALIGNED((ULONG *) (p),     (l)[(x) >> 4]); \
+		WRITE_VIDEO_LONG_UNALIGNED((ULONG *) (p) + 1, (l)[(x) & 0xf]); \
+	}
+#else /* WORDS_UNALIGNED_OK */
+#define IS_ZERO_ULONG(x) (!((const UBYTE *)(x))[0] && !((const UBYTE *)(x))[1] && !((const UBYTE *)(x))[2] && !((const UBYTE *)(x))[3])
+#define DO_GTIA_BYTE(p, l, x) { \
+		WRITE_VIDEO((UWORD *) (p),     (UWORD) ((l)[(x) >> 4])); \
+		WRITE_VIDEO((UWORD *) (p) + 1, (UWORD) ((l)[(x) >> 4])); \
+		WRITE_VIDEO((UWORD *) (p) + 2, (UWORD) ((l)[(x) & 0xf])); \
+		WRITE_VIDEO((UWORD *) (p) + 3, (UWORD) ((l)[(x) & 0xf])); \
+	}
+#endif /* WORDS_UNALIGNED_OK */
+
+/* ANTIC Registers --------------------------------------------------------- */
+
+UBYTE ANTIC_DMACTL;
+UBYTE ANTIC_CHACTL;
+UWORD ANTIC_dlist;
+UBYTE ANTIC_HSCROL;
+UBYTE ANTIC_VSCROL;
+UBYTE ANTIC_PMBASE;
+UBYTE ANTIC_CHBASE;
+UBYTE ANTIC_NMIEN;
+UBYTE ANTIC_NMIST;
+
+/* ANTIC Memory ------------------------------------------------------------ */
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+static UBYTE antic_memory[52];
+#define ANTIC_margin 4
+/* It's number of bytes in antic_memory, which are never loaded, but may be
+   read in wide playfield mode. These bytes are uninitialized, because on
+   real computer there's some kind of 'garbage'. Possibly 1 is enough, but
+   4 bytes surely won't cause negative indexes. :) */
+
+/* Screen -----------------------------------------------------------------
+   Define screen as ULONG to ensure that it is Longword aligned.
+   This allows special optimisations under certain conditions.
+   ------------------------------------------------------------------------ */
+
+static UWORD *scrn_ptr;
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+/* Separate access to XE extended memory ----------------------------------- */
+/* It's available in 130 XE and 320 KB Compy Shop.
+   Note: during ANTIC access to extended memory in Compy Shop Self Test
+   is disabled. It is unknown if this is true for real 130 XE. If not,
+   then some extra code has to be added to:
+   - check if selftest_enabled is set
+   - check if the address is in range 0x5000..0x57ff
+   - if both conditions are true, then access memory instead of ANTIC_xe_ptr */
+
+/* Pointer to 16 KB seen by ANTIC in 0x4000-0x7fff.
+   If it's the same what the CPU sees (and what's in MEMORY_mem[0x4000..0x7fff],
+   then NULL. */
+const UBYTE *ANTIC_xe_ptr = NULL;
+
+/* ANTIC Timing --------------------------------------------------------------
+
+NOTE: this information was written before NEW_CYCLE_EXACT was introduced!
+
+I've introduced global variable ANTIC_xpos, which contains current number of cycle
+in a line. This simplifies ANTIC/CPU timing much. The CPU_GO() function which
+emulates CPU is now void and is called with ANTIC_xpos limit, below which CPU can go.
+
+All strange variables holding 'unused cycles', 'DMA cycles', 'allocated cycles'
+etc. are removed. Simply whenever ANTIC fetches a byte, it takes single cycle,
+which can be done now with ANTIC_xpos++. There's only one exception: in text modes
+2-5 ANTIC takes more bytes than cycles, because it does less than ANTIC_DMAR refresh
+cycles.
+
+Now emulation is really screenline-oriented. We do ANTIC_ypos++ after a line,
+not inside it.
+
+This simplified diagram shows when what is done in a line:
+
+MDPPPPDD..............(------R/S/F------)..........
+^  ^     ^      ^     ^                     ^    ^ ^        ---> time/xpos
+0  |  NMIST_C NMI_C SCR_C                 WSYNC_C|LINE_C
+VSCON_C                                        VSCOF_C
+
+M - fetch Missiles
+D - fetch DL
+P - fetch Players
+S - fetch Screen
+F - fetch Font (in text modes)
+R - refresh Memory (ANTIC_DMAR cycles)
+
+Only Memory Refresh happens in every line, other tasks are optional.
+
+Below are exact diagrams for some non-scrolled modes:
+                                                                                                    11111111111111
+          11111111112222222222333333333344444444445555555555666666666677777777778888888888999999999900000000001111
+012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123
+                            /--------------------------narrow------------------------------\
+                    /----------------------------------normal--------------------------------------\
+            /-------------------------------------------wide--------------------------------------------\
+
+blank line:
+MDPPPPDD.................R...R...R...R...R...R...R...R...R........................................................
+
+mode 8,9:
+MDPPPPDD....S.......S....R..SR...R..SR...R..SR...R..SR...R..S.......S.......S.......S.......S.......S.............
+
+mode a,b,c:
+MDPPPPDD....S...S...S...SR..SR..SR..SR..SR..SR..SR..SR..SR..S...S...S...S...S...S...S...S...S...S...S...S.........
+
+mode d,e,f:
+MDPPPPDD....S.S.S.S.S.S.SRS.SRS.SRS.SRS.SRS.SRS.SRS.SRS.SRS.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.S.........
+
+Notes:
+* At the beginning of a line fetched are:
+  - a byte of Missiles
+  - a byte of DL (instruction)
+  - four bytes of Players
+  - two bytes of DL argument (jump or screen address)
+  The emulator, however, fetches them all continuously.
+
+* Refresh cycles and Screen/Font fetches have been tested for some modes (see above).
+  This is for making the emulator more accurate, able to change colour registers,
+  sprite positions or GTIA modes during scanline. These modes are the most commonly used
+  with those effects.
+  Currently this isn't implemented, and all R/S/F cycles are fetched continuously in *all* modes
+  (however, right number of cycles is taken in every mode, basing on screen width and HSCROL).
+
+There are a few constants representing following events:
+
+* VSCON_C - in first VSC line dctr is loaded with VSCROL
+
+* ANTIC_NMIST_C - NMIST is updated (set to 0x9f on DLI, set to 0x5f on VBLKI)
+
+* ANTIC_NMI_C - If NMIEN permits, NMI interrupt is generated
+
+* SCR_C - We draw whole line of screen. On a real computer you can change
+  ANTIC/GTIA registers while displaying screen, however this emulator
+  isn't that accurate.
+
+* ANTIC_WSYNC_C - ANTIC holds CPU until this moment, when WSYNC is written
+
+* VSCOF_C - in last VSC line dctr is compared with VSCROL
+
+* ANTIC_LINE_C - simply end of line (this used to be called CPUL)
+
+All constants are determined by tests on real Atari computer. It is assumed,
+that ANTIC registers are read with LDA, LDX, LDY and written with STA, STX,
+STY, all in absolute addressing mode. All these instructions last 4 cycles
+and perform read/write operation in last cycle. The CPU emulation should
+correctly emulate WSYNC and add cycles for current instruction BEFORE
+executing it. That's why VSCOF_C > ANTIC_LINE_C is correct.
+
+How WSYNC is now implemented:
+
+* On writing WSYNC:
+  - if ANTIC_xpos <= ANTIC_WSYNC_C && ANTIC_xpos_limit >= ANTIC_WSYNC_C,
+    we only change ANTIC_xpos to ANTIC_WSYNC_C - that's all
+  - otherwise we set ANTIC_wsync_halt and change ANTIC_xpos to ANTIC_xpos_limit causing CPU_GO()
+    to return
+
+* At the beginning of CPU_GO() (CPU emulation), when ANTIC_wsync_halt is set:
+  - if ANTIC_xpos_limit < ANTIC_WSYNC_C we return
+  - else we set ANTIC_xpos to ANTIC_WSYNC_C, reset ANTIC_wsync_halt and emulate some cycles
+
+We don't emulate ANTIC_NMIST_C, ANTIC_NMI_C and SCR_C if it is unnecessary.
+These are all cases:
+
+* Common overscreen line
+  Nothing happens except that ANTIC gets ANTIC_DMAR cycles:
+  ANTIC_xpos += ANTIC_DMAR; GOEOL;
+
+* First overscreen line - start of vertical blank
+  - CPU goes until ANTIC_NMIST_C
+  - ANTIC sets NMIST to 0x5f
+  if (ANTIC_NMIEN & 0x40) {
+      - CPU goes until ANTIC_NMI_C
+      - ANTIC forces NMI
+  }
+  - ANTIC gets ANTIC_DMAR cycles
+  - CPU goes until ANTIC_LINE_C
+
+* Screen line without DLI
+  - ANTIC fetches DL and P/MG
+  - CPU goes until SCR_C
+  - ANTIC draws whole line fetching Screen/Font and refreshing memory
+  - CPU goes until ANTIC_LINE_C
+
+* Screen line with DLI
+  - ANTIC fetches DL and P/MG
+  - CPU goes until ANTIC_NMIST_C
+  - ANTIC sets NMIST to 0x9f
+  if (ANTIC_NMIEN & 0x80) {
+      - CPU goes until ANTIC_NMI_C
+      - ANTIC forces NMI
+  }
+  - CPU goes until SCR_C
+  - ANTIC draws line with ANTIC_DMAR
+  - CPU goes until ANTIC_LINE_C
+
+  -------------------------------------------------------------------------- */
+
+#define VSCON_C	1
+#define SCR_C	28
+#define VSCOF_C	112
+
+unsigned int ANTIC_screenline_cpu_clock = 0;
+
+#ifdef NEW_CYCLE_EXACT
+#define UPDATE_DMACTL do{if (dmactl_changed) { \
+		dmactl_changed = 0; \
+		ANTIC_PutByte(ANTIC_OFFSET_DMACTL, delayed_DMACTL); \
+	} \
+	if (draw_antic_ptr_changed) { \
+		draw_antic_ptr_changed = 0; \
+		draw_antic_ptr = saved_draw_antic_ptr; \
+	}}while(0)
+#else
+#define UPDATE_DMACTL do{}while(0)
+#endif /* NEW_CYCLE_EXACT */
+#define UPDATE_GTIA_BUG /* update GTIA if it was in bug mode */\
+	do{if(gtia_bug_active) {\
+		/* restore draw_antic_ptr for multi-line modes*/\
+		draw_antic_ptr = draw_antic_table[GTIA_PRIOR >> 6][anticmode];\
+		gtia_bug_active = FALSE;\
+	}}while(0)
+#define GOEOL_CYCLE_EXACT  CPU_GO(ANTIC_antic2cpu_ptr[ANTIC_LINE_C]); \
+	ANTIC_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos]; \
+	ANTIC_xpos -= ANTIC_LINE_C; \
+	ANTIC_screenline_cpu_clock += ANTIC_LINE_C; \
+	DRAWLINE();ANTIC_ypos++; \
+	GTIA_UpdatePmplColls();
+#define GOEOL CPU_GO(ANTIC_LINE_C); ANTIC_xpos -= ANTIC_LINE_C; ANTIC_screenline_cpu_clock += ANTIC_LINE_C; UPDATE_DMACTL; DRAWLINE();ANTIC_ypos++; UPDATE_GTIA_BUG
+#define OVERSCREEN_LINE	ANTIC_xpos += ANTIC_DMAR; GOEOL
+
+int ANTIC_xpos = 0;
+int ANTIC_xpos_limit;
+int ANTIC_wsync_halt = FALSE;
+
+int ANTIC_ypos;						/* Line number - lines 8..247 are on screen */
+
+/* Timing in first line of modes 2-5
+In these modes ANTIC takes more bytes than cycles. Despite this, it would be
+possible that SCR_C + cycles_taken > ANTIC_WSYNC_C. To avoid this we must take some
+cycles before SCR_C. before_cycles contains number of them, while extra_cycles
+contains difference between bytes taken and cycles taken plus before_cycles. */
+
+#define BEFORE_CYCLES (SCR_C - 28)
+/* It's number of cycles taken before SCR_C for not scrolled, narrow playfield.
+   It wasn't tested, but should be ok. ;) */
+
+/* Light pen support ------------------------------------------------------- */
+
+static UBYTE PENH;
+static UBYTE PENV;
+UBYTE ANTIC_PENH_input = 0x00;
+UBYTE ANTIC_PENV_input = 0xff;
+
+#ifndef BASIC
+
+/* Internal ANTIC registers ------------------------------------------------ */
+
+static UWORD screenaddr;		/* Screen Pointer */
+static UBYTE IR;				/* Instruction Register */
+static UBYTE anticmode;			/* Antic mode */
+static UBYTE dctr;				/* Delta Counter */
+static UBYTE lastline;			/* dctr limit */
+static UBYTE need_dl;			/* boolean: fetch DL next line */
+static UBYTE vscrol_off;		/* boolean: displaying line ending VSC */
+
+#endif
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+
+/* Pre-computed values for improved performance ---------------------------- */
+
+#define NORMAL0 0				/* modes 2,3,4,5,0xd,0xe,0xf */
+#define NORMAL1 1				/* modes 6,7,0xa,0xb,0xc */
+#define NORMAL2 2				/* modes 8,9 */
+#define SCROLL0 3				/* modes 2,3,4,5,0xd,0xe,0xf with HSC */
+#define SCROLL1 4				/* modes 6,7,0xa,0xb,0xc with HSC */
+#define SCROLL2 5				/* modes 8,9 with HSC */
+static int md;					/* current mode NORMAL0..SCROLL2 */
+/* tables for modes NORMAL0..SCROLL2 */
+static int chars_read[6];
+static int chars_displayed[6];
+static int x_min[6];
+static int ch_offset[6];
+static int load_cycles[6];
+static int font_cycles[6];
+static int before_cycles[6];
+static int extra_cycles[6];
+
+/* border parameters for current display width */
+static int left_border_chars;
+static int right_border_start;
+#ifdef NEW_CYCLE_EXACT
+static int left_border_start = LCHOP * 4;
+static int right_border_end = (48 - RCHOP) * 4;
+#define LBORDER_START left_border_start
+#define RBORDER_END right_border_end
+#else
+#define LBORDER_START (LCHOP * 4)
+#define RBORDER_END ((48 - RCHOP) * 4)
+#endif /* NEW_CYCLE_EXACT */
+
+/* set with CHBASE *and* CHACTL - bits 0..2 set if flip on */
+static UWORD chbase_20;			/* CHBASE for 20 character mode */
+
+/* set with CHACTL */
+static UBYTE invert_mask;
+static int blank_mask;
+
+/* A scanline of AN0 and AN1 signals as transmitted from ANTIC to GTIA.
+   In every byte, bit 0 is AN0 and bit 1 is AN1 */
+static UBYTE an_scanline[ATARI_WIDTH / 2 + 8];
+
+/* lookup tables */
+static UBYTE blank_lookup[256];
+static UWORD lookup2[256];
+ULONG ANTIC_lookup_gtia9[16];
+ULONG ANTIC_lookup_gtia11[16];
+static UBYTE playfield_lookup[257];
+static UBYTE mode_e_an_lookup[256];
+
+/* Colour lookup table
+   This single table replaces 4 previously used: cl_word, cur_prior,
+   prior_table and pf_colls. It should be treated as a two-dimensional table,
+   with playfield colours in rows and PMG colours in columns:
+       no_PMG PM0 PM1 PM01 PM2 PM3 PM23 PM023 PM123 PM0123 PM25 PM35 PM235 colls ... ...
+   BAK
+   ...
+   HI2
+   HI3
+   PF0
+   PF1
+   PF2
+   PF3
+   The table contains word value (lsb = msb) of colour to be drawn.
+   The table is being updated taking current PRIOR setting into consideration.
+   '...' represent two unused columns and single unused row.
+   HI2 and HI3 are used only if colour_translation_table is being used.
+   They're colours of hi-res pixels on PF2 and PF3 respectively (PF2 is
+   default background for hi-res, PF3 is PM5).
+   Columns PM023, PM123 and PM0123 are used when PRIOR & 0xf equals any
+   of 5,7,0xc,0xd,0xe,0xf. The columns represent PM0, PM1 and PM01 respectively
+   covered by PM2 and/or PM3. This is to handle black colour on PF2 and PF3.
+   Columns PM25, PM35 and PM235 are used when PRIOR & 0x1f equals any
+   of 0x10,0x1a,0x1c,0x1e. The columns represent PM2, PM3 and PM23
+   respectively covered by PM5. This to handle colour on PF0 and PF1:
+   PF3 if (PRIOR & 0x1f) == 0x10, PF0 or PF1 otherwise.
+   Additional column 'colls' holds collisions of playfields with PMG. */
+
+UWORD ANTIC_cl[128];
+
+#define C_PM0	0x01
+#define C_PM1	0x02
+#define C_PM01	0x03
+#define C_PM2	0x04
+#define C_PM3	0x05
+#define C_PM23	0x06
+#define C_PM023	0x07
+#define C_PM123	0x08
+#define C_PM0123 0x09
+#define C_PM25	0x0a
+#define C_PM35	0x0b
+#define C_PM235	0x0c
+#define C_COLLS	0x0d
+#define C_BAK	0x00
+#define C_HI2	0x20
+#define C_HI3	0x30
+#define C_PF0	0x40
+#define C_PF1	0x50
+#define C_PF2	0x60
+#define C_PF3	0x70
+#define C_BLACK	(C_PF3 | C_PM25)
+
+/* these are byte-offsets in the table, so left shift for indexing word table
+   has been avoided */
+#define COLOUR(x) (*(UWORD *) ((UBYTE *) ANTIC_cl + (x) ))
+#define L_PM0	(2 * C_PM0)
+#define L_PM1	(2 * C_PM1)
+#define L_PM01	(2 * C_PM01)
+#define L_PM2	(2 * C_PM2)
+#define L_PM3	(2 * C_PM3)
+#define L_PM23	(2 * C_PM23)
+#define L_PM023	(2 * C_PM023)
+#define L_PM123	(2 * C_PM123)
+#define L_PM0123 (2 * C_PM0123)
+#define L_PM25	(2 * C_PM25)
+#define L_PM35	(2 * C_PM35)
+#define L_PM235	(2 * C_PM235)
+#define L_COLLS	(2 * C_COLLS)
+#define L_BAK	(2 * C_BAK)
+#define L_HI2	(2 * C_HI2)
+#define L_HI3	(2 * C_HI3)
+#define L_PF0	(2 * C_PF0)
+#define L_PF1	(2 * C_PF1)
+#define L_PF2	(2 * C_PF2)
+#define L_PF3	(2 * C_PF3)
+#define L_BLACK	(2 * C_BLACK)
+
+/* Blank areas optimizations
+   Routines for most graphics modes take advantage of fact, that often
+   large areas of screen are background colour. If it is possible, 8 pixels
+   of background are drawn at once - with two longs or four words, if
+   the platform doesn't allow unaligned long access.
+   Artifacting also uses unaligned long access if it's supported. */
+
+#ifdef WORDS_UNALIGNED_OK
+
+#define INIT_BACKGROUND_6 ULONG background = ANTIC_cl[C_PF2] | (((ULONG) ANTIC_cl[C_PF2]) << 16);
+#define INIT_BACKGROUND_8 ULONG background = ANTIC_lookup_gtia9[0];
+#define DRAW_BACKGROUND(colreg) { \
+		WRITE_VIDEO_LONG_UNALIGNED((ULONG *) ptr, background); \
+		WRITE_VIDEO_LONG_UNALIGNED(((ULONG *) ptr) + 1, background); \
+		ptr += 4; \
+	}
+#define DRAW_ARTIF { \
+		WRITE_VIDEO_LONG_UNALIGNED((ULONG *) ptr, art_curtable[(UBYTE) (screendata_tally >> 10)]); \
+		WRITE_VIDEO_LONG_UNALIGNED(((ULONG *) ptr) + 1, art_curtable[(UBYTE) (screendata_tally >> 6)]); \
+		ptr += 4; \
+	}
+
+#else
+
+#define INIT_BACKGROUND_6
+#define INIT_BACKGROUND_8
+#define DRAW_BACKGROUND(colreg) {\
+		WRITE_VIDEO(ptr,     ANTIC_cl[colreg]); \
+		WRITE_VIDEO(ptr + 1, ANTIC_cl[colreg]); \
+		WRITE_VIDEO(ptr + 2, ANTIC_cl[colreg]); \
+		WRITE_VIDEO(ptr + 3, ANTIC_cl[colreg]); \
+		ptr += 4;\
+	}
+#define DRAW_ARTIF {\
+		WRITE_VIDEO(ptr++, ((UWORD *) art_curtable)[(screendata_tally & 0x03fc00) >> 9]); \
+		WRITE_VIDEO(ptr++, ((UWORD *) art_curtable)[((screendata_tally & 0x03fc00) >> 9) + 1]); \
+		WRITE_VIDEO(ptr++, ((UWORD *) art_curtable)[(screendata_tally & 0x003fc0) >> 5]); \
+		WRITE_VIDEO(ptr++, ((UWORD *) art_curtable)[((screendata_tally & 0x003fc0) >> 5) + 1]); \
+	}
+
+#endif /* WORDS_UNALIGNED_OK */
+
+#define DRAW_ARTIF_NEW {\
+		WRITE_VIDEO(ptr++, art_lookup_new[(screendata_tally & 0x03f000) >> 12]); \
+		WRITE_VIDEO(ptr++, art_lookup_new[(screendata_tally & 0x00fc00) >> 10]); \
+		WRITE_VIDEO(ptr++, art_lookup_new[(screendata_tally & 0x003f00) >> 8]); \
+		WRITE_VIDEO(ptr++, art_lookup_new[(screendata_tally & 0x000fc0) >> 6]); \
+	}
+
+/* Hi-res modes optimizations
+   Now hi-res modes are drawn with words, not bytes. Endianess defaults
+   to little-endian. WORDS_BIGENDIAN should be defined when compiling on
+   a big-endian machine. */
+
+#ifdef WORDS_BIGENDIAN
+#define BYTE0_MASK		0xff00
+#define BYTE1_MASK		0x00ff
+#define HIRES_MASK_01	0xfff0
+#define HIRES_MASK_10	0xf0ff
+#define HIRES_LUM_01	0x000f
+#define HIRES_LUM_10	0x0f00
+#else
+#define BYTE0_MASK		0x00ff
+#define BYTE1_MASK		0xff00
+#define HIRES_MASK_01	0xf0ff
+#define HIRES_MASK_10	0xfff0
+#define HIRES_LUM_01	0x0f00
+#define HIRES_LUM_10	0x000f
+#endif
+
+static UWORD hires_lookup_n[128];
+static UWORD hires_lookup_m[128];
+#define hires_norm(x)	hires_lookup_n[(x) >> 1]
+#define hires_mask(x)	hires_lookup_m[(x) >> 1]
+
+#ifndef USE_COLOUR_TRANSLATION_TABLE
+int ANTIC_artif_new = FALSE; /* New type of artifacting */
+UWORD ANTIC_hires_lookup_l[128];	/* accessed in gtia.c */
+#define hires_lum(x)	ANTIC_hires_lookup_l[(x) >> 1]
+#endif
+
+/* Player/Missile Graphics ------------------------------------------------- */
+
+#define PF0PM (*(UBYTE *) &ANTIC_cl[C_PF0 | C_COLLS])
+#define PF1PM (*(UBYTE *) &ANTIC_cl[C_PF1 | C_COLLS])
+#define PF2PM (*(UBYTE *) &ANTIC_cl[C_PF2 | C_COLLS])
+#define PF3PM (*(UBYTE *) &ANTIC_cl[C_PF3 | C_COLLS])
+#define PF_COLLS(x) (((UBYTE *) &ANTIC_cl)[(x) + L_COLLS])
+
+static int singleline;
+int ANTIC_player_dma_enabled;
+int ANTIC_player_gra_enabled;
+int ANTIC_missile_dma_enabled;
+int ANTIC_missile_gra_enabled;
+int ANTIC_player_flickering;
+int ANTIC_missile_flickering;
+
+static UWORD pmbase_s;
+static UWORD pmbase_d;
+
+/* PMG lookup tables */
+static UBYTE pm_lookup_table[20][256];
+/* current PMG lookup table */
+static const UBYTE *pm_lookup_ptr;
+
+#define PL_00	0	/* 0x00,0x01,0x02,0x03,0x04,0x06,0x08,0x09,0x0a,0x0b */
+#define PL_05	1	/* 0x05,0x07,0x0c,0x0d,0x0e,0x0f */
+#define PL_10	2	/* 0x10,0x1a */
+#define PL_11	3	/* 0x11,0x18,0x19 */
+#define PL_12	4	/* 0x12 */
+#define PL_13	5	/* 0x13,0x1b */
+#define PL_14	6	/* 0x14,0x16 */
+#define PL_15	7	/* 0x15,0x17,0x1d,0x1f */
+#define PL_1c	8	/* 0x1c */
+#define PL_1e	9	/* 0x1e */
+#define PL_20	10	/* 0x20,0x21,0x22,0x23,0x24,0x26,0x28,0x29,0x2a,0x2b */
+#define PL_25	11	/* 0x25,0x27,0x2c,0x2d,0x2e,0x2f */
+#define PL_30	12	/* 0x30,0x3a */
+#define PL_31	13	/* 0x31,0x38,0x39 */
+#define PL_32	14	/* 0x32 */
+#define PL_33	15	/* 0x33,0x3b */
+#define PL_34	16	/* 0x34,0x36 */
+#define PL_35	17	/* 0x35,0x37,0x3d,0x3f */
+#define PL_3c	18	/* 0x3c */
+#define PL_3e	19	/* 0x3e */
+
+static const UBYTE prior_to_pm_lookup[64] = {
+	PL_00, PL_00, PL_00, PL_00, PL_00, PL_05, PL_00, PL_05,
+	PL_00, PL_00, PL_00, PL_00, PL_05, PL_05, PL_05, PL_05,
+	PL_10, PL_11, PL_12, PL_13, PL_14, PL_15, PL_14, PL_15,
+	PL_11, PL_11, PL_10, PL_13, PL_1c, PL_15, PL_1e, PL_15,
+	PL_20, PL_20, PL_20, PL_20, PL_20, PL_25, PL_20, PL_25,
+	PL_20, PL_20, PL_20, PL_20, PL_25, PL_25, PL_25, PL_25,
+	PL_30, PL_31, PL_32, PL_33, PL_34, PL_35, PL_34, PL_35,
+	PL_31, PL_31, PL_30, PL_33, PL_3c, PL_35, PL_3e, PL_35
+};
+
+static void init_pm_lookup(void)
+{
+	static const UBYTE pm_lookup_template[10][16] = {
+		/* PL_20 */
+		{ L_BAK, L_PM0, L_PM1, L_PM01, L_PM2, L_PM0, L_PM1, L_PM01,
+		L_PM3, L_PM0, L_PM1, L_PM01, L_PM23, L_PM0, L_PM1, L_PM01 },
+		/* PL_25 */
+		{ L_BAK, L_PM0, L_PM1, L_PM01, L_PM2, L_PM023, L_PM123, L_PM0123,
+		L_PM3, L_PM023, L_PM123, L_PM0123, L_PM23, L_PM023, L_PM123, L_PM0123 },
+		/* PL_30 */
+		{ L_PF3, L_PM0, L_PM1, L_PM01, L_PM25, L_PM0, L_PM1, L_PM01,
+		L_PM35, L_PM0, L_PM1, L_PM01, L_PM235, L_PM0, L_PM1, L_PM01 },
+		/* PL_31 */
+		{ L_PF3, L_PM0, L_PM1, L_PM01, L_PM2, L_PM0, L_PM1, L_PM01,
+		L_PM3, L_PM0, L_PM1, L_PM01, L_PM23, L_PM0, L_PM1, L_PM01 },
+		/* PL_32 */
+		{ L_PF3, L_PM0, L_PM1, L_PM01, L_PF3, L_PM0, L_PM1, L_PM01,
+		L_PF3, L_PM0, L_PM1, L_PM01, L_PF3, L_PM0, L_PM1, L_PM01 },
+		/* PL_33 */
+		{ L_PF3, L_PM0, L_PM1, L_PM01, L_BLACK, L_PM0, L_PM1, L_PM01,
+		L_BLACK, L_PM0, L_PM1, L_PM01, L_BLACK, L_PM0, L_PM1, L_PM01 },
+		/* PL_34 */
+		{ L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3,
+		L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3, L_PF3 },
+		/* PL_35 */
+		{ L_PF3, L_PF3, L_PF3, L_PF3, L_BLACK, L_BLACK, L_BLACK, L_BLACK,
+		L_BLACK, L_BLACK, L_BLACK, L_BLACK, L_BLACK, L_BLACK, L_BLACK, L_BLACK },
+		/* PL_3c */
+		{ L_PF3, L_PF3, L_PF3, L_PF3, L_PM25, L_PM25, L_PM25, L_PM25,
+		L_PM25, L_PM25, L_PM25, L_PM25, L_PM25, L_PM25, L_PM25, L_PM25 },
+		/* PL_3e */
+		{ L_PF3, L_PF3, L_PF3, L_PF3, L_PM25, L_BLACK, L_BLACK, L_BLACK,
+		L_PM25, L_BLACK, L_BLACK, L_BLACK, L_PM25, L_BLACK, L_BLACK, L_BLACK }
+	};
+
+	static const UBYTE multi_to_normal[] = {
+		L_BAK,
+		L_PM0, L_PM1, L_PM0,
+		L_PM2, L_PM3, L_PM2,
+		L_PM023, L_PM123, L_PM023,
+		L_PM25, L_PM35, L_PM25
+	};
+
+	int i;
+	int j;
+	UBYTE temp;
+
+	for (i = 0; i <= 1; i++)
+		for (j = 0; j <= 255; j++) {
+			pm_lookup_table[i + 10][j] = temp = pm_lookup_template[i][(j & 0xf) | (j >> 4)];
+			pm_lookup_table[i][j] = temp <= L_PM235 ? multi_to_normal[temp >> 1] : temp;
+		}
+	for (; i <= 9; i++) {
+		for (j = 0; j <= 15; j++) {
+			pm_lookup_table[i + 10][j] = temp = pm_lookup_template[i < 7 ? 0 : 1][j];
+			pm_lookup_table[i][j] = temp <= L_PM235 ? multi_to_normal[temp >> 1] : temp;
+		}
+		for (; j <= 255; j++) {
+			pm_lookup_table[i + 10][j] = temp = pm_lookup_template[i][j & 0xf];
+			pm_lookup_table[i][j] = temp <= L_PM235 ? multi_to_normal[temp >> 1] : temp;
+		}
+	}
+}
+
+static const UBYTE hold_missiles_tab[16] = {
+	0x00,0x03,0x0c,0x0f,0x30,0x33,0x3c,0x3f,
+	0xc0,0xc3,0xcc,0xcf,0xf0,0xf3,0xfc,0xff};
+
+static void pmg_dma(void)
+{
+	/* VDELAY bit set == GTIA ignores PMG DMA in even lines */
+	if (ANTIC_player_dma_enabled) {
+		if (ANTIC_player_gra_enabled) {
+			const UBYTE *base;
+			if (singleline) {
+				if (ANTIC_xe_ptr != NULL && pmbase_s < 0x8000 && pmbase_s >= 0x4000)
+					base = ANTIC_xe_ptr + pmbase_s - 0x4000 + ANTIC_ypos;
+				else
+					base = memory + pmbase_s + ANTIC_ypos;
+				if (ANTIC_ypos & 1) {
+					GTIA_GRAFP0 = base[0x400];
+					GTIA_GRAFP1 = base[0x500];
+					GTIA_GRAFP2 = base[0x600];
+					GTIA_GRAFP3 = base[0x700];
+				}
+				else {
+					if ((GTIA_VDELAY & 0x10) == 0)
+						GTIA_GRAFP0 = base[0x400];
+					if ((GTIA_VDELAY & 0x20) == 0)
+						GTIA_GRAFP1 = base[0x500];
+					if ((GTIA_VDELAY & 0x40) == 0)
+						GTIA_GRAFP2 = base[0x600];
+					if ((GTIA_VDELAY & 0x80) == 0)
+						GTIA_GRAFP3 = base[0x700];
+				}
+			}
+			else {
+				if (ANTIC_xe_ptr != NULL && pmbase_d < 0x8000 && pmbase_d >= 0x4000)
+					base = ANTIC_xe_ptr + (pmbase_d - 0x4000) + (ANTIC_ypos >> 1);
+				else
+					base = memory + pmbase_d + (ANTIC_ypos >> 1);
+				if (ANTIC_ypos & 1) {
+					GTIA_GRAFP0 = base[0x200];
+					GTIA_GRAFP1 = base[0x280];
+					GTIA_GRAFP2 = base[0x300];
+					GTIA_GRAFP3 = base[0x380];
+				}
+				else {
+					if ((GTIA_VDELAY & 0x10) == 0)
+						GTIA_GRAFP0 = base[0x200];
+					if ((GTIA_VDELAY & 0x20) == 0)
+						GTIA_GRAFP1 = base[0x280];
+					if ((GTIA_VDELAY & 0x40) == 0)
+						GTIA_GRAFP2 = base[0x300];
+					if ((GTIA_VDELAY & 0x80) == 0)
+						GTIA_GRAFP3 = base[0x380];
+				}
+			}
+		}
+		ANTIC_xpos += 4;
+	}
+	if (ANTIC_missile_dma_enabled) {
+		if (ANTIC_missile_gra_enabled) {
+			UBYTE data;
+			if (ANTIC_xe_ptr != NULL && pmbase_s < 0x8000 && pmbase_s >= 0x4000)
+				data = ANTIC_xe_ptr[singleline ? pmbase_s + ANTIC_ypos + 0x300 - 0x4000 : pmbase_d + (ANTIC_ypos >> 1) + 0x180 - 0x4000];
+			else
+				data = MEMORY_dGetByte(singleline ? pmbase_s + ANTIC_ypos + 0x300 : pmbase_d + (ANTIC_ypos >> 1) + 0x180);
+			/* in odd lines load all missiles, in even only those, for which VDELAY bit is zero */
+			GTIA_GRAFM = ANTIC_ypos & 1 ? data : ((GTIA_GRAFM ^ data) & hold_missiles_tab[GTIA_VDELAY & 0xf]) ^ data;
+		}
+		ANTIC_xpos++;
+	}
+}
+
+/* Artifacting ------------------------------------------------------------ */
+
+int ANTIC_artif_mode;
+
+static UWORD art_lookup_new[64];
+static UWORD art_colour1_new;
+static UWORD art_colour2_new;
+
+static ULONG art_lookup_normal[256];
+static ULONG art_lookup_reverse[256];
+static ULONG art_bkmask_normal[256];
+static ULONG art_lummask_normal[256];
+static ULONG art_bkmask_reverse[256];
+static ULONG art_lummask_reverse[256];
+
+static ULONG *art_curtable = art_lookup_normal;
+static ULONG *art_curbkmask = art_bkmask_normal;
+static ULONG *art_curlummask = art_lummask_normal;
+
+static UWORD art_normal_colpf1_save;
+static UWORD art_normal_colpf2_save;
+static UWORD art_reverse_colpf1_save;
+static UWORD art_reverse_colpf2_save;
+
+static void setup_art_colours(void)
+{
+	static UWORD *art_colpf1_save = &art_normal_colpf1_save;
+	static UWORD *art_colpf2_save = &art_normal_colpf2_save;
+	UWORD curlum = ANTIC_cl[C_PF1] & 0x0f0f;
+
+	if (curlum != *art_colpf1_save || ANTIC_cl[C_PF2] != *art_colpf2_save) {
+		if (curlum < (ANTIC_cl[C_PF2] & 0x0f0f)) {
+			art_colpf1_save = &art_reverse_colpf1_save;
+			art_colpf2_save = &art_reverse_colpf2_save;
+			art_curtable = art_lookup_reverse;
+			art_curlummask = art_lummask_reverse;
+			art_curbkmask = art_bkmask_reverse;
+		}
+		else {
+			art_colpf1_save = &art_normal_colpf1_save;
+			art_colpf2_save = &art_normal_colpf2_save;
+			art_curtable = art_lookup_normal;
+			art_curlummask = art_lummask_normal;
+			art_curbkmask = art_bkmask_normal;
+		}
+		if (curlum ^ *art_colpf1_save) {
+			int i;
+			ULONG new_colour = curlum ^ *art_colpf1_save;
+			new_colour |= new_colour << 16;
+			*art_colpf1_save = curlum;
+			for (i = 0; i <= 255; i++)
+				art_curtable[i] ^= art_curlummask[i] & new_colour;
+		}
+		if (ANTIC_cl[C_PF2] ^ *art_colpf2_save) {
+			int i;
+			ULONG new_colour = ANTIC_cl[C_PF2] ^ *art_colpf2_save;
+			new_colour |= new_colour << 16;
+			*art_colpf2_save = ANTIC_cl[C_PF2];
+			for (i = 0; i <= 255; i++)
+				art_curtable[i] ^= art_curbkmask[i] & new_colour;
+		}
+
+	}
+}
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+/* Initialization ---------------------------------------------------------- */
+
+int ANTIC_Initialise(void)
+{
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+#if SKIP
+	int i, j;
+
+	for (i = j = 1; i < *argc; i++) {
+		int i_a = (i + 1 < *argc);		/* is argument available? */
+		int a_m = FALSE;			/* error, argument missing! */
+		
+		if (strcmp(argv[i], "-artif") == 0) {
+			if (i_a) {
+				ANTIC_artif_mode = Util_sscandec(argv[++i]);
+				if (ANTIC_artif_mode < 0 || ANTIC_artif_mode > 4) {
+					Log_print("Invalid artifacting mode, using default.");
+					ANTIC_artif_mode = 0;
+				}
+			}
+			else a_m = TRUE;
+		}
+		else {
+			if (strcmp(argv[i], "-help") == 0) {
+				Log_print("\t-artif <num>     Set artifacting mode 0-4 (0 = disable)");
+			}
+			argv[j++] = argv[i];
+		}
+
+		if (a_m) {
+			Log_print("Missing argument for '%s'", argv[i]);
+			return FALSE;
+		}
+	}
+	*argc = j;
+#endif
+	ANTIC_UpdateArtifacting();
+
+	playfield_lookup[0x00] = L_BAK;
+	playfield_lookup[0x40] = L_PF0;
+	playfield_lookup[0x80] = L_PF1;
+	playfield_lookup[0xc0] = L_PF2;
+	playfield_lookup[0x100] = L_PF3;
+	blank_lookup[0x80] = blank_lookup[0xa0] = blank_lookup[0xc0] = blank_lookup[0xe0] = 0x00;
+	hires_mask(0x00) = 0xffff;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+	hires_mask(0x40) = BYTE0_MASK;
+	hires_mask(0x80) = BYTE1_MASK;
+	hires_mask(0xc0) = 0;
+#else
+	hires_mask(0x40) = HIRES_MASK_01;
+	hires_mask(0x80) = HIRES_MASK_10;
+	hires_mask(0xc0) = 0xf0f0;
+	hires_lum(0x00) = hires_lum(0x40) = hires_lum(0x80) = hires_lum(0xc0) = 0;
+#endif
+	init_pm_lookup();
+	mode_e_an_lookup[0] = 0;
+	mode_e_an_lookup[1] = mode_e_an_lookup[4] = mode_e_an_lookup[0x10] = mode_e_an_lookup[0x40] = 0;
+	mode_e_an_lookup[2] = mode_e_an_lookup[8] = mode_e_an_lookup[0x20] = mode_e_an_lookup[0x80] = 1;
+	mode_e_an_lookup[3] = mode_e_an_lookup[12] = mode_e_an_lookup[0x30] = mode_e_an_lookup[0xc0] = 2;
+#ifdef NEW_CYCLE_EXACT
+	CYCLE_MAP_Create();
+	ANTIC_cpu2antic_ptr = &CYCLE_MAP_cpu2antic[0];
+	ANTIC_antic2cpu_ptr = &CYCLE_MAP_antic2cpu[0];
+#endif /* NEW_CYCLE_EXACT */
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+	return TRUE;
+}
+
+void ANTIC_Reset(void)
+{
+	ANTIC_NMIEN = 0x00;
+	ANTIC_NMIST = 0x1f;
+	ANTIC_PutByte(ANTIC_OFFSET_DMACTL, 0);
+}
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+
+/* Border ------------------------------------------------------------------ */
+
+#define DO_BORDER_1 {\
+	if (IS_ZERO_ULONG(pm_scanline_ptr)) {\
+		ULONG *l_ptr = (ULONG *) ptr;\
+		WRITE_VIDEO_LONG(l_ptr++, background); \
+		WRITE_VIDEO_LONG(l_ptr++, background); \
+		ptr = (UWORD *) l_ptr;\
+		pm_scanline_ptr += 4;\
+	}\
+	else {\
+		int k = 4;\
+		do
+
+#define DO_BORDER DO_BORDER_1\
+			WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[*pm_scanline_ptr++]));\
+		while (--k);\
+	}\
+}
+
+#define DO_GTIA10_BORDER DO_BORDER_1\
+			WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[*pm_scanline_ptr++ | 1]));\
+		while (--k);\
+	}\
+}
+
+static void do_border(void)
+{
+	int kk;
+	UWORD *ptr = &scrn_ptr[LBORDER_START];
+	const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+	ULONG background = ANTIC_lookup_gtia9[0];
+	/* left border */
+	for (kk = left_border_chars; kk; kk--)
+			DO_BORDER
+	/* right border */
+	ptr = &scrn_ptr[right_border_start];
+	pm_scanline_ptr = &GTIA_pm_scanline[right_border_start];
+	while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END])
+			DO_BORDER
+}
+
+static void do_border_gtia10(void)
+{
+	int kk;
+	UWORD *ptr = &scrn_ptr[LBORDER_START];
+	const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+	ULONG background = ANTIC_cl[C_PM0] | (ANTIC_cl[C_PM0] << 16);
+	/* left border */
+	for (kk = left_border_chars; kk; kk--)
+		DO_GTIA10_BORDER
+	WRITE_VIDEO(ptr, COLOUR(pm_lookup_ptr[*pm_scanline_ptr | 1])); /* one extra pixel, because of the right shift of gtia10*/
+	/* right border */
+	pm_scanline_ptr = &GTIA_pm_scanline[right_border_start];
+	if (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END]) {
+		ptr = &scrn_ptr[right_border_start + 1]; /*start one pixel further right because of the right shift of gtia10*/
+		WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_scanline_ptr[1] | 1]));
+		WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_scanline_ptr[2] | 1]));
+		WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_scanline_ptr[3] | 1]));
+		pm_scanline_ptr += 4;
+		while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END])
+			DO_GTIA10_BORDER
+	}
+}
+
+static void do_border_gtia11(void)
+{
+	int kk;
+	UWORD *ptr = &scrn_ptr[LBORDER_START];
+	const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+	ULONG background = ANTIC_lookup_gtia11[0];
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+	ANTIC_cl[C_PF3] = colour_translation_table[GTIA_COLPF3 & 0xf0];
+#else
+	ANTIC_cl[C_PF3] &= 0xf0f0;
+#endif
+	ANTIC_cl[C_BAK] = (UWORD) background;
+	/* left border */
+	for (kk = left_border_chars; kk; kk--)
+		DO_BORDER
+	/* right border */
+	ptr = &scrn_ptr[right_border_start];
+	pm_scanline_ptr = &GTIA_pm_scanline[right_border_start];
+	while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END])
+		DO_BORDER
+	GTIA_COLOUR_TO_WORD(ANTIC_cl[C_PF3],GTIA_COLPF3)
+	GTIA_COLOUR_TO_WORD(ANTIC_cl[C_BAK],GTIA_COLBK)
+}
+
+static void draw_antic_0(void)
+{
+	UWORD *ptr = scrn_ptr + LBORDER_START;
+	if (GTIA_pm_dirty) {
+		const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+		ULONG background = ANTIC_lookup_gtia9[0];
+		do
+			DO_BORDER
+		while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END]);
+	}
+	else
+		FILL_VIDEO(ptr, ANTIC_cl[C_BAK], (RBORDER_END - LBORDER_START) * 2);
+}
+
+static void draw_antic_0_gtia10(void)
+{
+	UWORD *ptr = scrn_ptr + LBORDER_START;
+	if (GTIA_pm_dirty) {
+		const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+		ULONG background = ANTIC_cl[C_PM0] | (ANTIC_cl[C_PM0] << 16);
+		do
+			DO_GTIA10_BORDER
+		while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END]);
+	}
+	else
+		FILL_VIDEO(ptr, ANTIC_cl[C_PM0], (RBORDER_END - LBORDER_START) * 2);
+}
+
+static void draw_antic_0_gtia11(void)
+{
+	UWORD *ptr = scrn_ptr + LBORDER_START;
+	if (GTIA_pm_dirty) {
+		const UBYTE *pm_scanline_ptr = &GTIA_pm_scanline[LBORDER_START];
+		ULONG background = ANTIC_lookup_gtia11[0];
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+		ANTIC_cl[C_PF3] = colour_translation_table[GTIA_COLPF3 & 0xf0];
+#else
+		ANTIC_cl[C_PF3] &= 0xf0f0;
+#endif
+		ANTIC_cl[C_BAK] = (UWORD) background;
+		do
+			DO_BORDER
+		while (pm_scanline_ptr < &GTIA_pm_scanline[RBORDER_END]);
+		GTIA_COLOUR_TO_WORD(ANTIC_cl[C_PF3],GTIA_COLPF3)
+		GTIA_COLOUR_TO_WORD(ANTIC_cl[C_BAK],GTIA_COLBK)
+	}
+	else
+		FILL_VIDEO(ptr, ANTIC_lookup_gtia11[0], (RBORDER_END - LBORDER_START) * 2);
+}
+
+/* ANTIC modes ------------------------------------------------------------- */
+
+static const UBYTE gtia_10_lookup[] =
+{L_BAK, L_BAK, L_BAK, L_BAK, L_PF0, L_PF1, L_PF2, L_PF3,
+ L_BAK, L_BAK, L_BAK, L_BAK, L_PF0, L_PF1, L_PF2, L_PF3};
+static const UBYTE gtia_10_pm[] =
+{1, 2, 4, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+static void draw_an_gtia9(const ULONG *t_pm_scanline_ptr)
+{
+	int i = ((const UBYTE *) t_pm_scanline_ptr - GTIA_pm_scanline) & ~1;
+	while (i < right_border_start) {
+		UWORD *ptr = scrn_ptr + i;
+		int pixel = (an_scanline[i] << 2) + an_scanline[i + 1];
+		UBYTE pm_reg;
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia9[pixel]);
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			pm_reg = pm_lookup_ptr[pm_reg];
+			if (pm_reg == L_PF3) {
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+				WRITE_VIDEO(ptr, colour_translation_table[pixel | GTIA_COLPF3]);
+#else
+				WRITE_VIDEO(ptr, pixel | (pixel << 8) | ANTIC_cl[C_PF3]);
+#endif
+			}
+			else {
+				WRITE_VIDEO(ptr, COLOUR(pm_reg));
+			}
+		}
+		i++;
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			pm_reg = pm_lookup_ptr[pm_reg];
+			if (pm_reg == L_PF3) {
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+				WRITE_VIDEO(ptr + 1, colour_translation_table[pixel | GTIA_COLPF3]);
+#else
+				WRITE_VIDEO(ptr + 1, pixel | (pixel << 8) | ANTIC_cl[C_PF3]);
+#endif
+			}
+			else {
+				WRITE_VIDEO(ptr + 1, COLOUR(pm_reg));
+			}
+		}
+		i++;
+	}
+	do_border();
+}
+
+static void draw_an_gtia10(const ULONG *t_pm_scanline_ptr)
+{
+	int i = ((const UBYTE *) t_pm_scanline_ptr - GTIA_pm_scanline) | 1;
+	UWORD lookup_gtia10[16];
+	lookup_gtia10[0] = ANTIC_cl[C_PM0];
+	lookup_gtia10[1] = ANTIC_cl[C_PM1];
+	lookup_gtia10[2] = ANTIC_cl[C_PM2];
+	lookup_gtia10[3] = ANTIC_cl[C_PM3];
+	lookup_gtia10[12] = lookup_gtia10[4] = ANTIC_cl[C_PF0];
+	lookup_gtia10[13] = lookup_gtia10[5] = ANTIC_cl[C_PF1];
+	lookup_gtia10[14] = lookup_gtia10[6] = ANTIC_cl[C_PF2];
+	lookup_gtia10[15] = lookup_gtia10[7] = ANTIC_cl[C_PF3];
+	lookup_gtia10[8] = lookup_gtia10[9] = lookup_gtia10[10] = lookup_gtia10[11] = ANTIC_cl[C_BAK];
+	while (i < right_border_start) {
+		UWORD *ptr = scrn_ptr + i;
+		int pixel = (an_scanline[i - 1] << 2) + an_scanline[i];
+		UBYTE pm_reg;
+		int colreg;
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			colreg = gtia_10_lookup[pixel];
+			PF_COLLS(colreg) |= pm_reg;
+			pm_reg |= gtia_10_pm[pixel];
+			WRITE_VIDEO(ptr, COLOUR(pm_lookup_ptr[pm_reg] | colreg));
+		}
+		else {
+			WRITE_VIDEO(ptr, lookup_gtia10[pixel]);
+		}
+		i++;
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			colreg = gtia_10_lookup[pixel];
+			PF_COLLS(colreg) |= pm_reg;
+			pm_reg |= gtia_10_pm[pixel];
+			WRITE_VIDEO(ptr + 1, COLOUR(pm_lookup_ptr[pm_reg] | colreg));
+		}
+		else {
+			WRITE_VIDEO(ptr + 1, lookup_gtia10[pixel]);
+		}
+		i++;
+	}
+	do_border_gtia10();
+}
+
+static void draw_an_gtia11(const ULONG *t_pm_scanline_ptr)
+{
+	int i = ((const UBYTE *) t_pm_scanline_ptr - GTIA_pm_scanline) & ~1;
+	while (i < right_border_start) {
+		UWORD *ptr = scrn_ptr + i;
+		int pixel = (an_scanline[i] << 2) + an_scanline[i + 1];
+		UBYTE pm_reg;
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia11[pixel]);
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			pm_reg = pm_lookup_ptr[pm_reg];
+			if (pm_reg == L_PF3) {
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+				WRITE_VIDEO(ptr, colour_translation_table[pixel ? pixel | GTIA_COLPF3 : GTIA_COLPF3 & 0xf0]);
+#else
+				WRITE_VIDEO(ptr, pixel ? (pixel << 4) | (pixel << 12) | ANTIC_cl[C_PF3] : ANTIC_cl[C_PF3] & 0xf0f0);
+#endif
+			}
+			else {
+				WRITE_VIDEO(ptr, COLOUR(pm_reg));
+			}
+		}
+		i++;
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			pm_reg = pm_lookup_ptr[pm_reg];
+			if (pm_reg == L_PF3) {
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+				WRITE_VIDEO(ptr + 1, colour_translation_table[pixel ? pixel | GTIA_COLPF3 : GTIA_COLPF3 & 0xf0]);
+#else
+				WRITE_VIDEO(ptr + 1, pixel ? (pixel << 4) | (pixel << 12) | ANTIC_cl[C_PF3] : ANTIC_cl[C_PF3] & 0xf0f0);
+#endif
+			}
+			else {
+				WRITE_VIDEO(ptr + 1, COLOUR(pm_reg));
+			}
+		}
+		i++;
+	}
+	do_border_gtia11();
+}
+
+static void draw_an_gtia_bug(const ULONG *t_pm_scanline_ptr)
+{
+	static const UBYTE gtia_bug_colreg[] = {L_PF0, L_PF1, L_PF2, L_PF3};
+	UWORD lookup_gtia_bug[16];
+	int i;
+	lookup_gtia_bug[0] = ANTIC_cl[C_PF0];
+	lookup_gtia_bug[1] = ANTIC_cl[C_PF1];
+	lookup_gtia_bug[2] = ANTIC_cl[C_PF2];
+	lookup_gtia_bug[3] = ANTIC_cl[C_PF3];
+	i = ((const UBYTE *) t_pm_scanline_ptr - GTIA_pm_scanline);
+	while (i < right_border_start) {
+		UWORD *ptr = scrn_ptr + i;
+		int pixel = an_scanline[i];
+		UBYTE pm_reg;
+		int colreg;
+		pm_reg = GTIA_pm_scanline[i];
+		if (pm_reg) {
+			colreg = gtia_bug_colreg[pixel];
+			PF_COLLS(colreg) |= pm_reg;
+			WRITE_VIDEO(ptr, COLOUR(pm_lookup_ptr[pm_reg] | colreg));
+		}
+		else {
+			WRITE_VIDEO(ptr, lookup_gtia_bug[pixel]);
+		}
+		i++;
+	}
+	do_border();
+}
+
+#define DEFINE_DRAW_AN(anticmode) \
+	static void draw_antic_ ## anticmode ## _gtia9 (int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)\
+	{\
+		prepare_an_antic_ ## anticmode (nchars, antic_memptr, t_pm_scanline_ptr);\
+		draw_an_gtia9(t_pm_scanline_ptr);\
+	}\
+	static void draw_antic_ ## anticmode ## _gtia10 (int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)\
+	{\
+		prepare_an_antic_ ## anticmode (nchars, antic_memptr, t_pm_scanline_ptr);\
+		draw_an_gtia10(t_pm_scanline_ptr);\
+	}\
+	static void draw_antic_ ## anticmode ## _gtia11 (int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)\
+	{\
+		prepare_an_antic_ ## anticmode (nchars, antic_memptr, t_pm_scanline_ptr);\
+		draw_an_gtia11(t_pm_scanline_ptr);\
+	}
+
+#define CHAR_LOOP_BEGIN do {
+#define CHAR_LOOP_END } while (--nchars);
+
+#define DO_PMG_LORES PF_COLLS(colreg) |= pm_pixel = *c_pm_scanline_ptr++;\
+	WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_pixel] | colreg));
+
+#ifdef ALTERNATE_LOOP_COUNTERS 	/* speeds-up pmg in hires a bit or not? try it :) */
+#define FOUR_LOOP_BEGIN(data) data |= 0x800000; do {	/* data becomes negative after four data <<= 2 */
+#define FOUR_LOOP_END(data) } while (data >= 0);
+#else
+#define FOUR_LOOP_BEGIN(data) int k = 4; do {
+#define FOUR_LOOP_END(data) } while (--k);
+#endif
+
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+
+#define INIT_HIRES hires_norm(0x00) = ANTIC_cl[C_PF2];\
+	hires_norm(0x40) = hires_norm(0x10) = hires_norm(0x04) = (ANTIC_cl[C_PF2] & BYTE0_MASK) | (ANTIC_cl[C_HI2] & BYTE1_MASK);\
+	hires_norm(0x80) = hires_norm(0x20) = hires_norm(0x08) = (ANTIC_cl[C_HI2] & BYTE0_MASK) | (ANTIC_cl[C_PF2] & BYTE1_MASK);\
+	hires_norm(0xc0) = hires_norm(0x30) = hires_norm(0x0c) = ANTIC_cl[C_HI2];
+
+#define DO_PMG_HIRES(data) {\
+	const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;\
+	int pm_pixel;\
+	int mask;\
+	FOUR_LOOP_BEGIN(data)\
+		pm_pixel = *c_pm_scanline_ptr++;\
+		if (data & 0xc0)\
+			PF2PM |= pm_pixel;\
+		mask = hires_mask(data & 0xc0);\
+		pm_pixel = pm_lookup_ptr[pm_pixel] | L_PF2;\
+		WRITE_VIDEO(ptr++, (COLOUR(pm_pixel) & mask) | (COLOUR(pm_pixel + (L_HI2 - L_PF2)) & ~mask));\
+		data <<= 2;\
+	FOUR_LOOP_END(data)\
+}
+
+#else /* USE_COLOUR_TRANSLATION_TABLE */
+
+#define INIT_HIRES hires_norm(0x00) = ANTIC_cl[C_PF2];\
+	hires_norm(0x40) = hires_norm(0x10) = hires_norm(0x04) = (ANTIC_cl[C_PF2] & HIRES_MASK_01) | hires_lum(0x40);\
+	hires_norm(0x80) = hires_norm(0x20) = hires_norm(0x08) = (ANTIC_cl[C_PF2] & HIRES_MASK_10) | hires_lum(0x80);\
+	hires_norm(0xc0) = hires_norm(0x30) = hires_norm(0x0c) = (ANTIC_cl[C_PF2] & 0xf0f0) | hires_lum(0xc0);
+
+#define INIT_ARTIF_NEW art_lookup_new[0] = art_lookup_new[1] = art_lookup_new[2] = art_lookup_new[3] = \
+	art_lookup_new[16] = art_lookup_new[17] = art_lookup_new[18] = art_lookup_new[19] = \
+	art_lookup_new[32] = art_lookup_new[33] = art_lookup_new[34] = art_lookup_new[35] = \
+	art_lookup_new[48] = art_lookup_new[49] = art_lookup_new[50] = art_lookup_new[51] = ANTIC_cl[C_PF2];\
+	art_lookup_new[7] = art_lookup_new[23] = art_lookup_new[39] = art_lookup_new[55] = (ANTIC_cl[C_PF2] & HIRES_MASK_01) | hires_lum(0x40);\
+	art_lookup_new[56] = art_lookup_new[57] = art_lookup_new[58] = art_lookup_new[59] = (ANTIC_cl[C_PF2] & HIRES_MASK_10) | hires_lum(0x80);\
+	art_lookup_new[12] = art_lookup_new[13] = art_lookup_new[14] = art_lookup_new[15] = \
+	art_lookup_new[28] = art_lookup_new[29] = art_lookup_new[30] = art_lookup_new[31] = \
+	art_lookup_new[44] = art_lookup_new[45] = art_lookup_new[46] = art_lookup_new[47] = \
+	art_lookup_new[60] = art_lookup_new[61] = art_lookup_new[62] = art_lookup_new[63] = (ANTIC_cl[C_PF2] & 0xf0f0) | hires_lum(0xc0);\
+	if ((ANTIC_cl[C_PF2] & 0x0F00) != (ANTIC_cl[C_PF1] & 0x0F00)) { \
+		art_lookup_new[4] = art_lookup_new[5] = art_lookup_new[36] = art_lookup_new[37] = \
+		art_lookup_new[52] = art_lookup_new[53 ]= ((art_colour1_new & BYTE1_MASK & ~(HIRES_LUM_01))) | hires_lum(0x40) | (ANTIC_cl[C_PF2] & BYTE0_MASK);\
+		art_lookup_new[20] = art_lookup_new[21] = (art_colour1_new & 0xf0f0) | hires_lum(0xc0);\
+		art_lookup_new[8] = art_lookup_new[9] = art_lookup_new[11] = art_lookup_new[40] = \
+		art_lookup_new[43] = ((art_colour2_new & BYTE0_MASK & ~(HIRES_LUM_10))) | hires_lum(0x80) | (ANTIC_cl[C_PF2] & BYTE1_MASK);\
+		art_lookup_new[10] = art_lookup_new[41] = art_lookup_new[42] = (art_colour2_new & 0xf0f0) | hires_lum(0xc0);\
+		}\
+	else {\
+		art_lookup_new[4] = art_lookup_new[5] = art_lookup_new[36] = art_lookup_new[37] = \
+		art_lookup_new[52] = art_lookup_new[53 ]= art_lookup_new[20] = art_lookup_new[21] = \
+		art_lookup_new[8] = art_lookup_new[9] = art_lookup_new[11] = art_lookup_new[40] = \
+		art_lookup_new[43] = art_lookup_new[10] = art_lookup_new[41] = art_lookup_new[42] = ANTIC_cl[C_PF2];\
+		}\
+	art_lookup_new[6] = art_lookup_new[22] = art_lookup_new[38] = art_lookup_new[54] = (ANTIC_cl[C_PF2] & HIRES_MASK_01) | hires_lum(0x40);\
+	art_lookup_new[24] = art_lookup_new[25] = art_lookup_new[26] = art_lookup_new[27] = (ANTIC_cl[C_PF2] & HIRES_MASK_10) | hires_lum(0x80);
+
+#define DO_PMG_HIRES(data) {\
+	const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;\
+	int pm_pixel;\
+	FOUR_LOOP_BEGIN(data)\
+		pm_pixel = *c_pm_scanline_ptr++;\
+		if (data & 0xc0)\
+			PF2PM |= pm_pixel;\
+		WRITE_VIDEO(ptr++, (COLOUR(pm_lookup_ptr[pm_pixel] | L_PF2) & hires_mask(data & 0xc0)) | hires_lum(data & 0xc0));\
+		data <<= 2;\
+	FOUR_LOOP_END(data)\
+}
+
+#define DO_PMG_HIRES_NEW(data, tally) {\
+	const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;\
+	int pm_pixel;\
+	FOUR_LOOP_BEGIN(data)\
+		pm_pixel = *c_pm_scanline_ptr++;\
+		if (pm_pixel) \
+			WRITE_VIDEO(ptr++, (COLOUR(pm_lookup_ptr[pm_pixel] | L_PF2)));\
+		else\
+			WRITE_VIDEO(ptr++, art_lookup_new[(tally & 0xfc0000) >> 18]); \
+		data <<= 2;\
+		tally <<= 6;\
+	FOUR_LOOP_END(data)\
+}
+
+#endif /* USE_COLOUR_TRANSLATION_TABLE */
+
+#ifdef NEW_CYCLE_EXACT
+#define ADD_FONT_CYCLES
+#else
+#define ADD_FONT_CYCLES ANTIC_xpos += font_cycles[md]
+#endif
+
+#ifdef PAGED_MEM
+
+#define INIT_ANTIC_2	int t_chbase = (dctr ^ chbase_20) & 0xfc07;\
+	ADD_FONT_CYCLES;\
+	blank_lookup[0x60] = (anticmode == 2 || dctr & 0xe) ? 0xff : 0;\
+	blank_lookup[0x00] = blank_lookup[0x20] = blank_lookup[0x40] = (dctr & 0xe) == 8 ? 0 : 0xff;
+
+#define GET_CHDATA_ANTIC_2	chdata = (screendata & invert_mask) ? 0xff : 0;\
+	if (blank_lookup[screendata & blank_mask])\
+		chdata ^= MEMORY_dGetByte(t_chbase + ((UWORD) (screendata & 0x7f) << 3));
+
+#else /* PAGED_MEM */
+
+#define INIT_ANTIC_2	const UBYTE *chptr;\
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)\
+		chptr = ANTIC_xe_ptr + ((dctr ^ chbase_20) & 0x3c07);\
+	else\
+		chptr = MEMORY_mem + ((dctr ^ chbase_20) & 0xfc07);\
+	ADD_FONT_CYCLES;\
+	blank_lookup[0x60] = (anticmode == 2 || dctr & 0xe) ? 0xff : 0;\
+	blank_lookup[0x00] = blank_lookup[0x20] = blank_lookup[0x40] = (dctr & 0xe) == 8 ? 0 : 0xff;
+
+#define GET_CHDATA_ANTIC_2	chdata = (screendata & invert_mask) ? 0xff : 0;\
+	if (blank_lookup[screendata & blank_mask])\
+		chdata ^= chptr[(screendata & 0x7f) << 3];
+
+#endif /* PAGED_MEM */
+
+static void draw_antic_2(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_BACKGROUND_6
+	INIT_ANTIC_2
+	INIT_HIRES
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int chdata;
+
+		GET_CHDATA_ANTIC_2
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			if (chdata) {
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0xc0));
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0x30));
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0x0c));
+				WRITE_VIDEO(ptr++, hires_norm((chdata & 0x03) << 2));
+			}
+			else
+				DRAW_BACKGROUND(C_PF2)
+		}
+		else
+			DO_PMG_HIRES(chdata)
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+#ifdef NEW_CYCLE_EXACT
+static void draw_antic_2_dmactl_bug(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_BACKGROUND_6
+	INIT_ANTIC_2
+	(void)chptr; /* suppress GCC -Wunused-but-set-variable warning */
+	INIT_HIRES
+
+	CHAR_LOOP_BEGIN
+		/* UBYTE screendata = *antic_memptr++; */
+
+/* In this glitched mode, the output depends on the MSB of the last char */
+/* drawn in the previous line, and invert_mask.  It seems to reveal that */
+/* ANTIC has a latch that is set by the MSB of the char that controls an */
+/* invert gate. */
+/* When this gate was set on the last line and the next line is glitched */
+/* it remains set and the whole line appears inverted */
+/* We'll use this modeline to draw antic f glitched as well, and set */
+/* dmactl_bug_chdata to 0 */
+		int chdata = (dmactl_bug_chdata & invert_mask) ? 0xff : 0;
+		/* GET_CHDATA_ANTIC_2 */
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+
+			if (chdata) {
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0xc0));
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0x30));
+				WRITE_VIDEO(ptr++, hires_norm(chdata & 0x0c));
+				WRITE_VIDEO(ptr++, hires_norm((chdata & 0x03) << 2));
+			}
+			else
+				DRAW_BACKGROUND(C_PF2)
+		}
+		else
+			DO_PMG_HIRES(chdata)
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+#endif
+
+static void draw_antic_2_artif(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	ULONG screendata_tally;
+	INIT_ANTIC_2
+	{
+		UBYTE screendata = *antic_memptr++;
+		UBYTE chdata;
+		GET_CHDATA_ANTIC_2
+		screendata_tally = chdata;
+	}
+	setup_art_colours();
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		ULONG chdata;
+
+		GET_CHDATA_ANTIC_2
+		screendata_tally <<= 8;
+		screendata_tally |= chdata;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			DRAW_ARTIF
+		else {
+			chdata = screendata_tally >> 8;
+			DO_PMG_HIRES(chdata)
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+#ifndef USE_COLOUR_TRANSLATION_TABLE
+static void draw_antic_2_artif_new(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	ULONG screendata_tally;
+	ULONG pmtally;
+	UBYTE screendata = *antic_memptr++;
+	UBYTE chdata;
+	INIT_ANTIC_2
+	INIT_ARTIF_NEW
+	GET_CHDATA_ANTIC_2
+	screendata_tally = chdata;
+	setup_art_colours();
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		ULONG chdata;
+
+		GET_CHDATA_ANTIC_2
+		screendata_tally <<= 8;
+		screendata_tally |= chdata;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			DRAW_ARTIF_NEW
+		else {
+			chdata = screendata_tally >> 8;
+			pmtally = ((screendata_tally & 0x03f000) << 6) |
+					  ((screendata_tally & 0x00fc00) << 2) |
+					  ((screendata_tally & 0x003f00) >> 2) |
+					  ((screendata_tally & 0x000fc0) >> 6);
+			DO_PMG_HIRES_NEW(chdata,pmtally)
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+#endif
+
+static void prepare_an_antic_2(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+#ifdef PAGED_MEM
+	int t_chbase = (dctr ^ chbase_20) & 0xfc07;
+#else
+	const UBYTE *chptr;
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)
+		chptr = ANTIC_xe_ptr + ((dctr ^ chbase_20) & 0x3c07);
+	else
+		chptr = MEMORY_mem + ((dctr ^ chbase_20) & 0xfc07);
+#endif
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int chdata;
+		GET_CHDATA_ANTIC_2
+		*an_ptr++ = chdata >> 6;
+		*an_ptr++ = (chdata >> 4) & 3;
+		*an_ptr++ = (chdata >> 2) & 3;
+		*an_ptr++ = chdata & 3;
+	CHAR_LOOP_END
+}
+
+static void draw_antic_2_gtia9(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_ANTIC_2
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_2(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia9(t_pm_scanline_ptr);
+		return;
+	}
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int chdata;
+
+		GET_CHDATA_ANTIC_2
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia9[chdata >> 4]);
+		WRITE_VIDEO_LONG((ULONG *) ptr + 1, ANTIC_lookup_gtia9[chdata & 0xf]);
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			ptr += 4;
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int k = 4;
+			UBYTE pm_reg;
+			do {
+				pm_reg = pm_lookup_ptr[*c_pm_scanline_ptr++];
+				if (pm_reg) {
+					if (pm_reg == L_PF3) {
+						UBYTE tmp = k > 2 ? chdata >> 4 : chdata & 0xf;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+						WRITE_VIDEO(ptr, colour_translation_table[tmp | GTIA_COLPF3]);
+#else
+						WRITE_VIDEO(ptr, tmp | ((UWORD)tmp << 8) | ANTIC_cl[C_PF3]);
+#endif
+					}
+					else
+					{
+						WRITE_VIDEO(ptr, COLOUR(pm_reg));
+					}
+				}
+				ptr++;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void draw_antic_2_gtia10(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+#ifdef WORDS_UNALIGNED_OK
+	ULONG lookup_gtia10[16];
+#else
+	UWORD lookup_gtia10[16];
+#endif
+	INIT_ANTIC_2
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_2(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia10(t_pm_scanline_ptr);
+		return;
+	}
+
+#ifdef WORDS_UNALIGNED_OK
+	lookup_gtia10[0] = ANTIC_cl[C_PM0] | (ANTIC_cl[C_PM0] << 16);
+	lookup_gtia10[1] = ANTIC_cl[C_PM1] | (ANTIC_cl[C_PM1] << 16);
+	lookup_gtia10[2] = ANTIC_cl[C_PM2] | (ANTIC_cl[C_PM2] << 16);
+	lookup_gtia10[3] = ANTIC_cl[C_PM3] | (ANTIC_cl[C_PM3] << 16);
+	lookup_gtia10[12] = lookup_gtia10[4] = ANTIC_cl[C_PF0] | (ANTIC_cl[C_PF0] << 16);
+	lookup_gtia10[13] = lookup_gtia10[5] = ANTIC_cl[C_PF1] | (ANTIC_cl[C_PF1] << 16);
+	lookup_gtia10[14] = lookup_gtia10[6] = ANTIC_cl[C_PF2] | (ANTIC_cl[C_PF2] << 16);
+	lookup_gtia10[15] = lookup_gtia10[7] = ANTIC_cl[C_PF3] | (ANTIC_cl[C_PF3] << 16);
+	lookup_gtia10[8] = lookup_gtia10[9] = lookup_gtia10[10] = lookup_gtia10[11] = ANTIC_lookup_gtia9[0];
+#else
+	lookup_gtia10[0] = ANTIC_cl[C_PM0];
+	lookup_gtia10[1] = ANTIC_cl[C_PM1];
+	lookup_gtia10[2] = ANTIC_cl[C_PM2];
+	lookup_gtia10[3] = ANTIC_cl[C_PM3];
+	lookup_gtia10[12] = lookup_gtia10[4] = ANTIC_cl[C_PF0];
+	lookup_gtia10[13] = lookup_gtia10[5] = ANTIC_cl[C_PF1];
+	lookup_gtia10[14] = lookup_gtia10[6] = ANTIC_cl[C_PF2];
+	lookup_gtia10[15] = lookup_gtia10[7] = ANTIC_cl[C_PF3];
+	lookup_gtia10[8] = lookup_gtia10[9] = lookup_gtia10[10] = lookup_gtia10[11] = ANTIC_cl[C_BAK];
+#endif
+	ptr++;
+	t_pm_scanline_ptr = (const ULONG *) (((const UBYTE *) t_pm_scanline_ptr) + 1);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int chdata;
+
+		GET_CHDATA_ANTIC_2
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			DO_GTIA_BYTE(ptr, lookup_gtia10, chdata)
+			ptr += 4;
+		}
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int pm_pixel;
+			int colreg;
+			int k = 4;
+			UBYTE t_screendata = chdata >> 4;
+			do {
+				colreg = gtia_10_lookup[t_screendata];
+				PF_COLLS(colreg) |= pm_pixel = *c_pm_scanline_ptr++;
+				pm_pixel |= gtia_10_pm[t_screendata];
+				WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_pixel] | colreg));
+				if (k == 3)
+					t_screendata = chdata & 0x0f;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border_gtia10();
+}
+
+static void draw_antic_2_gtia11(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_ANTIC_2
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_2(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia11(t_pm_scanline_ptr);
+		return;
+	}
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int chdata;
+
+		GET_CHDATA_ANTIC_2
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia11[chdata >> 4]);
+		WRITE_VIDEO_LONG((ULONG *) ptr + 1, ANTIC_lookup_gtia11[chdata & 0xf]);
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			ptr += 4;
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int k = 4;
+			UBYTE pm_reg;
+			do {
+				pm_reg = pm_lookup_ptr[*c_pm_scanline_ptr++];
+				if (pm_reg) {
+					if (pm_reg == L_PF3) {
+						UBYTE tmp = k > 2 ? chdata & 0xf0 : chdata << 4;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+						WRITE_VIDEO(ptr, colour_translation_table[tmp ? tmp | GTIA_COLPF3 : GTIA_COLPF3 & 0xf0]);
+#else
+						WRITE_VIDEO(ptr, tmp ? tmp | ((UWORD)tmp << 8) | ANTIC_cl[C_PF3] : ANTIC_cl[C_PF3] & 0xf0f0);
+#endif
+					}
+					else
+					{
+						WRITE_VIDEO(ptr, COLOUR(pm_reg));
+					}
+				}
+				ptr++;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border_gtia11();
+}
+
+static void draw_antic_2_gtia_bug(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	prepare_an_antic_2(nchars, antic_memptr, t_pm_scanline_ptr);
+	draw_an_gtia_bug(t_pm_scanline_ptr);
+	return;
+}
+
+static void draw_antic_4(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_BACKGROUND_8
+#ifdef PAGED_MEM
+	UWORD t_chbase = ((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0xfc07;
+#else
+	const UBYTE *chptr;
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)
+		chptr = ANTIC_xe_ptr + (((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0x3c07);
+	else
+		chptr = MEMORY_mem + (((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0xfc07);
+#endif
+
+	ADD_FONT_CYCLES;
+	lookup2[0x0f] = lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x4f] = lookup2[0x1f] = lookup2[0x13] =
+	lookup2[0x40] = lookup2[0x10] = lookup2[0x04] = lookup2[0x01] = ANTIC_cl[C_PF0];
+	lookup2[0x8f] = lookup2[0x2f] = lookup2[0x17] = lookup2[0x11] =
+	lookup2[0x80] = lookup2[0x20] = lookup2[0x08] = lookup2[0x02] = ANTIC_cl[C_PF1];
+	lookup2[0xc0] = lookup2[0x30] = lookup2[0x0c] = lookup2[0x03] = ANTIC_cl[C_PF2];
+	lookup2[0xcf] = lookup2[0x3f] = lookup2[0x1b] = lookup2[0x12] = ANTIC_cl[C_PF3];
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		const UWORD *lookup;
+		UBYTE chdata;
+		if (screendata & 0x80)
+			lookup = lookup2 + 0xf;
+		else
+			lookup = lookup2;
+#ifdef PAGED_MEM
+		chdata = MEMORY_dGetByte(t_chbase + ((UWORD) (screendata & 0x7f) << 3));
+#else
+		chdata = chptr[(screendata & 0x7f) << 3];
+#endif
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			if (chdata) {
+				WRITE_VIDEO(ptr++, lookup[chdata & 0xc0]);
+				WRITE_VIDEO(ptr++, lookup[chdata & 0x30]);
+				WRITE_VIDEO(ptr++, lookup[chdata & 0x0c]);
+				WRITE_VIDEO(ptr++, lookup[chdata & 0x03]);
+			}
+			else
+				DRAW_BACKGROUND(C_BAK)
+		}
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int pm_pixel;
+			int colreg;
+			int k = 4;
+			playfield_lookup[0xc0] = screendata & 0x80 ? L_PF3 : L_PF2;
+			do {
+				colreg = playfield_lookup[chdata & 0xc0];
+				DO_PMG_LORES
+				chdata <<= 2;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	playfield_lookup[0xc0] = L_PF2;
+	do_border();
+}
+
+static void prepare_an_antic_4(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+#ifdef PAGED_MEM
+	UWORD t_chbase = ((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0xfc07;
+#else
+	const UBYTE *chptr;
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)
+		chptr = ANTIC_xe_ptr + (((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0x3c07);
+	else
+		chptr = MEMORY_mem + (((anticmode == 4 ? dctr : dctr >> 1) ^ chbase_20) & 0xfc07);
+#endif
+
+	ADD_FONT_CYCLES;
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		UBYTE an;
+		UBYTE chdata;
+#ifdef PAGED_MEM
+		chdata = MEMORY_dGetByte(t_chbase + ((UWORD) (screendata & 0x7f) << 3));
+#else
+		chdata = chptr[(screendata & 0x7f) << 3];
+#endif
+		an = mode_e_an_lookup[chdata & 0xc0];
+		*an_ptr++ = (an == 2 && screendata & 0x80) ? 3 : an;
+		an = mode_e_an_lookup[chdata & 0x30];
+		*an_ptr++ = (an == 2 && screendata & 0x80) ? 3 : an;
+		an = mode_e_an_lookup[chdata & 0x0c];
+		*an_ptr++ = (an == 2 && screendata & 0x80) ? 3 : an;
+		an = mode_e_an_lookup[chdata & 0x03];
+		*an_ptr++ = (an == 2 && screendata & 0x80) ? 3 : an;
+	CHAR_LOOP_END
+}
+
+DEFINE_DRAW_AN(4)
+
+static void draw_antic_6(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+#ifdef PAGED_MEM
+	UWORD t_chbase = (anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20;
+#else
+	const UBYTE *chptr;
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)
+		chptr = ANTIC_xe_ptr + (((anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20) - 0x4000);
+	else
+		chptr = MEMORY_mem + ((anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20);
+#endif
+
+	ADD_FONT_CYCLES;
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		UBYTE chdata;
+		UWORD colour;
+		int kk = 2;
+		colour = COLOUR((playfield_lookup + 0x40)[screendata & 0xc0]);
+#ifdef PAGED_MEM
+		chdata = MEMORY_dGetByte(t_chbase + ((UWORD) (screendata & 0x3f) << 3));
+#else
+		chdata = chptr[(screendata & 0x3f) << 3];
+#endif
+		do {
+			if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+				if (chdata & 0xf0) {
+					if (chdata & 0x80) {
+						WRITE_VIDEO(ptr++, colour);
+					}
+					else {
+						WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					}
+					if (chdata & 0x40) {
+						WRITE_VIDEO(ptr++, colour);
+					}
+					else {
+						WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					}
+					if (chdata & 0x20) {
+						WRITE_VIDEO(ptr++, colour);
+					}
+					else {
+						WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					}
+					if (chdata & 0x10) {
+						WRITE_VIDEO(ptr++, colour);
+					}
+					else {
+						WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					}
+				}
+				else {
+					WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+					WRITE_VIDEO(ptr++, ANTIC_cl[C_BAK]);
+				}
+				chdata <<= 4;
+			}
+			else {
+				const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+				int pm_pixel;
+				UBYTE setcol = (playfield_lookup + 0x40)[screendata & 0xc0];
+				int colreg;
+				int k = 4;
+				do {
+					colreg = chdata & 0x80 ? setcol : L_BAK;
+					DO_PMG_LORES
+					chdata <<= 1;
+				} while (--k);
+
+			}
+			t_pm_scanline_ptr++;
+		} while (--kk);
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void prepare_an_antic_6(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+#ifdef PAGED_MEM
+	UWORD t_chbase = (anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20;
+#else
+	const UBYTE *chptr;
+	if (ANTIC_xe_ptr != NULL && chbase_20 < 0x8000 && chbase_20 >= 0x4000)
+		chptr = ANTIC_xe_ptr + (((anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20) - 0x4000);
+	else
+		chptr = MEMORY_mem + ((anticmode == 6 ? dctr & 7 : dctr >> 1) ^ chbase_20);
+#endif
+
+	ADD_FONT_CYCLES;
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		UBYTE an = screendata >> 6;
+		UBYTE chdata;
+#ifdef PAGED_MEM
+		chdata = MEMORY_dGetByte(t_chbase + ((UWORD) (screendata & 0x3f) << 3));
+#else
+		chdata = chptr[(screendata & 0x3f) << 3];
+#endif
+		*an_ptr++ = chdata & 0x80 ? an : 0;
+		*an_ptr++ = chdata & 0x40 ? an : 0;
+		*an_ptr++ = chdata & 0x20 ? an : 0;
+		*an_ptr++ = chdata & 0x10 ? an : 0;
+		*an_ptr++ = chdata & 0x08 ? an : 0;
+		*an_ptr++ = chdata & 0x04 ? an : 0;
+		*an_ptr++ = chdata & 0x02 ? an : 0;
+		*an_ptr++ = chdata & 0x01 ? an : 0;
+	CHAR_LOOP_END
+}
+
+DEFINE_DRAW_AN(6)
+
+static void draw_antic_8(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x40] = ANTIC_cl[C_PF0];
+	lookup2[0x80] = ANTIC_cl[C_PF1];
+	lookup2[0xc0] = ANTIC_cl[C_PF2];
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int kk = 4;
+		do {
+			if ((const UBYTE *) t_pm_scanline_ptr >= GTIA_pm_scanline + 4 * (48 - RCHOP))
+				break;
+			if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+				UWORD data = lookup2[screendata & 0xc0];
+				WRITE_VIDEO(ptr++, data);
+				WRITE_VIDEO(ptr++, data);
+				WRITE_VIDEO(ptr++, data);
+				WRITE_VIDEO(ptr++, data);
+			}
+			else {
+				const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+				int pm_pixel;
+				int colreg = playfield_lookup[screendata & 0xc0];
+				int k = 4;
+				do {
+					DO_PMG_LORES
+				} while (--k);
+			}
+			screendata <<= 2;
+			t_pm_scanline_ptr++;
+		} while (--kk);
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void prepare_an_antic_8(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int kk = 4;
+		do {
+			UBYTE data = mode_e_an_lookup[screendata & 0xc0];
+			*an_ptr++ = data;
+			*an_ptr++ = data;
+			*an_ptr++ = data;
+			*an_ptr++ = data;
+			screendata <<= 2;
+		} while (--kk);
+	CHAR_LOOP_END
+}
+
+DEFINE_DRAW_AN(8)
+
+static void draw_antic_9(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x80] = lookup2[0x40] = ANTIC_cl[C_PF0];
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int kk = 4;
+		do {
+			if ((const UBYTE *) t_pm_scanline_ptr >= GTIA_pm_scanline + 4 * (48 - RCHOP))
+				break;
+			if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x80]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x80]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x40]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x40]);
+				screendata <<= 2;
+			}
+			else {
+				const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+				int pm_pixel;
+				int colreg;
+				int k = 4;
+				do {
+					colreg = (screendata & 0x80) ? L_PF0 : L_BAK;
+					DO_PMG_LORES
+					if (k & 0x01)
+						screendata <<= 1;
+				} while (--k);
+			}
+			t_pm_scanline_ptr++;
+		} while (--kk);
+	CHAR_LOOP_END
+	do_border();
+}
+
+/* ANTIC modes 9, b and c use BAK and PF0 colours only so they're not visible in GTIA modes */
+
+static void draw_antic_9_gtia9(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	draw_antic_0();
+}
+
+static void draw_antic_9_gtia10(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	draw_antic_0_gtia10();
+}
+
+static void draw_antic_9_gtia11(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	draw_antic_0_gtia11();
+}
+
+static void draw_antic_a(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x40] = lookup2[0x10] = ANTIC_cl[C_PF0];
+	lookup2[0x80] = lookup2[0x20] = ANTIC_cl[C_PF1];
+	lookup2[0xc0] = lookup2[0x30] = ANTIC_cl[C_PF2];
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int kk = 2;
+		do {
+			if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0xc0]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0xc0]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x30]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x30]);
+				screendata <<= 4;
+			}
+			else {
+				const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+				int pm_pixel;
+				int colreg;
+				int k = 4;
+				do {
+					colreg = playfield_lookup[screendata & 0xc0];
+					DO_PMG_LORES
+					if (k & 0x01)
+						screendata <<= 2;
+				} while (--k);
+			}
+			t_pm_scanline_ptr++;
+		} while (--kk);
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void prepare_an_antic_a(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		UBYTE data = mode_e_an_lookup[screendata & 0xc0];
+		*an_ptr++ = data;
+		*an_ptr++ = data;
+		data = mode_e_an_lookup[screendata & 0x30];
+		*an_ptr++ = data;
+		*an_ptr++ = data;
+		data = mode_e_an_lookup[screendata & 0x0c];
+		*an_ptr++ = data;
+		*an_ptr++ = data;
+		data = mode_e_an_lookup[screendata & 0x03];
+		*an_ptr++ = data;
+		*an_ptr++ = data;
+	CHAR_LOOP_END
+}
+
+DEFINE_DRAW_AN(a)
+
+static void draw_antic_c(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x80] = lookup2[0x40] = lookup2[0x20] = lookup2[0x10] = ANTIC_cl[C_PF0];
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		int kk = 2;
+		do {
+			if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x80]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x40]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x20]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x10]);
+				screendata <<= 4;
+			}
+			else {
+				const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+				int pm_pixel;
+				int colreg;
+				int k = 4;
+				do {
+					colreg = (screendata & 0x80) ? L_PF0 : L_BAK;
+					DO_PMG_LORES
+					screendata <<= 1;
+				} while (--k);
+			}
+			t_pm_scanline_ptr++;
+		} while (--kk);
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void draw_antic_e(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_BACKGROUND_8
+	lookup2[0x00] = ANTIC_cl[C_BAK];
+	lookup2[0x40] = lookup2[0x10] = lookup2[0x04] = lookup2[0x01] = ANTIC_cl[C_PF0];
+	lookup2[0x80] = lookup2[0x20] = lookup2[0x08] = lookup2[0x02] = ANTIC_cl[C_PF1];
+	lookup2[0xc0] = lookup2[0x30] = lookup2[0x0c] = lookup2[0x03] = ANTIC_cl[C_PF2];
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			if (screendata) {
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0xc0]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x30]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x0c]);
+				WRITE_VIDEO(ptr++, lookup2[screendata & 0x03]);
+			}
+			else
+				DRAW_BACKGROUND(C_BAK)
+		}
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int pm_pixel;
+			int colreg;
+			int k = 4;
+			do {
+				colreg = playfield_lookup[screendata & 0xc0];
+				DO_PMG_LORES
+				screendata <<= 2;
+			} while (--k);
+
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void prepare_an_antic_e(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		*an_ptr++ = mode_e_an_lookup[screendata & 0xc0];
+		*an_ptr++ = mode_e_an_lookup[screendata & 0x30];
+		*an_ptr++ = mode_e_an_lookup[screendata & 0x0c];
+		*an_ptr++ = mode_e_an_lookup[screendata & 0x03];
+	CHAR_LOOP_END
+}
+
+static void draw_antic_e_gtia9(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	ULONG lookup[16];
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_e(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia9(t_pm_scanline_ptr);
+		return;
+	}
+	lookup[0] = lookup[1] = lookup[4] = lookup[5] = ANTIC_lookup_gtia9[0];
+	lookup[2] = lookup[6] = ANTIC_lookup_gtia9[1];
+	lookup[3] = lookup[7] = ANTIC_lookup_gtia9[2];
+	lookup[8] = lookup[9] = ANTIC_lookup_gtia9[4];
+	lookup[10] = ANTIC_lookup_gtia9[5];
+	lookup[11] = ANTIC_lookup_gtia9[6];
+	lookup[12] = lookup[13] = ANTIC_lookup_gtia9[8];
+	lookup[14] = ANTIC_lookup_gtia9[9];
+	lookup[15] = ANTIC_lookup_gtia9[10];
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		WRITE_VIDEO_LONG((ULONG *) ptr, lookup[screendata >> 4]);
+		WRITE_VIDEO_LONG((ULONG *) ptr + 1, lookup[screendata & 0xf]);
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			ptr += 4;
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int k = 4;
+			UBYTE pm_reg;
+			do {
+				pm_reg = pm_lookup_ptr[*c_pm_scanline_ptr++];
+				if (pm_reg) {
+					if (pm_reg == L_PF3) {
+						UBYTE tmp = k > 2 ? screendata >> 4 : screendata & 0xf;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+						WRITE_VIDEO(ptr, colour_translation_table[tmp | GTIA_COLPF3]);
+#else
+						WRITE_VIDEO(ptr, tmp | ((UWORD)tmp << 8) | ANTIC_cl[C_PF3]);
+#endif
+					}
+					else
+					{
+						WRITE_VIDEO(ptr, COLOUR(pm_reg));
+					}
+				}
+				ptr++;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void draw_antic_e_gtia10 (int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	prepare_an_antic_e(nchars, antic_memptr, t_pm_scanline_ptr);
+	draw_an_gtia10(t_pm_scanline_ptr);
+}
+static void draw_antic_e_gtia11 (int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	prepare_an_antic_e(nchars, antic_memptr, t_pm_scanline_ptr);
+	draw_an_gtia11(t_pm_scanline_ptr);
+}
+
+static void draw_antic_f(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	INIT_BACKGROUND_6
+	INIT_HIRES
+
+	CHAR_LOOP_BEGIN
+		int screendata = *antic_memptr++;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			if (screendata) {
+				WRITE_VIDEO(ptr++, hires_norm(screendata & 0xc0));
+				WRITE_VIDEO(ptr++, hires_norm(screendata & 0x30));
+				WRITE_VIDEO(ptr++, hires_norm(screendata & 0x0c));
+				WRITE_VIDEO(ptr++, hires_norm((screendata & 0x03) << 2));
+			}
+			else
+				DRAW_BACKGROUND(C_PF2)
+		}
+		else
+			DO_PMG_HIRES(screendata)
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void draw_antic_f_artif(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	ULONG screendata_tally = *antic_memptr++;
+
+	setup_art_colours();
+	CHAR_LOOP_BEGIN
+		int screendata = *antic_memptr++;
+		screendata_tally <<= 8;
+		screendata_tally |= screendata;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			DRAW_ARTIF
+		else {
+			screendata = antic_memptr[-2];
+			DO_PMG_HIRES(screendata)
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+#ifndef USE_COLOUR_TRANSLATION_TABLE
+static void draw_antic_f_artif_new(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	ULONG pmtally;
+	ULONG screendata_tally = *antic_memptr++;
+	INIT_ARTIF_NEW
+
+	setup_art_colours();
+	CHAR_LOOP_BEGIN
+		int screendata = *antic_memptr++;
+		screendata_tally <<= 8;
+		screendata_tally |= screendata;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			DRAW_ARTIF_NEW
+		else {
+			screendata = antic_memptr[-2];
+			pmtally = ((screendata_tally & 0x03f000) << 6) |
+					  ((screendata_tally & 0x00fc00) << 2) |
+					  ((screendata_tally & 0x003f00) >> 2) |
+					  ((screendata_tally & 0x000fc0) >> 6);
+			DO_PMG_HIRES_NEW(screendata,pmtally)
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+#endif
+
+static void prepare_an_antic_f(int nchars, const UBYTE *antic_memptr, const ULONG *t_pm_scanline_ptr)
+{
+	UBYTE *an_ptr = (UBYTE *) t_pm_scanline_ptr + (an_scanline - GTIA_pm_scanline);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		*an_ptr++ = screendata >> 6;
+		*an_ptr++ = (screendata >> 4) & 3;
+		*an_ptr++ = (screendata >> 2) & 3;
+		*an_ptr++ = screendata & 3;
+	CHAR_LOOP_END
+}
+
+static void draw_antic_f_gtia9(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_f(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia9(t_pm_scanline_ptr);
+		return;
+	}
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia9[screendata >> 4]);
+		WRITE_VIDEO_LONG((ULONG *) ptr + 1, ANTIC_lookup_gtia9[screendata & 0xf]);
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			ptr += 4;
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int k = 4;
+			UBYTE pm_reg;
+			do {
+				pm_reg = pm_lookup_ptr[*c_pm_scanline_ptr++];
+				if (pm_reg) {
+					if (pm_reg == L_PF3) {
+						UBYTE tmp = k > 2 ? screendata >> 4 : screendata & 0xf;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+						WRITE_VIDEO(ptr, colour_translation_table[tmp | GTIA_COLPF3]);
+#else
+						WRITE_VIDEO(ptr, tmp | ((UWORD)tmp << 8) | ANTIC_cl[C_PF3]);
+#endif
+					}
+					else {
+						WRITE_VIDEO(ptr, COLOUR(pm_reg));
+					}
+				}
+				ptr++;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+static void draw_antic_f_gtia10(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+#ifdef WORDS_UNALIGNED_OK
+	ULONG lookup_gtia10[16];
+#else
+	UWORD lookup_gtia10[16];
+#endif
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_f(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia10(t_pm_scanline_ptr);
+		return;
+	}
+#ifdef WORDS_UNALIGNED_OK
+	lookup_gtia10[0] = ANTIC_cl[C_PM0] | (ANTIC_cl[C_PM0] << 16);
+	lookup_gtia10[1] = ANTIC_cl[C_PM1] | (ANTIC_cl[C_PM1] << 16);
+	lookup_gtia10[2] = ANTIC_cl[C_PM2] | (ANTIC_cl[C_PM2] << 16);
+	lookup_gtia10[3] = ANTIC_cl[C_PM3] | (ANTIC_cl[C_PM3] << 16);
+	lookup_gtia10[12] = lookup_gtia10[4] = ANTIC_cl[C_PF0] | (ANTIC_cl[C_PF0] << 16);
+	lookup_gtia10[13] = lookup_gtia10[5] = ANTIC_cl[C_PF1] | (ANTIC_cl[C_PF1] << 16);
+	lookup_gtia10[14] = lookup_gtia10[6] = ANTIC_cl[C_PF2] | (ANTIC_cl[C_PF2] << 16);
+	lookup_gtia10[15] = lookup_gtia10[7] = ANTIC_cl[C_PF3] | (ANTIC_cl[C_PF3] << 16);
+	lookup_gtia10[8] = lookup_gtia10[9] = lookup_gtia10[10] = lookup_gtia10[11] = ANTIC_lookup_gtia9[0];
+#else
+	lookup_gtia10[0] = ANTIC_cl[C_PM0];
+	lookup_gtia10[1] = ANTIC_cl[C_PM1];
+	lookup_gtia10[2] = ANTIC_cl[C_PM2];
+	lookup_gtia10[3] = ANTIC_cl[C_PM3];
+	lookup_gtia10[12] = lookup_gtia10[4] = ANTIC_cl[C_PF0];
+	lookup_gtia10[13] = lookup_gtia10[5] = ANTIC_cl[C_PF1];
+	lookup_gtia10[14] = lookup_gtia10[6] = ANTIC_cl[C_PF2];
+	lookup_gtia10[15] = lookup_gtia10[7] = ANTIC_cl[C_PF3];
+	lookup_gtia10[8] = lookup_gtia10[9] = lookup_gtia10[10] = lookup_gtia10[11] = ANTIC_cl[C_BAK];
+#endif
+	ptr++;
+	t_pm_scanline_ptr = (const ULONG *) (((const UBYTE *) t_pm_scanline_ptr) + 1);
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			DO_GTIA_BYTE(ptr, lookup_gtia10, screendata)
+			ptr += 4;
+		}
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int pm_pixel;
+			int colreg;
+			int k = 4;
+			UBYTE t_screendata = screendata >> 4;
+			do {
+				colreg = gtia_10_lookup[t_screendata];
+				PF_COLLS(colreg) |= pm_pixel = *c_pm_scanline_ptr++; /*playfield colours can generate collisions*/
+				pm_pixel |= gtia_10_pm[t_screendata]; /*but player colours don't*/
+				WRITE_VIDEO(ptr++, COLOUR(pm_lookup_ptr[pm_pixel] | colreg)); /*although they mix with the real players*/
+				if (k == 3)
+					t_screendata = screendata & 0x0f;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border_gtia10();
+}
+
+static void draw_antic_f_gtia11(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	if ((unsigned long) ptr & 2) { /* HSCROL & 1 */
+		prepare_an_antic_f(nchars, antic_memptr, t_pm_scanline_ptr);
+		draw_an_gtia11(t_pm_scanline_ptr);
+		return;
+	}
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		WRITE_VIDEO_LONG((ULONG *) ptr, ANTIC_lookup_gtia11[screendata >> 4]);
+		WRITE_VIDEO_LONG((ULONG *) ptr + 1, ANTIC_lookup_gtia11[screendata & 0xf]);
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr))
+			ptr += 4;
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int k = 4;
+			UBYTE pm_reg;
+			do {
+				pm_reg = pm_lookup_ptr[*c_pm_scanline_ptr++];
+				if (pm_reg) {
+					if (pm_reg == L_PF3) {
+						UBYTE tmp = k > 2 ? screendata & 0xf0 : screendata << 4;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+						WRITE_VIDEO(ptr, colour_translation_table[tmp ? tmp | GTIA_COLPF3 : GTIA_COLPF3 & 0xf0]);
+#else
+						WRITE_VIDEO(ptr, tmp ? tmp | ((UWORD)tmp << 8) | ANTIC_cl[C_PF3] : ANTIC_cl[C_PF3] & 0xf0f0);
+#endif
+					}
+					else
+					{
+						WRITE_VIDEO(ptr, COLOUR(pm_reg));
+					}
+				}
+				ptr++;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border_gtia11();
+}
+
+/* GTIA-switch-to-mode-00 bug
+If while drawing line in hi-res mode PRIOR is changed from 0x40..0xff to
+0x00..0x3f, GTIA doesn't back to hi-res, but starts generating mode similar
+to ANTIC's 0xe, but with colours PF0, PF1, PF2, PF3. */
+
+/* Technical explaination by perrym:
+ * in gtia.pdf there is a flip-flop at page 40, drawing location C3 with
+ * what looks like W and A on the gates
+ * This is set by AN2=0 AN1=1 AN0=1 durning HBLANK
+ * The middle input to the lower NOR gate is the inverted signal !NRM(?)
+ * (NRM means NORMAL?) which arrives from the top left of the page.
+ * This signal is defined on page 38, positions C2/B2
+ * where there is a NOR gate pointing downwards with 00 written to the
+ * right of its output.
+ * !NRM is the condition that PRIOR is not set to b7=0,b6=0.
+ * When PRIOR is not set to NRM, the flip-flip is always reset,
+ * which seems necessary for the proper operation of the GTIA modes.
+ * If PRIOR is reset to NRM then the flip-flop remains reset, and
+ * since ANTIC data in hi-res modes is sent as PF0-PF3, this data is used
+ * by GTIA directly.*/
+
+static void draw_antic_f_gtia_bug(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	lookup2[0x00] = ANTIC_cl[C_PF0];
+	lookup2[0x40] = lookup2[0x10] = lookup2[0x04] = lookup2[0x01] = ANTIC_cl[C_PF1];
+	lookup2[0x80] = lookup2[0x20] = lookup2[0x08] = lookup2[0x02] = ANTIC_cl[C_PF2];
+	lookup2[0xc0] = lookup2[0x30] = lookup2[0x0c] = lookup2[0x03] = ANTIC_cl[C_PF3];
+
+	CHAR_LOOP_BEGIN
+		UBYTE screendata = *antic_memptr++;
+		if (IS_ZERO_ULONG(t_pm_scanline_ptr)) {
+			WRITE_VIDEO(ptr++, lookup2[screendata & 0xc0]);
+			WRITE_VIDEO(ptr++, lookup2[screendata & 0x30]);
+			WRITE_VIDEO(ptr++, lookup2[screendata & 0x0c]);
+			WRITE_VIDEO(ptr++, lookup2[screendata & 0x03]);
+		}
+		else {
+			const UBYTE *c_pm_scanline_ptr = (const UBYTE *) t_pm_scanline_ptr;
+			int pm_pixel;
+			int colreg;
+			int k = 4;
+			do {
+				colreg = (playfield_lookup + 0x40)[screendata & 0xc0];
+				DO_PMG_LORES
+				screendata <<= 2;
+			} while (--k);
+		}
+		t_pm_scanline_ptr++;
+	CHAR_LOOP_END
+	do_border();
+}
+
+/* pointer to a function that draws a single line of graphics */
+typedef void (*draw_antic_function)(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr);
+
+/* tables for all GTIA and ANTIC modes */
+static draw_antic_function draw_antic_table[4][16] = {
+/* normal */
+		{ NULL,			NULL,			draw_antic_2,	draw_antic_2,
+		draw_antic_4,	draw_antic_4,	draw_antic_6,	draw_antic_6,
+		draw_antic_8,	draw_antic_9,	draw_antic_a,	draw_antic_c,
+		draw_antic_c,	draw_antic_e,	draw_antic_e,	draw_antic_f},
+/* GTIA 9 */
+		{ NULL,			NULL,			draw_antic_2_gtia9,	draw_antic_2_gtia9,
+		draw_antic_4_gtia9,	draw_antic_4_gtia9,	draw_antic_6_gtia9,	draw_antic_6_gtia9,
+		draw_antic_8_gtia9,	draw_antic_9_gtia9,	draw_antic_a_gtia9,	draw_antic_9_gtia9,
+		draw_antic_9_gtia9, draw_antic_e_gtia9,	draw_antic_e_gtia9,	draw_antic_f_gtia9},
+/* GTIA 10 */
+		{ NULL,			NULL,			draw_antic_2_gtia10,	draw_antic_2_gtia10,
+		draw_antic_4_gtia10,	draw_antic_4_gtia10,	draw_antic_6_gtia10,	draw_antic_6_gtia10,
+		draw_antic_8_gtia10,	draw_antic_9_gtia10,	draw_antic_a_gtia10,	draw_antic_9_gtia10,
+		draw_antic_9_gtia10,	draw_antic_e_gtia10,	draw_antic_e_gtia10,	draw_antic_f_gtia10},
+/* GTIA 11 */
+		{ NULL,			NULL,			draw_antic_2_gtia11,	draw_antic_2_gtia11,
+		draw_antic_4_gtia11,	draw_antic_4_gtia11,	draw_antic_6_gtia11,	draw_antic_6_gtia11,
+		draw_antic_8_gtia11,	draw_antic_9_gtia11,	draw_antic_a_gtia11,	draw_antic_9_gtia11,
+		draw_antic_9_gtia11,	draw_antic_e_gtia11,	draw_antic_e_gtia11,	draw_antic_f_gtia11}};
+
+/* pointer to current GTIA/ANTIC mode routine */
+static draw_antic_function draw_antic_ptr = draw_antic_8;
+#ifdef NEW_CYCLE_EXACT
+static draw_antic_function saved_draw_antic_ptr;
+#endif
+/* pointer to current GTIA mode blank drawing routine */
+static void (*draw_antic_0_ptr)(void) = draw_antic_0;
+
+#ifdef NEW_CYCLE_EXACT
+/* wrapper for antic_0, for dmactl bugs */
+static void draw_antic_0_dmactl_bug(int nchars, const UBYTE *antic_memptr, UWORD *ptr, const ULONG *t_pm_scanline_ptr)
+{
+	draw_antic_0_ptr();
+}
+#endif
+
+/* Artifacting ------------------------------------------------------------ */
+
+void ANTIC_UpdateArtifacting(void)
+{
+#define ART_BROWN 0
+#define ART_BLUE 1
+#define ART_DARK_BROWN 2
+#define ART_DARK_BLUE 3
+#define ART_BRIGHT_BROWN 4
+#define ART_BRIGHT_BLUE 5
+#define ART_RED 6
+#define ART_GREEN 7
+	static const UBYTE art_colour_table[4][8] = {
+		{ 0x88, 0x14, 0x88, 0x14, 0x8f, 0x1f, 0xbb, 0x5f },	/* brownblue */
+		{ 0x14, 0x88, 0x14, 0x88, 0x1f, 0x8f, 0x5f, 0xbb },	/* bluebrown */
+		{ 0xd6, 0x46, 0xd6, 0x46, 0xdf, 0x4a, 0x4f, 0xac },	/* redgreen */
+		{ 0x46, 0xd6, 0x46, 0xd6, 0x4a, 0xdf, 0xac, 0x4f }	/* greenred */
+	};
+
+	int i;
+	int j;
+	int c;
+	const UBYTE *art_colours;
+	UBYTE q;
+	UBYTE art_white;
+
+	if (ANTIC_artif_mode == 0) {
+		draw_antic_table[0][2] = draw_antic_table[0][3] = draw_antic_2;
+		draw_antic_table[0][0xf] = draw_antic_f;
+		return;
+	}
+
+#ifndef USE_COLOUR_TRANSLATION_TABLE
+	if (ANTIC_artif_new) {
+		static UWORD new_art_colour_table[4][2] = {
+			{0x4040, 0x8080},
+			{0x8080, 0x4040},
+			{0x8080, 0xd0d0},
+			{0xd0d0, 0x8080}
+		};
+		draw_antic_table[0][2] = draw_antic_table[0][3] = draw_antic_2_artif_new;
+		draw_antic_table[0][0xf] = draw_antic_f_artif_new;
+		art_colour1_new = new_art_colour_table[ANTIC_artif_mode - 1][0];
+		art_colour2_new = new_art_colour_table[ANTIC_artif_mode - 1][1];
+	}
+	else
+#endif
+	{
+		draw_antic_table[0][2] = draw_antic_table[0][3] = draw_antic_2_artif;
+		draw_antic_table[0][0xf] = draw_antic_f_artif;
+	}
+
+	art_colours = (ANTIC_artif_mode <= 4 ? art_colour_table[ANTIC_artif_mode - 1] : art_colour_table[2]);
+
+	art_reverse_colpf1_save = art_normal_colpf1_save = ANTIC_cl[C_PF1] & 0x0f0f;
+	art_reverse_colpf2_save = art_normal_colpf2_save = ANTIC_cl[C_PF2];
+	art_white = (ANTIC_cl[C_PF2] & 0xf0) | (ANTIC_cl[C_PF1] & 0x0f);
+
+	for (i = 0; i <= 255; i++) {
+		art_bkmask_normal[i] = 0;
+		art_lummask_normal[i] = 0;
+		art_bkmask_reverse[255 - i] = 0;
+		art_lummask_reverse[255 - i] = 0;
+
+		for (j = 0; j <= 3; j++) {
+			q = i << j;
+			if (!(q & 0x20)) {
+				if ((q & 0xf8) == 0x50)
+					c = ART_BLUE;				/* 01010 */
+				else if ((q & 0xf8) == 0xD8)
+					c = ART_DARK_BLUE;			/* 11011 */
+				else {							/* xx0xx */
+					((UBYTE *) art_lookup_normal)[(i << 2) + j] = GTIA_COLPF2;
+					((UBYTE *) art_lookup_reverse)[((255 - i) << 2) + j] = art_white;
+					((UBYTE *) art_bkmask_normal)[(i << 2) + j] = 0xff;
+					((UBYTE *) art_lummask_reverse)[((255 - i) << 2) + j] = 0x0f;
+					((UBYTE *) art_bkmask_reverse)[((255 - i) << 2) + j] = 0xf0;
+					continue;
+				}
+			}
+			else if (q & 0x40) {
+				if (q & 0x10)
+					goto colpf1_pixel;			/* x111x */
+				else if (q & 0x80) {
+					if (q & 0x08)
+						c = ART_BRIGHT_BROWN;	/* 11101 */
+					else
+						goto colpf1_pixel;		/* 11100 */
+				}
+				else
+					c = ART_GREEN;				/* 0110x */
+			}
+			else if (q & 0x10) {
+				if (q & 0x08) {
+					if (q & 0x80)
+						c = ART_BRIGHT_BROWN;	/* 00111 */
+					else
+						goto colpf1_pixel;		/* 10111 */
+				}
+				else
+					c = ART_RED;				/* x0110 */
+			}
+			else
+				c = ART_BROWN;					/* x010x */
+
+			((UBYTE *) art_lookup_reverse)[((255 - i) << 2) + j] =
+			((UBYTE *) art_lookup_normal)[(i << 2) + j] = art_colours[(j & 1) ^ c];
+			continue;
+
+			colpf1_pixel:
+			((UBYTE *) art_lookup_normal)[(i << 2) + j] = art_white;
+			((UBYTE *) art_lookup_reverse)[((255 - i) << 2) + j] = GTIA_COLPF2;
+			((UBYTE *) art_bkmask_reverse)[((255 - i) << 2) + j] = 0xff;
+			((UBYTE *) art_lummask_normal)[(i << 2) + j] = 0x0f;
+			((UBYTE *) art_bkmask_normal)[(i << 2) + j] = 0xf0;
+		}
+	}
+}
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+/* Display List ------------------------------------------------------------ */
+
+UBYTE ANTIC_GetDLByte(UWORD *paddr)
+{
+	int addr = *paddr;
+	UBYTE result;
+	if (ANTIC_xe_ptr != NULL && addr < 0x8000 && addr >= 0x4000)
+		result = ANTIC_xe_ptr[addr - 0x4000];
+	else
+		result = MEMORY_GetByte((UWORD) addr);
+	addr++;
+	if ((addr & 0x3FF) == 0)
+		addr -= 0x400;
+	*paddr = (UWORD) addr;
+	return result;
+}
+
+UWORD ANTIC_GetDLWord(UWORD *paddr)
+{
+	UBYTE lsb = ANTIC_GetDLByte(paddr);
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+	if (ANTIC_player_flickering && ((GTIA_VDELAY & 0x80) == 0 || ANTIC_ypos & 1))
+		GTIA_GRAFP3 = lsb;
+#endif
+	return (ANTIC_GetDLByte(paddr) << 8) + lsb;
+}
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+
+/* Real ANTIC doesn't fetch beginning bytes in HSC
+   nor screen+47 in wide playfield. This function does. */
+static void antic_load(void)
+{
+#ifdef PAGED_MEM
+	UBYTE *antic_memptr = antic_memory + ANTIC_margin;
+	UWORD new_screenaddr = screenaddr + chars_read[md];
+	if ((screenaddr ^ new_screenaddr) & 0xf000) {
+		do
+			*antic_memptr++ = MEMORY_dGetByte(screenaddr++);
+		while (screenaddr & 0xfff);
+		screenaddr -= 0x1000;
+		new_screenaddr -= 0x1000;
+	}
+	while (screenaddr < new_screenaddr)
+		*antic_memptr++ = MEMORY_dGetByte(screenaddr++);
+#else
+	UWORD new_screenaddr = screenaddr + chars_read[md];
+	if ((screenaddr ^ new_screenaddr) & 0xf000) {
+		int bytes = (-screenaddr) & 0xfff;
+		if (ANTIC_xe_ptr != NULL && screenaddr < 0x8000 && screenaddr >= 0x4000) {
+			memcpy(antic_memory + ANTIC_margin, ANTIC_xe_ptr + (screenaddr - 0x4000), bytes);
+			if (new_screenaddr & 0xfff)
+				memcpy(antic_memory + ANTIC_margin + bytes, ANTIC_xe_ptr + (screenaddr + bytes - 0x5000), new_screenaddr & 0xfff);
+		}
+		else if ((screenaddr & 0xf000) == 0xd000) {
+			MEMORY_CopyFromMem(screenaddr, antic_memory + ANTIC_margin, bytes);
+			if (new_screenaddr & 0xfff)
+				MEMORY_CopyFromMem((UWORD) (screenaddr + bytes - 0x1000), antic_memory + ANTIC_margin + bytes, new_screenaddr & 0xfff);
+		}
+		else {
+			MEMORY_dCopyFromMem(screenaddr, antic_memory + ANTIC_margin, bytes);
+			if (new_screenaddr & 0xfff)
+				MEMORY_dCopyFromMem(screenaddr + bytes - 0x1000, antic_memory + ANTIC_margin + bytes, new_screenaddr & 0xfff);
+		}
+		screenaddr = new_screenaddr - 0x1000;
+	}
+	else {
+		if (ANTIC_xe_ptr != NULL && screenaddr < 0x8000 && screenaddr >= 0x4000)
+			memcpy(antic_memory + ANTIC_margin, ANTIC_xe_ptr + (screenaddr - 0x4000), chars_read[md]);
+		else if ((screenaddr & 0xf000) == 0xd000)
+			MEMORY_CopyFromMem(screenaddr, antic_memory + ANTIC_margin, chars_read[md]);
+		else
+			MEMORY_dCopyFromMem(screenaddr, antic_memory + ANTIC_margin, chars_read[md]);
+		screenaddr = new_screenaddr;
+	}
+#endif
+}
+
+#ifdef NEW_CYCLE_EXACT
+int ANTIC_cur_screen_pos = ANTIC_NOT_DRAWING;
+#endif
+
+#ifdef USE_CURSES
+static int scanlines_to_curses_display = 0;
+#endif
+
+/* This function emulates one frame drawing screen at Screen_atari */
+void ANTIC_Frame(int draw_display)
+{
+	static const UBYTE mode_type[32] = {
+		NORMAL0, NORMAL0, NORMAL0, NORMAL0, NORMAL0, NORMAL0, NORMAL1, NORMAL1,
+		NORMAL2, NORMAL2, NORMAL1, NORMAL1, NORMAL1, NORMAL0, NORMAL0, NORMAL0,
+		SCROLL0, SCROLL0, SCROLL0, SCROLL0, SCROLL0, SCROLL0, SCROLL1, SCROLL1,
+		SCROLL2, SCROLL2, SCROLL1, SCROLL1, SCROLL1, SCROLL0, SCROLL0, SCROLL0
+	};
+	static const UBYTE normal_lastline[16] =
+		{ 0, 0, 7, 9, 7, 15, 7, 15, 7, 3, 3, 1, 0, 1, 0, 0 };
+	UBYTE vscrol_flag = FALSE;
+	UBYTE no_jvb = TRUE;
+#ifndef NEW_CYCLE_EXACT
+	UBYTE need_load;
+#endif
+
+#ifdef NEW_CYCLE_EXACT
+	int cpu2antic_index;
+#endif /* NEW_CYCLE_EXACT */
+
+	ANTIC_ypos = 0;
+	do {
+		POKEY_Scanline();		/* check and generate IRQ */
+		OVERSCREEN_LINE;
+	} while (ANTIC_ypos < 8);
+
+	scrn_ptr = (UWORD *) Screen_atari;
+#ifdef NEW_CYCLE_EXACT
+	ANTIC_cur_screen_pos = ANTIC_NOT_DRAWING;
+#endif
+	need_dl = TRUE;
+	do {
+#ifdef SKIP
+		if ((INPUT_mouse_mode == INPUT_MOUSE_PEN || INPUT_mouse_mode == INPUT_MOUSE_GUN) && (ANTIC_ypos >> 1 == ANTIC_PENV_input)) {
+			PENH = ANTIC_PENH_input;
+			PENV = ANTIC_PENV_input;
+			if (GTIA_GRACTL & 4)
+				GTIA_TRIG_latch[INPUT_mouse_port] = 0;
+		}
+#endif
+		POKEY_Scanline();		/* check and generate IRQ */
+		pmg_dma();
+
+#ifdef USE_CURSES
+		if (--scanlines_to_curses_display == 0)
+			curses_display_line(anticmode, antic_memory + ANTIC_margin);
+#endif
+
+		need_load = FALSE;
+		if (need_dl) {
+			if (ANTIC_DMACTL & 0x20) {
+				IR = ANTIC_GetDLByte(&ANTIC_dlist);
+				anticmode = IR & 0xf;
+				ANTIC_xpos++;
+				/* PMG flickering :-) */
+				if (ANTIC_missile_flickering)
+					GTIA_GRAFM = ANTIC_ypos & 1 ? IR : ((GTIA_GRAFM ^ IR) & hold_missiles_tab[GTIA_VDELAY & 0xf]) ^ IR;			
+				if (ANTIC_player_flickering) 
+				{
+					UBYTE hold = ANTIC_ypos & 1 ? 0 : GTIA_VDELAY;
+					if ((hold & 0x10) == 0)
+						GTIA_GRAFP0 = MEMORY_dGetByte((UWORD) (CPU_regPC - ANTIC_xpos + 8));
+					if ((hold & 0x20) == 0)
+						GTIA_GRAFP1 = MEMORY_dGetByte((UWORD) (CPU_regPC - ANTIC_xpos + 9));
+					if ((hold & 0x40) == 0)
+						GTIA_GRAFP2 = MEMORY_dGetByte((UWORD) (CPU_regPC - ANTIC_xpos + 10));
+					if ((hold & 0x80) == 0)
+						GTIA_GRAFP3 = MEMORY_dGetByte((UWORD) (CPU_regPC - ANTIC_xpos + 11));
+				}
+			}
+			else
+				IR &= 0x7f;	/* repeat last instruction, but don't generate DLI */
+
+			dctr = 0;
+			need_dl = FALSE;
+			vscrol_off = FALSE;
+
+			switch (anticmode) {
+			case 0x00:
+				lastline = (IR >> 4) & 7;
+				if (vscrol_flag) {
+					lastline = ANTIC_VSCROL;
+					vscrol_flag = FALSE;
+					vscrol_off = TRUE;
+				}
+				break;
+			case 0x01:
+				lastline = 0;
+				if (IR & 0x40 && ANTIC_DMACTL & 0x20) {
+					ANTIC_dlist = ANTIC_GetDLWord(&ANTIC_dlist);
+					ANTIC_xpos += 2;
+					no_jvb = FALSE;
+				}
+				else
+					if (vscrol_flag) {
+						lastline = ANTIC_VSCROL;
+						vscrol_flag = FALSE;
+						vscrol_off = TRUE;
+					}
+				break;
+			default:
+				lastline = normal_lastline[anticmode];
+				if (IR & 0x20) {
+					if (!vscrol_flag) {
+						CPU_GO(VSCON_C);
+						dctr = ANTIC_VSCROL;
+						vscrol_flag = TRUE;
+					}
+				}
+				else if (vscrol_flag) {
+					lastline = ANTIC_VSCROL;
+					vscrol_flag = FALSE;
+					vscrol_off = TRUE;
+				}
+				if (IR & 0x40 && ANTIC_DMACTL & 0x20) {
+					screenaddr = ANTIC_GetDLWord(&ANTIC_dlist);
+					ANTIC_xpos += 2;
+				}
+				md = mode_type[IR & 0x1f];
+				need_load = TRUE;
+				draw_antic_ptr = draw_antic_table[GTIA_PRIOR >> 6][anticmode];
+				break;
+			}
+		}
+#ifdef NEW_CYCLE_EXACT
+		cpu2antic_index = 0;
+		if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0 ||
+			(anticmode >= 8 && !need_load)) {
+			cpu2antic_index = 0;
+		}
+		else {
+/* TODO: use a cleaner lookup table here */
+			if (!(IR & 0x10) && ((ANTIC_DMACTL & 3) == 1))
+				cpu2antic_index = 1;
+			else if ((!(IR &0x10) && ((ANTIC_DMACTL & 3) == 2)) ||
+				((IR & 0x10) && ((ANTIC_DMACTL & 3) == 1))) {
+				cpu2antic_index = 2;
+			}
+			else
+				cpu2antic_index = 10;
+			if (IR & 0x10) {
+				cpu2antic_index += (ANTIC_HSCROL >> 1);
+			}
+			if (anticmode >=2 && anticmode <=7 && !need_load)
+				cpu2antic_index += 17;
+			if (anticmode ==6 || anticmode ==7)
+				cpu2antic_index += 17 * 2;
+		 	else if (anticmode==8 || anticmode == 9)
+				cpu2antic_index += 17 * 6;
+			else if (anticmode >=0xa && anticmode <=0xc)
+				cpu2antic_index += 17 * 5;
+			else if (anticmode >=0x0d)
+				cpu2antic_index += 17 * 4;
+		}
+		ANTIC_cpu2antic_ptr = &CYCLE_MAP_cpu2antic[CYCLE_MAP_SIZE * cpu2antic_index];
+		ANTIC_antic2cpu_ptr = &CYCLE_MAP_antic2cpu[CYCLE_MAP_SIZE * cpu2antic_index];
+#endif /* NEW_CYCLE_EXACT */
+
+		if ((IR & 0x4f) == 1 && (ANTIC_DMACTL & 0x20)) {
+			ANTIC_dlist = ANTIC_GetDLWord(&ANTIC_dlist);
+			ANTIC_xpos += 2;
+		}
+
+#ifdef NEW_CYCLE_EXACT
+		/* begin drawing here */
+		if (draw_display) {
+			ANTIC_cur_screen_pos = LBORDER_START;
+			ANTIC_xpos = ANTIC_antic2cpu_ptr[ANTIC_xpos]; /* convert antic to cpu(need for WSYNC) */
+			if (dctr == lastline) {
+				if (no_jvb)
+					need_dl = TRUE;
+				if (IR & 0x80) {
+					CPU_GO(ANTIC_antic2cpu_ptr[ANTIC_NMIST_C]);
+					ANTIC_NMIST = 0x9f;
+					if (ANTIC_NMIEN & 0x80) {
+						CPU_GO(ANTIC_antic2cpu_ptr[ANTIC_NMI_C]);
+						CPU_NMI();
+					}
+				}
+			}
+		}
+		else /* force this to be within an else if NEW_CYCLE_EXACT */
+#endif /* NEW_CYCLE_EXACT */
+		if (dctr == lastline) {
+			if (no_jvb)
+				need_dl = TRUE;
+			if (IR & 0x80) {
+				CPU_GO(ANTIC_NMIST_C);
+				ANTIC_NMIST = 0x9f;
+				if (ANTIC_NMIEN & 0x80) {
+					CPU_GO(ANTIC_NMI_C);
+					CPU_NMI();
+				}
+			}
+		}
+		if (!draw_display) {
+			ANTIC_xpos += ANTIC_DMAR;
+			if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0) {
+				GOEOL;
+				if (no_jvb) {
+					dctr++;
+					dctr &= 0xf;
+				}
+				continue;
+			}
+			if (need_load) {
+				ANTIC_xpos += load_cycles[md];
+				if (anticmode <= 5)	/* extra cycles in font modes */
+					ANTIC_xpos += before_cycles[md] - extra_cycles[md];
+			}
+			if (anticmode < 8)
+				ANTIC_xpos += font_cycles[md];
+			GOEOL;
+			dctr++;
+			dctr &= 0xf;
+			continue;
+		}
+#ifndef NO_YPOS_BREAK_FLICKER
+#define YPOS_BREAK_FLICKER do{if (ANTIC_ypos == ANTIC_break_ypos - 1000) {\
+				static int toggle;\
+				if (toggle == 1) {\
+					FILL_VIDEO(scrn_ptr + LBORDER_START, 0x0f0f, (RBORDER_END - LBORDER_START) * 2);\
+				}\
+				toggle = !toggle;\
+			}}while(0)
+#else
+#define YPOS_BREAK_FLICKER do{}while(0)
+#endif /* NO_YPOS_BREAK_FLICKER */
+
+#ifdef NEW_CYCLE_EXACT
+		GTIA_NewPmScanline();
+		if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0) {
+			GOEOL_CYCLE_EXACT;
+			draw_partial_scanline(ANTIC_cur_screen_pos, RBORDER_END);
+			UPDATE_DMACTL;
+			UPDATE_GTIA_BUG;
+			ANTIC_cur_screen_pos = ANTIC_NOT_DRAWING;
+			YPOS_BREAK_FLICKER;
+			scrn_ptr += Screen_WIDTH / 2;
+			if (no_jvb) {
+				dctr++;
+				dctr &= 0xf;
+			}
+			continue;
+		}
+
+		GOEOL_CYCLE_EXACT;
+		draw_partial_scanline(ANTIC_cur_screen_pos, RBORDER_END);
+		UPDATE_DMACTL;
+		UPDATE_GTIA_BUG;
+		ANTIC_cur_screen_pos = ANTIC_NOT_DRAWING;
+
+#else /* NEW_CYCLE_EXACT not defined */
+		if (need_load && anticmode <= 5 && ANTIC_DMACTL & 3)
+			ANTIC_xpos += before_cycles[md];
+
+		CPU_GO(SCR_C);
+		GTIA_NewPmScanline();
+
+		ANTIC_xpos += ANTIC_DMAR;
+
+		if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0) {
+			draw_antic_0_ptr();
+			GOEOL;
+			YPOS_BREAK_FLICKER;
+			scrn_ptr += scrn_line;
+			if (no_jvb) {
+				dctr++;
+				dctr &= 0xf;
+			}
+			continue;
+		}
+
+		if (need_load) {
+			antic_load();
+#ifdef USE_CURSES
+			/* Normally, we would call curses_display_line here,
+			   and not use scanlines_to_curses_display at all.
+			   That would however cause incorrect color of the "MEMORY"
+			   menu item in Self Test - it isn't set properly
+			   in the first scanline. We therefore postpone
+			   curses_display_line call to the next scanline. */
+			scanlines_to_curses_display = 1;
+#endif
+			ANTIC_xpos += load_cycles[md];
+			if (anticmode <= 5)	/* extra cycles in font modes */
+				ANTIC_xpos -= extra_cycles[md];
+		}
+
+		draw_antic_ptr(chars_displayed[md],
+			antic_memory + ANTIC_margin + ch_offset[md],
+			scrn_ptr + x_min[md],
+			(ULONG *) &GTIA_pm_scanline[x_min[md]]);
+
+		GOEOL;
+#endif /* NEW_CYCLE_EXACT */
+		YPOS_BREAK_FLICKER;
+		scrn_ptr += scrn_line;
+		dctr++;
+		dctr &= 0xf;
+	} while (ANTIC_ypos < (ATARI_HEIGHT + 8));
+
+  emu_DrawVsync();
+
+#ifndef NO_SIMPLE_PAL_BLENDING
+	/* Simple PAL blending, using only the base 256 color palette. */
+	if (ANTIC_pal_blending)
+	{
+		int ypos = ANTIC_ypos - 1;
+		/* Start at the last screen line (248). */
+		ULONG *ptr = (ULONG *) (scrn_ptr - 4 * RCHOP);
+		do {
+			int k = 2 * (48 - LCHOP - RCHOP);
+			do {
+				/* For each grayscale pixel (colors $00..$0f) blend it with
+				   chrominance of a pixel from the previous line. */
+				ULONG pix = READ_VIDEO_LONG(--ptr);
+				ULONG mask = 0xf0f0f0f0;
+				/* Take advantage of the fact that chrominance can change only
+				   every two pixels. This way we may test only two pixels in a
+				   quadruplet instead of four. */
+				if (pix & 0x0000f0f0)
+					/* Two LSBs are non-grayscale */
+					mask &= 0xf0f00000;
+				if (pix & 0xf0f00000)
+					/* Two MSBs are non-grayscale */
+					mask &= 0x0000f0f0;
+
+				WRITE_VIDEO_LONG(ptr, (READ_VIDEO_LONG(ptr - ATARI_WIDTH / 4) & mask) | pix);
+			} while (--k);
+			ptr -= 2 * (LCHOP + RCHOP); /* Move one line up */
+		} while (--ypos > 8); /* Stop after line 9 */
+   
+	}
+#endif /* NO_SIMPLE_PAL_BLENDING */
+
+/* TODO: cycle-exact overscreen lines */
+	POKEY_Scanline();		/* check and generate IRQ */
+	CPU_GO(ANTIC_NMIST_C);
+	ANTIC_NMIST = 0x5f;				/* Set VBLANK */
+	if (ANTIC_NMIEN & 0x40) {
+		CPU_GO(ANTIC_NMI_C);
+		CPU_NMI();
+	}
+	ANTIC_xpos += ANTIC_DMAR;
+	GOEOL;
+
+	do {
+		POKEY_Scanline();		/* check and generate IRQ */
+		OVERSCREEN_LINE;
+	} while (ANTIC_ypos < max_ypos);
+	ANTIC_ypos = 0; /* just for monitor.c */
+}
+
+#ifdef NEW_CYCLE_EXACT
+
+/* update the scanline from the last changed position to the current
+position, when a change was made to a display register during drawing */
+void ANTIC_UpdateScanline(void)
+{
+	int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+        int oldpos = ANTIC_cur_screen_pos;
+	ANTIC_cur_screen_pos = actual_xpos * 2 - 37;
+	draw_partial_scanline(oldpos, ANTIC_cur_screen_pos);
+}
+
+/* prior needs a different adjustment and could generate small glitches
+between mode changes */
+/* TODO: support glitches between mode changes (tiny areas that are neither
+the new mode nor the old mode, which occur between mode changes */
+void ANTIC_UpdateScanlinePrior(UBYTE byte)
+{
+	int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+	int prior_mode_adj = 2;
+	int oldpos = ANTIC_cur_screen_pos;
+	ANTIC_cur_screen_pos = actual_xpos * 2 - 37 + prior_mode_adj;
+	draw_partial_scanline(oldpos, ANTIC_cur_screen_pos);
+}
+
+/* chbase needs a different adjustment */
+void update_scanline_chbase(void)
+{
+	int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+	int hscrol_adj = (IR & 0x10) ? ANTIC_HSCROL : 0;
+	int hscrollsb_adj = (hscrol_adj & 1);
+	int oldpos = ANTIC_cur_screen_pos;
+	int fontfetch_adj;
+	/* antic fetches character font data every 2 or 4 cycles */
+	/* we want to delay the change until the next fetch */
+	/* empirically determined: */
+	if (anticmode >= 2 && anticmode <= 5) {
+		fontfetch_adj = (((hscrol_adj >>1) - actual_xpos + 0) & 1) * 2 + 9;
+	}
+	else if (anticmode == 6 || anticmode == 7) {
+		fontfetch_adj = (((hscrol_adj >> 1) - actual_xpos + 2) & 3) * 2 + 9;
+	}
+	else {
+		fontfetch_adj = 0;
+	}
+	ANTIC_cur_screen_pos = actual_xpos * 2 - 37 + hscrollsb_adj + fontfetch_adj;
+	draw_partial_scanline(oldpos, ANTIC_cur_screen_pos);
+}
+
+/* chactl invert needs a different adjustment */
+void update_scanline_invert(void)
+{
+	int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+	int hscrol_adj = (IR & 0x10) ? ANTIC_HSCROL : 0;
+	int hscrollsb_adj = (hscrol_adj & 1);
+	int oldpos = ANTIC_cur_screen_pos;
+
+	/* empirically determined: adjustment of 4 */
+	ANTIC_cur_screen_pos = actual_xpos * 2 - 37 + hscrollsb_adj + 4;
+	draw_partial_scanline(oldpos, ANTIC_cur_screen_pos);
+}
+
+/* chactl blank needs a different adjustment */
+void update_scanline_blank(void)
+{
+	int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+	int hscrol_adj = (IR & 0x10) ? ANTIC_HSCROL : 0;
+	int hscrollsb_adj = (hscrol_adj & 1);
+	int oldpos = ANTIC_cur_screen_pos;
+
+	/* empirically determined: adjustment of 7 */
+	ANTIC_cur_screen_pos = actual_xpos * 2 - 37 + hscrollsb_adj + 7;
+	draw_partial_scanline(oldpos, ANTIC_cur_screen_pos);
+}
+
+static void set_dmactl_bug(void){
+	need_load = FALSE;
+	saved_draw_antic_ptr = draw_antic_ptr;
+	draw_antic_ptr_changed = 1;
+	if (anticmode == 2 || anticmode == 3 || anticmode == 0xf) {
+		draw_antic_ptr = draw_antic_2_dmactl_bug;
+		dmactl_bug_chdata = (anticmode == 0xf) ? 0 : antic_memory[ANTIC_margin + chars_read[md] - 1];
+	}
+	else {
+		draw_antic_ptr = draw_antic_0_dmactl_bug;
+	}
+}
+
+/* draw a partial scanline between point l and point r */
+/* l is the left hand word, r is the point one past the right-most word to draw */
+void draw_partial_scanline(int l, int r)
+{
+	/* lborder_chars: save left border chars,we restore it after */
+	/*                it is the number of 8pixel 'chars' in the left border */
+	int lborder_chars = left_border_chars;
+
+	/* rborder_start: save right border start, we restore it after */
+	/*                it is the start of the right border, in words */
+	int rborder_start = right_border_start;
+
+	/* lborder_start: start of the left border, in words */
+	int lborder_start = LCHOP * 4;
+	/* end of the left border, in words */
+	int lborder_end = LCHOP * 4 + left_border_chars * 4;
+	/* end of the right border, in words */
+	int rborder_end = (48 - RCHOP) * 4;
+	/* flag: if true, don't show playfield. used if the partial scanline */
+	/*    does not include the playfield */
+	int dont_display_playfield = 0;
+	/* offset of the left most drawable 8 pixel pf block */
+	/* int l_pfchar = (lborder_end - x_min[md]) / 4; */
+	int l_pfchar = 0;
+	/* offset of the right most drawable 8 pixel pf plock, *plus one* */
+	int r_pfchar = 0;
+	/* buffer to save 0,1,2 or 3 words of the left hand portion of an 8pixel */
+	/* 'char' which is going to be erased by the left hand side of the */
+	/* left most 8pixel 'char' in the partial scanline and must be saved */
+	/* and restored later */
+	UWORD sv_buf[4];
+	/* buffer to save 0 or 1 (modes 6,7,a,b,c) ,or , (0,1,2 or 3) (modes 8,9) */
+	/* 8pixel 'chars' of playfield which is going to be erased by the left */
+	/* hand most 8pixel 'char's of the 2(modes 67abc) or 4(modes 89) 8pixel */
+	/* 'char'-sized blocks that these modes must draw. */
+	UWORD sv_buf2[4 * 4]; /* for modes 6,7,8,9,a,b,c */
+	/* start,size of the above buffers */
+	int sv_bufstart = 0;
+	int sv_bufsize = 0;
+	int sv_bufstart2 = 0;
+	int sv_bufsize2 = 0;
+	/* number of 8,16,32pixel chars to draw in the playfield */
+	int nchars = 0;
+	/* adjustment to ch_index , it is the number of 8,16,32pixel chars */
+	/* that we do not draw on the left hand side that would usually be drawn */
+	/* for this mode */
+	int ch_adj = 0;
+	/* adjustment to x_min to skip over the left side */
+	int x_min_adj = 0;
+	/* it's the offset of the left most drawable 8pixel pfblock which is */
+	/* rounded *down* to the nearest factor of (2:mode 67abc,4:mode 89) */
+	/* if it is divided by (2:mode 67abc,4:mode 89) it will give the */
+	/* offset of the left most drawable (16,32)pixel 'char' */
+	int l_pfactual = 0;
+	/* it is the offset of the right most drawable 8pixel pf block which is */
+	/* rounded *up* to the nearest factor of (2,4),  *plus one* */
+	/* so that r_pfactual-l_pfactual / (2,4) = number of 16,32 pixel 'chars' */
+	/* to be drawn */
+	int r_pfactual = 0;
+	/* it is the offset of the 8pixel block aligned with pf which overlaps */
+	/* the left border. We need this for modes 6-c, because in these modes */
+	/* the code will save 8pixel blocks to the left of l_pfchar and */
+	/* >= l_pfactual, which will result in portions of the left border */
+	/* being saved on some occasions which should not be, unless we */
+	/* use this variable to alter the number of chars saved */
+	/* int l_borderpfchar=0; */
+
+	r_pfchar = chars_displayed[md];
+	if (md == NORMAL1 || md == SCROLL1) { /* modes 6,7,a,b,c */
+		r_pfchar *= 2;
+	}
+	else if (md == NORMAL2 || md == SCROLL2) { /* modes 8,9 */
+		r_pfchar *= 4;
+	}
+	if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0) {
+		lborder_end = rborder_end;
+		dont_display_playfield = 1;
+	}
+	if (l > rborder_end)
+		l = rborder_end;
+	if (r > rborder_end)
+		r = rborder_end;
+	if (l < lborder_start)
+		l = lborder_start;
+	if (r < lborder_start)
+		r = lborder_start;
+	if (l >= r)
+		return;
+	if (l < lborder_end) {
+		/* left point is within left border */
+		sv_bufstart = (l & (~3)); /* high order bits give buffer start */
+		sv_bufsize = l - sv_bufstart;
+		left_border_start = sv_bufstart;
+		left_border_chars = lborder_chars - (sv_bufstart - lborder_start) / 4;
+		if (l > x_min[md]) {
+			/* special case for modes 56789abc */
+			/* position buffer within the reference frame */
+			/* of the playfield if that */
+			/* results in more pixels being saved in the buffer */
+			/* needed because for modes 5789abc the overlapping part */
+			/* can be more than 1 8pixel char and we only save the left */
+			/* hand most 8pixel chars in the code in the later section */
+			/* further down, so there is a possibility that the 8pixels */
+			/* which are saved within the reference frame of the border */
+			/* are not enough to ensure that everything gets saved */
+			l_pfchar = (l - x_min[md]) / 4;
+			if (((l - x_min[md]) & 3) > sv_bufsize) {
+				sv_bufsize = ((l - x_min[md]) & 3);
+				sv_bufstart = l - sv_bufsize;
+			}
+		}
+	}
+	else if (l >= rborder_start) {
+		sv_bufstart = (l & (~3)); /* high order bits give buffer start */
+		sv_bufsize = l - sv_bufstart;
+		right_border_start = sv_bufstart;
+		dont_display_playfield = 1; /* don't display the playfield */
+	}
+	else { /*within screen */
+		sv_bufsize = ((l - x_min[md]) & 3); /* low bits have buf size */
+		sv_bufstart = l - sv_bufsize; /* difference gives start */
+		l_pfchar = (sv_bufstart - x_min[md]) / 4;
+		left_border_chars = 0; /* don't display left border */
+	}
+	memcpy(sv_buf, scrn_ptr + sv_bufstart, sv_bufsize * sizeof(UWORD)); /* save part of screen */
+
+	if (r <= lborder_end) {
+		/* right_end_char = (r + 3) / 4; */
+		left_border_chars = (r + 3) / 4 - sv_bufstart / 4;
+		/* everything must be within the left border */
+		dont_display_playfield = 1; /* don't display the playfield */
+	}
+	else { /* right point is past start of playfield */
+		/* now load ANTIC data: needed for ANTIC glitches */
+		if (need_load) {
+			antic_load();
+#ifdef USE_CURSES
+			/* Normally, we would call curses_display_line here,
+			   and not use scanlines_to_curses_display at all.
+			   That would however cause incorrect color of the "MEMORY"
+			   menu item in Self Test - it isn't set properly
+			   in the first scanline. We therefore postpone
+			   curses_display_line call to the next scanline. */
+			scanlines_to_curses_display = 1;
+#endif
+			need_load = FALSE;
+		}
+
+		if (r > rborder_start) {
+			right_border_end = ((r + 3) & (~3)); /* round up to nearest 8pixel */
+		}
+		else {
+			r_pfchar = (r - x_min[md] + 3) / 4; /* round up to nearest 8pixel */
+		}
+	}
+	if (dont_display_playfield) {
+		nchars = 0;
+		x_min_adj = 0;
+		ch_adj = 0;
+	}
+	else if (md == NORMAL1 || md == SCROLL1) { /* modes 6,7,a,b,c */
+		l_pfactual = (l_pfchar & (~1)); /* round down to nearest 16pixel */
+		sv_bufsize2 = (l_pfchar - l_pfactual) * 4;
+		sv_bufstart2 = x_min[md] + l_pfactual * 4;
+		r_pfactual = ((r_pfchar + 1) & (~1)); /* round up to nearest 16pixel */
+		nchars = (r_pfactual - l_pfactual) / 2;
+		x_min_adj = l_pfactual * 4;
+		ch_adj = l_pfactual / 2;
+	}
+	else if (md == NORMAL2 || md == SCROLL2) { /* modes 8,9 */
+		l_pfactual = (l_pfchar & (~3));
+		sv_bufsize2 = (l_pfchar - l_pfactual) * 4;
+		sv_bufstart2 = x_min[md] + l_pfactual * 4;
+		r_pfactual = ((r_pfchar + 3) & (~3));
+		nchars = (r_pfactual - l_pfactual) / 4;
+		x_min_adj = l_pfactual * 4;
+		ch_adj = l_pfactual / 4;
+	}
+	else {
+		nchars = r_pfchar - l_pfchar;
+		x_min_adj = l_pfchar * 4;
+		ch_adj = l_pfchar;
+	}
+	memcpy(sv_buf2, scrn_ptr + sv_bufstart2, sv_bufsize2 * sizeof(UWORD)); /* save part of screen */
+
+	if (dont_display_playfield) {
+/* the idea here is to use draw_antic_0_ptr() to draw just the border only, since */
+/* we can't set nchars=0.  draw_antic_0_ptr will work if left_border_start and */
+/* right_border_end are set correctly */
+		if (anticmode < 2 || (ANTIC_DMACTL & 3) == 0 || r <= lborder_end) {
+			right_border_end = left_border_start + left_border_chars * 4;
+		}
+		else if (l >= rborder_start) {
+			left_border_start = right_border_start;
+		}
+		draw_antic_0_ptr();
+	}
+	else {
+		draw_antic_ptr(nchars, /* chars_displayed[md], */
+			antic_memory + ANTIC_margin + ch_offset[md] + ch_adj,
+			scrn_ptr + x_min[md] + x_min_adj,
+			(ULONG *) &GTIA_pm_scanline[x_min[md] + x_min_adj]);
+	}
+	memcpy(scrn_ptr + sv_bufstart2, sv_buf2, sv_bufsize2 * sizeof(UWORD)); /* restore screen */
+	memcpy(scrn_ptr + sv_bufstart, sv_buf, sv_bufsize * sizeof(UWORD)); /* restore screen */
+
+	/* restore border global variables */
+	left_border_chars=lborder_chars;
+	right_border_start=rborder_start;
+	left_border_start = LCHOP * 4;
+	right_border_end = (48-RCHOP)  *4;
+}
+#endif /* NEW_CYCLE_EXACT */
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+/* ANTIC registers --------------------------------------------------------- */
+
+UBYTE ANTIC_GetByte(UWORD addr, int no_side_effects)
+{
+	switch (addr & 0xf) {
+	case ANTIC_OFFSET_VCOUNT:
+		if (ANTIC_XPOS < ANTIC_LINE_C)
+			return ANTIC_ypos >> 1;
+		if (ANTIC_ypos + 1 < max_ypos)
+			return (ANTIC_ypos + 1) >> 1;
+		return 0;
+	case ANTIC_OFFSET_PENH:
+		return PENH;
+	case ANTIC_OFFSET_PENV:
+		return PENV;
+	case ANTIC_OFFSET_NMIST:
+		return ANTIC_NMIST;
+	default:
+		return 0xff;
+	}
+}
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+
+/* GTIA calls it on write to PRIOR */
+void ANTIC_SetPrior(UBYTE byte)
+{
+	if ((byte ^ GTIA_PRIOR) & 0x0f) {
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+		UBYTE col = 0;
+		UBYTE col2 = 0;
+		UBYTE hi;
+		UBYTE hi2;
+		if ((byte & 3) == 0) {
+			col = GTIA_COLPF0;
+			col2 = GTIA_COLPF1;
+		}
+		if ((byte & 0xc) == 0) {
+			ANTIC_cl[C_PF0 | C_PM0] = colour_translation_table[col | GTIA_COLPM0];
+			ANTIC_cl[C_PF0 | C_PM1] = colour_translation_table[col | GTIA_COLPM1];
+			ANTIC_cl[C_PF0 | C_PM01] = colour_translation_table[col | GTIA_COLPM0 | GTIA_COLPM1];
+			ANTIC_cl[C_PF1 | C_PM0] = colour_translation_table[col2 | GTIA_COLPM0];
+			ANTIC_cl[C_PF1 | C_PM1] = colour_translation_table[col2 | GTIA_COLPM1];
+			ANTIC_cl[C_PF1 | C_PM01] = colour_translation_table[col2 | GTIA_COLPM0 | GTIA_COLPM1];
+		}
+		else {
+			ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF0 | C_PM0] = colour_translation_table[col];
+			ANTIC_cl[C_PF1 | C_PM01] = ANTIC_cl[C_PF1 | C_PM1] = ANTIC_cl[C_PF1 | C_PM0] = colour_translation_table[col2];
+		}
+		if (byte & 4) {
+			ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PF2];
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF3 | C_PM0] = ANTIC_cl[C_PF3];
+			ANTIC_cl[C_HI2 | C_PM01] = ANTIC_cl[C_HI2 | C_PM1] = ANTIC_cl[C_HI2 | C_PM0] = ANTIC_cl[C_HI2];
+		}
+		else {
+			ANTIC_cl[C_PF3 | C_PM0] = ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PM0];
+			ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PM1];
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PM01];
+			ANTIC_cl[C_HI2 | C_PM0] = colour_translation_table[(GTIA_COLPM0 & 0xf0) | (GTIA_COLPF1 & 0xf)];
+			ANTIC_cl[C_HI2 | C_PM1] = colour_translation_table[(GTIA_COLPM1 & 0xf0) | (GTIA_COLPF1 & 0xf)];
+			ANTIC_cl[C_HI2 | C_PM01] = colour_translation_table[((GTIA_COLPM0 | GTIA_COLPM1) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+		}
+		col = col2 = 0;
+		hi = hi2 = GTIA_COLPF1 & 0xf;
+		ANTIC_cl[C_BLACK - C_PF2 + C_HI2] = colour_translation_table[hi];
+		if ((byte & 9) == 0) {
+			col = GTIA_COLPF2;
+			col2 = GTIA_COLPF3;
+			hi |= col & 0xf0;
+			hi2 |= col2 & 0xf0;
+		}
+		if ((byte & 6) == 0) {
+			ANTIC_cl[C_PF2 | C_PM2] = colour_translation_table[col | GTIA_COLPM2];
+			ANTIC_cl[C_PF2 | C_PM3] = colour_translation_table[col | GTIA_COLPM3];
+			ANTIC_cl[C_PF2 | C_PM23] = colour_translation_table[col | GTIA_COLPM2 | GTIA_COLPM3];
+			ANTIC_cl[C_PF3 | C_PM2] = colour_translation_table[col2 | GTIA_COLPM2];
+			ANTIC_cl[C_PF3 | C_PM3] = colour_translation_table[col2 | GTIA_COLPM3];
+			ANTIC_cl[C_PF3 | C_PM23] = colour_translation_table[col2 | GTIA_COLPM2 | GTIA_COLPM3];
+			ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[hi | (GTIA_COLPM2 & 0xf0)];
+			ANTIC_cl[C_HI2 | C_PM3] = colour_translation_table[hi | (GTIA_COLPM3 & 0xf0)];
+			ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[hi | ((GTIA_COLPM2 | GTIA_COLPM3) & 0xf0)];
+			ANTIC_cl[C_HI2 | C_PM25] = colour_translation_table[hi2 | (GTIA_COLPM2 & 0xf0)];
+			ANTIC_cl[C_HI2 | C_PM35] = colour_translation_table[hi2 | (GTIA_COLPM3 & 0xf0)];
+			ANTIC_cl[C_HI2 | C_PM235] = colour_translation_table[hi2 | ((GTIA_COLPM2 | GTIA_COLPM3) & 0xf0)];
+		}
+		else {
+			ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF2 | C_PM2] = colour_translation_table[col];
+			ANTIC_cl[C_PF3 | C_PM23] = ANTIC_cl[C_PF3 | C_PM3] = ANTIC_cl[C_PF3 | C_PM2] = colour_translation_table[col2];
+			ANTIC_cl[C_HI2 | C_PM23] = ANTIC_cl[C_HI2 | C_PM3] = ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[hi];
+		}
+#else /* USE_COLOUR_TRANSLATION_TABLE */
+		UWORD cword = 0;
+		UWORD cword2 = 0;
+		if ((byte & 3) == 0) {
+			cword = ANTIC_cl[C_PF0];
+			cword2 = ANTIC_cl[C_PF1];
+		}
+		if ((byte & 0xc) == 0) {
+			ANTIC_cl[C_PF0 | C_PM0] = cword | ANTIC_cl[C_PM0];
+			ANTIC_cl[C_PF0 | C_PM1] = cword | ANTIC_cl[C_PM1];
+			ANTIC_cl[C_PF0 | C_PM01] = cword | ANTIC_cl[C_PM01];
+			ANTIC_cl[C_PF1 | C_PM0] = cword2 | ANTIC_cl[C_PM0];
+			ANTIC_cl[C_PF1 | C_PM1] = cword2 | ANTIC_cl[C_PM1];
+			ANTIC_cl[C_PF1 | C_PM01] = cword2 | ANTIC_cl[C_PM01];
+		}
+		else {
+			ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF0 | C_PM0] = cword;
+			ANTIC_cl[C_PF1 | C_PM01] = ANTIC_cl[C_PF1 | C_PM1] = ANTIC_cl[C_PF1 | C_PM0] = cword2;
+		}
+		if (byte & 4) {
+			ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PF2];
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF3 | C_PM0] = ANTIC_cl[C_PF3];
+		}
+		else {
+			ANTIC_cl[C_PF3 | C_PM0] = ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PM0];
+			ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PM1];
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PM01];
+		}
+		cword = cword2 = 0;
+		if ((byte & 9) == 0) {
+			cword = ANTIC_cl[C_PF2];
+			cword2 = ANTIC_cl[C_PF3];
+		}
+		if ((byte & 6) == 0) {
+			ANTIC_cl[C_PF2 | C_PM2] = cword | ANTIC_cl[C_PM2];
+			ANTIC_cl[C_PF2 | C_PM3] = cword | ANTIC_cl[C_PM3];
+			ANTIC_cl[C_PF2 | C_PM23] = cword | ANTIC_cl[C_PM23];
+			ANTIC_cl[C_PF3 | C_PM2] = cword2 | ANTIC_cl[C_PM2];
+			ANTIC_cl[C_PF3 | C_PM3] = cword2 | ANTIC_cl[C_PM3];
+			ANTIC_cl[C_PF3 | C_PM23] = cword2 | ANTIC_cl[C_PM23];
+		}
+		else {
+			ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF2 | C_PM2] = cword;
+			ANTIC_cl[C_PF3 | C_PM23] = ANTIC_cl[C_PF3 | C_PM3] = ANTIC_cl[C_PF3 | C_PM2] = cword2;
+		}
+#endif /* USE_COLOUR_TRANSLATION_TABLE */
+		if (byte & 1) {
+			ANTIC_cl[C_PF1 | C_PM2] = ANTIC_cl[C_PF0 | C_PM2] = ANTIC_cl[C_PM2];
+			ANTIC_cl[C_PF1 | C_PM3] = ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PM3];
+			ANTIC_cl[C_PF1 | C_PM23] = ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PM23];
+		}
+		else {
+			ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PF0 | C_PM2] = ANTIC_cl[C_PF0];
+			ANTIC_cl[C_PF1 | C_PM23] = ANTIC_cl[C_PF1 | C_PM3] = ANTIC_cl[C_PF1 | C_PM2] = ANTIC_cl[C_PF1];
+		}
+		if ((byte & 0xf) == 0xc) {
+			ANTIC_cl[C_PF0 | C_PM0123] = ANTIC_cl[C_PF0 | C_PM123] = ANTIC_cl[C_PF0 | C_PM023] = ANTIC_cl[C_PF0];
+			ANTIC_cl[C_PF1 | C_PM0123] = ANTIC_cl[C_PF1 | C_PM123] = ANTIC_cl[C_PF1 | C_PM023] = ANTIC_cl[C_PF1];
+		}
+		else
+			ANTIC_cl[C_PF0 | C_PM0123] = ANTIC_cl[C_PF0 | C_PM123] = ANTIC_cl[C_PF0 | C_PM023] =
+			ANTIC_cl[C_PF1 | C_PM0123] = ANTIC_cl[C_PF1 | C_PM123] = ANTIC_cl[C_PF1 | C_PM023] = GTIA_COLOUR_BLACK;
+		if (byte & 0xf) {
+			ANTIC_cl[C_PF0 | C_PM25] = ANTIC_cl[C_PF0];
+			ANTIC_cl[C_PF1 | C_PM25] = ANTIC_cl[C_PF1];
+			ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = GTIA_COLOUR_BLACK;
+		}
+		else {
+			ANTIC_cl[C_PF0 | C_PM235] = ANTIC_cl[C_PF0 | C_PM35] = ANTIC_cl[C_PF0 | C_PM25] =
+			ANTIC_cl[C_PF1 | C_PM235] = ANTIC_cl[C_PF1 | C_PM35] = ANTIC_cl[C_PF1 | C_PM25] = ANTIC_cl[C_PF3];
+			ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = ANTIC_cl[C_PF3 | C_PM2];
+			ANTIC_cl[C_PF3 | C_PM35] = ANTIC_cl[C_PF2 | C_PM35] = ANTIC_cl[C_PM35] = ANTIC_cl[C_PF3 | C_PM3];
+			ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23];
+		}
+	}
+	pm_lookup_ptr = pm_lookup_table[prior_to_pm_lookup[byte & 0x3f]];
+	draw_antic_0_ptr = byte < 0x80 ? draw_antic_0 : byte < 0xc0 ? draw_antic_0_gtia10 : draw_antic_0_gtia11;
+	if (byte < 0x40 && (GTIA_PRIOR >= 0x40 || gtia_bug_active) && (anticmode == 2 || anticmode == 3 || anticmode == 0xf) && ANTIC_XPOS >= ((ANTIC_DMACTL & 3) == 3 ? 16 : 18)) {
+		/* A GTIA Mode was active, and no longer is.  An ANTIC hi-res mode is being used. GTIA is no longer set in hi-res mode */
+		if (anticmode == 2 || anticmode == 3) draw_antic_ptr = draw_antic_2_gtia_bug;
+		else if (anticmode == 0xf) draw_antic_ptr = draw_antic_f_gtia_bug;
+		gtia_bug_active = TRUE;
+	}
+	else
+		draw_antic_ptr = draw_antic_table[byte >> 6][anticmode];
+}
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+void ANTIC_PutByte(UWORD addr, UBYTE byte)
+{
+	switch (addr & 0xf) {
+	case ANTIC_OFFSET_DLISTL:
+		ANTIC_dlist = (ANTIC_dlist & 0xff00) | byte;
+		break;
+	case ANTIC_OFFSET_DLISTH:
+		ANTIC_dlist = (ANTIC_dlist & 0x00ff) | (byte << 8);
+		break;
+	case ANTIC_OFFSET_DMACTL:
+/* TODO: make this truly cycle-exact, update cpu2antic and antic2cpu,
+add support for wider->narrow glitches including the interesting mode 6
+glitch */
+#ifdef NEW_CYCLE_EXACT
+		dmactl_changed=0;
+		/* has DMACTL width changed?  */
+		if ((byte & 3) != (ANTIC_DMACTL & 3) ){
+			/* DMACTL width changed from 0 */
+			if ((ANTIC_DMACTL & 3) == 0) {
+				int glitch_cycle = (3 + 32) - 8*(byte & 3);
+				int x = ANTIC_XPOS;
+				if((IR & 0x10) && ((byte & 3) != 3)){
+					/*adjust for narrow or std HSCROL*/
+				       	glitch_cycle -= 8;
+				}
+				/*ANTIC doesn't fetch and display data if the*/
+				/*DMACTL width changes from zero after this */
+				/*cycle.  Instead, it displays a blank scan */
+				/*line for modes other than 23F and for 23F */
+				/*it displays a glitched line after the change*/
+				if(x >= glitch_cycle){
+					if(ANTIC_DRAWING_SCREEN){
+						ANTIC_UpdateScanline();
+					        set_dmactl_bug();
+					}
+				}
+				else {
+					if (ANTIC_DRAWING_SCREEN) {
+						ANTIC_UpdateScanline();
+					}
+				}
+			}
+			/* DMACTL width changed to 0 */
+			else if ((byte & 3)==0)  {
+				/* TODO: this is not 100% correct */
+				if (ANTIC_DRAWING_SCREEN) {
+					int actual_xpos = ANTIC_cpu2antic_ptr[ANTIC_xpos];
+					int antic_limit = ANTIC_cpu2antic_ptr[ANTIC_xpos_limit];
+					ANTIC_UpdateScanline();
+					/*fix for a minor glitch in fasteddie*/
+					/*don't steal cycles after DMACTL off*/
+					ANTIC_cpu2antic_ptr = &CYCLE_MAP_cpu2antic[0];
+					ANTIC_antic2cpu_ptr = &CYCLE_MAP_antic2cpu[0];
+					ANTIC_xpos = ANTIC_antic2cpu_ptr[actual_xpos];
+					ANTIC_xpos_limit = ANTIC_antic2cpu_ptr[antic_limit];
+				}
+			/* DMACTL width has changed and not to 0 and not from 0 */
+			}
+			else {
+				/* DMACTL width has increased and no HSCROL */
+				if (((byte & 3) > (ANTIC_DMACTL & 3)) && !(IR & 0x10)) {
+					int x; /* the change cycle */
+					int left_glitch_cycle = 0;
+					int right_glitch_cycle = 0;
+					x = ANTIC_XPOS;
+					if (((ANTIC_DMACTL & 3) == 2) && ((byte & 3) == 3)) { /* Normal->Wide */
+						left_glitch_cycle = 11;
+						right_glitch_cycle = 18;
+					}
+					else if (((ANTIC_DMACTL & 3) == 1) && ((byte & 3) == 3)) { /* Narrow->Wide */
+						left_glitch_cycle = 11;
+						right_glitch_cycle = 26;
+					}
+					else if (((ANTIC_DMACTL & 3) == 1) && ((byte & 3) == 2)) { /* Narrow->Normal */
+						left_glitch_cycle = 19;
+						right_glitch_cycle = 27;
+					}
+					/* change occurs during drawing of line */
+					/* delay change till next line */
+					if (x > right_glitch_cycle) {
+						dmactl_changed = 1;
+						delayed_DMACTL = byte;
+						break;
+					/* change occurs during 'glitch' region */
+					}
+					else if (x >= left_glitch_cycle && x <= right_glitch_cycle && anticmode > 1) {
+						set_dmactl_bug();
+					}
+				}
+				else {
+					/* DMACTL width has decreased or HSCROL */
+					/* TODO: this is not 100% correct */
+					if (ANTIC_DRAWING_SCREEN) {
+						ANTIC_UpdateScanline();
+					}
+				}
+			}
+		}
+#endif /* NEW_CYCLE_EXACT */
+		ANTIC_DMACTL = byte;
+#if defined(BASIC) || defined(CURSES_BASIC)
+		break;
+#else
+		switch (byte & 0x03) {
+		case 0x00:
+			/* no antic_load when screen off */
+			/* chars_read[NORMAL0] = 0;
+			chars_read[NORMAL1] = 0;
+			chars_read[NORMAL2] = 0;
+			chars_read[SCROLL0] = 0;
+			chars_read[SCROLL1] = 0;
+			chars_read[SCROLL2] = 0; */
+			/* no draw_antic_* when screen off */
+			/* chars_displayed[NORMAL0] = 0;
+			chars_displayed[NORMAL1] = 0;
+			chars_displayed[NORMAL2] = 0;
+			chars_displayed[SCROLL0] = 0;
+			chars_displayed[SCROLL1] = 0;
+			chars_displayed[SCROLL2] = 0;
+			x_min[NORMAL0] = 0;
+			x_min[NORMAL1] = 0;
+			x_min[NORMAL2] = 0;
+			x_min[SCROLL0] = 0;
+			x_min[SCROLL1] = 0;
+			x_min[SCROLL2] = 0;
+			ch_offset[NORMAL0] = 0;
+			ch_offset[NORMAL1] = 0;
+			ch_offset[NORMAL2] = 0;
+			ch_offset[SCROLL0] = 0;
+			ch_offset[SCROLL1] = 0;
+			ch_offset[SCROLL2] = 0; */
+			/* no borders when screen off, only background */
+			/* left_border_chars = 48 - LCHOP - RCHOP;
+			right_border_start = 0; */
+			break;
+		case 0x01:
+			chars_read[NORMAL0] = 32;
+			chars_read[NORMAL1] = 16;
+			chars_read[NORMAL2] = 8;
+			chars_read[SCROLL0] = 40;
+			chars_read[SCROLL1] = 20;
+			chars_read[SCROLL2] = 10;
+			chars_displayed[NORMAL0] = 32;
+			chars_displayed[NORMAL1] = 16;
+			chars_displayed[NORMAL2] = 8;
+			x_min[NORMAL0] = 32;
+			x_min[NORMAL1] = 32;
+			x_min[NORMAL2] = 32;
+			ch_offset[NORMAL0] = 0;
+			ch_offset[NORMAL1] = 0;
+			ch_offset[NORMAL2] = 0;
+			font_cycles[NORMAL0] = load_cycles[NORMAL0] = 32;
+			font_cycles[NORMAL1] = load_cycles[NORMAL1] = 16;
+			load_cycles[NORMAL2] = 8;
+			before_cycles[NORMAL0] = BEFORE_CYCLES;
+			before_cycles[SCROLL0] = BEFORE_CYCLES + 8;
+			extra_cycles[NORMAL0] = 7 + BEFORE_CYCLES;
+			extra_cycles[SCROLL0] = 8 + BEFORE_CYCLES + 8;
+			left_border_chars = 8 - LCHOP;
+			right_border_start = (ATARI_WIDTH - 64) / 2;
+			break;
+		case 0x02:
+			chars_read[NORMAL0] = 40;
+			chars_read[NORMAL1] = 20;
+			chars_read[NORMAL2] = 10;
+			chars_read[SCROLL0] = 48;
+			chars_read[SCROLL1] = 24;
+			chars_read[SCROLL2] = 12;
+			chars_displayed[NORMAL0] = 40;
+			chars_displayed[NORMAL1] = 20;
+			chars_displayed[NORMAL2] = 10;
+			x_min[NORMAL0] = 16;
+			x_min[NORMAL1] = 16;
+			x_min[NORMAL2] = 16;
+			ch_offset[NORMAL0] = 0;
+			ch_offset[NORMAL1] = 0;
+			ch_offset[NORMAL2] = 0;
+			font_cycles[NORMAL0] = load_cycles[NORMAL0] = 40;
+			font_cycles[NORMAL1] = load_cycles[NORMAL1] = 20;
+			load_cycles[NORMAL2] = 10;
+			before_cycles[NORMAL0] = BEFORE_CYCLES + 8;
+			before_cycles[SCROLL0] = BEFORE_CYCLES + 16;
+			extra_cycles[NORMAL0] = 8 + BEFORE_CYCLES + 8;
+			extra_cycles[SCROLL0] = 7 + BEFORE_CYCLES + 16;
+			left_border_chars = 4 - LCHOP;
+			right_border_start = (ATARI_WIDTH - 32) / 2;
+			break;
+		case 0x03:
+			chars_read[NORMAL0] = 48;
+			chars_read[NORMAL1] = 24;
+			chars_read[NORMAL2] = 12;
+			chars_read[SCROLL0] = 48;
+			chars_read[SCROLL1] = 24;
+			chars_read[SCROLL2] = 12;
+			chars_displayed[NORMAL0] = 42;
+			chars_displayed[NORMAL1] = 22;
+			chars_displayed[NORMAL2] = 12;
+			x_min[NORMAL0] = 12;
+			x_min[NORMAL1] = 8;
+			x_min[NORMAL2] = 0;
+			ch_offset[NORMAL0] = 3;
+			ch_offset[NORMAL1] = 1;
+			ch_offset[NORMAL2] = 0;
+			font_cycles[NORMAL0] = load_cycles[NORMAL0] = 47;
+			font_cycles[NORMAL1] = load_cycles[NORMAL1] = 24;
+			load_cycles[NORMAL2] = 12;
+			before_cycles[NORMAL0] = BEFORE_CYCLES + 16;
+			before_cycles[SCROLL0] = BEFORE_CYCLES + 16;
+			extra_cycles[NORMAL0] = 7 + BEFORE_CYCLES + 16;
+			extra_cycles[SCROLL0] = 7 + BEFORE_CYCLES + 16;
+			left_border_chars = 3 - LCHOP;
+			right_border_start = (ATARI_WIDTH - 8) / 2;
+			break;
+		}
+
+		ANTIC_missile_dma_enabled = (byte & 0x0c);	/* no player dma without missile */
+		ANTIC_player_dma_enabled = (byte & 0x08);
+		singleline = (byte & 0x10);
+		ANTIC_player_flickering = ((ANTIC_player_dma_enabled | ANTIC_player_gra_enabled) == 0x02);
+		ANTIC_missile_flickering = ((ANTIC_missile_dma_enabled | ANTIC_missile_gra_enabled) == 0x01);
+
+		byte = ANTIC_HSCROL;	/* update horizontal scroll data */
+/* ******* FALLTHROUGH ******* */
+	case ANTIC_OFFSET_HSCROL:
+/* TODO: make this truely cycle exact, and update cpu2antic and antic2cpu */
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+		}
+#endif
+		ANTIC_HSCROL = byte &= 0x0f;
+		if (ANTIC_DMACTL & 3) {
+			chars_displayed[SCROLL0] = chars_displayed[NORMAL0];
+			ch_offset[SCROLL0] = 4 - (byte >> 2);
+			x_min[SCROLL0] = x_min[NORMAL0];
+			if (byte & 3) {
+				x_min[SCROLL0] += (byte & 3) - 4;
+				chars_displayed[SCROLL0]++;
+				ch_offset[SCROLL0]--;
+			}
+			chars_displayed[SCROLL2] = chars_displayed[NORMAL2];
+			if ((ANTIC_DMACTL & 3) == 3) {	/* wide playfield */
+				ch_offset[SCROLL0]--;
+				if (byte == 4 || byte == 12)
+					chars_displayed[SCROLL1] = 21;
+				else
+					chars_displayed[SCROLL1] = 22;
+				if (byte <= 4) {
+					x_min[SCROLL1] = byte + 8;
+					ch_offset[SCROLL1] = 1;
+				}
+				else if (byte <= 12) {
+					x_min[SCROLL1] = byte;
+					ch_offset[SCROLL1] = 0;
+				}
+				else {
+					x_min[SCROLL1] = byte - 8;
+					ch_offset[SCROLL1] = -1;
+				}
+				/* technically, the part below is wrong */
+				/* scrolling in mode 8,9 with HSCROL=13,14,15 */
+				/* will set x_min=13,14,15 > 4*LCHOP = 12 */
+				/* so that nothing is drawn on the far left side */
+				/* of the screen.  We could fix this, but only */
+				/* by setting x_min to be negative. */
+				x_min[SCROLL2] = byte;
+				ch_offset[SCROLL2] = 0;
+			}
+			else {
+				chars_displayed[SCROLL1] = chars_displayed[NORMAL1];
+				ch_offset[SCROLL1] = 2 - (byte >> 3);
+				x_min[SCROLL1] = x_min[NORMAL0];
+				if (byte) {
+					if (byte & 7) {
+						x_min[SCROLL1] += (byte & 7) - 8;
+						chars_displayed[SCROLL1]++;
+						ch_offset[SCROLL1]--;
+					}
+					x_min[SCROLL2] = x_min[NORMAL2] + byte - 16;
+					chars_displayed[SCROLL2]++;
+					ch_offset[SCROLL2] = 0;
+				}
+				else {
+					x_min[SCROLL2] = x_min[NORMAL2];
+					ch_offset[SCROLL2] = 1;
+				}
+			}
+
+			if (ANTIC_DMACTL & 2) {		/* normal & wide playfield */
+				load_cycles[SCROLL0] = 47 - (byte >> 2);
+				font_cycles[SCROLL0] = (47 * 4 + 1 - byte) >> 2;
+				load_cycles[SCROLL1] = (24 * 8 + 3 - byte) >> 3;
+				font_cycles[SCROLL1] = (24 * 8 + 1 - byte) >> 3;
+				load_cycles[SCROLL2] = byte < 0xc ? 12 : 11;
+			}
+			else {					/* narrow playfield */
+				font_cycles[SCROLL0] = load_cycles[SCROLL0] = 40;
+				font_cycles[SCROLL1] = load_cycles[SCROLL1] = 20;
+				load_cycles[SCROLL2] = 16;
+			}
+		}
+		break;
+	case ANTIC_OFFSET_VSCROL:
+		ANTIC_VSCROL = byte & 0x0f;
+		if (vscrol_off) {
+			lastline = ANTIC_VSCROL;
+			if (ANTIC_XPOS < VSCOF_C)
+				need_dl = dctr == lastline;
+		}
+		break;
+	case ANTIC_OFFSET_PMBASE:
+		ANTIC_PMBASE = byte;
+		pmbase_d = (byte & 0xfc) << 8;
+		pmbase_s = pmbase_d & 0xf8ff;
+		break;
+	case ANTIC_OFFSET_CHACTL:
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+			update_scanline_invert();
+		}
+#endif
+		invert_mask = byte & 2 ? 0x80 : 0;
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+			update_scanline_blank();
+		}
+#endif
+		blank_mask = byte & 1 ? 0xe0 : 0x60;
+		if ((ANTIC_CHACTL ^ byte) & 4) {
+#ifdef NEW_CYCLE_EXACT
+			if (ANTIC_DRAWING_SCREEN) {
+				/* timing for flip is the same as chbase */
+				update_scanline_chbase();
+			}
+#endif
+			chbase_20 ^= 7;
+		}
+		ANTIC_CHACTL = byte;
+		break;
+	case ANTIC_OFFSET_CHBASE:
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+			update_scanline_chbase();
+		}
+#endif
+		ANTIC_CHBASE = byte;
+		chbase_20 = (byte & 0xfe) << 8;
+		if (ANTIC_CHACTL & 4)
+			chbase_20 ^= 7;
+		break;
+#endif /* defined(BASIC) || defined(CURSES_BASIC) */
+	case ANTIC_OFFSET_WSYNC:
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+			if (ANTIC_xpos <= ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C] && ANTIC_xpos_limit >= ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C])
+				if (ANTIC_cpu2antic_ptr[ANTIC_xpos + 1] == ANTIC_cpu2antic_ptr[ANTIC_xpos] + 1) {
+					/* antic does not steal the current cycle */
+/* note that if ANTIC_WSYNC_C is a stolen cycle, then ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C+1]-1 corresponds
+to the last cpu cycle < ANTIC_WSYNC_C.  Then the cpu will see this cycle if WSYNC
+is not delayed, since it really occurred one cycle after the STA WSYNC.  But if
+WSYNC is "delayed" then ANTIC_xpos is the next cpu cycle after ANTIC_WSYNC_C (which was stolen
+), so it is one greater than the above value.  EG if ANTIC_WSYNC_C=10 and is stolen
+(and let us say cycle 9,11 are also stolen, and 8,12 are not), then in the first
+case we have ANTIC_cpu2antic_ptr[ANTIC_WSYNC_C+1]-1 = 8 and in the 2nd =12  */
+					ANTIC_xpos = ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C + 1] - 1;
+				}
+				else {
+					ANTIC_xpos = ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C + 1];
+				}
+			else {
+				ANTIC_wsync_halt = TRUE;
+				ANTIC_xpos = ANTIC_xpos_limit;
+				if (ANTIC_cpu2antic_ptr[ANTIC_xpos + 1] == ANTIC_cpu2antic_ptr[ANTIC_xpos] + 1) {
+					/* antic does not steal the current cycle */
+					ANTIC_delayed_wsync = 0;
+				}
+				else {
+					ANTIC_delayed_wsync = 1;
+				}
+			}
+		}
+		else {
+			ANTIC_delayed_wsync = 0;
+#endif /* NEW_CYCLE_EXACT */
+			if (ANTIC_xpos <= ANTIC_WSYNC_C && ANTIC_xpos_limit >= ANTIC_WSYNC_C)
+				ANTIC_xpos = ANTIC_WSYNC_C;
+			else {
+				ANTIC_wsync_halt = TRUE;
+				ANTIC_xpos = ANTIC_xpos_limit;
+			}
+#ifdef NEW_CYCLE_EXACT
+		}
+#endif /* NEW_CYCLE_EXACT */
+		break;
+	case ANTIC_OFFSET_NMIEN:
+		ANTIC_NMIEN = byte;
+		break;
+	case ANTIC_OFFSET_NMIRES:
+		ANTIC_NMIST = 0x1f;
+		break;
+	default:
+		break;
+	}
+}
+
+/* State ------------------------------------------------------------------- */
+
+#ifndef BASIC
+
+void ANTIC_StateSave(void)
+{
+	StateSav_SaveUBYTE(&ANTIC_DMACTL, 1);
+	StateSav_SaveUBYTE(&ANTIC_CHACTL, 1);
+	StateSav_SaveUBYTE(&ANTIC_HSCROL, 1);
+	StateSav_SaveUBYTE(&ANTIC_VSCROL, 1);
+	StateSav_SaveUBYTE(&ANTIC_PMBASE, 1);
+	StateSav_SaveUBYTE(&ANTIC_CHBASE, 1);
+	StateSav_SaveUBYTE(&ANTIC_NMIEN, 1);
+	StateSav_SaveUBYTE(&ANTIC_NMIST, 1);
+	StateSav_SaveUBYTE(&IR, 1);
+	StateSav_SaveUBYTE(&anticmode, 1);
+	StateSav_SaveUBYTE(&dctr, 1);
+	StateSav_SaveUBYTE(&lastline, 1);
+	StateSav_SaveUBYTE(&need_dl, 1);
+	StateSav_SaveUBYTE(&vscrol_off, 1);
+
+	StateSav_SaveUWORD(&ANTIC_dlist, 1);
+	StateSav_SaveUWORD(&screenaddr, 1);
+
+	StateSav_SaveINT(&ANTIC_xpos, 1);
+	StateSav_SaveINT(&ANTIC_xpos_limit, 1);
+	StateSav_SaveINT(&ANTIC_ypos, 1);
+}
+
+void ANTIC_StateRead(void)
+{
+	StateSav_ReadUBYTE(&ANTIC_DMACTL, 1);
+	StateSav_ReadUBYTE(&ANTIC_CHACTL, 1);
+	StateSav_ReadUBYTE(&ANTIC_HSCROL, 1);
+	StateSav_ReadUBYTE(&ANTIC_VSCROL, 1);
+	StateSav_ReadUBYTE(&ANTIC_PMBASE, 1);
+	StateSav_ReadUBYTE(&ANTIC_CHBASE, 1);
+	StateSav_ReadUBYTE(&ANTIC_NMIEN, 1);
+	StateSav_ReadUBYTE(&ANTIC_NMIST, 1);
+	StateSav_ReadUBYTE(&IR, 1);
+	StateSav_ReadUBYTE(&anticmode, 1);
+	StateSav_ReadUBYTE(&dctr, 1);
+	StateSav_ReadUBYTE(&lastline, 1);
+	StateSav_ReadUBYTE(&need_dl, 1);
+	StateSav_ReadUBYTE(&vscrol_off, 1);
+
+	StateSav_ReadUWORD(&ANTIC_dlist, 1);
+	StateSav_ReadUWORD(&screenaddr, 1);
+
+	StateSav_ReadINT(&ANTIC_xpos, 1);
+	StateSav_ReadINT(&ANTIC_xpos_limit, 1);
+	StateSav_ReadINT(&ANTIC_ypos, 1);
+
+	ANTIC_PutByte(ANTIC_OFFSET_DMACTL, ANTIC_DMACTL);
+	ANTIC_PutByte(ANTIC_OFFSET_CHACTL, ANTIC_CHACTL);
+	ANTIC_PutByte(ANTIC_OFFSET_PMBASE, ANTIC_PMBASE);
+	ANTIC_PutByte(ANTIC_OFFSET_CHBASE, ANTIC_CHBASE);
+}
+
+#endif /* BASIC */
diff --git a/MCUME_pico2/pico800/antic.h b/MCUME_pico2/pico800/antic.h
new file mode 100644
index 0000000..0a89e66
--- /dev/null
+++ b/MCUME_pico2/pico800/antic.h
@@ -0,0 +1,136 @@
+#ifndef ANTIC_H_
+#define ANTIC_H_
+
+#include "atari.h"
+/*
+ * Offset to registers in custom relative to start of antic memory addresses.
+ */
+
+#define ANTIC_OFFSET_DMACTL 0x00
+#define ANTIC_OFFSET_CHACTL 0x01
+#define ANTIC_OFFSET_DLISTL 0x02
+#define ANTIC_OFFSET_DLISTH 0x03
+#define ANTIC_OFFSET_HSCROL 0x04
+#define ANTIC_OFFSET_VSCROL 0x05
+#define ANTIC_OFFSET_PMBASE 0x07
+#define ANTIC_OFFSET_CHBASE 0x09
+#define ANTIC_OFFSET_WSYNC 0x0a
+#define ANTIC_OFFSET_VCOUNT 0x0b
+#define ANTIC_OFFSET_PENH 0x0c
+#define ANTIC_OFFSET_PENV 0x0d
+#define ANTIC_OFFSET_NMIEN 0x0e
+#define ANTIC_OFFSET_NMIRES 0x0f
+#define ANTIC_OFFSET_NMIST 0x0f
+
+extern UBYTE ANTIC_CHACTL;
+extern UBYTE ANTIC_CHBASE;
+extern UWORD ANTIC_dlist;
+extern UBYTE ANTIC_DMACTL;
+extern UBYTE ANTIC_HSCROL;
+extern UBYTE ANTIC_NMIEN;
+extern UBYTE ANTIC_NMIST;
+extern UBYTE ANTIC_PMBASE;
+extern UBYTE ANTIC_VSCROL;
+
+extern int ANTIC_break_ypos;
+extern int ANTIC_ypos;
+extern int ANTIC_wsync_halt;
+
+/* Current clock cycle in a scanline.
+   Normally 0 <= ANTIC_xpos && ANTIC_xpos < ANTIC_LINE_C, but in some cases ANTIC_xpos >= ANTIC_LINE_C,
+   which means that we are already in line (ypos + 1). */
+extern int ANTIC_xpos;
+
+/* ANTIC_xpos limit for the currently running 6502 emulation. */
+extern int ANTIC_xpos_limit;
+
+/* Main clock value at the beginning of the current scanline. */
+extern unsigned int ANTIC_screenline_cpu_clock;
+
+/* Current main clock value. */
+#define ANTIC_CPU_CLOCK (ANTIC_screenline_cpu_clock + ANTIC_XPOS)
+
+#define ANTIC_NMIST_C	6
+#define ANTIC_NMI_C	12
+
+/* Number of cycles per scanline. */
+#define ANTIC_LINE_C   114
+
+/* STA WSYNC resumes here. */
+#define ANTIC_WSYNC_C  106
+
+/* Number of memory refresh cycles per scanline.
+   In the first scanline of a font mode there are actually less than ANTIC_DMAR
+   memory refresh cycles. */
+#define ANTIC_DMAR     9
+
+extern int ANTIC_artif_mode;
+extern int ANTIC_artif_new;
+
+extern UBYTE ANTIC_PENH_input;
+extern UBYTE ANTIC_PENV_input;
+
+int ANTIC_Initialise(void);
+void ANTIC_Reset(void);
+void ANTIC_Frame(int draw_display);
+UBYTE ANTIC_GetByte(UWORD addr, int no_side_effects);
+void ANTIC_PutByte(UWORD addr, UBYTE byte);
+
+UBYTE ANTIC_GetDLByte(UWORD *paddr);
+UWORD ANTIC_GetDLWord(UWORD *paddr);
+
+/* always call ANTIC_UpdateArtifacting after changing ANTIC_artif_mode */
+void ANTIC_UpdateArtifacting(void);
+
+/* Video memory access */
+void ANTIC_VideoMemset(UBYTE *ptr, UBYTE val, ULONG size);
+void ANTIC_VideoPutByte(UBYTE *ptr, UBYTE val);
+
+/* GTIA calls it on a write to PRIOR */
+void ANTIC_SetPrior(UBYTE prior);
+
+/* Saved states */
+void ANTIC_StateSave(void);
+void ANTIC_StateRead(void);
+
+/* Pointer to 16 KB seen by ANTIC in 0x4000-0x7fff.
+   If it's the same what the CPU sees (and what's in memory[0x4000..0x7fff],
+   then NULL. */
+extern const UBYTE *ANTIC_xe_ptr;
+
+/* PM graphics for GTIA */
+extern int ANTIC_player_dma_enabled;
+extern int ANTIC_missile_dma_enabled;
+extern int ANTIC_player_gra_enabled;
+extern int ANTIC_missile_gra_enabled;
+extern int ANTIC_player_flickering;
+extern int ANTIC_missile_flickering;
+
+/* ANTIC colour lookup tables, used by GTIA */
+extern UWORD ANTIC_cl[128];
+extern ULONG ANTIC_lookup_gtia9[16];
+extern ULONG ANTIC_lookup_gtia11[16];
+extern UWORD ANTIC_hires_lookup_l[128];
+
+#ifdef NEW_CYCLE_EXACT
+#define ANTIC_NOT_DRAWING -999
+#define ANTIC_DRAWING_SCREEN (ANTIC_cur_screen_pos!=ANTIC_NOT_DRAWING)
+extern int ANTIC_delayed_wsync;
+extern int ANTIC_cur_screen_pos;
+extern const int *ANTIC_cpu2antic_ptr;
+extern const int *ANTIC_antic2cpu_ptr;
+void ANTIC_UpdateScanline(void);
+void ANTIC_UpdateScanlinePrior(UBYTE byte);
+
+#define ANTIC_XPOS ( ANTIC_DRAWING_SCREEN ? ANTIC_cpu2antic_ptr[ANTIC_xpos] : ANTIC_xpos )
+#else
+#define ANTIC_XPOS ANTIC_xpos
+#endif /* NEW_CYCLE_EXACT */
+
+#ifndef NO_SIMPLE_PAL_BLENDING
+/* Set to 1 to enable simplified emulation of PAL blending, that uses only
+   the standard 8-bit palette. */
+extern int ANTIC_pal_blending;
+#endif /* NO_SIMPLE_PAL_BLENDING */
+
+#endif /* ANTIC_H_ */
diff --git a/MCUME_pico2/pico800/atari.h b/MCUME_pico2/pico800/atari.h
new file mode 100644
index 0000000..14891ca
--- /dev/null
+++ b/MCUME_pico2/pico800/atari.h
@@ -0,0 +1,102 @@
+#ifndef __ATARI__
+#define __ATARI__
+
+// define globals
+#define MEMORY_SIZE 0xC000 //0x10000
+
+#define ATARI_WIDTH  384
+#define ATARI_HEIGHT 240
+#define TV_PAL      312
+#define TV_NTSC     262
+
+//#define DIRTYRECT 1
+//#define WORDS_UNALIGNED_OK 1
+//#define ALTERNATE_LOOP_COUNTERS 1
+//#define NEW_CYCLE_EXACT 1
+//#define USE_CURSES 1
+//#define WORDS_BIGENDIAN 1
+//#define SYNCHRONIZED_SOUND 1 
+#define CLIP_SOUND 1 
+#define STEREO_SOUND 1 
+#define POKEYSND_SIGNED_SAMPLES 1
+#define PAGED_MEM 1
+#define SOUND 1
+#define NO_SIMPLE_PAL_BLENDING 1
+
+#define max_ypos    tv_mode
+
+extern int tv_mode;
+extern unsigned char INPUT_key_consol;
+
+enum ESCAPE {
+  ESC_SIOV,
+/*
+ * These are special device escape codes required by the Basic version
+ */
+  ESC_E_OPEN,
+  ESC_E_CLOSE,
+  ESC_E_READ,
+  ESC_E_WRITE,
+  ESC_E_STATUS,
+  ESC_E_SPECIAL,
+
+  ESC_K_OPEN,
+  ESC_K_CLOSE,
+  ESC_K_READ,
+  ESC_K_WRITE,
+  ESC_K_STATUS,
+  ESC_K_SPECIAL,
+/*
+ * These are Escape codes for the normal device handlers.
+ * Some are never used and some are only sometimes used.
+ */
+
+  ESC_PHOPEN = 0xb0,
+  ESC_PHCLOS = 0xb1,
+  ESC_PHREAD = 0xb2,
+  ESC_PHWRIT = 0xb3,
+  ESC_PHSTAT = 0xb4,
+  ESC_PHSPEC = 0xb5,
+  ESC_PHINIT = 0xb6,
+
+  ESC_HHOPEN = 0xc0,
+  ESC_HHCLOS = 0xc1,
+  ESC_HHREAD = 0xc2,
+  ESC_HHWRIT = 0xc3,
+  ESC_HHSTAT = 0xc4,
+  ESC_HHSPEC = 0xc5,
+  ESC_HHINIT = 0xc6,
+  ESC_BREAK = 0xff
+};
+
+#ifndef _TYPEDEF_H
+#define _TYPEDEF_H
+
+//data types
+#define UBYTE unsigned char
+#define UWORD unsigned short
+#define ULONG unsigned int
+
+#define SBYTE signed char
+#define SWORD signed short
+#define SLONG signed int
+
+#define int8  char
+#define int16 short
+#define int32 int
+
+#define uint8  unsigned int8
+#define uint16 unsigned int16
+#define uint32 unsigned int32
+#ifndef FALSE
+#define FALSE  0
+#endif
+#ifndef TRUE
+#define TRUE   1
+#endif
+
+#endif
+
+
+
+#endif
diff --git a/MCUME_pico2/pico800/atari800.c b/MCUME_pico2/pico800/atari800.c
new file mode 100644
index 0000000..2d7be53
--- /dev/null
+++ b/MCUME_pico2/pico800/atari800.c
@@ -0,0 +1,562 @@
+#define PROGMEM
+
+#include "atari800.h"
+#include <string.h>
+#include "memory.h"
+#include "cpu.h"
+#include "atari.h"
+#include "akey.h"
+#include "pokey.h"
+//#include "romatariosa.h"
+#include "romatariosb.h"
+//#include "romatarixl.h"
+#include "antic.h"
+#include "gtia.h"
+#include "pia.h"
+#include "colours.h"
+#include "emuapi.h"
+#if HAS_SND
+#include "pokeysnd.h"
+#endif
+#include "kbd.h"
+
+// Controllers
+typedef struct
+{ 
+  // All values are 1 or 0, or perhaps not...
+  int left;
+  int right;
+  int up;
+  int down;
+  int trig;
+
+} CONTROLLER;
+
+
+// global variables
+unsigned char mem[MEMORY_SIZE];
+unsigned char * memory=mem;
+int tv_mode = TV_PAL;
+UBYTE INPUT_key_consol;
+
+
+// local variables
+static CONTROLLER cont1, cont2;
+static int INPUT_key_code = AKEY_NONE;
+static int INPUT_key_shift = 0;
+
+/* MEMORY MAP                   INDEX  (0 is invalid)
+* 0-3FFF    RAM       (read/write)
+* 4000-7FFF RAM       (read/write)
+* 8000-9FFF BASIC     right CART 8K
+* A000-BFFF BASIC     left  CART 8K
+* D000-D0FF GTIA regs
+* D200-D2FF POKEY regs
+* D300-D3FF PIA  regs
+* D400-D4FF ANTIC regs
+* D800-FFFF OS ROM (ro)
+* E000    I/O expansion
+*/
+
+
+// memory CPU read (load) handler
+uint8 Atari_GetByte(uint16 addr)
+{
+  if (addr < MEMORY_SIZE) { // MAPPER_RAM
+      return(memory[addr]);
+  }
+  else if ( (addr >= 0xD000) && (addr < 0xD100) ) {  // MAPPER_GTIA
+      return GTIA_GetByte(addr,1);
+  } 
+  else if ( (addr >= 0xD200) && (addr < 0xD300) ) {  // MAPPER_POKEY
+      return POKEY_GetByte(addr,1);       
+  } 
+  else if ( (addr >= 0xD300) && (addr < 0xD400) ) {  // MAPPER_PIA
+      return PIA_GetByte(addr);       
+  } 
+  else if ( (addr >= 0xD400) && (addr < 0xD500) ) {  // MAPPER_ANTIC
+      return ANTIC_GetByte(addr,1);
+  }
+  else if ((addr >= 0xD800) && (addr < 0x10000)) {  // MAPPER_ROM (bios)
+      //return(memory[addr]);
+      return(romos[addr-0xD800]);
+  }
+
+  //case MAPPER_IOEXP:  // I/O exp read
+  //  return IOEXPread(addr);
+
+  return 0xff;
+}
+
+// memory CPU write (store) handler
+void Atari_PutByte(uint16 addr, uint8 byte)
+{
+  if (addr < 0x8000) { // MAPPER_RAM
+      memory[addr] = byte;
+  }
+  else if (addr < 0xC000) {  // MAPPER_ROM
+  }
+  else if ( (addr >= 0xD000) && (addr < 0xD100) ) {  // MAPPER_GTIA
+      GTIA_PutByte(addr, byte);    
+  } 
+  else if ( (addr >= 0xD200) && (addr < 0xD300)  ) {  // MAPPER_POKEY
+      POKEY_PutByte(addr, byte);                     
+  } 
+  else if ( (addr >= 0xD300) && (addr < 0xD400)  ) {  // MAPPER_PIA
+      PIA_PutByte(addr, byte);                     
+  } 
+  else if ( (addr >= 0xD400) && (addr < 0xD500) ) {  // MAPPER_ANTIC
+      ANTIC_PutByte(addr, byte);
+  }
+  
+  //case MAPPER_IOEXP:  // I/O exp write
+  //  IOEXPwrite(addr, byte);
+}
+
+
+static void INPUT_Frame(void)
+{
+  int i;
+  static int last_key_code = AKEY_NONE;
+  static int last_key_break = 0;
+
+  if (cont1.trig) GTIA_TRIG[0]=0; else GTIA_TRIG[0]=1;
+
+
+  i = (INPUT_key_code == AKEY_BREAK);
+  if (i && !last_key_break) {
+    if (POKEY_IRQEN & 0x80) {
+      POKEY_IRQST &= ~0x80;
+      CPU_GenerateIRQ();
+    }
+  }
+  last_key_break = i;
+  POKEY_SKSTAT |= 0xc;
+  if (INPUT_key_shift)
+    POKEY_SKSTAT &= ~8;
+
+  if (INPUT_key_code < 0) {
+    //if (CASSETTE_press_space) {
+    //  INPUT_key_code = AKEY_SPACE;
+    //  CASSETTE_press_space = 0;
+    //}
+    //else {
+      last_key_code = AKEY_NONE;
+    //}
+  }  
+  if ((INPUT_key_code&~0x17) == AKEY_SHFTCTRL) {
+    INPUT_key_code = AKEY_NONE;
+  }
+  if (INPUT_key_code >= 0) {    
+//emu_printi(INPUT_key_code);     
+    POKEY_SKSTAT &= ~4;
+    if ((INPUT_key_code ^ last_key_code) & ~AKEY_SHFTCTRL) {
+    /* ignore if only shift or control has changed its state */
+      last_key_code = INPUT_key_code;
+      POKEY_KBCODE = (UBYTE) INPUT_key_code;
+      if (POKEY_IRQEN & 0x40) {
+        if (POKEY_IRQST & 0x40) {       
+          POKEY_IRQST &= ~0x40;
+          CPU_GenerateIRQ();
+        }
+        else {
+          /* keyboard over-run */
+          POKEY_SKSTAT &= ~0x40;
+          /* assert(CPU_IRQ != 0); */
+        }
+      }
+    }
+  }  
+}
+
+// check keyboard and set kbcode on VBI (not for A800)
+void INPUT_Scanline(void)
+{
+//  if (cont1.trig) GTIA_TRIG[0]=0; else GTIA_TRIG[0]=1;
+}
+
+
+static void load_CART(char * cartname) 
+{
+  int flen = emu_FileSize(cartname);
+  int f=emu_FileOpen(cartname, "r+b");
+  if (flen < 16384) {
+    emu_printf("8k");
+    for(int i=0; i<flen; i++) memory[0xA000 + i] = emu_FileGetc(f);    
+  }
+  else {
+    emu_printf("16k");    
+    for(int i=0; i<flen; i++) memory[0x8000 + i] = emu_FileGetc(f);
+  }
+
+  emu_FileClose(f); 
+}
+
+  
+
+
+void add_esc(UWORD address, UBYTE esc_code)
+{
+  memory[address++] = 0xf2; /* ESC */
+  memory[address++] = esc_code; /* ESC CODE */
+  memory[address] = 0x60;   /* RTS */
+}
+
+int Atari_PORT(int num)
+{
+  int nibble_0 = 0xff;
+  int nibble_1 = 0xff;
+
+  if (num == 0)
+  {  
+    if (cont1.left) nibble_0 &= ~0x04;   
+    if (cont1.right) nibble_0 &= ~0x08;   
+    if (cont1.up) nibble_0 &= ~0x01;   
+    if (cont1.down) nibble_0 &= ~0x02;   
+    if (cont2.left) nibble_1 &= ~0x04;   
+    if (cont2.right) nibble_1 &= ~0x08;   
+    if (cont2.up) nibble_1 &= ~0x01;   
+    if (cont2.down) nibble_1 &= ~0x02;   
+  }
+  return (nibble_1 << 4) | nibble_0;
+}
+
+static void Initialise(void)
+{
+  int i;
+
+  emu_printf("Initialising ...");
+
+  // Set up memory area
+  memset(memory, 0, MEMORY_SIZE);
+  memset(memory+0x8000, 0xff, 0x4000);
+
+  // init controllers
+  memset(&cont1, 0, sizeof(CONTROLLER));
+  memset(&cont2, 0, sizeof(CONTROLLER));
+  
+
+  // Load bios to address 0xF800
+  //for (i = 0; i < 0x2800; i++)
+  //{
+  //  memory[0xD800 + i] = romos[i];
+  //}  
+  //add_esc(0xe459, ESC_SIOV);  
+}
+
+
+
+#define INV_KEY 255
+
+const unsigned char keyboardAsciiConv[] = // Ascii to ATARI keys
+{
+/* 0x00 */ INV_KEY,
+/* 0x01 */ INV_KEY,
+/* 0x02 */ INV_KEY,
+/* 0x03 */ INV_KEY,
+/* 0x04 */ INV_KEY,
+/* 0x05 */ INV_KEY,
+/* 0x06 */ INV_KEY,
+/* 0x07 */ INV_KEY,
+/* 0x08 */ INV_KEY,
+/* 0x09 */ 0x2C,      // tab
+/* 0x0A */ INV_KEY,
+/* 0x0B */ INV_KEY,
+/* 0x0C */ INV_KEY,
+/* 0x0D */ 0x0C,      // enter
+/* 0x0E */ INV_KEY,
+/* 0x0F */ INV_KEY,
+/* 0x10 */ INV_KEY,
+/* 0x11 */ INV_KEY,
+/* 0x12 */ INV_KEY,
+/* 0x13 */ INV_KEY,
+/* 0x14 */ INV_KEY,
+/* 0x15 */ INV_KEY,
+/* 0x16 */ INV_KEY,
+/* 0x17 */ INV_KEY,
+/* 0x18 */ INV_KEY,
+/* 0x19 */ INV_KEY,
+/* 0x1A */ INV_KEY,
+/* 0x1B */ INV_KEY,  // esc
+/* 0x1C */ INV_KEY,
+/* 0x1D */ INV_KEY,
+/* 0x1E */ INV_KEY,
+/* 0x1F */ INV_KEY,
+/* 0x20 */ 0x21,     // space
+/* 0x21 */ 95,       // ! exclamation mark
+/* 0x22 */ 94,       // " double quote   
+/* 0x23 */ 90,       // # dies
+/* 0x24 */ 88,       // $ dollar
+/* 0x25 */ 93,       // % percent
+/* 0x26 */ 91,       // & ampercent
+/* 0x27 */ INV_KEY,  // ' singlequote
+/* 0x28 */ 112,      // ( bracket left
+/* 0x29 */ 114,      // ) bracket right
+/* 0x2A */ 0x0E,     // * mult
+/* 0x2B */ 0x06,     // + plus
+/* 0x2C */ 0x20,     // , comma
+/* 0x2D */ 0x0E,     // - minus
+/* 0x2E */ 0x22,     // . period
+/* 0x2F */ 0x26,     // / slash
+/* 0x30 */ 0x32,     // 0
+/* 0x31 */ 0x1F,     // 1
+/* 0x32 */ 0x1E,     // 2 
+/* 0x33 */ 0x1A,     // 3 
+/* 0x34 */ 0x18,     // 4
+/* 0x35 */ 0x1D,     // 5
+/* 0x36 */ 0x1B,     // 6
+/* 0x37 */ 0x33,     // 7
+/* 0x38 */ 0x35,     // 8
+/* 0x39 */ 0x30,     // 9
+/* 0x3A */ 66,       // : colon
+/* 0x3B */ 0x02,     // ; semi colon
+/* 0x3C */ 0x36,     // <
+/* 0x3D */ 0x0F,     // = equal
+/* 0x3E */ 0x37,     // >
+/* 0x3F */ 102,      // ?
+/* 0x40 */ 117,      // @
+/* 0x41 */ INV_KEY,  // A
+/* 0x42 */ INV_KEY,  // B
+/* 0x43 */ INV_KEY,  // C
+/* 0x44 */ INV_KEY,  // D
+/* 0x45 */ INV_KEY,  // E
+/* 0x46 */ INV_KEY,  // F
+/* 0x47 */ INV_KEY,  // G
+/* 0x48 */ INV_KEY,  // H
+/* 0x49 */ INV_KEY,  // I
+/* 0x4A */ INV_KEY,  // J
+/* 0x4B */ INV_KEY,  // K
+/* 0x4C */ INV_KEY,  // L
+/* 0x4D */ INV_KEY,  // M
+/* 0x4E */ INV_KEY,  // N
+/* 0x4F */ INV_KEY,  // O
+/* 0x50 */ INV_KEY,  // P
+/* 0x51 */ INV_KEY,  // Q
+/* 0x52 */ INV_KEY,  // R
+/* 0x53 */ INV_KEY,  // S
+/* 0x54 */ INV_KEY,  // T
+/* 0x55 */ INV_KEY,  // U
+/* 0x56 */ INV_KEY,  // V
+/* 0x57 */ INV_KEY,  // W
+/* 0x58 */ INV_KEY,  // X
+/* 0x59 */ INV_KEY,  // Y
+/* 0x5A */ INV_KEY,  // Z
+/* 0x5B */ INV_KEY,  // square bracket open
+/* 0x5C */ INV_KEY,  // backslach
+/* 0x5D */ INV_KEY,  // square braquet close
+/* 0x5E */ INV_KEY,  // ^ circonflex
+/* 0x5F */ INV_KEY,  // _ undescore
+/* 0x60 */ INV_KEY,  // `backquote
+/* 0x61 */ 0x3F,     // a
+/* 0x62 */ 0x15,     // b
+/* 0x63 */ 0x12,     // c
+/* 0x64 */ 0x3A,     // d
+/* 0x65 */ 0x2A,     // e
+/* 0x66 */ 0x38,     // f
+/* 0x67 */ 0x3D,     // g
+/* 0x68 */ 0x39,     // h
+/* 0x69 */ 0x0D,     // i
+/* 0x6A */ 0x01,     // j
+/* 0x6B */ 0x05,     // k
+/* 0x6C */ 0x00,     // l
+/* 0x6D */ 0x25,     // m
+/* 0x6E */ 0x23,     // n
+/* 0x6F */ 0x08,     // o
+/* 0x70 */ 0x0A,     // p
+/* 0x71 */ 0x2F,     // q
+/* 0x72 */ 0x28,     // r
+/* 0x73 */ 0x3E,     // s
+/* 0x74 */ 0x2D,     // t
+/* 0x75 */ 0x0B,     // u
+/* 0x76 */ 0x10,     // v
+/* 0x77 */ 0x2E,     // w
+/* 0x78 */ 0x16,     // x
+/* 0x79 */ 0x2B,     // y
+/* 0x7A */ 0x17,     // z
+/* 0x7B */ INV_KEY,  // curly bracket open
+/* 0x7C */ INV_KEY,  // or
+/* 0x7D */ INV_KEY,  // curly bracket close  
+/* 0x7E */ INV_KEY,  // tilt
+/* 0x7F */ AKEY_BACKSPACE,     // backspace
+
+/* 0xC0 */ INV_KEY,
+/* 0xC1 */ INV_KEY,
+/* 0xC2 */ INV_KEY,   // F1
+/* 0xC3 */ INV_KEY,   // F2
+/* 0xC4 */ INV_KEY,   // F3
+/* 0xC5 */ INV_KEY,   // F4
+/* 0xC6 */ INV_KEY,   // F5
+/* 0xC7 */ INV_KEY,   // F6
+/* 0xC8 */ INV_KEY,   // F7
+/* 0xC9 */ INV_KEY,   // F8
+/* 0xCA */ INV_KEY,   // F9
+/* 0xCB */ INV_KEY,   // F10
+/* 0xCC */ INV_KEY,
+/* 0xCD */ INV_KEY,
+/* 0xCE */ INV_KEY,
+/* 0xCF */ INV_KEY,
+/* 0xD0 */ INV_KEY,
+/* 0xD1 */ INV_KEY,
+/* 0xD2 */ INV_KEY,
+/* 0xD3 */ INV_KEY,
+/* 0xD4 */ INV_KEY,   // DEL
+/* 0xD5 */ INV_KEY,
+/* 0xD6 */ INV_KEY,
+/* 0xD7 */ AKEY_UP,   // U
+/* 0xD8 */ AKEY_LEFT, // L
+/* 0xD9 */ AKEY_RIGHT,// R
+/* 0xDA */ AKEY_DOWN, // D
+/* 0xDB */ INV_KEY,
+/* 0xDC */ INV_KEY,
+/* 0xDD */ INV_KEY,
+/* 0xDE */ INV_KEY,
+/* 0xDF */ INV_KEY
+};
+
+
+static int ik;     // joypad key
+static int ihk;    // I2C keyboard key
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+void at8_Input(int click) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();   
+}
+
+#define R32(rgb) ((rgb>>16)&0xff) 
+#define G32(rgb) ((rgb>>8)&0xff) 
+#define B32(rgb) (rgb & 0xff) 
+
+void at8_Init(void)
+{
+   int i;
+
+  // Palette
+  for (i = 0; i < PALETTE_SIZE; i++)
+  {
+    emu_SetPaletteEntry(R32(colourtable[i]), G32(colourtable[i]), B32(colourtable[i]), i);
+  }
+
+#if HAS_SND
+  emu_sndInit();
+  POKEYSND_Init(POKEYSND_FREQ_17_APPROX, 44100, 1, POKEYSND_BIT16);
+#endif
+
+  emu_printf("Allocating RAM");
+  if (memory == NULL) memory = emu_Malloc(MEMORY_SIZE);
+
+  Initialise();
+}
+
+
+void at8_Step(void)
+{
+  int k  = ik;
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+    
+  CONTROLLER * which;
+  
+  if (k & 0x8000) which=&cont2;
+  else which=&cont1;
+
+  // Start
+  if (k & MASK_KEY_USER1)
+    INPUT_key_consol &= ~0x01;
+  else
+    INPUT_key_consol |= 0x01;   
+
+  // Select
+  if (k & MASK_KEY_USER2)
+    INPUT_key_consol &= ~0x02;
+  else
+    INPUT_key_consol |= 0x02;   
+
+  // OPTION
+  if (k & MASK_KEY_USER3)
+    INPUT_key_consol &= ~0x04;
+  else
+    INPUT_key_consol |= 0x04;   
+
+  if (hk != 0) {
+    int key = keyboardAsciiConv[hk];
+    if (key != INV_KEY) INPUT_key_code = key;  
+  }
+  else {
+    INPUT_key_code = AKEY_NONE;    
+  }
+  
+  // Keyboard
+  INPUT_Frame();
+
+  // Joystick side button, trigger and directions
+  if ( (k & MASK_JOY2_BTN) || (k & MASK_JOY1_BTN) )
+      which->trig = 1;    
+  else
+      which->trig = 0;
+  if ( (k & MASK_JOY2_DOWN) || (k & MASK_JOY1_DOWN) )
+      which->down = 1;
+  else
+      which->down = 0;
+  if ( (k & MASK_JOY2_UP) || (k & MASK_JOY1_UP) )
+      which->up = 1;
+  else
+      which->up = 0;
+  if ( (k & MASK_JOY2_LEFT) || (k & MASK_JOY1_LEFT) ) 
+      which->right = 1;
+  else
+      which->right = 0;
+  if ( (k & MASK_JOY2_RIGHT) || (k & MASK_JOY1_RIGHT) )
+      which->left = 1;
+  else
+      which->left = 0; 
+
+  GTIA_Frame();
+  ANTIC_Frame(1); 
+  emu_DrawVsync();
+  POKEY_Frame();
+}
+
+
+
+void at8_Start(char * cartname)
+{
+  load_CART(cartname);
+
+  emu_printf("antic");
+  ANTIC_Initialise();
+  emu_printf("gtia");  
+  GTIA_Initialise();
+  emu_printf("pia");
+  PIA_Initialise();  
+  emu_printf("pokey");
+  POKEY_Initialise();
+  PORTA = 0x00;
+  ANTIC_NMIEN = 0x00;
+  ANTIC_NMIST = 0x00;
+  memory[0x244] = 1;  
+  GTIA_TRIG[0]=1;
+  GTIA_TRIG[1]=1;
+  GTIA_TRIG[2]=1;
+  GTIA_TRIG[3]=1;
+  emu_printf("6502 reset");
+  CPU_Reset();
+    
+  emu_printf("init done");   
+}
diff --git a/MCUME_pico2/pico800/atari800.h b/MCUME_pico2/pico800/atari800.h
new file mode 100644
index 0000000..2db7482
--- /dev/null
+++ b/MCUME_pico2/pico800/atari800.h
@@ -0,0 +1,5 @@
+extern void at8_Init(void);
+extern void at8_Step(void);
+extern void at8_Start(char * filename);
+extern void at8_Input(int click);
+
diff --git a/MCUME_pico2/pico800/colours.h b/MCUME_pico2/pico800/colours.h
new file mode 100644
index 0000000..a31db53
--- /dev/null
+++ b/MCUME_pico2/pico800/colours.h
@@ -0,0 +1,68 @@
+const unsigned int colourtable[256] =
+{
+	0x0, 0x1c1c1c, 0x393939, 0x595959, 
+	0x797979, 0x929292, 0xababab, 0xbcbcbc, 
+	0xcdcdcd, 0xd9d9d9, 0xe6e6e6, 0xececec, 
+	0xf2f2f2, 0xf8f8f8, 0xffffff, 0xffffff, 
+	0x391701, 0x5e2304, 0x833008, 0xa54716, 
+	0xc85f24, 0xe37820, 0xff911d, 0xffab1d, 
+	0xffc51d, 0xffce34, 0xffd84c, 0xffe651, 
+	0xfff456, 0xfff977, 0xffff98, 0xffff98, 
+	0x451904, 0x721e11, 0x9f241e, 0xb33a20, 
+	0xc85122, 0xe36920, 0xff811e, 0xff8c25, 
+	0xff982c, 0xffae38, 0xffc545, 0xffc559, 
+	0xffc66d, 0xffd587, 0xffe4a1, 0xffe4a1, 
+	0x4a1704, 0x7e1a0d, 0xb21d17, 0xc82119, 
+	0xdf251c, 0xec3b38, 0xfa5255, 0xfc6161, 
+	0xff706e, 0xff7f7e, 0xff8f8f, 0xff9d9e, 
+	0xffabad, 0xffb9bd, 0xffc7ce, 0xffc7ce, 
+	0x50568, 0x3b136d, 0x712272, 0x8b2a8c, 
+	0xa532a6, 0xb938ba, 0xcd3ecf, 0xdb47dd, 
+	0xea51eb, 0xf45ff5, 0xfe6dff, 0xfe7afd, 
+	0xff87fb, 0xff95fd, 0xffa4ff, 0xffa4ff, 
+	0x280479, 0x400984, 0x590f90, 0x70249d, 
+	0x8839aa, 0xa441c3, 0xc04adc, 0xd054ed, 
+	0xe05eff, 0xe96dff, 0xf27cff, 0xf88aff, 
+	0xff98ff, 0xfea1ff, 0xfeabff, 0xfeabff, 
+	0x35088a, 0x420aad, 0x500cd0, 0x6428d0, 
+	0x7945d0, 0x8d4bd4, 0xa251d9, 0xb058ec, 
+	0xbe60ff, 0xc56bff, 0xcc77ff, 0xd183ff, 
+	0xd790ff, 0xdb9dff, 0xdfaaff, 0xdfaaff, 
+	0x51e81, 0x626a5, 0x82fca, 0x263dd4, 
+	0x444cde, 0x4f5aee, 0x5a68ff, 0x6575ff, 
+	0x7183ff, 0x8091ff, 0x90a0ff, 0x97a9ff, 
+	0x9fb2ff, 0xafbeff, 0xc0cbff, 0xc0cbff, 
+	0xc048b, 0x2218a0, 0x382db5, 0x483ec7, 
+	0x584fda, 0x6159ec, 0x6b64ff, 0x7a74ff, 
+	0x8a84ff, 0x918eff, 0x9998ff, 0xa5a3ff, 
+	0xb1aeff, 0xb8b8ff, 0xc0c2ff, 0xc0c2ff, 
+	0x1d295a, 0x1d3876, 0x1d4892, 0x1c5cac, 
+	0x1c71c6, 0x3286cf, 0x489bd9, 0x4ea8ec, 
+	0x55b6ff, 0x70c7ff, 0x8cd8ff, 0x93dbff, 
+	0x9bdfff, 0xafe4ff, 0xc3e9ff, 0xc3e9ff, 
+	0x2f4302, 0x395202, 0x446103, 0x417a12, 
+	0x3e9421, 0x4a9f2e, 0x57ab3b, 0x5cbd55, 
+	0x61d070, 0x69e27a, 0x72f584, 0x7cfa8d, 
+	0x87ff97, 0x9affa6, 0xadffb6, 0xadffb6, 
+	0xa4108, 0xd540a, 0x10680d, 0x137d0f, 
+	0x169212, 0x19a514, 0x1cb917, 0x1ec919, 
+	0x21d91b, 0x47e42d, 0x6ef040, 0x78f74d, 
+	0x83ff5b, 0x9aff7a, 0xb2ff9a, 0xb2ff9a, 
+	0x4410b, 0x5530e, 0x66611, 0x77714, 
+	0x88817, 0x99b1a, 0xbaf1d, 0x48c41f, 
+	0x86d922, 0x8fe924, 0x99f927, 0xa8fc41, 
+	0xb7ff5b, 0xc9ff6e, 0xdcff81, 0xdcff81, 
+	0x2350f, 0x73f15, 0xc4a1c, 0x2d5f1e, 
+	0x4f7420, 0x598324, 0x649228, 0x82a12e, 
+	0xa1b034, 0xa9c13a, 0xb2d241, 0xc4d945, 
+	0xd6e149, 0xe4f04e, 0xf2ff53, 0xf2ff53, 
+	0x263001, 0x243803, 0x234005, 0x51541b, 
+	0x806931, 0x978135, 0xaf993a, 0xc2a73e, 
+	0xd5b543, 0xdbc03d, 0xe1cb38, 0xe2d836, 
+	0xe3e534, 0xeff258, 0xfbff7d, 0xfbff7d, 
+	0x401a02, 0x581f05, 0x702408, 0x8d3a13, 
+	0xab511f, 0xb56427, 0xbf7730, 0xd0853a, 
+	0xe19344, 0xeda04e, 0xf9ad58, 0xfcb75c, 
+	0xffc160, 0xffc671, 0xffcb83, 0xffcb83, 
+};
+
diff --git a/MCUME_pico2/pico800/cpu.c b/MCUME_pico2/pico800/cpu.c
new file mode 100644
index 0000000..cc73b28
--- /dev/null
+++ b/MCUME_pico2/pico800/cpu.c
@@ -0,0 +1,2444 @@
+/*
+ * cpu.c - 6502 CPU emulation
+ *
+ * Copyright (C) 1995-1998 David Firth
+ * Copyright (C) 1998-2005 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/*
+	Configuration symbols
+	=====================
+
+	Define CPU65C02 if you don't want 6502 JMP() bug emulation.
+	Define CYCLES_PER_OPCODE to update ANTIC_xpos in each opcode's emulation.
+	Define MONITOR_BREAK if you want code breakpoints and execution history.
+	Define MONITOR_BREAKPOINTS if you want user-defined breakpoints.
+	Define MONITOR_PROFILE if you want 6502 opcode profiling.
+	Define MONITOR_TRACE if you want the code to be disassembled while it is executed.
+	Define NO_GOTO if you compile with GCC, but want switch() rather than goto *.
+	Define NO_V_FLAG_VARIABLE to don't use local (static) variable V for the V flag.
+	Define PC_PTR to emulate 6502 Program Counter using UBYTE *.
+	Define PREFETCH_CODE to always fetch 2 bytes after the opcode.
+	Define WRAP_64K to correctly emulate instructions that wrap at 64K.
+	Define WRAP_ZPAGE to prevent incorrect access to the address 0x0100 in zeropage
+	indirect mode.
+
+
+	Limitations & Known bugs
+	========================
+
+	There is no emulation of the bug in the BRK instruction executed simultaneously
+	with another interrupt.
+
+	The 6502 emulation ignores memory attributes for instruction fetch.
+	This is because the instruction must come from either RAM or ROM.
+	A program that executes instructions from within hardware addresses will fail
+	since there is never any usable code there.
+
+	The 6502 emulation also ignores memory attributes for accesses to page 0 and page 1.
+ */
+
+
+#ifdef SKIP
+#include "config.h"
+#include <stdio.h>
+#include <stdlib.h>  /* exit() */
+
+#include "cpu.h"
+#ifdef ASAP /* external project, see http://asap.sf.net */
+#include "asap_internal.h"
+#else
+#include "antic.h"
+#include "atari.h"
+#include "esc.h"
+#include "memory.h"
+#include "monitor.h"
+#ifndef BASIC
+#include "statesav.h"
+#ifndef __PLUS
+#include "ui.h"
+#endif
+#endif /* BASIC */
+#endif /* ASAP */
+#else
+
+#include <stdio.h>
+#include <stdlib.h>  /* exit() */
+#include "cpu.h"
+#include "antic.h"
+#include "memory.h"
+
+#define ESC_Run(x)
+
+#endif
+
+
+/* For Atari Basic loader */
+void (*CPU_rts_handler)(void) = NULL;
+
+/* 6502 instruction profiling */
+#ifdef MONITOR_PROFILE
+int CPU_instruction_count[256];
+#endif
+
+/* Execution history */
+#ifdef MONITOR_BREAK
+UWORD CPU_remember_PC[CPU_REMEMBER_PC_STEPS];
+UBYTE CPU_remember_op[CPU_REMEMBER_PC_STEPS][3];
+unsigned int CPU_remember_PC_curpos = 0;
+int CPU_remember_xpos[CPU_REMEMBER_PC_STEPS];
+UWORD CPU_remember_JMP[CPU_REMEMBER_JMP_STEPS];
+unsigned int CPU_remember_jmp_curpos = 0;
+#define INC_RET_NESTING MONITOR_ret_nesting++
+#else /* MONITOR_BREAK */
+#define INC_RET_NESTING
+#endif /* MONITOR_BREAK */
+
+UBYTE CPU_cim_encountered = FALSE;
+UBYTE CPU_IRQ;
+
+#ifdef FALCON_CPUASM
+
+#if defined(PAGED_MEM) || defined(PAGED_ATTRIB)
+#error cpu_m68k.asm cannot work with paged memory/attributes
+#endif
+
+#if defined(MONITOR_BREAKPOINTS)
+#error cpu_m68k.asm does not support user-defined breakpoints
+#endif
+
+#if defined(MONITOR_TRACE)
+#error cpu_m68k.asm does not support disassembling the code while it is executed
+#endif
+
+#else /* FALCON_CPUASM */
+
+/* Windows headers define it */
+#undef ABSOLUTE
+
+#ifndef __GNUC__
+#define NO_GOTO
+#endif
+
+/* #define CYCLES_PER_OPCODE */
+
+/* #define MONITOR_PROFILE */
+
+/* #define NO_V_FLAG_VARIABLE */
+
+/* If PC_PTR is defined, local PC is "const UBYTE *", otherwise it's UWORD. */
+/* #define PC_PTR */
+
+/* If PREFETCH_CODE is defined, 2 bytes after the opcode are always fetched. */
+/* #define PREFETCH_CODE */
+
+
+/* 6502 stack handling */
+#define PL                  MEMORY_dGetByte(0x0100 + ++S)
+#define PH(x)               MEMORY_dPutByte(0x0100 + S--, x)
+#define PHW(x)              PH((x) >> 8); PH((x) & 0xff)
+
+/* 6502 code fetching */
+#ifdef PC_PTR
+#define GET_PC()            (PC - MEMORY_mem)
+#define SET_PC(newpc)       (PC = MEMORY_mem + (newpc))
+#define PHPC                { UWORD tmp = PC - MEMORY_mem; PHW(tmp); }
+#define GET_CODE_BYTE()     (*PC++)
+#define PEEK_CODE_BYTE()    (*PC)
+#if !defined(WORDS_BIGENDIAN) && defined(WORDS_UNALIGNED_OK)
+#define PEEK_CODE_WORD()    (*(const UWORD *) PC)
+#else
+#define PEEK_CODE_WORD()    (*PC + (PC[1] << 8))
+#endif
+#else /* PC_PTR */
+#define GET_PC()            PC
+#define SET_PC(newpc)       (PC = (newpc))
+#define PHPC                PHW(PC)
+#define GET_CODE_BYTE()     MEMORY_dGetByte(PC++)
+#define PEEK_CODE_BYTE()    MEMORY_dGetByte(PC)
+#define PEEK_CODE_WORD()    MEMORY_dGetWord(PC)
+#endif /* PC_PTR */
+
+/* Cycle-exact Read-Modify-Write instructions.
+   RMW instructions: ASL, LSR, ROL, ROR, INC, DEC
+   (+ some undocumented) write to the specified address
+   *twice*: first the unmodified value, then the modified value.
+   This can be observed only with some hardware registers. */
+/* XXX: we do this only for GTIA, because NEW_CYCLE_EXACT does not correctly
+   emulate INC $D400 (and INC $D40A wasn't tested) */
+#ifdef NEW_CYCLE_EXACT
+#ifndef PAGED_ATTRIB
+#define RMW_GetByte(x, addr) \
+	if (MEMORY_attrib[addr] == MEMORY_HARDWARE) { \
+		x = MEMORY_HwGetByte(addr, FALSE); \
+		if ((addr & 0xef00) == 0xc000) { \
+			ANTIC_xpos--; \
+			MEMORY_HwPutByte(addr, x); \
+			ANTIC_xpos++; \
+		} \
+	} else \
+		x = MEMORY_dGetByte(addr);
+#else /* PAGED_ATTRIB */
+#define RMW_GetByte(x, addr) \
+	x = MEMORY_GetByte(addr); \
+	if ((addr & 0xef00) == 0xc000) { \
+		ANTIC_xpos--; \
+		MEMORY_PutByte(addr, x); \
+		ANTIC_xpos++; \
+	}
+#endif /* PAGED_ATTRIB */
+#else /* NEW_CYCLE_EXACT */
+/* Don't emulate the first write */
+#define RMW_GetByte(x, addr) x = MEMORY_GetByte(addr);
+#endif /* NEW_CYCLE_EXACT */
+
+/* 6502 registers. */
+UWORD CPU_regPC;
+UBYTE CPU_regA;
+UBYTE CPU_regX;
+UBYTE CPU_regY;
+UBYTE CPU_regP;						/* Processor Status Byte (Partial) */
+UBYTE CPU_regS;
+
+/* Transfer 6502 registers between global variables and local variables inside CPU_GO() */
+#define UPDATE_GLOBAL_REGS  CPU_regPC = GET_PC(); CPU_regS = S; CPU_regA = A; CPU_regX = X; CPU_regY = Y
+#define UPDATE_LOCAL_REGS   SET_PC(CPU_regPC); S = CPU_regS; A = CPU_regA; X = CPU_regX; Y = CPU_regY
+
+/* 6502 flags local to this module */
+static UBYTE N;					/* bit7 set => N flag set */
+#ifndef NO_V_FLAG_VARIABLE
+static UBYTE V;                 /* non-zero => V flag set */
+#endif
+static UBYTE Z;					/* zero     => Z flag set */
+static UBYTE C;					/* must be 0 or 1 */
+/* B, D, I are always in CPU_regP */
+
+void CPU_GetStatus(void)
+{
+#ifndef NO_V_FLAG_VARIABLE
+	CPU_regP = (N & 0x80) + (V ? 0x40 : 0) + (CPU_regP & 0x3c) + ((Z == 0) ? 0x02 : 0) + C;
+#else
+	CPU_regP = (N & 0x80) + (CPU_regP & 0x7c) + ((Z == 0) ? 0x02 : 0) + C;
+#endif
+}
+
+void CPU_PutStatus(void)
+{
+	N = CPU_regP;
+#ifndef NO_V_FLAG_VARIABLE
+	V = (CPU_regP & 0x40);
+#endif
+	Z = (CPU_regP & 0x02) ^ 0x02;
+	C = (CPU_regP & 0x01);
+}
+
+/* Addressing modes */
+#ifdef WRAP_ZPAGE
+#define zGetWord(x) (MEMORY_dGetByte(x) + (MEMORY_dGetByte((UBYTE) ((x) + 1)) << 8))
+#else
+#define zGetWord(x) MEMORY_dGetWord(x)
+#endif
+#ifdef PREFETCH_CODE
+#if defined(WORDS_BIGENDIAN) || !defined(WORDS_UNALIGNED_OK)
+#warning PREFETCH_CODE is efficient only on little-endian machines with WORDS_UNALIGNED_OK
+#endif
+#define OP_BYTE     ((UBYTE) addr)
+#define OP_WORD     addr
+#define IMMEDIATE   (PC++, (UBYTE) addr)
+#define ABSOLUTE    PC += 2
+#define ZPAGE       PC++; addr &= 0xff
+#define ABSOLUTE_X  addr += X; PC += 2
+#define ABSOLUTE_Y  addr += Y; PC += 2
+#define INDIRECT_X  PC++; addr = (UBYTE) (addr + X); addr = zGetWord(addr)
+#define INDIRECT_Y  PC++; addr &= 0xff; addr = zGetWord(addr) + Y
+#define ZPAGE_X     PC++; addr = (UBYTE) (addr + X)
+#define ZPAGE_Y     PC++; addr = (UBYTE) (addr + Y)
+#else /* PREFETCH_CODE */
+#define OP_BYTE     PEEK_CODE_BYTE()
+#define OP_WORD     PEEK_CODE_WORD()
+#define IMMEDIATE   GET_CODE_BYTE()
+#define ABSOLUTE    addr = PEEK_CODE_WORD(); PC += 2
+#define ZPAGE       addr = GET_CODE_BYTE()
+#define ABSOLUTE_X  addr = PEEK_CODE_WORD() + X; PC += 2
+#define ABSOLUTE_Y  addr = PEEK_CODE_WORD() + Y; PC += 2
+#define INDIRECT_X  addr = (UBYTE) (GET_CODE_BYTE() + X); addr = zGetWord(addr)
+#define INDIRECT_Y  addr = GET_CODE_BYTE(); addr = zGetWord(addr) + Y
+#define ZPAGE_X     addr = (UBYTE) (GET_CODE_BYTE() + X)
+#define ZPAGE_Y     addr = (UBYTE) (GET_CODE_BYTE() + Y)
+#endif /* PREFETCH_CODE */
+
+/* Instructions */
+#define AND(t_data) Z = N = A &= t_data
+#define CMP(t_data) data = t_data; Z = N = A - data; C = (A >= data)
+#define CPX(t_data) data = t_data; Z = N = X - data; C = (X >= data)
+#define CPY(t_data) data = t_data; Z = N = Y - data; C = (Y >= data)
+#define EOR(t_data) Z = N = A ^= t_data
+#define LDA(t_data) Z = N = A = t_data
+#define LDX(t_data) Z = N = X = t_data
+#define LDY(t_data) Z = N = Y = t_data
+#define ORA(t_data) Z = N = A |= t_data
+#ifndef NO_V_FLAG_VARIABLE
+#define PHP(x)      data = (N & 0x80) + (V ? 0x40 : 0) + (CPU_regP & (x)) + ((Z == 0) ? 0x02 : 0) + C; PH(data)
+#define PHPB0       PHP(0x2c)  /* push flags with B flag clear (NMI, IRQ) */
+#define PHPB1       PHP(0x3c)  /* push flags with B flag set (PHP, BRK) */
+#define PLP         data = PL; N = data; V = (data & 0x40); Z = (data & 0x02) ^ 0x02; C = (data & 0x01); CPU_regP = (data & 0x0c) + 0x30
+#else /* NO_V_FLAG_VARIABLE */
+#define PHP(x)      data = (N & 0x80) + (CPU_regP & (x)) + ((Z == 0) ? 0x02 : 0) + C; PH(data)
+#define PHPB0       PHP(0x6c)  /* push flags with B flag clear (NMI, IRQ) */
+#define PHPB1       PHP(0x7c)  /* push flags with B flag set (PHP, BRK) */
+#define PLP         data = PL; N = data; Z = (data & 0x02) ^ 0x02; C = (data & 0x01); CPU_regP = (data & 0x4c) + 0x30
+#endif /* NO_V_FLAG_VARIABLE */
+/* 1 or 2 extra cycles for conditional jumps */
+#if 0
+/* old, less efficient version */
+#define BRANCH(cond) \
+	if (cond) { \
+		SWORD sdata = (SBYTE) GET_CODE_BYTE(); \
+		if ((sdata + (UBYTE) GET_PC()) & 0xff00) \
+			ANTIC_xpos++; \
+		ANTIC_xpos++; \
+		PC += sdata; \
+		DONE \
+	} \
+	PC++; \
+	DONE
+#else
+#define BRANCH(cond) \
+	if (cond) { \
+		addr = (UWORD) (SBYTE) IMMEDIATE; \
+		addr += GET_PC(); \
+		if ((addr ^ GET_PC()) & 0xff00) \
+			ANTIC_xpos++; \
+		ANTIC_xpos++; \
+		SET_PC(addr); \
+		DONE \
+	} \
+	PC++; \
+	DONE
+#endif
+
+/* 1 extra cycle for X (or Y) index overflow */
+#define NCYCLES_X   if ((UBYTE) addr < X) ANTIC_xpos++
+#define NCYCLES_Y   if ((UBYTE) addr < Y) ANTIC_xpos++
+
+/* Triggers a Non-Maskable Interrupt */
+void CPU_NMI(void)
+{
+	UBYTE S = CPU_regS;
+	UBYTE data;
+
+	PHW(CPU_regPC);
+	PHPB0;
+	CPU_SetI;
+	CPU_regPC = MEMORY_dGetWordAligned(0xfffa);
+	CPU_regS = S;
+	ANTIC_xpos += 7; /* handling an interrupt by 6502 takes 7 cycles */
+	INC_RET_NESTING;
+}
+
+/* Check pending IRQ, helps in (not only) Lucasfilm games */
+#define CPUCHECKIRQ \
+	if (CPU_IRQ && !(CPU_regP & CPU_I_FLAG) && ANTIC_xpos < ANTIC_xpos_limit) { \
+		PHPC; \
+		PHPB0; \
+		CPU_SetI; \
+		SET_PC(MEMORY_dGetWordAligned(0xfffe)); \
+		ANTIC_xpos += 7; \
+		INC_RET_NESTING; \
+	}
+
+/* Enter monitor */
+#ifdef __PLUS
+#define ENTER_MONITOR  Atari800_Exit(TRUE)
+#else
+#ifdef SKIP
+#define ENTER_MONITOR  if (!Atari800_Exit(TRUE)) exit(0)
+#else
+#define ENTER_MONITOR  exit(0)
+#endif
+#endif
+#define DO_BREAK \
+	UPDATE_GLOBAL_REGS; \
+	CPU_GetStatus(); \
+	ENTER_MONITOR; \
+	CPU_PutStatus(); \
+	UPDATE_LOCAL_REGS;
+
+
+/*	0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
+static const int cycles[256] =
+{
+	7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6,		/* 0x */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,		/* 1x */
+	6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6,		/* 2x */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,		/* 3x */
+
+	6, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6,		/* 4x */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,		/* 5x */
+	6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6,		/* 6x */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,		/* 7x */
+
+	2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,		/* 8x */
+	2, 6, 2, 6, 4, 4, 4, 4, 2, 5, 2, 5, 5, 5, 5, 5,		/* 9x */
+	2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4,		/* Ax */
+	2, 5, 2, 5, 4, 4, 4, 4, 2, 4, 2, 4, 4, 4, 4, 4,		/* Bx */
+
+	2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,		/* Cx */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,		/* Dx */
+	2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,		/* Ex */
+	2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7		/* Fx */
+};
+
+/* 6502 emulation routine */
+#ifndef NO_GOTO
+__extension__ /* suppress -ansi -pedantic warnings */
+#endif
+void CPU_GO(int limit)
+{
+#ifdef NO_GOTO
+#define OPCODE_ALIAS(code)	case 0x##code:
+#define DONE				break;
+#else
+#define OPCODE_ALIAS(code)	opcode_##code:
+#define DONE				goto next;
+	static const void *opcode[256] =
+	{
+		&&opcode_00, &&opcode_01, &&opcode_02, &&opcode_03,
+		&&opcode_04, &&opcode_05, &&opcode_06, &&opcode_07,
+		&&opcode_08, &&opcode_09, &&opcode_0a, &&opcode_0b,
+		&&opcode_0c, &&opcode_0d, &&opcode_0e, &&opcode_0f,
+
+		&&opcode_10, &&opcode_11, &&opcode_12, &&opcode_13,
+		&&opcode_14, &&opcode_15, &&opcode_16, &&opcode_17,
+		&&opcode_18, &&opcode_19, &&opcode_1a, &&opcode_1b,
+		&&opcode_1c, &&opcode_1d, &&opcode_1e, &&opcode_1f,
+
+		&&opcode_20, &&opcode_21, &&opcode_22, &&opcode_23,
+		&&opcode_24, &&opcode_25, &&opcode_26, &&opcode_27,
+		&&opcode_28, &&opcode_29, &&opcode_2a, &&opcode_2b,
+		&&opcode_2c, &&opcode_2d, &&opcode_2e, &&opcode_2f,
+
+		&&opcode_30, &&opcode_31, &&opcode_32, &&opcode_33,
+		&&opcode_34, &&opcode_35, &&opcode_36, &&opcode_37,
+		&&opcode_38, &&opcode_39, &&opcode_3a, &&opcode_3b,
+		&&opcode_3c, &&opcode_3d, &&opcode_3e, &&opcode_3f,
+
+		&&opcode_40, &&opcode_41, &&opcode_42, &&opcode_43,
+		&&opcode_44, &&opcode_45, &&opcode_46, &&opcode_47,
+		&&opcode_48, &&opcode_49, &&opcode_4a, &&opcode_4b,
+		&&opcode_4c, &&opcode_4d, &&opcode_4e, &&opcode_4f,
+
+		&&opcode_50, &&opcode_51, &&opcode_52, &&opcode_53,
+		&&opcode_54, &&opcode_55, &&opcode_56, &&opcode_57,
+		&&opcode_58, &&opcode_59, &&opcode_5a, &&opcode_5b,
+		&&opcode_5c, &&opcode_5d, &&opcode_5e, &&opcode_5f,
+
+		&&opcode_60, &&opcode_61, &&opcode_62, &&opcode_63,
+		&&opcode_64, &&opcode_65, &&opcode_66, &&opcode_67,
+		&&opcode_68, &&opcode_69, &&opcode_6a, &&opcode_6b,
+		&&opcode_6c, &&opcode_6d, &&opcode_6e, &&opcode_6f,
+
+		&&opcode_70, &&opcode_71, &&opcode_72, &&opcode_73,
+		&&opcode_74, &&opcode_75, &&opcode_76, &&opcode_77,
+		&&opcode_78, &&opcode_79, &&opcode_7a, &&opcode_7b,
+		&&opcode_7c, &&opcode_7d, &&opcode_7e, &&opcode_7f,
+
+		&&opcode_80, &&opcode_81, &&opcode_82, &&opcode_83,
+		&&opcode_84, &&opcode_85, &&opcode_86, &&opcode_87,
+		&&opcode_88, &&opcode_89, &&opcode_8a, &&opcode_8b,
+		&&opcode_8c, &&opcode_8d, &&opcode_8e, &&opcode_8f,
+
+		&&opcode_90, &&opcode_91, &&opcode_92, &&opcode_93,
+		&&opcode_94, &&opcode_95, &&opcode_96, &&opcode_97,
+		&&opcode_98, &&opcode_99, &&opcode_9a, &&opcode_9b,
+		&&opcode_9c, &&opcode_9d, &&opcode_9e, &&opcode_9f,
+
+		&&opcode_a0, &&opcode_a1, &&opcode_a2, &&opcode_a3,
+		&&opcode_a4, &&opcode_a5, &&opcode_a6, &&opcode_a7,
+		&&opcode_a8, &&opcode_a9, &&opcode_aa, &&opcode_ab,
+		&&opcode_ac, &&opcode_ad, &&opcode_ae, &&opcode_af,
+
+		&&opcode_b0, &&opcode_b1, &&opcode_b2, &&opcode_b3,
+		&&opcode_b4, &&opcode_b5, &&opcode_b6, &&opcode_b7,
+		&&opcode_b8, &&opcode_b9, &&opcode_ba, &&opcode_bb,
+		&&opcode_bc, &&opcode_bd, &&opcode_be, &&opcode_bf,
+
+		&&opcode_c0, &&opcode_c1, &&opcode_c2, &&opcode_c3,
+		&&opcode_c4, &&opcode_c5, &&opcode_c6, &&opcode_c7,
+		&&opcode_c8, &&opcode_c9, &&opcode_ca, &&opcode_cb,
+		&&opcode_cc, &&opcode_cd, &&opcode_ce, &&opcode_cf,
+
+		&&opcode_d0, &&opcode_d1, &&opcode_d2, &&opcode_d3,
+		&&opcode_d4, &&opcode_d5, &&opcode_d6, &&opcode_d7,
+		&&opcode_d8, &&opcode_d9, &&opcode_da, &&opcode_db,
+		&&opcode_dc, &&opcode_dd, &&opcode_de, &&opcode_df,
+
+		&&opcode_e0, &&opcode_e1, &&opcode_e2, &&opcode_e3,
+		&&opcode_e4, &&opcode_e5, &&opcode_e6, &&opcode_e7,
+		&&opcode_e8, &&opcode_e9, &&opcode_ea, &&opcode_eb,
+		&&opcode_ec, &&opcode_ed, &&opcode_ee, &&opcode_ef,
+
+		&&opcode_f0, &&opcode_f1, &&opcode_f2, &&opcode_f3,
+		&&opcode_f4, &&opcode_f5, &&opcode_f6, &&opcode_f7,
+		&&opcode_f8, &&opcode_f9, &&opcode_fa, &&opcode_fb,
+		&&opcode_fc, &&opcode_fd, &&opcode_fe, &&opcode_ff,
+	};
+#endif	/* NO_GOTO */
+
+#ifdef CYCLES_PER_OPCODE
+#define OPCODE(code) OPCODE_ALIAS(code) ANTIC_xpos += cycles[0x##code];
+#else
+#define OPCODE(code) OPCODE_ALIAS(code)
+#endif
+
+#ifdef PC_PTR
+	const UBYTE *PC;
+#else
+	UWORD PC;
+#endif
+	UBYTE A;
+	UBYTE X;
+	UBYTE Y;
+	UBYTE S;
+
+	UWORD addr;
+	UBYTE data;
+#define insn data
+
+/*
+   This used to be in the main loop but has been removed to improve
+   execution speed. It does not seem to have any adverse effect on
+   the emulation for two reasons:
+
+   1. NMI's will can only be raised in antic.c - there is
+      no way an NMI can be generated whilst in this routine.
+
+   2. The timing of the IRQs are not that critical. */
+
+	if (ANTIC_wsync_halt) {
+
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN) {
+/* if ANTIC_WSYNC_C is a stolen cycle, ANTIC_antic2cpu_ptr will convert that to the nearest
+   cpu cycle before that cycle.  The CPU will see this cycle, if WSYNC is not
+   delayed. (Actually this cycle is the first cycle of the instruction after
+   STA WSYNC, which was really executed one cycle after STA WSYNC because
+   of an internal antic delay ).   ANTIC_delayed_wsync is added to this cycle to form
+   the limit in the case that WSYNC is not early (does not allow this extra cycle) */
+
+			if (limit < ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C] + ANTIC_delayed_wsync)
+				return;
+			ANTIC_xpos = ANTIC_antic2cpu_ptr[ANTIC_WSYNC_C] + ANTIC_delayed_wsync;
+		}
+		else {
+			if (limit < (ANTIC_WSYNC_C + ANTIC_delayed_wsync))
+				return;
+			ANTIC_xpos = ANTIC_WSYNC_C;
+		}
+		ANTIC_delayed_wsync = 0;
+
+#else /* NEW_CYCLE_EXACT */
+
+		if (limit < ANTIC_WSYNC_C)
+			return;
+		ANTIC_xpos = ANTIC_WSYNC_C;
+
+#endif /* NEW_CYCLE_EXACT */
+
+		ANTIC_wsync_halt = 0;
+	}
+	ANTIC_xpos_limit = limit;			/* needed for WSYNC store inside ANTIC */
+
+	UPDATE_LOCAL_REGS;
+
+	CPUCHECKIRQ;
+
+	while (ANTIC_xpos < ANTIC_xpos_limit) {
+#ifdef MONITOR_PROFILE
+		int old_xpos = ANTIC_xpos;
+		UWORD old_PC = GET_PC();
+#endif
+
+
+#ifdef MONITOR_BREAKPOINTS
+	breakpoint_return:
+#endif
+
+#ifdef PC_PTR
+		/* must handle 64k wrapping */
+		if (PC >= MEMORY_mem + 0xfffe) {
+			if (PC >= MEMORY_mem + 0x10000)
+				PC -= 0x10000;
+			else {
+				/* the opcode is before 0x10000, but the operand is past */
+#ifdef WORDS_UNALIGNED_OK
+				*(UWORD *) (MEMORY_mem + 0x10000) = *(UWORD *) MEMORY_mem;
+#else
+				MEMORY_mem[0x10000] = MEMORY_mem[0];
+				MEMORY_mem[0x10001] = MEMORY_mem[1];
+#endif /* WORDS_UNALIGNED_OK */
+			}
+		}
+#endif /* PC_PTR */
+
+#ifdef MONITOR_TRACE
+		if (MONITOR_trace_file != NULL) {
+			MONITOR_ShowState(MONITOR_trace_file, GET_PC(), A, X, Y, S,
+				(N & 0x80) ? 'N' : '-',
+#ifndef NO_V_FLAG_VARIABLE
+				V ? 'V' : '-',
+#else
+				(CPU_regP & CPU_V_FLAG) ? 'V' : '-',
+#endif
+				(Z == 0) ? 'Z' : '-',
+				(C != 0) ? 'C' : '-');
+		}
+#endif
+
+#ifdef MONITOR_BREAK
+		CPU_remember_PC[CPU_remember_PC_curpos] = GET_PC();
+		CPU_remember_op[CPU_remember_PC_curpos][0] = MEMORY_dGetByte(GET_PC());
+		CPU_remember_op[CPU_remember_PC_curpos][1] = MEMORY_dGetByte(GET_PC()+1);
+		CPU_remember_op[CPU_remember_PC_curpos][2] = MEMORY_dGetByte(GET_PC()+2);
+#ifdef NEW_CYCLE_EXACT
+		if (ANTIC_DRAWING_SCREEN)
+			CPU_remember_xpos[CPU_remember_PC_curpos] = ANTIC_cpu2antic_ptr[ANTIC_xpos] + (ANTIC_ypos << 8);
+		else
+#endif
+			CPU_remember_xpos[CPU_remember_PC_curpos] = ANTIC_xpos + (ANTIC_ypos << 8);
+		CPU_remember_PC_curpos = (CPU_remember_PC_curpos + 1) % CPU_REMEMBER_PC_STEPS;
+
+		if (MONITOR_break_addr == GET_PC() || ANTIC_break_ypos == ANTIC_ypos) {
+			DO_BREAK;
+		}
+#endif /* MONITOR_BREAK */
+
+#if defined(WRAP_64K) && !defined(PC_PTR)
+		MEMORY_mem[0x10000] = MEMORY_mem[0];
+#endif
+
+		insn = GET_CODE_BYTE();
+
+#ifdef MONITOR_BREAKPOINTS
+#ifdef MONITOR_BREAK
+		if (MONITOR_breakpoint_table_size > 0 && MONITOR_breakpoints_enabled && !MONITOR_break_step)
+#else
+		if (MONITOR_breakpoint_table_size > 0 && MONITOR_breakpoints_enabled)
+#endif
+		{
+			UBYTE optype = MONITOR_optype6502[insn];
+			int i;
+			switch (optype >> 4) {
+			case 1:
+				addr = PEEK_CODE_WORD();
+				break;
+			case 2:
+				addr = PEEK_CODE_BYTE();
+				break;
+			case 3:
+				addr = PEEK_CODE_WORD() + X;
+				break;
+			case 4:
+				addr = PEEK_CODE_WORD() + Y;
+				break;
+			case 5:
+				addr = (UBYTE) (PEEK_CODE_BYTE() + X);
+				addr = zGetWord(addr);
+				break;
+			case 6:
+				addr = PEEK_CODE_BYTE();
+				addr = zGetWord(addr) + Y;
+				break;
+			case 7:
+				addr = (UBYTE) (PEEK_CODE_BYTE() + X);
+				break;
+			case 8:
+				addr = (UBYTE) (PEEK_CODE_BYTE() + Y);
+				break;
+			/* XXX: case 13 */
+			default:
+				addr = 0;
+				break;
+			}
+			for (i = 0; i < MONITOR_breakpoint_table_size; i++) {
+				int cond;
+				int value, m_addr;
+				if (!MONITOR_breakpoint_table[i].enabled)
+					continue; /* skip */
+				cond = MONITOR_breakpoint_table[i].condition;
+				if (cond == MONITOR_BREAKPOINT_OR)
+					break; /* fire */
+				value = MONITOR_breakpoint_table[i].value;
+				m_addr = MONITOR_breakpoint_table[i].m_addr;
+				if (cond == MONITOR_BREAKPOINT_FLAG_CLEAR) {
+					switch (value) {
+					case CPU_N_FLAG:
+						if ((N & 0x80) == 0)
+							continue;
+						break;
+#ifndef NO_V_FLAG_VARIABLE
+					case CPU_V_FLAG:
+						if (V == 0)
+							continue;
+						break;
+#endif
+					case CPU_Z_FLAG:
+						if (Z != 0)
+							continue;
+						break;
+					case CPU_C_FLAG:
+						if (C == 0)
+							continue;
+						break;
+					default:
+						if ((CPU_regP & value) == 0)
+							continue;
+						break;
+					}
+				}
+				else if (cond == MONITOR_BREAKPOINT_FLAG_SET) {
+					switch (value) {
+					case CPU_N_FLAG:
+						if ((N & 0x80) != 0)
+							continue;
+						break;
+#ifndef NO_V_FLAG_VARIABLE
+					case CPU_V_FLAG:
+						if (V != 0)
+							continue;
+						break;
+#endif
+					case CPU_Z_FLAG:
+						if (Z == 0)
+							continue;
+						break;
+					case CPU_C_FLAG:
+						if (C != 0)
+							continue;
+						break;
+					default:
+						if ((CPU_regP & value) != 0)
+							continue;
+						break;
+					}
+				}
+				else {
+					int val;
+					switch (cond >> 3) {
+					case MONITOR_BREAKPOINT_PC >> 3:
+						val = GET_PC() - 1;
+						break;
+					case MONITOR_BREAKPOINT_A >> 3:
+						val = A;
+						break;
+					case MONITOR_BREAKPOINT_X >> 3:
+						val = X;
+						break;
+					case MONITOR_BREAKPOINT_Y >> 3:
+						val = Y;
+						break;
+					case MONITOR_BREAKPOINT_S >> 3:
+						val = S;
+						break;
+					case MONITOR_BREAKPOINT_READ >> 3:
+						if ((optype & 4) == 0)
+							goto cond_failed;
+						val = addr;
+						break;
+					case MONITOR_BREAKPOINT_WRITE >> 3:
+						if ((optype & 8) == 0)
+							goto cond_failed;
+						val = addr;
+						break;
+					case MONITOR_BREAKPOINT_ACCESS >> 3:
+						if ((optype & 12) == 0)
+							goto cond_failed;
+						val = addr;
+						break;
+					case MONITOR_BREAKPOINT_MEMORY >> 3:
+						val = MEMORY_SafeGetByte(m_addr);
+						break;
+					default:
+						/* shouldn't happen */
+						continue;
+					}
+					if ((cond & MONITOR_BREAKPOINT_LESS) != 0 && val < value)
+						continue;
+					if ((cond & MONITOR_BREAKPOINT_EQUAL) != 0 && val == value)
+						continue;
+					if ((cond & MONITOR_BREAKPOINT_GREATER) != 0 && val > value)
+						continue;
+				cond_failed:
+					;
+				}
+				/* a condition failed */
+				/* quickly skip AND-connected conditions */
+				do {
+					if (++i >= MONITOR_breakpoint_table_size)
+						goto no_breakpoint;
+				} while (MONITOR_breakpoint_table[i].condition != MONITOR_BREAKPOINT_OR || !MONITOR_breakpoint_table[i].enabled);
+			}
+			/* fire breakpoint */
+			PC--;
+			DO_BREAK;
+			goto breakpoint_return;
+		no_breakpoint:
+			;
+		}
+#endif /* MONITOR_BREAKPOINTS */
+
+#ifndef CYCLES_PER_OPCODE
+		ANTIC_xpos += cycles[insn];
+#endif
+
+#ifdef MONITOR_PROFILE
+		CPU_instruction_count[insn]++;
+		MONITOR_coverage[old_PC = PC - 1].count++;
+		MONITOR_coverage_insns++;
+#endif
+
+#ifdef PREFETCH_CODE
+		addr = PEEK_CODE_WORD();
+#endif
+
+#ifdef NO_GOTO
+		switch (insn) {
+#else
+		goto *opcode[insn];
+#endif
+
+	OPCODE(00)				/* BRK */
+#ifdef MONITOR_BREAK
+		if (MONITOR_break_brk) {
+			DO_BREAK;
+		}
+		else
+#endif
+		{
+			PC++;
+			PHPC;
+			PHPB1;
+			CPU_SetI;
+			SET_PC(MEMORY_dGetWordAligned(0xfffe));
+			INC_RET_NESTING;
+		}
+		DONE
+
+	OPCODE(01)				/* ORA (ab,x) */
+		INDIRECT_X;
+		ORA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(03)				/* ASO (ab,x) [unofficial - ASL then ORA with Acc] */
+		INDIRECT_X;
+
+	aso:
+		RMW_GetByte(data, addr);
+		C = (data & 0x80) ? 1 : 0;
+		data <<= 1;
+		MEMORY_PutByte(addr, data);
+		Z = N = A |= data;
+		DONE
+
+	OPCODE_ALIAS(04)		/* NOP ab [unofficial - skip byte] */
+	OPCODE_ALIAS(44)
+	OPCODE(64)
+		PC++;
+		DONE
+
+	OPCODE_ALIAS(14)		/* NOP ab,x [unofficial - skip byte] */
+	OPCODE_ALIAS(34)
+	OPCODE_ALIAS(54)
+	OPCODE_ALIAS(74)
+	OPCODE_ALIAS(d4)
+	OPCODE(f4)
+		PC++;
+		DONE
+
+	OPCODE_ALIAS(80)		/* NOP #ab [unofficial - skip byte] */
+	OPCODE_ALIAS(82)
+	OPCODE_ALIAS(89)
+	OPCODE_ALIAS(c2)
+	OPCODE(e2)
+		PC++;
+		DONE
+
+	OPCODE(05)				/* ORA ab */
+		ZPAGE;
+		ORA(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(06)				/* ASL ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		C = (data & 0x80) ? 1 : 0;
+		Z = N = data << 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(07)				/* ASO ab [unofficial - ASL then ORA with Acc] */
+		ZPAGE;
+
+	aso_zpage:
+		data = MEMORY_dGetByte(addr);
+		C = (data & 0x80) ? 1 : 0;
+		data <<= 1;
+		MEMORY_dPutByte(addr, data);
+		Z = N = A |= data;
+		DONE
+
+	OPCODE(08)				/* PHP */
+		PHPB1;
+		DONE
+
+	OPCODE(09)				/* ORA #ab */
+		ORA(IMMEDIATE);
+		DONE
+
+	OPCODE(0a)				/* ASL */
+		C = (A & 0x80) ? 1 : 0;
+		Z = N = A <<= 1;
+		DONE
+
+	OPCODE_ALIAS(0b)		/* ANC #ab [unofficial - AND then copy N to C (Fox) */
+	OPCODE(2b)
+		AND(IMMEDIATE);
+		C = N >= 0x80;
+		DONE
+
+	OPCODE(0c)				/* NOP abcd [unofficial - skip word] */
+		PC += 2;
+		DONE
+
+	OPCODE(0d)				/* ORA abcd */
+		ABSOLUTE;
+		ORA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(0e)				/* ASL abcd */
+		ABSOLUTE;
+		RMW_GetByte(data, addr);
+		C = (data & 0x80) ? 1 : 0;
+		Z = N = data << 1;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(0f)				/* ASO abcd [unofficial - ASL then ORA with Acc] */
+		ABSOLUTE;
+		goto aso;
+
+	OPCODE(10)				/* BPL */
+		BRANCH(!(N & 0x80))
+
+	OPCODE(11)				/* ORA (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		ORA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(13)				/* ASO (ab),y [unofficial - ASL then ORA with Acc] */
+		INDIRECT_Y;
+		goto aso;
+
+	OPCODE(15)				/* ORA ab,x */
+		ZPAGE_X;
+		ORA(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(16)				/* ASL ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		C = (data & 0x80) ? 1 : 0;
+		Z = N = data << 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(17)				/* ASO ab,x [unofficial - ASL then ORA with Acc] */
+		ZPAGE_X;
+		goto aso_zpage;
+
+	OPCODE(18)				/* CLC */
+		C = 0;
+		DONE
+
+	OPCODE(19)				/* ORA abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		ORA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(1b)				/* ASO abcd,y [unofficial - ASL then ORA with Acc] */
+		ABSOLUTE_Y;
+		goto aso;
+
+	OPCODE_ALIAS(1c)		/* NOP abcd,x [unofficial - skip word] */
+	OPCODE_ALIAS(3c)
+	OPCODE_ALIAS(5c)
+	OPCODE_ALIAS(7c)
+	OPCODE_ALIAS(dc)
+	OPCODE(fc)
+		if (OP_BYTE + X >= 0x100)
+			ANTIC_xpos++;
+		PC += 2;
+		DONE
+
+	OPCODE(1d)				/* ORA abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		ORA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(1e)				/* ASL abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(data, addr);
+		C = (data & 0x80) ? 1 : 0;
+		Z = N = data << 1;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(1f)				/* ASO abcd,x [unofficial - ASL then ORA with Acc] */
+		ABSOLUTE_X;
+		goto aso;
+
+	OPCODE(20)				/* JSR abcd */
+		{
+			UWORD retaddr = GET_PC() + 1;
+#ifdef MONITOR_BREAK
+			CPU_remember_JMP[CPU_remember_jmp_curpos] = GET_PC() - 1;
+			CPU_remember_jmp_curpos = (CPU_remember_jmp_curpos + 1) % CPU_REMEMBER_JMP_STEPS;
+			MONITOR_ret_nesting++;
+#endif
+			PHW(retaddr);
+		}
+		SET_PC(OP_WORD);
+		DONE
+
+	OPCODE(21)				/* AND (ab,x) */
+		INDIRECT_X;
+		AND(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(23)				/* RLA (ab,x) [unofficial - ROL Mem, then AND with A] */
+		INDIRECT_X;
+
+	rla:
+		RMW_GetByte(data, addr);
+		if (C) {
+			C = (data & 0x80) ? 1 : 0;
+			data = (data << 1) + 1;
+		}
+		else {
+			C = (data & 0x80) ? 1 : 0;
+			data = (data << 1);
+		}
+		MEMORY_PutByte(addr, data);
+		Z = N = A &= data;
+		DONE
+
+	OPCODE(24)				/* BIT ab */
+		ZPAGE;
+		N = MEMORY_dGetByte(addr);
+#ifndef NO_V_FLAG_VARIABLE
+		V = N & 0x40;
+#else
+		CPU_regP = (CPU_regP & 0xbf) + (N & 0x40);
+#endif
+		Z = (A & N);
+		DONE
+
+	OPCODE(25)				/* AND ab */
+		ZPAGE;
+		AND(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(26)				/* ROL ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		Z = N = (data << 1) + C;
+		C = (data & 0x80) ? 1 : 0;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(27)				/* RLA ab [unofficial - ROL Mem, then AND with A] */
+		ZPAGE;
+
+	rla_zpage:
+		data = MEMORY_dGetByte(addr);
+		if (C) {
+			C = (data & 0x80) ? 1 : 0;
+			data = (data << 1) + 1;
+		}
+		else {
+			C = (data & 0x80) ? 1 : 0;
+			data = (data << 1);
+		}
+		MEMORY_dPutByte(addr, data);
+		Z = N = A &= data;
+		DONE
+
+	OPCODE(28)				/* PLP */
+		PLP;
+		CPUCHECKIRQ;
+		DONE
+
+	OPCODE(29)				/* AND #ab */
+		AND(IMMEDIATE);
+		DONE
+
+	OPCODE(2a)				/* ROL */
+		Z = N = (A << 1) + C;
+		C = (A & 0x80) ? 1 : 0;
+		A = Z;
+		DONE
+
+	OPCODE(2c)				/* BIT abcd */
+		ABSOLUTE;
+		N = MEMORY_GetByte(addr);
+#ifndef NO_V_FLAG_VARIABLE
+		V = N & 0x40;
+#else
+		CPU_regP = (CPU_regP & 0xbf) + (N & 0x40);
+#endif
+		Z = (A & N);
+		DONE
+
+	OPCODE(2d)				/* AND abcd */
+		ABSOLUTE;
+		AND(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(2e)				/* ROL abcd */
+		ABSOLUTE;
+		RMW_GetByte(data, addr);
+		Z = N = (data << 1) + C;
+		C = (data & 0x80) ? 1 : 0;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(2f)				/* RLA abcd [unofficial - ROL Mem, then AND with A] */
+		ABSOLUTE;
+		goto rla;
+
+	OPCODE(30)				/* BMI */
+		BRANCH(N & 0x80)
+
+	OPCODE(31)				/* AND (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		AND(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(33)				/* RLA (ab),y [unofficial - ROL Mem, then AND with A] */
+		INDIRECT_Y;
+		goto rla;
+
+	OPCODE(35)				/* AND ab,x */
+		ZPAGE_X;
+		AND(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(36)				/* ROL ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		Z = N = (data << 1) + C;
+		C = (data & 0x80) ? 1 : 0;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(37)				/* RLA ab,x [unofficial - ROL Mem, then AND with A] */
+		ZPAGE_X;
+		goto rla_zpage;
+
+	OPCODE(38)				/* SEC */
+		C = 1;
+		DONE
+
+	OPCODE(39)				/* AND abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		AND(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(3b)				/* RLA abcd,y [unofficial - ROL Mem, then AND with A] */
+		ABSOLUTE_Y;
+		goto rla;
+
+	OPCODE(3d)				/* AND abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		AND(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(3e)				/* ROL abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(data, addr);
+		Z = N = (data << 1) + C;
+		C = (data & 0x80) ? 1 : 0;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(3f)				/* RLA abcd,x [unofficial - ROL Mem, then AND with A] */
+		ABSOLUTE_X;
+		goto rla;
+
+	OPCODE(40)				/* RTI */
+		PLP;
+		data = PL;
+		SET_PC((PL << 8) + data);
+		CPUCHECKIRQ;
+#ifdef MONITOR_BREAK
+		if (MONITOR_break_ret && --MONITOR_ret_nesting <= 0)
+			MONITOR_break_step = TRUE;
+#endif
+		DONE
+
+	OPCODE(41)				/* EOR (ab,x) */
+		INDIRECT_X;
+		EOR(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(43)				/* LSE (ab,x) [unofficial - LSR then EOR result with A] */
+		INDIRECT_X;
+
+	lse:
+		RMW_GetByte(data, addr);
+		C = data & 1;
+		data >>= 1;
+		MEMORY_PutByte(addr, data);
+		Z = N = A ^= data;
+		DONE
+
+	OPCODE(45)				/* EOR ab */
+		ZPAGE;
+		EOR(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(46)				/* LSR ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		C = data & 1;
+		Z = data >> 1;
+		N = 0;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(47)				/* LSE ab [unofficial - LSR then EOR result with A] */
+		ZPAGE;
+
+	lse_zpage:
+		data = MEMORY_dGetByte(addr);
+		C = data & 1;
+		data >>= 1;
+		MEMORY_dPutByte(addr, data);
+		Z = N = A ^= data;
+		DONE
+
+	OPCODE(48)				/* PHA */
+		PH(A);
+		DONE
+
+	OPCODE(49)				/* EOR #ab */
+		EOR(IMMEDIATE);
+		DONE
+
+	OPCODE(4a)				/* LSR */
+		C = A & 1;
+		Z = N = A >>= 1;
+		DONE
+
+	OPCODE(4b)				/* ALR #ab [unofficial - Acc AND Data, LSR result] */
+		data = A & IMMEDIATE;
+		C = data & 1;
+		Z = N = A = (data >> 1);
+		DONE
+
+	OPCODE(4c)				/* JMP abcd */
+#ifdef MONITOR_BREAK
+		CPU_remember_JMP[CPU_remember_jmp_curpos] = GET_PC() - 1;
+		CPU_remember_jmp_curpos = (CPU_remember_jmp_curpos + 1) % CPU_REMEMBER_JMP_STEPS;
+#endif
+		SET_PC(OP_WORD);
+		DONE
+
+	OPCODE(4d)				/* EOR abcd */
+		ABSOLUTE;
+		EOR(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(4e)				/* LSR abcd */
+		ABSOLUTE;
+		RMW_GetByte(data, addr);
+		C = data & 1;
+		Z = data >> 1;
+		N = 0;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(4f)				/* LSE abcd [unofficial - LSR then EOR result with A] */
+		ABSOLUTE;
+		goto lse;
+
+	OPCODE(50)				/* BVC */
+#ifndef NO_V_FLAG_VARIABLE
+		BRANCH(!V)
+#else
+		BRANCH(!(CPU_regP & 0x40))
+#endif
+
+	OPCODE(51)				/* EOR (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		EOR(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(53)				/* LSE (ab),y [unofficial - LSR then EOR result with A] */
+		INDIRECT_Y;
+		goto lse;
+
+	OPCODE(55)				/* EOR ab,x */
+		ZPAGE_X;
+		EOR(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(56)				/* LSR ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		C = data & 1;
+		Z = data >> 1;
+		N = 0;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(57)				/* LSE ab,x [unofficial - LSR then EOR result with A] */
+		ZPAGE_X;
+		goto lse_zpage;
+
+	OPCODE(58)				/* CLI */
+		CPU_ClrI;
+		CPUCHECKIRQ;
+		DONE
+
+	OPCODE(59)				/* EOR abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		EOR(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(5b)				/* LSE abcd,y [unofficial - LSR then EOR result with A] */
+		ABSOLUTE_Y;
+		goto lse;
+
+	OPCODE(5d)				/* EOR abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		EOR(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(5e)				/* LSR abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(data, addr);
+		C = data & 1;
+		Z = data >> 1;
+		N = 0;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(5f)				/* LSE abcd,x [unofficial - LSR then EOR result with A] */
+		ABSOLUTE_X;
+		goto lse;
+
+	OPCODE(60)				/* RTS */
+		data = PL;
+		SET_PC((PL << 8) + data + 1);
+#ifdef MONITOR_BREAK
+		if (MONITOR_break_ret && --MONITOR_ret_nesting <= 0)
+			MONITOR_break_step = TRUE;
+#endif
+		if (CPU_rts_handler != NULL) {
+			CPU_rts_handler();
+			CPU_rts_handler = NULL;
+		}
+		DONE
+
+	OPCODE(61)				/* ADC (ab,x) */
+		INDIRECT_X;
+		data = MEMORY_GetByte(addr);
+		goto adc;
+
+	OPCODE(63)				/* RRA (ab,x) [unofficial - ROR Mem, then ADC to Acc] */
+		INDIRECT_X;
+
+	rra:
+		RMW_GetByte(data, addr);
+		if (C) {
+			C = data & 1;
+			data = (data >> 1) + 0x80;
+		}
+		else {
+			C = data & 1;
+			data >>= 1;
+		}
+		MEMORY_PutByte(addr, data);
+		goto adc;
+
+	OPCODE(65)				/* ADC ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		goto adc;
+
+	OPCODE(66)				/* ROR ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		Z = N = (C << 7) + (data >> 1);
+		C = data & 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(67)				/* RRA ab [unofficial - ROR Mem, then ADC to Acc] */
+		ZPAGE;
+
+	rra_zpage:
+		data = MEMORY_dGetByte(addr);
+		if (C) {
+			C = data & 1;
+			data = (data >> 1) + 0x80;
+		}
+		else {
+			C = data & 1;
+			data >>= 1;
+		}
+		MEMORY_dPutByte(addr, data);
+		goto adc;
+
+	OPCODE(68)				/* PLA */
+		Z = N = A = PL;
+		DONE
+
+	OPCODE(69)				/* ADC #ab */
+		data = IMMEDIATE;
+		goto adc;
+
+	OPCODE(6a)				/* ROR */
+		Z = N = (C << 7) + (A >> 1);
+		C = A & 1;
+		A = Z;
+		DONE
+
+	OPCODE(6b)				/* ARR #ab [unofficial - Acc AND Data, ROR result] */
+		/* It does some 'BCD fixup' if D flag is set */
+		/* MPC 05/24/00 */
+		data = A & IMMEDIATE;
+		if (CPU_regP & CPU_D_FLAG) {
+			UBYTE temp = (data >> 1) + (C << 7);
+			Z = N = temp;
+#ifndef NO_V_FLAG_VARIABLE
+			V = ((temp ^ data) & 0x40);
+#else
+			CPU_regP = (CPU_regP & 0xbf) + ((temp ^ data) & 0x40);
+#endif
+			if ((data & 0x0F) + (data & 0x01) > 5)
+				temp = (temp & 0xF0) + ((temp + 0x6) & 0x0F);
+			if (data + (data & 0x10) >= 0x60) {
+				temp += 0x60;
+				C = 1;
+			}
+			else
+				C = 0;
+			A = (UBYTE) temp;
+		}
+		else {
+			Z = N = A = (data >> 1) + (C << 7);
+			C = data >> 7;
+#ifndef NO_V_FLAG_VARIABLE
+			V = C ^ ((A >> 5) & 1);
+#else
+			CPU_regP = (CPU_regP & 0xbf) + ((A ^ data) & 0x40);
+#endif
+		}
+		DONE
+
+	OPCODE(6c)				/* JMP (abcd) */
+#ifdef MONITOR_BREAK
+		CPU_remember_JMP[CPU_remember_jmp_curpos] = GET_PC() - 1;
+		CPU_remember_jmp_curpos = (CPU_remember_jmp_curpos + 1) % CPU_REMEMBER_JMP_STEPS;
+#endif
+		ABSOLUTE;
+#ifdef CPU65C02
+		/* XXX: if ((UBYTE) addr == 0xff) ANTIC_xpos++; */
+		SET_PC(MEMORY_dGetWord(addr));
+#else
+		/* original 6502 had a bug in JMP (addr) when addr crossed page boundary */
+		if ((UBYTE) addr == 0xff)
+			SET_PC((MEMORY_dGetByte(addr - 0xff) << 8) + MEMORY_dGetByte(addr));
+		else
+			SET_PC(MEMORY_dGetWord(addr));
+#endif
+		DONE
+
+	OPCODE(6d)				/* ADC abcd */
+		ABSOLUTE;
+		data = MEMORY_GetByte(addr);
+		goto adc;
+
+	OPCODE(6e)				/* ROR abcd */
+		ABSOLUTE;
+		RMW_GetByte(data, addr);
+		Z = N = (C << 7) + (data >> 1);
+		C = data & 1;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(6f)				/* RRA abcd [unofficial - ROR Mem, then ADC to Acc] */
+		ABSOLUTE;
+		goto rra;
+
+	OPCODE(70)				/* BVS */
+#ifndef NO_V_FLAG_VARIABLE
+		BRANCH(V)
+#else
+		BRANCH(CPU_regP & 0x40)
+#endif
+
+	OPCODE(71)				/* ADC (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		data = MEMORY_GetByte(addr);
+		goto adc;
+
+	OPCODE(73)				/* RRA (ab),y [unofficial - ROR Mem, then ADC to Acc] */
+		INDIRECT_Y;
+		goto rra;
+
+	OPCODE(75)				/* ADC ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		goto adc;
+
+	OPCODE(76)				/* ROR ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		Z = N = (C << 7) + (data >> 1);
+		C = data & 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(77)				/* RRA ab,x [unofficial - ROR Mem, then ADC to Acc] */
+		ZPAGE_X;
+		goto rra_zpage;
+
+	OPCODE(78)				/* SEI */
+		CPU_SetI;
+		DONE
+
+	OPCODE(79)				/* ADC abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		data = MEMORY_GetByte(addr);
+		goto adc;
+
+	OPCODE(7b)				/* RRA abcd,y [unofficial - ROR Mem, then ADC to Acc] */
+		ABSOLUTE_Y;
+		goto rra;
+
+	OPCODE(7d)				/* ADC abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		data = MEMORY_GetByte(addr);
+		goto adc;
+
+	OPCODE(7e)				/* ROR abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(data, addr);
+		Z = N = (C << 7) + (data >> 1);
+		C = data & 1;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(7f)				/* RRA abcd,x [unofficial - ROR Mem, then ADC to Acc] */
+		ABSOLUTE_X;
+		goto rra;
+
+	OPCODE(81)				/* STA (ab,x) */
+		INDIRECT_X;
+		MEMORY_PutByte(addr, A);
+		DONE
+
+	/* AXS doesn't change flags and SAX is better name for it (Fox) */
+	OPCODE(83)				/* SAX (ab,x) [unofficial - Store result A AND X */
+		INDIRECT_X;
+		data = A & X;
+		MEMORY_PutByte(addr, data);
+		DONE
+
+	OPCODE(84)				/* STY ab */
+		ZPAGE;
+		MEMORY_dPutByte(addr, Y);
+		DONE
+
+	OPCODE(85)				/* STA ab */
+		ZPAGE;
+		MEMORY_dPutByte(addr, A);
+		DONE
+
+	OPCODE(86)				/* STX ab */
+		ZPAGE;
+		MEMORY_dPutByte(addr, X);
+		DONE
+
+	OPCODE(87)				/* SAX ab [unofficial - Store result A AND X] */
+		ZPAGE;
+		data = A & X;
+		MEMORY_dPutByte(addr, data);
+		DONE
+
+	OPCODE(88)				/* DEY */
+		Z = N = --Y;
+		DONE
+
+	OPCODE(8a)				/* TXA */
+		Z = N = A = X;
+		DONE
+
+	OPCODE(8b)				/* ANE #ab [unofficial - A AND X AND (Mem OR $EF) to Acc] (Fox) */
+		data = IMMEDIATE;
+		Z = N = A & X & data;
+		A &= X & (data | 0xef);
+		DONE
+
+	OPCODE(8c)				/* STY abcd */
+		ABSOLUTE;
+		MEMORY_PutByte(addr, Y);
+		DONE
+
+	OPCODE(8d)				/* STA abcd */
+		ABSOLUTE;
+		MEMORY_PutByte(addr, A);
+		DONE
+
+	OPCODE(8e)				/* STX abcd */
+		ABSOLUTE;
+		MEMORY_PutByte(addr, X);
+		DONE
+
+	OPCODE(8f)				/* SAX abcd [unofficial - Store result A AND X] */
+		ABSOLUTE;
+		data = A & X;
+		MEMORY_PutByte(addr, data);
+		DONE
+
+	OPCODE(90)				/* BCC */
+		BRANCH(!C)
+
+	OPCODE(91)				/* STA (ab),y */
+		INDIRECT_Y;
+		MEMORY_PutByte(addr, A);
+		DONE
+
+	OPCODE(93)				/* SHA (ab),y [unofficial, UNSTABLE - Store A AND X AND (H+1) ?] (Fox) */
+		/* It seems previous memory value is important - also in 9f */
+		ZPAGE;
+		addr = zGetWord(addr);
+		data = A & X & ((addr >> 8) + 1);
+		if ((addr & 0xff) + Y > 0xff) { /* if it crosses a page */
+			MEMORY_PutByte(((addr + Y) & 0xff) | (data << 8), data);
+		}
+		else {
+			MEMORY_PutByte(addr + Y, data);
+		}
+		DONE
+
+	OPCODE(94)				/* STY ab,x */
+		ZPAGE_X;
+		MEMORY_dPutByte(addr, Y);
+		DONE
+
+	OPCODE(95)				/* STA ab,x */
+		ZPAGE_X;
+		MEMORY_dPutByte(addr, A);
+		DONE
+
+	OPCODE(96)				/* STX ab,y */
+		ZPAGE_Y;
+		MEMORY_PutByte(addr, X);
+		DONE
+
+	OPCODE(97)				/* SAX ab,y [unofficial - Store result A AND X] */
+		ZPAGE_Y;
+		data = A & X;
+		MEMORY_dPutByte(addr, data);
+		DONE
+
+	OPCODE(98)				/* TYA */
+		Z = N = A = Y;
+		DONE
+
+	OPCODE(99)				/* STA abcd,y */
+		ABSOLUTE_Y;
+		MEMORY_PutByte(addr, A);
+		DONE
+
+	OPCODE(9a)				/* TXS */
+		S = X;
+		DONE
+
+	OPCODE(9b)				/* SHS abcd,y [unofficial, UNSTABLE] (Fox) */
+		/* Transfer A AND X to S, then store S AND (H+1)] */
+		/* S seems to be stable, only memory values vary */
+		ABSOLUTE;
+		S = A & X;
+		data = S & ((addr >> 8) + 1);
+		if ((addr & 0xff) + Y > 0xff) { /* if it crosses a page */
+			MEMORY_PutByte(((addr + Y) & 0xff) | (data << 8), data);
+		}
+		else {
+			MEMORY_PutByte(addr + Y, data);
+		}
+		DONE
+
+	OPCODE(9c)				/* SHY abcd,x [unofficial - Store Y and (H+1)] (Fox) */
+		/* Seems to be stable */
+		ABSOLUTE;
+		/* MPC 05/24/00 */
+		data = Y & ((UBYTE) ((addr >> 8) + 1));
+		if ((addr & 0xff) + X > 0xff) { /* if it crosses a page */
+			MEMORY_PutByte(((addr + X) & 0xff) | (data << 8), data);
+		}
+		else {
+			MEMORY_PutByte(addr + X, data);
+		}
+		DONE
+
+	OPCODE(9d)				/* STA abcd,x */
+		ABSOLUTE_X;
+		MEMORY_PutByte(addr, A);
+		DONE
+
+	OPCODE(9e)				/* SHX abcd,y [unofficial - Store X and (H+1)] (Fox) */
+		/* Seems to be stable */
+		ABSOLUTE;
+		/* MPC 05/24/00 */
+		data = X & ((UBYTE) ((addr >> 8) + 1));
+		if ((addr & 0xff) + Y > 0xff) { /* if it crosses a page */
+			MEMORY_PutByte(((addr + Y) & 0xff) | (data << 8), data);
+		}
+		else {
+			MEMORY_PutByte(addr + Y, data);
+		}
+		DONE
+
+	OPCODE(9f)				/* SHA abcd,y [unofficial, UNSTABLE - Store A AND X AND (H+1) ?] (Fox) */
+		ABSOLUTE;
+		data = A & X & ((addr >> 8) + 1);
+		if ((addr & 0xff) + Y > 0xff) { /* if it crosses a page */
+			MEMORY_PutByte(((addr + Y) & 0xff) | (data << 8), data);
+		}
+		else {
+			MEMORY_PutByte(addr + Y, data);
+		}
+		DONE
+
+	OPCODE(a0)				/* LDY #ab */
+		LDY(IMMEDIATE);
+		DONE
+
+	OPCODE(a1)				/* LDA (ab,x) */
+		INDIRECT_X;
+		LDA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(a2)				/* LDX #ab */
+		LDX(IMMEDIATE);
+		DONE
+
+	OPCODE(a3)				/* LAX (ab,x) [unofficial] */
+		INDIRECT_X;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(a4)				/* LDY ab */
+		ZPAGE;
+		LDY(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(a5)				/* LDA ab */
+		ZPAGE;
+		LDA(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(a6)				/* LDX ab */
+		ZPAGE;
+		LDX(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(a7)				/* LAX ab [unofficial] */
+		ZPAGE;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(a8)				/* TAY */
+		Z = N = Y = A;
+		DONE
+
+	OPCODE(a9)				/* LDA #ab */
+		LDA(IMMEDIATE);
+		DONE
+
+	OPCODE(aa)				/* TAX */
+		Z = N = X = A;
+		DONE
+
+	OPCODE(ab)				/* ANX #ab [unofficial - AND #ab, then TAX] */
+		Z = N = X = A &= IMMEDIATE;
+		DONE
+
+	OPCODE(ac)				/* LDY abcd */
+		ABSOLUTE;
+		LDY(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(ad)				/* LDA abcd */
+		ABSOLUTE;
+		LDA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(ae)				/* LDX abcd */
+		ABSOLUTE;
+		LDX(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(af)				/* LAX abcd [unofficial] */
+		ABSOLUTE;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(b0)				/* BCS */
+		BRANCH(C)
+
+	OPCODE(b1)				/* LDA (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		LDA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(b3)				/* LAX (ab),y [unofficial] */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(b4)				/* LDY ab,x */
+		ZPAGE_X;
+		LDY(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(b5)				/* LDA ab,x */
+		ZPAGE_X;
+		LDA(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(b6)				/* LDX ab,y */
+		ZPAGE_Y;
+		LDX(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(b7)				/* LAX ab,y [unofficial] */
+		ZPAGE_Y;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(b8)				/* CLV */
+#ifndef NO_V_FLAG_VARIABLE
+		V = 0;
+#else
+		CPU_ClrV;
+#endif
+		DONE
+
+	OPCODE(b9)				/* LDA abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		LDA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(ba)				/* TSX */
+		Z = N = X = S;
+		DONE
+
+/* AXA [unofficial - original decode by R.Sterba and R.Petruzela 15.1.1998 :-)]
+   AXA - this is our new imaginative name for instruction with opcode hex BB.
+   AXA - Store Mem AND #$FD to Acc and X, then set stackpoint to value (Acc - 4)
+   It's cool! :-)
+   LAS - this is better name for this :) (Fox)
+   It simply ANDs stack pointer with Mem, then transfers result to A and X
+ */
+
+	OPCODE(bb)				/* LAS abcd,y [unofficial - AND S with Mem, transfer to A and X (Fox) */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		Z = N = A = X = S &= MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(bc)				/* LDY abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		LDY(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(bd)				/* LDA abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		LDA(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(be)				/* LDX abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		LDX(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(bf)				/* LAX abcd,y [unofficial] */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		Z = N = X = A = MEMORY_GetByte(addr);
+		DONE
+
+	OPCODE(c0)				/* CPY #ab */
+		CPY(IMMEDIATE);
+		DONE
+
+	OPCODE(c1)				/* CMP (ab,x) */
+		INDIRECT_X;
+		CMP(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(c3)				/* DCM (ab,x) [unofficial - DEC Mem then CMP with Acc] */
+		INDIRECT_X;
+
+	dcm:
+		RMW_GetByte(data, addr);
+		data--;
+		MEMORY_PutByte(addr, data);
+		CMP(data);
+		DONE
+
+	OPCODE(c4)				/* CPY ab */
+		ZPAGE;
+		CPY(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(c5)				/* CMP ab */
+		ZPAGE;
+		CMP(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(c6)				/* DEC ab */
+		ZPAGE;
+		Z = N = MEMORY_dGetByte(addr) - 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(c7)				/* DCM ab [unofficial - DEC Mem then CMP with Acc] */
+		ZPAGE;
+
+	dcm_zpage:
+		data = MEMORY_dGetByte(addr) - 1;
+		MEMORY_dPutByte(addr, data);
+		CMP(data);
+		DONE
+
+	OPCODE(c8)				/* INY */
+		Z = N = ++Y;
+		DONE
+
+	OPCODE(c9)				/* CMP #ab */
+		CMP(IMMEDIATE);
+		DONE
+
+	OPCODE(ca)				/* DEX */
+		Z = N = --X;
+		DONE
+
+	OPCODE(cb)				/* SBX #ab [unofficial - store ((A AND X) - Mem) in X] (Fox) */
+		X &= A;
+		data = IMMEDIATE;
+		C = X >= data;
+		/* MPC 05/24/00 */
+		Z = N = X -= data;
+		DONE
+
+	OPCODE(cc)				/* CPY abcd */
+		ABSOLUTE;
+		CPY(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(cd)				/* CMP abcd */
+		ABSOLUTE;
+		CMP(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(ce)				/* DEC abcd */
+		ABSOLUTE;
+		RMW_GetByte(Z, addr);
+		N = --Z;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(cf)				/* DCM abcd [unofficial - DEC Mem then CMP with Acc] */
+		ABSOLUTE;
+		goto dcm;
+
+	OPCODE(d0)				/* BNE */
+		BRANCH(Z)
+
+	OPCODE(d1)				/* CMP (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		CMP(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(d3)				/* DCM (ab),y [unofficial - DEC Mem then CMP with Acc] */
+		INDIRECT_Y;
+		goto dcm;
+
+	OPCODE(d5)				/* CMP ab,x */
+		ZPAGE_X;
+		CMP(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(d6)				/* DEC ab,x */
+		ZPAGE_X;
+		Z = N = MEMORY_dGetByte(addr) - 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(d7)				/* DCM ab,x [unofficial - DEC Mem then CMP with Acc] */
+		ZPAGE_X;
+		goto dcm_zpage;
+
+	OPCODE(d8)				/* CLD */
+		CPU_ClrD;
+		DONE
+
+	OPCODE(d9)				/* CMP abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		CMP(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(db)				/* DCM abcd,y [unofficial - DEC Mem then CMP with Acc] */
+		ABSOLUTE_Y;
+		goto dcm;
+
+	OPCODE(dd)				/* CMP abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		CMP(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(de)				/* DEC abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(Z, addr);
+		N = --Z;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(df)				/* DCM abcd,x [unofficial - DEC Mem then CMP with Acc] */
+		ABSOLUTE_X;
+		goto dcm;
+
+	OPCODE(e0)				/* CPX #ab */
+		CPX(IMMEDIATE);
+		DONE
+
+	OPCODE(e1)				/* SBC (ab,x) */
+		INDIRECT_X;
+		data = MEMORY_GetByte(addr);
+		goto sbc;
+
+	OPCODE(e3)				/* INS (ab,x) [unofficial - INC Mem then SBC with Acc] */
+		INDIRECT_X;
+
+	ins:
+		RMW_GetByte(data, addr);
+		++data;
+		MEMORY_PutByte(addr, data);
+		goto sbc;
+
+	OPCODE(e4)				/* CPX ab */
+		ZPAGE;
+		CPX(MEMORY_dGetByte(addr));
+		DONE
+
+	OPCODE(e5)				/* SBC ab */
+		ZPAGE;
+		data = MEMORY_dGetByte(addr);
+		goto sbc;
+
+	OPCODE(e6)				/* INC ab */
+		ZPAGE;
+		Z = N = MEMORY_dGetByte(addr) + 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(e7)				/* INS ab [unofficial - INC Mem then SBC with Acc] */
+		ZPAGE;
+
+	ins_zpage:
+		data = MEMORY_dGetByte(addr) + 1;
+		MEMORY_dPutByte(addr, data);
+		goto sbc;
+
+	OPCODE(e8)				/* INX */
+		Z = N = ++X;
+		DONE
+
+	OPCODE_ALIAS(e9)		/* SBC #ab */
+	OPCODE(eb)				/* SBC #ab [unofficial] */
+		data = IMMEDIATE;
+		goto sbc;
+
+	OPCODE_ALIAS(ea)		/* NOP */
+	OPCODE_ALIAS(1a)		/* NOP [unofficial] */
+	OPCODE_ALIAS(3a)
+	OPCODE_ALIAS(5a)
+	OPCODE_ALIAS(7a)
+	OPCODE_ALIAS(da)
+	OPCODE(fa)
+		DONE
+
+	OPCODE(ec)				/* CPX abcd */
+		ABSOLUTE;
+		CPX(MEMORY_GetByte(addr));
+		DONE
+
+	OPCODE(ed)				/* SBC abcd */
+		ABSOLUTE;
+		data = MEMORY_GetByte(addr);
+		goto sbc;
+
+	OPCODE(ee)				/* INC abcd */
+		ABSOLUTE;
+		RMW_GetByte(Z, addr);
+		N = ++Z;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(ef)				/* INS abcd [unofficial - INC Mem then SBC with Acc] */
+		ABSOLUTE;
+		goto ins;
+
+	OPCODE(f0)				/* BEQ */
+		BRANCH(!Z)
+
+	OPCODE(f1)				/* SBC (ab),y */
+		INDIRECT_Y;
+		NCYCLES_Y;
+		data = MEMORY_GetByte(addr);
+		goto sbc;
+
+	OPCODE(f3)				/* INS (ab),y [unofficial - INC Mem then SBC with Acc] */
+		INDIRECT_Y;
+		goto ins;
+
+	OPCODE(f5)				/* SBC ab,x */
+		ZPAGE_X;
+		data = MEMORY_dGetByte(addr);
+		goto sbc;
+
+	OPCODE(f6)				/* INC ab,x */
+		ZPAGE_X;
+		Z = N = MEMORY_dGetByte(addr) + 1;
+		MEMORY_dPutByte(addr, Z);
+		DONE
+
+	OPCODE(f7)				/* INS ab,x [unofficial - INC Mem then SBC with Acc] */
+		ZPAGE_X;
+		goto ins_zpage;
+
+	OPCODE(f8)				/* SED */
+		CPU_SetD;
+		DONE
+
+	OPCODE(f9)				/* SBC abcd,y */
+		ABSOLUTE_Y;
+		NCYCLES_Y;
+		data = MEMORY_GetByte(addr);
+		goto sbc;
+
+	OPCODE(fb)				/* INS abcd,y [unofficial - INC Mem then SBC with Acc] */
+		ABSOLUTE_Y;
+		goto ins;
+
+	OPCODE(fd)				/* SBC abcd,x */
+		ABSOLUTE_X;
+		NCYCLES_X;
+		data = MEMORY_GetByte(addr);
+		goto sbc;
+
+	OPCODE(fe)				/* INC abcd,x */
+		ABSOLUTE_X;
+		RMW_GetByte(Z, addr);
+		N = ++Z;
+		MEMORY_PutByte(addr, Z);
+		DONE
+
+	OPCODE(ff)				/* INS abcd,x [unofficial - INC Mem then SBC with Acc] */
+		ABSOLUTE_X;
+		goto ins;
+
+#ifdef ASAP
+
+	OPCODE_ALIAS(d2)
+	OPCODE_ALIAS(f2)
+
+#else
+
+	OPCODE(d2)				/* ESCRTS #ab (CIM) - on Atari is here instruction CIM [unofficial] !RS! */
+		data = IMMEDIATE;
+		UPDATE_GLOBAL_REGS;
+		CPU_GetStatus();
+		ESC_Run(data);
+		CPU_PutStatus();
+		UPDATE_LOCAL_REGS;
+		data = PL;
+		SET_PC((PL << 8) + data + 1);
+#ifdef MONITOR_BREAK
+		if (MONITOR_break_ret && --MONITOR_ret_nesting <= 0)
+			MONITOR_break_step = TRUE;
+#endif
+		DONE
+
+	OPCODE(f2)				/* ESC #ab (CIM) - on Atari is here instruction CIM [unofficial] !RS! */
+		/* OPCODE(ff: ESC #ab - opcode FF is now used for INS [unofficial] instruction !RS! */
+		data = IMMEDIATE;
+		UPDATE_GLOBAL_REGS;
+		CPU_GetStatus();
+		ESC_Run(data);
+		CPU_PutStatus();
+		UPDATE_LOCAL_REGS;
+		DONE
+
+#endif /* ASAP */
+
+	OPCODE_ALIAS(02)		/* CIM [unofficial - crash intermediate] */
+	OPCODE_ALIAS(12)
+	OPCODE_ALIAS(22)
+	OPCODE_ALIAS(32)
+	OPCODE_ALIAS(42)
+	OPCODE_ALIAS(52)
+	OPCODE_ALIAS(62)
+	OPCODE_ALIAS(72)
+	OPCODE_ALIAS(92)
+	OPCODE(b2)
+
+#ifdef ASAP
+
+		ASAP_CIM();
+		DONE
+
+#else
+
+	/* OPCODE(d2) Used for ESCRTS #ab (CIM) */
+	/* OPCODE(f2) Used for ESC #ab (CIM) */
+		PC--;
+		UPDATE_GLOBAL_REGS;
+		CPU_GetStatus();
+
+#ifdef CRASH_MENU
+		UI_crash_address = GET_PC();
+		UI_crash_afterCIM = GET_PC() + 1;
+		UI_crash_code = insn;
+		UI_Run();
+#else
+		CPU_cim_encountered = TRUE;
+		ENTER_MONITOR;
+#endif /* CRASH_MENU */
+
+		CPU_PutStatus();
+		UPDATE_LOCAL_REGS;
+		DONE
+
+#endif /* ASAP */
+
+/* ---------------------------------------------- */
+/* ADC and SBC routines */
+
+	adc:
+		if (!(CPU_regP & CPU_D_FLAG)) {
+			/* Binary mode */
+			unsigned int tmp;
+			tmp = A + data + C;
+			C = tmp > 0xff;
+			/* C = tmp >> 8; */
+#ifndef NO_V_FLAG_VARIABLE
+			V = !((A ^ data) & 0x80) && ((data ^ tmp) & 0x80);
+#else
+			CPU_ClrV;
+			if (!((A ^ data) & 0x80) && ((data ^ tmp) & 0x80))
+				CPU_SetV;
+#endif
+			Z = N = A = (UBYTE) tmp;
+	    }
+		else {
+			/* Decimal mode */
+			unsigned int tmp;
+			tmp = (A & 0x0f) + (data & 0x0f) + C;
+			if (tmp >= 0x0a)
+				tmp = ((tmp + 0x06) & 0x0f) + 0x10;
+			tmp += (A & 0xf0) + (data & 0xf0);
+
+			Z = A + data + C;
+			N = (UBYTE) tmp;
+#ifndef NO_V_FLAG_VARIABLE
+			V = !((A ^ data) & 0x80) && ((data ^ tmp) & 0x80);
+#else
+			CPU_ClrV;
+			if (!((A ^ data) & 0x80) && ((data ^ tmp) & 0x80))
+				CPU_SetV;
+#endif
+
+			if (tmp >= 0xa0)
+				tmp += 0x60;
+			C = tmp > 0xff;
+			A = (UBYTE) tmp;
+		}
+		DONE
+
+	sbc:
+		if (!(CPU_regP & CPU_D_FLAG)) {
+			/* Binary mode */
+			unsigned int tmp;
+			/* tmp = A - data - !C; */
+			tmp = A - data - 1 + C;
+			C = tmp < 0x100;
+#ifndef NO_V_FLAG_VARIABLE
+			V = ((A ^ data) & 0x80) && ((A ^ tmp) & 0x80);
+#else
+			CPU_ClrV;
+			if (((A ^ data) & 0x80) && ((A ^ tmp) & 0x80))
+				CPU_SetV;
+#endif
+			Z = N = A = (UBYTE) tmp;
+		}
+		else {
+			/* Decimal mode */
+			unsigned int tmp;
+			tmp = (A & 0x0f) - (data & 0x0f) - 1 + C;
+			if (tmp & 0x10)
+				tmp = ((tmp - 0x06) & 0x0f) - 0x10;
+			tmp += (A & 0xf0) - (data & 0xf0);
+			if (tmp & 0x100)
+				tmp -= 0x60;
+
+			Z = N = A - data - 1 + C;
+#ifndef NO_V_FLAG_VARIABLE
+			V = ((A ^ data) & 0x80) && ((A ^ Z) & 0x80);
+#else
+			CPU_ClrV;
+			if (((A ^ data) & 0x80) && ((A ^ Z) & 0x80))
+				CPU_SetV;
+#endif
+			C = ((unsigned int) (A - data - 1 + C)) <= 0xff;
+
+			A = tmp;
+		}
+		DONE
+
+#ifdef NO_GOTO
+	}
+#else
+	next:
+#endif
+
+#ifdef MONITOR_PROFILE
+		{
+			int cyc = ANTIC_xpos - old_xpos;
+			MONITOR_coverage[old_PC].cycles += cyc;
+			MONITOR_coverage_cycles += cyc;
+		}
+#endif
+
+#ifdef MONITOR_BREAK
+		if (MONITOR_break_step) {
+			DO_BREAK;
+		}
+#endif
+		/* This "continue" does nothing here.
+		   But it is necessary because, if we're not using NO_GOTO nor MONITOR_BREAK,
+		   gcc can complain: "error: label at end of compound statement". */
+		continue;
+	}
+
+	UPDATE_GLOBAL_REGS;
+}
+
+#endif /* FALCON_CPUASM */
+
+void CPU_Reset(void)
+{
+#ifdef MONITOR_PROFILE
+	memset(CPU_instruction_count, 0, sizeof(CPU_instruction_count));
+#endif
+
+	CPU_IRQ = 0;
+
+	CPU_regP = 0x34;				/* The unused bit is always 1, I flag set! */
+	CPU_PutStatus();	/* Make sure flags are all updated */
+	CPU_regS = 0xff;
+	CPU_regPC = MEMORY_dGetWordAligned(0xfffc);
+}
+
+#if !defined(BASIC) && !defined(ASAP)
+
+void CPU_StateSave(UBYTE SaveVerbose)
+{
+	StateSav_SaveUBYTE(&CPU_regA, 1);
+
+	CPU_GetStatus();	/* Make sure flags are all updated */
+	StateSav_SaveUBYTE(&CPU_regP, 1);
+
+	StateSav_SaveUBYTE(&CPU_regS, 1);
+	StateSav_SaveUBYTE(&CPU_regX, 1);
+	StateSav_SaveUBYTE(&CPU_regY, 1);
+	StateSav_SaveUBYTE(&CPU_IRQ, 1);
+
+	MEMORY_StateSave(SaveVerbose);
+
+	StateSav_SaveUWORD(&CPU_regPC, 1);
+}
+
+void CPU_StateRead(UBYTE SaveVerbose, UBYTE StateVersion)
+{
+	StateSav_ReadUBYTE(&CPU_regA, 1);
+
+	StateSav_ReadUBYTE(&CPU_regP, 1);
+	CPU_PutStatus();	/* Make sure flags are all updated */
+
+	StateSav_ReadUBYTE(&CPU_regS, 1);
+	StateSav_ReadUBYTE(&CPU_regX, 1);
+	StateSav_ReadUBYTE(&CPU_regY, 1);
+	StateSav_ReadUBYTE(&CPU_IRQ, 1);
+
+	MEMORY_StateRead(SaveVerbose, StateVersion);
+
+	StateSav_ReadUWORD(&CPU_regPC, 1);
+}
+
+#endif
diff --git a/MCUME_pico2/pico800/cpu.h b/MCUME_pico2/pico800/cpu.h
new file mode 100644
index 0000000..3ee25e6
--- /dev/null
+++ b/MCUME_pico2/pico800/cpu.h
@@ -0,0 +1,65 @@
+#ifndef CPU_H_
+#define CPU_H_
+
+#include "atari.h"
+
+#define CPU_N_FLAG 0x80
+#define CPU_V_FLAG 0x40
+#define CPU_B_FLAG 0x10
+#define CPU_D_FLAG 0x08
+#define CPU_I_FLAG 0x04
+#define CPU_Z_FLAG 0x02
+#define CPU_C_FLAG 0x01
+
+void CPU_GetStatus(void);
+void CPU_PutStatus(void);
+void CPU_Reset(void);
+void CPU_StateSave(UBYTE SaveVerbose);
+void CPU_StateRead(UBYTE SaveVerbose, UBYTE StateVersion);
+void CPU_NMI(void);
+void CPU_GO(int limit);
+#define CPU_GenerateIRQ() (CPU_IRQ = 1)
+
+extern UWORD CPU_regPC;
+extern UBYTE CPU_regA;
+extern UBYTE CPU_regP;
+extern UBYTE CPU_regS;
+extern UBYTE CPU_regY;
+extern UBYTE CPU_regX;
+
+#define CPU_SetN CPU_regP |= CPU_N_FLAG
+#define CPU_ClrN CPU_regP &= (~CPU_N_FLAG)
+#define CPU_SetV CPU_regP |= CPU_V_FLAG
+#define CPU_ClrV CPU_regP &= (~CPU_V_FLAG)
+#define CPU_SetB CPU_regP |= CPU_B_FLAG
+#define CPU_ClrB CPU_regP &= (~CPU_B_FLAG)
+#define CPU_SetD CPU_regP |= CPU_D_FLAG
+#define CPU_ClrD CPU_regP &= (~CPU_D_FLAG)
+#define CPU_SetI CPU_regP |= CPU_I_FLAG
+#define CPU_ClrI CPU_regP &= (~CPU_I_FLAG)
+#define CPU_SetZ CPU_regP |= CPU_Z_FLAG
+#define CPU_ClrZ CPU_regP &= (~CPU_Z_FLAG)
+#define CPU_SetC CPU_regP |= CPU_C_FLAG
+#define CPU_ClrC CPU_regP &= (~CPU_C_FLAG)
+
+extern UBYTE CPU_IRQ;
+
+extern void (*CPU_rts_handler)(void);
+
+extern UBYTE CPU_cim_encountered;
+
+#define CPU_REMEMBER_PC_STEPS 64
+extern UWORD CPU_remember_PC[CPU_REMEMBER_PC_STEPS];
+extern UBYTE CPU_remember_op[CPU_REMEMBER_PC_STEPS][3];
+extern unsigned int CPU_remember_PC_curpos;
+extern int CPU_remember_xpos[CPU_REMEMBER_PC_STEPS];
+
+#define CPU_REMEMBER_JMP_STEPS 16
+extern UWORD CPU_remember_JMP[CPU_REMEMBER_JMP_STEPS];
+extern unsigned int CPU_remember_jmp_curpos;
+
+#ifdef MONITOR_PROFILE
+extern int CPU_instruction_count[256];
+#endif
+
+#endif /* CPU_H_ */
diff --git a/MCUME_pico2/pico800/crc32.c b/MCUME_pico2/pico800/crc32.c
new file mode 100644
index 0000000..d22e223
--- /dev/null
+++ b/MCUME_pico2/pico800/crc32.c
@@ -0,0 +1,86 @@
+/* CRC32.C -- Calculates 32bit CRC checksum
+ */
+// modified main() (see crc32.orig) to get calc_crc32() function
+// JH 2002
+
+#include <stdio.h>
+#include <stdlib.h>
+
+const unsigned long crc32_table[256] = { /* lookup table */
+0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F,
+0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
+0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2,
+0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
+0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9,
+0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
+0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C,
+0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
+0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423,
+0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
+0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106,
+0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
+0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D,
+0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
+0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950,
+0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
+0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7,
+0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
+0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA,
+0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
+0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81,
+0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
+0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84,
+0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
+0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB,
+0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
+0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E,
+0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
+0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55,
+0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
+0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28,
+0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
+0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F,
+0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
+0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242,
+0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
+0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69,
+0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
+0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC,
+0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
+0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693,
+0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
+0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D};
+
+unsigned long calc_crc32(unsigned char *buf, int buflen)
+{
+    // buf is pointer to input buffer (data to crc)
+    // buflen is length of input buffer
+
+	unsigned long crc;  /* CRC value */
+	//size_t j;        /* buffer positions*/
+	int j;		        /* buffer positions*/
+	int k;              /* generic integer */
+
+#ifdef DEBUG
+	printf("32bit Cyclic Redudancy Check\n");
+#endif
+
+	crc = 0xFFFFFFFF; /* preconditioning sets non zero value */
+
+	/* loop through the buffer and calculate CRC */
+	for(j=0; j<buflen; j++){
+		k=(crc ^ buf[j]) & 0x000000FFL;
+		crc=((crc >> 8) & 0x00FFFFFFL) ^ crc32_table[k];
+	}
+
+	crc=~crc; /* postconditioning */
+
+	/* print results */
+#ifdef DEBUG
+	printf("CRC32 is %08lX\n", crc);
+#endif
+
+	return crc;
+}
+
+
diff --git a/MCUME_pico2/pico800/emucfg.h b/MCUME_pico2/pico800/emucfg.h
new file mode 100644
index 0000000..9600d0c
--- /dev/null
+++ b/MCUME_pico2/pico800/emucfg.h
@@ -0,0 +1,98 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+#define CUSTOM_SND_C         1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    Atari 800 Emulator"
+#define ROMSDIR "800"
+
+#define emu_Init(ROM) {at8_Init(); at8_Start(ROM);}
+#define emu_Step(x) {at8_Step();}
+#define emu_Input(x) {at8_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  0x1F+1,0x1F,0x1A+1,0x18+1,0x1D+1,0x1B+1,0x33+1,0x35+1,0x30+1,0x32+1,
+  0x2F+1,0x2F,0x2A+1,0x28+1,0x2D+1,0x2B+1,0x0B+1,0x0D+1,0x08+1,0x0A+1,
+  0x3F+1,0x3F,0x3A+1,0x38+1,0x3D+1,0x39+1,0x01+1,0x05+1,0x00+1,0x0D,
+  0,0x17+1,0x16+1,0x12+1,0x10+1,0x15+1,0x23+1,0x25+1,0,0x21+1,
+  0,0,0,0,0x34+1,0x87+1 // back R
+  };  
+
+const unsigned short key_map2[] = {
+  95+1,117+1,90+1,88+1,93+1,91+1,115+1,112+1,114+1,0,
+  0,0,0,0x36+1,0x37+1,0,0,0,0x02+1,94+1,
+  0,0,0,0,0,0,0x0E + 1,0x06+1,0x0F+1,0x0D,
+  0,66+1,0,102+1,0x26+1,0x07+1,0x20+1,0x22+1,0,' ',
+  0x8e + 1,0x86+1,0x87+1,0x8f+1,0x34+1,0x87+1 //U L R D back R
+  };  
+
+const unsigned short key_map3[] = {
+  3+1,4+1,19+1,20+1,17+1,0,0,0,0,0, // function keys
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0x8e + 1,0x86+1,0x87+1,0x8f+1,0x34+1,0x87+1 //U L R D back R
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else
+
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  0x2F+1,0x2F,0x2A+1,0x28+1,0x2D+1,0x2B+1,0x0B+1,0x0D+1,0x08+1,0x0A+1,0x34+1, 
+  0,0x3F+1,0x3F,0x3A+1,0x38+1,0x3D+1,0x39+1,0x01+1,0x05+1,0x00+1,0x0C+1, 
+  0,0x17+1,0x16+1,0x12+1,0x10+1,0x15+1,0x23+1,0x25+1,0x22+1, 0x21+1,
+  0,0,0,0
+  };  
+
+#define keylables_map2_0 (char *)"1234567890="
+#define keylables_map2_1 (char *)"T!@#$%+&*- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  0x1F+1,0x1F,0x1A+1,0x18+1,0x1D+1,0x1B+1,0x33+1,0x35+1,0x30+1,0x32+1,0x0F+1, // Digits
+  0x2C+1,95+1,117+1,90+1,88+1,93+1,0x06+1,91+1,0x07+1,0x0E + 1,0, // various 
+  0, 112+1,114+1,102+1,0x26+1,94+1,0x36+1,0x37+1,0x20+1,66+1,
+  0x8e + 1,0x86+1,0x87+1,0x8f+1 //U L R D
+  };  
+  //0x07+1=*, 0x22+1=.,0x26+1=/, 0x02+1=;, 0x06+1=+, 0x36+1=<, 0x37+1=>, 0x0F+1==, 0x0E+1=-, 0x06+1=+
+
+#define keylables_map3_0 (char *)"\x11\x12\x13\x14H      "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"     '  ;  "
+const unsigned short key_map3[] = {
+  3+1,4+1,19+1,20+1,17+1,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,115+1,0,0,0x02+1,0,
+  0x8e + 1,0x86+1,0x87+1,0x8f+1 //U L R D
+  };
+
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico800/gtia.c b/MCUME_pico2/pico800/gtia.c
new file mode 100644
index 0000000..1d3612c
--- /dev/null
+++ b/MCUME_pico2/pico800/gtia.c
@@ -0,0 +1,1330 @@
+/*
+ * gtia.c - GTIA chip emulation
+ *
+ * Copyright (C) 1995-1998 David Firth
+ * Copyright (C) 1998-2015 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <string.h>
+
+#include "antic.h"
+#include "gtia.h"
+
+/* GTIA Registers ---------------------------------------------------------- */
+
+UBYTE GTIA_M0PL;
+UBYTE GTIA_M1PL;
+UBYTE GTIA_M2PL;
+UBYTE GTIA_M3PL;
+UBYTE GTIA_P0PL;
+UBYTE GTIA_P1PL;
+UBYTE GTIA_P2PL;
+UBYTE GTIA_P3PL;
+UBYTE GTIA_HPOSP0;
+UBYTE GTIA_HPOSP1;
+UBYTE GTIA_HPOSP2;
+UBYTE GTIA_HPOSP3;
+UBYTE GTIA_HPOSM0;
+UBYTE GTIA_HPOSM1;
+UBYTE GTIA_HPOSM2;
+UBYTE GTIA_HPOSM3;
+UBYTE GTIA_SIZEP0;
+UBYTE GTIA_SIZEP1;
+UBYTE GTIA_SIZEP2;
+UBYTE GTIA_SIZEP3;
+UBYTE GTIA_SIZEM;
+UBYTE GTIA_GRAFP0;
+UBYTE GTIA_GRAFP1;
+UBYTE GTIA_GRAFP2;
+UBYTE GTIA_GRAFP3;
+UBYTE GTIA_GRAFM;
+UBYTE GTIA_COLPM0;
+UBYTE GTIA_COLPM1;
+UBYTE GTIA_COLPM2;
+UBYTE GTIA_COLPM3;
+UBYTE GTIA_COLPF0;
+UBYTE GTIA_COLPF1;
+UBYTE GTIA_COLPF2;
+UBYTE GTIA_COLPF3;
+UBYTE GTIA_COLBK;
+UBYTE GTIA_PRIOR;
+UBYTE GTIA_VDELAY;
+UBYTE GTIA_GRACTL;
+
+/* Internal GTIA state ----------------------------------------------------- */
+
+int GTIA_speaker;
+int GTIA_consol_override = 0;
+static UBYTE consol;
+UBYTE consol_mask;
+UBYTE GTIA_TRIG[4];
+UBYTE GTIA_TRIG_latch[4];
+
+#if defined(BASIC) || defined(CURSES_BASIC)
+
+static UBYTE PF0PM = 0;
+static UBYTE PF1PM = 0;
+static UBYTE PF2PM = 0;
+static UBYTE PF3PM = 0;
+#define GTIA_collisions_mask_missile_playfield 0
+#define GTIA_collisions_mask_player_playfield 0
+#define GTIA_collisions_mask_missile_player 0
+#define GTIA_collisions_mask_player_player 0
+
+#else /* defined(BASIC) || defined(CURSES_BASIC) */
+
+void set_prior(UBYTE byte);			/* in antic.c */
+
+/* Player/Missile stuff ---------------------------------------------------- */
+
+/* change to 0x00 to disable collisions */
+UBYTE GTIA_collisions_mask_missile_playfield = 0x0f;
+UBYTE GTIA_collisions_mask_player_playfield = 0x0f;
+UBYTE GTIA_collisions_mask_missile_player = 0x0f;
+UBYTE GTIA_collisions_mask_player_player = 0x0f;
+
+#ifdef NEW_CYCLE_EXACT
+/* temporary collision registers for the current scanline only */
+UBYTE P1PL_T;
+UBYTE P2PL_T;
+UBYTE P3PL_T;
+UBYTE M0PL_T;
+UBYTE M1PL_T;
+UBYTE M2PL_T;
+UBYTE M3PL_T;
+/* If partial collisions have been generated during a scanline, this
+ * is the position of the up-to-date collision point , otherwise it is 0
+ */
+int collision_curpos;
+/* if hitclr has been written to during a scanline, this is the position
+ * within pm_scaline at which it was written to, and collisions should
+ * only be generated from this point on, otherwise it is 0
+ */
+int hitclr_pos;
+#else
+#define P1PL_T GTIA_P1PL
+#define P2PL_T GTIA_P2PL
+#define P3PL_T GTIA_P3PL
+#define M0PL_T GTIA_M0PL
+#define M1PL_T GTIA_M1PL
+#define M2PL_T GTIA_M2PL
+#define M3PL_T GTIA_M3PL
+#endif /* NEW_CYCLE_EXACT */
+
+static UBYTE *hposp_ptr[4];
+static UBYTE *hposm_ptr[4];
+static ULONG hposp_mask[4];
+
+static ULONG grafp_lookup[4][256];
+static ULONG *grafp_ptr[4];
+static int global_sizem[4];
+
+static const int PM_Width[4] = {1, 2, 1, 4};
+
+/* Meaning of bits in GTIA_pm_scanline:
+bit 0 - Player 0
+bit 1 - Player 1
+bit 2 - Player 2
+bit 3 - Player 3
+bit 4 - Missile 0
+bit 5 - Missile 1
+bit 6 - Missile 2
+bit 7 - Missile 3
+*/
+
+UBYTE GTIA_pm_scanline[ATARI_WIDTH / 2 + 8];	/* there's a byte for every *pair* of pixels */
+int GTIA_pm_dirty = TRUE;
+
+#define C_PM0	0x01
+#define C_PM1	0x02
+#define C_PM01	0x03
+#define C_PM2	0x04
+#define C_PM3	0x05
+#define C_PM23	0x06
+#define C_PM023	0x07
+#define C_PM123	0x08
+#define C_PM0123 0x09
+#define C_PM25	0x0a
+#define C_PM35	0x0b
+#define C_PM235	0x0c
+#define C_COLLS	0x0d
+#define C_BAK	0x00
+#define C_HI2	0x20
+#define C_HI3	0x30
+#define C_PF0	0x40
+#define C_PF1	0x50
+#define C_PF2	0x60
+#define C_PF3	0x70
+
+#define PF0PM (*(UBYTE *) &ANTIC_cl[C_PF0 | C_COLLS])
+#define PF1PM (*(UBYTE *) &ANTIC_cl[C_PF1 | C_COLLS])
+#define PF2PM (*(UBYTE *) &ANTIC_cl[C_PF2 | C_COLLS])
+#define PF3PM (*(UBYTE *) &ANTIC_cl[C_PF3 | C_COLLS])
+
+/* Colours ----------------------------------------------------------------- */
+
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+UWORD colour_translation_table[256];
+#endif /* USE_COLOUR_TRANSLATION_TABLE */
+
+static void setup_gtia9_11(void) {
+	int i;
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+	UWORD temp;
+	temp = colour_translation_table[GTIA_COLBK & 0xf0];
+	ANTIC_lookup_gtia11[0] = ((ULONG) temp << 16) + temp;
+	for (i = 1; i < 16; i++) {
+		temp = colour_translation_table[GTIA_COLBK | i];
+		ANTIC_lookup_gtia9[i] = ((ULONG) temp << 16) + temp;
+		temp = colour_translation_table[GTIA_COLBK | (i << 4)];
+		ANTIC_lookup_gtia11[i] = ((ULONG) temp << 16) + temp;
+	}
+#else
+	ULONG count9 = 0;
+	ULONG count11 = 0;
+	ANTIC_lookup_gtia11[0] = ANTIC_lookup_gtia9[0] & 0xf0f0f0f0;
+	for (i = 1; i < 16; i++) {
+		ANTIC_lookup_gtia9[i] = ANTIC_lookup_gtia9[0] | (count9 += 0x01010101);
+		ANTIC_lookup_gtia11[i] = ANTIC_lookup_gtia9[0] | (count11 += 0x10101010);
+	}
+#endif
+}
+
+#endif /* defined(BASIC) || defined(CURSES_BASIC) */
+
+/* Initialization ---------------------------------------------------------- */
+
+int GTIA_Initialise(void)
+{
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+	int i;
+	for (i = 0; i < 256; i++) {
+		int tmp = i + 0x100;
+		ULONG grafp1 = 0;
+		ULONG grafp2 = 0;
+		ULONG grafp4 = 0;
+		do {
+			grafp1 <<= 1;
+			grafp2 <<= 2;
+			grafp4 <<= 4;
+			if (tmp & 1) {
+				grafp1++;
+				grafp2 += 3;
+				grafp4 += 15;
+			}
+			tmp >>= 1;
+		} while (tmp != 1);
+		grafp_lookup[2][i] = grafp_lookup[0][i] = grafp1;
+		grafp_lookup[1][i] = grafp2;
+		grafp_lookup[3][i] = grafp4;
+	}
+	memset(ANTIC_cl, GTIA_COLOUR_BLACK, sizeof(ANTIC_cl));
+	for (i = 0; i < 32; i++)
+		GTIA_PutByte((UWORD) i, 0);
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+	return TRUE;
+}
+
+#ifdef NEW_CYCLE_EXACT
+
+/* generate updated PxPL and MxPL for part of a scanline */
+/* slow, but should be called rarely */
+static void generate_partial_pmpl_colls(int l, int r)
+{
+	int i;
+	if (r < 0 || l >= (int) sizeof(GTIA_pm_scanline) / (int) sizeof(GTIA_pm_scanline[0]))
+		return;
+	if (r >= (int) sizeof(GTIA_pm_scanline) / (int) sizeof(GTIA_pm_scanline[0])) {
+		r = (int) sizeof(GTIA_pm_scanline) / (int) sizeof(GTIA_pm_scanline[0]);
+	}
+	if (l < 0)
+		l = 0;
+
+	for (i = l; i <= r; i++) {
+		UBYTE p = GTIA_pm_scanline[i];
+/* It is possible that some bits are set in PxPL/MxPL here, which would
+ * not otherwise be set ever in GTIA_NewPmScanline.  This is because the
+ * player collisions are always generated in order in GTIA_NewPmScanline.
+ * However this does not cause any problem because we never use those bits
+ * of PxPL/MxPL in the collision reading code.
+ */
+		GTIA_P1PL |= (p & (1 << 1)) ?  p : 0;
+		GTIA_P2PL |= (p & (1 << 2)) ?  p : 0;
+		GTIA_P3PL |= (p & (1 << 3)) ?  p : 0;
+		GTIA_M0PL |= (p & (0x10 << 0)) ?  p : 0;
+		GTIA_M1PL |= (p & (0x10 << 1)) ?  p : 0;
+		GTIA_M2PL |= (p & (0x10 << 2)) ?  p : 0;
+		GTIA_M3PL |= (p & (0x10 << 3)) ?  p : 0;
+	}
+
+}
+
+/* update pm->pl collisions for a partial scanline */
+static void update_partial_pmpl_colls(void)
+{
+	int l = collision_curpos;
+	int r = ANTIC_XPOS * 2 - 37;
+	generate_partial_pmpl_colls(l, r);
+	collision_curpos = r;
+}
+
+/* update pm-> pl collisions at the end of a scanline */
+void GTIA_UpdatePmplColls(void)
+{
+	if (hitclr_pos != 0){
+		generate_partial_pmpl_colls(hitclr_pos,
+				sizeof(GTIA_pm_scanline) / sizeof(GTIA_pm_scanline[0]) - 1);
+/* If hitclr was written to, then only part of GTIA_pm_scanline should be used
+ * for collisions */
+
+	}
+	else {
+/* otherwise the whole of pm_scaline can be used for collisions.  This will
+ * update the collision registers based on the generated collisions for the
+ * current line */
+		GTIA_P1PL |= P1PL_T;
+		GTIA_P2PL |= P2PL_T;
+		GTIA_P3PL |= P3PL_T;
+		GTIA_M0PL |= M0PL_T;
+		GTIA_M1PL |= M1PL_T;
+		GTIA_M2PL |= M2PL_T;
+		GTIA_M3PL |= M3PL_T;
+	}
+	collision_curpos = 0;
+	hitclr_pos = 0;
+}
+
+#else
+#define update_partial_pmpl_colls()
+#endif /* NEW_CYCLE_EXACT */
+
+/* Prepare PMG scanline ---------------------------------------------------- */
+
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+
+void GTIA_NewPmScanline(void)
+{
+#ifdef NEW_CYCLE_EXACT
+/* reset temporary pm->pl collisions */
+	P1PL_T = P2PL_T = P3PL_T = 0;
+	M0PL_T = M1PL_T = M2PL_T = M3PL_T = 0;
+#endif /* NEW_CYCLE_EXACT */
+/* Clear if necessary */
+	if (GTIA_pm_dirty) {
+		memset(GTIA_pm_scanline, 0, ATARI_WIDTH / 2);
+		GTIA_pm_dirty = FALSE;
+	}
+
+/* Draw Players */
+
+#define DO_PLAYER(n)	if (GTIA_GRAFP##n) {						\
+	ULONG grafp = grafp_ptr[n][GTIA_GRAFP##n] & hposp_mask[n];	\
+	if (grafp) {											\
+		UBYTE *ptr = hposp_ptr[n];							\
+		GTIA_pm_dirty = TRUE;									\
+		do {												\
+			if (grafp & 1)									\
+				P##n##PL_T |= *ptr |= 1 << n;					\
+			ptr++;											\
+			grafp >>= 1;									\
+		} while (grafp);									\
+	}														\
+}
+
+	/* optimized DO_PLAYER(0): GTIA_pm_scanline is clear and P0PL is unused */
+	if (GTIA_GRAFP0) {
+		ULONG grafp = grafp_ptr[0][GTIA_GRAFP0] & hposp_mask[0];
+		if (grafp) {
+			UBYTE *ptr = hposp_ptr[0];
+			GTIA_pm_dirty = TRUE;
+			do {
+				if (grafp & 1)
+					*ptr = 1;
+				ptr++;
+				grafp >>= 1;
+			} while (grafp);
+		}
+	}
+
+	DO_PLAYER(1)
+	DO_PLAYER(2)
+	DO_PLAYER(3)
+
+/* Draw Missiles */
+
+#define DO_MISSILE(n,p,m,r,l)	if (GTIA_GRAFM & m) {	\
+	int j = global_sizem[n];						\
+	UBYTE *ptr = hposm_ptr[n];						\
+	if (GTIA_GRAFM & r) {								\
+		if (GTIA_GRAFM & l)								\
+			j <<= 1;								\
+	}												\
+	else											\
+		ptr += j;									\
+	if (ptr < GTIA_pm_scanline + 2) {					\
+		j += ptr - GTIA_pm_scanline - 2;					\
+		ptr = GTIA_pm_scanline + 2;						\
+	}												\
+	else if (ptr + j > GTIA_pm_scanline + ATARI_WIDTH / 2 - 2)	\
+		j = GTIA_pm_scanline + ATARI_WIDTH / 2 - 2 - ptr;		\
+	if (j > 0)										\
+		do											\
+			M##n##PL_T |= *ptr++ |= p;				\
+		while (--j);								\
+}
+
+	if (GTIA_GRAFM) {
+		GTIA_pm_dirty = TRUE;
+		DO_MISSILE(3, 0x80, 0xc0, 0x80, 0x40)
+		DO_MISSILE(2, 0x40, 0x30, 0x20, 0x10)
+		DO_MISSILE(1, 0x20, 0x0c, 0x08, 0x04)
+		DO_MISSILE(0, 0x10, 0x03, 0x02, 0x01)
+	}
+}
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+/* GTIA registers ---------------------------------------------------------- */
+
+void GTIA_Frame(void)
+{
+#ifdef BASIC
+	consol = 0xf;
+#else
+	consol = INPUT_key_consol | 0x08;
+#endif
+
+	if (GTIA_GRACTL & 4) {
+		GTIA_TRIG_latch[0] &= GTIA_TRIG[0];
+		GTIA_TRIG_latch[1] &= GTIA_TRIG[1];
+		GTIA_TRIG_latch[2] &= GTIA_TRIG[2];
+		GTIA_TRIG_latch[3] &= GTIA_TRIG[3];
+	}
+}
+
+UBYTE GTIA_GetByte(UWORD addr, int no_side_effects)
+{
+	switch (addr & 0x1f) {
+	case GTIA_OFFSET_M0PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x10) >> 4)
+		      + ((PF1PM & 0x10) >> 3)
+		      + ((PF2PM & 0x10) >> 2)
+		      + ((PF3PM & 0x10) >> 1)) & GTIA_collisions_mask_missile_playfield;
+	case GTIA_OFFSET_M1PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x20) >> 5)
+		      + ((PF1PM & 0x20) >> 4)
+		      + ((PF2PM & 0x20) >> 3)
+		      + ((PF3PM & 0x20) >> 2)) & GTIA_collisions_mask_missile_playfield;
+	case GTIA_OFFSET_M2PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x40) >> 6)
+		      + ((PF1PM & 0x40) >> 5)
+		      + ((PF2PM & 0x40) >> 4)
+		      + ((PF3PM & 0x40) >> 3)) & GTIA_collisions_mask_missile_playfield;
+	case GTIA_OFFSET_M3PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x80) >> 7)
+		      + ((PF1PM & 0x80) >> 6)
+		      + ((PF2PM & 0x80) >> 5)
+		      + ((PF3PM & 0x80) >> 4)) & GTIA_collisions_mask_missile_playfield;
+	case GTIA_OFFSET_P0PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return ((PF0PM & 0x01)
+		      + ((PF1PM & 0x01) << 1)
+		      + ((PF2PM & 0x01) << 2)
+		      + ((PF3PM & 0x01) << 3)) & GTIA_collisions_mask_player_playfield;
+	case GTIA_OFFSET_P1PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x02) >> 1)
+		      + (PF1PM & 0x02)
+		      + ((PF2PM & 0x02) << 1)
+		      + ((PF3PM & 0x02) << 2)) & GTIA_collisions_mask_player_playfield;
+	case GTIA_OFFSET_P2PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x04) >> 2)
+		      + ((PF1PM & 0x04) >> 1)
+		      + (PF2PM & 0x04)
+		      + ((PF3PM & 0x04) << 1)) & GTIA_collisions_mask_player_playfield;
+	case GTIA_OFFSET_P3PF:
+#ifdef NEW_CYCLE_EXACT
+	if (ANTIC_DRAWING_SCREEN) {
+			ANTIC_UpdateScanline();
+	}
+#endif
+		return (((PF0PM & 0x08) >> 3)
+		      + ((PF1PM & 0x08) >> 2)
+		      + ((PF2PM & 0x08) >> 1)
+		      + (PF3PM & 0x08)) & GTIA_collisions_mask_player_playfield;
+	case GTIA_OFFSET_M0PL:
+		update_partial_pmpl_colls();
+		return GTIA_M0PL & GTIA_collisions_mask_missile_player;
+	case GTIA_OFFSET_M1PL:
+		update_partial_pmpl_colls();
+		return GTIA_M1PL & GTIA_collisions_mask_missile_player;
+	case GTIA_OFFSET_M2PL:
+		update_partial_pmpl_colls();
+		return GTIA_M2PL & GTIA_collisions_mask_missile_player;
+	case GTIA_OFFSET_M3PL:
+		update_partial_pmpl_colls();
+		return GTIA_M3PL & GTIA_collisions_mask_missile_player;
+	case GTIA_OFFSET_P0PL:
+		update_partial_pmpl_colls();
+		return (((GTIA_P1PL & 0x01) << 1)  /* mask in player 1 */
+		      + ((GTIA_P2PL & 0x01) << 2)  /* mask in player 2 */
+		      + ((GTIA_P3PL & 0x01) << 3)) /* mask in player 3 */
+		     & GTIA_collisions_mask_player_player;
+	case GTIA_OFFSET_P1PL:
+		update_partial_pmpl_colls();
+		return ((GTIA_P1PL & 0x01)         /* mask in player 0 */
+		      + ((GTIA_P2PL & 0x02) << 1)  /* mask in player 2 */
+		      + ((GTIA_P3PL & 0x02) << 2)) /* mask in player 3 */
+		     & GTIA_collisions_mask_player_player;
+	case GTIA_OFFSET_P2PL:
+		update_partial_pmpl_colls();
+		return ((GTIA_P2PL & 0x03)         /* mask in player 0 and 1 */
+		      + ((GTIA_P3PL & 0x04) << 1)) /* mask in player 3 */
+		     & GTIA_collisions_mask_player_player;
+	case GTIA_OFFSET_P3PL:
+		update_partial_pmpl_colls();
+		return (GTIA_P3PL & 0x07)          /* mask in player 0,1, and 2 */
+		     & GTIA_collisions_mask_player_player;
+	case GTIA_OFFSET_TRIG0:
+		return GTIA_TRIG[0] & GTIA_TRIG_latch[0];
+	case GTIA_OFFSET_TRIG1:
+		return GTIA_TRIG[1] & GTIA_TRIG_latch[1];
+	case GTIA_OFFSET_TRIG2:
+		return GTIA_TRIG[2] & GTIA_TRIG_latch[2];
+	case GTIA_OFFSET_TRIG3:
+		return GTIA_TRIG[3] & GTIA_TRIG_latch[3];
+	case GTIA_OFFSET_PAL:
+		return (tv_mode == TV_PAL) ? 0x01 : 0x0f;
+  case GTIA_OFFSET_CONSOL:
+		{
+      UBYTE byte = consol & consol_mask;
+#if SKIP  
+			if (!no_side_effects && GTIA_consol_override > 0) {
+				/* Check if we're called from outside OS. This avoids sending
+				   console keystrokes to diagnostic cartridges. */
+				if (CPU_regPC < 0xc000)
+					/* Not from OS. Disable console override. */
+					GTIA_consol_override = 0;
+				else {
+				--GTIA_consol_override;
+					if (Atari800_builtin_basic && Atari800_disable_basic && !BINLOAD_loading_basic)
+						/* Only for XL/XE - hold Option during reboot. */
+						byte &= ~INPUT_CONSOL_OPTION;
+					if (CASSETTE_hold_start && Atari800_machine_type != Atari800_MACHINE_5200) {
+						/* Only for the computers - hold Start during reboot. */
+						byte &= ~INPUT_CONSOL_START;
+						if (GTIA_consol_override == 0) {
+							/* press Space after Start to start cassette boot. */
+							CASSETTE_press_space = 1;
+							CASSETTE_hold_start = CASSETTE_hold_start_on_reboot;
+						}
+					}
+				}
+			}
+#endif   
+			return byte;
+		}
+	default:
+		break;
+	}
+
+	return 0xf;
+}
+
+void GTIA_PutByte(UWORD addr, UBYTE byte)
+{
+#if !defined(BASIC) && !defined(CURSES_BASIC)
+	UWORD cword;
+	UWORD cword2;
+
+#ifdef NEW_CYCLE_EXACT
+	int x; /* the cycle-exact update position in GTIA_pm_scanline */
+	if (ANTIC_DRAWING_SCREEN) {
+		if ((addr & 0x1f) != GTIA_PRIOR) {
+			ANTIC_UpdateScanline();
+		} else {
+			ANTIC_UpdateScanlinePrior(byte);
+		}
+	}
+#define UPDATE_PM_CYCLE_EXACT if(ANTIC_DRAWING_SCREEN) GTIA_NewPmScanline();
+#else
+#define UPDATE_PM_CYCLE_EXACT
+#endif
+
+#endif /* !defined(BASIC) && !defined(CURSES_BASIC) */
+
+	switch (addr & 0x1f) {
+	case GTIA_OFFSET_CONSOL:
+		GTIA_speaker = !(byte & 0x08);
+#ifdef CONSOLE_SOUND
+		POKEYSND_UpdateConsol(1);
+#endif
+		consol_mask = (~byte) & 0x0f; 
+		break;
+
+#if defined(BASIC) || defined(CURSES_BASIC)
+
+	/* We use these for Antic modes 6, 7 on Curses */
+	case GTIA_OFFSET_COLPF0:
+		GTIA_COLPF0 = byte;
+		break;
+	case GTIA_OFFSET_COLPF1:
+		GTIA_COLPF1 = byte;
+		break;
+	case GTIA_OFFSET_COLPF2:
+		GTIA_COLPF2 = byte;
+		break;
+	case GTIA_OFFSET_COLPF3:
+		GTIA_COLPF3 = byte;
+		break;
+
+#else
+
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+	case GTIA_OFFSET_COLBK:
+		GTIA_COLBK = byte &= 0xfe;
+		ANTIC_cl[C_BAK] = cword = colour_translation_table[byte];
+		if (cword != (UWORD) (ANTIC_lookup_gtia9[0]) ) {
+			ANTIC_lookup_gtia9[0] = cword + (cword << 16);
+			if (GTIA_PRIOR & 0x40)
+				setup_gtia9_11();
+		}
+		break;
+	case GTIA_OFFSET_COLPF0:
+		GTIA_COLPF0 = byte &= 0xfe;
+		ANTIC_cl[C_PF0] = cword = GTIA_colour_translation_table[byte];
+		if ((GTIA_PRIOR & 1) == 0) {
+			ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PF0 | C_PM2] = cword;
+			if ((GTIA_PRIOR & 3) == 0) {
+				if (GTIA_PRIOR & 0xf) {
+					ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF0 | C_PM0] = cword;
+					if ((GTIA_PRIOR & 0xf) == 0xc)
+						ANTIC_cl[C_PF0 | C_PM0123] = ANTIC_cl[C_PF0 | C_PM123] = ANTIC_cl[C_PF0 | C_PM023] = cword;
+				}
+				else {
+					ANTIC_cl[C_PF0 | C_PM0] = colour_translation_table[byte | GTIA_COLPM0];
+					ANTIC_cl[C_PF0 | C_PM1] = colour_translation_table[byte | GTIA_COLPM1];
+					ANTIC_cl[C_PF0 | C_PM01] = colour_translation_table[byte | GTIA_COLPM0 | GTIA_COLPM1];
+				}
+			}
+			if ((GTIA_PRIOR & 0xf) >= 0xa)
+				ANTIC_cl[C_PF0 | C_PM25] = cword;
+		}
+		break;
+	case GTIA_OFFSET_COLPF1:
+		GTIA_COLPF1 = byte &= 0xfe;
+		ANTIC_cl[C_PF1] = cword = GTIA_colour_translation_table[byte];
+		if ((GTIA_PRIOR & 1) == 0) {
+			ANTIC_cl[C_PF1 | C_PM23] = ANTIC_cl[C_PF1 | C_PM3] = ANTIC_cl[C_PF1 | C_PM2] = cword;
+			if ((GTIA_PRIOR & 3) == 0) {
+				if (GTIA_PRIOR & 0xf) {
+					ANTIC_cl[C_PF1 | C_PM01] = ANTIC_cl[C_PF1 | C_PM1] = ANTIC_cl[C_PF1 | C_PM0] = cword;
+					if ((GTIA_PRIOR & 0xf) == 0xc)
+						ANTIC_cl[C_PF1 | C_PM0123] = ANTIC_cl[C_PF1 | C_PM123] = ANTIC_cl[C_PF1 | C_PM023] = cword;
+				}
+				else {
+					ANTIC_cl[C_PF1 | C_PM0] = colour_translation_table[byte | GTIA_COLPM0];
+					ANTIC_cl[C_PF1 | C_PM1] = colour_translation_table[byte | GTIA_COLPM1];
+					ANTIC_cl[C_PF1 | C_PM01] = colour_translation_table[byte | GTIA_COLPM0 | GTIA_COLPM1];
+				}
+			}
+		}
+		{
+			UBYTE byte2 = (GTIA_COLPF2 & 0xf0) + (byte & 0xf);
+			ANTIC_cl[C_HI2] = cword = colour_translation_table[byte2];
+			ANTIC_cl[C_HI3] = colour_translation_table[(GTIA_COLPF3 & 0xf0) | (byte & 0xf)];
+			if (GTIA_PRIOR & 4)
+				ANTIC_cl[C_HI2 | C_PM01] = ANTIC_cl[C_HI2 | C_PM1] = ANTIC_cl[C_HI2 | C_PM0] = cword;
+			if ((GTIA_PRIOR & 9) == 0) {
+				if (GTIA_PRIOR & 0xf)
+					ANTIC_cl[C_HI2 | C_PM23] = ANTIC_cl[C_HI2 | C_PM3] = ANTIC_cl[C_HI2 | C_PM2] = cword;
+				else {
+					ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[byte2 | (GTIA_COLPM2 & 0xf0)];
+					ANTIC_cl[C_HI2 | C_PM3] = colour_translation_table[byte2 | (GTIA_COLPM3 & 0xf0)];
+					ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[byte2 | ((GTIA_COLPM2 | GTIA_COLPM3) & 0xf0)];
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPF2:
+		GTIA_COLPF2 = byte &= 0xfe;
+		ANTIC_cl[C_PF2] = cword = GTIA_colour_translation_table[byte];
+		{
+			UBYTE byte2 = (byte & 0xf0) + (GTIA_COLPF1 & 0xf);
+			ANTIC_cl[C_HI2] = cword2 = colour_translation_table[byte2];
+			if (GTIA_PRIOR & 4) {
+				ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF2 | C_PM0] = cword;
+				ANTIC_cl[C_HI2 | C_PM01] = ANTIC_cl[C_HI2 | C_PM1] = ANTIC_cl[C_HI2 | C_PM0] = cword2;
+			}
+			if ((GTIA_PRIOR & 9) == 0) {
+				if (GTIA_PRIOR & 0xf) {
+					ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF2 | C_PM2] = cword;
+					ANTIC_cl[C_HI2 | C_PM23] = ANTIC_cl[C_HI2 | C_PM3] = ANTIC_cl[C_HI2 | C_PM2] = cword2;
+				}
+				else {
+					ANTIC_cl[C_PF2 | C_PM2] = colour_translation_table[byte | GTIA_COLPM2];
+					ANTIC_cl[C_PF2 | C_PM3] = colour_translation_table[byte | GTIA_COLPM3];
+					ANTIC_cl[C_PF2 | C_PM23] = colour_translation_table[byte | GTIA_COLPM2 | GTIA_COLPM3];
+					ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[byte2 | (GTIA_COLPM2 & 0xf0)];
+					ANTIC_cl[C_HI2 | C_PM3] = colour_translation_table[byte2 | (GTIA_COLPM3 & 0xf0)];
+					ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[byte2 | ((GTIA_COLPM2 | GTIA_COLPM3) & 0xf0)];
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPF3:
+		GTIA_COLPF3 = byte &= 0xfe;
+		ANTIC_cl[C_PF3] = cword = colour_translation_table[byte];
+		ANTIC_cl[C_HI3] = cword2 = colour_translation_table[(byte & 0xf0) | (GTIA_COLPF1 & 0xf)];
+		if (GTIA_PRIOR & 4)
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF3 | C_PM0] = cword;
+		if ((GTIA_PRIOR & 9) == 0) {
+			if (GTIA_PRIOR & 0xf)
+				ANTIC_cl[C_PF3 | C_PM23] = ANTIC_cl[C_PF3 | C_PM3] = ANTIC_cl[C_PF3 | C_PM2] = cword;
+			else {
+				ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = ANTIC_cl[C_PF3 | C_PM2] = colour_translation_table[byte | GTIA_COLPM2];
+				ANTIC_cl[C_PF3 | C_PM35] = ANTIC_cl[C_PF2 | C_PM35] = ANTIC_cl[C_PM35] = ANTIC_cl[C_PF3 | C_PM3] = colour_translation_table[byte | GTIA_COLPM3];
+				ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = colour_translation_table[byte | GTIA_COLPM2 | GTIA_COLPM3];
+				ANTIC_cl[C_PF0 | C_PM235] = ANTIC_cl[C_PF0 | C_PM35] = ANTIC_cl[C_PF0 | C_PM25] =
+				ANTIC_cl[C_PF1 | C_PM235] = ANTIC_cl[C_PF1 | C_PM35] = ANTIC_cl[C_PF1 | C_PM25] = cword;
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM0:
+		GTIA_COLPM0 = byte &= 0xfe;
+		ANTIC_cl[C_PM023] = ANTIC_cl[C_PM0] = cword = colour_translation_table[byte];
+		{
+			UBYTE byte2 = byte | GTIA_COLPM1;
+			ANTIC_cl[C_PM0123] = ANTIC_cl[C_PM01] = cword2 = colour_translation_table[byte2];
+			if ((GTIA_PRIOR & 4) == 0) {
+				ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PF3 | C_PM0] = cword;
+				ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF3 | C_PM01] = cword2;
+				ANTIC_cl[C_HI2 | C_PM0] = colour_translation_table[(byte & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				ANTIC_cl[C_HI2 | C_PM01] = colour_translation_table[(byte2 & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				if ((GTIA_PRIOR & 0xc) == 0) {
+					if (GTIA_PRIOR & 3) {
+						ANTIC_cl[C_PF0 | C_PM0] = ANTIC_cl[C_PF1 | C_PM0] = cword;
+						ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF1 | C_PM01] = cword2;
+					}
+					else {
+						ANTIC_cl[C_PF0 | C_PM0] = colour_translation_table[byte | GTIA_COLPF0];
+						ANTIC_cl[C_PF1 | C_PM0] = colour_translation_table[byte | GTIA_COLPF1];
+						ANTIC_cl[C_PF0 | C_PM01] = colour_translation_table[byte2 | GTIA_COLPF0];
+						ANTIC_cl[C_PF1 | C_PM01] = colour_translation_table[byte2 | GTIA_COLPF1];
+					}
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM1:
+		GTIA_COLPM1 = byte &= 0xfe;
+		ANTIC_cl[C_PM123] = ANTIC_cl[C_PM1] = cword = colour_translation_table[byte];
+		{
+			UBYTE byte2 = byte | GTIA_COLPM0;
+			ANTIC_cl[C_PM0123] = ANTIC_cl[C_PM01] = cword2 = colour_translation_table[byte2];
+			if ((GTIA_PRIOR & 4) == 0) {
+				ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF3 | C_PM1] = cword;
+				ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF3 | C_PM01] = cword2;
+				ANTIC_cl[C_HI2 | C_PM1] = colour_translation_table[(byte & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				ANTIC_cl[C_HI2 | C_PM01] = colour_translation_table[(byte2 & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				if ((GTIA_PRIOR & 0xc) == 0) {
+					if (GTIA_PRIOR & 3) {
+						ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF1 | C_PM1] = cword;
+						ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF1 | C_PM01] = cword2;
+					}
+					else {
+						ANTIC_cl[C_PF0 | C_PM1] = colour_translation_table[byte | GTIA_COLPF0];
+						ANTIC_cl[C_PF1 | C_PM1] = colour_translation_table[byte | GTIA_COLPF1];
+						ANTIC_cl[C_PF0 | C_PM01] = colour_translation_table[byte2 | GTIA_COLPF0];
+						ANTIC_cl[C_PF1 | C_PM01] = colour_translation_table[byte2 | GTIA_COLPF1];
+					}
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM2:
+		GTIA_COLPM2 = byte &= 0xfe;
+		ANTIC_cl[C_PM2] = cword = colour_translation_table[byte];
+		{
+			UBYTE byte2 = byte | GTIA_COLPM3;
+			ANTIC_cl[C_PM23] = cword2 = colour_translation_table[byte2];
+			if (GTIA_PRIOR & 1) {
+				ANTIC_cl[C_PF0 | C_PM2] = ANTIC_cl[C_PF1 | C_PM2] = cword;
+				ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF1 | C_PM23] = cword2;
+			}
+			if ((GTIA_PRIOR & 6) == 0) {
+				if (GTIA_PRIOR & 9) {
+					ANTIC_cl[C_PF2 | C_PM2] = ANTIC_cl[C_PF3 | C_PM2] = cword;
+					ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF3 | C_PM23] = cword2;
+					ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[(byte & 0xf0) | (GTIA_COLPF1 & 0xf)];
+					ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[(byte2 & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				}
+				else {
+					ANTIC_cl[C_PF2 | C_PM2] = colour_translation_table[byte | GTIA_COLPF2];
+					ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = ANTIC_cl[C_PF3 | C_PM2] = colour_translation_table[byte | GTIA_COLPF3];
+					ANTIC_cl[C_PF2 | C_PM23] = colour_translation_table[byte2 | GTIA_COLPF2];
+					ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = colour_translation_table[byte2 | GTIA_COLPF3];
+					ANTIC_cl[C_HI2 | C_PM2] = colour_translation_table[((byte | GTIA_COLPF2) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+					ANTIC_cl[C_HI2 | C_PM25] = colour_translation_table[((byte | GTIA_COLPF3) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+					ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[((byte2 | GTIA_COLPF2) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+					ANTIC_cl[C_HI2 | C_PM235] = colour_translation_table[((byte2 | GTIA_COLPF3) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM3:
+		GTIA_COLPM3 = byte &= 0xfe;
+		ANTIC_cl[C_PM3] = cword = colour_translation_table[byte];
+		{
+			UBYTE byte2 = byte | GTIA_COLPM2;
+			ANTIC_cl[C_PM23] = cword2 = colour_translation_table[byte2];
+			if (GTIA_PRIOR & 1) {
+				ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PF1 | C_PM3] = cword;
+				ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF1 | C_PM23] = cword2;
+			}
+			if ((GTIA_PRIOR & 6) == 0) {
+				if (GTIA_PRIOR & 9) {
+					ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF3 | C_PM3] = cword;
+					ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF3 | C_PM23] = cword2;
+				}
+				else {
+					ANTIC_cl[C_PF2 | C_PM3] = colour_translation_table[byte | GTIA_COLPF2];
+					ANTIC_cl[C_PF3 | C_PM35] = ANTIC_cl[C_PF2 | C_PM35] = ANTIC_cl[C_PM35] = ANTIC_cl[C_PF3 | C_PM3] = colour_translation_table[byte | GTIA_COLPF3];
+					ANTIC_cl[C_PF2 | C_PM23] = colour_translation_table[byte2 | GTIA_COLPF2];
+					ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = colour_translation_table[byte2 | GTIA_COLPF3];
+					ANTIC_cl[C_HI2 | C_PM3] = colour_translation_table[((byte | GTIA_COLPF2) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+					ANTIC_cl[C_HI2 | C_PM23] = colour_translation_table[((byte2 | GTIA_COLPF2) & 0xf0) | (GTIA_COLPF1 & 0xf)];
+				}
+			}
+		}
+		break;
+#else /* USE_COLOUR_TRANSLATION_TABLE */
+	case GTIA_OFFSET_COLBK:
+		GTIA_COLBK = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_BAK] = cword;
+		if (cword != (UWORD) (ANTIC_lookup_gtia9[0]) ) {
+			ANTIC_lookup_gtia9[0] = cword + (cword << 16);
+			if (GTIA_PRIOR & 0x40)
+				setup_gtia9_11();
+		}
+		break;
+	case GTIA_OFFSET_COLPF0:
+		GTIA_COLPF0 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PF0] = cword;
+		if ((GTIA_PRIOR & 1) == 0) {
+			ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PF0 | C_PM2] = cword;
+			if ((GTIA_PRIOR & 3) == 0) {
+				if (GTIA_PRIOR & 0xf) {
+					ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF0 | C_PM0] = cword;
+					if ((GTIA_PRIOR & 0xf) == 0xc)
+						ANTIC_cl[C_PF0 | C_PM0123] = ANTIC_cl[C_PF0 | C_PM123] = ANTIC_cl[C_PF0 | C_PM023] = cword;
+				}
+				else
+					ANTIC_cl[C_PF0 | C_PM01] = (ANTIC_cl[C_PF0 | C_PM0] = cword | ANTIC_cl[C_PM0]) | (ANTIC_cl[C_PF0 | C_PM1] = cword | ANTIC_cl[C_PM1]);
+			}
+			if ((GTIA_PRIOR & 0xf) >= 0xa)
+				ANTIC_cl[C_PF0 | C_PM25] = cword;
+		}
+		break;
+	case GTIA_OFFSET_COLPF1:
+		GTIA_COLPF1 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PF1] = cword;
+		if ((GTIA_PRIOR & 1) == 0) {
+			ANTIC_cl[C_PF1 | C_PM23] = ANTIC_cl[C_PF1 | C_PM3] = ANTIC_cl[C_PF1 | C_PM2] = cword;
+			if ((GTIA_PRIOR & 3) == 0) {
+				if (GTIA_PRIOR & 0xf) {
+					ANTIC_cl[C_PF1 | C_PM01] = ANTIC_cl[C_PF1 | C_PM1] = ANTIC_cl[C_PF1 | C_PM0] = cword;
+					if ((GTIA_PRIOR & 0xf) == 0xc)
+						ANTIC_cl[C_PF1 | C_PM0123] = ANTIC_cl[C_PF1 | C_PM123] = ANTIC_cl[C_PF1 | C_PM023] = cword;
+				}
+				else
+					ANTIC_cl[C_PF1 | C_PM01] = (ANTIC_cl[C_PF1 | C_PM0] = cword | ANTIC_cl[C_PM0]) | (ANTIC_cl[C_PF1 | C_PM1] = cword | ANTIC_cl[C_PM1]);
+			}
+		}
+		((UBYTE *)ANTIC_hires_lookup_l)[0x80] = ((UBYTE *)ANTIC_hires_lookup_l)[0x41] = (UBYTE)
+			(ANTIC_hires_lookup_l[0x60] = cword & 0xf0f);
+		break;
+	case GTIA_OFFSET_COLPF2:
+		GTIA_COLPF2 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PF2] = cword;
+		if (GTIA_PRIOR & 4)
+			ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF2 | C_PM0] = cword;
+		if ((GTIA_PRIOR & 9) == 0) {
+			if (GTIA_PRIOR & 0xf)
+				ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF2 | C_PM2] = cword;
+			else
+				ANTIC_cl[C_PF2 | C_PM23] = (ANTIC_cl[C_PF2 | C_PM2] = cword | ANTIC_cl[C_PM2]) | (ANTIC_cl[C_PF2 | C_PM3] = cword | ANTIC_cl[C_PM3]);
+		}
+		break;
+	case GTIA_OFFSET_COLPF3:
+		GTIA_COLPF3 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PF3] = cword;
+		if (GTIA_PRIOR & 4)
+			ANTIC_cl[C_PF3 | C_PM01] = ANTIC_cl[C_PF3 | C_PM1] = ANTIC_cl[C_PF3 | C_PM0] = cword;
+		if ((GTIA_PRIOR & 9) == 0) {
+			if (GTIA_PRIOR & 0xf)
+				ANTIC_cl[C_PF3 | C_PM23] = ANTIC_cl[C_PF3 | C_PM3] = ANTIC_cl[C_PF3 | C_PM2] = cword;
+			else {
+				ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = ANTIC_cl[C_PF3 | C_PM2] = cword | ANTIC_cl[C_PM2];
+				ANTIC_cl[C_PF3 | C_PM35] = ANTIC_cl[C_PF2 | C_PM35] = ANTIC_cl[C_PM35] = ANTIC_cl[C_PF3 | C_PM3] = cword | ANTIC_cl[C_PM3];
+				ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = ANTIC_cl[C_PF3 | C_PM2] | ANTIC_cl[C_PF3 | C_PM3];
+				ANTIC_cl[C_PF0 | C_PM235] = ANTIC_cl[C_PF0 | C_PM35] = ANTIC_cl[C_PF0 | C_PM25] =
+				ANTIC_cl[C_PF1 | C_PM235] = ANTIC_cl[C_PF1 | C_PM35] = ANTIC_cl[C_PF1 | C_PM25] = cword;
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM0:
+		GTIA_COLPM0 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PM023] = ANTIC_cl[C_PM0] = cword;
+		ANTIC_cl[C_PM0123] = ANTIC_cl[C_PM01] = cword2 = cword | ANTIC_cl[C_PM1];
+		if ((GTIA_PRIOR & 4) == 0) {
+			ANTIC_cl[C_PF2 | C_PM0] = ANTIC_cl[C_PF3 | C_PM0] = cword;
+			ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF3 | C_PM01] = cword2;
+			if ((GTIA_PRIOR & 0xc) == 0) {
+				if (GTIA_PRIOR & 3) {
+					ANTIC_cl[C_PF0 | C_PM0] = ANTIC_cl[C_PF1 | C_PM0] = cword;
+					ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF1 | C_PM01] = cword2;
+				}
+				else {
+					ANTIC_cl[C_PF0 | C_PM0] = cword | ANTIC_cl[C_PF0];
+					ANTIC_cl[C_PF1 | C_PM0] = cword | ANTIC_cl[C_PF1];
+					ANTIC_cl[C_PF0 | C_PM01] = cword2 | ANTIC_cl[C_PF0];
+					ANTIC_cl[C_PF1 | C_PM01] = cword2 | ANTIC_cl[C_PF1];
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM1:
+		GTIA_COLPM1 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PM123] = ANTIC_cl[C_PM1] = cword;
+		ANTIC_cl[C_PM0123] = ANTIC_cl[C_PM01] = cword2 = cword | ANTIC_cl[C_PM0];
+		if ((GTIA_PRIOR & 4) == 0) {
+			ANTIC_cl[C_PF2 | C_PM1] = ANTIC_cl[C_PF3 | C_PM1] = cword;
+			ANTIC_cl[C_PF2 | C_PM01] = ANTIC_cl[C_PF3 | C_PM01] = cword2;
+			if ((GTIA_PRIOR & 0xc) == 0) {
+				if (GTIA_PRIOR & 3) {
+					ANTIC_cl[C_PF0 | C_PM1] = ANTIC_cl[C_PF1 | C_PM1] = cword;
+					ANTIC_cl[C_PF0 | C_PM01] = ANTIC_cl[C_PF1 | C_PM01] = cword2;
+				}
+				else {
+					ANTIC_cl[C_PF0 | C_PM1] = cword | ANTIC_cl[C_PF0];
+					ANTIC_cl[C_PF1 | C_PM1] = cword | ANTIC_cl[C_PF1];
+					ANTIC_cl[C_PF0 | C_PM01] = cword2 | ANTIC_cl[C_PF0];
+					ANTIC_cl[C_PF1 | C_PM01] = cword2 | ANTIC_cl[C_PF1];
+				}
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM2:
+		GTIA_COLPM2 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PM2] = cword;
+		ANTIC_cl[C_PM23] = cword2 = cword | ANTIC_cl[C_PM3];
+		if (GTIA_PRIOR & 1) {
+			ANTIC_cl[C_PF0 | C_PM2] = ANTIC_cl[C_PF1 | C_PM2] = cword;
+			ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF1 | C_PM23] = cword2;
+		}
+		if ((GTIA_PRIOR & 6) == 0) {
+			if (GTIA_PRIOR & 9) {
+				ANTIC_cl[C_PF2 | C_PM2] = ANTIC_cl[C_PF3 | C_PM2] = cword;
+				ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF3 | C_PM23] = cword2;
+			}
+			else {
+				ANTIC_cl[C_PF2 | C_PM2] = cword | ANTIC_cl[C_PF2];
+				ANTIC_cl[C_PF3 | C_PM25] = ANTIC_cl[C_PF2 | C_PM25] = ANTIC_cl[C_PM25] = ANTIC_cl[C_PF3 | C_PM2] = cword | ANTIC_cl[C_PF3];
+				ANTIC_cl[C_PF2 | C_PM23] = cword2 | ANTIC_cl[C_PF2];
+				ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = cword2 | ANTIC_cl[C_PF3];
+			}
+		}
+		break;
+	case GTIA_OFFSET_COLPM3:
+		GTIA_COLPM3 = byte &= 0xfe;
+		GTIA_COLOUR_TO_WORD(cword,byte);
+		ANTIC_cl[C_PM3] = cword;
+		ANTIC_cl[C_PM23] = cword2 = cword | ANTIC_cl[C_PM2];
+		if (GTIA_PRIOR & 1) {
+			ANTIC_cl[C_PF0 | C_PM3] = ANTIC_cl[C_PF1 | C_PM3] = cword;
+			ANTIC_cl[C_PF0 | C_PM23] = ANTIC_cl[C_PF1 | C_PM23] = cword2;
+		}
+		if ((GTIA_PRIOR & 6) == 0) {
+			if (GTIA_PRIOR & 9) {
+				ANTIC_cl[C_PF2 | C_PM3] = ANTIC_cl[C_PF3 | C_PM3] = cword;
+				ANTIC_cl[C_PF2 | C_PM23] = ANTIC_cl[C_PF3 | C_PM23] = cword2;
+			}
+			else {
+				ANTIC_cl[C_PF2 | C_PM3] = cword | ANTIC_cl[C_PF2];
+				ANTIC_cl[C_PF3 | C_PM35] = ANTIC_cl[C_PF2 | C_PM35] = ANTIC_cl[C_PM35] = ANTIC_cl[C_PF3 | C_PM3] = cword | ANTIC_cl[C_PF3];
+				ANTIC_cl[C_PF2 | C_PM23] = cword2 | ANTIC_cl[C_PF2];
+				ANTIC_cl[C_PF3 | C_PM235] = ANTIC_cl[C_PF2 | C_PM235] = ANTIC_cl[C_PM235] = ANTIC_cl[C_PF3 | C_PM23] = cword2 | ANTIC_cl[C_PF3];
+			}
+		}
+		break;
+#endif /* USE_COLOUR_TRANSLATION_TABLE */
+	case GTIA_OFFSET_GRAFM:
+		GTIA_GRAFM = byte;
+		UPDATE_PM_CYCLE_EXACT
+		break;
+
+#ifdef NEW_CYCLE_EXACT
+#define CYCLE_EXACT_GRAFP(n) x = ANTIC_XPOS * 2 - 3;\
+	if (GTIA_HPOSP##n >= x) {\
+	/* hpos right of x */\
+		/* redraw */  \
+		UPDATE_PM_CYCLE_EXACT\
+	}
+#else
+#define CYCLE_EXACT_GRAFP(n)
+#endif /* NEW_CYCLE_EXACT */
+
+#define DO_GRAFP(n) case GTIA_OFFSET_GRAFP##n:\
+	GTIA_GRAFP##n = byte;\
+	CYCLE_EXACT_GRAFP(n);\
+	break;
+
+	DO_GRAFP(0)
+	DO_GRAFP(1)
+	DO_GRAFP(2)
+	DO_GRAFP(3)
+
+	case GTIA_OFFSET_HITCLR:
+		GTIA_M0PL = GTIA_M1PL = GTIA_M2PL = GTIA_M3PL = 0;
+		GTIA_P0PL = GTIA_P1PL = GTIA_P2PL = GTIA_P3PL = 0;
+		PF0PM = PF1PM = PF2PM = PF3PM = 0;
+#ifdef NEW_CYCLE_EXACT
+		hitclr_pos = ANTIC_XPOS * 2 - 37;
+		collision_curpos = hitclr_pos;
+#endif
+		break;
+/* TODO: cycle-exact missile HPOS, GRAF, SIZE */
+/* this is only an approximation */
+	case GTIA_OFFSET_HPOSM0:
+		GTIA_HPOSM0 = byte;
+		hposm_ptr[0] = GTIA_pm_scanline + byte - 0x20;
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_HPOSM1:
+		GTIA_HPOSM1 = byte;
+		hposm_ptr[1] = GTIA_pm_scanline + byte - 0x20;
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_HPOSM2:
+		GTIA_HPOSM2 = byte;
+		hposm_ptr[2] = GTIA_pm_scanline + byte - 0x20;
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_HPOSM3:
+		GTIA_HPOSM3 = byte;
+		hposm_ptr[3] = GTIA_pm_scanline + byte - 0x20;
+		UPDATE_PM_CYCLE_EXACT
+		break;
+
+#ifdef NEW_CYCLE_EXACT
+#define CYCLE_EXACT_HPOSP(n) x = ANTIC_XPOS * 2 - 1;\
+	if (GTIA_HPOSP##n < x && byte < x) {\
+	/* case 1: both left of x */\
+		/* do nothing */\
+	}\
+	else if (GTIA_HPOSP##n >= x && byte >= x ) {\
+	/* case 2: both right of x */\
+		/* redraw, clearing first */\
+		UPDATE_PM_CYCLE_EXACT\
+	}\
+	else if (GTIA_HPOSP##n <x && byte >= x) {\
+	/* case 3: new value is right, old value is left */\
+		/* redraw without clearing first */\
+		/* note: a hack, we can get away with it unless another change occurs */\
+		/* before the original copy that wasn't erased due to changing */\
+		/* GTIA_pm_dirty is drawn */\
+		GTIA_pm_dirty = FALSE;\
+		UPDATE_PM_CYCLE_EXACT\
+		GTIA_pm_dirty = TRUE; /* can't trust that it was reset correctly */\
+	}\
+	else {\
+	/* case 4: new value is left, old value is right */\
+		/* remove old player and don't draw the new one */\
+		UBYTE save_graf = GTIA_GRAFP##n;\
+		GTIA_GRAFP##n = 0;\
+		UPDATE_PM_CYCLE_EXACT\
+		GTIA_GRAFP##n = save_graf;\
+	}
+#else
+#define CYCLE_EXACT_HPOSP(n)
+#endif /* NEW_CYCLE_EXACT */
+#define DO_HPOSP(n)	case GTIA_OFFSET_HPOSP##n:								\
+	hposp_ptr[n] = GTIA_pm_scanline + byte - 0x20;					\
+	if (byte >= 0x22) {											\
+		if (byte > 0xbe) {										\
+			if (byte >= 0xde)									\
+				hposp_mask[n] = 0;								\
+			else												\
+				hposp_mask[n] = 0xffffffff >> (byte - 0xbe);	\
+		}														\
+		else													\
+			hposp_mask[n] = 0xffffffff;							\
+	}															\
+	else if (byte > 2)											\
+		hposp_mask[n] = 0xffffffff << (0x22 - byte);			\
+	else														\
+		hposp_mask[n] = 0;										\
+	CYCLE_EXACT_HPOSP(n)\
+	GTIA_HPOSP##n = byte;											\
+	break;
+
+	DO_HPOSP(0)
+	DO_HPOSP(1)
+	DO_HPOSP(2)
+	DO_HPOSP(3)
+
+/* TODO: cycle-exact size changes */
+/* this is only an approximation */
+	case GTIA_OFFSET_SIZEM:
+		GTIA_SIZEM = byte;
+		global_sizem[0] = PM_Width[byte & 0x03];
+		global_sizem[1] = PM_Width[(byte & 0x0c) >> 2];
+		global_sizem[2] = PM_Width[(byte & 0x30) >> 4];
+		global_sizem[3] = PM_Width[(byte & 0xc0) >> 6];
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_SIZEP0:
+		GTIA_SIZEP0 = byte;
+		grafp_ptr[0] = grafp_lookup[byte & 3];
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_SIZEP1:
+		GTIA_SIZEP1 = byte;
+		grafp_ptr[1] = grafp_lookup[byte & 3];
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_SIZEP2:
+		GTIA_SIZEP2 = byte;
+		grafp_ptr[2] = grafp_lookup[byte & 3];
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_SIZEP3:
+		GTIA_SIZEP3 = byte;
+		grafp_ptr[3] = grafp_lookup[byte & 3];
+		UPDATE_PM_CYCLE_EXACT
+		break;
+	case GTIA_OFFSET_PRIOR:
+		ANTIC_SetPrior(byte);
+		GTIA_PRIOR = byte;
+		if (byte & 0x40)
+			setup_gtia9_11();
+		break;
+	case GTIA_OFFSET_VDELAY:
+		GTIA_VDELAY = byte;
+		break;
+	case GTIA_OFFSET_GRACTL:
+		GTIA_GRACTL = byte;
+		ANTIC_missile_gra_enabled = (byte & 0x01);
+		ANTIC_player_gra_enabled = (byte & 0x02);
+		ANTIC_player_flickering = ((ANTIC_player_dma_enabled | ANTIC_player_gra_enabled) == 0x02);
+		ANTIC_missile_flickering = ((ANTIC_missile_dma_enabled | ANTIC_missile_gra_enabled) == 0x01);
+		if ((byte & 4) == 0)
+			GTIA_TRIG_latch[0] = GTIA_TRIG_latch[1] = GTIA_TRIG_latch[2] = GTIA_TRIG_latch[3] = 1;
+		break;
+
+#endif /* defined(BASIC) || defined(CURSES_BASIC) */
+	}
+}
+
+/* State ------------------------------------------------------------------- */
+
+#ifndef BASIC
+
+void GTIA_StateSave(void)
+{
+	int next_console_value = 7;
+
+	StateSav_SaveUBYTE(&GTIA_HPOSP0, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSP1, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSP2, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSP3, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSM0, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSM1, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSM2, 1);
+	StateSav_SaveUBYTE(&GTIA_HPOSM3, 1);
+	StateSav_SaveUBYTE(&PF0PM, 1);
+	StateSav_SaveUBYTE(&PF1PM, 1);
+	StateSav_SaveUBYTE(&PF2PM, 1);
+	StateSav_SaveUBYTE(&PF3PM, 1);
+	StateSav_SaveUBYTE(&GTIA_M0PL, 1);
+	StateSav_SaveUBYTE(&GTIA_M1PL, 1);
+	StateSav_SaveUBYTE(&GTIA_M2PL, 1);
+	StateSav_SaveUBYTE(&GTIA_M3PL, 1);
+	StateSav_SaveUBYTE(&GTIA_P0PL, 1);
+	StateSav_SaveUBYTE(&GTIA_P1PL, 1);
+	StateSav_SaveUBYTE(&GTIA_P2PL, 1);
+	StateSav_SaveUBYTE(&GTIA_P3PL, 1);
+	StateSav_SaveUBYTE(&GTIA_SIZEP0, 1);
+	StateSav_SaveUBYTE(&GTIA_SIZEP1, 1);
+	StateSav_SaveUBYTE(&GTIA_SIZEP2, 1);
+	StateSav_SaveUBYTE(&GTIA_SIZEP3, 1);
+	StateSav_SaveUBYTE(&GTIA_SIZEM, 1);
+	StateSav_SaveUBYTE(&GTIA_GRAFP0, 1);
+	StateSav_SaveUBYTE(&GTIA_GRAFP1, 1);
+	StateSav_SaveUBYTE(&GTIA_GRAFP2, 1);
+	StateSav_SaveUBYTE(&GTIA_GRAFP3, 1);
+	StateSav_SaveUBYTE(&GTIA_GRAFM, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPM0, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPM1, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPM2, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPM3, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPF0, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPF1, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPF2, 1);
+	StateSav_SaveUBYTE(&GTIA_COLPF3, 1);
+	StateSav_SaveUBYTE(&GTIA_COLBK, 1);
+	StateSav_SaveUBYTE(&GTIA_PRIOR, 1);
+	StateSav_SaveUBYTE(&GTIA_VDELAY, 1);
+	StateSav_SaveUBYTE(&GTIA_GRACTL, 1);
+
+	StateSav_SaveUBYTE(&consol_mask, 1);
+	StateSav_SaveINT(&GTIA_speaker, 1);
+	StateSav_SaveINT(&next_console_value, 1);
+	StateSav_SaveUBYTE(GTIA_TRIG_latch, 4);
+}
+
+void GTIA_StateRead(UBYTE version)
+{
+	int next_console_value;	/* ignored */
+
+	StateSav_ReadUBYTE(&GTIA_HPOSP0, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSP1, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSP2, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSP3, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSM0, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSM1, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSM2, 1);
+	StateSav_ReadUBYTE(&GTIA_HPOSM3, 1);
+	StateSav_ReadUBYTE(&PF0PM, 1);
+	StateSav_ReadUBYTE(&PF1PM, 1);
+	StateSav_ReadUBYTE(&PF2PM, 1);
+	StateSav_ReadUBYTE(&PF3PM, 1);
+	StateSav_ReadUBYTE(&GTIA_M0PL, 1);
+	StateSav_ReadUBYTE(&GTIA_M1PL, 1);
+	StateSav_ReadUBYTE(&GTIA_M2PL, 1);
+	StateSav_ReadUBYTE(&GTIA_M3PL, 1);
+	StateSav_ReadUBYTE(&GTIA_P0PL, 1);
+	StateSav_ReadUBYTE(&GTIA_P1PL, 1);
+	StateSav_ReadUBYTE(&GTIA_P2PL, 1);
+	StateSav_ReadUBYTE(&GTIA_P3PL, 1);
+	StateSav_ReadUBYTE(&GTIA_SIZEP0, 1);
+	StateSav_ReadUBYTE(&GTIA_SIZEP1, 1);
+	StateSav_ReadUBYTE(&GTIA_SIZEP2, 1);
+	StateSav_ReadUBYTE(&GTIA_SIZEP3, 1);
+	StateSav_ReadUBYTE(&GTIA_SIZEM, 1);
+	StateSav_ReadUBYTE(&GTIA_GRAFP0, 1);
+	StateSav_ReadUBYTE(&GTIA_GRAFP1, 1);
+	StateSav_ReadUBYTE(&GTIA_GRAFP2, 1);
+	StateSav_ReadUBYTE(&GTIA_GRAFP3, 1);
+	StateSav_ReadUBYTE(&GTIA_GRAFM, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPM0, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPM1, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPM2, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPM3, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPF0, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPF1, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPF2, 1);
+	StateSav_ReadUBYTE(&GTIA_COLPF3, 1);
+	StateSav_ReadUBYTE(&GTIA_COLBK, 1);
+	StateSav_ReadUBYTE(&GTIA_PRIOR, 1);
+	StateSav_ReadUBYTE(&GTIA_VDELAY, 1);
+	StateSav_ReadUBYTE(&GTIA_GRACTL, 1);
+
+	StateSav_ReadUBYTE(&consol_mask, 1);
+	StateSav_ReadINT(&GTIA_speaker, 1);
+	StateSav_ReadINT(&next_console_value, 1);
+	if (version >= 7)
+		StateSav_ReadUBYTE(GTIA_TRIG_latch, 4);
+
+	GTIA_PutByte(GTIA_OFFSET_HPOSP0, GTIA_HPOSP0);
+	GTIA_PutByte(GTIA_OFFSET_HPOSP1, GTIA_HPOSP1);
+	GTIA_PutByte(GTIA_OFFSET_HPOSP2, GTIA_HPOSP2);
+	GTIA_PutByte(GTIA_OFFSET_HPOSP3, GTIA_HPOSP3);
+	GTIA_PutByte(GTIA_OFFSET_HPOSM0, GTIA_HPOSM0);
+	GTIA_PutByte(GTIA_OFFSET_HPOSM1, GTIA_HPOSM1);
+	GTIA_PutByte(GTIA_OFFSET_HPOSM2, GTIA_HPOSM2);
+	GTIA_PutByte(GTIA_OFFSET_HPOSM3, GTIA_HPOSM3);
+	GTIA_PutByte(GTIA_OFFSET_SIZEP0, GTIA_SIZEP0);
+	GTIA_PutByte(GTIA_OFFSET_SIZEP1, GTIA_SIZEP1);
+	GTIA_PutByte(GTIA_OFFSET_SIZEP2, GTIA_SIZEP2);
+	GTIA_PutByte(GTIA_OFFSET_SIZEP3, GTIA_SIZEP3);
+	GTIA_PutByte(GTIA_OFFSET_SIZEM, GTIA_SIZEM);
+	GTIA_PutByte(GTIA_OFFSET_GRAFP0, GTIA_GRAFP0);
+	GTIA_PutByte(GTIA_OFFSET_GRAFP1, GTIA_GRAFP1);
+	GTIA_PutByte(GTIA_OFFSET_GRAFP2, GTIA_GRAFP2);
+	GTIA_PutByte(GTIA_OFFSET_GRAFP3, GTIA_GRAFP3);
+	GTIA_PutByte(GTIA_OFFSET_GRAFM, GTIA_GRAFM);
+	GTIA_PutByte(GTIA_OFFSET_COLPM0, GTIA_COLPM0);
+	GTIA_PutByte(GTIA_OFFSET_COLPM1, GTIA_COLPM1);
+	GTIA_PutByte(GTIA_OFFSET_COLPM2, GTIA_COLPM2);
+	GTIA_PutByte(GTIA_OFFSET_COLPM3, GTIA_COLPM3);
+	GTIA_PutByte(GTIA_OFFSET_COLPF0, GTIA_COLPF0);
+	GTIA_PutByte(GTIA_OFFSET_COLPF1, GTIA_COLPF1);
+	GTIA_PutByte(GTIA_OFFSET_COLPF2, GTIA_COLPF2);
+	GTIA_PutByte(GTIA_OFFSET_COLPF3, GTIA_COLPF3);
+	GTIA_PutByte(GTIA_OFFSET_COLBK, GTIA_COLBK);
+	GTIA_PutByte(GTIA_OFFSET_PRIOR, GTIA_PRIOR);
+	GTIA_PutByte(GTIA_OFFSET_GRACTL, GTIA_GRACTL);
+}
+
+#endif /* BASIC */
diff --git a/MCUME_pico2/pico800/gtia.h b/MCUME_pico2/pico800/gtia.h
new file mode 100644
index 0000000..865c4ae
--- /dev/null
+++ b/MCUME_pico2/pico800/gtia.h
@@ -0,0 +1,136 @@
+#ifndef GTIA_H_
+#define GTIA_H_
+
+
+#define GTIA_OFFSET_HPOSP0 0x00
+#define GTIA_OFFSET_M0PF 0x00
+#define GTIA_OFFSET_HPOSP1 0x01
+#define GTIA_OFFSET_M1PF 0x01
+#define GTIA_OFFSET_HPOSP2 0x02
+#define GTIA_OFFSET_M2PF 0x02
+#define GTIA_OFFSET_HPOSP3 0x03
+#define GTIA_OFFSET_M3PF 0x03
+#define GTIA_OFFSET_HPOSM0 0x04
+#define GTIA_OFFSET_P0PF 0x04
+#define GTIA_OFFSET_HPOSM1 0x05
+#define GTIA_OFFSET_P1PF 0x05
+#define GTIA_OFFSET_HPOSM2 0x06
+#define GTIA_OFFSET_P2PF 0x06
+#define GTIA_OFFSET_HPOSM3 0x07
+#define GTIA_OFFSET_P3PF 0x07
+#define GTIA_OFFSET_SIZEP0 0x08
+#define GTIA_OFFSET_M0PL 0x08
+#define GTIA_OFFSET_SIZEP1 0x09
+#define GTIA_OFFSET_M1PL 0x09
+#define GTIA_OFFSET_SIZEP2 0x0a
+#define GTIA_OFFSET_M2PL 0x0a
+#define GTIA_OFFSET_SIZEP3 0x0b
+#define GTIA_OFFSET_M3PL 0x0b
+#define GTIA_OFFSET_SIZEM 0x0c
+#define GTIA_OFFSET_P0PL 0x0c
+#define GTIA_OFFSET_GRAFP0 0x0d
+#define GTIA_OFFSET_P1PL 0x0d
+#define GTIA_OFFSET_GRAFP1 0x0e
+#define GTIA_OFFSET_P2PL 0x0e
+#define GTIA_OFFSET_GRAFP2 0x0f
+#define GTIA_OFFSET_P3PL 0x0f
+#define GTIA_OFFSET_GRAFP3 0x10
+#define GTIA_OFFSET_TRIG0 0x10
+#define GTIA_OFFSET_GRAFM 0x11
+#define GTIA_OFFSET_TRIG1 0x11
+#define GTIA_OFFSET_COLPM0 0x12
+#define GTIA_OFFSET_TRIG2 0x12
+#define GTIA_OFFSET_COLPM1 0x13
+#define GTIA_OFFSET_TRIG3 0x13
+#define GTIA_OFFSET_COLPM2 0x14
+#define GTIA_OFFSET_PAL 0x14
+#define GTIA_OFFSET_COLPM3 0x15
+#define GTIA_OFFSET_COLPF0 0x16
+#define GTIA_OFFSET_COLPF1 0x17
+#define GTIA_OFFSET_COLPF2 0x18
+#define GTIA_OFFSET_COLPF3 0x19
+#define GTIA_OFFSET_COLBK 0x1a
+#define GTIA_OFFSET_PRIOR 0x1b
+#define GTIA_OFFSET_VDELAY 0x1c
+#define GTIA_OFFSET_GRACTL 0x1d
+#define GTIA_OFFSET_HITCLR 0x1e
+#define GTIA_OFFSET_CONSOL 0x1f
+
+extern UBYTE GTIA_GRAFM;
+extern UBYTE GTIA_GRAFP0;
+extern UBYTE GTIA_GRAFP1;
+extern UBYTE GTIA_GRAFP2;
+extern UBYTE GTIA_GRAFP3;
+extern UBYTE GTIA_HPOSP0;
+extern UBYTE GTIA_HPOSP1;
+extern UBYTE GTIA_HPOSP2;
+extern UBYTE GTIA_HPOSP3;
+extern UBYTE GTIA_HPOSM0;
+extern UBYTE GTIA_HPOSM1;
+extern UBYTE GTIA_HPOSM2;
+extern UBYTE GTIA_HPOSM3;
+extern UBYTE GTIA_SIZEP0;
+extern UBYTE GTIA_SIZEP1;
+extern UBYTE GTIA_SIZEP2;
+extern UBYTE GTIA_SIZEP3;
+extern UBYTE GTIA_SIZEM;
+extern UBYTE GTIA_COLPM0;
+extern UBYTE GTIA_COLPM1;
+extern UBYTE GTIA_COLPM2;
+extern UBYTE GTIA_COLPM3;
+extern UBYTE GTIA_COLPF0;
+extern UBYTE GTIA_COLPF1;
+extern UBYTE GTIA_COLPF2;
+extern UBYTE GTIA_COLPF3;
+extern UBYTE GTIA_COLBK;
+extern UBYTE GTIA_GRACTL;
+extern UBYTE GTIA_M0PL;
+extern UBYTE GTIA_M1PL;
+extern UBYTE GTIA_M2PL;
+extern UBYTE GTIA_M3PL;
+extern UBYTE GTIA_P0PL;
+extern UBYTE GTIA_P1PL;
+extern UBYTE GTIA_P2PL;
+extern UBYTE GTIA_P3PL;
+extern UBYTE GTIA_PRIOR;
+extern UBYTE GTIA_VDELAY;
+
+#ifdef USE_COLOUR_TRANSLATION_TABLE
+
+extern UWORD GTIA_colour_translation_table[256];
+#define GTIA_COLOUR_BLACK GTIA_colour_translation_table[0]
+#define GTIA_COLOUR_TO_WORD(dest,src) dest = GTIA_colour_translation_table[src];
+
+#else
+
+#define GTIA_COLOUR_BLACK 0
+#define GTIA_COLOUR_TO_WORD(dest,src) dest = (((UWORD) (src)) << 8) | (src);
+
+#endif /* USE_COLOUR_TRANSLATION_TABLE */
+
+extern UBYTE GTIA_pm_scanline[ATARI_WIDTH / 2 + 8];	/* there's a byte for every *pair* of pixels */
+extern int GTIA_pm_dirty;
+
+extern UBYTE GTIA_collisions_mask_missile_playfield;
+extern UBYTE GTIA_collisions_mask_player_playfield;
+extern UBYTE GTIA_collisions_mask_missile_player;
+extern UBYTE GTIA_collisions_mask_player_player;
+
+extern UBYTE GTIA_TRIG[4];
+extern UBYTE GTIA_TRIG_latch[4];
+
+extern int GTIA_consol_override;
+extern int GTIA_speaker;
+
+int GTIA_Initialise(void);
+void GTIA_Frame(void);
+void GTIA_NewPmScanline(void);
+UBYTE GTIA_GetByte(UWORD addr, int no_side_effects);
+void GTIA_PutByte(UWORD addr, UBYTE byte);
+void GTIA_StateSave(void);
+void GTIA_StateRead(UBYTE version);
+
+#ifdef NEW_CYCLE_EXACT
+void GTIA_UpdatePmplColls(void);
+#endif
+#endif /* GTIA_H_ */
diff --git a/MCUME_pico2/pico800/keyboard_osd.h b/MCUME_pico2/pico800/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/pico800/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/pico800/memory.h b/MCUME_pico2/pico800/memory.h
new file mode 100644
index 0000000..1945156
--- /dev/null
+++ b/MCUME_pico2/pico800/memory.h
@@ -0,0 +1,18 @@
+#ifndef __MEMORY__
+#define __MEMORY__
+
+extern unsigned char * memory;
+
+#define  MEMORY_GetByte(addr)   (Atari_GetByte(addr))
+#define  MEMORY_PutByte(addr,byte)  Atari_PutByte(addr,byte)
+
+#define  MEMORY_dGetByte(addr)   (Atari_GetByte(addr))
+#define  MEMORY_dPutByte(addr,byte)  Atari_PutByte(addr,byte)
+#define MEMORY_dGetWord(x)       (Atari_GetByte(x) | (Atari_GetByte((x) + 1) << 8))
+#define MEMORY_dPutWord(x,y)     (Atari_PutByte(x,(UBYTE) (y)) , Atari_PutByte(x + 1,(UBYTE) ((y) >> 8)) 
+/* faster versions of dGetWord and dPutWord for even addresses */
+/* TODO: guarantee that memory is UWORD-aligned and use UWORD access */
+#define MEMORY_dGetWordAligned(x)    MEMORY_dGetWord(x)
+#define MEMORY_dPutWordAligned(x,y)  MEMORY_dPutWord(x,y)
+
+#endif
diff --git a/MCUME_pico2/pico800/noise.h b/MCUME_pico2/pico800/noise.h
new file mode 100644
index 0000000..c93ac89
--- /dev/null
+++ b/MCUME_pico2/pico800/noise.h
@@ -0,0 +1,1059 @@
+const UBYTE POKEY_poly9_lookup[] = {
+255,127,63,31,15,135,195,225,240,120,188,222,239,119,59,29,
+14,135,67,161,208,104,52,154,205,102,179,217,108,182,219,237,
+246,123,189,94,47,23,11,133,194,225,112,56,156,206,103,51,
+25,12,134,67,33,144,72,36,18,137,68,162,81,168,212,234,
+117,186,93,174,215,235,245,122,61,158,79,39,147,73,164,210,
+233,116,58,157,206,231,115,57,28,14,7,3,129,192,224,112,
+184,220,238,119,187,93,46,151,203,229,242,121,188,94,175,87,
+43,149,74,165,82,41,20,10,5,2,129,64,160,80,168,84,
+170,85,170,213,234,245,250,125,190,95,175,215,107,181,90,45,
+22,11,5,130,193,96,176,216,236,118,187,221,110,183,219,109,
+182,91,173,214,107,53,26,13,6,131,65,160,208,232,116,186,
+221,238,247,251,125,62,31,143,199,227,241,120,60,158,207,103,
+179,89,44,150,203,101,178,89,172,214,235,117,58,29,142,199,
+99,177,88,44,22,139,69,162,209,232,244,250,253,254,127,191,
+95,47,151,75,165,210,105,52,26,141,70,163,81,40,148,202,
+101,50,25,140,198,99,49,24,12,6,3,1,128,192,96,48,
+152,204,102,51,153,76,166,83,169,212,106,53,154,77,38,147,
+201,228,242,249,252,126,191,223,111,183,91,45,150,75,37,146,
+73,36,146,201,100,178,217,236,246,251,253,126,63,159,79,167,
+211,105,180,90,173,86,43,21,10,133,66,161,80,40,20,138,
+69,34,145,200,228,114,185,220,110,55,155,77,166,211,233,244,
+122,189,222,111,55,27,13,134,195,97,176,88,172,86,171,85,
+42,149,202,229,114,57,156,78,39,19,9,132,194,97,48,24,
+140,70,35,17,8,132,66,33,16,8,4,2,1,0,128,64,
+32,16,136,68,34,17,136,196,98,49,152,76,38,19,137,196,
+226,113,184,92,174,87,171,213,106,181,218,109,54,27,141,198,
+227,113,56,28,142,71,35,145,72,164,82,169,84,42,21,138,
+197,98,177,216,108,54,155,205,230,243,249,124,62,159,207,231,
+243,121,60,30,143,71,163,209,104,180,218,237,118,59,157,78,
+167,83,41,148,74,37,18,9,4,130,65,32,144,200,100,50,
+153,204,230,115,185,92,46,23,139,197,226,241,248,124,190,223,
+239,247,123,61,30,15,7,131,193,224,240,248,252,254,255,};
+const UBYTE POKEY_poly17_lookup[] = {
+255,1,224,3,254,231,131,241,31,28,254,217,99,142,33,4,
+1,24,130,17,28,226,25,90,146,145,61,250,216,123,12,48,
+24,227,1,216,131,141,223,227,130,233,157,13,226,59,122,212,
+179,149,60,226,90,106,16,210,1,185,147,73,190,119,7,152,
+142,217,133,238,227,227,249,89,108,118,190,11,199,103,242,233,
+123,109,32,220,130,149,93,242,158,11,132,87,112,170,71,46,
+107,238,48,210,66,137,17,10,130,52,76,170,60,158,154,149,
+108,226,255,58,80,118,197,187,54,28,174,217,198,222,97,160,
+197,26,39,68,12,76,216,28,125,232,125,14,28,220,249,37,
+172,137,194,59,57,228,49,214,0,161,17,88,162,149,30,194,
+28,72,184,20,59,152,245,105,116,149,191,211,68,234,45,10,
+249,132,189,209,96,174,39,38,45,158,184,181,42,192,87,252,
+106,87,163,155,252,254,22,146,12,237,201,68,223,125,99,204,
+0,148,65,49,151,17,55,82,77,113,142,5,68,75,60,82,
+91,17,163,19,124,230,159,50,22,6,77,220,94,85,232,47,
+46,189,142,145,5,122,171,67,108,67,238,98,242,227,219,121,
+42,84,22,205,253,70,148,201,177,143,152,151,72,166,245,22,
+132,108,192,223,124,114,222,3,129,23,122,142,19,36,102,42,
+106,246,178,195,94,107,8,80,16,165,113,80,228,229,150,165,
+116,1,254,226,211,251,26,88,180,245,51,212,36,229,27,116,
+118,143,27,166,86,38,200,206,124,81,238,71,162,171,254,189,
+34,80,71,213,218,7,200,143,108,215,175,83,101,242,236,43,
+103,37,152,200,185,13,168,155,234,158,59,132,52,64,106,36,
+146,106,141,3,34,39,54,44,175,170,244,31,22,94,205,105,
+6,181,92,161,172,136,211,41,58,241,103,157,25,163,2,108,
+197,142,102,117,155,93,239,78,48,153,243,11,88,151,197,119,
+247,152,97,40,69,2,174,228,22,167,92,132,252,192,246,237,
+50,245,54,133,62,226,94,42,24,214,81,177,182,9,246,115,
+211,208,171,28,157,232,179,239,156,17,32,34,98,102,162,234,
+238,59,99,68,128,140,200,145,141,250,179,202,204,89,5,230,
+106,98,243,242,201,122,63,2,93,212,255,85,160,174,170,247,
+47,16,93,241,175,29,133,106,162,243,126,8,122,176,243,91,
+88,50,149,55,83,92,99,141,16,18,0,37,80,72,37,196,
+8,4,81,24,39,65,92,70,221,88,55,196,45,84,25,61,
+227,73,88,23,197,127,118,152,107,137,65,10,39,100,12,14,
+248,156,63,192,124,76,62,124,191,15,133,79,242,187,91,204,
+114,180,162,67,127,115,201,113,142,4,84,73,61,70,25,24,
+179,1,125,211,205,123,39,128,76,200,29,76,250,60,59,202,
+213,200,38,253,159,5,102,107,122,112,243,215,153,50,26,198,
+85,208,174,77,135,239,246,177,242,72,106,53,130,73,156,87,
+65,186,38,31,191,207,133,195,51,187,212,61,116,56,111,131,
+232,142,63,229,44,4,27,184,183,11,212,87,213,250,7,138,
+175,236,149,135,82,39,208,76,109,77,12,94,248,57,111,128,
+216,136,60,217,234,31,43,142,180,84,34,140,134,112,5,182,
+106,199,163,178,109,190,61,167,8,196,81,148,230,65,211,183,
+219,212,250,4,186,169,239,169,65,73,23,230,79,50,187,215,
+13,114,59,83,69,243,190,9,230,115,242,192,235,61,9,232,
+146,254,204,50,181,54,1,126,226,219,122,26,82,21,241,59,
+93,164,255,178,208,110,76,27,44,247,42,65,71,246,234,67,
+235,51,232,228,158,39,68,13,92,218,29,105,170,116,30,14,
+221,204,119,229,184,68,58,45,167,40,196,19,180,102,3,251,
+182,153,246,90,66,144,128,41,153,193,43,63,165,45,144,89,
+185,38,25,223,195,131,187,191,140,180,81,114,134,131,52,79,
+154,58,157,166,83,119,210,201,57,15,128,30,232,188,30,146,
+28,237,232,84,159,92,247,204,33,133,17,18,2,5,84,74,
+13,64,26,36,117,26,77,229,206,36,209,91,31,66,31,112,
+63,23,13,255,234,81,203,22,250,140,59,161,100,8,79,224,
+154,110,220,27,5,102,106,106,114,242,195,219,59,10,212,84,
+229,252,4,182,105,247,165,177,81,120,38,151,62,199,14,98,
+61,18,89,181,231,17,209,50,143,150,118,68,170,44,158,187,
+133,44,195,107,58,113,103,149,152,163,8,205,193,134,239,245,
+129,244,75,86,243,153,121,170,84,30,76,253,76,53,205,185,
+6,24,141,225,2,237,213,132,230,97,211,245,251,84,184,44,
+187,235,205,9,7,99,62,32,127,178,217,255,78,16,153,177,
+43,216,213,237,118,181,186,193,110,111,43,104,212,150,197,116,
+199,158,98,20,131,25,158,210,21,248,170,95,175,74,244,209,
+247,222,0,176,1,123,179,193,125,95,12,123,168,113,74,68,
+208,140,109,193,205,94,119,200,105,12,21,72,171,36,28,139,
+137,142,251,165,168,193,75,63,99,77,16,158,193,37,223,185,
+35,72,197,196,198,229,209,213,254,70,146,169,189,137,224,27,
+127,198,153,16,58,128,119,120,104,119,166,137,214,123,16,240,
+33,255,177,225,120,77,38,254,174,19,103,86,168,41,202,241,
+136,108,217,79,79,107,42,112,86,135,217,150,222,196,240,133,
+190,227,70,169,25,200,178,188,174,146,119,92,40,61,130,89,
+156,118,81,250,7,139,191,238,148,147,16,46,192,94,108,120,
+94,23,201,191,110,148,155,145,46,202,255,104,112,215,151,211,
+22,202,140,88,145,164,107,243,225,249,93,44,126,186,91,207,
+66,178,161,127,185,104,249,71,141,91,162,146,110,204,27,36,
+118,42,75,230,242,226,202,107,41,65,64,134,228,68,135,253,
+214,148,224,32,207,179,162,76,143,109,198,189,80,112,164,167,
+50,101,54,172,175,162,117,31,28,255,201,97,143,53,70,8,
+8,144,16,41,176,80,107,20,144,41,185,193,105,31,37,111,
+184,88,251,4,185,153,233,170,125,143,12,214,121,49,228,33,
+214,33,177,81,121,54,149,63,211,76,107,45,0,88,128,181,
+88,224,180,142,130,53,93,184,63,139,204,222,117,224,236,14,
+55,109,189,12,177,9,249,131,205,223,103,194,233,24,93,224,
+191,62,148,62,193,110,110,59,106,213,130,135,125,215,140,99,
+33,209,80,175,84,20,236,233,70,189,89,225,166,172,135,35,
+55,53,61,185,233,233,77,13,79,234,58,122,214,147,145,62,
+202,222,120,48,246,3,211,55,219,220,123,4,176,8,235,161,
+200,201,13,79,235,42,120,215,135,211,55,218,204,121,5,164,
+74,226,177,218,200,56,29,162,27,254,214,147,144,46,200,223,
+108,114,255,19,193,54,238,142,50,53,54,9,255,226,209,219,
+30,90,156,113,33,244,0,231,113,208,228,237,23,165,126,160,
+250,234,90,123,0,241,16,237,240,212,174,68,23,253,255,5,
+160,11,250,183,139,212,95,84,250,13,43,171,228,28,7,72,
+142,116,84,174,77,134,255,244,176,230,10,99,37,144,72,169,
+5,8,139,160,30,171,140,156,209,32,174,163,102,45,27,232,
+183,174,132,23,113,62,5,47,250,252,59,70,20,200,169,12,
+153,137,171,171,237,141,5,67,59,50,85,55,223,157,99,2,
+225,20,140,232,144,223,216,50,156,166,81,87,214,203,17,139,
+146,62,204,190,116,54,142,143,228,87,183,218,197,232,7,175,
+255,164,176,67,90,35,129,84,74,12,80,24,37,97,88,68,
+245,220,37,228,9,86,115,153,113,43,84,20,237,249,68,188,
+77,163,175,188,149,34,2,103,116,136,111,232,89,78,86,248,
+41,111,161,200,200,29,77,234,62,58,222,151,193,54,239,158,
+48,52,34,75,246,242,195,218,43,8,213,64,167,245,20,164,
+104,194,247,248,96,254,39,131,125,222,28,113,40,101,2,236,
+196,150,229,116,133,190,226,86,171,24,220,240,181,190,128,118,
+105,122,116,179,223,157,98,18,227,21,152,170,153,207,202,51,
+169,244,24,102,80,202,5,200,139,44,223,171,3,109,215,172,
+99,99,241,208,237,124,21,174,203,230,251,115,200,96,156,7,
+65,31,118,95,27,11,135,102,102,171,122,252,50,215,22,195,
+28,74,152,16,57,176,113,123,84,177,189,185,224,120,79,6,
+250,172,59,227,68,136,13,200,155,44,254,187,67,76,67,172,
+66,114,161,243,120,104,118,182,139,215,111,82,249,49,237,176,
+212,42,4,23,120,175,7,36,79,186,58,223,134,211,53,250,
+200,123,45,32,88,194,149,216,162,156,143,192,23,253,254,21,
+162,10,238,245,130,196,77,85,207,95,98,154,98,29,19,11,
+151,102,71,187,58,221,166,215,55,210,76,105,13,4,90,168,
+49,74,192,144,140,232,145,207,218,51,136,228,88,71,196,202,
+36,217,219,15,74,191,96,117,151,157,247,66,192,129,156,203,
+128,155,185,174,152,215,72,34,181,22,1,60,194,91,56,50,
+83,87,211,155,27,142,214,116,224,238,46,51,111,149,136,163,
+41,221,129,167,123,245,160,229,27,117,102,141,26,178,20,47,
+216,220,125,100,188,14,147,45,255,169,97,73,85,198,207,112,
+147,214,79,80,155,21,111,218,120,57,102,17,218,131,137,159,
+235,134,185,149,40,162,115,126,0,251,176,249,250,92,58,28,
+183,73,245,199,149,211,18,138,132,92,193,172,78,179,169,253,
+137,100,91,127,67,201,18,190,196,55,245,60,37,42,232,214,
+190,64,118,229,187,116,60,46,155,238,223,35,130,101,92,13,
+109,202,124,88,126,85,171,31,172,254,178,210,78,72,25,4,
+115,56,97,99,244,128,231,121,81,228,231,182,161,118,41,122,
+240,243,223,24,50,16,103,81,216,39,205,157,70,82,169,49,
+72,224,148,142,192,21,221,250,23,138,142,252,213,166,198,39,
+241,93,61,110,153,74,155,33,47,177,76,169,13,136,155,168,
+190,187,198,28,65,40,6,50,44,167,42,228,23,182,78,135,
+233,150,189,244,48,230,2,226,37,154,233,173,13,129,11,186,
+183,15,148,95,209,170,15,175,239,164,145,83,26,2,21,84,
+107,29,0,59,176,117,59,92,181,237,177,197,56,7,2,46,
+228,30,38,92,142,93,196,254,100,178,239,159,33,38,33,94,
+160,185,218,216,56,60,178,91,223,66,147,177,63,152,252,249,
+102,156,11,129,7,122,175,3,100,71,190,106,215,163,147,125,
+254,28,51,8,229,64,196,197,212,199,212,195,148,203,144,155,
+152,190,216,246,220,34,148,7,81,31,87,79,91,42,19,102,
+71,186,42,223,167,195,117,219,92,123,12,49,8,225,0,204,
+193,132,207,241,131,220,207,68,211,189,123,192,240,140,46,241,
+79,29,75,139,34,62,167,15,180,95,147,138,143,237,199,165,
+211,113,186,68,63,125,173,45,128,89,152,54,89,254,87,131,
+154,174,220,151,196,102,229,155,116,126,14,27,172,247,34,192,
+71,252,75,71,227,186,104,254,55,131,92,206,92,80,188,101,
+35,253,148,181,112,96,230,166,162,103,63,57,237,161,196,9,
+21,67,27,50,23,23,95,223,75,3,163,54,44,174,186,246,
+30,2,28,196,121,20,180,105,243,229,185,85,40,46,178,126,
+143,10,182,117,55,156,173,225,65,221,87,199,218,34,152,199,
+73,19,167,87,52,234,203,106,59,99,69,144,142,201,133,207,
+243,163,216,205,108,87,175,91,228,242,230,138,99,45,17,72,
+163,164,12,131,41,158,177,37,56,201,227,174,41,199,33,146,
+97,61,21,41,187,224,125,31,12,255,232,113,207,20,210,8,
+41,129,64,10,37,68,8,12,208,24,45,224,88,78,84,216,
+45,109,137,76,218,61,105,232,84,158,76,245,205,53,199,24,
+2,16,4,97,24,68,113,156,37,97,89,84,247,221,49,166,
+0,70,97,152,68,121,29,37,107,248,80,255,84,177,188,169,
+226,121,91,68,243,188,41,226,113,218,68,249,29,45,234,248,
+90,94,80,185,53,41,248,208,255,92,48,188,163,67,125,83,
+205,115,166,128,70,105,25,68,115,188,33,99,113,208,229,253,
+21,164,106,226,243,250,72,122,53,163,89,220,118,213,186,7,
+14,239,236,16,215,80,163,148,12,224,25,94,210,153,57,170,
+208,94,76,120,28,55,73,253,70,149,217,179,142,140,213,65,
+182,231,23,177,62,137,238,250,115,202,64,152,5,105,155,100,
+127,63,9,237,194,244,201,118,255,26,81,36,231,58,96,118,
+166,139,246,127,18,216,165,237,145,197,122,39,130,108,204,31,
+100,126,46,27,238,215,162,130,111,253,9,101,67,252,66,215,
+241,179,220,172,116,19,222,199,193,147,191,222,148,240,32,238,
+163,226,109,27,109,231,172,0,83,49,179,81,125,118,157,59,
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+255,};
diff --git a/MCUME_pico2/pico800/pia.c b/MCUME_pico2/pico800/pia.c
new file mode 100644
index 0000000..9dfd9ce
--- /dev/null
+++ b/MCUME_pico2/pico800/pia.c
@@ -0,0 +1,71 @@
+#include <stdio.h>
+
+#include "atari.h"
+#include "cpu.h"
+#include "pia.h"
+
+UBYTE PACTL;
+UBYTE PBCTL;
+UBYTE PORTA;
+UBYTE PORTB;
+
+
+static UBYTE PORTA_mask = 0xff;
+static UBYTE PORTB_mask = 0xff;
+
+void PIA_Initialise(void)
+{
+	PORTA = 0xff;
+	PORTB = 0xff;
+}
+
+UBYTE PIA_GetByte(UWORD addr)
+{
+	UBYTE byte;
+
+	addr &= 0x03;
+	switch (addr) {
+  	case _PACTL:
+  		byte = PACTL;
+  		break;
+  	case _PBCTL:
+  		byte = PBCTL;
+  		break;
+  	case _PORTA:
+  		byte = Atari_PORT(0);
+  		byte &= PORTA_mask;
+  		break;
+  	case _PORTB:
+  		byte = Atari_PORT(1);
+  		byte &= PORTB_mask;
+  		break;
+	}
+
+	return byte;
+}
+
+int PIA_PutByte(UWORD addr, UBYTE byte)
+{
+	addr &= 0xff03;
+
+	switch (addr) {
+  	case _PACTL:
+  		PACTL = byte;
+  		break;
+  	case _PBCTL:
+  		PBCTL = byte;
+  		break;
+  	case _PORTA:
+  		if (!(PACTL & 0x04))
+  			PORTA_mask = ~byte;
+  		break;
+  	case _PORTB:
+  //		if ((byte == 0) && (machine == AtariXL || machine == AtariXE))
+  //			break;				/* special hack for old Atari800 games like is Tapper, for example */
+  		if (!(PBCTL & 0x04))
+  			PORTB_mask = ~byte;
+  		break;
+	}
+
+	return FALSE;
+}
diff --git a/MCUME_pico2/pico800/pia.h b/MCUME_pico2/pico800/pia.h
new file mode 100644
index 0000000..24080a5
--- /dev/null
+++ b/MCUME_pico2/pico800/pia.h
@@ -0,0 +1,22 @@
+#ifndef __PIA__
+#define __PIA__
+
+#include "atari.h"
+
+#define _PORTA 0x00
+#define _PORTB 0x01
+#define _PACTL 0x02
+#define _PBCTL 0x03
+
+extern UBYTE PACTL;
+extern UBYTE PBCTL;
+extern UBYTE PORTA;
+extern UBYTE PORTB;
+
+extern int xe_bank;
+
+void PIA_Initialise(void);
+UBYTE PIA_GetByte(UWORD addr);
+int PIA_PutByte(UWORD addr, UBYTE byte);
+
+#endif
diff --git a/MCUME_pico2/pico800/pico800.cpp b/MCUME_pico2/pico800/pico800.cpp
new file mode 100644
index 0000000..067f9bf
--- /dev/null
+++ b/MCUME_pico2/pico800/pico800.cpp
@@ -0,0 +1,169 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+extern "C" {
+#include "atari800.h"
+}
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);     
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(5, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        //uint16_t bClick = emu_DebounceLocalKeys();
+        //emu_Input(bClick);  
+        emu_Step();        
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    volatile bool vb=vbl; 
+    while (vbl==vb) {};
+#ifdef USE_VGA
+    //tft.waitSync();            
+#else                      
+    //volatile bool vb=vbl;
+    //while (vbl==vb) {};
+#endif
+}
+
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/pico800/pokey.c b/MCUME_pico2/pico800/pokey.c
new file mode 100644
index 0000000..228580c
--- /dev/null
+++ b/MCUME_pico2/pico800/pokey.c
@@ -0,0 +1,699 @@
+/*
+ * pokey.c - POKEY sound chip emulation
+ *
+ * Copyright (C) 1995-1998 David Firth
+ * Copyright (C) 1998-2008 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+
+#include "cpu.h"
+#include "pokey.h"
+#include "gtia.h"
+#include "sio.h"
+#ifdef SOUND
+#include "pokeysnd.h"
+#endif
+#include "antic.h"
+
+#ifdef VOICEBOX
+#include "voicebox.h"
+#include "votraxsnd.h"
+#endif
+
+#ifdef POKEY_UPDATE
+void pokey_update(void);
+#endif
+
+UBYTE POKEY_KBCODE;
+UBYTE POKEY_SERIN;
+UBYTE POKEY_IRQST;
+UBYTE POKEY_IRQEN;
+UBYTE POKEY_SKSTAT;
+UBYTE POKEY_SKCTL;
+int POKEY_DELAYED_SERIN_IRQ;
+int POKEY_DELAYED_SEROUT_IRQ;
+int POKEY_DELAYED_XMTDONE_IRQ;
+
+/* structures to hold the 9 pokey control bytes */
+UBYTE POKEY_AUDF[4 * POKEY_MAXPOKEYS];	/* AUDFx (D200, D202, D204, D206) */
+UBYTE POKEY_AUDC[4 * POKEY_MAXPOKEYS];	/* AUDCx (D201, D203, D205, D207) */
+UBYTE POKEY_AUDCTL[POKEY_MAXPOKEYS];	/* AUDCTL (D208) */
+int POKEY_DivNIRQ[4], POKEY_DivNMax[4];
+int POKEY_Base_mult[POKEY_MAXPOKEYS];		/* selects either 64Khz or 15Khz clock mult */
+
+UBYTE POKEY_POT_input[8] = {228, 228, 228, 228, 228, 228, 228, 228};
+static int pot_scanline;
+
+#include "noise.h"
+//UBYTE POKEY_poly9_lookup[POKEY_POLY9_SIZE];
+//UBYTE POKEY_poly17_lookup[POKEY_POLY17_SIZE];
+
+static ULONG random_scanline_counter;
+
+ULONG POKEY_GetRandomCounter(void)
+{
+	return random_scanline_counter;
+}
+
+void POKEY_SetRandomCounter(ULONG value)
+{
+	random_scanline_counter = value;
+}
+
+UBYTE POKEY_GetByte(UWORD addr, int no_side_effects)
+{
+	UBYTE byte = 0xff;
+
+#ifdef STEREO_SOUND
+	if (addr & 0x0010 && POKEYSND_stereo_enabled)
+		return 0;
+#endif
+	addr &= 0x0f;
+	if (addr < 8) {
+		byte = POKEY_POT_input[addr];
+		if (byte <= pot_scanline)
+			return byte;
+		return pot_scanline;
+	}
+	switch (addr) {
+	case POKEY_OFFSET_ALLPOT:
+		{
+			int i;
+			for (i = 0; i < 8; i++)
+				if (POKEY_POT_input[i] <= pot_scanline)
+					byte &= ~(1 << i);		/* reset bit if pot value known */
+		}
+		break;
+	case POKEY_OFFSET_KBCODE:
+		byte = POKEY_KBCODE;
+		break;
+	case POKEY_OFFSET_RANDOM:
+		if ((POKEY_SKCTL & 0x03) != 0) {
+			int i = random_scanline_counter + ANTIC_XPOS;
+			if (POKEY_AUDCTL[0] & POKEY_POLY9)
+				byte = POKEY_poly9_lookup[i % POKEY_POLY9_SIZE];
+			else {
+				const UBYTE *ptr;
+				i %= POKEY_POLY17_SIZE;
+				ptr = POKEY_poly17_lookup + (i >> 3);
+				i &= 7;
+				byte = (UBYTE) ((ptr[0] >> i) + (ptr[1] << (8 - i)));
+			}
+		}
+		break;
+	case POKEY_OFFSET_SERIN:
+		byte = POKEY_SERIN;
+#ifdef DEBUG3
+		printf("SERIO: SERIN read, bytevalue %02x\n", POKEY_SERIN);
+#endif
+#ifdef SERIO_SOUND
+		POKEYSND_UpdateSerio(0,byte);
+#endif
+		break;
+	case POKEY_OFFSET_IRQST:
+		byte = POKEY_IRQST;
+		break;
+	case POKEY_OFFSET_SKSTAT:
+#if SKIP      
+		byte = POKEY_SKSTAT + (CASSETTE_IOLineStatus() << 4);
+#else
+    byte = POKEY_SKSTAT;
+#endif   
+#ifdef VOICEBOX
+		if (VOICEBOX_enabled) {
+			byte = POKEY_SKSTAT + (VOTRAXSND_busy  << 4);
+		}
+#endif
+		break;
+	}
+
+	return byte;
+}
+
+static void Update_Counter(int chan_mask);
+
+static int POKEY_siocheck(void)
+{
+	return (((POKEY_AUDF[POKEY_CHAN3] == 0x28 || POKEY_AUDF[POKEY_CHAN3] == 0x10
+	        || POKEY_AUDF[POKEY_CHAN3] == 0x08 || POKEY_AUDF[POKEY_CHAN3] == 0x0a)
+		&& POKEY_AUDF[POKEY_CHAN4] == 0x00) /* intelligent peripherals speeds */
+		|| (POKEY_SKCTL & 0x78) == 0x28) /* cassette save mode */
+		&& (POKEY_AUDCTL[0] & 0x28) == 0x28;
+}
+
+#ifndef SOUND_GAIN /* sound gain can be pre-defined in the configure/Makefile */
+#define SOUND_GAIN 4
+#endif
+
+#ifndef SOUND
+#define POKEYSND_Update(addr, val, chip, gain)
+#else
+//#define POKEYSND_Update(addr, val, chip, gain) if (chip == 0) emu_sndPlaySound((chip*4)+addr, gain*16, val*16)
+#endif
+
+void POKEY_PutByte(UWORD addr, UBYTE byte)
+{
+#ifdef STEREO_SOUND
+	addr &= POKEYSND_stereo_enabled ? 0x1f : 0x0f;
+#else
+	addr &= 0x0f;
+#endif
+	switch (addr) {
+	case POKEY_OFFSET_AUDC1:
+		POKEY_AUDC[POKEY_CHAN1] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC1, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC2:
+		POKEY_AUDC[POKEY_CHAN2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC2, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC3:
+		POKEY_AUDC[POKEY_CHAN3] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC3, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC4:
+		POKEY_AUDC[POKEY_CHAN4] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC4, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDCTL:
+		POKEY_AUDCTL[0] = byte;
+
+		/* determine the base multiplier for the 'div by n' calculations */
+		if (byte & POKEY_CLOCK_15)
+			POKEY_Base_mult[0] = POKEY_DIV_15;
+		else
+			POKEY_Base_mult[0] = POKEY_DIV_64;
+
+		Update_Counter((1 << POKEY_CHAN1) | (1 << POKEY_CHAN2) | (1 << POKEY_CHAN3) | (1 << POKEY_CHAN4));
+		POKEYSND_Update(POKEY_OFFSET_AUDCTL, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF1:
+		POKEY_AUDF[POKEY_CHAN1] = byte;
+		Update_Counter((POKEY_AUDCTL[0] & POKEY_CH1_CH2) ? ((1 << POKEY_CHAN2) | (1 << POKEY_CHAN1)) : (1 << POKEY_CHAN1));
+		POKEYSND_Update(POKEY_OFFSET_AUDF1, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF2:
+		POKEY_AUDF[POKEY_CHAN2] = byte;
+		Update_Counter(1 << POKEY_CHAN2);
+		POKEYSND_Update(POKEY_OFFSET_AUDF2, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF3:
+		POKEY_AUDF[POKEY_CHAN3] = byte;
+		Update_Counter((POKEY_AUDCTL[0] & POKEY_CH3_CH4) ? ((1 << POKEY_CHAN4) | (1 << POKEY_CHAN3)) : (1 << POKEY_CHAN3));
+		POKEYSND_Update(POKEY_OFFSET_AUDF3, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF4:
+		POKEY_AUDF[POKEY_CHAN4] = byte;
+		Update_Counter(1 << POKEY_CHAN4);
+		POKEYSND_Update(POKEY_OFFSET_AUDF4, byte, 0, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_IRQEN:
+		POKEY_IRQEN = byte;
+#ifdef DEBUG1
+		printf("WR: IRQEN = %x, PC = %x\n", POKEY_IRQEN, PC);
+#endif
+		POKEY_IRQST |= ~byte & 0xf7;	/* Reset disabled IRQs except XMTDONE */
+#if SKIP
+		if ((~POKEY_IRQST & POKEY_IRQEN) == 0 && PBI_IRQ == 0 && PIA_IRQ == 0)
+#else
+    if ((~POKEY_IRQST & POKEY_IRQEN) == 0)
+#endif
+    {
+      CPU_IRQ = 0;      
+    }
+		else {
+      CPU_GenerateIRQ();      
+		}
+		break;
+	case POKEY_OFFSET_SKRES:
+		POKEY_SKSTAT |= 0xe0;
+		break;
+	case POKEY_OFFSET_POTGO:
+		if (!(POKEY_SKCTL & 4))
+			pot_scanline = 0;	/* slow pot mode */
+		break;
+	case POKEY_OFFSET_SEROUT:
+#ifdef VOICEBOX
+		VOICEBOX_SEROUTPutByte(byte);
+#endif   
+		if ((POKEY_SKCTL & 0x70) == 0x20 && POKEY_siocheck())
+			SIO_PutByte(byte);     
+		/* check if cassette 2-tone mode has been enabled */
+		if ((POKEY_SKCTL & 0x08) == 0x00) {
+			/* intelligent device */    
+			POKEY_DELAYED_SEROUT_IRQ = SIO_SEROUT_INTERVAL;    
+			POKEY_IRQST |= 0x08;    
+			POKEY_DELAYED_XMTDONE_IRQ = SIO_XMTDONE_INTERVAL;    
+		}
+		else {
+			/* cassette */
+			/* some savers patch the cassette baud rate, so we evaluate it here */
+			/* scanlines per second*10 bit*audiofrequency/(1.79 MHz/2) */
+                        POKEY_DELAYED_SEROUT_IRQ = 312*50*10*(POKEY_AUDF[POKEY_CHAN3] + POKEY_AUDF[POKEY_CHAN4]*0x100)/895000;
+			/* safety check */
+			if (POKEY_DELAYED_SEROUT_IRQ >= 3) {
+                        	POKEY_IRQST |= 0x08;
+                        	POKEY_DELAYED_XMTDONE_IRQ = 2*POKEY_DELAYED_SEROUT_IRQ - 2;
+			}
+			else {
+				POKEY_DELAYED_SEROUT_IRQ = 0;
+				POKEY_DELAYED_XMTDONE_IRQ = 0;
+			}
+		};
+#ifdef SERIO_SOUND
+		POKEYSND_UpdateSerio(1, byte);
+#endif
+		break;
+	case POKEY_OFFSET_STIMER:
+		POKEY_DivNIRQ[POKEY_CHAN1] = POKEY_DivNMax[POKEY_CHAN1];
+		POKEY_DivNIRQ[POKEY_CHAN2] = POKEY_DivNMax[POKEY_CHAN2];
+		POKEY_DivNIRQ[POKEY_CHAN4] = POKEY_DivNMax[POKEY_CHAN4];
+		POKEYSND_Update(POKEY_OFFSET_STIMER, byte, 0, SOUND_GAIN);
+#ifdef DEBUG1
+		printf("WR: STIMER = %x\n", byte);
+#endif
+		break;
+	case POKEY_OFFSET_SKCTL:
+#ifdef VOICEBOX
+		VOICEBOX_SKCTLPutByte(byte);
+#endif
+		POKEY_SKCTL = byte;
+		POKEYSND_Update(POKEY_OFFSET_SKCTL, byte, 0, SOUND_GAIN);
+		if (byte & 4)
+			pot_scanline = 228;	/* fast pot mode - return results immediately */
+		if ((byte & 0x03) == 0) {
+			/* POKEY reset. */
+			/* Stop serial IO. */
+			POKEY_DELAYED_SERIN_IRQ = 0;
+			POKEY_DELAYED_SEROUT_IRQ = 0;
+			POKEY_DELAYED_XMTDONE_IRQ = 0;
+#if SKIP
+			CASSETTE_ResetPOKEY();
+#endif      
+			/* TODO other registers should also be reset. */
+		}
+		break;
+#ifdef STEREO_SOUND
+	case POKEY_OFFSET_AUDC1 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDC[POKEY_CHAN1 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC1, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC2 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDC[POKEY_CHAN2 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC2, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC3 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDC[POKEY_CHAN3 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC3, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDC4 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDC[POKEY_CHAN4 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDC4, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDCTL + POKEY_OFFSET_POKEY2:
+		POKEY_AUDCTL[1] = byte;
+		/* determine the base multiplier for the 'div by n' calculations */
+		if (byte & POKEY_CLOCK_15)
+			POKEY_Base_mult[1] = POKEY_DIV_15;
+		else
+			POKEY_Base_mult[1] = POKEY_DIV_64;
+
+		POKEYSND_Update(POKEY_OFFSET_AUDCTL, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF1 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDF[POKEY_CHAN1 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDF1, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF2 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDF[POKEY_CHAN2 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDF2, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF3 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDF[POKEY_CHAN3 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDF3, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_AUDF4 + POKEY_OFFSET_POKEY2:
+		POKEY_AUDF[POKEY_CHAN4 + POKEY_CHIP2] = byte;
+		POKEYSND_Update(POKEY_OFFSET_AUDF4, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_STIMER + POKEY_OFFSET_POKEY2:
+		POKEYSND_Update(POKEY_OFFSET_STIMER, byte, 1, SOUND_GAIN);
+		break;
+	case POKEY_OFFSET_SKCTL + POKEY_OFFSET_POKEY2:
+		POKEYSND_Update(POKEY_OFFSET_SKCTL, byte, 1, SOUND_GAIN);
+		break;
+#endif
+	}
+}
+
+int POKEY_Initialise(void)
+{
+	int i;
+	ULONG reg;
+
+	/* Initialise Serial Port Interrupts */
+	POKEY_DELAYED_SERIN_IRQ = 0;
+	POKEY_DELAYED_SEROUT_IRQ = 0;
+	POKEY_DELAYED_XMTDONE_IRQ = 0;
+
+	POKEY_KBCODE = 0xff;
+	POKEY_SERIN = 0x00;	/* or 0xff ? */
+	POKEY_IRQST = 0xff;
+	POKEY_IRQEN = 0x00;
+	POKEY_SKSTAT = 0xef;
+	POKEY_SKCTL = 0x00;
+
+	for (i = 0; i < (POKEY_MAXPOKEYS * 4); i++) {
+		POKEY_AUDC[i] = 0;
+		POKEY_AUDF[i] = 0;
+	}
+
+	for (i = 0; i < POKEY_MAXPOKEYS; i++) {
+		POKEY_AUDCTL[i] = 0;
+		POKEY_Base_mult[i] = POKEY_DIV_64;
+	}
+
+	for (i = 0; i < 4; i++)
+		POKEY_DivNIRQ[i] = POKEY_DivNMax[i] = 0;
+
+	pot_scanline = 0;
+
+#if SKIP
+	/* initialise poly9_lookup */
+	reg = 0x1ff;
+	for (i = 0; i < POKEY_POLY9_SIZE; i++) {
+		reg = ((((reg >> 5) ^ reg) & 1) << 8) + (reg >> 1);
+		POKEY_poly9_lookup[i] = (UBYTE) reg;
+	}
+	/* initialise poly17_lookup */
+	reg = 0x1ffff;
+	for (i = 0; i < POKEY_POLY17_SIZE; i++) {
+		reg = ((((reg >> 5) ^ reg) & 0xff) << 9) + (reg >> 8);
+		POKEY_poly17_lookup[i] = (UBYTE) (reg >> 1);
+	}
+#endif
+
+#ifndef BASIC
+#if SKIP
+	if (INPUT_Playingback()) {
+		random_scanline_counter = INPUT_PlaybackInt();
+	}
+	else
+#endif 
+#endif
+	{
+		random_scanline_counter =
+#ifdef HAVE_WINDOWS_H
+		GetTickCount() % POKEY_POLY17_SIZE;
+#elif defined(HAVE_TIME)
+		time(NULL) % POKEY_POLY17_SIZE;
+#else
+		0;
+#endif
+	}
+#ifndef BASIC
+#if SKIP
+	if (INPUT_Recording()) {
+		INPUT_RecordInt(random_scanline_counter);
+	}
+#endif 
+#endif
+
+	return TRUE;
+}
+
+void POKEY_Frame(void)
+{
+	random_scanline_counter %= (POKEY_AUDCTL[0] & POKEY_POLY9) ? POKEY_POLY9_SIZE : POKEY_POLY17_SIZE;
+}
+
+/***************************************************************************
+ ** Generate POKEY Timer IRQs if required                                 **
+ ** called on a per-scanline basis, not very precise, but good enough     **
+ ** for most applications                                                 **
+ ***************************************************************************/
+
+void POKEY_Scanline(void)
+{
+#ifdef POKEY_UPDATE
+	pokey_update();
+#endif
+
+#ifdef VOL_ONLY_SOUND
+	POKEYSND_UpdateVolOnly();
+#endif
+
+#ifndef BASIC
+	INPUT_Scanline();	/* Handle Amiga and ST mice. */
+						/* It's not a part of POKEY emulation, */
+						/* but it looks to be the best place to put it. */
+#endif
+
+	/* on nonpatched i/o-operation, enable the cassette timing */
+#if SKIP      
+	if (!ESC_enable_sio_patch) {
+		if (CASSETTE_AddScanLine())
+			POKEY_DELAYED_SERIN_IRQ = 1;
+	}
+#endif
+	if ((POKEY_SKCTL & 0x03) == 0)
+		/* Don't process timers when POKEY is in reset mode. */
+		return;
+
+	if (pot_scanline < 228)
+		pot_scanline++;
+
+	random_scanline_counter += ANTIC_LINE_C;
+
+	if (POKEY_DELAYED_SERIN_IRQ > 0) {
+		if (--POKEY_DELAYED_SERIN_IRQ == 0) {
+			/* Load a byte to SERIN - even when the IRQ is disabled. */
+			POKEY_SERIN = SIO_GetByte();   
+			if (POKEY_IRQEN & 0x20) {
+				if (POKEY_IRQST & 0x20) {
+					POKEY_IRQST &= 0xdf;
+#ifdef DEBUG2
+					printf("SERIO: SERIN Interrupt triggered, bytevalue %02x\n", POKEY_SERIN);
+#endif
+				}
+				else {
+					POKEY_SKSTAT &= 0xdf;
+#ifdef DEBUG2
+					printf("SERIO: SERIN Interrupt triggered, bytevalue %02x\n", POKEY_SERIN);
+#endif
+				}
+				CPU_GenerateIRQ();
+			}
+#ifdef DEBUG2
+			else {
+				printf("SERIO: SERIN Interrupt missed, bytevalue %02x\n", POKEY_SERIN);
+			}
+#endif
+		}
+	}
+
+	if (POKEY_DELAYED_SEROUT_IRQ > 0) {
+		if (--POKEY_DELAYED_SEROUT_IRQ == 0) {
+			if (POKEY_IRQEN & 0x10) {
+#ifdef DEBUG2
+				printf("SERIO: SEROUT Interrupt triggered\n");
+#endif
+				POKEY_IRQST &= 0xef;
+				CPU_GenerateIRQ();
+			}
+#ifdef DEBUG2
+			else {
+				printf("SERIO: SEROUT Interrupt missed\n");
+			}
+#endif
+		}
+	}
+
+	if (POKEY_DELAYED_XMTDONE_IRQ > 0)
+		if (--POKEY_DELAYED_XMTDONE_IRQ == 0) {
+			POKEY_IRQST &= 0xf7;
+			if (POKEY_IRQEN & 0x08) {
+#ifdef DEBUG2
+				printf("SERIO: XMTDONE Interrupt triggered\n");
+#endif
+				CPU_GenerateIRQ();
+			}
+#ifdef DEBUG2
+			else
+				printf("SERIO: XMTDONE Interrupt missed\n");
+#endif
+		}
+
+	if ((POKEY_DivNIRQ[POKEY_CHAN1] -= ANTIC_LINE_C) < 0 ) {
+		POKEY_DivNIRQ[POKEY_CHAN1] += POKEY_DivNMax[POKEY_CHAN1];
+		if (POKEY_IRQEN & 0x01) {
+			POKEY_IRQST &= 0xfe;
+			CPU_GenerateIRQ();
+		}
+	}
+
+	if ((POKEY_DivNIRQ[POKEY_CHAN2] -= ANTIC_LINE_C) < 0 ) {
+		POKEY_DivNIRQ[POKEY_CHAN2] += POKEY_DivNMax[POKEY_CHAN2];
+		if (POKEY_IRQEN & 0x02) {
+			POKEY_IRQST &= 0xfd;
+			CPU_GenerateIRQ();
+		}
+	}
+
+	if ((POKEY_DivNIRQ[POKEY_CHAN4] -= ANTIC_LINE_C) < 0 ) {
+		POKEY_DivNIRQ[POKEY_CHAN4] += POKEY_DivNMax[POKEY_CHAN4];
+		if (POKEY_IRQEN & 0x04) {
+			POKEY_IRQST &= 0xfb;
+			CPU_GenerateIRQ();
+		}
+	}
+}
+
+/*****************************************************************************/
+/* Module:  Update_Counter()                                                 */
+/* Purpose: To process the latest control values stored in the AUDF, AUDC,   */
+/*          and AUDCTL registers.  It pre-calculates as much information as  */
+/*          possible for better performance.  This routine has been added    */
+/*          here again as I need the precise frequency for the pokey timers  */
+/*          again. The pokey emulation is therefore somewhat sub-optimal     */
+/*          since the actual pokey emulation should grab the frequency values */
+/*          directly from here instead of calculating them again.            */
+/*                                                                           */
+/* Author:  Ron Fries,Thomas Richter                                         */
+/* Date:    March 27, 1998                                                   */
+/*                                                                           */
+/* Inputs:  chan_mask: Channel mask, one bit per channel.                    */
+/*          The channels that need to be updated                             */
+/*                                                                           */
+/* Outputs: Adjusts local globals - no return value                          */
+/*                                                                           */
+/*****************************************************************************/
+
+static void Update_Counter(int chan_mask)
+{
+
+/************************************************************/
+/* As defined in the manual, the exact Div_n_cnt values are */
+/* different depending on the frequency and resolution:     */
+/*    64 kHz or 15 kHz - AUDF + 1                           */
+/*    1 MHz, 8-bit -     AUDF + 4                           */
+/*    1 MHz, 16-bit -    AUDF[CHAN1]+256*AUDF[CHAN2] + 7    */
+/************************************************************/
+
+	/* only reset the channels that have changed */
+
+	if (chan_mask & (1 << POKEY_CHAN1)) {
+		/* process channel 1 frequency */
+		if (POKEY_AUDCTL[0] & POKEY_CH1_179)
+			POKEY_DivNMax[POKEY_CHAN1] = POKEY_AUDF[POKEY_CHAN1] + 4;
+		else
+			POKEY_DivNMax[POKEY_CHAN1] = (POKEY_AUDF[POKEY_CHAN1] + 1) * POKEY_Base_mult[0];
+		if (POKEY_DivNMax[POKEY_CHAN1] < ANTIC_LINE_C)
+			POKEY_DivNMax[POKEY_CHAN1] = ANTIC_LINE_C;
+	}
+
+	if (chan_mask & (1 << POKEY_CHAN2)) {
+		/* process channel 2 frequency */
+		if (POKEY_AUDCTL[0] & POKEY_CH1_CH2) {
+			if (POKEY_AUDCTL[0] & POKEY_CH1_179)
+				POKEY_DivNMax[POKEY_CHAN2] = POKEY_AUDF[POKEY_CHAN2] * 256 + POKEY_AUDF[POKEY_CHAN1] + 7;
+			else
+				POKEY_DivNMax[POKEY_CHAN2] = (POKEY_AUDF[POKEY_CHAN2] * 256 + POKEY_AUDF[POKEY_CHAN1] + 1) * POKEY_Base_mult[0];
+		}
+		else
+			POKEY_DivNMax[POKEY_CHAN2] = (POKEY_AUDF[POKEY_CHAN2] + 1) * POKEY_Base_mult[0];
+		if (POKEY_DivNMax[POKEY_CHAN2] < ANTIC_LINE_C)
+			POKEY_DivNMax[POKEY_CHAN2] = ANTIC_LINE_C;
+	}
+
+	if (chan_mask & (1 << POKEY_CHAN4)) {
+		/* process channel 4 frequency */
+		if (POKEY_AUDCTL[0] & POKEY_CH3_CH4) {
+			if (POKEY_AUDCTL[0] & POKEY_CH3_179)
+				POKEY_DivNMax[POKEY_CHAN4] = POKEY_AUDF[POKEY_CHAN4] * 256 + POKEY_AUDF[POKEY_CHAN3] + 7;
+			else
+				POKEY_DivNMax[POKEY_CHAN4] = (POKEY_AUDF[POKEY_CHAN4] * 256 + POKEY_AUDF[POKEY_CHAN3] + 1) * POKEY_Base_mult[0];
+		}
+		else
+			POKEY_DivNMax[POKEY_CHAN4] = (POKEY_AUDF[POKEY_CHAN4] + 1) * POKEY_Base_mult[0];
+		if (POKEY_DivNMax[POKEY_CHAN4] < ANTIC_LINE_C)
+			POKEY_DivNMax[POKEY_CHAN4] = ANTIC_LINE_C;
+	}
+}
+
+#ifndef BASIC
+
+void POKEY_StateSave(void)
+{
+	int shift_key = 0;
+	int keypressed = 0;
+
+	StateSav_SaveUBYTE(&POKEY_KBCODE, 1);
+	StateSav_SaveUBYTE(&POKEY_IRQST, 1);
+	StateSav_SaveUBYTE(&POKEY_IRQEN, 1);
+	StateSav_SaveUBYTE(&POKEY_SKCTL, 1);
+
+	StateSav_SaveINT(&shift_key, 1);
+	StateSav_SaveINT(&keypressed, 1);
+	StateSav_SaveINT(&POKEY_DELAYED_SERIN_IRQ, 1);
+	StateSav_SaveINT(&POKEY_DELAYED_SEROUT_IRQ, 1);
+	StateSav_SaveINT(&POKEY_DELAYED_XMTDONE_IRQ, 1);
+
+	StateSav_SaveUBYTE(&POKEY_AUDF[0], 4);
+	StateSav_SaveUBYTE(&POKEY_AUDC[0], 4);
+	StateSav_SaveUBYTE(&POKEY_AUDCTL[0], 1);
+
+	StateSav_SaveINT(&POKEY_DivNIRQ[0], 4);
+	StateSav_SaveINT(&POKEY_DivNMax[0], 4);
+	StateSav_SaveINT(&POKEY_Base_mult[0], 1);
+}
+
+void POKEY_StateRead(void)
+{
+	int i;
+	int shift_key;
+	int keypressed;
+
+	StateSav_ReadUBYTE(&POKEY_KBCODE, 1);
+	StateSav_ReadUBYTE(&POKEY_IRQST, 1);
+	StateSav_ReadUBYTE(&POKEY_IRQEN, 1);
+	StateSav_ReadUBYTE(&POKEY_SKCTL, 1);
+
+	StateSav_ReadINT(&shift_key, 1);
+	StateSav_ReadINT(&keypressed, 1);
+	StateSav_ReadINT(&POKEY_DELAYED_SERIN_IRQ, 1);
+	StateSav_ReadINT(&POKEY_DELAYED_SEROUT_IRQ, 1);
+	StateSav_ReadINT(&POKEY_DELAYED_XMTDONE_IRQ, 1);
+
+	StateSav_ReadUBYTE(&POKEY_AUDF[0], 4);
+	StateSav_ReadUBYTE(&POKEY_AUDC[0], 4);
+	StateSav_ReadUBYTE(&POKEY_AUDCTL[0], 1);
+	for (i = 0; i < 4; i++) {
+		POKEY_PutByte((UWORD) (POKEY_OFFSET_AUDF1 + i * 2), POKEY_AUDF[i]);
+		POKEY_PutByte((UWORD) (POKEY_OFFSET_AUDC1 + i * 2), POKEY_AUDC[i]);
+	}
+	POKEY_PutByte(POKEY_OFFSET_AUDCTL, POKEY_AUDCTL[0]);
+
+	StateSav_ReadINT(&POKEY_DivNIRQ[0], 4);
+	StateSav_ReadINT(&POKEY_DivNMax[0], 4);
+	StateSav_ReadINT(&POKEY_Base_mult[0], 1);
+}
+
+#endif
diff --git a/MCUME_pico2/pico800/pokey.h b/MCUME_pico2/pico800/pokey.h
new file mode 100644
index 0000000..b9a0c29
--- /dev/null
+++ b/MCUME_pico2/pico800/pokey.h
@@ -0,0 +1,120 @@
+#ifndef POKEY_H_
+#define POKEY_H_
+
+
+#include "atari.h"
+
+
+#define POKEY_OFFSET_AUDF1 0x00
+#define POKEY_OFFSET_AUDC1 0x01
+#define POKEY_OFFSET_AUDF2 0x02
+#define POKEY_OFFSET_AUDC2 0x03
+#define POKEY_OFFSET_AUDF3 0x04
+#define POKEY_OFFSET_AUDC3 0x05
+#define POKEY_OFFSET_AUDF4 0x06
+#define POKEY_OFFSET_AUDC4 0x07
+#define POKEY_OFFSET_AUDCTL 0x08
+#define POKEY_OFFSET_STIMER 0x09
+#define POKEY_OFFSET_SKRES 0x0a
+#define POKEY_OFFSET_POTGO 0x0b
+#define POKEY_OFFSET_SEROUT 0x0d
+#define POKEY_OFFSET_IRQEN 0x0e
+#define POKEY_OFFSET_SKCTL 0x0f
+
+#define POKEY_OFFSET_POT0 0x00
+#define POKEY_OFFSET_POT1 0x01
+#define POKEY_OFFSET_POT2 0x02
+#define POKEY_OFFSET_POT3 0x03
+#define POKEY_OFFSET_POT4 0x04
+#define POKEY_OFFSET_POT5 0x05
+#define POKEY_OFFSET_POT6 0x06
+#define POKEY_OFFSET_POT7 0x07
+#define POKEY_OFFSET_ALLPOT 0x08
+#define POKEY_OFFSET_KBCODE 0x09
+#define POKEY_OFFSET_RANDOM 0x0a
+#define POKEY_OFFSET_SERIN 0x0d
+#define POKEY_OFFSET_IRQST 0x0e
+#define POKEY_OFFSET_SKSTAT 0x0f
+
+#define POKEY_OFFSET_POKEY2 0x10			/* offset to second pokey chip (STEREO expansion) */
+
+#ifndef ASAP
+
+extern UBYTE POKEY_KBCODE;
+extern UBYTE POKEY_IRQST;
+extern UBYTE POKEY_IRQEN;
+extern UBYTE POKEY_SKSTAT;
+extern UBYTE POKEY_SKCTL;
+extern int POKEY_DELAYED_SERIN_IRQ;
+extern int POKEY_DELAYED_SEROUT_IRQ;
+extern int POKEY_DELAYED_XMTDONE_IRQ;
+
+extern UBYTE POKEY_POT_input[8];
+
+ULONG POKEY_GetRandomCounter(void);
+void POKEY_SetRandomCounter(ULONG value);
+UBYTE POKEY_GetByte(UWORD addr, int no_side_effects);
+void POKEY_PutByte(UWORD addr, UBYTE byte);
+int POKEY_Initialise(void);
+void POKEY_Frame(void);
+void POKEY_Scanline(void);
+void POKEY_StateSave(void);
+void POKEY_StateRead(void);
+
+#endif
+
+/* CONSTANT DEFINITIONS */
+
+/* definitions for AUDCx (D201, D203, D205, D207) */
+#define POKEY_NOTPOLY5    0x80		/* selects POLY5 or direct CLOCK */
+#define POKEY_POLY4       0x40		/* selects POLY4 or POLY17 */
+#define POKEY_PURETONE    0x20		/* selects POLY4/17 or PURE tone */
+#define POKEY_VOL_ONLY    0x10		/* selects VOLUME OUTPUT ONLY */
+#define POKEY_VOLUME_MASK 0x0f		/* volume mask */
+
+/* definitions for AUDCTL (D208) */
+#define POKEY_POLY9       0x80		/* selects POLY9 or POLY17 */
+#define POKEY_CH1_179     0x40		/* selects 1.78979 MHz for Ch 1 */
+#define POKEY_CH3_179     0x20		/* selects 1.78979 MHz for Ch 3 */
+#define POKEY_CH1_CH2     0x10		/* clocks channel 1 w/channel 2 */
+#define POKEY_CH3_CH4     0x08		/* clocks channel 3 w/channel 4 */
+#define POKEY_CH1_FILTER  0x04		/* selects channel 1 high pass filter */
+#define POKEY_CH2_FILTER  0x02		/* selects channel 2 high pass filter */
+#define POKEY_CLOCK_15    0x01		/* selects 15.6999kHz or 63.9210kHz */
+
+/* for accuracy, the 64kHz and 15kHz clocks are exact divisions of
+   the 1.79MHz clock */
+#define POKEY_DIV_64      28			/* divisor for 1.79MHz clock to 64 kHz */
+#define POKEY_DIV_15      114			/* divisor for 1.79MHz clock to 15 kHz */
+
+/* the size (in entries) of the 4 polynomial tables */
+#define POKEY_POLY4_SIZE  0x000f
+#define POKEY_POLY5_SIZE  0x001f
+#define POKEY_POLY9_SIZE  511 //0x01ff
+#define POKEY_POLY17_SIZE 16385//0x0001ffff
+
+#define POKEY_MAXPOKEYS         2		/* max number of emulated chips */
+
+/* channel/chip definitions */
+#define POKEY_CHAN1       0
+#define POKEY_CHAN2       1
+#define POKEY_CHAN3       2
+#define POKEY_CHAN4       3
+#define POKEY_CHIP1       0
+#define POKEY_CHIP2       4
+#define POKEY_CHIP3       8
+#define POKEY_CHIP4      12
+#define POKEY_SAMPLE    127
+
+/* structures to hold the 9 pokey control bytes */
+extern UBYTE POKEY_AUDF[4 * POKEY_MAXPOKEYS];	/* AUDFx (D200, D202, D204, D206) */
+extern UBYTE POKEY_AUDC[4 * POKEY_MAXPOKEYS];	/* AUDCx (D201, D203, D205, D207) */
+extern UBYTE POKEY_AUDCTL[POKEY_MAXPOKEYS];		/* AUDCTL (D208) */
+
+extern int POKEY_DivNIRQ[4], POKEY_DivNMax[4];
+extern int POKEY_Base_mult[POKEY_MAXPOKEYS];	/* selects either 64Khz or 15Khz clock mult */
+
+extern const UBYTE POKEY_poly9_lookup[POKEY_POLY9_SIZE];
+extern const UBYTE POKEY_poly17_lookup[POKEY_POLY17_SIZE];
+
+#endif /* POKEY_H_ */
diff --git a/MCUME_pico2/pico800/pokeysnd.c b/MCUME_pico2/pico800/pokeysnd.c
new file mode 100644
index 0000000..7545f7a
--- /dev/null
+++ b/MCUME_pico2/pico800/pokeysnd.c
@@ -0,0 +1,1428 @@
+/*
+ * pokeysnd.c - POKEY sound chip emulation, v2.4
+ *
+ * Copyright (C) 1996-1998 Ron Fries
+ * Copyright (C) 1998-2014 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifdef skip
+#include "config.h"
+#include <stdlib.h>
+#include <math.h>
+
+#ifdef ASAP /* external project, see http://asap.sf.net */
+#include "asap_internal.h"
+#else
+#include "atari.h"
+#ifndef __PLUS
+#include "sndsave.h"
+#else
+#include "sound_win.h"
+#endif
+#endif
+#include "mzpokeysnd.h"
+#include "pokeysnd.h"
+#if defined(PBI_XLD) || defined (VOICEBOX)
+#include "votraxsnd.h"
+#endif
+#include "antic.h"
+#include "gtia.h"
+#include "util.h"
+#endif
+
+#include "pokeysnd.h"
+#if defined(PBI_XLD) || defined (VOICEBOX)
+#include "votraxsnd.h"
+#endif
+#include "antic.h"
+#include "gtia.h"
+
+#ifdef WORDS_UNALIGNED_OK
+#  define READ_U32(x)     (*(ULONG *) (x))
+#  define WRITE_U32(x, d) (*(ULONG *) (x) = (d))
+#else
+#  ifdef WORDS_BIGENDIAN
+#    define READ_U32(x) (((*(unsigned char *)(x)) << 24) | ((*((unsigned char *)(x) + 1)) << 16) | \
+                        ((*((unsigned char *)(x) + 2)) << 8) | ((*((unsigned char *)(x) + 3))))
+#    define WRITE_U32(x, d) \
+  { \
+  ULONG i = d; \
+  (*(unsigned char *) (x)) = (((i) >> 24) & 255); \
+  (*((unsigned char *) (x) + 1)) = (((i) >> 16) & 255); \
+  (*((unsigned char *) (x) + 2)) = (((i) >> 8) & 255); \
+  (*((unsigned char *) (x) + 3)) = ((i) & 255); \
+  }
+#  else
+#    define READ_U32(x) ((*(unsigned char *) (x)) | ((*((unsigned char *) (x) + 1)) << 8) | \
+                        ((*((unsigned char *) (x) + 2)) << 16) | ((*((unsigned char *) (x) + 3)) << 24))
+#    define WRITE_U32(x, d) \
+  { \
+  ULONG i = d; \
+  (*(unsigned char *)(x)) = ((i) & 255); \
+  (*((unsigned char *)(x) + 1)) = (((i) >> 8) & 255); \
+  (*((unsigned char *)(x) + 2)) = (((i) >> 16) & 255); \
+  (*((unsigned char *)(x) + 3)) = (((i) >> 24) & 255); \
+  }
+#  endif
+#endif
+
+/* GLOBAL VARIABLE DEFINITIONS */
+
+/* number of pokey chips currently emulated */
+static UBYTE Num_pokeys;
+
+static UBYTE pokeysnd_AUDV[4 * POKEY_MAXPOKEYS];	/* Channel volume - derived */
+
+static UBYTE Outbit[4 * POKEY_MAXPOKEYS];		/* current state of the output (high or low) */
+
+static UBYTE Outvol[4 * POKEY_MAXPOKEYS];		/* last output volume for each channel */
+
+/* Initialize the bit patterns for the polynomials. */
+
+/* The 4bit and 5bit patterns are the identical ones used in the pokey chip. */
+/* Though the patterns could be packed with 8 bits per byte, using only a */
+/* single bit per byte keeps the math simple, which is important for */
+/* efficient processing. */
+
+static const UBYTE bit4[POKEY_POLY4_SIZE] =
+#ifndef POKEY23_POLY
+{1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0};	/* new table invented by Perry */
+#else
+{1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0};	/* original POKEY 2.3 table */
+#endif
+
+static const UBYTE bit5[POKEY_POLY5_SIZE] =
+#ifndef POKEY23_POLY
+{1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0};
+#else
+{0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1};
+#endif
+
+static ULONG P4 = 0,			/* Global position pointer for the 4-bit  POLY array */
+ P5 = 0,						/* Global position pointer for the 5-bit  POLY array */
+ P9 = 0,						/* Global position pointer for the 9-bit  POLY array */
+ P17 = 0;						/* Global position pointer for the 17-bit POLY array */
+
+static ULONG Div_n_cnt[4 * POKEY_MAXPOKEYS],		/* Divide by n counter. one for each channel */
+ Div_n_max[4 * POKEY_MAXPOKEYS];		/* Divide by n maximum, one for each channel */
+
+static ULONG Samp_n_max,		/* Sample max.  For accuracy, it is *256 */
+ Samp_n_cnt[2];					/* Sample cnt. */
+
+#ifdef INTERPOLATE_SOUND
+#ifdef CLIP_SOUND
+static SWORD last_val = 0;		/* last output value */
+#else
+static UWORD last_val = 0;
+#endif
+#ifdef STEREO_SOUND
+#ifdef CLIP_SOUND
+static SWORD last_val2 = 0;	/* last output value */
+#else
+static UWORD last_val2 = 0;
+#endif
+#endif
+#endif
+
+/* Volume only emulations declarations */
+#ifdef VOL_ONLY_SOUND
+
+int	POKEYSND_sampbuf_val[POKEYSND_SAMPBUF_MAX];	/* volume values */
+int	POKEYSND_sampbuf_cnt[POKEYSND_SAMPBUF_MAX];	/* relative start time */
+int	POKEYSND_sampbuf_ptr = 0;		/* pointer to sampbuf */
+int	POKEYSND_sampbuf_rptr = 0;		/* pointer to read from sampbuf */
+int	POKEYSND_sampbuf_last = 0;		/* last absolute time */
+int	POKEYSND_sampbuf_AUDV[4 * POKEY_MAXPOKEYS];	/* prev. channel volume */
+int	POKEYSND_sampbuf_lastval = 0;		/* last volume */
+int	POKEYSND_sampout;			/* last out volume */
+int	POKEYSND_samp_freq;
+int	POKEYSND_samp_consol_val = 0;		/* actual value of console sound */
+#ifdef STEREO_SOUND
+static int	sampbuf_val2[POKEYSND_SAMPBUF_MAX];	/* volume values */
+static int	sampbuf_cnt2[POKEYSND_SAMPBUF_MAX];	/* relative start time */
+static int	sampbuf_ptr2 = 0;		/* pointer to sampbuf */
+static int	sampbuf_rptr2 = 0;		/* pointer to read from sampbuf */
+static int	sampbuf_last2 = 0;		/* last absolute time */
+static int	sampbuf_lastval2 = 0;		/* last volume */
+static int	sampout2;			/* last out volume */
+#endif
+#endif  /* VOL_ONLY_SOUND */
+
+static ULONG snd_freq17 = POKEYSND_FREQ_17_EXACT;
+int POKEYSND_playback_freq = 44100;
+UBYTE POKEYSND_num_pokeys = 1;
+int POKEYSND_snd_flags = 0;
+static int mz_quality = 0;		/* default quality for mzpokeysnd */
+#ifdef __PLUS
+int mz_clear_regs = 0;
+#endif
+
+int POKEYSND_enable_new_pokey = TRUE;
+int POKEYSND_bienias_fix = TRUE;  /* when TRUE, high frequencies get emulated: better sound but slower */
+#if defined(__PLUS) && !defined(_WX_)
+#define BIENIAS_FIX (g_Sound.nBieniasFix)
+#else
+#define BIENIAS_FIX POKEYSND_bienias_fix
+#endif
+#ifndef ASAP
+int POKEYSND_stereo_enabled = FALSE;
+#endif
+
+int POKEYSND_volume = 0x100;
+
+/* multiple sound engine interface */
+static void pokeysnd_process_8(void *sndbuffer, int sndn);
+static void pokeysnd_process_16(void *sndbuffer, int sndn);
+static void null_pokey_process(void *sndbuffer, int sndn) {}
+void (*POKEYSND_Process_ptr)(void *sndbuffer, int sndn) = null_pokey_process;
+
+static void Update_pokey_sound_rf(UWORD, UBYTE, UBYTE, UBYTE);
+static void null_pokey_sound(UWORD addr, UBYTE val, UBYTE chip, UBYTE gain) {}
+void (*POKEYSND_Update_ptr) (UWORD addr, UBYTE val, UBYTE chip, UBYTE gain)
+  = null_pokey_sound;
+
+#ifdef SERIO_SOUND
+static void Update_serio_sound_rf(int out, UBYTE data);
+static void null_serio_sound(int out, UBYTE data) {}
+void (*POKEYSND_UpdateSerio)(int out, UBYTE data) = null_serio_sound;
+int POKEYSND_serio_sound_enabled = 1;
+#endif
+
+#ifdef CONSOLE_SOUND
+static void Update_consol_sound_rf(int set);
+static void null_consol_sound(int set) {}
+void (*POKEYSND_UpdateConsol_ptr)(int set) = null_consol_sound;
+int POKEYSND_console_sound_enabled = 1;
+#endif
+
+#ifdef VOL_ONLY_SOUND
+static void Update_vol_only_sound_rf(void);
+static void null_vol_only_sound(void) {}
+void (*POKEYSND_UpdateVolOnly)(void) = null_vol_only_sound;
+#endif
+
+#ifdef SYNCHRONIZED_SOUND
+UBYTE *POKEYSND_process_buffer = NULL;
+unsigned int POKEYSND_process_buffer_length;
+unsigned int POKEYSND_process_buffer_fill;
+static unsigned int prev_update_tick;
+
+static void Generate_sync_rf(unsigned int num_ticks);
+static void null_generate_sync(unsigned int num_ticks) {}
+void (*POKEYSND_GenerateSync)(unsigned int num_ticks) = null_generate_sync;
+
+static double ticks_per_sample;
+static double samp_pos;
+static int speaker;
+static int const CONSOLE_VOL = 32;
+#endif /* SYNCHRONIZED_SOUND */
+
+/*****************************************************************************/
+/* In my routines, I treat the sample output as another divide by N counter  */
+/* For better accuracy, the Samp_n_cnt has a fixed binary decimal point      */
+/* which has 8 binary digits to the right of the decimal point.  I use a two */
+/* byte array to give me a minimum of 40 bits, and then use pointer math to  */
+/* reference either the 24.8 whole/fraction combination or the 32-bit whole  */
+/* only number.  This is mainly used to keep the math simple for             */
+/* optimization. See below:                                                  */
+/*                                                                           */
+/* Representation on little-endian machines:                                 */
+/* xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx | xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx */
+/* fraction   whole    whole    whole      whole   unused   unused   unused  */
+/*                                                                           */
+/* Samp_n_cnt[0] gives me a 32-bit int 24 whole bits with 8 fractional bits, */
+/* while (ULONG *)((UBYTE *)(&Samp_n_cnt[0])+1) gives me the 32-bit whole   */
+/* number only.                                                              */
+/*                                                                           */
+/* Representation on big-endian machines:                                    */
+/* xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx | xxxxxxxx xxxxxxxx xxxxxxxx.xxxxxxxx */
+/*  unused   unused   unused    whole      whole    whole    whole  fraction */
+/*                                                                           */
+/* Samp_n_cnt[1] gives me a 32-bit int 24 whole bits with 8 fractional bits, */
+/* while (ULONG *)((UBYTE *)(&Samp_n_cnt[0])+3) gives me the 32-bit whole   */
+/* number only.                                                              */
+/*****************************************************************************/
+
+
+/*****************************************************************************/
+/* Module:  pokeysnd_init_rf()                                              */
+/* Purpose: to handle the power-up initialization functions                  */
+/*          these functions should only be executed on a cold-restart        */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    January 1, 1997                                                  */
+/*                                                                           */
+/* Inputs:  freq17 - the value for the '1.79MHz' Pokey audio clock           */
+/*          playback_freq - the playback frequency in samples per second     */
+/*          num_pokeys - specifies the number of pokey chips to be emulated  */
+/*                                                                           */
+/* Outputs: Adjusts local globals - no return value                          */
+/*                                                                           */
+/*****************************************************************************/
+
+static int pokeysnd_init_rf(ULONG freq17, int playback_freq,
+           UBYTE num_pokeys, int flags);
+
+#ifdef VOL_ONLY_SOUND
+/* Initialise variables related to volume-only sound. */
+static void init_vol_only(void)
+{
+	POKEYSND_sampbuf_rptr = POKEYSND_sampbuf_ptr;
+	POKEYSND_sampbuf_last = ANTIC_CPU_CLOCK;
+	POKEYSND_sampbuf_lastval = 0;
+	POKEYSND_samp_consol_val = 0;
+#ifdef STEREO_SOUND
+	sampbuf_rptr2 = sampbuf_ptr2;
+	sampbuf_last2 = ANTIC_CPU_CLOCK;
+	sampbuf_lastval2 = 0;
+#endif /* STEREO_SOUND */
+}
+#endif /* VOL_ONLY_SOUND */
+
+int POKEYSND_DoInit(void)
+{
+#if SKIP  
+	SndSave_CloseSoundFile();
+#endif
+
+#ifdef VOL_ONLY_SOUND
+	init_vol_only();
+#endif /* VOL_ONLY_SOUND */
+
+#if SKIP    
+	if (POKEYSND_enable_new_pokey)
+		return MZPOKEYSND_Init(snd_freq17, POKEYSND_playback_freq,
+				POKEYSND_num_pokeys, POKEYSND_snd_flags, mz_quality
+#ifdef __PLUS
+				, mz_clear_regs
+#endif
+		);
+	else
+#endif  
+		return pokeysnd_init_rf(snd_freq17, POKEYSND_playback_freq,
+				POKEYSND_num_pokeys, POKEYSND_snd_flags);
+}
+
+int POKEYSND_Init(ULONG freq17, int playback_freq, UBYTE num_pokeys,
+                     int flags
+#ifdef __PLUS
+                     , int clear_regs
+#endif
+)
+{
+	snd_freq17 = freq17;
+	POKEYSND_playback_freq = playback_freq;
+	POKEYSND_num_pokeys = num_pokeys;
+	POKEYSND_snd_flags = flags;
+#ifdef __PLUS
+	mz_clear_regs = clear_regs;
+#endif
+#ifdef SYNCHRONIZED_SOUND
+	{
+		/* A single call to Atari800_Frame may emulate a bit more CPU ticks than the exact number of
+		   ticks per frame (Atari800_tv_mode*114). So we add a few ticks to buffer size just to be safe. */
+		unsigned int const surplus_ticks = 10;
+		double samples_per_frame = (double)POKEYSND_playback_freq/(Atari800_tv_mode == Atari800_TV_PAL ? Atari800_FPS_PAL : Atari800_FPS_NTSC);
+		unsigned int ticks_per_frame = Atari800_tv_mode*114;
+		unsigned int max_ticks_per_frame = ticks_per_frame + surplus_ticks;
+		double ticks_per_sample = (double)ticks_per_frame / samples_per_frame;
+		POKEYSND_process_buffer_length = POKEYSND_num_pokeys * (unsigned int)ceil((double)max_ticks_per_frame / ticks_per_sample) * ((POKEYSND_snd_flags & POKEYSND_BIT16) ? 2:1);
+		free(POKEYSND_process_buffer);
+		POKEYSND_process_buffer = (UBYTE *)Util_malloc(POKEYSND_process_buffer_length);
+		POKEYSND_process_buffer_fill = 0;
+	    prev_update_tick = ANTIC_CPU_CLOCK;
+	}
+#endif /* SYNCHRONIZED_SOUND */
+
+#if defined(PBI_XLD) || defined (VOICEBOX)
+	VOTRAXSND_Init(playback_freq, num_pokeys, (flags & POKEYSND_BIT16));
+#endif
+	return POKEYSND_DoInit();
+}
+
+void POKEYSND_SetMzQuality(int quality)	/* specially for win32, perhaps not needed? */
+{
+	mz_quality = quality;
+}
+
+void SND_Process(void *sndbuffer, int sndn)
+{
+	POKEYSND_Process_ptr(sndbuffer, sndn);
+#if defined(PBI_XLD) || defined (VOICEBOX)
+	VOTRAXSND_Process(sndbuffer,sndn);
+#endif
+#if !defined(__PLUS) && !defined(ASAP)
+#if SKIP
+	SndSave_WriteToSoundFile((const unsigned char *)sndbuffer, sndn);
+#endif
+#endif
+}
+
+#ifdef SYNCHRONIZED_SOUND
+static void Update_synchronized_sound(void)
+{
+	POKEYSND_GenerateSync(ANTIC_CPU_CLOCK - prev_update_tick);
+	prev_update_tick = ANTIC_CPU_CLOCK;
+}
+
+int POKEYSND_UpdateProcessBuffer(void)
+{
+	int sndn;
+	Update_synchronized_sound();
+	sndn = POKEYSND_process_buffer_fill / ((POKEYSND_snd_flags & POKEYSND_BIT16) ? 2 : 1);
+	POKEYSND_process_buffer_fill = 0;
+
+#if defined(PBI_XLD) || defined (VOICEBOX)
+	VOTRAXSND_Process(POKEYSND_process_buffer, sndn);
+#endif
+#if !defined(__PLUS) && !defined(ASAP)
+	SndSave_WriteToSoundFile((const unsigned char *)POKEYSND_process_buffer, sndn);
+#endif
+	return sndn;
+}
+#endif /* SYNCHRONIZED_SOUND */
+
+#ifdef SYNCHRONIZED_SOUND
+static void init_syncsound(void)
+{
+	double samples_per_frame = (double)POKEYSND_playback_freq/(Atari800_tv_mode == Atari800_TV_PAL ? Atari800_FPS_PAL : Atari800_FPS_NTSC);
+	unsigned int ticks_per_frame = Atari800_tv_mode*114;
+	ticks_per_sample = (double)ticks_per_frame / samples_per_frame;
+	samp_pos = 0.0;
+	POKEYSND_GenerateSync = Generate_sync_rf;
+	speaker = 0;
+}
+#endif /* SYNCHRONIZED_SOUND */
+
+static int pokeysnd_init_rf(ULONG freq17, int playback_freq,
+           UBYTE num_pokeys, int flags)
+{
+	UBYTE chan;
+
+	POKEYSND_Update_ptr = Update_pokey_sound_rf;
+#ifdef SERIO_SOUND
+	POKEYSND_UpdateSerio = Update_serio_sound_rf;
+#endif
+#ifdef CONSOLE_SOUND
+	POKEYSND_UpdateConsol_ptr = Update_consol_sound_rf;
+#endif
+#ifdef VOL_ONLY_SOUND
+	POKEYSND_UpdateVolOnly = Update_vol_only_sound_rf;
+#endif
+
+	POKEYSND_Process_ptr = (flags & POKEYSND_BIT16) ? pokeysnd_process_16 : pokeysnd_process_8;
+
+#ifdef VOL_ONLY_SOUND
+	POKEYSND_samp_freq = playback_freq;
+#endif
+
+	/* start all of the polynomial counters at zero */
+	P4 = 0;
+	P5 = 0;
+	P9 = 0;
+	P17 = 0;
+
+	/* calculate the sample 'divide by N' value based on the playback freq. */
+	Samp_n_max = ((ULONG) freq17 << 8) / playback_freq;
+
+	Samp_n_cnt[0] = 0;			/* initialize all bits of the sample */
+	Samp_n_cnt[1] = 0;			/* 'divide by N' counter */
+
+	for (chan = 0; chan < (POKEY_MAXPOKEYS * 4); chan++) {
+		Outvol[chan] = 0;
+		Outbit[chan] = 0;
+		Div_n_cnt[chan] = 0;
+		Div_n_max[chan] = 0x7fffffffL;
+		pokeysnd_AUDV[chan] = 0;
+#ifdef VOL_ONLY_SOUND
+		POKEYSND_sampbuf_AUDV[chan] = 0;
+#endif
+	}
+
+	/* set the number of pokey chips currently emulated */
+	Num_pokeys = num_pokeys;
+
+#ifdef SYNCHRONIZED_SOUND
+	init_syncsound();
+#endif
+	return 0; /* OK */
+}
+
+
+/*****************************************************************************/
+/* Module:  Update_pokey_sound_rf()                                          */
+/* Purpose: To process the latest control values stored in the AUDF, AUDC,   */
+/*          and AUDCTL registers.  It pre-calculates as much information as  */
+/*          possible for better performance.  This routine has not been      */
+/*          optimized.                                                       */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    January 1, 1997                                                  */
+/*                                                                           */
+/* Inputs:  addr - the address of the parameter to be changed                */
+/*          val - the new value to be placed in the specified address        */
+/*          gain - specified as an 8-bit fixed point number - use 1 for no   */
+/*                 amplification (output is multiplied by gain)              */
+/*                                                                           */
+/* Outputs: Adjusts local globals - no return value                          */
+/*                                                                           */
+/*****************************************************************************/
+
+void POKEYSND_Update(UWORD addr, UBYTE val, UBYTE chip, UBYTE gain)
+{
+#ifdef SYNCHRONIZED_SOUND
+    Update_synchronized_sound();
+#endif /* SYNCHRONIZED_SOUND */
+	POKEYSND_Update_ptr(addr, val, chip, gain);
+}
+
+static void Update_pokey_sound_rf(UWORD addr, UBYTE val, UBYTE chip,
+				  UBYTE gain)
+{
+	ULONG new_val = 0;
+	UBYTE chan;
+	UBYTE chan_mask;
+	UBYTE chip_offs;
+
+	/* calculate the chip_offs for the channel arrays */
+	chip_offs = chip << 2;
+
+	/* determine which address was changed */
+	switch (addr & 0x0f) {
+	case POKEY_OFFSET_AUDF1:
+		/* POKEY_AUDF[POKEY_CHAN1 + chip_offs] = val; */
+		chan_mask = 1 << POKEY_CHAN1;
+		if (POKEY_AUDCTL[chip] & POKEY_CH1_CH2)		/* if ch 1&2 tied together */
+			chan_mask |= 1 << POKEY_CHAN2;	/* then also change on ch2 */
+		break;
+	case POKEY_OFFSET_AUDC1:
+		/* POKEY_AUDC[POKEY_CHAN1 + chip_offs] = val; */
+		pokeysnd_AUDV[POKEY_CHAN1 + chip_offs] = (val & POKEY_VOLUME_MASK) * gain;
+		chan_mask = 1 << POKEY_CHAN1;
+		break;
+	case POKEY_OFFSET_AUDF2:
+		/* POKEY_AUDF[POKEY_CHAN2 + chip_offs] = val; */
+		chan_mask = 1 << POKEY_CHAN2;
+		break;
+	case POKEY_OFFSET_AUDC2:
+		/* POKEY_AUDC[POKEY_CHAN2 + chip_offs] = val; */
+		pokeysnd_AUDV[POKEY_CHAN2 + chip_offs] = (val & POKEY_VOLUME_MASK) * gain;
+		chan_mask = 1 << POKEY_CHAN2;
+		break;
+	case POKEY_OFFSET_AUDF3:
+		/* POKEY_AUDF[POKEY_CHAN3 + chip_offs] = val; */
+		chan_mask = 1 << POKEY_CHAN3;
+		if (POKEY_AUDCTL[chip] & POKEY_CH3_CH4)		/* if ch 3&4 tied together */
+			chan_mask |= 1 << POKEY_CHAN4;	/* then also change on ch4 */
+		break;
+	case POKEY_OFFSET_AUDC3:
+		/* POKEY_AUDC[POKEY_CHAN3 + chip_offs] = val; */
+		pokeysnd_AUDV[POKEY_CHAN3 + chip_offs] = (val & POKEY_VOLUME_MASK) * gain;
+		chan_mask = 1 << POKEY_CHAN3;
+		break;
+	case POKEY_OFFSET_AUDF4:
+		/* POKEY_AUDF[POKEY_CHAN4 + chip_offs] = val; */
+		chan_mask = 1 << POKEY_CHAN4;
+		break;
+	case POKEY_OFFSET_AUDC4:
+		/* POKEY_AUDC[POKEY_CHAN4 + chip_offs] = val; */
+		pokeysnd_AUDV[POKEY_CHAN4 + chip_offs] = (val & POKEY_VOLUME_MASK) * gain;
+		chan_mask = 1 << POKEY_CHAN4;
+		break;
+	case POKEY_OFFSET_AUDCTL:
+		/* POKEY_AUDCTL[chip] = val; */
+		chan_mask = 15;			/* all channels */
+		break;
+	default:
+		chan_mask = 0;
+		break;
+	}
+
+	/************************************************************/
+	/* As defined in the manual, the exact Div_n_cnt values are */
+	/* different depending on the frequency and resolution:     */
+	/*    64 kHz or 15 kHz - AUDF + 1                           */
+	/*    1 MHz, 8-bit -     AUDF + 4                           */
+	/*    1 MHz, 16-bit -    POKEY_AUDF[POKEY_CHAN1]+256*POKEY_AUDF[POKEY_CHAN2] + 7    */
+	/************************************************************/
+
+	/* only reset the channels that have changed */
+
+	if (chan_mask & (1 << POKEY_CHAN1)) {
+		/* process channel 1 frequency */
+		if (POKEY_AUDCTL[chip] & POKEY_CH1_179)
+			new_val = POKEY_AUDF[POKEY_CHAN1 + chip_offs] + 4;
+		else
+			new_val = (POKEY_AUDF[POKEY_CHAN1 + chip_offs] + 1) * POKEY_Base_mult[chip];
+
+		if (new_val != Div_n_max[POKEY_CHAN1 + chip_offs]) {
+			Div_n_max[POKEY_CHAN1 + chip_offs] = new_val;
+
+			if (Div_n_cnt[POKEY_CHAN1 + chip_offs] > new_val) {
+				Div_n_cnt[POKEY_CHAN1 + chip_offs] = new_val;
+			}
+		}
+	}
+
+	if (chan_mask & (1 << POKEY_CHAN2)) {
+		/* process channel 2 frequency */
+		if (POKEY_AUDCTL[chip] & POKEY_CH1_CH2) {
+			if (POKEY_AUDCTL[chip] & POKEY_CH1_179)
+				new_val = POKEY_AUDF[POKEY_CHAN2 + chip_offs] * 256 +
+					POKEY_AUDF[POKEY_CHAN1 + chip_offs] + 7;
+			else
+				new_val = (POKEY_AUDF[POKEY_CHAN2 + chip_offs] * 256 +
+						   POKEY_AUDF[POKEY_CHAN1 + chip_offs] + 1) * POKEY_Base_mult[chip];
+		}
+		else
+			new_val = (POKEY_AUDF[POKEY_CHAN2 + chip_offs] + 1) * POKEY_Base_mult[chip];
+
+		if (new_val != Div_n_max[POKEY_CHAN2 + chip_offs]) {
+			Div_n_max[POKEY_CHAN2 + chip_offs] = new_val;
+
+			if (Div_n_cnt[POKEY_CHAN2 + chip_offs] > new_val) {
+				Div_n_cnt[POKEY_CHAN2 + chip_offs] = new_val;
+			}
+		}
+	}
+
+	if (chan_mask & (1 << POKEY_CHAN3)) {
+		/* process channel 3 frequency */
+		if (POKEY_AUDCTL[chip] & POKEY_CH3_179)
+			new_val = POKEY_AUDF[POKEY_CHAN3 + chip_offs] + 4;
+		else
+			new_val = (POKEY_AUDF[POKEY_CHAN3 + chip_offs] + 1) * POKEY_Base_mult[chip];
+
+		if (new_val != Div_n_max[POKEY_CHAN3 + chip_offs]) {
+			Div_n_max[POKEY_CHAN3 + chip_offs] = new_val;
+
+			if (Div_n_cnt[POKEY_CHAN3 + chip_offs] > new_val) {
+				Div_n_cnt[POKEY_CHAN3 + chip_offs] = new_val;
+			}
+		}
+	}
+
+	if (chan_mask & (1 << POKEY_CHAN4)) {
+		/* process channel 4 frequency */
+		if (POKEY_AUDCTL[chip] & POKEY_CH3_CH4) {
+			if (POKEY_AUDCTL[chip] & POKEY_CH3_179)
+				new_val = POKEY_AUDF[POKEY_CHAN4 + chip_offs] * 256 +
+					POKEY_AUDF[POKEY_CHAN3 + chip_offs] + 7;
+			else
+				new_val = (POKEY_AUDF[POKEY_CHAN4 + chip_offs] * 256 +
+						   POKEY_AUDF[POKEY_CHAN3 + chip_offs] + 1) * POKEY_Base_mult[chip];
+		}
+		else
+			new_val = (POKEY_AUDF[POKEY_CHAN4 + chip_offs] + 1) * POKEY_Base_mult[chip];
+
+		if (new_val != Div_n_max[POKEY_CHAN4 + chip_offs]) {
+			Div_n_max[POKEY_CHAN4 + chip_offs] = new_val;
+
+			if (Div_n_cnt[POKEY_CHAN4 + chip_offs] > new_val) {
+				Div_n_cnt[POKEY_CHAN4 + chip_offs] = new_val;
+			}
+		}
+	}
+
+	/* if channel is volume only, set current output */
+	for (chan = POKEY_CHAN1; chan <= POKEY_CHAN4; chan++) {
+		if (chan_mask & (1 << chan)) {
+
+#ifdef VOL_ONLY_SOUND
+
+#ifdef __PLUS
+			if (g_Sound.nDigitized)
+#endif
+			if ((POKEY_AUDC[chan + chip_offs] & POKEY_VOL_ONLY)) {
+
+#ifdef STEREO_SOUND
+
+#ifdef __PLUS
+				if (POKEYSND_stereo_enabled && chip & 0x01)
+#else
+				if (chip & 0x01)
+#endif
+				{
+					sampbuf_lastval2 += pokeysnd_AUDV[chan + chip_offs]
+						- POKEYSND_sampbuf_AUDV[chan + chip_offs];
+
+					sampbuf_val2[sampbuf_ptr2] = sampbuf_lastval2;
+					POKEYSND_sampbuf_AUDV[chan + chip_offs] = pokeysnd_AUDV[chan + chip_offs];
+					sampbuf_cnt2[sampbuf_ptr2] =
+						(ANTIC_CPU_CLOCK - sampbuf_last2) * 128 * POKEYSND_samp_freq / 178979;
+					sampbuf_last2 = ANTIC_CPU_CLOCK;
+					sampbuf_ptr2++;
+					if (sampbuf_ptr2 >= POKEYSND_SAMPBUF_MAX)
+						sampbuf_ptr2 = 0;
+					if (sampbuf_ptr2 == sampbuf_rptr2) {
+						sampbuf_rptr2++;
+						if (sampbuf_rptr2 >= POKEYSND_SAMPBUF_MAX)
+							sampbuf_rptr2 = 0;
+					}
+				}
+				else
+#endif /* STEREO_SOUND */
+				{
+					POKEYSND_sampbuf_lastval += pokeysnd_AUDV[chan + chip_offs]
+						-POKEYSND_sampbuf_AUDV[chan + chip_offs];
+
+					POKEYSND_sampbuf_val[POKEYSND_sampbuf_ptr] = POKEYSND_sampbuf_lastval;
+					POKEYSND_sampbuf_AUDV[chan + chip_offs] = pokeysnd_AUDV[chan + chip_offs];
+					POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_ptr] =
+						(ANTIC_CPU_CLOCK - POKEYSND_sampbuf_last) * 128 * POKEYSND_samp_freq / 178979;
+					POKEYSND_sampbuf_last = ANTIC_CPU_CLOCK;
+					POKEYSND_sampbuf_ptr++;
+					if (POKEYSND_sampbuf_ptr >= POKEYSND_SAMPBUF_MAX)
+						POKEYSND_sampbuf_ptr = 0;
+					if (POKEYSND_sampbuf_ptr == POKEYSND_sampbuf_rptr) {
+						POKEYSND_sampbuf_rptr++;
+						if (POKEYSND_sampbuf_rptr >= POKEYSND_SAMPBUF_MAX)
+							POKEYSND_sampbuf_rptr = 0;
+					}
+				}
+			}
+
+#endif /* VOL_ONLY_SOUND */
+
+			/* I've disabled any frequencies that exceed the sampling
+			   frequency.  There isn't much point in processing frequencies
+			   that the hardware can't reproduce.  I've also disabled
+			   processing if the volume is zero. */
+
+			/* if the channel is volume only */
+			/* or the channel is off (volume == 0) */
+			/* or the channel freq is greater than the playback freq */
+			if ( (POKEY_AUDC[chan + chip_offs] & POKEY_VOL_ONLY) ||
+				((POKEY_AUDC[chan + chip_offs] & POKEY_VOLUME_MASK) == 0)
+				|| (!BIENIAS_FIX && (Div_n_max[chan + chip_offs] < (Samp_n_max >> 8)))
+				) {
+				/* indicate the channel is 'on' */
+				Outvol[chan + chip_offs] = 1;
+
+				/* can only ignore channel if filtering off */
+				if ((chan == POKEY_CHAN3 && !(POKEY_AUDCTL[chip] & POKEY_CH1_FILTER)) ||
+					(chan == POKEY_CHAN4 && !(POKEY_AUDCTL[chip] & POKEY_CH2_FILTER)) ||
+					(chan == POKEY_CHAN1) ||
+					(chan == POKEY_CHAN2)
+					|| (!BIENIAS_FIX && (Div_n_max[chan + chip_offs] < (Samp_n_max >> 8)))
+				) {
+					/* and set channel freq to max to reduce processing */
+					Div_n_max[chan + chip_offs] = 0x7fffffffL;
+					Div_n_cnt[chan + chip_offs] = 0x7fffffffL;
+				}
+			}
+		}
+	}
+
+	/*    _enable(); */ /* RSF - removed for portability 31-MAR-97 */
+}
+
+
+/*****************************************************************************/
+/* Module:  pokeysnd_process()                                                  */
+/* Purpose: To fill the output buffer with the sound output based on the     */
+/*          pokey chip parameters.                                           */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    January 1, 1997                                                  */
+/*                                                                           */
+/* Inputs:  *buffer - pointer to the buffer where the audio output will      */
+/*                    be placed                                              */
+/*          sndn - for mono, size of the playback buffer in samples          */
+/*                 for stereo, size of the playback buffer in left samples   */
+/*                    plus right samples.                                    */
+/*          num_pokeys - number of currently active pokeys to process        */
+/*                                                                           */
+/* Outputs: the buffer will be filled with n bytes of audio - no return val  */
+/*          Also the buffer will be written to disk if Sound recording is ON */
+/*                                                                           */
+/*****************************************************************************/
+
+static void pokeysnd_process_8(void *sndbuffer, int sndn)
+{
+	register UBYTE *buffer = (UBYTE *) sndbuffer;
+	register int n = sndn;
+
+	register ULONG *div_n_ptr;
+	register UBYTE *samp_cnt_w_ptr;
+	register ULONG event_min;
+	register UBYTE next_event;
+#ifdef CLIP_SOUND
+	register SWORD cur_val;		/* then we have to count as 16-bit signed */
+#ifdef STEREO_SOUND
+	register SWORD cur_val2;
+#endif
+#else /* CLIP_SOUND */
+	register UBYTE cur_val;		/* otherwise we'll simplify as 8-bit unsigned */
+#ifdef STEREO_SOUND
+	register UBYTE cur_val2;
+#endif
+#endif /* CLIP_SOUND */
+	register UBYTE *out_ptr;
+	register UBYTE audc;
+	register UBYTE toggle;
+	register UBYTE count;
+	register UBYTE *vol_ptr;
+
+	/* set a pointer to the whole portion of the samp_n_cnt */
+#ifdef WORDS_BIGENDIAN
+	samp_cnt_w_ptr = ((UBYTE *) (&Samp_n_cnt[0]) + 3);
+#else
+	samp_cnt_w_ptr = ((UBYTE *) (&Samp_n_cnt[0]) + 1);
+#endif
+
+	/* set a pointer for optimization */
+	out_ptr = Outvol;
+	vol_ptr = pokeysnd_AUDV;
+
+	/* The current output is pre-determined and then adjusted based on each */
+	/* output change for increased performance (less over-all math). */
+	/* add the output values of all 4 channels */
+	cur_val = POKEYSND_SAMP_MIN;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+	if (POKEYSND_stereo_enabled)
+#endif
+	cur_val2 = POKEYSND_SAMP_MIN;
+#endif /* STEREO_SOUND */
+
+	count = Num_pokeys;
+	do {
+		if (*out_ptr++)
+			cur_val += *vol_ptr;
+		vol_ptr++;
+
+		if (*out_ptr++)
+			cur_val += *vol_ptr;
+		vol_ptr++;
+
+		if (*out_ptr++)
+			cur_val += *vol_ptr;
+		vol_ptr++;
+
+		if (*out_ptr++)
+			cur_val += *vol_ptr;
+		vol_ptr++;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+		if (POKEYSND_stereo_enabled)
+#endif
+		{
+			count--;
+			if (count) {
+				if (*out_ptr++)
+					cur_val2 += *vol_ptr;
+				vol_ptr++;
+
+				if (*out_ptr++)
+					cur_val2 += *vol_ptr;
+				vol_ptr++;
+
+				if (*out_ptr++)
+					cur_val2 += *vol_ptr;
+				vol_ptr++;
+
+				if (*out_ptr++)
+					cur_val2 += *vol_ptr;
+				vol_ptr++;
+			}
+			else
+				break;
+		}
+#endif /* STEREO_SOUND */
+		count--;
+	} while (count);
+
+#ifdef SYNCHRONIZED_SOUND
+	cur_val += speaker;
+#endif
+
+	/* loop until the buffer is filled */
+	while (n) {
+		/* Normally the routine would simply decrement the 'div by N' */
+		/* counters and react when they reach zero.  Since we normally */
+		/* won't be processing except once every 80 or so counts, */
+		/* I've optimized by finding the smallest count and then */
+		/* 'accelerated' time by adjusting all pointers by that amount. */
+
+		/* find next smallest event (either sample or chan 1-4) */
+		next_event = POKEY_SAMPLE;
+		event_min = READ_U32(samp_cnt_w_ptr);
+
+		div_n_ptr = Div_n_cnt;
+
+		count = 0;
+		do {
+			/* Though I could have used a loop here, this is faster */
+			if (*div_n_ptr <= event_min) {
+				event_min = *div_n_ptr;
+				next_event = POKEY_CHAN1 + (count << 2);
+			}
+			div_n_ptr++;
+			if (*div_n_ptr <= event_min) {
+				event_min = *div_n_ptr;
+				next_event = POKEY_CHAN2 + (count << 2);
+			}
+			div_n_ptr++;
+			if (*div_n_ptr <= event_min) {
+				event_min = *div_n_ptr;
+				next_event = POKEY_CHAN3 + (count << 2);
+			}
+			div_n_ptr++;
+			if (*div_n_ptr <= event_min) {
+				event_min = *div_n_ptr;
+				next_event = POKEY_CHAN4 + (count << 2);
+			}
+			div_n_ptr++;
+
+			count++;
+		} while (count < Num_pokeys);
+
+		/* if the next event is a channel change */
+		if (next_event != POKEY_SAMPLE) {
+			/* shift the polynomial counters */
+
+			count = Num_pokeys;
+			do {
+				/* decrement all counters by the smallest count found */
+				/* again, no loop for efficiency */
+				div_n_ptr--;
+				*div_n_ptr -= event_min;
+				div_n_ptr--;
+				*div_n_ptr -= event_min;
+				div_n_ptr--;
+				*div_n_ptr -= event_min;
+				div_n_ptr--;
+				*div_n_ptr -= event_min;
+
+				count--;
+			} while (count);
+
+
+			WRITE_U32(samp_cnt_w_ptr, READ_U32(samp_cnt_w_ptr) - event_min);
+
+			/* since the polynomials require a mod (%) function which is
+			   division, I don't adjust the polynomials on the SAMPLE events,
+			   only the CHAN events.  I have to keep track of the change,
+			   though. */
+
+			P4 = (P4 + event_min) % POKEY_POLY4_SIZE;
+			P5 = (P5 + event_min) % POKEY_POLY5_SIZE;
+			P9 = (P9 + event_min) % POKEY_POLY9_SIZE;
+			P17 = (P17 + event_min) % POKEY_POLY17_SIZE;
+
+			/* adjust channel counter */
+			Div_n_cnt[next_event] += Div_n_max[next_event];
+
+			/* get the current AUDC into a register (for optimization) */
+			audc = POKEY_AUDC[next_event];
+
+			/* set a pointer to the current output (for opt...) */
+			out_ptr = &Outvol[next_event];
+
+			/* assume no changes to the output */
+			toggle = FALSE;
+
+			/* From here, a good understanding of the hardware is required */
+			/* to understand what is happening.  I won't be able to provide */
+			/* much description to explain it here. */
+
+			/* if VOLUME only then nothing to process */
+			if (!(audc & POKEY_VOL_ONLY)) {
+				/* if the output is pure or the output is poly5 and the poly5 bit */
+				/* is set */
+				if ((audc & POKEY_NOTPOLY5) || bit5[P5]) {
+					/* if the PURETONE bit is set */
+					if (audc & POKEY_PURETONE) {
+						/* then simply toggle the output */
+						toggle = TRUE;
+					}
+					/* otherwise if POLY4 is selected */
+					else if (audc & POKEY_POLY4) {
+						/* then compare to the poly4 bit */
+						toggle = (bit4[P4] == !(*out_ptr));
+					}
+					else {
+						/* if 9-bit poly is selected on this chip */
+						if (POKEY_AUDCTL[next_event >> 2] & POKEY_POLY9) {
+							/* compare to the poly9 bit */
+							toggle = ((POKEY_poly9_lookup[P9] & 1) == !(*out_ptr));
+						}
+						else {
+							/* otherwise compare to the poly17 bit */
+							toggle = (((POKEY_poly17_lookup[P17 >> 3] >> (P17 & 7)) & 1) == !(*out_ptr));
+						}
+					}
+				}
+			}
+
+			/* check channel 1 filter (clocked by channel 3) */
+			if ( POKEY_AUDCTL[next_event >> 2] & POKEY_CH1_FILTER) {
+				/* if we're processing channel 3 */
+				if ((next_event & 0x03) == POKEY_CHAN3) {
+					/* check output of channel 1 on same chip */
+					if (Outvol[next_event & 0xfd]) {
+						/* if on, turn it off */
+						Outvol[next_event & 0xfd] = 0;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+						if (POKEYSND_stereo_enabled && (next_event & 0x04))
+#else
+						if ((next_event & 0x04))
+#endif
+							cur_val2 -= pokeysnd_AUDV[next_event & 0xfd];
+						else
+#endif /* STEREO_SOUND */
+							cur_val -= pokeysnd_AUDV[next_event & 0xfd];
+					}
+				}
+			}
+
+			/* check channel 2 filter (clocked by channel 4) */
+			if ( POKEY_AUDCTL[next_event >> 2] & POKEY_CH2_FILTER) {
+				/* if we're processing channel 4 */
+				if ((next_event & 0x03) == POKEY_CHAN4) {
+					/* check output of channel 2 on same chip */
+					if (Outvol[next_event & 0xfd]) {
+						/* if on, turn it off */
+						Outvol[next_event & 0xfd] = 0;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+						if (POKEYSND_stereo_enabled && (next_event & 0x04))
+#else
+						if ((next_event & 0x04))
+#endif
+							cur_val2 -= pokeysnd_AUDV[next_event & 0xfd];
+						else
+#endif /* STEREO_SOUND */
+							cur_val -= pokeysnd_AUDV[next_event & 0xfd];
+					}
+				}
+			}
+
+			/* if the current output bit has changed */
+			if (toggle) {
+				if (*out_ptr) {
+					/* remove this channel from the signal */
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+					if (POKEYSND_stereo_enabled && (next_event & 0x04))
+#else
+					if ((next_event & 0x04))
+#endif
+						cur_val2 -= pokeysnd_AUDV[next_event];
+					else
+#endif /* STEREO_SOUND */
+						cur_val -= pokeysnd_AUDV[next_event];
+
+					/* and turn the output off */
+					*out_ptr = 0;
+				}
+				else {
+					/* turn the output on */
+					*out_ptr = 1;
+
+					/* and add it to the output signal */
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+					if (POKEYSND_stereo_enabled && (next_event & 0x04))
+#else
+					if ((next_event & 0x04))
+#endif
+						cur_val2 += pokeysnd_AUDV[next_event];
+					else
+#endif /* STEREO_SOUND */
+						cur_val += pokeysnd_AUDV[next_event];
+				}
+			}
+		}
+		else {					/* otherwise we're processing a sample */
+			/* adjust the sample counter - note we're using the 24.8 integer
+			   which includes an 8 bit fraction for accuracy */
+
+			int iout;
+#ifdef STEREO_SOUND
+			int iout2;
+#endif
+#ifdef INTERPOLATE_SOUND
+			if (cur_val != last_val) {
+				if (*Samp_n_cnt < Samp_n_max) {		/* need interpolation */
+#ifdef CLIP_SOUND
+					iout = (cur_val * (SLONG)(*Samp_n_cnt) +
+							last_val * (SLONG)(Samp_n_max - *Samp_n_cnt))
+						/ (SLONG)Samp_n_max;
+#else
+					iout = (cur_val * (*Samp_n_cnt) +
+							last_val * (Samp_n_max - *Samp_n_cnt))
+						/ Samp_n_max;
+#endif
+				}
+				else
+					iout = cur_val;
+				last_val = cur_val;
+			}
+			else
+				iout = cur_val;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+		if (POKEYSND_stereo_enabled)
+#endif
+			if (cur_val2 != last_val2) {
+				if (*Samp_n_cnt < Samp_n_max) {		/* need interpolation */
+#ifdef CLIP_SOUND
+					iout2 = (cur_val2 * (SLONG)(*Samp_n_cnt) +
+							last_val2 * (SLONG)(Samp_n_max - *Samp_n_cnt))
+						/ (SLONG)Samp_n_max;
+#else
+					iout2 = (cur_val2 * (*Samp_n_cnt) +
+							last_val2 * (Samp_n_max - *Samp_n_cnt))
+						/ Samp_n_max;
+#endif
+				}
+				else
+					iout2 = cur_val2;
+				last_val2 = cur_val2;
+			}
+			else
+				iout2 = cur_val2;
+#endif  /* STEREO_SOUND */
+#else   /* INTERPOLATE_SOUND */
+			iout = cur_val;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+		if (POKEYSND_stereo_enabled)
+#endif
+			iout2 = cur_val2;
+#endif  /* STEREO_SOUND */
+#endif  /* INTERPOLATE_SOUND */
+
+#ifdef VOL_ONLY_SOUND
+#ifdef __PLUS
+			if (g_Sound.nDigitized)
+#endif
+			{
+				if (POKEYSND_sampbuf_rptr != POKEYSND_sampbuf_ptr) {
+					int l;
+					if (POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_rptr] > 0)
+						POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_rptr] -= 1280;
+					while ((l = POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_rptr]) <= 0) {
+						POKEYSND_sampout = POKEYSND_sampbuf_val[POKEYSND_sampbuf_rptr];
+						POKEYSND_sampbuf_rptr++;
+						if (POKEYSND_sampbuf_rptr >= POKEYSND_SAMPBUF_MAX)
+							POKEYSND_sampbuf_rptr = 0;
+						if (POKEYSND_sampbuf_rptr != POKEYSND_sampbuf_ptr)
+							POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_rptr] += l;
+						else
+							break;
+					}
+				}
+				iout += POKEYSND_sampout;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+				if (POKEYSND_stereo_enabled)
+#endif
+				{
+					if (sampbuf_rptr2 != sampbuf_ptr2) {
+						int l;
+						if (sampbuf_cnt2[sampbuf_rptr2] > 0)
+							sampbuf_cnt2[sampbuf_rptr2] -= 1280;
+						while ((l = sampbuf_cnt2[sampbuf_rptr2]) <= 0) {
+							sampout2 = sampbuf_val2[sampbuf_rptr2];
+							sampbuf_rptr2++;
+							if (sampbuf_rptr2 >= POKEYSND_SAMPBUF_MAX)
+								sampbuf_rptr2 = 0;
+							if (sampbuf_rptr2 != sampbuf_ptr2)
+								sampbuf_cnt2[sampbuf_rptr2] += l;
+							else
+								break;
+						}
+					}
+					iout2 += sampout2;
+				}
+#endif  /* STEREO_SOUND */
+			}
+#endif  /* VOL_ONLY_SOUND */
+
+#ifdef CLIP_SOUND
+			if (iout > POKEYSND_SAMP_MAX) {	/* then check high limit */
+				*buffer++ = (UBYTE) POKEYSND_SAMP_MAX;	/* and limit if greater */
+			}
+			else if (iout < POKEYSND_SAMP_MIN) {		/* else check low limit */
+				*buffer++ = (UBYTE) POKEYSND_SAMP_MIN;	/* and limit if less */
+			}
+			else {				/* otherwise use raw value */
+				*buffer++ = (UBYTE) iout;
+			}
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+			if (POKEYSND_stereo_enabled) {
+				if (iout2 > POKEYSND_SAMP_MAX)
+					*buffer++ = (UBYTE) POKEYSND_SAMP_MAX;
+				else if (iout2 < POKEYSND_SAMP_MIN)
+					*buffer++ = (UBYTE) POKEYSND_SAMP_MIN;
+				else
+					*buffer++ = (UBYTE) iout2;
+			}
+#else /* __PLUS */
+			if (Num_pokeys > 1) {
+				if ((POKEYSND_stereo_enabled ? iout2 : iout) > POKEYSND_SAMP_MAX) {	/* then check high limit */
+					*buffer++ = (UBYTE) POKEYSND_SAMP_MAX;	/* and limit if greater */
+				}
+				else if ((POKEYSND_stereo_enabled ? iout2 : iout) < POKEYSND_SAMP_MIN) {		/* else check low limit */
+					*buffer++ = (UBYTE) POKEYSND_SAMP_MIN;	/* and limit if less */
+				}
+				else {				/* otherwise use raw value */
+					*buffer++ = (UBYTE) (POKEYSND_stereo_enabled ? iout2 : iout);
+				}
+			}
+#endif /* __PLUS */
+#endif /* STEREO_SOUND */
+#else /* CLIP_SOUND */
+			*buffer++ = (UBYTE) iout;	/* clipping not selected, use value */
+#ifdef STEREO_SOUND
+			if (Num_pokeys > 1)
+#ifdef ASAP
+				*buffer++ = (UBYTE) iout2;
+#else
+				*buffer++ = (UBYTE) (POKEYSND_stereo_enabled ? iout2 : iout);
+#endif
+#endif /* STEREO_SOUND */
+#endif /* CLIP_SOUND */
+
+#ifdef WORDS_BIGENDIAN
+			*(Samp_n_cnt + 1) += Samp_n_max;
+#else
+			*Samp_n_cnt += Samp_n_max;
+#endif
+			/* and indicate one less byte in the buffer */
+			n--;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+			if (POKEYSND_stereo_enabled)
+#endif
+			if (Num_pokeys > 1)
+				n--;
+#endif
+		}
+	}
+#ifdef VOL_ONLY_SOUND
+#ifdef __PLUS
+	if (g_Sound.nDigitized)
+#endif
+	{
+		if (POKEYSND_sampbuf_rptr == POKEYSND_sampbuf_ptr)
+			POKEYSND_sampbuf_last = ANTIC_CPU_CLOCK;
+#ifdef STEREO_SOUND
+#ifdef __PLUS
+	if (POKEYSND_stereo_enabled)
+#endif
+		if (sampbuf_rptr2 == sampbuf_ptr2)
+			sampbuf_last2 = ANTIC_CPU_CLOCK;
+#endif /* STEREO_SOUND */
+	}
+#endif  /* VOL_ONLY_SOUND */
+}
+
+#ifdef SERIO_SOUND
+static void Update_serio_sound_rf(int out, UBYTE data)
+{
+#ifdef VOL_ONLY_SOUND
+#ifdef __PLUS
+	if (g_Sound.nDigitized) {
+#endif
+	int bits, pv, future;
+	if (!POKEYSND_serio_sound_enabled) return;
+
+	pv = 0;
+	future = 0;
+	bits = (data << 1) | 0x200;
+	while (bits)
+	{
+		POKEYSND_sampbuf_lastval -= pv;
+		pv = (bits & 0x01) * pokeysnd_AUDV[3];	/* FIXME!!! - set volume from AUDV */
+		POKEYSND_sampbuf_lastval += pv;
+
+	POKEYSND_sampbuf_val[POKEYSND_sampbuf_ptr] = POKEYSND_sampbuf_lastval;
+	POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_ptr] =
+		(ANTIC_CPU_CLOCK + future-POKEYSND_sampbuf_last) * 128 * POKEYSND_samp_freq / 178979;
+	POKEYSND_sampbuf_last = ANTIC_CPU_CLOCK + future;
+	POKEYSND_sampbuf_ptr++;
+	if (POKEYSND_sampbuf_ptr >= POKEYSND_SAMPBUF_MAX )
+		POKEYSND_sampbuf_ptr = 0;
+	if (POKEYSND_sampbuf_ptr == POKEYSND_sampbuf_rptr ) {
+		POKEYSND_sampbuf_rptr++;
+		if (POKEYSND_sampbuf_rptr >= POKEYSND_SAMPBUF_MAX)
+			POKEYSND_sampbuf_rptr = 0;
+	}
+		/* 1789790/19200 = 93 */
+		future += 93;	/* ~ 19200 bit/s - FIXME!!! set speed form AUDF [2] ??? */
+		bits >>= 1;
+	}
+	POKEYSND_sampbuf_lastval -= pv;
+#ifdef __PLUS
+	}
+#endif
+#endif  /* VOL_ONLY_SOUND */
+}
+#endif /* SERIO_SOUND */
+
+void POKEYSND_SetVolume(int vol)
+{
+    if (vol > 100)
+        vol = 100;
+    if (vol < 0)
+        vol = 0;
+
+    POKEYSND_volume = vol * 0x100 / 100;
+}
+
+static void pokeysnd_process_16(void *sndbuffer, int sndn)
+{
+	short *buffer = (UWORD *) sndbuffer;
+	int i;
+
+	pokeysnd_process_8(buffer, sndn);
+
+	for (i = sndn - 1; i >= 0; i--) {
+#ifndef POKEYSND_SIGNED_SAMPLES
+		int smp = ((int) (((UBYTE *) buffer)[i]) - 0x80) * POKEYSND_volume;
+#else
+		int smp = ((int) ((SBYTE *) buffer)[i]) * POKEYSND_volume;
+#endif
+		if (smp > 32767)
+			smp = 32767;
+		else if (smp < -32768)
+			smp = -32768;
+
+		buffer[i] = smp;
+	}
+ 
+}
+
+#ifdef SYNCHRONIZED_SOUND
+static void Generate_sync_rf(unsigned int num_ticks)
+{
+	double new_samp_pos;
+	unsigned int ticks;
+	UBYTE *buffer = POKEYSND_process_buffer + POKEYSND_process_buffer_fill;
+	UBYTE *buffer_end = POKEYSND_process_buffer + POKEYSND_process_buffer_length;
+
+	for (;;) {
+		double int_part;
+		new_samp_pos = samp_pos + ticks_per_sample;
+		new_samp_pos = modf(new_samp_pos, &int_part);
+		ticks = (unsigned int)int_part;
+		if (ticks > num_ticks) {
+			samp_pos -= num_ticks;
+			break;
+		}
+		if (buffer >= buffer_end)
+			break;
+
+		samp_pos = new_samp_pos;
+		num_ticks -= ticks;
+
+		if (POKEYSND_snd_flags & POKEYSND_BIT16) {
+			pokeysnd_process_16(buffer, POKEYSND_num_pokeys);
+			buffer += 2 * POKEYSND_num_pokeys;
+		}
+		else {
+			pokeysnd_process_8(buffer, POKEYSND_num_pokeys);
+			buffer += POKEYSND_num_pokeys;
+		}
+
+	}
+
+	POKEYSND_process_buffer_fill = buffer - POKEYSND_process_buffer;
+}
+#endif /* SYNCHRONIZED_SOUND */
+
+#ifdef CONSOLE_SOUND
+void POKEYSND_UpdateConsol(int set)
+{
+	if (!POKEYSND_console_sound_enabled)
+		return;
+#ifdef SYNCHRONIZED_SOUND
+	if (set)
+		Update_synchronized_sound();
+#endif /* SYNCHRONIZED_SOUND */
+	POKEYSND_UpdateConsol_ptr(set);
+}
+
+static void Update_consol_sound_rf(int set)
+{
+#ifdef SYNCHRONIZED_SOUND
+	if (set)
+		speaker = CONSOLE_VOL * GTIA_speaker;
+#elif defined(VOL_ONLY_SOUND)
+	static int prev_atari_speaker = 0;
+	static unsigned int prev_cpu_clock = 0;
+	int d;
+#ifdef __PLUS
+	if (!g_Sound.nDigitized)
+		return;
+#endif
+
+	if (!set && POKEYSND_samp_consol_val == 0)
+		return;
+	POKEYSND_sampbuf_lastval -= POKEYSND_samp_consol_val;
+	if (prev_atari_speaker != GTIA_speaker) {
+		POKEYSND_samp_consol_val = GTIA_speaker * 8 * 4;	/* gain */
+		prev_cpu_clock = ANTIC_CPU_CLOCK;
+	}
+	else if (!set) {
+		d = ANTIC_CPU_CLOCK - prev_cpu_clock;
+		if (d < 114) {
+			POKEYSND_sampbuf_lastval += POKEYSND_samp_consol_val;
+			return;
+		}
+		while (d >= 114 /* CPUL */) {
+			POKEYSND_samp_consol_val = POKEYSND_samp_consol_val * 99 / 100;
+			d -= 114;
+		}
+		prev_cpu_clock = ANTIC_CPU_CLOCK - d;
+	}
+	POKEYSND_sampbuf_lastval += POKEYSND_samp_consol_val;
+	prev_atari_speaker = GTIA_speaker;
+
+	POKEYSND_sampbuf_val[POKEYSND_sampbuf_ptr] = POKEYSND_sampbuf_lastval;
+	POKEYSND_sampbuf_cnt[POKEYSND_sampbuf_ptr] =
+		(ANTIC_CPU_CLOCK - POKEYSND_sampbuf_last) * 128 * POKEYSND_samp_freq / 178979;
+	POKEYSND_sampbuf_last = ANTIC_CPU_CLOCK;
+	POKEYSND_sampbuf_ptr++;
+	if (POKEYSND_sampbuf_ptr >= POKEYSND_SAMPBUF_MAX)
+		POKEYSND_sampbuf_ptr = 0;
+	if (POKEYSND_sampbuf_ptr == POKEYSND_sampbuf_rptr) {
+		POKEYSND_sampbuf_rptr++;
+		if (POKEYSND_sampbuf_rptr >= POKEYSND_SAMPBUF_MAX)
+			POKEYSND_sampbuf_rptr = 0;
+	}
+#endif /* !SYNCHRONIZED_SOUND && VOL_ONLY_SOUND */
+}
+#endif /* CONSOLE_SOUND */
+
+#ifdef VOL_ONLY_SOUND
+static void Update_vol_only_sound_rf(void)
+{
+#ifdef CONSOLE_SOUND
+	POKEYSND_UpdateConsol(0);	/* mmm */
+#endif /* CONSOLE_SOUND */
+}
+#endif  /* VOL_ONLY_SOUND */
diff --git a/MCUME_pico2/pico800/pokeysnd.h b/MCUME_pico2/pico800/pokeysnd.h
new file mode 100644
index 0000000..64f5cd6
--- /dev/null
+++ b/MCUME_pico2/pico800/pokeysnd.h
@@ -0,0 +1,144 @@
+/*****************************************************************************/
+/*                                                                           */
+/* Module:  POKEY Chip Simulator Includes, V2.3                              */
+/* Purpose: To emulate the sound generation hardware of the Atari POKEY chip. */
+/* Author:  Ron Fries                                                        */
+/*                                                                           */
+/* Revision History:                                                         */
+/*                                                                           */
+/* 09/22/96 - Ron Fries - Initial Release                                    */
+/* 04/06/97 - Brad Oliver - Some cross-platform modifications. Added         */
+/*                          big/little endian #defines, removed <dos.h>,     */
+/*                          conditional defines for TRUE/FALSE               */
+/* 01/19/98 - Ron Fries - Changed signed/unsigned sample support to a        */
+/*                        compile-time option.  Defaults to unsigned -       */
+/*                        define SIGNED_SAMPLES to create signed.            */
+/*                                                                           */
+/*****************************************************************************/
+/*                                                                           */
+/*                 License Information and Copyright Notice                  */
+/*                 ========================================                  */
+/*                                                                           */
+/* PokeySound is Copyright(c) 1996-1998 by Ron Fries                         */
+/*                                                                           */
+/* This library is free software; you can redistribute it and/or modify it   */
+/* under the terms of version 2 of the GNU Library General Public License    */
+/* as published by the Free Software Foundation.                             */
+/*                                                                           */
+/* This library is distributed in the hope that it will be useful, but       */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of                */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Library */
+/* General Public License for more details.                                  */
+/* To obtain a copy of the GNU Library General Public License, write to the  */
+/* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.   */
+/*                                                                           */
+/* Any permitted reproduction of these routines, in whole or in part, must   */
+/* bear this legend.                                                         */
+/*                                                                           */
+/*****************************************************************************/
+
+#ifndef POKEYSND_H_
+#define POKEYSND_H_
+
+#include "atari.h"
+#include "pokey.h"
+
+/* CONSTANT DEFINITIONS */
+
+/* As an alternative to using the exact frequencies, selecting a playback
+   frequency that is an exact division of the main clock provides a higher
+   quality output due to less aliasing.  For best results, a value of
+   1787520 MHz is used for the main clock.  With this value, both the
+   64 kHz and 15 kHz clocks are evenly divisible.  Selecting a playback
+   frequency that is also a division of the clock provides the best
+   results.  The best options are FREQ_64 divided by either 2, 3, or 4.
+   The best selection is based on a trade off between performance and
+   sound quality.
+
+   Of course, using a main clock frequency that is not exact will affect
+   the pitch of the output.  With these numbers, the pitch will be low
+   by 0.127%.  (More than likely, an actual unit will vary by this much!) */
+
+#define POKEYSND_FREQ_17_EXACT     1789790	/* exact 1.79 MHz clock freq */
+#define POKEYSND_FREQ_17_APPROX    1787520	/* approximate 1.79 MHz clock freq */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef  POKEYSND_SIGNED_SAMPLES			/* if signed output selected */
+#define POKEYSND_SAMP_MAX 127			/* then set signed 8-bit clipping ranges */
+#define POKEYSND_SAMP_MIN -128
+#define POKEYSND_SAMP_MID 0
+#else
+#define POKEYSND_SAMP_MAX 255			/* else set unsigned 8-bit clip ranges */
+#define POKEYSND_SAMP_MIN 0
+#define POKEYSND_SAMP_MID 128
+#endif
+
+/* init flags */
+#define POKEYSND_BIT16	1
+
+extern SLONG POKEYSND_playback_freq;
+extern UBYTE POKEYSND_num_pokeys;
+extern int POKEYSND_snd_flags;
+extern int POKEYSND_volume;
+
+extern int POKEYSND_enable_new_pokey;
+extern int POKEYSND_stereo_enabled;
+extern int POKEYSND_serio_sound_enabled;
+extern int POKEYSND_console_sound_enabled;
+extern int POKEYSND_bienias_fix;
+
+extern void (*POKEYSND_Process_ptr)(void *sndbuffer, int sndn);
+extern void (*POKEYSND_Update_ptr)(UWORD addr, UBYTE val, UBYTE chip, UBYTE gain);
+extern void (*POKEYSND_UpdateSerio)(int out, UBYTE data);
+extern void (*POKEYSND_UpdateConsol_ptr)(int set);
+extern void (*POKEYSND_UpdateVolOnly)(void);
+
+int POKEYSND_Init(ULONG freq17, int playback_freq, UBYTE num_pokeys,
+                     int flags
+#ifdef __PLUS
+                     , int clear_regs
+#endif
+                     );
+void POKEYSND_Update(UWORD addr, UBYTE val, UBYTE /*chip*/, UBYTE gain);
+void POKEYSND_UpdateConsol(int set);
+
+/* Fill sndbuffer with sndn samples of audio. Number of bytes written to
+   sndbuffer is sndn with 8-bit sound, and 2*sndn with 16-bit sound. sndn
+   must be a multiple of POKEYSND_num_pokeys. */
+void POKEYSND_Process(void *sndbuffer, int sndn);
+int POKEYSND_DoInit(void);
+void POKEYSND_SetMzQuality(int quality);
+void POKEYSND_SetVolume(int vol);
+
+/* Volume only emulations declarations */
+#ifdef VOL_ONLY_SOUND
+
+#define	POKEYSND_SAMPBUF_MAX	2000
+extern int	POKEYSND_sampbuf_val[POKEYSND_SAMPBUF_MAX];	/* volume values */
+extern int	POKEYSND_sampbuf_cnt[POKEYSND_SAMPBUF_MAX];	/* relative start time */
+extern int	POKEYSND_sampbuf_ptr;                    /* pointer to sampbuf */
+extern int	POKEYSND_sampbuf_rptr;                   /* pointer to read from sampbuf */
+extern int	POKEYSND_sampbuf_last;                   /* last absolute time */
+extern int	POKEYSND_sampbuf_AUDV[4 * POKEY_MAXPOKEYS];	/* prev. channel volume */
+extern int	POKEYSND_sampbuf_lastval;		/* last volume */
+extern int	POKEYSND_sampout;			/* last out volume */
+extern int	POKEYSND_samp_freq;
+extern int	POKEYSND_samp_consol_val;		/* actual value of console sound */
+#endif  /* VOL_ONLY_SOUND */
+
+#ifdef SYNCHRONIZED_SOUND
+extern UBYTE *POKEYSND_process_buffer;
+extern unsigned int POKEYSND_process_buffer_length;
+extern unsigned int POKEYSND_process_buffer_fill;
+extern void (*POKEYSND_GenerateSync)(unsigned int num_ticks);
+int POKEYSND_UpdateProcessBuffer(void);
+#endif /* SYNCHRONIZED_SOUND */
+
+#ifdef __cplusplus
+}
+
+#endif
+#endif /* POKEYSND_H_ */
diff --git a/MCUME_pico2/pico800/program_config.h b/MCUME_pico2/pico800/program_config.h
new file mode 100644
index 0000000..91f04b3
--- /dev/null
+++ b/MCUME_pico2/pico800/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/pico800/romatariosa.h b/MCUME_pico2/pico800/romatariosa.h
new file mode 100644
index 0000000..207cb1a
--- /dev/null
+++ b/MCUME_pico2/pico800/romatariosa.h
@@ -0,0 +1,642 @@
+const UBYTE PROGMEM romos[10240] = {
+0x20,0xA1,0xDB,0x20,0xBB,0xDB,0xB0,0x39,0xA2,0xED,0xA0,0x04,0x20,0x48,0xDA,0xA2,
+0xFF,0x86,0xF1,0x20,0x44,0xDA,0xF0,0x04,0xA9,0xFF,0x85,0xF0,0x20,0x94,0xDB,0xB0,
+0x21,0x48,0xA6,0xD5,0xD0,0x11,0x20,0xEB,0xDB,0x68,0x05,0xD9,0x85,0xD9,0xA6,0xF1,
+0x30,0xE6,0xE8,0x86,0xF1,0xD0,0xE1,0x68,0xA6,0xF1,0x10,0x02,0xE6,0xED,0x4C,0x18,
+0xD8,0x60,0xC9,0x2E,0xF0,0x14,0xC9,0x45,0xF0,0x19,0xA6,0xF0,0xD0,0x68,0xC9,0x2B,
+0xF0,0xC6,0xC9,0x2D,0xF0,0x00,0x85,0xEE,0xF0,0xBE,0xA6,0xF1,0x10,0x58,0xE8,0x86,
+0xF1,0xF0,0xB5,0xA5,0xF2,0x85,0xEC,0x20,0x94,0xDB,0xB0,0x37,0xAA,0xA5,0xED,0x48,
+0x86,0xED,0x20,0x94,0xDB,0xB0,0x17,0x48,0xA5,0xED,0x0A,0x85,0xED,0x0A,0x0A,0x65,
+0xED,0x85,0xED,0x68,0x18,0x65,0xED,0x85,0xED,0xA4,0xF2,0x20,0x9D,0xDB,0xA5,0xEF,
+0xF0,0x09,0xA5,0xED,0x49,0xFF,0x18,0x69,0x01,0x85,0xED,0x68,0x18,0x65,0xED,0x85,
+0xED,0xD0,0x13,0xC9,0x2B,0xF0,0x06,0xC9,0x2D,0xD0,0x07,0x85,0xEF,0x20,0x94,0xDB,
+0x90,0xBA,0xA5,0xEC,0x85,0xF2,0xC6,0xF2,0xA5,0xED,0xA6,0xF1,0x30,0x05,0xF0,0x03,
+0x38,0xE5,0xF1,0x48,0x2A,0x68,0x6A,0x85,0xED,0x90,0x03,0x20,0xEB,0xDB,0xA5,0xED,
+0x18,0x69,0x44,0x85,0xD4,0x20,0x00,0xDC,0xB0,0x0B,0xA6,0xEE,0xF0,0x06,0xA5,0xD4,
+0x09,0x80,0x85,0xD4,0x18,0x60,0x20,0x51,0xDA,0xA9,0x30,0x8D,0x7F,0x05,0xA5,0xD4,
+0xF0,0x28,0x29,0x7F,0xC9,0x3F,0x90,0x28,0xC9,0x45,0xB0,0x24,0x38,0xE9,0x3F,0x20,
+0x70,0xDC,0x20,0xA4,0xDC,0x09,0x80,0x9D,0x80,0x05,0xAD,0x80,0x05,0xC9,0x2E,0xF0,
+0x03,0x4C,0x88,0xD9,0x20,0xC1,0xDC,0x4C,0x9C,0xD9,0xA9,0xB0,0x8D,0x80,0x05,0x60,
+0xA9,0x01,0x20,0x70,0xDC,0x20,0xA4,0xDC,0xE8,0x86,0xF2,0xA5,0xD4,0x0A,0x38,0xE9,
+0x80,0xAE,0x80,0x05,0xE0,0x30,0xF0,0x17,0xAE,0x81,0x05,0xAC,0x82,0x05,0x8E,0x82,
+0x05,0x8C,0x81,0x05,0xA6,0xF2,0xE0,0x02,0xD0,0x02,0xE6,0xF2,0x18,0x69,0x01,0x85,
+0xED,0xA9,0x45,0xA4,0xF2,0x20,0x9F,0xDC,0x84,0xF2,0xA5,0xED,0x10,0x0B,0xA9,0x00,
+0x38,0xE5,0xED,0x85,0xED,0xA9,0x2D,0xD0,0x02,0xA9,0x2B,0x20,0x9F,0xDC,0xA2,0x00,
+0xA5,0xED,0x38,0xE9,0x0A,0x90,0x03,0xE8,0xD0,0xF8,0x18,0x69,0x0A,0x48,0x8A,0x20,
+0x9D,0xDC,0x68,0x09,0x80,0x20,0x9D,0xDC,0xAD,0x80,0x05,0xC9,0x30,0xD0,0x0D,0x18,
+0xA5,0xF3,0x69,0x01,0x85,0xF3,0xA5,0xF4,0x69,0x00,0x85,0xF4,0xA5,0xD4,0x10,0x09,
+0x20,0xC1,0xDC,0xA0,0x00,0xA9,0x2D,0x91,0xF3,0x60,0xA5,0xD4,0x85,0xF8,0xA5,0xD5,
+0x85,0xF7,0x20,0x44,0xDA,0xF8,0xA0,0x10,0x06,0xF8,0x26,0xF7,0xA2,0x03,0xB5,0xD4,
+0x75,0xD4,0x95,0xD4,0xCA,0xD0,0xF7,0x88,0xD0,0xEE,0xD8,0xA9,0x42,0x85,0xD4,0x4C,
+0x00,0xDC,0xA9,0x00,0x85,0xF7,0x85,0xF8,0xA5,0xD4,0x30,0x66,0xC9,0x43,0xB0,0x62,
+0x38,0xE9,0x40,0x90,0x3F,0x69,0x00,0x0A,0x85,0xF5,0x20,0x5A,0xDA,0xB0,0x53,0xA5,
+0xF7,0x85,0xF9,0xA5,0xF8,0x85,0xFA,0x20,0x5A,0xDA,0xB0,0x46,0x20,0x5A,0xDA,0xB0,
+0x41,0x18,0xA5,0xF8,0x65,0xFA,0x85,0xF8,0xA5,0xF7,0x65,0xF9,0x85,0xF7,0xB0,0x32,
+0x20,0xB9,0xDC,0x18,0x65,0xF8,0x85,0xF8,0xA5,0xF7,0x69,0x00,0xB0,0x24,0x85,0xF7,
+0xC6,0xF5,0xD0,0xC6,0x20,0xB9,0xDC,0xC9,0x05,0x90,0x0D,0x18,0xA5,0xF8,0x69,0x01,
+0x85,0xF8,0xA5,0xF7,0x69,0x00,0x85,0xF7,0xA5,0xF8,0x85,0xD4,0xA5,0xF7,0x85,0xD5,
+0x18,0x60,0x38,0x60,0xA2,0xD4,0xA0,0x06,0xA9,0x00,0x95,0x00,0xE8,0x88,0xD0,0xFA,
+0x60,0xA9,0x05,0x85,0xF4,0xA9,0x80,0x85,0xF3,0x60,0x18,0x26,0xF8,0x26,0xF7,0x60,
+0xA5,0xE0,0x49,0x80,0x85,0xE0,0xA5,0xE0,0x29,0x7F,0x85,0xF7,0xA5,0xD4,0x29,0x7F,
+0x38,0xE5,0xF7,0x10,0x10,0xA2,0x05,0xB5,0xD4,0xB4,0xE0,0x95,0xE0,0x98,0x95,0xD4,
+0xCA,0x10,0xF4,0x30,0xE1,0xF0,0x07,0xC9,0x05,0xB0,0x19,0x20,0x3E,0xDC,0xF8,0xA5,
+0xD4,0x45,0xE0,0x30,0x1E,0xA2,0x04,0x18,0xB5,0xD5,0x75,0xE1,0x95,0xD5,0xCA,0x10,
+0xF7,0xD8,0xB0,0x03,0x4C,0x00,0xDC,0xA9,0x01,0x20,0x3A,0xDC,0xA9,0x01,0x85,0xD5,
+0x4C,0x00,0xDC,0xA2,0x04,0x38,0xB5,0xD5,0xF5,0xE1,0x95,0xD5,0xCA,0x10,0xF7,0x90,
+0x04,0xD8,0x4C,0x00,0xDC,0xA5,0xD4,0x49,0x80,0x85,0xD4,0x38,0xA2,0x04,0xA9,0x00,
+0xF5,0xD5,0x95,0xD5,0xCA,0x10,0xF7,0xD8,0x4C,0x00,0xDC,0xA5,0xD4,0xF0,0x45,0xA5,
+0xE0,0xF0,0x3E,0x20,0xCF,0xDC,0x38,0xE9,0x40,0x38,0x65,0xE0,0x30,0x38,0x20,0xE0,
+0xDC,0xA5,0xDF,0x29,0x0F,0x85,0xF6,0xC6,0xF6,0x30,0x06,0x20,0x01,0xDD,0x4C,0xF7,
+0xDA,0xA5,0xDF,0x4A,0x4A,0x4A,0x4A,0x85,0xF6,0xC6,0xF6,0x30,0x06,0x20,0x05,0xDD,
+0x4C,0x09,0xDB,0x20,0x62,0xDC,0xC6,0xF5,0xD0,0xD7,0xA5,0xED,0x85,0xD4,0x4C,0x04,
+0xDC,0x20,0x44,0xDA,0x18,0x60,0x38,0x60,0xA5,0xE0,0xF0,0xFA,0xA5,0xD4,0xF0,0xF4,
+0x20,0xCF,0xDC,0x38,0xE5,0xE0,0x18,0x69,0x40,0x30,0xEB,0x20,0xE0,0xDC,0xE6,0xF5,
+0x4C,0x4E,0xDB,0xA2,0x00,0xB5,0xD5,0x95,0xD4,0xE8,0xE0,0x0C,0xD0,0xF7,0xA0,0x05,
+0x38,0xF8,0xB9,0xDA,0x00,0xF9,0xE6,0x00,0x99,0xDA,0x00,0x88,0x10,0xF4,0xD8,0x90,
+0x04,0xE6,0xD9,0xD0,0xE9,0x20,0x0F,0xDD,0x06,0xD9,0x06,0xD9,0x06,0xD9,0x06,0xD9,
+0xA0,0x05,0x38,0xF8,0xB9,0xDA,0x00,0xF9,0xE0,0x00,0x99,0xDA,0x00,0x88,0x10,0xF4,
+0xD8,0x90,0x04,0xE6,0xD9,0xD0,0xE9,0x20,0x09,0xDD,0xC6,0xF5,0xD0,0xB5,0x20,0x62,
+0xDC,0x4C,0x1A,0xDB,0x20,0xAF,0xDB,0xA4,0xF2,0x90,0x02,0xB1,0xF3,0xC8,0x84,0xF2,
+0x60,0xA4,0xF2,0xA9,0x20,0xD1,0xF3,0xD0,0x03,0xC8,0xD0,0xF9,0x84,0xF2,0x60,0xA4,
+0xF2,0xB1,0xF3,0x38,0xE9,0x30,0x90,0x18,0xC9,0x0A,0x60,0xA5,0xF2,0x48,0x20,0x94,
+0xDB,0x90,0x1F,0xC9,0x2E,0xF0,0x14,0xC9,0x2B,0xF0,0x07,0xC9,0x2D,0xF0,0x03,0x68,
+0x38,0x60,0x20,0x94,0xDB,0x90,0x0B,0xC9,0x2E,0xD0,0xF4,0x20,0x94,0xDB,0x90,0x02,
+0xB0,0xED,0x68,0x85,0xF2,0x18,0x60,0xA2,0xE7,0xD0,0x02,0xA2,0xD5,0xA0,0x04,0x18,
+0x36,0x04,0x36,0x03,0x36,0x02,0x36,0x01,0x36,0x00,0x26,0xEC,0x88,0xD0,0xF0,0x60,
+0xA2,0x00,0x86,0xDA,0xA2,0x04,0xA5,0xD4,0xF0,0x2E,0xA5,0xD5,0xD0,0x1A,0xA0,0x00,
+0xB9,0xD6,0x00,0x99,0xD5,0x00,0xC8,0xC0,0x05,0x90,0xF5,0xC6,0xD4,0xCA,0xD0,0xEA,
+0xA5,0xD5,0xD0,0x04,0x85,0xD4,0x18,0x60,0xA5,0xD4,0x29,0x7F,0xC9,0x71,0x90,0x01,
+0x60,0xC9,0x0F,0xB0,0x03,0x20,0x44,0xDA,0x18,0x60,0xA2,0xD4,0xD0,0x02,0xA2,0xE0,
+0x86,0xF9,0x85,0xF7,0x85,0xF8,0xA0,0x04,0xB5,0x04,0x95,0x05,0xCA,0x88,0xD0,0xF8,
+0xA9,0x00,0x95,0x05,0xA6,0xF9,0xC6,0xF7,0xD0,0xEC,0xB5,0x00,0x18,0x65,0xF8,0x95,
+0x00,0x60,0xA2,0x0A,0xB5,0xD4,0x95,0xD5,0xCA,0x10,0xF9,0xA9,0x00,0x85,0xD4,0x60,
+0x85,0xF7,0xA2,0x00,0xA0,0x00,0x20,0x93,0xDC,0x38,0xE9,0x01,0x85,0xF7,0xB5,0xD5,
+0x4A,0x4A,0x4A,0x4A,0x20,0x9D,0xDC,0xB5,0xD5,0x29,0x0F,0x20,0x9D,0xDC,0xE8,0xE0,
+0x05,0x90,0xE3,0xA5,0xF7,0xD0,0x05,0xA9,0x2E,0x20,0x9F,0xDC,0x60,0x09,0x30,0x99,
+0x80,0x05,0xC8,0x60,0xA2,0x0A,0xBD,0x80,0x05,0xC9,0x2E,0xF0,0x07,0xC9,0x30,0xD0,
+0x07,0xCA,0xD0,0xF2,0xCA,0xBD,0x80,0x05,0x60,0x20,0xEB,0xDB,0xA5,0xEC,0x29,0x0F,
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+0x02,0xA5,0x66,0x18,0x65,0x64,0x85,0x64,0x85,0x5E,0xA5,0x67,0x65,0x65,0x85,0x65,
+0x85,0x5F,0xBD,0xB1,0xFE,0x8D,0xA0,0x02,0x85,0x6F,0x68,0x85,0x56,0x68,0x85,0x55,
+0x68,0x85,0x54,0x60,0xA9,0x00,0xF0,0x02,0xA9,0x9B,0x85,0x7D,0xE6,0x63,0xE6,0x55,
+0xD0,0x02,0xE6,0x56,0xA5,0x55,0xA6,0x57,0xDD,0x8D,0xFE,0xF0,0x0B,0xE0,0x00,0xD0,
+0x06,0xC5,0x53,0xF0,0x02,0xB0,0x01,0x60,0xE0,0x08,0x90,0x04,0xA5,0x56,0xF0,0xF7,
+0xA5,0x57,0xD0,0x30,0xA5,0x63,0xC9,0x51,0x90,0x0A,0xA5,0x7D,0xF0,0x26,0x20,0x30,
+0xFA,0x4C,0x77,0xFA,0x20,0x34,0xFA,0xA5,0x54,0x18,0x69,0x78,0x20,0x25,0xFB,0x90,
+0x08,0xA5,0x7D,0xF0,0x04,0x18,0x20,0xA5,0xF8,0x4C,0xDD,0xFB,0xA9,0x00,0xF0,0x02,
+0xA9,0x9B,0x85,0x7D,0x20,0xE4,0xFC,0xA9,0x00,0x85,0x56,0xE6,0x54,0xA6,0x57,0xA0,
+0x18,0x24,0x7B,0x10,0x05,0xA0,0x04,0x98,0xD0,0x03,0xBD,0x99,0xFE,0xC5,0x54,0xD0,
+0x26,0x8C,0x9D,0x02,0x8A,0xD0,0x20,0xA5,0x7D,0xF0,0x1C,0xC9,0x9B,0x38,0xF0,0x01,
+0x18,0x20,0xAC,0xFB,0xEE,0xBB,0x02,0xC6,0x6C,0xCE,0x9D,0x02,0xAD,0xB2,0x02,0x38,
+0x10,0xEF,0xAD,0x9D,0x02,0x85,0x54,0x4C,0xDD,0xFB,0x38,0xB5,0x70,0xE5,0x74,0x95,
+0x70,0xB5,0x71,0xE5,0x75,0x95,0x71,0x60,0xAD,0xBF,0x02,0xC9,0x04,0xF0,0x07,0xA5,
+0x57,0xF0,0x03,0x20,0xFC,0xF3,0xA9,0x27,0xC5,0x53,0xB0,0x02,0x85,0x53,0xA6,0x57,
+0xBD,0x99,0xFE,0xC5,0x54,0x90,0x2A,0xF0,0x28,0xE0,0x08,0xD0,0x0A,0xA5,0x56,0xF0,
+0x13,0xC9,0x01,0xD0,0x1C,0xF0,0x04,0xA5,0x56,0xD0,0x16,0xBD,0x8D,0xFE,0xC5,0x55,
+0x90,0x0F,0xF0,0x0D,0xA9,0x01,0x85,0x4C,0xA9,0x80,0xA6,0x11,0x85,0x11,0xF0,0x06,
+0x60,0x20,0xD6,0xF7,0xA9,0x8D,0x85,0x4C,0x68,0x68,0xA5,0x7B,0x10,0x03,0x20,0xB9,
+0xFC,0x4C,0x34,0xF6,0xA0,0x00,0xA5,0x5D,0x91,0x5E,0x60,0x48,0x29,0x07,0xAA,0xBD,
+0xB9,0xFE,0x85,0x6E,0x68,0x4A,0x4A,0x4A,0xAA,0x60,0x2E,0xB4,0x02,0x2E,0xB3,0x02,
+0x2E,0xB2,0x02,0x60,0x90,0x0C,0x20,0xEB,0xFA,0xBD,0xA3,0x02,0x05,0x6E,0x9D,0xA3,
+0x02,0x60,0x20,0xEB,0xFA,0xA5,0x6E,0x49,0xFF,0x3D,0xA3,0x02,0x9D,0xA3,0x02,0x60,
+0xA5,0x54,0x18,0x69,0x78,0x20,0xEB,0xFA,0x18,0xBD,0xA3,0x02,0x25,0x6E,0xF0,0x01,
+0x38,0x60,0xAD,0xFA,0x02,0xA4,0x57,0xC0,0x03,0xB0,0x0F,0x2A,0x2A,0x2A,0x2A,0x29,
+0x03,0xAA,0xAD,0xFA,0x02,0x29,0x9F,0x1D,0xFA,0xFE,0x8D,0xFB,0x02,0x60,0xA9,0x02,
+0x85,0x65,0xA9,0x47,0x85,0x64,0xA0,0x27,0xB1,0x66,0x85,0x50,0xB1,0x68,0x91,0x66,
+0xA5,0x50,0x91,0x64,0x88,0x10,0xF1,0xA5,0x65,0x85,0x69,0xA5,0x64,0x85,0x68,0x18,
+0xA5,0x66,0x69,0x28,0x85,0x66,0x90,0x02,0xE6,0x67,0x60,0x08,0xA0,0x17,0x98,0x20,
+0x22,0xFB,0x08,0x98,0x18,0x69,0x79,0x28,0x20,0x04,0xFB,0x88,0x30,0x04,0xC4,0x54,
+0xB0,0xEC,0xA5,0x54,0x18,0x69,0x78,0x28,0x4C,0x04,0xFB,0xA5,0x52,0x85,0x55,0x20,
+0x47,0xF9,0xA0,0x27,0xA9,0x00,0x91,0x64,0x88,0x10,0xFB,0x60,0x20,0xFA,0xFA,0xA5,
+0x58,0x85,0x64,0xA5,0x59,0x85,0x65,0xA0,0x28,0xB1,0x64,0xA6,0x6A,0xCA,0xE4,0x65,
+0xD0,0x08,0xA2,0xD7,0xE4,0x64,0xB0,0x02,0xA9,0x00,0xA0,0x00,0x91,0x64,0xE6,0x64,
+0xD0,0xE5,0xE6,0x65,0xA5,0x65,0xC5,0x6A,0xD0,0xDD,0x4C,0xDD,0xFB,0xA9,0x00,0x85,
+0x63,0xA5,0x54,0x85,0x51,0xA5,0x51,0x20,0x22,0xFB,0xB0,0x0C,0xA5,0x63,0x18,0x69,
+0x28,0x85,0x63,0xC6,0x51,0x4C,0xE5,0xFB,0x18,0xA5,0x63,0x65,0x55,0x85,0x63,0x60,
+0x20,0x9D,0xFC,0xA5,0x63,0x48,0xA5,0x6C,0x85,0x54,0xA5,0x6D,0x85,0x55,0xA9,0x01,
+0x85,0x6B,0xA2,0x17,0xA5,0x7B,0x10,0x02,0xA2,0x03,0xE4,0x54,0xD0,0x0B,0xA5,0x55,
+0xC5,0x53,0xD0,0x05,0xE6,0x6B,0x4C,0x39,0xFC,0x20,0xD4,0xF9,0xE6,0x6B,0xA5,0x63,
+0xC5,0x52,0xD0,0xDE,0xC6,0x54,0x20,0x99,0xF7,0x20,0xA2,0xF5,0xD0,0x17,0xC6,0x6B,
+0xA5,0x63,0xC5,0x52,0xF0,0x0F,0x20,0x99,0xF7,0xA5,0x55,0xC5,0x53,0xD0,0x02,0xC6,
+0x54,0xA5,0x6B,0xD0,0xE4,0x68,0x85,0x63,0x20,0xA8,0xFC,0x60,0x20,0xDD,0xFB,0xA5,
+0x51,0x85,0x6C,0xA5,0x52,0x85,0x6D,0x60,0xA5,0x63,0xC5,0x52,0xD0,0x02,0xC6,0x54,
+0x20,0xDD,0xFB,0xA5,0x63,0xC5,0x52,0xF0,0x13,0x20,0x47,0xF9,0xA5,0x53,0x38,0xE5,
+0x52,0xA8,0xB1,0x64,0xD0,0x06,0x88,0x10,0xF9,0x4C,0xDB,0xF8,0x60,0xA2,0x2D,0xBD,
+0xC6,0xFE,0xCD,0xFB,0x02,0xF0,0x05,0xCA,0xCA,0xCA,0x10,0xF3,0x60,0xA2,0x02,0xB5,
+0x54,0x9D,0xB8,0x02,0xCA,0x10,0xF8,0x60,0xA2,0x02,0xBD,0xB8,0x02,0x95,0x54,0xCA,
+0x10,0xF8,0x60,0x20,0xB9,0xFC,0x4C,0x34,0xF6,0xAD,0xBF,0x02,0xC9,0x18,0xF0,0x17,
+0xA2,0x0B,0xB5,0x54,0x48,0xBD,0x90,0x02,0x95,0x54,0x68,0x9D,0x90,0x02,0xCA,0x10,
+0xF1,0xA5,0x7B,0x49,0xFF,0x85,0x7B,0x60,0xA2,0x7F,0x8E,0x1F,0xD0,0x8E,0x0A,0xD4,
+0xCA,0x10,0xF7,0x60,0xA9,0x00,0xA6,0x7B,0xD0,0x04,0xA6,0x57,0xD0,0x02,0xA5,0x52,
+0x85,0x55,0x60,0xA5,0x58,0x85,0x64,0xA5,0x59,0x85,0x65,0x60,0xA2,0x00,0xA5,0x22,
+0xC9,0x11,0xF0,0x08,0xC9,0x12,0xF0,0x03,0xA0,0x84,0x60,0xE8,0x8E,0xB7,0x02,0xA5,
+0x54,0x85,0x60,0xA5,0x55,0x85,0x61,0xA5,0x56,0x85,0x62,0xA9,0x01,0x85,0x79,0x85,
+0x7A,0x38,0xA5,0x60,0xE5,0x5A,0x85,0x76,0xB0,0x0D,0xA9,0xFF,0x85,0x79,0xA5,0x76,
+0x49,0xFF,0x18,0x69,0x01,0x85,0x76,0x38,0xA5,0x61,0xE5,0x5B,0x85,0x77,0xA5,0x62,
+0xE5,0x5C,0x85,0x78,0xB0,0x16,0xA9,0xFF,0x85,0x7A,0xA5,0x77,0x49,0xFF,0x85,0x77,
+0xA5,0x78,0x49,0xFF,0x85,0x78,0xE6,0x77,0xD0,0x02,0xE6,0x78,0xA2,0x02,0xA0,0x00,
+0x84,0x73,0x98,0x95,0x70,0xB5,0x5A,0x95,0x54,0xCA,0x10,0xF6,0xA5,0x77,0xE8,0xA8,
+0xA5,0x78,0x85,0x7F,0x85,0x75,0xD0,0x0B,0xA5,0x77,0xC5,0x76,0xB0,0x05,0xA5,0x76,
+0xA2,0x02,0xA8,0x98,0x85,0x7E,0x85,0x74,0x48,0xA5,0x75,0x4A,0x68,0x6A,0x95,0x70,
+0xA5,0x7E,0x05,0x7F,0xD0,0x03,0x4C,0x42,0xFE,0x18,0xA5,0x70,0x65,0x76,0x85,0x70,
+0x90,0x02,0xE6,0x71,0xA5,0x71,0xC5,0x75,0x90,0x14,0xD0,0x06,0xA5,0x70,0xC5,0x74,
+0x90,0x0C,0x18,0xA5,0x54,0x65,0x79,0x85,0x54,0xA2,0x00,0x20,0x7A,0xFA,0x18,0xA5,
+0x72,0x65,0x77,0x85,0x72,0xA5,0x73,0x65,0x78,0x85,0x73,0xC5,0x75,0x90,0x27,0xD0,
+0x06,0xA5,0x72,0xC5,0x74,0x90,0x1F,0x24,0x7A,0x10,0x10,0xC6,0x55,0xA5,0x55,0xC9,
+0xFF,0xD0,0x0E,0xA5,0x56,0xF0,0x0A,0xC6,0x56,0x10,0x06,0xE6,0x55,0xD0,0x02,0xE6,
+0x56,0xA2,0x02,0x20,0x7A,0xFA,0x20,0x96,0xFA,0x20,0xE0,0xF5,0xAD,0xB7,0x02,0xF0,
+0x2F,0x20,0x9D,0xFC,0xAD,0xFB,0x02,0x8D,0xBC,0x02,0xA5,0x54,0x48,0x20,0xDC,0xF9,
+0x68,0x85,0x54,0x20,0x96,0xFA,0x20,0xA2,0xF5,0xD0,0x0C,0xAD,0xFD,0x02,0x8D,0xFB,
+0x02,0x20,0xE0,0xF5,0x4C,0x0A,0xFE,0xAD,0xBC,0x02,0x8D,0xFB,0x02,0x20,0xA8,0xFC,
+0x38,0xA5,0x7E,0xE9,0x01,0x85,0x7E,0xA5,0x7F,0xE9,0x00,0x85,0x7F,0x30,0x03,0x4C,
+0x90,0xFD,0x4C,0x34,0xF6,0x18,0x10,0x0A,0x0A,0x10,0x1C,0x34,0x64,0xC4,0xC4,0xC4,
+0xC4,0x17,0x17,0x0B,0x17,0x2F,0x2F,0x5F,0x5F,0x61,0x61,0x61,0x61,0x13,0x13,0x09,
+0x13,0x27,0x27,0x4F,0x4F,0x41,0x41,0x41,0x41,0x02,0x06,0x07,0x08,0x09,0x0A,0x0B,
+0x0D,0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,
+0x01,0x02,0x01,0x01,0x00,0x00,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x28,0x14,0x14,
+0x28,0x50,0x50,0xA0,0xA0,0x40,0x50,0x50,0x50,0x18,0x18,0x0C,0x18,0x30,0x30,0x60,
+0x60,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x02,0x03,0x02,0x03,0x02,0x03,0x01,0x01,
+0x01,0x00,0xFF,0xF0,0x0F,0xC0,0x30,0x0C,0x03,0x80,0x40,0x20,0x10,0x08,0x04,0x02,
+0x01,0x28,0xCA,0x94,0x46,0x00,0x1B,0x79,0xF7,0x1C,0x7F,0xF7,0x1D,0x8C,0xF7,0x1E,
+0x99,0xF7,0x1F,0xAA,0xF7,0x7D,0xB9,0xF7,0x7E,0xE6,0xF7,0x7F,0x10,0xF8,0x9B,0x30,
+0xFA,0x9C,0xD4,0xF8,0x9D,0xA4,0xF8,0x9E,0x32,0xF8,0x9F,0x2D,0xF8,0xFD,0x0A,0xF9,
+0xFE,0x6D,0xF8,0xFF,0x37,0xF8,0x40,0x00,0x20,0x60,0x20,0x40,0x00,0x60,0x6C,0x6A,
+0x3B,0x80,0x80,0x6B,0x2B,0x2A,0x6F,0x80,0x70,0x75,0x9B,0x69,0x2D,0x3D,0x76,0x80,
+0x63,0x80,0x80,0x62,0x78,0x7A,0x34,0x80,0x33,0x36,0x1B,0x35,0x32,0x31,0x2C,0x20,
+0x2E,0x6E,0x80,0x6D,0x2F,0x81,0x72,0x80,0x65,0x79,0x7F,0x74,0x77,0x71,0x39,0x80,
+0x30,0x37,0x7E,0x38,0x3C,0x3E,0x66,0x68,0x64,0x80,0x82,0x67,0x73,0x61,0x4C,0x4A,
+0x3A,0x80,0x80,0x4B,0x5C,0x5E,0x4F,0x80,0x50,0x55,0x9B,0x49,0x5F,0x7C,0x56,0x80,
+0x43,0x80,0x80,0x42,0x58,0x5A,0x24,0x80,0x23,0x26,0x1B,0x25,0x22,0x21,0x5B,0x20,
+0x5D,0x4E,0x80,0x4D,0x3F,0x81,0x52,0x80,0x45,0x59,0x9F,0x54,0x57,0x51,0x28,0x80,
+0x29,0x27,0x9C,0x40,0x7D,0x9D,0x46,0x48,0x44,0x80,0x83,0x47,0x53,0x41,0x0C,0x0A,
+0x7B,0x80,0x80,0x0B,0x1E,0x1F,0x0F,0x80,0x10,0x15,0x9B,0x09,0x1C,0x1D,0x16,0x80,
+0x03,0x80,0x80,0x02,0x18,0x1A,0x80,0x80,0x85,0x80,0x1B,0x80,0xFD,0x80,0x00,0x20,
+0x60,0x0E,0x80,0x0D,0x80,0x81,0x12,0x80,0x05,0x19,0x9E,0x14,0x17,0x11,0x80,0x80,
+0x80,0x80,0xFE,0x80,0x7D,0xFF,0x06,0x08,0x04,0x80,0x84,0x07,0x13,0x01,0xAD,0x09,
+0xD2,0xCD,0xF2,0x02,0xD0,0x05,0xAD,0xF1,0x02,0xD0,0x20,0xAD,0x09,0xD2,0xC9,0x9F,
+0xD0,0x0A,0xAD,0xFF,0x02,0x49,0xFF,0x8D,0xFF,0x02,0xB0,0x0F,0x8D,0xFC,0x02,0x8D,
+0xF2,0x02,0xA9,0x03,0x8D,0xF1,0x02,0xA9,0x00,0x85,0x4D,0xA9,0x30,0x8D,0x2B,0x02,
+0x68,0x40,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xD6,0x57,0xB4,0xE7,0x77,0xE4,0xF3,0xE6,
+};
diff --git a/MCUME_pico2/pico800/romatariosb.h b/MCUME_pico2/pico800/romatariosb.h
new file mode 100644
index 0000000..c0691f9
--- /dev/null
+++ b/MCUME_pico2/pico800/romatariosb.h
@@ -0,0 +1,642 @@
+const UBYTE PROGMEM romos[10240] = {
+0x20,0xA1,0xDB,0x20,0xBB,0xDB,0xB0,0x39,0xA2,0xED,0xA0,0x04,0x20,0x48,0xDA,0xA2,
+0xFF,0x86,0xF1,0x20,0x44,0xDA,0xF0,0x04,0xA9,0xFF,0x85,0xF0,0x20,0x94,0xDB,0xB0,
+0x21,0x48,0xA6,0xD5,0xD0,0x11,0x20,0xEB,0xDB,0x68,0x05,0xD9,0x85,0xD9,0xA6,0xF1,
+0x30,0xE6,0xE8,0x86,0xF1,0xD0,0xE1,0x68,0xA6,0xF1,0x10,0x02,0xE6,0xED,0x4C,0x18,
+0xD8,0x60,0xC9,0x2E,0xF0,0x14,0xC9,0x45,0xF0,0x19,0xA6,0xF0,0xD0,0x68,0xC9,0x2B,
+0xF0,0xC6,0xC9,0x2D,0xF0,0x00,0x85,0xEE,0xF0,0xBE,0xA6,0xF1,0x10,0x58,0xE8,0x86,
+0xF1,0xF0,0xB5,0xA5,0xF2,0x85,0xEC,0x20,0x94,0xDB,0xB0,0x37,0xAA,0xA5,0xED,0x48,
+0x86,0xED,0x20,0x94,0xDB,0xB0,0x17,0x48,0xA5,0xED,0x0A,0x85,0xED,0x0A,0x0A,0x65,
+0xED,0x85,0xED,0x68,0x18,0x65,0xED,0x85,0xED,0xA4,0xF2,0x20,0x9D,0xDB,0xA5,0xEF,
+0xF0,0x09,0xA5,0xED,0x49,0xFF,0x18,0x69,0x01,0x85,0xED,0x68,0x18,0x65,0xED,0x85,
+0xED,0xD0,0x13,0xC9,0x2B,0xF0,0x06,0xC9,0x2D,0xD0,0x07,0x85,0xEF,0x20,0x94,0xDB,
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+0x85,0x55,0x60,0xA5,0x58,0x85,0x64,0xA5,0x59,0x85,0x65,0x60,0xA2,0x00,0xA5,0x22,
+0xC9,0x11,0xF0,0x08,0xC9,0x12,0xF0,0x03,0xA0,0x84,0x60,0xE8,0x8E,0xB7,0x02,0xA5,
+0x54,0x85,0x60,0xA5,0x55,0x85,0x61,0xA5,0x56,0x85,0x62,0xA9,0x01,0x85,0x79,0x85,
+0x7A,0x38,0xA5,0x60,0xE5,0x5A,0x85,0x76,0xB0,0x0D,0xA9,0xFF,0x85,0x79,0xA5,0x76,
+0x49,0xFF,0x18,0x69,0x01,0x85,0x76,0x38,0xA5,0x61,0xE5,0x5B,0x85,0x77,0xA5,0x62,
+0xE5,0x5C,0x85,0x78,0xB0,0x16,0xA9,0xFF,0x85,0x7A,0xA5,0x77,0x49,0xFF,0x85,0x77,
+0xA5,0x78,0x49,0xFF,0x85,0x78,0xE6,0x77,0xD0,0x02,0xE6,0x78,0xA2,0x02,0xA0,0x00,
+0x84,0x73,0x98,0x95,0x70,0xB5,0x5A,0x95,0x54,0xCA,0x10,0xF6,0xA5,0x77,0xE8,0xA8,
+0xA5,0x78,0x85,0x7F,0x85,0x75,0xD0,0x0B,0xA5,0x77,0xC5,0x76,0xB0,0x05,0xA5,0x76,
+0xA2,0x02,0xA8,0x98,0x85,0x7E,0x85,0x74,0x48,0xA5,0x75,0x4A,0x68,0x6A,0x95,0x70,
+0xA5,0x7E,0x05,0x7F,0xD0,0x03,0x4C,0x42,0xFE,0x18,0xA5,0x70,0x65,0x76,0x85,0x70,
+0x90,0x02,0xE6,0x71,0xA5,0x71,0xC5,0x75,0x90,0x14,0xD0,0x06,0xA5,0x70,0xC5,0x74,
+0x90,0x0C,0x18,0xA5,0x54,0x65,0x79,0x85,0x54,0xA2,0x00,0x20,0x7A,0xFA,0x18,0xA5,
+0x72,0x65,0x77,0x85,0x72,0xA5,0x73,0x65,0x78,0x85,0x73,0xC5,0x75,0x90,0x27,0xD0,
+0x06,0xA5,0x72,0xC5,0x74,0x90,0x1F,0x24,0x7A,0x10,0x10,0xC6,0x55,0xA5,0x55,0xC9,
+0xFF,0xD0,0x0E,0xA5,0x56,0xF0,0x0A,0xC6,0x56,0x10,0x06,0xE6,0x55,0xD0,0x02,0xE6,
+0x56,0xA2,0x02,0x20,0x7A,0xFA,0x20,0x96,0xFA,0x20,0xE0,0xF5,0xAD,0xB7,0x02,0xF0,
+0x2F,0x20,0x9D,0xFC,0xAD,0xFB,0x02,0x8D,0xBC,0x02,0xA5,0x54,0x48,0x20,0xDC,0xF9,
+0x68,0x85,0x54,0x20,0x96,0xFA,0x20,0xA2,0xF5,0xD0,0x0C,0xAD,0xFD,0x02,0x8D,0xFB,
+0x02,0x20,0xE0,0xF5,0x4C,0x0A,0xFE,0xAD,0xBC,0x02,0x8D,0xFB,0x02,0x20,0xA8,0xFC,
+0x38,0xA5,0x7E,0xE9,0x01,0x85,0x7E,0xA5,0x7F,0xE9,0x00,0x85,0x7F,0x30,0x03,0x4C,
+0x90,0xFD,0x4C,0x34,0xF6,0x18,0x10,0x0A,0x0A,0x10,0x1C,0x34,0x64,0xC4,0xC4,0xC4,
+0xC4,0x17,0x17,0x0B,0x17,0x2F,0x2F,0x5F,0x5F,0x61,0x61,0x61,0x61,0x13,0x13,0x09,
+0x13,0x27,0x27,0x4F,0x4F,0x41,0x41,0x41,0x41,0x02,0x06,0x07,0x08,0x09,0x0A,0x0B,
+0x0D,0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,
+0x01,0x02,0x01,0x01,0x00,0x00,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x28,0x14,0x14,
+0x28,0x50,0x50,0xA0,0xA0,0x40,0x50,0x50,0x50,0x18,0x18,0x0C,0x18,0x30,0x30,0x60,
+0x60,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x02,0x03,0x02,0x03,0x02,0x03,0x01,0x01,
+0x01,0x00,0xFF,0xF0,0x0F,0xC0,0x30,0x0C,0x03,0x80,0x40,0x20,0x10,0x08,0x04,0x02,
+0x01,0x28,0xCA,0x94,0x46,0x00,0x1B,0x79,0xF7,0x1C,0x7F,0xF7,0x1D,0x8C,0xF7,0x1E,
+0x99,0xF7,0x1F,0xAA,0xF7,0x7D,0xB9,0xF7,0x7E,0xE6,0xF7,0x7F,0x10,0xF8,0x9B,0x30,
+0xFA,0x9C,0xD4,0xF8,0x9D,0xA4,0xF8,0x9E,0x32,0xF8,0x9F,0x2D,0xF8,0xFD,0x0A,0xF9,
+0xFE,0x6D,0xF8,0xFF,0x37,0xF8,0x40,0x00,0x20,0x60,0x20,0x40,0x00,0x60,0x6C,0x6A,
+0x3B,0x80,0x80,0x6B,0x2B,0x2A,0x6F,0x80,0x70,0x75,0x9B,0x69,0x2D,0x3D,0x76,0x80,
+0x63,0x80,0x80,0x62,0x78,0x7A,0x34,0x80,0x33,0x36,0x1B,0x35,0x32,0x31,0x2C,0x20,
+0x2E,0x6E,0x80,0x6D,0x2F,0x81,0x72,0x80,0x65,0x79,0x7F,0x74,0x77,0x71,0x39,0x80,
+0x30,0x37,0x7E,0x38,0x3C,0x3E,0x66,0x68,0x64,0x80,0x82,0x67,0x73,0x61,0x4C,0x4A,
+0x3A,0x80,0x80,0x4B,0x5C,0x5E,0x4F,0x80,0x50,0x55,0x9B,0x49,0x5F,0x7C,0x56,0x80,
+0x43,0x80,0x80,0x42,0x58,0x5A,0x24,0x80,0x23,0x26,0x1B,0x25,0x22,0x21,0x5B,0x20,
+0x5D,0x4E,0x80,0x4D,0x3F,0x81,0x52,0x80,0x45,0x59,0x9F,0x54,0x57,0x51,0x28,0x80,
+0x29,0x27,0x9C,0x40,0x7D,0x9D,0x46,0x48,0x44,0x80,0x83,0x47,0x53,0x41,0x0C,0x0A,
+0x7B,0x80,0x80,0x0B,0x1E,0x1F,0x0F,0x80,0x10,0x15,0x9B,0x09,0x1C,0x1D,0x16,0x80,
+0x03,0x80,0x80,0x02,0x18,0x1A,0x80,0x80,0x85,0x80,0x1B,0x80,0xFD,0x80,0x00,0x20,
+0x60,0x0E,0x80,0x0D,0x80,0x81,0x12,0x80,0x05,0x19,0x9E,0x14,0x17,0x11,0x80,0x80,
+0x80,0x80,0xFE,0x80,0x7D,0xFF,0x06,0x08,0x04,0x80,0x84,0x07,0x13,0x01,0xAD,0x09,
+0xD2,0xCD,0xF2,0x02,0xD0,0x05,0xAD,0xF1,0x02,0xD0,0x20,0xAD,0x09,0xD2,0xC9,0x9F,
+0xD0,0x0A,0xAD,0xFF,0x02,0x49,0xFF,0x8D,0xFF,0x02,0xB0,0x0F,0x8D,0xFC,0x02,0x8D,
+0xF2,0x02,0xA9,0x03,0x8D,0xF1,0x02,0xA9,0x00,0x85,0x4D,0xA9,0x30,0x8D,0x2B,0x02,
+0x68,0x40,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF3,0xE6,0x91,0xE7,0x25,0xF1,0xF3,0xE6,
+};
diff --git a/MCUME_pico2/pico800/romatarixl.h b/MCUME_pico2/pico800/romatarixl.h
new file mode 100644
index 0000000..2582bee
--- /dev/null
+++ b/MCUME_pico2/pico800/romatarixl.h
@@ -0,0 +1,1026 @@
+const UBYTE romos[16384] = {
+0x11,0x92,0x10,0x05,0x83,0x00,0x42,0x42,0x00,0x00,0x01,0x02,0xA9,0x40,0x8D,0x0E,
+0xD4,0xAD,0x13,0xD0,0x8D,0xFA,0x03,0x60,0x2C,0x0F,0xD4,0x10,0x03,0x6C,0x00,0x02,
+0xD8,0x48,0x8A,0x48,0x98,0x48,0x8D,0x0F,0xD4,0x6C,0x22,0x02,0xD8,0x6C,0x16,0x02,
+0x48,0xAD,0x0E,0xD2,0x29,0x20,0xD0,0x0D,0xA9,0xDF,0x8D,0x0E,0xD2,0xA5,0x10,0x8D,
+0x0E,0xD2,0x6C,0x0A,0x02,0x8A,0x48,0xAD,0xFF,0xD1,0x2D,0x49,0x02,0xF0,0x03,0x6C,
+0x38,0x02,0xA2,0x06,0xBD,0xCF,0xC0,0xE0,0x05,0xD0,0x04,0x25,0x10,0xF0,0x05,0x2C,
+0x0E,0xD2,0xF0,0x06,0xCA,0x10,0xED,0x4C,0xA0,0xC0,0x49,0xFF,0x8D,0x0E,0xD2,0xA5,
+0x10,0x8D,0x0E,0xD2,0xE0,0x00,0xD0,0x05,0xAD,0x6D,0x02,0xD0,0x23,0xBD,0xD7,0xC0,
+0xAA,0xBD,0x00,0x02,0x8D,0x8C,0x02,0xBD,0x01,0x02,0x8D,0x8D,0x02,0x68,0xAA,0x6C,
+0x8C,0x02,0xA9,0x00,0x85,0x11,0x8D,0xFF,0x02,0x8D,0xF0,0x02,0x85,0x4D,0x68,0x40,
+0x68,0xAA,0x2C,0x02,0xD3,0x10,0x06,0xAD,0x00,0xD3,0x6C,0x02,0x02,0x2C,0x03,0xD3,
+0x10,0x06,0xAD,0x01,0xD3,0x6C,0x04,0x02,0x68,0x8D,0x8C,0x02,0x68,0x48,0x29,0x10,
+0xF0,0x07,0xAD,0x8C,0x02,0x48,0x6C,0x06,0x02,0xAD,0x8C,0x02,0x48,0x68,0x40,0x80,
+0x40,0x04,0x02,0x01,0x08,0x10,0x20,0x36,0x08,0x14,0x12,0x10,0x0E,0x0C,0x0A,0x4C,
+0xDF,0xC0,0xE6,0x14,0xD0,0x08,0xE6,0x4D,0xE6,0x13,0xD0,0x02,0xE6,0x12,0xA9,0xFE,
+0xA2,0x00,0xA4,0x4D,0x10,0x06,0x85,0x4D,0xA6,0x13,0xA9,0xF6,0x85,0x4E,0x86,0x4F,
+0xAD,0xC5,0x02,0x45,0x4F,0x25,0x4E,0x8D,0x17,0xD0,0xA2,0x00,0x20,0x55,0xC2,0xD0,
+0x03,0x20,0x4F,0xC2,0xA5,0x42,0xD0,0x08,0xBA,0xBD,0x04,0x01,0x29,0x04,0xF0,0x03,
+0x4C,0x8A,0xC2,0xAD,0x13,0xD0,0xCD,0xFA,0x03,0xD0,0xB4,0xAD,0x0D,0xD4,0x8D,0x35,
+0x02,0xAD,0x0C,0xD4,0x8D,0x34,0x02,0xAD,0x31,0x02,0x8D,0x03,0xD4,0xAD,0x30,0x02,
+0x8D,0x02,0xD4,0xAD,0x2F,0x02,0x8D,0x00,0xD4,0xAD,0x6F,0x02,0x8D,0x1B,0xD0,0xAD,
+0x6C,0x02,0xF0,0x0E,0xCE,0x6C,0x02,0xA9,0x08,0x38,0xED,0x6C,0x02,0x29,0x07,0x8D,
+0x05,0xD4,0xA2,0x08,0x8E,0x1F,0xD0,0x58,0xBD,0xC0,0x02,0x45,0x4F,0x25,0x4E,0x9D,
+0x12,0xD0,0xCA,0x10,0xF2,0xAD,0xF4,0x02,0x8D,0x09,0xD4,0xAD,0xF3,0x02,0x8D,0x01,
+0xD4,0xA2,0x02,0x20,0x55,0xC2,0xD0,0x03,0x20,0x52,0xC2,0xA2,0x02,0xE8,0xE8,0xBD,
+0x18,0x02,0x1D,0x19,0x02,0xF0,0x06,0x20,0x55,0xC2,0x9D,0x26,0x02,0xE0,0x08,0xD0,
+0xEC,0xAD,0x0F,0xD2,0x29,0x04,0xF0,0x08,0xAD,0xF1,0x02,0xF0,0x03,0xCE,0xF1,0x02,
+0xAD,0x2B,0x02,0xF0,0x3E,0xAD,0x0F,0xD2,0x29,0x04,0xD0,0x32,0xCE,0x2B,0x02,0xD0,
+0x32,0xAD,0x6D,0x02,0xD0,0x2D,0xAD,0xDA,0x02,0x8D,0x2B,0x02,0xAD,0x09,0xD2,0xC9,
+0x9F,0xF0,0x20,0xC9,0x83,0xF0,0x1C,0xC9,0x84,0xF0,0x18,0xC9,0x94,0xF0,0x14,0x29,
+0x3F,0xC9,0x11,0xF0,0x0E,0xAD,0x09,0xD2,0x8D,0xFC,0x02,0x4C,0xF3,0xC1,0xA9,0x00,
+0x8D,0x2B,0x02,0xAD,0x00,0xD3,0x4A,0x4A,0x4A,0x4A,0x8D,0x79,0x02,0x8D,0x7B,0x02,
+0xAD,0x00,0xD3,0x29,0x0F,0x8D,0x78,0x02,0x8D,0x7A,0x02,0xAD,0x10,0xD0,0x8D,0x84,
+0x02,0x8D,0x86,0x02,0xAD,0x11,0xD0,0x8D,0x85,0x02,0x8D,0x87,0x02,0xA2,0x03,0xBD,
+0x00,0xD2,0x9D,0x70,0x02,0x9D,0x74,0x02,0xCA,0x10,0xF4,0x8D,0x0B,0xD2,0xA2,0x02,
+0xA0,0x01,0xB9,0x78,0x02,0x4A,0x4A,0x4A,0x9D,0x7D,0x02,0x9D,0x81,0x02,0xA9,0x00,
+0x2A,0x9D,0x7C,0x02,0x9D,0x80,0x02,0xCA,0xCA,0x88,0x10,0xE6,0x6C,0x24,0x02,0x6C,
+0x26,0x02,0x6C,0x28,0x02,0xBC,0x18,0x02,0xD0,0x08,0xBC,0x19,0x02,0xF0,0x10,0xDE,
+0x19,0x02,0xDE,0x18,0x02,0xD0,0x08,0xBC,0x19,0x02,0xD0,0x03,0xA9,0x00,0x60,0xA9,
+0xFF,0x60,0x0A,0x8D,0x2D,0x02,0x8A,0xA2,0x05,0x8D,0x0A,0xD4,0xCA,0xD0,0xFD,0xAE,
+0x2D,0x02,0x9D,0x17,0x02,0x98,0x9D,0x16,0x02,0x60,0x68,0xA8,0x68,0xAA,0x68,0x40,
+0x78,0xAD,0x13,0xD0,0xCD,0xFA,0x03,0xD0,0x2F,0x6A,0x90,0x05,0x20,0xC9,0xC4,0xD0,
+0x27,0xAD,0x44,0x02,0xD0,0x22,0xA9,0xFF,0xD0,0x20,0x78,0xA2,0x8C,0x88,0xD0,0xFD,
+0xCA,0xD0,0xFA,0xAD,0x3D,0x03,0xC9,0x5C,0xD0,0x0E,0xAD,0x3E,0x03,0xC9,0x93,0xD0,
+0x07,0xAD,0x3F,0x03,0xC9,0x25,0xF0,0xC8,0xA9,0x00,0x85,0x08,0x78,0xD8,0xA2,0xFF,
+0x9A,0x20,0x71,0xC4,0xA9,0x01,0x85,0x01,0xA5,0x08,0xD0,0x52,0xA9,0x00,0xA0,0x08,
+0x85,0x04,0x85,0x05,0xA9,0xFF,0x91,0x04,0xD1,0x04,0xF0,0x02,0x46,0x01,0xA9,0x00,
+0x91,0x04,0xD1,0x04,0xF0,0x02,0x46,0x01,0xC8,0xD0,0xE9,0xE6,0x05,0xA6,0x05,0xE4,
+0x06,0xD0,0xE1,0xA9,0x23,0x85,0x0A,0xA9,0xF2,0x85,0x0B,0xAD,0x01,0xD3,0x29,0x7F,
+0x8D,0x01,0xD3,0x20,0x73,0xFF,0xB0,0x05,0x20,0x92,0xFF,0x90,0x02,0x46,0x01,0xAD,
+0x01,0xD3,0x09,0x80,0x8D,0x01,0xD3,0xA9,0xFF,0x8D,0x44,0x02,0xD0,0x22,0xA2,0x00,
+0xAD,0xEC,0x03,0xF0,0x07,0x8E,0x0E,0x00,0x8E,0x0F,0x00,0x8A,0x9D,0x00,0x02,0xE0,
+0xED,0xB0,0x03,0x9D,0x00,0x03,0xCA,0xD0,0xF3,0xA2,0x10,0x95,0x00,0xE8,0x10,0xFB,
+0xA2,0x00,0xAD,0x01,0xD3,0x29,0x02,0xF0,0x01,0xE8,0x8E,0xF8,0x03,0xA9,0x5C,0x8D,
+0x3D,0x03,0xA9,0x93,0x8D,0x3E,0x03,0xA9,0x25,0x8D,0x3F,0x03,0xA9,0x02,0x85,0x52,
+0xA9,0x27,0x85,0x53,0xAD,0x14,0xD0,0x29,0x0E,0xD0,0x08,0xA9,0x05,0xA2,0x01,0xA0,
+0x28,0xD0,0x06,0xA9,0x06,0xA2,0x00,0xA0,0x30,0x8D,0xDA,0x02,0x86,0x62,0x8C,0xD9,
+0x02,0xA2,0x25,0xBD,0x4B,0xC4,0x9D,0x00,0x02,0xCA,0x10,0xF7,0xA2,0x0E,0xBD,0x2E,
+0xC4,0x9D,0x1A,0x03,0xCA,0x10,0xF7,0x20,0x35,0xC5,0x58,0xA5,0x01,0xD0,0x15,0xAD,
+0x01,0xD3,0x29,0x7F,0x8D,0x01,0xD3,0xA9,0x02,0x8D,0xF3,0x02,0xA9,0xE0,0x8D,0xF4,
+0x02,0x4C,0x03,0x50,0xA2,0x00,0x86,0x06,0xAE,0xE4,0x02,0xE0,0xB0,0xB0,0x0D,0xAE,
+0xFC,0xBF,0xD0,0x08,0xE6,0x06,0x20,0xC9,0xC4,0x20,0x29,0xC4,0xA9,0x03,0xA2,0x00,
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+0x3F,0xA0,0x88,0x60,0xA6,0x3D,0x9D,0x00,0x04,0xE6,0x3D,0xA0,0x01,0xE0,0x7F,0xF0,
+0x01,0x60,0xA9,0xFC,0x20,0x7C,0xFE,0xA9,0x00,0x85,0x3D,0x60,0xA0,0x01,0x60,0xAD,
+0x89,0x02,0x30,0x08,0xA0,0x01,0xA9,0x3C,0x8D,0x02,0xD3,0x60,0xA6,0x3D,0xF0,0x0A,
+0x8E,0x7F,0x04,0xA9,0xFA,0x20,0x7C,0xFE,0x30,0xEC,0xA2,0x7F,0xA9,0x00,0x9D,0x00,
+0x04,0xCA,0x10,0xFA,0xA9,0xFE,0x20,0x7C,0xFE,0x4C,0xD6,0xFD,0x85,0x40,0xA5,0x14,
+0x18,0xA6,0x62,0x7D,0x95,0xFE,0xAA,0xA9,0xFF,0x8D,0x1F,0xD0,0xA9,0x00,0xA0,0xF0,
+0x88,0xD0,0xFD,0x8D,0x1F,0xD0,0xA0,0xF0,0x88,0xD0,0xFD,0xE4,0x14,0xD0,0xE8,0xC6,
+0x40,0xF0,0x0E,0x8A,0x18,0xA6,0x62,0x7D,0x97,0xFE,0xAA,0xE4,0x14,0xD0,0xFC,0xF0,
+0xCD,0x20,0x36,0xFE,0x98,0x60,0xAD,0x25,0xE4,0x48,0xAD,0x24,0xE4,0x48,0x60,0x8D,
+0x02,0x03,0xA9,0x00,0x8D,0x09,0x03,0xA9,0x83,0x8D,0x08,0x03,0xA9,0x03,0x8D,0x05,
+0x03,0xA9,0xFD,0x8D,0x04,0x03,0xA9,0x60,0x8D,0x00,0x03,0xA9,0x00,0x8D,0x01,0x03,
+0xA9,0x23,0x8D,0x06,0x03,0xAD,0x02,0x03,0xA0,0x40,0xC9,0x52,0xF0,0x02,0xA0,0x80,
+0x8C,0x03,0x03,0xA5,0x3E,0x8D,0x0B,0x03,0x20,0x59,0xE4,0x60,0x8D,0xFF,0x03,0xA9,
+0x55,0x8D,0xFD,0x03,0x8D,0xFE,0x03,0xA9,0x57,0x20,0x3F,0xFE,0x60,0x04,0x03,0x80,
+0xC0,0x02,0x01,0x40,0xE0,0x1E,0x19,0x0A,0x08,0xA9,0x1E,0x8D,0x14,0x03,0x60,0xEA,
+0x02,0xC0,0x03,0xA9,0x04,0x8D,0xDF,0x02,0xAE,0x9F,0xFE,0xAC,0xA0,0xFE,0xA9,0x53,
+0x8D,0x02,0x03,0x8D,0x0A,0x03,0x20,0x14,0xFF,0x20,0x59,0xE4,0x30,0x03,0x20,0x44,
+0xFF,0x60,0x20,0xA3,0xFE,0xA9,0x00,0x8D,0xDE,0x02,0x60,0x48,0xBD,0x41,0x03,0x85,
+0x21,0x20,0x4B,0xFF,0xAE,0xDE,0x02,0x68,0x9D,0xC0,0x03,0xE8,0xEC,0xDF,0x02,0xF0,
+0x15,0x8E,0xDE,0x02,0xC9,0x9B,0xF0,0x03,0xA0,0x01,0x60,0xA9,0x20,0x9D,0xC0,0x03,
+0xE8,0xEC,0xDF,0x02,0xD0,0xF7,0xA9,0x00,0x8D,0xDE,0x02,0xAE,0xA1,0xFE,0xAC,0xA2,
+0xFE,0x20,0x14,0xFF,0x4C,0x59,0xE4,0x20,0x4B,0xFF,0xA9,0x9B,0xAE,0xDE,0x02,0xD0,
+0xDC,0xA0,0x01,0x60,0x8E,0x04,0x03,0x8C,0x05,0x03,0xA9,0x40,0x8D,0x00,0x03,0xA5,
+0x21,0x8D,0x01,0x03,0xA9,0x80,0xAE,0x02,0x03,0xE0,0x53,0xD0,0x02,0xA9,0x40,0x8D,
+0x03,0x03,0xAD,0xDF,0x02,0x8D,0x08,0x03,0xA9,0x00,0x8D,0x09,0x03,0xAD,0x14,0x03,
+0x8D,0x06,0x03,0x60,0xAD,0xEC,0x02,0x8D,0x14,0x03,0x60,0xA0,0x57,0xA5,0x2B,0xC9,
+0x4E,0xD0,0x04,0xA2,0x28,0xD0,0x0E,0xC9,0x44,0xD0,0x04,0xA2,0x14,0xD0,0x06,0xC9,
+0x53,0xD0,0x0C,0xA2,0x1D,0x8E,0xDF,0x02,0x8C,0x02,0x03,0x8D,0x0A,0x03,0x60,0xA9,
+0x4E,0xD0,0xDC,0xA2,0x00,0x86,0x8B,0x86,0x8C,0x20,0xA9,0xFF,0xE0,0x0C,0xD0,0xF9,
+0xAD,0x00,0xC0,0xAE,0x01,0xC0,0xC5,0x8B,0xD0,0x06,0xE4,0x8C,0xD0,0x02,0x18,0x60,
+0x38,0x60,0xA2,0x00,0x86,0x8B,0x86,0x8C,0xA2,0x0C,0x20,0xA9,0xFF,0x20,0xA9,0xFF,
+0xAD,0xF8,0xFF,0xAE,0xF9,0xFF,0x4C,0x86,0xFF,0xA0,0x00,0xBD,0xD7,0xFF,0x99,0x9E,
+0x00,0xE8,0xC8,0xC0,0x04,0xD0,0xF4,0xA0,0x00,0x18,0xB1,0x9E,0x65,0x8B,0x85,0x8B,
+0x90,0x02,0xE6,0x8C,0xE6,0x9E,0xD0,0x02,0xE6,0x9F,0xA5,0x9E,0xC5,0xA0,0xD0,0xE9,
+0xA5,0x9F,0xC5,0xA1,0xD0,0xE3,0x60,0x02,0xC0,0x00,0xD0,0x00,0x50,0x00,0x58,0x00,
+0xD8,0x00,0xE0,0x00,0xE0,0xF8,0xFF,0xFA,0xFF,0x00,0x00,0x00,0x00,0x00,0x10,0x05,
+0x83,0x02,0x42,0x42,0x00,0x00,0x01,0x02,0x8C,0x6C,0x18,0xC0,0xAA,0xC2,0x2C,0xC0,
+};
diff --git a/MCUME_pico2/pico800/sio.c b/MCUME_pico2/pico800/sio.c
new file mode 100644
index 0000000..575c914
--- /dev/null
+++ b/MCUME_pico2/pico800/sio.c
@@ -0,0 +1,55 @@
+/*
+ * sio.c - Serial I/O emulation
+ *
+ * Copyright (C) 1995-1998 David Firth
+ * Copyright (C) 1998-2010 Atari800 development team (see DOC/CREDITS)
+ *
+ * This file is part of the Atari800 emulator project which emulates
+ * the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
+ *
+ * Atari800 is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Atari800 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Atari800; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#define _POSIX_C_SOURCE 200112L /* for snprintf */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#include "antic.h"  /* ANTIC_ypos */
+#include "atari.h"
+#include "cpu.h"
+#include "memory.h"
+#include "pokey.h"
+#include "pokeysnd.h"
+#include "sio.h"
+
+
+
+
+/* Put a byte that comes out of POKEY. So get it here... */
+void SIO_PutByte(int byte)
+{
+}
+
+/* Get a byte from the floppy to the pokey. */
+int SIO_GetByte(void)
+{
+	int byte = 0;
+
+	return byte;
+}
+
diff --git a/MCUME_pico2/pico800/sio.h b/MCUME_pico2/pico800/sio.h
new file mode 100644
index 0000000..8a182f9
--- /dev/null
+++ b/MCUME_pico2/pico800/sio.h
@@ -0,0 +1,61 @@
+#ifndef SIO_H_
+#define SIO_H_
+
+
+#include <stdio.h> /* FILENAME_MAX */
+
+#include "atari.h"
+
+#define SIO_MAX_DRIVES 8
+
+typedef enum SIO_tagUnitStatus {
+	SIO_OFF,
+	SIO_NO_DISK,
+	SIO_READ_ONLY,
+	SIO_READ_WRITE
+} SIO_UnitStatus;
+
+extern char SIO_status[256];
+extern SIO_UnitStatus SIO_drive_status[SIO_MAX_DRIVES];
+extern char SIO_filename[SIO_MAX_DRIVES][FILENAME_MAX];
+
+#define SIO_LAST_READ 0
+#define SIO_LAST_WRITE 1
+extern int SIO_last_op;
+extern int SIO_last_op_time;
+extern int SIO_last_drive; /* 1 .. 8 */
+extern int SIO_last_sector;
+
+int SIO_Mount(int diskno, const char *filename, int b_open_readonly);
+void SIO_Dismount(int diskno);
+void SIO_DisableDrive(int diskno);
+int SIO_RotateDisks(void);
+void SIO_Handler(void);
+
+UBYTE SIO_ChkSum(const UBYTE *buffer, int length);
+void SIO_SwitchCommandFrame(int onoff);
+void SIO_PutByte(int byte);
+int SIO_GetByte(void);
+int SIO_Initialise(int *argc, char *argv[]);
+void SIO_Exit(void);
+
+/* Some defines about the serial I/O timing. Currently fixed! */
+#define SIO_XMTDONE_INTERVAL  15
+#define SIO_SERIN_INTERVAL     8
+#define SIO_SEROUT_INTERVAL    8
+#define SIO_ACK_INTERVAL      36
+
+/* These functions are also used by the 1450XLD Parallel disk device */
+extern int SIO_format_sectorcount[SIO_MAX_DRIVES];
+extern int SIO_format_sectorsize[SIO_MAX_DRIVES];
+int SIO_ReadStatusBlock(int unit, UBYTE *buffer);
+int SIO_FormatDisk(int unit, UBYTE *buffer, int sectsize, int sectcount);
+void SIO_SizeOfSector(UBYTE unit, int sector, int *sz, ULONG *ofs);
+int SIO_ReadSector(int unit, int sector, UBYTE *buffer);
+int SIO_DriveStatus(int unit, UBYTE *buffer);
+int SIO_WriteStatusBlock(int unit, const UBYTE *buffer);
+int SIO_WriteSector(int unit, int sector, const UBYTE *buffer);
+void SIO_StateSave(void);
+void SIO_StateRead(void);
+
+#endif	/* SIO_H_ */
diff --git a/MCUME_pico2/pico8086/.DS_Store b/MCUME_pico2/pico8086/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/pico8086/.DS_Store differ
diff --git a/MCUME_pico2/pico8086/cpu.cpp b/MCUME_pico2/pico8086/cpu.cpp
new file mode 100755
index 0000000..18904e7
--- /dev/null
+++ b/MCUME_pico2/pico8086/cpu.cpp
@@ -0,0 +1,2263 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "intf.h"
+#include "rom.h"
+
+extern void portout(uint16_t portnum, uint16_t value);
+extern uint16_t portin(uint16_t portnum);
+
+extern void readdisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount);
+extern void insertdisk();
+
+extern void doirq(uint8_t irqnum);
+extern uint8_t nextintr();
+extern struct structpic {
+  uint8_t imr; //mask register
+  uint8_t irr; //request register
+  uint8_t isr; //service register
+  uint8_t icwstep; //used during initialization to keep track of which ICW we're at
+  uint8_t icw[5];
+  uint8_t intoffset; //interrupt vector offset
+  uint8_t priority; //which IRQ has highest priority
+  uint8_t autoeoi; //automatic EOI mode
+  uint8_t readmode; //remember what to return on read register from OCW3
+  uint8_t enabled;
+} i8259;
+
+extern uint8_t curkey;
+void intcall86(uint8_t intnum);
+
+uint64_t curtimer, lasttimer, timerfreq;
+
+char *biosfile = NULL;
+uint8_t byteregtable[8] = { regal, regcl, regdl, regbl, regah, regch, regdh, regbh };
+
+uint8_t parity[0x100];
+
+_bytewordregs_ regs;
+
+uint16_t segregs[6];
+uint8_t opcode, segoverride, reptype, bootdrive, hdcount = 0;
+uint16_t savecs, saveip, ip, useseg, oldsp;
+uint8_t tempcf, oldcf, cf, pf, af, zf, sf, tf, ifl, df, of, nt, iopriv, mode, reg, rm, msw = 0;
+uint16_t oper1, oper2, res16, disp16, temp16, dummy, stacksize, frametemp;
+uint8_t oper1b, oper2b, res8, disp8, temp8, nestlev, addrbyte;
+uint16_t cr0 = 0, cr1 = 0, cr2 = 0, cr3 = 0;
+uint32_t ldtr = 0, gdtr = 0, gdtlimit = 0, idtr = 0, idtlimit = 0;
+uint32_t temp1, temp2, temp3, temp4, temp5, temp32, tempaddr32, ea;
+int32_t result, speed = 0;
+uint32_t totalexec;
+uint32_t ips[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
+uint16_t *tempwordptr;
+
+uint8_t vidmode, cgabg, blankattr, vidgfxmode, vidcolor;
+uint16_t cursx, cursy, cols, rows, vgapage, cursorposition, cursorvisible;
+uint8_t updatedscreen, port3da, port6, portout16;
+//uint16_t VGA_SC[0xFF], VGA_CRTC[0xFF], VGA_ATTR[0xFF], VGA_GC[0xFF];
+uint32_t videobase, textbase, x, y;
+
+uint8_t debugmode, showcsip, verbose, mouseemu;
+
+extern "C" unsigned char read_ram(int address);
+extern "C" void  write_ram(int address, unsigned char val);
+
+extern uint8_t * LORAM;
+
+void write86(uint32_t addr32, uint8_t value) {
+  if (addr32 < NATIVE_RAM) {
+    LORAM[addr32] = value;
+    return;
+  } 
+  else if (addr32 < RAM_SIZE) {
+    write_ram(addr32, value);
+    return;
+  } 
+  else if ((addr32 >= 0xB8000) && (addr32 < 0xC0000)) {
+    VRAM_write(addr32 - 0xB8000UL, value);
+  }
+}
+
+#define writew86(addr32,value) {write86((addr32),(uint8_t)(value));write86((addr32)+1,(uint8_t)((uint16_t)(value)>>8));}
+
+uint8_t read86(uint32_t addr32) {
+  if (addr32 < NATIVE_RAM) {
+    switch (addr32) { //some hardcoded values for the BIOS data area
+      case 0x410: //0040:0010 is the equipment word
+#ifdef VGA
+        return (0x41); //video type (0x41 is VGA/EGA, 0x61 is CGA, 0x31 = MDA)
+#else
+        return (0x61); //video type (0x41 is VGA/EGA, 0x61 is CGA, 0x31 = MDA)
+#endif
+      case 0x475: //hard drive count
+        return (hdcount);
+      default:
+        return LORAM[addr32];
+    }    
+  } 
+  else if (addr32 < RAM_SIZE) {
+    return read_ram(addr32);
+  } 
+  else if ((addr32 >= 0xB8000) && (addr32 < 0xC0000)) {
+    addr32 -= 0xB8000UL;
+    return VRAM_read(addr32);
+  }
+  else if (addr32 >= 0xFE000UL) {
+    addr32 -= 0xFE000UL;
+    return ROM_READ(BIOS, addr32); //BIOS[addr32];
+  }
+  else if ((addr32 >= 0xD0000) && (addr32 < 0xD0640)) {
+    return net_read_ram(addr32 - 0xD0000);
+  }
+  else if ((addr32 >= 0xE0000) && (addr32 < 0xE0006)) {
+    return net_mac[addr32 - 0xE0000];
+  }
+#ifdef INCLUDE_ROM_BASIC
+  else if ((addr32 >= 0xF6000UL) && (addr32 < 0xFA000UL)) {
+    addr32 -= 0xF6000UL;
+    return ROM_READ(BASICL, addr32); //BASICL[addr32];
+  } else if ((addr32 >= 0xFA000UL) && (addr32 < 0xFE000UL)) {
+    addr32 -= 0xFA000UL;
+    return ROM_READ(BASICH, addr32); //BASICH[addr32];
+  }
+#endif
+  else return 0;
+}
+
+
+
+#define readw86(addr32) ((uint16_t)read86((addr32))|((uint16_t)read86((addr32)+1)<<8))
+
+//inline void flag_szp8(uint8_t value) {
+#define flag_szp8(value) {\
+  if (!(value)) zf = 1; else zf = 0;\
+  if ((value) & 0x80) sf = 1; else sf = 0;\
+  pf = parity[value];\
+}
+
+//inline void flag_szp16(uint16_t value) {
+#define flag_szp16(value) {\
+  if (!(value)) zf = 1; else zf = 0;\
+  if (value & 0x8000) sf = 1; else sf = 0;\
+  pf = parity[(uint8_t)value];\
+}
+
+//inline void flag_log8(uint8_t value) {
+#define flag_log8(value) {\
+  flag_szp8(value);\
+  cf = 0; of = 0;\
+}
+
+//inline void flag_log16(uint16_t value) {
+#define flag_log16(value) {\
+  flag_szp16(value);\
+  cf = 0; of = 0;\
+}
+
+//inline void flag_adc8(uint8_t v1, uint8_t v2, uint8_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag
+#define flag_adc8(v1, v2, v3) {\
+  uint16_t dst;\
+  dst = (uint16_t)(v1) + (uint16_t)(v2) + (uint16_t)(v3);\
+  flag_szp8((uint8_t)dst);\
+  if (((dst ^ (v1)) & (dst ^ (v2)) & 0x80) == 0x80) of = 1; else of = 0;\
+  if (dst & 0xFF00) cf = 1; else cf = 0;\
+  if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_adc16(uint16_t v1, uint16_t v2, uint16_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag
+#define flag_adc16(v1, v2, v3) {\
+  uint32_t dst;\
+  dst = (uint32_t)(v1) + (uint32_t)(v2) + (uint32_t)(v3);\
+  flag_szp16((uint16_t)dst);\
+  if ((((dst ^ (v1)) & (dst ^ (v2))) & 0x8000) == 0x8000) of = 1; else of = 0;\
+  if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\
+  if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_add8(uint8_t v1, uint8_t v2) { //v1 = destination operand, v2 = source operand
+#define flag_add8(v1, v2) {\
+  uint16_t dst;\
+  dst = (uint16_t)(v1) + (uint16_t)(v2);\
+  flag_szp8((uint8_t)dst);\
+  if (dst & 0xFF00) cf = 1; else cf = 0;\
+  if (((dst ^ (v1)) & (dst ^ (v2)) & 0x80) == 0x80) of = 1; else of = 0;\
+  if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_add16(uint16_t v1, uint16_t v2) { //v1 = destination operand, v2 = source operand
+#define flag_add16(v1, v2) {\
+  uint32_t dst;\
+  dst = (uint32_t)(v1) + (uint32_t)(v2);\
+  flag_szp16((uint16_t)dst);\
+  if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\
+  if (((dst ^ (v1)) & (dst ^ (v2)) & 0x8000) == 0x8000) of = 1; else of = 0;\
+  if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_sbb8(uint8_t v1, uint8_t v2, uint8_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag
+#define flag_sbb8(v1, v2, v3) {\
+  uint16_t dst;\
+  uint16_t newv2;\
+  newv2 = (uint16_t)(v2) + (uint16_t)(v3);\
+  dst = (uint16_t)(v1) - (uint16_t)newv2;\
+  flag_szp8((uint8_t)dst);\
+  if (dst & 0xFF00) cf = 1; else cf = 0;\
+  if ((dst ^ (v1)) & ((v1) ^ newv2) & 0x80) of = 1; else of = 0;\
+  if (((v1) ^ newv2 ^ dst) & 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_sbb16(uint16_t v1, uint16_t v2, uint16_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag
+#define flag_sbb16(v1, v2, v3){\
+  uint32_t dst;\
+  uint32_t newv2;\
+  newv2 = (uint32_t)(v2) + (uint32_t)(v3);\
+  dst = (uint32_t)v1 - newv2;\
+  flag_szp16((uint16_t)dst);\
+  if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\
+  if ((dst ^ (v1)) & (v1 ^ newv2) & 0x8000) of = 1; else of = 0;\
+  if (((v1) ^ newv2 ^ dst) & 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_sub8(uint8_t v1, uint8_t v2) { //v1 = destination operand, v2 = source operand
+#define flag_sub8(v1, v2) {\
+  uint16_t dst;\
+  dst = (uint16_t)(v1) - (uint16_t)(v2);\
+  flag_szp8((uint8_t)dst);\
+  if (dst & 0xFF00) cf = 1; else cf = 0;\
+  if ((dst ^ (v1)) & ((v1) ^ (v2)) & 0x80) of = 1; else of = 0;\
+  if (((v1) ^ (v2) ^ dst) & 0x10) af = 1; else af = 0;\
+}
+
+//inline void flag_sub16(uint16_t v1, uint16_t v2) { //v1 = destination operand, v2 = source operand
+#define flag_sub16(v1, v2) {\
+  uint32_t dst;\
+  dst = (uint32_t)(v1) - (uint32_t)(v2);\
+  flag_szp16((uint16_t)dst);\
+  if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\
+  if ((dst ^ (v1)) & ((v1) ^ (v2)) & 0x8000) of = 1; else of = 0;\
+  if (((v1) ^ (v2) ^ dst) & 0x10) af = 1; else af = 0;\
+}
+
+//inline void op_adc8() {
+#define op_adc8() {\
+  res8 = oper1b + oper2b + cf;\
+  flag_adc8(oper1b, oper2b, cf);\
+}
+
+//inline void op_adc16() {
+#define op_adc16() {\
+  res16 = oper1 + oper2 + cf;\
+  flag_adc16(oper1, oper2, cf);\
+}
+
+//inline void op_add8() {
+#define op_add8() {\
+  res8 = oper1b + oper2b;\
+  flag_add8(oper1b, oper2b);\
+}
+
+//inline void op_add16() {
+#define op_add16() {\
+  res16 = oper1 + oper2;\
+  flag_add16(oper1, oper2);\
+}
+
+//inline void op_and8() {
+#define op_and8() {\
+  res8 = oper1b & oper2b;\
+  flag_log8(res8);\
+}
+
+//inline void op_and16() {
+#define op_and16() {\
+  res16 = oper1 & oper2;\
+  flag_log16(res16);\
+}
+
+//inline void op_or8() {
+#define op_or8() {\
+  res8 = oper1b | oper2b;\
+  flag_log8(res8);\
+}
+
+//inline void op_or16() {
+#define op_or16() {\
+  res16 = oper1 | oper2;\
+  flag_log16(res16);\
+}
+
+//inline void op_xor8() {
+#define op_xor8() {\
+  res8 = oper1b ^ oper2b;\
+  flag_log8(res8);\
+}
+
+//inline void op_xor16() {
+#define op_xor16() {\
+  res16 = oper1 ^ oper2;\
+  flag_log16(res16);\
+}
+
+//inline void op_sub8() {
+#define op_sub8() {\
+  res8 = oper1b - oper2b;\
+  flag_sub8(oper1b, oper2b);\
+}
+
+//inline void op_sub16() {
+#define op_sub16() {\
+  res16 = oper1 - oper2;\
+  flag_sub16(oper1, oper2);\
+}
+
+//inline void op_sbb8() {
+#define op_sbb8() {\
+  res8 = oper1b - (oper2b + cf);\
+  flag_sbb8(oper1b, oper2b, cf);\
+}
+
+//inline void op_sbb16() {
+#define op_sbb16() {\
+  res16 = oper1 - (oper2 + cf);\
+  flag_sbb16(oper1, oper2, cf);\
+}
+
+//inline void modregrm() {
+#define modregrm() {\
+  addrbyte = getmem8(segregs[regcs], ip); StepIP(1);\
+  mode = addrbyte >> 6;\
+  reg = (addrbyte >> 3) & 7;\
+  rm = addrbyte & 7;\
+  switch (mode) {\
+    case 0:\
+      if (rm == 6) {\
+        disp16 = getmem16(segregs[regcs], ip);\
+        StepIP(2);\
+      }\
+      if (((rm == 2) || (rm == 3)) && !segoverride) useseg = segregs[regss]; break;\
+    case 1:\
+      disp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);\
+      if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) useseg = segregs[regss]; break;\
+    case 2:\
+      disp16 = getmem16(segregs[regcs], ip); StepIP(2);\
+      if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) useseg = segregs[regss]; break;\
+    default:\
+      disp8 = 0; disp16 = 0;\
+  }\
+  if (mode < 3) getea(rm);\
+}
+
+//inline void getea(uint8_t rmval) {
+#define getea(rmval) {\
+  uint32_t tempea;\
+  tempea = 0;\
+  switch (mode) {\
+    case 0:\
+      switch (rmval) {\
+        case 0: tempea = regs.wordregs[regbx] + regs.wordregs[regsi]; break;\
+        case 1: tempea = regs.wordregs[regbx] + regs.wordregs[regdi]; break;\
+        case 2: tempea = regs.wordregs[regbp] + regs.wordregs[regsi]; break;\
+        case 3: tempea = regs.wordregs[regbp] + regs.wordregs[regdi]; break;\
+        case 4: tempea = regs.wordregs[regsi]; break;\
+        case 5: tempea = regs.wordregs[regdi]; break;\
+        case 6: tempea = disp16; break;\
+        case 7: tempea = regs.wordregs[regbx]; break;\
+      } break;\
+    case 1: case 2:\
+      switch (rmval) {\
+        case 0: tempea = regs.wordregs[regbx] + regs.wordregs[regsi] + disp16; break;\
+        case 1: tempea = regs.wordregs[regbx] + regs.wordregs[regdi] + disp16; break;\
+        case 2: tempea = regs.wordregs[regbp] + regs.wordregs[regsi] + disp16; break;\
+        case 3: tempea = regs.wordregs[regbp] + regs.wordregs[regdi] + disp16; break;\
+        case 4: tempea = regs.wordregs[regsi] + disp16; break;\
+        case 5: tempea = regs.wordregs[regdi] + disp16; break;\
+        case 6: tempea = regs.wordregs[regbp] + disp16; break;\
+        case 7: tempea = regs.wordregs[regbx] + disp16; break;\
+      } break;\
+  }\
+  ea = useseg;\
+  ea <<= 4;\
+  ea += (tempea & 0xFFFF);\
+}
+
+inline void push(uint16_t pushval) {
+  putreg16(regsp, getreg16(regsp) - 2);
+  //printf("  %04X:%04X PUSH\n", segregs[regss], getreg16(regsp));
+  putmem16(segregs[regss], getreg16(regsp), pushval);
+}
+
+inline uint16_t pop() {
+  uint16_t tempval;
+  //printf("  %04X:%04X POP\n", segregs[regss], getreg16(regsp));
+  tempval = getmem16(segregs[regss], getreg16(regsp));
+  putreg16(regsp, getreg16(regsp) + 2);
+  return (tempval);
+}
+
+void reset86() {
+  uint16_t i, cnt, bitcount;
+  segregs[regcs] = 0xFFFF;
+  ip = 0x0000;
+  segregs[regss] = 0x0000;
+  regs.wordregs[regsp] = 0xFFFE;
+
+  //generate parity lookup table
+  for (i = 0; i < 256; i++) {
+    bitcount = 0;
+    for (cnt = 0; cnt < 8; cnt++)
+      bitcount += ((i >> cnt) & 1);
+    if (bitcount & 1) parity[i] = 0; else parity[i] = 1;
+  }
+}
+
+/*inline uint16_t readrm16(uint8_t rmval) {
+  if (mode < 3) {
+    getea(rmval);
+    return (read86(ea) | ((uint16_t)read86(ea + 1) << 8));
+  } else {
+    return (getreg16(rmval));
+  }
+}*/
+
+#define readrm16(rmval) ( (mode < 3) ? (read86(ea) | ((uint16_t)read86(ea + 1) << 8)) : (getreg16(rmval)) )
+
+/*inline uint8_t readrm8(uint8_t rmval) {
+  if (mode < 3) {
+    //getea(rmval);
+    return (read86(ea));
+  } else {
+    return (getreg8(rmval));
+  }
+}*/
+
+#define readrm8(rmval) ( (mode < 3) ? read86(ea) : getreg8(rmval) )
+
+inline void writerm16(uint8_t rmval, uint16_t value) {
+//#define writerm16(rmval, value) {
+  if (mode < 3) {\
+    /*getea(rmval);*/\
+    write86(ea, value & 0xFF);\
+    write86(ea + 1, value >> 8);\
+  } else {\
+    putreg16(rmval, value);\
+  }\
+}
+
+inline void writerm8(uint8_t rmval, uint8_t value) {
+//#define writerm8(rmval, value) {
+  if (mode < 3) {\
+    /*getea(rmval);*/\
+    write86(ea, value);\
+  } else {\
+    putreg8(rmval, value);\
+  }\
+}
+
+inline uint8_t op_grp2_8(uint8_t cnt) {
+  uint16_t s, oldcf, msb;
+  uint8_t shift;
+  s = oper1b;
+  oldcf = cf;
+  switch (reg) {
+    case 0: //ROL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        if (s & 0x80) cf = 1; else cf = 0;
+        s = s << 1;
+        s = s | cf;
+      }
+      if (cnt == 1) of = cf ^ ((s >> 7) & 1);
+      break;
+
+    case 1: //ROR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        cf = s & 1;
+        s = (s >> 1) | (cf << 7);
+      }
+      if (cnt == 1) of = (s >> 7) ^ ((s >> 6) & 1);
+      break;
+
+    case 2: //RCL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        oldcf = cf;
+        if (s & 0x80) cf = 1; else cf = 0;
+        s = s << 1;
+        s = s | oldcf;
+      }
+      if (cnt == 1) of = cf ^ ((s >> 7) & 1);
+      break;
+
+    case 3: //RCR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        oldcf = cf;
+        cf = s & 1;
+        s = (s >> 1) | (oldcf << 7);
+      }
+      if (cnt == 1) of = (s >> 7) ^ ((s >> 6) & 1);
+      break;
+
+    case 4: case 6: //SHL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        if (s & 0x80) cf = 1; else cf = 0;
+        s = (s << 1) & 0xFF;
+      }
+      if ((cnt == 1) && (cf == (s >> 7))) of = 0; else of = 1;
+      flag_szp8((uint8_t)s); break;
+
+    case 5: //SHR r/m8
+      if ((cnt == 1) && (s & 0x80)) of = 1; else of = 0;
+      for (shift = 1; shift <= cnt; shift++) {
+        cf = s & 1;
+        s = s >> 1;
+      }
+      flag_szp8((uint8_t)s); break;
+
+    case 7: //SAR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        msb = s & 0x80;
+        cf = s & 1;
+        s = (s >> 1) | msb;
+      }
+      of = 0;
+      flag_szp8((uint8_t)s); break;
+
+  }
+  return (s & 0xFF);
+}
+
+inline uint16_t op_grp2_16(uint8_t cnt) {
+  uint32_t s, oldcf, msb;
+  uint8_t shift;
+  s = oper1;
+  oldcf = cf;
+  switch (reg) {
+    case 0: //ROL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        if (s & 0x8000) cf = 1; else cf = 0;
+        s = s << 1;
+        s = s | cf;
+      }
+      if (cnt == 1) of = cf ^ ((s >> 15) & 1);
+      break;
+
+    case 1: //ROR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        cf = s & 1;
+        s = (s >> 1) | (cf << 15);
+      }
+      if (cnt == 1) of = (s >> 15) ^ ((s >> 14) & 1);
+      break;
+
+    case 2: //RCL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        oldcf = cf;
+        if (s & 0x8000) cf = 1; else cf = 0;
+        s = s << 1;
+        s = s | oldcf;
+      }
+      if (cnt == 1) of = cf ^ ((s >> 15) & 1);
+      break;
+
+    case 3: //RCR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        oldcf = cf;
+        cf = s & 1;
+        s = (s >> 1) | (oldcf << 15);
+      }
+      if (cnt == 1) of = (s >> 15) ^ ((s >> 14) & 1);
+      break;
+
+    case 4: case 6: //SHL r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        if (s & 0x8000) cf = 1; else cf = 0;
+        s = (uint16_t)(s << 1);
+      }
+      if ((cnt == 1) && (cf == (s >> 15))) of = 0; else of = 1;
+      flag_szp16((uint16_t)s); break;
+
+    case 5: //SHR r/m8
+      if ((cnt == 1) && (s & 0x8000)) of = 1; else of = 0;
+      for (shift = 1; shift <= cnt; shift++) {
+        cf = s & 1;
+        s = s >> 1;
+      }
+      flag_szp16((uint16_t)s); break;
+
+    case 7: //SAR r/m8
+      for (shift = 1; shift <= cnt; shift++) {
+        msb = s & 0x8000;
+        cf = s & 1;
+        s = (s >> 1) | msb;
+      }
+      of = 0;
+      flag_szp16((uint16_t)s); break;
+
+  }
+  return ((uint16_t)s);
+}
+
+inline void op_div8(uint16_t valdiv, uint8_t divisor) {
+  if (divisor == 0) {
+    intcall86(0);
+    return;
+  }
+  if ((valdiv / (uint16_t)divisor) > 0xFF) {
+    intcall86(0);
+    return;
+  }
+  regs.byteregs[regah] = valdiv % (uint16_t)divisor;
+  regs.byteregs[regal] = valdiv / (uint16_t)divisor;
+}
+
+inline void op_idiv8(uint16_t valdiv, uint8_t divisor) {
+  uint16_t s1, s2, d1, d2, sign;
+  if (divisor == 0) {
+    intcall86(0);
+    return;
+  }
+  s1 = valdiv;
+  s2 = divisor;
+  sign = (((s1 ^ s2) & 0x8000) != 0);
+  s1 = (s1 < 0x8000) ? s1 : (uint16_t)(~s1 + 1);
+  s2 = (s2 < 0x8000) ? s2 : (uint16_t)(~s2 + 1);
+  d1 = s1 / s2;
+  d2 = s1 % s2;
+  if (d1 & 0xFF00) {
+    intcall86(0);
+    return;
+  }
+  if (sign) {
+    d1 = (~d1 + 1) & 0xff;
+    d2 = (~d2 + 1) & 0xff;
+  }
+  regs.byteregs[regah] = d2;
+  regs.byteregs[regal] = d1;
+}
+
+inline void op_grp3_8() {
+  oper1 = signext(oper1b); oper2 = signext(oper2b);
+  switch (reg) {
+    case 0: case 1: //TEST
+      flag_log8(oper1b & getmem8(segregs[regcs], ip)); StepIP(1);
+      break;
+
+    case 2: //NOT
+      res8 = ~oper1b; break;
+
+    case 3: //NEG
+      res8 = (~oper1b) + 1;
+      flag_sub8(0, oper1b);
+      if (res8 == 0) cf = 0; else cf = 1;
+      break;
+
+    case 4: //MUL
+      temp1 = (uint32_t)oper1b * (uint32_t)regs.byteregs[regal];
+      putreg16(regax, (uint16_t)temp1);
+      flag_szp8((uint8_t)temp1);
+      if (regs.byteregs[regah]) {
+        cf = 1;
+        of = 1;
+      } else {
+        cf = 0;
+        of = 0;
+      }
+      break;
+
+    case 5: //IMUL
+      oper1 = signext(oper1b);
+      temp1 = signext(regs.byteregs[regal]);
+      temp2 = oper1;
+      if ((temp1 & 0x80) == 0x80) temp1 = temp1 | 0xFFFFFF00UL;
+      if ((temp2 & 0x80) == 0x80) temp2 = temp2 | 0xFFFFFF00UL;
+      temp3 = (uint16_t)(temp1 * temp2);
+      putreg16(regax, (uint16_t)temp3);
+      if (regs.byteregs[regah]) {
+        cf = 1;
+        of = 1;
+      } else {
+        cf = 0;
+        of = 0;
+      }
+      break;
+
+    case 6: //DIV
+      op_div8(getreg16(regax), oper1b);
+      break;
+
+    case 7: //IDIV
+      op_idiv8(getreg16(regax), oper1b);
+      break;
+  }
+}
+
+void op_div16(uint32_t valdiv, uint16_t divisor) {
+  if (divisor == 0) {
+    intcall86(0);
+    return;
+  }
+  if ((valdiv / (uint32_t)divisor) > 0xFFFF) {
+    intcall86(0);
+    return;
+  }
+  putreg16(regdx, valdiv % (uint32_t)divisor);
+  putreg16(regax, valdiv / (uint32_t)divisor);
+}
+
+void op_idiv16(uint32_t valdiv, uint16_t divisor) {
+  uint32_t d1, d2, s1, s2, sign;
+  if (divisor == 0) {
+    intcall86(0);
+    return;
+  }
+  s1 = valdiv;
+  s2 = divisor;
+  s2 = (s2 & 0x8000) ? (s2 | 0xffff0000UL) : s2;
+  sign = (((s1 ^ s2) & 0x80000000UL) != 0);
+  s1 = (s1 < 0x80000000UL) ? s1 : ((~s1 + 1) & 0xffffffffUL);
+  s2 = (s2 < 0x80000000UL) ? s2 : ((~s2 + 1) & 0xffffffffUL);
+  d1 = s1 / s2;
+  d2 = s1 % s2;
+  if (d1 & 0xFFFF0000UL) {
+    intcall86(0);
+    return;
+  }
+  if (sign) {
+    d1 = (uint16_t)(~d1 + 1);
+    d2 = (uint16_t)(~d2 + 1);
+  }
+  putreg16(regax, d1);
+  putreg16(regdx, d2);
+}
+
+inline void op_grp3_16() {
+  switch (reg) {
+    case 0: case 1: //TEST
+      flag_log16(oper1 & getmem16(segregs[regcs], ip)); StepIP(2); break;
+    case 2: //NOT
+      res16 = ~oper1; break;
+    case 3: //NEG
+      res16 = (~oper1) + 1;
+      flag_sub16(0, oper1);
+      if (res16) cf = 1; else cf = 0;
+      break;
+    case 4: //MUL
+      temp1 = (uint32_t)oper1 * (uint32_t)getreg16(regax);
+      putreg16(regax, (uint16_t)temp1);
+      putreg16(regdx, temp1 >> 16);
+      flag_szp16((uint16_t)temp1);
+      if (getreg16(regdx)) {
+        cf = 1;
+        of = 1;
+      } else {
+        cf = 0;
+        of = 0;
+      }
+      break;
+    case 5: //IMUL
+      temp1 = getreg16(regax);
+      temp2 = oper1;
+      if (temp1 & 0x8000) temp1 |= 0xFFFF0000UL;
+      if (temp2 & 0x8000) temp2 |= 0xFFFF0000UL;
+      temp3 = temp1 * temp2;
+      putreg16(regax, (uint16_t)temp3); //into register ax
+      putreg16(regdx, temp3 >> 16); //into register dx
+      if (getreg16(regdx)) {
+        cf = 1;
+        of = 1;
+      } else {
+        cf = 0;
+        of = 0;
+      }
+      break;
+    case 6: //DIV
+      op_div16(((uint32_t)getreg16(regdx) << 16) + (uint32_t)getreg16(regax), oper1); break;
+    case 7: //DIV
+      op_idiv16(((uint32_t)getreg16(regdx) << 16) + (uint32_t)getreg16(regax), oper1); break;
+  }
+}
+
+//inline void op_grp5() {
+#define op_grp5() {\
+  switch (reg) {\
+    case 0: /*INC Ev*/\
+      oper2 = 1;\
+      tempcf = cf;\
+      op_add16();\
+      cf = tempcf;\
+      writerm16(rm, res16); break;\
+    case 1: /*DEC Ev*/\
+      oper2 = 1;\
+      tempcf = cf;\
+      op_sub16();\
+      cf = tempcf;\
+      writerm16(rm, res16); break;\
+    case 2: /*CALL Ev*/\
+      push(ip);\
+      ip = oper1; break;\
+    case 3: /*CALL Mp*/\
+      push(segregs[regcs]); push(ip);\
+      /*getea(rm);*/\
+      ip = (uint16_t)read86(ea) + ((uint16_t)read86(ea + 1) << 8);\
+      segregs[regcs] = (uint16_t)read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); break;\
+    case 4: /*JMP Ev*/\
+      ip = oper1; break;\
+    case 5: /*JMP Mp*/\
+      /*getea(rm);*/\
+      ip = (uint16_t)read86(ea) + ((uint16_t)read86(ea + 1) << 8);\
+      segregs[regcs] = (uint16_t)read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); break;\
+    case 6: /*PUSH Ev*/\
+      push(oper1); break;\
+  }\
+}
+
+uint8_t didintr = 0;
+
+void intcall86(uint8_t intnum) {
+  didintr = 1;
+
+  switch (intnum) {
+    case 0x10: //video services
+      if (regs.byteregs[regah] == 0) { //video mode set
+#ifdef ADVANCED_CLIENT
+      Serial.write(0xFF);
+      Serial.write(0x02);
+      Serial.write(regs.byteregs[regal]);
+      Serial.write(regs.byteregs[regal]); //duplicate for checksum
+      Serial.write(0xFE);
+      Serial.write(0x02);
+#endif
+#ifdef USE_DISPLAY
+        if (vidmode != regs.byteregs[regal]) clear_display();
+        palettereset();
+#endif
+        vidmode = regs.byteregs[regal];
+        //Serial.print("vidmode = "); Serial.println(vidmode);
+      }
+      break;
+    case 0x13: //disk services
+      diskhandler();
+      return;
+    case 0x19: //bootstrap
+      //Serial.println("Bootstrap!");
+      if (bootdrive < 255) { //read first sector of boot drive into 07C0:0000 and execute it
+        regs.byteregs[regdl] = bootdrive;
+        readdisk((bootdrive & 0x80) ? bootdrive - 126 : bootdrive, 0x07C0, 0x0000, 0, 1, 0, 1);
+        segregs[regcs] = 0x0000; ip = 0x7C00;
+      } else {
+        segregs[regcs] = 0xF600;  //start ROM BASIC at bootstrap if requested
+        ip = 0x0000;
+      }
+      return;
+    case 0xFC:
+      net_handler();
+      return;
+    default:
+      break;
+  }
+
+  push(makeflagsword());
+  push(segregs[regcs]);
+  push(ip);
+  segregs[regcs] = getmem16(0, ((uint16_t)intnum << 2) + 2);
+  ip = getmem16(0, (uint16_t)intnum << 2);
+  ifl = 0;
+  tf = 0;
+}
+
+uint64_t frametimer = 0, didwhen = 0, didticks = 0;
+uint32_t makeupticks = 0;
+extern float timercomp;
+uint64_t timerticks = 0, realticks = 0;
+uint64_t lastcountertimer = 0, counterticks = 10000;
+
+#ifdef PROFILING
+uint32_t startmicros, endmicros;
+uint32_t instrtime[0x100];
+#endif
+
+#ifdef PS2_KEYBOARD
+extern uint8_t kbloop;
+#endif
+
+extern volatile uint8_t timerTick;
+
+void exec86(uint32_t execloops) {
+  uint32_t loopcount;
+  uint8_t docontinue;
+  static uint16_t firstip, trap_toggle = 0;
+
+  for (loopcount = 0; loopcount < execloops; loopcount++) {
+    /*Serial.print(segregs[regcs], HEX);
+    Serial.write(':');
+    Serial.println(ip, HEX);*/
+    #ifdef PS2_KEYBOARD
+    if (kbloop) {
+      uint32_t msnow;
+      msnow = micros();
+      while ((micros() - msnow) < 20000) { }
+      kbloop = 0;
+      ps2poll();
+    }
+    #endif
+
+    if (timerTick) {
+      //printf("isr\n");
+      timerTick = 0;
+      doirq(0);
+    }
+    
+    if (trap_toggle) intcall86(1);
+    if (tf)  trap_toggle = 1;
+    else trap_toggle = 0;
+    if (!trap_toggle && (ifl && (i8259.irr & (~i8259.imr)))) intcall86(nextintr()); //get next interrupt from the i8259, if any
+    reptype = 0; segoverride = 0;
+    useseg = segregs[regds]; docontinue = 0;
+    firstip = ip;
+    while (!docontinue) {
+      segregs[regcs] = segregs[regcs] & 0xFFFF; ip = ip & 0xFFFF;
+      savecs = segregs[regcs]; saveip = ip;
+      opcode = getmem8(segregs[regcs], ip); StepIP(1);
+
+      switch (opcode) {
+        //segment prefix check
+        case 0x2E: //segment segregs[regcs]
+          useseg = segregs[regcs]; segoverride = 1; break;
+        case 0x3E: //segment segregs[regds]
+          useseg = segregs[regds]; segoverride = 1; break;
+        case 0x26: //segment segregs[reges]
+          useseg = segregs[reges]; segoverride = 1; break;
+        case 0x36: //segment segregs[regss]
+          useseg = segregs[regss]; segoverride = 1; break;
+
+        //repetition prefix check
+        case 0xF3: //REP/REPE/REPZ
+          reptype = 1; break;
+        case 0xF2: //REPNE/REPNZ
+          reptype = 2; break;
+        default:
+          docontinue = 1;
+          break;
+      }
+    }
+    totalexec++;
+    //printf("%04X:%04X %02X\n", segregs[regcs], ip, opcode);
+    //if ((segregs[regcs]==0xF000) && (ip < 0xE000)) exit(0);
+
+#ifdef PROFILING
+    startmicros = micros();
+#endif
+    switch (opcode) {
+      case 0x0: //00 ADD Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_add8();
+        writerm8(rm, res8);
+        break;
+      case 0x1: //01 ADD Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_add16();
+        writerm16(rm, res16);
+        break;
+      case 0x2: //02 ADD Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_add8();
+        putreg8(reg, res8);
+        break;
+      case 0x3: //03 ADD Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_add16();
+        putreg16(reg, res16);
+        break;
+      case 0x4: //04 ADD regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_add8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x5: //05 ADD eAX Iv
+        oper1 = (getreg16(regax)); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_add16();
+        putreg16(regax, res16);
+        break;
+      case 0x6: //06 PUSH segregs[reges]
+        push(segregs[reges]);
+        break;
+      case 0x7: //07 POP segregs[reges]
+        segregs[reges] = pop();
+        break;
+      case 0x8: //08 OR Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_or8();
+        writerm8(rm, res8);
+        break;
+      case 0x9: //09 OR Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_or16();
+        writerm16(rm, res16);
+        break;
+      case 0xA: //0A OR Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_or8();
+        putreg8(reg, res8);
+        break;
+      case 0xB: //0B OR Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_or16();
+        if ((oper1 == 0xF802) && (oper2 == 0xF802)) sf = 0; //cheap hack to make Wolf 3D think we're a 286 so it plays
+        putreg16(reg, res16);
+        break;
+      case 0xC: //0C OR regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_or8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0xD: //0D OR eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_or16();
+        putreg16(regax, res16);
+        break;
+      case 0xE: //0E PUSH segregs[regcs]
+        push(segregs[regcs]);
+        break;
+      case 0xF: //0F POP CS
+        segregs[regcs] = pop();
+        break;
+      /*case 0xF: //0F 80286+ extended opcodes
+          segregs[regcs] = segregs[regcs] & 0xFFFF; ip = ip & 0xFFFF;
+          savecs = segregs[regcs]; saveip = ip;
+          opcode = getmem8(segregs[regcs], ip); StepIP(1);
+          op_286();
+          break;*/
+      case 0x10: //10 ADC Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_adc8();
+        writerm8(rm, res8);
+        break;
+      case 0x11: //11 ADC Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_adc16();
+        writerm16(rm, res16);
+        break;
+      case 0x12: //12 ADC Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_adc8();
+        putreg8(reg, res8);
+        break;
+      case 0x13: //13 ADC Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_adc16();
+        putreg16(reg, res16);
+        break;
+      case 0x14: //14 ADC regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_adc8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x15: //15 ADC eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_adc16();
+        putreg16(regax, res16);
+        break;
+      case 0x16: //16 PUSH segregs[regss]
+        push(segregs[regss]);
+        break;
+      case 0x17: //17 POP segregs[regss]
+        segregs[regss] = pop();
+        break;
+      case 0x18: //18 SBB Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_sbb8();
+        writerm8(rm, res8);
+        break;
+      case 0x19: //19 SBB Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_sbb16();
+        writerm16(rm, res16);
+        break;
+      case 0x1A: //1A SBB Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_sbb8();
+        putreg8(reg, res8);
+        break;
+      case 0x1B: //1B SBB Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_sbb16();
+        putreg16(reg, res16);
+        break;
+      case 0x1C: //1C SBB regs.byteregs[regal] Ib;
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_sbb8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x1D: //1D SBB eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_sbb16();
+        putreg16(regax, res16);
+        break;
+      case 0x1E: //1E PUSH segregs[regds]
+        push(segregs[regds]);
+        break;
+      case 0x1F: //1F POP segregs[regds]
+        segregs[regds] = pop();
+        break;
+      case 0x20: //20 AND Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_and8();
+        writerm8(rm, res8);
+        break;
+      case 0x21: //21 AND Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_and16();
+        writerm16(rm, res16);
+        break;
+      case 0x22: //22 AND Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_and8();
+        putreg8(reg, res8);
+        break;
+      case 0x23: //23 AND Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_and16();
+        putreg16(reg, res16);
+        break;
+      case 0x24: //24 AND regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_and8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x25: //25 AND eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_and16();
+        putreg16(regax, res16);
+        break;
+      case 0x27: //27 DAA
+        if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) {
+          oper1 = regs.byteregs[regal] + 6;
+          regs.byteregs[regal] = oper1 & 255;
+          if (oper1 & 0xFF00) cf = 1; else cf = 0;
+          af = 1;
+        } else af = 0;
+        if (((regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1)) {
+          regs.byteregs[regal] = regs.byteregs[regal] + 0x60;
+          cf = 1;
+        } else cf = 0;
+        regs.byteregs[regal] = regs.byteregs[regal] & 255;
+        flag_szp8(regs.byteregs[regal]);
+        break;
+      case 0x28: //28 SUB Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_sub8();
+        writerm8(rm, res8);
+        break;
+      case 0x29: //29 SUB Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_sub16();
+        writerm16(rm, res16);
+        break;
+      case 0x2A: //2A SUB Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_sub8();
+        putreg8(reg, res8);
+        break;
+      case 0x2B: //2B SUB Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_sub16();
+        putreg16(reg, res16);
+        break;
+      case 0x2C: //2C SUB regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_sub8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x2D: //2D SUB eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_sub16();
+        putreg16(regax, res16);
+        break;
+      case 0x2F: //2F DAS
+        if (((regs.byteregs[regal] & 15) > 9) || (af == 1)) {
+          oper1 = regs.byteregs[regal] - 6;
+          regs.byteregs[regal] = oper1 & 255;
+          if (oper1 & 0xFF00) cf = 1; else cf = 0;
+          af = 1;
+        } else af = 0;
+        if (((regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1)) {
+          regs.byteregs[regal] = regs.byteregs[regal] - 0x60;
+          cf = 1;
+        } else cf = 0;
+        flag_szp8(regs.byteregs[regal]);
+        break;
+      case 0x30: //30 XOR Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        op_xor8();
+        writerm8(rm, res8);
+        break;
+      case 0x31: //31 XOR Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        op_xor16();
+        writerm16(rm, res16);
+        break;
+      case 0x32: //32 XOR Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        op_xor8();
+        putreg8(reg, res8);
+        break;
+      case 0x33: //33 XOR Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        op_xor16();
+        putreg16(reg, res16);
+        break;
+      case 0x34: //34 XOR regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        op_xor8();
+        regs.byteregs[regal] = res8;
+        break;
+      case 0x35: //35 XOR eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        op_xor16();
+        putreg16(regax, res16);
+        break;
+      case 0x37: //37 AAA ASCII
+        if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) {
+          regs.byteregs[regal] = regs.byteregs[regal] + 6;
+          regs.byteregs[regah] = regs.byteregs[regah] + 1;
+          af = 1;
+          cf = 1;
+        } else {
+          af = 0;
+          cf = 0;
+        }
+        regs.byteregs[regal] = regs.byteregs[regal] & 0xF;
+        break;
+      case 0x38: //38 CMP Eb Gb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = getreg8(reg);
+        flag_sub8(oper1b, oper2b);
+        break;
+      case 0x39: //39 CMP Ev Gv
+        modregrm();
+        oper1 = readrm16(rm); oper2 = getreg16(reg);
+        flag_sub16(oper1, oper2);
+        break;
+      case 0x3A: //3A CMP Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        flag_sub8(oper1b, oper2b);
+        break;
+      case 0x3B: //3B CMP Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        flag_sub16(oper1, oper2);
+        break;
+      case 0x3C: //3C CMP regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        flag_sub8(oper1b, oper2b);
+        break;
+      case 0x3D: //3D CMP eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        flag_sub16(oper1, oper2);
+        break;
+      case 0x3F: //3F AAS ASCII
+        if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) {
+          regs.byteregs[regal] = regs.byteregs[regal] - 6;
+          regs.byteregs[regah] = regs.byteregs[regah] - 1;
+          af = 1;
+          cf = 1;
+        } else {
+          af = 0;
+          cf = 0;
+        }
+        regs.byteregs[regal] = regs.byteregs[regal] & 0xF;
+        break;
+      case 0x40: //40 INC eAX
+        oldcf = cf;
+        oper1 = getreg16(regax); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regax, res16);
+        break;
+      case 0x41: //41 INC eCX
+        oldcf = cf;
+        oper1 = getreg16(regcx); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regcx, res16);
+        break;
+      case 0x42: //42 INC eDX
+        oldcf = cf;
+        oper1 = getreg16(regdx); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regdx, res16);
+        break;
+      case 0x43: //43 INC eBX
+        oldcf = cf;
+        oper1 = getreg16(regbx); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regbx, res16);
+        break;
+      case 0x44: //44 INC eSP
+        oldcf = cf;
+        oper1 = getreg16(regsp); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regsp, res16);
+        break;
+      case 0x45: //45 INC eBP
+        oldcf = cf;
+        oper1 = getreg16(regbp); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regbp, res16);
+        break;
+      case 0x46: //46 INC eSI
+        oldcf = cf;
+        oper1 = getreg16(regsi); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regsi, res16);
+        break;
+      case 0x47: //47 INC eDI
+        oldcf = cf;
+        oper1 = getreg16(regdi); oper2 = 1;
+        op_add16();
+        cf = oldcf;
+        putreg16(regdi, res16);
+        break;
+      case 0x48: //48 DEC eAX
+        oldcf = cf;
+        oper1 = getreg16(regax); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regax, res16);
+        break;
+      case 0x49: //49 DEC eCX
+        oldcf = cf;
+        oper1 = getreg16(regcx); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regcx, res16);
+        break;
+      case 0x4A: //4A DEC eDX
+        oldcf = cf;
+        oper1 = getreg16(regdx); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regdx, res16);
+        break;
+      case 0x4B: //4B DEC eBX
+        oldcf = cf;
+        oper1 = getreg16(regbx); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regbx, res16);
+        break;
+      case 0x4C: //4C DEC eSP
+        oldcf = cf;
+        oper1 = getreg16(regsp); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regsp, res16);
+        break;
+      case 0x4D: //4D DEC eBP
+        oldcf = cf;
+        oper1 = getreg16(regbp); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regbp, res16);
+        break;
+      case 0x4E: //4E DEC eSI
+        oldcf = cf;
+        oper1 = getreg16(regsi); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regsi, res16);
+        break;
+      case 0x4F: //4F DEC eDI
+        oldcf = cf;
+        oper1 = getreg16(regdi); oper2 = 1;
+        op_sub16();
+        cf = oldcf;
+        putreg16(regdi, res16);
+        break;
+      case 0x50: //50 PUSH eAX
+        push (getreg16(regax));
+        break;
+      case 0x51: //51 PUSH eCX
+        push (getreg16(regcx));
+        break;
+      case 0x52: //52 PUSH eDX
+        push (getreg16(regdx));
+        break;
+      case 0x53: //53 PUSH eBX
+        push (getreg16(regbx));
+        break;
+      case 0x54: //54 PUSH eSP
+        push (getreg16(regsp) - 2);
+        break;
+      case 0x55: //55 PUSH eBP
+        push (getreg16(regbp));
+        break;
+      case 0x56: //56 PUSH eSI
+        push (getreg16(regsi));
+        break;
+      case 0x57: //57 PUSH eDI
+        push (getreg16(regdi));
+        break;
+      case 0x58: //58 POP eAX
+        putreg16(regax, pop());
+        break;
+      case 0x59: //59 POP eCX
+        putreg16(regcx, pop());
+        break;
+      case 0x5A: //5A POP eDX
+        putreg16(regdx, pop());
+        break;
+      case 0x5B: //5B POP eBX
+        putreg16(regbx, pop());
+        break;
+      case 0x5C: //5C POP eSP
+        putreg16(regsp, pop());
+        break;
+      case 0x5D: //5D POP eBP
+        putreg16(regbp, pop());
+        break;
+      case 0x5E: //5E POP eSI
+        putreg16(regsi, pop());
+        break;
+      case 0x5F: //5F POP eDI
+        putreg16(regdi, pop());
+        break;
+      case 0x60: //60 PUSHA (80186+)
+        oldsp = getreg16(regsp);
+        push(getreg16(regax));
+        push(getreg16(regcx));
+        push(getreg16(regdx));
+        push(getreg16(regbx));
+        push(oldsp);
+        push(getreg16(regbp));
+        push(getreg16(regsi));
+        push(getreg16(regdi));
+        break;
+      case 0x61: //61 POPA (80186+)
+        putreg16(regdi, pop());
+        putreg16(regsi, pop());
+        putreg16(regbp, pop());
+        dummy = pop();
+        putreg16(regbx, pop());
+        putreg16(regdx, pop());
+        putreg16(regcx, pop());
+        putreg16(regax, pop());
+        break;
+      case 0x68: //68 PUSH Iv (80186+)
+        push(getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0x69: //69 IMUL Gv Ev Iv (80186+)
+        //print("WE HIT 69h IMUL\r\n");
+        modregrm();
+        temp1 = readrm16(rm);
+        temp2 = getmem16(segregs[regcs], ip); StepIP(2);
+        if ((temp1 & 0x8000L) == 0x8000L) temp1 = temp1 | 0xFFFF0000L;
+        if ((temp2 & 0x8000L) == 0x8000L) temp2 = temp2 | 0xFFFF0000L;
+        temp3 = temp1 * temp2;
+        putreg16(reg, temp3 & 0xFFFFL);
+        if (temp3 & 0xFFFF0000L) {
+          cf = 1;
+          of = 1;
+        } else {
+          cf = 0;
+          of = 0;
+        }
+        break;
+      case 0x6A: //6A PUSH Ib (80186+)
+        push(getmem8(segregs[regcs], ip)); StepIP(1);
+        break;
+      case 0x6B: //6B IMUL Gv Eb Ib (80186+)
+        //print("WE HIT 6Bh IMUL\r\n");
+        modregrm();
+        temp1 = readrm16(rm);
+        temp2 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if ((temp1 & 0x8000L) == 0x8000L) temp1 = temp1 | 0xFFFF0000L;
+        if ((temp2 & 0x8000L) == 0x8000L) temp2 = temp2 | 0xFFFF0000L;
+        temp3 = temp1 * temp2;
+        putreg16(reg, temp3 & 0xFFFFL);
+        if (temp3 & 0xFFFF0000L) {
+          cf = 1;
+          of = 1;
+        } else {
+          cf = 0;
+          of = 0;
+        }
+        break;
+      //case 0x6C ... 0x6F: //80186 port operations, just act as if they//re NOPs for now...
+      //    StepIP(1); //they have a modregrm(); byte we must skip... i may properly emulate these later.
+      //    break;
+      case 0x6E: //6E OUTSB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        portout16 = 0;
+        portout(regs.wordregs[regdx], getmem16(useseg, getreg16(regsi)));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 1);
+          putreg16(regdi, getreg16(regdi) - 1);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 1);
+          putreg16(regdi, getreg16(regdi) + 1);
+        }
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0x6F: //6F OUTSW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        portout16 = 1;
+        portout(regs.wordregs[regdx], getmem16(useseg, getreg16(regsi)));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 2);
+          putreg16(regdi, getreg16(regdi) - 2);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 2);
+          putreg16(regdi, getreg16(regdi) + 2);
+        }
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+
+      case 0x70: //70 JO Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (of) ip = ip + temp16;
+        break;
+      case 0x71: //71 JNO Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!of) ip = ip + temp16;
+        break;
+      case 0x72: //72 JB Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (cf) ip = ip + temp16;
+        break;
+      case 0x73: //73 JNB Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!cf) ip = ip + temp16;
+        break;
+      case 0x74: //74 JZ Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (zf) ip = ip + temp16;
+        break;
+      case 0x75: //75 JNZ Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!zf) ip = ip + temp16;
+        break;
+      case 0x76: //76 JBE Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (cf || zf) ip = ip + temp16;
+        break;
+      case 0x77: //77 JA Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!cf && !zf) ip = ip + temp16;
+        break;
+      case 0x78: //78 JS Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (sf) ip = ip + temp16;
+        break;
+      case 0x79: //79 JNS Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!sf) ip = ip + temp16;
+        break;
+      case 0x7A: //7A JPE Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (pf) ip = ip + temp16;
+        break;
+      case 0x7B: //7B JPO Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!pf) ip = ip + temp16;
+        break;
+      case 0x7C: //7C JL Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (sf != of) ip = ip + temp16;
+        break;
+      case 0x7D: //7D JGE Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (sf == of) ip = ip + temp16;
+        break;
+      case 0x7E: //7E JLE Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if ((sf != of) || zf) ip = ip + temp16;
+        break;
+      case 0x7F: //7F JG Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!zf && (sf == of)) ip = ip + temp16;
+        break;
+      case 0x80: case 0x82: //80/82 GRP1 Eb Ib
+        modregrm();
+        oper1b = readrm8(rm);
+        oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        switch (reg) {
+          case 0: op_add8(); break;
+          case 1: op_or8(); break;
+          case 2: op_adc8(); break;
+          case 3: op_sbb8(); break;
+          case 4: op_and8(); break;
+          case 5: op_sub8(); break;
+          case 6: op_xor8(); break;
+          case 7: flag_sub8(oper1b, oper2b); break;
+          default: break; //to avoid compiler warnings
+        }
+        if (reg < 7) writerm8(rm, res8);
+        break;
+      case 0x81: //81 GRP1 Ev Iv
+      case 0x83: //83 GRP1 Ev Ib
+        modregrm();
+        oper1 = readrm16(rm);
+        if (opcode == 0x81) {
+          oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        } else {
+          oper2 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        }
+        switch (reg) {
+          case 0: op_add16(); break;
+          case 1: op_or16(); break;
+          case 2: op_adc16(); break;
+          case 3: op_sbb16(); break;
+          case 4: op_and16(); break;
+          case 5: op_sub16(); break;
+          case 6: op_xor16(); break;
+          case 7: flag_sub16(oper1, oper2); break;
+          default: break; //to avoid compiler warnings
+        }
+        if (reg < 7) writerm16(rm, res16);
+        break;
+      case 0x84: //84 TEST Gb Eb
+        modregrm();
+        oper1b = getreg8(reg); oper2b = readrm8(rm);
+        flag_log8(oper1b & oper2b);
+        break;
+      case 0x85: //85 TEST Gv Ev
+        modregrm();
+        oper1 = getreg16(reg); oper2 = readrm16(rm);
+        flag_log16(oper1 & oper2);
+        break;
+      case 0x86: //86 XCHG Gb Eb
+        modregrm();
+        oper1b = getreg8(reg);
+        putreg8(reg, readrm8(rm));
+        writerm8(rm, oper1b);
+        break;
+      case 0x87: //87 XCHG Gv Ev
+        modregrm();
+        oper1 = getreg16(reg);
+        putreg16(reg, readrm16(rm));
+        writerm16(rm, oper1);
+        break;
+      case 0x88: //88 MOV Eb Gb
+        modregrm();
+        writerm8(rm, getreg8(reg));
+        break;
+      case 0x89: //89 MOV Ev Gv
+        modregrm();
+        writerm16(rm, getreg16(reg));
+        break;
+      case 0x8A: //8A MOV Gb Eb
+        modregrm();
+        putreg8(reg, readrm8(rm));
+        break;
+      case 0x8B: //8B MOV Gv Ev
+        modregrm();
+        putreg16(reg, readrm16(rm));
+        break;
+      case 0x8C: //8C MOV Ew Sw
+        modregrm();
+        writerm16(rm, getsegreg(reg));
+        break;
+      case 0x8D: //8D LEA Gv M
+        modregrm();
+        //getea(rm);
+        putreg16(reg, ea - segbase(useseg));
+        break;
+      case 0x8E: //8E MOV Sw Ew
+        modregrm();
+        putsegreg(reg, readrm16(rm));
+        break;
+      case 0x8F: //8F POP Ev
+        modregrm();
+        writerm16(rm, pop());
+        break;
+      case 0x90: //90 NOP
+        break;
+      case 0x91: //91 XCHG eCX eAX
+        oper1 = getreg16(regcx);
+        putreg16(regcx, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x92: //92 XCHG eDX eAX
+        oper1 = getreg16(regdx);
+        putreg16(regdx, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x93: //93 XCHG eBX eAX
+        oper1 = getreg16(regbx);
+        putreg16(regbx, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x94: //94 XCHG eSP eAX
+        oper1 = getreg16(regsp);
+        putreg16(regsp, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x95: //95 XCHG eBP eAX
+        oper1 = getreg16(regbp);
+        putreg16(regbp, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x96: //96 XCHG eSI eAX
+        oper1 = getreg16(regsi);
+        putreg16(regsi, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x97: //97 XCHG eDI eAX
+        oper1 = getreg16(regdi);
+        putreg16(regdi, getreg16(regax));
+        putreg16(regax, oper1);
+        break;
+      case 0x98: //98 CBW
+        if ((regs.byteregs[regal] & 0x80) == 0x80) regs.byteregs[regah] = 0xFF; else regs.byteregs[regah] = 0;
+        break;
+      case 0x99: //99 CWD
+        if ((regs.byteregs[regah] & 0x80) == 0x80) putreg16(regdx, 0xFFFF); else putreg16(regdx, 0);
+        break;
+      case 0x9A: //9A CALL Ap
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        push(segregs[regcs]); push(ip); ip = oper1; segregs[regcs] = oper2;
+        break;
+      case 0x9B: //9B WAIT
+        break;
+      case 0x9C: //9C PUSHF
+        push(makeflagsword() | 0xF800);
+        break;
+      case 0x9D: //9D POPF
+        temp16 = pop();
+        decodeflagsword(temp16);
+        break;
+      case 0x9E: //9E SAHF
+        decodeflagsword ((makeflagsword() & 0xFF00) | regs.byteregs[regah]);
+        break;
+      case 0x9F: //9F LAHF
+        regs.byteregs[regah] = makeflagsword() & 0xFF;
+        break;
+      case 0xA0: //A0 MOV regs.byteregs[regal] Ob
+        regs.byteregs[regal] = getmem8(useseg, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xA1: //A1 MOV eAX Ov
+        oper1 = getmem16(useseg, getmem16(segregs[regcs], ip)); StepIP(2);
+        putreg16(regax, oper1);
+        break;
+      case 0xA2: //A2 MOV Ob regs.byteregs[regal]
+        putmem8(useseg, getmem16(segregs[regcs], ip), regs.byteregs[regal]); StepIP(2);
+        break;
+      case 0xA3: //A3 MOV Ov eAX
+        putmem16(useseg, getmem16(segregs[regcs], ip), getreg16(regax)); StepIP(2);
+        break;
+      case 0xA4: //A4 MOVSB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        putmem8(segregs[reges], getreg16(regdi), getmem8(useseg, getreg16(regsi)));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 1);
+          putreg16(regdi, getreg16(regdi) - 1);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 1);
+          putreg16(regdi, getreg16(regdi) + 1);
+        }
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xA5: //A5 MOVSW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        putmem16(segregs[reges], getreg16(regdi), getmem16(useseg, getreg16(regsi)));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 2);
+          putreg16(regdi, getreg16(regdi) - 2);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 2);
+          putreg16(regdi, getreg16(regdi) + 2);
+        }
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xA6: //A6 CMPSB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        oper1b = getmem8(useseg, getreg16(regsi)); oper2b = getmem8(segregs[reges], getreg16(regdi));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 1);
+          putreg16(regdi, getreg16(regdi) - 1);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 1);
+          putreg16(regdi, getreg16(regdi) + 1);
+        }
+        flag_sub8(oper1b, oper2b);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if ((reptype == 1) && !zf) break;
+        else if ((reptype == 2) && (zf == 1)) break;
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xA7: //A7 CMPSW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        oper1 = getmem16(useseg, getreg16(regsi)); oper2 = getmem16(segregs[reges], getreg16(regdi));
+        if (df) {
+          putreg16(regsi, getreg16(regsi) - 2);
+          putreg16(regdi, getreg16(regdi) - 2);
+        }
+        else {
+          putreg16(regsi, getreg16(regsi) + 2);
+          putreg16(regdi, getreg16(regdi) + 2);
+        }
+        flag_sub16(oper1, oper2);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if ((reptype == 1) && !zf) break;
+        if ((reptype == 2) && (zf == 1)) break;
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xA8: //A8 TEST regs.byteregs[regal] Ib
+        oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        flag_log8(oper1b & oper2b);
+        break;
+      case 0xA9: //A9 TEST eAX Iv
+        oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2);
+        flag_log16(oper1 & oper2);
+        break;
+      case 0xAA: //AA STOSB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        putmem8(segregs[reges], getreg16(regdi), regs.byteregs[regal]);
+        if (df) putreg16(regdi, getreg16(regdi) - 1);
+        else putreg16(regdi, getreg16(regdi) + 1);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xAB: //AB STOSW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        putmem16(segregs[reges], getreg16(regdi), getreg16(regax));
+        if (df) putreg16(regdi, getreg16(regdi) - 2);
+        else putreg16(regdi, getreg16(regdi) + 2);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xAC: //AC LODSB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        regs.byteregs[regal] = getmem8(useseg, getreg16(regsi));
+        if (df) putreg16(regsi, getreg16(regsi) - 1);
+        else putreg16(regsi, getreg16(regsi) + 1);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xAD: //AD LODSW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        oper1 = getmem16(useseg, getreg16(regsi));
+        putreg16(regax, oper1);
+        if (df) putreg16(regsi, getreg16(regsi) - 2);
+        else putreg16(regsi, getreg16(regsi) + 2);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xAE: //AE SCASB
+        if (reptype && (getreg16(regcx) == 0)) break;
+        oper1b = getmem8(segregs[reges], getreg16(regdi)); oper2b = regs.byteregs[regal];
+        flag_sub8(oper1b, oper2b);
+        if (df) putreg16(regdi, getreg16(regdi) - 1);
+        else putreg16(regdi, getreg16(regdi) + 1);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if ((reptype == 1) && !zf) break;
+        else if ((reptype == 2) && (zf == 1)) break;
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xAF: //AF SCASW
+        if (reptype && (getreg16(regcx) == 0)) break;
+        oper1 = getmem16(segregs[reges], getreg16(regdi)); oper2 = getreg16(regax);
+        flag_sub16(oper1, oper2);
+        if (df) putreg16(regdi, getreg16(regdi) - 2);
+        else putreg16(regdi, getreg16(regdi) + 2);
+        if (reptype) putreg16(regcx, getreg16(regcx) - 1);
+        if ((reptype == 1) && !zf) break;
+        else if ((reptype == 2) & (zf == 1)) break;
+        if (!reptype) break;
+        ip = firstip;
+        break;
+      case 0xB0: //B0 MOV regs.byteregs[regal] Ib
+        regs.byteregs[regal] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB1: //B1 MOV regs.byteregs[regcl] Ib
+        regs.byteregs[regcl] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB2: //B2 MOV regs.byteregs[regdl] Ib
+        regs.byteregs[regdl] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB3: //B3 MOV regs.byteregs[regbl] Ib
+        regs.byteregs[regbl] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB4: //B4 MOV regs.byteregs[regah] Ib
+        regs.byteregs[regah] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB5: //B5 MOV regs.byteregs[regch] Ib
+        regs.byteregs[regch] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB6: //B6 MOV regs.byteregs[regdh] Ib
+        regs.byteregs[regdh] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB7: //B7 MOV regs.byteregs[regbh] Ib
+        regs.byteregs[regbh] = getmem8(segregs[regcs], ip); StepIP(1);
+        break;
+      case 0xB8: //B8 MOV eAX Iv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        putreg16(regax, oper1);
+        break;
+      case 0xB9: //B9 MOV eCX Iv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        putreg16(regcx, oper1);
+        break;
+      case 0xBA: //BA MOV eDX Iv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        putreg16(regdx, oper1);
+        break;
+      case 0xBB: //BB MOV eBX Iv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        putreg16(regbx, oper1);
+        break;
+      case 0xBC: //BC MOV eSP Iv
+        putreg16(regsp, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xBD: //BD MOV eBP Iv
+        putreg16(regbp, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xBE: //BE MOV eSI Iv
+        putreg16(regsi, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xBF: //BF MOV eDI Iv
+        putreg16(regdi, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xC0: //C0 GRP2 byte imm8 (80186+)
+        modregrm();
+        oper1b = readrm8(rm);
+        oper2b = getmem8(segregs[regcs], ip); StepIP(1);
+        writerm8(rm, op_grp2_8(oper2b));
+        break;
+      case 0xC1: //C1 GRP2 word imm8 (80186+)
+        modregrm();
+        oper1 = readrm16(rm);
+        oper2 = getmem8(segregs[regcs], ip); StepIP(1);
+        writerm16(rm, op_grp2_16(oper2));
+        break;
+      case 0xC2: //C2 RET Iw
+        oper1 = getmem16(segregs[regcs], ip);
+        ip = pop();
+        putreg16(regsp, getreg16(regsp) + oper1);
+        break;
+      case 0xC3: //C3 RET
+        ip = pop();
+        break;
+      case 0xC4: //C4 LES Gv Mp
+        modregrm();
+        //getea(rm);
+        putreg16(reg, read86(ea) + ((uint16_t)read86(ea + 1) << 8));
+        segregs[reges] = read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8);
+        break;
+      case 0xC5: //C5 LDS Gv Mp
+        modregrm();
+        //getea(rm);
+        putreg16(reg, read86(ea) + ((uint16_t)read86(ea + 1) << 8));
+        segregs[regds] = read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8);
+        break;
+      case 0xC6: //C6 MOV Eb Ib
+        modregrm();
+        writerm8(rm, getmem8(segregs[regcs], ip)); StepIP(1);
+        break;
+      case 0xC7: //C7 MOV Ev Iv
+        modregrm();
+        writerm16(rm, getmem16(segregs[regcs], ip)); StepIP(2);
+        break;
+      case 0xC8: //C8 ENTER (80186+)
+        stacksize = getmem16(segregs[regcs], ip); StepIP(2);
+        nestlev = getmem8(segregs[regcs], ip); StepIP(1);
+        push(getreg16(regbp));
+        frametemp = getreg16(regsp);
+        if (nestlev) {
+          for (temp16 = 1; temp16 < nestlev; temp16++) {
+            putreg16(regbp, getreg16(regbp) - 2);
+            push(getreg16(regbp));
+          }
+          push(getreg16(regsp));
+        }
+        putreg16(regbp, frametemp);
+        putreg16(regsp, getreg16(regbp) - stacksize);
+
+        break;
+      case 0xC9: //C9 LEAVE (80186+)
+        putreg16(regsp, getreg16(regbp));
+        putreg16(regbp, pop());
+
+        break;
+      case 0xCA: //CA RETF Iw
+        oper1 = getmem16(segregs[regcs], ip);
+        ip = pop(); segregs[regcs] = pop();
+        putreg16(regsp, getreg16(regsp) + oper1);
+        break;
+      case 0xCB: //CB RETF
+        ip = pop();; segregs[regcs] = pop();
+        break;
+      case 0xCC: //CC INT 3
+        intcall86(3);
+        break;
+      case 0xCD: //CD INT Ib
+        oper1 = getmem8(segregs[regcs], ip); StepIP(1);
+        intcall86(oper1);
+        break;
+      case 0xCE: //CE INTO
+        if (of) intcall86(4);
+        break;
+      case 0xCF: //CF IRET
+        ip = pop(); segregs[regcs] = pop();
+        decodeflagsword(pop());
+        //if (net.enabled) net.canrecv = 1;
+        break;
+      case 0xD0: //D0 GRP2 Eb 1
+        modregrm();
+        oper1b = readrm8(rm);
+        writerm8(rm, op_grp2_8(1));
+        break;
+      case 0xD1: //D1 GRP2 Ev 1
+        modregrm();
+        oper1 = readrm16(rm);
+        writerm16(rm, op_grp2_16(1));
+        break;
+      case 0xD2: //D2 GRP2 Eb regs.byteregs[regcl]
+        modregrm();
+        oper1b = readrm8(rm);
+        writerm8(rm, op_grp2_8(regs.byteregs[regcl]));
+        break;
+      case 0xD3: //D3 GRP2 Ev regs.byteregs[regcl]
+        modregrm();
+        oper1 = readrm16(rm);
+        writerm16(rm, op_grp2_16(regs.byteregs[regcl]));
+        break;
+      case 0xD4: //D4 AAM I0
+        oper1 = getmem8(segregs[regcs], ip); StepIP(1);
+        if (!oper1) {
+          intcall86(0);  //division by zero
+          return;
+        }
+        regs.byteregs[regah] = (regs.byteregs[regal] / oper1) & 255;
+        regs.byteregs[regal] = (regs.byteregs[regal] % oper1) & 255;
+        flag_szp16 (getreg16(regax));
+        break;
+      case 0xD5: //D5 AAD I0
+        oper1 = getmem8(segregs[regcs], ip); StepIP(1);
+        regs.byteregs[regal] = (regs.byteregs[regah] * oper1 + regs.byteregs[regal]) & 255;
+        regs.byteregs[regah] = 0;
+        flag_szp16(regs.byteregs[regah] * oper1 + regs.byteregs[regal]);
+        sf = 0;
+        break;
+      case 0xD6: //D6 XLAT on V20/V30, SALC on 8086/8088
+        regs.byteregs[regal] = cf;
+        break;
+      case 0xD7: //D7 XLAT
+        putreg8(regal, read86(segbase(useseg) + (uint32_t)getreg16(regbx) + (uint32_t)getreg8(regal)));
+        break;
+      case 0xD8: case 0xD9: case 0xDA: case 0xDB: case 0xDC: case 0xDE: case 0xDD: case 0xDF: //escape
+        StepIP(1);
+        break;
+      case 0xE0: //E0 LOOPNZ Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        putreg16(regcx, getreg16(regcx) - 1);
+        if ((getreg16(regcx)) && !zf) ip = ip + temp16;
+        break;
+      case 0xE1: //E1 LOOPZ Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        putreg16(regcx, (getreg16(regcx)) - 1);
+        if ((getreg16(regcx)) && (zf == 1)) ip = ip + temp16;
+        break;
+      case 0xE2: //E2 LOOP Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        putreg16(regcx, (getreg16(regcx)) - 1);
+        if (getreg16(regcx)) ip = ip + temp16;
+        break;
+      case 0xE3: //E3 JCXZ Jb
+        temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        if (!(getreg16(regcx))) ip = ip + temp16;
+        break;
+      case 0xE4: //E4 IN regs.byteregs[regal] Ib
+        oper1b = getmem8(segregs[regcs], ip);
+        StepIP(1);
+        regs.byteregs[regal] = portin(oper1b);
+        break;
+      case 0xE5: //E5 IN eAX Ib
+        oper1b = getmem8(segregs[regcs], ip);
+        StepIP(1);
+        putreg16(regax, portin(oper1b));
+        break;
+      case 0xE6: //E6 OUT Ib regs.byteregs[regal]
+        oper1b = getmem8(segregs[regcs], ip);
+        StepIP(1);
+        portout16 = 0;
+        portout(oper1b, regs.byteregs[regal]);
+        break;
+      case 0xE7: //E7 OUT Ib eAX
+        oper1b = getmem8(segregs[regcs], ip);
+        StepIP(1);
+        portout16 = 1;
+        portout(oper1b, (getreg16(regax)));
+        break;
+      case 0xE8: //E8 CALL Jv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        push(ip);
+        ip = ip + oper1;
+        break;
+      case 0xE9: //E9 JMP Jv
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        ip = ip + oper1;
+        break;
+      case 0xEA: //EA JMP Ap
+        oper1 = getmem16(segregs[regcs], ip); StepIP(2);
+        oper2 = getmem16(segregs[regcs], ip);
+        ip = oper1; segregs[regcs] = oper2;
+        break;
+      case 0xEB: //EB JMP Jb
+        oper1 = signext(getmem8(segregs[regcs], ip)); StepIP(1);
+        ip = ip + oper1;
+        break;
+      case 0xEC: //EC IN regs.byteregs[regal] regdx
+        oper1 = (getreg16(regdx));
+        regs.byteregs[regal] = portin(oper1);
+        break;
+      case 0xED: //ED IN eAX regdx
+        oper1 = (getreg16(regdx));
+        putreg16(regax, portin(oper1));
+        break;
+      case 0xEE: //EE OUT regdx regs.byteregs[regal]
+        oper1 = (getreg16(regdx));
+        portout16 = 0;
+        portout(oper1, regs.byteregs[regal]);
+        break;
+      case 0xEF: //EF OUT regdx eAX
+        oper1 = (getreg16(regdx));
+        portout16 = 1;
+        portout(oper1, (getreg16(regax)));
+        break;
+      case 0xF0: //F0 LOCK
+      case 0xF4: //F4 HLT
+        break;
+      case 0xF5: //F5 CMC
+        if (!cf) cf = 1; else cf = 0;
+        break;
+      case 0xF6: //F6 GRP3a Eb
+        modregrm();
+        oper1b = readrm8(rm);
+        op_grp3_8();
+        if ((reg > 1) && (reg < 4))     writerm8(rm, res8);
+
+        break;
+      case 0xF7: //F7 GRP3b Ev
+        modregrm();
+        oper1 = readrm16(rm);
+        op_grp3_16();
+        if ((reg > 1) && (reg < 4)) writerm16(rm, res16);
+        break;
+      case 0xF8: //F8 CLC
+        cf = 0;
+        break;
+      case 0xF9: //F9 STC
+        cf = 1;
+        break;
+      case 0xFA: //FA CLI
+        ifl = 0;
+        break;
+      case 0xFB: //FB STI
+        ifl = 1;
+        break;
+      case 0xFC: //FC CLD
+        df = 0;
+        break;
+      case 0xFD: //FD STD
+        df = 1;
+        break;
+      case 0xFE: //FE GRP4 Eb
+        modregrm();
+        oper1b = readrm8(rm); oper2b = 1;
+        if (!reg) {
+          tempcf = cf;
+          res8 = oper1b + oper2b;
+          flag_add8(oper1b, oper2b);
+          cf = tempcf; writerm8(rm, res8);
+        } else {
+          tempcf = cf;
+          res8 = oper1b - oper2b;
+          flag_sub8(oper1b, oper2b);
+          cf = tempcf; writerm8(rm, res8);
+        }
+        break;
+      case 0xFF: //FF GRP5 Ev
+        modregrm();
+        oper1 = readrm16(rm);
+        op_grp5();
+        break;
+      default:
+        intcall86(6); //trip invalid opcode exception (this occurs on the 80186+, 8086/8088 CPUs treat them as NOPs
+        if (verbose) {
+          //if (opcode==0xF) sprintf(msg, "Illegal opcode: %02X @ %04X:%04X\n", opcode, savecs, saveip);
+          //else
+          //sprintf(msg, "Illegal opcode: %02X %02X @ %04X:%04X\n", opcode, getmem8(savecs, saveip + 1), savecs, saveip);
+        }
+
+        break;
+    }
+#ifdef PROFILING
+    endmicros = micros();
+    if (instrtime[opcode]) {
+      instrtime[opcode] = (instrtime[opcode] + (endmicros - startmicros)) >> 1;
+    } else {
+      instrtime[opcode] = endmicros - startmicros;
+    }
+#endif
+    //if (!running) return;
+  }
+}
+
+void testmem() {
+
+}
+
diff --git a/MCUME_pico2/pico8086/disk.cpp b/MCUME_pico2/pico8086/disk.cpp
new file mode 100644
index 0000000..577d7c2
--- /dev/null
+++ b/MCUME_pico2/pico8086/disk.cpp
@@ -0,0 +1,256 @@
+#include <stdint.h>
+#include <stdio.h>
+#include "intf.h"
+#include "emuapi.h"
+
+extern uint8_t bootdrive, hdcount;
+extern uint16_t segregs[6];
+extern uint8_t cf; 
+extern _bytewordregs_ regs;
+
+int file;
+
+struct struct_drive {
+  uint32_t filesize;
+  uint16_t cyls;
+  uint16_t sects;
+  uint16_t heads;
+  uint8_t inserted;
+} disk[4];
+uint8_t sectorbuffer[512];
+
+uint8_t insertdisk(uint8_t drivenum) {
+  if (drivenum & 0x80) {
+    drivenum -= 126;
+    disk[drivenum].sects = 63;
+    disk[drivenum].heads = 16;
+    disk[drivenum].cyls = 1023; //up to 512 MB
+    hdcount = 1;
+  } else {
+#ifdef FDD_144M
+    disk[drivenum].cyls = 80;
+    disk[drivenum].sects = 18;
+    disk[drivenum].heads = 2;
+#endif
+#ifdef FDD_122M
+    disk[drivenum].cyls = 80;
+    disk[drivenum].sects = 15;
+    disk[drivenum].heads = 2;
+#endif
+#ifdef FDD_720K
+    disk[drivenum].cyls = 80;
+    disk[drivenum].sects = 9;
+    disk[drivenum].heads = 2;
+#endif
+#ifdef FDD_360K
+    disk[drivenum].cyls = 40;
+    disk[drivenum].sects = 9;
+    disk[drivenum].heads = 2;
+#endif
+#ifdef FDD_320K
+    disk[drivenum].cyls = 40;
+    disk[drivenum].sects = 8;
+    disk[drivenum].heads = 2;
+#endif
+#ifdef FDD_180K
+    disk[drivenum].cyls = 40;
+    disk[drivenum].sects = 9;
+    disk[drivenum].heads = 1;
+#endif
+  }
+  disk[drivenum].inserted = 1;
+  return 0;
+}
+
+void ejectdisk(uint8_t drivenum) {
+  if (drivenum & 0x80) drivenum -= 126;
+  disk[drivenum].inserted = 0;
+}
+
+extern uint16_t ramseg;
+extern "C" {
+extern void emu_SdReadBlock(int block, void * buf);
+}
+uint8_t sectdone;
+void getsect(uint32_t lba, uint8_t *dst) {
+#ifdef USB_DISK
+  uint8_t chksum;
+  uint32_t curmicros;
+retrysectget:
+  Serial.write(0xFF);
+  Serial.write(0x05);
+  outByte(lba & 0xFF); chksum = lba & 0xFF;
+  outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF;
+  outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF;
+  outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF;
+  outByte(chksum);
+  Serial.write(0xFE);
+  Serial.write(0x02);
+  sectdone = 0;
+  curmicros = micros();
+  while (!sectdone) {
+    if (micros() < curmicros) curmicros = micros();
+    if ((micros() - curmicros) >= 200000) goto retrysectget;
+    net_loop();
+  }
+#else
+  if (file) 
+  {  
+    //printf("read block %d\n",lba);  
+    emu_FileSeek(file,lba*512,0);
+    emu_FileRead(dst,1*512,file); 
+  }   
+#endif
+}
+
+void putsect(uint32_t lba, uint8_t *src) {
+#ifdef USB_DISK
+  uint8_t chksum;
+  uint16_t i;
+  uint32_t curmicros;
+retrysectput:
+  Serial.write(0xFF);
+  Serial.write(0x06);
+  outByte(lba & 0xFF); chksum = lba & 0xFF;
+  outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF;
+  outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF;
+  outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF;
+  for (i=0; i<512; i++) {
+    outByte(src[i]);
+    chksum += src[i];
+  }
+  outByte(chksum);
+  Serial.write(0xFE);
+  Serial.write(0x02);
+  sectdone = 0;
+  curmicros = micros();
+  while (!sectdone) {
+    if (micros() < curmicros) curmicros = micros();
+    if ((micros() - curmicros) >= 200000) goto retrysectput;
+    net_loop();
+  }
+#else
+  //card.writeBlock(lba, src);
+#endif
+}
+void readdisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) {
+  uint32_t memdest, goodsects, dummy, lba;
+  if ((sect == 0) || !disk[drivenum].inserted) return;
+#ifdef MEGA
+  SPI.setClockDivider(SPI_CLOCK_SDCARD);
+#endif
+  lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1;
+  memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
+  for (goodsects = 0; goodsects < sectcount; goodsects++) {
+    getsect(lba, sectorbuffer);
+    memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
+    for (dummy = 0; dummy < 512; dummy++) {
+      write86(memdest++, sectorbuffer[dummy]);
+      //Serial.write(sectorbuffer[dummy]);
+    }
+    dstoff += 512;
+    lba++;
+  }
+  cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount;
+#ifdef MEGA
+  SPI.setClockDivider(SPI_CLOCK_SPIRAM);
+#endif
+}
+
+void writedisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) {
+  uint32_t memdest, goodsects, dummy, lba;
+  if ((sect == 0) || !disk[drivenum].inserted) return;
+#ifdef MEGA
+  SPI.setClockDivider(SPI_CLOCK_SDCARD);
+#endif
+  lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1;
+  for (goodsects = 0; goodsects < sectcount; goodsects++) {
+    memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff;
+    for (dummy = 0; dummy < 512; dummy++) {
+      sectorbuffer[dummy] = read86(memdest++);
+    }
+    //card.erase(lba, lba);
+    putsect(lba, sectorbuffer);
+    dstoff += 512;
+    lba++;
+  }
+  cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount;
+#ifdef MEGA
+  SPI.setClockDivider(SPI_CLOCK_SPIRAM);
+#endif
+}
+
+void diskhandler() {
+  static uint8_t lastdiskah[4], lastdiskcf[4];
+  uint8_t drivenum;
+  drivenum = regs.byteregs[regdl];
+  if (drivenum & 0x80) drivenum -= 126;
+  switch (regs.byteregs[regah]) {
+    case 0: //reset disk system
+      regs.byteregs[regah] = 0; cf = 0; //useless function in an emulator. say success and return.
+      break;
+    case 1: //return last status
+      regs.byteregs[regah] = lastdiskah[drivenum];
+      cf = lastdiskcf[drivenum];
+      return;
+    case 2: //read sector(s) into memory
+      if (disk[drivenum].inserted) {
+        readdisk(drivenum, segregs[reges], getreg16(regbx), (uint16_t)regs.byteregs[regch] + ((uint16_t)regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]);
+        cf = 0; regs.byteregs[regah] = 0;
+      } else {
+        cf = 1;
+        regs.byteregs[regah] = 1;
+      }
+      break;
+    case 3: //write sector(s) from memory
+      if (disk[drivenum].inserted) {
+        writedisk(drivenum, segregs[reges], getreg16(regbx), regs.byteregs[regch] + (regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]);
+        cf = 0; regs.byteregs[regah] = 0;
+      } else {
+        cf = 1;
+        regs.byteregs[regah] = 1;
+      }
+      break;
+    case 4:
+    case 5: //format track
+      cf = 0; regs.byteregs[regah] = 0;
+      break;
+    case 8: //get drive parameters
+      if (disk[drivenum].inserted) {
+        cf = 0; regs.byteregs[regah] = 0;
+        regs.byteregs[regch] = disk[drivenum].cyls - 1;
+        regs.byteregs[regcl] = disk[drivenum].sects & 63;
+        regs.byteregs[regcl] = regs.byteregs[regcl] + (disk[drivenum].cyls / 256) * 64;
+        regs.byteregs[regdh] = disk[drivenum].heads - 1;
+        //segregs[reges] = 0; regs.wordregs[regdi] = 0x7C0B; //floppy parameter table
+        if (drivenum < 2) {
+          regs.byteregs[regbl] = 4; //else regs.byteregs[regbl] = 0;
+          regs.byteregs[regdl] = 2;
+        } else regs.byteregs[regdl] = hdcount;
+      } else {
+        cf = 1; regs.byteregs[regah] = 0xAA;
+      }
+      break;
+    default:
+      cf = 1;
+  }
+  lastdiskah[drivenum] = regs.byteregs[regah];
+  lastdiskcf[drivenum] = cf;
+  if (regs.byteregs[regdl] & 0x80) write86(0x474, regs.byteregs[regah]);
+}
+
+void initDisk(char * filename) {
+  int len=emu_FileSize(filename);
+  file = emu_FileOpen(filename,"r+b");  
+  if (len) {
+    bootdrive = 0x80;
+    insertdisk(0x80);
+    hdcount = 1;
+  }
+  else {
+    bootdrive = 0xFF;
+    emu_FileClose(file);
+    file = 0;
+  }
+}
+
diff --git a/MCUME_pico2/pico8086/emu.cpp b/MCUME_pico2/pico8086/emu.cpp
new file mode 100644
index 0000000..4e0ee9c
--- /dev/null
+++ b/MCUME_pico2/pico8086/emu.cpp
@@ -0,0 +1,692 @@
+#include <string.h>
+#include "intf.h"
+#include "emuapi.h"
+#include "iopins.h"
+
+#include "emu.h"
+#include "ps2.h"
+
+static uint8_t LOMEM[NATIVE_RAM];
+
+
+uint8_t * LORAM;
+
+extern void timer_isr(void);
+
+#include "psram_t.h"
+
+PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO);
+
+extern "C" unsigned char read_ram(int address) {
+  return (psram.psread(address));
+}
+
+extern "C" void  write_ram(int address, unsigned char val)  {
+  psram.pswrite(address,val); 
+}
+
+#define PALMULT8(x)  ((x)<<5)
+#define RGBVAL16(r,g,b)  ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) )
+
+struct i8253_s {
+  uint16_t chandata[3];
+  uint8_t accessmode[3];
+  uint8_t bytetoggle[3];
+  uint32_t effectivedata[3];
+  float chanfreq[3];
+  uint8_t active[3];
+  uint16_t counter[3];
+};
+
+extern struct i8253_s i8253;
+
+void doirq(uint8_t irqnum);
+void write86(uint32_t addr32, uint8_t value);
+uint8_t read86(uint32_t addr32);
+
+uint8_t curkey = 0;
+
+
+
+uint8_t VRAM[16384];
+
+
+uint32_t updateaddrs[64];
+uint8_t updatepos = 0;
+
+void VRAM_write(uint32_t addr32, uint8_t value) {
+
+  if (addr32 < 16384) {
+    VRAM[addr32] = value;    
+  }
+}
+
+uint8_t VRAM_read(uint32_t addr32) {
+
+  if (addr32 < 16384) return VRAM[addr32];
+  return 0;
+}
+
+uint8_t ansicolor[16] = { 0, 4, 2, 6, 1, 5, 3, 7, 0, 4, 2, 6, 1, 5, 3, 7 };
+uint16_t palettecga[16], palettevga[256];
+
+
+void installPalette(void) {
+  palettecga[0] = RGBVAL16(0, 0, 0);
+  palettecga[1] = RGBVAL16(0, 0, 0xAA);
+  palettecga[2] = RGBVAL16(0, 0xAA, 0);
+  palettecga[3] = RGBVAL16(0, 0xAA, 0xAA);
+  palettecga[4] = RGBVAL16(0xAA, 0, 0);
+  palettecga[5] = RGBVAL16(0xAA, 0, 0xAA);
+  palettecga[6] = RGBVAL16(0xAA, 0x55, 0);
+  palettecga[7] = RGBVAL16(0xAA, 0xAA, 0xAA);
+  palettecga[8] = RGBVAL16(0x55, 0x55, 0x55);
+  palettecga[9] = RGBVAL16(0x55, 0x55, 0xFF);
+  palettecga[10] = RGBVAL16(0x55, 0xFF, 0x55);
+  palettecga[11] = RGBVAL16(0x55, 0xFF, 0xFF);
+  palettecga[12] = RGBVAL16(0xFF, 0x55, 0x55);
+  palettecga[13] = RGBVAL16(0xFF, 0x55, 0xFF);
+  palettecga[14] = RGBVAL16(0xFF, 0xFF, 0x55);
+  palettecga[15] = RGBVAL16(0xFF, 0xFF, 0xFF);
+  palettevga[0] = RGBVAL16(0, 0, 0);
+  palettevga[1] = RGBVAL16(0, 0, 169);
+  palettevga[2] = RGBVAL16(0, 169, 0);
+  palettevga[3] = RGBVAL16(0, 169, 169);
+  palettevga[4] = RGBVAL16(169, 0, 0);
+  palettevga[5] = RGBVAL16(169, 0, 169);
+  palettevga[6] = RGBVAL16(169, 169, 0);
+  palettevga[7] = RGBVAL16(169, 169, 169);
+  palettevga[8] = RGBVAL16(0, 0, 84);
+  palettevga[9] = RGBVAL16(0, 0, 255);
+  palettevga[10] = RGBVAL16(0, 169, 84);
+  palettevga[11] = RGBVAL16(0, 169, 255);
+  palettevga[12] = RGBVAL16(169, 0, 84);
+  palettevga[13] = RGBVAL16(169, 0, 255);
+  palettevga[14] = RGBVAL16(169, 169, 84);
+  palettevga[15] = RGBVAL16(169, 169, 255);
+  palettevga[16] = RGBVAL16(0, 84, 0);
+  palettevga[17] = RGBVAL16(0, 84, 169);
+  palettevga[18] = RGBVAL16(0, 255, 0);
+  palettevga[19] = RGBVAL16(0, 255, 169);
+  palettevga[20] = RGBVAL16(169, 84, 0);
+  palettevga[21] = RGBVAL16(169, 84, 169);
+  palettevga[22] = RGBVAL16(169, 255, 0);
+  palettevga[23] = RGBVAL16(169, 255, 169);
+  palettevga[24] = RGBVAL16(0, 84, 84);
+  palettevga[25] = RGBVAL16(0, 84, 255);
+  palettevga[26] = RGBVAL16(0, 255, 84);
+  palettevga[27] = RGBVAL16(0, 255, 255);
+  palettevga[28] = RGBVAL16(169, 84, 84);
+  palettevga[29] = RGBVAL16(169, 84, 255);
+  palettevga[30] = RGBVAL16(169, 255, 84);
+  palettevga[31] = RGBVAL16(169, 255, 255);
+  palettevga[32] = RGBVAL16(84, 0, 0);
+  palettevga[33] = RGBVAL16(84, 0, 169);
+  palettevga[34] = RGBVAL16(84, 169, 0);
+  palettevga[35] = RGBVAL16(84, 169, 169);
+  palettevga[36] = RGBVAL16(255, 0, 0);
+  palettevga[37] = RGBVAL16(255, 0, 169);
+  palettevga[38] = RGBVAL16(255, 169, 0);
+  palettevga[39] = RGBVAL16(255, 169, 169);
+  palettevga[40] = RGBVAL16(84, 0, 84);
+  palettevga[41] = RGBVAL16(84, 0, 255);
+  palettevga[42] = RGBVAL16(84, 169, 84);
+  palettevga[43] = RGBVAL16(84, 169, 255);
+  palettevga[44] = RGBVAL16(255, 0, 84);
+  palettevga[45] = RGBVAL16(255, 0, 255);
+  palettevga[46] = RGBVAL16(255, 169, 84);
+  palettevga[47] = RGBVAL16(255, 169, 255);
+  palettevga[48] = RGBVAL16(84, 84, 0);
+  palettevga[49] = RGBVAL16(84, 84, 169);
+  palettevga[50] = RGBVAL16(84, 255, 0);
+  palettevga[51] = RGBVAL16(84, 255, 169);
+  palettevga[52] = RGBVAL16(255, 84, 0);
+  palettevga[53] = RGBVAL16(255, 84, 169);
+  palettevga[54] = RGBVAL16(255, 255, 0);
+  palettevga[55] = RGBVAL16(255, 255, 169);
+  palettevga[56] = RGBVAL16(84, 84, 84);
+  palettevga[57] = RGBVAL16(84, 84, 255);
+  palettevga[58] = RGBVAL16(84, 255, 84);
+  palettevga[59] = RGBVAL16(84, 255, 255);
+  palettevga[60] = RGBVAL16(255, 84, 84);
+  palettevga[61] = RGBVAL16(255, 84, 255);
+  palettevga[62] = RGBVAL16(255, 255, 84);
+  palettevga[63] = RGBVAL16(255, 255, 255);
+  palettevga[64] = RGBVAL16(255, 125, 125);
+  palettevga[65] = RGBVAL16(255, 157, 125);
+  palettevga[66] = RGBVAL16(255, 190, 125);
+  palettevga[67] = RGBVAL16(255, 222, 125);
+  palettevga[68] = RGBVAL16(255, 255, 125);
+  palettevga[69] = RGBVAL16(222, 255, 125);
+  palettevga[70] = RGBVAL16(190, 255, 125);
+  palettevga[71] = RGBVAL16(157, 255, 125);
+  palettevga[72] = RGBVAL16(125, 255, 125);
+  palettevga[73] = RGBVAL16(125, 255, 157);
+  palettevga[74] = RGBVAL16(125, 255, 190);
+  palettevga[75] = RGBVAL16(125, 255, 222);
+  palettevga[76] = RGBVAL16(125, 255, 255);
+  palettevga[77] = RGBVAL16(125, 222, 255);
+  palettevga[78] = RGBVAL16(125, 190, 255);
+  palettevga[79] = RGBVAL16(125, 157, 255);
+  palettevga[80] = RGBVAL16(182, 182, 255);
+  palettevga[81] = RGBVAL16(198, 182, 255);
+  palettevga[82] = RGBVAL16(218, 182, 255);
+  palettevga[83] = RGBVAL16(234, 182, 255);
+  palettevga[84] = RGBVAL16(255, 182, 255);
+  palettevga[85] = RGBVAL16(255, 182, 234);
+  palettevga[86] = RGBVAL16(255, 182, 218);
+  palettevga[87] = RGBVAL16(255, 182, 198);
+  palettevga[88] = RGBVAL16(255, 182, 182);
+  palettevga[89] = RGBVAL16(255, 198, 182);
+  palettevga[90] = RGBVAL16(255, 218, 182);
+  palettevga[91] = RGBVAL16(255, 234, 182);
+  palettevga[92] = RGBVAL16(255, 255, 182);
+  palettevga[93] = RGBVAL16(234, 255, 182);
+  palettevga[94] = RGBVAL16(218, 255, 182);
+  palettevga[95] = RGBVAL16(198, 255, 182);
+  palettevga[96] = RGBVAL16(182, 255, 182);
+  palettevga[97] = RGBVAL16(182, 255, 198);
+  palettevga[98] = RGBVAL16(182, 255, 218);
+  palettevga[99] = RGBVAL16(182, 255, 234);
+  palettevga[100] = RGBVAL16(182, 255, 255);
+  palettevga[101] = RGBVAL16(182, 234, 255);
+  palettevga[102] = RGBVAL16(182, 218, 255);
+  palettevga[103] = RGBVAL16(182, 198, 255);
+  palettevga[104] = RGBVAL16(0, 0, 113);
+  palettevga[105] = RGBVAL16(28, 0, 113);
+  palettevga[106] = RGBVAL16(56, 0, 113);
+  palettevga[107] = RGBVAL16(84, 0, 113);
+  palettevga[108] = RGBVAL16(113, 0, 113);
+  palettevga[109] = RGBVAL16(113, 0, 84);
+  palettevga[110] = RGBVAL16(113, 0, 56);
+  palettevga[111] = RGBVAL16(113, 0, 28);
+  palettevga[112] = RGBVAL16(113, 0, 0);
+  palettevga[113] = RGBVAL16(113, 28, 0);
+  palettevga[114] = RGBVAL16(113, 56, 0);
+  palettevga[115] = RGBVAL16(113, 84, 0);
+  palettevga[116] = RGBVAL16(113, 113, 0);
+  palettevga[117] = RGBVAL16(84, 113, 0);
+  palettevga[118] = RGBVAL16(56, 113, 0);
+  palettevga[119] = RGBVAL16(28, 113, 0);
+  palettevga[120] = RGBVAL16(0, 113, 0);
+  palettevga[121] = RGBVAL16(0, 113, 28);
+  palettevga[122] = RGBVAL16(0, 113, 56);
+  palettevga[123] = RGBVAL16(0, 113, 84);
+  palettevga[124] = RGBVAL16(0, 113, 113);
+  palettevga[125] = RGBVAL16(0, 84, 113);
+  palettevga[126] = RGBVAL16(0, 56, 113);
+  palettevga[127] = RGBVAL16(0, 28, 113);
+  palettevga[128] = RGBVAL16(56, 56, 113);
+  palettevga[129] = RGBVAL16(68, 56, 113);
+  palettevga[130] = RGBVAL16(84, 56, 113);
+  palettevga[131] = RGBVAL16(97, 56, 113);
+  palettevga[132] = RGBVAL16(113, 56, 113);
+  palettevga[133] = RGBVAL16(113, 56, 97);
+  palettevga[134] = RGBVAL16(113, 56, 84);
+  palettevga[135] = RGBVAL16(113, 56, 68);
+  palettevga[136] = RGBVAL16(113, 56, 56);
+  palettevga[137] = RGBVAL16(113, 68, 56);
+  palettevga[138] = RGBVAL16(113, 84, 56);
+  palettevga[139] = RGBVAL16(113, 97, 56);
+  palettevga[140] = RGBVAL16(113, 113, 56);
+  palettevga[141] = RGBVAL16(97, 113, 56);
+  palettevga[142] = RGBVAL16(84, 113, 56);
+  palettevga[143] = RGBVAL16(68, 113, 56);
+  palettevga[144] = RGBVAL16(56, 113, 56);
+  palettevga[145] = RGBVAL16(56, 113, 68);
+  palettevga[146] = RGBVAL16(56, 113, 84);
+  palettevga[147] = RGBVAL16(56, 113, 97);
+  palettevga[148] = RGBVAL16(56, 113, 113);
+  palettevga[149] = RGBVAL16(56, 97, 113);
+  palettevga[150] = RGBVAL16(56, 84, 113);
+  palettevga[151] = RGBVAL16(56, 68, 113);
+  palettevga[152] = RGBVAL16(80, 80, 113);
+  palettevga[153] = RGBVAL16(89, 80, 113);
+  palettevga[154] = RGBVAL16(97, 80, 113);
+  palettevga[155] = RGBVAL16(105, 80, 113);
+  palettevga[156] = RGBVAL16(113, 80, 113);
+  palettevga[157] = RGBVAL16(113, 80, 105);
+  palettevga[158] = RGBVAL16(113, 80, 97);
+  palettevga[159] = RGBVAL16(113, 80, 89);
+  palettevga[160] = RGBVAL16(113, 80, 80);
+  palettevga[161] = RGBVAL16(113, 89, 80);
+  palettevga[162] = RGBVAL16(113, 97, 80);
+  palettevga[163] = RGBVAL16(113, 105, 80);
+  palettevga[164] = RGBVAL16(113, 113, 80);
+  palettevga[165] = RGBVAL16(105, 113, 80);
+  palettevga[166] = RGBVAL16(97, 113, 80);
+  palettevga[167] = RGBVAL16(89, 113, 80);
+  palettevga[168] = RGBVAL16(80, 113, 80);
+  palettevga[169] = RGBVAL16(80, 113, 89);
+  palettevga[170] = RGBVAL16(80, 113, 97);
+  palettevga[171] = RGBVAL16(80, 113, 105);
+  palettevga[172] = RGBVAL16(80, 113, 113);
+  palettevga[173] = RGBVAL16(80, 105, 113);
+  palettevga[174] = RGBVAL16(80, 97, 113);
+  palettevga[175] = RGBVAL16(80, 89, 113);
+  palettevga[176] = RGBVAL16(0, 0, 64);
+  palettevga[177] = RGBVAL16(16, 0, 64);
+  palettevga[178] = RGBVAL16(32, 0, 64);
+  palettevga[179] = RGBVAL16(48, 0, 64);
+  palettevga[180] = RGBVAL16(64, 0, 64);
+  palettevga[181] = RGBVAL16(64, 0, 48);
+  palettevga[182] = RGBVAL16(64, 0, 32);
+  palettevga[183] = RGBVAL16(64, 0, 16);
+  palettevga[184] = RGBVAL16(64, 0, 0);
+  palettevga[185] = RGBVAL16(64, 16, 0);
+  palettevga[186] = RGBVAL16(64, 32, 0);
+  palettevga[187] = RGBVAL16(64, 48, 0);
+  palettevga[188] = RGBVAL16(64, 64, 0);
+  palettevga[189] = RGBVAL16(48, 64, 0);
+  palettevga[190] = RGBVAL16(32, 64, 0);
+  palettevga[191] = RGBVAL16(16, 64, 0);
+  palettevga[192] = RGBVAL16(0, 64, 0);
+  palettevga[193] = RGBVAL16(0, 64, 16);
+  palettevga[194] = RGBVAL16(0, 64, 32);
+  palettevga[195] = RGBVAL16(0, 64, 48);
+  palettevga[196] = RGBVAL16(0, 64, 64);
+  palettevga[197] = RGBVAL16(0, 48, 64);
+  palettevga[198] = RGBVAL16(0, 32, 64);
+  palettevga[199] = RGBVAL16(0, 16, 64);
+  palettevga[200] = RGBVAL16(32, 32, 64);
+  palettevga[201] = RGBVAL16(40, 32, 64);
+  palettevga[202] = RGBVAL16(48, 32, 64);
+  palettevga[203] = RGBVAL16(56, 32, 64);
+  palettevga[204] = RGBVAL16(64, 32, 64);
+  palettevga[205] = RGBVAL16(64, 32, 56);
+  palettevga[206] = RGBVAL16(64, 32, 48);
+  palettevga[207] = RGBVAL16(64, 32, 40);
+  palettevga[208] = RGBVAL16(64, 32, 32);
+  palettevga[209] = RGBVAL16(64, 40, 32);
+  palettevga[210] = RGBVAL16(64, 48, 32);
+  palettevga[211] = RGBVAL16(64, 56, 32);
+  palettevga[212] = RGBVAL16(64, 64, 32);
+  palettevga[213] = RGBVAL16(56, 64, 32);
+  palettevga[214] = RGBVAL16(48, 64, 32);
+  palettevga[215] = RGBVAL16(40, 64, 32);
+  palettevga[216] = RGBVAL16(32, 64, 32);
+  palettevga[217] = RGBVAL16(32, 64, 40);
+  palettevga[218] = RGBVAL16(32, 64, 48);
+  palettevga[219] = RGBVAL16(32, 64, 56);
+  palettevga[220] = RGBVAL16(32, 64, 64);
+  palettevga[221] = RGBVAL16(32, 56, 64);
+  palettevga[222] = RGBVAL16(32, 48, 64);
+  palettevga[223] = RGBVAL16(32, 40, 64);
+  palettevga[224] = RGBVAL16(44, 44, 64);
+  palettevga[225] = RGBVAL16(48, 44, 64);
+  palettevga[226] = RGBVAL16(52, 44, 64);
+  palettevga[227] = RGBVAL16(60, 44, 64);
+  palettevga[228] = RGBVAL16(64, 44, 64);
+  palettevga[229] = RGBVAL16(64, 44, 60);
+  palettevga[230] = RGBVAL16(64, 44, 52);
+  palettevga[231] = RGBVAL16(64, 44, 48);
+  palettevga[232] = RGBVAL16(64, 44, 44);
+  palettevga[233] = RGBVAL16(64, 48, 44);
+  palettevga[234] = RGBVAL16(64, 52, 44);
+  palettevga[235] = RGBVAL16(64, 60, 44);
+  palettevga[236] = RGBVAL16(64, 64, 44);
+  palettevga[237] = RGBVAL16(60, 64, 44);
+  palettevga[238] = RGBVAL16(52, 64, 44);
+  palettevga[239] = RGBVAL16(48, 64, 44);
+  palettevga[240] = RGBVAL16(44, 64, 44);
+  palettevga[241] = RGBVAL16(44, 64, 48);
+  palettevga[242] = RGBVAL16(44, 64, 52);
+  palettevga[243] = RGBVAL16(44, 64, 60);
+  palettevga[244] = RGBVAL16(44, 64, 64);
+  palettevga[245] = RGBVAL16(44, 60, 64);
+  palettevga[246] = RGBVAL16(44, 52, 64);
+  palettevga[247] = RGBVAL16(44, 48, 64);
+  palettevga[248] = RGBVAL16(0, 0, 0);
+  palettevga[249] = RGBVAL16(0, 0, 0);
+  palettevga[250] = RGBVAL16(0, 0, 0);
+  palettevga[251] = RGBVAL16(0, 0, 0);
+  palettevga[252] = RGBVAL16(0, 0, 0);
+  palettevga[253] = RGBVAL16(0, 0, 0);
+  palettevga[254] = RGBVAL16(0, 0, 0);
+  palettevga[255] = RGBVAL16(0, 0, 0);
+}
+
+extern uint8_t vidmode, portram[0x400];
+
+#define XRES_MAX 640
+#define XRES_HI  640
+#define XRES_LO  320
+#define YRES     200
+
+#include "font.h"
+
+
+static unsigned short line[XRES_MAX];
+
+void drawscreentext80(void) {
+  uint16_t row, col, y, x, xpos;
+  uint16_t fontdata;
+
+  for (y=0; y<(25*8); y++) 
+  {
+    row = y>>3;
+    uint8_t * vrampt=&VRAM[160*row];
+    xpos = 0;
+    for (col=0; col<80; col++) 
+    {
+      uint8_t bold, attrib, cc, bg, fg;
+      cc = *vrampt++;
+      attrib = *vrampt++;
+      bg = (attrib >> 4) & 7;
+      fg = attrib & 0x0F;
+      //if (y == 0) {printf("0x%02X",cc);}
+      fontdata = ROM_READ(font, ((uint32_t)cc << 3) + (y&0x7));
+      for (x=0; x<8; x++) 
+      //for (x=0; x<4; x++) 
+      {
+        if (fontdata & 1) {
+          line[xpos++] = palettecga[fg];
+        } else {
+          line[xpos++] = palettecga[bg];
+        }
+        fontdata >>= 1;
+        //fontdata >>= 2;
+      }
+    } 
+    emu_DrawLine16(&line[0], XRES_HI, YRES, y);       
+  }
+}
+
+void drawscreenlorescga(void) {
+  uint16_t y, x, xpos;
+  uint8_t intensity, usepal;
+  uint16_t color;
+  usepal = (portram[0x3D9]>>5) & 1;
+  intensity = ( (portram[0x3D9]>>4) & 1) << 3;
+
+  for (y=0; y<(25*8); y++) 
+  {
+    xpos = 0;
+    for (x=0; x<XRES_LO; x++) 
+    {
+      int ychar = y;// >> 1;
+      int xchar = x;// >> 1;
+      uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 2))];
+      switch (xchar & 3) {
+        case 3: color = curchar & 3; break;
+        case 2: color = (curchar >> 2) & 3; break;
+        case 1: color = (curchar >> 4) & 3; break;
+        case 0: color = (curchar >> 6) & 3; break;
+      }
+      color = (color << 1) + usepal + intensity;
+      if (color == (usepal + intensity)) color = 0; 
+      line[xpos++] = palettecga[color];     
+    } 
+    emu_DrawLine16(&line[0], XRES_LO, YRES, y);       
+  }
+}
+
+
+void drawscreenhirescga(void) {
+  uint16_t y, x, xpos;
+  uint16_t color;
+  for (y=0; y<(25*8); y++) 
+  {
+    xpos = 0;
+    for (x=0; x<XRES_HI; x++) 
+    {
+      int ychar = y >> 1;
+      int xchar = x;
+      uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 3))];
+      color = ((curchar >> (7-(x&7))) & 1) ? 15 : 0;
+      line[xpos++] = palettecga[color];     
+    } 
+    emu_DrawLine16(&line[0], XRES_HI, YRES, y);       
+  }
+}
+
+
+void updatescreen() {
+  switch (vidmode & 0x7F) {
+    case 0:
+    case 1:
+      //drawtext40(origaddr, value);
+      break;
+    case 2:
+    case 3:
+    //case 7:
+      drawscreentext80();
+      break;
+    case 4:
+      drawscreenlorescga();
+      break;
+    case 5:
+      drawscreenlorescga(); //change to BW function later
+      break;
+    case 6:
+      drawscreenhirescga();
+      break;
+  }
+//printf("%d\n",vidmode & 0x7F);      
+}
+
+static uint8_t nbkeys=0;
+static uint8_t kcnt=0;
+static int toggle=1;
+
+static char * seq;
+static char * seq1="PRINCE.BAT\r";
+static char * seq2="CAT.EXE\r";
+static char * seq3="DIR\r";
+
+static int mouse_x = 160;
+static int mouse_y = 100;
+static int prev_key = 0; 
+static int prev_j = 0; 
+static int prev_mouseb = 0;
+static bool isMouse = true;
+static int joynum = 1;
+static int hk = 0;
+static int iusbhk; // USB keyboard key
+static int prev_hk = 0;
+static int k = 0;
+
+static void keyevent(int keysym, int isdown)
+{
+  uint8_t scancode = translatescancode(keysym);
+  if (scancode != 0xFF) {
+    portram[0x60] = scancode;
+    if (!isdown) portram[0x60] |= 0x80;
+    portram[0x64] |= 2;
+    doirq(1);
+  }
+}
+
+static int cnt=5;
+
+extern void apc_Input(int bClick) {
+  timer_isr();  
+
+  if (cnt-- < 0) {
+    cnt=5;
+
+    hk = emu_ReadI2CKeyboard();
+    k = emu_ReadKeys(); 
+
+    if (nbkeys == 0) {
+      if (bClick & MASK_JOY2_BTN) {
+          nbkeys = strlen(seq1);
+          seq=seq1;   
+          kcnt=0;
+      }  
+      if (bClick & MASK_KEY_USER1) {
+          nbkeys = strlen(seq2);
+          seq=seq2;  
+          kcnt=0;
+      }  
+    }
+    else {
+      char k = seq[kcnt];
+      if (k == 13) keyevent(0xFF0D,toggle);
+      else keyevent(k,toggle);
+      //setKey(ascii2scan[k],toggle);
+      if (!toggle) {
+          kcnt++;
+          nbkeys--;
+          toggle = true;
+      }
+      else {
+          toggle = false; 
+      }
+    }
+  }
+}
+
+static void do_events(void) 
+{
+  if (iusbhk) hk = iusbhk;  
+  if (hk != prev_hk) {
+    prev_hk == hk;
+    if ( (hk != 0) && (hk != prev_key) ) {
+      prev_key = hk;
+      keyevent ( hk, 0 );
+      if (hk == 68) {
+        if (isMouse) isMouse = false;
+        else isMouse = true;
+      }
+    }     
+  }
+  if ( (hk == 0) && (prev_key) ) {
+      keyevent ( prev_key, 1 );
+      prev_key = 0;
+  }           
+
+
+  if (!isMouse)
+  {
+    int j = 0;     
+    if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+      j |= 0x08;
+    }
+    if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+      j |= 0x04;
+    }
+    if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+      j |= 0x01;
+    }
+    if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+      j |= 0x02;
+    }  
+    if ( k & MASK_JOY2_BTN) {
+      j |= 0x80;
+    }
+    if (j != prev_j) {
+      //IkbdJoystickChange(joynum,j);
+      prev_j = j;
+    }
+  }
+  else {
+    if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+      if ( mouse_x < XRES_HI ) {
+        mouse_x += 1;
+      } 
+    }
+    else if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+      if ( mouse_x > 1 ) {
+        mouse_x -= 1;       
+      }
+    }
+    else if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+      if ( mouse_y > 1 ) {
+        mouse_y -= 1;     
+      }
+    }
+    else if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+      if ( mouse_y < YRES ) {
+        mouse_y += 1;      
+      }
+    }  
+    
+    int mouseb=0;
+    if ( ( k & MASK_JOY2_BTN) ){
+      mouseb=1;
+    }
+    if ( (mouseb != prev_mouseb) ){
+      prev_mouseb = mouseb;  
+    }    
+  }
+}     
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  int keyCode = -1;
+  if ((key >=0xc0) && (key <=0xdf)) {
+    keyCode = ((key-0xc0) & 0x1f) + 0x7f;
+  }
+  else {
+    keyCode = key & 0x7f;
+  }
+
+  //emu_printi(keyCode);
+
+  switch (keyCode) {
+   case  0x7F:  keyCode = 0xFF08; break; //backspace
+   case  0x09:  keyCode = 0xFF09; break; //tab
+   case  0x0A:  keyCode = 0xFF0D; break; //enter
+   case  0X1B:  keyCode = 0xFF1B; break; //escape
+   case  0x90:  keyCode = 0xFF63; break; //KP 0 / insert
+   case  0x93:  keyCode = 0xFFFF; break; //KP . / delete
+   case  0x92:  keyCode = 0xFF55; break; //pgup
+   case  0x95:  keyCode = 0xFF56; break; //pgdn
+   case  0x91:  keyCode = 0xFF50; break; //home
+   case  0x94:  keyCode = 0xFF57; break; //end
+   case  0x81:  keyCode = 0xFFBE; break; //F1
+   case  0x82:  keyCode = 0xFFBF; break; //F2
+   case  0x83:  keyCode = 0xFFC0; break; //F3
+   case  0x84:  keyCode = 0xFFC1; break; //F4
+   case  0x85:  keyCode = 0xFFC2; break; //F5
+   case  0x86:  keyCode = 0xFFC3; break; //F6
+   case  0x87:  keyCode = 0xFFC4; break; //F7
+   case  0x88:  keyCode = 0xFFC5; break; //F8
+   case  0x89:  keyCode = 0xFFC6; break; //F9
+   case  0x8A:  keyCode = 0xFFC7; break; //F10
+   case  0x8B:  keyCode = 0xFFC8; break; //F11
+   case  0x8C:  keyCode = 0xFFC9; break; //F12
+   case  0x97:  keyCode = 0xFF51; break; //left
+   case  0x99:  keyCode = 0xFF52; break; //up
+   case  0x96:  keyCode = 0xFF53; break; //right
+   case  0x98:  keyCode = 0xFF54; break; //down    
+  }
+
+  if (keyCode != -1) {
+    iusbhk = keyCode;
+  }  
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;  
+}
+
+void apc_Step(void)
+{ 
+  exec86(8000);
+  updatescreen();
+  do_events();
+  emu_DrawVsync();
+}
+
+ 
+
+void apc_Init(void)
+{
+  psram.begin();
+  //RAM = (uint8_t*) malloc(RAM_SIZE);
+  //if (!RAM) emu_printf("RAM malloc failed"); 
+  LORAM = &LOMEM[0];
+
+  installPalette();
+  init8253();
+  reset86();
+  init8259();  
+}
+
+void apc_Start(char * filename)
+{
+  emu_printf("init started");
+  initDisk(filename);
+  emu_printf("init done");
+}
diff --git a/MCUME_pico2/pico8086/emu.h b/MCUME_pico2/pico8086/emu.h
new file mode 100644
index 0000000..2b13c4a
--- /dev/null
+++ b/MCUME_pico2/pico8086/emu.h
@@ -0,0 +1,5 @@
+extern void apc_Init(void);
+extern void apc_Step(void);
+extern void apc_Start(char * filename);
+extern void apc_Input(int click);
+
diff --git a/MCUME_pico2/pico8086/emucfg.h b/MCUME_pico2/pico8086/emucfg.h
new file mode 100644
index 0000000..3e544b6
--- /dev/null
+++ b/MCUME_pico2/pico8086/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >                                      >
+#define TITLE "    8086 PC Emulator"
+#define ROMSDIR "pc"
+
+#define emu_Init(ROM) {apc_Init(); apc_Start(ROM);}
+#define emu_Step(x) {apc_Step();}
+#define emu_Input(x) {apc_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico8086/font.h b/MCUME_pico2/pico8086/font.h
new file mode 100644
index 0000000..b953dfd
--- /dev/null
+++ b/MCUME_pico2/pico8086/font.h
@@ -0,0 +1,259 @@
+  const uint8_t font[2048] = {
+  0,0,0,0,0,0,0,
+  0,126,129,165,129,189,153,129,
+  126,126,255,219,255,195,231,255,
+  126,54,127,127,127,62,28,8,
+  0,8,28,62,127,62,28,8,
+  0,28,62,28,127,127,62,28,
+  62,8,8,28,62,127,62,28,
+  62,0,0,0,0,0,0,0,
+  0,255,255,231,195,195,231,255,
+  255,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,254,198,254,198,198,230,103,
+  3,153,90,60,231,231,60,90,
+  153,1,7,31,127,31,7,1,
+  0,64,112,124,127,124,112,64,
+  0,24,60,126,24,24,126,60,
+  24,102,102,102,102,102,0,102,
+  0,254,219,219,222,216,216,216,
+  0,124,198,28,54,54,28,51,
+  30,0,0,0,0,126,126,126,
+  0,24,60,126,24,126,60,24,
+  255,24,60,126,24,24,24,24,
+  0,24,24,24,24,126,60,24,
+  0,0,24,48,127,48,24,0,
+  0,0,12,6,127,6,12,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,
+  0,12,30,30,12,12,0,12,
+  0,54,54,54,0,0,0,0,
+  0,54,54,127,54,127,54,54,
+  0,12,62,3,30,48,31,12,
+  0,0,99,51,24,12,102,99,
+  0,28,54,28,110,59,51,110,
+  0,6,6,3,0,0,0,0,
+  0,24,12,6,6,6,12,24,
+  0,6,12,24,24,24,12,6,
+  0,0,102,60,255,60,102,0,
+  0,0,12,12,63,12,12,0,
+  0,0,0,0,0,0,12,12,
+  6,0,0,0,63,0,0,0,
+  0,0,0,0,0,0,12,12,
+  0,96,48,24,12,6,3,1,
+  0,62,99,115,123,111,103,62,
+  0,12,14,12,12,12,12,63,
+  0,30,51,48,28,6,51,63,
+  0,30,51,48,28,48,51,30,
+  0,56,60,54,51,127,48,120,
+  0,63,3,31,48,48,51,30,
+  0,28,6,3,31,51,51,30,
+  0,63,51,48,24,12,12,12,
+  0,30,51,51,30,51,51,30,
+  0,30,51,51,62,48,24,14,
+  0,0,12,12,0,0,12,12,
+  0,0,12,12,0,0,12,12,
+  6,24,12,6,3,6,12,24,
+  0,0,0,63,0,0,63,0,
+  0,6,12,24,48,24,12,6,
+  0,30,51,48,24,12,0,12,
+  0,62,99,123,123,123,3,30,
+  0,12,30,51,51,63,51,51,
+  0,63,102,102,62,102,102,63,
+  0,60,102,3,3,3,102,60,
+  0,31,54,102,102,102,54,31,
+  0,127,70,22,30,22,70,127,
+  0,127,70,22,30,22,6,15,
+  0,60,102,3,3,115,102,124,
+  0,51,51,51,63,51,51,51,
+  0,30,12,12,12,12,12,30,
+  0,120,48,48,48,51,51,30,
+  0,103,102,54,30,54,102,103,
+  0,15,6,6,6,70,102,127,
+  0,99,119,127,127,107,99,99,
+  0,99,103,111,123,115,99,99,
+  0,28,54,99,99,99,54,28,
+  0,63,102,102,62,6,6,15,
+  0,30,51,51,51,59,30,56,
+  0,63,102,102,62,54,102,103,
+  0,30,51,7,14,56,51,30,
+  0,63,45,12,12,12,12,30,
+  0,51,51,51,51,51,51,63,
+  0,51,51,51,51,51,30,12,
+  0,99,99,99,107,127,119,99,
+  0,99,99,54,28,28,54,99,
+  0,51,51,51,30,12,12,30,
+  0,127,99,49,24,76,102,127,
+  0,30,6,6,6,6,6,30,
+  0,3,6,12,24,48,96,64,
+  0,30,24,24,24,24,24,30,
+  0,8,28,54,99,0,0,0,
+  0,0,0,0,0,0,0,0,
+  255,12,12,24,0,0,0,0,
+  0,0,0,30,48,62,51,110,
+  0,7,6,6,62,102,102,59,
+  0,0,0,30,51,3,51,30,
+  0,56,48,48,62,51,51,110,
+  0,0,0,30,51,63,3,30,
+  0,28,54,6,15,6,6,15,
+  0,0,0,110,51,51,62,48,
+  31,7,6,54,110,102,102,103,
+  0,12,0,14,12,12,12,30,
+  0,48,0,48,48,48,51,51,
+  30,7,6,102,54,30,54,103,
+  0,14,12,12,12,12,12,30,
+  0,0,0,51,127,127,107,99,
+  0,0,0,31,51,51,51,51,
+  0,0,0,30,51,51,51,30,
+  0,0,0,59,102,102,62,6,
+  15,0,0,110,51,51,62,48,
+  120,0,0,59,110,102,6,15,
+  0,0,0,62,3,30,48,31,
+  0,8,12,62,12,12,44,24,
+  0,0,0,51,51,51,51,110,
+  0,0,0,51,51,51,30,12,
+  0,0,0,99,107,127,127,54,
+  0,0,0,99,54,28,54,99,
+  0,0,0,51,51,51,62,48,
+  31,0,0,63,25,12,38,63,
+  0,56,12,12,7,12,12,56,
+  0,24,24,24,0,24,24,24,
+  0,7,12,12,56,12,12,7,
+  0,110,59,0,0,0,0,0,
+  0,0,8,28,54,99,99,127,
+  0,30,51,3,51,30,24,48,
+  30,0,51,0,51,51,51,126,
+  0,56,0,30,51,63,3,30,
+  0,126,195,60,96,124,102,252,
+  0,51,0,30,48,62,51,126,
+  0,7,0,30,48,62,51,126,
+  0,12,12,30,48,62,51,126,
+  0,0,0,30,3,3,30,48,
+  28,126,195,60,102,126,6,60,
+  0,51,0,30,51,63,3,30,
+  0,7,0,30,51,63,3,30,
+  0,51,0,14,12,12,12,30,
+  0,62,99,28,24,24,24,60,
+  0,7,0,14,12,12,12,30,
+  0,99,28,54,99,127,99,99,
+  0,12,12,0,30,51,63,51,
+  0,56,0,63,6,30,6,63,
+  0,0,0,254,48,254,51,254,
+  0,124,54,51,127,51,51,115,
+  0,30,51,0,30,51,51,30,
+  0,0,51,0,30,51,51,30,
+  0,0,7,0,30,51,51,30,
+  0,30,51,0,51,51,51,126,
+  0,0,7,0,51,51,51,126,
+  0,0,51,0,51,51,62,48,
+  31,195,24,60,102,102,60,24,
+  0,51,0,51,51,51,51,30,
+  0,24,24,126,3,3,126,24,
+  24,28,54,38,15,6,103,63,
+  0,51,51,30,63,12,63,12,
+  12,31,51,51,95,99,243,99,
+  227,112,216,24,60,24,24,27,
+  14,56,0,30,48,62,51,126,
+  0,28,0,14,12,12,12,30,
+  0,0,56,0,30,51,51,30,
+  0,0,56,0,51,51,51,126,
+  0,0,31,0,31,51,51,51,
+  0,63,0,51,55,63,59,51,
+  0,60,54,54,124,0,126,0,
+  0,28,54,54,28,0,62,0,
+  0,12,0,12,6,3,51,30,
+  0,0,0,0,63,3,3,0,
+  0,0,0,0,63,48,48,0,
+  0,195,99,51,123,204,102,51,
+  240,195,99,51,219,236,246,243,
+  192,24,24,0,24,24,24,24,
+  0,0,204,102,51,102,204,0,
+  0,0,51,102,204,102,51,0,
+  0,68,17,68,17,68,17,68,
+  17,170,85,170,85,170,85,170,
+  85,219,238,219,119,219,238,219,
+  119,24,24,24,24,24,24,24,
+  24,24,24,24,24,31,24,24,
+  24,24,24,31,24,31,24,24,
+  24,108,108,108,108,111,108,108,
+  108,0,0,0,0,127,108,108,
+  108,0,0,31,24,31,24,24,
+  24,108,108,111,96,111,108,108,
+  108,108,108,108,108,108,108,108,
+  108,0,0,127,96,111,108,108,
+  108,108,108,111,96,127,0,0,
+  0,108,108,108,108,127,0,0,
+  0,24,24,31,24,31,0,0,
+  0,0,0,0,0,31,24,24,
+  24,24,24,24,24,248,0,0,
+  0,24,24,24,24,255,0,0,
+  0,0,0,0,0,255,24,24,
+  24,24,24,24,24,248,24,24,
+  24,0,0,0,0,255,0,0,
+  0,24,24,24,24,255,24,24,
+  24,24,24,248,24,248,24,24,
+  24,108,108,108,108,236,108,108,
+  108,108,108,236,12,252,0,0,
+  0,0,0,252,12,236,108,108,
+  108,108,108,239,0,255,0,0,
+  0,0,0,255,0,239,108,108,
+  108,108,108,236,12,236,108,108,
+  108,0,0,255,0,255,0,0,
+  0,108,108,239,0,239,108,108,
+  108,24,24,255,0,255,0,0,
+  0,108,108,108,108,255,0,0,
+  0,0,0,255,0,255,24,24,
+  24,0,0,0,0,255,108,108,
+  108,108,108,108,108,252,0,0,
+  0,24,24,248,24,248,0,0,
+  0,0,0,248,24,248,24,24,
+  24,0,0,0,0,252,108,108,
+  108,108,108,108,108,255,108,108,
+  108,24,24,255,24,255,24,24,
+  24,24,24,24,24,31,0,0,
+  0,0,0,0,0,248,24,24,
+  24,255,255,255,255,255,255,255,
+  255,0,0,0,0,255,255,255,
+  255,15,15,15,15,15,15,15,
+  15,240,240,240,240,240,240,240,
+  240,255,255,255,255,0,0,0,
+  0,0,0,110,59,19,59,110,
+  0,0,30,51,31,51,31,3,
+  3,0,63,51,3,3,3,3,
+  0,0,127,54,54,54,54,54,
+  0,63,51,6,12,6,51,63,
+  0,0,0,126,27,27,27,14,
+  0,0,102,102,102,102,62,6,
+  3,0,110,59,24,24,24,24,
+  0,63,12,30,51,51,30,12,
+  63,28,54,99,127,99,54,28,
+  0,28,54,99,99,54,54,119,
+  0,56,12,24,62,51,51,30,
+  0,0,0,126,219,219,126,0,
+  0,96,48,126,219,219,126,6,
+  3,28,6,3,31,3,6,28,
+  0,30,51,51,51,51,51,51,
+  0,0,63,0,63,0,63,0,
+  0,12,12,63,12,12,0,63,
+  0,6,12,24,12,6,0,63,
+  0,24,12,6,12,24,0,63,
+  0,112,216,216,24,24,24,24,
+  24,24,24,24,24,24,27,27,
+  14,12,12,0,63,0,12,12,
+  0,0,110,59,0,110,59,0,
+  0,28,54,54,28,0,0,0,
+  0,0,0,0,24,24,0,0,
+  0,0,0,0,0,24,0,0,
+  0,240,48,48,48,55,54,60,
+  56,30,54,54,54,54,0,0,
+  0,14,24,12,6,30,0,0,
+  0,0,0,60,60,60,60,0,
+  0,0,0,0,0,0,0,0,0
+};
+
diff --git a/MCUME_pico2/pico8086/i8253.cpp b/MCUME_pico2/pico8086/i8253.cpp
new file mode 100644
index 0000000..5c02cc8
--- /dev/null
+++ b/MCUME_pico2/pico8086/i8253.cpp
@@ -0,0 +1,114 @@
+#include <stdint.h>
+#include <string.h>
+
+/*
+#ifdef MEGA
+  #include <TimerOne.h>
+#else
+IntervalTimer myTimer;
+#endif
+*/
+
+#define PIT_MODE_LATCHCOUNT  0
+#define PIT_MODE_LOBYTE 1
+#define PIT_MODE_HIBYTE 2
+#define PIT_MODE_TOGGLE 3
+
+
+struct i8253_s {
+  uint16_t chandata[3];
+  uint8_t accessmode[3];
+  uint8_t bytetoggle[3];
+  uint32_t effectivedata[3];
+  float chanfreq[3];
+  uint8_t active[3];
+  uint16_t counter[3];
+} i8253;
+
+volatile uint8_t timerTick = 0;
+
+void timer_isr(void) {
+  timerTick = 1;
+}
+
+void out8253 (uint16_t portnum, uint8_t value) {
+  uint8_t curbyte;
+  portnum &= 3;
+  switch (portnum) {
+      case 0:
+      case 1:
+      case 2: //channel data
+        if ( (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
+        else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
+        if (curbyte == 0) { //low byte
+            i8253.chandata[portnum] = (i8253.chandata[portnum] & 0xFF00) | value;
+          }
+        else {   //high byte
+            i8253.chandata[portnum] = (i8253.chandata[portnum] & 0x00FF) | ( (uint16_t) value << 8);
+          }
+        if (i8253.chandata[portnum] == 0) i8253.effectivedata[portnum] = 65536;
+        else i8253.effectivedata[portnum] = i8253.chandata[portnum];
+        i8253.active[portnum] = 1;
+        if (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1;
+        //i8253.chanfreq[portnum] = (float) ( (uint32_t) ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]) * (float) 1000.0) );
+        //Serial.print("period "); Serial.println((uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]))));
+        if (portnum == 0) {
+          uint32_t period;
+          period = (uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum])));
+/*
+#ifdef MEGA
+          if (period < 4000) period = 4000; //limit to 250 Hz, or the emulator just can't keep up on a Mega
+          //Serial.println((float)1000000.0 / (float)period);
+          Timer1.attachInterrupt(timer_isr, period);
+#else
+          myTimer.begin(timer_isr, period);
+#endif
+*/
+        }
+        break;
+      case 3: //mode/command
+        i8253.accessmode[value>>6] = (value >> 4) & 3;
+        if (i8253.accessmode[value>>6] == PIT_MODE_TOGGLE) i8253.bytetoggle[value>>6] = 0;
+        break;
+    }
+}
+
+uint8_t in8253 (uint16_t portnum) {
+  uint8_t curbyte;
+  portnum &= 3;
+  switch (portnum) {
+      case 0:
+      case 1:
+      case 2: //channel data
+        if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
+        else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
+        if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0;
+        else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1;
+        if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) ) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1;
+        if (curbyte == 0) { //low byte
+          if (i8253.counter[portnum] < 10) i8253.counter[portnum] = i8253.chandata[portnum];
+          i8253.counter[portnum] -= 10;
+            return ( (uint8_t) i8253.counter[portnum]);
+          }
+        else {   //high byte
+            return ( (uint8_t) (i8253.counter[portnum] >> 8) );
+          }
+        break;
+    }
+  return (0);
+}
+
+void init8253() {
+  memset (&i8253, 0, sizeof (i8253) );
+/*
+#ifdef MEGA
+  Timer1.initialize(54925);
+  Timer1.attachInterrupt(timer_isr, 54925);
+#else
+  myTimer.begin(timer_isr, 54925);
+#endif
+*/
+  //set_port_write_redirector (0x40, 0x43, &out8253);
+  //set_port_read_redirector (0x40, 0x43, &in8253);
+}
+
diff --git a/MCUME_pico2/pico8086/i8259.cpp b/MCUME_pico2/pico8086/i8259.cpp
new file mode 100755
index 0000000..f26f2cd
--- /dev/null
+++ b/MCUME_pico2/pico8086/i8259.cpp
@@ -0,0 +1,83 @@
+/* i8259.c - emulation code for the Intel 8259 controller.
+   Note: This is not a very complete i8259 interrupt controller
+   implementation, but for the purposes of a PC, it's all we need. */
+
+#include <stdint.h>
+#include <string.h>
+
+struct structpic {
+  uint8_t imr; //mask register
+  uint8_t irr; //request register
+  uint8_t isr; //service register
+  uint8_t icwstep; //used during initialization to keep track of which ICW we're at
+  uint8_t icw[5];
+  uint8_t intoffset; //interrupt vector offset
+  uint8_t priority; //which IRQ has highest priority
+  uint8_t autoeoi; //automatic EOI mode
+  uint8_t readmode; //remember what to return on read register from OCW3
+  uint8_t enabled;
+} i8259;
+
+
+void init8259() {
+     memset((void *)&i8259, 0, sizeof(i8259));
+}
+
+uint8_t in8259(uint16_t portnum) {
+        switch (portnum & 1) {
+               case 0:
+                    if (i8259.readmode==0) return(i8259.irr); else return(i8259.isr);
+               case 1: //read mask register
+                    return(i8259.imr);
+                }
+                return(0); //can't get here, but the compiler bitches
+}
+
+extern uint32_t makeupticks;
+void out8259(uint16_t portnum, uint8_t value) {
+     uint8_t i;
+     switch (portnum & 1) {
+            case 0:
+                 if (value & 0x10) { //begin initialization sequence
+                    i8259.icwstep = 1;
+                    i8259.imr = 0; //clear interrupt mask register
+                    i8259.icw[i8259.icwstep++] = value;
+                    return;
+                 }
+                 if ((value & 0x98)==8) { //it's an OCW3
+                    if (value & 2) i8259.readmode = value & 2;
+                 }
+                 if (value & 0x20) { //EOI command
+                    for (i=0; i<8; i++)
+                        if ((i8259.isr >> i) & 1) {
+                           i8259.isr ^= (1 << i);
+                           if ((i==0) && (makeupticks>0)) { makeupticks = 0; i8259.irr |= 1; }
+                           return;
+                        }
+                 }
+                 break;
+            case 1:
+                 if ((i8259.icwstep==3) && (i8259.icw[1] & 2)) i8259.icwstep = 4; //single mode, so don't read ICW3
+                 if (i8259.icwstep<5) { i8259.icw[i8259.icwstep++] = value; return; }
+                 //if we get to this point, this is just a new IMR value
+                 i8259.imr = value;
+                 break;
+     }
+}
+
+uint8_t nextintr() {
+        uint8_t i, tmpirr;
+        tmpirr = i8259.irr & (~i8259.imr); //XOR request register with inverted mask register
+        for (i=0; i<8; i++)
+            if ((tmpirr >> i) & 1) {
+               i8259.irr ^= (1 << i);
+               i8259.isr |= (1 << i);
+               return(i8259.icw[2] + i);
+                        }
+                return(0); //can't get here, but the compiler bitches
+}
+
+void doirq(uint8_t irqnum) {
+     i8259.irr |= (1 << irqnum);
+}
+
diff --git a/MCUME_pico2/pico8086/intf.h b/MCUME_pico2/pico8086/intf.h
new file mode 100644
index 0000000..57d1eca
--- /dev/null
+++ b/MCUME_pico2/pico8086/intf.h
@@ -0,0 +1,148 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+//  #define RAM_SIZE 0xF8000 // 512k //655360UL
+//  #define NATIVE_RAM (0X28000) //  128k+32768 //231424UL
+
+
+
+#define RAM_SIZE 0x80000 // 512k //655360UL
+#define NATIVE_RAM (0X40000) //  256k
+#define NATIVE_START 0UL
+
+
+
+#define ROM_READ(a,b) a[b]
+
+
+//#define INCLUDE_ROM_BASIC
+
+
+//#define BOOT_FDD
+#define BOOT_HDD
+//#define BOOT_BASIC
+
+//#define FDD_180K
+//#define FDD_320K
+//#define FDD_360K
+//#define FDD_720K
+//#define FDD_122M
+//#define FDD_144M
+
+
+#define BAUD_RATE 1000000
+
+//#define USE_NETWORKING
+//#define USE_PARALLEL
+
+//#define PROFILING
+
+// END ARDUINO86 USER CONFIGURABLE OPTIONS
+
+#define regax 0
+#define regcx 1
+#define regdx 2
+#define regbx 3
+#define regsp 4
+#define regbp 5
+#define regsi 6
+#define regdi 7
+#define reges 0
+#define regcs 1
+#define regss 2
+#define regds 3
+
+#define regal 0
+#define regah 1
+#define regcl 2
+#define regch 3
+#define regdl 4
+#define regdh 5
+#define regbl 6
+#define regbh 7
+
+#define StepIP(x) ip+=x
+#define getmem8(x,y) read86(segbase(x)+(uint32_t)y)
+//#define getmem16(x,y) (read86(segbase(x)+y) | ((uint16_t)read86(segbase(x)+y+1)<<8))
+#define getmem16(x,y) readw86(segbase(x)+(uint32_t)y)
+#define putmem8(x,y,z) write86(segbase(x)+(uint32_t)y, z)
+//#define putmem16(x,y,z) write86(segbase(x)+y, ((z)&0xFF)); write86(segbase(x)+y+1, (((z)>>8)&0xFF))
+#define putmem16(x,y,z) writew86(segbase(x)+(uint32_t)y, z)
+#define signext(value) ((((uint16_t)value&0x80)*0x1FE)|(uint16_t)value)
+#define signext32(value) ((((uint32_t)value&0x8000)*0x1FFFE)|(uint32_t)value)
+#define getreg16(regid) regs.wordregs[regid]
+#define getreg8(regid) regs.byteregs[byteregtable[regid]]
+#define putreg16(regid, writeval) regs.wordregs[regid] = writeval
+#define putreg8(regid, writeval) regs.byteregs[byteregtable[regid]] = writeval
+#define getsegreg(regid) segregs[regid]
+#define putsegreg(regid, writeval) segregs[regid] = writeval
+#define segbase(x) ((uint32_t)x<<4)
+
+#define makeflagsword() (2 | (uint16_t)cf | ((uint16_t)pf << 2) | ((uint16_t)af << 4) | ((uint16_t)zf << 6) \
+        | ((uint16_t)sf << 7) | ((uint16_t)tf << 8) | ((uint16_t)ifl << 9) | ((uint16_t)df << 10) | ((uint16_t)of << 11))
+
+#define decodeflagsword(x) {\
+        temp16 = x;\
+        cf = temp16 & 1;\
+        pf = (temp16 >> 2) & 1;\
+        af = (temp16 >> 4) & 1;\
+        zf = (temp16 >> 6) & 1;\
+        sf = (temp16 >> 7) & 1;\
+        tf = (temp16 >> 8) & 1;\
+        ifl = (temp16 >> 9) & 1;\
+        df = (temp16 >> 10) & 1;\
+        of = (temp16 >> 11) & 1;\
+}
+
+
+void setup_memory();
+void setup_timer();
+uint8_t insertdisk(uint8_t drivenum);
+void reset86();
+void exec86(uint32_t execloops);
+uint8_t read86(uint32_t addr32);
+void write86(uint32_t addr32, uint8_t value);
+void doirq(uint8_t irqnum);
+void incsends();
+void init_display();
+void write_video(uint16_t addr);
+void clear_display();
+void palettereset();
+void display_CSIP();
+void ps2poll();
+void setup_ps2(uint8_t data_pin, uint8_t irq_pin);
+void video_init();
+uint8_t VRAM_read(uint32_t addr32);
+void VRAM_write(uint32_t addr32, uint8_t value);
+void setup_ps2(uint8_t data_pin, uint8_t irq_pin);
+void ps2poll();
+void out8253 (uint16_t portnum, uint8_t value);
+uint8_t in8253 (uint16_t portnum);
+void init8259();
+void out8259(uint16_t portnum, uint8_t value);
+uint8_t in8259(uint16_t portnum);
+
+extern uint8_t port3da;
+
+void initDisk(char * filename);
+void init8253();
+void net_init();
+void net_loop();
+void net_handler();
+uint8_t cached_read(uint32_t addr32);
+void cached_write(uint32_t addr32, uint8_t value);
+void cache_init();
+
+uint8_t net_read_ram(uint32_t addr32);
+void diskhandler();
+
+//extern uint8_t SPI_RAM_pins[8];
+extern uint8_t net_mac[6];
+extern uint8_t bufSerial[1600];
+void outByte(uint8_t cc);
+
+extern struct i8253_s i8253;
+union _bytewordregs_{
+  uint16_t wordregs[8];
+  uint8_t byteregs[8];
+} ;
diff --git a/MCUME_pico2/pico8086/keyboard_osd.h b/MCUME_pico2/pico8086/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/pico8086/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/pico8086/network.cpp b/MCUME_pico2/pico8086/network.cpp
new file mode 100755
index 0000000..755bed9
--- /dev/null
+++ b/MCUME_pico2/pico8086/network.cpp
@@ -0,0 +1,146 @@
+
+#include <stdint.h>
+#include <string.h>
+
+#include "intf.h"
+
+
+#ifdef USE_ENC28J60
+#include <enc28j60.h>
+
+byte ENC28J60::buffer[1514];
+//uint8_t net_mac[6] = { 0x90, 0xAD, 0xBE, 0xEF, 0x13, 0x37 };
+uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 };
+
+extern union _bytewordregs_ regs;
+extern uint16_t segregs[6];
+
+struct netstruct {
+  uint8_t enabled;
+  uint8_t canrecv;
+  uint16_t pktlen;
+} net;
+
+void net_handler() {
+  uint32_t i;
+  uint16_t j;
+  //if (ethif==254) return; //networking not enabled
+  switch (regs.byteregs[regah]) { //function number
+      case 0x00: //enable packet reception
+        net.enabled = 1;
+        net.canrecv = 1;
+        return;
+      case 0x01: //send packet of CX at DS:SI
+        //if (verbose) {
+            //Serial.println("Sending packet of %u bytes.", regs.wordregs[regcx]);
+          //}
+        //sendpkt (&RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]], regs.wordregs[regcx]);
+        i = ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi];
+        for (j=0; j<net.pktlen; j++) {
+          ENC28J60::buffer[j] = read86(i++);
+        }
+        SPI.setClockDivider(SPI_CLOCK_ENC28J60);
+        ENC28J60::packetSend(segregs[regcx]);
+        SPI.setClockDivider(SPI_CLOCK_SPIRAM);
+        return;
+      case 0x02: //return packet info (packet buffer in DS:SI, length in CX)
+        segregs[regds] = 0xD000;
+        regs.wordregs[regsi] = 0x0000;
+        regs.wordregs[regcx] = net.pktlen;
+        return;
+      case 0x03: //copy packet to final destination (given in ES:DI)
+        //memcpy (&RAM[ ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi]], &RAM[0xD0000], net.pktlen);
+        i = ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi];
+        for (j=0; j<net.pktlen; j++) {
+          write86(i++, ENC28J60::buffer[j]);
+        }
+        net.canrecv = 1;
+        net.pktlen = 0;
+        return;
+      case 0x04: //disable packets
+        net.enabled = 0;
+        net.canrecv = 0;
+        return;
+      case 0x05: //DEBUG: dump packet (DS:SI) of CX bytes to stdout
+        /*for (i=0; i<regs.wordregs[regcx]; i++) {
+            printf ("%c", RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi] + i]);
+          }*/
+        return;
+      case 0x06: //DEBUG: print milestone string
+        //print("PACKET DRIVER MILESTONE REACHED\n");
+        return;
+    }
+}
+
+uint8_t net_read_ram(uint32_t addr32) {
+  if (addr32 < 1514) return ENC28J60::buffer[addr32];
+  return 0;
+}
+
+/*void net_write_ram(uint32_t addr32, uint8_t value) {
+  if (addr32 < 1514) ENC28J60::buffer[addr32] = value;
+}*/
+
+void net_loop() {
+  uint16_t i, len;
+  uint8_t cc;
+  if (!net.enabled || !net.canrecv) return;
+  SPI.setClockDivider(SPI_CLOCK_ENC28J60);
+  len = ENC28J60::packetReceive();
+  SPI.setClockDivider(SPI_CLOCK_SPIRAM);
+  if (len > 0) {
+    for (i=0; i<len; i++) {
+      Serial.print(ENC28J60::buffer[i], HEX);
+      Serial.write(' ');
+    }
+    Serial.println("");
+    Serial.println("");
+    net.canrecv = 0;
+    net.pktlen = len;
+    doirq(6);
+  }
+}
+
+void net_init() {
+  uint8_t ret;
+  Serial.println("enter net_init");
+  //SPI.setClockDivider(SPI_CLOCK_ENC28J60);
+  ret = ENC28J60::initialize(1514, net_mac, NET_PIN);
+  //SPI.setClockDivider(SPI_CLOCK_LCD);
+  Serial.print("net init result = ");
+  Serial.println(ret);
+  ENC28J60::enablePromiscuous();
+  //ENC28J60::broadcast_enabled = true;
+  while(1) {
+    uint16_t len, i;
+    //delay(100);
+    //SPI.setClockDivider(SPI_CLOCK_ENC28J60);
+    len = ENC28J60::packetReceive();
+    //SPI.setClockDivider(SPI_CLOCK_LCD);
+    if (len > 0) {
+      for (i=0; i<len; i++) {
+        Serial.print(ENC28J60::buffer[i], HEX);
+        Serial.write(' ');
+      }
+      Serial.println("");
+      Serial.println("");
+    }
+  }
+}
+#else
+uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 };
+
+
+void net_init() {
+}  
+
+void net_loop() {
+}
+
+void net_handler() {
+}
+uint8_t net_read_ram(uint32_t addr32) {
+  return 0;
+}
+#endif
+
diff --git a/MCUME_pico2/pico8086/pico8086.cpp b/MCUME_pico2/pico8086/pico8086.cpp
new file mode 100644
index 0000000..057261b
--- /dev/null
+++ b/MCUME_pico2/pico8086/pico8086.cpp
@@ -0,0 +1,189 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);         
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+//psram_spi_inst_t* async_spi_inst;
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+//    set_sys_clock_khz(125000, true);
+
+    set_sys_clock_khz(280000, true);
+    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+     emu_init();
+   
+
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(5, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    } 
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/pico8086/ports.cpp b/MCUME_pico2/pico8086/ports.cpp
new file mode 100755
index 0000000..c59fa98
--- /dev/null
+++ b/MCUME_pico2/pico8086/ports.cpp
@@ -0,0 +1,98 @@
+/* ports.c - handles port I/O for Fake86 CPU core. it's ugly, will fix up later. */
+
+#include <stdint.h>
+#include "intf.h"
+
+volatile uint16_t pit0counter = 65535;
+volatile uint32_t speakercountdown, latch42, pit0latch, pit0command, pit0divisor;
+uint8_t portram[0x400];
+uint8_t crt_controller_idx, crt_controller[256], port3D9 = 0;
+
+void portout(uint16_t portnum, uint16_t value) {
+  if (portnum < 0x400) portram[portnum] = value;
+  switch (portnum) {
+    case 0x20:
+    case 0x21: //i8259
+      out8259(portnum, value);
+      return;
+    case 0x40:
+    case 0x41:
+    case 0x42:
+    case 0x43: //i8253
+      out8253(portnum, value);
+      break;
+    case 0x3D4:
+      crt_controller_idx = value;
+      break;
+    case 0x3D5:
+      crt_controller[crt_controller_idx] = value;
+      if ((crt_controller_idx == 0x0E) || (crt_controller_idx == 0x0F)) {
+        //setcursor(((uint16_t)crt_controller[0x0E] << 8) | crt_controller[0x0F]);
+        //Serial.write(27); Serial.write('['); Serial.print(crt_controller[0x0E] + 1); Serial.write(';'); Serial.print(crt_controller[0x0F] + 1); Serial.write('H');
+      }
+      break;
+    case 0x3D9:
+      port3D9 = value;
+      break;
+  }
+
+#ifdef ADVANCED_CLIENT
+  if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) {
+    uint8_t chksum;
+    Serial.write(0xFF);
+    Serial.write(0x04);
+    outByte(portnum & 0xFF); chksum = portnum & 0xFF;
+    outByte(portnum >> 8); chksum += portnum >> 8;
+    outByte(value); chksum += value;
+    outByte(chksum);
+    Serial.write(0xFE);
+    Serial.write(0x02);
+  }
+#endif
+
+#ifdef VGA
+  if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) outVGA(portnum, value);
+#endif
+}
+
+uint16_t portin(uint16_t portnum) {
+#ifdef VGA
+  if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) return inVGA(portnum);
+#endif
+/*  uint8_t chksum;
+  Serial.write(0xFF);
+  Serial.write(0x07);
+  outByte(portnum & 0xFF); chksum = portnum & 0xFF;
+  outByte((portnum >> 8) & 0xFF); chksum += (portnum >> 8) & 0xFF;
+  outByte(chksum);
+  Serial.write(0xFE);
+  Serial.write(0x02);*/
+  switch (portnum) {
+    case 0x20:
+    case 0x21: //i8259
+      return (in8259(portnum));
+    case 0x40:
+    case 0x41:
+    case 0x42:
+    case 0x43: //i8253
+      return in8253(portnum);
+    case 0x60:
+    case 0x64:
+      return portram[portnum];
+    case 0x3D4:
+      return crt_controller_idx;
+      break;
+    case 0x3D5:
+      return crt_controller[crt_controller_idx];
+      break;
+    case 0x3DA:
+      port3da ^= 1;
+      if (!(port3da & 1)) port3da ^= 8;
+      //port3da = random(256) & 9;
+      return (port3da);
+    default:
+      return (0xFF);
+  }
+}
+
+
diff --git a/MCUME_pico2/pico8086/program_config.h b/MCUME_pico2/pico8086/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/pico8086/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/pico8086/ps2.h b/MCUME_pico2/pico8086/ps2.h
new file mode 100755
index 0000000..dc6f578
--- /dev/null
+++ b/MCUME_pico2/pico8086/ps2.h
@@ -0,0 +1,89 @@
+uint8_t translatescancode(uint32_t keysym) {
+  if ((keysym >= 'a') && (keysym <= 'z')) {
+    keysym -= 0x20;
+  }
+  switch (keysym) {
+    case 0xFF08: return 0x0E; //backspace
+    case 0xFF09: return 0x0F; //tab
+    case 0xFF0D: return 0x1C; //enter
+    case 0xFF1B: return 0x01; //escape
+    case 0xFF63: return 0x52; //KP 0 / insert
+    case 0xFFFF: return 0x53; //KP . / delete
+    case 0xFF55: return 0x49; //pgup
+    case 0xFF56: return 0x51; //pgdn
+    case 0xFF50: return 0x47; //home
+    case 0xFF57: return 0x4F; //end
+    case 'A': return 0x1E;
+    case 'B': return 0x30;
+    case 'C': return 0x2E;
+    case 'D': return 0x20;
+    case 'E': return 0x12;
+    case 'F': return 0x21;
+    case 'G': return 0x22;
+    case 'H': return 0x23;
+    case 'I': return 0x17;
+    case 'J': return 0x24;
+    case 'K': return 0x25;
+    case 'L': return 0x26;
+    case 'M': return 0x32;
+    case 'N': return 0x31;
+    case 'O': return 0x18;
+    case 'P': return 0x19;
+    case 'Q': return 0x10;
+    case 'R': return 0x13;
+    case 'S': return 0x1F;
+    case 'T': return 0x14;
+    case 'U': return 0x16;
+    case 'V': return 0x2F;
+    case 'W': return 0x11;
+    case 'X': return 0x2D;
+    case 'Y': return 0x15;
+    case 'Z': return 0x2C;
+    case '0': case ')': return 0x0B;
+    case '1': case '!': return 0x02;
+    case '2': case '@': return 0x03;
+    case '3': case '#': return 0x04;
+    case '4': case '$': return 0x05;
+    case '5': case '%': return 0x06;
+    case '6': case '^': return 0x07;
+    case '7': case '&': return 0x08;
+    case '8': case '*': return 0x09;
+    case '9': case '(': return 0x0A;
+    case '`': case '~': return 0x29;
+    case '-': case '_': return 0x0C;
+    case '=': case '+': return 0x0D;
+    case '[': case '{': return 0x1A;
+    case ']': case '}': return 0x1B;
+    case '\\': case '|': return 0x2B;
+    case ';': case ':': return 0x27;
+    case '\'': case '"': return 0x28;
+    case ' ': return 0x39;
+    case ',': case '<': return 0x33;
+    case '.': case '>': return 0x34;
+    case '/': case '?': return 0x35;
+    case 0xFFBE: return 0x3B; //F1
+    case 0xFFBF: return 0x3C; //F2
+    case 0xFFC0: return 0x3D; //F3
+    case 0xFFC1: return 0x3E; //F4
+    case 0xFFC2: return 0x3F; //F5
+    case 0xFFC3: return 0x40; //F6
+    case 0xFFC4: return 0x41; //F7
+    case 0xFFC5: return 0x42; //F8
+    case 0xFFC6: return 0x43; //F9
+    case 0xFFC7: return 0x44; //F10
+    case 0xFFC8: return 0x57; //F11
+    case 0xFFC9: return 0x58; //F12
+    case 0xFFE1: return 0x2A; //left shift
+    case 0xFFE2: return 0x36; //right shift
+    case 0xFFE3: case 0xFFE4: return 0x1D; //control
+    case 0xFFE9: case 0xFFEA: return 0x38; //alt
+    case 0xFF51: return 0x4B; //left
+    case 0xFF52: return 0x48; //up
+    case 0xFF53: return 0x4D; //right
+    case 0xFF54: return 0x50; //down
+  }
+  return 0xFF;
+}
+
+
+
diff --git a/MCUME_pico2/pico8086/rom.h b/MCUME_pico2/pico8086/rom.h
new file mode 100644
index 0000000..cd73b08
--- /dev/null
+++ b/MCUME_pico2/pico8086/rom.h
@@ -0,0 +1,3744 @@
+  const uint8_t BIOS[8192] = {
+  0x54, 0x75, 0x72, 0x62, 0x6F, 0x20, 0x58, 0x54, 0x20, 0x42, 0x49,
+  0x4F, 0x53, 0x20, 0x76, 0x32, 0x2E, 0x35, 0x20, 0x66, 0x6F, 0x72,
+  0x20, 0x38, 0x30, 0x38, 0x38, 0x2F, 0x56, 0x32, 0x30, 0x00, 0xC3,
+  0x20, 0x45, 0x47, 0x41, 0x2F, 0x56, 0x47, 0x41, 0x20, 0x47, 0x72,
+  0x61, 0x70, 0x68, 0x69, 0x63, 0x73, 0x00, 0xC3, 0x20, 0x50, 0x61,
+  0x72, 0x61, 0x6C, 0x6C, 0x65, 0x6C, 0x20, 0x50, 0x6F, 0x72, 0x74,
+  0x20, 0x61, 0x74, 0x20, 0x00, 0xC3, 0x20, 0x47, 0x61, 0x6D, 0x65,
+  0x20, 0x50, 0x6F, 0x72, 0x74, 0x20, 0x61, 0x74, 0x20, 0x32, 0x30,
+  0x31, 0x68, 0x00, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0xC7, 0x06, 0x72,
+  0x00, 0x00, 0x00, 0xFA, 0xFC, 0xB0, 0x00, 0xE6, 0xA0, 0xBA, 0xD8,
+  0x03, 0xEE, 0xBA, 0xB8, 0x03, 0xFE, 0xC0, 0xEE, 0xB0, 0x99, 0xE6,
+  0x63, 0xB0, 0xA5, 0xE6, 0x61, 0xB0, 0x54, 0xE6, 0x43, 0xB0, 0x12,
+  0xE6, 0x41, 0xB0, 0x40, 0xE6, 0x43, 0xB0, 0x00, 0xE6, 0x81, 0xE6,
+  0x82, 0xE6, 0x83, 0xE6, 0x0D, 0xB0, 0x58, 0xE6, 0x0B, 0xB0, 0x41,
+  0xE6, 0x0B, 0xB0, 0x42, 0xE6, 0x0B, 0xB0, 0x43, 0xE6, 0x0B, 0xB0,
+  0xFF, 0xE6, 0x01, 0xE6, 0x01, 0xB0, 0x00, 0xE6, 0x08, 0xE6, 0x0A,
+  0xB0, 0x36, 0xE6, 0x43, 0xB0, 0x00, 0xE6, 0x40, 0xE6, 0x40, 0xBA,
+  0x13, 0x02, 0xB0, 0x01, 0xEE, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0x8B,
+  0x36, 0x72, 0x00, 0x33, 0xC0, 0x8B, 0xE8, 0x8B, 0xD8, 0xBA, 0xAA,
+  0x55, 0xFC, 0x33, 0xFF, 0x8E, 0xC3, 0x26, 0x89, 0x15, 0x26, 0x3B,
+  0x15, 0x75, 0x0D, 0xB9, 0x00, 0x20, 0xF3, 0xAB, 0x80, 0xC7, 0x04,
+  0x80, 0xFF, 0xA0, 0x72, 0xE7, 0x33, 0xC0, 0x8E, 0xC0, 0xB8, 0x80,
+  0x00, 0x8E, 0xD0, 0xBC, 0x00, 0x01, 0x55, 0x53, 0xBD, 0x02, 0x00,
+  0xE8, 0x19, 0x19, 0x89, 0x36, 0x72, 0x00, 0x58, 0xB1, 0x06, 0xD3,
+  0xE8, 0xA3, 0x13, 0x00, 0x58, 0x73, 0x02, 0x0C, 0x10, 0xA2, 0x15,
+  0x00, 0x33, 0xC0, 0x50, 0x50, 0x50, 0x50, 0x50, 0xB8, 0x30, 0x00,
+  0x8E, 0xD0, 0xBC, 0x00, 0x01, 0x1E, 0xBB, 0x00, 0xE0, 0x0E, 0x1F,
+  0xB4, 0x01, 0xE8, 0xDE, 0x18, 0x1F, 0x74, 0x05, 0x80, 0x0E, 0x15,
+  0x00, 0x01, 0xFA, 0xB0, 0x13, 0xE6, 0x20, 0xB0, 0x08, 0xE6, 0x21,
+  0xB0, 0x09, 0xE6, 0x21, 0xB0, 0xFF, 0xE6, 0x21, 0x1E, 0x33, 0xC0,
+  0x8E, 0xC0, 0x0E, 0x1F, 0xB9, 0x08, 0x00, 0x33, 0xFF, 0xB8, 0x23,
+  0xFF, 0xAB, 0x8C, 0xC8, 0xAB, 0xE2, 0xF7, 0xBE, 0xF3, 0xFE, 0xB9,
+  0x18, 0x00, 0xA5, 0x8C, 0xC8, 0xAB, 0xE2, 0xFA, 0xB8, 0x00, 0xF6,
+  0x8E, 0xD8, 0x33, 0xDB, 0xB4, 0x04, 0x8B, 0xEC, 0x0E, 0xBA, 0x88,
+  0xE1, 0x52, 0xBA, 0x90, 0xEA, 0x52, 0xBA, 0x8B, 0x17, 0x52, 0x16,
+  0x8B, 0xD4, 0x83, 0xC2, 0x02, 0x52, 0xCB, 0x8B, 0xE5, 0x3A, 0xD6,
+  0x74, 0x0C, 0x1F, 0xBF, 0x60, 0x00, 0x33, 0xC0, 0xAB, 0xB8, 0x00,
+  0xF6, 0xAB, 0x1E, 0x1F, 0x26, 0xC7, 0x06, 0x08, 0x00, 0x5F, 0xF8,
+  0x26, 0xC7, 0x06, 0x14, 0x00, 0x54, 0xFF, 0x26, 0xC7, 0x06, 0x7C,
+  0x00, 0x00, 0x00, 0x26, 0xC7, 0x06, 0x7E, 0x00, 0x00, 0x00, 0xBA,
+  0x61, 0x00, 0xEC, 0x0C, 0x30, 0xEE, 0x24, 0xCF, 0xEE, 0xB0, 0x80,
+  0xE6, 0xA0, 0xB8, 0x30, 0x00, 0xA3, 0x10, 0x00, 0xCD, 0x10, 0xB8,
+  0x20, 0x00, 0xA3, 0x10, 0x00, 0xCD, 0x10, 0xE4, 0x62, 0x24, 0x0F,
+  0x8A, 0xE0, 0xB0, 0xAD, 0xEE, 0xE4, 0x62, 0xB1, 0x04, 0xD2, 0xE0,
+  0x0A, 0xC4, 0xB4, 0x00, 0xA3, 0x10, 0x00, 0x24, 0x30, 0x75, 0x09,
+  0xB8, 0x53, 0xFF, 0x26, 0xA3, 0x40, 0x00, 0xEB, 0x03, 0xE8, 0xCC,
+  0x17, 0xB0, 0x08, 0xEE, 0xB9, 0x56, 0x29, 0xE2, 0xFE, 0xB0, 0xC8,
+  0xEE, 0x34, 0x80, 0xEE, 0xB8, 0x1E, 0x00, 0xA3, 0x1A, 0x00, 0xA3,
+  0x1C, 0x00, 0xA3, 0x80, 0x00, 0x05, 0x20, 0x00, 0xA3, 0x82, 0x00,
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+  0x05, 0xF8, 0x03, 0x47, 0x47, 0xBA, 0xFB, 0x02, 0xB0, 0x1A, 0xEE,
+  0xB0, 0xFF, 0xE6, 0xC0, 0xEC, 0x3C, 0x1A, 0x75, 0x06, 0xC7, 0x05,
+  0xF8, 0x02, 0x47, 0x47, 0x8B, 0xC7, 0x08, 0x06, 0x11, 0x00, 0xB9,
+  0x64, 0x00, 0xBA, 0x01, 0x02, 0xEC, 0x3C, 0xFF, 0x75, 0x05, 0x49,
+  0xE3, 0x07, 0xEB, 0xF6, 0x80, 0x0E, 0x11, 0x00, 0x10, 0xE8, 0x65,
+  0x04, 0xBA, 0x00, 0xC0, 0x8B, 0x1E, 0x72, 0x00, 0x53, 0x1E, 0xE4,
+  0x61, 0x34, 0x0C, 0xE6, 0x61, 0x8E, 0xDA, 0xEB, 0x13, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xE9, 0x99, 0x15, 0x33, 0xDB, 0x8B, 0x07, 0x3D,
+  0x55, 0xAA, 0x75, 0x36, 0xB8, 0x40, 0x00, 0x8E, 0xC0, 0xB4, 0x00,
+  0x8A, 0x47, 0x02, 0xB1, 0x05, 0xD3, 0xE0, 0x03, 0xD0, 0xB1, 0x04,
+  0xD3, 0xE0, 0x8B, 0xC8, 0xE8, 0x27, 0x17, 0x75, 0x15, 0x52, 0x26,
+  0xC7, 0x06, 0x67, 0x00, 0x03, 0x00, 0x26, 0x8C, 0x1E, 0x69, 0x00,
+  0x26, 0xFF, 0x1E, 0x67, 0x00, 0x5A, 0xEB, 0x0A, 0x26, 0x80, 0x0E,
+  0x15, 0x00, 0x20, 0x81, 0xC2, 0x80, 0x00, 0x81, 0xFA, 0x00, 0xF6,
+  0x7C, 0xA0, 0x1F, 0x5B, 0x89, 0x1E, 0x72, 0x00, 0xE4, 0x21, 0x24,
+  0xBC, 0xE6, 0x21, 0xB4, 0x12, 0xBB, 0x10, 0xFF, 0xCD, 0x10, 0x80,
+  0xFF, 0xFF, 0x74, 0x07, 0x80, 0x26, 0x10, 0x00, 0xCF, 0xEB, 0x09,
+  0xA0, 0x49, 0x00, 0xE8, 0xDF, 0x0B, 0xE8, 0x90, 0x16, 0xB4, 0x01,
+  0xB5, 0xF0, 0xCD, 0x10, 0xE8, 0xDB, 0x01, 0xC6, 0x06, 0x96, 0x00,
+  0x10, 0x81, 0x3E, 0x72, 0x00, 0x34, 0x12, 0x1E, 0x07, 0x0E, 0x1F,
+  0x75, 0x05, 0xB7, 0xFD, 0xE9, 0x28, 0x01, 0xBE, 0x00, 0xE0, 0xE8,
+  0x3E, 0x16, 0xBE, 0x5C, 0xE5, 0xE8, 0x20, 0x16, 0x26, 0xF6, 0x06,
+  0x15, 0x00, 0xFF, 0x74, 0x3E, 0xB8, 0x00, 0x03, 0xE8, 0x1D, 0x16,
+  0xBE, 0xF9, 0xE7, 0xE8, 0x0C, 0x16, 0x26, 0xA0, 0x15, 0x00, 0xE8,
+  0xE2, 0x15, 0xBE, 0x42, 0xF9, 0xE8, 0xFF, 0x15, 0xB3, 0x02, 0xE8,
+  0x60, 0x16, 0xE8, 0x58, 0x16, 0x50, 0xE8, 0xE8, 0x15, 0x58, 0x3C,
+  0x59, 0x74, 0x09, 0x3C, 0x79, 0x74, 0x05, 0xEA, 0x5B, 0xE0, 0x00,
+  0xF0, 0x26, 0xC6, 0x06, 0x15, 0x00, 0x00, 0xE8, 0x75, 0x01, 0xEB,
+  0xAE, 0xB8, 0x00, 0x03, 0xE8, 0xDF, 0x15, 0xE8, 0x84, 0x01, 0xBE,
+  0xB1, 0xE5, 0xB8, 0x07, 0x04, 0xE8, 0xD3, 0x15, 0x26, 0xA0, 0x49,
+  0x00, 0x3C, 0x07, 0x74, 0x10, 0x26, 0xA0, 0x10, 0x00, 0x24, 0x30,
+  0x75, 0x05, 0xBE, 0x20, 0xE0, 0xEB, 0x03, 0xBE, 0x36, 0xF0, 0xE8,
+  0xAD, 0x15, 0xBB, 0x07, 0x05, 0x26, 0xA0, 0x11, 0x00, 0x50, 0xB1,
+  0x06, 0xD2, 0xC8, 0x24, 0x03, 0x74, 0x09, 0xBD, 0x08, 0x00, 0xBE,
+  0x33, 0xE0, 0xE8, 0xC9, 0x00, 0x58, 0x50, 0xBE, 0x19, 0xF9, 0xD0,
+  0xC8, 0x24, 0x03, 0x74, 0x05, 0x33, 0xED, 0xE8, 0xB9, 0x00, 0x58,
+  0xBE, 0x47, 0xE0, 0xA8, 0x10, 0x74, 0x0A, 0x8B, 0xC3, 0xE8, 0x82,
+  0x15, 0xE8, 0x74, 0x15, 0xFE, 0xC7, 0xE8, 0xF0, 0x00, 0x72, 0x0D,
+  0x8B, 0xC3, 0xE8, 0x73, 0x15, 0xFE, 0xC7, 0xBE, 0xC2, 0xFF, 0xE8,
+  0x60, 0x15, 0xFE, 0xCF, 0xB3, 0x07, 0x8B, 0xC3, 0xE8, 0x62, 0x15,
+  0xBE, 0xA2, 0xF0, 0xE8, 0x51, 0x15, 0xFE, 0xC7, 0xFE, 0xC7, 0x32,
+  0xDB, 0x8B, 0xC3, 0xE8, 0x51, 0x15, 0xBE, 0x9C, 0xE5, 0xE8, 0x40,
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+  0x00, 0x8B, 0xD6, 0xB8, 0x80, 0x00, 0x8E, 0xC0, 0x80, 0xC3, 0x0D,
+  0x53, 0x58, 0x50, 0x8C, 0xC1, 0x83, 0xFD, 0x01, 0x74, 0x09, 0xF7,
+  0xC1, 0xFF, 0x01, 0x74, 0x02, 0x32, 0xED, 0x4A, 0xE8, 0x20, 0x15,
+  0xE8, 0x69, 0x00, 0x42, 0xE8, 0xA5, 0x15, 0x72, 0x2D, 0x4D, 0x75,
+  0xDF, 0x5B, 0x07, 0xE8, 0x13, 0x13, 0xB3, 0x01, 0xE8, 0x65, 0x15,
+  0xE8, 0x95, 0x00, 0x33, 0xC0, 0x8E, 0xD8, 0xC7, 0x06, 0x72, 0x04,
+  0x34, 0x12, 0xB4, 0x01, 0xB9, 0x0C, 0x0B, 0x80, 0x3E, 0x49, 0x04,
+  0x07, 0x74, 0x03, 0xB9, 0x07, 0x06, 0xCD, 0x10, 0xCD, 0x19, 0x4D,
+  0x5B, 0x07, 0x26, 0x80, 0x0E, 0x15, 0x00, 0x02, 0xFE, 0xC7, 0xFE,
+  0xC7, 0x32, 0xDB, 0x8B, 0xC3, 0xE9, 0xB6, 0xFE, 0x8A, 0xD0, 0x8B,
+  0xC3, 0xE8, 0xCF, 0x14, 0x56, 0xE8, 0xC0, 0x14, 0x26, 0x8B, 0x46,
+  0x00, 0xE8, 0xA3, 0x14, 0xBE, 0x4E, 0xFF, 0xE8, 0xB3, 0x14, 0x5E,
+  0x45, 0x45, 0xFE, 0xC7, 0xFE, 0xCA, 0x75, 0xE1, 0xC3, 0xF8, 0x8A,
+  0xC2, 0xFE, 0xC0, 0x27, 0x8A, 0xD0, 0x73, 0x07, 0x8A, 0xC6, 0x14,
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+  0x00, 0xF6, 0x75, 0xE4, 0xCD, 0x18, 0x3C, 0xE0, 0x75, 0x10, 0x80,
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+  0x51, 0xF6, 0xC3, 0x02, 0x74, 0x47, 0x80, 0xE3, 0xFD, 0x3C, 0xAA,
+  0x75, 0x06, 0x8A, 0xC7, 0x0C, 0x80, 0x8A, 0xE0, 0x8A, 0xF8, 0x8A,
+  0xC8, 0x80, 0xE1, 0x7F, 0x80, 0xF9, 0x2A, 0x74, 0xCD, 0x80, 0xF9,
+  0x36, 0x74, 0xC8, 0x3C, 0x35, 0x74, 0x25, 0x3C, 0x1C, 0x74, 0x21,
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+  0x15, 0xE8, 0x88, 0x08, 0xE8, 0xFA, 0x04, 0x72, 0x0D, 0xB0, 0xE0,
+  0x59, 0x50, 0x55, 0x8B, 0xEC, 0xC7, 0x46, 0x02, 0xA4, 0xEB, 0x5D,
+  0x89, 0x1E, 0x96, 0x00, 0xC3, 0x80, 0xC4, 0x2E, 0xA0, 0x17, 0x00,
+  0xA8, 0x08, 0x75, 0x0A, 0xA8, 0x04, 0x75, 0x09, 0xA8, 0x03, 0x75,
+  0x08, 0xEB, 0x09, 0x80, 0xC4, 0x02, 0x80, 0xC4, 0x02, 0x80, 0xC4,
+  0x02, 0x32, 0xC0, 0xEB, 0xCF, 0xFF, 0xFF, 0xE9, 0x0B, 0xFF, 0x32,
+  0xC0, 0xB0, 0x40, 0xF6, 0xE0, 0x74, 0x04, 0xBE, 0xEB, 0xF7, 0xC3,
+  0xBE, 0xF6, 0xF7, 0xC3, 0xDB, 0xE3, 0xBE, 0x00, 0x02, 0xC6, 0x44,
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+  0x06, 0x80, 0x0E, 0x10, 0x00, 0x02, 0xC3, 0x80, 0x26, 0x10, 0x00,
+  0xFD, 0xC3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x17, 0x04, 0x00, 0x03,
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+  0x00, 0xFB, 0x1E, 0x52, 0x56, 0x57, 0x51, 0x53, 0xBB, 0x40, 0x00,
+  0x8E, 0xDB, 0x8B, 0xFA, 0x8B, 0xDA, 0xD1, 0xE3, 0x8B, 0x17, 0x0B,
+  0xD2, 0x74, 0x10, 0x0A, 0xE4, 0x74, 0x13, 0xFE, 0xCC, 0x74, 0x3A,
+  0xFE, 0xCC, 0x74, 0x53, 0xFE, 0xCC, 0x74, 0x63, 0x5B, 0x59, 0x5F,
+  0x5E, 0x5A, 0x1F, 0xCF, 0x50, 0x8A, 0xD8, 0x83, 0xC2, 0x03, 0xB0,
+  0x80, 0xEE, 0xB1, 0x04, 0xD2, 0xC3, 0x83, 0xE3, 0x0E, 0x2E, 0x8B,
+  0x87, 0x29, 0xE7, 0x83, 0xEA, 0x03, 0xEE, 0x42, 0x8A, 0xC4, 0xEE,
+  0x58, 0x42, 0x42, 0x24, 0x1F, 0xEE, 0xB0, 0x00, 0x4A, 0x4A, 0xEE,
+  0x4A, 0xEB, 0x31, 0x50, 0xB0, 0x03, 0xB7, 0x30, 0xB3, 0x20, 0xE8,
+  0x48, 0x00, 0x75, 0x09, 0x83, 0xEA, 0x05, 0x59, 0x8A, 0xC1, 0xEE,
+  0xEB, 0xB9, 0x59, 0x8A, 0xC1, 0x80, 0xCC, 0x80, 0xEB, 0xB1, 0xB0,
+  0x01, 0xB7, 0x20, 0xB3, 0x01, 0xE8, 0x2C, 0x00, 0x75, 0xF0, 0x80,
+  0xE4, 0x1E, 0x83, 0xEA, 0x05, 0xEC, 0xEB, 0x9D, 0x83, 0xC2, 0x05,
+  0xEC, 0x8A, 0xE0, 0x42, 0xEC, 0xEB, 0x93, 0x8A, 0x5D, 0x7C, 0x2B,
+  0xC9, 0xEC, 0x8A, 0xE0, 0x22, 0xC7, 0x3A, 0xC7, 0x74, 0x08, 0xE2,
+  0xF5, 0xFE, 0xCB, 0x75, 0xEF, 0x0A, 0xFF, 0xC3, 0x83, 0xC2, 0x04,
+  0xEE, 0x42, 0x42, 0x53, 0xE8, 0xDF, 0xFF, 0x5B, 0x75, 0x06, 0x4A,
+  0x8A, 0xFB, 0xE8, 0xD6, 0xFF, 0xC3, 0x53, 0x79, 0x73, 0x74, 0x65,
+  0x6D, 0x20, 0x45, 0x72, 0x72, 0x6F, 0x72, 0x3A, 0x20, 0x00, 0xFA,
+  0x8B, 0x1E, 0x1A, 0x00, 0x3B, 0x1E, 0x1C, 0x00, 0x8B, 0x07, 0xFB,
+  0x5B, 0x1F, 0xCA, 0x02, 0x00, 0xA1, 0x17, 0x00, 0xEB, 0x2E, 0x8B,
+  0xC1, 0xE8, 0xBA, 0x03, 0xB0, 0x00, 0x73, 0x25, 0xFE, 0xC0, 0xEB,
+  0x21, 0xFF, 0xFF, 0xFF, 0xFB, 0x1E, 0x53, 0xBB, 0x40, 0x00, 0x8E,
+  0xDB, 0x80, 0xFC, 0x05, 0x74, 0xE3, 0x8B, 0xD8, 0x80, 0xE4, 0x0F,
+  0x0A, 0xE4, 0x74, 0x0B, 0xFE, 0xCC, 0x74, 0xC0, 0xFE, 0xCC, 0x74,
+  0xCD, 0x5B, 0x1F, 0xCF, 0xFA, 0xA1, 0x1A, 0x00, 0x3B, 0x06, 0x1C,
+  0x00, 0x75, 0x03, 0xFB, 0xEB, 0xF3, 0xF6, 0xC7, 0x10, 0x9C, 0x93,
+  0x8B, 0x07, 0x9D, 0x75, 0x06, 0x3C, 0xE0, 0x75, 0x02, 0x32, 0xC0,
+  0x43, 0x43, 0x89, 0x1E, 0x1A, 0x00, 0x3B, 0x1E, 0x82, 0x00, 0x75,
+  0xD4, 0x8B, 0x1E, 0x80, 0x00, 0x89, 0x1E, 0x1A, 0x00, 0xEB, 0xCA,
+  0xFF, 0xFF, 0xFF, 0x00, 0x37, 0x2E, 0x20, 0x2F, 0x30, 0x31, 0x21,
+  0x32, 0x33, 0x34, 0x35, 0x22, 0x36, 0x38, 0x3E, 0x11, 0x17, 0x05,
+  0x12, 0x14, 0x19, 0x15, 0x09, 0x0F, 0x10, 0x39, 0x3A, 0x3B, 0x84,
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+  0x41, 0x82, 0x3C, 0x1A, 0x18, 0x03, 0x16, 0x02, 0x0E, 0x0D, 0x42,
+  0x43, 0x44, 0x81, 0x3D, 0x88, 0x2D, 0xC0, 0x23, 0x24, 0x25, 0x26,
+  0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0xA0, 0x90, 0x32, 0x36, 0x2D,
+  0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0x20,
+  0x31, 0x33, 0x34, 0x35, 0x37, 0x38, 0x39, 0x30, 0x3D, 0x1B, 0x08,
+  0x5B, 0x5D, 0x0D, 0x5C, 0x2A, 0x09, 0x3B, 0x27, 0x60, 0x2C, 0x2E,
+  0x2F, 0x40, 0x5E, 0x5F, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA,
+  0xDB, 0xDC, 0xDD, 0x20, 0x21, 0x23, 0x24, 0x25, 0x26, 0x2A, 0x28,
+  0x29, 0x2B, 0x1B, 0x08, 0x7B, 0x7D, 0x0D, 0x7C, 0x05, 0x8F, 0x3A,
+  0x22, 0x7E, 0x3C, 0x3E, 0x3F, 0x03, 0x1E, 0x1F, 0xDE, 0xDF, 0xE0,
+  0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0x20, 0x05, 0x05, 0x05,
+  0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x1B, 0x7F, 0x1B, 0x1D, 0x0A,
+  0x1C, 0xF2, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0xF9, 0xFD,
+  0x02, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1,
+  0x20, 0xF8, 0xFA, 0xFB, 0xFC, 0xFE, 0xFF, 0x00, 0x01, 0x03, 0x05,
+  0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
+  0x05, 0x05, 0x37, 0x38, 0x39, 0x2D, 0x34, 0x35, 0x36, 0x2B, 0x31,
+  0x32, 0x33, 0x30, 0x2E, 0xF7, 0x05, 0x04, 0x05, 0xF3, 0x05, 0xF4,
+  0x05, 0xF5, 0x05, 0xF6, 0x05, 0x05, 0xC7, 0xC8, 0xC9, 0x2D, 0xCB,
+  0x05, 0xCD, 0x2B, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xFB, 0x50, 0x53,
+  0x51, 0x52, 0x56, 0x57, 0x1E, 0xFC, 0xB8, 0x40, 0x00, 0x8E, 0xD8,
+  0xE4, 0x60, 0x50, 0xE4, 0x61, 0x50, 0x0C, 0x80, 0xE6, 0x61, 0x58,
+  0xE6, 0x61, 0x58, 0x8A, 0xE0, 0x8B, 0x1E, 0x96, 0x00, 0xE8, 0xB6,
+  0xFC, 0x3C, 0xFF, 0x75, 0x0F, 0xE9, 0xF6, 0x01, 0xB0, 0x20, 0xE6,
+  0x20, 0x1F, 0x5F, 0x5E, 0x5A, 0x59, 0x5B, 0x58, 0xCF, 0x24, 0x7F,
+  0x3C, 0x46, 0x76, 0x03, 0xE9, 0x22, 0x01, 0xBB, 0x85, 0xE8, 0x2E,
+  0xD7, 0x0A, 0xC0, 0x78, 0x06, 0x0A, 0xE4, 0x78, 0xDE, 0xEB, 0x4D,
+  0x24, 0x7F, 0x0A, 0xE4, 0x78, 0x21, 0x3C, 0x10, 0x73, 0x06, 0x08,
+  0x06, 0x17, 0x00, 0xEB, 0xCC, 0xF6, 0x06, 0x17, 0x00, 0x04, 0x75,
+  0x36, 0x84, 0x06, 0x18, 0x00, 0x75, 0xBF, 0x08, 0x06, 0x18, 0x00,
+  0x30, 0x06, 0x17, 0x00, 0xEB, 0xB5, 0x3C, 0x10, 0x73, 0x1A, 0xF6,
+  0xD0, 0x20, 0x06, 0x17, 0x00, 0x3C, 0xF7, 0x75, 0xA7, 0xA0, 0x19,
+  0x00, 0xB4, 0x00, 0x88, 0x26, 0x19, 0x00, 0x3A, 0xC4, 0x74, 0x9A,
+  0xE9, 0x95, 0x01, 0xF6, 0xD0, 0x20, 0x06, 0x18, 0x00, 0xEB, 0x8F,
+  0xF6, 0x06, 0x18, 0x00, 0x08, 0x74, 0x0D, 0x80, 0xFC, 0x45, 0x74,
+  0x05, 0x80, 0x26, 0x18, 0x00, 0xF7, 0xE9, 0x7B, 0xFF, 0x8A, 0x16,
+  0x17, 0x00, 0xF6, 0xC2, 0x08, 0x75, 0x1D, 0xF6, 0xC2, 0x04, 0x75,
+  0x2B, 0xF6, 0xC2, 0x03, 0x75, 0x7E, 0x3C, 0x1A, 0x77, 0x05, 0x04,
+  0x60, 0xE9, 0x16, 0x01, 0xBB, 0xCC, 0xE8, 0x2C, 0x20, 0x2E, 0xD7,
+  0xE9, 0x0C, 0x01, 0x3C, 0x1A, 0x77, 0x05, 0xB0, 0x00, 0xE9, 0x3D,
+  0x01, 0xBB, 0x3B, 0xE9, 0x2C, 0x20, 0x2E, 0xD7, 0xE9, 0xF9, 0x00,
+  0x80, 0xFC, 0x46, 0x75, 0x15, 0xC6, 0x06, 0x71, 0x00, 0x80, 0xA1,
+  0x80, 0x00, 0xA3, 0x1C, 0x00, 0xA3, 0x1A, 0x00, 0xCD, 0x1B, 0x2B,
+  0xC0, 0xE9, 0xF1, 0x00, 0x80, 0xFC, 0x45, 0x75, 0x21, 0x80, 0x0E,
+  0x18, 0x00, 0x08, 0xB0, 0x20, 0xE6, 0x20, 0x80, 0x3E, 0x49, 0x00,
+  0x07, 0x74, 0x07, 0xBA, 0xD8, 0x03, 0xA0, 0x65, 0x00, 0xEE, 0xF6,
+  0x06, 0x18, 0x00, 0x08, 0x75, 0xF9, 0xE9, 0x06, 0xFF, 0x80, 0xFC,
+  0x03, 0x75, 0x05, 0xB0, 0x00, 0xE9, 0xE9, 0x00, 0x3C, 0x1A, 0x76,
+  0xF9, 0xBB, 0x16, 0xE9, 0x2C, 0x20, 0x2E, 0xD7, 0xE9, 0xA1, 0x00,
+  0x80, 0xFC, 0x37, 0x75, 0x09, 0xB0, 0x20, 0xE6, 0x20, 0xCD, 0x05,
+  0xE9, 0xE0, 0xFE, 0x3C, 0x1A, 0x77, 0x05, 0x04, 0x40, 0xE9, 0x8A,
+  0x00, 0xBB, 0xF1, 0xE8, 0x2C, 0x20, 0x2E, 0xD7, 0xE9, 0x80, 0x00,
+  0x2C, 0x47, 0x8A, 0x1E, 0x17, 0x00, 0xF6, 0xC3, 0x08, 0x75, 0x18,
+  0xF6, 0xC3, 0x04, 0x75, 0x50, 0xF6, 0xC3, 0x20, 0x74, 0x07, 0xF6,
+  0xC3, 0x03, 0x75, 0x51, 0xEB, 0x5B, 0xF6, 0xC3, 0x03, 0x74, 0x4A,
+  0xEB, 0x54, 0x0A, 0xE4, 0x78, 0x36, 0xF6, 0x06, 0x17, 0x00, 0x04,
+  0x74, 0x16, 0x80, 0xFC, 0x53, 0x75, 0x09, 0xC7, 0x06, 0x72, 0x00,
+  0x34, 0x12, 0xE9, 0x40, 0xF5, 0x80, 0xFC, 0x4A, 0x75, 0x03, 0xE8,
+  0xD1, 0x00, 0xBB, 0x60, 0xE9, 0x2E, 0xD7, 0x3C, 0x30, 0x72, 0x10,
+  0x2C, 0x30, 0x8A, 0xD8, 0xA0, 0x19, 0x00, 0xB4, 0x0A, 0xF6, 0xE4,
+  0x02, 0xC3, 0xA2, 0x19, 0x00, 0xE9, 0x69, 0xFE, 0x0A, 0xE4, 0x78,
+  0xF9, 0xBB, 0x6D, 0xE9, 0x2E, 0xD7, 0xEB, 0x15, 0xE8, 0x5D, 0x00,
+  0x72, 0xED, 0xBB, 0x7A, 0xE9, 0x2E, 0xD7, 0xEB, 0x09, 0x0A, 0xE4,
+  0x78, 0xE2, 0xBB, 0x60, 0xE9, 0x2E, 0xD7, 0x3C, 0x05, 0x74, 0x40,
+  0x3C, 0x04, 0x77, 0x04, 0x0C, 0x80, 0xEB, 0x06, 0xA8, 0x80, 0x74,
+  0x06, 0x24, 0x7F, 0x8A, 0xE0, 0xB0, 0x00, 0xF6, 0x06, 0x17, 0x00,
+  0x40, 0x74, 0x1D, 0xF6, 0x06, 0x17, 0x00, 0x03, 0x74, 0x0C, 0x3C,
+  0x41, 0x72, 0x12, 0x3C, 0x5A, 0x77, 0x0E, 0x04, 0x20, 0xEB, 0x0A,
+  0x3C, 0x61, 0x72, 0x06, 0x3C, 0x7A, 0x77, 0x02, 0x2C, 0x20, 0xE8,
+  0x36, 0x00, 0x73, 0x05, 0xB3, 0x01, 0xE8, 0x3A, 0x0E, 0xE9, 0x02,
+  0xFE, 0xB4, 0x38, 0xEB, 0xEF, 0x80, 0xFC, 0xD2, 0x75, 0x07, 0x80,
+  0x26, 0x18, 0x00, 0x7F, 0xF9, 0xC3, 0x0A, 0xE4, 0x78, 0xFA, 0x80,
+  0xFC, 0x52, 0x75, 0x11, 0xF6, 0x06, 0x18, 0x00, 0x80, 0x75, 0x0A,
+  0x80, 0x36, 0x17, 0x00, 0x80, 0x80, 0x0E, 0x18, 0x00, 0x80, 0xF8,
+  0xC3, 0x8B, 0x1E, 0x1C, 0x00, 0x8B, 0xFB, 0x43, 0x43, 0x3B, 0x1E,
+  0x82, 0x00, 0x75, 0x04, 0x8B, 0x1E, 0x80, 0x00, 0x3B, 0x1E, 0x1A,
+  0x00, 0x75, 0x02, 0xF9, 0xC3, 0x89, 0x05, 0x89, 0x1E, 0x1C, 0x00,
+  0xF8, 0xC3, 0x50, 0x53, 0x51, 0xE4, 0x61, 0x34, 0x0C, 0xE6, 0x61,
+  0xBB, 0x89, 0x0F, 0x24, 0x04, 0x74, 0x03, 0xBB, 0x2E, 0x05, 0xB0,
+  0xB6, 0xE6, 0x43, 0x8B, 0xC3, 0xE6, 0x42, 0x8A, 0xC4, 0xE6, 0x42,
+  0xE4, 0x61, 0x50, 0x0C, 0x03, 0xE6, 0x61, 0xB9, 0x00, 0x20, 0xE2,
+  0xFE, 0x58, 0xE6, 0x61, 0x59, 0x5B, 0x58, 0xC3, 0x4E, 0x6F, 0x20,
+  0x52, 0x4F, 0x4D, 0x20, 0x42, 0x41, 0x53, 0x49, 0x43, 0x2C, 0x20,
+  0x62, 0x6F, 0x6F, 0x74, 0x69, 0x6E, 0x67, 0x20, 0x66, 0x72, 0x6F,
+  0x6D, 0x20, 0x64, 0x69, 0x73, 0x6B, 0x2E, 0x2E, 0x2E, 0x00, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0x55, 0x56, 0x57, 0x1E, 0x06, 0x53,
+  0x8B, 0xF8, 0x33, 0xC0, 0x8E, 0xD8, 0xC4, 0x36, 0x78, 0x00, 0xB8,
+  0x40, 0x00, 0x8E, 0xD8, 0xBB, 0x05, 0x00, 0x26, 0x8B, 0x00, 0x50,
+  0x4B, 0x4B, 0x26, 0x8B, 0x00, 0x50, 0x86, 0xCE, 0x86, 0xD1, 0x52,
+  0x51, 0x57, 0x8B, 0xEC, 0xE8, 0x22, 0x00, 0x26, 0x8A, 0x64, 0x02,
+  0x88, 0x26, 0x40, 0x00, 0x8A, 0x26, 0x41, 0x00, 0x80, 0xFC, 0x01,
+  0xF5, 0x5B, 0x59, 0x5A, 0x86, 0xD1, 0x86, 0xCE, 0x5B, 0x5B, 0x5B,
+  0x07, 0x1F, 0x5F, 0x5E, 0x5D, 0xCA, 0x02, 0x00, 0x8A, 0x46, 0x01,
+  0x0A, 0xC0, 0x74, 0x1B, 0xFE, 0xC8, 0x74, 0x13, 0x80, 0x7E, 0x02,
+  0x03, 0x77, 0x04, 0x3C, 0x05, 0x76, 0x06, 0xC6, 0x06, 0x41, 0x00,
+  0x01, 0xC3, 0xE9, 0x81, 0x00, 0xA0, 0x41, 0x00, 0xC3, 0xBA, 0xF2,
+  0x03, 0xFA, 0x80, 0x26, 0x3F, 0x00, 0x0F, 0xA0, 0x3F, 0x00, 0xB1,
+  0x04, 0xD2, 0xE0, 0xA8, 0x20, 0x75, 0x0C, 0xA8, 0x40, 0x75, 0x06,
+  0xA8, 0x80, 0x74, 0x06, 0xFE, 0xC0, 0xFE, 0xC0, 0xFE, 0xC0, 0xC6,
+  0x06, 0x3E, 0x00, 0x00, 0xC6, 0x06, 0x41, 0x00, 0x00, 0x0C, 0x08,
+  0xEE, 0x0C, 0x04, 0xEE, 0xFB, 0xE8, 0xB3, 0x01, 0xE8, 0x66, 0x02,
+  0xA0, 0x42, 0x00, 0x3C, 0xC0, 0x74, 0x07, 0xC6, 0x06, 0x41, 0x00,
+  0x20, 0xEB, 0x12, 0xB0, 0x03, 0xE8, 0x7B, 0x02, 0x26, 0x8A, 0x04,
+  0xE8, 0x75, 0x02, 0x26, 0x8A, 0x44, 0x01, 0xE8, 0x6E, 0x02, 0xC3,
+  0x03, 0x00, 0xE6, 0xC5, 0xE6, 0x4D, 0x00, 0x00, 0x46, 0x4A, 0x42,
+  0x4A, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x01, 0x02, 0x04, 0x08,
+  0x80, 0x20, 0x10, 0x04, 0x02, 0x01, 0x04, 0x10, 0x08, 0x04, 0x03,
+  0x02, 0x20, 0xFA, 0xC6, 0x06, 0x41, 0x00, 0x00, 0x8A, 0x46, 0x01,
+  0xB4, 0x00, 0x8B, 0xF8, 0xE6, 0x0C, 0x2E, 0x8A, 0x85, 0x2C, 0xED,
+  0xE6, 0x0B, 0x8B, 0x46, 0x0C, 0xB1, 0x04, 0xD3, 0xC0, 0x8A, 0xE8,
+  0x80, 0xE5, 0x0F, 0x24, 0xF0, 0x03, 0x46, 0x0A, 0x80, 0xD5, 0x00,
+  0x8B, 0xD0, 0xE6, 0x04, 0x8A, 0xC4, 0xE6, 0x04, 0x8A, 0xC5, 0xE6,
+  0x81, 0x8A, 0x66, 0x00, 0xB0, 0x00, 0xD1, 0xE8, 0x8A, 0x4E, 0x06,
+  0xD3, 0xE0, 0x48, 0xE6, 0x05, 0x86, 0xC4, 0xE6, 0x05, 0x86, 0xC4,
+  0x03, 0xC2, 0x73, 0x09, 0xFB, 0xC6, 0x06, 0x41, 0x00, 0x09, 0xE9,
+  0x11, 0x01, 0xB0, 0x02, 0xE6, 0x0A, 0xC6, 0x06, 0x40, 0x00, 0xFF,
+  0x8A, 0x5E, 0x02, 0xB7, 0x00, 0x2E, 0x8A, 0x87, 0x38, 0xED, 0x8A,
+  0xE8, 0xB1, 0x04, 0xD2, 0xE0, 0x0A, 0xC3, 0x0C, 0x0C, 0xBA, 0xF2,
+  0x03, 0xEE, 0xFB, 0x2E, 0x8A, 0x85, 0x32, 0xED, 0x08, 0x06, 0x3F,
+  0x00, 0x0A, 0xC0, 0x79, 0x11, 0x26, 0x8A, 0x64, 0x0A, 0x0A, 0xE4,
+  0x74, 0x09, 0x84, 0x2E, 0x3F, 0x00, 0x75, 0x03, 0xE8, 0x27, 0x01,
+  0x08, 0x2E, 0x3F, 0x00, 0x84, 0x2E, 0x3E, 0x00, 0x75, 0x14, 0x08,
+  0x2E, 0x3E, 0x00, 0xB0, 0x07, 0xE8, 0x9F, 0x01, 0x8A, 0xC3, 0xE8,
+  0x9A, 0x01, 0xE8, 0xB9, 0x00, 0xE8, 0xBB, 0x01, 0xB0, 0x0F, 0xE8,
+  0x8F, 0x01, 0x8A, 0xC3, 0xE8, 0x8A, 0x01, 0x8A, 0x46, 0x03, 0xE8,
+  0x84, 0x01, 0xE8, 0xA3, 0x00, 0xE8, 0x56, 0x01, 0x26, 0x8A, 0x44,
+  0x09, 0x0A, 0xC0, 0x74, 0x09, 0xB9, 0x26, 0x02, 0xE2, 0xFE, 0xFE,
+  0xC8, 0x75, 0xF7, 0x2E, 0x8A, 0x85, 0x26, 0xED, 0xE8, 0x65, 0x01,
+  0x8A, 0x46, 0x04, 0x24, 0x01, 0xD0, 0xE0, 0xD0, 0xE0, 0x0A, 0xC3,
+  0xE8, 0x57, 0x01, 0x80, 0x7E, 0x01, 0x05, 0x75, 0x1C, 0x8A, 0x46,
+  0x06, 0xE8, 0x4B, 0x01, 0x8A, 0x46, 0x07, 0xE8, 0x45, 0x01, 0x26,
+  0x8A, 0x44, 0x07, 0xE8, 0x3E, 0x01, 0x26, 0x8A, 0x44, 0x08, 0xE8,
+  0x37, 0x01, 0xEB, 0x0E, 0xB9, 0x07, 0x00, 0xBF, 0x03, 0x00, 0x8A,
+  0x03, 0xE8, 0x2A, 0x01, 0x47, 0xE2, 0xF8, 0xE8, 0x46, 0x00, 0xE8,
+  0xFE, 0x00, 0xA0, 0x42, 0x00, 0x24, 0xC0, 0x74, 0x25, 0x3C, 0x40,
+  0x74, 0x07, 0xC6, 0x06, 0x41, 0x00, 0x20, 0xEB, 0x1A, 0xA0, 0x43,
+  0x00, 0xB9, 0x06, 0x00, 0x33, 0xDB, 0x2E, 0x84, 0x87, 0x3C, 0xED,
+  0x75, 0x03, 0x43, 0xE2, 0xF6, 0x2E, 0x8A, 0x87, 0x42, 0xED, 0xA2,
+  0x41, 0x00, 0xA0, 0x45, 0x00, 0x3A, 0x46, 0x03, 0xA0, 0x47, 0x00,
+  0x74, 0x05, 0x8A, 0x46, 0x07, 0xFE, 0xC0, 0x2A, 0x46, 0x05, 0xC3,
+  0xB0, 0x00, 0xC3, 0xFB, 0x33, 0xC9, 0xB0, 0x02, 0xF6, 0x06, 0x3E,
+  0x00, 0x80, 0xF8, 0x75, 0x10, 0xE2, 0xF6, 0xFE, 0xC8, 0x75, 0xF2,
+  0xC6, 0x06, 0x41, 0x00, 0x80, 0x58, 0xB0, 0x00, 0xF9, 0xC3, 0x80,
+  0x26, 0x3E, 0x00, 0x7F, 0xC3, 0x51, 0x33, 0xC9, 0xBA, 0xF4, 0x03,
+  0xEC, 0x0A, 0xC0, 0x78, 0x09, 0xE2, 0xF9, 0xC6, 0x06, 0x41, 0x00,
+  0x80, 0xEB, 0x09, 0xA8, 0x40, 0x75, 0x08, 0xC6, 0x06, 0x41, 0x00,
+  0x20, 0x59, 0xF9, 0xC3, 0x42, 0xEC, 0x50, 0xB9, 0x0A, 0x00, 0xE2,
+  0xFE, 0x4A, 0xEC, 0xA8, 0x10, 0xF8, 0x58, 0x59, 0xC3, 0x51, 0x33,
+  0xC9, 0xE2, 0xFE, 0xFE, 0xCC, 0x75, 0xF8, 0x59, 0xC3, 0xBD, 0x04,
+  0x00, 0xBB, 0x00, 0xB0, 0x3C, 0x07, 0x74, 0x06, 0xBD, 0x10, 0x00,
+  0xBB, 0x00, 0xB8, 0x53, 0x07, 0xA0, 0x65, 0x00, 0x24, 0xF7, 0x8B,
+  0x16, 0x63, 0x00, 0x83, 0xC2, 0x04, 0xEE, 0xE8, 0xE4, 0x0A, 0x4D,
+  0x75, 0xFA, 0x73, 0x05, 0x80, 0x0E, 0x15, 0x00, 0x04, 0xC3, 0x3C,
+  0x53, 0x75, 0x11, 0x8A, 0x0E, 0x17, 0x00, 0xF6, 0xC1, 0x04, 0x74,
+  0x08, 0xF6, 0xC1, 0x08, 0x74, 0x03, 0xE9, 0xC8, 0xFB, 0xC3, 0xFF,
+  0xFB, 0x1E, 0x50, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0x80, 0x0E, 0x3E,
+  0x00, 0x80, 0xB0, 0x20, 0xE6, 0x20, 0x58, 0x1F, 0xCF, 0xB0, 0x08,
+  0xE8, 0x23, 0x00, 0x53, 0x51, 0xB9, 0x07, 0x00, 0x33, 0xDB, 0xE8,
+  0x5E, 0xFF, 0x72, 0x0D, 0x88, 0x47, 0x42, 0x74, 0x0F, 0x43, 0xE2,
+  0xF3, 0xC6, 0x06, 0x41, 0x00, 0x20, 0xF9, 0x59, 0x5B, 0x58, 0xB0,
+  0x00, 0xC3, 0x59, 0x5B, 0xC3, 0x51, 0x52, 0x50, 0x33, 0xC9, 0xBA,
+  0xF4, 0x03, 0xEC, 0x0A, 0xC0, 0x78, 0x09, 0xE2, 0xF9, 0xC6, 0x06,
+  0x41, 0x00, 0x80, 0xEB, 0x12, 0xA8, 0x40, 0x74, 0x07, 0xC6, 0x06,
+  0x41, 0x00, 0x20, 0xEB, 0x07, 0x42, 0x58, 0xEE, 0xF8, 0x5A, 0x59,
+  0xC3, 0x58, 0x5A, 0x59, 0x58, 0xB0, 0x00, 0xF9, 0xC3, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xCF, 0x02, 0x25, 0x02, 0x08, 0x2A, 0xFF, 0x50, 0xF6,
+  0x19, 0x04, 0xFB, 0x1E, 0x53, 0x51, 0x52, 0xBB, 0x40, 0x00, 0x8E,
+  0xDB, 0x8B, 0xDA, 0xD1, 0xE3, 0x8B, 0x57, 0x08, 0x0B, 0xD2, 0x74,
+  0x0C, 0x0A, 0xE4, 0x74, 0x0D, 0xFE, 0xCC, 0x74, 0x39, 0xFE, 0xCC,
+  0x74, 0x29, 0x5A, 0x59, 0x5B, 0x1F, 0xCF, 0xEE, 0x42, 0x8A, 0x7F,
+  0x78, 0x8A, 0xE0, 0x33, 0xC9, 0xEC, 0x0A, 0xC0, 0x78, 0x0C, 0xE2,
+  0xF9, 0xFE, 0xCF, 0x75, 0xF3, 0x0C, 0x01, 0x24, 0xF9, 0xEB, 0x10,
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+  0x8A, 0xC8, 0xC3, 0x52, 0x8B, 0x16, 0x63, 0x00, 0x86, 0xC4, 0xEE,
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+  0x2E, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0x1E, 0xB8, 0x40, 0x00, 0x8E,
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+  0x24, 0xEC, 0xA8, 0xC0, 0x75, 0x0E, 0x46, 0xE2, 0xF6, 0x8C, 0xD8,
+  0x40, 0x8E, 0xD8, 0x3B, 0xC3, 0x75, 0xE8, 0xEB, 0x0C, 0x88, 0x24,
+  0x8C, 0xD8, 0xE8, 0x8E, 0xEC, 0x8B, 0xC6, 0xE8, 0x85, 0x00, 0xB8,
+  0x16, 0x00, 0xE8, 0xBD, 0x00, 0x1E, 0x0E, 0x1F, 0xBE, 0x42, 0xF9,
+  0xE8, 0xA9, 0x00, 0x1F, 0xE4, 0x21, 0x50, 0xB0, 0xFC, 0xE6, 0x21,
+  0xFB, 0xE8, 0xFE, 0x00, 0x50, 0xE8, 0x8E, 0x00, 0x58, 0x3C, 0x59,
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+  0xEC, 0x58, 0xE6, 0x21, 0xBA, 0x61, 0x00, 0xEC, 0x0C, 0x30, 0xEE,
+  0x24, 0xCF, 0xEE, 0xB0, 0x80, 0xE6, 0xA0, 0x07, 0x1F, 0x5D, 0x5F,
+  0x5E, 0x5A, 0x59, 0x5B, 0x58, 0xCF, 0xBC, 0x03, 0x78, 0x03, 0x78,
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+  0xE8, 0xFF, 0x58, 0xE8, 0xE4, 0xFF, 0xC3, 0x50, 0x8A, 0xC4, 0xE8,
+  0xDD, 0xFF, 0x58, 0xE8, 0xE9, 0xFF, 0xC3, 0x53, 0x50, 0xB4, 0x0E,
+  0xB3, 0x07, 0xCD, 0x10, 0x58, 0x5B, 0xC3, 0xAC, 0x0A, 0xC0, 0x74,
+  0x05, 0xE8, 0xED, 0xFF, 0xEB, 0xF6, 0xC3, 0x52, 0x53, 0x8B, 0xD0,
+  0xB4, 0x02, 0xB7, 0x00, 0xCD, 0x10, 0x5B, 0x5A, 0xC3, 0xBB, 0x70,
+  0x00, 0x26, 0x80, 0x3E, 0x49, 0x00, 0x07, 0x74, 0x03, 0xBB, 0x1F,
+  0x00, 0xB9, 0x01, 0x00, 0xAC, 0x0A, 0xC0, 0x74, 0x05, 0xE8, 0x05,
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+  0x03, 0xCD, 0x10, 0xB4, 0x02, 0xFE, 0xC2, 0xCD, 0x10, 0xC3, 0x8A,
+  0x26, 0x10, 0x00, 0x80, 0xE4, 0x30, 0xB0, 0x00, 0x80, 0xFC, 0x30,
+  0x74, 0x09, 0xB0, 0x01, 0x80, 0xFC, 0x10, 0x74, 0x02, 0xB0, 0x03,
+  0xB4, 0x00, 0xCD, 0x10, 0xC3, 0xB4, 0x00, 0xCD, 0x16, 0xC3, 0x50,
+  0x51, 0xB0, 0xB6, 0xE6, 0x43, 0xB8, 0x28, 0x05, 0xE6, 0x42, 0x8A,
+  0xC4, 0xE6, 0x42, 0xE4, 0x61, 0x50, 0x0C, 0x03, 0xE6, 0x61, 0x33,
+  0xC9, 0xE2, 0xFE, 0xFE, 0xCB, 0x75, 0xFA, 0x58, 0xE6, 0x61, 0x59,
+  0x58, 0xC3, 0xB9, 0x00, 0x20, 0xB0, 0x00, 0x02, 0x07, 0x43, 0xE2,
+  0xFB, 0x0A, 0xC0, 0xC3, 0xBB, 0x00, 0x04, 0xB0, 0x55, 0x33, 0xFF,
+  0x8B, 0xCB, 0x32, 0xC0, 0xF3, 0xAA, 0x8C, 0xC0, 0x05, 0x40, 0x00,
+  0x8E, 0xC0, 0xC3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x81,
+  0xA5, 0x81, 0xBD, 0x99, 0x81, 0x7E, 0x7E, 0xFF, 0xDB, 0xFF, 0xC3,
+  0xE7, 0xFF, 0x7E, 0x6C, 0xFE, 0xFE, 0xFE, 0x7C, 0x38, 0x10, 0x00,
+  0x10, 0x38, 0x7C, 0xFE, 0x7C, 0x38, 0x10, 0x00, 0x38, 0x7C, 0x38,
+  0xFE, 0xFE, 0x7C, 0x38, 0x7C, 0x10, 0x10, 0x38, 0x7C, 0xFE, 0x7C,
+  0x38, 0x7C, 0x00, 0x00, 0x18, 0x3C, 0x3C, 0x18, 0x00, 0x00, 0xFF,
+  0xFF, 0xE7, 0xC3, 0xC3, 0xE7, 0xFF, 0xFF, 0x00, 0x3C, 0x66, 0x42,
+  0x42, 0x66, 0x3C, 0x00, 0xFF, 0xC3, 0x99, 0xBD, 0xBD, 0x99, 0xC3,
+  0xFF, 0x0F, 0x07, 0x0F, 0x7D, 0xCC, 0xCC, 0xCC, 0x78, 0x3C, 0x66,
+  0x66, 0x66, 0x3C, 0x18, 0x7E, 0x18, 0x3F, 0x33, 0x3F, 0x30, 0x30,
+  0x70, 0xF0, 0xE0, 0x7F, 0x63, 0x7F, 0x63, 0x63, 0x67, 0xE6, 0xC0,
+  0x99, 0x5A, 0x3C, 0xE7, 0xE7, 0x3C, 0x5A, 0x99, 0x80, 0xE0, 0xF8,
+  0xFE, 0xF8, 0xE0, 0x80, 0x00, 0x02, 0x0E, 0x3E, 0xFE, 0x3E, 0x0E,
+  0x02, 0x00, 0x18, 0x3C, 0x7E, 0x18, 0x18, 0x7E, 0x3C, 0x18, 0x66,
+  0x66, 0x66, 0x66, 0x66, 0x00, 0x66, 0x00, 0x7F, 0xDB, 0xDB, 0x7B,
+  0x1B, 0x1B, 0x1B, 0x00, 0x3E, 0x63, 0x38, 0x6C, 0x6C, 0x38, 0xCC,
+  0x78, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x7E, 0x7E, 0x00, 0x18, 0x3C,
+  0x7E, 0x18, 0x7E, 0x3C, 0x18, 0xFF, 0x18, 0x3C, 0x7E, 0x18, 0x18,
+  0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x3C, 0x18, 0x00,
+  0x00, 0x18, 0x0C, 0xFE, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x30, 0x60,
+  0xFE, 0x60, 0x30, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC0, 0xC0, 0xFE,
+  0x00, 0x00, 0x00, 0x24, 0x66, 0xFF, 0x66, 0x24, 0x00, 0x00, 0x00,
+  0x18, 0x3C, 0x7E, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x7E,
+  0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x30, 0x78, 0x78, 0x30, 0x30, 0x00, 0x30, 0x00, 0x6C, 0x6C,
+  0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x6C, 0xFE, 0x6C, 0xFE,
+  0x6C, 0x6C, 0x00, 0x30, 0x7C, 0xC0, 0x78, 0x0C, 0xF8, 0x30, 0x00,
+  0x00, 0xC6, 0xCC, 0x18, 0x30, 0x66, 0xC6, 0x00, 0x38, 0x6C, 0x38,
+  0x76, 0xDC, 0xCC, 0x76, 0x00, 0x60, 0x60, 0xC0, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x18, 0x30, 0x60, 0x60, 0x60, 0x30, 0x18, 0x00, 0x60,
+  0x30, 0x18, 0x18, 0x18, 0x30, 0x60, 0x00, 0x00, 0x66, 0x3C, 0xFF,
+  0x3C, 0x66, 0x00, 0x00, 0x00, 0x30, 0x30, 0xFC, 0x30, 0x30, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x60, 0x00, 0x00,
+  0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x30, 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0x80, 0x00,
+  0x7C, 0xC6, 0xCE, 0xDE, 0xF6, 0xE6, 0x7C, 0x00, 0x30, 0x70, 0x30,
+  0x30, 0x30, 0x30, 0xFC, 0x00, 0x78, 0xCC, 0x0C, 0x38, 0x60, 0xCC,
+  0xFC, 0x00, 0x78, 0xCC, 0x0C, 0x38, 0x0C, 0xCC, 0x78, 0x00, 0x1C,
+  0x3C, 0x6C, 0xCC, 0xFE, 0x0C, 0x1E, 0x00, 0xFC, 0xC0, 0xF8, 0x0C,
+  0x0C, 0xCC, 0x78, 0x00, 0x38, 0x60, 0xC0, 0xF8, 0xCC, 0xCC, 0x78,
+  0x00, 0xFC, 0xCC, 0x0C, 0x18, 0x30, 0x30, 0x30, 0x00, 0x78, 0xCC,
+  0xCC, 0x78, 0xCC, 0xCC, 0x78, 0x00, 0x78, 0xCC, 0xCC, 0x7C, 0x0C,
+  0x18, 0x70, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x00,
+  0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x60, 0x18, 0x30, 0x60,
+  0xC0, 0x60, 0x30, 0x18, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFC,
+  0x00, 0x00, 0x60, 0x30, 0x18, 0x0C, 0x18, 0x30, 0x60, 0x00, 0x78,
+  0xCC, 0x0C, 0x18, 0x30, 0x00, 0x30, 0x00, 0x7C, 0xC6, 0xDE, 0xDE,
+  0xDE, 0xC0, 0x78, 0x00, 0x30, 0x78, 0xCC, 0xCC, 0xFC, 0xCC, 0xCC,
+  0x00, 0xFC, 0x66, 0x66, 0x7C, 0x66, 0x66, 0xFC, 0x00, 0x3C, 0x66,
+  0xC0, 0xC0, 0xC0, 0x66, 0x3C, 0x00, 0xF8, 0x6C, 0x66, 0x66, 0x66,
+  0x6C, 0xF8, 0x00, 0xFE, 0x62, 0x68, 0x78, 0x68, 0x62, 0xFE, 0x00,
+  0xFE, 0x62, 0x68, 0x78, 0x68, 0x60, 0xF0, 0x00, 0x3C, 0x66, 0xC0,
+  0xC0, 0xCE, 0x66, 0x3E, 0x00, 0xCC, 0xCC, 0xCC, 0xFC, 0xCC, 0xCC,
+  0xCC, 0x00, 0x78, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00, 0x1E,
+  0x0C, 0x0C, 0x0C, 0xCC, 0xCC, 0x78, 0x00, 0xE6, 0x66, 0x6C, 0x78,
+  0x6C, 0x66, 0xE6, 0x00, 0xF0, 0x60, 0x60, 0x60, 0x62, 0x66, 0xFE,
+  0x00, 0xC6, 0xEE, 0xFE, 0xFE, 0xD6, 0xC6, 0xC6, 0x00, 0xC6, 0xE6,
+  0xF6, 0xDE, 0xCE, 0xC6, 0xC6, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xC6,
+  0x6C, 0x38, 0x00, 0xFC, 0x66, 0x66, 0x7C, 0x60, 0x60, 0xF0, 0x00,
+  0x78, 0xCC, 0xCC, 0xCC, 0xDC, 0x78, 0x1C, 0x00, 0xFC, 0x66, 0x66,
+  0x7C, 0x6C, 0x66, 0xE6, 0x00, 0x78, 0xCC, 0xE0, 0x70, 0x1C, 0xCC,
+  0x78, 0x00, 0xFC, 0xB4, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00, 0xCC,
+  0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xFC, 0x00, 0xCC, 0xCC, 0xCC, 0xCC,
+  0xCC, 0x78, 0x30, 0x00, 0xC6, 0xC6, 0xC6, 0xD6, 0xFE, 0xEE, 0xC6,
+  0x00, 0xC6, 0xC6, 0x6C, 0x38, 0x38, 0x6C, 0xC6, 0x00, 0xCC, 0xCC,
+  0xCC, 0x78, 0x30, 0x30, 0x78, 0x00, 0xFE, 0xC6, 0x8C, 0x18, 0x32,
+  0x66, 0xFE, 0x00, 0x78, 0x60, 0x60, 0x60, 0x60, 0x60, 0x78, 0x00,
+  0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x02, 0x00, 0x78, 0x18, 0x18,
+  0x18, 0x18, 0x18, 0x78, 0x00, 0x10, 0x38, 0x6C, 0xC6, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x30,
+  0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x0C,
+  0x7C, 0xCC, 0x76, 0x00, 0xE0, 0x60, 0x60, 0x7C, 0x66, 0x66, 0xDC,
+  0x00, 0x00, 0x00, 0x78, 0xCC, 0xC0, 0xCC, 0x78, 0x00, 0x1C, 0x0C,
+  0x0C, 0x7C, 0xCC, 0xCC, 0x76, 0x00, 0x00, 0x00, 0x78, 0xCC, 0xFC,
+  0xC0, 0x78, 0x00, 0x38, 0x6C, 0x60, 0xF0, 0x60, 0x60, 0xF0, 0x00,
+  0x00, 0x00, 0x76, 0xCC, 0xCC, 0x7C, 0x0C, 0xF8, 0xE0, 0x60, 0x6C,
+  0x76, 0x66, 0x66, 0xE6, 0x00, 0x30, 0x00, 0x70, 0x30, 0x30, 0x30,
+  0x78, 0x00, 0x0C, 0x00, 0x0C, 0x0C, 0x0C, 0xCC, 0xCC, 0x78, 0xE0,
+  0x60, 0x66, 0x6C, 0x78, 0x6C, 0xE6, 0x00, 0x70, 0x30, 0x30, 0x30,
+  0x30, 0x30, 0x78, 0x00, 0x00, 0x00, 0xCC, 0xFE, 0xFE, 0xD6, 0xC6,
+  0x00, 0x00, 0x00, 0xF8, 0xCC, 0xCC, 0xCC, 0xCC, 0x00, 0x00, 0x00,
+  0x78, 0xCC, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0xDC, 0x66, 0x66,
+  0x7C, 0x60, 0xF0, 0x00, 0x00, 0x76, 0xCC, 0xCC, 0x7C, 0x0C, 0x1E,
+  0x00, 0x00, 0xDC, 0x76, 0x66, 0x60, 0xF0, 0x00, 0x00, 0x00, 0x7C,
+  0xC0, 0x78, 0x0C, 0xF8, 0x00, 0x10, 0x30, 0x7C, 0x30, 0x30, 0x34,
+  0x18, 0x00, 0x00, 0x00, 0xCC, 0xCC, 0xCC, 0xCC, 0x76, 0x00, 0x00,
+  0x00, 0xCC, 0xCC, 0xCC, 0x78, 0x30, 0x00, 0x00, 0x00, 0xC6, 0xD6,
+  0xFE, 0xFE, 0x6C, 0x00, 0x00, 0x00, 0xC6, 0x6C, 0x38, 0x6C, 0xC6,
+  0x00, 0x00, 0x00, 0xCC, 0xCC, 0xCC, 0x7C, 0x0C, 0xF8, 0x00, 0x00,
+  0xFC, 0x98, 0x30, 0x64, 0xFC, 0x00, 0x1C, 0x30, 0x30, 0xE0, 0x30,
+  0x30, 0x1C, 0x00, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00,
+  0xE0, 0x30, 0x30, 0x1C, 0x30, 0x30, 0xE0, 0x00, 0x76, 0xDC, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x6C, 0xC6, 0xC6,
+  0xFE, 0x00, 0xFB, 0x1E, 0x50, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0x58,
+  0xFA, 0x0A, 0xE4, 0x74, 0x13, 0xFE, 0xCC, 0x75, 0x1A, 0x89, 0x16,
+  0x6C, 0x00, 0x89, 0x0E, 0x6E, 0x00, 0xC6, 0x06, 0x70, 0x00, 0x00,
+  0xEB, 0x0B, 0x8B, 0x0E, 0x6E, 0x00, 0x8B, 0x16, 0x6C, 0x00, 0xE8,
+  0x03, 0x00, 0xFB, 0x1F, 0xCF, 0xA0, 0x70, 0x00, 0x30, 0x06, 0x70,
+  0x00, 0xC3, 0xFB, 0x1E, 0x52, 0x50, 0xB8, 0x40, 0x00, 0x8E, 0xD8,
+  0xFE, 0x0E, 0x40, 0x00, 0x75, 0x0B, 0x80, 0x26, 0x3F, 0x00, 0xF0,
+  0xB0, 0x0C, 0xBA, 0xF2, 0x03, 0xEE, 0xFF, 0x06, 0x6C, 0x00, 0x75,
+  0x04, 0xFF, 0x06, 0x6E, 0x00, 0x83, 0x3E, 0x6E, 0x00, 0x18, 0x75,
+  0x19, 0x81, 0x3E, 0x6C, 0x00, 0xB0, 0x00, 0x75, 0x11, 0xC7, 0x06,
+  0x6E, 0x00, 0x00, 0x00, 0xC7, 0x06, 0x6C, 0x00, 0x00, 0x00, 0xC6,
+  0x06, 0x70, 0x00, 0x01, 0xCD, 0x1C, 0xB0, 0x20, 0xE6, 0x20, 0x58,
+  0x5A, 0x1F, 0xCF, 0xA5, 0xFE, 0x87, 0xE9, 0x23, 0xFF, 0x23, 0xFF,
+  0x23, 0xFF, 0x23, 0xFF, 0x57, 0xEF, 0x23, 0xFF, 0x65, 0xF0, 0x4D,
+  0xF8, 0x41, 0xF8, 0x59, 0xEC, 0x39, 0xE7, 0x59, 0xF8, 0x2E, 0xE8,
+  0xD2, 0xEF, 0x23, 0xFF, 0xF2, 0xE6, 0x6E, 0xFE, 0x53, 0xFF, 0x53,
+  0xFF, 0xA4, 0xF0, 0xC7, 0xEF, 0x00, 0x00, 0x1E, 0x52, 0x50, 0xB8,
+  0x40, 0x00, 0x8E, 0xD8, 0xB0, 0x0B, 0xE6, 0x20, 0x90, 0xE4, 0x20,
+  0x8A, 0xE0, 0x0A, 0xC0, 0x75, 0x04, 0xB0, 0xFF, 0xEB, 0x0A, 0xE4,
+  0x21, 0x0A, 0xC4, 0xE6, 0x21, 0xB0, 0x20, 0xE6, 0x20, 0x88, 0x26,
+  0x6B, 0x00, 0x58, 0x5A, 0x1F, 0xCF, 0x68, 0x00, 0xFF, 0xFF, 0xFF,
+  0xCF, 0xFB, 0x1E, 0x50, 0x53, 0x51, 0x52, 0xB8, 0x40, 0x00, 0x8E,
+  0xD8, 0x80, 0x3E, 0x00, 0x01, 0x01, 0x74, 0x56, 0xC6, 0x06, 0x00,
+  0x01, 0x01, 0xE8, 0x5D, 0x00, 0xB4, 0x0F, 0xCD, 0x10, 0x50, 0xB4,
+  0x03, 0xCD, 0x10, 0x58, 0x52, 0xB5, 0x19, 0x8A, 0xCC, 0x33, 0xD2,
+  0xB4, 0x02, 0xCD, 0x10, 0xB4, 0x08, 0xCD, 0x10, 0x0A, 0xC0, 0x75,
+  0x02, 0xB0, 0x20, 0x52, 0x33, 0xD2, 0x8A, 0xE2, 0xCD, 0x17, 0x5A,
+  0xF6, 0xC4, 0x25, 0x74, 0x07, 0xC6, 0x06, 0x00, 0x01, 0xFF, 0xEB,
+  0x16, 0xFE, 0xC2, 0x3A, 0xCA, 0x75, 0xD8, 0xB2, 0x00, 0xE8, 0x1F,
+  0x00, 0xFE, 0xC6, 0x3A, 0xF5, 0x75, 0xCD, 0xC6, 0x06, 0x00, 0x01,
+  0x00, 0x5A, 0xB4, 0x02, 0xCD, 0x10, 0x5A, 0x59, 0x5B, 0x58, 0x1F,
+  0xCF, 0xC3, 0x20, 0x54, 0x69, 0x6D, 0x65, 0x72, 0x00, 0xFF, 0x52,
+  0x33, 0xD2, 0x8A, 0xE2, 0xB0, 0x0A, 0xCD, 0x17, 0xB4, 0x00, 0xB0,
+  0x0D, 0xCD, 0x17, 0x5A, 0xC3, 0xC7, 0x06, 0x60, 0x00, 0x07, 0x06,
+  0x80, 0x3E, 0x49, 0x00, 0x07, 0x75, 0x06, 0xC7, 0x06, 0x60, 0x00,
+  0x0C, 0x0B, 0xC3, 0xEA, 0x5B, 0xE0, 0x00, 0xF0, 0x30, 0x35, 0x2F,
+  0x30, 0x32, 0x2F, 0x31, 0x32, 0xFF, 0xFE, 0xE2
+};
+
+#ifdef INCLUDE_ROM_BASIC
+#ifdef MEGA
+  const uint8_t BASICL[16384] PROGMEM = {
+#else
+  const uint8_t BASICL[16384] = {
+#endif
+  0xE9, 0x8F, 0x7E, 0xE8, 0xA7, 0x6B, 0xCB, 0xE8, 0x2, 0x65, 0xCB,
+  0x5D, 0xE8, 0xC7, 0x2F, 0x74, 0xD, 0x8B, 0x36, 0xE9, 0x4, 0x8A,
+  0x44, 0x2E, 0x3C, 0xFE, 0x74, 0x2, 0x3C, 0xFD, 0xC3, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x33, 0x2E, 0x94, 0xD, 0x68, 0x73, 0x5B,
+  0x11, 0x59, 0x15, 0x66, 0x37, 0x3E, 0x16, 0x8F, 0x11, 0xED, 0x10,
+  0xB6, 0x10, 0xF8, 0x12, 0xC, 0x2E, 0xCE, 0x10, 0x35, 0x11, 0x5F,
+  0x11, 0x2D, 0x2E, 0x48, 0x13, 0x50, 0x2F, 0x35, 0x1F, 0x1B, 0x2D,
+  0xFE, 0x11, 0x58, 0x1E, 0xF0, 0x1B, 0x91, 0x22, 0x85, 0x2E, 0xBE,
+  0x7, 0xBE, 0x7, 0x53, 0x1E, 0x43, 0x13, 0x2E, 0x1F, 0x0, 0x0,
+  0x8A, 0x1E, 0x5F, 0x11, 0x9C, 0x2E, 0x9D, 0x2E, 0xA3, 0x2E, 0xF3,
+  0x2E, 0xDF, 0x36, 0xA9, 0x12, 0x58, 0x12, 0x39, 0x22, 0xB8, 0x12,
+  0xD8, 0x22, 0xFB, 0xF, 0xFE, 0xF, 0x1, 0x10, 0x4, 0x10, 0xD9,
+  0x14, 0x4, 0x3D, 0x30, 0x3D, 0xA0, 0x5D, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0xA9, 0x3D, 0x3F, 0x24, 0x9E, 0x24, 0x4, 0x40, 0x52,
+  0x43, 0x6C, 0x41, 0x6D, 0x41, 0xCE, 0x41, 0x2F, 0x53, 0xE7, 0x52,
+  0x26, 0x5D, 0x13, 0x46, 0x33, 0x46, 0x29, 0x58, 0xD, 0x58, 0xD1,
+  0x47, 0xCD, 0x47, 0x93, 0x51, 0x2A, 0x50, 0x17, 0x54, 0x68, 0x29,
+  0xA5, 0x29, 0xB1, 0x29, 0x1C, 0x65, 0x80, 0x7E, 0x96, 0x7D, 0xF1,
+  0x70, 0x87, 0x78, 0xE, 0x7A, 0xC, 0x73, 0x84, 0x62, 0xF4, 0x79,
+  0xAD, 0x7A, 0xCD, 0x7A, 0x8C, 0x2B, 0x3D, 0x1E, 0x7A, 0x1B, 0xE8,
+  0x28, 0x17, 0x26, 0xE9, 0x29, 0xF8, 0x28, 0xB, 0x29, 0x80, 0x22,
+  0x47, 0x29, 0xD, 0x26, 0x12, 0x26, 0x75, 0x1B, 0xAD, 0x6B, 0x51,
+  0x6B, 0x82, 0x6B, 0x9C, 0x65, 0xFA, 0x55, 0x98, 0x56, 0x12, 0x57,
+  0xC0, 0x44, 0x98, 0x44, 0xAC, 0x44, 0x37, 0x1, 0x48, 0x1, 0x57,
+  0x1, 0x8B, 0x1, 0xB4, 0x1, 0xD9, 0x1, 0xE5, 0x1, 0xF4, 0x1,
+  0xF9, 0x1, 0x15, 0x2, 0x16, 0x2, 0x1A, 0x2, 0x50, 0x2, 0x62,
+  0x2, 0x6D, 0x2, 0x86, 0x2, 0xA9, 0x2, 0xAA, 0x2, 0xDF, 0x2,
+  0x23, 0x3, 0x3A, 0x3, 0x43, 0x3, 0x4D, 0x3, 0x65, 0x3, 0x69,
+  0x3, 0x6A, 0x3, 0x55, 0x54, 0xCF, 0xAA, 0x4E, 0xC4, 0xEE, 0x42,
+  0xD3, 0x6, 0x54, 0xCE, 0xE, 0x53, 0xC3, 0x15, 0x0, 0x53, 0x41,
+  0x56, 0xC5, 0xC2, 0x4C, 0x4F, 0x41, 0xC4, 0xC3, 0x45, 0x45, 0xD0,
+  0xC5, 0x0, 0x4F, 0x4C, 0x4F, 0xD2, 0xBF, 0x4C, 0x4F, 0x53, 0xC5,
+  0xBB, 0x4F, 0x4E, 0xD4, 0x99, 0x4C, 0x45, 0x41, 0xD2, 0x92, 0x53,
+  0x52, 0x4C, 0x49, 0xCE, 0xDB, 0x49, 0x4E, 0xD4, 0x1C, 0x53, 0x4E,
+  0xC7, 0x1D, 0x44, 0x42, 0xCC, 0x1E, 0x4F, 0xD3, 0xC, 0x48, 0x52,
+  0xA4, 0x16, 0x41, 0x4C, 0xCC, 0xB3, 0x4C, 0xD3, 0xC0, 0x0, 0x45,
+  0x4C, 0x45, 0x54, 0xC5, 0xA9, 0x41, 0x54, 0xC1, 0x84, 0x49, 0xCD,
+  0x86, 0x45, 0x46, 0x53, 0x54, 0xD2, 0xAC, 0x45, 0x46, 0x49, 0x4E,
+  0xD4, 0xAD, 0x45, 0x46, 0x53, 0x4E, 0xC7, 0xAE, 0x45, 0x46, 0x44,
+  0x42, 0xCC, 0xAF, 0x45, 0xC6, 0x97, 0x0, 0x4C, 0x53, 0xC5, 0xA1,
+  0x4E, 0xC4, 0x81, 0x52, 0x41, 0x53, 0xC5, 0xA5, 0x44, 0x49, 0xD4,
+  0xA6, 0x52, 0x52, 0x4F, 0xD2, 0xA7, 0x52, 0xCC, 0xD4, 0x52, 0xD2,
+  0xD5, 0x58, 0xD0, 0xB, 0x4F, 0xC6, 0x23, 0x51, 0xD6, 0xF1, 0x0,
+  0x4F, 0xD2, 0x82, 0xCE, 0xD1, 0x52, 0xC5, 0xF, 0x49, 0xD8, 0x1F,
+  0x0, 0x4F, 0x54, 0xCF, 0x89, 0x4F, 0x20, 0x54, 0xCF, 0x89, 0x4F,
+  0x53, 0x55, 0xC2, 0x8D, 0x0, 0x45, 0x58, 0xA4, 0x1A, 0x0, 0x4E,
+  0x50, 0x55, 0xD4, 0x85, 0xC6, 0x8B, 0x4E, 0x53, 0x54, 0xD2, 0xD8,
+  0x4E, 0xD4, 0x5, 0x4E, 0xD0, 0x10, 0x4D, 0xD0, 0xF2, 0x4E, 0x4B,
+  0x45, 0x59, 0xA4, 0xDE, 0x0, 0x0, 0x45, 0xD9, 0xC9, 0x0, 0x4F,
+  0x43, 0x41, 0x54, 0xC5, 0xCA, 0x50, 0x52, 0x49, 0x4E, 0xD4, 0x9D,
+  0x4C, 0x49, 0x53, 0xD4, 0x9E, 0x50, 0x4F, 0xD3, 0x1B, 0x45, 0xD4,
+  0x88, 0x49, 0x4E, 0xC5, 0xB0, 0x4F, 0x41, 0xC4, 0xBC, 0x49, 0x53,
+  0xD4, 0x93, 0x4F, 0xC7, 0xA, 0x4F, 0xC3, 0x24, 0x45, 0xCE, 0x12,
+  0x45, 0x46, 0x54, 0xA4, 0x1, 0x4F, 0xC6, 0x25, 0x0, 0x4F, 0x54,
+  0x4F, 0xD2, 0xC1, 0x45, 0x52, 0x47, 0xC5, 0xBD, 0x4F, 0xC4, 0xF3,
+  0x49, 0x44, 0xA4, 0x3, 0x0, 0x45, 0x58, 0xD4, 0x83, 0x45, 0xD7,
+  0x94, 0x4F, 0xD4, 0xD3, 0x0, 0x50, 0x45, 0xCE, 0xBA, 0x55, 0xD4,
+  0x9C, 0xCE, 0x95, 0xD2, 0xEF, 0x43, 0x54, 0xA4, 0x19, 0x50, 0x54,
+  0x49, 0x4F, 0xCE, 0xB8, 0x46, 0xC6, 0xDD, 0x0, 0x52, 0x49, 0x4E,
+  0xD4, 0x91, 0x4F, 0x4B, 0xC5, 0x98, 0x4F, 0xD3, 0x11, 0x45, 0x45,
+  0xCB, 0x17, 0x53, 0x45, 0xD4, 0xC6, 0x52, 0x45, 0x53, 0x45, 0xD4,
+  0xC7, 0x4F, 0x49, 0x4E, 0xD4, 0xDC, 0x45, 0xCE, 0x20, 0x0, 0x0,
+  0x55, 0xCE, 0x8A, 0x45, 0x54, 0x55, 0x52, 0xCE, 0x8E, 0x45, 0x41,
+  0xC4, 0x87, 0x45, 0x53, 0x54, 0x4F, 0x52, 0xC5, 0x8C, 0x45, 0xCD,
+  0x8F, 0x45, 0x53, 0x55, 0x4D, 0xC5, 0xA8, 0x49, 0x47, 0x48, 0x54,
+  0xA4, 0x2, 0x4E, 0xC4, 0x8, 0x45, 0x4E, 0x55, 0xCD, 0xAB, 0x41,
+  0x4E, 0x44, 0x4F, 0x4D, 0x49, 0x5A, 0xC5, 0xB9, 0x0, 0x43, 0x52,
+  0x45, 0x45, 0xCE, 0xC8, 0x54, 0x4F, 0xD0, 0x90, 0x57, 0x41, 0xD0,
+  0xA4, 0x41, 0x56, 0xC5, 0xBE, 0x50, 0x43, 0xA8, 0xD2, 0x54, 0x45,
+  0xD0, 0xCF, 0x47, 0xCE, 0x4, 0x51, 0xD2, 0x7, 0x49, 0xCE, 0x9,
+  0x54, 0x52, 0xA4, 0x13, 0x54, 0x52, 0x49, 0x4E, 0x47, 0xA4, 0xD6,
+  0x50, 0x41, 0x43, 0x45, 0xA4, 0x18, 0x4F, 0x55, 0x4E, 0xC4, 0xC4,
+  0x54, 0x49, 0x43, 0xCB, 0x21, 0x54, 0x52, 0x49, 0xC7, 0x22, 0x0,
+  0x48, 0x45, 0xCE, 0xCD, 0x52, 0x4F, 0xCE, 0xA2, 0x52, 0x4F, 0x46,
+  0xC6, 0xA3, 0x41, 0x42, 0xA8, 0xCE, 0xCF, 0xCC, 0x41, 0xCE, 0xD,
+  0x0, 0x53, 0x49, 0x4E, 0xC7, 0xD7, 0x53, 0xD2, 0xD0, 0x0, 0x41,
+  0xCC, 0x14, 0x41, 0x52, 0x50, 0x54, 0xD2, 0xDA, 0x0, 0x49, 0x44,
+  0x54, 0xC8, 0xA0, 0x41, 0x49, 0xD4, 0x96, 0x48, 0x49, 0x4C, 0xC5,
+  0xB1, 0x45, 0x4E, 0xC4, 0xB2, 0x52, 0x49, 0x54, 0xC5, 0xB7, 0x0,
+  0x4F, 0xD2, 0xF0, 0x0, 0x0, 0x0, 0xAB, 0xE9, 0xAD, 0xEA, 0xAA,
+  0xEB, 0xAF, 0xEC, 0xDE, 0xED, 0xDC, 0xF4, 0xA7, 0xD9, 0xBE, 0xE6,
+  0xBD, 0xE7, 0xBC, 0xE8, 0x0, 0x79, 0x79, 0x7C, 0x7C, 0x7F, 0x50,
+  0x46, 0x3C, 0x32, 0x28, 0x7A, 0x7B, 0x82, 0x6B, 0x0, 0x0, 0xAD,
+  0x6B, 0x3B, 0x64, 0x51, 0x6B, 0xA8, 0x66, 0x3, 0x63, 0x53, 0x6C,
+  0x20, 0x63, 0x74, 0x65, 0x12, 0x63, 0x19, 0x63, 0x41, 0x63, 0x28,
+  0x63, 0x31, 0x64, 0x6A, 0x63, 0x4F, 0x63, 0x89, 0x63, 0xD7, 0x18,
+  0xB4, 0x65, 0x0, 0x4E, 0x45, 0x58, 0x54, 0x20, 0x77, 0x69, 0x74,
+  0x68, 0x6F, 0x75, 0x74, 0x20, 0x46, 0x4F, 0x52, 0x0, 0x53, 0x79,
+  0x6E, 0x74, 0x61, 0x78, 0x20, 0x65, 0x72, 0x72, 0x6F, 0x72, 0x0,
+  0x52, 0x45, 0x54, 0x55, 0x52, 0x4E, 0x20, 0x77, 0x69, 0x74, 0x68,
+  0x6F, 0x75, 0x74, 0x20, 0x47, 0x4F, 0x53, 0x55, 0x42, 0x0, 0x4F,
+  0x75, 0x74, 0x20, 0x6F, 0x66, 0x20, 0x44, 0x41, 0x54, 0x41, 0x0,
+  0x49, 0x6C, 0x6C, 0x65, 0x67, 0x61, 0x6C, 0x20, 0x66, 0x75, 0x6E,
+  0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x63, 0x61, 0x6C, 0x6C, 0x0,
+  0x4F, 0x76, 0x65, 0x72, 0x66, 0x6C, 0x6F, 0x77, 0x0, 0x4F, 0x75,
+  0x74, 0x20, 0x6F, 0x66, 0x20, 0x6D, 0x65, 0x6D, 0x6F, 0x72, 0x79,
+  0x0, 0x55, 0x6E, 0x64, 0x65, 0x66, 0x69, 0x6E, 0x65, 0x64, 0x20,
+  0x6C, 0x69, 0x6E, 0x65, 0x20, 0x6E, 0x75, 0x6D, 0x62, 0x65, 0x72,
+  0x0, 0x53, 0x75, 0x62, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20,
+  0x6F, 0x75, 0x74, 0x20, 0x6F, 0x66, 0x20, 0x72, 0x61, 0x6E, 0x67,
+  0x65, 0x0, 0x44, 0x75, 0x70, 0x6C, 0x69, 0x63, 0x61, 0x74, 0x65,
+  0x20, 0x44, 0x65, 0x66, 0x69, 0x6E, 0x69, 0x74, 0x69, 0x6F, 0x6E,
+  0x0, 0x44, 0x69, 0x76, 0x69, 0x73, 0x69, 0x6F, 0x6E, 0x20, 0x62,
+  0x79, 0x20, 0x7A, 0x65, 0x72, 0x6F, 0x0, 0x49, 0x6C, 0x6C, 0x65,
+  0x67, 0x61, 0x6C, 0x20, 0x64, 0x69, 0x72, 0x65, 0x63, 0x74, 0x0,
+  0x54, 0x79, 0x70, 0x65, 0x20, 0x6D, 0x69, 0x73, 0x6D, 0x61, 0x74,
+  0x63, 0x68, 0x0, 0x4F, 0x75, 0x74, 0x20, 0x6F, 0x66, 0x20, 0x73,
+  0x74, 0x72, 0x69, 0x6E, 0x67, 0x20, 0x73, 0x70, 0x61, 0x63, 0x65,
+  0x0, 0x53, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x20, 0x74, 0x6F, 0x6F,
+  0x20, 0x6C, 0x6F, 0x6E, 0x67, 0x0, 0x53, 0x74, 0x72, 0x69, 0x6E,
+  0x67, 0x20, 0x66, 0x6F, 0x72, 0x6D, 0x75, 0x6C, 0x61, 0x20, 0x74,
+  0x6F, 0x6F, 0x20, 0x63, 0x6F, 0x6D, 0x70, 0x6C, 0x65, 0x78, 0x0,
+  0x43, 0x61, 0x6E, 0x27, 0x74, 0x20, 0x63, 0x6F, 0x6E, 0x74, 0x69,
+  0x6E, 0x75, 0x65, 0x0, 0x55, 0x6E, 0x64, 0x65, 0x66, 0x69, 0x6E,
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+  0xEB, 0x8D, 0x4B, 0x50, 0xCD, 0x92, 0xBA, 0xC, 0xC, 0x8A, 0xC8,
+  0x8B, 0xF2, 0x2E, 0xAC, 0xA, 0xC0, 0x74, 0x17, 0x42, 0x3A, 0xC1,
+  0x75, 0xF3, 0xEB, 0x14, 0x8C, 0xAA, 0xAB, 0xA9, 0xA6, 0xA8, 0xD4,
+  0xA1, 0x8A, 0x93, 0x9E, 0x89, 0x8E, 0xCD, 0x8D, 0x0, 0x32, 0xC0,
+  0xEB, 0x2, 0xB0, 0x1, 0xA2, 0xFD, 0x2, 0x58, 0x59, 0x5A, 0x3C,
+  0xA1, 0x50, 0x75, 0x3, 0xE8, 0xFA, 0x0, 0x58, 0x3C, 0xB1, 0x75,
+  0x5, 0xE8, 0xF4, 0x0, 0xB0, 0xE9, 0x3C, 0xD9, 0x74, 0x3, 0xE9,
+  0xC6, 0x0, 0x50, 0xE8, 0xE5, 0x0, 0xB0, 0x8F, 0xE8, 0xE2, 0x0,
+  0x58, 0x50, 0xE9, 0xAD, 0xFE, 0x8A, 0x7, 0x3C, 0x2E, 0x74, 0xE,
+  0x3C, 0x3A, 0x72, 0x3, 0xE9, 0x90, 0x0, 0x3C, 0x30, 0x73, 0x3,
+  0xE9, 0x89, 0x0, 0xA0, 0xFD, 0x2, 0xA, 0xC0, 0x8A, 0x7, 0x59,
+  0x5A, 0x79, 0x3, 0xE9, 0x62, 0xFE, 0x74, 0x27, 0x3C, 0x2E, 0x75,
+  0x3, 0xE9, 0x59, 0xFE, 0xB0, 0xE, 0xE8, 0xAD, 0x0, 0x52, 0xE8,
+  0xE8, 0x3, 0xE8, 0xFD, 0x0, 0x5E, 0x87, 0xDE, 0x56, 0x87, 0xDA,
+  0x8A, 0xC3, 0xE8, 0x9B, 0x0, 0x8A, 0xC7, 0x5B, 0xE8, 0x95, 0x0,
+  0xE9, 0xFF, 0xFD, 0x52, 0x51, 0x8A, 0x7, 0xE8, 0x1F, 0x5D, 0xE8,
+  0xDF, 0x0, 0x59, 0x5A, 0x53, 0xA0, 0xFB, 0x2, 0x3C, 0x2, 0x75,
+  0x1A, 0x8B, 0x1E, 0xA3, 0x4, 0x8A, 0xC7, 0xA, 0xC0, 0xB0, 0x2,
+  0x75, 0xE, 0x8A, 0xC3, 0x8A, 0xFB, 0xB3, 0xF, 0x3C, 0xA, 0x73,
+  0xC8, 0x4, 0x11, 0xEB, 0xCB, 0x50, 0xD0, 0xC8, 0x4, 0x1B, 0xE8,
+  0x5C, 0x0, 0xBB, 0xA3, 0x4, 0xE8, 0x4F, 0xE, 0x72, 0x3, 0xBB,
+  0x9F, 0x4, 0x58, 0x50, 0x8A, 0x7, 0xE8, 0x4A, 0x0, 0x58, 0x43,
+  0xFE, 0xC8, 0x75, 0xF4, 0x5B, 0xE9, 0xAD, 0xFD, 0xBA, 0x6A, 0x3,
+  0x42, 0x8B, 0xF2, 0x2E, 0xAC, 0x24, 0x7F, 0x75, 0x3, 0xE9, 0x6B,
+  0x0, 0x42, 0x3A, 0x7, 0x8B, 0xF2, 0x2E, 0xAC, 0x75, 0xEB, 0xE9,
+  0x6F, 0x0, 0x3C, 0x26, 0x74, 0x3, 0xE9, 0xC5, 0xFD, 0x53, 0xE8,
+  0xB, 0x2, 0x5B, 0xE8, 0xD7, 0xC, 0x3C, 0x48, 0xB0, 0xB, 0x75,
+  0x2, 0xB0, 0xC, 0xE8, 0xB, 0x0, 0x52, 0x51, 0xE8, 0xD9, 0xC,
+  0x59, 0xE9, 0x5C, 0xFF, 0xB0, 0x3A, 0x8B, 0xFA, 0xAA, 0x42, 0x49,
+  0x8A, 0xC1, 0xA, 0xC5, 0x74, 0x1, 0xC3, 0xB2, 0x17, 0xE9, 0x9B,
+  0xFA, 0xCD, 0x93, 0x5B, 0x4B, 0xFE, 0xC8, 0xA2, 0xFD, 0x2, 0x59,
+  0x5A, 0xE8, 0xA0, 0xC, 0xE8, 0xDE, 0xFF, 0x43, 0xE8, 0x99, 0xC,
+  0xE8, 0xF0, 0x21, 0x73, 0xF4, 0x3C, 0x3A, 0x73, 0x8, 0x3C, 0x30,
+  0x73, 0xEC, 0x3C, 0x2E, 0x74, 0xE8, 0xE9, 0x33, 0xFD, 0x8A, 0x7,
+  0x3C, 0x20, 0x73, 0xA, 0x3C, 0x9, 0x74, 0x6, 0x3C, 0xA, 0x74,
+  0x2, 0xB0, 0x20, 0x50, 0xA0, 0xFD, 0x2, 0xFE, 0xC0, 0x74, 0x2,
+  0xFE, 0xC8, 0xE9, 0x9F, 0xFE, 0x4B, 0x8A, 0x7, 0x3C, 0x20, 0x74,
+  0xF9, 0x3C, 0x9, 0x74, 0xF5, 0x3C, 0xA, 0x74, 0xF1, 0x43, 0xC3,
+  0xB0, 0x64, 0xA2, 0x39, 0x3, 0xE8, 0xD2, 0x29, 0xE8, 0x55, 0x20,
+  0xE7, 0x52, 0x89, 0x16, 0x3B, 0x3, 0xA0, 0xFB, 0x2, 0x50, 0xE8,
+  0x7B, 0x9, 0x58, 0x53, 0xE8, 0x29, 0x10, 0xBB, 0x56, 0x4, 0xE8,
+  0x45, 0x56, 0x5B, 0x5A, 0x59, 0x53, 0xE8, 0x9D, 0x3, 0x89, 0x1E,
+  0x35, 0x3, 0xBB, 0x2, 0x0, 0x3, 0xDC, 0xE8, 0x73, 0xF9, 0x75,
+  0x1E, 0x3, 0xD9, 0x52, 0x4B, 0x8A, 0x37, 0x4B, 0x8A, 0x17, 0x43,
+  0x43, 0x53, 0x8B, 0x1E, 0x35, 0x3, 0x3B, 0xDA, 0x5B, 0x5A, 0x75,
+  0xE5, 0x5A, 0x8B, 0xE3, 0x89, 0x1E, 0x45, 0x3, 0xB1, 0x5A, 0x87,
+  0xDA, 0xB1, 0x8, 0xE8, 0xE3, 0x1E, 0x53, 0x8B, 0x1E, 0x35, 0x3,
+  0x5E, 0x87, 0xDE, 0x56, 0x53, 0x8B, 0x1E, 0x2E, 0x0, 0x5E, 0x87,
+  0xDE, 0x56, 0xE8, 0xED, 0x1F, 0xCC, 0xE8, 0x1A, 0xD, 0x75, 0x3,
+  0xE9, 0xC6, 0xF9, 0x72, 0x3, 0xE9, 0xC1, 0xF9, 0x9C, 0xE8, 0xE,
+  0x9, 0x9D, 0x53, 0x78, 0x3, 0xE9, 0x1C, 0x0, 0xE8, 0x8A, 0x5D,
+  0x5E, 0x87, 0xDE, 0x56, 0xBA, 0x1, 0x0, 0x8A, 0x7, 0x3C, 0xCF,
+  0x75, 0x3, 0xE8, 0xD4, 0x10, 0x52, 0x53, 0x87, 0xDA, 0xE8, 0xC6,
+  0x56, 0xEB, 0x27, 0xE8, 0x12, 0x5D, 0xE8, 0xB1, 0x55, 0x5B, 0x51,
+  0x52, 0xB9, 0x0, 0x81, 0x8A, 0xF1, 0x8A, 0xD6, 0xCD, 0x94, 0x8A,
+  0x7, 0x3C, 0xCF, 0xB0, 0x1, 0x75, 0xE, 0xE8, 0xCF, 0x8, 0x53,
+  0xE8, 0xF4, 0x5C, 0xE8, 0x93, 0x55, 0xE8, 0x12, 0x6D, 0x5B, 0x51,
+  0x52, 0x8A, 0xC8, 0xE8, 0xBA, 0xC, 0x8A, 0xE8, 0x51, 0x4B, 0xE8,
+  0xAB, 0x0, 0x74, 0x3, 0xE9, 0x47, 0xF9, 0xE8, 0x81, 0x16, 0xE8,
+  0xA0, 0x0, 0x53, 0x53, 0x8B, 0x1E, 0x5A, 0x4, 0x89, 0x1E, 0x2E,
+  0x0, 0x8B, 0x1E, 0x3B, 0x3, 0x5E, 0x87, 0xDE, 0x56, 0xB5, 0x82,
+  0x51, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x9F, 0x86, 0xC4, 0x50,
+  0x86, 0xC4, 0xE9, 0xCF, 0x64, 0xB5, 0x82, 0x51, 0xEB, 0x42, 0xE9,
+  0xCB, 0xF8, 0xE9, 0x12, 0xF9, 0xC3, 0xE8, 0x75, 0x0, 0xEB, 0x50,
+  0xCD, 0x95, 0xE9, 0x63, 0xF, 0xE9, 0xD5, 0x2, 0xA, 0xC0, 0x75,
+  0xEB, 0x43, 0x8A, 0x7, 0x43, 0xA, 0x7, 0x74, 0xE0, 0x43, 0x8B,
+  0x17, 0x43, 0x89, 0x16, 0x2E, 0x0, 0xF6, 0x6, 0x76, 0x4, 0xFF,
+  0x74, 0x26, 0x53, 0xB0, 0x5B, 0xE8, 0xCA, 0x1C, 0x87, 0xDA, 0xE8,
+  0x70, 0x56, 0xB0, 0x5D, 0xE8, 0xC0, 0x1C, 0x5B, 0xEB, 0x13, 0xCD,
+  0x96, 0xE8, 0x9B, 0x1D, 0x89, 0x26, 0x45, 0x3, 0x89, 0x1E, 0x43,
+  0x3, 0x8A, 0x7, 0x3C, 0x3A, 0x75, 0xBF, 0x43, 0x8A, 0x7, 0x3C,
+  0x3A, 0x72, 0xAB, 0xBA, 0xE8, 0xE, 0x52, 0x74, 0xA4, 0x2C, 0x81,
+  0x72, 0xAB, 0x3C, 0x4A, 0x73, 0xA2, 0x32, 0xE4, 0x2, 0xC0, 0x8B,
+  0xF0, 0xCD, 0x97, 0x2E, 0xFF, 0xB4, 0x25, 0x0, 0x43, 0x8A, 0x7,
+  0x3C, 0x3A, 0x72, 0x1, 0xC3, 0x3C, 0x20, 0x74, 0xF4, 0x72, 0x8,
+  0x3C, 0x30, 0xF5, 0xFE, 0xC0, 0xFE, 0xC8, 0xC3, 0xA, 0xC0, 0x74,
+  0xFB, 0x3C, 0xB, 0x72, 0x72, 0x3C, 0x1E, 0x75, 0x6, 0xA0, 0x0,
+  0x3, 0xA, 0xC0, 0xC3, 0x3C, 0x10, 0x74, 0x3C, 0x50, 0x43, 0xA2,
+  0x0, 0x3, 0x2C, 0x1C, 0x73, 0x39, 0x2C, 0xF5, 0x73, 0x7, 0x3C,
+  0xFE, 0x75, 0x1B, 0x8A, 0x7, 0x43, 0x89, 0x1E, 0xFE, 0x2, 0xB7,
+  0x0, 0x8A, 0xD8, 0x89, 0x1E, 0x2, 0x3, 0xB0, 0x2, 0xA2, 0x1,
+  0x3, 0xBB, 0x4, 0x0, 0x58, 0xA, 0xC0, 0xC3, 0x8A, 0x7, 0x43,
+  0x43, 0x89, 0x1E, 0xFE, 0x2, 0x4B, 0x8A, 0x3F, 0xEB, 0xE1, 0xE8,
+  0x37, 0x0, 0x8B, 0x1E, 0xFE, 0x2, 0xEB, 0x93, 0xFE, 0xC0, 0xD0,
+  0xC0, 0xA2, 0x1, 0x3, 0x52, 0x51, 0xBA, 0x2, 0x3, 0x87, 0xDA,
+  0x8A, 0xE8, 0xE8, 0x13, 0x55, 0x87, 0xDA, 0x59, 0x5A, 0x89, 0x1E,
+  0xFE, 0x2, 0x58, 0xBB, 0x4, 0x0, 0xA, 0xC0, 0xC3, 0x3C, 0x9,
+  0x72, 0x3, 0xE9, 0x69, 0xFF, 0x3C, 0x30, 0xF5, 0xFE, 0xC0, 0xFE,
+  0xC8, 0xC3, 0xA0, 0x0, 0x3, 0x3C, 0xF, 0x73, 0x17, 0x3C, 0xD,
+  0x72, 0x13, 0x8B, 0x1E, 0x2, 0x3, 0x75, 0xA, 0x43, 0x43, 0x43,
+  0x8A, 0x17, 0x43, 0x8A, 0x37, 0x87, 0xDA, 0xE9, 0x6A, 0x54, 0xA0,
+  0x1, 0x3, 0xA2, 0xFB, 0x2, 0x3C, 0x8, 0x74, 0x11, 0x8B, 0x1E,
+  0x2, 0x3, 0x89, 0x1E, 0xA3, 0x4, 0x8B, 0x1E, 0x4, 0x3, 0x89,
+  0x1E, 0xA5, 0x4, 0xC3, 0xBB, 0x2, 0x3, 0xE9, 0x9D, 0x54, 0xB2,
+  0x3, 0xB9, 0xB2, 0x2, 0xB9, 0xB2, 0x4, 0xB9, 0xB2, 0x8, 0xE8,
+  0x3A, 0x1F, 0xB9, 0xBE, 0x7, 0x51, 0x72, 0xE5, 0x2C, 0x41, 0x8A,
+  0xC8, 0x8A, 0xE8, 0xE8, 0x5, 0xFF, 0x3C, 0xEA, 0x75, 0xF, 0xE8,
+  0xFE, 0xFE, 0xE8, 0x21, 0x1F, 0x72, 0xD0, 0x2C, 0x41, 0x8A, 0xE8,
+  0xE8, 0xF2, 0xFE, 0x8A, 0xC5, 0x2A, 0xC1, 0x72, 0xC3, 0xFE, 0xC0,
+  0x5E, 0x87, 0xDE, 0x56, 0xBB, 0x60, 0x3, 0xB5, 0x0, 0x3, 0xD9,
+  0x88, 0x17, 0x43, 0xFE, 0xC8, 0x75, 0xF9, 0x5B, 0x8A, 0x7, 0x3C,
+  0x2C, 0x75, 0xA8, 0xE8, 0xCE, 0xFE, 0xEB, 0xB5, 0xE8, 0xC9, 0xFE,
+  0xE8, 0xB3, 0xE, 0x79, 0x9B, 0xB2, 0x5, 0xE9, 0x7A, 0xF7, 0x8A,
+  0x7, 0x3C, 0x2E, 0x8B, 0x16, 0x49, 0x3, 0x75, 0x3, 0xE9, 0xB2,
+  0xFE, 0x4B, 0xE8, 0xAE, 0xFE, 0x3C, 0xE, 0x74, 0x2, 0x3C, 0xD,
+  0x8B, 0x16, 0x2, 0x3, 0x75, 0x3, 0xE9, 0x9F, 0xFE, 0x32, 0xC0,
+  0xA2, 0x0, 0x3, 0x4B, 0xBA, 0x0, 0x0, 0xE8, 0x93, 0xFE, 0x72,
+  0x1, 0xC3, 0x53, 0x9F, 0x50, 0xBB, 0x98, 0x19, 0x3B, 0xDA, 0x72,
+  0x1B, 0x8A, 0xFE, 0x8A, 0xDA, 0x3, 0xDA, 0x3, 0xDB, 0x3, 0xDA,
+  0x3, 0xDB, 0x58, 0x9E, 0x2C, 0x30, 0x8A, 0xD0, 0xB6, 0x0, 0x3,
+  0xDA, 0x87, 0xDA, 0x5B, 0xEB, 0xD5, 0x58, 0x9E, 0x5B, 0xC3, 0x75,
+  0x3, 0xE9, 0x7C, 0x1C, 0x3C, 0xE, 0x74, 0x7, 0x3C, 0xD, 0x74,
+  0x3, 0xE9, 0xA3, 0x30, 0xE8, 0x75, 0x1C, 0xB9, 0xE8, 0xE, 0xEB,
+  0x1E, 0xB1, 0x3, 0xE8, 0x2, 0x1C, 0xE8, 0x95, 0xFF, 0x59, 0x53,
+  0x53, 0x8B, 0x1E, 0x2E, 0x0, 0x5E, 0x87, 0xDE, 0x56, 0xB0, 0x8D,
+  0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x51, 0xEB, 0x4, 0x51, 0xE8,
+  0x7B, 0xFF, 0xA0, 0x0, 0x3, 0x3C, 0xD, 0x87, 0xDA, 0x74, 0xBC,
+  0x3C, 0xE, 0x74, 0x3, 0xE9, 0xBE, 0xF6, 0x87, 0xDA, 0x53, 0x8B,
+  0x1E, 0xFE, 0x2, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0x51, 0x0, 0x43,
+  0x53, 0x8B, 0x1E, 0x2E, 0x0, 0x3B, 0xDA, 0x5B, 0x73, 0x3, 0xE8,
+  0x4F, 0xF9, 0x72, 0x3, 0xE8, 0x46, 0xF9, 0x73, 0xD, 0x49, 0xB0,
+  0xD, 0xA2, 0x3D, 0x3, 0x5B, 0xE8, 0xFC, 0x12, 0x8B, 0xD9, 0xC3,
+  0xB2, 0x8, 0xE9, 0xA3, 0xF6, 0xCD, 0x98, 0x75, 0xF6, 0xB6, 0xFF,
+  0xE8, 0xFA, 0xF5, 0x8B, 0xE3, 0x89, 0x1E, 0x45, 0x3, 0x3C, 0x8D,
+  0xB2, 0x3, 0x74, 0x3, 0xE9, 0x8B, 0xF6, 0x5B, 0x89, 0x1E, 0x2E,
+  0x0, 0xBB, 0xE8, 0xE, 0x5E, 0x87, 0xDE, 0x56, 0xB0, 0x5B, 0xB1,
+  0x3A, 0xEB, 0x2, 0xB1, 0x0, 0xB5, 0x0, 0x8A, 0xC1, 0x8A, 0xCD,
+  0x8A, 0xE8, 0x4B, 0xE8, 0xB0, 0xFD, 0xA, 0xC0, 0x74, 0xBE, 0x3A,
+  0xC5, 0x74, 0xBA, 0x43, 0x3C, 0x22, 0x74, 0xE9, 0xFE, 0xC0, 0x74,
+  0xEC, 0x2C, 0x8C, 0x75, 0xE7, 0x3A, 0xC5, 0x12, 0xC6, 0x8A, 0xF0,
+  0xEB, 0xDF, 0x58, 0x4, 0x3, 0xEB, 0x14, 0xE8, 0xDC, 0x25, 0xE8,
+  0x5F, 0x1C, 0xE7, 0x89, 0x16, 0x3B, 0x3, 0x52, 0xA0, 0xFB, 0x2,
+  0x50, 0xE8, 0x85, 0x5, 0x58, 0x5E, 0x87, 0xDE, 0x56, 0x8A, 0xE8,
+  0xA0, 0xFB, 0x2, 0x3A, 0xC5, 0x8A, 0xC5, 0x74, 0x6, 0xE8, 0x25,
+  0xC, 0xA0, 0xFB, 0x2, 0xBA, 0xA3, 0x4, 0x3C, 0x5, 0x72, 0x3,
+  0xBA, 0x9F, 0x4, 0x53, 0x3C, 0x3, 0x75, 0x31, 0x8B, 0x1E, 0xA3,
+  0x4, 0x53, 0x43, 0x8B, 0x17, 0x8B, 0x1E, 0x30, 0x0, 0x3B, 0xDA,
+  0x73, 0x11, 0x8B, 0x1E, 0x5C, 0x3, 0x3B, 0xDA, 0x5A, 0x73, 0x11,
+  0xBB, 0x2C, 0x3, 0x3B, 0xDA, 0x73, 0xA, 0xB0, 0x5A, 0xE8, 0xE6,
+  0x16, 0x87, 0xDA, 0xE8, 0x33, 0x14, 0xE8, 0xDE, 0x16, 0x5E, 0x87,
+  0xDE, 0x56, 0xE8, 0xBE, 0x52, 0x5A, 0x5B, 0xC3, 0x3C, 0xA7, 0x75,
+  0x32, 0xE8, 0x18, 0xFD, 0xE8, 0xEC, 0x1B, 0x89, 0xE8, 0x5F, 0xFE,
+  0xB, 0xD2, 0x74, 0xD, 0xE8, 0x4F, 0xF8, 0x8A, 0xF5, 0x8A, 0xD1,
+  0x5B, 0x72, 0x3, 0xE9, 0x13, 0xFF, 0x89, 0x16, 0x4D, 0x3, 0x72,
+  0xDA, 0xA0, 0x4F, 0x3, 0xA, 0xC0, 0x8A, 0xC2, 0x74, 0xD1, 0xA0,
+  0x28, 0x0, 0x8A, 0xD0, 0xE9, 0xCE, 0xF5, 0xE8, 0xE5, 0xC, 0x8A,
+  0x7, 0x8A, 0xE8, 0x3C, 0x8D, 0x74, 0x5, 0xE8, 0xB2, 0x1B, 0x89,
+  0x4B, 0x8A, 0xCA, 0xFE, 0xC9, 0x8A, 0xC5, 0x75, 0x3, 0xE9, 0xB9,
+  0xFC, 0xE8, 0x1A, 0xFE, 0x3C, 0x2C, 0x75, 0xA7, 0xEB, 0xEE, 0xA0,
+  0x4F, 0x3, 0xA, 0xC0, 0x75, 0x8, 0x33, 0xC0, 0xA3, 0x4D, 0x3,
+  0xE9, 0x66, 0xF5, 0xFE, 0xC0, 0xA2, 0x28, 0x0, 0x80, 0x3F, 0x83,
+  0x74, 0x12, 0xE8, 0xF7, 0xFD, 0x75, 0xC, 0xB, 0xD2, 0x74, 0x10,
+  0xE8, 0x73, 0xFE, 0x32, 0xC0, 0xA2, 0x4F, 0x3, 0xC3, 0xE8, 0x97,
+  0xFC, 0x75, 0xFA, 0xEB, 0x7, 0x32, 0xC0, 0xA2, 0x4F, 0x3, 0xFE,
+  0xC0, 0xA1, 0x47, 0x3, 0xA3, 0x2E, 0x0, 0x8B, 0x1E, 0x4B, 0x3,
+  0x75, 0xE5, 0x80, 0x3F, 0x0, 0x75, 0x3, 0x83, 0xC3, 0x4, 0x43,
+  0xE9, 0x17, 0x19, 0xE8, 0x70, 0xC, 0x75, 0xDA, 0xA, 0xC0, 0x75,
+  0x3, 0xE9, 0xA4, 0xFD, 0xE9, 0x20, 0xF5, 0xBA, 0xA, 0x0, 0x52,
+  0x74, 0x1F, 0xE8, 0x9D, 0xFD, 0x87, 0xDA, 0x5E, 0x87, 0xDE, 0x56,
+  0x74, 0x16, 0x87, 0xDA, 0xE8, 0x26, 0x1B, 0x2C, 0x8B, 0x16, 0x41,
+  0x3, 0x74, 0x8, 0xE8, 0x93, 0xFD, 0x74, 0x3, 0xE9, 0xE1, 0xF4,
+  0x87, 0xDA, 0x8A, 0xC7, 0xA, 0xC3, 0x75, 0x3, 0xE9, 0x71, 0xFD,
+  0x89, 0x1E, 0x41, 0x3, 0xA2, 0x3E, 0x3, 0x5B, 0x89, 0x1E, 0x3F,
+  0x3, 0x59, 0xE9, 0xDB, 0xF5, 0xE8, 0x2C, 0x4, 0x8A, 0x7, 0x3C,
+  0x2C, 0x75, 0x3, 0xE8, 0x19, 0xFC, 0x3C, 0x89, 0x74, 0x5, 0xE8,
+  0xE9, 0x1A, 0xCD, 0x4B, 0x53, 0xE8, 0xD2, 0x51, 0x5B, 0x74, 0x19,
+  0xE8, 0x6, 0xFC, 0x75, 0x1, 0xC3, 0x3C, 0xE, 0x75, 0x3, 0xE9,
+  0xCC, 0xFD, 0x3C, 0xD, 0x74, 0x3, 0xE9, 0xE0, 0xFB, 0x8B, 0x1E,
+  0x2, 0x3, 0xC3, 0xB6, 0x1, 0xE8, 0x29, 0xFE, 0xA, 0xC0, 0x74,
+  0xF6, 0xE8, 0xE4, 0xFB, 0x3C, 0xA1, 0x75, 0xF2, 0xFE, 0xCE, 0x75,
+  0xEE, 0xEB, 0xD1, 0xE8, 0x6A, 0x1, 0xEB, 0x3, 0xE8, 0x9B, 0x31,
+  0x4B, 0xE8, 0xCE, 0xFB, 0x75, 0x3, 0xE8, 0x1D, 0x19, 0x75, 0x3,
+  0xE9, 0x3F, 0x1, 0x3C, 0xD7, 0x75, 0x3, 0xE9, 0x6B, 0x27, 0x3C,
+  0xCE, 0x75, 0x3, 0xE9, 0xAB, 0x0, 0x3C, 0xD2, 0x75, 0x3, 0xE9,
+  0xA4, 0x0, 0x53, 0x3C, 0x2C, 0x74, 0x6D, 0x3C, 0x3B, 0x75, 0x3,
+  0xE9, 0x17, 0x1, 0x59, 0xE8, 0xA9, 0x3, 0x53, 0xE8, 0xA3, 0x7,
+  0x74, 0xF, 0xE8, 0x41, 0x5D, 0xE8, 0xC2, 0x12, 0xC6, 0x7, 0x20,
+  0x8B, 0x1E, 0xA3, 0x4, 0xFE, 0x7, 0xCD, 0x99, 0x8B, 0x1E, 0xA3,
+  0x4, 0x53, 0xE8, 0x39, 0x1C, 0x74, 0xD, 0xE8, 0x31, 0x1, 0x78,
+  0x3, 0xE9, 0x31, 0x0, 0xE8, 0x81, 0x45, 0xEB, 0x3, 0xA0, 0x29,
+  0x0, 0x8A, 0xE8, 0xFE, 0xC0, 0x74, 0x23, 0xE8, 0x1E, 0x1C, 0x74,
+  0x7, 0xE8, 0x66, 0x45, 0x8A, 0x7, 0xEB, 0x3, 0xE8, 0x68, 0x3B,
+  0x5B, 0x53, 0xA, 0xC0, 0x74, 0xE, 0x2, 0x7, 0xF5, 0x73, 0x4,
+  0xFE, 0xC8, 0x3A, 0xC5, 0x72, 0x3, 0xE8, 0x99, 0x18, 0x5B, 0xE8,
+  0xDE, 0x12, 0x5B, 0xE9, 0x6B, 0xFF, 0xCD, 0x9A, 0xB9, 0x32, 0x0,
+  0x8B, 0x1E, 0xE9, 0x4, 0x3, 0xD9, 0xE8, 0xE8, 0x1B, 0x8A, 0x7,
+  0x75, 0x18, 0xA0, 0x2A, 0x0, 0x8A, 0xE8, 0xE8, 0x32, 0x3B, 0x3C,
+  0xFF, 0x74, 0xC, 0x3A, 0xC5, 0x72, 0x3, 0xE8, 0x6C, 0x18, 0x72,
+  0x3, 0xE9, 0x87, 0x0, 0x2C, 0xE, 0x73, 0xFC, 0xF6, 0xD0, 0xEB,
+  0x72, 0x50, 0xE8, 0x7, 0xFB, 0xE8, 0xF1, 0xA, 0x58, 0x50, 0x3C,
+  0xD2, 0x74, 0x1, 0x4A, 0x8A, 0xC6, 0xA, 0xC0, 0x78, 0x3, 0xE9,
+  0x3, 0x0, 0xBA, 0x0, 0x0, 0x53, 0xE8, 0xA6, 0x1B, 0x74, 0xD,
+  0xE8, 0x9E, 0x0, 0x78, 0x3, 0xE9, 0x15, 0x0, 0xE8, 0xEE, 0x44,
+  0xEB, 0x3, 0xA0, 0x29, 0x0, 0x8A, 0xD8, 0xFE, 0xC0, 0x74, 0x7,
+  0xB7, 0x0, 0xE8, 0x7C, 0x51, 0x87, 0xDA, 0x5B, 0xE8, 0xA1, 0x19,
+  0x29, 0x4B, 0x58, 0x2C, 0xD2, 0x53, 0x74, 0x13, 0xB9, 0x32, 0x0,
+  0x8B, 0x1E, 0xE9, 0x4, 0x3, 0xD9, 0xE8, 0x6F, 0x1B, 0x8A, 0x7,
+  0x75, 0x3, 0xE8, 0xBE, 0x3A, 0xF6, 0xD0, 0x2, 0xC2, 0x72, 0x10,
+  0xFE, 0xC0, 0x74, 0x19, 0xE8, 0xF6, 0x17, 0x8A, 0xC2, 0xFE, 0xC8,
+  0x79, 0x3, 0xE9, 0xD, 0x0, 0xFE, 0xC0, 0x8A, 0xE8, 0xB0, 0x20,
+  0xE8, 0x18, 0x17, 0xFE, 0xCD, 0x75, 0xF9, 0x5B, 0xE8, 0x88, 0xFA,
+  0xE9, 0xBC, 0xFE, 0xCD, 0x9B, 0x32, 0xC0, 0x53, 0x52, 0x51, 0xE8,
+  0x86, 0x2C, 0x59, 0x5A, 0x32, 0xC0, 0x8A, 0xF8, 0x8A, 0xD8, 0x89,
+  0x1E, 0xE9, 0x4, 0x5B, 0xC3, 0x53, 0x32, 0xC0, 0x9F, 0x86, 0xC4,
+  0x50, 0x86, 0xC4, 0xE8, 0xE9, 0x2A, 0x74, 0x3, 0xE9, 0xE2, 0xF2,
+  0x53, 0xB9, 0x2E, 0x0, 0xB2, 0x2, 0xB6, 0xFD, 0x3, 0xD9, 0x88,
+  0x37, 0xB0, 0x0, 0x5B, 0xE9, 0xE6, 0x29, 0xE8, 0x33, 0x2E, 0xA,
+  0xC0, 0xC3, 0x3C, 0x85, 0x74, 0x3, 0xE9, 0xA2, 0x33, 0xE8, 0x11,
+  0x19, 0x85, 0x3C, 0x23, 0x75, 0x3, 0xE9, 0x28, 0x30, 0xE8, 0x30,
+  0x1D, 0xE8, 0x73, 0x0, 0xE8, 0x7A, 0x22, 0xE8, 0x44, 0x4F, 0x52,
+  0x53, 0xE8, 0xA7, 0x1C, 0x5A, 0x59, 0x73, 0x3, 0xE9, 0x45, 0x19,
+  0x51, 0x52, 0xB5, 0x0, 0xE8, 0x45, 0x11, 0x5B, 0xB0, 0x3, 0xE9,
+  0x93, 0xFC, 0x3F, 0x52, 0x65, 0x64, 0x6F, 0x20, 0x66, 0x72, 0x6F,
+  0x6D, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0xD, 0x0, 0x43, 0x8A,
+  0x7, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x92, 0xF2, 0x3C, 0x22, 0x75,
+  0xF2, 0xE9, 0x9B, 0x0, 0x5B, 0x5B, 0xEB, 0xC, 0xCD, 0x9C, 0xA0,
+  0x3A, 0x3, 0xA, 0xC0, 0x74, 0x3, 0xE9, 0x73, 0xF2, 0x59, 0xBB,
+  0x10, 0x15, 0xE8, 0xB, 0x66, 0x8B, 0x1E, 0x43, 0x3, 0xC3, 0xE8,
+  0x94, 0x2F, 0x53, 0xBB, 0xF6, 0x1, 0xE9, 0xE0, 0x0, 0x3C, 0x23,
+  0x74, 0xF2, 0xE8, 0xBE, 0x1C, 0xB9, 0x8C, 0x15, 0x51, 0x3C, 0x22,
+  0xB0, 0x0, 0xB0, 0xFF, 0xA2, 0x5F, 0x4, 0x75, 0xDF, 0xE8, 0xDB,
+  0x10, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0xA, 0x32, 0xC0, 0xA2, 0x5F,
+  0x4, 0xE8, 0x9D, 0xF9, 0xEB, 0x4, 0xE8, 0x6F, 0x18, 0x3B, 0x53,
+  0xE8, 0x30, 0x11, 0x5B, 0xC3, 0x53, 0xA0, 0x5F, 0x4, 0xA, 0xC0,
+  0x74, 0xA, 0xB0, 0x3F, 0xE8, 0xC, 0x16, 0xB0, 0x20, 0xE8, 0x7,
+  0x16, 0xE8, 0x2, 0x1C, 0x59, 0x73, 0x3, 0xE9, 0xA1, 0x18, 0x51,
+  0x32, 0xC0, 0xA2, 0x3A, 0x3, 0xC6, 0x7, 0x2C, 0x87, 0xDA, 0x5B,
+  0x53, 0x52, 0x52, 0x4B, 0xB0, 0x80, 0xA2, 0x39, 0x3, 0xE8, 0x5E,
+  0xF9, 0xE8, 0xA5, 0x22, 0x8A, 0x7, 0x4B, 0x3C, 0x28, 0x75, 0x20,
+  0x43, 0xB5, 0x0, 0xFE, 0xC5, 0xE8, 0x4C, 0xF9, 0x75, 0x3, 0xE9,
+  0xE8, 0xF1, 0x3C, 0x22, 0x75, 0x3, 0xE9, 0x45, 0xFF, 0x3C, 0x28,
+  0x74, 0xEB, 0x3C, 0x29, 0x75, 0xE9, 0xFE, 0xCD, 0x75, 0xE5, 0xE8,
+  0x31, 0xF9, 0x74, 0x7, 0x3C, 0x2C, 0x74, 0x3, 0xE9, 0xC9, 0xF1,
+  0x5E, 0x87, 0xDE, 0x56, 0x8A, 0x7, 0x3C, 0x2C, 0x74, 0x3, 0xE9,
+  0x31, 0xFF, 0xB0, 0x1, 0xA2, 0xA9, 0x4, 0xE8, 0x62, 0x0, 0xA0,
+  0xA9, 0x4, 0xFE, 0xC8, 0x74, 0x3, 0xE9, 0x1F, 0xFF, 0x53, 0xE8,
+  0xD, 0x5, 0x75, 0x3, 0xE8, 0x8C, 0x12, 0x5B, 0x4B, 0xE8, 0xFB,
+  0xF8, 0x5E, 0x87, 0xDE, 0x56, 0x8A, 0x7, 0x3C, 0x2C, 0x74, 0x8B,
+  0x5B, 0x4B, 0xE8, 0xEC, 0xF8, 0xA, 0xC0, 0x5B, 0x74, 0x3, 0xE9,
+  0xA, 0xFF, 0xC6, 0x7, 0x2C, 0xEB, 0x6, 0x53, 0x8B, 0x1E, 0x5E,
+  0x3, 0xD, 0x32, 0xC0, 0xA2, 0x3A, 0x3, 0x5E, 0x87, 0xDE, 0x56,
+  0xEB, 0x4, 0xE8, 0xA2, 0x17, 0x2C, 0xE8, 0x18, 0x21, 0x5E, 0x87,
+  0xDE, 0x56, 0x52, 0x8A, 0x7, 0x3C, 0x2C, 0x74, 0xA, 0xA0, 0x3A,
+  0x3, 0xA, 0xC0, 0x74, 0x3, 0xE9, 0x8B, 0x0, 0xD, 0x32, 0xC0,
+  0xA2, 0x52, 0x4, 0xE8, 0x62, 0x19, 0x74, 0x3, 0xE9, 0x8B, 0x2E,
+  0xE8, 0xA9, 0x4, 0x50, 0x75, 0x38, 0xE8, 0x9B, 0xF8, 0x8A, 0xF0,
+  0x8A, 0xE8, 0x3C, 0x22, 0x74, 0xE, 0xA0, 0x3A, 0x3, 0xA, 0xC0,
+  0x8A, 0xF0, 0x74, 0x2, 0xB6, 0x3A, 0xB5, 0x2C, 0x4B, 0xE8, 0xB6,
+  0xF, 0x58, 0x4, 0x3, 0x8A, 0xC8, 0xA0, 0x52, 0x4, 0xA, 0xC0,
+  0x75, 0x1, 0xC3, 0x8A, 0xC1, 0x87, 0xDA, 0xBB, 0xCA, 0x16, 0x5E,
+  0x87, 0xDE, 0x56, 0x52, 0xE9, 0xF0, 0xFA, 0xE8, 0x63, 0xF8, 0x58,
+  0x50, 0x3C, 0x5, 0xB9, 0x9B, 0x16, 0x51, 0x73, 0x3, 0xE9, 0xF9,
+  0x52, 0xE9, 0xFD, 0x52, 0x4B, 0xE8, 0x4F, 0xF8, 0x74, 0x7, 0x3C,
+  0x2C, 0x74, 0x3, 0xE9, 0x60, 0xFE, 0x5E, 0x87, 0xDE, 0x56, 0x4B,
+  0xE8, 0x3E, 0xF8, 0x74, 0x3, 0xE9, 0x6B, 0xFF, 0x5A, 0xA0, 0x3A,
+  0x3, 0xA, 0xC0, 0x87, 0xDA, 0x74, 0x3, 0xE9, 0x35, 0x17, 0x52,
+  0x5B, 0xE9, 0xA2, 0xFD, 0xE8, 0x62, 0xFA, 0xA, 0xC0, 0x75, 0x15,
+  0x43, 0x8A, 0x7, 0x43, 0xA, 0x7, 0xB2, 0x4, 0x75, 0x3, 0xE9,
+  0xCE, 0xF0, 0x43, 0x8B, 0x17, 0x43, 0x89, 0x16, 0x37, 0x3, 0xE8,
+  0x8, 0xF8, 0x3C, 0x84, 0x75, 0xDD, 0xE9, 0x4F, 0xFF, 0xE8, 0xD5,
+  0x16, 0xE7, 0xE9, 0x4, 0x0, 0xE8, 0xCE, 0x16, 0x28, 0x4B, 0xB6,
+  0x0, 0x52, 0xB1, 0x1, 0xE8, 0xA5, 0x15, 0xCD, 0x9D, 0xE8, 0xB2,
+  0x1, 0x32, 0xC0, 0xA2, 0xA8, 0x4, 0x89, 0x1E, 0x52, 0x3, 0x8B,
+  0x1E, 0x52, 0x3, 0x59, 0x8A, 0x7, 0x89, 0x1E, 0x31, 0x3, 0x3C,
+  0xE6, 0x73, 0x1, 0xC3, 0x3C, 0xE9, 0x72, 0x75, 0x2C, 0xE9, 0x8A,
+  0xD0, 0x75, 0xC, 0xA0, 0xFB, 0x2, 0x3C, 0x3, 0x8A, 0xC2, 0x75,
+  0x3, 0xE9, 0xD6, 0x10, 0x3C, 0xC, 0x73, 0xE5, 0xBB, 0x80, 0x3,
+  0xB6, 0x0, 0x3, 0xDA, 0x8A, 0xC5, 0x2E, 0x8A, 0x37, 0x3A, 0xC6,
+  0x73, 0xD5, 0x51, 0xB9, 0x3E, 0x17, 0x51, 0x8A, 0xC6, 0xCD, 0x9E,
+  0x3C, 0x7F, 0x74, 0x64, 0x3C, 0x51, 0x72, 0x6D, 0x24, 0xFE, 0x3C,
+  0x7A, 0x74, 0x67, 0xA0, 0xFB, 0x2, 0x2C, 0x3, 0x75, 0x3, 0xE9,
+  0x3D, 0xF0, 0xA, 0xC0, 0xFF, 0x36, 0xA3, 0x4, 0x79, 0x3, 0xE9,
+  0x11, 0x0, 0xFF, 0x36, 0xA5, 0x4, 0x7A, 0x3, 0xE9, 0x8, 0x0,
+  0xFF, 0x36, 0x9F, 0x4, 0xFF, 0x36, 0xA1, 0x4, 0x4, 0x3, 0x8A,
+  0xCA, 0x8A, 0xE8, 0x51, 0xB9, 0x23, 0x18, 0x51, 0x8B, 0x1E, 0x31,
+  0x3, 0xE9, 0x63, 0xFF, 0xB6, 0x0, 0x2C, 0xE6, 0x72, 0x34, 0x3C,
+  0x3, 0x73, 0x30, 0x3C, 0x1, 0xD0, 0xD0, 0x32, 0xC6, 0x3A, 0xC6,
+  0x8A, 0xF0, 0x73, 0x3, 0xE9, 0xDE, 0xEF, 0x89, 0x1E, 0x31, 0x3,
+  0xE8, 0x36, 0xF7, 0xEB, 0xE0, 0xE8, 0x65, 0x53, 0xE8, 0x37, 0x4C,
+  0xB9, 0x29, 0x65, 0xB6, 0x7F, 0xEB, 0xC9, 0x52, 0xE8, 0xB3, 0x53,
+  0x5A, 0x53, 0xB9, 0x31, 0x1B, 0xEB, 0xBE, 0x8A, 0xC5, 0x3C, 0x64,
+  0x72, 0x1, 0xC3, 0x51, 0x52, 0xBA, 0x4, 0x64, 0xBB, 0x3, 0x1B,
+  0x53, 0xE8, 0x11, 0x3, 0x74, 0x3, 0xE9, 0x76, 0xFF, 0x8B, 0x1E,
+  0xA3, 0x4, 0x53, 0xB9, 0xC8, 0x25, 0xEB, 0x9C, 0x59, 0x8A, 0xC1,
+  0xA2, 0xFC, 0x2, 0xA0, 0xFB, 0x2, 0x3A, 0xC5, 0x75, 0xD, 0x3C,
+  0x2, 0x74, 0x28, 0x3C, 0x4, 0x75, 0x3, 0xE9, 0x7F, 0x0, 0x73,
+  0x39, 0x8A, 0xF0, 0x8A, 0xC5, 0x3C, 0x8, 0x74, 0x2E, 0x8A, 0xC6,
+  0x3C, 0x8, 0x74, 0x57, 0x8A, 0xC5, 0x3C, 0x4, 0x74, 0x66, 0x8A,
+  0xC6, 0x3C, 0x3, 0x75, 0x3, 0xE9, 0x7C, 0xEF, 0x73, 0x65, 0xBB,
+  0xAA, 0x3, 0xB5, 0x0, 0x3, 0xD9, 0x3, 0xD9, 0x2E, 0x8A, 0xF,
+  0x43, 0x2E, 0x8A, 0x2F, 0x5A, 0x8B, 0x1E, 0xA3, 0x4, 0x51, 0xC3,
+  0xE8, 0xC, 0x53, 0xE8, 0x25, 0x4C, 0x5B, 0x89, 0x1E, 0xA1, 0x4,
+  0x5B, 0x89, 0x1E, 0x9F, 0x4, 0x59, 0x5A, 0xE8, 0x5A, 0x4B, 0xE8,
+  0xF7, 0x52, 0xBB, 0x96, 0x3, 0xA0, 0xFC, 0x2, 0xD0, 0xC0, 0x2,
+  0xC3, 0x8A, 0xD8, 0x12, 0xC7, 0x2A, 0xC3, 0x8A, 0xF8, 0x2E, 0x8B,
+  0x1F, 0xFF, 0xE3, 0x8A, 0xC5, 0x50, 0xE8, 0xF6, 0x4B, 0x58, 0xA2,
+  0xFB, 0x2, 0x3C, 0x4, 0x74, 0xD3, 0x5B, 0x89, 0x1E, 0xA3, 0x4,
+  0xEB, 0xD1, 0xE8, 0x97, 0x52, 0x59, 0x5A, 0xBB, 0xA0, 0x3, 0xEB,
+  0xCD, 0x5B, 0xE8, 0x61, 0x4B, 0xE8, 0x65, 0x4A, 0xE8, 0x28, 0x4B,
+  0x5B, 0x89, 0x1E, 0xA5, 0x4, 0x5B, 0x89, 0x1E, 0xA3, 0x4, 0xEB,
+  0xE5, 0x53, 0x87, 0xDA, 0xE8, 0x50, 0x4A, 0x5B, 0xE8, 0x45, 0x4B,
+  0xE8, 0x49, 0x4A, 0xE9, 0x3B, 0x4C, 0xE8, 0x33, 0xF6, 0x75, 0x3,
+  0xE9, 0xE4, 0xEE, 0x73, 0x3, 0xE9, 0xCC, 0x50, 0xE8, 0x4E, 0x16,
+  0x72, 0x3, 0xE9, 0xDB, 0x0, 0x3C, 0x20, 0x73, 0x3, 0xE9, 0x7F,
+  0xF6, 0xCD, 0x9F, 0xFE, 0xC0, 0x75, 0x3, 0xE9, 0x6A, 0x1, 0xFE,
+  0xC8, 0x3C, 0xE9, 0x74, 0xD5, 0x3C, 0xEA, 0x75, 0x3, 0xE9, 0xAF,
+  0x0, 0x3C, 0x22, 0x75, 0x3, 0xE9, 0x2D, 0xD, 0x3C, 0xD3, 0x75,
+  0x3, 0xE9, 0xEC, 0x1, 0x3C, 0x26, 0x75, 0x3, 0xE9, 0xD1, 0x0,
+  0x3C, 0xD5, 0x75, 0xC, 0xE8, 0xE8, 0xF5, 0xA0, 0x28, 0x0, 0x53,
+  0xE8, 0x43, 0x2, 0x5B, 0xC3, 0x3C, 0xD4, 0x75, 0xD, 0xE8, 0xD8,
+  0xF5, 0x53, 0x8B, 0x1E, 0x47, 0x3, 0xE8, 0xF7, 0x4A, 0x5B, 0xC3,
+  0x3C, 0xDA, 0x75, 0x2E, 0xE8, 0xC7, 0xF5, 0xE8, 0x9B, 0x14, 0x28,
+  0x3C, 0x23, 0x75, 0xD, 0xE8, 0xB8, 0x5, 0x53, 0xE8, 0x40, 0x26,
+  0x87, 0xDA, 0x5B, 0xE9, 0x3, 0x0, 0xE8, 0xF9, 0x1E, 0xE8, 0x83,
+  0x14, 0x29, 0x53, 0x87, 0xDA, 0xB, 0xDB, 0x75, 0x3, 0xE9, 0xDD,
+  0xF6, 0xE8, 0x8D, 0x4B, 0x5B, 0xC3, 0x3C, 0xD0, 0x75, 0x3, 0xE9,
+  0x0, 0x2, 0x3C, 0xD8, 0x75, 0x3, 0xE9, 0x8B, 0x10, 0x3C, 0xC8,
+  0x75, 0x3, 0xE9, 0xD0, 0x3B, 0x3C, 0xDC, 0x75, 0x3, 0xE9, 0x4C,
+  0x2E, 0x3C, 0xDE, 0x75, 0x3, 0xE9, 0xF9, 0x12, 0x3C, 0xD6, 0x75,
+  0x3, 0xE9, 0x70, 0xF, 0x3C, 0x85, 0x75, 0x3, 0xE9, 0x38, 0x2A,
+  0x3C, 0xDB, 0x75, 0x3, 0xE9, 0xA4, 0x3B, 0x3C, 0xD1, 0x75, 0x3,
+  0xE9, 0x7E, 0x2, 0xE8, 0x60, 0xFD, 0xE8, 0x2E, 0x14, 0x29, 0xC3,
+  0xB6, 0x7D, 0xE8, 0x5D, 0xFD, 0x8B, 0x1E, 0x52, 0x3, 0x53, 0xE8,
+  0xD6, 0x63, 0x5B, 0xC3, 0xE8, 0x94, 0x1D, 0x53, 0x87, 0xDA, 0x89,
+  0x1E, 0xA3, 0x4, 0xE8, 0x41, 0x1, 0x74, 0x3, 0xE8, 0xAF, 0x4A,
+  0x5B, 0xC3, 0x8A, 0x7, 0x3C, 0x61, 0x72, 0xF9, 0x3C, 0x7B, 0x73,
+  0xF5, 0x24, 0x5F, 0xC3, 0x3C, 0x26, 0x74, 0x3, 0xE9, 0x6C, 0xF6,
+  0xBA, 0x0, 0x0, 0xE8, 0x18, 0xF5, 0xE8, 0xE5, 0xFF, 0x3C, 0x4F,
+  0x74, 0x39, 0x3C, 0x48, 0x75, 0x34, 0xB5, 0x5, 0x43, 0x8A, 0x7,
+  0xE8, 0xD5, 0xFF, 0xE8, 0x2A, 0x15, 0x87, 0xDA, 0x73, 0xA, 0x3C,
+  0x3A, 0x73, 0x4D, 0x2C, 0x30, 0x72, 0x49, 0xEB, 0x6, 0x3C, 0x47,
+  0x73, 0x43, 0x2C, 0x37, 0x3, 0xDB, 0x3, 0xDB, 0x3, 0xDB, 0x3,
+  0xDB, 0xA, 0xC3, 0x8A, 0xD8, 0x87, 0xDA, 0xFE, 0xCD, 0x75, 0xD1,
+  0xE9, 0x8C, 0xED, 0x4B, 0xE8, 0xD5, 0xF4, 0x87, 0xDA, 0x73, 0x24,
+  0x3C, 0x38, 0x72, 0x3, 0xE9, 0x6B, 0xED, 0xB9, 0xD0, 0x7, 0x51,
+  0x3, 0xDB, 0x72, 0x9C, 0x3, 0xDB, 0x72, 0x98, 0x3, 0xDB, 0x72,
+  0x94, 0x59, 0xB5, 0x0, 0x2C, 0x30, 0x8A, 0xC8, 0x3, 0xD9, 0x87,
+  0xDA, 0xEB, 0xD5, 0xE8, 0x99, 0x4A, 0x87, 0xDA, 0xC3, 0x43, 0x8A,
+  0x7, 0x2C, 0x81, 0x3C, 0x7, 0x75, 0xE, 0x53, 0xE8, 0x9A, 0xF4,
+  0x3C, 0x28, 0x5B, 0x74, 0x3, 0xE9, 0xE0, 0x49, 0xB0, 0x7, 0xB5,
+  0x0, 0xD0, 0xC0, 0x8A, 0xC8, 0x51, 0xE8, 0x86, 0xF4, 0x8A, 0xC1,
+  0x3C, 0x5, 0x73, 0x22, 0xE8, 0x83, 0xFC, 0xE8, 0x51, 0x13, 0x2C,
+  0xE8, 0x94, 0x49, 0x87, 0xDA, 0x8B, 0x1E, 0xA3, 0x4, 0x5E, 0x87,
+  0xDE, 0x56, 0x53, 0x87, 0xDA, 0xE8, 0x65, 0x4, 0x87, 0xDA, 0x5E,
+  0x87, 0xDE, 0x56, 0xEB, 0x21, 0xE8, 0xFE, 0xFE, 0x5E, 0x87, 0xDE,
+  0x56, 0x8A, 0xC3, 0x3C, 0xC, 0x72, 0xB, 0x3C, 0x1B, 0xCD, 0xA1,
+  0x53, 0x73, 0x3, 0xE8, 0x7B, 0x50, 0x5B, 0xBA, 0xD5, 0x19, 0x52,
+  0xB0, 0x1, 0xA2, 0xA8, 0x4, 0xB9, 0xB9, 0x0, 0xCD, 0xA0, 0x3,
+  0xD9, 0x2E, 0xFF, 0x27, 0xFE, 0xCE, 0x3C, 0xEA, 0x74, 0x85, 0x3C,
+  0x2D, 0x74, 0x81, 0xFE, 0xC6, 0x3C, 0x2B, 0x75, 0x1, 0xC3, 0x3C,
+  0xE9, 0x74, 0xFB, 0x9F, 0x4B, 0x9E, 0xC3, 0xFE, 0xC0, 0x12, 0xC0,
+  0x59, 0x22, 0xC5, 0x4, 0xFF, 0x1A, 0xC0, 0xE8, 0xF8, 0x49, 0xEB,
+  0xF, 0xB6, 0x5A, 0xE8, 0x12, 0xFC, 0xE8, 0x92, 0x50, 0xF7, 0xD3,
+  0x89, 0x1E, 0xA3, 0x4, 0x59, 0xE9, 0x19, 0xFC, 0xA0, 0xFB, 0x2,
+  0x3C, 0x8, 0xFE, 0xC8, 0xFE, 0xC8, 0xFE, 0xC8, 0xC3, 0x8A, 0xC5,
+  0x50, 0xE8, 0x76, 0x50, 0x58, 0x5A, 0x3C, 0x7A, 0x75, 0x3, 0xE9,
+  0x89, 0x4A, 0x3C, 0x7B, 0x75, 0x3, 0xE9, 0x66, 0x48, 0xB9, 0xC,
+  0x65, 0x51, 0x3C, 0x46, 0x75, 0x3, 0xB, 0xDA, 0xC3, 0x3C, 0x50,
+  0x75, 0x3, 0x23, 0xDA, 0xC3, 0x3C, 0x3C, 0x75, 0x3, 0x33, 0xDA,
+  0xC3, 0x3C, 0x32, 0x75, 0x5, 0x33, 0xDA, 0xF7, 0xD3, 0xC3, 0xF7,
+  0xD3, 0x23, 0xDA, 0xF7, 0xD3, 0xC3, 0x2B, 0xDA, 0xE9, 0xCF, 0x48,
+  0xA0, 0x63, 0x0, 0xEB, 0x3, 0xE8, 0xAF, 0x33, 0xFE, 0xC0, 0x8A,
+  0xD8, 0x32, 0xC0, 0x8A, 0xF8, 0xE9, 0x84, 0x49, 0xE8, 0x2E, 0x0,
+  0x52, 0xE8, 0x31, 0xFE, 0x5E, 0x87, 0xDE, 0x56, 0x8B, 0x17, 0x80,
+  0xFA, 0xFF, 0x75, 0x3, 0xE9, 0xBC, 0xF4, 0xE, 0xBB, 0x7, 0x65,
+  0x53, 0xFF, 0x36, 0x50, 0x3, 0x52, 0xA0, 0xFB, 0x2, 0x50, 0x3C,
+  0x3, 0x75, 0x3, 0xE8, 0xF7, 0xC, 0x58, 0x87, 0xDA, 0xBB, 0xA3,
+  0x4, 0xCB, 0xE8, 0x61, 0xF3, 0xB9, 0x0, 0x0, 0x3C, 0x1B, 0x73,
+  0x10, 0x3C, 0x11, 0x72, 0xC, 0xE8, 0x53, 0xF3, 0xA0, 0x2, 0x3,
+  0xA, 0xC0, 0xD0, 0xD0, 0x8A, 0xC8, 0x87, 0xDA, 0xBB, 0x12, 0x0,
+  0x3, 0xD9, 0x87, 0xDA, 0xC3, 0xE8, 0xD9, 0xFF, 0x52, 0xE8, 0x10,
+  0x12, 0xE7, 0xE8, 0xC2, 0x6, 0x5E, 0x87, 0xDE, 0x56, 0x89, 0x17,
+  0x5B, 0xC3, 0x3C, 0xD0, 0x74, 0xE9, 0x3C, 0xD1, 0x74, 0x1C, 0xE8,
+  0xF9, 0x11, 0x53, 0xE8, 0xF5, 0x11, 0x45, 0xE8, 0xF1, 0x11, 0x47,
+  0x8C, 0xDA, 0x74, 0x7, 0xE8, 0xE9, 0x11, 0xE7, 0xE8, 0x9B, 0x6,
+  0x89, 0x16, 0x50, 0x3, 0xC3, 0xE8, 0xF3, 0x1, 0xE8, 0xE0, 0x1,
+  0x87, 0xDA, 0x89, 0x17, 0x87, 0xDA, 0x8A, 0x7, 0x3C, 0x28, 0x74,
+  0x3, 0xE9, 0x32, 0xF5, 0xE8, 0xF1, 0xF2, 0xE8, 0x3F, 0x1B, 0x8A,
+  0x7, 0x3C, 0x29, 0x75, 0x3, 0xE9, 0x23, 0xF5, 0xE8, 0xB9, 0x11,
+  0x2C, 0xEB, 0xEE, 0xE8, 0xC9, 0x1, 0xA0, 0xFB, 0x2, 0xA, 0xC0,
+  0x50, 0x89, 0x1E, 0x52, 0x3, 0x87, 0xDA, 0x8B, 0x1F, 0xB, 0xDB,
+  0x75, 0x3, 0xE9, 0x74, 0xEB, 0x8A, 0x7, 0x3C, 0x28, 0x74, 0x3,
+  0xE9, 0xCE, 0x0, 0xE8, 0xBB, 0xF2, 0x89, 0x1E, 0x31, 0x3, 0x87,
+  0xDA, 0x8B, 0x1E, 0x52, 0x3, 0xE8, 0x85, 0x11, 0x28, 0x32, 0xC0,
+  0x50, 0x53, 0x87, 0xDA, 0xB0, 0x80, 0xA2, 0x39, 0x3, 0xE8, 0xF0,
+  0x1A, 0x87, 0xDA, 0x5E, 0x87, 0xDE, 0x56, 0xA0, 0xFB, 0x2, 0x50,
+  0x52, 0xE8, 0x9B, 0xFA, 0x89, 0x1E, 0x52, 0x3, 0x5B, 0x89, 0x1E,
+  0x31, 0x3, 0x58, 0xE8, 0x41, 0x1, 0xB1, 0x4, 0xE8, 0x37, 0x10,
+  0xBB, 0xF8, 0xFF, 0x3, 0xDC, 0x8B, 0xE3, 0xE8, 0xF9, 0x47, 0xA0,
+  0xFB, 0x2, 0x50, 0x8B, 0x1E, 0x52, 0x3, 0x8A, 0x7, 0x3C, 0x29,
+  0x74, 0x13, 0xE8, 0x3B, 0x11, 0x2C, 0x53, 0x8B, 0x1E, 0x31, 0x3,
+  0xE8, 0x32, 0x11, 0x2C, 0xEB, 0xB1, 0x58, 0xA2, 0xE4, 0x3, 0x58,
+  0xA, 0xC0, 0x74, 0x4E, 0xA2, 0xFB, 0x2, 0xBB, 0x0, 0x0, 0x3,
+  0xDC, 0xE8, 0xBF, 0x47, 0xBB, 0x8, 0x0, 0x3, 0xDC, 0x8B, 0xE3,
+  0x5A, 0xB3, 0x3, 0xFE, 0xC3, 0x4A, 0x8B, 0xF2, 0xAC, 0xA, 0xC0,
+  0x78, 0xF6, 0x4A, 0x4A, 0x4A, 0xA0, 0xFB, 0x2, 0x2, 0xC3, 0x8A,
+  0xE8, 0xA0, 0xE4, 0x3, 0x8A, 0xC8, 0x2, 0xC5, 0x3C, 0x64, 0x72,
+  0x3, 0xE9, 0x54, 0xF3, 0x50, 0x8A, 0xC3, 0xB5, 0x0, 0xBB, 0xE6,
+  0x3, 0x3, 0xD9, 0x8A, 0xC8, 0xE8, 0xDF, 0x0, 0xB9, 0xC5, 0x1C,
+  0x51, 0x51, 0xE9, 0x99, 0xF4, 0x8B, 0x1E, 0x52, 0x3, 0xE8, 0xFA,
+  0xF1, 0x53, 0x8B, 0x1E, 0x31, 0x3, 0xE8, 0xC9, 0x10, 0x29, 0xB0,
+  0x52, 0x89, 0x1E, 0x31, 0x3, 0xA0, 0x7C, 0x3, 0x4, 0x4, 0x50,
+  0xD0, 0xC8, 0x8A, 0xC8, 0xE8, 0x96, 0xF, 0x58, 0x8A, 0xC8, 0xF6,
+  0xD0, 0xFE, 0xC0, 0x8A, 0xD8, 0xB7, 0xFF, 0x3, 0xDC, 0x8B, 0xE3,
+  0x53, 0xBA, 0x7A, 0x3, 0xE8, 0x9E, 0x0, 0x5B, 0x89, 0x1E, 0x7A,
+  0x3, 0x8B, 0x1E, 0xE4, 0x3, 0x89, 0x1E, 0x7C, 0x3, 0x8B, 0xCB,
+  0xBB, 0x7E, 0x3, 0xBA, 0xE6, 0x3, 0xE8, 0x86, 0x0, 0x8A, 0xF8,
+  0x8A, 0xD8, 0x89, 0x1E, 0xE4, 0x3, 0x8B, 0x1E, 0x50, 0x4, 0x43,
+  0x89, 0x1E, 0x50, 0x4, 0x8A, 0xC7, 0xA, 0xC3, 0xA2, 0x4D, 0x4,
+  0x8B, 0x1E, 0x31, 0x3, 0xE8, 0x90, 0xF9, 0x4B, 0xE8, 0x8D, 0xF1,
+  0x74, 0x3, 0xE9, 0x29, 0xEA, 0xE8, 0x8D, 0xFD, 0x75, 0x11, 0xBA,
+  0x2C, 0x3, 0x8B, 0x1E, 0xA3, 0x4, 0x3B, 0xDA, 0x72, 0x6, 0xE8,
+  0x7C, 0x8, 0xE8, 0xE6, 0x8, 0x8B, 0x1E, 0x7A, 0x3, 0x8A, 0xF7,
+  0x8A, 0xD3, 0x43, 0x43, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0x41, 0x41,
+  0x41, 0x41, 0xBB, 0x7A, 0x3, 0xE8, 0x2F, 0x0, 0x87, 0xDA, 0x8B,
+  0xE3, 0x8B, 0x1E, 0x50, 0x4, 0x4B, 0x89, 0x1E, 0x50, 0x4, 0x8A,
+  0xC7, 0xA, 0xC3, 0xA2, 0x4D, 0x4, 0x5B, 0x58, 0x53, 0x24, 0x7,
+  0xBB, 0x8C, 0x3, 0x8A, 0xC8, 0xB5, 0x0, 0x3, 0xD9, 0xE8, 0xFC,
+  0xFC, 0x5B, 0xC3, 0x8B, 0xF2, 0xAC, 0x88, 0x7, 0x43, 0x42, 0x49,
+  0x8A, 0xC5, 0xA, 0xC1, 0x75, 0xF2, 0xC3, 0x53, 0x8B, 0x1E, 0x2E,
+  0x0, 0x43, 0xB, 0xDB, 0x5B, 0x75, 0xF4, 0xB2, 0xC, 0xE9, 0xCE,
+  0xE9, 0xE8, 0xE7, 0xF, 0xD1, 0xB0, 0x80, 0xA2, 0x39, 0x3, 0xA,
+  0x7, 0x8A, 0xC8, 0xE9, 0x5B, 0x19, 0x3C, 0x7E, 0x74, 0x3, 0xE9,
+  0x9D, 0xE9, 0x43, 0x8A, 0x7, 0x43, 0x3C, 0x83, 0x75, 0x3, 0xE9,
+  0xA4, 0xC, 0x3C, 0xA0, 0x75, 0x3, 0xE9, 0xAF, 0x37, 0x3C, 0xA2,
+  0x75, 0x3, 0xE9, 0xC0, 0x38, 0xE9, 0x81, 0xE9, 0xE8, 0x75, 0x4,
+  0x87, 0xDA, 0xEC, 0xE9, 0x39, 0xFD, 0xE8, 0x61, 0x4, 0x52, 0xE8,
+  0xA7, 0xF, 0x2C, 0xE8, 0xCB, 0x0, 0x5A, 0xC3, 0xE8, 0xF0, 0xFF,
+  0xEE, 0xC3, 0xE8, 0xEB, 0xFF, 0x52, 0x50, 0xB2, 0x0, 0x4B, 0xE8,
+  0xBA, 0xF0, 0x74, 0x7, 0xE8, 0x8C, 0xF, 0x2C, 0xE8, 0xB0, 0x0,
+  0x58, 0x8A, 0xF0, 0x5E, 0x87, 0xDE, 0x56, 0xA0, 0x5E, 0x0, 0xA,
+  0xC0, 0x75, 0xB, 0x87, 0xDA, 0xEC, 0x87, 0xDA, 0x32, 0xC2, 0x22,
+  0xC6, 0x74, 0xEE, 0x5B, 0xC3, 0xE9, 0x34, 0xE9, 0x3C, 0x23, 0x74,
+  0x3C, 0xE8, 0x96, 0xF8, 0xE8, 0x91, 0xFC, 0x75, 0x58, 0xE8, 0x7D,
+  0x20, 0x8A, 0xC6, 0xB6, 0x0, 0xF6, 0xD0, 0xA, 0xC0, 0x79, 0x3,
+  0xE9, 0xB3, 0xF1, 0x8A, 0xD0, 0x52, 0xE8, 0x48, 0xF, 0x2C, 0xE8,
+  0x6C, 0x0, 0x5A, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x53, 0x52,
+  0x8A, 0xC2, 0x2, 0xC0, 0x8A, 0xD0, 0xB0, 0x14, 0x9F, 0x86, 0xC4,
+  0x50, 0x86, 0xC4, 0xE9, 0x8, 0x20, 0xE8, 0x50, 0xF0, 0xE8, 0x4C,
+  0x0, 0x50, 0xE8, 0x20, 0xF, 0x2C, 0xE8, 0x44, 0x0, 0x58, 0x53,
+  0x52, 0xE8, 0xC7, 0x20, 0xE8, 0x32, 0x3A, 0xA, 0xC0, 0x79, 0x3,
+  0xE9, 0x71, 0xF1, 0x43, 0x5A, 0x88, 0x17, 0x5B, 0xC3, 0xE8, 0x2E,
+  0x0, 0xE8, 0xB8, 0x33, 0xA2, 0x29, 0x0, 0x2C, 0xE, 0x73, 0xFC,
+  0x4, 0x1C, 0xF6, 0xD0, 0xFE, 0xC0, 0x2, 0xC2, 0xA2, 0x2A, 0x0,
+  0xC3, 0xE8, 0x13, 0xF0, 0xE8, 0x1A, 0xF8, 0x53, 0xE8, 0x9C, 0x4C,
+  0x87, 0xDA, 0x5B, 0x8A, 0xC6, 0xA, 0xC0, 0xC3, 0xE8, 0x1, 0xF0,
+  0xE8, 0x8, 0xF8, 0xE8, 0xEB, 0xFF, 0x74, 0x3, 0xE9, 0x32, 0xF1,
+  0x4B, 0xE8, 0xF2, 0xEF, 0x8A, 0xC2, 0xC3, 0xE8, 0x7F, 0xF5, 0x4B,
+  0xE8, 0xE8, 0xEF, 0xCD, 0xA2, 0x59, 0xE8, 0xF2, 0xEA, 0x51, 0xE8,
+  0x19, 0x28, 0x8B, 0x1E, 0x3B, 0x3, 0x4B, 0xE8, 0xD6, 0xEF, 0x74,
+  0xE, 0xE8, 0xA8, 0xE, 0x2C, 0xE8, 0xC3, 0x1F, 0xB2, 0x2, 0x32,
+  0xC0, 0xE8, 0x96, 0x21, 0xBB, 0xFF, 0xFF, 0x89, 0x1E, 0x2E, 0x0,
+  0xE8, 0x75, 0x10, 0x75, 0x5, 0xB0, 0x1, 0xA2, 0x6F, 0x0, 0x5B,
+  0x5A, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0x43, 0x8A, 0xC5, 0xA, 0xC1,
+  0x75, 0x3, 0xE9, 0x3D, 0xE9, 0xE8, 0x90, 0xE0, 0x75, 0x3, 0xE8,
+  0x7, 0xD, 0x51, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0x43, 0x51, 0x5E,
+  0x87, 0xDE, 0x56, 0x87, 0xDA, 0x3B, 0xDA, 0x59, 0x73, 0x3, 0xE9,
+  0x1E, 0xE9, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0x51, 0x87, 0xDA, 0x89,
+  0x1E, 0x49, 0x3, 0xE8, 0xAA, 0x45, 0x5B, 0x8A, 0x7, 0x3C, 0x9,
+  0x74, 0x5, 0xB0, 0x20, 0xE8, 0xF3, 0xB, 0xE8, 0x18, 0x0, 0xBB,
+  0xF7, 0x1, 0xE8, 0x5, 0x0, 0xE8, 0xB3, 0xC, 0xEB, 0x97, 0x8A,
+  0x7, 0xA, 0xC0, 0x75, 0x1, 0xC3, 0xE8, 0x69, 0x17, 0x43, 0xEB,
+  0xF3, 0xB9, 0xF7, 0x1, 0xB6, 0xFF, 0x32, 0xC0, 0xA2, 0xFC, 0x2,
+  0x32, 0xC0, 0xA2, 0x5E, 0x4, 0xE8, 0x79, 0x27, 0xEB, 0x6, 0x41,
+  0x43, 0xFE, 0xCE, 0x74, 0xDF, 0x8A, 0x7, 0xA, 0xC0, 0x8B, 0xF9,
+  0xAA, 0x74, 0xD6, 0x3C, 0xB, 0x72, 0x28, 0x3C, 0x20, 0x8A, 0xD0,
+  0x72, 0x38, 0x3C, 0x22, 0x75, 0xA, 0xA0, 0xFC, 0x2, 0x34, 0x1,
+  0xA2, 0xFC, 0x2, 0xB0, 0x22, 0x3C, 0x3A, 0x75, 0x10, 0xA0, 0xFC,
+  0x2, 0xD0, 0xD8, 0x72, 0x7, 0xD0, 0xD0, 0x24, 0xFD, 0xA2, 0xFC,
+  0x2, 0xB0, 0x3A, 0xA, 0xC0, 0x79, 0x3, 0xE9, 0x3C, 0x0, 0x8A,
+  0xD0, 0x3C, 0x2E, 0x74, 0x9, 0xE8, 0x57, 0x1, 0x73, 0x4, 0x32,
+  0xC0, 0xEB, 0x18, 0xA0, 0x5E, 0x4, 0xA, 0xC0, 0x74, 0xF, 0xFE,
+  0xC0, 0x75, 0xB, 0xB0, 0x20, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE,
+  0x75, 0x1, 0xC3, 0xB0, 0x1, 0xA2, 0x5E, 0x4, 0x8A, 0xC2, 0x3C,
+  0xB, 0x72, 0x7, 0x3C, 0x20, 0x73, 0x3, 0xE9, 0x37, 0x1, 0x8B,
+  0xF9, 0xAA, 0xEB, 0x82, 0xA0, 0xFC, 0x2, 0xD0, 0xD8, 0x72, 0x43,
+  0xD0, 0xD8, 0xD0, 0xD8, 0x73, 0x52, 0x8A, 0x7, 0x3C, 0xD9, 0x53,
+  0x51, 0xBB, 0xA5, 0x20, 0x53, 0x75, 0xCF, 0x49, 0x8B, 0xF1, 0xAC,
+  0x3C, 0x4D, 0x75, 0xC7, 0x49, 0x8B, 0xF1, 0xAC, 0x3C, 0x45, 0x75,
+  0xBF, 0x49, 0x8B, 0xF1, 0xAC, 0x3C, 0x52, 0x75, 0xB7, 0x49, 0x8B,
+  0xF1, 0xAC, 0x3C, 0x3A, 0x75, 0xAF, 0x58, 0x58, 0x5B, 0xFE, 0xC6,
+  0xFE, 0xC6, 0xFE, 0xC6, 0xFE, 0xC6, 0xEB, 0x2D, 0x59, 0x5B, 0x8A,
+  0x7, 0xE9, 0x35, 0xFF, 0xA0, 0xFC, 0x2, 0xC, 0x2, 0xA2, 0xFC,
+  0x2, 0x32, 0xC0, 0xC3, 0xA0, 0xFC, 0x2, 0xC, 0x4, 0xEB, 0xF3,
+  0xD0, 0xD0, 0x72, 0xE7, 0x8A, 0x7, 0x3C, 0x84, 0x75, 0x3, 0xE8,
+  0xE1, 0xFF, 0x3C, 0x8F, 0x75, 0x3, 0xE8, 0xE5, 0xFF, 0x8A, 0x7,
+  0xFE, 0xC0, 0x8A, 0x7, 0x75, 0x5, 0x43, 0x8A, 0x7, 0x24, 0x7F,
+  0x43, 0x3C, 0xA1, 0x75, 0x3, 0xE8, 0xF8, 0x43, 0x3C, 0xB1, 0x75,
+  0xA, 0x8A, 0x7, 0x43, 0x3C, 0xE9, 0xB0, 0xB1, 0x74, 0x1, 0x4B,
+  0x53, 0x51, 0x52, 0xCD, 0xA3, 0xBB, 0x36, 0x1, 0x8A, 0xE8, 0xB1,
+  0x40, 0xFE, 0xC1, 0x43, 0x8A, 0xF7, 0x8A, 0xD3, 0x2E, 0x8A, 0x7,
+  0xA, 0xC0, 0x74, 0xF2, 0x9F, 0x43, 0x9E, 0x79, 0xF4, 0x2E, 0x8A,
+  0x7, 0x3A, 0xC5, 0x75, 0xE8, 0x87, 0xDA, 0x3C, 0xD0, 0x74, 0x2,
+  0x3C, 0xD1, 0x8A, 0xC1, 0x5A, 0x59, 0x8A, 0xD0, 0x75, 0xC, 0xA0,
+  0x5E, 0x4, 0xA, 0xC0, 0xB0, 0x0, 0xA2, 0x5E, 0x4, 0xEB, 0x15,
+  0x3C, 0x5B, 0x75, 0x7, 0x32, 0xC0, 0xA2, 0x5E, 0x4, 0xEB, 0x1D,
+  0xA0, 0x5E, 0x4, 0xA, 0xC0, 0xB0, 0xFF, 0xA2, 0x5E, 0x4, 0x74,
+  0xD, 0xB0, 0x20, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE, 0x75, 0x3,
+  0xE9, 0xA4, 0x5, 0x8A, 0xC2, 0xEB, 0x6, 0x2E, 0x8A, 0x7, 0x43,
+  0x8A, 0xD0, 0x24, 0x7F, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE, 0x75,
+  0x3, 0xE9, 0x8D, 0x5, 0xA, 0xC2, 0x79, 0xE9, 0x3C, 0xA8, 0x75,
+  0x5, 0x32, 0xC0, 0xA2, 0x5E, 0x4, 0x5B, 0xE9, 0x64, 0xFE, 0xE8,
+  0xBF, 0xD, 0x72, 0x1, 0xC3, 0x3C, 0x30, 0x72, 0xFB, 0x3C, 0x3A,
+  0xF5, 0xC3, 0x4B, 0xE8, 0x88, 0xED, 0x52, 0x51, 0x50, 0xE8, 0x21,
+  0xEE, 0x58, 0xB9, 0xB5, 0x21, 0x51, 0x3C, 0xB, 0x75, 0x3, 0xE9,
+  0x60, 0x42, 0x3C, 0xC, 0x75, 0x3, 0xE9, 0x63, 0x42, 0x8B, 0x1E,
+  0x2, 0x3, 0xE9, 0x13, 0x4F, 0x59, 0x5A, 0xA0, 0x0, 0x3, 0xB2,
+  0x4F, 0x3C, 0xB, 0x74, 0x6, 0x3C, 0xC, 0xB2, 0x48, 0x75, 0x14,
+  0xB0, 0x26, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE, 0x74, 0xC0, 0x8A,
+  0xC2, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE, 0x74, 0xB6, 0xA0, 0x1,
+  0x3, 0x3C, 0x4, 0xB2, 0x0, 0x72, 0x6, 0xB2, 0x21, 0x74, 0x2,
+  0xB2, 0x23, 0x8A, 0x7, 0x3C, 0x20, 0x75, 0x3, 0xE8, 0x52, 0x43,
+  0x8A, 0x7, 0x43, 0xA, 0xC0, 0x74, 0x2A, 0x8B, 0xF9, 0xAA, 0x41,
+  0xFE, 0xCE, 0x74, 0x8F, 0xA0, 0x1, 0x3, 0x3C, 0x4, 0x72, 0xEA,
+  0x9F, 0x49, 0x9E, 0x8B, 0xF1, 0xAC, 0x9F, 0x41, 0x9E, 0x75, 0x4,
+  0x3C, 0x2E, 0x74, 0x8, 0x3C, 0x44, 0x74, 0x4, 0x3C, 0x45, 0x75,
+  0xD3, 0xB2, 0x0, 0xEB, 0xCF, 0x8A, 0xC2, 0xA, 0xC0, 0x74, 0x9,
+  0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE, 0x75, 0x1, 0xC3, 0x8B, 0x1E,
+  0xFE, 0x2, 0xE9, 0xAE, 0xFD, 0xE8, 0xF1, 0xE7, 0x51, 0xE8, 0xF5,
+  0x1, 0x59, 0x5A, 0x51, 0x51, 0xE8, 0x20, 0xE8, 0x73, 0xB, 0x8A,
+  0xF7, 0x8A, 0xD3, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0x3B, 0xDA, 0x72,
+  0x3, 0xE9, 0x0, 0xEE, 0xBB, 0x2D, 0x7, 0xE8, 0xF6, 0x58, 0x59,
+  0xBB, 0xDD, 0x9, 0x5E, 0x87, 0xDE, 0x56, 0x87, 0xDA, 0x8B, 0x1E,
+  0x58, 0x3, 0x8B, 0xF2, 0xAC, 0x8B, 0xF9, 0xAA, 0x41, 0x42, 0x3B,
+  0xDA, 0x75, 0xF4, 0x8B, 0xD9, 0x89, 0x1E, 0x58, 0x3, 0xC3, 0xE8,
+  0x32, 0x0, 0xE8, 0xC3, 0x24, 0x1E, 0x8E, 0x1E, 0x50, 0x3, 0x8A,
+  0x7, 0x1F, 0xE9, 0xEE, 0xF8, 0xE8, 0x16, 0x0, 0x52, 0xE8, 0xB1,
+  0x24, 0xE8, 0x59, 0xB, 0x2C, 0xE8, 0x7D, 0xFC, 0x5A, 0x6, 0x8E,
+  0x6, 0x50, 0x3, 0x8B, 0xFA, 0xAA, 0x7, 0xC3, 0xE8, 0x7A, 0xF4,
+  0x53, 0xE8, 0x4, 0x0, 0x87, 0xDA, 0x5B, 0xC3, 0xB9, 0xAD, 0x6B,
+  0x51, 0xE8, 0x69, 0xF8, 0x78, 0xF6, 0xCD, 0xA4, 0xA0, 0xA6, 0x4,
+  0x3C, 0x90, 0x75, 0xED, 0xE8, 0xAB, 0x58, 0x78, 0xE8, 0xE8, 0x82,
+  0x48, 0xB9, 0x80, 0x91, 0xBA, 0x0, 0x0, 0xE9, 0x3A, 0x40, 0xB9,
+  0xA, 0x0, 0x51, 0x8A, 0xF5, 0x8A, 0xD5, 0x74, 0x35, 0x3C, 0x2C,
+  0x74, 0xB, 0x52, 0xE8, 0x74, 0xED, 0x8A, 0xEE, 0x8A, 0xCA, 0x5A,
+  0x74, 0x26, 0xE8, 0x0, 0xB, 0x2C, 0xE8, 0x66, 0xED, 0x74, 0x1D,
+  0x58, 0xE8, 0xF6, 0xA, 0x2C, 0x52, 0xE8, 0x68, 0xED, 0x74, 0x3,
+  0xE9, 0xB6, 0xE4, 0xB, 0xD2, 0x75, 0x3, 0xE9, 0x4A, 0xED, 0x87,
+  0xDA, 0x5E, 0x87, 0xDE, 0x56, 0x87, 0xDA, 0x51, 0xE8, 0x4C, 0xE7,
+  0x5A, 0x52, 0x51, 0xE8, 0x46, 0xE7, 0x8B, 0xD9, 0x5A, 0x3B, 0xDA,
+  0x87, 0xDA, 0x73, 0x3, 0xE9, 0x2C, 0xED, 0x5A, 0x59, 0x58, 0x53,
+  0x52, 0xEB, 0x15, 0x3, 0xD9, 0x73, 0x3, 0xE9, 0x1E, 0xED, 0x87,
+  0xDA, 0x53, 0xBB, 0xF9, 0xFF, 0x3B, 0xDA, 0x5B, 0x73, 0x3, 0xE9,
+  0x10, 0xED, 0x52, 0x8B, 0x17, 0xB, 0xD2, 0x87, 0xDA, 0x5A, 0x74,
+  0xC, 0x8A, 0x7, 0x43, 0xA, 0x7, 0x9F, 0x4B, 0x9E, 0x87, 0xDA,
+  0x75, 0xD5, 0x51, 0xE8, 0x24, 0x0, 0x59, 0x5A, 0x5B, 0x52, 0x8B,
+  0x17, 0x43, 0xB, 0xD2, 0x74, 0x14, 0x87, 0xDA, 0x5E, 0x87, 0xDE,
+  0x56, 0x87, 0xDA, 0x43, 0x89, 0x17, 0x87, 0xDA, 0x3, 0xD9, 0x87,
+  0xDA, 0x5B, 0xEB, 0xE4, 0xB9, 0xB5, 0x8, 0x51, 0x3C, 0xD, 0x32,
+  0xC0, 0xA2, 0x3D, 0x3, 0x8B, 0x1E, 0x30, 0x0, 0x4B, 0x43, 0x8A,
+  0x7, 0x43, 0xA, 0x7, 0x75, 0x1, 0xC3, 0x43, 0x8B, 0x17, 0x43,
+  0xE8, 0x7B, 0xEB, 0xA, 0xC0, 0x74, 0xEC, 0x8A, 0xC8, 0xA0, 0x3D,
+  0x3, 0xA, 0xC0, 0x8A, 0xC1, 0x74, 0x5B, 0xCD, 0xA5, 0x3C, 0xA7,
+  0x75, 0x18, 0xE8, 0x63, 0xEB, 0x3C, 0x89, 0x75, 0xE4, 0xE8, 0x5C,
+  0xEB, 0x3C, 0xE, 0x75, 0xDD, 0x52, 0xE8, 0xAC, 0xEC, 0xB, 0xD2,
+  0x75, 0xA, 0xEB, 0x29, 0x3C, 0xE, 0x75, 0xCC, 0x52, 0xE8, 0x9E,
+  0xEC, 0x53, 0xE8, 0x8C, 0xE6, 0x9F, 0x49, 0x9E, 0xB0, 0xD, 0x72,
+  0x3F, 0xE8, 0x78, 0x8, 0xBB, 0xFC, 0x23, 0x52, 0xE8, 0x69, 0x57,
+  0x5B, 0xE8, 0x60, 0x41, 0x59, 0x5B, 0x53, 0x51, 0xE8, 0x51, 0x41,
+  0x5B, 0x5A, 0x4B, 0xEB, 0xA3, 0x55, 0x6E, 0x64, 0x65, 0x66, 0x69,
+  0x6E, 0x65, 0x64, 0x20, 0x6C, 0x69, 0x6E, 0x65, 0x20, 0x0, 0x3C,
+  0xD, 0x75, 0xEA, 0x52, 0xE8, 0x61, 0xEC, 0x53, 0x87, 0xDA, 0x43,
+  0x43, 0x43, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0xB0, 0xE, 0xBB, 0xF7,
+  0x23, 0x53, 0x8B, 0x1E, 0xFE, 0x2, 0x53, 0x4B, 0x88, 0x2F, 0x4B,
+  0x88, 0xF, 0x4B, 0x88, 0x7, 0x5B, 0xC3, 0xA0, 0x3D, 0x3, 0xA,
+  0xC0, 0x74, 0xF8, 0xE9, 0x49, 0xFF, 0xE8, 0xB2, 0x9, 0x42, 0xE8,
+  0xAE, 0x9, 0x41, 0xE8, 0xAA, 0x9, 0x53, 0xE8, 0xA6, 0x9, 0x45,
+  0xA0, 0x5D, 0x4, 0xA, 0xC0, 0x74, 0x3, 0xE9, 0x6E, 0xE3, 0x53,
+  0x8B, 0x1E, 0x5A, 0x3, 0x87, 0xDA, 0x8B, 0x1E, 0x5C, 0x3, 0x3B,
+  0xDA, 0x74, 0x3, 0xE9, 0x5C, 0xE3, 0x5B, 0x8A, 0x7, 0x2C, 0x30,
+  0x73, 0x3, 0xE9, 0x49, 0xE3, 0x3C, 0x2, 0x72, 0x3, 0xE9, 0x42,
+  0xE3, 0xA2, 0x5C, 0x4, 0xFE, 0xC0, 0xA2, 0x5D, 0x4, 0xE8, 0x96,
+  0xEA, 0xC3, 0x2E, 0x8A, 0x7, 0xA, 0xC0, 0x74, 0xF8, 0xE8, 0x3,
+  0x0, 0x43, 0xEB, 0xF3, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0xE9,
+  0x19, 0x7, 0x74, 0x9, 0xE8, 0x84, 0xF2, 0x53, 0xE8, 0x6, 0x47,
+  0xEB, 0x20, 0x53, 0xBB, 0xD2, 0x24, 0xE8, 0xA5, 0x56, 0xE8, 0xE1,
+  0xC, 0x5A, 0x73, 0x3, 0xE9, 0x8F, 0x9, 0x52, 0x43, 0x8A, 0x7,
+  0xE8, 0x0, 0x45, 0x8A, 0x7, 0xA, 0xC0, 0x75, 0xE4, 0xE8, 0xE4,
+  0x46, 0x89, 0x1E, 0xC, 0x0, 0xE8, 0x9E, 0x3F, 0x5B, 0xC3, 0x52,
+  0x61, 0x6E, 0x64, 0x6F, 0x6D, 0x20, 0x6E, 0x75, 0x6D, 0x62, 0x65,
+  0x72, 0x20, 0x73, 0x65, 0x65, 0x64, 0x20, 0x28, 0x2D, 0x33, 0x32,
+  0x37, 0x36, 0x38, 0x20, 0x74, 0x6F, 0x20, 0x33, 0x32, 0x37, 0x36,
+  0x37, 0x29, 0x0, 0xB1, 0x1D, 0xEB, 0x2, 0xB1, 0x1A, 0xB5, 0x0,
+  0x87, 0xDA, 0x8B, 0x1E, 0x2E, 0x0, 0x89, 0x1E, 0x5A, 0x4, 0x87,
+  0xDA, 0xFE, 0xC5, 0x4B, 0xE8, 0xC, 0xEA, 0x74, 0x17, 0x3C, 0x22,
+  0x75, 0xB, 0xE8, 0x3, 0xEA, 0xA, 0xC0, 0x74, 0xC, 0x3C, 0x22,
+  0x75, 0xF5, 0x3C, 0xA1, 0x74, 0x1D, 0x3C, 0xCD, 0x75, 0xE4, 0xA,
+  0xC0, 0x75, 0x15, 0x43, 0x8A, 0x7, 0x43, 0xA, 0x7, 0x8A, 0xD1,
+  0x75, 0x3, 0xE9, 0x9D, 0xE2, 0x43, 0x8B, 0x17, 0x43, 0x89, 0x16,
+  0x5A, 0x4, 0xE8, 0xD7, 0xE9, 0x3C, 0x8F, 0x75, 0x7, 0x51, 0xE8,
+  0x11, 0xEC, 0x59, 0xEB, 0xD9, 0x3C, 0x84, 0x75, 0x7, 0x51, 0xE8,
+  0x2, 0xEC, 0x59, 0xEB, 0xCE, 0x8A, 0xC1, 0x3C, 0x1A, 0x8A, 0x7,
+  0x74, 0xD, 0x3C, 0xB1, 0x74, 0xA3, 0x3C, 0xB2, 0x75, 0xA1, 0xFE,
+  0xCD, 0x75, 0x9D, 0xC3, 0x3C, 0x82, 0x74, 0x96, 0x3C, 0x83, 0x75,
+  0x94, 0xFE, 0xCD, 0x74, 0xF3, 0xE8, 0x9D, 0xE9, 0x74, 0xA8, 0x87,
+  0xDA, 0x8B, 0x1E, 0x2E, 0x0, 0x53, 0x8B, 0x1E, 0x5A, 0x4, 0x89,
+  0x1E, 0x2E, 0x0, 0x87, 0xDA, 0x51, 0xE8, 0xD7, 0x11, 0x59, 0x4B,
+  0xE8, 0x81, 0xE9, 0xBA, 0x2A, 0x25, 0x74, 0x8, 0xE8, 0x50, 0x8,
+  0x2C, 0x4B, 0xBA, 0x79, 0x25, 0x5E, 0x87, 0xDE, 0x56, 0x89, 0x1E,
+  0x2E, 0x0, 0x5B, 0x52, 0xC3, 0x9F, 0x50, 0xA0, 0xA8, 0x4, 0xA2,
+  0xA9, 0x4, 0x58, 0x9E, 0x9F, 0x50, 0x32, 0xC0, 0xA2, 0xA8, 0x4,
+  0x58, 0x9E, 0xC3, 0xE8, 0xDB, 0x2, 0x8A, 0x7, 0x43, 0x8A, 0xF,
+  0x43, 0x8A, 0x2F, 0x5A, 0x51, 0x50, 0xE8, 0xD6, 0x2, 0x58, 0x8A,
+  0xF0, 0x8A, 0x17, 0x43, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0x5B, 0x8A,
+  0xC2, 0xA, 0xC6, 0x75, 0x1, 0xC3, 0x8A, 0xC6, 0x2C, 0x1, 0x72,
+  0xF9, 0x32, 0xC0, 0x3A, 0xC2, 0xFE, 0xC0, 0x73, 0xF1, 0xFE, 0xCE,
+  0xFE, 0xCA, 0x8B, 0xF1, 0xAC, 0x41, 0x3A, 0x7, 0x9F, 0x43, 0x9E,
+  0x74, 0xDC, 0xF5, 0xE9, 0x72, 0x3F, 0xE8, 0xF7, 0x3D, 0xEB, 0x8,
+  0xE8, 0xFC, 0x3D, 0xEB, 0x3, 0xE8, 0xAE, 0x4A, 0xE8, 0x2F, 0x0,
+  0xE8, 0x89, 0x2, 0xB9, 0x17, 0x29, 0x51, 0x8A, 0x7, 0x43, 0x53,
+  0xE8, 0xAB, 0x0, 0x5B, 0x8A, 0xF, 0x43, 0x8A, 0x2F, 0xE8, 0xD,
+  0x0, 0x53, 0x8A, 0xD8, 0xE8, 0x5B, 0x2, 0x5A, 0xC3, 0xB0, 0x1,
+  0xE8, 0x95, 0x0, 0xBB, 0x2C, 0x3, 0x53, 0x88, 0x7, 0x43, 0x89,
+  0x17, 0x5B, 0xC3, 0x4B, 0xB5, 0x22, 0x8A, 0xF5, 0x53, 0xB1, 0xFF,
+  0x43, 0x8A, 0x7, 0xFE, 0xC1, 0xA, 0xC0, 0x74, 0x8, 0x3A, 0xC6,
+  0x74, 0x4, 0x3A, 0xC5, 0x75, 0xEF, 0x3C, 0x22, 0x75, 0x3, 0xE8,
+  0xB1, 0xE8, 0x53, 0x8A, 0xC5, 0x3C, 0x2C, 0x75, 0xD, 0xFE, 0xC1,
+  0xFE, 0xC9, 0x74, 0x7, 0x4B, 0x8A, 0x7, 0x3C, 0x20, 0x74, 0xF5,
+  0x5B, 0x5E, 0x87, 0xDE, 0x56, 0x43, 0x87, 0xDA, 0x8A, 0xC1, 0xE8,
+  0xB4, 0xFF, 0xBA, 0x2C, 0x3, 0xB0, 0x52, 0x8B, 0x1E, 0xC, 0x3,
+  0x89, 0x1E, 0xA3, 0x4, 0xB0, 0x3, 0xA2, 0xFB, 0x2, 0xE8, 0x17,
+  0x3E, 0xBA, 0x2F, 0x3, 0x3B, 0xDA, 0x89, 0x1E, 0xC, 0x3, 0x5B,
+  0x8A, 0x7, 0x75, 0x9B, 0xBA, 0x10, 0x0, 0xE9, 0x22, 0xE1, 0x43,
+  0xE8, 0x92, 0xFF, 0xE8, 0xEC, 0x1, 0xE8, 0x7C, 0x3E, 0xFE, 0xC6,
+  0xFE, 0xCE, 0x74, 0x85, 0x8B, 0xF1, 0xAC, 0xE8, 0xD9, 0x4, 0x3C,
+  0xD, 0x75, 0x3, 0xE8, 0xA5, 0x5, 0x41, 0xEB, 0xEC, 0xA, 0xC0,
+  0xEB, 0x2, 0x58, 0x9E, 0x9F, 0x50, 0x8B, 0x1E, 0x5C, 0x3, 0x87,
+  0xDA, 0x8B, 0x1E, 0x2F, 0x3, 0xF6, 0xD0, 0x8A, 0xC8, 0xB5, 0xFF,
+  0x3, 0xD9, 0x43, 0x3B, 0xDA, 0x72, 0xF, 0x89, 0x1E, 0x2F, 0x3,
+  0x43, 0x87, 0xDA, 0x58, 0x9E, 0xC3, 0x58, 0x86, 0xC4, 0x9E, 0xC3,
+  0x58, 0x9E, 0xBA, 0xE, 0x0, 0x75, 0x3, 0xE9, 0xCA, 0xE0, 0x3A,
+  0xC0, 0x9F, 0x50, 0xB9, 0xDA, 0x26, 0x51, 0x8B, 0x1E, 0xA, 0x3,
+  0x89, 0x1E, 0x2F, 0x3, 0xBB, 0x0, 0x0, 0x53, 0x8B, 0x1E, 0x5C,
+  0x3, 0x53, 0xBB, 0xE, 0x3, 0x8B, 0x16, 0xC, 0x3, 0x3B, 0xDA,
+  0xB9, 0x2A, 0x27, 0x74, 0x3, 0xE9, 0x9C, 0x0, 0xBB, 0xE2, 0x3,
+  0x89, 0x1E, 0x4E, 0x4, 0x8B, 0x1E, 0x5A, 0x3, 0x89, 0x1E, 0x4B,
+  0x4, 0x8B, 0x1E, 0x58, 0x3, 0x8B, 0x16, 0x4B, 0x4, 0x3B, 0xDA,
+  0x74, 0x1B, 0x8A, 0x7, 0x43, 0x43, 0x43, 0x50, 0xE8, 0x45, 0x13,
+  0x58, 0x3C, 0x3, 0x75, 0x5, 0xE8, 0x71, 0x0, 0x32, 0xC0, 0x8A,
+  0xD0, 0xB6, 0x0, 0x3, 0xDA, 0xEB, 0xDD, 0x8B, 0x1E, 0x4E, 0x4,
+  0x8B, 0x17, 0xB, 0xD2, 0x8B, 0x1E, 0x5A, 0x3, 0x74, 0x19, 0x87,
+  0xDA, 0x89, 0x1E, 0x4E, 0x4, 0x43, 0x43, 0x8B, 0x17, 0x43, 0x43,
+  0x87, 0xDA, 0x3, 0xDA, 0x89, 0x1E, 0x4B, 0x4, 0x87, 0xDA, 0xEB,
+  0xB7, 0x59, 0x8B, 0x16, 0x5C, 0x3, 0x3B, 0xDA, 0x75, 0x3, 0xE9,
+  0x6C, 0x0, 0x8A, 0x7, 0x43, 0x50, 0x43, 0x43, 0xE8, 0xF8, 0x12,
+  0x8A, 0xF, 0x43, 0x8A, 0x2F, 0x43, 0x58, 0x53, 0x3, 0xD9, 0x3C,
+  0x3, 0x75, 0xDD, 0x89, 0x1E, 0x33, 0x3, 0x5B, 0x8A, 0xF, 0xB5,
+  0x0, 0x3, 0xD9, 0x3, 0xD9, 0x43, 0x87, 0xDA, 0x8B, 0x1E, 0x33,
+  0x3, 0x87, 0xDA, 0x3B, 0xDA, 0x74, 0xC4, 0xB9, 0xC5, 0x27, 0x51,
+  0x32, 0xC0, 0xA, 0x7, 0x9F, 0x43, 0x9E, 0x8A, 0x17, 0x9F, 0x43,
+  0x9E, 0x8A, 0x37, 0x9F, 0x43, 0x9E, 0x75, 0x1, 0xC3, 0x8B, 0xCB,
+  0x8B, 0x1E, 0x2F, 0x3, 0x3B, 0xDA, 0x8B, 0xD9, 0x72, 0xF3, 0x5B,
+  0x5E, 0x87, 0xDE, 0x56, 0x3B, 0xDA, 0x5E, 0x87, 0xDE, 0x56, 0x53,
+  0x8B, 0xD9, 0x73, 0xE3, 0x59, 0x58, 0x58, 0x53, 0x52, 0x51, 0xC3,
+  0x5A, 0x5B, 0xB, 0xDB, 0x74, 0xF9, 0x4B, 0x8A, 0x2F, 0x4B, 0x8A,
+  0xF, 0x53, 0x4B, 0x8A, 0x1F, 0xB7, 0x0, 0x3, 0xD9, 0x8A, 0xF5,
+  0x8A, 0xD1, 0x4B, 0x8B, 0xCB, 0x8B, 0x1E, 0x2F, 0x3, 0xE8, 0xA0,
+  0x3C, 0x5B, 0x88, 0xF, 0x43, 0x88, 0x2F, 0x8B, 0xD9, 0x4B, 0xE9,
+  0xE0, 0xFE, 0x51, 0x53, 0x8B, 0x1E, 0xA3, 0x4, 0x5E, 0x87, 0xDE,
+  0x56, 0xE8, 0xA0, 0xF0, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0xED, 0x3B,
+  0x8A, 0x7, 0x53, 0x8B, 0x1E, 0xA3, 0x4, 0x53, 0x2, 0x7, 0xBA,
+  0xF, 0x0, 0x73, 0x3, 0xE9, 0x78, 0xDF, 0xE8, 0xDB, 0xFD, 0x5A,
+  0xE8, 0x48, 0x0, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0x3F, 0x0, 0x53,
+  0x8B, 0x1E, 0x2D, 0x3, 0x87, 0xDA, 0xE8, 0xE, 0x0, 0xE8, 0xB,
+  0x0, 0xBB, 0x3A, 0x17, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0xE9, 0x7,
+  0xFE, 0x5B, 0x5E, 0x87, 0xDE, 0x56, 0x8A, 0x7, 0x43, 0x8A, 0xF,
+  0x43, 0x8A, 0x2F, 0x8A, 0xD8, 0xFE, 0xC3, 0xFE, 0xCB, 0x75, 0x1,
+  0xC3, 0x8B, 0xF1, 0xAC, 0x8B, 0xFA, 0xAA, 0x41, 0x42, 0xEB, 0xF1,
+  0xE8, 0x92, 0x3B, 0x8B, 0x1E, 0xA3, 0x4, 0x87, 0xDA, 0xE8, 0x20,
+  0x0, 0x87, 0xDA, 0x75, 0xE5, 0x52, 0x8A, 0xF5, 0x8A, 0xD1, 0x4A,
+  0x8A, 0xF, 0x8B, 0x1E, 0x2F, 0x3, 0x3B, 0xDA, 0x75, 0xA, 0x32,
+  0xC0, 0x8A, 0xE8, 0x3, 0xD9, 0x89, 0x1E, 0x2F, 0x3, 0x5B, 0xC3,
+  0xCD, 0xEE, 0x8B, 0x1E, 0xC, 0x3, 0x4B, 0x8A, 0x2F, 0x4B, 0x8A,
+  0xF, 0x4B, 0x3B, 0xDA, 0x75, 0xEE, 0x89, 0x1E, 0xC, 0x3, 0xC3,
+  0xB9, 0x7F, 0x1B, 0x51, 0xE8, 0xB7, 0xFF, 0x32, 0xC0, 0x8A, 0xF0,
+  0x8A, 0x7, 0xA, 0xC0, 0xC3, 0xB9, 0x7F, 0x1B, 0x51, 0xE8, 0xED,
+  0xFF, 0x75, 0x3, 0xE9, 0x55, 0xE7, 0x43, 0x8B, 0x17, 0x8B, 0xF2,
+  0xAC, 0xC3, 0xE8, 0x2E, 0xFD, 0xE8, 0xE, 0xF6, 0x8B, 0x1E, 0x2D,
+  0x3, 0x88, 0x17, 0x59, 0xE9, 0x72, 0xFD, 0xE8, 0xFF, 0xE5, 0xE8,
+  0xD3, 0x4, 0x28, 0xE8, 0xF7, 0xF5, 0x52, 0xE8, 0xCB, 0x4, 0x2C,
+  0xE8, 0xFA, 0xED, 0xE8, 0xC4, 0x4, 0x29, 0x5E, 0x87, 0xDE, 0x56,
+  0x53, 0xE8, 0xEC, 0xF1, 0x74, 0x5, 0xE8, 0xE1, 0xF5, 0xEB, 0x3,
+  0xE8, 0xB9, 0xFF, 0x5A, 0xE8, 0x5, 0x0, 0xE8, 0xD5, 0xF5, 0xB0,
+  0x20, 0x50, 0x8A, 0xC2, 0xE8, 0xEC, 0xFC, 0x8A, 0xE8, 0x58, 0xFE,
+  0xC5, 0xFE, 0xCD, 0x74, 0xBC, 0x8B, 0x1E, 0x2D, 0x3, 0x88, 0x7,
+  0x43, 0xFE, 0xCD, 0x75, 0xF9, 0xEB, 0xAF, 0xE8, 0xA3, 0x0, 0x32,
+  0xC0, 0x5E, 0x87, 0xDE, 0x56, 0x8A, 0xC8, 0xB0, 0x53, 0x53, 0x8A,
+  0x7, 0x3A, 0xC5, 0x72, 0x3, 0x8A, 0xC5, 0xBA, 0xB1, 0x0, 0x51,
+  0xE8, 0x51, 0xFD, 0x59, 0x5B, 0x53, 0x43, 0x8A, 0x2F, 0x43, 0x8A,
+  0x3F, 0x8A, 0xDD, 0xB5, 0x0, 0x3, 0xD9, 0x8B, 0xCB, 0xE8, 0xA8,
+  0xFC, 0x8A, 0xD8, 0xE8, 0xF7, 0xFE, 0x5A, 0xE8, 0xD, 0xFF, 0xE9,
+  0xE8, 0xFC, 0xE8, 0x66, 0x0, 0x5A, 0x52, 0x8B, 0xF2, 0xAC, 0x2A,
+  0xC5, 0xEB, 0xBC, 0x87, 0xDA, 0x8A, 0x7, 0xE8, 0x5C, 0x0, 0xFE,
+  0xC5, 0xFE, 0xCD, 0x75, 0x3, 0xE9, 0x98, 0xE6, 0x51, 0xE8, 0xB5,
+  0x1, 0x58, 0x86, 0xC4, 0x9E, 0x5E, 0x87, 0xDE, 0x56, 0xB9, 0x75,
+  0x29, 0x51, 0xFE, 0xC8, 0x3A, 0x7, 0xB5, 0x0, 0x72, 0x1, 0xC3,
+  0x8A, 0xC8, 0x8A, 0x7, 0x2A, 0xC1, 0x3A, 0xC2, 0x8A, 0xE8, 0x72,
+  0xF3, 0x8A, 0xEA, 0xC3, 0xE8, 0x0, 0xFF, 0x75, 0x3, 0xE9, 0x8E,
+  0xF1, 0x8A, 0xD0, 0x43, 0x8B, 0x1F, 0x53, 0x3, 0xDA, 0x8A, 0x2F,
+  0x88, 0x37, 0x5E, 0x87, 0xDE, 0x56, 0x51, 0x4B, 0xE8, 0x17, 0xE5,
+  0xE8, 0xBE, 0x3F, 0x59, 0x5B, 0x88, 0x2F, 0xC3, 0x87, 0xDA, 0xE8,
+  0xE1, 0x3, 0x29, 0x59, 0x5A, 0x51, 0x8A, 0xEA, 0xC3, 0xE8, 0x0,
+  0xE5, 0xE8, 0x3, 0xED, 0xE8, 0x2, 0xF1, 0xB0, 0x1, 0x50, 0x74,
+  0x16, 0x58, 0xE8, 0xF3, 0xF4, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x26,
+  0xE6, 0x50, 0xE8, 0xBD, 0x3, 0x2C, 0xE8, 0xEC, 0xEC, 0xE8, 0xFD,
+  0x39, 0xE8, 0xB3, 0x3, 0x2C, 0x53, 0x8B, 0x1E, 0xA3, 0x4, 0x5E,
+  0x87, 0xDE, 0x56, 0xE8, 0xD9, 0xEC, 0xE8, 0xA3, 0x3, 0x29, 0x53,
+  0xE8, 0x50, 0xFE, 0x87, 0xDA, 0x59, 0x5B, 0x58, 0x51, 0xB9, 0x7,
+  0x65, 0x51, 0xB9, 0x7F, 0x1B, 0x51, 0x50, 0x52, 0xE8, 0x44, 0xFE,
+  0x5A, 0x58, 0x8A, 0xE8, 0xFE, 0xC8, 0x8A, 0xC8, 0x3A, 0x7, 0xB0,
+  0x0, 0x73, 0xA2, 0x8B, 0xF2, 0xAC, 0xA, 0xC0, 0x8A, 0xC5, 0x74,
+  0x99, 0x8A, 0x7, 0x43, 0x8A, 0x2F, 0x43, 0x8A, 0x3F, 0x8A, 0xDD,
+  0xB5, 0x0, 0x3, 0xD9, 0x2A, 0xC1, 0x8A, 0xE8, 0x51, 0x52, 0x5E,
+  0x87, 0xDE, 0x56, 0x8A, 0xF, 0x43, 0x8B, 0x17, 0x5B, 0x53, 0x52,
+  0x51, 0x8B, 0xF2, 0xAC, 0x3A, 0x7, 0x75, 0x1E, 0x42, 0xFE, 0xC9,
+  0x74, 0xC, 0x43, 0xFE, 0xCD, 0x75, 0xEF, 0x5A, 0x5A, 0x59, 0x5A,
+  0x32, 0xC0, 0xC3, 0x5B, 0x5A, 0x5A, 0x59, 0x8A, 0xC5, 0x2A, 0xC7,
+  0x2, 0xC1, 0xFE, 0xC0, 0xC3, 0x59, 0x5A, 0x5B, 0x43, 0xFE, 0xCD,
+  0x75, 0xD0, 0xEB, 0xE5, 0xE8, 0x21, 0x3, 0x28, 0xE8, 0x97, 0xC,
+  0xE8, 0x61, 0x39, 0x53, 0x52, 0x87, 0xDA, 0x43, 0x8B, 0x17, 0x8B,
+  0x1E, 0x5C, 0x3, 0x3B, 0xDA, 0x72, 0x12, 0x8B, 0x1E, 0x30, 0x0,
+  0x3B, 0xDA, 0x73, 0xA, 0x5B, 0x53, 0xE8, 0x2E, 0xFB, 0x5B, 0x53,
+  0xE8, 0xBE, 0x39, 0x5B, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0xF1, 0x2,
+  0x2C, 0xE8, 0x15, 0xF4, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x4B, 0xE5,
+  0x50, 0x8A, 0x7, 0xE8, 0x66, 0x0, 0x52, 0xE8, 0x4, 0xEC, 0x53,
+  0xE8, 0x8A, 0xFD, 0x87, 0xDA, 0x5B, 0x59, 0x58, 0x8A, 0xE8, 0x5E,
+  0x87, 0xDE, 0x56, 0x53, 0xBB, 0x7, 0x65, 0x5E, 0x87, 0xDE, 0x56,
+  0x8A, 0xC1, 0xA, 0xC0, 0x74, 0x90, 0x8A, 0x7, 0x2A, 0xC5, 0x73,
+  0x3, 0xE9, 0x1B, 0xE5, 0xFE, 0xC0, 0x3A, 0xC1, 0x72, 0x2, 0x8A,
+  0xC1, 0x8A, 0xCD, 0xFE, 0xC9, 0xB5, 0x0, 0x52, 0x43, 0x8A, 0x17,
+  0x43, 0x8A, 0x3F, 0x8A, 0xDA, 0x3, 0xD9, 0x8A, 0xE8, 0x5A, 0x87,
+  0xDA, 0x8A, 0xF, 0x43, 0x8B, 0x1F, 0x87, 0xDA, 0x8A, 0xC1, 0xA,
+  0xC0, 0x75, 0x1, 0xC3, 0x8B, 0xF2, 0xAC, 0x88, 0x7, 0x42, 0x43,
+  0xFE, 0xC9, 0x74, 0xF4, 0xFE, 0xCD, 0x75, 0xF1, 0xC3, 0xB2, 0xFF,
+  0x3C, 0x29, 0x74, 0x7, 0xE8, 0x71, 0x2, 0x2C, 0xE8, 0x95, 0xF3,
+  0xE8, 0x6A, 0x2, 0x29, 0xC3, 0xE8, 0x96, 0xEF, 0x74, 0x3, 0xE9,
+  0x6, 0x0, 0xE8, 0x12, 0xFD, 0xE8, 0x7C, 0xFB, 0x8B, 0x16, 0x5C,
+  0x3, 0x8B, 0x1E, 0x2F, 0x3, 0xE9, 0xCB, 0xEF, 0xCD, 0xB4, 0x9F,
+  0x86, 0xC4, 0x50, 0x86, 0xC4, 0x53, 0xE8, 0x25, 0x4, 0x74, 0x3,
+  0xE9, 0xDD, 0x17, 0x5B, 0x58, 0x86, 0xC4, 0x9E, 0x51, 0x9F, 0x50,
+  0xEB, 0x12, 0x32, 0xC0, 0xA2, 0x4F, 0x3, 0xE9, 0x93, 0xE5, 0x19,
+  0xFE, 0xC8, 0xE8, 0x63, 0x23, 0xB0, 0x8, 0xEB, 0x38, 0x3C, 0x9,
+  0x75, 0x10, 0xB0, 0x20, 0xE8, 0xCA, 0xFF, 0xE8, 0x4E, 0x23, 0x24,
+  0x7, 0x75, 0xF4, 0x58, 0x9E, 0x59, 0xC3, 0x3C, 0x20, 0x72, 0x20,
+  0xA0, 0x29, 0x0, 0x8A, 0xE8, 0xE8, 0x3A, 0x23, 0xFE, 0xC5, 0x74,
+  0xB, 0xFE, 0xCD, 0x3A, 0xC5, 0x75, 0x3, 0xE8, 0x72, 0x0, 0x74,
+  0x9, 0x3C, 0xFF, 0x74, 0x5, 0xFE, 0xC0, 0xE8, 0x27, 0x23, 0x58,
+  0x9E, 0x59, 0x9F, 0x50, 0x58, 0x9E, 0xE8, 0x7C, 0x22, 0xC3, 0xCD,
+  0xB5, 0xE8, 0xBC, 0x3, 0x74, 0x3D, 0xE8, 0xB6, 0x17, 0x73, 0xF3,
+  0x51, 0x52, 0x53, 0xA0, 0x36, 0x5, 0x24, 0xC8, 0xA2, 0x36, 0x5,
+  0xE8, 0xCC, 0x18, 0x5B, 0x5A, 0x59, 0xA0, 0x6B, 0x4, 0xA, 0xC0,
+  0x74, 0x3, 0xE9, 0xA, 0x31, 0xA0, 0xEF, 0x4, 0xA, 0xC0, 0x74,
+  0x7, 0xBB, 0xE8, 0xE, 0x53, 0xE9, 0xED, 0x0, 0x53, 0x51, 0x52,
+  0xBB, 0x2D, 0x7, 0xE8, 0x2, 0x4F, 0x5A, 0x59, 0xB0, 0xD, 0x5B,
+  0xC3, 0xE8, 0x12, 0x21, 0xC3, 0xE8, 0xCC, 0x22, 0xA, 0xC0, 0x74,
+  0xF8, 0xEB, 0xB, 0xC6, 0x7, 0x0, 0xE8, 0x6A, 0x3, 0xBB, 0xF6,
+  0x1, 0x75, 0x7, 0xCD, 0xB6, 0xB0, 0xD, 0xE8, 0x2D, 0xFF, 0xE8,
+  0x5B, 0x3, 0x74, 0x3, 0x32, 0xC0, 0xC3, 0x32, 0xC0, 0xE8, 0xAC,
+  0x22, 0x32, 0xC0, 0xC3, 0xCD, 0xB7, 0xA0, 0x5E, 0x0, 0xA, 0xC0,
+  0x75, 0x1, 0xC3, 0xE8, 0xC4, 0xFF, 0x75, 0x3, 0xE8, 0xDC, 0x1,
+  0xE9, 0x90, 0x1, 0xE8, 0xEF, 0x32, 0x53, 0xE8, 0xAF, 0x20, 0x74,
+  0x21, 0xE8, 0xB0, 0xFF, 0xA, 0xC0, 0x75, 0x10, 0x50, 0xB0, 0x2,
+  0xE8, 0x8B, 0xF9, 0x8B, 0x1E, 0x2D, 0x3, 0x5A, 0x89, 0x17, 0xE9,
+  0xD0, 0xF9, 0x50, 0xE8, 0x7B, 0xF9, 0x58, 0x8A, 0xD0, 0xE8, 0x4A,
+  0xFC, 0xBB, 0x6, 0x0, 0x89, 0x1E, 0xA3, 0x4, 0xB0, 0x3, 0xA2,
+  0xFB, 0x2, 0x5B, 0xC3, 0x53, 0x8B, 0x1E, 0xA, 0x3, 0xB5, 0x0,
+  0x3, 0xD9, 0x3, 0xD9, 0xB0, 0x26, 0x2A, 0xC3, 0x8A, 0xD8, 0xB0,
+  0xFF, 0x1A, 0xC7, 0x8A, 0xF8, 0x72, 0x6, 0x3, 0xDC, 0x5B, 0x73,
+  0x1, 0xC3, 0x8B, 0x1E, 0x2C, 0x0, 0x4B, 0x4B, 0x89, 0x1E, 0x45,
+  0x3, 0xBA, 0x7, 0x0, 0xE9, 0xD4, 0xDA, 0x39, 0x1E, 0x2F, 0x3,
+  0x73, 0xE9, 0x51, 0x52, 0x53, 0xE8, 0x6, 0xFA, 0x5B, 0x5A, 0x59,
+  0x39, 0x1E, 0x2F, 0x3, 0x73, 0xDA, 0xEB, 0xE3, 0x75, 0xD6, 0x8B,
+  0x1E, 0x30, 0x0, 0xE8, 0x79, 0x1, 0xA2, 0x64, 0x4, 0xA2, 0x3E,
+  0x3, 0xA2, 0x3D, 0x3, 0x88, 0x7, 0x43, 0x88, 0x7, 0x43, 0x89,
+  0x1E, 0x58, 0x3, 0xCD, 0xAE, 0x8B, 0x1E, 0x30, 0x0, 0x4B, 0xCD,
+  0xAF, 0x89, 0x1E, 0x3B, 0x3, 0xA0, 0x65, 0x4, 0xA, 0xC0, 0x75,
+  0x17, 0x32, 0xC0, 0xA2, 0x5D, 0x4, 0xA2, 0x5C, 0x4, 0xB5, 0x1A,
+  0xBB, 0x60, 0x3, 0xCD, 0xB0, 0xC6, 0x7, 0x4, 0x43, 0xFE, 0xCD,
+  0x75, 0xF8, 0xBA, 0x7, 0x0, 0xBB, 0xB, 0x0, 0xE8, 0xC6, 0x37,
+  0x32, 0xC0, 0xA2, 0x4F, 0x3, 0x8A, 0xD8, 0x8A, 0xF8, 0x89, 0x1E,
+  0x4D, 0x3, 0x89, 0x1E, 0x56, 0x3, 0x8B, 0x1E, 0xA, 0x3, 0xA0,
+  0x6B, 0x4, 0xA, 0xC0, 0x75, 0x4, 0x89, 0x1E, 0x2F, 0x3, 0x32,
+  0xC0, 0xE8, 0x7C, 0x0, 0x8B, 0x1E, 0x58, 0x3, 0x89, 0x1E, 0x5A,
+  0x3, 0x89, 0x1E, 0x5C, 0x3, 0xA0, 0x65, 0x4, 0xA, 0xC0, 0x75,
+  0x3, 0xE8, 0xB4, 0x15, 0xA0, 0x36, 0x5, 0x24, 0x1, 0x75, 0x3,
+  0xA2, 0x36, 0x5, 0x59, 0x8B, 0x1E, 0x2C, 0x0, 0x4B, 0x4B, 0x89,
+  0x1E, 0x45, 0x3, 0x43, 0x43, 0xCD, 0xB1, 0x8B, 0xE3, 0xBB, 0xE,
+  0x3, 0x89, 0x1E, 0xC, 0x3, 0xE8, 0xF3, 0xF7, 0xE8, 0xCA, 0xE6,
+  0x32, 0xC0, 0x8A, 0xF8, 0x8A, 0xD8, 0x89, 0x1E, 0x7C, 0x3, 0xA2,
+  0x4D, 0x4, 0x89, 0x1E, 0xE4, 0x3, 0x89, 0x1E, 0x50, 0x4, 0x89,
+  0x1E, 0x7A, 0x3, 0xA2, 0x39, 0x3, 0x53, 0x51, 0x8B, 0x1E, 0x3B,
+  0x3, 0xC3, 0x3B, 0xDA, 0xC3, 0x5E, 0x8B, 0xFB, 0xFC, 0x2E, 0xA6,
+  0x56, 0x8B, 0xDF, 0x75, 0xA, 0x8A, 0x7, 0x3C, 0x3A, 0x72, 0x1,
+  0xC3, 0xE9, 0x1C, 0xE1, 0xE9, 0xB2, 0xD9, 0x87, 0xDA, 0x8B, 0x1E,
+  0x30, 0x0, 0x74, 0x11, 0x87, 0xDA, 0xE8, 0x52, 0xE2, 0x53, 0xE8,
+  0x4A, 0xDC, 0x8B, 0xD9, 0x5A, 0x72, 0x3, 0xE9, 0xB, 0xE3, 0x4B,
+  0x89, 0x1E, 0x5E, 0x3, 0x87, 0xDA, 0xC3, 0x75, 0xFD, 0xFE, 0xC0,
+  0xEB, 0x9, 0x75, 0xF7, 0x9C, 0x75, 0x3, 0xE8, 0x9F, 0xA, 0x9D,
+  0x89, 0x1E, 0x43, 0x3, 0xBB, 0xE, 0x3, 0x89, 0x1E, 0xC, 0x3,
+  0xBB, 0xC, 0xFF, 0x59, 0x8B, 0x1E, 0x2E, 0x0, 0x53, 0x9C, 0x8A,
+  0xC3, 0x22, 0xC7, 0xFE, 0xC0, 0x74, 0xC, 0x89, 0x1E, 0x54, 0x3,
+  0x8B, 0x1E, 0x43, 0x3, 0x89, 0x1E, 0x56, 0x3, 0xE8, 0xF5, 0xFD,
+  0x9D, 0xBB, 0x32, 0x7, 0x74, 0x3, 0xE9, 0x14, 0xDA, 0xE9, 0x41,
+  0xDA, 0xB0, 0xF, 0x50, 0xB0, 0x5E, 0xE8, 0x29, 0xFD, 0x58, 0x4,
+  0x40, 0xE8, 0x23, 0xFD, 0xE9, 0xEC, 0xFD, 0x8B, 0x1E, 0x56, 0x3,
+  0xB, 0xDB, 0xBA, 0x11, 0x0, 0x75, 0x3, 0xE9, 0x45, 0xD9, 0x8B,
+  0x16, 0x54, 0x3, 0x89, 0x16, 0x2E, 0x0, 0xC3, 0xB8, 0x32, 0xC0,
+  0xA2, 0x76, 0x4, 0xC3, 0xE8, 0xC8, 0x8, 0x52, 0x53, 0xBB, 0x6E,
+  0x4, 0xE8, 0xB, 0x36, 0x8B, 0x1E, 0x5A, 0x3, 0x5E, 0x87, 0xDE,
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+  0xEB, 0xE4, 0x87, 0xDA, 0xB0, 0xFE, 0x2A, 0xC6, 0x8A, 0xF0, 0x4B,
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+  0x36, 0x1B, 0x32, 0xC0, 0xC3, 0x2A, 0xC7, 0x74, 0xFB, 0x50, 0xA0,
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+  0x32, 0xC0, 0xC3, 0x53, 0x8B, 0x1E, 0x56, 0x0, 0x50, 0xA0, 0x72,
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+  0xA0, 0x58, 0x0, 0x3A, 0xC3, 0x75, 0x10, 0x53, 0xBB, 0x5A, 0x0,
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+  0x74, 0xDC, 0x50, 0x32, 0xC0, 0xE8, 0x28, 0xFD, 0xFE, 0xC3, 0xE8,
+  0xE6, 0x1, 0x58, 0xFE, 0xCB, 0xFE, 0xC3, 0xB7, 0x1, 0xEB, 0xE3,
+  0x53, 0xA0, 0x29, 0x0, 0x3A, 0xC7, 0x75, 0xB, 0xB7, 0x0, 0xA0,
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+  0x9, 0x0, 0x5B, 0x53, 0xE8, 0xAD, 0x1A, 0x32, 0xC0, 0x5B, 0xC3,
+  0xB0, 0x1, 0x3A, 0xC7, 0x74, 0x4, 0xFE, 0xCF, 0xEB, 0x14, 0x53,
+  0xFE, 0xCB, 0x74, 0xE, 0xA0, 0x29, 0x0, 0x8A, 0xF8, 0xE8, 0xD0,
+  0xFC, 0x75, 0x4, 0x5E, 0x87, 0xDE, 0x56, 0x5B, 0xE8, 0x88, 0x1A,
+  0xA0, 0x58, 0x0, 0x3A, 0xC3, 0x75, 0xA, 0xA0, 0x5A, 0x0, 0xFE,
+  0xC8, 0x74, 0x3, 0xA2, 0x5A, 0x0, 0xE8, 0x42, 0x1, 0x53, 0xE8,
+  0xAE, 0xFC, 0x75, 0x11, 0xFE, 0xC3, 0xB7, 0x1, 0xE8, 0x5, 0x2,
+  0x5E, 0x87, 0xDE, 0x56, 0xE8, 0xFB, 0x1, 0x5B, 0xEB, 0xE6, 0x5B,
+  0xE8, 0x55, 0x1A, 0x32, 0xC0, 0xC3, 0xE8, 0x91, 0xFC, 0x75, 0xB,
+  0xA0, 0x5B, 0x0, 0x3A, 0xC3, 0x74, 0x4, 0xFE, 0xC3, 0xEB, 0xF0,
+  0xA0, 0x29, 0x0, 0x8A, 0xF8, 0xA0, 0x50, 0x0, 0x8A, 0xC8, 0x51,
+  0xE8, 0x22, 0x1A, 0x59, 0xA, 0xC0, 0x74, 0xC, 0x3A, 0xC1, 0x74,
+  0x8, 0xFE, 0xC7, 0xE8, 0x2A, 0x1A, 0x32, 0xC0, 0xC3, 0xFE, 0xCF,
+  0x74, 0xF4, 0xEB, 0xE5, 0xE8, 0x94, 0x0, 0xB7, 0x1, 0xE8, 0x19,
+  0x1A, 0x53, 0xA0, 0x50, 0x0, 0xE8, 0xAD, 0x1, 0x5B, 0xFE, 0xC7,
+  0xA0, 0x29, 0x0, 0xFE, 0xC0, 0x3A, 0xC7, 0x75, 0xED, 0xE8, 0x41,
+  0xFC, 0x75, 0xA5, 0xB7, 0x1, 0xFE, 0xC3, 0xEB, 0xE2, 0xC6, 0x6,
+  0x70, 0x0, 0x0, 0xEB, 0x8, 0xE8, 0xE5, 0x19, 0xE8, 0x4A, 0x1,
+  0x72, 0xF, 0xE8, 0x40, 0x0, 0x74, 0x13, 0xEB, 0xF1, 0xE8, 0xD6,
+  0x19, 0xE8, 0x3B, 0x1, 0x73, 0x7, 0xE8, 0x31, 0x0, 0x74, 0x4,
+  0xEB, 0xF1, 0x32, 0xC0, 0xC3, 0x32, 0xC0, 0xA2, 0x70, 0x0, 0xEB,
+  0x8, 0xE8, 0xBD, 0x19, 0xE8, 0x22, 0x1, 0x73, 0xF, 0xE8, 0x26,
+  0x0, 0x74, 0xEB, 0xEB, 0xF1, 0xE8, 0xAE, 0x19, 0xE8, 0x13, 0x1,
+  0x72, 0x7, 0xE8, 0x17, 0x0, 0x74, 0xDC, 0xEB, 0xF1, 0xE8, 0x2,
+  0x0, 0xEB, 0xD3, 0x8B, 0x1E, 0x56, 0x0, 0xE8, 0xC4, 0xFA, 0x75,
+  0xCC, 0xB7, 0x1, 0xE9, 0x96, 0xFA, 0x8B, 0x1E, 0x56, 0x0, 0xE8,
+  0xDF, 0xFA, 0x75, 0xBE, 0xA0, 0x29, 0x0, 0x8A, 0xF8, 0xE9, 0x9A,
+  0xFA, 0xFE, 0xCB, 0x74, 0x5, 0xE8, 0xC1, 0xFB, 0x74, 0xF7, 0xFE,
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+  0x87, 0xDE, 0x56, 0xE8, 0x1C, 0xEC, 0x5B, 0xE9, 0x3, 0xD8, 0xC3,
+  0xE8, 0x5D, 0x0, 0xFE, 0xCD, 0x8A, 0x7, 0x43, 0xE8, 0x4, 0xEF,
+  0xEB, 0xCA, 0xB1, 0x0, 0xEB, 0x5, 0xB1, 0x1, 0xEB, 0x1, 0x58,
+  0xFE, 0xCD, 0xE8, 0x45, 0x0, 0x5B, 0x9D, 0x74, 0xD0, 0x51, 0xE8,
+  0x6E, 0xDA, 0xE8, 0x7F, 0x27, 0x59, 0x51, 0x53, 0x8B, 0x1E, 0xA3,
+  0x4, 0x8A, 0xE9, 0xB1, 0x0, 0x8A, 0xC5, 0x50, 0x8A, 0xC5, 0xA,
+  0xC0, 0x74, 0x3, 0xE8, 0xA1, 0xEC, 0xE8, 0xE4, 0xE9, 0x8B, 0x1E,
+  0xA3, 0x4, 0x58, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x5E, 0xFF, 0x2A,
+  0x7, 0x8A, 0xE8, 0xB0, 0x20, 0xFE, 0xC5, 0xFE, 0xCD, 0x75, 0x3,
+  0xE9, 0x4F, 0xFF, 0xE8, 0xB1, 0xEE, 0xEB, 0xF4, 0x50, 0x8A, 0xC6,
+  0xA, 0xC0, 0xB0, 0x2B, 0x74, 0x3, 0xE8, 0xA3, 0xEE, 0x58, 0xC3,
+  0x89, 0x1E, 0x35, 0x3, 0xE8, 0xEC, 0xE7, 0xE8, 0xF, 0xD2, 0x87,
+  0xDA, 0xE8, 0x66, 0x0, 0x9F, 0x44, 0x9E, 0x9F, 0x44, 0x9E, 0x75,
+  0x8, 0x3, 0xD9, 0x8B, 0xE3, 0x89, 0x1E, 0x45, 0x3, 0x8B, 0x1E,
+  0x2E, 0x0, 0x53, 0x8B, 0x1E, 0x35, 0x3, 0x53, 0x52, 0xEB, 0x28,
+  0x74, 0x3, 0xE9, 0x89, 0xCA, 0x87, 0xDA, 0xE8, 0x3F, 0x0, 0x75,
+  0x67, 0x8B, 0xE3, 0x89, 0x1E, 0x45, 0x3, 0x8B, 0x16, 0x2E, 0x0,
+  0x89, 0x16, 0x5A, 0x4, 0x43, 0x43, 0x8B, 0x17, 0x43, 0x43, 0x8B,
+  0x1F, 0x89, 0x1E, 0x2E, 0x0, 0x87, 0xDA, 0xE8, 0xCC, 0xD9, 0x53,
+  0xE8, 0x84, 0x27, 0x5B, 0x74, 0x9, 0xB9, 0xB1, 0x0, 0x8A, 0xE9,
+  0x51, 0xE9, 0x7D, 0xD1, 0x8B, 0x1E, 0x5A, 0x4, 0x89, 0x1E, 0x2E,
+  0x0, 0x5B, 0x59, 0x59, 0xE9, 0x6F, 0xD1, 0xBB, 0x4, 0x0, 0x3,
+  0xDC, 0x43, 0x8A, 0x7, 0x43, 0xB9, 0x82, 0x0, 0x3A, 0xC1, 0x75,
+  0x7, 0xB9, 0x12, 0x0, 0x3, 0xD9, 0xEB, 0xEE, 0xB9, 0xB1, 0x0,
+  0x3A, 0xC1, 0x74, 0x1, 0xC3, 0x39, 0x17, 0xB9, 0x6, 0x0, 0x74,
+  0xF8, 0x3, 0xD9, 0xEB, 0xDB, 0xBA, 0x1E, 0x0, 0xE9, 0x2F, 0xCA,
+  0xE8, 0x3A, 0x7, 0x4B, 0xE8, 0x6D, 0xD1, 0x74, 0x55, 0xE8, 0x72,
+  0xD9, 0x53, 0xE8, 0x6C, 0xDD, 0x74, 0x3D, 0xE8, 0xA, 0x33, 0xE8,
+  0x8B, 0xE8, 0x8B, 0x1E, 0xA3, 0x4, 0x43, 0x8A, 0x17, 0x43, 0x8A,
+  0x37, 0x8B, 0xF2, 0xAC, 0x3C, 0x20, 0x75, 0x9, 0x42, 0x88, 0x37,
+  0x4B, 0x88, 0x17, 0x4B, 0xFE, 0xF, 0xE8, 0xDC, 0xE8, 0x5B, 0x4B,
+  0xE8, 0x3A, 0xD1, 0x74, 0x22, 0x3C, 0x3B, 0x74, 0x5, 0xE8, 0x8,
+  0xF0, 0x2C, 0x4B, 0xE8, 0x2C, 0xD1, 0xB0, 0x2C, 0xE8, 0xAF, 0xED,
+  0xEB, 0xBA, 0xB0, 0x22, 0xE8, 0xA8, 0xED, 0xE8, 0xBA, 0xE8, 0xB0,
+  0x22, 0xE8, 0xA0, 0xED, 0xEB, 0xD7, 0xE8, 0x67, 0xEE, 0xE9, 0x8B,
+  0xD6, 0xCD, 0xA8, 0x53, 0x8A, 0xF2, 0xE8, 0x87, 0x1, 0x74, 0x9,
+  0x3C, 0x3A, 0x74, 0xF, 0xE8, 0x7E, 0x1, 0x79, 0xF7, 0x8A, 0xD6,
+  0x5B, 0x32, 0xC0, 0xB0, 0xFC, 0xCD, 0xAB, 0xC3, 0x8A, 0xC6, 0x2A,
+  0xC2, 0xFE, 0xC8, 0x3C, 0x2, 0x73, 0x5, 0xCD, 0xAC, 0xE9, 0x61,
+  0xC9, 0x3C, 0x5, 0x72, 0x3, 0xE9, 0x5A, 0xC9, 0x59, 0x52, 0x51,
+  0x8A, 0xC8, 0x8A, 0xE8, 0xBA, 0x9C, 0x3E, 0x5E, 0x87, 0xDE, 0x56,
+  0x53, 0x8A, 0x7, 0x3C, 0x61, 0x72, 0x6, 0x3C, 0x7B, 0x73, 0x2,
+  0x2C, 0x20, 0x51, 0x8A, 0xE8, 0x8B, 0xF2, 0x2E, 0xAC, 0x43, 0x42,
+  0x3A, 0xC5, 0x59, 0x75, 0x15, 0xFE, 0xC9, 0x75, 0xE2, 0x8B, 0xF2,
+  0x2E, 0xAC, 0xA, 0xC0, 0x78, 0x3, 0xE9, 0x6, 0x0, 0x5B, 0x5B,
+  0x5A, 0xA, 0xC0, 0xC3, 0xA, 0xC0, 0x78, 0xEB, 0x8B, 0xF2, 0x2E,
+  0xAC, 0xA, 0xC0, 0x9F, 0x42, 0x9E, 0x79, 0xF5, 0x8A, 0xCD, 0x5B,
+  0x53, 0x8B, 0xF2, 0x2E, 0xAC, 0xA, 0xC0, 0x75, 0xB6, 0xE9, 0xFE,
+  0xC8, 0x4B, 0x59, 0x42, 0x44, 0xFF, 0x53, 0x43, 0x52, 0x4E, 0xFE,
+  0x4C, 0x50, 0x54, 0x31, 0xFD, 0x43, 0x41, 0x53, 0x31, 0xFC, 0x0,
+  0x7B, 0x58, 0x91, 0x58, 0xA7, 0x58, 0xBD, 0x58, 0xCD, 0xA9, 0x53,
+  0x52, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0xBA, 0x2E, 0x0, 0x3,
+  0xDA, 0xB0, 0xFF, 0x2A, 0x7, 0x2, 0xC0, 0x8A, 0xD0, 0xCD, 0xAA,
+  0xB6, 0x0, 0xBB, 0xB1, 0x3E, 0x3, 0xDA, 0x2E, 0x8A, 0x17, 0x43,
+  0x2E, 0x8A, 0x37, 0x58, 0x86, 0xC4, 0x9E, 0x8A, 0xD8, 0xB7, 0x0,
+  0x3, 0xDA, 0x2E, 0x8A, 0x17, 0x43, 0x2E, 0x8A, 0x37, 0x87, 0xDA,
+  0x5A, 0x5E, 0x87, 0xDE, 0x56, 0xC3, 0x47, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xE8,
+  0x11, 0xD8, 0x53, 0xE8, 0x8C, 0xE9, 0x8A, 0x7, 0xA, 0xC0, 0x74,
+  0x4F, 0x43, 0x8A, 0x17, 0x43, 0x8A, 0x3F, 0x8A, 0xDA, 0x8A, 0xD0,
+  0x32, 0xC0, 0xA2, 0xFF, 0x6, 0xE8, 0xDB, 0xFE, 0x9F, 0x86, 0xC4,
+  0x50, 0x86, 0xC4, 0xB9, 0xF0, 0x4, 0xB6, 0xB, 0xFE, 0xC2, 0xFE,
+  0xCA, 0x74, 0x4D, 0x8A, 0x7, 0x3C, 0x20, 0x72, 0x26, 0x3C, 0x2E,
+  0x74, 0x28, 0x8B, 0xF9, 0xAA, 0x41, 0x43, 0xFE, 0xCE, 0x75, 0xE9,
+  0x58, 0x86, 0xC4, 0x9E, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x8A,
+  0xF0, 0xA0, 0xF0, 0x4, 0xFE, 0xC0, 0x74, 0x6, 0x58, 0x86, 0xC4,
+  0x9E, 0x5B, 0xC3, 0xE9, 0x28, 0xC8, 0x43, 0xEB, 0xCA, 0xB0, 0x1,
+  0xA2, 0xFF, 0x6, 0x8A, 0xC6, 0x3C, 0xB, 0x74, 0xEF, 0x3C, 0x3,
+  0x72, 0xEB, 0x74, 0xEC, 0xB0, 0x20, 0x8B, 0xF9, 0xAA, 0x41, 0xFE,
+  0xCE, 0xEB, 0xEA, 0xB0, 0x20, 0x8B, 0xF9, 0xAA, 0x41, 0xFE, 0xCE,
+  0x75, 0xF6, 0xEB, 0xBA, 0x8A, 0x7, 0x43, 0xFE, 0xCA, 0xC3, 0xE8,
+  0x7A, 0xDF, 0x8A, 0xD8, 0xA0, 0xDF, 0x4, 0x3A, 0xC3, 0x73, 0x3,
+  0xE9, 0xE9, 0xC7, 0xB7, 0x0, 0x3, 0xDB, 0x87, 0xDA, 0x8B, 0x1E,
+  0xE0, 0x4, 0x3, 0xDA, 0x8B, 0x1F, 0xA0, 0x36, 0x5, 0xFE, 0xC0,
+  0x74, 0xDB, 0x8A, 0x7, 0xA, 0xC0, 0x74, 0xD5, 0x53, 0xBA, 0x2E,
+  0x0, 0x3, 0xDA, 0x8A, 0x7, 0x3C, 0x9, 0x73, 0x5, 0xCD, 0xDC,
+  0xE9, 0xC0, 0xC7, 0x5B, 0x8A, 0x7, 0xA, 0xC0, 0xF9, 0xC3, 0x4B,
+  0xE8, 0x35, 0xCF, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0x2E, 0xCF, 0xE8,
+  0x2A, 0xDF, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0xE8, 0xAB, 0xFF, 0x75,
+  0x3, 0xE9, 0x9B, 0xC7, 0x89
+};
+
+#ifdef MEGA
+  const uint8_t BASICH[16384] PROGMEM = {
+#else
+  const uint8_t BASICH[16384] = {
+#endif
+  0x1E, 0xE9, 0x4, 0xC3, 0xB9, 0x98, 0x14, 0x51, 0xE8, 0x1C, 0xD7,
+  0x8A, 0x7, 0x3C, 0x2C, 0x75, 0x59, 0x53, 0xE8, 0x91, 0xE8, 0x8A,
+  0x7, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x7C, 0xC7, 0x43, 0x8B, 0x1F,
+  0x8A, 0x7, 0x24, 0xDF, 0xB2, 0x1, 0x3C, 0x49, 0x74, 0x15, 0xB2,
+  0x2, 0x3C, 0x4F, 0x74, 0xF, 0xB2, 0x4, 0x3C, 0x52, 0x74, 0x9,
+  0xB2, 0x8, 0x3C, 0x41, 0x74, 0x3, 0xE9, 0x54, 0xC7, 0x5B, 0x52,
+  0xE8, 0xAF, 0xED, 0x2C, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0xD0, 0xCE,
+  0xE8, 0xCC, 0xDE, 0xE8, 0xA1, 0xED, 0x2C, 0x8A, 0xC2, 0xA, 0xC0,
+  0x75, 0x3, 0xE9, 0x3D, 0xC7, 0x50, 0xE8, 0xB2, 0xFE, 0x58, 0x59,
+  0x8A, 0xD1, 0xCD, 0xDD, 0xE9, 0x83, 0x0, 0xE8, 0xA9, 0xFE, 0x8A,
+  0x7, 0x3C, 0x82, 0xB2, 0x4, 0x75, 0x59, 0xE8, 0xA5, 0xCE, 0x3C,
+  0x85, 0xB2, 0x1, 0x74, 0x4D, 0x3C, 0x4F, 0x74, 0x20, 0x3C, 0x49,
+  0x74, 0x37, 0xE8, 0x6B, 0xED, 0x41, 0xE8, 0x67, 0xED, 0x50, 0xE8,
+  0x63, 0xED, 0x50, 0xE8, 0x5F, 0xED, 0x45, 0xE8, 0x5B, 0xED, 0x4E,
+  0xE8, 0x57, 0xED, 0x44, 0xB2, 0x8, 0xEB, 0x2C, 0xE8, 0x78, 0xCE,
+  0xE8, 0x4C, 0xED, 0x55, 0xE8, 0x48, 0xED, 0x54, 0xE8, 0x44, 0xED,
+  0x50, 0xE8, 0x40, 0xED, 0x55, 0xE8, 0x3C, 0xED, 0x54, 0xB2, 0x2,
+  0xEB, 0x11, 0xE8, 0x5D, 0xCE, 0xE8, 0x31, 0xED, 0x42, 0xE8, 0x2D,
+  0xED, 0x4D, 0xB2, 0x20, 0x4B, 0xE8, 0x4F, 0xCE, 0xE8, 0x23, 0xED,
+  0x41, 0xE8, 0x1F, 0xED, 0x53, 0x52, 0x8A, 0x7, 0x3C, 0x23, 0x75,
+  0x3, 0xE8, 0x3D, 0xCE, 0xE8, 0x39, 0xDE, 0xA, 0xC0, 0x75, 0x3,
+  0xE9, 0xB0, 0xC6, 0xCD, 0xDE, 0xB4, 0x52, 0x4B, 0x8A, 0xD0, 0xE8,
+  0x29, 0xCE, 0x74, 0x3, 0xE9, 0xC5, 0xC6, 0x5E, 0x87, 0xDE, 0x56,
+  0x8A, 0xC2, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x53, 0xE8, 0x9C,
+  0xFE, 0x74, 0x3, 0xE9, 0x95, 0xC6, 0x5A, 0x8A, 0xC6, 0x3C, 0x9,
+  0xCD, 0xDF, 0x73, 0x3, 0xE9, 0x83, 0xC6, 0x53, 0xB9, 0x2E, 0x0,
+  0x3, 0xD9, 0x88, 0x37, 0xB0, 0x0, 0x5B, 0xE9, 0x91, 0xFD, 0x53,
+  0xA, 0xC0, 0x75, 0xA, 0xA0, 0x36, 0x5, 0x24, 0x1, 0x74, 0x3,
+  0xE9, 0x46, 0x3, 0xE8, 0x6B, 0xFE, 0x74, 0x15, 0x89, 0x1E, 0xE9,
+  0x4, 0x53, 0xB0, 0x2, 0x73, 0x3, 0xE9, 0x71, 0xFD, 0xCD, 0xE0,
+  0xE9, 0x50, 0xC6, 0xE8, 0x24, 0x3, 0x5B, 0x53, 0xBA, 0x31, 0x0,
+  0x3, 0xDA, 0x88, 0x7, 0x8A, 0xF8, 0x8A, 0xD8, 0x89, 0x1E, 0xE9,
+  0x4, 0x5B, 0x2, 0x7, 0xC6, 0x7, 0x0, 0x5B, 0xC3, 0xF9, 0xEB,
+  0x3, 0xD, 0x32, 0xC0, 0x9F, 0x50, 0xE8, 0x9F, 0xFD, 0xCD, 0xE9,
+  0x58, 0x9E, 0x9F, 0x50, 0x74, 0x14, 0x8A, 0x7, 0x2C, 0x2C, 0xA,
+  0xC0, 0x75, 0xC, 0xE8, 0x96, 0xCD, 0xE8, 0x6A, 0xEC, 0x52, 0x58,
+  0x9E, 0xF9, 0x9F, 0x50, 0x9F, 0x50, 0x32, 0xC0, 0xB2, 0x1, 0xE8,
+  0x54, 0xFF, 0x8B, 0x1E, 0xE9, 0x4, 0xB9, 0x31, 0x0, 0x3, 0xD9,
+  0x58, 0x9E, 0x1A, 0xC0, 0x24, 0x80, 0xC, 0x1, 0xA2, 0x36, 0x5,
+  0x58, 0x9E, 0x9F, 0x50, 0x1A, 0xC0, 0xA2, 0xEF, 0x4, 0x8A, 0x7,
+  0xA, 0xC0, 0x79, 0x3, 0xE9, 0xD8, 0x0, 0x58, 0x9E, 0x74, 0x3,
+  0xE8, 0x57, 0xEB, 0x32, 0xC0, 0xE8, 0x2C, 0xFE, 0xE9, 0x5, 0xC7,
+  0xE8, 0x42, 0xFD, 0xCD, 0xEA, 0x4B, 0xE8, 0x46, 0xCD, 0xB2, 0x80,
+  0xF9, 0x75, 0x3, 0xE8, 0x79, 0x5, 0x74, 0x18, 0xE8, 0x10, 0xEC,
+  0x2C, 0x3C, 0x50, 0xB2, 0x92, 0x75, 0x6, 0xE8, 0x2F, 0xCD, 0xF9,
+  0xEB, 0x8, 0xE8, 0x0, 0xEC, 0x41, 0xA, 0xC0, 0xB2, 0x2, 0x9F,
+  0x50, 0x8A, 0xC2, 0x24, 0x10, 0xA2, 0x62, 0x4, 0x58, 0x9E, 0x9F,
+  0x50, 0xFE, 0xC0, 0xA2, 0x5F, 0x0, 0x32, 0xC0, 0xE8, 0xDD, 0xFE,
+  0x58, 0x9E, 0x53, 0x8B, 0x1E, 0xE9, 0x4, 0x8A, 0x7, 0x5B, 0x24,
+  0x80, 0x75, 0x3, 0xE9, 0x14, 0xDD, 0x53, 0xE8, 0x63, 0xE1, 0xA0,
+  0x62, 0x4, 0xA, 0xC0, 0x74, 0x3, 0xE8, 0x79, 0x4, 0x8B, 0x1E,
+  0x58, 0x3, 0x89, 0x1E, 0x4, 0x7, 0x8B, 0x1E, 0x30, 0x0, 0x53,
+  0x8B, 0x1E, 0xE9, 0x4, 0xE8, 0xC6, 0x0, 0xA, 0xC0, 0x79, 0x3,
+  0xE9, 0x16, 0x0, 0xE9, 0x4D, 0xC5, 0xA0, 0x62, 0x4, 0xA, 0xC0,
+  0x74, 0x3, 0xE8, 0xA2, 0x4, 0x5B, 0x32, 0xC0, 0xA2, 0x62, 0x4,
+  0xE9, 0xC8, 0xFE, 0x5B, 0xE8, 0x2, 0x0, 0xEB, 0xE7, 0xE8, 0xA0,
+  0x0, 0x3C, 0xFC, 0x75, 0x3, 0xE9, 0xD, 0x1A, 0xCD, 0xEB, 0xE9,
+  0x1F, 0xC5, 0x8B, 0x1E, 0x30, 0x0, 0xA, 0xC0, 0xE8, 0x3, 0x0,
+  0xE9, 0x46, 0x0, 0x9F, 0x50, 0xE8, 0x83, 0x0, 0x3C, 0xFC, 0x75,
+  0x3, 0xE9, 0x36, 0x1A, 0x58, 0x9E, 0xCD, 0xEC, 0xE9, 0x0, 0xC5,
+  0x58, 0x9E, 0xC3, 0x24, 0x20, 0xA2, 0x63, 0x4, 0x58, 0x9E, 0x75,
+  0x3, 0xE9, 0xF1, 0xC4, 0xE8, 0x77, 0xEA, 0xA0, 0x63, 0x4, 0xA2,
+  0x64, 0x4, 0xE8, 0xAB, 0x0, 0x32, 0xC0, 0xE8, 0xF1, 0xFC, 0xC6,
+  0x7, 0x80, 0x89, 0x1E, 0xE9, 0x4, 0xE8, 0x4B, 0x0, 0xA, 0xC0,
+  0x78, 0xB3, 0xCD, 0xED, 0xE9, 0xD3, 0xC4, 0xA0, 0x64, 0x4, 0xA,
+  0xC0, 0x74, 0x3, 0xE8, 0x28, 0x4, 0xE8, 0x27, 0xC7, 0x43, 0x43,
+  0x89, 0x1E, 0x58, 0x3, 0xE8, 0x5A, 0xEA, 0x32, 0xC0, 0xA2, 0x36,
+  0x5, 0xE8, 0x43, 0xFE, 0xA0, 0xEF, 0x4, 0xA, 0xC0, 0x74, 0x3,
+  0xE9, 0xF9, 0xCB, 0xE9, 0xC4, 0xC5, 0x87, 0xDA, 0x8B, 0x1E, 0x2F,
+  0x3, 0x87, 0xDA, 0x3B, 0xDA, 0x72, 0x98, 0xE8, 0x1C, 0xEA, 0x32,
+  0xC0, 0xA2, 0x36, 0x5, 0xE9, 0xEB, 0xE9, 0x53, 0x52, 0x8B, 0x1E,
+  0xE9, 0x4, 0xBA, 0x2E, 0x0, 0x3, 0xDA, 0x8A, 0x7, 0x5A, 0x5B,
+  0xC3, 0x75, 0x1E, 0x53, 0x51, 0x50, 0xBA, 0x26, 0x43, 0x52, 0x51,
+  0xA, 0xC0, 0xC3, 0x58, 0x59, 0xFE, 0xC8, 0x79, 0xF0, 0x5B, 0xC3,
+  0x59, 0x5B, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0xF7, 0xE8, 0xE4, 0xCB,
+  0x51, 0x8A, 0x7, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0xDA, 0xCB, 0xE8,
+  0xD6, 0xDB, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0xBA, 0x2E, 0x43, 0x52,
+  0xF9, 0xFF, 0xE3, 0xB9, 0x28, 0x41, 0xA0, 0xDF, 0x4, 0xEB, 0xBF,
+  0xA0, 0x36, 0x5, 0xA, 0xC0, 0x78, 0xCC, 0xB9, 0x28, 0x41, 0x32,
+  0xC0, 0xA0, 0xDF, 0x4, 0xEB, 0xAE, 0x32, 0xC0, 0x8A, 0xE8, 0x8A,
+  0xC5, 0xE8, 0x31, 0xFC, 0xC6, 0x7, 0x0, 0xA0, 0xDF, 0x4, 0xFE,
+  0xC5, 0x2A, 0xC5, 0x73, 0xEF, 0x32, 0xC0, 0xA2, 0x36, 0x5, 0xE8,
+  0x95, 0xE9, 0x8B, 0x1E, 0x30, 0x0, 0x4B, 0xC6, 0x7, 0x0, 0xE9,
+  0xDB, 0xC3, 0x5B, 0x58, 0x86, 0xC4, 0x9E, 0x53, 0x52, 0x51, 0x9F,
+  0x86, 0xC4, 0x50, 0x86, 0xC4, 0x8B, 0x1E, 0xE9, 0x4, 0xB0, 0x6,
+  0xE8, 0x5, 0x0, 0xCD, 0xE3, 0xE9, 0xEB, 0xC3, 0x9F, 0x86, 0xC4,
+  0x50, 0x86, 0xC4, 0x52, 0x87, 0xDA, 0xBB, 0x2E, 0x0, 0x3, 0xDA,
+  0x8A, 0x7, 0x87, 0xDA, 0x5A, 0x3C, 0x9, 0x73, 0x3, 0xE9, 0xCA,
+  0x0, 0x58, 0x86, 0xC4, 0x9E, 0x5E, 0x87, 0xDE, 0x56, 0x5B, 0xE9,
+  0xE4, 0xFA, 0x51, 0x53, 0x52, 0x8B, 0x1E, 0xE9, 0x4, 0xB0, 0x8,
+  0xE8, 0xCE, 0xFF, 0xCD, 0xE4, 0xE9, 0xB4, 0xC3, 0x5A, 0x5B, 0x59,
+  0xC3, 0xE8, 0x30, 0xCB, 0xE8, 0x4, 0xEA, 0x24, 0xE8, 0x0, 0xEA,
+  0x28, 0x53, 0x8B, 0x1E, 0xE9, 0x4, 0x53, 0xBB, 0x0, 0x0, 0x89,
+  0x1E, 0xE9, 0x4, 0x5B, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0x12, 0xDB,
+  0x52, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0xB, 0xE8, 0x9, 0xCB, 0xE8,
+  0xCD, 0xFB, 0x5B, 0x32, 0xC0, 0x8A, 0x7, 0x9F, 0x50, 0xE8, 0xD3,
+  0xE9, 0x29, 0x58, 0x9E, 0x5E, 0x87, 0xDE, 0x56, 0x9F, 0x50, 0x8A,
+  0xC3, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x26, 0xCC, 0x53, 0xE8, 0x7,
+  0xE2, 0x87, 0xDA, 0x59, 0x58, 0x9E, 0x9F, 0x50, 0x74, 0x28, 0xE8,
+  0x16, 0xE8, 0x3C, 0x3, 0x74, 0x13, 0x88, 0x7, 0x43, 0xFE, 0xC9,
+  0x75, 0xEC, 0x58, 0x9E, 0x59, 0x5B, 0x89, 0x1E, 0xE9, 0x4, 0x51,
+  0xE9, 0x33, 0xE2, 0x58, 0x9E, 0x8B, 0x1E, 0x2E, 0x0, 0x89, 0x1E,
+  0x47, 0x3, 0x5B, 0xE9, 0x6, 0xC3, 0xE8, 0x6A, 0xFF, 0x73, 0x3,
+  0xE9, 0x30, 0xC3, 0xEB, 0xD5, 0xCD, 0xE5, 0xE8, 0x12, 0x0, 0x53,
+  0xB5, 0x1, 0xE8, 0x2, 0x0, 0x5B, 0xC3, 0x32, 0xC0, 0x88, 0x7,
+  0x43, 0xFE, 0xCD, 0x75, 0xF9, 0xC3, 0x8B, 0x1E, 0xE9, 0x4, 0xBA,
+  0x33, 0x0, 0x3, 0xDA, 0xC3, 0x58, 0x86, 0xC4, 0x9E, 0xC3, 0xE8,
+  0x7, 0xFB, 0x75, 0x3, 0xE9, 0xFA, 0xC2, 0xB0, 0xA, 0x73, 0x3,
+  0xE9, 0x12, 0xFA, 0xCD, 0xE6, 0xE9, 0xEE, 0xC2, 0xE8, 0xF3, 0xFA,
+  0x75, 0x3, 0xE9, 0xE6, 0xC2, 0xB0, 0xC, 0x73, 0x3, 0xE9, 0xFE,
+  0xF9, 0xCD, 0xE7, 0xE9, 0xDA, 0xC2, 0xE8, 0xDF, 0xFA, 0x75, 0x3,
+  0xE9, 0xD2, 0xC2, 0xB0, 0xE, 0x73, 0x3, 0xE9, 0xEA, 0xF9, 0xCD,
+  0xE8, 0xE9, 0xC6, 0xC2, 0xE8, 0xFF, 0xEA, 0x75, 0x3, 0xE9, 0x1F,
+  0xCA, 0x32, 0xC0, 0xE8, 0x47, 0xFC, 0xB2, 0x42, 0xE9, 0xF2, 0xC2,
+  0x3C, 0x23, 0x75, 0xAD, 0xE8, 0x2C, 0xDA, 0xE8, 0x4, 0xE9, 0x2C,
+  0x8A, 0xC2, 0x53, 0xE8, 0x0, 0xFB, 0x5B, 0x8A, 0x7, 0xC3, 0xB9,
+  0xEC, 0x2D, 0x51, 0x32, 0xC0, 0xE9, 0x24, 0xFC, 0xE8, 0x1E, 0xD6,
+  0xB9, 0x9B, 0x16, 0xBA, 0x20, 0x2C, 0x75, 0x1B, 0x8A, 0xD6, 0xEB,
+  0x17, 0xB9, 0x98, 0x14, 0x51, 0xE8, 0xCC, 0xFF, 0xE8, 0x51, 0xF2,
+  0xE8, 0x1B, 0x1F, 0x52, 0xB9, 0x8A, 0x11, 0x32, 0xC0, 0x8A, 0xF0,
+  0x8A, 0xD0, 0x50, 0x51, 0x53, 0xE8, 0xA5, 0xFE, 0x73, 0x3, 0xE9,
+  0x6B, 0xC2, 0x3C, 0x20, 0x75, 0x6, 0xFE, 0xC6, 0xFE, 0xCE, 0x75,
+  0xEE, 0x3C, 0x22, 0x75, 0x13, 0x8A, 0xE8, 0x8A, 0xC2, 0x3C, 0x2C,
+  0x8A, 0xC5, 0x75, 0x9, 0x8A, 0xF5, 0x8A, 0xD5, 0xE8, 0x81, 0xFE,
+  0x72, 0x53, 0xBB, 0xF7, 0x1, 0xB5, 0xFF, 0x8A, 0xC8, 0x8A, 0xC6,
+  0x3C, 0x22, 0x8A, 0xC1, 0x74, 0x2E, 0x3C, 0xD, 0x53, 0x74, 0x59,
+  0x5B, 0x3C, 0xA, 0x75, 0x24, 0x8A, 0xC8, 0x8A, 0xC2, 0x3C, 0x2C,
+  0x8A, 0xC1, 0x74, 0x3, 0xE8, 0x89, 0x0, 0x53, 0xE8, 0x55, 0xFE,
+  0x5B, 0x72, 0x26, 0x3C, 0xD, 0x75, 0xC, 0x8A, 0xC2, 0x3C, 0x20,
+  0x74, 0x15, 0x3C, 0x2C, 0xB0, 0xD, 0x74, 0xF, 0xA, 0xC0, 0x74,
+  0xB, 0x3A, 0xC6, 0x74, 0xE, 0x3A, 0xC2, 0x74, 0xA, 0xE8, 0x63,
+  0x0, 0x53, 0xE8, 0x2F, 0xFE, 0x5B, 0x73, 0xB2, 0x53, 0x3C, 0x22,
+  0x74, 0x4, 0x3C, 0x20, 0x75, 0x25, 0xE8, 0x20, 0xFE, 0x72, 0x20,
+  0x3C, 0x20, 0x74, 0xF7, 0x3C, 0x2C, 0x74, 0x18, 0x3C, 0xD, 0x75,
+  0x4, 0xCD, 0xE1, 0x74, 0x10, 0x8B, 0x1E, 0xE9, 0x4, 0x8A, 0xC8,
+  0xB0, 0x12, 0xE8, 0xDD, 0xFD, 0xCD, 0xE2, 0xE9, 0xC3, 0xC1, 0x5B,
+  0xC6, 0x7, 0x0, 0xBB, 0xF6, 0x1, 0x8A, 0xC2, 0x2C, 0x20, 0x74,
+  0x7, 0xB5, 0x0, 0xE8, 0x66, 0xE0, 0x5B, 0xC3, 0xE8, 0x37, 0xD5,
+  0x9F, 0x50, 0xE8, 0x2A, 0xC9, 0x58, 0x9E, 0x9F, 0x50, 0x73, 0x3,
+  0xE8, 0xC4, 0x23, 0x58, 0x9E, 0x72, 0x3, 0xE8, 0xC4, 0x23, 0x5B,
+  0xC3, 0xA, 0xC0, 0x74, 0xFB, 0x88, 0x7, 0x43, 0xFE, 0xCD, 0x75,
+  0xF4, 0x59, 0xEB, 0xC5, 0xE8, 0x46, 0x0, 0xA2, 0x60, 0x0, 0xFE,
+  0xC0, 0x74, 0x3, 0xE9, 0x9E, 0xC1, 0x53, 0x51, 0xB2, 0x2, 0xE8,
+  0xC6, 0xFA, 0x5B, 0xE8, 0x3B, 0xFC, 0x32, 0xC0, 0xA2, 0x60, 0x0,
+  0xE9, 0x1A, 0xFC, 0xE8, 0x26, 0x0, 0xA, 0xC0, 0x74, 0x7, 0xFE,
+  0xC0, 0x75, 0x3, 0xE9, 0x7D, 0xC1, 0xFE, 0xC8, 0xA2, 0x60, 0x0,
+  0x53, 0x51, 0x32, 0xC0, 0xB2, 0x1, 0xE8, 0x9E, 0xFA, 0x5B, 0xE8,
+  0x2E, 0xFC, 0x32, 0xC0, 0xA2, 0x60, 0x0, 0x5B, 0xE9, 0xCC, 0xFA,
+  0xE8, 0xB4, 0xF8, 0x52, 0x4B, 0xE8, 0xB9, 0xC8, 0x5A, 0x75, 0x3,
+  0xB0, 0x1, 0xC3, 0x52, 0xE8, 0x86, 0xE7, 0x2C, 0xE8, 0x2B, 0x0,
+  0x52, 0x4B, 0xE8, 0xA6, 0xC8, 0x75, 0x5, 0x59, 0x5A, 0x32, 0xC0,
+  0xC3, 0xE8, 0x73, 0xE7, 0x2C, 0xE8, 0x18, 0x0, 0x59, 0x87, 0xDA,
+  0x3, 0xD9, 0x89, 0x1E, 0x4, 0x7, 0x87, 0xDA, 0x4B, 0xE8, 0x89,
+  0xC8, 0x74, 0x3, 0xE9, 0x25, 0xC1, 0x5A, 0xB0, 0xFF, 0xC3, 0xE8,
+  0x87, 0xD0, 0x53, 0xE8, 0x11, 0xDC, 0x5A, 0x87, 0xDA, 0xC3, 0xB9,
+  0xB, 0xD, 0x8B, 0x1E, 0x30, 0x0, 0x87, 0xDA, 0x8B, 0x1E, 0x58,
+  0x3, 0x3B, 0xDA, 0x75, 0x1, 0xC3, 0xBB, 0x17, 0x62, 0x8A, 0xC3,
+  0x2, 0xC1, 0x8A, 0xD8, 0x8A, 0xC7, 0x14, 0x0, 0x8A, 0xF8, 0x8B,
+  0xF2, 0xAC, 0x2A, 0xC5, 0x2E, 0x32, 0x7, 0x50, 0xBB, 0x76, 0x61,
+  0x8A, 0xC3, 0x2, 0xC5, 0x8A, 0xD8, 0x8A, 0xC7, 0x14, 0x0, 0x8A,
+  0xF8, 0x58, 0x2E, 0x32, 0x7, 0x2, 0xC1, 0x8B, 0xFA, 0xAA, 0x42,
+  0xFE, 0xC9, 0x75, 0x2, 0xB1, 0xB, 0xFE, 0xCD, 0x75, 0xBC, 0xB5,
+  0xD, 0xEB, 0xB8, 0xB9, 0xB, 0xD, 0x8B, 0x1E, 0x30, 0x0, 0x87,
+  0xDA, 0x8B, 0x1E, 0x58, 0x3, 0x3B, 0xDA, 0x74, 0xAF, 0xBB, 0x76,
+  0x61, 0x8A, 0xC3, 0x2, 0xC5, 0x8A, 0xD8, 0x8A, 0xC7, 0x14, 0x0,
+  0x8A, 0xF8, 0x8B, 0xF2, 0xAC, 0x2A, 0xC1, 0x2E, 0x32, 0x7, 0x50,
+  0xBB, 0x17, 0x62, 0x8A, 0xC3, 0x2, 0xC1, 0x8A, 0xD8, 0x8A, 0xC7,
+  0x14, 0x0, 0x8A, 0xF8, 0x58, 0x2E, 0x32, 0x7, 0x2, 0xC5, 0x8B,
+  0xFA, 0xAA, 0x42, 0xFE, 0xC9, 0x75, 0x2, 0xB1, 0xB, 0xFE, 0xCD,
+  0x75, 0xBD, 0xB5, 0xD, 0xEB, 0xB9, 0x53, 0x8B, 0x1E, 0x2E, 0x0,
+  0x8A, 0xC7, 0x22, 0xC3, 0x5B, 0xFE, 0xC0, 0x74, 0x1, 0xC3, 0x9F,
+  0x50, 0xA0, 0x64, 0x4, 0xA, 0xC0, 0x74, 0x3, 0xE9, 0xF5, 0xC8,
+  0x58, 0x9E, 0xC3, 0x8A, 0x7, 0x3C, 0x40, 0x75, 0x3, 0xE8, 0xAD,
+  0xC7, 0xB9, 0x0, 0x0, 0x8A, 0xF5, 0x8A, 0xD1, 0x3C, 0xEA, 0x74,
+  0x1F, 0x8A, 0x7, 0x3C, 0xCF, 0x9C, 0x75, 0x3, 0xE8, 0x98, 0xC7,
+  0xE8, 0x6C, 0xE6, 0x28, 0xE8, 0x7E, 0xD7, 0x52, 0xE8, 0x64, 0xE6,
+  0x2C, 0xE8, 0x76, 0xD7, 0xE8, 0x5D, 0xE6, 0x29, 0x59, 0x9D, 0x53,
+  0x8B, 0x1E, 0x3D, 0x5, 0x74, 0x3, 0xBB, 0x0, 0x0, 0x9F, 0x3,
+  0xD9, 0xD1, 0xDE, 0x9E, 0xD1, 0xD6, 0x89, 0x1E, 0x3D, 0x5, 0x89,
+  0x1E, 0x37, 0x5, 0x8B, 0xCB, 0x8B, 0x1E, 0x3B, 0x5, 0x74, 0x3,
+  0xBB, 0x0, 0x0, 0x3, 0xDA, 0x89, 0x1E, 0x3B, 0x5, 0x89, 0x1E,
+  0x39, 0x5, 0x87, 0xDA, 0x5B, 0xC3, 0x32, 0xC0, 0xEB, 0x2, 0xB0,
+  0x3, 0x50, 0xE8, 0xA4, 0xFF, 0x58, 0xE8, 0x2E, 0x0, 0x53, 0xE8,
+  0x28, 0x3, 0x73, 0x6, 0xE8, 0x7F, 0x2, 0xE8, 0x55, 0x2, 0x5B,
+  0xC3, 0xE8, 0x31, 0xC7, 0xE8, 0x8C, 0xFF, 0x53, 0xE8, 0x14, 0x3,
+  0xBB, 0xFF, 0xFF, 0x73, 0xA, 0xE8, 0x68, 0x2, 0xE8, 0x1B, 0x2,
+  0x8A, 0xD8, 0xB7, 0x0, 0xE8, 0x7, 0x1D, 0x5B, 0xC3, 0xB0, 0x3,
+  0x51, 0x52, 0x8A, 0xD0, 0x4B, 0xE8, 0xC, 0xC7, 0x74, 0xB, 0xE8,
+  0xDE, 0xE5, 0x2C, 0x3C, 0x2C, 0x74, 0x3, 0xE8, 0xFE, 0xD6, 0x8A,
+  0xC2, 0x53, 0xE8, 0xC1, 0x2, 0x73, 0x3, 0xE9, 0x30, 0xC8, 0x5B,
+  0x5A, 0x59, 0xE9, 0xEF, 0xC6, 0x8B, 0x1E, 0x37, 0x5, 0x8A, 0xC3,
+  0x2A, 0xC1, 0x8A, 0xD8, 0x8A, 0xC7, 0x1A, 0xC5, 0x8A, 0xF8, 0x73,
+  0xC5, 0x32, 0xC0, 0x2A, 0xC3, 0x8A, 0xD8, 0x1A, 0xC7, 0x2A, 0xC3,
+  0x8A, 0xF8, 0xF9, 0xC3, 0x8B, 0x1E, 0x39, 0x5, 0x8A, 0xC3, 0x2A,
+  0xC2, 0x8A, 0xD8, 0x8A, 0xC7, 0x1A, 0xC6, 0x8A, 0xF8, 0xEB, 0xDE,
+  0x53, 0x8B, 0x1E, 0x39, 0x5, 0x87, 0xDA, 0x89, 0x1E, 0x39, 0x5,
+  0x5B, 0xC3, 0xE8, 0xF0, 0xFF, 0x53, 0x51, 0x8B, 0x1E, 0x37, 0x5,
+  0x5E, 0x87, 0xDE, 0x56, 0x89, 0x1E, 0x37, 0x5, 0x59, 0x5B, 0xC3,
+  0xE8, 0xE2, 0xFE, 0x51, 0x52, 0xE8, 0x6A, 0xE5, 0xEA, 0xE8, 0xED,
+  0xFE, 0xE8, 0x76, 0xFF, 0x5A, 0x59, 0x74, 0x53, 0xE8, 0x5C, 0xE5,
+  0x2C, 0xE8, 0x58, 0xE5, 0x42, 0x75, 0x3, 0xE9, 0x60, 0x0, 0xE8,
+  0x4F, 0xE5, 0x46, 0x53, 0xE8, 0x5D, 0x2, 0xE8, 0xC1, 0xFF, 0xE8,
+  0x57, 0x2, 0xE8, 0x9C, 0xFF, 0x73, 0x3, 0xE8, 0xA9, 0xFF, 0x43,
+  0x53, 0xE8, 0x72, 0xFF, 0x73, 0x3, 0xE8, 0xAF, 0xFF, 0x43, 0x53,
+  0xE8, 0x9C, 0x1, 0x5A, 0x59, 0x52, 0x51, 0xE8, 0xDB, 0x0, 0x50,
+  0x53, 0x87, 0xDA, 0xE8, 0x69, 0x2, 0x5B, 0x58, 0xE8, 0xD7, 0x0,
+  0xE8, 0xF8, 0x0, 0x59, 0x5A, 0x49, 0x8A, 0xC5, 0xA, 0xC1, 0x75,
+  0xE3, 0x5B, 0xC3, 0x51, 0x52, 0x53, 0xE8, 0x45, 0x0, 0x8B, 0x1E,
+  0x3D, 0x5, 0x89, 0x1E, 0x37, 0x5, 0x8B, 0x1E, 0x3B, 0x5, 0x89,
+  0x1E, 0x39, 0x5, 0x5B, 0x5A, 0x59, 0xC3, 0x53, 0x8B, 0x1E, 0x39,
+  0x5, 0x53, 0x52, 0x87, 0xDA, 0xE8, 0xDA, 0xFF, 0x5B, 0x89, 0x1E,
+  0x39, 0x5, 0x87, 0xDA, 0xE8, 0xD0, 0xFF, 0x5B, 0x89, 0x1E, 0x39,
+  0x5, 0x8B, 0x1E, 0x37, 0x5, 0x51, 0x8B, 0xCB, 0xE8, 0xC1, 0xFF,
+  0x5B, 0x89, 0x1E, 0x37, 0x5, 0x8B, 0xCB, 0xE8, 0xB7, 0xFF, 0x5B,
+  0xC3, 0xCD, 0xB8, 0xE8, 0xCF, 0x1, 0xE8, 0x33, 0xFF, 0xE8, 0xC9,
+  0x1, 0xE8, 0xE, 0xFF, 0x73, 0x3, 0xE8, 0x28, 0xFF, 0x52, 0x53,
+  0xE8, 0xE4, 0xFE, 0x87, 0xDA, 0xBB, 0xF1, 0x49, 0x73, 0x3, 0xBB,
+  0x5, 0x4A, 0x5E, 0x87, 0xDE, 0x56, 0x3B, 0xDA, 0x73, 0x14, 0x89,
+  0x1E, 0xFD, 0x6, 0x5B, 0x89, 0x1E, 0xF7, 0x6, 0xBB, 0xD5, 0x49,
+  0x89, 0x1E, 0xF9, 0x6, 0x87, 0xDA, 0xEB, 0x16, 0x5E, 0x87, 0xDE,
+  0x56, 0x89, 0x1E, 0xF9, 0x6, 0xBB, 0xD5, 0x49, 0x89, 0x1E, 0xF7,
+  0x6, 0x87, 0xDA, 0x89, 0x1E, 0xFD, 0x6, 0x5B, 0x5A, 0x53, 0x89,
+  0x1E, 0xFB, 0x6, 0xE8, 0xD3, 0x0, 0x5A, 0x52, 0xE8, 0x5, 0x0,
+  0x59, 0x41, 0xE9, 0x20, 0x2, 0x8A, 0xC6, 0xA, 0xC0, 0xD0, 0xD8,
+  0x8A, 0xF0, 0x8A, 0xC2, 0xD0, 0xD8, 0x8A, 0xD0, 0xC3, 0x8B, 0x1E,
+  0xF3, 0x6, 0xA0, 0xF5, 0x6, 0xC3, 0x89, 0x1E, 0xF3, 0x6, 0xA2,
+  0xF5, 0x6, 0xC3, 0x8B, 0x1E, 0xF3, 0x6, 0x81, 0xFB, 0x0, 0x20,
+  0x72, 0x9, 0x81, 0xEB, 0x0, 0x20, 0x89, 0x1E, 0xF3, 0x6, 0xC3,
+  0x81, 0xC3, 0x50, 0x20, 0x89, 0x1E, 0xF3, 0x6, 0xC3, 0x8B, 0x1E,
+  0xF3, 0x6, 0x81, 0xFB, 0x0, 0x20, 0x72, 0x9, 0x81, 0xEB, 0xB0,
+  0x1F, 0x89, 0x1E, 0xF3, 0x6, 0xC3, 0x81, 0xC3, 0x0, 0x20, 0x89,
+  0x1E, 0xF3, 0x6, 0xC3, 0x8A, 0xC1, 0x8A, 0xE, 0x55, 0x0, 0xD2,
+  0xE, 0xF5, 0x6, 0x8A, 0xC8, 0x72, 0x1, 0xC3, 0xFF, 0x6, 0xF3,
+  0x6, 0xC3, 0x8A, 0xC1, 0x8A, 0xE, 0x55, 0x0, 0xD2, 0x6, 0xF5,
+  0x6, 0x8A, 0xC8, 0x72, 0x1, 0xC3, 0xFF, 0xE, 0xF3, 0x6, 0xC3,
+  0x8C, 0xC6, 0xBF, 0x0, 0xB8, 0x8E, 0xC7, 0x8B, 0x1E, 0xF3, 0x6,
+  0x26, 0x8A, 0x7, 0x8A, 0x16, 0xF5, 0x6, 0x22, 0xC2, 0x8A, 0xE,
+  0x55, 0x0, 0xD2, 0xEA, 0x72, 0x4, 0xD2, 0xE8, 0xEB, 0xF8, 0x8E,
+  0xC6, 0xC3, 0x8C, 0xC6, 0xBF, 0x0, 0xB8, 0x8E, 0xC7, 0x8B, 0x1E,
+  0xF3, 0x6, 0x8B, 0xE9, 0xA0, 0xF5, 0x6, 0xF6, 0xD0, 0x26, 0x22,
+  0x7, 0x8A, 0xE, 0xF6, 0x6, 0x22, 0xE, 0xF5, 0x6, 0xA, 0xC1,
+  0x26, 0x88, 0x7, 0x8B, 0xCD, 0x8E, 0xC6, 0xC3, 0x8B, 0xE9, 0xD1,
+  0xEA, 0x9F, 0x8B, 0xDA, 0xB1, 0x2, 0xD3, 0xE2, 0x3, 0xD3, 0xB1,
+  0x4, 0xD3, 0xE2, 0x9E, 0x73, 0x4, 0x81, 0xC2, 0x0, 0x20, 0x89,
+  0x16, 0xF3, 0x6, 0x8B, 0xD5, 0x8A, 0xCA, 0xF6, 0x6, 0x55, 0x0,
+  0x1, 0x74, 0x14, 0xB0, 0x7, 0x22, 0xC8, 0xB0, 0x80, 0xD2, 0xE8,
+  0xA2, 0xF5, 0x6, 0xB1, 0x3, 0xD3, 0xEA, 0x1, 0x16, 0xF3, 0x6,
+  0xC3, 0xB0, 0x3, 0x22, 0xC8, 0x2, 0xC9, 0xB0, 0xC0, 0xD2, 0xE8,
+  0xA2, 0xF5, 0x6, 0xB1, 0x2, 0xD3, 0xEA, 0x1, 0x16, 0xF3, 0x6,
+  0xC3, 0xA0, 0x48, 0x0, 0xC7, 0x6, 0x3B, 0x5, 0x64, 0x0, 0x3C,
+  0x6, 0x74, 0x12, 0x73, 0x1C, 0x3C, 0x4, 0x72, 0x18, 0xC6, 0x6,
+  0x55, 0x0, 0x2, 0xC7, 0x6, 0x3D, 0x5, 0xA0, 0x0, 0xC3, 0xC6,
+  0x6, 0x55, 0x0, 0x1, 0xC7, 0x6, 0x3D, 0x5, 0x40, 0x1, 0xC3,
+  0xC6, 0x6, 0x55, 0x0, 0x0, 0xC3, 0x3C, 0x4, 0x73, 0xF, 0xF6,
+  0x6, 0x55, 0x0, 0x1, 0x74, 0xC, 0x24, 0x1, 0xF6, 0xD8, 0xA2,
+  0xF6, 0x6, 0xF8, 0xC3, 0xE9, 0x5D, 0xC5, 0x24, 0x3, 0xB1, 0x55,
+  0xF6, 0xE1, 0xA2, 0xF6, 0x6, 0xF8, 0xC3, 0xA0, 0x55, 0x0, 0xA,
+  0xC0, 0x74, 0xEB, 0xA, 0xED, 0x78, 0x27, 0xBB, 0x80, 0x2, 0x84,
+  0x6, 0x1, 0x0, 0x74, 0x3, 0xBB, 0x40, 0x1, 0x3B, 0xCB, 0x9F,
+  0x72, 0x3, 0x4B, 0x8B, 0xCB, 0xA, 0xF6, 0x78, 0xC, 0x81, 0xFA,
+  0xC8, 0x0, 0x72, 0x4, 0xBA, 0xC7, 0x0, 0xC3, 0x9E, 0xC3, 0x33,
+  0xD2, 0xC3, 0x33, 0xC9, 0x9F, 0xEB, 0xE8, 0x8C, 0xC6, 0xBF, 0x0,
+  0xB8, 0x8E, 0xC7, 0x8B, 0xD3, 0xB, 0xD2, 0x74, 0x6C, 0x8B, 0x1E,
+  0xF3, 0x6, 0x26, 0x8A, 0x2F, 0xA0, 0xF5, 0x6, 0x8A, 0xE0, 0xF6,
+  0xD0, 0x8A, 0xE, 0x55, 0x0, 0x8A, 0x1E, 0xF6, 0x6, 0x22, 0xE8,
+  0x8A, 0xFC, 0x22, 0xFB, 0xA, 0xEF, 0x4A, 0x74, 0x40, 0xD2, 0xC8,
+  0xD2, 0xCC, 0x73, 0xEF, 0x8B, 0x1E, 0xF3, 0x6, 0x26, 0x88, 0x2F,
+  0xFF, 0x6, 0xF3, 0x6, 0x88, 0x26, 0xF5, 0x6, 0x8B, 0xCA, 0xD1,
+  0xE9, 0xD1, 0xE9, 0xF6, 0x6, 0x55, 0x0, 0x1, 0x75, 0x6, 0x81,
+  0xE2, 0x3, 0x0, 0xEB, 0x6, 0x81, 0xE2, 0x7, 0x0, 0xD1, 0xE9,
+  0xE3, 0xAB, 0xFC, 0xA0, 0xF6, 0x6, 0x8B, 0x3E, 0xF3, 0x6, 0xF3,
+  0xAA, 0x89, 0x3E, 0xF3, 0x6, 0xEB, 0x9B, 0x8B, 0x1E, 0xF3, 0x6,
+  0x26, 0x88, 0x2F, 0x88, 0x26, 0xF5, 0x6, 0x8E, 0xC6, 0xC3, 0xE8,
+  0x7F, 0xFE, 0x3, 0x16, 0xFD, 0x6, 0x3B, 0x16, 0xFB, 0x6, 0x72,
+  0x9, 0x2B, 0x16, 0xFB, 0x6, 0x3E, 0xFF, 0x16, 0xF9, 0x6, 0x3E,
+  0xFF, 0x16, 0xF7, 0x6, 0xE2, 0xE3, 0xC3, 0x53, 0xE8, 0xA3, 0xCF,
+  0x5B, 0xC3, 0x53, 0xE8, 0x27, 0x19, 0x5B, 0xC3, 0xF6, 0x80, 0x3E,
+  0x71, 0x0, 0x0, 0x74, 0x3, 0xE9, 0xF9, 0x4, 0xC3, 0xA0, 0x29,
+  0x0, 0x8A, 0xD0, 0xE8, 0xFF, 0xD2, 0xE9, 0xED, 0x4, 0x0, 0x0,
+  0x0, 0xB4, 0xF, 0xCD, 0x10, 0xA2, 0x48, 0x0, 0xB4, 0x28, 0x3C,
+  0x2, 0x72, 0xD, 0xB4, 0x50, 0x3C, 0x7, 0x75, 0x7, 0xB9, 0xC,
+  0xB, 0x89, 0xE, 0x68, 0x0, 0x88, 0x26, 0x29, 0x0, 0xFA, 0x8C,
+  0xDB, 0x89, 0x1E, 0x50, 0x3, 0x1E, 0xBA, 0x0, 0x0, 0x8E, 0xDA,
+  0x89, 0x1E, 0x10, 0x5, 0xBB, 0x34, 0x4D, 0x89, 0x1E, 0x6C, 0x0,
+  0xBB, 0x44, 0x57, 0x89, 0x1E, 0x70, 0x0, 0x8C, 0xE, 0x6E, 0x0,
+  0x8C, 0xE, 0x72, 0x0, 0x1F, 0xE8, 0x32, 0x0, 0xBB, 0x18, 0x2,
+  0xB9, 0x0, 0x0, 0x8E, 0xC1, 0xB9, 0x7A, 0x0, 0x26, 0x8C, 0x8F,
+  0x2, 0x0, 0x26, 0xC7, 0x7, 0x94, 0x4C, 0x83, 0xC3, 0x4, 0xE0,
+  0xF1, 0x8C, 0xDB, 0x8E, 0xC3, 0xE8, 0x48, 0xE1, 0xFB, 0xB4, 0x1,
+  0xCD, 0x17, 0xE8, 0x77, 0x6, 0xBB, 0x9B, 0x4C, 0xE8, 0xDF, 0x2E,
+  0xE9, 0x63, 0x32, 0xBE, 0xED, 0x4C, 0xBB, 0x53, 0x6, 0xB9, 0xA,
+  0x0, 0x53, 0xFC, 0x2E, 0xAC, 0x88, 0x7, 0x43, 0xA, 0xC0, 0x75,
+  0xF6, 0x5B, 0x83, 0xC3, 0x10, 0xE0, 0xEF, 0xC3, 0xCF, 0x3E, 0xFF,
+  0x2E, 0x0, 0x7, 0xCB, 0x54, 0x68, 0x65, 0x20, 0x49, 0x42, 0x4D,
+  0x20, 0x50, 0x65, 0x72, 0x73, 0x6F, 0x6E, 0x61, 0x6C, 0x20, 0x43,
+  0x6F, 0x6D, 0x70, 0x75, 0x74, 0x65, 0x72, 0x20, 0x42, 0x61, 0x73,
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+  0x20, 0x43, 0x31, 0x2E, 0x31, 0x30, 0x20, 0x43, 0x6F, 0x70, 0x79,
+  0x72, 0x69, 0x67, 0x68, 0x74, 0x20, 0x49, 0x42, 0x4D, 0x20, 0x43,
+  0x6F, 0x72, 0x70, 0x20, 0x31, 0x39, 0x38, 0x31, 0xFF, 0xD, 0x0,
+  0x32, 0x35, 0x2D, 0x41, 0x70, 0x72, 0x2D, 0x38, 0x31, 0x4C, 0x49,
+  0x53, 0x54, 0x20, 0x0, 0x52, 0x55, 0x4E, 0xD, 0x0, 0x4C, 0x4F,
+  0x41, 0x44, 0x22, 0x0, 0x53, 0x41, 0x56, 0x45, 0x22, 0x0, 0x43,
+  0x4F, 0x4E, 0x54, 0xD, 0x0, 0x2C, 0x22, 0x4C, 0x50, 0x54, 0x31,
+  0x3A, 0x22, 0xD, 0x0, 0x54, 0x52, 0x4F, 0x4E, 0xD, 0x0, 0x54,
+  0x52, 0x4F, 0x46, 0x46, 0xD, 0x0, 0x4B, 0x45, 0x59, 0x20, 0x0,
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+  0xDA, 0x8E, 0x1E, 0x10, 0x5, 0xE8, 0x3A, 0xA, 0x88, 0x16, 0x6A,
+  0x0, 0xFE, 0xCA, 0x88, 0x16, 0x5E, 0x0, 0x5A, 0x1F, 0x58, 0x9D,
+  0xCF, 0x56, 0xA0, 0x5E, 0x0, 0xA, 0xC0, 0x75, 0x11, 0xA0, 0x6A,
+  0x0, 0xA, 0xC0, 0x75, 0xA, 0xB4, 0x1, 0xCD, 0x16, 0xB0, 0x0,
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+  0x74, 0x8, 0x32, 0xC0, 0xA2, 0x5E, 0x0, 0xB0, 0x3, 0xC3, 0x56,
+  0x57, 0xA0, 0x6A, 0x0, 0xA, 0xC0, 0x75, 0x74, 0xB4, 0x0, 0xCD,
+  0x16, 0xA, 0xC0, 0x74, 0x3, 0x5F, 0x5E, 0xC3, 0x53, 0x80, 0xFC,
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+  0xEB, 0xE0, 0x50, 0x86, 0xC4, 0x2C, 0x3B, 0xB3, 0x10, 0xF6, 0xE3,
+  0xBB, 0x53, 0x6, 0x3, 0xD8, 0xF6, 0x7, 0xFF, 0x58, 0x74, 0xCC,
+  0x89, 0x1E, 0x6B, 0x0, 0x8C, 0x1E, 0x6D, 0x0, 0xFE, 0xE, 0x6A,
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+  0xB0, 0x20, 0xEB, 0xB2, 0x1E, 0xC5, 0x1E, 0x6B, 0x0, 0x8A, 0x7,
+  0x1F, 0xFF, 0x6, 0x6B, 0x0, 0xA, 0xC0, 0x74, 0x2, 0x79, 0xA0,
+  0x32, 0xE4, 0x8C, 0xCB, 0x8A, 0x1E, 0x6E, 0x0, 0x3A, 0xDF, 0x72,
+  0x4, 0xFE, 0xC4, 0x24, 0x7F, 0x88, 0x26, 0x6A, 0x0, 0xA, 0xC0,
+  0x75, 0x88, 0x5B, 0xE9, 0x77, 0x11, 0x1E, 0x30, 0x2E, 0x20, 0x12,
+  0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, 0x32, 0x31, 0x18, 0x19,
+  0x10, 0x13, 0x1F, 0x14, 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x53,
+  0x51, 0x56, 0xBE, 0x6C, 0x4E, 0xB1, 0xE, 0xFC, 0x2E, 0xAC, 0x3A,
+  0xE0, 0x74, 0x9, 0x46, 0xFE, 0xC9, 0x75, 0xF4, 0x32, 0xC0, 0xEB,
+  0x2, 0x2E, 0xAC, 0x5E, 0x59, 0x5B, 0xC3, 0x47, 0xB, 0x48, 0x1E,
+  0x4B, 0x1D, 0x4D, 0x1C, 0x50, 0x1F, 0x1C, 0xA, 0x74, 0x6, 0x73,
+  0x2, 0x76, 0x1, 0x52, 0x12, 0x53, 0x7F, 0x4F, 0xE, 0x75, 0x5,
+  0x77, 0xC, 0x1F, 0x1E, 0x1D, 0x1C, 0xD, 0xC, 0xB, 0xA, 0x9C,
+  0x53, 0x51, 0x52, 0x50, 0x3C, 0x7, 0x74, 0x4D, 0x3C, 0xD, 0x75,
+  0xA, 0xF6, 0x6, 0x6F, 0x0, 0xFF, 0x74, 0x3, 0xE8, 0x8B, 0x0,
+  0xE8, 0x2C, 0x2, 0x74, 0x4, 0x3C, 0xFF, 0x74, 0x39, 0x3C, 0xC,
+  0x74, 0x22, 0xBB, 0x87, 0x4E, 0xB9, 0x8, 0x0, 0x43, 0xFE, 0xC9,
+  0x78, 0x1C, 0x2E, 0x3A, 0x7, 0x75, 0xF6, 0xD0, 0xE1, 0x8B, 0xD9,
+  0xB9, 0xE9, 0x4E, 0x51, 0x2E, 0xFF, 0xB7, 0xE1, 0x2F, 0x8B, 0x1E,
+  0x56, 0x0, 0xC3, 0xE8, 0xE, 0x4, 0xEB, 0xE, 0xE8, 0x3E, 0x0,
+  0xE8, 0xE, 0x0, 0xE8, 0xD, 0xE1, 0xEB, 0x3, 0xE8, 0x24, 0x9,
+  0x58, 0x5A, 0x59, 0x5B, 0x9D, 0xC3, 0x50, 0x8A, 0x3E, 0x49, 0x0,
+  0x8A, 0x1E, 0x4E, 0x0, 0xB9, 0x1, 0x0, 0xB4, 0x9, 0xCD, 0x10,
+  0x58, 0xC3, 0x53, 0xE8, 0x71, 0x0, 0xE8, 0xE7, 0xFF, 0x5B, 0xC3,
+  0x53, 0xE8, 0x68, 0x0, 0xB4, 0x8, 0xCD, 0x10, 0x5B, 0xC3, 0xE8,
+  0xF3, 0xFF, 0x8A, 0xE8, 0x8A, 0xCC, 0xC3, 0x8B, 0x1E, 0x56, 0x0,
+  0x89, 0x1E, 0x56, 0x0, 0x9C, 0x53, 0xE8, 0x4D, 0x0, 0x5B, 0x9D,
+  0xC3, 0xA0, 0x57, 0x0, 0xFE, 0xC8, 0xC3, 0x50, 0x8A, 0xE, 0x29,
+  0x0, 0x2A, 0xE, 0x57, 0x0, 0xFE, 0xC1, 0xB5, 0x0, 0x8A, 0x3E,
+  0x49, 0x0, 0x8A, 0x1E, 0x4F, 0x0, 0xB0, 0x20, 0xB4, 0x9, 0xCD,
+  0x10, 0x8B, 0x16, 0x56, 0x0, 0x86, 0xF2, 0xFE, 0xCE, 0xFE, 0xCA,
+  0xB4, 0x2, 0xCD, 0x10, 0x58, 0xC3, 0x53, 0xE8, 0x15, 0x0, 0x8A,
+  0x3E, 0x49, 0x0, 0x8A, 0x1E, 0x4F, 0x0, 0x8A, 0xE, 0x29, 0x0,
+  0xB5, 0x0, 0xB0, 0x20, 0xB4, 0x9, 0xCD, 0x10, 0x5B, 0x50, 0x52,
+  0x8B, 0xD3, 0x86, 0xF2, 0xFE, 0xCE, 0xFE, 0xCA, 0x8A, 0x3E, 0x49,
+  0x0, 0xB4, 0x2, 0xCD, 0x10, 0x5A, 0x58, 0xC3, 0x53, 0x52, 0xB1,
+  0x0, 0x8A, 0xEF, 0x8A, 0xF3, 0xE8, 0x1B, 0x0, 0xB4, 0x6, 0xCD,
+  0x10, 0xEB, 0xF, 0x53, 0x52, 0xB1, 0x0, 0x8A, 0xEB, 0x8A, 0xF7,
+  0xE8, 0xA, 0x0, 0xB4, 0x7, 0xCD, 0x10, 0xE8, 0x1C, 0x0, 0x5A,
+  0x5B, 0xC3, 0xE8, 0x11, 0x0, 0x8A, 0x16, 0x29, 0x0, 0xFE, 0xCA,
+  0xFE, 0xCE, 0xFE, 0xCD, 0xB0, 0x1, 0x8A, 0x3E, 0x4F, 0x0, 0xC3,
+  0xA0, 0x49, 0x0, 0xEB, 0x3, 0xA0, 0x4A, 0x0, 0xE8, 0x6, 0x1,
+  0x75, 0x20, 0x8A, 0x26, 0x48, 0x0, 0x80, 0xFC, 0x7, 0x74, 0x17,
+  0x52, 0xBA, 0x0, 0x8, 0x80, 0xFC, 0x2, 0x72, 0x2, 0xD0, 0xE6,
+  0x32, 0xE4, 0xF7, 0xE2, 0x1E, 0x8E, 0xDA, 0xA3, 0x4E, 0x4, 0x1F,
+  0x5A, 0xC3, 0x9C, 0x53, 0x52, 0x50, 0xBA, 0x0, 0x0, 0xB4, 0x0,
+  0xCD, 0x17, 0x8A, 0xC4, 0x80, 0xE4, 0x28, 0x80, 0xFC, 0x28, 0x74,
+  0xD, 0xF6, 0xC4, 0x8, 0x75, 0xC, 0xA8, 0x1, 0x74, 0xD, 0xB2,
+  0x18, 0xEB, 0x6, 0xB2, 0x1B, 0xEB, 0x2, 0xB2, 0x19, 0xE9, 0xBA,
+  0xB7, 0x58, 0x50, 0x3C, 0xD, 0xE9, 0x5D, 0xF, 0x58, 0x5A, 0x5B,
+  0x9D, 0xC3, 0x3C, 0x93, 0x74, 0x60, 0x3C, 0x95, 0x74, 0x46, 0x3C,
+  0xDD, 0x74, 0x46, 0xE8, 0xE3, 0xCE, 0xA, 0xC0, 0x74, 0x38, 0xFE,
+  0xC8, 0x3C, 0xA, 0x73, 0x32, 0xBA, 0x10, 0x0, 0xF6, 0xE2, 0x8A,
+  0xD0, 0x81, 0xC2, 0x53, 0x6, 0x52, 0xE8, 0xA2, 0xDD, 0x2C, 0xE8,
+  0xD1, 0xC6, 0x53, 0xE8, 0x4C, 0xD8, 0x8A, 0xF, 0x80, 0xF9, 0xF,
+  0x72, 0x2, 0xB1, 0xF, 0x43, 0x8B, 0x37, 0x5B, 0x5F, 0x53, 0xB5,
+  0x0, 0xFC, 0xF3, 0xA4, 0x88, 0x2D, 0xE8, 0x72, 0xFB, 0x5B, 0xC3,
+  0xE9, 0xE1, 0xBF, 0xB0, 0xFF, 0xEB, 0x2, 0xB0, 0x0, 0x3A, 0x6,
+  0x71, 0x0, 0xA2, 0x71, 0x0, 0x74, 0x3, 0xE8, 0x5E, 0x0, 0xE8,
+  0x90, 0xBE, 0xC3, 0x53, 0xBE, 0x53, 0x6, 0xB9, 0xA, 0x0, 0xFE,
+  0xC5, 0x56, 0xB0, 0x46, 0xE8, 0x8, 0xDB, 0x51, 0x8A, 0xDD, 0xB7,
+  0x0, 0xE8, 0xAB, 0x14, 0xB0, 0x20, 0xE8, 0xFB, 0xDA, 0x59, 0x5E,
+  0x56, 0x51, 0xFC, 0xAC, 0xA, 0xC0, 0x74, 0x5, 0xE8, 0x13, 0x0,
+  0xEB, 0xF5, 0xB0, 0xD, 0xE8, 0xE7, 0xDA, 0x59, 0x5E, 0x83, 0xC6,
+  0x10, 0xFE, 0xC9, 0x75, 0xCE, 0x5B, 0xEB, 0xC0, 0x56, 0x3C, 0xD,
+  0x75, 0x2, 0xB0, 0x1B, 0xE8, 0xD1, 0xDA, 0x5E, 0xC3, 0x50, 0xA0,
+  0x48, 0x0, 0x3C, 0x7, 0x74, 0x4, 0x3C, 0x4, 0x73, 0x2, 0x32,
+  0xC0, 0xA, 0xC0, 0x58, 0xC3, 0x53, 0xCD, 0xAD, 0xB6, 0x18, 0xB2,
+  0x0, 0x8A, 0x3E, 0x49, 0x0, 0xB4, 0x2, 0xCD, 0x10, 0xA0, 0x71,
+  0x0, 0xA, 0xC0, 0x75, 0x13, 0x8A, 0x1E, 0x4F, 0x0, 0x8A, 0xE,
+  0x29, 0x0, 0xB5, 0x0, 0xB4, 0x9, 0xCD, 0x10, 0xE8, 0xD, 0xFE,
+  0x5B, 0xC3, 0xB3, 0x7, 0xE8, 0xC0, 0xFF, 0x75, 0x9, 0xA0, 0x4C,
+  0x0, 0xA, 0xC0, 0x75, 0x2, 0xB3, 0x70, 0xBE, 0x53, 0x6, 0xB5,
+  0x5, 0xA0, 0x29, 0x0, 0x3C, 0x28, 0xB0, 0x31, 0x74, 0x2, 0xB5,
+  0xA, 0x50, 0x53, 0x8A, 0x1E, 0x4E, 0x0, 0xE8, 0x37, 0x0, 0x5B,
+  0x56, 0xB1, 0x6, 0x51, 0xFC, 0xAC, 0xA, 0xC0, 0x9C, 0x56, 0x75,
+  0x2, 0x32, 0xC0, 0xE8, 0x25, 0x0, 0x5E, 0x9D, 0x75, 0x1, 0x4E,
+  0x59, 0xFE, 0xC9, 0x75, 0xE8, 0xE8, 0x16, 0x0, 0x5E, 0x83, 0xC6,
+  0x10, 0x58, 0xFE, 0xC0, 0x3C, 0x3A, 0x72, 0x2, 0xB0, 0x30, 0xFE,
+  0xCD, 0x75, 0xC7, 0xE8, 0xAF, 0xFD, 0x5B, 0xC3, 0x32, 0xC0, 0x53,
+  0xA, 0xC0, 0x75, 0x6, 0xB0, 0x20, 0x8A, 0x1E, 0x4F, 0x0, 0x3C,
+  0xD, 0x75, 0x2, 0xB0, 0x1B, 0x51, 0xB9, 0x1, 0x0, 0xB4, 0x9,
+  0xCD, 0x10, 0xFE, 0xC2, 0xB4, 0x2, 0xCD, 0x10, 0x59, 0x5B, 0xC3,
+  0x8A, 0xE, 0x49, 0x0, 0xB5, 0x0, 0x8A, 0x26, 0x48, 0x0, 0xF6,
+  0xC4, 0x1, 0x74, 0x3, 0x80, 0xCD, 0x80, 0x80, 0xFC, 0x4, 0x72,
+  0x9, 0xFE, 0xC5, 0x80, 0xFC, 0x6, 0x72, 0x2, 0xFE, 0xC5, 0x51,
+  0x3C, 0x2C, 0x74, 0xC, 0xE8, 0x61, 0xCD, 0x59, 0x8A, 0xE8, 0x51,
+  0xE8, 0x5C, 0xBD, 0x74, 0x40, 0xE8, 0x2D, 0xDC, 0x2C, 0x3C, 0x2C,
+  0x74, 0x15, 0xE8, 0x4D, 0xCD, 0xA, 0xC0, 0x74, 0x2, 0xB0, 0x80,
+  0x59, 0x80, 0xE5, 0x3, 0xA, 0xE8, 0x51, 0xE8, 0x3F, 0xBD, 0x74,
+  0x23, 0xE8, 0x10, 0xDC, 0x2C, 0x3C, 0x2C, 0x74, 0xC, 0xE8, 0x30,
+  0xCD, 0x59, 0x8A, 0xC8, 0x51, 0xE8, 0x2B, 0xBD, 0x74, 0xF, 0xE8,
+  0xFC, 0xDB, 0x2C, 0xE8, 0x20, 0xCD, 0x8A, 0xF0, 0x59, 0xEB, 0x6,
+  0xE9, 0x55, 0xBE, 0x59, 0x8A, 0xF1, 0x8A, 0x26, 0x29, 0x0, 0x8A,
+  0xC5, 0x24, 0x7F, 0xA, 0xC0, 0x74, 0xA, 0x32, 0xD2, 0xA, 0xD6,
+  0xA, 0xD1, 0x75, 0xE6, 0xEB, 0x1B, 0x80, 0xFC, 0x28, 0x74, 0xC,
+  0x80, 0xFE, 0x4, 0x73, 0xDA, 0x80, 0xF9, 0x4, 0x72, 0xC, 0xEB,
+  0xD3, 0x80, 0xFE, 0x8, 0x73, 0xCE, 0x80, 0xF9, 0x8, 0x73, 0xC9,
+  0x8A, 0xD1, 0xA, 0xC0, 0x74, 0x20, 0x80, 0x3E, 0x48, 0x0, 0x7,
+  0x74, 0x5C, 0xB1, 0x6, 0x3C, 0x2, 0xB4, 0x50, 0x74, 0x2A, 0xB4,
+  0x28, 0xFE, 0xC9, 0xFE, 0xC8, 0x75, 0xAC, 0xF6, 0xC5, 0x80, 0x75,
+  0x1D, 0xFE, 0xC9, 0xEB, 0x19, 0xB1, 0x2, 0x80, 0xFC, 0x28, 0x74,
+  0x9, 0xF6, 0xC5, 0x80, 0x74, 0xD, 0xFE, 0xC1, 0xEB, 0x9, 0xFE,
+  0xC9, 0xF6, 0xC5, 0x80, 0x75, 0x2, 0xFE, 0xC9, 0x88, 0x26, 0x29,
+  0x0, 0xA1, 0x48, 0x0, 0x88, 0xE, 0x48, 0x0, 0x89, 0x16, 0x49,
+  0x0, 0x3A, 0xC1, 0x74, 0x1A, 0xB8, 0x7, 0x0, 0xA3, 0x4B, 0x0,
+  0x86, 0xC4, 0xA3, 0x4D, 0x0, 0x88, 0x26, 0x4F, 0x0, 0xE8, 0x3A,
+  0xFE, 0x74, 0x3, 0xA2, 0x4F, 0x0, 0xE8, 0x6E, 0x0, 0xA0, 0x4A,
+  0x0, 0xB4, 0x5, 0xCD, 0x10, 0xC3, 0x3A, 0x6, 0x29, 0x0, 0x74,
+  0x34, 0x8A, 0x26, 0x48, 0x0, 0x3C, 0x50, 0x74, 0x7, 0x3C, 0x28,
+  0x74, 0x3, 0xE9, 0x98, 0xBD, 0x80, 0xFC, 0x7, 0x75, 0x4, 0xB0,
+  0x50, 0xEB, 0x1C, 0x80, 0xF4, 0x2, 0x80, 0xFC, 0x7, 0x75, 0x2,
+  0xFE, 0xCC, 0x50, 0xA2, 0x29, 0x0, 0x88, 0x26, 0x48, 0x0, 0xC7,
+  0x6, 0x49, 0x0, 0x0, 0x0, 0xE8, 0x2D, 0x0, 0x58, 0xC3, 0x53,
+  0xE8, 0xDA, 0xFC, 0xB2, 0x27, 0x80, 0x3E, 0x29, 0x0, 0x28, 0x74,
+  0x2, 0xB2, 0x4F, 0xB6, 0x18, 0x8A, 0x3E, 0x4F, 0x0, 0xB9, 0x0,
+  0x0, 0x8A, 0xC1, 0xB4, 0x6, 0xCD, 0x10, 0xBA, 0x0, 0x0, 0x8A,
+  0x3E, 0x49, 0x0, 0xB4, 0x2, 0xCD, 0x10, 0xEB, 0xF, 0x53, 0xB9,
+  0x0, 0x0, 0x89, 0xE, 0x49, 0x0, 0xA0, 0x48, 0x0, 0xB4, 0x0,
+  0xCD, 0x10, 0xE8, 0xBD, 0xDD, 0xE8, 0xC9, 0xF8, 0xE8, 0x8A, 0xF7,
+  0xE8, 0x9D, 0xFC, 0x5B, 0xC3, 0xE8, 0xA4, 0xFD, 0x74, 0x5B, 0xB1,
+  0x0, 0xBE, 0x51, 0x0, 0x80, 0x3E, 0x48, 0x0, 0x6, 0x75, 0x3,
+  0xE9, 0x16, 0xBD, 0x8A, 0x2C, 0x56, 0x51, 0xE8, 0xD4, 0xBB, 0x74,
+  0x40, 0x3C, 0x2C, 0x74, 0x7, 0xE8, 0xC9, 0xCB, 0x59, 0x8A, 0xE8,
+  0x51, 0x59, 0x51, 0x53, 0x8A, 0xF9, 0x8A, 0xDD, 0x80, 0xFF, 0x0,
+  0x75, 0x8, 0x80, 0xFB, 0x8, 0x72, 0x3, 0x80, 0xCB, 0x10, 0xB4,
+  0xB, 0xCD, 0x10, 0x5B, 0xE8, 0xAB, 0xBB, 0x74, 0x3, 0xE8, 0xA5,
+  0xBB, 0x59, 0x5E, 0x88, 0x2C, 0x74, 0x8, 0x46, 0xFE, 0xC1, 0x80,
+  0xF9, 0x4, 0x72, 0xBD, 0xC6, 0x6, 0x4F, 0x0, 0x0, 0xC3, 0x59,
+  0x5E, 0xC3, 0xFF, 0x36, 0x4D, 0x0, 0xFF, 0x36, 0x4B, 0x0, 0x3C,
+  0x2C, 0x74, 0x10, 0xE8, 0x7E, 0xCB, 0x3C, 0x20, 0x73, 0x18, 0x59,
+  0x8A, 0xC8, 0x51, 0xE8, 0x75, 0xBB, 0x74, 0x2C, 0xE8, 0x46, 0xDA,
+  0x2C, 0x3C, 0x2C, 0x74, 0x13, 0xE8, 0x66, 0xCB, 0x3C, 0x10, 0x72,
+  0x3, 0xE9, 0x9C, 0xBC, 0x59, 0x8A, 0xE8, 0x51, 0xE8, 0x5A, 0xBB,
+  0x74, 0x11, 0xE8, 0x2B, 0xDA, 0x2C, 0xE8, 0x4F, 0xCB, 0x3C, 0x10,
+  0x73, 0xE9, 0x59, 0x5A, 0x8A, 0xD0, 0x52, 0x51, 0x59, 0x5A, 0x8A,
+  0xF1, 0x80, 0xE6, 0xF, 0x89, 0xE, 0x4B, 0x0, 0x8A, 0xC5, 0xD0,
+  0xE0, 0x24, 0x10, 0xA, 0xC2, 0x80, 0xE5, 0x7, 0xD0, 0xE5, 0xD0,
+  0xE5, 0xD0, 0xE5, 0xD0, 0xE5, 0xF6, 0xC1, 0x10, 0x74, 0x3, 0x80,
+  0xCD, 0x80, 0xA, 0xEE, 0x53, 0x8A, 0xD8, 0xB7, 0x0, 0x24, 0xF,
+  0xA2, 0x4D, 0x0, 0x88, 0x2E, 0x4E, 0x0, 0x88, 0x2E, 0x4F, 0x0,
+  0xB4, 0xB, 0xCD, 0x10, 0x5B, 0xC3, 0xFF, 0x36, 0x56, 0x0, 0x3C,
+  0x2C, 0x74, 0x20, 0xE8, 0xFA, 0xCA, 0xA, 0xC0, 0x74, 0x5B, 0x3C,
+  0x1A, 0x73, 0x57, 0x8A, 0x26, 0x71, 0x0, 0xA, 0xE4, 0x74, 0x4,
+  0x3C, 0x19, 0x73, 0x4B, 0x5A, 0x8A, 0xD0, 0x52, 0xE8, 0xE1, 0xBA,
+  0x74, 0x7B, 0xE8, 0xB2, 0xD9, 0x2C, 0x3C, 0x2C, 0x74, 0x18, 0xE8,
+  0xD2, 0xCA, 0xA, 0xC0, 0x74, 0x33, 0x8A, 0x26, 0x29, 0x0, 0x3A,
+  0xE0, 0x72, 0x2B, 0x5A, 0x8A, 0xF0, 0x52, 0xE8, 0xC1, 0xBA, 0x74,
+  0x5B, 0xFF, 0x36, 0x68, 0x0, 0xE8, 0x8E, 0xD9, 0x2C, 0x3C, 0x2C,
+  0x74, 0x19, 0xE8, 0xAE, 0xCA, 0xA, 0xC0, 0xB0, 0x0, 0x75, 0x2,
+  0xB0, 0x20, 0x59, 0xA, 0xE8, 0x51, 0xE8, 0xA1, 0xBA, 0x74, 0x2D,
+  0xEB, 0x3, 0xE9, 0xD5, 0xBB, 0xE8, 0x6D, 0xD9, 0x2C, 0xE8, 0x91,
+  0xCA, 0x3C, 0x20, 0x73, 0xF2, 0x59, 0x80, 0xE5, 0x20, 0xA, 0xE8,
+  0x8A, 0xC8, 0x51, 0xE8, 0x83, 0xBA, 0x74, 0xF, 0xE8, 0x54, 0xD9,
+  0x2C, 0xE8, 0x78, 0xCA, 0x3C, 0x20, 0x73, 0xD9, 0x59, 0x8A, 0xC8,
+  0x51, 0x59, 0x51, 0x80, 0xE5, 0xF, 0x89, 0xE, 0x68, 0x0, 0x59,
+  0xB4, 0x1, 0xCD, 0x10, 0x5A, 0x89, 0x16, 0x56, 0x0, 0x86, 0xF2,
+  0xFE, 0xCE, 0xFE, 0xCA, 0x53, 0x8A, 0x3E, 0x49, 0x0, 0xB4, 0x2,
+  0xCD, 0x10, 0x5B, 0xC3, 0x50, 0xB0, 0x0, 0xEB, 0x3, 0x50, 0xB0,
+  0x20, 0x9C, 0x51, 0x53, 0x50, 0xE8, 0x3D, 0xFA, 0x58, 0x5B, 0x8B,
+  0xE, 0x68, 0x0, 0xF6, 0x6, 0x72, 0x0, 0xFF, 0x74, 0x2, 0xB5,
+  0x4, 0xA, 0xE8, 0xB4, 0x1, 0xCD, 0x10, 0x59, 0x9D, 0x58, 0xC3,
+  0x0, 0x0, 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0x9C, 0xE8, 0xC9, 0xFB, 0x74,
+  0x4B, 0x53, 0x51, 0x52, 0x8C, 0xC6, 0xBF, 0x0, 0x0, 0x8E, 0xC7,
+  0x26, 0xFF, 0x36, 0x7C, 0x0, 0x26, 0xFF, 0x36, 0x7E, 0x0, 0x26,
+  0xC7, 0x6, 0x7C, 0x0, 0xF8, 0x54, 0x26, 0x8C, 0xE, 0x7E, 0x0,
+  0x8E, 0xC6, 0xB0, 0x81, 0x2, 0x6, 0x72, 0x0, 0xB3, 0x83, 0x8A,
+  0x3E, 0x49, 0x0, 0xB9, 0x1, 0x0, 0xB4, 0x9, 0xCD, 0x10, 0x8C,
+  0xC6, 0xBF, 0x0, 0x0, 0x8E, 0xC7, 0x26, 0x8F, 0x6, 0x7E, 0x0,
+  0x26, 0x8F, 0x6, 0x7C, 0x0, 0x8E, 0xC6, 0x5A, 0x59, 0x5B, 0x9D,
+  0x58, 0xC3, 0xE8, 0xBD, 0xB9, 0xA0, 0x56, 0x0, 0xE9, 0x72, 0xF6,
+  0xE8, 0xB4, 0xB9, 0xE8, 0x65, 0x0, 0xA, 0xEE, 0x75, 0x56, 0xA,
+  0xEA, 0xA, 0xE9, 0x74, 0x50, 0x8A, 0x26, 0x29, 0x0, 0x3A, 0xE2,
+  0x72, 0x48, 0x80, 0xF9, 0x1A, 0x73, 0x43, 0xA0, 0x71, 0x0, 0xA,
+  0xC0, 0x74, 0x5, 0x80, 0xF9, 0x19, 0x73, 0x37, 0x53, 0x8A, 0xF1,
+  0xFE, 0xCE, 0xFE, 0xCA, 0x8A, 0x3E, 0x49, 0x0, 0xB4, 0x2, 0xCD,
+  0x10, 0xB4, 0x8, 0xCD, 0x10, 0x5B, 0x50, 0xE8, 0x77, 0xB9, 0x3C,
+  0x2C, 0x74, 0x4, 0xB0, 0x0, 0xEB, 0x7, 0xE8, 0x42, 0xD8, 0x2C,
+  0xE8, 0x66, 0xC9, 0x50, 0xE8, 0x3A, 0xD8, 0x29, 0x58, 0xA, 0xC0,
+  0x58, 0x74, 0x2, 0x8A, 0xC4, 0xE9, 0x12, 0xF6, 0xE9, 0x90, 0xBA,
+  0xE8, 0x5, 0x0, 0xE8, 0x25, 0xD8, 0x29, 0xC3, 0xE8, 0x20, 0xD8,
+  0x28, 0xE8, 0x32, 0xC9, 0x52, 0xE8, 0x18, 0xD8, 0x2C, 0xE8, 0x2A,
+  0xC9, 0x59, 0xC3, 0xE8, 0x38, 0xB9, 0x3C, 0x95, 0x74, 0x8, 0xE8,
+  0x8, 0xD8, 0xDD, 0x32, 0xC0, 0xEB, 0x5, 0xE8, 0x29, 0xB9, 0xB0,
+  0xFF, 0xA2, 0x34, 0x0, 0xC3, 0xA0, 0x34, 0x0, 0xA, 0xC0, 0x74,
+  0x30, 0xE8, 0x1B, 0xC9, 0x3C, 0xA, 0x73, 0x29, 0x53, 0x56, 0xBA,
+  0x1A, 0x56, 0x52, 0x32, 0xE4, 0xD1, 0xE0, 0x8B, 0xF0, 0x2E, 0xFF,
+  0xB4, 0x1D, 0x56, 0xC3, 0x5E, 0x5B, 0xC3, 0x34, 0x56, 0x3F, 0x56,
+  0x46, 0x56, 0x4C, 0x56, 0x6B, 0x56, 0x72, 0x56, 0x78, 0x56, 0x80,
+  0x56, 0x88, 0x56, 0x90, 0x56, 0xE9, 0x25, 0xBA, 0xBB, 0x35, 0x0,
+  0x8A, 0x7, 0xC6, 0x7, 0x0, 0xE9, 0x9F, 0xF5, 0x8B, 0x1E, 0x37,
+  0x0, 0xE9, 0xC6, 0xE, 0xA0, 0x39, 0x0, 0xE9, 0x8C, 0xF5, 0xB4,
+  0x4, 0xCD, 0x10, 0x50, 0xA, 0xE4, 0x74, 0xC, 0x89, 0x1E, 0x3A,
+  0x0, 0x88, 0x2E, 0x3C, 0x0, 0x89, 0x16, 0x3F, 0x0, 0x58, 0x8A,
+  0xC4, 0xFE, 0xC8, 0xF6, 0xD0, 0xE9, 0x73, 0xF5, 0x8B, 0x1E, 0x3A,
+  0x0, 0xE9, 0x9A, 0xE, 0xA0, 0x3C, 0x0, 0xE9, 0x60, 0xF5, 0xA0,
+  0x3E, 0x0, 0xFE, 0xC0, 0xE9, 0x58, 0xF5, 0xA0, 0x3D, 0x0, 0xFE,
+  0xC0, 0xE9, 0x50, 0xF5, 0xA0, 0x40, 0x0, 0xFE, 0xC0, 0xE9, 0x48,
+  0xF5, 0xA0, 0x3F, 0x0, 0xFE, 0xC0, 0xE9, 0x40, 0xF5, 0xE8, 0x84,
+  0xC8, 0xA, 0xC0, 0x74, 0x12, 0x3C, 0x4, 0x73, 0x54, 0xB4, 0x0,
+  0x53, 0xBB, 0x41, 0x0, 0x3, 0xD8, 0x8A, 0x7, 0x5B, 0xE9, 0x27,
+  0xF5, 0x53, 0xBA, 0x1, 0x2, 0xB9, 0x1, 0x1, 0xBB, 0xF, 0x0,
+  0xFA, 0xEE, 0xEC, 0x24, 0xF, 0x3A, 0xC3, 0xE1, 0xF9, 0xE3, 0xB,
+  0x32, 0xC3, 0x8A, 0xE1, 0x50, 0xFE, 0xC7, 0x32, 0xD8, 0xEB, 0xEC,
+  0xA, 0xFF, 0x74, 0x1A, 0x8A, 0xD7, 0xBB, 0x41, 0x0, 0xB9, 0x4,
+  0x0, 0x58, 0xF6, 0xD4, 0x2, 0xE2, 0xD0, 0xE8, 0x73, 0x2, 0x88,
+  0x27, 0x43, 0xE2, 0xF7, 0xFE, 0xCA, 0x75, 0xE8, 0xFB, 0x5B, 0xA0,
+  0x41, 0x0, 0xE9, 0xE1, 0xF4, 0xE9, 0x5F, 0xB9, 0xE8, 0x20, 0xB8,
+  0x3C, 0x95, 0x74, 0x8, 0xE8, 0xF0, 0xD6, 0xDD, 0x32, 0xC0, 0xEB,
+  0x5, 0xE8, 0x11, 0xB8, 0xB0, 0xFF, 0xA2, 0x45, 0x0, 0xC3, 0xA0,
+  0x45, 0x0, 0xA, 0xC0, 0x74, 0xDE, 0xE8, 0x3, 0xC8, 0x3C, 0x4,
+  0x73, 0xD7, 0xA8, 0x1, 0x74, 0xE, 0xB4, 0x10, 0xFE, 0xC8, 0x74,
+  0x2, 0xB4, 0x40, 0xE8, 0xD0, 0x0, 0xE9, 0xAC, 0xF4, 0x53, 0xBB,
+  0x46, 0x0, 0xA, 0xC0, 0x74, 0x1, 0x43, 0x8A, 0x7, 0xC6, 0x7,
+  0x0, 0x5B, 0xE9, 0x9A, 0xF4, 0x9C, 0x50, 0x55, 0x56, 0x57, 0x1E,
+  0xBA, 0x0, 0x0, 0x8E, 0xDA, 0x8E, 0x1E, 0x10, 0x5, 0xA1, 0x66,
+  0x0, 0xA, 0xC4, 0x74, 0x9, 0xFF, 0xE, 0x66, 0x0, 0x75, 0x3,
+  0xE8, 0x27, 0x0, 0xA0, 0x34, 0x0, 0xA, 0xC0, 0x74, 0x3, 0xE8,
+  0x36, 0x0, 0xA0, 0x45, 0x0, 0xA, 0xC0, 0x74, 0x3, 0xE8, 0x69,
+  0x0, 0x1F, 0x5F, 0x5E, 0x5D, 0x58, 0x9D, 0xCF, 0xC6, 0x6, 0x65,
+  0x0, 0x0, 0xA1, 0x66, 0x0, 0xB, 0xC0, 0x74, 0x18, 0x52, 0xFA,
+  0xF6, 0x6, 0x65, 0x0, 0xFF, 0x75, 0x7, 0xBA, 0x61, 0x0, 0xEC,
+  0x24, 0xFC, 0xEE, 0xC7, 0x6, 0x66, 0x0, 0x0, 0x0, 0xFB, 0x5A,
+  0xC3, 0x53, 0x51, 0x52, 0xB4, 0x4, 0xCD, 0x10, 0x50, 0xA, 0xE4,
+  0x74, 0xC, 0x89, 0x1E, 0x3A, 0x0, 0x88, 0x2E, 0x3C, 0x0, 0x89,
+  0x16, 0x3F, 0x0, 0x58, 0xA0, 0x36, 0x0, 0x32, 0xC4, 0x74, 0x19,
+  0xA, 0xE4, 0x88, 0x26, 0x36, 0x0, 0x74, 0x11, 0x89, 0x1E, 0x37,
+  0x0, 0x88, 0x2E, 0x39, 0x0, 0x89, 0x16, 0x3D, 0x0, 0xB0, 0xFF,
+  0xA2, 0x35, 0x0, 0x5A, 0x59, 0x5B, 0xC3, 0x53, 0xBB, 0x46, 0x0,
+  0x80, 0x3F, 0x0, 0x75, 0x7, 0xB4, 0x10, 0xE8, 0x11, 0x0, 0x88,
+  0x7, 0x43, 0x80, 0x3F, 0x0, 0x75, 0x7, 0xB4, 0x40, 0xE8, 0x4,
+  0x0, 0x88, 0x7, 0x5B, 0xC3, 0x52, 0xBA, 0x1, 0x2, 0xEC, 0x22,
+  0xC4, 0xFE, 0xC8, 0x98, 0x8A, 0xC4, 0x5A, 0xC3, 0xE8, 0x9, 0x0,
+  0xB8, 0xD3, 0x5, 0xBA, 0x4, 0x0, 0x52, 0xEB, 0x38, 0x8B, 0x16,
+  0x66, 0x0, 0xA, 0xF2, 0x74, 0x7, 0xC6, 0x6, 0x65, 0x0, 0xFF,
+  0xEB, 0xF1, 0xC3, 0xE8, 0xDE, 0xC6, 0x83, 0xFA, 0x25, 0x72, 0x12,
+  0x52, 0xE8, 0xBF, 0xD5, 0x2C, 0xE8, 0x71, 0xCA, 0x59, 0x52, 0xB,
+  0xD2, 0x75, 0x7, 0x5A, 0xE9, 0x3B, 0xFF, 0xE9, 0x13, 0xB8, 0xE8,
+  0xD0, 0xFF, 0xBA, 0x12, 0x0, 0xB8, 0xDC, 0x34, 0xF7, 0xF1, 0xF6,
+  0x6, 0x65, 0x0, 0xFF, 0x75, 0x8, 0x50, 0xBA, 0x43, 0x0, 0xB0,
+  0xB6, 0xEE, 0x58, 0xBA, 0x42, 0x0, 0xEE, 0x8A, 0xC4, 0xEE, 0x75,
+  0x7, 0xBA, 0x61, 0x0, 0xEC, 0xC, 0x3, 0xEE, 0x5A, 0x89, 0x16,
+  0x66, 0x0, 0xC6, 0x6, 0x65, 0x0, 0x0, 0xC3, 0xA, 0x5A, 0x4D,
+  0x41, 0x59, 0x10, 0x59, 0x10, 0x19, 0x5A, 0x59, 0x10, 0x59, 0x10,
+  0x59, 0x10, 0x59, 0x10, 0x2D, 0x5A, 0x59, 0x10, 0x34, 0x5A, 0x4D,
+  0x41, 0x59, 0x10, 0x45, 0x5A, 0x59, 0x10, 0x59, 0x10, 0x59, 0x10,
+  0x59, 0x10, 0x59, 0x10, 0x59, 0x10, 0x5D, 0x5A, 0x63, 0x5A, 0x4D,
+  0x41, 0x59, 0x10, 0x7C, 0x5A, 0x59, 0x10, 0x59, 0x10, 0x59, 0x10,
+  0x59, 0x10, 0x59, 0x10, 0x59, 0x10, 0xAA, 0x5A, 0xB1, 0x5A, 0x6E,
+  0x5B, 0x59, 0x10, 0xAB, 0x5B, 0xF0, 0x5B, 0x59, 0x10, 0x59, 0x10,
+  0x6C, 0x5C, 0x59, 0x10, 0x76, 0x5C, 0x59, 0x10, 0x22, 0xC2, 0x75,
+  0x22, 0x9C, 0x50, 0x53, 0x89, 0x1E, 0xE9, 0x4, 0x88, 0x17, 0x83,
+  0xC3, 0x2D, 0xC6, 0x7, 0x0, 0x43, 0x43, 0x88, 0x2F, 0x43, 0xC6,
+  0x7, 0x0, 0x43, 0x88, 0xF, 0x43, 0xC6, 0x7, 0x0, 0x5B, 0x58,
+  0x9D, 0xC3, 0xE9, 0x98, 0xAE, 0x58, 0x5B, 0xC3, 0x80, 0xFA, 0x80,
+  0x75, 0x2, 0xB2, 0x2, 0xC3, 0x58, 0x86, 0xC4, 0x9E, 0x59, 0x5A,
+  0x5B, 0xC3, 0x5A, 0x5B, 0x59, 0xC3, 0x83, 0xC3, 0x2E, 0x8A, 0x7,
+  0xF6, 0xD0, 0xC3, 0x8B, 0x1E, 0xE9, 0x4, 0x83, 0xC3, 0x2B, 0xC3,
+  0x8B, 0x1E, 0xE9, 0x4, 0x83, 0xC3, 0x32, 0xC3, 0x8B, 0x1E, 0xE9,
+  0x4, 0x8A, 0x87, 0x2F, 0x0, 0xC3, 0x56, 0x57, 0x51, 0xC6, 0x6,
+  0x3F, 0x5, 0xA5, 0xBE, 0xF0, 0x4, 0xBF, 0x40, 0x5, 0xB9, 0x8,
+  0x0, 0xFC, 0xA4, 0xE2, 0xFD, 0x59, 0x5F, 0x5E, 0xC3, 0x53, 0x51,
+  0xBB, 0x40, 0x5, 0xB1, 0x8, 0x80, 0x3F, 0x20, 0x75, 0xD, 0x43,
+  0xFE, 0xC9, 0x75, 0xF6, 0xBE, 0x5C, 0x5, 0xBF, 0x48, 0x5, 0xEB,
+  0x10, 0xBE, 0x54, 0x5, 0xBF, 0x40, 0x5, 0xB1, 0x8, 0xFC, 0xA6,
+  0x75, 0x27, 0xFE, 0xC9, 0x75, 0xF9, 0x8A, 0x5, 0x3A, 0x4, 0x74,
+  0x9, 0xA, 0xC0, 0x75, 0x19, 0xF6, 0x4, 0x1, 0x75, 0x14, 0x8A,
+  0x4, 0x8B, 0x1E, 0xE9, 0x4, 0x88, 0x87, 0x31, 0x0, 0xBB, 0xF4,
+  0x59, 0xE8, 0xE, 0x0, 0x32, 0xC0, 0xEB, 0x7, 0xBB, 0xFE, 0x59,
+  0xE8, 0x4, 0x0, 0xF9, 0x59, 0x5B, 0xC3, 0x53, 0x8B, 0x1E, 0x2E,
+  0x0, 0x43, 0xB, 0xDB, 0x74, 0x2, 0x5B, 0xC3, 0xBB, 0x53, 0x5,
+  0x53, 0x43, 0xB1, 0x8, 0x8A, 0x7, 0xE8, 0xD5, 0xF4, 0x43, 0xFE,
+  0xC9, 0x75, 0xF6, 0xB0, 0x2E, 0xE8, 0xCB, 0xF4, 0x5B, 0x83, 0xC3,
+  0x9, 0xB0, 0x44, 0xF6, 0x7, 0xE1, 0x74, 0x17, 0xB0, 0x50, 0xF6,
+  0x7, 0x20, 0x75, 0x10, 0xB0, 0x42, 0xF6, 0x7, 0x80, 0x75, 0x9,
+  0xB0, 0x41, 0xF6, 0x7, 0x40, 0x75, 0x2, 0xB0, 0x4D, 0x5B, 0xE8,
+  0xA5, 0xF4, 0x2E, 0x8A, 0x7, 0x43, 0xA, 0xC0, 0x75, 0xF5, 0xC3,
+  0x20, 0x46, 0x6F, 0x75, 0x6E, 0x64, 0x2E, 0xFF, 0xD, 0x0, 0x20,
+  0x53, 0x6B, 0x69, 0x70, 0x70, 0x65, 0x64, 0x2E, 0xFF, 0xD, 0x0,
+  0xB9, 0x0, 0x0, 0x88, 0xE, 0x52, 0x5, 0xB0, 0xEA, 0xE8, 0xBD,
+  0xFE, 0xE9, 0xE3, 0xFE, 0xBB, 0x52, 0x5, 0x8A, 0x7, 0xC6, 0x7,
+  0x0, 0xA, 0xC0, 0x75, 0x5, 0xE8, 0x46, 0xF3, 0xA, 0xC0, 0xE9,
+  0xE2, 0xFE, 0x88, 0xE, 0x52, 0x5, 0xE9, 0xA3, 0xEB, 0xE8, 0xC8,
+  0xFE, 0x8A, 0x2E, 0x29, 0x0, 0xB1, 0x0, 0xB0, 0xED, 0xE8, 0x91,
+  0xFE, 0xE9, 0xB7, 0xFE, 0x58, 0x50, 0x86, 0xC4, 0xE8, 0x44, 0xF4,
+  0x8A, 0xE, 0x57, 0x0, 0xFE, 0xC9, 0x8B, 0x1E, 0xE9, 0x4, 0x88,
+  0x8F, 0x32, 0x0, 0xE9, 0xAA, 0xFE, 0x58, 0x86, 0xC4, 0xE9, 0x49,
+  0xF8, 0x8A, 0x2E, 0x62, 0x0, 0xB1, 0x0, 0xE8, 0x93, 0xFE, 0xB0,
+  0x6D, 0xE8, 0x62, 0xFE, 0xE8, 0xAF, 0xFE, 0xA0, 0x63, 0x0, 0x88,
+  0x7, 0xE9, 0x80, 0xFE, 0x58, 0x50, 0x86, 0xC4, 0xE8, 0x3, 0x0,
+  0xE9, 0x81, 0xFE, 0xE8, 0x6A, 0xF5, 0xBB, 0x63, 0x0, 0x3C, 0xD,
+  0x75, 0x3, 0xE9, 0xE4, 0x4, 0x3C, 0x20, 0x73, 0x1, 0xC3, 0xFE,
+  0x7, 0x53, 0xE8, 0x8D, 0xFE, 0x5B, 0xFE, 0xC0, 0x74, 0xF4, 0xFE,
+  0xC8, 0x38, 0x7, 0xE9, 0xC5, 0x4, 0x58, 0x86, 0xC4, 0xA2, 0x62,
+  0x0, 0xC3, 0xA0, 0x61, 0x0, 0xA, 0xC0, 0x74, 0x3, 0xE9, 0xE8,
+  0xAC, 0x80, 0xE2, 0xFB, 0x75, 0x2, 0xB2, 0x1, 0xA2, 0x51, 0x5,
+  0xFE, 0xC0, 0xA2, 0x50, 0x5, 0x8A, 0xCA, 0x80, 0xE1, 0x80, 0x80,
+  0xE9, 0x1, 0xF5, 0x1A, 0xC9, 0x80, 0xE1, 0x80, 0xF6, 0xC2, 0x10,
+  0x74, 0x3, 0x80, 0xC9, 0x20, 0xA0, 0x60, 0x0, 0xA, 0xC0, 0x74,
+  0x2, 0xB1, 0x1, 0xA, 0xC9, 0x75, 0x9, 0xF6, 0x6, 0x5F, 0x0,
+  0xFF, 0x74, 0x2, 0xB1, 0x40, 0x88, 0xE, 0x48, 0x5, 0xB5, 0xFF,
+  0xB0, 0x68, 0xE8, 0xD2, 0xFD, 0x8A, 0x27, 0xE8, 0x2E, 0xFE, 0xF6,
+  0xC4, 0x1, 0x75, 0xC, 0xF6, 0xC1, 0x81, 0x75, 0x3, 0xE8, 0x2F,
+  0x0, 0xB0, 0xFF, 0xEB, 0x1F, 0xE8, 0x33, 0x0, 0xE8, 0x30, 0xFE,
+  0x72, 0xF8, 0x8B, 0x1E, 0xE9, 0x4, 0xF6, 0x87, 0x31, 0x0, 0x81,
+  0x75, 0xA, 0xE8, 0x11, 0x1, 0x73, 0x5, 0xC6, 0x6, 0x50, 0x5,
+  0x0, 0xB0, 0x1, 0xA2, 0x61, 0x0, 0xE8, 0xE7, 0xFD, 0xC6, 0x7,
+  0x1, 0xE9, 0xBA, 0xFD, 0xBB, 0x3F, 0x5, 0xB9, 0x11, 0x0, 0xB4,
+  0x3, 0xCD, 0x15, 0xC3, 0xBB, 0x53, 0x5, 0xB9, 0x11, 0x0, 0x53,
+  0xB4, 0x2, 0xCD, 0x15, 0x73, 0x3, 0xE9, 0x2, 0x1, 0x5B, 0xA0,
+  0x5E, 0x0, 0xA, 0xC0, 0x75, 0x6, 0x80, 0x3F, 0xA5, 0x75, 0xE6,
+  0xC3, 0xE9, 0x29, 0xAC, 0xA0, 0x61, 0x0, 0xFE, 0xC0, 0x74, 0xB,
+  0x32, 0xC0, 0xA2, 0x61, 0x0, 0xA2, 0x60, 0x0, 0xE9, 0xCD, 0xE5,
+  0x8B, 0x1E, 0xE9, 0x4, 0xF6, 0x87, 0x31, 0x0, 0x81, 0x75, 0xEA,
+  0xE8, 0x3B, 0x0, 0xE8, 0x1F, 0x1, 0xEB, 0xE2, 0x53, 0xBB, 0x61,
+  0x0, 0x38, 0x27, 0x75, 0xD, 0x8B, 0x1E, 0xE9, 0x4, 0xF6, 0x87,
+  0x31, 0x0, 0x81, 0x5B, 0x75, 0x1, 0xC3, 0xE9, 0xE9, 0xAB, 0xB4,
+  0xFF, 0xE8, 0xE3, 0xFF, 0x58, 0x50, 0x86, 0xC4, 0xE8, 0x3, 0x0,
+  0xE9, 0x4D, 0xFD, 0xE8, 0x26, 0x0, 0x88, 0x7, 0xFE, 0xC1, 0x74,
+  0xB, 0xE8, 0x5D, 0xFD, 0x88, 0xF, 0xC3, 0xE8, 0x57, 0xFD, 0x8A,
+  0xF, 0xBB, 0x53, 0x5, 0xB5, 0x0, 0xFE, 0xC9, 0x41, 0x88, 0xF,
+  0xB4, 0x3, 0xCD, 0x15, 0xE8, 0x44, 0xFD, 0xC6, 0x7, 0x1, 0xC3,
+  0xE8, 0x3D, 0xFD, 0x8A, 0xF, 0xB5, 0x0, 0xBB, 0x53, 0x5, 0x3,
+  0xD9, 0xC3, 0xB4, 0x1, 0xE8, 0x9E, 0xFF, 0xE8, 0x3, 0x0, 0xE9,
+  0x14, 0xFD, 0xA0, 0x50, 0x5, 0x2C, 0x1, 0x73, 0x1, 0xC3, 0xBB,
+  0x51, 0x5, 0x8A, 0x7, 0xC6, 0x7, 0x0, 0xA, 0xC0, 0x74, 0x1,
+  0xC3, 0xE8, 0xA, 0x0, 0x73, 0x7, 0xC6, 0x6, 0x50, 0x5, 0x0,
+  0xA, 0xC0, 0xC3, 0xE8, 0xC3, 0xFF, 0x8A, 0x7, 0xFE, 0xC1, 0xE8,
+  0xFC, 0xFC, 0x88, 0xF, 0xE8, 0xEF, 0xFC, 0x3A, 0xF, 0x74, 0x3,
+  0xA, 0xC0, 0xC3, 0x80, 0x3F, 0x0, 0x75, 0xDD, 0x50, 0xE8, 0x2,
+  0x0, 0x58, 0xC3, 0xBB, 0x53, 0x5, 0xB9, 0x0, 0x1, 0xB4, 0x2,
+  0xCD, 0x15, 0x72, 0x15, 0xA0, 0x53, 0x5, 0xE8, 0xCB, 0xFC, 0x88,
+  0x7, 0xE8, 0xCE, 0xFC, 0xC6, 0x7, 0x1, 0xFE, 0xC8, 0xF9, 0x74,
+  0x1, 0xF8, 0xC3, 0x80, 0xFC, 0x4, 0x75, 0x5, 0xB2, 0x18, 0xE9,
+  0x6F, 0xAB, 0xE9, 0x25, 0xAB, 0xA0, 0x50, 0x5, 0x2C, 0x1, 0x1A,
+  0xC0, 0xE9, 0x93, 0x8, 0x88, 0xE, 0x51, 0x5, 0xE9, 0x5A, 0xE9,
+  0xC6, 0x6, 0x5F, 0x0, 0x0, 0x53, 0x89, 0x1E, 0x4D, 0x5, 0x8B,
+  0x16, 0x50, 0x3, 0x89, 0x16, 0x4B, 0x5, 0x8B, 0xE, 0x4, 0x7,
+  0x2B, 0xCB, 0x89, 0xE, 0x49, 0x5, 0x51, 0x52, 0xE8, 0xA4, 0xFE,
+  0x5A, 0x59, 0x5B, 0xA0, 0x60, 0x0, 0xA, 0xC0, 0x6, 0x74, 0x2,
+  0x8E, 0xC2, 0xB4, 0x3, 0xCD, 0x15, 0x7, 0xE8, 0x89, 0x0, 0xBA,
+  0x5, 0x0, 0xB9, 0x0, 0x0, 0x49, 0x75, 0xFD, 0x4A, 0x75, 0xFA,
+  0xE8, 0x76, 0x0, 0xC3, 0xBE, 0x53, 0x5, 0x8B, 0x8C, 0xA, 0x0,
+  0xA0, 0x60, 0x0, 0xA, 0xC0, 0x9C, 0x51, 0x75, 0xD, 0x50, 0x53,
+  0x51, 0x56, 0x3, 0xD9, 0xE8, 0x16, 0xE6, 0x5E, 0x59, 0x5B, 0x58,
+  0x3C, 0x1, 0x75, 0x4, 0x8B, 0x9C, 0xE, 0x0, 0x6, 0xA, 0xC0,
+  0x74, 0xE, 0x8B, 0x94, 0xC, 0x0, 0xFE, 0xC8, 0x74, 0x4, 0x8B,
+  0x16, 0x50, 0x3, 0x8E, 0xC2, 0xB4, 0x2, 0xCD, 0x15, 0x7, 0x72,
+  0x12, 0x59, 0x9D, 0x75, 0xB, 0x8B, 0x1E, 0x30, 0x0, 0x3, 0xD9,
+  0x43, 0x89, 0x1E, 0x58, 0x3, 0xE9, 0x80, 0xE5, 0x50, 0xE8, 0x5,
+  0xD0, 0x58, 0x80, 0xFC, 0x4, 0x75, 0x5, 0xB2, 0x18, 0xE9, 0xB5,
+  0xAA, 0xE9, 0x6B, 0xAA, 0x4B, 0xE8, 0xF3, 0xB1, 0x75, 0x5, 0xA0,
+  0x64, 0x0, 0xEB, 0x3, 0xE8, 0xE8, 0xC1, 0xA, 0xC0, 0x75, 0x4,
+  0xB0, 0x1, 0xEB, 0x2, 0xB0, 0x0, 0xA2, 0x64, 0x0, 0x8A, 0xE0,
+  0xCD, 0x15, 0xC3, 0xCD, 0xDB, 0xF9, 0xEB, 0x1, 0xF8, 0x8B, 0xF3,
+  0x9C, 0x8B, 0xE, 0xA5, 0x4, 0x8A, 0xC3, 0x32, 0xC1, 0xA2, 0xA7,
+  0x4, 0x8A, 0xC7, 0x32, 0xE4, 0x8A, 0xDD, 0x32, 0xFF, 0x9D, 0x73,
+  0x7, 0x3, 0xC3, 0x2D, 0x1, 0x1, 0xEB, 0x2, 0x2B, 0xC3, 0xA,
+  0xE4, 0x78, 0xD, 0x3D, 0x80, 0x0, 0x72, 0x15, 0x8B, 0xDE, 0x83,
+  0xC4, 0x2, 0xE9, 0x5D, 0x17, 0x5, 0x80, 0x0, 0x79, 0xB, 0x8B,
+  0xDE, 0x83, 0xC4, 0x2, 0xE9, 0xDF, 0x1D, 0x5, 0x80, 0x0, 0xA2,
+  0xA6, 0x4, 0xBB, 0xA5, 0x4, 0x80, 0xF, 0x80, 0x8B, 0xDE, 0x32,
+  0xFF, 0x80, 0xCB, 0x80, 0xC3, 0xC6, 0x6, 0x39, 0x3, 0x80, 0xE8,
+  0xC6, 0xD9, 0x53, 0x8B, 0xDA, 0xE8, 0xEA, 0x6, 0xE8, 0x4, 0xC5,
+  0x89, 0x1E, 0x5E, 0x4, 0xB1, 0x20, 0xE8, 0x1B, 0xCF, 0x5B, 0xE8,
+  0x60, 0xB1, 0x74, 0x17, 0xE8, 0x31, 0xD0, 0x28, 0xE8, 0xA7, 0xD9,
+  0x52, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0x5, 0xE8, 0x4C, 0xB1, 0xEB,
+  0xF1, 0xE8, 0x1E, 0xD0, 0x29, 0x89, 0x1E, 0x3B, 0x3, 0xE, 0xB8,
+  0xE9, 0x5D, 0x50, 0xFF, 0x36, 0x50, 0x3, 0xFF, 0x36, 0x5E, 0x4,
+  0xCB, 0x8B, 0x1E, 0x3B, 0x3, 0xC3, 0x53, 0xE8, 0xE, 0x5, 0x3C,
+  0x6C, 0x74, 0xA, 0x3C, 0x4C, 0x74, 0x6, 0x3C, 0x71, 0x74, 0x2,
+  0x3C, 0x51, 0x5B, 0xC3, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26,
+  0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26,
+  0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x25, 0x25, 0x25, 0x24,
+  0x24, 0x24, 0x23, 0x23, 0x23, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21,
+  0x21, 0x20, 0x20, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1E,
+  0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, 0x1B, 0x1B, 0x1B, 0x1A,
+  0x1A, 0x1A, 0x19, 0x19, 0x19, 0x19, 0x18, 0x18, 0x18, 0x17, 0x17,
+  0x17, 0x17, 0x16, 0x16, 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14,
+  0x14, 0x13, 0x13, 0x13, 0x13, 0x12, 0x12, 0x12, 0x11, 0x11, 0x11,
+  0x10, 0x10, 0x10, 0x10, 0xF, 0xF, 0xF, 0xE, 0xE, 0xE, 0xD,
+  0xD, 0xD, 0xD, 0xC, 0xC, 0xC, 0xB, 0xB, 0xB, 0xA, 0xA,
+  0xA, 0xA, 0x9, 0x9, 0x9, 0x8, 0x8, 0x8, 0x7, 0x7, 0x7,
+  0x6, 0x6, 0x6, 0x6, 0x5, 0x5, 0x5, 0x4, 0x4, 0x4, 0x3,
+  0x3, 0x3, 0x3, 0x2, 0x2, 0x2, 0x1, 0x1, 0x1, 0x0, 0x0,
+  0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFD, 0xFD, 0xFD,
+  0xFD, 0xFC, 0xFC, 0xFC, 0xFB, 0xFB, 0xFB, 0xFA, 0xFA, 0xFA, 0xFA,
+  0xF9, 0xF9, 0xF9, 0xF8, 0xF8, 0xF8, 0xF7, 0xF7, 0xF7, 0xF7, 0xF6,
+  0xF6, 0xF6, 0xF5, 0xF5, 0xF5, 0xF4, 0xF4, 0xF4, 0xF4, 0xF3, 0xF3,
+  0xF3, 0xF2, 0xF2, 0xF2, 0xF1, 0xF1, 0xF1, 0xF1, 0xF0, 0xF0, 0xF0,
+  0xEF, 0xEF, 0xEF, 0xEE, 0xEE, 0xEE, 0xEE, 0xED, 0xED, 0xED, 0xEC,
+  0xEC, 0xEC, 0xEB, 0xEB, 0xEB, 0xEB, 0xEA, 0xEA, 0xEA, 0xE9, 0xE9,
+  0xE9, 0xE8, 0xE8, 0xE8, 0xE7, 0xE7, 0xE7, 0xE7, 0xE6, 0xE6, 0xE6,
+  0xE5, 0xE5, 0xE5, 0xE4, 0xE4, 0xE4, 0xE4, 0xE3, 0xE3, 0xE3, 0xE2,
+  0xE2, 0xE2, 0xE1, 0xE1, 0xE1, 0xE1, 0xE0, 0xB, 0xF6, 0x79, 0x2,
+  0xF7, 0xDA, 0x2B, 0xD7, 0x70, 0x3D, 0x74, 0x3A, 0x53, 0xE8, 0x90,
+  0x1C, 0x9C, 0x73, 0x3, 0xE8, 0x6A, 0xC, 0xB, 0xD2, 0x78, 0xF,
+  0x83, 0xFA, 0x27, 0x72, 0x1D, 0x9D, 0x73, 0x3, 0xE8, 0x3D, 0xC,
+  0x5B, 0xE9, 0xB1, 0x15, 0x83, 0xFA, 0xDA, 0x7D, 0xE, 0x83, 0xC2,
+  0x26, 0x83, 0xFA, 0xDA, 0x7C, 0x11, 0xE8, 0x13, 0x0, 0xBA, 0xDA,
+  0xFF, 0xE8, 0xD, 0x0, 0x9D, 0x73, 0x3, 0xE8, 0x1D, 0xC, 0x5B,
+  0xC3, 0xE8, 0x1F, 0x1C, 0xEB, 0xF3, 0xB, 0xD2, 0x9C, 0x79, 0x2,
+  0xF7, 0xDA, 0xB9, 0x3, 0x0, 0xD3, 0xE2, 0x81, 0xC2, 0x32, 0x60,
+  0x87, 0xDA, 0xE8, 0x25, 0x1D, 0x9D, 0x78, 0x3, 0xE9, 0xEC, 0xC,
+  0xE8, 0xEC, 0x1C, 0xE9, 0xD4, 0x8, 0x72, 0x9, 0xB0, 0xD, 0x90,
+  0xE9, 0xF, 0xFB, 0xC6, 0x7, 0x0, 0x8A, 0x7, 0xE8, 0xA4, 0xF9,
+  0x88, 0x7, 0xC3, 0x75, 0x6, 0xB0, 0xA, 0x90, 0xE8, 0x69, 0xF0,
+  0x58, 0x5A, 0x5B, 0x9D, 0xC3, 0x80, 0x3E, 0x6A, 0x0, 0x0, 0x74,
+  0x12, 0x1E, 0x53, 0xC5, 0x1E, 0x6B, 0x0, 0x80, 0x3F, 0x0, 0x5B,
+  0x1F, 0x75, 0x5, 0xC6, 0x6, 0x6A, 0x0, 0x0, 0xE9, 0x72, 0xAF,
+  0x5F, 0x5E, 0xE9, 0xBE, 0xED, 0x75, 0x10, 0x5B, 0x88, 0x36, 0xA7,
+  0x4, 0xBB, 0x0, 0x10, 0xC6, 0x6, 0xFB, 0x2, 0x4, 0xE9, 0x28,
+  0x15, 0xC7, 0x6, 0xA5, 0x4, 0x0, 0x0, 0xC3, 0x10, 0x5B, 0x88,
+  0x36, 0xA7, 0x4, 0xBB, 0x0, 0x10, 0xC6, 0x6, 0xFB, 0x2, 0x4,
+  0xE9, 0x10, 0x15, 0xC7, 0x6, 0xA5, 0x4, 0x0, 0x0, 0xC3, 0x5C,
+  0xD6, 0xED, 0xBD, 0xCE, 0xFE, 0xE6, 0x5B, 0x5F, 0xA6, 0xB4, 0x36,
+  0x41, 0x5F, 0x70, 0x9, 0x63, 0xCF, 0x61, 0x84, 0x11, 0x77, 0xCC,
+  0x2B, 0x66, 0x43, 0x7A, 0xE5, 0xD5, 0x94, 0xBF, 0x56, 0x69, 0x6A,
+  0x6C, 0xAF, 0x5, 0xBD, 0x37, 0x6, 0x6D, 0x85, 0x47, 0x1B, 0x47,
+  0xAC, 0xC5, 0x27, 0x70, 0x66, 0x19, 0xE2, 0x58, 0x17, 0xB7, 0x51,
+  0x73, 0xE0, 0x4F, 0x8D, 0x97, 0x6E, 0x12, 0x3, 0x77, 0xD8, 0xA3,
+  0x70, 0x3D, 0xA, 0xD7, 0x23, 0x7A, 0xCD, 0xCC, 0xCC, 0xCC, 0xCC,
+  0xCC, 0x4C, 0x7D, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x81,
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x84, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x48, 0x87, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+  0x7A, 0x8A, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x1C, 0x8E, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x50, 0x43, 0x91, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x24, 0x74, 0x94, 0x0, 0x0, 0x0, 0x0, 0x80, 0x96, 0x18,
+  0x98, 0x0, 0x0, 0x0, 0x0, 0x20, 0xBC, 0x3E, 0x9B, 0x0, 0x0,
+  0x0, 0x0, 0x28, 0x6B, 0x6E, 0x9E, 0x0, 0x0, 0x0, 0x0, 0xF9,
+  0x2, 0x15, 0xA2, 0x0, 0x0, 0x0, 0x40, 0xB7, 0x43, 0x3A, 0xA5,
+  0x0, 0x0, 0x0, 0x10, 0xA5, 0xD4, 0x68, 0xA8, 0x0, 0x0, 0x0,
+  0x2A, 0xE7, 0x84, 0x11, 0xAC, 0x0, 0x0, 0x80, 0xF4, 0x20, 0xE6,
+  0x35, 0xAF, 0x0, 0x0, 0xA0, 0x31, 0xA9, 0x5F, 0x63, 0xB2, 0x0,
+  0x0, 0x4, 0xBF, 0xC9, 0x1B, 0xE, 0xB6, 0x0, 0x0, 0xC5, 0x2E,
+  0xBC, 0xA2, 0x31, 0xB9, 0x0, 0x40, 0x76, 0x3A, 0x6B, 0xB, 0x5E,
+  0xBC, 0x0, 0xE8, 0x89, 0x4, 0x23, 0xC7, 0xA, 0xC0, 0x0, 0x62,
+  0xAC, 0xC5, 0xEB, 0x78, 0x2D, 0xC3, 0x80, 0x7A, 0x17, 0xB7, 0x26,
+  0xD7, 0x58, 0xC6, 0x90, 0xAC, 0x6E, 0x32, 0x78, 0x86, 0x7, 0xCA,
+  0xB5, 0x57, 0xA, 0x3F, 0x16, 0x68, 0x29, 0xCD, 0xA2, 0xED, 0xCC,
+  0xCE, 0x1B, 0xC2, 0x53, 0xD0, 0x85, 0x14, 0x40, 0x61, 0x51, 0x59,
+  0x4, 0xD4, 0xA6, 0x19, 0x90, 0xB9, 0xA5, 0x6F, 0x25, 0xD7, 0x10,
+  0x20, 0xF4, 0x27, 0x8F, 0xCB, 0x4E, 0xDA, 0xA, 0x94, 0xF8, 0x78,
+  0x39, 0x3F, 0x1, 0xDE, 0xC, 0xB9, 0x36, 0xD7, 0x7, 0x8F, 0x21,
+  0xE1, 0x4F, 0x67, 0x4, 0xCD, 0xC9, 0xF2, 0x49, 0xE4, 0x23, 0x81,
+  0x45, 0x40, 0x7C, 0x6F, 0x7C, 0xE7, 0xB6, 0x70, 0x2B, 0xA8, 0xAD,
+  0xC5, 0x1D, 0xEB, 0xE4, 0x4C, 0x36, 0x12, 0x19, 0x37, 0x45, 0xEE,
+  0x1C, 0xE0, 0xC3, 0x56, 0xDF, 0x84, 0x76, 0xF1, 0x12, 0x6C, 0x3A,
+  0x96, 0xB, 0x13, 0x1A, 0xF5, 0x16, 0x7, 0xC9, 0x7B, 0xCE, 0x97,
+  0x40, 0xF8, 0xDC, 0x48, 0xBB, 0x1A, 0xC2, 0xBD, 0x70, 0xFB, 0x89,
+  0xD, 0xB5, 0x50, 0x99, 0x76, 0x16, 0xFF, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x80, 0xF1, 0x4, 0x35, 0x80, 0x4, 0x9A, 0xF7,
+  0x19, 0x83, 0x24, 0x63, 0x43, 0x83, 0x75, 0xCD, 0x8D, 0x84, 0xA9,
+  0x7F, 0x83, 0x82, 0x4, 0x0, 0x0, 0x0, 0x81, 0xE2, 0xB0, 0x4D,
+  0x83, 0xA, 0x72, 0x11, 0x83, 0xF4, 0x4, 0x35, 0x7F, 0x18, 0x72,
+  0x31, 0x80, 0x2E, 0x65, 0x45, 0x25, 0x23, 0x21, 0x44, 0x64, 0x2C,
+  0x30, 0x0, 0x80, 0xC6, 0xA4, 0x7E, 0x8D, 0x3, 0x0, 0x40, 0x7A,
+  0x10, 0xF3, 0x5A, 0x0, 0x0, 0xA0, 0x72, 0x4E, 0x18, 0x9, 0x0,
+  0x0, 0x10, 0xA5, 0xD4, 0xE8, 0x0, 0x0, 0x0, 0xE8, 0x76, 0x48,
+  0x17, 0x0, 0x0, 0x0, 0xE4, 0xB, 0x54, 0x2, 0x0, 0x0, 0x0,
+  0xCA, 0x9A, 0x3B, 0x0, 0x0, 0x0, 0x0, 0xE1, 0xF5, 0x5, 0x0,
+  0x0, 0x0, 0x80, 0x96, 0x98, 0x0, 0x0, 0x0, 0x0, 0x40, 0x42,
+  0xF, 0x0, 0x0, 0x0, 0x0, 0x40, 0x42, 0xF, 0xA0, 0x86, 0x1,
+  0x10, 0x27, 0x0, 0x10, 0x27, 0xE8, 0x3, 0x64, 0x0, 0xA, 0x0,
+  0x1, 0x0, 0x0, 0x0, 0x80, 0x90, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x3B, 0xAA, 0x38, 0x81, 0x7, 0x7C, 0x88, 0x59, 0x74, 0xE0, 0x97,
+  0x26, 0x77, 0xC4, 0x1D, 0x1E, 0x7A, 0x5E, 0x50, 0x63, 0x7C, 0x1A,
+  0xFE, 0x75, 0x7E, 0x18, 0x72, 0x31, 0x80, 0x0, 0x0, 0x0, 0x81,
+  0x5, 0xFB, 0xD7, 0x1E, 0x86, 0x65, 0x26, 0x99, 0x87, 0x58, 0x34,
+  0x23, 0x87, 0xE1, 0x5D, 0xA5, 0x86, 0xDB, 0xF, 0x49, 0x83, 0x2,
+  0xD7, 0xB3, 0x5D, 0x81, 0x0, 0x0, 0x80, 0x81, 0x4, 0x62, 0x35,
+  0x83, 0x7E, 0x50, 0x24, 0x4C, 0x7E, 0x79, 0xA9, 0xAA, 0x7F, 0x0,
+  0x0, 0x0, 0x81, 0xB, 0x44, 0x4E, 0x6E, 0x83, 0xF9, 0x22, 0x7E,
+  0xFD, 0x43, 0x3, 0xC3, 0x9E, 0x26, 0x1, 0x0, 0x0, 0x30, 0x31,
+  0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x43,
+  0x44, 0x45, 0x46, 0xBA, 0x3B, 0xAA, 0xBB, 0x38, 0x81, 0xE8, 0x72,
+  0xA, 0xA0, 0xA6, 0x4, 0x3C, 0x88, 0x73, 0x3C, 0x3C, 0x68, 0x72,
+  0x4B, 0xFF, 0x36, 0xA3, 0x4, 0xFF, 0x36, 0xA5, 0x4, 0xE8, 0x60,
+  0x10, 0x8A, 0xE2, 0x80, 0xC4, 0x81, 0x74, 0x23, 0x50, 0xF6, 0x6,
+  0xA7, 0x4, 0x80, 0xE8, 0x43, 0x10, 0x32, 0xE4, 0xE8, 0xE6, 0x11,
+  0x58, 0x5B, 0x5A, 0x50, 0xE8, 0xA8, 0x4, 0xBB, 0x17, 0x62, 0xE8,
+  0x8D, 0x12, 0x5B, 0x33, 0xD2, 0x8A, 0xDA, 0xE9, 0x32, 0xA, 0x83,
+  0xC4, 0x4, 0x80, 0x26, 0xA5, 0x4, 0x80, 0x74, 0x3, 0xE9, 0x91,
+  0x18, 0x32, 0xE4, 0x88, 0x26, 0xA7, 0x4, 0xE9, 0xF9, 0x11, 0xBF,
+  0xA3, 0x4, 0x90, 0x33, 0xC0, 0xFC, 0xAB, 0xC7, 0x5, 0x0, 0x81,
+  0xC3, 0xE8, 0xAF, 0x18, 0x75, 0x3, 0xE9, 0xDE, 0xA4, 0xC3, 0xFC,
+  0xAB, 0xC7, 0x5, 0x0, 0x81, 0xC3, 0xE9, 0x1A, 0xAC, 0xCD, 0xB9,
+  0x80, 0x36, 0xA5, 0x4, 0x80, 0x80, 0x36, 0xB1, 0x4, 0x80, 0xE9,
+  0x8A, 0x3, 0xCD, 0xBA, 0x87, 0xD9, 0xE9, 0x5A, 0x4, 0xCD, 0xBB,
+  0x87, 0xD9, 0xE9, 0x47, 0x4, 0xCD, 0xBC, 0xE8, 0x33, 0x19, 0xE9,
+  0x1B, 0x5, 0x87, 0xD9, 0xE9, 0xB1, 0x5, 0xCD, 0xBD, 0x89, 0x1E,
+  0xA3, 0x4, 0xE9, 0x6B, 0x8, 0xCD, 0xBE, 0x52, 0x98, 0x8B, 0xD0,
+  0xE8, 0xEE, 0x8, 0x5A, 0xC3, 0xCD, 0xBF, 0x87, 0xD9, 0xE9, 0xB7,
+  0x9, 0xCD, 0xC0, 0x87, 0xD9, 0xE9, 0xED, 0xD, 0x81, 0xFB, 0x0,
+  0x80, 0x75, 0x13, 0xCD, 0xC1, 0xE8, 0xD3, 0x8, 0x33, 0xD2, 0xBB,
+  0x80, 0x90, 0xE8, 0x5, 0x4, 0xE8, 0x4B, 0x1A, 0xE9, 0x45, 0x8,
+  0xF7, 0xDB, 0x53, 0x3, 0xDA, 0x70, 0x4, 0x58, 0xE9, 0x99, 0x1,
+  0xCD, 0xC2, 0xE8, 0xB5, 0x8, 0x5A, 0xFF, 0x36, 0xA3, 0x4, 0xFF,
+  0x36, 0xA5, 0x4, 0xE8, 0xA9, 0x8, 0x5B, 0x5A, 0xE9, 0xEA, 0x3,
+  0x8B, 0xC3, 0x52, 0xF7, 0xEA, 0x5A, 0x72, 0x5, 0x8B, 0xD8, 0xE9,
+  0x76, 0x1, 0xCD, 0xC3, 0x53, 0xE8, 0x91, 0x8, 0x5A, 0xFF, 0x36,
+  0xA3, 0x4, 0xFF, 0x36, 0xA5, 0x4, 0xE8, 0x85, 0x8, 0x5B, 0x5A,
+  0xE9, 0x52, 0x9, 0xB, 0xDB, 0x75, 0xC, 0x88, 0x36, 0xA7, 0x4,
+  0xC6, 0x6, 0xFB, 0x2, 0x4, 0xE9, 0x2D, 0x11, 0x89, 0x1E, 0xA3,
+  0x4, 0xB8, 0x0, 0x0, 0xA3, 0xA5, 0x4, 0x92, 0xB, 0xC0, 0x79,
+  0x3, 0xBA, 0xFF, 0xFF, 0xB, 0xDB, 0x79, 0x6, 0xC7, 0x6, 0xA5,
+  0x4, 0xFF, 0xFF, 0xF7, 0x3E, 0xA3, 0x4, 0x8B, 0xD8, 0xE9, 0x2A,
+  0x1, 0x87, 0xD9, 0xE8, 0xD7, 0x18, 0x87, 0xD9, 0xC3, 0x53, 0xE8,
+  0x45, 0x1A, 0x5B, 0x83, 0xC3, 0x4, 0xC3, 0x8B, 0x16, 0xA3, 0x4,
+  0x8B, 0xE, 0xA5, 0x4, 0xC3, 0x9C, 0x53, 0xE8, 0x19, 0x1A, 0x5B,
+  0x83, 0xC3, 0x4, 0x9D, 0xC3, 0xE8, 0xAB, 0xBE, 0x89, 0x1E, 0xA3,
+  0x4, 0xE9, 0x67, 0xA, 0xE8, 0xA1, 0xBE, 0x89, 0x1E, 0xA3, 0x4,
+  0xE9, 0x65, 0xA, 0xCD, 0xC4, 0x8B, 0x17, 0x8B, 0x9F, 0x2, 0x0,
+  0xE9, 0x4D, 0x3, 0x5E, 0xFF, 0x36, 0xA3, 0x4, 0xFF, 0x36, 0xA5,
+  0x4, 0xFF, 0xE6, 0xCD, 0xC5, 0x87, 0xD9, 0xE8, 0xA0, 0x18, 0x87,
+  0xD9, 0xC3, 0xE8, 0x64, 0x17, 0x74, 0x3, 0xE9, 0x93, 0xA3, 0xC3,
+  0x87, 0xDA, 0xE8, 0xCD, 0x0, 0x32, 0xC0, 0xB5, 0x98, 0xCD, 0xC6,
+  0xBB, 0xA6, 0x4, 0x8A, 0xC8, 0x88, 0x2F, 0xB5, 0x0, 0x43, 0x88,
+  0x2F, 0xD0, 0xD0, 0xCD, 0xC7, 0x73, 0x3, 0xE8, 0x20, 0x1, 0x8A,
+  0xE5, 0x8A, 0xD9, 0xE9, 0x33, 0x10, 0xE8, 0x92, 0xFE, 0x53, 0x33,
+  0xDB, 0x89, 0x1E, 0xA3, 0x4, 0xB7, 0x81, 0x89, 0x1E, 0xA5, 0x4,
+  0xC6, 0x6, 0xFB, 0x2, 0x4, 0xE8, 0x4, 0x14, 0x5B, 0xC6, 0x6,
+  0xFB, 0x2, 0x4, 0xC3, 0x8B, 0xC1, 0xF7, 0xE2, 0x92, 0x73, 0x3,
+  0xE9, 0x25, 0xD5, 0xC3, 0xBB, 0xAB, 0x4, 0xBA, 0xB7, 0x64, 0xE9,
+  0x6, 0x0, 0xBB, 0xAB, 0x4, 0xBA, 0xB9, 0x64, 0x52, 0xBA, 0xA3,
+  0x4, 0xE8, 0xF7, 0x16, 0x72, 0x3, 0xBA, 0x9F, 0x4, 0xC3, 0x8A,
+  0xCD, 0x32, 0xED, 0xEB, 0x8, 0x87, 0xDA, 0xA0, 0xFB, 0x2, 0x98,
+  0x8B, 0xC8, 0xFC, 0x8B, 0xF2, 0x8B, 0xFB, 0xF3, 0xA4, 0x8B, 0xD6,
+  0x8B, 0xDF, 0xC3, 0xE8, 0x36, 0xC8, 0x8B, 0xF1, 0x8B, 0xFB, 0xFD,
+  0x2B, 0xCA, 0x41, 0xF3, 0xA4, 0x8B, 0xDA, 0x8B, 0xCF, 0x41, 0xFC,
+  0xC3, 0x9C, 0x49, 0x9D, 0xC3, 0xE8, 0xBC, 0x16, 0x75, 0x3, 0xE9,
+  0xEB, 0xA2, 0xCD, 0xC8, 0x78, 0x3, 0xE9, 0x83, 0x16, 0xA1, 0xA3,
+  0x4, 0xB, 0xC0, 0x74, 0x6, 0xB0, 0x1, 0x79, 0x2, 0xB0, 0xFF,
+  0xC3, 0x33, 0xC0, 0xB, 0xDB, 0x75, 0xF3, 0xC3, 0x5B, 0xC3, 0x98,
+  0x8B, 0xD8, 0xC6, 0x6, 0xFB, 0x2, 0x2, 0x89, 0x1E, 0xA3, 0x4,
+  0xC3, 0xC6, 0x6, 0xFB, 0x2, 0x4, 0xC3, 0xE8, 0xC4, 0xFF, 0xE9,
+  0xE7, 0xFF, 0xCD, 0xC9, 0x5B, 0x5A, 0xE9, 0xB5, 0x3, 0xE8, 0x25,
+  0x6, 0x5B, 0x5A, 0xE9, 0xB, 0xC, 0xB9, 0x4, 0x0, 0xE9, 0x88,
+  0xFF, 0x9C, 0x8A, 0x17, 0x43, 0x9D, 0x9C, 0x8A, 0x37, 0x43, 0x8B,
+  0xF, 0x43, 0x9D, 0x9C, 0x43, 0x9D, 0xC3, 0x53, 0xBB, 0x28, 0x7,
+  0xE8, 0x6, 0x16, 0x5B, 0xB9, 0xB6, 0x26, 0x51, 0xE8, 0xB5, 0xFF,
+  0x32, 0xC0, 0xCD, 0xCA, 0xA2, 0x31, 0x3, 0xBB, 0xB4, 0x4, 0xC6,
+  0x7, 0x20, 0xA, 0x7, 0x43, 0xC6, 0x7, 0x30, 0xE9, 0x6A, 0xB,
+  0xCD, 0xCB, 0xA0, 0xA5, 0x4, 0xEB, 0x9, 0xCD, 0xCC, 0xE8, 0xE5,
+  0x17, 0x74, 0x8, 0xF6, 0xD0, 0xD0, 0xE0, 0x1A, 0xC0, 0x74, 0x3D,
+  0xC3, 0xCD, 0xCD, 0x80, 0x36, 0xA7, 0x4, 0x80, 0x33, 0xDB, 0xF6,
+  0xDD, 0x8B, 0xC3, 0x1B, 0xC2, 0x8B, 0xD0, 0x8A, 0xC3, 0x1A, 0xC1,
+  0x8A, 0xC8, 0xC3, 0xE8, 0x3, 0x16, 0x78, 0xFA, 0xCD, 0xCE, 0xE8,
+  0xCF, 0x15, 0x78, 0x3, 0xE9, 0xD5, 0x18, 0xE8, 0x2, 0x18, 0xE8,
+  0xCF, 0x18, 0xE9, 0xFC, 0x17, 0x8B, 0xC3, 0x2B, 0xC2, 0x74, 0xE,
+  0x70, 0x7, 0x78, 0x7, 0x32, 0xC0, 0xFE, 0xC0, 0xC3, 0x78, 0xF9,
+  0xF9, 0x1A, 0xC0, 0xC3, 0x3B, 0xDA, 0x75, 0x5, 0x33, 0xDB, 0xE9,
+  0x26, 0x0, 0x8B, 0xC2, 0x89, 0x1E, 0xA3, 0x4, 0xB, 0xDB, 0xE8,
+  0xD3, 0xF9, 0x90, 0x90, 0x90, 0x79, 0x6, 0xC7, 0x6, 0xA5, 0x4,
+  0xFF, 0xFF, 0xB, 0xC0, 0xBA, 0x0, 0x0, 0x79, 0x3, 0xBA, 0xFF,
+  0xFF, 0xF7, 0x3E, 0xA3, 0x4, 0x8B, 0xDA, 0x89, 0x1E, 0xA3, 0x4,
+  0xC3, 0xAD, 0x3A, 0xE1, 0x74, 0x11, 0x46, 0x2, 0x4, 0xFE, 0xC0,
+  0x98, 0x3, 0xF0, 0x3B, 0xF5, 0x75, 0xEF, 0x8B, 0xD6, 0xE9, 0x39,
+  0xD2, 0x3A, 0x6, 0xFB, 0x2, 0x75, 0xE9, 0x3A, 0x2C, 0x75, 0xE5,
+  0x46, 0x8A, 0xD0, 0xAC, 0x3A, 0x6, 0x8E, 0x0, 0x74, 0x4, 0x2,
+  0xC2, 0xEB, 0xDC, 0xA, 0xC0, 0x74, 0x10, 0x98, 0x91, 0xBF, 0x8F,
+  0x0, 0xF3, 0xA6, 0x91, 0x74, 0x6, 0x3, 0xF0, 0x8A, 0xC2, 0xEB,
+  0xC8, 0x8B, 0xD6, 0x5B, 0xC3, 0x8B, 0xF3, 0x8B, 0x2E, 0x4B, 0x4,
+  0xFC, 0xEB, 0xBE, 0x8B, 0xF3, 0x8B, 0x2E, 0x5C, 0x3, 0xFC, 0xE9,
+  0xD, 0x0, 0xAD, 0x3A, 0xE1, 0x74, 0x11, 0x46, 0xAC, 0x98, 0x3,
+  0xF0, 0xAD, 0x3, 0xF0, 0x3B, 0xEE, 0x75, 0xEF, 0x8B, 0xDE, 0xE9,
+  0x53, 0xD3, 0x3A, 0x6, 0xFB, 0x2, 0x75, 0xE9, 0x3A, 0x2C, 0x75,
+  0xE5, 0x46, 0xAC, 0x3A, 0x6, 0x8E, 0x0, 0x75, 0xDF, 0xA, 0xC0,
+  0x74, 0xE, 0x98, 0x91, 0xBF, 0x8F, 0x0, 0xF3, 0xA6, 0x91, 0x74,
+  0x4, 0x3, 0xF0, 0xEB, 0xD0, 0xAD, 0x8B, 0xD0, 0x8B, 0xDE, 0xE9,
+  0x5, 0xD3, 0xE8, 0x18, 0x16, 0xC3, 0xA1, 0xA5, 0x4, 0xA, 0xE4,
+  0x74, 0xF5, 0x80, 0x36, 0xA5, 0x4, 0x80, 0xCD, 0xD7, 0xB0, 0x0,
+  0xA2, 0x9E, 0x4, 0xA2, 0xAA, 0x4, 0xA0, 0xB2, 0x4, 0xA, 0xC0,
+  0x74, 0xE2, 0xA1, 0xA5, 0x4, 0xA, 0xE4, 0x74, 0xD8, 0x8B, 0x1E,
+  0xB1, 0x4, 0x80, 0xE, 0xA5, 0x4, 0x80, 0x80, 0xE, 0xB1, 0x4,
+  0x80, 0x8A, 0xCC, 0x2A, 0xCF, 0xA2, 0xA7, 0x4, 0x74, 0x22, 0x73,
+  0x12, 0x86, 0xC3, 0xF6, 0xD9, 0xA2, 0xA7, 0x4, 0x88, 0x3E, 0xA6,
+  0x4, 0x50, 0x51, 0xE8, 0x6F, 0x15, 0x59, 0x58, 0x80, 0xF9, 0x39,
+  0x73, 0x5F, 0x53, 0xF8, 0xE8, 0x21, 0x15, 0xA0, 0xA7, 0x4, 0x5B,
+  0x32, 0xC3, 0xBB, 0x9E, 0x4, 0xBE, 0xAA, 0x4, 0xB9, 0x4, 0x0,
+  0xF8, 0xFC, 0x78, 0x1E, 0xAD, 0x11, 0x7, 0x43, 0x43, 0xE2, 0xF9,
+  0x73, 0x12, 0xBB, 0xA6, 0x4, 0xFE, 0x7, 0x74, 0x34, 0x4B, 0x4B,
+  0xB9, 0x4, 0x0, 0xD1, 0x1F, 0x4B, 0x4B, 0xE2, 0xFA, 0xE9, 0xE9,
+  0x11, 0xAD, 0x19, 0x7, 0x43, 0x43, 0xE2, 0xF9, 0x73, 0x1A, 0xF6,
+  0x97, 0x1, 0x0, 0xB9, 0x4, 0x0, 0x4B, 0x4B, 0xF7, 0x17, 0xE2,
+  0xFA, 0xB9, 0x4, 0x0, 0xFF, 0x7, 0x75, 0x6, 0x43, 0x43, 0xE2,
+  0xF8, 0x74, 0xC8, 0xE9, 0xF4, 0xC, 0xE9, 0x8D, 0xD, 0xA0, 0xA7,
+  0x4, 0x24, 0x80, 0x80, 0x26, 0xA5, 0x4, 0x7F, 0x8, 0x6, 0xA5,
+  0x4, 0xC3, 0x89, 0x1E, 0xA5, 0x4, 0x89, 0x16, 0xA3, 0x4, 0xC3,
+  0xA1, 0xA5, 0x4, 0xA, 0xE4, 0x74, 0xF0, 0x80, 0x36, 0xA5, 0x4,
+  0x80, 0xA, 0xFF, 0x74, 0xEF, 0xA1, 0xA5, 0x4, 0xA, 0xE4, 0x74,
+  0xE0, 0x33, 0xC9, 0x8B, 0x36, 0xA3, 0x4, 0xA2, 0xA7, 0x4, 0x8A,
+  0xCC, 0x2A, 0xCF, 0x73, 0xD, 0xF6, 0xD9, 0x86, 0xDF, 0x89, 0x1E,
+  0xA6, 0x4, 0x86, 0xDF, 0x93, 0x87, 0xD6, 0x8A, 0xE0, 0x32, 0xE3,
+  0x9C, 0xB4, 0x80, 0xA, 0xC4, 0xA, 0xDC, 0x32, 0xE4, 0x8A, 0xFC,
+  0xB, 0xC9, 0x74, 0x46, 0x83, 0xF9, 0x19, 0x72, 0x12, 0x9D, 0x89,
+  0x36, 0xA3, 0x4, 0x8A, 0x26, 0xA7, 0x4, 0x25, 0x7F, 0x80, 0xA,
+  0xC4, 0xA2, 0xA5, 0x4, 0xC3, 0x80, 0xF9, 0x8, 0x72, 0x1C, 0xE9,
+  0x5, 0x3, 0x90, 0x8A, 0xF3, 0x32, 0xDB, 0x80, 0xE9, 0x8, 0xF6,
+  0xC4, 0x1F, 0x74, 0xD0, 0x80, 0xCC, 0x20, 0xEB, 0xCB, 0x80, 0xCC,
+  0x20, 0xE2, 0x3, 0xEB, 0xE, 0xF8, 0xD0, 0xDB, 0xD1, 0xDA, 0xD0,
+  0xDC, 0xF6, 0xC4, 0x10, 0x75, 0xED, 0xE2, 0xF3, 0x9D, 0x79, 0x25,
+  0x2A, 0xCC, 0x8A, 0xE1, 0x1B, 0xF2, 0x8B, 0xD6, 0x1A, 0xC3, 0x8A,
+  0xD8, 0x73, 0x2F, 0xF6, 0x16, 0xA7, 0x4, 0xF6, 0xD4, 0xF7, 0xD2,
+  0xF6, 0xD3, 0xFE, 0xC4, 0x75, 0x21, 0x42, 0x75, 0x1E, 0xFE, 0xC3,
+  0x75, 0x1A, 0xEB, 0x6, 0x3, 0xD6, 0x12, 0xD8, 0x73, 0xC, 0xFE,
+  0x6, 0xA6, 0x4, 0x74, 0x9, 0xD0, 0xDB, 0xD1, 0xDA, 0xD0, 0xDC,
+  0xE9, 0x24, 0x11, 0xE9, 0xA9, 0xC, 0xE9, 0x68, 0xC, 0xE8, 0x25,
+  0x13, 0xC3, 0xA0, 0xB1, 0x4, 0xA2, 0xA7, 0x4, 0xE9, 0xA7, 0xC,
+  0xF6, 0x6, 0xA6, 0x4, 0xFF, 0x74, 0xF0, 0xF6, 0x6, 0xB2, 0x4,
+  0xFF, 0x74, 0xE5, 0x8B, 0x1E, 0xB1, 0x4, 0xE8, 0xF3, 0xF4, 0x89,
+  0x1E, 0xB1, 0x4, 0xBB, 0xA4, 0x4, 0xF8, 0xE8, 0xA1, 0x13, 0xBB,
+  0xB0, 0x4, 0xF8, 0xE8, 0x9A, 0x13, 0xFF, 0x36, 0xA6, 0x4, 0xE8,
+  0x5E, 0x15, 0x8F, 0x6, 0xA6, 0x4, 0xB9, 0x40, 0x0, 0x51, 0xEB,
+  0x8, 0x51, 0xF8, 0xBB, 0xAA, 0x4, 0xE8, 0x77, 0x13, 0x8B, 0xFC,
+  0x83, 0xEC, 0x8, 0x83, 0xEF, 0x2, 0xBE, 0xB0, 0x4, 0xB9, 0x4,
+  0x0, 0xFD, 0xF3, 0xA5, 0xBE, 0x78, 0x4, 0xB9, 0x4, 0x0, 0xBB,
+  0xAA, 0x4, 0xF8, 0xFC, 0xAD, 0x19, 0x7, 0x43, 0x43, 0xE2, 0xF9,
+  0x73, 0x10, 0xB9, 0x4, 0x0, 0x8B, 0xF4, 0xBF, 0xAA, 0x4, 0xFC,
+  0xF3, 0xA5, 0x8B, 0xE6, 0xF8, 0xEB, 0x4, 0x83, 0xC4, 0x8, 0xF9,
+  0xBB, 0x9E, 0x4, 0xE8, 0x38, 0x13, 0x59, 0xE2, 0xB6, 0xF6, 0x6,
+  0xA5, 0x4, 0x80, 0x74, 0x9, 0xFF, 0x6, 0xA6, 0x4, 0x75, 0x9,
+  0xE9, 0x7, 0xC, 0xBB, 0x9E, 0x4, 0xE8, 0x1F, 0x13, 0xE9, 0x31,
+  0x10, 0xE8, 0x94, 0x12, 0x75, 0x7, 0x88, 0x1E, 0xA7, 0x4, 0xE9,
+  0x0, 0xC, 0xA, 0xFF, 0x75, 0x3, 0xE9, 0x7A, 0x12, 0xE8, 0x57,
+  0xF4, 0x8B, 0xFA, 0x33, 0xD2, 0x8A, 0xFE, 0x8B, 0xF3, 0x8A, 0xDF,
+  0xB9, 0x20, 0x0, 0x55, 0x8B, 0x2E, 0xA3, 0x4, 0xA0, 0xA5, 0x4,
+  0x8A, 0xE7, 0xEB, 0x5, 0xF8, 0xD1, 0xD7, 0xD1, 0xD6, 0x56, 0x57,
+  0x2B, 0xFD, 0x1B, 0xF0, 0x73, 0x4, 0x5F, 0x5E, 0xEB, 0x4, 0x83,
+  0xC4, 0x4, 0xF8, 0xF5, 0xD1, 0xD2, 0xD1, 0xD3, 0xE2, 0xE4, 0xB,
+  0xDB, 0x79, 0xA, 0xFE, 0x6, 0xA6, 0x4, 0x75, 0x8, 0x5D, 0xE9,
+  0xA5, 0xB, 0xD1, 0xD2, 0xD1, 0xD3, 0x8A, 0xE2, 0x8A, 0xD6, 0x8A,
+  0xF3, 0x8A, 0xDF, 0x5D, 0xE9, 0xD, 0x10, 0x13, 0xF9, 0x53, 0x57,
+  0x51, 0x2C, 0x30, 0x50, 0xE8, 0x50, 0x12, 0x58, 0x98, 0x79, 0x1E,
+  0x8B, 0x1E, 0xA3, 0x4, 0x81, 0xFB, 0xCD, 0xC, 0x73, 0x19, 0x8B,
+  0xCB, 0xD1, 0xE3, 0xD1, 0xE3, 0x3, 0xD9, 0xD1, 0xE3, 0x3, 0xD8,
+  0x78, 0xB, 0x89, 0x1E, 0xA3, 0x4, 0xEB, 0x48, 0x50, 0x72, 0x8,
+  0xEB, 0x33, 0x50, 0xE8, 0x24, 0x2, 0xEB, 0x14, 0xC7, 0x6, 0x7C,
+  0x4, 0x0, 0x24, 0xC7, 0x6, 0x7E, 0x4, 0x74, 0x94, 0xBB, 0x7E,
+  0x4, 0xE8, 0x83, 0x13, 0x79, 0x16, 0xE8, 0x3C, 0x12, 0x5A, 0xFF,
+  0x36, 0xA3, 0x4, 0xFF, 0x36, 0xA5, 0x4, 0xE8, 0x8B, 0x2, 0x5B,
+  0x5A, 0xE8, 0xCC, 0xFD, 0xEB, 0x13, 0xE8, 0xE7, 0x1, 0xE8, 0x23,
+  0x12, 0xE8, 0xEE, 0x12, 0x5A, 0xE8, 0x77, 0x2, 0xE8, 0xDA, 0x1,
+  0xE8, 0xEE, 0xFC, 0x59, 0x5F, 0x5B, 0xC3, 0xCD, 0xD9, 0x32, 0xC0,
+  0xE9, 0x9, 0x0, 0xCD, 0xDA, 0xB0, 0x1, 0xC6, 0x6, 0xFB, 0x2,
+  0x8, 0xC6, 0x6, 0xA8, 0x4, 0x1, 0xBE, 0xB4, 0x25, 0x56, 0x33,
+  0xFF, 0x8B, 0xCF, 0x8B, 0xF7, 0xF7, 0xD1, 0x50, 0xE8, 0x86, 0x11,
+  0x58, 0xA, 0xC0, 0x75, 0x5, 0xC6, 0x6, 0xFB, 0x2, 0x2, 0x8A,
+  0x7, 0x3C, 0x26, 0x75, 0x3, 0xE9, 0x7, 0xB0, 0x3C, 0x2D, 0x9C,
+  0x74, 0x5, 0x3C, 0x2B, 0x74, 0x1, 0x4B, 0xE8, 0xFB, 0xF8, 0x73,
+  0x6, 0xE8, 0x3D, 0xFF, 0xE9, 0xF5, 0xFF, 0xBD, 0xA3, 0x61, 0x33,
+  0xD2, 0x8B, 0xF2, 0x2E, 0x3A, 0x86, 0x0, 0x0, 0x74, 0xA, 0x81,
+  0xFD, 0x9C, 0x61, 0x74, 0x24, 0x4D, 0xE9, 0xEF, 0xFF, 0x81, 0xED,
+  0x9C, 0x61, 0xD1, 0xE5, 0x2E, 0xFF, 0xA6, 0x30, 0x6A, 0x4B, 0x6A,
+  0x5F, 0x6A, 0x5F, 0x6A, 0x67, 0x6A, 0x6D, 0x6A, 0x73, 0x6A, 0x40,
+  0x6A, 0x40, 0x6A, 0x32, 0xC0, 0xE8, 0x9C, 0x0, 0xE8, 0x41, 0x0,
+  0xE9, 0x2D, 0x0, 0x41, 0x75, 0xF7, 0xE8, 0x51, 0x11, 0x79, 0xAF,
+  0x51, 0x53, 0x57, 0xE8, 0x48, 0x1, 0x5F, 0x5B, 0x59, 0xE9, 0xA3,
+  0xFF, 0xE8, 0x8C, 0xF3, 0x74, 0xE1, 0xE9, 0xDB, 0xFF, 0x43, 0xEB,
+  0xDB, 0xE9, 0xB, 0x0, 0xE8, 0xBC, 0x0, 0xE9, 0x5, 0x0, 0x32,
+  0xC0, 0xE8, 0xB6, 0x0, 0x9D, 0x75, 0xD, 0xE8, 0x2D, 0x13, 0xE8,
+  0x21, 0x11, 0x7A, 0x5, 0x53, 0xE8, 0xED, 0x12, 0x5B, 0xC3, 0xE9,
+  0x76, 0xF4, 0xC6, 0x6, 0x55, 0x4, 0xFF, 0xE8, 0x89, 0xA4, 0x8B,
+  0xD4, 0xE9, 0xE3, 0x8, 0xA, 0xFF, 0x75, 0x5, 0xE8, 0xE8, 0x10,
+  0xF9, 0xC3, 0xA0, 0xA6, 0x4, 0xA, 0xC0, 0x75, 0x8, 0x8A, 0xC3,
+  0xF6, 0xD0, 0xE8, 0xE4, 0x10, 0xF9, 0xC3, 0xE8, 0xE4, 0xFF, 0x5D,
+  0x72, 0x14, 0xEB, 0x10, 0x53, 0x8B, 0x1F, 0xE8, 0xD9, 0xFF, 0x5B,
+  0x5D, 0x72, 0x8, 0x53, 0x57, 0xBF, 0xA5, 0x4, 0x90, 0x55, 0xC3,
+  0xFE, 0xC0, 0x2C, 0x1, 0xC3, 0xF6, 0xC4, 0xFF, 0x8A, 0xE2, 0x74,
+  0x3, 0x80, 0xCC, 0x20, 0x8A, 0xD6, 0xE9, 0xED, 0xFC, 0x10, 0x9F,
+  0x80, 0x3E, 0xFB, 0x2, 0x8, 0x75, 0x4, 0x9E, 0xE9, 0x8, 0x0,
+  0x9E, 0x53, 0x57, 0xE8, 0x5C, 0x0, 0x5F, 0x5B, 0x33, 0xF6, 0x8B,
+  0xD6, 0xE8, 0x4, 0xF8, 0x72, 0x13, 0x3C, 0x2D, 0x75, 0x4, 0xF7,
+  0xD6, 0xEB, 0x5, 0x3C, 0x2B, 0x74, 0x1, 0xC3, 0xE8, 0xF2, 0xF7,
+  0x72, 0x1, 0xC3, 0x81, 0xFA, 0xCC, 0xC, 0x72, 0x5, 0xBA, 0xFF,
+  0x7F, 0xEB, 0xEF, 0x50, 0xB8, 0xA, 0x0, 0xF7, 0xE2, 0x5A, 0x80,
+  0xEA, 0x30, 0x32, 0xF6, 0x3, 0xD0, 0xEB, 0xDF, 0xC, 0x1, 0x53,
+  0x57, 0x75, 0x7, 0xE8, 0x1C, 0x0, 0xEB, 0x5, 0x90, 0x90, 0xE8,
+  0x46, 0x0, 0x5F, 0x5B, 0x33, 0xF6, 0x8B, 0xD6, 0xE8, 0xBD, 0xF3,
+  0x43, 0xC3, 0xE8, 0x58, 0x10, 0x78, 0xF9, 0xE9, 0x6F, 0x9C, 0x74,
+  0x31, 0xE8, 0x4E, 0x10, 0x7B, 0x56, 0x75, 0x3, 0xE9, 0x7B, 0x9C,
+  0xCD, 0xCF, 0x79, 0x5, 0xE8, 0x3F, 0x0, 0xEB, 0x48, 0xB0, 0x4,
+  0xA2, 0xFB, 0x2, 0x8A, 0x1E, 0xA5, 0x4, 0x88, 0x1E, 0xA7, 0x4,
+  0x8B, 0x16, 0xA3, 0x4, 0x8A, 0x26, 0xA2, 0x4, 0x80, 0xCC, 0x40,
+  0x80, 0xCB, 0x80, 0xE9, 0xD5, 0xD, 0xE8, 0x1D, 0x10, 0x73, 0x25,
+  0x75, 0x3, 0xE9, 0x4A, 0x9C, 0xCD, 0xD0, 0x79, 0x3, 0xE8, 0xE,
+  0x0, 0xB0, 0x8, 0xA2, 0xFB, 0x2, 0x33, 0xC0, 0xA3, 0x9F, 0x4,
+  0xA3, 0xA1, 0x4, 0xC3, 0x52, 0x56, 0x8B, 0x16, 0xA3, 0x4, 0xE8,
+  0x83, 0x0, 0x5E, 0x5A, 0xC3, 0xE8, 0xF2, 0xF, 0x79, 0x5, 0x8B,
+  0x1E, 0xA3, 0x4, 0xC3, 0xCD, 0xD1, 0x75, 0x3, 0xE9, 0x18, 0x9C,
+  0xA0, 0xA6, 0x4, 0x3C, 0x90, 0x72, 0x31, 0x74, 0x3, 0xE9, 0x6,
+  0x9C, 0xA0, 0xA5, 0x4, 0xA, 0xC0, 0x78, 0x3, 0xE9, 0xFC, 0x9B,
+  0xBA, 0x0, 0x0, 0xBB, 0x0, 0x80, 0xE8, 0x8A, 0xFB, 0xE8, 0xCB,
+  0x6, 0xE8, 0xCD, 0x11, 0xBA, 0x0, 0x0, 0xBB, 0x80, 0x90, 0xE8,
+  0xEC, 0x10, 0x74, 0x3, 0xE9, 0xDF, 0x9B, 0xBB, 0x0, 0x80, 0xEB,
+  0x2D, 0xA0, 0xA5, 0x4, 0xA, 0xC0, 0x9C, 0x79, 0x5, 0x24, 0x7F,
+  0xA2, 0xA5, 0x4, 0xBA, 0x0, 0x0, 0xBB, 0x0, 0x80, 0xE8, 0x67,
+  0xFB, 0xA0, 0xA6, 0x4, 0x3C, 0x90, 0x75, 0x6, 0x9D, 0x78, 0xDB,
+  0xE9, 0xB7, 0x9B, 0xE8, 0xE7, 0x6, 0x8B, 0xDA, 0x9D, 0x79, 0x2,
+  0xF7, 0xDB, 0x89, 0x1E, 0xA3, 0x4, 0xC6, 0x6, 0xFB, 0x2, 0x2,
+  0xC3, 0x33, 0xDB, 0x32, 0xE4, 0xBE, 0xA7, 0x4, 0xC6, 0x84, 0xFF,
+  0xFF, 0x90, 0xC6, 0x4, 0x0, 0xB, 0xD2, 0x79, 0x5, 0xF7, 0xDA,
+  0xC6, 0x4, 0x80, 0x8A, 0xDE, 0x8A, 0xF2, 0x8A, 0xD7, 0xC6, 0x6,
+  0xFB, 0x2, 0x4, 0xE9, 0x4B, 0x8, 0xCD, 0xD6, 0xA0, 0xA6, 0x4,
+  0xA, 0xC0, 0x74, 0xA, 0xA0, 0xB2, 0x4, 0xA, 0xC0, 0x75, 0x4,
+  0xE9, 0xF8, 0xE, 0xC3, 0x8B, 0x1E, 0xB1, 0x4, 0xE8, 0xDA, 0xF0,
+  0xFF, 0x36, 0xA6, 0x4, 0x89, 0x1E, 0xB1, 0x4, 0xE8, 0x56, 0x11,
+  0x8B, 0xF0, 0xA3, 0xA6, 0x4, 0xBB, 0x78, 0x4, 0xA3, 0xB2, 0x4,
+  0xBD, 0xAB, 0x4, 0x8B, 0x0, 0xB, 0xC0, 0x74, 0x2C, 0xBF, 0x0,
+  0x0, 0x8B, 0xCF, 0x8B, 0x0, 0xF7, 0x23, 0x53, 0x8B, 0xDE, 0x3,
+  0xDF, 0x81, 0xC3, 0x97, 0x4, 0x3, 0x7, 0x73, 0x1, 0x42, 0x3,
+  0xC1, 0x73, 0x1, 0x42, 0x89, 0x7, 0x8B, 0xCA, 0x5B, 0x83, 0xFF,
+  0x6, 0x74, 0x4, 0x47, 0x47, 0xEB, 0xDB, 0x8B, 0xC1, 0x53, 0xBB,
+  0x9F, 0x4, 0x89, 0x0, 0x5B, 0x83, 0xFE, 0x6, 0x74, 0x4, 0x46,
+  0x46, 0xEB, 0xBE, 0xBE, 0x9D, 0x4, 0xFD, 0xB9, 0x7, 0x0, 0xAC,
+  0xA, 0xC0, 0xE1, 0xFB, 0x74, 0x5, 0x80, 0xE, 0x9E, 0x4, 0x20,
+  0xA0, 0xA5, 0x4, 0xA, 0xC0, 0x8F, 0x6, 0xA6, 0x4, 0x78, 0xF,
+  0xBB, 0x9E, 0x4, 0xB9, 0x4, 0x0, 0xD1, 0x17, 0x43, 0x43, 0xE2,
+  0xFA, 0xE9, 0x19, 0xC, 0xFE, 0x6, 0xA6, 0x4, 0x75, 0xF7, 0xE9,
+  0xDD, 0x7, 0xE8, 0x73, 0xE, 0x74, 0x4, 0xA, 0xFF, 0x75, 0x3,
+  0xE9, 0x60, 0xE, 0xE8, 0x3A, 0xF0, 0x8B, 0xE, 0xA5, 0x4, 0x32,
+  0xED, 0xA1, 0xA3, 0x4, 0x8A, 0xFD, 0x53, 0x51, 0x52, 0x51, 0x50,
+  0xF7, 0xE2, 0x8B, 0xCA, 0x58, 0xF7, 0xE3, 0x3, 0xC8, 0x73, 0x1,
+  0x42, 0x8B, 0xDA, 0x5A, 0x58, 0xF7, 0xE2, 0x3, 0xC8, 0x73, 0x1,
+  0x42, 0x3, 0xDA, 0x5A, 0x58, 0xF6, 0xE2, 0x3, 0xD8, 0x73, 0xD,
+  0xD1, 0xDB, 0xD1, 0xD9, 0xFE, 0x6, 0xA6, 0x4, 0x75, 0x3, 0xE9,
+  0x90, 0x7, 0xA, 0xFF, 0x79, 0x9, 0xFE, 0x6, 0xA6, 0x4, 0x75,
+  0x7, 0xE9, 0x83, 0x7, 0xD1, 0xD1, 0xD1, 0xD3, 0x8A, 0xD5, 0x8A,
+  0xF3, 0x8A, 0xDF, 0x8A, 0xE1, 0xE9, 0xEC, 0xB, 0xC3, 0x53, 0xB0,
+  0x8, 0x72, 0x2, 0xB0, 0x11, 0x8A, 0xE8, 0x8A, 0xC8, 0x51, 0x9C,
+  0xE8, 0x48, 0x2, 0xA, 0xC0, 0x74, 0x2, 0x79, 0xC, 0x9D, 0x59,
+  0x50, 0x7B, 0xB, 0x4, 0x10, 0x58, 0x79, 0x1A, 0xEB, 0x9, 0x9D,
+  0x59, 0xEB, 0x26, 0x4, 0x7, 0x58, 0x79, 0xF, 0x50, 0xE8, 0xF6,
+  0xB, 0x58, 0x8A, 0xE0, 0x2, 0xE1, 0x7E, 0x16, 0x2, 0xE8, 0xEB,
+  0xC, 0x2, 0xC5, 0xFE, 0xC5, 0x3A, 0xE8, 0xB5, 0x3, 0x72, 0xC,
+  0x8A, 0xE8, 0xFE, 0xC5, 0xB0, 0x2, 0xEB, 0x4, 0x2, 0xC5, 0xB5,
+  0x3, 0xFE, 0xC8, 0xFE, 0xC8, 0x5B, 0x50, 0x9C, 0x32, 0xC9, 0xE8,
+  0x4D, 0x0, 0xC6, 0x7, 0x30, 0x75, 0x1, 0x43, 0xE8, 0xE8, 0x0,
+  0x4B, 0x80, 0x3F, 0x30, 0x74, 0xFA, 0x80, 0x3F, 0x2E, 0x74, 0x1,
+  0x43, 0x9D, 0x58, 0x74, 0x2B, 0x9C, 0x50, 0xE8, 0xBF, 0xD, 0xB4,
+  0x45, 0x7B, 0x2, 0xB4, 0x44, 0x88, 0x27, 0x43, 0x58, 0x9D, 0xC6,
+  0x7, 0x2B, 0x79, 0x5, 0xC6, 0x7, 0x2D, 0xF6, 0xD8, 0xB4, 0x2F,
+  0xFE, 0xC4, 0x2C, 0xA, 0x73, 0xFA, 0x4, 0x3A, 0x43, 0x86, 0xC4,
+  0x89, 0x7, 0x43, 0x43, 0xC6, 0x7, 0x0, 0x87, 0xD9, 0xBB, 0xB4,
+  0x4, 0xC3, 0xFE, 0xCD, 0x79, 0x16, 0x89, 0x1E, 0x52, 0x3, 0xC6,
+  0x7, 0x2E, 0x43, 0xC6, 0x7, 0x30, 0xFE, 0xC5, 0x75, 0xF8, 0x43,
+  0x33, 0xC9, 0xEB, 0x1A, 0xFE, 0xCD, 0x75, 0xC, 0xC6, 0x7, 0x2E,
+  0x89, 0x1E, 0x52, 0x3, 0x43, 0x33, 0xC9, 0xEB, 0xA, 0xFE, 0xC9,
+  0x75, 0x6, 0xC6, 0x7, 0x2C, 0x43, 0xB1, 0x3, 0x89, 0xE, 0x81,
+  0x4, 0xC3, 0xB4, 0x5, 0xBD, 0xF5, 0x61, 0xE8, 0xD9, 0xFF, 0x2E,
+  0x8B, 0x96, 0x0, 0x0, 0x45, 0x45, 0x8B, 0x36, 0xA3, 0x4, 0xB0,
+  0x2F, 0xFE, 0xC0, 0x2B, 0xF2, 0x73, 0xFA, 0x3, 0xF2, 0x88, 0x7,
+  0x43, 0x89, 0x36, 0xA3, 0x4, 0xFE, 0xCC, 0x75, 0xDD, 0xE8, 0xB6,
+  0xFF, 0xC6, 0x7, 0x0, 0xC3, 0xB9, 0x1, 0x3, 0xBE, 0x6, 0x0,
+  0xEB, 0x6, 0xB9, 0x4, 0x4, 0xBE, 0x4, 0x0, 0xBF, 0xB3, 0x4,
+  0xFC, 0xBB, 0x74, 0x62, 0x8B, 0x16, 0xA3, 0x4, 0x56, 0x8A, 0xC6,
+  0x32, 0xE4, 0xD3, 0xE0, 0x86, 0xE0, 0x2E, 0xD7, 0xAA, 0xD3, 0xE2,
+  0x8A, 0xCD, 0x4E, 0x75, 0xEE, 0xC6, 0x5, 0x0, 0xBB, 0xB3, 0x4,
+  0x59, 0xFE, 0xC9, 0x80, 0x3F, 0x30, 0x75, 0x3, 0x43, 0xE2, 0xF8,
+  0xC3, 0xE8, 0xE9, 0xC, 0x7B, 0x77, 0x51, 0x53, 0xBE, 0x9F, 0x4,
+  0xBF, 0xAB, 0x4, 0xB9, 0x4, 0x0, 0xFC, 0xF3, 0xA5, 0xE8, 0x75,
+  0x3, 0x53, 0xBB, 0xB1, 0x4, 0xE8, 0xFD, 0xD, 0x5B, 0xBE, 0xAB,
+  0x4, 0xBF, 0x9F, 0x4, 0xB9, 0x4, 0x0, 0xFC, 0xF3, 0xA5, 0x74,
+  0x3, 0xE8, 0xCE, 0xC, 0x8A, 0xE, 0xA6, 0x4, 0x80, 0xE9, 0xB8,
+  0xF6, 0xD9, 0xF8, 0xE8, 0x5A, 0x3, 0x5B, 0x59, 0xBE, 0xA6, 0x61,
+  0xB0, 0x9, 0xE8, 0x2E, 0xFF, 0x50, 0xB0, 0x2F, 0x50, 0x58, 0xFE,
+  0xC0, 0x50, 0xE8, 0x94, 0x0, 0x73, 0xF7, 0xE8, 0xA3, 0x0, 0x58,
+  0xEB, 0xB, 0x75, 0x9, 0xC6, 0x7, 0x31, 0x43, 0xC6, 0x7, 0x30,
+  0xEB, 0x2, 0x88, 0x7, 0x43, 0x58, 0xFE, 0xC8, 0x75, 0xD7, 0x51,
+  0xBE, 0x9F, 0x4, 0xBF, 0xA3, 0x4, 0xB9, 0x2, 0x0, 0xFC, 0xF3,
+  0xA5, 0x59, 0xEB, 0x29, 0x53, 0x51, 0xE8, 0x18, 0xF, 0xE8, 0x71,
+  0x3, 0x5A, 0x5B, 0xE8, 0x99, 0xD, 0x74, 0xB, 0x89, 0x1E, 0xA5,
+  0x4, 0x89, 0x16, 0xA3, 0x4, 0xE8, 0x73, 0xC, 0xB0, 0x1, 0xE8,
+  0xB2, 0x3, 0x89, 0x1E, 0xA5, 0x4, 0x89, 0x16, 0xA3, 0x4, 0x59,
+  0x5B, 0xB0, 0x3, 0xBA, 0xEC, 0x61, 0xE8, 0xC7, 0xFE, 0x50, 0x53,
+  0x52, 0xE8, 0x5E, 0xD, 0x5D, 0xB0, 0x2F, 0x50, 0x58, 0xFE, 0xC0,
+  0x50, 0xE8, 0x17, 0xE, 0x73, 0xF7, 0x2E, 0x3, 0x96, 0x0, 0x0,
+  0x2E, 0x12, 0x9E, 0x2, 0x0, 0x45, 0x45, 0x45, 0xE8, 0x38, 0xD,
+  0x58, 0x87, 0xD5, 0x5B, 0x88, 0x7, 0x43, 0x58, 0xFE, 0xC8, 0x75,
+  0xCE, 0x42, 0x42, 0x8B, 0xEA, 0xB4, 0x4, 0xE9, 0xB3, 0xFE, 0x51,
+  0x56, 0xB9, 0x7, 0x0, 0xBF, 0x9F, 0x4, 0xF8, 0xFC, 0x2E, 0xAC,
+  0x18, 0x5, 0x47, 0xE2, 0xF9, 0x5E, 0x59, 0xC3, 0x51, 0xB9, 0x7,
+  0x0, 0xBF, 0x9F, 0x4, 0xF8, 0xFC, 0x2E, 0xAC, 0x10, 0x5, 0x47,
+  0xE2, 0xF9, 0x59, 0xC3, 0x53, 0x51, 0x33, 0xFF, 0x57, 0xBB, 0x2,
+  0x5E, 0xA0, 0xA6, 0x4, 0x2E, 0xD7, 0xA, 0xC0, 0x74, 0xC, 0x5F,
+  0x98, 0x2B, 0xF8, 0x57, 0x8B, 0xD0, 0xE8, 0x32, 0xEF, 0xEB, 0xE8,
+  0xBB, 0x66, 0x60, 0xE8, 0x88, 0xC, 0xE8, 0x2D, 0xD, 0x73, 0x6,
+  0xE8, 0xE6, 0xB, 0x5F, 0x4F, 0x57, 0xE8, 0xB0, 0xB, 0x72, 0x1F,
+  0xBB, 0x7A, 0x60, 0xE8, 0x8E, 0xC, 0xE8, 0x58, 0xFC, 0x58, 0x2C,
+  0x9, 0x50, 0xBB, 0xF6, 0x7F, 0xE8, 0x6D, 0xC, 0xE8, 0x57, 0xD,
+  0x76, 0x7, 0xE8, 0xB9, 0xB, 0x58, 0xFE, 0xC0, 0x50, 0x58, 0x59,
+  0x5B, 0xA, 0xC0, 0xC3, 0x58, 0x59, 0x5B, 0xA, 0xC0, 0xC3, 0xBB,
+  0xB4, 0x4, 0x8A, 0x2F, 0xB1, 0x20, 0x8A, 0x26, 0x83, 0x4, 0xF6,
+  0xC4, 0x20, 0x74, 0xD, 0x3A, 0xE9, 0xB1, 0x2A, 0x75, 0x7, 0xF6,
+  0xC4, 0x4, 0x75, 0x2, 0x8A, 0xE9, 0x88, 0xF, 0xE8, 0xBF, 0xF2,
+  0x74, 0x32, 0xBD, 0xA5, 0x61, 0x2E, 0x3A, 0x86, 0x0, 0x0, 0x74,
+  0x9, 0x81, 0xFD, 0x9C, 0x61, 0x74, 0x26, 0x4D, 0xEB, 0xF0, 0x81,
+  0xED, 0x9C, 0x61, 0xD1, 0xE5, 0x2E, 0xFF, 0xA6, 0x61, 0x70, 0x75,
+  0x70, 0x75, 0x70, 0x79, 0x70, 0x79, 0x70, 0x79, 0x70, 0x79, 0x70,
+  0x75, 0x70, 0x79, 0x70, 0x3C, 0x70, 0x3C, 0x70, 0x4B, 0xC6, 0x7,
+  0x30, 0x8A, 0x26, 0x83, 0x4, 0xF6, 0xC4, 0x10, 0x74, 0x4, 0x4B,
+  0xC6, 0x7, 0x24, 0xF6, 0xC4, 0x4, 0x75, 0x5, 0x4B, 0x88, 0x2F,
+  0x32, 0xED, 0xC3, 0xA, 0xC0, 0xEB, 0x6, 0xC6, 0x7, 0x30, 0x43,
+  0xFE, 0xC8, 0x75, 0xF8, 0xC3, 0xE8, 0x89, 0xFD, 0xC6, 0x7, 0x30,
+  0x43, 0xFE, 0xC8, 0x75, 0xF5, 0xC3, 0xBB, 0xB4, 0x4, 0xC6, 0x7,
+  0x20, 0x53, 0xE8, 0xC1, 0xA, 0x5B, 0x9C, 0x79, 0xA, 0xC6, 0x7,
+  0x2D, 0x53, 0xE8, 0xEC, 0xC, 0x5B, 0xC, 0x1, 0x43, 0xC6, 0x7,
+  0x30, 0x9D, 0xC3, 0xCD, 0xD8, 0xE8, 0xDD, 0xFF, 0x75, 0x8, 0x43,
+  0xC6, 0x7, 0x0, 0xBB, 0xB4, 0x4, 0xC3, 0xE8, 0xC8, 0xA, 0x79,
+  0x12, 0xB9, 0x0, 0x7, 0x33, 0xC0, 0xA3, 0x83, 0x4, 0x89, 0xE,
+  0x81, 0x4, 0xE8, 0x5E, 0xFD, 0xE9, 0x31, 0xFF, 0xE9, 0x78, 0xFC,
+  0xE8, 0x81, 0xA, 0x79, 0x3, 0xE9, 0x60, 0x9F, 0x75, 0x1, 0xC3,
+  0xA0, 0xA6, 0x4, 0xD0, 0xE8, 0x50, 0xC6, 0x6, 0xA6, 0x4, 0x40,
+  0xD0, 0x16, 0xA6, 0x4, 0xBB, 0xAB, 0x4, 0xE8, 0x9, 0xD, 0xB9,
+  0x4, 0x0, 0x51, 0xE8, 0x37, 0xD, 0x8B, 0x16, 0xAB, 0x4, 0x8B,
+  0x1E, 0xAD, 0x4, 0xE8, 0xBB, 0xF7, 0x5A, 0x5B, 0xE8, 0x4B, 0xF6,
+  0xFE, 0xE, 0xA6, 0x4, 0x59, 0x74, 0xA, 0xE2, 0xE3, 0x58, 0x4,
+  0xC0, 0x0, 0x6, 0xA6, 0x4, 0xC3, 0xE9, 0x2F, 0xA, 0xBF, 0xBE,
+  0x25, 0x57, 0xBF, 0xA8, 0x4, 0xC6, 0x5, 0x1, 0xE8, 0x2C, 0xA,
+  0x75, 0x3, 0xE9, 0x36, 0xF1, 0x79, 0x7, 0xA, 0xFF, 0x75, 0xA,
+  0xE9, 0x93, 0x3, 0xA, 0xFF, 0x75, 0x3, 0xE9, 0xD, 0xA, 0xA,
+  0xDB, 0x79, 0x26, 0x80, 0x3E, 0xA6, 0x4, 0x99, 0x72, 0x3, 0xE9,
+  0xED, 0x9E, 0x52, 0x53, 0xFF, 0x36, 0xA3, 0x4, 0xFF, 0x36, 0xA5,
+  0x4, 0xE8, 0x32, 0x1, 0x5B, 0x5A, 0xE8, 0x5A, 0xB, 0xE8, 0x3D,
+  0xB, 0x5B, 0x5A, 0x74, 0x3, 0xE9, 0xD1, 0x9E, 0xA0, 0xA5, 0x4,
+  0xA, 0xC0, 0x79, 0x9, 0xBF, 0xC4, 0x71, 0x57, 0x24, 0x7F, 0xA2,
+  0xA5, 0x4, 0x53, 0x52, 0x80, 0xCB, 0x7F, 0x9C, 0xFF, 0x36, 0xA5,
+  0x4, 0xFF, 0x36, 0xA3, 0x4, 0xE8, 0x2, 0x1, 0x5A, 0x5B, 0xE8,
+  0x2A, 0xB, 0x75, 0x1C, 0x52, 0x53, 0x33, 0xD2, 0xBB, 0x0, 0x90,
+  0xE8, 0x1E, 0xB, 0x5B, 0x5A, 0x79, 0xE, 0x9D, 0x5A, 0x5B, 0xEB,
+  0x3C, 0x90, 0x33, 0xD2, 0xBB, 0x0, 0x81, 0xE9, 0x12, 0xF7, 0x9D,
+  0x79, 0xE, 0x53, 0x52, 0xE8, 0x2F, 0x1, 0x8A, 0xC2, 0xE8, 0xC5,
+  0x2, 0x5A, 0x5B, 0xD0, 0xD8, 0x8F, 0x6, 0xA3, 0x4, 0x8F, 0x6,
+  0xA5, 0x4, 0x9F, 0x80, 0x26, 0xA5, 0x4, 0x7F, 0x9E, 0x73, 0x4,
+  0xBF, 0xB0, 0x7D, 0x57, 0x53, 0x52, 0xE8, 0x15, 0x1, 0x5A, 0x5B,
+  0xE8, 0x3, 0xFB, 0xE9, 0x85, 0xF0, 0x53, 0x52, 0xE8, 0xFF, 0x0,
+  0x89, 0x16, 0xB2, 0x4, 0xC7, 0x6, 0xA3, 0x4, 0x0, 0x0, 0xC7,
+  0x6, 0xA5, 0x4, 0x0, 0x81, 0xD1, 0x2E, 0xB2, 0x4, 0x73, 0x7,
+  0x5A, 0x5B, 0x53, 0x52, 0xE8, 0xDE, 0xFA, 0xF7, 0x6, 0xB2, 0x4,
+  0xFF, 0xFF, 0x74, 0x15, 0x5A, 0x5B, 0xE8, 0x21, 0xC, 0xE8, 0x8D,
+  0xA, 0xE8, 0xCB, 0xFA, 0x5A, 0x5B, 0xE8, 0x16, 0xC, 0xE8, 0x82,
+  0xA, 0xEB, 0xD6, 0x5A, 0x5B, 0xC3, 0x8A, 0xE, 0xA6, 0x4, 0x80,
+  0xE9, 0xB8, 0x73, 0x39, 0xF6, 0xD9, 0x9C, 0xBB, 0xA4, 0x4, 0x8A,
+  0x87, 0x1, 0x0, 0x88, 0x87, 0x3, 0x0, 0xA, 0xC0, 0x9C, 0xC,
+  0x80, 0x88, 0x87, 0x1, 0x0, 0xC6, 0x87, 0x2, 0x0, 0xB8, 0x9D,
+  0x9C, 0x79, 0x3, 0xE8, 0x22, 0x0, 0x32, 0xED, 0xE8, 0x12, 0x0,
+  0x9D, 0x79, 0x3, 0xE8, 0x26, 0x0, 0xC6, 0x6, 0x9E, 0x4, 0x0,
+  0x9D, 0x73, 0x3, 0xE9, 0xBD, 0x1, 0xC3, 0x51, 0x53, 0xF8, 0xE8,
+  0x7A, 0x9, 0x5B, 0x59, 0xE2, 0xF6, 0xC3, 0x53, 0xBB, 0x9F, 0x4,
+  0x83, 0x2F, 0x1, 0x73, 0x4, 0x43, 0x43, 0xEB, 0xF7, 0x5B, 0xC3,
+  0x53, 0xBB, 0x9F, 0x4, 0xFE, 0x7, 0x75, 0x3, 0x43, 0xEB, 0xF9,
+  0x5B, 0xC3, 0x8A, 0xE, 0xA6, 0x4, 0x80, 0xE9, 0x98, 0x73, 0x41,
+  0xF6, 0xD9, 0x9C, 0x8B, 0x16, 0xA3, 0x4, 0x8B, 0x1E, 0xA5, 0x4,
+  0xA, 0xDB, 0x9C, 0x88, 0x1E, 0xA7, 0x4, 0xC6, 0x6, 0xA6, 0x4,
+  0x98, 0x80, 0xCB, 0x80, 0x9D, 0x9C, 0x79, 0x6, 0x83, 0xEA, 0x1,
+  0x80, 0xDB, 0x0, 0x32, 0xED, 0xA, 0xC9, 0x74, 0x6, 0xD0, 0xEB,
+  0xD1, 0xDA, 0xE2, 0xFA, 0x9D, 0x9F, 0x79, 0x5, 0x42, 0x75, 0x2,
+  0xFE, 0xC3, 0x9D, 0x73, 0x5, 0x32, 0xE4, 0xE9, 0xA9, 0x1, 0x9E,
+  0x79, 0xA, 0xF7, 0xD2, 0xF6, 0xD3, 0x83, 0xC2, 0x1, 0x80, 0xD3,
+  0x0, 0xC3, 0xB1, 0x98, 0x2A, 0xE, 0xA6, 0x4, 0xF8, 0xEB, 0xAA,
+  0xE8, 0x66, 0x8, 0x7E, 0x51, 0xBA, 0x0, 0x0, 0xBB, 0x0, 0x81,
+  0xE8, 0xBE, 0x9, 0x75, 0x9, 0x89, 0x16, 0xA3, 0x4, 0x89, 0x16,
+  0xA5, 0x4, 0xC3, 0xA0, 0xA6, 0x4, 0x2C, 0x80, 0x98, 0x50, 0xC6,
+  0x6, 0xA6, 0x4, 0x80, 0xE8, 0x1B, 0xB, 0xBB, 0x76, 0x61, 0xE8,
+  0x18, 0x2, 0x5A, 0x5B, 0xE8, 0x10, 0xB, 0xE8, 0x7C, 0x9, 0xBB,
+  0x87, 0x61, 0xE8, 0xA, 0x2, 0x5A, 0x5B, 0xE8, 0x91, 0xF5, 0x5A,
+  0xE8, 0xFE, 0xA, 0xE8, 0xD9, 0xF8, 0x5A, 0x5B, 0xE8, 0x1A, 0xF4,
+  0xBB, 0x31, 0x80, 0xBA, 0x18, 0x72, 0xE9, 0x9D, 0xF9, 0xE9, 0xF4,
+  0x9C, 0xE9, 0x5C, 0x94, 0x9F, 0x86, 0xE0, 0x50, 0xB0, 0x1, 0xEB,
+  0x2, 0x32, 0xC0, 0xA2, 0x55, 0x4, 0x58, 0x86, 0xC4, 0x9E, 0xBA,
+  0x0, 0x0, 0x89, 0x1E, 0x53, 0x4, 0x74, 0x3, 0xE8, 0xE9, 0xC3,
+  0x89, 0x1E, 0x3B, 0x3, 0xE8, 0xAC, 0x93, 0x75, 0xD7, 0x8B, 0xE3,
+  0x8B, 0x36, 0x53, 0x4, 0x39, 0x37, 0x75, 0xCD, 0x52, 0x8A, 0xA7,
+  0x2, 0x0, 0x50, 0x52, 0x83, 0xC3, 0x4, 0xF6, 0x87, 0xFF, 0xFF,
+  0x80, 0x78, 0x41, 0xB9, 0x2, 0x0, 0xFC, 0x8B, 0xF3, 0xBF, 0xA3,
+  0x4, 0xF3, 0xA5, 0x5B, 0x56, 0x53, 0xF6, 0x6, 0x55, 0x4, 0xFF,
+  0x75, 0xF, 0xBE, 0x56, 0x4, 0x83, 0xEF, 0x4, 0xB9, 0x2, 0x0,
+  0xF3, 0xA5, 0x32, 0xC0, 0x74, 0x3, 0xE8, 0x4B, 0xF0, 0x5F, 0xBE,
+  0xA3, 0x4, 0xB9, 0x2, 0x0, 0xFC, 0xF3, 0xA5, 0x5E, 0x8B, 0x14,
+  0x8B, 0x8C, 0x2, 0x0, 0x83, 0xC6, 0x4, 0x56, 0xE8, 0x49, 0xF0,
+  0xEB, 0x27, 0x83, 0xC3, 0x4, 0x8B, 0xF, 0x43, 0x43, 0x5E, 0x8B,
+  0x14, 0xF6, 0x6, 0x55, 0x4, 0xFF, 0x75, 0x6, 0x8B, 0x16, 0x56,
+  0x4, 0xEB, 0x4, 0x3, 0xD1, 0x70, 0x35, 0x89, 0x14, 0x52, 0x8B,
+  0x17, 0x43, 0x43, 0x58, 0x53, 0xE8, 0xA5, 0xF1, 0x5B, 0x59, 0x2A,
+  0xC5, 0xE8, 0x1F, 0xF1, 0x74, 0xB, 0x89, 0x16, 0x2E, 0x0, 0x8B,
+  0xD1, 0x87, 0xD3, 0xE9, 0x7C, 0x9A, 0x8B, 0xE3, 0x89, 0x1E, 0x45,
+  0x3, 0x8B, 0x1E, 0x3B, 0x3, 0x80, 0x3F, 0x2C, 0x75, 0x9, 0xE8,
+  0x55, 0xF6, 0xE8, 0x42, 0xFF, 0xE9, 0x93, 0x93, 0xE9, 0xA8, 0x9A,
+  0x51, 0x53, 0x56, 0x57, 0x52, 0xB2, 0x39, 0xBB, 0x9E, 0x4, 0xBF,
+  0xA5, 0x4, 0xBE, 0xA6, 0x4, 0xEB, 0x19, 0x53, 0xB9, 0x4, 0x0,
+  0xF8, 0xD1, 0x17, 0x43, 0x43, 0xE2, 0xFA, 0x5B, 0xF6, 0x7, 0x40,
+  0x75, 0x29, 0xFE, 0xC, 0x74, 0x2A, 0xFE, 0xCA, 0x74, 0x26, 0xF6,
+  0x5, 0xFF, 0x78, 0x21, 0x75, 0xE0, 0x80, 0x2C, 0x8, 0x76, 0x1A,
+  0x80, 0xEA, 0x8, 0x76, 0x15, 0xBE, 0xA4, 0x4, 0xB9, 0x7, 0x0,
+  0xFD, 0xF3, 0xA4, 0x80, 0x26, 0x9E, 0x4, 0x20, 0xEB, 0xBE, 0x80,
+  0xF, 0x20, 0xEB, 0xD2, 0x5A, 0x5F, 0x5E, 0x5B, 0x59, 0x76, 0x3,
+  0xE9, 0x74, 0x4, 0xE9, 0xC0, 0x6, 0x8A, 0x3E, 0xA6, 0x4, 0xB9,
+  0x4, 0x0, 0xA, 0xDB, 0x78, 0x21, 0x75, 0x11, 0x80, 0xEF, 0x8,
+  0x72, 0x17, 0x8A, 0xDE, 0x8A, 0xF2, 0x8A, 0xD4, 0x32, 0xE4, 0xE2,
+  0xEB, 0x74, 0xB, 0xF8, 0xD0, 0xD4, 0xD1, 0xD2, 0xD0, 0xD3, 0xFE,
+  0xCF, 0x75, 0xDE, 0xE9, 0xA1, 0x6, 0x88, 0x3E, 0xA6, 0x4, 0xE9,
+  0x83, 0x4, 0xCC, 0x20, 0xEB, 0xF4, 0x88, 0x3E, 0xA6, 0x4, 0xE9,
+  0x78, 0x4, 0x53, 0xE8, 0x2, 0x0, 0x5B, 0xC3, 0xE8, 0x2D, 0x0,
+  0xBB, 0xA, 0x4, 0xEB, 0xC, 0x53, 0xE8, 0x2, 0x0, 0x5B, 0xC3,
+  0xE8, 0x1F, 0x0, 0xBB, 0x63, 0x4, 0x80, 0x3E, 0xA8, 0x4, 0x1,
+  0x78, 0x7, 0x75, 0x12, 0xC6, 0x6, 0xA8, 0x4, 0x2, 0xE8, 0x81,
+  0xAF, 0xB0, 0xD, 0xE8, 0x89, 0xAF, 0xB0, 0xA, 0xE8, 0x84, 0xAF,
+  0xC3, 0xFC, 0xA, 0xFF, 0xBE, 0x3, 0x62, 0x74, 0xA, 0xF6, 0x6,
+  0xA7, 0x4, 0x80, 0x79, 0x3, 0xBE, 0xB, 0x62, 0xE8, 0x7B, 0x6,
+  0x72, 0x8, 0xBF, 0x9F, 0x4, 0xB9, 0x4, 0x0, 0xEB, 0x9, 0x83,
+  0xC6, 0x4, 0xBF, 0xA3, 0x4, 0xB9, 0x2, 0x0, 0x2E, 0xA5, 0xE2,
+  0xFC, 0xC3, 0xE8, 0xD, 0x9, 0x53, 0xE8, 0x81, 0x7, 0xE8, 0xB6,
+  0xF7, 0x5B, 0xE8, 0x5, 0x0, 0x5A, 0x5B, 0xE9, 0xAD, 0xF7, 0x2E,
+  0x8A, 0x7, 0x98, 0xE8, 0xF6, 0x8, 0x50, 0x43, 0x2E, 0x8B, 0x7,
+  0xA3, 0xA3, 0x4, 0x83, 0xC3, 0x2, 0x2E, 0x8B, 0x7, 0xA3, 0xA5,
+  0x4, 0x83, 0xC3, 0x2, 0x58, 0x5A, 0x59, 0x48, 0x74, 0x1C, 0x51,
+  0x52, 0x50, 0x53, 0x87, 0xD9, 0xE8, 0x83, 0xF7, 0x5B, 0x53, 0x2E,
+  0x8B, 0x17, 0x2E, 0x8B, 0x9F, 0x2, 0x0, 0xE8, 0xEA, 0xF1, 0x5B,
+  0x83, 0xC3, 0x4, 0xEB, 0xDE, 0xC3, 0x53, 0xD0, 0xE8, 0x73, 0x3,
+  0xE9, 0x9, 0x1, 0xBB, 0xB2, 0x60, 0xE8, 0xD6, 0x6, 0xE8, 0x2F,
+  0x7, 0x72, 0x9, 0x5B, 0xE8, 0x23, 0xFB, 0x4B, 0xC6, 0x7, 0x25,
+  0xC3, 0xE8, 0xF3, 0x5, 0xB5, 0x10, 0x73, 0x2, 0xB5, 0x7, 0xE8,
+  0xBD, 0x5, 0x74, 0x3, 0xE8, 0x4, 0xFA, 0x5B, 0x78, 0x3F, 0x8A,
+  0xD0, 0x2, 0xC5, 0x2A, 0x6, 0x82, 0x4, 0x79, 0x5, 0xF6, 0xD8,
+  0xE8, 0xC2, 0xFA, 0x32, 0xC9, 0xE8, 0xB1, 0x0, 0xFF, 0x36, 0x81,
+  0x4, 0x52, 0xE8, 0xDA, 0xF8, 0x5A, 0x8F, 0x6, 0x81, 0x4, 0xFF,
+  0x36, 0x81, 0x4, 0x32, 0xC0, 0xA, 0xC2, 0x74, 0x6, 0xE8, 0xB3,
+  0xFA, 0xE8, 0x39, 0xF8, 0x8F, 0x6, 0x81, 0x4, 0xFF, 0x36, 0x81,
+  0x4, 0xA0, 0x81, 0x4, 0xE9, 0x72, 0x2, 0x8A, 0xD0, 0xA0, 0x81,
+  0x4, 0xA, 0xC0, 0x74, 0x2, 0xFE, 0xC8, 0x8A, 0xF0, 0x2, 0xC2,
+  0x8A, 0xC8, 0x78, 0x4, 0x32, 0xC0, 0x8A, 0xC8, 0x79, 0x11, 0x50,
+  0x51, 0x52, 0x53, 0xE8, 0xA9, 0x5, 0x5B, 0x5A, 0x59, 0x58, 0xFE,
+  0xC0, 0x78, 0xF1, 0x8A, 0xE1, 0x8A, 0xC2, 0x2A, 0xC1, 0x2, 0xC5,
+  0x79, 0x17, 0xA0, 0x82, 0x4, 0xE8, 0x5A, 0xFA, 0xC6, 0x7, 0x2E,
+  0x89, 0x1E, 0x52, 0x3, 0x43, 0x32, 0xC9, 0x8A, 0xC6, 0x2A, 0xC5,
+  0xE9, 0xA1, 0x9, 0xA0, 0x82, 0x4, 0x52, 0xFF, 0x36, 0x81, 0x4,
+  0x2A, 0xC5, 0x2A, 0xC2, 0x2, 0xC1, 0x78, 0x3, 0xE8, 0x36, 0xFA,
+  0xE8, 0x27, 0x0, 0xFF, 0x36, 0x81, 0x4, 0xE8, 0x51, 0xF8, 0xA0,
+  0x82, 0x4, 0x8F, 0x6, 0x81, 0x4, 0xA, 0xC0, 0x58, 0x5A, 0x75,
+  0x7, 0x8B, 0x1E, 0x52, 0x3, 0xE9, 0x67, 0x1, 0x2, 0xC2, 0xFE,
+  0xC8, 0x78, 0x3, 0xE8, 0xF, 0xFA, 0xE9, 0x5B, 0x1, 0x8A, 0xC5,
+  0x2, 0xC2, 0x2A, 0xC1, 0xFE, 0xC0, 0x8A, 0xE8, 0x2C, 0x3, 0x7F,
+  0xFC, 0x4, 0x3, 0x8A, 0xC8, 0xA0, 0x83, 0x4, 0x24, 0x40, 0x75,
+  0x2, 0x8A, 0xC8, 0xC3, 0xE8, 0xFE, 0x4, 0xB4, 0x7, 0x72, 0x2,
+  0xB4, 0x10, 0xE8, 0xC8, 0x4, 0x5B, 0xF9, 0x74, 0x9, 0x53, 0x50,
+  0xE8, 0xB, 0xF9, 0x5A, 0x5B, 0x8A, 0xE6, 0x9C, 0x50, 0x8B, 0x16,
+  0x81, 0x4, 0xA, 0xF6, 0x9C, 0xA, 0xD2, 0x74, 0x2, 0xFE, 0xCA,
+  0x2, 0xF2, 0x9D, 0x74, 0x9, 0xF6, 0x6, 0x83, 0x4, 0x4, 0x75,
+  0x2, 0xFE, 0xCE, 0x2A, 0xF4, 0x8A, 0xE6, 0x50, 0x78, 0x3, 0xE9,
+  0x4E, 0x0, 0x53, 0x50, 0x50, 0xE8, 0xE1, 0x4, 0x58, 0xFE, 0xC4,
+  0x75, 0xF7, 0xE8, 0xBF, 0x4, 0xE8, 0x8E, 0x7, 0x58, 0x50, 0xB9,
+  0x3, 0x0, 0xD2, 0xE4, 0xE8, 0xA6, 0x4, 0x72, 0x10, 0x8A, 0xC4,
+  0x98, 0xBB, 0xB2, 0x60, 0x3, 0xD8, 0xE8, 0x6B, 0x5, 0xE8, 0x55,
+  0x6, 0xEB, 0xE, 0xBB, 0x6E, 0x60, 0x8A, 0xC4, 0x98, 0x3, 0xD8,
+  0xE8, 0x53, 0x5, 0xE8, 0xF8, 0x5, 0x58, 0x5B, 0x78, 0x11, 0x58,
+  0x59, 0xFE, 0xC1, 0x51, 0x50, 0x53, 0x50, 0xE8, 0x9D, 0x4, 0x58,
+  0x5B, 0xEB, 0x2, 0x32, 0xE4, 0xF6, 0xDC, 0xA0, 0x82, 0x4, 0x2,
+  0xE0, 0xFE, 0xC4, 0xA, 0xC0, 0x74, 0x9, 0xF6, 0x6, 0x83, 0x4,
+  0x4, 0x75, 0x2, 0xFE, 0xCC, 0x8A, 0xEC, 0x32, 0xC9, 0x58, 0xFF,
+  0x36, 0x81, 0x4, 0x50, 0x88, 0x2E, 0x82, 0x4, 0xE8, 0x5E, 0xF7,
+  0x58, 0xA, 0xE4, 0x7E, 0x5, 0x8A, 0xC4, 0xE8, 0x3F, 0xF9, 0x58,
+  0xA3, 0x81, 0x4, 0xA, 0xC0, 0x75, 0xC, 0x4B, 0x8A, 0x7, 0x3C,
+  0x2E, 0x74, 0x1, 0x43, 0x89, 0x1E, 0x52, 0x3, 0x58, 0x9D, 0x72,
+  0x15, 0x2, 0xC4, 0x8A, 0x26, 0x82, 0x4, 0x2A, 0xC4, 0xA, 0xE4,
+  0x74, 0x9, 0xF6, 0x6, 0x83, 0x4, 0x4, 0x75, 0x2, 0xFE, 0xC0,
+  0xA, 0xC0, 0xE8, 0x4A, 0xF6, 0x8B, 0xD9, 0xE9, 0x47, 0x0, 0x8A,
+  0xE0, 0xF6, 0xC4, 0x40, 0xB4, 0x3, 0x75, 0x2, 0x32, 0xE4, 0xA3,
+  0x83, 0x4, 0x89, 0xE, 0x81, 0x4, 0x8A, 0xE0, 0xBB, 0xB4, 0x4,
+  0xC6, 0x7, 0x20, 0xF6, 0xC4, 0x8, 0x74, 0x3, 0xC6, 0x7, 0x2B,
+  0x53, 0xE8, 0xB6, 0x3, 0x5B, 0x79, 0x8, 0xC6, 0x7, 0x2D, 0x53,
+  0xE8, 0xE2, 0x5, 0x5B, 0x43, 0xC6, 0x7, 0x30, 0xE8, 0xD1, 0x3,
+  0xA1, 0x83, 0x4, 0x8B, 0xE, 0x81, 0x4, 0x78, 0x3, 0xE9, 0xB3,
+  0xFD, 0xE9, 0x68, 0x0, 0x53, 0xE8, 0x3B, 0xF8, 0x5B, 0x74, 0x3,
+  0x88, 0x2F, 0x43, 0xC6, 0x7, 0x0, 0xBB, 0xB3, 0x4, 0x43, 0x8B,
+  0x3E, 0x52, 0x3, 0x8B, 0x16, 0x81, 0x4, 0xA0, 0x82, 0x4, 0x32,
+  0xE4, 0x2B, 0xFB, 0x2B, 0xF8, 0x74, 0x43, 0x8A, 0x7, 0x3C, 0x20,
+  0x74, 0xE6, 0x3C, 0x2A, 0x74, 0xE2, 0xB4, 0x1, 0x4B, 0x53, 0x50,
+  0xE8, 0xEA, 0xEA, 0x32, 0xE4, 0x3C, 0x2D, 0x74, 0xF6, 0x3C, 0x2B,
+  0x74, 0xF2, 0x3C, 0x24, 0x74, 0xEE, 0x3C, 0x30, 0x75, 0x16, 0x43,
+  0xE8, 0xD4, 0xEA, 0x73, 0x10, 0x4B, 0xEB, 0x3, 0x4B, 0x88, 0x7,
+  0x58, 0xA, 0xE4, 0x74, 0xF8, 0x83, 0xC4, 0x2, 0xEB, 0xB3, 0x58,
+  0xA, 0xE4, 0x74, 0xFB, 0x5B, 0xC6, 0x7, 0x25, 0xC3, 0xA1, 0x83,
+  0x4, 0x8A, 0xCC, 0xB5, 0x6, 0xD0, 0xE8, 0x8B, 0x16, 0x81, 0x4,
+  0x73, 0xB, 0x53, 0x52, 0xE8, 0x45, 0xF3, 0x32, 0xC0, 0x5A, 0xE9,
+  0x3F, 0xFE, 0x8A, 0xC6, 0x2C, 0x5, 0x78, 0x3, 0xE8, 0x26, 0xF8,
+  0x52, 0xE8, 0xDA, 0xF5, 0x58, 0x50, 0xA, 0xC0, 0x75, 0x1, 0x4B,
+  0xFE, 0xC8, 0x78, 0x6, 0xE8, 0x14, 0xF8, 0xC6, 0x7, 0x0, 0x8F,
+  0x6, 0x81, 0x4, 0xE9, 0x59, 0xFF, 0xE8, 0xEB, 0x2, 0x74, 0x6D,
+  0x79, 0xC, 0xA1, 0xA3, 0x4, 0xA3, 0xB, 0x0, 0xA0, 0xA5, 0x4,
+  0xA2, 0xD, 0x0, 0xA1, 0xB, 0x0, 0x2E, 0xF7, 0x26, 0x6B, 0x62,
+  0x8B, 0xF8, 0x8A, 0xCA, 0x2E, 0xA0, 0x6D, 0x62, 0xF6, 0x26, 0xB,
+  0x0, 0x2, 0xC8, 0x2E, 0xA0, 0xD, 0x0, 0x2E, 0xF6, 0x26, 0x6B,
+  0x62, 0x2, 0xC8, 0x32, 0xC0, 0x2E, 0x8B, 0x16, 0x6E, 0x62, 0x3,
+  0xD7, 0x2E, 0x8A, 0x1E, 0x70, 0x62, 0x12, 0xD9, 0xA2, 0xA7, 0x4,
+  0xB0, 0x80, 0xA2, 0xA6, 0x4, 0x89, 0x16, 0xB, 0x0, 0x88, 0x1E,
+  0xD, 0x0, 0xB0, 0x4, 0xA2, 0xFB, 0x2, 0xE9, 0xBB, 0xFB, 0x0,
+  0x0, 0x0, 0xBB, 0xB3, 0x4, 0xB9, 0x20, 0x0, 0x3, 0x7, 0x43,
+  0x43, 0xE2, 0xFA, 0x24, 0xFE, 0xA3, 0xB, 0x0, 0xEB, 0xA1, 0x8B,
+  0x16, 0xB, 0x0, 0x8A, 0x1E, 0xD, 0x0, 0x33, 0xC0, 0xB0, 0x80,
+  0xA2, 0xA6, 0x4, 0x88, 0x26, 0xA7, 0x4, 0xE9, 0x8F, 0xFB, 0x53,
+  0x51, 0xBB, 0x9E, 0x4, 0x81, 0x7, 0x80, 0x0, 0xB9, 0x3, 0x0,
+  0x73, 0xE, 0x43, 0x43, 0xFF, 0x7, 0x75, 0x8, 0xE2, 0xF8, 0xFE,
+  0x6, 0xA6, 0x4, 0xD1, 0x1F, 0x59, 0x74, 0x20, 0xF6, 0x6, 0x9E,
+  0x4, 0xFF, 0x75, 0x5, 0x80, 0x26, 0x9F, 0x4, 0xFE, 0xBB, 0xA5,
+  0x4, 0x8A, 0x7, 0x8A, 0xA7, 0x2, 0x0, 0x24, 0x7F, 0x80, 0xE4,
+  0x80, 0xA, 0xE0, 0x88, 0x27, 0x5B, 0xC3, 0x90, 0x90, 0x90, 0xE9,
+  0x88, 0xFB, 0x80, 0xE4, 0xE0, 0x80, 0xC4, 0x80, 0x73, 0x1C, 0x9C,
+  0x42, 0x75, 0x12, 0x9D, 0xFE, 0xC3, 0x75, 0x13, 0xF9, 0xD0, 0xDB,
+  0xFE, 0x6, 0xA6, 0x4, 0x75, 0xA, 0x90, 0xE9, 0x6A, 0xFB, 0x9D,
+  0x75, 0x3, 0x80, 0xE2, 0xFE, 0x56, 0xBE, 0xA3, 0x4, 0x89, 0x14,
+  0x46, 0x46, 0x8A, 0x3E, 0xA7, 0x4, 0x81, 0xE3, 0x7F, 0x80, 0xA,
+  0xDF, 0x88, 0x1C, 0x5E, 0xC3, 0x8B, 0xF1, 0xE8, 0xB4, 0x4, 0x8B,
+  0xCE, 0x51, 0xE8, 0x9, 0x2, 0x72, 0x9, 0x80, 0x3E, 0xA6, 0x4,
+  0xB8, 0x79, 0xF, 0xEB, 0x7, 0x80, 0x3E, 0xA6, 0x4, 0x98, 0x79,
+  0x6, 0xE8, 0x0, 0x2, 0xE8, 0xCF, 0x4, 0xBB, 0x86, 0x4, 0xE8,
+  0x51, 0x4, 0x59, 0x51, 0xBF, 0x8E, 0x4, 0xBB, 0x86, 0x4, 0xE8,
+  0x35, 0x4, 0xBB, 0x86, 0x4, 0xE8, 0x5D, 0x4, 0xE8, 0xFD, 0x1,
+  0xE8, 0xB2, 0x4, 0xBB, 0x86, 0x4, 0xE8, 0x34, 0x4, 0xE8, 0xFB,
+  0x1, 0xBB, 0x94, 0x4, 0xE8, 0xC5, 0x1, 0x73, 0x3, 0x83, 0xEB,
+  0x4, 0xE8, 0x57, 0x4, 0x59, 0x75, 0x4, 0xFE, 0xC1, 0xEB, 0xCC,
+  0x8B, 0xE9, 0xE8, 0x75, 0x4, 0x8B, 0xCD, 0xC3, 0x80, 0x26, 0xA5,
+  0x4, 0x7F, 0xE8, 0x86, 0x0, 0xE8, 0xA5, 0x0, 0xC6, 0x6, 0xB2,
+  0x4, 0x7F, 0xE8, 0xA3, 0xEC, 0xE8, 0x84, 0x0, 0xEB, 0x1B, 0x65,
+  0xED, 0xA1, 0xA5, 0x4, 0x80, 0xFC, 0x77, 0x73, 0x1, 0xC3, 0xA,
+  0xC0, 0x79, 0x9, 0x24, 0x7F, 0xA2, 0xA5, 0x4, 0xB8, 0xB0, 0x7D,
+  0x50, 0xE8, 0x5B, 0x0, 0xA0, 0xA6, 0x4, 0xA, 0xC0, 0x74, 0x5,
+  0x80, 0x6, 0xA6, 0x4, 0x2, 0xE8, 0x61, 0x0, 0xA1, 0xB1, 0x4,
+  0x80, 0xFC, 0x82, 0x9C, 0xF6, 0xC4, 0x1, 0x75, 0x2, 0xA8, 0x40,
+  0x9C, 0xE8, 0x49, 0x0, 0x9D, 0x74, 0x9, 0xBB, 0x32, 0x60, 0xE8,
+  0x37, 0x2, 0xE8, 0x48, 0xEC, 0x80, 0x2E, 0xA6, 0x4, 0x2, 0x73,
+  0x3, 0xE8, 0x0, 0x1, 0xE8, 0x3, 0xF1, 0xA0, 0xA6, 0x4, 0x3C,
+  0x74, 0x73, 0xB, 0xBA, 0xDB, 0xF, 0xBB, 0x49, 0x83, 0xE8, 0x8E,
+  0xF2, 0xEB, 0x6, 0xBB, 0x34, 0x62, 0xE8, 0xC6, 0xFA, 0x9D, 0x75,
+  0x5, 0x80, 0x36, 0xA5, 0x4, 0x80, 0xC3, 0xBB, 0x63, 0x62, 0xE8,
+  0x0, 0x2, 0xE8, 0x8, 0xF1, 0xE8, 0xC7, 0xF1, 0xE8, 0x6, 0x0,
+  0xE8, 0x8, 0xEC, 0xE9, 0x19, 0x3, 0xE8, 0xAD, 0x3, 0xE8, 0xA4,
+  0xF7, 0xE8, 0x0, 0x2, 0xE8, 0xC3, 0x3, 0xC3, 0xBB, 0x32, 0x60,
+  0xE9, 0xDE, 0x1, 0xB8, 0xF0, 0xC3, 0xFF, 0x36, 0xA5, 0x4, 0xFF,
+  0x36, 0xA3, 0x4, 0xE8, 0x56, 0xFF, 0x5A, 0x5B, 0xFF, 0x36, 0xA3,
+  0x4, 0xFF, 0x36, 0xA5, 0x4, 0xE8, 0xF9, 0x1, 0xE8, 0x2C, 0xFF,
+  0x5B, 0x5A, 0xE9, 0x11, 0xEE, 0xA1, 0xA5, 0x4, 0xA, 0xC0, 0x79,
+  0x9, 0xBF, 0xB0, 0x7D, 0x57, 0x24, 0x7F, 0xA2, 0xA5, 0x4, 0x80,
+  0xFC, 0x81, 0x72, 0xC, 0xBF, 0x39, 0x7B, 0x57, 0x33, 0xD2, 0xBB,
+  0x0, 0x81, 0xE8, 0xF0, 0xED, 0xBA, 0xA2, 0x30, 0xBB, 0x9, 0x7F,
+  0xE8, 0xE1, 0x1, 0x78, 0x3A, 0xBF, 0x42, 0x7B, 0x57, 0xFF, 0x36,
+  0xA3, 0x4, 0xFF, 0x36, 0xA5, 0x4, 0xBA, 0xD7, 0xB3, 0xBB, 0x5D,
+  0x81, 0xE8, 0x65, 0xEC, 0x5B, 0x5A, 0xFF, 0x36, 0xA3, 0x4, 0xFF,
+  0x36, 0xA5, 0x4, 0xE8, 0xA3, 0x1, 0xBB, 0x49, 0x62, 0xE8, 0x31,
+  0xFA, 0x5B, 0x5A, 0xFF, 0x36, 0xA3, 0x4, 0xFF, 0x36, 0xA5, 0x4,
+  0xE8, 0x90, 0x1, 0x5B, 0x5A, 0xE8, 0xAB, 0xED, 0xBB, 0x52, 0x62,
+  0xE9, 0x6, 0xFA, 0xBA, 0xDB, 0xF, 0xBB, 0x49, 0x81, 0xE9, 0x25,
+  0xEC, 0xBA, 0x92, 0xA, 0xBB, 0x6, 0x80, 0xE9, 0x28, 0xEC, 0xE8,
+  0x57, 0xB0, 0x3C, 0xD, 0x75, 0x3, 0xE8, 0x23, 0xB1, 0x2E, 0x8A,
+  0x7, 0x43, 0xA, 0xC0, 0x75, 0xEE, 0xC3, 0xBF, 0x9F, 0x4, 0xB9,
+  0x4, 0x0, 0xB8, 0x0, 0x0, 0xFC, 0xF3, 0xAB, 0xC3, 0xB8, 0x0,
+  0x0, 0xA3, 0xA3, 0x4, 0xA3, 0xA5, 0x4, 0xC3, 0xE8, 0x78, 0xE7,
+  0x79, 0xE, 0xA1, 0xA3, 0x4, 0xB, 0xC0, 0x74, 0x20, 0xB0, 0x1,
+  0x79, 0x1C, 0xF6, 0xD8, 0xC3, 0xCD, 0xD4, 0xA0, 0xA6, 0x4, 0xA,
+  0xC0, 0x74, 0x10, 0xA0, 0xA5, 0x4, 0xA, 0xC0, 0x74, 0x7, 0xB0,
+  0x1, 0x79, 0x5, 0xF6, 0xD8, 0xC3, 0xC, 0x1, 0xC3, 0xA0, 0xFB,
+  0x2, 0x3C, 0x8, 0xFE, 0xC8, 0xFE, 0xC8, 0xFE, 0xC8, 0xC3, 0xE8,
+  0xF1, 0xFF, 0x72, 0xC, 0x53, 0xBB, 0x6A, 0x61, 0xE8, 0xCE, 0x0,
+  0xE8, 0xED, 0xEA, 0x5B, 0xC3, 0x33, 0xD2, 0xBB, 0x0, 0x80, 0xE8,
+  0xAC, 0xEB, 0xC3, 0xE8, 0xD7, 0xFF, 0xBB, 0x2A, 0x60, 0x72, 0x11,
+  0xEB, 0x8, 0xE8, 0xCD, 0xFF, 0xBB, 0x3A, 0x60, 0x72, 0x7, 0xE8,
+  0xAB, 0x0, 0xE8, 0x75, 0xF0, 0xC3, 0xFF, 0x36, 0xA5, 0x4, 0xFF,
+  0x36, 0xA3, 0x4, 0xC6, 0x6, 0xFB, 0x2, 0x8, 0xE8, 0x9C, 0x0,
+  0xE8, 0x70, 0xEF, 0x5A, 0x5B, 0xE8, 0x6, 0xF1, 0xC3, 0xB9, 0x4,
+  0x0, 0xD1, 0x17, 0x43, 0x43, 0xE2, 0xFA, 0xC3, 0xB9, 0x4, 0x0,
+  0xD1, 0x1F, 0x4B, 0x4B, 0xE2, 0xFA, 0xC3, 0x80, 0x8F, 0x2, 0x0,
+  0x20, 0xE2, 0x1, 0xC3, 0xBB, 0xB0, 0x4, 0x80, 0xF9, 0x8, 0x72,
+  0x26, 0x51, 0xB9, 0x7, 0x0, 0xBB, 0xAA, 0x4, 0x8A, 0x27, 0x8A,
+  0x87, 0x1, 0x0, 0x88, 0x7, 0x43, 0xE2, 0xF7, 0x32, 0xC0, 0x88,
+  0x7, 0x59, 0x80, 0xE9, 0x8, 0x80, 0xE4, 0x20, 0x74, 0xD9, 0x8,
+  0x26, 0xAA, 0x4, 0xE9, 0xD2, 0xFF, 0xA, 0xC9, 0x74, 0xF, 0x51,
+  0xF8, 0xE8, 0xB7, 0xFF, 0x59, 0xF6, 0x87, 0x2, 0x0, 0x10, 0x75,
+  0xB9, 0xE2, 0xBF, 0xC3, 0xBE, 0x9F, 0x4, 0xBF, 0xAB, 0x4, 0xFC,
+  0xB9, 0x4, 0x0, 0x8B, 0x5, 0xA5, 0x89, 0x84, 0xFE, 0xFF, 0xE2,
+  0xF7, 0xC3, 0xBF, 0x7C, 0x4, 0xB9, 0x2, 0x0, 0xEB, 0x6, 0xBF,
+  0x78, 0x4, 0xB9, 0x4, 0x0, 0xFC, 0x2E, 0x8B, 0x7, 0xAB, 0x43,
+  0x43, 0xE2, 0xF8, 0x8B, 0xDF, 0x4B, 0x4B, 0xC3, 0xBF, 0xAB, 0x4,
+  0xEB, 0xEA, 0xBF, 0x9F, 0x4, 0xEB, 0xE5, 0xBF, 0xAB, 0x4, 0xB9,
+  0x4, 0x0, 0x87, 0xDE, 0xFC, 0xF3, 0xA5, 0x87, 0xDE, 0xC3, 0x51,
+  0x53, 0x57, 0xBB, 0x9F, 0x4, 0xBF, 0xAB, 0x4, 0xB9, 0x4, 0x0,
+  0xE8, 0xE9, 0xFF, 0x5F, 0x5B, 0x59, 0xC3, 0x51, 0x53, 0x57, 0xBB,
+  0xAB, 0x4, 0xBF, 0x9F, 0x4, 0xEB, 0xEB, 0x89, 0x16, 0xA3, 0x4,
+  0x89, 0x1E, 0xA5, 0x4, 0xC3, 0x8B, 0x16, 0xA3, 0x4, 0x8B, 0x1E,
+  0xA5, 0x4, 0xC3, 0xE8, 0xCF, 0xFE, 0x72, 0x3F, 0xE9, 0x89, 0x0,
+  0xE8, 0xD7, 0xED, 0x53, 0x57, 0x8A, 0xC3, 0x32, 0x6, 0xA5, 0x4,
+  0x78, 0x3C, 0xA, 0xDB, 0x78, 0x10, 0xA1, 0xA5, 0x4, 0x2B, 0xC3,
+  0x72, 0x3F, 0x75, 0x37, 0xA1, 0xA3, 0x4, 0x2B, 0xC2, 0xEB, 0x10,
+  0x8B, 0xC3, 0x2B, 0x6, 0xA5, 0x4, 0x72, 0x2E, 0x75, 0x26, 0x8B,
+  0xC2, 0x2B, 0x6, 0xA3, 0x4, 0x72, 0x24, 0x75, 0x1C, 0x32, 0xC0,
+  0xEB, 0x4A, 0xC0, 0xEB, 0x47, 0xE8, 0xA3, 0xED, 0x90, 0x90, 0x8B,
+  0x7, 0x32, 0x6, 0xA5, 0x4, 0x79, 0x13, 0x8A, 0x26, 0xA5, 0x4,
+  0xA, 0xE4, 0x78, 0x6, 0xB0, 0x1, 0xA, 0xC0, 0xEB, 0x2C, 0xB0,
+  0xFF, 0xF9, 0xEB, 0x27, 0x51, 0xB9, 0x2, 0x0, 0x87, 0xDE, 0xA0,
+  0xA5, 0x4, 0xA, 0xC0, 0x79, 0x2, 0x87, 0xF7, 0xFD, 0xA7, 0x75,
+  0x6, 0xE2, 0xFB, 0xB0, 0x0, 0xEB, 0xD, 0x73, 0x6, 0xB0, 0x1,
+  0xA, 0xC0, 0xEB, 0x5, 0xB0, 0xFF, 0xA, 0xC0, 0xF9, 0x59, 0x5F,
+  0x5B, 0xC3, 0xBB, 0xB1, 0x4, 0xE8, 0x56, 0xED, 0x90, 0x90, 0x8A,
+  0x5, 0x32, 0x7, 0x79, 0x2, 0xEB, 0xB3, 0x51, 0xB9, 0x4, 0x0,
+  0xEB, 0xC4, 0xBB, 0xFF, 0x61, 0xE8, 0xF2, 0xFE, 0xE8, 0x97, 0xFF,
+  0x75, 0xB, 0xC6, 0x6, 0xFB, 0x2, 0x2, 0xC7, 0x6, 0xA3, 0x4,
+  0x0, 0x80, 0xC3, 0x2E, 0x2B, 0x96, 0x0, 0x0, 0x2E, 0x1A, 0x9E,
+  0x2, 0x0, 0xC3, 0xE8, 0x9, 0xFE, 0x78, 0x8, 0xA0, 0xA5, 0x4,
+  0xA, 0xC0, 0x78, 0xE, 0xC3, 0xA1, 0xA3, 0x4, 0xB, 0xC0, 0x78,
+  0x11, 0xC3, 0xE8, 0xF4, 0xFD, 0x78, 0x8, 0xCD, 0xD2, 0x80, 0x36,
+  0xA5, 0x4, 0x80, 0xC3, 0xA1, 0xA3, 0x4, 0x3D, 0x0, 0x80, 0x75,
+  0xA, 0xCD, 0xD3, 0x53, 0xE8, 0xDB, 0xED, 0x5B, 0xE9, 0xE6, 0xFF,
+  0xF7, 0x1E, 0xA3, 0x4, 0xC3, 0xBB, 0x79, 0x4, 0xE8, 0x33, 0x0,
+  0xBF, 0x97, 0x4, 0xB9, 0x8, 0x0, 0xB8, 0x0, 0x0, 0xFC, 0xF3,
+  0xAB, 0xA2, 0x78, 0x4, 0xA2, 0xAA, 0x4, 0xC3, 0xE8, 0xB7, 0xFD,
+  0x72, 0x3, 0xE9, 0xA2, 0xFE, 0x8B, 0x17, 0x8B, 0x9F, 0x2, 0x0,
+  0xC3, 0xB9, 0x4, 0x0, 0xE8, 0xA5, 0xFD, 0x72, 0x3, 0xE9, 0x96,
+  0xFE, 0xB9, 0x2, 0x0, 0xE9, 0x90, 0xFE, 0xB9, 0x4, 0x0, 0x87,
+  0xFB, 0xBB, 0x9F, 0x4, 0xE8, 0x8F, 0xFD, 0x72, 0x3, 0xE9, 0x80,
+  0xFE, 0x87, 0xDF, 0xB9, 0x2, 0x0, 0xBF, 0xA3, 0x4, 0x87, 0xFB,
+  0xE9, 0x73, 0xFE, 0xB9, 0x4, 0x0, 0xBF, 0x9F, 0x4, 0xE8, 0x74,
+  0xFD, 0x72, 0x3, 0xE9, 0x65, 0xFE, 0xB9, 0x2, 0x0, 0xBF, 0xA3,
+  0x4, 0xE9, 0x5C, 0xFE, 0xE8, 0x63, 0xFD, 0x72, 0x3, 0xE9, 0x1D,
+  0xFF, 0xE9, 0xCD, 0xFE, 0xE8, 0x58, 0xFD, 0xB9, 0x4, 0x0, 0x73,
+  0x3, 0xB9, 0x2, 0x0, 0x5D, 0xBF, 0xA5, 0x4, 0xFF, 0x35, 0x4F,
+  0x4F, 0xE2, 0xFA, 0x55, 0xC3, 0xBF, 0xAB, 0x4, 0xB9, 0x4, 0x0,
+  0xEB, 0x11, 0xE8, 0x39, 0xFD, 0xBF, 0x9F, 0x4, 0xB9, 0x4, 0x0,
+  0x73, 0x6, 0xBF, 0xA3, 0x4, 0xB9, 0x2, 0x0, 0x58, 0x8F, 0x5,
+  0x47, 0x47, 0xE2, 0xFA, 0x50, 0xC3, 0xE8, 0x1F, 0xFD, 0x79, 0x1,
+  0xC3, 0xCD, 0xD5, 0x72, 0x3, 0xE9, 0xB4, 0xF3, 0xE9, 0x1B, 0xF4,
+  0x0, 0x0, 0xFA, 0xBA, 0x60, 0x0, 0x8E, 0xDA, 0x8E, 0xC2, 0x8E,
+  0xD2, 0x32, 0xC0, 0xA2, 0x64, 0x4, 0xB5, 0x91, 0xBB, 0x0, 0x0,
+  0xBA, 0x9A, 0x6, 0x8B, 0xF2, 0x2E, 0xAC, 0x88, 0x7, 0x43, 0x42,
+  0xFE, 0xCD, 0x75, 0xF4, 0xBC, 0xE, 0x7, 0xCD, 0x12, 0xFA, 0xBB,
+  0x40, 0x0, 0xF7, 0xE3, 0x8C, 0xDB, 0x2B, 0xC3, 0xBB, 0x0, 0x0,
+  0xF6, 0xC4, 0xF0, 0x75, 0x6, 0xB1, 0x4, 0xD3, 0xE0, 0x8B, 0xD8,
+  0x4B, 0x89, 0x1E, 0x2C, 0x0, 0x8B, 0xE3, 0xE9, 0x22, 0xCD, 0xB0,
+  0x2C, 0xA2, 0xF6, 0x1, 0xBB, 0xB7, 0x0, 0xC6, 0x7, 0x3A, 0x32,
+  0xC0, 0xA2, 0xF9, 0x2, 0xA2, 0x6, 0x0, 0xA2, 0x6B, 0x4, 0xA2,
+  0x65, 0x4, 0xA2, 0x28, 0x0, 0xBB, 0xE, 0x3, 0x89, 0x1E, 0xC,
+  0x3, 0xBB, 0x7A, 0x3, 0x89, 0x1E, 0xE2, 0x3, 0x8B, 0x1E, 0x2C,
+  0x0, 0x4B, 0x89, 0x1E, 0xA, 0x3, 0x4B, 0x53, 0xBB, 0xE, 0x7,
+  0xB0, 0x4, 0xA2, 0xDF, 0x4, 0x53, 0x89, 0x1E, 0xE0, 0x4, 0xA0,
+  0xDF, 0x4, 0xFE, 0xC0, 0x2, 0xC0, 0x8A, 0xD0, 0xB6, 0x0, 0x3,
+  0xDA, 0x5A, 0x87, 0xDA, 0x8B, 0x1E, 0xE0, 0x4, 0x88, 0x17, 0x43,
+  0x88, 0x37, 0x43, 0xA0, 0xDF, 0x4, 0xB9, 0x34, 0x0, 0xA, 0xC0,
+  0x74, 0xE, 0x87, 0xDA, 0x3, 0xD9, 0x87, 0xDA, 0x89, 0x17, 0x43,
+  0x43, 0xFE, 0xC8, 0x75, 0xF2, 0x87, 0xDA, 0x3, 0xD9, 0x43, 0x53,
+  0xFE, 0xC8, 0xA2, 0x36, 0x5, 0x8B, 0x1E, 0xE0, 0x4, 0x8B, 0x17,
+  0xBB, 0x33, 0x0, 0x3, 0xDA, 0x89, 0x1E, 0xE4, 0x4, 0x5B, 0x43,
+  0x89, 0x1E, 0x30, 0x0, 0x89, 0x1E, 0x45, 0x3, 0x5A, 0x8A, 0xC2,
+  0x24, 0xFE, 0x8A, 0xD0, 0x8A, 0xC2, 0x2A, 0xC3, 0x8A, 0xD8, 0x8A,
+  0xC6, 0x1A, 0xC7, 0x8A, 0xF8, 0x73, 0x3, 0xE9, 0x68, 0xAD, 0xB1,
+  0x3, 0xD3, 0xEB, 0x8A, 0xC7, 0x3C, 0x2, 0x72, 0x3, 0xBB, 0x0,
+  0x2, 0x8A, 0xC2, 0x2A, 0xC3, 0x8A, 0xD8, 0x8A, 0xC6, 0x1A, 0xC7,
+  0x8A, 0xF8, 0x73, 0x3, 0xE9, 0x4A, 0xAD, 0x89, 0x1E, 0xA, 0x3,
+  0x87, 0xDA, 0x89, 0x1E, 0x2C, 0x0, 0x89, 0x1E, 0x2F, 0x3, 0x8B,
+  0xE3, 0x89, 0x1E, 0x45, 0x3, 0x8B, 0x1E, 0x30, 0x0, 0x87, 0xDA,
+  0xE8, 0x3D, 0xAD, 0x2B, 0xDA, 0x4B, 0x4B, 0x53, 0x5B, 0xE8, 0x80,
+  0xE5, 0xBB, 0xDC, 0x7F, 0xE8, 0x7F, 0xFB, 0xE8, 0x98, 0xAC, 0xE9,
+  0x8F, 0xC3, 0x20, 0x42, 0x79, 0x74, 0x65, 0x73, 0x20, 0x66, 0x72,
+  0x65, 0x65, 0x0, 0x14, 0xE8, 0xA5, 0xF0, 0x33, 0xC9, 0x52, 0xFF,
+  0x36, 0x81, 0x4, 0xE9, 0x68, 0xF6, 0xFD, 0xFF, 0x3, 0xBF, 0xC9,
+  0x1B, 0xE, 0xB6, 0x0, 0x0
+};
+#endif
+
diff --git a/MCUME_pico2/pico81/AY8910.c b/MCUME_pico2/pico81/AY8910.c
new file mode 100644
index 0000000..189e358
--- /dev/null
+++ b/MCUME_pico2/pico81/AY8910.c
@@ -0,0 +1,316 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.c                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.h for declarations.                              **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2014                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "AY8910.h"
+#include "emuapi.h"
+#include <string.h>
+
+static const unsigned char Envelopes[16][32] =
+{
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+};
+
+static const int Volumes[16] =
+{ 0,1,2,4,6,8,11,16,23,32,45,64,90,128,180,255 };
+//{ 0,16,33,50,67,84,101,118,135,152,169,186,203,220,237,254 };
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int ClockHz,int First)
+{
+  static byte RegInit[16] =
+  {
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFD,
+    0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00
+  };
+  int J;
+
+  /* Reset state */
+  memcpy(D->R,RegInit,sizeof(D->R));
+  D->EPhase  = 0;
+  D->Clock   = ClockHz>>4;
+  D->First   = First;
+  D->Sync    = AY8910_ASYNC;
+  D->Changed = 0x00;
+  D->EPeriod = 0;
+  D->ECount  = 0;
+  D->Latch   = 0x00;
+
+  /* Set sound types */
+  //SetSound(0+First,SND_MELODIC);
+  //SetSound(1+First,SND_MELODIC);
+  //SetSound(2+First,SND_MELODIC);
+  //SetSound(3+First,SND_NOISE);
+  //SetSound(4+First,SND_NOISE);
+  //SetSound(5+First,SND_NOISE);
+
+  /* Silence all channels */
+  for(J=0;J<AY8910_CHANNELS;J++)
+  {
+    D->Freq[J]=D->Volume[J]=0;
+#if HAS_SND    
+    emu_sndPlaySound(J+First, 0, 0);
+#endif    
+    //Sound(J+First,0,0);
+  }
+}
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V)
+{
+  D->Latch=V&0x0F;
+}
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V)
+{
+  Write8910(D,D->Latch,V);
+}
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D)
+{
+  return(D->R[D->Latch]);
+}
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V)
+{
+  register int J,I;
+
+  switch(R)
+  {
+    case 1:
+    case 3:
+    case 5:
+      V&=0x0F;
+      /* Fall through */
+    case 0:
+    case 2:
+    case 4:
+      /* Write value */
+      D->R[R]=V;
+      /* Exit if the channel is silenced */
+      if(D->R[7]&(1<<(R>>1))) return;
+      /* Go to the first register in the pair */
+      R&=0xFE;
+      /* Compute frequency */
+      J=((int)(D->R[R+1]&0x0F)<<8)+D->R[R];
+      /* Compute channel number */
+      R>>=1;
+      /* Assign frequency */
+      D->Freq[R]=D->Clock/(J? J:0x1000);
+      /* Compute changed channels mask */
+      D->Changed|=1<<R;
+      break;
+
+    case 6:
+      /* Write value */
+      D->R[6]=V&=0x1F;
+      /* Exit if noise channels are silenced */
+      if(!(~D->R[7]&0x38)) return;
+      /* Compute and assign noise frequency */
+      /* Shouldn't do <<2, but need to keep frequency down */
+      J=D->Clock/((V&0x1F? (V&0x1F):0x20)<<2);
+      if(!(D->R[7]&0x08)) D->Freq[3]=J;
+      if(!(D->R[7]&0x10)) D->Freq[4]=J;
+      if(!(D->R[7]&0x20)) D->Freq[5]=J;
+      /* Compute changed channels mask */
+      D->Changed|=0x38&~D->R[7];
+      break;
+
+    case 7:
+      /* Find changed channels */
+      R=(V^D->R[7])&0x3F;
+      D->Changed|=R;
+      /* Write value */
+      D->R[7]=V;
+      /* Update frequencies */
+      for(J=0;R&&(J<AY8910_CHANNELS);J++,R>>=1,V>>=1)
+        if(R&1)
+        {
+          if(V&1) D->Freq[J]=0;
+          else if(J<3)
+          {
+            I=((int)(D->R[J*2+1]&0x0F)<<8)+D->R[J*2];
+            D->Freq[J]=D->Clock/(I? I:0x1000);
+          }
+          else
+          {
+            /* Shouldn't do <<2, but need to keep frequency down */
+            I=D->R[6]&0x1F;
+            D->Freq[J]=D->Clock/((I? I:0x20)<<2);
+          }
+        }
+      break;
+      
+    case 8:
+    case 9:
+    case 10:
+      /* Write value */
+      D->R[R]=V&=0x1F;
+      /* Compute channel number */
+      R-=8;
+      /* Compute and assign new volume */
+      J=Volumes[V&0x10? Envelopes[D->R[13]&0x0F][D->EPhase]:(V&0x0F)];
+      D->Volume[R]=J;
+      D->Volume[R+3]=(J+1)>>1;
+      /* Compute changed channels mask */
+      D->Changed|=(0x09<<R)&~D->R[7];
+      break;
+
+    case 11:
+    case 12:
+      /* Write value */
+      D->R[R]=V;
+      /* Compute envelope period (why not <<4?) */
+      J=((int)D->R[12]<<8)+D->R[11];
+      D->EPeriod=1000*(J? J:0x10000)/D->Clock;
+      /* No channels changed */
+      return;
+
+    case 13:
+      /* Write value */
+      D->R[R]=V&=0x0F;
+      /* Reset envelope */
+      D->ECount = 0;
+      D->EPhase = 0;
+      for(J=0;J<AY8910_CHANNELS/2;++J)
+        if(D->R[J+8]&0x10)
+        {
+          I = Volumes[Envelopes[V][0]];
+          D->Volume[J]   = I;
+          D->Volume[J+3] = (I+1)>>1;
+          D->Changed    |= (0x09<<J)&~D->R[7];
+        }
+      break;
+
+    case 14:
+    case 15:
+      /* Write value */
+      D->R[R]=V;
+      /* No channels changed */
+      return;
+
+    default:
+      /* Wrong register, do nothing */
+      return;
+  }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS)
+{
+  register int J,I;
+
+  /* Exit if no envelope running */
+  if(!D->EPeriod) return;
+
+  /* Count milliseconds */
+  D->ECount += mS;
+  if(D->ECount<D->EPeriod) return;
+
+  /* Count steps */
+  J = D->ECount/D->EPeriod;
+  D->ECount -= J*D->EPeriod;
+
+  /* Count phases */
+  D->EPhase += J;
+  if(D->EPhase>31)
+    D->EPhase = (D->R[13]&0x09)==0x08? (D->EPhase&0x1F):31;
+
+  /* Set envelope volumes for relevant channels */
+  for(I=0;I<3;++I)
+    if(D->R[I+8]&0x10)
+    {
+      J = Volumes[Envelopes[D->R[13]&0x0F][D->EPhase]];
+      D->Volume[I]   = J;
+      D->Volume[I+3] = (J+1)>>1;
+      D->Changed    |= (0x09<<I)&~D->R[7];
+    }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync)
+{
+  register int J,I;
+
+  /* Hit MIDI drums for noise channels, if requested */
+  if(Sync&AY8910_DRUMS)
+  {
+    Sync&=~AY8910_DRUMS;
+    J = (D->Freq[3]? D->Volume[3]:0)
+      + (D->Freq[4]? D->Volume[4]:0)
+      + (D->Freq[5]? D->Volume[5]:0);
+    if(J) {
+      //Drum(DRM_MIDI|28,(J+2)/3);
+    }
+  }
+
+  if(Sync!=AY8910_FLUSH) D->Sync=Sync;
+
+  for(J=0,I=D->Changed;I&&(J<AY8910_CHANNELS);J++,I>>=1)
+    if(I&1) {
+#if HAS_SND      
+      emu_sndPlaySound(J+D->First, D->Volume[J], D->Freq[J]);
+#endif      
+      //Sound(J+D->First,D->Freq[J],D->Volume[J]);
+    }
+
+  D->Changed=0x00;
+}
+
diff --git a/MCUME_pico2/pico81/AY8910.h b/MCUME_pico2/pico81/AY8910.h
new file mode 100644
index 0000000..3c8e7fb
--- /dev/null
+++ b/MCUME_pico2/pico81/AY8910.h
@@ -0,0 +1,98 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.h                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.c for the actual code.                           **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2014                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef AY8910_H
+#define AY8910_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AY8910_CHANNELS 6      /* 3 melodic + 3 noise chanls */
+
+#define AY8910_ASYNC    0      /* Asynchronous emulation     */
+#define AY8910_SYNC     1      /* Synchronous emulation      */
+#define AY8910_FLUSH    2      /* Flush buffers only         */
+#define AY8910_DRUMS    0x80   /* Hit drums for noise chnls  */
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** AY8910 ***************************************************/
+/** This data structure stores AY8910 state.                **/
+/*************************************************************/
+typedef struct
+{
+  byte R[16];                  /* PSG registers contents     */
+  int Freq[AY8910_CHANNELS];   /* Frequencies (0 for off)    */
+  int Volume[AY8910_CHANNELS]; /* Volumes (0..255)           */
+  int Clock;                   /* Base clock used by PSG     */
+  int First;                   /* First used Sound() channel */
+  byte Changed;                /* Bitmap of changed channels */
+  byte Sync;                   /* AY8910_SYNC/AY8910_ASYNC   */
+  byte Latch;                  /* Latch for the register num */
+  int EPeriod;                 /* Envelope step in msecs     */
+  int ECount;                  /* Envelope step counter      */
+  int EPhase;                  /* Envelope phase             */
+} AY8910;
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int ClockHz,int First);
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V);
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V);
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V);
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D);
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync);
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* AY8910_H */
+
diff --git a/MCUME_pico2/pico81/Z80.c b/MCUME_pico2/pico81/Z80.c
new file mode 100644
index 0000000..130a2ce
--- /dev/null
+++ b/MCUME_pico2/pico81/Z80.c
@@ -0,0 +1,462 @@
+/* Emulation of the Z80 CPU with hooks into the other parts of z81.
+ * Copyright (C) 1994 Ian Collier.
+ * z81 changes (C) 1995-2001 Russell Marks.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <string.h>	/* for memset/memcpy */
+#include "z80.h"
+
+#define parity(a) (partable[a])
+
+unsigned char partable[256]={
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      0, 4, 4, 0, 4, 0, 0, 4, 4, 0, 0, 4, 0, 4, 4, 0,
+      4, 0, 0, 4, 0, 4, 4, 0, 0, 4, 4, 0, 4, 0, 0, 4
+   };
+
+
+unsigned long tstates=0,tsmax=65000,frames=0;
+
+/* odd place to have this, but the display does work in an odd way :-) */
+unsigned char scrnbmp_new[ZX_VID_FULLWIDTH*ZX_VID_FULLHEIGHT/8]; /* written */
+
+/* checked against for diffs */
+int liney=0, lineyi=0;
+int vsy=0;
+unsigned long linestart=0;
+int vsync_toggle=0,vsync_lasttoggle=0;
+
+static int linestate=0, linex=0, nrmvideo=1;
+
+#define LINEX 	((tstates-linestart)>>2)
+
+
+
+/* for vsync off -> on */
+void vsync_raise(void)
+{
+  /* save current pos */
+  vsy=liney;
+}
+
+
+/* for vsync on -> off */
+void vsync_lower(void)
+{
+  int ny=liney,y;
+  
+  vsync_toggle++;
+  
+  /* we don't emulate this stuff by default; if nothing else,
+   * it can be fscking annoying when you're typing in a program.
+   */
+  if(!vsync_visuals)
+    return;
+  
+  /* even when we do emulate it, we don't bother with x timing,
+   * just the y. It gives reasonable results without being too
+   * complicated, I think.
+   */
+  if(vsy<0) vsy=0;
+  if(vsy>=ZX_VID_FULLHEIGHT) vsy=ZX_VID_FULLHEIGHT-1;
+  if(ny<0) ny=0;
+  if(ny>=ZX_VID_FULLHEIGHT) ny=ZX_VID_FULLHEIGHT-1;
+  
+  /* XXX both of these could/should be made into single memset calls */
+  if(ny<vsy)
+    {
+    /* must be wrapping around a frame edge; do bottom half */
+    for(y=vsy;y<ZX_VID_FULLHEIGHT;y++)
+      memset(scrnbmp_new+y*(ZX_VID_FULLWIDTH/8),0xff,ZX_VID_FULLWIDTH/8);
+    vsy=0;
+    }
+  
+  for(y=vsy;y<ny;y++)
+    memset(scrnbmp_new+y*(ZX_VID_FULLWIDTH/8),0xff,ZX_VID_FULLWIDTH/8);
+}
+
+
+unsigned char a, f, b, c, d, e, h, l;
+unsigned char r, a1, f1, b1, c1, d1, e1, h1, l1, i, iff1, iff2, im;
+unsigned short pc;
+unsigned short ix, iy, sp;
+unsigned long nextlinetime=0,linegap=208,lastvsyncpend=0;
+unsigned char radjust;
+unsigned char ixoriy, new_ixoriy;
+unsigned char intsample=0;
+unsigned char op;
+int ulacharline=0;
+int nmipend=0,intpend=0,vsyncpend=0,vsynclen=0;
+int hsyncskip=0;
+int framewait=0;
+
+
+
+
+
+void ExecZ80(void)
+{
+  int retval=0;
+  while(1)
+  {
+    /* this *has* to be checked before radjust is incr'd */
+    if(intsample && !(radjust&64))
+      intpend=1;
+  
+    ixoriy=new_ixoriy;
+    new_ixoriy=0;
+    intsample=1;
+    op=fetch(pc&0x7fff);
+  
+    if (pc&0x8000 && !(op&64) && linestate==0) {
+      nrmvideo = i<0x20 || radjust==0xdf;
+      linestate = 1;
+      linex = 5;
+      if (liney<ZX_VID_MARGIN) liney=ZX_VID_MARGIN;
+    } else if (linestate>=1) {
+      if (op&64) {
+        linestate = 0;
+        linex = ZX_VID_FULLWIDTH/8;
+        if (ramsize>=4 && !zx80) {
+          liney++;
+          lineyi=1;
+        }
+      } else {
+        linestate++;
+        linex++;
+      }
+    }
+  
+    if (!nrmvideo) ulacharline = 0;
+  
+    if((pc&0x8000) && !(op&64))
+    {
+      int x,y,v;
+      
+      /* do the ULA's char-generating stuff */
+      x=linex;
+      y=liney;
+      /*    printf("ULA %3d,%3d = %02X\n",x,y,op);*/
+      if(y>=0 && y<ZX_VID_FULLHEIGHT && x>=0 && x<ZX_VID_FULLWIDTH/8)
+      {
+        /* XXX I think this is what's needed for the `true hi-res'
+         * stuff from the ULA's side, but the timing is messed up
+         * at the moment so not worth it currently.
+         */
+        if (nrmvideo)
+          v=mem[((i&0xfe)<<8)|((op&63)<<3)|ulacharline];
+        else
+          v=mem[(i<<8)|(r&0x80)|(radjust&0x7f)];
+        //if(taguladisp) v^=128;
+        scrnbmp_new[y*(ZX_VID_FULLWIDTH/8)+x]=((op&128)?~v:v);
+      }
+  
+      op=0;  /* the CPU sees a nop */
+    }
+  
+    pc++;
+    radjust++;
+  
+    switch(op)
+    {
+#include "z80ops.h"
+    }
+  
+    if(tstates>=tsmax)
+    {
+      retval=1;   
+      tstates-=tsmax;
+      linestart-=tsmax;
+      nextlinetime-=tsmax;
+      lastvsyncpend-=tsmax;
+      vsync_lasttoggle=vsync_toggle;
+      vsync_toggle=0;
+    
+      frames++;
+      frame_pause();
+    }
+
+    /* the vsync length test is pretty arbitrary, because
+     * the timing isn't very accurate (more or less an instruction
+     * count) - but it's good enough in practice.
+     *
+     * the vsync_toggle test is fairly arbitrary too;
+     * there has to have been `not too many' for a TV to get
+     * confused. In practice, more than one would screw it up,
+     * but since we could be looking at over a frames' worth
+     * given where vsync_toggle is zeroed, we play it safe.
+     * also, we use a copy of the previous chunk's worth,
+     * since we need a full frame(-plus) to decide this.
+     */
+    if(vsynclen && !vsync)
+    {
+      if(vsynclen>=10)
+      {
+        if(vsync_lasttoggle<=2)
+        {
+          vsyncpend=1;	/* start of frame */
+          /* FAST mode screws up without this, but it's a bit
+           * unpleasant... :-/
+           */
+          tstates=nextlinetime;
+        }
+      }
+      else
+      {
+        /* independent timing for this would be awkward, so
+         * anywhere on the line is good enough. Also,
+         * don't count it as a toggle.
+         */
+        vsync_toggle--;
+        hsyncskip=1;
+      }
+    }
+
+    /* should do this all the time vsync is set */
+    if(vsync)
+    {
+      ulacharline=0;
+      vsynclen++;
+    }
+    else {
+      vsynclen=0;    
+    }
+  
+    if(tstates>=nextlinetime)	/* new line */
+    {
+      /* generate fake sync if we haven't had one for a while;
+       * but if we just loaded/saved, wait for the first real frame instead
+       * to avoid jumpiness.
+       */
+      if(!vsync && tstates-lastvsyncpend>=tsmax && !framewait)
+        vsyncpend=1;
+  
+      /* but that won't ever happen if we always have vsync on -
+       * i.e., if we're grinding away in FAST mode. So for that
+       * case, we check for vsync being held for a full frame.
+       */
+      if(vsync_visuals && vsynclen>=tsmax)
+      {
+        vsyncpend=1;
+        vsynclen=1;      
+        goto postcopy;				/* skip the usual copying */
+      }
+  
+      if(!vsyncpend)
+      {
+        if (!lineyi) liney++;
+        
+        if(hsyncgen && !hsyncskip)
+        {
+          ulacharline++;
+          ulacharline&=7;
+        }
+      }
+      else
+      {
+        bitbufBlit(scrnbmp_new);
+        postcopy:
+        memset(scrnbmp_new,0,sizeof(scrnbmp_new));
+        lastvsyncpend=tstates;
+        vsyncpend=0;
+        framewait=0;
+        liney=-1;		/* XXX might be something up here */
+      }
+      
+      if(nmigen)
+        nmipend=1;
+  
+      hsyncskip=0;
+      linestart=nextlinetime;
+      nextlinetime+=linegap;
+    }
+  
+    if(intsample && nmipend)
+    {
+      nmipend=0;
+  
+      if(nmigen)
+      {
+        iff2=iff1;
+        iff1=0;
+        /* hardware syncs tstates to falling of NMI pulse (?),
+         * so a slight kludge here...
+         */
+        if(fetch(pc&0x7fff)==0x76)
+        {
+          pc++;
+          tstates=linestart;
+        }
+        else
+        {
+          /* this seems curiously long, but equally, seems
+           * to be just about right. :-)
+           */
+          tstates+=27;
+        }
+        push2(pc);
+        pc=0x66;
+      }
+    }
+
+    if(intsample && intpend)
+    {
+      intpend=0;
+      if(iff1)
+      {
+        if(fetch(pc&0x7fff)==0x76)pc++;
+        iff1=iff2=0;
+        tstates+=5; /* accompanied by an input from the data bus */
+        switch(im)
+        {
+          case 0: /* IM 0 */
+          case 1: /* undocumented */
+          case 2: /* IM 1 */
+            /* there is little to distinguish between these cases */
+            tstates+=9; /* perhaps */
+            push2(pc);
+            pc=0x38;
+            break;
+          case 3: /* IM 2 */
+            /* (seems unlikely it'd ever be used on the '81, but...) */
+            tstates+=13; /* perhaps */
+            {
+              int addr=fetch2((i<<8)|0xff);
+              push2(pc);
+              pc=addr;
+            }
+        }
+      }
+    }
+
+    /* this isn't used for any sort of Z80 interrupts,
+     * purely for the emulator's UI.
+     */
+    if(interrupted)
+    {
+      if(interrupted==1)
+      {
+        do_interrupt();	/* also zeroes it */
+      }
+      else	/* must be 2 */
+      {
+        /* a kludge to let us do a reset */
+        interrupted=0;
+        a=f=b=c=d=e=h=l=a1=f1=b1=c1=d1=e1=h1=l1=i=iff1=iff2=im=r=0;
+        ixoriy=new_ixoriy=0;
+        ix=iy=sp=pc=0;
+        tstates=radjust=0;
+        nextlinetime=linegap;
+        vsyncpend=vsynclen=0;
+        hsyncskip=0;
+      }
+    }
+    
+    if (retval) break;  
+  }
+
+}
+
+void ResetZ80(void)
+{
+  a=f=b=c=d=e=h=l=a1=f1=b1=c1=d1=e1=h1=l1=i=iff1=iff2=im=r=0;
+  ixoriy=new_ixoriy=0;
+  ix=iy=sp=pc=0;
+  tstates=radjust=0;
+  nextlinetime=linegap; 
+  tstates=0;
+  frames=0;
+  liney=0;
+  vsy=0;
+  linestart=0;
+  vsync_toggle=0;
+  vsync_lasttoggle=0;
+
+   /* we load a snapshot, in effect.This does the registers.
+     */
+  if(autoload)
+  {
+    if (zx80) {
+      /* Registers (common values) */
+      a = 0x00; f = 0x44; b = 0x00; c = 0x00;
+      d = 0x07; e = 0xae; h = 0x40; l = 0x2a;
+      pc = 0x0283;
+      ix = 0x0000; iy = 0x4000; i = 0x0e; r = 0xdd;
+      a1 = 0x00; f1 = 0x00; b1 = 0x00; c1 = 0x21;
+      d1 = 0xd8; e1 = 0xf0; h1 = 0xd8; l1 = 0xf0;
+      iff1 = 0x00; iff2 = 0x00; im = 0x02;
+      radjust = 0x6a;
+      /* Machine Stack (common values) */
+      if (ramsize >= 16) {
+        sp = 0x8000 - 4;
+      } else {
+        sp = 0x4000 - 4 + ramsize * 1024;
+      }
+      mem[sp + 0] = 0x47;
+      mem[sp + 1] = 0x04;
+      mem[sp + 2] = 0xba;
+      mem[sp + 3] = 0x3f;
+      /* Now override if RAM configuration changes things
+       * (there's a possibility these changes are unimportant) */
+      if (ramsize == 16) {
+        mem[sp + 2] = 0x22;
+      }
+    } else {
+      static unsigned char bit1[9]={0xFF,0x80,0xFC,0x7F,0x00,0x80,0x00,0xFE,0xFF};
+      static unsigned char bit2[4]={0x76,0x06,0x00,0x3e};
+    
+      /* memory will already be zeroed at this point */
+      
+      memcpy(mem+0x4000,bit1,9);
+      memcpy(mem+0x7ffc,bit2,4);
+  
+      a=0x0B; f=0x85; b=0x00; c=0xFF;
+      d=0x43; e=0x99; h=0xC3; l=0x99;
+      a1=0xE2; f1=0xA1; b1=0x81; c1=0x02;
+      d1=0x00; e1=0x2B; h1=0x00; l1=0x00;
+      i=0x1E; iff1=iff2=0;
+      im=2;
+      r=0xDD; radjust=0xCA;
+      ix=0x281; iy=0x4000;
+      sp=0x7FFC;
+      pc=0x207;      
+    }
+    
+
+    /* finally, load. It'll reset (via reset81) if it fails. */
+    load_p(32768);
+
+    /* wait for a real frame, to avoid an annoying frame `jump'. */
+    framewait=1;
+  }
+}
+
+
diff --git a/MCUME_pico2/pico81/Z80.h b/MCUME_pico2/pico81/Z80.h
new file mode 100644
index 0000000..5a20dd8
--- /dev/null
+++ b/MCUME_pico2/pico81/Z80.h
@@ -0,0 +1,79 @@
+/* z81/xz81, Linux console and X ZX81/ZX80 emulators.
+ * Copyright (C) 1994 Ian Collier. z81 changes (C) 1995-2001 Russell Marks.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "common.h"
+
+#define Z80_quit  1
+#define Z80_NMI   2
+#define Z80_reset 3
+#define Z80_load  4
+#define Z80_save  5
+#define Z80_log   6
+
+extern int interrupted;
+extern unsigned long tstates,tsmax,frames;
+
+extern void setzx80mode(void);
+extern void vsync_raise(void);
+extern void vsync_lower(void);
+extern void ResetZ80(void);
+extern void ExecZ80(void);
+
+#define fetch(x) (memptr[(unsigned short)(x)>>10][(x)&1023])
+#define fetch2(x) ((fetch((x)+1)<<8)|fetch(x))
+
+
+#define store(x,y) do {\
+          unsigned short off=(x)&1023;\
+          unsigned char page=(unsigned short)(x)>>10;\
+          int attr=memattr[page];\
+          if(attr){\
+             memptr[page][off]=(y);\
+             }\
+           } while(0)
+
+#define store2b(x,hi,lo) do {\
+          unsigned short off=(x)&1023;\
+          unsigned char page=(unsigned short)(x)>>10;\
+          int attr=memattr[page];\
+          if(attr) { \
+             memptr[page][off]=(lo);\
+             memptr[page][off+1]=(hi);\
+             }\
+          } while(0)
+
+#define store2(x,y) store2b(x,(y)>>8,(y)&255)
+
+#ifdef __GNUC__
+static void inline storefunc(unsigned short ad,unsigned char b){
+   store(ad,b);
+}
+#undef store
+#define store(x,y) storefunc(x,y)
+
+static void inline store2func(unsigned short ad,unsigned char b1,unsigned char b2){
+   store2b(ad,b1,b2);
+}
+#undef store2b
+#define store2b(x,hi,lo) store2func(x,hi,lo)
+#endif
+
+#define bc ((b<<8)|c)
+#define de ((d<<8)|e)
+#define hl ((h<<8)|l)
+
diff --git a/MCUME_pico2/pico81/cbops.h b/MCUME_pico2/pico81/cbops.h
new file mode 100644
index 0000000..b5148ba
--- /dev/null
+++ b/MCUME_pico2/pico81/cbops.h
@@ -0,0 +1,177 @@
+/* Emulations of the CB operations of the Z80 instruction set.
+ * Copyright (C) 1994 Ian Collier.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define var_t   unsigned char t
+#define rlc(x)  (x=(x<<1)|(x>>7),rflags(x,x&1))
+#define rrc(x)  do{var_t=x&1;x=(x>>1)|(t<<7);rflags(x,t);}while(0)
+#define rl(x)   do{var_t=x>>7;x=(x<<1)|(f&1);rflags(x,t);}while(0)
+#define rr(x)   do{var_t=x&1;x=(x>>1)|(f<<7);rflags(x,t);}while(0)
+#define sla(x)  do{var_t=x>>7;x<<=1;rflags(x,t);}while(0)
+#define sra(x)  do{var_t=x&1;x=((signed char)x)>>1;rflags(x,t);}while(0)
+#define sll(x)  do{var_t=x>>7;x=(x<<1)|1;rflags(x,t);}while(0)
+#define srl(x)  do{var_t=x&1;x>>=1;rflags(x,t);}while(0)
+
+#define rflags(x,c) (f=(c)|(x&0xa8)|((!x)<<6)|parity(x))
+
+#define bit(n,x) (f=(f&1)|((x&(1<<n))?0x10:0x54)|(x&0x28))
+#define set(n,x) (x|=(1<<n))
+#define res(n,x) (x&=~(1<<n))
+
+{
+   /* reg/val are initialised to stop gcc's (incorrect) warning,
+    * and static to save initialising them every time.
+    */
+   static unsigned char reg=0,val=0;
+   unsigned short addr;
+   unsigned char op;
+   if(ixoriy){
+      addr=(ixoriy==1?ix:iy)+(signed char)fetch(pc);
+      pc++;
+      tstates+=8;
+      op=fetch(pc);
+      reg=op&7;
+      op=(op&0xf8)|6;
+   }
+   else{
+      op=fetch(pc);
+      tstates+=4;
+      radjust++;
+      addr=hl;
+   }
+   pc++;
+
+   if(op<64)switch(op){
+   case  0: rlc(b); break;
+   case  1: rlc(c); break;
+   case  2: rlc(d); break;
+   case  3: rlc(e); break;
+   case  4: rlc(h); break;
+   case  5: rlc(l); break;
+   case  6: tstates+=7;val=fetch(addr);rlc(val);store(addr,val);break;
+   case  7: rlc(a); break;
+   case  8: rrc(b); break;
+   case  9: rrc(c); break;
+   case 10: rrc(d); break;
+   case 11: rrc(e); break;
+   case 12: rrc(h); break;
+   case 13: rrc(l); break;
+   case 14: tstates+=7;val=fetch(addr);rrc(val);store(addr,val);break;
+   case 15: rrc(a); break;
+   case 0x10: rl(b); break;
+   case 0x11: rl(c); break;
+   case 0x12: rl(d); break;
+   case 0x13: rl(e); break;
+   case 0x14: rl(h); break;
+   case 0x15: rl(l); break;
+   case 0x16: tstates+=7;val=fetch(addr);rl(val);store(addr,val);break;
+   case 0x17: rl(a); break;
+   case 0x18: rr(b); break;
+   case 0x19: rr(c); break;
+   case 0x1a: rr(d); break;
+   case 0x1b: rr(e); break;
+   case 0x1c: rr(h); break;
+   case 0x1d: rr(l); break;
+   case 0x1e: tstates+=7;val=fetch(addr);rr(val);store(addr,val);break;
+   case 0x1f: rr(a); break;
+   case 0x20: sla(b); break;
+   case 0x21: sla(c); break;
+   case 0x22: sla(d); break;
+   case 0x23: sla(e); break;
+   case 0x24: sla(h); break;
+   case 0x25: sla(l); break;
+   case 0x26: tstates+=7;val=fetch(addr);sla(val);store(addr,val);break;
+   case 0x27: sla(a); break;
+   case 0x28: sra(b); break;
+   case 0x29: sra(c); break;
+   case 0x2a: sra(d); break;
+   case 0x2b: sra(e); break;
+   case 0x2c: sra(h); break;
+   case 0x2d: sra(l); break;
+   case 0x2e: tstates+=7;val=fetch(addr);sra(val);store(addr,val);break;
+   case 0x2f: sra(a); break;
+   case 0x30: sll(b); break;
+   case 0x31: sll(c); break;
+   case 0x32: sll(d); break;
+   case 0x33: sll(e); break;
+   case 0x34: sll(h); break;
+   case 0x35: sll(l); break;
+   case 0x36: tstates+=7;val=fetch(addr);sll(val);store(addr,val);break;
+   case 0x37: sll(a); break;
+   case 0x38: srl(b); break;
+   case 0x39: srl(c); break;
+   case 0x3a: srl(d); break;
+   case 0x3b: srl(e); break;
+   case 0x3c: srl(h); break;
+   case 0x3d: srl(l); break;
+   case 0x3e: tstates+=7;val=fetch(addr);srl(val);store(addr,val);break;
+   case 0x3f: srl(a); break;
+   }
+   else{
+      unsigned char n=(op>>3)&7;
+      switch(op&0xc7){
+      case 0x40: bit(n,b); break;
+      case 0x41: bit(n,c); break;
+      case 0x42: bit(n,d); break;
+      case 0x43: bit(n,e); break;
+      case 0x44: bit(n,h); break;
+      case 0x45: bit(n,l); break;
+      case 0x46: tstates+=4;val=fetch(addr);bit(n,val);store(addr,val);break;
+      case 0x47: bit(n,a); break;
+      case 0x80: res(n,b); break;
+      case 0x81: res(n,c); break;
+      case 0x82: res(n,d); break;
+      case 0x83: res(n,e); break;
+      case 0x84: res(n,h); break;
+      case 0x85: res(n,l); break;
+      case 0x86: tstates+=4;val=fetch(addr);res(n,val);store(addr,val);break;
+      case 0x87: res(n,a); break;
+      case 0xc0: set(n,b); break;
+      case 0xc1: set(n,c); break;
+      case 0xc2: set(n,d); break;
+      case 0xc3: set(n,e); break;
+      case 0xc4: set(n,h); break;
+      case 0xc5: set(n,l); break;
+      case 0xc6: tstates+=4;val=fetch(addr);set(n,val);store(addr,val);break;
+      case 0xc7: set(n,a); break;
+      }
+   }
+   if(ixoriy)switch(reg){
+      case 0:b=val; break;
+      case 1:c=val; break;
+      case 2:d=val; break;
+      case 3:e=val; break;
+      case 4:h=val; break;
+      case 5:l=val; break;
+      case 7:a=val; break;
+   }
+}
+
+#undef var_t
+#undef rlc
+#undef rrc
+#undef rl
+#undef rr
+#undef sla
+#undef sra
+#undef sll
+#undef srl
+#undef rflags
+#undef bit
+#undef set
+#undef res
+
diff --git a/MCUME_pico2/pico81/common.h b/MCUME_pico2/pico81/common.h
new file mode 100644
index 0000000..1fd420d
--- /dev/null
+++ b/MCUME_pico2/pico81/common.h
@@ -0,0 +1,46 @@
+
+typedef unsigned char  byte;
+//typedef unsigned short  word;
+
+#define WIDTH  320
+#define HEIGHT 192
+#define BORDER 32
+
+#define CYCLES_PER_FRAME 65000//3500000/50
+
+
+/* full internal image with overscan (but not hsync/vsync areas) */
+#define ZX_VID_MARGIN		55
+#define ZX_VID_HMARGIN		(8*8)
+#define ZX_VID_FULLWIDTH	(2*ZX_VID_HMARGIN+32*8)	/* sic */
+#define ZX_VID_FULLHEIGHT	(2*ZX_VID_MARGIN+192)
+
+
+/* AY board types */
+#define AY_TYPE_NONE		0
+#define AY_TYPE_QUICKSILVA	1
+#define AY_TYPE_ZONX		2
+
+
+extern unsigned char * mem;
+extern unsigned char *memptr[64];
+extern int memattr[64];
+extern unsigned long tstates,tsmax;
+extern int vsync_visuals;
+extern int ramsize;
+extern int interrupted;
+extern int nmigen,hsyncgen,vsync;
+extern int autoload;
+extern int zx80;
+
+extern void sighandler(int a);
+extern unsigned int in(int h,int l);
+extern unsigned int out(int h,int l,int a);
+extern void do_interrupt();
+extern void save_p(int a);
+extern void load_p(int a);
+extern void do_interrupt();
+extern void reset81();
+extern void frame_pause(void);
+extern void bitbufBlit(unsigned char * buf);
+
diff --git a/MCUME_pico2/pico81/edops.h b/MCUME_pico2/pico81/edops.h
new file mode 100644
index 0000000..c68237e
--- /dev/null
+++ b/MCUME_pico2/pico81/edops.h
@@ -0,0 +1,545 @@
+/* Emulations of the ED operations of the Z80 instruction set.
+ * Copyright (C) 1994 Ian Collier.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define input(var) {  unsigned short u;\
+                      var=u=in(b,c);\
+                      tstates+=u>>8;\
+                      f=(f&1)|(var&0xa8)|((!var)<<6)|parity(var);\
+                   }
+#define sbchl(x) {    unsigned short z=(x);\
+                      unsigned long t=(hl-z-cy)&0x1ffff;\
+                      f=((t>>8)&0xa8)|(t>>16)|2|\
+                        (((hl&0xfff)<(z&0xfff)+cy)<<4)|\
+                        (((hl^z)&(hl^t)&0x8000)>>13)|\
+                        ((!(t&0xffff))<<6)|2;\
+                      l=t;\
+                      h=t>>8;\
+                   }
+
+#define adchl(x) {    unsigned short z=(x);\
+                      unsigned long t=hl+z+cy;\
+                      f=((t>>8)&0xa8)|(t>>16)|\
+                        (((hl&0xfff)+(z&0xfff)+cy>0xfff)<<4)|\
+                        (((~hl^z)&(hl^t)&0x8000)>>13)|\
+                        ((!(t&0xffff))<<6)|2;\
+                      l=t;\
+                      h=t>>8;\
+                 }
+
+#define neg (a=-a,\
+            f=(a&0xa8)|((!a)<<6)|(((a&15)>0)<<4)|((a==128)<<2)|2|(a>0))
+
+{
+   unsigned char op=fetch(pc&0x7fff);
+   pc++;
+   radjust++;
+   switch(op){
+instr(0x40,8);
+   input(b);
+endinstr;
+
+instr(0x41,8);
+   tstates+=out(b,c,b);
+endinstr;
+
+instr(0x42,11);
+   sbchl(bc);
+endinstr;
+
+instr(0x43,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    store2b(addr,b,c);
+   }
+endinstr;
+
+instr(0x44,4);
+   neg;
+endinstr;
+
+instr(0x45,4);
+   iff1=iff2;
+   ret;
+endinstr;
+
+instr(0x46,4);
+   im=0;
+endinstr;
+
+instr(0x47,5);
+   i=a;
+endinstr;
+
+instr(0x48,8);
+   input(c);
+endinstr;
+
+instr(0x49,8);
+   tstates+=out(b,c,c);
+endinstr;
+
+instr(0x4a,11);
+   adchl(bc);
+endinstr;
+
+instr(0x4b,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    c=fetch(addr);
+    b=fetch(addr+1);
+   }
+endinstr;
+
+instr(0x4c,4);
+   neg;
+endinstr;
+
+instr(0x4d,4);
+   ret;
+endinstr;
+
+instr(0x4e,4);
+   im=1;
+endinstr;
+
+instr(0x4f,5);
+   r=a;
+   radjust=r;
+endinstr;
+
+instr(0x50,8);
+   input(d);
+endinstr;
+
+instr(0x51,8);
+   tstates+=out(b,c,d);
+endinstr;
+
+instr(0x52,11);
+   sbchl(de);
+endinstr;
+
+instr(0x53,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    store2b(addr,d,e);
+   }
+endinstr;
+
+instr(0x54,4);
+   neg;
+endinstr;
+
+instr(0x55,4);
+   ret;
+endinstr;
+
+instr(0x56,4);
+   im=2;
+endinstr;
+
+instr(0x57,5);
+   a=i;
+   f=(f&1)|(a&0xa8)|((!a)<<6)|(iff2<<2);
+endinstr;
+
+instr(0x58,8);
+   input(e);
+endinstr;
+
+instr(0x59,8);
+   tstates+=out(b,c,e);
+endinstr;
+
+instr(0x5a,11);
+   adchl(de);
+endinstr;
+
+instr(0x5b,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    e=fetch(addr);
+    d=fetch(addr+1);
+   }
+endinstr;
+
+instr(0x5c,4);
+   neg;
+endinstr;
+
+instr(0x5d,4);
+   ret;
+endinstr;
+
+instr(0x5e,4);
+   im=3;
+endinstr;
+
+instr(0x5f,5);
+   r=(r&0x80)|(radjust&0x7f);
+   a=r;
+   f=(f&1)|(a&0xa8)|((!a)<<6)|(iff2<<2);
+endinstr;
+
+instr(0x60,8);
+   input(h);
+endinstr;
+
+instr(0x61,8);
+   tstates+=out(b,c,h);
+endinstr;
+
+instr(0x62,11);
+   sbchl(hl);
+endinstr;
+
+instr(0x63,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    store2b(addr,h,l);
+   }
+endinstr;
+
+instr(0x64,4);
+   neg;
+endinstr;
+
+instr(0x65,4);
+   ret;
+endinstr;
+
+instr(0x66,4);
+   im=0;
+endinstr;
+
+instr(0x67,14);
+   {unsigned char t=fetch(hl);
+    unsigned char u=(a<<4)|(t>>4);
+    a=(a&0xf0)|(t&0x0f);
+    store(hl,u);
+    f=(f&1)|(a&0xa8)|((!a)<<6)|parity(a);
+   }
+endinstr;
+
+instr(0x68,8);
+   input(l);
+endinstr;
+
+instr(0x69,8);
+   tstates+=out(b,c,l);
+endinstr;
+
+instr(0x6a,11);
+   adchl(hl);
+endinstr;
+
+instr(0x6b,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    l=fetch(addr);
+    h=fetch(addr+1);
+   }
+endinstr;
+
+instr(0x6c,4);
+   neg;
+endinstr;
+
+instr(0x6d,4);
+   ret;
+endinstr;
+
+instr(0x6e,4);
+   im=1;
+endinstr;
+
+instr(0x6f,5);
+   {unsigned char t=fetch(hl);
+    unsigned char u=(a&0x0f)|(t<<4);
+    a=(a&0xf0)|(t>>4);
+    store(hl,u);
+    f=(f&1)|(a&0xa8)|((!a)<<6)|parity(a);
+   }
+endinstr;
+
+instr(0x70,8);
+   {unsigned char x;input(x);}
+endinstr;
+
+instr(0x71,8);
+   tstates+=out(b,c,0);
+endinstr;
+
+instr(0x72,11);
+   sbchl(sp);
+endinstr;
+
+instr(0x73,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    store2(addr,sp);
+   }
+endinstr;
+
+instr(0x74,4);
+   neg;
+endinstr;
+
+instr(0x75,4);
+   ret;
+endinstr;
+
+instr(0x76,4);
+   im=2;
+endinstr;
+
+instr(0x78,8);
+   input(a);
+endinstr;
+
+instr(0x79,8);
+   tstates+=out(b,c,a);
+endinstr;
+
+instr(0x7a,11);
+   adchl(sp);
+endinstr;
+
+instr(0x7b,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    sp=fetch2(addr);
+   }
+endinstr;
+
+instr(0x7c,4);
+   neg;
+endinstr;
+
+instr(0x7d,4);
+   ret;
+endinstr;
+
+instr(0x7e,4);
+   im=3;
+endinstr;
+
+instr(0xa0,12);
+   {unsigned char x=fetch(hl);
+    store(de,x);
+    if(!++l)h++;
+    if(!++e)d++;
+    if(!c--)b--;
+    f=(f&0xc1)|(x&0x28)|(((b|c)>0)<<2);
+   }
+endinstr;
+
+instr(0xa1,12);
+   {unsigned char carry=cy;
+    cpa(fetch(hl));
+    if(!++l)h++;
+    if(!c--)b--;
+    f=(f&0xfa)|carry|(((b|c)>0)<<2);
+   }
+endinstr;
+
+instr(0xa2,12);
+   {unsigned short t=in(b,c);
+    store(hl,t);
+    tstates+=t>>8;
+    if(!++l)h++;
+    b--;
+    f=(b&0xa8)|((b>0)<<6)|2|((parity(b)^c)&4);
+   }
+endinstr;
+
+instr(0xa3,12); /* I can't determine the correct flags outcome for the
+                   block OUT instructions.  Spec says that the carry
+                   flag is left unchanged and N is set to 1, but that
+                   doesn't seem to be the case... */
+   {unsigned char x=fetch(hl);
+    tstates+=out(b,c,x);
+    if(!++l)h++;
+    b--;
+    f=(f&1)|0x12|(b&0xa8)|((b==0)<<6);
+   }
+endinstr;
+
+instr(0xa8,12);
+   {unsigned char x=fetch(hl);
+    store(de,x);
+    if(!l--)h--;
+    if(!e--)d--;
+    if(!c--)b--;
+    f=(f&0xc1)|(x&0x28)|(((b|c)>0)<<2);
+   }
+endinstr;
+
+instr(0xa9,12);
+   {unsigned char carry=cy;
+    cpa(fetch(hl));
+    if(!l--)h--;
+    if(!c--)b--;
+    f=(f&0xfa)|carry|(((b|c)>0)<<2);
+   }
+endinstr;
+
+instr(0xaa,12);
+   {unsigned short t=in(b,c);
+    store(hl,t);
+    tstates+=t>>8;
+    if(!l--)h--;
+    b--;
+    f=(b&0xa8)|((b>0)<<6)|2|((parity(b)^c^4)&4);
+   }
+endinstr;
+
+instr(0xab,12);
+   {unsigned char x=fetch(hl);
+    tstates+=out(b,c,x);
+    if(!l--)h--;
+    b--;
+    f=(f&1)|0x12|(b&0xa8)|((b==0)<<6);
+   }
+endinstr;
+
+/* Note: the Z80 implements "*R" as "*" followed by JR -2.  No reason
+   to change this... */
+
+instr(0xb0,12);
+   {unsigned char x=fetch(hl);
+    store(de,x);
+    if(!++l)h++;
+    if(!++e)d++;
+    if(!c--)b--;
+    f=(f&0xc1)|(x&0x28)|(((b|c)>0)<<2);
+    if(b|c)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xb1,12);
+   {unsigned char carry=cy;
+    cpa(fetch(hl));
+    if(!++l)h++;
+    if(!c--)b--;
+    f=(f&0xfa)|carry|(((b|c)>0)<<2);
+    if((f&0x44)==4)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xb2,12);
+   {unsigned short t=in(b,c);
+    store(hl,t);
+    tstates+=t>>8;
+    if(!++l)h++;
+    b--;
+    f=(b&0xa8)|((b>0)<<6)|2|((parity(b)^c)&4);
+    if(b)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xb3,12);
+   {unsigned char x=fetch(hl);
+    tstates+=out(b,c,x);
+    if(!++l)h++;
+    b--;
+    f=(f&1)|0x12|(b&0xa8)|((b==0)<<6);
+    if(b)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xb8,12);
+   {unsigned char x=fetch(hl);
+    store(de,x);
+    if(!l--)h--;
+    if(!e--)d--;
+    if(!c--)b--;
+    f=(f&0xc1)|(x&0x28)|(((b|c)>0)<<2);
+    if(b|c)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xb9,12);
+   {unsigned char carry=cy;
+    cpa(fetch(hl));
+    if(!l--)h--;
+    if(!c--)b--;
+    f=(f&0xfa)|carry|(((b|c)>0)<<2);
+    if((f&0x44)==4)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xba,12);
+   {unsigned short t=in(b,c);
+    store(hl,t);
+    tstates+=t>>8;
+    if(!l--)h--;
+    b--;
+    f=(b&0xa8)|((b>0)<<6)|2|((parity(b)^c^4)&4);
+    if(b)pc-=2,tstates+=5;
+   }
+endinstr;
+
+instr(0xbb,12);
+   {unsigned char x=fetch(hl);
+    tstates+=out(b,c,x);
+    if(!l--)h--;
+    b--;
+    f=(f&1)|0x12|(b&0xa8)|((b==0)<<6);
+    if(b)pc-=2,tstates+=5;
+   }
+endinstr;
+
+/* save/load patches */
+
+instr(0xfc,4);
+#ifdef SZ81	/* Added by Thunor */
+  if(!zx80 && hl < 0x8000)
+    {
+    sdl_load_file(hl,LOAD_FILE_METHOD_NAMEDLOAD);
+    }
+  else /* if((!zx80 && hl >= 0x8000) || zx80) */
+    {
+    sdl_load_file(hl,LOAD_FILE_METHOD_SELECTLOAD);
+    }
+#else
+  load_p(hl);
+#endif
+  framewait=1;
+endinstr;
+
+instr(0xfd,4);
+#ifdef SZ81	/* Added by Thunor */
+  if(zx80)
+    {
+    sdl_save_file(hl,SAVE_FILE_METHOD_UNNAMEDSAVE);
+    }
+  else
+    {
+    sdl_save_file(hl,SAVE_FILE_METHOD_NAMEDSAVE);
+    }
+#else
+  save_p(hl);
+#endif
+  framewait=1;
+endinstr;
+
+default: tstates+=4;
+
+}}
+
diff --git a/MCUME_pico2/pico81/emucfg.h b/MCUME_pico2/pico81/emucfg.h
new file mode 100644
index 0000000..937c40b
--- /dev/null
+++ b/MCUME_pico2/pico81/emucfg.h
@@ -0,0 +1,112 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         2
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    ZX81/ZX80 Emulator"
+#define ROMSDIR "z81"
+
+#define emu_Init(ROM) {z81_Start(ROM); z81_Init(); }
+#define emu_Step(x) {z81_Step();}
+#define emu_Input(x) {z81_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  30,31,32,33,34,35,36,37,38,39,
+  20,26, 8,21,23,28,24,12,18,19,
+   4,22, 7, 9,10,11,13,14,15,40,
+   0,29,27, 6,25, 5,17,16, 0,44,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,0,24+64,34+64,35+64,36+64,37+64,18+64,0,
+  21+64,23+64,28+64,17+64,16+64,31+64,26+64,0,0,19+64,
+  0,0,0,12+64,18+64,0,13+64,14+64,15+64,40+64,
+  0,29+64,27+64, 6+64,25+64, 5+64,1+64,1,0,44+64,
+  0,0,0,0,0,0
+  }; 
+  // To be mapped
+  //30+64,0,32+64,33+64,0,0,0,0,38+64,39+64,
+  //20+64,0, 8+64,0,0,0,0,0,0,0,
+  //4+64,22+64, 7+64, 9+64,10+64,11+64,0,0,0,0,
+  //0,    0,0, 0,0, 0,0,0, 0,0,
+  //0,0,0,0,0,0
+  //};  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else
+/*
+    {25, 6,27,29,224},// vcxz<caps shift=Lshift>
+    {10, 9, 7,22, 4}, // gfdsa
+    {23,21, 8,26,20}, // trewq
+    {34,33,32,31,30}, // 54321
+    {35,36,37,38,39}, // 67890
+    {28,24,12,18,19}, // yuiop
+    {11,13,14,15,40}, // hjkl<enter>
+    { 5,17,16,1,44},  // bnm. <space>
+*/
+
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  20,26,8,21,23,28,24,12,18,19,39+64,
+  0, 4, 22, 7,9, 10,11,13,14,15,40,
+  0,29,27,6,25,5,17,16,1,44, 
+  0,0,0,0   //up,left,right,down
+  };  
+
+#define keylables_map2_0 (char *)"1234567890="
+#define keylables_map2_1 (char *)"    $ + *- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  30,31,32,33,34,35,36,37,38,39,15+64,
+  0, 0,0,0,24+64,0,14+64,0,5+64,13+64,0,
+  0, 12+64,18+64,6+64,25+64,19+64,17+64,16+64,1+64,29+64,
+  36+64,34+64,37+64,35+64   //up,left,right,down
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"        ;  "
+const unsigned short key_map3[] = {
+  0, 0,0,0,0,0,0,0,0,0,0, // Upper case
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,27+64,0,
+  36+64,34+64,37+64,35+64   //up,left,right,down
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/pico81/keyboard_osd.h b/MCUME_pico2/pico81/keyboard_osd.h
new file mode 100644
index 0000000..081bcdd
--- /dev/null
+++ b/MCUME_pico2/pico81/keyboard_osd.h
@@ -0,0 +1,21 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
+
diff --git a/MCUME_pico2/pico81/pico81.cpp b/MCUME_pico2/pico81/pico81.cpp
new file mode 100644
index 0000000..1f82baa
--- /dev/null
+++ b/MCUME_pico2/pico81/pico81.cpp
@@ -0,0 +1,181 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "zx81.h"
+}
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {   
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(15, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();        
+    }
+}
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+     if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    volatile bool vb=vbl; 
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        //while (vbl==vb) {};
+    }
+}
+
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/pico81/program_config.h b/MCUME_pico2/pico81/program_config.h
new file mode 100644
index 0000000..91f04b3
--- /dev/null
+++ b/MCUME_pico2/pico81/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/pico81/z80ops.h b/MCUME_pico2/pico81/z80ops.h
new file mode 100644
index 0000000..c6f0fe3
--- /dev/null
+++ b/MCUME_pico2/pico81/z80ops.h
@@ -0,0 +1,1306 @@
+/* Emulations of the Z80 CPU instruction set - part of xz80.
+ * Copyright (C) 1994 Ian Collier.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define instr(opcode,cycles) case opcode: {tstates+=cycles
+#define HLinstr(opcode,cycles,morecycles) \
+                             case opcode: {unsigned short addr; \
+                                tstates+=cycles; \
+                                if(ixoriy==0)addr=hl; \
+                                else tstates+=morecycles, \
+                                   addr=(ixoriy==1?ix:iy)+ \
+                                        (signed char)fetch(pc),\
+                                   pc++
+#define endinstr             }; break
+
+#define cy (f&1)
+
+#define xh (ixoriy==0?h:ixoriy==1?(ix>>8):(iy>>8))
+#define xl (ixoriy==0?l:ixoriy==1?(ix&0xff):(iy&0xff))
+
+#define setxh(x) (ixoriy==0?(h=(x)):ixoriy==1?(ix=(ix&0xff)|((x)<<8)):\
+                  (iy=(iy&0xff)|((x)<<8)))
+#define setxl(x) (ixoriy==0?(l=(x)):ixoriy==1?(ix=(ix&0xff00)|(x)):\
+                  (iy=(iy&0xff00)|(x)))
+
+#define inc(var) /* 8-bit increment */ ( var++,\
+                                         f=(f&1)|(var&0xa8)|\
+                                           ((!(var&15))<<4)|((!var)<<6)|\
+                                           ((var==128)<<2)\
+                                       )
+#define dec(var) /* 8-bit decrement */ ( f=(f&1)|((!(var&15))<<4)|2,\
+                                         --var,\
+                                         f|=(var&0xa8)|((var==127)<<2)|\
+                                            ((!var)<<6)\
+                                       )
+#define swap(x,y) {unsigned char t=x; x=y; y=t;}
+#define addhl(hi,lo) /* 16-bit add */ if(!ixoriy){\
+                      unsigned short t;\
+                      l=t=l+(lo);\
+                      f=(f&0xc4)|(((t>>=8)+(h&0x0f)+((hi)&0x0f)>15)<<4);\
+                      h=t+=h+(hi);\
+                      f|=(h&0x28)|(t>>8);\
+                   }\
+                   else do{unsigned long t=(ixoriy==1?ix:iy);\
+                      f=(f&0xc4)|(((t&0xfff)+((hi<<8)|lo)>0xfff)<<4);\
+                      t+=(hi<<8)|lo;\
+                      if(ixoriy==1)ix=t; else iy=t;\
+                      f|=((t>>8)&0x28)|(t>>16);\
+                   } while(0)
+#define adda(x,c) /* 8-bit add */ do{unsigned short y;\
+                      unsigned char z=(x);\
+                      y=a+z+(c);\
+                      f=(y&0xa8)|(y>>8)|(((a&0x0f)+(z&0x0f)+(c)>15)<<4)|\
+                        (((~a^z)&0x80&(y^a))>>5);\
+                      f|=(!(a=y))<<6;\
+                   } while(0)
+#define suba(x,c) /* 8-bit subtract */ do{unsigned short y;\
+                      unsigned char z=(x);\
+                      y=(a-z-(c))&0x1ff;\
+                      f=(y&0xa8)|(y>>8)|(((a&0x0f)<(z&0x0f)+(c))<<4)|\
+                        (((a^z)&0x80&(y^a))>>5)|2;\
+                      f|=(!(a=y))<<6;\
+                   } while(0)
+#define cpa(x) /* 8-bit compare */ do{unsigned short y;\
+                      unsigned char z=(x);\
+                      y=(a-z)&0x1ff;\
+                      f=(y&0xa8)|(y>>8)|(((a&0x0f)<(z&0x0f))<<4)|\
+                        (((a^z)&0x80&(y^a))>>5)|2|((!y)<<6);\
+                   } while(0)
+#define anda(x) /* logical and */ do{\
+                      a&=(x);\
+                      f=(a&0xa8)|((!a)<<6)|0x10|parity(a);\
+                   } while(0)
+#define xora(x) /* logical xor */ do{\
+                      a^=(x);\
+                      f=(a&0xa8)|((!a)<<6)|parity(a);\
+                   } while(0)
+#define ora(x) /* logical or */ do{\
+                      a|=(x);\
+                      f=(a&0xa8)|((!a)<<6)|parity(a);\
+                   } while(0)
+
+#define jr /* execute relative jump */ do{int j=(signed char)fetch(pc);\
+                      pc+=j+1;\
+                      tstates+=5;\
+                   } while(0)
+#define jp /* execute jump */ (pc=fetch2(pc))
+#define call /* execute call */ do{\
+                      tstates+=7;\
+                      push2(pc+2);\
+                      jp;\
+                   } while(0)
+#define ret /* execute return */ do{\
+                      tstates+=6;\
+                      pop2(pc);\
+                   } while(0)
+#define pop2(var) /* pop 16-bit register */ (var=fetch2(sp),sp+=2)
+#define pop1(v1,v2) /* pop register pair */ (v2=fetch(sp),\
+                                             v1=fetch(sp+1),sp+=2)
+#define push2(val) /* push 16-bit register */ do{sp-=2;store2(sp,(val));}\
+                                              while(0)
+#define push1(v1,v2) /* push register pair */ do{sp-=2;\
+                                                 store2b(sp,v1,v2);\
+                                              }while(0)
+
+instr(0,4);
+   /* nop */
+endinstr;
+
+instr(1,10);
+   c=fetch(pc),pc++;
+   b=fetch(pc),pc++;
+endinstr;
+
+instr(2,7);
+   store(bc,a);
+endinstr;
+
+instr(3,6);
+   if(!++c)b++;
+endinstr;
+
+instr(4,4);
+   inc(b);
+endinstr;
+
+instr(5,4);
+   dec(b);
+endinstr;
+
+instr(6,7);
+   b=fetch(pc),pc++;
+endinstr;
+
+instr(7,4);
+   a=(a<<1)|(a>>7);
+   f=(f&0xc4)|(a&0x29);
+endinstr;
+
+instr(8,4);
+   swap(a,a1);
+   swap(f,f1);
+endinstr;
+
+instr(9,11);
+   addhl(b,c);
+endinstr;
+
+instr(10,7);
+   a=fetch(bc);
+endinstr;
+
+instr(11,6);
+   if(!c--)b--;
+endinstr;
+
+instr(12,4);
+   inc(c);
+endinstr;
+
+instr(13,4);
+   dec(c);
+endinstr;
+
+instr(14,4);
+   c=fetch(pc),pc++;
+endinstr;
+
+instr(15,4);
+   f=(f&0xc4)|(a&1);
+   a=(a>>1)|(a<<7);
+   f|=a&0x28;
+endinstr;
+
+instr(16,8);
+   if(!--b)pc++;
+   else jr;
+endinstr;
+
+instr(17,10);
+   e=fetch(pc),pc++;
+   d=fetch(pc),pc++;
+endinstr;
+
+instr(18,7);
+   store(de,a);
+endinstr;
+
+instr(19,6);
+   if(!++e)d++;
+endinstr;
+
+instr(20,4);
+   inc(d);
+endinstr;
+
+instr(21,4);
+   dec(d);
+endinstr;
+
+instr(22,7);
+   d=fetch(pc),pc++;
+endinstr;
+
+instr(23,4);
+  {int t=a>>7;
+   a=(a<<1)|(f&1);
+   f=(f&0xc4)|(a&0x28)|t;
+  }
+endinstr;
+
+instr(24,7);
+   jr;
+endinstr;
+
+instr(25,11);
+   addhl(d,e);
+endinstr;
+
+instr(26,7);
+   a=fetch(de);
+endinstr;
+
+instr(27,6);
+   if(!e--)d--;
+endinstr;
+
+instr(28,4);
+   inc(e);
+endinstr;
+
+instr(29,4);
+   dec(e);
+endinstr;
+
+instr(30,4);
+   e=fetch(pc),pc++;
+endinstr;
+
+instr(31,4);
+  {int t=a&1;
+   a=(a>>1)|(f<<7);
+   f=(f&0xc4)|(a&0x28)|t;
+  }
+endinstr;
+
+instr(32,7);
+  if(f&0x40)pc++;
+  else jr;
+endinstr;
+
+instr(33,10);
+   if(!ixoriy){
+      l=fetch(pc),pc++;
+      h=fetch(pc),pc++;
+   }
+   else {
+      if(ixoriy==1)
+        ix=fetch2(pc);
+      else iy=fetch2(pc);
+      pc+=2;
+   }
+endinstr;
+
+instr(34,16);
+   {unsigned short addr=fetch2(pc);
+    pc+=2;
+    if(!ixoriy)store2b(addr,h,l);
+    else if(ixoriy==1)store2(addr,ix);
+    else store2(addr,iy);
+   }
+endinstr;
+
+instr(35,6);
+   if(!ixoriy){if(!++l)h++;}
+   else if(ixoriy==1)ix++;
+   else iy++;
+endinstr;
+
+instr(36,4);
+   if(ixoriy==0)inc(h);
+   else{unsigned char t;
+      t=(ixoriy==1?ix:iy)>>8;
+      inc(t);
+      if(ixoriy==1)ix=(ix&0xff)|(t<<8);
+      else iy=(iy&0xff)|(t<<8);
+   }
+endinstr;
+
+instr(37,4);
+   if(ixoriy==0)dec(h);
+   else{unsigned char t;
+      t=(ixoriy==1?ix:iy)>>8;
+      dec(t);
+      if(ixoriy==1)ix=(ix&0xff)|(t<<8);
+      else iy=(iy&0xff)|(t<<8);
+   }
+endinstr;
+
+instr(38,7);
+   setxh(fetch(pc));
+   pc++;
+endinstr;
+
+instr(39,4);
+   {
+      unsigned char incr=0, carry=cy;
+      if((f&0x10) || (a&0x0f)>9) incr=6;
+      if((f&1) || (a>>4)>9) incr|=0x60;
+      if(f&2)suba(incr,0);
+      else {
+         if(a>0x90 && (a&15)>9)incr|=0x60;
+         adda(incr,0);
+      }
+      f=((f|carry)&0xfb)|parity(a);
+   }
+endinstr;
+
+instr(40,7);
+   if(f&0x40)jr;
+   else pc++;
+endinstr;
+
+instr(41,11);
+   if(!ixoriy)addhl(h,l);
+   else if(ixoriy==1)addhl((ix>>8),(ix&0xff));
+   else addhl((iy>>8),(iy&0xff));
+endinstr;
+
+instr(42,16);
+  {unsigned short addr=fetch2(pc);
+   pc+=2;
+   if(!ixoriy){
+      l=fetch(addr);
+      h=fetch(addr+1);
+   }
+   else if(ixoriy==1)ix=fetch2(addr);
+   else iy=fetch2(addr);
+  }
+endinstr;
+
+instr(43,6);
+   if(!ixoriy){if(!l--)h--;}
+   else if(ixoriy==1)ix--;
+   else iy--;
+endinstr;
+
+instr(44,4);
+   if(!ixoriy)inc(l);
+   else {unsigned char t;
+      t=(ixoriy==1?ix:iy);
+      inc(t);
+      if(ixoriy==1)ix=(ix&0xff00)|t;
+      else iy=(iy&0xff00)|t;
+   }
+endinstr;
+
+instr(45,4);
+   if(!ixoriy)dec(l);
+   else {unsigned char t;
+      t=(ixoriy==1?ix:iy);
+      dec(t);
+      if(ixoriy==1)ix=(ix&0xff00)|t;
+      else iy=(iy&0xff00)|t;
+   }
+endinstr;
+
+instr(46,4);
+   setxl(fetch(pc));
+   pc++;
+endinstr;
+
+instr(47,4);
+   a=~a;
+   f=(f&0xc5)|(a&0x28)|0x12;
+endinstr;
+
+instr(48,7);
+   if(f&1)pc++;
+   else jr;
+endinstr;
+
+instr(49,10);
+   sp=fetch2(pc);
+   pc+=2;
+endinstr;
+
+instr(50,13);
+  {unsigned short addr=fetch2(pc);
+   pc+=2;
+   store(addr,a);
+  }
+endinstr;
+
+instr(51,6);
+   sp++;
+endinstr;
+
+HLinstr(52,11,8);
+  {unsigned char t=fetch(addr);
+   inc(t);
+   store(addr,t);
+  }
+endinstr;
+
+HLinstr(53,11,8);
+  {unsigned char t=fetch(addr);
+   dec(t);
+   store(addr,t);
+  }
+endinstr;
+
+HLinstr(54,10,5);
+   store(addr,fetch(pc));
+   pc++;
+endinstr;
+
+instr(55,4);
+   f=(f&0xc4)|1|(a&0x28);
+endinstr;
+
+instr(56,7);
+   if(f&1)jr;
+   else pc++;
+endinstr;
+
+instr(57,11);
+   addhl((sp>>8),(sp&0xff));
+endinstr;
+
+instr(58,13);
+  {unsigned short addr=fetch2(pc);
+   pc+=2;
+   a=fetch(addr);
+  }
+endinstr;
+
+instr(59,6);
+   sp--;
+endinstr;
+
+instr(60,4);
+   inc(a);
+endinstr;
+
+instr(61,4);
+   dec(a);
+endinstr;
+
+instr(62,4);
+   a=fetch(pc),pc++;
+endinstr;
+
+instr(63,4);
+   f=(f&0xc4)|(cy^1)|(cy<<4)|(a&0x28);
+endinstr;
+
+instr(0x40,4);
+   /* ld b,b */
+endinstr;
+
+instr(0x41,4);
+   b=c;
+endinstr;
+
+instr(0x42,4);
+   b=d;
+endinstr;
+
+instr(0x43,4);
+   b=e;
+endinstr;
+
+instr(0x44,4);
+   b=xh;
+endinstr;
+
+instr(0x45,4);
+   b=xl;
+endinstr;
+
+HLinstr(0x46,7,8);
+   b=fetch(addr);
+endinstr;
+
+instr(0x47,4);
+   b=a;
+endinstr;
+
+instr(0x48,4);
+   c=b;
+endinstr;
+
+instr(0x49,4);
+   /* ld c,c */
+endinstr;
+
+instr(0x4a,4);
+   c=d;
+endinstr;
+
+instr(0x4b,4);
+   c=e;
+endinstr;
+
+instr(0x4c,4);
+   c=xh;
+endinstr;
+
+instr(0x4d,4);
+   c=xl;
+endinstr;
+
+HLinstr(0x4e,7,8);
+   c=fetch(addr);
+endinstr;
+
+instr(0x4f,4);
+   c=a;
+endinstr;
+
+instr(0x50,4);
+   d=b;
+endinstr;
+
+instr(0x51,4);
+   d=c;
+endinstr;
+
+instr(0x52,4);
+   /* ld d,d */
+endinstr;
+
+instr(0x53,4);
+   d=e;
+endinstr;
+
+instr(0x54,4);
+   d=xh;
+endinstr;
+
+instr(0x55,4);
+   d=xl;
+endinstr;
+
+HLinstr(0x56,7,8);
+   d=fetch(addr);
+endinstr;
+
+instr(0x57,4);
+   d=a;
+endinstr;
+
+instr(0x58,4);
+   e=b;
+endinstr;
+
+instr(0x59,4);
+   e=c;
+endinstr;
+
+instr(0x5a,4);
+   e=d;
+endinstr;
+
+instr(0x5b,4);
+   /* ld e,e */
+endinstr;
+
+instr(0x5c,4);
+   e=xh;
+endinstr;
+
+instr(0x5d,4);
+   e=xl;
+endinstr;
+
+HLinstr(0x5e,7,8);
+   e=fetch(addr);
+endinstr;
+
+instr(0x5f,4);
+   e=a;
+endinstr;
+
+instr(0x60,4);
+   setxh(b);
+endinstr;
+
+instr(0x61,4);
+   setxh(c);
+endinstr;
+
+instr(0x62,4);
+   setxh(d);
+endinstr;
+
+instr(0x63,4);
+   setxh(e);
+endinstr;
+
+instr(0x64,4);
+   /* ld h,h */
+endinstr;
+
+instr(0x65,4);
+   setxh(xl);
+endinstr;
+
+HLinstr(0x66,7,8);
+   h=fetch(addr);
+endinstr;
+
+instr(0x67,4);
+   setxh(a);
+endinstr;
+
+instr(0x68,4);
+   setxl(b);
+endinstr;
+
+instr(0x69,4);
+   setxl(c);
+endinstr;
+
+instr(0x6a,4);
+   setxl(d);
+endinstr;
+
+instr(0x6b,4);
+   setxl(e);
+endinstr;
+
+instr(0x6c,4);
+   setxl(xh);
+endinstr;
+
+instr(0x6d,4);
+   /* ld l,l */
+endinstr;
+
+HLinstr(0x6e,7,8);
+   l=fetch(addr);
+endinstr;
+
+instr(0x6f,4);
+   setxl(a);
+endinstr;
+
+HLinstr(0x70,7,8);
+   store(addr,b);
+endinstr;
+
+HLinstr(0x71,7,8);
+   store(addr,c);
+endinstr;
+
+HLinstr(0x72,7,8);
+   store(addr,d);
+endinstr;
+
+HLinstr(0x73,7,8);
+   store(addr,e);
+endinstr;
+
+HLinstr(0x74,7,8);
+   store(addr,h);
+endinstr;
+
+HLinstr(0x75,7,8);
+   store(addr,l);
+endinstr;
+
+instr(0x76,4);
+pc--;		/* keep nopping until int */
+endinstr;
+
+HLinstr(0x77,7,8);
+   store(addr,a);
+endinstr;
+
+instr(0x78,4);
+   a=b;
+endinstr;
+
+instr(0x79,4);
+   a=c;
+endinstr;
+
+instr(0x7a,4);
+   a=d;
+endinstr;
+
+instr(0x7b,4);
+   a=e;
+endinstr;
+
+instr(0x7c,4);
+   a=xh;
+endinstr;
+
+instr(0x7d,4);
+   a=xl;
+endinstr;
+
+HLinstr(0x7e,7,8);
+   a=fetch(addr);
+endinstr;
+
+instr(0x7f,4);
+   /* ld a,a */
+endinstr;
+
+instr(0x80,4);
+   adda(b,0);
+endinstr;
+
+instr(0x81,4);
+   adda(c,0);
+endinstr;
+
+instr(0x82,4);
+   adda(d,0);
+endinstr;
+
+instr(0x83,4);
+   adda(e,0);
+endinstr;
+
+instr(0x84,4);
+   adda(xh,0);
+endinstr;
+
+instr(0x85,4);
+   adda(xl,0);
+endinstr;
+
+HLinstr(0x86,7,8);
+   adda(fetch(addr),0);
+endinstr;
+
+instr(0x87,4);
+   adda(a,0);
+endinstr;
+
+instr(0x88,4);
+   adda(b,cy);
+endinstr;
+
+instr(0x89,4);
+   adda(c,cy);
+endinstr;
+
+instr(0x8a,4);
+   adda(d,cy);
+endinstr;
+
+instr(0x8b,4);
+   adda(e,cy);
+endinstr;
+
+instr(0x8c,4);
+   adda(xh,cy);
+endinstr;
+
+instr(0x8d,4);
+   adda(xl,cy);
+endinstr;
+
+HLinstr(0x8e,7,8);
+   adda(fetch(addr),cy);
+endinstr;
+
+instr(0x8f,4);
+   adda(a,cy);
+endinstr;
+
+instr(0x90,4);
+   suba(b,0);
+endinstr;
+
+instr(0x91,4);
+   suba(c,0);
+endinstr;
+
+instr(0x92,4);
+   suba(d,0);
+endinstr;
+
+instr(0x93,4);
+   suba(e,0);
+endinstr;
+
+instr(0x94,4);
+   suba(xh,0);
+endinstr;
+
+instr(0x95,4);
+   suba(xl,0);
+endinstr;
+
+HLinstr(0x96,7,8);
+   suba(fetch(addr),0);
+endinstr;
+
+instr(0x97,4);
+   suba(a,0);
+endinstr;
+
+instr(0x98,4);
+   suba(b,cy);
+endinstr;
+
+instr(0x99,4);
+   suba(c,cy);
+endinstr;
+
+instr(0x9a,4);
+   suba(d,cy);
+endinstr;
+
+instr(0x9b,4);
+   suba(e,cy);
+endinstr;
+
+instr(0x9c,4);
+   suba(xh,cy);
+endinstr;
+
+instr(0x9d,4);
+   suba(xl,cy);
+endinstr;
+
+HLinstr(0x9e,7,8);
+   suba(fetch(addr),cy);
+endinstr;
+
+instr(0x9f,4);
+   suba(a,cy);
+endinstr;
+
+instr(0xa0,4);
+   anda(b);
+endinstr;
+
+instr(0xa1,4);
+   anda(c);
+endinstr;
+
+instr(0xa2,4);
+   anda(d);
+endinstr;
+
+instr(0xa3,4);
+   anda(e);
+endinstr;
+
+instr(0xa4,4);
+   anda(xh);
+endinstr;
+
+instr(0xa5,4);
+   anda(xl);
+endinstr;
+
+HLinstr(0xa6,7,8);
+   anda(fetch(addr));
+endinstr;
+
+instr(0xa7,4);
+   anda(a);
+endinstr;
+
+instr(0xa8,4);
+   xora(b);
+endinstr;
+
+instr(0xa9,4);
+   xora(c);
+endinstr;
+
+instr(0xaa,4);
+   xora(d);
+endinstr;
+
+instr(0xab,4);
+   xora(e);
+endinstr;
+
+instr(0xac,4);
+   xora(xh);
+endinstr;
+
+instr(0xad,4);
+   xora(xl);
+endinstr;
+
+HLinstr(0xae,7,8);
+   xora(fetch(addr));
+endinstr;
+
+instr(0xaf,4);
+   xora(a);
+endinstr;
+
+instr(0xb0,4);
+   ora(b);
+endinstr;
+
+instr(0xb1,4);
+   ora(c);
+endinstr;
+
+instr(0xb2,4);
+   ora(d);
+endinstr;
+
+instr(0xb3,4);
+   ora(e);
+endinstr;
+
+instr(0xb4,4);
+   ora(xh);
+endinstr;
+
+instr(0xb5,4);
+   ora(xl);
+endinstr;
+
+HLinstr(0xb6,7,8);
+   ora(fetch(addr));
+endinstr;
+
+instr(0xb7,4);
+   ora(a);
+endinstr;
+
+instr(0xb8,4);
+   cpa(b);
+endinstr;
+
+instr(0xb9,4);
+   cpa(c);
+endinstr;
+
+instr(0xba,4);
+   cpa(d);
+endinstr;
+
+instr(0xbb,4);
+   cpa(e);
+endinstr;
+
+instr(0xbc,4);
+   cpa(xh);
+endinstr;
+
+instr(0xbd,4);
+   cpa(xl);
+endinstr;
+
+HLinstr(0xbe,7,8);
+   cpa(fetch(addr));
+endinstr;
+
+instr(0xbf,4);
+   cpa(a);
+endinstr;
+
+instr(0xc0,5);
+   if(!(f&0x40))ret;
+endinstr;
+
+instr(0xc1,10);
+   pop1(b,c);
+endinstr;
+
+instr(0xc2,10);
+   if(!(f&0x40))jp;
+   else pc+=2;
+endinstr;
+
+instr(0xc3,10);
+   jp;
+endinstr;
+
+instr(0xc4,10);
+   if(!(f&0x40))call;
+   else pc+=2;
+endinstr;
+
+instr(0xc5,11);
+   push1(b,c);
+endinstr;
+
+instr(0xc6,7);
+   adda(fetch(pc),0);
+   pc++;
+endinstr;
+
+instr(0xc7,11);
+   push2(pc);
+   pc=0;
+endinstr;
+
+instr(0xc8,5);
+   if(f&0x40)ret;
+endinstr;
+
+instr(0xc9,4);
+   ret;
+endinstr;
+
+instr(0xca,10);
+   if(f&0x40)jp;
+   else pc+=2;
+endinstr;
+
+instr(0xcb,4);
+#include "cbops.h"
+endinstr;
+
+instr(0xcc,10);
+   if(f&0x40)call;
+   else pc+=2;
+endinstr;
+
+instr(0xcd,10);
+   call;
+endinstr;
+
+instr(0xce,7);
+   adda(fetch(pc),cy);
+   pc++;
+endinstr;
+
+instr(0xcf,11);
+   push2(pc);
+   pc=8;
+endinstr;
+
+instr(0xd0,5);
+   if(!cy)ret;
+endinstr;
+
+instr(0xd1,10);
+   pop1(d,e);
+endinstr;
+
+instr(0xd2,10);
+   if(!cy)jp;
+   else pc+=2;
+endinstr;
+
+instr(0xd3,11);
+   tstates+=out(a,fetch(pc),a);
+   pc++;
+endinstr;
+
+instr(0xd4,10);
+   if(!cy)call;
+   else pc+=2;
+endinstr;
+
+instr(0xd5,11);
+   push1(d,e);
+endinstr;
+
+instr(0xd6,7);
+   suba(fetch(pc),0);
+   pc++;
+endinstr;
+
+instr(0xd7,11);
+   push2(pc);
+   pc=16;
+endinstr;
+
+instr(0xd8,5);
+   if(cy)ret;
+endinstr;
+
+instr(0xd9,4);
+   swap(b,b1);
+   swap(c,c1);
+   swap(d,d1);
+   swap(e,e1);
+   swap(h,h1);
+   swap(l,l1);
+endinstr;
+
+instr(0xda,10);
+   if(cy)jp;
+   else pc+=2;
+endinstr;
+
+instr(0xdb,11);
+   {unsigned short t;
+      a=t=in(a,fetch(pc));
+      tstates+=t>>8;
+      pc++;
+   }
+endinstr;
+
+instr(0xdc,10);
+   if(cy)call;
+   else pc+=2;
+endinstr;
+
+instr(0xdd,4);
+   new_ixoriy=1;
+   intsample=0;
+endinstr;
+
+instr(0xde,7);
+   suba(fetch(pc),cy);
+   pc++;
+endinstr;
+
+instr(0xdf,11);
+   push2(pc);
+   pc=24;
+endinstr;
+
+instr(0xe0,5);
+   if(!(f&4))ret;
+endinstr;
+
+instr(0xe1,10);
+   if(!ixoriy)pop1(h,l);
+   else if(ixoriy==1)pop2(ix);
+   else pop2(iy);
+endinstr;
+
+instr(0xe2,10);
+   if(!(f&4))jp;
+   else pc+=2;
+endinstr;
+
+instr(0xe3,19);
+   if(!ixoriy){
+      unsigned short t=fetch2(sp);
+      store2b(sp,h,l);
+      l=t;
+      h=t>>8;
+   }
+   else if(ixoriy==1){
+      unsigned short t=fetch2(sp);
+      store2(sp,ix);
+      ix=t;
+   }
+   else{
+      unsigned short t=fetch2(sp);
+      store2(sp,iy);
+      iy=t;
+   }
+endinstr;
+
+instr(0xe4,10);
+   if(!(f&4))call;
+   else pc+=2;
+endinstr;
+
+instr(0xe5,11);
+   if(!ixoriy)push1(h,l);
+   else if(ixoriy==1)push2(ix);
+   else push2(iy);
+endinstr;
+
+instr(0xe6,7);
+   anda(fetch(pc));
+   pc++;
+endinstr;
+
+instr(0xe7,11);
+   push2(pc);
+   pc=32;
+endinstr;
+
+instr(0xe8,5);
+   if(f&4)ret;
+endinstr;
+
+instr(0xe9,4);
+   pc=!ixoriy?hl:ixoriy==1?ix:iy;
+endinstr;
+
+instr(0xea,10);
+   if(f&4)jp;
+   else pc+=2;
+endinstr;
+
+instr(0xeb,4);
+   swap(h,d);
+   swap(e,l);
+endinstr;
+
+instr(0xec,10);
+   if(f&4)call;
+   else pc+=2;
+endinstr;
+
+instr(0xed,4);
+#include"edops.h"
+endinstr;
+
+instr(0xee,7);
+   xora(fetch(pc));
+   pc++;
+endinstr;
+
+instr(0xef,11);
+   push2(pc);
+   pc=40;
+endinstr;
+
+instr(0xf0,5);
+   if(!(f&0x80))ret;
+endinstr;
+
+instr(0xf1,10);
+   pop1(a,f);
+endinstr;
+
+instr(0xf2,10);
+   if(!(f&0x80))jp;
+   else pc+=2;
+endinstr;
+
+instr(0xf3,4);
+   iff1=iff2=0;
+   intsample=0;
+endinstr;
+
+instr(0xf4,10);
+   if(!(f&0x80))call;
+   else pc+=2;
+endinstr;
+
+instr(0xf5,11);
+   push1(a,f);
+endinstr;
+
+instr(0xf6,7);
+   ora(fetch(pc));
+   pc++;
+endinstr;
+
+instr(0xf7,11);
+   push2(pc);
+   pc=48;
+endinstr;
+
+instr(0xf8,5);
+   if(f&0x80)ret;
+endinstr;
+
+instr(0xf9,6);
+   sp=!ixoriy?hl:ixoriy==1?ix:iy;
+endinstr;
+
+instr(0xfa,10);
+   if(f&0x80)jp;
+   else pc+=2;
+endinstr;
+
+instr(0xfb,4);
+   iff1=iff2=1;
+   intsample=0;
+endinstr;
+
+instr(0xfc,10);
+   if(f&0x80)call;
+   else pc+=2;
+endinstr;
+
+instr(0xfd,4);
+   new_ixoriy=2;
+   intsample=0;
+endinstr;
+
+instr(0xfe,7);
+   cpa(fetch(pc));
+   pc++;
+endinstr;
+
+instr(0xff,11);
+   push2(pc);
+   pc=56;
+endinstr;
+
+
diff --git a/MCUME_pico2/pico81/zx80rom.h b/MCUME_pico2/pico81/zx80rom.h
new file mode 100644
index 0000000..7b35247
--- /dev/null
+++ b/MCUME_pico2/pico81/zx80rom.h
@@ -0,0 +1,259 @@
+const unsigned char PROGMEM zx80rom[] = {
+	0x21, 0xff, 0x7f, 0x3e, 0x3f, 0xc3, 0x61, 0x02, 0xe1, 0x6e, 0xfd, 0xcb, 0x00, 0x7e, 0x18, 0x03, 
+	0xc3, 0x60, 0x05, 0xc8, 0xfd, 0x75, 0x00, 0xc9, 0x18, 0x38, 0x2a, 0x26, 0x40, 0x7e, 0xa7, 0xc0, 
+	0xcd, 0x52, 0x00, 0x18, 0xf9, 0xcd, 0x55, 0x00, 0xcd, 0x1a, 0x00, 0x06, 0x00, 0xc3, 0xe1, 0x09, 
+	0xcd, 0x4f, 0x09, 0xd0, 0xc5, 0xc3, 0xf3, 0x0c, 0x0d, 0xc2, 0x45, 0x00, 0xe1, 0x05, 0xc8, 0xcb, 
+	0xd9, 0xed, 0x4f, 0xfb, 0xe9, 0xd1, 0xc8, 0x18, 0xf8, 0xcd, 0x25, 0x00, 0x7e, 0xfe, 0xd9, 0xc2, 
+	0xae, 0x08, 0x2a, 0x26, 0x40, 0x23, 0x22, 0x26, 0x40, 0x7e, 0xfe, 0xb0, 0xc0, 0x22, 0x04, 0x40, 
+	0xfd, 0xcb, 0x19, 0x7e, 0x28, 0xef, 0xfd, 0xcb, 0x01, 0xd6, 0x18, 0xe9, 0x3f, 0x3d, 0x28, 0x3b, 
+	0x26, 0x38, 0x29, 0x2b, 0x2c, 0x36, 0x3c, 0x2a, 0x37, 0x39, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x1c, 
+	0x25, 0x24, 0x23, 0x22, 0x35, 0x34, 0x2e, 0x3a, 0x3e, 0x76, 0x31, 0x30, 0x2f, 0x2d, 0x00, 0x1b, 
+	0x32, 0x33, 0x27, 0x0e, 0xd7, 0x0f, 0xdf, 0x09, 0x08, 0x06, 0x07, 0x0b, 0x02, 0x03, 0x04, 0x05, 
+	0x0a, 0xdb, 0xe0, 0xd5, 0xd6, 0x72, 0x77, 0x74, 0x73, 0x70, 0x71, 0xde, 0xd9, 0xda, 0x0d, 0x01, 
+	0x75, 0xe3, 0xdd, 0xdc, 0xe2, 0x0c, 0xd8, 0xe4, 0xe5, 0xe1, 0xd4, 0x8f, 0x81, 0x39, 0x2d, 0x2a, 
+	0xb3, 0x39, 0xb4, 0x99, 0x9a, 0x91, 0x90, 0x33, 0x34, 0xb9, 0x92, 0x93, 0x94, 0x95, 0x26, 0x33, 
+	0xa9, 0x34, 0xb7, 0x14, 0x94, 0x96, 0x97, 0x98, 0x31, 0x2e, 0x38, 0xb9, 0x37, 0x2a, 0x39, 0x3a, 
+	0x37, 0xb3, 0x28, 0x31, 0xb8, 0x29, 0x2e, 0xb2, 0x38, 0x26, 0x3b, 0xaa, 0x2b, 0x34, 0xb7, 0x2c, 
+	0x34, 0x00, 0x39, 0xb4, 0x35, 0x34, 0x30, 0xaa, 0x2e, 0x33, 0x35, 0x3a, 0xb9, 0x37, 0x26, 0x33, 
+	0x29, 0x34, 0x32, 0x2e, 0x38, 0xaa, 0x31, 0x2a, 0xb9, 0x8f, 0x8f, 0x33, 0x2a, 0x3d, 0xb9, 0x35, 
+	0x37, 0x2e, 0x33, 0xb9, 0x8f, 0x33, 0x2a, 0xbc, 0x37, 0x3a, 0xb3, 0x38, 0x39, 0x34, 0xb5, 0x28, 
+	0x34, 0x33, 0x39, 0x2e, 0x33, 0x3a, 0xaa, 0x2e, 0xab, 0x2c, 0x34, 0x00, 0x38, 0x3a, 0xa7, 0x31, 
+	0x34, 0x26, 0xa9, 0x28, 0x31, 0x2a, 0x26, 0xb7, 0x37, 0x2a, 0xb2, 0x8f, 0xcd, 0xad, 0x01, 0x06, 
+	0x08, 0x10, 0xfe, 0x2a, 0x1e, 0x40, 0x23, 0x22, 0x1e, 0x40, 0x21, 0xff, 0xff, 0x06, 0xfe, 0x48, 
+	0xed, 0x78, 0xf6, 0x01, 0xf6, 0xe0, 0x57, 0x2f, 0xfe, 0x01, 0x9f, 0xb0, 0xa5, 0x6f, 0x7c, 0xa2, 
+	0x67, 0xcb, 0x00, 0xed, 0x78, 0x38, 0xed, 0x1f, 0xcb, 0x14, 0x17, 0x17, 0x17, 0x9f, 0xe6, 0x18, 
+	0xc6, 0x20, 0x32, 0x23, 0x40, 0xed, 0x4b, 0x26, 0x40, 0x22, 0x26, 0x40, 0x78, 0xc6, 0x02, 0xed, 
+	0x42, 0xeb, 0x21, 0x22, 0x40, 0x7e, 0xb2, 0xb3, 0xc8, 0x78, 0xfe, 0xfe, 0x9f, 0x06, 0x1f, 0xb6, 
+	0xa0, 0x1f, 0x77, 0x05, 0x10, 0xfe, 0xd3, 0xff, 0x3e, 0xec, 0x06, 0x19, 0x2a, 0x0c, 0x40, 0xcb, 
+	0xfc, 0xcd, 0xad, 0x01, 0x3e, 0xf3, 0x04, 0x2b, 0xfd, 0x35, 0x23, 0x18, 0x8f, 0xfd, 0x4e, 0x23, 
+	0xed, 0x4f, 0x3e, 0xdd, 0xfb, 0xe9, 0xd1, 0x11, 0xcb, 0x12, 0x3e, 0x7f, 0xdb, 0xfe, 0x1f, 0x30, 
+	0x42, 0x10, 0xfe, 0x1b, 0x7a, 0xb3, 0x20, 0xf2, 0x21, 0x00, 0x40, 0x11, 0x08, 0xf8, 0xcb, 0x06, 
+	0x9f, 0xe6, 0x05, 0xc6, 0x04, 0x4f, 0xd3, 0xff, 0x06, 0x24, 0x10, 0xfe, 0x3e, 0x7f, 0xdb, 0xfe, 
+	0x06, 0x23, 0x10, 0xfe, 0x0d, 0x20, 0xef, 0x42, 0x00, 0x10, 0xfd, 0x16, 0xfe, 0x1d, 0x20, 0xde, 
+	0x1f, 0x30, 0x10, 0xcd, 0xf8, 0x01, 0x18, 0xd3, 0x23, 0xeb, 0x2a, 0x0a, 0x40, 0x37, 0xed, 0x52, 
+	0xeb, 0xd0, 0xe1, 0xc3, 0x83, 0x02, 0xd1, 0x11, 0x12, 0x57, 0x3e, 0x7f, 0xdb, 0xfe, 0x1f, 0x30, 
+	0xf2, 0x17, 0x17, 0x38, 0xf2, 0x1b, 0x7a, 0xb3, 0x20, 0xf0, 0xfd, 0x34, 0x0b, 0x21, 0x00, 0x40, 
+	0x1e, 0x08, 0x3e, 0x7f, 0xdb, 0xfe, 0x1f, 0x30, 0x24, 0x17, 0x17, 0x30, 0xf5, 0x0e, 0x94, 0x06, 
+	0x1a, 0x0d, 0xdb, 0xfe, 0x17, 0xcb, 0x79, 0x79, 0x38, 0xf5, 0x10, 0xf5, 0x20, 0x04, 0xfe, 0x56, 
+	0x30, 0xe0, 0x3f, 0xcb, 0x16, 0x1d, 0x20, 0xda, 0xcd, 0xf8, 0x01, 0x18, 0xd3, 0x15, 0xf2, 0x00, 
+	0x00, 0xfd, 0x35, 0x0b, 0x18, 0xad, 0xcb, 0xb8, 0xcb, 0xb0, 0xed, 0x43, 0x06, 0x40, 0xc1, 0x18, 
+	0x22, 0x36, 0x01, 0x2b, 0xbc, 0x20, 0xfa, 0x23, 0x35, 0x28, 0xfc, 0xf9, 0xf5, 0x3e, 0x0e, 0xed, 
+	0x47, 0xed, 0x56, 0xfd, 0x21, 0x00, 0x40, 0x21, 0x28, 0x40, 0x22, 0x08, 0x40, 0x36, 0x80, 0x23, 
+	0x22, 0x0a, 0x40, 0x2a, 0x0a, 0x40, 0x36, 0xb0, 0x23, 0x36, 0x76, 0x23, 0x22, 0x0c, 0x40, 0xfd, 
+	0x36, 0x12, 0x02, 0xcd, 0x47, 0x07, 0xeb, 0x78, 0xfd, 0x96, 0x12, 0x38, 0x5a, 0x3c, 0x47, 0xd9, 
+	0x2a, 0x06, 0x40, 0xed, 0x5b, 0x13, 0x40, 0xed, 0x52, 0xeb, 0x30, 0x04, 0x19, 0x22, 0x13, 0x40, 
+	0xcd, 0x0a, 0x06, 0x1e, 0x00, 0xcd, 0xf7, 0x04, 0x38, 0xfb, 0x1d, 0x20, 0x33, 0xe5, 0x2a, 0x06, 
+	0x40, 0xcd, 0x0a, 0x06, 0xe1, 0xa7, 0xed, 0x52, 0x21, 0x13, 0x40, 0x30, 0x0b, 0xeb, 0x7e, 0x23, 
+	0xed, 0xa0, 0x12, 0x18, 0xbe, 0x21, 0x06, 0x40, 0x5e, 0x23, 0x56, 0xe5, 0xeb, 0x23, 0xcd, 0x0a, 
+	0x06, 0xcd, 0xc2, 0x03, 0xe1, 0xfd, 0xcb, 0x19, 0x6e, 0x20, 0x0c, 0x72, 0x2b, 0x73, 0x18, 0xa3, 
+	0xcd, 0xc2, 0x05, 0xed, 0x53, 0x0e, 0x40, 0xfd, 0x36, 0x01, 0x01, 0x2a, 0x0a, 0x40, 0xcd, 0xbe, 
+	0x07, 0xed, 0x5b, 0x0e, 0x40, 0xfd, 0x46, 0x12, 0x0e, 0x01, 0xd9, 0x2a, 0x0a, 0x40, 0xcd, 0x12, 
+	0x05, 0x38, 0x0a, 0x21, 0x12, 0x40, 0x34, 0x3e, 0x18, 0xbe, 0x30, 0xb7, 0x77, 0xcd, 0xc2, 0x05, 
+	0xcd, 0x3f, 0x01, 0xcb, 0x28, 0x9f, 0xf6, 0x26, 0x2e, 0x05, 0x95, 0x85, 0x37, 0xcb, 0x19, 0x38, 
+	0xfa, 0x0c, 0x20, 0xc3, 0x48, 0x2d, 0x2e, 0x01, 0x20, 0xf1, 0x21, 0x6b, 0x00, 0x5f, 0x19, 0x7e, 
+	0xfd, 0xcb, 0x01, 0x56, 0x28, 0x07, 0xc6, 0xc0, 0xfe, 0xe6, 0x30, 0x01, 0x7e, 0xfe, 0xc0, 0xea, 
+	0x5e, 0x03, 0x2a, 0x04, 0x40, 0x01, 0x01, 0x00, 0xcd, 0xd5, 0x05, 0x12, 0x18, 0x99, 0x5f, 0x21, 
+	0x92, 0x02, 0x19, 0x19, 0x4e, 0x23, 0x46, 0xc5, 0x2a, 0x04, 0x40, 0xc9, 0x01, 0x01, 0x00, 0xc3, 
+	0x66, 0x06, 0xa9, 0x03, 0xd5, 0x02, 0x82, 0x03, 0x87, 0x03, 0xb9, 0x03, 0xcb, 0x03, 0x08, 0x04, 
+	0x95, 0x03, 0xcd, 0x9e, 0x03, 0x2b, 0x2b, 0x23, 0x7e, 0xfe, 0x76, 0x28, 0x1a, 0x36, 0xb0, 0x2a, 
+	0x04, 0x40, 0x77, 0x18, 0xc7, 0xcd, 0x9e, 0x03, 0x2b, 0xcd, 0x6c, 0x03, 0x18, 0xbe, 0xed, 0x5b, 
+	0x0a, 0x40, 0x1a, 0xfe, 0xb0, 0xc0, 0xd1, 0x18, 0xb3, 0x2a, 0x06, 0x40, 0xcd, 0x0a, 0x06, 0xeb, 
+	0xcd, 0xc2, 0x03, 0x21, 0x07, 0x40, 0xc3, 0xe5, 0x02, 0x11, 0x00, 0x00, 0x18, 0xf5, 0xeb, 0x11, 
+	0xba, 0x03, 0x7e, 0xe6, 0xc0, 0x20, 0xf7, 0x56, 0x23, 0x5e, 0xc9, 0x0e, 0x00, 0xed, 0x5b, 0x0a, 
+	0x40, 0xd9, 0x2a, 0x06, 0x40, 0xcd, 0x0a, 0x06, 0xcd, 0xc2, 0x03, 0x7a, 0xb3, 0xca, 0x83, 0x02, 
+	0x2b, 0xcd, 0xbf, 0x06, 0x2b, 0xcd, 0x24, 0x06, 0x23, 0x23, 0x0b, 0x0b, 0xd9, 0xd5, 0xd9, 0xd1, 
+	0x3e, 0xb0, 0x12, 0x13, 0xe5, 0x21, 0x22, 0x00, 0x19, 0x09, 0xed, 0x72, 0x30, 0xa9, 0xe1, 0xed, 
+	0xb0, 0xed, 0x53, 0x0c, 0x40, 0xc3, 0x93, 0x02, 0x2a, 0x15, 0x40, 0x7c, 0xb5, 0x20, 0x98, 0x2a, 
+	0x04, 0x40, 0xcd, 0x6c, 0x03, 0x2a, 0x0a, 0x40, 0x22, 0x26, 0x40, 0xcd, 0x1a, 0x00, 0xfd, 0xcb, 
+	0x19, 0x6e, 0x20, 0x18, 0xcd, 0x79, 0x06, 0xd9, 0x7c, 0xb5, 0xc2, 0xba, 0x04, 0x2b, 0x2b, 0x22, 
+	0x02, 0x40, 0xcd, 0x47, 0x07, 0xd9, 0x7e, 0xfe, 0x76, 0xca, 0x83, 0x02, 0xfd, 0x36, 0x00, 0xff, 
+	0xfd, 0x36, 0x01, 0x88, 0xcd, 0xbe, 0x07, 0xcd, 0x0a, 0x0d, 0xed, 0x5b, 0x02, 0x40, 0x21, 0x19, 
+	0x40, 0xcb, 0x6e, 0x28, 0x03, 0xcb, 0xae, 0x13, 0xfd, 0xcb, 0x00, 0x7e, 0x28, 0x2a, 0x21, 0x01, 
+	0x40, 0xcb, 0x5e, 0xcb, 0x9e, 0x2a, 0x26, 0x40, 0x23, 0x28, 0x09, 0xeb, 0x7c, 0xe6, 0xc0, 0x20, 
+	0x17, 0xcd, 0x0a, 0x06, 0x7e, 0xe6, 0xc0, 0x20, 0x0f, 0x56, 0x23, 0x5e, 0xed, 0x53, 0x02, 0x40, 
+	0x23, 0x3e, 0x7f, 0xdb, 0xfe, 0x1f, 0x38, 0xbc, 0xcd, 0xe0, 0x06, 0xcd, 0xc2, 0x05, 0x01, 0x20, 
+	0x01, 0xd9, 0x3a, 0x00, 0x40, 0xed, 0x4b, 0x02, 0x40, 0x3c, 0x28, 0x0c, 0xfe, 0x09, 0x20, 0x01, 
+	0x03, 0xed, 0x43, 0x17, 0x40, 0x20, 0x01, 0x0b, 0xcd, 0x56, 0x05, 0x3e, 0x15, 0xd7, 0xcd, 0xa1, 
+	0x06, 0xcd, 0xc2, 0x05, 0xcd, 0x3f, 0x01, 0xc3, 0x83, 0x02, 0x22, 0x06, 0x40, 0xd9, 0xeb, 0xcd, 
+	0x47, 0x07, 0xed, 0x52, 0xd9, 0xcd, 0x0a, 0x06, 0xe5, 0x20, 0x06, 0xcd, 0x24, 0x06, 0xcd, 0x66, 
+	0x06, 0xd9, 0x23, 0x44, 0x4d, 0x7d, 0xd6, 0x03, 0xb4, 0xc4, 0x4f, 0x09, 0xe1, 0x30, 0x15, 0xc5, 
+	0x2b, 0xcd, 0xd5, 0x05, 0x13, 0x2a, 0x0c, 0x40, 0x2b, 0xc1, 0x0b, 0xed, 0xb8, 0x2a, 0x06, 0x40, 
+	0xeb, 0x72, 0x23, 0x73, 0xc3, 0x83, 0x02, 0xed, 0x4b, 0x06, 0x40, 0xcd, 0x1c, 0x06, 0x16, 0x97, 
+	0x28, 0x05, 0x11, 0x00, 0x00, 0xcb, 0x13, 0x7e, 0xfe, 0x40, 0xdc, 0xbf, 0x06, 0xd0, 0x23, 0x7a, 
+	0xd7, 0xd0, 0xfd, 0xcb, 0x01, 0xc6, 0xed, 0x4b, 0x15, 0x40, 0xa7, 0xed, 0x42, 0x20, 0x04, 0x3e, 
+	0xb8, 0xd7, 0xc8, 0x09, 0x7e, 0x23, 0xfe, 0xb0, 0x28, 0x12, 0xfe, 0xc0, 0xea, 0x59, 0x05, 0x38, 
+	0x05, 0xcd, 0x84, 0x05, 0x18, 0x03, 0xcd, 0x59, 0x05, 0xd0, 0x18, 0xda, 0xfd, 0xcb, 0x01, 0x56, 
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+	0x01, 0x2b, 0x77, 0xc9, 0x21, 0x30, 0x0c, 0xc9, 0x7e, 0x3d, 0xc8, 0x23, 0xc9, 0xfd, 0xcb, 0x00, 
+	0x7e, 0xc8, 0xc5, 0x2a, 0x20, 0x40, 0xcd, 0x3b, 0x0b, 0x21, 0x00, 0x40, 0x7e, 0xfe, 0x02, 0x28, 
+	0xd1, 0x17, 0xfd, 0xcb, 0x01, 0x76, 0x38, 0x3b, 0x36, 0xff, 0x28, 0x47, 0x2a, 0x20, 0x40, 0x01, 
+	0x02, 0x00, 0x03, 0x23, 0x7e, 0xcd, 0x18, 0x0d, 0x38, 0xf8, 0xfe, 0xda, 0x28, 0x62, 0xf7, 0x30, 
+	0xb1, 0xd5, 0x2a, 0x20, 0x40, 0x0b, 0x0b, 0x0b, 0x1b, 0x78, 0xb1, 0x3e, 0x40, 0x28, 0x08, 0xed, 
+	0xb0, 0x7e, 0xf6, 0x80, 0x12, 0x3e, 0x60, 0xe1, 0xcd, 0xb9, 0x0c, 0xeb, 0x1b, 0xe1, 0xeb, 0x72, 
+	0x2b, 0x73, 0xc9, 0x20, 0xf8, 0xe1, 0xcd, 0xa4, 0x0c, 0x2a, 0x22, 0x40, 0x2b, 0xcd, 0x24, 0x06, 
+	0xc3, 0x66, 0x06, 0xe1, 0x3e, 0x01, 0x01, 0x01, 0x00, 0xbe, 0x23, 0x03, 0x20, 0xfb, 0xe5, 0xf7, 
+	0xeb, 0xe1, 0xd0, 0xed, 0xb8, 0xeb, 0x23, 0x3e, 0xa0, 0xeb, 0x2a, 0x20, 0x40, 0xae, 0xeb, 0xf5, 
+	0xcd, 0x0d, 0x0d, 0xf1, 0x2b, 0x77, 0x2a, 0x0c, 0x40, 0x22, 0x0a, 0x40, 0x2b, 0x36, 0x80, 0xc9, 
+	0xe1, 0xcf, 0x01, 0xa0, 0xc2, 0xbe, 0x0b, 0xc5, 0x60, 0x69, 0x23, 0x23, 0x29, 0x44, 0x4d, 0xf7, 
+	0xd2, 0x22, 0x0c, 0x2b, 0x54, 0x5d, 0x1b, 0x0b, 0x0b, 0x36, 0x00, 0xed, 0xb8, 0xc1, 0x71, 0x3e, 
+	0x80, 0x18, 0xc6, 0x2a, 0x0a, 0x40, 0xe5, 0x2a, 0x0c, 0x40, 0x2b, 0xcd, 0xd5, 0x05, 0x23, 0x23, 
+	0xc1, 0xed, 0x43, 0x0a, 0x40, 0xc1, 0xeb, 0x23, 0x37, 0xc9, 0x2a, 0x0c, 0x40, 0xed, 0x5b, 0x0a, 
+	0x40, 0xc3, 0x63, 0x06, 0xfe, 0x26, 0x18, 0x02, 0xfe, 0x1c, 0x3f, 0xd0, 0xfe, 0x40, 0xc9, 0x39, 
+	0x0d, 0x3e, 0x0d, 0x44, 0x0d, 0x90, 0x0d, 0xb5, 0x0d, 0xbc, 0x0d, 0x70, 0x0d, 0xc3, 0x0d, 0xcc, 
+	0x0d, 0xcd, 0x0d, 0xd9, 0x0d, 0xdf, 0x0d, 0xde, 0x0d, 0xa7, 0xed, 0x52, 0x18, 0x03, 0xa7, 0xed, 
+	0x5a, 0xe0, 0xcf, 0x05, 0xcd, 0xed, 0x0d, 0xc5, 0x08, 0xcd, 0x55, 0x0d, 0x20, 0x3f, 0xc1, 0x08, 
+	0x1f, 0xd0, 0xc3, 0xf6, 0x0d, 0x44, 0x4d, 0x3e, 0x10, 0x21, 0x00, 0x00, 0x29, 0xcb, 0x11, 0xcb, 
+	0x10, 0x30, 0x04, 0x19, 0x30, 0x01, 0x03, 0x3d, 0x20, 0xf2, 0x7c, 0xe6, 0x80, 0xb0, 0xb1, 0xc9, 
+	0xcb, 0x7a, 0x20, 0xce, 0xaf, 0xcd, 0xf2, 0x0d, 0xa3, 0x08, 0xc5, 0x42, 0x4b, 0xeb, 0x21, 0x01, 
+	0x00, 0x0b, 0xcb, 0x78, 0x20, 0xc8, 0xc5, 0xcd, 0x55, 0x0d, 0xc1, 0x28, 0xf4, 0xc1, 0x18, 0xb2, 
+	0x7a, 0xb3, 0x28, 0xae, 0xcd, 0xed, 0x0d, 0xc5, 0x1f, 0xed, 0x6a, 0x7c, 0x4d, 0x21, 0x00, 0x00, 
+	0x06, 0x10, 0xed, 0x6a, 0xed, 0x52, 0x30, 0x01, 0x19, 0xcb, 0x11, 0x17, 0x10, 0xf4, 0x67, 0x69, 
+	0x23, 0xc1, 0xd8, 0x18, 0x41, 0x7c, 0xa2, 0x67, 0x7d, 0xa3, 0x6f, 0xc9, 0x7c, 0xb2, 0x67, 0x7d, 
+	0xb3, 0x6f, 0xc9, 0xa7, 0xed, 0x52, 0x21, 0xff, 0xff, 0xc8, 0x23, 0xc9, 0xeb, 0xa7, 0xed, 0x52, 
+	0x7c, 0x17, 0xe2, 0xd6, 0x0d, 0x3f, 0xed, 0x62, 0xc9, 0xcd, 0xe4, 0x0d, 0x18, 0xe8, 0xeb, 0xcd, 
+	0xe4, 0x0d, 0x18, 0xf2, 0x1a, 0xbe, 0xc0, 0x3d, 0xc8, 0x13, 0x23, 0x18, 0xf7, 0xaf, 0xcd, 0xf1, 
+	0x0d, 0xeb, 0xcb, 0x7c, 0xc8, 0x3c, 0x08, 0x7c, 0x2f, 0x67, 0x7d, 0x2f, 0x6f, 0x23, 0x08, 0xc9, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 
+	0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
+	0xf0, 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 
+	0x0f, 0x0f, 0x0f, 0x0f, 0xf0, 0xf0, 0xf0, 0xf0, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 
+	0x00, 0x00, 0x00, 0x00, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0x00, 0x00, 0x00, 0x00, 
+	0x00, 0x1e, 0x21, 0x78, 0x20, 0x20, 0x7f, 0x00, 0x00, 0x08, 0x3e, 0x48, 0x3e, 0x09, 0x3e, 0x08, 
+	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x3e, 0x41, 0x06, 0x08, 0x00, 0x08, 0x00, 
+	0x00, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x00, 0x00, 0x10, 0x08, 0x08, 0x08, 0x08, 0x10, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 
+	0x00, 0x00, 0x2a, 0x1c, 0x08, 0x1c, 0x2a, 0x00, 0x00, 0x00, 0x02, 0x04, 0x08, 0x10, 0x20, 0x00, 
+	0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x10, 0x08, 0x04, 0x08, 0x10, 0x00, 
+	0x00, 0x00, 0x04, 0x08, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x08, 0x10, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x00, 
+	0x00, 0x1c, 0x22, 0x41, 0x41, 0x22, 0x1c, 0x00, 0x00, 0x0c, 0x14, 0x04, 0x04, 0x04, 0x1e, 0x00, 
+	0x00, 0x3e, 0x41, 0x01, 0x3e, 0x40, 0x7f, 0x00, 0x00, 0x3e, 0x41, 0x06, 0x01, 0x41, 0x3e, 0x00, 
+	0x00, 0x0c, 0x14, 0x24, 0x44, 0x7f, 0x04, 0x00, 0x00, 0x7f, 0x40, 0x7e, 0x01, 0x41, 0x3e, 0x00, 
+	0x00, 0x3e, 0x40, 0x7e, 0x41, 0x41, 0x3e, 0x00, 0x00, 0x7f, 0x01, 0x02, 0x04, 0x08, 0x08, 0x00, 
+	0x00, 0x3e, 0x41, 0x3e, 0x41, 0x41, 0x3e, 0x00, 0x00, 0x3e, 0x41, 0x41, 0x3f, 0x01, 0x3e, 0x00, 
+	0x00, 0x3e, 0x41, 0x41, 0x7f, 0x41, 0x41, 0x00, 0x00, 0x7e, 0x41, 0x7e, 0x41, 0x41, 0x7e, 0x00, 
+	0x00, 0x1e, 0x21, 0x40, 0x40, 0x21, 0x1e, 0x00, 0x00, 0x7c, 0x42, 0x41, 0x41, 0x42, 0x7c, 0x00, 
+	0x00, 0x7f, 0x40, 0x7c, 0x40, 0x40, 0x7f, 0x00, 0x00, 0x7f, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x00, 
+	0x00, 0x1e, 0x21, 0x40, 0x47, 0x21, 0x1e, 0x00, 0x00, 0x41, 0x41, 0x7f, 0x41, 0x41, 0x41, 0x00, 
+	0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x02, 0x02, 0x02, 0x42, 0x22, 0x1c, 0x00, 
+	0x00, 0x42, 0x44, 0x78, 0x44, 0x42, 0x41, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x7f, 0x00, 
+	0x00, 0x41, 0x63, 0x55, 0x49, 0x41, 0x41, 0x00, 0x00, 0x61, 0x51, 0x49, 0x45, 0x43, 0x41, 0x00, 
+	0x00, 0x3e, 0x41, 0x41, 0x41, 0x41, 0x3e, 0x00, 0x00, 0x7e, 0x41, 0x41, 0x7e, 0x40, 0x40, 0x00, 
+	0x00, 0x3e, 0x41, 0x41, 0x49, 0x45, 0x3e, 0x00, 0x00, 0x7e, 0x41, 0x41, 0x7e, 0x44, 0x42, 0x00, 
+	0x00, 0x3e, 0x40, 0x3e, 0x01, 0x41, 0x3e, 0x00, 0x00, 0x7f, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 
+	0x00, 0x41, 0x41, 0x41, 0x41, 0x41, 0x3e, 0x00, 0x00, 0x41, 0x41, 0x41, 0x22, 0x14, 0x08, 0x00, 
+	0x00, 0x41, 0x41, 0x41, 0x49, 0x55, 0x22, 0x00, 0x00, 0x21, 0x12, 0x0c, 0x0c, 0x12, 0x21, 0x00, 
+	0x00, 0x41, 0x22, 0x1c, 0x08, 0x08, 0x08, 0x00, 0x00, 0x7f, 0x02, 0x04, 0x08, 0x10, 0x7f, 0x00, 
+};
+
diff --git a/MCUME_pico2/pico81/zx81.c b/MCUME_pico2/pico81/zx81.c
new file mode 100644
index 0000000..0140f94
--- /dev/null
+++ b/MCUME_pico2/pico81/zx81.c
@@ -0,0 +1,768 @@
+
+#define PROGMEM
+#include "z80.h"
+//#include "Arduino.h"
+#include "zx80rom.h"
+#include "zx81rom.h"
+#include "emuapi.h"
+#include "common.h"
+#include "AY8910.h"
+#include "kbd.h"
+
+#define MEMORYRAM_SIZE 0x10000
+
+static AY8910 ay;
+//byte memo[ MEMORYRAM_SIZE ];
+byte * mem = 0;
+unsigned char *memptr[64];
+int memattr[64];
+int unexpanded=0;
+int nmigen=0,hsyncgen=0,vsync=0;
+int vsync_visuals=0;
+int signal_int_flag=0;
+int interrupted=0;
+int ramsize=32; //32;
+
+/* the keyboard state and other */
+static byte keyboard[ 8 ] = {0xff,0xff,0xff,0xff, 0xff,0xff,0xff,0xff};;
+static byte * XBuf=0; 
+int zx80=0;
+int autoload=1;
+
+
+struct { unsigned char R,G,B; } Palette[2] = {
+  {   0,   0,   0},
+  { 255, 255, 255}
+};
+
+
+const byte map_qw[8][5] = {
+    {25, 6,27,29,224},// vcxz<caps shift=Lshift>
+    {10, 9, 7,22, 4}, // gfdsa
+    {23,21, 8,26,20}, // trewq
+    {34,33,32,31,30}, // 54321
+    {35,36,37,38,39}, // 67890
+    {28,24,12,18,19}, // yuiop
+    {11,13,14,15,40}, // hjkl<enter>
+    { 5,17,16,1,44},  // bnm. <space>
+};
+
+static char tapename[64]={0};
+static const int kBuf[]={13,25,19,25,19,40}; //,21,40}; // LOAD "" (J shift p shift p, R ENTER) 
+static const int tBuf[]={2,0,2,0,2,2};//200!,2,2};
+static int kcount=0;
+static int timeout=100;
+
+
+
+unsigned int in(int h, int l)
+{
+
+  int ts=0;    /* additional cycles*256 */
+  int tapezeromask=0x80;  /* = 0x80 if no tape noise (?) */
+
+  if(!(l&4)) l=0xfb;
+  if(!(l&1)) l=0xfe;
+
+  switch(l)
+  {
+  //case 0xfb:
+  //  return(printer_inout(0,0));
+    
+  case 0xfe:
+    /* also disables hsync/vsync if nmi off
+     * (yes, vsync requires nmi off too, Flight Simulation confirms this)
+     */
+    if(!nmigen)
+    {
+      hsyncgen=0;
+
+      /* if vsync was on before, record position */
+      if(!vsync)
+        vsync_raise();
+      vsync=1;
+
+    }
+
+    switch(h)
+    {
+        case 0xfe:  return(ts|(keyboard[0]^tapezeromask));
+        case 0xfd:  return(ts|(keyboard[1]^tapezeromask));
+        case 0xfb:  return(ts|(keyboard[2]^tapezeromask));
+        case 0xf7:  return(ts|(keyboard[3]^tapezeromask));
+        case 0xef:  return(ts|(keyboard[4]^tapezeromask));
+        case 0xdf:  return(ts|(keyboard[5]^tapezeromask));
+        case 0xbf:  return(ts|(keyboard[6]^tapezeromask));
+        case 0x7f:  return(ts|(keyboard[7]^tapezeromask));
+        default:
+          {
+            int i,mask,retval=0xff;
+          
+            /* some games (e.g. ZX Galaxians) do smart-arse things
+            * like zero more than one bit. What we have to do to
+            * support this is AND together any for which the corresponding
+            * bit is zero.
+            */
+            for(i=0,mask=1;i<8;i++,mask<<=1)
+              if(!(h&mask))
+                retval&=keyboard[i];
+            return(ts|(retval^tapezeromask));
+          }
+    }
+    break;
+  }
+
+  return(ts|255);
+}
+
+unsigned int out(int h,int l,int a)
+
+{
+  /* either in from fe or out to ff takes one extra cycle;
+   * experimentation strongly suggests not only that out to
+   * ff takes one extra, but that *all* outs do.
+   */
+  int ts=1;  /* additional cycles */
+
+
+
+  /* the examples in the manual (using DF/0F) and the
+   * documented ports (CF/0F) don't match, so decode is
+   * important for that.
+   */
+  if(!(l&0xf0))   /* not sure how many needed, so assume all 4 */
+    l=0x0f;
+  else
+    if(!(l&0x20))   /* bit 5 low is common to DF and CF */
+      l=0xdf;
+
+
+  if(!(l&4)) l=0xfb;
+  if(!(l&2)) l=0xfd;
+  if(!(l&1)) l=0xfe;
+
+
+  switch(l)
+  {
+    case 0x0f:    /* Zon X data */   
+      WrData8910(&ay,a);
+      break;
+    case 0xdf:    /* Zon X reg. select */  
+      WrCtrl8910(&ay,(a &0x0F));
+      break;
+  
+    case 0xfb:
+      return(ts/*|printer_inout(1,a)*/);
+    case 0xfd:
+      nmigen=0;
+      if(vsync)
+        vsync_lower();
+      vsync=0;
+      hsyncgen=1;
+      break;
+    case 0xfe:
+      if(!zx80)
+      {
+        nmigen=1;
+        break;
+      }
+      /* falls through, if zx80 */
+    case 0xff:  /* XXX should *any* out turn off vsync? */
+      /* fill screen gap since last raising of vsync */
+      if(vsync)
+        vsync_lower();
+      vsync=0;
+      hsyncgen=1;
+      break;
+  }
+
+  return(ts);
+}
+
+
+
+void sighandler(int a)
+{
+  signal_int_flag=1;
+}
+
+void frame_pause(void)
+{
+  signal_int_flag=0;
+
+  if(interrupted<2)
+    interrupted=1;
+}
+
+void do_interrupt()
+{
+  /* being careful here not to screw up any pending reset... */
+  if(interrupted==1)
+    interrupted=0;
+}
+
+static int ik;
+static int ihk;
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+void z81_Input(int bClick) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();
+}
+
+void bitbufBlit(unsigned char * buf)
+{
+  emu_DrawVsync();  
+  memset( XBuf, 1, WIDTH*8 ); 
+  buf = buf + (ZX_VID_MARGIN*(ZX_VID_FULLWIDTH/8));
+  int y,x,i;
+  byte d;
+  for(y=0;y<192;y++)
+  {
+    byte * src = buf + 4;
+    for(x=0;x<32;x++)
+    {
+      byte * dst=&XBuf[(x<<3)+BORDER];
+      d = *src++;
+      for (i=0;i<8;i++)
+      {
+        if ( d & 128 )
+        {
+          *dst++=0;
+        }
+        else
+        {
+          *dst++=1;
+        }
+        d <<= 1;
+      }       
+    }
+    emu_DrawLinePal16(&XBuf[0], WIDTH, HEIGHT, y);   
+    buf += (ZX_VID_FULLWIDTH/8);
+  }
+}
+
+#define INV_KEY 0
+
+const short keyboardAsciiConv[] = // Ascii to Spectrum keys
+{
+/* 0x00 */ INV_KEY,
+/* 0x01 */ INV_KEY,
+/* 0x02 */ INV_KEY,
+/* 0x03 */ INV_KEY,
+/* 0x04 */ INV_KEY,
+/* 0x05 */ INV_KEY,
+/* 0x06 */ INV_KEY,
+/* 0x07 */ INV_KEY,
+/* 0x08 */ INV_KEY,
+/* 0x09 */ INV_KEY,   // tab
+/* 0x0A */ INV_KEY,
+/* 0x0B */ INV_KEY,
+/* 0x0C */ INV_KEY,
+/* 0x0D */ 40,        // enter
+/* 0x0E */ INV_KEY,
+/* 0x0F */ INV_KEY,
+/* 0x10 */ INV_KEY,
+/* 0x11 */ INV_KEY,
+/* 0x12 */ INV_KEY,
+/* 0x13 */ INV_KEY,
+/* 0x14 */ INV_KEY,
+/* 0x15 */ INV_KEY,
+/* 0x16 */ INV_KEY,
+/* 0x17 */ INV_KEY,
+/* 0x18 */ INV_KEY,
+/* 0x19 */ INV_KEY,
+/* 0x1A */ INV_KEY,
+/* 0x1B */ INV_KEY,  // esc
+/* 0x1C */ INV_KEY,
+/* 0x1D */ INV_KEY,
+/* 0x1E */ INV_KEY,
+/* 0x1F */ INV_KEY,
+/* 0x20 */ 44,       // space
+/* 0x21 */ 30+64,    // ! exclamation mark
+/* 0x22 */ 19+64,    // " double quote   
+/* 0x23 */ INV_KEY,  // # dies
+/* 0x24 */ 24+64,    // $ dollar
+/* 0x25 */ INV_KEY,  // % percent
+/* 0x26 */ INV_KEY,  // & ampercent
+/* 0x27 */ INV_KEY,  // ' singlequote
+/* 0x28 */ 12+64,    // ( bracket left
+/* 0x29 */ 18+64,    // ) bracket right
+/* 0x2A */ 5+64,     // * mult
+/* 0x2B */ 14+64,    // + plus
+/* 0x2C */ 1+64,     // , comma
+/* 0x2D */ 13+64,    // - minus
+/* 0x2E */ 1,        // . period
+/* 0x2F */ 25+64,    // / slash
+/* 0x30 */ 39,       // 0
+/* 0x31 */ 30,       // 1
+/* 0x32 */ 31,       // 2 
+/* 0x33 */ 32,       // 3 
+/* 0x34 */ 33,       // 4
+/* 0x35 */ 34,       // 5
+/* 0x36 */ 35,       // 6
+/* 0x37 */ 36,       // 7
+/* 0x38 */ 37,       // 8
+/* 0x39 */ 38,       // 9
+/* 0x3A */ 29+64,    // : colon
+/* 0x3B */ 27+64,    // ; semi colon
+/* 0x3C */ 17+64,    // <
+/* 0x3D */ 15+64,    // = equal
+/* 0x3E */ 16+64,    // >
+/* 0x3F */ 6+64,     // ?
+/* 0x40 */ INV_KEY,    // @
+/* 0x41 */ INV_KEY,  // A
+/* 0x42 */ INV_KEY,  // B
+/* 0x43 */ INV_KEY,  // C
+/* 0x44 */ INV_KEY,  // D
+/* 0x45 */ INV_KEY,  // E
+/* 0x46 */ INV_KEY,  // F
+/* 0x47 */ INV_KEY,  // G
+/* 0x48 */ INV_KEY,  // H
+/* 0x49 */ INV_KEY,  // I
+/* 0x4A */ INV_KEY,  // J
+/* 0x4B */ INV_KEY,  // K
+/* 0x4C */ INV_KEY,  // L
+/* 0x4D */ INV_KEY,  // M
+/* 0x4E */ INV_KEY,  // N
+/* 0x4F */ INV_KEY,  // O
+/* 0x50 */ INV_KEY,  // P
+/* 0x51 */ INV_KEY,  // Q
+/* 0x52 */ INV_KEY,  // R
+/* 0x53 */ INV_KEY,  // S
+/* 0x54 */ INV_KEY,  // T
+/* 0x55 */ INV_KEY,  // U
+/* 0x56 */ INV_KEY,  // V
+/* 0x57 */ INV_KEY,  // W
+/* 0x58 */ INV_KEY,  // X
+/* 0x59 */ INV_KEY,  // Y
+/* 0x5A */ INV_KEY,  // Z
+/* 0x5B */ INV_KEY,  // square bracket open
+/* 0x5C */ INV_KEY,  // baclslach
+/* 0x5D */ INV_KEY,  // square braquet close
+/* 0x5E */ INV_KEY,  // ^ circonflex
+/* 0x5F */ INV_KEY,  // _ undescore
+/* 0x60 */ INV_KEY,  // `backquote
+/* 0x61 */ 4,        // a
+/* 0x62 */ 5,        // b
+/* 0x63 */ 6,        // c
+/* 0x64 */ 7,        // d
+/* 0x65 */ 8,        // e
+/* 0x66 */ 9,        // f
+/* 0x67 */ 10,       // g
+/* 0x68 */ 11,       // h
+/* 0x69 */ 12,       // i
+/* 0x6A */ 13,       // j
+/* 0x6B */ 14,       // k
+/* 0x6C */ 15,       // l
+/* 0x6D */ 16,       // m
+/* 0x6E */ 17,       // n
+/* 0x6F */ 18,       // o
+/* 0x70 */ 19,       // p
+/* 0x71 */ 20,       // q
+/* 0x72 */ 21,       // r
+/* 0x73 */ 22,       // s
+/* 0x74 */ 23,       // t
+/* 0x75 */ 24,       // u
+/* 0x76 */ 25,       // v
+/* 0x77 */ 26,       // w
+/* 0x78 */ 27,       // x
+/* 0x79 */ 28,       // y
+/* 0x7A */ 29,       // z
+/* 0x7B */ INV_KEY,  // curly bracket open
+/* 0x7C */ INV_KEY,  // or
+/* 0x7D */ INV_KEY,  // curly bracket close  
+/* 0x7E */ INV_KEY,  // tilt
+/* 0x7F */ 39+64,   // backspace
+
+/* 0xC0 */ INV_KEY,
+/* 0xC1 */ INV_KEY,
+/* 0xC2 */ INV_KEY,   // F1
+/* 0xC3 */ INV_KEY,   // F2
+/* 0xC4 */ INV_KEY,   // F3
+/* 0xC5 */ INV_KEY,   // F4
+/* 0xC6 */ INV_KEY,   // F5
+/* 0xC7 */ INV_KEY,   // F6
+/* 0xC8 */ INV_KEY,   // F7
+/* 0xC9 */ INV_KEY,   // F8
+/* 0xCA */ INV_KEY,   // F9
+/* 0xCB */ INV_KEY,   // F10
+/* 0xCC */ INV_KEY,
+/* 0xCD */ INV_KEY,
+/* 0xCE */ INV_KEY,
+/* 0xCF */ INV_KEY,
+/* 0xD0 */ INV_KEY,
+/* 0xD1 */ INV_KEY,
+/* 0xD2 */ INV_KEY,
+/* 0xD3 */ INV_KEY,
+/* 0xD4 */ INV_KEY,   // DEL
+/* 0xD5 */ INV_KEY,
+/* 0xD6 */ INV_KEY,
+/* 0xD7 */ 37+64,     // U
+/* 0xD8 */ 34+64,     // L
+/* 0xD9 */ 35+64,     // R
+/* 0xDA */ 36+64,     // D
+/* 0xDB */ INV_KEY,
+/* 0xDC */ INV_KEY,
+/* 0xDD */ INV_KEY,
+/* 0xDE */ INV_KEY,
+/* 0xDF */ INV_KEY
+};
+
+static void updateKeyboard (int asckey)
+{
+  int hk = keyboardAsciiConv[asckey]; 
+
+  memset(keyboard, 0xff, sizeof(keyboard));    
+  {
+    int shift = hk;
+    if (hk >=128) hk -= 128;
+    else if (hk >=64) hk -= 64;    
+    // scan all possibilities
+    for (int j=0;j<8;j++) {
+      for(int i=0;i<5;i++){
+        if ( /*(k == map_qw[j][i]) ||*/ (hk == map_qw[j][i]) ) {
+            keyboard[j] &= ~ (1<<(4-i));
+        }   
+      }  
+    } 
+    if (shift >=64) keyboard[0] &= ~ (1<<0);  // SHift 
+    //else if (shift >=64) keyboard[7] &= ~ (1<<1);  // SHift symboles       
+  } 
+}
+
+/*
+static void handleKeyBuf(void)
+{
+  if (timeout) {
+    timeout--;
+    if (timeout==0) {
+      memset(keyboard, 0xff, sizeof(keyboard)); 
+      emu_printf("key up");
+    }
+  }
+  else {
+    if (!(kcount == (sizeof(kBuf)/sizeof(int)))) {
+      emu_printf("key dw");     
+      timeout=tBuf[kcount];
+      int k=kBuf[kcount++];
+      // scan all possibilities
+      for (int j=0;j<8;j++) {
+        for(int i=0;i<5;i++){
+          if ( (k == map_qw[j][i]) ) {
+              keyboard[j] &= ~ (1<<(4-i));
+          }   
+        }  
+      } 
+      if (timeout == 0) {
+        timeout=tBuf[kcount];
+        int k=kBuf[kcount++];
+        // scan all possibilities
+        for (int j=0;j<8;j++) {
+          for(int i=0;i<5;i++){
+            if ( (k == map_qw[j][i]) ) {
+                keyboard[j] &= ~ (1<<(4-i));
+            }   
+          }  
+        }         
+      }      
+    }       
+  }
+}
+*/
+
+
+/* despite the name, this also works for the ZX80 :-) */
+void reset81()
+{
+  interrupted=2;  /* will cause a reset */
+  memset(mem+0x4000,0,0xc000);  
+}
+
+void load_p(int a)
+{
+  emu_printf("loading...");
+/*
+  int got_ascii_already=0;
+  if(zx80) {    
+  }
+  else
+  {
+    if(a>=32768)  
+    {
+      got_ascii_already=1;
+      emu_printf("got ascii");
+    } 
+    if(!got_ascii_already)
+    {
+    }
+  }
+*/    
+  emu_printf(tapename);
+  int size = emu_FileSize(tapename);
+  int f = emu_FileOpen(tapename, "r+b");  
+  if ( !f ) {
+    /* the partial snap will crash without a file, so reset */
+    if(autoload)
+      reset81(),autoload=0;
+    return;
+  }
+
+  autoload=0;
+  emu_FileRead(mem + (zx80?0x4000:0x4009), size, f);
+  emu_FileClose(f);
+
+  if(zx80)
+    store(0x400b,fetch(0x400b)+1);         
+}
+
+void save_p(int a)
+{
+  
+}
+
+
+
+void zx81hacks()
+{
+  /* patch save routine */
+  mem[0x2fc]=0xed; mem[0x2fd]=0xfd;
+  mem[0x2fe]=0xc3; mem[0x2ff]=0x07; mem[0x300]=0x02;
+
+  /* patch load routine */
+  mem[0x347]=0xeb;
+  mem[0x348]=0xed; mem[0x349]=0xfc;
+  mem[0x34a]=0xc3; mem[0x34b]=0x07; mem[0x34c]=0x02;
+}
+
+void zx80hacks()
+{
+  /* patch save routine */
+  mem[0x1b6]=0xed; mem[0x1b7]=0xfd;
+  mem[0x1b8]=0xc3; mem[0x1b9]=0x83; mem[0x1ba]=0x02;
+
+  /* patch load routine */
+  mem[0x206]=0xed; mem[0x207]=0xfc;
+  mem[0x208]=0xc3; mem[0x209]=0x83; mem[0x20a]=0x02;
+}
+
+static void initmem()
+{
+  int f;
+  int count;
+
+  if(zx80)
+  {
+    memset(mem+0x1000,0,0xf000);
+  }
+  else
+  {
+    memset(mem+0x2000,0,0xe000);
+  }
+
+
+  /* ROM setup */
+  count=0;
+  for(f=0;f<16;f++)
+  {
+    memattr[f]=memattr[32+f]=0;
+    memptr[f]=memptr[32+f]=mem+1024*count;
+    count++;
+    if(count>=(zx80?4:8)) count=0;
+  }
+
+  /* RAM setup */
+  if(unexpanded)
+    ramsize=1;
+  count=0;
+  for(f=16;f<32;f++)
+  {
+    memattr[f]=memattr[32+f]=1;
+    memptr[f]=memptr[32+f]=mem+1024*(16+count);
+    count++;
+    if(count>=ramsize) count=0;
+  }
+
+
+/* z81's ROM and RAM initialisation code is OK for <= 16K RAM but beyond
+ * that it requires a little tweaking.
+ * 
+ * The following diagram shows the ZX81 + 8K ROM. The ZX80 version is
+ * the same except that each 8K ROM region will contain two copies of
+ * the 4K ROM.
+ * 
+ * RAM less than 16K is mirrored throughout the 16K region.
+ * 
+ * The ROM will only detect up to 8000h when setting RAMTOP, therefore
+ * having more than 16K RAM will require RAMTOP to be set by the user
+ * (or user program) to either 49152 for 32K or 65535 for 48/56K.
+ * 
+ *           1K to 16K       32K           48K           56K      Extra Info.
+ * 
+ *  65535  +----------+  +----------+  +----------+  +----------+ 
+ * (FFFFh) | 16K RAM  |  | 16K RAM  |  | 16K RAM  |  | 16K RAM  | DFILE can be
+ *         | mirrored |  | mirrored |  |          |  |          | wholly here.
+ *         |          |  |          |  |          |  |          | 
+ *         |          |  |          |  |          |  |          | BASIC variables
+ *         |          |  |          |  |          |  |          | can go here.
+ *  49152  +----------+  +----------+  +----------+  +----------+ 
+ * (C000h) | 8K ROM   |  | 16K RAM  |  | 16K RAM  |  | 16K RAM  | BASIC program
+ *         | mirrored |  |          |  |          |  |          | is restricted
+ *  40960  +----------+  |          |  |          |  |          | to here.
+ * (A000h) | 8K ROM   |  |          |  |          |  |          | 
+ *         | mirrored |  |          |  |          |  |          | 
+ *  32768  +----------+  +----------+  +----------+  +----------+ 
+ * (8000h) | 16K RAM  |  | 16K RAM  |  | 16K RAM  |  | 16K RAM  | No machine code
+ *         |          |  |          |  |          |  |          | beyond here.
+ *         |          |  |          |  |          |  |          | 
+ *         |          |  |          |  |          |  |          | DFILE can be
+ *         |          |  |          |  |          |  |          | wholly here.
+ *  16384  +----------+  +----------+  +----------+  +----------+ 
+ * (4000h) | 8K ROM   |  | 8K ROM   |  | 8K ROM   |  | 8K RAM   | 
+ *         | mirrored |  | mirrored |  | mirrored |  |          | 
+ *   8192  +----------+  +----------+  +----------+  +----------+ 
+ * (2000h) | 8K ROM   |  | 8K ROM   |  | 8K ROM   |  | 8K ROM   | 
+ *         |          |  |          |  |          |  |          | 
+ *      0  +----------+  +----------+  +----------+  +----------+ 
+ */
+
+  switch(ramsize)
+  {
+    case 56:
+      for(f=8;f<16;f++)
+      {
+        memattr[f]=1;         /* It's now writable */
+        memptr[f]=mem+1024*f;
+      }
+    case 48:
+      for(f=48;f<64;f++)
+      {
+        memattr[f]=1;
+        memptr[f]=mem+1024*f;
+      }
+    case 32:
+      for(f=32;f<48;f++)
+      {
+        memattr[f]=1;
+        memptr[f]=mem+1024*f;
+      }
+      break;
+  }
+
+  if(zx80)
+    zx80hacks();
+  else
+    zx81hacks();
+}
+
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+
+void z81_Init(void) 
+{
+#if HAS_SND
+  emu_sndInit(); 
+#endif 
+  
+  if (XBuf == 0) XBuf = (byte *)emu_Malloc(WIDTH*8);
+  /* Set up the palette */
+  int J;
+  for(J=0;J<2;J++)
+    emu_SetPaletteEntry(Palette[J].R,Palette[J].G,Palette[J].B, J);
+
+
+  emu_printf("Allocating RAM");
+  if (mem == 0) mem = emu_Malloc(MEMORYRAM_SIZE); //&memo[0];
+  
+  Reset8910(&ay,3500000,0);
+  
+  /* load rom with ghosting at 0x2000 */
+  int siz=(zx80?4096:8192);  
+  if(zx80)
+  {
+    memcpy( mem + 0x0000, zx80rom, siz );    
+  }
+  else 
+  {
+    memcpy( mem + 0x0000, zx81rom, siz );   
+  }
+  memcpy(mem+siz,mem,siz);
+  if(zx80)
+    memcpy(mem+siz*2,mem,siz*2);
+    
+  initmem();
+ 
+  /* reset the keyboard state */
+  memset( keyboard, 255, sizeof( keyboard ) );  
+
+  ResetZ80();
+ }
+
+
+void z81_Step(void)
+{
+  ExecZ80();
+  sighandler(0);
+
+  int k  = ik;
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+    
+  updateKeyboard(hk);
+
+  Loop8910(&ay,20);
+}
+
+static int endsWith(const char * s, const char * suffix)
+{
+  int retval = 0;
+  int len = strlen(s);
+  int slen = strlen(suffix);
+  if (len > slen ) {
+    if (!strcmp(&s[len-slen], suffix)) {
+      retval = 1;
+    }
+  }
+   return (retval);  
+}
+
+void z81_Start(char * filename)
+{
+  char c;
+  strncpy(tapename,filename,64);
+  int f = emu_FileOpen(tapename, "r+b");
+  if ( f ) {
+    int fsize = emu_FileRead(&c, 1, f);
+    if ( fsize == 0) { 
+      autoload = 0;
+      emu_printf("no autoload");
+    }
+    emu_FileClose(f);
+  }
+
+  //emu_setKeymap(1); 
+  
+  if ( (endsWith(filename, ".80")) || (endsWith(filename, ".o")) || (endsWith(filename, ".O")))  {
+    zx80 = 1;
+    ramsize = 48;
+    //emu_setKeymap(0);    
+  }
+  else if (endsWith(filename, ".56") ) {
+    ramsize = 56;
+  }
+}
diff --git a/MCUME_pico2/pico81/zx81.h b/MCUME_pico2/pico81/zx81.h
new file mode 100644
index 0000000..b5eded8
--- /dev/null
+++ b/MCUME_pico2/pico81/zx81.h
@@ -0,0 +1,4 @@
+extern void z81_Init(void);
+extern void z81_Step(void);
+extern void z81_Start(char * filename);
+extern void z81_Input(int bClick);
diff --git a/MCUME_pico2/pico81/zx81rom.h b/MCUME_pico2/pico81/zx81rom.h
new file mode 100644
index 0000000..49ac42c
--- /dev/null
+++ b/MCUME_pico2/pico81/zx81rom.h
@@ -0,0 +1,515 @@
+const unsigned char PROGMEM zx81rom[] = {
+	0xd3, 0xfd, 0x01, 0xff, 0x7f, 0xc3, 0xcb, 0x03, 0x2a, 0x16, 0x40, 0x22, 0x18, 0x40, 0x18, 0x46, 
+	0xa7, 0xc2, 0xf1, 0x07, 0xc3, 0xf5, 0x07, 0xff, 0x2a, 0x16, 0x40, 0x7e, 0xa7, 0xc0, 0x00, 0x00, 
+	0xcd, 0x49, 0x00, 0x18, 0xf7, 0xff, 0xff, 0xff, 0xc3, 0x9d, 0x19, 0xf1, 0xd9, 0xe3, 0xd9, 0xc9, 
+	0xc5, 0x2a, 0x14, 0x40, 0xe5, 0xc3, 0x88, 0x14, 0x0d, 0xc2, 0x45, 0x00, 0xe1, 0x05, 0xc8, 0xcb, 
+	0xd9, 0xed, 0x4f, 0xfb, 0xe9, 0xd1, 0xc8, 0x18, 0xf8, 0x2a, 0x16, 0x40, 0x23, 0x22, 0x16, 0x40, 
+	0x7e, 0xfe, 0x7f, 0xc0, 0x18, 0xf6, 0xe1, 0x6e, 0xfd, 0x75, 0x00, 0xed, 0x7b, 0x02, 0x40, 0xcd, 
+	0x07, 0x02, 0xc3, 0xbc, 0x14, 0xff, 0x08, 0x3c, 0xfa, 0x6d, 0x00, 0x28, 0x02, 0x08, 0xc9, 0x08, 
+	0xf5, 0xc5, 0xd5, 0xe5, 0x2a, 0x0c, 0x40, 0xcb, 0xfc, 0x76, 0xd3, 0xfd, 0xdd, 0xe9, 0x3f, 0x3d, 
+	0x28, 0x3b, 0x26, 0x38, 0x29, 0x2b, 0x2c, 0x36, 0x3c, 0x2a, 0x37, 0x39, 0x1d, 0x1e, 0x1f, 0x20, 
+	0x21, 0x1c, 0x25, 0x24, 0x23, 0x22, 0x35, 0x34, 0x2e, 0x3a, 0x3e, 0x76, 0x31, 0x30, 0x2f, 0x2d, 
+	0x00, 0x1b, 0x32, 0x33, 0x27, 0x0e, 0x19, 0x0f, 0x18, 0xe3, 0xe1, 0xe4, 0xe5, 0xe2, 0xc0, 0xd9, 
+	0xe0, 0xdb, 0xdd, 0x75, 0xda, 0xde, 0xdf, 0x72, 0x77, 0x74, 0x73, 0x70, 0x71, 0x0b, 0x11, 0x10, 
+	0x0d, 0xdc, 0x79, 0x14, 0x15, 0x16, 0xd8, 0x0c, 0x1a, 0x12, 0x13, 0x17, 0xcd, 0xce, 0xc1, 0x78, 
+	0xca, 0xcb, 0xcc, 0xd1, 0xd2, 0xc7, 0xc8, 0xc9, 0xcf, 0x40, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 
+	0x78, 0x78, 0x78, 0x78, 0xc2, 0xd3, 0xc4, 0xd6, 0xd5, 0x78, 0xd4, 0xc6, 0xc5, 0xd0, 0x78, 0x78, 
+	0x42, 0xd7, 0x41, 0x08, 0x0a, 0x09, 0x8a, 0x89, 0x81, 0x82, 0x07, 0x84, 0x06, 0x01, 0x02, 0x87, 
+	0x04, 0x05, 0x77, 0x78, 0x85, 0x03, 0x83, 0x8b, 0x91, 0x90, 0x8d, 0x86, 0x78, 0x92, 0x95, 0x96, 
+	0x88, 0x8f, 0x0b, 0x8b, 0x26, 0xb9, 0x39, 0x26, 0xa7, 0x8f, 0x28, 0x34, 0x29, 0xaa, 0x3b, 0x26, 
+	0xb1, 0x31, 0x2a, 0xb3, 0x38, 0x2e, 0xb3, 0x28, 0x34, 0xb8, 0x39, 0x26, 0xb3, 0x26, 0x38, 0xb3, 
+	0x26, 0x28, 0xb8, 0x26, 0x39, 0xb3, 0x31, 0xb3, 0x2a, 0x3d, 0xb5, 0x2e, 0x33, 0xb9, 0x38, 0x36, 
+	0xb7, 0x38, 0x2c, 0xb3, 0x26, 0x27, 0xb8, 0x35, 0x2a, 0x2a, 0xb0, 0x3a, 0x38, 0xb7, 0x38, 0x39, 
+	0x37, 0x8d, 0x28, 0x2d, 0x37, 0x8d, 0x33, 0x34, 0xb9, 0x17, 0x97, 0x34, 0xb7, 0x26, 0x33, 0xa9, 
+	0x13, 0x94, 0x12, 0x94, 0x13, 0x92, 0x39, 0x2d, 0x2a, 0xb3, 0x39, 0xb4, 0x38, 0x39, 0x2a, 0xb5, 
+	0x31, 0x35, 0x37, 0x2e, 0x33, 0xb9, 0x31, 0x31, 0x2e, 0x38, 0xb9, 0x38, 0x39, 0x34, 0xb5, 0x38, 
+	0x31, 0x34, 0xbc, 0x2b, 0x26, 0x38, 0xb9, 0x33, 0x2a, 0xbc, 0x38, 0x28, 0x37, 0x34, 0x31, 0xb1, 
+	0x28, 0x34, 0x33, 0xb9, 0x29, 0x2e, 0xb2, 0x37, 0x2a, 0xb2, 0x2b, 0x34, 0xb7, 0x2c, 0x34, 0x39, 
+	0xb4, 0x2c, 0x34, 0x38, 0x3a, 0xa7, 0x2e, 0x33, 0x35, 0x3a, 0xb9, 0x31, 0x34, 0x26, 0xa9, 0x31, 
+	0x2e, 0x38, 0xb9, 0x31, 0x2a, 0xb9, 0x35, 0x26, 0x3a, 0x38, 0xaa, 0x33, 0x2a, 0x3d, 0xb9, 0x35, 
+	0x34, 0x30, 0xaa, 0x35, 0x37, 0x2e, 0x33, 0xb9, 0x35, 0x31, 0x34, 0xb9, 0x37, 0x3a, 0xb3, 0x38, 
+	0x26, 0x3b, 0xaa, 0x37, 0x26, 0x33, 0xa9, 0x2e, 0xab, 0x28, 0x31, 0xb8, 0x3a, 0x33, 0x35, 0x31, 
+	0x34, 0xb9, 0x28, 0x31, 0x2a, 0x26, 0xb7, 0x37, 0x2a, 0x39, 0x3a, 0x37, 0xb3, 0x28, 0x34, 0x35, 
+	0xbe, 0x37, 0x33, 0xa9, 0x2e, 0x33, 0x30, 0x2a, 0x3e, 0x8d, 0x35, 0xae, 0x23, 0xeb, 0x2a, 0x14, 
+	0x40, 0x37, 0xed, 0x52, 0xeb, 0xd0, 0xe1, 0x21, 0x3b, 0x40, 0x7e, 0x17, 0xae, 0x17, 0xd0, 0x3e, 
+	0x7f, 0x08, 0x06, 0x11, 0xd3, 0xfe, 0x10, 0xfe, 0xd3, 0xfd, 0x08, 0x17, 0x30, 0x08, 0xcb, 0xfe, 
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+	0x00, 0x1c, 0x22, 0x78, 0x20, 0x20, 0x7e, 0x00, 0x00, 0x08, 0x3e, 0x28, 0x3e, 0x0a, 0x3e, 0x08, 
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, 0x3c, 0x42, 0x04, 0x08, 0x00, 0x08, 0x00, 
+	0x00, 0x04, 0x08, 0x08, 0x08, 0x08, 0x04, 0x00, 0x00, 0x20, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, 
+	0x00, 0x00, 0x10, 0x08, 0x04, 0x08, 0x10, 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, 0x08, 0x04, 0x00, 
+	0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 
+	0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x08, 0x3e, 0x08, 0x14, 0x00, 
+	0x00, 0x00, 0x02, 0x04, 0x08, 0x10, 0x20, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x10, 0x20, 
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 
+	0x00, 0x3c, 0x46, 0x4a, 0x52, 0x62, 0x3c, 0x00, 0x00, 0x18, 0x28, 0x08, 0x08, 0x08, 0x3e, 0x00, 
+	0x00, 0x3c, 0x42, 0x02, 0x3c, 0x40, 0x7e, 0x00, 0x00, 0x3c, 0x42, 0x0c, 0x02, 0x42, 0x3c, 0x00, 
+	0x00, 0x08, 0x18, 0x28, 0x48, 0x7e, 0x08, 0x00, 0x00, 0x7e, 0x40, 0x7c, 0x02, 0x42, 0x3c, 0x00, 
+	0x00, 0x3c, 0x40, 0x7c, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x7e, 0x02, 0x04, 0x08, 0x10, 0x10, 0x00, 
+	0x00, 0x3c, 0x42, 0x3c, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x3e, 0x02, 0x3c, 0x00, 
+	0x00, 0x3c, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x00, 0x00, 0x7c, 0x42, 0x7c, 0x42, 0x42, 0x7c, 0x00, 
+	0x00, 0x3c, 0x42, 0x40, 0x40, 0x42, 0x3c, 0x00, 0x00, 0x78, 0x44, 0x42, 0x42, 0x44, 0x78, 0x00, 
+	0x00, 0x7e, 0x40, 0x7c, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x7e, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x00, 
+	0x00, 0x3c, 0x42, 0x40, 0x4e, 0x42, 0x3c, 0x00, 0x00, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x42, 0x00, 
+	0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x02, 0x02, 0x02, 0x42, 0x42, 0x3c, 0x00, 
+	0x00, 0x44, 0x48, 0x70, 0x48, 0x44, 0x42, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x7e, 0x00, 
+	0x00, 0x42, 0x66, 0x5a, 0x42, 0x42, 0x42, 0x00, 0x00, 0x42, 0x62, 0x52, 0x4a, 0x46, 0x42, 0x00, 
+	0x00, 0x3c, 0x42, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x7c, 0x40, 0x40, 0x00, 
+	0x00, 0x3c, 0x42, 0x42, 0x52, 0x4a, 0x3c, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x7c, 0x44, 0x42, 0x00, 
+	0x00, 0x3c, 0x40, 0x3c, 0x02, 0x42, 0x3c, 0x00, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 
+	0x00, 0x42, 0x42, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, 0x00, 
+	0x00, 0x42, 0x42, 0x42, 0x42, 0x5a, 0x24, 0x00, 0x00, 0x42, 0x24, 0x18, 0x18, 0x24, 0x42, 0x00, 
+	0x00, 0x82, 0x44, 0x28, 0x10, 0x10, 0x10, 0x00, 0x00, 0x7e, 0x04, 0x08, 0x10, 0x20, 0x7e, 0x00, 
+};
+
diff --git a/MCUME_pico2/pico_sdk_import.cmake b/MCUME_pico2/pico_sdk_import.cmake
new file mode 100644
index 0000000..28efe9e
--- /dev/null
+++ b/MCUME_pico2/pico_sdk_import.cmake
@@ -0,0 +1,62 @@
+# This is a copy of <PICO_SDK_PATH>/external/pico_sdk_import.cmake
+
+# This can be dropped into an external project to help locate this SDK
+# It should be include()ed prior to project()
+
+if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH))
+    set(PICO_SDK_PATH $ENV{PICO_SDK_PATH})
+    message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT))
+    set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT})
+    message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH))
+    set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH})
+    message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')")
+endif ()
+
+set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK")
+set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable")
+set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK")
+
+if (NOT PICO_SDK_PATH)
+    if (PICO_SDK_FETCH_FROM_GIT)
+        include(FetchContent)
+        set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR})
+        if (PICO_SDK_FETCH_FROM_GIT_PATH)
+            get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}")
+        endif ()
+        FetchContent_Declare(
+                pico_sdk
+                GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk
+                GIT_TAG master
+        )
+        if (NOT pico_sdk)
+            message("Downloading Raspberry Pi Pico SDK")
+            FetchContent_Populate(pico_sdk)
+            set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR})
+        endif ()
+        set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE})
+    else ()
+        message(FATAL_ERROR
+                "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git."
+                )
+    endif ()
+endif ()
+
+get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
+if (NOT EXISTS ${PICO_SDK_PATH})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found")
+endif ()
+
+set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake)
+if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK")
+endif ()
+
+set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
+
+include(${PICO_SDK_INIT_CMAKE_FILE})
diff --git a/MCUME_pico2/picocolem/Codes.h b/MCUME_pico2/picocolem/Codes.h
new file mode 100644
index 0000000..28f1d1b
--- /dev/null
+++ b/MCUME_pico2/picocolem/Codes.h
@@ -0,0 +1,378 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Codes.h                        **/
+/**                                                         **/
+/** This file contains implementation for the main table of **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->HL.B.h);break;
+case ADD_L:    M_ADD(R->HL.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
+case ADD_BYTE: I=RdZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->HL.B.h);break;
+case SUB_L:    M_SUB(R->HL.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
+case SUB_BYTE: I=RdZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->HL.B.h);break;
+case AND_L:    M_AND(R->HL.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
+case AND_BYTE: I=RdZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->HL.B.h);break;
+case OR_L:     M_OR(R->HL.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
+case OR_BYTE:  I=RdZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->HL.B.h);break;
+case ADC_L:    M_ADC(R->HL.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
+case ADC_BYTE: I=RdZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->HL.B.h);break;
+case SBC_L:    M_SBC(R->HL.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
+case SBC_BYTE: I=RdZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->HL.B.h);break;
+case XOR_L:    M_XOR(R->HL.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
+case XOR_BYTE: I=RdZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->HL.B.h);break;
+case CP_L:     M_CP(R->HL.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
+case CP_BYTE:  I=RdZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(HL);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->HL.W;break;
+case LD_SP_HL: R->SP.W=R->HL.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(HL,BC);break;
+case ADD_HL_DE:  M_ADDW(HL,DE);break;
+case ADD_HL_HL:  M_ADDW(HL,HL);break;
+case ADD_HL_SP:  M_ADDW(HL,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->HL.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->HL.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->HL.B.h);break;
+case DEC_L:    M_DEC(R->HL.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->HL.B.h);break;
+case INC_L:    M_INC(R->HL.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+
+case RLCA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(HL);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(HL);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: OutZ80(RdZ80(R->PC.W++),R->AF.B.h);break;
+case INA:  R->AF.B.h=InZ80(RdZ80(R->PC.W++));break;
+case HALT: R->PC.W--;R->IFF|=0x80;R->ICount=0;break;
+
+case DI:
+  R->IFF&=0xFE;
+  break;
+case EI:
+  R->IFF|=0x01;
+  if(R->IRequest!=INT_NONE)
+  {
+    R->IFF|=0x20;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
+case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
+case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
+case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
+case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
+case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
+case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
+case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
+case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
+case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
+case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
+case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
+case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
+case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
+case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
+case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
+case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
+case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
+case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
+case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
+
+case LD_B_BYTE:   R->BC.B.h=RdZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=RdZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=RdZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=RdZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->HL.B.h=RdZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->HL.B.l=RdZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=RdZ80(R->PC.W++);break;
+case LD_xHL_BYTE: WrZ80(R->HL.W,RdZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++); 
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
+  R->HL.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
+
+default:
+  if(R->TrapBadOps)
+    printf
+    (
+      "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
+      (long)R->User,RdZ80(R->PC.W-1),R->PC.W-1
+    );
+  break;
diff --git a/MCUME_pico2/picocolem/CodesCB.h b/MCUME_pico2/picocolem/CodesCB.h
new file mode 100644
index 0000000..c8a5f91
--- /dev/null
+++ b/MCUME_pico2/picocolem/CodesCB.h
@@ -0,0 +1,204 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesCB.h                       **/
+/**                                                         **/
+/** This file contains implementation for the CB table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
+case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
+case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
+case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
+case RLC_A: M_RLC(R->AF.B.h);break;
+
+case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
+case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
+case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
+case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
+case RRC_A: M_RRC(R->AF.B.h);break;
+
+case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
+case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
+case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
+case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
+case RL_A: M_RL(R->AF.B.h);break;
+
+case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
+case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
+case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
+case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
+case RR_A: M_RR(R->AF.B.h);break;
+
+case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
+case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
+case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
+case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
+case SLA_A: M_SLA(R->AF.B.h);break;
+
+case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
+case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
+case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
+case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
+case SRA_A: M_SRA(R->AF.B.h);break;
+
+case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
+case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
+case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
+case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
+case SLL_A: M_SLL(R->AF.B.h);break;
+
+case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
+case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
+case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
+case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
+case SRL_A: M_SRL(R->AF.B.h);break;
+    
+case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
+case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
+case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
+case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,R->AF.B.h);break;
+
+case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
+case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
+case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
+case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,R->AF.B.h);break;
+
+case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
+case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
+case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
+case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,R->AF.B.h);break;
+
+case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
+case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
+case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
+case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,R->AF.B.h);break;
+
+case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
+case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
+case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
+case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,R->AF.B.h);break;
+
+case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
+case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
+case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
+case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,R->AF.B.h);break;
+
+case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
+case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
+case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
+case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,R->AF.B.h);break;
+
+case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
+case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
+case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
+case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,R->AF.B.h);break;
+
+case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
+case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
+case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
+case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
+case RES0_A: M_RES(0,R->AF.B.h);break;
+
+case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
+case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
+case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
+case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
+case RES1_A: M_RES(1,R->AF.B.h);break;
+
+case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
+case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
+case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
+case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
+case RES2_A: M_RES(2,R->AF.B.h);break;
+
+case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
+case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
+case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
+case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
+case RES3_A: M_RES(3,R->AF.B.h);break;
+
+case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
+case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
+case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
+case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
+case RES4_A: M_RES(4,R->AF.B.h);break;
+
+case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
+case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
+case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
+case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
+case RES5_A: M_RES(5,R->AF.B.h);break;
+
+case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
+case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
+case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
+case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
+case RES6_A: M_RES(6,R->AF.B.h);break;
+
+case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
+case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
+case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
+case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
+case RES7_A: M_RES(7,R->AF.B.h);break;
+
+case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
+case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
+case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
+case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
+case SET0_A: M_SET(0,R->AF.B.h);break;
+
+case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
+case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
+case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
+case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
+case SET1_A: M_SET(1,R->AF.B.h);break;
+
+case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
+case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
+case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
+case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
+case SET2_A: M_SET(2,R->AF.B.h);break;
+
+case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
+case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
+case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
+case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
+case SET3_A: M_SET(3,R->AF.B.h);break;
+
+case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
+case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
+case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
+case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
+case SET4_A: M_SET(4,R->AF.B.h);break;
+
+case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
+case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
+case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
+case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
+case SET5_A: M_SET(5,R->AF.B.h);break;
+
+case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
+case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
+case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
+case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
+case SET6_A: M_SET(6,R->AF.B.h);break;
+
+case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
+case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
+case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
+case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
+case SET7_A: M_SET(7,R->AF.B.h);break;
diff --git a/MCUME_pico2/picocolem/CodesED.h b/MCUME_pico2/picocolem/CodesED.h
new file mode 100644
index 0000000..56a7c69
--- /dev/null
+++ b/MCUME_pico2/picocolem/CodesED.h
@@ -0,0 +1,282 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesED.h                       **/
+/**                                                         **/
+/** This file contains implementation for the ED table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+/** This is a special patch for emulating BIOS calls: ********/
+case DB_FE:     PatchZ80(R);break;
+/*************************************************************/
+
+case ADC_HL_BC: M_ADCW(BC);break;
+case ADC_HL_DE: M_ADCW(DE);break;
+case ADC_HL_HL: M_ADCW(HL);break;
+case ADC_HL_SP: M_ADCW(SP);break;
+
+case SBC_HL_BC: M_SBCW(BC);break;
+case SBC_HL_DE: M_SBCW(DE);break;
+case SBC_HL_HL: M_SBCW(HL);break;
+case SBC_HL_SP: M_SBCW(SP);break;
+
+case LD_xWORDe_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+case LD_xWORDe_DE:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->DE.B.l);
+  WrZ80(J.W,R->DE.B.h);
+  break;
+case LD_xWORDe_BC:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->BC.B.l);
+  WrZ80(J.W,R->BC.B.h);
+  break;
+case LD_xWORDe_SP:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->SP.B.l);
+  WrZ80(J.W,R->SP.B.h);
+  break;
+
+case LD_HL_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+case LD_DE_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->DE.B.l=RdZ80(J.W++);
+  R->DE.B.h=RdZ80(J.W);
+  break;
+case LD_BC_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->BC.B.l=RdZ80(J.W++);
+  R->BC.B.h=RdZ80(J.W);
+  break;
+case LD_SP_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->SP.B.l=RdZ80(J.W++);
+  R->SP.B.h=RdZ80(J.W);
+  break;
+
+case RRD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I>>4)|(R->AF.B.h<<4);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+case RLD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+
+case LD_A_I:
+  R->AF.B.h=R->I;
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&1? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_A_R:
+  R->R++;
+  R->AF.B.h=(byte)(R->R-R->ICount);
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&1? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_I_A:   R->I=R->AF.B.h;break;
+case LD_R_A:   break;
+
+case IM_0:     R->IFF&=0xF9;break;
+case IM_1:     R->IFF=(R->IFF&0xF9)|2;break;
+case IM_2:     R->IFF=(R->IFF&0xF9)|4;break;
+
+case RETI:     M_RET;break;
+case RETN:     if(R->IFF&0x40) R->IFF|=0x01; else R->IFF&=0xFE;
+               M_RET;break;
+
+case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+
+case IN_B_xC:  M_IN(R->BC.B.h);break;
+case IN_C_xC:  M_IN(R->BC.B.l);break;
+case IN_D_xC:  M_IN(R->DE.B.h);break;
+case IN_E_xC:  M_IN(R->DE.B.l);break;
+case IN_H_xC:  M_IN(R->HL.B.h);break;
+case IN_L_xC:  M_IN(R->HL.B.l);break;
+case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_F_xC:  M_IN(J.B.l);break;
+
+case OUT_xC_B: OutZ80(R->BC.B.l,R->BC.B.h);break;
+case OUT_xC_C: OutZ80(R->BC.B.l,R->BC.B.l);break;
+case OUT_xC_D: OutZ80(R->BC.B.l,R->DE.B.h);break;
+case OUT_xC_E: OutZ80(R->BC.B.l,R->DE.B.l);break;
+case OUT_xC_H: OutZ80(R->BC.B.l,R->HL.B.h);break;
+case OUT_xC_L: OutZ80(R->BC.B.l,R->HL.B.l);break;
+case OUT_xC_A: OutZ80(R->BC.B.l,R->AF.B.h);break;
+
+case INI:
+  WrZ80(R->HL.W++,InZ80(R->BC.B.l));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INIR:
+  do
+  {
+    WrZ80(R->HL.W++,InZ80(R->BC.B.l));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case IND:
+  WrZ80(R->HL.W--,InZ80(R->BC.B.l));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INDR:
+  do
+  {
+    WrZ80(R->HL.W--,InZ80(R->BC.B.l));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTI:
+  OutZ80(R->BC.B.l,RdZ80(R->HL.W++));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case OTIR:
+  do
+  {
+    OutZ80(R->BC.B.l,RdZ80(R->HL.W++));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTD:
+  OutZ80(R->BC.B.l,RdZ80(R->HL.W--));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case OTDR:
+  do
+  {
+    OutZ80(R->BC.B.l,RdZ80(R->HL.W--));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case LDI:
+  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+  R->BC.W--;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDIR:
+  do
+  {
+    WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case LDD:
+  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+  R->BC.W--;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDDR:
+  do
+  {
+    WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case CPI:
+  I=RdZ80(R->HL.W++);
+  J.B.l=R->AF.B.h-I;
+  R->BC.W--;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    J.B.l=R->AF.B.h-I;
+    R->BC.W--;R->ICount-=21;
+  }  
+  while(R->BC.W&&J.B.l&&(R->ICount>0));
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;  
+
+case CPD:
+  I=RdZ80(R->HL.W--);
+  J.B.l=R->AF.B.h-I;
+  R->BC.W--;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    J.B.l=R->AF.B.h-I;
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&J.B.l);
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;
diff --git a/MCUME_pico2/picocolem/CodesXCB.h b/MCUME_pico2/picocolem/CodesXCB.h
new file mode 100644
index 0000000..0b84ca2
--- /dev/null
+++ b/MCUME_pico2/picocolem/CodesXCB.h
@@ -0,0 +1,64 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXCB.h                      **/
+/**                                                         **/
+/** This file contains implementation for FD/DD-CB tables   **/
+/** of Z80 commands. It is included from Z80.c.             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
+case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
+case RL_xHL:  I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
+case RR_xHL:  I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
+case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
+case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
+case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
+case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
+
+case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
+case BIT0_H: case BIT0_L: case BIT0_A:
+case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
+case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
+case BIT1_H: case BIT1_L: case BIT1_A:
+case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
+case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
+case BIT2_H: case BIT2_L: case BIT2_A:
+case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
+case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
+case BIT3_H: case BIT3_L: case BIT3_A:
+case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
+case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
+case BIT4_H: case BIT4_L: case BIT4_A:
+case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
+case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
+case BIT5_H: case BIT5_L: case BIT5_A:
+case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
+case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
+case BIT6_H: case BIT6_L: case BIT6_A:
+case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
+case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
+case BIT7_H: case BIT7_L: case BIT7_A:
+case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
+
+case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
+case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;   
+case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;   
+case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;   
+case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;   
+case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;   
+case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;   
+case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;   
+
+case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;   
+case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break; 
+case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break; 
+case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break; 
+case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break; 
+case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break; 
+case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break; 
+case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break; 
diff --git a/MCUME_pico2/picocolem/CodesXX.h b/MCUME_pico2/picocolem/CodesXX.h
new file mode 100644
index 0000000..98733cd
--- /dev/null
+++ b/MCUME_pico2/picocolem/CodesXX.h
@@ -0,0 +1,388 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXX.h                       **/
+/**                                                         **/
+/** This file contains implementation for FD/DD tables of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:    if(R->AF.B.l&Z_FLAG)  R->PC.W++; else { M_JR; } break;
+case JR_NC:    if(R->AF.B.l&C_FLAG)  R->PC.W++; else { M_JR; } break;
+case JR_Z:     if(R->AF.B.l&Z_FLAG)  { M_JR; } else R->PC.W++; break;
+case JR_C:     if(R->AF.B.l&C_FLAG)  { M_JR; } else R->PC.W++; break;
+
+case JP_NZ:    if(R->AF.B.l&Z_FLAG)  R->PC.W+=2; else { M_JP; }  break;
+case JP_NC:    if(R->AF.B.l&C_FLAG)  R->PC.W+=2; else { M_JP; }  break;
+case JP_PO:    if(R->AF.B.l&P_FLAG)  R->PC.W+=2; else { M_JP; }  break;
+case JP_P:     if(R->AF.B.l&S_FLAG)  R->PC.W+=2; else { M_JP; }  break;
+case JP_Z:     if(R->AF.B.l&Z_FLAG)  { M_JP; }  else R->PC.W+=2; break;
+case JP_C:     if(R->AF.B.l&C_FLAG)  { M_JP; }  else R->PC.W+=2; break;
+case JP_PE:    if(R->AF.B.l&P_FLAG)  { M_JP; }  else R->PC.W+=2; break;
+case JP_M:     if(R->AF.B.l&S_FLAG)  { M_JP; }  else R->PC.W+=2; break;
+
+case RET_NZ:   if(!(R->AF.B.l&Z_FLAG))  { M_RET; }  break;
+case RET_NC:   if(!(R->AF.B.l&C_FLAG))  { M_RET; }  break;
+case RET_PO:   if(!(R->AF.B.l&P_FLAG))  { M_RET; }  break;
+case RET_P:    if(!(R->AF.B.l&S_FLAG))  { M_RET; }  break;
+case RET_Z:    if(R->AF.B.l&Z_FLAG)     { M_RET; }  break;
+case RET_C:    if(R->AF.B.l&C_FLAG)     { M_RET; }  break;
+case RET_PE:   if(R->AF.B.l&P_FLAG)     { M_RET; }  break;
+case RET_M:    if(R->AF.B.l&S_FLAG)     { M_RET; }  break;
+
+case CALL_NZ:  if(R->AF.B.l&Z_FLAG)  R->PC.W+=2;  else { M_CALL; } break;
+case CALL_NC:  if(R->AF.B.l&C_FLAG)  R->PC.W+=2;  else { M_CALL; } break;
+case CALL_PO:  if(R->AF.B.l&P_FLAG)  R->PC.W+=2;  else { M_CALL; } break;
+case CALL_P:   if(R->AF.B.l&S_FLAG)  R->PC.W+=2;  else { M_CALL; } break;
+case CALL_Z:   if(R->AF.B.l&Z_FLAG)  { M_CALL; } else R->PC.W+=2;  break;
+case CALL_C:   if(R->AF.B.l&C_FLAG)  { M_CALL; } else R->PC.W+=2;  break;
+case CALL_PE:  if(R->AF.B.l&P_FLAG)  { M_CALL; } else R->PC.W+=2;  break;
+case CALL_M:   if(R->AF.B.l&S_FLAG)  { M_CALL; } else R->PC.W+=2;  break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->XX.B.h);break;
+case ADD_L:    M_ADD(R->XX.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_ADD(I);break;
+case ADD_BYTE: I=RdZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->XX.B.h);break;
+case SUB_L:    M_SUB(R->XX.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_SUB(I);break;
+case SUB_BYTE: I=RdZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->XX.B.h);break;
+case AND_L:    M_AND(R->XX.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_AND(I);break;
+case AND_BYTE: I=RdZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->XX.B.h);break;
+case OR_L:     M_OR(R->XX.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_OR(I);break;
+case OR_BYTE:  I=RdZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->XX.B.h);break;
+case ADC_L:    M_ADC(R->XX.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_ADC(I);break;
+case ADC_BYTE: I=RdZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->XX.B.h);break;
+case SBC_L:    M_SBC(R->XX.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_SBC(I);break;
+case SBC_BYTE: I=RdZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->XX.B.h);break;
+case XOR_L:    M_XOR(R->XX.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_XOR(I);break;
+case XOR_BYTE: I=RdZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->XX.B.h);break;
+case CP_L:     M_CP(R->XX.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_CP(I);break;
+case CP_BYTE:  I=RdZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(XX);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->XX.W;break;
+case LD_SP_HL: R->SP.W=R->XX.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(XX,BC);break;
+case ADD_HL_DE:  M_ADDW(XX,DE);break;
+case ADD_HL_HL:  M_ADDW(XX,XX);break;
+case ADD_HL_SP:  M_ADDW(XX,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->XX.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->XX.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->XX.B.h);break;
+case DEC_L:    M_DEC(R->XX.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
+               WrZ80(R->XX.W+(offset)RdZ80(R->PC.W++),I);
+               break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->XX.B.h);break;
+case INC_L:    M_INC(R->XX.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
+               WrZ80(R->XX.W+(offset)RdZ80(R->PC.W++),I);
+               break;
+
+case RLCA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(XX);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(XX);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: OutZ80(RdZ80(R->PC.W++),R->AF.B.h);break;
+case INA:  R->AF.B.h=InZ80(RdZ80(R->PC.W++));break;
+
+case DI:   
+  R->IFF&=0xFE;
+  break;  
+case EI:
+  R->IFF|=0x01;
+  if(R->IRequest!=INT_NONE)
+  {
+    R->IFF|=0x20;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
+case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
+case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
+case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
+case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
+case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
+case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
+case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
+case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
+case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
+case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
+case LD_xHL_H: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
+case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
+case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
+case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
+case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
+case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
+case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
+case LD_xHL_L: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
+case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+
+case LD_B_BYTE:   R->BC.B.h=RdZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=RdZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=RdZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=RdZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->XX.B.h=RdZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->XX.B.l=RdZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=RdZ80(R->PC.W++);break;
+case LD_xHL_BYTE: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+                  WrZ80(J.W,RdZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->XX.B.l);
+  WrZ80(J.W,R->XX.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->XX.B.l=RdZ80(J.W++);
+  R->XX.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
+  R->XX.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
diff --git a/MCUME_pico2/picocolem/Colem.c b/MCUME_pico2/picocolem/Colem.c
new file mode 100644
index 0000000..40de9b4
--- /dev/null
+++ b/MCUME_pico2/picocolem/Colem.c
@@ -0,0 +1,971 @@
+#include "options.h"
+
+#include "Z80.h"            /* Z80 CPU emulation             */
+#include "SN76489.h"        /* SN76489 PSG emulation         */
+#include <stdlib.h>
+
+#include "emuapi.h"
+
+
+/**************************************
+* Local macros/typedef
+**************************************/
+#define WIDTH     256
+#define HEIGHT    192
+
+#define MAXSCREEN 3         /* Highest screen mode supported */
+#define NORAM     0xFF      /* Byte to be returned from      */
+                            /* non-existing pages and ports  */
+
+/***** Following are macros to be used in screen drivers *****/
+#define BigSprites    (VDP[1]&0x01)   /* Zoomed sprites      */
+#define Sprites16x16  (VDP[1]&0x02)   /* 16x16/8x8 sprites   */
+#define ScreenON      (VDP[1]&0x40)   /* Show screen         */
+
+/***************************************
+* Local procedures definition
+***************************************/
+static void snd_Reset(void);
+static void snd_Sound(int C, int F, int V);
+static void SetColor(byte N,byte R,byte G,byte B);
+static void RefreshSprites(byte Y);
+static void RefreshBorder(byte Y);
+static void RefreshLine0(byte Y);
+static void RefreshLine1(byte Y);
+static void RefreshLine2(byte Y);
+static void RefreshLine3(byte Y);
+static void RefreshScreen(void);
+static void VDPOut(byte Reg,byte Value); /* Write value into VDP */
+static void CheckSprites(void);          /* Collisions/5th spr.  */
+static void Play(int C,int F,int V);     /* Log and play sound   */
+
+/***************************************
+* Local data
+***************************************/
+static byte * XBuf=0; // = (byte *)XBuf32;
+static byte XPal[16],XPal0;
+
+
+/*** TMS9918/9928 Palette *******************************************/
+struct { byte R,G,B; } Palette[16] =
+{
+  {0x00,0x00,0x00},{0x00,0x00,0x00},{0x20,0xC0,0x20},{0x60,0xE0,0x60},
+  {0x20,0x20,0xE0},{0x40,0x60,0xE0},{0xA0,0x20,0x20},{0x40,0xC0,0xE0},
+  {0xE0,0x20,0x20},{0xE0,0x60,0x60},{0xC0,0xC0,0x20},{0xC0,0xC0,0x80},
+  {0x20,0x80,0x20},{0xC0,0x40,0xA0},{0xA0,0xA0,0xA0},{0xE0,0xE0,0xE0}
+};
+
+byte Verbose     = 1;          /* Debug msgs ON/OFF             */
+byte UPeriod     = 2;          /* Interrupts/scr. update        */
+int  VPeriod     = 60000;      /* Number of cycles per VBlank   */
+int  HPeriod     = 215;        /* Number of cycles per HBlank   */
+byte AutoA=0,AutoB=0;          /* 1: Autofire for A,B buttons   */
+byte Adam        = 0;          /* 1: Emulate Coleco Adam        */
+
+#define MEMRELOC -0x4000
+
+#define VRAMSIZE  0x4000
+#define RAMSIZE   0xC000
+	
+
+/* Main and Video RAMs           */
+//static byte * VRAM=0; //[VRAMSIZE];
+//static byte * RAM=0; //RAM[RAMSIZE];
+static byte VRAM[VRAMSIZE];
+static byte RAM[RAMSIZE];
+
+Z80 ccpu;                       /* Z80 CPU registers and state   */
+SN76489 PSG;                   /* SN76489 PSG state             */
+
+byte *ChrGen,*ChrTab,*ColTab;  /* VDP tables (screens)          */
+byte *SprGen,*SprTab;          /* VDP tables (sprites)          */
+pair WVAddr,RVAddr;            /* Storage for VRAM addresses    */
+byte VKey;                     /* VDP address latch key         */
+byte FGColor,BGColor;          /* Colors                        */
+byte ScrMode;                  /* Current screen mode           */
+byte CurLine;                  /* Current scanline              */
+byte VDP[8],VDPStatus;         /* VDP registers                 */
+
+byte JoyMode;                  /* Joystick controller mode      */
+word JoyState[2];              /* Joystick states               */
+
+/*** Screen handlers and masks for VDP table address registers ******/
+struct
+{
+  void (*Refresh)(byte Y);
+  byte R2,R3,R4,R5;
+} SCR[MAXSCREEN+1] =
+{
+  { RefreshLine0,0x7F,0x00,0x3F,0x00 },   /* SCREEN 0:TEXT 40x24    */
+  { RefreshLine1,0x7F,0xFF,0x3F,0xFF },   /* SCREEN 1:TEXT 32x24    */
+  { RefreshLine2,0x7F,0x80,0x3C,0xFF },   /* SCREEN 2:BLOCK 256x192 */
+  { RefreshLine3,0x7F,0x00,0x3F,0xFF }    /* SCREEN 3:GFX 64x48x16  */
+};
+
+/***************************************
+* Global data
+***************************************/
+static int ik;     // joypad key
+static int ihk;    // I2C keyboard key
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+/***************************************
+* Exported procedures
+***************************************/
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  //else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  //else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  //else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  //else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  //else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+void coc_Input(int click) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();  
+}
+
+void coc_Init(void)
+{
+  int J;
+
+  /* Set up the palette */
+  for(J=0;J<16;J++)
+    SetColor(J,Palette[J].R,Palette[J].G,Palette[J].B);
+
+  //if (VRAM == 0) VRAM = (byte *)emu_Malloc(VRAMSIZE);
+  //if (RAM == 0) RAM = (byte *)emu_Malloc(RAMSIZE);
+#if SINGLELINE_RENDERING
+  if (XBuf == 0) XBuf = (byte *)emu_Malloc(WIDTH);
+#else
+  if (XBuf == 0) XBuf = (byte *)emu_Malloc(WIDTH*HEIGHT);
+#endif  
+
+}
+
+int coc_Start(char * Cartridge)
+{ 
+  int *T,I,J;
+  char *P;
+
+  /*** VDP control register states: ***/
+  static byte VDPInit[8] =
+  { 0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00 };
+
+  /*** STARTUP CODE starts here: ***/
+  T=(int *)"\01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
+#ifdef LSB_FIRST
+  if(*T!=1)
+  {
+    emu_printf("********** This machine is high-endian. **********\n");
+    emu_printf("Take #define LSB_FIRST out and compile ColEm again.\n");    
+    return(0);
+  }
+#else
+  if(*T==1)
+  {
+    emu_printf("********** This machine is low-endian. **********\n");
+    emu_printf("Insert #define LSB_FIRST and compile ColEm again.\n");    
+    return(0);
+  }
+#endif
+
+  /* Calculate IPeriod from VPeriod */
+  if(UPeriod<1) UPeriod=1;
+  if(VPeriod/HPeriod<256) VPeriod=256*HPeriod;
+  ccpu.IPeriod=HPeriod;
+  ccpu.TrapBadOps=Verbose&0x04;
+  ccpu.IAutoReset=0;
+
+  memset(RAM,NORAM,RAMSIZE);
+  memset(VRAM,NORAM,VRAMSIZE);
+
+  if(Verbose) emu_printf("OK\nLoading ROMs:\nOpening COLECO.ROM...");
+  P=NULL;
+  if (emu_LoadFile(ROMSDIR "/" "coleco.rom", (unsigned char *)RAM, 0x2000) != 0x2000)
+    P="NOT FOUND OR SHORT FILE";
+ 
+  //if(P) { if(Verbose) puts(P);return(0); }
+  if(Verbose) emu_printf("OK\nOpening ROM");
+  if(Verbose) emu_printf(Cartridge);
+
+  P=NULL;
+  J= emu_LoadFile(Cartridge, (unsigned char *)RAM+0x8000+MEMRELOC, 0x8000);
+
+  if(J<0x1000) P="SHORT FILE";
+  I=RAM[0x8000+MEMRELOC];J=RAM[0x8001+MEMRELOC];
+  if( !( ((I==0x55)&&(J==0xAA))||((I==0xAA)&&(J==0x55)) ) )
+    P="INVALID IMAGE";
+
+  //if(P) { if(Verbose) puts(P);return(0); }
+  if(Verbose) emu_printf("bytes loaded\n");
+
+  if(Verbose)
+  {
+    emu_printf("Initializing CPU and System Hardware:\n");
+    //emu_printf("  VBlank = %d cycles\n  HBlank = %d cycles\n",VPeriod,HPeriod);
+  }
+
+#ifdef HAS_SND
+  snd_Reset();
+#endif  
+
+  /* Initialize VDP registers */
+  memcpy(VDP,VDPInit,sizeof(VDP));
+
+  /* Initialize internal variables */
+  VKey=1;                              /* VDP address latch key */
+  VDPStatus=0x9F;                      /* VDP status register   */
+  FGColor=BGColor=0;                   /* Fore/Background color */
+  ScrMode=0;                           /* Current screenmode    */
+  CurLine=0;                           /* Current scanline      */
+  ChrTab=ColTab=ChrGen=VRAM;           /* VDP tables (screen)   */
+  SprTab=SprGen=VRAM;                  /* VDP tables (sprites)  */
+  JoyMode=0;                           /* Joystick mode key     */
+  JoyState[0]=JoyState[1]=0xFFFF;      /* Joystick states       */
+  Reset76489(&PSG,Play);               /* Reset SN76489 PSG     */
+  Sync76489(&PSG,PSG_SYNC);            /* Make it synchronous   */
+  ResetZ80(&ccpu);                      /* Reset Z80 registers   */
+
+  if(Verbose) emu_printf("RUNNING ROM CODE...\n");
+  return(1);
+}
+
+void coc_Step(void)
+{
+  RunZ80(&ccpu);
+}
+
+void coc_Stop(void)
+{
+}
+
+
+#ifdef HAS_SND
+static void snd_Reset(void)
+{
+  emu_sndInit();
+}
+
+static void snd_Sound(int C, int F, int V)
+{
+  emu_sndPlaySound(C, V, F);
+}
+#endif
+
+/** Joysticks ************************************************/
+/** Check for keyboard events, parse them, and modify       **/
+/** joystick controller status                              **/
+/*************************************************************/
+
+void SetColor(byte N,byte R,byte G,byte B)
+{
+  unsigned char val = R;
+  XPal[N] = N; //(R&0xe0) | ((G>>3) & 0x1c) | ((B>>6) & 0x3); // RGBVAL(R,G,B); //(byte)lld_SetPaletteEntry(-1, R,G,B,0);
+  emu_SetPaletteEntry(R,G,B,N);
+}
+
+void Joysticks(void)
+{
+  int N=0;
+  word JS[2] = { 0xFFFF,0xFFFF };
+
+  int k  = ik & 0x7fff;
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+
+  //if (k & 0x8000) N = 1;
+  //else N = 0;
+
+  if(k)
+     JS[N]=(JS[N]&0xFFF0)|(k-1);
+
+  switch(hk) {
+    case 'a':
+    case 'q':
+    case '1':
+      hk = 2;
+      break;
+    case 'z':
+    case 'w':
+    case '2':
+      hk = 3;
+      break;
+    case 'e':
+    case '3':
+      hk = 4;
+      break;
+    case 'r':
+    case '4':
+      hk = 5;
+      break;
+    case 't':
+    case '5':
+      hk = 6;
+      break;
+    case 'y':
+    case '6':
+      hk = 7;
+      break;
+    case 'u':
+    case '7':
+      hk = 8;
+      break;
+    case 'i':
+    case '8':
+      hk = 9;
+      break;
+    case 'o':
+    case '9':
+      hk = 10;
+    case 'p':
+    case '0':
+      hk = 1;
+      break;
+    case '#':
+      hk = 11;
+      //emu_printf("#");
+      break;
+    case '*':
+      //emu_printf("*");
+      hk = 12;
+      break;
+    default:
+      hk = 0;
+      break;
+  };
+     
+  if(hk) {
+     JS[N]=(JS[N]&0xFFF0)|(hk-1);    
+  }
+  else {
+    JS[N]=(JS[N]&0xFFF0);
+    if ( (k & MASK_JOY2_BTN) || (k & MASK_JOY1_BTN) )
+    {
+            JS[N]&=0xBFFF; //Fire 1
+    }
+    if (k & MASK_KEY_USER1)
+    {
+            JS[N]&=0xFFBF; //Fire 2
+    }
+    if (k & MASK_KEY_USER2)
+    {
+            JS[0]=(JS[0]&0xFFF0)|(2); //1
+    }
+    //   JS[0]=(JS[0]&0xFFF0)|(12);
+    //   JS[0]=(JS[0]&0xFFF0)|(13);
+  
+    if ( (k & MASK_JOY2_DOWN) || (k & MASK_JOY1_DOWN) )
+            JS[N]&=0xFBFF; //Down
+    if ( (k & MASK_JOY2_UP) || (k & MASK_JOY1_UP) )
+            JS[N]&=0xFEFF; //Up
+    if ( (k & MASK_JOY2_LEFT) || (k & MASK_JOY1_LEFT) )
+            JS[N]&=0xFDFF; //Right
+    if ( (k & MASK_JOY2_RIGHT) || (k & MASK_JOY1_RIGHT) )
+            JS[N]&=0xF7FF; //Left
+  
+      
+  }
+
+  JoyState[0]=JS[0];JoyState[1]=JS[1];
+}
+
+/** WrZ80() **************************************************/
+/** Z80 emulation calls this function to write byte V to    **/
+/** address A of Z80 address space.                         **/
+/*************************************************************/
+void WrZ80(register word A,register byte V)
+{
+  if((A>0x5FFF)&&(A<0x8000))
+  {
+    A&=0x03FF;
+    RAM[0x6000+A+MEMRELOC]=RAM[0x6400+A+MEMRELOC]=RAM[0x6800+A+MEMRELOC]=RAM[0x6C00+A+MEMRELOC]=
+    RAM[0x7000+A+MEMRELOC]=RAM[0x7400+A+MEMRELOC]=RAM[0x7800+A+MEMRELOC]=RAM[0x7C00+A+MEMRELOC]=V;
+  }
+}
+
+/** RdZ80() **************************************************/
+/** Z80 emulation calls this function to read a byte from   **/
+/** address A of Z80 address space. Now  moved to z80.c and **/
+/** made inlined to speed things up.                        **/
+/*************************************************************/
+
+byte RdZ80(register word A) { 
+  if ( (A>=0x6000) && (A<0x10000) )
+    return(RAM[A+MEMRELOC]); 
+  else
+    return(RAM[A]); 
+}
+
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/*************************************************************/
+void PatchZ80(Z80 *R) {}
+
+/** InZ80() **************************************************/
+/** Z80 emulation calls this function to read a byte from   **/
+/** a given I/O port.                                       **/
+/*************************************************************/
+byte InZ80(register word Port)
+{
+  static byte KeyCodes[16] =
+  {
+    0x0A,0x0D,0x07,0x0C,0x02,0x03,0x0E,0x05,
+    0x01,0x0B,0x06,0x09,0x08,0x04,0x0F,0x0F,
+  };
+
+  switch(Port&0xE0)
+  {
+
+case 0x40: /* Printer Status */
+  if(Adam&&(Port==0x40)) return(0xFF);
+  break;
+
+case 0xE0: /* Joysticks Data */
+  Port=(Port>>1)&0x01;
+  Port=JoyMode?
+    (JoyState[Port]>>8):
+    (JoyState[Port]&0xF0)|KeyCodes[JoyState[Port]&0x0F];
+  return((Port|0xB0)&0x7F);
+
+case 0xA0: /* VDP Status/Data */
+  if(Port&0x01) { Port=VDPStatus;VDPStatus&=0x5F;VKey=1; }
+  else { Port=VRAM[RVAddr.W];RVAddr.W=(RVAddr.W+1)&0x3FFF; }
+  return(Port);
+  }
+
+  /* No such port */
+  return(NORAM);
+}
+
+/** OutZ80() *************************************************/
+/** Z80 emulation calls this function to write a byte to a  **/
+/** given I/O port.                                         **/
+/*************************************************************/
+void OutZ80(register word Port,register byte Value)
+{
+  static byte SR,VR; /* Sound and VDP register storage */
+
+  switch(Port&0xE0)
+  {
+
+case 0x80: JoyMode=0;return;
+case 0xC0: JoyMode=1;return;
+case 0xE0: Write76489(&PSG,Value);return; 
+
+case 0x40:
+//  if(Adam&&(Port==0x40)) fputc(Value,PrnStream);
+  return;
+
+case 0xA0:
+  if(Port&0x01)
+    if(VKey) { VR=Value;VKey--; }
+    else
+    {
+      VKey++;
+      switch(Value&0xC0)
+      {
+        case 0x80: VDPOut(Value&0x07,VR);break;
+        case 0x40: WVAddr.B.l=VR;WVAddr.B.h=Value&0x3F;break;
+        case 0x00: RVAddr.B.l=VR;RVAddr.B.h=Value;
+      }
+    }
+  else
+    if(VKey)
+    { VRAM[WVAddr.W]=Value;WVAddr.W=(WVAddr.W+1)&0x3FFF; }
+  return;
+
+  }
+}
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts.         **/
+/*************************************************************/
+word LoopZ80(Z80 *R, int * ras)
+{
+  static byte UCount=0;
+  static byte ACount=0;
+
+  /* Next scanline */
+  CurLine=(CurLine+1)%193;
+
+  /* Refresh scanline if needed */
+  if(CurLine<192)
+  {
+    if(!UCount) {
+      (SCR[ScrMode].Refresh)(CurLine);
+#if SINGLELINE_RENDERING
+      emu_DrawLinePal16(XBuf, WIDTH, HEIGHT, CurLine);
+#else
+#endif    
+    }
+    R->IPeriod=HPeriod;
+    return(INT_NONE);
+  }
+
+  /* End of screen reached... */
+
+  /* Set IPeriod to the beginning of next screen */
+  R->IPeriod=VPeriod-HPeriod*192;
+
+  /* Check joysticks */
+  Joysticks();
+
+  /* Autofire emulation */
+  ACount=(ACount+1)&0x07;
+  if(ACount>3)
+  {
+    if(AutoA) { JoyState[0]|=0x0040;JoyState[1]|=0x0040; }
+    if(AutoB) { JoyState[0]|=0x4000;JoyState[1]|=0x4000; }
+  }
+
+
+  /* Flush any accumulated sound changes */
+  Sync76489(&PSG,PSG_FLUSH);
+    
+  /* Refresh screen if needed */
+  if(UCount) 
+    UCount--; 
+  else 
+  { 
+    UCount=UPeriod-1;
+    RefreshScreen(); 
+  }
+
+  /* Setting VDPStatus flags */
+  VDPStatus=(VDPStatus&0xDF)|0x80;
+
+  /* Checking sprites: */
+  if(ScrMode) CheckSprites();
+
+  /* If exit requested, return INT_QUIT */
+//  if(ExitNow) return(INT_QUIT);
+  *ras = 1;
+  /* Generate VDP interrupt */
+  return(VKey&&(VDP[1]&0x20)? INT_NMI:INT_NONE);
+}
+
+/** VDPOut() *************************************************/
+/** Emulator calls this function to write byte V into a VDP **/
+/** register R.                                             **/
+/*************************************************************/
+void VDPOut(register byte R,register byte V)
+{ 
+  register byte J;
+
+  switch(R)  
+  {
+    case  0: switch(((V&0x0E)>>1)|(VDP[1]&0x18))
+             {
+               case 0x10: J=0;break;
+               case 0x00: J=1;break;
+               case 0x01: J=2;break;
+               case 0x08: J=3;break;
+               default:   J=ScrMode;
+             }   
+             if(J!=ScrMode)
+             {
+               ChrTab=VRAM+((long)(VDP[2]&SCR[J].R2)<<10);
+               ChrGen=VRAM+((long)(VDP[4]&SCR[J].R4)<<11);
+               ColTab=VRAM+((long)(VDP[3]&SCR[J].R3)<<6);
+               SprTab=VRAM+((long)(VDP[5]&SCR[J].R5)<<7);
+               SprGen=VRAM+((long)VDP[6]<<11);
+               ScrMode=J;
+             }
+             break;
+    case  1: switch(((VDP[0]&0x0E)>>1)|(V&0x18))
+             {
+               case 0x10: J=0;break;
+               case 0x00: J=1;break;
+               case 0x01: J=2;break;
+               case 0x08: J=3;break;
+               default:   J=ScrMode;
+             }   
+             if(J!=ScrMode)
+             {
+               ChrTab=VRAM+((long)(VDP[2]&SCR[J].R2)<<10);
+               ChrGen=VRAM+((long)(VDP[4]&SCR[J].R4)<<11);
+               ColTab=VRAM+((long)(VDP[3]&SCR[J].R3)<<6);
+               SprTab=VRAM+((long)(VDP[5]&SCR[J].R5)<<7);
+               SprGen=VRAM+((long)VDP[6]<<11);
+               ScrMode=J;
+             }
+             break;       
+    case  2: ChrTab=VRAM+((long)(V&SCR[ScrMode].R2)<<10);break;
+    case  3: ColTab=VRAM+((long)(V&SCR[ScrMode].R3)<<6);break;
+    case  4: ChrGen=VRAM+((long)(V&SCR[ScrMode].R4)<<11);break;
+    case  5: SprTab=VRAM+((long)(V&SCR[ScrMode].R5)<<7);break;
+    case  6: V&=0x3F;SprGen=VRAM+((long)V<<11);break;
+    case  7: FGColor=V>>4;BGColor=V&0x0F;break;
+
+  }
+  VDP[R]=V;return;
+} 
+
+/** CheckSprites() *******************************************/
+/** This function is periodically called to check for the   **/
+/** sprite collisions and 5th sprite, and set appropriate   **/
+/** bits in the VDP status register.                        **/
+/*************************************************************/
+void CheckSprites(void)
+{
+  register word LS,LD;
+  register byte DH,DV,*PS,*PD,*T;
+  byte I,J,N,*S,*D;
+
+  VDPStatus=(VDPStatus&0x9F)|0x1F;
+  for(N=0,S=SprTab;(N<32)&&(S[0]!=208);N++,S+=4);
+
+  if(Sprites16x16)
+  {
+    for(J=0,S=SprTab;J<N;J++,S+=4)
+      if(S[3]&0x0F)
+        for(I=J+1,D=S+4;I<N;I++,D+=4)
+          if(D[3]&0x0F)
+          {
+            DV=S[0]-D[0];
+            if((DV<16)||(DV>240))
+            {
+              DH=S[1]-D[1];
+              if((DH<16)||(DH>240))
+              {
+                PS=SprGen+((long)(S[2]&0xFC)<<3);
+                PD=SprGen+((long)(D[2]&0xFC)<<3);
+                if(DV<16) PD+=DV; else { DV=256-DV;PS+=DV; }
+                if(DH>240) { DH=256-DH;T=PS;PS=PD;PD=T; }
+                while(DV<16)
+                {
+                  LS=((word)*PS<<8)+*(PS+16);
+                  LD=((word)*PD<<8)+*(PD+16);
+                  if(LD&(LS>>DH)) break;
+                  else { DV++;PS++;PD++; }
+                }
+                if(DV<16) { VDPStatus|=0x20;return; }
+              }
+            }
+          }
+  }
+  else
+  {
+    for(J=0,S=SprTab;J<N;J++,S+=4)
+      if(S[3]&0x0F)
+        for(I=J+1,D=S+4;I<N;I++,D+=4)
+          if(D[3]&0x0F)
+          {
+            DV=S[0]-D[0];
+            if((DV<8)||(DV>248))
+            {
+              DH=S[1]-D[1];
+              if((DH<8)||(DH>248))
+              {
+                PS=SprGen+((long)S[2]<<3);
+                PD=SprGen+((long)D[2]<<3);
+                if(DV<8) PD+=DV; else { DV=256-DV;PS+=DV; }
+                if(DH>248) { DH=256-DH;T=PS;PS=PD;PD=T; }
+                while((DV<8)&&!(*PD&(*PS>>DH))) { DV++;PS++;PD++; }
+                if(DV<8) { VDPStatus|=0x20;return; }
+              }
+            }
+          }
+  }
+}
+
+
+/** Play() ***************************************************/
+/** Log and play sound of given frequency (Hz) and volume   **/
+/** (0..255) via given channel (0..3).                      **/
+/*************************************************************/
+void Play(int C,int F,int V)
+{
+  /* Play actual sound */
+#ifdef HAS_SND  
+  snd_Sound(C,F,V);
+#endif  
+}
+
+
+/** RefreshScreen() ******************************************/
+/** Refresh screen. This function is called in the end of   **/
+/** refresh cycle to show the entire screen.                **/
+/*************************************************************/
+void RefreshScreen(void) 
+{ 
+#if SINGLELINE_RENDERING
+#else
+  emu_DrawScreen(XBuf, WIDTH, HEIGHT, WIDTH);
+#endif
+  emu_DrawVsync();  
+}
+
+/** RefreshBorder() ******************************************/
+/** This function is called from RefreshLine#() to refresh  **/
+/** the screen border.                                      **/
+/*************************************************************/
+void RefreshBorder(register byte Y)
+{
+//  if(!Y)
+//    memset(XBuf,XPal[BGColor],WIDTH*(HEIGHT-192)/2);
+//  if(Y==191)
+//    memset(XBuf+WIDTH*(HEIGHT+192)/2,XPal[BGColor],WIDTH*(HEIGHT-192)/2);  
+}
+
+/** RefreshSprites() *****************************************/
+/** This function is called from RefreshLine#() to refresh  **/
+/** sprites.                                                **/
+/*************************************************************/
+void RefreshSprites(register byte Y)
+{
+  register byte C,H;
+  register byte *P,*PT,*AT;
+  register int L,K;
+  register unsigned int M;
+
+  H=Sprites16x16? 16:8;
+  C=0;M=0;L=0;AT=SprTab-4;
+  do
+  {
+    M<<=1;AT+=4;L++;    /* Iterating through SprTab */
+    K=AT[0];            /* K = sprite Y coordinate */
+    if(K==208) break;   /* Iteration terminates if Y=208 */
+    if(K>256-H) K-=256; /* Y coordinate may be negative */
+
+    /* Mark all valid sprites with 1s, break at 4 sprites */
+    if((Y>K)&&(Y<=K+H)) { M|=1;if(++C==4) break; }
+  }
+  while(L<32);
+
+  for(;M;M>>=1,AT-=4)
+    if(M&1)
+    {
+      C=AT[3];                  /* C = sprite attributes */
+      L=C&0x80? AT[1]-32:AT[1]; /* Sprite may be shifted left by 32 */
+      C&=0x0F;                  /* C = sprite color */
+
+      if((L<256)&&(L>-H)&&C)
+      {
+        K=AT[0];                /* K = sprite Y coordinate */
+        if(K>256-H) K-=256;     /* Y coordinate may be negative */
+
+#if SINGLELINE_RENDERING
+        P=XBuf+L;
+#else
+        P=XBuf+WIDTH*(HEIGHT-192)/2+(WIDTH-256)/2+WIDTH*Y+L;
+#endif
+        PT=SprGen+((int)(H>8? AT[2]&0xFC:AT[2])<<3)+Y-K-1;
+        C=XPal[C];
+
+        /* Mask 1: clip left sprite boundary */
+        K=L>=0? 0x0FFFF:(0x10000>>-L)-1;
+        /* Mask 2: clip right sprite boundary */
+        if(L>256-H) K^=((0x00200>>(H-8))<<(L-257+H))-1;
+        /* Get and clip the sprite data */
+        K&=((int)PT[0]<<8)|(H>8? PT[16]:0x00);
+
+        /* Draw left 8 pixels of the sprite */
+        if(K&0xFF00)
+        {
+          if(K&0x8000) P[0]=C;if(K&0x4000) P[1]=C;
+          if(K&0x2000) P[2]=C;if(K&0x1000) P[3]=C;
+          if(K&0x0800) P[4]=C;if(K&0x0400) P[5]=C;
+          if(K&0x0200) P[6]=C;if(K&0x0100) P[7]=C;
+        }
+
+        /* Draw right 8 pixels of the sprite */
+        if(K&0x00FF)
+        {
+          if(K&0x0080) P[8]=C; if(K&0x0040) P[9]=C;
+          if(K&0x0020) P[10]=C;if(K&0x0010) P[11]=C;
+          if(K&0x0008) P[12]=C;if(K&0x0004) P[13]=C;
+          if(K&0x0002) P[14]=C;if(K&0x0001) P[15]=C;
+        }
+      }
+    }
+}
+
+/** RefreshLine0() *******************************************/
+/** Refresh line Y (0..191) of SCREEN0, including sprites   **/
+/** in this line.                                           **/
+/*************************************************************/
+void RefreshLine0(register byte Y)
+{
+  register byte X,K,Offset,FC,BC;
+  register byte *P,*T;
+#if SINGLELINE_RENDERING
+  P=XBuf;
+#else
+  P=XBuf+WIDTH*(HEIGHT-192)/2+WIDTH*Y;
+#endif  
+  XPal[0]=BGColor? XPal[BGColor]:XPal0;
+
+  if(!ScreenON) memset(P,XPal[BGColor],WIDTH);
+  else
+  {
+    BC=XPal[BGColor];
+    FC=XPal[FGColor];
+    T=ChrTab+(Y>>3)*40;
+    Offset=Y&0x07;
+
+    //memset(P,BC,(WIDTH-240)/2);
+    //P+=(WIDTH-240)/2;
+
+    for(X=0;X<40;X++)
+    {
+      K=ChrGen[((int)*T<<3)+Offset];
+      P[0]=K&0x80? FC:BC;P[1]=K&0x40? FC:BC;
+      P[2]=K&0x20? FC:BC;P[3]=K&0x10? FC:BC;
+      P[4]=K&0x08? FC:BC;P[5]=K&0x04? FC:BC;
+      P+=6;T++;
+    }
+
+    //memset(P,BC,(WIDTH-240)/2);
+  }
+
+  //RefreshBorder(Y);
+}
+
+/** RefreshLine1() *******************************************/
+/** Refresh line Y (0..191) of SCREEN1, including sprites   **/
+/** in this line.                                           **/
+/*************************************************************/
+void RefreshLine1(register byte Y)
+{
+  register byte X,K,Offset,FC,BC;
+  register byte *P,*T;
+
+#if SINGLELINE_RENDERING
+  P=XBuf;
+#else
+  P=XBuf+WIDTH*(HEIGHT-192)/2+WIDTH*Y;
+#endif  
+  XPal[0]=BGColor? XPal[BGColor]:XPal0;
+
+  if(!ScreenON) memset(P,XPal[BGColor],WIDTH);
+  else
+  {
+    T=ChrTab+(Y>>3)*32;
+    Offset=Y&0x07;
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    //P+=(WIDTH-256)/2;
+
+    for(X=0;X<32;X++)
+    {
+      K=*T;
+      BC=ColTab[K>>3];
+      K=ChrGen[((int)K<<3)+Offset];
+      FC=XPal[BC>>4];
+      BC=XPal[BC&0x0F];
+      P[0]=K&0x80? FC:BC;P[1]=K&0x40? FC:BC;
+      P[2]=K&0x20? FC:BC;P[3]=K&0x10? FC:BC;
+      P[4]=K&0x08? FC:BC;P[5]=K&0x04? FC:BC; 
+      P[6]=K&0x02? FC:BC;P[7]=K&0x01? FC:BC;
+      P+=8;T++;
+    }
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    RefreshSprites(Y);
+  }
+
+  RefreshBorder(Y);
+}
+
+/** RefreshLine2() *******************************************/
+/** Refresh line Y (0..191) of SCREEN2, including sprites   **/
+/** in this line.                                           **/
+/*************************************************************/
+void RefreshLine2(register byte Y)
+{
+  register byte X,K,FC,BC,Offset;
+  register byte *P,*T,*PGT,*CLT;
+  register int I;
+
+#if SINGLELINE_RENDERING
+  P=XBuf;
+#else
+  P=XBuf+WIDTH*(HEIGHT-192)/2+WIDTH*Y;
+#endif  
+  XPal[0]=BGColor? XPal[BGColor]:XPal0;
+
+  if(!ScreenON) memset(P,XPal[BGColor],WIDTH);
+  else
+  {
+    I=(int)(Y&0xC0)<<5;
+    PGT=ChrGen+I;
+    CLT=ColTab+I;
+    T=ChrTab+(Y>>3)*32;
+    Offset=Y&0x07;
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    //P+=(WIDTH-256)/2;
+
+    for(X=0;X<32;X++)
+    {
+      I=((int)*T<<3)+Offset;
+      K=PGT[I];
+      BC=CLT[I];
+      FC=XPal[BC>>4];
+      BC=XPal[BC&0x0F];
+      P[0]=K&0x80? FC:BC;P[1]=K&0x40? FC:BC;
+      P[2]=K&0x20? FC:BC;P[3]=K&0x10? FC:BC;
+      P[4]=K&0x08? FC:BC;P[5]=K&0x04? FC:BC;
+      P[6]=K&0x02? FC:BC;P[7]=K&0x01? FC:BC;
+      P+=8;T++;
+    }
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    RefreshSprites(Y);
+  }    
+
+  RefreshBorder(Y);
+}
+
+/** RefreshLine3() *******************************************/
+/** Refresh line Y (0..191) of SCREEN3, including sprites   **/
+/** in this line.                                           **/
+/*************************************************************/
+void RefreshLine3(register byte Y)
+{
+  register byte X,K,Offset;
+  register byte *P,*T;
+
+#if SINGLELINE_RENDERING
+  P=XBuf;
+#else
+  P=XBuf+WIDTH*(HEIGHT-192)/2+WIDTH*Y;
+#endif  
+  XPal[0]=BGColor? XPal[BGColor]:XPal0;
+
+  if(!ScreenON) memset(P,XPal[BGColor],WIDTH);
+  else
+  {
+    T=ChrTab+(Y>>3)*32;
+    Offset=(Y&0x1C)>>2;
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    //P+=(WIDTH-256)/2;
+
+    for(X=0;X<32;X++)
+    {
+      K=ChrGen[((int)*T<<3)+Offset];
+      P[0]=P[1]=P[2]=P[3]=XPal[K>>4];
+      P[4]=P[5]=P[6]=P[7]=XPal[K&0x0F];
+      P+=8;T++;
+    }
+
+    //memset(P,XPal[BGColor],(WIDTH-256)/2);
+    RefreshSprites(Y);
+  }
+
+  RefreshBorder(Y);
+}
diff --git a/MCUME_pico2/picocolem/Colem.h b/MCUME_pico2/picocolem/Colem.h
new file mode 100644
index 0000000..260b97c
--- /dev/null
+++ b/MCUME_pico2/picocolem/Colem.h
@@ -0,0 +1,5 @@
+extern void coc_Init(void);
+extern void coc_Start(char * CartName);
+extern void coc_Step(void);
+extern void coc_Stop(void);
+extern void coc_Input(int click);
\ No newline at end of file
diff --git a/MCUME_pico2/picocolem/SN76489.c b/MCUME_pico2/picocolem/SN76489.c
new file mode 100644
index 0000000..d359590
--- /dev/null
+++ b/MCUME_pico2/picocolem/SN76489.c
@@ -0,0 +1,98 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                        SN76489.c                        **/
+/**                                                         **/
+/** This file contains emulation for the SN76489 sound chip **/
+/** produced by Intel.                                      **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "SN76489.h"
+
+/** Reset76489() *********************************************/
+/** Reset the sound chip. The user has to provide a pointer **/
+/** to a function Sound(Channel,Freq,Volume) used to make   **/
+/** actual sound.                                           **/
+/*************************************************************/
+void Reset76489(SN76489 *D,void (*Sound)(int,int,int))
+{
+  register int J;
+
+  for(J=0;J<4;J++) D->Volume[J]=D->Freq[J]=0;
+  D->NoiseMode=D->Buf=D->Changed=0x00;
+  D->Sync=PSG_ASYNC;D->Sound=Sound;
+}
+
+/** Sync76489() **********************************************/
+/** Flush all accumulated changes by issuing Sound() calls, **/
+/** and set the synchronization on/off. The second argument **/
+/** should be PSG_SYNC, PSG_ASYNC to set/reset sync, or     **/
+/** PSG_FLUSH to leave sync mode as it is.                  **/
+/*************************************************************/
+void Sync76489(SN76489 *D,unsigned char Sync)
+{
+  register int J,I;
+
+  if(D->Sync&&D->Changed)
+  {
+    for(J=0,I=1;J<4;J++,I<<=1)
+      if(D->Changed&I)
+        D->Sound(J,D->Freq[J],D->Volume[J]);
+  }
+  D->Changed=0x00;
+  if(Sync!=PSG_FLUSH) D->Sync=Sync;
+}
+
+/** Write76489() *********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write76489(SN76489 *D,unsigned char V)
+{
+  register unsigned char N,J;
+  register long L;
+
+  switch(V&0xF0)
+  {
+    case 0xE0:
+      J=V&0x03;
+      if(J==D->NoiseMode) return;
+      switch(J)
+      {
+        case 0: D->Freq[3]=20000;break;
+        case 1: D->Freq[3]=10000;break;
+        case 2: D->Freq[3]=5000;break;
+        case 3: D->Freq[3]=D->Freq[2];break;
+      }
+      N=3;break;
+    case 0x80: case 0xA0: case 0xC0:
+      D->Buf=V;return;
+    case 0x90: case 0xB0: case 0xD0: case 0xF0:
+      N=(V-0x90)>>5;
+      J=(~V&0x0F)*16;
+      if(J==D->Volume[N]) return;
+      D->Volume[N]=J;
+      break;
+    default:
+      if(!(D->Buf&0xC0)) return;
+      N=(D->Buf-0x80)>>5;
+      L=PSG_BASE/((V&0x3F)*16+(D->Buf&0x0F)+1);
+      if(L>15000) L=0;
+      if(L==D->Freq[N]) return;
+      if((N==2)&&(D->NoiseMode==3))
+      {
+        D->Freq[3]=L;
+        if(D->Sync) D->Changed|=0x08;
+        else D->Sound(3,D->Freq[3],D->Volume[3]);
+      }
+      D->Freq[N]=L;
+      break;
+  }
+
+  if(D->Sync) D->Changed|=1<<N;
+  else D->Sound(N,D->Freq[N],D->Volume[N]);
+}
diff --git a/MCUME_pico2/picocolem/SN76489.h b/MCUME_pico2/picocolem/SN76489.h
new file mode 100644
index 0000000..552fc15
--- /dev/null
+++ b/MCUME_pico2/picocolem/SN76489.h
@@ -0,0 +1,50 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                        SN76489.c                        **/
+/**                                                         **/
+/** This file contains emulation for the SN76489 sound chip **/
+/** produced by Intel.                                      **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef SN76489_H
+#define SN76489_H
+
+#define PSG_BASE     131072    /* Base frequency for SN76489 */
+
+#define PSG_ASYNC    0         /* Asynchronous emulation     */
+#define PSG_SYNC     1         /* Synchronous emulation mode */
+#define PSG_FLUSH    2         /* Flush buffers only         */
+
+typedef struct
+{
+  int Channel,Freq[4],Volume[4],Sync;
+  unsigned char NoiseMode,Buf,Changed;
+  void (*Sound)(int,int,int);
+} SN76489;
+
+/** Reset76489() *********************************************/
+/** Reset the sound chip. The user has to provide a pointer **/
+/** to a function Sound(Channel,Freq,Volume) used to make   **/
+/** actual sound.                                           **/
+/*************************************************************/
+void Reset76489(register SN76489 *D,void (*Sound)(int,int,int));
+
+/** Sync76489() **********************************************/
+/** Flush all accumulated changes by issuing Sound() calls, **/
+/** and set the synchronization on/off. The second argument **/
+/** should be PSG_SYNC, PSG_ASYNC to set/reset sync, or     **/
+/** PSG_FLUSH to leave sync mode as it is.                  **/
+/*************************************************************/
+void Sync76489(register SN76489 *D,register unsigned char Sync);
+
+/** Write76489() *********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write76489(register SN76489 *D,register unsigned char V);
+
+#endif /* SN76489_H */
diff --git a/MCUME_pico2/picocolem/Tables.h b/MCUME_pico2/picocolem/Tables.h
new file mode 100644
index 0000000..3373adf
--- /dev/null
+++ b/MCUME_pico2/picocolem/Tables.h
@@ -0,0 +1,447 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Tables.h                       **/
+/**                                                         **/
+/** This file contains tables of used by Z80 emulation to   **/
+/** compute SIGN,ZERO, PARITY flags, and decimal correction **/
+/** There are also timing tables for Z80 opcodes. This file **/
+/** is included from Z80.c.                                 **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+static byte Cycles[256] =
+{
+   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+   8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+   7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+   7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+   5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+   5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+   5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 
+};
+
+static byte CyclesCB[256] =
+{
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 
+};
+
+static byte CyclesED[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
+  12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
+  12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
+  12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static byte CyclesXX[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
+   0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
+  19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
+};
+
+static byte CyclesXXCB[256] =
+{
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
+};
+
+static byte ZSTable[256] =
+{
+  Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
+};
+
+static byte PZSTable[256] =
+{
+  Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
+};
+
+static word DAATable[2048] =
+{
+  0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,
+  0x0808,0x090C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,
+  0x180C,0x1908,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,
+  0x282C,0x2928,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,
+  0x3828,0x392C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,
+  0x480C,0x4908,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,
+  0x5808,0x590C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,
+  0x6828,0x692C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,
+  0x782C,0x7928,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,
+  0x888C,0x8988,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,
+  0x9888,0x998C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6025,0x6121,0x6221,0x6325,0x6421,0x6525,0x6625,0x6721,
+  0x6829,0x692D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7021,0x7125,0x7225,0x7321,0x7425,0x7521,0x7621,0x7725,
+  0x782D,0x7929,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8081,0x8185,0x8285,0x8381,0x8485,0x8581,0x8681,0x8785,
+  0x888D,0x8989,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9085,0x9181,0x9281,0x9385,0x9481,0x9585,0x9685,0x9781,
+  0x9889,0x998D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA0A5,0xA1A1,0xA2A1,0xA3A5,0xA4A1,0xA5A5,0xA6A5,0xA7A1,
+  0xA8A9,0xA9AD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB0A1,0xB1A5,0xB2A5,0xB3A1,0xB4A5,0xB5A1,0xB6A1,0xB7A5,
+  0xB8AD,0xB9A9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC085,0xC181,0xC281,0xC385,0xC481,0xC585,0xC685,0xC781,
+  0xC889,0xC98D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD081,0xD185,0xD285,0xD381,0xD485,0xD581,0xD681,0xD785,
+  0xD88D,0xD989,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE0A1,0xE1A5,0xE2A5,0xE3A1,0xE4A5,0xE5A1,0xE6A1,0xE7A5,
+  0xE8AD,0xE9A9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF0A5,0xF1A1,0xF2A1,0xF3A5,0xF4A1,0xF5A5,0xF6A5,0xF7A1,
+  0xF8A9,0xF9AD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0604,0x0700,0x0808,0x090C,0x0A0C,0x0B08,0x0C0C,0x0D08,
+  0x0E08,0x0F0C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1600,0x1704,0x180C,0x1908,0x1A08,0x1B0C,0x1C08,0x1D0C,
+  0x1E0C,0x1F08,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2620,0x2724,0x282C,0x2928,0x2A28,0x2B2C,0x2C28,0x2D2C,
+  0x2E2C,0x2F28,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3624,0x3720,0x3828,0x392C,0x3A2C,0x3B28,0x3C2C,0x3D28,
+  0x3E28,0x3F2C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4600,0x4704,0x480C,0x4908,0x4A08,0x4B0C,0x4C08,0x4D0C,
+  0x4E0C,0x4F08,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5604,0x5700,0x5808,0x590C,0x5A0C,0x5B08,0x5C0C,0x5D08,
+  0x5E08,0x5F0C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6624,0x6720,0x6828,0x692C,0x6A2C,0x6B28,0x6C2C,0x6D28,
+  0x6E28,0x6F2C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7620,0x7724,0x782C,0x7928,0x7A28,0x7B2C,0x7C28,0x7D2C,
+  0x7E2C,0x7F28,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8680,0x8784,0x888C,0x8988,0x8A88,0x8B8C,0x8C88,0x8D8C,
+  0x8E8C,0x8F88,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9684,0x9780,0x9888,0x998C,0x9A8C,0x9B88,0x9C8C,0x9D88,
+  0x9E88,0x9F8C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6625,0x6721,0x6829,0x692D,0x6A2D,0x6B29,0x6C2D,0x6D29,
+  0x6E29,0x6F2D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7621,0x7725,0x782D,0x7929,0x7A29,0x7B2D,0x7C29,0x7D2D,
+  0x7E2D,0x7F29,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8681,0x8785,0x888D,0x8989,0x8A89,0x8B8D,0x8C89,0x8D8D,
+  0x8E8D,0x8F89,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9685,0x9781,0x9889,0x998D,0x9A8D,0x9B89,0x9C8D,0x9D89,
+  0x9E89,0x9F8D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA6A5,0xA7A1,0xA8A9,0xA9AD,0xAAAD,0xABA9,0xACAD,0xADA9,
+  0xAEA9,0xAFAD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB6A1,0xB7A5,0xB8AD,0xB9A9,0xBAA9,0xBBAD,0xBCA9,0xBDAD,
+  0xBEAD,0xBFA9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC685,0xC781,0xC889,0xC98D,0xCA8D,0xCB89,0xCC8D,0xCD89,
+  0xCE89,0xCF8D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD681,0xD785,0xD88D,0xD989,0xDA89,0xDB8D,0xDC89,0xDD8D,
+  0xDE8D,0xDF89,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE6A1,0xE7A5,0xE8AD,0xE9A9,0xEAA9,0xEBAD,0xECA9,0xEDAD,
+  0xEEAD,0xEFA9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF6A5,0xF7A1,0xF8A9,0xF9AD,0xFAAD,0xFBA9,0xFCAD,0xFDA9,
+  0xFEA9,0xFFAD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0046,0x0102,0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,
+  0x080A,0x090E,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x1002,0x1106,0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,
+  0x180E,0x190A,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x2022,0x2126,0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,
+  0x282E,0x292A,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x3026,0x3122,0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,
+  0x382A,0x392E,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x4002,0x4106,0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,
+  0x480E,0x490A,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x5006,0x5102,0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,
+  0x580A,0x590E,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x6026,0x6122,0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,
+  0x682A,0x692E,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x7022,0x7126,0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,
+  0x782E,0x792A,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x8082,0x8186,0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,
+  0x888E,0x898A,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x9086,0x9182,0x9282,0x9386,0x9482,0x9586,0x9686,0x9782,
+  0x988A,0x998E,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xA0A7,0xA1A3,0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,
+  0xA8AB,0xA9AF,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xB0A3,0xB1A7,0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,
+  0xB8AF,0xB9AB,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xC087,0xC183,0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,
+  0xC88B,0xC98F,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xD083,0xD187,0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,
+  0xD88F,0xD98B,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xE0A3,0xE1A7,0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,
+  0xE8AF,0xE9AB,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xF0A7,0xF1A3,0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,
+  0xF8AB,0xF9AF,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0x0047,0x0103,0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,
+  0x080B,0x090F,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x1003,0x1107,0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,
+  0x180F,0x190B,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x2023,0x2127,0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,
+  0x282F,0x292B,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x3027,0x3123,0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,
+  0x382B,0x392F,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xFABE,0xFBBA,0xFCBE,0xFDBA,0xFEBA,0xFFBE,0x0046,0x0102,
+  0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x0A1E,0x0B1A,0x0C1E,0x0D1A,0x0E1A,0x0F1E,0x1002,0x1106,
+  0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x1A1A,0x1B1E,0x1C1A,0x1D1E,0x1E1E,0x1F1A,0x2022,0x2126,
+  0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x2A3A,0x2B3E,0x2C3A,0x2D3E,0x2E3E,0x2F3A,0x3026,0x3122,
+  0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x3A3E,0x3B3A,0x3C3E,0x3D3A,0x3E3A,0x3F3E,0x4002,0x4106,
+  0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x4A1A,0x4B1E,0x4C1A,0x4D1E,0x4E1E,0x4F1A,0x5006,0x5102,
+  0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x5A1E,0x5B1A,0x5C1E,0x5D1A,0x5E1A,0x5F1E,0x6026,0x6122,
+  0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x6A3E,0x6B3A,0x6C3E,0x6D3A,0x6E3A,0x6F3E,0x7022,0x7126,
+  0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x7A3A,0x7B3E,0x7C3A,0x7D3E,0x7E3E,0x7F3A,0x8082,0x8186,
+  0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x8A9A,0x8B9E,0x8C9A,0x8D9E,0x8E9E,0x8F9A,0x9086,0x9182,
+  0x9282,0x9386,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0x9A9F,0x9B9B,0x9C9F,0x9D9B,0x9E9B,0x9F9F,0xA0A7,0xA1A3,
+  0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xAABF,0xABBB,0xACBF,0xADBB,0xAEBB,0xAFBF,0xB0A3,0xB1A7,
+  0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xBABB,0xBBBF,0xBCBB,0xBDBF,0xBEBF,0xBFBB,0xC087,0xC183,
+  0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xCA9F,0xCB9B,0xCC9F,0xCD9B,0xCE9B,0xCF9F,0xD083,0xD187,
+  0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xDA9B,0xDB9F,0xDC9B,0xDD9F,0xDE9F,0xDF9B,0xE0A3,0xE1A7,
+  0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xEABB,0xEBBF,0xECBB,0xEDBF,0xEEBF,0xEFBB,0xF0A7,0xF1A3,
+  0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0xFABF,0xFBBB,0xFCBF,0xFDBB,0xFEBB,0xFFBF,0x0047,0x0103,
+  0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x0A1F,0x0B1B,0x0C1F,0x0D1B,0x0E1B,0x0F1F,0x1003,0x1107,
+  0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x1A1B,0x1B1F,0x1C1B,0x1D1F,0x1E1F,0x1F1B,0x2023,0x2127,
+  0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x2A3B,0x2B3F,0x2C3B,0x2D3F,0x2E3F,0x2F3B,0x3027,0x3123,
+  0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F
+};
diff --git a/MCUME_pico2/picocolem/Z80.c b/MCUME_pico2/picocolem/Z80.c
new file mode 100644
index 0000000..7da58db
--- /dev/null
+++ b/MCUME_pico2/picocolem/Z80.c
@@ -0,0 +1,583 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.c                         **/
+/**                                                         **/
+/** This file contains implementation for Z80 CPU. Don't    **/
+/** forget to provide RdZ80(), WrZ80(), InZ80(), OutZ80(),  **/
+/** LoopZ80(), and PatchZ80() functions to accomodate the   **/
+/** emulated machine's architecture.                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#include "options.h"
+#include "Z80.h"
+#include "Tables.h"
+//#include <stdio.h>
+#define printf(...) 
+
+/** INLINE ***************************************************/
+/** Different compilers inline C functions differently.     **/
+/*************************************************************/
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE static
+#endif
+
+/** System-Dependent Stuff ***********************************/
+/** This is system-dependent code put here to speed things  **/
+/** up. It has to stay inlined to be fast.                  **/
+/*************************************************************/
+#ifdef COLEM
+extern byte *RAM;
+INLINE byte RdZ80(word A) { return(RAM[A]); }
+#endif
+#ifdef MG
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>13][A&0x1FFF]); }
+#endif
+#ifdef FMSX
+extern byte *RAM[],PSL[],SSLReg;
+INLINE byte RdZ80(word A)
+{
+  if(A!=0xFFFF) return(RAM[A>>13][A&0x1FFF]);
+  else return((PSL[3]==3)? ~SSLReg:RAM[7][0x1FFF]);
+}
+#endif
+
+#define S(Fl)        R->AF.B.l|=Fl
+#define R(Fl)        R->AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
+
+#define M_RLC(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+#define M_RRC(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+#define M_RL(Rg)       \
+  if(Rg&0x80)          \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+#define M_RR(Rg)       \
+  if(Rg&0x01)          \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+  
+#define M_SLA(Rg)      \
+  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+#define M_SRA(Rg)      \
+  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+
+#define M_SLL(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+#define M_SRL(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+
+#define M_BIT(Bit,Rg)  \
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|Z_FLAG))|H_FLAG|(Rg&(1<<Bit)? 0:Z_FLAG)
+
+#define M_SET(Bit,Rg) Rg|=1<<Bit
+#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
+
+#define M_POP(Rg)      \
+  R->Rg.B.l=RdZ80(R->SP.W++);R->Rg.B.h=RdZ80(R->SP.W++)
+#define M_PUSH(Rg)     \
+  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+
+#define M_CALL         \
+  J.B.l=RdZ80(R->PC.W++);J.B.h=RdZ80(R->PC.W++);         \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
+  R->PC.W=J.W
+
+#define M_JP  J.B.l=RdZ80(R->PC.W++);J.B.h=RdZ80(R->PC.W);R->PC.W=J.W
+#define M_JR  R->PC.W+=(offset)RdZ80(R->PC.W)+1
+#define M_RET R->PC.B.l=RdZ80(R->SP.W++);R->PC.B.h=RdZ80(R->SP.W++)
+
+#define M_RST(Ad)      \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad
+
+#define M_LDWORD(Rg)   \
+  R->Rg.B.l=RdZ80(R->PC.W++);R->Rg.B.h=RdZ80(R->PC.W++)
+
+#define M_ADD(Rg)      \
+  J.W=R->AF.B.h+Rg;     \
+  R->AF.B.l=            \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|                        \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  R->AF.B.h=J.B.l       
+
+#define M_SUB(Rg)      \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  R->AF.B.h=J.B.l
+
+#define M_ADC(Rg)      \
+  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|              \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_SBC(Rg)      \
+  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_CP(Rg)       \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+
+#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
+#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_IN(Rg)  Rg=InZ80(R->BC.B.l);R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+
+#define M_INC(Rg)       \
+  Rg++;                 \
+  R->AF.B.l=            \
+    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+    (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
+
+#define M_DEC(Rg)       \
+  Rg--;                 \
+  R->AF.B.l=            \
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+    (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
+
+#define M_ADDW(Rg1,Rg2) \
+  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
+  R->AF.B.l=                                             \
+    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
+  R->Rg1.W=J.W
+
+#define M_ADCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+   
+#define M_SBCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    N_FLAG|                                                    \
+    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+
+enum Codes
+{
+  NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
+  EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
+  DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
+  JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
+  JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
+  JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
+  JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
+  JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
+  LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
+  LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
+  LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
+  LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
+  LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
+  LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
+  LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
+  LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
+  ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
+  ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
+  SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
+  SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
+  AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
+  XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
+  OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
+  CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
+  RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
+  RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
+  RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
+  RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
+  RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
+  RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
+  RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
+  RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
+};
+
+enum CodesCB
+{
+  RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
+  RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
+  RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
+  RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
+  SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
+  SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
+  SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
+  SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
+  BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
+  BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
+  BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
+  BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
+  BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
+  BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
+  BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
+  BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
+  RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
+  RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
+  RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
+  RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
+  RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
+  RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
+  RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
+  RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
+  SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
+  SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
+  SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
+  SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
+  SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
+  SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
+  SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
+  SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
+};
+  
+enum CodesED
+{
+  DB_00,DB_01,DB_02,DB_03,DB_04,DB_05,DB_06,DB_07,
+  DB_08,DB_09,DB_0A,DB_0B,DB_0C,DB_0D,DB_0E,DB_0F,
+  DB_10,DB_11,DB_12,DB_13,DB_14,DB_15,DB_16,DB_17,
+  DB_18,DB_19,DB_1A,DB_1B,DB_1C,DB_1D,DB_1E,DB_1F,
+  DB_20,DB_21,DB_22,DB_23,DB_24,DB_25,DB_26,DB_27,
+  DB_28,DB_29,DB_2A,DB_2B,DB_2C,DB_2D,DB_2E,DB_2F,
+  DB_30,DB_31,DB_32,DB_33,DB_34,DB_35,DB_36,DB_37,
+  DB_38,DB_39,DB_3A,DB_3B,DB_3C,DB_3D,DB_3E,DB_3F,
+  IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
+  IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,DB_4C,RETI,DB_,LD_R_A,
+  IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,DB_54,DB_55,IM_1,LD_A_I,
+  IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,DB_5C,DB_5D,IM_2,LD_A_R,
+  IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,DB_64,DB_65,DB_66,RRD,
+  IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,DB_6C,DB_6D,DB_6E,RLD,
+  IN_F_xC,DB_71,SBC_HL_SP,LD_xWORDe_SP,DB_74,DB_75,DB_76,DB_77,
+  IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,DB_7C,DB_7D,DB_7E,DB_7F,
+  DB_80,DB_81,DB_82,DB_83,DB_84,DB_85,DB_86,DB_87,
+  DB_88,DB_89,DB_8A,DB_8B,DB_8C,DB_8D,DB_8E,DB_8F,
+  DB_90,DB_91,DB_92,DB_93,DB_94,DB_95,DB_96,DB_97,
+  DB_98,DB_99,DB_9A,DB_9B,DB_9C,DB_9D,DB_9E,DB_9F,
+  LDI,CPI,INI,OUTI,DB_A4,DB_A5,DB_A6,DB_A7,
+  LDD,CPD,IND,OUTD,DB_AC,DB_AD,DB_AE,DB_AF,
+  LDIR,CPIR,INIR,OTIR,DB_B4,DB_B5,DB_B6,DB_B7,
+  LDDR,CPDR,INDR,OTDR,DB_BC,DB_BD,DB_BE,DB_BF,
+  DB_C0,DB_C1,DB_C2,DB_C3,DB_C4,DB_C5,DB_C6,DB_C7,
+  DB_C8,DB_C9,DB_CA,DB_CB,DB_CC,DB_CD,DB_CE,DB_CF,
+  DB_D0,DB_D1,DB_D2,DB_D3,DB_D4,DB_D5,DB_D6,DB_D7,
+  DB_D8,DB_D9,DB_DA,DB_DB,DB_DC,DB_DD,DB_DE,DB_DF,
+  DB_E0,DB_E1,DB_E2,DB_E3,DB_E4,DB_E5,DB_E6,DB_E7,
+  DB_E8,DB_E9,DB_EA,DB_EB,DB_EC,DB_ED,DB_EE,DB_EF,
+  DB_F0,DB_F1,DB_F2,DB_F3,DB_F4,DB_F5,DB_F6,DB_F7,
+  DB_F8,DB_F9,DB_FA,DB_FB,DB_FC,DB_FD,DB_FE,DB_FF
+};
+
+static void CodesCB(register Z80 *R)
+{
+  register byte I;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesCB[I];
+  switch(I)
+  {
+#include "CodesCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (   
+          "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
+          (long)(R->User),RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IX    
+  J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
+          (long)(R->User),RdZ80(R->PC.W-2),RdZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesFDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IY
+  J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-2),RdZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesED(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesED[I];
+  switch(I)
+  {
+#include "CodesED.h"
+    case PFX_ED:
+      R->PC.W--;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IX
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesDDCB(R);break;
+    case HALT:
+      R->PC.W--;R->IFF|=0x80;R->ICount=0;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+static void CodesFD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IY
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesFDCB(R);break;
+    case HALT:
+      R->PC.W--;R->IFF|=0x80;R->ICount=0;break;
+    default:
+        printf
+        (
+          "Unrecognized instruction: FD %02X at PC=%04X\n",
+          RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the register struct  **/
+/** before starting execution with Z80(). It sets the       **/
+/** registers to their supposed initial values.             **/
+/*************************************************************/
+void ResetZ80(Z80 *R)
+{
+  R->PC.W=0x0000;R->SP.W=0xF000;
+  R->AF.W=R->BC.W=R->DE.W=R->HL.W=0x0000;
+  R->AF1.W=R->BC1.W=R->DE1.W=R->HL1.W=0x0000;
+  R->IX.W=R->IY.W=0x0000;
+  R->I=0x00;R->IFF=0x00;
+  R->ICount=R->IPeriod;
+  R->IRequest=INT_NONE;
+}
+
+/** ExecZ80() ************************************************/
+/** This function will execute a single Z80 opcode. It will **/
+/** then return next PC, and current register values in R.  **/
+/*************************************************************/
+word ExecZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=Cycles[I];
+  switch(I)
+  {
+#include "Codes.h"
+    case PFX_CB: CodesCB(R);break;
+    case PFX_ED: CodesED(R);break;
+    case PFX_FD: CodesFD(R);break;
+    case PFX_DD: CodesDD(R);break;
+  }
+
+  /* We are done */
+  return(R->PC.W);
+}
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(Z80 *R,word Vector)
+{
+  if((R->IFF&0x01)||(Vector==INT_NMI))
+  {
+    /* Experimental V Shouldn't disable all interrupts? */
+    R->IFF=(R->IFF&0x9E)|((R->IFF&0x01)<<6);
+    if(R->IFF&0x80) { R->PC.W++;R->IFF&=0x7F; }
+    M_PUSH(PC);
+
+    /* Automatically reset IRequest if needed */
+    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+
+    if(Vector==INT_NMI) R->PC.W=INT_NMI;
+    else
+      if(R->IFF&0x04)
+      { 
+        Vector=(Vector&0xFF)|((word)(R->I)<<8);
+        R->PC.B.l=RdZ80(Vector++);
+        R->PC.B.h=RdZ80(Vector);
+      }
+      else
+        if(R->IFF&0x02) R->PC.W=INT_IRQ;
+        else R->PC.W=Vector;
+  }
+}
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+static byte I;
+static pair J;
+
+word RunZ80(Z80 *R)
+{
+//  register byte I;
+//  register pair J;
+  int ras=0;
+ 
+  for(;;)
+  {
+//#ifdef DEBUG
+//    /* Turn tracing on when reached trap address */
+//    if(R->PC.W==R->Trap) R->Trace=1;
+//    /* Call single-step debugger, exit if requested */
+//    if(R->Trace)
+//      if(!DebugZ80(R)) return(R->PC.W);
+//#endif
+
+    I=RdZ80(R->PC.W++);
+    R->ICount-=Cycles[I];
+    switch(I)
+    {
+#include "Codes.h"
+      case PFX_CB: CodesCB(R);break;
+      case PFX_ED: CodesED(R);break;
+      case PFX_FD: CodesFD(R);break;
+      case PFX_DD: CodesDD(R);break;
+    }
+ 
+    /* If cycle counter expired... */
+    if(R->ICount<=0)
+    {
+      /* If we have come after EI, get address from IRequest */
+      /* Otherwise, get it from the loop handler             */
+      if(R->IFF&0x20)
+      {
+        J.W=R->IRequest;         /* Get pending interrupt    */
+        R->ICount+=R->IBackup-1; /* Restore the ICount       */
+        R->IFF&=0xDF;            /* Done with AfterEI state  */
+      }
+      else
+      {
+        J.W=LoopZ80(R, &ras);          /* Call periodic handler    */
+        R->ICount=R->IPeriod;    /* Reset the cycle counter  */
+        if(J.W==INT_NONE) I=R->IRequest; /* Pending int-rupt */
+      }
+
+      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
+    }
+    if (ras == 1) break;
+  }
+
+  /* Execution stopped */
+  return(R->PC.W);
+}
diff --git a/MCUME_pico2/picocolem/Z80.h b/MCUME_pico2/picocolem/Z80.h
new file mode 100644
index 0000000..2f222e4
--- /dev/null
+++ b/MCUME_pico2/picocolem/Z80.h
@@ -0,0 +1,141 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to emulation   **/
+/** of Z80 CPU.                                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-1998                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef Z80_H
+#define Z80_H
+
+                               /* Compilation options:       */
+/* #define DEBUG */            /* Compile debugging version  */
+/* #define LSB_FIRST */        /* Compile for low-endian CPU */
+/* #define MSB_FIRST */        /* Compile for hi-endian CPU  */
+
+                               /* LoopZ80() may return:      */
+#define INT_IRQ     0x0038     /* Standard RST 38h interrupt */
+#define INT_NMI     0x0066     /* Non-maskable interrupt     */
+#define INT_NONE    0xFFFF     /* No interrupt required      */
+#define INT_QUIT    0xFFFE     /* Exit the emulation         */
+
+                               /* Bits in Z80 F register:    */
+#define S_FLAG      0x80       /* 1: Result negative         */
+#define Z_FLAG      0x40       /* 1: Result is zero          */
+#define H_FLAG      0x10       /* 1: Halfcarry/Halfborrow    */
+#define P_FLAG      0x04       /* 1: Result is even          */
+#define V_FLAG      0x04       /* 1: Overflow occured        */
+#define N_FLAG      0x02       /* 1: Subtraction occured     */
+#define C_FLAG      0x01       /* 1: Carry/Borrow occured    */
+
+/** Simple Datatypes *****************************************/
+/** NOTICE: sizeof(byte)=1 and sizeof(word)=2               **/
+/*************************************************************/
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef signed char offset;
+
+/** Structured Datatypes *************************************/
+/** NOTICE: #define LSB_FIRST for machines where least      **/
+/**         signifcant byte goes first.                     **/
+/*************************************************************/
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+
+typedef struct
+{
+  pair AF,BC,DE,HL,IX,IY,PC,SP;       /* Main registers      */
+  pair AF1,BC1,DE1,HL1;               /* Shadow registers    */
+  byte IFF,I;                         /* Interrupt registers */
+  byte R;                             /* Refresh register    */
+
+  int IPeriod,ICount; /* Set IPeriod to number of CPU cycles */
+                      /* between calls to LoopZ80()          */
+  int IBackup;        /* Private, don't touch                */
+  word IRequest;      /* Set to address of pending IRQ       */
+  byte IAutoReset;    /* Set to 1 to autom. reset IRequest   */
+  byte TrapBadOps;    /* Set to 1 to warn of illegal opcodes */
+  word Trap;          /* Set Trap to address to trace from   */
+  byte Trace;         /* Set Trace=1 to start tracing        */
+  void *User;         /* Arbitrary user data (ID,RAM*,etc.)  */
+} Z80;
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the registers before **/
+/** starting execution with RunZ80(). It sets registers to  **/
+/** their initial values.                                   **/
+/*************************************************************/
+void ResetZ80(register Z80 *R);
+
+/** ExecZ80() ************************************************/
+/** This function will execute a single Z80 opcode. It will **/
+/** then return next PC, and current register values in R.  **/
+/*************************************************************/
+word ExecZ80(register Z80 *R);
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(register Z80 *R,register word Vector);
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+word RunZ80(register Z80 *R);
+
+/** RdZ80()/WrZ80() ******************************************/
+/** These functions are called when access to RAM occurs.   **/
+/** They allow to control memory access.                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void WrZ80(register word Addr,register byte Value);
+byte RdZ80(register word Addr);
+
+/** InZ80()/OutZ80() *****************************************/
+/** Z80 emulation calls these functions to read/write from  **/
+/** I/O ports. There can be 65536 I/O ports, but only first **/
+/** 256 are usually used                                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void OutZ80(register word Port,register byte Value);
+byte InZ80(register word Port);
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/** For example, it can be called to emulate BIOS calls,    **/
+/** such as disk and tape access. Replace it with an empty  **/
+/** macro for no patching.                                  **/
+/************************************ TO BE WRITTEN BY USER **/
+void PatchZ80(register Z80 *R);
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers. Emulation exits   **/
+/** if DebugZ80() returns 0.                                **/
+/*************************************************************/
+byte DebugZ80(register Z80 *R);
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts. This    **/
+/** function must return an address of the interrupt vector **/
+/** (0x0038, 0x0066, etc.) or INT_NONE for no interrupt.    **/
+/** Return INT_QUIT to exit the emulation loop.             **/
+/************************************ TO BE WRITTEN BY USER **/
+word LoopZ80(register Z80 *R, int * ras);
+
+#endif /* Z80_H */
diff --git a/MCUME_pico2/picocolem/emucfg.h b/MCUME_pico2/picocolem/emucfg.h
new file mode 100644
index 0000000..79f257d
--- /dev/null
+++ b/MCUME_pico2/picocolem/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         16
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    Coleco Emulator"
+#define ROMSDIR "coleco"
+
+#define emu_Init(ROM) {coc_Init();coc_Start(ROM);}
+#define emu_Step() {coc_Step();}
+#define emu_Input(x) {coc_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picocolem/keyboard_osd.h b/MCUME_pico2/picocolem/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/picocolem/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/picocolem/options.h b/MCUME_pico2/picocolem/options.h
new file mode 100644
index 0000000..36c1ef8
--- /dev/null
+++ b/MCUME_pico2/picocolem/options.h
@@ -0,0 +1 @@
+#define LSB_FIRST 1
diff --git a/MCUME_pico2/picocolem/picocolem.cpp b/MCUME_pico2/picocolem/picocolem.cpp
new file mode 100644
index 0000000..e81c23b
--- /dev/null
+++ b/MCUME_pico2/picocolem/picocolem.cpp
@@ -0,0 +1,191 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "Colem.h"
+}
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+    emu_init();
+
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picocolem/program_config.h b/MCUME_pico2/picocolem/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/picocolem/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/picogb/.DS_Store b/MCUME_pico2/picogb/.DS_Store
new file mode 100644
index 0000000..978e02f
Binary files /dev/null and b/MCUME_pico2/picogb/.DS_Store differ
diff --git a/MCUME_pico2/picogb/emu.cpp b/MCUME_pico2/picogb/emu.cpp
new file mode 100644
index 0000000..cb978f0
--- /dev/null
+++ b/MCUME_pico2/picogb/emu.cpp
@@ -0,0 +1,138 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+extern "C" {
+#include "minigb_apu/minigb_apu.h"
+#include "palettes/gbcolors.h"
+#include "palettes/hedley.h"
+#include "palettes/peanut_gb.h"
+}
+
+#include "flash_t.h"
+
+static uint8_t ram[32768];
+static gb_s gb;
+
+static palette_t palette16; // Colour palette
+#define RGB565_TO_RGB888(rgb565) ((((rgb565) & 0xF800) << 8) | (((rgb565) & 0x07E0) << 5) | (((rgb565) & 0x001F) << 3))
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+void gb_error(struct gb_s* gb, const enum gb_error_e gb_err, const uint16_t addr) {
+    const char* gb_err_str[4] = {
+        "UNKNOWN",
+        "INVALID OPCODE",
+        "INVALID READ",
+        "INVALID WRITE"
+    };
+    printf("Error %d occurred: %s at %04X\n.\n", gb_err, gb_err_str[gb_err], addr);
+}
+
+/**
+ * Returns a byte from the ROM file at the given address.
+ */
+uint8_t __not_in_flash_func(gb_rom_read)(struct gb_s* gb, const uint_fast32_t addr) {
+    return flash_start[addr];
+}
+
+/**
+ * Returns a byte from the cartridge RAM at the given address.
+ */
+uint8_t __not_in_flash_func(gb_cart_ram_read)(struct gb_s* gb, const uint_fast32_t addr) {
+    return ram[addr];
+}
+
+/**
+ * Writes a given byte to the cartridge RAM at the given address.
+ */
+void __not_in_flash_func(gb_cart_ram_write)(struct gb_s* gb, const uint_fast32_t addr, const uint8_t val) {
+    ram[addr] = val;
+}
+
+
+static uint8_t tmppixels[LCD_WIDTH];
+
+/**
+ * Draws scanline into framebuffer.
+ */
+void __always_inline lcd_draw_line(struct gb_s* gb, const unsigned char  *pixels, const uint_fast8_t y) {
+    if (gb->cgb.cgbMode) {
+        emu_DrawLinePal16((unsigned char *)&pixels[0], 160, 128, y);
+    }
+    else 
+    {       
+        for (unsigned int x = 0; x < LCD_WIDTH; x++)
+            tmppixels[x] = pixels[x] & 3; //(pixels[x] & LCD_PALETTE_ALL) >> 4;
+        emu_DrawLinePal16((unsigned char *)&tmppixels[0], 160, 128, y); 
+    }
+}
+
+void gbc_Init(void)
+{
+  emu_printf("gbc_Init");   
+  emu_printf("gbc_Init done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void gbc_Input(int click) {
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();    
+}
+
+
+void gbc_Start(char * filename)
+{
+  emu_printf("gbc_Start");
+
+  int size = flash_load(filename);
+
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND  
+  emu_sndInit();
+#endif  
+#else
+#endif
+  /* Initialise GB context. */
+  gb_init_error_e ret = gb_init(&gb, &gb_rom_read, &gb_cart_ram_read,
+                                &gb_cart_ram_write, &gb_error, nullptr);
+
+  auto_assign_palette(palette16, gb_colour_hash(&gb), gb_get_rom_name(&gb, filename));
+  //manual_assign_palette(palette16, 0);
+
+  for (int i = 0; i < 3; i++)
+      for (int j = 0; j < 4; j++) {
+          uint32_t val = RGB565_TO_RGB888(palette16[i][j]);
+          emu_SetPaletteEntry(val>>16, (val>>8) & 0xff, val & 0xff, i * 4 + j);
+      }
+
+  gb_init_lcd(&gb, &lcd_draw_line);  
+  emu_printf("gbc_Start done");
+}
+
+void gbc_Step(void) {
+  gb_run_frame(&gb);
+  gb.direct.joypad_bits.up = !(( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP));
+  gb.direct.joypad_bits.down = !(( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN));
+  gb.direct.joypad_bits.right = !(( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT));
+  gb.direct.joypad_bits.left = !(( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT));
+  gb.direct.joypad_bits.a = !(k & MASK_KEY_USER3);
+  gb.direct.joypad_bits.b = !(k & MASK_JOY2_BTN);
+  gb.direct.joypad_bits.select = !(k & MASK_KEY_USER1);
+  gb.direct.joypad_bits.start = !(k & MASK_KEY_USER2);
+
+  emu_DrawVsync();   
+}
+
+void SND_Process(void *stream, int len) {
+//  psg_update((int16*)stream, 0, len);  
+} 
diff --git a/MCUME_pico2/picogb/emu.h b/MCUME_pico2/picogb/emu.h
new file mode 100644
index 0000000..dd39b1b
--- /dev/null
+++ b/MCUME_pico2/picogb/emu.h
@@ -0,0 +1,5 @@
+extern void gbc_Init(void);
+extern void gbc_Step(void);
+extern void gbc_Start(char * filename);
+extern void gbc_Input(int click);
+
diff --git a/MCUME_pico2/picogb/emucfg.h b/MCUME_pico2/picogb/emucfg.h
new file mode 100644
index 0000000..7490734
--- /dev/null
+++ b/MCUME_pico2/picogb/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         64
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    Gameboy Emulator"
+#define ROMSDIR "gameboy"
+
+#define emu_Init(ROM) {gbc_Init(); gbc_Start(ROM);}
+#define emu_Step(x) {gbc_Step();}
+#define emu_Input(x) {gbc_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picogb/keyboard_osd.h b/MCUME_pico2/picogb/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picogb/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picogb/minigb_apu/LICENSE b/MCUME_pico2/picogb/minigb_apu/LICENSE
new file mode 100755
index 0000000..af254b2
--- /dev/null
+++ b/MCUME_pico2/picogb/minigb_apu/LICENSE
@@ -0,0 +1,20 @@
+Copyright (c) 2017 Alex Baines <alex@abaines.me.uk>
+Copyright (c) 2019 Mahyar Koshkouei <mk@deltabeard.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/MCUME_pico2/picogb/minigb_apu/minigb_apu.c b/MCUME_pico2/picogb/minigb_apu/minigb_apu.c
new file mode 100755
index 0000000..5f44507
--- /dev/null
+++ b/MCUME_pico2/picogb/minigb_apu/minigb_apu.c
@@ -0,0 +1,602 @@
+/**
+ * minigb_apu is released under the terms listed within the LICENSE file.
+ *
+ * minigb_apu emulates the audio processing unit (APU) of the Game Boy. This
+ * project is based on MiniGBS by Alex Baines: https://github.com/baines/MiniGBS
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "minigb_apu.h"
+
+#define DMG_CLOCK_FREQ_U	((unsigned)DMG_CLOCK_FREQ)
+#define AUDIO_NSAMPLES		(AUDIO_SAMPLES * 2u)
+
+#define AUDIO_MEM_SIZE		(0xFF3F - 0xFF10 + 1)
+#define AUDIO_ADDR_COMPENSATION	0xFF10
+
+#define MAX(a, b)		( a > b ? a : b )
+#define MIN(a, b)		( a <= b ? a : b )
+
+#define VOL_INIT_MAX		(INT16_MAX/8)
+#define VOL_INIT_MIN		(INT16_MIN/8)
+
+/* Handles time keeping for sound generation.
+ * FREQ_INC_REF must be equal to, or larger than AUDIO_SAMPLE_RATE in order
+ * to avoid a division by zero error.
+ * Using a square of 2 simplifies calculations. */
+#define FREQ_INC_REF		(AUDIO_SAMPLE_RATE * 16)
+
+#define MAX_CHAN_VOLUME		15
+
+/**
+ * Memory holding audio registers between 0xFF10 and 0xFF3F inclusive.
+ */
+static uint8_t audio_mem[AUDIO_MEM_SIZE];
+
+struct chan_len_ctr {
+	uint8_t load;
+	unsigned enabled : 1;
+	uint32_t counter;
+	uint32_t inc;
+};
+
+struct chan_vol_env {
+	uint8_t step;
+	unsigned up : 1;
+	uint32_t counter;
+	uint32_t inc;
+};
+
+struct chan_freq_sweep {
+	uint16_t freq;
+	uint8_t rate;
+	uint8_t shift;
+	unsigned up : 1;
+	uint32_t counter;
+	uint32_t inc;
+};
+
+static struct chan {
+	unsigned enabled : 1;
+	unsigned powered : 1;
+	unsigned on_left : 1;
+	unsigned on_right : 1;
+	unsigned muted : 1;
+
+	uint8_t volume;
+	uint8_t volume_init;
+
+	uint16_t freq;
+	uint32_t freq_counter;
+	uint32_t freq_inc;
+
+	int_fast16_t val;
+
+	struct chan_len_ctr    len;
+	struct chan_vol_env    env;
+	struct chan_freq_sweep sweep;
+
+	union {
+		struct {
+			uint8_t duty;
+			uint8_t duty_counter;
+		} square;
+		struct {
+			uint16_t lfsr_reg;
+			uint8_t  lfsr_wide;
+			uint8_t  lfsr_div;
+		} noise;
+		struct {
+			uint8_t sample;
+		} wave;
+	};
+} chans[4];
+
+static int32_t vol_l, vol_r;
+
+static void set_note_freq(struct chan *c, const uint32_t freq)
+{
+	/* Lowest expected value of freq is 64. */
+	c->freq_inc = freq * (uint32_t)(FREQ_INC_REF / AUDIO_SAMPLE_RATE);
+}
+
+static void chan_enable(const uint_fast8_t i, const bool enable)
+{
+	uint8_t val;
+
+	chans[i].enabled = enable;
+	val = (audio_mem[0xFF26 - AUDIO_ADDR_COMPENSATION] & 0x80) |
+		(chans[3].enabled << 3) | (chans[2].enabled << 2) |
+		(chans[1].enabled << 1) | (chans[0].enabled << 0);
+
+	audio_mem[0xFF26 - AUDIO_ADDR_COMPENSATION] = val;
+	//audio_mem[0xFF26 - AUDIO_ADDR_COMPENSATION] |= 0x80 | ((uint8_t)enable) << i;
+}
+
+static void update_env(struct chan *c)
+{
+	c->env.counter += c->env.inc;
+
+	while (c->env.counter > FREQ_INC_REF) {
+		if (c->env.step) {
+			c->volume += c->env.up ? 1 : -1;
+			if (c->volume == 0 || c->volume == MAX_CHAN_VOLUME) {
+				c->env.inc = 0;
+			}
+			c->volume = MAX(0, MIN(MAX_CHAN_VOLUME, c->volume));
+		}
+		c->env.counter -= FREQ_INC_REF;
+	}
+}
+
+static void update_len(struct chan *c)
+{
+	if (!c->len.enabled)
+		return;
+
+	c->len.counter += c->len.inc;
+	if (c->len.counter > FREQ_INC_REF) {
+		chan_enable(c - chans, 0);
+		c->len.counter = 0;
+	}
+}
+
+static bool update_freq(struct chan *c, uint32_t *pos)
+{
+	uint32_t inc = c->freq_inc - *pos;
+	c->freq_counter += inc;
+
+	if (c->freq_counter > FREQ_INC_REF) {
+		*pos		= c->freq_inc - (c->freq_counter - FREQ_INC_REF);
+		c->freq_counter = 0;
+		return true;
+	} else {
+		*pos = c->freq_inc;
+		return false;
+	}
+}
+
+static void update_sweep(struct chan *c)
+{
+	c->sweep.counter += c->sweep.inc;
+
+	while (c->sweep.counter > FREQ_INC_REF) {
+		if (c->sweep.shift) {
+			uint16_t inc = (c->sweep.freq >> c->sweep.shift);
+			if (!c->sweep.up)
+				inc *= -1;
+
+			c->freq += inc;
+			if (c->freq > 2047) {
+				c->enabled = 0;
+			} else {
+				set_note_freq(c,
+					DMG_CLOCK_FREQ_U / ((2048 - c->freq)<< 5));
+				c->freq_inc *= 8;
+			}
+		} else if (c->sweep.rate) {
+			c->enabled = 0;
+		}
+		c->sweep.counter -= FREQ_INC_REF;
+	}
+}
+
+static void update_square(int16_t* samples, const bool ch2)
+{
+	uint32_t freq;
+	struct chan* c = chans + ch2;
+
+	if (!c->powered || !c->enabled)
+		return;
+
+	freq = DMG_CLOCK_FREQ_U / ((2048 - c->freq) << 5);
+	set_note_freq(c, freq);
+	c->freq_inc *= 8;
+
+	for (uint_fast16_t i = 0; i < AUDIO_NSAMPLES; i += 2) {
+		update_len(c);
+
+		if (!c->enabled)
+			continue;
+
+		update_env(c);
+		if (!ch2)
+			update_sweep(c);
+
+		uint32_t pos = 0;
+		uint32_t prev_pos = 0;
+		int32_t sample = 0;
+
+		while (update_freq(c, &pos)) {
+			c->square.duty_counter = (c->square.duty_counter + 1) & 7;
+			sample += ((pos - prev_pos) / c->freq_inc) * c->val;
+			c->val = (c->square.duty & (1 << c->square.duty_counter)) ?
+				VOL_INIT_MAX / MAX_CHAN_VOLUME :
+				VOL_INIT_MIN / MAX_CHAN_VOLUME;
+			prev_pos = pos;
+		}
+
+		if (c->muted)
+			continue;
+
+		sample += c->val;
+		sample *= c->volume;
+		sample /= 4;
+
+		samples[i + 0] += sample * c->on_left * vol_l;
+		samples[i + 1] += sample * c->on_right * vol_r;
+	}
+}
+
+static uint8_t wave_sample(const unsigned int pos, const unsigned int volume)
+{
+	uint8_t sample;
+
+	sample =  audio_mem[(0xFF30 + pos / 2) - AUDIO_ADDR_COMPENSATION];
+	if (pos & 1) {
+		sample &= 0xF;
+	} else {
+		sample >>= 4;
+	}
+	return volume ? (sample >> (volume - 1)) : 0;
+}
+
+static void update_wave(int16_t *samples)
+{
+	uint32_t freq;
+	struct chan *c = chans + 2;
+
+	if (!c->powered || !c->enabled)
+		return;
+
+	freq = (DMG_CLOCK_FREQ_U / 64) / (2048 - c->freq);
+	set_note_freq(c, freq);
+
+	c->freq_inc *= 32;
+
+	for (uint_fast16_t i = 0; i < AUDIO_NSAMPLES; i += 2) {
+		update_len(c);
+
+		if (!c->enabled)
+			continue;
+
+		uint32_t pos      = 0;
+		uint32_t prev_pos = 0;
+		int32_t sample   = 0;
+
+		c->wave.sample = wave_sample(c->val, c->volume);
+
+		while (update_freq(c, &pos)) {
+			c->val = (c->val + 1) & 31;
+			sample += ((pos - prev_pos) / c->freq_inc) *
+				((int)c->wave.sample - 8) * (INT16_MAX/64);
+			c->wave.sample = wave_sample(c->val, c->volume);
+			prev_pos  = pos;
+		}
+
+		sample += ((int)c->wave.sample - 8) * (int)(INT16_MAX/64);
+
+		if (c->volume == 0)
+			continue;
+
+		{
+			/* First element is unused. */
+			int16_t div[] = { INT16_MAX, 1, 2, 4 };
+			sample = sample / (div[c->volume]);
+		}
+
+		if (c->muted)
+			continue;
+
+		sample /= 4;
+
+		samples[i + 0] += sample * c->on_left * vol_l;
+		samples[i + 1] += sample * c->on_right * vol_r;
+	}
+}
+
+static void update_noise(int16_t *samples)
+{
+	struct chan *c = chans + 3;
+
+	if (!c->powered)
+		return;
+
+	{
+		const uint32_t lfsr_div_lut[] = {
+			8, 16, 32, 48, 64, 80, 96, 112
+		};
+		uint32_t freq;
+
+		freq = DMG_CLOCK_FREQ_U / (lfsr_div_lut[c->noise.lfsr_div] << c->freq);
+		set_note_freq(c, freq);
+	}
+
+	if (c->freq >= 14)
+		c->enabled = 0;
+
+	for (uint_fast16_t i = 0; i < AUDIO_NSAMPLES; i += 2) {
+		update_len(c);
+
+		if (!c->enabled)
+			continue;
+
+		update_env(c);
+
+		uint32_t pos      = 0;
+		uint32_t prev_pos = 0;
+		int32_t sample    = 0;
+
+		while (update_freq(c, &pos)) {
+			c->noise.lfsr_reg = (c->noise.lfsr_reg << 1) |
+				(c->val >= VOL_INIT_MAX/MAX_CHAN_VOLUME);
+
+			if (c->noise.lfsr_wide) {
+				c->val = !(((c->noise.lfsr_reg >> 14) & 1) ^
+						((c->noise.lfsr_reg >> 13) & 1)) ?
+					VOL_INIT_MAX / MAX_CHAN_VOLUME :
+					VOL_INIT_MIN / MAX_CHAN_VOLUME;
+			} else {
+				c->val = !(((c->noise.lfsr_reg >> 6) & 1) ^
+						((c->noise.lfsr_reg >> 5) & 1)) ?
+					VOL_INIT_MAX / MAX_CHAN_VOLUME :
+					VOL_INIT_MIN / MAX_CHAN_VOLUME;
+			}
+
+			sample += ((pos - prev_pos) / c->freq_inc) * c->val;
+			prev_pos = pos;
+		}
+
+		if (c->muted)
+			continue;
+
+		sample += c->val;
+		sample *= c->volume;
+		sample /= 4;
+
+		samples[i + 0] += sample * c->on_left * vol_l;
+		samples[i + 1] += sample * c->on_right * vol_r;
+	}
+}
+
+/**
+ * SDL2 style audio callback function.
+ */
+void audio_callback(void *userdata, int16_t *stream, size_t len)
+{
+	/* Appease unused variable warning. */
+	(void)userdata;
+
+	memset(stream, 0, len);
+
+	update_square(stream, 0);
+	update_square(stream, 1);
+	update_wave(stream);
+	update_noise(stream);
+}
+
+static void chan_trigger(uint_fast8_t i)
+{
+	struct chan *c = chans + i;
+
+	chan_enable(i, 1);
+	c->volume = c->volume_init;
+
+	// volume envelope
+	{
+		uint8_t val =
+			audio_mem[(0xFF12 + (i * 5)) - AUDIO_ADDR_COMPENSATION];
+
+		c->env.step = val & 0x07;
+		c->env.up   = val & 0x08 ? 1 : 0;
+		c->env.inc  = c->env.step ?
+			(FREQ_INC_REF * 64ul) / ((uint32_t)c->env.step * AUDIO_SAMPLE_RATE) :
+			(8ul * FREQ_INC_REF) / AUDIO_SAMPLE_RATE ;
+		c->env.counter = 0;
+	}
+
+	// freq sweep
+	if (i == 0) {
+		uint8_t val = audio_mem[0xFF10 - AUDIO_ADDR_COMPENSATION];
+
+		c->sweep.freq  = c->freq;
+		c->sweep.rate  = (val >> 4) & 0x07;
+		c->sweep.up    = !(val & 0x08);
+		c->sweep.shift = (val & 0x07);
+		c->sweep.inc   = c->sweep.rate ?
+			((128 * FREQ_INC_REF) / (c->sweep.rate * AUDIO_SAMPLE_RATE)) : 0;
+		c->sweep.counter = FREQ_INC_REF;
+	}
+
+	int len_max = 64;
+
+	if (i == 2) { // wave
+		len_max = 256;
+		c->val = 0;
+	} else if (i == 3) { // noise
+		c->noise.lfsr_reg = 0xFFFF;
+		c->val = VOL_INIT_MIN / MAX_CHAN_VOLUME;
+	}
+
+	c->len.inc = (256 * FREQ_INC_REF) / (AUDIO_SAMPLE_RATE * (len_max - c->len.load));
+	c->len.counter = 0;
+}
+
+/**
+ * Read audio register.
+ * \param addr	Address of audio register. Must be 0xFF10 <= addr <= 0xFF3F.
+ *				This is not checked in this function.
+ * \return	Byte at address.
+ */
+uint8_t audio_read(const uint16_t addr)
+{
+	static const uint8_t ortab[] = {
+		0x80, 0x3f, 0x00, 0xff, 0xbf,
+		0xff, 0x3f, 0x00, 0xff, 0xbf,
+		0x7f, 0xff, 0x9f, 0xff, 0xbf,
+		0xff, 0xff, 0x00, 0x00, 0xbf,
+		0x00, 0x00, 0x70,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+	};
+
+	return audio_mem[addr - AUDIO_ADDR_COMPENSATION] |
+		ortab[addr - AUDIO_ADDR_COMPENSATION];
+}
+
+/**
+ * Write audio register.
+ * \param addr	Address of audio register. Must be 0xFF10 <= addr <= 0xFF3F.
+ *				This is not checked in this function.
+ * \param val	Byte to write at address.
+ */
+void audio_write(const uint16_t addr, const uint8_t val)
+{
+	/* Find sound channel corresponding to register address. */
+	uint_fast8_t i;
+
+	if(addr == 0xFF26)
+	{
+		audio_mem[addr - AUDIO_ADDR_COMPENSATION] = val & 0x80;
+		/* On APU power off, clear all registers apart from wave
+		 * RAM. */
+		if((val & 0x80) == 0)
+		{
+			memset(audio_mem, 0x00, 0xFF26 - AUDIO_ADDR_COMPENSATION);
+			chans[0].enabled = false;
+			chans[1].enabled = false;
+			chans[2].enabled = false;
+			chans[3].enabled = false;
+		}
+
+		return;
+	}
+
+	/* Ignore register writes if APU powered off. */
+	if(audio_mem[0xFF26 - AUDIO_ADDR_COMPENSATION] == 0x00)
+		return;
+
+	audio_mem[addr - AUDIO_ADDR_COMPENSATION] = val;
+	i = (addr - AUDIO_ADDR_COMPENSATION) / 5;
+
+	switch (addr) {
+	case 0xFF12:
+	case 0xFF17:
+	case 0xFF21: {
+		chans[i].volume_init = val >> 4;
+		chans[i].powered     = (val >> 3) != 0;
+
+		// "zombie mode" stuff, needed for Prehistorik Man and probably
+		// others
+		if (chans[i].powered && chans[i].enabled) {
+			if ((chans[i].env.step == 0 && chans[i].env.inc != 0)) {
+				if (val & 0x08) {
+					chans[i].volume++;
+				} else {
+					chans[i].volume += 2;
+				}
+			} else {
+				chans[i].volume = 16 - chans[i].volume;
+			}
+
+			chans[i].volume &= 0x0F;
+			chans[i].env.step = val & 0x07;
+		}
+	} break;
+
+	case 0xFF1C:
+		chans[i].volume = chans[i].volume_init = (val >> 5) & 0x03;
+		break;
+
+	case 0xFF11:
+	case 0xFF16:
+	case 0xFF20: {
+		const uint8_t duty_lookup[] = { 0x10, 0x30, 0x3C, 0xCF };
+		chans[i].len.load = val & 0x3f;
+		chans[i].square.duty = duty_lookup[val >> 6];
+		break;
+	}
+
+	case 0xFF1B:
+		chans[i].len.load = val;
+		break;
+
+	case 0xFF13:
+	case 0xFF18:
+	case 0xFF1D:
+		chans[i].freq &= 0xFF00;
+		chans[i].freq |= val;
+		break;
+
+	case 0xFF1A:
+		chans[i].powered = (val & 0x80) != 0;
+		chan_enable(i, val & 0x80);
+		break;
+
+	case 0xFF14:
+	case 0xFF19:
+	case 0xFF1E:
+		chans[i].freq &= 0x00FF;
+		chans[i].freq |= ((val & 0x07) << 8);
+		/* Intentional fall-through. */
+	case 0xFF23:
+		chans[i].len.enabled = val & 0x40 ? 1 : 0;
+		if (val & 0x80)
+			chan_trigger(i);
+
+		break;
+
+	case 0xFF22:
+		chans[3].freq = val >> 4;
+		chans[3].noise.lfsr_wide = !(val & 0x08);
+		chans[3].noise.lfsr_div = val & 0x07;
+		break;
+
+	case 0xFF24:
+	{
+		vol_l = ((val >> 4) & 0x07);
+		vol_r = (val & 0x07);
+		break;
+	}
+
+	case 0xFF25:
+		for (uint_fast8_t j = 0; j < 4; j++) {
+			chans[j].on_left  = (val >> (4 + j)) & 1;
+			chans[j].on_right = (val >> j) & 1;
+		}
+		break;
+	}
+}
+
+void audio_init(void)
+{
+	/* Initialise channels and samples. */
+	memset(chans, 0, sizeof(chans));
+	chans[0].val = chans[1].val = -1;
+
+	/* Initialise IO registers. */
+	{
+		const uint8_t regs_init[] = { 0x80, 0xBF, 0xF3, 0xFF, 0x3F,
+					      0xFF, 0x3F, 0x00, 0xFF, 0x3F,
+					      0x7F, 0xFF, 0x9F, 0xFF, 0x3F,
+					      0xFF, 0xFF, 0x00, 0x00, 0x3F,
+					      0x77, 0xF3, 0xF1 };
+
+		for(uint_fast8_t i = 0; i < sizeof(regs_init); ++i)
+			audio_write(0xFF10 + i, regs_init[i]);
+	}
+
+	/* Initialise Wave Pattern RAM. */
+	{
+		const uint8_t wave_init[] = { 0xac, 0xdd, 0xda, 0x48,
+					      0x36, 0x02, 0xcf, 0x16,
+					      0x2c, 0x04, 0xe5, 0x2c,
+					      0xac, 0xdd, 0xda, 0x48 };
+
+		for(uint_fast8_t i = 0; i < sizeof(wave_init); ++i)
+			audio_write(0xFF30 + i, wave_init[i]);
+	}
+}
diff --git a/MCUME_pico2/picogb/minigb_apu/minigb_apu.h b/MCUME_pico2/picogb/minigb_apu/minigb_apu.h
new file mode 100755
index 0000000..d8eabd0
--- /dev/null
+++ b/MCUME_pico2/picogb/minigb_apu/minigb_apu.h
@@ -0,0 +1,47 @@
+/**
+ * minigb_apu is released under the terms listed within the LICENSE file.
+ *
+ * minigb_apu emulates the audio processing unit (APU) of the Game Boy. This
+ * project is based on MiniGBS by Alex Baines: https://github.com/baines/MiniGBS
+ */
+
+#pragma once
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define AUDIO_SAMPLE_RATE	44100
+
+#define DMG_CLOCK_FREQ		4194304.0
+#define SCREEN_REFRESH_CYCLES	70224.0
+#define VERTICAL_SYNC		(DMG_CLOCK_FREQ/SCREEN_REFRESH_CYCLES)
+
+#define AUDIO_SAMPLES		((unsigned)(AUDIO_SAMPLE_RATE / VERTICAL_SYNC))
+#define AUDIO_BUFFER_SIZE_BYTES (AUDIO_SAMPLES*4)
+
+/**
+ * Fill allocated buffer "data" with "len" number of 32-bit floating point
+ * samples (native endian order) in stereo interleaved format.
+ */
+void audio_callback(void *ptr, int16_t *data, size_t len);
+
+/**
+ * Read audio register at given address "addr".
+ */
+uint8_t audio_read(const uint16_t addr);
+
+/**
+ * Write "val" to audio register at given address "addr".
+ */
+void audio_write(const uint16_t addr, const uint8_t val);
+
+/**
+ * Initialise audio driver.
+ */
+void audio_init(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/MCUME_pico2/picogb/palettes/gbcolors.h b/MCUME_pico2/picogb/palettes/gbcolors.h
new file mode 100755
index 0000000..4d2250e
--- /dev/null
+++ b/MCUME_pico2/picogb/palettes/gbcolors.h
@@ -0,0 +1,1354 @@
+/**
+ * MIT License
+ *
+ * Copyright (c) 2022 Vincent Mistler
+ * Original source code from deltabeard/Peanut-GB Copyright (c) 2018 Mahyar Koshkouei
+ * https://github.com/deltabeard/Peanut-GB/blob/master/examples/sdl2/peanut_sdl.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#define NUMBER_OF_MANUAL_PALETTES 13
+#define PALETTE_SIZE_IN_BYTES (3 * 4 * sizeof(uint16_t))
+
+typedef uint16_t palette_t[3][4];
+
+/*
+ * Get an RGB565 colour palette by entry ID & shuffling flags
+ * 
+ * A total of 51 unique palette configurations are in here. 
+ * 45 are known to be used by some games (6 of which are shared with
+ * manual palette selection), and 6 are unique to manual palette selection
+ * 
+ * Palettes configurations from The Cutting Room Floor
+ * https://tcrf.net/Game_Boy_Color_Bootstrap_ROM
+ */
+void get_colour_palette(palette_t selected_palette,uint8_t table_entry,uint8_t shuffling_flags)
+{
+	printf("I get_colour_palette(table_entry=0x%02X,shuffling_flags=0x%02X)\n",
+		table_entry,
+		shuffling_flags);
+	if(table_entry==0x00 && shuffling_flags==0x01)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFB80, 0x9200, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xAD70, 0x438F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xAD70, 0x438F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x00 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFB80, 0x9200, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFB80, 0x9200, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xAD70, 0x438F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x00 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFB80, 0x9200, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x5DFF, 0xF800, 0x001F }, /* OBJ1 */
+			{ 0xFFFF, 0xAD70, 0x438F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x01 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFE28, 0xFEA0, 0x91C0, 0x4800 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFF3, 0x95BF, 0x64AE, 0x01C7 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x02 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFFFF, 0x653F, 0x001F }, /* OBJ0 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ1 */
+			{ 0x6FE0, 0xFFFF, 0xFA89, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x03 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFFFF, 0x653F, 0x001F }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0x56E0, 0xFC20, 0xFFE0, 0xFFFF }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x04 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x7FE0, 0xB380, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x05 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x05 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x05 && shuffling_flags==0x04)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x5DFF, 0xF800, 0x001F }, /* OBJ1 */
+			{ 0xFFFF, 0x57E0, 0xFA00, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x06 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x06 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x06 && shuffling_flags==0x04)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x5DFF, 0xF800, 0x001F }, /* OBJ1 */
+			{ 0xFFFF, 0xFCE0, 0xF800, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x07 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFFE0, 0xF800, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFFE0, 0xF800, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFFE0, 0xF800, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x07 && shuffling_flags==0x04)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFFE0, 0xF800, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x5DFF, 0xF800, 0x001F }, /* OBJ1 */
+			{ 0xFFFF, 0xFFE0, 0xF800, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x08 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xA4FF, 0xFFE0, 0x0300, 0x0000 }, /* OBJ0 */
+			{ 0xA4FF, 0xFFE0, 0x0300, 0x0000 }, /* OBJ1 */
+			{ 0xA4FF, 0xFFE0, 0x0300, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x08 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFB0A, 0xD000, 0x6000, 0x0000 }, /* OBJ0 */
+			{ 0xFB0A, 0xD000, 0x6000, 0x0000 }, /* OBJ1 */
+			{ 0xA4FF, 0xFFE0, 0x0300, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x08 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFB0A, 0xD000, 0x6000, 0x0000 }, /* OBJ0 */
+			{ 0x001F, 0xFFFF, 0xFFEF, 0x043F }, /* OBJ1 */
+			{ 0xA4FF, 0xFFE0, 0x0300, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x09 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFB80, 0x9200, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFF9, 0x677D, 0x9C26, 0x5ACB }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0A && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0x0000, 0xFFFF, 0xFC30, 0x91C7 }, /* OBJ0 */
+			{ 0x0000, 0xFFFF, 0xFC30, 0x91C7 }, /* OBJ1 */
+			{ 0xB5BF, 0xFFF2, 0xAAC8, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0B && shuffling_flags==0x01)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0B && shuffling_flags==0x02)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0B && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFFEF, 0x043F, 0xF800 }, /* OBJ1 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0C && shuffling_flags==0x02)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }, /* OBJ0 */
+			{ 0xFE28, 0xFEA0, 0x91C0, 0x4800 }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0C && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFE28, 0xFEA0, 0x91C0, 0x4800 }, /* OBJ0 */
+			{ 0xFE28, 0xFEA0, 0x91C0, 0x4800 }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0C && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFE28, 0xFEA0, 0x91C0, 0x4800 }, /* OBJ0 */
+			{ 0xFFFF, 0x5DFF, 0xF800, 0x001F }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0D && shuffling_flags==0x01)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0D && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0D && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x8C7B, 0x5291, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0E && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0E && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0F && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x0F && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x10 && shuffling_flags==0x01)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x10 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x11 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x07E0, 0x3420, 0x0240 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x12 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x12 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x12 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x13 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0x0000, 0x0430, 0xFEE0, 0xFFFF }, /* OBJ0 */
+			{ 0x0000, 0x0430, 0xFEE0, 0xFFFF }, /* OBJ1 */
+			{ 0x0000, 0x0430, 0xFEE0, 0xFFFF }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x14 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFE0, 0xF800, 0x6000, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x15 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xAD70, 0x438F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x16 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xB634, 0x8CCF, 0x63AA, 0x31C4 }, /* OBJ0 */
+			{ 0xB634, 0x8CCF, 0x63AA, 0x31C4 }, /* OBJ1 */
+			{ 0xB634, 0x8CCF, 0x63AA, 0x31C4 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x17 && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFF4, 0xFCB2, 0x94BF, 0x0000 }, /* OBJ0 */
+			{ 0xFFF4, 0xFCB2, 0x94BF, 0x0000 }, /* OBJ1 */
+			{ 0xFFF4, 0xFCB2, 0x94BF, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x18 && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x19 && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFD6C, 0x8180, 0x0000 }, /* OBJ1 */
+			{ 0xC864, 0xCCF0, 0x8345, 0x5981 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x1A && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0420, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFFE0, 0x7A40, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x1B && shuffling_flags==0x00)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFE60, 0x9B00, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFE60, 0x9B00, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0xFE60, 0x9B00, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x1C && shuffling_flags==0x01)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x7FE6, 0x0318, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x7FE6, 0x0318, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x1C && shuffling_flags==0x03)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x14c8, 0x0318, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0x1C && shuffling_flags==0x05)
+	{
+		const palette_t palette = 	{
+			{ 0xFFFF, 0xFC30, 0x91C7, 0x0000 }, /* OBJ0 */
+			{ 0xFFFF, 0x653F, 0x001F, 0x0000 }, /* OBJ1 */
+			{ 0xFFFF, 0x7FE6, 0x0318, 0x0000 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	if(table_entry==0xFF && shuffling_flags==0xFF)
+	{
+		/* Game Boy DMG palette (4 shades of green) */
+		const palette_t palette = 	{
+			{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }, /* OBJ0 */
+			{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }, /* OBJ1 */
+			{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }  /* BG */
+		};
+		memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+		return;
+	}
+	/* default palette */
+	printf("E get_colour_palette: No palette found for table_entry=0x%02X shuffling_flags=0x%02X\n",
+		table_entry,
+		shuffling_flags);
+	/* Game Boy DMG palette (4 shades of green) */
+	const palette_t palette = 	{
+		{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }, /* OBJ0 */
+		{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }, /* OBJ1 */
+		{ 0xDFEA, 0xAE68, 0x74E6, 0x4388 }  /* BG */
+	};
+	memcpy(selected_palette, palette, PALETTE_SIZE_IN_BYTES);
+}
+
+/**
+ * Automatically assigns a colour palette to the game using a given game
+ * checksum and disambiguation characters (4th character of the game title)
+ * 
+ * "The Game Boy Color Bootstrap ROM is executed when the GBC is turned on.
+ * The ROM assigns color palettes to certain monochrome Game Boy games by 
+ * computing a hash of the ROM's header title for every Nintendo Licensee game 
+ * and checking it against an internal database of hashes. 
+ * The resulting index is then used to obtain an entry ID 
+ * (from 0x00 up to and including 0x1C) and shuffling flags (a 3-bit bitfield). 
+ * An entry is a triplet of palettes, and the "shuffling flags" replace some 
+ * of the triplet's palettes with others." 
+ * Source: The Cutting Room Floor (https://tcrf.net/Game_Boy_Color_Bootstrap_ROM)
+ */
+void auto_assign_palette(uint16_t palette[3][4], uint8_t game_checksum, const char *game_title)
+{
+	char disambiguation_character=game_title[3]; /* e.g. 'METROID' -> R */
+	printf("I auto_assign_palette(0x%02X,%s)\n", game_checksum,game_title);
+	switch(game_checksum)
+	{
+		case 0x00:
+		{
+			/*  */
+			get_colour_palette(palette,0x1C,0x03);
+			break;
+		}
+		case 0x01:
+		{
+			/* Arcade Classic No. 4 - Defender & Joust (USA, Europe) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x0C:
+		{
+			/* Nigel Mansell's World Championship Racing (Europe) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x0D:
+		{
+			if(disambiguation_character=='E') {
+				/* Pocket Bomberman (Europe) */
+				get_colour_palette(palette,0x0C,0x03);
+				break;
+			} else {
+				/* Tetris 2 (Europe) */ 
+				/* Tetris 2 (USA) */
+				get_colour_palette(palette,0x07,0x04);
+				break;
+			}
+
+		}
+		case 0x10:
+		{
+			/* Super R.C. Pro-Am (USA, Europe) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x14:
+		{
+			/* Game Boy Camera Gold (USA) */
+			/* Pocket Monsters Aka (Japan) */
+			/* Pocket Monsters Aka (Japan) (Rev A) */
+			/* Pokemon - Edicion Roja (Spain) */
+			/* Pokemon - Red Version (USA, Europe) */
+			/* Pokemon - Rote Edition (Germany) */
+			/* Pokemon - Version Rouge (France) */
+			/* Pokemon - Versione Rossa (Italy) */
+			get_colour_palette(palette,0x10,0x01);
+			break;
+		}
+		case 0x15:
+		{
+			/* Pocket Monsters - Pikachu (Japan) (Rev 0A) */
+			/* Pocket Monsters - Pikachu (Japan) (Rev B) */
+			/* Pocket Monsters - Pikachu (Japan) (Rev C) */
+			/* Pocket Monsters - Pikachu (Japan) (Rev D) */
+			get_colour_palette(palette,0x07,0x00);
+			break;
+		}
+		case 0x16:
+		{
+			if(disambiguation_character=='M') {
+				/* CUSTOM */
+				/* Batman - The Animated Series (USA, Europe) */
+				get_colour_palette(palette,0x0D,0x05);
+				break;
+			} else {
+				/* Donkey Kong Land (Japan) */
+				get_colour_palette(palette,0x0C,0x05);
+				break;
+			}
+
+			/* Yakuman (Japan);; Yakuman (Japan) (Rev A) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x17:
+		{
+			/* Othello (Europe) */
+			get_colour_palette(palette,0x0E,0x05);
+			break;
+		}
+		case 0x18:
+		{
+			if(disambiguation_character=='I') {
+				/* Wario Blast Featuring Bomberman! (USA, Europe) */
+				get_colour_palette(palette,0x1C,0x03);
+				break;
+			} else {
+				/* Donkey Kong Land (Japan) */
+				get_colour_palette(palette,0x0C,0x05);
+				break;
+			}
+		}
+		case 0x19:
+		{
+			/* Donkey Kong (World) */
+			/* Donkey Kong (World) (Rev A) */
+			get_colour_palette(palette,0x06,0x03);
+			break;
+		}
+		case 0x1D:
+		{
+			/* Kirby no Pinball (Japan) */
+			/* Kirby's Pinball Land (USA, Europe) */
+			get_colour_palette(palette,0x08,0x03);
+			break;
+		}
+		case 0x27:
+		{
+			if(disambiguation_character=='B') {
+				/* Kirby no Block Ball (Japan) */
+				/* Kirby's Block Ball (USA, Europe) */
+				get_colour_palette(palette,0x08,0x05);
+				break;
+			} else {
+				/* Magnetic Soccer (Europe) */
+				get_colour_palette(palette,0x0E,0x05);
+				break;
+			}
+		}
+		case 0x28:
+		{
+			if(disambiguation_character=='A') {
+				/* Arcade Classic No. 3 - Galaga & Galaxian (USA) */
+				get_colour_palette(palette,0x13,0x00);
+				break;	
+			} else {
+				/* Golf (World) */
+				get_colour_palette(palette,0x0E,0x03);
+				break;
+			}
+		}
+		case 0x29:
+		{
+			/* Mega Man III (Europe) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x2B:
+		{
+			/* Mega Man V (USA) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x34:
+		{
+			/* Game Boy Gallery (Japan) */
+			get_colour_palette(palette,0x04,0x03);
+			break;
+		}
+		case 0x35:
+		{
+			/* Mario no Picross (Japan) */
+			/* Mario's Picross (USA, Europe) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x36:
+		{
+			/* Baseball (World) */
+			get_colour_palette(palette,0x03,0x05);
+			break;
+		}
+		case 0x39:
+		{
+			/* Dynablaster (Europe) */
+			get_colour_palette(palette,0x0F,0x03);
+			break;
+		}
+		case 0x3C:
+		{
+			/* Dr. Mario (World) */
+			/* Dr. Mario (World) (Rev A) */
+			get_colour_palette(palette,0x0B,0x02);
+			break;
+		}
+		case 0x3D:
+		{
+			/* Yoshi (USA) */
+			/* Yoshi no Tamago (Japan) */
+			get_colour_palette(palette,0x05,0x03);
+			break;
+		}
+		case 0x3E:
+		{
+			/* Yoshi no Cookie (Japan) */
+			get_colour_palette(palette,0x06,0x04);
+			break;
+		}
+		case 0x3F:
+		{
+			/* Tetris Plus (USA, Europe) */
+			get_colour_palette(palette,0x1C,0x03);
+			break;
+		}
+		case 0x43:
+		{
+			/* Chessmaster, The (Europe) */
+			get_colour_palette(palette,0x0F,0x03);
+			break;
+		}
+		case 0x46:
+		{
+			if(disambiguation_character=='E') {
+				/* Super Mario Land (World) */
+				/* Super Mario Land (World) (Rev A) */
+				get_colour_palette(palette,0x0A,0x03);
+				break;
+			} else {
+				/* Metroid II - Return of Samus (World) */
+				get_colour_palette(palette,0x14,0x05);
+				break;
+			}
+		}
+		case 0x49:
+		{
+			/* Kirby's Dream Land (USA, Europe) */
+			get_colour_palette(palette,0x08,0x05);
+			break;
+		}
+		case 0x4B:
+		{
+			/* Play Action Football (USA) */
+			get_colour_palette(palette,0x0E,0x03);
+			break;
+		}
+		case 0x4E:
+		{
+			/* Wave Race (USA, Europe) */
+			get_colour_palette(palette,0x0B,0x05);
+			break;
+		}
+		case 0x50:
+		{
+			/* Castlevania II - Belmont's Revenge (USA, Europe) */
+			get_colour_palette(palette,0x0C,0x05);
+			break;
+		}
+		case 0x52:
+		{
+			/* Street Fighter II (USA, Europe) (Rev A) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x58:
+		{
+			/* X (Japan) */
+			get_colour_palette(palette,0x16,0x00);
+			break;
+		}
+		case 0x59:
+		{
+			/* Wario Land - Super Mario Land 3 (World) */
+			get_colour_palette(palette,0x00,0x05);
+			break;
+		}
+		case 0x5C:
+		{
+			/* Hoshi no Kirby (Japan) */ 
+			/* Hoshi no Kirby (Japan) (Rev A) */
+			get_colour_palette(palette,0x08,0x05);
+			break;
+		}
+		case 0x5D:
+		{
+			/* Battle Arena Toshinden (USA) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x61:
+		{
+			if(disambiguation_character=='A') {
+				/* Vegas Stakes (USA, Europe) */
+			 	get_colour_palette(palette,0x0E,0x05);
+			 	break;
+			} else {
+				/* Pocket Monsters Ao (Japan) */
+				/* Pokemon - Blaue Edition (Germany) */
+				/* Pokemon - Blue Version (USA, Europe) */
+				/* Pokemon - Edicion Azul (Spain) */
+				/* Pokemon - Version Bleue (France) */
+				/* Pokemon - Versione Blu (Italy) */
+				get_colour_palette(palette,0x0B,0x01);
+				break;
+			}
+		}
+		case 0x66:
+		{
+			if(disambiguation_character=='E') {
+				/* Game Boy Gallery 2 (Australia) */
+				/* Game Boy Gallery 2 (Japan) */
+				get_colour_palette(palette,0x04,0x03);
+				break;
+			} else {
+				/* Arcade Classic No. 2 - Centipede & Millipede (USA, Europe) */
+				get_colour_palette(palette,0x1C,0x03);
+				break;
+			}
+		}
+		case 0x67:
+		{
+			/* Kirby's Star Stacker (USA, Europe) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x68:
+		{
+			/* Adventures of Lolo (Europe) */
+			/* Mega Man II (Europe) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x69:
+		{
+			/* Tetris Flash (Japan) */
+			get_colour_palette(palette,0x07,0x04);
+			break;
+		}
+		case 0x6A:
+		{
+			if(disambiguation_character=='K') {
+				/* Donkey Kong Land 2 (USA, Europe) */
+				get_colour_palette(palette,0x0C,0x05);
+				break;
+			} else {
+				/* Mario & Yoshi (Europe) */
+				get_colour_palette(palette,0x05,0x03);
+				break;
+			}
+		}
+		case 0x6B:
+		{
+			/* Castlevania Adventure, The (USA) */
+			/* Donkey Kong Land III (USA, Europe) */
+			/* Donkey Kong Land III (USA, Europe) (Rev A) */
+			get_colour_palette(palette,0x0C,0x05);
+			break;
+		}
+		case 0x6D:
+		{
+			/* King of Fighters '95, The (USA) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0x6F:
+		{
+			/* Pocket Camera (Japan) (Rev A) */
+			get_colour_palette(palette,0x1B,0x00);
+			break;
+		}
+		case 0x70:
+		{
+			/* Legend of Zelda, The - Link's Awakening (France) */
+			/* Legend of Zelda, The - Link's Awakening (Germany) */
+			/* Legend of Zelda, The - Link's Awakening (USA, Europe) */
+			/* Legend of Zelda, The - Link's Awakening (USA, Europe) (Rev A) */
+			/* Legend of Zelda, The - Link's Awakening (USA, Europe) (Rev B) */
+			/* Zelda no Densetsu - Yume o Miru Shima (Japan) */
+			/* Zelda no Densetsu - Yume o Miru Shima (Japan) (Rev A) */
+			get_colour_palette(palette,0x11,0x05);
+			break;
+		}
+		case 0x71:
+		{
+			/* Tetris Blast (USA, Europe) */
+			get_colour_palette(palette,0x06,0x00);
+			break;
+		}
+		case 0x75:
+		{
+			/* Picross 2 (Japan) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x86:
+		{
+			/* Donkey Kong Land (USA, Europe) */
+			get_colour_palette(palette,0x01,0x05);
+			break;
+		}
+		case 0x88:
+		{
+			/* Alleyway (World) */
+			get_colour_palette(palette,0x08,0x00);
+			break;
+		}
+		case 0x8B:
+		{
+			/* Mystic Quest (Europe);; Mystic Quest (France) */
+			/* Mystic Quest (Germany) */
+			get_colour_palette(palette,0x0E,0x05);
+			break;
+		}
+		case 0x8C:
+		{
+			/* Radar Mission (Japan) */
+			/* Radar Mission (USA, Europe) */
+			get_colour_palette(palette,0x00,0x01);
+			break;
+		}
+		case 0x90:
+		{
+			/* Nintendo World Cup (USA, Europe) */
+			get_colour_palette(palette,0x0E,0x03);
+			break;
+		}
+		case 0x92:
+		{
+			/* F-1 Race (World);; F-1 Race (World) (Rev A) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x95:
+		{
+			/* Yoshi no Panepon (Japan) */
+			get_colour_palette(palette,0x05,0x04);
+			break;
+		}
+		case 0x97:
+		{
+			/* King of the Zoo (Europe) */
+			get_colour_palette(palette,0x0F,0x03);
+			break;
+		}
+		case 0x99:
+		{
+			/* Kirby no Kirakira Kids (Japan) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0x9A:
+		{
+			/* Arcade Classic No. 1 - Asteroids & Missile Command (USA, Europe) */
+			get_colour_palette(palette,0x0E,0x03);
+			break;
+		}
+		case 0x9C:
+		{
+			/* Pinocchio (Europe) */
+			get_colour_palette(palette,0x0C,0x02);
+			break;
+		}
+		case 0x9D:
+		{
+			/* Killer Instinct (USA, Europe) */
+			get_colour_palette(palette,0x0D,0x05);
+			break;
+		}
+		case 0xA2:
+		{
+			/* Star Wars (USA, Europe) (Rev A) */
+			get_colour_palette(palette,0x12,0x05);
+			break;
+		}
+		case 0xA5:
+		{
+			if(disambiguation_character=='R') {
+				/* Battletoads in Ragnarok's World (Europe) */
+				get_colour_palette(palette,0x12,0x03);
+				break;
+			} else {
+				/* Solar Striker (World) */
+				get_colour_palette(palette,0x13,0x00);
+				break;
+			}
+		}
+		case 0xA8:
+		{
+			/* Super Donkey Kong GB (Japan) */
+			get_colour_palette(palette,0x01,0x05);
+			break;
+		}
+		case 0xAA:
+		{
+			/* James Bond 007 (USA, Europe) */
+			/* Pocket Monsters Midori (Japan) */
+			/* Pocket Monsters Midori (Japan) (Rev A) */
+			get_colour_palette(palette,0x1C,0x01);
+			break;
+		}
+		case 0xB3:
+		{
+			if(disambiguation_character=='U') {
+				/* Moguranya (Japan) */
+				/* Mole Mania (USA, Europe) */
+				get_colour_palette(palette,0x00,0x03);
+				break;
+			} else if(disambiguation_character=='R') {
+				/* Tetris Attack (USA) */
+				/* Tetris Attack (USA, Europe) (Rev A) */
+				get_colour_palette(palette,0x05,0x04);
+				break;
+			} else {
+				/* Hoshi no Kirby 2 (Japan) */
+				/* Kirby's Dream Land 2 (USA, Europe) */
+				get_colour_palette(palette,0x08,0x05);
+				break;
+			}
+		}
+		case 0xB7:
+		{
+			/* Game Boy Gallery (Europe) */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 0xBD:
+		{
+			/* Toy Story (Europe) */
+			get_colour_palette(palette,0x0E,0x03);
+			break;
+		}
+		case 0xBF:
+		{
+			if(disambiguation_character=='C') {
+				/* Soccer (Europe) (En,Fr,De) */
+				get_colour_palette(palette,0x02,0x05);
+				break;
+			} else {
+				/* Kid Icarus - Of Myths and Monsters (USA, Europe) */
+				get_colour_palette(palette,0x0D,0x03);
+				break;
+			}
+		}
+		case 0xC6:
+		{
+			if(disambiguation_character==' ') {
+				/* Ken Griffey Jr. presents Major League Baseball (USA, Europe) */
+				get_colour_palette(palette,0x1C,0x03);
+				break;
+			} else {
+				/* Game Boy Wars (Japan) */
+				get_colour_palette(palette,0x00,0x05);
+				break;
+			}
+		}
+		case 0xC9:
+		{
+			/* Super Mario Land 2 - 6 Golden Coins (USA, Europe) */
+			/* Super Mario Land 2 - 6 Golden Coins (USA, Europe) (Rev A) */
+			/* Super Mario Land 2 - 6 Golden Coins (USA, Europe) (Rev B) */
+			/* Super Mario Land 2 - 6-tsu no Kinka (Japan) */
+			/* Super Mario Land 2 - 6-tsu no Kinka (Japan) (Rev B) */
+			get_colour_palette(palette,0x09,0x05);
+			break;
+		}
+		case 0xCE:
+		{
+			/* Top Ranking Tennis (Europe) */
+			get_colour_palette(palette,0x02,0x05);
+			break;
+		}
+		case 0xD1:
+		{
+			/* Tennis (World) */
+			get_colour_palette(palette,0x02,0x05);
+			break;
+		}
+		case 0xD3:
+		{
+			if(disambiguation_character=='R') {
+				/* Kaeru no Tame ni Kane wa Naru (Japan) */
+				get_colour_palette(palette,0x0D,0x01);
+				break;
+			} else {
+				/* Wario Land II (USA, Europe) */
+				get_colour_palette(palette,0x15,0x05);
+				break;
+			}
+		}
+		case 0xDB:
+		{
+			/* Tetris (World);; Tetris (World) (Rev A) */
+			get_colour_palette(palette,0x07,0x00);
+			break;
+		}
+		case 0xE0:
+		{
+			/* Yoshi's Cookie (USA, Europe) */
+			get_colour_palette(palette,0x06,0x04);
+			break;
+		}
+		case 0xE8:
+		{
+			/* Space Invaders (Europe) */
+			/* Space Invaders (USA) */
+			get_colour_palette(palette,0x13,0x00);
+			break;
+		}
+		case 0xF0:
+		{
+			/* Top Rank Tennis (USA) */
+			get_colour_palette(palette,0x02,0x05);
+			break;
+		}
+		case 0xF2:
+		{
+			/* Qix (World) */
+			get_colour_palette(palette,0x07,0x04);
+			break;
+		}
+		case 0xF4:
+		{
+			if(disambiguation_character==' ') {
+				/* Game & Watch Gallery (Europe)*/
+				/* Game & Watch Gallery (USA) */
+				/* Game & Watch Gallery (USA) (Rev A) */
+				get_colour_palette(palette,0x04,0x03);
+				break;	
+			} else {
+				/* Pac-In-Time (USA) */
+				get_colour_palette(palette,0x1C,0x05);
+				break;
+			}
+		}
+		case 0xF6:
+		{
+			/* Mega Man - Dr. Wily's Revenge (Europe) */
+			get_colour_palette(palette,0x0F,0x05);
+			break;
+		}
+		case 0xF7:
+		{
+			/* Boy and His Blob in the Rescue of Princess Blobette, A (Europe) */
+			get_colour_palette(palette,0x12,0x05);
+			break;
+		}
+		case 0xFF:
+		{
+			/* Balloon Kid (USA, Europe) */
+			get_colour_palette(palette,0x06,0x00);
+			break;
+		}
+		default:
+		{
+			printf("E auto_assign_palette: No palette found for checksum 0x%02X.\n", game_checksum);
+			/* Original Game Boy DMG color palette (monochrome 4-shades of green!) */
+ 			get_colour_palette(palette,0xFF,0xFF);
+			break;
+		}
+	}
+}
+
+/**
+ * Manually assigns a palette. This is used to allow the user to manually select a
+ * different colour palette if one was not found automatically, or if the user
+ * prefers a different colour palette.
+ * selection is the requested colour palette. This should be a maximum of
+ * NUMBER_OF_MANUAL_PALETTES - 1. The default palette is selected otherwise.
+ * The entries are listed here in the order they are stored in the ROM.
+ * 
+ * A total of twelve palette configurations are in here. 
+ * Six of these are unique to the manual selection mode. 
+ * The button combinations trigger the respective configuration 
+ * and are previewed in the respective shades while the Nintendo
+ * Game Boy Color logo is still being displayed on the screen.
+ */
+void manual_assign_palette(palette_t palette, uint8_t selection)
+{
+	printf("I manual_assign_palette(%d)\n", selection);
+	switch(selection)
+	{
+		case 0:
+		{
+			/* Right */
+			get_colour_palette(palette,0x05,0x00);
+			break;
+		}
+		case 1:
+		{
+			/* A + Down */
+			get_colour_palette(palette,0x07,0x00);
+			break;
+		}
+		case 2:
+		{
+			/* Up */
+			get_colour_palette(palette,0x12,0x00);
+			break;
+		}
+		case 3:
+		{
+			/* B + Right */
+			get_colour_palette(palette,0x13,0x00);
+			break;
+		}
+		case 4:
+		{
+			/* B + Left Game Boy Pocket (monochrome 4-shades of white) */
+			get_colour_palette(palette,0x16,0x00);
+			break;
+		}
+		case 5:
+		{
+			/* Down */
+			get_colour_palette(palette,0x17,0x00);
+			break;
+		}
+		case 6:
+		{
+			/* B + Up */
+			get_colour_palette(palette,0x19,0x03);
+			break;
+		}
+		case 7:
+		{
+			/* A + Right */
+			get_colour_palette(palette,0x1C,0x03);
+			break;
+		}
+		case 8:
+		{
+			/* A + Left */
+			get_colour_palette(palette,0x0D,0x05);
+			break;
+		}
+		case 9:
+		{
+			/* A + Up */
+			get_colour_palette(palette,0x10,0x05);
+			break;
+		}
+		case 10:
+		{
+			/* Left */
+			get_colour_palette(palette,0x18,0x05);
+			break;
+		}
+		case 11:
+		{
+			/* B + Down */
+			get_colour_palette(palette,0x1A,0x05);
+			break;	
+		}
+	 	case 12:
+ 		{
+			/* A + B Original Game Boy DMG color palette (monochrome 4-shades of green!) */
+ 			get_colour_palette(palette,0xFF,0xFF);
+ 			break;
+		}
+		default:
+		{
+			/* Original Game Boy DMG color palette (monochrome 4-shades of green!) */
+ 			get_colour_palette(palette,0xFF,0xFF);
+ 			break;
+		}
+	}
+}
\ No newline at end of file
diff --git a/MCUME_pico2/picogb/palettes/hedley.h b/MCUME_pico2/picogb/palettes/hedley.h
new file mode 100755
index 0000000..8a713e6
--- /dev/null
+++ b/MCUME_pico2/picogb/palettes/hedley.h
@@ -0,0 +1,2042 @@
+/* Hedley - https://nemequ.github.io/hedley
+ * Created by Evan Nemerson <evan@nemerson.com>
+ *
+ * To the extent possible under law, the author(s) have dedicated all
+ * copyright and related and neighboring rights to this software to
+ * the public domain worldwide. This software is distributed without
+ * any warranty.
+ *
+ * For details, see <http://creativecommons.org/publicdomain/zero/1.0/>.
+ * SPDX-License-Identifier: CC0-1.0
+ */
+
+#if !defined(HEDLEY_VERSION) || (HEDLEY_VERSION < 15)
+#if defined(HEDLEY_VERSION)
+#  undef HEDLEY_VERSION
+#endif
+#define HEDLEY_VERSION 15
+
+#if defined(HEDLEY_STRINGIFY_EX)
+#  undef HEDLEY_STRINGIFY_EX
+#endif
+#define HEDLEY_STRINGIFY_EX(x) #x
+
+#if defined(HEDLEY_STRINGIFY)
+#  undef HEDLEY_STRINGIFY
+#endif
+#define HEDLEY_STRINGIFY(x) HEDLEY_STRINGIFY_EX(x)
+
+#if defined(HEDLEY_CONCAT_EX)
+#  undef HEDLEY_CONCAT_EX
+#endif
+#define HEDLEY_CONCAT_EX(a,b) a##b
+
+#if defined(HEDLEY_CONCAT)
+#  undef HEDLEY_CONCAT
+#endif
+#define HEDLEY_CONCAT(a,b) HEDLEY_CONCAT_EX(a,b)
+
+#if defined(HEDLEY_CONCAT3_EX)
+#  undef HEDLEY_CONCAT3_EX
+#endif
+#define HEDLEY_CONCAT3_EX(a,b,c) a##b##c
+
+#if defined(HEDLEY_CONCAT3)
+#  undef HEDLEY_CONCAT3
+#endif
+#define HEDLEY_CONCAT3(a,b,c) HEDLEY_CONCAT3_EX(a,b,c)
+
+#if defined(HEDLEY_VERSION_ENCODE)
+#  undef HEDLEY_VERSION_ENCODE
+#endif
+#define HEDLEY_VERSION_ENCODE(major,minor,revision) (((major) * 1000000) + ((minor) * 1000) + (revision))
+
+#if defined(HEDLEY_VERSION_DECODE_MAJOR)
+#  undef HEDLEY_VERSION_DECODE_MAJOR
+#endif
+#define HEDLEY_VERSION_DECODE_MAJOR(version) ((version) / 1000000)
+
+#if defined(HEDLEY_VERSION_DECODE_MINOR)
+#  undef HEDLEY_VERSION_DECODE_MINOR
+#endif
+#define HEDLEY_VERSION_DECODE_MINOR(version) (((version) % 1000000) / 1000)
+
+#if defined(HEDLEY_VERSION_DECODE_REVISION)
+#  undef HEDLEY_VERSION_DECODE_REVISION
+#endif
+#define HEDLEY_VERSION_DECODE_REVISION(version) ((version) % 1000)
+
+#if defined(HEDLEY_GNUC_VERSION)
+#  undef HEDLEY_GNUC_VERSION
+#endif
+#if defined(__GNUC__) && defined(__GNUC_PATCHLEVEL__)
+#  define HEDLEY_GNUC_VERSION HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__)
+#elif defined(__GNUC__)
+#  define HEDLEY_GNUC_VERSION HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, 0)
+#endif
+
+#if defined(HEDLEY_GNUC_VERSION_CHECK)
+#  undef HEDLEY_GNUC_VERSION_CHECK
+#endif
+#if defined(HEDLEY_GNUC_VERSION)
+#  define HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (HEDLEY_GNUC_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_MSVC_VERSION)
+#  undef HEDLEY_MSVC_VERSION
+#endif
+#if defined(_MSC_FULL_VER) && (_MSC_FULL_VER >= 140000000) && !defined(__ICL)
+#  define HEDLEY_MSVC_VERSION HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 10000000, (_MSC_FULL_VER % 10000000) / 100000, (_MSC_FULL_VER % 100000) / 100)
+#elif defined(_MSC_FULL_VER) && !defined(__ICL)
+#  define HEDLEY_MSVC_VERSION HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 1000000, (_MSC_FULL_VER % 1000000) / 10000, (_MSC_FULL_VER % 10000) / 10)
+#elif defined(_MSC_VER) && !defined(__ICL)
+#  define HEDLEY_MSVC_VERSION HEDLEY_VERSION_ENCODE(_MSC_VER / 100, _MSC_VER % 100, 0)
+#endif
+
+#if defined(HEDLEY_MSVC_VERSION_CHECK)
+#  undef HEDLEY_MSVC_VERSION_CHECK
+#endif
+#if !defined(HEDLEY_MSVC_VERSION)
+#  define HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (0)
+#elif defined(_MSC_VER) && (_MSC_VER >= 1400)
+#  define HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 10000000) + (minor * 100000) + (patch)))
+#elif defined(_MSC_VER) && (_MSC_VER >= 1200)
+#  define HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 1000000) + (minor * 10000) + (patch)))
+#else
+#  define HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_VER >= ((major * 100) + (minor)))
+#endif
+
+#if defined(HEDLEY_INTEL_VERSION)
+#  undef HEDLEY_INTEL_VERSION
+#endif
+#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && !defined(__ICL)
+#  define HEDLEY_INTEL_VERSION HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, __INTEL_COMPILER_UPDATE)
+#elif defined(__INTEL_COMPILER) && !defined(__ICL)
+#  define HEDLEY_INTEL_VERSION HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, 0)
+#endif
+
+#if defined(HEDLEY_INTEL_VERSION_CHECK)
+#  undef HEDLEY_INTEL_VERSION_CHECK
+#endif
+#if defined(HEDLEY_INTEL_VERSION)
+#  define HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (HEDLEY_INTEL_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_INTEL_CL_VERSION)
+#  undef HEDLEY_INTEL_CL_VERSION
+#endif
+#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && defined(__ICL)
+#  define HEDLEY_INTEL_CL_VERSION HEDLEY_VERSION_ENCODE(__INTEL_COMPILER, __INTEL_COMPILER_UPDATE, 0)
+#endif
+
+#if defined(HEDLEY_INTEL_CL_VERSION_CHECK)
+#  undef HEDLEY_INTEL_CL_VERSION_CHECK
+#endif
+#if defined(HEDLEY_INTEL_CL_VERSION)
+#  define HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (HEDLEY_INTEL_CL_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_PGI_VERSION)
+#  undef HEDLEY_PGI_VERSION
+#endif
+#if defined(__PGI) && defined(__PGIC__) && defined(__PGIC_MINOR__) && defined(__PGIC_PATCHLEVEL__)
+#  define HEDLEY_PGI_VERSION HEDLEY_VERSION_ENCODE(__PGIC__, __PGIC_MINOR__, __PGIC_PATCHLEVEL__)
+#endif
+
+#if defined(HEDLEY_PGI_VERSION_CHECK)
+#  undef HEDLEY_PGI_VERSION_CHECK
+#endif
+#if defined(HEDLEY_PGI_VERSION)
+#  define HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (HEDLEY_PGI_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_SUNPRO_VERSION)
+#  undef HEDLEY_SUNPRO_VERSION
+#endif
+#if defined(__SUNPRO_C) && (__SUNPRO_C > 0x1000)
+#  define HEDLEY_SUNPRO_VERSION HEDLEY_VERSION_ENCODE((((__SUNPRO_C >> 16) & 0xf) * 10) + ((__SUNPRO_C >> 12) & 0xf), (((__SUNPRO_C >> 8) & 0xf) * 10) + ((__SUNPRO_C >> 4) & 0xf), (__SUNPRO_C & 0xf) * 10)
+#elif defined(__SUNPRO_C)
+#  define HEDLEY_SUNPRO_VERSION HEDLEY_VERSION_ENCODE((__SUNPRO_C >> 8) & 0xf, (__SUNPRO_C >> 4) & 0xf, (__SUNPRO_C) & 0xf)
+#elif defined(__SUNPRO_CC) && (__SUNPRO_CC > 0x1000)
+#  define HEDLEY_SUNPRO_VERSION HEDLEY_VERSION_ENCODE((((__SUNPRO_CC >> 16) & 0xf) * 10) + ((__SUNPRO_CC >> 12) & 0xf), (((__SUNPRO_CC >> 8) & 0xf) * 10) + ((__SUNPRO_CC >> 4) & 0xf), (__SUNPRO_CC & 0xf) * 10)
+#elif defined(__SUNPRO_CC)
+#  define HEDLEY_SUNPRO_VERSION HEDLEY_VERSION_ENCODE((__SUNPRO_CC >> 8) & 0xf, (__SUNPRO_CC >> 4) & 0xf, (__SUNPRO_CC) & 0xf)
+#endif
+
+#if defined(HEDLEY_SUNPRO_VERSION_CHECK)
+#  undef HEDLEY_SUNPRO_VERSION_CHECK
+#endif
+#if defined(HEDLEY_SUNPRO_VERSION)
+#  define HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (HEDLEY_SUNPRO_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_EMSCRIPTEN_VERSION)
+#  undef HEDLEY_EMSCRIPTEN_VERSION
+#endif
+#if defined(__EMSCRIPTEN__)
+#  define HEDLEY_EMSCRIPTEN_VERSION HEDLEY_VERSION_ENCODE(__EMSCRIPTEN_major__, __EMSCRIPTEN_minor__, __EMSCRIPTEN_tiny__)
+#endif
+
+#if defined(HEDLEY_EMSCRIPTEN_VERSION_CHECK)
+#  undef HEDLEY_EMSCRIPTEN_VERSION_CHECK
+#endif
+#if defined(HEDLEY_EMSCRIPTEN_VERSION)
+#  define HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (HEDLEY_EMSCRIPTEN_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_ARM_VERSION)
+#  undef HEDLEY_ARM_VERSION
+#endif
+#if defined(__CC_ARM) && defined(__ARMCOMPILER_VERSION)
+#  define HEDLEY_ARM_VERSION HEDLEY_VERSION_ENCODE(__ARMCOMPILER_VERSION / 1000000, (__ARMCOMPILER_VERSION % 1000000) / 10000, (__ARMCOMPILER_VERSION % 10000) / 100)
+#elif defined(__CC_ARM) && defined(__ARMCC_VERSION)
+#  define HEDLEY_ARM_VERSION HEDLEY_VERSION_ENCODE(__ARMCC_VERSION / 1000000, (__ARMCC_VERSION % 1000000) / 10000, (__ARMCC_VERSION % 10000) / 100)
+#endif
+
+#if defined(HEDLEY_ARM_VERSION_CHECK)
+#  undef HEDLEY_ARM_VERSION_CHECK
+#endif
+#if defined(HEDLEY_ARM_VERSION)
+#  define HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (HEDLEY_ARM_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_IBM_VERSION)
+#  undef HEDLEY_IBM_VERSION
+#endif
+#if defined(__ibmxl__)
+#  define HEDLEY_IBM_VERSION HEDLEY_VERSION_ENCODE(__ibmxl_version__, __ibmxl_release__, __ibmxl_modification__)
+#elif defined(__xlC__) && defined(__xlC_ver__)
+#  define HEDLEY_IBM_VERSION HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, (__xlC_ver__ >> 8) & 0xff)
+#elif defined(__xlC__)
+#  define HEDLEY_IBM_VERSION HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, 0)
+#endif
+
+#if defined(HEDLEY_IBM_VERSION_CHECK)
+#  undef HEDLEY_IBM_VERSION_CHECK
+#endif
+#if defined(HEDLEY_IBM_VERSION)
+#  define HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (HEDLEY_IBM_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_VERSION)
+#  undef HEDLEY_TI_VERSION
+#endif
+#if \
+    defined(__TI_COMPILER_VERSION__) && \
+    ( \
+      defined(__TMS470__) || defined(__TI_ARM__) || \
+      defined(__MSP430__) || \
+      defined(__TMS320C2000__) \
+    )
+#  if (__TI_COMPILER_VERSION__ >= 16000000)
+#    define HEDLEY_TI_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#  endif
+#endif
+
+#if defined(HEDLEY_TI_VERSION_CHECK)
+#  undef HEDLEY_TI_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_VERSION)
+#  define HEDLEY_TI_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_CL2000_VERSION)
+#  undef HEDLEY_TI_CL2000_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C2000__)
+#  define HEDLEY_TI_CL2000_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_CL2000_VERSION_CHECK)
+#  undef HEDLEY_TI_CL2000_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_CL2000_VERSION)
+#  define HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_CL2000_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_CL430_VERSION)
+#  undef HEDLEY_TI_CL430_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && defined(__MSP430__)
+#  define HEDLEY_TI_CL430_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_CL430_VERSION_CHECK)
+#  undef HEDLEY_TI_CL430_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_CL430_VERSION)
+#  define HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_CL430_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_ARMCL_VERSION)
+#  undef HEDLEY_TI_ARMCL_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && (defined(__TMS470__) || defined(__TI_ARM__))
+#  define HEDLEY_TI_ARMCL_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_ARMCL_VERSION_CHECK)
+#  undef HEDLEY_TI_ARMCL_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_ARMCL_VERSION)
+#  define HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_ARMCL_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_CL6X_VERSION)
+#  undef HEDLEY_TI_CL6X_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C6X__)
+#  define HEDLEY_TI_CL6X_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_CL6X_VERSION_CHECK)
+#  undef HEDLEY_TI_CL6X_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_CL6X_VERSION)
+#  define HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_CL6X_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_CL7X_VERSION)
+#  undef HEDLEY_TI_CL7X_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && defined(__C7000__)
+#  define HEDLEY_TI_CL7X_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_CL7X_VERSION_CHECK)
+#  undef HEDLEY_TI_CL7X_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_CL7X_VERSION)
+#  define HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_CL7X_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TI_CLPRU_VERSION)
+#  undef HEDLEY_TI_CLPRU_VERSION
+#endif
+#if defined(__TI_COMPILER_VERSION__) && defined(__PRU__)
+#  define HEDLEY_TI_CLPRU_VERSION HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000))
+#endif
+
+#if defined(HEDLEY_TI_CLPRU_VERSION_CHECK)
+#  undef HEDLEY_TI_CLPRU_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TI_CLPRU_VERSION)
+#  define HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (HEDLEY_TI_CLPRU_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_CRAY_VERSION)
+#  undef HEDLEY_CRAY_VERSION
+#endif
+#if defined(_CRAYC)
+#  if defined(_RELEASE_PATCHLEVEL)
+#    define HEDLEY_CRAY_VERSION HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, _RELEASE_PATCHLEVEL)
+#  else
+#    define HEDLEY_CRAY_VERSION HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, 0)
+#  endif
+#endif
+
+#if defined(HEDLEY_CRAY_VERSION_CHECK)
+#  undef HEDLEY_CRAY_VERSION_CHECK
+#endif
+#if defined(HEDLEY_CRAY_VERSION)
+#  define HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (HEDLEY_CRAY_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_IAR_VERSION)
+#  undef HEDLEY_IAR_VERSION
+#endif
+#if defined(__IAR_SYSTEMS_ICC__)
+#  if __VER__ > 1000
+#    define HEDLEY_IAR_VERSION HEDLEY_VERSION_ENCODE((__VER__ / 1000000), ((__VER__ / 1000) % 1000), (__VER__ % 1000))
+#  else
+#    define HEDLEY_IAR_VERSION HEDLEY_VERSION_ENCODE(__VER__ / 100, __VER__ % 100, 0)
+#  endif
+#endif
+
+#if defined(HEDLEY_IAR_VERSION_CHECK)
+#  undef HEDLEY_IAR_VERSION_CHECK
+#endif
+#if defined(HEDLEY_IAR_VERSION)
+#  define HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (HEDLEY_IAR_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_TINYC_VERSION)
+#  undef HEDLEY_TINYC_VERSION
+#endif
+#if defined(__TINYC__)
+#  define HEDLEY_TINYC_VERSION HEDLEY_VERSION_ENCODE(__TINYC__ / 1000, (__TINYC__ / 100) % 10, __TINYC__ % 100)
+#endif
+
+#if defined(HEDLEY_TINYC_VERSION_CHECK)
+#  undef HEDLEY_TINYC_VERSION_CHECK
+#endif
+#if defined(HEDLEY_TINYC_VERSION)
+#  define HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (HEDLEY_TINYC_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_DMC_VERSION)
+#  undef HEDLEY_DMC_VERSION
+#endif
+#if defined(__DMC__)
+#  define HEDLEY_DMC_VERSION HEDLEY_VERSION_ENCODE(__DMC__ >> 8, (__DMC__ >> 4) & 0xf, __DMC__ & 0xf)
+#endif
+
+#if defined(HEDLEY_DMC_VERSION_CHECK)
+#  undef HEDLEY_DMC_VERSION_CHECK
+#endif
+#if defined(HEDLEY_DMC_VERSION)
+#  define HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (HEDLEY_DMC_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_COMPCERT_VERSION)
+#  undef HEDLEY_COMPCERT_VERSION
+#endif
+#if defined(__COMPCERT_VERSION__)
+#  define HEDLEY_COMPCERT_VERSION HEDLEY_VERSION_ENCODE(__COMPCERT_VERSION__ / 10000, (__COMPCERT_VERSION__ / 100) % 100, __COMPCERT_VERSION__ % 100)
+#endif
+
+#if defined(HEDLEY_COMPCERT_VERSION_CHECK)
+#  undef HEDLEY_COMPCERT_VERSION_CHECK
+#endif
+#if defined(HEDLEY_COMPCERT_VERSION)
+#  define HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (HEDLEY_COMPCERT_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_PELLES_VERSION)
+#  undef HEDLEY_PELLES_VERSION
+#endif
+#if defined(__POCC__)
+#  define HEDLEY_PELLES_VERSION HEDLEY_VERSION_ENCODE(__POCC__ / 100, __POCC__ % 100, 0)
+#endif
+
+#if defined(HEDLEY_PELLES_VERSION_CHECK)
+#  undef HEDLEY_PELLES_VERSION_CHECK
+#endif
+#if defined(HEDLEY_PELLES_VERSION)
+#  define HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (HEDLEY_PELLES_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_MCST_LCC_VERSION)
+#  undef HEDLEY_MCST_LCC_VERSION
+#endif
+#if defined(__LCC__) && defined(__LCC_MINOR__)
+#  define HEDLEY_MCST_LCC_VERSION HEDLEY_VERSION_ENCODE(__LCC__ / 100, __LCC__ % 100, __LCC_MINOR__)
+#endif
+
+#if defined(HEDLEY_MCST_LCC_VERSION_CHECK)
+#  undef HEDLEY_MCST_LCC_VERSION_CHECK
+#endif
+#if defined(HEDLEY_MCST_LCC_VERSION)
+#  define HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (HEDLEY_MCST_LCC_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_GCC_VERSION)
+#  undef HEDLEY_GCC_VERSION
+#endif
+#if \
+  defined(HEDLEY_GNUC_VERSION) && \
+  !defined(__clang__) && \
+  !defined(HEDLEY_INTEL_VERSION) && \
+  !defined(HEDLEY_PGI_VERSION) && \
+  !defined(HEDLEY_ARM_VERSION) && \
+  !defined(HEDLEY_CRAY_VERSION) && \
+  !defined(HEDLEY_TI_VERSION) && \
+  !defined(HEDLEY_TI_ARMCL_VERSION) && \
+  !defined(HEDLEY_TI_CL430_VERSION) && \
+  !defined(HEDLEY_TI_CL2000_VERSION) && \
+  !defined(HEDLEY_TI_CL6X_VERSION) && \
+  !defined(HEDLEY_TI_CL7X_VERSION) && \
+  !defined(HEDLEY_TI_CLPRU_VERSION) && \
+  !defined(__COMPCERT__) && \
+  !defined(HEDLEY_MCST_LCC_VERSION)
+#  define HEDLEY_GCC_VERSION HEDLEY_GNUC_VERSION
+#endif
+
+#if defined(HEDLEY_GCC_VERSION_CHECK)
+#  undef HEDLEY_GCC_VERSION_CHECK
+#endif
+#if defined(HEDLEY_GCC_VERSION)
+#  define HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (HEDLEY_GCC_VERSION >= HEDLEY_VERSION_ENCODE(major, minor, patch))
+#else
+#  define HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (0)
+#endif
+
+#if defined(HEDLEY_HAS_ATTRIBUTE)
+#  undef HEDLEY_HAS_ATTRIBUTE
+#endif
+#if \
+  defined(__has_attribute) && \
+  ( \
+    (!defined(HEDLEY_IAR_VERSION) || HEDLEY_IAR_VERSION_CHECK(8,5,9)) \
+  )
+#  define HEDLEY_HAS_ATTRIBUTE(attribute) __has_attribute(attribute)
+#else
+#  define HEDLEY_HAS_ATTRIBUTE(attribute) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_ATTRIBUTE)
+#  undef HEDLEY_GNUC_HAS_ATTRIBUTE
+#endif
+#if defined(__has_attribute)
+#  define HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_HAS_ATTRIBUTE(attribute)
+#else
+#  define HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_ATTRIBUTE)
+#  undef HEDLEY_GCC_HAS_ATTRIBUTE
+#endif
+#if defined(__has_attribute)
+#  define HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_HAS_ATTRIBUTE(attribute)
+#else
+#  define HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_CPP_ATTRIBUTE)
+#  undef HEDLEY_HAS_CPP_ATTRIBUTE
+#endif
+#if \
+  defined(__has_cpp_attribute) && \
+  defined(__cplusplus) && \
+  (!defined(HEDLEY_SUNPRO_VERSION) || HEDLEY_SUNPRO_VERSION_CHECK(5,15,0))
+#  define HEDLEY_HAS_CPP_ATTRIBUTE(attribute) __has_cpp_attribute(attribute)
+#else
+#  define HEDLEY_HAS_CPP_ATTRIBUTE(attribute) (0)
+#endif
+
+#if defined(HEDLEY_HAS_CPP_ATTRIBUTE_NS)
+#  undef HEDLEY_HAS_CPP_ATTRIBUTE_NS
+#endif
+#if !defined(__cplusplus) || !defined(__has_cpp_attribute)
+#  define HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0)
+#elif \
+  !defined(HEDLEY_PGI_VERSION) && \
+  !defined(HEDLEY_IAR_VERSION) && \
+  (!defined(HEDLEY_SUNPRO_VERSION) || HEDLEY_SUNPRO_VERSION_CHECK(5,15,0)) && \
+  (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
+#  define HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) HEDLEY_HAS_CPP_ATTRIBUTE(ns::attribute)
+#else
+#  define HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_CPP_ATTRIBUTE)
+#  undef HEDLEY_GNUC_HAS_CPP_ATTRIBUTE
+#endif
+#if defined(__has_cpp_attribute) && defined(__cplusplus)
+#  define HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute)
+#else
+#  define HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_CPP_ATTRIBUTE)
+#  undef HEDLEY_GCC_HAS_CPP_ATTRIBUTE
+#endif
+#if defined(__has_cpp_attribute) && defined(__cplusplus)
+#  define HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute)
+#else
+#  define HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_BUILTIN)
+#  undef HEDLEY_HAS_BUILTIN
+#endif
+#if defined(__has_builtin)
+#  define HEDLEY_HAS_BUILTIN(builtin) __has_builtin(builtin)
+#else
+#  define HEDLEY_HAS_BUILTIN(builtin) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_BUILTIN)
+#  undef HEDLEY_GNUC_HAS_BUILTIN
+#endif
+#if defined(__has_builtin)
+#  define HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin)
+#else
+#  define HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_BUILTIN)
+#  undef HEDLEY_GCC_HAS_BUILTIN
+#endif
+#if defined(__has_builtin)
+#  define HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin)
+#else
+#  define HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_FEATURE)
+#  undef HEDLEY_HAS_FEATURE
+#endif
+#if defined(__has_feature)
+#  define HEDLEY_HAS_FEATURE(feature) __has_feature(feature)
+#else
+#  define HEDLEY_HAS_FEATURE(feature) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_FEATURE)
+#  undef HEDLEY_GNUC_HAS_FEATURE
+#endif
+#if defined(__has_feature)
+#  define HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature)
+#else
+#  define HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_FEATURE)
+#  undef HEDLEY_GCC_HAS_FEATURE
+#endif
+#if defined(__has_feature)
+#  define HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature)
+#else
+#  define HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_EXTENSION)
+#  undef HEDLEY_HAS_EXTENSION
+#endif
+#if defined(__has_extension)
+#  define HEDLEY_HAS_EXTENSION(extension) __has_extension(extension)
+#else
+#  define HEDLEY_HAS_EXTENSION(extension) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_EXTENSION)
+#  undef HEDLEY_GNUC_HAS_EXTENSION
+#endif
+#if defined(__has_extension)
+#  define HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension)
+#else
+#  define HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_EXTENSION)
+#  undef HEDLEY_GCC_HAS_EXTENSION
+#endif
+#if defined(__has_extension)
+#  define HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension)
+#else
+#  define HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_DECLSPEC_ATTRIBUTE)
+#  undef HEDLEY_HAS_DECLSPEC_ATTRIBUTE
+#endif
+#if defined(__has_declspec_attribute)
+#  define HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) __has_declspec_attribute(attribute)
+#else
+#  define HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE)
+#  undef HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE
+#endif
+#if defined(__has_declspec_attribute)
+#  define HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute)
+#else
+#  define HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE)
+#  undef HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE
+#endif
+#if defined(__has_declspec_attribute)
+#  define HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute)
+#else
+#  define HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_HAS_WARNING)
+#  undef HEDLEY_HAS_WARNING
+#endif
+#if defined(__has_warning)
+#  define HEDLEY_HAS_WARNING(warning) __has_warning(warning)
+#else
+#  define HEDLEY_HAS_WARNING(warning) (0)
+#endif
+
+#if defined(HEDLEY_GNUC_HAS_WARNING)
+#  undef HEDLEY_GNUC_HAS_WARNING
+#endif
+#if defined(__has_warning)
+#  define HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning)
+#else
+#  define HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) HEDLEY_GNUC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_GCC_HAS_WARNING)
+#  undef HEDLEY_GCC_HAS_WARNING
+#endif
+#if defined(__has_warning)
+#  define HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning)
+#else
+#  define HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if \
+  (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \
+  defined(__clang__) || \
+  HEDLEY_GCC_VERSION_CHECK(3,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_IAR_VERSION_CHECK(8,0,0) || \
+  HEDLEY_PGI_VERSION_CHECK(18,4,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,0,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_CRAY_VERSION_CHECK(5,0,0) || \
+  HEDLEY_TINYC_VERSION_CHECK(0,9,17) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(8,0,0) || \
+  (HEDLEY_IBM_VERSION_CHECK(10,1,0) && defined(__C99_PRAGMA_OPERATOR))
+#  define HEDLEY_PRAGMA(value) _Pragma(#value)
+#elif HEDLEY_MSVC_VERSION_CHECK(15,0,0)
+#  define HEDLEY_PRAGMA(value) __pragma(value)
+#else
+#  define HEDLEY_PRAGMA(value)
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_PUSH)
+#  undef HEDLEY_DIAGNOSTIC_PUSH
+#endif
+#if defined(HEDLEY_DIAGNOSTIC_POP)
+#  undef HEDLEY_DIAGNOSTIC_POP
+#endif
+#if defined(__clang__)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("clang diagnostic push")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("clang diagnostic pop")
+#elif HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)")
+#elif HEDLEY_GCC_VERSION_CHECK(4,6,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("GCC diagnostic push")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("GCC diagnostic pop")
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH __pragma(warning(push))
+#  define HEDLEY_DIAGNOSTIC_POP __pragma(warning(pop))
+#elif HEDLEY_ARM_VERSION_CHECK(5,6,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("push")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("pop")
+#elif \
+    HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+    HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+    HEDLEY_TI_CL430_VERSION_CHECK(4,4,0) || \
+    HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \
+    HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+    HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("diag_push")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("diag_pop")
+#elif HEDLEY_PELLES_VERSION_CHECK(2,90,0)
+#  define HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)")
+#  define HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)")
+#else
+#  define HEDLEY_DIAGNOSTIC_PUSH
+#  define HEDLEY_DIAGNOSTIC_POP
+#endif
+
+/* HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_ is for
+   HEDLEY INTERNAL USE ONLY.  API subject to change without notice. */
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_
+#endif
+#if defined(__cplusplus)
+#  if HEDLEY_HAS_WARNING("-Wc++98-compat")
+#    if HEDLEY_HAS_WARNING("-Wc++17-extensions")
+#      if HEDLEY_HAS_WARNING("-Wc++1z-extensions")
+#        define HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \
+           HEDLEY_DIAGNOSTIC_PUSH \
+           _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \
+           _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \
+           _Pragma("clang diagnostic ignored \"-Wc++1z-extensions\"") \
+           xpr \
+           HEDLEY_DIAGNOSTIC_POP
+#      else
+#        define HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \
+           HEDLEY_DIAGNOSTIC_PUSH \
+           _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \
+           _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \
+           xpr \
+           HEDLEY_DIAGNOSTIC_POP
+#      endif
+#    else
+#      define HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \
+         HEDLEY_DIAGNOSTIC_PUSH \
+         _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \
+         xpr \
+         HEDLEY_DIAGNOSTIC_POP
+#    endif
+#  endif
+#endif
+#if !defined(HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(x) x
+#endif
+
+#if defined(HEDLEY_CONST_CAST)
+#  undef HEDLEY_CONST_CAST
+#endif
+#if defined(__cplusplus)
+#  define HEDLEY_CONST_CAST(T, expr) (const_cast<T>(expr))
+#elif \
+  HEDLEY_HAS_WARNING("-Wcast-qual") || \
+  HEDLEY_GCC_VERSION_CHECK(4,6,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_CONST_CAST(T, expr) (__extension__ ({ \
+      HEDLEY_DIAGNOSTIC_PUSH \
+      HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL \
+      ((T) (expr)); \
+      HEDLEY_DIAGNOSTIC_POP \
+    }))
+#else
+#  define HEDLEY_CONST_CAST(T, expr) ((T) (expr))
+#endif
+
+#if defined(HEDLEY_REINTERPRET_CAST)
+#  undef HEDLEY_REINTERPRET_CAST
+#endif
+#if defined(__cplusplus)
+#  define HEDLEY_REINTERPRET_CAST(T, expr) (reinterpret_cast<T>(expr))
+#else
+#  define HEDLEY_REINTERPRET_CAST(T, expr) ((T) (expr))
+#endif
+
+#if defined(HEDLEY_STATIC_CAST)
+#  undef HEDLEY_STATIC_CAST
+#endif
+#if defined(__cplusplus)
+#  define HEDLEY_STATIC_CAST(T, expr) (static_cast<T>(expr))
+#else
+#  define HEDLEY_STATIC_CAST(T, expr) ((T) (expr))
+#endif
+
+#if defined(HEDLEY_CPP_CAST)
+#  undef HEDLEY_CPP_CAST
+#endif
+#if defined(__cplusplus)
+#  if HEDLEY_HAS_WARNING("-Wold-style-cast")
+#    define HEDLEY_CPP_CAST(T, expr) \
+       HEDLEY_DIAGNOSTIC_PUSH \
+       _Pragma("clang diagnostic ignored \"-Wold-style-cast\"") \
+       ((T) (expr)) \
+       HEDLEY_DIAGNOSTIC_POP
+#  elif HEDLEY_IAR_VERSION_CHECK(8,3,0)
+#    define HEDLEY_CPP_CAST(T, expr) \
+       HEDLEY_DIAGNOSTIC_PUSH \
+       _Pragma("diag_suppress=Pe137") \
+       HEDLEY_DIAGNOSTIC_POP
+#  else
+#    define HEDLEY_CPP_CAST(T, expr) ((T) (expr))
+#  endif
+#else
+#  define HEDLEY_CPP_CAST(T, expr) (expr)
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED
+#endif
+#if HEDLEY_HAS_WARNING("-Wdeprecated-declarations")
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("clang diagnostic ignored \"-Wdeprecated-declarations\"")
+#elif HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warning(disable:1478 1786)")
+#elif HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:1478 1786))
+#elif HEDLEY_PGI_VERSION_CHECK(20,7,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1216,1444,1445")
+#elif HEDLEY_PGI_VERSION_CHECK(17,10,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444")
+#elif HEDLEY_GCC_VERSION_CHECK(4,3,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"")
+#elif HEDLEY_MSVC_VERSION_CHECK(15,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:4996))
+#elif HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444")
+#elif \
+    HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+    (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+    HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+    (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+    HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+    (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+    HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+    (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+    HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+    HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+    HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1291,1718")
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && !defined(__cplusplus)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,E_DEPRECATED_ATT,E_DEPRECATED_ATT_MESS)")
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && defined(__cplusplus)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,symdeprecated,symdeprecated2)")
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress=Pe1444,Pe1215")
+#elif HEDLEY_PELLES_VERSION_CHECK(2,90,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warn(disable:2241)")
+#else
+#  define HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS
+#endif
+#if HEDLEY_HAS_WARNING("-Wunknown-pragmas")
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("clang diagnostic ignored \"-Wunknown-pragmas\"")
+#elif HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("warning(disable:161)")
+#elif HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:161))
+#elif HEDLEY_PGI_VERSION_CHECK(17,10,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 1675")
+#elif HEDLEY_GCC_VERSION_CHECK(4,3,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("GCC diagnostic ignored \"-Wunknown-pragmas\"")
+#elif HEDLEY_MSVC_VERSION_CHECK(15,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:4068))
+#elif \
+    HEDLEY_TI_VERSION_CHECK(16,9,0) || \
+    HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \
+    HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+    HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163")
+#elif HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163")
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress=Pe161")
+#elif HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 161")
+#else
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES
+#endif
+#if HEDLEY_HAS_WARNING("-Wunknown-attributes")
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("clang diagnostic ignored \"-Wunknown-attributes\"")
+#elif HEDLEY_GCC_VERSION_CHECK(4,6,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"")
+#elif HEDLEY_INTEL_VERSION_CHECK(17,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("warning(disable:1292)")
+#elif HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:1292))
+#elif HEDLEY_MSVC_VERSION_CHECK(19,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:5030))
+#elif HEDLEY_PGI_VERSION_CHECK(20,7,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097,1098")
+#elif HEDLEY_PGI_VERSION_CHECK(17,10,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097")
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("error_messages(off,attrskipunsup)")
+#elif \
+    HEDLEY_TI_VERSION_CHECK(18,1,0) || \
+    HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \
+    HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1173")
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress=Pe1097")
+#elif HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097")
+#else
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL
+#endif
+#if HEDLEY_HAS_WARNING("-Wcast-qual")
+#  define HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("clang diagnostic ignored \"-Wcast-qual\"")
+#elif HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("warning(disable:2203 2331)")
+#elif HEDLEY_GCC_VERSION_CHECK(3,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
+#else
+#  define HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL
+#endif
+
+#if defined(HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION)
+#  undef HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION
+#endif
+#if HEDLEY_HAS_WARNING("-Wunused-function")
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("clang diagnostic ignored \"-Wunused-function\"")
+#elif HEDLEY_GCC_VERSION_CHECK(3,4,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("GCC diagnostic ignored \"-Wunused-function\"")
+#elif HEDLEY_MSVC_VERSION_CHECK(1,0,0)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION __pragma(warning(disable:4505))
+#elif HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("diag_suppress 3142")
+#else
+#  define HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION
+#endif
+
+#if defined(HEDLEY_DEPRECATED)
+#  undef HEDLEY_DEPRECATED
+#endif
+#if defined(HEDLEY_DEPRECATED_FOR)
+#  undef HEDLEY_DEPRECATED_FOR
+#endif
+#if \
+  HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DEPRECATED(since) __declspec(deprecated("Since " # since))
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated("Since " #since "; use " #replacement))
+#elif \
+  (HEDLEY_HAS_EXTENSION(attribute_deprecated_with_message) && !defined(HEDLEY_IAR_VERSION)) || \
+  HEDLEY_GCC_VERSION_CHECK(4,5,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_ARM_VERSION_CHECK(5,6,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) || \
+  HEDLEY_PGI_VERSION_CHECK(17,10,0) || \
+  HEDLEY_TI_VERSION_CHECK(18,1,0) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(18,1,0) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_DEPRECATED(since) __attribute__((__deprecated__("Since " #since)))
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__("Since " #since "; use " #replacement)))
+#elif defined(__cplusplus) && (__cplusplus >= 201402L)
+#  define HEDLEY_DEPRECATED(since) HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since)]])
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since "; use " #replacement)]])
+#elif \
+  HEDLEY_HAS_ATTRIBUTE(deprecated) || \
+  HEDLEY_GCC_VERSION_CHECK(3,1,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \
+  HEDLEY_IAR_VERSION_CHECK(8,10,0)
+#  define HEDLEY_DEPRECATED(since) __attribute__((__deprecated__))
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__))
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \
+  HEDLEY_PELLES_VERSION_CHECK(6,50,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_DEPRECATED(since) __declspec(deprecated)
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated)
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_DEPRECATED(since) _Pragma("deprecated")
+#  define HEDLEY_DEPRECATED_FOR(since, replacement) _Pragma("deprecated")
+#else
+#  define HEDLEY_DEPRECATED(since)
+#  define HEDLEY_DEPRECATED_FOR(since, replacement)
+#endif
+
+#if defined(HEDLEY_UNAVAILABLE)
+#  undef HEDLEY_UNAVAILABLE
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(warning) || \
+  HEDLEY_GCC_VERSION_CHECK(4,3,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_UNAVAILABLE(available_since) __attribute__((__warning__("Not available until " #available_since)))
+#else
+#  define HEDLEY_UNAVAILABLE(available_since)
+#endif
+
+#if defined(HEDLEY_WARN_UNUSED_RESULT)
+#  undef HEDLEY_WARN_UNUSED_RESULT
+#endif
+#if defined(HEDLEY_WARN_UNUSED_RESULT_MSG)
+#  undef HEDLEY_WARN_UNUSED_RESULT_MSG
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(warn_unused_result) || \
+  HEDLEY_GCC_VERSION_CHECK(3,4,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  (HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \
+  HEDLEY_PGI_VERSION_CHECK(17,10,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_WARN_UNUSED_RESULT __attribute__((__warn_unused_result__))
+#  define HEDLEY_WARN_UNUSED_RESULT_MSG(msg) __attribute__((__warn_unused_result__))
+#elif (HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard) >= 201907L)
+#  define HEDLEY_WARN_UNUSED_RESULT HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]])
+#  define HEDLEY_WARN_UNUSED_RESULT_MSG(msg) HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard(msg)]])
+#elif HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard)
+#  define HEDLEY_WARN_UNUSED_RESULT HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]])
+#  define HEDLEY_WARN_UNUSED_RESULT_MSG(msg) HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]])
+#elif defined(_Check_return_) /* SAL */
+#  define HEDLEY_WARN_UNUSED_RESULT _Check_return_
+#  define HEDLEY_WARN_UNUSED_RESULT_MSG(msg) _Check_return_
+#else
+#  define HEDLEY_WARN_UNUSED_RESULT
+#  define HEDLEY_WARN_UNUSED_RESULT_MSG(msg)
+#endif
+
+#if defined(HEDLEY_SENTINEL)
+#  undef HEDLEY_SENTINEL
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(sentinel) || \
+  HEDLEY_GCC_VERSION_CHECK(4,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_ARM_VERSION_CHECK(5,4,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_SENTINEL(position) __attribute__((__sentinel__(position)))
+#else
+#  define HEDLEY_SENTINEL(position)
+#endif
+
+#if defined(HEDLEY_NO_RETURN)
+#  undef HEDLEY_NO_RETURN
+#endif
+#if HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_NO_RETURN __noreturn
+#elif \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_NO_RETURN __attribute__((__noreturn__))
+#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
+#  define HEDLEY_NO_RETURN _Noreturn
+#elif defined(__cplusplus) && (__cplusplus >= 201103L)
+#  define HEDLEY_NO_RETURN HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[noreturn]])
+#elif \
+  HEDLEY_HAS_ATTRIBUTE(noreturn) || \
+  HEDLEY_GCC_VERSION_CHECK(3,2,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_IAR_VERSION_CHECK(8,10,0)
+#  define HEDLEY_NO_RETURN __attribute__((__noreturn__))
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,10,0)
+#  define HEDLEY_NO_RETURN _Pragma("does_not_return")
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_NO_RETURN __declspec(noreturn)
+#elif HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus)
+#  define HEDLEY_NO_RETURN _Pragma("FUNC_NEVER_RETURNS;")
+#elif HEDLEY_COMPCERT_VERSION_CHECK(3,2,0)
+#  define HEDLEY_NO_RETURN __attribute((noreturn))
+#elif HEDLEY_PELLES_VERSION_CHECK(9,0,0)
+#  define HEDLEY_NO_RETURN __declspec(noreturn)
+#else
+#  define HEDLEY_NO_RETURN
+#endif
+
+#if defined(HEDLEY_NO_ESCAPE)
+#  undef HEDLEY_NO_ESCAPE
+#endif
+#if HEDLEY_HAS_ATTRIBUTE(noescape)
+#  define HEDLEY_NO_ESCAPE __attribute__((__noescape__))
+#else
+#  define HEDLEY_NO_ESCAPE
+#endif
+
+#if defined(HEDLEY_UNREACHABLE)
+#  undef HEDLEY_UNREACHABLE
+#endif
+#if defined(HEDLEY_UNREACHABLE_RETURN)
+#  undef HEDLEY_UNREACHABLE_RETURN
+#endif
+#if defined(HEDLEY_ASSUME)
+#  undef HEDLEY_ASSUME
+#endif
+#if \
+  HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_ASSUME(expr) __assume(expr)
+#elif HEDLEY_HAS_BUILTIN(__builtin_assume)
+#  define HEDLEY_ASSUME(expr) __builtin_assume(expr)
+#elif \
+    HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \
+    HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0)
+#  if defined(__cplusplus)
+#    define HEDLEY_ASSUME(expr) std::_nassert(expr)
+#  else
+#    define HEDLEY_ASSUME(expr) _nassert(expr)
+#  endif
+#endif
+#if \
+  (HEDLEY_HAS_BUILTIN(__builtin_unreachable) && (!defined(HEDLEY_ARM_VERSION))) || \
+  HEDLEY_GCC_VERSION_CHECK(4,5,0) || \
+  HEDLEY_PGI_VERSION_CHECK(18,10,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_IBM_VERSION_CHECK(13,1,5) || \
+  HEDLEY_CRAY_VERSION_CHECK(10,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_UNREACHABLE() __builtin_unreachable()
+#elif defined(HEDLEY_ASSUME)
+#  define HEDLEY_UNREACHABLE() HEDLEY_ASSUME(0)
+#endif
+#if !defined(HEDLEY_ASSUME)
+#  if defined(HEDLEY_UNREACHABLE)
+#    define HEDLEY_ASSUME(expr) HEDLEY_STATIC_CAST(void, ((expr) ? 1 : (HEDLEY_UNREACHABLE(), 1)))
+#  else
+#    define HEDLEY_ASSUME(expr) HEDLEY_STATIC_CAST(void, expr)
+#  endif
+#endif
+#if defined(HEDLEY_UNREACHABLE)
+#  if  \
+      HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \
+      HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0)
+#    define HEDLEY_UNREACHABLE_RETURN(value) return (HEDLEY_STATIC_CAST(void, HEDLEY_ASSUME(0)), (value))
+#  else
+#    define HEDLEY_UNREACHABLE_RETURN(value) HEDLEY_UNREACHABLE()
+#  endif
+#else
+#  define HEDLEY_UNREACHABLE_RETURN(value) return (value)
+#endif
+#if !defined(HEDLEY_UNREACHABLE)
+#  define HEDLEY_UNREACHABLE() HEDLEY_ASSUME(0)
+#endif
+
+HEDLEY_DIAGNOSTIC_PUSH
+#if HEDLEY_HAS_WARNING("-Wpedantic")
+#  pragma clang diagnostic ignored "-Wpedantic"
+#endif
+#if HEDLEY_HAS_WARNING("-Wc++98-compat-pedantic") && defined(__cplusplus)
+#  pragma clang diagnostic ignored "-Wc++98-compat-pedantic"
+#endif
+#if HEDLEY_GCC_HAS_WARNING("-Wvariadic-macros",4,0,0)
+#  if defined(__clang__)
+#    pragma clang diagnostic ignored "-Wvariadic-macros"
+#  elif defined(HEDLEY_GCC_VERSION)
+#    pragma GCC diagnostic ignored "-Wvariadic-macros"
+#  endif
+#endif
+#if defined(HEDLEY_NON_NULL)
+#  undef HEDLEY_NON_NULL
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(nonnull) || \
+  HEDLEY_GCC_VERSION_CHECK(3,3,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0)
+#  define HEDLEY_NON_NULL(...) __attribute__((__nonnull__(__VA_ARGS__)))
+#else
+#  define HEDLEY_NON_NULL(...)
+#endif
+HEDLEY_DIAGNOSTIC_POP
+
+#if defined(HEDLEY_PRINTF_FORMAT)
+#  undef HEDLEY_PRINTF_FORMAT
+#endif
+#if defined(__MINGW32__) && HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && !defined(__USE_MINGW_ANSI_STDIO)
+#  define HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(ms_printf, string_idx, first_to_check)))
+#elif defined(__MINGW32__) && HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && defined(__USE_MINGW_ANSI_STDIO)
+#  define HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(gnu_printf, string_idx, first_to_check)))
+#elif \
+  HEDLEY_HAS_ATTRIBUTE(format) || \
+  HEDLEY_GCC_VERSION_CHECK(3,1,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_ARM_VERSION_CHECK(5,6,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(__printf__, string_idx, first_to_check)))
+#elif HEDLEY_PELLES_VERSION_CHECK(6,0,0)
+#  define HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __declspec(vaformat(printf,string_idx,first_to_check))
+#else
+#  define HEDLEY_PRINTF_FORMAT(string_idx,first_to_check)
+#endif
+
+#if defined(HEDLEY_CONSTEXPR)
+#  undef HEDLEY_CONSTEXPR
+#endif
+#if defined(__cplusplus)
+#  if __cplusplus >= 201103L
+#    define HEDLEY_CONSTEXPR HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(constexpr)
+#  endif
+#endif
+#if !defined(HEDLEY_CONSTEXPR)
+#  define HEDLEY_CONSTEXPR
+#endif
+
+#if defined(HEDLEY_PREDICT)
+#  undef HEDLEY_PREDICT
+#endif
+#if defined(HEDLEY_LIKELY)
+#  undef HEDLEY_LIKELY
+#endif
+#if defined(HEDLEY_UNLIKELY)
+#  undef HEDLEY_UNLIKELY
+#endif
+#if defined(HEDLEY_UNPREDICTABLE)
+#  undef HEDLEY_UNPREDICTABLE
+#endif
+#if HEDLEY_HAS_BUILTIN(__builtin_unpredictable)
+#  define HEDLEY_UNPREDICTABLE(expr) __builtin_unpredictable((expr))
+#endif
+#if \
+  (HEDLEY_HAS_BUILTIN(__builtin_expect_with_probability) && !defined(HEDLEY_PGI_VERSION)) || \
+  HEDLEY_GCC_VERSION_CHECK(9,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_PREDICT(expr, value, probability) __builtin_expect_with_probability(  (expr), (value), (probability))
+#  define HEDLEY_PREDICT_TRUE(expr, probability)   __builtin_expect_with_probability(!!(expr),    1   , (probability))
+#  define HEDLEY_PREDICT_FALSE(expr, probability)  __builtin_expect_with_probability(!!(expr),    0   , (probability))
+#  define HEDLEY_LIKELY(expr)                      __builtin_expect                 (!!(expr),    1                  )
+#  define HEDLEY_UNLIKELY(expr)                    __builtin_expect                 (!!(expr),    0                  )
+#elif \
+  (HEDLEY_HAS_BUILTIN(__builtin_expect) && !defined(HEDLEY_INTEL_CL_VERSION)) || \
+  HEDLEY_GCC_VERSION_CHECK(3,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  (HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_TINYC_VERSION_CHECK(0,9,27) || \
+  HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_PREDICT(expr, expected, probability) \
+     (((probability) >= 0.9) ? __builtin_expect((expr), (expected)) : (HEDLEY_STATIC_CAST(void, expected), (expr)))
+#  define HEDLEY_PREDICT_TRUE(expr, probability) \
+     (__extension__ ({ \
+       double hedley_probability_ = (probability); \
+       ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 1) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 0) : !!(expr))); \
+     }))
+#  define HEDLEY_PREDICT_FALSE(expr, probability) \
+     (__extension__ ({ \
+       double hedley_probability_ = (probability); \
+       ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 0) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 1) : !!(expr))); \
+     }))
+#  define HEDLEY_LIKELY(expr)   __builtin_expect(!!(expr), 1)
+#  define HEDLEY_UNLIKELY(expr) __builtin_expect(!!(expr), 0)
+#else
+#  define HEDLEY_PREDICT(expr, expected, probability) (HEDLEY_STATIC_CAST(void, expected), (expr))
+#  define HEDLEY_PREDICT_TRUE(expr, probability) (!!(expr))
+#  define HEDLEY_PREDICT_FALSE(expr, probability) (!!(expr))
+#  define HEDLEY_LIKELY(expr) (!!(expr))
+#  define HEDLEY_UNLIKELY(expr) (!!(expr))
+#endif
+#if !defined(HEDLEY_UNPREDICTABLE)
+#  define HEDLEY_UNPREDICTABLE(expr) HEDLEY_PREDICT(expr, 1, 0.5)
+#endif
+
+#if defined(HEDLEY_MALLOC)
+#  undef HEDLEY_MALLOC
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(malloc) || \
+  HEDLEY_GCC_VERSION_CHECK(3,1,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(12,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_MALLOC __attribute__((__malloc__))
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,10,0)
+#  define HEDLEY_MALLOC _Pragma("returns_new_memory")
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_MALLOC __declspec(restrict)
+#else
+#  define HEDLEY_MALLOC
+#endif
+
+#if defined(HEDLEY_PURE)
+#  undef HEDLEY_PURE
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(pure) || \
+  HEDLEY_GCC_VERSION_CHECK(2,96,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_PGI_VERSION_CHECK(17,10,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_PURE __attribute__((__pure__))
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,10,0)
+#  define HEDLEY_PURE _Pragma("does_not_write_global_data")
+#elif defined(__cplusplus) && \
+    ( \
+      HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \
+      HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) || \
+      HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) \
+    )
+#  define HEDLEY_PURE _Pragma("FUNC_IS_PURE;")
+#else
+#  define HEDLEY_PURE
+#endif
+
+#if defined(HEDLEY_CONST)
+#  undef HEDLEY_CONST
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(const) || \
+  HEDLEY_GCC_VERSION_CHECK(2,5,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_PGI_VERSION_CHECK(17,10,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_CONST __attribute__((__const__))
+#elif \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,10,0)
+#  define HEDLEY_CONST _Pragma("no_side_effect")
+#else
+#  define HEDLEY_CONST HEDLEY_PURE
+#endif
+
+#if defined(HEDLEY_RESTRICT)
+#  undef HEDLEY_RESTRICT
+#endif
+#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && !defined(__cplusplus)
+#  define HEDLEY_RESTRICT restrict
+#elif \
+  HEDLEY_GCC_VERSION_CHECK(3,1,0) || \
+  HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_PGI_VERSION_CHECK(17,10,0) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,2,4) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  (HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus)) || \
+  HEDLEY_IAR_VERSION_CHECK(8,0,0) || \
+  defined(__clang__) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_RESTRICT __restrict
+#elif HEDLEY_SUNPRO_VERSION_CHECK(5,3,0) && !defined(__cplusplus)
+#  define HEDLEY_RESTRICT _Restrict
+#else
+#  define HEDLEY_RESTRICT
+#endif
+
+#if defined(HEDLEY_INLINE)
+#  undef HEDLEY_INLINE
+#endif
+#if \
+  (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \
+  (defined(__cplusplus) && (__cplusplus >= 199711L))
+#  define HEDLEY_INLINE inline
+#elif \
+  defined(HEDLEY_GCC_VERSION) || \
+  HEDLEY_ARM_VERSION_CHECK(6,2,0)
+#  define HEDLEY_INLINE __inline__
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,1,0) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_INLINE __inline
+#else
+#  define HEDLEY_INLINE
+#endif
+
+#if defined(HEDLEY_ALWAYS_INLINE)
+#  undef HEDLEY_ALWAYS_INLINE
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(always_inline) || \
+  HEDLEY_GCC_VERSION_CHECK(4,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \
+  HEDLEY_IAR_VERSION_CHECK(8,10,0)
+#  define HEDLEY_ALWAYS_INLINE __attribute__((__always_inline__)) HEDLEY_INLINE
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_ALWAYS_INLINE __forceinline
+#elif defined(__cplusplus) && \
+    ( \
+      HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+      HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+      HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+      HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \
+      HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+      HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) \
+    )
+#  define HEDLEY_ALWAYS_INLINE _Pragma("FUNC_ALWAYS_INLINE;")
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_ALWAYS_INLINE _Pragma("inline=forced")
+#else
+#  define HEDLEY_ALWAYS_INLINE HEDLEY_INLINE
+#endif
+
+#if defined(HEDLEY_NEVER_INLINE)
+#  undef HEDLEY_NEVER_INLINE
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(noinline) || \
+  HEDLEY_GCC_VERSION_CHECK(4,0,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(10,1,0) || \
+  HEDLEY_TI_VERSION_CHECK(15,12,0) || \
+  (HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \
+  (HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \
+  (HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \
+  (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \
+  HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \
+  HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \
+  HEDLEY_IAR_VERSION_CHECK(8,10,0)
+#  define HEDLEY_NEVER_INLINE __attribute__((__noinline__))
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_NEVER_INLINE __declspec(noinline)
+#elif HEDLEY_PGI_VERSION_CHECK(10,2,0)
+#  define HEDLEY_NEVER_INLINE _Pragma("noinline")
+#elif HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus)
+#  define HEDLEY_NEVER_INLINE _Pragma("FUNC_CANNOT_INLINE;")
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_NEVER_INLINE _Pragma("inline=never")
+#elif HEDLEY_COMPCERT_VERSION_CHECK(3,2,0)
+#  define HEDLEY_NEVER_INLINE __attribute((noinline))
+#elif HEDLEY_PELLES_VERSION_CHECK(9,0,0)
+#  define HEDLEY_NEVER_INLINE __declspec(noinline)
+#else
+#  define HEDLEY_NEVER_INLINE
+#endif
+
+#if defined(HEDLEY_PRIVATE)
+#  undef HEDLEY_PRIVATE
+#endif
+#if defined(HEDLEY_PUBLIC)
+#  undef HEDLEY_PUBLIC
+#endif
+#if defined(HEDLEY_IMPORT)
+#  undef HEDLEY_IMPORT
+#endif
+#if defined(_WIN32) || defined(__CYGWIN__)
+#  define HEDLEY_PRIVATE
+#  define HEDLEY_PUBLIC   __declspec(dllexport)
+#  define HEDLEY_IMPORT   __declspec(dllimport)
+#else
+#  if \
+    HEDLEY_HAS_ATTRIBUTE(visibility) || \
+    HEDLEY_GCC_VERSION_CHECK(3,3,0) || \
+    HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \
+    HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+    HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+    HEDLEY_IBM_VERSION_CHECK(13,1,0) || \
+    ( \
+      defined(__TI_EABI__) && \
+      ( \
+        (HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \
+        HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) \
+      ) \
+    ) || \
+    HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#    define HEDLEY_PRIVATE __attribute__((__visibility__("hidden")))
+#    define HEDLEY_PUBLIC  __attribute__((__visibility__("default")))
+#  else
+#    define HEDLEY_PRIVATE
+#    define HEDLEY_PUBLIC
+#  endif
+#  define HEDLEY_IMPORT    extern
+#endif
+
+#if defined(HEDLEY_NO_THROW)
+#  undef HEDLEY_NO_THROW
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(nothrow) || \
+  HEDLEY_GCC_VERSION_CHECK(3,3,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_NO_THROW __attribute__((__nothrow__))
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(13,1,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0)
+#  define HEDLEY_NO_THROW __declspec(nothrow)
+#else
+#  define HEDLEY_NO_THROW
+#endif
+
+#if defined(HEDLEY_FALL_THROUGH)
+# undef HEDLEY_FALL_THROUGH
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(fallthrough) || \
+  HEDLEY_GCC_VERSION_CHECK(7,0,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_FALL_THROUGH __attribute__((__fallthrough__))
+#elif HEDLEY_HAS_CPP_ATTRIBUTE_NS(clang,fallthrough)
+#  define HEDLEY_FALL_THROUGH HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[clang::fallthrough]])
+#elif HEDLEY_HAS_CPP_ATTRIBUTE(fallthrough)
+#  define HEDLEY_FALL_THROUGH HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[fallthrough]])
+#elif defined(__fallthrough) /* SAL */
+#  define HEDLEY_FALL_THROUGH __fallthrough
+#else
+#  define HEDLEY_FALL_THROUGH
+#endif
+
+#if defined(HEDLEY_RETURNS_NON_NULL)
+#  undef HEDLEY_RETURNS_NON_NULL
+#endif
+#if \
+  HEDLEY_HAS_ATTRIBUTE(returns_nonnull) || \
+  HEDLEY_GCC_VERSION_CHECK(4,9,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_RETURNS_NON_NULL __attribute__((__returns_nonnull__))
+#elif defined(_Ret_notnull_) /* SAL */
+#  define HEDLEY_RETURNS_NON_NULL _Ret_notnull_
+#else
+#  define HEDLEY_RETURNS_NON_NULL
+#endif
+
+#if defined(HEDLEY_ARRAY_PARAM)
+#  undef HEDLEY_ARRAY_PARAM
+#endif
+#if \
+  defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && \
+  !defined(__STDC_NO_VLA__) && \
+  !defined(__cplusplus) && \
+  !defined(HEDLEY_PGI_VERSION) && \
+  !defined(HEDLEY_TINYC_VERSION)
+#  define HEDLEY_ARRAY_PARAM(name) (name)
+#else
+#  define HEDLEY_ARRAY_PARAM(name)
+#endif
+
+#if defined(HEDLEY_IS_CONSTANT)
+#  undef HEDLEY_IS_CONSTANT
+#endif
+#if defined(HEDLEY_REQUIRE_CONSTEXPR)
+#  undef HEDLEY_REQUIRE_CONSTEXPR
+#endif
+/* HEDLEY_IS_CONSTEXPR_ is for
+   HEDLEY INTERNAL USE ONLY.  API subject to change without notice. */
+#if defined(HEDLEY_IS_CONSTEXPR_)
+#  undef HEDLEY_IS_CONSTEXPR_
+#endif
+#if \
+  HEDLEY_HAS_BUILTIN(__builtin_constant_p) || \
+  HEDLEY_GCC_VERSION_CHECK(3,4,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+  HEDLEY_TINYC_VERSION_CHECK(0,9,19) || \
+  HEDLEY_ARM_VERSION_CHECK(4,1,0) || \
+  HEDLEY_IBM_VERSION_CHECK(13,1,0) || \
+  HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \
+  (HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) && !defined(__cplusplus)) || \
+  HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \
+  HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10)
+#  define HEDLEY_IS_CONSTANT(expr) __builtin_constant_p(expr)
+#endif
+#if !defined(__cplusplus)
+#  if \
+       HEDLEY_HAS_BUILTIN(__builtin_types_compatible_p) || \
+       HEDLEY_GCC_VERSION_CHECK(3,4,0) || \
+       HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+       HEDLEY_IBM_VERSION_CHECK(13,1,0) || \
+       HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \
+       HEDLEY_ARM_VERSION_CHECK(5,4,0) || \
+       HEDLEY_TINYC_VERSION_CHECK(0,9,24)
+#    if defined(__INTPTR_TYPE__)
+#      define HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0)), int*)
+#    else
+#      include <stdint.h>
+#      define HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((intptr_t) ((expr) * 0)) : (int*) 0)), int*)
+#    endif
+#  elif \
+       ( \
+          defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) && \
+          !defined(HEDLEY_SUNPRO_VERSION) && \
+          !defined(HEDLEY_PGI_VERSION) && \
+          !defined(HEDLEY_IAR_VERSION)) || \
+       (HEDLEY_HAS_EXTENSION(c_generic_selections) && !defined(HEDLEY_IAR_VERSION)) || \
+       HEDLEY_GCC_VERSION_CHECK(4,9,0) || \
+       HEDLEY_INTEL_VERSION_CHECK(17,0,0) || \
+       HEDLEY_IBM_VERSION_CHECK(12,1,0) || \
+       HEDLEY_ARM_VERSION_CHECK(5,3,0)
+#    if defined(__INTPTR_TYPE__)
+#      define HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0), int*: 1, void*: 0)
+#    else
+#      include <stdint.h>
+#      define HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((intptr_t) * 0) : (int*) 0), int*: 1, void*: 0)
+#    endif
+#  elif \
+       defined(HEDLEY_GCC_VERSION) || \
+       defined(HEDLEY_INTEL_VERSION) || \
+       defined(HEDLEY_TINYC_VERSION) || \
+       defined(HEDLEY_TI_ARMCL_VERSION) || \
+       HEDLEY_TI_CL430_VERSION_CHECK(18,12,0) || \
+       defined(HEDLEY_TI_CL2000_VERSION) || \
+       defined(HEDLEY_TI_CL6X_VERSION) || \
+       defined(HEDLEY_TI_CL7X_VERSION) || \
+       defined(HEDLEY_TI_CLPRU_VERSION) || \
+       defined(__clang__)
+#    define HEDLEY_IS_CONSTEXPR_(expr) ( \
+         sizeof(void) != \
+         sizeof(*( \
+           1 ? \
+             ((void*) ((expr) * 0L) ) : \
+             ((struct { char v[sizeof(void) * 2]; } *) 1) \
+           ) \
+         ) \
+       )
+#  endif
+#endif
+#if defined(HEDLEY_IS_CONSTEXPR_)
+#  if !defined(HEDLEY_IS_CONSTANT)
+#    define HEDLEY_IS_CONSTANT(expr) HEDLEY_IS_CONSTEXPR_(expr)
+#  endif
+#  define HEDLEY_REQUIRE_CONSTEXPR(expr) (HEDLEY_IS_CONSTEXPR_(expr) ? (expr) : (-1))
+#else
+#  if !defined(HEDLEY_IS_CONSTANT)
+#    define HEDLEY_IS_CONSTANT(expr) (0)
+#  endif
+#  define HEDLEY_REQUIRE_CONSTEXPR(expr) (expr)
+#endif
+
+#if defined(HEDLEY_BEGIN_C_DECLS)
+#  undef HEDLEY_BEGIN_C_DECLS
+#endif
+#if defined(HEDLEY_END_C_DECLS)
+#  undef HEDLEY_END_C_DECLS
+#endif
+#if defined(HEDLEY_C_DECL)
+#  undef HEDLEY_C_DECL
+#endif
+#if defined(__cplusplus)
+#  define HEDLEY_BEGIN_C_DECLS extern "C" {
+#  define HEDLEY_END_C_DECLS }
+#  define HEDLEY_C_DECL extern "C"
+#else
+#  define HEDLEY_BEGIN_C_DECLS
+#  define HEDLEY_END_C_DECLS
+#  define HEDLEY_C_DECL
+#endif
+
+#if defined(HEDLEY_STATIC_ASSERT)
+#  undef HEDLEY_STATIC_ASSERT
+#endif
+#if \
+  !defined(__cplusplus) && ( \
+      (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)) || \
+      (HEDLEY_HAS_FEATURE(c_static_assert) && !defined(HEDLEY_INTEL_CL_VERSION)) || \
+      HEDLEY_GCC_VERSION_CHECK(6,0,0) || \
+      HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \
+      defined(_Static_assert) \
+    )
+#  define HEDLEY_STATIC_ASSERT(expr, message) _Static_assert(expr, message)
+#elif \
+  (defined(__cplusplus) && (__cplusplus >= 201103L)) || \
+  HEDLEY_MSVC_VERSION_CHECK(16,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_STATIC_ASSERT(expr, message) HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(static_assert(expr, message))
+#else
+#  define HEDLEY_STATIC_ASSERT(expr, message)
+#endif
+
+#if defined(HEDLEY_NULL)
+#  undef HEDLEY_NULL
+#endif
+#if defined(__cplusplus)
+#  if __cplusplus >= 201103L
+#    define HEDLEY_NULL HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(nullptr)
+#  elif defined(NULL)
+#    define HEDLEY_NULL NULL
+#  else
+#    define HEDLEY_NULL HEDLEY_STATIC_CAST(void*, 0)
+#  endif
+#elif defined(NULL)
+#  define HEDLEY_NULL NULL
+#else
+#  define HEDLEY_NULL ((void*) 0)
+#endif
+
+#if defined(HEDLEY_MESSAGE)
+#  undef HEDLEY_MESSAGE
+#endif
+#if HEDLEY_HAS_WARNING("-Wunknown-pragmas")
+#  define HEDLEY_MESSAGE(msg) \
+  HEDLEY_DIAGNOSTIC_PUSH \
+  HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \
+  HEDLEY_PRAGMA(message msg) \
+  HEDLEY_DIAGNOSTIC_POP
+#elif \
+  HEDLEY_GCC_VERSION_CHECK(4,4,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_MESSAGE(msg) HEDLEY_PRAGMA(message msg)
+#elif HEDLEY_CRAY_VERSION_CHECK(5,0,0)
+#  define HEDLEY_MESSAGE(msg) HEDLEY_PRAGMA(_CRI message msg)
+#elif HEDLEY_IAR_VERSION_CHECK(8,0,0)
+#  define HEDLEY_MESSAGE(msg) HEDLEY_PRAGMA(message(msg))
+#elif HEDLEY_PELLES_VERSION_CHECK(2,0,0)
+#  define HEDLEY_MESSAGE(msg) HEDLEY_PRAGMA(message(msg))
+#else
+#  define HEDLEY_MESSAGE(msg)
+#endif
+
+#if defined(HEDLEY_WARNING)
+#  undef HEDLEY_WARNING
+#endif
+#if HEDLEY_HAS_WARNING("-Wunknown-pragmas")
+#  define HEDLEY_WARNING(msg) \
+  HEDLEY_DIAGNOSTIC_PUSH \
+  HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \
+  HEDLEY_PRAGMA(clang warning msg) \
+  HEDLEY_DIAGNOSTIC_POP
+#elif \
+  HEDLEY_GCC_VERSION_CHECK(4,8,0) || \
+  HEDLEY_PGI_VERSION_CHECK(18,4,0) || \
+  HEDLEY_INTEL_VERSION_CHECK(13,0,0)
+#  define HEDLEY_WARNING(msg) HEDLEY_PRAGMA(GCC warning msg)
+#elif \
+  HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_WARNING(msg) HEDLEY_PRAGMA(message(msg))
+#else
+#  define HEDLEY_WARNING(msg) HEDLEY_MESSAGE(msg)
+#endif
+
+#if defined(HEDLEY_REQUIRE)
+#  undef HEDLEY_REQUIRE
+#endif
+#if defined(HEDLEY_REQUIRE_MSG)
+#  undef HEDLEY_REQUIRE_MSG
+#endif
+#if HEDLEY_HAS_ATTRIBUTE(diagnose_if)
+#  if HEDLEY_HAS_WARNING("-Wgcc-compat")
+#    define HEDLEY_REQUIRE(expr) \
+       HEDLEY_DIAGNOSTIC_PUSH \
+       _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \
+       __attribute__((diagnose_if(!(expr), #expr, "error"))) \
+       HEDLEY_DIAGNOSTIC_POP
+#    define HEDLEY_REQUIRE_MSG(expr,msg) \
+       HEDLEY_DIAGNOSTIC_PUSH \
+       _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \
+       __attribute__((diagnose_if(!(expr), msg, "error"))) \
+       HEDLEY_DIAGNOSTIC_POP
+#  else
+#    define HEDLEY_REQUIRE(expr) __attribute__((diagnose_if(!(expr), #expr, "error")))
+#    define HEDLEY_REQUIRE_MSG(expr,msg) __attribute__((diagnose_if(!(expr), msg, "error")))
+#  endif
+#else
+#  define HEDLEY_REQUIRE(expr)
+#  define HEDLEY_REQUIRE_MSG(expr,msg)
+#endif
+
+#if defined(HEDLEY_FLAGS)
+#  undef HEDLEY_FLAGS
+#endif
+#if HEDLEY_HAS_ATTRIBUTE(flag_enum) && (!defined(__cplusplus) || HEDLEY_HAS_WARNING("-Wbitfield-enum-conversion"))
+#  define HEDLEY_FLAGS __attribute__((__flag_enum__))
+#else
+#  define HEDLEY_FLAGS
+#endif
+
+#if defined(HEDLEY_FLAGS_CAST)
+#  undef HEDLEY_FLAGS_CAST
+#endif
+#if HEDLEY_INTEL_VERSION_CHECK(19,0,0)
+#  define HEDLEY_FLAGS_CAST(T, expr) (__extension__ ({ \
+  HEDLEY_DIAGNOSTIC_PUSH \
+      _Pragma("warning(disable:188)") \
+      ((T) (expr)); \
+      HEDLEY_DIAGNOSTIC_POP \
+    }))
+#else
+#  define HEDLEY_FLAGS_CAST(T, expr) HEDLEY_STATIC_CAST(T, expr)
+#endif
+
+#if defined(HEDLEY_EMPTY_BASES)
+#  undef HEDLEY_EMPTY_BASES
+#endif
+#if \
+  (HEDLEY_MSVC_VERSION_CHECK(19,0,23918) && !HEDLEY_MSVC_VERSION_CHECK(20,0,0)) || \
+  HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0)
+#  define HEDLEY_EMPTY_BASES __declspec(empty_bases)
+#else
+#  define HEDLEY_EMPTY_BASES
+#endif
+
+/* Remaining macros are deprecated. */
+
+#if defined(HEDLEY_GCC_NOT_CLANG_VERSION_CHECK)
+#  undef HEDLEY_GCC_NOT_CLANG_VERSION_CHECK
+#endif
+#if defined(__clang__)
+#  define HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) (0)
+#else
+#  define HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) HEDLEY_GCC_VERSION_CHECK(major,minor,patch)
+#endif
+
+#if defined(HEDLEY_CLANG_HAS_ATTRIBUTE)
+#  undef HEDLEY_CLANG_HAS_ATTRIBUTE
+#endif
+#define HEDLEY_CLANG_HAS_ATTRIBUTE(attribute) HEDLEY_HAS_ATTRIBUTE(attribute)
+
+#if defined(HEDLEY_CLANG_HAS_CPP_ATTRIBUTE)
+#  undef HEDLEY_CLANG_HAS_CPP_ATTRIBUTE
+#endif
+#define HEDLEY_CLANG_HAS_CPP_ATTRIBUTE(attribute) HEDLEY_HAS_CPP_ATTRIBUTE(attribute)
+
+#if defined(HEDLEY_CLANG_HAS_BUILTIN)
+#  undef HEDLEY_CLANG_HAS_BUILTIN
+#endif
+#define HEDLEY_CLANG_HAS_BUILTIN(builtin) HEDLEY_HAS_BUILTIN(builtin)
+
+#if defined(HEDLEY_CLANG_HAS_FEATURE)
+#  undef HEDLEY_CLANG_HAS_FEATURE
+#endif
+#define HEDLEY_CLANG_HAS_FEATURE(feature) HEDLEY_HAS_FEATURE(feature)
+
+#if defined(HEDLEY_CLANG_HAS_EXTENSION)
+#  undef HEDLEY_CLANG_HAS_EXTENSION
+#endif
+#define HEDLEY_CLANG_HAS_EXTENSION(extension) HEDLEY_HAS_EXTENSION(extension)
+
+#if defined(HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE)
+#  undef HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE
+#endif
+#define HEDLEY_CLANG_HAS_DECLSPEC_ATTRIBUTE(attribute) HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute)
+
+#if defined(HEDLEY_CLANG_HAS_WARNING)
+#  undef HEDLEY_CLANG_HAS_WARNING
+#endif
+#define HEDLEY_CLANG_HAS_WARNING(warning) HEDLEY_HAS_WARNING(warning)
+
+#endif /* !defined(HEDLEY_VERSION) || (HEDLEY_VERSION < X) */
diff --git a/MCUME_pico2/picogb/palettes/peanut_gb.h b/MCUME_pico2/picogb/palettes/peanut_gb.h
new file mode 100755
index 0000000..223f914
--- /dev/null
+++ b/MCUME_pico2/picogb/palettes/peanut_gb.h
@@ -0,0 +1,4370 @@
+/**
+ * MIT License
+ *
+ * Copyright (c) 2018-2023 Mahyar Koshkouei
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Please note that at least three parts of source code within this project was
+ * taken from the SameBoy project at https://github.com/LIJI32/SameBoy/ which at
+ * the time of this writing is released under the MIT License. Occurrences of
+ * this code is marked as being taken from SameBoy with a comment.
+ * SameBoy, and code marked as being taken from SameBoy,
+ * is Copyright (c) 2015-2019 Lior Halphon.
+ */
+
+#ifndef PEANUT_GB_H
+#define PEANUT_GB_H
+
+
+
+#if defined(__has_include)
+# if __has_include("version.all")
+#  include "version.all"	/* Version information */
+# endif
+#else
+/* Stub __has_include for later. */
+# define __has_include(x) 0
+#endif
+
+#include <cstdlib>	/* Required for qsort and abort */
+#include <cstdint>	/* Required for int types */
+#include <cstring>	/* Required for memset */
+#include <ctime>	/* Required for tm struct */
+#include <pico/runtime.h>
+/**
+* If PEANUT_GB_IS_LITTLE_ENDIAN is positive, then Peanut-GB will be configured
+* for a little endian platform. If 0, then big endian.
+*/
+#if !defined(PEANUT_GB_IS_LITTLE_ENDIAN)
+/* If endian is not defined, then attempt to detect it. */
+# if defined(__BYTE_ORDER__)
+#  if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+/* Building for a big endian platform. */
+#   define PEANUT_GB_IS_LITTLE_ENDIAN 0
+#  else
+#   define PEANUT_GB_IS_LITTLE_ENDIAN 1
+#  endif /* __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ */
+# elif defined(_WIN32)
+/* We assume that Windows is always little endian by default. */
+#  define PEANUT_GB_IS_LITTLE_ENDIAN 1
+# elif !defined(PEANUT_GB_IS_LITTLE_ENDIAN)
+#  error "Could not detect target platform endian. Please define PEANUT_GB_IS_LITTLE_ENDIAN"
+# endif
+#endif /* !defined(PEANUT_GB_IS_LITTLE_ENDIAN) */
+
+#if PEANUT_GB_IS_LITTLE_ENDIAN == 0
+# error "Peanut-GB only supports little endian targets"
+/* This is because the logic has been written with assumption of little
+ * endian byte order. */
+#endif
+
+/** Definitions for compile-time setting of features. **/
+/**
+ * Sound support must be provided by an external library. When audio_read() and
+ * audio_write() functions are provided, define ENABLE_SOUND to a non-zero value
+ * before including peanut_gb.h in order for these functions to be used.
+ */
+#ifndef ENABLE_SOUND
+# define ENABLE_SOUND 0
+#endif
+
+/* Enable LCD drawing. On by default. May be turned off for testing purposes. */
+#ifndef ENABLE_LCD
+# define ENABLE_LCD 1
+#endif
+
+/* Enable 16 bit colour palette. If disabled, only four colour shades are set in
+ * pixel data. */
+#ifndef PEANUT_GB_12_COLOUR
+# define PEANUT_GB_12_COLOUR 1
+#endif
+
+/* Adds more code to improve LCD rendering accuracy. */
+#ifndef PEANUT_GB_HIGH_LCD_ACCURACY
+# define PEANUT_GB_HIGH_LCD_ACCURACY 0
+#endif
+
+/* Use intrinsic functions. This may produce smaller and faster code. */
+#ifndef PEANUT_GB_USE_INTRINSICS
+# define PEANUT_GB_USE_INTRINSICS 1
+#endif
+
+#ifndef PEANUT_FULL_GBC_SUPPORT
+# define PEANUT_FULL_GBC_SUPPORT 1
+#endif
+
+/* Only include function prototypes. At least one file must *not* have this
+ * defined. */
+// #define PEANUT_GB_HEADER_ONLY
+
+/** Internal source code. **/
+/* Interrupt masks */
+#define VBLANK_INTR	0x01
+#define LCDC_INTR	0x02
+#define TIMER_INTR	0x04
+#define SERIAL_INTR	0x08
+#define CONTROL_INTR	0x10
+#define ANY_INTR	0x1F
+
+/* Memory section sizes for DMG */
+#if PEANUT_FULL_GBC_SUPPORT
+#define WRAM_SIZE	0x8000
+#define VRAM_SIZE	0x4000
+#else
+#define WRAM_SIZE	0x2000
+#define VRAM_SIZE	0x2000
+#endif
+#define HRAM_IO_SIZE	0x0100
+#define OAM_SIZE	0x00A0
+
+/* Memory addresses */
+#define ROM_0_ADDR      0x0000
+#define ROM_N_ADDR      0x4000
+#define VRAM_ADDR       0x8000
+#define CART_RAM_ADDR   0xA000
+#define WRAM_0_ADDR     0xC000
+#define WRAM_1_ADDR     0xD000
+#define ECHO_ADDR       0xE000
+#define OAM_ADDR        0xFE00
+#define UNUSED_ADDR     0xFEA0
+#define IO_ADDR         0xFF00
+#define HRAM_ADDR       0xFF80
+#define INTR_EN_ADDR    0xFFFF
+
+/* Cart section sizes */
+#define ROM_BANK_SIZE   0x4000
+#define WRAM_BANK_SIZE  0x1000
+#define CRAM_BANK_SIZE  0x2000
+#define VRAM_BANK_SIZE  0x2000
+
+/* DIV Register is incremented at rate of 16384Hz.
+ * 4194304 / 16384 = 256 clock cycles for one increment. */
+#define DIV_CYCLES          256
+
+/* Serial clock locked to 8192Hz on DMG.
+ * 4194304 / (8192 / 8) = 4096 clock cycles for sending 1 byte. */
+#define SERIAL_CYCLES       4096
+#define SERIAL_CYCLES_1KB   (SERIAL_CYCLES/1ul)
+#define SERIAL_CYCLES_2KB   (SERIAL_CYCLES/2ul)
+#define SERIAL_CYCLES_32KB  (SERIAL_CYCLES/32ul)
+#define SERIAL_CYCLES_64KB  (SERIAL_CYCLES/64ul)
+
+/* Calculating VSYNC. */
+#define DMG_CLOCK_FREQ      4194304.0
+#define SCREEN_REFRESH_CYCLES 70224.0
+#define VERTICAL_SYNC       (DMG_CLOCK_FREQ/SCREEN_REFRESH_CYCLES)
+
+/* SERIAL SC register masks. */
+#define SERIAL_SC_TX_START  0x80
+#define SERIAL_SC_CLOCK_SRC 0x01
+
+/* STAT register masks */
+#define STAT_LYC_INTR       0x40
+#define STAT_MODE_2_INTR    0x20
+#define STAT_MODE_1_INTR    0x10
+#define STAT_MODE_0_INTR    0x08
+#define STAT_LYC_COINC      0x04
+#define STAT_MODE           0x03
+#define STAT_USER_BITS      0xF8
+
+/* LCDC control masks */
+#define LCDC_ENABLE         0x80
+#define LCDC_WINDOW_MAP     0x40
+#define LCDC_WINDOW_ENABLE  0x20
+#define LCDC_TILE_SELECT    0x10
+#define LCDC_BG_MAP         0x08
+#define LCDC_OBJ_SIZE       0x04
+#define LCDC_OBJ_ENABLE     0x02
+#define LCDC_BG_ENABLE      0x01
+
+/** LCD characteristics **/
+/* PPU cycles through modes every 456 cycles. */
+#define LCD_LINE_CYCLES     456
+/* Mode 0 starts on cycle 372. */
+#define LCD_MODE_0_CYCLES   372
+/* Mode 2 starts on cycle 204. */
+#define LCD_MODE_2_CYCLES   204
+/* Mode 3 starts on cycle 284. */
+#define LCD_MODE_3_CYCLES   284
+/* There are 154 scanlines. LY < 154. */
+#define LCD_VERT_LINES      154
+#define LCD_WIDTH           160
+#define LCD_HEIGHT          144
+
+/* VRAM Locations */
+#define VRAM_TILES_1        (0x8000 - VRAM_ADDR)
+#define VRAM_TILES_2        (0x8800 - VRAM_ADDR)
+#define VRAM_BMAP_1         (0x9800 - VRAM_ADDR)
+#define VRAM_BMAP_2         (0x9C00 - VRAM_ADDR)
+#define VRAM_TILES_3        (0x8000 - VRAM_ADDR + VRAM_BANK_SIZE)
+#define VRAM_TILES_4        (0x8800 - VRAM_ADDR + VRAM_BANK_SIZE)
+
+/* Interrupt jump addresses */
+#define VBLANK_INTR_ADDR    0x0040
+#define LCDC_INTR_ADDR      0x0048
+#define TIMER_INTR_ADDR     0x0050
+#define SERIAL_INTR_ADDR    0x0058
+#define CONTROL_INTR_ADDR   0x0060
+
+/* SPRITE controls */
+#define NUM_SPRITES         0x28
+#define MAX_SPRITES_LINE    0x0A
+#define OBJ_PRIORITY        0x80
+#define OBJ_FLIP_Y          0x40
+#define OBJ_FLIP_X          0x20
+#define OBJ_PALETTE         0x10
+#if PEANUT_FULL_GBC_SUPPORT
+#define OBJ_BANK            0x08
+#define OBJ_CGB_PALETTE     0x07
+#endif
+
+#define ROM_HEADER_CHECKSUM_LOC	0x014D
+
+/* Local macros. */
+#ifndef MIN
+# define MIN(a, b)          ((a) < (b) ? (a) : (b))
+#endif
+
+#define PEANUT_GB_ARRAYSIZE(array)    (sizeof(array)/sizeof(array[0]))
+
+#if !defined(__has_builtin)
+/* Stub __has_builtin if it isn't available. */
+# define __has_builtin(x) 0
+#endif
+
+/* The PGB_UNREACHABLE() macro tells the compiler that the code path will never
+ * be reached, allowing for further optimisation. */
+#if !defined(PGB_UNREACHABLE)
+# if __has_builtin(__builtin_unreachable)
+#  define PGB_UNREACHABLE() __builtin_unreachable()
+# elif defined(_MSC_VER) && _MSC_VER >= 1200
+#  /* __assume is not available before VC6. */
+#  define PGB_UNREACHABLE() __assume(0)
+# else
+#  define PGB_UNREACHABLE() abort()
+# endif
+#endif /* !defined(PGB_UNREACHABLE) */
+
+#if PEANUT_GB_USE_INTRINSICS
+/* If using MSVC, only enable intrinsics for x86 platforms*/
+# if defined(_MSC_VER) && __has_include("intrin.h") && \
+	(defined(_M_IX86_FP) || defined(_M_AMD64) || defined(_M_X64))
+/* Define intrinsic functions for MSVC. */
+#  include <intrin.h>
+#  define PGB_INTRIN_SBC(x,y,cin,res) _subborrow_u8(cin,x,y,&res)
+#  define PGB_INTRIN_ADC(x,y,cin,res) _addcarry_u8(cin,x,y,&res)
+# endif /* MSVC */
+
+/* Check for intrinsic functions in GCC and Clang. */
+# if __has_builtin(__builtin_sub_overflow)
+#  define PGB_INTRIN_SBC(x,y,cin,res) __builtin_sub_overflow(x,y+cin,&res)
+#  define PGB_INTRIN_ADC(x,y,cin,res) __builtin_add_overflow(x,y+cin,&res)
+# endif
+#endif /* PEANUT_GB_USE_INTRINSICS */
+
+#if defined(PGB_INTRIN_SBC)
+# define PGB_INSTR_SBC_R8(r,cin)						\
+	{									\
+		uint8_t temp;							\
+		gb->cpu_reg.f_bits.c = PGB_INTRIN_SBC(gb->cpu_reg.a,r,cin,temp);\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0;	\
+		gb->cpu_reg.f_bits.n = 1;					\
+		gb->cpu_reg.f_bits.z = (temp == 0x00);				\
+		gb->cpu_reg.a = temp;						\
+	}
+
+# define PGB_INSTR_CP_R8(r)							\
+	{									\
+		uint8_t temp;							\
+		gb->cpu_reg.f_bits.c = PGB_INTRIN_SBC(gb->cpu_reg.a,r,0,temp);	\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0;	\
+		gb->cpu_reg.f_bits.n = 1;					\
+		gb->cpu_reg.f_bits.z = (temp == 0x00);				\
+	}
+#else
+# define PGB_INSTR_SBC_R8(r,cin)						\
+	{									\
+		uint16_t temp = gb->cpu_reg.a - (r + cin);			\
+		gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0;			\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
+		gb->cpu_reg.f_bits.n = 1;					\
+		gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00);			\
+		gb->cpu_reg.a = (temp & 0xFF);					\
+	}
+
+# define PGB_INSTR_CP_R8(r)							\
+	{									\
+		uint16_t temp = gb->cpu_reg.a - r;				\
+		gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0;			\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
+		gb->cpu_reg.f_bits.n = 1;					\
+		gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00);			\
+	}
+#endif  /* PGB_INTRIN_SBC */
+
+#if defined(PGB_INTRIN_ADC)
+# define PGB_INSTR_ADC_R8(r,cin)						\
+	{									\
+		uint8_t temp;							\
+		gb->cpu_reg.f_bits.c = PGB_INTRIN_ADC(gb->cpu_reg.a,r,cin,temp);\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
+		gb->cpu_reg.f_bits.n = 0;					\
+		gb->cpu_reg.f_bits.z = (temp == 0x00);				\
+		gb->cpu_reg.a = temp;						\
+	}
+#else
+# define PGB_INSTR_ADC_R8(r,cin)						\
+	{									\
+		uint16_t temp = gb->cpu_reg.a + r + cin;			\
+		gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0;			\
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
+		gb->cpu_reg.f_bits.n = 0;					\
+		gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00);			\
+		gb->cpu_reg.a = (temp & 0xFF);					\
+	}
+#endif /* PGB_INTRIN_ADC */
+
+#define PGB_INSTR_DEC_R8(r)							\
+	r--;									\
+	gb->cpu_reg.f_bits.h = ((r & 0x0F) == 0x0F);				\
+	gb->cpu_reg.f_bits.n = 1;						\
+	gb->cpu_reg.f_bits.z = (r == 0x00);
+
+#define PGB_INSTR_XOR_R8(r)							\
+	gb->cpu_reg.a ^= r;							\
+	gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);				\
+	gb->cpu_reg.f_bits.n = 0;						\
+	gb->cpu_reg.f_bits.h = 0;						\
+	gb->cpu_reg.f_bits.c = 0;
+
+#define PGB_INSTR_OR_R8(r)							\
+	gb->cpu_reg.a |= r;							\
+	gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);				\
+	gb->cpu_reg.f_bits.n = 0;						\
+	gb->cpu_reg.f_bits.h = 0;						\
+	gb->cpu_reg.f_bits.c = 0;
+
+#define PGB_INSTR_AND_R8(r)							\
+	gb->cpu_reg.a &= r;							\
+	gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);				\
+	gb->cpu_reg.f_bits.n = 0;						\
+	gb->cpu_reg.f_bits.h = 1;						\
+	gb->cpu_reg.f_bits.c = 0;
+
+#if PEANUT_GB_IS_LITTLE_ENDIAN
+# define PEANUT_GB_GET_LSB16(x) (x & 0xFF)
+# define PEANUT_GB_GET_MSB16(x) (x >> 8)
+# define PEANUT_GB_GET_MSN16(x) (x >> 12)
+# define PEANUT_GB_U8_TO_U16(h,l) ((l) | ((h) << 8))
+#else
+# define PEANUT_GB_GET_LSB16(x) (x >> 8)
+# define PEANUT_GB_GET_MSB16(x) (x & 0xFF)
+# define PEANUT_GB_GET_MSN16(x) ((x & 0xF0) >> 4)
+# define PEANUT_GB_U8_TO_U16(h,l) ((h) | ((l) << 8))
+#endif
+
+static inline uint32_t RGB555_TO_RGB888(uint16_t rgb555) {
+// Extract individual color components from rgb555
+	const uint8_t R = (rgb555 >> 10 & 0b11111) * 8;
+	const uint8_t G = (rgb555 >> 5 & 0b11111) * 8;
+	const uint8_t B = (rgb555 & 0b11111) * 8;
+
+    return RGB888(R + R / 32,G + G / 32, B + B / 32);
+}
+
+struct cpu_registers_s
+{
+/* Change register order if big endian.
+ * Macro receives registers in little endian order. */
+#if PEANUT_GB_IS_LITTLE_ENDIAN
+# define PEANUT_GB_LE_REG(x,y) x,y
+#else
+# define PEANUT_GB_LE_REG(x,y) y,x
+#endif
+	/* Define specific bits of Flag register. */
+	struct
+	{
+		uint8_t c : 1; /* Carry flag. */
+		uint8_t h : 1; /* Half carry flag. */
+		uint8_t n : 1; /* Add/sub flag. */
+		uint8_t z : 1; /* Zero flag. */
+	} f_bits;
+	uint8_t a;
+
+	union
+	{
+		struct
+		{
+			uint8_t PEANUT_GB_LE_REG(c,b);
+		} bytes;
+		uint16_t reg;
+	} bc;
+
+	union
+	{
+		struct
+		{
+			uint8_t PEANUT_GB_LE_REG(e,d);
+		} bytes;
+		uint16_t reg;
+	} de;
+
+	union
+	{
+		struct
+		{
+			uint8_t PEANUT_GB_LE_REG(l,h);
+		} bytes;
+		uint16_t reg;
+	} hl;
+
+	/* Stack pointer */
+	union
+	{
+		struct
+		{
+			uint8_t PEANUT_GB_LE_REG(p, s);
+		} bytes;
+		uint16_t reg;
+	} sp;
+
+	/* Program counter */
+	union
+	{
+		struct
+		{
+			uint8_t PEANUT_GB_LE_REG(c, p);
+		} bytes;
+		uint16_t reg;
+	} pc;
+#undef PEANUT_GB_LE_REG
+};
+
+struct count_s
+{
+	uint_fast16_t lcd_count;	/* LCD Timing */
+	uint_fast16_t div_count;	/* Divider Register Counter */
+	uint_fast16_t tima_count;	/* Timer Counter */
+	uint_fast16_t serial_count;	/* Serial Counter */
+};
+
+#if ENABLE_LCD
+	/* Bit mask for the shade of pixel to display */
+	#define LCD_COLOUR	0x03
+
+# if PEANUT_GB_12_COLOUR
+	/**
+	* Bit mask for whether a pixel is OBJ0, OBJ1, or BG. Each may have a different
+	* palette when playing a DMG game on CGB.
+	*/
+	#define LCD_PALETTE_OBJ	0x10
+	#define LCD_PALETTE_BG	0x20
+	/**
+	* Bit mask for the two bits listed above.
+	* LCD_PALETTE_ALL == 0b00 --> OBJ0
+	* LCD_PALETTE_ALL == 0b01 --> OBJ1
+	* LCD_PALETTE_ALL == 0b10 --> BG
+	* LCD_PALETTE_ALL == 0b11 --> NOT POSSIBLE
+	*/
+	#define LCD_PALETTE_ALL 0x30
+# endif
+#endif
+
+/**
+ * Errors that may occur during emulation.
+ */
+enum gb_error_e
+{
+	GB_UNKNOWN_ERROR = 0,
+	GB_INVALID_OPCODE,
+	GB_INVALID_READ,
+	GB_INVALID_WRITE,
+	GB_HALT_FOREVER,
+
+	GB_INVALID_MAX
+};
+
+/**
+ * Errors that may occur during library initialisation.
+ */
+enum gb_init_error_e
+{
+	GB_INIT_NO_ERROR = 0,
+	GB_INIT_CARTRIDGE_UNSUPPORTED,
+	GB_INIT_INVALID_CHECKSUM
+};
+
+/**
+ * Return codes for serial receive function, mainly for clarity.
+ */
+enum gb_serial_rx_ret_e
+{
+	GB_SERIAL_RX_SUCCESS = 0,
+	GB_SERIAL_RX_NO_CONNECTION = 1
+};
+
+/**
+ * Emulator context.
+ *
+ * Only values within the `direct` struct may be modified directly by the
+ * front-end implementation. Other variables must not be modified.
+ */
+struct gb_s
+{
+	/**
+	 * Return byte from ROM at given address.
+	 *
+	 * \param gb_s	emulator context
+	 * \param addr	address
+	 * \return		byte at address in ROM
+	 */
+	uint8_t (*gb_rom_read)(struct gb_s*, const uint_fast32_t addr);
+
+	/**
+	 * Return byte from cart RAM at given address.
+	 *
+	 * \param gb_s	emulator context
+	 * \param addr	address
+	 * \return		byte at address in RAM
+	 */
+	uint8_t (*gb_cart_ram_read)(struct gb_s*, const uint_fast32_t addr);
+
+	/**
+	 * Write byte to cart RAM at given address.
+	 *
+	 * \param gb_s	emulator context
+	 * \param addr	address
+	 * \param val	value to write to address in RAM
+	 */
+	void (*gb_cart_ram_write)(struct gb_s*, const uint_fast32_t addr,
+				  const uint8_t val);
+
+	/**
+	 * Notify front-end of error.
+	 *
+	 * \param gb_s		emulator context
+	 * \param gb_error_e	error code
+	 * \param addr		address of where error occurred
+	 */
+	void (*gb_error)(struct gb_s*, const enum gb_error_e, const uint16_t addr);
+
+	/* Transmit one byte and return the received byte. */
+	void (*gb_serial_tx)(struct gb_s*, const uint8_t tx);
+	enum gb_serial_rx_ret_e (*gb_serial_rx)(struct gb_s*, uint8_t* rx);
+
+	/* Read byte from boot ROM at given address. */
+	uint8_t (*gb_bootrom_read)(struct gb_s*, const uint_fast16_t addr);
+
+	struct
+	{
+		uint8_t gb_halt		: 1;
+		uint8_t gb_ime		: 1;
+		uint8_t gb_frame	: 1; /* New frame drawn. */
+		uint8_t lcd_blank	: 1;
+	};
+
+	/* Cartridge information:
+	 * Memory Bank Controller (MBC) type. */
+	int8_t mbc;
+	/* Whether the MBC has internal RAM. */
+	uint8_t cart_ram;
+	/* Number of ROM banks in cartridge. */
+	uint16_t num_rom_banks_mask;
+	/* Number of RAM banks in cartridge. Ignore for MBC2. */
+	uint8_t num_ram_banks;
+
+	uint16_t selected_rom_bank;
+	/* WRAM and VRAM bank selection not available. */
+	uint8_t cart_ram_bank;
+	uint8_t enable_cart_ram;
+	/* Cartridge ROM/RAM mode select. */
+	uint8_t cart_mode_select;
+	union
+	{
+		struct
+		{
+			uint8_t sec;
+			uint8_t min;
+			uint8_t hour;
+			uint8_t yday;
+			uint8_t high;
+		} rtc_bits;
+		uint8_t cart_rtc[5];
+	};
+
+	struct cpu_registers_s cpu_reg;
+	//struct gb_registers_s gb_reg;
+	struct count_s counter;
+
+	/* TODO: Allow implementation to allocate WRAM, VRAM and Frame Buffer. */
+	uint8_t wram[WRAM_SIZE];
+	uint8_t vram[VRAM_SIZE];
+	uint8_t oam[OAM_SIZE];
+	uint8_t hram_io[HRAM_IO_SIZE];
+
+	struct
+	{
+		/**
+		 * Draw line on screen.
+		 *
+		 * \param gb_s		emulator context
+		 * \param pixels	The 160 pixels to draw.
+		 * 			Bits 1-0 are the colour to draw.
+		 * 			Bits 5-4 are the palette, where:
+		 * 				OBJ0 = 0b00,
+		 * 				OBJ1 = 0b01,
+		 * 				BG = 0b10
+		 * 			Other bits are undefined.
+		 * 			Bits 5-4 are only required by front-ends
+		 * 			which want to use a different colour for
+		 * 			different object palettes. This is what
+		 * 			the Game Boy Color (CGB) does to DMG
+		 * 			games.
+		 * \param line		Line to draw pixels on. This is
+		 * guaranteed to be between 0-144 inclusive.
+		 */
+		void (*lcd_draw_line)(struct gb_s *gb,
+				const uint8_t *pixels,
+				const uint_fast8_t line);
+
+		/* Palettes */
+		uint8_t bg_palette[4];
+		uint8_t sp_palette[8];
+
+		uint8_t window_clear;
+		uint8_t WY;
+
+		/* Only support 30fps frame skip. */
+		uint8_t frame_skip_count : 1;
+		uint8_t interlace_count : 1;
+	} display;
+
+#if PEANUT_FULL_GBC_SUPPORT
+	/* Game Boy Color Mode*/
+	struct {
+		uint8_t cgbMode;
+		uint8_t doubleSpeed;
+		uint8_t doubleSpeedPrep;
+		uint8_t wramBank;
+		uint16_t wramBankOffset;
+		uint8_t vramBank;
+		uint16_t vramBankOffset;
+		uint32_t fixPalette[0x40];  //BG then OAM palettes fixed for the screen
+		uint8_t OAMPalette[0x40];
+		uint8_t BGPalette[0x40];
+		uint8_t OAMPaletteID;
+		uint8_t BGPaletteID;
+		uint8_t OAMPaletteInc;
+		uint8_t BGPaletteInc;
+		uint8_t dmaActive;
+		uint8_t dmaMode;
+		uint8_t dmaSize;
+		uint16_t dmaSource;
+		uint16_t dmaDest;
+	} cgb;
+#endif
+
+	/**
+	 * Variables that may be modified directly by the front-end.
+	 * This method seems to be easier and possibly less overhead than
+	 * calling a function to modify these variables each time.
+	 *
+	 * None of this is thread-safe.
+	 */
+	struct
+	{
+		/* Set to enable interlacing. Interlacing will start immediately
+		 * (at the next line drawing).
+		 */
+		uint8_t interlace : 1;
+		uint8_t frame_skip : 1;
+
+		union
+		{
+			struct
+			{
+				uint8_t a	: 1;
+				uint8_t b	: 1;
+				uint8_t select	: 1;
+				uint8_t start	: 1;
+				uint8_t right	: 1;
+				uint8_t left	: 1;
+				uint8_t up	: 1;
+				uint8_t down	: 1;
+			} joypad_bits;
+			uint8_t joypad;
+		};
+
+		/* Implementation defined data. Set to NULL if not required. */
+		void *priv;
+	} direct;
+};
+
+#ifndef PEANUT_GB_HEADER_ONLY
+
+#define IO_JOYP	0x00
+#define IO_SB	0x01
+#define IO_SC	0x02
+#define IO_DIV	0x04
+#define IO_TIMA	0x05
+#define IO_TMA	0x06
+#define IO_TAC	0x07
+#define IO_IF	0x0F
+#define IO_BOOT	0x50
+#define IO_LCDC	0x40
+#define IO_STAT	0x41
+#define IO_SCY	0x42
+#define IO_SCX	0x43
+#define IO_LY	0x44
+#define IO_LYC	0x45
+#define	IO_DMA	0x46
+#define	IO_BGP	0x47
+#define	IO_OBP0	0x48
+#define IO_OBP1	0x49
+#define IO_WY	0x4A
+#define IO_WX	0x4B
+#define IO_BANK	0x50
+#define IO_IE	0xFF
+
+#define IO_TAC_RATE_MASK	0x3
+#define IO_TAC_ENABLE_MASK	0x4
+
+/* LCD Mode defines. */
+#define IO_STAT_MODE_HBLANK		0
+#define IO_STAT_MODE_VBLANK		1
+#define IO_STAT_MODE_SEARCH_OAM		2
+#define IO_STAT_MODE_SEARCH_TRANSFER	3
+#define IO_STAT_MODE_VBLANK_OR_TRANSFER_MASK 0x1
+
+/**
+ * Internal function used to read bytes.
+ * addr is host platform endian.
+ */
+uint8_t __gb_read(struct gb_s *gb, uint16_t addr)
+{
+	switch(PEANUT_GB_GET_MSN16(addr))
+	{
+	case 0x0:
+		/* IO_BANK is only set to 1 if gb->gb_bootrom_read was not NULL
+		 * on reset. */
+		if(gb->hram_io[IO_BANK] == 0 && addr < 0x0100)
+		{
+			return gb->gb_bootrom_read(gb, addr);
+		}
+
+		/* Fallthrough */
+	case 0x1:
+	case 0x2:
+	case 0x3:
+		return gb->gb_rom_read(gb, addr);
+
+	case 0x4:
+	case 0x5:
+	case 0x6:
+	case 0x7:
+		if(gb->mbc == 1 && gb->cart_mode_select)
+			return gb->gb_rom_read(gb,
+					       addr + ((gb->selected_rom_bank & 0x1F) - 1) * ROM_BANK_SIZE);
+		else
+			return gb->gb_rom_read(gb, addr + (gb->selected_rom_bank - 1) * ROM_BANK_SIZE);
+
+	case 0x8:
+	case 0x9:
+#if PEANUT_FULL_GBC_SUPPORT
+		return gb->vram[addr - gb->cgb.vramBankOffset];
+#else
+		return gb->vram[addr - VRAM_ADDR];
+#endif
+	case 0xA:
+	case 0xB:
+		if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
+		{
+			return gb->cart_rtc[gb->cart_ram_bank - 0x08];
+		}
+		else if(gb->cart_ram && gb->enable_cart_ram)
+		{
+			if(gb->mbc == 2)
+			{
+				/* Only 9 bits are available in address. */
+				addr &= 0x1FF;
+				return gb->gb_cart_ram_read(gb, addr);
+			}
+			else if((gb->cart_mode_select || gb->mbc != 1) &&
+					gb->cart_ram_bank < gb->num_ram_banks)
+			{
+				return gb->gb_cart_ram_read(gb, addr - CART_RAM_ADDR +
+							    (gb->cart_ram_bank * CRAM_BANK_SIZE));
+			}
+			else
+				return gb->gb_cart_ram_read(gb, addr - CART_RAM_ADDR);
+		}
+
+		return 0xFF;
+
+	case 0xC:
+	case 0xD:
+#if PEANUT_FULL_GBC_SUPPORT
+	if(gb->cgb.cgbMode && addr >= WRAM_1_ADDR)
+		return gb->wram[addr - gb->cgb.wramBankOffset];
+#endif
+		return gb->wram[addr - WRAM_0_ADDR];
+
+	case 0xE:
+		return gb->wram[addr - ECHO_ADDR];
+
+	case 0xF:
+		if(addr < OAM_ADDR)
+#if PEANUT_FULL_GBC_SUPPORT
+			return gb->wram[(addr - 0x2000) - gb->cgb.wramBankOffset];
+#else
+			return gb->wram[addr - ECHO_ADDR];
+#endif
+
+		if(addr < UNUSED_ADDR)
+			return gb->oam[addr - OAM_ADDR];
+
+		/* Unusable memory area. Reading from this area returns 0xFF.*/
+		if(addr < IO_ADDR)
+			return 0xFF;
+
+		/* APU registers. */
+		if((addr >= 0xFF10) && (addr <= 0xFF3F))
+		{
+#if ENABLE_SOUND
+			return audio_read(addr);
+#else
+			static const uint8_t ortab[] = {
+				0x80, 0x3f, 0x00, 0xff, 0xbf,
+				0xff, 0x3f, 0x00, 0xff, 0xbf,
+				0x7f, 0xff, 0x9f, 0xff, 0xbf,
+				0xff, 0xff, 0x00, 0x00, 0xbf,
+				0x00, 0x00, 0x70,
+				0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+			};
+			return gb->hram_io[addr - IO_ADDR] | ortab[addr - IO_ADDR];
+#endif
+		}
+
+#if PEANUT_FULL_GBC_SUPPORT
+		/* IO and Interrupts. */
+		switch (addr & 0xFF)
+		{
+		/* Speed Switch*/
+		case 0x4D:
+			return (gb->cgb.doubleSpeed << 7) + gb->cgb.doubleSpeedPrep;
+		/* CGB VRAM Bank*/
+		case 0x4F:
+			return gb->cgb.vramBank | 0xFE;
+		/* CGB DMA*/
+		case 0x51:
+			return (gb->cgb.dmaSource >> 8);
+		case 0x52:
+			return (gb->cgb.dmaSource & 0xF0);
+		case 0x53:
+			return (gb->cgb.dmaDest >> 8);
+		case 0x54:
+			return (gb->cgb.dmaDest & 0xF0);
+		case 0x55:
+			return (gb->cgb.dmaActive << 7) | (gb->cgb.dmaSize - 1);
+		/* IR Register*/
+		case 0x56:
+			return gb->hram_io[0x56];
+		/* CGB BG Palette Index*/
+		case 0x68:
+			return (gb->cgb.BGPaletteID & 0x3F) + (gb->cgb.BGPaletteInc << 7);
+		/* CGB BG Palette*/
+		case 0x69:
+			return gb->cgb.BGPalette[(gb->cgb.BGPaletteID & 0x3F)];
+		/* CGB OAM Palette Index*/
+		case 0x6A:
+			return (gb->cgb.OAMPaletteID & 0x3F) + (gb->cgb.OAMPaletteInc << 7);
+		/* CGB OAM Palette*/
+		case 0x6B:
+			return gb->cgb.OAMPalette[(gb->cgb.OAMPaletteID & 0x3F)];
+		/* CGB WRAM Bank*/
+		case 0x70:
+			return gb->cgb.wramBank;
+		default:
+#endif
+			/* HRAM */
+			if(addr >= IO_ADDR)
+				return gb->hram_io[addr - IO_ADDR];
+#if PEANUT_FULL_GBC_SUPPORT
+		}
+#endif
+	}
+
+
+	/* Return address that caused read error. */
+	(gb->gb_error)(gb, GB_INVALID_READ, addr);
+	PGB_UNREACHABLE();
+}
+
+/**
+ * Internal function used to write bytes.
+ */
+void __gb_write(struct gb_s *gb, uint_fast16_t addr, uint8_t val)
+{
+	switch(PEANUT_GB_GET_MSN16(addr))
+	{
+	case 0x0:
+	case 0x1:
+		/* Set RAM enable bit. MBC2 is handled in fall-through. */
+		if(gb->mbc > 0 && gb->mbc != 2 && gb->cart_ram)
+		{
+			gb->enable_cart_ram = ((val & 0x0F) == 0x0A);
+			return;
+		}
+
+	/* Intentional fall through. */
+	case 0x2:
+		if(gb->mbc == 5)
+		{
+			gb->selected_rom_bank = (gb->selected_rom_bank & 0x100) | val;
+			gb->selected_rom_bank =
+				gb->selected_rom_bank & gb->num_rom_banks_mask;
+			return;
+		}
+
+	/* Intentional fall through. */
+	case 0x3:
+		if(gb->mbc == 1)
+		{
+			//selected_rom_bank = val & 0x7;
+			gb->selected_rom_bank = (val & 0x1F) | (gb->selected_rom_bank & 0x60);
+
+			if((gb->selected_rom_bank & 0x1F) == 0x00)
+				gb->selected_rom_bank++;
+		}
+		else if(gb->mbc == 2)
+		{
+			/* If bit 8 is 1, then set ROM bank number. */
+			if(addr & 0x100)
+			{
+				gb->selected_rom_bank = val & 0x0F;
+				/* Setting ROM bank to 0, sets it to 1. */
+				if(!gb->selected_rom_bank)
+					gb->selected_rom_bank++;
+			}
+			/* Otherwise set whether RAM is enabled or not. */
+			else
+			{
+				gb->enable_cart_ram = ((val & 0x0F) == 0x0A);
+				return;
+			}
+		}
+		else if(gb->mbc == 3)
+		{
+			gb->selected_rom_bank = val & 0x7F;
+
+			if(!gb->selected_rom_bank)
+				gb->selected_rom_bank++;
+		}
+		else if(gb->mbc == 5)
+			gb->selected_rom_bank = (val & 0x01) << 8 | (gb->selected_rom_bank & 0xFF);
+
+		gb->selected_rom_bank = gb->selected_rom_bank & gb->num_rom_banks_mask;
+		return;
+
+	case 0x4:
+	case 0x5:
+		if(gb->mbc == 1)
+		{
+			gb->cart_ram_bank = (val & 3);
+			gb->selected_rom_bank = ((val & 3) << 5) | (gb->selected_rom_bank & 0x1F);
+			gb->selected_rom_bank = gb->selected_rom_bank & gb->num_rom_banks_mask;
+		}
+		else if(gb->mbc == 3)
+			gb->cart_ram_bank = val;
+		else if(gb->mbc == 5)
+			gb->cart_ram_bank = (val & 0x0F);
+
+		return;
+
+	case 0x6:
+	case 0x7:
+		gb->cart_mode_select = (val & 1);
+		return;
+
+	case 0x8:
+	case 0x9:
+#if PEANUT_FULL_GBC_SUPPORT
+		gb->vram[addr - gb->cgb.vramBankOffset] = val;
+#else
+		gb->vram[addr - VRAM_ADDR] = val;
+#endif
+		return;
+
+	case 0xA:
+	case 0xB:
+		if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
+		{
+			gb->cart_rtc[gb->cart_ram_bank - 0x08] = val;
+		}
+		/* Do not write to RAM if unavailable or disabled. */
+		else if(gb->cart_ram && gb->enable_cart_ram)
+		{
+			if(gb->mbc == 2)
+			{
+				/* Only 9 bits are available in address. */
+				addr &= 0x1FF;
+				/* Data is only 4 bits wide in MBC2 RAM. */
+				val &= 0x0F;
+				gb->gb_cart_ram_write(gb, addr, val);
+			}
+			else if(gb->cart_mode_select &&
+					gb->cart_ram_bank < gb->num_ram_banks)
+			{
+				gb->gb_cart_ram_write(gb,
+						      addr - CART_RAM_ADDR + (gb->cart_ram_bank * CRAM_BANK_SIZE), val);
+			}
+			else if(gb->num_ram_banks)
+				gb->gb_cart_ram_write(gb, addr - CART_RAM_ADDR, val);
+		}
+
+		return;
+
+	case 0xC:
+		gb->wram[addr - WRAM_0_ADDR] = val;
+		return;
+
+	case 0xD:
+#if PEANUT_FULL_GBC_SUPPORT
+		gb->wram[addr - gb->cgb.wramBankOffset] = val;
+#else
+		gb->wram[addr - WRAM_1_ADDR + WRAM_BANK_SIZE] = val;
+#endif
+		return;
+
+	case 0xE:
+		gb->wram[addr - ECHO_ADDR] = val;
+		return;
+
+	case 0xF:
+		if(addr < OAM_ADDR)
+		{
+#if PEANUT_FULL_GBC_SUPPORT
+			gb->wram[(addr - 0x2000) - gb->cgb.wramBankOffset] = val;
+#else
+			gb->wram[addr - ECHO_ADDR] = val;
+#endif
+			return;
+		}
+
+		if(addr < UNUSED_ADDR)
+		{
+			gb->oam[addr - OAM_ADDR] = val;
+			return;
+		}
+
+		/* Unusable memory area. */
+		if(addr < IO_ADDR)
+			return;
+
+		if(HRAM_ADDR <= addr && addr < INTR_EN_ADDR)
+		{
+			gb->hram_io[addr - IO_ADDR] = val;
+			return;
+		}
+
+		if((addr >= 0xFF10) && (addr <= 0xFF3F))
+		{
+#if ENABLE_SOUND
+			audio_write(addr, val);
+#else
+			gb->hram_io[addr - IO_ADDR] = val;
+#endif
+			return;
+		}
+#if PEANUT_FULL_GBC_SUPPORT
+		uint16_t fixPaletteTemp;
+#endif
+		/* IO and Interrupts. */
+		switch(PEANUT_GB_GET_LSB16(addr))
+		{
+		/* Joypad */
+		case 0x00:
+			/* Only bits 5 and 4 are R/W.
+			 * The lower bits are overwritten later, and the two most
+			 * significant bits are unused. */
+			gb->hram_io[IO_JOYP] = val;
+
+			/* Direction keys selected */
+			if((gb->hram_io[IO_JOYP] & 0x10) == 0)
+				gb->hram_io[IO_JOYP] |= (gb->direct.joypad >> 4);
+			/* Button keys selected */
+			else
+				gb->hram_io[IO_JOYP] |= (gb->direct.joypad & 0x0F);
+
+			return;
+
+		/* Serial */
+		case 0x01:
+			gb->hram_io[IO_SB] = val;
+			return;
+
+		case 0x02:
+			gb->hram_io[IO_SC] = val;
+			return;
+
+		/* Timer Registers */
+		case 0x04:
+			gb->hram_io[IO_DIV] = 0x00;
+			return;
+
+		case 0x05:
+			gb->hram_io[IO_TIMA] = val;
+			return;
+
+		case 0x06:
+			gb->hram_io[IO_TMA] = val;
+			return;
+
+		case 0x07:
+			gb->hram_io[IO_TAC] = val;
+			return;
+
+		/* Interrupt Flag Register */
+		case 0x0F:
+			gb->hram_io[IO_IF] = (val | 0xE0);
+			return;
+
+		/* LCD Registers */
+		case 0x40:
+		{
+			uint8_t lcd_enabled;
+
+			/* Check if LCD is already enabled. */
+			lcd_enabled = (gb->hram_io[IO_LCDC] & LCDC_ENABLE);
+
+			gb->hram_io[IO_LCDC] = val;
+
+			/* Check if LCD is going to be switched on. */
+			if (!lcd_enabled && (val & LCDC_ENABLE))
+			{
+				gb->lcd_blank = 1;
+			}
+			/* Check if LCD is being switched off. */
+			else if (lcd_enabled && !(val & LCDC_ENABLE))
+			{
+				/* Peanut-GB will happily turn off LCD outside
+				 * of VBLANK even though this damages real
+				 * hardware. */
+
+				/* Set LCD to Mode 0. */
+				gb->hram_io[IO_STAT] =
+					(gb->hram_io[IO_STAT] & ~STAT_MODE) |
+					IO_STAT_MODE_HBLANK;
+				/* LY fixed to 0 when LCD turned off. */
+				gb->hram_io[IO_LY] = 0;
+				/* Reset LCD timer. */
+				gb->counter.lcd_count = 0;
+			}
+			return;
+		}
+
+		case 0x41:
+			gb->hram_io[IO_STAT] = (val & STAT_USER_BITS) | (gb->hram_io[IO_STAT] & STAT_MODE);
+			return;
+
+		case 0x42:
+			gb->hram_io[IO_SCY] = val;
+			return;
+
+		case 0x43:
+			gb->hram_io[IO_SCX] = val;
+			return;
+
+		/* LY (0xFF44) is read only. */
+		case 0x45:
+			gb->hram_io[IO_LYC] = val;
+			return;
+
+		/* DMA Register */
+		case 0x46:
+		{
+			uint16_t dma_addr;
+			uint16_t i;
+#if PEANUT_FULL_GBC_SUPPORT
+			dma_addr = (uint_fast16_t)(val % 0xF1) << 8;
+			gb->hram_io[IO_DMA] = (val % 0xF1);
+#else
+			dma_addr = (uint_fast16_t)val << 8;
+			gb->hram_io[IO_DMA] = val;
+#endif
+			for(i = 0; i < OAM_SIZE; i++)
+			{
+				gb->oam[i] = __gb_read(gb, dma_addr + i);
+			}
+
+			return;
+		}
+
+		/* DMG Palette Registers */
+		case 0x47:
+			gb->hram_io[IO_BGP] = val;
+			gb->display.bg_palette[0] = (gb->hram_io[IO_BGP] & 0x03);
+			gb->display.bg_palette[1] = (gb->hram_io[IO_BGP] >> 2) & 0x03;
+			gb->display.bg_palette[2] = (gb->hram_io[IO_BGP] >> 4) & 0x03;
+			gb->display.bg_palette[3] = (gb->hram_io[IO_BGP] >> 6) & 0x03;
+			return;
+
+		case 0x48:
+			gb->hram_io[IO_OBP0] = val;
+			gb->display.sp_palette[0] = (gb->hram_io[IO_OBP0] & 0x03);
+			gb->display.sp_palette[1] = (gb->hram_io[IO_OBP0] >> 2) & 0x03;
+			gb->display.sp_palette[2] = (gb->hram_io[IO_OBP0] >> 4) & 0x03;
+			gb->display.sp_palette[3] = (gb->hram_io[IO_OBP0] >> 6) & 0x03;
+			return;
+
+		case 0x49:
+			gb->hram_io[IO_OBP1] = val;
+			gb->display.sp_palette[4] = (gb->hram_io[IO_OBP1] & 0x03);
+			gb->display.sp_palette[5] = (gb->hram_io[IO_OBP1] >> 2) & 0x03;
+			gb->display.sp_palette[6] = (gb->hram_io[IO_OBP1] >> 4) & 0x03;
+			gb->display.sp_palette[7] = (gb->hram_io[IO_OBP1] >> 6) & 0x03;
+			return;
+
+		/* Window Position Registers */
+		case 0x4A:
+			gb->hram_io[IO_WY] = val;
+			return;
+
+		case 0x4B:
+			gb->hram_io[IO_WX] = val;
+			return;
+
+#if PEANUT_FULL_GBC_SUPPORT
+		/* Prepare Speed Switch*/
+		case 0x4D:
+			gb->cgb.doubleSpeedPrep = val & 1;
+			return;
+
+		/* CGB VRAM Bank*/
+		case 0x4F:
+			gb->cgb.vramBank = val & 0x01;
+			if(gb->cgb.cgbMode) gb->cgb.vramBankOffset = VRAM_ADDR - (gb->cgb.vramBank << 13);
+			return;
+#endif
+		/* Turn off boot ROM */
+		case 0x50:
+			gb->hram_io[IO_BANK] = val;
+			return;
+#if PEANUT_FULL_GBC_SUPPORT
+		/* DMA Register */
+		case 0x51:
+			gb->cgb.dmaSource = (gb->cgb.dmaSource & 0xFF) + (val << 8);
+			return;
+		case 0x52:
+			gb->cgb.dmaSource = (gb->cgb.dmaSource & 0xFF00) + val;
+			return;
+		case 0x53:
+			gb->cgb.dmaDest = (gb->cgb.dmaDest & 0xFF) + (val << 8);
+			return;
+		case 0x54:
+			gb->cgb.dmaDest = (gb->cgb.dmaDest & 0xFF00) + val;
+			return;
+
+		/* DMA Register*/
+		case 0x55:
+			gb->cgb.dmaSize = (val & 0x7F) + 1;
+			gb->cgb.dmaMode = val >> 7;
+			//DMA GBC
+			if(gb->cgb.dmaActive)
+			{  // Only transfer if dma is not active (=1) otherwise treat it as a termination
+				if(gb->cgb.cgbMode && (!gb->cgb.dmaMode))
+				{
+					for (int i = 0; i < (gb->cgb.dmaSize << 4); i++)
+					{
+						__gb_write(gb, ((gb->cgb.dmaDest & 0x1FF0) | 0x8000) + i, __gb_read(gb, (gb->cgb.dmaSource & 0xFFF0) + i));
+					}
+					gb->cgb.dmaSource += (gb->cgb.dmaSize << 4);
+					gb->cgb.dmaDest += (gb->cgb.dmaSize << 4);
+					gb->cgb.dmaSize = 0;
+				}
+			}
+			gb->cgb.dmaActive = gb->cgb.dmaMode ^ 1;  // set active if it's an HBlank DMA
+			return;
+
+		/* IR Register*/
+		case 0x56:
+			gb->hram_io[0x56] = val;
+			return;
+
+		/* CGB BG Palette Index*/
+		case 0x68:
+			gb->cgb.BGPaletteID = val & 0x3F;
+			gb->cgb.BGPaletteInc = val >> 7;
+			return;
+
+		/* CGB BG Palette*/
+		case 0x69:
+			gb->cgb.BGPalette[(gb->cgb.BGPaletteID & 0x3F)] = val;
+			fixPaletteTemp = (gb->cgb.BGPalette[(gb->cgb.BGPaletteID & 0x3E) + 1] << 8) + (gb->cgb.BGPalette[(gb->cgb.BGPaletteID & 0x3E)]);
+			gb->cgb.fixPalette[((gb->cgb.BGPaletteID & 0x3E) >> 1)] = RGB555_TO_RGB888(((fixPaletteTemp & 0x7C00) >> 10) | (fixPaletteTemp & 0x03E0) | ((fixPaletteTemp & 0x001F) << 10));  // swap Red and Blue
+			//graphics_set_palette((gb->cgb.BGPaletteID & 0x3E) >> 1,gb->cgb.fixPalette[((gb->cgb.BGPaletteID & 0x3E) >> 1)]);
+			emu_SetPaletteEntry(gb->cgb.fixPalette[((gb->cgb.BGPaletteID & 0x3E) >> 1)]>>16, (gb->cgb.fixPalette[((gb->cgb.BGPaletteID & 0x3E) >> 1)]>>8) & 0xff, gb->cgb.fixPalette[((gb->cgb.BGPaletteID & 0x3E) >> 1)] & 0xff, (gb->cgb.BGPaletteID & 0x3E) >> 1);
+			if(gb->cgb.BGPaletteInc) gb->cgb.BGPaletteID = (++gb->cgb.BGPaletteID) & 0x3F;
+			return;
+
+		/* CGB OAM Palette Index*/
+		case 0x6A:
+			gb->cgb.OAMPaletteID = val & 0x3F;
+			gb->cgb.OAMPaletteInc = val >> 7;
+			return;
+
+		/* CGB OAM Palette*/
+		case 0x6B:
+			gb->cgb.OAMPalette[(gb->cgb.OAMPaletteID & 0x3F)] = val;
+			fixPaletteTemp = (gb->cgb.OAMPalette[(gb->cgb.OAMPaletteID & 0x3E) + 1] << 8) + (gb->cgb.OAMPalette[(gb->cgb.OAMPaletteID & 0x3E)]);
+			gb->cgb.fixPalette[0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1)] = RGB555_TO_RGB888(((fixPaletteTemp & 0x7C00) >> 10) | (fixPaletteTemp & 0x03E0) | ((fixPaletteTemp & 0x001F) << 10));  // swap Red and Blue
+			//graphics_set_palette(0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1), gb->cgb.fixPalette[0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1)]);
+			emu_SetPaletteEntry(gb->cgb.fixPalette[0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1)]>>16, (gb->cgb.fixPalette[0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1)]>>8) & 0xff, gb->cgb.fixPalette[0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1)] & 0xff, 0x20 + ((gb->cgb.OAMPaletteID & 0x3E) >> 1));
+			if(gb->cgb.OAMPaletteInc) gb->cgb.OAMPaletteID = (++gb->cgb.OAMPaletteID) & 0x3F;
+			return;
+
+		/* CGB WRAM Bank*/
+		case 0x70:
+			gb->cgb.wramBank = val;
+			gb->cgb.wramBankOffset = WRAM_1_ADDR - (1 << 12);
+			if(gb->cgb.cgbMode && (gb->cgb.wramBank & 7) > 0) gb->cgb.wramBankOffset = WRAM_1_ADDR - ((gb->cgb.wramBank & 7) << 12);
+			return;
+#endif
+
+		/* Interrupt Enable Register */
+		case 0xFF:
+			gb->hram_io[IO_IE] = val;
+			return;
+		}
+	}
+
+	/* Invalid writes are ignored. */
+	return;
+}
+
+uint8_t __gb_execute_cb(struct gb_s *gb)
+{
+	uint8_t inst_cycles;
+	uint8_t cbop = __gb_read(gb, gb->cpu_reg.pc.reg++);
+	uint8_t r = (cbop & 0x7);
+	uint8_t b = (cbop >> 3) & 0x7;
+	uint8_t d = (cbop >> 3) & 0x1;
+	uint8_t val;
+	uint8_t writeback = 1;
+
+	inst_cycles = 8;
+	/* Add an additional 8 cycles to these sets of instructions. */
+	switch(cbop & 0xC7)
+	{
+	case 0x06:
+	case 0x86:
+    	case 0xC6:
+		inst_cycles += 8;
+    	break;
+    	case 0x46:
+		inst_cycles += 4;
+    	break;
+	}
+
+	switch(r)
+	{
+	case 0:
+		val = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 1:
+		val = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 2:
+		val = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 3:
+		val = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 4:
+		val = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 5:
+		val = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 6:
+		val = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	/* Only values 0-7 are possible here, so we make the final case
+	 * default to satisfy -Wmaybe-uninitialized warning. */
+	default:
+		val = gb->cpu_reg.a;
+		break;
+	}
+
+	/* TODO: Find out WTF this is doing. */
+	switch(cbop >> 6)
+	{
+	case 0x0:
+		cbop = (cbop >> 4) & 0x3;
+
+		switch(cbop)
+		{
+		case 0x0: /* RdC R */
+		case 0x1: /* Rd R */
+			if(d) /* RRC R / RR R */
+			{
+				uint8_t temp = val;
+				val = (val >> 1);
+				val |= cbop ? (gb->cpu_reg.f_bits.c << 7) : (temp << 7);
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+				gb->cpu_reg.f_bits.c = (temp & 0x01);
+			}
+			else /* RLC R / RL R */
+			{
+				uint8_t temp = val;
+				val = (val << 1);
+				val |= cbop ? gb->cpu_reg.f_bits.c : (temp >> 7);
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+				gb->cpu_reg.f_bits.c = (temp >> 7);
+			}
+
+			break;
+
+		case 0x2:
+			if(d) /* SRA R */
+			{
+				gb->cpu_reg.f_bits.c = val & 0x01;
+				val = (val >> 1) | (val & 0x80);
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+			}
+			else /* SLA R */
+			{
+				gb->cpu_reg.f_bits.c = (val >> 7);
+				val = val << 1;
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+			}
+
+			break;
+
+		case 0x3:
+			if(d) /* SRL R */
+			{
+				gb->cpu_reg.f_bits.c = val & 0x01;
+				val = val >> 1;
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+			}
+			else /* SWAP R */
+			{
+				uint8_t temp = (val >> 4) & 0x0F;
+				temp |= (val << 4) & 0xF0;
+				val = temp;
+				gb->cpu_reg.f_bits.z = (val == 0x00);
+				gb->cpu_reg.f_bits.n = 0;
+				gb->cpu_reg.f_bits.h = 0;
+				gb->cpu_reg.f_bits.c = 0;
+			}
+
+			break;
+		}
+
+		break;
+
+	case 0x1: /* BIT B, R */
+		gb->cpu_reg.f_bits.z = !((val >> b) & 0x1);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 1;
+		writeback = 0;
+		break;
+
+	case 0x2: /* RES B, R */
+		val &= (0xFE << b) | (0xFF >> (8 - b));
+		break;
+
+	case 0x3: /* SET B, R */
+		val |= (0x1 << b);
+		break;
+	}
+
+	if(writeback)
+	{
+		switch(r)
+		{
+		case 0:
+			gb->cpu_reg.bc.bytes.b = val;
+			break;
+
+		case 1:
+			gb->cpu_reg.bc.bytes.c = val;
+			break;
+
+		case 2:
+			gb->cpu_reg.de.bytes.d = val;
+			break;
+
+		case 3:
+			gb->cpu_reg.de.bytes.e = val;
+			break;
+
+		case 4:
+			gb->cpu_reg.hl.bytes.h = val;
+			break;
+
+		case 5:
+			gb->cpu_reg.hl.bytes.l = val;
+			break;
+
+		case 6:
+			__gb_write(gb, gb->cpu_reg.hl.reg, val);
+			break;
+
+		case 7:
+			gb->cpu_reg.a = val;
+			break;
+		}
+	}
+	return inst_cycles;
+}
+
+#if ENABLE_LCD
+struct sprite_data {
+	uint8_t sprite_number;
+	uint8_t x;
+};
+
+#if PEANUT_GB_HIGH_LCD_ACCURACY
+static int compare_sprites(const void *in1, const void *in2)
+{
+	const struct sprite_data *sd1, *sd2;
+	int x_res;
+
+	sd1 = (struct sprite_data *)in1;
+	sd2 = (struct sprite_data *)in2;
+	x_res = (int)sd1->x - (int)sd2->x;
+	if(x_res != 0)
+		return x_res;
+
+	return (int)sd1->sprite_number - (int)sd2->sprite_number;
+}
+#endif
+
+void __gb_draw_line(struct gb_s *gb)
+{
+	uint8_t pixels[160] = {0};
+
+	/* If LCD not initialised by front-end, don't render anything. */
+	if(gb->display.lcd_draw_line == NULL)
+		return;
+
+	if(gb->direct.frame_skip && !gb->display.frame_skip_count)
+		return;
+
+#if PEANUT_FULL_GBC_SUPPORT
+	uint8_t pixelsPrio[160] = {0};  //do these pixels have priority over OAM?
+#endif
+	/* If interlaced mode is activated, check if we need to draw the current
+	 * line. */
+	if(gb->direct.interlace)
+	{
+		if((gb->display.interlace_count == 0
+				&& (gb->hram_io[IO_LY] & 1) == 0)
+				|| (gb->display.interlace_count == 1
+				    && (gb->hram_io[IO_LY] & 1) == 1))
+		{
+			/* Compensate for missing window draw if required. */
+			if(gb->hram_io[IO_LCDC] & LCDC_WINDOW_ENABLE
+					&& gb->hram_io[IO_LY] >= gb->display.WY
+					&& gb->hram_io[IO_WX] <= 166)
+				gb->display.window_clear++;
+
+			return;
+		}
+	}
+
+	/* If background is enabled, draw it. */
+#if PEANUT_FULL_GBC_SUPPORT
+	if(gb->cgb.cgbMode || gb->hram_io[IO_LCDC] & LCDC_BG_ENABLE)
+#else
+	if(gb->hram_io[IO_LCDC] & LCDC_BG_ENABLE)
+#endif
+	{
+		uint8_t bg_y, disp_x, bg_x, idx, py, px, t1, t2;
+		uint16_t bg_map, tile;
+
+		/* Calculate current background line to draw. Constant because
+		 * this function draws only this one line each time it is
+		 * called. */
+		bg_y = gb->hram_io[IO_LY] + gb->hram_io[IO_SCY];
+
+		/* Get selected background map address for first tile
+		 * corresponding to current line.
+		 * 0x20 (32) is the width of a background tile, and the bit
+		 * shift is to calculate the address. */
+		bg_map =
+			((gb->hram_io[IO_LCDC] & LCDC_BG_MAP) ?
+			 VRAM_BMAP_2 : VRAM_BMAP_1)
+			+ ((bg_y >> 3) << 5);
+
+		/* The displays (what the player sees) X coordinate, drawn right
+		 * to left. */
+		disp_x = LCD_WIDTH - 1;
+
+		/* The X coordinate to begin drawing the background at. */
+		bg_x = disp_x + gb->hram_io[IO_SCX];
+
+		/* Get tile index for current background tile. */
+		idx = gb->vram[bg_map + (bg_x >> 3)];
+#if PEANUT_FULL_GBC_SUPPORT
+		uint8_t idxAtt = gb->vram[bg_map + (bg_x >> 3) + 0x2000];
+#endif
+		/* Y coordinate of tile pixel to draw. */
+		py = (bg_y & 0x07);
+		/* X coordinate of tile pixel to draw. */
+		px = 7 - (bg_x & 0x07);
+
+		/* Select addressing mode. */
+		if(gb->hram_io[IO_LCDC] & LCDC_TILE_SELECT)
+			tile = VRAM_TILES_1 + (idx << 4);
+		else
+			tile = VRAM_TILES_2 + (((idx + 0x80) % 0x100) << 4);
+
+#if PEANUT_FULL_GBC_SUPPORT
+		if(gb->cgb.cgbMode)
+		{
+			if(idxAtt & 0x08) tile += 0x2000; //VRAM bank 2
+			if(idxAtt & 0x40) tile += 2 * (7 - py);
+		}
+		if(!(idxAtt & 0x40))
+		{
+			tile += py << 1;
+		}
+
+		/* fetch first tile */
+		if(gb->cgb.cgbMode && (idxAtt & 0x20))
+		{  //Horizantal Flip
+			t1 = gb->vram[tile] << px;
+			t2 = gb->vram[tile + 1] << px;
+		}
+		else
+		{
+			t1 = gb->vram[tile] >> px;
+			t2 = gb->vram[tile + 1] >> px;
+		}
+#else
+		tile += 2 * py;
+
+		/* fetch first tile */
+		t1 = gb->vram[tile] >> px;
+		t2 = gb->vram[tile + 1] >> px;
+#endif
+		for(; disp_x != 0xFF; disp_x--)
+		{
+			uint8_t c;
+
+			if(px == 8)
+			{
+				/* fetch next tile */
+				px = 0;
+				bg_x = disp_x + gb->hram_io[IO_SCX];
+				idx = gb->vram[bg_map + (bg_x >> 3)];
+#if PEANUT_FULL_GBC_SUPPORT
+				idxAtt = gb->vram[bg_map + (bg_x >> 3) + 0x2000];
+#endif
+				if(gb->hram_io[IO_LCDC] & LCDC_TILE_SELECT)
+					tile = VRAM_TILES_1 + (idx << 4);
+				else
+					tile = VRAM_TILES_2 + (((idx + 0x80) % 0x100) << 4);
+
+#if PEANUT_FULL_GBC_SUPPORT
+				if(gb->cgb.cgbMode)
+				{
+					if(idxAtt & 0x08) tile += 0x2000; //VRAM bank 2
+					if(idxAtt & 0x40) tile += 2 * (7 - py);
+				}
+				if(!(idxAtt & 0x40))
+				{
+                    tile += py << 1;
+				}
+#else
+                tile += py << 1;
+#endif
+				t1 = gb->vram[tile];
+				t2 = gb->vram[tile + 1];
+			}
+
+			/* copy background */
+#if PEANUT_FULL_GBC_SUPPORT
+			if(gb->cgb.cgbMode && (idxAtt & 0x20))
+			{  //Horizantal Flip
+				c = (((t1 & 0x80) >> 1) | (t2 & 0x80)) >> 6;
+				pixels[disp_x] = ((idxAtt & 0x07) << 2) + c;
+				pixelsPrio[disp_x] = (idxAtt >> 7);
+				t1 = t1 << 1;
+				t2 = t2 << 1;
+			}
+			else
+			{
+				c = (t1 & 0x1) | ((t2 & 0x1) << 1);
+				if(gb->cgb.cgbMode)
+				{
+					pixels[disp_x] = ((idxAtt & 0x07) << 2) + c;
+					pixelsPrio[disp_x] = (idxAtt >> 7);
+				}
+				else
+				{
+					pixels[disp_x] = gb->display.bg_palette[c];
+#if PEANUT_GB_12_COLOUR
+					pixels[disp_x] |= LCD_PALETTE_BG;
+#endif
+				}
+				t1 = t1 >> 1;
+				t2 = t2 >> 1;
+			}
+#else
+			c = (t1 & 0x1) | ((t2 & 0x1) << 1);
+			pixels[disp_x] = gb->display.bg_palette[c];
+#if PEANUT_GB_12_COLOUR
+			pixels[disp_x] |= LCD_PALETTE_BG;
+#endif
+			t1 = t1 >> 1;
+			t2 = t2 >> 1;
+#endif
+			px++;
+		}
+	}
+
+	/* draw window */
+	if(gb->hram_io[IO_LCDC] & LCDC_WINDOW_ENABLE
+			&& gb->hram_io[IO_LY] >= gb->display.WY
+			&& gb->hram_io[IO_WX] <= 166)
+	{
+		uint16_t win_line, tile;
+		uint8_t disp_x, win_x, py, px, idx, t1, t2, end;
+
+		/* Calculate Window Map Address. */
+		win_line = (gb->hram_io[IO_LCDC] & LCDC_WINDOW_MAP) ?
+				    VRAM_BMAP_2 : VRAM_BMAP_1;
+		win_line += (gb->display.window_clear >> 3) << 5;
+
+		disp_x = LCD_WIDTH - 1;
+		win_x = disp_x - gb->hram_io[IO_WX] + 7;
+
+		// look up tile
+		py = gb->display.window_clear & 0x07;
+		px = 7 - (win_x & 0x07);
+		idx = gb->vram[win_line + (win_x >> 3)];
+#if PEANUT_FULL_GBC_SUPPORT
+		uint8_t idxAtt = gb->vram[win_line + (win_x >> 3) + 0x2000];
+#endif
+
+		if(gb->hram_io[IO_LCDC] & LCDC_TILE_SELECT)
+			tile = VRAM_TILES_1 + (idx << 4);
+		else
+			tile = VRAM_TILES_2 + (((idx + 0x80) % 0x100) << 4);
+
+#if PEANUT_FULL_GBC_SUPPORT
+		if(gb->cgb.cgbMode)
+		{
+			if(idxAtt & 0x08) tile += 0x2000; //VRAM bank 2
+			if(idxAtt & 0x40) tile += 2 * (7 - py);
+		}
+		if(!(idxAtt & 0x40))
+		{
+            tile += py << 1;
+		}
+
+		// fetch first tile
+		if(gb->cgb.cgbMode && (idxAtt & 0x20))
+		{  //Horizantal Flip
+			t1 = gb->vram[tile] << px;
+			t2 = gb->vram[tile + 1] << px;
+		}
+		else
+		{
+			t1 = gb->vram[tile] >> px;
+			t2 = gb->vram[tile + 1] >> px;
+		}
+#else
+        tile += py << 1;
+
+		// fetch first tile
+		t1 = gb->vram[tile] >> px;
+		t2 = gb->vram[tile + 1] >> px;
+#endif
+		// loop & copy window
+		end = (gb->hram_io[IO_WX] < 7 ? 0 : gb->hram_io[IO_WX] - 7) - 1;
+
+		for(; disp_x != end; disp_x--)
+		{
+			uint8_t c;
+
+			if(px == 8)
+			{
+				// fetch next tile
+				px = 0;
+				win_x = disp_x - gb->hram_io[IO_WX] + 7;
+				idx = gb->vram[win_line + (win_x >> 3)];
+#if PEANUT_FULL_GBC_SUPPORT
+				idxAtt = gb->vram[win_line + (win_x >> 3) + 0x2000];
+#endif
+
+				if(gb->hram_io[IO_LCDC] & LCDC_TILE_SELECT)
+					tile = VRAM_TILES_1 + (idx << 4);
+				else
+					tile = VRAM_TILES_2 + (((idx + 0x80) % 0x100) << 4);
+
+#if PEANUT_FULL_GBC_SUPPORT
+				if(gb->cgb.cgbMode)
+				{
+					if(idxAtt & 0x08) tile += 0x2000; //VRAM bank 2
+					if(idxAtt & 0x40) tile += 2 * (7 - py);
+				}
+				if(!(idxAtt & 0x40))
+				{
+                    tile += py << 1;
+				}
+#else
+                tile += py << 1;
+#endif
+				t1 = gb->vram[tile];
+				t2 = gb->vram[tile + 1];
+			}
+
+			// copy window
+#if PEANUT_FULL_GBC_SUPPORT
+			if(idxAtt & 0x20)
+			{  //Horizantal Flip
+				c = (((t1 & 0x80) >> 1) | (t2 & 0x80)) >> 6;
+				pixels[disp_x] = ((idxAtt & 0x07) << 2) + c;
+				pixelsPrio[disp_x] = (idxAtt >> 7);
+				t1 = t1 << 1;
+				t2 = t2 << 1;
+			}
+			else
+			{
+				c = (t1 & 0x1) | ((t2 & 0x1) << 1);
+				if(gb->cgb.cgbMode)
+				{
+					pixels[disp_x] = ((idxAtt & 0x07) << 2) + c;
+					pixelsPrio[disp_x] = (idxAtt >> 7);
+				}
+				else
+				{
+					pixels[disp_x] = gb->display.bg_palette[c];
+#if PEANUT_GB_12_COLOUR
+					pixels[disp_x] |= LCD_PALETTE_BG;
+#endif
+				}
+				t1 = t1 >> 1;
+				t2 = t2 >> 1;
+			}
+#else
+			c = (t1 & 0x1) | ((t2 & 0x1) << 1);
+			pixels[disp_x] = gb->display.bg_palette[c];
+#if PEANUT_GB_12_COLOUR
+			pixels[disp_x] |= LCD_PALETTE_BG;
+#endif
+			t1 = t1 >> 1;
+			t2 = t2 >> 1;
+#endif
+			px++;
+		}
+
+		gb->display.window_clear++; // advance window line
+	}
+
+	// draw sprites
+	if(gb->hram_io[IO_LCDC] & LCDC_OBJ_ENABLE)
+	{
+		uint8_t sprite_number;
+#if PEANUT_GB_HIGH_LCD_ACCURACY
+		uint8_t number_of_sprites = 0;
+
+		struct sprite_data sprites_to_render[NUM_SPRITES];
+
+		/* Record number of sprites on the line being rendered, limited
+		 * to the maximum number sprites that the Game Boy is able to
+		 * render on each line (10 sprites). */
+		for(sprite_number = 0;
+				sprite_number < PEANUT_GB_ARRAYSIZE(sprites_to_render);
+				sprite_number++)
+		{
+			/* Sprite Y position. */
+			uint8_t OY = gb->oam[sprite_number << 2];
+			/* Sprite X position. */
+			uint8_t OX = gb->oam[(sprite_number << 2)+ 1];
+
+			/* If sprite isn't on this line, continue. */
+			if(gb->hram_io[IO_LY] +
+				(gb->hram_io[IO_LCDC] & LCDC_OBJ_SIZE ? 0 : 8) >= OY
+					|| gb->hram_io[IO_LY] + 16 < OY)
+				continue;
+
+
+			sprites_to_render[number_of_sprites].sprite_number = sprite_number;
+			sprites_to_render[number_of_sprites].x = OX;
+			number_of_sprites++;
+		}
+#if PEANUT_FULL_GBC_SUPPORT
+		if(!gb->cgb.cgbMode)
+		{
+#endif
+		/* If maximum number of sprites reached, prioritise X
+		 * coordinate and object location in OAM. */
+		qsort(&sprites_to_render[0], number_of_sprites,
+				sizeof(sprites_to_render[0]), compare_sprites);
+#if PEANUT_FULL_GBC_SUPPORT
+		}
+#endif
+		if(number_of_sprites > MAX_SPRITES_LINE)
+			number_of_sprites = MAX_SPRITES_LINE;
+#endif
+
+		/* Render each sprite, from low priority to high priority. */
+#if PEANUT_GB_HIGH_LCD_ACCURACY
+		/* Render the top ten prioritised sprites on this scanline. */
+		for(sprite_number = number_of_sprites - 1;
+				sprite_number != 0xFF;
+				sprite_number--)
+		{
+			uint8_t s = sprites_to_render[sprite_number].sprite_number;
+#else
+		for (sprite_number = NUM_SPRITES - 1;
+			sprite_number != 0xFF;
+			sprite_number--)
+		{
+			uint8_t s = sprite_number;
+#endif
+			uint8_t py, t1, t2, dir, start, end, shift, disp_x;
+			/* Sprite Y position. */
+			uint8_t OY = gb->oam[s << 2];
+			/* Sprite X position. */
+			uint8_t OX = gb->oam[(s << 2) + 1];
+			/* Sprite Tile/Pattern Number. */
+			uint8_t OT = gb->oam[(s << 2) + 2]
+				     & (gb->hram_io[IO_LCDC] & LCDC_OBJ_SIZE ? 0xFE : 0xFF);
+			/* Additional attributes. */
+			uint8_t OF = gb->oam[(s << 2) + 3];
+
+#if !PEANUT_GB_HIGH_LCD_ACCURACY
+			/* If sprite isn't on this line, continue. */
+			if(gb->hram_io[IO_LY] +
+					(gb->hram_io[IO_LCDC] & LCDC_OBJ_SIZE ? 0 : 8) >= OY ||
+					gb->hram_io[IO_LY] + 16 < OY)
+				continue;
+#endif
+
+			/* Continue if sprite not visible. */
+			if(OX == 0 || OX >= 168)
+				continue;
+
+			// y flip
+			py = gb->hram_io[IO_LY] - OY + 16;
+
+			if(OF & OBJ_FLIP_Y)
+				py = (gb->hram_io[IO_LCDC] & LCDC_OBJ_SIZE ? 15 : 7) - py;
+
+			// fetch the tile
+#if PEANUT_FULL_GBC_SUPPORT
+			if(gb->cgb.cgbMode)
+			{
+				t1 = gb->vram[((OF & OBJ_BANK) << 10) + VRAM_TILES_1 + (OT << 4) + (py << 1)];
+				t2 = gb->vram[((OF & OBJ_BANK) << 10) + VRAM_TILES_1 + (OT << 4) + (py << 1) + 1];
+			}
+			else
+#endif
+			{
+				t1 = gb->vram[VRAM_TILES_1 + OT * 0x10 + 2 * py];
+				t2 = gb->vram[VRAM_TILES_1 + OT * 0x10 + 2 * py + 1];
+			}
+
+			// handle x flip
+			if(OF & OBJ_FLIP_X)
+			{
+				dir = 1;
+				start = (OX < 8 ? 0 : OX - 8);
+				end = MIN(OX, LCD_WIDTH);
+				shift = 8 - OX + start;
+			}
+			else
+			{
+				dir = (uint8_t)-1;
+				start = MIN(OX, LCD_WIDTH) - 1;
+				end = (OX < 8 ? 0 : OX - 8) - 1;
+				shift = OX - (start + 1);
+			}
+
+			// copy tile
+			t1 >>= shift;
+			t2 >>= shift;
+
+			/* TODO: Put for loop within the to if statements
+			 * because the BG priority bit will be the same for
+			 * all the pixels in the tile. */
+			for(disp_x = start; disp_x != end; disp_x += dir)
+			{
+				uint8_t c = (t1 & 0x1) | ((t2 & 0x1) << 1);
+				// check transparency / sprite overlap / background overlap
+#if PEANUT_FULL_GBC_SUPPORT
+				if(gb->cgb.cgbMode)
+				{
+					uint8_t isBackgroundDisabled = c && !(gb->hram_io[IO_LCDC] & LCDC_BG_ENABLE);
+					uint8_t isPixelPriorityNonConflicting = c &&
+															!(pixelsPrio[disp_x] && (pixels[disp_x] & 0x3)) &&
+															!((OF & OBJ_PRIORITY) && (pixels[disp_x] & 0x3));
+
+					if(isBackgroundDisabled || isPixelPriorityNonConflicting)
+					{
+						/* Set pixel colour. */
+						pixels[disp_x] = ((OF & OBJ_CGB_PALETTE) << 2) + c + 0x20;  // add 0x20 to differentiate from BG
+					}
+				}
+				else
+#endif
+				if(c && !(OF & OBJ_PRIORITY && !((pixels[disp_x] & 0x3) == gb->display.bg_palette[0])))
+				{
+					/* Set pixel colour. */
+					pixels[disp_x] = (OF & OBJ_PALETTE)
+						? gb->display.sp_palette[c + 4]
+						: gb->display.sp_palette[c];
+#if PEANUT_GB_12_COLOUR
+					/* Set pixel palette (OBJ0 or OBJ1). */
+					pixels[disp_x] |= (OF & OBJ_PALETTE);
+#endif
+#if PEANUT_FULL_GBC_SUPPORT
+					/* Deselect BG palette. */
+					pixels[disp_x] &= ~LCD_PALETTE_BG;
+#endif
+				}
+
+				t1 = t1 >> 1;
+				t2 = t2 >> 1;
+			}
+		}
+	}
+
+	gb->display.lcd_draw_line(gb, pixels, gb->hram_io[IO_LY]);
+}
+#endif
+
+/**
+ * Internal function used to step the CPU.
+ */
+void __gb_step_cpu(struct gb_s *gb)
+{
+	uint8_t opcode;
+	uint_fast16_t inst_cycles;
+	static const uint8_t op_cycles[0x100] =
+	{
+		/* *INDENT-OFF* */
+		/*0 1 2  3  4  5  6  7  8  9  A  B  C  D  E  F	*/
+		4,12, 8, 8, 4, 4, 8, 4,20, 8, 8, 8, 4, 4, 8, 4,	/* 0x00 */
+		4,12, 8, 8, 4, 4, 8, 4,12, 8, 8, 8, 4, 4, 8, 4,	/* 0x10 */
+		8,12, 8, 8, 4, 4, 8, 4, 8, 8, 8, 8, 4, 4, 8, 4,	/* 0x20 */
+		8,12, 8, 8,12,12,12, 4, 8, 8, 8, 8, 4, 4, 8, 4,	/* 0x30 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0x40 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0x50 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0x60 */
+		8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4, /* 0x70 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0x80 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0x90 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0xA0 */
+		4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,	/* 0xB0 */
+		8,12,12,16,12,16, 8,16, 8,16,12, 8,12,24, 8,16,	/* 0xC0 */
+		8,12,12, 0,12,16, 8,16, 8,16,12, 0,12, 0, 8,16,	/* 0xD0 */
+		12,12,8, 0, 0,16, 8,16,16, 4,16, 0, 0, 0, 8,16,	/* 0xE0 */
+		12,12,8, 4, 0,16, 8,16,12, 8,16, 4, 0, 0, 8,16	/* 0xF0 */
+		/* *INDENT-ON* */
+	};
+	static const uint_fast16_t TAC_CYCLES[4] = {1024, 16, 64, 256};
+
+	/* Handle interrupts */
+	/* If gb_halt is positive, then an interrupt must have occured by the
+	 * time we reach here, becuase on HALT, we jump to the next interrupt
+	 * immediately. */
+	while(gb->gb_halt || (gb->gb_ime &&
+			gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & ANY_INTR))
+	{
+		gb->gb_halt = 0;
+
+		if(!gb->gb_ime)
+			break;
+
+		/* Disable interrupts */
+		gb->gb_ime = 0;
+
+		/* Push Program Counter */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+
+		/* Call interrupt handler if required. */
+		if(gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & VBLANK_INTR)
+		{
+			gb->cpu_reg.pc.reg = VBLANK_INTR_ADDR;
+			gb->hram_io[IO_IF] ^= VBLANK_INTR;
+		}
+		else if(gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & LCDC_INTR)
+		{
+			gb->cpu_reg.pc.reg = LCDC_INTR_ADDR;
+			gb->hram_io[IO_IF] ^= LCDC_INTR;
+		}
+		else if(gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & TIMER_INTR)
+		{
+			gb->cpu_reg.pc.reg = TIMER_INTR_ADDR;
+			gb->hram_io[IO_IF] ^= TIMER_INTR;
+		}
+		else if(gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & SERIAL_INTR)
+		{
+			gb->cpu_reg.pc.reg = SERIAL_INTR_ADDR;
+			gb->hram_io[IO_IF] ^= SERIAL_INTR;
+		}
+		else if(gb->hram_io[IO_IF] & gb->hram_io[IO_IE] & CONTROL_INTR)
+		{
+			gb->cpu_reg.pc.reg = CONTROL_INTR_ADDR;
+			gb->hram_io[IO_IF] ^= CONTROL_INTR;
+		}
+
+		break;
+	}
+
+	/* Obtain opcode */
+	opcode = __gb_read(gb, gb->cpu_reg.pc.reg++);
+	inst_cycles = op_cycles[opcode];
+
+	/* Execute opcode */
+	switch(opcode)
+	{
+	case 0x00: /* NOP */
+		break;
+
+	case 0x01: /* LD BC, imm */
+		gb->cpu_reg.bc.bytes.c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.bc.bytes.b = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x02: /* LD (BC), A */
+		__gb_write(gb, gb->cpu_reg.bc.reg, gb->cpu_reg.a);
+		break;
+
+	case 0x03: /* INC BC */
+		gb->cpu_reg.bc.reg++;
+		break;
+
+	case 0x04: /* INC B */
+		gb->cpu_reg.bc.bytes.b++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.bc.bytes.b == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.bc.bytes.b & 0x0F) == 0x00);
+		break;
+
+	case 0x05: /* DEC B */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0x06: /* LD B, imm */
+		gb->cpu_reg.bc.bytes.b = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x07: /* RLCA */
+		gb->cpu_reg.a = (gb->cpu_reg.a << 1) | (gb->cpu_reg.a >> 7);
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = (gb->cpu_reg.a & 0x01);
+		break;
+
+	case 0x08: /* LD (imm), SP */
+	{
+		uint8_t h, l;
+		uint16_t temp;
+		l = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		h = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		temp = PEANUT_GB_U8_TO_U16(h,l);
+		__gb_write(gb, temp++, gb->cpu_reg.sp.bytes.p);
+		__gb_write(gb, temp, gb->cpu_reg.sp.bytes.s);
+		break;
+	}
+
+	case 0x09: /* ADD HL, BC */
+	{
+		uint_fast32_t temp = gb->cpu_reg.hl.reg + gb->cpu_reg.bc.reg;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h =
+			(temp ^ gb->cpu_reg.hl.reg ^ gb->cpu_reg.bc.reg) & 0x1000 ? 1 : 0;
+		gb->cpu_reg.f_bits.c = (temp & 0xFFFF0000) ? 1 : 0;
+		gb->cpu_reg.hl.reg = (temp & 0x0000FFFF);
+		break;
+	}
+
+	case 0x0A: /* LD A, (BC) */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.bc.reg);
+		break;
+
+	case 0x0B: /* DEC BC */
+		gb->cpu_reg.bc.reg--;
+		break;
+
+	case 0x0C: /* INC C */
+		gb->cpu_reg.bc.bytes.c++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.bc.bytes.c == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.bc.bytes.c & 0x0F) == 0x00);
+		break;
+
+	case 0x0D: /* DEC C */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0x0E: /* LD C, imm */
+		gb->cpu_reg.bc.bytes.c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x0F: /* RRCA */
+		gb->cpu_reg.f_bits.c = gb->cpu_reg.a & 0x01;
+		gb->cpu_reg.a = (gb->cpu_reg.a >> 1) | (gb->cpu_reg.a << 7);
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		break;
+
+	case 0x10: /* STOP */
+		//gb->gb_halt = 1;
+#if PEANUT_FULL_GBC_SUPPORT
+		if(gb->cgb.cgbMode & gb->cgb.doubleSpeedPrep)
+		{
+			gb->cgb.doubleSpeedPrep = 0;
+			gb->cgb.doubleSpeed ^= 1;
+		}
+#endif
+		break;
+
+	case 0x11: /* LD DE, imm */
+		gb->cpu_reg.de.bytes.e = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.de.bytes.d = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x12: /* LD (DE), A */
+		__gb_write(gb, gb->cpu_reg.de.reg, gb->cpu_reg.a);
+		break;
+
+	case 0x13: /* INC DE */
+		gb->cpu_reg.de.reg++;
+		break;
+
+	case 0x14: /* INC D */
+		gb->cpu_reg.de.bytes.d++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.de.bytes.d == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.de.bytes.d & 0x0F) == 0x00);
+		break;
+
+	case 0x15: /* DEC D */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0x16: /* LD D, imm */
+		gb->cpu_reg.de.bytes.d = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x17: /* RLA */
+	{
+		uint8_t temp = gb->cpu_reg.a;
+		gb->cpu_reg.a = (gb->cpu_reg.a << 1) | gb->cpu_reg.f_bits.c;
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = (temp >> 7) & 0x01;
+		break;
+	}
+
+	case 0x18: /* JR imm */
+	{
+		int8_t temp = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.pc.reg += temp;
+		break;
+	}
+
+	case 0x19: /* ADD HL, DE */
+	{
+		uint_fast32_t temp = gb->cpu_reg.hl.reg + gb->cpu_reg.de.reg;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h =
+			(temp ^ gb->cpu_reg.hl.reg ^ gb->cpu_reg.de.reg) & 0x1000 ? 1 : 0;
+		gb->cpu_reg.f_bits.c = (temp & 0xFFFF0000) ? 1 : 0;
+		gb->cpu_reg.hl.reg = (temp & 0x0000FFFF);
+		break;
+	}
+
+	case 0x1A: /* LD A, (DE) */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.de.reg);
+		break;
+
+	case 0x1B: /* DEC DE */
+		gb->cpu_reg.de.reg--;
+		break;
+
+	case 0x1C: /* INC E */
+		gb->cpu_reg.de.bytes.e++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.de.bytes.e == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.de.bytes.e & 0x0F) == 0x00);
+		break;
+
+	case 0x1D: /* DEC E */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0x1E: /* LD E, imm */
+		gb->cpu_reg.de.bytes.e = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x1F: /* RRA */
+	{
+		uint8_t temp = gb->cpu_reg.a;
+		gb->cpu_reg.a = gb->cpu_reg.a >> 1 | (gb->cpu_reg.f_bits.c << 7);
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = temp & 0x1;
+		break;
+	}
+
+	case 0x20: /* JR NZ, imm */
+		if(!gb->cpu_reg.f_bits.z)
+		{
+			int8_t temp = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+			gb->cpu_reg.pc.reg += temp;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg++;
+
+		break;
+
+	case 0x21: /* LD HL, imm */
+		gb->cpu_reg.hl.bytes.l = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.hl.bytes.h = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x22: /* LDI (HL), A */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.a);
+		gb->cpu_reg.hl.reg++;
+		break;
+
+	case 0x23: /* INC HL */
+		gb->cpu_reg.hl.reg++;
+		break;
+
+	case 0x24: /* INC H */
+		gb->cpu_reg.hl.bytes.h++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.hl.bytes.h == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.hl.bytes.h & 0x0F) == 0x00);
+		break;
+
+	case 0x25: /* DEC H */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0x26: /* LD H, imm */
+		gb->cpu_reg.hl.bytes.h = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x27: /* DAA */
+	{
+		/* The following is from SameBoy. MIT License. */
+		int16_t a = gb->cpu_reg.a;
+
+		if(gb->cpu_reg.f_bits.n)
+		{
+			if(gb->cpu_reg.f_bits.h)
+				a = (a - 0x06) & 0xFF;
+
+			if(gb->cpu_reg.f_bits.c)
+				a -= 0x60;
+		}
+		else
+		{
+			if(gb->cpu_reg.f_bits.h || (a & 0x0F) > 9)
+				a += 0x06;
+
+			if(gb->cpu_reg.f_bits.c || a > 0x9F)
+				a += 0x60;
+		}
+
+		if((a & 0x100) == 0x100)
+			gb->cpu_reg.f_bits.c = 1;
+
+		gb->cpu_reg.a = a;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0);
+		gb->cpu_reg.f_bits.h = 0;
+
+		break;
+	}
+
+	case 0x28: /* JR Z, imm */
+		if(gb->cpu_reg.f_bits.z)
+		{
+			int8_t temp = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+			gb->cpu_reg.pc.reg += temp;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg++;
+
+		break;
+
+	case 0x29: /* ADD HL, HL */
+	{
+		gb->cpu_reg.f_bits.c = (gb->cpu_reg.hl.reg & 0x8000) > 0;
+		gb->cpu_reg.hl.reg <<= 1;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = (gb->cpu_reg.hl.reg & 0x1000) > 0;
+		break;
+	}
+
+	case 0x2A: /* LD A, (HL+) */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.hl.reg++);
+		break;
+
+	case 0x2B: /* DEC HL */
+		gb->cpu_reg.hl.reg--;
+		break;
+
+	case 0x2C: /* INC L */
+		gb->cpu_reg.hl.bytes.l++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.hl.bytes.l == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.hl.bytes.l & 0x0F) == 0x00);
+		break;
+
+	case 0x2D: /* DEC L */
+		PGB_INSTR_DEC_R8(gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0x2E: /* LD L, imm */
+		gb->cpu_reg.hl.bytes.l = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x2F: /* CPL */
+		gb->cpu_reg.a = ~gb->cpu_reg.a;
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = 1;
+		break;
+
+	case 0x30: /* JR NC, imm */
+		if(!gb->cpu_reg.f_bits.c)
+		{
+			int8_t temp = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+			gb->cpu_reg.pc.reg += temp;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg++;
+
+		break;
+
+	case 0x31: /* LD SP, imm */
+		gb->cpu_reg.sp.bytes.p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.sp.bytes.s = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x32: /* LD (HL), A */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.a);
+		gb->cpu_reg.hl.reg--;
+		break;
+
+	case 0x33: /* INC SP */
+		gb->cpu_reg.sp.reg++;
+		break;
+
+	case 0x34: /* INC (HL) */
+	{
+		uint8_t temp = __gb_read(gb, gb->cpu_reg.hl.reg) + 1;
+		gb->cpu_reg.f_bits.z = (temp == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((temp & 0x0F) == 0x00);
+		__gb_write(gb, gb->cpu_reg.hl.reg, temp);
+		break;
+	}
+
+	case 0x35: /* DEC (HL) */
+	{
+		uint8_t temp = __gb_read(gb, gb->cpu_reg.hl.reg) - 1;
+		gb->cpu_reg.f_bits.z = (temp == 0x00);
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = ((temp & 0x0F) == 0x0F);
+		__gb_write(gb, gb->cpu_reg.hl.reg, temp);
+		break;
+	}
+
+	case 0x36: /* LD (HL), imm */
+		__gb_write(gb, gb->cpu_reg.hl.reg, __gb_read(gb, gb->cpu_reg.pc.reg++));
+		break;
+
+	case 0x37: /* SCF */
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = 1;
+		break;
+
+	case 0x38: /* JR C, imm */
+		if(gb->cpu_reg.f_bits.c)
+		{
+			int8_t temp = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+			gb->cpu_reg.pc.reg += temp;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg++;
+
+		break;
+
+	case 0x39: /* ADD HL, SP */
+	{
+		uint_fast32_t temp = gb->cpu_reg.hl.reg + gb->cpu_reg.sp.reg;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h =
+			((gb->cpu_reg.hl.reg & 0xFFF) + (gb->cpu_reg.sp.reg & 0xFFF)) & 0x1000 ? 1 : 0;
+		gb->cpu_reg.f_bits.c = temp & 0x10000 ? 1 : 0;
+		gb->cpu_reg.hl.reg = (uint16_t)temp;
+		break;
+	}
+
+	case 0x3A: /* LD A, (HL) */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.hl.reg--);
+		break;
+
+	case 0x3B: /* DEC SP */
+		gb->cpu_reg.sp.reg--;
+		break;
+
+	case 0x3C: /* INC A */
+		gb->cpu_reg.a++;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a & 0x0F) == 0x00);
+		break;
+
+	case 0x3D: /* DEC A */
+		gb->cpu_reg.a--;
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a & 0x0F) == 0x0F);
+		break;
+
+	case 0x3E: /* LD A, imm */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		break;
+
+	case 0x3F: /* CCF */
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = ~gb->cpu_reg.f_bits.c;
+		break;
+
+	case 0x40: /* LD B, B */
+		break;
+
+	case 0x41: /* LD B, C */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x42: /* LD B, D */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x43: /* LD B, E */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x44: /* LD B, H */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x45: /* LD B, L */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x46: /* LD B, (HL) */
+		gb->cpu_reg.bc.bytes.b = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x47: /* LD B, A */
+		gb->cpu_reg.bc.bytes.b = gb->cpu_reg.a;
+		break;
+
+	case 0x48: /* LD C, B */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x49: /* LD C, C */
+		break;
+
+	case 0x4A: /* LD C, D */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x4B: /* LD C, E */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x4C: /* LD C, H */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x4D: /* LD C, L */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x4E: /* LD C, (HL) */
+		gb->cpu_reg.bc.bytes.c = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x4F: /* LD C, A */
+		gb->cpu_reg.bc.bytes.c = gb->cpu_reg.a;
+		break;
+
+	case 0x50: /* LD D, B */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x51: /* LD D, C */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x52: /* LD D, D */
+		break;
+
+	case 0x53: /* LD D, E */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x54: /* LD D, H */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x55: /* LD D, L */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x56: /* LD D, (HL) */
+		gb->cpu_reg.de.bytes.d = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x57: /* LD D, A */
+		gb->cpu_reg.de.bytes.d = gb->cpu_reg.a;
+		break;
+
+	case 0x58: /* LD E, B */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x59: /* LD E, C */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x5A: /* LD E, D */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x5B: /* LD E, E */
+		break;
+
+	case 0x5C: /* LD E, H */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x5D: /* LD E, L */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x5E: /* LD E, (HL) */
+		gb->cpu_reg.de.bytes.e = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x5F: /* LD E, A */
+		gb->cpu_reg.de.bytes.e = gb->cpu_reg.a;
+		break;
+
+	case 0x60: /* LD H, B */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x61: /* LD H, C */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x62: /* LD H, D */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x63: /* LD H, E */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x64: /* LD H, H */
+		break;
+
+	case 0x65: /* LD H, L */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x66: /* LD H, (HL) */
+		gb->cpu_reg.hl.bytes.h = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x67: /* LD H, A */
+		gb->cpu_reg.hl.bytes.h = gb->cpu_reg.a;
+		break;
+
+	case 0x68: /* LD L, B */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x69: /* LD L, C */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x6A: /* LD L, D */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x6B: /* LD L, E */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x6C: /* LD L, H */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x6D: /* LD L, L */
+		break;
+
+	case 0x6E: /* LD L, (HL) */
+		gb->cpu_reg.hl.bytes.l = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x6F: /* LD L, A */
+		gb->cpu_reg.hl.bytes.l = gb->cpu_reg.a;
+		break;
+
+	case 0x70: /* LD (HL), B */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0x71: /* LD (HL), C */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0x72: /* LD (HL), D */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0x73: /* LD (HL), E */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0x74: /* LD (HL), H */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0x75: /* LD (HL), L */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0x76: /* HALT */
+	{
+		int_fast16_t halt_cycles = INT_FAST16_MAX;
+
+		/* TODO: Emulate HALT bug? */
+		gb->gb_halt = 1;
+
+		if (gb->hram_io[IO_IE] == 0)
+		{
+			/* Return program counter where this halt forever state started. */
+			/* This may be intentional, but this is required to stop an infinite
+			 * loop. */
+			(gb->gb_error)(gb, GB_HALT_FOREVER, gb->cpu_reg.pc.reg - 1);
+			PGB_UNREACHABLE();
+		}
+
+		if(gb->hram_io[IO_SC] & SERIAL_SC_TX_START)
+		{
+			int serial_cycles = SERIAL_CYCLES -
+				gb->counter.serial_count;
+
+			if(serial_cycles < halt_cycles)
+				halt_cycles = serial_cycles;
+		}
+
+		if(gb->hram_io[IO_TAC] & IO_TAC_ENABLE_MASK)
+		{
+			int tac_cycles = TAC_CYCLES[gb->hram_io[IO_TAC] & IO_TAC_RATE_MASK] -
+				gb->counter.tima_count;
+
+			if(tac_cycles < halt_cycles)
+				halt_cycles = tac_cycles;
+		}
+
+		if((gb->hram_io[IO_LCDC] & LCDC_ENABLE))
+		{
+			int lcd_cycles;
+
+			/* If LCD is in HBlank, calculate the number of cycles
+			 * until the end of HBlank and the start of mode 2 or
+			 * mode 1. */
+			if((gb->hram_io[IO_STAT] & STAT_MODE) == IO_STAT_MODE_HBLANK)
+			{
+				lcd_cycles = LCD_MODE_2_CYCLES -
+					     gb->counter.lcd_count;
+			}
+			else if((gb->hram_io[IO_STAT] & STAT_MODE) == IO_STAT_MODE_SEARCH_OAM)
+			{
+				lcd_cycles = LCD_MODE_3_CYCLES -
+					gb->counter.lcd_count;
+			}
+			else if((gb->hram_io[IO_STAT] & STAT_MODE) == IO_STAT_MODE_SEARCH_TRANSFER)
+			{
+				lcd_cycles = LCD_MODE_0_CYCLES -
+					gb->counter.lcd_count;
+			}
+			else
+			{
+				/* VBlank */
+				lcd_cycles =
+					LCD_LINE_CYCLES - gb->counter.lcd_count;
+			}
+
+			if(lcd_cycles < halt_cycles)
+				halt_cycles = lcd_cycles;
+		}
+
+		/* Some halt cycles may already be very high, so make sure we
+		 * don't underflow here. */
+		if(halt_cycles <= 0)
+			halt_cycles = 4;
+
+		inst_cycles = (uint_fast16_t)halt_cycles;
+		break;
+	}
+
+	case 0x77: /* LD (HL), A */
+		__gb_write(gb, gb->cpu_reg.hl.reg, gb->cpu_reg.a);
+		break;
+
+	case 0x78: /* LD A, B */
+		gb->cpu_reg.a = gb->cpu_reg.bc.bytes.b;
+		break;
+
+	case 0x79: /* LD A, C */
+		gb->cpu_reg.a = gb->cpu_reg.bc.bytes.c;
+		break;
+
+	case 0x7A: /* LD A, D */
+		gb->cpu_reg.a = gb->cpu_reg.de.bytes.d;
+		break;
+
+	case 0x7B: /* LD A, E */
+		gb->cpu_reg.a = gb->cpu_reg.de.bytes.e;
+		break;
+
+	case 0x7C: /* LD A, H */
+		gb->cpu_reg.a = gb->cpu_reg.hl.bytes.h;
+		break;
+
+	case 0x7D: /* LD A, L */
+		gb->cpu_reg.a = gb->cpu_reg.hl.bytes.l;
+		break;
+
+	case 0x7E: /* LD A, (HL) */
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.hl.reg);
+		break;
+
+	case 0x7F: /* LD A, A */
+		break;
+
+	case 0x80: /* ADD A, B */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.bc.bytes.b, 0);
+		break;
+
+	case 0x81: /* ADD A, C */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.bc.bytes.c, 0);
+		break;
+
+	case 0x82: /* ADD A, D */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.de.bytes.d, 0);
+		break;
+
+	case 0x83: /* ADD A, E */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.de.bytes.e, 0);
+		break;
+
+	case 0x84: /* ADD A, H */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.hl.bytes.h, 0);
+		break;
+
+	case 0x85: /* ADD A, L */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.hl.bytes.l, 0);
+		break;
+
+	case 0x86: /* ADD A, (HL) */
+		PGB_INSTR_ADC_R8(__gb_read(gb, gb->cpu_reg.hl.reg), 0);
+		break;
+
+	case 0x87: /* ADD A, A */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.a, 0);
+		break;
+
+	case 0x88: /* ADC A, B */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.bc.bytes.b, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x89: /* ADC A, C */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.bc.bytes.c, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8A: /* ADC A, D */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.de.bytes.d, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8B: /* ADC A, E */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.de.bytes.e, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8C: /* ADC A, H */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.hl.bytes.h, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8D: /* ADC A, L */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.hl.bytes.l, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8E: /* ADC A, (HL) */
+		PGB_INSTR_ADC_R8(__gb_read(gb, gb->cpu_reg.hl.reg), gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x8F: /* ADC A, A */
+		PGB_INSTR_ADC_R8(gb->cpu_reg.a, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x90: /* SUB B */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.bc.bytes.b, 0);
+		break;
+
+	case 0x91: /* SUB C */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.bc.bytes.c, 0);
+		break;
+
+	case 0x92: /* SUB D */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.de.bytes.d, 0);
+		break;
+
+	case 0x93: /* SUB E */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.de.bytes.e, 0);
+		break;
+
+	case 0x94: /* SUB H */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.hl.bytes.h, 0);
+		break;
+
+	case 0x95: /* SUB L */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.hl.bytes.l, 0);
+		break;
+
+	case 0x96: /* SUB (HL) */
+		PGB_INSTR_SBC_R8(__gb_read(gb, gb->cpu_reg.hl.reg), 0);
+		break;
+
+	case 0x97: /* SUB A */
+		gb->cpu_reg.a = 0;
+		gb->cpu_reg.f_bits.z = 1;
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = 0;
+		break;
+
+	case 0x98: /* SBC A, B */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.bc.bytes.b, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x99: /* SBC A, C */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.bc.bytes.c, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9A: /* SBC A, D */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.de.bytes.d, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9B: /* SBC A, E */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.de.bytes.e, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9C: /* SBC A, H */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.hl.bytes.h, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9D: /* SBC A, L */
+		PGB_INSTR_SBC_R8(gb->cpu_reg.hl.bytes.l, gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9E: /* SBC A, (HL) */
+		PGB_INSTR_SBC_R8(__gb_read(gb, gb->cpu_reg.hl.reg), gb->cpu_reg.f_bits.c);
+		break;
+
+	case 0x9F: /* SBC A, A */
+		gb->cpu_reg.a = gb->cpu_reg.f_bits.c ? 0xFF : 0x00;
+		gb->cpu_reg.f_bits.z = !gb->cpu_reg.f_bits.c;
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = gb->cpu_reg.f_bits.c;
+		break;
+
+	case 0xA0: /* AND B */
+		PGB_INSTR_AND_R8(gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0xA1: /* AND C */
+		PGB_INSTR_AND_R8(gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xA2: /* AND D */
+		PGB_INSTR_AND_R8(gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0xA3: /* AND E */
+		PGB_INSTR_AND_R8(gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0xA4: /* AND H */
+		PGB_INSTR_AND_R8(gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0xA5: /* AND L */
+		PGB_INSTR_AND_R8(gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0xA6: /* AND (HL) */
+		PGB_INSTR_AND_R8(__gb_read(gb, gb->cpu_reg.hl.reg));
+		break;
+
+	case 0xA7: /* AND A */
+		PGB_INSTR_AND_R8(gb->cpu_reg.a);
+		break;
+
+	case 0xA8: /* XOR B */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0xA9: /* XOR C */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xAA: /* XOR D */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0xAB: /* XOR E */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0xAC: /* XOR H */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0xAD: /* XOR L */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0xAE: /* XOR (HL) */
+		PGB_INSTR_XOR_R8(__gb_read(gb, gb->cpu_reg.hl.reg));
+		break;
+
+	case 0xAF: /* XOR A */
+		PGB_INSTR_XOR_R8(gb->cpu_reg.a);
+		break;
+
+	case 0xB0: /* OR B */
+		PGB_INSTR_OR_R8(gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0xB1: /* OR C */
+		PGB_INSTR_OR_R8(gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xB2: /* OR D */
+		PGB_INSTR_OR_R8(gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0xB3: /* OR E */
+		PGB_INSTR_OR_R8(gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0xB4: /* OR H */
+		PGB_INSTR_OR_R8(gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0xB5: /* OR L */
+		PGB_INSTR_OR_R8(gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0xB6: /* OR (HL) */
+		PGB_INSTR_OR_R8(__gb_read(gb, gb->cpu_reg.hl.reg));
+		break;
+
+	case 0xB7: /* OR A */
+		PGB_INSTR_OR_R8(gb->cpu_reg.a);
+		break;
+
+	case 0xB8: /* CP B */
+		PGB_INSTR_CP_R8(gb->cpu_reg.bc.bytes.b);
+		break;
+
+	case 0xB9: /* CP C */
+		PGB_INSTR_CP_R8(gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xBA: /* CP D */
+		PGB_INSTR_CP_R8(gb->cpu_reg.de.bytes.d);
+		break;
+
+	case 0xBB: /* CP E */
+		PGB_INSTR_CP_R8(gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0xBC: /* CP H */
+		PGB_INSTR_CP_R8(gb->cpu_reg.hl.bytes.h);
+		break;
+
+	case 0xBD: /* CP L */
+		PGB_INSTR_CP_R8(gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0xBE: /* CP (HL) */
+		PGB_INSTR_CP_R8(__gb_read(gb, gb->cpu_reg.hl.reg));
+		break;
+
+	case 0xBF: /* CP A */
+		gb->cpu_reg.f_bits.z = 1;
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h = 0;
+		gb->cpu_reg.f_bits.c = 0;
+		break;
+
+	case 0xC0: /* RET NZ */
+		if(!gb->cpu_reg.f_bits.z)
+		{
+			gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			inst_cycles += 12;
+		}
+
+		break;
+
+	case 0xC1: /* POP BC */
+		gb->cpu_reg.bc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.bc.bytes.b = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		break;
+
+	case 0xC2: /* JP NZ, imm */
+		if(!gb->cpu_reg.f_bits.z)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xC3: /* JP imm */
+	{
+		uint8_t p, c;
+		c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		p = __gb_read(gb, gb->cpu_reg.pc.reg);
+		gb->cpu_reg.pc.bytes.c = c;
+		gb->cpu_reg.pc.bytes.p = p;
+		break;
+	}
+
+	case 0xC4: /* CALL NZ imm */
+		if(!gb->cpu_reg.f_bits.z)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 12;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xC5: /* PUSH BC */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.bc.bytes.b);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xC6: /* ADD A, imm */
+	{
+		uint8_t val = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		PGB_INSTR_ADC_R8(val, 0);
+		break;
+	}
+
+	case 0xC7: /* RST 0x0000 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0000;
+		break;
+
+	case 0xC8: /* RET Z */
+		if(gb->cpu_reg.f_bits.z)
+		{
+			gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			inst_cycles += 12;
+		}
+		break;
+
+	case 0xC9: /* RET */
+	{
+		gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		break;
+	}
+
+	case 0xCA: /* JP Z, imm */
+		if(gb->cpu_reg.f_bits.z)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xCB: /* CB INST */
+		inst_cycles = __gb_execute_cb(gb);
+		break;
+
+	case 0xCC: /* CALL Z, imm */
+		if(gb->cpu_reg.f_bits.z)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 12;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xCD: /* CALL imm */
+	{
+		uint8_t p, c;
+		c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.bytes.c = c;
+		gb->cpu_reg.pc.bytes.p = p;
+	}
+	break;
+
+	case 0xCE: /* ADC A, imm */
+	{
+		uint8_t val = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		PGB_INSTR_ADC_R8(val, gb->cpu_reg.f_bits.c);
+		break;
+	}
+
+	case 0xCF: /* RST 0x0008 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0008;
+		break;
+
+	case 0xD0: /* RET NC */
+		if(!gb->cpu_reg.f_bits.c)
+		{
+			gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			inst_cycles += 12;
+		}
+
+		break;
+
+	case 0xD1: /* POP DE */
+		gb->cpu_reg.de.bytes.e = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.de.bytes.d = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		break;
+
+	case 0xD2: /* JP NC, imm */
+		if(!gb->cpu_reg.f_bits.c)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xD4: /* CALL NC, imm */
+		if(!gb->cpu_reg.f_bits.c)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 12;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xD5: /* PUSH DE */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.de.bytes.d);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.de.bytes.e);
+		break;
+
+	case 0xD6: /* SUB imm */
+	{
+		uint8_t val = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		uint16_t temp = gb->cpu_reg.a - val;
+		gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00);
+		gb->cpu_reg.f_bits.n = 1;
+		gb->cpu_reg.f_bits.h =
+			(gb->cpu_reg.a ^ val ^ temp) & 0x10 ? 1 : 0;
+		gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0;
+		gb->cpu_reg.a = (temp & 0xFF);
+		break;
+	}
+
+	case 0xD7: /* RST 0x0010 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0010;
+		break;
+
+	case 0xD8: /* RET C */
+		if(gb->cpu_reg.f_bits.c)
+		{
+			gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+			inst_cycles += 12;
+		}
+
+		break;
+
+	case 0xD9: /* RETI */
+	{
+		gb->cpu_reg.pc.bytes.c = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.pc.bytes.p = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->gb_ime = 1;
+	}
+	break;
+
+	case 0xDA: /* JP C, imm */
+		if(gb->cpu_reg.f_bits.c)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 4;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xDC: /* CALL C, imm */
+		if(gb->cpu_reg.f_bits.c)
+		{
+			uint8_t p, c;
+			c = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			p = __gb_read(gb, gb->cpu_reg.pc.reg++);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+			__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+			gb->cpu_reg.pc.bytes.c = c;
+			gb->cpu_reg.pc.bytes.p = p;
+			inst_cycles += 12;
+		}
+		else
+			gb->cpu_reg.pc.reg += 2;
+
+		break;
+
+	case 0xDE: /* SBC A, imm */
+	{
+		uint8_t val = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		PGB_INSTR_SBC_R8(val, gb->cpu_reg.f_bits.c);
+		break;
+	}
+
+	case 0xDF: /* RST 0x0018 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0018;
+		break;
+
+	case 0xE0: /* LD (0xFF00+imm), A */
+		__gb_write(gb, 0xFF00 | __gb_read(gb, gb->cpu_reg.pc.reg++),
+			   gb->cpu_reg.a);
+		break;
+
+	case 0xE1: /* POP HL */
+		gb->cpu_reg.hl.bytes.l = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.hl.bytes.h = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		break;
+
+	case 0xE2: /* LD (C), A */
+		__gb_write(gb, 0xFF00 | gb->cpu_reg.bc.bytes.c, gb->cpu_reg.a);
+		break;
+
+	case 0xE5: /* PUSH HL */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.hl.bytes.h);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.hl.bytes.l);
+		break;
+
+	case 0xE6: /* AND imm */
+		/* TODO: Optimisation? */
+		gb->cpu_reg.a = gb->cpu_reg.a & __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00);
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = 1;
+		gb->cpu_reg.f_bits.c = 0;
+		break;
+
+	case 0xE7: /* RST 0x0020 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0020;
+		break;
+
+	case 0xE8: /* ADD SP, imm */
+	{
+		int8_t offset = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.sp.reg & 0xF) + (offset & 0xF) > 0xF) ? 1 : 0;
+		gb->cpu_reg.f_bits.c = ((gb->cpu_reg.sp.reg & 0xFF) + (offset & 0xFF) > 0xFF);
+		gb->cpu_reg.sp.reg += offset;
+		break;
+	}
+
+	case 0xE9: /* JP (HL) */
+		gb->cpu_reg.pc.reg = gb->cpu_reg.hl.reg;
+		break;
+
+	case 0xEA: /* LD (imm), A */
+	{
+		uint8_t h, l;
+		uint16_t addr;
+		l = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		h = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		addr = PEANUT_GB_U8_TO_U16(h, l);
+		__gb_write(gb, addr, gb->cpu_reg.a);
+		break;
+	}
+
+	case 0xEE: /* XOR imm */
+		PGB_INSTR_XOR_R8(__gb_read(gb, gb->cpu_reg.pc.reg++));
+		break;
+
+	case 0xEF: /* RST 0x0028 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0028;
+		break;
+
+	case 0xF0: /* LD A, (0xFF00+imm) */
+		gb->cpu_reg.a =
+			__gb_read(gb, 0xFF00 | __gb_read(gb, gb->cpu_reg.pc.reg++));
+		break;
+
+	case 0xF1: /* POP AF */
+	{
+		uint8_t temp_8 = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		gb->cpu_reg.f_bits.z = (temp_8 >> 7) & 1;
+		gb->cpu_reg.f_bits.n = (temp_8 >> 6) & 1;
+		gb->cpu_reg.f_bits.h = (temp_8 >> 5) & 1;
+		gb->cpu_reg.f_bits.c = (temp_8 >> 4) & 1;
+		gb->cpu_reg.a = __gb_read(gb, gb->cpu_reg.sp.reg++);
+		break;
+	}
+
+	case 0xF2: /* LD A, (C) */
+		gb->cpu_reg.a = __gb_read(gb, 0xFF00 | gb->cpu_reg.bc.bytes.c);
+		break;
+
+	case 0xF3: /* DI */
+		gb->gb_ime = 0;
+		break;
+
+	case 0xF5: /* PUSH AF */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.a);
+		__gb_write(gb, --gb->cpu_reg.sp.reg,
+			   gb->cpu_reg.f_bits.z << 7 | gb->cpu_reg.f_bits.n << 6 |
+			   gb->cpu_reg.f_bits.h << 5 | gb->cpu_reg.f_bits.c << 4);
+		break;
+
+	case 0xF6: /* OR imm */
+		PGB_INSTR_OR_R8(__gb_read(gb, gb->cpu_reg.pc.reg++));
+		break;
+
+	case 0xF7: /* PUSH AF */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0030;
+		break;
+
+	case 0xF8: /* LD HL, SP+/-imm */
+	{
+		/* Taken from SameBoy, which is released under MIT Licence. */
+		int8_t offset = (int8_t) __gb_read(gb, gb->cpu_reg.pc.reg++);
+		gb->cpu_reg.hl.reg = gb->cpu_reg.sp.reg + offset;
+		gb->cpu_reg.f_bits.z = 0;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = ((gb->cpu_reg.sp.reg & 0xF) + (offset & 0xF) > 0xF) ? 1 : 0;
+		gb->cpu_reg.f_bits.c = ((gb->cpu_reg.sp.reg & 0xFF) + (offset & 0xFF) > 0xFF) ? 1 :
+				       0;
+		break;
+	}
+
+	case 0xF9: /* LD SP, HL */
+		gb->cpu_reg.sp.reg = gb->cpu_reg.hl.reg;
+		break;
+
+	case 0xFA: /* LD A, (imm) */
+	{
+		uint8_t h, l;
+		uint16_t addr;
+		l = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		h = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		addr = PEANUT_GB_U8_TO_U16(h, l);
+		gb->cpu_reg.a = __gb_read(gb, addr);
+		break;
+	}
+
+	case 0xFB: /* EI */
+		gb->gb_ime = 1;
+		break;
+
+	case 0xFE: /* CP imm */
+	{
+		uint8_t val = __gb_read(gb, gb->cpu_reg.pc.reg++);
+		PGB_INSTR_CP_R8(val);
+		break;
+	}
+
+	case 0xFF: /* RST 0x0038 */
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.p);
+		__gb_write(gb, --gb->cpu_reg.sp.reg, gb->cpu_reg.pc.bytes.c);
+		gb->cpu_reg.pc.reg = 0x0038;
+		break;
+
+	default:
+		/* Return address where invlid opcode that was read. */
+		(gb->gb_error)(gb, GB_INVALID_OPCODE, gb->cpu_reg.pc.reg - 1);
+		PGB_UNREACHABLE();
+	}
+
+	do
+	{
+		/* DIV register timing */
+		gb->counter.div_count += inst_cycles;
+		while(gb->counter.div_count >= DIV_CYCLES)
+		{
+			gb->hram_io[IO_DIV]++;
+			gb->counter.div_count -= DIV_CYCLES;
+		}
+
+		/* Check serial transmission. */
+		if(gb->hram_io[IO_SC] & SERIAL_SC_TX_START)
+		{
+			unsigned int serial_cycles = SERIAL_CYCLES_1KB;
+
+			/* If new transfer, call TX function. */
+			if(gb->counter.serial_count == 0 &&
+				gb->gb_serial_tx != NULL)
+				(gb->gb_serial_tx)(gb, gb->hram_io[IO_SB]);
+
+#if PEANUT_FULL_GBC_SUPPORT
+			if(gb->hram_io[IO_SC] & 0x3)
+				serial_cycles = SERIAL_CYCLES_32KB;
+#endif
+
+			gb->counter.serial_count += inst_cycles;
+
+			/* If it's time to receive byte, call RX function. */
+			if(gb->counter.serial_count >= serial_cycles)
+			{
+				/* If RX can be done, do it. */
+				/* If RX failed, do not change SB if using external
+				 * clock, or set to 0xFF if using internal clock. */
+				uint8_t rx;
+
+				if(gb->gb_serial_rx != NULL &&
+					(gb->gb_serial_rx(gb, &rx) ==
+						GB_SERIAL_RX_SUCCESS))
+				{
+					gb->hram_io[IO_SB] = rx;
+
+					/* Inform game of serial TX/RX completion. */
+					gb->hram_io[IO_SC] &= 0x01;
+					gb->hram_io[IO_IF] |= SERIAL_INTR;
+				}
+				else if(gb->hram_io[IO_SC] & SERIAL_SC_CLOCK_SRC)
+				{
+					/* If using internal clock, and console is not
+					 * attached to any external peripheral, shifted
+					 * bits are replaced with logic 1. */
+					gb->hram_io[IO_SB] = 0xFF;
+
+					/* Inform game of serial TX/RX completion. */
+					gb->hram_io[IO_SC] &= 0x01;
+					gb->hram_io[IO_IF] |= SERIAL_INTR;
+				}
+				else
+				{
+					/* If using external clock, and console is not
+					 * attached to any external peripheral, bits are
+					 * not shifted, so SB is not modified. */
+				}
+
+				gb->counter.serial_count = 0;
+			}
+		}
+
+		/* TIMA register timing */
+		/* TODO: Change tac_enable to struct of TAC timer control bits. */
+		if(gb->hram_io[IO_TAC] & IO_TAC_ENABLE_MASK)
+		{
+			gb->counter.tima_count += inst_cycles;
+
+			while(gb->counter.tima_count >=
+				TAC_CYCLES[gb->hram_io[IO_TAC] & IO_TAC_RATE_MASK])
+			{
+				gb->counter.tima_count -=
+					TAC_CYCLES[gb->hram_io[IO_TAC] & IO_TAC_RATE_MASK];
+
+				if(++gb->hram_io[IO_TIMA] == 0)
+				{
+					gb->hram_io[IO_IF] |= TIMER_INTR;
+					/* On overflow, set TMA to TIMA. */
+					gb->hram_io[IO_TIMA] = gb->hram_io[IO_TMA];
+				}
+			}
+		}
+
+		/* If LCD is off, don't update LCD state or increase the LCD
+		 * ticks. */
+		if(!(gb->hram_io[IO_LCDC] & LCDC_ENABLE))
+			continue;
+
+		/* LCD Timing */
+#if PEANUT_FULL_GBC_SUPPORT
+        if (inst_cycles > 1)
+            gb->counter.lcd_count += (inst_cycles >> gb->cgb.doubleSpeed);
+        else
+#endif
+		gb->counter.lcd_count += inst_cycles;
+
+		/* New Scanline */
+		if(gb->counter.lcd_count >= LCD_LINE_CYCLES)
+		{
+			gb->counter.lcd_count -= LCD_LINE_CYCLES;
+
+			/* Next line */
+			gb->hram_io[IO_LY] = (gb->hram_io[IO_LY] + 1) % LCD_VERT_LINES;
+
+			/* LYC Update */
+			if(gb->hram_io[IO_LY] == gb->hram_io[IO_LYC])
+			{
+				gb->hram_io[IO_STAT] |= STAT_LYC_COINC;
+
+				if(gb->hram_io[IO_STAT] & STAT_LYC_INTR)
+					gb->hram_io[IO_IF] |= LCDC_INTR;
+			}
+			else
+				gb->hram_io[IO_STAT] &= 0xFB;
+
+			/* VBLANK Start */
+			if(gb->hram_io[IO_LY] == LCD_HEIGHT)
+			{
+				gb->hram_io[IO_STAT] =
+					(gb->hram_io[IO_STAT] & ~STAT_MODE) | IO_STAT_MODE_VBLANK;
+				gb->gb_frame = 1;
+				gb->hram_io[IO_IF] |= VBLANK_INTR;
+				gb->lcd_blank = 0;
+
+				if(gb->hram_io[IO_STAT] & STAT_MODE_1_INTR)
+					gb->hram_io[IO_IF] |= LCDC_INTR;
+
+#if ENABLE_LCD
+				/* If frame skip is activated, check if we need to draw
+				 * the frame or skip it. */
+				if(gb->direct.frame_skip)
+				{
+					gb->display.frame_skip_count =
+						!gb->display.frame_skip_count;
+				}
+
+				/* If interlaced is activated, change which lines get
+				 * updated. Also, only update lines on frames that are
+				 * actually drawn when frame skip is enabled. */
+				if(gb->direct.interlace &&
+						(!gb->direct.frame_skip ||
+						 gb->display.frame_skip_count))
+				{
+					gb->display.interlace_count =
+						!gb->display.interlace_count;
+				}
+#endif
+			}
+			/* Normal Line */
+			else if(gb->hram_io[IO_LY] < LCD_HEIGHT)
+			{
+				if(gb->hram_io[IO_LY] == 0)
+				{
+					/* Clear Screen */
+					gb->display.WY = gb->hram_io[IO_WY];
+					gb->display.window_clear = 0;
+				}
+
+				gb->hram_io[IO_STAT] =
+					(gb->hram_io[IO_STAT] & ~STAT_MODE) | IO_STAT_MODE_HBLANK;
+
+#if PEANUT_FULL_GBC_SUPPORT
+				//DMA GBC
+				if(gb->cgb.cgbMode && !gb->cgb.dmaActive && gb->cgb.dmaMode)
+				{
+					for (uint8_t i = 0; i < 0x10; i++)
+					{
+						__gb_write(gb, ((gb->cgb.dmaDest & 0x1FF0) | 0x8000) + i,
+								   __gb_read(gb, (gb->cgb.dmaSource & 0xFFF0) + i));
+					}
+					gb->cgb.dmaSource += 0x10;
+					gb->cgb.dmaDest += 0x10;
+					if(!(--gb->cgb.dmaSize)) gb->cgb.dmaActive = 1;
+				}
+#endif
+				if(gb->hram_io[IO_STAT] & STAT_MODE_0_INTR)
+					gb->hram_io[IO_IF] |= LCDC_INTR;
+
+				/* If halted immediately jump to next LCD mode. */
+				if(gb->counter.lcd_count < LCD_MODE_2_CYCLES)
+					inst_cycles = LCD_MODE_2_CYCLES - gb->counter.lcd_count;
+			}
+		}
+		/* OAM access */
+		else if((gb->hram_io[IO_STAT] & STAT_MODE) == IO_STAT_MODE_HBLANK &&
+				gb->counter.lcd_count >= LCD_MODE_2_CYCLES)
+		{
+			gb->hram_io[IO_STAT] =
+				(gb->hram_io[IO_STAT] & ~STAT_MODE) | IO_STAT_MODE_SEARCH_OAM;
+
+			if(gb->hram_io[IO_STAT] & STAT_MODE_2_INTR)
+				gb->hram_io[IO_IF] |= LCDC_INTR;
+
+			/* If halted immediately jump to next LCD mode. */
+			if (gb->counter.lcd_count < LCD_MODE_3_CYCLES)
+				inst_cycles = LCD_MODE_3_CYCLES - gb->counter.lcd_count;
+		}
+		/* Update LCD */
+		else if((gb->hram_io[IO_STAT] & STAT_MODE) == IO_STAT_MODE_SEARCH_OAM &&
+				gb->counter.lcd_count >= LCD_MODE_3_CYCLES)
+		{
+			gb->hram_io[IO_STAT] =
+				(gb->hram_io[IO_STAT] & ~STAT_MODE) | IO_STAT_MODE_SEARCH_TRANSFER;
+#if ENABLE_LCD
+			if(!gb->lcd_blank)
+				__gb_draw_line(gb);
+#endif
+			/* If halted immediately jump to next LCD mode. */
+			if (gb->counter.lcd_count < LCD_MODE_0_CYCLES)
+				inst_cycles = LCD_MODE_0_CYCLES - gb->counter.lcd_count;
+		}
+	} while(gb->gb_halt && (gb->hram_io[IO_IF] & gb->hram_io[IO_IE]) == 0);
+	/* If halted, loop until an interrupt occurs. */
+}
+
+void gb_run_frame(struct gb_s *gb)
+{
+	gb->gb_frame = 0;
+
+	while(!gb->gb_frame)
+		__gb_step_cpu(gb);
+}
+
+/**
+ * Gets the size of the save file required for the ROM.
+ */
+uint_fast32_t gb_get_save_size(struct gb_s *gb)
+{
+	const uint_fast16_t ram_size_location = 0x0149;
+	const uint_fast32_t ram_sizes[] =
+	{
+		0x00, 0x800, 0x2000, 0x8000, 0x20000
+	};
+	uint8_t ram_size = gb->gb_rom_read(gb, ram_size_location);
+
+	/* MBC2 always has 512 half-bytes of cart RAM. */
+	if(gb->mbc == 2)
+		return 0x200;
+
+	return ram_sizes[ram_size];
+}
+
+void gb_init_serial(struct gb_s *gb,
+		    void (*gb_serial_tx)(struct gb_s*, const uint8_t),
+		    enum gb_serial_rx_ret_e (*gb_serial_rx)(struct gb_s*,
+			    uint8_t*))
+{
+	gb->gb_serial_tx = gb_serial_tx;
+	gb->gb_serial_rx = gb_serial_rx;
+}
+
+uint8_t gb_colour_hash(struct gb_s *gb)
+{
+#define ROM_TITLE_START_ADDR	0x0134
+#define ROM_TITLE_END_ADDR	0x0143
+
+	uint8_t x = 0;
+	uint16_t i;
+
+	for(i = ROM_TITLE_START_ADDR; i <= ROM_TITLE_END_ADDR; i++)
+		x += gb->gb_rom_read(gb, i);
+
+	return x;
+}
+
+/**
+ * Resets the context, and initialises startup values for a DMG console.
+ */
+void gb_reset(struct gb_s *gb)
+{
+	gb->gb_halt = 0;
+	gb->gb_ime = 1;
+
+	/* Initialise MBC values. */
+	gb->selected_rom_bank = 1;
+	gb->cart_ram_bank = 0;
+	gb->enable_cart_ram = 0;
+	gb->cart_mode_select = 0;
+
+	/* Use values as though the boot ROM was already executed. */
+	if(gb->gb_bootrom_read == NULL)
+	{
+		uint8_t hdr_chk;
+		hdr_chk = gb->gb_rom_read(gb, ROM_HEADER_CHECKSUM_LOC) != 0;
+
+		gb->cpu_reg.a = 0x01;
+		gb->cpu_reg.f_bits.z = 1;
+		gb->cpu_reg.f_bits.n = 0;
+		gb->cpu_reg.f_bits.h = hdr_chk;
+		gb->cpu_reg.f_bits.c = hdr_chk;
+		gb->cpu_reg.bc.reg = 0x0013;
+		gb->cpu_reg.de.reg = 0x00D8;
+		gb->cpu_reg.hl.reg = 0x014D;
+		gb->cpu_reg.sp.reg = 0xFFFE;
+		gb->cpu_reg.pc.reg = 0x0100;
+
+		gb->hram_io[IO_DIV ] = 0xAB;
+		gb->hram_io[IO_LCDC] = 0x91;
+		gb->hram_io[IO_STAT] = 0x85;
+		gb->hram_io[IO_BANK] = 0x01;
+#if PEANUT_FULL_GBC_SUPPORT
+		if(gb->cgb.cgbMode)
+		{
+			gb->cpu_reg.a = 0x11;
+			gb->cpu_reg.f_bits.z = 1;
+			gb->cpu_reg.f_bits.n = 0;
+			gb->cpu_reg.f_bits.h = hdr_chk;
+			gb->cpu_reg.f_bits.c = hdr_chk;
+			gb->cpu_reg.bc.reg = 0x0000;
+			gb->cpu_reg.de.reg = 0x0008;
+			gb->cpu_reg.hl.reg = 0x007C;
+			gb->hram_io[IO_DIV] = 0xFF;
+		}
+#endif
+
+		memset(gb->vram, 0x00, VRAM_SIZE);
+	}
+	else
+	{
+		/* Set value as though the console was just switched on.
+		 * CPU registers are uninitialised. */
+		gb->cpu_reg.pc.reg = 0x0000;
+		gb->hram_io[IO_DIV ] = 0x00;
+		gb->hram_io[IO_LCDC] = 0x00;
+		gb->hram_io[IO_STAT] = 0x84;
+		gb->hram_io[IO_BANK] = 0x00;
+	}
+
+	gb->counter.lcd_count = 0;
+	gb->counter.div_count = 0;
+	gb->counter.tima_count = 0;
+	gb->counter.serial_count = 0;
+
+	gb->direct.joypad = 0xFF;
+	gb->hram_io[IO_JOYP] = 0xCF;
+	gb->hram_io[IO_SB  ] = 0x00;
+	gb->hram_io[IO_SC  ] = 0x7E;
+#if PEANUT_FULL_GBC_SUPPORT
+	if(gb->cgb.cgbMode) gb->hram_io[IO_SC] = 0x7F;
+#endif
+	/* DIV */
+	gb->hram_io[IO_TIMA] = 0x00;
+	gb->hram_io[IO_TMA ] = 0x00;
+	gb->hram_io[IO_TAC ] = 0xF8;
+	gb->hram_io[IO_IF  ] = 0xE1;
+
+	/* LCDC */
+	/* STAT */
+	gb->hram_io[IO_SCY ] = 0x00;
+	gb->hram_io[IO_SCX ] = 0x00;
+	gb->hram_io[IO_LY  ] = 0x00;
+	gb->hram_io[IO_LYC ] = 0x00;
+	__gb_write(gb, 0xFF47, 0xFC); // BGP
+	__gb_write(gb, 0xFF48, 0xFF); // OBJP0
+	__gb_write(gb, 0xFF49, 0xFF); // OBJP1
+	gb->hram_io[IO_WY] = 0x00;
+	gb->hram_io[IO_WX] = 0x00;
+	gb->hram_io[IO_IE] = 0x00;
+	gb->hram_io[IO_IF] = 0xE1;
+#if PEANUT_FULL_GBC_SUPPORT
+	/* Initialize some CGB registers */
+	gb->cgb.doubleSpeed = 0;
+	gb->cgb.doubleSpeedPrep = 0;
+	gb->cgb.wramBank = 1;
+	gb->cgb.wramBankOffset = WRAM_0_ADDR;
+	gb->cgb.vramBank = 0;
+	gb->cgb.vramBankOffset = VRAM_ADDR;
+	for (int i = 0; i < 0x20; i++)
+	{
+		gb->cgb.OAMPalette[(i << 1)] = gb->cgb.BGPalette[(i << 1)] = 0x7F;
+		gb->cgb.OAMPalette[(i << 1) + 1] = gb->cgb.BGPalette[(i << 1) + 1] = 0xFF;
+	}
+	gb->cgb.OAMPaletteID = 0;
+	gb->cgb.BGPaletteID = 0;
+	gb->cgb.OAMPaletteInc = 0;
+	gb->cgb.BGPaletteInc = 0;
+	gb->cgb.dmaActive = 1;  // Not active
+	gb->cgb.dmaMode = 0;
+	gb->cgb.dmaSize = 0;
+	gb->cgb.dmaSource = 0;
+	gb->cgb.dmaDest = 0;
+#endif
+}
+
+enum gb_init_error_e gb_init(struct gb_s *gb,
+			     uint8_t (*gb_rom_read)(struct gb_s*, const uint_fast32_t),
+			     uint8_t (*gb_cart_ram_read)(struct gb_s*, const uint_fast32_t),
+			     void (*gb_cart_ram_write)(struct gb_s*, const uint_fast32_t, const uint8_t),
+			     void (*gb_error)(struct gb_s*, const enum gb_error_e, const uint16_t),
+			     void *priv)
+{
+#if PEANUT_FULL_GBC_SUPPORT
+	const uint16_t cgb_flag = 0x0143;
+#endif
+	const uint16_t mbc_location = 0x0147;
+	const uint16_t bank_count_location = 0x0148;
+	const uint16_t ram_size_location = 0x0149;
+	/**
+	 * Table for cartridge type (MBC). -1 if invalid.
+	 * TODO: MMM01 is untested.
+	 * TODO: MBC6 is untested.
+	 * TODO: MBC7 is unsupported.
+	 * TODO: POCKET CAMERA is unsupported.
+	 * TODO: BANDAI TAMA5 is unsupported.
+	 * TODO: HuC3 is unsupported.
+	 * TODO: HuC1 is unsupported.
+	 **/
+	const int8_t cart_mbc[] =
+	{
+		0, 1, 1, 1, -1, 2, 2, -1, 0, 0, -1, 0, 0, 0, -1, 3,
+		3, 3, 3, 3, -1, -1, -1, -1, -1, 5, 5, 5, 5, 5, 5, -1
+	};
+	const uint8_t cart_ram[] =
+	{
+		0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
+		1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0
+	};
+	const uint16_t num_rom_banks_mask[] =
+	{
+		2, 4, 8, 16, 32, 64, 128, 256, 512
+	};
+	const uint8_t num_ram_banks[] = { 0, 1, 1, 4, 16, 8 };
+
+	gb->gb_rom_read = gb_rom_read;
+	gb->gb_cart_ram_read = gb_cart_ram_read;
+	gb->gb_cart_ram_write = gb_cart_ram_write;
+	gb->gb_error = gb_error;
+	gb->direct.priv = priv;
+
+	/* Initialise serial transfer function to NULL. If the front-end does
+	 * not provide serial support, Peanut-GB will emulate no cable connected
+	 * automatically. */
+	gb->gb_serial_tx = NULL;
+	gb->gb_serial_rx = NULL;
+
+	gb->gb_bootrom_read = NULL;
+
+	/* Check valid ROM using checksum value. */
+	{
+		uint8_t x = 0;
+		uint16_t i;
+
+		for(i = 0x0134; i <= 0x014C; i++)
+			x = x - gb->gb_rom_read(gb, i) - 1;
+
+		if(x != gb->gb_rom_read(gb, ROM_HEADER_CHECKSUM_LOC))
+			return GB_INIT_INVALID_CHECKSUM;
+	}
+
+	/* Check if cartridge type is supported, and set MBC type. */
+	{
+#if PEANUT_FULL_GBC_SUPPORT
+		gb->cgb.cgbMode = (gb->gb_rom_read(gb, cgb_flag) & 0x80) >> 7;
+#endif
+		const uint8_t mbc_value = gb->gb_rom_read(gb, mbc_location);
+
+		if(mbc_value > sizeof(cart_mbc) - 1 ||
+				(gb->mbc = cart_mbc[mbc_value]) == -1)
+			return GB_INIT_CARTRIDGE_UNSUPPORTED;
+	}
+
+	gb->cart_ram = cart_ram[gb->gb_rom_read(gb, mbc_location)];
+	gb->num_rom_banks_mask = num_rom_banks_mask[gb->gb_rom_read(gb, bank_count_location)] - 1;
+	gb->num_ram_banks = num_ram_banks[gb->gb_rom_read(gb, ram_size_location)];
+
+	/* Note that MBC2 will appear to have no RAM banks, but it actually
+	 * always has 512 half-bytes of RAM. Hence, gb->num_ram_banks must be
+	 * ignored for MBC2. */
+
+	gb->lcd_blank = 0;
+	gb->display.lcd_draw_line = NULL;
+
+	gb_reset(gb);
+
+	return GB_INIT_NO_ERROR;
+}
+
+const char* gb_get_rom_name(struct gb_s* gb, char *title_str)
+{
+	uint_fast16_t title_loc = 0x134;
+	/* End of title may be 0x13E for newer games. */
+	//const uint_fast16_t title_end = 0x14в;
+	const char* title_start = title_str;
+
+	for(; title_loc <= title_loc+ 24; title_loc++)
+	{
+		const char title_char = gb->gb_rom_read(gb, title_loc);
+        if (title_char == '\0') break;
+
+		if((title_char >= '0' && title_char <= '9') || (title_char >= 'A' && title_char <= 'Z'))
+		{
+                *title_str = title_char;
+
+		} else {
+            *title_str = '_';
+        }
+        title_str++;
+	}
+
+	*title_str = '\0';
+	return title_start;
+}
+
+#if ENABLE_LCD
+void gb_init_lcd(struct gb_s *gb,
+		void (*lcd_draw_line)(struct gb_s *gb,
+			const uint8_t *pixels,
+			const uint_fast8_t line))
+{
+	gb->display.lcd_draw_line = lcd_draw_line;
+
+	gb->direct.interlace = 0;
+	gb->display.interlace_count = 0;
+	gb->direct.frame_skip = 0;
+	gb->display.frame_skip_count = 0;
+
+	gb->display.window_clear = 0;
+	gb->display.WY = 0;
+
+	return;
+}
+#endif
+
+void gb_set_bootrom(struct gb_s *gb,
+		 uint8_t (*gb_bootrom_read)(struct gb_s*, const uint_fast16_t))
+{
+	gb->gb_bootrom_read = gb_bootrom_read;
+}
+
+/**
+ * This was taken from SameBoy, which is released under MIT Licence.
+ */
+void gb_tick_rtc(struct gb_s *gb)
+{
+	/* is timer running? */
+	if((gb->cart_rtc[4] & 0x40) == 0)
+	{
+		if(++gb->rtc_bits.sec == 60)
+		{
+			gb->rtc_bits.sec = 0;
+
+			if(++gb->rtc_bits.min == 60)
+			{
+				gb->rtc_bits.min = 0;
+
+				if(++gb->rtc_bits.hour == 24)
+				{
+					gb->rtc_bits.hour = 0;
+
+					if(++gb->rtc_bits.yday == 0)
+					{
+						if(gb->rtc_bits.high & 1)  /* Bit 8 of days*/
+						{
+							gb->rtc_bits.high |= 0x80; /* Overflow bit */
+						}
+
+						gb->rtc_bits.high ^= 1;
+					}
+				}
+			}
+		}
+	}
+}
+
+void gb_set_rtc(struct gb_s *gb, const struct tm * const time)
+{
+	gb->cart_rtc[0] = time->tm_sec;
+	gb->cart_rtc[1] = time->tm_min;
+	gb->cart_rtc[2] = time->tm_hour;
+	gb->cart_rtc[3] = time->tm_yday & 0xFF; /* Low 8 bits of day counter. */
+	gb->cart_rtc[4] = time->tm_yday >> 8; /* High 1 bit of day counter. */
+}
+#endif // PEANUT_GB_HEADER_ONLY
+
+/** Function prototypes: Required functions **/
+/**
+ * Initialises the emulator context to a known state. Call this before calling
+ * any other peanut-gb function.
+ * To reset the emulator, you can call gb_reset() instead.
+ *
+ * \param gb	Allocated emulator context. Must not be NULL.
+ * \param gb_rom_read Pointer to function that reads ROM data. ROM banking is
+ * 		already handled by Peanut-GB. Must not be NULL.
+ * \param gb_cart_ram_read Pointer to function that reads Cart RAM. Must not be
+ * 		NULL.
+ * \param gb_cart_ram_write Pointer to function to writes to Cart RAM. Must not
+ * 		be NULL.
+ * \param gb_error Pointer to function that is called when an unrecoverable
+ *		error occurs. Must not be NULL. Returning from this
+ *		function is undefined and will result in SIGABRT.
+ * \param priv	Private data that is stored within the emulator context. Set to
+ * 		NULL if unused.
+ * \returns	0 on success or an enum that describes the error.
+ */
+enum gb_init_error_e gb_init(struct gb_s *gb,
+			     uint8_t (*gb_rom_read)(struct gb_s*, const uint_fast32_t),
+			     uint8_t (*gb_cart_ram_read)(struct gb_s*, const uint_fast32_t),
+			     void (*gb_cart_ram_write)(struct gb_s*, const uint_fast32_t, const uint8_t),
+			     void (*gb_error)(struct gb_s*, const enum gb_error_e, const uint16_t),
+			     void *priv);
+
+/**
+ * Executes the emulator and runs for one frame.
+ *
+ * \param	An initialised emulator context. Must not be NULL.
+ */
+void gb_run_frame(struct gb_s *gb);
+
+/**
+ * Internal function used to step the CPU. Used mainly for testing.
+ * Use gb_run_frame() instead.
+ *
+ * \param	An initialised emulator context. Must not be NULL.
+ */
+void __gb_step_cpu(struct gb_s *gb);
+
+/** Function prototypes: Optional Functions **/
+/**
+ * Reset the emulator, like turning the Game Boy off and on again.
+ * This function can be called at any time.
+ *
+ * \param	An initialised emulator context. Must not be NULL.
+ */
+void gb_reset(struct gb_s *gb);
+
+/**
+ * Initialises the display context of the emulator. Only available when
+ * ENABLE_LCD is defined to a non-zero value.
+ * The pixel data sent to lcd_draw_line comes with both shade and layer data.
+ * The first two least significant bits are the shade data (black, dark, light,
+ * white). Bits 4 and 5 are layer data (OBJ0, OBJ1, BG), which can be used to
+ * add more colours to the game in the same way that the Game Boy Color does to
+ * older Game Boy games.
+ * This function can be called at any time.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \param lcd_draw_line Pointer to function that draws the 2-bit pixel data on the line
+ *		"line". Must not be NULL.
+ */
+#if ENABLE_LCD
+void gb_init_lcd(struct gb_s *gb,
+		void (*lcd_draw_line)(struct gb_s *gb,
+			const uint8_t *pixels,
+			const uint_fast8_t line));
+#endif
+
+/**
+ * Initialises the serial connection of the emulator. This function is optional,
+ * and if not called, the emulator will assume that no link cable is connected
+ * to the game.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \param gb_serial_tx Pointer to function that transmits a byte of data over
+ *		the serial connection. Must not be NULL.
+ * \param gb_serial_rx Pointer to function that receives a byte of data over the
+ *		serial connection. If no byte is received,
+ *		return GB_SERIAL_RX_NO_CONNECTION. Must not be NULL.
+ */
+void gb_init_serial(struct gb_s *gb,
+		    void (*gb_serial_tx)(struct gb_s*, const uint8_t),
+		    enum gb_serial_rx_ret_e (*gb_serial_rx)(struct gb_s*,
+			    uint8_t*));
+
+/**
+ * Obtains the save size of the game (size of the Cart RAM). Required by the
+ * frontend to allocate enough memory for the Cart RAM.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \returns	Size of the Cart RAM in bytes. 0 if Cartridge has not battery
+ *		backed RAM.
+ */
+uint_fast32_t gb_get_save_size(struct gb_s *gb);
+
+/**
+ * Calculates and returns a hash of the game header in the same way the Game
+ * Boy Color does for colourising old Game Boy games. The frontend can use this
+ * hash to automatically set a colour palette.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \returns	Hash of the game header.
+ */
+uint8_t gb_colour_hash(struct gb_s *gb);
+
+/**
+ * Returns the title of ROM.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \param title_str Allocated string at least 16 characters.
+ * \returns	Pointer to start of string, null terminated.
+ */
+const char* gb_get_rom_name(struct gb_s* gb, char *title_str);
+
+/**
+ * Tick the internal RTC by one second. This does not affect games with no RTC
+ * support.
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ */
+void gb_tick_rtc(struct gb_s *gb);
+
+/**
+ * Set initial values in RTC.
+ * Should be called after gb_init().
+ *
+ * \param gb	An initialised emulator context. Must not be NULL.
+ * \param time	Time structure with date and time.
+ */
+void gb_set_rtc(struct gb_s *gb, const struct tm * const time);
+
+/**
+ * Use boot ROM on reset. gb_reset() must be called for this to take affect.
+ * \param gb 	An initialised emulator context. Must not be NULL.
+ * \param gb_bootrom_read Function pointer to read boot ROM binary.
+ */
+void gb_set_bootrom(struct gb_s *gb,
+	uint8_t (*gb_bootrom_read)(struct gb_s*, const uint_fast16_t));
+
+/* Undefine CPU Flag helper functions. */
+#undef PEANUT_GB_CPUFLAG_MASK_CARRY
+#undef PEANUT_GB_CPUFLAG_MASK_HALFC
+#undef PEANUT_GB_CPUFLAG_MASK_ARITH
+#undef PEANUT_GB_CPUFLAG_MASK_ZERO
+#undef PEANUT_GB_CPUFLAG_BIT_CARRY
+#undef PEANUT_GB_CPUFLAG_BIT_HALFC
+#undef PEANUT_GB_CPUFLAG_BIT_ARITH
+#undef PEANUT_GB_CPUFLAG_BIT_ZERO
+#undef PGB_SET_CARRY
+#undef PGB_SET_HALFC
+#undef PGB_SET_ARITH
+#undef PGB_SET_ZERO
+#undef PGB_GET_CARRY
+#undef PGB_GET_HALFC
+#undef PGB_GET_ARITH
+#undef PGB_GET_ZERO
+#endif //PEANUT_GB_H
diff --git a/MCUME_pico2/picogb/picogb.cpp b/MCUME_pico2/picogb/picogb.cpp
new file mode 100644
index 0000000..acc8ab0
--- /dev/null
+++ b/MCUME_pico2/picogb/picogb.cpp
@@ -0,0 +1,188 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+     emu_init();
+ 
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+*/
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picogb/program_config.h b/MCUME_pico2/picogb/program_config.h
new file mode 100644
index 0000000..ae30c2e
--- /dev/null
+++ b/MCUME_pico2/picogb/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define FLASH_STORE_START 0x100000  
+
+#endif
diff --git a/MCUME_pico2/picogen/.DS_Store b/MCUME_pico2/picogen/.DS_Store
new file mode 100644
index 0000000..1de0b98
Binary files /dev/null and b/MCUME_pico2/picogen/.DS_Store differ
diff --git a/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.c b/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.c
new file mode 100755
index 0000000..9922272
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.c
@@ -0,0 +1,649 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <ctype.h>
+
+#include "../cpus/M68K/m68k.h"
+
+#include "../sound/z80inst.h"
+#include "gwenesis_bus.h"
+
+#include <gwenesis/sound/gwenesis_sn76489.h>
+#include <gwenesis/sound/ym2612.h>
+
+#include "../io/gwenesis_io.h"
+#include "../vdp/gwenesis_vdp.h"
+#include "../savestate/gwenesis_savestate.h"
+
+#pragma GCC optimize("Ofast")
+
+#define BUS_DISABLE_LOGGING 1
+
+uint8_t GWENESIS_AUDIO_SAMPLING_DIVISOR = 6;
+
+#if !BUS_DISABLE_LOGGING
+#include <stdarg.h>
+void bus_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%04x hc:%04x hv:%04x ", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter(),gwenesis_vdp_hvcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define bus_log(...)
+#endif
+
+// Setup M68k memories ROM & RAM
+//#include "rom_manager.h"
+const unsigned char* ROM_DATA; // 68K Main Program (uncompressed)
+// const unsigned char* ROM_METADATA; // 68K Main Program (uncompressed)
+//unsigned char* M68K_RAM=(void *)(uint32_t)(0); // 68K RAM
+//unsigned char* M68K_RAM = NULL; // 68K RAM
+unsigned char M68K_RAM[MAX_RAM_SIZE]; // 68K RAM
+
+// Setup Z80 Memory
+//unsigned char* ZRAM = NULL; // Z80 RAM
+unsigned char ZRAM[MAX_Z80_RAM_SIZE]; // Z80 RAM
+unsigned char TMSS[0x4];
+extern unsigned short gwenesis_vdp_status;
+
+extern int audio_enabled;
+
+// TMSS
+int tmss_state = 0;
+int tmss_count = 0;
+
+/******************************************************************************
+ *
+ *   Load a Sega Genesis Cartridge into CPU Memory
+ *
+ ******************************************************************************/
+
+void load_cartridge(uintptr_t rom) {
+    ROM_DATA = (const unsigned char *)rom;
+    // Clear all volatile memory
+    memset(M68K_RAM, 0, MAX_RAM_SIZE);
+    memset(ZRAM, 0, MAX_Z80_RAM_SIZE);
+
+    // Set Z80 Memory as Z80_RAM
+    z80_set_memory(ZRAM);
+
+    z80_pulse_reset();
+
+
+    set_region();
+}
+
+/******************************************************************************
+ *
+ *   Power ON the CPU
+ *   Initialize 68K, Z80 and YM2612 Cores
+ *
+ ******************************************************************************/
+void power_on() {
+    // Set M68K CPU as original MOTOROLA 68000
+    //m68k_set_cpu_type(M68K_CPU_TYPE_68000);
+    // Initialize M68K CPU
+    m68k_init();
+    // Initialize Z80 CPU
+    z80_start();
+
+    // Initialize YM2612 chip
+    YM2612Init();
+    YM2612Config(9);
+    // Initialize PSG SN76489 chip
+    //CLOCK_NTSC      = 3579545,
+    //CLOCK_PAL       = 3546895,
+    // CLOCK_NTSC_SMS1 = 3579527
+
+    //  if (mode_pal) {
+    //     gwenesis_SN76489_Init(3546895, GWENESIS_AUDIO_BUFFER_LENGTH_PAL*50,AUDIO_FREQ_DIVISOR);
+    //   } else{
+    //     gwenesis_SN76489_Init(3579545, GWENESIS_AUDIO_BUFFER_LENGTH_NTSC*60,AUDIO_FREQ_DIVISOR);
+    //   }
+
+    gwenesis_SN76489_Init(3579545, GWENESIS_AUDIO_BUFFER_LENGTH_NTSC * 60,AUDIO_FREQ_DIVISOR);
+}
+
+/******************************************************************************
+ *
+ *   Reset the CPU Emulation
+ *   Send a pulse reset to 68K, Z80 and YM2612 Cores
+ *
+ ******************************************************************************/
+void reset_emulation() {
+    // Send a reset pulse to Z80 CPU
+    z80_pulse_reset();
+    // Send a reset pulse to Z80 M68K
+    m68k_pulse_reset();
+    // Send a reset pulse to YM2612 chip
+    YM2612ResetChip();
+
+    // Send a reset pulse to SEGA 315-5313 chip
+    gwenesis_vdp_reset();
+    gwenesis_SN76489_Reset();
+}
+
+/******************************************************************************
+ *
+ *   Set Region
+ *   Look at ROM to set console compatible region
+ *
+ ******************************************************************************/
+void set_region() {
+    /*
+      old style : JUE characters
+      J : Domestic 60Hz (Asia)
+      U : Oversea  60Hz (USA)
+      E : Oversea  50Hz (Europe)
+
+      new style : 1st character
+      bit 0 : +1 Domestic 60Hz (Asia)
+      bit 1 : +2 Domestc  50Hz (Asia)
+      bit 2:  +4 Oversea  60Hz (USA)
+      bit 3:  +4 Oversea  50Hz (Europe)
+    */
+
+    // extern int mode_pal;
+
+    int country = 0;
+
+    char rom_str[3];
+
+    printf("ROM game  : ");
+    for (int j = 0; j < 48; j++) printf("%c", (char)FETCH8ROM(0x150+j));
+    printf("\n");
+
+    rom_str[0] = FETCH8ROM(0x1F0);
+    rom_str[1] = FETCH8ROM(0x1F1);
+    rom_str[2] = FETCH8ROM(0x1F2);
+
+    printf("ROM region:%c%c%c (0x%02x 0x%02x 0x%02x)\n", rom_str[0], rom_str[1], rom_str[2], rom_str[0], rom_str[1],
+           rom_str[2]);
+
+    /* from Gens */
+    if (!memcmp(rom_str, "eur", 3)) country |= 8;
+    else if (!memcmp(rom_str, "EUR", 3)) country |= 8;
+    else if (!memcmp(rom_str, "Europe", 3)) country |= 8;
+    else if (!memcmp(rom_str, "jap", 3)) country |= 1;
+    else if (!memcmp(rom_str, "JAP", 3)) country |= 1;
+    else if (!memcmp(rom_str, "usa", 3)) country |= 4;
+    else if (!memcmp(rom_str, "USA", 3)) country |= 4;
+    else {
+        int i;
+        unsigned char c;
+
+        /* look for each characters */
+        for (i = 0; i < 3; i++) {
+            c = rom_str[i];
+
+            if (c == 'E' || c == 'e') country |= 8;
+            else if (c == 'U') country |= 4;
+            else if (c == 'J' || c == 'j') country |= 1;
+            else if (c == 'K' || c == 'k') country |= 1;
+            else if (c < 16) country |= c;
+            else if ((c >= '0') && (c <= '9')) country |= c - '0';
+            else if ((c >= 'A') && (c <= 'F')) country |= c - 'A' + 10;
+        }
+    }
+    printf("country code=%01x : ", country);
+    /* set default console region (USA > EUROPE > JAPAN) */
+    /*
+    IO REG0	:	MODE 	VMOD 	DISK 	RSV 	VER3 	VER2 	VER1 	VER0
+    MODE (R) 	0: Domestic Model
+                1: Overseas Model
+    VMOD (R) 	0: NTSC CPU clock 7.67 MHz
+                1: PAL CPU clock 7.60 MHz
+    */
+
+    /* EUROPE 50Hz */
+    if (country & 8) {
+        printf("Oversea-PAL Europe 50Hz\n");
+        gwenesis_io_set_reg(0, 0xC1);
+        //  gwenesis_vdp_status |= 0x1;
+        //mode_pal = 1;
+        return;
+    }
+    /* USA 60Hz*/
+    if (country & 4) {
+        printf("Oversea-NTSC USA 60Hz\n");
+        gwenesis_io_set_reg(0, 0x81);
+        //   gwenesis_vdp_status &= 0xFFFE;
+        // mode_pal = 0;
+        return;
+    }
+
+    /* set Asia 60HZ */
+    if (country & 1) {
+        printf("Domestic-NTSC Asia 60Hz\n");
+        gwenesis_io_set_reg(0, 0x1);
+        //  gwenesis_vdp_status &= 0xFFFE;
+        //mode_pal = 0;
+        return;
+    }
+    printf("Oversea-NTSC USA 60Hz no detection>> default mode\n");
+    gwenesis_io_set_reg(0, 0x81);
+    // gwenesis_vdp_status &= 0xFFFE;
+    // mode_pal = 0;
+}
+
+/******************************************************************************
+ *
+ *   Main memory address mapper
+ *   Map all main memory region address for CPU program
+ *   68K Access to Z80 Memory
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_map_z80_address(unsigned int address) {
+    unsigned int range = (address & 0xF000);
+    switch (range) {
+        case 0:
+        case 0x1000:
+            return Z80_RAM_ADDR;
+        case 0x2000:
+        case 0x3000:
+            return Z80_RAM_ADDR1K;
+        case 0x4000:
+            return Z80_YM2612_ADDR;
+        case 0x6000:
+            return Z80_BANK_ADDR;
+        case 0x7000:
+            return Z80_SN76489_ADDR;
+        default:
+            bus_log(__FUNCTION__, "no map Z80 %x", address);
+            assert(0);
+            return NONE;
+    }
+}
+
+/******************************************************************************
+ *
+ *   IO memory address mapper
+ *   Map all input/output region address for CPU program
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_map_io_address(unsigned int address) {
+    unsigned int range = (address & 0x1000);
+    switch (range) {
+        case 0: return IO_CTRL;
+        case 0x1000: return Z80_CTRL;
+        default:
+            // if (address >= 0xa14000 && address < 0xa11404)
+            // return (tmss_state == 0) ? TMSS_CTRL : NONE;
+            bus_log(__FUNCTION__, "no map io %x", address);
+
+            return NONE;
+    }
+}
+
+/******************************************************************************
+ *
+ *   Main memory address mapper
+ *   Map all main memory region address for CPU program
+ *
+ ******************************************************************************/
+
+static inline
+unsigned int gwenesis_bus_map_address(unsigned int address) {
+    // Mask address page
+    unsigned int range = (address & 0xFF0000) >> 16;
+
+    // Check mask and select memory type
+    if (range < 0x80) //        ROM ADDRESS 0x000000 - 0x3FFFFF
+        return ROM_ADDR;
+    if (range == 0xA0) // Z80 ADDRESS 0xA00000 - 0xA0FFFF
+        return gwenesis_bus_map_z80_address(address);
+    if (range == 0xA1) //                  IO ADDRESS  0xA10000 - 0xA1FFFF
+        return gwenesis_bus_map_io_address(address);
+    if (range == 0xC0) // VDP ADDRESS 0xC00000 - 0xDFFFFFF
+        return VDP_ADDR;
+    if (range == 0xFF) // RAM ADDRESS 0xE00000 - 0xFFFFFFF
+        return RAM_ADDR;
+
+
+    // If not a valid address return 0
+    bus_log(__FUNCTION__, "M68K > ?? unnmap address %x", address);
+    //assert(0);
+    return NONE;
+}
+
+/******************************************************************************
+ *
+ *   Main read address routine
+ *   Write an value to memory mapped on specified address
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_read_memory_8(unsigned int address) {
+    bus_log(__FUNCTION__, "read8  %x", address);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            return gwenesis_vdp_read_memory_8(address);
+
+        case ROM_ADDR:
+            return FETCH8ROM(address);
+
+        case RAM_ADDR:
+            return FETCH8RAM(address);
+
+        case IO_CTRL:
+            return gwenesis_io_read_ctrl(address & 0x1F);
+
+        case Z80_CTRL:
+            return z80_read_ctrl(address & 0xFFFF);
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            return ZRAM[address & 0x1FFF];
+
+        case Z80_YM2612_ADDR:
+            return audio_enabled ? YM2612Read(m68k_cycles_master()) : 0x00;
+
+        case Z80_SN76489_ADDR:
+            return 0xff;
+
+        case Z80_BANK_ADDR:
+            return 0xff;
+
+        case TMSS_CTRL:
+            bus_log(__FUNCTION__, "TMS");
+            if (tmss_state == 0)
+                return TMSS[address & 0x4];
+            return 0xFF;
+
+        default:
+            bus_log(__FUNCTION__, " default read 8 %x", address);
+            return 0x00;
+    }
+    return 0x00;
+}
+
+static inline unsigned int gwenesis_bus_read_memory_16(unsigned int address) {
+    bus_log(__FUNCTION__, "read16 %x", address);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            return gwenesis_vdp_read_memory_16(address);
+
+        case RAM_ADDR:
+            return FETCH16RAM(address);
+
+        case ROM_ADDR:
+            return FETCH16ROM(address);
+
+        case IO_CTRL:
+            return gwenesis_io_read_ctrl(address & 0x1F);
+
+        case Z80_CTRL:
+            //  ret_value = z80_read_ctrl(address & 0xFFFF);
+            // return ret_value | ret_value << 8;
+            address &= 0xFFFF;
+            return (z80_read_ctrl(address) << 8) | z80_read_ctrl(address | 1);
+
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            return ZRAM[address & 0X1FFF] | (ZRAM[address & 0X1FFF] << 8);
+
+        case Z80_YM2612_ADDR: {
+            if (audio_enabled) {
+                unsigned int ret_value = YM2612Read(m68k_cycles_master());
+                return ret_value | ret_value << 8;
+            }
+            return 0x00;
+        }
+
+
+        case Z80_SN76489_ADDR:
+            return 0xff;
+
+        case Z80_BANK_ADDR:
+            return 0xff;
+
+        default:
+            bus_log(__FUNCTION__, "read mem 16 default %x", address);
+            return (gwenesis_bus_read_memory_8(address) << 8) |
+                   gwenesis_bus_read_memory_8(address + 1);
+    }
+    return 0x00;
+}
+
+/******************************************************************************
+ *
+ *   Main write address routine
+ *   Write an value to memory mapped on specified address
+ *
+ ******************************************************************************/
+static inline void gwenesis_bus_write_memory_8(unsigned int address,
+                                               unsigned int value) {
+    bus_log(__FUNCTION__, "write8  @%x:%x", address, value);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            gwenesis_vdp_write_memory_16(address & ~1, (value << 8) | value);
+            return;
+
+        case RAM_ADDR:
+            WRITE8RAM(address, value);
+            return;
+
+        case IO_CTRL:
+            gwenesis_io_write_ctrl(address & 0x1F, value);
+            return;
+
+        case Z80_CTRL:
+            z80_write_ctrl(address & 0x1FFF, value);
+            return;
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            ZRAM[address & 0x1FFF] = value;
+            return;
+
+        case Z80_YM2612_ADDR:
+            bus_log(__FUNCTION__, "CPUZ80PSG8 ,m68kclk= %d", m68k_cycles_master());
+            if (audio_enabled)
+                YM2612Write(address & 0x3, value & 0Xff, m68k_cycles_master());
+
+            return;
+
+        case Z80_SN76489_ADDR:
+            bus_log(__FUNCTION__, "CPUZ80FM8  ,m68kclk= %d", m68k_cycles_master());
+            if (audio_enabled)
+                gwenesis_SN76489_Write(value & 0Xff, m68k_cycles_master());
+            return;
+
+        case Z80_BANK_ADDR:
+            //TODO
+            return;
+
+        case TMSS_CTRL:
+
+            if (tmss_state == 0) {
+                TMSS[address & 0x4] = value;
+                tmss_count++;
+                if (tmss_count == 4)
+                    tmss_state = 1;
+            }
+            return;
+
+
+        default:
+            //printf("write(%x, %x)\n", address, value);
+            return;
+    }
+    return;
+}
+
+extern bool sn76489_enabled;
+
+static inline void gwenesis_bus_write_memory_16(unsigned int address,
+                                                unsigned int value) {
+    bus_log(__FUNCTION__, "write16  @%x:%x", address, value);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            gwenesis_vdp_write_memory_16(address, value);
+            return;
+
+        case RAM_ADDR:
+            WRITE16RAM(address, value);
+            return;
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            ZRAM[address & 0X1FFF] = value >> 8;
+            return;
+
+        case IO_CTRL:
+            gwenesis_io_write_ctrl(address & 0x1F, value);
+            return;
+
+        case Z80_CTRL:
+            z80_write_ctrl(address & 0xFFFF, value >> 8);
+            return;
+
+        case Z80_YM2612_ADDR:
+            bus_log(__FUNCTION__, "CZYM16 ,mclk=%d", m68k_cycles_master());
+            if (audio_enabled)
+                YM2612Write(address & 0x3, value >> 8, m68k_cycles_master());
+
+            return;
+
+        case Z80_SN76489_ADDR:
+            bus_log(__FUNCTION__, "CZSN16 ,mclk=%d", m68k_cycles_master());
+            if (audio_enabled && sn76489_enabled)
+                gwenesis_SN76489_Write(value >> 8, m68k_cycles_master());
+            return;
+
+        default:
+            bus_log(__FUNCTION__, "write mem 16 default %x ", address);
+            gwenesis_bus_write_memory_8(address, (value >> 8) & 0xff);
+            gwenesis_bus_write_memory_8(address + 1, (value) & 0xff);
+
+            return;
+    }
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R8
+ *   Read an address from memory mapped and return value as byte
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_8(unsigned int address) {
+    //  if ((address &  0xFF0000 ) == 0xFF0000) return FETCH8RAM(address);
+    return gwenesis_bus_read_memory_8(address);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R16
+ *   Read an address from memory mapped and return value as word
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_16(unsigned int address) {
+    //   if ((address &  0xFF0000 ) == 0xFF0000) return FETCH16RAM(address);
+    return gwenesis_bus_read_memory_16(address);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R32
+ *   Read an address from memory mapped and return value as long
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_32(unsigned int address) {
+    //  if ((address &  0xFF0000 ) == 0xFF0000) return FETCH32RAM(address);
+    return (gwenesis_bus_read_memory_16(address) << 16) | gwenesis_bus_read_memory_16(address + 2);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W8
+ *   Write an value as byte to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_8(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE8RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_8(address, value);
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W16
+ *   Write an value as word to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_16(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE16RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_16(address, value);
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W32
+ *   Write an value as word to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_32(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE32RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_16(address, (value >> 16) & 0xffff);
+    gwenesis_bus_write_memory_16(address + 2, (value) & 0xffff);
+
+    return;
+}
+
+unsigned int m68k_read_disassembler_16(unsigned int address) {
+    return m68k_read_memory_16(address);
+}
+
+unsigned int m68k_read_disassembler_32(unsigned int address) {
+    return m68k_read_memory_32(address);
+}
+
+void gwenesis_bus_save_state() {
+
+}
+
+void gwenesis_bus_load_state() {
+
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.h b/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.h
new file mode 100755
index 0000000..12c092f
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/bus/gwenesis_bus.h
@@ -0,0 +1,98 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_bus_H_
+#define _gwenesis_bus_H_
+
+#pragma once
+
+#include <stdio.h>
+#include <string.h>
+
+#define MAX_ROM_SIZE 0x800000
+#define MAX_RAM_SIZE 0x10000
+#define MAX_Z80_RAM_SIZE 8192
+
+// NTSC PAL timings
+#define MCLOCK_PAL 53203424
+#define MCLOCK_NTSC 53693175
+
+#define MCYCLES_PER_FRAME_NTSC 896040
+#define MCYCLES_PER_FRAME_PAL 1067040
+#define LINES_PER_FRAME_NTSC 262
+#define LINES_PER_FRAME_PAL 313
+
+#define GWENESIS_REFRESH_RATE_NTSC 60
+#define GWENESIS_AUDIO_FREQ_NTSC 53267
+
+#define GWENESIS_REFRESH_RATE_PAL 50
+#define GWENESIS_AUDIO_FREQ_PAL 52781
+
+#define Z80_FREQ_DIVISOR 14     // Frequency divisor to Z80 clock
+#define VDP_CYCLES_PER_LINE 3420// VDP Cycles per Line
+#define GWENESIS_SCREEN_WIDTH 320
+#define GWENESIS_SCREEN_HEIGHT 240
+
+extern uint8_t GWENESIS_AUDIO_SAMPLING_DIVISOR; // Audio quality (i.e. sampling rate) 1: best ... 10: poor
+
+#define AUDIO_FREQ_DIVISOR 1009  //1009
+#define GWENESIS_AUDIO_BUFFER_LENGTH_NTSC 888
+#define GWENESIS_AUDIO_BUFFER_LENGTH_PAL 1056
+
+/* Audio buffer length */
+
+enum mapped_address
+{
+    NONE = 0,
+    ROM_ADDR,
+    ROM_ADDR_MIRROR,
+    Z80_RAM_ADDR,
+    Z80_RAM_ADDR1K,
+    Z80_YM2612_ADDR,
+    Z80_BANK_ADDR,
+    Z80_VDP_ADDR,
+    Z80_SN76489_ADDR,
+    IO_CTRL,
+    Z80_CTRL,
+    TMSS_CTRL,
+    VDP_ADDR,
+    RAM_ADDR
+};
+
+enum gwenesis_bus_pad_button
+{
+    PAD_UP,
+    PAD_DOWN,
+    PAD_LEFT,
+    PAD_RIGHT,
+    PAD_B,
+    PAD_C,
+    PAD_A,
+    PAD_S,
+};
+
+void load_cartridge(uintptr_t rom);
+
+void power_on();
+void reset_emulation();
+void set_region();
+
+void gwenesis_bus_save_state();
+void gwenesis_bus_load_state();
+
+#endif
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68k.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68k.h
new file mode 100755
index 0000000..3968047
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68k.h
@@ -0,0 +1,462 @@
+#ifndef M68K__HEADER
+#define M68K__HEADER
+
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.32
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright Karl Stenerud.  All rights reserved.
+ *
+ * This code may be freely used for non-commercial purposes as long as this
+ * copyright notice remains unaltered in the source code and any binary files
+ * containing this code in compiled form.
+ *
+ * All other licensing terms must be negotiated with the author
+ * (Karl Stenerud).
+ *
+ * The latest version of this code can be obtained at:
+ * http://kstenerud.cjb.net
+ */
+
+ /* Modified by Eke-Eke for Genesis Plus GX:
+
+    - removed unused stuff to reduce memory usage / optimize execution (multiple CPU types support, NMI support, ...)
+    - moved stuff to compile statically in a single object file
+    - implemented support for global cycle count (shared by 68k & Z80 CPU)
+    - added support for interrupt latency (Sesame's Street Counting Cafe, Fatal Rewind)
+    - added proper cycle use on reset
+    - added cycle accurate timings for MUL/DIV instructions (thanks to Jorge Cwik !) 
+    - fixed undocumented flags for DIV instructions (Blood Shot)
+    - fixed undocumented behaviors for ABCD/SBCD/NBCD instructions (thanks to flamewing for his test ROM)
+    - improved auto-vectored interrupts acknowledge cycle timing accuracy
+    - added MAIN-CPU & SUB-CPU support for Mega CD emulation
+    
+  */
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include <setjmp.h>
+#include "macros.h"
+#ifdef HOOK_CPU
+#include "cpuhook.h"
+#endif
+//#include <avr/pgmspace.h>
+
+/* ======================================================================== */
+/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */
+/* ======================================================================== */
+
+/* Check for > 32bit sizes */
+#if UINT_MAX > 0xffffffff
+  #define M68K_INT_GT_32_BIT  1
+#else
+  #define M68K_INT_GT_32_BIT  0
+#endif
+
+/* Data types used in this emulation core */
+#undef sint8
+#undef sint16
+#undef sint32
+#undef sint64
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+#undef sint
+#undef uint
+
+#define sint8  signed   char      /* ASG: changed from char to signed char */
+#define sint16 signed   short
+#define sint32 signed   int      /* AWJ: changed from long to int */
+#define uint8  unsigned char
+#define uint16 unsigned short
+#define uint32 unsigned int      /* AWJ: changed from long to int */
+
+/* signed and unsigned int must be at least 32 bits wide */
+#define sint   signed   int
+//#define uint   unsigned int
+
+
+#if M68K_USE_64_BIT
+#define sint64 signed   long long
+#define uint64 unsigned long long
+#else
+#define sint64 sint32
+#define uint64 uint32
+#endif /* M68K_USE_64_BIT */
+
+
+
+/* Allow for architectures that don't have 8-bit sizes */
+/*#if UCHAR_MAX == 0xff*/
+  #define MAKE_INT_8(A) (sint8)(A)
+/*#else
+  #undef  sint8
+  #define sint8  signed   int
+  #undef  uint8
+  #define uint8  unsigned int
+  INLINE sint MAKE_INT_8(uint value)
+  {
+    return (value & 0x80) ? value | ~0xff : value & 0xff;
+  }*/
+/*#endif *//* UCHAR_MAX == 0xff */
+
+
+/* Allow for architectures that don't have 16-bit sizes */
+/*#if USHRT_MAX == 0xffff*/
+  #define MAKE_INT_16(A) (sint16)(A)
+/*#else
+  #undef  sint16
+  #define sint16 signed   int
+  #undef  uint16
+  #define uint16 unsigned int
+  INLINE sint MAKE_INT_16(uint value)
+  {
+    return (value & 0x8000) ? value | ~0xffff : value & 0xffff;
+  }*/
+/*#endif *//* USHRT_MAX == 0xffff */
+
+
+/* Allow for architectures that don't have 32-bit sizes */
+/*#if UINT_MAX == 0xffffffff*/
+  #define MAKE_INT_32(A) (sint32)(A)
+/*#else
+  #undef  sint32
+  #define sint32  signed   int
+  #undef  uint32
+  #define uint32  unsigned int
+  INLINE sint MAKE_INT_32(uint value)
+  {
+    return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff;
+  }*/
+/*#endif *//* UINT_MAX == 0xffffffff */
+
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/*** BZHXX ***/
+#ifndef FALSE
+#define FALSE 0
+#define TRUE 1
+#endif
+
+#define ROM_SWAP
+#define RAM_SWAP
+
+// 8/16/32 bits access to RAM/ROM
+
+extern const unsigned char *ROM_DATA;
+extern const unsigned char *ROM_METADATA;
+//extern unsigned char* M68K_RAM;
+extern unsigned char M68K_RAM[];
+
+// ROM needs to be converted for this to work!
+#define FETCH8ROM(A)    (unsigned char)  ROM_DATA[ A^1 ]
+#define FETCH16ROM(A)  ( (unsigned short)  (*((unsigned short *) &ROM_DATA[A])) )
+#define FETCH32ROM(A) ( (*(unsigned short *)(&ROM_DATA[(A+2)])) | ((*(unsigned short *)(&ROM_DATA[A])) << 16))
+
+#define FETCH8RAM(A)         (unsigned char)  M68K_RAM[ (A ^ 1) & 0xFFFF]
+#define FETCH16RAM(A)   ( (unsigned short)  (*((unsigned short *) &M68K_RAM[A&0XFFFF])) )
+#define FETCH32RAM(A) ( (*(unsigned short *)(&M68K_RAM[(A+2)&0XFFFF])) | ((*(unsigned short *)(&M68K_RAM[A&0XFFFF])) << 16))
+
+#define WRITE8RAM(A, V)   M68K_RAM[ (A ^ 1) & 0xFFFF ] =  V
+#define WRITE16RAM(A, V)  ( *((unsigned short *) &M68K_RAM[ A & 0XFFFF ]) = V )
+// RAM needs to be cyclically accessible (i.e. addresses wrap around)
+#define WRITE32RAM(A, V)  ( *((unsigned short *) &M68K_RAM[  A      & 0XFFFF ]) = V >> 16); \
+                          ( *((unsigned short *) &M68K_RAM[ (A + 2) & 0XFFFF ]) = V & 0xffff); \
+
+#define m68k_read_immediate_16(A) ( ( (A) & 0x800000) ? FETCH16RAM((A)) : FETCH16ROM((A)) )
+#define m68k_read_immediate_32(A) ( ( (A) & 0x800000) ? FETCH32RAM((A)) : FETCH32ROM((A)) )
+
+#define m68k_read_pcrelative_8(A) ( FETCH8ROM((A)) )
+#define m68k_read_pcrelative_16(A) ( FETCH16ROM((A)) )
+#define m68k_read_pcrelative_32(A) ( FETCH32ROM((A)) )
+
+/* Read from anywhere */
+unsigned int  m68k_read_memory_8(unsigned int address);
+unsigned int  m68k_read_memory_16(unsigned int address);
+unsigned int  m68k_read_memory_32(unsigned int address);
+
+/* Read data immediately following the PC */
+// unsigned int  m68k_read_immediate_16(unsigned int address);
+// unsigned int  m68k_read_immediate_32(unsigned int address);
+
+/* Read data relative to the PC */
+//unsigned int  m68k_read_pcrelative_8(unsigned int address);
+//unsigned int  m68k_read_pcrelative_16(unsigned int address);
+//unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+/* Memory access for the disassembler */
+unsigned int m68k_read_disassembler_8  (unsigned int address);
+unsigned int m68k_read_disassembler_16 (unsigned int address);
+unsigned int m68k_read_disassembler_32 (unsigned int address);
+
+/* Write to anywhere */
+void m68k_write_memory_8(unsigned int address, unsigned int value);
+void m68k_write_memory_16(unsigned int address, unsigned int value);
+void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+/*** BZHXX ***/
+/* ======================================================================== */
+
+/* There are 7 levels of interrupt to the 68K.
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ */
+#define M68K_IRQ_NONE 0
+#define M68K_IRQ_1    1
+#define M68K_IRQ_2    2
+#define M68K_IRQ_3    3
+#define M68K_IRQ_4    4
+#define M68K_IRQ_5    5
+#define M68K_IRQ_6    6
+#define M68K_IRQ_7    7
+
+
+/* Special interrupt acknowledge values.
+ * Use these as special returns from the interrupt acknowledge callback
+ * (specified later in this header).
+ */
+
+/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
+ * This happens in a real 68K if VPA or AVEC is asserted during an interrupt
+ * acknowledge cycle instead of DTACK.
+ */
+#define M68K_INT_ACK_AUTOVECTOR    0xffffffff
+
+/* Causes the spurious interrupt vector (0x18) to be taken
+ * This happens in a real 68K if BERR is asserted during the interrupt
+ * acknowledge cycle (i.e. no devices responded to the acknowledge).
+ */
+#define M68K_INT_ACK_SPURIOUS      0xfffffffe
+
+
+/* Registers used by m68k_get_reg() and m68k_set_reg() */
+typedef enum
+{
+  /* Real registers */
+  M68K_REG_D0,    /* Data registers */
+  M68K_REG_D1,
+  M68K_REG_D2,
+  M68K_REG_D3,
+  M68K_REG_D4,
+  M68K_REG_D5,
+  M68K_REG_D6,
+  M68K_REG_D7,
+  M68K_REG_A0,    /* Address registers */
+  M68K_REG_A1,
+  M68K_REG_A2,
+  M68K_REG_A3,
+  M68K_REG_A4,
+  M68K_REG_A5,
+  M68K_REG_A6,
+  M68K_REG_A7,
+  M68K_REG_PC,    /* Program Counter */
+  M68K_REG_SR,    /* Status Register */
+  M68K_REG_SP,    /* The current Stack Pointer (located in A7) */
+  M68K_REG_USP,   /* User Stack Pointer */
+  M68K_REG_ISP,   /* Interrupt Stack Pointer */
+
+#if M68K_EMULATE_PREFETCH
+  /* Assumed registers */
+  /* These are cheat registers which emulate the 1-longword prefetch
+   * present in the 68000 and 68010.
+   */
+  M68K_REG_PREF_ADDR,  /* Last prefetch address */
+  M68K_REG_PREF_DATA,  /* Last prefetch data */
+#endif
+
+  /* Convenience registers */
+  M68K_REG_IR    /* Instruction register */
+} m68k_register_t;
+
+
+/* 68k memory map structure */
+typedef struct 
+{
+  unsigned char *base;                             /* memory-based access (ROM, RAM) */
+  unsigned int (*read8)(unsigned int address);               /* I/O byte read access */
+  unsigned int (*read16)(unsigned int address);              /* I/O word read access */
+  void (*write8)(unsigned int address, unsigned int data);  /* I/O byte write access */
+  void (*write16)(unsigned int address, unsigned int data); /* I/O word write access */
+} cpu_memory_map;
+
+/* 68k idle loop detection */
+typedef struct
+{
+  uint pc;
+  uint cycle;
+  uint detected;
+} cpu_idle_t;
+
+typedef struct
+{
+  cpu_memory_map memory_map[256]; /* memory mapping */
+
+  cpu_idle_t poll;      /* polling detection */
+
+  uint cycles;          /* current master cycle count */ 
+  uint cycle_end;       /* aimed master cycle count for current execution frame */
+
+  uint dar[16];         /* Data and Address Registers */
+  uint pc;              /* Program Counter */
+  uint sp[5];           /* User and Interrupt Stack Pointers */
+  uint ir;              /* Instruction Register */
+  uint t1_flag;         /* Trace 1 */
+  uint s_flag;          /* Supervisor */
+  uint x_flag;          /* Extend */
+  uint n_flag;          /* Negative */
+  uint not_z_flag;      /* Zero, inverted for speedups */
+  uint v_flag;          /* Overflow */
+  uint c_flag;          /* Carry */
+  uint int_mask;        /* I0-I2 */
+  uint int_level;       /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
+  uint stopped;         /* Stopped state */
+
+  uint pref_addr;       /* Last prefetch address */
+  uint pref_data;       /* Data in the prefetch queue */
+
+  uint instr_mode;      /* Stores whether we are in instruction mode or group 0/1 exception mode */
+  uint run_mode;        /* Stores whether we are processing a reset, bus error, address error, or something else */
+  uint aerr_enabled;    /* Enables/deisables address error checks at runtime */
+  jmp_buf aerr_trap;    /* Address error jump */
+  uint aerr_address;    /* Address error location */
+  uint aerr_write_mode; /* Address error write mode */
+  uint aerr_fc;         /* Address error FC code */
+
+  uint tracing;         /* Tracing enable flag */
+
+  uint address_space;   /* Current FC code */
+
+#ifdef M68K_OVERCLOCK_SHIFT
+  int cycle_ratio;
+#endif
+
+  /* Callbacks to host */
+  int  (*int_ack_callback)(int int_line);           /* Interrupt Acknowledge */
+  void (*reset_instr_callback)(void);               /* Called when a RESET instruction is encountered */
+  int  (*tas_instr_callback)(void);                 /* Called when a TAS instruction is encountered, allows / disallows writeback */
+  void (*set_fc_callback)(unsigned int new_fc);     /* Called when the CPU function code changes */
+} m68ki_cpu_core;
+
+/* CPU cores */
+extern m68ki_cpu_core m68k;
+
+/* ======================================================================== */
+/* ============================== CALLBACKS =============================== */
+/* ======================================================================== */
+
+/* These functions allow you to set callbacks to the host when specific events
+ * occur.  Note that you must enable the corresponding value in m68kconf.h
+ * in order for these to do anything useful.
+ * Note: I have defined default callbacks which are used if you have enabled
+ * the corresponding #define in m68kconf.h but either haven't assigned a
+ * callback or have assigned a callback of NULL.
+ */
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+/* Set the callback for an interrupt acknowledge.
+ * You must enable M68K_EMULATE_INT_ACK in m68kconf.h.
+ * The CPU will call the callback with the interrupt level being acknowledged.
+ * The host program must return either a vector from 0x02-0xff, or one of the
+ * special interrupt acknowledge values specified earlier in this header.
+ * If this is not implemented, the CPU will always assume an autovectored
+ * interrupt, and will automatically clear the interrupt request when it
+ * services the interrupt.
+ * Default behavior: return M68K_INT_ACK_AUTOVECTOR.
+ */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level));
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+/* Set the callback for the RESET instruction.
+ * You must enable M68K_EMULATE_RESET in m68kconf.h.
+ * The CPU calls this callback every time it encounters a RESET instruction.
+ * Default behavior: do nothing.
+ */
+void m68k_set_reset_instr_callback(void  (*callback)(void));
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+/* Set the callback for the TAS instruction.
+ * You must enable M68K_TAS_HAS_CALLBACK in m68kconf.h.
+ * The CPU calls this callback every time it encounters a TAS instruction.
+ * Default behavior: return 1, allow writeback.
+ */
+void m68k_set_tas_instr_callback(int  (*callback)(void));
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+/* Set the callback for CPU function code changes.
+ * You must enable M68K_EMULATE_FC in m68kconf.h.
+ * The CPU calls this callback with the function code before every memory
+ * access to set the CPU's function code according to what kind of memory
+ * access it is (supervisor/user, program/data and such).
+ * Default behavior: do nothing.
+ */
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc));
+#endif
+
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */
+/* ======================================================================== */
+
+/* Do whatever initialisations the core requires.  Should be called
+ * at least once at init time.
+ */
+extern void m68k_init(void);
+
+/* Pulse the RESET pin on the CPU.
+ * You *MUST* reset the CPU at least once to initialize the emulation
+ */
+extern void m68k_pulse_reset(void);
+
+/* Run until given cycle count is reached */
+extern void m68k_run(unsigned int cycles);
+
+/* Get current instruction execution time */
+extern int m68k_cycles(void);
+
+/* Number of cycles run so far from start of frame */
+extern int m68k_cycles_master(void);
+
+/* Number of cycles run so far from run call */
+extern int m68k_cycles_run(void);
+
+/* Set the IPL0-IPL2 pins on the CPU (IRQ).
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ * Setting IRQ to 0 will clear an interrupt request.
+ */
+extern void m68k_set_irq(unsigned int int_level);
+extern void m68k_set_irq_delay(unsigned int int_level);
+extern void m68k_update_irq(unsigned int mask);
+
+/* Halt the CPU as if you pulsed the HALT pin. */
+extern void m68k_pulse_halt(void);
+extern void m68k_clear_halt(void);
+
+/* Peek at the internals of a CPU context.  This can either be a context
+ * retrieved using m68k_get_context() or the currently running context.
+ * If context is NULL, the currently running CPU context will be used.
+ */
+extern unsigned int m68k_get_reg(m68k_register_t reg);
+
+/* Poke values into the internals of the currently running CPU context */
+extern void m68k_set_reg(m68k_register_t reg, unsigned int value);
+
+/* Load/Save state of CPU */
+extern void gwenesis_m68k_save_state();
+extern void gwenesis_m68k_load_state();
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68K__HEADER */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kconf.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kconf.h
new file mode 100755
index 0000000..d426577
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kconf.h
@@ -0,0 +1,93 @@
+#ifndef M68KCONF__HEADER
+#define M68KCONF__HEADER
+
+/* ======================================================================== */
+/* ======================== MAIN 68K CONFIGURATION ======================== */
+/* ======================================================================== */
+
+/* Configuration switches.
+ * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks.
+ * OPT_SPECIFY_HANDLER causes the core to link directly to the function
+ * or macro you specify, rather than using callback functions whose pointer
+ * must be passed in using m68k_set_xxx_callback().
+ */
+#define OPT_OFF             0
+#define OPT_ON              1
+#define OPT_SPECIFY_HANDLER 2
+
+/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a
+ * predecrement destination EA mode instead of m68k_write_32().
+ * To simulate real 68k behavior, m68k_write_32_pd() must first write the high
+ * word to [address+2], and then write the low word to [address].
+ */
+#define M68K_SIMULATE_PD_WRITES     OPT_OFF
+
+/* If ON, CPU will call the interrupt acknowledge callback when it services an
+ * interrupt.
+ * If off, all interrupts will be autovectored and all interrupt requests will
+ * auto-clear when the interrupt is serviced.
+ */
+#define M68K_EMULATE_INT_ACK        OPT_ON //OPT_SPECIFY_HANDLER
+#define M68K_INT_ACK_CALLBACK(A)    your_int_ack_handler_function(A)
+
+/* If ON, CPU will call the output reset callback when it encounters a reset
+ * instruction.
+ */
+#define M68K_EMULATE_RESET          OPT_OFF
+#define M68K_RESET_CALLBACK()       your_reset_handler_function()
+
+/* If ON, CPU will call the callback when it encounters a tas
+ * instruction.
+ */
+#define M68K_TAS_HAS_CALLBACK       OPT_OFF
+#define M68K_TAS_CALLBACK()         your_tas_handler_function()
+
+/* If ON, CPU will call the set fc callback on every memory access to
+ * differentiate between user/supervisor, program/data access like a real
+ * 68000 would.  This should be enabled and the callback should be set if you
+ * want to properly emulate the m68010 or higher. (moves uses function codes
+ * to read/write data from different address spaces)
+ */
+#define M68K_EMULATE_FC             OPT_OFF
+#define M68K_SET_FC_CALLBACK(A)     your_set_fc_handler_function(A)
+
+/* If ON, the CPU will monitor the trace flags and take trace exceptions
+ */
+#define M68K_EMULATE_TRACE          OPT_OFF
+
+/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */
+#define M68K_EMULATE_PREFETCH       OPT_OFF
+
+/* If ON, the CPU will generate address error exceptions if it tries to
+ * access a word or longword at an odd address.
+ * NOTE: This is only emulated properly for 68000 mode.
+ */
+#define M68K_EMULATE_ADDRESS_ERROR  OPT_ON
+
+/* If ON and previous option is also ON, address error exceptions will
+   also be checked when fetching instructions. Disabling this can help
+   speeding up emulation while still emulating address error exceptions
+   on other memory access if needed.
+ * NOTE: This is only emulated properly for 68000 mode.
+ */
+#define M68K_CHECK_PC_ADDRESS_ERROR OPT_OFF
+
+
+/* ----------------------------- COMPATIBILITY ---------------------------- */
+
+/* The following options set optimizations that violate the current ANSI
+ * standard, but will be compliant under the forthcoming C9X standard.
+ */
+
+
+/* If ON, the enulation core will use 64-bit integers to speed up some
+ * operations.
+*/
+#define M68K_USE_64_BIT  OPT_OFF
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCONF__HEADER */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.c b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.c
new file mode 100755
index 0000000..f14d3be
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.c
@@ -0,0 +1,455 @@
+/* ======================================================================== */
+/*                            MAIN 68K CORE                                 */
+/* ======================================================================== */
+#pragma GCC optimize("Ofast")
+#include "pico.h"
+extern int vdp_68k_irq_ack(int int_level);
+
+#define m68ki_cpu m68k
+#define MUL (7)
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#ifndef BUILD_TABLES
+  #ifndef TABLES_FULL
+    #include "m68ki_cycles.h"
+  #else
+    #include "m68ki_cycles_full.h"
+  #endif
+#endif
+
+#include "m68kconf.h"
+#include "m68kcpu.h"
+#include "m68kops.h"
+#include "../../savestate/gwenesis_savestate.h"
+
+
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+#ifdef BUILD_TABLES
+static unsigned char m68ki_cycles[0x10000];
+#endif
+
+static int irq_latency;
+
+m68ki_cpu_core m68k;
+
+
+/* ======================================================================== */
+/* =============================== CALLBACKS ============================== */
+/* ======================================================================== */
+
+/* Default callbacks used if the callback hasn't been set yet, or if the
+ * callback is set to NULL
+ */
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+/* Interrupt acknowledge */
+static int default_int_ack_callback(int int_level)
+{
+  CPU_INT_LEVEL = 0;
+  return M68K_INT_ACK_AUTOVECTOR;
+}
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+/* Called when a reset instruction is executed */
+static void default_reset_instr_callback(void)
+{
+}
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+/* Called when a tas instruction is executed */
+static int default_tas_instr_callback(void)
+{
+  return 1; // allow writeback
+}
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+/* Called every time there's bus activity (read/write to/from memory */
+static void default_set_fc_callback(unsigned int new_fc)
+{
+}
+#endif
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+/* Access the internals of the CPU */
+unsigned int m68k_get_reg(m68k_register_t regnum)
+{
+  switch(regnum)
+  {
+    case M68K_REG_D0:  return m68ki_cpu.dar[0];
+    case M68K_REG_D1:  return m68ki_cpu.dar[1];
+    case M68K_REG_D2:  return m68ki_cpu.dar[2];
+    case M68K_REG_D3:  return m68ki_cpu.dar[3];
+    case M68K_REG_D4:  return m68ki_cpu.dar[4];
+    case M68K_REG_D5:  return m68ki_cpu.dar[5];
+    case M68K_REG_D6:  return m68ki_cpu.dar[6];
+    case M68K_REG_D7:  return m68ki_cpu.dar[7];
+    case M68K_REG_A0:  return m68ki_cpu.dar[8];
+    case M68K_REG_A1:  return m68ki_cpu.dar[9];
+    case M68K_REG_A2:  return m68ki_cpu.dar[10];
+    case M68K_REG_A3:  return m68ki_cpu.dar[11];
+    case M68K_REG_A4:  return m68ki_cpu.dar[12];
+    case M68K_REG_A5:  return m68ki_cpu.dar[13];
+    case M68K_REG_A6:  return m68ki_cpu.dar[14];
+    case M68K_REG_A7:  return m68ki_cpu.dar[15];
+    case M68K_REG_PC:  return MASK_OUT_ABOVE_32(m68ki_cpu.pc);
+    case M68K_REG_SR:  return  m68ki_cpu.t1_flag        |
+                  (m68ki_cpu.s_flag << 11)              |
+                   m68ki_cpu.int_mask                   |
+                  ((m68ki_cpu.x_flag & XFLAG_SET) >> 4) |
+                  ((m68ki_cpu.n_flag & NFLAG_SET) >> 4) |
+                  ((!m68ki_cpu.not_z_flag) << 2)        |
+                  ((m68ki_cpu.v_flag & VFLAG_SET) >> 6) |
+                  ((m68ki_cpu.c_flag & CFLAG_SET) >> 8);
+    case M68K_REG_SP:  return m68ki_cpu.dar[15];
+    case M68K_REG_USP:  return m68ki_cpu.s_flag ? m68ki_cpu.sp[0] : m68ki_cpu.dar[15];
+    case M68K_REG_ISP:  return m68ki_cpu.s_flag ? m68ki_cpu.dar[15] : m68ki_cpu.sp[4];
+#if M68K_EMULATE_PREFETCH
+    case M68K_REG_PREF_ADDR:  return m68ki_cpu.pref_addr;
+    case M68K_REG_PREF_DATA:  return m68ki_cpu.pref_data;
+#endif
+    case M68K_REG_IR:  return m68ki_cpu.ir;
+    default:      return 0;
+  }
+}
+
+void m68k_set_reg(m68k_register_t regnum, unsigned int value)
+{
+  switch(regnum)
+  {
+    case M68K_REG_D0:  REG_D[0] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D1:  REG_D[1] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D2:  REG_D[2] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D3:  REG_D[3] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D4:  REG_D[4] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D5:  REG_D[5] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D6:  REG_D[6] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D7:  REG_D[7] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A0:  REG_A[0] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A1:  REG_A[1] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A2:  REG_A[2] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A3:  REG_A[3] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A4:  REG_A[4] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A5:  REG_A[5] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A6:  REG_A[6] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A7:  REG_A[7] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_PC:  m68ki_jump(MASK_OUT_ABOVE_32(value)); return;
+    case M68K_REG_SR:  m68ki_set_sr(value); return;
+    case M68K_REG_SP:  REG_SP = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_USP:  if(FLAG_S)
+                REG_USP = MASK_OUT_ABOVE_32(value);
+              else
+                REG_SP = MASK_OUT_ABOVE_32(value);
+              return;
+    case M68K_REG_ISP:  if(FLAG_S)
+                REG_SP = MASK_OUT_ABOVE_32(value);
+              else
+                REG_ISP = MASK_OUT_ABOVE_32(value);
+              return;
+    case M68K_REG_IR:  REG_IR = MASK_OUT_ABOVE_16(value); return;
+#if M68K_EMULATE_PREFETCH
+    case M68K_REG_PREF_ADDR:  CPU_PREF_ADDR = MASK_OUT_ABOVE_32(value); return;
+#endif
+    default:      return;
+  }
+}
+
+/* Set the callbacks */
+#if M68K_EMULATE_INT_ACK == OPT_ON
+void m68k_set_int_ack_callback(int  (*callback)(int int_level))
+{
+  CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback;
+}
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+void m68k_set_reset_instr_callback(void  (*callback)(void))
+{
+  CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback;
+}
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+void m68k_set_tas_instr_callback(int  (*callback)(void))
+{
+  CALLBACK_TAS_INSTR = callback ? callback : default_tas_instr_callback;
+}
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc))
+{
+  CALLBACK_SET_FC = callback ? callback : default_set_fc_callback;
+}
+#endif
+
+#ifdef LOGERROR
+
+extern void error(char *format, ...);
+extern uint16 v_counter;
+#endif
+
+/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
+/* KS: Modified so that IPL* bits match with mask positions in the SR
+ *     and cleaned out remenants of the interrupt controller.
+ */
+void m68k_update_irq(unsigned int mask)
+{
+  /* Update IRQ level */
+  CPU_INT_LEVEL |= (mask << 8);
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+}
+
+void m68k_set_irq(unsigned int int_level)
+{
+  /* Set IRQ level */
+  CPU_INT_LEVEL = int_level << 8;
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+}
+
+/* IRQ latency (Fatal Rewind, Sesame's Street Counting Cafe)*/
+void m68k_set_irq_delay(unsigned int int_level)
+{
+  /* Prevent reentrance */
+  if (!irq_latency)
+  {
+    /* This is always triggered from MOVE instructions (VDP CTRL port write) */
+    /* We just make sure this is not a MOVE.L instruction as we could be in */
+    /* the middle of its execution (first memory write).                   */
+    if ((REG_IR & 0xF000) != 0x2000)
+    {
+      /* Finish executing current instruction */
+      USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+
+      /* One instruction delay before interrupt */
+      irq_latency = 1;
+      m68ki_trace_t1() /* auto-disable (see m68kcpu.h) */
+      m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+      REG_IR = m68ki_read_imm_16();
+      m68ki_instruction_jump_table[REG_IR]();
+      m68ki_exception_if_trace() /* auto-disable (see m68kcpu.h) */
+      irq_latency = 0;
+    }
+
+    /* Set IRQ level */
+    CPU_INT_LEVEL = int_level << 8;
+  }
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+
+  /* Check interrupt mask to process IRQ  */
+  m68ki_check_interrupts(); /* Level triggered (IRQ) */
+}
+
+void __time_critical_func(m68k_run)(unsigned int cycles)
+{
+    //  printf("m68K_run current_cycles=%d add=%d STOP=%x\n",m68k.cycles,cycles,CPU_STOPPED);
+  /* Make sure CPU is not already ahead */
+  if (m68k.cycles >= cycles)
+  {
+    return;
+  }
+
+  /* Check interrupt mask to process IRQ if needed */
+  m68ki_check_interrupts();
+
+  /* Make sure we're not stopped */
+  if (CPU_STOPPED)
+  {
+    m68k.cycles = cycles;
+    return;
+  }
+
+  /* Save end cycles count for when CPU is stopped */
+  m68k.cycle_end = cycles;
+
+  /* Return point for when we have an address error (TODO: use goto) */
+  m68ki_set_address_error_trap() /* auto-disable (see m68kcpu.h) */
+
+#ifdef LOGERROR
+  error("[%d][%d] m68k run to %d cycles (%x), irq mask = %x (%x)\n", v_counter, m68k.cycles, cycles, m68k.pc,FLAG_INT_MASK, CPU_INT_LEVEL);
+#endif
+#pragma GCC unroll(4)
+  while (m68k.cycles < cycles)
+  {
+    /* Set tracing accodring to T1. */
+    m68ki_trace_t1() /* auto-disable (see m68kcpu.h) */
+
+    /* Set the address space for reads */
+    m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+    /* Trigger execution hook */
+    if (cpu_hook)
+      cpu_hook(HOOK_M68K_E, 0, REG_PC, 0);
+#endif
+
+    /* Decode next instruction */
+    REG_IR = m68ki_read_imm_16();
+
+//    printf("PC=%x IR=%x CYCLES=%d \n",m68k.pc,REG_IR,CYC_INSTRUCTION[REG_IR]);
+    /* Execute instruction */
+    m68ki_instruction_jump_table[REG_IR]();
+    USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+    /* Trace m68k_exception, if necessary */
+    m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */
+  }
+}
+
+int m68k_cycles(void)
+{
+  return CYC_INSTRUCTION[REG_IR];
+}
+
+int __always_inline m68k_cycles_run(void)
+{
+	return m68k.cycle_end - m68k.cycles;
+}
+
+int __always_inline m68k_cycles_master(void)
+{
+	return m68k.cycles;
+}
+
+void m68k_init(void)
+{
+#ifdef BUILD_TABLES
+  static uint emulation_initialized = 0;
+
+  /* The first call to this function initializes the opcode handler jump table */
+  if(!emulation_initialized)
+  {
+    m68ki_build_opcode_table();
+    emulation_initialized = 1;
+  }
+#endif
+
+#ifdef M68K_OVERCLOCK_SHIFT
+  m68k.cycle_ratio = 1 << M68K_OVERCLOCK_SHIFT;
+#endif
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+  m68k_set_int_ack_callback(NULL);
+#endif
+#if M68K_EMULATE_RESET == OPT_ON
+  m68k_set_reset_instr_callback(NULL);
+#endif
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+  m68k_set_tas_instr_callback(NULL);
+#endif
+#if M68K_EMULATE_FC == OPT_ON
+  m68k_set_fc_callback(NULL);
+#endif
+}
+
+/* Pulse the RESET line on the CPU */
+void m68k_pulse_reset(void)
+{
+  /* Clear all stop levels */
+  CPU_STOPPED = 0;
+#if M68K_EMULATE_ADDRESS_ERROR
+  CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+#endif
+
+  /* Turn off tracing */
+  FLAG_T1 = 0;
+  m68ki_clear_trace()
+
+  /* Interrupt mask to level 7 */
+  FLAG_INT_MASK = 0x0700;
+  CPU_INT_LEVEL = 0;
+  irq_latency = 0;
+
+  /* Go to supervisor mode */
+  m68ki_set_s_flag(SFLAG_SET);
+
+  /* Invalidate the prefetch queue */
+#if M68K_EMULATE_PREFETCH
+  /* Set to arbitrary number since our first fetch is from 0 */
+  CPU_PREF_ADDR = 0x1000;
+#endif /* M68K_EMULATE_PREFETCH */
+
+  /* Read the initial stack pointer and program counter */
+  m68ki_jump(0);
+  REG_SP = m68ki_read_imm_32();
+  REG_PC = m68ki_read_imm_32();
+  m68ki_jump(REG_PC);
+
+#if M68K_EMULATE_ADDRESS_ERROR
+  CPU_RUN_MODE = RUN_MODE_NORMAL;
+#endif
+
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_RESET]);
+}
+
+void m68k_pulse_halt(void)
+{
+  /* Pulse the HALT line on the CPU */
+  CPU_STOPPED |= STOP_LEVEL_HALT;
+}
+
+void m68k_clear_halt(void)
+{
+  /* Clear the HALT line on the CPU */
+  CPU_STOPPED &= ~STOP_LEVEL_HALT;
+}
+
+void gwenesis_m68k_save_state() {
+  SaveState *state;
+  state = saveGwenesisStateOpenForWrite("m68k");
+  
+  saveGwenesisStateSetBuffer(state, "REG_D", REG_D, sizeof(REG_D));
+  saveGwenesisStateSet(state, "SR", m68ki_get_sr());
+  saveGwenesisStateSet(state, "REG_PC", REG_PC);
+  saveGwenesisStateSet(state, "REG_SP", REG_SP);
+  saveGwenesisStateSet(state, "REG_USP", REG_USP);
+  saveGwenesisStateSet(state, "REG_ISP", REG_ISP);
+  saveGwenesisStateSet(state, "REG_IR", REG_IR);
+
+  saveGwenesisStateSet(state, "m68k_cycle_end", m68k.cycle_end);
+  saveGwenesisStateSet(state, "m68k_cycles", m68k.cycles);
+  saveGwenesisStateSet(state, "m68k_int_level", m68k.int_level);
+  saveGwenesisStateSet(state, "m68k_stopped", m68k.stopped);
+}
+
+void gwenesis_m68k_load_state() {
+  SaveState *state = saveGwenesisStateOpenForRead("m68k");
+  saveGwenesisStateGetBuffer(state, "REG_D", REG_D, sizeof(REG_D));
+
+  m68ki_set_sr(saveGwenesisStateGet(state, "SR"));
+  REG_PC = saveGwenesisStateGet(state, "REG_PC");
+  REG_SP = saveGwenesisStateGet(state, "REG_SP");
+  REG_USP = saveGwenesisStateGet(state, "REG_USP");
+  REG_ISP = saveGwenesisStateGet(state, "REG_ISP");
+  REG_IR = saveGwenesisStateGet(state, "REG_IR");
+
+  m68k.cycle_end = saveGwenesisStateGet(state, "m68k_cycle_end");
+  m68k.cycles = saveGwenesisStateGet(state, "m68k_cycles");
+  m68k.int_level = saveGwenesisStateGet(state, "m68k_int_level");
+  m68k.stopped = saveGwenesisStateGet(state, "m68k_stopped");
+
+}
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.h
new file mode 100755
index 0000000..e42b435
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kcpu.h
@@ -0,0 +1,1505 @@
+#ifndef M68KCPU__HEADER
+#define M68KCPU__HEADER
+
+/* ======================================================================== */
+/*                         GENERIC 68K CORE                                 */
+/* ======================================================================== */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <limits.h>
+
+#if M68K_EMULATE_ADDRESS_ERROR
+#include <setjmp.h>
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+#include "m68k.h"
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/* ======================================================================== */
+
+/* Exception Vectors handled by emulation */
+#define EXCEPTION_RESET                    0
+#define EXCEPTION_BUS_ERROR                2 /* This one is not emulated! */
+#define EXCEPTION_ADDRESS_ERROR            3 /* This one is partially emulated (doesn't stack a proper frame yet) */
+#define EXCEPTION_ILLEGAL_INSTRUCTION      4
+#define EXCEPTION_ZERO_DIVIDE              5
+#define EXCEPTION_CHK                      6
+#define EXCEPTION_TRAPV                    7
+#define EXCEPTION_PRIVILEGE_VIOLATION      8
+#define EXCEPTION_TRACE                    9
+#define EXCEPTION_1010                    10
+#define EXCEPTION_1111                    11
+#define EXCEPTION_FORMAT_ERROR            14
+#define EXCEPTION_UNINITIALIZED_INTERRUPT 15
+#define EXCEPTION_SPURIOUS_INTERRUPT      24
+#define EXCEPTION_INTERRUPT_AUTOVECTOR    24
+#define EXCEPTION_TRAP_BASE               32
+
+/* Function codes set by CPU during data/address bus activity */
+#define FUNCTION_CODE_USER_DATA          1
+#define FUNCTION_CODE_USER_PROGRAM       2
+#define FUNCTION_CODE_SUPERVISOR_DATA    5
+#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6
+#define FUNCTION_CODE_CPU_SPACE          7
+
+/* Different ways to stop the CPU */
+#define STOP_LEVEL_STOP 1
+#define STOP_LEVEL_HALT 2
+
+/* Used for 68000 address error processing */
+#if M68K_EMULATE_ADDRESS_ERROR
+#define INSTRUCTION_YES 0
+#define INSTRUCTION_NO  0x08
+#define MODE_READ       0x10
+#define MODE_WRITE      0
+
+#define RUN_MODE_NORMAL          0
+#define RUN_MODE_BERR_AERR_RESET 1
+#endif
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/* ======================================================================== */
+/* ================================ MACROS ================================ */
+/* ======================================================================== */
+
+
+/* ---------------------------- General Macros ---------------------------- */
+
+/* Bit Isolation Macros */
+#define BIT_0(A)  ((A) & 0x00000001)
+#define BIT_1(A)  ((A) & 0x00000002)
+#define BIT_2(A)  ((A) & 0x00000004)
+#define BIT_3(A)  ((A) & 0x00000008)
+#define BIT_4(A)  ((A) & 0x00000010)
+#define BIT_5(A)  ((A) & 0x00000020)
+#define BIT_6(A)  ((A) & 0x00000040)
+#define BIT_7(A)  ((A) & 0x00000080)
+#define BIT_8(A)  ((A) & 0x00000100)
+#define BIT_9(A)  ((A) & 0x00000200)
+#define BIT_A(A)  ((A) & 0x00000400)
+#define BIT_B(A)  ((A) & 0x00000800)
+#define BIT_C(A)  ((A) & 0x00001000)
+#define BIT_D(A)  ((A) & 0x00002000)
+#define BIT_E(A)  ((A) & 0x00004000)
+#define BIT_F(A)  ((A) & 0x00008000)
+#define BIT_10(A) ((A) & 0x00010000)
+#define BIT_11(A) ((A) & 0x00020000)
+#define BIT_12(A) ((A) & 0x00040000)
+#define BIT_13(A) ((A) & 0x00080000)
+#define BIT_14(A) ((A) & 0x00100000)
+#define BIT_15(A) ((A) & 0x00200000)
+#define BIT_16(A) ((A) & 0x00400000)
+#define BIT_17(A) ((A) & 0x00800000)
+#define BIT_18(A) ((A) & 0x01000000)
+#define BIT_19(A) ((A) & 0x02000000)
+#define BIT_1A(A) ((A) & 0x04000000)
+#define BIT_1B(A) ((A) & 0x08000000)
+#define BIT_1C(A) ((A) & 0x10000000)
+#define BIT_1D(A) ((A) & 0x20000000)
+#define BIT_1E(A) ((A) & 0x40000000)
+#define BIT_1F(A) ((A) & 0x80000000)
+
+/* Get the most significant bit for specific sizes */
+#define GET_MSB_8(A)  ((A) & 0x80)
+#define GET_MSB_9(A)  ((A) & 0x100)
+#define GET_MSB_16(A) ((A) & 0x8000)
+#define GET_MSB_17(A) ((A) & 0x10000)
+#define GET_MSB_32(A) ((A) & 0x80000000)
+#if M68K_USE_64_BIT
+#define GET_MSB_33(A) ((A) & 0x100000000)
+#endif /* M68K_USE_64_BIT */
+
+/* Isolate nibbles */
+#define LOW_NIBBLE(A)  ((A) & 0x0f)
+#define HIGH_NIBBLE(A) ((A) & 0xf0)
+
+/* These are used to isolate 8, 16, and 32 bit sizes */
+#define MASK_OUT_ABOVE_2(A)  ((A) & 3)
+#define MASK_OUT_ABOVE_8(A)  ((A) & 0xff)
+#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff)
+#define MASK_OUT_BELOW_2(A)  ((A) & ~3)
+#define MASK_OUT_BELOW_8(A)  ((A) & ~0xff)
+#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff)
+
+/* No need to mask if we are 32 bit */
+#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT
+  #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff)
+  #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff)
+#else
+  #define MASK_OUT_ABOVE_32(A) (A)
+  #define MASK_OUT_BELOW_32(A) 0
+#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */
+
+/* Simulate address lines of 68k family */
+#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)
+
+
+/* Shift & Rotate Macros. */
+#define LSL(A, C) ((A) << (C))
+#define LSR(A, C) ((A) >> (C))
+
+/* Some > 32-bit optimizations */
+#if M68K_INT_GT_32_BIT
+  /* Shift left and right */
+  #define LSR_32(A, C) ((A) >> (C))
+  #define LSL_32(A, C) ((A) << (C))
+#else
+  /* We have to do this because the morons at ANSI decided that shifts
+     * by >= data size are undefined.
+     */
+  #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0)
+  #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0)
+#endif /* M68K_INT_GT_32_BIT */
+
+#if M68K_USE_64_BIT
+  #define LSL_32_64(A, C) ((A) << (C))
+  #define LSR_32_64(A, C) ((A) >> (C))
+  #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C)))
+  #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C)))
+#endif /* M68K_USE_64_BIT */
+
+#define ROL_8(A, C)      MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C)))
+#define ROL_9(A, C)                      (LSL(A, C) | LSR(A, 9-(C)))
+#define ROL_16(A, C)    MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C)))
+#define ROL_17(A, C)                     (LSL(A, C) | LSR(A, 17-(C)))
+#define ROL_32(A, C)    MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C)))
+#define ROL_33(A, C)                     (LSL_32(A, C) | LSR_32(A, 33-(C)))
+
+#define ROR_8(A, C)      MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C)))
+#define ROR_9(A, C)                      (LSR(A, C) | LSL(A, 9-(C)))
+#define ROR_16(A, C)    MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C)))
+#define ROR_17(A, C)                     (LSR(A, C) | LSL(A, 17-(C)))
+#define ROR_32(A, C)    MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C)))
+#define ROR_33(A, C)                     (LSR_32(A, C) | LSL_32(A, 33-(C)))
+
+
+
+/* ------------------------------ CPU Access ------------------------------ */
+
+/* Access the CPU registers */
+#define REG_DA           m68ki_cpu.dar /* easy access to data and address regs */
+#define REG_D            m68ki_cpu.dar
+#define REG_A            (m68ki_cpu.dar+8)
+#define REG_PC           m68ki_cpu.pc
+#define REG_SP_BASE      m68ki_cpu.sp
+#define REG_USP          m68ki_cpu.sp[0]
+#define REG_ISP          m68ki_cpu.sp[4]
+#define REG_SP           m68ki_cpu.dar[15]
+#define REG_IR           m68ki_cpu.ir
+
+#define FLAG_T1          m68ki_cpu.t1_flag
+#define FLAG_S           m68ki_cpu.s_flag
+#define FLAG_X           m68ki_cpu.x_flag
+#define FLAG_N           m68ki_cpu.n_flag
+#define FLAG_Z           m68ki_cpu.not_z_flag
+#define FLAG_V           m68ki_cpu.v_flag
+#define FLAG_C           m68ki_cpu.c_flag
+#define FLAG_INT_MASK    m68ki_cpu.int_mask
+
+#define CPU_INT_LEVEL    m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
+#define CPU_STOPPED      m68ki_cpu.stopped
+#if M68K_EMULATE_PREFETCH
+#define CPU_PREF_ADDR    m68ki_cpu.pref_addr
+#define CPU_PREF_DATA    m68ki_cpu.pref_data
+#endif
+#define CPU_ADDRESS_MASK  0x00ffffff
+#if M68K_EMULATE_ADDRESS_ERROR
+#define CPU_INSTR_MODE   m68ki_cpu.instr_mode
+#define CPU_RUN_MODE     m68ki_cpu.run_mode
+#endif
+
+#define CYC_INSTRUCTION   m68ki_cycles
+#define CYC_EXCEPTION     m68ki_exception_cycle_table
+#define CYC_BCC_NOTAKE_B  ( -2 * MUL)
+#define CYC_BCC_NOTAKE_W  (  2 * MUL)
+#define CYC_DBCC_F_NOEXP  ( -2 * MUL)
+#define CYC_DBCC_F_EXP    (  2 * MUL)
+#define CYC_SCC_R_TRUE    (  2 * MUL)
+#define CYC_MOVEM_W       (  4 * MUL)
+#define CYC_MOVEM_L       (  8 * MUL)
+#define CYC_SHIFT         (  2 * MUL)
+#define CYC_RESET         (132 * MUL)
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+#define CALLBACK_INT_ACK      m68ki_cpu.int_ack_callback
+#endif
+#if M68K_EMULATE_RESET == OPT_ON
+#define CALLBACK_RESET_INSTR  m68ki_cpu.reset_instr_callback
+#endif
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+#define CALLBACK_TAS_INSTR    m68ki_cpu.tas_instr_callback
+#endif
+#if M68K_EMULATE_FC == OPT_ON
+#define CALLBACK_SET_FC       m68ki_cpu.set_fc_callback
+#endif
+
+
+/* ----------------------------- Configuration ---------------------------- */
+
+/* These defines are dependant on the configuration defines in m68kconf.h */
+
+/* Enable or disable callback functions */
+#if M68K_EMULATE_INT_ACK
+  #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER
+    #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A);
+  #else
+    #define m68ki_int_ack(A) CALLBACK_INT_ACK(A);
+  #endif
+#else
+  /* Default action is to used autovector mode, which is most common */
+  #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR
+#endif /* M68K_EMULATE_INT_ACK */
+
+#if M68K_EMULATE_RESET
+  #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER
+    #define m68ki_output_reset() M68K_RESET_CALLBACK();
+  #else
+    #define m68ki_output_reset() CALLBACK_RESET_INSTR();
+  #endif
+#else
+  #define m68ki_output_reset()
+#endif /* M68K_EMULATE_RESET */
+
+#if M68K_TAS_HAS_CALLBACK
+  #if M68K_TAS_HAS_CALLBACK == OPT_SPECIFY_HANDLER
+    #define m68ki_tas_callback() M68K_TAS_CALLBACK()
+  #else
+    #define m68ki_tas_callback() CALLBACK_TAS_INSTR()
+  #endif
+#else
+  #define m68ki_tas_callback() 0
+#endif /* M68K_TAS_HAS_CALLBACK */
+
+
+/* Enable or disable function code emulation */
+#if M68K_EMULATE_FC
+  #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER
+    #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A);
+  #else
+    #define m68ki_set_fc(A) CALLBACK_SET_FC(A);
+  #endif
+  #define m68ki_use_data_space() m68ki_cpu.address_space = FUNCTION_CODE_USER_DATA;
+  #define m68ki_use_program_space() m68ki_cpu.address_space = FUNCTION_CODE_USER_PROGRAM;
+  #define m68ki_get_address_space() m68ki_cpu.address_space
+#else
+  #define m68ki_set_fc(A)
+  #define m68ki_use_data_space()
+  #define m68ki_use_program_space()
+  #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA
+#endif /* M68K_EMULATE_FC */
+
+
+/* Enable or disable trace emulation */
+#if M68K_EMULATE_TRACE
+  /* Initiates trace checking before each instruction (t1) */
+  #define m68ki_trace_t1() m68ki_cpu.tracing = FLAG_T1;
+  /* Clear all tracing */
+  #define m68ki_clear_trace() m68ki_cpu.tracing = 0;
+  /* Cause a trace exception if we are tracing */
+  #define m68ki_exception_if_trace() if(m68ki_cpu.tracing) m68ki_exception_trace();
+#else
+  #define m68ki_trace_t1()
+  #define m68ki_clear_trace()
+  #define m68ki_exception_if_trace()
+#endif /* M68K_EMULATE_TRACE */
+
+
+/* Enable or disable Address error emulation */
+#if M68K_EMULATE_ADDRESS_ERROR
+  #define m68ki_set_address_error_trap() \
+    if(setjmp(m68ki_cpu.aerr_trap) != 0) \
+    { \
+      m68ki_exception_address_error(); \
+    }
+
+  #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+    if((ADDR)&1) \
+    { \
+      if (m68ki_cpu.aerr_enabled) \
+      { \
+        m68ki_cpu.aerr_address = ADDR; \
+        m68ki_cpu.aerr_write_mode = WRITE_MODE; \
+        m68ki_cpu.aerr_fc = FC; \
+        longjmp(m68ki_cpu.aerr_trap, 1); \
+      } \
+    }
+#else
+  #define m68ki_set_address_error_trap()
+  #define m68ki_check_address_error(ADDR, WRITE_MODE, FC)
+#endif /* M68K_ADDRESS_ERROR */
+
+
+/* -------------------------- EA / Operand Access ------------------------- */
+
+/*
+ * The general instruction format follows this pattern:
+ * .... XXX. .... .YYY
+ * where XXX is register X and YYY is register Y
+ */
+
+/* Data Register Isolation */
+#define DX (REG_D[(REG_IR >> 9) & 7])
+#define DY (REG_D[REG_IR & 7])
+
+/* Address Register Isolation */
+#define AX (REG_A[(REG_IR >> 9) & 7])
+#define AY (REG_A[REG_IR & 7])
+
+/* Effective Address Calculations */
+#define EA_AY_AI_8()   AY                                    /* address register indirect */
+#define EA_AY_AI_16()  EA_AY_AI_8()
+#define EA_AY_AI_32()  EA_AY_AI_8()
+#define EA_AY_PI_8()   (AY++)                                /* postincrement (size = byte) */
+#define EA_AY_PI_16()  ((AY+=2)-2)                           /* postincrement (size = word) */
+#define EA_AY_PI_32()  ((AY+=4)-4)                           /* postincrement (size = long) */
+#define EA_AY_PD_8()   (--AY)                                /* predecrement (size = byte) */
+#define EA_AY_PD_16()  (AY-=2)                               /* predecrement (size = word) */
+#define EA_AY_PD_32()  (AY-=4)                               /* predecrement (size = long) */
+#define EA_AY_DI_8()   (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_16()  EA_AY_DI_8()
+#define EA_AY_DI_32()  EA_AY_DI_8()
+#define EA_AY_IX_8()   m68ki_get_ea_ix(AY)                   /* indirect + index */
+#define EA_AY_IX_16()  EA_AY_IX_8()
+#define EA_AY_IX_32()  EA_AY_IX_8()
+
+#define EA_AX_AI_8()   AX
+#define EA_AX_AI_16()  EA_AX_AI_8()
+#define EA_AX_AI_32()  EA_AX_AI_8()
+#define EA_AX_PI_8()   (AX++)
+#define EA_AX_PI_16()  ((AX+=2)-2)
+#define EA_AX_PI_32()  ((AX+=4)-4)
+#define EA_AX_PD_8()   (--AX)
+#define EA_AX_PD_16()  (AX-=2)
+#define EA_AX_PD_32()  (AX-=4)
+#define EA_AX_DI_8()   (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_16()  EA_AX_DI_8()
+#define EA_AX_DI_32()  EA_AX_DI_8()
+#define EA_AX_IX_8()   m68ki_get_ea_ix(AX)
+#define EA_AX_IX_16()  EA_AX_IX_8()
+#define EA_AX_IX_32()  EA_AX_IX_8()
+
+#define EA_A7_PI_8()   ((REG_A[7]+=2)-2)
+#define EA_A7_PD_8()   (REG_A[7]-=2)
+
+#define EA_AW_8()      MAKE_INT_16(m68ki_read_imm_16())      /* absolute word */
+#define EA_AW_16()     EA_AW_8()
+#define EA_AW_32()     EA_AW_8()
+#define EA_AL_8()      m68ki_read_imm_32()                   /* absolute long */
+#define EA_AL_16()     EA_AL_8()
+#define EA_AL_32()     EA_AL_8()
+#define EA_PCDI_8()    m68ki_get_ea_pcdi()                   /* pc indirect + displacement */
+#define EA_PCDI_16()   EA_PCDI_8()
+#define EA_PCDI_32()   EA_PCDI_8()
+#define EA_PCIX_8()    m68ki_get_ea_pcix()                   /* pc indirect + index */
+#define EA_PCIX_16()   EA_PCIX_8()
+#define EA_PCIX_32()   EA_PCIX_8()
+
+
+#define OPER_I_8()     m68ki_read_imm_8()
+#define OPER_I_16()    m68ki_read_imm_16()
+#define OPER_I_32()    m68ki_read_imm_32()
+
+
+/* --------------------------- Status Register ---------------------------- */
+
+/* Flag Calculation Macros */
+#define CFLAG_8(A) (A)
+#define CFLAG_16(A) ((A)>>8)
+
+#if M68K_INT_GT_32_BIT
+  #define CFLAG_ADD_32(S, D, R) ((R)>>24)
+  #define CFLAG_SUB_32(S, D, R) ((R)>>24)
+#else
+  #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23)
+  #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23)
+#endif /* M68K_INT_GT_32_BIT */
+
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
+#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24)
+
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
+#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24)
+
+#define NFLAG_8(A) (A)
+#define NFLAG_16(A) ((A)>>8)
+#define NFLAG_32(A) ((A)>>24)
+#define NFLAG_64(A) ((A)>>56)
+
+#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A)
+#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A)
+#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A)
+
+
+/* Flag values */
+#define NFLAG_SET   0x80
+#define NFLAG_CLEAR 0
+#define CFLAG_SET   0x100
+#define CFLAG_CLEAR 0
+#define XFLAG_SET   0x100
+#define XFLAG_CLEAR 0
+#define VFLAG_SET   0x80
+#define VFLAG_CLEAR 0
+#define ZFLAG_SET   0
+#define ZFLAG_CLEAR 0xffffffff
+#define SFLAG_SET   4
+#define SFLAG_CLEAR 0
+
+/* Turn flag values into 1 or 0 */
+#define XFLAG_AS_1() ((FLAG_X>>8)&1)
+#define NFLAG_AS_1() ((FLAG_N>>7)&1)
+#define VFLAG_AS_1() ((FLAG_V>>7)&1)
+#define ZFLAG_AS_1() (!FLAG_Z)
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)
+
+
+/* Conditions */
+#define COND_CS() (FLAG_C&0x100)
+#define COND_CC() (!COND_CS())
+#define COND_VS() (FLAG_V&0x80)
+#define COND_VC() (!COND_VS())
+#define COND_NE() FLAG_Z
+#define COND_EQ() (!COND_NE())
+#define COND_MI() (FLAG_N&0x80)
+#define COND_PL() (!COND_MI())
+#define COND_LT() ((FLAG_N^FLAG_V)&0x80)
+#define COND_GE() (!COND_LT())
+#define COND_HI() (COND_CC() && COND_NE())
+#define COND_LS() (COND_CS() || COND_EQ())
+#define COND_GT() (COND_GE() && COND_NE())
+#define COND_LE() (COND_LT() || COND_EQ())
+
+/* Reversed conditions */
+#define COND_NOT_CS() COND_CC()
+#define COND_NOT_CC() COND_CS()
+#define COND_NOT_VS() COND_VC()
+#define COND_NOT_VC() COND_VS()
+#define COND_NOT_NE() COND_EQ()
+#define COND_NOT_EQ() COND_NE()
+#define COND_NOT_MI() COND_PL()
+#define COND_NOT_PL() COND_MI()
+#define COND_NOT_LT() COND_GE()
+#define COND_NOT_GE() COND_LT()
+#define COND_NOT_HI() COND_LS()
+#define COND_NOT_LS() COND_HI()
+#define COND_NOT_GT() COND_LE()
+#define COND_NOT_LE() COND_GT()
+
+/* Not real conditions, but here for convenience */
+#define COND_XS() (FLAG_X&0x100)
+#define COND_XC() (!COND_XS)
+
+
+/* Get the condition code register */
+#define m68ki_get_ccr() ((COND_XS() >> 4) | \
+             (COND_MI() >> 4) | \
+             (COND_EQ() << 2) | \
+             (COND_VS() >> 6) | \
+             (COND_CS() >> 8))
+
+/* Get the status register */
+#define m68ki_get_sr() ( FLAG_T1  | \
+            (FLAG_S        << 11) | \
+             FLAG_INT_MASK        | \
+             m68ki_get_ccr())
+
+
+
+/* ---------------------------- Cycle Counting ---------------------------- */
+
+#ifdef M68K_OVERCLOCK_SHIFT
+#define USE_CYCLES(A) m68ki_cpu.cycles += ((A) * m68ki_cpu.cycle_ratio) >> M68K_OVERCLOCK_SHIFT
+#else
+#define USE_CYCLES(A) m68ki_cpu.cycles += (A)
+#endif
+#define SET_CYCLES(A) m68ki_cpu.cycles  = (A)
+
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+void gwenesis_m68k_save_state();
+void gwenesis_m68k_load_state();
+
+/* ----------------------------- Read / Write ----------------------------- */
+
+/*** BZHXX ***/
+/* Read data immediately following the PC */
+//#define m68k_read_immediate_16(address) *(uint16 *)(m68ki_cpu.memory_map[((address)>>16)&0xff].base + ((address) & 0xffff))
+//#define m68k_read_immediate_32(address) (m68k_read_immediate_16(address) << 16) | (m68k_read_immediate_16(address+2))
+
+/* Read data relative to the PC */
+//#define m68k_read_pcrelative_8(address)  READ_BYTE(m68ki_cpu.memory_map[((address)>>16)&0xff].base, (address) & 0xffff)
+//#define m68k_read_pcrelative_16(address) m68k_read_immediate_16(address)
+//#define m68k_read_pcrelative_32(address) m68k_read_immediate_32(address)
+
+/* map read immediate 8 to read immediate 16 */
+#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16())
+
+/* Map PC-relative reads */
+#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)
+#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)
+#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)
+
+
+/* ======================================================================== */
+/* =============================== PROTOTYPES ============================= */
+/* ======================================================================== */
+
+/* Used by shift & rotate instructions */
+static const uint8 m68ki_shift_8_table[65] =
+{
+  0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff
+};
+
+static const uint16 m68ki_shift_16_table[65] =
+{
+  0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00,
+  0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff
+};
+
+static const uint m68ki_shift_32_table[65] =
+{
+  0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000,
+  0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000,
+  0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000,
+  0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00,
+  0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8,
+  0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+
+/* Number of clock cycles to use for exception processing.
+ * I used 4 for any vectors that are undocumented for processing times.
+ */
+static const uint16 m68ki_exception_cycle_table[256] =
+{
+     40*MUL, /*  0: Reset - Initial Stack Pointer                      */
+      4*MUL, /*  1: Reset - Initial Program Counter                    */
+     50*MUL, /*  2: Bus Error                             (unemulated) */
+     50*MUL, /*  3: Address Error                         (unemulated) */
+     34*MUL, /*  4: Illegal Instruction                                */
+     38*MUL, /*  5: Divide by Zero -- ASG: changed from 42             */
+     40*MUL, /*  6: CHK -- ASG: chanaged from 44                       */
+     34*MUL, /*  7: TRAPV                                              */
+     34*MUL, /*  8: Privilege Violation                                */
+     34*MUL, /*  9: Trace                                              */
+      4*MUL, /* 10: 1010                                               */
+      4*MUL, /* 11: 1111                                               */
+      4*MUL, /* 12: RESERVED                                           */
+      4*MUL, /* 13: Coprocessor Protocol Violation        (unemulated) */
+      4*MUL, /* 14: Format Error                                       */
+     44*MUL, /* 15: Uninitialized Interrupt                            */
+      4*MUL, /* 16: RESERVED                                           */
+      4*MUL, /* 17: RESERVED                                           */
+      4*MUL, /* 18: RESERVED                                           */
+      4*MUL, /* 19: RESERVED                                           */
+      4*MUL, /* 20: RESERVED                                           */
+      4*MUL, /* 21: RESERVED                                           */
+      4*MUL, /* 22: RESERVED                                           */
+      4*MUL, /* 23: RESERVED                                           */
+     44*MUL, /* 24: Spurious Interrupt                                 */
+     54*MUL, /* 25: Level 1 Interrupt Autovector                       */
+     54*MUL, /* 26: Level 2 Interrupt Autovector                       */
+     54*MUL, /* 27: Level 3 Interrupt Autovector                       */
+     54*MUL, /* 28: Level 4 Interrupt Autovector                       */
+     54*MUL, /* 29: Level 5 Interrupt Autovector                       */
+     54*MUL, /* 30: Level 6 Interrupt Autovector                       */
+     54*MUL, /* 31: Level 7 Interrupt Autovector                       */
+     34*MUL, /* 32: TRAP #0 -- ASG: chanaged from 38                   */
+     34*MUL, /* 33: TRAP #1                                            */
+     34*MUL, /* 34: TRAP #2                                            */
+     34*MUL, /* 35: TRAP #3                                            */
+     34*MUL, /* 36: TRAP #4                                            */
+     34*MUL, /* 37: TRAP #5                                            */
+     34*MUL, /* 38: TRAP #6                                            */
+     34*MUL, /* 39: TRAP #7                                            */
+     34*MUL, /* 40: TRAP #8                                            */
+     34*MUL, /* 41: TRAP #9                                            */
+     34*MUL, /* 42: TRAP #10                                           */
+     34*MUL, /* 43: TRAP #11                                           */
+     34*MUL, /* 44: TRAP #12                                           */
+     34*MUL, /* 45: TRAP #13                                           */
+     34*MUL, /* 46: TRAP #14                                           */
+     34*MUL, /* 47: TRAP #15                                           */
+      4*MUL, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+      4*MUL, /* 49: FP Inexact Result                     (unemulated) */
+      4*MUL, /* 50: FP Divide by Zero                     (unemulated) */
+      4*MUL, /* 51: FP Underflow                          (unemulated) */
+      4*MUL, /* 52: FP Operand Error                      (unemulated) */
+      4*MUL, /* 53: FP Overflow                           (unemulated) */
+      4*MUL, /* 54: FP Signaling NAN                      (unemulated) */
+      4*MUL, /* 55: FP Unimplemented Data Type            (unemulated) */
+      4*MUL, /* 56: MMU Configuration Error               (unemulated) */
+      4*MUL, /* 57: MMU Illegal Operation Error           (unemulated) */
+      4*MUL, /* 58: MMU Access Level Violation Error      (unemulated) */
+      4*MUL, /* 59: RESERVED                                           */
+      4*MUL, /* 60: RESERVED                                           */
+      4*MUL, /* 61: RESERVED                                           */
+      4*MUL, /* 62: RESERVED                                           */
+      4*MUL, /* 63: RESERVED                                           */
+         /* 64-255: User Defined                                   */
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL
+};
+
+/* Read data immediately after the program counter */
+INLINE uint m68ki_read_imm_16(void);
+INLINE uint m68ki_read_imm_32(void);
+
+/* Read from the current address space */
+INLINE uint m68ki_read_8(uint address);
+INLINE uint m68ki_read_16(uint address);
+INLINE uint m68ki_read_32(uint address);
+
+/* Write to the current data space */
+INLINE void m68ki_write_8(uint address, uint value);
+INLINE void m68ki_write_16(uint address, uint value);
+INLINE void m68ki_write_32(uint address, uint value);
+
+/* Indexed and PC-relative ea fetching */
+INLINE uint m68ki_get_ea_pcdi(void);
+INLINE uint m68ki_get_ea_pcix(void);
+INLINE uint m68ki_get_ea_ix(uint An);
+
+/* Operand fetching */
+INLINE uint OPER_AY_AI_8(void);
+INLINE uint OPER_AY_AI_16(void);
+INLINE uint OPER_AY_AI_32(void);
+INLINE uint OPER_AY_PI_8(void);
+INLINE uint OPER_AY_PI_16(void);
+INLINE uint OPER_AY_PI_32(void);
+INLINE uint OPER_AY_PD_8(void);
+INLINE uint OPER_AY_PD_16(void);
+INLINE uint OPER_AY_PD_32(void);
+INLINE uint OPER_AY_DI_8(void);
+INLINE uint OPER_AY_DI_16(void);
+INLINE uint OPER_AY_DI_32(void);
+INLINE uint OPER_AY_IX_8(void);
+INLINE uint OPER_AY_IX_16(void);
+INLINE uint OPER_AY_IX_32(void);
+
+INLINE uint OPER_AX_AI_8(void);
+INLINE uint OPER_AX_AI_16(void);
+INLINE uint OPER_AX_AI_32(void);
+INLINE uint OPER_AX_PI_8(void);
+INLINE uint OPER_AX_PI_16(void);
+INLINE uint OPER_AX_PI_32(void);
+INLINE uint OPER_AX_PD_8(void);
+INLINE uint OPER_AX_PD_16(void);
+INLINE uint OPER_AX_PD_32(void);
+INLINE uint OPER_AX_DI_8(void);
+INLINE uint OPER_AX_DI_16(void);
+INLINE uint OPER_AX_DI_32(void);
+INLINE uint OPER_AX_IX_8(void);
+INLINE uint OPER_AX_IX_16(void);
+INLINE uint OPER_AX_IX_32(void);
+
+INLINE uint OPER_A7_PI_8(void);
+INLINE uint OPER_A7_PD_8(void);
+
+INLINE uint OPER_AW_8(void);
+INLINE uint OPER_AW_16(void);
+INLINE uint OPER_AW_32(void);
+INLINE uint OPER_AL_8(void);
+INLINE uint OPER_AL_16(void);
+INLINE uint OPER_AL_32(void);
+INLINE uint OPER_PCDI_8(void);
+INLINE uint OPER_PCDI_16(void);
+INLINE uint OPER_PCDI_32(void);
+INLINE uint OPER_PCIX_8(void);
+INLINE uint OPER_PCIX_16(void);
+INLINE uint OPER_PCIX_32(void);
+
+/* Stack operations */
+INLINE void m68ki_push_16(uint value);
+INLINE void m68ki_push_32(uint value);
+INLINE uint m68ki_pull_16(void);
+INLINE uint m68ki_pull_32(void);
+
+/* Program flow operations */
+INLINE void m68ki_jump(uint new_pc);
+INLINE void m68ki_jump_vector(uint vector);
+INLINE void m68ki_branch_8(uint offset);
+INLINE void m68ki_branch_16(uint offset);
+INLINE void m68ki_branch_32(uint offset);
+
+/* Status register operations. */
+INLINE void m68ki_set_s_flag(uint value);            /* Only bit 2 of value should be set (i.e. 4 or 0) */
+INLINE void m68ki_set_ccr(uint value);               /* set the condition code register */
+INLINE void m68ki_set_sr(uint value);                /* set the status register */
+
+/* Exception processing */
+INLINE uint m68ki_init_exception(void);              /* Initial exception processing */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */
+#if M68K_EMULATE_ADDRESS_ERROR
+INLINE void m68ki_stack_frame_buserr(uint sr);
+#endif
+INLINE void m68ki_exception_trap(uint vector);
+INLINE void m68ki_exception_trapN(uint vector);
+#if M68K_EMULATE_TRACE
+INLINE void m68ki_exception_trace(void);
+#endif
+static void m68ki_exception_privilege_violation(void); /* do not inline in order to reduce function size and allow inlining of read/write functions by the compile */
+INLINE void m68ki_exception_1010(void);
+INLINE void m68ki_exception_1111(void);
+INLINE void m68ki_exception_illegal(void);
+#if M68K_EMULATE_ADDRESS_ERROR
+INLINE void m68ki_exception_address_error(void);
+#endif
+INLINE void m68ki_exception_interrupt(uint int_level);
+INLINE void m68ki_check_interrupts(void);            /* ASG: check for interrupts */
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+
+/* ---------------------------- Read Immediate ---------------------------- */
+
+/* Handles all immediate reads, does address error check, function code setting,
+ * and prefetching if they are enabled in m68kconf.h
+ */
+INLINE uint m68ki_read_imm_16(void)
+{
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+#if M68K_EMULATE_PREFETCH
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+  }
+  REG_PC += 2;
+  return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3));
+#else
+  uint pc = REG_PC;
+  REG_PC += 2;
+  return m68k_read_immediate_16(pc);
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+INLINE uint m68ki_read_imm_32(void)
+{
+#if M68K_EMULATE_PREFETCH
+  uint temp_val;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+  }
+  temp_val = CPU_PREF_DATA;
+  REG_PC += 2;
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+    temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16));
+  }
+  REG_PC += 2;
+
+  return temp_val;
+#else
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+  uint pc = REG_PC;
+  REG_PC += 4;
+  return m68k_read_immediate_32(pc);
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+
+
+/* ------------------------- Top level read/write ------------------------- */
+
+/* Handles all memory accesses (except for immediate reads if they are
+ * configured to use separate functions in m68kconf.h).
+ * All memory accesses must go through these top level functions.
+ * These functions will also check for address error and set the function
+ * code if they are enabled in m68kconf.h.
+ */
+ /*** BZHXX ***/
+
+INLINE uint m68ki_read_8(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+	if (ADDRESS_68K(address) <  0x800000) return FETCH8ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH8RAM(ADDRESS_68K(address));
+	return m68k_read_memory_8(ADDRESS_68K(address));
+
+}
+
+INLINE uint m68ki_read_16(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+ 
+ 	if (ADDRESS_68K(address) <  0x800000) return FETCH16ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH16RAM(ADDRESS_68K(address));
+	return m68k_read_memory_16(ADDRESS_68K(address));
+
+}
+
+INLINE uint m68ki_read_32(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+	if (ADDRESS_68K(address) <  0x800000) return FETCH32ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH32RAM(ADDRESS_68K(address));
+	return m68k_read_memory_32(ADDRESS_68K(address));
+}
+
+INLINE void m68ki_write_8(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE8RAM(ADDRESS_68K(address), value);
+        } else
+        m68k_write_memory_8(ADDRESS_68K(address), value);
+}
+
+INLINE void m68ki_write_16(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE16RAM(ADDRESS_68K(address), value);
+        } else
+	m68k_write_memory_16(ADDRESS_68K(address), value);
+}
+
+INLINE void m68ki_write_32(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE32RAM(ADDRESS_68K(address), value);
+        } else
+	m68k_write_memory_32(ADDRESS_68K(address), value);
+}
+
+
+#if 0
+INLINE uint m68ki_read_8(uint address)
+{
+  cpu_memory_map *temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+  if (temp->read8) val = (*temp->read8)(ADDRESS_68K(address));
+  else val = READ_BYTE(temp->base, (address) & 0xffff);
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 1, address, val);
+#endif
+
+  return val;
+}
+
+INLINE uint m68ki_read_16(uint address)
+{
+  cpu_memory_map *temp;
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_READ, FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->read16) val = (*temp->read16)(ADDRESS_68K(address));
+  else val = *(uint16 *)(temp->base + ((address) & 0xffff));
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 2, address, val);
+#endif
+
+  return val;
+}
+
+INLINE uint m68ki_read_32(uint address)
+{
+  cpu_memory_map *temp;
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_READ, FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->read16) val = ((*temp->read16)(ADDRESS_68K(address)) << 16) | ((*temp->read16)(ADDRESS_68K(address + 2)));
+  else val = m68k_read_immediate_32(address);
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 4, address, val);
+#endif
+
+  return val;
+}
+
+INLINE void m68ki_write_8(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 1, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write8) (*temp->write8)(ADDRESS_68K(address),value);
+  else WRITE_BYTE(temp->base, (address) & 0xffff, value);
+}
+
+INLINE void m68ki_write_16(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_WRITE, FLAG_S | FUNCTION_CODE_USER_DATA); /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 2, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address),value);
+  else *(uint16 *)(temp->base + ((address) & 0xffff)) = value;
+}
+
+INLINE void m68ki_write_32(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_WRITE, FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 4, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address),value>>16);
+  else *(uint16 *)(temp->base + ((address) & 0xffff)) = value >> 16;
+
+  temp = &m68ki_cpu.memory_map[((address + 2)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address+2),value&0xffff);
+  else *(uint16 *)(temp->base + ((address + 2) & 0xffff)) = value;
+}
+#endif
+
+/* --------------------- Effective Address Calculation -------------------- */
+
+/* The program counter relative addressing modes cause operands to be
+ * retrieved from program space, not data space.
+ */
+INLINE uint m68ki_get_ea_pcdi(void)
+{
+  uint old_pc = REG_PC;
+  m68ki_use_program_space() /* auto-disable */
+  return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+}
+
+
+INLINE uint m68ki_get_ea_pcix(void)
+{
+  m68ki_use_program_space() /* auto-disable */
+  return m68ki_get_ea_ix(REG_PC);
+}
+
+/* Indexed addressing modes are encoded as follows:
+ *
+ * Base instruction format:
+ * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+ * x x x x x x x x x x | 1 1 0 | BASE REGISTER      (An)
+ *
+ * Base instruction format for destination EA in move instructions:
+ * F E D C | B A 9    | 8 7 6 | 5 4 3 2 1 0
+ * x x x x | BASE REG | 1 1 0 | X X X X X X       (An)
+ *
+ * Brief extension format:
+ *  F  |  E D C   |  B  |  A 9  | 8 | 7 6 5 4 3 2 1 0
+ * D/A | REGISTER | W/L | SCALE | 0 |  DISPLACEMENT
+ *
+ * Full extension format:
+ *  F     E D C      B     A 9    8   7    6    5 4       3   2 1 0
+ * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS
+ * BASE DISPLACEMENT (0, 16, 32 bit)                (bd)
+ * OUTER DISPLACEMENT (0, 16, 32 bit)               (od)
+ *
+ * D/A:     0 = Dn, 1 = An                          (Xn)
+ * W/L:     0 = W (sign extend), 1 = L              (.SIZE)
+ * SCALE:   00=1, 01=2, 10=4, 11=8                  (*SCALE)
+ * BS:      0=add base reg, 1=suppress base reg     (An suppressed)
+ * IS:      0=add index, 1=suppress index           (Xn suppressed)
+ * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long  (size of bd)
+ *
+ * IS I/IS Operation
+ * 0  000  No Memory Indirect
+ * 0  001  indir prex with null outer
+ * 0  010  indir prex with word outer
+ * 0  011  indir prex with long outer
+ * 0  100  reserved
+ * 0  101  indir postx with null outer
+ * 0  110  indir postx with word outer
+ * 0  111  indir postx with long outer
+ * 1  000  no memory indirect
+ * 1  001  mem indir with null outer
+ * 1  010  mem indir with word outer
+ * 1  011  mem indir with long outer
+ * 1  100-111  reserved
+ */
+INLINE uint m68ki_get_ea_ix(uint An)
+{
+  /* An = base register */
+  uint extension = m68ki_read_imm_16();
+
+  uint Xn = 0;                        /* Index register */
+
+  /* Calculate index */
+  Xn = REG_DA[extension>>12];     /* Xn */
+  if(!BIT_B(extension))           /* W/L */
+    Xn = MAKE_INT_16(Xn);
+
+  /* Add base register and displacement and return */
+  return An + Xn + MAKE_INT_8(extension);
+}
+
+
+/* Fetch operands */
+INLINE uint OPER_AY_AI_8(void)  {uint ea = EA_AY_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PI_8(void)  {uint ea = EA_AY_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PD_8(void)  {uint ea = EA_AY_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_DI_8(void)  {uint ea = EA_AY_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_IX_8(void)  {uint ea = EA_AY_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_AX_AI_8(void)  {uint ea = EA_AX_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PI_8(void)  {uint ea = EA_AX_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PD_8(void)  {uint ea = EA_AX_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_DI_8(void)  {uint ea = EA_AX_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_IX_8(void)  {uint ea = EA_AX_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_A7_PI_8(void)  {uint ea = EA_A7_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_A7_PD_8(void)  {uint ea = EA_A7_PD_8();  return m68ki_read_8(ea); }
+
+INLINE uint OPER_AW_8(void)     {uint ea = EA_AW_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AW_16(void)    {uint ea = EA_AW_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AW_32(void)    {uint ea = EA_AW_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_AL_8(void)     {uint ea = EA_AL_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AL_16(void)    {uint ea = EA_AL_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AL_32(void)    {uint ea = EA_AL_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_PCDI_8(void)   {uint ea = EA_PCDI_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCDI_16(void)  {uint ea = EA_PCDI_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCDI_32(void)  {uint ea = EA_PCDI_32();  return m68ki_read_pcrel_32(ea);}
+INLINE uint OPER_PCIX_8(void)   {uint ea = EA_PCIX_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCIX_16(void)  {uint ea = EA_PCIX_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCIX_32(void)  {uint ea = EA_PCIX_32();  return m68ki_read_pcrel_32(ea);}
+
+
+
+/* ---------------------------- Stack Functions --------------------------- */
+
+/* Push/pull data from the stack */
+INLINE void m68ki_push_16(uint value)
+{
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+  m68ki_write_16(REG_SP, value);
+}
+
+INLINE void m68ki_push_32(uint value)
+{
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+  m68ki_write_32(REG_SP, value);
+}
+
+INLINE uint m68ki_pull_16(void)
+{
+  uint sp = REG_SP;
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+  return m68ki_read_16(sp);
+}
+
+INLINE uint m68ki_pull_32(void)
+{
+  uint sp = REG_SP;
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+  return m68ki_read_32(sp);
+}
+
+
+
+/* ----------------------------- Program Flow ----------------------------- */
+
+/* Jump to a new program location or vector.
+ * These functions will also call the pc_changed callback if it was enabled
+ * in m68kconf.h.
+ */
+INLINE void m68ki_jump(uint new_pc)
+{
+  REG_PC = new_pc;
+}
+
+INLINE void m68ki_jump_vector(uint vector)
+{
+  m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+  REG_PC = m68ki_read_32(vector<<2);
+}
+
+
+/* Branch to a new memory location.
+ * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h.
+ * So far I've found no problems with not calling pc_changed for 8 or 16
+ * bit branches.
+ */
+INLINE void m68ki_branch_8(uint offset)
+{
+  REG_PC += MAKE_INT_8(offset);
+}
+
+INLINE void m68ki_branch_16(uint offset)
+{
+  REG_PC += MAKE_INT_16(offset);
+}
+
+INLINE void m68ki_branch_32(uint offset)
+{
+  REG_PC += offset;
+}
+
+
+
+/* ---------------------------- Status Register --------------------------- */
+
+/* Set the S flag and change the active stack pointer.
+ * Note that value MUST be 4 or 0.
+ */
+INLINE void m68ki_set_s_flag(uint value)
+{
+  /* Backup the old stack pointer */
+  REG_SP_BASE[FLAG_S] = REG_SP;
+  /* Set the S flag */
+  FLAG_S = value;
+  /* Set the new stack pointer */
+  REG_SP = REG_SP_BASE[FLAG_S];
+}
+
+
+/* Set the condition code register */
+INLINE void m68ki_set_ccr(uint value)
+{
+  FLAG_X = BIT_4(value)  << 4;
+  FLAG_N = BIT_3(value)  << 4;
+  FLAG_Z = !BIT_2(value);
+  FLAG_V = BIT_1(value)  << 6;
+  FLAG_C = BIT_0(value)  << 8;
+}
+
+
+/* Set the status register and check for interrupts */
+INLINE void m68ki_set_sr(uint value)
+{
+  /* Set the status register */
+  FLAG_T1 = BIT_F(value);
+  FLAG_INT_MASK = value & 0x0700;
+  m68ki_set_ccr(value);
+  m68ki_set_s_flag((value >> 11) & 4);
+
+  /* Check current IRQ status */
+  m68ki_check_interrupts();
+}
+
+
+/* ------------------------- Exception Processing ------------------------- */
+
+/* Initiate exception processing */
+INLINE uint m68ki_init_exception(void)
+{
+  /* Save the old status register */
+  uint sr = m68ki_get_sr();
+
+  /* Turn off trace flag, clear pending traces */
+  FLAG_T1 = 0;
+  m68ki_clear_trace()
+
+  /* Enter supervisor mode */
+  m68ki_set_s_flag(SFLAG_SET);
+
+  return sr;
+}
+
+/* 3 word stack frame (68000 only) */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr)
+{
+  m68ki_push_32(pc);
+  m68ki_push_16(sr);
+}
+
+#if M68K_EMULATE_ADDRESS_ERROR
+/* Bus error stack frame (68000 only).
+ */
+INLINE void m68ki_stack_frame_buserr(uint sr)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_push_16(sr);
+  m68ki_push_16(REG_IR);
+  m68ki_push_32(m68ki_cpu.aerr_address);  /* access address */
+  /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC
+     * R/W  0 = write, 1 = read
+     * I/N  0 = instruction, 1 = not
+     * FC   3-bit function code
+     */
+  m68ki_push_16(m68ki_cpu.aerr_write_mode | CPU_INSTR_MODE | m68ki_cpu.aerr_fc);
+}
+#endif
+
+/* Used for Group 2 exceptions.
+ */
+INLINE void m68ki_exception_trap(uint vector)
+{
+  uint sr = m68ki_init_exception();
+
+  m68ki_stack_frame_3word(REG_PC, sr);
+
+  m68ki_jump_vector(vector);
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
+INLINE void m68ki_exception_trapN(uint vector)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC, sr);
+  m68ki_jump_vector(vector);
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+#if M68K_EMULATE_TRACE
+/* Exception for trace mode */
+INLINE void m68ki_exception_trace(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC, sr);
+  m68ki_jump_vector(EXCEPTION_TRACE);
+
+  /* Trace nullifies a STOP instruction */
+  CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]);
+}
+#endif
+
+/* Exception for privilege violation */
+static void m68ki_exception_privilege_violation(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for A-Line instructions */
+INLINE void m68ki_exception_1010(void)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_1010);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for F-Line instructions */
+INLINE void m68ki_exception_1111(void)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_1111);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for illegal instructions */
+INLINE void m68ki_exception_illegal(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+
+#if M68K_EMULATE_ADDRESS_ERROR
+/* Exception for address error */
+INLINE void m68ki_exception_address_error(void)
+{
+  uint sr = m68ki_init_exception();
+
+  /* If we were processing a bus error, address error, or reset,
+     * this is a catastrophic failure.
+     * Halt the CPU
+     */
+  if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET)
+  {
+    CPU_STOPPED = STOP_LEVEL_HALT;
+    SET_CYCLES(m68ki_cpu.cycle_end - CYC_INSTRUCTION[REG_IR]);
+    return;
+  }
+  CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+
+  /* Note: This is implemented for 68000 only! */
+  m68ki_stack_frame_buserr(sr);
+
+  m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR] - CYC_INSTRUCTION[REG_IR]);
+}
+#endif
+
+/* Service an interrupt request and start exception processing */
+INLINE void m68ki_exception_interrupt(uint int_level)
+{
+  uint vector, sr, new_pc;
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  /* Turn off the stopped state */
+  CPU_STOPPED &= STOP_LEVEL_HALT;
+
+  /* If we are halted, don't do anything */
+  if(CPU_STOPPED)
+    return;
+
+  /* Always use the autovectors. */
+  vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
+
+  /* Start exception processing */
+  sr = m68ki_init_exception();
+
+  /* Set the interrupt mask to the level of the one being serviced */
+  FLAG_INT_MASK = int_level<<8;
+
+  /* Acknowledge the interrupt */
+  m68ki_int_ack(int_level);
+
+  /* Get the new PC */
+  m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+  new_pc = m68ki_read_32(vector<<2);
+
+  /* If vector is uninitialized, call the uninitialized interrupt vector */
+  if(new_pc == 0)
+    new_pc = m68ki_read_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2));
+
+  /* Generate a stack frame */
+  m68ki_stack_frame_3word(REG_PC, sr);
+
+  m68ki_jump(new_pc);
+
+  /* Update cycle count now */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* ASG: Check for interrupts */
+INLINE void m68ki_check_interrupts(void)
+{
+  if(CPU_INT_LEVEL > FLAG_INT_MASK)
+    m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCPU__HEADER */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles.h
new file mode 100755
index 0000000..7207fde
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles.h
@@ -0,0 +1,3839 @@
+static unsigned char m68ki_cycles[] =
+{
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,  10*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  16*7,  20*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,   0*7,   0*7,   4*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    0*7,   4*7,   4*7,  20*7,   0*7,  16*7,   4*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  18*7,  20*7,  18*7,  22*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  10*7,  12*7,  10*7,  14*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    };
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles_full.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles_full.h
new file mode 100755
index 0000000..d49a776
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_cycles_full.h
@@ -0,0 +1,4099 @@
+static const unsigned char m68ki_cycles[0x10000] =
+{
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,  10*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
+   24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  22*7,  26*7,  22*7,  24*7,  18*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  16*7,  20*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,   0*7,   0*7,   4*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    0*7,   4*7,   4*7,  20*7,   0*7,  16*7,   4*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  18*7,  20*7,  18*7,  22*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  10*7,  12*7,  10*7,  14*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+};
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table.h
new file mode 100755
index 0000000..e79f7fa
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table.h
@@ -0,0 +1,7675 @@
+static void  (* const m68ki_instruction_jump_table[])(void) =
+{
+  m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, 
+  m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi7, 
+  m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd7, 
+  m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, 
+  m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, 
+  m68k_op_ori_8_aw, m68k_op_ori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, 
+  m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, 
+  m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, 
+  m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, 
+  m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, 
+  m68k_op_ori_16_aw, m68k_op_ori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, 
+  m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, 
+  m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, 
+  m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, 
+  m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, 
+  m68k_op_ori_32_aw, m68k_op_ori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, 
+  m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi7, 
+  m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd7, 
+  m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, 
+  m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, 
+  m68k_op_andi_8_aw, m68k_op_andi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, 
+  m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, 
+  m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, 
+  m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, 
+  m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, 
+  m68k_op_andi_16_aw, m68k_op_andi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, 
+  m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, 
+  m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, 
+  m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, 
+  m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, 
+  m68k_op_andi_32_aw, m68k_op_andi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, 
+  m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi7, 
+  m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd7, 
+  m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, 
+  m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, 
+  m68k_op_subi_8_aw, m68k_op_subi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, 
+  m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, 
+  m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, 
+  m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, 
+  m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, 
+  m68k_op_subi_16_aw, m68k_op_subi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, 
+  m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, 
+  m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, 
+  m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, 
+  m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, 
+  m68k_op_subi_32_aw, m68k_op_subi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, 
+  m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi7, 
+  m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd7, 
+  m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, 
+  m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, 
+  m68k_op_addi_8_aw, m68k_op_addi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, 
+  m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, 
+  m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, 
+  m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, 
+  m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, 
+  m68k_op_addi_16_aw, m68k_op_addi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, 
+  m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, 
+  m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, 
+  m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, 
+  m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, 
+  m68k_op_addi_32_aw, m68k_op_addi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, 
+  m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi7, 
+  m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd7, 
+  m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, 
+  m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, 
+  m68k_op_btst_8_s_aw, m68k_op_btst_8_s_al, m68k_op_btst_8_s_pcdi, m68k_op_btst_8_s_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, 
+  m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi7, 
+  m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd7, 
+  m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, 
+  m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, 
+  m68k_op_bchg_8_s_aw, m68k_op_bchg_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, 
+  m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi7, 
+  m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd7, 
+  m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, 
+  m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, 
+  m68k_op_bclr_8_s_aw, m68k_op_bclr_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, 
+  m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi7, 
+  m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd7, 
+  m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, 
+  m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, 
+  m68k_op_bset_8_s_aw, m68k_op_bset_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, 
+  m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi7, 
+  m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd7, 
+  m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, 
+  m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, 
+  m68k_op_eori_8_aw, m68k_op_eori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, 
+  m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, 
+  m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, 
+  m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, 
+  m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, 
+  m68k_op_eori_16_aw, m68k_op_eori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, 
+  m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, 
+  m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, 
+  m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, 
+  m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, 
+  m68k_op_eori_32_aw, m68k_op_eori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, 
+  m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi7, 
+  m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd7, 
+  m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, 
+  m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, 
+  m68k_op_cmpi_8_aw, m68k_op_cmpi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, 
+  m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, 
+  m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, 
+  m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, 
+  m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, 
+  m68k_op_cmpi_16_aw, m68k_op_cmpi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, 
+  m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, 
+  m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, 
+  m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, 
+  m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, 
+  m68k_op_cmpi_32_aw, m68k_op_cmpi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, 
+  m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi7, 
+  m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd7, 
+  m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, 
+  m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, 
+  m68k_op_move_8_aw_aw, m68k_op_move_8_aw_al, m68k_op_move_8_aw_pcdi, m68k_op_move_8_aw_pcix, m68k_op_move_8_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, 
+  m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi7, 
+  m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd7, 
+  m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, 
+  m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, 
+  m68k_op_move_8_al_aw, m68k_op_move_8_al_al, m68k_op_move_8_al_pcdi, m68k_op_move_8_al_pcix, m68k_op_move_8_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, 
+  m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi7, 
+  m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd7, 
+  m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, 
+  m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, 
+  m68k_op_move_8_pi7_aw, m68k_op_move_8_pi7_al, m68k_op_move_8_pi7_pcdi, m68k_op_move_8_pi7_pcix, m68k_op_move_8_pi7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, 
+  m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi7, 
+  m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd7, 
+  m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, 
+  m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, 
+  m68k_op_move_8_pd7_aw, m68k_op_move_8_pd7_al, m68k_op_move_8_pd7_pcdi, m68k_op_move_8_pd7_pcix, m68k_op_move_8_pd7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, 
+  m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, 
+  m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, 
+  m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, 
+  m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, 
+  m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, 
+  m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, 
+  m68k_op_move_32_aw_aw, m68k_op_move_32_aw_al, m68k_op_move_32_aw_pcdi, m68k_op_move_32_aw_pcix, m68k_op_move_32_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, 
+  m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, 
+  m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, 
+  m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, 
+  m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, 
+  m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, 
+  m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, 
+  m68k_op_move_32_al_aw, m68k_op_move_32_al_al, m68k_op_move_32_al_pcdi, m68k_op_move_32_al_pcix, m68k_op_move_32_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, 
+  m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, 
+  m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, 
+  m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, 
+  m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, 
+  m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, 
+  m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, 
+  m68k_op_move_16_aw_aw, m68k_op_move_16_aw_al, m68k_op_move_16_aw_pcdi, m68k_op_move_16_aw_pcix, m68k_op_move_16_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, 
+  m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, 
+  m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, 
+  m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, 
+  m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, 
+  m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, 
+  m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, 
+  m68k_op_move_16_al_aw, m68k_op_move_16_al_al, m68k_op_move_16_al_pcdi, m68k_op_move_16_al_pcix, m68k_op_move_16_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, 
+  m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi7, 
+  m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd7, 
+  m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, 
+  m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, 
+  m68k_op_negx_8_aw, m68k_op_negx_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, 
+  m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, 
+  m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, 
+  m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, 
+  m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, 
+  m68k_op_negx_16_aw, m68k_op_negx_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, 
+  m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, 
+  m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, 
+  m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, 
+  m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, 
+  m68k_op_negx_32_aw, m68k_op_negx_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, 
+  m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, 
+  m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, 
+  m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, 
+  m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, 
+  m68k_op_move_16_frs_aw, m68k_op_move_16_frs_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, 
+  m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi7, 
+  m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd7, 
+  m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, 
+  m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, 
+  m68k_op_clr_8_aw, m68k_op_clr_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, 
+  m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, 
+  m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, 
+  m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, 
+  m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, 
+  m68k_op_clr_16_aw, m68k_op_clr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, 
+  m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, 
+  m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, 
+  m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, 
+  m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, 
+  m68k_op_clr_32_aw, m68k_op_clr_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, 
+  m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi7, 
+  m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd7, 
+  m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, 
+  m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, 
+  m68k_op_neg_8_aw, m68k_op_neg_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, 
+  m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, 
+  m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, 
+  m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, 
+  m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, 
+  m68k_op_neg_16_aw, m68k_op_neg_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, 
+  m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, 
+  m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, 
+  m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, 
+  m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, 
+  m68k_op_neg_32_aw, m68k_op_neg_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, 
+  m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, 
+  m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, 
+  m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, 
+  m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, 
+  m68k_op_move_16_toc_aw, m68k_op_move_16_toc_al, m68k_op_move_16_toc_pcdi, m68k_op_move_16_toc_pcix, m68k_op_move_16_toc_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, 
+  m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi7, 
+  m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd7, 
+  m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, 
+  m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, 
+  m68k_op_not_8_aw, m68k_op_not_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, 
+  m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, 
+  m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, 
+  m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, 
+  m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, 
+  m68k_op_not_16_aw, m68k_op_not_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, 
+  m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, 
+  m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, 
+  m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, 
+  m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, 
+  m68k_op_not_32_aw, m68k_op_not_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, 
+  m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, 
+  m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, 
+  m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, 
+  m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, 
+  m68k_op_move_16_tos_aw, m68k_op_move_16_tos_al, m68k_op_move_16_tos_pcdi, m68k_op_move_16_tos_pcix, m68k_op_move_16_tos_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, 
+  m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi7, 
+  m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd7, 
+  m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, 
+  m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, 
+  m68k_op_nbcd_8_aw, m68k_op_nbcd_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, 
+  m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, 
+  m68k_op_pea_32_aw, m68k_op_pea_32_al, m68k_op_pea_32_pcdi, m68k_op_pea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, 
+  m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, 
+  m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, 
+  m68k_op_movem_16_re_aw, m68k_op_movem_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, 
+  m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, 
+  m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, 
+  m68k_op_movem_32_re_aw, m68k_op_movem_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, 
+  m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi7, 
+  m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd7, 
+  m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, 
+  m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, 
+  m68k_op_tst_8_aw, m68k_op_tst_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, 
+  m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, 
+  m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, 
+  m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, 
+  m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, 
+  m68k_op_tst_16_aw, m68k_op_tst_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, 
+  m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, 
+  m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, 
+  m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, 
+  m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, 
+  m68k_op_tst_32_aw, m68k_op_tst_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, 
+  m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi7, 
+  m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd7, 
+  m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, 
+  m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, 
+  m68k_op_tas_8_aw, m68k_op_tas_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, 
+  m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, 
+  m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, 
+  m68k_op_movem_16_er_aw, m68k_op_movem_16_er_al, m68k_op_movem_16_er_pcdi, m68k_op_movem_16_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, 
+  m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, 
+  m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, 
+  m68k_op_movem_32_er_aw, m68k_op_movem_32_er_al, m68k_op_movem_32_er_pcdi, m68k_op_movem_32_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16_a7, 
+  m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32_a7, 
+  m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, 
+  m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, 
+  m68k_op_reset, m68k_op_nop, m68k_op_stop, m68k_op_rte_32, m68k_op_illegal, m68k_op_rts_32, m68k_op_trapv, m68k_op_rtr_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, 
+  m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, 
+  m68k_op_jsr_32_aw, m68k_op_jsr_32_al, m68k_op_jsr_32_pcdi, m68k_op_jsr_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, 
+  m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, 
+  m68k_op_jmp_32_aw, m68k_op_jmp_32_al, m68k_op_jmp_32_pcdi, m68k_op_jmp_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, 
+  m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, 
+  m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, 
+  m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi7, 
+  m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd7, 
+  m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, 
+  m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, 
+  m68k_op_st_8_aw, m68k_op_st_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, 
+  m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, 
+  m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, 
+  m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi7, 
+  m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd7, 
+  m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, 
+  m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, 
+  m68k_op_sf_8_aw, m68k_op_sf_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, 
+  m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, 
+  m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, 
+  m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi7, 
+  m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd7, 
+  m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, 
+  m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, 
+  m68k_op_shi_8_aw, m68k_op_shi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, 
+  m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, 
+  m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, 
+  m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi7, 
+  m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd7, 
+  m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, 
+  m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, 
+  m68k_op_sls_8_aw, m68k_op_sls_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, 
+  m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, 
+  m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, 
+  m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi7, 
+  m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd7, 
+  m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, 
+  m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, 
+  m68k_op_scc_8_aw, m68k_op_scc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, 
+  m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, 
+  m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, 
+  m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi7, 
+  m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd7, 
+  m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, 
+  m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, 
+  m68k_op_scs_8_aw, m68k_op_scs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, 
+  m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, 
+  m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, 
+  m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi7, 
+  m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd7, 
+  m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, 
+  m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, 
+  m68k_op_sne_8_aw, m68k_op_sne_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, 
+  m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, 
+  m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, 
+  m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi7, 
+  m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd7, 
+  m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, 
+  m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, 
+  m68k_op_seq_8_aw, m68k_op_seq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, 
+  m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, 
+  m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, 
+  m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi7, 
+  m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd7, 
+  m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, 
+  m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, 
+  m68k_op_svc_8_aw, m68k_op_svc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, 
+  m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, 
+  m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, 
+  m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi7, 
+  m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd7, 
+  m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, 
+  m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, 
+  m68k_op_svs_8_aw, m68k_op_svs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, 
+  m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, 
+  m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, 
+  m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi7, 
+  m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd7, 
+  m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, 
+  m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, 
+  m68k_op_spl_8_aw, m68k_op_spl_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, 
+  m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, 
+  m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, 
+  m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi7, 
+  m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd7, 
+  m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, 
+  m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, 
+  m68k_op_smi_8_aw, m68k_op_smi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, 
+  m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, 
+  m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, 
+  m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi7, 
+  m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd7, 
+  m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, 
+  m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, 
+  m68k_op_sge_8_aw, m68k_op_sge_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, 
+  m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, 
+  m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, 
+  m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi7, 
+  m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd7, 
+  m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, 
+  m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, 
+  m68k_op_slt_8_aw, m68k_op_slt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, 
+  m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, 
+  m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, 
+  m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi7, 
+  m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd7, 
+  m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, 
+  m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, 
+  m68k_op_sgt_8_aw, m68k_op_sgt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, 
+  m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, 
+  m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, 
+  m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi7, 
+  m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd7, 
+  m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, 
+  m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, 
+  m68k_op_sle_8_aw, m68k_op_sle_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bra_16, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_32, 
+  m68k_op_bsr_16, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_32, 
+  m68k_op_bhi_16, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_32, 
+  m68k_op_bls_16, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_32, 
+  m68k_op_bcc_16, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_32, 
+  m68k_op_bcs_16, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_32, 
+  m68k_op_bne_16, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_32, 
+  m68k_op_beq_16, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_32, 
+  m68k_op_bvc_16, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_32, 
+  m68k_op_bvs_16, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_32, 
+  m68k_op_bpl_16, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_32, 
+  m68k_op_bmi_16, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_32, 
+  m68k_op_bge_16, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_32, 
+  m68k_op_blt_16, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_32, 
+  m68k_op_bgt_16, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_32, 
+  m68k_op_ble_16, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_axy7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_axy7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_axy7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_axy7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_axy7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, 
+  m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, 
+  m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, 
+  m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, 
+  m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, 
+  m68k_op_asr_16_aw, m68k_op_asr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, 
+  m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, 
+  m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, 
+  m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, 
+  m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, 
+  m68k_op_asl_16_aw, m68k_op_asl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, 
+  m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, 
+  m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, 
+  m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, 
+  m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, 
+  m68k_op_lsr_16_aw, m68k_op_lsr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, 
+  m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, 
+  m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, 
+  m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, 
+  m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, 
+  m68k_op_lsl_16_aw, m68k_op_lsl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, 
+  m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, 
+  m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, 
+  m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, 
+  m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, 
+  m68k_op_roxr_16_aw, m68k_op_roxr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, 
+  m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, 
+  m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, 
+  m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, 
+  m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, 
+  m68k_op_roxl_16_aw, m68k_op_roxl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, 
+  m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, 
+  m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, 
+  m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, 
+  m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, 
+  m68k_op_ror_16_aw, m68k_op_ror_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, 
+  m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, 
+  m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, 
+  m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, 
+  m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, 
+  m68k_op_rol_16_aw, m68k_op_rol_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  };
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h
new file mode 100755
index 0000000..eac71fe
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h
@@ -0,0 +1,8195 @@
+static void (* const m68ki_instruction_jump_table[0x10000])(void) =
+{
+  m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, 
+  m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi7, 
+  m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd7, 
+  m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, 
+  m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, 
+  m68k_op_ori_8_aw, m68k_op_ori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, 
+  m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, 
+  m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, 
+  m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, 
+  m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, 
+  m68k_op_ori_16_aw, m68k_op_ori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, 
+  m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, 
+  m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, 
+  m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, 
+  m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, 
+  m68k_op_ori_32_aw, m68k_op_ori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, 
+  m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi7, 
+  m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd7, 
+  m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, 
+  m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, 
+  m68k_op_andi_8_aw, m68k_op_andi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, 
+  m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, 
+  m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, 
+  m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, 
+  m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, 
+  m68k_op_andi_16_aw, m68k_op_andi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, 
+  m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, 
+  m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, 
+  m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, 
+  m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, 
+  m68k_op_andi_32_aw, m68k_op_andi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, 
+  m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi7, 
+  m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd7, 
+  m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, 
+  m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, 
+  m68k_op_subi_8_aw, m68k_op_subi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, 
+  m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, 
+  m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, 
+  m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, 
+  m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, 
+  m68k_op_subi_16_aw, m68k_op_subi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, 
+  m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, 
+  m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, 
+  m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, 
+  m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, 
+  m68k_op_subi_32_aw, m68k_op_subi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, 
+  m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi7, 
+  m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd7, 
+  m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, 
+  m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, 
+  m68k_op_addi_8_aw, m68k_op_addi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, 
+  m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, 
+  m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, 
+  m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, 
+  m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, 
+  m68k_op_addi_16_aw, m68k_op_addi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, 
+  m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, 
+  m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, 
+  m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, 
+  m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, 
+  m68k_op_addi_32_aw, m68k_op_addi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, 
+  m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi7, 
+  m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd7, 
+  m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, 
+  m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, 
+  m68k_op_btst_8_s_aw, m68k_op_btst_8_s_al, m68k_op_btst_8_s_pcdi, m68k_op_btst_8_s_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, 
+  m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi7, 
+  m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd7, 
+  m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, 
+  m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, 
+  m68k_op_bchg_8_s_aw, m68k_op_bchg_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, 
+  m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi7, 
+  m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd7, 
+  m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, 
+  m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, 
+  m68k_op_bclr_8_s_aw, m68k_op_bclr_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, 
+  m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi7, 
+  m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd7, 
+  m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, 
+  m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, 
+  m68k_op_bset_8_s_aw, m68k_op_bset_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, 
+  m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi7, 
+  m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd7, 
+  m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, 
+  m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, 
+  m68k_op_eori_8_aw, m68k_op_eori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, 
+  m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, 
+  m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, 
+  m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, 
+  m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, 
+  m68k_op_eori_16_aw, m68k_op_eori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, 
+  m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, 
+  m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, 
+  m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, 
+  m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, 
+  m68k_op_eori_32_aw, m68k_op_eori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, 
+  m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi7, 
+  m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd7, 
+  m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, 
+  m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, 
+  m68k_op_cmpi_8_aw, m68k_op_cmpi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, 
+  m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, 
+  m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, 
+  m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, 
+  m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, 
+  m68k_op_cmpi_16_aw, m68k_op_cmpi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, 
+  m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, 
+  m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, 
+  m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, 
+  m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, 
+  m68k_op_cmpi_32_aw, m68k_op_cmpi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, 
+  m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi7, 
+  m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd7, 
+  m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, 
+  m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, 
+  m68k_op_move_8_aw_aw, m68k_op_move_8_aw_al, m68k_op_move_8_aw_pcdi, m68k_op_move_8_aw_pcix, m68k_op_move_8_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, 
+  m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi7, 
+  m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd7, 
+  m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, 
+  m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, 
+  m68k_op_move_8_al_aw, m68k_op_move_8_al_al, m68k_op_move_8_al_pcdi, m68k_op_move_8_al_pcix, m68k_op_move_8_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, 
+  m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi7, 
+  m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd7, 
+  m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, 
+  m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, 
+  m68k_op_move_8_pi7_aw, m68k_op_move_8_pi7_al, m68k_op_move_8_pi7_pcdi, m68k_op_move_8_pi7_pcix, m68k_op_move_8_pi7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, 
+  m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi7, 
+  m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd7, 
+  m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, 
+  m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, 
+  m68k_op_move_8_pd7_aw, m68k_op_move_8_pd7_al, m68k_op_move_8_pd7_pcdi, m68k_op_move_8_pd7_pcix, m68k_op_move_8_pd7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, 
+  m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, 
+  m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, 
+  m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, 
+  m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, 
+  m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, 
+  m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, 
+  m68k_op_move_32_aw_aw, m68k_op_move_32_aw_al, m68k_op_move_32_aw_pcdi, m68k_op_move_32_aw_pcix, m68k_op_move_32_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, 
+  m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, 
+  m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, 
+  m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, 
+  m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, 
+  m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, 
+  m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, 
+  m68k_op_move_32_al_aw, m68k_op_move_32_al_al, m68k_op_move_32_al_pcdi, m68k_op_move_32_al_pcix, m68k_op_move_32_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, 
+  m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, 
+  m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, 
+  m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, 
+  m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, 
+  m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, 
+  m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, 
+  m68k_op_move_16_aw_aw, m68k_op_move_16_aw_al, m68k_op_move_16_aw_pcdi, m68k_op_move_16_aw_pcix, m68k_op_move_16_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, 
+  m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, 
+  m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, 
+  m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, 
+  m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, 
+  m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, 
+  m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, 
+  m68k_op_move_16_al_aw, m68k_op_move_16_al_al, m68k_op_move_16_al_pcdi, m68k_op_move_16_al_pcix, m68k_op_move_16_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, 
+  m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi7, 
+  m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd7, 
+  m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, 
+  m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, 
+  m68k_op_negx_8_aw, m68k_op_negx_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, 
+  m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, 
+  m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, 
+  m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, 
+  m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, 
+  m68k_op_negx_16_aw, m68k_op_negx_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, 
+  m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, 
+  m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, 
+  m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, 
+  m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, 
+  m68k_op_negx_32_aw, m68k_op_negx_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, 
+  m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, 
+  m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, 
+  m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, 
+  m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, 
+  m68k_op_move_16_frs_aw, m68k_op_move_16_frs_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, 
+  m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi7, 
+  m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd7, 
+  m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, 
+  m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, 
+  m68k_op_clr_8_aw, m68k_op_clr_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, 
+  m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, 
+  m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, 
+  m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, 
+  m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, 
+  m68k_op_clr_16_aw, m68k_op_clr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, 
+  m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, 
+  m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, 
+  m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, 
+  m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, 
+  m68k_op_clr_32_aw, m68k_op_clr_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, 
+  m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi7, 
+  m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd7, 
+  m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, 
+  m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, 
+  m68k_op_neg_8_aw, m68k_op_neg_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, 
+  m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, 
+  m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, 
+  m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, 
+  m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, 
+  m68k_op_neg_16_aw, m68k_op_neg_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, 
+  m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, 
+  m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, 
+  m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, 
+  m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, 
+  m68k_op_neg_32_aw, m68k_op_neg_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, 
+  m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, 
+  m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, 
+  m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, 
+  m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, 
+  m68k_op_move_16_toc_aw, m68k_op_move_16_toc_al, m68k_op_move_16_toc_pcdi, m68k_op_move_16_toc_pcix, m68k_op_move_16_toc_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, 
+  m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi7, 
+  m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd7, 
+  m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, 
+  m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, 
+  m68k_op_not_8_aw, m68k_op_not_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, 
+  m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, 
+  m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, 
+  m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, 
+  m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, 
+  m68k_op_not_16_aw, m68k_op_not_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, 
+  m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, 
+  m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, 
+  m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, 
+  m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, 
+  m68k_op_not_32_aw, m68k_op_not_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, 
+  m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, 
+  m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, 
+  m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, 
+  m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, 
+  m68k_op_move_16_tos_aw, m68k_op_move_16_tos_al, m68k_op_move_16_tos_pcdi, m68k_op_move_16_tos_pcix, m68k_op_move_16_tos_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, 
+  m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi7, 
+  m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd7, 
+  m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, 
+  m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, 
+  m68k_op_nbcd_8_aw, m68k_op_nbcd_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, 
+  m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, 
+  m68k_op_pea_32_aw, m68k_op_pea_32_al, m68k_op_pea_32_pcdi, m68k_op_pea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, 
+  m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, 
+  m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, 
+  m68k_op_movem_16_re_aw, m68k_op_movem_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, 
+  m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, 
+  m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, 
+  m68k_op_movem_32_re_aw, m68k_op_movem_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, 
+  m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi7, 
+  m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd7, 
+  m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, 
+  m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, 
+  m68k_op_tst_8_aw, m68k_op_tst_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, 
+  m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, 
+  m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, 
+  m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, 
+  m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, 
+  m68k_op_tst_16_aw, m68k_op_tst_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, 
+  m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, 
+  m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, 
+  m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, 
+  m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, 
+  m68k_op_tst_32_aw, m68k_op_tst_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, 
+  m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi7, 
+  m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd7, 
+  m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, 
+  m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, 
+  m68k_op_tas_8_aw, m68k_op_tas_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, 
+  m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, 
+  m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, 
+  m68k_op_movem_16_er_aw, m68k_op_movem_16_er_al, m68k_op_movem_16_er_pcdi, m68k_op_movem_16_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, 
+  m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, 
+  m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, 
+  m68k_op_movem_32_er_aw, m68k_op_movem_32_er_al, m68k_op_movem_32_er_pcdi, m68k_op_movem_32_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16_a7, 
+  m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32_a7, 
+  m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, 
+  m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, 
+  m68k_op_reset, m68k_op_nop, m68k_op_stop, m68k_op_rte_32, m68k_op_illegal, m68k_op_rts_32, m68k_op_trapv, m68k_op_rtr_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, 
+  m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, 
+  m68k_op_jsr_32_aw, m68k_op_jsr_32_al, m68k_op_jsr_32_pcdi, m68k_op_jsr_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, 
+  m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, 
+  m68k_op_jmp_32_aw, m68k_op_jmp_32_al, m68k_op_jmp_32_pcdi, m68k_op_jmp_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, 
+  m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, 
+  m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, 
+  m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi7, 
+  m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd7, 
+  m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, 
+  m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, 
+  m68k_op_st_8_aw, m68k_op_st_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, 
+  m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, 
+  m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, 
+  m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi7, 
+  m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd7, 
+  m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, 
+  m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, 
+  m68k_op_sf_8_aw, m68k_op_sf_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, 
+  m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, 
+  m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, 
+  m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi7, 
+  m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd7, 
+  m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, 
+  m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, 
+  m68k_op_shi_8_aw, m68k_op_shi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, 
+  m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, 
+  m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, 
+  m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi7, 
+  m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd7, 
+  m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, 
+  m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, 
+  m68k_op_sls_8_aw, m68k_op_sls_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, 
+  m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, 
+  m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, 
+  m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi7, 
+  m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd7, 
+  m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, 
+  m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, 
+  m68k_op_scc_8_aw, m68k_op_scc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, 
+  m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, 
+  m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, 
+  m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi7, 
+  m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd7, 
+  m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, 
+  m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, 
+  m68k_op_scs_8_aw, m68k_op_scs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, 
+  m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, 
+  m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, 
+  m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi7, 
+  m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd7, 
+  m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, 
+  m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, 
+  m68k_op_sne_8_aw, m68k_op_sne_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, 
+  m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, 
+  m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, 
+  m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi7, 
+  m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd7, 
+  m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, 
+  m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, 
+  m68k_op_seq_8_aw, m68k_op_seq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, 
+  m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, 
+  m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, 
+  m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi7, 
+  m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd7, 
+  m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, 
+  m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, 
+  m68k_op_svc_8_aw, m68k_op_svc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, 
+  m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, 
+  m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, 
+  m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi7, 
+  m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd7, 
+  m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, 
+  m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, 
+  m68k_op_svs_8_aw, m68k_op_svs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, 
+  m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, 
+  m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, 
+  m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi7, 
+  m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd7, 
+  m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, 
+  m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, 
+  m68k_op_spl_8_aw, m68k_op_spl_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, 
+  m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, 
+  m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, 
+  m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi7, 
+  m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd7, 
+  m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, 
+  m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, 
+  m68k_op_smi_8_aw, m68k_op_smi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, 
+  m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, 
+  m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, 
+  m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi7, 
+  m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd7, 
+  m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, 
+  m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, 
+  m68k_op_sge_8_aw, m68k_op_sge_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, 
+  m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, 
+  m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, 
+  m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi7, 
+  m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd7, 
+  m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, 
+  m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, 
+  m68k_op_slt_8_aw, m68k_op_slt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, 
+  m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, 
+  m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, 
+  m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi7, 
+  m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd7, 
+  m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, 
+  m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, 
+  m68k_op_sgt_8_aw, m68k_op_sgt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, 
+  m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, 
+  m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, 
+  m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi7, 
+  m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd7, 
+  m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, 
+  m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, 
+  m68k_op_sle_8_aw, m68k_op_sle_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bra_16, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_32, 
+  m68k_op_bsr_16, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_32, 
+  m68k_op_bhi_16, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_32, 
+  m68k_op_bls_16, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_32, 
+  m68k_op_bcc_16, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_32, 
+  m68k_op_bcs_16, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_32, 
+  m68k_op_bne_16, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_32, 
+  m68k_op_beq_16, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_32, 
+  m68k_op_bvc_16, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_32, 
+  m68k_op_bvs_16, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_32, 
+  m68k_op_bpl_16, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_32, 
+  m68k_op_bmi_16, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_32, 
+  m68k_op_bge_16, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_32, 
+  m68k_op_blt_16, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_32, 
+  m68k_op_bgt_16, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_32, 
+  m68k_op_ble_16, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_axy7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_axy7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_axy7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_axy7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_axy7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, 
+  m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, 
+  m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, 
+  m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, 
+  m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, 
+  m68k_op_asr_16_aw, m68k_op_asr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, 
+  m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, 
+  m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, 
+  m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, 
+  m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, 
+  m68k_op_asl_16_aw, m68k_op_asl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, 
+  m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, 
+  m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, 
+  m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, 
+  m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, 
+  m68k_op_lsr_16_aw, m68k_op_lsr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, 
+  m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, 
+  m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, 
+  m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, 
+  m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, 
+  m68k_op_lsl_16_aw, m68k_op_lsl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, 
+  m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, 
+  m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, 
+  m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, 
+  m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, 
+  m68k_op_roxr_16_aw, m68k_op_roxr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, 
+  m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, 
+  m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, 
+  m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, 
+  m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, 
+  m68k_op_roxl_16_aw, m68k_op_roxl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, 
+  m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, 
+  m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, 
+  m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, 
+  m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, 
+  m68k_op_ror_16_aw, m68k_op_ror_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, 
+  m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, 
+  m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, 
+  m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, 
+  m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, 
+  m68k_op_rol_16_aw, m68k_op_rol_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+};
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kops.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kops.h
new file mode 100755
index 0000000..42f09be
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/m68kops.h
@@ -0,0 +1,25494 @@
+
+/* ======================================================================== */
+/* ============== CYCLE-ACCURATE DIV/MUL EXECUTION ======================== */
+/* ======================================================================== */
+
+INLINE void UseDivuCycles(uint32 dst, uint32 src)
+{
+  int i;
+
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* 16-bit divisor */
+  src <<= 16;
+
+  /* 16-bit dividend */
+  for (i=0; i<15; i++)
+  {
+    /* check if carry bit set  */
+    if ((sint32) dst < 0)
+    {
+      /* shift dividend and apply divisor */
+      dst <<= 1;
+      dst -= src;
+    }
+    else
+    {
+      /* shift dividend and add two cycles */
+      dst <<= 1;
+      mcycles += (2 * MUL);
+
+      if (dst >= src)
+      {
+        /* apply divisor and remove one cycle */
+        dst -= src;
+        mcycles -= 1 * MUL;
+      }
+    }
+  }
+
+  USE_CYCLES(mcycles << 1);
+}
+
+INLINE void UseDivsCycles(sint32 dst, sint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 6 * MUL;
+
+  /* negative dividend */
+  if (dst < 0) mcycles += 1 * MUL;
+
+  if ((abs(dst) >> 16) < abs(src))
+  {
+    int i;
+
+    /* absolute quotient */
+    uint32 quotient = abs(dst) / abs(src);
+
+    /* add default cycle time */
+    mcycles += (55 * MUL);
+
+    /* positive divisor */
+    if (src >= 0)
+    {
+      /* check dividend sign */
+      if (dst >= 0) mcycles -= 1 * MUL;
+      else mcycles += 1 * MUL;
+    }
+
+    /* check higher 15-bits of quotient */
+    for (i=0; i<15; i++)
+    {
+      quotient >>= 1;
+      if (!(quotient & 1)) mcycles += 1 * MUL;
+    }
+  }
+  else
+  {
+    /* absolute overflow */
+    mcycles += (2 * MUL);
+  }
+
+  USE_CYCLES(mcycles << 1);
+}
+
+INLINE void UseMuluCycles(uint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* count number of bits set to 1 */
+  while (src)
+  {
+    if (src & 1) mcycles += (2 * MUL);
+    src >>= 1;
+  }
+
+  /* 38 + 2*N */
+  USE_CYCLES(mcycles);
+}
+
+INLINE void UseMulsCycles(sint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* detect 01 or 10 patterns */
+  sint32 tmp = src << 1;
+  tmp = (tmp ^ src) & 0xFFFF;
+
+  /* count number of bits set to 1 */
+  while (tmp)
+  {
+    if (tmp & 1) mcycles += (2 * MUL);
+    tmp >>= 1;
+  }
+
+  /* 38 + 2*N */
+  USE_CYCLES(mcycles);
+}
+
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+static void __inline m68k_op_1010(void)
+{
+  m68ki_exception_1010();
+}
+
+#ifdef TABLES_FULL
+
+static void __inline m68k_op_1111(void)
+{
+  m68ki_exception_1111();
+}
+#endif
+
+static void __inline m68k_op_abcd_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_abcd_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_add_8_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pi7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pd7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = AY;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_adda_16_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
+}
+
+
+static void __inline m68k_op_adda_16_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
+}
+
+
+static void __inline m68k_op_adda_16_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AW_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AL_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_I_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_32_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
+}
+
+
+static void __inline m68k_op_adda_32_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
+}
+
+
+static void __inline m68k_op_adda_32_ai(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_AI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pi(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_PI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pd(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_PD_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_di(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_DI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_ix(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_IX_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_aw(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AW_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_al(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AL_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pcdi(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_PCDI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pcix(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_PCIX_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_i(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_I_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_addi_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_8_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pi7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pd7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_16_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+static void __inline m68k_op_addq_16_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_32_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+static void __inline m68k_op_addq_32_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addx_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_addx_16_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_addx_32_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_addx_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_16_mm(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint ea  = EA_AX_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_addx_32_mm(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint ea  = EA_AX_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_8_er_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_ai(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pi7(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pd(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pd7(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_di(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_ix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_aw(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_al(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pcdi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pcix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_i(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_ai(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pd(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_di(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_ix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_aw(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_al(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pcdi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pcix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_i(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_d(void)
+{
+  FLAG_Z = DX &= DY;
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_ai(void)
+{
+  FLAG_Z = DX &= OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pi(void)
+{
+  FLAG_Z = DX &= OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pd(void)
+{
+  FLAG_Z = DX &= OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_di(void)
+{
+  FLAG_Z = DX &= OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_ix(void)
+{
+  FLAG_Z = DX &= OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_aw(void)
+{
+  FLAG_Z = DX &= OPER_AW_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_al(void)
+{
+  FLAG_Z = DX &= OPER_AL_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pcdi(void)
+{
+  FLAG_Z = DX &= OPER_PCDI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pcix(void)
+{
+  FLAG_Z = DX &= OPER_PCIX_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_i(void)
+{
+  FLAG_Z = DX &= OPER_I_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_d(void)
+{
+  FLAG_Z = DY &= (OPER_I_32());
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
+}
+
+
+static void __inline m68k_op_andi_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() & src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_asr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_8(src))
+    res |= m68ki_shift_8_table[shift];
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_16(src))
+    res |= m68ki_shift_16_table[shift];
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_32(src))
+    res |= m68ki_shift_32_table[shift];
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 8)
+    {
+      if(GET_MSB_8(src))
+        res |= m68ki_shift_8_table[shift];
+
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+      FLAG_X = FLAG_C = src << (9-shift);
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_8(src))
+    {
+      *r_dst |= 0xff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 16)
+    {
+      if(GET_MSB_16(src))
+        res |= m68ki_shift_16_table[shift];
+
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_16(src))
+    {
+      *r_dst |= 0xffff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      if(GET_MSB_32(src))
+        res |= m68ki_shift_32_table[shift];
+
+      *r_dst = res;
+
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_32(src))
+    {
+      *r_dst = 0xffffffff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_X = FLAG_C = src << shift;
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  src &= m68ki_shift_8_table[shift + 1];
+  FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (8-shift);
+  src &= m68ki_shift_16_table[shift + 1];
+  FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+}
+
+
+static void __inline m68k_op_asl_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (24-shift);
+  src &= m68ki_shift_32_table[shift + 1];
+  FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+}
+
+
+static void __inline m68k_op_asl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_8_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_X = FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_16_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_32_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_bhi_8(void)
+{
+  if(COND_HI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bls_8(void)
+{
+  if(COND_LS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcc_8(void)
+{
+  if(COND_CC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcs_8(void)
+{
+  if(COND_CS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bne_8(void)
+{
+  if(COND_NE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_beq_8(void)
+{
+  if(COND_EQ())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvc_8(void)
+{
+  if(COND_VC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvs_8(void)
+{
+  if(COND_VS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bpl_8(void)
+{
+  if(COND_PL())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bmi_8(void)
+{
+  if(COND_MI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bge_8(void)
+{
+  if(COND_GE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_blt_8(void)
+{
+  if(COND_LT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bgt_8(void)
+{
+  if(COND_GT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_ble_8(void)
+{
+  if(COND_LE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bhi_16(void)
+{
+  if(COND_HI())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bls_16(void)
+{
+  if(COND_LS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bcc_16(void)
+{
+  if(COND_CC())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bcs_16(void)
+{
+  if(COND_CS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bne_16(void)
+{
+  if(COND_NE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_beq_16(void)
+{
+  if(COND_EQ())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bvc_16(void)
+{
+  if(COND_VC())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bvs_16(void)
+{
+  if(COND_VS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bpl_16(void)
+{
+  if(COND_PL())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bmi_16(void)
+{
+  if(COND_MI())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bge_16(void)
+{
+  if(COND_GE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_blt_16(void)
+{
+  if(COND_LT())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bgt_16(void)
+{
+  if(COND_GT())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_ble_16(void)
+{
+  if(COND_LE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bhi_32(void)
+{
+  if(COND_HI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bls_32(void)
+{
+  if(COND_LS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcc_32(void)
+{
+  if(COND_CC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcs_32(void)
+{
+  if(COND_CS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bne_32(void)
+{
+  if(COND_NE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_beq_32(void)
+{
+  if(COND_EQ())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvc_32(void)
+{
+  if(COND_VC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvs_32(void)
+{
+  if(COND_VS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bpl_32(void)
+{
+  if(COND_PL())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bmi_32(void)
+{
+  if(COND_MI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bge_32(void)
+{
+  if(COND_GE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_blt_32(void)
+{
+  if(COND_LT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bgt_32(void)
+{
+  if(COND_GT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_ble_32(void)
+{
+  if(COND_LE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bchg_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst ^= mask;
+}
+
+
+static void __inline m68k_op_bchg_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst ^= mask;
+}
+
+
+static void __inline m68k_op_bchg_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bclr_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst &= ~mask;
+}
+
+
+static void __inline m68k_op_bclr_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst &= ~mask;
+}
+
+
+static void __inline m68k_op_bclr_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bra_8(void)
+{
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bra_16(void)
+{
+  uint offset = OPER_I_16();
+  REG_PC -= 2;
+  m68ki_branch_16(offset);
+}
+
+
+static void __inline m68k_op_bra_32(void)
+{
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bset_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst |= mask;
+}
+
+
+static void __inline m68k_op_bset_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst |= mask;
+}
+
+
+static void __inline m68k_op_bset_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bsr_8(void)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bsr_16(void)
+{
+  uint offset = OPER_I_16();
+  m68ki_push_32(REG_PC);
+  REG_PC -= 2;
+  m68ki_branch_16(offset);
+}
+
+
+static void __inline m68k_op_bsr_32(void)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_btst_32_r_d(void)
+{
+  FLAG_Z = DY & (1 << (DX & 0x1f));
+}
+
+
+static void __inline m68k_op_btst_8_r_ai(void)
+{
+  FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pi(void)
+{
+  FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pi7(void)
+{
+  FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pd(void)
+{
+  FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pd7(void)
+{
+  FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_di(void)
+{
+  FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_ix(void)
+{
+  FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_aw(void)
+{
+  FLAG_Z = OPER_AW_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_al(void)
+{
+  FLAG_Z = OPER_AL_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pcdi(void)
+{
+  FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pcix(void)
+{
+  FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_i(void)
+{
+  FLAG_Z = OPER_I_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_32_s_d(void)
+{
+  FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+}
+
+
+static void __inline m68k_op_btst_8_s_ai(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_AI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pi(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_PI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pi7(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_A7_PI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pd(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_PD_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pd7(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_A7_PD_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_di(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_DI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_ix(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_IX_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_aw(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AW_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_al(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AL_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pcdi(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_PCDI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pcix(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_PCIX_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_chk_16_d(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(DY);
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_ai(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_AI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pi(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_PI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pd(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_PD_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_di(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_DI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_ix(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_IX_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_aw(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AW_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_al(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AL_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pcdi(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_PCDI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pcix(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_PCIX_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_i(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_I_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_clr_8_d(void)
+{
+  DY &= 0xffffff00;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_d(void)
+{
+  DY &= 0xffff0000;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_ai(void)
+{
+  m68ki_write_16(EA_AY_AI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_pi(void)
+{
+  m68ki_write_16(EA_AY_PI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_pd(void)
+{
+  m68ki_write_16(EA_AY_PD_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_di(void)
+{
+  m68ki_write_16(EA_AY_DI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_ix(void)
+{
+  m68ki_write_16(EA_AY_IX_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_aw(void)
+{
+  m68ki_write_16(EA_AW_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_al(void)
+{
+  m68ki_write_16(EA_AL_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_d(void)
+{
+  DY = 0;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_ai(void)
+{
+  m68ki_write_32(EA_AY_AI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_pi(void)
+{
+  m68ki_write_32(EA_AY_PI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_pd(void)
+{
+  m68ki_write_32(EA_AY_PD_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_di(void)
+{
+  m68ki_write_32(EA_AY_DI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_ix(void)
+{
+  m68ki_write_32(EA_AY_IX_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_aw(void)
+{
+  m68ki_write_32(EA_AW_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_al(void)
+{
+  m68ki_write_32(EA_AL_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_cmp_8_d(void)
+{
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_ai(void)
+{
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pi(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pi7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pd(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pd7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_di(void)
+{
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_ix(void)
+{
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_aw(void)
+{
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_al(void)
+{
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pcdi(void)
+{
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pcix(void)
+{
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_i(void)
+{
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_16_d(void)
+{
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_a(void)
+{
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_ai(void)
+{
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pi(void)
+{
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pd(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_di(void)
+{
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_ix(void)
+{
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_aw(void)
+{
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_al(void)
+{
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pcdi(void)
+{
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pcix(void)
+{
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_i(void)
+{
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_32_d(void)
+{
+  uint src = DY;
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_a(void)
+{
+  uint src = AY;
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_ai(void)
+{
+  uint src = OPER_AY_AI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pi(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pd(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_di(void)
+{
+  uint src = OPER_AY_DI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_ix(void)
+{
+  uint src = OPER_AY_IX_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_aw(void)
+{
+  uint src = OPER_AW_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_al(void)
+{
+  uint src = OPER_AL_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pcdi(void)
+{
+  uint src = OPER_PCDI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pcix(void)
+{
+  uint src = OPER_PCIX_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_i(void)
+{
+  uint src = OPER_I_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_d(void)
+{
+  uint src = MAKE_INT_16(DY);
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_a(void)
+{
+  uint src = MAKE_INT_16(AY);
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_ai(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pi(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pd(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_di(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_ix(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_aw(void)
+{
+  uint src = MAKE_INT_16(OPER_AW_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_al(void)
+{
+  uint src = MAKE_INT_16(OPER_AL_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pcdi(void)
+{
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pcix(void)
+{
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_i(void)
+{
+  uint src = MAKE_INT_16(OPER_I_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_d(void)
+{
+  uint src = DY;
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_a(void)
+{
+  uint src = AY;
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_ai(void)
+{
+  uint src = OPER_AY_AI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pi(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pd(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_di(void)
+{
+  uint src = OPER_AY_DI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_ix(void)
+{
+  uint src = OPER_AY_IX_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_aw(void)
+{
+  uint src = OPER_AW_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_al(void)
+{
+  uint src = OPER_AL_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pcdi(void)
+{
+  uint src = OPER_PCDI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pcix(void)
+{
+  uint src = OPER_PCIX_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_i(void)
+{
+  uint src = OPER_I_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_8_d(void)
+{
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(DY);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_AI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_PD_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_A7_PD_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_DI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_IX_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AW_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AL_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_d(void)
+{
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(DY);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_AI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_PI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_PD_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_DI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_IX_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AW_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AL_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_32_d(void)
+{
+  uint src = OPER_I_32();
+  uint dst = DY;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_AI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_PI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_PD_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_DI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_IX_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AW_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AL_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpm_8_ax7(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8_ay7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = OPER_AX_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8_axy7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = OPER_AX_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_16(void)
+{
+  uint src = OPER_AY_PI_16();
+  uint dst = OPER_AX_PI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpm_32(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = OPER_AX_PI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_dbt_16(void)
+{
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbf_16(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  if(res != 0xffff)
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+    /* reset idle loop detection */
+    m68ki_cpu.poll.detected = 0;
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_DBCC_F_EXP);
+}
+
+
+static void __inline m68k_op_dbhi_16(void)
+{
+  if(COND_NOT_HI())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbls_16(void)
+{
+  if(COND_NOT_LS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbcc_16(void)
+{
+  if(COND_NOT_CC())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbcs_16(void)
+{
+  if(COND_NOT_CS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbne_16(void)
+{
+  if(COND_NOT_NE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbeq_16(void)
+{
+  if(COND_NOT_EQ())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbvc_16(void)
+{
+  if(COND_NOT_VC())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbvs_16(void)
+{
+  if(COND_NOT_VS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbpl_16(void)
+{
+  if(COND_NOT_PL())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbmi_16(void)
+{
+  if(COND_NOT_MI())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbge_16(void)
+{
+  if(COND_NOT_GE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dblt_16(void)
+{
+  if(COND_NOT_LT())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbgt_16(void)
+{
+  if(COND_NOT_GT())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dble_16(void)
+{
+  if(COND_NOT_LE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_divs_16_d(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(DY);
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_ai(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_AI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pd(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PD_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_di(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_DI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_ix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_IX_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_aw(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AW_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_al(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AL_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCDI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCIX_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_i(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_I_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_eor_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_d(void)
+{
+  uint res = DY ^= DX;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_d(void)
+{
+  uint res = DY ^= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
+}
+
+
+static void __inline m68k_op_eori_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() ^ src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_exg_32_dd(void)
+{
+  uint* reg_a = &DX;
+  uint* reg_b = &DY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_exg_32_aa(void)
+{
+  uint* reg_a = &AX;
+  uint* reg_b = &AY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_exg_32_da(void)
+{
+  uint* reg_a = &DX;
+  uint* reg_b = &AY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_ext_16(void)
+{
+  uint* r_dst = &DY;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
+
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ext_32(void)
+{
+  uint* r_dst = &DY;
+
+  *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
+
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_illegal(void)
+{
+  m68ki_exception_illegal();
+}
+
+
+static void __inline m68k_op_jmp_32_ai(void)
+{
+  m68ki_jump(EA_AY_AI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_di(void)
+{
+  m68ki_jump(EA_AY_DI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_ix(void)
+{
+  m68ki_jump(EA_AY_IX_32());
+}
+
+
+static void __inline m68k_op_jmp_32_aw(void)
+{
+  m68ki_jump(EA_AW_32());
+}
+
+
+static void __inline m68k_op_jmp_32_al(void)
+{
+  m68ki_jump(EA_AL_32());
+}
+
+
+static void __inline m68k_op_jmp_32_pcdi(void)
+{
+  m68ki_jump(EA_PCDI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_pcix(void)
+{
+  m68ki_jump(EA_PCIX_32());
+}
+
+
+static void __inline m68k_op_jsr_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_al(void)
+{
+  uint ea = EA_AL_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_pcdi(void)
+{
+  uint ea = EA_PCDI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_pcix(void)
+{
+  uint ea = EA_PCIX_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_lea_32_ai(void)
+{
+  AX = EA_AY_AI_32();
+}
+
+
+static void __inline m68k_op_lea_32_di(void)
+{
+  AX = EA_AY_DI_32();
+}
+
+
+static void __inline m68k_op_lea_32_ix(void)
+{
+  AX = EA_AY_IX_32();
+}
+
+
+static void __inline m68k_op_lea_32_aw(void)
+{
+  AX = EA_AW_32();
+}
+
+
+static void __inline m68k_op_lea_32_al(void)
+{
+  AX = EA_AL_32();
+}
+
+
+static void __inline m68k_op_lea_32_pcdi(void)
+{
+  AX = EA_PCDI_32();
+}
+
+
+static void __inline m68k_op_lea_32_pcix(void)
+{
+  AX = EA_PCIX_32();
+}
+
+
+static void __inline m68k_op_link_16_a7(void)
+{
+  REG_A[7] -= 4;
+  m68ki_write_32(REG_A[7], REG_A[7]);
+  REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+static void __inline m68k_op_link_16(void)
+{
+  uint* r_dst = &AY;
+
+  m68ki_push_32(*r_dst);
+  *r_dst = REG_A[7];
+  REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+static void __inline m68k_op_lsr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << (9-shift);
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << shift;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (8-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (24-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_X = FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_al(void)
+{
+  uint res = OPER_AL_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_i(void)
+{
+  uint res = OPER_I_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_ai_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_d_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_al(void)
+{
+  uint res = OPER_AL_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_i(void)
+{
+  uint res = OPER_I_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_ai_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_d_d(void)
+{
+  uint res = DY;
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_a(void)
+{
+  uint res = AY;
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_al(void)
+{
+  uint res = OPER_AL_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_i(void)
+{
+  uint res = OPER_I_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_ai_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pd_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_di_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_movea_16_d(void)
+{
+  AX = MAKE_INT_16(DY);
+}
+
+
+static void __inline m68k_op_movea_16_a(void)
+{
+  AX = MAKE_INT_16(AY);
+}
+
+
+static void __inline m68k_op_movea_16_ai(void)
+{
+  AX = MAKE_INT_16(OPER_AY_AI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pi(void)
+{
+  AX = MAKE_INT_16(OPER_AY_PI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pd(void)
+{
+  AX = MAKE_INT_16(OPER_AY_PD_16());
+}
+
+
+static void __inline m68k_op_movea_16_di(void)
+{
+  AX = MAKE_INT_16(OPER_AY_DI_16());
+}
+
+
+static void __inline m68k_op_movea_16_ix(void)
+{
+  AX = MAKE_INT_16(OPER_AY_IX_16());
+}
+
+
+static void __inline m68k_op_movea_16_aw(void)
+{
+  AX = MAKE_INT_16(OPER_AW_16());
+}
+
+
+static void __inline m68k_op_movea_16_al(void)
+{
+  AX = MAKE_INT_16(OPER_AL_16());
+}
+
+
+static void __inline m68k_op_movea_16_pcdi(void)
+{
+  AX = MAKE_INT_16(OPER_PCDI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pcix(void)
+{
+  AX = MAKE_INT_16(OPER_PCIX_16());
+}
+
+
+static void __inline m68k_op_movea_16_i(void)
+{
+  AX = MAKE_INT_16(OPER_I_16());
+}
+
+
+static void __inline m68k_op_movea_32_d(void)
+{
+  AX = DY;
+}
+
+
+static void __inline m68k_op_movea_32_a(void)
+{
+  AX = AY;
+}
+
+
+static void __inline m68k_op_movea_32_ai(void)
+{
+  AX = OPER_AY_AI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pi(void)
+{
+  AX = OPER_AY_PI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pd(void)
+{
+  AX = OPER_AY_PD_32();
+}
+
+
+static void __inline m68k_op_movea_32_di(void)
+{
+  AX = OPER_AY_DI_32();
+}
+
+
+static void __inline m68k_op_movea_32_ix(void)
+{
+  AX = OPER_AY_IX_32();
+}
+
+
+static void __inline m68k_op_movea_32_aw(void)
+{
+  AX = OPER_AW_32();
+}
+
+
+static void __inline m68k_op_movea_32_al(void)
+{
+  AX = OPER_AL_32();
+}
+
+
+static void __inline m68k_op_movea_32_pcdi(void)
+{
+  AX = OPER_PCDI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pcix(void)
+{
+  AX = OPER_PCIX_32();
+}
+
+
+static void __inline m68k_op_movea_32_i(void)
+{
+  AX = OPER_I_32();
+}
+
+static void __inline m68k_op_move_16_toc_d(void)
+{
+  m68ki_set_ccr(DY);
+}
+
+
+static void __inline m68k_op_move_16_toc_ai(void)
+{
+  m68ki_set_ccr(OPER_AY_AI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pi(void)
+{
+  m68ki_set_ccr(OPER_AY_PI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pd(void)
+{
+  m68ki_set_ccr(OPER_AY_PD_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_di(void)
+{
+  m68ki_set_ccr(OPER_AY_DI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_ix(void)
+{
+  m68ki_set_ccr(OPER_AY_IX_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_aw(void)
+{
+  m68ki_set_ccr(OPER_AW_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_al(void)
+{
+  m68ki_set_ccr(OPER_AL_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pcdi(void)
+{
+  m68ki_set_ccr(OPER_PCDI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pcix(void)
+{
+  m68ki_set_ccr(OPER_PCIX_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_i(void)
+{
+  m68ki_set_ccr(OPER_I_16());
+}
+
+
+static void __inline m68k_op_move_16_frs_d(void)
+{
+  DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
+}
+
+
+static void __inline m68k_op_move_16_frs_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_aw(void)
+{
+  uint ea = EA_AW_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_al(void)
+{
+  uint ea = EA_AL_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_tos_d(void)
+{
+  if(FLAG_S)
+  {
+    m68ki_set_sr(DY);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_ai(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_AI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pi(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_PI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pd(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_PD_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_di(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_DI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_ix(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_IX_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_aw(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AW_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_al(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AL_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pcdi(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_PCDI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pcix(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_PCIX_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_i(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_I_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_32_fru(void)
+{
+  if(FLAG_S)
+  {
+    AY = REG_USP;
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_32_tou(void)
+{
+  if(FLAG_S)
+  {
+    REG_USP = AY;
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_movem_16_re_pd(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      ea -= 2;
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_32_re_pd(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      ea -= 4;
+      m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
+      m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_16_er_pi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_pcdi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCDI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_pcix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCIX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_32_er_pi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_pcdi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCDI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_pcrel_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_pcix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCIX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_pcrel_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movep_16_re(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = DX;
+
+  m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+static void __inline m68k_op_movep_32_re(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+
+  m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+static void __inline m68k_op_movep_16_er(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
+}
+
+
+static void __inline m68k_op_movep_32_er(void)
+{
+  uint ea = EA_AY_DI_32();
+
+  DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
+    + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
+}
+
+
+static void __inline m68k_op_moveq_32(void)
+{
+  uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_d(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(DY);
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_ai(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_AI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pd(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PD_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_di(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_DI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_ix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_IX_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_aw(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AW_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_al(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AL_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCDI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCIX_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_i(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_I_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_nbcd_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_neg_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = *r_dst & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (*r_dst & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - *r_dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
+  FLAG_V = (*r_dst & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_negx_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = *r_dst & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_negx_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (*r_dst & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_negx_16_ai(void)
+{
+  uint ea  = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_pi(void)
+{
+  uint ea  = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_pd(void)
+{
+  uint ea  = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_di(void)
+{
+  uint ea  = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_ix(void)
+{
+  uint ea  = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_aw(void)
+{
+  uint ea  = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_al(void)
+{
+  uint ea  = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
+  FLAG_V = (*r_dst & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_negx_32_ai(void)
+{
+  uint ea  = EA_AY_AI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_pi(void)
+{
+  uint ea  = EA_AY_PI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_pd(void)
+{
+  uint ea  = EA_AY_PD_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_di(void)
+{
+  uint ea  = EA_AY_DI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_ix(void)
+{
+  uint ea  = EA_AY_IX_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_aw(void)
+{
+  uint ea  = EA_AW_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_al(void)
+{
+  uint ea  = EA_AL_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_nop(void)
+{
+}
+
+
+static void __inline m68k_op_not_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_8(~*r_dst);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_16(~*r_dst);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_ai(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pi(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pi7(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pd(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pd7(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_di(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_ix(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_aw(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_al(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pcdi(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pcix(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_i(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_ai(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pi(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pd(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_di(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_ix(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_aw(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_al(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pcdi(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pcix(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_i(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_d(void)
+{
+  uint res = DX |= DY;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_ai(void)
+{
+  uint res = DX |= OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pi(void)
+{
+  uint res = DX |= OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pd(void)
+{
+  uint res = DX |= OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_di(void)
+{
+  uint res = DX |= OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_ix(void)
+{
+  uint res = DX |= OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_aw(void)
+{
+  uint res = DX |= OPER_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_al(void)
+{
+  uint res = DX |= OPER_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pcdi(void)
+{
+  uint res = DX |= OPER_PCDI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pcix(void)
+{
+  uint res = DX |= OPER_PCIX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_i(void)
+{
+  uint res = DX |= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_d(void)
+{
+  uint res = DY |= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
+}
+
+
+static void __inline m68k_op_ori_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() | src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_pea_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_aw(void)
+{
+  uint ea = EA_AW_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_al(void)
+{
+  uint ea = EA_AL_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_pcdi(void)
+{
+  uint ea = EA_PCDI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_pcix(void)
+{
+  uint ea = EA_PCIX_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_reset(void)
+{
+  if(FLAG_S)
+  {
+    m68ki_output_reset()       /* auto-disable (see m68kcpu.h) */
+    USE_CYCLES(CYC_RESET);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_ror_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_8(src, shift);
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-orig_shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_16(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src = *r_dst;
+  uint res = ROR_32(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_8(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_C = src << (8-((shift-1)&7));
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 15;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_16(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_C = (src >> ((shift - 1) & 15)) << 8;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 31;
+  uint64 src = *r_dst;
+  uint res = ROR_32(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = res;
+    FLAG_C = (src >> ((shift - 1) & 31)) << 8;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_8(src, shift);
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = src << orig_shift;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROL_16(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> (8-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src = *r_dst;
+  uint res = ROL_32(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = src >> (24-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_8(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    if(shift != 0)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+    FLAG_C = (src & 1)<<8;
+    FLAG_N = NFLAG_8(src);
+    FLAG_Z = src;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 15;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    if(shift != 0)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+    FLAG_C = (src & 1)<<8;
+    FLAG_N = NFLAG_16(src);
+    FLAG_Z = src;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 31;
+  uint64 src = *r_dst;
+  uint res = ROL_32(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = res;
+
+    FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res;
+  res = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src   = *r_dst;
+  uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  res = ROR_33_64(res, shift);
+
+  FLAG_C = FLAG_X = res >> 24;
+  res = MASK_OUT_ABOVE_32(res);
+
+  *r_dst =  res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+  uint new_x_flag = src & (1 << (shift - 1));
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 9;
+    uint src   = MASK_OUT_ABOVE_8(*r_dst);
+    uint res   = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res;
+    res = MASK_OUT_ABOVE_8(res);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 17;
+    uint src   = MASK_OUT_ABOVE_16(*r_dst);
+    uint res   = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 8;
+    res = MASK_OUT_ABOVE_16(res);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint   shift = orig_shift % 33;
+    uint64 src   = *r_dst;
+    uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+    res = ROR_33_64(res, shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 24;
+    res = MASK_OUT_ABOVE_32(res);
+
+    *r_dst = res;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift % 33;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+  uint new_x_flag = src & (1 << (shift - 1));
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  if(shift != 0)
+  {
+    *r_dst = res;
+    FLAG_X = (new_x_flag != 0)<<8;
+  }
+  else
+    res = src;
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res;
+  res = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src   = *r_dst;
+  uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  res = ROL_33_64(res, shift);
+
+  FLAG_C = FLAG_X = res >> 24;
+  res = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+  uint new_x_flag = src & (1 << (32 - shift));
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 9;
+    uint src   = MASK_OUT_ABOVE_8(*r_dst);
+    uint res   = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res;
+    res = MASK_OUT_ABOVE_8(res);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 17;
+    uint src   = MASK_OUT_ABOVE_16(*r_dst);
+    uint res   = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 8;
+    res = MASK_OUT_ABOVE_16(res);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint   shift = orig_shift % 33;
+    uint64 src   = *r_dst;
+    uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+    res = ROL_33_64(res, shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 24;
+    res = MASK_OUT_ABOVE_32(res);
+
+    *r_dst = res;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift % 33;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+  uint new_x_flag = src & (1 << (32 - shift));
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  if(shift != 0)
+  {
+    *r_dst = res;
+    FLAG_X = (new_x_flag != 0)<<8;
+  }
+  else
+    res = src;
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rte_32(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr;
+    uint new_pc;
+
+    new_sr = m68ki_pull_16();
+    new_pc = m68ki_pull_32();
+    m68ki_jump(new_pc);
+    m68ki_set_sr(new_sr);
+
+#if M68K_EMULATE_ADDRESS_ERROR
+    CPU_INSTR_MODE = INSTRUCTION_YES;
+    CPU_RUN_MODE = RUN_MODE_NORMAL;
+#endif
+
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_rtr_32(void)
+{
+  m68ki_set_ccr(m68ki_pull_16());
+  m68ki_jump(m68ki_pull_32());
+}
+
+
+static void __inline m68k_op_rts_32(void)
+{
+  m68ki_jump(m68ki_pull_32());
+}
+
+
+static void __inline m68k_op_sbcd_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_st_8_d(void)
+{
+  DY |= 0xff;
+}
+
+
+static void __inline m68k_op_st_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0xff);
+}
+
+
+static void __inline m68k_op_sf_8_d(void)
+{
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sf_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0);
+}
+
+
+static void __inline m68k_op_shi_8_d(void)
+{
+  if(COND_HI())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sls_8_d(void)
+{
+  if(COND_LS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_scc_8_d(void)
+{
+  if(COND_CC())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_scs_8_d(void)
+{
+  if(COND_CS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sne_8_d(void)
+{
+  if(COND_NE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_seq_8_d(void)
+{
+  if(COND_EQ())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_svc_8_d(void)
+{
+  if(COND_VC())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_svs_8_d(void)
+{
+  if(COND_VS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_spl_8_d(void)
+{
+  if(COND_PL())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_smi_8_d(void)
+{
+  if(COND_MI())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sge_8_d(void)
+{
+  if(COND_GE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_slt_8_d(void)
+{
+  if(COND_LT())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sgt_8_d(void)
+{
+  if(COND_GT())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sle_8_d(void)
+{
+  if(COND_LE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_shi_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_stop(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_I_16();
+    CPU_STOPPED |= STOP_LEVEL_STOP;
+    m68ki_set_sr(new_sr);
+    if (CPU_STOPPED)
+    {
+      SET_CYCLES(m68ki_cpu.cycle_end - 4*MUL);
+    }
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_sub_8_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pi7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pd7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = AY;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_suba_16_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
+}
+
+
+static void __inline m68k_op_suba_16_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
+}
+
+
+static void __inline m68k_op_suba_16_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AW_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AL_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_I_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
+}
+
+
+static void __inline m68k_op_suba_32_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
+}
+
+
+static void __inline m68k_op_suba_32_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_AI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_PI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_PD_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_DI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_IX_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AW_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AL_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_PCDI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_PCIX_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_I_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_subi_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_8_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pi7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pd7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_16_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+static void __inline m68k_op_subq_16_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_32_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+static void __inline m68k_op_subq_32_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subx_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_subx_16_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_subx_32_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_subx_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_16_mm(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint ea  = EA_AX_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_subx_32_mm(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint ea  = EA_AX_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_swap_32(void)
+{
+  uint* r_dst = &DY;
+
+  FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
+  *r_dst = (*r_dst>>16) | FLAG_Z;
+
+  FLAG_Z = *r_dst;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tas_8_d(void)
+{
+  uint* r_dst = &DY;
+
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  *r_dst |= 0x80;
+}
+
+
+static void __inline m68k_op_tas_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_trap(void)
+{
+  /* Trap#n stacks exception frame type 0 */
+  m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf));  /* HJB 990403 */
+}
+
+
+static void __inline m68k_op_trapv(void)
+{
+  if(COND_VC())
+  {
+    return;
+  }
+  m68ki_exception_trap(EXCEPTION_TRAPV);  /* HJB 990403 */
+}
+
+
+static void __inline m68k_op_tst_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_di(void)
+{
+  uint res = OPER_AY_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_aw(void)
+{
+  uint res = OPER_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_al(void)
+{
+  uint res = OPER_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_di(void)
+{
+  uint res = OPER_AY_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_aw(void)
+{
+  uint res = OPER_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_al(void)
+{
+  uint res = OPER_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_d(void)
+{
+  uint res = DY;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_di(void)
+{
+  uint res = OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_aw(void)
+{
+  uint res = OPER_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_al(void)
+{
+  uint res = OPER_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_unlk_32_a7(void)
+{
+  REG_A[7] = m68ki_read_32(REG_A[7]);
+}
+
+
+static void __inline m68k_op_unlk_32(void)
+{
+  uint* r_dst = &AY;
+
+  REG_A[7] = *r_dst;
+  *r_dst = m68ki_pull_32();
+}
+
+
+/* ======================================================================== */
+/* ========================= OPCODE TABLE BUILDER ========================= */
+/* ======================================================================== */
+
+#ifndef BUILD_TABLES
+
+  #ifndef TABLES_FULL
+    #include "m68ki_instruction_jump_table.h"
+  #else
+    #include "m68ki_instruction_jump_table_full.h"
+  #endif
+#else
+
+/* This is used to generate the opcode handler jump table */
+typedef struct
+{
+  void (*opcode_handler)(void); /* handler function */
+  unsigned int  mask;           /* mask on opcode */
+  unsigned int  match;          /* what to match after masking */
+  unsigned char cycles;         /* cycles each cpu type takes */
+} opcode_handler_struct;
+
+/* opcode handler jump table */
+static void __inline  (*m68ki_instruction_jump_table[0x10000])(void);
+
+/* Opcode handler table */
+static const opcode_handler_struct m68k_opcode_handler_table[] =
+{
+/*   function                      mask    match  cyc */
+  {m68k_op_1010                , 0xf000, 0xa000,  4},
+  {m68k_op_1111                , 0xf000, 0xf000,  4},
+  {m68k_op_moveq_32            , 0xf100, 0x7000,  4},
+  {m68k_op_bra_8               , 0xff00, 0x6000, 10},
+  {m68k_op_bsr_8               , 0xff00, 0x6100, 18},
+  {m68k_op_bhi_8               , 0xff00, 0x6200, 10},
+  {m68k_op_bls_8               , 0xff00, 0x6300, 10},
+  {m68k_op_bcc_8               , 0xff00, 0x6400, 10},
+  {m68k_op_bcs_8               , 0xff00, 0x6500, 10},
+  {m68k_op_bne_8               , 0xff00, 0x6600, 10},
+  {m68k_op_beq_8               , 0xff00, 0x6700, 10},
+  {m68k_op_bvc_8               , 0xff00, 0x6800, 10},
+  {m68k_op_bvs_8               , 0xff00, 0x6900, 10},
+  {m68k_op_bpl_8               , 0xff00, 0x6a00, 10},
+  {m68k_op_bmi_8               , 0xff00, 0x6b00, 10},
+  {m68k_op_bge_8               , 0xff00, 0x6c00, 10},
+  {m68k_op_blt_8               , 0xff00, 0x6d00, 10},
+  {m68k_op_bgt_8               , 0xff00, 0x6e00, 10},
+  {m68k_op_ble_8               , 0xff00, 0x6f00, 10},
+  {m68k_op_btst_32_r_d         , 0xf1f8, 0x0100,  6},
+  {m68k_op_movep_16_er         , 0xf1f8, 0x0108, 16},
+  {m68k_op_btst_8_r_ai         , 0xf1f8, 0x0110,  8},
+  {m68k_op_btst_8_r_pi         , 0xf1f8, 0x0118,  8},
+  {m68k_op_btst_8_r_pd         , 0xf1f8, 0x0120, 10},
+  {m68k_op_btst_8_r_di         , 0xf1f8, 0x0128, 12},
+  {m68k_op_btst_8_r_ix         , 0xf1f8, 0x0130, 14},
+  {m68k_op_bchg_32_r_d         , 0xf1f8, 0x0140,  8},
+  {m68k_op_movep_32_er         , 0xf1f8, 0x0148, 24},
+  {m68k_op_bchg_8_r_ai         , 0xf1f8, 0x0150, 12},
+  {m68k_op_bchg_8_r_pi         , 0xf1f8, 0x0158, 12},
+  {m68k_op_bchg_8_r_pd         , 0xf1f8, 0x0160, 14},
+  {m68k_op_bchg_8_r_di         , 0xf1f8, 0x0168, 16},
+  {m68k_op_bchg_8_r_ix         , 0xf1f8, 0x0170, 18},
+  {m68k_op_bclr_32_r_d         , 0xf1f8, 0x0180, 10},
+  {m68k_op_movep_16_re         , 0xf1f8, 0x0188, 16},
+  {m68k_op_bclr_8_r_ai         , 0xf1f8, 0x0190, 12},
+  {m68k_op_bclr_8_r_pi         , 0xf1f8, 0x0198, 12},
+  {m68k_op_bclr_8_r_pd         , 0xf1f8, 0x01a0, 14},
+  {m68k_op_bclr_8_r_di         , 0xf1f8, 0x01a8, 16},
+  {m68k_op_bclr_8_r_ix         , 0xf1f8, 0x01b0, 18},
+  {m68k_op_bset_32_r_d         , 0xf1f8, 0x01c0,  8},
+  {m68k_op_movep_32_re         , 0xf1f8, 0x01c8, 24},
+  {m68k_op_bset_8_r_ai         , 0xf1f8, 0x01d0, 12},
+  {m68k_op_bset_8_r_pi         , 0xf1f8, 0x01d8, 12},
+  {m68k_op_bset_8_r_pd         , 0xf1f8, 0x01e0, 14},
+  {m68k_op_bset_8_r_di         , 0xf1f8, 0x01e8, 16},
+  {m68k_op_bset_8_r_ix         , 0xf1f8, 0x01f0, 18},
+  {m68k_op_move_8_d_d          , 0xf1f8, 0x1000,  4},
+  {m68k_op_move_8_d_ai         , 0xf1f8, 0x1010,  8},
+  {m68k_op_move_8_d_pi         , 0xf1f8, 0x1018,  8},
+  {m68k_op_move_8_d_pd         , 0xf1f8, 0x1020, 10},
+  {m68k_op_move_8_d_di         , 0xf1f8, 0x1028, 12},
+  {m68k_op_move_8_d_ix         , 0xf1f8, 0x1030, 14},
+  {m68k_op_move_8_ai_d         , 0xf1f8, 0x1080,  8},
+  {m68k_op_move_8_ai_ai        , 0xf1f8, 0x1090, 12},
+  {m68k_op_move_8_ai_pi        , 0xf1f8, 0x1098, 12},
+  {m68k_op_move_8_ai_pd        , 0xf1f8, 0x10a0, 14},
+  {m68k_op_move_8_ai_di        , 0xf1f8, 0x10a8, 16},
+  {m68k_op_move_8_ai_ix        , 0xf1f8, 0x10b0, 18},
+  {m68k_op_move_8_pi_d         , 0xf1f8, 0x10c0,  8},
+  {m68k_op_move_8_pi_ai        , 0xf1f8, 0x10d0, 12},
+  {m68k_op_move_8_pi_pi        , 0xf1f8, 0x10d8, 12},
+  {m68k_op_move_8_pi_pd        , 0xf1f8, 0x10e0, 14},
+  {m68k_op_move_8_pi_di        , 0xf1f8, 0x10e8, 16},
+  {m68k_op_move_8_pi_ix        , 0xf1f8, 0x10f0, 18},
+  {m68k_op_move_8_pd_d         , 0xf1f8, 0x1100,  8},
+  {m68k_op_move_8_pd_ai        , 0xf1f8, 0x1110, 12},
+  {m68k_op_move_8_pd_pi        , 0xf1f8, 0x1118, 12},
+  {m68k_op_move_8_pd_pd        , 0xf1f8, 0x1120, 14},
+  {m68k_op_move_8_pd_di        , 0xf1f8, 0x1128, 16},
+  {m68k_op_move_8_pd_ix        , 0xf1f8, 0x1130, 18},
+  {m68k_op_move_8_di_d         , 0xf1f8, 0x1140, 12},
+  {m68k_op_move_8_di_ai        , 0xf1f8, 0x1150, 16},
+  {m68k_op_move_8_di_pi        , 0xf1f8, 0x1158, 16},
+  {m68k_op_move_8_di_pd        , 0xf1f8, 0x1160, 18},
+  {m68k_op_move_8_di_di        , 0xf1f8, 0x1168, 20},
+  {m68k_op_move_8_di_ix        , 0xf1f8, 0x1170, 22},
+  {m68k_op_move_8_ix_d         , 0xf1f8, 0x1180, 14},
+  {m68k_op_move_8_ix_ai        , 0xf1f8, 0x1190, 18},
+  {m68k_op_move_8_ix_pi        , 0xf1f8, 0x1198, 18},
+  {m68k_op_move_8_ix_pd        , 0xf1f8, 0x11a0, 20},
+  {m68k_op_move_8_ix_di        , 0xf1f8, 0x11a8, 22},
+  {m68k_op_move_8_ix_ix        , 0xf1f8, 0x11b0, 24},
+  {m68k_op_move_32_d_d         , 0xf1f8, 0x2000,  4},
+  {m68k_op_move_32_d_a         , 0xf1f8, 0x2008,  4},
+  {m68k_op_move_32_d_ai        , 0xf1f8, 0x2010, 12},
+  {m68k_op_move_32_d_pi        , 0xf1f8, 0x2018, 12},
+  {m68k_op_move_32_d_pd        , 0xf1f8, 0x2020, 14},
+  {m68k_op_move_32_d_di        , 0xf1f8, 0x2028, 16},
+  {m68k_op_move_32_d_ix        , 0xf1f8, 0x2030, 18},
+  {m68k_op_movea_32_d          , 0xf1f8, 0x2040,  4},
+  {m68k_op_movea_32_a          , 0xf1f8, 0x2048,  4},
+  {m68k_op_movea_32_ai         , 0xf1f8, 0x2050, 12},
+  {m68k_op_movea_32_pi         , 0xf1f8, 0x2058, 12},
+  {m68k_op_movea_32_pd         , 0xf1f8, 0x2060, 14},
+  {m68k_op_movea_32_di         , 0xf1f8, 0x2068, 16},
+  {m68k_op_movea_32_ix         , 0xf1f8, 0x2070, 18},
+  {m68k_op_move_32_ai_d        , 0xf1f8, 0x2080, 12},
+  {m68k_op_move_32_ai_a        , 0xf1f8, 0x2088, 12},
+  {m68k_op_move_32_ai_ai       , 0xf1f8, 0x2090, 20},
+  {m68k_op_move_32_ai_pi       , 0xf1f8, 0x2098, 20},
+  {m68k_op_move_32_ai_pd       , 0xf1f8, 0x20a0, 22},
+  {m68k_op_move_32_ai_di       , 0xf1f8, 0x20a8, 24},
+  {m68k_op_move_32_ai_ix       , 0xf1f8, 0x20b0, 26},
+  {m68k_op_move_32_pi_d        , 0xf1f8, 0x20c0, 12},
+  {m68k_op_move_32_pi_a        , 0xf1f8, 0x20c8, 12},
+  {m68k_op_move_32_pi_ai       , 0xf1f8, 0x20d0, 20},
+  {m68k_op_move_32_pi_pi       , 0xf1f8, 0x20d8, 20},
+  {m68k_op_move_32_pi_pd       , 0xf1f8, 0x20e0, 22},
+  {m68k_op_move_32_pi_di       , 0xf1f8, 0x20e8, 24},
+  {m68k_op_move_32_pi_ix       , 0xf1f8, 0x20f0, 26},
+  {m68k_op_move_32_pd_d        , 0xf1f8, 0x2100, 12},
+  {m68k_op_move_32_pd_a        , 0xf1f8, 0x2108, 12},
+  {m68k_op_move_32_pd_ai       , 0xf1f8, 0x2110, 20},
+  {m68k_op_move_32_pd_pi       , 0xf1f8, 0x2118, 20},
+  {m68k_op_move_32_pd_pd       , 0xf1f8, 0x2120, 22},
+  {m68k_op_move_32_pd_di       , 0xf1f8, 0x2128, 24},
+  {m68k_op_move_32_pd_ix       , 0xf1f8, 0x2130, 26},
+  {m68k_op_move_32_di_d        , 0xf1f8, 0x2140, 16},
+  {m68k_op_move_32_di_a        , 0xf1f8, 0x2148, 16},
+  {m68k_op_move_32_di_ai       , 0xf1f8, 0x2150, 24},
+  {m68k_op_move_32_di_pi       , 0xf1f8, 0x2158, 24},
+  {m68k_op_move_32_di_pd       , 0xf1f8, 0x2160, 26},
+  {m68k_op_move_32_di_di       , 0xf1f8, 0x2168, 28},
+  {m68k_op_move_32_di_ix       , 0xf1f8, 0x2170, 30},
+  {m68k_op_move_32_ix_d        , 0xf1f8, 0x2180, 18},
+  {m68k_op_move_32_ix_a        , 0xf1f8, 0x2188, 18},
+  {m68k_op_move_32_ix_ai       , 0xf1f8, 0x2190, 26},
+  {m68k_op_move_32_ix_pi       , 0xf1f8, 0x2198, 26},
+  {m68k_op_move_32_ix_pd       , 0xf1f8, 0x21a0, 28},
+  {m68k_op_move_32_ix_di       , 0xf1f8, 0x21a8, 30},
+  {m68k_op_move_32_ix_ix       , 0xf1f8, 0x21b0, 32},
+  {m68k_op_move_16_d_d         , 0xf1f8, 0x3000,  4},
+  {m68k_op_move_16_d_a         , 0xf1f8, 0x3008,  4},
+  {m68k_op_move_16_d_ai        , 0xf1f8, 0x3010,  8},
+  {m68k_op_move_16_d_pi        , 0xf1f8, 0x3018,  8},
+  {m68k_op_move_16_d_pd        , 0xf1f8, 0x3020, 10},
+  {m68k_op_move_16_d_di        , 0xf1f8, 0x3028, 12},
+  {m68k_op_move_16_d_ix        , 0xf1f8, 0x3030, 14},
+  {m68k_op_movea_16_d          , 0xf1f8, 0x3040,  4},
+  {m68k_op_movea_16_a          , 0xf1f8, 0x3048,  4},
+  {m68k_op_movea_16_ai         , 0xf1f8, 0x3050,  8},
+  {m68k_op_movea_16_pi         , 0xf1f8, 0x3058,  8},
+  {m68k_op_movea_16_pd         , 0xf1f8, 0x3060, 10},
+  {m68k_op_movea_16_di         , 0xf1f8, 0x3068, 12},
+  {m68k_op_movea_16_ix         , 0xf1f8, 0x3070, 14},
+  {m68k_op_move_16_ai_d        , 0xf1f8, 0x3080,  8},
+  {m68k_op_move_16_ai_a        , 0xf1f8, 0x3088,  8},
+  {m68k_op_move_16_ai_ai       , 0xf1f8, 0x3090, 12},
+  {m68k_op_move_16_ai_pi       , 0xf1f8, 0x3098, 12},
+  {m68k_op_move_16_ai_pd       , 0xf1f8, 0x30a0, 14},
+  {m68k_op_move_16_ai_di       , 0xf1f8, 0x30a8, 16},
+  {m68k_op_move_16_ai_ix       , 0xf1f8, 0x30b0, 18},
+  {m68k_op_move_16_pi_d        , 0xf1f8, 0x30c0,  8},
+  {m68k_op_move_16_pi_a        , 0xf1f8, 0x30c8,  8},
+  {m68k_op_move_16_pi_ai       , 0xf1f8, 0x30d0, 12},
+  {m68k_op_move_16_pi_pi       , 0xf1f8, 0x30d8, 12},
+  {m68k_op_move_16_pi_pd       , 0xf1f8, 0x30e0, 14},
+  {m68k_op_move_16_pi_di       , 0xf1f8, 0x30e8, 16},
+  {m68k_op_move_16_pi_ix       , 0xf1f8, 0x30f0, 18},
+  {m68k_op_move_16_pd_d        , 0xf1f8, 0x3100,  8},
+  {m68k_op_move_16_pd_a        , 0xf1f8, 0x3108,  8},
+  {m68k_op_move_16_pd_ai       , 0xf1f8, 0x3110, 12},
+  {m68k_op_move_16_pd_pi       , 0xf1f8, 0x3118, 12},
+  {m68k_op_move_16_pd_pd       , 0xf1f8, 0x3120, 14},
+  {m68k_op_move_16_pd_di       , 0xf1f8, 0x3128, 16},
+  {m68k_op_move_16_pd_ix       , 0xf1f8, 0x3130, 18},
+  {m68k_op_move_16_di_d        , 0xf1f8, 0x3140, 12},
+  {m68k_op_move_16_di_a        , 0xf1f8, 0x3148, 12},
+  {m68k_op_move_16_di_ai       , 0xf1f8, 0x3150, 16},
+  {m68k_op_move_16_di_pi       , 0xf1f8, 0x3158, 16},
+  {m68k_op_move_16_di_pd       , 0xf1f8, 0x3160, 18},
+  {m68k_op_move_16_di_di       , 0xf1f8, 0x3168, 20},
+  {m68k_op_move_16_di_ix       , 0xf1f8, 0x3170, 22},
+  {m68k_op_move_16_ix_d        , 0xf1f8, 0x3180, 14},
+  {m68k_op_move_16_ix_a        , 0xf1f8, 0x3188, 14},
+  {m68k_op_move_16_ix_ai       , 0xf1f8, 0x3190, 18},
+  {m68k_op_move_16_ix_pi       , 0xf1f8, 0x3198, 18},
+  {m68k_op_move_16_ix_pd       , 0xf1f8, 0x31a0, 20},
+  {m68k_op_move_16_ix_di       , 0xf1f8, 0x31a8, 22},
+  {m68k_op_move_16_ix_ix       , 0xf1f8, 0x31b0, 24},
+  {m68k_op_chk_16_d            , 0xf1f8, 0x4180, 10},
+  {m68k_op_chk_16_ai           , 0xf1f8, 0x4190, 14},
+  {m68k_op_chk_16_pi           , 0xf1f8, 0x4198, 14},
+  {m68k_op_chk_16_pd           , 0xf1f8, 0x41a0, 16},
+  {m68k_op_chk_16_di           , 0xf1f8, 0x41a8, 18},
+  {m68k_op_chk_16_ix           , 0xf1f8, 0x41b0, 20},
+  {m68k_op_lea_32_ai           , 0xf1f8, 0x41d0,  4},
+  {m68k_op_lea_32_di           , 0xf1f8, 0x41e8,  8},
+  {m68k_op_lea_32_ix           , 0xf1f8, 0x41f0, 12},
+  {m68k_op_addq_8_d            , 0xf1f8, 0x5000,  4},
+  {m68k_op_addq_8_ai           , 0xf1f8, 0x5010, 12},
+  {m68k_op_addq_8_pi           , 0xf1f8, 0x5018, 12},
+  {m68k_op_addq_8_pd           , 0xf1f8, 0x5020, 14},
+  {m68k_op_addq_8_di           , 0xf1f8, 0x5028, 16},
+  {m68k_op_addq_8_ix           , 0xf1f8, 0x5030, 18},
+  {m68k_op_addq_16_d           , 0xf1f8, 0x5040,  4},
+  {m68k_op_addq_16_a           , 0xf1f8, 0x5048,  8}, /* see Yacht.txt */
+  {m68k_op_addq_16_ai          , 0xf1f8, 0x5050, 12},
+  {m68k_op_addq_16_pi          , 0xf1f8, 0x5058, 12},
+  {m68k_op_addq_16_pd          , 0xf1f8, 0x5060, 14},
+  {m68k_op_addq_16_di          , 0xf1f8, 0x5068, 16},
+  {m68k_op_addq_16_ix          , 0xf1f8, 0x5070, 18},
+  {m68k_op_addq_32_d           , 0xf1f8, 0x5080,  8},
+  {m68k_op_addq_32_a           , 0xf1f8, 0x5088,  8},
+  {m68k_op_addq_32_ai          , 0xf1f8, 0x5090, 20},
+  {m68k_op_addq_32_pi          , 0xf1f8, 0x5098, 20},
+  {m68k_op_addq_32_pd          , 0xf1f8, 0x50a0, 22},
+  {m68k_op_addq_32_di          , 0xf1f8, 0x50a8, 24},
+  {m68k_op_addq_32_ix          , 0xf1f8, 0x50b0, 26},
+  {m68k_op_subq_8_d            , 0xf1f8, 0x5100,  4},
+  {m68k_op_subq_8_ai           , 0xf1f8, 0x5110, 12},
+  {m68k_op_subq_8_pi           , 0xf1f8, 0x5118, 12},
+  {m68k_op_subq_8_pd           , 0xf1f8, 0x5120, 14},
+  {m68k_op_subq_8_di           , 0xf1f8, 0x5128, 16},
+  {m68k_op_subq_8_ix           , 0xf1f8, 0x5130, 18},
+  {m68k_op_subq_16_d           , 0xf1f8, 0x5140,  4},
+  {m68k_op_subq_16_a           , 0xf1f8, 0x5148,  8},
+  {m68k_op_subq_16_ai          , 0xf1f8, 0x5150, 12},
+  {m68k_op_subq_16_pi          , 0xf1f8, 0x5158, 12},
+  {m68k_op_subq_16_pd          , 0xf1f8, 0x5160, 14},
+  {m68k_op_subq_16_di          , 0xf1f8, 0x5168, 16},
+  {m68k_op_subq_16_ix          , 0xf1f8, 0x5170, 18},
+  {m68k_op_subq_32_d           , 0xf1f8, 0x5180,  8},
+  {m68k_op_subq_32_a           , 0xf1f8, 0x5188,  8},
+  {m68k_op_subq_32_ai          , 0xf1f8, 0x5190, 20},
+  {m68k_op_subq_32_pi          , 0xf1f8, 0x5198, 20},
+  {m68k_op_subq_32_pd          , 0xf1f8, 0x51a0, 22},
+  {m68k_op_subq_32_di          , 0xf1f8, 0x51a8, 24},
+  {m68k_op_subq_32_ix          , 0xf1f8, 0x51b0, 26},
+  {m68k_op_or_8_er_d           , 0xf1f8, 0x8000,  4},
+  {m68k_op_or_8_er_ai          , 0xf1f8, 0x8010,  8},
+  {m68k_op_or_8_er_pi          , 0xf1f8, 0x8018,  8},
+  {m68k_op_or_8_er_pd          , 0xf1f8, 0x8020, 10},
+  {m68k_op_or_8_er_di          , 0xf1f8, 0x8028, 12},
+  {m68k_op_or_8_er_ix          , 0xf1f8, 0x8030, 14},
+  {m68k_op_or_16_er_d          , 0xf1f8, 0x8040,  4},
+  {m68k_op_or_16_er_ai         , 0xf1f8, 0x8050,  8},
+  {m68k_op_or_16_er_pi         , 0xf1f8, 0x8058,  8},
+  {m68k_op_or_16_er_pd         , 0xf1f8, 0x8060, 10},
+  {m68k_op_or_16_er_di         , 0xf1f8, 0x8068, 12},
+  {m68k_op_or_16_er_ix         , 0xf1f8, 0x8070, 14},
+  {m68k_op_or_32_er_d          , 0xf1f8, 0x8080,  8},
+  {m68k_op_or_32_er_ai         , 0xf1f8, 0x8090, 14},
+  {m68k_op_or_32_er_pi         , 0xf1f8, 0x8098, 14},
+  {m68k_op_or_32_er_pd         , 0xf1f8, 0x80a0, 16},
+  {m68k_op_or_32_er_di         , 0xf1f8, 0x80a8, 18},
+  {m68k_op_or_32_er_ix         , 0xf1f8, 0x80b0, 20},
+  {m68k_op_divu_16_d           , 0xf1f8, 0x80c0,  0},
+  {m68k_op_divu_16_ai          , 0xf1f8, 0x80d0,  4},
+  {m68k_op_divu_16_pi          , 0xf1f8, 0x80d8,  4},
+  {m68k_op_divu_16_pd          , 0xf1f8, 0x80e0,  6},
+  {m68k_op_divu_16_di          , 0xf1f8, 0x80e8,  8},
+  {m68k_op_divu_16_ix          , 0xf1f8, 0x80f0, 10},
+  {m68k_op_sbcd_8_rr           , 0xf1f8, 0x8100,  6},
+  {m68k_op_sbcd_8_mm           , 0xf1f8, 0x8108, 18},
+  {m68k_op_or_8_re_ai          , 0xf1f8, 0x8110, 12},
+  {m68k_op_or_8_re_pi          , 0xf1f8, 0x8118, 12},
+  {m68k_op_or_8_re_pd          , 0xf1f8, 0x8120, 14},
+  {m68k_op_or_8_re_di          , 0xf1f8, 0x8128, 16},
+  {m68k_op_or_8_re_ix          , 0xf1f8, 0x8130, 18},
+  {m68k_op_or_16_re_ai         , 0xf1f8, 0x8150, 12},
+  {m68k_op_or_16_re_pi         , 0xf1f8, 0x8158, 12},
+  {m68k_op_or_16_re_pd         , 0xf1f8, 0x8160, 14},
+  {m68k_op_or_16_re_di         , 0xf1f8, 0x8168, 16},
+  {m68k_op_or_16_re_ix         , 0xf1f8, 0x8170, 18},
+  {m68k_op_or_32_re_ai         , 0xf1f8, 0x8190, 20},
+  {m68k_op_or_32_re_pi         , 0xf1f8, 0x8198, 20},
+  {m68k_op_or_32_re_pd         , 0xf1f8, 0x81a0, 22},
+  {m68k_op_or_32_re_di         , 0xf1f8, 0x81a8, 24},
+  {m68k_op_or_32_re_ix         , 0xf1f8, 0x81b0, 26},
+  {m68k_op_divs_16_d           , 0xf1f8, 0x81c0,  0},
+  {m68k_op_divs_16_ai          , 0xf1f8, 0x81d0,  4},
+  {m68k_op_divs_16_pi          , 0xf1f8, 0x81d8,  4},
+  {m68k_op_divs_16_pd          , 0xf1f8, 0x81e0,  6},
+  {m68k_op_divs_16_di          , 0xf1f8, 0x81e8,  8},
+  {m68k_op_divs_16_ix          , 0xf1f8, 0x81f0, 10},
+  {m68k_op_sub_8_er_d          , 0xf1f8, 0x9000,  4},
+  {m68k_op_sub_8_er_ai         , 0xf1f8, 0x9010,  8},
+  {m68k_op_sub_8_er_pi         , 0xf1f8, 0x9018,  8},
+  {m68k_op_sub_8_er_pd         , 0xf1f8, 0x9020, 10},
+  {m68k_op_sub_8_er_di         , 0xf1f8, 0x9028, 12},
+  {m68k_op_sub_8_er_ix         , 0xf1f8, 0x9030, 14},
+  {m68k_op_sub_16_er_d         , 0xf1f8, 0x9040,  4},
+  {m68k_op_sub_16_er_a         , 0xf1f8, 0x9048,  4},
+  {m68k_op_sub_16_er_ai        , 0xf1f8, 0x9050,  8},
+  {m68k_op_sub_16_er_pi        , 0xf1f8, 0x9058,  8},
+  {m68k_op_sub_16_er_pd        , 0xf1f8, 0x9060, 10},
+  {m68k_op_sub_16_er_di        , 0xf1f8, 0x9068, 12},
+  {m68k_op_sub_16_er_ix        , 0xf1f8, 0x9070, 14},
+  {m68k_op_sub_32_er_d         , 0xf1f8, 0x9080,  8},
+  {m68k_op_sub_32_er_a         , 0xf1f8, 0x9088,  8},
+  {m68k_op_sub_32_er_ai        , 0xf1f8, 0x9090, 14},
+  {m68k_op_sub_32_er_pi        , 0xf1f8, 0x9098, 14},
+  {m68k_op_sub_32_er_pd        , 0xf1f8, 0x90a0, 16},
+  {m68k_op_sub_32_er_di        , 0xf1f8, 0x90a8, 18},
+  {m68k_op_sub_32_er_ix        , 0xf1f8, 0x90b0, 20},
+  {m68k_op_suba_16_d           , 0xf1f8, 0x90c0,  8},
+  {m68k_op_suba_16_a           , 0xf1f8, 0x90c8,  8},
+  {m68k_op_suba_16_ai          , 0xf1f8, 0x90d0, 12},
+  {m68k_op_suba_16_pi          , 0xf1f8, 0x90d8, 12},
+  {m68k_op_suba_16_pd          , 0xf1f8, 0x90e0, 14},
+  {m68k_op_suba_16_di          , 0xf1f8, 0x90e8, 16},
+  {m68k_op_suba_16_ix          , 0xf1f8, 0x90f0, 18},
+  {m68k_op_subx_8_rr           , 0xf1f8, 0x9100,  4},
+  {m68k_op_subx_8_mm           , 0xf1f8, 0x9108, 18},
+  {m68k_op_sub_8_re_ai         , 0xf1f8, 0x9110, 12},
+  {m68k_op_sub_8_re_pi         , 0xf1f8, 0x9118, 12},
+  {m68k_op_sub_8_re_pd         , 0xf1f8, 0x9120, 14},
+  {m68k_op_sub_8_re_di         , 0xf1f8, 0x9128, 16},
+  {m68k_op_sub_8_re_ix         , 0xf1f8, 0x9130, 18},
+  {m68k_op_subx_16_rr          , 0xf1f8, 0x9140,  4},
+  {m68k_op_subx_16_mm          , 0xf1f8, 0x9148, 18},
+  {m68k_op_sub_16_re_ai        , 0xf1f8, 0x9150, 12},
+  {m68k_op_sub_16_re_pi        , 0xf1f8, 0x9158, 12},
+  {m68k_op_sub_16_re_pd        , 0xf1f8, 0x9160, 14},
+  {m68k_op_sub_16_re_di        , 0xf1f8, 0x9168, 16},
+  {m68k_op_sub_16_re_ix        , 0xf1f8, 0x9170, 18},
+  {m68k_op_subx_32_rr          , 0xf1f8, 0x9180,  8},
+  {m68k_op_subx_32_mm          , 0xf1f8, 0x9188, 30},
+  {m68k_op_sub_32_re_ai        , 0xf1f8, 0x9190, 20},
+  {m68k_op_sub_32_re_pi        , 0xf1f8, 0x9198, 20},
+  {m68k_op_sub_32_re_pd        , 0xf1f8, 0x91a0, 22},
+  {m68k_op_sub_32_re_di        , 0xf1f8, 0x91a8, 24},
+  {m68k_op_sub_32_re_ix        , 0xf1f8, 0x91b0, 26},
+  {m68k_op_suba_32_d           , 0xf1f8, 0x91c0,  8},
+  {m68k_op_suba_32_a           , 0xf1f8, 0x91c8,  8},
+  {m68k_op_suba_32_ai          , 0xf1f8, 0x91d0, 14},
+  {m68k_op_suba_32_pi          , 0xf1f8, 0x91d8, 14},
+  {m68k_op_suba_32_pd          , 0xf1f8, 0x91e0, 16},
+  {m68k_op_suba_32_di          , 0xf1f8, 0x91e8, 18},
+  {m68k_op_suba_32_ix          , 0xf1f8, 0x91f0, 20},
+  {m68k_op_cmp_8_d             , 0xf1f8, 0xb000,  4},
+  {m68k_op_cmp_8_ai            , 0xf1f8, 0xb010,  8},
+  {m68k_op_cmp_8_pi            , 0xf1f8, 0xb018,  8},
+  {m68k_op_cmp_8_pd            , 0xf1f8, 0xb020, 10},
+  {m68k_op_cmp_8_di            , 0xf1f8, 0xb028, 12},
+  {m68k_op_cmp_8_ix            , 0xf1f8, 0xb030, 14},
+  {m68k_op_cmp_16_d            , 0xf1f8, 0xb040,  4},
+  {m68k_op_cmp_16_a            , 0xf1f8, 0xb048,  4},
+  {m68k_op_cmp_16_ai           , 0xf1f8, 0xb050,  8},
+  {m68k_op_cmp_16_pi           , 0xf1f8, 0xb058,  8},
+  {m68k_op_cmp_16_pd           , 0xf1f8, 0xb060, 10},
+  {m68k_op_cmp_16_di           , 0xf1f8, 0xb068, 12},
+  {m68k_op_cmp_16_ix           , 0xf1f8, 0xb070, 14},
+  {m68k_op_cmp_32_d            , 0xf1f8, 0xb080,  6},
+  {m68k_op_cmp_32_a            , 0xf1f8, 0xb088,  6},
+  {m68k_op_cmp_32_ai           , 0xf1f8, 0xb090, 14},
+  {m68k_op_cmp_32_pi           , 0xf1f8, 0xb098, 14},
+  {m68k_op_cmp_32_pd           , 0xf1f8, 0xb0a0, 16},
+  {m68k_op_cmp_32_di           , 0xf1f8, 0xb0a8, 18},
+  {m68k_op_cmp_32_ix           , 0xf1f8, 0xb0b0, 20},
+  {m68k_op_cmpa_16_d           , 0xf1f8, 0xb0c0,  6},
+  {m68k_op_cmpa_16_a           , 0xf1f8, 0xb0c8,  6},
+  {m68k_op_cmpa_16_ai          , 0xf1f8, 0xb0d0, 10},
+  {m68k_op_cmpa_16_pi          , 0xf1f8, 0xb0d8, 10},
+  {m68k_op_cmpa_16_pd          , 0xf1f8, 0xb0e0, 12},
+  {m68k_op_cmpa_16_di          , 0xf1f8, 0xb0e8, 14},
+  {m68k_op_cmpa_16_ix          , 0xf1f8, 0xb0f0, 16},
+  {m68k_op_eor_8_d             , 0xf1f8, 0xb100,  4},
+  {m68k_op_cmpm_8              , 0xf1f8, 0xb108, 12},
+  {m68k_op_eor_8_ai            , 0xf1f8, 0xb110, 12},
+  {m68k_op_eor_8_pi            , 0xf1f8, 0xb118, 12},
+  {m68k_op_eor_8_pd            , 0xf1f8, 0xb120, 14},
+  {m68k_op_eor_8_di            , 0xf1f8, 0xb128, 16},
+  {m68k_op_eor_8_ix            , 0xf1f8, 0xb130, 18},
+  {m68k_op_eor_16_d            , 0xf1f8, 0xb140,  4},
+  {m68k_op_cmpm_16             , 0xf1f8, 0xb148, 12},
+  {m68k_op_eor_16_ai           , 0xf1f8, 0xb150, 12},
+  {m68k_op_eor_16_pi           , 0xf1f8, 0xb158, 12},
+  {m68k_op_eor_16_pd           , 0xf1f8, 0xb160, 14},
+  {m68k_op_eor_16_di           , 0xf1f8, 0xb168, 16},
+  {m68k_op_eor_16_ix           , 0xf1f8, 0xb170, 18},
+  {m68k_op_eor_32_d            , 0xf1f8, 0xb180,  8},
+  {m68k_op_cmpm_32             , 0xf1f8, 0xb188, 20},
+  {m68k_op_eor_32_ai           , 0xf1f8, 0xb190, 20},
+  {m68k_op_eor_32_pi           , 0xf1f8, 0xb198, 20},
+  {m68k_op_eor_32_pd           , 0xf1f8, 0xb1a0, 22},
+  {m68k_op_eor_32_di           , 0xf1f8, 0xb1a8, 24},
+  {m68k_op_eor_32_ix           , 0xf1f8, 0xb1b0, 26},
+  {m68k_op_cmpa_32_d           , 0xf1f8, 0xb1c0,  6},
+  {m68k_op_cmpa_32_a           , 0xf1f8, 0xb1c8,  6},
+  {m68k_op_cmpa_32_ai          , 0xf1f8, 0xb1d0, 14},
+  {m68k_op_cmpa_32_pi          , 0xf1f8, 0xb1d8, 14},
+  {m68k_op_cmpa_32_pd          , 0xf1f8, 0xb1e0, 16},
+  {m68k_op_cmpa_32_di          , 0xf1f8, 0xb1e8, 18},
+  {m68k_op_cmpa_32_ix          , 0xf1f8, 0xb1f0, 20},
+  {m68k_op_and_8_er_d          , 0xf1f8, 0xc000,  4},
+  {m68k_op_and_8_er_ai         , 0xf1f8, 0xc010,  8},
+  {m68k_op_and_8_er_pi         , 0xf1f8, 0xc018,  8},
+  {m68k_op_and_8_er_pd         , 0xf1f8, 0xc020, 10},
+  {m68k_op_and_8_er_di         , 0xf1f8, 0xc028, 12},
+  {m68k_op_and_8_er_ix         , 0xf1f8, 0xc030, 14},
+  {m68k_op_and_16_er_d         , 0xf1f8, 0xc040,  4},
+  {m68k_op_and_16_er_ai        , 0xf1f8, 0xc050,  8},
+  {m68k_op_and_16_er_pi        , 0xf1f8, 0xc058,  8},
+  {m68k_op_and_16_er_pd        , 0xf1f8, 0xc060, 10},
+  {m68k_op_and_16_er_di        , 0xf1f8, 0xc068, 12},
+  {m68k_op_and_16_er_ix        , 0xf1f8, 0xc070, 14},
+  {m68k_op_and_32_er_d         , 0xf1f8, 0xc080,  8},
+  {m68k_op_and_32_er_ai        , 0xf1f8, 0xc090, 14},
+  {m68k_op_and_32_er_pi        , 0xf1f8, 0xc098, 14},
+  {m68k_op_and_32_er_pd        , 0xf1f8, 0xc0a0, 16},
+  {m68k_op_and_32_er_di        , 0xf1f8, 0xc0a8, 18},
+  {m68k_op_and_32_er_ix        , 0xf1f8, 0xc0b0, 20},
+  {m68k_op_mulu_16_d           , 0xf1f8, 0xc0c0,  0},
+  {m68k_op_mulu_16_ai          , 0xf1f8, 0xc0d0,  4},
+  {m68k_op_mulu_16_pi          , 0xf1f8, 0xc0d8,  4},
+  {m68k_op_mulu_16_pd          , 0xf1f8, 0xc0e0,  6},
+  {m68k_op_mulu_16_di          , 0xf1f8, 0xc0e8,  8},
+  {m68k_op_mulu_16_ix          , 0xf1f8, 0xc0f0, 10},
+  {m68k_op_abcd_8_rr           , 0xf1f8, 0xc100,  6},
+  {m68k_op_abcd_8_mm           , 0xf1f8, 0xc108, 18},
+  {m68k_op_and_8_re_ai         , 0xf1f8, 0xc110, 12},
+  {m68k_op_and_8_re_pi         , 0xf1f8, 0xc118, 12},
+  {m68k_op_and_8_re_pd         , 0xf1f8, 0xc120, 14},
+  {m68k_op_and_8_re_di         , 0xf1f8, 0xc128, 16},
+  {m68k_op_and_8_re_ix         , 0xf1f8, 0xc130, 18},
+  {m68k_op_exg_32_dd           , 0xf1f8, 0xc140,  6},
+  {m68k_op_exg_32_aa           , 0xf1f8, 0xc148,  6},
+  {m68k_op_and_16_re_ai        , 0xf1f8, 0xc150, 12},
+  {m68k_op_and_16_re_pi        , 0xf1f8, 0xc158, 12},
+  {m68k_op_and_16_re_pd        , 0xf1f8, 0xc160, 14},
+  {m68k_op_and_16_re_di        , 0xf1f8, 0xc168, 16},
+  {m68k_op_and_16_re_ix        , 0xf1f8, 0xc170, 18},
+  {m68k_op_exg_32_da           , 0xf1f8, 0xc188,  6},
+  {m68k_op_and_32_re_ai        , 0xf1f8, 0xc190, 20},
+  {m68k_op_and_32_re_pi        , 0xf1f8, 0xc198, 20},
+  {m68k_op_and_32_re_pd        , 0xf1f8, 0xc1a0, 22},
+  {m68k_op_and_32_re_di        , 0xf1f8, 0xc1a8, 24},
+  {m68k_op_and_32_re_ix        , 0xf1f8, 0xc1b0, 26},
+  {m68k_op_muls_16_d           , 0xf1f8, 0xc1c0,  0},
+  {m68k_op_muls_16_ai          , 0xf1f8, 0xc1d0,  4},
+  {m68k_op_muls_16_pi          , 0xf1f8, 0xc1d8,  4},
+  {m68k_op_muls_16_pd          , 0xf1f8, 0xc1e0,  6},
+  {m68k_op_muls_16_di          , 0xf1f8, 0xc1e8,  8},
+  {m68k_op_muls_16_ix          , 0xf1f8, 0xc1f0, 10},
+  {m68k_op_add_8_er_d          , 0xf1f8, 0xd000,  4},
+  {m68k_op_add_8_er_ai         , 0xf1f8, 0xd010,  8},
+  {m68k_op_add_8_er_pi         , 0xf1f8, 0xd018,  8},
+  {m68k_op_add_8_er_pd         , 0xf1f8, 0xd020, 10},
+  {m68k_op_add_8_er_di         , 0xf1f8, 0xd028, 12},
+  {m68k_op_add_8_er_ix         , 0xf1f8, 0xd030, 14},
+  {m68k_op_add_16_er_d         , 0xf1f8, 0xd040,  4},
+  {m68k_op_add_16_er_a         , 0xf1f8, 0xd048,  4},
+  {m68k_op_add_16_er_ai        , 0xf1f8, 0xd050,  8},
+  {m68k_op_add_16_er_pi        , 0xf1f8, 0xd058,  8},
+  {m68k_op_add_16_er_pd        , 0xf1f8, 0xd060, 10},
+  {m68k_op_add_16_er_di        , 0xf1f8, 0xd068, 12},
+  {m68k_op_add_16_er_ix        , 0xf1f8, 0xd070, 14},
+  {m68k_op_add_32_er_d         , 0xf1f8, 0xd080,  8},
+  {m68k_op_add_32_er_a         , 0xf1f8, 0xd088,  8},
+  {m68k_op_add_32_er_ai        , 0xf1f8, 0xd090, 14},
+  {m68k_op_add_32_er_pi        , 0xf1f8, 0xd098, 14},
+  {m68k_op_add_32_er_pd        , 0xf1f8, 0xd0a0, 16},
+  {m68k_op_add_32_er_di        , 0xf1f8, 0xd0a8, 18},
+  {m68k_op_add_32_er_ix        , 0xf1f8, 0xd0b0, 20},
+  {m68k_op_adda_16_d           , 0xf1f8, 0xd0c0,  8},
+  {m68k_op_adda_16_a           , 0xf1f8, 0xd0c8,  8},
+  {m68k_op_adda_16_ai          , 0xf1f8, 0xd0d0, 12},
+  {m68k_op_adda_16_pi          , 0xf1f8, 0xd0d8, 12},
+  {m68k_op_adda_16_pd          , 0xf1f8, 0xd0e0, 14},
+  {m68k_op_adda_16_di          , 0xf1f8, 0xd0e8, 16},
+  {m68k_op_adda_16_ix          , 0xf1f8, 0xd0f0, 18},
+  {m68k_op_addx_8_rr           , 0xf1f8, 0xd100,  4},
+  {m68k_op_addx_8_mm           , 0xf1f8, 0xd108, 18},
+  {m68k_op_add_8_re_ai         , 0xf1f8, 0xd110, 12},
+  {m68k_op_add_8_re_pi         , 0xf1f8, 0xd118, 12},
+  {m68k_op_add_8_re_pd         , 0xf1f8, 0xd120, 14},
+  {m68k_op_add_8_re_di         , 0xf1f8, 0xd128, 16},
+  {m68k_op_add_8_re_ix         , 0xf1f8, 0xd130, 18},
+  {m68k_op_addx_16_rr          , 0xf1f8, 0xd140,  4},
+  {m68k_op_addx_16_mm          , 0xf1f8, 0xd148, 18},
+  {m68k_op_add_16_re_ai        , 0xf1f8, 0xd150, 12},
+  {m68k_op_add_16_re_pi        , 0xf1f8, 0xd158, 12},
+  {m68k_op_add_16_re_pd        , 0xf1f8, 0xd160, 14},
+  {m68k_op_add_16_re_di        , 0xf1f8, 0xd168, 16},
+  {m68k_op_add_16_re_ix        , 0xf1f8, 0xd170, 18},
+  {m68k_op_addx_32_rr          , 0xf1f8, 0xd180,  8},
+  {m68k_op_addx_32_mm          , 0xf1f8, 0xd188, 30},
+  {m68k_op_add_32_re_ai        , 0xf1f8, 0xd190, 20},
+  {m68k_op_add_32_re_pi        , 0xf1f8, 0xd198, 20},
+  {m68k_op_add_32_re_pd        , 0xf1f8, 0xd1a0, 22},
+  {m68k_op_add_32_re_di        , 0xf1f8, 0xd1a8, 24},
+  {m68k_op_add_32_re_ix        , 0xf1f8, 0xd1b0, 26},
+  {m68k_op_adda_32_d           , 0xf1f8, 0xd1c0,  8},
+  {m68k_op_adda_32_a           , 0xf1f8, 0xd1c8,  8},
+  {m68k_op_adda_32_ai          , 0xf1f8, 0xd1d0, 14},
+  {m68k_op_adda_32_pi          , 0xf1f8, 0xd1d8, 14},
+  {m68k_op_adda_32_pd          , 0xf1f8, 0xd1e0, 16},
+  {m68k_op_adda_32_di          , 0xf1f8, 0xd1e8, 18},
+  {m68k_op_adda_32_ix          , 0xf1f8, 0xd1f0, 20},
+  {m68k_op_asr_8_s             , 0xf1f8, 0xe000,  6},
+  {m68k_op_lsr_8_s             , 0xf1f8, 0xe008,  6},
+  {m68k_op_roxr_8_s            , 0xf1f8, 0xe010,  6},
+  {m68k_op_ror_8_s             , 0xf1f8, 0xe018,  6},
+  {m68k_op_asr_8_r             , 0xf1f8, 0xe020,  6},
+  {m68k_op_lsr_8_r             , 0xf1f8, 0xe028,  6},
+  {m68k_op_roxr_8_r            , 0xf1f8, 0xe030,  6},
+  {m68k_op_ror_8_r             , 0xf1f8, 0xe038,  6},
+  {m68k_op_asr_16_s            , 0xf1f8, 0xe040,  6},
+  {m68k_op_lsr_16_s            , 0xf1f8, 0xe048,  6},
+  {m68k_op_roxr_16_s           , 0xf1f8, 0xe050,  6},
+  {m68k_op_ror_16_s            , 0xf1f8, 0xe058,  6},
+  {m68k_op_asr_16_r            , 0xf1f8, 0xe060,  6},
+  {m68k_op_lsr_16_r            , 0xf1f8, 0xe068,  6},
+  {m68k_op_roxr_16_r           , 0xf1f8, 0xe070,  6},
+  {m68k_op_ror_16_r            , 0xf1f8, 0xe078,  6},
+  {m68k_op_asr_32_s            , 0xf1f8, 0xe080,  8},
+  {m68k_op_lsr_32_s            , 0xf1f8, 0xe088,  8},
+  {m68k_op_roxr_32_s           , 0xf1f8, 0xe090,  8},
+  {m68k_op_ror_32_s            , 0xf1f8, 0xe098,  8},
+  {m68k_op_asr_32_r            , 0xf1f8, 0xe0a0,  8},
+  {m68k_op_lsr_32_r            , 0xf1f8, 0xe0a8,  8},
+  {m68k_op_roxr_32_r           , 0xf1f8, 0xe0b0,  8},
+  {m68k_op_ror_32_r            , 0xf1f8, 0xe0b8,  8},
+  {m68k_op_asl_8_s             , 0xf1f8, 0xe100,  6},
+  {m68k_op_lsl_8_s             , 0xf1f8, 0xe108,  6},
+  {m68k_op_roxl_8_s            , 0xf1f8, 0xe110,  6},
+  {m68k_op_rol_8_s             , 0xf1f8, 0xe118,  6},
+  {m68k_op_asl_8_r             , 0xf1f8, 0xe120,  6},
+  {m68k_op_lsl_8_r             , 0xf1f8, 0xe128,  6},
+  {m68k_op_roxl_8_r            , 0xf1f8, 0xe130,  6},
+  {m68k_op_rol_8_r             , 0xf1f8, 0xe138,  6},
+  {m68k_op_asl_16_s            , 0xf1f8, 0xe140,  6},
+  {m68k_op_lsl_16_s            , 0xf1f8, 0xe148,  6},
+  {m68k_op_roxl_16_s           , 0xf1f8, 0xe150,  6},
+  {m68k_op_rol_16_s            , 0xf1f8, 0xe158,  6},
+  {m68k_op_asl_16_r            , 0xf1f8, 0xe160,  6},
+  {m68k_op_lsl_16_r            , 0xf1f8, 0xe168,  6},
+  {m68k_op_roxl_16_r           , 0xf1f8, 0xe170,  6},
+  {m68k_op_rol_16_r            , 0xf1f8, 0xe178,  6},
+  {m68k_op_asl_32_s            , 0xf1f8, 0xe180,  8},
+  {m68k_op_lsl_32_s            , 0xf1f8, 0xe188,  8},
+  {m68k_op_roxl_32_s           , 0xf1f8, 0xe190,  8},
+  {m68k_op_rol_32_s            , 0xf1f8, 0xe198,  8},
+  {m68k_op_asl_32_r            , 0xf1f8, 0xe1a0,  8},
+  {m68k_op_lsl_32_r            , 0xf1f8, 0xe1a8,  8},
+  {m68k_op_roxl_32_r           , 0xf1f8, 0xe1b0,  8},
+  {m68k_op_rol_32_r            , 0xf1f8, 0xe1b8,  8},
+  {m68k_op_trap                , 0xfff0, 0x4e40,  4},
+  {m68k_op_btst_8_r_pi7        , 0xf1ff, 0x011f,  8},
+  {m68k_op_btst_8_r_pd7        , 0xf1ff, 0x0127, 10},
+  {m68k_op_btst_8_r_aw         , 0xf1ff, 0x0138, 12},
+  {m68k_op_btst_8_r_al         , 0xf1ff, 0x0139, 16},
+  {m68k_op_btst_8_r_pcdi       , 0xf1ff, 0x013a, 12},
+  {m68k_op_btst_8_r_pcix       , 0xf1ff, 0x013b, 14},
+  {m68k_op_btst_8_r_i          , 0xf1ff, 0x013c, 10},
+  {m68k_op_bchg_8_r_pi7        , 0xf1ff, 0x015f, 12},
+  {m68k_op_bchg_8_r_pd7        , 0xf1ff, 0x0167, 14},
+  {m68k_op_bchg_8_r_aw         , 0xf1ff, 0x0178, 16},
+  {m68k_op_bchg_8_r_al         , 0xf1ff, 0x0179, 20},
+  {m68k_op_bclr_8_r_pi7        , 0xf1ff, 0x019f, 12},
+  {m68k_op_bclr_8_r_pd7        , 0xf1ff, 0x01a7, 14},
+  {m68k_op_bclr_8_r_aw         , 0xf1ff, 0x01b8, 16},
+  {m68k_op_bclr_8_r_al         , 0xf1ff, 0x01b9, 20},
+  {m68k_op_bset_8_r_pi7        , 0xf1ff, 0x01df, 12},
+  {m68k_op_bset_8_r_pd7        , 0xf1ff, 0x01e7, 14},
+  {m68k_op_bset_8_r_aw         , 0xf1ff, 0x01f8, 16},
+  {m68k_op_bset_8_r_al         , 0xf1ff, 0x01f9, 20},
+  {m68k_op_move_8_d_pi7        , 0xf1ff, 0x101f,  8},
+  {m68k_op_move_8_d_pd7        , 0xf1ff, 0x1027, 10},
+  {m68k_op_move_8_d_aw         , 0xf1ff, 0x1038, 12},
+  {m68k_op_move_8_d_al         , 0xf1ff, 0x1039, 16},
+  {m68k_op_move_8_d_pcdi       , 0xf1ff, 0x103a, 12},
+  {m68k_op_move_8_d_pcix       , 0xf1ff, 0x103b, 14},
+  {m68k_op_move_8_d_i          , 0xf1ff, 0x103c,  8},
+  {m68k_op_move_8_ai_pi7       , 0xf1ff, 0x109f, 12},
+  {m68k_op_move_8_ai_pd7       , 0xf1ff, 0x10a7, 14},
+  {m68k_op_move_8_ai_aw        , 0xf1ff, 0x10b8, 16},
+  {m68k_op_move_8_ai_al        , 0xf1ff, 0x10b9, 20},
+  {m68k_op_move_8_ai_pcdi      , 0xf1ff, 0x10ba, 16},
+  {m68k_op_move_8_ai_pcix      , 0xf1ff, 0x10bb, 18},
+  {m68k_op_move_8_ai_i         , 0xf1ff, 0x10bc, 12},
+  {m68k_op_move_8_pi_pi7       , 0xf1ff, 0x10df, 12},
+  {m68k_op_move_8_pi_pd7       , 0xf1ff, 0x10e7, 14},
+  {m68k_op_move_8_pi_aw        , 0xf1ff, 0x10f8, 16},
+  {m68k_op_move_8_pi_al        , 0xf1ff, 0x10f9, 20},
+  {m68k_op_move_8_pi_pcdi      , 0xf1ff, 0x10fa, 16},
+  {m68k_op_move_8_pi_pcix      , 0xf1ff, 0x10fb, 18},
+  {m68k_op_move_8_pi_i         , 0xf1ff, 0x10fc, 12},
+  {m68k_op_move_8_pd_pi7       , 0xf1ff, 0x111f, 12},
+  {m68k_op_move_8_pd_pd7       , 0xf1ff, 0x1127, 14},
+  {m68k_op_move_8_pd_aw        , 0xf1ff, 0x1138, 16},
+  {m68k_op_move_8_pd_al        , 0xf1ff, 0x1139, 20},
+  {m68k_op_move_8_pd_pcdi      , 0xf1ff, 0x113a, 16},
+  {m68k_op_move_8_pd_pcix      , 0xf1ff, 0x113b, 18},
+  {m68k_op_move_8_pd_i         , 0xf1ff, 0x113c, 12},
+  {m68k_op_move_8_di_pi7       , 0xf1ff, 0x115f, 16},
+  {m68k_op_move_8_di_pd7       , 0xf1ff, 0x1167, 18},
+  {m68k_op_move_8_di_aw        , 0xf1ff, 0x1178, 20},
+  {m68k_op_move_8_di_al        , 0xf1ff, 0x1179, 24},
+  {m68k_op_move_8_di_pcdi      , 0xf1ff, 0x117a, 20},
+  {m68k_op_move_8_di_pcix      , 0xf1ff, 0x117b, 22},
+  {m68k_op_move_8_di_i         , 0xf1ff, 0x117c, 16},
+  {m68k_op_move_8_ix_pi7       , 0xf1ff, 0x119f, 18},
+  {m68k_op_move_8_ix_pd7       , 0xf1ff, 0x11a7, 20},
+  {m68k_op_move_8_ix_aw        , 0xf1ff, 0x11b8, 22},
+  {m68k_op_move_8_ix_al        , 0xf1ff, 0x11b9, 26},
+  {m68k_op_move_8_ix_pcdi      , 0xf1ff, 0x11ba, 22},
+  {m68k_op_move_8_ix_pcix      , 0xf1ff, 0x11bb, 24},
+  {m68k_op_move_8_ix_i         , 0xf1ff, 0x11bc, 18},
+  {m68k_op_move_32_d_aw        , 0xf1ff, 0x2038, 16},
+  {m68k_op_move_32_d_al        , 0xf1ff, 0x2039, 20},
+  {m68k_op_move_32_d_pcdi      , 0xf1ff, 0x203a, 16},
+  {m68k_op_move_32_d_pcix      , 0xf1ff, 0x203b, 18},
+  {m68k_op_move_32_d_i         , 0xf1ff, 0x203c, 12},
+  {m68k_op_movea_32_aw         , 0xf1ff, 0x2078, 16},
+  {m68k_op_movea_32_al         , 0xf1ff, 0x2079, 20},
+  {m68k_op_movea_32_pcdi       , 0xf1ff, 0x207a, 16},
+  {m68k_op_movea_32_pcix       , 0xf1ff, 0x207b, 18},
+  {m68k_op_movea_32_i          , 0xf1ff, 0x207c, 12},
+  {m68k_op_move_32_ai_aw       , 0xf1ff, 0x20b8, 24},
+  {m68k_op_move_32_ai_al       , 0xf1ff, 0x20b9, 28},
+  {m68k_op_move_32_ai_pcdi     , 0xf1ff, 0x20ba, 24},
+  {m68k_op_move_32_ai_pcix     , 0xf1ff, 0x20bb, 26},
+  {m68k_op_move_32_ai_i        , 0xf1ff, 0x20bc, 20},
+  {m68k_op_move_32_pi_aw       , 0xf1ff, 0x20f8, 24},
+  {m68k_op_move_32_pi_al       , 0xf1ff, 0x20f9, 28},
+  {m68k_op_move_32_pi_pcdi     , 0xf1ff, 0x20fa, 24},
+  {m68k_op_move_32_pi_pcix     , 0xf1ff, 0x20fb, 26},
+  {m68k_op_move_32_pi_i        , 0xf1ff, 0x20fc, 20},
+  {m68k_op_move_32_pd_aw       , 0xf1ff, 0x2138, 24},
+  {m68k_op_move_32_pd_al       , 0xf1ff, 0x2139, 28},
+  {m68k_op_move_32_pd_pcdi     , 0xf1ff, 0x213a, 24},
+  {m68k_op_move_32_pd_pcix     , 0xf1ff, 0x213b, 26},
+  {m68k_op_move_32_pd_i        , 0xf1ff, 0x213c, 20},
+  {m68k_op_move_32_di_aw       , 0xf1ff, 0x2178, 28},
+  {m68k_op_move_32_di_al       , 0xf1ff, 0x2179, 32},
+  {m68k_op_move_32_di_pcdi     , 0xf1ff, 0x217a, 28},
+  {m68k_op_move_32_di_pcix     , 0xf1ff, 0x217b, 30},
+  {m68k_op_move_32_di_i        , 0xf1ff, 0x217c, 24},
+  {m68k_op_move_32_ix_aw       , 0xf1ff, 0x21b8, 30},
+  {m68k_op_move_32_ix_al       , 0xf1ff, 0x21b9, 34},
+  {m68k_op_move_32_ix_pcdi     , 0xf1ff, 0x21ba, 30},
+  {m68k_op_move_32_ix_pcix     , 0xf1ff, 0x21bb, 32},
+  {m68k_op_move_32_ix_i        , 0xf1ff, 0x21bc, 26},
+  {m68k_op_move_16_d_aw        , 0xf1ff, 0x3038, 12},
+  {m68k_op_move_16_d_al        , 0xf1ff, 0x3039, 16},
+  {m68k_op_move_16_d_pcdi      , 0xf1ff, 0x303a, 12},
+  {m68k_op_move_16_d_pcix      , 0xf1ff, 0x303b, 14},
+  {m68k_op_move_16_d_i         , 0xf1ff, 0x303c,  8},
+  {m68k_op_movea_16_aw         , 0xf1ff, 0x3078, 12},
+  {m68k_op_movea_16_al         , 0xf1ff, 0x3079, 16},
+  {m68k_op_movea_16_pcdi       , 0xf1ff, 0x307a, 12},
+  {m68k_op_movea_16_pcix       , 0xf1ff, 0x307b, 14},
+  {m68k_op_movea_16_i          , 0xf1ff, 0x307c,  8},
+  {m68k_op_move_16_ai_aw       , 0xf1ff, 0x30b8, 16},
+  {m68k_op_move_16_ai_al       , 0xf1ff, 0x30b9, 20},
+  {m68k_op_move_16_ai_pcdi     , 0xf1ff, 0x30ba, 16},
+  {m68k_op_move_16_ai_pcix     , 0xf1ff, 0x30bb, 18},
+  {m68k_op_move_16_ai_i        , 0xf1ff, 0x30bc, 12},
+  {m68k_op_move_16_pi_aw       , 0xf1ff, 0x30f8, 16},
+  {m68k_op_move_16_pi_al       , 0xf1ff, 0x30f9, 20},
+  {m68k_op_move_16_pi_pcdi     , 0xf1ff, 0x30fa, 16},
+  {m68k_op_move_16_pi_pcix     , 0xf1ff, 0x30fb, 18},
+  {m68k_op_move_16_pi_i        , 0xf1ff, 0x30fc, 12},
+  {m68k_op_move_16_pd_aw       , 0xf1ff, 0x3138, 16},
+  {m68k_op_move_16_pd_al       , 0xf1ff, 0x3139, 20},
+  {m68k_op_move_16_pd_pcdi     , 0xf1ff, 0x313a, 16},
+  {m68k_op_move_16_pd_pcix     , 0xf1ff, 0x313b, 18},
+  {m68k_op_move_16_pd_i        , 0xf1ff, 0x313c, 12},
+  {m68k_op_move_16_di_aw       , 0xf1ff, 0x3178, 20},
+  {m68k_op_move_16_di_al       , 0xf1ff, 0x3179, 24},
+  {m68k_op_move_16_di_pcdi     , 0xf1ff, 0x317a, 20},
+  {m68k_op_move_16_di_pcix     , 0xf1ff, 0x317b, 22},
+  {m68k_op_move_16_di_i        , 0xf1ff, 0x317c, 16},
+  {m68k_op_move_16_ix_aw       , 0xf1ff, 0x31b8, 22},
+  {m68k_op_move_16_ix_al       , 0xf1ff, 0x31b9, 26},
+  {m68k_op_move_16_ix_pcdi     , 0xf1ff, 0x31ba, 22},
+  {m68k_op_move_16_ix_pcix     , 0xf1ff, 0x31bb, 24},
+  {m68k_op_move_16_ix_i        , 0xf1ff, 0x31bc, 18},
+  {m68k_op_chk_16_aw           , 0xf1ff, 0x41b8, 18},
+  {m68k_op_chk_16_al           , 0xf1ff, 0x41b9, 22},
+  {m68k_op_chk_16_pcdi         , 0xf1ff, 0x41ba, 18},
+  {m68k_op_chk_16_pcix         , 0xf1ff, 0x41bb, 20},
+  {m68k_op_chk_16_i            , 0xf1ff, 0x41bc, 14},
+  {m68k_op_lea_32_aw           , 0xf1ff, 0x41f8,  8},
+  {m68k_op_lea_32_al           , 0xf1ff, 0x41f9, 12},
+  {m68k_op_lea_32_pcdi         , 0xf1ff, 0x41fa,  8},
+  {m68k_op_lea_32_pcix         , 0xf1ff, 0x41fb, 12},
+  {m68k_op_addq_8_pi7          , 0xf1ff, 0x501f, 12},
+  {m68k_op_addq_8_pd7          , 0xf1ff, 0x5027, 14},
+  {m68k_op_addq_8_aw           , 0xf1ff, 0x5038, 16},
+  {m68k_op_addq_8_al           , 0xf1ff, 0x5039, 20},
+  {m68k_op_addq_16_aw          , 0xf1ff, 0x5078, 16},
+  {m68k_op_addq_16_al          , 0xf1ff, 0x5079, 20},
+  {m68k_op_addq_32_aw          , 0xf1ff, 0x50b8, 24},
+  {m68k_op_addq_32_al          , 0xf1ff, 0x50b9, 28},
+  {m68k_op_subq_8_pi7          , 0xf1ff, 0x511f, 12},
+  {m68k_op_subq_8_pd7          , 0xf1ff, 0x5127, 14},
+  {m68k_op_subq_8_aw           , 0xf1ff, 0x5138, 16},
+  {m68k_op_subq_8_al           , 0xf1ff, 0x5139, 20},
+  {m68k_op_subq_16_aw          , 0xf1ff, 0x5178, 16},
+  {m68k_op_subq_16_al          , 0xf1ff, 0x5179, 20},
+  {m68k_op_subq_32_aw          , 0xf1ff, 0x51b8, 24},
+  {m68k_op_subq_32_al          , 0xf1ff, 0x51b9, 28},
+  {m68k_op_or_8_er_pi7         , 0xf1ff, 0x801f,  8},
+  {m68k_op_or_8_er_pd7         , 0xf1ff, 0x8027, 10},
+  {m68k_op_or_8_er_aw          , 0xf1ff, 0x8038, 12},
+  {m68k_op_or_8_er_al          , 0xf1ff, 0x8039, 16},
+  {m68k_op_or_8_er_pcdi        , 0xf1ff, 0x803a, 12},
+  {m68k_op_or_8_er_pcix        , 0xf1ff, 0x803b, 14},
+  {m68k_op_or_8_er_i           , 0xf1ff, 0x803c,  8},
+  {m68k_op_or_16_er_aw         , 0xf1ff, 0x8078, 12},
+  {m68k_op_or_16_er_al         , 0xf1ff, 0x8079, 16},
+  {m68k_op_or_16_er_pcdi       , 0xf1ff, 0x807a, 12},
+  {m68k_op_or_16_er_pcix       , 0xf1ff, 0x807b, 14},
+  {m68k_op_or_16_er_i          , 0xf1ff, 0x807c,  8},
+  {m68k_op_or_32_er_aw         , 0xf1ff, 0x80b8, 18},
+  {m68k_op_or_32_er_al         , 0xf1ff, 0x80b9, 22},
+  {m68k_op_or_32_er_pcdi       , 0xf1ff, 0x80ba, 18},
+  {m68k_op_or_32_er_pcix       , 0xf1ff, 0x80bb, 20},
+  {m68k_op_or_32_er_i          , 0xf1ff, 0x80bc, 16},
+  {m68k_op_divu_16_aw          , 0xf1ff, 0x80f8,  8},
+  {m68k_op_divu_16_al          , 0xf1ff, 0x80f9, 12},
+  {m68k_op_divu_16_pcdi        , 0xf1ff, 0x80fa,  8},
+  {m68k_op_divu_16_pcix        , 0xf1ff, 0x80fb, 10},
+  {m68k_op_divu_16_i           , 0xf1ff, 0x80fc,  4},
+  {m68k_op_sbcd_8_mm_ay7       , 0xf1ff, 0x810f, 18},
+  {m68k_op_or_8_re_pi7         , 0xf1ff, 0x811f, 12},
+  {m68k_op_or_8_re_pd7         , 0xf1ff, 0x8127, 14},
+  {m68k_op_or_8_re_aw          , 0xf1ff, 0x8138, 16},
+  {m68k_op_or_8_re_al          , 0xf1ff, 0x8139, 20},
+  {m68k_op_or_16_re_aw         , 0xf1ff, 0x8178, 16},
+  {m68k_op_or_16_re_al         , 0xf1ff, 0x8179, 20},
+  {m68k_op_or_32_re_aw         , 0xf1ff, 0x81b8, 24},
+  {m68k_op_or_32_re_al         , 0xf1ff, 0x81b9, 28},
+  {m68k_op_divs_16_aw          , 0xf1ff, 0x81f8,  8},
+  {m68k_op_divs_16_al          , 0xf1ff, 0x81f9, 12},
+  {m68k_op_divs_16_pcdi        , 0xf1ff, 0x81fa,  8},
+  {m68k_op_divs_16_pcix        , 0xf1ff, 0x81fb, 10},
+  {m68k_op_divs_16_i           , 0xf1ff, 0x81fc,  4},
+  {m68k_op_sub_8_er_pi7        , 0xf1ff, 0x901f,  8},
+  {m68k_op_sub_8_er_pd7        , 0xf1ff, 0x9027, 10},
+  {m68k_op_sub_8_er_aw         , 0xf1ff, 0x9038, 12},
+  {m68k_op_sub_8_er_al         , 0xf1ff, 0x9039, 16},
+  {m68k_op_sub_8_er_pcdi       , 0xf1ff, 0x903a, 12},
+  {m68k_op_sub_8_er_pcix       , 0xf1ff, 0x903b, 14},
+  {m68k_op_sub_8_er_i          , 0xf1ff, 0x903c,  8},
+  {m68k_op_sub_16_er_aw        , 0xf1ff, 0x9078, 12},
+  {m68k_op_sub_16_er_al        , 0xf1ff, 0x9079, 16},
+  {m68k_op_sub_16_er_pcdi      , 0xf1ff, 0x907a, 12},
+  {m68k_op_sub_16_er_pcix      , 0xf1ff, 0x907b, 14},
+  {m68k_op_sub_16_er_i         , 0xf1ff, 0x907c,  8},
+  {m68k_op_sub_32_er_aw        , 0xf1ff, 0x90b8, 18},
+  {m68k_op_sub_32_er_al        , 0xf1ff, 0x90b9, 22},
+  {m68k_op_sub_32_er_pcdi      , 0xf1ff, 0x90ba, 18},
+  {m68k_op_sub_32_er_pcix      , 0xf1ff, 0x90bb, 20},
+  {m68k_op_sub_32_er_i         , 0xf1ff, 0x90bc, 16},
+  {m68k_op_suba_16_aw          , 0xf1ff, 0x90f8, 16},
+  {m68k_op_suba_16_al          , 0xf1ff, 0x90f9, 20},
+  {m68k_op_suba_16_pcdi        , 0xf1ff, 0x90fa, 16},
+  {m68k_op_suba_16_pcix        , 0xf1ff, 0x90fb, 18},
+  {m68k_op_suba_16_i           , 0xf1ff, 0x90fc, 12},
+  {m68k_op_subx_8_mm_ay7       , 0xf1ff, 0x910f, 18},
+  {m68k_op_sub_8_re_pi7        , 0xf1ff, 0x911f, 12},
+  {m68k_op_sub_8_re_pd7        , 0xf1ff, 0x9127, 14},
+  {m68k_op_sub_8_re_aw         , 0xf1ff, 0x9138, 16},
+  {m68k_op_sub_8_re_al         , 0xf1ff, 0x9139, 20},
+  {m68k_op_sub_16_re_aw        , 0xf1ff, 0x9178, 16},
+  {m68k_op_sub_16_re_al        , 0xf1ff, 0x9179, 20},
+  {m68k_op_sub_32_re_aw        , 0xf1ff, 0x91b8, 24},
+  {m68k_op_sub_32_re_al        , 0xf1ff, 0x91b9, 28},
+  {m68k_op_suba_32_aw          , 0xf1ff, 0x91f8, 18},
+  {m68k_op_suba_32_al          , 0xf1ff, 0x91f9, 22},
+  {m68k_op_suba_32_pcdi        , 0xf1ff, 0x91fa, 18},
+  {m68k_op_suba_32_pcix        , 0xf1ff, 0x91fb, 20},
+  {m68k_op_suba_32_i           , 0xf1ff, 0x91fc, 16},
+  {m68k_op_cmp_8_pi7           , 0xf1ff, 0xb01f,  8},
+  {m68k_op_cmp_8_pd7           , 0xf1ff, 0xb027, 10},
+  {m68k_op_cmp_8_aw            , 0xf1ff, 0xb038, 12},
+  {m68k_op_cmp_8_al            , 0xf1ff, 0xb039, 16},
+  {m68k_op_cmp_8_pcdi          , 0xf1ff, 0xb03a, 12},
+  {m68k_op_cmp_8_pcix          , 0xf1ff, 0xb03b, 14},
+  {m68k_op_cmp_8_i             , 0xf1ff, 0xb03c,  8},
+  {m68k_op_cmp_16_aw           , 0xf1ff, 0xb078, 12},
+  {m68k_op_cmp_16_al           , 0xf1ff, 0xb079, 16},
+  {m68k_op_cmp_16_pcdi         , 0xf1ff, 0xb07a, 12},
+  {m68k_op_cmp_16_pcix         , 0xf1ff, 0xb07b, 14},
+  {m68k_op_cmp_16_i            , 0xf1ff, 0xb07c,  8},
+  {m68k_op_cmp_32_aw           , 0xf1ff, 0xb0b8, 18},
+  {m68k_op_cmp_32_al           , 0xf1ff, 0xb0b9, 22},
+  {m68k_op_cmp_32_pcdi         , 0xf1ff, 0xb0ba, 18},
+  {m68k_op_cmp_32_pcix         , 0xf1ff, 0xb0bb, 20},
+  {m68k_op_cmp_32_i            , 0xf1ff, 0xb0bc, 14},
+  {m68k_op_cmpa_16_aw          , 0xf1ff, 0xb0f8, 14},
+  {m68k_op_cmpa_16_al          , 0xf1ff, 0xb0f9, 18},
+  {m68k_op_cmpa_16_pcdi        , 0xf1ff, 0xb0fa, 14},
+  {m68k_op_cmpa_16_pcix        , 0xf1ff, 0xb0fb, 16},
+  {m68k_op_cmpa_16_i           , 0xf1ff, 0xb0fc, 10},
+  {m68k_op_cmpm_8_ay7          , 0xf1ff, 0xb10f, 12},
+  {m68k_op_eor_8_pi7           , 0xf1ff, 0xb11f, 12},
+  {m68k_op_eor_8_pd7           , 0xf1ff, 0xb127, 14},
+  {m68k_op_eor_8_aw            , 0xf1ff, 0xb138, 16},
+  {m68k_op_eor_8_al            , 0xf1ff, 0xb139, 20},
+  {m68k_op_eor_16_aw           , 0xf1ff, 0xb178, 16},
+  {m68k_op_eor_16_al           , 0xf1ff, 0xb179, 20},
+  {m68k_op_eor_32_aw           , 0xf1ff, 0xb1b8, 24},
+  {m68k_op_eor_32_al           , 0xf1ff, 0xb1b9, 28},
+  {m68k_op_cmpa_32_aw          , 0xf1ff, 0xb1f8, 18},
+  {m68k_op_cmpa_32_al          , 0xf1ff, 0xb1f9, 22},
+  {m68k_op_cmpa_32_pcdi        , 0xf1ff, 0xb1fa, 18},
+  {m68k_op_cmpa_32_pcix        , 0xf1ff, 0xb1fb, 20},
+  {m68k_op_cmpa_32_i           , 0xf1ff, 0xb1fc, 14},
+  {m68k_op_and_8_er_pi7        , 0xf1ff, 0xc01f,  8},
+  {m68k_op_and_8_er_pd7        , 0xf1ff, 0xc027, 10},
+  {m68k_op_and_8_er_aw         , 0xf1ff, 0xc038, 12},
+  {m68k_op_and_8_er_al         , 0xf1ff, 0xc039, 16},
+  {m68k_op_and_8_er_pcdi       , 0xf1ff, 0xc03a, 12},
+  {m68k_op_and_8_er_pcix       , 0xf1ff, 0xc03b, 14},
+  {m68k_op_and_8_er_i          , 0xf1ff, 0xc03c,  8},
+  {m68k_op_and_16_er_aw        , 0xf1ff, 0xc078, 12},
+  {m68k_op_and_16_er_al        , 0xf1ff, 0xc079, 16},
+  {m68k_op_and_16_er_pcdi      , 0xf1ff, 0xc07a, 12},
+  {m68k_op_and_16_er_pcix      , 0xf1ff, 0xc07b, 14},
+  {m68k_op_and_16_er_i         , 0xf1ff, 0xc07c,  8},
+  {m68k_op_and_32_er_aw        , 0xf1ff, 0xc0b8, 18},
+  {m68k_op_and_32_er_al        , 0xf1ff, 0xc0b9, 22},
+  {m68k_op_and_32_er_pcdi      , 0xf1ff, 0xc0ba, 18},
+  {m68k_op_and_32_er_pcix      , 0xf1ff, 0xc0bb, 20},
+  {m68k_op_and_32_er_i         , 0xf1ff, 0xc0bc, 16},
+  {m68k_op_mulu_16_aw          , 0xf1ff, 0xc0f8,  8},
+  {m68k_op_mulu_16_al          , 0xf1ff, 0xc0f9, 12},
+  {m68k_op_mulu_16_pcdi        , 0xf1ff, 0xc0fa,  8},
+  {m68k_op_mulu_16_pcix        , 0xf1ff, 0xc0fb, 10},
+  {m68k_op_mulu_16_i           , 0xf1ff, 0xc0fc,  4},
+  {m68k_op_abcd_8_mm_ay7       , 0xf1ff, 0xc10f, 18},
+  {m68k_op_and_8_re_pi7        , 0xf1ff, 0xc11f, 12},
+  {m68k_op_and_8_re_pd7        , 0xf1ff, 0xc127, 14},
+  {m68k_op_and_8_re_aw         , 0xf1ff, 0xc138, 16},
+  {m68k_op_and_8_re_al         , 0xf1ff, 0xc139, 20},
+  {m68k_op_and_16_re_aw        , 0xf1ff, 0xc178, 16},
+  {m68k_op_and_16_re_al        , 0xf1ff, 0xc179, 20},
+  {m68k_op_and_32_re_aw        , 0xf1ff, 0xc1b8, 24},
+  {m68k_op_and_32_re_al        , 0xf1ff, 0xc1b9, 28},
+  {m68k_op_muls_16_aw          , 0xf1ff, 0xc1f8,  8},
+  {m68k_op_muls_16_al          , 0xf1ff, 0xc1f9, 12},
+  {m68k_op_muls_16_pcdi        , 0xf1ff, 0xc1fa,  8},
+  {m68k_op_muls_16_pcix        , 0xf1ff, 0xc1fb, 10},
+  {m68k_op_muls_16_i           , 0xf1ff, 0xc1fc,  4},
+  {m68k_op_add_8_er_pi7        , 0xf1ff, 0xd01f,  8},
+  {m68k_op_add_8_er_pd7        , 0xf1ff, 0xd027, 10},
+  {m68k_op_add_8_er_aw         , 0xf1ff, 0xd038, 12},
+  {m68k_op_add_8_er_al         , 0xf1ff, 0xd039, 16},
+  {m68k_op_add_8_er_pcdi       , 0xf1ff, 0xd03a, 12},
+  {m68k_op_add_8_er_pcix       , 0xf1ff, 0xd03b, 14},
+  {m68k_op_add_8_er_i          , 0xf1ff, 0xd03c,  8},
+  {m68k_op_add_16_er_aw        , 0xf1ff, 0xd078, 12},
+  {m68k_op_add_16_er_al        , 0xf1ff, 0xd079, 16},
+  {m68k_op_add_16_er_pcdi      , 0xf1ff, 0xd07a, 12},
+  {m68k_op_add_16_er_pcix      , 0xf1ff, 0xd07b, 14},
+  {m68k_op_add_16_er_i         , 0xf1ff, 0xd07c,  8},
+  {m68k_op_add_32_er_aw        , 0xf1ff, 0xd0b8, 18},
+  {m68k_op_add_32_er_al        , 0xf1ff, 0xd0b9, 22},
+  {m68k_op_add_32_er_pcdi      , 0xf1ff, 0xd0ba, 18},
+  {m68k_op_add_32_er_pcix      , 0xf1ff, 0xd0bb, 20},
+  {m68k_op_add_32_er_i         , 0xf1ff, 0xd0bc, 16},
+  {m68k_op_adda_16_aw          , 0xf1ff, 0xd0f8, 16},
+  {m68k_op_adda_16_al          , 0xf1ff, 0xd0f9, 20},
+  {m68k_op_adda_16_pcdi        , 0xf1ff, 0xd0fa, 16},
+  {m68k_op_adda_16_pcix        , 0xf1ff, 0xd0fb, 18},
+  {m68k_op_adda_16_i           , 0xf1ff, 0xd0fc, 12},
+  {m68k_op_addx_8_mm_ay7       , 0xf1ff, 0xd10f, 18},
+  {m68k_op_add_8_re_pi7        , 0xf1ff, 0xd11f, 12},
+  {m68k_op_add_8_re_pd7        , 0xf1ff, 0xd127, 14},
+  {m68k_op_add_8_re_aw         , 0xf1ff, 0xd138, 16},
+  {m68k_op_add_8_re_al         , 0xf1ff, 0xd139, 20},
+  {m68k_op_add_16_re_aw        , 0xf1ff, 0xd178, 16},
+  {m68k_op_add_16_re_al        , 0xf1ff, 0xd179, 20},
+  {m68k_op_add_32_re_aw        , 0xf1ff, 0xd1b8, 24},
+  {m68k_op_add_32_re_al        , 0xf1ff, 0xd1b9, 28},
+  {m68k_op_adda_32_aw          , 0xf1ff, 0xd1f8, 18},
+  {m68k_op_adda_32_al          , 0xf1ff, 0xd1f9, 22},
+  {m68k_op_adda_32_pcdi        , 0xf1ff, 0xd1fa, 18},
+  {m68k_op_adda_32_pcix        , 0xf1ff, 0xd1fb, 20},
+  {m68k_op_adda_32_i           , 0xf1ff, 0xd1fc, 16},
+  {m68k_op_ori_8_d             , 0xfff8, 0x0000,  8},
+  {m68k_op_ori_8_ai            , 0xfff8, 0x0010, 16},
+  {m68k_op_ori_8_pi            , 0xfff8, 0x0018, 16},
+  {m68k_op_ori_8_pd            , 0xfff8, 0x0020, 18},
+  {m68k_op_ori_8_di            , 0xfff8, 0x0028, 20},
+  {m68k_op_ori_8_ix            , 0xfff8, 0x0030, 22},
+  {m68k_op_ori_16_d            , 0xfff8, 0x0040,  8},
+  {m68k_op_ori_16_ai           , 0xfff8, 0x0050, 16},
+  {m68k_op_ori_16_pi           , 0xfff8, 0x0058, 16},
+  {m68k_op_ori_16_pd           , 0xfff8, 0x0060, 18},
+  {m68k_op_ori_16_di           , 0xfff8, 0x0068, 20},
+  {m68k_op_ori_16_ix           , 0xfff8, 0x0070, 22},
+  {m68k_op_ori_32_d            , 0xfff8, 0x0080, 16},
+  {m68k_op_ori_32_ai           , 0xfff8, 0x0090, 28},
+  {m68k_op_ori_32_pi           , 0xfff8, 0x0098, 28},
+  {m68k_op_ori_32_pd           , 0xfff8, 0x00a0, 30},
+  {m68k_op_ori_32_di           , 0xfff8, 0x00a8, 32},
+  {m68k_op_ori_32_ix           , 0xfff8, 0x00b0, 34},
+  {m68k_op_andi_8_d            , 0xfff8, 0x0200,  8},
+  {m68k_op_andi_8_ai           , 0xfff8, 0x0210, 16},
+  {m68k_op_andi_8_pi           , 0xfff8, 0x0218, 16},
+  {m68k_op_andi_8_pd           , 0xfff8, 0x0220, 18},
+  {m68k_op_andi_8_di           , 0xfff8, 0x0228, 20},
+  {m68k_op_andi_8_ix           , 0xfff8, 0x0230, 22},
+  {m68k_op_andi_16_d           , 0xfff8, 0x0240,  8},
+  {m68k_op_andi_16_ai          , 0xfff8, 0x0250, 16},
+  {m68k_op_andi_16_pi          , 0xfff8, 0x0258, 16},
+  {m68k_op_andi_16_pd          , 0xfff8, 0x0260, 18},
+  {m68k_op_andi_16_di          , 0xfff8, 0x0268, 20},
+  {m68k_op_andi_16_ix          , 0xfff8, 0x0270, 22},
+  {m68k_op_andi_32_d           , 0xfff8, 0x0280, 16}, /* see Yacht.txt */
+  {m68k_op_andi_32_ai          , 0xfff8, 0x0290, 28},
+  {m68k_op_andi_32_pi          , 0xfff8, 0x0298, 28},
+  {m68k_op_andi_32_pd          , 0xfff8, 0x02a0, 30},
+  {m68k_op_andi_32_di          , 0xfff8, 0x02a8, 32},
+  {m68k_op_andi_32_ix          , 0xfff8, 0x02b0, 34},
+  {m68k_op_subi_8_d            , 0xfff8, 0x0400,  8},
+  {m68k_op_subi_8_ai           , 0xfff8, 0x0410, 16},
+  {m68k_op_subi_8_pi           , 0xfff8, 0x0418, 16},
+  {m68k_op_subi_8_pd           , 0xfff8, 0x0420, 18},
+  {m68k_op_subi_8_di           , 0xfff8, 0x0428, 20},
+  {m68k_op_subi_8_ix           , 0xfff8, 0x0430, 22},
+  {m68k_op_subi_16_d           , 0xfff8, 0x0440,  8},
+  {m68k_op_subi_16_ai          , 0xfff8, 0x0450, 16},
+  {m68k_op_subi_16_pi          , 0xfff8, 0x0458, 16},
+  {m68k_op_subi_16_pd          , 0xfff8, 0x0460, 18},
+  {m68k_op_subi_16_di          , 0xfff8, 0x0468, 20},
+  {m68k_op_subi_16_ix          , 0xfff8, 0x0470, 22},
+  {m68k_op_subi_32_d           , 0xfff8, 0x0480, 16},
+  {m68k_op_subi_32_ai          , 0xfff8, 0x0490, 28},
+  {m68k_op_subi_32_pi          , 0xfff8, 0x0498, 28},
+  {m68k_op_subi_32_pd          , 0xfff8, 0x04a0, 30},
+  {m68k_op_subi_32_di          , 0xfff8, 0x04a8, 32},
+  {m68k_op_subi_32_ix          , 0xfff8, 0x04b0, 34},
+  {m68k_op_addi_8_d            , 0xfff8, 0x0600,  8},
+  {m68k_op_addi_8_ai           , 0xfff8, 0x0610, 16},
+  {m68k_op_addi_8_pi           , 0xfff8, 0x0618, 16},
+  {m68k_op_addi_8_pd           , 0xfff8, 0x0620, 18},
+  {m68k_op_addi_8_di           , 0xfff8, 0x0628, 20},
+  {m68k_op_addi_8_ix           , 0xfff8, 0x0630, 22},
+  {m68k_op_addi_16_d           , 0xfff8, 0x0640,  8},
+  {m68k_op_addi_16_ai          , 0xfff8, 0x0650, 16},
+  {m68k_op_addi_16_pi          , 0xfff8, 0x0658, 16},
+  {m68k_op_addi_16_pd          , 0xfff8, 0x0660, 18},
+  {m68k_op_addi_16_di          , 0xfff8, 0x0668, 20},
+  {m68k_op_addi_16_ix          , 0xfff8, 0x0670, 22},
+  {m68k_op_addi_32_d           , 0xfff8, 0x0680, 16},
+  {m68k_op_addi_32_ai          , 0xfff8, 0x0690, 28},
+  {m68k_op_addi_32_pi          , 0xfff8, 0x0698, 28},
+  {m68k_op_addi_32_pd          , 0xfff8, 0x06a0, 30},
+  {m68k_op_addi_32_di          , 0xfff8, 0x06a8, 32},
+  {m68k_op_addi_32_ix          , 0xfff8, 0x06b0, 34},
+  {m68k_op_btst_32_s_d         , 0xfff8, 0x0800, 10},
+  {m68k_op_btst_8_s_ai         , 0xfff8, 0x0810, 12},
+  {m68k_op_btst_8_s_pi         , 0xfff8, 0x0818, 12},
+  {m68k_op_btst_8_s_pd         , 0xfff8, 0x0820, 14},
+  {m68k_op_btst_8_s_di         , 0xfff8, 0x0828, 16},
+  {m68k_op_btst_8_s_ix         , 0xfff8, 0x0830, 18},
+  {m68k_op_bchg_32_s_d         , 0xfff8, 0x0840, 12},
+  {m68k_op_bchg_8_s_ai         , 0xfff8, 0x0850, 16},
+  {m68k_op_bchg_8_s_pi         , 0xfff8, 0x0858, 16},
+  {m68k_op_bchg_8_s_pd         , 0xfff8, 0x0860, 18},
+  {m68k_op_bchg_8_s_di         , 0xfff8, 0x0868, 20},
+  {m68k_op_bchg_8_s_ix         , 0xfff8, 0x0870, 22},
+  {m68k_op_bclr_32_s_d         , 0xfff8, 0x0880, 14},
+  {m68k_op_bclr_8_s_ai         , 0xfff8, 0x0890, 16},
+  {m68k_op_bclr_8_s_pi         , 0xfff8, 0x0898, 16},
+  {m68k_op_bclr_8_s_pd         , 0xfff8, 0x08a0, 18},
+  {m68k_op_bclr_8_s_di         , 0xfff8, 0x08a8, 20},
+  {m68k_op_bclr_8_s_ix         , 0xfff8, 0x08b0, 22},
+  {m68k_op_bset_32_s_d         , 0xfff8, 0x08c0, 12},
+  {m68k_op_bset_8_s_ai         , 0xfff8, 0x08d0, 16},
+  {m68k_op_bset_8_s_pi         , 0xfff8, 0x08d8, 16},
+  {m68k_op_bset_8_s_pd         , 0xfff8, 0x08e0, 18},
+  {m68k_op_bset_8_s_di         , 0xfff8, 0x08e8, 20},
+  {m68k_op_bset_8_s_ix         , 0xfff8, 0x08f0, 22},
+  {m68k_op_eori_8_d            , 0xfff8, 0x0a00,  8},
+  {m68k_op_eori_8_ai           , 0xfff8, 0x0a10, 16},
+  {m68k_op_eori_8_pi           , 0xfff8, 0x0a18, 16},
+  {m68k_op_eori_8_pd           , 0xfff8, 0x0a20, 18},
+  {m68k_op_eori_8_di           , 0xfff8, 0x0a28, 20},
+  {m68k_op_eori_8_ix           , 0xfff8, 0x0a30, 22},
+  {m68k_op_eori_16_d           , 0xfff8, 0x0a40,  8},
+  {m68k_op_eori_16_ai          , 0xfff8, 0x0a50, 16},
+  {m68k_op_eori_16_pi          , 0xfff8, 0x0a58, 16},
+  {m68k_op_eori_16_pd          , 0xfff8, 0x0a60, 18},
+  {m68k_op_eori_16_di          , 0xfff8, 0x0a68, 20},
+  {m68k_op_eori_16_ix          , 0xfff8, 0x0a70, 22},
+  {m68k_op_eori_32_d           , 0xfff8, 0x0a80, 16},
+  {m68k_op_eori_32_ai          , 0xfff8, 0x0a90, 28},
+  {m68k_op_eori_32_pi          , 0xfff8, 0x0a98, 28},
+  {m68k_op_eori_32_pd          , 0xfff8, 0x0aa0, 30},
+  {m68k_op_eori_32_di          , 0xfff8, 0x0aa8, 32},
+  {m68k_op_eori_32_ix          , 0xfff8, 0x0ab0, 34},
+  {m68k_op_cmpi_8_d            , 0xfff8, 0x0c00,  8},
+  {m68k_op_cmpi_8_ai           , 0xfff8, 0x0c10, 12},
+  {m68k_op_cmpi_8_pi           , 0xfff8, 0x0c18, 12},
+  {m68k_op_cmpi_8_pd           , 0xfff8, 0x0c20, 14},
+  {m68k_op_cmpi_8_di           , 0xfff8, 0x0c28, 16},
+  {m68k_op_cmpi_8_ix           , 0xfff8, 0x0c30, 18},
+  {m68k_op_cmpi_16_d           , 0xfff8, 0x0c40,  8},
+  {m68k_op_cmpi_16_ai          , 0xfff8, 0x0c50, 12},
+  {m68k_op_cmpi_16_pi          , 0xfff8, 0x0c58, 12},
+  {m68k_op_cmpi_16_pd          , 0xfff8, 0x0c60, 14},
+  {m68k_op_cmpi_16_di          , 0xfff8, 0x0c68, 16},
+  {m68k_op_cmpi_16_ix          , 0xfff8, 0x0c70, 18},
+  {m68k_op_cmpi_32_d           , 0xfff8, 0x0c80, 14},
+  {m68k_op_cmpi_32_ai          , 0xfff8, 0x0c90, 20},
+  {m68k_op_cmpi_32_pi          , 0xfff8, 0x0c98, 20},
+  {m68k_op_cmpi_32_pd          , 0xfff8, 0x0ca0, 22},
+  {m68k_op_cmpi_32_di          , 0xfff8, 0x0ca8, 24},
+  {m68k_op_cmpi_32_ix          , 0xfff8, 0x0cb0, 26},
+  {m68k_op_move_8_aw_d         , 0xfff8, 0x11c0, 12},
+  {m68k_op_move_8_aw_ai        , 0xfff8, 0x11d0, 16},
+  {m68k_op_move_8_aw_pi        , 0xfff8, 0x11d8, 16},
+  {m68k_op_move_8_aw_pd        , 0xfff8, 0x11e0, 18},
+  {m68k_op_move_8_aw_di        , 0xfff8, 0x11e8, 20},
+  {m68k_op_move_8_aw_ix        , 0xfff8, 0x11f0, 22},
+  {m68k_op_move_8_al_d         , 0xfff8, 0x13c0, 16},
+  {m68k_op_move_8_al_ai        , 0xfff8, 0x13d0, 20},
+  {m68k_op_move_8_al_pi        , 0xfff8, 0x13d8, 20},
+  {m68k_op_move_8_al_pd        , 0xfff8, 0x13e0, 22},
+  {m68k_op_move_8_al_di        , 0xfff8, 0x13e8, 24},
+  {m68k_op_move_8_al_ix        , 0xfff8, 0x13f0, 26},
+  {m68k_op_move_8_pi7_d        , 0xfff8, 0x1ec0,  8},
+  {m68k_op_move_8_pi7_ai       , 0xfff8, 0x1ed0, 12},
+  {m68k_op_move_8_pi7_pi       , 0xfff8, 0x1ed8, 12},
+  {m68k_op_move_8_pi7_pd       , 0xfff8, 0x1ee0, 14},
+  {m68k_op_move_8_pi7_di       , 0xfff8, 0x1ee8, 16},
+  {m68k_op_move_8_pi7_ix       , 0xfff8, 0x1ef0, 18},
+  {m68k_op_move_8_pd7_d        , 0xfff8, 0x1f00,  8},
+  {m68k_op_move_8_pd7_ai       , 0xfff8, 0x1f10, 12},
+  {m68k_op_move_8_pd7_pi       , 0xfff8, 0x1f18, 12},
+  {m68k_op_move_8_pd7_pd       , 0xfff8, 0x1f20, 14},
+  {m68k_op_move_8_pd7_di       , 0xfff8, 0x1f28, 16},
+  {m68k_op_move_8_pd7_ix       , 0xfff8, 0x1f30, 18},
+  {m68k_op_move_32_aw_d        , 0xfff8, 0x21c0, 16},
+  {m68k_op_move_32_aw_a        , 0xfff8, 0x21c8, 16},
+  {m68k_op_move_32_aw_ai       , 0xfff8, 0x21d0, 24},
+  {m68k_op_move_32_aw_pi       , 0xfff8, 0x21d8, 24},
+  {m68k_op_move_32_aw_pd       , 0xfff8, 0x21e0, 26},
+  {m68k_op_move_32_aw_di       , 0xfff8, 0x21e8, 28},
+  {m68k_op_move_32_aw_ix       , 0xfff8, 0x21f0, 30},
+  {m68k_op_move_32_al_d        , 0xfff8, 0x23c0, 20},
+  {m68k_op_move_32_al_a        , 0xfff8, 0x23c8, 20},
+  {m68k_op_move_32_al_ai       , 0xfff8, 0x23d0, 28},
+  {m68k_op_move_32_al_pi       , 0xfff8, 0x23d8, 28},
+  {m68k_op_move_32_al_pd       , 0xfff8, 0x23e0, 30},
+  {m68k_op_move_32_al_di       , 0xfff8, 0x23e8, 32},
+  {m68k_op_move_32_al_ix       , 0xfff8, 0x23f0, 34},
+  {m68k_op_move_16_aw_d        , 0xfff8, 0x31c0, 12},
+  {m68k_op_move_16_aw_a        , 0xfff8, 0x31c8, 12},
+  {m68k_op_move_16_aw_ai       , 0xfff8, 0x31d0, 16},
+  {m68k_op_move_16_aw_pi       , 0xfff8, 0x31d8, 16},
+  {m68k_op_move_16_aw_pd       , 0xfff8, 0x31e0, 18},
+  {m68k_op_move_16_aw_di       , 0xfff8, 0x31e8, 20},
+  {m68k_op_move_16_aw_ix       , 0xfff8, 0x31f0, 22},
+  {m68k_op_move_16_al_d        , 0xfff8, 0x33c0, 16},
+  {m68k_op_move_16_al_a        , 0xfff8, 0x33c8, 16},
+  {m68k_op_move_16_al_ai       , 0xfff8, 0x33d0, 20},
+  {m68k_op_move_16_al_pi       , 0xfff8, 0x33d8, 20},
+  {m68k_op_move_16_al_pd       , 0xfff8, 0x33e0, 22},
+  {m68k_op_move_16_al_di       , 0xfff8, 0x33e8, 24},
+  {m68k_op_move_16_al_ix       , 0xfff8, 0x33f0, 26},
+  {m68k_op_negx_8_d            , 0xfff8, 0x4000,  4},
+  {m68k_op_negx_8_ai           , 0xfff8, 0x4010, 12},
+  {m68k_op_negx_8_pi           , 0xfff8, 0x4018, 12},
+  {m68k_op_negx_8_pd           , 0xfff8, 0x4020, 14},
+  {m68k_op_negx_8_di           , 0xfff8, 0x4028, 16},
+  {m68k_op_negx_8_ix           , 0xfff8, 0x4030, 18},
+  {m68k_op_negx_16_d           , 0xfff8, 0x4040,  4},
+  {m68k_op_negx_16_ai          , 0xfff8, 0x4050, 12},
+  {m68k_op_negx_16_pi          , 0xfff8, 0x4058, 12},
+  {m68k_op_negx_16_pd          , 0xfff8, 0x4060, 14},
+  {m68k_op_negx_16_di          , 0xfff8, 0x4068, 16},
+  {m68k_op_negx_16_ix          , 0xfff8, 0x4070, 18},
+  {m68k_op_negx_32_d           , 0xfff8, 0x4080,  6},
+  {m68k_op_negx_32_ai          , 0xfff8, 0x4090, 20},
+  {m68k_op_negx_32_pi          , 0xfff8, 0x4098, 20},
+  {m68k_op_negx_32_pd          , 0xfff8, 0x40a0, 22},
+  {m68k_op_negx_32_di          , 0xfff8, 0x40a8, 24},
+  {m68k_op_negx_32_ix          , 0xfff8, 0x40b0, 26},
+  {m68k_op_move_16_frs_d       , 0xfff8, 0x40c0,  6},
+  {m68k_op_move_16_frs_ai      , 0xfff8, 0x40d0, 12},
+  {m68k_op_move_16_frs_pi      , 0xfff8, 0x40d8, 12},
+  {m68k_op_move_16_frs_pd      , 0xfff8, 0x40e0, 14},
+  {m68k_op_move_16_frs_di      , 0xfff8, 0x40e8, 16},
+  {m68k_op_move_16_frs_ix      , 0xfff8, 0x40f0, 18},
+  {m68k_op_clr_8_d             , 0xfff8, 0x4200,  4},
+  {m68k_op_clr_8_ai            , 0xfff8, 0x4210, 12},
+  {m68k_op_clr_8_pi            , 0xfff8, 0x4218, 12},
+  {m68k_op_clr_8_pd            , 0xfff8, 0x4220, 14},
+  {m68k_op_clr_8_di            , 0xfff8, 0x4228, 16},
+  {m68k_op_clr_8_ix            , 0xfff8, 0x4230, 18},
+  {m68k_op_clr_16_d            , 0xfff8, 0x4240,  4},
+  {m68k_op_clr_16_ai           , 0xfff8, 0x4250, 12},
+  {m68k_op_clr_16_pi           , 0xfff8, 0x4258, 12},
+  {m68k_op_clr_16_pd           , 0xfff8, 0x4260, 14},
+  {m68k_op_clr_16_di           , 0xfff8, 0x4268, 16},
+  {m68k_op_clr_16_ix           , 0xfff8, 0x4270, 18},
+  {m68k_op_clr_32_d            , 0xfff8, 0x4280,  6},
+  {m68k_op_clr_32_ai           , 0xfff8, 0x4290, 20},
+  {m68k_op_clr_32_pi           , 0xfff8, 0x4298, 20},
+  {m68k_op_clr_32_pd           , 0xfff8, 0x42a0, 22},
+  {m68k_op_clr_32_di           , 0xfff8, 0x42a8, 24},
+  {m68k_op_clr_32_ix           , 0xfff8, 0x42b0, 26},
+  {m68k_op_neg_8_d             , 0xfff8, 0x4400,  4},
+  {m68k_op_neg_8_ai            , 0xfff8, 0x4410, 12},
+  {m68k_op_neg_8_pi            , 0xfff8, 0x4418, 12},
+  {m68k_op_neg_8_pd            , 0xfff8, 0x4420, 14},
+  {m68k_op_neg_8_di            , 0xfff8, 0x4428, 16},
+  {m68k_op_neg_8_ix            , 0xfff8, 0x4430, 18},
+  {m68k_op_neg_16_d            , 0xfff8, 0x4440,  4},
+  {m68k_op_neg_16_ai           , 0xfff8, 0x4450, 12},
+  {m68k_op_neg_16_pi           , 0xfff8, 0x4458, 12},
+  {m68k_op_neg_16_pd           , 0xfff8, 0x4460, 14},
+  {m68k_op_neg_16_di           , 0xfff8, 0x4468, 16},
+  {m68k_op_neg_16_ix           , 0xfff8, 0x4470, 18},
+  {m68k_op_neg_32_d            , 0xfff8, 0x4480,  6},
+  {m68k_op_neg_32_ai           , 0xfff8, 0x4490, 20},
+  {m68k_op_neg_32_pi           , 0xfff8, 0x4498, 20},
+  {m68k_op_neg_32_pd           , 0xfff8, 0x44a0, 22},
+  {m68k_op_neg_32_di           , 0xfff8, 0x44a8, 24},
+  {m68k_op_neg_32_ix           , 0xfff8, 0x44b0, 26},
+  {m68k_op_move_16_toc_d       , 0xfff8, 0x44c0, 12},
+  {m68k_op_move_16_toc_ai      , 0xfff8, 0x44d0, 16},
+  {m68k_op_move_16_toc_pi      , 0xfff8, 0x44d8, 16},
+  {m68k_op_move_16_toc_pd      , 0xfff8, 0x44e0, 18},
+  {m68k_op_move_16_toc_di      , 0xfff8, 0x44e8, 20},
+  {m68k_op_move_16_toc_ix      , 0xfff8, 0x44f0, 22},
+  {m68k_op_not_8_d             , 0xfff8, 0x4600,  4},
+  {m68k_op_not_8_ai            , 0xfff8, 0x4610, 12},
+  {m68k_op_not_8_pi            , 0xfff8, 0x4618, 12},
+  {m68k_op_not_8_pd            , 0xfff8, 0x4620, 14},
+  {m68k_op_not_8_di            , 0xfff8, 0x4628, 16},
+  {m68k_op_not_8_ix            , 0xfff8, 0x4630, 18},
+  {m68k_op_not_16_d            , 0xfff8, 0x4640,  4},
+  {m68k_op_not_16_ai           , 0xfff8, 0x4650, 12},
+  {m68k_op_not_16_pi           , 0xfff8, 0x4658, 12},
+  {m68k_op_not_16_pd           , 0xfff8, 0x4660, 14},
+  {m68k_op_not_16_di           , 0xfff8, 0x4668, 16},
+  {m68k_op_not_16_ix           , 0xfff8, 0x4670, 18},
+  {m68k_op_not_32_d            , 0xfff8, 0x4680,  6},
+  {m68k_op_not_32_ai           , 0xfff8, 0x4690, 20},
+  {m68k_op_not_32_pi           , 0xfff8, 0x4698, 20},
+  {m68k_op_not_32_pd           , 0xfff8, 0x46a0, 22},
+  {m68k_op_not_32_di           , 0xfff8, 0x46a8, 24},
+  {m68k_op_not_32_ix           , 0xfff8, 0x46b0, 26},
+  {m68k_op_move_16_tos_d       , 0xfff8, 0x46c0, 12},
+  {m68k_op_move_16_tos_ai      , 0xfff8, 0x46d0, 16},
+  {m68k_op_move_16_tos_pi      , 0xfff8, 0x46d8, 16},
+  {m68k_op_move_16_tos_pd      , 0xfff8, 0x46e0, 18},
+  {m68k_op_move_16_tos_di      , 0xfff8, 0x46e8, 20},
+  {m68k_op_move_16_tos_ix      , 0xfff8, 0x46f0, 22},
+  {m68k_op_nbcd_8_d            , 0xfff8, 0x4800,  6},
+  {m68k_op_nbcd_8_ai           , 0xfff8, 0x4810, 12},
+  {m68k_op_nbcd_8_pi           , 0xfff8, 0x4818, 12},
+  {m68k_op_nbcd_8_pd           , 0xfff8, 0x4820, 14},
+  {m68k_op_nbcd_8_di           , 0xfff8, 0x4828, 16},
+  {m68k_op_nbcd_8_ix           , 0xfff8, 0x4830, 18},
+  {m68k_op_swap_32             , 0xfff8, 0x4840,  4},
+  {m68k_op_pea_32_ai           , 0xfff8, 0x4850, 12},
+  {m68k_op_pea_32_di           , 0xfff8, 0x4868, 16},
+  {m68k_op_pea_32_ix           , 0xfff8, 0x4870, 20},
+  {m68k_op_ext_16              , 0xfff8, 0x4880,  4},
+  {m68k_op_movem_16_re_ai      , 0xfff8, 0x4890,  8},
+  {m68k_op_movem_16_re_pd      , 0xfff8, 0x48a0,  8},
+  {m68k_op_movem_16_re_di      , 0xfff8, 0x48a8, 12},
+  {m68k_op_movem_16_re_ix      , 0xfff8, 0x48b0, 14},
+  {m68k_op_ext_32              , 0xfff8, 0x48c0,  4},
+  {m68k_op_movem_32_re_ai      , 0xfff8, 0x48d0,  8},
+  {m68k_op_movem_32_re_pd      , 0xfff8, 0x48e0,  8},
+  {m68k_op_movem_32_re_di      , 0xfff8, 0x48e8, 12},
+  {m68k_op_movem_32_re_ix      , 0xfff8, 0x48f0, 14},
+  {m68k_op_tst_8_d             , 0xfff8, 0x4a00,  4},
+  {m68k_op_tst_8_ai            , 0xfff8, 0x4a10,  8},
+  {m68k_op_tst_8_pi            , 0xfff8, 0x4a18,  8},
+  {m68k_op_tst_8_pd            , 0xfff8, 0x4a20, 10},
+  {m68k_op_tst_8_di            , 0xfff8, 0x4a28, 12},
+  {m68k_op_tst_8_ix            , 0xfff8, 0x4a30, 14},
+  {m68k_op_tst_16_d            , 0xfff8, 0x4a40,  4},
+  {m68k_op_tst_16_ai           , 0xfff8, 0x4a50,  8},
+  {m68k_op_tst_16_pi           , 0xfff8, 0x4a58,  8},
+  {m68k_op_tst_16_pd           , 0xfff8, 0x4a60, 10},
+  {m68k_op_tst_16_di           , 0xfff8, 0x4a68, 12},
+  {m68k_op_tst_16_ix           , 0xfff8, 0x4a70, 14},
+  {m68k_op_tst_32_d            , 0xfff8, 0x4a80,  4},
+  {m68k_op_tst_32_ai           , 0xfff8, 0x4a90, 12},
+  {m68k_op_tst_32_pi           , 0xfff8, 0x4a98, 12},
+  {m68k_op_tst_32_pd           , 0xfff8, 0x4aa0, 14},
+  {m68k_op_tst_32_di           , 0xfff8, 0x4aa8, 16},
+  {m68k_op_tst_32_ix           , 0xfff8, 0x4ab0, 18},
+  {m68k_op_tas_8_d             , 0xfff8, 0x4ac0,  4},
+  {m68k_op_tas_8_ai            , 0xfff8, 0x4ad0, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pi            , 0xfff8, 0x4ad8, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pd            , 0xfff8, 0x4ae0, 16}, /* see Yacht.txt */
+  {m68k_op_tas_8_di            , 0xfff8, 0x4ae8, 18}, /* see Yacht.txt */
+  {m68k_op_tas_8_ix            , 0xfff8, 0x4af0, 20}, /* see Yacht.txt */
+  {m68k_op_movem_16_er_ai      , 0xfff8, 0x4c90, 12},
+  {m68k_op_movem_16_er_pi      , 0xfff8, 0x4c98, 12},
+  {m68k_op_movem_16_er_di      , 0xfff8, 0x4ca8, 16},
+  {m68k_op_movem_16_er_ix      , 0xfff8, 0x4cb0, 18},
+  {m68k_op_movem_32_er_ai      , 0xfff8, 0x4cd0, 12},
+  {m68k_op_movem_32_er_pi      , 0xfff8, 0x4cd8, 12},
+  {m68k_op_movem_32_er_di      , 0xfff8, 0x4ce8, 16},
+  {m68k_op_movem_32_er_ix      , 0xfff8, 0x4cf0, 18},
+  {m68k_op_link_16             , 0xfff8, 0x4e50, 16},
+  {m68k_op_unlk_32             , 0xfff8, 0x4e58, 12},
+  {m68k_op_move_32_tou         , 0xfff8, 0x4e60,  4},
+  {m68k_op_move_32_fru         , 0xfff8, 0x4e68,  4},
+  {m68k_op_jsr_32_ai           , 0xfff8, 0x4e90, 16},
+  {m68k_op_jsr_32_di           , 0xfff8, 0x4ea8, 18},
+  {m68k_op_jsr_32_ix           , 0xfff8, 0x4eb0, 22},
+  {m68k_op_jmp_32_ai           , 0xfff8, 0x4ed0,  8},
+  {m68k_op_jmp_32_di           , 0xfff8, 0x4ee8, 10},
+  {m68k_op_jmp_32_ix           , 0xfff8, 0x4ef0, 14},
+  {m68k_op_st_8_d              , 0xfff8, 0x50c0,  6},
+  {m68k_op_dbt_16              , 0xfff8, 0x50c8, 12},
+  {m68k_op_st_8_ai             , 0xfff8, 0x50d0, 12},
+  {m68k_op_st_8_pi             , 0xfff8, 0x50d8, 12},
+  {m68k_op_st_8_pd             , 0xfff8, 0x50e0, 14},
+  {m68k_op_st_8_di             , 0xfff8, 0x50e8, 16},
+  {m68k_op_st_8_ix             , 0xfff8, 0x50f0, 18},
+  {m68k_op_sf_8_d              , 0xfff8, 0x51c0,  4},
+  {m68k_op_dbf_16              , 0xfff8, 0x51c8, 12},
+  {m68k_op_sf_8_ai             , 0xfff8, 0x51d0, 12},
+  {m68k_op_sf_8_pi             , 0xfff8, 0x51d8, 12},
+  {m68k_op_sf_8_pd             , 0xfff8, 0x51e0, 14},
+  {m68k_op_sf_8_di             , 0xfff8, 0x51e8, 16},
+  {m68k_op_sf_8_ix             , 0xfff8, 0x51f0, 18},
+  {m68k_op_shi_8_d             , 0xfff8, 0x52c0,  4},
+  {m68k_op_dbhi_16             , 0xfff8, 0x52c8, 12},
+  {m68k_op_shi_8_ai            , 0xfff8, 0x52d0, 12},
+  {m68k_op_shi_8_pi            , 0xfff8, 0x52d8, 12},
+  {m68k_op_shi_8_pd            , 0xfff8, 0x52e0, 14},
+  {m68k_op_shi_8_di            , 0xfff8, 0x52e8, 16},
+  {m68k_op_shi_8_ix            , 0xfff8, 0x52f0, 18},
+  {m68k_op_sls_8_d             , 0xfff8, 0x53c0,  4},
+  {m68k_op_dbls_16             , 0xfff8, 0x53c8, 12},
+  {m68k_op_sls_8_ai            , 0xfff8, 0x53d0, 12},
+  {m68k_op_sls_8_pi            , 0xfff8, 0x53d8, 12},
+  {m68k_op_sls_8_pd            , 0xfff8, 0x53e0, 14},
+  {m68k_op_sls_8_di            , 0xfff8, 0x53e8, 16},
+  {m68k_op_sls_8_ix            , 0xfff8, 0x53f0, 18},
+  {m68k_op_scc_8_d             , 0xfff8, 0x54c0,  4},
+  {m68k_op_dbcc_16             , 0xfff8, 0x54c8, 12},
+  {m68k_op_scc_8_ai            , 0xfff8, 0x54d0, 12},
+  {m68k_op_scc_8_pi            , 0xfff8, 0x54d8, 12},
+  {m68k_op_scc_8_pd            , 0xfff8, 0x54e0, 14},
+  {m68k_op_scc_8_di            , 0xfff8, 0x54e8, 16},
+  {m68k_op_scc_8_ix            , 0xfff8, 0x54f0, 18},
+  {m68k_op_scs_8_d             , 0xfff8, 0x55c0,  4},
+  {m68k_op_dbcs_16             , 0xfff8, 0x55c8, 12},
+  {m68k_op_scs_8_ai            , 0xfff8, 0x55d0, 12},
+  {m68k_op_scs_8_pi            , 0xfff8, 0x55d8, 12},
+  {m68k_op_scs_8_pd            , 0xfff8, 0x55e0, 14},
+  {m68k_op_scs_8_di            , 0xfff8, 0x55e8, 16},
+  {m68k_op_scs_8_ix            , 0xfff8, 0x55f0, 18},
+  {m68k_op_sne_8_d             , 0xfff8, 0x56c0,  4},
+  {m68k_op_dbne_16             , 0xfff8, 0x56c8, 12},
+  {m68k_op_sne_8_ai            , 0xfff8, 0x56d0, 12},
+  {m68k_op_sne_8_pi            , 0xfff8, 0x56d8, 12},
+  {m68k_op_sne_8_pd            , 0xfff8, 0x56e0, 14},
+  {m68k_op_sne_8_di            , 0xfff8, 0x56e8, 16},
+  {m68k_op_sne_8_ix            , 0xfff8, 0x56f0, 18},
+  {m68k_op_seq_8_d             , 0xfff8, 0x57c0,  4},
+  {m68k_op_dbeq_16             , 0xfff8, 0x57c8, 12},
+  {m68k_op_seq_8_ai            , 0xfff8, 0x57d0, 12},
+  {m68k_op_seq_8_pi            , 0xfff8, 0x57d8, 12},
+  {m68k_op_seq_8_pd            , 0xfff8, 0x57e0, 14},
+  {m68k_op_seq_8_di            , 0xfff8, 0x57e8, 16},
+  {m68k_op_seq_8_ix            , 0xfff8, 0x57f0, 18},
+  {m68k_op_svc_8_d             , 0xfff8, 0x58c0,  4},
+  {m68k_op_dbvc_16             , 0xfff8, 0x58c8, 12},
+  {m68k_op_svc_8_ai            , 0xfff8, 0x58d0, 12},
+  {m68k_op_svc_8_pi            , 0xfff8, 0x58d8, 12},
+  {m68k_op_svc_8_pd            , 0xfff8, 0x58e0, 14},
+  {m68k_op_svc_8_di            , 0xfff8, 0x58e8, 16},
+  {m68k_op_svc_8_ix            , 0xfff8, 0x58f0, 18},
+  {m68k_op_svs_8_d             , 0xfff8, 0x59c0,  4},
+  {m68k_op_dbvs_16             , 0xfff8, 0x59c8, 12},
+  {m68k_op_svs_8_ai            , 0xfff8, 0x59d0, 12},
+  {m68k_op_svs_8_pi            , 0xfff8, 0x59d8, 12},
+  {m68k_op_svs_8_pd            , 0xfff8, 0x59e0, 14},
+  {m68k_op_svs_8_di            , 0xfff8, 0x59e8, 16},
+  {m68k_op_svs_8_ix            , 0xfff8, 0x59f0, 18},
+  {m68k_op_spl_8_d             , 0xfff8, 0x5ac0,  4},
+  {m68k_op_dbpl_16             , 0xfff8, 0x5ac8, 12},
+  {m68k_op_spl_8_ai            , 0xfff8, 0x5ad0, 12},
+  {m68k_op_spl_8_pi            , 0xfff8, 0x5ad8, 12},
+  {m68k_op_spl_8_pd            , 0xfff8, 0x5ae0, 14},
+  {m68k_op_spl_8_di            , 0xfff8, 0x5ae8, 16},
+  {m68k_op_spl_8_ix            , 0xfff8, 0x5af0, 18},
+  {m68k_op_smi_8_d             , 0xfff8, 0x5bc0,  4},
+  {m68k_op_dbmi_16             , 0xfff8, 0x5bc8, 12},
+  {m68k_op_smi_8_ai            , 0xfff8, 0x5bd0, 12},
+  {m68k_op_smi_8_pi            , 0xfff8, 0x5bd8, 12},
+  {m68k_op_smi_8_pd            , 0xfff8, 0x5be0, 14},
+  {m68k_op_smi_8_di            , 0xfff8, 0x5be8, 16},
+  {m68k_op_smi_8_ix            , 0xfff8, 0x5bf0, 18},
+  {m68k_op_sge_8_d             , 0xfff8, 0x5cc0,  4},
+  {m68k_op_dbge_16             , 0xfff8, 0x5cc8, 12},
+  {m68k_op_sge_8_ai            , 0xfff8, 0x5cd0, 12},
+  {m68k_op_sge_8_pi            , 0xfff8, 0x5cd8, 12},
+  {m68k_op_sge_8_pd            , 0xfff8, 0x5ce0, 14},
+  {m68k_op_sge_8_di            , 0xfff8, 0x5ce8, 16},
+  {m68k_op_sge_8_ix            , 0xfff8, 0x5cf0, 18},
+  {m68k_op_slt_8_d             , 0xfff8, 0x5dc0,  4},
+  {m68k_op_dblt_16             , 0xfff8, 0x5dc8, 12},
+  {m68k_op_slt_8_ai            , 0xfff8, 0x5dd0, 12},
+  {m68k_op_slt_8_pi            , 0xfff8, 0x5dd8, 12},
+  {m68k_op_slt_8_pd            , 0xfff8, 0x5de0, 14},
+  {m68k_op_slt_8_di            , 0xfff8, 0x5de8, 16},
+  {m68k_op_slt_8_ix            , 0xfff8, 0x5df0, 18},
+  {m68k_op_sgt_8_d             , 0xfff8, 0x5ec0,  4},
+  {m68k_op_dbgt_16             , 0xfff8, 0x5ec8, 12},
+  {m68k_op_sgt_8_ai            , 0xfff8, 0x5ed0, 12},
+  {m68k_op_sgt_8_pi            , 0xfff8, 0x5ed8, 12},
+  {m68k_op_sgt_8_pd            , 0xfff8, 0x5ee0, 14},
+  {m68k_op_sgt_8_di            , 0xfff8, 0x5ee8, 16},
+  {m68k_op_sgt_8_ix            , 0xfff8, 0x5ef0, 18},
+  {m68k_op_sle_8_d             , 0xfff8, 0x5fc0,  4},
+  {m68k_op_dble_16             , 0xfff8, 0x5fc8, 12},
+  {m68k_op_sle_8_ai            , 0xfff8, 0x5fd0, 12},
+  {m68k_op_sle_8_pi            , 0xfff8, 0x5fd8, 12},
+  {m68k_op_sle_8_pd            , 0xfff8, 0x5fe0, 14},
+  {m68k_op_sle_8_di            , 0xfff8, 0x5fe8, 16},
+  {m68k_op_sle_8_ix            , 0xfff8, 0x5ff0, 18},
+  {m68k_op_sbcd_8_mm_ax7       , 0xfff8, 0x8f08, 18},
+  {m68k_op_subx_8_mm_ax7       , 0xfff8, 0x9f08, 18},
+  {m68k_op_cmpm_8_ax7          , 0xfff8, 0xbf08, 12},
+  {m68k_op_abcd_8_mm_ax7       , 0xfff8, 0xcf08, 18},
+  {m68k_op_addx_8_mm_ax7       , 0xfff8, 0xdf08, 18},
+  {m68k_op_asr_16_ai           , 0xfff8, 0xe0d0, 12},
+  {m68k_op_asr_16_pi           , 0xfff8, 0xe0d8, 12},
+  {m68k_op_asr_16_pd           , 0xfff8, 0xe0e0, 14},
+  {m68k_op_asr_16_di           , 0xfff8, 0xe0e8, 16},
+  {m68k_op_asr_16_ix           , 0xfff8, 0xe0f0, 18},
+  {m68k_op_asl_16_ai           , 0xfff8, 0xe1d0, 12},
+  {m68k_op_asl_16_pi           , 0xfff8, 0xe1d8, 12},
+  {m68k_op_asl_16_pd           , 0xfff8, 0xe1e0, 14},
+  {m68k_op_asl_16_di           , 0xfff8, 0xe1e8, 16},
+  {m68k_op_asl_16_ix           , 0xfff8, 0xe1f0, 18},
+  {m68k_op_lsr_16_ai           , 0xfff8, 0xe2d0, 12},
+  {m68k_op_lsr_16_pi           , 0xfff8, 0xe2d8, 12},
+  {m68k_op_lsr_16_pd           , 0xfff8, 0xe2e0, 14},
+  {m68k_op_lsr_16_di           , 0xfff8, 0xe2e8, 16},
+  {m68k_op_lsr_16_ix           , 0xfff8, 0xe2f0, 18},
+  {m68k_op_lsl_16_ai           , 0xfff8, 0xe3d0, 12},
+  {m68k_op_lsl_16_pi           , 0xfff8, 0xe3d8, 12},
+  {m68k_op_lsl_16_pd           , 0xfff8, 0xe3e0, 14},
+  {m68k_op_lsl_16_di           , 0xfff8, 0xe3e8, 16},
+  {m68k_op_lsl_16_ix           , 0xfff8, 0xe3f0, 18},
+  {m68k_op_roxr_16_ai          , 0xfff8, 0xe4d0, 12},
+  {m68k_op_roxr_16_pi          , 0xfff8, 0xe4d8, 12},
+  {m68k_op_roxr_16_pd          , 0xfff8, 0xe4e0, 14},
+  {m68k_op_roxr_16_di          , 0xfff8, 0xe4e8, 16},
+  {m68k_op_roxr_16_ix          , 0xfff8, 0xe4f0, 18},
+  {m68k_op_roxl_16_ai          , 0xfff8, 0xe5d0, 12},
+  {m68k_op_roxl_16_pi          , 0xfff8, 0xe5d8, 12},
+  {m68k_op_roxl_16_pd          , 0xfff8, 0xe5e0, 14},
+  {m68k_op_roxl_16_di          , 0xfff8, 0xe5e8, 16},
+  {m68k_op_roxl_16_ix          , 0xfff8, 0xe5f0, 18},
+  {m68k_op_ror_16_ai           , 0xfff8, 0xe6d0, 12},
+  {m68k_op_ror_16_pi           , 0xfff8, 0xe6d8, 12},
+  {m68k_op_ror_16_pd           , 0xfff8, 0xe6e0, 14},
+  {m68k_op_ror_16_di           , 0xfff8, 0xe6e8, 16},
+  {m68k_op_ror_16_ix           , 0xfff8, 0xe6f0, 18},
+  {m68k_op_rol_16_ai           , 0xfff8, 0xe7d0, 12},
+  {m68k_op_rol_16_pi           , 0xfff8, 0xe7d8, 12},
+  {m68k_op_rol_16_pd           , 0xfff8, 0xe7e0, 14},
+  {m68k_op_rol_16_di           , 0xfff8, 0xe7e8, 16},
+  {m68k_op_rol_16_ix           , 0xfff8, 0xe7f0, 18},
+  {m68k_op_ori_8_pi7           , 0xffff, 0x001f, 16},
+  {m68k_op_ori_8_pd7           , 0xffff, 0x0027, 18},
+  {m68k_op_ori_8_aw            , 0xffff, 0x0038, 20},
+  {m68k_op_ori_8_al            , 0xffff, 0x0039, 24},
+  {m68k_op_ori_16_toc          , 0xffff, 0x003c, 20},
+  {m68k_op_ori_16_aw           , 0xffff, 0x0078, 20},
+  {m68k_op_ori_16_al           , 0xffff, 0x0079, 24},
+  {m68k_op_ori_16_tos          , 0xffff, 0x007c, 20},
+  {m68k_op_ori_32_aw           , 0xffff, 0x00b8, 32},
+  {m68k_op_ori_32_al           , 0xffff, 0x00b9, 36},
+  {m68k_op_andi_8_pi7          , 0xffff, 0x021f, 16},
+  {m68k_op_andi_8_pd7          , 0xffff, 0x0227, 18},
+  {m68k_op_andi_8_aw           , 0xffff, 0x0238, 20},
+  {m68k_op_andi_8_al           , 0xffff, 0x0239, 24},
+  {m68k_op_andi_16_toc         , 0xffff, 0x023c, 20},
+  {m68k_op_andi_16_aw          , 0xffff, 0x0278, 20},
+  {m68k_op_andi_16_al          , 0xffff, 0x0279, 24},
+  {m68k_op_andi_16_tos         , 0xffff, 0x027c, 20},
+  {m68k_op_andi_32_aw          , 0xffff, 0x02b8, 32},
+  {m68k_op_andi_32_al          , 0xffff, 0x02b9, 36},
+  {m68k_op_subi_8_pi7          , 0xffff, 0x041f, 16},
+  {m68k_op_subi_8_pd7          , 0xffff, 0x0427, 18},
+  {m68k_op_subi_8_aw           , 0xffff, 0x0438, 20},
+  {m68k_op_subi_8_al           , 0xffff, 0x0439, 24},
+  {m68k_op_subi_16_aw          , 0xffff, 0x0478, 20},
+  {m68k_op_subi_16_al          , 0xffff, 0x0479, 24},
+  {m68k_op_subi_32_aw          , 0xffff, 0x04b8, 32},
+  {m68k_op_subi_32_al          , 0xffff, 0x04b9, 36},
+  {m68k_op_addi_8_pi7          , 0xffff, 0x061f, 16},
+  {m68k_op_addi_8_pd7          , 0xffff, 0x0627, 18},
+  {m68k_op_addi_8_aw           , 0xffff, 0x0638, 20},
+  {m68k_op_addi_8_al           , 0xffff, 0x0639, 24},
+  {m68k_op_addi_16_aw          , 0xffff, 0x0678, 20},
+  {m68k_op_addi_16_al          , 0xffff, 0x0679, 24},
+  {m68k_op_addi_32_aw          , 0xffff, 0x06b8, 32},
+  {m68k_op_addi_32_al          , 0xffff, 0x06b9, 36},
+  {m68k_op_btst_8_s_pi7        , 0xffff, 0x081f, 12},
+  {m68k_op_btst_8_s_pd7        , 0xffff, 0x0827, 14},
+  {m68k_op_btst_8_s_aw         , 0xffff, 0x0838, 16},
+  {m68k_op_btst_8_s_al         , 0xffff, 0x0839, 20},
+  {m68k_op_btst_8_s_pcdi       , 0xffff, 0x083a, 16},
+  {m68k_op_btst_8_s_pcix       , 0xffff, 0x083b, 18},
+  {m68k_op_bchg_8_s_pi7        , 0xffff, 0x085f, 16},
+  {m68k_op_bchg_8_s_pd7        , 0xffff, 0x0867, 18},
+  {m68k_op_bchg_8_s_aw         , 0xffff, 0x0878, 20},
+  {m68k_op_bchg_8_s_al         , 0xffff, 0x0879, 24},
+  {m68k_op_bclr_8_s_pi7        , 0xffff, 0x089f, 16},
+  {m68k_op_bclr_8_s_pd7        , 0xffff, 0x08a7, 18},
+  {m68k_op_bclr_8_s_aw         , 0xffff, 0x08b8, 20},
+  {m68k_op_bclr_8_s_al         , 0xffff, 0x08b9, 24},
+  {m68k_op_bset_8_s_pi7        , 0xffff, 0x08df, 16},
+  {m68k_op_bset_8_s_pd7        , 0xffff, 0x08e7, 18},
+  {m68k_op_bset_8_s_aw         , 0xffff, 0x08f8, 20},
+  {m68k_op_bset_8_s_al         , 0xffff, 0x08f9, 24},
+  {m68k_op_eori_8_pi7          , 0xffff, 0x0a1f, 16},
+  {m68k_op_eori_8_pd7          , 0xffff, 0x0a27, 18},
+  {m68k_op_eori_8_aw           , 0xffff, 0x0a38, 20},
+  {m68k_op_eori_8_al           , 0xffff, 0x0a39, 24},
+  {m68k_op_eori_16_toc         , 0xffff, 0x0a3c, 20},
+  {m68k_op_eori_16_aw          , 0xffff, 0x0a78, 20},
+  {m68k_op_eori_16_al          , 0xffff, 0x0a79, 24},
+  {m68k_op_eori_16_tos         , 0xffff, 0x0a7c, 20},
+  {m68k_op_eori_32_aw          , 0xffff, 0x0ab8, 32},
+  {m68k_op_eori_32_al          , 0xffff, 0x0ab9, 36},
+  {m68k_op_cmpi_8_pi7          , 0xffff, 0x0c1f, 12},
+  {m68k_op_cmpi_8_pd7          , 0xffff, 0x0c27, 14},
+  {m68k_op_cmpi_8_aw           , 0xffff, 0x0c38, 16},
+  {m68k_op_cmpi_8_al           , 0xffff, 0x0c39, 20},
+  {m68k_op_cmpi_16_aw          , 0xffff, 0x0c78, 16},
+  {m68k_op_cmpi_16_al          , 0xffff, 0x0c79, 20},
+  {m68k_op_cmpi_32_aw          , 0xffff, 0x0cb8, 24},
+  {m68k_op_cmpi_32_al          , 0xffff, 0x0cb9, 28},
+  {m68k_op_move_8_aw_pi7       , 0xffff, 0x11df, 16},
+  {m68k_op_move_8_aw_pd7       , 0xffff, 0x11e7, 18},
+  {m68k_op_move_8_aw_aw        , 0xffff, 0x11f8, 20},
+  {m68k_op_move_8_aw_al        , 0xffff, 0x11f9, 24},
+  {m68k_op_move_8_aw_pcdi      , 0xffff, 0x11fa, 20},
+  {m68k_op_move_8_aw_pcix      , 0xffff, 0x11fb, 22},
+  {m68k_op_move_8_aw_i         , 0xffff, 0x11fc, 16},
+  {m68k_op_move_8_al_pi7       , 0xffff, 0x13df, 20},
+  {m68k_op_move_8_al_pd7       , 0xffff, 0x13e7, 22},
+  {m68k_op_move_8_al_aw        , 0xffff, 0x13f8, 24},
+  {m68k_op_move_8_al_al        , 0xffff, 0x13f9, 28},
+  {m68k_op_move_8_al_pcdi      , 0xffff, 0x13fa, 24},
+  {m68k_op_move_8_al_pcix      , 0xffff, 0x13fb, 26},
+  {m68k_op_move_8_al_i         , 0xffff, 0x13fc, 20},
+  {m68k_op_move_8_pi7_pi7      , 0xffff, 0x1edf, 12},
+  {m68k_op_move_8_pi7_pd7      , 0xffff, 0x1ee7, 14},
+  {m68k_op_move_8_pi7_aw       , 0xffff, 0x1ef8, 16},
+  {m68k_op_move_8_pi7_al       , 0xffff, 0x1ef9, 20},
+  {m68k_op_move_8_pi7_pcdi     , 0xffff, 0x1efa, 16},
+  {m68k_op_move_8_pi7_pcix     , 0xffff, 0x1efb, 18},
+  {m68k_op_move_8_pi7_i        , 0xffff, 0x1efc, 12},
+  {m68k_op_move_8_pd7_pi7      , 0xffff, 0x1f1f, 12},
+  {m68k_op_move_8_pd7_pd7      , 0xffff, 0x1f27, 14},
+  {m68k_op_move_8_pd7_aw       , 0xffff, 0x1f38, 16},
+  {m68k_op_move_8_pd7_al       , 0xffff, 0x1f39, 20},
+  {m68k_op_move_8_pd7_pcdi     , 0xffff, 0x1f3a, 16},
+  {m68k_op_move_8_pd7_pcix     , 0xffff, 0x1f3b, 18},
+  {m68k_op_move_8_pd7_i        , 0xffff, 0x1f3c, 12},
+  {m68k_op_move_32_aw_aw       , 0xffff, 0x21f8, 28},
+  {m68k_op_move_32_aw_al       , 0xffff, 0x21f9, 32},
+  {m68k_op_move_32_aw_pcdi     , 0xffff, 0x21fa, 28},
+  {m68k_op_move_32_aw_pcix     , 0xffff, 0x21fb, 30},
+  {m68k_op_move_32_aw_i        , 0xffff, 0x21fc, 24},
+  {m68k_op_move_32_al_aw       , 0xffff, 0x23f8, 32},
+  {m68k_op_move_32_al_al       , 0xffff, 0x23f9, 36},
+  {m68k_op_move_32_al_pcdi     , 0xffff, 0x23fa, 32},
+  {m68k_op_move_32_al_pcix     , 0xffff, 0x23fb, 34},
+  {m68k_op_move_32_al_i        , 0xffff, 0x23fc, 28},
+  {m68k_op_move_16_aw_aw       , 0xffff, 0x31f8, 20},
+  {m68k_op_move_16_aw_al       , 0xffff, 0x31f9, 24},
+  {m68k_op_move_16_aw_pcdi     , 0xffff, 0x31fa, 20},
+  {m68k_op_move_16_aw_pcix     , 0xffff, 0x31fb, 22},
+  {m68k_op_move_16_aw_i        , 0xffff, 0x31fc, 16},
+  {m68k_op_move_16_al_aw       , 0xffff, 0x33f8, 24},
+  {m68k_op_move_16_al_al       , 0xffff, 0x33f9, 28},
+  {m68k_op_move_16_al_pcdi     , 0xffff, 0x33fa, 24},
+  {m68k_op_move_16_al_pcix     , 0xffff, 0x33fb, 26},
+  {m68k_op_move_16_al_i        , 0xffff, 0x33fc, 20},
+  {m68k_op_negx_8_pi7          , 0xffff, 0x401f, 12},
+  {m68k_op_negx_8_pd7          , 0xffff, 0x4027, 14},
+  {m68k_op_negx_8_aw           , 0xffff, 0x4038, 16},
+  {m68k_op_negx_8_al           , 0xffff, 0x4039, 20},
+  {m68k_op_negx_16_aw          , 0xffff, 0x4078, 16},
+  {m68k_op_negx_16_al          , 0xffff, 0x4079, 20},
+  {m68k_op_negx_32_aw          , 0xffff, 0x40b8, 24},
+  {m68k_op_negx_32_al          , 0xffff, 0x40b9, 28},
+  {m68k_op_move_16_frs_aw      , 0xffff, 0x40f8, 16},
+  {m68k_op_move_16_frs_al      , 0xffff, 0x40f9, 20},
+  {m68k_op_clr_8_pi7           , 0xffff, 0x421f, 12},
+  {m68k_op_clr_8_pd7           , 0xffff, 0x4227, 14},
+  {m68k_op_clr_8_aw            , 0xffff, 0x4238, 16},
+  {m68k_op_clr_8_al            , 0xffff, 0x4239, 20},
+  {m68k_op_clr_16_aw           , 0xffff, 0x4278, 16},
+  {m68k_op_clr_16_al           , 0xffff, 0x4279, 20},
+  {m68k_op_clr_32_aw           , 0xffff, 0x42b8, 24},
+  {m68k_op_clr_32_al           , 0xffff, 0x42b9, 28},
+  {m68k_op_neg_8_pi7           , 0xffff, 0x441f, 12},
+  {m68k_op_neg_8_pd7           , 0xffff, 0x4427, 14},
+  {m68k_op_neg_8_aw            , 0xffff, 0x4438, 16},
+  {m68k_op_neg_8_al            , 0xffff, 0x4439, 20},
+  {m68k_op_neg_16_aw           , 0xffff, 0x4478, 16},
+  {m68k_op_neg_16_al           , 0xffff, 0x4479, 20},
+  {m68k_op_neg_32_aw           , 0xffff, 0x44b8, 24},
+  {m68k_op_neg_32_al           , 0xffff, 0x44b9, 28},
+  {m68k_op_move_16_toc_aw      , 0xffff, 0x44f8, 20},
+  {m68k_op_move_16_toc_al      , 0xffff, 0x44f9, 24},
+  {m68k_op_move_16_toc_pcdi    , 0xffff, 0x44fa, 20},
+  {m68k_op_move_16_toc_pcix    , 0xffff, 0x44fb, 22},
+  {m68k_op_move_16_toc_i       , 0xffff, 0x44fc, 16},
+  {m68k_op_not_8_pi7           , 0xffff, 0x461f, 12},
+  {m68k_op_not_8_pd7           , 0xffff, 0x4627, 14},
+  {m68k_op_not_8_aw            , 0xffff, 0x4638, 16},
+  {m68k_op_not_8_al            , 0xffff, 0x4639, 20},
+  {m68k_op_not_16_aw           , 0xffff, 0x4678, 16},
+  {m68k_op_not_16_al           , 0xffff, 0x4679, 20},
+  {m68k_op_not_32_aw           , 0xffff, 0x46b8, 24},
+  {m68k_op_not_32_al           , 0xffff, 0x46b9, 28},
+  {m68k_op_move_16_tos_aw      , 0xffff, 0x46f8, 20},
+  {m68k_op_move_16_tos_al      , 0xffff, 0x46f9, 24},
+  {m68k_op_move_16_tos_pcdi    , 0xffff, 0x46fa, 20},
+  {m68k_op_move_16_tos_pcix    , 0xffff, 0x46fb, 22},
+  {m68k_op_move_16_tos_i       , 0xffff, 0x46fc, 16},
+  {m68k_op_nbcd_8_pi7          , 0xffff, 0x481f, 12},
+  {m68k_op_nbcd_8_pd7          , 0xffff, 0x4827, 14},
+  {m68k_op_nbcd_8_aw           , 0xffff, 0x4838, 16},
+  {m68k_op_nbcd_8_al           , 0xffff, 0x4839, 20},
+  {m68k_op_pea_32_aw           , 0xffff, 0x4878, 16},
+  {m68k_op_pea_32_al           , 0xffff, 0x4879, 20},
+  {m68k_op_pea_32_pcdi         , 0xffff, 0x487a, 16},
+  {m68k_op_pea_32_pcix         , 0xffff, 0x487b, 20},
+  {m68k_op_movem_16_re_aw      , 0xffff, 0x48b8, 12},
+  {m68k_op_movem_16_re_al      , 0xffff, 0x48b9, 16},
+  {m68k_op_movem_32_re_aw      , 0xffff, 0x48f8, 12},
+  {m68k_op_movem_32_re_al      , 0xffff, 0x48f9, 16},
+  {m68k_op_tst_8_pi7           , 0xffff, 0x4a1f,  8},
+  {m68k_op_tst_8_pd7           , 0xffff, 0x4a27, 10},
+  {m68k_op_tst_8_aw            , 0xffff, 0x4a38, 12},
+  {m68k_op_tst_8_al            , 0xffff, 0x4a39, 16},
+  {m68k_op_tst_16_aw           , 0xffff, 0x4a78, 12},
+  {m68k_op_tst_16_al           , 0xffff, 0x4a79, 16},
+  {m68k_op_tst_32_aw           , 0xffff, 0x4ab8, 16},
+  {m68k_op_tst_32_al           , 0xffff, 0x4ab9, 20},
+  {m68k_op_tas_8_pi7           , 0xffff, 0x4adf, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pd7           , 0xffff, 0x4ae7, 16}, /* see Yacht.txt */
+  {m68k_op_tas_8_aw            , 0xffff, 0x4af8, 18}, /* see Yacht.txt */
+  {m68k_op_tas_8_al            , 0xffff, 0x4af9, 22}, /* see Yacht.txt */
+  {m68k_op_illegal             , 0xffff, 0x4afc,  4},
+  {m68k_op_movem_16_er_aw      , 0xffff, 0x4cb8, 16},
+  {m68k_op_movem_16_er_al      , 0xffff, 0x4cb9, 20},
+  {m68k_op_movem_16_er_pcdi    , 0xffff, 0x4cba, 16},
+  {m68k_op_movem_16_er_pcix    , 0xffff, 0x4cbb, 18},
+  {m68k_op_movem_32_er_aw      , 0xffff, 0x4cf8, 16},
+  {m68k_op_movem_32_er_al      , 0xffff, 0x4cf9, 20},
+  {m68k_op_movem_32_er_pcdi    , 0xffff, 0x4cfa, 16},
+  {m68k_op_movem_32_er_pcix    , 0xffff, 0x4cfb, 18},
+  {m68k_op_link_16_a7          , 0xffff, 0x4e57, 16},
+  {m68k_op_unlk_32_a7          , 0xffff, 0x4e5f, 12},
+  {m68k_op_reset               , 0xffff, 0x4e70,  0},
+  {m68k_op_nop                 , 0xffff, 0x4e71,  4},
+  {m68k_op_stop                , 0xffff, 0x4e72,  4},
+  {m68k_op_rte_32              , 0xffff, 0x4e73, 20},
+  {m68k_op_rts_32              , 0xffff, 0x4e75, 16},
+  {m68k_op_trapv               , 0xffff, 0x4e76,  4},
+  {m68k_op_rtr_32              , 0xffff, 0x4e77, 20},
+  {m68k_op_jsr_32_aw           , 0xffff, 0x4eb8, 18},
+  {m68k_op_jsr_32_al           , 0xffff, 0x4eb9, 20},
+  {m68k_op_jsr_32_pcdi         , 0xffff, 0x4eba, 18},
+  {m68k_op_jsr_32_pcix         , 0xffff, 0x4ebb, 22},
+  {m68k_op_jmp_32_aw           , 0xffff, 0x4ef8, 10},
+  {m68k_op_jmp_32_al           , 0xffff, 0x4ef9, 12},
+  {m68k_op_jmp_32_pcdi         , 0xffff, 0x4efa, 10},
+  {m68k_op_jmp_32_pcix         , 0xffff, 0x4efb, 14},
+  {m68k_op_st_8_pi7            , 0xffff, 0x50df, 12},
+  {m68k_op_st_8_pd7            , 0xffff, 0x50e7, 14},
+  {m68k_op_st_8_aw             , 0xffff, 0x50f8, 16},
+  {m68k_op_st_8_al             , 0xffff, 0x50f9, 20},
+  {m68k_op_sf_8_pi7            , 0xffff, 0x51df, 12},
+  {m68k_op_sf_8_pd7            , 0xffff, 0x51e7, 14},
+  {m68k_op_sf_8_aw             , 0xffff, 0x51f8, 16},
+  {m68k_op_sf_8_al             , 0xffff, 0x51f9, 20},
+  {m68k_op_shi_8_pi7           , 0xffff, 0x52df, 12},
+  {m68k_op_shi_8_pd7           , 0xffff, 0x52e7, 14},
+  {m68k_op_shi_8_aw            , 0xffff, 0x52f8, 16},
+  {m68k_op_shi_8_al            , 0xffff, 0x52f9, 20},
+  {m68k_op_sls_8_pi7           , 0xffff, 0x53df, 12},
+  {m68k_op_sls_8_pd7           , 0xffff, 0x53e7, 14},
+  {m68k_op_sls_8_aw            , 0xffff, 0x53f8, 16},
+  {m68k_op_sls_8_al            , 0xffff, 0x53f9, 20},
+  {m68k_op_scc_8_pi7           , 0xffff, 0x54df, 12},
+  {m68k_op_scc_8_pd7           , 0xffff, 0x54e7, 14},
+  {m68k_op_scc_8_aw            , 0xffff, 0x54f8, 16},
+  {m68k_op_scc_8_al            , 0xffff, 0x54f9, 20},
+  {m68k_op_scs_8_pi7           , 0xffff, 0x55df, 12},
+  {m68k_op_scs_8_pd7           , 0xffff, 0x55e7, 14},
+  {m68k_op_scs_8_aw            , 0xffff, 0x55f8, 16},
+  {m68k_op_scs_8_al            , 0xffff, 0x55f9, 20},
+  {m68k_op_sne_8_pi7           , 0xffff, 0x56df, 12},
+  {m68k_op_sne_8_pd7           , 0xffff, 0x56e7, 14},
+  {m68k_op_sne_8_aw            , 0xffff, 0x56f8, 16},
+  {m68k_op_sne_8_al            , 0xffff, 0x56f9, 20},
+  {m68k_op_seq_8_pi7           , 0xffff, 0x57df, 12},
+  {m68k_op_seq_8_pd7           , 0xffff, 0x57e7, 14},
+  {m68k_op_seq_8_aw            , 0xffff, 0x57f8, 16},
+  {m68k_op_seq_8_al            , 0xffff, 0x57f9, 20},
+  {m68k_op_svc_8_pi7           , 0xffff, 0x58df, 12},
+  {m68k_op_svc_8_pd7           , 0xffff, 0x58e7, 14},
+  {m68k_op_svc_8_aw            , 0xffff, 0x58f8, 16},
+  {m68k_op_svc_8_al            , 0xffff, 0x58f9, 20},
+  {m68k_op_svs_8_pi7           , 0xffff, 0x59df, 12},
+  {m68k_op_svs_8_pd7           , 0xffff, 0x59e7, 14},
+  {m68k_op_svs_8_aw            , 0xffff, 0x59f8, 16},
+  {m68k_op_svs_8_al            , 0xffff, 0x59f9, 20},
+  {m68k_op_spl_8_pi7           , 0xffff, 0x5adf, 12},
+  {m68k_op_spl_8_pd7           , 0xffff, 0x5ae7, 14},
+  {m68k_op_spl_8_aw            , 0xffff, 0x5af8, 16},
+  {m68k_op_spl_8_al            , 0xffff, 0x5af9, 20},
+  {m68k_op_smi_8_pi7           , 0xffff, 0x5bdf, 12},
+  {m68k_op_smi_8_pd7           , 0xffff, 0x5be7, 14},
+  {m68k_op_smi_8_aw            , 0xffff, 0x5bf8, 16},
+  {m68k_op_smi_8_al            , 0xffff, 0x5bf9, 20},
+  {m68k_op_sge_8_pi7           , 0xffff, 0x5cdf, 12},
+  {m68k_op_sge_8_pd7           , 0xffff, 0x5ce7, 14},
+  {m68k_op_sge_8_aw            , 0xffff, 0x5cf8, 16},
+  {m68k_op_sge_8_al            , 0xffff, 0x5cf9, 20},
+  {m68k_op_slt_8_pi7           , 0xffff, 0x5ddf, 12},
+  {m68k_op_slt_8_pd7           , 0xffff, 0x5de7, 14},
+  {m68k_op_slt_8_aw            , 0xffff, 0x5df8, 16},
+  {m68k_op_slt_8_al            , 0xffff, 0x5df9, 20},
+  {m68k_op_sgt_8_pi7           , 0xffff, 0x5edf, 12},
+  {m68k_op_sgt_8_pd7           , 0xffff, 0x5ee7, 14},
+  {m68k_op_sgt_8_aw            , 0xffff, 0x5ef8, 16},
+  {m68k_op_sgt_8_al            , 0xffff, 0x5ef9, 20},
+  {m68k_op_sle_8_pi7           , 0xffff, 0x5fdf, 12},
+  {m68k_op_sle_8_pd7           , 0xffff, 0x5fe7, 14},
+  {m68k_op_sle_8_aw            , 0xffff, 0x5ff8, 16},
+  {m68k_op_sle_8_al            , 0xffff, 0x5ff9, 20},
+  {m68k_op_bra_16              , 0xffff, 0x6000, 10},
+  {m68k_op_bra_32              , 0xffff, 0x60ff, 10},
+  {m68k_op_bsr_16              , 0xffff, 0x6100, 18},
+  {m68k_op_bsr_32              , 0xffff, 0x61ff, 18},
+  {m68k_op_bhi_16              , 0xffff, 0x6200, 10},
+  {m68k_op_bhi_32              , 0xffff, 0x62ff, 10},
+  {m68k_op_bls_16              , 0xffff, 0x6300, 10},
+  {m68k_op_bls_32              , 0xffff, 0x63ff, 10},
+  {m68k_op_bcc_16              , 0xffff, 0x6400, 10},
+  {m68k_op_bcc_32              , 0xffff, 0x64ff, 10},
+  {m68k_op_bcs_16              , 0xffff, 0x6500, 10},
+  {m68k_op_bcs_32              , 0xffff, 0x65ff, 10},
+  {m68k_op_bne_16              , 0xffff, 0x6600, 10},
+  {m68k_op_bne_32              , 0xffff, 0x66ff, 10},
+  {m68k_op_beq_16              , 0xffff, 0x6700, 10},
+  {m68k_op_beq_32              , 0xffff, 0x67ff, 10},
+  {m68k_op_bvc_16              , 0xffff, 0x6800, 10},
+  {m68k_op_bvc_32              , 0xffff, 0x68ff, 10},
+  {m68k_op_bvs_16              , 0xffff, 0x6900, 10},
+  {m68k_op_bvs_32              , 0xffff, 0x69ff, 10},
+  {m68k_op_bpl_16              , 0xffff, 0x6a00, 10},
+  {m68k_op_bpl_32              , 0xffff, 0x6aff, 10},
+  {m68k_op_bmi_16              , 0xffff, 0x6b00, 10},
+  {m68k_op_bmi_32              , 0xffff, 0x6bff, 10},
+  {m68k_op_bge_16              , 0xffff, 0x6c00, 10},
+  {m68k_op_bge_32              , 0xffff, 0x6cff, 10},
+  {m68k_op_blt_16              , 0xffff, 0x6d00, 10},
+  {m68k_op_blt_32              , 0xffff, 0x6dff, 10},
+  {m68k_op_bgt_16              , 0xffff, 0x6e00, 10},
+  {m68k_op_bgt_32              , 0xffff, 0x6eff, 10},
+  {m68k_op_ble_16              , 0xffff, 0x6f00, 10},
+  {m68k_op_ble_32              , 0xffff, 0x6fff, 10},
+  {m68k_op_sbcd_8_mm_axy7      , 0xffff, 0x8f0f, 18},
+  {m68k_op_subx_8_mm_axy7      , 0xffff, 0x9f0f, 18},
+  {m68k_op_cmpm_8_axy7         , 0xffff, 0xbf0f, 12},
+  {m68k_op_abcd_8_mm_axy7      , 0xffff, 0xcf0f, 18},
+  {m68k_op_addx_8_mm_axy7      , 0xffff, 0xdf0f, 18},
+  {m68k_op_asr_16_aw           , 0xffff, 0xe0f8, 16},
+  {m68k_op_asr_16_al           , 0xffff, 0xe0f9, 20},
+  {m68k_op_asl_16_aw           , 0xffff, 0xe1f8, 16},
+  {m68k_op_asl_16_al           , 0xffff, 0xe1f9, 20},
+  {m68k_op_lsr_16_aw           , 0xffff, 0xe2f8, 16},
+  {m68k_op_lsr_16_al           , 0xffff, 0xe2f9, 20},
+  {m68k_op_lsl_16_aw           , 0xffff, 0xe3f8, 16},
+  {m68k_op_lsl_16_al           , 0xffff, 0xe3f9, 20},
+  {m68k_op_roxr_16_aw          , 0xffff, 0xe4f8, 16},
+  {m68k_op_roxr_16_al          , 0xffff, 0xe4f9, 20},
+  {m68k_op_roxl_16_aw          , 0xffff, 0xe5f8, 16},
+  {m68k_op_roxl_16_al          , 0xffff, 0xe5f9, 20},
+  {m68k_op_ror_16_aw           , 0xffff, 0xe6f8, 16},
+  {m68k_op_ror_16_al           , 0xffff, 0xe6f9, 20},
+  {m68k_op_rol_16_aw           , 0xffff, 0xe7f8, 16},
+  {m68k_op_rol_16_al           , 0xffff, 0xe7f9, 20},
+  {0, 0, 0, 0}
+};
+
+
+/* Build the opcode handler jump table */
+static void __inline m68ki_build_opcode_table(void)
+{
+  const opcode_handler_struct *ostruct;
+  int instr;
+  int i;
+  int j;
+
+  for(i = 0; i < 0x10000; i++)
+  {
+    /* default to illegal */
+    m68ki_instruction_jump_table[i] = m68k_op_illegal;
+    m68ki_cycles[i] = 4;
+  }
+
+  ostruct = &m68k_opcode_handler_table[0];
+  while(ostruct->mask != 0xff00)
+  {
+    for(i = 0;i < 0x10000;i++)
+    {
+      if((i & ostruct->mask) == ostruct->match)
+      {
+        m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
+        m68ki_cycles[i] = ostruct->cycles * MUL;
+      }
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xff00)
+  {
+    for(i = 0;i <= 0xff;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xf1f8)
+  {
+    for(i = 0;i < 8;i++)
+    {
+      for(j = 0;j < 8;j++)
+      {
+        instr = ostruct->match | (i << 9) | j;
+        m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
+        m68ki_cycles[instr] = ostruct->cycles * MUL;
+      }
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xfff0)
+  {
+    for(i = 0;i <= 0x0f;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xf1ff)
+  {
+    for(i = 0;i <= 0x07;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | (i << 9)] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xfff8)
+  {
+    for(i = 0;i <= 0x07;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xffff)
+  {
+    m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
+    m68ki_cycles[ostruct->match] = ostruct->cycles * MUL;
+    ostruct++;
+  }
+}
+
+#endif
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/macros.h b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/macros.h
new file mode 100755
index 0000000..b3a639b
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/macros.h
@@ -0,0 +1,70 @@
+#ifndef _MACROS_H_
+#define _MACROS_H_
+
+#ifdef LSB_FIRST
+
+#define READ_BYTE(BASE, ADDR) (BASE)[(ADDR)^1]
+
+#define READ_WORD(BASE, ADDR) (((BASE)[ADDR]<<8) | (BASE)[(ADDR)+1])
+
+#define READ_WORD_LONG(BASE, ADDR) (((BASE)[(ADDR)+1]<<24) |      \
+                                    ((BASE)[(ADDR)]<<16) |  \
+                                    ((BASE)[(ADDR)+3]<<8) |   \
+                                    (BASE)[(ADDR)+2])
+
+#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[(ADDR)^1] = (VAL)&0xff
+
+#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[ADDR] = ((VAL)>>8) & 0xff; \
+                                      (BASE)[(ADDR)+1] = (VAL)&0xff
+
+#define WRITE_WORD_LONG(BASE, ADDR, VAL) (BASE)[(ADDR+1)] = ((VAL)>>24) & 0xff;    \
+                                          (BASE)[(ADDR)] = ((VAL)>>16)&0xff;  \
+                                          (BASE)[(ADDR+3)] = ((VAL)>>8)&0xff;   \
+                                          (BASE)[(ADDR+2)] = (VAL)&0xff
+
+#else
+
+#define READ_BYTE(BASE, ADDR) (BASE)[ADDR]
+#define READ_WORD(BASE, ADDR) *(uint16 *)((BASE) + (ADDR))
+#define READ_WORD_LONG(BASE, ADDR) *(uint32 *)((BASE) + (ADDR))
+#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[ADDR] = VAL & 0xff
+#define WRITE_WORD(BASE, ADDR, VAL) *(uint16 *)((BASE) + (ADDR)) = VAL & 0xffff
+#define WRITE_WORD_LONG(BASE, ADDR, VAL) *(uint32 *)((BASE) + (ADDR)) = VAL & 0xffffffff
+#endif
+
+/* C89 compatibility */
+#ifndef M_PI
+#define M_PI 3.14159265358979323846264338327f
+#endif /* M_PI */
+
+/* Set to your compiler's static inline keyword to enable it, or
+ * set it to blank to disable it.
+ * If you define INLINE in makefile or osd.h, it will override this value.
+ * NOTE: not enabling inline functions will SEVERELY slow down emulation.
+ */
+#ifndef INLINE
+#define INLINE static __inline__
+#endif /* INLINE */
+
+/* Alignment macros for cross compiler compatibility */
+#if defined(_MSC_VER)
+#define ALIGNED_(x) __declspec(align(x))
+#elif defined(__GNUC__)
+#define ALIGNED_(x) __attribute__ ((aligned(x)))
+#endif
+
+/* Default CD image file access (read-only) functions */
+/* If you need to override default stdio.h functions with custom filesystem API,
+   redefine following macros in platform specific include file (osd.h) or Makefile
+*/
+#ifndef cdStream
+#define cdStream            FILE
+#define cdStreamOpen(fname) fopen(fname, "rb")
+#define cdStreamClose       fclose
+#define cdStreamRead        fread
+#define cdStreamSeek        fseek
+#define cdStreamTell        ftell
+#define cdStreamGets        fgets
+#endif
+
+#endif /* _MACROS_H_ */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/M68K/readme.txt b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/readme.txt
new file mode 100755
index 0000000..9154901
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/M68K/readme.txt
@@ -0,0 +1,315 @@
+                                    MUSASHI
+                                    =======
+
+                                  Version 3.3
+
+             A portable Motorola M680x0 processor emulation engine.
+            Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+
+
+
+INTRODUCTION:
+------------
+
+Musashi is a Motorola 68000, 68010, 68EC020, and 68020 emulator written in C.
+This emulator was written with two goals in mind: portability and speed.
+
+The emulator is written to ANSI C specifications with the exception that I use
+inline functions.  This is not compliant to the ANSI spec, but will be
+compliant to the ANSI C9X spec.
+
+It has been successfully running in the MAME project (www.mame.net) for over 2
+years and so has had time to mature.
+
+
+
+LICENSE AND COPYRIGHT:
+---------------------
+
+The Musashi M680x0 emulator is copyright 1998-2001 Karl Stenerud.
+
+The source code included in this archive is provided AS-IS, free for any
+non-commercial purpose.
+
+If you build a program using this core, please give credit to the author.
+
+If you wish to use this core in a commercial environment, please contact
+the author to discuss commercial licensing.
+
+
+
+AVAILABILITY:
+------------
+The latest version of this code can be obtained at:
+http://kstenerud.cjb.net
+
+
+
+CONTACTING THE AUTHOR:
+---------------------
+I can be reached at kstenerud@mame.net
+
+
+
+BASIC CONFIGURATION:
+-------------------
+The basic configuration will give you a standard 68000 that has sufficient
+functionality to work in a primitive environment.
+
+This setup assumes that you only have 1 device interrupting it, that the
+device will always request an autovectored interrupt, and it will always clear
+the interrupt before the interrupt service routine finishes (but could
+possibly re-assert the interrupt).
+You will have only one address space, no tracing, and no instruction prefetch.
+
+To implement the basic configuration:
+
+- Open m68kconf.h and verify that the settings for INLINE and DECL_SPEC will
+  work with your compiler. (They are set for gcc)
+
+- In your host program, implement the following functions:
+    unsigned int  m68k_read_memory_8(unsigned int address);
+    unsigned int  m68k_read_memory_16(unsigned int address);
+    unsigned int  m68k_read_memory_32(unsigned int address);
+    void m68k_write_memory_8(unsigned int address, unsigned int value);
+    void m68k_write_memory_16(unsigned int address, unsigned int value);
+    void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+- In your host program, be sure to call m68k_pulse_reset() once before calling
+  any of the other functions as this initializes the core.
+
+- Use m68k_execute() to execute instructions and m68k_set_irq() to cause an
+  interrupt.
+
+
+
+ADDING PROPER INTERRUPT HANDLING:
+--------------------------------
+The interrupt handling in the basic configuration doesn't emulate the
+interrupt acknowledge phase of the CPU and automatically clears an interrupt
+request during interrupt processing.
+While this works for most systems, you may need more accurate interrupt
+handling.
+
+To add proper interrupt handling:
+
+- In m68kconf.h, set M68K_EMULATE_INT_ACK to OPT_SPECIFY_HANDLER
+
+- In m68kconf.h, set M68K_INT_ACK_CALLBACK(A) to your interrupt acknowledge
+  routine
+
+- Your interrupt acknowledge routine must return an interrupt vector,
+  M68K_INT_ACK_AUTOVECTOR, or M68K_INT_ACK_SPURIOUS.  most m68k
+  implementations just use autovectored interrupts.
+
+- When the interrupting device is satisfied, you must call m68k_set_irq(0) to
+  remove the interrupt request.
+
+
+
+MULTIPLE INTERRUPTS:
+-------------------
+The above system will work if you have only one device interrupting the CPU,
+but if you have more than one device, you must do a bit more.
+
+To add multiple interrupts:
+
+- You must make an interrupt arbitration device that will take the highest
+  priority interrupt and encode it onto the IRQ pins on the CPU.
+
+- The interrupt arbitration device should use m68k_set_irq() to set the
+  highest pending interrupt, or 0 for no interrupts pending.
+
+
+
+SEPARATE IMMEDIATE AND PC-RELATIVE READS:
+----------------------------------------
+You can write faster memory access functions if you know whether you are
+fetching from ROM or RAM.  Immediate reads are always from the program space
+(Always in ROM unless it is running self-modifying code).
+This will also separate the pc-relative reads, since some systems treat
+PROGRAM mode reads and DATA mode reads differently (for program encryption,
+for instance).  See the section below (ADDRESS SPACE) for an explanation of
+PROGRAM and DATA mode.
+
+To enable separate reads:
+
+- In m68kconf.h, turn on M68K_SEPARATE_READS.
+
+- In your host program, implement the following functions:
+    unsigned int  m68k_read_immediate_16(unsigned int address);
+    unsigned int  m68k_read_immediate_32(unsigned int address);
+
+    unsigned int  m68k_read_pcrelative_8(unsigned int address);
+    unsigned int  m68k_read_pcrelative_16(unsigned int address);
+    unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+- If you need to know the current PC (for banking and such), set
+  M68K_MONITOR_PC to OPT_SPECIFY_HANDLER, and set M68K_SET_PC_CALLBACK(A) to
+  your routine.
+
+
+
+ADDRESS SPACES:
+--------------
+Most systems will only implement one address space, placing ROM at the lower
+addresses and RAM at the higher.  However, there is the possibility that a
+system will implement ROM and RAM in the same address range, but in different
+address spaces, or will have different mamory types that require different
+handling for the program and the data.
+
+The 68k accomodates this by allowing different program spaces, the most
+important to us being PROGRAM and DATA space.  Here is a breakdown of
+how information is fetched:
+
+- All immediate reads are fetched from PROGRAM space.
+
+- All PC-relative reads are fetched from PROGRAM space.
+
+- The initial stack pointer and program counter are fetched from PROGRAM space.
+
+- All other reads (except for those from the moves instruction for 68020)
+   are fetched from DATA space.
+
+The m68k deals with this by encoding the requested address space on the
+function code pins:
+
+                       FC
+    Address Space      210
+    ------------------ ---
+    USER DATA          001
+    USER PROGRAM       010
+    SUPERVISOR DATA    101
+    SUPERVISOR PROGRAM 110
+    CPU SPACE          111 <-- not emulated in this core since we emulate
+                               interrupt acknowledge in another way.
+
+Problems arise here if you need to emulate this distinction (if, for example,
+your ROM and RAM are at the same address range, with RAM and ROM enable
+wired to the function code pins).
+
+There are 2 ways to deal with this situation using Musashi:
+
+1. If you only need the distinction between PROGRAM and DATA (the most common),
+   you can just separate the reads (see the preceeding section).  This is the
+   faster solution.
+
+2. You can emulate the function code pins entirely.
+
+To emulate the function code pins:
+
+- In m68kconf.h, set M68K_EMULATE_FC to OPT_SPECIFY_HANDLER and set
+  M68K_SET_FC_CALLBACK(A) to your function code handler function.
+
+- Your function code handler should select the proper address space for
+  subsequent calls to m68k_read_xx (and m68k_write_xx for 68010+).
+
+Note: immediate reads are always done from program space, so technically you
+      don't need to implement the separate immediate reads, although you could
+      gain more speed improvements leaving them in and doing some clever
+      programming.
+
+
+
+USING DIFFERENT CPU TYPES:
+-------------------------
+The default is to enable only the 68000 cpu type.  To change this, change the
+settings for M68K_EMULATE_010 etc in m68kconf.h.
+
+To set the CPU type you want to use:
+
+- Make sure it is enabled in m68kconf.h.  Current switches are:
+    M68K_EMULATE_010
+    M68K_EMULATE_EC020
+    M68K_EMULATE_020
+
+- In your host program, call m68k_set_cpu_type() and then call
+  m68k_pulse_reset().  Valid CPU types are:
+    M68K_CPU_TYPE_68000,
+    M68K_CPU_TYPE_68010,
+    M68K_CPU_TYPE_68EC020,
+    M68K_CPU_TYPE_68020
+
+
+
+CLOCK FREQUENCY:
+---------------
+In order to emulate the correct clock frequency, you will have to calculate
+how long it takes the emulation to execute a certain number of "cycles" and
+vary your calls to m68k_execute() accordingly.
+As well, it is a good idea to take away the CPU's timeslice when it writes to
+a memory-mapped port in order to give the device it wrote to a chance to
+react.
+
+You can use the functions m68k_cycles_run(), m68k_cycles_remaining(),
+m68k_modify_timeslice(), and m68k_end_timeslice() to do this.
+Try to use large cycle values in your calls to m68k_execute() since it will
+increase throughput.  You can always take away the timeslice later.
+
+
+
+MORE CORRECT EMULATION:
+----------------------
+You may need to enable these in order to properly emulate some of the more
+obscure functions of the m68k:
+
+- M68K_EMULATE_BKPT_ACK causes the CPU to call a breakpoint handler on a BKPT
+  instruction
+
+- M68K_EMULATE_TRACE causes the CPU to generate trace exceptions when the
+  trace bits are set
+
+- M68K_EMULATE_RESET causes the CPU to call a reset handler on a RESET
+  instruction.
+
+- M68K_EMULATE_PREFETCH emulates the 4-word instruction prefetch that is part
+  of the 68000/68010 (needed for Amiga emulation).
+
+- call m68k_pulse_halt() to emulate the HALT pin.
+
+
+
+CONVENIENCE FUNCTIONS:
+---------------------
+These are in here for programmer convenience:
+
+- M68K_INSTRUCTION_HOOK lets you call a handler before each instruction.
+
+- M68K_LOG_ENABLE and M68K_LOG_1010_1111 lets you log illegal and A/F-line
+  instructions.
+
+
+
+MULTIPLE CPU EMULATION:
+----------------------
+The default is to use only one CPU.  To use more than one CPU in this core,
+there are some things to keep in mind:
+
+- To have different cpus call different functions, use OPT_ON instead of
+  OPT_SPECIFY_HANDLER, and use the m68k_set_xxx_callback() functions to set
+  your callback handlers on a per-cpu basis.
+
+- Be sure to call set_cpu_type() for each CPU you use.
+
+- Use m68k_set_context() and m68k_get_context() to switch to another CPU.
+
+
+
+LOAD AND SAVE CPU CONTEXTS FROM DISK:
+------------------------------------
+You can use them68k_load_context() and m68k_save_context() functions to load
+and save the CPU state to disk.
+
+
+
+GET/SET INFORMATION FROM THE CPU:
+--------------------------------
+You can use m68k_get_reg() and m68k_set_reg() to gain access to the internals
+of the CPU.
+
+
+
+EXAMPLE:
+-------
+
+I have included a file example.zip that contains a full example.
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Codes.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Codes.h
new file mode 100755
index 0000000..ab5cc6e
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Codes.h
@@ -0,0 +1,385 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Codes.h                        **/
+/**                                                         **/
+/** This file contains implementation for the main table of **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->HL.B.h);break;
+case ADD_L:    M_ADD(R->HL.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->HL.B.h);break;
+case SUB_L:    M_SUB(R->HL.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->HL.B.h);break;
+case AND_L:    M_AND(R->HL.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->HL.B.h);break;
+case OR_L:     M_OR(R->HL.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->HL.B.h);break;
+case ADC_L:    M_ADC(R->HL.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->HL.B.h);break;
+case SBC_L:    M_SBC(R->HL.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->HL.B.h);break;
+case XOR_L:    M_XOR(R->HL.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->HL.B.h);break;
+case CP_L:     M_CP(R->HL.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(HL);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->HL.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->HL.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(HL,BC);break;
+case ADD_HL_DE:  M_ADDW(HL,DE);break;
+case ADD_HL_HL:  M_ADDW(HL,HL);break;
+case ADD_HL_SP:  M_ADDW(HL,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->HL.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->HL.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->HL.B.h);break;
+case DEC_L:    M_DEC(R->HL.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->HL.B.h);break;
+case INC_L:    M_INC(R->HL.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+
+case RLCA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(HL);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(HL);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
+case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
+case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
+case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
+case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
+case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
+case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
+case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
+case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
+case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
+case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
+case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
+case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
+case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
+case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
+case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
+case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
+case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
+case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
+case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->HL.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->HL.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: WrZ80(R->HL.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++); 
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
+  R->HL.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
+
+default:
+  if(R->TrapBadOps)
+    printf
+    (
+      "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
+      (long)R->User,OpZ80(R->PC.W-1),R->PC.W-1
+    );
+  break;
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesCB.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesCB.h
new file mode 100755
index 0000000..dd904d4
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesCB.h
@@ -0,0 +1,204 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesCB.h                       **/
+/**                                                         **/
+/** This file contains implementation for the CB table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
+case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
+case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
+case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
+case RLC_A: M_RLC(R->AF.B.h);break;
+
+case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
+case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
+case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
+case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
+case RRC_A: M_RRC(R->AF.B.h);break;
+
+case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
+case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
+case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
+case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
+case RL_A: M_RL(R->AF.B.h);break;
+
+case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
+case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
+case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
+case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
+case RR_A: M_RR(R->AF.B.h);break;
+
+case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
+case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
+case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
+case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
+case SLA_A: M_SLA(R->AF.B.h);break;
+
+case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
+case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
+case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
+case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
+case SRA_A: M_SRA(R->AF.B.h);break;
+
+case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
+case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
+case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
+case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
+case SLL_A: M_SLL(R->AF.B.h);break;
+
+case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
+case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
+case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
+case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
+case SRL_A: M_SRL(R->AF.B.h);break;
+    
+case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
+case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
+case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
+case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,R->AF.B.h);break;
+
+case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
+case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
+case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
+case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,R->AF.B.h);break;
+
+case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
+case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
+case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
+case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,R->AF.B.h);break;
+
+case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
+case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
+case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
+case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,R->AF.B.h);break;
+
+case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
+case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
+case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
+case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,R->AF.B.h);break;
+
+case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
+case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
+case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
+case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,R->AF.B.h);break;
+
+case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
+case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
+case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
+case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,R->AF.B.h);break;
+
+case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
+case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
+case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
+case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,R->AF.B.h);break;
+
+case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
+case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
+case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
+case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
+case RES0_A: M_RES(0,R->AF.B.h);break;
+
+case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
+case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
+case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
+case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
+case RES1_A: M_RES(1,R->AF.B.h);break;
+
+case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
+case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
+case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
+case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
+case RES2_A: M_RES(2,R->AF.B.h);break;
+
+case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
+case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
+case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
+case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
+case RES3_A: M_RES(3,R->AF.B.h);break;
+
+case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
+case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
+case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
+case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
+case RES4_A: M_RES(4,R->AF.B.h);break;
+
+case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
+case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
+case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
+case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
+case RES5_A: M_RES(5,R->AF.B.h);break;
+
+case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
+case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
+case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
+case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
+case RES6_A: M_RES(6,R->AF.B.h);break;
+
+case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
+case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
+case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
+case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
+case RES7_A: M_RES(7,R->AF.B.h);break;
+
+case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
+case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
+case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
+case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
+case SET0_A: M_SET(0,R->AF.B.h);break;
+
+case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
+case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
+case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
+case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
+case SET1_A: M_SET(1,R->AF.B.h);break;
+
+case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
+case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
+case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
+case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
+case SET2_A: M_SET(2,R->AF.B.h);break;
+
+case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
+case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
+case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
+case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
+case SET3_A: M_SET(3,R->AF.B.h);break;
+
+case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
+case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
+case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
+case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
+case SET4_A: M_SET(4,R->AF.B.h);break;
+
+case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
+case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
+case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
+case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
+case SET5_A: M_SET(5,R->AF.B.h);break;
+
+case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
+case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
+case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
+case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
+case SET6_A: M_SET(6,R->AF.B.h);break;
+
+case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
+case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
+case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
+case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
+case SET7_A: M_SET(7,R->AF.B.h);break;
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesED.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesED.h
new file mode 100755
index 0000000..075ec99
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesED.h
@@ -0,0 +1,304 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesED.h                       **/
+/**                                                         **/
+/** This file contains implementation for the ED table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+/** This is a special patch for emulating BIOS calls: ********/
+case DB_FE:     PatchZ80(R);break;
+/*************************************************************/
+
+case ADC_HL_BC: M_ADCW(BC);break;
+case ADC_HL_DE: M_ADCW(DE);break;
+case ADC_HL_HL: M_ADCW(HL);break;
+case ADC_HL_SP: M_ADCW(SP);break;
+
+case SBC_HL_BC: M_SBCW(BC);break;
+case SBC_HL_DE: M_SBCW(DE);break;
+case SBC_HL_HL: M_SBCW(HL);break;
+case SBC_HL_SP: M_SBCW(SP);break;
+
+case LD_xWORDe_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+case LD_xWORDe_DE:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->DE.B.l);
+  WrZ80(J.W,R->DE.B.h);
+  break;
+case LD_xWORDe_BC:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->BC.B.l);
+  WrZ80(J.W,R->BC.B.h);
+  break;
+case LD_xWORDe_SP:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->SP.B.l);
+  WrZ80(J.W,R->SP.B.h);
+  break;
+
+case LD_HL_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+case LD_DE_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->DE.B.l=RdZ80(J.W++);
+  R->DE.B.h=RdZ80(J.W);
+  break;
+case LD_BC_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->BC.B.l=RdZ80(J.W++);
+  R->BC.B.h=RdZ80(J.W);
+  break;
+case LD_SP_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->SP.B.l=RdZ80(J.W++);
+  R->SP.B.h=RdZ80(J.W);
+  break;
+
+case RRD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I>>4)|(R->AF.B.h<<4);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+case RLD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+
+case LD_A_I:
+  R->AF.B.h=R->I;
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_A_R:
+  R->R++;
+  R->AF.B.h=(byte)(R->R-R->ICount);
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_I_A:   R->I=R->AF.B.h;break;
+case LD_R_A:   break;
+
+case IM_0:     R->IFF&=~(IFF_IM1|IFF_IM2);break;
+case IM_1:     R->IFF=(R->IFF&~IFF_IM2)|IFF_IM1;break;
+case IM_2:     R->IFF=(R->IFF&~IFF_IM1)|IFF_IM2;break;
+
+case RETI:
+case RETN:     if(R->IFF&IFF_2) R->IFF|=IFF_1; else R->IFF&=~IFF_1;
+               M_RET;break;
+
+case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+
+case IN_B_xC:  M_IN(R->BC.B.h);break;
+case IN_C_xC:  M_IN(R->BC.B.l);break;
+case IN_D_xC:  M_IN(R->DE.B.h);break;
+case IN_E_xC:  M_IN(R->DE.B.l);break;
+case IN_H_xC:  M_IN(R->HL.B.h);break;
+case IN_L_xC:  M_IN(R->HL.B.l);break;
+case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_F_xC:  M_IN(J.B.l);break;
+
+case OUT_xC_B: OutZ80(R->BC.W,R->BC.B.h);break;
+case OUT_xC_C: OutZ80(R->BC.W,R->BC.B.l);break;
+case OUT_xC_D: OutZ80(R->BC.W,R->DE.B.h);break;
+case OUT_xC_E: OutZ80(R->BC.W,R->DE.B.l);break;
+case OUT_xC_H: OutZ80(R->BC.W,R->HL.B.h);break;
+case OUT_xC_L: OutZ80(R->BC.W,R->HL.B.l);break;
+case OUT_xC_A: OutZ80(R->BC.W,R->AF.B.h);break;
+
+case INI:
+  WrZ80(R->HL.W++,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INIR:
+  do
+  {
+    WrZ80(R->HL.W++,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case IND:
+  WrZ80(R->HL.W--,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INDR:
+  do
+  {
+    WrZ80(R->HL.W--,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTI:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W++);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTIR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W++);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case OUTD:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W--);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTDR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W--);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case LDI:
+  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDIR:
+  do
+  {
+    WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case LDD:
+  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDDR:
+  do
+  {
+    WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case CPI:
+  I=RdZ80(R->HL.W++);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }  
+  while(R->BC.W&&J.B.l&&(R->ICount>0));
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;  
+
+case CPD:
+  I=RdZ80(R->HL.W--);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&J.B.l);
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXCB.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXCB.h
new file mode 100755
index 0000000..9a89306
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXCB.h
@@ -0,0 +1,64 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXCB.h                      **/
+/**                                                         **/
+/** This file contains implementation for FD/DD-CB tables   **/
+/** of Z80 commands. It is included from Z80.c.             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
+case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
+case RL_xHL:  I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
+case RR_xHL:  I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
+case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
+case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
+case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
+case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
+
+case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
+case BIT0_H: case BIT0_L: case BIT0_A:
+case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
+case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
+case BIT1_H: case BIT1_L: case BIT1_A:
+case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
+case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
+case BIT2_H: case BIT2_L: case BIT2_A:
+case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
+case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
+case BIT3_H: case BIT3_L: case BIT3_A:
+case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
+case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
+case BIT4_H: case BIT4_L: case BIT4_A:
+case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
+case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
+case BIT5_H: case BIT5_L: case BIT5_A:
+case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
+case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
+case BIT6_H: case BIT6_L: case BIT6_A:
+case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
+case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
+case BIT7_H: case BIT7_L: case BIT7_A:
+case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
+
+case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
+case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;   
+case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;   
+case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;   
+case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;   
+case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;   
+case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;   
+case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;   
+
+case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;   
+case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break; 
+case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break; 
+case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break; 
+case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break; 
+case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break; 
+case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break; 
+case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break; 
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXX.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXX.h
new file mode 100755
index 0000000..ad84f45
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/CodesXX.h
@@ -0,0 +1,396 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXX.h                       **/
+/**                                                         **/
+/** This file contains implementation for FD/DD tables of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->XX.B.h);break;
+case ADD_L:    M_ADD(R->XX.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->XX.B.h);break;
+case SUB_L:    M_SUB(R->XX.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->XX.B.h);break;
+case AND_L:    M_AND(R->XX.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->XX.B.h);break;
+case OR_L:     M_OR(R->XX.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->XX.B.h);break;
+case ADC_L:    M_ADC(R->XX.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->XX.B.h);break;
+case SBC_L:    M_SBC(R->XX.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->XX.B.h);break;
+case XOR_L:    M_XOR(R->XX.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->XX.B.h);break;
+case CP_L:     M_CP(R->XX.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(XX);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->XX.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->XX.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(XX,BC);break;
+case ADD_HL_DE:  M_ADDW(XX,DE);break;
+case ADD_HL_HL:  M_ADDW(XX,XX);break;
+case ADD_HL_SP:  M_ADDW(XX,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->XX.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->XX.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->XX.B.h);break;
+case DEC_L:    M_DEC(R->XX.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->XX.B.h);break;
+case INC_L:    M_INC(R->XX.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case RLCA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(XX);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(XX);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
+case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
+case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
+case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
+case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
+case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
+case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
+case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
+case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
+case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
+case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
+case LD_xHL_H: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
+case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
+case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
+case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
+case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
+case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
+case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
+case LD_xHL_L: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
+case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->XX.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->XX.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+                  WrZ80(J.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->XX.B.l);
+  WrZ80(J.W,R->XX.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->XX.B.l=RdZ80(J.W++);
+  R->XX.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
+  R->XX.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/ConDebug.c b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/ConDebug.c
new file mode 100755
index 0000000..92ab27a
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/ConDebug.c
@@ -0,0 +1,278 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                       ConDebug.c                        **/
+/**                                                         **/
+/** This file contains a console version of the built-in    **/
+/** debugger, using EMULib's Console.c. When -DCONDEBUG is  **/
+/** ommitted, ConDebug.c just includes the default command  **/
+/** line based debugger (Debug.c).                          **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2005-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#ifdef DEBUG
+
+#ifndef CONDEBUG
+/** Normal DebugZ80() ****************************************/
+/** When CONDEBUG #undefined, we use plain command line.    **/
+/*************************************************************/
+#include "Debug.c"
+
+#else
+/** Console DebugZ80() ***************************************/
+/** When CONDEBUG #defined, we use EMULib console.          **/
+/*************************************************************/
+
+#include "Z80.h"
+#include "Console.h"
+#include <stdlib.h>
+
+#define DebugZ80 OriginalDebugZ80
+#include "Debug.c"
+#undef DebugZ80
+
+#define CLR_BACK   PIXEL(255,255,255)
+#define CLR_TEXT   PIXEL(0,0,0)
+#define CLR_DIALOG PIXEL(0,100,0)
+#define CLR_PC     PIXEL(255,0,0)
+#define CLR_SP     PIXEL(0,0,100)
+
+static byte ChrDump(byte C)
+{
+  return((C>=32)&&(C<128)? C:'.');
+}
+ 
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers.                   **/
+/*************************************************************/
+byte DebugZ80(Z80 *R)
+{
+  char S[1024];
+  word A,Addr,ABuf[20];
+  int J,I,K,X,Y,MemoryDump,DrawWindow,ExitNow;
+
+  /* If we don't have enough screen estate... */
+  if((VideoW<32*8)||(VideoH<23*8))
+  {
+    /* Show warning message */
+    CONMsg(
+      -1,-1,-1,-1,PIXEL(255,255,255),PIXEL(255,0,0),
+      "Error","Screen is\0too small!\0\0"
+    );
+    /* Continue emulation */
+    R->Trace=0;
+    return(1);
+  }
+
+  X    = ((VideoW>>3)-32)>>1;
+  Y    = ((VideoH>>3)-23)>>1;
+  Addr = R->PC.W;
+  A    = ~Addr;
+  K    = 0;
+  
+  for(DrawWindow=1,MemoryDump=ExitNow=0;!ExitNow&&VideoImg;)
+  {
+    if(DrawWindow)
+    {
+      CONWindow(X,Y,32,23,CLR_TEXT,CLR_BACK,"Z80 Debugger");
+
+      sprintf(S,"PC %04X",R->PC.W);
+      CONSetColor(CLR_BACK,CLR_PC);
+      CONPrint(X+24,Y+18,S);
+      sprintf(S,"SP %04X",R->SP.W);
+      CONSetColor(CLR_BACK,CLR_SP);
+      CONPrint(X+24,Y+19,S);
+
+      CONSetColor(CLR_TEXT,CLR_BACK);
+      sprintf(S,
+        " %c%c%c%c%c%c\n\n"
+        "AF %04X\nBC %04X\nDE %04X\nHL %04X\nIX %04X\nIY %04X\n\n"
+        "AF'%04X\nBC'%04X\nDE'%04X\nHL'%04X\n\n"
+        "IR %02X%02X",
+        R->AF.B.l&0x80? 'S':'.',R->AF.B.l&0x40? 'Z':'.',R->AF.B.l&0x10? 'H':'.',
+        R->AF.B.l&0x04? 'P':'.',R->AF.B.l&0x02? 'N':'.',R->AF.B.l&0x01? 'C':'.',
+        R->AF.W,R->BC.W,R->DE.W,R->HL.W,
+        R->IX.W,R->IY.W,
+        R->AF1.W,R->BC1.W,R->DE1.W,R->HL1.W,
+        R->I,R->R
+      );
+      CONPrint(X+24,Y+2,S);
+      sprintf(S,
+        "%s %s",
+        R->IFF&0x04? "IM2":R->IFF&0x02? "IM1":"IM0",
+        R->IFF&0x01? "EI":"DI"
+      );
+      CONPrint(X+25,Y+21,S);
+      DrawWindow=0;
+      A=~Addr;
+    }
+
+    /* If top address has changed... */
+    if(A!=Addr)
+    {
+      /* Clear display */
+      CONBox((X+1)<<3,(Y+2)<<3,23*8,20*8,CLR_BACK);
+
+      if(MemoryDump)
+      {
+        /* Draw memory dump */
+        for(J=0,A=Addr;J<20;J++,A+=4)
+        {
+          if(A==R->PC.W)      CONSetColor(CLR_BACK,CLR_PC);
+          else if(A==R->SP.W) CONSetColor(CLR_BACK,CLR_SP);
+          else                CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,"%04X%c",A,A==R->PC.W? CON_MORE:A==R->SP.W? CON_LESS:':');
+          CONPrint(X+1,Y+J+2,S);
+
+          CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,
+            "%02X %02X %02X %02X %c%c%c%c",
+            RdZ80(A),RdZ80(A+1),RdZ80(A+2),RdZ80(A+3),
+            ChrDump(RdZ80(A)),ChrDump(RdZ80(A+1)),
+            ChrDump(RdZ80(A+2)),ChrDump(RdZ80(A+3))
+          );
+          CONPrint(X+7,Y+J+2,S);
+        }
+      }
+      else
+      {
+        /* Draw listing */
+        for(J=0,A=Addr;J<20;J++)
+        {
+          if(A==R->PC.W)      CONSetColor(CLR_BACK,CLR_PC);
+          else if(A==R->SP.W) CONSetColor(CLR_BACK,CLR_SP);
+          else                CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,"%04X%c",A,A==R->PC.W? CON_MORE:A==R->SP.W? CON_LESS:':');
+          CONPrint(X+1,Y+J+2,S);
+
+          ABuf[J]=A;
+          A+=DAsm(S,A);
+
+          CONSetColor(CLR_TEXT,CLR_BACK);
+          CONPrintN(X+7,Y+J+2,S,23);
+        }
+      }
+
+      /* Display redrawn */
+      A=Addr;
+    }
+
+    /* Draw pointer */
+    CONChar(X+6,Y+K+2,CON_ARROW);
+
+    /* Show screen buffer */
+    ShowVideo();
+
+    /* Get key code */
+    I=WaitKey();
+
+    /* Clear pointer */
+    CONChar(X+6,Y+K+2,' ');
+
+    /* Get and process key code */
+    switch(I)
+    {
+      case 'H':
+        CONMsg(
+          -1,-1,-1,-1,
+          CLR_BACK,CLR_DIALOG,
+          "Debugger Help",
+          "ENTER - Execute next opcode\0"
+          "   UP - Previous opcode\0"
+          " DOWN - Next opcode\0"
+          " LEFT - Page up\0"
+          "RIGHT - Page down\0"
+          "    H - This help page\0"
+          "    G - Go to address\0"
+          "    D - Disassembler view\0"
+          "    M - Memory dump view\0"
+          "    S - Show stack\0"
+          "    J - Jump to cursor\0"
+          "    R - Run to cursor\0"
+          "    C - Continue execution\0"
+          "    Q - Quit emulator\0"
+        );
+        DrawWindow=1;
+        break;
+      case CON_UP:
+        if(K) --K;
+        else
+          if(MemoryDump) Addr-=4;
+          else for(--Addr;Addr+DAsm(S,Addr)>A;--Addr);
+        break;
+      case CON_DOWN:
+        if(K<19) ++K;
+        else
+          if(MemoryDump) Addr+=4;
+          else Addr+=DAsm(S,Addr);
+        break;
+      case CON_LEFT:
+        if(MemoryDump)
+          Addr-=4*20;
+        else
+        {
+          for(I=20,Addr=~A;(Addr>A)||((A^Addr)&~Addr&0x8000);++I)
+            for(J=0,Addr=A-I;J<20;++J) Addr+=DAsm(S,Addr);
+          Addr=A-I+1;
+        }
+        break; 
+      case CON_RIGHT:
+        if(MemoryDump)
+          Addr+=4*20;
+        else
+          for(J=0;J<20;++J) Addr+=DAsm(S,Addr);
+        break;
+      case CON_OK:
+        ExitNow=1;
+        break;
+      case 'Q':
+        return(0);
+      case CON_EXIT:
+      case 'C':
+        R->Trap=0xFFFF;
+        R->Trace=0;
+        ExitNow=1;
+        break;
+      case 'R':
+        R->Trap=ABuf[K];
+        R->Trace=0;
+        ExitNow=1;
+        break;
+      case 'M':
+        MemoryDump=1;
+        A=~Addr;
+        break;
+      case 'S':
+        MemoryDump=1;
+        Addr=R->SP.W;
+        K=0;
+        A=~Addr;
+        break;
+      case 'D':
+        MemoryDump=0;
+        A=~Addr;
+        break;        
+      case 'G':
+        if(CONInput(-1,-1,CLR_BACK,CLR_DIALOG,"Go to Address:",S,5|CON_HEX))
+        { Addr=strtol(S,0,16);K=0; }
+        DrawWindow=1;
+        break;
+      case 'J':
+        R->PC.W=ABuf[K];
+        A=~Addr;
+        break;
+    }
+  }
+
+  /* Continue emulation */
+  return(1);
+}
+
+#endif /* CONDEBUG */
+#endif /* DEBUG */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Debug.c b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Debug.c
new file mode 100755
index 0000000..9c843e9
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Debug.c
@@ -0,0 +1,436 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         Debug.c                         **/
+/**                                                         **/
+/** This file contains the built-in debugging routine for   **/
+/** the Z80 emulator which is called on each Z80 step when  **/
+/** Trap!=0.                                                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1995-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#ifdef DEBUG
+
+#include "Z80.h"
+
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+
+#ifdef FMSX
+#include "AY8910.h"
+extern AY8910 PSG;
+#endif
+
+static const char *Mnemonics[256] =
+{
+  "NOP","LD BC,#h","LD (BC),A","INC BC","INC B","DEC B","LD B,*h","RLCA",
+  "EX AF,AF'","ADD HL,BC","LD A,(BC)","DEC BC","INC C","DEC C","LD C,*h","RRCA",
+  "DJNZ @h","LD DE,#h","LD (DE),A","INC DE","INC D","DEC D","LD D,*h","RLA",
+  "JR @h","ADD HL,DE","LD A,(DE)","DEC DE","INC E","DEC E","LD E,*h","RRA",
+  "JR NZ,@h","LD HL,#h","LD (#h),HL","INC HL","INC H","DEC H","LD H,*h","DAA",
+  "JR Z,@h","ADD HL,HL","LD HL,(#h)","DEC HL","INC L","DEC L","LD L,*h","CPL",
+  "JR NC,@h","LD SP,#h","LD (#h),A","INC SP","INC (HL)","DEC (HL)","LD (HL),*h","SCF",
+  "JR C,@h","ADD HL,SP","LD A,(#h)","DEC SP","INC A","DEC A","LD A,*h","CCF",
+  "LD B,B","LD B,C","LD B,D","LD B,E","LD B,H","LD B,L","LD B,(HL)","LD B,A",
+  "LD C,B","LD C,C","LD C,D","LD C,E","LD C,H","LD C,L","LD C,(HL)","LD C,A",
+  "LD D,B","LD D,C","LD D,D","LD D,E","LD D,H","LD D,L","LD D,(HL)","LD D,A",
+  "LD E,B","LD E,C","LD E,D","LD E,E","LD E,H","LD E,L","LD E,(HL)","LD E,A",
+  "LD H,B","LD H,C","LD H,D","LD H,E","LD H,H","LD H,L","LD H,(HL)","LD H,A",
+  "LD L,B","LD L,C","LD L,D","LD L,E","LD L,H","LD L,L","LD L,(HL)","LD L,A",
+  "LD (HL),B","LD (HL),C","LD (HL),D","LD (HL),E","LD (HL),H","LD (HL),L","HALT","LD (HL),A",
+  "LD A,B","LD A,C","LD A,D","LD A,E","LD A,H","LD A,L","LD A,(HL)","LD A,A",
+  "ADD B","ADD C","ADD D","ADD E","ADD H","ADD L","ADD (HL)","ADD A",
+  "ADC B","ADC C","ADC D","ADC E","ADC H","ADC L","ADC (HL)","ADC A",
+  "SUB B","SUB C","SUB D","SUB E","SUB H","SUB L","SUB (HL)","SUB A",
+  "SBC B","SBC C","SBC D","SBC E","SBC H","SBC L","SBC (HL)","SBC A",
+  "AND B","AND C","AND D","AND E","AND H","AND L","AND (HL)","AND A",
+  "XOR B","XOR C","XOR D","XOR E","XOR H","XOR L","XOR (HL)","XOR A",
+  "OR B","OR C","OR D","OR E","OR H","OR L","OR (HL)","OR A",
+  "CP B","CP C","CP D","CP E","CP H","CP L","CP (HL)","CP A",
+  "RET NZ","POP BC","JP NZ,#h","JP #h","CALL NZ,#h","PUSH BC","ADD *h","RST 00h",
+  "RET Z","RET","JP Z,#h","PFX_CB","CALL Z,#h","CALL #h","ADC *h","RST 08h",
+  "RET NC","POP DE","JP NC,#h","OUTA (*h)","CALL NC,#h","PUSH DE","SUB *h","RST 10h",
+  "RET C","EXX","JP C,#h","INA (*h)","CALL C,#h","PFX_DD","SBC *h","RST 18h",
+  "RET PO","POP HL","JP PO,#h","EX HL,(SP)","CALL PO,#h","PUSH HL","AND *h","RST 20h",
+  "RET PE","LD PC,HL","JP PE,#h","EX DE,HL","CALL PE,#h","PFX_ED","XOR *h","RST 28h",
+  "RET P","POP AF","JP P,#h","DI","CALL P,#h","PUSH AF","OR *h","RST 30h",
+  "RET M","LD SP,HL","JP M,#h","EI","CALL M,#h","PFX_FD","CP *h","RST 38h"
+};
+
+static const char *MnemonicsCB[256] =
+{
+  "RLC B","RLC C","RLC D","RLC E","RLC H","RLC L","RLC (HL)","RLC A",
+  "RRC B","RRC C","RRC D","RRC E","RRC H","RRC L","RRC (HL)","RRC A",
+  "RL B","RL C","RL D","RL E","RL H","RL L","RL (HL)","RL A",
+  "RR B","RR C","RR D","RR E","RR H","RR L","RR (HL)","RR A",
+  "SLA B","SLA C","SLA D","SLA E","SLA H","SLA L","SLA (HL)","SLA A",
+  "SRA B","SRA C","SRA D","SRA E","SRA H","SRA L","SRA (HL)","SRA A",
+  "SLL B","SLL C","SLL D","SLL E","SLL H","SLL L","SLL (HL)","SLL A",
+  "SRL B","SRL C","SRL D","SRL E","SRL H","SRL L","SRL (HL)","SRL A",
+  "BIT 0,B","BIT 0,C","BIT 0,D","BIT 0,E","BIT 0,H","BIT 0,L","BIT 0,(HL)","BIT 0,A",
+  "BIT 1,B","BIT 1,C","BIT 1,D","BIT 1,E","BIT 1,H","BIT 1,L","BIT 1,(HL)","BIT 1,A",
+  "BIT 2,B","BIT 2,C","BIT 2,D","BIT 2,E","BIT 2,H","BIT 2,L","BIT 2,(HL)","BIT 2,A",
+  "BIT 3,B","BIT 3,C","BIT 3,D","BIT 3,E","BIT 3,H","BIT 3,L","BIT 3,(HL)","BIT 3,A",
+  "BIT 4,B","BIT 4,C","BIT 4,D","BIT 4,E","BIT 4,H","BIT 4,L","BIT 4,(HL)","BIT 4,A",
+  "BIT 5,B","BIT 5,C","BIT 5,D","BIT 5,E","BIT 5,H","BIT 5,L","BIT 5,(HL)","BIT 5,A",
+  "BIT 6,B","BIT 6,C","BIT 6,D","BIT 6,E","BIT 6,H","BIT 6,L","BIT 6,(HL)","BIT 6,A",
+  "BIT 7,B","BIT 7,C","BIT 7,D","BIT 7,E","BIT 7,H","BIT 7,L","BIT 7,(HL)","BIT 7,A",
+  "RES 0,B","RES 0,C","RES 0,D","RES 0,E","RES 0,H","RES 0,L","RES 0,(HL)","RES 0,A",
+  "RES 1,B","RES 1,C","RES 1,D","RES 1,E","RES 1,H","RES 1,L","RES 1,(HL)","RES 1,A",
+  "RES 2,B","RES 2,C","RES 2,D","RES 2,E","RES 2,H","RES 2,L","RES 2,(HL)","RES 2,A",
+  "RES 3,B","RES 3,C","RES 3,D","RES 3,E","RES 3,H","RES 3,L","RES 3,(HL)","RES 3,A",
+  "RES 4,B","RES 4,C","RES 4,D","RES 4,E","RES 4,H","RES 4,L","RES 4,(HL)","RES 4,A",
+  "RES 5,B","RES 5,C","RES 5,D","RES 5,E","RES 5,H","RES 5,L","RES 5,(HL)","RES 5,A",
+  "RES 6,B","RES 6,C","RES 6,D","RES 6,E","RES 6,H","RES 6,L","RES 6,(HL)","RES 6,A",
+  "RES 7,B","RES 7,C","RES 7,D","RES 7,E","RES 7,H","RES 7,L","RES 7,(HL)","RES 7,A",
+  "SET 0,B","SET 0,C","SET 0,D","SET 0,E","SET 0,H","SET 0,L","SET 0,(HL)","SET 0,A",
+  "SET 1,B","SET 1,C","SET 1,D","SET 1,E","SET 1,H","SET 1,L","SET 1,(HL)","SET 1,A",
+  "SET 2,B","SET 2,C","SET 2,D","SET 2,E","SET 2,H","SET 2,L","SET 2,(HL)","SET 2,A",
+  "SET 3,B","SET 3,C","SET 3,D","SET 3,E","SET 3,H","SET 3,L","SET 3,(HL)","SET 3,A",
+  "SET 4,B","SET 4,C","SET 4,D","SET 4,E","SET 4,H","SET 4,L","SET 4,(HL)","SET 4,A",
+  "SET 5,B","SET 5,C","SET 5,D","SET 5,E","SET 5,H","SET 5,L","SET 5,(HL)","SET 5,A",
+  "SET 6,B","SET 6,C","SET 6,D","SET 6,E","SET 6,H","SET 6,L","SET 6,(HL)","SET 6,A",
+  "SET 7,B","SET 7,C","SET 7,D","SET 7,E","SET 7,H","SET 7,L","SET 7,(HL)","SET 7,A"
+};
+
+static const char *MnemonicsED[256] =
+{
+  "DB EDh,00h","DB EDh,01h","DB EDh,02h","DB EDh,03h",
+  "DB EDh,04h","DB EDh,05h","DB EDh,06h","DB EDh,07h",
+  "DB EDh,08h","DB EDh,09h","DB EDh,0Ah","DB EDh,0Bh",
+  "DB EDh,0Ch","DB EDh,0Dh","DB EDh,0Eh","DB EDh,0Fh",
+  "DB EDh,10h","DB EDh,11h","DB EDh,12h","DB EDh,13h",
+  "DB EDh,14h","DB EDh,15h","DB EDh,16h","DB EDh,17h",
+  "DB EDh,18h","DB EDh,19h","DB EDh,1Ah","DB EDh,1Bh",
+  "DB EDh,1Ch","DB EDh,1Dh","DB EDh,1Eh","DB EDh,1Fh",
+  "DB EDh,20h","DB EDh,21h","DB EDh,22h","DB EDh,23h",
+  "DB EDh,24h","DB EDh,25h","DB EDh,26h","DB EDh,27h",
+  "DB EDh,28h","DB EDh,29h","DB EDh,2Ah","DB EDh,2Bh",
+  "DB EDh,2Ch","DB EDh,2Dh","DB EDh,2Eh","DB EDh,2Fh",
+  "DB EDh,30h","DB EDh,31h","DB EDh,32h","DB EDh,33h",
+  "DB EDh,34h","DB EDh,35h","DB EDh,36h","DB EDh,37h",
+  "DB EDh,38h","DB EDh,39h","DB EDh,3Ah","DB EDh,3Bh",
+  "DB EDh,3Ch","DB EDh,3Dh","DB EDh,3Eh","DB EDh,3Fh",
+  "IN B,(C)","OUT (C),B","SBC HL,BC","LD (#h),BC",
+  "NEG","RETN","IM 0","LD I,A",
+  "IN C,(C)","OUT (C),C","ADC HL,BC","LD BC,(#h)",
+  "DB EDh,4Ch","RETI","DB EDh,4Eh","LD R,A",
+  "IN D,(C)","OUT (C),D","SBC HL,DE","LD (#h),DE",
+  "DB EDh,54h","DB EDh,55h","IM 1","LD A,I",
+  "IN E,(C)","OUT (C),E","ADC HL,DE","LD DE,(#h)",
+  "DB EDh,5Ch","DB EDh,5Dh","IM 2","LD A,R",
+  "IN H,(C)","OUT (C),H","SBC HL,HL","LD (#h),HL",
+  "DB EDh,64h","DB EDh,65h","DB EDh,66h","RRD",
+  "IN L,(C)","OUT (C),L","ADC HL,HL","LD HL,(#h)",
+  "DB EDh,6Ch","DB EDh,6Dh","DB EDh,6Eh","RLD",
+  "IN F,(C)","DB EDh,71h","SBC HL,SP","LD (#h),SP",
+  "DB EDh,74h","DB EDh,75h","DB EDh,76h","DB EDh,77h",
+  "IN A,(C)","OUT (C),A","ADC HL,SP","LD SP,(#h)",
+  "DB EDh,7Ch","DB EDh,7Dh","DB EDh,7Eh","DB EDh,7Fh",
+  "DB EDh,80h","DB EDh,81h","DB EDh,82h","DB EDh,83h",
+  "DB EDh,84h","DB EDh,85h","DB EDh,86h","DB EDh,87h",
+  "DB EDh,88h","DB EDh,89h","DB EDh,8Ah","DB EDh,8Bh",
+  "DB EDh,8Ch","DB EDh,8Dh","DB EDh,8Eh","DB EDh,8Fh",
+  "DB EDh,90h","DB EDh,91h","DB EDh,92h","DB EDh,93h",
+  "DB EDh,94h","DB EDh,95h","DB EDh,96h","DB EDh,97h",
+  "DB EDh,98h","DB EDh,99h","DB EDh,9Ah","DB EDh,9Bh",
+  "DB EDh,9Ch","DB EDh,9Dh","DB EDh,9Eh","DB EDh,9Fh",
+  "LDI","CPI","INI","OUTI",
+  "DB EDh,A4h","DB EDh,A5h","DB EDh,A6h","DB EDh,A7h",
+  "LDD","CPD","IND","OUTD",
+  "DB EDh,ACh","DB EDh,ADh","DB EDh,AEh","DB EDh,AFh",
+  "LDIR","CPIR","INIR","OTIR",
+  "DB EDh,B4h","DB EDh,B5h","DB EDh,B6h","DB EDh,B7h",
+  "LDDR","CPDR","INDR","OTDR",
+  "DB EDh,BCh","DB EDh,BDh","DB EDh,BEh","DB EDh,BFh",
+  "DB EDh,C0h","DB EDh,C1h","DB EDh,C2h","DB EDh,C3h",
+  "DB EDh,C4h","DB EDh,C5h","DB EDh,C6h","DB EDh,C7h",
+  "DB EDh,C8h","DB EDh,C9h","DB EDh,CAh","DB EDh,CBh",
+  "DB EDh,CCh","DB EDh,CDh","DB EDh,CEh","DB EDh,CFh",
+  "DB EDh,D0h","DB EDh,D1h","DB EDh,D2h","DB EDh,D3h",
+  "DB EDh,D4h","DB EDh,D5h","DB EDh,D6h","DB EDh,D7h",
+  "DB EDh,D8h","DB EDh,D9h","DB EDh,DAh","DB EDh,DBh",
+  "DB EDh,DCh","DB EDh,DDh","DB EDh,DEh","DB EDh,DFh",
+  "DB EDh,E0h","DB EDh,E1h","DB EDh,E2h","DB EDh,E3h",
+  "DB EDh,E4h","DB EDh,E5h","DB EDh,E6h","DB EDh,E7h",
+  "DB EDh,E8h","DB EDh,E9h","DB EDh,EAh","DB EDh,EBh",
+  "DB EDh,ECh","DB EDh,EDh","DB EDh,EEh","DB EDh,EFh",
+  "DB EDh,F0h","DB EDh,F1h","DB EDh,F2h","DB EDh,F3h",
+  "DB EDh,F4h","DB EDh,F5h","DB EDh,F6h","DB EDh,F7h",
+  "DB EDh,F8h","DB EDh,F9h","DB EDh,FAh","DB EDh,FBh",
+  "DB EDh,FCh","DB EDh,FDh","DB EDh,FEh","DB EDh,FFh"
+};
+
+static const char *MnemonicsXX[256] =
+{
+  "NOP","LD BC,#h","LD (BC),A","INC BC","INC B","DEC B","LD B,*h","RLCA",
+  "EX AF,AF'","ADD I%,BC","LD A,(BC)","DEC BC","INC C","DEC C","LD C,*h","RRCA",
+  "DJNZ @h","LD DE,#h","LD (DE),A","INC DE","INC D","DEC D","LD D,*h","RLA",
+  "JR @h","ADD I%,DE","LD A,(DE)","DEC DE","INC E","DEC E","LD E,*h","RRA",
+  "JR NZ,@h","LD I%,#h","LD (#h),I%","INC I%","INC I%h","DEC I%h","LD I%h,*h","DAA",
+  "JR Z,@h","ADD I%,I%","LD I%,(#h)","DEC I%","INC I%l","DEC I%l","LD I%l,*h","CPL",
+  "JR NC,@h","LD SP,#h","LD (#h),A","INC SP","INC (I%+^h)","DEC (I%+^h)","LD (I%+^h),*h","SCF",
+  "JR C,@h","ADD I%,SP","LD A,(#h)","DEC SP","INC A","DEC A","LD A,*h","CCF",
+  "LD B,B","LD B,C","LD B,D","LD B,E","LD B,I%h","LD B,I%l","LD B,(I%+^h)","LD B,A",
+  "LD C,B","LD C,C","LD C,D","LD C,E","LD C,I%h","LD C,I%l","LD C,(I%+^h)","LD C,A",
+  "LD D,B","LD D,C","LD D,D","LD D,E","LD D,I%h","LD D,I%l","LD D,(I%+^h)","LD D,A",
+  "LD E,B","LD E,C","LD E,D","LD E,E","LD E,I%h","LD E,I%l","LD E,(I%+^h)","LD E,A",
+  "LD I%h,B","LD I%h,C","LD I%h,D","LD I%h,E","LD I%h,I%h","LD I%h,I%l","LD H,(I%+^h)","LD I%h,A",
+  "LD I%l,B","LD I%l,C","LD I%l,D","LD I%l,E","LD I%l,I%h","LD I%l,I%l","LD L,(I%+^h)","LD I%l,A",
+  "LD (I%+^h),B","LD (I%+^h),C","LD (I%+^h),D","LD (I%+^h),E","LD (I%+^h),H","LD (I%+^h),L","HALT","LD (I%+^h),A",
+  "LD A,B","LD A,C","LD A,D","LD A,E","LD A,I%h","LD A,I%l","LD A,(I%+^h)","LD A,A",
+  "ADD B","ADD C","ADD D","ADD E","ADD I%h","ADD I%l","ADD (I%+^h)","ADD A",
+  "ADC B","ADC C","ADC D","ADC E","ADC I%h","ADC I%l","ADC (I%+^h)","ADC,A",
+  "SUB B","SUB C","SUB D","SUB E","SUB I%h","SUB I%l","SUB (I%+^h)","SUB A",
+  "SBC B","SBC C","SBC D","SBC E","SBC I%h","SBC I%l","SBC (I%+^h)","SBC A",
+  "AND B","AND C","AND D","AND E","AND I%h","AND I%l","AND (I%+^h)","AND A",
+  "XOR B","XOR C","XOR D","XOR E","XOR I%h","XOR I%l","XOR (I%+^h)","XOR A",
+  "OR B","OR C","OR D","OR E","OR I%h","OR I%l","OR (I%+^h)","OR A",
+  "CP B","CP C","CP D","CP E","CP I%h","CP I%l","CP (I%+^h)","CP A",
+  "RET NZ","POP BC","JP NZ,#h","JP #h","CALL NZ,#h","PUSH BC","ADD *h","RST 00h",
+  "RET Z","RET","JP Z,#h","PFX_CB","CALL Z,#h","CALL #h","ADC *h","RST 08h",
+  "RET NC","POP DE","JP NC,#h","OUTA (*h)","CALL NC,#h","PUSH DE","SUB *h","RST 10h",
+  "RET C","EXX","JP C,#h","INA (*h)","CALL C,#h","PFX_DD","SBC *h","RST 18h",
+  "RET PO","POP I%","JP PO,#h","EX I%,(SP)","CALL PO,#h","PUSH I%","AND *h","RST 20h",
+  "RET PE","LD PC,I%","JP PE,#h","EX DE,I%","CALL PE,#h","PFX_ED","XOR *h","RST 28h",
+  "RET P","POP AF","JP P,#h","DI","CALL P,#h","PUSH AF","OR *h","RST 30h",
+  "RET M","LD SP,I%","JP M,#h","EI","CALL M,#h","PFX_FD","CP *h","RST 38h"
+};
+
+static const char *MnemonicsXCB[256] =
+{
+  "RLC B","RLC C","RLC D","RLC E","RLC H","RLC L","RLC (I%@h)","RLC A",
+  "RRC B","RRC C","RRC D","RRC E","RRC H","RRC L","RRC (I%@h)","RRC A",
+  "RL B","RL C","RL D","RL E","RL H","RL L","RL (I%@h)","RL A",
+  "RR B","RR C","RR D","RR E","RR H","RR L","RR (I%@h)","RR A",
+  "SLA B","SLA C","SLA D","SLA E","SLA H","SLA L","SLA (I%@h)","SLA A",
+  "SRA B","SRA C","SRA D","SRA E","SRA H","SRA L","SRA (I%@h)","SRA A",
+  "SLL B","SLL C","SLL D","SLL E","SLL H","SLL L","SLL (I%@h)","SLL A",
+  "SRL B","SRL C","SRL D","SRL E","SRL H","SRL L","SRL (I%@h)","SRL A",
+  "BIT 0,B","BIT 0,C","BIT 0,D","BIT 0,E","BIT 0,H","BIT 0,L","BIT 0,(I%@h)","BIT 0,A",
+  "BIT 1,B","BIT 1,C","BIT 1,D","BIT 1,E","BIT 1,H","BIT 1,L","BIT 1,(I%@h)","BIT 1,A",
+  "BIT 2,B","BIT 2,C","BIT 2,D","BIT 2,E","BIT 2,H","BIT 2,L","BIT 2,(I%@h)","BIT 2,A",
+  "BIT 3,B","BIT 3,C","BIT 3,D","BIT 3,E","BIT 3,H","BIT 3,L","BIT 3,(I%@h)","BIT 3,A",
+  "BIT 4,B","BIT 4,C","BIT 4,D","BIT 4,E","BIT 4,H","BIT 4,L","BIT 4,(I%@h)","BIT 4,A",
+  "BIT 5,B","BIT 5,C","BIT 5,D","BIT 5,E","BIT 5,H","BIT 5,L","BIT 5,(I%@h)","BIT 5,A",
+  "BIT 6,B","BIT 6,C","BIT 6,D","BIT 6,E","BIT 6,H","BIT 6,L","BIT 6,(I%@h)","BIT 6,A",
+  "BIT 7,B","BIT 7,C","BIT 7,D","BIT 7,E","BIT 7,H","BIT 7,L","BIT 7,(I%@h)","BIT 7,A",
+  "RES 0,B","RES 0,C","RES 0,D","RES 0,E","RES 0,H","RES 0,L","RES 0,(I%@h)","RES 0,A",
+  "RES 1,B","RES 1,C","RES 1,D","RES 1,E","RES 1,H","RES 1,L","RES 1,(I%@h)","RES 1,A",
+  "RES 2,B","RES 2,C","RES 2,D","RES 2,E","RES 2,H","RES 2,L","RES 2,(I%@h)","RES 2,A",
+  "RES 3,B","RES 3,C","RES 3,D","RES 3,E","RES 3,H","RES 3,L","RES 3,(I%@h)","RES 3,A",
+  "RES 4,B","RES 4,C","RES 4,D","RES 4,E","RES 4,H","RES 4,L","RES 4,(I%@h)","RES 4,A",
+  "RES 5,B","RES 5,C","RES 5,D","RES 5,E","RES 5,H","RES 5,L","RES 5,(I%@h)","RES 5,A",
+  "RES 6,B","RES 6,C","RES 6,D","RES 6,E","RES 6,H","RES 6,L","RES 6,(I%@h)","RES 6,A",
+  "RES 7,B","RES 7,C","RES 7,D","RES 7,E","RES 7,H","RES 7,L","RES 7,(I%@h)","RES 7,A",
+  "SET 0,B","SET 0,C","SET 0,D","SET 0,E","SET 0,H","SET 0,L","SET 0,(I%@h)","SET 0,A",
+  "SET 1,B","SET 1,C","SET 1,D","SET 1,E","SET 1,H","SET 1,L","SET 1,(I%@h)","SET 1,A",
+  "SET 2,B","SET 2,C","SET 2,D","SET 2,E","SET 2,H","SET 2,L","SET 2,(I%@h)","SET 2,A",
+  "SET 3,B","SET 3,C","SET 3,D","SET 3,E","SET 3,H","SET 3,L","SET 3,(I%@h)","SET 3,A",
+  "SET 4,B","SET 4,C","SET 4,D","SET 4,E","SET 4,H","SET 4,L","SET 4,(I%@h)","SET 4,A",
+  "SET 5,B","SET 5,C","SET 5,D","SET 5,E","SET 5,H","SET 5,L","SET 5,(I%@h)","SET 5,A",
+  "SET 6,B","SET 6,C","SET 6,D","SET 6,E","SET 6,H","SET 6,L","SET 6,(I%@h)","SET 6,A",
+  "SET 7,B","SET 7,C","SET 7,D","SET 7,E","SET 7,H","SET 7,L","SET 7,(I%@h)","SET 7,A"
+};
+
+/** DAsm() ***************************************************/
+/** DAsm() will disassemble the code at adress A and put    **/
+/** the output text into S. It will return the number of    **/
+/** bytes disassembled.                                     **/
+/*************************************************************/
+static int DAsm(char *S,word A)
+{
+  char R[128],H[10],C,*P;
+  const char *T;
+  byte J,Offset;
+  word B;
+
+  Offset=0;
+  B=A;
+  C='\0';
+  J=0;
+
+  switch(RdZ80(B))
+  {
+    case 0xCB: B++;T=MnemonicsCB[RdZ80(B++)];break;
+    case 0xED: B++;T=MnemonicsED[RdZ80(B++)];break;
+    case 0xDD: B++;C='X';
+               if(RdZ80(B)!=0xCB) T=MnemonicsXX[RdZ80(B++)];
+               else
+               { B++;Offset=RdZ80(B++);J=1;T=MnemonicsXCB[RdZ80(B++)]; }
+               break;
+    case 0xFD: B++;C='Y';
+               if(RdZ80(B)!=0xCB) T=MnemonicsXX[RdZ80(B++)];
+               else
+               { B++;Offset=RdZ80(B++);J=1;T=MnemonicsXCB[RdZ80(B++)]; }
+               break;
+    default:   T=Mnemonics[RdZ80(B++)];
+  }
+
+  if(P=strchr(T,'^'))
+  {
+    strncpy(R,T,P-T);R[P-T]='\0';
+    sprintf(H,"%02X",RdZ80(B++));
+    strcat(R,H);strcat(R,P+1);
+  }
+  else strcpy(R,T);
+  if(P=strchr(R,'%')) *P=C;
+
+  if(P=strchr(R,'*'))
+  {
+    strncpy(S,R,P-R);S[P-R]='\0';
+    sprintf(H,"%02X",RdZ80(B++));
+    strcat(S,H);strcat(S,P+1);
+  }
+  else
+    if(P=strchr(R,'@'))
+    {
+      strncpy(S,R,P-R);S[P-R]='\0';
+      if(!J) Offset=RdZ80(B++);
+      strcat(S,Offset&0x80? "-":"+");
+      J=Offset&0x80? 256-Offset:Offset;
+      sprintf(H,"%02X",J);
+      strcat(S,H);strcat(S,P+1);
+    }
+    else
+      if(P=strchr(R,'#'))
+      {
+        strncpy(S,R,P-R);S[P-R]='\0';
+        sprintf(H,"%04X",RdZ80(B)+256*RdZ80(B+1));
+        strcat(S,H);strcat(S,P+1);
+        B+=2;
+      }
+      else strcpy(S,R);
+
+  return(B-A);
+}
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers.                   **/
+/*************************************************************/
+byte DebugZ80(Z80 *R)
+{
+  static const char Flags[9] = "SZ.H.PNC";
+  char S[128],T[10];
+  byte J,I;
+
+  DAsm(S,R->PC.W);
+  for(J=0,I=R->AF.B.l;J<8;J++,I<<=1) T[J]=I&0x80? Flags[J]:'.';
+  T[8]='\0';
+
+  printf
+  (
+    "AF:%04X HL:%04X DE:%04X BC:%04X PC:%04X SP:%04X IX:%04X IY:%04X I:%02X\n",
+    R->AF.W,R->HL.W,R->DE.W,R->BC.W,R->PC.W,R->SP.W,R->IX.W,R->IY.W,R->I
+  ); 
+  printf
+  ( 
+    "AT PC: [%02X - %s]   AT SP: [%04X]   FLAGS: [%s]   %s: %s\n\n",
+    RdZ80(R->PC.W),S,RdZ80(R->SP.W)+RdZ80(R->SP.W+1)*256,T,
+    R->IFF&0x04? "IM2":R->IFF&0x02? "IM1":"IM0",
+    R->IFF&0x01? "EI":"DI"
+  );
+
+  while(1)
+  {
+    printf("\n[Command,'?']-> ");
+    fflush(stdout);fflush(stdin);
+
+    fgets(S,50,stdin);
+    for(J=0;S[J]>=' ';J++)
+      S[J]=toupper(S[J]);
+    S[J]='\0';
+
+    switch(S[0])
+    {
+      case 'H':
+      case '?':
+        puts("\n***** Built-in Z80 Debugger Commands *****");
+        puts("<CR>       : Break at next instruction");
+        puts("= <addr>   : Break at addr");
+        puts("+ <offset> : Break at PC + offset");
+        puts("c          : Continue without break");
+        puts("j <addr>   : Continue from addr");
+        puts("m <addr>   : Memory dump at addr");
+        puts("d <addr>   : Disassembly at addr");
+        puts("?,h        : Show this help text");
+        puts("q          : Exit Z80 emulation");
+        break;
+
+      case '\0': return(1);
+      case '=':  if(strlen(S)>=2)
+                 { sscanf(S+1,"%hX",&(R->Trap));R->Trace=0;return(1); }
+                 break;
+      case '+':  if(strlen(S)>=2)
+                 {
+                   sscanf(S+1,"%hX",&(R->Trap));
+                   R->Trap+=R->PC.W;R->Trace=0;
+                   return(1);
+                 }
+                 break;
+      case 'J':  if(strlen(S)>=2)
+                 { sscanf(S+1,"%hX",&(R->PC.W));R->Trace=0;return(1); }
+                 break;
+      case 'C':  R->Trap=0xFFFF;R->Trace=0;return(1); 
+      case 'Q':  return(0);
+
+      case 'M':
+        {
+          word Addr;
+
+          if(strlen(S)>1) sscanf(S+1,"%hX",&Addr); else Addr=R->PC.W;
+          puts("");
+          for(J=0;J<16;J++)
+          {
+            printf("%04X: ",Addr);
+            for(I=0;I<16;I++,Addr++)
+              printf("%02X ",RdZ80(Addr));
+            printf(" | ");Addr-=16;
+            for(I=0;I<16;I++,Addr++)
+              putchar(isprint(RdZ80(Addr))? RdZ80(Addr):'.');
+            puts("");
+          }
+        }
+        break;
+
+      case 'D':
+        {
+          word Addr;
+
+          if(strlen(S)>1) sscanf(S+1,"%hX",&Addr); else Addr=R->PC.W;
+          puts("");
+          for(J=0;J<16;J++)
+          {
+            printf("%04X: ",Addr);
+            Addr+=DAsm(S,Addr);
+            puts(S);
+          }
+        }
+        break;
+
+#ifdef FMSX
+      case 'S':
+        for(J=0;J<AY8910_CHANNELS;J++)
+        {
+          printf("Channel %d: Volume %d, Frequency %dHz",J,PSG.Volume[J],PSG.Freq[J]);
+          if(!(PSG.R[8+(J%3)]&0x10)) printf("\n");
+          else printf(", Envelope %d\n",PSG.R[8+(J%3)]&0x0F);
+        }
+        printf("Envelope period %dms\n",PSG.EPeriod);
+        break;
+#endif /* FMSX */
+    }
+  }
+
+  /* Continue emulation */
+  return(1);
+}
+
+#endif /* DEBUG */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Tables.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Tables.h
new file mode 100755
index 0000000..dbb299a
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Tables.h
@@ -0,0 +1,447 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Tables.h                       **/
+/**                                                         **/
+/** This file contains tables of used by Z80 emulation to   **/
+/** compute SIGN,ZERO, PARITY flags, and decimal correction **/
+/** There are also timing tables for Z80 opcodes. This file **/
+/** is included from Z80.c.                                 **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+static const byte Cycles[256] =
+{
+   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+   8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+   7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+   7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+   5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+   5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+   5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 
+};
+
+static const byte CyclesCB[256] =
+{
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 
+};
+
+static const byte CyclesED[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
+  12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
+  12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
+  12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXX[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
+   0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+  19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXXCB[256] =
+{
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
+};
+
+static const byte ZSTable[256] =
+{
+  Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
+};
+
+static const byte PZSTable[256] =
+{
+  Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
+};
+
+static const word DAATable[2048] =
+{
+  0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,
+  0x0808,0x090C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,
+  0x180C,0x1908,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,
+  0x282C,0x2928,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,
+  0x3828,0x392C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,
+  0x480C,0x4908,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,
+  0x5808,0x590C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,
+  0x6828,0x692C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,
+  0x782C,0x7928,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,
+  0x888C,0x8988,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,
+  0x9888,0x998C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6025,0x6121,0x6221,0x6325,0x6421,0x6525,0x6625,0x6721,
+  0x6829,0x692D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7021,0x7125,0x7225,0x7321,0x7425,0x7521,0x7621,0x7725,
+  0x782D,0x7929,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8081,0x8185,0x8285,0x8381,0x8485,0x8581,0x8681,0x8785,
+  0x888D,0x8989,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9085,0x9181,0x9281,0x9385,0x9481,0x9585,0x9685,0x9781,
+  0x9889,0x998D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA0A5,0xA1A1,0xA2A1,0xA3A5,0xA4A1,0xA5A5,0xA6A5,0xA7A1,
+  0xA8A9,0xA9AD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB0A1,0xB1A5,0xB2A5,0xB3A1,0xB4A5,0xB5A1,0xB6A1,0xB7A5,
+  0xB8AD,0xB9A9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC085,0xC181,0xC281,0xC385,0xC481,0xC585,0xC685,0xC781,
+  0xC889,0xC98D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD081,0xD185,0xD285,0xD381,0xD485,0xD581,0xD681,0xD785,
+  0xD88D,0xD989,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE0A1,0xE1A5,0xE2A5,0xE3A1,0xE4A5,0xE5A1,0xE6A1,0xE7A5,
+  0xE8AD,0xE9A9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF0A5,0xF1A1,0xF2A1,0xF3A5,0xF4A1,0xF5A5,0xF6A5,0xF7A1,
+  0xF8A9,0xF9AD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0604,0x0700,0x0808,0x090C,0x0A0C,0x0B08,0x0C0C,0x0D08,
+  0x0E08,0x0F0C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1600,0x1704,0x180C,0x1908,0x1A08,0x1B0C,0x1C08,0x1D0C,
+  0x1E0C,0x1F08,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2620,0x2724,0x282C,0x2928,0x2A28,0x2B2C,0x2C28,0x2D2C,
+  0x2E2C,0x2F28,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3624,0x3720,0x3828,0x392C,0x3A2C,0x3B28,0x3C2C,0x3D28,
+  0x3E28,0x3F2C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4600,0x4704,0x480C,0x4908,0x4A08,0x4B0C,0x4C08,0x4D0C,
+  0x4E0C,0x4F08,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5604,0x5700,0x5808,0x590C,0x5A0C,0x5B08,0x5C0C,0x5D08,
+  0x5E08,0x5F0C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6624,0x6720,0x6828,0x692C,0x6A2C,0x6B28,0x6C2C,0x6D28,
+  0x6E28,0x6F2C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7620,0x7724,0x782C,0x7928,0x7A28,0x7B2C,0x7C28,0x7D2C,
+  0x7E2C,0x7F28,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8680,0x8784,0x888C,0x8988,0x8A88,0x8B8C,0x8C88,0x8D8C,
+  0x8E8C,0x8F88,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9684,0x9780,0x9888,0x998C,0x9A8C,0x9B88,0x9C8C,0x9D88,
+  0x9E88,0x9F8C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6625,0x6721,0x6829,0x692D,0x6A2D,0x6B29,0x6C2D,0x6D29,
+  0x6E29,0x6F2D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7621,0x7725,0x782D,0x7929,0x7A29,0x7B2D,0x7C29,0x7D2D,
+  0x7E2D,0x7F29,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8681,0x8785,0x888D,0x8989,0x8A89,0x8B8D,0x8C89,0x8D8D,
+  0x8E8D,0x8F89,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9685,0x9781,0x9889,0x998D,0x9A8D,0x9B89,0x9C8D,0x9D89,
+  0x9E89,0x9F8D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA6A5,0xA7A1,0xA8A9,0xA9AD,0xAAAD,0xABA9,0xACAD,0xADA9,
+  0xAEA9,0xAFAD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB6A1,0xB7A5,0xB8AD,0xB9A9,0xBAA9,0xBBAD,0xBCA9,0xBDAD,
+  0xBEAD,0xBFA9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC685,0xC781,0xC889,0xC98D,0xCA8D,0xCB89,0xCC8D,0xCD89,
+  0xCE89,0xCF8D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD681,0xD785,0xD88D,0xD989,0xDA89,0xDB8D,0xDC89,0xDD8D,
+  0xDE8D,0xDF89,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE6A1,0xE7A5,0xE8AD,0xE9A9,0xEAA9,0xEBAD,0xECA9,0xEDAD,
+  0xEEAD,0xEFA9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF6A5,0xF7A1,0xF8A9,0xF9AD,0xFAAD,0xFBA9,0xFCAD,0xFDA9,
+  0xFEA9,0xFFAD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0046,0x0102,0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,
+  0x080A,0x090E,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x1002,0x1106,0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,
+  0x180E,0x190A,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x2022,0x2126,0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,
+  0x282E,0x292A,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x3026,0x3122,0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,
+  0x382A,0x392E,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x4002,0x4106,0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,
+  0x480E,0x490A,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x5006,0x5102,0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,
+  0x580A,0x590E,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x6026,0x6122,0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,
+  0x682A,0x692E,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x7022,0x7126,0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,
+  0x782E,0x792A,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x8082,0x8186,0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,
+  0x888E,0x898A,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x9086,0x9182,0x9282,0x9386,0x9482,0x9586,0x9686,0x9782,
+  0x988A,0x998E,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xA0A7,0xA1A3,0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,
+  0xA8AB,0xA9AF,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xB0A3,0xB1A7,0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,
+  0xB8AF,0xB9AB,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xC087,0xC183,0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,
+  0xC88B,0xC98F,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xD083,0xD187,0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,
+  0xD88F,0xD98B,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xE0A3,0xE1A7,0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,
+  0xE8AF,0xE9AB,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xF0A7,0xF1A3,0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,
+  0xF8AB,0xF9AF,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0x0047,0x0103,0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,
+  0x080B,0x090F,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x1003,0x1107,0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,
+  0x180F,0x190B,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x2023,0x2127,0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,
+  0x282F,0x292B,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x3027,0x3123,0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,
+  0x382B,0x392F,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xFABE,0xFBBA,0xFCBE,0xFDBA,0xFEBA,0xFFBE,0x0046,0x0102,
+  0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x0A1E,0x0B1A,0x0C1E,0x0D1A,0x0E1A,0x0F1E,0x1002,0x1106,
+  0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x1A1A,0x1B1E,0x1C1A,0x1D1E,0x1E1E,0x1F1A,0x2022,0x2126,
+  0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x2A3A,0x2B3E,0x2C3A,0x2D3E,0x2E3E,0x2F3A,0x3026,0x3122,
+  0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x3A3E,0x3B3A,0x3C3E,0x3D3A,0x3E3A,0x3F3E,0x4002,0x4106,
+  0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x4A1A,0x4B1E,0x4C1A,0x4D1E,0x4E1E,0x4F1A,0x5006,0x5102,
+  0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x5A1E,0x5B1A,0x5C1E,0x5D1A,0x5E1A,0x5F1E,0x6026,0x6122,
+  0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x6A3E,0x6B3A,0x6C3E,0x6D3A,0x6E3A,0x6F3E,0x7022,0x7126,
+  0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x7A3A,0x7B3E,0x7C3A,0x7D3E,0x7E3E,0x7F3A,0x8082,0x8186,
+  0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x8A9A,0x8B9E,0x8C9A,0x8D9E,0x8E9E,0x8F9A,0x9086,0x9182,
+  0x9282,0x9386,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0x9A9F,0x9B9B,0x9C9F,0x9D9B,0x9E9B,0x9F9F,0xA0A7,0xA1A3,
+  0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xAABF,0xABBB,0xACBF,0xADBB,0xAEBB,0xAFBF,0xB0A3,0xB1A7,
+  0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xBABB,0xBBBF,0xBCBB,0xBDBF,0xBEBF,0xBFBB,0xC087,0xC183,
+  0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xCA9F,0xCB9B,0xCC9F,0xCD9B,0xCE9B,0xCF9F,0xD083,0xD187,
+  0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xDA9B,0xDB9F,0xDC9B,0xDD9F,0xDE9F,0xDF9B,0xE0A3,0xE1A7,
+  0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xEABB,0xEBBF,0xECBB,0xEDBF,0xEEBF,0xEFBB,0xF0A7,0xF1A3,
+  0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0xFABF,0xFBBB,0xFCBF,0xFDBB,0xFEBB,0xFFBF,0x0047,0x0103,
+  0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x0A1F,0x0B1B,0x0C1F,0x0D1B,0x0E1B,0x0F1F,0x1003,0x1107,
+  0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x1A1B,0x1B1F,0x1C1B,0x1D1F,0x1E1F,0x1F1B,0x2023,0x2127,
+  0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x2A3B,0x2B3F,0x2C3B,0x2D3F,0x2E3F,0x2F3B,0x3027,0x3123,
+  0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F
+};
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.c b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.c
new file mode 100755
index 0000000..6ec53f1
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.c
@@ -0,0 +1,703 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.c                         **/
+/**                                                         **/
+/** This file contains implementation for Z80 CPU. Don't    **/
+/** forget to provide RdZ80(), WrZ80(), InZ80(), OutZ80(),  **/
+/** LoopZ80(), and PatchZ80() functions to accomodate the   **/
+/** emulated machine's architecture.                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#define GENESIS 1
+
+#include "Z80.h"
+#include "Tables.h"
+#include <stdio.h>
+
+/** INLINE ***************************************************/
+/** C99 standard has "inline", but older compilers used     **/
+/** __inline for the same purpose.                          **/
+/*************************************************************/
+#ifdef __C99__
+#define INLINE static inline
+#else
+#define INLINE static __inline
+#endif
+
+/** System-Dependent Stuff ***********************************/
+/** This is system-dependent code put here to speed things  **/
+/** up. It has to stay inlined to be fast.                  **/
+/*************************************************************/
+#ifdef COLEM
+#define RdZ80 RDZ80
+extern byte *ROMPage[];
+INLINE byte RdZ80(word A) { return(ROMPage[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef SPECCY
+#define RdZ80 RDZ80
+#define WrZ80 WRZ80
+extern byte *Page[],*ROM;
+INLINE byte RdZ80(word A)        { return(Page[A>>13][A&0x1FFF]); }
+INLINE void WrZ80(word A,byte V) { if(Page[A>>13]<ROM) Page[A>>13][A&0x1FFF]=V; }
+#endif
+
+#ifdef MG
+#define RdZ80 RDZ80
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef FMSX
+#define FAST_RDOP
+extern byte *RAM[];
+INLINE byte OpZ80(word A) { return(RAM[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef GENESIS
+#define FAST_RDOP
+extern byte *Z80_RAM[];
+INLINE byte OpZ80(word A) { return(Z80_RAM[A>>13][A&0x1FFF]); }
+#endif
+
+/** FAST_RDOP ************************************************/
+/** With this #define not present, RdZ80() should perform   **/
+/** the functions of OpZ80().                               **/
+/*************************************************************/
+#ifndef FAST_RDOP
+#define OpZ80(A) RdZ80(A)
+#endif
+
+#define S(Fl)        R->AF.B.l|=Fl
+#define R(Fl)        R->AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
+
+#define M_RLC(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+#define M_RRC(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+#define M_RL(Rg)       \
+  if(Rg&0x80)          \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+#define M_RR(Rg)       \
+  if(Rg&0x01)          \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+  
+#define M_SLA(Rg)      \
+  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+#define M_SRA(Rg)      \
+  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+
+#define M_SLL(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+#define M_SRL(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+
+#define M_BIT(Bit,Rg)  \
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
+
+#define M_SET(Bit,Rg) Rg|=1<<Bit
+#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
+
+#define M_POP(Rg)      \
+  R->Rg.B.l=OpZ80(R->SP.W++);R->Rg.B.h=OpZ80(R->SP.W++)
+#define M_PUSH(Rg)     \
+  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+
+#define M_CALL         \
+  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W++);         \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
+  R->PC.W=J.W; \
+  JumpZ80(J.W)
+
+#define M_JP  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W);R->PC.W=J.W;JumpZ80(J.W)
+#define M_JR  R->PC.W+=(offset)OpZ80(R->PC.W)+1;JumpZ80(R->PC.W)
+#define M_RET R->PC.B.l=OpZ80(R->SP.W++);R->PC.B.h=OpZ80(R->SP.W++);JumpZ80(R->PC.W)
+
+#define M_RST(Ad)      \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad;JumpZ80(Ad)
+
+#define M_LDWORD(Rg)   \
+  R->Rg.B.l=OpZ80(R->PC.W++);R->Rg.B.h=OpZ80(R->PC.W++)
+
+#define M_ADD(Rg)      \
+  J.W=R->AF.B.h+Rg;    \
+  R->AF.B.l=           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|                        \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  R->AF.B.h=J.B.l       
+
+#define M_SUB(Rg)      \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  R->AF.B.h=J.B.l
+
+#define M_ADC(Rg)      \
+  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|              \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_SBC(Rg)      \
+  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_CP(Rg)       \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+
+#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
+#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+
+#define M_IN(Rg)        \
+  Rg=InZ80(R->BC.W);  \
+  R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+
+#define M_INC(Rg)       \
+  Rg++;                 \
+  R->AF.B.l=            \
+    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+    (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
+
+#define M_DEC(Rg)       \
+  Rg--;                 \
+  R->AF.B.l=            \
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+    (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
+
+#define M_ADDW(Rg1,Rg2) \
+  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
+  R->AF.B.l=                                             \
+    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
+  R->Rg1.W=J.W
+
+#define M_ADCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+   
+#define M_SBCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    N_FLAG|                                                    \
+    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+
+enum Codes
+{
+  NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
+  EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
+  DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
+  JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
+  JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
+  JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
+  JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
+  JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
+  LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
+  LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
+  LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
+  LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
+  LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
+  LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
+  LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
+  LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
+  ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
+  ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
+  SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
+  SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
+  AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
+  XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
+  OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
+  CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
+  RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
+  RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
+  RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
+  RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
+  RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
+  RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
+  RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
+  RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
+};
+
+enum CodesCB
+{
+  RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
+  RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
+  RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
+  RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
+  SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
+  SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
+  SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
+  SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
+  BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
+  BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
+  BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
+  BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
+  BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
+  BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
+  BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
+  BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
+  RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
+  RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
+  RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
+  RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
+  RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
+  RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
+  RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
+  RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
+  SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
+  SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
+  SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
+  SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
+  SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
+  SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
+  SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
+  SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
+};
+  
+enum CodesED
+{
+  DB_00,DB_01,DB_02,DB_03,DB_04,DB_05,DB_06,DB_07,
+  DB_08,DB_09,DB_0A,DB_0B,DB_0C,DB_0D,DB_0E,DB_0F,
+  DB_10,DB_11,DB_12,DB_13,DB_14,DB_15,DB_16,DB_17,
+  DB_18,DB_19,DB_1A,DB_1B,DB_1C,DB_1D,DB_1E,DB_1F,
+  DB_20,DB_21,DB_22,DB_23,DB_24,DB_25,DB_26,DB_27,
+  DB_28,DB_29,DB_2A,DB_2B,DB_2C,DB_2D,DB_2E,DB_2F,
+  DB_30,DB_31,DB_32,DB_33,DB_34,DB_35,DB_36,DB_37,
+  DB_38,DB_39,DB_3A,DB_3B,DB_3C,DB_3D,DB_3E,DB_3F,
+  IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
+  IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,DB_4C,RETI,DB_,LD_R_A,
+  IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,DB_54,DB_55,IM_1,LD_A_I,
+  IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,DB_5C,DB_5D,IM_2,LD_A_R,
+  IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,DB_64,DB_65,DB_66,RRD,
+  IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,DB_6C,DB_6D,DB_6E,RLD,
+  IN_F_xC,DB_71,SBC_HL_SP,LD_xWORDe_SP,DB_74,DB_75,DB_76,DB_77,
+  IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,DB_7C,DB_7D,DB_7E,DB_7F,
+  DB_80,DB_81,DB_82,DB_83,DB_84,DB_85,DB_86,DB_87,
+  DB_88,DB_89,DB_8A,DB_8B,DB_8C,DB_8D,DB_8E,DB_8F,
+  DB_90,DB_91,DB_92,DB_93,DB_94,DB_95,DB_96,DB_97,
+  DB_98,DB_99,DB_9A,DB_9B,DB_9C,DB_9D,DB_9E,DB_9F,
+  LDI,CPI,INI,OUTI,DB_A4,DB_A5,DB_A6,DB_A7,
+  LDD,CPD,IND,OUTD,DB_AC,DB_AD,DB_AE,DB_AF,
+  LDIR,CPIR,INIR,OTIR,DB_B4,DB_B5,DB_B6,DB_B7,
+  LDDR,CPDR,INDR,OTDR,DB_BC,DB_BD,DB_BE,DB_BF,
+  DB_C0,DB_C1,DB_C2,DB_C3,DB_C4,DB_C5,DB_C6,DB_C7,
+  DB_C8,DB_C9,DB_CA,DB_CB,DB_CC,DB_CD,DB_CE,DB_CF,
+  DB_D0,DB_D1,DB_D2,DB_D3,DB_D4,DB_D5,DB_D6,DB_D7,
+  DB_D8,DB_D9,DB_DA,DB_DB,DB_DC,DB_DD,DB_DE,DB_DF,
+  DB_E0,DB_E1,DB_E2,DB_E3,DB_E4,DB_E5,DB_E6,DB_E7,
+  DB_E8,DB_E9,DB_EA,DB_EB,DB_EC,DB_ED,DB_EE,DB_EF,
+  DB_F0,DB_F1,DB_F2,DB_F3,DB_F4,DB_F5,DB_F6,DB_F7,
+  DB_F8,DB_F9,DB_FA,DB_FB,DB_FC,DB_FD,DB_FE,DB_FF
+};
+
+static void CodesCB(register Z80 *R)
+{
+  register byte I;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesCB[I];
+  switch(I)
+  {
+#include "CodesCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (   
+          "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IX    
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesFDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IY
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesED(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesED[I];
+  switch(I)
+  {
+#include "CodesED.h"
+    case PFX_ED:
+      R->PC.W--;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IX
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesDDCB(R);break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+static void CodesFD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IY
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesFDCB(R);break;
+    default:
+        printf
+        (
+          "Unrecognized instruction: FD %02X at PC=%04X\n",
+          OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the register struct  **/
+/** before starting execution with Z80(). It sets the       **/
+/** registers to their supposed initial values.             **/
+/*************************************************************/
+void ResetZ80(Z80 *R)
+{
+  R->PC.W     = 0x0000;
+  R->SP.W     = 0xF000;
+  R->AF.W     = 0x0000;
+  R->BC.W     = 0x0000;
+  R->DE.W     = 0x0000;
+  R->HL.W     = 0x0000;
+  R->AF1.W    = 0x0000;
+  R->BC1.W    = 0x0000;
+  R->DE1.W    = 0x0000;
+  R->HL1.W    = 0x0000;
+  R->IX.W     = 0x0000;
+  R->IY.W     = 0x0000;
+  R->I        = 0x00;
+  R->R        = 0x00;
+  R->IFF      = 0x00;
+  R->ICount   = R->IPeriod;
+  R->RunCycles =0;
+  R->IRequest = INT_NONE;
+  R->IBackup  = 0;
+
+  JumpZ80(R->PC.W);
+}
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int GetRunCyclesZ80(register Z80 *R)
+{
+  return(R->ICount - R->RunCycles);
+}
+int ExecZ80(register Z80 *R,register int RunCycles)
+{
+  register byte I;
+  register pair J;
+  R->RunCycles = R->ICount;
+
+  for(R->ICount=RunCycles;;)
+  {
+    while(R->ICount>0)
+    {
+#ifdef DEBUG
+      /* Turn tracing on when reached trap address */
+      if(R->PC.W==R->Trap) R->Trace=1;
+      /* Call single-step debugger, exit if requested */
+      if(R->Trace)
+        if(!DebugZ80(R)) return(R->ICount);
+#endif
+
+      /* Read opcode and count cycles */
+      I=OpZ80(R->PC.W++);
+      /* Count cycles */
+      R->ICount-=Cycles[I];
+
+      /* Interpret opcode */
+      switch(I)
+      {
+#include "Codes.h"
+        case PFX_CB: CodesCB(R);break;
+        case PFX_ED: CodesED(R);break;
+        case PFX_FD: CodesFD(R);break;
+        case PFX_DD: CodesDD(R);break;
+      }
+
+      /* Unless we have come here after EI, exit */
+      if(!(R->IFF&IFF_EI))
+      {
+        /* Interrupt CPU if needed */
+        if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
+      }
+      else
+      {
+        /* Done with AfterEI state */
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1;
+        /* Restore the ICount */
+        R->ICount+=R->IBackup-1;
+      }
+    }
+
+    return(R->ICount);
+  }
+}
+#endif /* EXECZ80 */
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(Z80 *R,word Vector)
+{
+  /* If HALTed, take CPU off HALT instruction */
+  if(R->IFF&IFF_HALT) { R->PC.W++;R->IFF&=~IFF_HALT; }
+
+  if((R->IFF&IFF_1)||(Vector==INT_NMI))
+  {
+    /* Save PC on stack */
+    M_PUSH(PC);
+
+    /* Automatically reset IRequest if needed */
+    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+
+    /* If it is NMI... */
+    if(Vector==INT_NMI)
+    {
+      /* Clear IFF1 */
+      R->IFF&=~(IFF_1|IFF_EI);
+      /* Jump to hardwired NMI vector */
+      R->PC.W=0x0066;
+      JumpZ80(0x0066);
+      /* Done */
+      return;
+    }
+
+    /* Further interrupts off */
+    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+
+    /* If in IM2 mode... */
+    if(R->IFF&IFF_IM2)
+    {
+      /* Make up the vector address */
+      Vector=(Vector&0xFF)|((word)(R->I)<<8);
+      /* Read the vector */
+      R->PC.B.l=RdZ80(Vector++);
+      R->PC.B.h=RdZ80(Vector);
+      JumpZ80(R->PC.W);
+      /* Done */
+      return;
+    }
+
+    /* If in IM1 mode, just jump to hardwired IRQ vector */
+    if(R->IFF&IFF_IM1) { R->PC.W=0x0038;JumpZ80(0x0038);return; }
+
+    /* If in IM0 mode... */
+
+    /* Jump to a vector */
+    switch(Vector)
+    {
+      case INT_RST00: R->PC.W=0x0000;JumpZ80(0x0000);break;
+      case INT_RST08: R->PC.W=0x0008;JumpZ80(0x0008);break;
+      case INT_RST10: R->PC.W=0x0010;JumpZ80(0x0010);break;
+      case INT_RST18: R->PC.W=0x0018;JumpZ80(0x0018);break;
+      case INT_RST20: R->PC.W=0x0020;JumpZ80(0x0020);break;
+      case INT_RST28: R->PC.W=0x0028;JumpZ80(0x0028);break;
+      case INT_RST30: R->PC.W=0x0030;JumpZ80(0x0030);break;
+      case INT_RST38: R->PC.W=0x0038;JumpZ80(0x0038);break;
+    }
+  }
+}
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  for(;;)
+  {
+#ifdef DEBUG
+    /* Turn tracing on when reached trap address */
+    if(R->PC.W==R->Trap) R->Trace=1;
+    /* Call single-step debugger, exit if requested */
+    if(R->Trace)
+      if(!DebugZ80(R)) return(R->PC.W);
+#endif
+
+    I=OpZ80(R->PC.W++);
+    R->ICount-=Cycles[I];
+
+    switch(I)
+    {
+#include "Codes.h"
+      case PFX_CB: CodesCB(R);break;
+      case PFX_ED: CodesED(R);break;
+      case PFX_FD: CodesFD(R);break;
+      case PFX_DD: CodesDD(R);break;
+    }
+ 
+    /* If cycle counter expired... */
+    if(R->ICount<=0)
+    {
+      /* If we have come after EI, get address from IRequest */
+      /* Otherwise, get it from the loop handler             */
+      if(R->IFF&IFF_EI)
+      {
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
+        R->ICount+=R->IBackup-1;       /* Restore the ICount      */
+
+        /* Call periodic handler or set pending IRQ */
+        if(R->ICount>0) J.W=R->IRequest;
+        else
+        {
+          J.W=LoopZ80(R);        /* Call periodic handler    */
+          R->ICount+=R->IPeriod; /* Reset the cycle counter  */
+          if(J.W==INT_NONE) J.W=R->IRequest;  /* Pending IRQ */
+        }
+      }
+      else
+      {
+        J.W=LoopZ80(R);          /* Call periodic handler    */
+        R->ICount+=R->IPeriod;   /* Reset the cycle counter  */
+        if(J.W==INT_NONE) J.W=R->IRequest;    /* Pending IRQ */
+      }
+
+      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
+    }
+  }
+
+  /* Execution stopped */
+  return(R->PC.W);
+}
+#endif /* !EXECZ80 */
diff --git a/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.h b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.h
new file mode 100755
index 0000000..96e1064
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/cpus/Z80/Z80.h
@@ -0,0 +1,192 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to emulation   **/
+/** of Z80 CPU.                                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef Z80_H
+#define Z80_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+                               /* Compilation options:       */
+/* #define DEBUG */            /* Compile debugging version  */
+#define LSB_FIRST              /* Compile for low-endian CPU */
+/* #define MSB_FIRST */        /* Compile for hi-endian CPU  */
+#define EXECZ80
+
+                               /* LoopZ80() may return:      */
+#define INT_RST00   0x00C7     /* RST 00h                    */
+#define INT_RST08   0x00CF     /* RST 08h                    */
+#define INT_RST10   0x00D7     /* RST 10h                    */
+#define INT_RST18   0x00DF     /* RST 18h                    */
+#define INT_RST20   0x00E7     /* RST 20h                    */
+#define INT_RST28   0x00EF     /* RST 28h                    */
+#define INT_RST30   0x00F7     /* RST 30h                    */
+#define INT_RST38   0x00FF     /* RST 38h                    */
+#define INT_IRQ     INT_RST38  /* Default IRQ opcode is FFh  */
+#define INT_NMI     0xFFFD     /* Non-maskable interrupt     */
+#define INT_NONE    0xFFFF     /* No interrupt required      */
+#define INT_QUIT    0xFFFE     /* Exit the emulation         */
+
+                               /* Bits in Z80 F register:    */
+#define S_FLAG      0x80       /* 1: Result negative         */
+#define Z_FLAG      0x40       /* 1: Result is zero          */
+#define H_FLAG      0x10       /* 1: Halfcarry/Halfborrow    */
+#define P_FLAG      0x04       /* 1: Result is even          */
+#define V_FLAG      0x04       /* 1: Overflow occured        */
+#define N_FLAG      0x02       /* 1: Subtraction occured     */
+#define C_FLAG      0x01       /* 1: Carry/Borrow occured    */
+
+                               /* Bits in IFF flip-flops:    */
+#define IFF_1       0x01       /* IFF1 flip-flop             */
+#define IFF_IM1     0x02       /* 1: IM1 mode                */
+#define IFF_IM2     0x04       /* 1: IM2 mode                */
+#define IFF_2       0x08       /* IFF2 flip-flop             */
+#define IFF_EI      0x20       /* 1: EI pending              */
+#define IFF_HALT    0x80       /* 1: CPU HALTed              */
+
+/** Simple Datatypes *****************************************/
+/** NOTICE: sizeof(byte)=1 and sizeof(word)=2               **/
+/*************************************************************/
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+#ifndef WORD_TYPE_DEFINED
+#define WORD_TYPE_DEFINED
+typedef unsigned short word;
+#endif
+typedef signed char offset;
+
+/** Structured Datatypes *************************************/
+/** NOTICE: #define LSB_FIRST for machines where least      **/
+/**         signifcant byte goes first.                     **/
+/*************************************************************/
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+
+typedef struct
+{
+  pair AF,BC,DE,HL,IX,IY,PC,SP;       /* Main registers      */
+  pair AF1,BC1,DE1,HL1;               /* Shadow registers    */
+  byte IFF,I;                         /* Interrupt registers */
+  byte R;                             /* Refresh register    */
+
+  int IPeriod,ICount; /* Set IPeriod to number of CPU cycles */
+  int RunCycles;      /* Number of cycle to run              */
+                      /* between calls to LoopZ80()          */
+  int IBackup;        /* Private, don't touch                */
+  word IRequest;      /* Set to address of pending IRQ       */
+  byte IAutoReset;    /* Set to 1 to autom. reset IRequest   */
+  byte TrapBadOps;    /* Set to 1 to warn of illegal opcodes */
+  word Trap;          /* Set Trap to address to trace from   */
+  byte Trace;         /* Set Trace=1 to start tracing        */
+  void *User;         /* Arbitrary user data (ID,RAM*,etc.)  */
+} Z80;
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the registers before **/
+/** starting execution with RunZ80(). It sets registers to  **/
+/** their initial values.                                   **/
+/*************************************************************/
+void ResetZ80(register Z80 *R);
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int ExecZ80(register Z80 *R,register int RunCycles);
+int GetRunCyclesZ80(register Z80 *R);
+#endif
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(register Z80 *R,register word Vector);
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(register Z80 *R);
+#endif
+
+/** RdZ80()/WrZ80() ******************************************/
+/** These functions are called when access to RAM occurs.   **/
+/** They allow to control memory access.                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void WrZ80(register word Addr,register byte Value);
+void WrZ80byM68k(register word Addr,register byte Value);
+byte RdZ80(register word Addr);
+
+/** InZ80()/OutZ80() *****************************************/
+/** Z80 emulation calls these functions to read/write from  **/
+/** I/O ports. There can be 65536 I/O ports, but only first **/
+/** 256 are usually used.                                   **/
+/************************************ TO BE WRITTEN BY USER **/
+void OutZ80(register word Port,register byte Value);
+byte InZ80(register word Port);
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/** For example, it can be called to emulate BIOS calls,    **/
+/** such as disk and tape access. Replace it with an empty  **/
+/** macro for no patching.                                  **/
+/************************************ TO BE WRITTEN BY USER **/
+void PatchZ80(register Z80 *R);
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers. Emulation exits   **/
+/** if DebugZ80() returns 0.                                **/
+/*************************************************************/
+#ifdef DEBUG
+byte DebugZ80(register Z80 *R);
+#endif
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts. This    **/
+/** function must return an address of the interrupt vector **/
+/** (0x0038, 0x0066, etc.) or INT_NONE for no interrupt.    **/
+/** Return INT_QUIT to exit the emulation loop.             **/
+/************************************ TO BE WRITTEN BY USER **/
+word LoopZ80(register Z80 *R);
+
+/** JumpZ80() ************************************************/
+/** Z80 emulation calls this function when it executes a    **/
+/** JP, JR, CALL, RST, or RET. You can use JumpZ80() to     **/
+/** trap these opcodes and switch memory layout.            **/
+/************************************ TO BE WRITTEN BY USER **/
+#ifndef JUMPZ80
+#define JumpZ80(PC)
+#else
+void JumpZ80(word PC);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* Z80_H */
diff --git a/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.c b/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.c
new file mode 100755
index 0000000..9fb1e5f
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.c
@@ -0,0 +1,242 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include "gwenesis_io.h"
+#include "../savestate/gwenesis_savestate.h"
+
+unsigned short button_state[3]= {0xff,0xff,0xff};
+
+/* Button mapping 
+    7 6 5 4 3 2 1 0
+Start A B C R L D U 
+*/
+static unsigned char gwenesis_io_pad_state[3] = {0x33,0x33,0x33};
+
+//#define GWENESIS_IO_VERSION 0x81 /* oversea NTSC model version 81 */
+#define GWENESIS_IO_VERSION 0xC1 /* oversea PAL model version C1 */
+/*
+$A10003	:	MODE 	VMOD 	DISK 	RSV 	VER3 	VER2 	VER1 	VER0
+MODE (R) 	0: Domestic Model
+  	        1: Overseas Model
+VMOD (R) 	0: NTSC CPU clock 7.67 MHz
+  	        1: PAL CPU clock 7.60 MHz
+RSV (R) 	Currently not used
+VER3-0 (R)	MEGA DRIVE version is indicated by $0-$F. The present hardware version is indicated by $0. 
+$A10003	: DATA 1 ( CTRL1 )
+$A10005	: DATA 2 ( CTRL2 )
+$A10007	: DATA 3 ( EXP )
+$A10009	: CTRL 1
+$A1000B	: CTRL 2
+$A1000D	: CTRL 3
+$A1000F	: TxDATA 1
+$A10011	: RxDATA 1
+$A10013	: S-CTRL 1
+$A10015	: TxDATA 2
+$A10017	: RxDATA 2
+$A10019	: S-CTRL 2
+$A1001B	: TxDATA 3
+$A1001D	: RxDATA 3
+$A1001F	: S-CTRL 3 
+
+DATA shows the status of each port. The I/O direction of each bit is set by CTRL and S-CTRL.
+DATA =	PD7 	PD6 	PD5 	PD4 	PD3 	PD2 	PD1 	PD0
+
+PD7 (RW)
+PD6 (RW) TH
+PD5 (RW) TR
+PD4 (RW) TL
+PD3 (RW) RIGHT
+PD2 (RW) LEFT
+PD1 (RW) DOWN
+PD0 (RW) UP 
+
+TH = 0
+PD7 0
+PD6 TH=0
+PD5 Start
+PD4 A
+PD3 0
+PD2 0
+PD1 DOWN
+PD0 UP    
+
+TH = 1
+PD7 0
+PD6 TH=1
+PD5 B
+PD4 C
+PD3 RIGHT
+PD2 LEFT
+PD1 DOWN
+PD0 UP   
+
+
+CTRL designates the I/O direction of each port and the INTERRUPT CONTROL of TH.
+CTRL = 	INT 	PC6 	PC5 	PC4 	PC3 	PC2 	PC1 	PC0
+
+INT (RW)	0: TH-INT PROHIBITED
+	1: TH-INT ALLOWED
+PC6 (RW)	0: PD6 INPUT MODE
+	1: OUTPUT MODE
+PC5 (RW)	0: PD5 INPUT MODE
+	1: OUTPUT MODE
+PC4 (RW)	0: PD4 INPUT MODE
+	1: OUTPUT MODE
+PC3 (RW)	0: PD3 INPUT MODE
+	1: OUTPUT MODE
+PC2 (RW)	0: PD2 INPUT MODE
+	1: OUTPUT MODE
+PC1 (RW)	0: PD1 INPUT MODE
+	1: OUTPUT MODE
+PC0 (RW)	0: PD0 INPUT MODE
+	1: OUTPUT MODE  
+
+S-CTRL is for the status, etc. of each port's mode change, baud rate and SERIAL.
+
+S-CTRL = BPS1 	BPS0 	SIN 	SOUT 	RINT 	RERR 	RRDY 	TFUL
+
+SIN (RW) 	0: TR-PARALLEL MODE
+	1: SERIAL IN
+SOUT (RW)	0: TL-PARALLEL MODE
+	1: SERIAL OUT
+RINT (RW)	0: Rxd READY INTERRUPT PROHIBITED
+	1: Rxd READY INTERRUPT ALLOWED
+RERR (R) 	0:
+	1: Rxd ERROR
+RRDY (R) 	0:
+	1: Rxd READY
+TFUL (R) 	0:
+	1: Txd FULL 
+*/
+
+unsigned char io_reg[16] = {GWENESIS_IO_VERSION, /* 0x1 Version */
+                             0x7f, 0x7f, 0x7f,   /* 0x3-5-7 JOYPAD DATA 1 2 & EXT */
+                             0x00, 0x00, 0x00,   /* 0x9-A-C JOYPAD CTRL 1 2 & EXT */
+                             0xff,    0,    0,   /* PORT 1 */
+                             0xff,    0,    0,   /* PORT 2 */
+                             0xff,    0,    0};  /* PORT 3 */
+
+void gwenesis_io_pad_release_button(int pad, int button)
+{
+    button_state[pad] |= (1 << button);
+}
+
+void gwenesis_io_pad_press_button(int pad, int button)
+{
+    button_state[pad] &= ~(1 << button);
+}
+
+static inline void gwenesis_io_pad_write(int pad, int value)
+{
+    unsigned char mask = io_reg[pad + 4];
+
+     gwenesis_io_pad_state[pad] &= ~mask;
+    gwenesis_io_pad_state[pad] |= value & mask;
+ 
+}
+
+static inline  unsigned char gwenesis_io_pad_read(int pad)
+{
+    unsigned char value;
+ 
+    /* get host button */
+    gwenesis_io_get_buttons();
+
+    value = gwenesis_io_pad_state[pad] & 0x40;
+    value |= 0x3f;
+
+    if (value & 0x40)
+    {
+        value &= (button_state[pad] & 0x3f);
+    }
+    else
+    {
+        value &= ((button_state[pad] & 3) | ((button_state[pad] >> 2) & 0x30));
+    }
+    return value;
+}
+
+void gwenesis_io_write_ctrl(unsigned int address, unsigned int value)
+{
+
+    address >>= 1;
+ 
+    // JOYPAD DATA
+    if (address >= 0x1 && address <= 0x3)
+    {
+
+        io_reg[address] = value;
+        gwenesis_io_pad_write(address - 1, value);
+        return;
+    }
+    // JOYPAD CTRL
+    else if (address >= 0x4 && address <= 0x6)
+    {
+        if (io_reg[address] != value)
+        {
+            io_reg[address] = value;
+            gwenesis_io_pad_write(address - 4, io_reg[address - 3]);
+        }
+        return;
+    }
+
+    return;
+}
+
+unsigned int gwenesis_io_read_ctrl(unsigned int address)
+{
+    address >>= 1;
+    if (address >= 0x1 && address < 0x4)
+    {
+        unsigned char mask = 0x80 | io_reg[address + 3];
+        unsigned char value;
+        value = io_reg[address] & mask;
+        value |= gwenesis_io_pad_read(address - 1) & ~mask;
+
+        return value;
+    }
+    else
+    {
+        return io_reg[address];
+    }
+}
+
+void gwenesis_io_set_reg(unsigned int reg, unsigned int value) {
+    io_reg[reg] = value;
+    return;
+}
+
+void gwenesis_io_save_state() {
+    SaveState* state;
+    state = saveGwenesisStateOpenForWrite("io");
+    saveGwenesisStateSetBuffer(state, "button_state", button_state, sizeof(button_state));
+    saveGwenesisStateSetBuffer(state, "gwenesis_io_pad_state", gwenesis_io_pad_state, sizeof(gwenesis_io_pad_state));
+    saveGwenesisStateSetBuffer(state, "io_reg", io_reg, sizeof(io_reg));
+}
+
+void gwenesis_io_load_state() {
+    SaveState* state = saveGwenesisStateOpenForRead("io");
+    saveGwenesisStateGetBuffer(state, "button_state", button_state, sizeof(button_state));
+    saveGwenesisStateGetBuffer(state, "gwenesis_io_pad_state", gwenesis_io_pad_state, sizeof(gwenesis_io_pad_state));
+    saveGwenesisStateGetBuffer(state, "io_reg", io_reg, sizeof(io_reg));
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.h b/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.h
new file mode 100755
index 0000000..a1a1b75
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/io/gwenesis_io.h
@@ -0,0 +1,36 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_io_H_
+#define _gwenesis_io_H_
+
+#pragma once
+
+void gwenesis_io_pad_press_button(int pad, int button);
+void gwenesis_io_pad_release_button(int pad, int button);
+
+void gwenesis_io_write_ctrl(unsigned int address, unsigned int value);
+unsigned int gwenesis_io_read_ctrl(unsigned int address);
+
+void gwenesis_io_set_reg(unsigned int reg, unsigned int value);
+void gwenesis_io_get_buttons();
+
+void gwenesis_io_save_state();
+void gwenesis_io_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.c b/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.c
new file mode 100755
index 0000000..014555b
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.c
@@ -0,0 +1,54 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "../cpus/M68K/m68k.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../vdp/gwenesis_vdp.h"
+#include "../sound/z80inst.h"
+
+#include "../savestate/gwenesis_savestate.h"
+
+#include <assert.h>
+
+void gwenesis_save_state() {
+  /* DO NOT CHANGE ORDER - NEEDS TO BE SAME AS IN LOAD */
+  gwenesis_m68k_save_state();
+  gwenesis_io_save_state();
+  gwenesis_bus_save_state();
+  gwenesis_vdp_gfx_save_state();
+  gwenesis_vdp_mem_save_state();
+
+}
+
+void gwenesis_load_state() {
+  /* DO NOT CHANGE ORDER - NEEDS TO BE SAME AS IN SAVE */
+  gwenesis_m68k_load_state();
+  gwenesis_io_load_state();
+  gwenesis_bus_load_state();
+  gwenesis_vdp_gfx_load_state();
+  gwenesis_vdp_mem_load_state();
+
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.h b/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.h
new file mode 100755
index 0000000..0709ec8
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/savestate/gwenesis_savestate.h
@@ -0,0 +1,45 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_savestate_H_
+#define _gwenesis_savestate_H_
+
+#pragma once
+
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+typedef struct SaveState SaveState;
+
+bool initLoadGwenesisState(unsigned char *srcBuffer);
+int saveGwenesisState(unsigned char *destBuffer, int save_size);
+int loadGwenesisState(unsigned char *srcBuffer);
+
+SaveState* saveGwenesisStateOpenForRead(const char* fileName);
+SaveState* saveGwenesisStateOpenForWrite(const char* fileName);
+
+int saveGwenesisStateGet(SaveState* state, const char* tagName);
+void saveGwenesisStateSet(SaveState* state, const char* tagName, int value);
+
+void saveGwenesisStateGetBuffer(SaveState* state, const char* tagName, void* buffer, int length);
+void saveGwenesisStateSetBuffer(SaveState* state, const char* tagName, void* buffer, int length);
+
+void gwenesis_save_state();
+void gwenesis_load_state();
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/fn_table.h b/MCUME_pico2/picogen/_gwenesis/sound/fn_table.h
new file mode 100755
index 0000000..e55fbb3
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/fn_table.h
@@ -0,0 +1,258 @@
+const unsigned int __in_flash() __aligned(4) fn_table[] = {
+ // freqbase: 6.000000
+  0, 12288, 24576, 36864, 49152, 61440, 73728, 86016, 98304, 110592, 122880, 135168, 147456, 159744, 172032, 184320 // 0x00000000
+, 196608, 208896, 221184, 233472, 245760, 258048, 270336, 282624, 294912, 307200, 319488, 331776, 344064, 356352, 368640, 380928 // 0x00000040
+, 393216, 405504, 417792, 430080, 442368, 454656, 466944, 479232, 491520, 503808, 516096, 528384, 540672, 552960, 565248, 577536 // 0x00000080
+, 589824, 602112, 614400, 626688, 638976, 651264, 663552, 675840, 688128, 700416, 712704, 724992, 737280, 749568, 761856, 774144 // 0x000000C0
+, 786432, 798720, 811008, 823296, 835584, 847872, 860160, 872448, 884736, 897024, 909312, 921600, 933888, 946176, 958464, 970752 // 0x00000100
+, 983040, 995328, 1007616, 1019904, 1032192, 1044480, 1056768, 1069056, 1081344, 1093632, 1105920, 1118208, 1130496, 1142784, 1155072, 1167360 // 0x00000140
+, 1179648, 1191936, 1204224, 1216512, 1228800, 1241088, 1253376, 1265664, 1277952, 1290240, 1302528, 1314816, 1327104, 1339392, 1351680, 1363968 // 0x00000180
+, 1376256, 1388544, 1400832, 1413120, 1425408, 1437696, 1449984, 1462272, 1474560, 1486848, 1499136, 1511424, 1523712, 1536000, 1548288, 1560576 // 0x000001C0
+, 1572864, 1585152, 1597440, 1609728, 1622016, 1634304, 1646592, 1658880, 1671168, 1683456, 1695744, 1708032, 1720320, 1732608, 1744896, 1757184 // 0x00000200
+, 1769472, 1781760, 1794048, 1806336, 1818624, 1830912, 1843200, 1855488, 1867776, 1880064, 1892352, 1904640, 1916928, 1929216, 1941504, 1953792 // 0x00000240
+, 1966080, 1978368, 1990656, 2002944, 2015232, 2027520, 2039808, 2052096, 2064384, 2076672, 2088960, 2101248, 2113536, 2125824, 2138112, 2150400 // 0x00000280
+, 2162688, 2174976, 2187264, 2199552, 2211840, 2224128, 2236416, 2248704, 2260992, 2273280, 2285568, 2297856, 2310144, 2322432, 2334720, 2347008 // 0x000002C0
+, 2359296, 2371584, 2383872, 2396160, 2408448, 2420736, 2433024, 2445312, 2457600, 2469888, 2482176, 2494464, 2506752, 2519040, 2531328, 2543616 // 0x00000300
+, 2555904, 2568192, 2580480, 2592768, 2605056, 2617344, 2629632, 2641920, 2654208, 2666496, 2678784, 2691072, 2703360, 2715648, 2727936, 2740224 // 0x00000340
+, 2752512, 2764800, 2777088, 2789376, 2801664, 2813952, 2826240, 2838528, 2850816, 2863104, 2875392, 2887680, 2899968, 2912256, 2924544, 2936832 // 0x00000380
+, 2949120, 2961408, 2973696, 2985984, 2998272, 3010560, 3022848, 3035136, 3047424, 3059712, 3072000, 3084288, 3096576, 3108864, 3121152, 3133440 // 0x000003C0
+, 3145728, 3158016, 3170304, 3182592, 3194880, 3207168, 3219456, 3231744, 3244032, 3256320, 3268608, 3280896, 3293184, 3305472, 3317760, 3330048 // 0x00000400
+, 3342336, 3354624, 3366912, 3379200, 3391488, 3403776, 3416064, 3428352, 3440640, 3452928, 3465216, 3477504, 3489792, 3502080, 3514368, 3526656 // 0x00000440
+, 3538944, 3551232, 3563520, 3575808, 3588096, 3600384, 3612672, 3624960, 3637248, 3649536, 3661824, 3674112, 3686400, 3698688, 3710976, 3723264 // 0x00000480
+, 3735552, 3747840, 3760128, 3772416, 3784704, 3796992, 3809280, 3821568, 3833856, 3846144, 3858432, 3870720, 3883008, 3895296, 3907584, 3919872 // 0x000004C0
+, 3932160, 3944448, 3956736, 3969024, 3981312, 3993600, 4005888, 4018176, 4030464, 4042752, 4055040, 4067328, 4079616, 4091904, 4104192, 4116480 // 0x00000500
+, 4128768, 4141056, 4153344, 4165632, 4177920, 4190208, 4202496, 4214784, 4227072, 4239360, 4251648, 4263936, 4276224, 4288512, 4300800, 4313088 // 0x00000540
+, 4325376, 4337664, 4349952, 4362240, 4374528, 4386816, 4399104, 4411392, 4423680, 4435968, 4448256, 4460544, 4472832, 4485120, 4497408, 4509696 // 0x00000580
+, 4521984, 4534272, 4546560, 4558848, 4571136, 4583424, 4595712, 4608000, 4620288, 4632576, 4644864, 4657152, 4669440, 4681728, 4694016, 4706304 // 0x000005C0
+, 4718592, 4730880, 4743168, 4755456, 4767744, 4780032, 4792320, 4804608, 4816896, 4829184, 4841472, 4853760, 4866048, 4878336, 4890624, 4902912 // 0x00000600
+, 4915200, 4927488, 4939776, 4952064, 4964352, 4976640, 4988928, 5001216, 5013504, 5025792, 5038080, 5050368, 5062656, 5074944, 5087232, 5099520 // 0x00000640
+, 5111808, 5124096, 5136384, 5148672, 5160960, 5173248, 5185536, 5197824, 5210112, 5222400, 5234688, 5246976, 5259264, 5271552, 5283840, 5296128 // 0x00000680
+, 5308416, 5320704, 5332992, 5345280, 5357568, 5369856, 5382144, 5394432, 5406720, 5419008, 5431296, 5443584, 5455872, 5468160, 5480448, 5492736 // 0x000006C0
+, 5505024, 5517312, 5529600, 5541888, 5554176, 5566464, 5578752, 5591040, 5603328, 5615616, 5627904, 5640192, 5652480, 5664768, 5677056, 5689344 // 0x00000700
+, 5701632, 5713920, 5726208, 5738496, 5750784, 5763072, 5775360, 5787648, 5799936, 5812224, 5824512, 5836800, 5849088, 5861376, 5873664, 5885952 // 0x00000740
+, 5898240, 5910528, 5922816, 5935104, 5947392, 5959680, 5971968, 5984256, 5996544, 6008832, 6021120, 6033408, 6045696, 6057984, 6070272, 6082560 // 0x00000780
+, 6094848, 6107136, 6119424, 6131712, 6144000, 6156288, 6168576, 6180864, 6193152, 6205440, 6217728, 6230016, 6242304, 6254592, 6266880, 6279168 // 0x000007C0
+, 6291456, 6303744, 6316032, 6328320, 6340608, 6352896, 6365184, 6377472, 6389760, 6402048, 6414336, 6426624, 6438912, 6451200, 6463488, 6475776 // 0x00000800
+, 6488064, 6500352, 6512640, 6524928, 6537216, 6549504, 6561792, 6574080, 6586368, 6598656, 6610944, 6623232, 6635520, 6647808, 6660096, 6672384 // 0x00000840
+, 6684672, 6696960, 6709248, 6721536, 6733824, 6746112, 6758400, 6770688, 6782976, 6795264, 6807552, 6819840, 6832128, 6844416, 6856704, 6868992 // 0x00000880
+, 6881280, 6893568, 6905856, 6918144, 6930432, 6942720, 6955008, 6967296, 6979584, 6991872, 7004160, 7016448, 7028736, 7041024, 7053312, 7065600 // 0x000008C0
+, 7077888, 7090176, 7102464, 7114752, 7127040, 7139328, 7151616, 7163904, 7176192, 7188480, 7200768, 7213056, 7225344, 7237632, 7249920, 7262208 // 0x00000900
+, 7274496, 7286784, 7299072, 7311360, 7323648, 7335936, 7348224, 7360512, 7372800, 7385088, 7397376, 7409664, 7421952, 7434240, 7446528, 7458816 // 0x00000940
+, 7471104, 7483392, 7495680, 7507968, 7520256, 7532544, 7544832, 7557120, 7569408, 7581696, 7593984, 7606272, 7618560, 7630848, 7643136, 7655424 // 0x00000980
+, 7667712, 7680000, 7692288, 7704576, 7716864, 7729152, 7741440, 7753728, 7766016, 7778304, 7790592, 7802880, 7815168, 7827456, 7839744, 7852032 // 0x000009C0
+, 7864320, 7876608, 7888896, 7901184, 7913472, 7925760, 7938048, 7950336, 7962624, 7974912, 7987200, 7999488, 8011776, 8024064, 8036352, 8048640 // 0x00000A00
+, 8060928, 8073216, 8085504, 8097792, 8110080, 8122368, 8134656, 8146944, 8159232, 8171520, 8183808, 8196096, 8208384, 8220672, 8232960, 8245248 // 0x00000A40
+, 8257536, 8269824, 8282112, 8294400, 8306688, 8318976, 8331264, 8343552, 8355840, 8368128, 8380416, 8392704, 8404992, 8417280, 8429568, 8441856 // 0x00000A80
+, 8454144, 8466432, 8478720, 8491008, 8503296, 8515584, 8527872, 8540160, 8552448, 8564736, 8577024, 8589312, 8601600, 8613888, 8626176, 8638464 // 0x00000AC0
+, 8650752, 8663040, 8675328, 8687616, 8699904, 8712192, 8724480, 8736768, 8749056, 8761344, 8773632, 8785920, 8798208, 8810496, 8822784, 8835072 // 0x00000B00
+, 8847360, 8859648, 8871936, 8884224, 8896512, 8908800, 8921088, 8933376, 8945664, 8957952, 8970240, 8982528, 8994816, 9007104, 9019392, 9031680 // 0x00000B40
+, 9043968, 9056256, 9068544, 9080832, 9093120, 9105408, 9117696, 9129984, 9142272, 9154560, 9166848, 9179136, 9191424, 9203712, 9216000, 9228288 // 0x00000B80
+, 9240576, 9252864, 9265152, 9277440, 9289728, 9302016, 9314304, 9326592, 9338880, 9351168, 9363456, 9375744, 9388032, 9400320, 9412608, 9424896 // 0x00000BC0
+, 9437184, 9449472, 9461760, 9474048, 9486336, 9498624, 9510912, 9523200, 9535488, 9547776, 9560064, 9572352, 9584640, 9596928, 9609216, 9621504 // 0x00000C00
+, 9633792, 9646080, 9658368, 9670656, 9682944, 9695232, 9707520, 9719808, 9732096, 9744384, 9756672, 9768960, 9781248, 9793536, 9805824, 9818112 // 0x00000C40
+, 9830400, 9842688, 9854976, 9867264, 9879552, 9891840, 9904128, 9916416, 9928704, 9940992, 9953280, 9965568, 9977856, 9990144, 10002432, 10014720 // 0x00000C80
+, 10027008, 10039296, 10051584, 10063872, 10076160, 10088448, 10100736, 10113024, 10125312, 10137600, 10149888, 10162176, 10174464, 10186752, 10199040, 10211328 // 0x00000CC0
+, 10223616, 10235904, 10248192, 10260480, 10272768, 10285056, 10297344, 10309632, 10321920, 10334208, 10346496, 10358784, 10371072, 10383360, 10395648, 10407936 // 0x00000D00
+, 10420224, 10432512, 10444800, 10457088, 10469376, 10481664, 10493952, 10506240, 10518528, 10530816, 10543104, 10555392, 10567680, 10579968, 10592256, 10604544 // 0x00000D40
+, 10616832, 10629120, 10641408, 10653696, 10665984, 10678272, 10690560, 10702848, 10715136, 10727424, 10739712, 10752000, 10764288, 10776576, 10788864, 10801152 // 0x00000D80
+, 10813440, 10825728, 10838016, 10850304, 10862592, 10874880, 10887168, 10899456, 10911744, 10924032, 10936320, 10948608, 10960896, 10973184, 10985472, 10997760 // 0x00000DC0
+, 11010048, 11022336, 11034624, 11046912, 11059200, 11071488, 11083776, 11096064, 11108352, 11120640, 11132928, 11145216, 11157504, 11169792, 11182080, 11194368 // 0x00000E00
+, 11206656, 11218944, 11231232, 11243520, 11255808, 11268096, 11280384, 11292672, 11304960, 11317248, 11329536, 11341824, 11354112, 11366400, 11378688, 11390976 // 0x00000E40
+, 11403264, 11415552, 11427840, 11440128, 11452416, 11464704, 11476992, 11489280, 11501568, 11513856, 11526144, 11538432, 11550720, 11563008, 11575296, 11587584 // 0x00000E80
+, 11599872, 11612160, 11624448, 11636736, 11649024, 11661312, 11673600, 11685888, 11698176, 11710464, 11722752, 11735040, 11747328, 11759616, 11771904, 11784192 // 0x00000EC0
+, 11796480, 11808768, 11821056, 11833344, 11845632, 11857920, 11870208, 11882496, 11894784, 11907072, 11919360, 11931648, 11943936, 11956224, 11968512, 11980800 // 0x00000F00
+, 11993088, 12005376, 12017664, 12029952, 12042240, 12054528, 12066816, 12079104, 12091392, 12103680, 12115968, 12128256, 12140544, 12152832, 12165120, 12177408 // 0x00000F40
+, 12189696, 12201984, 12214272, 12226560, 12238848, 12251136, 12263424, 12275712, 12288000, 12300288, 12312576, 12324864, 12337152, 12349440, 12361728, 12374016 // 0x00000F80
+, 12386304, 12398592, 12410880, 12423168, 12435456, 12447744, 12460032, 12472320, 12484608, 12496896, 12509184, 12521472, 12533760, 12546048, 12558336, 12570624 // 0x00000FC0
+, 12582912, 12595200, 12607488, 12619776, 12632064, 12644352, 12656640, 12668928, 12681216, 12693504, 12705792, 12718080, 12730368, 12742656, 12754944, 12767232 // 0x00001000
+, 12779520, 12791808, 12804096, 12816384, 12828672, 12840960, 12853248, 12865536, 12877824, 12890112, 12902400, 12914688, 12926976, 12939264, 12951552, 12963840 // 0x00001040
+, 12976128, 12988416, 13000704, 13012992, 13025280, 13037568, 13049856, 13062144, 13074432, 13086720, 13099008, 13111296, 13123584, 13135872, 13148160, 13160448 // 0x00001080
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diff --git a/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.c b/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.c
new file mode 100755
index 0000000..f49465f
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.c
@@ -0,0 +1,299 @@
+#pragma GCC optimize("Ofast")
+/*
+    SN76489 emulation
+    by Maxim in 2001 and 2002
+    converted from my original Delphi implementation
+
+    I'm a C newbie so I'm sure there are loads of stupid things
+    in here which I'll come back to some day and redo
+
+    Includes:
+    - Super-high quality tone channel "oversampling" by calculating fractional positions on transitions
+    - Noise output pattern reverse engineered from actual SMS output
+    - Volume levels taken from actual SMS output
+
+    07/08/04  Charles MacDonald
+    Modified for use with SMS Plus:
+    - Added support for multiple PSG chips.
+    - Added reset/config/update routines.
+    - Added context management routines.
+    - Removed SN76489_GetValues().
+    - Removed some unused variables.
+
+    07/08/04  bzhxx few simplication for gwenesis to fit on MCU
+*/
+
+#pragma GCC optimize("Ofast")
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <signal.h>
+#include <stdio.h>
+#include <limits.h>
+#include "../bus/gwenesis_bus.h"
+#include "../sound/gwenesis_sn76489.h"
+
+#include <pico.h>
+
+extern int audio_enabled;
+
+/* compiler dependence */
+#ifndef INLINE
+#define INLINE static __always_inline
+#endif
+#define NoiseInitialState   0x8000  /* Initial state of shift register */
+#define PSG_CUTOFF          0x6     /* Value below which PSG does not output */
+// #define PSG_MAX_VOLUME 2800
+// static const uint16 chanVolume[16] = {
+//   PSG_MAX_VOLUME,               /*  MAX  */
+//   PSG_MAX_VOLUME * 0.794328234, /* -2dB  */
+//   PSG_MAX_VOLUME * 0.630957344, /* -4dB  */
+//   PSG_MAX_VOLUME * 0.501187233, /* -6dB  */
+//   PSG_MAX_VOLUME * 0.398107170, /* -8dB  */
+//   PSG_MAX_VOLUME * 0.316227766, /* -10dB */
+//   PSG_MAX_VOLUME * 0.251188643, /* -12dB */
+//   PSG_MAX_VOLUME * 0.199526231, /* -14dB */
+//   PSG_MAX_VOLUME * 0.158489319, /* -16dB */
+//   PSG_MAX_VOLUME * 0.125892541, /* -18dB */
+//   PSG_MAX_VOLUME * 0.1,         /* -20dB */
+//   PSG_MAX_VOLUME * 0.079432823, /* -22dB */
+//   PSG_MAX_VOLUME * 0.063095734, /* -24dB */
+//   PSG_MAX_VOLUME * 0.050118723, /* -26dB */
+//   PSG_MAX_VOLUME * 0.039810717, /* -28dB */
+//   0                             /*  OFF  */
+// };
+
+#define PSG_MAX_VOLUME_MAX 3100
+#define PSG_MAX_VOLUME_2dB (int)(PSG_MAX_VOLUME_MAX*0.794328234)
+#define PSG_MAX_VOLUME_4dB (int)(PSG_MAX_VOLUME_MAX*0.630957344)
+
+static const int PSGVolumeValues[16] = {
+    PSG_MAX_VOLUME_MAX,PSG_MAX_VOLUME_2dB,PSG_MAX_VOLUME_4dB,
+    PSG_MAX_VOLUME_MAX / 2,PSG_MAX_VOLUME_2dB / 2,PSG_MAX_VOLUME_4dB / 2,
+    PSG_MAX_VOLUME_MAX / 4,PSG_MAX_VOLUME_2dB / 4,PSG_MAX_VOLUME_4dB / 4,
+    PSG_MAX_VOLUME_MAX / 8,PSG_MAX_VOLUME_2dB / 8,PSG_MAX_VOLUME_4dB / 8,
+    PSG_MAX_VOLUME_MAX / 16,PSG_MAX_VOLUME_2dB / 16,PSG_MAX_VOLUME_4dB / 16,
+    0
+};
+
+extern uint8_t snd_accurate;
+
+
+static SN76489_Context gwenesis_SN76489;
+
+void gwenesis_SN76489_Init(int PSGClockValue, int SamplingRate, int freq_divisor) {
+    gwenesis_SN76489.dClock = (float)PSGClockValue / 16 / SamplingRate * GWENESIS_AUDIO_SAMPLING_DIVISOR;
+    gwenesis_SN76489.divisor = freq_divisor;
+
+    gwenesis_SN76489_Reset();
+}
+
+void gwenesis_SN76489_Reset() {
+    int i;
+
+    for (i = 0; i <= 3; i++) {
+        /* Initialise PSG state */
+        gwenesis_SN76489.Registers[2 * i] = 1; /* tone freq=1 */
+        gwenesis_SN76489.Registers[2 * i + 1] = 0xf; /* vol=off */
+        gwenesis_SN76489.NoiseFreq = 0x10;
+
+        /* Set counters to 0 */
+        gwenesis_SN76489.ToneFreqVals[i] = 0;
+
+        /* Set flip-flops to 1 */
+        gwenesis_SN76489.ToneFreqPos[i] = 1;
+
+        /* Set intermediate positions to do-not-use value */
+        gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+    }
+
+    gwenesis_SN76489.LatchedRegister = 0;
+
+    /* Initialise noise generator */
+    gwenesis_SN76489.NoiseShiftRegister = NoiseInitialState;
+
+    /* Zero clock */
+    gwenesis_SN76489.Clock = 0;
+    sn76489_index = 0;
+    sn76489_clock = 0;
+}
+
+void gwenesis_SN76489_SetContext(uint8* data) {
+    memcpy(&gwenesis_SN76489, data, sizeof(SN76489_Context));
+}
+
+void gwenesis_SN76489_GetContext(uint8* data) {
+    memcpy(data, &gwenesis_SN76489, sizeof(SN76489_Context));
+}
+
+uint8* gwenesis_SN76489_GetContextPtr() {
+    return (uint8 *)&gwenesis_SN76489;
+}
+
+int gwenesis_SN76489_GetContextSize(void) {
+    return sizeof(SN76489_Context);
+}
+
+INLINE void gwenesis_SN76489_Update(INT16* buffer, int length) {
+    int i, j;
+
+#pragma gcc unroll
+    for (j = 0; j < length; j++) {
+#pragma gcc unroll(2)
+        for (i = 0; i <= 2; ++i)
+            if (gwenesis_SN76489.IntermediatePos[i] != LONG_MIN)
+                gwenesis_SN76489.Channels[i] = __mul_instruction(gwenesis_SN76489.IntermediatePos[i],
+                        PSGVolumeValues[gwenesis_SN76489.Registers[__fast_mul(i, 2) + 1]]
+                        ) / 65536;
+            else
+                gwenesis_SN76489.Channels[i] = __mul_instruction(gwenesis_SN76489.ToneFreqPos[i], PSGVolumeValues[gwenesis_SN76489.Registers[__fast_mul(i, 2) + 1]]);
+
+        gwenesis_SN76489.Channels[3] = (short)(__mul_instruction(PSGVolumeValues[gwenesis_SN76489.Registers[7]], (
+                                                   gwenesis_SN76489.NoiseShiftRegister & 0x1)));
+
+        gwenesis_SN76489.Channels[3] <<= 1; /* Double noise volume to make some people happy */
+
+        buffer[j] = (gwenesis_SN76489.Channels[0]);
+        buffer[j] += (gwenesis_SN76489.Channels[1]);
+        buffer[j] += (gwenesis_SN76489.Channels[2]);
+        buffer[j] += (gwenesis_SN76489.Channels[3]);
+
+        gwenesis_SN76489.Clock += gwenesis_SN76489.dClock;
+        gwenesis_SN76489.NumClocksForSample = (int)gwenesis_SN76489.Clock; /* truncates */
+        gwenesis_SN76489.Clock -= gwenesis_SN76489.NumClocksForSample; /* remove integer part */
+
+        /* Decrement tone channel counters */
+        for (i = 0; i <= 2; ++i)
+            gwenesis_SN76489.ToneFreqVals[i] -= gwenesis_SN76489.NumClocksForSample;
+
+        /* Noise channel: match to tone2 or decrement its counter */
+        if (gwenesis_SN76489.NoiseFreq == 0x80) gwenesis_SN76489.ToneFreqVals[3] = gwenesis_SN76489.ToneFreqVals[2];
+        else gwenesis_SN76489.ToneFreqVals[3] -= gwenesis_SN76489.NumClocksForSample;
+
+        /* Tone channels: */
+#pragma gcc unroll(4)
+        for (i = 0; i <= 2; ++i) {
+            if (gwenesis_SN76489.ToneFreqVals[i] <= 0) {
+                /* If it gets below 0... */
+                if (gwenesis_SN76489.Registers[__fast_mul(i, 2)] > PSG_CUTOFF) {
+                    /* Calculate how much of the sample is + and how much is - */
+                    /* Go to floating point and include the clock fraction for extreme accuracy :D */
+                    /* Store as long int, maybe it's faster? I'm not very good at this */
+                    gwenesis_SN76489.IntermediatePos[i] = (long)(
+                        (gwenesis_SN76489.NumClocksForSample - gwenesis_SN76489.Clock +
+                            __fast_mul(gwenesis_SN76489.ToneFreqVals[i], 2)
+                            )
+                            * gwenesis_SN76489.ToneFreqPos[i] / (__fast_mul(gwenesis_SN76489.NumClocksForSample + gwenesis_SN76489.Clock,65536)));
+                    gwenesis_SN76489.ToneFreqPos[i] = -gwenesis_SN76489.ToneFreqPos[i]; /* Flip the flip-flop */
+                }
+                else {
+                    gwenesis_SN76489.ToneFreqPos[i] = 1; /* stuck value */
+                    gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+                }
+                gwenesis_SN76489.ToneFreqVals[i] += gwenesis_SN76489.Registers[__fast_mul(i,2)] * (gwenesis_SN76489.NumClocksForSample / gwenesis_SN76489.Registers[__fast_mul(i, 2)] + 1);
+            }
+            else gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+        }
+
+        /* Noise channel */
+        if (gwenesis_SN76489.ToneFreqVals[3] <= 0) {
+            /* If it gets below 0... */
+            gwenesis_SN76489.ToneFreqPos[3] = -gwenesis_SN76489.ToneFreqPos[3]; /* Flip the flip-flop */
+            if (gwenesis_SN76489.NoiseFreq != 0x80) /* If not matching tone2, decrement counter */
+                gwenesis_SN76489.ToneFreqVals[3] += __mul_instruction(gwenesis_SN76489.NoiseFreq, (
+                    gwenesis_SN76489.NumClocksForSample / gwenesis_SN76489.NoiseFreq + 1));
+            if (gwenesis_SN76489.ToneFreqPos[3] == 1) {
+                /* Only once per cycle... */
+                int Feedback;
+                if (gwenesis_SN76489.Registers[6] & 0x4) {
+                    /* White noise */
+                    /* Calculate parity of fed-back bits for feedback */
+
+                    /* If two bits fed back, I can do Feedback=(nsr & fb) && (nsr & fb ^ fb) */
+                    /* since that's (one or more bits set) && (not all bits set) */
+                    Feedback = ((gwenesis_SN76489.NoiseShiftRegister & gwenesis_SN76489.WhiteNoiseFeedback) && (
+                                    (gwenesis_SN76489.NoiseShiftRegister & gwenesis_SN76489.WhiteNoiseFeedback) ^
+                                    gwenesis_SN76489.WhiteNoiseFeedback));
+                }
+                else /* Periodic noise */
+                    Feedback = gwenesis_SN76489.NoiseShiftRegister & 1;
+
+                gwenesis_SN76489.NoiseShiftRegister = (gwenesis_SN76489.NoiseShiftRegister >> 1) | (Feedback << 15);
+            }
+        }
+    }
+}
+
+/* SN76589 execution */
+extern int scan_line;
+extern bool sn76489_enabled;
+
+void YM2612Update(uint16_t *buffer, int length);
+
+void gwenesis_SN76489_run(int target) {
+    if (sn76489_clock >= target) return;
+
+    target /= GWENESIS_AUDIO_SAMPLING_DIVISOR;
+
+    int sn76489_prev_index = sn76489_index;
+    sn76489_index += (target - sn76489_clock) / gwenesis_SN76489.divisor;
+    if (sn76489_index > sn76489_prev_index) {
+        int16* buf = gwenesis_sn76489_buffer + sn76489_prev_index;
+        int len = sn76489_index - sn76489_prev_index;
+        if (sn76489_enabled) gwenesis_SN76489_Update(buf, len);
+        YM2612Update(buf, len);
+        sn76489_clock = __mul_instruction(sn76489_index, gwenesis_SN76489.divisor);
+    }
+    else {
+        sn76489_index = sn76489_prev_index;
+    }
+}
+
+void gwenesis_SN76489_Write(int data, int target) {
+    if (!audio_enabled)
+        return;
+
+    if (snd_accurate == 1)
+        gwenesis_SN76489_run(target);
+
+    if (data & 0x80) {
+        /* Latch/data byte  %1 cc t dddd */
+        gwenesis_SN76489.LatchedRegister = ((data >> 4) & 0x07);
+        gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] =
+                (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] &
+                 0x3f0) /* zero low 4 bits */
+                | (data & 0xf); /* and replace with data */
+    }
+    else {
+        /* Data byte        %0 - dddddd */
+        if (!(gwenesis_SN76489.LatchedRegister % 2) && (gwenesis_SN76489.LatchedRegister < 5))
+            /* Tone register */
+            gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] =
+                    (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] & 0x00f) /* zero high 6 bits */
+                    | ((data & 0x3f) << 4); /* and replace with data */
+        else
+            /* Other register */
+            gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] = data & 0x0f; /* Replace with data */
+    }
+    switch (gwenesis_SN76489.LatchedRegister) {
+        case 0:
+        case 2:
+        case 4: /* Tone channels */
+            if (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] == 0)
+                gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] = 1;
+        /* Zero frequency changed to 1 to avoid div/0 */
+            break;
+        case 6: /* Noise */
+            gwenesis_SN76489.NoiseShiftRegister = NoiseInitialState; /* reset shift register */
+            gwenesis_SN76489.NoiseFreq = 0x10 << (gwenesis_SN76489.Registers[6] & 0x3);
+        /* set noise signal generator frequency */
+            break;
+    }
+}
+
+void gwenesis_sn76489_save_state() {
+}
+
+void gwenesis_sn76489_load_state() {
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.h b/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.h
new file mode 100755
index 0000000..94c0dae
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/gwenesis_sn76489.h
@@ -0,0 +1,73 @@
+
+#ifndef _GWENESIS_SN76489_H_
+#define _GWENESIS_SN76489_H_
+
+/*
+    More testing is needed to find and confirm feedback patterns for
+    SN76489 variants and compatible chips.
+*/
+
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+
+typedef unsigned char uint8;
+typedef unsigned short int uint16;
+typedef unsigned int uint32;
+
+typedef signed char int8;
+typedef signed short int int16;
+typedef signed int int32;
+
+typedef unsigned char UINT8;
+typedef unsigned short int UINT16;
+typedef unsigned int UINT32;
+
+typedef signed char INT8;
+typedef signed short int INT16;
+typedef signed int INT32;
+typedef long signed int INT641;
+
+typedef struct
+{
+    /* Variables */
+    float Clock;
+    float dClock;
+    int NumClocksForSample;
+    int WhiteNoiseFeedback;
+    int divisor;
+
+    /* PSG registers: */
+    UINT16 Registers[8];        /* Tone, vol x4 */
+    int LatchedRegister;
+    UINT16 NoiseShiftRegister;
+    INT16 NoiseFreq;            /* Noise channel signal generator frequency */
+
+    /* Output calculation variables */
+    INT16 ToneFreqVals[4];      /* Frequency register values (counters) */
+    INT8 ToneFreqPos[4];        /* Frequency channel flip-flops */
+    INT16 Channels[4];          /* Value of each channel, before stereo is applied */
+    INT641 IntermediatePos[4];   /* intermediate values used at boundaries between + and - */
+
+} SN76489_Context;
+
+extern int16 gwenesis_sn76489_buffer[];
+extern int sn76489_index;
+extern int sn76489_clock;
+
+/* Function prototypes */
+void gwenesis_SN76489_Init( int PSGClockValue, int SamplingRate,int freq_divisor);
+void gwenesis_SN76489_Reset();
+void gwenesis_SN76489_start();
+void gwenesis_SN76489_SetContext(uint8 *data);
+void gwenesis_SN76489_GetContext(uint8 *data);
+uint8 *gwenesis_SN76489_GetContextPtr();
+int gwenesis_SN76489_GetContextSize(void);
+void gwenesis_SN76489_Write(int data, int target);
+void gwenesis_SN76489_run(int target);
+
+void gwenesis_sn76489_save_state();
+void gwenesis_sn76489_load_state();
+
+#endif /* _GWENESIS_SN76489_H_ */
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/lfo_pm_table.h b/MCUME_pico2/picogen/_gwenesis/sound/lfo_pm_table.h
new file mode 100755
index 0000000..8d97448
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/lfo_pm_table.h
@@ -0,0 +1,1025 @@
+const unsigned char __in_flash() __aligned(4) lfo_pm_table[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000000
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000010
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000020
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000030
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000040
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000050
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000060
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000070
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000080
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000090
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000C0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000D0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000E0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000000F0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000100
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000110
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000120
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000130
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000140
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000150
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x00000160
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x00000170
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000180
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000190
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001C0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001D0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000001E0
+, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x03, 0x04, 0x04, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00 // 0x000001F0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000200
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000210
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000220
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000230
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000240
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x00000250
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x00000260
+, 0x00, 0x00, 0x02, 0x03, 0x04, 0x04, 0x05, 0x06, 0x06, 0x05, 0x04, 0x04, 0x03, 0x02, 0x00, 0x00 // 0x00000270
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000280
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000290
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002C0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000002D0
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x000002E0
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+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001B10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001B20
+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001B30
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+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001CB0
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+, 0x00, 0x00, 0x0E, 0x15, 0x1C, 0x1C, 0x23, 0x2A, 0x2A, 0x23, 0x1C, 0x1C, 0x15, 0x0E, 0x00, 0x00 // 0x00001CE0
+, 0x00, 0x00, 0x1C, 0x2A, 0x39, 0x39, 0x47, 0x55, 0x55, 0x47, 0x39, 0x39, 0x2A, 0x1C, 0x00, 0x00 // 0x00001CF0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001D00
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001D10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001D20
+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001D30
+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0E, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001D40
+, 0x00, 0x00, 0x07, 0x0A, 0x0E, 0x0E, 0x11, 0x15, 0x15, 0x11, 0x0E, 0x0E, 0x0A, 0x07, 0x00, 0x00 // 0x00001D50
+, 0x00, 0x00, 0x0E, 0x15, 0x1D, 0x1D, 0x24, 0x2B, 0x2B, 0x24, 0x1D, 0x1D, 0x15, 0x0E, 0x00, 0x00 // 0x00001D60
+, 0x00, 0x00, 0x1D, 0x2B, 0x3A, 0x3A, 0x48, 0x57, 0x57, 0x48, 0x3A, 0x3A, 0x2B, 0x1D, 0x00, 0x00 // 0x00001D70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001D80
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001D90
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001DA0
+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001DB0
+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0E, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001DC0
+, 0x00, 0x00, 0x07, 0x0A, 0x0E, 0x0E, 0x11, 0x15, 0x15, 0x11, 0x0E, 0x0E, 0x0A, 0x07, 0x00, 0x00 // 0x00001DD0
+, 0x00, 0x00, 0x0E, 0x15, 0x1D, 0x1D, 0x24, 0x2B, 0x2B, 0x24, 0x1D, 0x1D, 0x15, 0x0E, 0x00, 0x00 // 0x00001DE0
+, 0x00, 0x00, 0x1D, 0x2B, 0x3B, 0x3B, 0x49, 0x58, 0x58, 0x49, 0x3B, 0x3B, 0x2B, 0x1D, 0x00, 0x00 // 0x00001DF0
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+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001E10
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+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001EA0
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+, 0x00, 0x00, 0x1F, 0x2E, 0x3E, 0x3E, 0x4D, 0x5D, 0x5D, 0x4D, 0x3E, 0x3E, 0x2E, 0x1F, 0x00, 0x00 // 0x00003EE0
+, 0x00, 0x00, 0x3E, 0x5D, 0x7D, 0x7D, 0x9C, 0xBB, 0xBB, 0x9C, 0x7D, 0x7D, 0x5D, 0x3E, 0x00, 0x00 // 0x00003EF0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00003F00
+, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00 // 0x00003F10
+, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00 // 0x00003F20
+, 0x00, 0x00, 0x07, 0x07, 0x0F, 0x0F, 0x16, 0x16, 0x16, 0x16, 0x0F, 0x0F, 0x07, 0x07, 0x00, 0x00 // 0x00003F30
+, 0x00, 0x00, 0x07, 0x0F, 0x0F, 0x0F, 0x16, 0x1F, 0x1F, 0x16, 0x0F, 0x0F, 0x0F, 0x07, 0x00, 0x00 // 0x00003F40
+, 0x00, 0x00, 0x0F, 0x16, 0x1F, 0x1F, 0x26, 0x2E, 0x2E, 0x26, 0x1F, 0x1F, 0x16, 0x0F, 0x00, 0x00 // 0x00003F50
+, 0x00, 0x00, 0x1F, 0x2E, 0x3F, 0x3F, 0x4E, 0x5E, 0x5E, 0x4E, 0x3F, 0x3F, 0x2E, 0x1F, 0x00, 0x00 // 0x00003F60
+, 0x00, 0x00, 0x3F, 0x5E, 0x7E, 0x7E, 0x9D, 0xBD, 0xBD, 0x9D, 0x7E, 0x7E, 0x5E, 0x3F, 0x00, 0x00 // 0x00003F70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00003F80
+, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00 // 0x00003F90
+, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00 // 0x00003FA0
+, 0x00, 0x00, 0x07, 0x07, 0x0F, 0x0F, 0x16, 0x16, 0x16, 0x16, 0x0F, 0x0F, 0x07, 0x07, 0x00, 0x00 // 0x00003FB0
+, 0x00, 0x00, 0x07, 0x0F, 0x0F, 0x0F, 0x16, 0x1F, 0x1F, 0x16, 0x0F, 0x0F, 0x0F, 0x07, 0x00, 0x00 // 0x00003FC0
+, 0x00, 0x00, 0x0F, 0x16, 0x1F, 0x1F, 0x26, 0x2E, 0x2E, 0x26, 0x1F, 0x1F, 0x16, 0x0F, 0x00, 0x00 // 0x00003FD0
+, 0x00, 0x00, 0x1F, 0x2E, 0x3F, 0x3F, 0x4E, 0x5E, 0x5E, 0x4E, 0x3F, 0x3F, 0x2E, 0x1F, 0x00, 0x00 // 0x00003FE0
+, 0x00, 0x00, 0x3F, 0x5E, 0x7F, 0x7F, 0x9E, 0xBE, 0xBE, 0x9E, 0x7F, 0x7F, 0x5E, 0x3F, 0x00, 0x00};
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/sin_tab.h b/MCUME_pico2/picogen/_gwenesis/sound/sin_tab.h
new file mode 100755
index 0000000..8c73012
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/sin_tab.h
@@ -0,0 +1,65 @@
+const unsigned int __in_flash() __aligned(4) sin_tab[] = {
+  4274, 3462, 3086, 2838, 2652, 2504, 2380, 2274, 2182, 2100, 2026, 1958, 1898, 1840, 1788, 1738 // 0x00000000
+, 1692, 1650, 1608, 1570, 1534, 1498, 1464, 1434, 1402, 1374, 1344, 1318, 1292, 1266, 1242, 1218 // 0x00000040
+, 1196, 1174, 1152, 1132, 1112, 1092, 1072, 1054, 1036, 1018, 1002, 984, 968, 952, 936, 922 // 0x00000080
+, 906, 892, 878, 864, 850, 836, 822, 810, 798, 784, 772, 760, 750, 738, 726, 716 // 0x000000C0
+, 704, 694, 682, 672, 662, 652, 642, 632, 622, 614, 604, 594, 586, 578, 568, 560 // 0x00000100
+, 552, 542, 534, 526, 518, 510, 502, 496, 488, 480, 472, 466, 458, 452, 444, 438 // 0x00000140
+, 430, 424, 418, 410, 404, 398, 392, 386, 380, 374, 368, 362, 356, 350, 344, 338 // 0x00000180
+, 334, 328, 322, 318, 312, 306, 302, 296, 292, 286, 282, 276, 272, 268, 262, 258 // 0x000001C0
+, 254, 250, 244, 240, 236, 232, 228, 224, 220, 216, 212, 208, 204, 200, 196, 192 // 0x00000200
+, 188, 184, 182, 178, 174, 170, 166, 164, 160, 156, 154, 150, 148, 144, 140, 138 // 0x00000240
+, 134, 132, 128, 126, 124, 120, 118, 114, 112, 110, 106, 104, 102, 98, 96, 94 // 0x00000280
+, 92, 90, 86, 84, 82, 80, 78, 76, 74, 72, 70, 68, 66, 64, 62, 60 // 0x000002C0
+, 58, 56, 54, 52, 50, 48, 46, 46, 44, 42, 40, 40, 38, 36, 34, 34 // 0x00000300
+, 32, 30, 30, 28, 26, 26, 24, 24, 22, 20, 20, 18, 18, 16, 16, 14 // 0x00000340
+, 14, 14, 12, 12, 10, 10, 10, 8, 8, 8, 6, 6, 6, 4, 4, 4 // 0x00000380
+, 4, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0 // 0x000003C0
+, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 4 // 0x00000400
+, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 14, 14 // 0x00000440
+, 14, 16, 16, 18, 18, 20, 20, 22, 24, 24, 26, 26, 28, 30, 30, 32 // 0x00000480
+, 34, 34, 36, 38, 40, 40, 42, 44, 46, 46, 48, 50, 52, 54, 56, 58 // 0x000004C0
+, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 90, 92 // 0x00000500
+, 94, 96, 98, 102, 104, 106, 110, 112, 114, 118, 120, 124, 126, 128, 132, 134 // 0x00000540
+, 138, 140, 144, 148, 150, 154, 156, 160, 164, 166, 170, 174, 178, 182, 184, 188 // 0x00000580
+, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 250, 254 // 0x000005C0
+, 258, 262, 268, 272, 276, 282, 286, 292, 296, 302, 306, 312, 318, 322, 328, 334 // 0x00000600
+, 338, 344, 350, 356, 362, 368, 374, 380, 386, 392, 398, 404, 410, 418, 424, 430 // 0x00000640
+, 438, 444, 452, 458, 466, 472, 480, 488, 496, 502, 510, 518, 526, 534, 542, 552 // 0x00000680
+, 560, 568, 578, 586, 594, 604, 614, 622, 632, 642, 652, 662, 672, 682, 694, 704 // 0x000006C0
+, 716, 726, 738, 750, 760, 772, 784, 798, 810, 822, 836, 850, 864, 878, 892, 906 // 0x00000700
+, 922, 936, 952, 968, 984, 1002, 1018, 1036, 1054, 1072, 1092, 1112, 1132, 1152, 1174, 1196 // 0x00000740
+, 1218, 1242, 1266, 1292, 1318, 1344, 1374, 1402, 1434, 1464, 1498, 1534, 1570, 1608, 1650, 1692 // 0x00000780
+, 1738, 1788, 1840, 1898, 1958, 2026, 2100, 2182, 2274, 2380, 2504, 2652, 2838, 3086, 3462, 4274 // 0x000007C0
+, 4275, 3463, 3087, 2839, 2653, 2505, 2381, 2275, 2183, 2101, 2027, 1959, 1899, 1841, 1789, 1739 // 0x00000800
+, 1693, 1651, 1609, 1571, 1535, 1499, 1465, 1435, 1403, 1375, 1345, 1319, 1293, 1267, 1243, 1219 // 0x00000840
+, 1197, 1175, 1153, 1133, 1113, 1093, 1073, 1055, 1037, 1019, 1003, 985, 969, 953, 937, 923 // 0x00000880
+, 907, 893, 879, 865, 851, 837, 823, 811, 799, 785, 773, 761, 751, 739, 727, 717 // 0x000008C0
+, 705, 695, 683, 673, 663, 653, 643, 633, 623, 615, 605, 595, 587, 579, 569, 561 // 0x00000900
+, 553, 543, 535, 527, 519, 511, 503, 497, 489, 481, 473, 467, 459, 453, 445, 439 // 0x00000940
+, 431, 425, 419, 411, 405, 399, 393, 387, 381, 375, 369, 363, 357, 351, 345, 339 // 0x00000980
+, 335, 329, 323, 319, 313, 307, 303, 297, 293, 287, 283, 277, 273, 269, 263, 259 // 0x000009C0
+, 255, 251, 245, 241, 237, 233, 229, 225, 221, 217, 213, 209, 205, 201, 197, 193 // 0x00000A00
+, 189, 185, 183, 179, 175, 171, 167, 165, 161, 157, 155, 151, 149, 145, 141, 139 // 0x00000A40
+, 135, 133, 129, 127, 125, 121, 119, 115, 113, 111, 107, 105, 103, 99, 97, 95 // 0x00000A80
+, 93, 91, 87, 85, 83, 81, 79, 77, 75, 73, 71, 69, 67, 65, 63, 61 // 0x00000AC0
+, 59, 57, 55, 53, 51, 49, 47, 47, 45, 43, 41, 41, 39, 37, 35, 35 // 0x00000B00
+, 33, 31, 31, 29, 27, 27, 25, 25, 23, 21, 21, 19, 19, 17, 17, 15 // 0x00000B40
+, 15, 15, 13, 13, 11, 11, 11, 9, 9, 9, 7, 7, 7, 5, 5, 5 // 0x00000B80
+, 5, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1 // 0x00000BC0
+, 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 5 // 0x00000C00
+, 5, 5, 5, 7, 7, 7, 9, 9, 9, 11, 11, 11, 13, 13, 15, 15 // 0x00000C40
+, 15, 17, 17, 19, 19, 21, 21, 23, 25, 25, 27, 27, 29, 31, 31, 33 // 0x00000C80
+, 35, 35, 37, 39, 41, 41, 43, 45, 47, 47, 49, 51, 53, 55, 57, 59 // 0x00000CC0
+, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 91, 93 // 0x00000D00
+, 95, 97, 99, 103, 105, 107, 111, 113, 115, 119, 121, 125, 127, 129, 133, 135 // 0x00000D40
+, 139, 141, 145, 149, 151, 155, 157, 161, 165, 167, 171, 175, 179, 183, 185, 189 // 0x00000D80
+, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 251, 255 // 0x00000DC0
+, 259, 263, 269, 273, 277, 283, 287, 293, 297, 303, 307, 313, 319, 323, 329, 335 // 0x00000E00
+, 339, 345, 351, 357, 363, 369, 375, 381, 387, 393, 399, 405, 411, 419, 425, 431 // 0x00000E40
+, 439, 445, 453, 459, 467, 473, 481, 489, 497, 503, 511, 519, 527, 535, 543, 553 // 0x00000E80
+, 561, 569, 579, 587, 595, 605, 615, 623, 633, 643, 653, 663, 673, 683, 695, 705 // 0x00000EC0
+, 717, 727, 739, 751, 761, 773, 785, 799, 811, 823, 837, 851, 865, 879, 893, 907 // 0x00000F00
+, 923, 937, 953, 969, 985, 1003, 1019, 1037, 1055, 1073, 1093, 1113, 1133, 1153, 1175, 1197 // 0x00000F40
+, 1219, 1243, 1267, 1293, 1319, 1345, 1375, 1403, 1435, 1465, 1499, 1535, 1571, 1609, 1651, 1693 // 0x00000F80
+, 1739, 1789, 1841, 1899, 1959, 2027, 2101, 2183, 2275, 2381, 2505, 2653, 2839, 3087, 3463, 4275};
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/tl_tab.h b/MCUME_pico2/picogen/_gwenesis/sound/tl_tab.h
new file mode 100755
index 0000000..391db36
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/tl_tab.h
@@ -0,0 +1,417 @@
+const signed int __in_flash() __aligned(4) tl_tab[] = {
+  8168, -8168, 8148, -8148, 8124, -8124, 8104, -8104, 8080, -8080, 8060, -8060, 8040, -8040, 8016, -8016 // 0x00000000
+, 7996, -7996, 7972, -7972, 7952, -7952, 7932, -7932, 7908, -7908, 7888, -7888, 7864, -7864, 7844, -7844 // 0x00000040
+, 7824, -7824, 7804, -7804, 7780, -7780, 7760, -7760, 7740, -7740, 7720, -7720, 7696, -7696, 7676, -7676 // 0x00000080
+, 7656, -7656, 7636, -7636, 7616, -7616, 7592, -7592, 7572, -7572, 7552, -7552, 7532, -7532, 7512, -7512 // 0x000000C0
+, 7492, -7492, 7472, -7472, 7452, -7452, 7432, -7432, 7412, -7412, 7392, -7392, 7372, -7372, 7352, -7352 // 0x00000100
+, 7332, -7332, 7312, -7312, 7292, -7292, 7272, -7272, 7252, -7252, 7232, -7232, 7212, -7212, 7192, -7192 // 0x00000140
+, 7176, -7176, 7156, -7156, 7136, -7136, 7116, -7116, 7096, -7096, 7076, -7076, 7060, -7060, 7040, -7040 // 0x00000180
+, 7020, -7020, 7000, -7000, 6984, -6984, 6964, -6964, 6944, -6944, 6928, -6928, 6908, -6908, 6888, -6888 // 0x000001C0
+, 6868, -6868, 6852, -6852, 6832, -6832, 6816, -6816, 6796, -6796, 6776, -6776, 6760, -6760, 6740, -6740 // 0x00000200
+, 6724, -6724, 6704, -6704, 6688, -6688, 6668, -6668, 6652, -6652, 6632, -6632, 6616, -6616, 6596, -6596 // 0x00000240
+, 6580, -6580, 6560, -6560, 6544, -6544, 6524, -6524, 6508, -6508, 6492, -6492, 6472, -6472, 6456, -6456 // 0x00000280
+, 6436, -6436, 6420, -6420, 6404, -6404, 6384, -6384, 6368, -6368, 6352, -6352, 6336, -6336, 6316, -6316 // 0x000002C0
+, 6300, -6300, 6284, -6284, 6264, -6264, 6248, -6248, 6232, -6232, 6216, -6216, 6200, -6200, 6180, -6180 // 0x00000300
+, 6164, -6164, 6148, -6148, 6132, -6132, 6116, -6116, 6100, -6100, 6080, -6080, 6064, -6064, 6048, -6048 // 0x00000340
+, 6032, -6032, 6016, -6016, 6000, -6000, 5984, -5984, 5968, -5968, 5952, -5952, 5936, -5936, 5920, -5920 // 0x00000380
+, 5904, -5904, 5888, -5888, 5872, -5872, 5856, -5856, 5840, -5840, 5824, -5824, 5808, -5808, 5792, -5792 // 0x000003C0
+, 5776, -5776, 5760, -5760, 5744, -5744, 5732, -5732, 5716, -5716, 5700, -5700, 5684, -5684, 5668, -5668 // 0x00000400
+, 5652, -5652, 5636, -5636, 5624, -5624, 5608, -5608, 5592, -5592, 5576, -5576, 5564, -5564, 5548, -5548 // 0x00000440
+, 5532, -5532, 5516, -5516, 5504, -5504, 5488, -5488, 5472, -5472, 5456, -5456, 5444, -5444, 5428, -5428 // 0x00000480
+, 5412, -5412, 5400, -5400, 5384, -5384, 5368, -5368, 5356, -5356, 5340, -5340, 5328, -5328, 5312, -5312 // 0x000004C0
+, 5296, -5296, 5284, -5284, 5268, -5268, 5256, -5256, 5240, -5240, 5228, -5228, 5212, -5212, 5200, -5200 // 0x00000500
+, 5184, -5184, 5168, -5168, 5156, -5156, 5144, -5144, 5128, -5128, 5116, -5116, 5100, -5100, 5088, -5088 // 0x00000540
+, 5072, -5072, 5060, -5060, 5044, -5044, 5032, -5032, 5020, -5020, 5004, -5004, 4992, -4992, 4976, -4976 // 0x00000580
+, 4964, -4964, 4952, -4952, 4936, -4936, 4924, -4924, 4912, -4912, 4896, -4896, 4884, -4884, 4872, -4872 // 0x000005C0
+, 4856, -4856, 4844, -4844, 4832, -4832, 4820, -4820, 4804, -4804, 4792, -4792, 4780, -4780, 4768, -4768 // 0x00000600
+, 4752, -4752, 4740, -4740, 4728, -4728, 4716, -4716, 4704, -4704, 4688, -4688, 4676, -4676, 4664, -4664 // 0x00000640
+, 4652, -4652, 4640, -4640, 4628, -4628, 4616, -4616, 4600, -4600, 4588, -4588, 4576, -4576, 4564, -4564 // 0x00000680
+, 4552, -4552, 4540, -4540, 4528, -4528, 4516, -4516, 4504, -4504, 4492, -4492, 4480, -4480, 4468, -4468 // 0x000006C0
+, 4456, -4456, 4444, -4444, 4432, -4432, 4420, -4420, 4408, -4408, 4396, -4396, 4384, -4384, 4372, -4372 // 0x00000700
+, 4360, -4360, 4348, -4348, 4336, -4336, 4324, -4324, 4312, -4312, 4300, -4300, 4288, -4288, 4276, -4276 // 0x00000740
+, 4264, -4264, 4256, -4256, 4244, -4244, 4232, -4232, 4220, -4220, 4208, -4208, 4196, -4196, 4184, -4184 // 0x00000780
+, 4176, -4176, 4164, -4164, 4152, -4152, 4140, -4140, 4128, -4128, 4120, -4120, 4108, -4108, 4096, -4096 // 0x000007C0
+, 4084, -4084, 4074, -4074, 4062, -4062, 4052, -4052, 4040, -4040, 4030, -4030, 4020, -4020, 4008, -4008 // 0x00000800
+, 3998, -3998, 3986, -3986, 3976, -3976, 3966, -3966, 3954, -3954, 3944, -3944, 3932, -3932, 3922, -3922 // 0x00000840
+, 3912, -3912, 3902, -3902, 3890, -3890, 3880, -3880, 3870, -3870, 3860, -3860, 3848, -3848, 3838, -3838 // 0x00000880
+, 3828, -3828, 3818, -3818, 3808, -3808, 3796, -3796, 3786, -3786, 3776, -3776, 3766, -3766, 3756, -3756 // 0x000008C0
+, 3746, -3746, 3736, -3736, 3726, -3726, 3716, -3716, 3706, -3706, 3696, -3696, 3686, -3686, 3676, -3676 // 0x00000900
+, 3666, -3666, 3656, -3656, 3646, -3646, 3636, -3636, 3626, -3626, 3616, -3616, 3606, -3606, 3596, -3596 // 0x00000940
+, 3588, -3588, 3578, -3578, 3568, -3568, 3558, -3558, 3548, -3548, 3538, -3538, 3530, -3530, 3520, -3520 // 0x00000980
+, 3510, -3510, 3500, -3500, 3492, -3492, 3482, -3482, 3472, -3472, 3464, -3464, 3454, -3454, 3444, -3444 // 0x000009C0
+, 3434, -3434, 3426, -3426, 3416, -3416, 3408, -3408, 3398, -3398, 3388, -3388, 3380, -3380, 3370, -3370 // 0x00000A00
+, 3362, -3362, 3352, -3352, 3344, -3344, 3334, -3334, 3326, -3326, 3316, -3316, 3308, -3308, 3298, -3298 // 0x00000A40
+, 3290, -3290, 3280, -3280, 3272, -3272, 3262, -3262, 3254, -3254, 3246, -3246, 3236, -3236, 3228, -3228 // 0x00000A80
+, 3218, -3218, 3210, -3210, 3202, -3202, 3192, -3192, 3184, -3184, 3176, -3176, 3168, -3168, 3158, -3158 // 0x00000AC0
+, 3150, -3150, 3142, -3142, 3132, -3132, 3124, -3124, 3116, -3116, 3108, -3108, 3100, -3100, 3090, -3090 // 0x00000B00
+, 3082, -3082, 3074, -3074, 3066, -3066, 3058, -3058, 3050, -3050, 3040, -3040, 3032, -3032, 3024, -3024 // 0x00000B40
+, 3016, -3016, 3008, -3008, 3000, -3000, 2992, -2992, 2984, -2984, 2976, -2976, 2968, -2968, 2960, -2960 // 0x00000B80
+, 2952, -2952, 2944, -2944, 2936, -2936, 2928, -2928, 2920, -2920, 2912, -2912, 2904, -2904, 2896, -2896 // 0x00000BC0
+, 2888, -2888, 2880, -2880, 2872, -2872, 2866, -2866, 2858, -2858, 2850, -2850, 2842, -2842, 2834, -2834 // 0x00000C00
+, 2826, -2826, 2818, -2818, 2812, -2812, 2804, -2804, 2796, -2796, 2788, -2788, 2782, -2782, 2774, -2774 // 0x00000C40
+, 2766, -2766, 2758, -2758, 2752, -2752, 2744, -2744, 2736, -2736, 2728, -2728, 2722, -2722, 2714, -2714 // 0x00000C80
+, 2706, -2706, 2700, -2700, 2692, -2692, 2684, -2684, 2678, -2678, 2670, -2670, 2664, -2664, 2656, -2656 // 0x00000CC0
+, 2648, -2648, 2642, -2642, 2634, -2634, 2628, -2628, 2620, -2620, 2614, -2614, 2606, -2606, 2600, -2600 // 0x00000D00
+, 2592, -2592, 2584, -2584, 2578, -2578, 2572, -2572, 2564, -2564, 2558, -2558, 2550, -2550, 2544, -2544 // 0x00000D40
+, 2536, -2536, 2530, -2530, 2522, -2522, 2516, -2516, 2510, -2510, 2502, -2502, 2496, -2496, 2488, -2488 // 0x00000D80
+, 2482, -2482, 2476, -2476, 2468, -2468, 2462, -2462, 2456, -2456, 2448, -2448, 2442, -2442, 2436, -2436 // 0x00000DC0
+, 2428, -2428, 2422, -2422, 2416, -2416, 2410, -2410, 2402, -2402, 2396, -2396, 2390, -2390, 2384, -2384 // 0x00000E00
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+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005CC0
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005D00
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005D40
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005D80
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005DC0
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005E00
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005E40
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005E80
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005EC0
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005F00
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005F40
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005F80
+, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2, 2, -2 // 0x00005FC0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006000
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006040
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006080
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000060C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006100
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006140
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006180
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000061C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006200
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006240
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006280
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000062C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006300
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006340
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006380
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000063C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006400
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006440
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006480
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000064C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006500
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006540
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006580
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000065C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006600
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006640
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006680
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000066C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006700
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006740
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006780
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1};
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/ym2612.c b/MCUME_pico2/picogen/_gwenesis/sound/ym2612.c
new file mode 100755
index 0000000..811f3e8
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/ym2612.c
@@ -0,0 +1,2427 @@
+#pragma GCC optimize("Ofast")
+#include "pico.h"
+/*
+**
+** software implementation of Yamaha FM sound generator (YM2612/YM3438)
+**
+** Original code (MAME fm.c)
+**
+** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
+** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
+**
+** Version 1.4 (final beta) 
+**
+** Additional code & fixes by Eke-Eke for Genesis Plus GX
+**
+** Huge thanks to Nemesis, most of those fixes came from his tests on Sega Genesis hardware
+** More informations at http://gendev.spritesmind.net/forum/viewtopic.php?t=386
+**
+**  TODO:
+**  - better documentation
+**  - BUSY flag emulation
+*/
+
+/*
+**  CHANGELOG:
+**
+** 2006~2011  Eke-Eke (Genesis Plus GX):
+**  - removed unused multichip support
+**  - added YM2612 Context external access functions
+**  - fixed LFO implementation:
+**      .added support for CH3 special mode: fixes various sound effects (birds in Warlock, bug sound in Aladdin...)
+**      .modified LFO behavior when switched off (AM/PM current level is held) and on (LFO step is reseted): fixes intro in Spider-Man & Venom : Separation Anxiety
+**      .improved LFO timing accuracy: now updated AFTER sample output, like EG/PG updates, and without any precision loss anymore.
+**  - improved internal timers emulation
+**  - adjusted lowest EG rates increment values
+**  - fixed Attack Rate not being updated in some specific cases (Batman & Robin intro)
+**  - fixed EG behavior when Attack Rate is maximal
+**  - fixed EG behavior when SL=0 (Mega Turrican tracks 03,09...) or/and Key ON occurs at minimal attenuation 
+**  - implemented EG output immediate changes on register writes
+**  - fixed YM2612 initial values (after the reset): fixes missing intro in B.O.B
+**  - implemented Detune overflow (Ariel, Comix Zone, Shaq Fu, Spiderman & many other games using GEMS sound engine)
+**  - implemented accurate CSM mode emulation
+**  - implemented accurate SSG-EG emulation (Asterix, Beavis&Butthead, Bubba'n Stix & many other games)
+**  - implemented accurate address/data ports behavior
+**  - added preliminar support for DAC precision
+**
+**
+** 03-08-2003 Jarek Burczynski:
+**  - fixed YM2608 initial values (after the reset)
+**  - fixed flag and irqmask handling (YM2608)
+**  - fixed BUFRDY flag handling (YM2608)
+**
+** 14-06-2003 Jarek Burczynski:
+**  - implemented all of the YM2608 status register flags
+**  - implemented support for external memory read/write via YM2608
+**  - implemented support for deltat memory limit register in YM2608 emulation
+**
+** 22-05-2003 Jarek Burczynski:
+**  - fixed LFO PM calculations (copy&paste bugfix)
+**
+** 08-05-2003 Jarek Burczynski:
+**  - fixed SSG support
+**
+** 22-04-2003 Jarek Burczynski:
+**  - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
+**
+** 15-04-2003 Jarek Burczynski:
+**  - added support for YM2608's register 0x110 - status mask
+**
+** 01-12-2002 Jarek Burczynski:
+**  - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
+**    The addressing patch used for early Neo-Geo games can be removed now.
+**
+** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
+**  - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
+**  - added emulation of YM2608 drums.
+**  - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
+**
+** 16-08-2002 Jarek Burczynski:
+**  - binary exact Envelope Generator (verified on real YM2203);
+**    identical to YM2151
+**  - corrected 'off by one' error in feedback calculations (when feedback is off)
+**  - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
+**
+** 18-12-2001 Jarek Burczynski:
+**  - added SSG-EG support (verified on real YM2203)
+**
+** 12-08-2001 Jarek Burczynski:
+**  - corrected sin_tab and tl_tab data (verified on real chip)
+**  - corrected feedback calculations (verified on real chip)
+**  - corrected phase generator calculations (verified on real chip)
+**  - corrected envelope generator calculations (verified on real chip)
+**  - corrected FM volume level (YM2610 and YM2610B).
+**  - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
+**    this was needed to calculate YM2610 FM channels output correctly.
+**    (Each FM channel is calculated as in other chips, but the output of the channel
+**    gets shifted right by one *before* sending to accumulator. That was impossible to do
+**    with previous implementation).
+**
+** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
+**  - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
+**
+** 11-06-2001 Jarek Burczynski:
+**  - corrected end of sample bug in ADPCMA_calc_cha().
+**    Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
+**
+** 08-12-98 hiro-shi:
+** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
+** move ROM limit check.(CALC_CH? -> 2610Write1/2)
+** test program (ADPCMB_TEST)
+** move ADPCM A/B end check.
+** ADPCMB repeat flag(no check)
+** change ADPCM volume rate (8->16) (32->48).
+**
+** 09-12-98 hiro-shi:
+** change ADPCM volume. (8->16, 48->64)
+** replace ym2610 ch0/3 (YM-2610B)
+** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
+** add ADPCM_SHIFT_MASK
+** change ADPCMA_DECODE_MIN/MAX.
+*/
+
+/************************************************************************/
+/*    comment of hiro-shi(Hiromitsu Shioya)                             */
+/*    YM2610(B) = OPN-B                                                 */
+/*    YM2610  : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch      */
+/*    YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch      */
+/************************************************************************/
+
+#pragma GCC optimize("Ofast")
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "ym2612.h"
+#include "../bus/gwenesis_bus.h"
+
+#if GENERATE_TABLES
+#include "ff.h"
+#endif
+
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t UINT8;
+typedef uint8_t uint8;
+typedef int32_t INT32;
+typedef int16_t INT16;
+typedef int8_t INT8;
+
+extern uint8_t snd_accurate;
+
+#define YM2612_DISABLE_LOGGING 1
+
+#if !YM2612_DISABLE_LOGGING
+#include <stdarg.h>
+void ym_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] ", frame_counter, scan_line, subs);
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define ym_log(...)
+#endif
+
+/* compiler dependence */
+#ifndef INLINE
+#define INLINE static __always_inline
+#endif
+
+/* globals */
+#define FREQ_SH     16    /* 16.16 fixed point (frequency calculations) */
+#define EG_SH       16    /* 16.16 fixed point (envelope generator timing) */
+#define LFO_SH      24    /*  8.24 fixed point (LFO calculations)       */
+#define TIMER_SH    16    /* 16.16 fixed point (timers calculations)    */
+
+#define FREQ_MASK    ((1<<FREQ_SH)-1)
+
+
+/* envelope generator */
+#define ENV_BITS    10
+#define ENV_LEN      (1<<ENV_BITS)
+#define ENV_STEP    (128.0/ENV_LEN)
+
+#define MAX_ATT_INDEX  (ENV_LEN-1) /* 1023 */
+#define MIN_ATT_INDEX  (0)      /* 0 */
+
+#define EG_ATT      4
+#define EG_DEC      3
+#define EG_SUS      2
+#define EG_REL      1
+#define EG_OFF      0
+
+/* operator unit */
+#define SIN_BITS    10
+#define SIN_LEN      (1<<SIN_BITS)
+#define SIN_MASK    (SIN_LEN-1)
+
+#define TL_RES_LEN    (256) /* 8 bits addressing (real chip) */
+
+#define TL_BITS    14 /* channel output */
+
+/*  TL_TAB_LEN is calculated as:
+*   13 - sinus amplitude bits     (Y axis)
+*   2  - sinus sign bit           (Y axis)
+*   TL_RES_LEN - sinus resolution (X axis)
+*/
+#define TL_TAB_LEN (13*2*TL_RES_LEN)
+#if GENERATE_TABLES
+static signed int tl_tab[TL_TAB_LEN];
+#else
+#include "tl_tab.h"
+#endif
+
+#define ENV_QUIET    (TL_TAB_LEN>>3)
+
+/* sin waveform table in 'decibel' scale */
+#if GENERATE_TABLES
+static unsigned int sin_tab[SIN_LEN];
+#else
+#include "sin_tab.h"
+#endif
+/* sustain level table (3dB per step) */
+/* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
+/* 1,    2,    4,    8,    16,   32,   64   (value)*/
+/* 0.75, 1.5,  3,    6,    12,   24,   48   (dB)*/
+
+/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
+/* attenuation value (10 bits) = (SL << 2) << 3 */
+#define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
+static const UINT32 sl_table[16] = {
+    SC(0),SC(1),SC(2),SC(3),SC(4),SC(5),SC(6),SC(7),
+    SC(8),SC(9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
+};
+#undef SC
+
+
+#define RATE_STEPS (8)
+static const UINT8 eg_inc[19 * RATE_STEPS] = {
+
+    /*cycle:0 1  2 3  4 5  6 7*/
+
+    /* 0 */ 0, 1, 0, 1, 0, 1, 0, 1, /* rates 00..11 0 (increment by 0 or 1) */
+    /* 1 */ 0, 1, 0, 1, 1, 1, 0, 1, /* rates 00..11 1 */
+    /* 2 */ 0, 1, 1, 1, 0, 1, 1, 1, /* rates 00..11 2 */
+    /* 3 */ 0, 1, 1, 1, 1, 1, 1, 1, /* rates 00..11 3 */
+
+    /* 4 */ 1, 1, 1, 1, 1, 1, 1, 1, /* rate 12 0 (increment by 1) */
+    /* 5 */ 1, 1, 1, 2, 1, 1, 1, 2, /* rate 12 1 */
+    /* 6 */ 1, 2, 1, 2, 1, 2, 1, 2, /* rate 12 2 */
+    /* 7 */ 1, 2, 2, 2, 1, 2, 2, 2, /* rate 12 3 */
+
+    /* 8 */ 2, 2, 2, 2, 2, 2, 2, 2, /* rate 13 0 (increment by 2) */
+    /* 9 */ 2, 2, 2, 4, 2, 2, 2, 4, /* rate 13 1 */
+    /*10 */ 2, 4, 2, 4, 2, 4, 2, 4, /* rate 13 2 */
+    /*11 */ 2, 4, 4, 4, 2, 4, 4, 4, /* rate 13 3 */
+
+    /*12 */ 4, 4, 4, 4, 4, 4, 4, 4, /* rate 14 0 (increment by 4) */
+    /*13 */ 4, 4, 4, 8, 4, 4, 4, 8, /* rate 14 1 */
+    /*14 */ 4, 8, 4, 8, 4, 8, 4, 8, /* rate 14 2 */
+    /*15 */ 4, 8, 8, 8, 4, 8, 8, 8, /* rate 14 3 */
+
+    /*16 */ 8, 8, 8, 8, 8, 8, 8, 8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
+    /*17 */ 16, 16, 16, 16, 16, 16, 16, 16, /* rates 15 2, 15 3 for attack */
+    /*18 */ 0, 0, 0, 0, 0, 0, 0, 0, /* infinity rates for attack and decay(s) */
+};
+
+
+#define O(a) (a*RATE_STEPS)
+
+/*note that there is no O(17) in this table - it's directly in the code */
+static const UINT8 eg_rate_select[32 + 64 + 32] = {
+    /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
+    /* 32 infinite time rates (same as Rate 0) */
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+
+    /* rates 00-11 */
+    /*
+    O( 0),O( 1),O( 2),O( 3),
+    O( 0),O( 1),O( 2),O( 3),
+    */
+    O(18),O(18),O(0),O(0),
+    O(0),O(0),O(2),O(2), /* Nemesis's tests */
+
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+
+    /* rate 12 */
+    O(4),O(5),O(6),O(7),
+
+    /* rate 13 */
+    O(8),O(9),O(10),O(11),
+
+    /* rate 14 */
+    O(12),O(13),O(14),O(15),
+
+    /* rate 15 */
+    O(16),O(16),O(16),O(16),
+
+    /* 32 dummy rates (same as 15 3) */
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
+
+};
+#undef O
+
+/*rate  0,    1,    2,   3,   4,   5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15*/
+/*shift 11,   10,   9,   8,   7,   6,  5,  4,  3,  2, 1,  0,  0,  0,  0,  0 */
+/*mask  2047, 1023, 511, 255, 127, 63, 31, 15, 7,  3, 1,  0,  0,  0,  0,  0 */
+
+#define O(a) (a*1)
+static const UINT8 eg_rate_shift[32 + 64 + 32] = {
+    /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
+    /* 32 infinite time rates */
+    /* O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), */
+
+    /* fixed (should be the same as rate 0, even if it makes no difference since increment value is 0 for these rates) */
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+
+    /* rates 00-11 */
+    O(11),O(11),O(11),O(11),
+    O(10),O(10),O(10),O(10),
+    O(9),O(9),O(9),O(9),
+    O(8),O(8),O(8),O(8),
+    O(7),O(7),O(7),O(7),
+    O(6),O(6),O(6),O(6),
+    O(5),O(5),O(5),O(5),
+    O(4),O(4),O(4),O(4),
+    O(3),O(3),O(3),O(3),
+    O(2),O(2),O(2),O(2),
+    O(1),O(1),O(1),O(1),
+    O(0),O(0),O(0),O(0),
+
+    /* rate 12 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 13 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 14 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 15 */
+    O(0),O(0),O(0),O(0),
+
+    /* 32 dummy rates (same as 15 3) */
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0)
+
+};
+#undef O
+
+static const UINT8 dt_tab[4 * 32] = {
+    /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
+    /* FD=0 */
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    /* FD=1 */
+    0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
+    2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
+    /* FD=2 */
+    1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
+    5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 16, 16, 16, 16,
+    /* FD=3 */
+    2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
+    8, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20, 22, 22, 22, 22
+};
+
+
+/* OPN key frequency number -> key code follow table */
+/* fnum higher 4bit -> keycode lower 2bit */
+static const UINT8 opn_fktable[16] = { 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 3, 3, 3, 3, 3, 3 };
+
+
+/* 8 LFO speed parameters */
+/* each value represents number of samples that one LFO level will last for */
+static const UINT32 lfo_samples_per_step[8] = { 108, 77, 71, 67, 62, 44, 8, 5 };
+
+
+/*There are 4 different LFO AM depths available, they are:
+  0 dB, 1.4 dB, 5.9 dB, 11.8 dB
+  Here is how it is generated (in EG steps):
+
+  11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
+   5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
+   1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
+
+  (1.4 dB is loosing precision as you can see)
+
+  It's implemented as generator from 0..126 with step 2 then a shift
+  right N times, where N is:
+    8 for 0 dB
+    3 for 1.4 dB
+    1 for 5.9 dB
+    0 for 11.8 dB
+*/
+static const UINT8 lfo_ams_depth_shift[4] = { 8, 3, 1, 0 };
+
+
+/*There are 8 different LFO PM depths available, they are:
+  0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
+
+  Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
+  (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
+
+  Here we store only first quarter (positive one) of full waveform.
+  Full table (lfo_pm_table) containing all 128 waveforms is build
+  at run (init) time.
+
+  One value in table below represents 4 (four) basic LFO steps
+  (1 PM step = 4 AM steps).
+
+  For example:
+   at LFO SPEED=0 (which is 108 samples per basic LFO step)
+   one value from "lfo_pm_output" table lasts for 432 consecutive
+   samples (4*108=432) and one full LFO waveform cycle lasts for 13824
+   samples (32*432=13824; 32 because we store only a quarter of whole
+            waveform in the table below)
+*/
+static const UINT8 lfo_pm_output[7 * 8][8] = {
+    /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
+    /* FNUM BIT 4: 000 0001xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 6 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 7 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+
+    /* FNUM BIT 5: 000 0010xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 6 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 7 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+
+    /* FNUM BIT 6: 000 0100xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 1 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 6 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+    /* DEPTH 7 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+
+    /* FNUM BIT 7: 000 1000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 1, 1 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 4 */ { 0, 0, 0, 1, 1, 1, 1, 2 },
+    /* DEPTH 5 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+    /* DEPTH 6 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+    /* DEPTH 7 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+
+    /* FNUM BIT 8: 001 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 2 */ { 0, 0, 0, 1, 1, 1, 2, 2 },
+    /* DEPTH 3 */ { 0, 0, 1, 1, 2, 2, 3, 3 },
+    /* DEPTH 4 */ { 0, 0, 1, 2, 2, 2, 3, 4 },
+    /* DEPTH 5 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+    /* DEPTH 6 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+    /* DEPTH 7 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+
+    /* FNUM BIT 9: 010 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 2, 2, 2, 2 },
+    /* DEPTH 2 */ { 0, 0, 0, 2, 2, 2, 4, 4 },
+    /* DEPTH 3 */ { 0, 0, 2, 2, 4, 4, 6, 6 },
+    /* DEPTH 4 */ { 0, 0, 2, 4, 4, 4, 6, 8 },
+    /* DEPTH 5 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+    /* DEPTH 6 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+    /* DEPTH 7 */ { 0, 0, 0x10, 0x18, 0x20, 0x20, 0x28, 0x30 },
+
+    /* FNUM BIT10: 100 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 4, 4, 4, 4 },
+    /* DEPTH 2 */ { 0, 0, 0, 4, 4, 4, 8, 8 },
+    /* DEPTH 3 */ { 0, 0, 4, 4, 8, 8, 0xc, 0xc },
+    /* DEPTH 4 */ { 0, 0, 4, 8, 8, 8, 0xc, 0x10 },
+    /* DEPTH 5 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+    /* DEPTH 6 */ { 0, 0, 0x10, 0x18, 0x20, 0x20, 0x28, 0x30 },
+    /* DEPTH 7 */ { 0, 0, 0x20, 0x30, 0x40, 0x40, 0x50, 0x60 },
+
+};
+
+/* all 128 LFO PM waveforms */
+#if GENERATE_TABLES
+static UINT8 lfo_pm_table[128*8*16];  /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
+#else
+#include "lfo_pm_table.h"
+#endif
+/* register number to channel number , slot offset */
+#define OPN_CHAN(N) (N&3)
+#define OPN_SLOT(N) ((N>>2)&3)
+
+/* slot number */
+#define SLOT1 0
+#define SLOT2 2
+#define SLOT3 1
+#define SLOT4 3
+
+/* struct describing a single operator (SLOT) */
+typedef struct {
+    INT32* DT; /* detune          :dt_tab[DT]      */
+    UINT8 KSR; /* key scale rate  :3-KSR           */
+    UINT32 ar; /* attack rate                      */
+    UINT32 d1r; /* decay rate                       */
+    UINT32 d2r; /* sustain rate                     */
+    UINT32 rr; /* release rate                     */
+    UINT8 ksr; /* key scale rate  :kcode>>(3-KSR)  */
+    UINT32 mul; /* multiple        :ML_TABLE[ML]    */
+
+    /* Phase Generator */
+    UINT32 phase; /* phase counter */
+    INT32 Incr; /* phase step */
+
+    /* Envelope Generator */
+    UINT8 state; /* phase type */
+    UINT32 tl; /* total level: TL << 3 */
+    INT32 volume; /* envelope counter */
+    UINT32 sl; /* sustain level:sl_table[SL] */
+    UINT32 vol_out; /* current output from EG circuit (without AM from LFO) */
+
+    UINT8 eg_sh_ar; /*  (attack state)  */
+    UINT8 eg_sel_ar; /*  (attack state)  */
+    UINT8 eg_sh_d1r; /*  (decay state)   */
+    UINT8 eg_sel_d1r; /*  (decay state)   */
+    UINT8 eg_sh_d2r; /*  (sustain state) */
+    UINT8 eg_sel_d2r; /*  (sustain state) */
+    UINT8 eg_sh_rr; /*  (release state) */
+    UINT8 eg_sel_rr; /*  (release state) */
+
+    UINT8 ssg; /* SSG-EG waveform  */
+    UINT8 ssgn; /* SSG-EG negated output  */
+
+    UINT8 key; /* 0=last key was KEY OFF, 1=KEY ON */
+
+    /* LFO */
+    UINT32 AMmask; /* AM enable flag */
+} FM_SLOT;
+
+typedef struct {
+    FM_SLOT SLOT[4]; /* four SLOTs (operators) */
+
+    UINT8 ALGO; /* algorithm */
+    UINT8 FB; /* feedback shift */
+    INT32 op1_out[2]; /* op1 output for feedback */
+
+    INT32* connect1; /* SLOT1 output pointer */
+    INT32* connect3; /* SLOT3 output pointer */
+    INT32* connect2; /* SLOT2 output pointer */
+    INT32* connect4; /* SLOT4 output pointer */
+
+    INT32* mem_connect; /* where to put the delayed sample (MEM) */
+    INT32 mem_value; /* delayed sample (MEM) value */
+
+    INT32 pms; /* channel PMS */
+    UINT8 ams; /* channel AMS */
+
+    UINT32 fc; /* fnum,blk:adjusted to sample rate */
+    UINT8 kcode; /* key code */
+    UINT32 block_fnum;
+    /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+} FM_CH;
+
+#if GENERATE_TABLES
+int ym2612_OPN_ST_dt_tab[8][32];  /* DeTune table         */
+#else
+#include "ym2612_OPN_ST_dt_tab.h"
+#endif
+
+typedef struct {
+    double clock; /* master clock  (Hz)   */
+    UINT32 rate; /* sampling rate (Hz)   */
+    UINT16 address; /* address register     */
+    UINT8 status; /* status flag          */
+    UINT32 mode; /* mode  CSM / 3SLOT    */
+    UINT8 fn_h; /* freq latch           */
+    INT32 TimerBase; /* Timer base time      */
+    INT32 TA; /* timer a value        */
+    INT32 TAL; /* timer a base          */
+    INT32 TAC; /* timer a counter      */
+    INT32 TB; /* timer b value        */
+    INT32 TBL; /* timer b base          */
+    INT32 TBC; /* timer b counter      */
+} FM_ST;
+
+
+/***********************************************************/
+/* OPN unit                                                */
+/***********************************************************/
+
+/* OPN 3slot struct */
+typedef struct {
+    UINT32 fc[3]; /* fnum3,blk3: calculated */
+    UINT8 fn_h; /* freq3 latch */
+    UINT8 kcode[3]; /* key code */
+    UINT32 block_fnum[3];
+    /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+    UINT8 key_csm; /* CSM mode Key-ON flag */
+} FM_3SLOT;
+
+#if GENERATE_TABLES
+static unsigned int fn_table[4096];
+#else
+#include "fn_table.h"
+#endif
+
+/* OPN/A/B common state */
+typedef struct {
+    FM_ST ST; /* general state */
+    FM_3SLOT SL3; /* 3 slot mode state */
+    unsigned int pan[6 * 2]; /* fm channels output masks (0xffffffff = enable) */
+
+    UINT32 eg_cnt; /* global envelope generator counter */
+    UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/144/3 */
+    UINT32 eg_timer_add; /* step of eg_timer */
+    UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 3 samples (on real chip) */
+
+    /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
+       but LFO works with one more bit of a precision so we really need 4096 elements */
+#if !GENERATE_TABLES
+    const
+#endif
+    unsigned int* pfn_table; /* fnumber->increment counter */
+    UINT32 fn_max; /* max increment (required for calculating phase overflow) */
+
+    /* LFO */
+    UINT8 lfo_cnt; /* current LFO phase (out of 128) */
+    UINT32 lfo_timer; /* current LFO phase runs at LFO frequency */
+    UINT32 lfo_timer_add; /* step of lfo_timer */
+    UINT32 lfo_timer_overflow; /* LFO timer overflows every N samples (depends on LFO frequency) */
+    UINT32 LFO_AM; /* current LFO AM step */
+    UINT32 LFO_PM; /* current LFO PM step */
+} FM_OPN;
+
+/***********************************************************/
+/* YM2612 chip                                                */
+/***********************************************************/
+typedef struct {
+    FM_CH CH[6]; /* channel state */
+    UINT8 dacen; /* DAC mode  */
+    INT32 dacout; /* DAC output */
+    FM_OPN OPN; /* OPN state */
+    UINT32 divisor; /* sample rate divsor in system clock */
+} YM2612;
+
+/* emulated chip */
+static YM2612 ym2612;
+
+/* current chip state */
+static INT32 m2, c1, c2; /* Phase Modulation input for operators 2,3,4 */
+static INT32 mem; /* one sample delay memory */
+static INT32 out_fm[8]; /* outputs of working channels */
+static UINT32 bitmask; /* working channels output bitmasking (DAC quantization) */
+
+/* mirror of all OPN registers */
+static uint8_t OPNREGS[512];
+
+/* limiter */
+#define Limit(val, max,min) { \
+  if ( val > max )      val = max; \
+  else if ( val < min ) val = min; \
+}
+
+INLINE void FM_KEYON(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (!SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        /* restart Phase Generator */
+        SLOT->phase = 0;
+
+        /* reset SSG-EG inversion flag */
+        SLOT->ssgn = 0;
+
+        if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+            SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
+        }
+        else {
+            /* force attenuation level to 0 */
+            SLOT->volume = MIN_ATT_INDEX;
+
+            /* directly switch to Decay (or Sustain) */
+            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+        }
+
+        /* recalculate EG output */
+        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+        else
+            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+    }
+
+    SLOT->key = 1;
+}
+
+INLINE void FM_KEYOFF(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        if (SLOT->state > EG_REL) {
+            SLOT->state = EG_REL; /* phase -> Release */
+
+            /* SSG-EG specific update */
+            if (SLOT->ssg & 0x08) {
+                /* convert EG attenuation level */
+                if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                    SLOT->volume = (0x200 - SLOT->volume);
+
+                /* force EG attenuation level */
+                if (SLOT->volume >= 0x200) {
+                    SLOT->volume = MAX_ATT_INDEX;
+                    SLOT->state = EG_OFF;
+                }
+
+                /* recalculate EG output */
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+        }
+    }
+
+    SLOT->key = 0;
+}
+
+INLINE void FM_KEYON_CSM(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (!SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        /* restart Phase Generator */
+        SLOT->phase = 0;
+
+        /* reset SSG-EG inversion flag */
+        SLOT->ssgn = 0;
+
+        if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+            SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
+        }
+        else {
+            /* force attenuation level to 0 */
+            SLOT->volume = MIN_ATT_INDEX;
+
+            /* directly switch to Decay (or Sustain) */
+            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+        }
+
+        /* recalculate EG output */
+        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+        else
+            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+    }
+}
+
+INLINE void FM_KEYOFF_CSM(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+    if (!SLOT->key) {
+        if (SLOT->state > EG_REL) {
+            SLOT->state = EG_REL; /* phase -> Release */
+
+            /* SSG-EG specific update */
+            if (SLOT->ssg & 0x08) {
+                /* convert EG attenuation level */
+                if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                    SLOT->volume = (0x200 - SLOT->volume);
+
+                /* force EG attenuation level */
+                if (SLOT->volume >= 0x200) {
+                    SLOT->volume = MAX_ATT_INDEX;
+                    SLOT->state = EG_OFF;
+                }
+
+                /* recalculate EG output */
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+        }
+    }
+}
+
+/* CSM Key Controll */
+INLINE void CSMKeyControll(FM_CH* CH) {
+    /* all key ON (verified by Nemesis on real hardware) */
+    FM_KEYON_CSM(CH,SLOT1);
+    FM_KEYON_CSM(CH,SLOT2);
+    FM_KEYON_CSM(CH,SLOT3);
+    FM_KEYON_CSM(CH,SLOT4);
+    ym2612.OPN.SL3.key_csm = 1;
+}
+
+INLINE void INTERNAL_TIMER_A() {
+    if (ym2612.OPN.ST.mode & 0x01) {
+        if ((ym2612.OPN.ST.TAC -= ym2612.OPN.ST.TimerBase) <= 0) {
+            /* set status (if enabled) */
+            if (ym2612.OPN.ST.mode & 0x04)
+                ym2612.OPN.ST.status |= 0x01;
+
+            /* reload the counter */
+            if (ym2612.OPN.ST.TAL)
+                ym2612.OPN.ST.TAC += ym2612.OPN.ST.TAL;
+            else
+                ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
+
+            /* CSM mode auto key on */
+            if ((ym2612.OPN.ST.mode & 0xC0) == 0x80)
+                CSMKeyControll(&ym2612.CH[2]);
+        }
+    }
+}
+
+INLINE void INTERNAL_TIMER_B(int step) {
+    if (ym2612.OPN.ST.mode & 0x02) {
+        if ((ym2612.OPN.ST.TBC -= (__mul_instruction(ym2612.OPN.ST.TimerBase, step))) <= 0) {
+            /* set status (if enabled) */
+            if (ym2612.OPN.ST.mode & 0x08)
+                ym2612.OPN.ST.status |= 0x02;
+
+            /* reload the counter */
+            if (ym2612.OPN.ST.TBL)
+                ym2612.OPN.ST.TBC += ym2612.OPN.ST.TBL;
+            else
+                ym2612.OPN.ST.TBC = ym2612.OPN.ST.TBL;
+        }
+    }
+}
+
+/* OPN Mode Register Write */
+INLINE void set_timers(int v) {
+    /* b7 = CSM MODE */
+    /* b6 = 3 slot mode */
+    /* b5 = reset b */
+    /* b4 = reset a */
+    /* b3 = timer enable b */
+    /* b2 = timer enable a */
+    /* b1 = load b */
+    /* b0 = load a */
+
+    if ((ym2612.OPN.ST.mode ^ v) & 0xC0) {
+        /* phase increment need to be recalculated */
+        ym2612.CH[2].SLOT[SLOT1].Incr = -1;
+
+        /* CSM mode disabled and CSM key ON active*/
+        if (((v & 0xC0) != 0x80) && ym2612.OPN.SL3.key_csm) {
+            /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
+            ym2612.OPN.SL3.key_csm = 0;
+        }
+    }
+
+    /* reload Timers */
+    if ((v & 1) && !(ym2612.OPN.ST.mode & 1))
+        ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
+    if ((v & 2) && !(ym2612.OPN.ST.mode & 2))
+        ym2612.OPN.ST.TBC = ym2612.OPN.ST.TBL;
+
+    /* reset Timers flags */
+    ym2612.OPN.ST.status &= (~v >> 4);
+
+    ym2612.OPN.ST.mode = v;
+}
+
+/* set algorithm connection */
+INLINE void setup_connection(FM_CH* CH, int ch) {
+    INT32* carrier = &out_fm[ch];
+
+    INT32** om1 = &CH->connect1;
+    INT32** om2 = &CH->connect3;
+    INT32** oc1 = &CH->connect2;
+
+    INT32** memc = &CH->mem_connect;
+
+    switch (CH->ALGO) {
+        case 0:
+            /* M1---C1---MEM---M2---C2---OUT */
+            *om1 = &c1;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 1:
+            /* M1------+-MEM---M2---C2---OUT */
+            /*      C1-+                     */
+            *om1 = &mem;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 2:
+            /* M1-----------------+-C2---OUT */
+            /*      C1---MEM---M2-+          */
+            *om1 = &c2;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 3:
+            /* M1---C1---MEM------+-C2---OUT */
+            /*                 M2-+          */
+            *om1 = &c1;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &c2;
+            break;
+        case 4:
+            /* M1---C1-+-OUT */
+            /* M2---C2-+     */
+            /* MEM: not used */
+            *om1 = &c1;
+            *oc1 = carrier;
+            *om2 = &c2;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+        case 5:
+            /*    +----C1----+     */
+            /* M1-+-MEM---M2-+-OUT */
+            /*    +----C2----+     */
+            *om1 = 0; /* special mark */
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &m2;
+            break;
+        case 6:
+            /* M1---C1-+     */
+            /*      M2-+-OUT */
+            /*      C2-+     */
+            /* MEM: not used */
+            *om1 = &c1;
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+        case 7:
+            /* M1-+     */
+            /* C1-+-OUT */
+            /* M2-+     */
+            /* C2-+     */
+            /* MEM: not used*/
+            *om1 = carrier;
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+    }
+
+    CH->connect4 = carrier;
+}
+
+/* set detune & multiple */
+INLINE void set_det_mul(FM_CH* CH, FM_SLOT* SLOT, int v) {
+    SLOT->mul = (v & 0x0f) ? __fast_mul(v & 0x0f, 2) : 1;
+    SLOT->DT = (INT32 *)ym2612_OPN_ST_dt_tab[(v >> 4) & 7];
+    CH->SLOT[SLOT1].Incr = -1;
+}
+
+/* set total level */
+INLINE void set_tl(FM_SLOT* SLOT, int v) {
+    SLOT->tl = (v & 0x7f) << (ENV_BITS - 7); /* 7bit TL */
+
+    /* recalculate EG output */
+    if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)) && (SLOT->state > EG_REL))
+        SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+    else
+        SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+}
+
+/* set attack rate & key scale  */
+INLINE void set_ar_ksr(FM_CH* CH, FM_SLOT* SLOT, int v) {
+    UINT8 old_KSR = SLOT->KSR;
+
+    SLOT->ar = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->KSR = 3 - (v >> 6);
+    if (SLOT->KSR != old_KSR) {
+        CH->SLOT[SLOT1].Incr = -1;
+    }
+
+    /* Even if it seems unnecessary to do it here, it could happen that KSR and KC  */
+    /* are modified but the resulted SLOT->ksr value (kc >> SLOT->KSR) remains unchanged. */
+    /* In such case, Attack Rate would not be recalculated by "refresh_fc_eg_slot". */
+    /* This actually fixes the intro of "The Adventures of Batman & Robin" (Eke-Eke)         */
+    if ((SLOT->ar + SLOT->ksr) < (32 + 62)) {
+        SLOT->eg_sh_ar = eg_rate_shift[SLOT->ar + SLOT->ksr];
+        SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr];
+    }
+    else {
+        /* verified by Nemesis on real hardware (Attack phase is blocked) */
+        SLOT->eg_sh_ar = 0;
+        SLOT->eg_sel_ar = 18 * RATE_STEPS;
+    }
+}
+
+/* set decay rate */
+INLINE void set_dr(FM_SLOT* SLOT, int v) {
+    SLOT->d1r = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->eg_sh_d1r = eg_rate_shift[SLOT->d1r + SLOT->ksr];
+    SLOT->eg_sel_d1r = eg_rate_select[SLOT->d1r + SLOT->ksr];
+}
+
+/* set sustain rate */
+INLINE void set_sr(FM_SLOT* SLOT, int v) {
+    SLOT->d2r = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->eg_sh_d2r = eg_rate_shift[SLOT->d2r + SLOT->ksr];
+    SLOT->eg_sel_d2r = eg_rate_select[SLOT->d2r + SLOT->ksr];
+}
+
+/* set release rate */
+INLINE void set_sl_rr(FM_SLOT* SLOT, int v) {
+    SLOT->sl = sl_table[v >> 4];
+
+    /* check EG state changes */
+    if ((SLOT->state == EG_DEC) && (SLOT->volume >= (INT32)(SLOT->sl)))
+        SLOT->state = EG_SUS;
+
+    SLOT->rr = 34 + ((v & 0x0f) << 2);
+
+    SLOT->eg_sh_rr = eg_rate_shift[SLOT->rr + SLOT->ksr];
+    SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
+}
+
+/* advance LFO to next sample */
+INLINE void advance_lfo() {
+    if (ym2612.OPN.lfo_timer_overflow) /* LFO enabled ? */
+    {
+        /* increment LFO timer */
+        ym2612.OPN.lfo_timer += ym2612.OPN.lfo_timer_add;
+
+        /* when LFO is enabled, one level will last for 108, 77, 71, 67, 62, 44, 8 or 5 samples */
+        while (ym2612.OPN.lfo_timer >= ym2612.OPN.lfo_timer_overflow) {
+            ym2612.OPN.lfo_timer -= ym2612.OPN.lfo_timer_overflow;
+
+            /* There are 128 LFO steps */
+            ym2612.OPN.lfo_cnt = (ym2612.OPN.lfo_cnt + 1) & 127;
+
+            /* triangle */
+            /* AM: 0 to 126 step +2, 126 to 0 step -2 */
+            if (ym2612.OPN.lfo_cnt < 64)
+                ym2612.OPN.LFO_AM = __fast_mul(ym2612.OPN.lfo_cnt, 2);
+            else
+                ym2612.OPN.LFO_AM = 126 - __fast_mul((ym2612.OPN.lfo_cnt&63), 2);
+
+            /* PM works with 4 times slower clock */
+            ym2612.OPN.LFO_PM = ym2612.OPN.lfo_cnt >> 2;
+        }
+    }
+}
+
+
+INLINE void advance_eg_channels(void) {
+    unsigned int eg_cnt = ym2612.OPN.eg_cnt;
+    unsigned int i = 0;
+    unsigned int j;
+    FM_SLOT* SLOT;
+
+    do {
+        SLOT = &ym2612.CH[i].SLOT[SLOT1];
+        j = 4; /* four operators per channel */
+        do {
+            switch (SLOT->state) {
+                case EG_ATT: /* attack phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_ar) - 1))) {
+                        /* update attenuation level */
+                        SLOT->volume += (~SLOT->volume * (eg_inc[SLOT->eg_sel_ar + ((eg_cnt >> SLOT->eg_sh_ar) & 7)]))
+                                >> 4;
+
+                        /* check phase transition*/
+                        if (SLOT->volume <= MIN_ATT_INDEX) {
+                            SLOT->volume = MIN_ATT_INDEX;
+                            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC; /* special case where SL=0 */
+                        }
+
+                        /* recalculate EG output */
+                        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04))) /* SSG-EG Output Inversion */
+                            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                        else
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                    }
+                    break;
+                }
+
+                case EG_DEC: /* decay phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_d1r) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200) {
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_d1r + ((eg_cnt>>SLOT->eg_sh_d1r)&7)], 4);
+
+                                /* recalculate EG output */
+                                if (SLOT->ssgn ^ (SLOT->ssg & 0x04)) /* SSG-EG Output Inversion */
+                                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                                else
+                                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((eg_cnt >> SLOT->eg_sh_d1r) & 7)];
+
+                            /* recalculate EG output */
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                        }
+
+                        /* check phase transition*/
+                        if (SLOT->volume >= (INT32)(SLOT->sl))
+                            SLOT->state = EG_SUS;
+                    }
+                    break;
+                }
+
+                case EG_SUS: /* sustain phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_d2r) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200) {
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_d2r + ((eg_cnt>>SLOT->eg_sh_d2r)&7)], 4);
+
+                                /* recalculate EG output */
+                                if (SLOT->ssgn ^ (SLOT->ssg & 0x04)) /* SSG-EG Output Inversion */
+                                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                                else
+                                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_d2r + ((eg_cnt >> SLOT->eg_sh_d2r) & 7)];
+
+                            /* check phase transition*/
+                            if (SLOT->volume >= MAX_ATT_INDEX)
+                                SLOT->volume = MAX_ATT_INDEX;
+                            /* do not change SLOT->state (verified on real chip) */
+
+                            /* recalculate EG output */
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                        }
+                    }
+                    break;
+                }
+
+                case EG_REL: /* release phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_rr) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200)
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_rr + ((eg_cnt>>SLOT->eg_sh_rr)&7)], 4);
+
+                            /* check phase transition */
+                            if (SLOT->volume >= 0x200) {
+                                SLOT->volume = MAX_ATT_INDEX;
+                                SLOT->state = EG_OFF;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((eg_cnt >> SLOT->eg_sh_rr) & 7)];
+
+                            /* check phase transition*/
+                            if (SLOT->volume >= MAX_ATT_INDEX) {
+                                SLOT->volume = MAX_ATT_INDEX;
+                                SLOT->state = EG_OFF;
+                            }
+                        }
+
+                        /* recalculate EG output */
+                        SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                    }
+                    break;
+                }
+            }
+            SLOT++;
+            j--;
+        }
+        while (j);
+        i++;
+    }
+    while (i < 6); /* 6 channels */
+}
+
+/* SSG-EG update process */
+/* The behavior is based upon Nemesis tests on real hardware */
+/* This is actually executed before each samples */
+INLINE void update_ssg_eg_channel(FM_SLOT* SLOT) {
+    unsigned int i = 4; /* four operators per channel */
+
+    do {
+        /* detect SSG-EG transition */
+        /* this is not required during release phase as the attenuation has been forced to MAX and output invert flag is not used */
+        /* if an Attack Phase is programmed, inversion can occur on each sample */
+        if ((SLOT->ssg & 0x08) && (SLOT->volume >= 0x200) && (SLOT->state > EG_REL)) {
+            if (SLOT->ssg & 0x01) /* bit 0 = hold SSG-EG */
+            {
+                /* set inversion flag */
+                if (SLOT->ssg & 0x02)
+                    SLOT->ssgn = 4;
+
+                /* force attenuation level during decay phases */
+                if ((SLOT->state != EG_ATT) && !(SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+                    SLOT->volume = MAX_ATT_INDEX;
+            }
+            else /* loop SSG-EG */
+            {
+                /* toggle output inversion flag or reset Phase Generator */
+                if (SLOT->ssg & 0x02)
+                    SLOT->ssgn ^= 4;
+                else
+                    SLOT->phase = 0;
+
+                /* same as Key ON */
+                if (SLOT->state != EG_ATT) {
+                    if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+                        SLOT->state = (SLOT->volume <= MIN_ATT_INDEX)
+                                          ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC)
+                                          : EG_ATT;
+                    }
+                    else {
+                        /* Attack Rate is maximal: directly switch to Decay or Substain */
+                        SLOT->volume = MIN_ATT_INDEX;
+                        SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+                    }
+                }
+            }
+
+            /* recalculate EG output */
+            if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+            else
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+        }
+
+        /* next slot */
+        SLOT++;
+        i--;
+    }
+    while (i);
+}
+
+INLINE void update_phase_lfo_slot(FM_SLOT* SLOT, INT32 pms, UINT32 block_fnum) {
+    INT32 lfo_fn_table_index_offset = lfo_pm_table[
+        (((block_fnum & 0x7f0) >> 4) << 7) + pms + (ym2612.OPN.LFO_PM & 0xF)];
+    if (ym2612.OPN.LFO_PM & 0x10) lfo_fn_table_index_offset = -lfo_fn_table_index_offset;
+
+    if (lfo_fn_table_index_offset) /* LFO phase modulation active */
+    {
+        UINT8 blk;
+        int kc, fc;
+
+        block_fnum = __fast_mul(block_fnum, 2) + lfo_fn_table_index_offset;
+        blk = (block_fnum & 0x7000) >> 12;
+        block_fnum = block_fnum & 0xfff;
+
+        /* keyscale code */
+        kc = (blk << 2) | opn_fktable[block_fnum >> 8];
+
+        /* (frequency) phase increment counter */
+        fc = (ym2612.OPN.pfn_table[block_fnum] >> (7 - blk)) + SLOT->DT[kc];
+
+        /* (frequency) phase overflow (credits to Nemesis) */
+        if (fc < 0) fc += ym2612.OPN.fn_max;
+
+        /* update phase */
+        SLOT->phase += (fc * SLOT->mul) >> 1;
+    }
+    else /* LFO phase modulation  = zero */
+    {
+        SLOT->phase += SLOT->Incr;
+    }
+}
+
+INLINE void update_phase_lfo_channel(FM_CH* CH) {
+    UINT32 block_fnum = CH->block_fnum;
+
+    INT32 lfo_fn_table_index_offset = lfo_pm_table[
+        (((block_fnum & 0x7f0) >> 4) << 7) + CH->pms + (ym2612.OPN.LFO_PM & 0xF)];
+    if (ym2612.OPN.LFO_PM & 0x10) lfo_fn_table_index_offset = -lfo_fn_table_index_offset;
+
+    if (lfo_fn_table_index_offset) /* LFO phase modulation active */
+    {
+        UINT8 blk;
+        int kc, fc, finc;
+
+        block_fnum = __fast_mul(block_fnum , 2) + lfo_fn_table_index_offset;
+        blk = (block_fnum & 0x7000) >> 12;
+        block_fnum = block_fnum & 0xfff;
+
+        /* keyscale code */
+        kc = (blk << 2) | opn_fktable[block_fnum >> 8];
+
+        /* (frequency) phase increment counter */
+        fc = (ym2612.OPN.pfn_table[block_fnum] >> (7 - blk));
+
+        /* (frequency) phase overflow (credits to Nemesis) */
+        finc = fc + CH->SLOT[SLOT1].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT1].phase += (finc * CH->SLOT[SLOT1].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT2].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT2].phase += (finc * CH->SLOT[SLOT2].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT3].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT3].phase += (finc * CH->SLOT[SLOT3].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT4].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT4].phase += (finc * CH->SLOT[SLOT4].mul) >> 1;
+    }
+    else /* LFO phase modulation  = zero */
+    {
+        CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
+        CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
+        CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
+        CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
+    }
+}
+
+/* update phase increment and envelope generator */
+INLINE void refresh_fc_eg_slot(FM_SLOT* SLOT, int fc, int kc) {
+    /* add detune value */
+    fc += SLOT->DT[kc];
+
+    /* (frequency) phase overflow (credits to Nemesis) */
+    if (fc < 0) fc += ym2612.OPN.fn_max;
+
+    /* (frequency) phase increment counter */
+    SLOT->Incr = (fc * SLOT->mul) >> 1;
+
+    /* ksr */
+    kc = kc >> SLOT->KSR;
+
+    if (SLOT->ksr != kc) {
+        SLOT->ksr = kc;
+
+        /* recalculate envelope generator rates */
+        if ((SLOT->ar + kc) < (32 + 62)) {
+            SLOT->eg_sh_ar = eg_rate_shift[SLOT->ar + kc];
+            SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + kc];
+        }
+        else {
+            /* verified by Nemesis on real hardware (Attack phase is blocked) */
+            SLOT->eg_sh_ar = 0;
+            SLOT->eg_sel_ar = 18 * RATE_STEPS;
+        }
+
+        SLOT->eg_sh_d1r = eg_rate_shift[SLOT->d1r + kc];
+        SLOT->eg_sel_d1r = eg_rate_select[SLOT->d1r + kc];
+
+        SLOT->eg_sh_d2r = eg_rate_shift[SLOT->d2r + kc];
+        SLOT->eg_sel_d2r = eg_rate_select[SLOT->d2r + kc];
+
+        SLOT->eg_sh_rr = eg_rate_shift[SLOT->rr + kc];
+        SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + kc];
+    }
+}
+
+/* update phase increment counters */
+INLINE void refresh_fc_eg_chan(FM_CH* CH) {
+    if (CH->SLOT[SLOT1].Incr == -1) {
+        int fc = CH->fc;
+        int kc = CH->kcode;
+        refresh_fc_eg_slot(&CH->SLOT[SLOT1], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT2], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT3], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT4], fc, kc);
+    }
+}
+
+#define volume_calc(OP) ((OP)->vol_out + (AM & (OP)->AMmask))
+
+INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm) {
+    UINT32 p = (env << 3) + sin_tab[(((signed int)((phase & ~FREQ_MASK) + (pm << 15))) >> FREQ_SH) & SIN_MASK];
+
+    if (p >= TL_TAB_LEN)
+        return 0;
+    return tl_tab[p];
+}
+
+INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm) {
+    UINT32 p = (env << 3) + sin_tab[(((signed int)((phase & ~FREQ_MASK) + pm)) >> FREQ_SH) & SIN_MASK];
+
+    if (p >= TL_TAB_LEN)
+        return 0;
+    return tl_tab[p];
+}
+
+INLINE void chan_calc(FM_CH* CH) {
+    UINT32 AM = ym2612.OPN.LFO_AM >> CH->ams;
+    unsigned int eg_out = volume_calc(&CH->SLOT[SLOT1]);
+
+    m2 = c1 = c2 = mem = 0;
+
+    *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
+    {
+        INT32 out = CH->op1_out[0] + CH->op1_out[1];
+        CH->op1_out[0] = CH->op1_out[1];
+
+        if (!CH->connect1) {
+            /* algorithm 5  */
+            mem = c1 = c2 = CH->op1_out[0];
+        }
+        else {
+            /* other algorithms */
+            *CH->connect1 += CH->op1_out[0];
+        }
+
+        CH->op1_out[1] = 0;
+        if (eg_out < ENV_QUIET) /* SLOT 1 */
+        {
+            if (!CH->FB)
+                out = 0;
+
+            CH->op1_out[1] = op_calc1(CH->SLOT[SLOT1].phase, eg_out, (out << CH->FB));
+        }
+    }
+
+    eg_out = volume_calc(&CH->SLOT[SLOT3]);
+    if (eg_out < ENV_QUIET) /* SLOT 3 */
+        *CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, m2);
+
+    eg_out = volume_calc(&CH->SLOT[SLOT2]);
+    if (eg_out < ENV_QUIET) /* SLOT 2 */
+        *CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, c1);
+
+    eg_out = volume_calc(&CH->SLOT[SLOT4]);
+    if (eg_out < ENV_QUIET) /* SLOT 4 */
+        *CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, c2);
+
+
+    /* store current MEM */
+    CH->mem_value = mem;
+
+    /* update phase counters AFTER output calculations */
+    if (CH->pms) {
+        /* add support for 3 slot mode */
+        if ((ym2612.OPN.ST.mode & 0xC0) && (CH == &ym2612.CH[2])) {
+            update_phase_lfo_slot(&CH->SLOT[SLOT1], CH->pms, ym2612.OPN.SL3.block_fnum[1]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT2], CH->pms, ym2612.OPN.SL3.block_fnum[2]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT3], CH->pms, ym2612.OPN.SL3.block_fnum[0]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
+        }
+        else update_phase_lfo_channel(CH);
+    }
+    else /* no LFO phase modulation */
+    {
+        CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
+        CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
+        CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
+        CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
+    }
+}
+
+/* write a OPN mode register 0x20-0x2f */
+INLINE void OPNWriteMode(int r, int v) {
+    UINT8 c;
+    FM_CH* CH;
+
+    OPNREGS[r] = v;
+
+    switch (r) {
+        case 0x21: /* Test */
+            break;
+
+        case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/ym2612) */
+            if (v & 8) /* LFO enabled ? */
+            {
+                if (!ym2612.OPN.lfo_timer_overflow) {
+                    /* restart LFO */
+                    ym2612.OPN.lfo_cnt = 0;
+                    ym2612.OPN.lfo_timer = 0;
+                    ym2612.OPN.LFO_AM = 0;
+                    ym2612.OPN.LFO_PM = 0;
+                }
+
+                ym2612.OPN.lfo_timer_overflow = lfo_samples_per_step[v & 7] << LFO_SH;
+            }
+            else {
+                ym2612.OPN.lfo_timer_overflow = 0;
+            }
+
+            break;
+        case 0x24: /* timer A High 8*/
+            ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x03) | (((int)v) << 2);
+            ym2612.OPN.ST.TAL = (1024 - ym2612.OPN.ST.TA) << TIMER_SH;
+            break;
+        case 0x25: /* timer A Low 2*/
+            ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x3fc) | (v & 3);
+            ym2612.OPN.ST.TAL = (1024 - ym2612.OPN.ST.TA) << TIMER_SH;
+            break;
+        case 0x26: /* timer B */
+            ym2612.OPN.ST.TB = v;
+            ym2612.OPN.ST.TBL = (256 - ym2612.OPN.ST.TB) << (TIMER_SH + 4);
+            break;
+        case 0x27: /* mode, timer control */
+            set_timers(v);
+            break;
+        case 0x28: /* key on / off */
+            c = v & 0x03;
+            if (c == 3) break;
+            if (v & 0x04) c += 3; /* CH 4-6 */
+            CH = &ym2612.CH[c];
+
+            if (v & 0x10) FM_KEYON(CH,SLOT1);
+            else FM_KEYOFF(CH,SLOT1);
+            if (v & 0x20) FM_KEYON(CH,SLOT2);
+            else FM_KEYOFF(CH,SLOT2);
+            if (v & 0x40) FM_KEYON(CH,SLOT3);
+            else FM_KEYOFF(CH,SLOT3);
+            if (v & 0x80) FM_KEYON(CH,SLOT4);
+            else FM_KEYOFF(CH,SLOT4);
+            break;
+    }
+}
+
+/* write a OPN register (0x30-0xff) */
+INLINE void OPNWriteReg(int r, int v) {
+    FM_CH* CH;
+    FM_SLOT* SLOT;
+
+    OPNREGS[r] = v;
+
+    UINT8 c = OPN_CHAN(r);
+
+    if (c == 3) return; /* 0xX3,0xX7,0xXB,0xXF */
+
+    if (r >= 0x100) c += 3;
+
+    CH = &ym2612.CH[c];
+
+    SLOT = &(CH->SLOT[OPN_SLOT(r)]);
+
+    switch (r & 0xf0) {
+        case 0x30: /* DET , MUL */
+            set_det_mul(CH, SLOT, v);
+            break;
+
+        case 0x40: /* TL */
+            set_tl(SLOT, v);
+            break;
+
+        case 0x50: /* KS, AR */
+            set_ar_ksr(CH, SLOT, v);
+            break;
+
+        case 0x60: /* bit7 = AM ENABLE, DR */
+            set_dr(SLOT, v);
+            SLOT->AMmask = (v & 0x80) ? ~0 : 0;
+            break;
+
+        case 0x70: /*     SR */
+            set_sr(SLOT, v);
+            break;
+
+        case 0x80: /* SL, RR */
+            set_sl_rr(SLOT, v);
+            break;
+
+        case 0x90: /* SSG-EG */
+            SLOT->ssg = v & 0x0f;
+
+        /* recalculate EG output */
+            if (SLOT->state > EG_REL) {
+                if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                else
+                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+
+        /* SSG-EG envelope shapes :
+
+        E AtAlH
+        1 0 0 0  \\\\
+
+        1 0 0 1  \___
+
+        1 0 1 0  \/\/
+                  ___
+        1 0 1 1  \
+
+        1 1 0 0  ////
+                  ___
+        1 1 0 1  /
+
+        1 1 1 0  /\/\
+
+        1 1 1 1  /___
+
+
+        E = SSG-EG enable
+
+
+        The shapes are generated using Attack, Decay and Sustain phases.
+
+        Each single character in the diagrams above represents this whole
+        sequence:
+
+        - when KEY-ON = 1, normal Attack phase is generated (*without* any
+          difference when compared to normal mode),
+
+        - later, when envelope level reaches minimum level (max volume),
+          the EG switches to Decay phase (which works with bigger steps
+          when compared to normal mode - see below),
+
+        - later when envelope level passes the SL level,
+          the EG swithes to Sustain phase (which works with bigger steps
+          when compared to normal mode - see below),
+
+        - finally when envelope level reaches maximum level (min volume),
+          the EG switches to Attack phase again (depends on actual waveform).
+
+        Important is that when switch to Attack phase occurs, the phase counter
+        of that operator will be zeroed-out (as in normal KEY-ON) but not always.
+        (I havent found the rule for that - perhaps only when the output level is low)
+
+        The difference (when compared to normal Envelope Generator mode) is
+        that the resolution in Decay and Sustain phases is 4 times lower;
+        this results in only 256 steps instead of normal 1024.
+        In other words:
+        when SSG-EG is disabled, the step inside of the EG is one,
+        when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
+
+        Times between the level changes are the same in both modes.
+
+
+        Important:
+        Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
+        it is the same in both SSG and no-SSG modes, with this exception:
+
+        when the SSG-EG is enabled and is generating raising levels
+        (when the EG output is inverted) the SL will be found at wrong level !!!
+        For example, when SL=02:
+          0 -6 = -6dB in non-inverted EG output
+          96-6 = -90dB in inverted EG output
+        Which means that EG compares its level to SL as usual, and that the
+        output is simply inverted afterall.
+
+
+        The Yamaha's manuals say that AR should be set to 0x1f (max speed).
+        That is not necessary, but then EG will be generating Attack phase.
+
+        */
+
+
+            break;
+
+        case 0xa0:
+            switch (OPN_SLOT(r)) {
+                case 0: /* 0xa0-0xa2 : FNUM1 */
+                {
+                    UINT32 fn = (((UINT32)((ym2612.OPN.ST.fn_h) & 7)) << 8) + v;
+                    UINT8 blk = ym2612.OPN.ST.fn_h >> 3;
+                    /* keyscale code */
+                    CH->kcode = (blk << 2) | opn_fktable[fn >> 7];
+                    /* phase increment counter */
+                    CH->fc = ym2612.OPN.pfn_table[__fast_mul(fn, 2)] >> (7 - blk);
+
+                    /* store fnum in clear form for LFO PM calculations */
+                    CH->block_fnum = (blk << 11) | fn;
+
+                    CH->SLOT[SLOT1].Incr = -1;
+                    break;
+                }
+                case 1: /* 0xa4-0xa6 : FNUM2,BLK */
+                    ym2612.OPN.ST.fn_h = v & 0x3f;
+                    break;
+                case 2: /* 0xa8-0xaa : 3CH FNUM1 */
+                    if (r < 0x100) {
+                        UINT32 fn = (((UINT32)(ym2612.OPN.SL3.fn_h & 7)) << 8) + v;
+                        UINT8 blk = ym2612.OPN.SL3.fn_h >> 3;
+                        /* keyscale code */
+                        ym2612.OPN.SL3.kcode[c] = (blk << 2) | opn_fktable[fn >> 7];
+                        /* phase increment counter */
+                        ym2612.OPN.SL3.fc[c] = ym2612.OPN.pfn_table[__fast_mul(fn, 2)] >> (7 - blk);
+                        ym2612.OPN.SL3.block_fnum[c] = (blk << 11) | fn;
+                        ym2612.CH[2].SLOT[SLOT1].Incr = -1;
+                    }
+                    break;
+                case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
+                    if (r < 0x100)
+                        ym2612.OPN.SL3.fn_h = v & 0x3f;
+                    break;
+            }
+            break;
+
+        case 0xb0:
+            switch (OPN_SLOT(r)) {
+                case 0: /* 0xb0-0xb2 : FB,ALGO */
+                {
+                    int feedback = (v >> 3) & 7;
+                    CH->ALGO = v & 7;
+                    CH->FB = feedback ? feedback + 6 : 0;
+                    setup_connection(CH, c);
+                    break;
+                }
+                case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (ym2612/YM2610B/YM2610/YM2608) */
+                    /* b0-2 PMS */
+                    CH->pms = __fast_mul(v & 7, 16); /* CH->pms = PM depth * 16 (index in lfo_pm_table) */
+
+                /* b4-5 AMS */
+                    CH->ams = lfo_ams_depth_shift[(v >> 4) & 0x03];
+
+                /* PAN :  b7 = L, b6 = R */
+                // ym2612.OPN.pan[ c*2   ] = (v & 0x80) ? ~0 : 0;
+                // ym2612.OPN.pan[ c*2+1 ] = (v & 0x40) ? ~0 : 0;
+                    break;
+            }
+            break;
+    }
+}
+
+
+/* initialize time tables */
+static void init_timetables(double freqbase) {
+    int i, d;
+    double rate;
+    ym2612.OPN.pfn_table = &fn_table[0];
+#if GENERATE_TABLES
+  /* DeTune table */
+  for (d = 0;d <= 3;d++)
+  {
+    for (i = 0;i <= 31;i++)
+    {
+      rate = ((double)dt_tab[d*32 + i]) * freqbase * (1<<(FREQ_SH-10)); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
+      ym2612_OPN_ST_dt_tab[d][i]   = (INT32) rate;
+      ym2612_OPN_ST_dt_tab[d+4][i] = -ym2612_OPN_ST_dt_tab[d][i];
+    }
+  }
+
+  /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
+      but LFO works with one more bit of a precision so we really need 4096 elements */
+  /* calculate fnumber -> increment counter table */
+  for(i = 0; i < 4096; i++)
+  {
+    /* freq table for octave 7 */
+    /* OPN phase increment counter = 20bit */
+    /* the correct formula is : F-Number = (144 * fnote * 2^20 / M) / 2^(B-1) */
+    /* where sample clock is  M/144 */
+    /* this means the increment value for one clock sample is FNUM * 2^(B-1) = FNUM * 64 for octave 7 */
+    /* we also need to handle the ratio between the chip frequency and the emulated frequency (can be 1.0)  */
+    ym2612.OPN.pfn_table[i] = (unsigned int)( (double)i * 32 * freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
+  }
+	FIL f;
+	UINT bw;
+	char tmp[64];
+	const char * str = "const unsigned int __in_flash() __aligned(4) fn_table[] = {\n";
+	f_open(&f, "\\fn_table.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+  sprintf(tmp, " // freqbase: %f\n", freqbase);
+	f_write(&f, tmp, strlen(tmp), &bw);
+	for(int i = 0; i < sizeof(fn_table) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", fn_table[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+  str = "const unsigned int __in_flash() __aligned(4) ym2612_OPN_ST_dt_tab[8][32] = {\n";
+	f_open(&f, "\\ym2612_OPN_ST_dt_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+  sprintf(tmp, " // freqbase: %f\n", freqbase);
+	f_write(&f, tmp, strlen(tmp), &bw);
+	for(int i = 0; i < 8; ++i) {
+	 if (i == 0) {
+			str = " {";
+	 } else {
+			str = ", {";
+	 }
+	 f_write(&f, str, strlen(str), &bw);
+   for(int j = 0; j < 32; ++j) {
+		if (j == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", ym2612_OPN_ST_dt_tab[i][j]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+   }
+   str = " },\n";
+	 f_write(&f, str, strlen(str), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+#endif
+    /* maximal frequency is required for Phase overflow calculation, register size is 17 bits (Nemesis) */
+    ym2612.OPN.fn_max = (UINT32)((double)0x20000 * freqbase * (1 << (FREQ_SH - 10)));
+}
+
+/* prescaler set (and make time tables) */
+static void OPNSetPres(int pres) {
+    /* frequency base (ratio between FM original samplerate & desired output samplerate)*/
+    double freqbase = ym2612.OPN.ST.clock / ym2612.OPN.ST.rate / pres;
+
+    //fcipaq
+    freqbase = GWENESIS_AUDIO_SAMPLING_DIVISOR; // override the above to prevent rounding error
+
+    /* YM2612 running at original frequency (~53267 Hz) */
+    //if (config.hq_fm) freqbase  = 1.0;
+
+    /* EG is updated every 3 samples */
+    ym2612.OPN.eg_timer_add = (UINT32)((1 << EG_SH) * freqbase);
+    ym2612.OPN.eg_timer_overflow = (3) * (1 << EG_SH);
+
+    /* LFO timer increment (every samples) */
+    ym2612.OPN.lfo_timer_add = (UINT32)((1 << LFO_SH) * freqbase);
+
+    /* Timers increment (every samples) */
+    ym2612.OPN.ST.TimerBase = (int)((1 << TIMER_SH) * freqbase);
+
+    /* make time tables */
+    init_timetables(freqbase);
+}
+
+static void reset_channels(FM_CH* CH, int num) {
+    int c, s;
+
+    for (c = 0; c < num; c++) {
+        CH[c].mem_value = 0;
+        CH[c].op1_out[0] = 0;
+        CH[c].op1_out[1] = 0;
+        for (s = 0; s < 4; s++) {
+            CH[c].SLOT[s].Incr = -1;
+            CH[c].SLOT[s].key = 0;
+            CH[c].SLOT[s].phase = 0;
+            CH[c].SLOT[s].ssgn = 0;
+            CH[c].SLOT[s].state = EG_OFF;
+            CH[c].SLOT[s].volume = MAX_ATT_INDEX;
+            CH[c].SLOT[s].vol_out = MAX_ATT_INDEX;
+        }
+    }
+}
+
+/* initialize generic tables */
+static void init_tables(void) {
+    signed int i, x, d;
+    signed int n;
+    double o, m;
+#if GENERATE_TABLES
+  /* build Linear Power Table */
+  for (x=0; x<TL_RES_LEN; x++)
+  {
+    m = (1<<16) / pow(2,(x+1) * (ENV_STEP/4.0) / 8.0);
+    m = floor(m);
+
+    /* we never reach (1<<16) here due to the (x+1) */
+    /* result fits within 16 bits at maximum */
+
+    n = (int)m; /* 16 bits here */
+    n >>= 4;    /* 12 bits here */
+    if (n&1)    /* round to nearest */
+      n = (n>>1)+1;
+    else
+      n = n>>1;
+                /* 11 bits here (rounded) */
+    n <<= 2;    /* 13 bits here (as in real chip) */
+
+    /* 14 bits (with sign bit) */
+    tl_tab[ x*2 + 0 ] = n;
+    tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
+
+    /* one entry in the 'Power' table use the following format, xxxxxyyyyyyyys with:            */
+    /*        s = sign bit                                                                      */
+    /* yyyyyyyy = 8-bits decimal part (0-TL_RES_LEN)                                            */
+    /* xxxxx    = 5-bits integer 'shift' value (0-31) but, since Power table output is 13 bits, */
+    /*            any value above 13 (included) would be discarded.                             */
+    for (i=1; i<13; i++)
+    {
+      tl_tab[ x*2+0 + i*2*TL_RES_LEN ] =  (tl_tab[ x*2+0 ]>>i);
+      tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
+    }
+  }
+
+  /* build Logarithmic Sinus table */
+  for (i=0; i<SIN_LEN; i++)
+  {
+    /* non-standard sinus */
+    m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
+    /* we never reach zero here due to ((i*2)+1) */
+
+    if (m>0.0)
+      o = 8*log(1.0/m)/log(2);  /* convert to 'decibels' */
+    else
+      o = 8*log(-1.0/m)/log(2);  /* convert to 'decibels' */
+
+    o = o / (ENV_STEP/4);
+
+    n = (int)(2.0*o);
+    if (n&1)            /* round to nearest */
+      n = (n>>1)+1;
+    else
+      n = n>>1;
+
+    /* 13-bits (8.5) value is formatted for above 'Power' table */
+    sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
+  }
+
+  /* build LFO PM modulation table */
+  for(i = 0; i < 8; i++) /* 8 PM depths */
+  {
+    UINT8 fnum;
+    for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
+    {
+      UINT8 value;
+      UINT8 step;
+      UINT32 offset_depth = i;
+      UINT32 offset_fnum_bit;
+      UINT32 bit_tmp;
+
+      for (step=0; step<8; step++)
+      {
+        value = 0;
+        for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
+        {
+          if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
+          {
+            offset_fnum_bit = bit_tmp * 8;
+            value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
+          }
+        }
+        /* 16 steps for LFO PM (sinus) */
+        lfo_pm_table[(fnum * 16 * 8) + (i * 16) + step + 0] = value;
+        lfo_pm_table[(fnum * 16 * 8) + (i * 16) + (step ^ 7) + 8] = value;
+      }
+    }
+  }
+  /* build DETUNE table */
+  for (d = 0;d <= 3;d++)
+  {
+    for (i = 0;i <= 31;i++)
+    {
+      ym2612_OPN_ST_dt_tab[d][i]   = (INT32) dt_tab[d*32 + i];
+      ym2612_OPN_ST_dt_tab[d+4][i] = -ym2612_OPN_ST_dt_tab[d][i];
+    }
+  }
+	FIL f;
+	UINT bw;
+	char tmp[64];
+	const char * str = "const unsigned char __in_flash() __aligned(4) lfo_pm_table[] = {\n";
+	f_open(&f, "\\lfo_pm_table.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(lfo_pm_table); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", i - 16);
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "0x%02X", (unsigned char)lfo_pm_table[i] & 0xFF);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+	str = "const signed int __in_flash() __aligned(4) tl_tab[] = {\n";
+	f_open(&f, "\\tl_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(tl_tab) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", tl_tab[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+	str = "const unsigned int __in_flash() __aligned(4) sin_tab[] = {\n";
+	f_open(&f, "\\sin_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(sin_tab) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", sin_tab[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+#endif
+}
+
+/* initialize ym2612 emulator(s) */
+void YM2612Init() {
+    memset(&ym2612, 0, sizeof(YM2612));
+    ym2612.OPN.pfn_table = fn_table;
+    init_tables();
+    ym2612.OPN.ST.clock = GWENESIS_AUDIO_FREQ_NTSC;
+    ym2612.OPN.ST.rate = GWENESIS_AUDIO_FREQ_NTSC / (6 * 24) / GWENESIS_AUDIO_SAMPLING_DIVISOR;
+    OPNSetPres(6 * 24);
+    /* YM2612 prescaler is fixed to 1/6, one sample (6 mixed channels) is output for each 24 FM clocks */
+}
+
+/* reset OPN registers */
+void YM2612ResetChip(void) {
+    int i;
+
+    ym2612.OPN.eg_timer = 0;
+    ym2612.OPN.eg_cnt = 0;
+
+    ym2612.OPN.lfo_timer_overflow = 0;
+    ym2612.OPN.lfo_timer = 0;
+    ym2612.OPN.lfo_cnt = 0;
+    ym2612.OPN.LFO_AM = 0;
+    ym2612.OPN.LFO_PM = 0;
+
+    ym2612.OPN.ST.TAC = 0;
+    ym2612.OPN.ST.TBC = 0;
+
+    ym2612.OPN.SL3.key_csm = 0;
+
+    ym2612.dacen = 0;
+    ym2612.dacout = 0;
+
+    set_timers(0x30);
+    ym2612.OPN.ST.TB = 0;
+    ym2612.OPN.ST.TBL = 256 << (TIMER_SH + 4);
+    ym2612.OPN.ST.TA = 0;
+    ym2612.OPN.ST.TAL = 1024 << TIMER_SH;
+
+    reset_channels(&ym2612.CH[0], 6);
+
+    for (i = 0xb6; i >= 0xb4; i--) {
+        OPNWriteReg(i, 0xc0);
+        OPNWriteReg(i | 0x100, 0xc0);
+    }
+    for (i = 0xb2; i >= 0x30; i--) {
+        OPNWriteReg(i, 0);
+        OPNWriteReg(i | 0x100, 0);
+    }
+}
+
+/* ym2612 write */
+/* n = number  */
+/* a = address */
+/* v = value   */
+void YM2612Write(unsigned int a, unsigned int v, int target) {
+    //Sync
+    if (snd_accurate == 1)
+        ym2612_run(target);
+
+    v &= 0xff; /* adjust to 8 bit bus */
+
+    switch (a) {
+        case 0: /* address port 0 */
+            ym2612.OPN.ST.address = v;
+            break;
+
+        case 2: /* address port 1 */
+            ym2612.OPN.ST.address = v | 0x100;
+            break;
+
+        default: /* data port */
+        {
+            int addr = ym2612.OPN.ST.address; /* verified by Nemesis on real YM2612 */
+            switch (addr & 0x1f0) {
+                case 0x20: /* 0x20-0x2f Mode */
+                    switch (addr) {
+                        case 0x2a: /* DAC data (ym2612) */
+                            ym2612.dacout = ((int)v - 0x80) << 6; /* level unknown (5 is too low, 8 is too loud) */
+                            break;
+                        case 0x2b: /* DAC Sel  (ym2612) */
+                            /* b7 = dac enable */
+                            ym2612.dacen = v & 0x80;
+                            break;
+                        default: /* OPN section */
+                            /* write register */
+                            OPNWriteMode(addr, v);
+                    }
+                    break;
+                default: /* 0x30-0xff OPN section */
+                    /* write register */
+                    OPNWriteReg(addr, v);
+            }
+            break;
+        }
+    }
+}
+
+unsigned int YM2612Read(int target) {
+    // //Sync
+    if (snd_accurate == 1)
+        ym2612_run(target);
+
+    return ym2612.OPN.ST.status & 0xff;
+}
+
+extern bool sn76489_enabled;
+
+/* Generate samples for ym2612 */
+void YM2612Update(int16_t* buffer, int length) {
+    int i;
+    int lt;
+
+    /* refresh PG increments and EG rates if required */
+    refresh_fc_eg_chan(&ym2612.CH[0]);
+    refresh_fc_eg_chan(&ym2612.CH[1]);
+
+    if (!(ym2612.OPN.ST.mode & 0xC0)) {
+        refresh_fc_eg_chan(&ym2612.CH[2]);
+    }
+    else {
+        /* 3SLOT MODE (operator order is 0,1,3,2) */
+        if (ym2612.CH[2].SLOT[SLOT1].Incr == -1) {
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT1], ym2612.OPN.SL3.fc[1], ym2612.OPN.SL3.kcode[1]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT2], ym2612.OPN.SL3.fc[2], ym2612.OPN.SL3.kcode[2]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT3], ym2612.OPN.SL3.fc[0], ym2612.OPN.SL3.kcode[0]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT4], ym2612.CH[2].fc, ym2612.CH[2].kcode);
+        }
+    }
+
+    refresh_fc_eg_chan(&ym2612.CH[3]);
+    refresh_fc_eg_chan(&ym2612.CH[4]);
+    refresh_fc_eg_chan(&ym2612.CH[5]);
+    bool inc_mode = sn76489_enabled;
+    /* buffering */
+    for (i = 0; i < length; i++) {
+        /* clear outputs */
+        out_fm[0] = 0;
+        out_fm[1] = 0;
+        out_fm[2] = 0;
+        out_fm[3] = 0;
+        out_fm[4] = 0;
+        out_fm[5] = 0;
+
+        /* update SSG-EG output */
+        update_ssg_eg_channel(&ym2612.CH[0].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[1].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[2].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[3].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[4].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[5].SLOT[SLOT1]);
+
+        /* calculate FM */
+        chan_calc(&ym2612.CH[0]);
+        chan_calc(&ym2612.CH[1]);
+        chan_calc(&ym2612.CH[2]);
+        chan_calc(&ym2612.CH[3]);
+        chan_calc(&ym2612.CH[4]);
+        if (!ym2612.dacen) {
+            chan_calc(&ym2612.CH[5]);
+        }
+        else {
+            /* DAC Mode */
+            out_fm[5] = ym2612.dacout;
+        }
+
+        /* advance LFO */
+        advance_lfo();
+
+        /* advance envelope generator */
+        ym2612.OPN.eg_timer += ym2612.OPN.eg_timer_add;
+        while (ym2612.OPN.eg_timer >= ym2612.OPN.eg_timer_overflow) {
+            ym2612.OPN.eg_timer -= ym2612.OPN.eg_timer_overflow;
+            ym2612.OPN.eg_cnt++;
+            advance_eg_channels();
+        }
+
+        /* 14-bit DAC inputs (range is -8192;+8191) */
+        if (out_fm[0] > 8192) out_fm[0] = 8191;
+        else if (out_fm[0] < -8192) out_fm[0] = -8192;
+        if (out_fm[1] > 8192) out_fm[1] = 8191;
+        else if (out_fm[1] < -8192) out_fm[1] = -8192;
+        if (out_fm[2] > 8192) out_fm[2] = 8191;
+        else if (out_fm[2] < -8192) out_fm[2] = -8192;
+        if (out_fm[3] > 8192) out_fm[3] = 8191;
+        else if (out_fm[3] < -8192) out_fm[3] = -8192;
+        if (out_fm[4] > 8192) out_fm[4] = 8191;
+        else if (out_fm[4] < -8192) out_fm[4] = -8192;
+        if (out_fm[5] > 8192) out_fm[5] = 8191;
+        else if (out_fm[5] < -8192) out_fm[5] = -8192;
+
+        /* 6-channels mono only  */
+        lt = out_fm[0];
+        lt += out_fm[1];
+        lt += out_fm[2];
+        lt += out_fm[3];
+        lt += out_fm[4];
+        lt += out_fm[5];
+
+        /* buffering */
+        if (inc_mode) *buffer++ += lt;
+        else *buffer++ = lt;
+        // *buffer++ += lt / (2 << (11 - snd_output_volume));
+
+        /* CSM mode: if CSM Key ON has occured, CSM Key OFF need to be sent       */
+        /* only if Timer A does not overflow again (i.e CSM Key ON not set again) */
+        ym2612.OPN.SL3.key_csm <<= 1;
+
+        /* timer A control */
+        INTERNAL_TIMER_A();
+
+        /* CSM Mode Key ON still disabled */
+        if (ym2612.OPN.SL3.key_csm & 2) {
+            /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
+            ym2612.OPN.SL3.key_csm = 0;
+        }
+    }
+
+    /* timer B control */
+    INTERNAL_TIMER_B(length);
+}
+
+void ym2612_run(int target) {
+    /**
+      if ( ym2612_clock >= target) {
+        return;
+      }
+
+      target /= GWENESIS_AUDIO_SAMPLING_DIVISOR;
+
+      int ym2612_prev_index = ym2612_index;
+      ym2612_index += (target-ym2612_clock) / ym2612.divisor;
+      if (ym2612_index > ym2612_prev_index) {
+        YM2612Update(gwenesis_sn76489_buffer + ym2612_prev_index, ym2612_index - ym2612_prev_index);
+        ym2612_clock = ym2612_index*ym2612.divisor;
+
+      } else {
+        ym2612_index = ym2612_prev_index;
+      }*/
+}
+
+unsigned char* YM2612GetContextPtr(void) {
+    return (unsigned char *)&ym2612;
+}
+
+unsigned int YM2612GetContextSize(void) {
+    return sizeof(YM2612);
+}
+
+void YM2612Restore(unsigned char* buffer) {
+    /* save current timings */
+    double clock = ym2612.OPN.ST.clock;
+    int rate = ym2612.OPN.ST.rate;
+
+    /* restore internal state */
+    memcpy(&ym2612, buffer, sizeof(YM2612));
+
+    /* keep current timings */
+    ym2612.OPN.ST.clock = clock;
+    ym2612.OPN.ST.rate = rate;
+    OPNSetPres(6 * 24);
+
+    /* restore outputs connections */
+    setup_connection(&ym2612.CH[0], 0);
+    setup_connection(&ym2612.CH[1], 1);
+    setup_connection(&ym2612.CH[2], 2);
+    setup_connection(&ym2612.CH[3], 3);
+    setup_connection(&ym2612.CH[4], 4);
+    setup_connection(&ym2612.CH[5], 5);
+
+    /* restore TL table (DAC resolution might have been modified) */
+    init_tables();
+}
+
+void YM2612Config(unsigned char dac_bits) //,unsigned int AUDIO_FREQ_DIVISOR)
+{
+    int i;
+
+    /* DAC precision (normally 9-bit on real hardware, implemented through simple 14-bit channel output bitmasking) */
+    bitmask = ~((1 << (TL_BITS - dac_bits)) - 1);
+
+    /* update L/R panning bitmasks */
+    for (i = 0; i < 2 * 6; i++) {
+        if (ym2612.OPN.pan[i]) {
+            ym2612.OPN.pan[i] = bitmask;
+        }
+    }
+    ym2612.divisor = AUDIO_FREQ_DIVISOR;
+}
+
+void YM2612SaveRegs(uint8_t* regs) {
+    memcpy(regs, OPNREGS, sizeof(OPNREGS));
+}
+
+void YM2612LoadRegs(uint8_t* regs) {
+    int i;
+    for (i = 0; i < sizeof(OPNREGS); ++i) {
+        if (i <= 0x30)
+            OPNWriteMode(i, *regs++);
+        else
+            OPNWriteReg(i, *regs++);
+    }
+
+    /* restore outputs connections */
+    setup_connection(&ym2612.CH[0], 0);
+    setup_connection(&ym2612.CH[1], 1);
+    setup_connection(&ym2612.CH[2], 2);
+    setup_connection(&ym2612.CH[3], 3);
+    setup_connection(&ym2612.CH[4], 4);
+    setup_connection(&ym2612.CH[5], 5);
+}
+
+#if 0
+int YM2612LoadContext(unsigned char *state)
+{
+  int c,s;
+  uint8 index;
+  int bufferptr = sizeof(YM2612);
+
+  /* restore YM2612 context */
+  YM2612Restore(state);
+
+  /* restore DT table address pointer for each channel slots */
+  for( c = 0 ; c < 6 ; c++ )
+  {
+    for(s = 0 ; s < 4 ; s++ )
+    {
+      load_param(&index,sizeof(index));
+      bufferptr += sizeof(index);
+      ym2612.CH[c].SLOT[s].DT = ym2612.OPN.ST.dt_tab[index&7];
+    }
+  }
+
+  return bufferptr;
+}
+
+int YM2612SaveContext(unsigned char *state)
+{
+  int c,s;
+  uint8 index;
+  int bufferptr = sizeof(YM2612);
+
+  /* save YM2612 context */
+  memcpy(state, &ym2612, sizeof(YM2612));
+
+  /* save DT table index for each channel slots */
+  for( c = 0 ; c < 6 ; c++ )
+  {
+    for(s = 0 ; s < 4 ; s++ )
+    {
+      index = (ym2612.CH[c].SLOT[s].DT - ym2612.OPN.ST.dt_tab[0]) >> 5;
+      save_param(&index,sizeof(index));
+      bufferptr += sizeof(index);
+    }
+  }
+
+  return bufferptr;
+}
+#endif
+
+void gwenesis_ym2612_save_state() {
+}
+
+void gwenesis_ym2612_load_state() {
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/ym2612.h b/MCUME_pico2/picogen/_gwenesis/sound/ym2612.h
new file mode 100755
index 0000000..e65576b
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/ym2612.h
@@ -0,0 +1,44 @@
+/*
+**
+** software implementation of Yamaha FM sound generator (YM2612/YM3438)
+**
+** Original code (MAME fm.c)
+**
+** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
+** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
+**
+** Version 1.4 (final beta)
+**
+** Additional code & fixes by Eke-Eke for Genesis Plus GX
+**
+*/
+
+#ifndef _H_YM2612_
+#define _H_YM2612_
+
+extern int16_t gwenesis_sn76489_buffer[];
+///extern int ym2612_index;
+///extern int ym2612_clock;
+
+extern int snd_output_volume;
+
+extern void YM2612Init();
+extern void YM2612Config(unsigned char dac_bits); //,unsigned int AUDIO_FREQ_DIVISOR);
+extern void YM2612ResetChip(void);
+//extern void YM2612Update(int16_t *buffer, int length);
+extern void YM2612Write(unsigned int a, unsigned int v,  int target);
+extern void ym2612_run(int target);
+extern unsigned int YM2612Read(int target);
+
+#if 0
+extern int YM2612LoadContext(unsigned char *state);
+extern int YM2612SaveContext(unsigned char *state);
+#endif
+
+//extern void YM2612LoadRegs(uint8_t *regs);
+//extern void YM2612SaveRegs(uint8_t *regs);
+
+void gwenesis_ym2612_save_state();
+void gwenesis_ym2612_load_state();
+
+#endif /* _YM2612_ */
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/ym2612_OPN_ST_dt_tab.h b/MCUME_pico2/picogen/_gwenesis/sound/ym2612_OPN_ST_dt_tab.h
new file mode 100755
index 0000000..f833655
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/ym2612_OPN_ST_dt_tab.h
@@ -0,0 +1,11 @@
+const unsigned int __in_flash() __aligned(4) ym2612_OPN_ST_dt_tab[8][32] = {
+ // freqbase: 6.000000
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 384, 384, 384, 384, 384, 384, 384, 384, 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3072, 3072 },
+ { 384, 384, 384, 384, 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3456, 3840, 4224, 4608, 4992, 5376, 6144, 6144, 6144, 6144 },
+ { 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3456, 3840, 4224, 4608, 4992, 5376, 6144, 6528, 7296, 7680, 8448, 8448, 8448, 8448 },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, -384, -384, -384, -384, -384, -384, -384, -384, -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3072, -3072 },
+ { -384, -384, -384, -384, -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3456, -3840, -4224, -4608, -4992, -5376, -6144, -6144, -6144, -6144 },
+ { -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3456, -3840, -4224, -4608, -4992, -5376, -6144, -6528, -7296, -7680, -8448, -8448, -8448, -8448 }
+};
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/z80inst.c b/MCUME_pico2/picogen/_gwenesis/sound/z80inst.c
new file mode 100755
index 0000000..454faa3
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/z80inst.c
@@ -0,0 +1,342 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stdio.h>
+#include <stdint.h>
+#include <assert.h>
+#include "../cpus/Z80/Z80.h"
+#include "z80inst.h"
+#include "../cpus/M68K/m68k.h"
+#include "../bus/gwenesis_bus.h"
+// #include "ym2612.h"
+#include "gwenesis_sn76489.h"
+#include "ym2612.h"
+#include "../savestate/gwenesis_savestate.h"
+
+static int bus_ack = 0;
+static int reset = 0;
+static int reset_once = 0;
+int zclk = 0;
+static int initialized = 0;
+
+extern int audio_enabled;
+extern bool sound_enabled;
+
+unsigned char *Z80_RAM;
+
+static Z80 cpu;
+
+void ResetZ80(register Z80 *R);
+
+#define Z80_INST_DISABLE_LOGGING 1
+
+#if !Z80_INST_DISABLE_LOGGING
+#include <stdarg.h>
+void z80_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s]", frame_counter, scan_line, subs);
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+	#define z80_log(...)  do {} while(0)
+#endif
+
+// Bank register used by Z80 to access M68K Memory space 1 BANK=32KByte
+int Z80_BANK;
+
+
+void z80_start() {
+    cpu.IPeriod = 1;
+    cpu.ICount = 0;
+    cpu.Trace = 0;
+    cpu.Trap = 0x0009;
+    ResetZ80(&cpu);
+    reset=1;
+    reset_once=0;
+    bus_ack=0;
+    zclk=0;
+}
+
+void z80_pulse_reset() {
+  ResetZ80(&cpu);
+}
+static int current_timeslice = 0;
+
+void z80_run(int target) {
+
+  // we are in advance,nothind to do
+current_timeslice = 0;
+  if (zclk >= target) {
+ // z80_log("z80_skip time","%1d%1d%1d||zclk=%d,tgt=%d",reset_once,bus_ack,reset, zclk, target);
+    return;
+  }
+
+  current_timeslice = target - zclk;
+
+  int rem = 0;
+  if ((reset_once == 1) && (bus_ack == 0) && (reset == 0)) {
+
+   // z80_log("z80_run", "%1d%1d%1d||zclk=%d,tgt=%d",reset_once, bus_ack, reset, zclk, target);
+    rem = ExecZ80(&cpu, current_timeslice / Z80_FREQ_DIVISOR);
+
+  }
+
+  zclk = target - rem * Z80_FREQ_DIVISOR;
+}
+
+void z80_sync(void) {
+  /*
+  get M68K cycles 
+  Execute cycles on z80 to sync with m68K
+  */
+
+  z80_run(m68k_cycles_master());
+}
+
+void z80_set_memory(unsigned char *buffer)
+{
+    Z80_RAM = buffer;
+    initialized = 1;
+}
+
+void z80_write_ctrl(unsigned int address, unsigned int value) {
+  z80_sync();
+
+  if (address == 0x1100) // BUSREQ
+  {
+    z80_log(__FUNCTION__,"BUSREQ = %d, current=%d", value,bus_ack);
+
+    // Bus request. Z80 bus on hold.
+    if (value) {
+      bus_ack = 1;
+
+
+    // Bus request cancel. Z80 runs.
+    } else {
+            bus_ack = 0;
+    }
+
+  } else if (address == 0x1200) // RESET
+  {
+    z80_log(__FUNCTION__,"RESET = %d, current=%d", value,reset);
+  
+    if (value == 0) {
+      reset = 1;
+    } else {
+
+      z80_pulse_reset();
+      reset = 0;
+      reset_once = 1;
+    }
+  }
+}
+
+unsigned int z80_read_ctrl(unsigned int address) {
+
+  z80_sync();
+
+  if (address == 0x1100) {
+
+    z80_log(__FUNCTION__,"RUNNING = %d ", bus_ack ? 0 : 1);
+    return bus_ack == 1 ? 0 : 1;
+
+  } else if (address == 0x1101) {
+    return 0x00;
+
+  } else if (address == 0x1200) {
+
+    z80_log(__FUNCTION__,"RESET = %d ", reset );
+    return reset;
+
+  } else if (address == 0x1201) {
+    return 0x00;
+  }
+  return 0xFF;
+}
+
+void z80_irq_line(unsigned int value)
+{
+    if (reset_once == 0) return;
+
+    if (value)
+        cpu.IRequest = INT_IRQ;
+    else
+        cpu.IRequest = INT_NONE;
+
+    z80_log(__FUNCTION__,"Interrupt = %d ", value);
+
+}
+
+#if 0
+
+word z80_get_reg(int reg_i) {
+    switch(reg_i) {
+        case 0: return cpu.AF.W; break;
+        case 1: return cpu.BC.W; break;
+        case 2: return cpu.DE.W; break;
+        case 3: return cpu.HL.W; break;
+        case 4: return cpu.IX.W; break;
+        case 5: return cpu.IY.W; break;
+        case 6: return cpu.PC.W; break;
+        case 7: return cpu.SP.W; break;
+    }
+}
+#endif
+
+/********************************************
+ * Z80 Bank
+ ********************************************/
+
+unsigned int zbankreg_mem_r8(unsigned int address)
+{
+      z80_log(__FUNCTION__,"Z80 bank read pointer : %06x", Z80_BANK);
+
+    return Z80_BANK;
+}
+
+static inline void zbankreg_mem_w8(unsigned int value) {
+  Z80_BANK >>= 1;
+  Z80_BANK |= (value & 1) << 8;
+  z80_log(__FUNCTION__,"Z80 bank points to: %06x", Z80_BANK << 15);
+  return;
+}
+
+static inline unsigned int zbank_mem_r8(unsigned int address)
+{
+    address &= 0x7FFF;
+    address |= (Z80_BANK << 15);
+
+    z80_log(__FUNCTION__,"Z80 bank read: %06x", address);
+    return m68k_read_memory_8(address);
+}
+
+static inline void zbank_mem_w8(unsigned int address, unsigned int value) {
+  address &= 0x7FFF;
+  address |= (Z80_BANK << 15);
+
+  z80_log(__FUNCTION__,"Z80 bank write %06x: %02x", address, value);
+  m68k_write_memory_8(address, value);
+
+}
+
+// TODO ??
+/*
+unsigned int zvdp_mem_r8(unsigned int address)
+{
+    if (address >= 0x7F00 && address < 0x7F20)
+        return vdp_mem_r8(address);
+    return 0xFF;
+}
+
+void zvdp_mem_w8(unsigned int address, unsigned int value)
+{
+    if (address >= 0x7F00 && address < 0x7F20)
+        vdp_mem_w8(address, value);
+}
+
+*/
+
+word LoopZ80(register Z80 *R)
+{
+    return 0;
+}
+
+byte RdZ80(register word Addr) {
+
+  if (Addr < 0x4000)
+    return Z80_RAM[Addr & 0x1FFF];
+
+  if (Addr < 0x6000)
+	   return (audio_enabled) ? YM2612Read(zclk + current_timeslice - (cpu.ICount * Z80_FREQ_DIVISOR)) : 0x00;
+
+  z80_log(__FUNCTION__, "addr= %x", Addr);
+
+  if (Addr >= 0x8000)
+    return zbank_mem_r8(Addr);
+
+  z80_log(__FUNCTION__, "addr= %x", Addr);
+
+  return 0xFF;
+}
+
+extern int system_clock;
+
+void WrZ80(register word Addr, register byte Value) {
+
+  // ZRAM & mirror
+  if (Addr < 0x4000) {
+    Z80_RAM[Addr&0x1FFF] = Value;
+    return;
+  }
+
+  // @4000-4003
+  if (Addr < 0x6000) {
+    z80_log("Z80","ZZYM(%x,%x) zk=%d,tgt=%d",Addr&0x3,Value, zclk, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    if (audio_enabled)
+	    YM2612Write(Addr&0x3, Value, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    return;
+  }
+
+  // @6000
+  if (Addr == 0x6000) {
+    zbankreg_mem_w8(Value);
+    return;
+  }
+
+  // @7F11
+  if (Addr ==  0x7F11) {
+    z80_log("Z80","ZZSN zk=%d,tgt=%d", zclk, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    gwenesis_SN76489_Write(Value,zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    return;
+  }
+ 
+  z80_log("Z80","WrZ80  %x %x", Addr, Value);
+
+  if (Addr >= 0x8000) {
+    zbank_mem_w8(Addr, Value);
+    return;
+  }
+  z80_log("Z80","WrZ80  %x %x", Addr, Value);
+
+}
+
+
+byte InZ80(register word Port) {return 0;}
+void OutZ80(register word Port, register byte Value) {;}
+void PatchZ80(register Z80 *R) {;}
+void DebugZ80(register Z80 *R) {;}
+
+void gwenesis_z80inst_save_state() {
+
+}
+
+void gwenesis_z80inst_load_state() {
+
+
+}
+
diff --git a/MCUME_pico2/picogen/_gwenesis/sound/z80inst.h b/MCUME_pico2/picogen/_gwenesis/sound/z80inst.h
new file mode 100755
index 0000000..b891394
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/sound/z80inst.h
@@ -0,0 +1,44 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _Z80_INTERFACE_H_
+#define _Z80_INTERFACE_H_
+
+void z80_write_ctrl(unsigned int address, unsigned int value);
+unsigned int z80_read_ctrl(unsigned int address);
+void z80_start();
+void z80_pulse_reset();
+void z80_execute(unsigned int target);
+void z80_run(int target);
+extern int zclk;
+
+void gwenesis_z80inst_save_state();
+void gwenesis_z80inst_load_state();
+
+void z80_set_memory(unsigned char *buffer);
+
+void z80_write_memory_8(unsigned int address, unsigned int value);
+void z80_write_memory_16(unsigned int address, unsigned int value);
+unsigned int z80_read_memory_16(unsigned int address);
+unsigned int z80_read_memory_8(unsigned int address);
+void z80_irq_line(unsigned int value);
+
+void gwenesis_z80inst_save_state();
+void gwenesis_z80inst_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp.h b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp.h
new file mode 100755
index 0000000..e24bb28
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp.h
@@ -0,0 +1,154 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_vdp_H_
+#define _gwenesis_vdp_H_
+
+#pragma once
+
+#define BIT(v, idx) (((v) >> (idx)) & 1)
+#define BITS(v, idx, n) (((v) >> (idx)) & ((1 << (n)) - 1))
+
+// VDP registers
+#define REG0_DISABLE_DISPLAY (gwenesis_vdp_regs[0] & 1)
+#define REG0_HVLATCH BIT(gwenesis_vdp_regs[0], 1)
+#define REG0_LINE_INTERRUPT BIT(gwenesis_vdp_regs[0], 4)
+#define REG1_PAL BIT(gwenesis_vdp_regs[1], 3)
+#define REG1_240_LINE ((gwenesis_vdp_regs[1] & 0x08) >> 3)
+#define REG1_DMA_ENABLED BIT(gwenesis_vdp_regs[1], 4)
+#define REG1_VBLANK_INTERRUPT BIT(gwenesis_vdp_regs[1], 5)
+#define REG1_DISP_ENABLED BIT(gwenesis_vdp_regs[1], 6)
+#define REG2_NAMETABLE_A (BITS(gwenesis_vdp_regs[2], 3, 3) << 13)
+#define REG3_NAMETABLE_W BITS(gwenesis_vdp_regs[3], 1, 5)
+#define REG4_NAMETABLE_B (BITS(gwenesis_vdp_regs[4], 0, 3) << 13)
+//#define REG5_SAT_ADDRESS ((gwenesis_vdp_regs[5] & (mode_h40 ? 0x7E : 0x7F)) << 9)
+//#define REG5_SAT_SIZE (mode_h40 ? (1 << 10) : (1 << 9))
+#define REG5_SAT_ADDRESS ((gwenesis_vdp_regs[5] & ((gwenesis_vdp_regs[12] & 0x01) ? 0x7E : 0x7F)) << 9)
+#define REG5_SAT_SIZE ((gwenesis_vdp_regs[12] & 0x01) ? (1 << 10) : (1 << 9))
+#define REG10_LINE_COUNTER BITS(gwenesis_vdp_regs[10], 0, 8)
+#define REG10_COLUMN_COUNTER BITS(gwenesis_vdp_regs[10], 8, 15)
+#define REG11_HSCROLL_MODE ((gwenesis_vdp_regs[11] & 3))
+#define REG11_VSCROLL_MODE ((gwenesis_vdp_regs[11] & 4) >> 2)
+#define REG12_RS0 (gwenesis_vdp_regs[12] & 0x80) >> 7
+#define REG12_RS1 (gwenesis_vdp_regs[12] & 0x01) >> 0
+#define REG12_MODE_H40 (gwenesis_vdp_regs[12] & 1)
+#define REG13_HSCROLL_ADDRESS (gwenesis_vdp_regs[13] << 10)
+#define REG15_DMA_INCREMENT gwenesis_vdp_regs[15]
+#define REG16_UNUSED1 ((gwenesis_vdp_regs[16] & 0xc0) >> 6)
+#define REG16_VSCROLL_SIZE ((gwenesis_vdp_regs[16] >> 4) & 3)
+#define REG16_UNUSED2 ((gwenesis_vdp_regs[16] & 0x0c) >> 2)
+#define REG16_HSCROLL_SIZE (gwenesis_vdp_regs[16] & 3)
+#define REG17_WINDOW_HPOS BITS(gwenesis_vdp_regs[17], 0, 5)
+#define REG17_WINDOW_RIGHT ((gwenesis_vdp_regs[17] & 0x80) >> 7)
+#define REG18_WINDOW_DOWN ((gwenesis_vdp_regs[0x12] & 0x80) >> 7)
+#define REG18_WINDOW_VPOS BITS(gwenesis_vdp_regs[18], 0, 5)
+#define REG19_DMA_LENGTH (gwenesis_vdp_regs[19] | (gwenesis_vdp_regs[20] << 8))
+#define REG21_DMA_SRCADDR_LOW (gwenesis_vdp_regs[21] | (gwenesis_vdp_regs[22] << 8))
+#define REG23_DMA_SRCADDR_HIGH ((gwenesis_vdp_regs[23] & 0x7F) << 16)
+#define REG23_DMA_TYPE BITS(gwenesis_vdp_regs[23], 6, 2)
+
+//VDP status register
+#define STATUS_FIFO_EMPTY (1 << 9)
+#define STATUS_FIFO_FULL (1 << 8)
+#define STATUS_VIRQPENDING (1 << 7)
+#define STATUS_SPRITEOVERFLOW (1 << 6)
+#define STATUS_SPRITECOLLISION (1 << 5)
+#define STATUS_ODDFRAME (1 << 4)
+#define STATUS_VBLANK (1 << 3)
+#define STATUS_HBLANK (1 << 2)
+#define STATUS_DMAPROGRESS (1 << 1)
+#define STATUS_PAL (1 << 0)
+
+#define VRAM_MAX_SIZE 0x10000    // VRAM maximum size
+#define CRAM_MAX_SIZE 0x40       // CRAM maximum size
+#define VSRAM_MAX_SIZE 0x40      // VSRAM maximum size
+#define SAT_CACHE_MAX_SIZE 0x400 // SAT CACHE maximum size
+#define REG_SIZE 0x20            // REGISTERS total
+#define FIFO_SIZE 0x4            // FIFO maximum size
+
+#define COLOR_3B_TO_8B(c)  (((c) << 5) | ((c) << 2) | ((c) >> 1))
+#define CRAM_R(c)          COLOR_3B_TO_8B(BITS((c), 1, 3))
+#define CRAM_G(c)          COLOR_3B_TO_8B(BITS((c), 5, 3))
+#define CRAM_B(c)          COLOR_3B_TO_8B(BITS((c), 9, 3))
+
+#define MODE_SHI           BITS(gwenesis_vdp_regs[12], 3, 1)
+
+#define SHADOW_COLOR(r,g,b) \
+    do { r >>= 1; g >>= 1; b >>= 1; } while (0)
+#define HIGHLIGHT_COLOR(r,g,b) \
+    do { SHADOW_COLOR(r,g,b); r |= 0x80; g |= 0x80; b |= 0x80; } while(0)
+
+// While we draw the planes, we use bit 0x80 on each pixel to save the
+// high-priority flag, so that we can later prioritize.
+#define PIXATTR_HIPRI        0x80
+#define PIXATTR_LOWPRI       0x00
+#define PIXATTR_SPRITE       0x40
+#define PIXATTR_SPRITE_HIPRI 0xC0
+
+
+// After mixing code, we use free bits 0x80 and 0x40 to indicate the
+// shadow/highlight effect to apply on each pixel. Notice that we use
+// 0x80 to indicate normal drawing and 0x00 to indicate shadowing,
+// which does match exactly the semantic of PIXATTR_HIPRI. This simplifies
+// mixing code quite a bit.
+#define SHI_NORMAL(x)        ((x) | 0x80)
+#define SHI_HIGHLIGHT(x)     ((x) | 0x40)
+#define SHI_SHADOW(x)        ((x) & 0x3F)
+
+#define SHI_IS_SHADOW(x)     (!((x) & 0x80))
+#define SHI_IS_HIGHLIGHT(x)  ((x) & 0x40)
+
+void gwenesis_vdp_reset();
+void gwenesis_vdp_set_hblank();
+void gwenesis_vdp_clear_hblank();
+void gwenesis_vdp_set_vblank();
+void gwenesis_vdp_clear_vblank();
+
+unsigned int gwenesis_vdp_get_reg(int reg);
+void gwenesis_vdp_set_reg(int reg, unsigned char value);
+
+unsigned int gwenesis_vdp_read_memory_8(unsigned int address);
+unsigned int gwenesis_vdp_read_memory_16(unsigned int address);
+
+void gwenesis_vdp_write_memory_8(unsigned int address, unsigned int value);
+void gwenesis_vdp_write_memory_16(unsigned int address, unsigned int value);
+
+void gwenesis_vdp_set_buffers(unsigned char *screen_buffer, unsigned char *scaled_buffer);
+void gwenesis_vdp_set_buffer(uint8_t *ptr_screen_buffer);
+void gwenesis_vdp_get_buffer(uint16_t** ptr_screen_buffer);
+void gwenesis_vdp_render_line(int line);
+
+void gwenesis_vdp_render_config();
+
+unsigned int gwenesis_vdp_get_status();
+void gwenesis_vdp_get_debug_status(char *s);
+unsigned short gwenesis_vdp_get_cram(int index);
+void gwenesis_vdp_get_vram(unsigned char *raw_buffer, int palette);
+void gwenesis_vdp_get_vram_raw(unsigned char *raw_buffer);
+void gwenesis_vdp_get_cram_raw(unsigned char *raw_buffer);
+
+int gwenesis_vdp_vcounter();
+int gwenesis_vdp_hcounter();
+unsigned short gwenesis_vdp_hvcounter();
+
+void gwenesis_vdp_gfx_save_state();
+void gwenesis_vdp_gfx_load_state();
+void gwenesis_vdp_mem_save_state();
+void gwenesis_vdp_mem_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_gfx.c b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_gfx.c
new file mode 100755
index 0000000..5fa7edf
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_gfx.c
@@ -0,0 +1,1038 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include <pico.h>
+
+#include "../cpus/M68K/m68k.h"
+#include "gwenesis_vdp.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../savestate/gwenesis_savestate.h"
+
+//#include <assert.h>
+
+#pragma GCC optimize("Ofast")
+
+extern unsigned char __aligned(4) VRAM[];
+
+extern unsigned short CRAM[]; // CRAM - Palettes
+extern unsigned char SAT_CACHE[]__attribute__((aligned(4))); // Sprite cache
+extern unsigned char gwenesis_vdp_regs[]; // Registers
+
+extern unsigned short VSRAM[]; // VSRAM - Scrolling
+
+// Define screen buffers: original and scaled for host RGB
+//unsigned char *screen, *scaled_screen;
+
+// Define SCREEN buffers for embedded 565 format
+static uint8_t* screen_buffer_line = 0;
+
+//static unsigned short *screen_buffer=0;
+
+// Overflow is the maximum size we can draw outside to avoid
+// wasting time and code in clipping. The maximum object is a 4x4 sprite,
+// so 32 pixels (on both side) is enough.
+
+#define PIX_OVERFLOW (32)
+static uint8_t render_buffer[GWENESIS_SCREEN_WIDTH + PIX_OVERFLOW * 2];
+static uint8_t sprite_buffer[GWENESIS_SCREEN_WIDTH + PIX_OVERFLOW * 2];
+
+// Define VIDEO MODE
+static int mode_h40;
+int mode_pal;
+
+// Define screen W/H
+int screen_width;
+int screen_height;
+
+int gwenesis_H32upscaler;
+
+int sprite_overflow;
+bool sprite_collision;
+
+// Window Plane and A plane spearation
+static int base_w;
+static int PlanA_firstcol;
+static int PlanA_lastcol;
+
+static int Window_firstcol;
+static int Window_lastcol;
+
+// 16 bits access to VRAM
+#define FETCH16VRAM(A)  ( (VRAM[(A)+1]) | (VRAM[(A)] << 8) )
+
+#define VDP_GFX_DISABLE_LOGGING 1
+
+#if !VDP_GFX_DISABLE_LOGGING
+#include <stdarg.h>
+void vdpg_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%03x hc:%03x", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define vdpg_log(...)
+#endif
+/******************************************************************************
+ *
+ *  set screen buffers in which the rendering occurs
+ *  Set original and scaled screen buffer for host
+ *
+ ******************************************************************************/
+//host
+/*
+void gwenesis_vdp_set_buffers(unsigned char *screen_buffer, unsigned char *scaled_buffer)
+{
+    screen = screen_buffer;
+    scaled_screen = scaled_buffer;
+}
+*/
+//embedded
+void gwenesis_vdp_set_buffer(uint8_t* ptr_screen_buffer) {
+    screen_buffer_line = ptr_screen_buffer;
+    //screen_buffer = ptr_screen_buffer;
+}
+
+void gwenesis_vdp_get_buffer(uint16_t** ptr_screen_buffer) {
+    *ptr_screen_buffer = (uint16_t *)&render_buffer[PIX_OVERFLOW];
+    //screen_buffer = ptr_screen_buffer;
+}
+
+/******************************************************************************
+ *
+ *  Draw  Sprite character /8pixels in row
+ *  without checking overdraw for pixels collision detection
+ *  with Horizontal flip variation
+ *  for Shadow/highlight :
+ *    draw in fresh line buffer using draw_pattern_xxfliph_sprite(..)
+ *  otherwise:
+ *   draw over dirty planes using draw_pattern_xxfliph_sprite_over_planes(..)
+ *
+ ******************************************************************************/
+
+#define PIX0(P) ( ((P) & 0x000000F0 ) >>   4 )
+#define PIX1(P) ( ((P) & 0x0000000F ) >>   0 )
+#define PIX2(P) ( ((P) & 0x0000F000 ) >>  12 )
+#define PIX3(P) ( ((P) & 0x00000F00 ) >>   8 )
+#define PIX4(P) ( ((P) & 0x00F00000 ) >>  20 )
+#define PIX5(P) ( ((P) & 0x000F0000 ) >>  16 )
+#define PIX6(P) ( ((P) & 0xF0000000 ) >>  28 )
+#define PIX7(P) ( ((P) & 0x0F000000 ) >>  24 )
+
+static inline __attribute__((always_inline))
+void draw_pattern_nofliph_sprite(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /*  not transparent pixel to write AND not already a sprite*/
+    if (PIX0(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX0(p);
+    if (PIX1(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX1(p);
+    if (PIX2(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX2(p);
+    if (PIX3(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX3(p);
+    if (PIX4(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX4(p);
+    if (PIX5(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX5(p);
+    if (PIX6(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX6(p);
+    if (PIX7(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX7(p);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_fliph_sprite(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /*  not transparent pixel to write AND not already a sprite*/
+    if (PIX7(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX7(p);
+    if (PIX6(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX6(p);
+    if (PIX5(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX5(p);
+    if (PIX4(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX4(p);
+    if (PIX3(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX3(p);
+    if (PIX2(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX2(p);
+    if (PIX1(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX1(p);
+    if (PIX0(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX0(p);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_nofliph_sprite_over_planes(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /* High priority */
+    if (attrs & PIXATTR_HIPRI) {
+        /*  not transparent pixel to write AND not already a sprite*/
+        if (PIX0(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX7(p);
+    }
+    /* Low priority */
+    else {
+        /*  not transparent pixel to write AND not already a sprite or higher priority*/
+        if (PIX0(p) && (scr[0] & PIXATTR_SPRITE_HIPRI) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_SPRITE_HIPRI) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_SPRITE_HIPRI) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_SPRITE_HIPRI) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_SPRITE_HIPRI) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_SPRITE_HIPRI) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_SPRITE_HIPRI) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_SPRITE_HIPRI) == 0) scr[7] = attrs | PIX7(p);
+    }
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_fliph_sprite_over_planes(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /* High priority */
+    if (attrs & PIXATTR_HIPRI) {
+        /*  not transparent pixel to write AND not already a sprite*/
+        if (PIX7(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX0(p);
+    }
+    /* Low priority */
+    else {
+        /*  not transparent pixel to write AND not already a sprite or higher priority*/
+        if (PIX7(p) && (scr[0] & PIXATTR_SPRITE_HIPRI) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_SPRITE_HIPRI) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_SPRITE_HIPRI) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_SPRITE_HIPRI) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_SPRITE_HIPRI) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_SPRITE_HIPRI) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_SPRITE_HIPRI) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_SPRITE_HIPRI) == 0) scr[7] = attrs | PIX0(p);
+    }
+}
+
+/******************************************************************************
+ *
+ *  Draw  characters/8pixels in row
+ *  without checking overdraw for pixels collision detection
+ *  with Horizontal flip variation for plane A & B
+ *
+ ******************************************************************************/
+
+
+static inline __attribute__((always_inline)) void
+draw_pattern_nofliph_planeB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    const uint8_t back = gwenesis_vdp_regs[7];
+
+    if (p == 0) {
+        scr[0] = back;
+        scr[1] = back;
+        scr[2] = back;
+        scr[3] = back;
+        scr[4] = back;
+        scr[5] = back;
+        scr[6] = back;
+        scr[7] = back;
+
+        return;
+    }
+
+    scr[0] = PIX0(p) ? attrs | (PIX0(p)) : back;
+    scr[1] = PIX1(p) ? attrs | (PIX1(p)) : back;
+    scr[2] = PIX2(p) ? attrs | (PIX2(p)) : back;
+    scr[3] = PIX3(p) ? attrs | (PIX3(p)) : back;
+    scr[4] = PIX4(p) ? attrs | (PIX4(p)) : back;
+    scr[5] = PIX5(p) ? attrs | (PIX5(p)) : back;
+    scr[6] = PIX6(p) ? attrs | (PIX6(p)) : back;
+    scr[7] = PIX7(p) ? attrs | (PIX7(p)) : back;
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_fliph_planeB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    const uint8_t back = gwenesis_vdp_regs[7];
+    if (p == 0) {
+        scr[0] = back;
+        scr[1] = back;
+        scr[2] = back;
+        scr[3] = back;
+        scr[4] = back;
+        scr[5] = back;
+        scr[6] = back;
+        scr[7] = back;
+
+        return;
+    }
+
+    scr[0] = PIX7(p) ? attrs | (PIX7(p)) : back;
+    scr[1] = PIX6(p) ? attrs | (PIX6(p)) : back;
+    scr[2] = PIX5(p) ? attrs | (PIX5(p)) : back;
+    scr[3] = PIX4(p) ? attrs | (PIX4(p)) : back;
+    scr[4] = PIX3(p) ? attrs | (PIX3(p)) : back;
+    scr[5] = PIX2(p) ? attrs | (PIX2(p)) : back;
+    scr[6] = PIX1(p) ? attrs | (PIX1(p)) : back;
+    scr[7] = PIX0(p) ? attrs | (PIX0(p)) : back;
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_nofliph_planeAoverB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    if (attrs & PIXATTR_HIPRI) {
+        if (PIX0(p)) scr[0] = attrs | (PIX0(p));
+        if (PIX1(p)) scr[1] = attrs | (PIX1(p));
+        if (PIX2(p)) scr[2] = attrs | (PIX2(p));
+        if (PIX3(p)) scr[3] = attrs | (PIX3(p));
+        if (PIX4(p)) scr[4] = attrs | (PIX4(p));
+        if (PIX5(p)) scr[5] = attrs | (PIX5(p));
+        if (PIX6(p)) scr[6] = attrs | (PIX6(p));
+        if (PIX7(p)) scr[7] = attrs | (PIX7(p));
+    }
+    else {
+        if (PIX0(p) && (scr[0] & PIXATTR_HIPRI) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_HIPRI) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_HIPRI) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_HIPRI) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_HIPRI) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_HIPRI) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_HIPRI) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_HIPRI) == 0) scr[7] = attrs | PIX7(p);
+    }
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_fliph_planeAoverB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    if (attrs & PIXATTR_HIPRI) {
+        if (PIX7(p)) scr[0] = attrs | PIX7(p);
+        if (PIX6(p)) scr[1] = attrs | PIX6(p);
+        if (PIX5(p)) scr[2] = attrs | PIX5(p);
+        if (PIX4(p)) scr[3] = attrs | PIX4(p);
+        if (PIX3(p)) scr[4] = attrs | PIX3(p);
+        if (PIX2(p)) scr[5] = attrs | PIX2(p);
+        if (PIX1(p)) scr[6] = attrs | PIX1(p);
+        if (PIX0(p)) scr[7] = attrs | PIX0(p);
+    }
+    else {
+        if (PIX7(p) && (scr[0] & PIXATTR_HIPRI) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_HIPRI) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_HIPRI) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_HIPRI) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_HIPRI) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_HIPRI) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_HIPRI) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_HIPRI) == 0) scr[7] = attrs | PIX0(p);
+    }
+}
+
+/******************************************************************************
+ *
+ *  Draw  characters/8pixels in row
+ *  with/without checking overdraw for pixels collision detection
+ *  used for sprites and planes drawing
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void draw_pattern_sprite(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5; //name * 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // //unsigned int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+    // uint8_t attrs = (pat_palette << 4) | ((name & 0x8000) ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8) + PIXATTR_SPRITE;
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    // unsigned int  pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_sprite(scr, pattern, attrs);
+    else
+        draw_pattern_nofliph_sprite(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_sprite_over_planes(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5 ; //* 32;
+    // int pat_palette = BITS(name, 13, 2);
+    // int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+    // uint8_t attrs = (pat_palette << 4) | (is_pat_pri ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    //uint8_t attrs = ( (name & 0x6000 ) >> 9 ) | ((name & 0x8000) ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8) + PIXATTR_SPRITE;
+    //uint8_t attrs = ( (name >>9) & 0x70 ) | PIXATTR_SPRITE;
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_sprite_over_planes(scr, pattern, attrs);
+    else
+        draw_pattern_nofliph_sprite_over_planes(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_planeB(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name  << 5; // * 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // unsigned int is_pat_pri = name & 0x8000;
+    //uint8_t *pattern = VRAM + pat_addr;
+
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8);
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    //  if ((*(unsigned int *)pattern) == 0 ) return;
+    // uint8_t *pattern = VRAM + ((name << 5) & 0xFFFF); //) pat_addr;
+    //uint32_t pattern = VRAM[(name & 0x07FF) << 5]; //) pat_addr;
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_planeB(scr, pattern, attrs);
+
+    else
+        draw_pattern_nofliph_planeB(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_planeA(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5; //* 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // unsigned int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8);
+
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_planeAoverB(scr, pattern, attrs);
+
+    else
+        draw_pattern_nofliph_planeAoverB(scr, pattern, attrs);
+}
+
+static uint16_t ntwidth_x2;
+static uint16_t ntw_mask, nth_mask;
+
+/******************************************************************************
+ *
+ *  Return the Horizontal scrolling
+ *
+ ******************************************************************************/
+
+static inline __attribute__((always_inline))
+unsigned int get_hscroll_vram(int line) {
+    switch (REG11_HSCROLL_MODE) {
+        case 0: // Full screen scrolling
+            return REG13_HSCROLL_ADDRESS;
+        case 1: // First 8 lines
+            return REG13_HSCROLL_ADDRESS + (line & 7) * 4;
+        case 2: // Every row
+            return REG13_HSCROLL_ADDRESS + (line & ~7) * 4;
+        case 3: // Every line
+            return REG13_HSCROLL_ADDRESS + line * 4;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render PLANE B on screen line
+ *
+ ******************************************************************************/
+//__attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_line_b(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    const unsigned int ntaddr = REG4_NAMETABLE_B;
+    uint16_t scrollx = FETCH16VRAM(get_hscroll_vram(line) + 2) & 0x3FF;
+    const uint16_t* vsram = &VSRAM[1];
+    const uint8_t* end = scr + screen_width;
+
+    //bool column_scrolling = BIT(gwenesis_vdp_regs[11], 2);
+    const bool column_scrolling = gwenesis_vdp_regs[11] & 0x4;
+
+    // Invert horizontal scrolling (because it goes right, but we need to offset
+    // of the first screen pixel)
+    scrollx = -scrollx;
+    uint8_t col = (scrollx >> 3) & ntw_mask;
+    const uint8_t patx = scrollx & 7;
+
+    unsigned int numcell = 0;
+    scr -= patx;
+    while (scr < end) {
+        // Calculate vertical scrolling for the current line
+        uint16_t scrolly = *vsram + line;
+        uint8_t row = (scrolly >> 3) & nth_mask;
+        uint8_t paty = scrolly & 7;
+
+        // unsigned int nt = ntaddr + row * (2 * ntwidth);
+        unsigned int nt = ntaddr + row * ntwidth_x2;
+
+        draw_pattern_planeB(scr, FETCH16VRAM(nt + __fast_mul(col , 2)), paty);
+        col = (col + 1) & ntw_mask;
+        scr += 8;
+        numcell++;
+
+        // If per-column scrolling is active, increment VSRAM pointer
+        if (column_scrolling && (numcell & 1) == 0)
+            vsram += 2;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render PLANE A and Window on screen line
+ *
+ ******************************************************************************/
+//_attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_line_aw(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    unsigned int ntaddr = REG2_NAMETABLE_A;
+    uint16_t scrollx = FETCH16VRAM(get_hscroll_vram(line) + 0) & 0x3FF;
+    uint16_t* vsram = &VSRAM[0];
+
+    // Check if we are in the window region only
+    // if it's the case, we cancel the plane A drawing
+    int Window_line = REG18_WINDOW_VPOS * 8;
+    //bool window_down = BIT(gwenesis_vdp_regs[18], 7);
+    int window_down = gwenesis_vdp_regs[18] & 0x80;
+
+    int PlanA_first = PlanA_firstcol;
+    int PlanA_last = PlanA_lastcol;
+    int Window_last = Window_lastcol;
+    int Window_first = Window_firstcol;
+
+    if (window_down) {
+        if (line > Window_line) {
+            PlanA_first = PlanA_last = 0;
+            Window_last = screen_width;
+            Window_first = 0;
+        }
+    }
+    else {
+        if (line < Window_line) {
+            PlanA_first = PlanA_last = 0;
+            Window_last = screen_width;
+            Window_first = 0;
+        }
+    }
+
+    // First draw A plane
+    uint8_t* pos = scr + PlanA_first; // scr + screen_width;
+    uint8_t* end = scr + PlanA_last; // scr + screen_width
+
+    //bool column_scrolling = BIT(gwenesis_vdp_regs[11], 2);
+    const unsigned int column_scrolling = gwenesis_vdp_regs[11] & 0x4;
+
+    // Invert horizontal scrolling (because it goes right, but we need to offset
+    // of the first screen pixel)
+    scrollx = -scrollx;
+    uint8_t col = (scrollx >> 3) & ntw_mask;
+    uint8_t patx = scrollx & 7;
+
+    unsigned int numcell = 0;
+    pos -= patx;
+    while (pos < end) {
+        // Calculate vertical scrolling for the current line
+        uint16_t scrolly = *vsram + line;
+        uint8_t row = (scrolly >> 3) & nth_mask;
+        uint8_t paty = scrolly & 7;
+
+        // unsigned int nt = ntaddr + row * (2 * ntwidth);
+        unsigned int nt = ntaddr + row * ntwidth_x2;
+
+        draw_pattern_planeA(pos, FETCH16VRAM(nt + __fast_mul(col , 2)), paty);
+
+        col = (col + 1) & ntw_mask;
+        pos += 8;
+        numcell++;
+
+        // If per-column scrolling is active, increment VSRAM pointer
+        if (column_scrolling && (numcell & 1) == 0)
+            vsram += 2;
+    }
+
+    // Second Draw Window Plane
+    int row = line >> 3;
+    int paty = line & 7;
+    //int wdwidth = (screen_width == 320 ? 64 : 32);
+    //unsigned int nt = base_w + row * 2 * wdwidth + Window_first / 4;
+
+    int wdwidth_x2 = (screen_width == 320 ? 128 : 64);
+
+    unsigned int nt = base_w + row * wdwidth_x2 + Window_first / 4;
+
+    #pragma GCC unroll(64)
+    for (int i = Window_first / 8; i < Window_last / 8; ++i) {
+        draw_pattern_planeA(end, FETCH16VRAM(nt), paty);
+        nt += 2;
+        end += 8;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render SPRITES on screen line
+ *
+ ******************************************************************************/
+
+//__attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_sprites_over_planes(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    //    scr = screen_buffer_line;
+
+    // uint8_t mask = mode_h40 ? 0x7E : 0x7F;
+    // uint8_t *start_table = VRAM + ((gwenesis_vdp_regs[5] & mask) << 9);
+
+    uint8_t* start_table = VRAM + REG5_SAT_ADDRESS;
+
+    // This is both the size of the table as seen by the VDP
+    // *and* the maximum number of sprites that are processed
+    // (important in case of infinite loops in links).
+    const int SPRITE_TABLE_SIZE = (screen_width == 320) ? 80 : 64;
+    const int MAX_SPRITES_PER_LINE = (screen_width == 320) ? 20 : 16;
+    const int MAX_PIXELS_PER_LINE = (screen_width == 320) ? 320 : 256;
+
+    bool masking = false, one_sprite_nonzero = false; // overdraw = false;
+    int sidx = 0, num_sprites = 0, num_pixels = 0;
+
+    for (int i = 0; (i < SPRITE_TABLE_SIZE) && sidx < (SPRITE_TABLE_SIZE); ++i) {
+        uint8_t* table = start_table + __fast_mul(sidx, 8);
+        uint8_t* cache = SAT_CACHE + __fast_mul(sidx, 8);
+        //uint8_t *cache = start_table + sidx*8;
+
+
+        int sy = ((cache[0] & 0x3) << 8) | cache[1];
+        int sx = ((table[6] & 0x3) << 8) | table[7];
+        uint16_t name = (table[4] << 8) | table[5];
+
+
+        int sh = BITS(cache[2], 0, 2) + 1;
+        int link = BITS(cache[3], 0, 7);
+
+        int isflipv = table[4] & 0x10;
+        int isfliph = table[4] & 0x8;
+
+        int sw = BITS(table[2], 2, 2) + 1;
+
+        sy -= 128;
+        if ((line >= sy) && (line < sy + __fast_mul(sh, 8))) {
+            // Sprite masking: a sprite on column 0 masks
+            // any lower-priority sprite, but with the following conditions
+            //   * it only works from the second visible sprite on each line
+            //   * if the previous line had a sprite pixel overflow, it
+            //     works even on the first sprite
+            // Notice that we need to continue parsing the table after masking
+            // to see if we reach a pixel overflow (because it would affect masking
+            // on next line).
+            if (sx == 0) {
+                if (one_sprite_nonzero || (sprite_overflow == line - 1))
+                    masking = true;
+            }
+            else
+                one_sprite_nonzero = true;
+
+            int row = (line - sy) >> 3;
+            int paty = (line - sy) & 7;
+            if (isflipv)
+                row = sh - row - 1;
+
+            sx -= 128;
+            if ((sx > (__fast_mul(-sw, 8))) && (sx < screen_width) && !masking) {
+                name += row;
+
+                if (isfliph) {
+                    name += sh * (sw - 1);
+
+                    for (int p = 0; (p < sw) && (num_pixels < MAX_PIXELS_PER_LINE); p++) {
+                        draw_pattern_sprite_over_planes(scr + sx + __fast_mul(p, 8), name, paty);
+                        name -= sh;
+                        num_pixels += 8;
+                    }
+                }
+                else {
+                    for (int p = 0; (p < sw) && (num_pixels < MAX_PIXELS_PER_LINE); p++) {
+                        draw_pattern_sprite_over_planes(scr + sx + __fast_mul(p, 8), name, paty);
+                        name += sh;
+                        num_pixels += 8;
+                    }
+                }
+            }
+            else
+                num_pixels += sw * 8;
+
+            if (num_pixels >= MAX_PIXELS_PER_LINE) {
+                sprite_overflow = line;
+                break;
+            }
+            if (++num_sprites >= MAX_SPRITES_PER_LINE)
+                break;
+        }
+
+        if (link == 0) break;
+        sidx = link;
+    }
+
+    //  if (overdraw)
+    //      sprite_collision = true;
+}
+
+static inline __attribute__((always_inline))
+void draw_sprites(int line) {
+    uint8_t* scr = &sprite_buffer[PIX_OVERFLOW];
+
+
+    //    scr = screen_buffer_line; //&sprite_buffer[PIX_OVERFLOW];
+
+    // uint8_t mask = mode_h40 ? 0x7E : 0x7F;
+    // uint8_t *start_table = VRAM + ((gwenesis_vdp_regs[5] & mask) << 9);
+
+    uint8_t* start_table = VRAM + REG5_SAT_ADDRESS;
+
+    // This is both the size of the table as seen by the VDP
+    // *and* the maximum number of sprites that are processed
+    // (important in case of infinite loops in links).
+    const int SPRITE_TABLE_SIZE = (screen_width == 320) ? 80 : 64;
+    const int MAX_SPRITES_PER_LINE = (screen_width == 320) ? 20 : 16;
+    const int MAX_PIXELS_PER_LINE = (screen_width == 320) ? 320 : 256;
+
+    bool masking = false, one_sprite_nonzero = false; // overdraw = false;
+    int sidx = 0, num_sprites = 0, num_pixels = 0;
+
+
+    for (int i = 0; i < SPRITE_TABLE_SIZE && sidx < SPRITE_TABLE_SIZE; ++i) {
+        uint8_t* table = start_table + __fast_mul(sidx, 8);
+        uint8_t* cache = start_table + __fast_mul(sidx, 8);
+
+        //uint8_t *cache = SAT_CACHE + sidx * 8;
+
+        int sy = ((cache[0] & 0x3) << 8) | cache[1];
+        int sx = ((table[6] & 0x3) << 8) | table[7];
+        uint16_t name = (table[4] << 8) | table[5];
+
+        int sh = BITS(cache[2], 0, 2) + 1;
+        int link = BITS(cache[3], 0, 7);
+
+        int isflipv = table[4] & 0x10;
+        int isfliph = table[4] & 0x8;
+
+        int sw = BITS(table[2], 2, 2) + 1;
+
+        sy -= 128;
+        if (line >= sy && line < sy + __fast_mul(sh, 8)) {
+            // Sprite masking: a sprite on column 0 masks
+            // any lower-priority sprite, but with the following conditions
+            //   * it only works from the second visible sprite on each line
+            //   * if the previous line had a sprite pixel overflow, it
+            //     works even on the first sprite
+            // Notice that we need to continue parsing the table after masking
+            // to see if we reach a pixel overflow (because it would affect masking
+            // on next line).
+            if (sx == 0) {
+                if (one_sprite_nonzero || sprite_overflow == line - 1)
+                    masking = true;
+            }
+            else
+                one_sprite_nonzero = true;
+
+            int row = (line - sy) >> 3;
+            int paty = (line - sy) & 7;
+            if (isflipv)
+                row = sh - row - 1;
+
+            sx -= 128;
+            if (sx > -__fast_mul(sw, 8) && sx < screen_width && !masking) {
+                name += row;
+
+                if (isfliph) {
+                    name += sh * (sw - 1);
+                    for (int p = 0; p < sw && num_pixels < MAX_PIXELS_PER_LINE; p++) {
+                        draw_pattern_sprite(scr + sx + __fast_mul(p, 8), name, paty);
+                        name -= sh;
+                        num_pixels += 8;
+                    }
+                }
+                else {
+                    for (int p = 0; p < sw && num_pixels < MAX_PIXELS_PER_LINE; p++) {
+                        draw_pattern_sprite(scr + sx + __fast_mul(p, 8), name, paty);
+                        name += sh;
+                        num_pixels += 8;
+                    }
+                }
+            }
+            else
+                num_pixels += __fast_mul(sw, 8);
+
+            if (num_pixels >= MAX_PIXELS_PER_LINE) {
+                sprite_overflow = line;
+                break;
+            }
+            if (++num_sprites >= MAX_SPRITES_PER_LINE)
+                break;
+        }
+
+        if (link == 0)
+            break;
+        sidx = link;
+    }
+
+    //  if (overdraw)
+    //      sprite_collision = true;
+}
+
+/******************************************************************************
+ *
+ *  Parse PLANE A/B size,scrolling at the start of image rendering
+ *
+ ******************************************************************************/
+//static unsigned short current_line[320];
+
+void __time_critical_func(gwenesis_vdp_render_config)() {
+    mode_h40 = REG12_MODE_H40;
+    mode_pal = REG1_PAL;
+
+    int ntwidth = BITS(gwenesis_vdp_regs[16], 0, 2);
+    int ntheight = BITS(gwenesis_vdp_regs[16], 4, 2);
+    ntwidth = __fast_mul((ntwidth + 1), 32);
+    ntheight = __fast_mul((ntheight + 1), 32);
+    ntw_mask = ntwidth - 1;
+    nth_mask = ntheight - 1;
+    ntwidth_x2 = ntwidth * 2;
+
+    // Window & A planes separation
+
+    if (mode_h40)
+        base_w = ((REG3_NAMETABLE_W & 0x1e) << 11);
+    else
+        base_w = ((REG3_NAMETABLE_W & 0x1f) << 11);
+
+
+    bool window_right = BIT(gwenesis_vdp_regs[17], 7);
+
+    // int window_is_bugged = 0;
+    PlanA_firstcol = 0;
+    PlanA_lastcol = screen_width;
+
+    Window_firstcol = 0;
+    Window_lastcol = 0;
+
+    if (window_right) {
+        Window_firstcol = REG17_WINDOW_HPOS * 16;
+        Window_lastcol = screen_width;
+
+        if (Window_firstcol > Window_lastcol)
+            Window_firstcol = Window_lastcol;
+
+        PlanA_firstcol = 0;
+        PlanA_lastcol = Window_firstcol;
+    }
+    else {
+        Window_firstcol = 0;
+        Window_lastcol = REG17_WINDOW_HPOS * 16;
+        if (Window_lastcol > screen_width)
+            Window_lastcol = screen_width;
+
+        PlanA_firstcol = Window_lastcol;
+        PlanA_lastcol = screen_width;
+        // if (Window_lastcol != 0)
+        //      window_is_bugged = 1;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render a line on screen
+ *  Get selected line and render it on screen processing each plane.
+ *
+ ******************************************************************************/
+
+void gwenesis_vdp_render_line(int line) {
+    uint8_t* line_buffer = &screen_buffer_line[__fast_mul(line, screen_width)];
+    mode_h40 = REG12_MODE_H40;
+    //mode_pal = REG1_PAL;
+
+    vdpg_log(__FUNCTION__, ": %3d", line);
+
+    //unsigned int line = scan_line;
+    // if (line == 0) gwenesis_vdp_render_config();
+
+    // interlace mode not implemented
+    if (BITS(gwenesis_vdp_regs[12], 1, 2) != 0)
+        return;
+
+    if (line >= (REG1_PAL ? 240 : 224))
+        return;
+
+    // Disable display >> black SCREEN
+    if (REG0_DISABLE_DISPLAY) {
+        memset(line_buffer, 0, screen_width);
+        return;
+    }
+
+    // Display is not enabled. fill with background colour
+    if (REG1_DISP_ENABLED == 0) {
+        memset(line_buffer, 0, screen_width);
+        return;
+    }
+
+
+    const uint8_t* pb = &render_buffer[PIX_OVERFLOW];
+    uint8_t* ps = &sprite_buffer[PIX_OVERFLOW];
+
+    if (MODE_SHI)
+        memset(ps, 0, GWENESIS_SCREEN_WIDTH);
+
+    draw_line_b(line);
+    draw_line_aw(line);
+
+    /* Mode Highlight/shadow is enabled */
+    if (MODE_SHI) {
+        draw_sprites(line);
+
+        for (int x = 0; x < screen_width; x++) {
+            const uint8_t plane = pb[x];
+            const uint8_t sprite = ps[x];
+
+            if ((plane & 0xC0) < (sprite & 0xC0)) {
+                switch (sprite & 0x3F) {
+                    // Palette=3, Sprite=14 :> draw plane, force highlight
+                    case 0x3E:
+                        line_buffer[x] = 0x8410 | plane >> 1;
+                        break;
+                    // Palette=3, Sprite=15 :> draw plane, force shadow
+                    case 0x3F:
+                        line_buffer[x] = plane >> 1;
+                        break;
+                    // draw sprite, normal
+                    default:
+                        line_buffer[x] = sprite;
+                        break;
+                }
+            }
+            else {
+                line_buffer[x] = plane;
+            }
+        }
+
+        /* Normal mode*/
+    }
+    else {
+        draw_sprites_over_planes(line);
+        memcpy(line_buffer, pb, screen_width);
+    }
+}
+
+void gwenesis_vdp_gfx_save_state() {
+    /*
+    SaveState* state;
+    state = saveGwenesisStateOpenForWrite("vdp_gfx");
+    saveGwenesisStateSetBuffer(state, "render_buffer", render_buffer, sizeof(render_buffer));
+    saveGwenesisStateSetBuffer(state, "sprite_buffer", sprite_buffer, sizeof(sprite_buffer));
+    saveGwenesisStateSet(state, "mode_h40", mode_h40);
+    saveGwenesisStateSet(state, "mode_pal", mode_pal);
+    saveGwenesisStateSet(state, "screen_width", screen_width);
+    saveGwenesisStateSet(state, "screen_height", screen_height);
+    saveGwenesisStateSet(state, "sprite_overflow", sprite_overflow);
+    saveGwenesisStateSet(state, "sprite_collision", sprite_collision);
+    saveGwenesisStateSet(state, "base_w", base_w);
+    saveGwenesisStateSet(state, "PlanA_firstcol", PlanA_firstcol);
+    saveGwenesisStateSet(state, "PlanA_lastcol", PlanA_lastcol);
+    saveGwenesisStateSet(state, "Window_firstcol", Window_firstcol);
+    saveGwenesisStateSet(state, "Window_lastcol", Window_lastcol);
+    */
+}
+
+void gwenesis_vdp_gfx_load_state() {
+    /*
+      SaveState* state = saveGwenesisStateOpenForRead("vdp_gfx");
+      saveGwenesisStateGetBuffer(state, "render_buffer", render_buffer, sizeof(render_buffer));
+      saveGwenesisStateGetBuffer(state, "sprite_buffer", sprite_buffer, sizeof(sprite_buffer));
+      mode_h40 = saveGwenesisStateGet(state, "mode_h40");
+      mode_pal = saveGwenesisStateGet(state, "mode_pal");
+      screen_width = saveGwenesisStateGet(state, "screen_width");
+      screen_height = saveGwenesisStateGet(state, "screen_height");
+      sprite_overflow = saveGwenesisStateGet(state, "sprite_overflow");
+      sprite_collision = saveGwenesisStateGet(state, "sprite_collision");
+      base_w = saveGwenesisStateGet(state, "base_w");
+      PlanA_firstcol = saveGwenesisStateGet(state, "PlanA_firstcol");
+      PlanA_lastcol = saveGwenesisStateGet(state, "PlanA_lastcol");
+      Window_firstcol = saveGwenesisStateGet(state, "Window_firstcol");
+      Window_lastcol = saveGwenesisStateGet(state, "Window_lastcol");
+      */
+}
diff --git a/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_mem.c b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_mem.c
new file mode 100755
index 0000000..378a1cd
--- /dev/null
+++ b/MCUME_pico2/picogen/_gwenesis/vdp/gwenesis_vdp_mem.c
@@ -0,0 +1,914 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include "../cpus/M68K/m68k.h"
+#include "gwenesis_vdp.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../savestate/gwenesis_savestate.h"
+
+#include <assert.h>
+//#include <graphics.h>
+#include <gwenesis/sound/gwenesis_sn76489.h>
+
+#include "pico.h"
+#pragma GCC optimize("Ofast")
+
+
+extern void emu_DrawLine16(unsigned short *src, int width , int height, int line); 
+extern void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line); 
+extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index);
+
+
+#define VDP_MEM_DISABLE_LOGGING 1
+
+#if !VDP_MEM_DISABLE_LOGGING
+#include <stdarg.h>
+void vdpm_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%04x hc:%04x hv:%04x ", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter(),gwenesis_vdp_hvcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define vdpm_log(...)
+#endif
+
+//#define _DMA_TRACE_
+
+/* Setup VDP Memories */
+
+//extern uint8_t emulator_framebuffer[1024*64];
+//unsigned char* VRAM = &emulator_framebuffer[0];
+unsigned char VRAM[VRAM_MAX_SIZE];
+//unsigned char* VRAM = NULL;
+
+unsigned short CRAM[CRAM_MAX_SIZE]; // CRAM - Palettes
+unsigned char SAT_CACHE[SAT_CACHE_MAX_SIZE]; // Sprite cache
+unsigned char gwenesis_vdp_regs[REG_SIZE]; // Registers
+unsigned short fifo[FIFO_SIZE]; // Fifo
+//uint8_t CRAM222[CRAM_MAX_SIZE * 4];    // CRAM - Palettes
+unsigned short VSRAM[VSRAM_MAX_SIZE]; // VSRAM - Scrolling
+
+// Define VDP control code and set initial code
+static unsigned char code_reg = 0;
+// Define VDP control address and set initial address
+static unsigned short address_reg = 0;
+// Define VDP control pending and set initial state
+int command_word_pending = 0;
+// Define VDP status and set initial status value
+unsigned short gwenesis_vdp_status = 0x3C00;
+
+extern int scan_line;
+extern bool sn76489_enabled;
+extern bool audio_enabled;
+// Define DMA
+//static unsigned int dma_length;
+//static unsigned int dma_source;
+// Define and set DMA FILL pending as initial state
+int dma_fill_pending = 0;
+
+// Define HVCounter latch and set initial state
+static int hvcounter_latch = 0;
+static int hvcounter_latched = 0;
+
+int hint_pending;
+
+
+// Define VIDEO MODE
+extern int mode_pal;
+
+extern int sprite_overflow;
+extern bool sprite_collision;
+
+// Store last address r/w
+//static unsigned int gwenesis_vdp_laddress_r=0;
+//unsigned int gwenesis_vdp_laddress_w=0;
+
+//static int DMA_RUN=0;
+
+// 16 bits access to VRAM
+#define FETCH16(A) ( ( (*(unsigned short *)&VRAM[(A)]) >> 8 ) | ( (*(unsigned short *)&VRAM[(A)]) << 8 ) )
+
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 Reset
+ *  Clear all volatile memory
+ *
+ ******************************************************************************/
+int m68k_irq_acked(int irq) {
+    /* VINT has higher priority (Fatal Rewind) */
+    if (REG1_VBLANK_INTERRUPT && (gwenesis_vdp_status & STATUS_VIRQPENDING)) {
+        /* Clear VINT pending flag */
+        gwenesis_vdp_status &= ~STATUS_VIRQPENDING;
+
+        if (hint_pending && REG0_LINE_INTERRUPT)
+            m68k_set_irq(4);
+        else
+            m68k_set_irq(0);
+    }
+    else {
+        /* Clear HINT pending flag */
+        hint_pending = 0;
+
+        /* Update IRQ status */
+        m68k_set_irq(0);
+    }
+
+    return M68K_INT_ACK_AUTOVECTOR;
+}
+
+
+void gwenesis_vdp_reset() {
+    memset(VRAM, 0, VRAM_MAX_SIZE);
+    memset(SAT_CACHE, 0, sizeof(SAT_CACHE));
+    memset(CRAM, 0, sizeof(CRAM));
+    //    memset(CRAM222, 0, sizeof(CRAM222));
+    memset(VSRAM, 0, sizeof(VSRAM));
+    memset(gwenesis_vdp_regs, 0, sizeof(gwenesis_vdp_regs));
+    command_word_pending = 0;
+    address_reg = 0;
+    code_reg = 0;
+    hint_pending = 0;
+    // _vcounter = 0;
+    gwenesis_vdp_status = 0x3C00;
+    // //line_counter_interrupt = 0;
+    hvcounter_latched = 0;
+
+    // register the M68K interrupt
+    m68k_set_int_ack_callback(m68k_irq_acked);
+}
+
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 HCOUNTER
+ *  Process SEGA 315-5313 HCOUNTER based on M68K Cycles
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+int gwenesis_vdp_hcounter() {
+    int mclk = m68k_cycles_run();
+    int pixclk;
+
+    // Accurate 9-bit hcounter emulation, from timing posted here:
+    // http://gendev.spritesmind.net/forum/viewtopic.php?p=17683#17683
+    if (REG12_MODE_H40) {
+        pixclk = mclk * 420 / VDP_CYCLES_PER_LINE;
+        pixclk += 0xD;
+        if (pixclk >= 0x16D)
+            pixclk += 0x1C9 - 0x16D;
+    }
+    else {
+        pixclk = mclk * 342 / VDP_CYCLES_PER_LINE;
+        pixclk += 0xB;
+        if (pixclk >= 0x128)
+            pixclk += 0x1D2 - 0x128;
+    }
+
+    return pixclk & 0x1FF;
+}
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 VCOUNTER
+ *  Process SEGA 315-5313 VCOUNTER based on M68K Cycles
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+int gwenesis_vdp_vcounter() {
+    int vc = scan_line;
+    int VERSION_PAL = gwenesis_vdp_status & 1;
+
+    /*
+    if (VERSION_PAL && mode_pal && (vc >= 0x10B))
+        vc += 0x1D2 - 0x10B;
+    else if (VERSION_PAL && (mode_pal==0) && (vc >= 0x103))
+        vc += 0x1CA - 0x103;
+    else if ((VERSION_PAL ==0 ) && (vc >= 0xEB))
+        vc += 0x1E5 - 0xEB;
+    assert(vc < 0x200);
+    */
+    if (VERSION_PAL && mode_pal && (vc >= 267))
+        vc = scan_line - 58;
+    else if (VERSION_PAL && (mode_pal == 0) && (vc >= 259))
+        vc = scan_line - 42;
+    else if ((VERSION_PAL == 0) && (vc >= 235))
+        vc = scan_line - 6;
+    assert(vc < 0x200);
+
+    // printf("VERSION_PAL:%d , mode_pal:%d,line:%d,vc:%d\n",VERSION_PAL,mode_pal,scan_line,vc);
+    return vc;
+}
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 HVCOUNTER
+ *  Process SEGA 315-5313 HVCOUNTER based on HCOUNTER and VCOUNTER
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+unsigned short gwenesis_vdp_hvcounter() {
+    /* H/V Counter */
+    if (hvcounter_latched == 1)
+        return hvcounter_latch;
+
+    int hc = gwenesis_vdp_hcounter();
+    int vc = gwenesis_vdp_vcounter();
+    assert(vc < 512);
+    assert(hc < 512);
+
+    return ((vc & 0xFF) << 8) | (hc >> 1);
+}
+
+//static inline __attribute__((always_inline))
+bool vblank(void) {
+    int vc = gwenesis_vdp_vcounter();
+    //  printf("vc=%d,REG1_DISP_ENABLED=%d,VBLAN?%d\n",vc,REG1_DISP_ENABLED,
+    // mode_pal?((vc >= 0xF0) && (vc < 0x1FF)):((vc >= 0xE0) && (vc < 0x1FF)));
+
+    if (REG1_DISP_ENABLED == 0)
+        return true;
+
+    if (mode_pal)
+        return ((vc >= 0xF0) && (vc < 0x1FF));
+    else
+        return ((vc >= 0xE0) && (vc < 0x1FF));
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Set Register
+ *   Write an value to specified register
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline)) void gwenesis_vdp_register_w(int reg, unsigned char value) {
+    // Mode4 is not emulated yet. Anyway, access to registers > 0xA is blocked.
+    if ((BIT(gwenesis_vdp_regs[0x1], 2) == 0) && reg > 0xA)
+        return;
+
+    gwenesis_vdp_regs[reg] = value;
+    vdpm_log(__FUNCTION__, "reg:%02d <- %02x", reg, value);
+
+
+    // Writing a register clear the first command word
+    // (see sonic3d intro wrong colors, and vdpfifotesting)
+    code_reg &= ~0x3;
+    address_reg &= ~0x3FFF;
+
+    switch (reg) {
+        case 0:
+
+            if (REG0_HVLATCH && (hvcounter_latched == 0)) {
+                hvcounter_latch = gwenesis_vdp_hvcounter();
+                hvcounter_latched = 1;
+                //printf("HVcounter latched:%x\n",hvcounter_latch);
+            }
+            else if ((REG0_HVLATCH == 0) && (hvcounter_latched == 1)) {
+                //printf("HVcounter released\n");
+                hvcounter_latched = 0;
+            }
+
+            break;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Simulate FIFO
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void push_fifo(unsigned int value) {
+    fifo[3] = fifo[2];
+    fifo[2] = fifo[1];
+    fifo[1] = fifo[0];
+    fifo[0] = value;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 VRAM Write
+ *   Write an value to VRAM on specified address
+ *
+ ******************************************************************************/
+
+//static inline __attribute__((always_inline))
+void __not_in_flash_func(gwenesis_vdp_vram_write)(unsigned int address, unsigned int value) {
+    VRAM[address] = value;
+
+    // Update internal SAT Cache
+    // used in Castlevania Bloodlines
+    if (address >= REG5_SAT_ADDRESS && address < REG5_SAT_ADDRESS + REG5_SAT_SIZE)
+        SAT_CACHE[address - REG5_SAT_ADDRESS] = value;
+}
+
+static inline __attribute__((always_inline))
+unsigned short status_register_r(void) {
+    unsigned short status = gwenesis_vdp_status; // & 0xF800;
+    // unsigned short status = gwenesis_vdp_status;// & 0xFC00;
+
+    int hc = gwenesis_vdp_hcounter();
+    // int vc = gwenesis_vdp_vcounter();
+
+    // TODO: FIFO not emulated
+    status |= STATUS_FIFO_EMPTY;
+
+    // VBLANK bit
+    if (vblank())
+        status |= STATUS_VBLANK;
+
+    // HBLANK bit (see Nemesis doc, as linked in hcounter())
+    if (REG12_MODE_H40) {
+        if (hc < 0xA || hc >= 0x166)
+            status |= STATUS_HBLANK;
+    }
+    else {
+        if (hc < 0x9 || hc >= 0x126)
+            status |= STATUS_HBLANK;
+    }
+
+    if (sprite_overflow)
+        status |= STATUS_SPRITEOVERFLOW;
+    if (sprite_collision)
+        status |= STATUS_SPRITECOLLISION;
+
+    if (mode_pal)
+        status |= STATUS_PAL;
+
+    // reading the status clears the pending flag for command words
+    command_word_pending = 0;
+
+    //gwenesis_vdp_status = status;
+
+    // printf("VDP status read:%04X H?%d V?%d line=%d\n",status, status & STATUS_HBLANK ,status & STATUS_VBLANK,scan_line);
+    return status;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Get Register
+ *   Read an value from specified register
+ *
+ ******************************************************************************/
+unsigned int gwenesis_vdp_get_reg(int reg) {
+    return gwenesis_vdp_regs[reg];
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA Fill
+ *   DMA process to fill memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_fill(unsigned short value) {
+    //vdpm_log(__FUNCTION__,"@%x len:%x val:%x",REG21_DMA_SRCADDR_LOW,REG19_DMA_LENGTH,value);
+    int dma_length = REG19_DMA_LENGTH;
+
+    // This address is not required for fills,
+    // but it's still updated by the DMA engine.
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+
+    if (dma_length == 0)
+        dma_length = 0xFFFF;
+
+    /*
+    vdpm_log(__FUNCTION__, "DMA %s fill: dst:%04x, length:%d, increment:%d, value=%02x",
+        (code_reg&0xF)==1 ? "VRAM" : ( (code_reg&0xF)==3 ? "CRAM" : "VSRAM"),
+        address_reg, dma_length, REG15_DMA_INCREMENT, value>>8);
+        */
+
+    switch (code_reg & 0xF) {
+        case 0x1:
+            do {
+                gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value >> 8);
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        case 0x3: // undocumented and buggy, see vdpfifotesting
+            do {
+                uint8_t addr = (address_reg & 0x7f) >> 1;
+                CRAM[addr] = fifo[3];
+                //graphics_set_palette(addr, RGB888(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr])));
+                emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        case 0x5: // undocumented and buggy, see vdpfifotesting:
+            do {
+                VSRAM[(address_reg & 0x7f) >> 1] = fifo[3] & 0x03FF;
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        default:
+            printf("Invalid code during DMA fill\n");
+    }
+
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = src_addr_low >> 8;
+
+    // gwenesis_vdp_regs[21] = src_addr_low >> 1 & 0xFF;
+    // gwenesis_vdp_regs[22] = src_addr_low >> 9 & 0xFF;
+    // gwenesis_vdp_regs[23] = src_addr_low >> 17 & 0xFF;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA M68K
+ *   DMA process to copy from m68k to memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_m68k() {
+    int dma_length = REG19_DMA_LENGTH;
+
+    // This address is not required for fills,
+    // but it's still updated by the DMA engine.
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+    unsigned int src_addr_high = REG23_DMA_SRCADDR_HIGH;
+    unsigned int src_addr = (src_addr_high | src_addr_low) << 1;
+    unsigned int value;
+
+    if (dma_length == 0)
+        dma_length = 0xFFFF;
+
+    /*
+    vdpm_log(__FUNCTION__,"DMA M68k->%s copy: src:%04x, dst:%04x, length:%d, increment:%d",
+        (code_reg&0xF)==1 ? "VRAM" : ( (code_reg&0xF)==3 ? "CRAM" : "VSRAM"),
+        (src_addr_high | src_addr_low) << 1, address_reg, dma_length, REG15_DMA_INCREMENT);
+    */
+
+    /* Source is :
+        68K_RAM if dma_source_high == 0x00FF : FETCH16RAM(dma_source_low << 1)
+        68K_ROM otherwise                    : FETCH16ROM((dma_source_high | dma_source_low) << 1))
+    */
+
+    /* Source is 68K RAM */
+    if (src_addr & 0x800000) {
+        switch (code_reg & 0xF) {
+            case 0x1: // dest is VRAM
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    gwenesis_vdp_vram_write((address_reg) & 0xFFFF, value >> 8);
+                    gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value & 0xFF);
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x3: // dest is CRAM
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    uint8_t addr = (address_reg & 0x7f) >> 1;
+                    CRAM[addr] = value;
+
+                    //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+                    emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x5: // dest is VSRAM
+
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    VSRAM[(address_reg & 0x7f) >> 1] = value & 0x03FF;
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+            default: // dest in unknown
+                break;
+        }
+
+        /* source is 68K ROM */
+    }
+    else {
+        // unsigned int dma_source_address = (dma_source_high | dma_source_low) << 1;
+
+        switch (code_reg & 0xF) {
+            case 0x1: // dest is VRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    gwenesis_vdp_vram_write((address_reg) & 0xFFFF, value >> 8);
+                    gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value & 0xFF);
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x3: // dest is CRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    uint8_t addr = (address_reg & 0x7f) >> 1;
+                    CRAM[addr] = value;
+
+                    //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+                    emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x5: // dest is VSRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    VSRAM[(address_reg & 0x7f) >> 1] = value & 0x03FF;
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+            default: // dest in unknown
+                break;
+        }
+    }
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr & 0xFF; //src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = (src_addr >> 8) & 0xFF; //src_addr_low >> 8;
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA Copy
+ *   DMA process to copy from memory to memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_copy() {
+    // DMA_RUN=1;
+
+    int dma_length = REG19_DMA_LENGTH;
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+    //vdpm_log(__FUNCTION__,"length:%x src:%x",dma_length,src_addr_low);
+
+    do {
+        unsigned short value = VRAM[src_addr_low ^ 1];
+        gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value);
+
+        address_reg += REG15_DMA_INCREMENT;
+        src_addr_low++;
+    }
+    while (--dma_length);
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = src_addr_low >> 8;
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read data R16
+ *   Read an data value from mapped memory on specified address
+ *   and return as word
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+unsigned int gwenesis_vdp_read_data_port_16() {
+    enum {
+        CRAM_BITMASK = 0x0EEE,
+        VSRAM_BITMASK = 0x07FF,
+        VRAM8_BITMASK = 0x00FF
+    };
+    unsigned int value;
+    command_word_pending = 0;
+
+    //if (code_reg & 1) /* check if write is set */
+    // {
+    switch (code_reg & 0xF) {
+        case 0x0:
+            // No byteswapping here
+            value = VRAM[(address_reg) & 0xFFFE] << 8;
+            value |= VRAM[(address_reg | 1) & 0xFFFF];
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+        //vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0x4:
+            if (((address_reg & 0x7f) >> 1) >= 0x28)
+                value = VSRAM[0];
+            else
+                value = VSRAM[(address_reg & 0x7f) >> 1];
+            value = (value & VSRAM_BITMASK) | (fifo[3] & ~VSRAM_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0x7F;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0x8:
+            value = CRAM[(address_reg & 0x7f) >> 1];
+            value = (value & CRAM_BITMASK) | (fifo[3] & ~CRAM_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0x7F;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0xC: /* 8-Bit memory access */
+            value = VRAM[(address_reg ^ 1) & 0xFFFF];
+            value = (value & VRAM8_BITMASK) | (fifo[3] & ~VRAM8_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        default:
+            printf("unhandled gwenesis_vdp_read_data_port_16(%x)\n", address_reg);
+            return 0xFF;
+    }
+    // }
+    //  return 0x00;
+}
+
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to control port
+ *   Write an control value to SEGA 315-5313 control port
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_control_port_write(unsigned int value) {
+    //vdpm_log(__FUNCTION__,"%04x",value);
+
+    if (command_word_pending == 1) {
+        // second half of the command word
+        code_reg &= ~0x3C;
+        code_reg |= (value >> 2) & 0x3C;
+        address_reg &= 0x3FFF;
+        address_reg |= value << 14;
+        command_word_pending = 0;
+        //vdpm_log(__FUNCTION__,"command word 2nd code:%x address:%x", code_reg, address_reg);
+
+
+        // DMA trigger
+        if (code_reg & (1 << 5)) {
+            // Check master DMA enable, otherwise skip
+            if (REG1_DMA_ENABLED == 0)
+                return;
+
+            // gwenesis_vdp_status |= 0x2;
+            switch (REG23_DMA_TYPE) {
+                case 0:
+                case 1:
+
+                    gwenesis_vdp_dma_m68k();
+                    break;
+
+                case 2:
+
+                    // VRAM fill will trigger on next data port write
+                    dma_fill_pending = 1;
+                    break;
+
+                case 3:
+
+                    gwenesis_vdp_dma_copy();
+                    break;
+            }
+        }
+        return;
+    }
+    if ((value >> 14) == 2) {
+        gwenesis_vdp_register_w((value >> 8) & 0x1F, value & 0xFF);
+        return;
+    }
+
+    // Anything else is treated as first half of the command word
+    // We directly update the code reg and address reg
+    code_reg &= ~0x3;
+    code_reg |= value >> 14;
+    address_reg &= ~0x3FFF;
+    address_reg |= value & 0x3FFF;
+    command_word_pending = 1;
+    // vdpm_log(__FUNCTION__,"command word 1st code:%x address:%x", code_reg, address_reg);
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write data W16
+ *   Write an data value to mapped memory on specified address
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_write_data_port_16(unsigned int value) {
+    vdpm_log(__FUNCTION__, "%04x", value);
+
+    command_word_pending = 0;
+
+    push_fifo(value);
+
+    switch (code_reg & 0xF) {
+        case 0x1: /* VRAM write */
+            //vdpm_log(__FUNCTION__,"VRAM write : addr:%x increment:%d value:%04x",
+            // address_reg, REG15_DMA_INCREMENT, value);
+            gwenesis_vdp_vram_write(address_reg & 0xFFFF, (value >> 8) & 0xFF);
+            gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, (value) & 0xFF);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+
+            break;
+        case 0x3: /* CRAM write */
+            //vdpm_log(__FUNCTION__,"CRAM write : addr:%x increment:%d value:%04x",
+            // address_reg, REG15_DMA_INCREMENT, value);
+        {
+            uint8_t addr = (address_reg & 0x7f) >> 1;
+            CRAM[addr] = value;
+
+            //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+            emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+
+            break;
+        }
+        case 0x5: /* VSRAM write */
+            //vdpm_log(__FUNCTION__,"VSRAM write : addr:%x increment:%d value:%04x",
+            //  address_reg, REG15_DMA_INCREMENT, value);
+            // printf("write dataport 16: VSRAM@%04x:%04x\n",address_reg,value);
+            VSRAM[(address_reg & 0x7f) >> 1] = value & 0X03FF;
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+            break;
+        case 0x0:
+        case 0x4:
+        case 0x8: // Write operation after setting up
+            // Makes Compatible with Alladin and Ecco 2
+            break;
+        case 0x9: // VDP FIFO TEST
+            break;
+        default:
+            printf("VDP Data Port invalid");
+    }
+
+    /* if a DMA is scheduled, do it */
+    if (dma_fill_pending) {
+        dma_fill_pending = 0;
+        gwenesis_vdp_dma_fill(value);
+        return;
+    }
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Get Status
+ *   Return current VDP Status
+ *
+ ******************************************************************************/
+unsigned int gwenesis_vdp_get_status() {
+    return gwenesis_vdp_status;
+}
+
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read from memory R8
+ *   Read an value from mapped memory on specified address
+ *   and return as byte
+ *
+ ******************************************************************************/
+//static inline
+unsigned int gwenesis_vdp_read_memory_8(unsigned int address) {
+    unsigned int ret = gwenesis_vdp_read_memory_16(address & ~1);
+    if (address & 1)
+        return ret & 0xFF;
+
+    // vdpm_log(__FUNCTION__,"%04x : %04x",address,ret);
+
+    return ret >> 8;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read from memory R16
+ *   Read an value from mapped memory on specified address
+ *   and return as word
+ *
+ ******************************************************************************/
+//static inline
+unsigned int gwenesis_vdp_read_memory_16(unsigned int address) {
+    address &= 0x1F;
+
+    if (address < 0X4)
+        return gwenesis_vdp_read_data_port_16();
+    else if (address < 0x8)
+        return status_register_r();
+    else if (address < 0xf)
+        return gwenesis_vdp_hvcounter();
+    else
+        return 0xff;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to memory W8
+ *   Write an byte value to mapped memory on specified address
+ *
+ ******************************************************************************/
+//static inline
+void gwenesis_vdp_write_memory_8(unsigned int address, unsigned int value) {
+    gwenesis_vdp_write_memory_16(address & ~1, (value << 8) | value);
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to memory W16
+ *   Write an word value to mapped memory on specified address
+ *
+ ******************************************************************************/
+//static inline
+extern int system_clock;
+
+void gwenesis_vdp_write_memory_16(unsigned int address, unsigned int value) {
+    address = address & 0x1F;
+
+    if (address < 0x4) {
+        gwenesis_vdp_write_data_port_16(value);
+        return;
+    }
+    if (address < 0x8) {
+        gwenesis_vdp_control_port_write(value);
+        return;
+    }
+    if (address < 0x18) {
+        // PSG 8 bits write
+        vdpm_log(__FUNCTION__, "PSG sclk=%d,mclk=%d", system_clock, m68k_cycles_master());
+        if(audio_enabled && sn76489_enabled)
+            gwenesis_SN76489_Write(value, m68k_cycles_master());
+        return;
+    }
+    // UNHANDLED
+    printf("unhandled gwenesis_vdp_write(%x, %x)\n", address, value);
+}
+
+void gwenesis_vdp_mem_save_state() {
+}
+
+void gwenesis_vdp_mem_load_state() {
+
+}
diff --git a/MCUME_pico2/picogen/emu.cpp b/MCUME_pico2/picogen/emu.cpp
new file mode 100644
index 0000000..3c776da
--- /dev/null
+++ b/MCUME_pico2/picogen/emu.cpp
@@ -0,0 +1,253 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+#include <pico/stdlib.h>
+
+/* Gwenesis Emulator */
+extern "C" {
+#include "gwenesis/cpus/M68K/m68k.h"
+#include "gwenesis/sound/z80inst.h"
+#include "gwenesis/bus/gwenesis_bus.h"
+#include "gwenesis/io/gwenesis_io.h"
+#include "gwenesis/vdp/gwenesis_vdp.h"
+#include "gwenesis/savestate/gwenesis_savestate.h"
+#include <gwenesis/sound/gwenesis_sn76489.h>
+#include <gwenesis/sound/ym2612.h>
+}
+
+#include "flash_t.h"
+
+// SETTINGS
+bool show_fps = true;
+bool limit_fps = true;
+bool interlace = true;
+bool frameskip = true;
+bool flash_line = false;
+bool flash_frame = false;
+int z80_enable_mode = 2;
+bool sn76489_enabled = true;
+//int z80_enable_mode = 0;
+//bool sn76489_enabled = false;
+
+
+uint8_t snd_accurate = 0;
+/* shared variables with gwenesis_sn76589 */
+int16_t gwenesis_sn76489_buffer[GWENESIS_AUDIO_BUFFER_LENGTH_NTSC * 2];  // 888 = NTSC, PAL = 1056 (too big) //GWENESIS_AUDIO_BUFFER_LENGTH_PAL];
+int sn76489_index;                                                      /* sn78649 audio buffer index */
+int sn76489_clock;                                                      /* sn78649 clock in video clock resolution */
+
+
+int audio_enabled = 1;
+int snd_output_volume = 9;
+
+void gwenesis_io_get_buttons() {
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+
+void gen_Init(void)
+{
+  emu_printf("gen_Init");  
+  emu_printf("gen_Init done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void gen_Input(int click) {
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();    
+}
+
+extern void * emu_LineBuffer(int line);
+
+void gen_Start(char * filename)
+{
+  emu_printf("gen_Start");
+
+  int size = flash_load(filename);
+
+  load_cartridge((uintptr_t)flash_start);
+  power_on();
+  reset_emulation();
+  gwenesis_vdp_set_buffer((uint8_t *) emu_LineBuffer(0));
+
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND  
+  emu_sndInit();
+#endif  
+#else
+#endif
+
+  emu_printf("gen_Start done");
+}
+
+int start_time = 0;
+int frame, frame_cnt = 0;
+int frame_timer_start = 0;
+
+/* Clocks and synchronization */
+/* system clock is video clock */
+int system_clock;
+
+unsigned int lines_per_frame = LINES_PER_FRAME_NTSC; //262; /* NTSC: 262, PAL: 313 */
+int scan_line;
+unsigned int frame_counter = 0;
+unsigned int drawFrame = 1;
+
+extern unsigned char gwenesis_vdp_regs[0x20];
+extern unsigned int gwenesis_vdp_status;
+extern unsigned int screen_width, screen_height;
+extern int hint_pending;
+
+void gen_Step(void) {
+        /* Eumulator loop */
+        int hint_counter = gwenesis_vdp_regs[10];
+
+        const bool is_pal = REG1_PAL;
+        screen_width = REG12_MODE_H40 ? 320 : 256;
+        screen_height = is_pal ? 240 : 224;
+        lines_per_frame = is_pal ? LINES_PER_FRAME_PAL : LINES_PER_FRAME_NTSC;
+
+        // graphics_set_buffer(buffer, screen_width, screen_height);
+        // TODO: move to separate function graphics_set_dimensions ?
+//        graphics_set_buffer((uint8_t*)SCREEN, screen_width, screen_height);
+//        graphics_set_offset(screen_width != 320 ? 32 : 0, screen_height != 240 ? 8 : 0);
+        gwenesis_vdp_render_config();
+
+        zclk = 0;
+        /* Reset the difference clocks and audio index */
+        system_clock = 0;
+        sn76489_clock = 0;
+        sn76489_index = 0;
+        scan_line = 0;
+         if (z80_enable_mode == 1)
+            z80_run(lines_per_frame * VDP_CYCLES_PER_LINE);
+  
+        while (scan_line < lines_per_frame) {
+            /* CPUs */
+            m68k_run(system_clock + VDP_CYCLES_PER_LINE);
+            if (z80_enable_mode == 2)
+                    z80_run(system_clock + VDP_CYCLES_PER_LINE);
+            /* Video */
+            // Interlace mode
+            if (drawFrame && !interlace || (frame % 2 == 0 && scan_line % 2) || scan_line % 2 == 0) {
+                if (scan_line < 200)
+                gwenesis_vdp_render_line(scan_line); /* render scan_line */
+            }
+
+            // On these lines, the line counter interrupt is reloaded
+            if (scan_line == 0 || scan_line > screen_height) {
+                hint_counter = REG10_LINE_COUNTER;
+            }
+
+            // interrupt line counter
+            if (--hint_counter < 0) {
+                if (REG0_LINE_INTERRUPT != 0 && scan_line <= screen_height) {
+                    hint_pending = 1;
+                    if ((gwenesis_vdp_status & STATUS_VIRQPENDING) == 0)
+                        m68k_update_irq(4);
+                }
+                hint_counter = REG10_LINE_COUNTER;
+            }
+
+            scan_line++;
+
+            // vblank begin at the end of last rendered line
+            if (scan_line == screen_height) {
+                if (REG1_VBLANK_INTERRUPT != 0) {
+                    gwenesis_vdp_status |= STATUS_VIRQPENDING;
+                    m68k_set_irq(6);
+                }
+                z80_irq_line(1);
+            }
+
+            if (!is_pal && scan_line == screen_height + 1) {
+                z80_irq_line(0);
+                // FRAMESKIP every 3rd frame
+                drawFrame = frameskip && frame % 3 != 0;
+                // if (frameskip && frame % 3 == 0) {
+                //     drawFrame = 0;
+                // } else {
+                //     drawFrame = 1;
+                // }
+            }
+
+            system_clock += VDP_CYCLES_PER_LINE;
+
+
+        }
+/*
+        frame++;
+        if (limit_fps) {
+            frame_cnt++;
+            if (frame_cnt == (is_pal ? 5 : 6)) {
+                while (time_us_64() - frame_timer_start < (is_pal ? 20000 * 5 : 16666 * 6)) {
+                    busy_wait_at_least_cycles(10);
+                }; // 60 Hz
+                frame_timer_start = time_us_64();
+                frame_cnt = 0;
+            }
+        }
+*/
+#if HDMI | SOFTTV | TV
+//        if (audio_enabled)
+//            gwenesis_SN76489_run(REG1_PAL ? LINES_PER_FRAME_PAL : LINES_PER_FRAME_NTSC * VDP_CYCLES_PER_LINE);
+#endif
+        // ym2612_run(262 * VDP_CYCLES_PER_LINE);
+        /*
+        gwenesis_SN76489_run(262 * VDP_CYCLES_PER_LINE);
+        ym2612_run(262 * VDP_CYCLES_PER_LINE);
+        static int16_t snd_buf[GWENESIS_AUDIO_BUFFER_LENGTH_NTSC * 2];
+        for (int h = 0; h < ym2612_index * 2 * GWENESIS_AUDIO_SAMPLING_DIVISOR; h++) {
+            snd_buf[h] = (gwenesis_sn76489_buffer[h / 2 / GWENESIS_AUDIO_SAMPLING_DIVISOR]) << 3;
+        }
+        i2s_dma_write(&i2s_config, snd_buf);*/
+        // reset m68k cycles to the begin of next frame cycle
+        m68k.cycles -= system_clock;
+
+        /* copy audio samples for DMA */
+        //gwenesis_sound_submit();
+
+
+/*
+  uint32_t buttons = 0;
+  if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+    buttons |= JOY_LEFT;
+  }
+  if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+    buttons |= JOY_RIGHT;
+  }
+  if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+    buttons |= JOY_UP;
+  }
+  if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+    buttons |= JOY_DOWN;
+  }  
+  if ( k & MASK_JOY2_BTN) {
+    buttons |= JOY_A;
+  }
+
+  if (k & MASK_KEY_USER1)  buttons |= JOY_B;
+  //if (k & MASK_KEY_USER3)  buttons |= JOY_SELECT;
+  if (k & MASK_KEY_USER2)  buttons |= JOY_RUN;
+*/          
+
+  //psg_update((int16_t *) audio_buffer, AUDIO_BUFFER_LENGTH, 0xff);
+  //i2s_dma_write(&i2s_config, (const int16_t *) audio_buffer);
+
+  //emu_DrawVsync();   
+}
+
+void SND_Process(void *stream, int len) {
+//  psg_update((int16*)stream, 0, len);  
+} 
diff --git a/MCUME_pico2/picogen/emu.h b/MCUME_pico2/picogen/emu.h
new file mode 100644
index 0000000..960a514
--- /dev/null
+++ b/MCUME_pico2/picogen/emu.h
@@ -0,0 +1,5 @@
+extern void gen_Init(void);
+extern void gen_Step(void);
+extern void gen_Start(char * filename);
+extern void gen_Input(int click);
+
diff --git a/MCUME_pico2/picogen/emucfg.h b/MCUME_pico2/picogen/emucfg.h
new file mode 100644
index 0000000..ac5770e
--- /dev/null
+++ b/MCUME_pico2/picogen/emucfg.h
@@ -0,0 +1,103 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+
+// Title:     <                                        >
+#define TITLE "           Genesis Emulator             "
+#define ROMSDIR "gen"
+
+#define emu_Init(ROM) {gen_Init(); gen_Start(ROM);}
+#define emu_Step(x) {gen_Step();}
+#define emu_Input(x) {gen_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.c b/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.c
new file mode 100755
index 0000000..9922272
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.c
@@ -0,0 +1,649 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <ctype.h>
+
+#include "../cpus/M68K/m68k.h"
+
+#include "../sound/z80inst.h"
+#include "gwenesis_bus.h"
+
+#include <gwenesis/sound/gwenesis_sn76489.h>
+#include <gwenesis/sound/ym2612.h>
+
+#include "../io/gwenesis_io.h"
+#include "../vdp/gwenesis_vdp.h"
+#include "../savestate/gwenesis_savestate.h"
+
+#pragma GCC optimize("Ofast")
+
+#define BUS_DISABLE_LOGGING 1
+
+uint8_t GWENESIS_AUDIO_SAMPLING_DIVISOR = 6;
+
+#if !BUS_DISABLE_LOGGING
+#include <stdarg.h>
+void bus_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%04x hc:%04x hv:%04x ", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter(),gwenesis_vdp_hvcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define bus_log(...)
+#endif
+
+// Setup M68k memories ROM & RAM
+//#include "rom_manager.h"
+const unsigned char* ROM_DATA; // 68K Main Program (uncompressed)
+// const unsigned char* ROM_METADATA; // 68K Main Program (uncompressed)
+//unsigned char* M68K_RAM=(void *)(uint32_t)(0); // 68K RAM
+//unsigned char* M68K_RAM = NULL; // 68K RAM
+unsigned char M68K_RAM[MAX_RAM_SIZE]; // 68K RAM
+
+// Setup Z80 Memory
+//unsigned char* ZRAM = NULL; // Z80 RAM
+unsigned char ZRAM[MAX_Z80_RAM_SIZE]; // Z80 RAM
+unsigned char TMSS[0x4];
+extern unsigned short gwenesis_vdp_status;
+
+extern int audio_enabled;
+
+// TMSS
+int tmss_state = 0;
+int tmss_count = 0;
+
+/******************************************************************************
+ *
+ *   Load a Sega Genesis Cartridge into CPU Memory
+ *
+ ******************************************************************************/
+
+void load_cartridge(uintptr_t rom) {
+    ROM_DATA = (const unsigned char *)rom;
+    // Clear all volatile memory
+    memset(M68K_RAM, 0, MAX_RAM_SIZE);
+    memset(ZRAM, 0, MAX_Z80_RAM_SIZE);
+
+    // Set Z80 Memory as Z80_RAM
+    z80_set_memory(ZRAM);
+
+    z80_pulse_reset();
+
+
+    set_region();
+}
+
+/******************************************************************************
+ *
+ *   Power ON the CPU
+ *   Initialize 68K, Z80 and YM2612 Cores
+ *
+ ******************************************************************************/
+void power_on() {
+    // Set M68K CPU as original MOTOROLA 68000
+    //m68k_set_cpu_type(M68K_CPU_TYPE_68000);
+    // Initialize M68K CPU
+    m68k_init();
+    // Initialize Z80 CPU
+    z80_start();
+
+    // Initialize YM2612 chip
+    YM2612Init();
+    YM2612Config(9);
+    // Initialize PSG SN76489 chip
+    //CLOCK_NTSC      = 3579545,
+    //CLOCK_PAL       = 3546895,
+    // CLOCK_NTSC_SMS1 = 3579527
+
+    //  if (mode_pal) {
+    //     gwenesis_SN76489_Init(3546895, GWENESIS_AUDIO_BUFFER_LENGTH_PAL*50,AUDIO_FREQ_DIVISOR);
+    //   } else{
+    //     gwenesis_SN76489_Init(3579545, GWENESIS_AUDIO_BUFFER_LENGTH_NTSC*60,AUDIO_FREQ_DIVISOR);
+    //   }
+
+    gwenesis_SN76489_Init(3579545, GWENESIS_AUDIO_BUFFER_LENGTH_NTSC * 60,AUDIO_FREQ_DIVISOR);
+}
+
+/******************************************************************************
+ *
+ *   Reset the CPU Emulation
+ *   Send a pulse reset to 68K, Z80 and YM2612 Cores
+ *
+ ******************************************************************************/
+void reset_emulation() {
+    // Send a reset pulse to Z80 CPU
+    z80_pulse_reset();
+    // Send a reset pulse to Z80 M68K
+    m68k_pulse_reset();
+    // Send a reset pulse to YM2612 chip
+    YM2612ResetChip();
+
+    // Send a reset pulse to SEGA 315-5313 chip
+    gwenesis_vdp_reset();
+    gwenesis_SN76489_Reset();
+}
+
+/******************************************************************************
+ *
+ *   Set Region
+ *   Look at ROM to set console compatible region
+ *
+ ******************************************************************************/
+void set_region() {
+    /*
+      old style : JUE characters
+      J : Domestic 60Hz (Asia)
+      U : Oversea  60Hz (USA)
+      E : Oversea  50Hz (Europe)
+
+      new style : 1st character
+      bit 0 : +1 Domestic 60Hz (Asia)
+      bit 1 : +2 Domestc  50Hz (Asia)
+      bit 2:  +4 Oversea  60Hz (USA)
+      bit 3:  +4 Oversea  50Hz (Europe)
+    */
+
+    // extern int mode_pal;
+
+    int country = 0;
+
+    char rom_str[3];
+
+    printf("ROM game  : ");
+    for (int j = 0; j < 48; j++) printf("%c", (char)FETCH8ROM(0x150+j));
+    printf("\n");
+
+    rom_str[0] = FETCH8ROM(0x1F0);
+    rom_str[1] = FETCH8ROM(0x1F1);
+    rom_str[2] = FETCH8ROM(0x1F2);
+
+    printf("ROM region:%c%c%c (0x%02x 0x%02x 0x%02x)\n", rom_str[0], rom_str[1], rom_str[2], rom_str[0], rom_str[1],
+           rom_str[2]);
+
+    /* from Gens */
+    if (!memcmp(rom_str, "eur", 3)) country |= 8;
+    else if (!memcmp(rom_str, "EUR", 3)) country |= 8;
+    else if (!memcmp(rom_str, "Europe", 3)) country |= 8;
+    else if (!memcmp(rom_str, "jap", 3)) country |= 1;
+    else if (!memcmp(rom_str, "JAP", 3)) country |= 1;
+    else if (!memcmp(rom_str, "usa", 3)) country |= 4;
+    else if (!memcmp(rom_str, "USA", 3)) country |= 4;
+    else {
+        int i;
+        unsigned char c;
+
+        /* look for each characters */
+        for (i = 0; i < 3; i++) {
+            c = rom_str[i];
+
+            if (c == 'E' || c == 'e') country |= 8;
+            else if (c == 'U') country |= 4;
+            else if (c == 'J' || c == 'j') country |= 1;
+            else if (c == 'K' || c == 'k') country |= 1;
+            else if (c < 16) country |= c;
+            else if ((c >= '0') && (c <= '9')) country |= c - '0';
+            else if ((c >= 'A') && (c <= 'F')) country |= c - 'A' + 10;
+        }
+    }
+    printf("country code=%01x : ", country);
+    /* set default console region (USA > EUROPE > JAPAN) */
+    /*
+    IO REG0	:	MODE 	VMOD 	DISK 	RSV 	VER3 	VER2 	VER1 	VER0
+    MODE (R) 	0: Domestic Model
+                1: Overseas Model
+    VMOD (R) 	0: NTSC CPU clock 7.67 MHz
+                1: PAL CPU clock 7.60 MHz
+    */
+
+    /* EUROPE 50Hz */
+    if (country & 8) {
+        printf("Oversea-PAL Europe 50Hz\n");
+        gwenesis_io_set_reg(0, 0xC1);
+        //  gwenesis_vdp_status |= 0x1;
+        //mode_pal = 1;
+        return;
+    }
+    /* USA 60Hz*/
+    if (country & 4) {
+        printf("Oversea-NTSC USA 60Hz\n");
+        gwenesis_io_set_reg(0, 0x81);
+        //   gwenesis_vdp_status &= 0xFFFE;
+        // mode_pal = 0;
+        return;
+    }
+
+    /* set Asia 60HZ */
+    if (country & 1) {
+        printf("Domestic-NTSC Asia 60Hz\n");
+        gwenesis_io_set_reg(0, 0x1);
+        //  gwenesis_vdp_status &= 0xFFFE;
+        //mode_pal = 0;
+        return;
+    }
+    printf("Oversea-NTSC USA 60Hz no detection>> default mode\n");
+    gwenesis_io_set_reg(0, 0x81);
+    // gwenesis_vdp_status &= 0xFFFE;
+    // mode_pal = 0;
+}
+
+/******************************************************************************
+ *
+ *   Main memory address mapper
+ *   Map all main memory region address for CPU program
+ *   68K Access to Z80 Memory
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_map_z80_address(unsigned int address) {
+    unsigned int range = (address & 0xF000);
+    switch (range) {
+        case 0:
+        case 0x1000:
+            return Z80_RAM_ADDR;
+        case 0x2000:
+        case 0x3000:
+            return Z80_RAM_ADDR1K;
+        case 0x4000:
+            return Z80_YM2612_ADDR;
+        case 0x6000:
+            return Z80_BANK_ADDR;
+        case 0x7000:
+            return Z80_SN76489_ADDR;
+        default:
+            bus_log(__FUNCTION__, "no map Z80 %x", address);
+            assert(0);
+            return NONE;
+    }
+}
+
+/******************************************************************************
+ *
+ *   IO memory address mapper
+ *   Map all input/output region address for CPU program
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_map_io_address(unsigned int address) {
+    unsigned int range = (address & 0x1000);
+    switch (range) {
+        case 0: return IO_CTRL;
+        case 0x1000: return Z80_CTRL;
+        default:
+            // if (address >= 0xa14000 && address < 0xa11404)
+            // return (tmss_state == 0) ? TMSS_CTRL : NONE;
+            bus_log(__FUNCTION__, "no map io %x", address);
+
+            return NONE;
+    }
+}
+
+/******************************************************************************
+ *
+ *   Main memory address mapper
+ *   Map all main memory region address for CPU program
+ *
+ ******************************************************************************/
+
+static inline
+unsigned int gwenesis_bus_map_address(unsigned int address) {
+    // Mask address page
+    unsigned int range = (address & 0xFF0000) >> 16;
+
+    // Check mask and select memory type
+    if (range < 0x80) //        ROM ADDRESS 0x000000 - 0x3FFFFF
+        return ROM_ADDR;
+    if (range == 0xA0) // Z80 ADDRESS 0xA00000 - 0xA0FFFF
+        return gwenesis_bus_map_z80_address(address);
+    if (range == 0xA1) //                  IO ADDRESS  0xA10000 - 0xA1FFFF
+        return gwenesis_bus_map_io_address(address);
+    if (range == 0xC0) // VDP ADDRESS 0xC00000 - 0xDFFFFFF
+        return VDP_ADDR;
+    if (range == 0xFF) // RAM ADDRESS 0xE00000 - 0xFFFFFFF
+        return RAM_ADDR;
+
+
+    // If not a valid address return 0
+    bus_log(__FUNCTION__, "M68K > ?? unnmap address %x", address);
+    //assert(0);
+    return NONE;
+}
+
+/******************************************************************************
+ *
+ *   Main read address routine
+ *   Write an value to memory mapped on specified address
+ *
+ ******************************************************************************/
+static inline unsigned int gwenesis_bus_read_memory_8(unsigned int address) {
+    bus_log(__FUNCTION__, "read8  %x", address);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            return gwenesis_vdp_read_memory_8(address);
+
+        case ROM_ADDR:
+            return FETCH8ROM(address);
+
+        case RAM_ADDR:
+            return FETCH8RAM(address);
+
+        case IO_CTRL:
+            return gwenesis_io_read_ctrl(address & 0x1F);
+
+        case Z80_CTRL:
+            return z80_read_ctrl(address & 0xFFFF);
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            return ZRAM[address & 0x1FFF];
+
+        case Z80_YM2612_ADDR:
+            return audio_enabled ? YM2612Read(m68k_cycles_master()) : 0x00;
+
+        case Z80_SN76489_ADDR:
+            return 0xff;
+
+        case Z80_BANK_ADDR:
+            return 0xff;
+
+        case TMSS_CTRL:
+            bus_log(__FUNCTION__, "TMS");
+            if (tmss_state == 0)
+                return TMSS[address & 0x4];
+            return 0xFF;
+
+        default:
+            bus_log(__FUNCTION__, " default read 8 %x", address);
+            return 0x00;
+    }
+    return 0x00;
+}
+
+static inline unsigned int gwenesis_bus_read_memory_16(unsigned int address) {
+    bus_log(__FUNCTION__, "read16 %x", address);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            return gwenesis_vdp_read_memory_16(address);
+
+        case RAM_ADDR:
+            return FETCH16RAM(address);
+
+        case ROM_ADDR:
+            return FETCH16ROM(address);
+
+        case IO_CTRL:
+            return gwenesis_io_read_ctrl(address & 0x1F);
+
+        case Z80_CTRL:
+            //  ret_value = z80_read_ctrl(address & 0xFFFF);
+            // return ret_value | ret_value << 8;
+            address &= 0xFFFF;
+            return (z80_read_ctrl(address) << 8) | z80_read_ctrl(address | 1);
+
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            return ZRAM[address & 0X1FFF] | (ZRAM[address & 0X1FFF] << 8);
+
+        case Z80_YM2612_ADDR: {
+            if (audio_enabled) {
+                unsigned int ret_value = YM2612Read(m68k_cycles_master());
+                return ret_value | ret_value << 8;
+            }
+            return 0x00;
+        }
+
+
+        case Z80_SN76489_ADDR:
+            return 0xff;
+
+        case Z80_BANK_ADDR:
+            return 0xff;
+
+        default:
+            bus_log(__FUNCTION__, "read mem 16 default %x", address);
+            return (gwenesis_bus_read_memory_8(address) << 8) |
+                   gwenesis_bus_read_memory_8(address + 1);
+    }
+    return 0x00;
+}
+
+/******************************************************************************
+ *
+ *   Main write address routine
+ *   Write an value to memory mapped on specified address
+ *
+ ******************************************************************************/
+static inline void gwenesis_bus_write_memory_8(unsigned int address,
+                                               unsigned int value) {
+    bus_log(__FUNCTION__, "write8  @%x:%x", address, value);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            gwenesis_vdp_write_memory_16(address & ~1, (value << 8) | value);
+            return;
+
+        case RAM_ADDR:
+            WRITE8RAM(address, value);
+            return;
+
+        case IO_CTRL:
+            gwenesis_io_write_ctrl(address & 0x1F, value);
+            return;
+
+        case Z80_CTRL:
+            z80_write_ctrl(address & 0x1FFF, value);
+            return;
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            ZRAM[address & 0x1FFF] = value;
+            return;
+
+        case Z80_YM2612_ADDR:
+            bus_log(__FUNCTION__, "CPUZ80PSG8 ,m68kclk= %d", m68k_cycles_master());
+            if (audio_enabled)
+                YM2612Write(address & 0x3, value & 0Xff, m68k_cycles_master());
+
+            return;
+
+        case Z80_SN76489_ADDR:
+            bus_log(__FUNCTION__, "CPUZ80FM8  ,m68kclk= %d", m68k_cycles_master());
+            if (audio_enabled)
+                gwenesis_SN76489_Write(value & 0Xff, m68k_cycles_master());
+            return;
+
+        case Z80_BANK_ADDR:
+            //TODO
+            return;
+
+        case TMSS_CTRL:
+
+            if (tmss_state == 0) {
+                TMSS[address & 0x4] = value;
+                tmss_count++;
+                if (tmss_count == 4)
+                    tmss_state = 1;
+            }
+            return;
+
+
+        default:
+            //printf("write(%x, %x)\n", address, value);
+            return;
+    }
+    return;
+}
+
+extern bool sn76489_enabled;
+
+static inline void gwenesis_bus_write_memory_16(unsigned int address,
+                                                unsigned int value) {
+    bus_log(__FUNCTION__, "write16  @%x:%x", address, value);
+
+    switch (gwenesis_bus_map_address(address)) {
+        case VDP_ADDR:
+            gwenesis_vdp_write_memory_16(address, value);
+            return;
+
+        case RAM_ADDR:
+            WRITE16RAM(address, value);
+            return;
+
+        case Z80_RAM_ADDR:
+        case Z80_RAM_ADDR1K:
+            ZRAM[address & 0X1FFF] = value >> 8;
+            return;
+
+        case IO_CTRL:
+            gwenesis_io_write_ctrl(address & 0x1F, value);
+            return;
+
+        case Z80_CTRL:
+            z80_write_ctrl(address & 0xFFFF, value >> 8);
+            return;
+
+        case Z80_YM2612_ADDR:
+            bus_log(__FUNCTION__, "CZYM16 ,mclk=%d", m68k_cycles_master());
+            if (audio_enabled)
+                YM2612Write(address & 0x3, value >> 8, m68k_cycles_master());
+
+            return;
+
+        case Z80_SN76489_ADDR:
+            bus_log(__FUNCTION__, "CZSN16 ,mclk=%d", m68k_cycles_master());
+            if (audio_enabled && sn76489_enabled)
+                gwenesis_SN76489_Write(value >> 8, m68k_cycles_master());
+            return;
+
+        default:
+            bus_log(__FUNCTION__, "write mem 16 default %x ", address);
+            gwenesis_bus_write_memory_8(address, (value >> 8) & 0xff);
+            gwenesis_bus_write_memory_8(address + 1, (value) & 0xff);
+
+            return;
+    }
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R8
+ *   Read an address from memory mapped and return value as byte
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_8(unsigned int address) {
+    //  if ((address &  0xFF0000 ) == 0xFF0000) return FETCH8RAM(address);
+    return gwenesis_bus_read_memory_8(address);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R16
+ *   Read an address from memory mapped and return value as word
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_16(unsigned int address) {
+    //   if ((address &  0xFF0000 ) == 0xFF0000) return FETCH16RAM(address);
+    return gwenesis_bus_read_memory_16(address);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU read address R32
+ *   Read an address from memory mapped and return value as long
+ *
+ ******************************************************************************/
+unsigned int m68k_read_memory_32(unsigned int address) {
+    //  if ((address &  0xFF0000 ) == 0xFF0000) return FETCH32RAM(address);
+    return (gwenesis_bus_read_memory_16(address) << 16) | gwenesis_bus_read_memory_16(address + 2);
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W8
+ *   Write an value as byte to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_8(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE8RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_8(address, value);
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W16
+ *   Write an value as word to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_16(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE16RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_16(address, value);
+    return;
+}
+
+/******************************************************************************
+ *
+ *   68K CPU write address W32
+ *   Write an value as word to memory mapped on specified address
+ *
+ ******************************************************************************/
+void m68k_write_memory_32(unsigned int address, unsigned int value) {
+    // if ((address & 0xFF0000) == 0xFF0000) {
+    //   WRITE32RAM(address, value);
+    //   return;
+    // }
+    gwenesis_bus_write_memory_16(address, (value >> 16) & 0xffff);
+    gwenesis_bus_write_memory_16(address + 2, (value) & 0xffff);
+
+    return;
+}
+
+unsigned int m68k_read_disassembler_16(unsigned int address) {
+    return m68k_read_memory_16(address);
+}
+
+unsigned int m68k_read_disassembler_32(unsigned int address) {
+    return m68k_read_memory_32(address);
+}
+
+void gwenesis_bus_save_state() {
+
+}
+
+void gwenesis_bus_load_state() {
+
+}
diff --git a/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.h b/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.h
new file mode 100755
index 0000000..12c092f
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/bus/gwenesis_bus.h
@@ -0,0 +1,98 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_bus_H_
+#define _gwenesis_bus_H_
+
+#pragma once
+
+#include <stdio.h>
+#include <string.h>
+
+#define MAX_ROM_SIZE 0x800000
+#define MAX_RAM_SIZE 0x10000
+#define MAX_Z80_RAM_SIZE 8192
+
+// NTSC PAL timings
+#define MCLOCK_PAL 53203424
+#define MCLOCK_NTSC 53693175
+
+#define MCYCLES_PER_FRAME_NTSC 896040
+#define MCYCLES_PER_FRAME_PAL 1067040
+#define LINES_PER_FRAME_NTSC 262
+#define LINES_PER_FRAME_PAL 313
+
+#define GWENESIS_REFRESH_RATE_NTSC 60
+#define GWENESIS_AUDIO_FREQ_NTSC 53267
+
+#define GWENESIS_REFRESH_RATE_PAL 50
+#define GWENESIS_AUDIO_FREQ_PAL 52781
+
+#define Z80_FREQ_DIVISOR 14     // Frequency divisor to Z80 clock
+#define VDP_CYCLES_PER_LINE 3420// VDP Cycles per Line
+#define GWENESIS_SCREEN_WIDTH 320
+#define GWENESIS_SCREEN_HEIGHT 240
+
+extern uint8_t GWENESIS_AUDIO_SAMPLING_DIVISOR; // Audio quality (i.e. sampling rate) 1: best ... 10: poor
+
+#define AUDIO_FREQ_DIVISOR 1009  //1009
+#define GWENESIS_AUDIO_BUFFER_LENGTH_NTSC 888
+#define GWENESIS_AUDIO_BUFFER_LENGTH_PAL 1056
+
+/* Audio buffer length */
+
+enum mapped_address
+{
+    NONE = 0,
+    ROM_ADDR,
+    ROM_ADDR_MIRROR,
+    Z80_RAM_ADDR,
+    Z80_RAM_ADDR1K,
+    Z80_YM2612_ADDR,
+    Z80_BANK_ADDR,
+    Z80_VDP_ADDR,
+    Z80_SN76489_ADDR,
+    IO_CTRL,
+    Z80_CTRL,
+    TMSS_CTRL,
+    VDP_ADDR,
+    RAM_ADDR
+};
+
+enum gwenesis_bus_pad_button
+{
+    PAD_UP,
+    PAD_DOWN,
+    PAD_LEFT,
+    PAD_RIGHT,
+    PAD_B,
+    PAD_C,
+    PAD_A,
+    PAD_S,
+};
+
+void load_cartridge(uintptr_t rom);
+
+void power_on();
+void reset_emulation();
+void set_region();
+
+void gwenesis_bus_save_state();
+void gwenesis_bus_load_state();
+
+#endif
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68k.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68k.h
new file mode 100755
index 0000000..4d7f75e
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68k.h
@@ -0,0 +1,462 @@
+#ifndef M68K__HEADER
+#define M68K__HEADER
+
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.32
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright Karl Stenerud.  All rights reserved.
+ *
+ * This code may be freely used for non-commercial purposes as long as this
+ * copyright notice remains unaltered in the source code and any binary files
+ * containing this code in compiled form.
+ *
+ * All other licensing terms must be negotiated with the author
+ * (Karl Stenerud).
+ *
+ * The latest version of this code can be obtained at:
+ * http://kstenerud.cjb.net
+ */
+
+ /* Modified by Eke-Eke for Genesis Plus GX:
+
+    - removed unused stuff to reduce memory usage / optimize execution (multiple CPU types support, NMI support, ...)
+    - moved stuff to compile statically in a single object file
+    - implemented support for global cycle count (shared by 68k & Z80 CPU)
+    - added support for interrupt latency (Sesame's Street Counting Cafe, Fatal Rewind)
+    - added proper cycle use on reset
+    - added cycle accurate timings for MUL/DIV instructions (thanks to Jorge Cwik !) 
+    - fixed undocumented flags for DIV instructions (Blood Shot)
+    - fixed undocumented behaviors for ABCD/SBCD/NBCD instructions (thanks to flamewing for his test ROM)
+    - improved auto-vectored interrupts acknowledge cycle timing accuracy
+    - added MAIN-CPU & SUB-CPU support for Mega CD emulation
+    
+  */
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include <setjmp.h>
+#include "macros.h"
+#ifdef HOOK_CPU
+#include "cpuhook.h"
+#endif
+//#include <avr/pgmspace.h>
+
+/* ======================================================================== */
+/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */
+/* ======================================================================== */
+
+/* Check for > 32bit sizes */
+#if UINT_MAX > 0xffffffff
+  #define M68K_INT_GT_32_BIT  1
+#else
+  #define M68K_INT_GT_32_BIT  0
+#endif
+
+/* Data types used in this emulation core */
+#undef sint8
+#undef sint16
+#undef sint32
+#undef sint64
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+#undef sint
+#undef uint
+
+#define sint8  signed   char      /* ASG: changed from char to signed char */
+#define sint16 signed   short
+#define sint32 signed   int      /* AWJ: changed from long to int */
+#define uint8  unsigned char
+#define uint16 unsigned short
+#define uint32 unsigned int      /* AWJ: changed from long to int */
+
+/* signed and unsigned int must be at least 32 bits wide */
+#define sint   signed   int
+//#define uint   unsigned int
+
+
+#if M68K_USE_64_BIT
+#define sint64 signed   long long
+#define uint64 unsigned long long
+#else
+#define sint64 sint32
+#define uint64 uint32
+#endif /* M68K_USE_64_BIT */
+
+
+
+/* Allow for architectures that don't have 8-bit sizes */
+/*#if UCHAR_MAX == 0xff*/
+  #define MAKE_INT_8(A) (sint8)(A)
+/*#else
+  #undef  sint8
+  #define sint8  signed   int
+  #undef  uint8
+  #define uint8  unsigned int
+  INLINE sint MAKE_INT_8(uint value)
+  {
+    return (value & 0x80) ? value | ~0xff : value & 0xff;
+  }*/
+/*#endif *//* UCHAR_MAX == 0xff */
+
+
+/* Allow for architectures that don't have 16-bit sizes */
+/*#if USHRT_MAX == 0xffff*/
+  #define MAKE_INT_16(A) (sint16)(A)
+/*#else
+  #undef  sint16
+  #define sint16 signed   int
+  #undef  uint16
+  #define uint16 unsigned int
+  INLINE sint MAKE_INT_16(uint value)
+  {
+    return (value & 0x8000) ? value | ~0xffff : value & 0xffff;
+  }*/
+/*#endif *//* USHRT_MAX == 0xffff */
+
+
+/* Allow for architectures that don't have 32-bit sizes */
+/*#if UINT_MAX == 0xffffffff*/
+  #define MAKE_INT_32(A) (sint32)(A)
+/*#else
+  #undef  sint32
+  #define sint32  signed   int
+  #undef  uint32
+  #define uint32  unsigned int
+  INLINE sint MAKE_INT_32(uint value)
+  {
+    return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff;
+  }*/
+/*#endif *//* UINT_MAX == 0xffffffff */
+
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/*** BZHXX ***/
+#ifndef FALSE
+#define FALSE 0
+#define TRUE 1
+#endif
+
+#define ROM_SWAP
+#define RAM_SWAP
+
+// 8/16/32 bits access to RAM/ROM
+
+extern const unsigned char *ROM_DATA;
+extern const unsigned char *ROM_METADATA;
+//extern unsigned char* M68K_RAM;
+extern unsigned char M68K_RAM[];
+
+// ROM needs to be converted for this to work!
+#define FETCH8ROM(A)    (unsigned char)  ROM_DATA[ A^1 ]
+#define FETCH16ROM(A)  ( (unsigned short)  (*((unsigned short *) &ROM_DATA[A])) )
+#define FETCH32ROM(A) ( (*(unsigned short *)(&ROM_DATA[(A+2)])) | ((*(unsigned short *)(&ROM_DATA[A])) << 16))
+
+#define FETCH8RAM(A)         (unsigned char)  M68K_RAM[ (A ^ 1) & 0xFFFF]
+#define FETCH16RAM(A)   ( (unsigned short)  (*((unsigned short *) &M68K_RAM[A&0XFFFF])) )
+#define FETCH32RAM(A) ( (*(unsigned short *)(&M68K_RAM[(A+2)&0XFFFF])) | ((*(unsigned short *)(&M68K_RAM[A&0XFFFF])) << 16))
+
+#define WRITE8RAM(A, V)   M68K_RAM[ (A ^ 1) & 0xFFFF ] =  V
+#define WRITE16RAM(A, V)  ( *((unsigned short *) &M68K_RAM[ A & 0XFFFF ]) = V )
+// RAM needs to be cyclically accessible (i.e. addresses wrap around)
+#define WRITE32RAM(A, V)  ( *((unsigned short *) &M68K_RAM[  A      & 0XFFFF ]) = V >> 16); \
+                          ( *((unsigned short *) &M68K_RAM[ (A + 2) & 0XFFFF ]) = V & 0xffff); \
+
+#define m68k_read_immediate_16(A) ( ( (A) & 0x800000) ? FETCH16RAM((A)) : FETCH16ROM((A)) )
+#define m68k_read_immediate_32(A) ( ( (A) & 0x800000) ? FETCH32RAM((A)) : FETCH32ROM((A)) )
+
+#define m68k_read_pcrelative_8(A) ( FETCH8ROM((A)) )
+#define m68k_read_pcrelative_16(A) ( FETCH16ROM((A)) )
+#define m68k_read_pcrelative_32(A) ( FETCH32ROM((A)) )
+
+/* Read from anywhere */
+unsigned int  m68k_read_memory_8(unsigned int address);
+unsigned int  m68k_read_memory_16(unsigned int address);
+unsigned int  m68k_read_memory_32(unsigned int address);
+
+/* Read data immediately following the PC */
+// unsigned int  m68k_read_immediate_16(unsigned int address);
+// unsigned int  m68k_read_immediate_32(unsigned int address);
+
+/* Read data relative to the PC */
+//unsigned int  m68k_read_pcrelative_8(unsigned int address);
+//unsigned int  m68k_read_pcrelative_16(unsigned int address);
+//unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+/* Memory access for the disassembler */
+unsigned int m68k_read_disassembler_8  (unsigned int address);
+unsigned int m68k_read_disassembler_16 (unsigned int address);
+unsigned int m68k_read_disassembler_32 (unsigned int address);
+
+/* Write to anywhere */
+void m68k_write_memory_8(unsigned int address, unsigned int value);
+void m68k_write_memory_16(unsigned int address, unsigned int value);
+void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+/*** BZHXX ***/
+/* ======================================================================== */
+
+/* There are 7 levels of interrupt to the 68K.
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ */
+#define M68K_IRQ_NONE 0
+#define M68K_IRQ_1    1
+#define M68K_IRQ_2    2
+#define M68K_IRQ_3    3
+#define M68K_IRQ_4    4
+#define M68K_IRQ_5    5
+#define M68K_IRQ_6    6
+#define M68K_IRQ_7    7
+
+
+/* Special interrupt acknowledge values.
+ * Use these as special returns from the interrupt acknowledge callback
+ * (specified later in this header).
+ */
+
+/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
+ * This happens in a real 68K if VPA or AVEC is asserted during an interrupt
+ * acknowledge cycle instead of DTACK.
+ */
+#define M68K_INT_ACK_AUTOVECTOR    0xffffffff
+
+/* Causes the spurious interrupt vector (0x18) to be taken
+ * This happens in a real 68K if BERR is asserted during the interrupt
+ * acknowledge cycle (i.e. no devices responded to the acknowledge).
+ */
+#define M68K_INT_ACK_SPURIOUS      0xfffffffe
+
+
+/* Registers used by m68k_get_reg() and m68k_set_reg() */
+typedef enum
+{
+  /* Real registers */
+  M68K_REG_D0,    /* Data registers */
+  M68K_REG_D1,
+  M68K_REG_D2,
+  M68K_REG_D3,
+  M68K_REG_D4,
+  M68K_REG_D5,
+  M68K_REG_D6,
+  M68K_REG_D7,
+  M68K_REG_A0,    /* Address registers */
+  M68K_REG_A1,
+  M68K_REG_A2,
+  M68K_REG_A3,
+  M68K_REG_A4,
+  M68K_REG_A5,
+  M68K_REG_A6,
+  M68K_REG_A7,
+  M68K_REG_PC,    /* Program Counter */
+  M68K_REG_SR,    /* Status Register */
+  M68K_REG_SP,    /* The current Stack Pointer (located in A7) */
+  M68K_REG_USP,   /* User Stack Pointer */
+  M68K_REG_ISP,   /* Interrupt Stack Pointer */
+
+#if M68K_EMULATE_PREFETCH
+  /* Assumed registers */
+  /* These are cheat registers which emulate the 1-longword prefetch
+   * present in the 68000 and 68010.
+   */
+  M68K_REG_PREF_ADDR,  /* Last prefetch address */
+  M68K_REG_PREF_DATA,  /* Last prefetch data */
+#endif
+
+  /* Convenience registers */
+  M68K_REG_IR    /* Instruction register */
+} m68k_register_t;
+
+
+/* 68k memory map structure */
+typedef struct 
+{
+  unsigned char *base;                             /* memory-based access (ROM, RAM) */
+  unsigned int (*read8)(unsigned int address);               /* I/O byte read access */
+  unsigned int (*read16)(unsigned int address);              /* I/O word read access */
+  void (*write8)(unsigned int address, unsigned int data);  /* I/O byte write access */
+  void (*write16)(unsigned int address, unsigned int data); /* I/O word write access */
+} cpu_memory_map;
+
+/* 68k idle loop detection */
+typedef struct
+{
+  unsigned int pc;
+  unsigned int cycle;
+  unsigned int detected;
+} cpu_idle_t;
+
+typedef struct
+{
+  cpu_memory_map memory_map[256]; /* memory mapping */
+
+  cpu_idle_t poll;      /* polling detection */
+
+  unsigned int cycles;          /* current master cycle count */
+  unsigned int cycle_end;       /* aimed master cycle count for current execution frame */
+
+  unsigned int dar[16];         /* Data and Address Registers */
+  unsigned int pc;              /* Program Counter */
+  unsigned int sp[5];           /* User and Interrupt Stack Pointers */
+  unsigned int ir;              /* Instruction Register */
+  unsigned int t1_flag;         /* Trace 1 */
+  unsigned int s_flag;          /* Supervisor */
+  unsigned int x_flag;          /* Extend */
+  unsigned int n_flag;          /* Negative */
+  unsigned int not_z_flag;      /* Zero, inverted for speedups */
+  unsigned int v_flag;          /* Overflow */
+  unsigned int c_flag;          /* Carry */
+  unsigned int int_mask;        /* I0-I2 */
+  unsigned int int_level;       /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
+  unsigned int stopped;         /* Stopped state */
+
+  unsigned int pref_addr;       /* Last prefetch address */
+  unsigned int pref_data;       /* Data in the prefetch queue */
+
+  unsigned int instr_mode;      /* Stores whether we are in instruction mode or group 0/1 exception mode */
+  unsigned int run_mode;        /* Stores whether we are processing a reset, bus error, address error, or something else */
+  unsigned int aerr_enabled;    /* Enables/deisables address error checks at runtime */
+  jmp_buf aerr_trap;    /* Address error jump */
+  unsigned int aerr_address;    /* Address error location */
+  unsigned int aerr_write_mode; /* Address error write mode */
+  unsigned int aerr_fc;         /* Address error FC code */
+
+  unsigned int tracing;         /* Tracing enable flag */
+
+  unsigned int address_space;   /* Current FC code */
+
+#ifdef M68K_OVERCLOCK_SHIFT
+  int cycle_ratio;
+#endif
+
+  /* Callbacks to host */
+  int  (*int_ack_callback)(int int_line);           /* Interrupt Acknowledge */
+  void (*reset_instr_callback)(void);               /* Called when a RESET instruction is encountered */
+  int  (*tas_instr_callback)(void);                 /* Called when a TAS instruction is encountered, allows / disallows writeback */
+  void (*set_fc_callback)(unsigned int new_fc);     /* Called when the CPU function code changes */
+} m68ki_cpu_core;
+
+/* CPU cores */
+extern m68ki_cpu_core m68k;
+
+/* ======================================================================== */
+/* ============================== CALLBACKS =============================== */
+/* ======================================================================== */
+
+/* These functions allow you to set callbacks to the host when specific events
+ * occur.  Note that you must enable the corresponding value in m68kconf.h
+ * in order for these to do anything useful.
+ * Note: I have defined default callbacks which are used if you have enabled
+ * the corresponding #define in m68kconf.h but either haven't assigned a
+ * callback or have assigned a callback of NULL.
+ */
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+/* Set the callback for an interrupt acknowledge.
+ * You must enable M68K_EMULATE_INT_ACK in m68kconf.h.
+ * The CPU will call the callback with the interrupt level being acknowledged.
+ * The host program must return either a vector from 0x02-0xff, or one of the
+ * special interrupt acknowledge values specified earlier in this header.
+ * If this is not implemented, the CPU will always assume an autovectored
+ * interrupt, and will automatically clear the interrupt request when it
+ * services the interrupt.
+ * Default behavior: return M68K_INT_ACK_AUTOVECTOR.
+ */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level));
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+/* Set the callback for the RESET instruction.
+ * You must enable M68K_EMULATE_RESET in m68kconf.h.
+ * The CPU calls this callback every time it encounters a RESET instruction.
+ * Default behavior: do nothing.
+ */
+void m68k_set_reset_instr_callback(void  (*callback)(void));
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+/* Set the callback for the TAS instruction.
+ * You must enable M68K_TAS_HAS_CALLBACK in m68kconf.h.
+ * The CPU calls this callback every time it encounters a TAS instruction.
+ * Default behavior: return 1, allow writeback.
+ */
+void m68k_set_tas_instr_callback(int  (*callback)(void));
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+/* Set the callback for CPU function code changes.
+ * You must enable M68K_EMULATE_FC in m68kconf.h.
+ * The CPU calls this callback with the function code before every memory
+ * access to set the CPU's function code according to what kind of memory
+ * access it is (supervisor/user, program/data and such).
+ * Default behavior: do nothing.
+ */
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc));
+#endif
+
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */
+/* ======================================================================== */
+
+/* Do whatever initialisations the core requires.  Should be called
+ * at least once at init time.
+ */
+extern void m68k_init(void);
+
+/* Pulse the RESET pin on the CPU.
+ * You *MUST* reset the CPU at least once to initialize the emulation
+ */
+extern void m68k_pulse_reset(void);
+
+/* Run until given cycle count is reached */
+extern void m68k_run(unsigned int cycles);
+
+/* Get current instruction execution time */
+extern int m68k_cycles(void);
+
+/* Number of cycles run so far from start of frame */
+extern int m68k_cycles_master(void);
+
+/* Number of cycles run so far from run call */
+extern int m68k_cycles_run(void);
+
+/* Set the IPL0-IPL2 pins on the CPU (IRQ).
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ * Setting IRQ to 0 will clear an interrupt request.
+ */
+extern void m68k_set_irq(unsigned int int_level);
+extern void m68k_set_irq_delay(unsigned int int_level);
+extern void m68k_update_irq(unsigned int mask);
+
+/* Halt the CPU as if you pulsed the HALT pin. */
+extern void m68k_pulse_halt(void);
+extern void m68k_clear_halt(void);
+
+/* Peek at the internals of a CPU context.  This can either be a context
+ * retrieved using m68k_get_context() or the currently running context.
+ * If context is NULL, the currently running CPU context will be used.
+ */
+extern unsigned int m68k_get_reg(m68k_register_t reg);
+
+/* Poke values into the internals of the currently running CPU context */
+extern void m68k_set_reg(m68k_register_t reg, unsigned int value);
+
+/* Load/Save state of CPU */
+extern void gwenesis_m68k_save_state();
+extern void gwenesis_m68k_load_state();
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68K__HEADER */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kconf.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kconf.h
new file mode 100755
index 0000000..d426577
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kconf.h
@@ -0,0 +1,93 @@
+#ifndef M68KCONF__HEADER
+#define M68KCONF__HEADER
+
+/* ======================================================================== */
+/* ======================== MAIN 68K CONFIGURATION ======================== */
+/* ======================================================================== */
+
+/* Configuration switches.
+ * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks.
+ * OPT_SPECIFY_HANDLER causes the core to link directly to the function
+ * or macro you specify, rather than using callback functions whose pointer
+ * must be passed in using m68k_set_xxx_callback().
+ */
+#define OPT_OFF             0
+#define OPT_ON              1
+#define OPT_SPECIFY_HANDLER 2
+
+/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a
+ * predecrement destination EA mode instead of m68k_write_32().
+ * To simulate real 68k behavior, m68k_write_32_pd() must first write the high
+ * word to [address+2], and then write the low word to [address].
+ */
+#define M68K_SIMULATE_PD_WRITES     OPT_OFF
+
+/* If ON, CPU will call the interrupt acknowledge callback when it services an
+ * interrupt.
+ * If off, all interrupts will be autovectored and all interrupt requests will
+ * auto-clear when the interrupt is serviced.
+ */
+#define M68K_EMULATE_INT_ACK        OPT_ON //OPT_SPECIFY_HANDLER
+#define M68K_INT_ACK_CALLBACK(A)    your_int_ack_handler_function(A)
+
+/* If ON, CPU will call the output reset callback when it encounters a reset
+ * instruction.
+ */
+#define M68K_EMULATE_RESET          OPT_OFF
+#define M68K_RESET_CALLBACK()       your_reset_handler_function()
+
+/* If ON, CPU will call the callback when it encounters a tas
+ * instruction.
+ */
+#define M68K_TAS_HAS_CALLBACK       OPT_OFF
+#define M68K_TAS_CALLBACK()         your_tas_handler_function()
+
+/* If ON, CPU will call the set fc callback on every memory access to
+ * differentiate between user/supervisor, program/data access like a real
+ * 68000 would.  This should be enabled and the callback should be set if you
+ * want to properly emulate the m68010 or higher. (moves uses function codes
+ * to read/write data from different address spaces)
+ */
+#define M68K_EMULATE_FC             OPT_OFF
+#define M68K_SET_FC_CALLBACK(A)     your_set_fc_handler_function(A)
+
+/* If ON, the CPU will monitor the trace flags and take trace exceptions
+ */
+#define M68K_EMULATE_TRACE          OPT_OFF
+
+/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */
+#define M68K_EMULATE_PREFETCH       OPT_OFF
+
+/* If ON, the CPU will generate address error exceptions if it tries to
+ * access a word or longword at an odd address.
+ * NOTE: This is only emulated properly for 68000 mode.
+ */
+#define M68K_EMULATE_ADDRESS_ERROR  OPT_ON
+
+/* If ON and previous option is also ON, address error exceptions will
+   also be checked when fetching instructions. Disabling this can help
+   speeding up emulation while still emulating address error exceptions
+   on other memory access if needed.
+ * NOTE: This is only emulated properly for 68000 mode.
+ */
+#define M68K_CHECK_PC_ADDRESS_ERROR OPT_OFF
+
+
+/* ----------------------------- COMPATIBILITY ---------------------------- */
+
+/* The following options set optimizations that violate the current ANSI
+ * standard, but will be compliant under the forthcoming C9X standard.
+ */
+
+
+/* If ON, the enulation core will use 64-bit integers to speed up some
+ * operations.
+*/
+#define M68K_USE_64_BIT  OPT_OFF
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCONF__HEADER */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.c b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.c
new file mode 100755
index 0000000..f14d3be
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.c
@@ -0,0 +1,455 @@
+/* ======================================================================== */
+/*                            MAIN 68K CORE                                 */
+/* ======================================================================== */
+#pragma GCC optimize("Ofast")
+#include "pico.h"
+extern int vdp_68k_irq_ack(int int_level);
+
+#define m68ki_cpu m68k
+#define MUL (7)
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#ifndef BUILD_TABLES
+  #ifndef TABLES_FULL
+    #include "m68ki_cycles.h"
+  #else
+    #include "m68ki_cycles_full.h"
+  #endif
+#endif
+
+#include "m68kconf.h"
+#include "m68kcpu.h"
+#include "m68kops.h"
+#include "../../savestate/gwenesis_savestate.h"
+
+
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+#ifdef BUILD_TABLES
+static unsigned char m68ki_cycles[0x10000];
+#endif
+
+static int irq_latency;
+
+m68ki_cpu_core m68k;
+
+
+/* ======================================================================== */
+/* =============================== CALLBACKS ============================== */
+/* ======================================================================== */
+
+/* Default callbacks used if the callback hasn't been set yet, or if the
+ * callback is set to NULL
+ */
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+/* Interrupt acknowledge */
+static int default_int_ack_callback(int int_level)
+{
+  CPU_INT_LEVEL = 0;
+  return M68K_INT_ACK_AUTOVECTOR;
+}
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+/* Called when a reset instruction is executed */
+static void default_reset_instr_callback(void)
+{
+}
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+/* Called when a tas instruction is executed */
+static int default_tas_instr_callback(void)
+{
+  return 1; // allow writeback
+}
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+/* Called every time there's bus activity (read/write to/from memory */
+static void default_set_fc_callback(unsigned int new_fc)
+{
+}
+#endif
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+/* Access the internals of the CPU */
+unsigned int m68k_get_reg(m68k_register_t regnum)
+{
+  switch(regnum)
+  {
+    case M68K_REG_D0:  return m68ki_cpu.dar[0];
+    case M68K_REG_D1:  return m68ki_cpu.dar[1];
+    case M68K_REG_D2:  return m68ki_cpu.dar[2];
+    case M68K_REG_D3:  return m68ki_cpu.dar[3];
+    case M68K_REG_D4:  return m68ki_cpu.dar[4];
+    case M68K_REG_D5:  return m68ki_cpu.dar[5];
+    case M68K_REG_D6:  return m68ki_cpu.dar[6];
+    case M68K_REG_D7:  return m68ki_cpu.dar[7];
+    case M68K_REG_A0:  return m68ki_cpu.dar[8];
+    case M68K_REG_A1:  return m68ki_cpu.dar[9];
+    case M68K_REG_A2:  return m68ki_cpu.dar[10];
+    case M68K_REG_A3:  return m68ki_cpu.dar[11];
+    case M68K_REG_A4:  return m68ki_cpu.dar[12];
+    case M68K_REG_A5:  return m68ki_cpu.dar[13];
+    case M68K_REG_A6:  return m68ki_cpu.dar[14];
+    case M68K_REG_A7:  return m68ki_cpu.dar[15];
+    case M68K_REG_PC:  return MASK_OUT_ABOVE_32(m68ki_cpu.pc);
+    case M68K_REG_SR:  return  m68ki_cpu.t1_flag        |
+                  (m68ki_cpu.s_flag << 11)              |
+                   m68ki_cpu.int_mask                   |
+                  ((m68ki_cpu.x_flag & XFLAG_SET) >> 4) |
+                  ((m68ki_cpu.n_flag & NFLAG_SET) >> 4) |
+                  ((!m68ki_cpu.not_z_flag) << 2)        |
+                  ((m68ki_cpu.v_flag & VFLAG_SET) >> 6) |
+                  ((m68ki_cpu.c_flag & CFLAG_SET) >> 8);
+    case M68K_REG_SP:  return m68ki_cpu.dar[15];
+    case M68K_REG_USP:  return m68ki_cpu.s_flag ? m68ki_cpu.sp[0] : m68ki_cpu.dar[15];
+    case M68K_REG_ISP:  return m68ki_cpu.s_flag ? m68ki_cpu.dar[15] : m68ki_cpu.sp[4];
+#if M68K_EMULATE_PREFETCH
+    case M68K_REG_PREF_ADDR:  return m68ki_cpu.pref_addr;
+    case M68K_REG_PREF_DATA:  return m68ki_cpu.pref_data;
+#endif
+    case M68K_REG_IR:  return m68ki_cpu.ir;
+    default:      return 0;
+  }
+}
+
+void m68k_set_reg(m68k_register_t regnum, unsigned int value)
+{
+  switch(regnum)
+  {
+    case M68K_REG_D0:  REG_D[0] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D1:  REG_D[1] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D2:  REG_D[2] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D3:  REG_D[3] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D4:  REG_D[4] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D5:  REG_D[5] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D6:  REG_D[6] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_D7:  REG_D[7] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A0:  REG_A[0] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A1:  REG_A[1] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A2:  REG_A[2] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A3:  REG_A[3] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A4:  REG_A[4] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A5:  REG_A[5] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A6:  REG_A[6] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_A7:  REG_A[7] = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_PC:  m68ki_jump(MASK_OUT_ABOVE_32(value)); return;
+    case M68K_REG_SR:  m68ki_set_sr(value); return;
+    case M68K_REG_SP:  REG_SP = MASK_OUT_ABOVE_32(value); return;
+    case M68K_REG_USP:  if(FLAG_S)
+                REG_USP = MASK_OUT_ABOVE_32(value);
+              else
+                REG_SP = MASK_OUT_ABOVE_32(value);
+              return;
+    case M68K_REG_ISP:  if(FLAG_S)
+                REG_SP = MASK_OUT_ABOVE_32(value);
+              else
+                REG_ISP = MASK_OUT_ABOVE_32(value);
+              return;
+    case M68K_REG_IR:  REG_IR = MASK_OUT_ABOVE_16(value); return;
+#if M68K_EMULATE_PREFETCH
+    case M68K_REG_PREF_ADDR:  CPU_PREF_ADDR = MASK_OUT_ABOVE_32(value); return;
+#endif
+    default:      return;
+  }
+}
+
+/* Set the callbacks */
+#if M68K_EMULATE_INT_ACK == OPT_ON
+void m68k_set_int_ack_callback(int  (*callback)(int int_level))
+{
+  CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback;
+}
+#endif
+
+#if M68K_EMULATE_RESET == OPT_ON
+void m68k_set_reset_instr_callback(void  (*callback)(void))
+{
+  CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback;
+}
+#endif
+
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+void m68k_set_tas_instr_callback(int  (*callback)(void))
+{
+  CALLBACK_TAS_INSTR = callback ? callback : default_tas_instr_callback;
+}
+#endif
+
+#if M68K_EMULATE_FC == OPT_ON
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc))
+{
+  CALLBACK_SET_FC = callback ? callback : default_set_fc_callback;
+}
+#endif
+
+#ifdef LOGERROR
+
+extern void error(char *format, ...);
+extern uint16 v_counter;
+#endif
+
+/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
+/* KS: Modified so that IPL* bits match with mask positions in the SR
+ *     and cleaned out remenants of the interrupt controller.
+ */
+void m68k_update_irq(unsigned int mask)
+{
+  /* Update IRQ level */
+  CPU_INT_LEVEL |= (mask << 8);
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+}
+
+void m68k_set_irq(unsigned int int_level)
+{
+  /* Set IRQ level */
+  CPU_INT_LEVEL = int_level << 8;
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+}
+
+/* IRQ latency (Fatal Rewind, Sesame's Street Counting Cafe)*/
+void m68k_set_irq_delay(unsigned int int_level)
+{
+  /* Prevent reentrance */
+  if (!irq_latency)
+  {
+    /* This is always triggered from MOVE instructions (VDP CTRL port write) */
+    /* We just make sure this is not a MOVE.L instruction as we could be in */
+    /* the middle of its execution (first memory write).                   */
+    if ((REG_IR & 0xF000) != 0x2000)
+    {
+      /* Finish executing current instruction */
+      USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+
+      /* One instruction delay before interrupt */
+      irq_latency = 1;
+      m68ki_trace_t1() /* auto-disable (see m68kcpu.h) */
+      m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+      REG_IR = m68ki_read_imm_16();
+      m68ki_instruction_jump_table[REG_IR]();
+      m68ki_exception_if_trace() /* auto-disable (see m68kcpu.h) */
+      irq_latency = 0;
+    }
+
+    /* Set IRQ level */
+    CPU_INT_LEVEL = int_level << 8;
+  }
+  
+#ifdef LOGERROR
+  error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
+#endif
+
+  /* Check interrupt mask to process IRQ  */
+  m68ki_check_interrupts(); /* Level triggered (IRQ) */
+}
+
+void __time_critical_func(m68k_run)(unsigned int cycles)
+{
+    //  printf("m68K_run current_cycles=%d add=%d STOP=%x\n",m68k.cycles,cycles,CPU_STOPPED);
+  /* Make sure CPU is not already ahead */
+  if (m68k.cycles >= cycles)
+  {
+    return;
+  }
+
+  /* Check interrupt mask to process IRQ if needed */
+  m68ki_check_interrupts();
+
+  /* Make sure we're not stopped */
+  if (CPU_STOPPED)
+  {
+    m68k.cycles = cycles;
+    return;
+  }
+
+  /* Save end cycles count for when CPU is stopped */
+  m68k.cycle_end = cycles;
+
+  /* Return point for when we have an address error (TODO: use goto) */
+  m68ki_set_address_error_trap() /* auto-disable (see m68kcpu.h) */
+
+#ifdef LOGERROR
+  error("[%d][%d] m68k run to %d cycles (%x), irq mask = %x (%x)\n", v_counter, m68k.cycles, cycles, m68k.pc,FLAG_INT_MASK, CPU_INT_LEVEL);
+#endif
+#pragma GCC unroll(4)
+  while (m68k.cycles < cycles)
+  {
+    /* Set tracing accodring to T1. */
+    m68ki_trace_t1() /* auto-disable (see m68kcpu.h) */
+
+    /* Set the address space for reads */
+    m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+    /* Trigger execution hook */
+    if (cpu_hook)
+      cpu_hook(HOOK_M68K_E, 0, REG_PC, 0);
+#endif
+
+    /* Decode next instruction */
+    REG_IR = m68ki_read_imm_16();
+
+//    printf("PC=%x IR=%x CYCLES=%d \n",m68k.pc,REG_IR,CYC_INSTRUCTION[REG_IR]);
+    /* Execute instruction */
+    m68ki_instruction_jump_table[REG_IR]();
+    USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+    /* Trace m68k_exception, if necessary */
+    m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */
+  }
+}
+
+int m68k_cycles(void)
+{
+  return CYC_INSTRUCTION[REG_IR];
+}
+
+int __always_inline m68k_cycles_run(void)
+{
+	return m68k.cycle_end - m68k.cycles;
+}
+
+int __always_inline m68k_cycles_master(void)
+{
+	return m68k.cycles;
+}
+
+void m68k_init(void)
+{
+#ifdef BUILD_TABLES
+  static uint emulation_initialized = 0;
+
+  /* The first call to this function initializes the opcode handler jump table */
+  if(!emulation_initialized)
+  {
+    m68ki_build_opcode_table();
+    emulation_initialized = 1;
+  }
+#endif
+
+#ifdef M68K_OVERCLOCK_SHIFT
+  m68k.cycle_ratio = 1 << M68K_OVERCLOCK_SHIFT;
+#endif
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+  m68k_set_int_ack_callback(NULL);
+#endif
+#if M68K_EMULATE_RESET == OPT_ON
+  m68k_set_reset_instr_callback(NULL);
+#endif
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+  m68k_set_tas_instr_callback(NULL);
+#endif
+#if M68K_EMULATE_FC == OPT_ON
+  m68k_set_fc_callback(NULL);
+#endif
+}
+
+/* Pulse the RESET line on the CPU */
+void m68k_pulse_reset(void)
+{
+  /* Clear all stop levels */
+  CPU_STOPPED = 0;
+#if M68K_EMULATE_ADDRESS_ERROR
+  CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+#endif
+
+  /* Turn off tracing */
+  FLAG_T1 = 0;
+  m68ki_clear_trace()
+
+  /* Interrupt mask to level 7 */
+  FLAG_INT_MASK = 0x0700;
+  CPU_INT_LEVEL = 0;
+  irq_latency = 0;
+
+  /* Go to supervisor mode */
+  m68ki_set_s_flag(SFLAG_SET);
+
+  /* Invalidate the prefetch queue */
+#if M68K_EMULATE_PREFETCH
+  /* Set to arbitrary number since our first fetch is from 0 */
+  CPU_PREF_ADDR = 0x1000;
+#endif /* M68K_EMULATE_PREFETCH */
+
+  /* Read the initial stack pointer and program counter */
+  m68ki_jump(0);
+  REG_SP = m68ki_read_imm_32();
+  REG_PC = m68ki_read_imm_32();
+  m68ki_jump(REG_PC);
+
+#if M68K_EMULATE_ADDRESS_ERROR
+  CPU_RUN_MODE = RUN_MODE_NORMAL;
+#endif
+
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_RESET]);
+}
+
+void m68k_pulse_halt(void)
+{
+  /* Pulse the HALT line on the CPU */
+  CPU_STOPPED |= STOP_LEVEL_HALT;
+}
+
+void m68k_clear_halt(void)
+{
+  /* Clear the HALT line on the CPU */
+  CPU_STOPPED &= ~STOP_LEVEL_HALT;
+}
+
+void gwenesis_m68k_save_state() {
+  SaveState *state;
+  state = saveGwenesisStateOpenForWrite("m68k");
+  
+  saveGwenesisStateSetBuffer(state, "REG_D", REG_D, sizeof(REG_D));
+  saveGwenesisStateSet(state, "SR", m68ki_get_sr());
+  saveGwenesisStateSet(state, "REG_PC", REG_PC);
+  saveGwenesisStateSet(state, "REG_SP", REG_SP);
+  saveGwenesisStateSet(state, "REG_USP", REG_USP);
+  saveGwenesisStateSet(state, "REG_ISP", REG_ISP);
+  saveGwenesisStateSet(state, "REG_IR", REG_IR);
+
+  saveGwenesisStateSet(state, "m68k_cycle_end", m68k.cycle_end);
+  saveGwenesisStateSet(state, "m68k_cycles", m68k.cycles);
+  saveGwenesisStateSet(state, "m68k_int_level", m68k.int_level);
+  saveGwenesisStateSet(state, "m68k_stopped", m68k.stopped);
+}
+
+void gwenesis_m68k_load_state() {
+  SaveState *state = saveGwenesisStateOpenForRead("m68k");
+  saveGwenesisStateGetBuffer(state, "REG_D", REG_D, sizeof(REG_D));
+
+  m68ki_set_sr(saveGwenesisStateGet(state, "SR"));
+  REG_PC = saveGwenesisStateGet(state, "REG_PC");
+  REG_SP = saveGwenesisStateGet(state, "REG_SP");
+  REG_USP = saveGwenesisStateGet(state, "REG_USP");
+  REG_ISP = saveGwenesisStateGet(state, "REG_ISP");
+  REG_IR = saveGwenesisStateGet(state, "REG_IR");
+
+  m68k.cycle_end = saveGwenesisStateGet(state, "m68k_cycle_end");
+  m68k.cycles = saveGwenesisStateGet(state, "m68k_cycles");
+  m68k.int_level = saveGwenesisStateGet(state, "m68k_int_level");
+  m68k.stopped = saveGwenesisStateGet(state, "m68k_stopped");
+
+}
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.h
new file mode 100755
index 0000000..e42b435
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kcpu.h
@@ -0,0 +1,1505 @@
+#ifndef M68KCPU__HEADER
+#define M68KCPU__HEADER
+
+/* ======================================================================== */
+/*                         GENERIC 68K CORE                                 */
+/* ======================================================================== */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <limits.h>
+
+#if M68K_EMULATE_ADDRESS_ERROR
+#include <setjmp.h>
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+#include "m68k.h"
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/* ======================================================================== */
+
+/* Exception Vectors handled by emulation */
+#define EXCEPTION_RESET                    0
+#define EXCEPTION_BUS_ERROR                2 /* This one is not emulated! */
+#define EXCEPTION_ADDRESS_ERROR            3 /* This one is partially emulated (doesn't stack a proper frame yet) */
+#define EXCEPTION_ILLEGAL_INSTRUCTION      4
+#define EXCEPTION_ZERO_DIVIDE              5
+#define EXCEPTION_CHK                      6
+#define EXCEPTION_TRAPV                    7
+#define EXCEPTION_PRIVILEGE_VIOLATION      8
+#define EXCEPTION_TRACE                    9
+#define EXCEPTION_1010                    10
+#define EXCEPTION_1111                    11
+#define EXCEPTION_FORMAT_ERROR            14
+#define EXCEPTION_UNINITIALIZED_INTERRUPT 15
+#define EXCEPTION_SPURIOUS_INTERRUPT      24
+#define EXCEPTION_INTERRUPT_AUTOVECTOR    24
+#define EXCEPTION_TRAP_BASE               32
+
+/* Function codes set by CPU during data/address bus activity */
+#define FUNCTION_CODE_USER_DATA          1
+#define FUNCTION_CODE_USER_PROGRAM       2
+#define FUNCTION_CODE_SUPERVISOR_DATA    5
+#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6
+#define FUNCTION_CODE_CPU_SPACE          7
+
+/* Different ways to stop the CPU */
+#define STOP_LEVEL_STOP 1
+#define STOP_LEVEL_HALT 2
+
+/* Used for 68000 address error processing */
+#if M68K_EMULATE_ADDRESS_ERROR
+#define INSTRUCTION_YES 0
+#define INSTRUCTION_NO  0x08
+#define MODE_READ       0x10
+#define MODE_WRITE      0
+
+#define RUN_MODE_NORMAL          0
+#define RUN_MODE_BERR_AERR_RESET 1
+#endif
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/* ======================================================================== */
+/* ================================ MACROS ================================ */
+/* ======================================================================== */
+
+
+/* ---------------------------- General Macros ---------------------------- */
+
+/* Bit Isolation Macros */
+#define BIT_0(A)  ((A) & 0x00000001)
+#define BIT_1(A)  ((A) & 0x00000002)
+#define BIT_2(A)  ((A) & 0x00000004)
+#define BIT_3(A)  ((A) & 0x00000008)
+#define BIT_4(A)  ((A) & 0x00000010)
+#define BIT_5(A)  ((A) & 0x00000020)
+#define BIT_6(A)  ((A) & 0x00000040)
+#define BIT_7(A)  ((A) & 0x00000080)
+#define BIT_8(A)  ((A) & 0x00000100)
+#define BIT_9(A)  ((A) & 0x00000200)
+#define BIT_A(A)  ((A) & 0x00000400)
+#define BIT_B(A)  ((A) & 0x00000800)
+#define BIT_C(A)  ((A) & 0x00001000)
+#define BIT_D(A)  ((A) & 0x00002000)
+#define BIT_E(A)  ((A) & 0x00004000)
+#define BIT_F(A)  ((A) & 0x00008000)
+#define BIT_10(A) ((A) & 0x00010000)
+#define BIT_11(A) ((A) & 0x00020000)
+#define BIT_12(A) ((A) & 0x00040000)
+#define BIT_13(A) ((A) & 0x00080000)
+#define BIT_14(A) ((A) & 0x00100000)
+#define BIT_15(A) ((A) & 0x00200000)
+#define BIT_16(A) ((A) & 0x00400000)
+#define BIT_17(A) ((A) & 0x00800000)
+#define BIT_18(A) ((A) & 0x01000000)
+#define BIT_19(A) ((A) & 0x02000000)
+#define BIT_1A(A) ((A) & 0x04000000)
+#define BIT_1B(A) ((A) & 0x08000000)
+#define BIT_1C(A) ((A) & 0x10000000)
+#define BIT_1D(A) ((A) & 0x20000000)
+#define BIT_1E(A) ((A) & 0x40000000)
+#define BIT_1F(A) ((A) & 0x80000000)
+
+/* Get the most significant bit for specific sizes */
+#define GET_MSB_8(A)  ((A) & 0x80)
+#define GET_MSB_9(A)  ((A) & 0x100)
+#define GET_MSB_16(A) ((A) & 0x8000)
+#define GET_MSB_17(A) ((A) & 0x10000)
+#define GET_MSB_32(A) ((A) & 0x80000000)
+#if M68K_USE_64_BIT
+#define GET_MSB_33(A) ((A) & 0x100000000)
+#endif /* M68K_USE_64_BIT */
+
+/* Isolate nibbles */
+#define LOW_NIBBLE(A)  ((A) & 0x0f)
+#define HIGH_NIBBLE(A) ((A) & 0xf0)
+
+/* These are used to isolate 8, 16, and 32 bit sizes */
+#define MASK_OUT_ABOVE_2(A)  ((A) & 3)
+#define MASK_OUT_ABOVE_8(A)  ((A) & 0xff)
+#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff)
+#define MASK_OUT_BELOW_2(A)  ((A) & ~3)
+#define MASK_OUT_BELOW_8(A)  ((A) & ~0xff)
+#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff)
+
+/* No need to mask if we are 32 bit */
+#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT
+  #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff)
+  #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff)
+#else
+  #define MASK_OUT_ABOVE_32(A) (A)
+  #define MASK_OUT_BELOW_32(A) 0
+#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */
+
+/* Simulate address lines of 68k family */
+#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)
+
+
+/* Shift & Rotate Macros. */
+#define LSL(A, C) ((A) << (C))
+#define LSR(A, C) ((A) >> (C))
+
+/* Some > 32-bit optimizations */
+#if M68K_INT_GT_32_BIT
+  /* Shift left and right */
+  #define LSR_32(A, C) ((A) >> (C))
+  #define LSL_32(A, C) ((A) << (C))
+#else
+  /* We have to do this because the morons at ANSI decided that shifts
+     * by >= data size are undefined.
+     */
+  #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0)
+  #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0)
+#endif /* M68K_INT_GT_32_BIT */
+
+#if M68K_USE_64_BIT
+  #define LSL_32_64(A, C) ((A) << (C))
+  #define LSR_32_64(A, C) ((A) >> (C))
+  #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C)))
+  #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C)))
+#endif /* M68K_USE_64_BIT */
+
+#define ROL_8(A, C)      MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C)))
+#define ROL_9(A, C)                      (LSL(A, C) | LSR(A, 9-(C)))
+#define ROL_16(A, C)    MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C)))
+#define ROL_17(A, C)                     (LSL(A, C) | LSR(A, 17-(C)))
+#define ROL_32(A, C)    MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C)))
+#define ROL_33(A, C)                     (LSL_32(A, C) | LSR_32(A, 33-(C)))
+
+#define ROR_8(A, C)      MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C)))
+#define ROR_9(A, C)                      (LSR(A, C) | LSL(A, 9-(C)))
+#define ROR_16(A, C)    MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C)))
+#define ROR_17(A, C)                     (LSR(A, C) | LSL(A, 17-(C)))
+#define ROR_32(A, C)    MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C)))
+#define ROR_33(A, C)                     (LSR_32(A, C) | LSL_32(A, 33-(C)))
+
+
+
+/* ------------------------------ CPU Access ------------------------------ */
+
+/* Access the CPU registers */
+#define REG_DA           m68ki_cpu.dar /* easy access to data and address regs */
+#define REG_D            m68ki_cpu.dar
+#define REG_A            (m68ki_cpu.dar+8)
+#define REG_PC           m68ki_cpu.pc
+#define REG_SP_BASE      m68ki_cpu.sp
+#define REG_USP          m68ki_cpu.sp[0]
+#define REG_ISP          m68ki_cpu.sp[4]
+#define REG_SP           m68ki_cpu.dar[15]
+#define REG_IR           m68ki_cpu.ir
+
+#define FLAG_T1          m68ki_cpu.t1_flag
+#define FLAG_S           m68ki_cpu.s_flag
+#define FLAG_X           m68ki_cpu.x_flag
+#define FLAG_N           m68ki_cpu.n_flag
+#define FLAG_Z           m68ki_cpu.not_z_flag
+#define FLAG_V           m68ki_cpu.v_flag
+#define FLAG_C           m68ki_cpu.c_flag
+#define FLAG_INT_MASK    m68ki_cpu.int_mask
+
+#define CPU_INT_LEVEL    m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
+#define CPU_STOPPED      m68ki_cpu.stopped
+#if M68K_EMULATE_PREFETCH
+#define CPU_PREF_ADDR    m68ki_cpu.pref_addr
+#define CPU_PREF_DATA    m68ki_cpu.pref_data
+#endif
+#define CPU_ADDRESS_MASK  0x00ffffff
+#if M68K_EMULATE_ADDRESS_ERROR
+#define CPU_INSTR_MODE   m68ki_cpu.instr_mode
+#define CPU_RUN_MODE     m68ki_cpu.run_mode
+#endif
+
+#define CYC_INSTRUCTION   m68ki_cycles
+#define CYC_EXCEPTION     m68ki_exception_cycle_table
+#define CYC_BCC_NOTAKE_B  ( -2 * MUL)
+#define CYC_BCC_NOTAKE_W  (  2 * MUL)
+#define CYC_DBCC_F_NOEXP  ( -2 * MUL)
+#define CYC_DBCC_F_EXP    (  2 * MUL)
+#define CYC_SCC_R_TRUE    (  2 * MUL)
+#define CYC_MOVEM_W       (  4 * MUL)
+#define CYC_MOVEM_L       (  8 * MUL)
+#define CYC_SHIFT         (  2 * MUL)
+#define CYC_RESET         (132 * MUL)
+
+#if M68K_EMULATE_INT_ACK == OPT_ON
+#define CALLBACK_INT_ACK      m68ki_cpu.int_ack_callback
+#endif
+#if M68K_EMULATE_RESET == OPT_ON
+#define CALLBACK_RESET_INSTR  m68ki_cpu.reset_instr_callback
+#endif
+#if M68K_TAS_HAS_CALLBACK == OPT_ON
+#define CALLBACK_TAS_INSTR    m68ki_cpu.tas_instr_callback
+#endif
+#if M68K_EMULATE_FC == OPT_ON
+#define CALLBACK_SET_FC       m68ki_cpu.set_fc_callback
+#endif
+
+
+/* ----------------------------- Configuration ---------------------------- */
+
+/* These defines are dependant on the configuration defines in m68kconf.h */
+
+/* Enable or disable callback functions */
+#if M68K_EMULATE_INT_ACK
+  #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER
+    #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A);
+  #else
+    #define m68ki_int_ack(A) CALLBACK_INT_ACK(A);
+  #endif
+#else
+  /* Default action is to used autovector mode, which is most common */
+  #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR
+#endif /* M68K_EMULATE_INT_ACK */
+
+#if M68K_EMULATE_RESET
+  #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER
+    #define m68ki_output_reset() M68K_RESET_CALLBACK();
+  #else
+    #define m68ki_output_reset() CALLBACK_RESET_INSTR();
+  #endif
+#else
+  #define m68ki_output_reset()
+#endif /* M68K_EMULATE_RESET */
+
+#if M68K_TAS_HAS_CALLBACK
+  #if M68K_TAS_HAS_CALLBACK == OPT_SPECIFY_HANDLER
+    #define m68ki_tas_callback() M68K_TAS_CALLBACK()
+  #else
+    #define m68ki_tas_callback() CALLBACK_TAS_INSTR()
+  #endif
+#else
+  #define m68ki_tas_callback() 0
+#endif /* M68K_TAS_HAS_CALLBACK */
+
+
+/* Enable or disable function code emulation */
+#if M68K_EMULATE_FC
+  #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER
+    #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A);
+  #else
+    #define m68ki_set_fc(A) CALLBACK_SET_FC(A);
+  #endif
+  #define m68ki_use_data_space() m68ki_cpu.address_space = FUNCTION_CODE_USER_DATA;
+  #define m68ki_use_program_space() m68ki_cpu.address_space = FUNCTION_CODE_USER_PROGRAM;
+  #define m68ki_get_address_space() m68ki_cpu.address_space
+#else
+  #define m68ki_set_fc(A)
+  #define m68ki_use_data_space()
+  #define m68ki_use_program_space()
+  #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA
+#endif /* M68K_EMULATE_FC */
+
+
+/* Enable or disable trace emulation */
+#if M68K_EMULATE_TRACE
+  /* Initiates trace checking before each instruction (t1) */
+  #define m68ki_trace_t1() m68ki_cpu.tracing = FLAG_T1;
+  /* Clear all tracing */
+  #define m68ki_clear_trace() m68ki_cpu.tracing = 0;
+  /* Cause a trace exception if we are tracing */
+  #define m68ki_exception_if_trace() if(m68ki_cpu.tracing) m68ki_exception_trace();
+#else
+  #define m68ki_trace_t1()
+  #define m68ki_clear_trace()
+  #define m68ki_exception_if_trace()
+#endif /* M68K_EMULATE_TRACE */
+
+
+/* Enable or disable Address error emulation */
+#if M68K_EMULATE_ADDRESS_ERROR
+  #define m68ki_set_address_error_trap() \
+    if(setjmp(m68ki_cpu.aerr_trap) != 0) \
+    { \
+      m68ki_exception_address_error(); \
+    }
+
+  #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+    if((ADDR)&1) \
+    { \
+      if (m68ki_cpu.aerr_enabled) \
+      { \
+        m68ki_cpu.aerr_address = ADDR; \
+        m68ki_cpu.aerr_write_mode = WRITE_MODE; \
+        m68ki_cpu.aerr_fc = FC; \
+        longjmp(m68ki_cpu.aerr_trap, 1); \
+      } \
+    }
+#else
+  #define m68ki_set_address_error_trap()
+  #define m68ki_check_address_error(ADDR, WRITE_MODE, FC)
+#endif /* M68K_ADDRESS_ERROR */
+
+
+/* -------------------------- EA / Operand Access ------------------------- */
+
+/*
+ * The general instruction format follows this pattern:
+ * .... XXX. .... .YYY
+ * where XXX is register X and YYY is register Y
+ */
+
+/* Data Register Isolation */
+#define DX (REG_D[(REG_IR >> 9) & 7])
+#define DY (REG_D[REG_IR & 7])
+
+/* Address Register Isolation */
+#define AX (REG_A[(REG_IR >> 9) & 7])
+#define AY (REG_A[REG_IR & 7])
+
+/* Effective Address Calculations */
+#define EA_AY_AI_8()   AY                                    /* address register indirect */
+#define EA_AY_AI_16()  EA_AY_AI_8()
+#define EA_AY_AI_32()  EA_AY_AI_8()
+#define EA_AY_PI_8()   (AY++)                                /* postincrement (size = byte) */
+#define EA_AY_PI_16()  ((AY+=2)-2)                           /* postincrement (size = word) */
+#define EA_AY_PI_32()  ((AY+=4)-4)                           /* postincrement (size = long) */
+#define EA_AY_PD_8()   (--AY)                                /* predecrement (size = byte) */
+#define EA_AY_PD_16()  (AY-=2)                               /* predecrement (size = word) */
+#define EA_AY_PD_32()  (AY-=4)                               /* predecrement (size = long) */
+#define EA_AY_DI_8()   (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_16()  EA_AY_DI_8()
+#define EA_AY_DI_32()  EA_AY_DI_8()
+#define EA_AY_IX_8()   m68ki_get_ea_ix(AY)                   /* indirect + index */
+#define EA_AY_IX_16()  EA_AY_IX_8()
+#define EA_AY_IX_32()  EA_AY_IX_8()
+
+#define EA_AX_AI_8()   AX
+#define EA_AX_AI_16()  EA_AX_AI_8()
+#define EA_AX_AI_32()  EA_AX_AI_8()
+#define EA_AX_PI_8()   (AX++)
+#define EA_AX_PI_16()  ((AX+=2)-2)
+#define EA_AX_PI_32()  ((AX+=4)-4)
+#define EA_AX_PD_8()   (--AX)
+#define EA_AX_PD_16()  (AX-=2)
+#define EA_AX_PD_32()  (AX-=4)
+#define EA_AX_DI_8()   (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_16()  EA_AX_DI_8()
+#define EA_AX_DI_32()  EA_AX_DI_8()
+#define EA_AX_IX_8()   m68ki_get_ea_ix(AX)
+#define EA_AX_IX_16()  EA_AX_IX_8()
+#define EA_AX_IX_32()  EA_AX_IX_8()
+
+#define EA_A7_PI_8()   ((REG_A[7]+=2)-2)
+#define EA_A7_PD_8()   (REG_A[7]-=2)
+
+#define EA_AW_8()      MAKE_INT_16(m68ki_read_imm_16())      /* absolute word */
+#define EA_AW_16()     EA_AW_8()
+#define EA_AW_32()     EA_AW_8()
+#define EA_AL_8()      m68ki_read_imm_32()                   /* absolute long */
+#define EA_AL_16()     EA_AL_8()
+#define EA_AL_32()     EA_AL_8()
+#define EA_PCDI_8()    m68ki_get_ea_pcdi()                   /* pc indirect + displacement */
+#define EA_PCDI_16()   EA_PCDI_8()
+#define EA_PCDI_32()   EA_PCDI_8()
+#define EA_PCIX_8()    m68ki_get_ea_pcix()                   /* pc indirect + index */
+#define EA_PCIX_16()   EA_PCIX_8()
+#define EA_PCIX_32()   EA_PCIX_8()
+
+
+#define OPER_I_8()     m68ki_read_imm_8()
+#define OPER_I_16()    m68ki_read_imm_16()
+#define OPER_I_32()    m68ki_read_imm_32()
+
+
+/* --------------------------- Status Register ---------------------------- */
+
+/* Flag Calculation Macros */
+#define CFLAG_8(A) (A)
+#define CFLAG_16(A) ((A)>>8)
+
+#if M68K_INT_GT_32_BIT
+  #define CFLAG_ADD_32(S, D, R) ((R)>>24)
+  #define CFLAG_SUB_32(S, D, R) ((R)>>24)
+#else
+  #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23)
+  #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23)
+#endif /* M68K_INT_GT_32_BIT */
+
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
+#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24)
+
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
+#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24)
+
+#define NFLAG_8(A) (A)
+#define NFLAG_16(A) ((A)>>8)
+#define NFLAG_32(A) ((A)>>24)
+#define NFLAG_64(A) ((A)>>56)
+
+#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A)
+#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A)
+#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A)
+
+
+/* Flag values */
+#define NFLAG_SET   0x80
+#define NFLAG_CLEAR 0
+#define CFLAG_SET   0x100
+#define CFLAG_CLEAR 0
+#define XFLAG_SET   0x100
+#define XFLAG_CLEAR 0
+#define VFLAG_SET   0x80
+#define VFLAG_CLEAR 0
+#define ZFLAG_SET   0
+#define ZFLAG_CLEAR 0xffffffff
+#define SFLAG_SET   4
+#define SFLAG_CLEAR 0
+
+/* Turn flag values into 1 or 0 */
+#define XFLAG_AS_1() ((FLAG_X>>8)&1)
+#define NFLAG_AS_1() ((FLAG_N>>7)&1)
+#define VFLAG_AS_1() ((FLAG_V>>7)&1)
+#define ZFLAG_AS_1() (!FLAG_Z)
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)
+
+
+/* Conditions */
+#define COND_CS() (FLAG_C&0x100)
+#define COND_CC() (!COND_CS())
+#define COND_VS() (FLAG_V&0x80)
+#define COND_VC() (!COND_VS())
+#define COND_NE() FLAG_Z
+#define COND_EQ() (!COND_NE())
+#define COND_MI() (FLAG_N&0x80)
+#define COND_PL() (!COND_MI())
+#define COND_LT() ((FLAG_N^FLAG_V)&0x80)
+#define COND_GE() (!COND_LT())
+#define COND_HI() (COND_CC() && COND_NE())
+#define COND_LS() (COND_CS() || COND_EQ())
+#define COND_GT() (COND_GE() && COND_NE())
+#define COND_LE() (COND_LT() || COND_EQ())
+
+/* Reversed conditions */
+#define COND_NOT_CS() COND_CC()
+#define COND_NOT_CC() COND_CS()
+#define COND_NOT_VS() COND_VC()
+#define COND_NOT_VC() COND_VS()
+#define COND_NOT_NE() COND_EQ()
+#define COND_NOT_EQ() COND_NE()
+#define COND_NOT_MI() COND_PL()
+#define COND_NOT_PL() COND_MI()
+#define COND_NOT_LT() COND_GE()
+#define COND_NOT_GE() COND_LT()
+#define COND_NOT_HI() COND_LS()
+#define COND_NOT_LS() COND_HI()
+#define COND_NOT_GT() COND_LE()
+#define COND_NOT_LE() COND_GT()
+
+/* Not real conditions, but here for convenience */
+#define COND_XS() (FLAG_X&0x100)
+#define COND_XC() (!COND_XS)
+
+
+/* Get the condition code register */
+#define m68ki_get_ccr() ((COND_XS() >> 4) | \
+             (COND_MI() >> 4) | \
+             (COND_EQ() << 2) | \
+             (COND_VS() >> 6) | \
+             (COND_CS() >> 8))
+
+/* Get the status register */
+#define m68ki_get_sr() ( FLAG_T1  | \
+            (FLAG_S        << 11) | \
+             FLAG_INT_MASK        | \
+             m68ki_get_ccr())
+
+
+
+/* ---------------------------- Cycle Counting ---------------------------- */
+
+#ifdef M68K_OVERCLOCK_SHIFT
+#define USE_CYCLES(A) m68ki_cpu.cycles += ((A) * m68ki_cpu.cycle_ratio) >> M68K_OVERCLOCK_SHIFT
+#else
+#define USE_CYCLES(A) m68ki_cpu.cycles += (A)
+#endif
+#define SET_CYCLES(A) m68ki_cpu.cycles  = (A)
+
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+void gwenesis_m68k_save_state();
+void gwenesis_m68k_load_state();
+
+/* ----------------------------- Read / Write ----------------------------- */
+
+/*** BZHXX ***/
+/* Read data immediately following the PC */
+//#define m68k_read_immediate_16(address) *(uint16 *)(m68ki_cpu.memory_map[((address)>>16)&0xff].base + ((address) & 0xffff))
+//#define m68k_read_immediate_32(address) (m68k_read_immediate_16(address) << 16) | (m68k_read_immediate_16(address+2))
+
+/* Read data relative to the PC */
+//#define m68k_read_pcrelative_8(address)  READ_BYTE(m68ki_cpu.memory_map[((address)>>16)&0xff].base, (address) & 0xffff)
+//#define m68k_read_pcrelative_16(address) m68k_read_immediate_16(address)
+//#define m68k_read_pcrelative_32(address) m68k_read_immediate_32(address)
+
+/* map read immediate 8 to read immediate 16 */
+#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16())
+
+/* Map PC-relative reads */
+#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)
+#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)
+#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)
+
+
+/* ======================================================================== */
+/* =============================== PROTOTYPES ============================= */
+/* ======================================================================== */
+
+/* Used by shift & rotate instructions */
+static const uint8 m68ki_shift_8_table[65] =
+{
+  0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff
+};
+
+static const uint16 m68ki_shift_16_table[65] =
+{
+  0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00,
+  0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+  0xffff, 0xffff
+};
+
+static const uint m68ki_shift_32_table[65] =
+{
+  0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000,
+  0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000,
+  0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000,
+  0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00,
+  0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8,
+  0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+
+/* Number of clock cycles to use for exception processing.
+ * I used 4 for any vectors that are undocumented for processing times.
+ */
+static const uint16 m68ki_exception_cycle_table[256] =
+{
+     40*MUL, /*  0: Reset - Initial Stack Pointer                      */
+      4*MUL, /*  1: Reset - Initial Program Counter                    */
+     50*MUL, /*  2: Bus Error                             (unemulated) */
+     50*MUL, /*  3: Address Error                         (unemulated) */
+     34*MUL, /*  4: Illegal Instruction                                */
+     38*MUL, /*  5: Divide by Zero -- ASG: changed from 42             */
+     40*MUL, /*  6: CHK -- ASG: chanaged from 44                       */
+     34*MUL, /*  7: TRAPV                                              */
+     34*MUL, /*  8: Privilege Violation                                */
+     34*MUL, /*  9: Trace                                              */
+      4*MUL, /* 10: 1010                                               */
+      4*MUL, /* 11: 1111                                               */
+      4*MUL, /* 12: RESERVED                                           */
+      4*MUL, /* 13: Coprocessor Protocol Violation        (unemulated) */
+      4*MUL, /* 14: Format Error                                       */
+     44*MUL, /* 15: Uninitialized Interrupt                            */
+      4*MUL, /* 16: RESERVED                                           */
+      4*MUL, /* 17: RESERVED                                           */
+      4*MUL, /* 18: RESERVED                                           */
+      4*MUL, /* 19: RESERVED                                           */
+      4*MUL, /* 20: RESERVED                                           */
+      4*MUL, /* 21: RESERVED                                           */
+      4*MUL, /* 22: RESERVED                                           */
+      4*MUL, /* 23: RESERVED                                           */
+     44*MUL, /* 24: Spurious Interrupt                                 */
+     54*MUL, /* 25: Level 1 Interrupt Autovector                       */
+     54*MUL, /* 26: Level 2 Interrupt Autovector                       */
+     54*MUL, /* 27: Level 3 Interrupt Autovector                       */
+     54*MUL, /* 28: Level 4 Interrupt Autovector                       */
+     54*MUL, /* 29: Level 5 Interrupt Autovector                       */
+     54*MUL, /* 30: Level 6 Interrupt Autovector                       */
+     54*MUL, /* 31: Level 7 Interrupt Autovector                       */
+     34*MUL, /* 32: TRAP #0 -- ASG: chanaged from 38                   */
+     34*MUL, /* 33: TRAP #1                                            */
+     34*MUL, /* 34: TRAP #2                                            */
+     34*MUL, /* 35: TRAP #3                                            */
+     34*MUL, /* 36: TRAP #4                                            */
+     34*MUL, /* 37: TRAP #5                                            */
+     34*MUL, /* 38: TRAP #6                                            */
+     34*MUL, /* 39: TRAP #7                                            */
+     34*MUL, /* 40: TRAP #8                                            */
+     34*MUL, /* 41: TRAP #9                                            */
+     34*MUL, /* 42: TRAP #10                                           */
+     34*MUL, /* 43: TRAP #11                                           */
+     34*MUL, /* 44: TRAP #12                                           */
+     34*MUL, /* 45: TRAP #13                                           */
+     34*MUL, /* 46: TRAP #14                                           */
+     34*MUL, /* 47: TRAP #15                                           */
+      4*MUL, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+      4*MUL, /* 49: FP Inexact Result                     (unemulated) */
+      4*MUL, /* 50: FP Divide by Zero                     (unemulated) */
+      4*MUL, /* 51: FP Underflow                          (unemulated) */
+      4*MUL, /* 52: FP Operand Error                      (unemulated) */
+      4*MUL, /* 53: FP Overflow                           (unemulated) */
+      4*MUL, /* 54: FP Signaling NAN                      (unemulated) */
+      4*MUL, /* 55: FP Unimplemented Data Type            (unemulated) */
+      4*MUL, /* 56: MMU Configuration Error               (unemulated) */
+      4*MUL, /* 57: MMU Illegal Operation Error           (unemulated) */
+      4*MUL, /* 58: MMU Access Level Violation Error      (unemulated) */
+      4*MUL, /* 59: RESERVED                                           */
+      4*MUL, /* 60: RESERVED                                           */
+      4*MUL, /* 61: RESERVED                                           */
+      4*MUL, /* 62: RESERVED                                           */
+      4*MUL, /* 63: RESERVED                                           */
+         /* 64-255: User Defined                                   */
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,
+      4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL,4*MUL
+};
+
+/* Read data immediately after the program counter */
+INLINE uint m68ki_read_imm_16(void);
+INLINE uint m68ki_read_imm_32(void);
+
+/* Read from the current address space */
+INLINE uint m68ki_read_8(uint address);
+INLINE uint m68ki_read_16(uint address);
+INLINE uint m68ki_read_32(uint address);
+
+/* Write to the current data space */
+INLINE void m68ki_write_8(uint address, uint value);
+INLINE void m68ki_write_16(uint address, uint value);
+INLINE void m68ki_write_32(uint address, uint value);
+
+/* Indexed and PC-relative ea fetching */
+INLINE uint m68ki_get_ea_pcdi(void);
+INLINE uint m68ki_get_ea_pcix(void);
+INLINE uint m68ki_get_ea_ix(uint An);
+
+/* Operand fetching */
+INLINE uint OPER_AY_AI_8(void);
+INLINE uint OPER_AY_AI_16(void);
+INLINE uint OPER_AY_AI_32(void);
+INLINE uint OPER_AY_PI_8(void);
+INLINE uint OPER_AY_PI_16(void);
+INLINE uint OPER_AY_PI_32(void);
+INLINE uint OPER_AY_PD_8(void);
+INLINE uint OPER_AY_PD_16(void);
+INLINE uint OPER_AY_PD_32(void);
+INLINE uint OPER_AY_DI_8(void);
+INLINE uint OPER_AY_DI_16(void);
+INLINE uint OPER_AY_DI_32(void);
+INLINE uint OPER_AY_IX_8(void);
+INLINE uint OPER_AY_IX_16(void);
+INLINE uint OPER_AY_IX_32(void);
+
+INLINE uint OPER_AX_AI_8(void);
+INLINE uint OPER_AX_AI_16(void);
+INLINE uint OPER_AX_AI_32(void);
+INLINE uint OPER_AX_PI_8(void);
+INLINE uint OPER_AX_PI_16(void);
+INLINE uint OPER_AX_PI_32(void);
+INLINE uint OPER_AX_PD_8(void);
+INLINE uint OPER_AX_PD_16(void);
+INLINE uint OPER_AX_PD_32(void);
+INLINE uint OPER_AX_DI_8(void);
+INLINE uint OPER_AX_DI_16(void);
+INLINE uint OPER_AX_DI_32(void);
+INLINE uint OPER_AX_IX_8(void);
+INLINE uint OPER_AX_IX_16(void);
+INLINE uint OPER_AX_IX_32(void);
+
+INLINE uint OPER_A7_PI_8(void);
+INLINE uint OPER_A7_PD_8(void);
+
+INLINE uint OPER_AW_8(void);
+INLINE uint OPER_AW_16(void);
+INLINE uint OPER_AW_32(void);
+INLINE uint OPER_AL_8(void);
+INLINE uint OPER_AL_16(void);
+INLINE uint OPER_AL_32(void);
+INLINE uint OPER_PCDI_8(void);
+INLINE uint OPER_PCDI_16(void);
+INLINE uint OPER_PCDI_32(void);
+INLINE uint OPER_PCIX_8(void);
+INLINE uint OPER_PCIX_16(void);
+INLINE uint OPER_PCIX_32(void);
+
+/* Stack operations */
+INLINE void m68ki_push_16(uint value);
+INLINE void m68ki_push_32(uint value);
+INLINE uint m68ki_pull_16(void);
+INLINE uint m68ki_pull_32(void);
+
+/* Program flow operations */
+INLINE void m68ki_jump(uint new_pc);
+INLINE void m68ki_jump_vector(uint vector);
+INLINE void m68ki_branch_8(uint offset);
+INLINE void m68ki_branch_16(uint offset);
+INLINE void m68ki_branch_32(uint offset);
+
+/* Status register operations. */
+INLINE void m68ki_set_s_flag(uint value);            /* Only bit 2 of value should be set (i.e. 4 or 0) */
+INLINE void m68ki_set_ccr(uint value);               /* set the condition code register */
+INLINE void m68ki_set_sr(uint value);                /* set the status register */
+
+/* Exception processing */
+INLINE uint m68ki_init_exception(void);              /* Initial exception processing */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */
+#if M68K_EMULATE_ADDRESS_ERROR
+INLINE void m68ki_stack_frame_buserr(uint sr);
+#endif
+INLINE void m68ki_exception_trap(uint vector);
+INLINE void m68ki_exception_trapN(uint vector);
+#if M68K_EMULATE_TRACE
+INLINE void m68ki_exception_trace(void);
+#endif
+static void m68ki_exception_privilege_violation(void); /* do not inline in order to reduce function size and allow inlining of read/write functions by the compile */
+INLINE void m68ki_exception_1010(void);
+INLINE void m68ki_exception_1111(void);
+INLINE void m68ki_exception_illegal(void);
+#if M68K_EMULATE_ADDRESS_ERROR
+INLINE void m68ki_exception_address_error(void);
+#endif
+INLINE void m68ki_exception_interrupt(uint int_level);
+INLINE void m68ki_check_interrupts(void);            /* ASG: check for interrupts */
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+
+/* ---------------------------- Read Immediate ---------------------------- */
+
+/* Handles all immediate reads, does address error check, function code setting,
+ * and prefetching if they are enabled in m68kconf.h
+ */
+INLINE uint m68ki_read_imm_16(void)
+{
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+#if M68K_EMULATE_PREFETCH
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+  }
+  REG_PC += 2;
+  return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3));
+#else
+  uint pc = REG_PC;
+  REG_PC += 2;
+  return m68k_read_immediate_16(pc);
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+INLINE uint m68ki_read_imm_32(void)
+{
+#if M68K_EMULATE_PREFETCH
+  uint temp_val;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+  }
+  temp_val = CPU_PREF_DATA;
+  REG_PC += 2;
+  if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+  {
+    CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+    CPU_PREF_DATA = m68k_read_immediate_32(CPU_PREF_ADDR);
+    temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16));
+  }
+  REG_PC += 2;
+
+  return temp_val;
+#else
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#if M68K_CHECK_PC_ADDRESS_ERROR
+  m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */
+#endif
+  uint pc = REG_PC;
+  REG_PC += 4;
+  return m68k_read_immediate_32(pc);
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+
+
+/* ------------------------- Top level read/write ------------------------- */
+
+/* Handles all memory accesses (except for immediate reads if they are
+ * configured to use separate functions in m68kconf.h).
+ * All memory accesses must go through these top level functions.
+ * These functions will also check for address error and set the function
+ * code if they are enabled in m68kconf.h.
+ */
+ /*** BZHXX ***/
+
+INLINE uint m68ki_read_8(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+	if (ADDRESS_68K(address) <  0x800000) return FETCH8ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH8RAM(ADDRESS_68K(address));
+	return m68k_read_memory_8(ADDRESS_68K(address));
+
+}
+
+INLINE uint m68ki_read_16(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+ 
+ 	if (ADDRESS_68K(address) <  0x800000) return FETCH16ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH16RAM(ADDRESS_68K(address));
+	return m68k_read_memory_16(ADDRESS_68K(address));
+
+}
+
+INLINE uint m68ki_read_32(uint address)
+{
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+	if (ADDRESS_68K(address) <  0x800000) return FETCH32ROM(ADDRESS_68K(address));
+	if (ADDRESS_68K(address) >= 0xFF0000) return FETCH32RAM(ADDRESS_68K(address));
+	return m68k_read_memory_32(ADDRESS_68K(address));
+}
+
+INLINE void m68ki_write_8(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE8RAM(ADDRESS_68K(address), value);
+        } else
+        m68k_write_memory_8(ADDRESS_68K(address), value);
+}
+
+INLINE void m68ki_write_16(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE16RAM(ADDRESS_68K(address), value);
+        } else
+	m68k_write_memory_16(ADDRESS_68K(address), value);
+}
+
+INLINE void m68ki_write_32(uint address, uint value)
+{
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+        if (ADDRESS_68K(address) >= 0xFF0000) {
+          WRITE32RAM(ADDRESS_68K(address), value);
+        } else
+	m68k_write_memory_32(ADDRESS_68K(address), value);
+}
+
+
+#if 0
+INLINE uint m68ki_read_8(uint address)
+{
+  cpu_memory_map *temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+  if (temp->read8) val = (*temp->read8)(ADDRESS_68K(address));
+  else val = READ_BYTE(temp->base, (address) & 0xffff);
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 1, address, val);
+#endif
+
+  return val;
+}
+
+INLINE uint m68ki_read_16(uint address)
+{
+  cpu_memory_map *temp;
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_READ, FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->read16) val = (*temp->read16)(ADDRESS_68K(address));
+  else val = *(uint16 *)(temp->base + ((address) & 0xffff));
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 2, address, val);
+#endif
+
+  return val;
+}
+
+INLINE uint m68ki_read_32(uint address)
+{
+  cpu_memory_map *temp;
+  uint val;
+
+  m68ki_set_fc(FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_READ, FLAG_S | m68ki_get_address_space()) /* auto-disable (see m68kcpu.h) */
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->read16) val = ((*temp->read16)(ADDRESS_68K(address)) << 16) | ((*temp->read16)(ADDRESS_68K(address + 2)));
+  else val = m68k_read_immediate_32(address);
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_R, 4, address, val);
+#endif
+
+  return val;
+}
+
+INLINE void m68ki_write_8(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 1, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write8) (*temp->write8)(ADDRESS_68K(address),value);
+  else WRITE_BYTE(temp->base, (address) & 0xffff, value);
+}
+
+INLINE void m68ki_write_16(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_WRITE, FLAG_S | FUNCTION_CODE_USER_DATA); /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 2, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address),value);
+  else *(uint16 *)(temp->base + ((address) & 0xffff)) = value;
+}
+
+INLINE void m68ki_write_32(uint address, uint value)
+{
+  cpu_memory_map *temp;
+
+  m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+  m68ki_check_address_error(address, MODE_WRITE, FLAG_S | FUNCTION_CODE_USER_DATA) /* auto-disable (see m68kcpu.h) */
+
+#ifdef HOOK_CPU
+  if (cpu_hook)
+    cpu_hook(HOOK_M68K_W, 4, address, value);
+#endif
+
+  temp = &m68ki_cpu.memory_map[((address)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address),value>>16);
+  else *(uint16 *)(temp->base + ((address) & 0xffff)) = value >> 16;
+
+  temp = &m68ki_cpu.memory_map[((address + 2)>>16)&0xff];
+  if (temp->write16) (*temp->write16)(ADDRESS_68K(address+2),value&0xffff);
+  else *(uint16 *)(temp->base + ((address + 2) & 0xffff)) = value;
+}
+#endif
+
+/* --------------------- Effective Address Calculation -------------------- */
+
+/* The program counter relative addressing modes cause operands to be
+ * retrieved from program space, not data space.
+ */
+INLINE uint m68ki_get_ea_pcdi(void)
+{
+  uint old_pc = REG_PC;
+  m68ki_use_program_space() /* auto-disable */
+  return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+}
+
+
+INLINE uint m68ki_get_ea_pcix(void)
+{
+  m68ki_use_program_space() /* auto-disable */
+  return m68ki_get_ea_ix(REG_PC);
+}
+
+/* Indexed addressing modes are encoded as follows:
+ *
+ * Base instruction format:
+ * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+ * x x x x x x x x x x | 1 1 0 | BASE REGISTER      (An)
+ *
+ * Base instruction format for destination EA in move instructions:
+ * F E D C | B A 9    | 8 7 6 | 5 4 3 2 1 0
+ * x x x x | BASE REG | 1 1 0 | X X X X X X       (An)
+ *
+ * Brief extension format:
+ *  F  |  E D C   |  B  |  A 9  | 8 | 7 6 5 4 3 2 1 0
+ * D/A | REGISTER | W/L | SCALE | 0 |  DISPLACEMENT
+ *
+ * Full extension format:
+ *  F     E D C      B     A 9    8   7    6    5 4       3   2 1 0
+ * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS
+ * BASE DISPLACEMENT (0, 16, 32 bit)                (bd)
+ * OUTER DISPLACEMENT (0, 16, 32 bit)               (od)
+ *
+ * D/A:     0 = Dn, 1 = An                          (Xn)
+ * W/L:     0 = W (sign extend), 1 = L              (.SIZE)
+ * SCALE:   00=1, 01=2, 10=4, 11=8                  (*SCALE)
+ * BS:      0=add base reg, 1=suppress base reg     (An suppressed)
+ * IS:      0=add index, 1=suppress index           (Xn suppressed)
+ * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long  (size of bd)
+ *
+ * IS I/IS Operation
+ * 0  000  No Memory Indirect
+ * 0  001  indir prex with null outer
+ * 0  010  indir prex with word outer
+ * 0  011  indir prex with long outer
+ * 0  100  reserved
+ * 0  101  indir postx with null outer
+ * 0  110  indir postx with word outer
+ * 0  111  indir postx with long outer
+ * 1  000  no memory indirect
+ * 1  001  mem indir with null outer
+ * 1  010  mem indir with word outer
+ * 1  011  mem indir with long outer
+ * 1  100-111  reserved
+ */
+INLINE uint m68ki_get_ea_ix(uint An)
+{
+  /* An = base register */
+  uint extension = m68ki_read_imm_16();
+
+  uint Xn = 0;                        /* Index register */
+
+  /* Calculate index */
+  Xn = REG_DA[extension>>12];     /* Xn */
+  if(!BIT_B(extension))           /* W/L */
+    Xn = MAKE_INT_16(Xn);
+
+  /* Add base register and displacement and return */
+  return An + Xn + MAKE_INT_8(extension);
+}
+
+
+/* Fetch operands */
+INLINE uint OPER_AY_AI_8(void)  {uint ea = EA_AY_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PI_8(void)  {uint ea = EA_AY_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PD_8(void)  {uint ea = EA_AY_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_DI_8(void)  {uint ea = EA_AY_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_IX_8(void)  {uint ea = EA_AY_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_AX_AI_8(void)  {uint ea = EA_AX_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PI_8(void)  {uint ea = EA_AX_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PD_8(void)  {uint ea = EA_AX_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_DI_8(void)  {uint ea = EA_AX_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_IX_8(void)  {uint ea = EA_AX_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_A7_PI_8(void)  {uint ea = EA_A7_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_A7_PD_8(void)  {uint ea = EA_A7_PD_8();  return m68ki_read_8(ea); }
+
+INLINE uint OPER_AW_8(void)     {uint ea = EA_AW_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AW_16(void)    {uint ea = EA_AW_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AW_32(void)    {uint ea = EA_AW_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_AL_8(void)     {uint ea = EA_AL_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AL_16(void)    {uint ea = EA_AL_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AL_32(void)    {uint ea = EA_AL_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_PCDI_8(void)   {uint ea = EA_PCDI_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCDI_16(void)  {uint ea = EA_PCDI_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCDI_32(void)  {uint ea = EA_PCDI_32();  return m68ki_read_pcrel_32(ea);}
+INLINE uint OPER_PCIX_8(void)   {uint ea = EA_PCIX_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCIX_16(void)  {uint ea = EA_PCIX_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCIX_32(void)  {uint ea = EA_PCIX_32();  return m68ki_read_pcrel_32(ea);}
+
+
+
+/* ---------------------------- Stack Functions --------------------------- */
+
+/* Push/pull data from the stack */
+INLINE void m68ki_push_16(uint value)
+{
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+  m68ki_write_16(REG_SP, value);
+}
+
+INLINE void m68ki_push_32(uint value)
+{
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+  m68ki_write_32(REG_SP, value);
+}
+
+INLINE uint m68ki_pull_16(void)
+{
+  uint sp = REG_SP;
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+  return m68ki_read_16(sp);
+}
+
+INLINE uint m68ki_pull_32(void)
+{
+  uint sp = REG_SP;
+  REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+  return m68ki_read_32(sp);
+}
+
+
+
+/* ----------------------------- Program Flow ----------------------------- */
+
+/* Jump to a new program location or vector.
+ * These functions will also call the pc_changed callback if it was enabled
+ * in m68kconf.h.
+ */
+INLINE void m68ki_jump(uint new_pc)
+{
+  REG_PC = new_pc;
+}
+
+INLINE void m68ki_jump_vector(uint vector)
+{
+  m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+  REG_PC = m68ki_read_32(vector<<2);
+}
+
+
+/* Branch to a new memory location.
+ * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h.
+ * So far I've found no problems with not calling pc_changed for 8 or 16
+ * bit branches.
+ */
+INLINE void m68ki_branch_8(uint offset)
+{
+  REG_PC += MAKE_INT_8(offset);
+}
+
+INLINE void m68ki_branch_16(uint offset)
+{
+  REG_PC += MAKE_INT_16(offset);
+}
+
+INLINE void m68ki_branch_32(uint offset)
+{
+  REG_PC += offset;
+}
+
+
+
+/* ---------------------------- Status Register --------------------------- */
+
+/* Set the S flag and change the active stack pointer.
+ * Note that value MUST be 4 or 0.
+ */
+INLINE void m68ki_set_s_flag(uint value)
+{
+  /* Backup the old stack pointer */
+  REG_SP_BASE[FLAG_S] = REG_SP;
+  /* Set the S flag */
+  FLAG_S = value;
+  /* Set the new stack pointer */
+  REG_SP = REG_SP_BASE[FLAG_S];
+}
+
+
+/* Set the condition code register */
+INLINE void m68ki_set_ccr(uint value)
+{
+  FLAG_X = BIT_4(value)  << 4;
+  FLAG_N = BIT_3(value)  << 4;
+  FLAG_Z = !BIT_2(value);
+  FLAG_V = BIT_1(value)  << 6;
+  FLAG_C = BIT_0(value)  << 8;
+}
+
+
+/* Set the status register and check for interrupts */
+INLINE void m68ki_set_sr(uint value)
+{
+  /* Set the status register */
+  FLAG_T1 = BIT_F(value);
+  FLAG_INT_MASK = value & 0x0700;
+  m68ki_set_ccr(value);
+  m68ki_set_s_flag((value >> 11) & 4);
+
+  /* Check current IRQ status */
+  m68ki_check_interrupts();
+}
+
+
+/* ------------------------- Exception Processing ------------------------- */
+
+/* Initiate exception processing */
+INLINE uint m68ki_init_exception(void)
+{
+  /* Save the old status register */
+  uint sr = m68ki_get_sr();
+
+  /* Turn off trace flag, clear pending traces */
+  FLAG_T1 = 0;
+  m68ki_clear_trace()
+
+  /* Enter supervisor mode */
+  m68ki_set_s_flag(SFLAG_SET);
+
+  return sr;
+}
+
+/* 3 word stack frame (68000 only) */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr)
+{
+  m68ki_push_32(pc);
+  m68ki_push_16(sr);
+}
+
+#if M68K_EMULATE_ADDRESS_ERROR
+/* Bus error stack frame (68000 only).
+ */
+INLINE void m68ki_stack_frame_buserr(uint sr)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_push_16(sr);
+  m68ki_push_16(REG_IR);
+  m68ki_push_32(m68ki_cpu.aerr_address);  /* access address */
+  /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC
+     * R/W  0 = write, 1 = read
+     * I/N  0 = instruction, 1 = not
+     * FC   3-bit function code
+     */
+  m68ki_push_16(m68ki_cpu.aerr_write_mode | CPU_INSTR_MODE | m68ki_cpu.aerr_fc);
+}
+#endif
+
+/* Used for Group 2 exceptions.
+ */
+INLINE void m68ki_exception_trap(uint vector)
+{
+  uint sr = m68ki_init_exception();
+
+  m68ki_stack_frame_3word(REG_PC, sr);
+
+  m68ki_jump_vector(vector);
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
+INLINE void m68ki_exception_trapN(uint vector)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC, sr);
+  m68ki_jump_vector(vector);
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+#if M68K_EMULATE_TRACE
+/* Exception for trace mode */
+INLINE void m68ki_exception_trace(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC, sr);
+  m68ki_jump_vector(EXCEPTION_TRACE);
+
+  /* Trace nullifies a STOP instruction */
+  CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+  /* Use up some clock cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]);
+}
+#endif
+
+/* Exception for privilege violation */
+static void m68ki_exception_privilege_violation(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for A-Line instructions */
+INLINE void m68ki_exception_1010(void)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_1010);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for F-Line instructions */
+INLINE void m68ki_exception_1111(void)
+{
+  uint sr = m68ki_init_exception();
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_1111);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for illegal instructions */
+INLINE void m68ki_exception_illegal(void)
+{
+  uint sr = m68ki_init_exception();
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  m68ki_stack_frame_3word(REG_PC-2, sr);
+  m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+
+#if M68K_EMULATE_ADDRESS_ERROR
+/* Exception for address error */
+INLINE void m68ki_exception_address_error(void)
+{
+  uint sr = m68ki_init_exception();
+
+  /* If we were processing a bus error, address error, or reset,
+     * this is a catastrophic failure.
+     * Halt the CPU
+     */
+  if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET)
+  {
+    CPU_STOPPED = STOP_LEVEL_HALT;
+    SET_CYCLES(m68ki_cpu.cycle_end - CYC_INSTRUCTION[REG_IR]);
+    return;
+  }
+  CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+
+  /* Note: This is implemented for 68000 only! */
+  m68ki_stack_frame_buserr(sr);
+
+  m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR);
+
+  /* Use up some clock cycles and undo the instruction's cycles */
+  USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR] - CYC_INSTRUCTION[REG_IR]);
+}
+#endif
+
+/* Service an interrupt request and start exception processing */
+INLINE void m68ki_exception_interrupt(uint int_level)
+{
+  uint vector, sr, new_pc;
+
+  #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+  CPU_INSTR_MODE = INSTRUCTION_NO;
+  #endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+  /* Turn off the stopped state */
+  CPU_STOPPED &= STOP_LEVEL_HALT;
+
+  /* If we are halted, don't do anything */
+  if(CPU_STOPPED)
+    return;
+
+  /* Always use the autovectors. */
+  vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
+
+  /* Start exception processing */
+  sr = m68ki_init_exception();
+
+  /* Set the interrupt mask to the level of the one being serviced */
+  FLAG_INT_MASK = int_level<<8;
+
+  /* Acknowledge the interrupt */
+  m68ki_int_ack(int_level);
+
+  /* Get the new PC */
+  m68ki_use_data_space() /* auto-disable (see m68kcpu.h) */
+  new_pc = m68ki_read_32(vector<<2);
+
+  /* If vector is uninitialized, call the uninitialized interrupt vector */
+  if(new_pc == 0)
+    new_pc = m68ki_read_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2));
+
+  /* Generate a stack frame */
+  m68ki_stack_frame_3word(REG_PC, sr);
+
+  m68ki_jump(new_pc);
+
+  /* Update cycle count now */
+  USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* ASG: Check for interrupts */
+INLINE void m68ki_check_interrupts(void)
+{
+  if(CPU_INT_LEVEL > FLAG_INT_MASK)
+    m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCPU__HEADER */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles.h
new file mode 100755
index 0000000..7207fde
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles.h
@@ -0,0 +1,3839 @@
+static unsigned char m68ki_cycles[] =
+{
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,  10*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  16*7,  20*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  18*7,  20*7,  18*7,  22*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+    };
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles_full.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles_full.h
new file mode 100755
index 0000000..d49a776
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_cycles_full.h
@@ -0,0 +1,4099 @@
+static const unsigned char m68ki_cycles[0x10000] =
+{
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,  10*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,   0*7,   0*7,  20*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7,  28*7, 
+   30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  30*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7,  32*7, 
+   34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  34*7,  32*7,  36*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
+   24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  22*7,  26*7,  22*7,  24*7,  18*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  20*7,  24*7,  20*7,  22*7,  16*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  16*7,  20*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,   0*7,   0*7,   4*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
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+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    0*7,   4*7,   4*7,  20*7,   0*7,  16*7,   4*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  18*7,  20*7,  18*7,  22*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  10*7,  12*7,  10*7,  14*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,   8*7,  12*7,   8*7,  12*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,  16*7,  18*7,  12*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7, 
+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  14*7,   0*7,   0*7,   0*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
+   10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,  10*7,   8*7,  12*7,   8*7,  10*7,   4*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
+   18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  16*7,  20*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7,   6*7, 
+   12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7,  12*7, 
+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7, 
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+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7, 
+   22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  22*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7,  24*7, 
+   26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  26*7,  24*7,  28*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
+    0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+    8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7,   8*7, 
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+   14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  14*7,  12*7,  16*7,  12*7,  14*7,   8*7,   0*7,   0*7,   0*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7,   0*7, 
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+   16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  16*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7,  18*7, 
+   20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  20*7,  18*7,  22*7,  18*7,  20*7,  16*7,   0*7,   0*7,   0*7, 
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+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+    4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7,   4*7, 
+};
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table.h
new file mode 100755
index 0000000..e79f7fa
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table.h
@@ -0,0 +1,7675 @@
+static void  (* const m68ki_instruction_jump_table[])(void) =
+{
+  m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, 
+  m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi7, 
+  m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd7, 
+  m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, 
+  m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, 
+  m68k_op_ori_8_aw, m68k_op_ori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, 
+  m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, 
+  m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, 
+  m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, 
+  m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, 
+  m68k_op_ori_16_aw, m68k_op_ori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, 
+  m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, 
+  m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, 
+  m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, 
+  m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, 
+  m68k_op_ori_32_aw, m68k_op_ori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, 
+  m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi7, 
+  m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd7, 
+  m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, 
+  m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, 
+  m68k_op_andi_8_aw, m68k_op_andi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, 
+  m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, 
+  m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, 
+  m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, 
+  m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, 
+  m68k_op_andi_16_aw, m68k_op_andi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, 
+  m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, 
+  m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, 
+  m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, 
+  m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, 
+  m68k_op_andi_32_aw, m68k_op_andi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, 
+  m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi7, 
+  m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd7, 
+  m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, 
+  m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, 
+  m68k_op_subi_8_aw, m68k_op_subi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, 
+  m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, 
+  m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, 
+  m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, 
+  m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, 
+  m68k_op_subi_16_aw, m68k_op_subi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, 
+  m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, 
+  m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, 
+  m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, 
+  m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, 
+  m68k_op_subi_32_aw, m68k_op_subi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, 
+  m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi7, 
+  m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd7, 
+  m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, 
+  m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, 
+  m68k_op_addi_8_aw, m68k_op_addi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, 
+  m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, 
+  m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, 
+  m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, 
+  m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, 
+  m68k_op_addi_16_aw, m68k_op_addi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, 
+  m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, 
+  m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, 
+  m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, 
+  m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, 
+  m68k_op_addi_32_aw, m68k_op_addi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, 
+  m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi7, 
+  m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd7, 
+  m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, 
+  m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, 
+  m68k_op_btst_8_s_aw, m68k_op_btst_8_s_al, m68k_op_btst_8_s_pcdi, m68k_op_btst_8_s_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, 
+  m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi7, 
+  m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd7, 
+  m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, 
+  m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, 
+  m68k_op_bchg_8_s_aw, m68k_op_bchg_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, 
+  m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi7, 
+  m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd7, 
+  m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, 
+  m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, 
+  m68k_op_bclr_8_s_aw, m68k_op_bclr_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, 
+  m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi7, 
+  m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd7, 
+  m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, 
+  m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, 
+  m68k_op_bset_8_s_aw, m68k_op_bset_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, 
+  m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi7, 
+  m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd7, 
+  m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, 
+  m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, 
+  m68k_op_eori_8_aw, m68k_op_eori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, 
+  m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, 
+  m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, 
+  m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, 
+  m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, 
+  m68k_op_eori_16_aw, m68k_op_eori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, 
+  m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, 
+  m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, 
+  m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, 
+  m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, 
+  m68k_op_eori_32_aw, m68k_op_eori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, 
+  m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi7, 
+  m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd7, 
+  m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, 
+  m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, 
+  m68k_op_cmpi_8_aw, m68k_op_cmpi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, 
+  m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, 
+  m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, 
+  m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, 
+  m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, 
+  m68k_op_cmpi_16_aw, m68k_op_cmpi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, 
+  m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, 
+  m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, 
+  m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, 
+  m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, 
+  m68k_op_cmpi_32_aw, m68k_op_cmpi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, 
+  m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi7, 
+  m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd7, 
+  m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, 
+  m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, 
+  m68k_op_move_8_aw_aw, m68k_op_move_8_aw_al, m68k_op_move_8_aw_pcdi, m68k_op_move_8_aw_pcix, m68k_op_move_8_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, 
+  m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi7, 
+  m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd7, 
+  m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, 
+  m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, 
+  m68k_op_move_8_al_aw, m68k_op_move_8_al_al, m68k_op_move_8_al_pcdi, m68k_op_move_8_al_pcix, m68k_op_move_8_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, 
+  m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi7, 
+  m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd7, 
+  m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, 
+  m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, 
+  m68k_op_move_8_pi7_aw, m68k_op_move_8_pi7_al, m68k_op_move_8_pi7_pcdi, m68k_op_move_8_pi7_pcix, m68k_op_move_8_pi7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, 
+  m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi7, 
+  m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd7, 
+  m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, 
+  m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, 
+  m68k_op_move_8_pd7_aw, m68k_op_move_8_pd7_al, m68k_op_move_8_pd7_pcdi, m68k_op_move_8_pd7_pcix, m68k_op_move_8_pd7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, 
+  m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, 
+  m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, 
+  m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, 
+  m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, 
+  m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, 
+  m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, 
+  m68k_op_move_32_aw_aw, m68k_op_move_32_aw_al, m68k_op_move_32_aw_pcdi, m68k_op_move_32_aw_pcix, m68k_op_move_32_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, 
+  m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, 
+  m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, 
+  m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, 
+  m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, 
+  m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, 
+  m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, 
+  m68k_op_move_32_al_aw, m68k_op_move_32_al_al, m68k_op_move_32_al_pcdi, m68k_op_move_32_al_pcix, m68k_op_move_32_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, 
+  m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, 
+  m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, 
+  m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, 
+  m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, 
+  m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, 
+  m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, 
+  m68k_op_move_16_aw_aw, m68k_op_move_16_aw_al, m68k_op_move_16_aw_pcdi, m68k_op_move_16_aw_pcix, m68k_op_move_16_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, 
+  m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, 
+  m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, 
+  m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, 
+  m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, 
+  m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, 
+  m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, 
+  m68k_op_move_16_al_aw, m68k_op_move_16_al_al, m68k_op_move_16_al_pcdi, m68k_op_move_16_al_pcix, m68k_op_move_16_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, 
+  m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi7, 
+  m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd7, 
+  m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, 
+  m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, 
+  m68k_op_negx_8_aw, m68k_op_negx_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, 
+  m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, 
+  m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, 
+  m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, 
+  m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, 
+  m68k_op_negx_16_aw, m68k_op_negx_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, 
+  m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, 
+  m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, 
+  m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, 
+  m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, 
+  m68k_op_negx_32_aw, m68k_op_negx_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, 
+  m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, 
+  m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, 
+  m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, 
+  m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, 
+  m68k_op_move_16_frs_aw, m68k_op_move_16_frs_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, 
+  m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi7, 
+  m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd7, 
+  m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, 
+  m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, 
+  m68k_op_clr_8_aw, m68k_op_clr_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, 
+  m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, 
+  m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, 
+  m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, 
+  m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, 
+  m68k_op_clr_16_aw, m68k_op_clr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, 
+  m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, 
+  m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, 
+  m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, 
+  m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, 
+  m68k_op_clr_32_aw, m68k_op_clr_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, 
+  m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi7, 
+  m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd7, 
+  m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, 
+  m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, 
+  m68k_op_neg_8_aw, m68k_op_neg_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, 
+  m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, 
+  m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, 
+  m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, 
+  m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, 
+  m68k_op_neg_16_aw, m68k_op_neg_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, 
+  m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, 
+  m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, 
+  m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, 
+  m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, 
+  m68k_op_neg_32_aw, m68k_op_neg_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, 
+  m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, 
+  m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, 
+  m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, 
+  m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, 
+  m68k_op_move_16_toc_aw, m68k_op_move_16_toc_al, m68k_op_move_16_toc_pcdi, m68k_op_move_16_toc_pcix, m68k_op_move_16_toc_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, 
+  m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi7, 
+  m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd7, 
+  m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, 
+  m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, 
+  m68k_op_not_8_aw, m68k_op_not_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, 
+  m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, 
+  m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, 
+  m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, 
+  m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, 
+  m68k_op_not_16_aw, m68k_op_not_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, 
+  m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, 
+  m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, 
+  m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, 
+  m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, 
+  m68k_op_not_32_aw, m68k_op_not_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, 
+  m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, 
+  m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, 
+  m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, 
+  m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, 
+  m68k_op_move_16_tos_aw, m68k_op_move_16_tos_al, m68k_op_move_16_tos_pcdi, m68k_op_move_16_tos_pcix, m68k_op_move_16_tos_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, 
+  m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi7, 
+  m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd7, 
+  m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, 
+  m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, 
+  m68k_op_nbcd_8_aw, m68k_op_nbcd_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, 
+  m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, 
+  m68k_op_pea_32_aw, m68k_op_pea_32_al, m68k_op_pea_32_pcdi, m68k_op_pea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, 
+  m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, 
+  m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, 
+  m68k_op_movem_16_re_aw, m68k_op_movem_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, 
+  m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, 
+  m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, 
+  m68k_op_movem_32_re_aw, m68k_op_movem_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, 
+  m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi7, 
+  m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd7, 
+  m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, 
+  m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, 
+  m68k_op_tst_8_aw, m68k_op_tst_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, 
+  m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, 
+  m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, 
+  m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, 
+  m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, 
+  m68k_op_tst_16_aw, m68k_op_tst_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, 
+  m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, 
+  m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, 
+  m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, 
+  m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, 
+  m68k_op_tst_32_aw, m68k_op_tst_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, 
+  m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi7, 
+  m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd7, 
+  m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, 
+  m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, 
+  m68k_op_tas_8_aw, m68k_op_tas_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, 
+  m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, 
+  m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, 
+  m68k_op_movem_16_er_aw, m68k_op_movem_16_er_al, m68k_op_movem_16_er_pcdi, m68k_op_movem_16_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, 
+  m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, 
+  m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, 
+  m68k_op_movem_32_er_aw, m68k_op_movem_32_er_al, m68k_op_movem_32_er_pcdi, m68k_op_movem_32_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16_a7, 
+  m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32_a7, 
+  m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, 
+  m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, 
+  m68k_op_reset, m68k_op_nop, m68k_op_stop, m68k_op_rte_32, m68k_op_illegal, m68k_op_rts_32, m68k_op_trapv, m68k_op_rtr_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, 
+  m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, 
+  m68k_op_jsr_32_aw, m68k_op_jsr_32_al, m68k_op_jsr_32_pcdi, m68k_op_jsr_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, 
+  m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, 
+  m68k_op_jmp_32_aw, m68k_op_jmp_32_al, m68k_op_jmp_32_pcdi, m68k_op_jmp_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, 
+  m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, 
+  m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, 
+  m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi7, 
+  m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd7, 
+  m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, 
+  m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, 
+  m68k_op_st_8_aw, m68k_op_st_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, 
+  m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, 
+  m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, 
+  m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi7, 
+  m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd7, 
+  m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, 
+  m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, 
+  m68k_op_sf_8_aw, m68k_op_sf_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, 
+  m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, 
+  m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, 
+  m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi7, 
+  m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd7, 
+  m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, 
+  m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, 
+  m68k_op_shi_8_aw, m68k_op_shi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, 
+  m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, 
+  m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, 
+  m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi7, 
+  m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd7, 
+  m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, 
+  m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, 
+  m68k_op_sls_8_aw, m68k_op_sls_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, 
+  m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, 
+  m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, 
+  m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi7, 
+  m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd7, 
+  m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, 
+  m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, 
+  m68k_op_scc_8_aw, m68k_op_scc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, 
+  m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, 
+  m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, 
+  m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi7, 
+  m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd7, 
+  m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, 
+  m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, 
+  m68k_op_scs_8_aw, m68k_op_scs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, 
+  m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, 
+  m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, 
+  m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi7, 
+  m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd7, 
+  m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, 
+  m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, 
+  m68k_op_sne_8_aw, m68k_op_sne_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, 
+  m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, 
+  m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, 
+  m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi7, 
+  m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd7, 
+  m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, 
+  m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, 
+  m68k_op_seq_8_aw, m68k_op_seq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, 
+  m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, 
+  m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, 
+  m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi7, 
+  m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd7, 
+  m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, 
+  m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, 
+  m68k_op_svc_8_aw, m68k_op_svc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, 
+  m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, 
+  m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, 
+  m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi7, 
+  m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd7, 
+  m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, 
+  m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, 
+  m68k_op_svs_8_aw, m68k_op_svs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, 
+  m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, 
+  m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, 
+  m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi7, 
+  m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd7, 
+  m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, 
+  m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, 
+  m68k_op_spl_8_aw, m68k_op_spl_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, 
+  m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, 
+  m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, 
+  m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi7, 
+  m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd7, 
+  m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, 
+  m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, 
+  m68k_op_smi_8_aw, m68k_op_smi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, 
+  m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, 
+  m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, 
+  m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi7, 
+  m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd7, 
+  m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, 
+  m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, 
+  m68k_op_sge_8_aw, m68k_op_sge_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, 
+  m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, 
+  m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, 
+  m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi7, 
+  m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd7, 
+  m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, 
+  m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, 
+  m68k_op_slt_8_aw, m68k_op_slt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, 
+  m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, 
+  m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, 
+  m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi7, 
+  m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd7, 
+  m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, 
+  m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, 
+  m68k_op_sgt_8_aw, m68k_op_sgt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, 
+  m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, 
+  m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, 
+  m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi7, 
+  m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd7, 
+  m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, 
+  m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, 
+  m68k_op_sle_8_aw, m68k_op_sle_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bra_16, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_32, 
+  m68k_op_bsr_16, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_32, 
+  m68k_op_bhi_16, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_32, 
+  m68k_op_bls_16, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_32, 
+  m68k_op_bcc_16, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_32, 
+  m68k_op_bcs_16, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_32, 
+  m68k_op_bne_16, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_32, 
+  m68k_op_beq_16, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_32, 
+  m68k_op_bvc_16, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_32, 
+  m68k_op_bvs_16, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_32, 
+  m68k_op_bpl_16, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_32, 
+  m68k_op_bmi_16, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_32, 
+  m68k_op_bge_16, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_32, 
+  m68k_op_blt_16, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_32, 
+  m68k_op_bgt_16, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_32, 
+  m68k_op_ble_16, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_axy7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_axy7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_axy7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_axy7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_axy7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, 
+  m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, 
+  m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, 
+  m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, 
+  m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, 
+  m68k_op_asr_16_aw, m68k_op_asr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, 
+  m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, 
+  m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, 
+  m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, 
+  m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, 
+  m68k_op_asl_16_aw, m68k_op_asl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, 
+  m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, 
+  m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, 
+  m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, 
+  m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, 
+  m68k_op_lsr_16_aw, m68k_op_lsr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, 
+  m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, 
+  m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, 
+  m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, 
+  m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, 
+  m68k_op_lsl_16_aw, m68k_op_lsl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, 
+  m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, 
+  m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, 
+  m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, 
+  m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, 
+  m68k_op_roxr_16_aw, m68k_op_roxr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, 
+  m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, 
+  m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, 
+  m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, 
+  m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, 
+  m68k_op_roxl_16_aw, m68k_op_roxl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, 
+  m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, 
+  m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, 
+  m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, 
+  m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, 
+  m68k_op_ror_16_aw, m68k_op_ror_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, 
+  m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, 
+  m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, 
+  m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, 
+  m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, 
+  m68k_op_rol_16_aw, m68k_op_rol_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  };
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h
new file mode 100755
index 0000000..eac71fe
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68ki_instruction_jump_table_full.h
@@ -0,0 +1,8195 @@
+static void (* const m68ki_instruction_jump_table[0x10000])(void) =
+{
+  m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, m68k_op_ori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, m68k_op_ori_8_ai, 
+  m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi, m68k_op_ori_8_pi7, 
+  m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd, m68k_op_ori_8_pd7, 
+  m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, m68k_op_ori_8_di, 
+  m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, m68k_op_ori_8_ix, 
+  m68k_op_ori_8_aw, m68k_op_ori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, m68k_op_ori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, m68k_op_ori_16_ai, 
+  m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, m68k_op_ori_16_pi, 
+  m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, m68k_op_ori_16_pd, 
+  m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, m68k_op_ori_16_di, 
+  m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, m68k_op_ori_16_ix, 
+  m68k_op_ori_16_aw, m68k_op_ori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_ori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, m68k_op_ori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, m68k_op_ori_32_ai, 
+  m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, m68k_op_ori_32_pi, 
+  m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, m68k_op_ori_32_pd, 
+  m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, m68k_op_ori_32_di, 
+  m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, m68k_op_ori_32_ix, 
+  m68k_op_ori_32_aw, m68k_op_ori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, m68k_op_andi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, m68k_op_andi_8_ai, 
+  m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi, m68k_op_andi_8_pi7, 
+  m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd, m68k_op_andi_8_pd7, 
+  m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, m68k_op_andi_8_di, 
+  m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, m68k_op_andi_8_ix, 
+  m68k_op_andi_8_aw, m68k_op_andi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, m68k_op_andi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, m68k_op_andi_16_ai, 
+  m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, m68k_op_andi_16_pi, 
+  m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, m68k_op_andi_16_pd, 
+  m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, m68k_op_andi_16_di, 
+  m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, m68k_op_andi_16_ix, 
+  m68k_op_andi_16_aw, m68k_op_andi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_andi_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, m68k_op_andi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, m68k_op_andi_32_ai, 
+  m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, m68k_op_andi_32_pi, 
+  m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, m68k_op_andi_32_pd, 
+  m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, m68k_op_andi_32_di, 
+  m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, m68k_op_andi_32_ix, 
+  m68k_op_andi_32_aw, m68k_op_andi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, m68k_op_subi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, m68k_op_subi_8_ai, 
+  m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi, m68k_op_subi_8_pi7, 
+  m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd, m68k_op_subi_8_pd7, 
+  m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, m68k_op_subi_8_di, 
+  m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, m68k_op_subi_8_ix, 
+  m68k_op_subi_8_aw, m68k_op_subi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, m68k_op_subi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, m68k_op_subi_16_ai, 
+  m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, m68k_op_subi_16_pi, 
+  m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, m68k_op_subi_16_pd, 
+  m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, m68k_op_subi_16_di, 
+  m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, m68k_op_subi_16_ix, 
+  m68k_op_subi_16_aw, m68k_op_subi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, m68k_op_subi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, m68k_op_subi_32_ai, 
+  m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, m68k_op_subi_32_pi, 
+  m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, m68k_op_subi_32_pd, 
+  m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, m68k_op_subi_32_di, 
+  m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, m68k_op_subi_32_ix, 
+  m68k_op_subi_32_aw, m68k_op_subi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, m68k_op_addi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, m68k_op_addi_8_ai, 
+  m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi, m68k_op_addi_8_pi7, 
+  m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd, m68k_op_addi_8_pd7, 
+  m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, m68k_op_addi_8_di, 
+  m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, m68k_op_addi_8_ix, 
+  m68k_op_addi_8_aw, m68k_op_addi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, m68k_op_addi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, m68k_op_addi_16_ai, 
+  m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, m68k_op_addi_16_pi, 
+  m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, m68k_op_addi_16_pd, 
+  m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, m68k_op_addi_16_di, 
+  m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, m68k_op_addi_16_ix, 
+  m68k_op_addi_16_aw, m68k_op_addi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, m68k_op_addi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, m68k_op_addi_32_ai, 
+  m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, m68k_op_addi_32_pi, 
+  m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, m68k_op_addi_32_pd, 
+  m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, m68k_op_addi_32_di, 
+  m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, m68k_op_addi_32_ix, 
+  m68k_op_addi_32_aw, m68k_op_addi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, m68k_op_btst_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, m68k_op_btst_8_s_ai, 
+  m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi, m68k_op_btst_8_s_pi7, 
+  m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd, m68k_op_btst_8_s_pd7, 
+  m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, m68k_op_btst_8_s_di, 
+  m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, m68k_op_btst_8_s_ix, 
+  m68k_op_btst_8_s_aw, m68k_op_btst_8_s_al, m68k_op_btst_8_s_pcdi, m68k_op_btst_8_s_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, m68k_op_bchg_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, m68k_op_bchg_8_s_ai, 
+  m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi, m68k_op_bchg_8_s_pi7, 
+  m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd, m68k_op_bchg_8_s_pd7, 
+  m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, m68k_op_bchg_8_s_di, 
+  m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, m68k_op_bchg_8_s_ix, 
+  m68k_op_bchg_8_s_aw, m68k_op_bchg_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, m68k_op_bclr_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, m68k_op_bclr_8_s_ai, 
+  m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi, m68k_op_bclr_8_s_pi7, 
+  m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd, m68k_op_bclr_8_s_pd7, 
+  m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, m68k_op_bclr_8_s_di, 
+  m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, m68k_op_bclr_8_s_ix, 
+  m68k_op_bclr_8_s_aw, m68k_op_bclr_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, m68k_op_bset_32_s_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, m68k_op_bset_8_s_ai, 
+  m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi, m68k_op_bset_8_s_pi7, 
+  m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd, m68k_op_bset_8_s_pd7, 
+  m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, m68k_op_bset_8_s_di, 
+  m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, m68k_op_bset_8_s_ix, 
+  m68k_op_bset_8_s_aw, m68k_op_bset_8_s_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, m68k_op_eori_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, m68k_op_eori_8_ai, 
+  m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi, m68k_op_eori_8_pi7, 
+  m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd, m68k_op_eori_8_pd7, 
+  m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, m68k_op_eori_8_di, 
+  m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, m68k_op_eori_8_ix, 
+  m68k_op_eori_8_aw, m68k_op_eori_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_toc, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, m68k_op_eori_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, m68k_op_eori_16_ai, 
+  m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, m68k_op_eori_16_pi, 
+  m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, m68k_op_eori_16_pd, 
+  m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, m68k_op_eori_16_di, 
+  m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, m68k_op_eori_16_ix, 
+  m68k_op_eori_16_aw, m68k_op_eori_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_eori_16_tos, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, m68k_op_eori_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, m68k_op_eori_32_ai, 
+  m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, m68k_op_eori_32_pi, 
+  m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, m68k_op_eori_32_pd, 
+  m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, m68k_op_eori_32_di, 
+  m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, m68k_op_eori_32_ix, 
+  m68k_op_eori_32_aw, m68k_op_eori_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, m68k_op_cmpi_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, m68k_op_cmpi_8_ai, 
+  m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi, m68k_op_cmpi_8_pi7, 
+  m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd, m68k_op_cmpi_8_pd7, 
+  m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, m68k_op_cmpi_8_di, 
+  m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, m68k_op_cmpi_8_ix, 
+  m68k_op_cmpi_8_aw, m68k_op_cmpi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, m68k_op_cmpi_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, m68k_op_cmpi_16_ai, 
+  m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, m68k_op_cmpi_16_pi, 
+  m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, m68k_op_cmpi_16_pd, 
+  m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, m68k_op_cmpi_16_di, 
+  m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, m68k_op_cmpi_16_ix, 
+  m68k_op_cmpi_16_aw, m68k_op_cmpi_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, m68k_op_cmpi_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, m68k_op_cmpi_32_ai, 
+  m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, m68k_op_cmpi_32_pi, 
+  m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, m68k_op_cmpi_32_pd, 
+  m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, m68k_op_cmpi_32_di, 
+  m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, m68k_op_cmpi_32_ix, 
+  m68k_op_cmpi_32_aw, m68k_op_cmpi_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, m68k_op_btst_32_r_d, 
+  m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, m68k_op_movep_16_er, 
+  m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, m68k_op_btst_8_r_ai, 
+  m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi, m68k_op_btst_8_r_pi7, 
+  m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd, m68k_op_btst_8_r_pd7, 
+  m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, m68k_op_btst_8_r_di, 
+  m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, m68k_op_btst_8_r_ix, 
+  m68k_op_btst_8_r_aw, m68k_op_btst_8_r_al, m68k_op_btst_8_r_pcdi, m68k_op_btst_8_r_pcix, m68k_op_btst_8_r_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, m68k_op_bchg_32_r_d, 
+  m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, m68k_op_movep_32_er, 
+  m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, m68k_op_bchg_8_r_ai, 
+  m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi, m68k_op_bchg_8_r_pi7, 
+  m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd, m68k_op_bchg_8_r_pd7, 
+  m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, m68k_op_bchg_8_r_di, 
+  m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, m68k_op_bchg_8_r_ix, 
+  m68k_op_bchg_8_r_aw, m68k_op_bchg_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, m68k_op_bclr_32_r_d, 
+  m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, m68k_op_movep_16_re, 
+  m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, m68k_op_bclr_8_r_ai, 
+  m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi, m68k_op_bclr_8_r_pi7, 
+  m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd, m68k_op_bclr_8_r_pd7, 
+  m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, m68k_op_bclr_8_r_di, 
+  m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, m68k_op_bclr_8_r_ix, 
+  m68k_op_bclr_8_r_aw, m68k_op_bclr_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, m68k_op_bset_32_r_d, 
+  m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, m68k_op_movep_32_re, 
+  m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, m68k_op_bset_8_r_ai, 
+  m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi, m68k_op_bset_8_r_pi7, 
+  m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd, m68k_op_bset_8_r_pd7, 
+  m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, m68k_op_bset_8_r_di, 
+  m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, m68k_op_bset_8_r_ix, 
+  m68k_op_bset_8_r_aw, m68k_op_bset_8_r_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, m68k_op_move_8_aw_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, m68k_op_move_8_aw_ai, 
+  m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi, m68k_op_move_8_aw_pi7, 
+  m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd, m68k_op_move_8_aw_pd7, 
+  m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, m68k_op_move_8_aw_di, 
+  m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, m68k_op_move_8_aw_ix, 
+  m68k_op_move_8_aw_aw, m68k_op_move_8_aw_al, m68k_op_move_8_aw_pcdi, m68k_op_move_8_aw_pcix, m68k_op_move_8_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, m68k_op_move_8_al_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, m68k_op_move_8_al_ai, 
+  m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi, m68k_op_move_8_al_pi7, 
+  m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd, m68k_op_move_8_al_pd7, 
+  m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, m68k_op_move_8_al_di, 
+  m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, m68k_op_move_8_al_ix, 
+  m68k_op_move_8_al_aw, m68k_op_move_8_al_al, m68k_op_move_8_al_pcdi, m68k_op_move_8_al_pcix, m68k_op_move_8_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, m68k_op_move_8_pi_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, m68k_op_move_8_pi_ai, 
+  m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi, m68k_op_move_8_pi_pi7, 
+  m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd, m68k_op_move_8_pi_pd7, 
+  m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, m68k_op_move_8_pi_di, 
+  m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, m68k_op_move_8_pi_ix, 
+  m68k_op_move_8_pi_aw, m68k_op_move_8_pi_al, m68k_op_move_8_pi_pcdi, m68k_op_move_8_pi_pcix, m68k_op_move_8_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, m68k_op_move_8_pd_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, m68k_op_move_8_pd_ai, 
+  m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi, m68k_op_move_8_pd_pi7, 
+  m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd, m68k_op_move_8_pd_pd7, 
+  m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, m68k_op_move_8_pd_di, 
+  m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, m68k_op_move_8_pd_ix, 
+  m68k_op_move_8_pd_aw, m68k_op_move_8_pd_al, m68k_op_move_8_pd_pcdi, m68k_op_move_8_pd_pcix, m68k_op_move_8_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, m68k_op_move_8_d_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, m68k_op_move_8_d_ai, 
+  m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi, m68k_op_move_8_d_pi7, 
+  m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd, m68k_op_move_8_d_pd7, 
+  m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, m68k_op_move_8_d_di, 
+  m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, m68k_op_move_8_d_ix, 
+  m68k_op_move_8_d_aw, m68k_op_move_8_d_al, m68k_op_move_8_d_pcdi, m68k_op_move_8_d_pcix, m68k_op_move_8_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, m68k_op_move_8_ai_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, m68k_op_move_8_ai_ai, 
+  m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi, m68k_op_move_8_ai_pi7, 
+  m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd, m68k_op_move_8_ai_pd7, 
+  m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, m68k_op_move_8_ai_di, 
+  m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, m68k_op_move_8_ai_ix, 
+  m68k_op_move_8_ai_aw, m68k_op_move_8_ai_al, m68k_op_move_8_ai_pcdi, m68k_op_move_8_ai_pcix, m68k_op_move_8_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, m68k_op_move_8_pi7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, m68k_op_move_8_pi7_ai, 
+  m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi, m68k_op_move_8_pi7_pi7, 
+  m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd, m68k_op_move_8_pi7_pd7, 
+  m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, m68k_op_move_8_pi7_di, 
+  m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, m68k_op_move_8_pi7_ix, 
+  m68k_op_move_8_pi7_aw, m68k_op_move_8_pi7_al, m68k_op_move_8_pi7_pcdi, m68k_op_move_8_pi7_pcix, m68k_op_move_8_pi7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, m68k_op_move_8_pd7_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, m68k_op_move_8_pd7_ai, 
+  m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi, m68k_op_move_8_pd7_pi7, 
+  m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd, m68k_op_move_8_pd7_pd7, 
+  m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, m68k_op_move_8_pd7_di, 
+  m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, m68k_op_move_8_pd7_ix, 
+  m68k_op_move_8_pd7_aw, m68k_op_move_8_pd7_al, m68k_op_move_8_pd7_pcdi, m68k_op_move_8_pd7_pcix, m68k_op_move_8_pd7_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, m68k_op_move_8_di_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, m68k_op_move_8_di_ai, 
+  m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi, m68k_op_move_8_di_pi7, 
+  m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd, m68k_op_move_8_di_pd7, 
+  m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, m68k_op_move_8_di_di, 
+  m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, m68k_op_move_8_di_ix, 
+  m68k_op_move_8_di_aw, m68k_op_move_8_di_al, m68k_op_move_8_di_pcdi, m68k_op_move_8_di_pcix, m68k_op_move_8_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, m68k_op_move_8_ix_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, m68k_op_move_8_ix_ai, 
+  m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi, m68k_op_move_8_ix_pi7, 
+  m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd, m68k_op_move_8_ix_pd7, 
+  m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, m68k_op_move_8_ix_di, 
+  m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, m68k_op_move_8_ix_ix, 
+  m68k_op_move_8_ix_aw, m68k_op_move_8_ix_al, m68k_op_move_8_ix_pcdi, m68k_op_move_8_ix_pcix, m68k_op_move_8_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, m68k_op_move_32_aw_d, 
+  m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, m68k_op_move_32_aw_a, 
+  m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, m68k_op_move_32_aw_ai, 
+  m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, m68k_op_move_32_aw_pi, 
+  m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, m68k_op_move_32_aw_pd, 
+  m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, m68k_op_move_32_aw_di, 
+  m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, m68k_op_move_32_aw_ix, 
+  m68k_op_move_32_aw_aw, m68k_op_move_32_aw_al, m68k_op_move_32_aw_pcdi, m68k_op_move_32_aw_pcix, m68k_op_move_32_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, m68k_op_move_32_al_d, 
+  m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, m68k_op_move_32_al_a, 
+  m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, m68k_op_move_32_al_ai, 
+  m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, m68k_op_move_32_al_pi, 
+  m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, m68k_op_move_32_al_pd, 
+  m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, m68k_op_move_32_al_di, 
+  m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, m68k_op_move_32_al_ix, 
+  m68k_op_move_32_al_aw, m68k_op_move_32_al_al, m68k_op_move_32_al_pcdi, m68k_op_move_32_al_pcix, m68k_op_move_32_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, m68k_op_move_32_d_d, 
+  m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, m68k_op_move_32_d_a, 
+  m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, m68k_op_move_32_d_ai, 
+  m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, m68k_op_move_32_d_pi, 
+  m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, m68k_op_move_32_d_pd, 
+  m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, m68k_op_move_32_d_di, 
+  m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, m68k_op_move_32_d_ix, 
+  m68k_op_move_32_d_aw, m68k_op_move_32_d_al, m68k_op_move_32_d_pcdi, m68k_op_move_32_d_pcix, m68k_op_move_32_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, m68k_op_movea_32_d, 
+  m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, m68k_op_movea_32_a, 
+  m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, m68k_op_movea_32_ai, 
+  m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, m68k_op_movea_32_pi, 
+  m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, m68k_op_movea_32_pd, 
+  m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, m68k_op_movea_32_di, 
+  m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, m68k_op_movea_32_ix, 
+  m68k_op_movea_32_aw, m68k_op_movea_32_al, m68k_op_movea_32_pcdi, m68k_op_movea_32_pcix, m68k_op_movea_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, m68k_op_move_32_ai_d, 
+  m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, m68k_op_move_32_ai_a, 
+  m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, m68k_op_move_32_ai_ai, 
+  m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, m68k_op_move_32_ai_pi, 
+  m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, m68k_op_move_32_ai_pd, 
+  m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, m68k_op_move_32_ai_di, 
+  m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, m68k_op_move_32_ai_ix, 
+  m68k_op_move_32_ai_aw, m68k_op_move_32_ai_al, m68k_op_move_32_ai_pcdi, m68k_op_move_32_ai_pcix, m68k_op_move_32_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, m68k_op_move_32_pi_d, 
+  m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, m68k_op_move_32_pi_a, 
+  m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, m68k_op_move_32_pi_ai, 
+  m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, m68k_op_move_32_pi_pi, 
+  m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, m68k_op_move_32_pi_pd, 
+  m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, m68k_op_move_32_pi_di, 
+  m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, m68k_op_move_32_pi_ix, 
+  m68k_op_move_32_pi_aw, m68k_op_move_32_pi_al, m68k_op_move_32_pi_pcdi, m68k_op_move_32_pi_pcix, m68k_op_move_32_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, m68k_op_move_32_pd_d, 
+  m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, m68k_op_move_32_pd_a, 
+  m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, m68k_op_move_32_pd_ai, 
+  m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, m68k_op_move_32_pd_pi, 
+  m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, m68k_op_move_32_pd_pd, 
+  m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, m68k_op_move_32_pd_di, 
+  m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, m68k_op_move_32_pd_ix, 
+  m68k_op_move_32_pd_aw, m68k_op_move_32_pd_al, m68k_op_move_32_pd_pcdi, m68k_op_move_32_pd_pcix, m68k_op_move_32_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, m68k_op_move_32_di_d, 
+  m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, m68k_op_move_32_di_a, 
+  m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, m68k_op_move_32_di_ai, 
+  m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, m68k_op_move_32_di_pi, 
+  m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, m68k_op_move_32_di_pd, 
+  m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, m68k_op_move_32_di_di, 
+  m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, m68k_op_move_32_di_ix, 
+  m68k_op_move_32_di_aw, m68k_op_move_32_di_al, m68k_op_move_32_di_pcdi, m68k_op_move_32_di_pcix, m68k_op_move_32_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, m68k_op_move_32_ix_d, 
+  m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, m68k_op_move_32_ix_a, 
+  m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, m68k_op_move_32_ix_ai, 
+  m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, m68k_op_move_32_ix_pi, 
+  m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, m68k_op_move_32_ix_pd, 
+  m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, m68k_op_move_32_ix_di, 
+  m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, m68k_op_move_32_ix_ix, 
+  m68k_op_move_32_ix_aw, m68k_op_move_32_ix_al, m68k_op_move_32_ix_pcdi, m68k_op_move_32_ix_pcix, m68k_op_move_32_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, m68k_op_move_16_aw_d, 
+  m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, m68k_op_move_16_aw_a, 
+  m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, m68k_op_move_16_aw_ai, 
+  m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, m68k_op_move_16_aw_pi, 
+  m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, m68k_op_move_16_aw_pd, 
+  m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, m68k_op_move_16_aw_di, 
+  m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, m68k_op_move_16_aw_ix, 
+  m68k_op_move_16_aw_aw, m68k_op_move_16_aw_al, m68k_op_move_16_aw_pcdi, m68k_op_move_16_aw_pcix, m68k_op_move_16_aw_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, m68k_op_move_16_al_d, 
+  m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, m68k_op_move_16_al_a, 
+  m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, m68k_op_move_16_al_ai, 
+  m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, m68k_op_move_16_al_pi, 
+  m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, m68k_op_move_16_al_pd, 
+  m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, m68k_op_move_16_al_di, 
+  m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, m68k_op_move_16_al_ix, 
+  m68k_op_move_16_al_aw, m68k_op_move_16_al_al, m68k_op_move_16_al_pcdi, m68k_op_move_16_al_pcix, m68k_op_move_16_al_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, m68k_op_move_16_d_d, 
+  m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, m68k_op_move_16_d_a, 
+  m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, m68k_op_move_16_d_ai, 
+  m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, m68k_op_move_16_d_pi, 
+  m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, m68k_op_move_16_d_pd, 
+  m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, m68k_op_move_16_d_di, 
+  m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, m68k_op_move_16_d_ix, 
+  m68k_op_move_16_d_aw, m68k_op_move_16_d_al, m68k_op_move_16_d_pcdi, m68k_op_move_16_d_pcix, m68k_op_move_16_d_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, m68k_op_movea_16_d, 
+  m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, m68k_op_movea_16_a, 
+  m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, m68k_op_movea_16_ai, 
+  m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, m68k_op_movea_16_pi, 
+  m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, m68k_op_movea_16_pd, 
+  m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, m68k_op_movea_16_di, 
+  m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, m68k_op_movea_16_ix, 
+  m68k_op_movea_16_aw, m68k_op_movea_16_al, m68k_op_movea_16_pcdi, m68k_op_movea_16_pcix, m68k_op_movea_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, m68k_op_move_16_ai_d, 
+  m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, m68k_op_move_16_ai_a, 
+  m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, m68k_op_move_16_ai_ai, 
+  m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, m68k_op_move_16_ai_pi, 
+  m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, m68k_op_move_16_ai_pd, 
+  m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, m68k_op_move_16_ai_di, 
+  m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, m68k_op_move_16_ai_ix, 
+  m68k_op_move_16_ai_aw, m68k_op_move_16_ai_al, m68k_op_move_16_ai_pcdi, m68k_op_move_16_ai_pcix, m68k_op_move_16_ai_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, m68k_op_move_16_pi_d, 
+  m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, m68k_op_move_16_pi_a, 
+  m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, m68k_op_move_16_pi_ai, 
+  m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, m68k_op_move_16_pi_pi, 
+  m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, m68k_op_move_16_pi_pd, 
+  m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, m68k_op_move_16_pi_di, 
+  m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, m68k_op_move_16_pi_ix, 
+  m68k_op_move_16_pi_aw, m68k_op_move_16_pi_al, m68k_op_move_16_pi_pcdi, m68k_op_move_16_pi_pcix, m68k_op_move_16_pi_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, m68k_op_move_16_pd_d, 
+  m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, m68k_op_move_16_pd_a, 
+  m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, m68k_op_move_16_pd_ai, 
+  m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, m68k_op_move_16_pd_pi, 
+  m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, m68k_op_move_16_pd_pd, 
+  m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, m68k_op_move_16_pd_di, 
+  m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, m68k_op_move_16_pd_ix, 
+  m68k_op_move_16_pd_aw, m68k_op_move_16_pd_al, m68k_op_move_16_pd_pcdi, m68k_op_move_16_pd_pcix, m68k_op_move_16_pd_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, m68k_op_move_16_di_d, 
+  m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, m68k_op_move_16_di_a, 
+  m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, m68k_op_move_16_di_ai, 
+  m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, m68k_op_move_16_di_pi, 
+  m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, m68k_op_move_16_di_pd, 
+  m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, m68k_op_move_16_di_di, 
+  m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, m68k_op_move_16_di_ix, 
+  m68k_op_move_16_di_aw, m68k_op_move_16_di_al, m68k_op_move_16_di_pcdi, m68k_op_move_16_di_pcix, m68k_op_move_16_di_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, m68k_op_move_16_ix_d, 
+  m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, m68k_op_move_16_ix_a, 
+  m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, m68k_op_move_16_ix_ai, 
+  m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, m68k_op_move_16_ix_pi, 
+  m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, m68k_op_move_16_ix_pd, 
+  m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, m68k_op_move_16_ix_di, 
+  m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, m68k_op_move_16_ix_ix, 
+  m68k_op_move_16_ix_aw, m68k_op_move_16_ix_al, m68k_op_move_16_ix_pcdi, m68k_op_move_16_ix_pcix, m68k_op_move_16_ix_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, m68k_op_negx_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, m68k_op_negx_8_ai, 
+  m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi, m68k_op_negx_8_pi7, 
+  m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd, m68k_op_negx_8_pd7, 
+  m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, m68k_op_negx_8_di, 
+  m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, m68k_op_negx_8_ix, 
+  m68k_op_negx_8_aw, m68k_op_negx_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, m68k_op_negx_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, m68k_op_negx_16_ai, 
+  m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, m68k_op_negx_16_pi, 
+  m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, m68k_op_negx_16_pd, 
+  m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, m68k_op_negx_16_di, 
+  m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, m68k_op_negx_16_ix, 
+  m68k_op_negx_16_aw, m68k_op_negx_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, m68k_op_negx_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, m68k_op_negx_32_ai, 
+  m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, m68k_op_negx_32_pi, 
+  m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, m68k_op_negx_32_pd, 
+  m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, m68k_op_negx_32_di, 
+  m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, m68k_op_negx_32_ix, 
+  m68k_op_negx_32_aw, m68k_op_negx_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, m68k_op_move_16_frs_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, m68k_op_move_16_frs_ai, 
+  m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, m68k_op_move_16_frs_pi, 
+  m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, m68k_op_move_16_frs_pd, 
+  m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, m68k_op_move_16_frs_di, 
+  m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, m68k_op_move_16_frs_ix, 
+  m68k_op_move_16_frs_aw, m68k_op_move_16_frs_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, m68k_op_clr_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, m68k_op_clr_8_ai, 
+  m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi, m68k_op_clr_8_pi7, 
+  m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd, m68k_op_clr_8_pd7, 
+  m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, m68k_op_clr_8_di, 
+  m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, m68k_op_clr_8_ix, 
+  m68k_op_clr_8_aw, m68k_op_clr_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, m68k_op_clr_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, m68k_op_clr_16_ai, 
+  m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, m68k_op_clr_16_pi, 
+  m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, m68k_op_clr_16_pd, 
+  m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, m68k_op_clr_16_di, 
+  m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, m68k_op_clr_16_ix, 
+  m68k_op_clr_16_aw, m68k_op_clr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, m68k_op_clr_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, m68k_op_clr_32_ai, 
+  m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, m68k_op_clr_32_pi, 
+  m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, m68k_op_clr_32_pd, 
+  m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, m68k_op_clr_32_di, 
+  m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, m68k_op_clr_32_ix, 
+  m68k_op_clr_32_aw, m68k_op_clr_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, m68k_op_neg_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, m68k_op_neg_8_ai, 
+  m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi, m68k_op_neg_8_pi7, 
+  m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd, m68k_op_neg_8_pd7, 
+  m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, m68k_op_neg_8_di, 
+  m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, m68k_op_neg_8_ix, 
+  m68k_op_neg_8_aw, m68k_op_neg_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, m68k_op_neg_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, m68k_op_neg_16_ai, 
+  m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, m68k_op_neg_16_pi, 
+  m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, m68k_op_neg_16_pd, 
+  m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, m68k_op_neg_16_di, 
+  m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, m68k_op_neg_16_ix, 
+  m68k_op_neg_16_aw, m68k_op_neg_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, m68k_op_neg_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, m68k_op_neg_32_ai, 
+  m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, m68k_op_neg_32_pi, 
+  m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, m68k_op_neg_32_pd, 
+  m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, m68k_op_neg_32_di, 
+  m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, m68k_op_neg_32_ix, 
+  m68k_op_neg_32_aw, m68k_op_neg_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, m68k_op_move_16_toc_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, m68k_op_move_16_toc_ai, 
+  m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, m68k_op_move_16_toc_pi, 
+  m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, m68k_op_move_16_toc_pd, 
+  m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, m68k_op_move_16_toc_di, 
+  m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, m68k_op_move_16_toc_ix, 
+  m68k_op_move_16_toc_aw, m68k_op_move_16_toc_al, m68k_op_move_16_toc_pcdi, m68k_op_move_16_toc_pcix, m68k_op_move_16_toc_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, m68k_op_not_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, m68k_op_not_8_ai, 
+  m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi, m68k_op_not_8_pi7, 
+  m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd, m68k_op_not_8_pd7, 
+  m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, m68k_op_not_8_di, 
+  m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, m68k_op_not_8_ix, 
+  m68k_op_not_8_aw, m68k_op_not_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, m68k_op_not_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, m68k_op_not_16_ai, 
+  m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, m68k_op_not_16_pi, 
+  m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, m68k_op_not_16_pd, 
+  m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, m68k_op_not_16_di, 
+  m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, m68k_op_not_16_ix, 
+  m68k_op_not_16_aw, m68k_op_not_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, m68k_op_not_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, m68k_op_not_32_ai, 
+  m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, m68k_op_not_32_pi, 
+  m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, m68k_op_not_32_pd, 
+  m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, m68k_op_not_32_di, 
+  m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, m68k_op_not_32_ix, 
+  m68k_op_not_32_aw, m68k_op_not_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, m68k_op_move_16_tos_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, m68k_op_move_16_tos_ai, 
+  m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, m68k_op_move_16_tos_pi, 
+  m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, m68k_op_move_16_tos_pd, 
+  m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, m68k_op_move_16_tos_di, 
+  m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, m68k_op_move_16_tos_ix, 
+  m68k_op_move_16_tos_aw, m68k_op_move_16_tos_al, m68k_op_move_16_tos_pcdi, m68k_op_move_16_tos_pcix, m68k_op_move_16_tos_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, m68k_op_nbcd_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, m68k_op_nbcd_8_ai, 
+  m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi, m68k_op_nbcd_8_pi7, 
+  m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd, m68k_op_nbcd_8_pd7, 
+  m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, m68k_op_nbcd_8_di, 
+  m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, m68k_op_nbcd_8_ix, 
+  m68k_op_nbcd_8_aw, m68k_op_nbcd_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, m68k_op_swap_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, m68k_op_pea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, m68k_op_pea_32_di, 
+  m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, m68k_op_pea_32_ix, 
+  m68k_op_pea_32_aw, m68k_op_pea_32_al, m68k_op_pea_32_pcdi, m68k_op_pea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, m68k_op_ext_16, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, m68k_op_movem_16_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, m68k_op_movem_16_re_pd, 
+  m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, m68k_op_movem_16_re_di, 
+  m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, m68k_op_movem_16_re_ix, 
+  m68k_op_movem_16_re_aw, m68k_op_movem_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, m68k_op_ext_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, m68k_op_movem_32_re_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, m68k_op_movem_32_re_pd, 
+  m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, m68k_op_movem_32_re_di, 
+  m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, m68k_op_movem_32_re_ix, 
+  m68k_op_movem_32_re_aw, m68k_op_movem_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, m68k_op_tst_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, m68k_op_tst_8_ai, 
+  m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi, m68k_op_tst_8_pi7, 
+  m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd, m68k_op_tst_8_pd7, 
+  m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, m68k_op_tst_8_di, 
+  m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, m68k_op_tst_8_ix, 
+  m68k_op_tst_8_aw, m68k_op_tst_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, m68k_op_tst_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, m68k_op_tst_16_ai, 
+  m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, m68k_op_tst_16_pi, 
+  m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, m68k_op_tst_16_pd, 
+  m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, m68k_op_tst_16_di, 
+  m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, m68k_op_tst_16_ix, 
+  m68k_op_tst_16_aw, m68k_op_tst_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, m68k_op_tst_32_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, m68k_op_tst_32_ai, 
+  m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, m68k_op_tst_32_pi, 
+  m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, m68k_op_tst_32_pd, 
+  m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, m68k_op_tst_32_di, 
+  m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, m68k_op_tst_32_ix, 
+  m68k_op_tst_32_aw, m68k_op_tst_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, m68k_op_tas_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, m68k_op_tas_8_ai, 
+  m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi, m68k_op_tas_8_pi7, 
+  m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd, m68k_op_tas_8_pd7, 
+  m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, m68k_op_tas_8_di, 
+  m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, m68k_op_tas_8_ix, 
+  m68k_op_tas_8_aw, m68k_op_tas_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, m68k_op_movem_16_er_ai, 
+  m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, m68k_op_movem_16_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, m68k_op_movem_16_er_di, 
+  m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, m68k_op_movem_16_er_ix, 
+  m68k_op_movem_16_er_aw, m68k_op_movem_16_er_al, m68k_op_movem_16_er_pcdi, m68k_op_movem_16_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, m68k_op_movem_32_er_ai, 
+  m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, m68k_op_movem_32_er_pi, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, m68k_op_movem_32_er_di, 
+  m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, m68k_op_movem_32_er_ix, 
+  m68k_op_movem_32_er_aw, m68k_op_movem_32_er_al, m68k_op_movem_32_er_pcdi, m68k_op_movem_32_er_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, m68k_op_trap, 
+  m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16, m68k_op_link_16_a7, 
+  m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32, m68k_op_unlk_32_a7, 
+  m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, m68k_op_move_32_tou, 
+  m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, m68k_op_move_32_fru, 
+  m68k_op_reset, m68k_op_nop, m68k_op_stop, m68k_op_rte_32, m68k_op_illegal, m68k_op_rts_32, m68k_op_trapv, m68k_op_rtr_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, m68k_op_jsr_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, m68k_op_jsr_32_di, 
+  m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, m68k_op_jsr_32_ix, 
+  m68k_op_jsr_32_aw, m68k_op_jsr_32_al, m68k_op_jsr_32_pcdi, m68k_op_jsr_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, m68k_op_jmp_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, m68k_op_jmp_32_di, 
+  m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, m68k_op_jmp_32_ix, 
+  m68k_op_jmp_32_aw, m68k_op_jmp_32_al, m68k_op_jmp_32_pcdi, m68k_op_jmp_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, m68k_op_chk_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, m68k_op_chk_16_ai, 
+  m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, m68k_op_chk_16_pi, 
+  m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, m68k_op_chk_16_pd, 
+  m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, m68k_op_chk_16_di, 
+  m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, m68k_op_chk_16_ix, 
+  m68k_op_chk_16_aw, m68k_op_chk_16_al, m68k_op_chk_16_pcdi, m68k_op_chk_16_pcix, m68k_op_chk_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, m68k_op_lea_32_ai, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, m68k_op_lea_32_di, 
+  m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, m68k_op_lea_32_ix, 
+  m68k_op_lea_32_aw, m68k_op_lea_32_al, m68k_op_lea_32_pcdi, m68k_op_lea_32_pcix, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, m68k_op_st_8_d, 
+  m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, m68k_op_dbt_16, 
+  m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, m68k_op_st_8_ai, 
+  m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi, m68k_op_st_8_pi7, 
+  m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd, m68k_op_st_8_pd7, 
+  m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, m68k_op_st_8_di, 
+  m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, m68k_op_st_8_ix, 
+  m68k_op_st_8_aw, m68k_op_st_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, m68k_op_sf_8_d, 
+  m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, m68k_op_dbf_16, 
+  m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, m68k_op_sf_8_ai, 
+  m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi, m68k_op_sf_8_pi7, 
+  m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd, m68k_op_sf_8_pd7, 
+  m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, m68k_op_sf_8_di, 
+  m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, m68k_op_sf_8_ix, 
+  m68k_op_sf_8_aw, m68k_op_sf_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, m68k_op_shi_8_d, 
+  m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, m68k_op_dbhi_16, 
+  m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, m68k_op_shi_8_ai, 
+  m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi, m68k_op_shi_8_pi7, 
+  m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd, m68k_op_shi_8_pd7, 
+  m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, m68k_op_shi_8_di, 
+  m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, m68k_op_shi_8_ix, 
+  m68k_op_shi_8_aw, m68k_op_shi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, m68k_op_sls_8_d, 
+  m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, m68k_op_dbls_16, 
+  m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, m68k_op_sls_8_ai, 
+  m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi, m68k_op_sls_8_pi7, 
+  m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd, m68k_op_sls_8_pd7, 
+  m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, m68k_op_sls_8_di, 
+  m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, m68k_op_sls_8_ix, 
+  m68k_op_sls_8_aw, m68k_op_sls_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, m68k_op_scc_8_d, 
+  m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, m68k_op_dbcc_16, 
+  m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, m68k_op_scc_8_ai, 
+  m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi, m68k_op_scc_8_pi7, 
+  m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd, m68k_op_scc_8_pd7, 
+  m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, m68k_op_scc_8_di, 
+  m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, m68k_op_scc_8_ix, 
+  m68k_op_scc_8_aw, m68k_op_scc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, m68k_op_scs_8_d, 
+  m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, m68k_op_dbcs_16, 
+  m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, m68k_op_scs_8_ai, 
+  m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi, m68k_op_scs_8_pi7, 
+  m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd, m68k_op_scs_8_pd7, 
+  m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, m68k_op_scs_8_di, 
+  m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, m68k_op_scs_8_ix, 
+  m68k_op_scs_8_aw, m68k_op_scs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, m68k_op_sne_8_d, 
+  m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, m68k_op_dbne_16, 
+  m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, m68k_op_sne_8_ai, 
+  m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi, m68k_op_sne_8_pi7, 
+  m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd, m68k_op_sne_8_pd7, 
+  m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, m68k_op_sne_8_di, 
+  m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, m68k_op_sne_8_ix, 
+  m68k_op_sne_8_aw, m68k_op_sne_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, m68k_op_seq_8_d, 
+  m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, m68k_op_dbeq_16, 
+  m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, m68k_op_seq_8_ai, 
+  m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi, m68k_op_seq_8_pi7, 
+  m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd, m68k_op_seq_8_pd7, 
+  m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, m68k_op_seq_8_di, 
+  m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, m68k_op_seq_8_ix, 
+  m68k_op_seq_8_aw, m68k_op_seq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, m68k_op_svc_8_d, 
+  m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, m68k_op_dbvc_16, 
+  m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, m68k_op_svc_8_ai, 
+  m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi, m68k_op_svc_8_pi7, 
+  m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd, m68k_op_svc_8_pd7, 
+  m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, m68k_op_svc_8_di, 
+  m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, m68k_op_svc_8_ix, 
+  m68k_op_svc_8_aw, m68k_op_svc_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, m68k_op_svs_8_d, 
+  m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, m68k_op_dbvs_16, 
+  m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, m68k_op_svs_8_ai, 
+  m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi, m68k_op_svs_8_pi7, 
+  m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd, m68k_op_svs_8_pd7, 
+  m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, m68k_op_svs_8_di, 
+  m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, m68k_op_svs_8_ix, 
+  m68k_op_svs_8_aw, m68k_op_svs_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, m68k_op_spl_8_d, 
+  m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, m68k_op_dbpl_16, 
+  m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, m68k_op_spl_8_ai, 
+  m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi, m68k_op_spl_8_pi7, 
+  m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd, m68k_op_spl_8_pd7, 
+  m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, m68k_op_spl_8_di, 
+  m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, m68k_op_spl_8_ix, 
+  m68k_op_spl_8_aw, m68k_op_spl_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, m68k_op_smi_8_d, 
+  m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, m68k_op_dbmi_16, 
+  m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, m68k_op_smi_8_ai, 
+  m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi, m68k_op_smi_8_pi7, 
+  m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd, m68k_op_smi_8_pd7, 
+  m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, m68k_op_smi_8_di, 
+  m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, m68k_op_smi_8_ix, 
+  m68k_op_smi_8_aw, m68k_op_smi_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, m68k_op_sge_8_d, 
+  m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, m68k_op_dbge_16, 
+  m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, m68k_op_sge_8_ai, 
+  m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi, m68k_op_sge_8_pi7, 
+  m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd, m68k_op_sge_8_pd7, 
+  m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, m68k_op_sge_8_di, 
+  m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, m68k_op_sge_8_ix, 
+  m68k_op_sge_8_aw, m68k_op_sge_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, m68k_op_slt_8_d, 
+  m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, m68k_op_dblt_16, 
+  m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, m68k_op_slt_8_ai, 
+  m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi, m68k_op_slt_8_pi7, 
+  m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd, m68k_op_slt_8_pd7, 
+  m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, m68k_op_slt_8_di, 
+  m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, m68k_op_slt_8_ix, 
+  m68k_op_slt_8_aw, m68k_op_slt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, m68k_op_addq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, m68k_op_addq_8_ai, 
+  m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi, m68k_op_addq_8_pi7, 
+  m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd, m68k_op_addq_8_pd7, 
+  m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, m68k_op_addq_8_di, 
+  m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, m68k_op_addq_8_ix, 
+  m68k_op_addq_8_aw, m68k_op_addq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, m68k_op_addq_16_d, 
+  m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, m68k_op_addq_16_a, 
+  m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, m68k_op_addq_16_ai, 
+  m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, m68k_op_addq_16_pi, 
+  m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, m68k_op_addq_16_pd, 
+  m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, m68k_op_addq_16_di, 
+  m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, m68k_op_addq_16_ix, 
+  m68k_op_addq_16_aw, m68k_op_addq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, m68k_op_addq_32_d, 
+  m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, m68k_op_addq_32_a, 
+  m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, m68k_op_addq_32_ai, 
+  m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, m68k_op_addq_32_pi, 
+  m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, m68k_op_addq_32_pd, 
+  m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, m68k_op_addq_32_di, 
+  m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, m68k_op_addq_32_ix, 
+  m68k_op_addq_32_aw, m68k_op_addq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, m68k_op_sgt_8_d, 
+  m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, m68k_op_dbgt_16, 
+  m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, m68k_op_sgt_8_ai, 
+  m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi, m68k_op_sgt_8_pi7, 
+  m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd, m68k_op_sgt_8_pd7, 
+  m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, m68k_op_sgt_8_di, 
+  m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, m68k_op_sgt_8_ix, 
+  m68k_op_sgt_8_aw, m68k_op_sgt_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, m68k_op_subq_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, m68k_op_subq_8_ai, 
+  m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi, m68k_op_subq_8_pi7, 
+  m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd, m68k_op_subq_8_pd7, 
+  m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, m68k_op_subq_8_di, 
+  m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, m68k_op_subq_8_ix, 
+  m68k_op_subq_8_aw, m68k_op_subq_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, m68k_op_subq_16_d, 
+  m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, m68k_op_subq_16_a, 
+  m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, m68k_op_subq_16_ai, 
+  m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, m68k_op_subq_16_pi, 
+  m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, m68k_op_subq_16_pd, 
+  m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, m68k_op_subq_16_di, 
+  m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, m68k_op_subq_16_ix, 
+  m68k_op_subq_16_aw, m68k_op_subq_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, m68k_op_subq_32_d, 
+  m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, m68k_op_subq_32_a, 
+  m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, m68k_op_subq_32_ai, 
+  m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, m68k_op_subq_32_pi, 
+  m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, m68k_op_subq_32_pd, 
+  m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, m68k_op_subq_32_di, 
+  m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, m68k_op_subq_32_ix, 
+  m68k_op_subq_32_aw, m68k_op_subq_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, m68k_op_sle_8_d, 
+  m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, m68k_op_dble_16, 
+  m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, m68k_op_sle_8_ai, 
+  m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi, m68k_op_sle_8_pi7, 
+  m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd, m68k_op_sle_8_pd7, 
+  m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, m68k_op_sle_8_di, 
+  m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, m68k_op_sle_8_ix, 
+  m68k_op_sle_8_aw, m68k_op_sle_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_bra_16, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, 
+  m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_8, m68k_op_bra_32, 
+  m68k_op_bsr_16, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, 
+  m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_8, m68k_op_bsr_32, 
+  m68k_op_bhi_16, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, 
+  m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_8, m68k_op_bhi_32, 
+  m68k_op_bls_16, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, 
+  m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_8, m68k_op_bls_32, 
+  m68k_op_bcc_16, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, 
+  m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_8, m68k_op_bcc_32, 
+  m68k_op_bcs_16, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, 
+  m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_8, m68k_op_bcs_32, 
+  m68k_op_bne_16, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, 
+  m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_8, m68k_op_bne_32, 
+  m68k_op_beq_16, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, 
+  m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_8, m68k_op_beq_32, 
+  m68k_op_bvc_16, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, 
+  m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_8, m68k_op_bvc_32, 
+  m68k_op_bvs_16, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, 
+  m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_8, m68k_op_bvs_32, 
+  m68k_op_bpl_16, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, 
+  m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_8, m68k_op_bpl_32, 
+  m68k_op_bmi_16, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, 
+  m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_8, m68k_op_bmi_32, 
+  m68k_op_bge_16, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, 
+  m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_8, m68k_op_bge_32, 
+  m68k_op_blt_16, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, 
+  m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_8, m68k_op_blt_32, 
+  m68k_op_bgt_16, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, 
+  m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_8, m68k_op_bgt_32, 
+  m68k_op_ble_16, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, 
+  m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_8, m68k_op_ble_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, m68k_op_moveq_32, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm, m68k_op_sbcd_8_mm_ay7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, m68k_op_or_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, m68k_op_or_8_er_ai, 
+  m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi, m68k_op_or_8_er_pi7, 
+  m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd, m68k_op_or_8_er_pd7, 
+  m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, m68k_op_or_8_er_di, 
+  m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, m68k_op_or_8_er_ix, 
+  m68k_op_or_8_er_aw, m68k_op_or_8_er_al, m68k_op_or_8_er_pcdi, m68k_op_or_8_er_pcix, m68k_op_or_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, m68k_op_or_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, m68k_op_or_16_er_ai, 
+  m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, m68k_op_or_16_er_pi, 
+  m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, m68k_op_or_16_er_pd, 
+  m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, m68k_op_or_16_er_di, 
+  m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, m68k_op_or_16_er_ix, 
+  m68k_op_or_16_er_aw, m68k_op_or_16_er_al, m68k_op_or_16_er_pcdi, m68k_op_or_16_er_pcix, m68k_op_or_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, m68k_op_or_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, m68k_op_or_32_er_ai, 
+  m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, m68k_op_or_32_er_pi, 
+  m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, m68k_op_or_32_er_pd, 
+  m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, m68k_op_or_32_er_di, 
+  m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, m68k_op_or_32_er_ix, 
+  m68k_op_or_32_er_aw, m68k_op_or_32_er_al, m68k_op_or_32_er_pcdi, m68k_op_or_32_er_pcix, m68k_op_or_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, m68k_op_divu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, m68k_op_divu_16_ai, 
+  m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, m68k_op_divu_16_pi, 
+  m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, m68k_op_divu_16_pd, 
+  m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, m68k_op_divu_16_di, 
+  m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, m68k_op_divu_16_ix, 
+  m68k_op_divu_16_aw, m68k_op_divu_16_al, m68k_op_divu_16_pcdi, m68k_op_divu_16_pcix, m68k_op_divu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, m68k_op_sbcd_8_rr, 
+  m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_ax7, m68k_op_sbcd_8_mm_axy7, 
+  m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, m68k_op_or_8_re_ai, 
+  m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi, m68k_op_or_8_re_pi7, 
+  m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd, m68k_op_or_8_re_pd7, 
+  m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, m68k_op_or_8_re_di, 
+  m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, m68k_op_or_8_re_ix, 
+  m68k_op_or_8_re_aw, m68k_op_or_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, m68k_op_or_16_re_ai, 
+  m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, m68k_op_or_16_re_pi, 
+  m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, m68k_op_or_16_re_pd, 
+  m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, m68k_op_or_16_re_di, 
+  m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, m68k_op_or_16_re_ix, 
+  m68k_op_or_16_re_aw, m68k_op_or_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, m68k_op_or_32_re_ai, 
+  m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, m68k_op_or_32_re_pi, 
+  m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, m68k_op_or_32_re_pd, 
+  m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, m68k_op_or_32_re_di, 
+  m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, m68k_op_or_32_re_ix, 
+  m68k_op_or_32_re_aw, m68k_op_or_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, m68k_op_divs_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, m68k_op_divs_16_ai, 
+  m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, m68k_op_divs_16_pi, 
+  m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, m68k_op_divs_16_pd, 
+  m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, m68k_op_divs_16_di, 
+  m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, m68k_op_divs_16_ix, 
+  m68k_op_divs_16_aw, m68k_op_divs_16_al, m68k_op_divs_16_pcdi, m68k_op_divs_16_pcix, m68k_op_divs_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm, m68k_op_subx_8_mm_ay7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, m68k_op_sub_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, m68k_op_sub_8_er_ai, 
+  m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi, m68k_op_sub_8_er_pi7, 
+  m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd, m68k_op_sub_8_er_pd7, 
+  m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, m68k_op_sub_8_er_di, 
+  m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, m68k_op_sub_8_er_ix, 
+  m68k_op_sub_8_er_aw, m68k_op_sub_8_er_al, m68k_op_sub_8_er_pcdi, m68k_op_sub_8_er_pcix, m68k_op_sub_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, m68k_op_sub_16_er_d, 
+  m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, m68k_op_sub_16_er_a, 
+  m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, m68k_op_sub_16_er_ai, 
+  m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, m68k_op_sub_16_er_pi, 
+  m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, m68k_op_sub_16_er_pd, 
+  m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, m68k_op_sub_16_er_di, 
+  m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, m68k_op_sub_16_er_ix, 
+  m68k_op_sub_16_er_aw, m68k_op_sub_16_er_al, m68k_op_sub_16_er_pcdi, m68k_op_sub_16_er_pcix, m68k_op_sub_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, m68k_op_sub_32_er_d, 
+  m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, m68k_op_sub_32_er_a, 
+  m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, m68k_op_sub_32_er_ai, 
+  m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, m68k_op_sub_32_er_pi, 
+  m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, m68k_op_sub_32_er_pd, 
+  m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, m68k_op_sub_32_er_di, 
+  m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, m68k_op_sub_32_er_ix, 
+  m68k_op_sub_32_er_aw, m68k_op_sub_32_er_al, m68k_op_sub_32_er_pcdi, m68k_op_sub_32_er_pcix, m68k_op_sub_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, m68k_op_suba_16_d, 
+  m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, m68k_op_suba_16_a, 
+  m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, m68k_op_suba_16_ai, 
+  m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, m68k_op_suba_16_pi, 
+  m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, m68k_op_suba_16_pd, 
+  m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, m68k_op_suba_16_di, 
+  m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, m68k_op_suba_16_ix, 
+  m68k_op_suba_16_aw, m68k_op_suba_16_al, m68k_op_suba_16_pcdi, m68k_op_suba_16_pcix, m68k_op_suba_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, m68k_op_subx_8_rr, 
+  m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_ax7, m68k_op_subx_8_mm_axy7, 
+  m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, m68k_op_sub_8_re_ai, 
+  m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi, m68k_op_sub_8_re_pi7, 
+  m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd, m68k_op_sub_8_re_pd7, 
+  m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, m68k_op_sub_8_re_di, 
+  m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, m68k_op_sub_8_re_ix, 
+  m68k_op_sub_8_re_aw, m68k_op_sub_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, m68k_op_subx_16_rr, 
+  m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, m68k_op_subx_16_mm, 
+  m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, m68k_op_sub_16_re_ai, 
+  m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, m68k_op_sub_16_re_pi, 
+  m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, m68k_op_sub_16_re_pd, 
+  m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, m68k_op_sub_16_re_di, 
+  m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, m68k_op_sub_16_re_ix, 
+  m68k_op_sub_16_re_aw, m68k_op_sub_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, m68k_op_subx_32_rr, 
+  m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, m68k_op_subx_32_mm, 
+  m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, m68k_op_sub_32_re_ai, 
+  m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, m68k_op_sub_32_re_pi, 
+  m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, m68k_op_sub_32_re_pd, 
+  m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, m68k_op_sub_32_re_di, 
+  m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, m68k_op_sub_32_re_ix, 
+  m68k_op_sub_32_re_aw, m68k_op_sub_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, m68k_op_suba_32_d, 
+  m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, m68k_op_suba_32_a, 
+  m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, m68k_op_suba_32_ai, 
+  m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, m68k_op_suba_32_pi, 
+  m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, m68k_op_suba_32_pd, 
+  m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, m68k_op_suba_32_di, 
+  m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, m68k_op_suba_32_ix, 
+  m68k_op_suba_32_aw, m68k_op_suba_32_al, m68k_op_suba_32_pcdi, m68k_op_suba_32_pcix, m68k_op_suba_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, m68k_op_1010, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8, m68k_op_cmpm_8_ay7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, m68k_op_cmp_8_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, m68k_op_cmp_8_ai, 
+  m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi, m68k_op_cmp_8_pi7, 
+  m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd, m68k_op_cmp_8_pd7, 
+  m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, m68k_op_cmp_8_di, 
+  m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, m68k_op_cmp_8_ix, 
+  m68k_op_cmp_8_aw, m68k_op_cmp_8_al, m68k_op_cmp_8_pcdi, m68k_op_cmp_8_pcix, m68k_op_cmp_8_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, m68k_op_cmp_16_d, 
+  m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, m68k_op_cmp_16_a, 
+  m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, m68k_op_cmp_16_ai, 
+  m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, m68k_op_cmp_16_pi, 
+  m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, m68k_op_cmp_16_pd, 
+  m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, m68k_op_cmp_16_di, 
+  m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, m68k_op_cmp_16_ix, 
+  m68k_op_cmp_16_aw, m68k_op_cmp_16_al, m68k_op_cmp_16_pcdi, m68k_op_cmp_16_pcix, m68k_op_cmp_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, m68k_op_cmp_32_d, 
+  m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, m68k_op_cmp_32_a, 
+  m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, m68k_op_cmp_32_ai, 
+  m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, m68k_op_cmp_32_pi, 
+  m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, m68k_op_cmp_32_pd, 
+  m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, m68k_op_cmp_32_di, 
+  m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, m68k_op_cmp_32_ix, 
+  m68k_op_cmp_32_aw, m68k_op_cmp_32_al, m68k_op_cmp_32_pcdi, m68k_op_cmp_32_pcix, m68k_op_cmp_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, m68k_op_cmpa_16_d, 
+  m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, m68k_op_cmpa_16_a, 
+  m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, m68k_op_cmpa_16_ai, 
+  m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, m68k_op_cmpa_16_pi, 
+  m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, m68k_op_cmpa_16_pd, 
+  m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, m68k_op_cmpa_16_di, 
+  m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, m68k_op_cmpa_16_ix, 
+  m68k_op_cmpa_16_aw, m68k_op_cmpa_16_al, m68k_op_cmpa_16_pcdi, m68k_op_cmpa_16_pcix, m68k_op_cmpa_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, m68k_op_eor_8_d, 
+  m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_ax7, m68k_op_cmpm_8_axy7, 
+  m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, m68k_op_eor_8_ai, 
+  m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi, m68k_op_eor_8_pi7, 
+  m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd, m68k_op_eor_8_pd7, 
+  m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, m68k_op_eor_8_di, 
+  m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, m68k_op_eor_8_ix, 
+  m68k_op_eor_8_aw, m68k_op_eor_8_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, m68k_op_eor_16_d, 
+  m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, m68k_op_cmpm_16, 
+  m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, m68k_op_eor_16_ai, 
+  m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, m68k_op_eor_16_pi, 
+  m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, m68k_op_eor_16_pd, 
+  m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, m68k_op_eor_16_di, 
+  m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, m68k_op_eor_16_ix, 
+  m68k_op_eor_16_aw, m68k_op_eor_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, m68k_op_eor_32_d, 
+  m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, m68k_op_cmpm_32, 
+  m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, m68k_op_eor_32_ai, 
+  m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, m68k_op_eor_32_pi, 
+  m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, m68k_op_eor_32_pd, 
+  m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, m68k_op_eor_32_di, 
+  m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, m68k_op_eor_32_ix, 
+  m68k_op_eor_32_aw, m68k_op_eor_32_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, m68k_op_cmpa_32_d, 
+  m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, m68k_op_cmpa_32_a, 
+  m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, m68k_op_cmpa_32_ai, 
+  m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, m68k_op_cmpa_32_pi, 
+  m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, m68k_op_cmpa_32_pd, 
+  m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, m68k_op_cmpa_32_di, 
+  m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, m68k_op_cmpa_32_ix, 
+  m68k_op_cmpa_32_aw, m68k_op_cmpa_32_al, m68k_op_cmpa_32_pcdi, m68k_op_cmpa_32_pcix, m68k_op_cmpa_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm, m68k_op_abcd_8_mm_ay7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, m68k_op_and_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, m68k_op_and_8_er_ai, 
+  m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi, m68k_op_and_8_er_pi7, 
+  m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd, m68k_op_and_8_er_pd7, 
+  m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, m68k_op_and_8_er_di, 
+  m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, m68k_op_and_8_er_ix, 
+  m68k_op_and_8_er_aw, m68k_op_and_8_er_al, m68k_op_and_8_er_pcdi, m68k_op_and_8_er_pcix, m68k_op_and_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, m68k_op_and_16_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, m68k_op_and_16_er_ai, 
+  m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, m68k_op_and_16_er_pi, 
+  m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, m68k_op_and_16_er_pd, 
+  m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, m68k_op_and_16_er_di, 
+  m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, m68k_op_and_16_er_ix, 
+  m68k_op_and_16_er_aw, m68k_op_and_16_er_al, m68k_op_and_16_er_pcdi, m68k_op_and_16_er_pcix, m68k_op_and_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, m68k_op_and_32_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, m68k_op_and_32_er_ai, 
+  m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, m68k_op_and_32_er_pi, 
+  m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, m68k_op_and_32_er_pd, 
+  m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, m68k_op_and_32_er_di, 
+  m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, m68k_op_and_32_er_ix, 
+  m68k_op_and_32_er_aw, m68k_op_and_32_er_al, m68k_op_and_32_er_pcdi, m68k_op_and_32_er_pcix, m68k_op_and_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, m68k_op_mulu_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, m68k_op_mulu_16_ai, 
+  m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, m68k_op_mulu_16_pi, 
+  m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, m68k_op_mulu_16_pd, 
+  m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, m68k_op_mulu_16_di, 
+  m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, m68k_op_mulu_16_ix, 
+  m68k_op_mulu_16_aw, m68k_op_mulu_16_al, m68k_op_mulu_16_pcdi, m68k_op_mulu_16_pcix, m68k_op_mulu_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, m68k_op_abcd_8_rr, 
+  m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_ax7, m68k_op_abcd_8_mm_axy7, 
+  m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, m68k_op_and_8_re_ai, 
+  m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi, m68k_op_and_8_re_pi7, 
+  m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd, m68k_op_and_8_re_pd7, 
+  m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, m68k_op_and_8_re_di, 
+  m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, m68k_op_and_8_re_ix, 
+  m68k_op_and_8_re_aw, m68k_op_and_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, m68k_op_exg_32_dd, 
+  m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, m68k_op_exg_32_aa, 
+  m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, m68k_op_and_16_re_ai, 
+  m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, m68k_op_and_16_re_pi, 
+  m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, m68k_op_and_16_re_pd, 
+  m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, m68k_op_and_16_re_di, 
+  m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, m68k_op_and_16_re_ix, 
+  m68k_op_and_16_re_aw, m68k_op_and_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, m68k_op_exg_32_da, 
+  m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, m68k_op_and_32_re_ai, 
+  m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, m68k_op_and_32_re_pi, 
+  m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, m68k_op_and_32_re_pd, 
+  m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, m68k_op_and_32_re_di, 
+  m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, m68k_op_and_32_re_ix, 
+  m68k_op_and_32_re_aw, m68k_op_and_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, m68k_op_muls_16_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, m68k_op_muls_16_ai, 
+  m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, m68k_op_muls_16_pi, 
+  m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, m68k_op_muls_16_pd, 
+  m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, m68k_op_muls_16_di, 
+  m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, m68k_op_muls_16_ix, 
+  m68k_op_muls_16_aw, m68k_op_muls_16_al, m68k_op_muls_16_pcdi, m68k_op_muls_16_pcix, m68k_op_muls_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm, m68k_op_addx_8_mm_ay7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, m68k_op_add_8_er_d, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, m68k_op_add_8_er_ai, 
+  m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi, m68k_op_add_8_er_pi7, 
+  m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd, m68k_op_add_8_er_pd7, 
+  m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, m68k_op_add_8_er_di, 
+  m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, m68k_op_add_8_er_ix, 
+  m68k_op_add_8_er_aw, m68k_op_add_8_er_al, m68k_op_add_8_er_pcdi, m68k_op_add_8_er_pcix, m68k_op_add_8_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, m68k_op_add_16_er_d, 
+  m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, m68k_op_add_16_er_a, 
+  m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, m68k_op_add_16_er_ai, 
+  m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, m68k_op_add_16_er_pi, 
+  m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, m68k_op_add_16_er_pd, 
+  m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, m68k_op_add_16_er_di, 
+  m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, m68k_op_add_16_er_ix, 
+  m68k_op_add_16_er_aw, m68k_op_add_16_er_al, m68k_op_add_16_er_pcdi, m68k_op_add_16_er_pcix, m68k_op_add_16_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, m68k_op_add_32_er_d, 
+  m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, m68k_op_add_32_er_a, 
+  m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, m68k_op_add_32_er_ai, 
+  m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, m68k_op_add_32_er_pi, 
+  m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, m68k_op_add_32_er_pd, 
+  m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, m68k_op_add_32_er_di, 
+  m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, m68k_op_add_32_er_ix, 
+  m68k_op_add_32_er_aw, m68k_op_add_32_er_al, m68k_op_add_32_er_pcdi, m68k_op_add_32_er_pcix, m68k_op_add_32_er_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, m68k_op_adda_16_d, 
+  m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, m68k_op_adda_16_a, 
+  m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, m68k_op_adda_16_ai, 
+  m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, m68k_op_adda_16_pi, 
+  m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, m68k_op_adda_16_pd, 
+  m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, m68k_op_adda_16_di, 
+  m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, m68k_op_adda_16_ix, 
+  m68k_op_adda_16_aw, m68k_op_adda_16_al, m68k_op_adda_16_pcdi, m68k_op_adda_16_pcix, m68k_op_adda_16_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, m68k_op_addx_8_rr, 
+  m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_ax7, m68k_op_addx_8_mm_axy7, 
+  m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, m68k_op_add_8_re_ai, 
+  m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi, m68k_op_add_8_re_pi7, 
+  m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd, m68k_op_add_8_re_pd7, 
+  m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, m68k_op_add_8_re_di, 
+  m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, m68k_op_add_8_re_ix, 
+  m68k_op_add_8_re_aw, m68k_op_add_8_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, m68k_op_addx_16_rr, 
+  m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, m68k_op_addx_16_mm, 
+  m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, m68k_op_add_16_re_ai, 
+  m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, m68k_op_add_16_re_pi, 
+  m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, m68k_op_add_16_re_pd, 
+  m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, m68k_op_add_16_re_di, 
+  m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, m68k_op_add_16_re_ix, 
+  m68k_op_add_16_re_aw, m68k_op_add_16_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, m68k_op_addx_32_rr, 
+  m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, m68k_op_addx_32_mm, 
+  m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, m68k_op_add_32_re_ai, 
+  m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, m68k_op_add_32_re_pi, 
+  m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, m68k_op_add_32_re_pd, 
+  m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, m68k_op_add_32_re_di, 
+  m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, m68k_op_add_32_re_ix, 
+  m68k_op_add_32_re_aw, m68k_op_add_32_re_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, m68k_op_adda_32_d, 
+  m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, m68k_op_adda_32_a, 
+  m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, m68k_op_adda_32_ai, 
+  m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, m68k_op_adda_32_pi, 
+  m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, m68k_op_adda_32_pd, 
+  m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, m68k_op_adda_32_di, 
+  m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, m68k_op_adda_32_ix, 
+  m68k_op_adda_32_aw, m68k_op_adda_32_al, m68k_op_adda_32_pcdi, m68k_op_adda_32_pcix, m68k_op_adda_32_i, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, m68k_op_asr_16_ai, 
+  m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, m68k_op_asr_16_pi, 
+  m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, m68k_op_asr_16_pd, 
+  m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, m68k_op_asr_16_di, 
+  m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, m68k_op_asr_16_ix, 
+  m68k_op_asr_16_aw, m68k_op_asr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, m68k_op_asl_16_ai, 
+  m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, m68k_op_asl_16_pi, 
+  m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, m68k_op_asl_16_pd, 
+  m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, m68k_op_asl_16_di, 
+  m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, m68k_op_asl_16_ix, 
+  m68k_op_asl_16_aw, m68k_op_asl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, m68k_op_lsr_16_ai, 
+  m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, m68k_op_lsr_16_pi, 
+  m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, m68k_op_lsr_16_pd, 
+  m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, m68k_op_lsr_16_di, 
+  m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, m68k_op_lsr_16_ix, 
+  m68k_op_lsr_16_aw, m68k_op_lsr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, m68k_op_lsl_16_ai, 
+  m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, m68k_op_lsl_16_pi, 
+  m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, m68k_op_lsl_16_pd, 
+  m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, m68k_op_lsl_16_di, 
+  m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, m68k_op_lsl_16_ix, 
+  m68k_op_lsl_16_aw, m68k_op_lsl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, m68k_op_roxr_16_ai, 
+  m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, m68k_op_roxr_16_pi, 
+  m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, m68k_op_roxr_16_pd, 
+  m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, m68k_op_roxr_16_di, 
+  m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, m68k_op_roxr_16_ix, 
+  m68k_op_roxr_16_aw, m68k_op_roxr_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, m68k_op_roxl_16_ai, 
+  m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, m68k_op_roxl_16_pi, 
+  m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, m68k_op_roxl_16_pd, 
+  m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, m68k_op_roxl_16_di, 
+  m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, m68k_op_roxl_16_ix, 
+  m68k_op_roxl_16_aw, m68k_op_roxl_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, m68k_op_ror_16_ai, 
+  m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, m68k_op_ror_16_pi, 
+  m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, m68k_op_ror_16_pd, 
+  m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, m68k_op_ror_16_di, 
+  m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, m68k_op_ror_16_ix, 
+  m68k_op_ror_16_aw, m68k_op_ror_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, m68k_op_rol_16_ai, 
+  m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, m68k_op_rol_16_pi, 
+  m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, m68k_op_rol_16_pd, 
+  m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, m68k_op_rol_16_di, 
+  m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, m68k_op_rol_16_ix, 
+  m68k_op_rol_16_aw, m68k_op_rol_16_al, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, m68k_op_asr_8_s, 
+  m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, m68k_op_lsr_8_s, 
+  m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, m68k_op_roxr_8_s, 
+  m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, m68k_op_ror_8_s, 
+  m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, m68k_op_asr_8_r, 
+  m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, m68k_op_lsr_8_r, 
+  m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, m68k_op_roxr_8_r, 
+  m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, m68k_op_ror_8_r, 
+  m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, m68k_op_asr_16_s, 
+  m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, m68k_op_lsr_16_s, 
+  m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, m68k_op_roxr_16_s, 
+  m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, m68k_op_ror_16_s, 
+  m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, m68k_op_asr_16_r, 
+  m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, m68k_op_lsr_16_r, 
+  m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, m68k_op_roxr_16_r, 
+  m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, m68k_op_ror_16_r, 
+  m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, m68k_op_asr_32_s, 
+  m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, m68k_op_lsr_32_s, 
+  m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, m68k_op_roxr_32_s, 
+  m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, m68k_op_ror_32_s, 
+  m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, m68k_op_asr_32_r, 
+  m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, m68k_op_lsr_32_r, 
+  m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, m68k_op_roxr_32_r, 
+  m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, m68k_op_ror_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, m68k_op_asl_8_s, 
+  m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, m68k_op_lsl_8_s, 
+  m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, m68k_op_roxl_8_s, 
+  m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, m68k_op_rol_8_s, 
+  m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, m68k_op_asl_8_r, 
+  m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, m68k_op_lsl_8_r, 
+  m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, m68k_op_roxl_8_r, 
+  m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, m68k_op_rol_8_r, 
+  m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, m68k_op_asl_16_s, 
+  m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, m68k_op_lsl_16_s, 
+  m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, m68k_op_roxl_16_s, 
+  m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, m68k_op_rol_16_s, 
+  m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, m68k_op_asl_16_r, 
+  m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, m68k_op_lsl_16_r, 
+  m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, m68k_op_roxl_16_r, 
+  m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, m68k_op_rol_16_r, 
+  m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, m68k_op_asl_32_s, 
+  m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, m68k_op_lsl_32_s, 
+  m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, m68k_op_roxl_32_s, 
+  m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, m68k_op_rol_32_s, 
+  m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, m68k_op_asl_32_r, 
+  m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, m68k_op_lsl_32_r, 
+  m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, m68k_op_roxl_32_r, 
+  m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, m68k_op_rol_32_r, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, m68k_op_illegal, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+  m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, m68k_op_1111, 
+};
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kops.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kops.h
new file mode 100755
index 0000000..42f09be
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/m68kops.h
@@ -0,0 +1,25494 @@
+
+/* ======================================================================== */
+/* ============== CYCLE-ACCURATE DIV/MUL EXECUTION ======================== */
+/* ======================================================================== */
+
+INLINE void UseDivuCycles(uint32 dst, uint32 src)
+{
+  int i;
+
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* 16-bit divisor */
+  src <<= 16;
+
+  /* 16-bit dividend */
+  for (i=0; i<15; i++)
+  {
+    /* check if carry bit set  */
+    if ((sint32) dst < 0)
+    {
+      /* shift dividend and apply divisor */
+      dst <<= 1;
+      dst -= src;
+    }
+    else
+    {
+      /* shift dividend and add two cycles */
+      dst <<= 1;
+      mcycles += (2 * MUL);
+
+      if (dst >= src)
+      {
+        /* apply divisor and remove one cycle */
+        dst -= src;
+        mcycles -= 1 * MUL;
+      }
+    }
+  }
+
+  USE_CYCLES(mcycles << 1);
+}
+
+INLINE void UseDivsCycles(sint32 dst, sint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 6 * MUL;
+
+  /* negative dividend */
+  if (dst < 0) mcycles += 1 * MUL;
+
+  if ((abs(dst) >> 16) < abs(src))
+  {
+    int i;
+
+    /* absolute quotient */
+    uint32 quotient = abs(dst) / abs(src);
+
+    /* add default cycle time */
+    mcycles += (55 * MUL);
+
+    /* positive divisor */
+    if (src >= 0)
+    {
+      /* check dividend sign */
+      if (dst >= 0) mcycles -= 1 * MUL;
+      else mcycles += 1 * MUL;
+    }
+
+    /* check higher 15-bits of quotient */
+    for (i=0; i<15; i++)
+    {
+      quotient >>= 1;
+      if (!(quotient & 1)) mcycles += 1 * MUL;
+    }
+  }
+  else
+  {
+    /* absolute overflow */
+    mcycles += (2 * MUL);
+  }
+
+  USE_CYCLES(mcycles << 1);
+}
+
+INLINE void UseMuluCycles(uint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* count number of bits set to 1 */
+  while (src)
+  {
+    if (src & 1) mcycles += (2 * MUL);
+    src >>= 1;
+  }
+
+  /* 38 + 2*N */
+  USE_CYCLES(mcycles);
+}
+
+INLINE void UseMulsCycles(sint16 src)
+{
+  /* minimum cycle time */
+  uint mcycles = 38 * MUL;
+
+  /* detect 01 or 10 patterns */
+  sint32 tmp = src << 1;
+  tmp = (tmp ^ src) & 0xFFFF;
+
+  /* count number of bits set to 1 */
+  while (tmp)
+  {
+    if (tmp & 1) mcycles += (2 * MUL);
+    tmp >>= 1;
+  }
+
+  /* 38 + 2*N */
+  USE_CYCLES(mcycles);
+}
+
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+static void __inline m68k_op_1010(void)
+{
+  m68ki_exception_1010();
+}
+
+#ifdef TABLES_FULL
+
+static void __inline m68k_op_1111(void)
+{
+  m68ki_exception_1111();
+}
+#endif
+
+static void __inline m68k_op_abcd_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_abcd_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_abcd_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 9)
+    corf = 6;
+  res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+  FLAG_V = ~res; /* Undefined V behavior */
+
+  res += corf;
+  FLAG_X = FLAG_C = (res > 0x9f) << 8;
+  if(FLAG_C)
+    res -= 0xa0;
+
+  FLAG_V &= res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_add_8_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pi7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pd7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_16_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = AY;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_32_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_add_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_add_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_adda_16_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
+}
+
+
+static void __inline m68k_op_adda_16_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
+}
+
+
+static void __inline m68k_op_adda_16_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AW_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AL_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_16_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_I_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+static void __inline m68k_op_adda_32_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
+}
+
+
+static void __inline m68k_op_adda_32_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
+}
+
+
+static void __inline m68k_op_adda_32_ai(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_AI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pi(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_PI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pd(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_PD_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_di(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_DI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_ix(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AY_IX_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_aw(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AW_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_al(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_AL_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pcdi(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_PCDI_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_pcix(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_PCIX_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_adda_32_i(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(OPER_I_32() + *r_dst);
+}
+
+
+static void __inline m68k_op_addi_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_addi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_8_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pi7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_pd7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_8_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_16_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+static void __inline m68k_op_addq_16_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_16_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = *r_dst;
+  uint res = src + dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_addq_32_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+static void __inline m68k_op_addq_32_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addq_32_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst;
+
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_addx_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_addx_16_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_addx_32_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_addx_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_V = VFLAG_ADD_8(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_addx_16_mm(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint ea  = EA_AX_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_V = VFLAG_ADD_16(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_addx_32_mm(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint ea  = EA_AX_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = src + dst + XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_ADD_32(src, dst, res);
+  FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_8_er_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_ai(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pi7(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pd(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pd7(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_di(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_ix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_aw(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_al(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pcdi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_pcix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_er_i(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_ai(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pd(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_di(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_ix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_aw(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_al(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pcdi(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_pcix(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_16_er_i(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_d(void)
+{
+  FLAG_Z = DX &= DY;
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_ai(void)
+{
+  FLAG_Z = DX &= OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pi(void)
+{
+  FLAG_Z = DX &= OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pd(void)
+{
+  FLAG_Z = DX &= OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_di(void)
+{
+  FLAG_Z = DX &= OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_ix(void)
+{
+  FLAG_Z = DX &= OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_aw(void)
+{
+  FLAG_Z = DX &= OPER_AW_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_al(void)
+{
+  FLAG_Z = DX &= OPER_AL_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pcdi(void)
+{
+  FLAG_Z = DX &= OPER_PCDI_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_pcix(void)
+{
+  FLAG_Z = DX &= OPER_PCIX_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_32_er_i(void)
+{
+  FLAG_Z = DX &= OPER_I_32();
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_and_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = DX & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = DX & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_and_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_and_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+
+  FLAG_N = NFLAG_8(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = src & m68ki_read_8(ea);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_d(void)
+{
+  FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+
+  FLAG_N = NFLAG_16(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = src & m68ki_read_16(ea);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_d(void)
+{
+  FLAG_Z = DY &= (OPER_I_32());
+
+  FLAG_N = NFLAG_32(FLAG_Z);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_andi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src & m68ki_read_32(ea);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_andi_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
+}
+
+
+static void __inline m68k_op_andi_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() & src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_asr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_8(src))
+    res |= m68ki_shift_8_table[shift];
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_16(src))
+    res |= m68ki_shift_16_table[shift];
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  if(GET_MSB_32(src))
+    res |= m68ki_shift_32_table[shift];
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+static void __inline m68k_op_asr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 8)
+    {
+      if(GET_MSB_8(src))
+        res |= m68ki_shift_8_table[shift];
+
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+      FLAG_X = FLAG_C = src << (9-shift);
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_8(src))
+    {
+      *r_dst |= 0xff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 16)
+    {
+      if(GET_MSB_16(src))
+        res |= m68ki_shift_16_table[shift];
+
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_16(src))
+    {
+      *r_dst |= 0xffff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      if(GET_MSB_32(src))
+        res |= m68ki_shift_32_table[shift];
+
+      *r_dst = res;
+
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    if(GET_MSB_32(src))
+    {
+      *r_dst = 0xffffffff;
+      FLAG_C = CFLAG_SET;
+      FLAG_X = XFLAG_SET;
+      FLAG_N = NFLAG_SET;
+      FLAG_Z = ZFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  if(GET_MSB_16(src))
+    res |= 0x8000;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = FLAG_X = src << 8;
+}
+
+
+static void __inline m68k_op_asl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_X = FLAG_C = src << shift;
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  src &= m68ki_shift_8_table[shift + 1];
+  FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (8-shift);
+  src &= m68ki_shift_16_table[shift + 1];
+  FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+}
+
+
+static void __inline m68k_op_asl_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (24-shift);
+  src &= m68ki_shift_32_table[shift + 1];
+  FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+}
+
+
+static void __inline m68k_op_asl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_8_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_X = FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_16_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      src &= m68ki_shift_32_table[shift + 1];
+      FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = (!(src == 0))<<7;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_asl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_asl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  src &= 0xc000;
+  FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+static void __inline m68k_op_bhi_8(void)
+{
+  if(COND_HI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bls_8(void)
+{
+  if(COND_LS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcc_8(void)
+{
+  if(COND_CC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcs_8(void)
+{
+  if(COND_CS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bne_8(void)
+{
+  if(COND_NE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_beq_8(void)
+{
+  if(COND_EQ())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvc_8(void)
+{
+  if(COND_VC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvs_8(void)
+{
+  if(COND_VS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bpl_8(void)
+{
+  if(COND_PL())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bmi_8(void)
+{
+  if(COND_MI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bge_8(void)
+{
+  if(COND_GE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_blt_8(void)
+{
+  if(COND_LT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bgt_8(void)
+{
+  if(COND_GT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_ble_8(void)
+{
+  if(COND_LE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bhi_16(void)
+{
+  if(COND_HI())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bls_16(void)
+{
+  if(COND_LS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bcc_16(void)
+{
+  if(COND_CC())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bcs_16(void)
+{
+  if(COND_CS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bne_16(void)
+{
+  if(COND_NE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_beq_16(void)
+{
+  if(COND_EQ())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bvc_16(void)
+{
+  if(COND_VC())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bvs_16(void)
+{
+  if(COND_VS())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bpl_16(void)
+{
+  if(COND_PL())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bmi_16(void)
+{
+  if(COND_MI())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bge_16(void)
+{
+  if(COND_GE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_blt_16(void)
+{
+  if(COND_LT())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bgt_16(void)
+{
+  if(COND_GT())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_ble_16(void)
+{
+  if(COND_LE())
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+static void __inline m68k_op_bhi_32(void)
+{
+  if(COND_HI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bls_32(void)
+{
+  if(COND_LS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcc_32(void)
+{
+  if(COND_CC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bcs_32(void)
+{
+  if(COND_CS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bne_32(void)
+{
+  if(COND_NE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_beq_32(void)
+{
+  if(COND_EQ())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvc_32(void)
+{
+  if(COND_VC())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bvs_32(void)
+{
+  if(COND_VS())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bpl_32(void)
+{
+  if(COND_PL())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bmi_32(void)
+{
+  if(COND_MI())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bge_32(void)
+{
+  if(COND_GE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_blt_32(void)
+{
+  if(COND_LT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bgt_32(void)
+{
+  if(COND_GT())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_ble_32(void)
+{
+  if(COND_LE())
+  {
+    m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+    return;
+  }
+  USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+static void __inline m68k_op_bchg_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst ^= mask;
+}
+
+
+static void __inline m68k_op_bchg_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst ^= mask;
+}
+
+
+static void __inline m68k_op_bchg_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bchg_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src ^ mask);
+}
+
+
+static void __inline m68k_op_bclr_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst &= ~mask;
+}
+
+
+static void __inline m68k_op_bclr_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst &= ~mask;
+}
+
+
+static void __inline m68k_op_bclr_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bclr_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src & ~mask);
+}
+
+
+static void __inline m68k_op_bra_8(void)
+{
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bra_16(void)
+{
+  uint offset = OPER_I_16();
+  REG_PC -= 2;
+  m68ki_branch_16(offset);
+}
+
+
+static void __inline m68k_op_bra_32(void)
+{
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bset_32_r_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (DX & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst |= mask;
+}
+
+
+static void __inline m68k_op_bset_8_r_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_r_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint mask = 1 << (DX & 7);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_32_s_d(void)
+{
+  uint* r_dst = &DY;
+  uint mask = 1 << (OPER_I_8() & 0x1f);
+
+  FLAG_Z = *r_dst & mask;
+  *r_dst |= mask;
+}
+
+
+static void __inline m68k_op_bset_8_s_ai(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pi(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pi7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pd(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_pd7(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_di(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_ix(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_aw(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bset_8_s_al(void)
+{
+  uint mask = 1 << (OPER_I_8() & 7);
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+
+  FLAG_Z = src & mask;
+  m68ki_write_8(ea, src | mask);
+}
+
+
+static void __inline m68k_op_bsr_8(void)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_bsr_16(void)
+{
+  uint offset = OPER_I_16();
+  m68ki_push_32(REG_PC);
+  REG_PC -= 2;
+  m68ki_branch_16(offset);
+}
+
+
+static void __inline m68k_op_bsr_32(void)
+{
+  m68ki_push_32(REG_PC);
+  m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+static void __inline m68k_op_btst_32_r_d(void)
+{
+  FLAG_Z = DY & (1 << (DX & 0x1f));
+}
+
+
+static void __inline m68k_op_btst_8_r_ai(void)
+{
+  FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pi(void)
+{
+  FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pi7(void)
+{
+  FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pd(void)
+{
+  FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pd7(void)
+{
+  FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_di(void)
+{
+  FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_ix(void)
+{
+  FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_aw(void)
+{
+  FLAG_Z = OPER_AW_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_al(void)
+{
+  FLAG_Z = OPER_AL_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pcdi(void)
+{
+  FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_pcix(void)
+{
+  FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_8_r_i(void)
+{
+  FLAG_Z = OPER_I_8() & (1 << (DX & 7));
+}
+
+
+static void __inline m68k_op_btst_32_s_d(void)
+{
+  FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+}
+
+
+static void __inline m68k_op_btst_8_s_ai(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_AI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pi(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_PI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pi7(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_A7_PI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pd(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_PD_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pd7(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_A7_PD_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_di(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_DI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_ix(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AY_IX_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_aw(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AW_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_al(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_AL_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pcdi(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_PCDI_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_btst_8_s_pcix(void)
+{
+  uint bit = OPER_I_8() & 7;
+
+  FLAG_Z = OPER_PCIX_8() & (1 << bit);
+}
+
+
+static void __inline m68k_op_chk_16_d(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(DY);
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_ai(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_AI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pi(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_PI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pd(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_PD_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_di(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_DI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_ix(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AY_IX_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_aw(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AW_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_al(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_AL_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pcdi(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_PCDI_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_pcix(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_PCIX_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_chk_16_i(void)
+{
+  sint src = MAKE_INT_16(DX);
+  sint bound = MAKE_INT_16(OPER_I_16());
+
+  FLAG_Z = ZFLAG_16(src); /* Undocumented */
+  FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+  FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+  if(src >= 0 && src <= bound)
+  {
+    return;
+  }
+  FLAG_N = (src < 0)<<7;
+  m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+static void __inline m68k_op_clr_8_d(void)
+{
+  DY &= 0xffffff00;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_d(void)
+{
+  DY &= 0xffff0000;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_ai(void)
+{
+  m68ki_write_16(EA_AY_AI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_pi(void)
+{
+  m68ki_write_16(EA_AY_PI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_pd(void)
+{
+  m68ki_write_16(EA_AY_PD_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_di(void)
+{
+  m68ki_write_16(EA_AY_DI_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_ix(void)
+{
+  m68ki_write_16(EA_AY_IX_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_aw(void)
+{
+  m68ki_write_16(EA_AW_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_16_al(void)
+{
+  m68ki_write_16(EA_AL_16(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_d(void)
+{
+  DY = 0;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_ai(void)
+{
+  m68ki_write_32(EA_AY_AI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_pi(void)
+{
+  m68ki_write_32(EA_AY_PI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_pd(void)
+{
+  m68ki_write_32(EA_AY_PD_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_di(void)
+{
+  m68ki_write_32(EA_AY_DI_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_ix(void)
+{
+  m68ki_write_32(EA_AY_IX_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_aw(void)
+{
+  m68ki_write_32(EA_AW_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_clr_32_al(void)
+{
+  m68ki_write_32(EA_AL_32(), 0);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_Z = ZFLAG_SET;
+}
+
+
+static void __inline m68k_op_cmp_8_d(void)
+{
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_ai(void)
+{
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pi(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pi7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pd(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pd7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_di(void)
+{
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_ix(void)
+{
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_aw(void)
+{
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_al(void)
+{
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pcdi(void)
+{
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_pcix(void)
+{
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_8_i(void)
+{
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmp_16_d(void)
+{
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_a(void)
+{
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_ai(void)
+{
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pi(void)
+{
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pd(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_di(void)
+{
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_ix(void)
+{
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_aw(void)
+{
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_al(void)
+{
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pcdi(void)
+{
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_pcix(void)
+{
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_16_i(void)
+{
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(DX);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmp_32_d(void)
+{
+  uint src = DY;
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_a(void)
+{
+  uint src = AY;
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_ai(void)
+{
+  uint src = OPER_AY_AI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pi(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pd(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_di(void)
+{
+  uint src = OPER_AY_DI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_ix(void)
+{
+  uint src = OPER_AY_IX_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_aw(void)
+{
+  uint src = OPER_AW_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_al(void)
+{
+  uint src = OPER_AL_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pcdi(void)
+{
+  uint src = OPER_PCDI_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_pcix(void)
+{
+  uint src = OPER_PCIX_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmp_32_i(void)
+{
+  uint src = OPER_I_32();
+  uint dst = DX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_d(void)
+{
+  uint src = MAKE_INT_16(DY);
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_a(void)
+{
+  uint src = MAKE_INT_16(AY);
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_ai(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pi(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pd(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_di(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_ix(void)
+{
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_aw(void)
+{
+  uint src = MAKE_INT_16(OPER_AW_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_al(void)
+{
+  uint src = MAKE_INT_16(OPER_AL_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pcdi(void)
+{
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_pcix(void)
+{
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_16_i(void)
+{
+  uint src = MAKE_INT_16(OPER_I_16());
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_d(void)
+{
+  uint src = DY;
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_a(void)
+{
+  uint src = AY;
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_ai(void)
+{
+  uint src = OPER_AY_AI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pi(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pd(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_di(void)
+{
+  uint src = OPER_AY_DI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_ix(void)
+{
+  uint src = OPER_AY_IX_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_aw(void)
+{
+  uint src = OPER_AW_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_al(void)
+{
+  uint src = OPER_AL_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pcdi(void)
+{
+  uint src = OPER_PCDI_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_pcix(void)
+{
+  uint src = OPER_PCIX_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpa_32_i(void)
+{
+  uint src = OPER_I_32();
+  uint dst = AX;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_8_d(void)
+{
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(DY);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_AI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_PD_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_A7_PD_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_DI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AY_IX_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AW_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint dst = OPER_AL_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_d(void)
+{
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(DY);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_AI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_PI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_PD_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_DI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AY_IX_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AW_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint dst = OPER_AL_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpi_32_d(void)
+{
+  uint src = OPER_I_32();
+  uint dst = DY;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_AI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_PI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_PD_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_DI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AY_IX_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AW_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint dst = OPER_AL_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_cmpm_8_ax7(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8_ay7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = OPER_AX_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8_axy7(void)
+{
+  uint src = OPER_A7_PI_8();
+  uint dst = OPER_A7_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_8(void)
+{
+  uint src = OPER_AY_PI_8();
+  uint dst = OPER_AX_PI_8();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_C = CFLAG_8(res);
+}
+
+
+static void __inline m68k_op_cmpm_16(void)
+{
+  uint src = OPER_AY_PI_16();
+  uint dst = OPER_AX_PI_16();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_C = CFLAG_16(res);
+}
+
+
+static void __inline m68k_op_cmpm_32(void)
+{
+  uint src = OPER_AY_PI_32();
+  uint dst = OPER_AX_PI_32();
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+static void __inline m68k_op_dbt_16(void)
+{
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbf_16(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  if(res != 0xffff)
+  {
+    uint offset = OPER_I_16();
+    REG_PC -= 2;
+    m68ki_branch_16(offset);
+    USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+    /* reset idle loop detection */
+    m68ki_cpu.poll.detected = 0;
+    return;
+  }
+  REG_PC += 2;
+  USE_CYCLES(CYC_DBCC_F_EXP);
+}
+
+
+static void __inline m68k_op_dbhi_16(void)
+{
+  if(COND_NOT_HI())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbls_16(void)
+{
+  if(COND_NOT_LS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbcc_16(void)
+{
+  if(COND_NOT_CC())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbcs_16(void)
+{
+  if(COND_NOT_CS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbne_16(void)
+{
+  if(COND_NOT_NE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbeq_16(void)
+{
+  if(COND_NOT_EQ())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbvc_16(void)
+{
+  if(COND_NOT_VC())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbvs_16(void)
+{
+  if(COND_NOT_VS())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbpl_16(void)
+{
+  if(COND_NOT_PL())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbmi_16(void)
+{
+  if(COND_NOT_MI())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbge_16(void)
+{
+  if(COND_NOT_GE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dblt_16(void)
+{
+  if(COND_NOT_LT())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dbgt_16(void)
+{
+  if(COND_NOT_GT())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_dble_16(void)
+{
+  if(COND_NOT_LE())
+  {
+    uint* r_dst = &DY;
+    uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    if(res != 0xffff)
+    {
+      uint offset = OPER_I_16();
+      REG_PC -= 2;
+      m68ki_branch_16(offset);
+      USE_CYCLES(CYC_DBCC_F_NOEXP);
+
+      /* reset idle loop detection */
+      m68ki_cpu.poll.detected = 0;
+      return;
+    }
+    REG_PC += 2;
+    USE_CYCLES(CYC_DBCC_F_EXP);
+    return;
+  }
+  REG_PC += 2;
+}
+
+
+static void __inline m68k_op_divs_16_d(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(DY);
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_ai(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_AI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pd(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PD_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_di(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_DI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_ix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_IX_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_aw(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AW_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_al(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AL_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCDI_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCIX_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divs_16_i(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_I_16());
+  sint quotient;
+  sint remainder;
+
+  if(src != 0)
+  {
+    UseDivsCycles(*r_dst,src);
+
+    if((uint32)*r_dst == 0x80000000 && src == -1)
+    {
+      FLAG_Z = 0;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = 0;
+      return;
+    }
+
+    quotient = MAKE_INT_32(*r_dst) / src;
+    remainder = MAKE_INT_32(*r_dst) % src;
+
+    if(quotient == MAKE_INT_16(quotient))
+    {
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_divu_16_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+
+  if(src != 0)
+  {
+    uint quotient = *r_dst / src;
+    uint remainder = *r_dst % src;
+
+    if(quotient < 0x10000)
+    {
+      UseDivuCycles(*r_dst,src);
+      FLAG_Z = quotient;
+      FLAG_N = NFLAG_16(quotient);
+      FLAG_V = VFLAG_CLEAR;
+      FLAG_C = CFLAG_CLEAR;
+      *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+      return;
+    }
+    USE_CYCLES(MUL * 10);
+    FLAG_V = VFLAG_SET;
+    FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
+    FLAG_C = CFLAG_CLEAR;
+    return;
+  }
+  FLAG_C = CFLAG_CLEAR;
+  m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+static void __inline m68k_op_eor_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_d(void)
+{
+  uint res = DY ^= DX;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eor_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = src ^ m68ki_read_8(ea);
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = src ^ m68ki_read_16(ea);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_d(void)
+{
+  uint res = DY ^= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src ^ m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_eori_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
+}
+
+
+static void __inline m68k_op_eori_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() ^ src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_exg_32_dd(void)
+{
+  uint* reg_a = &DX;
+  uint* reg_b = &DY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_exg_32_aa(void)
+{
+  uint* reg_a = &AX;
+  uint* reg_b = &AY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_exg_32_da(void)
+{
+  uint* reg_a = &DX;
+  uint* reg_b = &AY;
+  uint tmp = *reg_a;
+  *reg_a = *reg_b;
+  *reg_b = tmp;
+}
+
+
+static void __inline m68k_op_ext_16(void)
+{
+  uint* r_dst = &DY;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
+
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ext_32(void)
+{
+  uint* r_dst = &DY;
+
+  *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
+
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_illegal(void)
+{
+  m68ki_exception_illegal();
+}
+
+
+static void __inline m68k_op_jmp_32_ai(void)
+{
+  m68ki_jump(EA_AY_AI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_di(void)
+{
+  m68ki_jump(EA_AY_DI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_ix(void)
+{
+  m68ki_jump(EA_AY_IX_32());
+}
+
+
+static void __inline m68k_op_jmp_32_aw(void)
+{
+  m68ki_jump(EA_AW_32());
+}
+
+
+static void __inline m68k_op_jmp_32_al(void)
+{
+  m68ki_jump(EA_AL_32());
+}
+
+
+static void __inline m68k_op_jmp_32_pcdi(void)
+{
+  m68ki_jump(EA_PCDI_32());
+}
+
+
+static void __inline m68k_op_jmp_32_pcix(void)
+{
+  m68ki_jump(EA_PCIX_32());
+}
+
+
+static void __inline m68k_op_jsr_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_al(void)
+{
+  uint ea = EA_AL_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_pcdi(void)
+{
+  uint ea = EA_PCDI_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_jsr_32_pcix(void)
+{
+  uint ea = EA_PCIX_32();
+  m68ki_push_32(REG_PC);
+  m68ki_jump(ea);
+}
+
+
+static void __inline m68k_op_lea_32_ai(void)
+{
+  AX = EA_AY_AI_32();
+}
+
+
+static void __inline m68k_op_lea_32_di(void)
+{
+  AX = EA_AY_DI_32();
+}
+
+
+static void __inline m68k_op_lea_32_ix(void)
+{
+  AX = EA_AY_IX_32();
+}
+
+
+static void __inline m68k_op_lea_32_aw(void)
+{
+  AX = EA_AW_32();
+}
+
+
+static void __inline m68k_op_lea_32_al(void)
+{
+  AX = EA_AL_32();
+}
+
+
+static void __inline m68k_op_lea_32_pcdi(void)
+{
+  AX = EA_PCDI_32();
+}
+
+
+static void __inline m68k_op_lea_32_pcix(void)
+{
+  AX = EA_PCIX_32();
+}
+
+
+static void __inline m68k_op_link_16_a7(void)
+{
+  REG_A[7] -= 4;
+  m68ki_write_32(REG_A[7], REG_A[7]);
+  REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+static void __inline m68k_op_link_16(void)
+{
+  uint* r_dst = &AY;
+
+  m68ki_push_32(*r_dst);
+  *r_dst = REG_A[7];
+  REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+static void __inline m68k_op_lsr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << (9-shift);
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = src >> shift;
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+      FLAG_N = NFLAG_CLEAR;
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = src >> 1;
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_CLEAR;
+  FLAG_Z = res;
+  FLAG_C = FLAG_X = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src << shift;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (8-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> (24-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = MASK_OUT_ABOVE_8(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 8)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_X = FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffffff00;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift <= 16)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_X = FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst &= 0xffff0000;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint shift = DX & 0x3f;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32(src << shift);
+
+  if(shift != 0)
+  {
+    USE_CYCLES(shift * CYC_SHIFT);
+
+    if(shift < 32)
+    {
+      *r_dst = res;
+      FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+      FLAG_N = NFLAG_32(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+
+    *r_dst = 0;
+    FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+    FLAG_N = NFLAG_CLEAR;
+    FLAG_Z = ZFLAG_SET;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_lsl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(src << 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_X = FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_al(void)
+{
+  uint res = OPER_AL_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_d_i(void)
+{
+  uint res = OPER_I_8();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_8_ai_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ai_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi7_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pi_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd7_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_pd_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_di_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_ix_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AX_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_aw_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_di(void)
+{
+  uint res = OPER_AY_DI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_aw(void)
+{
+  uint res = OPER_AW_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_al(void)
+{
+  uint res = OPER_AL_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pcdi(void)
+{
+  uint res = OPER_PCDI_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_pcix(void)
+{
+  uint res = OPER_PCIX_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_8_al_i(void)
+{
+  uint res = OPER_I_8();
+  uint ea = EA_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_d_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_al(void)
+{
+  uint res = OPER_AL_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_d_i(void)
+{
+  uint res = OPER_I_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_16_ai_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ai_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pi_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_pd_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_di_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_ix_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AX_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_aw_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_a(void)
+{
+  uint res = MASK_OUT_ABOVE_16(AY);
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_di(void)
+{
+  uint res = OPER_AY_DI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_aw(void)
+{
+  uint res = OPER_AW_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_al(void)
+{
+  uint res = OPER_AL_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pcdi(void)
+{
+  uint res = OPER_PCDI_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_pcix(void)
+{
+  uint res = OPER_PCIX_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_16_al_i(void)
+{
+  uint res = OPER_I_16();
+  uint ea = EA_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_d_d(void)
+{
+  uint res = DY;
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_a(void)
+{
+  uint res = AY;
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_al(void)
+{
+  uint res = OPER_AL_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_d_i(void)
+{
+  uint res = OPER_I_32();
+  uint* r_dst = &DX;
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_move_32_ai_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ai_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pi_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_pd_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_pd_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_16(ea+2, res & 0xFFFF );
+  m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+}
+
+
+static void __inline m68k_op_move_32_di_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_di_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_ix_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AX_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_aw_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_d(void)
+{
+  uint res = DY;
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_a(void)
+{
+  uint res = AY;
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_di(void)
+{
+  uint res = OPER_AY_DI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_aw(void)
+{
+  uint res = OPER_AW_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_al(void)
+{
+  uint res = OPER_AL_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pcdi(void)
+{
+  uint res = OPER_PCDI_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_pcix(void)
+{
+  uint res = OPER_PCIX_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_move_32_al_i(void)
+{
+  uint res = OPER_I_32();
+  uint ea = EA_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_movea_16_d(void)
+{
+  AX = MAKE_INT_16(DY);
+}
+
+
+static void __inline m68k_op_movea_16_a(void)
+{
+  AX = MAKE_INT_16(AY);
+}
+
+
+static void __inline m68k_op_movea_16_ai(void)
+{
+  AX = MAKE_INT_16(OPER_AY_AI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pi(void)
+{
+  AX = MAKE_INT_16(OPER_AY_PI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pd(void)
+{
+  AX = MAKE_INT_16(OPER_AY_PD_16());
+}
+
+
+static void __inline m68k_op_movea_16_di(void)
+{
+  AX = MAKE_INT_16(OPER_AY_DI_16());
+}
+
+
+static void __inline m68k_op_movea_16_ix(void)
+{
+  AX = MAKE_INT_16(OPER_AY_IX_16());
+}
+
+
+static void __inline m68k_op_movea_16_aw(void)
+{
+  AX = MAKE_INT_16(OPER_AW_16());
+}
+
+
+static void __inline m68k_op_movea_16_al(void)
+{
+  AX = MAKE_INT_16(OPER_AL_16());
+}
+
+
+static void __inline m68k_op_movea_16_pcdi(void)
+{
+  AX = MAKE_INT_16(OPER_PCDI_16());
+}
+
+
+static void __inline m68k_op_movea_16_pcix(void)
+{
+  AX = MAKE_INT_16(OPER_PCIX_16());
+}
+
+
+static void __inline m68k_op_movea_16_i(void)
+{
+  AX = MAKE_INT_16(OPER_I_16());
+}
+
+
+static void __inline m68k_op_movea_32_d(void)
+{
+  AX = DY;
+}
+
+
+static void __inline m68k_op_movea_32_a(void)
+{
+  AX = AY;
+}
+
+
+static void __inline m68k_op_movea_32_ai(void)
+{
+  AX = OPER_AY_AI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pi(void)
+{
+  AX = OPER_AY_PI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pd(void)
+{
+  AX = OPER_AY_PD_32();
+}
+
+
+static void __inline m68k_op_movea_32_di(void)
+{
+  AX = OPER_AY_DI_32();
+}
+
+
+static void __inline m68k_op_movea_32_ix(void)
+{
+  AX = OPER_AY_IX_32();
+}
+
+
+static void __inline m68k_op_movea_32_aw(void)
+{
+  AX = OPER_AW_32();
+}
+
+
+static void __inline m68k_op_movea_32_al(void)
+{
+  AX = OPER_AL_32();
+}
+
+
+static void __inline m68k_op_movea_32_pcdi(void)
+{
+  AX = OPER_PCDI_32();
+}
+
+
+static void __inline m68k_op_movea_32_pcix(void)
+{
+  AX = OPER_PCIX_32();
+}
+
+
+static void __inline m68k_op_movea_32_i(void)
+{
+  AX = OPER_I_32();
+}
+
+static void __inline m68k_op_move_16_toc_d(void)
+{
+  m68ki_set_ccr(DY);
+}
+
+
+static void __inline m68k_op_move_16_toc_ai(void)
+{
+  m68ki_set_ccr(OPER_AY_AI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pi(void)
+{
+  m68ki_set_ccr(OPER_AY_PI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pd(void)
+{
+  m68ki_set_ccr(OPER_AY_PD_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_di(void)
+{
+  m68ki_set_ccr(OPER_AY_DI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_ix(void)
+{
+  m68ki_set_ccr(OPER_AY_IX_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_aw(void)
+{
+  m68ki_set_ccr(OPER_AW_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_al(void)
+{
+  m68ki_set_ccr(OPER_AL_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pcdi(void)
+{
+  m68ki_set_ccr(OPER_PCDI_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_pcix(void)
+{
+  m68ki_set_ccr(OPER_PCIX_16());
+}
+
+
+static void __inline m68k_op_move_16_toc_i(void)
+{
+  m68ki_set_ccr(OPER_I_16());
+}
+
+
+static void __inline m68k_op_move_16_frs_d(void)
+{
+  DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
+}
+
+
+static void __inline m68k_op_move_16_frs_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_aw(void)
+{
+  uint ea = EA_AW_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_frs_al(void)
+{
+  uint ea = EA_AL_16();
+  m68ki_write_16(ea, m68ki_get_sr());
+}
+
+
+static void __inline m68k_op_move_16_tos_d(void)
+{
+  if(FLAG_S)
+  {
+    m68ki_set_sr(DY);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_ai(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_AI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pi(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_PI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pd(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_PD_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_di(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_DI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_ix(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AY_IX_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_aw(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AW_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_al(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_AL_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pcdi(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_PCDI_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_pcix(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_PCIX_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_16_tos_i(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_I_16();
+    m68ki_set_sr(new_sr);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_32_fru(void)
+{
+  if(FLAG_S)
+  {
+    AY = REG_USP;
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_move_32_tou(void)
+{
+  if(FLAG_S)
+  {
+    REG_USP = AY;
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_movem_16_re_pd(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      ea -= 2;
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_re_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_32_re_pd(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      ea -= 4;
+      m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
+      m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_re_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      m68ki_write_32(ea, REG_DA[i]);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_16_er_pi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_pcdi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCDI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_pcix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCIX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_16_er_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+      ea += 2;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_W);
+}
+
+
+static void __inline m68k_op_movem_32_er_pi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = AY;
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+  AY = ea;
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_pcdi(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCDI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_pcrel_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_pcix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_PCIX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_pcrel_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_ai(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_AI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_di(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_DI_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_ix(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AY_IX_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_aw(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AW_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movem_32_er_al(void)
+{
+  uint i = 0;
+  uint register_list = OPER_I_16();
+  uint ea = EA_AL_32();
+  uint count = 0;
+
+  for(; i < 16; i++)
+    if(register_list & (1 << i))
+    {
+      REG_DA[i] = m68ki_read_32(ea);
+      ea += 4;
+      count++;
+    }
+
+  USE_CYCLES(count * CYC_MOVEM_L);
+}
+
+
+static void __inline m68k_op_movep_16_re(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = DX;
+
+  m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+static void __inline m68k_op_movep_32_re(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+
+  m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
+  m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+static void __inline m68k_op_movep_16_er(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint* r_dst = &DX;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
+}
+
+
+static void __inline m68k_op_movep_32_er(void)
+{
+  uint ea = EA_AY_DI_32();
+
+  DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
+    + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
+}
+
+
+static void __inline m68k_op_moveq_32(void)
+{
+  uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_d(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(DY);
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_ai(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_AI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pd(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_PD_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_di(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_DI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_ix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AY_IX_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_aw(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AW_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_al(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_AL_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCDI_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_PCIX_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_muls_16_i(void)
+{
+  uint* r_dst = &DX;
+  sint src = MAKE_INT_16(OPER_I_16());
+  uint res = MASK_OUT_ABOVE_32( src * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+  UseMulsCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_mulu_16_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint res = src * MASK_OUT_ABOVE_16(*r_dst);
+
+  UseMuluCycles(src);
+
+  *r_dst = res;
+
+  FLAG_Z = res;
+  FLAG_N = NFLAG_32(res);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_nbcd_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_nbcd_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = -dst - XFLAG_AS_1();
+
+  if(res)
+  {
+    FLAG_V = res; /* Undefined V behavior */
+
+    if(((res|dst) & 0x0f) == 0x0)
+      res = (res & 0xf0) + 6;
+
+    res = MASK_OUT_ABOVE_8(res+0x9a);
+
+    FLAG_V &= ~res; /* Undefined V behavior part II */
+
+    m68ki_write_8(ea, res);
+
+    FLAG_Z |= res;
+    FLAG_C = CFLAG_SET;
+    FLAG_X = XFLAG_SET;
+    FLAG_N = NFLAG_8(res);  /* Undefined N behavior */
+  }
+  else
+  {
+    FLAG_V = VFLAG_CLEAR;
+    FLAG_C = CFLAG_CLEAR;
+    FLAG_X = XFLAG_CLEAR;
+    FLAG_N = NFLAG_CLEAR;
+  }
+}
+
+
+static void __inline m68k_op_neg_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = *r_dst & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_C = FLAG_X = CFLAG_8(res);
+  FLAG_V = src & res;
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (*r_dst & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_C = FLAG_X = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - *r_dst;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
+  FLAG_V = (*r_dst & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_neg_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_neg_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_negx_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = *r_dst & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_negx_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = m68ki_read_8(ea);
+  uint res = 0 - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = src & res;
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (*r_dst & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_negx_16_ai(void)
+{
+  uint ea  = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_pi(void)
+{
+  uint ea  = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_pd(void)
+{
+  uint ea  = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_di(void)
+{
+  uint ea  = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_ix(void)
+{
+  uint ea  = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_aw(void)
+{
+  uint ea  = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_16_al(void)
+{
+  uint ea  = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = (src & res)>>8;
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
+  FLAG_V = (*r_dst & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_negx_32_ai(void)
+{
+  uint ea  = EA_AY_AI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_pi(void)
+{
+  uint ea  = EA_AY_PI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_pd(void)
+{
+  uint ea  = EA_AY_PD_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_di(void)
+{
+  uint ea  = EA_AY_DI_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_ix(void)
+{
+  uint ea  = EA_AY_IX_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_aw(void)
+{
+  uint ea  = EA_AW_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_negx_32_al(void)
+{
+  uint ea  = EA_AL_32();
+  uint src = m68ki_read_32(ea);
+  uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+  FLAG_V = (src & res)>>24;
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_nop(void)
+{
+}
+
+
+static void __inline m68k_op_not_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_8(~*r_dst);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = MASK_OUT_ABOVE_16(~*r_dst);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_not_32_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_ai(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pi(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pi7(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pd(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pd7(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_di(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_ix(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_aw(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_al(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pcdi(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_pcix(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_er_i(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_ai(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pi(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pd(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_di(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_ix(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_aw(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_al(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pcdi(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_pcix(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_er_i(void)
+{
+  uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16()));
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_d(void)
+{
+  uint res = DX |= DY;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_ai(void)
+{
+  uint res = DX |= OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pi(void)
+{
+  uint res = DX |= OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pd(void)
+{
+  uint res = DX |= OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_di(void)
+{
+  uint res = DX |= OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_ix(void)
+{
+  uint res = DX |= OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_aw(void)
+{
+  uint res = DX |= OPER_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_al(void)
+{
+  uint res = DX |= OPER_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pcdi(void)
+{
+  uint res = DX |= OPER_PCDI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_pcix(void)
+{
+  uint res = DX |= OPER_PCIX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_er_i(void)
+{
+  uint res = DX |= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_or_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint res = DX | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+  m68ki_write_8(ea, res);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_d(void)
+{
+  uint res = DY |= OPER_I_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint res = src | m68ki_read_32(ea);
+
+  m68ki_write_32(ea, res);
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ori_16_toc(void)
+{
+  m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
+}
+
+
+static void __inline m68k_op_ori_16_tos(void)
+{
+  if(FLAG_S)
+  {
+    uint src = OPER_I_16();
+    m68ki_set_sr(m68ki_get_sr() | src);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_pea_32_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_di(void)
+{
+  uint ea = EA_AY_DI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_aw(void)
+{
+  uint ea = EA_AW_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_al(void)
+{
+  uint ea = EA_AL_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_pcdi(void)
+{
+  uint ea = EA_PCDI_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_pea_32_pcix(void)
+{
+  uint ea = EA_PCIX_32();
+
+  m68ki_push_32(ea);
+}
+
+
+static void __inline m68k_op_reset(void)
+{
+  if(FLAG_S)
+  {
+    m68ki_output_reset()       /* auto-disable (see m68kcpu.h) */
+    USE_CYCLES(CYC_RESET);
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_ror_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_8(src, shift);
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-orig_shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_16(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src = *r_dst;
+  uint res = ROR_32(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = src << (9-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_8(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_C = src << (8-((shift-1)&7));
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 15;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_16(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_C = (src >> ((shift - 1) & 15)) << 8;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 31;
+  uint64 src = *r_dst;
+  uint res = ROR_32(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = res;
+    FLAG_C = (src >> ((shift - 1) & 31)) << 8;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_ror_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_16(src, 1);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src << 8;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_8(src, shift);
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_C = src << orig_shift;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROL_16(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> (8-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_32_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src = *r_dst;
+  uint res = ROL_32(src, shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_C = src >> (24-shift);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 7;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_8(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    if(shift != 0)
+    {
+      *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+      FLAG_C = src << shift;
+      FLAG_N = NFLAG_8(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+    FLAG_C = (src & 1)<<8;
+    FLAG_N = NFLAG_8(src);
+    FLAG_Z = src;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_8(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 15;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    if(shift != 0)
+    {
+      *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+      FLAG_C = (src << shift) >> 8;
+      FLAG_N = NFLAG_16(res);
+      FLAG_Z = res;
+      FLAG_V = VFLAG_CLEAR;
+      return;
+    }
+    FLAG_C = (src & 1)<<8;
+    FLAG_N = NFLAG_16(src);
+    FLAG_Z = src;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_16(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_32_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift & 31;
+  uint64 src = *r_dst;
+  uint res = ROL_32(src, shift);
+
+  if(orig_shift != 0)
+  {
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    *r_dst = res;
+
+    FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_N = NFLAG_32(src);
+  FLAG_Z = src;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rol_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_C = src >> 7;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res;
+  res = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src   = *r_dst;
+  uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  res = ROR_33_64(res, shift);
+
+  FLAG_C = FLAG_X = res >> 24;
+  res = MASK_OUT_ABOVE_32(res);
+
+  *r_dst =  res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+  uint new_x_flag = src & (1 << (shift - 1));
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxr_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 9;
+    uint src   = MASK_OUT_ABOVE_8(*r_dst);
+    uint res   = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res;
+    res = MASK_OUT_ABOVE_8(res);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 17;
+    uint src   = MASK_OUT_ABOVE_16(*r_dst);
+    uint res   = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 8;
+    res = MASK_OUT_ABOVE_16(res);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint   shift = orig_shift % 33;
+    uint64 src   = *r_dst;
+    uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+    res = ROR_33_64(res, shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 24;
+    res = MASK_OUT_ABOVE_32(res);
+
+    *r_dst = res;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift % 33;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+  uint new_x_flag = src & (1 << (shift - 1));
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  if(shift != 0)
+  {
+    *r_dst = res;
+    FLAG_X = (new_x_flag != 0)<<8;
+  }
+  else
+    res = src;
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxr_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxr_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_8_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res;
+  res = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_s(void)
+{
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint64 src   = *r_dst;
+  uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  res = ROL_33_64(res, shift);
+
+  FLAG_C = FLAG_X = res >> 24;
+  res = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = res;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+  uint new_x_flag = src & (1 << (32 - shift));
+
+  if(shift != 0)
+    USE_CYCLES(shift * CYC_SHIFT);
+
+  *r_dst = res;
+
+  FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxl_8_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 9;
+    uint src   = MASK_OUT_ABOVE_8(*r_dst);
+    uint res   = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res;
+    res = MASK_OUT_ABOVE_8(res);
+
+    *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+    FLAG_N = NFLAG_8(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_r(void)
+{
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint shift = orig_shift % 17;
+    uint src   = MASK_OUT_ABOVE_16(*r_dst);
+    uint res   = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 8;
+    res = MASK_OUT_ABOVE_16(res);
+
+    *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+    FLAG_N = NFLAG_16(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_16(*r_dst);
+  FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+  uint*  r_dst = &DY;
+  uint   orig_shift = DX & 0x3f;
+
+  if(orig_shift != 0)
+  {
+    uint   shift = orig_shift % 33;
+    uint64 src   = *r_dst;
+    uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+    res = ROL_33_64(res, shift);
+
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+    FLAG_C = FLAG_X = res >> 24;
+    res = MASK_OUT_ABOVE_32(res);
+
+    *r_dst = res;
+    FLAG_N = NFLAG_32(res);
+    FLAG_Z = res;
+    FLAG_V = VFLAG_CLEAR;
+    return;
+  }
+
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_Z = *r_dst;
+  FLAG_V = VFLAG_CLEAR;
+
+#else
+
+  uint* r_dst = &DY;
+  uint orig_shift = DX & 0x3f;
+  uint shift = orig_shift % 33;
+  uint src = *r_dst;
+  uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+  uint new_x_flag = src & (1 << (32 - shift));
+
+  if(orig_shift != 0)
+    USE_CYCLES(orig_shift * CYC_SHIFT);
+
+  if(shift != 0)
+  {
+    *r_dst = res;
+    FLAG_X = (new_x_flag != 0)<<8;
+  }
+  else
+    res = src;
+  FLAG_C = FLAG_X;
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+static void __inline m68k_op_roxl_16_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_roxl_16_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = m68ki_read_16(ea);
+  uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+  FLAG_C = FLAG_X = res >> 8;
+  res = MASK_OUT_ABOVE_16(res);
+
+  m68ki_write_16(ea, res);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_rte_32(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr;
+    uint new_pc;
+
+    new_sr = m68ki_pull_16();
+    new_pc = m68ki_pull_32();
+    m68ki_jump(new_pc);
+    m68ki_set_sr(new_sr);
+
+#if M68K_EMULATE_ADDRESS_ERROR
+    CPU_INSTR_MODE = INSTRUCTION_YES;
+    CPU_RUN_MODE = RUN_MODE_NORMAL;
+#endif
+
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_rtr_32(void)
+{
+  m68ki_set_ccr(m68ki_pull_16());
+  m68ki_jump(m68ki_pull_32());
+}
+
+
+static void __inline m68k_op_rts_32(void)
+{
+  m68ki_jump(m68ki_pull_32());
+}
+
+
+static void __inline m68k_op_sbcd_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_sbcd_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+  uint corf = 0;
+
+  if(res > 0xf)
+    corf = 6;
+  res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+  FLAG_V = res; /* Undefined V behavior */
+
+  if(res > 0xff)
+  {
+    res += 0xa0;
+    FLAG_X = FLAG_C = CFLAG_SET;
+  }
+  else if(res < corf)
+    FLAG_X = FLAG_C = CFLAG_SET;
+  else
+    FLAG_X = FLAG_C = 0;
+
+  res = MASK_OUT_ABOVE_8(res-corf);
+
+  FLAG_V &= ~res; /* Undefined V behavior part II */
+  FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_st_8_d(void)
+{
+  DY |= 0xff;
+}
+
+
+static void __inline m68k_op_st_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0xff);
+}
+
+
+static void __inline m68k_op_st_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0xff);
+}
+
+
+static void __inline m68k_op_sf_8_d(void)
+{
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sf_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), 0);
+}
+
+
+static void __inline m68k_op_sf_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), 0);
+}
+
+
+static void __inline m68k_op_shi_8_d(void)
+{
+  if(COND_HI())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sls_8_d(void)
+{
+  if(COND_LS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_scc_8_d(void)
+{
+  if(COND_CC())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_scs_8_d(void)
+{
+  if(COND_CS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sne_8_d(void)
+{
+  if(COND_NE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_seq_8_d(void)
+{
+  if(COND_EQ())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_svc_8_d(void)
+{
+  if(COND_VC())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_svs_8_d(void)
+{
+  if(COND_VS())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_spl_8_d(void)
+{
+  if(COND_PL())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_smi_8_d(void)
+{
+  if(COND_MI())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sge_8_d(void)
+{
+  if(COND_GE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_slt_8_d(void)
+{
+  if(COND_LT())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sgt_8_d(void)
+{
+  if(COND_GT())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_sle_8_d(void)
+{
+  if(COND_LE())
+  {
+    DY |= 0xff;
+    USE_CYCLES(CYC_SCC_R_TRUE);
+    return;
+  }
+  DY &= 0xffffff00;
+}
+
+
+static void __inline m68k_op_shi_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_shi_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sls_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scc_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_scs_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sne_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_seq_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svc_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_svs_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_spl_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_smi_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sge_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_slt_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sgt_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_ai(void)
+{
+  m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pi(void)
+{
+  m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pi7(void)
+{
+  m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pd(void)
+{
+  m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_pd7(void)
+{
+  m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_di(void)
+{
+  m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_ix(void)
+{
+  m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_aw(void)
+{
+  m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_sle_8_al(void)
+{
+  m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0);
+}
+
+
+static void __inline m68k_op_stop(void)
+{
+  if(FLAG_S)
+  {
+    uint new_sr = OPER_I_16();
+    CPU_STOPPED |= STOP_LEVEL_STOP;
+    m68ki_set_sr(new_sr);
+    if (CPU_STOPPED)
+    {
+      SET_CYCLES(m68ki_cpu.cycle_end - 4*MUL);
+    }
+    return;
+  }
+  m68ki_exception_privilege_violation();
+}
+
+
+static void __inline m68k_op_sub_8_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pi7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pd7(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_A7_PD_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(AY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_16_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_d(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_a(void)
+{
+  uint* r_dst = &DX;
+  uint src = AY;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_ai(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_AI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pd(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_PD_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_di(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_DI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_ix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AY_IX_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_aw(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AW_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_al(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_AL_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pcdi(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCDI_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_pcix(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_PCIX_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_32_er_i(void)
+{
+  uint* r_dst = &DX;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_sub_8_re_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_8_re_al(void)
+{
+  uint ea = EA_AL_8();
+  uint src = MASK_OUT_ABOVE_8(DX);
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_ai(void)
+{
+  uint ea = EA_AY_AI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_pi(void)
+{
+  uint ea = EA_AY_PI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_pd(void)
+{
+  uint ea = EA_AY_PD_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_di(void)
+{
+  uint ea = EA_AY_DI_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_ix(void)
+{
+  uint ea = EA_AY_IX_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_aw(void)
+{
+  uint ea = EA_AW_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_16_re_al(void)
+{
+  uint ea = EA_AL_16();
+  uint src = MASK_OUT_ABOVE_16(DX);
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_ai(void)
+{
+  uint ea = EA_AY_AI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_pi(void)
+{
+  uint ea = EA_AY_PI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_pd(void)
+{
+  uint ea = EA_AY_PD_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_di(void)
+{
+  uint ea = EA_AY_DI_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_ix(void)
+{
+  uint ea = EA_AY_IX_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_aw(void)
+{
+  uint ea = EA_AW_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_sub_32_re_al(void)
+{
+  uint ea = EA_AL_32();
+  uint src = DX;
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_suba_16_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
+}
+
+
+static void __inline m68k_op_suba_16_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
+}
+
+
+static void __inline m68k_op_suba_16_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_AI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_PD_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_DI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AY_IX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AW_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_AL_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCDI_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_PCIX_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_16_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = MAKE_INT_16(OPER_I_16());
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_d(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
+}
+
+
+static void __inline m68k_op_suba_32_a(void)
+{
+  uint* r_dst = &AX;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
+}
+
+
+static void __inline m68k_op_suba_32_ai(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_AI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pi(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_PI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pd(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_PD_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_di(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_DI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_ix(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AY_IX_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_aw(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AW_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_al(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_AL_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pcdi(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_PCDI_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_pcix(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_PCIX_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_suba_32_i(void)
+{
+  uint* r_dst = &AX;
+  uint src = OPER_I_32();
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+static void __inline m68k_op_subi_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_8();
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_8_ai(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pi(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pi7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pd(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_pd7(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_di(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_ix(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_aw(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_8_al(void)
+{
+  uint src = OPER_I_8();
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_16();
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_16_ai(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_pi(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_pd(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_di(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_ix(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_aw(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_16_al(void)
+{
+  uint src = OPER_I_16();
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = OPER_I_32();
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_subi_32_ai(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_pi(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_pd(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_di(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_ix(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_aw(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subi_32_al(void)
+{
+  uint src = OPER_I_32();
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_8_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pi7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_pd7(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_8_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = MASK_OUT_ABOVE_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  m68ki_write_8(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_16_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+static void __inline m68k_op_subq_16_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_16_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = MASK_OUT_ABOVE_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  m68ki_write_16(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_d(void)
+{
+  uint* r_dst = &DY;
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint dst = *r_dst;
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  *r_dst = FLAG_Z;
+}
+
+
+static void __inline m68k_op_subq_32_a(void)
+{
+  uint* r_dst = &AY;
+
+  *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+static void __inline m68k_op_subq_32_ai(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_AI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_pi(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_pd(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_di(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_DI_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_ix(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AY_IX_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_aw(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AW_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subq_32_al(void)
+{
+  uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+  uint ea = EA_AL_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = MASK_OUT_ABOVE_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  m68ki_write_32(ea, FLAG_Z);
+}
+
+
+static void __inline m68k_op_subx_8_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_8(DY);
+  uint dst = MASK_OUT_ABOVE_8(*r_dst);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_subx_16_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = MASK_OUT_ABOVE_16(DY);
+  uint dst = MASK_OUT_ABOVE_16(*r_dst);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+static void __inline m68k_op_subx_32_rr(void)
+{
+  uint* r_dst = &DX;
+  uint src = DY;
+  uint dst = *r_dst;
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  *r_dst = res;
+}
+
+
+static void __inline m68k_op_subx_8_mm_ax7(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm_ay7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm_axy7(void)
+{
+  uint src = OPER_A7_PD_8();
+  uint ea  = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_8_mm(void)
+{
+  uint src = OPER_AY_PD_8();
+  uint ea  = EA_AX_PD_8();
+  uint dst = m68ki_read_8(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_X = FLAG_C = CFLAG_8(res);
+  FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+  res = MASK_OUT_ABOVE_8(res);
+  FLAG_Z |= res;
+
+  m68ki_write_8(ea, res);
+}
+
+
+static void __inline m68k_op_subx_16_mm(void)
+{
+  uint src = OPER_AY_PD_16();
+  uint ea  = EA_AX_PD_16();
+  uint dst = m68ki_read_16(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_X = FLAG_C = CFLAG_16(res);
+  FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+  res = MASK_OUT_ABOVE_16(res);
+  FLAG_Z |= res;
+
+  m68ki_write_16(ea, res);
+}
+
+
+static void __inline m68k_op_subx_32_mm(void)
+{
+  uint src = OPER_AY_PD_32();
+  uint ea  = EA_AX_PD_32();
+  uint dst = m68ki_read_32(ea);
+  uint res = dst - src - XFLAG_AS_1();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+  FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+  res = MASK_OUT_ABOVE_32(res);
+  FLAG_Z |= res;
+
+  m68ki_write_32(ea, res);
+}
+
+
+static void __inline m68k_op_swap_32(void)
+{
+  uint* r_dst = &DY;
+
+  FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
+  *r_dst = (*r_dst>>16) | FLAG_Z;
+
+  FLAG_Z = *r_dst;
+  FLAG_N = NFLAG_32(*r_dst);
+  FLAG_C = CFLAG_CLEAR;
+  FLAG_V = VFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tas_8_d(void)
+{
+  uint* r_dst = &DY;
+
+  FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+  FLAG_N = NFLAG_8(*r_dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+  *r_dst |= 0x80;
+}
+
+
+static void __inline m68k_op_tas_8_ai(void)
+{
+  uint ea = EA_AY_AI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pi(void)
+{
+  uint ea = EA_AY_PI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pi7(void)
+{
+  uint ea = EA_A7_PI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pd(void)
+{
+  uint ea = EA_AY_PD_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_pd7(void)
+{
+  uint ea = EA_A7_PD_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_di(void)
+{
+  uint ea = EA_AY_DI_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_ix(void)
+{
+  uint ea = EA_AY_IX_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_aw(void)
+{
+  uint ea = EA_AW_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_tas_8_al(void)
+{
+  uint ea = EA_AL_8();
+  uint dst = m68ki_read_8(ea);
+
+  FLAG_Z = dst;
+  FLAG_N = NFLAG_8(dst);
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+
+  /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
+       disabled in order to function properly.  Some Amiga software may also rely
+       on this, but only when accessing specific addresses so additional functionality
+       will be needed. */
+  if (m68ki_tas_callback()) m68ki_write_8(ea, dst | 0x80);
+}
+
+
+static void __inline m68k_op_trap(void)
+{
+  /* Trap#n stacks exception frame type 0 */
+  m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf));  /* HJB 990403 */
+}
+
+
+static void __inline m68k_op_trapv(void)
+{
+  if(COND_VC())
+  {
+    return;
+  }
+  m68ki_exception_trap(EXCEPTION_TRAPV);  /* HJB 990403 */
+}
+
+
+static void __inline m68k_op_tst_8_d(void)
+{
+  uint res = MASK_OUT_ABOVE_8(DY);
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_ai(void)
+{
+  uint res = OPER_AY_AI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pi(void)
+{
+  uint res = OPER_AY_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pi7(void)
+{
+  uint res = OPER_A7_PI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pd(void)
+{
+  uint res = OPER_AY_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_pd7(void)
+{
+  uint res = OPER_A7_PD_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_di(void)
+{
+  uint res = OPER_AY_DI_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_ix(void)
+{
+  uint res = OPER_AY_IX_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_aw(void)
+{
+  uint res = OPER_AW_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_8_al(void)
+{
+  uint res = OPER_AL_8();
+
+  FLAG_N = NFLAG_8(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_d(void)
+{
+  uint res = MASK_OUT_ABOVE_16(DY);
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_ai(void)
+{
+  uint res = OPER_AY_AI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_pi(void)
+{
+  uint res = OPER_AY_PI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_pd(void)
+{
+  uint res = OPER_AY_PD_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_di(void)
+{
+  uint res = OPER_AY_DI_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_ix(void)
+{
+  uint res = OPER_AY_IX_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_aw(void)
+{
+  uint res = OPER_AW_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_16_al(void)
+{
+  uint res = OPER_AL_16();
+
+  FLAG_N = NFLAG_16(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_d(void)
+{
+  uint res = DY;
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_ai(void)
+{
+  uint res = OPER_AY_AI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_pi(void)
+{
+  uint res = OPER_AY_PI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_pd(void)
+{
+  uint res = OPER_AY_PD_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_di(void)
+{
+  uint res = OPER_AY_DI_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_ix(void)
+{
+  uint res = OPER_AY_IX_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_aw(void)
+{
+  uint res = OPER_AW_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_tst_32_al(void)
+{
+  uint res = OPER_AL_32();
+
+  FLAG_N = NFLAG_32(res);
+  FLAG_Z = res;
+  FLAG_V = VFLAG_CLEAR;
+  FLAG_C = CFLAG_CLEAR;
+}
+
+
+static void __inline m68k_op_unlk_32_a7(void)
+{
+  REG_A[7] = m68ki_read_32(REG_A[7]);
+}
+
+
+static void __inline m68k_op_unlk_32(void)
+{
+  uint* r_dst = &AY;
+
+  REG_A[7] = *r_dst;
+  *r_dst = m68ki_pull_32();
+}
+
+
+/* ======================================================================== */
+/* ========================= OPCODE TABLE BUILDER ========================= */
+/* ======================================================================== */
+
+#ifndef BUILD_TABLES
+
+  #ifndef TABLES_FULL
+    #include "m68ki_instruction_jump_table.h"
+  #else
+    #include "m68ki_instruction_jump_table_full.h"
+  #endif
+#else
+
+/* This is used to generate the opcode handler jump table */
+typedef struct
+{
+  void (*opcode_handler)(void); /* handler function */
+  unsigned int  mask;           /* mask on opcode */
+  unsigned int  match;          /* what to match after masking */
+  unsigned char cycles;         /* cycles each cpu type takes */
+} opcode_handler_struct;
+
+/* opcode handler jump table */
+static void __inline  (*m68ki_instruction_jump_table[0x10000])(void);
+
+/* Opcode handler table */
+static const opcode_handler_struct m68k_opcode_handler_table[] =
+{
+/*   function                      mask    match  cyc */
+  {m68k_op_1010                , 0xf000, 0xa000,  4},
+  {m68k_op_1111                , 0xf000, 0xf000,  4},
+  {m68k_op_moveq_32            , 0xf100, 0x7000,  4},
+  {m68k_op_bra_8               , 0xff00, 0x6000, 10},
+  {m68k_op_bsr_8               , 0xff00, 0x6100, 18},
+  {m68k_op_bhi_8               , 0xff00, 0x6200, 10},
+  {m68k_op_bls_8               , 0xff00, 0x6300, 10},
+  {m68k_op_bcc_8               , 0xff00, 0x6400, 10},
+  {m68k_op_bcs_8               , 0xff00, 0x6500, 10},
+  {m68k_op_bne_8               , 0xff00, 0x6600, 10},
+  {m68k_op_beq_8               , 0xff00, 0x6700, 10},
+  {m68k_op_bvc_8               , 0xff00, 0x6800, 10},
+  {m68k_op_bvs_8               , 0xff00, 0x6900, 10},
+  {m68k_op_bpl_8               , 0xff00, 0x6a00, 10},
+  {m68k_op_bmi_8               , 0xff00, 0x6b00, 10},
+  {m68k_op_bge_8               , 0xff00, 0x6c00, 10},
+  {m68k_op_blt_8               , 0xff00, 0x6d00, 10},
+  {m68k_op_bgt_8               , 0xff00, 0x6e00, 10},
+  {m68k_op_ble_8               , 0xff00, 0x6f00, 10},
+  {m68k_op_btst_32_r_d         , 0xf1f8, 0x0100,  6},
+  {m68k_op_movep_16_er         , 0xf1f8, 0x0108, 16},
+  {m68k_op_btst_8_r_ai         , 0xf1f8, 0x0110,  8},
+  {m68k_op_btst_8_r_pi         , 0xf1f8, 0x0118,  8},
+  {m68k_op_btst_8_r_pd         , 0xf1f8, 0x0120, 10},
+  {m68k_op_btst_8_r_di         , 0xf1f8, 0x0128, 12},
+  {m68k_op_btst_8_r_ix         , 0xf1f8, 0x0130, 14},
+  {m68k_op_bchg_32_r_d         , 0xf1f8, 0x0140,  8},
+  {m68k_op_movep_32_er         , 0xf1f8, 0x0148, 24},
+  {m68k_op_bchg_8_r_ai         , 0xf1f8, 0x0150, 12},
+  {m68k_op_bchg_8_r_pi         , 0xf1f8, 0x0158, 12},
+  {m68k_op_bchg_8_r_pd         , 0xf1f8, 0x0160, 14},
+  {m68k_op_bchg_8_r_di         , 0xf1f8, 0x0168, 16},
+  {m68k_op_bchg_8_r_ix         , 0xf1f8, 0x0170, 18},
+  {m68k_op_bclr_32_r_d         , 0xf1f8, 0x0180, 10},
+  {m68k_op_movep_16_re         , 0xf1f8, 0x0188, 16},
+  {m68k_op_bclr_8_r_ai         , 0xf1f8, 0x0190, 12},
+  {m68k_op_bclr_8_r_pi         , 0xf1f8, 0x0198, 12},
+  {m68k_op_bclr_8_r_pd         , 0xf1f8, 0x01a0, 14},
+  {m68k_op_bclr_8_r_di         , 0xf1f8, 0x01a8, 16},
+  {m68k_op_bclr_8_r_ix         , 0xf1f8, 0x01b0, 18},
+  {m68k_op_bset_32_r_d         , 0xf1f8, 0x01c0,  8},
+  {m68k_op_movep_32_re         , 0xf1f8, 0x01c8, 24},
+  {m68k_op_bset_8_r_ai         , 0xf1f8, 0x01d0, 12},
+  {m68k_op_bset_8_r_pi         , 0xf1f8, 0x01d8, 12},
+  {m68k_op_bset_8_r_pd         , 0xf1f8, 0x01e0, 14},
+  {m68k_op_bset_8_r_di         , 0xf1f8, 0x01e8, 16},
+  {m68k_op_bset_8_r_ix         , 0xf1f8, 0x01f0, 18},
+  {m68k_op_move_8_d_d          , 0xf1f8, 0x1000,  4},
+  {m68k_op_move_8_d_ai         , 0xf1f8, 0x1010,  8},
+  {m68k_op_move_8_d_pi         , 0xf1f8, 0x1018,  8},
+  {m68k_op_move_8_d_pd         , 0xf1f8, 0x1020, 10},
+  {m68k_op_move_8_d_di         , 0xf1f8, 0x1028, 12},
+  {m68k_op_move_8_d_ix         , 0xf1f8, 0x1030, 14},
+  {m68k_op_move_8_ai_d         , 0xf1f8, 0x1080,  8},
+  {m68k_op_move_8_ai_ai        , 0xf1f8, 0x1090, 12},
+  {m68k_op_move_8_ai_pi        , 0xf1f8, 0x1098, 12},
+  {m68k_op_move_8_ai_pd        , 0xf1f8, 0x10a0, 14},
+  {m68k_op_move_8_ai_di        , 0xf1f8, 0x10a8, 16},
+  {m68k_op_move_8_ai_ix        , 0xf1f8, 0x10b0, 18},
+  {m68k_op_move_8_pi_d         , 0xf1f8, 0x10c0,  8},
+  {m68k_op_move_8_pi_ai        , 0xf1f8, 0x10d0, 12},
+  {m68k_op_move_8_pi_pi        , 0xf1f8, 0x10d8, 12},
+  {m68k_op_move_8_pi_pd        , 0xf1f8, 0x10e0, 14},
+  {m68k_op_move_8_pi_di        , 0xf1f8, 0x10e8, 16},
+  {m68k_op_move_8_pi_ix        , 0xf1f8, 0x10f0, 18},
+  {m68k_op_move_8_pd_d         , 0xf1f8, 0x1100,  8},
+  {m68k_op_move_8_pd_ai        , 0xf1f8, 0x1110, 12},
+  {m68k_op_move_8_pd_pi        , 0xf1f8, 0x1118, 12},
+  {m68k_op_move_8_pd_pd        , 0xf1f8, 0x1120, 14},
+  {m68k_op_move_8_pd_di        , 0xf1f8, 0x1128, 16},
+  {m68k_op_move_8_pd_ix        , 0xf1f8, 0x1130, 18},
+  {m68k_op_move_8_di_d         , 0xf1f8, 0x1140, 12},
+  {m68k_op_move_8_di_ai        , 0xf1f8, 0x1150, 16},
+  {m68k_op_move_8_di_pi        , 0xf1f8, 0x1158, 16},
+  {m68k_op_move_8_di_pd        , 0xf1f8, 0x1160, 18},
+  {m68k_op_move_8_di_di        , 0xf1f8, 0x1168, 20},
+  {m68k_op_move_8_di_ix        , 0xf1f8, 0x1170, 22},
+  {m68k_op_move_8_ix_d         , 0xf1f8, 0x1180, 14},
+  {m68k_op_move_8_ix_ai        , 0xf1f8, 0x1190, 18},
+  {m68k_op_move_8_ix_pi        , 0xf1f8, 0x1198, 18},
+  {m68k_op_move_8_ix_pd        , 0xf1f8, 0x11a0, 20},
+  {m68k_op_move_8_ix_di        , 0xf1f8, 0x11a8, 22},
+  {m68k_op_move_8_ix_ix        , 0xf1f8, 0x11b0, 24},
+  {m68k_op_move_32_d_d         , 0xf1f8, 0x2000,  4},
+  {m68k_op_move_32_d_a         , 0xf1f8, 0x2008,  4},
+  {m68k_op_move_32_d_ai        , 0xf1f8, 0x2010, 12},
+  {m68k_op_move_32_d_pi        , 0xf1f8, 0x2018, 12},
+  {m68k_op_move_32_d_pd        , 0xf1f8, 0x2020, 14},
+  {m68k_op_move_32_d_di        , 0xf1f8, 0x2028, 16},
+  {m68k_op_move_32_d_ix        , 0xf1f8, 0x2030, 18},
+  {m68k_op_movea_32_d          , 0xf1f8, 0x2040,  4},
+  {m68k_op_movea_32_a          , 0xf1f8, 0x2048,  4},
+  {m68k_op_movea_32_ai         , 0xf1f8, 0x2050, 12},
+  {m68k_op_movea_32_pi         , 0xf1f8, 0x2058, 12},
+  {m68k_op_movea_32_pd         , 0xf1f8, 0x2060, 14},
+  {m68k_op_movea_32_di         , 0xf1f8, 0x2068, 16},
+  {m68k_op_movea_32_ix         , 0xf1f8, 0x2070, 18},
+  {m68k_op_move_32_ai_d        , 0xf1f8, 0x2080, 12},
+  {m68k_op_move_32_ai_a        , 0xf1f8, 0x2088, 12},
+  {m68k_op_move_32_ai_ai       , 0xf1f8, 0x2090, 20},
+  {m68k_op_move_32_ai_pi       , 0xf1f8, 0x2098, 20},
+  {m68k_op_move_32_ai_pd       , 0xf1f8, 0x20a0, 22},
+  {m68k_op_move_32_ai_di       , 0xf1f8, 0x20a8, 24},
+  {m68k_op_move_32_ai_ix       , 0xf1f8, 0x20b0, 26},
+  {m68k_op_move_32_pi_d        , 0xf1f8, 0x20c0, 12},
+  {m68k_op_move_32_pi_a        , 0xf1f8, 0x20c8, 12},
+  {m68k_op_move_32_pi_ai       , 0xf1f8, 0x20d0, 20},
+  {m68k_op_move_32_pi_pi       , 0xf1f8, 0x20d8, 20},
+  {m68k_op_move_32_pi_pd       , 0xf1f8, 0x20e0, 22},
+  {m68k_op_move_32_pi_di       , 0xf1f8, 0x20e8, 24},
+  {m68k_op_move_32_pi_ix       , 0xf1f8, 0x20f0, 26},
+  {m68k_op_move_32_pd_d        , 0xf1f8, 0x2100, 12},
+  {m68k_op_move_32_pd_a        , 0xf1f8, 0x2108, 12},
+  {m68k_op_move_32_pd_ai       , 0xf1f8, 0x2110, 20},
+  {m68k_op_move_32_pd_pi       , 0xf1f8, 0x2118, 20},
+  {m68k_op_move_32_pd_pd       , 0xf1f8, 0x2120, 22},
+  {m68k_op_move_32_pd_di       , 0xf1f8, 0x2128, 24},
+  {m68k_op_move_32_pd_ix       , 0xf1f8, 0x2130, 26},
+  {m68k_op_move_32_di_d        , 0xf1f8, 0x2140, 16},
+  {m68k_op_move_32_di_a        , 0xf1f8, 0x2148, 16},
+  {m68k_op_move_32_di_ai       , 0xf1f8, 0x2150, 24},
+  {m68k_op_move_32_di_pi       , 0xf1f8, 0x2158, 24},
+  {m68k_op_move_32_di_pd       , 0xf1f8, 0x2160, 26},
+  {m68k_op_move_32_di_di       , 0xf1f8, 0x2168, 28},
+  {m68k_op_move_32_di_ix       , 0xf1f8, 0x2170, 30},
+  {m68k_op_move_32_ix_d        , 0xf1f8, 0x2180, 18},
+  {m68k_op_move_32_ix_a        , 0xf1f8, 0x2188, 18},
+  {m68k_op_move_32_ix_ai       , 0xf1f8, 0x2190, 26},
+  {m68k_op_move_32_ix_pi       , 0xf1f8, 0x2198, 26},
+  {m68k_op_move_32_ix_pd       , 0xf1f8, 0x21a0, 28},
+  {m68k_op_move_32_ix_di       , 0xf1f8, 0x21a8, 30},
+  {m68k_op_move_32_ix_ix       , 0xf1f8, 0x21b0, 32},
+  {m68k_op_move_16_d_d         , 0xf1f8, 0x3000,  4},
+  {m68k_op_move_16_d_a         , 0xf1f8, 0x3008,  4},
+  {m68k_op_move_16_d_ai        , 0xf1f8, 0x3010,  8},
+  {m68k_op_move_16_d_pi        , 0xf1f8, 0x3018,  8},
+  {m68k_op_move_16_d_pd        , 0xf1f8, 0x3020, 10},
+  {m68k_op_move_16_d_di        , 0xf1f8, 0x3028, 12},
+  {m68k_op_move_16_d_ix        , 0xf1f8, 0x3030, 14},
+  {m68k_op_movea_16_d          , 0xf1f8, 0x3040,  4},
+  {m68k_op_movea_16_a          , 0xf1f8, 0x3048,  4},
+  {m68k_op_movea_16_ai         , 0xf1f8, 0x3050,  8},
+  {m68k_op_movea_16_pi         , 0xf1f8, 0x3058,  8},
+  {m68k_op_movea_16_pd         , 0xf1f8, 0x3060, 10},
+  {m68k_op_movea_16_di         , 0xf1f8, 0x3068, 12},
+  {m68k_op_movea_16_ix         , 0xf1f8, 0x3070, 14},
+  {m68k_op_move_16_ai_d        , 0xf1f8, 0x3080,  8},
+  {m68k_op_move_16_ai_a        , 0xf1f8, 0x3088,  8},
+  {m68k_op_move_16_ai_ai       , 0xf1f8, 0x3090, 12},
+  {m68k_op_move_16_ai_pi       , 0xf1f8, 0x3098, 12},
+  {m68k_op_move_16_ai_pd       , 0xf1f8, 0x30a0, 14},
+  {m68k_op_move_16_ai_di       , 0xf1f8, 0x30a8, 16},
+  {m68k_op_move_16_ai_ix       , 0xf1f8, 0x30b0, 18},
+  {m68k_op_move_16_pi_d        , 0xf1f8, 0x30c0,  8},
+  {m68k_op_move_16_pi_a        , 0xf1f8, 0x30c8,  8},
+  {m68k_op_move_16_pi_ai       , 0xf1f8, 0x30d0, 12},
+  {m68k_op_move_16_pi_pi       , 0xf1f8, 0x30d8, 12},
+  {m68k_op_move_16_pi_pd       , 0xf1f8, 0x30e0, 14},
+  {m68k_op_move_16_pi_di       , 0xf1f8, 0x30e8, 16},
+  {m68k_op_move_16_pi_ix       , 0xf1f8, 0x30f0, 18},
+  {m68k_op_move_16_pd_d        , 0xf1f8, 0x3100,  8},
+  {m68k_op_move_16_pd_a        , 0xf1f8, 0x3108,  8},
+  {m68k_op_move_16_pd_ai       , 0xf1f8, 0x3110, 12},
+  {m68k_op_move_16_pd_pi       , 0xf1f8, 0x3118, 12},
+  {m68k_op_move_16_pd_pd       , 0xf1f8, 0x3120, 14},
+  {m68k_op_move_16_pd_di       , 0xf1f8, 0x3128, 16},
+  {m68k_op_move_16_pd_ix       , 0xf1f8, 0x3130, 18},
+  {m68k_op_move_16_di_d        , 0xf1f8, 0x3140, 12},
+  {m68k_op_move_16_di_a        , 0xf1f8, 0x3148, 12},
+  {m68k_op_move_16_di_ai       , 0xf1f8, 0x3150, 16},
+  {m68k_op_move_16_di_pi       , 0xf1f8, 0x3158, 16},
+  {m68k_op_move_16_di_pd       , 0xf1f8, 0x3160, 18},
+  {m68k_op_move_16_di_di       , 0xf1f8, 0x3168, 20},
+  {m68k_op_move_16_di_ix       , 0xf1f8, 0x3170, 22},
+  {m68k_op_move_16_ix_d        , 0xf1f8, 0x3180, 14},
+  {m68k_op_move_16_ix_a        , 0xf1f8, 0x3188, 14},
+  {m68k_op_move_16_ix_ai       , 0xf1f8, 0x3190, 18},
+  {m68k_op_move_16_ix_pi       , 0xf1f8, 0x3198, 18},
+  {m68k_op_move_16_ix_pd       , 0xf1f8, 0x31a0, 20},
+  {m68k_op_move_16_ix_di       , 0xf1f8, 0x31a8, 22},
+  {m68k_op_move_16_ix_ix       , 0xf1f8, 0x31b0, 24},
+  {m68k_op_chk_16_d            , 0xf1f8, 0x4180, 10},
+  {m68k_op_chk_16_ai           , 0xf1f8, 0x4190, 14},
+  {m68k_op_chk_16_pi           , 0xf1f8, 0x4198, 14},
+  {m68k_op_chk_16_pd           , 0xf1f8, 0x41a0, 16},
+  {m68k_op_chk_16_di           , 0xf1f8, 0x41a8, 18},
+  {m68k_op_chk_16_ix           , 0xf1f8, 0x41b0, 20},
+  {m68k_op_lea_32_ai           , 0xf1f8, 0x41d0,  4},
+  {m68k_op_lea_32_di           , 0xf1f8, 0x41e8,  8},
+  {m68k_op_lea_32_ix           , 0xf1f8, 0x41f0, 12},
+  {m68k_op_addq_8_d            , 0xf1f8, 0x5000,  4},
+  {m68k_op_addq_8_ai           , 0xf1f8, 0x5010, 12},
+  {m68k_op_addq_8_pi           , 0xf1f8, 0x5018, 12},
+  {m68k_op_addq_8_pd           , 0xf1f8, 0x5020, 14},
+  {m68k_op_addq_8_di           , 0xf1f8, 0x5028, 16},
+  {m68k_op_addq_8_ix           , 0xf1f8, 0x5030, 18},
+  {m68k_op_addq_16_d           , 0xf1f8, 0x5040,  4},
+  {m68k_op_addq_16_a           , 0xf1f8, 0x5048,  8}, /* see Yacht.txt */
+  {m68k_op_addq_16_ai          , 0xf1f8, 0x5050, 12},
+  {m68k_op_addq_16_pi          , 0xf1f8, 0x5058, 12},
+  {m68k_op_addq_16_pd          , 0xf1f8, 0x5060, 14},
+  {m68k_op_addq_16_di          , 0xf1f8, 0x5068, 16},
+  {m68k_op_addq_16_ix          , 0xf1f8, 0x5070, 18},
+  {m68k_op_addq_32_d           , 0xf1f8, 0x5080,  8},
+  {m68k_op_addq_32_a           , 0xf1f8, 0x5088,  8},
+  {m68k_op_addq_32_ai          , 0xf1f8, 0x5090, 20},
+  {m68k_op_addq_32_pi          , 0xf1f8, 0x5098, 20},
+  {m68k_op_addq_32_pd          , 0xf1f8, 0x50a0, 22},
+  {m68k_op_addq_32_di          , 0xf1f8, 0x50a8, 24},
+  {m68k_op_addq_32_ix          , 0xf1f8, 0x50b0, 26},
+  {m68k_op_subq_8_d            , 0xf1f8, 0x5100,  4},
+  {m68k_op_subq_8_ai           , 0xf1f8, 0x5110, 12},
+  {m68k_op_subq_8_pi           , 0xf1f8, 0x5118, 12},
+  {m68k_op_subq_8_pd           , 0xf1f8, 0x5120, 14},
+  {m68k_op_subq_8_di           , 0xf1f8, 0x5128, 16},
+  {m68k_op_subq_8_ix           , 0xf1f8, 0x5130, 18},
+  {m68k_op_subq_16_d           , 0xf1f8, 0x5140,  4},
+  {m68k_op_subq_16_a           , 0xf1f8, 0x5148,  8},
+  {m68k_op_subq_16_ai          , 0xf1f8, 0x5150, 12},
+  {m68k_op_subq_16_pi          , 0xf1f8, 0x5158, 12},
+  {m68k_op_subq_16_pd          , 0xf1f8, 0x5160, 14},
+  {m68k_op_subq_16_di          , 0xf1f8, 0x5168, 16},
+  {m68k_op_subq_16_ix          , 0xf1f8, 0x5170, 18},
+  {m68k_op_subq_32_d           , 0xf1f8, 0x5180,  8},
+  {m68k_op_subq_32_a           , 0xf1f8, 0x5188,  8},
+  {m68k_op_subq_32_ai          , 0xf1f8, 0x5190, 20},
+  {m68k_op_subq_32_pi          , 0xf1f8, 0x5198, 20},
+  {m68k_op_subq_32_pd          , 0xf1f8, 0x51a0, 22},
+  {m68k_op_subq_32_di          , 0xf1f8, 0x51a8, 24},
+  {m68k_op_subq_32_ix          , 0xf1f8, 0x51b0, 26},
+  {m68k_op_or_8_er_d           , 0xf1f8, 0x8000,  4},
+  {m68k_op_or_8_er_ai          , 0xf1f8, 0x8010,  8},
+  {m68k_op_or_8_er_pi          , 0xf1f8, 0x8018,  8},
+  {m68k_op_or_8_er_pd          , 0xf1f8, 0x8020, 10},
+  {m68k_op_or_8_er_di          , 0xf1f8, 0x8028, 12},
+  {m68k_op_or_8_er_ix          , 0xf1f8, 0x8030, 14},
+  {m68k_op_or_16_er_d          , 0xf1f8, 0x8040,  4},
+  {m68k_op_or_16_er_ai         , 0xf1f8, 0x8050,  8},
+  {m68k_op_or_16_er_pi         , 0xf1f8, 0x8058,  8},
+  {m68k_op_or_16_er_pd         , 0xf1f8, 0x8060, 10},
+  {m68k_op_or_16_er_di         , 0xf1f8, 0x8068, 12},
+  {m68k_op_or_16_er_ix         , 0xf1f8, 0x8070, 14},
+  {m68k_op_or_32_er_d          , 0xf1f8, 0x8080,  8},
+  {m68k_op_or_32_er_ai         , 0xf1f8, 0x8090, 14},
+  {m68k_op_or_32_er_pi         , 0xf1f8, 0x8098, 14},
+  {m68k_op_or_32_er_pd         , 0xf1f8, 0x80a0, 16},
+  {m68k_op_or_32_er_di         , 0xf1f8, 0x80a8, 18},
+  {m68k_op_or_32_er_ix         , 0xf1f8, 0x80b0, 20},
+  {m68k_op_divu_16_d           , 0xf1f8, 0x80c0,  0},
+  {m68k_op_divu_16_ai          , 0xf1f8, 0x80d0,  4},
+  {m68k_op_divu_16_pi          , 0xf1f8, 0x80d8,  4},
+  {m68k_op_divu_16_pd          , 0xf1f8, 0x80e0,  6},
+  {m68k_op_divu_16_di          , 0xf1f8, 0x80e8,  8},
+  {m68k_op_divu_16_ix          , 0xf1f8, 0x80f0, 10},
+  {m68k_op_sbcd_8_rr           , 0xf1f8, 0x8100,  6},
+  {m68k_op_sbcd_8_mm           , 0xf1f8, 0x8108, 18},
+  {m68k_op_or_8_re_ai          , 0xf1f8, 0x8110, 12},
+  {m68k_op_or_8_re_pi          , 0xf1f8, 0x8118, 12},
+  {m68k_op_or_8_re_pd          , 0xf1f8, 0x8120, 14},
+  {m68k_op_or_8_re_di          , 0xf1f8, 0x8128, 16},
+  {m68k_op_or_8_re_ix          , 0xf1f8, 0x8130, 18},
+  {m68k_op_or_16_re_ai         , 0xf1f8, 0x8150, 12},
+  {m68k_op_or_16_re_pi         , 0xf1f8, 0x8158, 12},
+  {m68k_op_or_16_re_pd         , 0xf1f8, 0x8160, 14},
+  {m68k_op_or_16_re_di         , 0xf1f8, 0x8168, 16},
+  {m68k_op_or_16_re_ix         , 0xf1f8, 0x8170, 18},
+  {m68k_op_or_32_re_ai         , 0xf1f8, 0x8190, 20},
+  {m68k_op_or_32_re_pi         , 0xf1f8, 0x8198, 20},
+  {m68k_op_or_32_re_pd         , 0xf1f8, 0x81a0, 22},
+  {m68k_op_or_32_re_di         , 0xf1f8, 0x81a8, 24},
+  {m68k_op_or_32_re_ix         , 0xf1f8, 0x81b0, 26},
+  {m68k_op_divs_16_d           , 0xf1f8, 0x81c0,  0},
+  {m68k_op_divs_16_ai          , 0xf1f8, 0x81d0,  4},
+  {m68k_op_divs_16_pi          , 0xf1f8, 0x81d8,  4},
+  {m68k_op_divs_16_pd          , 0xf1f8, 0x81e0,  6},
+  {m68k_op_divs_16_di          , 0xf1f8, 0x81e8,  8},
+  {m68k_op_divs_16_ix          , 0xf1f8, 0x81f0, 10},
+  {m68k_op_sub_8_er_d          , 0xf1f8, 0x9000,  4},
+  {m68k_op_sub_8_er_ai         , 0xf1f8, 0x9010,  8},
+  {m68k_op_sub_8_er_pi         , 0xf1f8, 0x9018,  8},
+  {m68k_op_sub_8_er_pd         , 0xf1f8, 0x9020, 10},
+  {m68k_op_sub_8_er_di         , 0xf1f8, 0x9028, 12},
+  {m68k_op_sub_8_er_ix         , 0xf1f8, 0x9030, 14},
+  {m68k_op_sub_16_er_d         , 0xf1f8, 0x9040,  4},
+  {m68k_op_sub_16_er_a         , 0xf1f8, 0x9048,  4},
+  {m68k_op_sub_16_er_ai        , 0xf1f8, 0x9050,  8},
+  {m68k_op_sub_16_er_pi        , 0xf1f8, 0x9058,  8},
+  {m68k_op_sub_16_er_pd        , 0xf1f8, 0x9060, 10},
+  {m68k_op_sub_16_er_di        , 0xf1f8, 0x9068, 12},
+  {m68k_op_sub_16_er_ix        , 0xf1f8, 0x9070, 14},
+  {m68k_op_sub_32_er_d         , 0xf1f8, 0x9080,  8},
+  {m68k_op_sub_32_er_a         , 0xf1f8, 0x9088,  8},
+  {m68k_op_sub_32_er_ai        , 0xf1f8, 0x9090, 14},
+  {m68k_op_sub_32_er_pi        , 0xf1f8, 0x9098, 14},
+  {m68k_op_sub_32_er_pd        , 0xf1f8, 0x90a0, 16},
+  {m68k_op_sub_32_er_di        , 0xf1f8, 0x90a8, 18},
+  {m68k_op_sub_32_er_ix        , 0xf1f8, 0x90b0, 20},
+  {m68k_op_suba_16_d           , 0xf1f8, 0x90c0,  8},
+  {m68k_op_suba_16_a           , 0xf1f8, 0x90c8,  8},
+  {m68k_op_suba_16_ai          , 0xf1f8, 0x90d0, 12},
+  {m68k_op_suba_16_pi          , 0xf1f8, 0x90d8, 12},
+  {m68k_op_suba_16_pd          , 0xf1f8, 0x90e0, 14},
+  {m68k_op_suba_16_di          , 0xf1f8, 0x90e8, 16},
+  {m68k_op_suba_16_ix          , 0xf1f8, 0x90f0, 18},
+  {m68k_op_subx_8_rr           , 0xf1f8, 0x9100,  4},
+  {m68k_op_subx_8_mm           , 0xf1f8, 0x9108, 18},
+  {m68k_op_sub_8_re_ai         , 0xf1f8, 0x9110, 12},
+  {m68k_op_sub_8_re_pi         , 0xf1f8, 0x9118, 12},
+  {m68k_op_sub_8_re_pd         , 0xf1f8, 0x9120, 14},
+  {m68k_op_sub_8_re_di         , 0xf1f8, 0x9128, 16},
+  {m68k_op_sub_8_re_ix         , 0xf1f8, 0x9130, 18},
+  {m68k_op_subx_16_rr          , 0xf1f8, 0x9140,  4},
+  {m68k_op_subx_16_mm          , 0xf1f8, 0x9148, 18},
+  {m68k_op_sub_16_re_ai        , 0xf1f8, 0x9150, 12},
+  {m68k_op_sub_16_re_pi        , 0xf1f8, 0x9158, 12},
+  {m68k_op_sub_16_re_pd        , 0xf1f8, 0x9160, 14},
+  {m68k_op_sub_16_re_di        , 0xf1f8, 0x9168, 16},
+  {m68k_op_sub_16_re_ix        , 0xf1f8, 0x9170, 18},
+  {m68k_op_subx_32_rr          , 0xf1f8, 0x9180,  8},
+  {m68k_op_subx_32_mm          , 0xf1f8, 0x9188, 30},
+  {m68k_op_sub_32_re_ai        , 0xf1f8, 0x9190, 20},
+  {m68k_op_sub_32_re_pi        , 0xf1f8, 0x9198, 20},
+  {m68k_op_sub_32_re_pd        , 0xf1f8, 0x91a0, 22},
+  {m68k_op_sub_32_re_di        , 0xf1f8, 0x91a8, 24},
+  {m68k_op_sub_32_re_ix        , 0xf1f8, 0x91b0, 26},
+  {m68k_op_suba_32_d           , 0xf1f8, 0x91c0,  8},
+  {m68k_op_suba_32_a           , 0xf1f8, 0x91c8,  8},
+  {m68k_op_suba_32_ai          , 0xf1f8, 0x91d0, 14},
+  {m68k_op_suba_32_pi          , 0xf1f8, 0x91d8, 14},
+  {m68k_op_suba_32_pd          , 0xf1f8, 0x91e0, 16},
+  {m68k_op_suba_32_di          , 0xf1f8, 0x91e8, 18},
+  {m68k_op_suba_32_ix          , 0xf1f8, 0x91f0, 20},
+  {m68k_op_cmp_8_d             , 0xf1f8, 0xb000,  4},
+  {m68k_op_cmp_8_ai            , 0xf1f8, 0xb010,  8},
+  {m68k_op_cmp_8_pi            , 0xf1f8, 0xb018,  8},
+  {m68k_op_cmp_8_pd            , 0xf1f8, 0xb020, 10},
+  {m68k_op_cmp_8_di            , 0xf1f8, 0xb028, 12},
+  {m68k_op_cmp_8_ix            , 0xf1f8, 0xb030, 14},
+  {m68k_op_cmp_16_d            , 0xf1f8, 0xb040,  4},
+  {m68k_op_cmp_16_a            , 0xf1f8, 0xb048,  4},
+  {m68k_op_cmp_16_ai           , 0xf1f8, 0xb050,  8},
+  {m68k_op_cmp_16_pi           , 0xf1f8, 0xb058,  8},
+  {m68k_op_cmp_16_pd           , 0xf1f8, 0xb060, 10},
+  {m68k_op_cmp_16_di           , 0xf1f8, 0xb068, 12},
+  {m68k_op_cmp_16_ix           , 0xf1f8, 0xb070, 14},
+  {m68k_op_cmp_32_d            , 0xf1f8, 0xb080,  6},
+  {m68k_op_cmp_32_a            , 0xf1f8, 0xb088,  6},
+  {m68k_op_cmp_32_ai           , 0xf1f8, 0xb090, 14},
+  {m68k_op_cmp_32_pi           , 0xf1f8, 0xb098, 14},
+  {m68k_op_cmp_32_pd           , 0xf1f8, 0xb0a0, 16},
+  {m68k_op_cmp_32_di           , 0xf1f8, 0xb0a8, 18},
+  {m68k_op_cmp_32_ix           , 0xf1f8, 0xb0b0, 20},
+  {m68k_op_cmpa_16_d           , 0xf1f8, 0xb0c0,  6},
+  {m68k_op_cmpa_16_a           , 0xf1f8, 0xb0c8,  6},
+  {m68k_op_cmpa_16_ai          , 0xf1f8, 0xb0d0, 10},
+  {m68k_op_cmpa_16_pi          , 0xf1f8, 0xb0d8, 10},
+  {m68k_op_cmpa_16_pd          , 0xf1f8, 0xb0e0, 12},
+  {m68k_op_cmpa_16_di          , 0xf1f8, 0xb0e8, 14},
+  {m68k_op_cmpa_16_ix          , 0xf1f8, 0xb0f0, 16},
+  {m68k_op_eor_8_d             , 0xf1f8, 0xb100,  4},
+  {m68k_op_cmpm_8              , 0xf1f8, 0xb108, 12},
+  {m68k_op_eor_8_ai            , 0xf1f8, 0xb110, 12},
+  {m68k_op_eor_8_pi            , 0xf1f8, 0xb118, 12},
+  {m68k_op_eor_8_pd            , 0xf1f8, 0xb120, 14},
+  {m68k_op_eor_8_di            , 0xf1f8, 0xb128, 16},
+  {m68k_op_eor_8_ix            , 0xf1f8, 0xb130, 18},
+  {m68k_op_eor_16_d            , 0xf1f8, 0xb140,  4},
+  {m68k_op_cmpm_16             , 0xf1f8, 0xb148, 12},
+  {m68k_op_eor_16_ai           , 0xf1f8, 0xb150, 12},
+  {m68k_op_eor_16_pi           , 0xf1f8, 0xb158, 12},
+  {m68k_op_eor_16_pd           , 0xf1f8, 0xb160, 14},
+  {m68k_op_eor_16_di           , 0xf1f8, 0xb168, 16},
+  {m68k_op_eor_16_ix           , 0xf1f8, 0xb170, 18},
+  {m68k_op_eor_32_d            , 0xf1f8, 0xb180,  8},
+  {m68k_op_cmpm_32             , 0xf1f8, 0xb188, 20},
+  {m68k_op_eor_32_ai           , 0xf1f8, 0xb190, 20},
+  {m68k_op_eor_32_pi           , 0xf1f8, 0xb198, 20},
+  {m68k_op_eor_32_pd           , 0xf1f8, 0xb1a0, 22},
+  {m68k_op_eor_32_di           , 0xf1f8, 0xb1a8, 24},
+  {m68k_op_eor_32_ix           , 0xf1f8, 0xb1b0, 26},
+  {m68k_op_cmpa_32_d           , 0xf1f8, 0xb1c0,  6},
+  {m68k_op_cmpa_32_a           , 0xf1f8, 0xb1c8,  6},
+  {m68k_op_cmpa_32_ai          , 0xf1f8, 0xb1d0, 14},
+  {m68k_op_cmpa_32_pi          , 0xf1f8, 0xb1d8, 14},
+  {m68k_op_cmpa_32_pd          , 0xf1f8, 0xb1e0, 16},
+  {m68k_op_cmpa_32_di          , 0xf1f8, 0xb1e8, 18},
+  {m68k_op_cmpa_32_ix          , 0xf1f8, 0xb1f0, 20},
+  {m68k_op_and_8_er_d          , 0xf1f8, 0xc000,  4},
+  {m68k_op_and_8_er_ai         , 0xf1f8, 0xc010,  8},
+  {m68k_op_and_8_er_pi         , 0xf1f8, 0xc018,  8},
+  {m68k_op_and_8_er_pd         , 0xf1f8, 0xc020, 10},
+  {m68k_op_and_8_er_di         , 0xf1f8, 0xc028, 12},
+  {m68k_op_and_8_er_ix         , 0xf1f8, 0xc030, 14},
+  {m68k_op_and_16_er_d         , 0xf1f8, 0xc040,  4},
+  {m68k_op_and_16_er_ai        , 0xf1f8, 0xc050,  8},
+  {m68k_op_and_16_er_pi        , 0xf1f8, 0xc058,  8},
+  {m68k_op_and_16_er_pd        , 0xf1f8, 0xc060, 10},
+  {m68k_op_and_16_er_di        , 0xf1f8, 0xc068, 12},
+  {m68k_op_and_16_er_ix        , 0xf1f8, 0xc070, 14},
+  {m68k_op_and_32_er_d         , 0xf1f8, 0xc080,  8},
+  {m68k_op_and_32_er_ai        , 0xf1f8, 0xc090, 14},
+  {m68k_op_and_32_er_pi        , 0xf1f8, 0xc098, 14},
+  {m68k_op_and_32_er_pd        , 0xf1f8, 0xc0a0, 16},
+  {m68k_op_and_32_er_di        , 0xf1f8, 0xc0a8, 18},
+  {m68k_op_and_32_er_ix        , 0xf1f8, 0xc0b0, 20},
+  {m68k_op_mulu_16_d           , 0xf1f8, 0xc0c0,  0},
+  {m68k_op_mulu_16_ai          , 0xf1f8, 0xc0d0,  4},
+  {m68k_op_mulu_16_pi          , 0xf1f8, 0xc0d8,  4},
+  {m68k_op_mulu_16_pd          , 0xf1f8, 0xc0e0,  6},
+  {m68k_op_mulu_16_di          , 0xf1f8, 0xc0e8,  8},
+  {m68k_op_mulu_16_ix          , 0xf1f8, 0xc0f0, 10},
+  {m68k_op_abcd_8_rr           , 0xf1f8, 0xc100,  6},
+  {m68k_op_abcd_8_mm           , 0xf1f8, 0xc108, 18},
+  {m68k_op_and_8_re_ai         , 0xf1f8, 0xc110, 12},
+  {m68k_op_and_8_re_pi         , 0xf1f8, 0xc118, 12},
+  {m68k_op_and_8_re_pd         , 0xf1f8, 0xc120, 14},
+  {m68k_op_and_8_re_di         , 0xf1f8, 0xc128, 16},
+  {m68k_op_and_8_re_ix         , 0xf1f8, 0xc130, 18},
+  {m68k_op_exg_32_dd           , 0xf1f8, 0xc140,  6},
+  {m68k_op_exg_32_aa           , 0xf1f8, 0xc148,  6},
+  {m68k_op_and_16_re_ai        , 0xf1f8, 0xc150, 12},
+  {m68k_op_and_16_re_pi        , 0xf1f8, 0xc158, 12},
+  {m68k_op_and_16_re_pd        , 0xf1f8, 0xc160, 14},
+  {m68k_op_and_16_re_di        , 0xf1f8, 0xc168, 16},
+  {m68k_op_and_16_re_ix        , 0xf1f8, 0xc170, 18},
+  {m68k_op_exg_32_da           , 0xf1f8, 0xc188,  6},
+  {m68k_op_and_32_re_ai        , 0xf1f8, 0xc190, 20},
+  {m68k_op_and_32_re_pi        , 0xf1f8, 0xc198, 20},
+  {m68k_op_and_32_re_pd        , 0xf1f8, 0xc1a0, 22},
+  {m68k_op_and_32_re_di        , 0xf1f8, 0xc1a8, 24},
+  {m68k_op_and_32_re_ix        , 0xf1f8, 0xc1b0, 26},
+  {m68k_op_muls_16_d           , 0xf1f8, 0xc1c0,  0},
+  {m68k_op_muls_16_ai          , 0xf1f8, 0xc1d0,  4},
+  {m68k_op_muls_16_pi          , 0xf1f8, 0xc1d8,  4},
+  {m68k_op_muls_16_pd          , 0xf1f8, 0xc1e0,  6},
+  {m68k_op_muls_16_di          , 0xf1f8, 0xc1e8,  8},
+  {m68k_op_muls_16_ix          , 0xf1f8, 0xc1f0, 10},
+  {m68k_op_add_8_er_d          , 0xf1f8, 0xd000,  4},
+  {m68k_op_add_8_er_ai         , 0xf1f8, 0xd010,  8},
+  {m68k_op_add_8_er_pi         , 0xf1f8, 0xd018,  8},
+  {m68k_op_add_8_er_pd         , 0xf1f8, 0xd020, 10},
+  {m68k_op_add_8_er_di         , 0xf1f8, 0xd028, 12},
+  {m68k_op_add_8_er_ix         , 0xf1f8, 0xd030, 14},
+  {m68k_op_add_16_er_d         , 0xf1f8, 0xd040,  4},
+  {m68k_op_add_16_er_a         , 0xf1f8, 0xd048,  4},
+  {m68k_op_add_16_er_ai        , 0xf1f8, 0xd050,  8},
+  {m68k_op_add_16_er_pi        , 0xf1f8, 0xd058,  8},
+  {m68k_op_add_16_er_pd        , 0xf1f8, 0xd060, 10},
+  {m68k_op_add_16_er_di        , 0xf1f8, 0xd068, 12},
+  {m68k_op_add_16_er_ix        , 0xf1f8, 0xd070, 14},
+  {m68k_op_add_32_er_d         , 0xf1f8, 0xd080,  8},
+  {m68k_op_add_32_er_a         , 0xf1f8, 0xd088,  8},
+  {m68k_op_add_32_er_ai        , 0xf1f8, 0xd090, 14},
+  {m68k_op_add_32_er_pi        , 0xf1f8, 0xd098, 14},
+  {m68k_op_add_32_er_pd        , 0xf1f8, 0xd0a0, 16},
+  {m68k_op_add_32_er_di        , 0xf1f8, 0xd0a8, 18},
+  {m68k_op_add_32_er_ix        , 0xf1f8, 0xd0b0, 20},
+  {m68k_op_adda_16_d           , 0xf1f8, 0xd0c0,  8},
+  {m68k_op_adda_16_a           , 0xf1f8, 0xd0c8,  8},
+  {m68k_op_adda_16_ai          , 0xf1f8, 0xd0d0, 12},
+  {m68k_op_adda_16_pi          , 0xf1f8, 0xd0d8, 12},
+  {m68k_op_adda_16_pd          , 0xf1f8, 0xd0e0, 14},
+  {m68k_op_adda_16_di          , 0xf1f8, 0xd0e8, 16},
+  {m68k_op_adda_16_ix          , 0xf1f8, 0xd0f0, 18},
+  {m68k_op_addx_8_rr           , 0xf1f8, 0xd100,  4},
+  {m68k_op_addx_8_mm           , 0xf1f8, 0xd108, 18},
+  {m68k_op_add_8_re_ai         , 0xf1f8, 0xd110, 12},
+  {m68k_op_add_8_re_pi         , 0xf1f8, 0xd118, 12},
+  {m68k_op_add_8_re_pd         , 0xf1f8, 0xd120, 14},
+  {m68k_op_add_8_re_di         , 0xf1f8, 0xd128, 16},
+  {m68k_op_add_8_re_ix         , 0xf1f8, 0xd130, 18},
+  {m68k_op_addx_16_rr          , 0xf1f8, 0xd140,  4},
+  {m68k_op_addx_16_mm          , 0xf1f8, 0xd148, 18},
+  {m68k_op_add_16_re_ai        , 0xf1f8, 0xd150, 12},
+  {m68k_op_add_16_re_pi        , 0xf1f8, 0xd158, 12},
+  {m68k_op_add_16_re_pd        , 0xf1f8, 0xd160, 14},
+  {m68k_op_add_16_re_di        , 0xf1f8, 0xd168, 16},
+  {m68k_op_add_16_re_ix        , 0xf1f8, 0xd170, 18},
+  {m68k_op_addx_32_rr          , 0xf1f8, 0xd180,  8},
+  {m68k_op_addx_32_mm          , 0xf1f8, 0xd188, 30},
+  {m68k_op_add_32_re_ai        , 0xf1f8, 0xd190, 20},
+  {m68k_op_add_32_re_pi        , 0xf1f8, 0xd198, 20},
+  {m68k_op_add_32_re_pd        , 0xf1f8, 0xd1a0, 22},
+  {m68k_op_add_32_re_di        , 0xf1f8, 0xd1a8, 24},
+  {m68k_op_add_32_re_ix        , 0xf1f8, 0xd1b0, 26},
+  {m68k_op_adda_32_d           , 0xf1f8, 0xd1c0,  8},
+  {m68k_op_adda_32_a           , 0xf1f8, 0xd1c8,  8},
+  {m68k_op_adda_32_ai          , 0xf1f8, 0xd1d0, 14},
+  {m68k_op_adda_32_pi          , 0xf1f8, 0xd1d8, 14},
+  {m68k_op_adda_32_pd          , 0xf1f8, 0xd1e0, 16},
+  {m68k_op_adda_32_di          , 0xf1f8, 0xd1e8, 18},
+  {m68k_op_adda_32_ix          , 0xf1f8, 0xd1f0, 20},
+  {m68k_op_asr_8_s             , 0xf1f8, 0xe000,  6},
+  {m68k_op_lsr_8_s             , 0xf1f8, 0xe008,  6},
+  {m68k_op_roxr_8_s            , 0xf1f8, 0xe010,  6},
+  {m68k_op_ror_8_s             , 0xf1f8, 0xe018,  6},
+  {m68k_op_asr_8_r             , 0xf1f8, 0xe020,  6},
+  {m68k_op_lsr_8_r             , 0xf1f8, 0xe028,  6},
+  {m68k_op_roxr_8_r            , 0xf1f8, 0xe030,  6},
+  {m68k_op_ror_8_r             , 0xf1f8, 0xe038,  6},
+  {m68k_op_asr_16_s            , 0xf1f8, 0xe040,  6},
+  {m68k_op_lsr_16_s            , 0xf1f8, 0xe048,  6},
+  {m68k_op_roxr_16_s           , 0xf1f8, 0xe050,  6},
+  {m68k_op_ror_16_s            , 0xf1f8, 0xe058,  6},
+  {m68k_op_asr_16_r            , 0xf1f8, 0xe060,  6},
+  {m68k_op_lsr_16_r            , 0xf1f8, 0xe068,  6},
+  {m68k_op_roxr_16_r           , 0xf1f8, 0xe070,  6},
+  {m68k_op_ror_16_r            , 0xf1f8, 0xe078,  6},
+  {m68k_op_asr_32_s            , 0xf1f8, 0xe080,  8},
+  {m68k_op_lsr_32_s            , 0xf1f8, 0xe088,  8},
+  {m68k_op_roxr_32_s           , 0xf1f8, 0xe090,  8},
+  {m68k_op_ror_32_s            , 0xf1f8, 0xe098,  8},
+  {m68k_op_asr_32_r            , 0xf1f8, 0xe0a0,  8},
+  {m68k_op_lsr_32_r            , 0xf1f8, 0xe0a8,  8},
+  {m68k_op_roxr_32_r           , 0xf1f8, 0xe0b0,  8},
+  {m68k_op_ror_32_r            , 0xf1f8, 0xe0b8,  8},
+  {m68k_op_asl_8_s             , 0xf1f8, 0xe100,  6},
+  {m68k_op_lsl_8_s             , 0xf1f8, 0xe108,  6},
+  {m68k_op_roxl_8_s            , 0xf1f8, 0xe110,  6},
+  {m68k_op_rol_8_s             , 0xf1f8, 0xe118,  6},
+  {m68k_op_asl_8_r             , 0xf1f8, 0xe120,  6},
+  {m68k_op_lsl_8_r             , 0xf1f8, 0xe128,  6},
+  {m68k_op_roxl_8_r            , 0xf1f8, 0xe130,  6},
+  {m68k_op_rol_8_r             , 0xf1f8, 0xe138,  6},
+  {m68k_op_asl_16_s            , 0xf1f8, 0xe140,  6},
+  {m68k_op_lsl_16_s            , 0xf1f8, 0xe148,  6},
+  {m68k_op_roxl_16_s           , 0xf1f8, 0xe150,  6},
+  {m68k_op_rol_16_s            , 0xf1f8, 0xe158,  6},
+  {m68k_op_asl_16_r            , 0xf1f8, 0xe160,  6},
+  {m68k_op_lsl_16_r            , 0xf1f8, 0xe168,  6},
+  {m68k_op_roxl_16_r           , 0xf1f8, 0xe170,  6},
+  {m68k_op_rol_16_r            , 0xf1f8, 0xe178,  6},
+  {m68k_op_asl_32_s            , 0xf1f8, 0xe180,  8},
+  {m68k_op_lsl_32_s            , 0xf1f8, 0xe188,  8},
+  {m68k_op_roxl_32_s           , 0xf1f8, 0xe190,  8},
+  {m68k_op_rol_32_s            , 0xf1f8, 0xe198,  8},
+  {m68k_op_asl_32_r            , 0xf1f8, 0xe1a0,  8},
+  {m68k_op_lsl_32_r            , 0xf1f8, 0xe1a8,  8},
+  {m68k_op_roxl_32_r           , 0xf1f8, 0xe1b0,  8},
+  {m68k_op_rol_32_r            , 0xf1f8, 0xe1b8,  8},
+  {m68k_op_trap                , 0xfff0, 0x4e40,  4},
+  {m68k_op_btst_8_r_pi7        , 0xf1ff, 0x011f,  8},
+  {m68k_op_btst_8_r_pd7        , 0xf1ff, 0x0127, 10},
+  {m68k_op_btst_8_r_aw         , 0xf1ff, 0x0138, 12},
+  {m68k_op_btst_8_r_al         , 0xf1ff, 0x0139, 16},
+  {m68k_op_btst_8_r_pcdi       , 0xf1ff, 0x013a, 12},
+  {m68k_op_btst_8_r_pcix       , 0xf1ff, 0x013b, 14},
+  {m68k_op_btst_8_r_i          , 0xf1ff, 0x013c, 10},
+  {m68k_op_bchg_8_r_pi7        , 0xf1ff, 0x015f, 12},
+  {m68k_op_bchg_8_r_pd7        , 0xf1ff, 0x0167, 14},
+  {m68k_op_bchg_8_r_aw         , 0xf1ff, 0x0178, 16},
+  {m68k_op_bchg_8_r_al         , 0xf1ff, 0x0179, 20},
+  {m68k_op_bclr_8_r_pi7        , 0xf1ff, 0x019f, 12},
+  {m68k_op_bclr_8_r_pd7        , 0xf1ff, 0x01a7, 14},
+  {m68k_op_bclr_8_r_aw         , 0xf1ff, 0x01b8, 16},
+  {m68k_op_bclr_8_r_al         , 0xf1ff, 0x01b9, 20},
+  {m68k_op_bset_8_r_pi7        , 0xf1ff, 0x01df, 12},
+  {m68k_op_bset_8_r_pd7        , 0xf1ff, 0x01e7, 14},
+  {m68k_op_bset_8_r_aw         , 0xf1ff, 0x01f8, 16},
+  {m68k_op_bset_8_r_al         , 0xf1ff, 0x01f9, 20},
+  {m68k_op_move_8_d_pi7        , 0xf1ff, 0x101f,  8},
+  {m68k_op_move_8_d_pd7        , 0xf1ff, 0x1027, 10},
+  {m68k_op_move_8_d_aw         , 0xf1ff, 0x1038, 12},
+  {m68k_op_move_8_d_al         , 0xf1ff, 0x1039, 16},
+  {m68k_op_move_8_d_pcdi       , 0xf1ff, 0x103a, 12},
+  {m68k_op_move_8_d_pcix       , 0xf1ff, 0x103b, 14},
+  {m68k_op_move_8_d_i          , 0xf1ff, 0x103c,  8},
+  {m68k_op_move_8_ai_pi7       , 0xf1ff, 0x109f, 12},
+  {m68k_op_move_8_ai_pd7       , 0xf1ff, 0x10a7, 14},
+  {m68k_op_move_8_ai_aw        , 0xf1ff, 0x10b8, 16},
+  {m68k_op_move_8_ai_al        , 0xf1ff, 0x10b9, 20},
+  {m68k_op_move_8_ai_pcdi      , 0xf1ff, 0x10ba, 16},
+  {m68k_op_move_8_ai_pcix      , 0xf1ff, 0x10bb, 18},
+  {m68k_op_move_8_ai_i         , 0xf1ff, 0x10bc, 12},
+  {m68k_op_move_8_pi_pi7       , 0xf1ff, 0x10df, 12},
+  {m68k_op_move_8_pi_pd7       , 0xf1ff, 0x10e7, 14},
+  {m68k_op_move_8_pi_aw        , 0xf1ff, 0x10f8, 16},
+  {m68k_op_move_8_pi_al        , 0xf1ff, 0x10f9, 20},
+  {m68k_op_move_8_pi_pcdi      , 0xf1ff, 0x10fa, 16},
+  {m68k_op_move_8_pi_pcix      , 0xf1ff, 0x10fb, 18},
+  {m68k_op_move_8_pi_i         , 0xf1ff, 0x10fc, 12},
+  {m68k_op_move_8_pd_pi7       , 0xf1ff, 0x111f, 12},
+  {m68k_op_move_8_pd_pd7       , 0xf1ff, 0x1127, 14},
+  {m68k_op_move_8_pd_aw        , 0xf1ff, 0x1138, 16},
+  {m68k_op_move_8_pd_al        , 0xf1ff, 0x1139, 20},
+  {m68k_op_move_8_pd_pcdi      , 0xf1ff, 0x113a, 16},
+  {m68k_op_move_8_pd_pcix      , 0xf1ff, 0x113b, 18},
+  {m68k_op_move_8_pd_i         , 0xf1ff, 0x113c, 12},
+  {m68k_op_move_8_di_pi7       , 0xf1ff, 0x115f, 16},
+  {m68k_op_move_8_di_pd7       , 0xf1ff, 0x1167, 18},
+  {m68k_op_move_8_di_aw        , 0xf1ff, 0x1178, 20},
+  {m68k_op_move_8_di_al        , 0xf1ff, 0x1179, 24},
+  {m68k_op_move_8_di_pcdi      , 0xf1ff, 0x117a, 20},
+  {m68k_op_move_8_di_pcix      , 0xf1ff, 0x117b, 22},
+  {m68k_op_move_8_di_i         , 0xf1ff, 0x117c, 16},
+  {m68k_op_move_8_ix_pi7       , 0xf1ff, 0x119f, 18},
+  {m68k_op_move_8_ix_pd7       , 0xf1ff, 0x11a7, 20},
+  {m68k_op_move_8_ix_aw        , 0xf1ff, 0x11b8, 22},
+  {m68k_op_move_8_ix_al        , 0xf1ff, 0x11b9, 26},
+  {m68k_op_move_8_ix_pcdi      , 0xf1ff, 0x11ba, 22},
+  {m68k_op_move_8_ix_pcix      , 0xf1ff, 0x11bb, 24},
+  {m68k_op_move_8_ix_i         , 0xf1ff, 0x11bc, 18},
+  {m68k_op_move_32_d_aw        , 0xf1ff, 0x2038, 16},
+  {m68k_op_move_32_d_al        , 0xf1ff, 0x2039, 20},
+  {m68k_op_move_32_d_pcdi      , 0xf1ff, 0x203a, 16},
+  {m68k_op_move_32_d_pcix      , 0xf1ff, 0x203b, 18},
+  {m68k_op_move_32_d_i         , 0xf1ff, 0x203c, 12},
+  {m68k_op_movea_32_aw         , 0xf1ff, 0x2078, 16},
+  {m68k_op_movea_32_al         , 0xf1ff, 0x2079, 20},
+  {m68k_op_movea_32_pcdi       , 0xf1ff, 0x207a, 16},
+  {m68k_op_movea_32_pcix       , 0xf1ff, 0x207b, 18},
+  {m68k_op_movea_32_i          , 0xf1ff, 0x207c, 12},
+  {m68k_op_move_32_ai_aw       , 0xf1ff, 0x20b8, 24},
+  {m68k_op_move_32_ai_al       , 0xf1ff, 0x20b9, 28},
+  {m68k_op_move_32_ai_pcdi     , 0xf1ff, 0x20ba, 24},
+  {m68k_op_move_32_ai_pcix     , 0xf1ff, 0x20bb, 26},
+  {m68k_op_move_32_ai_i        , 0xf1ff, 0x20bc, 20},
+  {m68k_op_move_32_pi_aw       , 0xf1ff, 0x20f8, 24},
+  {m68k_op_move_32_pi_al       , 0xf1ff, 0x20f9, 28},
+  {m68k_op_move_32_pi_pcdi     , 0xf1ff, 0x20fa, 24},
+  {m68k_op_move_32_pi_pcix     , 0xf1ff, 0x20fb, 26},
+  {m68k_op_move_32_pi_i        , 0xf1ff, 0x20fc, 20},
+  {m68k_op_move_32_pd_aw       , 0xf1ff, 0x2138, 24},
+  {m68k_op_move_32_pd_al       , 0xf1ff, 0x2139, 28},
+  {m68k_op_move_32_pd_pcdi     , 0xf1ff, 0x213a, 24},
+  {m68k_op_move_32_pd_pcix     , 0xf1ff, 0x213b, 26},
+  {m68k_op_move_32_pd_i        , 0xf1ff, 0x213c, 20},
+  {m68k_op_move_32_di_aw       , 0xf1ff, 0x2178, 28},
+  {m68k_op_move_32_di_al       , 0xf1ff, 0x2179, 32},
+  {m68k_op_move_32_di_pcdi     , 0xf1ff, 0x217a, 28},
+  {m68k_op_move_32_di_pcix     , 0xf1ff, 0x217b, 30},
+  {m68k_op_move_32_di_i        , 0xf1ff, 0x217c, 24},
+  {m68k_op_move_32_ix_aw       , 0xf1ff, 0x21b8, 30},
+  {m68k_op_move_32_ix_al       , 0xf1ff, 0x21b9, 34},
+  {m68k_op_move_32_ix_pcdi     , 0xf1ff, 0x21ba, 30},
+  {m68k_op_move_32_ix_pcix     , 0xf1ff, 0x21bb, 32},
+  {m68k_op_move_32_ix_i        , 0xf1ff, 0x21bc, 26},
+  {m68k_op_move_16_d_aw        , 0xf1ff, 0x3038, 12},
+  {m68k_op_move_16_d_al        , 0xf1ff, 0x3039, 16},
+  {m68k_op_move_16_d_pcdi      , 0xf1ff, 0x303a, 12},
+  {m68k_op_move_16_d_pcix      , 0xf1ff, 0x303b, 14},
+  {m68k_op_move_16_d_i         , 0xf1ff, 0x303c,  8},
+  {m68k_op_movea_16_aw         , 0xf1ff, 0x3078, 12},
+  {m68k_op_movea_16_al         , 0xf1ff, 0x3079, 16},
+  {m68k_op_movea_16_pcdi       , 0xf1ff, 0x307a, 12},
+  {m68k_op_movea_16_pcix       , 0xf1ff, 0x307b, 14},
+  {m68k_op_movea_16_i          , 0xf1ff, 0x307c,  8},
+  {m68k_op_move_16_ai_aw       , 0xf1ff, 0x30b8, 16},
+  {m68k_op_move_16_ai_al       , 0xf1ff, 0x30b9, 20},
+  {m68k_op_move_16_ai_pcdi     , 0xf1ff, 0x30ba, 16},
+  {m68k_op_move_16_ai_pcix     , 0xf1ff, 0x30bb, 18},
+  {m68k_op_move_16_ai_i        , 0xf1ff, 0x30bc, 12},
+  {m68k_op_move_16_pi_aw       , 0xf1ff, 0x30f8, 16},
+  {m68k_op_move_16_pi_al       , 0xf1ff, 0x30f9, 20},
+  {m68k_op_move_16_pi_pcdi     , 0xf1ff, 0x30fa, 16},
+  {m68k_op_move_16_pi_pcix     , 0xf1ff, 0x30fb, 18},
+  {m68k_op_move_16_pi_i        , 0xf1ff, 0x30fc, 12},
+  {m68k_op_move_16_pd_aw       , 0xf1ff, 0x3138, 16},
+  {m68k_op_move_16_pd_al       , 0xf1ff, 0x3139, 20},
+  {m68k_op_move_16_pd_pcdi     , 0xf1ff, 0x313a, 16},
+  {m68k_op_move_16_pd_pcix     , 0xf1ff, 0x313b, 18},
+  {m68k_op_move_16_pd_i        , 0xf1ff, 0x313c, 12},
+  {m68k_op_move_16_di_aw       , 0xf1ff, 0x3178, 20},
+  {m68k_op_move_16_di_al       , 0xf1ff, 0x3179, 24},
+  {m68k_op_move_16_di_pcdi     , 0xf1ff, 0x317a, 20},
+  {m68k_op_move_16_di_pcix     , 0xf1ff, 0x317b, 22},
+  {m68k_op_move_16_di_i        , 0xf1ff, 0x317c, 16},
+  {m68k_op_move_16_ix_aw       , 0xf1ff, 0x31b8, 22},
+  {m68k_op_move_16_ix_al       , 0xf1ff, 0x31b9, 26},
+  {m68k_op_move_16_ix_pcdi     , 0xf1ff, 0x31ba, 22},
+  {m68k_op_move_16_ix_pcix     , 0xf1ff, 0x31bb, 24},
+  {m68k_op_move_16_ix_i        , 0xf1ff, 0x31bc, 18},
+  {m68k_op_chk_16_aw           , 0xf1ff, 0x41b8, 18},
+  {m68k_op_chk_16_al           , 0xf1ff, 0x41b9, 22},
+  {m68k_op_chk_16_pcdi         , 0xf1ff, 0x41ba, 18},
+  {m68k_op_chk_16_pcix         , 0xf1ff, 0x41bb, 20},
+  {m68k_op_chk_16_i            , 0xf1ff, 0x41bc, 14},
+  {m68k_op_lea_32_aw           , 0xf1ff, 0x41f8,  8},
+  {m68k_op_lea_32_al           , 0xf1ff, 0x41f9, 12},
+  {m68k_op_lea_32_pcdi         , 0xf1ff, 0x41fa,  8},
+  {m68k_op_lea_32_pcix         , 0xf1ff, 0x41fb, 12},
+  {m68k_op_addq_8_pi7          , 0xf1ff, 0x501f, 12},
+  {m68k_op_addq_8_pd7          , 0xf1ff, 0x5027, 14},
+  {m68k_op_addq_8_aw           , 0xf1ff, 0x5038, 16},
+  {m68k_op_addq_8_al           , 0xf1ff, 0x5039, 20},
+  {m68k_op_addq_16_aw          , 0xf1ff, 0x5078, 16},
+  {m68k_op_addq_16_al          , 0xf1ff, 0x5079, 20},
+  {m68k_op_addq_32_aw          , 0xf1ff, 0x50b8, 24},
+  {m68k_op_addq_32_al          , 0xf1ff, 0x50b9, 28},
+  {m68k_op_subq_8_pi7          , 0xf1ff, 0x511f, 12},
+  {m68k_op_subq_8_pd7          , 0xf1ff, 0x5127, 14},
+  {m68k_op_subq_8_aw           , 0xf1ff, 0x5138, 16},
+  {m68k_op_subq_8_al           , 0xf1ff, 0x5139, 20},
+  {m68k_op_subq_16_aw          , 0xf1ff, 0x5178, 16},
+  {m68k_op_subq_16_al          , 0xf1ff, 0x5179, 20},
+  {m68k_op_subq_32_aw          , 0xf1ff, 0x51b8, 24},
+  {m68k_op_subq_32_al          , 0xf1ff, 0x51b9, 28},
+  {m68k_op_or_8_er_pi7         , 0xf1ff, 0x801f,  8},
+  {m68k_op_or_8_er_pd7         , 0xf1ff, 0x8027, 10},
+  {m68k_op_or_8_er_aw          , 0xf1ff, 0x8038, 12},
+  {m68k_op_or_8_er_al          , 0xf1ff, 0x8039, 16},
+  {m68k_op_or_8_er_pcdi        , 0xf1ff, 0x803a, 12},
+  {m68k_op_or_8_er_pcix        , 0xf1ff, 0x803b, 14},
+  {m68k_op_or_8_er_i           , 0xf1ff, 0x803c,  8},
+  {m68k_op_or_16_er_aw         , 0xf1ff, 0x8078, 12},
+  {m68k_op_or_16_er_al         , 0xf1ff, 0x8079, 16},
+  {m68k_op_or_16_er_pcdi       , 0xf1ff, 0x807a, 12},
+  {m68k_op_or_16_er_pcix       , 0xf1ff, 0x807b, 14},
+  {m68k_op_or_16_er_i          , 0xf1ff, 0x807c,  8},
+  {m68k_op_or_32_er_aw         , 0xf1ff, 0x80b8, 18},
+  {m68k_op_or_32_er_al         , 0xf1ff, 0x80b9, 22},
+  {m68k_op_or_32_er_pcdi       , 0xf1ff, 0x80ba, 18},
+  {m68k_op_or_32_er_pcix       , 0xf1ff, 0x80bb, 20},
+  {m68k_op_or_32_er_i          , 0xf1ff, 0x80bc, 16},
+  {m68k_op_divu_16_aw          , 0xf1ff, 0x80f8,  8},
+  {m68k_op_divu_16_al          , 0xf1ff, 0x80f9, 12},
+  {m68k_op_divu_16_pcdi        , 0xf1ff, 0x80fa,  8},
+  {m68k_op_divu_16_pcix        , 0xf1ff, 0x80fb, 10},
+  {m68k_op_divu_16_i           , 0xf1ff, 0x80fc,  4},
+  {m68k_op_sbcd_8_mm_ay7       , 0xf1ff, 0x810f, 18},
+  {m68k_op_or_8_re_pi7         , 0xf1ff, 0x811f, 12},
+  {m68k_op_or_8_re_pd7         , 0xf1ff, 0x8127, 14},
+  {m68k_op_or_8_re_aw          , 0xf1ff, 0x8138, 16},
+  {m68k_op_or_8_re_al          , 0xf1ff, 0x8139, 20},
+  {m68k_op_or_16_re_aw         , 0xf1ff, 0x8178, 16},
+  {m68k_op_or_16_re_al         , 0xf1ff, 0x8179, 20},
+  {m68k_op_or_32_re_aw         , 0xf1ff, 0x81b8, 24},
+  {m68k_op_or_32_re_al         , 0xf1ff, 0x81b9, 28},
+  {m68k_op_divs_16_aw          , 0xf1ff, 0x81f8,  8},
+  {m68k_op_divs_16_al          , 0xf1ff, 0x81f9, 12},
+  {m68k_op_divs_16_pcdi        , 0xf1ff, 0x81fa,  8},
+  {m68k_op_divs_16_pcix        , 0xf1ff, 0x81fb, 10},
+  {m68k_op_divs_16_i           , 0xf1ff, 0x81fc,  4},
+  {m68k_op_sub_8_er_pi7        , 0xf1ff, 0x901f,  8},
+  {m68k_op_sub_8_er_pd7        , 0xf1ff, 0x9027, 10},
+  {m68k_op_sub_8_er_aw         , 0xf1ff, 0x9038, 12},
+  {m68k_op_sub_8_er_al         , 0xf1ff, 0x9039, 16},
+  {m68k_op_sub_8_er_pcdi       , 0xf1ff, 0x903a, 12},
+  {m68k_op_sub_8_er_pcix       , 0xf1ff, 0x903b, 14},
+  {m68k_op_sub_8_er_i          , 0xf1ff, 0x903c,  8},
+  {m68k_op_sub_16_er_aw        , 0xf1ff, 0x9078, 12},
+  {m68k_op_sub_16_er_al        , 0xf1ff, 0x9079, 16},
+  {m68k_op_sub_16_er_pcdi      , 0xf1ff, 0x907a, 12},
+  {m68k_op_sub_16_er_pcix      , 0xf1ff, 0x907b, 14},
+  {m68k_op_sub_16_er_i         , 0xf1ff, 0x907c,  8},
+  {m68k_op_sub_32_er_aw        , 0xf1ff, 0x90b8, 18},
+  {m68k_op_sub_32_er_al        , 0xf1ff, 0x90b9, 22},
+  {m68k_op_sub_32_er_pcdi      , 0xf1ff, 0x90ba, 18},
+  {m68k_op_sub_32_er_pcix      , 0xf1ff, 0x90bb, 20},
+  {m68k_op_sub_32_er_i         , 0xf1ff, 0x90bc, 16},
+  {m68k_op_suba_16_aw          , 0xf1ff, 0x90f8, 16},
+  {m68k_op_suba_16_al          , 0xf1ff, 0x90f9, 20},
+  {m68k_op_suba_16_pcdi        , 0xf1ff, 0x90fa, 16},
+  {m68k_op_suba_16_pcix        , 0xf1ff, 0x90fb, 18},
+  {m68k_op_suba_16_i           , 0xf1ff, 0x90fc, 12},
+  {m68k_op_subx_8_mm_ay7       , 0xf1ff, 0x910f, 18},
+  {m68k_op_sub_8_re_pi7        , 0xf1ff, 0x911f, 12},
+  {m68k_op_sub_8_re_pd7        , 0xf1ff, 0x9127, 14},
+  {m68k_op_sub_8_re_aw         , 0xf1ff, 0x9138, 16},
+  {m68k_op_sub_8_re_al         , 0xf1ff, 0x9139, 20},
+  {m68k_op_sub_16_re_aw        , 0xf1ff, 0x9178, 16},
+  {m68k_op_sub_16_re_al        , 0xf1ff, 0x9179, 20},
+  {m68k_op_sub_32_re_aw        , 0xf1ff, 0x91b8, 24},
+  {m68k_op_sub_32_re_al        , 0xf1ff, 0x91b9, 28},
+  {m68k_op_suba_32_aw          , 0xf1ff, 0x91f8, 18},
+  {m68k_op_suba_32_al          , 0xf1ff, 0x91f9, 22},
+  {m68k_op_suba_32_pcdi        , 0xf1ff, 0x91fa, 18},
+  {m68k_op_suba_32_pcix        , 0xf1ff, 0x91fb, 20},
+  {m68k_op_suba_32_i           , 0xf1ff, 0x91fc, 16},
+  {m68k_op_cmp_8_pi7           , 0xf1ff, 0xb01f,  8},
+  {m68k_op_cmp_8_pd7           , 0xf1ff, 0xb027, 10},
+  {m68k_op_cmp_8_aw            , 0xf1ff, 0xb038, 12},
+  {m68k_op_cmp_8_al            , 0xf1ff, 0xb039, 16},
+  {m68k_op_cmp_8_pcdi          , 0xf1ff, 0xb03a, 12},
+  {m68k_op_cmp_8_pcix          , 0xf1ff, 0xb03b, 14},
+  {m68k_op_cmp_8_i             , 0xf1ff, 0xb03c,  8},
+  {m68k_op_cmp_16_aw           , 0xf1ff, 0xb078, 12},
+  {m68k_op_cmp_16_al           , 0xf1ff, 0xb079, 16},
+  {m68k_op_cmp_16_pcdi         , 0xf1ff, 0xb07a, 12},
+  {m68k_op_cmp_16_pcix         , 0xf1ff, 0xb07b, 14},
+  {m68k_op_cmp_16_i            , 0xf1ff, 0xb07c,  8},
+  {m68k_op_cmp_32_aw           , 0xf1ff, 0xb0b8, 18},
+  {m68k_op_cmp_32_al           , 0xf1ff, 0xb0b9, 22},
+  {m68k_op_cmp_32_pcdi         , 0xf1ff, 0xb0ba, 18},
+  {m68k_op_cmp_32_pcix         , 0xf1ff, 0xb0bb, 20},
+  {m68k_op_cmp_32_i            , 0xf1ff, 0xb0bc, 14},
+  {m68k_op_cmpa_16_aw          , 0xf1ff, 0xb0f8, 14},
+  {m68k_op_cmpa_16_al          , 0xf1ff, 0xb0f9, 18},
+  {m68k_op_cmpa_16_pcdi        , 0xf1ff, 0xb0fa, 14},
+  {m68k_op_cmpa_16_pcix        , 0xf1ff, 0xb0fb, 16},
+  {m68k_op_cmpa_16_i           , 0xf1ff, 0xb0fc, 10},
+  {m68k_op_cmpm_8_ay7          , 0xf1ff, 0xb10f, 12},
+  {m68k_op_eor_8_pi7           , 0xf1ff, 0xb11f, 12},
+  {m68k_op_eor_8_pd7           , 0xf1ff, 0xb127, 14},
+  {m68k_op_eor_8_aw            , 0xf1ff, 0xb138, 16},
+  {m68k_op_eor_8_al            , 0xf1ff, 0xb139, 20},
+  {m68k_op_eor_16_aw           , 0xf1ff, 0xb178, 16},
+  {m68k_op_eor_16_al           , 0xf1ff, 0xb179, 20},
+  {m68k_op_eor_32_aw           , 0xf1ff, 0xb1b8, 24},
+  {m68k_op_eor_32_al           , 0xf1ff, 0xb1b9, 28},
+  {m68k_op_cmpa_32_aw          , 0xf1ff, 0xb1f8, 18},
+  {m68k_op_cmpa_32_al          , 0xf1ff, 0xb1f9, 22},
+  {m68k_op_cmpa_32_pcdi        , 0xf1ff, 0xb1fa, 18},
+  {m68k_op_cmpa_32_pcix        , 0xf1ff, 0xb1fb, 20},
+  {m68k_op_cmpa_32_i           , 0xf1ff, 0xb1fc, 14},
+  {m68k_op_and_8_er_pi7        , 0xf1ff, 0xc01f,  8},
+  {m68k_op_and_8_er_pd7        , 0xf1ff, 0xc027, 10},
+  {m68k_op_and_8_er_aw         , 0xf1ff, 0xc038, 12},
+  {m68k_op_and_8_er_al         , 0xf1ff, 0xc039, 16},
+  {m68k_op_and_8_er_pcdi       , 0xf1ff, 0xc03a, 12},
+  {m68k_op_and_8_er_pcix       , 0xf1ff, 0xc03b, 14},
+  {m68k_op_and_8_er_i          , 0xf1ff, 0xc03c,  8},
+  {m68k_op_and_16_er_aw        , 0xf1ff, 0xc078, 12},
+  {m68k_op_and_16_er_al        , 0xf1ff, 0xc079, 16},
+  {m68k_op_and_16_er_pcdi      , 0xf1ff, 0xc07a, 12},
+  {m68k_op_and_16_er_pcix      , 0xf1ff, 0xc07b, 14},
+  {m68k_op_and_16_er_i         , 0xf1ff, 0xc07c,  8},
+  {m68k_op_and_32_er_aw        , 0xf1ff, 0xc0b8, 18},
+  {m68k_op_and_32_er_al        , 0xf1ff, 0xc0b9, 22},
+  {m68k_op_and_32_er_pcdi      , 0xf1ff, 0xc0ba, 18},
+  {m68k_op_and_32_er_pcix      , 0xf1ff, 0xc0bb, 20},
+  {m68k_op_and_32_er_i         , 0xf1ff, 0xc0bc, 16},
+  {m68k_op_mulu_16_aw          , 0xf1ff, 0xc0f8,  8},
+  {m68k_op_mulu_16_al          , 0xf1ff, 0xc0f9, 12},
+  {m68k_op_mulu_16_pcdi        , 0xf1ff, 0xc0fa,  8},
+  {m68k_op_mulu_16_pcix        , 0xf1ff, 0xc0fb, 10},
+  {m68k_op_mulu_16_i           , 0xf1ff, 0xc0fc,  4},
+  {m68k_op_abcd_8_mm_ay7       , 0xf1ff, 0xc10f, 18},
+  {m68k_op_and_8_re_pi7        , 0xf1ff, 0xc11f, 12},
+  {m68k_op_and_8_re_pd7        , 0xf1ff, 0xc127, 14},
+  {m68k_op_and_8_re_aw         , 0xf1ff, 0xc138, 16},
+  {m68k_op_and_8_re_al         , 0xf1ff, 0xc139, 20},
+  {m68k_op_and_16_re_aw        , 0xf1ff, 0xc178, 16},
+  {m68k_op_and_16_re_al        , 0xf1ff, 0xc179, 20},
+  {m68k_op_and_32_re_aw        , 0xf1ff, 0xc1b8, 24},
+  {m68k_op_and_32_re_al        , 0xf1ff, 0xc1b9, 28},
+  {m68k_op_muls_16_aw          , 0xf1ff, 0xc1f8,  8},
+  {m68k_op_muls_16_al          , 0xf1ff, 0xc1f9, 12},
+  {m68k_op_muls_16_pcdi        , 0xf1ff, 0xc1fa,  8},
+  {m68k_op_muls_16_pcix        , 0xf1ff, 0xc1fb, 10},
+  {m68k_op_muls_16_i           , 0xf1ff, 0xc1fc,  4},
+  {m68k_op_add_8_er_pi7        , 0xf1ff, 0xd01f,  8},
+  {m68k_op_add_8_er_pd7        , 0xf1ff, 0xd027, 10},
+  {m68k_op_add_8_er_aw         , 0xf1ff, 0xd038, 12},
+  {m68k_op_add_8_er_al         , 0xf1ff, 0xd039, 16},
+  {m68k_op_add_8_er_pcdi       , 0xf1ff, 0xd03a, 12},
+  {m68k_op_add_8_er_pcix       , 0xf1ff, 0xd03b, 14},
+  {m68k_op_add_8_er_i          , 0xf1ff, 0xd03c,  8},
+  {m68k_op_add_16_er_aw        , 0xf1ff, 0xd078, 12},
+  {m68k_op_add_16_er_al        , 0xf1ff, 0xd079, 16},
+  {m68k_op_add_16_er_pcdi      , 0xf1ff, 0xd07a, 12},
+  {m68k_op_add_16_er_pcix      , 0xf1ff, 0xd07b, 14},
+  {m68k_op_add_16_er_i         , 0xf1ff, 0xd07c,  8},
+  {m68k_op_add_32_er_aw        , 0xf1ff, 0xd0b8, 18},
+  {m68k_op_add_32_er_al        , 0xf1ff, 0xd0b9, 22},
+  {m68k_op_add_32_er_pcdi      , 0xf1ff, 0xd0ba, 18},
+  {m68k_op_add_32_er_pcix      , 0xf1ff, 0xd0bb, 20},
+  {m68k_op_add_32_er_i         , 0xf1ff, 0xd0bc, 16},
+  {m68k_op_adda_16_aw          , 0xf1ff, 0xd0f8, 16},
+  {m68k_op_adda_16_al          , 0xf1ff, 0xd0f9, 20},
+  {m68k_op_adda_16_pcdi        , 0xf1ff, 0xd0fa, 16},
+  {m68k_op_adda_16_pcix        , 0xf1ff, 0xd0fb, 18},
+  {m68k_op_adda_16_i           , 0xf1ff, 0xd0fc, 12},
+  {m68k_op_addx_8_mm_ay7       , 0xf1ff, 0xd10f, 18},
+  {m68k_op_add_8_re_pi7        , 0xf1ff, 0xd11f, 12},
+  {m68k_op_add_8_re_pd7        , 0xf1ff, 0xd127, 14},
+  {m68k_op_add_8_re_aw         , 0xf1ff, 0xd138, 16},
+  {m68k_op_add_8_re_al         , 0xf1ff, 0xd139, 20},
+  {m68k_op_add_16_re_aw        , 0xf1ff, 0xd178, 16},
+  {m68k_op_add_16_re_al        , 0xf1ff, 0xd179, 20},
+  {m68k_op_add_32_re_aw        , 0xf1ff, 0xd1b8, 24},
+  {m68k_op_add_32_re_al        , 0xf1ff, 0xd1b9, 28},
+  {m68k_op_adda_32_aw          , 0xf1ff, 0xd1f8, 18},
+  {m68k_op_adda_32_al          , 0xf1ff, 0xd1f9, 22},
+  {m68k_op_adda_32_pcdi        , 0xf1ff, 0xd1fa, 18},
+  {m68k_op_adda_32_pcix        , 0xf1ff, 0xd1fb, 20},
+  {m68k_op_adda_32_i           , 0xf1ff, 0xd1fc, 16},
+  {m68k_op_ori_8_d             , 0xfff8, 0x0000,  8},
+  {m68k_op_ori_8_ai            , 0xfff8, 0x0010, 16},
+  {m68k_op_ori_8_pi            , 0xfff8, 0x0018, 16},
+  {m68k_op_ori_8_pd            , 0xfff8, 0x0020, 18},
+  {m68k_op_ori_8_di            , 0xfff8, 0x0028, 20},
+  {m68k_op_ori_8_ix            , 0xfff8, 0x0030, 22},
+  {m68k_op_ori_16_d            , 0xfff8, 0x0040,  8},
+  {m68k_op_ori_16_ai           , 0xfff8, 0x0050, 16},
+  {m68k_op_ori_16_pi           , 0xfff8, 0x0058, 16},
+  {m68k_op_ori_16_pd           , 0xfff8, 0x0060, 18},
+  {m68k_op_ori_16_di           , 0xfff8, 0x0068, 20},
+  {m68k_op_ori_16_ix           , 0xfff8, 0x0070, 22},
+  {m68k_op_ori_32_d            , 0xfff8, 0x0080, 16},
+  {m68k_op_ori_32_ai           , 0xfff8, 0x0090, 28},
+  {m68k_op_ori_32_pi           , 0xfff8, 0x0098, 28},
+  {m68k_op_ori_32_pd           , 0xfff8, 0x00a0, 30},
+  {m68k_op_ori_32_di           , 0xfff8, 0x00a8, 32},
+  {m68k_op_ori_32_ix           , 0xfff8, 0x00b0, 34},
+  {m68k_op_andi_8_d            , 0xfff8, 0x0200,  8},
+  {m68k_op_andi_8_ai           , 0xfff8, 0x0210, 16},
+  {m68k_op_andi_8_pi           , 0xfff8, 0x0218, 16},
+  {m68k_op_andi_8_pd           , 0xfff8, 0x0220, 18},
+  {m68k_op_andi_8_di           , 0xfff8, 0x0228, 20},
+  {m68k_op_andi_8_ix           , 0xfff8, 0x0230, 22},
+  {m68k_op_andi_16_d           , 0xfff8, 0x0240,  8},
+  {m68k_op_andi_16_ai          , 0xfff8, 0x0250, 16},
+  {m68k_op_andi_16_pi          , 0xfff8, 0x0258, 16},
+  {m68k_op_andi_16_pd          , 0xfff8, 0x0260, 18},
+  {m68k_op_andi_16_di          , 0xfff8, 0x0268, 20},
+  {m68k_op_andi_16_ix          , 0xfff8, 0x0270, 22},
+  {m68k_op_andi_32_d           , 0xfff8, 0x0280, 16}, /* see Yacht.txt */
+  {m68k_op_andi_32_ai          , 0xfff8, 0x0290, 28},
+  {m68k_op_andi_32_pi          , 0xfff8, 0x0298, 28},
+  {m68k_op_andi_32_pd          , 0xfff8, 0x02a0, 30},
+  {m68k_op_andi_32_di          , 0xfff8, 0x02a8, 32},
+  {m68k_op_andi_32_ix          , 0xfff8, 0x02b0, 34},
+  {m68k_op_subi_8_d            , 0xfff8, 0x0400,  8},
+  {m68k_op_subi_8_ai           , 0xfff8, 0x0410, 16},
+  {m68k_op_subi_8_pi           , 0xfff8, 0x0418, 16},
+  {m68k_op_subi_8_pd           , 0xfff8, 0x0420, 18},
+  {m68k_op_subi_8_di           , 0xfff8, 0x0428, 20},
+  {m68k_op_subi_8_ix           , 0xfff8, 0x0430, 22},
+  {m68k_op_subi_16_d           , 0xfff8, 0x0440,  8},
+  {m68k_op_subi_16_ai          , 0xfff8, 0x0450, 16},
+  {m68k_op_subi_16_pi          , 0xfff8, 0x0458, 16},
+  {m68k_op_subi_16_pd          , 0xfff8, 0x0460, 18},
+  {m68k_op_subi_16_di          , 0xfff8, 0x0468, 20},
+  {m68k_op_subi_16_ix          , 0xfff8, 0x0470, 22},
+  {m68k_op_subi_32_d           , 0xfff8, 0x0480, 16},
+  {m68k_op_subi_32_ai          , 0xfff8, 0x0490, 28},
+  {m68k_op_subi_32_pi          , 0xfff8, 0x0498, 28},
+  {m68k_op_subi_32_pd          , 0xfff8, 0x04a0, 30},
+  {m68k_op_subi_32_di          , 0xfff8, 0x04a8, 32},
+  {m68k_op_subi_32_ix          , 0xfff8, 0x04b0, 34},
+  {m68k_op_addi_8_d            , 0xfff8, 0x0600,  8},
+  {m68k_op_addi_8_ai           , 0xfff8, 0x0610, 16},
+  {m68k_op_addi_8_pi           , 0xfff8, 0x0618, 16},
+  {m68k_op_addi_8_pd           , 0xfff8, 0x0620, 18},
+  {m68k_op_addi_8_di           , 0xfff8, 0x0628, 20},
+  {m68k_op_addi_8_ix           , 0xfff8, 0x0630, 22},
+  {m68k_op_addi_16_d           , 0xfff8, 0x0640,  8},
+  {m68k_op_addi_16_ai          , 0xfff8, 0x0650, 16},
+  {m68k_op_addi_16_pi          , 0xfff8, 0x0658, 16},
+  {m68k_op_addi_16_pd          , 0xfff8, 0x0660, 18},
+  {m68k_op_addi_16_di          , 0xfff8, 0x0668, 20},
+  {m68k_op_addi_16_ix          , 0xfff8, 0x0670, 22},
+  {m68k_op_addi_32_d           , 0xfff8, 0x0680, 16},
+  {m68k_op_addi_32_ai          , 0xfff8, 0x0690, 28},
+  {m68k_op_addi_32_pi          , 0xfff8, 0x0698, 28},
+  {m68k_op_addi_32_pd          , 0xfff8, 0x06a0, 30},
+  {m68k_op_addi_32_di          , 0xfff8, 0x06a8, 32},
+  {m68k_op_addi_32_ix          , 0xfff8, 0x06b0, 34},
+  {m68k_op_btst_32_s_d         , 0xfff8, 0x0800, 10},
+  {m68k_op_btst_8_s_ai         , 0xfff8, 0x0810, 12},
+  {m68k_op_btst_8_s_pi         , 0xfff8, 0x0818, 12},
+  {m68k_op_btst_8_s_pd         , 0xfff8, 0x0820, 14},
+  {m68k_op_btst_8_s_di         , 0xfff8, 0x0828, 16},
+  {m68k_op_btst_8_s_ix         , 0xfff8, 0x0830, 18},
+  {m68k_op_bchg_32_s_d         , 0xfff8, 0x0840, 12},
+  {m68k_op_bchg_8_s_ai         , 0xfff8, 0x0850, 16},
+  {m68k_op_bchg_8_s_pi         , 0xfff8, 0x0858, 16},
+  {m68k_op_bchg_8_s_pd         , 0xfff8, 0x0860, 18},
+  {m68k_op_bchg_8_s_di         , 0xfff8, 0x0868, 20},
+  {m68k_op_bchg_8_s_ix         , 0xfff8, 0x0870, 22},
+  {m68k_op_bclr_32_s_d         , 0xfff8, 0x0880, 14},
+  {m68k_op_bclr_8_s_ai         , 0xfff8, 0x0890, 16},
+  {m68k_op_bclr_8_s_pi         , 0xfff8, 0x0898, 16},
+  {m68k_op_bclr_8_s_pd         , 0xfff8, 0x08a0, 18},
+  {m68k_op_bclr_8_s_di         , 0xfff8, 0x08a8, 20},
+  {m68k_op_bclr_8_s_ix         , 0xfff8, 0x08b0, 22},
+  {m68k_op_bset_32_s_d         , 0xfff8, 0x08c0, 12},
+  {m68k_op_bset_8_s_ai         , 0xfff8, 0x08d0, 16},
+  {m68k_op_bset_8_s_pi         , 0xfff8, 0x08d8, 16},
+  {m68k_op_bset_8_s_pd         , 0xfff8, 0x08e0, 18},
+  {m68k_op_bset_8_s_di         , 0xfff8, 0x08e8, 20},
+  {m68k_op_bset_8_s_ix         , 0xfff8, 0x08f0, 22},
+  {m68k_op_eori_8_d            , 0xfff8, 0x0a00,  8},
+  {m68k_op_eori_8_ai           , 0xfff8, 0x0a10, 16},
+  {m68k_op_eori_8_pi           , 0xfff8, 0x0a18, 16},
+  {m68k_op_eori_8_pd           , 0xfff8, 0x0a20, 18},
+  {m68k_op_eori_8_di           , 0xfff8, 0x0a28, 20},
+  {m68k_op_eori_8_ix           , 0xfff8, 0x0a30, 22},
+  {m68k_op_eori_16_d           , 0xfff8, 0x0a40,  8},
+  {m68k_op_eori_16_ai          , 0xfff8, 0x0a50, 16},
+  {m68k_op_eori_16_pi          , 0xfff8, 0x0a58, 16},
+  {m68k_op_eori_16_pd          , 0xfff8, 0x0a60, 18},
+  {m68k_op_eori_16_di          , 0xfff8, 0x0a68, 20},
+  {m68k_op_eori_16_ix          , 0xfff8, 0x0a70, 22},
+  {m68k_op_eori_32_d           , 0xfff8, 0x0a80, 16},
+  {m68k_op_eori_32_ai          , 0xfff8, 0x0a90, 28},
+  {m68k_op_eori_32_pi          , 0xfff8, 0x0a98, 28},
+  {m68k_op_eori_32_pd          , 0xfff8, 0x0aa0, 30},
+  {m68k_op_eori_32_di          , 0xfff8, 0x0aa8, 32},
+  {m68k_op_eori_32_ix          , 0xfff8, 0x0ab0, 34},
+  {m68k_op_cmpi_8_d            , 0xfff8, 0x0c00,  8},
+  {m68k_op_cmpi_8_ai           , 0xfff8, 0x0c10, 12},
+  {m68k_op_cmpi_8_pi           , 0xfff8, 0x0c18, 12},
+  {m68k_op_cmpi_8_pd           , 0xfff8, 0x0c20, 14},
+  {m68k_op_cmpi_8_di           , 0xfff8, 0x0c28, 16},
+  {m68k_op_cmpi_8_ix           , 0xfff8, 0x0c30, 18},
+  {m68k_op_cmpi_16_d           , 0xfff8, 0x0c40,  8},
+  {m68k_op_cmpi_16_ai          , 0xfff8, 0x0c50, 12},
+  {m68k_op_cmpi_16_pi          , 0xfff8, 0x0c58, 12},
+  {m68k_op_cmpi_16_pd          , 0xfff8, 0x0c60, 14},
+  {m68k_op_cmpi_16_di          , 0xfff8, 0x0c68, 16},
+  {m68k_op_cmpi_16_ix          , 0xfff8, 0x0c70, 18},
+  {m68k_op_cmpi_32_d           , 0xfff8, 0x0c80, 14},
+  {m68k_op_cmpi_32_ai          , 0xfff8, 0x0c90, 20},
+  {m68k_op_cmpi_32_pi          , 0xfff8, 0x0c98, 20},
+  {m68k_op_cmpi_32_pd          , 0xfff8, 0x0ca0, 22},
+  {m68k_op_cmpi_32_di          , 0xfff8, 0x0ca8, 24},
+  {m68k_op_cmpi_32_ix          , 0xfff8, 0x0cb0, 26},
+  {m68k_op_move_8_aw_d         , 0xfff8, 0x11c0, 12},
+  {m68k_op_move_8_aw_ai        , 0xfff8, 0x11d0, 16},
+  {m68k_op_move_8_aw_pi        , 0xfff8, 0x11d8, 16},
+  {m68k_op_move_8_aw_pd        , 0xfff8, 0x11e0, 18},
+  {m68k_op_move_8_aw_di        , 0xfff8, 0x11e8, 20},
+  {m68k_op_move_8_aw_ix        , 0xfff8, 0x11f0, 22},
+  {m68k_op_move_8_al_d         , 0xfff8, 0x13c0, 16},
+  {m68k_op_move_8_al_ai        , 0xfff8, 0x13d0, 20},
+  {m68k_op_move_8_al_pi        , 0xfff8, 0x13d8, 20},
+  {m68k_op_move_8_al_pd        , 0xfff8, 0x13e0, 22},
+  {m68k_op_move_8_al_di        , 0xfff8, 0x13e8, 24},
+  {m68k_op_move_8_al_ix        , 0xfff8, 0x13f0, 26},
+  {m68k_op_move_8_pi7_d        , 0xfff8, 0x1ec0,  8},
+  {m68k_op_move_8_pi7_ai       , 0xfff8, 0x1ed0, 12},
+  {m68k_op_move_8_pi7_pi       , 0xfff8, 0x1ed8, 12},
+  {m68k_op_move_8_pi7_pd       , 0xfff8, 0x1ee0, 14},
+  {m68k_op_move_8_pi7_di       , 0xfff8, 0x1ee8, 16},
+  {m68k_op_move_8_pi7_ix       , 0xfff8, 0x1ef0, 18},
+  {m68k_op_move_8_pd7_d        , 0xfff8, 0x1f00,  8},
+  {m68k_op_move_8_pd7_ai       , 0xfff8, 0x1f10, 12},
+  {m68k_op_move_8_pd7_pi       , 0xfff8, 0x1f18, 12},
+  {m68k_op_move_8_pd7_pd       , 0xfff8, 0x1f20, 14},
+  {m68k_op_move_8_pd7_di       , 0xfff8, 0x1f28, 16},
+  {m68k_op_move_8_pd7_ix       , 0xfff8, 0x1f30, 18},
+  {m68k_op_move_32_aw_d        , 0xfff8, 0x21c0, 16},
+  {m68k_op_move_32_aw_a        , 0xfff8, 0x21c8, 16},
+  {m68k_op_move_32_aw_ai       , 0xfff8, 0x21d0, 24},
+  {m68k_op_move_32_aw_pi       , 0xfff8, 0x21d8, 24},
+  {m68k_op_move_32_aw_pd       , 0xfff8, 0x21e0, 26},
+  {m68k_op_move_32_aw_di       , 0xfff8, 0x21e8, 28},
+  {m68k_op_move_32_aw_ix       , 0xfff8, 0x21f0, 30},
+  {m68k_op_move_32_al_d        , 0xfff8, 0x23c0, 20},
+  {m68k_op_move_32_al_a        , 0xfff8, 0x23c8, 20},
+  {m68k_op_move_32_al_ai       , 0xfff8, 0x23d0, 28},
+  {m68k_op_move_32_al_pi       , 0xfff8, 0x23d8, 28},
+  {m68k_op_move_32_al_pd       , 0xfff8, 0x23e0, 30},
+  {m68k_op_move_32_al_di       , 0xfff8, 0x23e8, 32},
+  {m68k_op_move_32_al_ix       , 0xfff8, 0x23f0, 34},
+  {m68k_op_move_16_aw_d        , 0xfff8, 0x31c0, 12},
+  {m68k_op_move_16_aw_a        , 0xfff8, 0x31c8, 12},
+  {m68k_op_move_16_aw_ai       , 0xfff8, 0x31d0, 16},
+  {m68k_op_move_16_aw_pi       , 0xfff8, 0x31d8, 16},
+  {m68k_op_move_16_aw_pd       , 0xfff8, 0x31e0, 18},
+  {m68k_op_move_16_aw_di       , 0xfff8, 0x31e8, 20},
+  {m68k_op_move_16_aw_ix       , 0xfff8, 0x31f0, 22},
+  {m68k_op_move_16_al_d        , 0xfff8, 0x33c0, 16},
+  {m68k_op_move_16_al_a        , 0xfff8, 0x33c8, 16},
+  {m68k_op_move_16_al_ai       , 0xfff8, 0x33d0, 20},
+  {m68k_op_move_16_al_pi       , 0xfff8, 0x33d8, 20},
+  {m68k_op_move_16_al_pd       , 0xfff8, 0x33e0, 22},
+  {m68k_op_move_16_al_di       , 0xfff8, 0x33e8, 24},
+  {m68k_op_move_16_al_ix       , 0xfff8, 0x33f0, 26},
+  {m68k_op_negx_8_d            , 0xfff8, 0x4000,  4},
+  {m68k_op_negx_8_ai           , 0xfff8, 0x4010, 12},
+  {m68k_op_negx_8_pi           , 0xfff8, 0x4018, 12},
+  {m68k_op_negx_8_pd           , 0xfff8, 0x4020, 14},
+  {m68k_op_negx_8_di           , 0xfff8, 0x4028, 16},
+  {m68k_op_negx_8_ix           , 0xfff8, 0x4030, 18},
+  {m68k_op_negx_16_d           , 0xfff8, 0x4040,  4},
+  {m68k_op_negx_16_ai          , 0xfff8, 0x4050, 12},
+  {m68k_op_negx_16_pi          , 0xfff8, 0x4058, 12},
+  {m68k_op_negx_16_pd          , 0xfff8, 0x4060, 14},
+  {m68k_op_negx_16_di          , 0xfff8, 0x4068, 16},
+  {m68k_op_negx_16_ix          , 0xfff8, 0x4070, 18},
+  {m68k_op_negx_32_d           , 0xfff8, 0x4080,  6},
+  {m68k_op_negx_32_ai          , 0xfff8, 0x4090, 20},
+  {m68k_op_negx_32_pi          , 0xfff8, 0x4098, 20},
+  {m68k_op_negx_32_pd          , 0xfff8, 0x40a0, 22},
+  {m68k_op_negx_32_di          , 0xfff8, 0x40a8, 24},
+  {m68k_op_negx_32_ix          , 0xfff8, 0x40b0, 26},
+  {m68k_op_move_16_frs_d       , 0xfff8, 0x40c0,  6},
+  {m68k_op_move_16_frs_ai      , 0xfff8, 0x40d0, 12},
+  {m68k_op_move_16_frs_pi      , 0xfff8, 0x40d8, 12},
+  {m68k_op_move_16_frs_pd      , 0xfff8, 0x40e0, 14},
+  {m68k_op_move_16_frs_di      , 0xfff8, 0x40e8, 16},
+  {m68k_op_move_16_frs_ix      , 0xfff8, 0x40f0, 18},
+  {m68k_op_clr_8_d             , 0xfff8, 0x4200,  4},
+  {m68k_op_clr_8_ai            , 0xfff8, 0x4210, 12},
+  {m68k_op_clr_8_pi            , 0xfff8, 0x4218, 12},
+  {m68k_op_clr_8_pd            , 0xfff8, 0x4220, 14},
+  {m68k_op_clr_8_di            , 0xfff8, 0x4228, 16},
+  {m68k_op_clr_8_ix            , 0xfff8, 0x4230, 18},
+  {m68k_op_clr_16_d            , 0xfff8, 0x4240,  4},
+  {m68k_op_clr_16_ai           , 0xfff8, 0x4250, 12},
+  {m68k_op_clr_16_pi           , 0xfff8, 0x4258, 12},
+  {m68k_op_clr_16_pd           , 0xfff8, 0x4260, 14},
+  {m68k_op_clr_16_di           , 0xfff8, 0x4268, 16},
+  {m68k_op_clr_16_ix           , 0xfff8, 0x4270, 18},
+  {m68k_op_clr_32_d            , 0xfff8, 0x4280,  6},
+  {m68k_op_clr_32_ai           , 0xfff8, 0x4290, 20},
+  {m68k_op_clr_32_pi           , 0xfff8, 0x4298, 20},
+  {m68k_op_clr_32_pd           , 0xfff8, 0x42a0, 22},
+  {m68k_op_clr_32_di           , 0xfff8, 0x42a8, 24},
+  {m68k_op_clr_32_ix           , 0xfff8, 0x42b0, 26},
+  {m68k_op_neg_8_d             , 0xfff8, 0x4400,  4},
+  {m68k_op_neg_8_ai            , 0xfff8, 0x4410, 12},
+  {m68k_op_neg_8_pi            , 0xfff8, 0x4418, 12},
+  {m68k_op_neg_8_pd            , 0xfff8, 0x4420, 14},
+  {m68k_op_neg_8_di            , 0xfff8, 0x4428, 16},
+  {m68k_op_neg_8_ix            , 0xfff8, 0x4430, 18},
+  {m68k_op_neg_16_d            , 0xfff8, 0x4440,  4},
+  {m68k_op_neg_16_ai           , 0xfff8, 0x4450, 12},
+  {m68k_op_neg_16_pi           , 0xfff8, 0x4458, 12},
+  {m68k_op_neg_16_pd           , 0xfff8, 0x4460, 14},
+  {m68k_op_neg_16_di           , 0xfff8, 0x4468, 16},
+  {m68k_op_neg_16_ix           , 0xfff8, 0x4470, 18},
+  {m68k_op_neg_32_d            , 0xfff8, 0x4480,  6},
+  {m68k_op_neg_32_ai           , 0xfff8, 0x4490, 20},
+  {m68k_op_neg_32_pi           , 0xfff8, 0x4498, 20},
+  {m68k_op_neg_32_pd           , 0xfff8, 0x44a0, 22},
+  {m68k_op_neg_32_di           , 0xfff8, 0x44a8, 24},
+  {m68k_op_neg_32_ix           , 0xfff8, 0x44b0, 26},
+  {m68k_op_move_16_toc_d       , 0xfff8, 0x44c0, 12},
+  {m68k_op_move_16_toc_ai      , 0xfff8, 0x44d0, 16},
+  {m68k_op_move_16_toc_pi      , 0xfff8, 0x44d8, 16},
+  {m68k_op_move_16_toc_pd      , 0xfff8, 0x44e0, 18},
+  {m68k_op_move_16_toc_di      , 0xfff8, 0x44e8, 20},
+  {m68k_op_move_16_toc_ix      , 0xfff8, 0x44f0, 22},
+  {m68k_op_not_8_d             , 0xfff8, 0x4600,  4},
+  {m68k_op_not_8_ai            , 0xfff8, 0x4610, 12},
+  {m68k_op_not_8_pi            , 0xfff8, 0x4618, 12},
+  {m68k_op_not_8_pd            , 0xfff8, 0x4620, 14},
+  {m68k_op_not_8_di            , 0xfff8, 0x4628, 16},
+  {m68k_op_not_8_ix            , 0xfff8, 0x4630, 18},
+  {m68k_op_not_16_d            , 0xfff8, 0x4640,  4},
+  {m68k_op_not_16_ai           , 0xfff8, 0x4650, 12},
+  {m68k_op_not_16_pi           , 0xfff8, 0x4658, 12},
+  {m68k_op_not_16_pd           , 0xfff8, 0x4660, 14},
+  {m68k_op_not_16_di           , 0xfff8, 0x4668, 16},
+  {m68k_op_not_16_ix           , 0xfff8, 0x4670, 18},
+  {m68k_op_not_32_d            , 0xfff8, 0x4680,  6},
+  {m68k_op_not_32_ai           , 0xfff8, 0x4690, 20},
+  {m68k_op_not_32_pi           , 0xfff8, 0x4698, 20},
+  {m68k_op_not_32_pd           , 0xfff8, 0x46a0, 22},
+  {m68k_op_not_32_di           , 0xfff8, 0x46a8, 24},
+  {m68k_op_not_32_ix           , 0xfff8, 0x46b0, 26},
+  {m68k_op_move_16_tos_d       , 0xfff8, 0x46c0, 12},
+  {m68k_op_move_16_tos_ai      , 0xfff8, 0x46d0, 16},
+  {m68k_op_move_16_tos_pi      , 0xfff8, 0x46d8, 16},
+  {m68k_op_move_16_tos_pd      , 0xfff8, 0x46e0, 18},
+  {m68k_op_move_16_tos_di      , 0xfff8, 0x46e8, 20},
+  {m68k_op_move_16_tos_ix      , 0xfff8, 0x46f0, 22},
+  {m68k_op_nbcd_8_d            , 0xfff8, 0x4800,  6},
+  {m68k_op_nbcd_8_ai           , 0xfff8, 0x4810, 12},
+  {m68k_op_nbcd_8_pi           , 0xfff8, 0x4818, 12},
+  {m68k_op_nbcd_8_pd           , 0xfff8, 0x4820, 14},
+  {m68k_op_nbcd_8_di           , 0xfff8, 0x4828, 16},
+  {m68k_op_nbcd_8_ix           , 0xfff8, 0x4830, 18},
+  {m68k_op_swap_32             , 0xfff8, 0x4840,  4},
+  {m68k_op_pea_32_ai           , 0xfff8, 0x4850, 12},
+  {m68k_op_pea_32_di           , 0xfff8, 0x4868, 16},
+  {m68k_op_pea_32_ix           , 0xfff8, 0x4870, 20},
+  {m68k_op_ext_16              , 0xfff8, 0x4880,  4},
+  {m68k_op_movem_16_re_ai      , 0xfff8, 0x4890,  8},
+  {m68k_op_movem_16_re_pd      , 0xfff8, 0x48a0,  8},
+  {m68k_op_movem_16_re_di      , 0xfff8, 0x48a8, 12},
+  {m68k_op_movem_16_re_ix      , 0xfff8, 0x48b0, 14},
+  {m68k_op_ext_32              , 0xfff8, 0x48c0,  4},
+  {m68k_op_movem_32_re_ai      , 0xfff8, 0x48d0,  8},
+  {m68k_op_movem_32_re_pd      , 0xfff8, 0x48e0,  8},
+  {m68k_op_movem_32_re_di      , 0xfff8, 0x48e8, 12},
+  {m68k_op_movem_32_re_ix      , 0xfff8, 0x48f0, 14},
+  {m68k_op_tst_8_d             , 0xfff8, 0x4a00,  4},
+  {m68k_op_tst_8_ai            , 0xfff8, 0x4a10,  8},
+  {m68k_op_tst_8_pi            , 0xfff8, 0x4a18,  8},
+  {m68k_op_tst_8_pd            , 0xfff8, 0x4a20, 10},
+  {m68k_op_tst_8_di            , 0xfff8, 0x4a28, 12},
+  {m68k_op_tst_8_ix            , 0xfff8, 0x4a30, 14},
+  {m68k_op_tst_16_d            , 0xfff8, 0x4a40,  4},
+  {m68k_op_tst_16_ai           , 0xfff8, 0x4a50,  8},
+  {m68k_op_tst_16_pi           , 0xfff8, 0x4a58,  8},
+  {m68k_op_tst_16_pd           , 0xfff8, 0x4a60, 10},
+  {m68k_op_tst_16_di           , 0xfff8, 0x4a68, 12},
+  {m68k_op_tst_16_ix           , 0xfff8, 0x4a70, 14},
+  {m68k_op_tst_32_d            , 0xfff8, 0x4a80,  4},
+  {m68k_op_tst_32_ai           , 0xfff8, 0x4a90, 12},
+  {m68k_op_tst_32_pi           , 0xfff8, 0x4a98, 12},
+  {m68k_op_tst_32_pd           , 0xfff8, 0x4aa0, 14},
+  {m68k_op_tst_32_di           , 0xfff8, 0x4aa8, 16},
+  {m68k_op_tst_32_ix           , 0xfff8, 0x4ab0, 18},
+  {m68k_op_tas_8_d             , 0xfff8, 0x4ac0,  4},
+  {m68k_op_tas_8_ai            , 0xfff8, 0x4ad0, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pi            , 0xfff8, 0x4ad8, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pd            , 0xfff8, 0x4ae0, 16}, /* see Yacht.txt */
+  {m68k_op_tas_8_di            , 0xfff8, 0x4ae8, 18}, /* see Yacht.txt */
+  {m68k_op_tas_8_ix            , 0xfff8, 0x4af0, 20}, /* see Yacht.txt */
+  {m68k_op_movem_16_er_ai      , 0xfff8, 0x4c90, 12},
+  {m68k_op_movem_16_er_pi      , 0xfff8, 0x4c98, 12},
+  {m68k_op_movem_16_er_di      , 0xfff8, 0x4ca8, 16},
+  {m68k_op_movem_16_er_ix      , 0xfff8, 0x4cb0, 18},
+  {m68k_op_movem_32_er_ai      , 0xfff8, 0x4cd0, 12},
+  {m68k_op_movem_32_er_pi      , 0xfff8, 0x4cd8, 12},
+  {m68k_op_movem_32_er_di      , 0xfff8, 0x4ce8, 16},
+  {m68k_op_movem_32_er_ix      , 0xfff8, 0x4cf0, 18},
+  {m68k_op_link_16             , 0xfff8, 0x4e50, 16},
+  {m68k_op_unlk_32             , 0xfff8, 0x4e58, 12},
+  {m68k_op_move_32_tou         , 0xfff8, 0x4e60,  4},
+  {m68k_op_move_32_fru         , 0xfff8, 0x4e68,  4},
+  {m68k_op_jsr_32_ai           , 0xfff8, 0x4e90, 16},
+  {m68k_op_jsr_32_di           , 0xfff8, 0x4ea8, 18},
+  {m68k_op_jsr_32_ix           , 0xfff8, 0x4eb0, 22},
+  {m68k_op_jmp_32_ai           , 0xfff8, 0x4ed0,  8},
+  {m68k_op_jmp_32_di           , 0xfff8, 0x4ee8, 10},
+  {m68k_op_jmp_32_ix           , 0xfff8, 0x4ef0, 14},
+  {m68k_op_st_8_d              , 0xfff8, 0x50c0,  6},
+  {m68k_op_dbt_16              , 0xfff8, 0x50c8, 12},
+  {m68k_op_st_8_ai             , 0xfff8, 0x50d0, 12},
+  {m68k_op_st_8_pi             , 0xfff8, 0x50d8, 12},
+  {m68k_op_st_8_pd             , 0xfff8, 0x50e0, 14},
+  {m68k_op_st_8_di             , 0xfff8, 0x50e8, 16},
+  {m68k_op_st_8_ix             , 0xfff8, 0x50f0, 18},
+  {m68k_op_sf_8_d              , 0xfff8, 0x51c0,  4},
+  {m68k_op_dbf_16              , 0xfff8, 0x51c8, 12},
+  {m68k_op_sf_8_ai             , 0xfff8, 0x51d0, 12},
+  {m68k_op_sf_8_pi             , 0xfff8, 0x51d8, 12},
+  {m68k_op_sf_8_pd             , 0xfff8, 0x51e0, 14},
+  {m68k_op_sf_8_di             , 0xfff8, 0x51e8, 16},
+  {m68k_op_sf_8_ix             , 0xfff8, 0x51f0, 18},
+  {m68k_op_shi_8_d             , 0xfff8, 0x52c0,  4},
+  {m68k_op_dbhi_16             , 0xfff8, 0x52c8, 12},
+  {m68k_op_shi_8_ai            , 0xfff8, 0x52d0, 12},
+  {m68k_op_shi_8_pi            , 0xfff8, 0x52d8, 12},
+  {m68k_op_shi_8_pd            , 0xfff8, 0x52e0, 14},
+  {m68k_op_shi_8_di            , 0xfff8, 0x52e8, 16},
+  {m68k_op_shi_8_ix            , 0xfff8, 0x52f0, 18},
+  {m68k_op_sls_8_d             , 0xfff8, 0x53c0,  4},
+  {m68k_op_dbls_16             , 0xfff8, 0x53c8, 12},
+  {m68k_op_sls_8_ai            , 0xfff8, 0x53d0, 12},
+  {m68k_op_sls_8_pi            , 0xfff8, 0x53d8, 12},
+  {m68k_op_sls_8_pd            , 0xfff8, 0x53e0, 14},
+  {m68k_op_sls_8_di            , 0xfff8, 0x53e8, 16},
+  {m68k_op_sls_8_ix            , 0xfff8, 0x53f0, 18},
+  {m68k_op_scc_8_d             , 0xfff8, 0x54c0,  4},
+  {m68k_op_dbcc_16             , 0xfff8, 0x54c8, 12},
+  {m68k_op_scc_8_ai            , 0xfff8, 0x54d0, 12},
+  {m68k_op_scc_8_pi            , 0xfff8, 0x54d8, 12},
+  {m68k_op_scc_8_pd            , 0xfff8, 0x54e0, 14},
+  {m68k_op_scc_8_di            , 0xfff8, 0x54e8, 16},
+  {m68k_op_scc_8_ix            , 0xfff8, 0x54f0, 18},
+  {m68k_op_scs_8_d             , 0xfff8, 0x55c0,  4},
+  {m68k_op_dbcs_16             , 0xfff8, 0x55c8, 12},
+  {m68k_op_scs_8_ai            , 0xfff8, 0x55d0, 12},
+  {m68k_op_scs_8_pi            , 0xfff8, 0x55d8, 12},
+  {m68k_op_scs_8_pd            , 0xfff8, 0x55e0, 14},
+  {m68k_op_scs_8_di            , 0xfff8, 0x55e8, 16},
+  {m68k_op_scs_8_ix            , 0xfff8, 0x55f0, 18},
+  {m68k_op_sne_8_d             , 0xfff8, 0x56c0,  4},
+  {m68k_op_dbne_16             , 0xfff8, 0x56c8, 12},
+  {m68k_op_sne_8_ai            , 0xfff8, 0x56d0, 12},
+  {m68k_op_sne_8_pi            , 0xfff8, 0x56d8, 12},
+  {m68k_op_sne_8_pd            , 0xfff8, 0x56e0, 14},
+  {m68k_op_sne_8_di            , 0xfff8, 0x56e8, 16},
+  {m68k_op_sne_8_ix            , 0xfff8, 0x56f0, 18},
+  {m68k_op_seq_8_d             , 0xfff8, 0x57c0,  4},
+  {m68k_op_dbeq_16             , 0xfff8, 0x57c8, 12},
+  {m68k_op_seq_8_ai            , 0xfff8, 0x57d0, 12},
+  {m68k_op_seq_8_pi            , 0xfff8, 0x57d8, 12},
+  {m68k_op_seq_8_pd            , 0xfff8, 0x57e0, 14},
+  {m68k_op_seq_8_di            , 0xfff8, 0x57e8, 16},
+  {m68k_op_seq_8_ix            , 0xfff8, 0x57f0, 18},
+  {m68k_op_svc_8_d             , 0xfff8, 0x58c0,  4},
+  {m68k_op_dbvc_16             , 0xfff8, 0x58c8, 12},
+  {m68k_op_svc_8_ai            , 0xfff8, 0x58d0, 12},
+  {m68k_op_svc_8_pi            , 0xfff8, 0x58d8, 12},
+  {m68k_op_svc_8_pd            , 0xfff8, 0x58e0, 14},
+  {m68k_op_svc_8_di            , 0xfff8, 0x58e8, 16},
+  {m68k_op_svc_8_ix            , 0xfff8, 0x58f0, 18},
+  {m68k_op_svs_8_d             , 0xfff8, 0x59c0,  4},
+  {m68k_op_dbvs_16             , 0xfff8, 0x59c8, 12},
+  {m68k_op_svs_8_ai            , 0xfff8, 0x59d0, 12},
+  {m68k_op_svs_8_pi            , 0xfff8, 0x59d8, 12},
+  {m68k_op_svs_8_pd            , 0xfff8, 0x59e0, 14},
+  {m68k_op_svs_8_di            , 0xfff8, 0x59e8, 16},
+  {m68k_op_svs_8_ix            , 0xfff8, 0x59f0, 18},
+  {m68k_op_spl_8_d             , 0xfff8, 0x5ac0,  4},
+  {m68k_op_dbpl_16             , 0xfff8, 0x5ac8, 12},
+  {m68k_op_spl_8_ai            , 0xfff8, 0x5ad0, 12},
+  {m68k_op_spl_8_pi            , 0xfff8, 0x5ad8, 12},
+  {m68k_op_spl_8_pd            , 0xfff8, 0x5ae0, 14},
+  {m68k_op_spl_8_di            , 0xfff8, 0x5ae8, 16},
+  {m68k_op_spl_8_ix            , 0xfff8, 0x5af0, 18},
+  {m68k_op_smi_8_d             , 0xfff8, 0x5bc0,  4},
+  {m68k_op_dbmi_16             , 0xfff8, 0x5bc8, 12},
+  {m68k_op_smi_8_ai            , 0xfff8, 0x5bd0, 12},
+  {m68k_op_smi_8_pi            , 0xfff8, 0x5bd8, 12},
+  {m68k_op_smi_8_pd            , 0xfff8, 0x5be0, 14},
+  {m68k_op_smi_8_di            , 0xfff8, 0x5be8, 16},
+  {m68k_op_smi_8_ix            , 0xfff8, 0x5bf0, 18},
+  {m68k_op_sge_8_d             , 0xfff8, 0x5cc0,  4},
+  {m68k_op_dbge_16             , 0xfff8, 0x5cc8, 12},
+  {m68k_op_sge_8_ai            , 0xfff8, 0x5cd0, 12},
+  {m68k_op_sge_8_pi            , 0xfff8, 0x5cd8, 12},
+  {m68k_op_sge_8_pd            , 0xfff8, 0x5ce0, 14},
+  {m68k_op_sge_8_di            , 0xfff8, 0x5ce8, 16},
+  {m68k_op_sge_8_ix            , 0xfff8, 0x5cf0, 18},
+  {m68k_op_slt_8_d             , 0xfff8, 0x5dc0,  4},
+  {m68k_op_dblt_16             , 0xfff8, 0x5dc8, 12},
+  {m68k_op_slt_8_ai            , 0xfff8, 0x5dd0, 12},
+  {m68k_op_slt_8_pi            , 0xfff8, 0x5dd8, 12},
+  {m68k_op_slt_8_pd            , 0xfff8, 0x5de0, 14},
+  {m68k_op_slt_8_di            , 0xfff8, 0x5de8, 16},
+  {m68k_op_slt_8_ix            , 0xfff8, 0x5df0, 18},
+  {m68k_op_sgt_8_d             , 0xfff8, 0x5ec0,  4},
+  {m68k_op_dbgt_16             , 0xfff8, 0x5ec8, 12},
+  {m68k_op_sgt_8_ai            , 0xfff8, 0x5ed0, 12},
+  {m68k_op_sgt_8_pi            , 0xfff8, 0x5ed8, 12},
+  {m68k_op_sgt_8_pd            , 0xfff8, 0x5ee0, 14},
+  {m68k_op_sgt_8_di            , 0xfff8, 0x5ee8, 16},
+  {m68k_op_sgt_8_ix            , 0xfff8, 0x5ef0, 18},
+  {m68k_op_sle_8_d             , 0xfff8, 0x5fc0,  4},
+  {m68k_op_dble_16             , 0xfff8, 0x5fc8, 12},
+  {m68k_op_sle_8_ai            , 0xfff8, 0x5fd0, 12},
+  {m68k_op_sle_8_pi            , 0xfff8, 0x5fd8, 12},
+  {m68k_op_sle_8_pd            , 0xfff8, 0x5fe0, 14},
+  {m68k_op_sle_8_di            , 0xfff8, 0x5fe8, 16},
+  {m68k_op_sle_8_ix            , 0xfff8, 0x5ff0, 18},
+  {m68k_op_sbcd_8_mm_ax7       , 0xfff8, 0x8f08, 18},
+  {m68k_op_subx_8_mm_ax7       , 0xfff8, 0x9f08, 18},
+  {m68k_op_cmpm_8_ax7          , 0xfff8, 0xbf08, 12},
+  {m68k_op_abcd_8_mm_ax7       , 0xfff8, 0xcf08, 18},
+  {m68k_op_addx_8_mm_ax7       , 0xfff8, 0xdf08, 18},
+  {m68k_op_asr_16_ai           , 0xfff8, 0xe0d0, 12},
+  {m68k_op_asr_16_pi           , 0xfff8, 0xe0d8, 12},
+  {m68k_op_asr_16_pd           , 0xfff8, 0xe0e0, 14},
+  {m68k_op_asr_16_di           , 0xfff8, 0xe0e8, 16},
+  {m68k_op_asr_16_ix           , 0xfff8, 0xe0f0, 18},
+  {m68k_op_asl_16_ai           , 0xfff8, 0xe1d0, 12},
+  {m68k_op_asl_16_pi           , 0xfff8, 0xe1d8, 12},
+  {m68k_op_asl_16_pd           , 0xfff8, 0xe1e0, 14},
+  {m68k_op_asl_16_di           , 0xfff8, 0xe1e8, 16},
+  {m68k_op_asl_16_ix           , 0xfff8, 0xe1f0, 18},
+  {m68k_op_lsr_16_ai           , 0xfff8, 0xe2d0, 12},
+  {m68k_op_lsr_16_pi           , 0xfff8, 0xe2d8, 12},
+  {m68k_op_lsr_16_pd           , 0xfff8, 0xe2e0, 14},
+  {m68k_op_lsr_16_di           , 0xfff8, 0xe2e8, 16},
+  {m68k_op_lsr_16_ix           , 0xfff8, 0xe2f0, 18},
+  {m68k_op_lsl_16_ai           , 0xfff8, 0xe3d0, 12},
+  {m68k_op_lsl_16_pi           , 0xfff8, 0xe3d8, 12},
+  {m68k_op_lsl_16_pd           , 0xfff8, 0xe3e0, 14},
+  {m68k_op_lsl_16_di           , 0xfff8, 0xe3e8, 16},
+  {m68k_op_lsl_16_ix           , 0xfff8, 0xe3f0, 18},
+  {m68k_op_roxr_16_ai          , 0xfff8, 0xe4d0, 12},
+  {m68k_op_roxr_16_pi          , 0xfff8, 0xe4d8, 12},
+  {m68k_op_roxr_16_pd          , 0xfff8, 0xe4e0, 14},
+  {m68k_op_roxr_16_di          , 0xfff8, 0xe4e8, 16},
+  {m68k_op_roxr_16_ix          , 0xfff8, 0xe4f0, 18},
+  {m68k_op_roxl_16_ai          , 0xfff8, 0xe5d0, 12},
+  {m68k_op_roxl_16_pi          , 0xfff8, 0xe5d8, 12},
+  {m68k_op_roxl_16_pd          , 0xfff8, 0xe5e0, 14},
+  {m68k_op_roxl_16_di          , 0xfff8, 0xe5e8, 16},
+  {m68k_op_roxl_16_ix          , 0xfff8, 0xe5f0, 18},
+  {m68k_op_ror_16_ai           , 0xfff8, 0xe6d0, 12},
+  {m68k_op_ror_16_pi           , 0xfff8, 0xe6d8, 12},
+  {m68k_op_ror_16_pd           , 0xfff8, 0xe6e0, 14},
+  {m68k_op_ror_16_di           , 0xfff8, 0xe6e8, 16},
+  {m68k_op_ror_16_ix           , 0xfff8, 0xe6f0, 18},
+  {m68k_op_rol_16_ai           , 0xfff8, 0xe7d0, 12},
+  {m68k_op_rol_16_pi           , 0xfff8, 0xe7d8, 12},
+  {m68k_op_rol_16_pd           , 0xfff8, 0xe7e0, 14},
+  {m68k_op_rol_16_di           , 0xfff8, 0xe7e8, 16},
+  {m68k_op_rol_16_ix           , 0xfff8, 0xe7f0, 18},
+  {m68k_op_ori_8_pi7           , 0xffff, 0x001f, 16},
+  {m68k_op_ori_8_pd7           , 0xffff, 0x0027, 18},
+  {m68k_op_ori_8_aw            , 0xffff, 0x0038, 20},
+  {m68k_op_ori_8_al            , 0xffff, 0x0039, 24},
+  {m68k_op_ori_16_toc          , 0xffff, 0x003c, 20},
+  {m68k_op_ori_16_aw           , 0xffff, 0x0078, 20},
+  {m68k_op_ori_16_al           , 0xffff, 0x0079, 24},
+  {m68k_op_ori_16_tos          , 0xffff, 0x007c, 20},
+  {m68k_op_ori_32_aw           , 0xffff, 0x00b8, 32},
+  {m68k_op_ori_32_al           , 0xffff, 0x00b9, 36},
+  {m68k_op_andi_8_pi7          , 0xffff, 0x021f, 16},
+  {m68k_op_andi_8_pd7          , 0xffff, 0x0227, 18},
+  {m68k_op_andi_8_aw           , 0xffff, 0x0238, 20},
+  {m68k_op_andi_8_al           , 0xffff, 0x0239, 24},
+  {m68k_op_andi_16_toc         , 0xffff, 0x023c, 20},
+  {m68k_op_andi_16_aw          , 0xffff, 0x0278, 20},
+  {m68k_op_andi_16_al          , 0xffff, 0x0279, 24},
+  {m68k_op_andi_16_tos         , 0xffff, 0x027c, 20},
+  {m68k_op_andi_32_aw          , 0xffff, 0x02b8, 32},
+  {m68k_op_andi_32_al          , 0xffff, 0x02b9, 36},
+  {m68k_op_subi_8_pi7          , 0xffff, 0x041f, 16},
+  {m68k_op_subi_8_pd7          , 0xffff, 0x0427, 18},
+  {m68k_op_subi_8_aw           , 0xffff, 0x0438, 20},
+  {m68k_op_subi_8_al           , 0xffff, 0x0439, 24},
+  {m68k_op_subi_16_aw          , 0xffff, 0x0478, 20},
+  {m68k_op_subi_16_al          , 0xffff, 0x0479, 24},
+  {m68k_op_subi_32_aw          , 0xffff, 0x04b8, 32},
+  {m68k_op_subi_32_al          , 0xffff, 0x04b9, 36},
+  {m68k_op_addi_8_pi7          , 0xffff, 0x061f, 16},
+  {m68k_op_addi_8_pd7          , 0xffff, 0x0627, 18},
+  {m68k_op_addi_8_aw           , 0xffff, 0x0638, 20},
+  {m68k_op_addi_8_al           , 0xffff, 0x0639, 24},
+  {m68k_op_addi_16_aw          , 0xffff, 0x0678, 20},
+  {m68k_op_addi_16_al          , 0xffff, 0x0679, 24},
+  {m68k_op_addi_32_aw          , 0xffff, 0x06b8, 32},
+  {m68k_op_addi_32_al          , 0xffff, 0x06b9, 36},
+  {m68k_op_btst_8_s_pi7        , 0xffff, 0x081f, 12},
+  {m68k_op_btst_8_s_pd7        , 0xffff, 0x0827, 14},
+  {m68k_op_btst_8_s_aw         , 0xffff, 0x0838, 16},
+  {m68k_op_btst_8_s_al         , 0xffff, 0x0839, 20},
+  {m68k_op_btst_8_s_pcdi       , 0xffff, 0x083a, 16},
+  {m68k_op_btst_8_s_pcix       , 0xffff, 0x083b, 18},
+  {m68k_op_bchg_8_s_pi7        , 0xffff, 0x085f, 16},
+  {m68k_op_bchg_8_s_pd7        , 0xffff, 0x0867, 18},
+  {m68k_op_bchg_8_s_aw         , 0xffff, 0x0878, 20},
+  {m68k_op_bchg_8_s_al         , 0xffff, 0x0879, 24},
+  {m68k_op_bclr_8_s_pi7        , 0xffff, 0x089f, 16},
+  {m68k_op_bclr_8_s_pd7        , 0xffff, 0x08a7, 18},
+  {m68k_op_bclr_8_s_aw         , 0xffff, 0x08b8, 20},
+  {m68k_op_bclr_8_s_al         , 0xffff, 0x08b9, 24},
+  {m68k_op_bset_8_s_pi7        , 0xffff, 0x08df, 16},
+  {m68k_op_bset_8_s_pd7        , 0xffff, 0x08e7, 18},
+  {m68k_op_bset_8_s_aw         , 0xffff, 0x08f8, 20},
+  {m68k_op_bset_8_s_al         , 0xffff, 0x08f9, 24},
+  {m68k_op_eori_8_pi7          , 0xffff, 0x0a1f, 16},
+  {m68k_op_eori_8_pd7          , 0xffff, 0x0a27, 18},
+  {m68k_op_eori_8_aw           , 0xffff, 0x0a38, 20},
+  {m68k_op_eori_8_al           , 0xffff, 0x0a39, 24},
+  {m68k_op_eori_16_toc         , 0xffff, 0x0a3c, 20},
+  {m68k_op_eori_16_aw          , 0xffff, 0x0a78, 20},
+  {m68k_op_eori_16_al          , 0xffff, 0x0a79, 24},
+  {m68k_op_eori_16_tos         , 0xffff, 0x0a7c, 20},
+  {m68k_op_eori_32_aw          , 0xffff, 0x0ab8, 32},
+  {m68k_op_eori_32_al          , 0xffff, 0x0ab9, 36},
+  {m68k_op_cmpi_8_pi7          , 0xffff, 0x0c1f, 12},
+  {m68k_op_cmpi_8_pd7          , 0xffff, 0x0c27, 14},
+  {m68k_op_cmpi_8_aw           , 0xffff, 0x0c38, 16},
+  {m68k_op_cmpi_8_al           , 0xffff, 0x0c39, 20},
+  {m68k_op_cmpi_16_aw          , 0xffff, 0x0c78, 16},
+  {m68k_op_cmpi_16_al          , 0xffff, 0x0c79, 20},
+  {m68k_op_cmpi_32_aw          , 0xffff, 0x0cb8, 24},
+  {m68k_op_cmpi_32_al          , 0xffff, 0x0cb9, 28},
+  {m68k_op_move_8_aw_pi7       , 0xffff, 0x11df, 16},
+  {m68k_op_move_8_aw_pd7       , 0xffff, 0x11e7, 18},
+  {m68k_op_move_8_aw_aw        , 0xffff, 0x11f8, 20},
+  {m68k_op_move_8_aw_al        , 0xffff, 0x11f9, 24},
+  {m68k_op_move_8_aw_pcdi      , 0xffff, 0x11fa, 20},
+  {m68k_op_move_8_aw_pcix      , 0xffff, 0x11fb, 22},
+  {m68k_op_move_8_aw_i         , 0xffff, 0x11fc, 16},
+  {m68k_op_move_8_al_pi7       , 0xffff, 0x13df, 20},
+  {m68k_op_move_8_al_pd7       , 0xffff, 0x13e7, 22},
+  {m68k_op_move_8_al_aw        , 0xffff, 0x13f8, 24},
+  {m68k_op_move_8_al_al        , 0xffff, 0x13f9, 28},
+  {m68k_op_move_8_al_pcdi      , 0xffff, 0x13fa, 24},
+  {m68k_op_move_8_al_pcix      , 0xffff, 0x13fb, 26},
+  {m68k_op_move_8_al_i         , 0xffff, 0x13fc, 20},
+  {m68k_op_move_8_pi7_pi7      , 0xffff, 0x1edf, 12},
+  {m68k_op_move_8_pi7_pd7      , 0xffff, 0x1ee7, 14},
+  {m68k_op_move_8_pi7_aw       , 0xffff, 0x1ef8, 16},
+  {m68k_op_move_8_pi7_al       , 0xffff, 0x1ef9, 20},
+  {m68k_op_move_8_pi7_pcdi     , 0xffff, 0x1efa, 16},
+  {m68k_op_move_8_pi7_pcix     , 0xffff, 0x1efb, 18},
+  {m68k_op_move_8_pi7_i        , 0xffff, 0x1efc, 12},
+  {m68k_op_move_8_pd7_pi7      , 0xffff, 0x1f1f, 12},
+  {m68k_op_move_8_pd7_pd7      , 0xffff, 0x1f27, 14},
+  {m68k_op_move_8_pd7_aw       , 0xffff, 0x1f38, 16},
+  {m68k_op_move_8_pd7_al       , 0xffff, 0x1f39, 20},
+  {m68k_op_move_8_pd7_pcdi     , 0xffff, 0x1f3a, 16},
+  {m68k_op_move_8_pd7_pcix     , 0xffff, 0x1f3b, 18},
+  {m68k_op_move_8_pd7_i        , 0xffff, 0x1f3c, 12},
+  {m68k_op_move_32_aw_aw       , 0xffff, 0x21f8, 28},
+  {m68k_op_move_32_aw_al       , 0xffff, 0x21f9, 32},
+  {m68k_op_move_32_aw_pcdi     , 0xffff, 0x21fa, 28},
+  {m68k_op_move_32_aw_pcix     , 0xffff, 0x21fb, 30},
+  {m68k_op_move_32_aw_i        , 0xffff, 0x21fc, 24},
+  {m68k_op_move_32_al_aw       , 0xffff, 0x23f8, 32},
+  {m68k_op_move_32_al_al       , 0xffff, 0x23f9, 36},
+  {m68k_op_move_32_al_pcdi     , 0xffff, 0x23fa, 32},
+  {m68k_op_move_32_al_pcix     , 0xffff, 0x23fb, 34},
+  {m68k_op_move_32_al_i        , 0xffff, 0x23fc, 28},
+  {m68k_op_move_16_aw_aw       , 0xffff, 0x31f8, 20},
+  {m68k_op_move_16_aw_al       , 0xffff, 0x31f9, 24},
+  {m68k_op_move_16_aw_pcdi     , 0xffff, 0x31fa, 20},
+  {m68k_op_move_16_aw_pcix     , 0xffff, 0x31fb, 22},
+  {m68k_op_move_16_aw_i        , 0xffff, 0x31fc, 16},
+  {m68k_op_move_16_al_aw       , 0xffff, 0x33f8, 24},
+  {m68k_op_move_16_al_al       , 0xffff, 0x33f9, 28},
+  {m68k_op_move_16_al_pcdi     , 0xffff, 0x33fa, 24},
+  {m68k_op_move_16_al_pcix     , 0xffff, 0x33fb, 26},
+  {m68k_op_move_16_al_i        , 0xffff, 0x33fc, 20},
+  {m68k_op_negx_8_pi7          , 0xffff, 0x401f, 12},
+  {m68k_op_negx_8_pd7          , 0xffff, 0x4027, 14},
+  {m68k_op_negx_8_aw           , 0xffff, 0x4038, 16},
+  {m68k_op_negx_8_al           , 0xffff, 0x4039, 20},
+  {m68k_op_negx_16_aw          , 0xffff, 0x4078, 16},
+  {m68k_op_negx_16_al          , 0xffff, 0x4079, 20},
+  {m68k_op_negx_32_aw          , 0xffff, 0x40b8, 24},
+  {m68k_op_negx_32_al          , 0xffff, 0x40b9, 28},
+  {m68k_op_move_16_frs_aw      , 0xffff, 0x40f8, 16},
+  {m68k_op_move_16_frs_al      , 0xffff, 0x40f9, 20},
+  {m68k_op_clr_8_pi7           , 0xffff, 0x421f, 12},
+  {m68k_op_clr_8_pd7           , 0xffff, 0x4227, 14},
+  {m68k_op_clr_8_aw            , 0xffff, 0x4238, 16},
+  {m68k_op_clr_8_al            , 0xffff, 0x4239, 20},
+  {m68k_op_clr_16_aw           , 0xffff, 0x4278, 16},
+  {m68k_op_clr_16_al           , 0xffff, 0x4279, 20},
+  {m68k_op_clr_32_aw           , 0xffff, 0x42b8, 24},
+  {m68k_op_clr_32_al           , 0xffff, 0x42b9, 28},
+  {m68k_op_neg_8_pi7           , 0xffff, 0x441f, 12},
+  {m68k_op_neg_8_pd7           , 0xffff, 0x4427, 14},
+  {m68k_op_neg_8_aw            , 0xffff, 0x4438, 16},
+  {m68k_op_neg_8_al            , 0xffff, 0x4439, 20},
+  {m68k_op_neg_16_aw           , 0xffff, 0x4478, 16},
+  {m68k_op_neg_16_al           , 0xffff, 0x4479, 20},
+  {m68k_op_neg_32_aw           , 0xffff, 0x44b8, 24},
+  {m68k_op_neg_32_al           , 0xffff, 0x44b9, 28},
+  {m68k_op_move_16_toc_aw      , 0xffff, 0x44f8, 20},
+  {m68k_op_move_16_toc_al      , 0xffff, 0x44f9, 24},
+  {m68k_op_move_16_toc_pcdi    , 0xffff, 0x44fa, 20},
+  {m68k_op_move_16_toc_pcix    , 0xffff, 0x44fb, 22},
+  {m68k_op_move_16_toc_i       , 0xffff, 0x44fc, 16},
+  {m68k_op_not_8_pi7           , 0xffff, 0x461f, 12},
+  {m68k_op_not_8_pd7           , 0xffff, 0x4627, 14},
+  {m68k_op_not_8_aw            , 0xffff, 0x4638, 16},
+  {m68k_op_not_8_al            , 0xffff, 0x4639, 20},
+  {m68k_op_not_16_aw           , 0xffff, 0x4678, 16},
+  {m68k_op_not_16_al           , 0xffff, 0x4679, 20},
+  {m68k_op_not_32_aw           , 0xffff, 0x46b8, 24},
+  {m68k_op_not_32_al           , 0xffff, 0x46b9, 28},
+  {m68k_op_move_16_tos_aw      , 0xffff, 0x46f8, 20},
+  {m68k_op_move_16_tos_al      , 0xffff, 0x46f9, 24},
+  {m68k_op_move_16_tos_pcdi    , 0xffff, 0x46fa, 20},
+  {m68k_op_move_16_tos_pcix    , 0xffff, 0x46fb, 22},
+  {m68k_op_move_16_tos_i       , 0xffff, 0x46fc, 16},
+  {m68k_op_nbcd_8_pi7          , 0xffff, 0x481f, 12},
+  {m68k_op_nbcd_8_pd7          , 0xffff, 0x4827, 14},
+  {m68k_op_nbcd_8_aw           , 0xffff, 0x4838, 16},
+  {m68k_op_nbcd_8_al           , 0xffff, 0x4839, 20},
+  {m68k_op_pea_32_aw           , 0xffff, 0x4878, 16},
+  {m68k_op_pea_32_al           , 0xffff, 0x4879, 20},
+  {m68k_op_pea_32_pcdi         , 0xffff, 0x487a, 16},
+  {m68k_op_pea_32_pcix         , 0xffff, 0x487b, 20},
+  {m68k_op_movem_16_re_aw      , 0xffff, 0x48b8, 12},
+  {m68k_op_movem_16_re_al      , 0xffff, 0x48b9, 16},
+  {m68k_op_movem_32_re_aw      , 0xffff, 0x48f8, 12},
+  {m68k_op_movem_32_re_al      , 0xffff, 0x48f9, 16},
+  {m68k_op_tst_8_pi7           , 0xffff, 0x4a1f,  8},
+  {m68k_op_tst_8_pd7           , 0xffff, 0x4a27, 10},
+  {m68k_op_tst_8_aw            , 0xffff, 0x4a38, 12},
+  {m68k_op_tst_8_al            , 0xffff, 0x4a39, 16},
+  {m68k_op_tst_16_aw           , 0xffff, 0x4a78, 12},
+  {m68k_op_tst_16_al           , 0xffff, 0x4a79, 16},
+  {m68k_op_tst_32_aw           , 0xffff, 0x4ab8, 16},
+  {m68k_op_tst_32_al           , 0xffff, 0x4ab9, 20},
+  {m68k_op_tas_8_pi7           , 0xffff, 0x4adf, 14}, /* see Yacht.txt */
+  {m68k_op_tas_8_pd7           , 0xffff, 0x4ae7, 16}, /* see Yacht.txt */
+  {m68k_op_tas_8_aw            , 0xffff, 0x4af8, 18}, /* see Yacht.txt */
+  {m68k_op_tas_8_al            , 0xffff, 0x4af9, 22}, /* see Yacht.txt */
+  {m68k_op_illegal             , 0xffff, 0x4afc,  4},
+  {m68k_op_movem_16_er_aw      , 0xffff, 0x4cb8, 16},
+  {m68k_op_movem_16_er_al      , 0xffff, 0x4cb9, 20},
+  {m68k_op_movem_16_er_pcdi    , 0xffff, 0x4cba, 16},
+  {m68k_op_movem_16_er_pcix    , 0xffff, 0x4cbb, 18},
+  {m68k_op_movem_32_er_aw      , 0xffff, 0x4cf8, 16},
+  {m68k_op_movem_32_er_al      , 0xffff, 0x4cf9, 20},
+  {m68k_op_movem_32_er_pcdi    , 0xffff, 0x4cfa, 16},
+  {m68k_op_movem_32_er_pcix    , 0xffff, 0x4cfb, 18},
+  {m68k_op_link_16_a7          , 0xffff, 0x4e57, 16},
+  {m68k_op_unlk_32_a7          , 0xffff, 0x4e5f, 12},
+  {m68k_op_reset               , 0xffff, 0x4e70,  0},
+  {m68k_op_nop                 , 0xffff, 0x4e71,  4},
+  {m68k_op_stop                , 0xffff, 0x4e72,  4},
+  {m68k_op_rte_32              , 0xffff, 0x4e73, 20},
+  {m68k_op_rts_32              , 0xffff, 0x4e75, 16},
+  {m68k_op_trapv               , 0xffff, 0x4e76,  4},
+  {m68k_op_rtr_32              , 0xffff, 0x4e77, 20},
+  {m68k_op_jsr_32_aw           , 0xffff, 0x4eb8, 18},
+  {m68k_op_jsr_32_al           , 0xffff, 0x4eb9, 20},
+  {m68k_op_jsr_32_pcdi         , 0xffff, 0x4eba, 18},
+  {m68k_op_jsr_32_pcix         , 0xffff, 0x4ebb, 22},
+  {m68k_op_jmp_32_aw           , 0xffff, 0x4ef8, 10},
+  {m68k_op_jmp_32_al           , 0xffff, 0x4ef9, 12},
+  {m68k_op_jmp_32_pcdi         , 0xffff, 0x4efa, 10},
+  {m68k_op_jmp_32_pcix         , 0xffff, 0x4efb, 14},
+  {m68k_op_st_8_pi7            , 0xffff, 0x50df, 12},
+  {m68k_op_st_8_pd7            , 0xffff, 0x50e7, 14},
+  {m68k_op_st_8_aw             , 0xffff, 0x50f8, 16},
+  {m68k_op_st_8_al             , 0xffff, 0x50f9, 20},
+  {m68k_op_sf_8_pi7            , 0xffff, 0x51df, 12},
+  {m68k_op_sf_8_pd7            , 0xffff, 0x51e7, 14},
+  {m68k_op_sf_8_aw             , 0xffff, 0x51f8, 16},
+  {m68k_op_sf_8_al             , 0xffff, 0x51f9, 20},
+  {m68k_op_shi_8_pi7           , 0xffff, 0x52df, 12},
+  {m68k_op_shi_8_pd7           , 0xffff, 0x52e7, 14},
+  {m68k_op_shi_8_aw            , 0xffff, 0x52f8, 16},
+  {m68k_op_shi_8_al            , 0xffff, 0x52f9, 20},
+  {m68k_op_sls_8_pi7           , 0xffff, 0x53df, 12},
+  {m68k_op_sls_8_pd7           , 0xffff, 0x53e7, 14},
+  {m68k_op_sls_8_aw            , 0xffff, 0x53f8, 16},
+  {m68k_op_sls_8_al            , 0xffff, 0x53f9, 20},
+  {m68k_op_scc_8_pi7           , 0xffff, 0x54df, 12},
+  {m68k_op_scc_8_pd7           , 0xffff, 0x54e7, 14},
+  {m68k_op_scc_8_aw            , 0xffff, 0x54f8, 16},
+  {m68k_op_scc_8_al            , 0xffff, 0x54f9, 20},
+  {m68k_op_scs_8_pi7           , 0xffff, 0x55df, 12},
+  {m68k_op_scs_8_pd7           , 0xffff, 0x55e7, 14},
+  {m68k_op_scs_8_aw            , 0xffff, 0x55f8, 16},
+  {m68k_op_scs_8_al            , 0xffff, 0x55f9, 20},
+  {m68k_op_sne_8_pi7           , 0xffff, 0x56df, 12},
+  {m68k_op_sne_8_pd7           , 0xffff, 0x56e7, 14},
+  {m68k_op_sne_8_aw            , 0xffff, 0x56f8, 16},
+  {m68k_op_sne_8_al            , 0xffff, 0x56f9, 20},
+  {m68k_op_seq_8_pi7           , 0xffff, 0x57df, 12},
+  {m68k_op_seq_8_pd7           , 0xffff, 0x57e7, 14},
+  {m68k_op_seq_8_aw            , 0xffff, 0x57f8, 16},
+  {m68k_op_seq_8_al            , 0xffff, 0x57f9, 20},
+  {m68k_op_svc_8_pi7           , 0xffff, 0x58df, 12},
+  {m68k_op_svc_8_pd7           , 0xffff, 0x58e7, 14},
+  {m68k_op_svc_8_aw            , 0xffff, 0x58f8, 16},
+  {m68k_op_svc_8_al            , 0xffff, 0x58f9, 20},
+  {m68k_op_svs_8_pi7           , 0xffff, 0x59df, 12},
+  {m68k_op_svs_8_pd7           , 0xffff, 0x59e7, 14},
+  {m68k_op_svs_8_aw            , 0xffff, 0x59f8, 16},
+  {m68k_op_svs_8_al            , 0xffff, 0x59f9, 20},
+  {m68k_op_spl_8_pi7           , 0xffff, 0x5adf, 12},
+  {m68k_op_spl_8_pd7           , 0xffff, 0x5ae7, 14},
+  {m68k_op_spl_8_aw            , 0xffff, 0x5af8, 16},
+  {m68k_op_spl_8_al            , 0xffff, 0x5af9, 20},
+  {m68k_op_smi_8_pi7           , 0xffff, 0x5bdf, 12},
+  {m68k_op_smi_8_pd7           , 0xffff, 0x5be7, 14},
+  {m68k_op_smi_8_aw            , 0xffff, 0x5bf8, 16},
+  {m68k_op_smi_8_al            , 0xffff, 0x5bf9, 20},
+  {m68k_op_sge_8_pi7           , 0xffff, 0x5cdf, 12},
+  {m68k_op_sge_8_pd7           , 0xffff, 0x5ce7, 14},
+  {m68k_op_sge_8_aw            , 0xffff, 0x5cf8, 16},
+  {m68k_op_sge_8_al            , 0xffff, 0x5cf9, 20},
+  {m68k_op_slt_8_pi7           , 0xffff, 0x5ddf, 12},
+  {m68k_op_slt_8_pd7           , 0xffff, 0x5de7, 14},
+  {m68k_op_slt_8_aw            , 0xffff, 0x5df8, 16},
+  {m68k_op_slt_8_al            , 0xffff, 0x5df9, 20},
+  {m68k_op_sgt_8_pi7           , 0xffff, 0x5edf, 12},
+  {m68k_op_sgt_8_pd7           , 0xffff, 0x5ee7, 14},
+  {m68k_op_sgt_8_aw            , 0xffff, 0x5ef8, 16},
+  {m68k_op_sgt_8_al            , 0xffff, 0x5ef9, 20},
+  {m68k_op_sle_8_pi7           , 0xffff, 0x5fdf, 12},
+  {m68k_op_sle_8_pd7           , 0xffff, 0x5fe7, 14},
+  {m68k_op_sle_8_aw            , 0xffff, 0x5ff8, 16},
+  {m68k_op_sle_8_al            , 0xffff, 0x5ff9, 20},
+  {m68k_op_bra_16              , 0xffff, 0x6000, 10},
+  {m68k_op_bra_32              , 0xffff, 0x60ff, 10},
+  {m68k_op_bsr_16              , 0xffff, 0x6100, 18},
+  {m68k_op_bsr_32              , 0xffff, 0x61ff, 18},
+  {m68k_op_bhi_16              , 0xffff, 0x6200, 10},
+  {m68k_op_bhi_32              , 0xffff, 0x62ff, 10},
+  {m68k_op_bls_16              , 0xffff, 0x6300, 10},
+  {m68k_op_bls_32              , 0xffff, 0x63ff, 10},
+  {m68k_op_bcc_16              , 0xffff, 0x6400, 10},
+  {m68k_op_bcc_32              , 0xffff, 0x64ff, 10},
+  {m68k_op_bcs_16              , 0xffff, 0x6500, 10},
+  {m68k_op_bcs_32              , 0xffff, 0x65ff, 10},
+  {m68k_op_bne_16              , 0xffff, 0x6600, 10},
+  {m68k_op_bne_32              , 0xffff, 0x66ff, 10},
+  {m68k_op_beq_16              , 0xffff, 0x6700, 10},
+  {m68k_op_beq_32              , 0xffff, 0x67ff, 10},
+  {m68k_op_bvc_16              , 0xffff, 0x6800, 10},
+  {m68k_op_bvc_32              , 0xffff, 0x68ff, 10},
+  {m68k_op_bvs_16              , 0xffff, 0x6900, 10},
+  {m68k_op_bvs_32              , 0xffff, 0x69ff, 10},
+  {m68k_op_bpl_16              , 0xffff, 0x6a00, 10},
+  {m68k_op_bpl_32              , 0xffff, 0x6aff, 10},
+  {m68k_op_bmi_16              , 0xffff, 0x6b00, 10},
+  {m68k_op_bmi_32              , 0xffff, 0x6bff, 10},
+  {m68k_op_bge_16              , 0xffff, 0x6c00, 10},
+  {m68k_op_bge_32              , 0xffff, 0x6cff, 10},
+  {m68k_op_blt_16              , 0xffff, 0x6d00, 10},
+  {m68k_op_blt_32              , 0xffff, 0x6dff, 10},
+  {m68k_op_bgt_16              , 0xffff, 0x6e00, 10},
+  {m68k_op_bgt_32              , 0xffff, 0x6eff, 10},
+  {m68k_op_ble_16              , 0xffff, 0x6f00, 10},
+  {m68k_op_ble_32              , 0xffff, 0x6fff, 10},
+  {m68k_op_sbcd_8_mm_axy7      , 0xffff, 0x8f0f, 18},
+  {m68k_op_subx_8_mm_axy7      , 0xffff, 0x9f0f, 18},
+  {m68k_op_cmpm_8_axy7         , 0xffff, 0xbf0f, 12},
+  {m68k_op_abcd_8_mm_axy7      , 0xffff, 0xcf0f, 18},
+  {m68k_op_addx_8_mm_axy7      , 0xffff, 0xdf0f, 18},
+  {m68k_op_asr_16_aw           , 0xffff, 0xe0f8, 16},
+  {m68k_op_asr_16_al           , 0xffff, 0xe0f9, 20},
+  {m68k_op_asl_16_aw           , 0xffff, 0xe1f8, 16},
+  {m68k_op_asl_16_al           , 0xffff, 0xe1f9, 20},
+  {m68k_op_lsr_16_aw           , 0xffff, 0xe2f8, 16},
+  {m68k_op_lsr_16_al           , 0xffff, 0xe2f9, 20},
+  {m68k_op_lsl_16_aw           , 0xffff, 0xe3f8, 16},
+  {m68k_op_lsl_16_al           , 0xffff, 0xe3f9, 20},
+  {m68k_op_roxr_16_aw          , 0xffff, 0xe4f8, 16},
+  {m68k_op_roxr_16_al          , 0xffff, 0xe4f9, 20},
+  {m68k_op_roxl_16_aw          , 0xffff, 0xe5f8, 16},
+  {m68k_op_roxl_16_al          , 0xffff, 0xe5f9, 20},
+  {m68k_op_ror_16_aw           , 0xffff, 0xe6f8, 16},
+  {m68k_op_ror_16_al           , 0xffff, 0xe6f9, 20},
+  {m68k_op_rol_16_aw           , 0xffff, 0xe7f8, 16},
+  {m68k_op_rol_16_al           , 0xffff, 0xe7f9, 20},
+  {0, 0, 0, 0}
+};
+
+
+/* Build the opcode handler jump table */
+static void __inline m68ki_build_opcode_table(void)
+{
+  const opcode_handler_struct *ostruct;
+  int instr;
+  int i;
+  int j;
+
+  for(i = 0; i < 0x10000; i++)
+  {
+    /* default to illegal */
+    m68ki_instruction_jump_table[i] = m68k_op_illegal;
+    m68ki_cycles[i] = 4;
+  }
+
+  ostruct = &m68k_opcode_handler_table[0];
+  while(ostruct->mask != 0xff00)
+  {
+    for(i = 0;i < 0x10000;i++)
+    {
+      if((i & ostruct->mask) == ostruct->match)
+      {
+        m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
+        m68ki_cycles[i] = ostruct->cycles * MUL;
+      }
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xff00)
+  {
+    for(i = 0;i <= 0xff;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xf1f8)
+  {
+    for(i = 0;i < 8;i++)
+    {
+      for(j = 0;j < 8;j++)
+      {
+        instr = ostruct->match | (i << 9) | j;
+        m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
+        m68ki_cycles[instr] = ostruct->cycles * MUL;
+      }
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xfff0)
+  {
+    for(i = 0;i <= 0x0f;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xf1ff)
+  {
+    for(i = 0;i <= 0x07;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | (i << 9)] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xfff8)
+  {
+    for(i = 0;i <= 0x07;i++)
+    {
+      m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
+      m68ki_cycles[ostruct->match | i] = ostruct->cycles * MUL;
+    }
+    ostruct++;
+  }
+  while(ostruct->mask == 0xffff)
+  {
+    m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
+    m68ki_cycles[ostruct->match] = ostruct->cycles * MUL;
+    ostruct++;
+  }
+}
+
+#endif
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/macros.h b/MCUME_pico2/picogen/gwenesis/cpus/M68K/macros.h
new file mode 100755
index 0000000..b3a639b
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/macros.h
@@ -0,0 +1,70 @@
+#ifndef _MACROS_H_
+#define _MACROS_H_
+
+#ifdef LSB_FIRST
+
+#define READ_BYTE(BASE, ADDR) (BASE)[(ADDR)^1]
+
+#define READ_WORD(BASE, ADDR) (((BASE)[ADDR]<<8) | (BASE)[(ADDR)+1])
+
+#define READ_WORD_LONG(BASE, ADDR) (((BASE)[(ADDR)+1]<<24) |      \
+                                    ((BASE)[(ADDR)]<<16) |  \
+                                    ((BASE)[(ADDR)+3]<<8) |   \
+                                    (BASE)[(ADDR)+2])
+
+#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[(ADDR)^1] = (VAL)&0xff
+
+#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[ADDR] = ((VAL)>>8) & 0xff; \
+                                      (BASE)[(ADDR)+1] = (VAL)&0xff
+
+#define WRITE_WORD_LONG(BASE, ADDR, VAL) (BASE)[(ADDR+1)] = ((VAL)>>24) & 0xff;    \
+                                          (BASE)[(ADDR)] = ((VAL)>>16)&0xff;  \
+                                          (BASE)[(ADDR+3)] = ((VAL)>>8)&0xff;   \
+                                          (BASE)[(ADDR+2)] = (VAL)&0xff
+
+#else
+
+#define READ_BYTE(BASE, ADDR) (BASE)[ADDR]
+#define READ_WORD(BASE, ADDR) *(uint16 *)((BASE) + (ADDR))
+#define READ_WORD_LONG(BASE, ADDR) *(uint32 *)((BASE) + (ADDR))
+#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[ADDR] = VAL & 0xff
+#define WRITE_WORD(BASE, ADDR, VAL) *(uint16 *)((BASE) + (ADDR)) = VAL & 0xffff
+#define WRITE_WORD_LONG(BASE, ADDR, VAL) *(uint32 *)((BASE) + (ADDR)) = VAL & 0xffffffff
+#endif
+
+/* C89 compatibility */
+#ifndef M_PI
+#define M_PI 3.14159265358979323846264338327f
+#endif /* M_PI */
+
+/* Set to your compiler's static inline keyword to enable it, or
+ * set it to blank to disable it.
+ * If you define INLINE in makefile or osd.h, it will override this value.
+ * NOTE: not enabling inline functions will SEVERELY slow down emulation.
+ */
+#ifndef INLINE
+#define INLINE static __inline__
+#endif /* INLINE */
+
+/* Alignment macros for cross compiler compatibility */
+#if defined(_MSC_VER)
+#define ALIGNED_(x) __declspec(align(x))
+#elif defined(__GNUC__)
+#define ALIGNED_(x) __attribute__ ((aligned(x)))
+#endif
+
+/* Default CD image file access (read-only) functions */
+/* If you need to override default stdio.h functions with custom filesystem API,
+   redefine following macros in platform specific include file (osd.h) or Makefile
+*/
+#ifndef cdStream
+#define cdStream            FILE
+#define cdStreamOpen(fname) fopen(fname, "rb")
+#define cdStreamClose       fclose
+#define cdStreamRead        fread
+#define cdStreamSeek        fseek
+#define cdStreamTell        ftell
+#define cdStreamGets        fgets
+#endif
+
+#endif /* _MACROS_H_ */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/M68K/readme.txt b/MCUME_pico2/picogen/gwenesis/cpus/M68K/readme.txt
new file mode 100755
index 0000000..9154901
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/M68K/readme.txt
@@ -0,0 +1,315 @@
+                                    MUSASHI
+                                    =======
+
+                                  Version 3.3
+
+             A portable Motorola M680x0 processor emulation engine.
+            Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+
+
+
+INTRODUCTION:
+------------
+
+Musashi is a Motorola 68000, 68010, 68EC020, and 68020 emulator written in C.
+This emulator was written with two goals in mind: portability and speed.
+
+The emulator is written to ANSI C specifications with the exception that I use
+inline functions.  This is not compliant to the ANSI spec, but will be
+compliant to the ANSI C9X spec.
+
+It has been successfully running in the MAME project (www.mame.net) for over 2
+years and so has had time to mature.
+
+
+
+LICENSE AND COPYRIGHT:
+---------------------
+
+The Musashi M680x0 emulator is copyright 1998-2001 Karl Stenerud.
+
+The source code included in this archive is provided AS-IS, free for any
+non-commercial purpose.
+
+If you build a program using this core, please give credit to the author.
+
+If you wish to use this core in a commercial environment, please contact
+the author to discuss commercial licensing.
+
+
+
+AVAILABILITY:
+------------
+The latest version of this code can be obtained at:
+http://kstenerud.cjb.net
+
+
+
+CONTACTING THE AUTHOR:
+---------------------
+I can be reached at kstenerud@mame.net
+
+
+
+BASIC CONFIGURATION:
+-------------------
+The basic configuration will give you a standard 68000 that has sufficient
+functionality to work in a primitive environment.
+
+This setup assumes that you only have 1 device interrupting it, that the
+device will always request an autovectored interrupt, and it will always clear
+the interrupt before the interrupt service routine finishes (but could
+possibly re-assert the interrupt).
+You will have only one address space, no tracing, and no instruction prefetch.
+
+To implement the basic configuration:
+
+- Open m68kconf.h and verify that the settings for INLINE and DECL_SPEC will
+  work with your compiler. (They are set for gcc)
+
+- In your host program, implement the following functions:
+    unsigned int  m68k_read_memory_8(unsigned int address);
+    unsigned int  m68k_read_memory_16(unsigned int address);
+    unsigned int  m68k_read_memory_32(unsigned int address);
+    void m68k_write_memory_8(unsigned int address, unsigned int value);
+    void m68k_write_memory_16(unsigned int address, unsigned int value);
+    void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+- In your host program, be sure to call m68k_pulse_reset() once before calling
+  any of the other functions as this initializes the core.
+
+- Use m68k_execute() to execute instructions and m68k_set_irq() to cause an
+  interrupt.
+
+
+
+ADDING PROPER INTERRUPT HANDLING:
+--------------------------------
+The interrupt handling in the basic configuration doesn't emulate the
+interrupt acknowledge phase of the CPU and automatically clears an interrupt
+request during interrupt processing.
+While this works for most systems, you may need more accurate interrupt
+handling.
+
+To add proper interrupt handling:
+
+- In m68kconf.h, set M68K_EMULATE_INT_ACK to OPT_SPECIFY_HANDLER
+
+- In m68kconf.h, set M68K_INT_ACK_CALLBACK(A) to your interrupt acknowledge
+  routine
+
+- Your interrupt acknowledge routine must return an interrupt vector,
+  M68K_INT_ACK_AUTOVECTOR, or M68K_INT_ACK_SPURIOUS.  most m68k
+  implementations just use autovectored interrupts.
+
+- When the interrupting device is satisfied, you must call m68k_set_irq(0) to
+  remove the interrupt request.
+
+
+
+MULTIPLE INTERRUPTS:
+-------------------
+The above system will work if you have only one device interrupting the CPU,
+but if you have more than one device, you must do a bit more.
+
+To add multiple interrupts:
+
+- You must make an interrupt arbitration device that will take the highest
+  priority interrupt and encode it onto the IRQ pins on the CPU.
+
+- The interrupt arbitration device should use m68k_set_irq() to set the
+  highest pending interrupt, or 0 for no interrupts pending.
+
+
+
+SEPARATE IMMEDIATE AND PC-RELATIVE READS:
+----------------------------------------
+You can write faster memory access functions if you know whether you are
+fetching from ROM or RAM.  Immediate reads are always from the program space
+(Always in ROM unless it is running self-modifying code).
+This will also separate the pc-relative reads, since some systems treat
+PROGRAM mode reads and DATA mode reads differently (for program encryption,
+for instance).  See the section below (ADDRESS SPACE) for an explanation of
+PROGRAM and DATA mode.
+
+To enable separate reads:
+
+- In m68kconf.h, turn on M68K_SEPARATE_READS.
+
+- In your host program, implement the following functions:
+    unsigned int  m68k_read_immediate_16(unsigned int address);
+    unsigned int  m68k_read_immediate_32(unsigned int address);
+
+    unsigned int  m68k_read_pcrelative_8(unsigned int address);
+    unsigned int  m68k_read_pcrelative_16(unsigned int address);
+    unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+- If you need to know the current PC (for banking and such), set
+  M68K_MONITOR_PC to OPT_SPECIFY_HANDLER, and set M68K_SET_PC_CALLBACK(A) to
+  your routine.
+
+
+
+ADDRESS SPACES:
+--------------
+Most systems will only implement one address space, placing ROM at the lower
+addresses and RAM at the higher.  However, there is the possibility that a
+system will implement ROM and RAM in the same address range, but in different
+address spaces, or will have different mamory types that require different
+handling for the program and the data.
+
+The 68k accomodates this by allowing different program spaces, the most
+important to us being PROGRAM and DATA space.  Here is a breakdown of
+how information is fetched:
+
+- All immediate reads are fetched from PROGRAM space.
+
+- All PC-relative reads are fetched from PROGRAM space.
+
+- The initial stack pointer and program counter are fetched from PROGRAM space.
+
+- All other reads (except for those from the moves instruction for 68020)
+   are fetched from DATA space.
+
+The m68k deals with this by encoding the requested address space on the
+function code pins:
+
+                       FC
+    Address Space      210
+    ------------------ ---
+    USER DATA          001
+    USER PROGRAM       010
+    SUPERVISOR DATA    101
+    SUPERVISOR PROGRAM 110
+    CPU SPACE          111 <-- not emulated in this core since we emulate
+                               interrupt acknowledge in another way.
+
+Problems arise here if you need to emulate this distinction (if, for example,
+your ROM and RAM are at the same address range, with RAM and ROM enable
+wired to the function code pins).
+
+There are 2 ways to deal with this situation using Musashi:
+
+1. If you only need the distinction between PROGRAM and DATA (the most common),
+   you can just separate the reads (see the preceeding section).  This is the
+   faster solution.
+
+2. You can emulate the function code pins entirely.
+
+To emulate the function code pins:
+
+- In m68kconf.h, set M68K_EMULATE_FC to OPT_SPECIFY_HANDLER and set
+  M68K_SET_FC_CALLBACK(A) to your function code handler function.
+
+- Your function code handler should select the proper address space for
+  subsequent calls to m68k_read_xx (and m68k_write_xx for 68010+).
+
+Note: immediate reads are always done from program space, so technically you
+      don't need to implement the separate immediate reads, although you could
+      gain more speed improvements leaving them in and doing some clever
+      programming.
+
+
+
+USING DIFFERENT CPU TYPES:
+-------------------------
+The default is to enable only the 68000 cpu type.  To change this, change the
+settings for M68K_EMULATE_010 etc in m68kconf.h.
+
+To set the CPU type you want to use:
+
+- Make sure it is enabled in m68kconf.h.  Current switches are:
+    M68K_EMULATE_010
+    M68K_EMULATE_EC020
+    M68K_EMULATE_020
+
+- In your host program, call m68k_set_cpu_type() and then call
+  m68k_pulse_reset().  Valid CPU types are:
+    M68K_CPU_TYPE_68000,
+    M68K_CPU_TYPE_68010,
+    M68K_CPU_TYPE_68EC020,
+    M68K_CPU_TYPE_68020
+
+
+
+CLOCK FREQUENCY:
+---------------
+In order to emulate the correct clock frequency, you will have to calculate
+how long it takes the emulation to execute a certain number of "cycles" and
+vary your calls to m68k_execute() accordingly.
+As well, it is a good idea to take away the CPU's timeslice when it writes to
+a memory-mapped port in order to give the device it wrote to a chance to
+react.
+
+You can use the functions m68k_cycles_run(), m68k_cycles_remaining(),
+m68k_modify_timeslice(), and m68k_end_timeslice() to do this.
+Try to use large cycle values in your calls to m68k_execute() since it will
+increase throughput.  You can always take away the timeslice later.
+
+
+
+MORE CORRECT EMULATION:
+----------------------
+You may need to enable these in order to properly emulate some of the more
+obscure functions of the m68k:
+
+- M68K_EMULATE_BKPT_ACK causes the CPU to call a breakpoint handler on a BKPT
+  instruction
+
+- M68K_EMULATE_TRACE causes the CPU to generate trace exceptions when the
+  trace bits are set
+
+- M68K_EMULATE_RESET causes the CPU to call a reset handler on a RESET
+  instruction.
+
+- M68K_EMULATE_PREFETCH emulates the 4-word instruction prefetch that is part
+  of the 68000/68010 (needed for Amiga emulation).
+
+- call m68k_pulse_halt() to emulate the HALT pin.
+
+
+
+CONVENIENCE FUNCTIONS:
+---------------------
+These are in here for programmer convenience:
+
+- M68K_INSTRUCTION_HOOK lets you call a handler before each instruction.
+
+- M68K_LOG_ENABLE and M68K_LOG_1010_1111 lets you log illegal and A/F-line
+  instructions.
+
+
+
+MULTIPLE CPU EMULATION:
+----------------------
+The default is to use only one CPU.  To use more than one CPU in this core,
+there are some things to keep in mind:
+
+- To have different cpus call different functions, use OPT_ON instead of
+  OPT_SPECIFY_HANDLER, and use the m68k_set_xxx_callback() functions to set
+  your callback handlers on a per-cpu basis.
+
+- Be sure to call set_cpu_type() for each CPU you use.
+
+- Use m68k_set_context() and m68k_get_context() to switch to another CPU.
+
+
+
+LOAD AND SAVE CPU CONTEXTS FROM DISK:
+------------------------------------
+You can use them68k_load_context() and m68k_save_context() functions to load
+and save the CPU state to disk.
+
+
+
+GET/SET INFORMATION FROM THE CPU:
+--------------------------------
+You can use m68k_get_reg() and m68k_set_reg() to gain access to the internals
+of the CPU.
+
+
+
+EXAMPLE:
+-------
+
+I have included a file example.zip that contains a full example.
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/Codes.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Codes.h
new file mode 100755
index 0000000..ab5cc6e
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Codes.h
@@ -0,0 +1,385 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Codes.h                        **/
+/**                                                         **/
+/** This file contains implementation for the main table of **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->HL.B.h);break;
+case ADD_L:    M_ADD(R->HL.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->HL.B.h);break;
+case SUB_L:    M_SUB(R->HL.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->HL.B.h);break;
+case AND_L:    M_AND(R->HL.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->HL.B.h);break;
+case OR_L:     M_OR(R->HL.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->HL.B.h);break;
+case ADC_L:    M_ADC(R->HL.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->HL.B.h);break;
+case SBC_L:    M_SBC(R->HL.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->HL.B.h);break;
+case XOR_L:    M_XOR(R->HL.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->HL.B.h);break;
+case CP_L:     M_CP(R->HL.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(HL);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->HL.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->HL.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(HL,BC);break;
+case ADD_HL_DE:  M_ADDW(HL,DE);break;
+case ADD_HL_HL:  M_ADDW(HL,HL);break;
+case ADD_HL_SP:  M_ADDW(HL,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->HL.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->HL.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->HL.B.h);break;
+case DEC_L:    M_DEC(R->HL.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->HL.B.h);break;
+case INC_L:    M_INC(R->HL.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+
+case RLCA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(HL);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(HL);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
+case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
+case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
+case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
+case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
+case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
+case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
+case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
+case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
+case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
+case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
+case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
+case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
+case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
+case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
+case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
+case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
+case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
+case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
+case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->HL.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->HL.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: WrZ80(R->HL.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++); 
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
+  R->HL.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
+
+default:
+  if(R->TrapBadOps)
+    printf
+    (
+      "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
+      (long)R->User,OpZ80(R->PC.W-1),R->PC.W-1
+    );
+  break;
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesCB.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesCB.h
new file mode 100755
index 0000000..dd904d4
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesCB.h
@@ -0,0 +1,204 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesCB.h                       **/
+/**                                                         **/
+/** This file contains implementation for the CB table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
+case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
+case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
+case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
+case RLC_A: M_RLC(R->AF.B.h);break;
+
+case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
+case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
+case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
+case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
+case RRC_A: M_RRC(R->AF.B.h);break;
+
+case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
+case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
+case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
+case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
+case RL_A: M_RL(R->AF.B.h);break;
+
+case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
+case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
+case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
+case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
+case RR_A: M_RR(R->AF.B.h);break;
+
+case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
+case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
+case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
+case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
+case SLA_A: M_SLA(R->AF.B.h);break;
+
+case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
+case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
+case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
+case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
+case SRA_A: M_SRA(R->AF.B.h);break;
+
+case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
+case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
+case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
+case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
+case SLL_A: M_SLL(R->AF.B.h);break;
+
+case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
+case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
+case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
+case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
+case SRL_A: M_SRL(R->AF.B.h);break;
+    
+case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
+case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
+case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
+case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,R->AF.B.h);break;
+
+case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
+case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
+case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
+case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,R->AF.B.h);break;
+
+case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
+case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
+case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
+case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,R->AF.B.h);break;
+
+case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
+case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
+case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
+case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,R->AF.B.h);break;
+
+case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
+case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
+case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
+case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,R->AF.B.h);break;
+
+case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
+case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
+case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
+case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,R->AF.B.h);break;
+
+case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
+case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
+case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
+case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,R->AF.B.h);break;
+
+case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
+case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
+case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
+case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,R->AF.B.h);break;
+
+case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
+case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
+case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
+case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
+case RES0_A: M_RES(0,R->AF.B.h);break;
+
+case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
+case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
+case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
+case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
+case RES1_A: M_RES(1,R->AF.B.h);break;
+
+case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
+case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
+case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
+case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
+case RES2_A: M_RES(2,R->AF.B.h);break;
+
+case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
+case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
+case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
+case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
+case RES3_A: M_RES(3,R->AF.B.h);break;
+
+case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
+case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
+case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
+case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
+case RES4_A: M_RES(4,R->AF.B.h);break;
+
+case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
+case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
+case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
+case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
+case RES5_A: M_RES(5,R->AF.B.h);break;
+
+case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
+case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
+case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
+case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
+case RES6_A: M_RES(6,R->AF.B.h);break;
+
+case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
+case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
+case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
+case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
+case RES7_A: M_RES(7,R->AF.B.h);break;
+
+case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
+case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
+case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
+case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
+case SET0_A: M_SET(0,R->AF.B.h);break;
+
+case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
+case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
+case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
+case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
+case SET1_A: M_SET(1,R->AF.B.h);break;
+
+case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
+case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
+case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
+case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
+case SET2_A: M_SET(2,R->AF.B.h);break;
+
+case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
+case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
+case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
+case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
+case SET3_A: M_SET(3,R->AF.B.h);break;
+
+case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
+case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
+case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
+case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
+case SET4_A: M_SET(4,R->AF.B.h);break;
+
+case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
+case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
+case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
+case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
+case SET5_A: M_SET(5,R->AF.B.h);break;
+
+case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
+case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
+case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
+case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
+case SET6_A: M_SET(6,R->AF.B.h);break;
+
+case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
+case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
+case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
+case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
+case SET7_A: M_SET(7,R->AF.B.h);break;
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesED.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesED.h
new file mode 100755
index 0000000..075ec99
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesED.h
@@ -0,0 +1,304 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesED.h                       **/
+/**                                                         **/
+/** This file contains implementation for the ED table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+/** This is a special patch for emulating BIOS calls: ********/
+case DB_FE:     PatchZ80(R);break;
+/*************************************************************/
+
+case ADC_HL_BC: M_ADCW(BC);break;
+case ADC_HL_DE: M_ADCW(DE);break;
+case ADC_HL_HL: M_ADCW(HL);break;
+case ADC_HL_SP: M_ADCW(SP);break;
+
+case SBC_HL_BC: M_SBCW(BC);break;
+case SBC_HL_DE: M_SBCW(DE);break;
+case SBC_HL_HL: M_SBCW(HL);break;
+case SBC_HL_SP: M_SBCW(SP);break;
+
+case LD_xWORDe_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+case LD_xWORDe_DE:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->DE.B.l);
+  WrZ80(J.W,R->DE.B.h);
+  break;
+case LD_xWORDe_BC:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->BC.B.l);
+  WrZ80(J.W,R->BC.B.h);
+  break;
+case LD_xWORDe_SP:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->SP.B.l);
+  WrZ80(J.W,R->SP.B.h);
+  break;
+
+case LD_HL_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+case LD_DE_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->DE.B.l=RdZ80(J.W++);
+  R->DE.B.h=RdZ80(J.W);
+  break;
+case LD_BC_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->BC.B.l=RdZ80(J.W++);
+  R->BC.B.h=RdZ80(J.W);
+  break;
+case LD_SP_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->SP.B.l=RdZ80(J.W++);
+  R->SP.B.h=RdZ80(J.W);
+  break;
+
+case RRD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I>>4)|(R->AF.B.h<<4);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+case RLD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+
+case LD_A_I:
+  R->AF.B.h=R->I;
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_A_R:
+  R->R++;
+  R->AF.B.h=(byte)(R->R-R->ICount);
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_I_A:   R->I=R->AF.B.h;break;
+case LD_R_A:   break;
+
+case IM_0:     R->IFF&=~(IFF_IM1|IFF_IM2);break;
+case IM_1:     R->IFF=(R->IFF&~IFF_IM2)|IFF_IM1;break;
+case IM_2:     R->IFF=(R->IFF&~IFF_IM1)|IFF_IM2;break;
+
+case RETI:
+case RETN:     if(R->IFF&IFF_2) R->IFF|=IFF_1; else R->IFF&=~IFF_1;
+               M_RET;break;
+
+case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+
+case IN_B_xC:  M_IN(R->BC.B.h);break;
+case IN_C_xC:  M_IN(R->BC.B.l);break;
+case IN_D_xC:  M_IN(R->DE.B.h);break;
+case IN_E_xC:  M_IN(R->DE.B.l);break;
+case IN_H_xC:  M_IN(R->HL.B.h);break;
+case IN_L_xC:  M_IN(R->HL.B.l);break;
+case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_F_xC:  M_IN(J.B.l);break;
+
+case OUT_xC_B: OutZ80(R->BC.W,R->BC.B.h);break;
+case OUT_xC_C: OutZ80(R->BC.W,R->BC.B.l);break;
+case OUT_xC_D: OutZ80(R->BC.W,R->DE.B.h);break;
+case OUT_xC_E: OutZ80(R->BC.W,R->DE.B.l);break;
+case OUT_xC_H: OutZ80(R->BC.W,R->HL.B.h);break;
+case OUT_xC_L: OutZ80(R->BC.W,R->HL.B.l);break;
+case OUT_xC_A: OutZ80(R->BC.W,R->AF.B.h);break;
+
+case INI:
+  WrZ80(R->HL.W++,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INIR:
+  do
+  {
+    WrZ80(R->HL.W++,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case IND:
+  WrZ80(R->HL.W--,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INDR:
+  do
+  {
+    WrZ80(R->HL.W--,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTI:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W++);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTIR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W++);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case OUTD:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W--);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTDR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W--);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case LDI:
+  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDIR:
+  do
+  {
+    WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case LDD:
+  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDDR:
+  do
+  {
+    WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case CPI:
+  I=RdZ80(R->HL.W++);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }  
+  while(R->BC.W&&J.B.l&&(R->ICount>0));
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;  
+
+case CPD:
+  I=RdZ80(R->HL.W--);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&J.B.l);
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXCB.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXCB.h
new file mode 100755
index 0000000..9a89306
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXCB.h
@@ -0,0 +1,64 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXCB.h                      **/
+/**                                                         **/
+/** This file contains implementation for FD/DD-CB tables   **/
+/** of Z80 commands. It is included from Z80.c.             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
+case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
+case RL_xHL:  I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
+case RR_xHL:  I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
+case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
+case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
+case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
+case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
+
+case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
+case BIT0_H: case BIT0_L: case BIT0_A:
+case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
+case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
+case BIT1_H: case BIT1_L: case BIT1_A:
+case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
+case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
+case BIT2_H: case BIT2_L: case BIT2_A:
+case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
+case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
+case BIT3_H: case BIT3_L: case BIT3_A:
+case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
+case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
+case BIT4_H: case BIT4_L: case BIT4_A:
+case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
+case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
+case BIT5_H: case BIT5_L: case BIT5_A:
+case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
+case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
+case BIT6_H: case BIT6_L: case BIT6_A:
+case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
+case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
+case BIT7_H: case BIT7_L: case BIT7_A:
+case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
+
+case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
+case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;   
+case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;   
+case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;   
+case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;   
+case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;   
+case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;   
+case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;   
+
+case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;   
+case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break; 
+case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break; 
+case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break; 
+case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break; 
+case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break; 
+case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break; 
+case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break; 
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXX.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXX.h
new file mode 100755
index 0000000..ad84f45
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/CodesXX.h
@@ -0,0 +1,396 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXX.h                       **/
+/**                                                         **/
+/** This file contains implementation for FD/DD tables of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->XX.B.h);break;
+case ADD_L:    M_ADD(R->XX.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->XX.B.h);break;
+case SUB_L:    M_SUB(R->XX.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->XX.B.h);break;
+case AND_L:    M_AND(R->XX.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->XX.B.h);break;
+case OR_L:     M_OR(R->XX.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->XX.B.h);break;
+case ADC_L:    M_ADC(R->XX.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->XX.B.h);break;
+case SBC_L:    M_SBC(R->XX.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->XX.B.h);break;
+case XOR_L:    M_XOR(R->XX.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->XX.B.h);break;
+case CP_L:     M_CP(R->XX.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(XX);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->XX.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->XX.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(XX,BC);break;
+case ADD_HL_DE:  M_ADDW(XX,DE);break;
+case ADD_HL_HL:  M_ADDW(XX,XX);break;
+case ADD_HL_SP:  M_ADDW(XX,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->XX.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->XX.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->XX.B.h);break;
+case DEC_L:    M_DEC(R->XX.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->XX.B.h);break;
+case INC_L:    M_INC(R->XX.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case RLCA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(XX);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(XX);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
+case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
+case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
+case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
+case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
+case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
+case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
+case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
+case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
+case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
+case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
+case LD_xHL_H: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
+case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
+case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
+case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
+case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
+case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
+case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
+case LD_xHL_L: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
+case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->XX.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->XX.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+                  WrZ80(J.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->XX.B.l);
+  WrZ80(J.W,R->XX.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->XX.B.l=RdZ80(J.W++);
+  R->XX.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
+  R->XX.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/ConDebug.c b/MCUME_pico2/picogen/gwenesis/cpus/Z80/ConDebug.c
new file mode 100755
index 0000000..92ab27a
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/ConDebug.c
@@ -0,0 +1,278 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                       ConDebug.c                        **/
+/**                                                         **/
+/** This file contains a console version of the built-in    **/
+/** debugger, using EMULib's Console.c. When -DCONDEBUG is  **/
+/** ommitted, ConDebug.c just includes the default command  **/
+/** line based debugger (Debug.c).                          **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2005-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#ifdef DEBUG
+
+#ifndef CONDEBUG
+/** Normal DebugZ80() ****************************************/
+/** When CONDEBUG #undefined, we use plain command line.    **/
+/*************************************************************/
+#include "Debug.c"
+
+#else
+/** Console DebugZ80() ***************************************/
+/** When CONDEBUG #defined, we use EMULib console.          **/
+/*************************************************************/
+
+#include "Z80.h"
+#include "Console.h"
+#include <stdlib.h>
+
+#define DebugZ80 OriginalDebugZ80
+#include "Debug.c"
+#undef DebugZ80
+
+#define CLR_BACK   PIXEL(255,255,255)
+#define CLR_TEXT   PIXEL(0,0,0)
+#define CLR_DIALOG PIXEL(0,100,0)
+#define CLR_PC     PIXEL(255,0,0)
+#define CLR_SP     PIXEL(0,0,100)
+
+static byte ChrDump(byte C)
+{
+  return((C>=32)&&(C<128)? C:'.');
+}
+ 
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers.                   **/
+/*************************************************************/
+byte DebugZ80(Z80 *R)
+{
+  char S[1024];
+  word A,Addr,ABuf[20];
+  int J,I,K,X,Y,MemoryDump,DrawWindow,ExitNow;
+
+  /* If we don't have enough screen estate... */
+  if((VideoW<32*8)||(VideoH<23*8))
+  {
+    /* Show warning message */
+    CONMsg(
+      -1,-1,-1,-1,PIXEL(255,255,255),PIXEL(255,0,0),
+      "Error","Screen is\0too small!\0\0"
+    );
+    /* Continue emulation */
+    R->Trace=0;
+    return(1);
+  }
+
+  X    = ((VideoW>>3)-32)>>1;
+  Y    = ((VideoH>>3)-23)>>1;
+  Addr = R->PC.W;
+  A    = ~Addr;
+  K    = 0;
+  
+  for(DrawWindow=1,MemoryDump=ExitNow=0;!ExitNow&&VideoImg;)
+  {
+    if(DrawWindow)
+    {
+      CONWindow(X,Y,32,23,CLR_TEXT,CLR_BACK,"Z80 Debugger");
+
+      sprintf(S,"PC %04X",R->PC.W);
+      CONSetColor(CLR_BACK,CLR_PC);
+      CONPrint(X+24,Y+18,S);
+      sprintf(S,"SP %04X",R->SP.W);
+      CONSetColor(CLR_BACK,CLR_SP);
+      CONPrint(X+24,Y+19,S);
+
+      CONSetColor(CLR_TEXT,CLR_BACK);
+      sprintf(S,
+        " %c%c%c%c%c%c\n\n"
+        "AF %04X\nBC %04X\nDE %04X\nHL %04X\nIX %04X\nIY %04X\n\n"
+        "AF'%04X\nBC'%04X\nDE'%04X\nHL'%04X\n\n"
+        "IR %02X%02X",
+        R->AF.B.l&0x80? 'S':'.',R->AF.B.l&0x40? 'Z':'.',R->AF.B.l&0x10? 'H':'.',
+        R->AF.B.l&0x04? 'P':'.',R->AF.B.l&0x02? 'N':'.',R->AF.B.l&0x01? 'C':'.',
+        R->AF.W,R->BC.W,R->DE.W,R->HL.W,
+        R->IX.W,R->IY.W,
+        R->AF1.W,R->BC1.W,R->DE1.W,R->HL1.W,
+        R->I,R->R
+      );
+      CONPrint(X+24,Y+2,S);
+      sprintf(S,
+        "%s %s",
+        R->IFF&0x04? "IM2":R->IFF&0x02? "IM1":"IM0",
+        R->IFF&0x01? "EI":"DI"
+      );
+      CONPrint(X+25,Y+21,S);
+      DrawWindow=0;
+      A=~Addr;
+    }
+
+    /* If top address has changed... */
+    if(A!=Addr)
+    {
+      /* Clear display */
+      CONBox((X+1)<<3,(Y+2)<<3,23*8,20*8,CLR_BACK);
+
+      if(MemoryDump)
+      {
+        /* Draw memory dump */
+        for(J=0,A=Addr;J<20;J++,A+=4)
+        {
+          if(A==R->PC.W)      CONSetColor(CLR_BACK,CLR_PC);
+          else if(A==R->SP.W) CONSetColor(CLR_BACK,CLR_SP);
+          else                CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,"%04X%c",A,A==R->PC.W? CON_MORE:A==R->SP.W? CON_LESS:':');
+          CONPrint(X+1,Y+J+2,S);
+
+          CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,
+            "%02X %02X %02X %02X %c%c%c%c",
+            RdZ80(A),RdZ80(A+1),RdZ80(A+2),RdZ80(A+3),
+            ChrDump(RdZ80(A)),ChrDump(RdZ80(A+1)),
+            ChrDump(RdZ80(A+2)),ChrDump(RdZ80(A+3))
+          );
+          CONPrint(X+7,Y+J+2,S);
+        }
+      }
+      else
+      {
+        /* Draw listing */
+        for(J=0,A=Addr;J<20;J++)
+        {
+          if(A==R->PC.W)      CONSetColor(CLR_BACK,CLR_PC);
+          else if(A==R->SP.W) CONSetColor(CLR_BACK,CLR_SP);
+          else                CONSetColor(CLR_TEXT,CLR_BACK);
+          sprintf(S,"%04X%c",A,A==R->PC.W? CON_MORE:A==R->SP.W? CON_LESS:':');
+          CONPrint(X+1,Y+J+2,S);
+
+          ABuf[J]=A;
+          A+=DAsm(S,A);
+
+          CONSetColor(CLR_TEXT,CLR_BACK);
+          CONPrintN(X+7,Y+J+2,S,23);
+        }
+      }
+
+      /* Display redrawn */
+      A=Addr;
+    }
+
+    /* Draw pointer */
+    CONChar(X+6,Y+K+2,CON_ARROW);
+
+    /* Show screen buffer */
+    ShowVideo();
+
+    /* Get key code */
+    I=WaitKey();
+
+    /* Clear pointer */
+    CONChar(X+6,Y+K+2,' ');
+
+    /* Get and process key code */
+    switch(I)
+    {
+      case 'H':
+        CONMsg(
+          -1,-1,-1,-1,
+          CLR_BACK,CLR_DIALOG,
+          "Debugger Help",
+          "ENTER - Execute next opcode\0"
+          "   UP - Previous opcode\0"
+          " DOWN - Next opcode\0"
+          " LEFT - Page up\0"
+          "RIGHT - Page down\0"
+          "    H - This help page\0"
+          "    G - Go to address\0"
+          "    D - Disassembler view\0"
+          "    M - Memory dump view\0"
+          "    S - Show stack\0"
+          "    J - Jump to cursor\0"
+          "    R - Run to cursor\0"
+          "    C - Continue execution\0"
+          "    Q - Quit emulator\0"
+        );
+        DrawWindow=1;
+        break;
+      case CON_UP:
+        if(K) --K;
+        else
+          if(MemoryDump) Addr-=4;
+          else for(--Addr;Addr+DAsm(S,Addr)>A;--Addr);
+        break;
+      case CON_DOWN:
+        if(K<19) ++K;
+        else
+          if(MemoryDump) Addr+=4;
+          else Addr+=DAsm(S,Addr);
+        break;
+      case CON_LEFT:
+        if(MemoryDump)
+          Addr-=4*20;
+        else
+        {
+          for(I=20,Addr=~A;(Addr>A)||((A^Addr)&~Addr&0x8000);++I)
+            for(J=0,Addr=A-I;J<20;++J) Addr+=DAsm(S,Addr);
+          Addr=A-I+1;
+        }
+        break; 
+      case CON_RIGHT:
+        if(MemoryDump)
+          Addr+=4*20;
+        else
+          for(J=0;J<20;++J) Addr+=DAsm(S,Addr);
+        break;
+      case CON_OK:
+        ExitNow=1;
+        break;
+      case 'Q':
+        return(0);
+      case CON_EXIT:
+      case 'C':
+        R->Trap=0xFFFF;
+        R->Trace=0;
+        ExitNow=1;
+        break;
+      case 'R':
+        R->Trap=ABuf[K];
+        R->Trace=0;
+        ExitNow=1;
+        break;
+      case 'M':
+        MemoryDump=1;
+        A=~Addr;
+        break;
+      case 'S':
+        MemoryDump=1;
+        Addr=R->SP.W;
+        K=0;
+        A=~Addr;
+        break;
+      case 'D':
+        MemoryDump=0;
+        A=~Addr;
+        break;        
+      case 'G':
+        if(CONInput(-1,-1,CLR_BACK,CLR_DIALOG,"Go to Address:",S,5|CON_HEX))
+        { Addr=strtol(S,0,16);K=0; }
+        DrawWindow=1;
+        break;
+      case 'J':
+        R->PC.W=ABuf[K];
+        A=~Addr;
+        break;
+    }
+  }
+
+  /* Continue emulation */
+  return(1);
+}
+
+#endif /* CONDEBUG */
+#endif /* DEBUG */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/Debug.c b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Debug.c
new file mode 100755
index 0000000..9c843e9
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Debug.c
@@ -0,0 +1,436 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         Debug.c                         **/
+/**                                                         **/
+/** This file contains the built-in debugging routine for   **/
+/** the Z80 emulator which is called on each Z80 step when  **/
+/** Trap!=0.                                                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1995-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#ifdef DEBUG
+
+#include "Z80.h"
+
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+
+#ifdef FMSX
+#include "AY8910.h"
+extern AY8910 PSG;
+#endif
+
+static const char *Mnemonics[256] =
+{
+  "NOP","LD BC,#h","LD (BC),A","INC BC","INC B","DEC B","LD B,*h","RLCA",
+  "EX AF,AF'","ADD HL,BC","LD A,(BC)","DEC BC","INC C","DEC C","LD C,*h","RRCA",
+  "DJNZ @h","LD DE,#h","LD (DE),A","INC DE","INC D","DEC D","LD D,*h","RLA",
+  "JR @h","ADD HL,DE","LD A,(DE)","DEC DE","INC E","DEC E","LD E,*h","RRA",
+  "JR NZ,@h","LD HL,#h","LD (#h),HL","INC HL","INC H","DEC H","LD H,*h","DAA",
+  "JR Z,@h","ADD HL,HL","LD HL,(#h)","DEC HL","INC L","DEC L","LD L,*h","CPL",
+  "JR NC,@h","LD SP,#h","LD (#h),A","INC SP","INC (HL)","DEC (HL)","LD (HL),*h","SCF",
+  "JR C,@h","ADD HL,SP","LD A,(#h)","DEC SP","INC A","DEC A","LD A,*h","CCF",
+  "LD B,B","LD B,C","LD B,D","LD B,E","LD B,H","LD B,L","LD B,(HL)","LD B,A",
+  "LD C,B","LD C,C","LD C,D","LD C,E","LD C,H","LD C,L","LD C,(HL)","LD C,A",
+  "LD D,B","LD D,C","LD D,D","LD D,E","LD D,H","LD D,L","LD D,(HL)","LD D,A",
+  "LD E,B","LD E,C","LD E,D","LD E,E","LD E,H","LD E,L","LD E,(HL)","LD E,A",
+  "LD H,B","LD H,C","LD H,D","LD H,E","LD H,H","LD H,L","LD H,(HL)","LD H,A",
+  "LD L,B","LD L,C","LD L,D","LD L,E","LD L,H","LD L,L","LD L,(HL)","LD L,A",
+  "LD (HL),B","LD (HL),C","LD (HL),D","LD (HL),E","LD (HL),H","LD (HL),L","HALT","LD (HL),A",
+  "LD A,B","LD A,C","LD A,D","LD A,E","LD A,H","LD A,L","LD A,(HL)","LD A,A",
+  "ADD B","ADD C","ADD D","ADD E","ADD H","ADD L","ADD (HL)","ADD A",
+  "ADC B","ADC C","ADC D","ADC E","ADC H","ADC L","ADC (HL)","ADC A",
+  "SUB B","SUB C","SUB D","SUB E","SUB H","SUB L","SUB (HL)","SUB A",
+  "SBC B","SBC C","SBC D","SBC E","SBC H","SBC L","SBC (HL)","SBC A",
+  "AND B","AND C","AND D","AND E","AND H","AND L","AND (HL)","AND A",
+  "XOR B","XOR C","XOR D","XOR E","XOR H","XOR L","XOR (HL)","XOR A",
+  "OR B","OR C","OR D","OR E","OR H","OR L","OR (HL)","OR A",
+  "CP B","CP C","CP D","CP E","CP H","CP L","CP (HL)","CP A",
+  "RET NZ","POP BC","JP NZ,#h","JP #h","CALL NZ,#h","PUSH BC","ADD *h","RST 00h",
+  "RET Z","RET","JP Z,#h","PFX_CB","CALL Z,#h","CALL #h","ADC *h","RST 08h",
+  "RET NC","POP DE","JP NC,#h","OUTA (*h)","CALL NC,#h","PUSH DE","SUB *h","RST 10h",
+  "RET C","EXX","JP C,#h","INA (*h)","CALL C,#h","PFX_DD","SBC *h","RST 18h",
+  "RET PO","POP HL","JP PO,#h","EX HL,(SP)","CALL PO,#h","PUSH HL","AND *h","RST 20h",
+  "RET PE","LD PC,HL","JP PE,#h","EX DE,HL","CALL PE,#h","PFX_ED","XOR *h","RST 28h",
+  "RET P","POP AF","JP P,#h","DI","CALL P,#h","PUSH AF","OR *h","RST 30h",
+  "RET M","LD SP,HL","JP M,#h","EI","CALL M,#h","PFX_FD","CP *h","RST 38h"
+};
+
+static const char *MnemonicsCB[256] =
+{
+  "RLC B","RLC C","RLC D","RLC E","RLC H","RLC L","RLC (HL)","RLC A",
+  "RRC B","RRC C","RRC D","RRC E","RRC H","RRC L","RRC (HL)","RRC A",
+  "RL B","RL C","RL D","RL E","RL H","RL L","RL (HL)","RL A",
+  "RR B","RR C","RR D","RR E","RR H","RR L","RR (HL)","RR A",
+  "SLA B","SLA C","SLA D","SLA E","SLA H","SLA L","SLA (HL)","SLA A",
+  "SRA B","SRA C","SRA D","SRA E","SRA H","SRA L","SRA (HL)","SRA A",
+  "SLL B","SLL C","SLL D","SLL E","SLL H","SLL L","SLL (HL)","SLL A",
+  "SRL B","SRL C","SRL D","SRL E","SRL H","SRL L","SRL (HL)","SRL A",
+  "BIT 0,B","BIT 0,C","BIT 0,D","BIT 0,E","BIT 0,H","BIT 0,L","BIT 0,(HL)","BIT 0,A",
+  "BIT 1,B","BIT 1,C","BIT 1,D","BIT 1,E","BIT 1,H","BIT 1,L","BIT 1,(HL)","BIT 1,A",
+  "BIT 2,B","BIT 2,C","BIT 2,D","BIT 2,E","BIT 2,H","BIT 2,L","BIT 2,(HL)","BIT 2,A",
+  "BIT 3,B","BIT 3,C","BIT 3,D","BIT 3,E","BIT 3,H","BIT 3,L","BIT 3,(HL)","BIT 3,A",
+  "BIT 4,B","BIT 4,C","BIT 4,D","BIT 4,E","BIT 4,H","BIT 4,L","BIT 4,(HL)","BIT 4,A",
+  "BIT 5,B","BIT 5,C","BIT 5,D","BIT 5,E","BIT 5,H","BIT 5,L","BIT 5,(HL)","BIT 5,A",
+  "BIT 6,B","BIT 6,C","BIT 6,D","BIT 6,E","BIT 6,H","BIT 6,L","BIT 6,(HL)","BIT 6,A",
+  "BIT 7,B","BIT 7,C","BIT 7,D","BIT 7,E","BIT 7,H","BIT 7,L","BIT 7,(HL)","BIT 7,A",
+  "RES 0,B","RES 0,C","RES 0,D","RES 0,E","RES 0,H","RES 0,L","RES 0,(HL)","RES 0,A",
+  "RES 1,B","RES 1,C","RES 1,D","RES 1,E","RES 1,H","RES 1,L","RES 1,(HL)","RES 1,A",
+  "RES 2,B","RES 2,C","RES 2,D","RES 2,E","RES 2,H","RES 2,L","RES 2,(HL)","RES 2,A",
+  "RES 3,B","RES 3,C","RES 3,D","RES 3,E","RES 3,H","RES 3,L","RES 3,(HL)","RES 3,A",
+  "RES 4,B","RES 4,C","RES 4,D","RES 4,E","RES 4,H","RES 4,L","RES 4,(HL)","RES 4,A",
+  "RES 5,B","RES 5,C","RES 5,D","RES 5,E","RES 5,H","RES 5,L","RES 5,(HL)","RES 5,A",
+  "RES 6,B","RES 6,C","RES 6,D","RES 6,E","RES 6,H","RES 6,L","RES 6,(HL)","RES 6,A",
+  "RES 7,B","RES 7,C","RES 7,D","RES 7,E","RES 7,H","RES 7,L","RES 7,(HL)","RES 7,A",
+  "SET 0,B","SET 0,C","SET 0,D","SET 0,E","SET 0,H","SET 0,L","SET 0,(HL)","SET 0,A",
+  "SET 1,B","SET 1,C","SET 1,D","SET 1,E","SET 1,H","SET 1,L","SET 1,(HL)","SET 1,A",
+  "SET 2,B","SET 2,C","SET 2,D","SET 2,E","SET 2,H","SET 2,L","SET 2,(HL)","SET 2,A",
+  "SET 3,B","SET 3,C","SET 3,D","SET 3,E","SET 3,H","SET 3,L","SET 3,(HL)","SET 3,A",
+  "SET 4,B","SET 4,C","SET 4,D","SET 4,E","SET 4,H","SET 4,L","SET 4,(HL)","SET 4,A",
+  "SET 5,B","SET 5,C","SET 5,D","SET 5,E","SET 5,H","SET 5,L","SET 5,(HL)","SET 5,A",
+  "SET 6,B","SET 6,C","SET 6,D","SET 6,E","SET 6,H","SET 6,L","SET 6,(HL)","SET 6,A",
+  "SET 7,B","SET 7,C","SET 7,D","SET 7,E","SET 7,H","SET 7,L","SET 7,(HL)","SET 7,A"
+};
+
+static const char *MnemonicsED[256] =
+{
+  "DB EDh,00h","DB EDh,01h","DB EDh,02h","DB EDh,03h",
+  "DB EDh,04h","DB EDh,05h","DB EDh,06h","DB EDh,07h",
+  "DB EDh,08h","DB EDh,09h","DB EDh,0Ah","DB EDh,0Bh",
+  "DB EDh,0Ch","DB EDh,0Dh","DB EDh,0Eh","DB EDh,0Fh",
+  "DB EDh,10h","DB EDh,11h","DB EDh,12h","DB EDh,13h",
+  "DB EDh,14h","DB EDh,15h","DB EDh,16h","DB EDh,17h",
+  "DB EDh,18h","DB EDh,19h","DB EDh,1Ah","DB EDh,1Bh",
+  "DB EDh,1Ch","DB EDh,1Dh","DB EDh,1Eh","DB EDh,1Fh",
+  "DB EDh,20h","DB EDh,21h","DB EDh,22h","DB EDh,23h",
+  "DB EDh,24h","DB EDh,25h","DB EDh,26h","DB EDh,27h",
+  "DB EDh,28h","DB EDh,29h","DB EDh,2Ah","DB EDh,2Bh",
+  "DB EDh,2Ch","DB EDh,2Dh","DB EDh,2Eh","DB EDh,2Fh",
+  "DB EDh,30h","DB EDh,31h","DB EDh,32h","DB EDh,33h",
+  "DB EDh,34h","DB EDh,35h","DB EDh,36h","DB EDh,37h",
+  "DB EDh,38h","DB EDh,39h","DB EDh,3Ah","DB EDh,3Bh",
+  "DB EDh,3Ch","DB EDh,3Dh","DB EDh,3Eh","DB EDh,3Fh",
+  "IN B,(C)","OUT (C),B","SBC HL,BC","LD (#h),BC",
+  "NEG","RETN","IM 0","LD I,A",
+  "IN C,(C)","OUT (C),C","ADC HL,BC","LD BC,(#h)",
+  "DB EDh,4Ch","RETI","DB EDh,4Eh","LD R,A",
+  "IN D,(C)","OUT (C),D","SBC HL,DE","LD (#h),DE",
+  "DB EDh,54h","DB EDh,55h","IM 1","LD A,I",
+  "IN E,(C)","OUT (C),E","ADC HL,DE","LD DE,(#h)",
+  "DB EDh,5Ch","DB EDh,5Dh","IM 2","LD A,R",
+  "IN H,(C)","OUT (C),H","SBC HL,HL","LD (#h),HL",
+  "DB EDh,64h","DB EDh,65h","DB EDh,66h","RRD",
+  "IN L,(C)","OUT (C),L","ADC HL,HL","LD HL,(#h)",
+  "DB EDh,6Ch","DB EDh,6Dh","DB EDh,6Eh","RLD",
+  "IN F,(C)","DB EDh,71h","SBC HL,SP","LD (#h),SP",
+  "DB EDh,74h","DB EDh,75h","DB EDh,76h","DB EDh,77h",
+  "IN A,(C)","OUT (C),A","ADC HL,SP","LD SP,(#h)",
+  "DB EDh,7Ch","DB EDh,7Dh","DB EDh,7Eh","DB EDh,7Fh",
+  "DB EDh,80h","DB EDh,81h","DB EDh,82h","DB EDh,83h",
+  "DB EDh,84h","DB EDh,85h","DB EDh,86h","DB EDh,87h",
+  "DB EDh,88h","DB EDh,89h","DB EDh,8Ah","DB EDh,8Bh",
+  "DB EDh,8Ch","DB EDh,8Dh","DB EDh,8Eh","DB EDh,8Fh",
+  "DB EDh,90h","DB EDh,91h","DB EDh,92h","DB EDh,93h",
+  "DB EDh,94h","DB EDh,95h","DB EDh,96h","DB EDh,97h",
+  "DB EDh,98h","DB EDh,99h","DB EDh,9Ah","DB EDh,9Bh",
+  "DB EDh,9Ch","DB EDh,9Dh","DB EDh,9Eh","DB EDh,9Fh",
+  "LDI","CPI","INI","OUTI",
+  "DB EDh,A4h","DB EDh,A5h","DB EDh,A6h","DB EDh,A7h",
+  "LDD","CPD","IND","OUTD",
+  "DB EDh,ACh","DB EDh,ADh","DB EDh,AEh","DB EDh,AFh",
+  "LDIR","CPIR","INIR","OTIR",
+  "DB EDh,B4h","DB EDh,B5h","DB EDh,B6h","DB EDh,B7h",
+  "LDDR","CPDR","INDR","OTDR",
+  "DB EDh,BCh","DB EDh,BDh","DB EDh,BEh","DB EDh,BFh",
+  "DB EDh,C0h","DB EDh,C1h","DB EDh,C2h","DB EDh,C3h",
+  "DB EDh,C4h","DB EDh,C5h","DB EDh,C6h","DB EDh,C7h",
+  "DB EDh,C8h","DB EDh,C9h","DB EDh,CAh","DB EDh,CBh",
+  "DB EDh,CCh","DB EDh,CDh","DB EDh,CEh","DB EDh,CFh",
+  "DB EDh,D0h","DB EDh,D1h","DB EDh,D2h","DB EDh,D3h",
+  "DB EDh,D4h","DB EDh,D5h","DB EDh,D6h","DB EDh,D7h",
+  "DB EDh,D8h","DB EDh,D9h","DB EDh,DAh","DB EDh,DBh",
+  "DB EDh,DCh","DB EDh,DDh","DB EDh,DEh","DB EDh,DFh",
+  "DB EDh,E0h","DB EDh,E1h","DB EDh,E2h","DB EDh,E3h",
+  "DB EDh,E4h","DB EDh,E5h","DB EDh,E6h","DB EDh,E7h",
+  "DB EDh,E8h","DB EDh,E9h","DB EDh,EAh","DB EDh,EBh",
+  "DB EDh,ECh","DB EDh,EDh","DB EDh,EEh","DB EDh,EFh",
+  "DB EDh,F0h","DB EDh,F1h","DB EDh,F2h","DB EDh,F3h",
+  "DB EDh,F4h","DB EDh,F5h","DB EDh,F6h","DB EDh,F7h",
+  "DB EDh,F8h","DB EDh,F9h","DB EDh,FAh","DB EDh,FBh",
+  "DB EDh,FCh","DB EDh,FDh","DB EDh,FEh","DB EDh,FFh"
+};
+
+static const char *MnemonicsXX[256] =
+{
+  "NOP","LD BC,#h","LD (BC),A","INC BC","INC B","DEC B","LD B,*h","RLCA",
+  "EX AF,AF'","ADD I%,BC","LD A,(BC)","DEC BC","INC C","DEC C","LD C,*h","RRCA",
+  "DJNZ @h","LD DE,#h","LD (DE),A","INC DE","INC D","DEC D","LD D,*h","RLA",
+  "JR @h","ADD I%,DE","LD A,(DE)","DEC DE","INC E","DEC E","LD E,*h","RRA",
+  "JR NZ,@h","LD I%,#h","LD (#h),I%","INC I%","INC I%h","DEC I%h","LD I%h,*h","DAA",
+  "JR Z,@h","ADD I%,I%","LD I%,(#h)","DEC I%","INC I%l","DEC I%l","LD I%l,*h","CPL",
+  "JR NC,@h","LD SP,#h","LD (#h),A","INC SP","INC (I%+^h)","DEC (I%+^h)","LD (I%+^h),*h","SCF",
+  "JR C,@h","ADD I%,SP","LD A,(#h)","DEC SP","INC A","DEC A","LD A,*h","CCF",
+  "LD B,B","LD B,C","LD B,D","LD B,E","LD B,I%h","LD B,I%l","LD B,(I%+^h)","LD B,A",
+  "LD C,B","LD C,C","LD C,D","LD C,E","LD C,I%h","LD C,I%l","LD C,(I%+^h)","LD C,A",
+  "LD D,B","LD D,C","LD D,D","LD D,E","LD D,I%h","LD D,I%l","LD D,(I%+^h)","LD D,A",
+  "LD E,B","LD E,C","LD E,D","LD E,E","LD E,I%h","LD E,I%l","LD E,(I%+^h)","LD E,A",
+  "LD I%h,B","LD I%h,C","LD I%h,D","LD I%h,E","LD I%h,I%h","LD I%h,I%l","LD H,(I%+^h)","LD I%h,A",
+  "LD I%l,B","LD I%l,C","LD I%l,D","LD I%l,E","LD I%l,I%h","LD I%l,I%l","LD L,(I%+^h)","LD I%l,A",
+  "LD (I%+^h),B","LD (I%+^h),C","LD (I%+^h),D","LD (I%+^h),E","LD (I%+^h),H","LD (I%+^h),L","HALT","LD (I%+^h),A",
+  "LD A,B","LD A,C","LD A,D","LD A,E","LD A,I%h","LD A,I%l","LD A,(I%+^h)","LD A,A",
+  "ADD B","ADD C","ADD D","ADD E","ADD I%h","ADD I%l","ADD (I%+^h)","ADD A",
+  "ADC B","ADC C","ADC D","ADC E","ADC I%h","ADC I%l","ADC (I%+^h)","ADC,A",
+  "SUB B","SUB C","SUB D","SUB E","SUB I%h","SUB I%l","SUB (I%+^h)","SUB A",
+  "SBC B","SBC C","SBC D","SBC E","SBC I%h","SBC I%l","SBC (I%+^h)","SBC A",
+  "AND B","AND C","AND D","AND E","AND I%h","AND I%l","AND (I%+^h)","AND A",
+  "XOR B","XOR C","XOR D","XOR E","XOR I%h","XOR I%l","XOR (I%+^h)","XOR A",
+  "OR B","OR C","OR D","OR E","OR I%h","OR I%l","OR (I%+^h)","OR A",
+  "CP B","CP C","CP D","CP E","CP I%h","CP I%l","CP (I%+^h)","CP A",
+  "RET NZ","POP BC","JP NZ,#h","JP #h","CALL NZ,#h","PUSH BC","ADD *h","RST 00h",
+  "RET Z","RET","JP Z,#h","PFX_CB","CALL Z,#h","CALL #h","ADC *h","RST 08h",
+  "RET NC","POP DE","JP NC,#h","OUTA (*h)","CALL NC,#h","PUSH DE","SUB *h","RST 10h",
+  "RET C","EXX","JP C,#h","INA (*h)","CALL C,#h","PFX_DD","SBC *h","RST 18h",
+  "RET PO","POP I%","JP PO,#h","EX I%,(SP)","CALL PO,#h","PUSH I%","AND *h","RST 20h",
+  "RET PE","LD PC,I%","JP PE,#h","EX DE,I%","CALL PE,#h","PFX_ED","XOR *h","RST 28h",
+  "RET P","POP AF","JP P,#h","DI","CALL P,#h","PUSH AF","OR *h","RST 30h",
+  "RET M","LD SP,I%","JP M,#h","EI","CALL M,#h","PFX_FD","CP *h","RST 38h"
+};
+
+static const char *MnemonicsXCB[256] =
+{
+  "RLC B","RLC C","RLC D","RLC E","RLC H","RLC L","RLC (I%@h)","RLC A",
+  "RRC B","RRC C","RRC D","RRC E","RRC H","RRC L","RRC (I%@h)","RRC A",
+  "RL B","RL C","RL D","RL E","RL H","RL L","RL (I%@h)","RL A",
+  "RR B","RR C","RR D","RR E","RR H","RR L","RR (I%@h)","RR A",
+  "SLA B","SLA C","SLA D","SLA E","SLA H","SLA L","SLA (I%@h)","SLA A",
+  "SRA B","SRA C","SRA D","SRA E","SRA H","SRA L","SRA (I%@h)","SRA A",
+  "SLL B","SLL C","SLL D","SLL E","SLL H","SLL L","SLL (I%@h)","SLL A",
+  "SRL B","SRL C","SRL D","SRL E","SRL H","SRL L","SRL (I%@h)","SRL A",
+  "BIT 0,B","BIT 0,C","BIT 0,D","BIT 0,E","BIT 0,H","BIT 0,L","BIT 0,(I%@h)","BIT 0,A",
+  "BIT 1,B","BIT 1,C","BIT 1,D","BIT 1,E","BIT 1,H","BIT 1,L","BIT 1,(I%@h)","BIT 1,A",
+  "BIT 2,B","BIT 2,C","BIT 2,D","BIT 2,E","BIT 2,H","BIT 2,L","BIT 2,(I%@h)","BIT 2,A",
+  "BIT 3,B","BIT 3,C","BIT 3,D","BIT 3,E","BIT 3,H","BIT 3,L","BIT 3,(I%@h)","BIT 3,A",
+  "BIT 4,B","BIT 4,C","BIT 4,D","BIT 4,E","BIT 4,H","BIT 4,L","BIT 4,(I%@h)","BIT 4,A",
+  "BIT 5,B","BIT 5,C","BIT 5,D","BIT 5,E","BIT 5,H","BIT 5,L","BIT 5,(I%@h)","BIT 5,A",
+  "BIT 6,B","BIT 6,C","BIT 6,D","BIT 6,E","BIT 6,H","BIT 6,L","BIT 6,(I%@h)","BIT 6,A",
+  "BIT 7,B","BIT 7,C","BIT 7,D","BIT 7,E","BIT 7,H","BIT 7,L","BIT 7,(I%@h)","BIT 7,A",
+  "RES 0,B","RES 0,C","RES 0,D","RES 0,E","RES 0,H","RES 0,L","RES 0,(I%@h)","RES 0,A",
+  "RES 1,B","RES 1,C","RES 1,D","RES 1,E","RES 1,H","RES 1,L","RES 1,(I%@h)","RES 1,A",
+  "RES 2,B","RES 2,C","RES 2,D","RES 2,E","RES 2,H","RES 2,L","RES 2,(I%@h)","RES 2,A",
+  "RES 3,B","RES 3,C","RES 3,D","RES 3,E","RES 3,H","RES 3,L","RES 3,(I%@h)","RES 3,A",
+  "RES 4,B","RES 4,C","RES 4,D","RES 4,E","RES 4,H","RES 4,L","RES 4,(I%@h)","RES 4,A",
+  "RES 5,B","RES 5,C","RES 5,D","RES 5,E","RES 5,H","RES 5,L","RES 5,(I%@h)","RES 5,A",
+  "RES 6,B","RES 6,C","RES 6,D","RES 6,E","RES 6,H","RES 6,L","RES 6,(I%@h)","RES 6,A",
+  "RES 7,B","RES 7,C","RES 7,D","RES 7,E","RES 7,H","RES 7,L","RES 7,(I%@h)","RES 7,A",
+  "SET 0,B","SET 0,C","SET 0,D","SET 0,E","SET 0,H","SET 0,L","SET 0,(I%@h)","SET 0,A",
+  "SET 1,B","SET 1,C","SET 1,D","SET 1,E","SET 1,H","SET 1,L","SET 1,(I%@h)","SET 1,A",
+  "SET 2,B","SET 2,C","SET 2,D","SET 2,E","SET 2,H","SET 2,L","SET 2,(I%@h)","SET 2,A",
+  "SET 3,B","SET 3,C","SET 3,D","SET 3,E","SET 3,H","SET 3,L","SET 3,(I%@h)","SET 3,A",
+  "SET 4,B","SET 4,C","SET 4,D","SET 4,E","SET 4,H","SET 4,L","SET 4,(I%@h)","SET 4,A",
+  "SET 5,B","SET 5,C","SET 5,D","SET 5,E","SET 5,H","SET 5,L","SET 5,(I%@h)","SET 5,A",
+  "SET 6,B","SET 6,C","SET 6,D","SET 6,E","SET 6,H","SET 6,L","SET 6,(I%@h)","SET 6,A",
+  "SET 7,B","SET 7,C","SET 7,D","SET 7,E","SET 7,H","SET 7,L","SET 7,(I%@h)","SET 7,A"
+};
+
+/** DAsm() ***************************************************/
+/** DAsm() will disassemble the code at adress A and put    **/
+/** the output text into S. It will return the number of    **/
+/** bytes disassembled.                                     **/
+/*************************************************************/
+static int DAsm(char *S,word A)
+{
+  char R[128],H[10],C,*P;
+  const char *T;
+  byte J,Offset;
+  word B;
+
+  Offset=0;
+  B=A;
+  C='\0';
+  J=0;
+
+  switch(RdZ80(B))
+  {
+    case 0xCB: B++;T=MnemonicsCB[RdZ80(B++)];break;
+    case 0xED: B++;T=MnemonicsED[RdZ80(B++)];break;
+    case 0xDD: B++;C='X';
+               if(RdZ80(B)!=0xCB) T=MnemonicsXX[RdZ80(B++)];
+               else
+               { B++;Offset=RdZ80(B++);J=1;T=MnemonicsXCB[RdZ80(B++)]; }
+               break;
+    case 0xFD: B++;C='Y';
+               if(RdZ80(B)!=0xCB) T=MnemonicsXX[RdZ80(B++)];
+               else
+               { B++;Offset=RdZ80(B++);J=1;T=MnemonicsXCB[RdZ80(B++)]; }
+               break;
+    default:   T=Mnemonics[RdZ80(B++)];
+  }
+
+  if(P=strchr(T,'^'))
+  {
+    strncpy(R,T,P-T);R[P-T]='\0';
+    sprintf(H,"%02X",RdZ80(B++));
+    strcat(R,H);strcat(R,P+1);
+  }
+  else strcpy(R,T);
+  if(P=strchr(R,'%')) *P=C;
+
+  if(P=strchr(R,'*'))
+  {
+    strncpy(S,R,P-R);S[P-R]='\0';
+    sprintf(H,"%02X",RdZ80(B++));
+    strcat(S,H);strcat(S,P+1);
+  }
+  else
+    if(P=strchr(R,'@'))
+    {
+      strncpy(S,R,P-R);S[P-R]='\0';
+      if(!J) Offset=RdZ80(B++);
+      strcat(S,Offset&0x80? "-":"+");
+      J=Offset&0x80? 256-Offset:Offset;
+      sprintf(H,"%02X",J);
+      strcat(S,H);strcat(S,P+1);
+    }
+    else
+      if(P=strchr(R,'#'))
+      {
+        strncpy(S,R,P-R);S[P-R]='\0';
+        sprintf(H,"%04X",RdZ80(B)+256*RdZ80(B+1));
+        strcat(S,H);strcat(S,P+1);
+        B+=2;
+      }
+      else strcpy(S,R);
+
+  return(B-A);
+}
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers.                   **/
+/*************************************************************/
+byte DebugZ80(Z80 *R)
+{
+  static const char Flags[9] = "SZ.H.PNC";
+  char S[128],T[10];
+  byte J,I;
+
+  DAsm(S,R->PC.W);
+  for(J=0,I=R->AF.B.l;J<8;J++,I<<=1) T[J]=I&0x80? Flags[J]:'.';
+  T[8]='\0';
+
+  printf
+  (
+    "AF:%04X HL:%04X DE:%04X BC:%04X PC:%04X SP:%04X IX:%04X IY:%04X I:%02X\n",
+    R->AF.W,R->HL.W,R->DE.W,R->BC.W,R->PC.W,R->SP.W,R->IX.W,R->IY.W,R->I
+  ); 
+  printf
+  ( 
+    "AT PC: [%02X - %s]   AT SP: [%04X]   FLAGS: [%s]   %s: %s\n\n",
+    RdZ80(R->PC.W),S,RdZ80(R->SP.W)+RdZ80(R->SP.W+1)*256,T,
+    R->IFF&0x04? "IM2":R->IFF&0x02? "IM1":"IM0",
+    R->IFF&0x01? "EI":"DI"
+  );
+
+  while(1)
+  {
+    printf("\n[Command,'?']-> ");
+    fflush(stdout);fflush(stdin);
+
+    fgets(S,50,stdin);
+    for(J=0;S[J]>=' ';J++)
+      S[J]=toupper(S[J]);
+    S[J]='\0';
+
+    switch(S[0])
+    {
+      case 'H':
+      case '?':
+        puts("\n***** Built-in Z80 Debugger Commands *****");
+        puts("<CR>       : Break at next instruction");
+        puts("= <addr>   : Break at addr");
+        puts("+ <offset> : Break at PC + offset");
+        puts("c          : Continue without break");
+        puts("j <addr>   : Continue from addr");
+        puts("m <addr>   : Memory dump at addr");
+        puts("d <addr>   : Disassembly at addr");
+        puts("?,h        : Show this help text");
+        puts("q          : Exit Z80 emulation");
+        break;
+
+      case '\0': return(1);
+      case '=':  if(strlen(S)>=2)
+                 { sscanf(S+1,"%hX",&(R->Trap));R->Trace=0;return(1); }
+                 break;
+      case '+':  if(strlen(S)>=2)
+                 {
+                   sscanf(S+1,"%hX",&(R->Trap));
+                   R->Trap+=R->PC.W;R->Trace=0;
+                   return(1);
+                 }
+                 break;
+      case 'J':  if(strlen(S)>=2)
+                 { sscanf(S+1,"%hX",&(R->PC.W));R->Trace=0;return(1); }
+                 break;
+      case 'C':  R->Trap=0xFFFF;R->Trace=0;return(1); 
+      case 'Q':  return(0);
+
+      case 'M':
+        {
+          word Addr;
+
+          if(strlen(S)>1) sscanf(S+1,"%hX",&Addr); else Addr=R->PC.W;
+          puts("");
+          for(J=0;J<16;J++)
+          {
+            printf("%04X: ",Addr);
+            for(I=0;I<16;I++,Addr++)
+              printf("%02X ",RdZ80(Addr));
+            printf(" | ");Addr-=16;
+            for(I=0;I<16;I++,Addr++)
+              putchar(isprint(RdZ80(Addr))? RdZ80(Addr):'.');
+            puts("");
+          }
+        }
+        break;
+
+      case 'D':
+        {
+          word Addr;
+
+          if(strlen(S)>1) sscanf(S+1,"%hX",&Addr); else Addr=R->PC.W;
+          puts("");
+          for(J=0;J<16;J++)
+          {
+            printf("%04X: ",Addr);
+            Addr+=DAsm(S,Addr);
+            puts(S);
+          }
+        }
+        break;
+
+#ifdef FMSX
+      case 'S':
+        for(J=0;J<AY8910_CHANNELS;J++)
+        {
+          printf("Channel %d: Volume %d, Frequency %dHz",J,PSG.Volume[J],PSG.Freq[J]);
+          if(!(PSG.R[8+(J%3)]&0x10)) printf("\n");
+          else printf(", Envelope %d\n",PSG.R[8+(J%3)]&0x0F);
+        }
+        printf("Envelope period %dms\n",PSG.EPeriod);
+        break;
+#endif /* FMSX */
+    }
+  }
+
+  /* Continue emulation */
+  return(1);
+}
+
+#endif /* DEBUG */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/Tables.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Tables.h
new file mode 100755
index 0000000..dbb299a
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Tables.h
@@ -0,0 +1,447 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Tables.h                       **/
+/**                                                         **/
+/** This file contains tables of used by Z80 emulation to   **/
+/** compute SIGN,ZERO, PARITY flags, and decimal correction **/
+/** There are also timing tables for Z80 opcodes. This file **/
+/** is included from Z80.c.                                 **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+static const byte Cycles[256] =
+{
+   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+   8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+   7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+   7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+   5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+   5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+   5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 
+};
+
+static const byte CyclesCB[256] =
+{
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 
+};
+
+static const byte CyclesED[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
+  12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
+  12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
+  12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXX[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
+   0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+  19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXXCB[256] =
+{
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
+};
+
+static const byte ZSTable[256] =
+{
+  Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
+};
+
+static const byte PZSTable[256] =
+{
+  Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
+};
+
+static const word DAATable[2048] =
+{
+  0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,
+  0x0808,0x090C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,
+  0x180C,0x1908,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,
+  0x282C,0x2928,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,
+  0x3828,0x392C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,
+  0x480C,0x4908,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,
+  0x5808,0x590C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,
+  0x6828,0x692C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,
+  0x782C,0x7928,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,
+  0x888C,0x8988,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,
+  0x9888,0x998C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6025,0x6121,0x6221,0x6325,0x6421,0x6525,0x6625,0x6721,
+  0x6829,0x692D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7021,0x7125,0x7225,0x7321,0x7425,0x7521,0x7621,0x7725,
+  0x782D,0x7929,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8081,0x8185,0x8285,0x8381,0x8485,0x8581,0x8681,0x8785,
+  0x888D,0x8989,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9085,0x9181,0x9281,0x9385,0x9481,0x9585,0x9685,0x9781,
+  0x9889,0x998D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA0A5,0xA1A1,0xA2A1,0xA3A5,0xA4A1,0xA5A5,0xA6A5,0xA7A1,
+  0xA8A9,0xA9AD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB0A1,0xB1A5,0xB2A5,0xB3A1,0xB4A5,0xB5A1,0xB6A1,0xB7A5,
+  0xB8AD,0xB9A9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC085,0xC181,0xC281,0xC385,0xC481,0xC585,0xC685,0xC781,
+  0xC889,0xC98D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD081,0xD185,0xD285,0xD381,0xD485,0xD581,0xD681,0xD785,
+  0xD88D,0xD989,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE0A1,0xE1A5,0xE2A5,0xE3A1,0xE4A5,0xE5A1,0xE6A1,0xE7A5,
+  0xE8AD,0xE9A9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF0A5,0xF1A1,0xF2A1,0xF3A5,0xF4A1,0xF5A5,0xF6A5,0xF7A1,
+  0xF8A9,0xF9AD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0604,0x0700,0x0808,0x090C,0x0A0C,0x0B08,0x0C0C,0x0D08,
+  0x0E08,0x0F0C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1600,0x1704,0x180C,0x1908,0x1A08,0x1B0C,0x1C08,0x1D0C,
+  0x1E0C,0x1F08,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2620,0x2724,0x282C,0x2928,0x2A28,0x2B2C,0x2C28,0x2D2C,
+  0x2E2C,0x2F28,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3624,0x3720,0x3828,0x392C,0x3A2C,0x3B28,0x3C2C,0x3D28,
+  0x3E28,0x3F2C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4600,0x4704,0x480C,0x4908,0x4A08,0x4B0C,0x4C08,0x4D0C,
+  0x4E0C,0x4F08,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5604,0x5700,0x5808,0x590C,0x5A0C,0x5B08,0x5C0C,0x5D08,
+  0x5E08,0x5F0C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6624,0x6720,0x6828,0x692C,0x6A2C,0x6B28,0x6C2C,0x6D28,
+  0x6E28,0x6F2C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7620,0x7724,0x782C,0x7928,0x7A28,0x7B2C,0x7C28,0x7D2C,
+  0x7E2C,0x7F28,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8680,0x8784,0x888C,0x8988,0x8A88,0x8B8C,0x8C88,0x8D8C,
+  0x8E8C,0x8F88,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9684,0x9780,0x9888,0x998C,0x9A8C,0x9B88,0x9C8C,0x9D88,
+  0x9E88,0x9F8C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6625,0x6721,0x6829,0x692D,0x6A2D,0x6B29,0x6C2D,0x6D29,
+  0x6E29,0x6F2D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7621,0x7725,0x782D,0x7929,0x7A29,0x7B2D,0x7C29,0x7D2D,
+  0x7E2D,0x7F29,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8681,0x8785,0x888D,0x8989,0x8A89,0x8B8D,0x8C89,0x8D8D,
+  0x8E8D,0x8F89,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9685,0x9781,0x9889,0x998D,0x9A8D,0x9B89,0x9C8D,0x9D89,
+  0x9E89,0x9F8D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA6A5,0xA7A1,0xA8A9,0xA9AD,0xAAAD,0xABA9,0xACAD,0xADA9,
+  0xAEA9,0xAFAD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB6A1,0xB7A5,0xB8AD,0xB9A9,0xBAA9,0xBBAD,0xBCA9,0xBDAD,
+  0xBEAD,0xBFA9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC685,0xC781,0xC889,0xC98D,0xCA8D,0xCB89,0xCC8D,0xCD89,
+  0xCE89,0xCF8D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD681,0xD785,0xD88D,0xD989,0xDA89,0xDB8D,0xDC89,0xDD8D,
+  0xDE8D,0xDF89,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE6A1,0xE7A5,0xE8AD,0xE9A9,0xEAA9,0xEBAD,0xECA9,0xEDAD,
+  0xEEAD,0xEFA9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF6A5,0xF7A1,0xF8A9,0xF9AD,0xFAAD,0xFBA9,0xFCAD,0xFDA9,
+  0xFEA9,0xFFAD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0046,0x0102,0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,
+  0x080A,0x090E,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x1002,0x1106,0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,
+  0x180E,0x190A,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x2022,0x2126,0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,
+  0x282E,0x292A,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x3026,0x3122,0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,
+  0x382A,0x392E,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x4002,0x4106,0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,
+  0x480E,0x490A,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x5006,0x5102,0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,
+  0x580A,0x590E,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x6026,0x6122,0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,
+  0x682A,0x692E,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x7022,0x7126,0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,
+  0x782E,0x792A,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x8082,0x8186,0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,
+  0x888E,0x898A,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x9086,0x9182,0x9282,0x9386,0x9482,0x9586,0x9686,0x9782,
+  0x988A,0x998E,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xA0A7,0xA1A3,0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,
+  0xA8AB,0xA9AF,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xB0A3,0xB1A7,0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,
+  0xB8AF,0xB9AB,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xC087,0xC183,0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,
+  0xC88B,0xC98F,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xD083,0xD187,0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,
+  0xD88F,0xD98B,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xE0A3,0xE1A7,0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,
+  0xE8AF,0xE9AB,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xF0A7,0xF1A3,0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,
+  0xF8AB,0xF9AF,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0x0047,0x0103,0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,
+  0x080B,0x090F,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x1003,0x1107,0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,
+  0x180F,0x190B,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x2023,0x2127,0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,
+  0x282F,0x292B,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x3027,0x3123,0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,
+  0x382B,0x392F,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xFABE,0xFBBA,0xFCBE,0xFDBA,0xFEBA,0xFFBE,0x0046,0x0102,
+  0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x0A1E,0x0B1A,0x0C1E,0x0D1A,0x0E1A,0x0F1E,0x1002,0x1106,
+  0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x1A1A,0x1B1E,0x1C1A,0x1D1E,0x1E1E,0x1F1A,0x2022,0x2126,
+  0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x2A3A,0x2B3E,0x2C3A,0x2D3E,0x2E3E,0x2F3A,0x3026,0x3122,
+  0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x3A3E,0x3B3A,0x3C3E,0x3D3A,0x3E3A,0x3F3E,0x4002,0x4106,
+  0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x4A1A,0x4B1E,0x4C1A,0x4D1E,0x4E1E,0x4F1A,0x5006,0x5102,
+  0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x5A1E,0x5B1A,0x5C1E,0x5D1A,0x5E1A,0x5F1E,0x6026,0x6122,
+  0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x6A3E,0x6B3A,0x6C3E,0x6D3A,0x6E3A,0x6F3E,0x7022,0x7126,
+  0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x7A3A,0x7B3E,0x7C3A,0x7D3E,0x7E3E,0x7F3A,0x8082,0x8186,
+  0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x8A9A,0x8B9E,0x8C9A,0x8D9E,0x8E9E,0x8F9A,0x9086,0x9182,
+  0x9282,0x9386,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0x9A9F,0x9B9B,0x9C9F,0x9D9B,0x9E9B,0x9F9F,0xA0A7,0xA1A3,
+  0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xAABF,0xABBB,0xACBF,0xADBB,0xAEBB,0xAFBF,0xB0A3,0xB1A7,
+  0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xBABB,0xBBBF,0xBCBB,0xBDBF,0xBEBF,0xBFBB,0xC087,0xC183,
+  0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xCA9F,0xCB9B,0xCC9F,0xCD9B,0xCE9B,0xCF9F,0xD083,0xD187,
+  0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xDA9B,0xDB9F,0xDC9B,0xDD9F,0xDE9F,0xDF9B,0xE0A3,0xE1A7,
+  0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xEABB,0xEBBF,0xECBB,0xEDBF,0xEEBF,0xEFBB,0xF0A7,0xF1A3,
+  0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0xFABF,0xFBBB,0xFCBF,0xFDBB,0xFEBB,0xFFBF,0x0047,0x0103,
+  0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x0A1F,0x0B1B,0x0C1F,0x0D1B,0x0E1B,0x0F1F,0x1003,0x1107,
+  0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x1A1B,0x1B1F,0x1C1B,0x1D1F,0x1E1F,0x1F1B,0x2023,0x2127,
+  0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x2A3B,0x2B3F,0x2C3B,0x2D3F,0x2E3F,0x2F3B,0x3027,0x3123,
+  0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F
+};
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.c b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.c
new file mode 100755
index 0000000..6ec53f1
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.c
@@ -0,0 +1,703 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.c                         **/
+/**                                                         **/
+/** This file contains implementation for Z80 CPU. Don't    **/
+/** forget to provide RdZ80(), WrZ80(), InZ80(), OutZ80(),  **/
+/** LoopZ80(), and PatchZ80() functions to accomodate the   **/
+/** emulated machine's architecture.                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#pragma GCC optimize("Ofast")
+
+#define GENESIS 1
+
+#include "Z80.h"
+#include "Tables.h"
+#include <stdio.h>
+
+/** INLINE ***************************************************/
+/** C99 standard has "inline", but older compilers used     **/
+/** __inline for the same purpose.                          **/
+/*************************************************************/
+#ifdef __C99__
+#define INLINE static inline
+#else
+#define INLINE static __inline
+#endif
+
+/** System-Dependent Stuff ***********************************/
+/** This is system-dependent code put here to speed things  **/
+/** up. It has to stay inlined to be fast.                  **/
+/*************************************************************/
+#ifdef COLEM
+#define RdZ80 RDZ80
+extern byte *ROMPage[];
+INLINE byte RdZ80(word A) { return(ROMPage[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef SPECCY
+#define RdZ80 RDZ80
+#define WrZ80 WRZ80
+extern byte *Page[],*ROM;
+INLINE byte RdZ80(word A)        { return(Page[A>>13][A&0x1FFF]); }
+INLINE void WrZ80(word A,byte V) { if(Page[A>>13]<ROM) Page[A>>13][A&0x1FFF]=V; }
+#endif
+
+#ifdef MG
+#define RdZ80 RDZ80
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef FMSX
+#define FAST_RDOP
+extern byte *RAM[];
+INLINE byte OpZ80(word A) { return(RAM[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef GENESIS
+#define FAST_RDOP
+extern byte *Z80_RAM[];
+INLINE byte OpZ80(word A) { return(Z80_RAM[A>>13][A&0x1FFF]); }
+#endif
+
+/** FAST_RDOP ************************************************/
+/** With this #define not present, RdZ80() should perform   **/
+/** the functions of OpZ80().                               **/
+/*************************************************************/
+#ifndef FAST_RDOP
+#define OpZ80(A) RdZ80(A)
+#endif
+
+#define S(Fl)        R->AF.B.l|=Fl
+#define R(Fl)        R->AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
+
+#define M_RLC(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+#define M_RRC(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+#define M_RL(Rg)       \
+  if(Rg&0x80)          \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+#define M_RR(Rg)       \
+  if(Rg&0x01)          \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+  
+#define M_SLA(Rg)      \
+  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+#define M_SRA(Rg)      \
+  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+
+#define M_SLL(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+#define M_SRL(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+
+#define M_BIT(Bit,Rg)  \
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
+
+#define M_SET(Bit,Rg) Rg|=1<<Bit
+#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
+
+#define M_POP(Rg)      \
+  R->Rg.B.l=OpZ80(R->SP.W++);R->Rg.B.h=OpZ80(R->SP.W++)
+#define M_PUSH(Rg)     \
+  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+
+#define M_CALL         \
+  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W++);         \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
+  R->PC.W=J.W; \
+  JumpZ80(J.W)
+
+#define M_JP  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W);R->PC.W=J.W;JumpZ80(J.W)
+#define M_JR  R->PC.W+=(offset)OpZ80(R->PC.W)+1;JumpZ80(R->PC.W)
+#define M_RET R->PC.B.l=OpZ80(R->SP.W++);R->PC.B.h=OpZ80(R->SP.W++);JumpZ80(R->PC.W)
+
+#define M_RST(Ad)      \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad;JumpZ80(Ad)
+
+#define M_LDWORD(Rg)   \
+  R->Rg.B.l=OpZ80(R->PC.W++);R->Rg.B.h=OpZ80(R->PC.W++)
+
+#define M_ADD(Rg)      \
+  J.W=R->AF.B.h+Rg;    \
+  R->AF.B.l=           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|                        \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  R->AF.B.h=J.B.l       
+
+#define M_SUB(Rg)      \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  R->AF.B.h=J.B.l
+
+#define M_ADC(Rg)      \
+  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|              \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_SBC(Rg)      \
+  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_CP(Rg)       \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+
+#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
+#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+
+#define M_IN(Rg)        \
+  Rg=InZ80(R->BC.W);  \
+  R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+
+#define M_INC(Rg)       \
+  Rg++;                 \
+  R->AF.B.l=            \
+    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+    (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
+
+#define M_DEC(Rg)       \
+  Rg--;                 \
+  R->AF.B.l=            \
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+    (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
+
+#define M_ADDW(Rg1,Rg2) \
+  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
+  R->AF.B.l=                                             \
+    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
+  R->Rg1.W=J.W
+
+#define M_ADCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+   
+#define M_SBCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    N_FLAG|                                                    \
+    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+
+enum Codes
+{
+  NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
+  EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
+  DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
+  JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
+  JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
+  JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
+  JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
+  JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
+  LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
+  LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
+  LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
+  LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
+  LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
+  LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
+  LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
+  LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
+  ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
+  ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
+  SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
+  SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
+  AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
+  XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
+  OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
+  CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
+  RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
+  RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
+  RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
+  RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
+  RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
+  RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
+  RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
+  RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
+};
+
+enum CodesCB
+{
+  RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
+  RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
+  RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
+  RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
+  SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
+  SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
+  SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
+  SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
+  BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
+  BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
+  BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
+  BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
+  BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
+  BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
+  BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
+  BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
+  RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
+  RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
+  RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
+  RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
+  RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
+  RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
+  RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
+  RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
+  SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
+  SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
+  SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
+  SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
+  SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
+  SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
+  SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
+  SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
+};
+  
+enum CodesED
+{
+  DB_00,DB_01,DB_02,DB_03,DB_04,DB_05,DB_06,DB_07,
+  DB_08,DB_09,DB_0A,DB_0B,DB_0C,DB_0D,DB_0E,DB_0F,
+  DB_10,DB_11,DB_12,DB_13,DB_14,DB_15,DB_16,DB_17,
+  DB_18,DB_19,DB_1A,DB_1B,DB_1C,DB_1D,DB_1E,DB_1F,
+  DB_20,DB_21,DB_22,DB_23,DB_24,DB_25,DB_26,DB_27,
+  DB_28,DB_29,DB_2A,DB_2B,DB_2C,DB_2D,DB_2E,DB_2F,
+  DB_30,DB_31,DB_32,DB_33,DB_34,DB_35,DB_36,DB_37,
+  DB_38,DB_39,DB_3A,DB_3B,DB_3C,DB_3D,DB_3E,DB_3F,
+  IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
+  IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,DB_4C,RETI,DB_,LD_R_A,
+  IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,DB_54,DB_55,IM_1,LD_A_I,
+  IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,DB_5C,DB_5D,IM_2,LD_A_R,
+  IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,DB_64,DB_65,DB_66,RRD,
+  IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,DB_6C,DB_6D,DB_6E,RLD,
+  IN_F_xC,DB_71,SBC_HL_SP,LD_xWORDe_SP,DB_74,DB_75,DB_76,DB_77,
+  IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,DB_7C,DB_7D,DB_7E,DB_7F,
+  DB_80,DB_81,DB_82,DB_83,DB_84,DB_85,DB_86,DB_87,
+  DB_88,DB_89,DB_8A,DB_8B,DB_8C,DB_8D,DB_8E,DB_8F,
+  DB_90,DB_91,DB_92,DB_93,DB_94,DB_95,DB_96,DB_97,
+  DB_98,DB_99,DB_9A,DB_9B,DB_9C,DB_9D,DB_9E,DB_9F,
+  LDI,CPI,INI,OUTI,DB_A4,DB_A5,DB_A6,DB_A7,
+  LDD,CPD,IND,OUTD,DB_AC,DB_AD,DB_AE,DB_AF,
+  LDIR,CPIR,INIR,OTIR,DB_B4,DB_B5,DB_B6,DB_B7,
+  LDDR,CPDR,INDR,OTDR,DB_BC,DB_BD,DB_BE,DB_BF,
+  DB_C0,DB_C1,DB_C2,DB_C3,DB_C4,DB_C5,DB_C6,DB_C7,
+  DB_C8,DB_C9,DB_CA,DB_CB,DB_CC,DB_CD,DB_CE,DB_CF,
+  DB_D0,DB_D1,DB_D2,DB_D3,DB_D4,DB_D5,DB_D6,DB_D7,
+  DB_D8,DB_D9,DB_DA,DB_DB,DB_DC,DB_DD,DB_DE,DB_DF,
+  DB_E0,DB_E1,DB_E2,DB_E3,DB_E4,DB_E5,DB_E6,DB_E7,
+  DB_E8,DB_E9,DB_EA,DB_EB,DB_EC,DB_ED,DB_EE,DB_EF,
+  DB_F0,DB_F1,DB_F2,DB_F3,DB_F4,DB_F5,DB_F6,DB_F7,
+  DB_F8,DB_F9,DB_FA,DB_FB,DB_FC,DB_FD,DB_FE,DB_FF
+};
+
+static void CodesCB(register Z80 *R)
+{
+  register byte I;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesCB[I];
+  switch(I)
+  {
+#include "CodesCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (   
+          "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IX    
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesFDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IY
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesED(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesED[I];
+  switch(I)
+  {
+#include "CodesED.h"
+    case PFX_ED:
+      R->PC.W--;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IX
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesDDCB(R);break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+static void CodesFD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IY
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesFDCB(R);break;
+    default:
+        printf
+        (
+          "Unrecognized instruction: FD %02X at PC=%04X\n",
+          OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the register struct  **/
+/** before starting execution with Z80(). It sets the       **/
+/** registers to their supposed initial values.             **/
+/*************************************************************/
+void ResetZ80(Z80 *R)
+{
+  R->PC.W     = 0x0000;
+  R->SP.W     = 0xF000;
+  R->AF.W     = 0x0000;
+  R->BC.W     = 0x0000;
+  R->DE.W     = 0x0000;
+  R->HL.W     = 0x0000;
+  R->AF1.W    = 0x0000;
+  R->BC1.W    = 0x0000;
+  R->DE1.W    = 0x0000;
+  R->HL1.W    = 0x0000;
+  R->IX.W     = 0x0000;
+  R->IY.W     = 0x0000;
+  R->I        = 0x00;
+  R->R        = 0x00;
+  R->IFF      = 0x00;
+  R->ICount   = R->IPeriod;
+  R->RunCycles =0;
+  R->IRequest = INT_NONE;
+  R->IBackup  = 0;
+
+  JumpZ80(R->PC.W);
+}
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int GetRunCyclesZ80(register Z80 *R)
+{
+  return(R->ICount - R->RunCycles);
+}
+int ExecZ80(register Z80 *R,register int RunCycles)
+{
+  register byte I;
+  register pair J;
+  R->RunCycles = R->ICount;
+
+  for(R->ICount=RunCycles;;)
+  {
+    while(R->ICount>0)
+    {
+#ifdef DEBUG
+      /* Turn tracing on when reached trap address */
+      if(R->PC.W==R->Trap) R->Trace=1;
+      /* Call single-step debugger, exit if requested */
+      if(R->Trace)
+        if(!DebugZ80(R)) return(R->ICount);
+#endif
+
+      /* Read opcode and count cycles */
+      I=OpZ80(R->PC.W++);
+      /* Count cycles */
+      R->ICount-=Cycles[I];
+
+      /* Interpret opcode */
+      switch(I)
+      {
+#include "Codes.h"
+        case PFX_CB: CodesCB(R);break;
+        case PFX_ED: CodesED(R);break;
+        case PFX_FD: CodesFD(R);break;
+        case PFX_DD: CodesDD(R);break;
+      }
+
+      /* Unless we have come here after EI, exit */
+      if(!(R->IFF&IFF_EI))
+      {
+        /* Interrupt CPU if needed */
+        if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
+      }
+      else
+      {
+        /* Done with AfterEI state */
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1;
+        /* Restore the ICount */
+        R->ICount+=R->IBackup-1;
+      }
+    }
+
+    return(R->ICount);
+  }
+}
+#endif /* EXECZ80 */
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(Z80 *R,word Vector)
+{
+  /* If HALTed, take CPU off HALT instruction */
+  if(R->IFF&IFF_HALT) { R->PC.W++;R->IFF&=~IFF_HALT; }
+
+  if((R->IFF&IFF_1)||(Vector==INT_NMI))
+  {
+    /* Save PC on stack */
+    M_PUSH(PC);
+
+    /* Automatically reset IRequest if needed */
+    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+
+    /* If it is NMI... */
+    if(Vector==INT_NMI)
+    {
+      /* Clear IFF1 */
+      R->IFF&=~(IFF_1|IFF_EI);
+      /* Jump to hardwired NMI vector */
+      R->PC.W=0x0066;
+      JumpZ80(0x0066);
+      /* Done */
+      return;
+    }
+
+    /* Further interrupts off */
+    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+
+    /* If in IM2 mode... */
+    if(R->IFF&IFF_IM2)
+    {
+      /* Make up the vector address */
+      Vector=(Vector&0xFF)|((word)(R->I)<<8);
+      /* Read the vector */
+      R->PC.B.l=RdZ80(Vector++);
+      R->PC.B.h=RdZ80(Vector);
+      JumpZ80(R->PC.W);
+      /* Done */
+      return;
+    }
+
+    /* If in IM1 mode, just jump to hardwired IRQ vector */
+    if(R->IFF&IFF_IM1) { R->PC.W=0x0038;JumpZ80(0x0038);return; }
+
+    /* If in IM0 mode... */
+
+    /* Jump to a vector */
+    switch(Vector)
+    {
+      case INT_RST00: R->PC.W=0x0000;JumpZ80(0x0000);break;
+      case INT_RST08: R->PC.W=0x0008;JumpZ80(0x0008);break;
+      case INT_RST10: R->PC.W=0x0010;JumpZ80(0x0010);break;
+      case INT_RST18: R->PC.W=0x0018;JumpZ80(0x0018);break;
+      case INT_RST20: R->PC.W=0x0020;JumpZ80(0x0020);break;
+      case INT_RST28: R->PC.W=0x0028;JumpZ80(0x0028);break;
+      case INT_RST30: R->PC.W=0x0030;JumpZ80(0x0030);break;
+      case INT_RST38: R->PC.W=0x0038;JumpZ80(0x0038);break;
+    }
+  }
+}
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  for(;;)
+  {
+#ifdef DEBUG
+    /* Turn tracing on when reached trap address */
+    if(R->PC.W==R->Trap) R->Trace=1;
+    /* Call single-step debugger, exit if requested */
+    if(R->Trace)
+      if(!DebugZ80(R)) return(R->PC.W);
+#endif
+
+    I=OpZ80(R->PC.W++);
+    R->ICount-=Cycles[I];
+
+    switch(I)
+    {
+#include "Codes.h"
+      case PFX_CB: CodesCB(R);break;
+      case PFX_ED: CodesED(R);break;
+      case PFX_FD: CodesFD(R);break;
+      case PFX_DD: CodesDD(R);break;
+    }
+ 
+    /* If cycle counter expired... */
+    if(R->ICount<=0)
+    {
+      /* If we have come after EI, get address from IRequest */
+      /* Otherwise, get it from the loop handler             */
+      if(R->IFF&IFF_EI)
+      {
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
+        R->ICount+=R->IBackup-1;       /* Restore the ICount      */
+
+        /* Call periodic handler or set pending IRQ */
+        if(R->ICount>0) J.W=R->IRequest;
+        else
+        {
+          J.W=LoopZ80(R);        /* Call periodic handler    */
+          R->ICount+=R->IPeriod; /* Reset the cycle counter  */
+          if(J.W==INT_NONE) J.W=R->IRequest;  /* Pending IRQ */
+        }
+      }
+      else
+      {
+        J.W=LoopZ80(R);          /* Call periodic handler    */
+        R->ICount+=R->IPeriod;   /* Reset the cycle counter  */
+        if(J.W==INT_NONE) J.W=R->IRequest;    /* Pending IRQ */
+      }
+
+      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
+    }
+  }
+
+  /* Execution stopped */
+  return(R->PC.W);
+}
+#endif /* !EXECZ80 */
diff --git a/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.h b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.h
new file mode 100755
index 0000000..96e1064
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/cpus/Z80/Z80.h
@@ -0,0 +1,192 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to emulation   **/
+/** of Z80 CPU.                                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef Z80_H
+#define Z80_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+                               /* Compilation options:       */
+/* #define DEBUG */            /* Compile debugging version  */
+#define LSB_FIRST              /* Compile for low-endian CPU */
+/* #define MSB_FIRST */        /* Compile for hi-endian CPU  */
+#define EXECZ80
+
+                               /* LoopZ80() may return:      */
+#define INT_RST00   0x00C7     /* RST 00h                    */
+#define INT_RST08   0x00CF     /* RST 08h                    */
+#define INT_RST10   0x00D7     /* RST 10h                    */
+#define INT_RST18   0x00DF     /* RST 18h                    */
+#define INT_RST20   0x00E7     /* RST 20h                    */
+#define INT_RST28   0x00EF     /* RST 28h                    */
+#define INT_RST30   0x00F7     /* RST 30h                    */
+#define INT_RST38   0x00FF     /* RST 38h                    */
+#define INT_IRQ     INT_RST38  /* Default IRQ opcode is FFh  */
+#define INT_NMI     0xFFFD     /* Non-maskable interrupt     */
+#define INT_NONE    0xFFFF     /* No interrupt required      */
+#define INT_QUIT    0xFFFE     /* Exit the emulation         */
+
+                               /* Bits in Z80 F register:    */
+#define S_FLAG      0x80       /* 1: Result negative         */
+#define Z_FLAG      0x40       /* 1: Result is zero          */
+#define H_FLAG      0x10       /* 1: Halfcarry/Halfborrow    */
+#define P_FLAG      0x04       /* 1: Result is even          */
+#define V_FLAG      0x04       /* 1: Overflow occured        */
+#define N_FLAG      0x02       /* 1: Subtraction occured     */
+#define C_FLAG      0x01       /* 1: Carry/Borrow occured    */
+
+                               /* Bits in IFF flip-flops:    */
+#define IFF_1       0x01       /* IFF1 flip-flop             */
+#define IFF_IM1     0x02       /* 1: IM1 mode                */
+#define IFF_IM2     0x04       /* 1: IM2 mode                */
+#define IFF_2       0x08       /* IFF2 flip-flop             */
+#define IFF_EI      0x20       /* 1: EI pending              */
+#define IFF_HALT    0x80       /* 1: CPU HALTed              */
+
+/** Simple Datatypes *****************************************/
+/** NOTICE: sizeof(byte)=1 and sizeof(word)=2               **/
+/*************************************************************/
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+#ifndef WORD_TYPE_DEFINED
+#define WORD_TYPE_DEFINED
+typedef unsigned short word;
+#endif
+typedef signed char offset;
+
+/** Structured Datatypes *************************************/
+/** NOTICE: #define LSB_FIRST for machines where least      **/
+/**         signifcant byte goes first.                     **/
+/*************************************************************/
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+
+typedef struct
+{
+  pair AF,BC,DE,HL,IX,IY,PC,SP;       /* Main registers      */
+  pair AF1,BC1,DE1,HL1;               /* Shadow registers    */
+  byte IFF,I;                         /* Interrupt registers */
+  byte R;                             /* Refresh register    */
+
+  int IPeriod,ICount; /* Set IPeriod to number of CPU cycles */
+  int RunCycles;      /* Number of cycle to run              */
+                      /* between calls to LoopZ80()          */
+  int IBackup;        /* Private, don't touch                */
+  word IRequest;      /* Set to address of pending IRQ       */
+  byte IAutoReset;    /* Set to 1 to autom. reset IRequest   */
+  byte TrapBadOps;    /* Set to 1 to warn of illegal opcodes */
+  word Trap;          /* Set Trap to address to trace from   */
+  byte Trace;         /* Set Trace=1 to start tracing        */
+  void *User;         /* Arbitrary user data (ID,RAM*,etc.)  */
+} Z80;
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the registers before **/
+/** starting execution with RunZ80(). It sets registers to  **/
+/** their initial values.                                   **/
+/*************************************************************/
+void ResetZ80(register Z80 *R);
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int ExecZ80(register Z80 *R,register int RunCycles);
+int GetRunCyclesZ80(register Z80 *R);
+#endif
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(register Z80 *R,register word Vector);
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(register Z80 *R);
+#endif
+
+/** RdZ80()/WrZ80() ******************************************/
+/** These functions are called when access to RAM occurs.   **/
+/** They allow to control memory access.                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void WrZ80(register word Addr,register byte Value);
+void WrZ80byM68k(register word Addr,register byte Value);
+byte RdZ80(register word Addr);
+
+/** InZ80()/OutZ80() *****************************************/
+/** Z80 emulation calls these functions to read/write from  **/
+/** I/O ports. There can be 65536 I/O ports, but only first **/
+/** 256 are usually used.                                   **/
+/************************************ TO BE WRITTEN BY USER **/
+void OutZ80(register word Port,register byte Value);
+byte InZ80(register word Port);
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/** For example, it can be called to emulate BIOS calls,    **/
+/** such as disk and tape access. Replace it with an empty  **/
+/** macro for no patching.                                  **/
+/************************************ TO BE WRITTEN BY USER **/
+void PatchZ80(register Z80 *R);
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers. Emulation exits   **/
+/** if DebugZ80() returns 0.                                **/
+/*************************************************************/
+#ifdef DEBUG
+byte DebugZ80(register Z80 *R);
+#endif
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts. This    **/
+/** function must return an address of the interrupt vector **/
+/** (0x0038, 0x0066, etc.) or INT_NONE for no interrupt.    **/
+/** Return INT_QUIT to exit the emulation loop.             **/
+/************************************ TO BE WRITTEN BY USER **/
+word LoopZ80(register Z80 *R);
+
+/** JumpZ80() ************************************************/
+/** Z80 emulation calls this function when it executes a    **/
+/** JP, JR, CALL, RST, or RET. You can use JumpZ80() to     **/
+/** trap these opcodes and switch memory layout.            **/
+/************************************ TO BE WRITTEN BY USER **/
+#ifndef JUMPZ80
+#define JumpZ80(PC)
+#else
+void JumpZ80(word PC);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* Z80_H */
diff --git a/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.c b/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.c
new file mode 100755
index 0000000..9fb1e5f
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.c
@@ -0,0 +1,242 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include "gwenesis_io.h"
+#include "../savestate/gwenesis_savestate.h"
+
+unsigned short button_state[3]= {0xff,0xff,0xff};
+
+/* Button mapping 
+    7 6 5 4 3 2 1 0
+Start A B C R L D U 
+*/
+static unsigned char gwenesis_io_pad_state[3] = {0x33,0x33,0x33};
+
+//#define GWENESIS_IO_VERSION 0x81 /* oversea NTSC model version 81 */
+#define GWENESIS_IO_VERSION 0xC1 /* oversea PAL model version C1 */
+/*
+$A10003	:	MODE 	VMOD 	DISK 	RSV 	VER3 	VER2 	VER1 	VER0
+MODE (R) 	0: Domestic Model
+  	        1: Overseas Model
+VMOD (R) 	0: NTSC CPU clock 7.67 MHz
+  	        1: PAL CPU clock 7.60 MHz
+RSV (R) 	Currently not used
+VER3-0 (R)	MEGA DRIVE version is indicated by $0-$F. The present hardware version is indicated by $0. 
+$A10003	: DATA 1 ( CTRL1 )
+$A10005	: DATA 2 ( CTRL2 )
+$A10007	: DATA 3 ( EXP )
+$A10009	: CTRL 1
+$A1000B	: CTRL 2
+$A1000D	: CTRL 3
+$A1000F	: TxDATA 1
+$A10011	: RxDATA 1
+$A10013	: S-CTRL 1
+$A10015	: TxDATA 2
+$A10017	: RxDATA 2
+$A10019	: S-CTRL 2
+$A1001B	: TxDATA 3
+$A1001D	: RxDATA 3
+$A1001F	: S-CTRL 3 
+
+DATA shows the status of each port. The I/O direction of each bit is set by CTRL and S-CTRL.
+DATA =	PD7 	PD6 	PD5 	PD4 	PD3 	PD2 	PD1 	PD0
+
+PD7 (RW)
+PD6 (RW) TH
+PD5 (RW) TR
+PD4 (RW) TL
+PD3 (RW) RIGHT
+PD2 (RW) LEFT
+PD1 (RW) DOWN
+PD0 (RW) UP 
+
+TH = 0
+PD7 0
+PD6 TH=0
+PD5 Start
+PD4 A
+PD3 0
+PD2 0
+PD1 DOWN
+PD0 UP    
+
+TH = 1
+PD7 0
+PD6 TH=1
+PD5 B
+PD4 C
+PD3 RIGHT
+PD2 LEFT
+PD1 DOWN
+PD0 UP   
+
+
+CTRL designates the I/O direction of each port and the INTERRUPT CONTROL of TH.
+CTRL = 	INT 	PC6 	PC5 	PC4 	PC3 	PC2 	PC1 	PC0
+
+INT (RW)	0: TH-INT PROHIBITED
+	1: TH-INT ALLOWED
+PC6 (RW)	0: PD6 INPUT MODE
+	1: OUTPUT MODE
+PC5 (RW)	0: PD5 INPUT MODE
+	1: OUTPUT MODE
+PC4 (RW)	0: PD4 INPUT MODE
+	1: OUTPUT MODE
+PC3 (RW)	0: PD3 INPUT MODE
+	1: OUTPUT MODE
+PC2 (RW)	0: PD2 INPUT MODE
+	1: OUTPUT MODE
+PC1 (RW)	0: PD1 INPUT MODE
+	1: OUTPUT MODE
+PC0 (RW)	0: PD0 INPUT MODE
+	1: OUTPUT MODE  
+
+S-CTRL is for the status, etc. of each port's mode change, baud rate and SERIAL.
+
+S-CTRL = BPS1 	BPS0 	SIN 	SOUT 	RINT 	RERR 	RRDY 	TFUL
+
+SIN (RW) 	0: TR-PARALLEL MODE
+	1: SERIAL IN
+SOUT (RW)	0: TL-PARALLEL MODE
+	1: SERIAL OUT
+RINT (RW)	0: Rxd READY INTERRUPT PROHIBITED
+	1: Rxd READY INTERRUPT ALLOWED
+RERR (R) 	0:
+	1: Rxd ERROR
+RRDY (R) 	0:
+	1: Rxd READY
+TFUL (R) 	0:
+	1: Txd FULL 
+*/
+
+unsigned char io_reg[16] = {GWENESIS_IO_VERSION, /* 0x1 Version */
+                             0x7f, 0x7f, 0x7f,   /* 0x3-5-7 JOYPAD DATA 1 2 & EXT */
+                             0x00, 0x00, 0x00,   /* 0x9-A-C JOYPAD CTRL 1 2 & EXT */
+                             0xff,    0,    0,   /* PORT 1 */
+                             0xff,    0,    0,   /* PORT 2 */
+                             0xff,    0,    0};  /* PORT 3 */
+
+void gwenesis_io_pad_release_button(int pad, int button)
+{
+    button_state[pad] |= (1 << button);
+}
+
+void gwenesis_io_pad_press_button(int pad, int button)
+{
+    button_state[pad] &= ~(1 << button);
+}
+
+static inline void gwenesis_io_pad_write(int pad, int value)
+{
+    unsigned char mask = io_reg[pad + 4];
+
+     gwenesis_io_pad_state[pad] &= ~mask;
+    gwenesis_io_pad_state[pad] |= value & mask;
+ 
+}
+
+static inline  unsigned char gwenesis_io_pad_read(int pad)
+{
+    unsigned char value;
+ 
+    /* get host button */
+    gwenesis_io_get_buttons();
+
+    value = gwenesis_io_pad_state[pad] & 0x40;
+    value |= 0x3f;
+
+    if (value & 0x40)
+    {
+        value &= (button_state[pad] & 0x3f);
+    }
+    else
+    {
+        value &= ((button_state[pad] & 3) | ((button_state[pad] >> 2) & 0x30));
+    }
+    return value;
+}
+
+void gwenesis_io_write_ctrl(unsigned int address, unsigned int value)
+{
+
+    address >>= 1;
+ 
+    // JOYPAD DATA
+    if (address >= 0x1 && address <= 0x3)
+    {
+
+        io_reg[address] = value;
+        gwenesis_io_pad_write(address - 1, value);
+        return;
+    }
+    // JOYPAD CTRL
+    else if (address >= 0x4 && address <= 0x6)
+    {
+        if (io_reg[address] != value)
+        {
+            io_reg[address] = value;
+            gwenesis_io_pad_write(address - 4, io_reg[address - 3]);
+        }
+        return;
+    }
+
+    return;
+}
+
+unsigned int gwenesis_io_read_ctrl(unsigned int address)
+{
+    address >>= 1;
+    if (address >= 0x1 && address < 0x4)
+    {
+        unsigned char mask = 0x80 | io_reg[address + 3];
+        unsigned char value;
+        value = io_reg[address] & mask;
+        value |= gwenesis_io_pad_read(address - 1) & ~mask;
+
+        return value;
+    }
+    else
+    {
+        return io_reg[address];
+    }
+}
+
+void gwenesis_io_set_reg(unsigned int reg, unsigned int value) {
+    io_reg[reg] = value;
+    return;
+}
+
+void gwenesis_io_save_state() {
+    SaveState* state;
+    state = saveGwenesisStateOpenForWrite("io");
+    saveGwenesisStateSetBuffer(state, "button_state", button_state, sizeof(button_state));
+    saveGwenesisStateSetBuffer(state, "gwenesis_io_pad_state", gwenesis_io_pad_state, sizeof(gwenesis_io_pad_state));
+    saveGwenesisStateSetBuffer(state, "io_reg", io_reg, sizeof(io_reg));
+}
+
+void gwenesis_io_load_state() {
+    SaveState* state = saveGwenesisStateOpenForRead("io");
+    saveGwenesisStateGetBuffer(state, "button_state", button_state, sizeof(button_state));
+    saveGwenesisStateGetBuffer(state, "gwenesis_io_pad_state", gwenesis_io_pad_state, sizeof(gwenesis_io_pad_state));
+    saveGwenesisStateGetBuffer(state, "io_reg", io_reg, sizeof(io_reg));
+}
diff --git a/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.h b/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.h
new file mode 100755
index 0000000..a1a1b75
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/io/gwenesis_io.h
@@ -0,0 +1,36 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_io_H_
+#define _gwenesis_io_H_
+
+#pragma once
+
+void gwenesis_io_pad_press_button(int pad, int button);
+void gwenesis_io_pad_release_button(int pad, int button);
+
+void gwenesis_io_write_ctrl(unsigned int address, unsigned int value);
+unsigned int gwenesis_io_read_ctrl(unsigned int address);
+
+void gwenesis_io_set_reg(unsigned int reg, unsigned int value);
+void gwenesis_io_get_buttons();
+
+void gwenesis_io_save_state();
+void gwenesis_io_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.c b/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.c
new file mode 100755
index 0000000..014555b
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.c
@@ -0,0 +1,54 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "../cpus/M68K/m68k.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../vdp/gwenesis_vdp.h"
+#include "../sound/z80inst.h"
+
+#include "../savestate/gwenesis_savestate.h"
+
+#include <assert.h>
+
+void gwenesis_save_state() {
+  /* DO NOT CHANGE ORDER - NEEDS TO BE SAME AS IN LOAD */
+  gwenesis_m68k_save_state();
+  gwenesis_io_save_state();
+  gwenesis_bus_save_state();
+  gwenesis_vdp_gfx_save_state();
+  gwenesis_vdp_mem_save_state();
+
+}
+
+void gwenesis_load_state() {
+  /* DO NOT CHANGE ORDER - NEEDS TO BE SAME AS IN SAVE */
+  gwenesis_m68k_load_state();
+  gwenesis_io_load_state();
+  gwenesis_bus_load_state();
+  gwenesis_vdp_gfx_load_state();
+  gwenesis_vdp_mem_load_state();
+
+}
diff --git a/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.h b/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.h
new file mode 100755
index 0000000..0709ec8
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/savestate/gwenesis_savestate.h
@@ -0,0 +1,45 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_savestate_H_
+#define _gwenesis_savestate_H_
+
+#pragma once
+
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+typedef struct SaveState SaveState;
+
+bool initLoadGwenesisState(unsigned char *srcBuffer);
+int saveGwenesisState(unsigned char *destBuffer, int save_size);
+int loadGwenesisState(unsigned char *srcBuffer);
+
+SaveState* saveGwenesisStateOpenForRead(const char* fileName);
+SaveState* saveGwenesisStateOpenForWrite(const char* fileName);
+
+int saveGwenesisStateGet(SaveState* state, const char* tagName);
+void saveGwenesisStateSet(SaveState* state, const char* tagName, int value);
+
+void saveGwenesisStateGetBuffer(SaveState* state, const char* tagName, void* buffer, int length);
+void saveGwenesisStateSetBuffer(SaveState* state, const char* tagName, void* buffer, int length);
+
+void gwenesis_save_state();
+void gwenesis_load_state();
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/gwenesis/sound/fn_table.h b/MCUME_pico2/picogen/gwenesis/sound/fn_table.h
new file mode 100755
index 0000000..e55fbb3
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/fn_table.h
@@ -0,0 +1,258 @@
+const unsigned int __in_flash() __aligned(4) fn_table[] = {
+ // freqbase: 6.000000
+  0, 12288, 24576, 36864, 49152, 61440, 73728, 86016, 98304, 110592, 122880, 135168, 147456, 159744, 172032, 184320 // 0x00000000
+, 196608, 208896, 221184, 233472, 245760, 258048, 270336, 282624, 294912, 307200, 319488, 331776, 344064, 356352, 368640, 380928 // 0x00000040
+, 393216, 405504, 417792, 430080, 442368, 454656, 466944, 479232, 491520, 503808, 516096, 528384, 540672, 552960, 565248, 577536 // 0x00000080
+, 589824, 602112, 614400, 626688, 638976, 651264, 663552, 675840, 688128, 700416, 712704, 724992, 737280, 749568, 761856, 774144 // 0x000000C0
+, 786432, 798720, 811008, 823296, 835584, 847872, 860160, 872448, 884736, 897024, 909312, 921600, 933888, 946176, 958464, 970752 // 0x00000100
+, 983040, 995328, 1007616, 1019904, 1032192, 1044480, 1056768, 1069056, 1081344, 1093632, 1105920, 1118208, 1130496, 1142784, 1155072, 1167360 // 0x00000140
+, 1179648, 1191936, 1204224, 1216512, 1228800, 1241088, 1253376, 1265664, 1277952, 1290240, 1302528, 1314816, 1327104, 1339392, 1351680, 1363968 // 0x00000180
+, 1376256, 1388544, 1400832, 1413120, 1425408, 1437696, 1449984, 1462272, 1474560, 1486848, 1499136, 1511424, 1523712, 1536000, 1548288, 1560576 // 0x000001C0
+, 1572864, 1585152, 1597440, 1609728, 1622016, 1634304, 1646592, 1658880, 1671168, 1683456, 1695744, 1708032, 1720320, 1732608, 1744896, 1757184 // 0x00000200
+, 1769472, 1781760, 1794048, 1806336, 1818624, 1830912, 1843200, 1855488, 1867776, 1880064, 1892352, 1904640, 1916928, 1929216, 1941504, 1953792 // 0x00000240
+, 1966080, 1978368, 1990656, 2002944, 2015232, 2027520, 2039808, 2052096, 2064384, 2076672, 2088960, 2101248, 2113536, 2125824, 2138112, 2150400 // 0x00000280
+, 2162688, 2174976, 2187264, 2199552, 2211840, 2224128, 2236416, 2248704, 2260992, 2273280, 2285568, 2297856, 2310144, 2322432, 2334720, 2347008 // 0x000002C0
+, 2359296, 2371584, 2383872, 2396160, 2408448, 2420736, 2433024, 2445312, 2457600, 2469888, 2482176, 2494464, 2506752, 2519040, 2531328, 2543616 // 0x00000300
+, 2555904, 2568192, 2580480, 2592768, 2605056, 2617344, 2629632, 2641920, 2654208, 2666496, 2678784, 2691072, 2703360, 2715648, 2727936, 2740224 // 0x00000340
+, 2752512, 2764800, 2777088, 2789376, 2801664, 2813952, 2826240, 2838528, 2850816, 2863104, 2875392, 2887680, 2899968, 2912256, 2924544, 2936832 // 0x00000380
+, 2949120, 2961408, 2973696, 2985984, 2998272, 3010560, 3022848, 3035136, 3047424, 3059712, 3072000, 3084288, 3096576, 3108864, 3121152, 3133440 // 0x000003C0
+, 3145728, 3158016, 3170304, 3182592, 3194880, 3207168, 3219456, 3231744, 3244032, 3256320, 3268608, 3280896, 3293184, 3305472, 3317760, 3330048 // 0x00000400
+, 3342336, 3354624, 3366912, 3379200, 3391488, 3403776, 3416064, 3428352, 3440640, 3452928, 3465216, 3477504, 3489792, 3502080, 3514368, 3526656 // 0x00000440
+, 3538944, 3551232, 3563520, 3575808, 3588096, 3600384, 3612672, 3624960, 3637248, 3649536, 3661824, 3674112, 3686400, 3698688, 3710976, 3723264 // 0x00000480
+, 3735552, 3747840, 3760128, 3772416, 3784704, 3796992, 3809280, 3821568, 3833856, 3846144, 3858432, 3870720, 3883008, 3895296, 3907584, 3919872 // 0x000004C0
+, 3932160, 3944448, 3956736, 3969024, 3981312, 3993600, 4005888, 4018176, 4030464, 4042752, 4055040, 4067328, 4079616, 4091904, 4104192, 4116480 // 0x00000500
+, 4128768, 4141056, 4153344, 4165632, 4177920, 4190208, 4202496, 4214784, 4227072, 4239360, 4251648, 4263936, 4276224, 4288512, 4300800, 4313088 // 0x00000540
+, 4325376, 4337664, 4349952, 4362240, 4374528, 4386816, 4399104, 4411392, 4423680, 4435968, 4448256, 4460544, 4472832, 4485120, 4497408, 4509696 // 0x00000580
+, 4521984, 4534272, 4546560, 4558848, 4571136, 4583424, 4595712, 4608000, 4620288, 4632576, 4644864, 4657152, 4669440, 4681728, 4694016, 4706304 // 0x000005C0
+, 4718592, 4730880, 4743168, 4755456, 4767744, 4780032, 4792320, 4804608, 4816896, 4829184, 4841472, 4853760, 4866048, 4878336, 4890624, 4902912 // 0x00000600
+, 4915200, 4927488, 4939776, 4952064, 4964352, 4976640, 4988928, 5001216, 5013504, 5025792, 5038080, 5050368, 5062656, 5074944, 5087232, 5099520 // 0x00000640
+, 5111808, 5124096, 5136384, 5148672, 5160960, 5173248, 5185536, 5197824, 5210112, 5222400, 5234688, 5246976, 5259264, 5271552, 5283840, 5296128 // 0x00000680
+, 5308416, 5320704, 5332992, 5345280, 5357568, 5369856, 5382144, 5394432, 5406720, 5419008, 5431296, 5443584, 5455872, 5468160, 5480448, 5492736 // 0x000006C0
+, 5505024, 5517312, 5529600, 5541888, 5554176, 5566464, 5578752, 5591040, 5603328, 5615616, 5627904, 5640192, 5652480, 5664768, 5677056, 5689344 // 0x00000700
+, 5701632, 5713920, 5726208, 5738496, 5750784, 5763072, 5775360, 5787648, 5799936, 5812224, 5824512, 5836800, 5849088, 5861376, 5873664, 5885952 // 0x00000740
+, 5898240, 5910528, 5922816, 5935104, 5947392, 5959680, 5971968, 5984256, 5996544, 6008832, 6021120, 6033408, 6045696, 6057984, 6070272, 6082560 // 0x00000780
+, 6094848, 6107136, 6119424, 6131712, 6144000, 6156288, 6168576, 6180864, 6193152, 6205440, 6217728, 6230016, 6242304, 6254592, 6266880, 6279168 // 0x000007C0
+, 6291456, 6303744, 6316032, 6328320, 6340608, 6352896, 6365184, 6377472, 6389760, 6402048, 6414336, 6426624, 6438912, 6451200, 6463488, 6475776 // 0x00000800
+, 6488064, 6500352, 6512640, 6524928, 6537216, 6549504, 6561792, 6574080, 6586368, 6598656, 6610944, 6623232, 6635520, 6647808, 6660096, 6672384 // 0x00000840
+, 6684672, 6696960, 6709248, 6721536, 6733824, 6746112, 6758400, 6770688, 6782976, 6795264, 6807552, 6819840, 6832128, 6844416, 6856704, 6868992 // 0x00000880
+, 6881280, 6893568, 6905856, 6918144, 6930432, 6942720, 6955008, 6967296, 6979584, 6991872, 7004160, 7016448, 7028736, 7041024, 7053312, 7065600 // 0x000008C0
+, 7077888, 7090176, 7102464, 7114752, 7127040, 7139328, 7151616, 7163904, 7176192, 7188480, 7200768, 7213056, 7225344, 7237632, 7249920, 7262208 // 0x00000900
+, 7274496, 7286784, 7299072, 7311360, 7323648, 7335936, 7348224, 7360512, 7372800, 7385088, 7397376, 7409664, 7421952, 7434240, 7446528, 7458816 // 0x00000940
+, 7471104, 7483392, 7495680, 7507968, 7520256, 7532544, 7544832, 7557120, 7569408, 7581696, 7593984, 7606272, 7618560, 7630848, 7643136, 7655424 // 0x00000980
+, 7667712, 7680000, 7692288, 7704576, 7716864, 7729152, 7741440, 7753728, 7766016, 7778304, 7790592, 7802880, 7815168, 7827456, 7839744, 7852032 // 0x000009C0
+, 7864320, 7876608, 7888896, 7901184, 7913472, 7925760, 7938048, 7950336, 7962624, 7974912, 7987200, 7999488, 8011776, 8024064, 8036352, 8048640 // 0x00000A00
+, 8060928, 8073216, 8085504, 8097792, 8110080, 8122368, 8134656, 8146944, 8159232, 8171520, 8183808, 8196096, 8208384, 8220672, 8232960, 8245248 // 0x00000A40
+, 8257536, 8269824, 8282112, 8294400, 8306688, 8318976, 8331264, 8343552, 8355840, 8368128, 8380416, 8392704, 8404992, 8417280, 8429568, 8441856 // 0x00000A80
+, 8454144, 8466432, 8478720, 8491008, 8503296, 8515584, 8527872, 8540160, 8552448, 8564736, 8577024, 8589312, 8601600, 8613888, 8626176, 8638464 // 0x00000AC0
+, 8650752, 8663040, 8675328, 8687616, 8699904, 8712192, 8724480, 8736768, 8749056, 8761344, 8773632, 8785920, 8798208, 8810496, 8822784, 8835072 // 0x00000B00
+, 8847360, 8859648, 8871936, 8884224, 8896512, 8908800, 8921088, 8933376, 8945664, 8957952, 8970240, 8982528, 8994816, 9007104, 9019392, 9031680 // 0x00000B40
+, 9043968, 9056256, 9068544, 9080832, 9093120, 9105408, 9117696, 9129984, 9142272, 9154560, 9166848, 9179136, 9191424, 9203712, 9216000, 9228288 // 0x00000B80
+, 9240576, 9252864, 9265152, 9277440, 9289728, 9302016, 9314304, 9326592, 9338880, 9351168, 9363456, 9375744, 9388032, 9400320, 9412608, 9424896 // 0x00000BC0
+, 9437184, 9449472, 9461760, 9474048, 9486336, 9498624, 9510912, 9523200, 9535488, 9547776, 9560064, 9572352, 9584640, 9596928, 9609216, 9621504 // 0x00000C00
+, 9633792, 9646080, 9658368, 9670656, 9682944, 9695232, 9707520, 9719808, 9732096, 9744384, 9756672, 9768960, 9781248, 9793536, 9805824, 9818112 // 0x00000C40
+, 9830400, 9842688, 9854976, 9867264, 9879552, 9891840, 9904128, 9916416, 9928704, 9940992, 9953280, 9965568, 9977856, 9990144, 10002432, 10014720 // 0x00000C80
+, 10027008, 10039296, 10051584, 10063872, 10076160, 10088448, 10100736, 10113024, 10125312, 10137600, 10149888, 10162176, 10174464, 10186752, 10199040, 10211328 // 0x00000CC0
+, 10223616, 10235904, 10248192, 10260480, 10272768, 10285056, 10297344, 10309632, 10321920, 10334208, 10346496, 10358784, 10371072, 10383360, 10395648, 10407936 // 0x00000D00
+, 10420224, 10432512, 10444800, 10457088, 10469376, 10481664, 10493952, 10506240, 10518528, 10530816, 10543104, 10555392, 10567680, 10579968, 10592256, 10604544 // 0x00000D40
+, 10616832, 10629120, 10641408, 10653696, 10665984, 10678272, 10690560, 10702848, 10715136, 10727424, 10739712, 10752000, 10764288, 10776576, 10788864, 10801152 // 0x00000D80
+, 10813440, 10825728, 10838016, 10850304, 10862592, 10874880, 10887168, 10899456, 10911744, 10924032, 10936320, 10948608, 10960896, 10973184, 10985472, 10997760 // 0x00000DC0
+, 11010048, 11022336, 11034624, 11046912, 11059200, 11071488, 11083776, 11096064, 11108352, 11120640, 11132928, 11145216, 11157504, 11169792, 11182080, 11194368 // 0x00000E00
+, 11206656, 11218944, 11231232, 11243520, 11255808, 11268096, 11280384, 11292672, 11304960, 11317248, 11329536, 11341824, 11354112, 11366400, 11378688, 11390976 // 0x00000E40
+, 11403264, 11415552, 11427840, 11440128, 11452416, 11464704, 11476992, 11489280, 11501568, 11513856, 11526144, 11538432, 11550720, 11563008, 11575296, 11587584 // 0x00000E80
+, 11599872, 11612160, 11624448, 11636736, 11649024, 11661312, 11673600, 11685888, 11698176, 11710464, 11722752, 11735040, 11747328, 11759616, 11771904, 11784192 // 0x00000EC0
+, 11796480, 11808768, 11821056, 11833344, 11845632, 11857920, 11870208, 11882496, 11894784, 11907072, 11919360, 11931648, 11943936, 11956224, 11968512, 11980800 // 0x00000F00
+, 11993088, 12005376, 12017664, 12029952, 12042240, 12054528, 12066816, 12079104, 12091392, 12103680, 12115968, 12128256, 12140544, 12152832, 12165120, 12177408 // 0x00000F40
+, 12189696, 12201984, 12214272, 12226560, 12238848, 12251136, 12263424, 12275712, 12288000, 12300288, 12312576, 12324864, 12337152, 12349440, 12361728, 12374016 // 0x00000F80
+, 12386304, 12398592, 12410880, 12423168, 12435456, 12447744, 12460032, 12472320, 12484608, 12496896, 12509184, 12521472, 12533760, 12546048, 12558336, 12570624 // 0x00000FC0
+, 12582912, 12595200, 12607488, 12619776, 12632064, 12644352, 12656640, 12668928, 12681216, 12693504, 12705792, 12718080, 12730368, 12742656, 12754944, 12767232 // 0x00001000
+, 12779520, 12791808, 12804096, 12816384, 12828672, 12840960, 12853248, 12865536, 12877824, 12890112, 12902400, 12914688, 12926976, 12939264, 12951552, 12963840 // 0x00001040
+, 12976128, 12988416, 13000704, 13012992, 13025280, 13037568, 13049856, 13062144, 13074432, 13086720, 13099008, 13111296, 13123584, 13135872, 13148160, 13160448 // 0x00001080
+, 13172736, 13185024, 13197312, 13209600, 13221888, 13234176, 13246464, 13258752, 13271040, 13283328, 13295616, 13307904, 13320192, 13332480, 13344768, 13357056 // 0x000010C0
+, 13369344, 13381632, 13393920, 13406208, 13418496, 13430784, 13443072, 13455360, 13467648, 13479936, 13492224, 13504512, 13516800, 13529088, 13541376, 13553664 // 0x00001100
+, 13565952, 13578240, 13590528, 13602816, 13615104, 13627392, 13639680, 13651968, 13664256, 13676544, 13688832, 13701120, 13713408, 13725696, 13737984, 13750272 // 0x00001140
+, 13762560, 13774848, 13787136, 13799424, 13811712, 13824000, 13836288, 13848576, 13860864, 13873152, 13885440, 13897728, 13910016, 13922304, 13934592, 13946880 // 0x00001180
+, 13959168, 13971456, 13983744, 13996032, 14008320, 14020608, 14032896, 14045184, 14057472, 14069760, 14082048, 14094336, 14106624, 14118912, 14131200, 14143488 // 0x000011C0
+, 14155776, 14168064, 14180352, 14192640, 14204928, 14217216, 14229504, 14241792, 14254080, 14266368, 14278656, 14290944, 14303232, 14315520, 14327808, 14340096 // 0x00001200
+, 14352384, 14364672, 14376960, 14389248, 14401536, 14413824, 14426112, 14438400, 14450688, 14462976, 14475264, 14487552, 14499840, 14512128, 14524416, 14536704 // 0x00001240
+, 14548992, 14561280, 14573568, 14585856, 14598144, 14610432, 14622720, 14635008, 14647296, 14659584, 14671872, 14684160, 14696448, 14708736, 14721024, 14733312 // 0x00001280
+, 14745600, 14757888, 14770176, 14782464, 14794752, 14807040, 14819328, 14831616, 14843904, 14856192, 14868480, 14880768, 14893056, 14905344, 14917632, 14929920 // 0x000012C0
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diff --git a/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.c b/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.c
new file mode 100755
index 0000000..f49465f
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.c
@@ -0,0 +1,299 @@
+#pragma GCC optimize("Ofast")
+/*
+    SN76489 emulation
+    by Maxim in 2001 and 2002
+    converted from my original Delphi implementation
+
+    I'm a C newbie so I'm sure there are loads of stupid things
+    in here which I'll come back to some day and redo
+
+    Includes:
+    - Super-high quality tone channel "oversampling" by calculating fractional positions on transitions
+    - Noise output pattern reverse engineered from actual SMS output
+    - Volume levels taken from actual SMS output
+
+    07/08/04  Charles MacDonald
+    Modified for use with SMS Plus:
+    - Added support for multiple PSG chips.
+    - Added reset/config/update routines.
+    - Added context management routines.
+    - Removed SN76489_GetValues().
+    - Removed some unused variables.
+
+    07/08/04  bzhxx few simplication for gwenesis to fit on MCU
+*/
+
+#pragma GCC optimize("Ofast")
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <signal.h>
+#include <stdio.h>
+#include <limits.h>
+#include "../bus/gwenesis_bus.h"
+#include "../sound/gwenesis_sn76489.h"
+
+#include <pico.h>
+
+extern int audio_enabled;
+
+/* compiler dependence */
+#ifndef INLINE
+#define INLINE static __always_inline
+#endif
+#define NoiseInitialState   0x8000  /* Initial state of shift register */
+#define PSG_CUTOFF          0x6     /* Value below which PSG does not output */
+// #define PSG_MAX_VOLUME 2800
+// static const uint16 chanVolume[16] = {
+//   PSG_MAX_VOLUME,               /*  MAX  */
+//   PSG_MAX_VOLUME * 0.794328234, /* -2dB  */
+//   PSG_MAX_VOLUME * 0.630957344, /* -4dB  */
+//   PSG_MAX_VOLUME * 0.501187233, /* -6dB  */
+//   PSG_MAX_VOLUME * 0.398107170, /* -8dB  */
+//   PSG_MAX_VOLUME * 0.316227766, /* -10dB */
+//   PSG_MAX_VOLUME * 0.251188643, /* -12dB */
+//   PSG_MAX_VOLUME * 0.199526231, /* -14dB */
+//   PSG_MAX_VOLUME * 0.158489319, /* -16dB */
+//   PSG_MAX_VOLUME * 0.125892541, /* -18dB */
+//   PSG_MAX_VOLUME * 0.1,         /* -20dB */
+//   PSG_MAX_VOLUME * 0.079432823, /* -22dB */
+//   PSG_MAX_VOLUME * 0.063095734, /* -24dB */
+//   PSG_MAX_VOLUME * 0.050118723, /* -26dB */
+//   PSG_MAX_VOLUME * 0.039810717, /* -28dB */
+//   0                             /*  OFF  */
+// };
+
+#define PSG_MAX_VOLUME_MAX 3100
+#define PSG_MAX_VOLUME_2dB (int)(PSG_MAX_VOLUME_MAX*0.794328234)
+#define PSG_MAX_VOLUME_4dB (int)(PSG_MAX_VOLUME_MAX*0.630957344)
+
+static const int PSGVolumeValues[16] = {
+    PSG_MAX_VOLUME_MAX,PSG_MAX_VOLUME_2dB,PSG_MAX_VOLUME_4dB,
+    PSG_MAX_VOLUME_MAX / 2,PSG_MAX_VOLUME_2dB / 2,PSG_MAX_VOLUME_4dB / 2,
+    PSG_MAX_VOLUME_MAX / 4,PSG_MAX_VOLUME_2dB / 4,PSG_MAX_VOLUME_4dB / 4,
+    PSG_MAX_VOLUME_MAX / 8,PSG_MAX_VOLUME_2dB / 8,PSG_MAX_VOLUME_4dB / 8,
+    PSG_MAX_VOLUME_MAX / 16,PSG_MAX_VOLUME_2dB / 16,PSG_MAX_VOLUME_4dB / 16,
+    0
+};
+
+extern uint8_t snd_accurate;
+
+
+static SN76489_Context gwenesis_SN76489;
+
+void gwenesis_SN76489_Init(int PSGClockValue, int SamplingRate, int freq_divisor) {
+    gwenesis_SN76489.dClock = (float)PSGClockValue / 16 / SamplingRate * GWENESIS_AUDIO_SAMPLING_DIVISOR;
+    gwenesis_SN76489.divisor = freq_divisor;
+
+    gwenesis_SN76489_Reset();
+}
+
+void gwenesis_SN76489_Reset() {
+    int i;
+
+    for (i = 0; i <= 3; i++) {
+        /* Initialise PSG state */
+        gwenesis_SN76489.Registers[2 * i] = 1; /* tone freq=1 */
+        gwenesis_SN76489.Registers[2 * i + 1] = 0xf; /* vol=off */
+        gwenesis_SN76489.NoiseFreq = 0x10;
+
+        /* Set counters to 0 */
+        gwenesis_SN76489.ToneFreqVals[i] = 0;
+
+        /* Set flip-flops to 1 */
+        gwenesis_SN76489.ToneFreqPos[i] = 1;
+
+        /* Set intermediate positions to do-not-use value */
+        gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+    }
+
+    gwenesis_SN76489.LatchedRegister = 0;
+
+    /* Initialise noise generator */
+    gwenesis_SN76489.NoiseShiftRegister = NoiseInitialState;
+
+    /* Zero clock */
+    gwenesis_SN76489.Clock = 0;
+    sn76489_index = 0;
+    sn76489_clock = 0;
+}
+
+void gwenesis_SN76489_SetContext(uint8* data) {
+    memcpy(&gwenesis_SN76489, data, sizeof(SN76489_Context));
+}
+
+void gwenesis_SN76489_GetContext(uint8* data) {
+    memcpy(data, &gwenesis_SN76489, sizeof(SN76489_Context));
+}
+
+uint8* gwenesis_SN76489_GetContextPtr() {
+    return (uint8 *)&gwenesis_SN76489;
+}
+
+int gwenesis_SN76489_GetContextSize(void) {
+    return sizeof(SN76489_Context);
+}
+
+INLINE void gwenesis_SN76489_Update(INT16* buffer, int length) {
+    int i, j;
+
+#pragma gcc unroll
+    for (j = 0; j < length; j++) {
+#pragma gcc unroll(2)
+        for (i = 0; i <= 2; ++i)
+            if (gwenesis_SN76489.IntermediatePos[i] != LONG_MIN)
+                gwenesis_SN76489.Channels[i] = __mul_instruction(gwenesis_SN76489.IntermediatePos[i],
+                        PSGVolumeValues[gwenesis_SN76489.Registers[__fast_mul(i, 2) + 1]]
+                        ) / 65536;
+            else
+                gwenesis_SN76489.Channels[i] = __mul_instruction(gwenesis_SN76489.ToneFreqPos[i], PSGVolumeValues[gwenesis_SN76489.Registers[__fast_mul(i, 2) + 1]]);
+
+        gwenesis_SN76489.Channels[3] = (short)(__mul_instruction(PSGVolumeValues[gwenesis_SN76489.Registers[7]], (
+                                                   gwenesis_SN76489.NoiseShiftRegister & 0x1)));
+
+        gwenesis_SN76489.Channels[3] <<= 1; /* Double noise volume to make some people happy */
+
+        buffer[j] = (gwenesis_SN76489.Channels[0]);
+        buffer[j] += (gwenesis_SN76489.Channels[1]);
+        buffer[j] += (gwenesis_SN76489.Channels[2]);
+        buffer[j] += (gwenesis_SN76489.Channels[3]);
+
+        gwenesis_SN76489.Clock += gwenesis_SN76489.dClock;
+        gwenesis_SN76489.NumClocksForSample = (int)gwenesis_SN76489.Clock; /* truncates */
+        gwenesis_SN76489.Clock -= gwenesis_SN76489.NumClocksForSample; /* remove integer part */
+
+        /* Decrement tone channel counters */
+        for (i = 0; i <= 2; ++i)
+            gwenesis_SN76489.ToneFreqVals[i] -= gwenesis_SN76489.NumClocksForSample;
+
+        /* Noise channel: match to tone2 or decrement its counter */
+        if (gwenesis_SN76489.NoiseFreq == 0x80) gwenesis_SN76489.ToneFreqVals[3] = gwenesis_SN76489.ToneFreqVals[2];
+        else gwenesis_SN76489.ToneFreqVals[3] -= gwenesis_SN76489.NumClocksForSample;
+
+        /* Tone channels: */
+#pragma gcc unroll(4)
+        for (i = 0; i <= 2; ++i) {
+            if (gwenesis_SN76489.ToneFreqVals[i] <= 0) {
+                /* If it gets below 0... */
+                if (gwenesis_SN76489.Registers[__fast_mul(i, 2)] > PSG_CUTOFF) {
+                    /* Calculate how much of the sample is + and how much is - */
+                    /* Go to floating point and include the clock fraction for extreme accuracy :D */
+                    /* Store as long int, maybe it's faster? I'm not very good at this */
+                    gwenesis_SN76489.IntermediatePos[i] = (long)(
+                        (gwenesis_SN76489.NumClocksForSample - gwenesis_SN76489.Clock +
+                            __fast_mul(gwenesis_SN76489.ToneFreqVals[i], 2)
+                            )
+                            * gwenesis_SN76489.ToneFreqPos[i] / (__fast_mul(gwenesis_SN76489.NumClocksForSample + gwenesis_SN76489.Clock,65536)));
+                    gwenesis_SN76489.ToneFreqPos[i] = -gwenesis_SN76489.ToneFreqPos[i]; /* Flip the flip-flop */
+                }
+                else {
+                    gwenesis_SN76489.ToneFreqPos[i] = 1; /* stuck value */
+                    gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+                }
+                gwenesis_SN76489.ToneFreqVals[i] += gwenesis_SN76489.Registers[__fast_mul(i,2)] * (gwenesis_SN76489.NumClocksForSample / gwenesis_SN76489.Registers[__fast_mul(i, 2)] + 1);
+            }
+            else gwenesis_SN76489.IntermediatePos[i] = LONG_MIN;
+        }
+
+        /* Noise channel */
+        if (gwenesis_SN76489.ToneFreqVals[3] <= 0) {
+            /* If it gets below 0... */
+            gwenesis_SN76489.ToneFreqPos[3] = -gwenesis_SN76489.ToneFreqPos[3]; /* Flip the flip-flop */
+            if (gwenesis_SN76489.NoiseFreq != 0x80) /* If not matching tone2, decrement counter */
+                gwenesis_SN76489.ToneFreqVals[3] += __mul_instruction(gwenesis_SN76489.NoiseFreq, (
+                    gwenesis_SN76489.NumClocksForSample / gwenesis_SN76489.NoiseFreq + 1));
+            if (gwenesis_SN76489.ToneFreqPos[3] == 1) {
+                /* Only once per cycle... */
+                int Feedback;
+                if (gwenesis_SN76489.Registers[6] & 0x4) {
+                    /* White noise */
+                    /* Calculate parity of fed-back bits for feedback */
+
+                    /* If two bits fed back, I can do Feedback=(nsr & fb) && (nsr & fb ^ fb) */
+                    /* since that's (one or more bits set) && (not all bits set) */
+                    Feedback = ((gwenesis_SN76489.NoiseShiftRegister & gwenesis_SN76489.WhiteNoiseFeedback) && (
+                                    (gwenesis_SN76489.NoiseShiftRegister & gwenesis_SN76489.WhiteNoiseFeedback) ^
+                                    gwenesis_SN76489.WhiteNoiseFeedback));
+                }
+                else /* Periodic noise */
+                    Feedback = gwenesis_SN76489.NoiseShiftRegister & 1;
+
+                gwenesis_SN76489.NoiseShiftRegister = (gwenesis_SN76489.NoiseShiftRegister >> 1) | (Feedback << 15);
+            }
+        }
+    }
+}
+
+/* SN76589 execution */
+extern int scan_line;
+extern bool sn76489_enabled;
+
+void YM2612Update(uint16_t *buffer, int length);
+
+void gwenesis_SN76489_run(int target) {
+    if (sn76489_clock >= target) return;
+
+    target /= GWENESIS_AUDIO_SAMPLING_DIVISOR;
+
+    int sn76489_prev_index = sn76489_index;
+    sn76489_index += (target - sn76489_clock) / gwenesis_SN76489.divisor;
+    if (sn76489_index > sn76489_prev_index) {
+        int16* buf = gwenesis_sn76489_buffer + sn76489_prev_index;
+        int len = sn76489_index - sn76489_prev_index;
+        if (sn76489_enabled) gwenesis_SN76489_Update(buf, len);
+        YM2612Update(buf, len);
+        sn76489_clock = __mul_instruction(sn76489_index, gwenesis_SN76489.divisor);
+    }
+    else {
+        sn76489_index = sn76489_prev_index;
+    }
+}
+
+void gwenesis_SN76489_Write(int data, int target) {
+    if (!audio_enabled)
+        return;
+
+    if (snd_accurate == 1)
+        gwenesis_SN76489_run(target);
+
+    if (data & 0x80) {
+        /* Latch/data byte  %1 cc t dddd */
+        gwenesis_SN76489.LatchedRegister = ((data >> 4) & 0x07);
+        gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] =
+                (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] &
+                 0x3f0) /* zero low 4 bits */
+                | (data & 0xf); /* and replace with data */
+    }
+    else {
+        /* Data byte        %0 - dddddd */
+        if (!(gwenesis_SN76489.LatchedRegister % 2) && (gwenesis_SN76489.LatchedRegister < 5))
+            /* Tone register */
+            gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] =
+                    (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] & 0x00f) /* zero high 6 bits */
+                    | ((data & 0x3f) << 4); /* and replace with data */
+        else
+            /* Other register */
+            gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] = data & 0x0f; /* Replace with data */
+    }
+    switch (gwenesis_SN76489.LatchedRegister) {
+        case 0:
+        case 2:
+        case 4: /* Tone channels */
+            if (gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] == 0)
+                gwenesis_SN76489.Registers[gwenesis_SN76489.LatchedRegister] = 1;
+        /* Zero frequency changed to 1 to avoid div/0 */
+            break;
+        case 6: /* Noise */
+            gwenesis_SN76489.NoiseShiftRegister = NoiseInitialState; /* reset shift register */
+            gwenesis_SN76489.NoiseFreq = 0x10 << (gwenesis_SN76489.Registers[6] & 0x3);
+        /* set noise signal generator frequency */
+            break;
+    }
+}
+
+void gwenesis_sn76489_save_state() {
+}
+
+void gwenesis_sn76489_load_state() {
+}
diff --git a/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.h b/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.h
new file mode 100755
index 0000000..94c0dae
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/gwenesis_sn76489.h
@@ -0,0 +1,73 @@
+
+#ifndef _GWENESIS_SN76489_H_
+#define _GWENESIS_SN76489_H_
+
+/*
+    More testing is needed to find and confirm feedback patterns for
+    SN76489 variants and compatible chips.
+*/
+
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+
+typedef unsigned char uint8;
+typedef unsigned short int uint16;
+typedef unsigned int uint32;
+
+typedef signed char int8;
+typedef signed short int int16;
+typedef signed int int32;
+
+typedef unsigned char UINT8;
+typedef unsigned short int UINT16;
+typedef unsigned int UINT32;
+
+typedef signed char INT8;
+typedef signed short int INT16;
+typedef signed int INT32;
+typedef long signed int INT641;
+
+typedef struct
+{
+    /* Variables */
+    float Clock;
+    float dClock;
+    int NumClocksForSample;
+    int WhiteNoiseFeedback;
+    int divisor;
+
+    /* PSG registers: */
+    UINT16 Registers[8];        /* Tone, vol x4 */
+    int LatchedRegister;
+    UINT16 NoiseShiftRegister;
+    INT16 NoiseFreq;            /* Noise channel signal generator frequency */
+
+    /* Output calculation variables */
+    INT16 ToneFreqVals[4];      /* Frequency register values (counters) */
+    INT8 ToneFreqPos[4];        /* Frequency channel flip-flops */
+    INT16 Channels[4];          /* Value of each channel, before stereo is applied */
+    INT641 IntermediatePos[4];   /* intermediate values used at boundaries between + and - */
+
+} SN76489_Context;
+
+extern int16 gwenesis_sn76489_buffer[];
+extern int sn76489_index;
+extern int sn76489_clock;
+
+/* Function prototypes */
+void gwenesis_SN76489_Init( int PSGClockValue, int SamplingRate,int freq_divisor);
+void gwenesis_SN76489_Reset();
+void gwenesis_SN76489_start();
+void gwenesis_SN76489_SetContext(uint8 *data);
+void gwenesis_SN76489_GetContext(uint8 *data);
+uint8 *gwenesis_SN76489_GetContextPtr();
+int gwenesis_SN76489_GetContextSize(void);
+void gwenesis_SN76489_Write(int data, int target);
+void gwenesis_SN76489_run(int target);
+
+void gwenesis_sn76489_save_state();
+void gwenesis_sn76489_load_state();
+
+#endif /* _GWENESIS_SN76489_H_ */
diff --git a/MCUME_pico2/picogen/gwenesis/sound/lfo_pm_table.h b/MCUME_pico2/picogen/gwenesis/sound/lfo_pm_table.h
new file mode 100755
index 0000000..8d97448
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/lfo_pm_table.h
@@ -0,0 +1,1025 @@
+const unsigned char __in_flash() __aligned(4) lfo_pm_table[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000000
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000010
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000020
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000030
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000040
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000050
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000060
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000070
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000080
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000090
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000C0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000D0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000000E0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000000F0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000100
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000110
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000120
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000130
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000140
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000150
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x00000160
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x00000170
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000180
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000190
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001C0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000001D0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000001E0
+, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x03, 0x04, 0x04, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00 // 0x000001F0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000200
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000210
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000220
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000230
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000240
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x00000250
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x00000260
+, 0x00, 0x00, 0x02, 0x03, 0x04, 0x04, 0x05, 0x06, 0x06, 0x05, 0x04, 0x04, 0x03, 0x02, 0x00, 0x00 // 0x00000270
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000280
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000290
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002A0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002B0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x000002C0
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x000002D0
+, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00 // 0x000002E0
+, 0x00, 0x00, 0x02, 0x03, 0x05, 0x05, 0x06, 0x07, 0x07, 0x06, 0x05, 0x05, 0x03, 0x02, 0x00, 0x00 // 0x000002F0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000300
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000310
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000320
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000330
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000340
+, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 // 0x00000350
+, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x03, 0x04, 0x04, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00 // 0x00000360
+, 0x00, 0x00, 0x03, 0x04, 0x06, 0x06, 0x07, 0x09, 0x09, 0x07, 0x06, 0x06, 0x04, 0x03, 0x00, 0x00 // 0x00000370
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00000380
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+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001810
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+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001830
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+, 0x00, 0x00, 0x0C, 0x12, 0x18, 0x18, 0x1E, 0x24, 0x24, 0x1E, 0x18, 0x18, 0x12, 0x0C, 0x00, 0x00 // 0x00001860
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+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x000018A0
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+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001920
+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001930
+, 0x00, 0x00, 0x03, 0x06, 0x06, 0x06, 0x09, 0x0C, 0x0C, 0x09, 0x06, 0x06, 0x06, 0x03, 0x00, 0x00 // 0x00001940
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+, 0x00, 0x00, 0x0C, 0x12, 0x19, 0x19, 0x1F, 0x25, 0x25, 0x1F, 0x19, 0x19, 0x12, 0x0C, 0x00, 0x00 // 0x00001960
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+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x000019B0
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+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001A30
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+, 0x00, 0x00, 0x03, 0x06, 0x06, 0x06, 0x09, 0x0D, 0x0D, 0x09, 0x06, 0x06, 0x06, 0x03, 0x00, 0x00 // 0x00001AC0
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+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001B10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001B20
+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001B30
+, 0x00, 0x00, 0x03, 0x06, 0x06, 0x06, 0x09, 0x0D, 0x0D, 0x09, 0x06, 0x06, 0x06, 0x03, 0x00, 0x00 // 0x00001B40
+, 0x00, 0x00, 0x06, 0x09, 0x0D, 0x0D, 0x10, 0x13, 0x13, 0x10, 0x0D, 0x0D, 0x09, 0x06, 0x00, 0x00 // 0x00001B50
+, 0x00, 0x00, 0x0D, 0x13, 0x1B, 0x1B, 0x21, 0x28, 0x28, 0x21, 0x1B, 0x1B, 0x13, 0x0D, 0x00, 0x00 // 0x00001B60
+, 0x00, 0x00, 0x1B, 0x28, 0x36, 0x36, 0x43, 0x51, 0x51, 0x43, 0x36, 0x36, 0x28, 0x1B, 0x00, 0x00 // 0x00001B70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001B80
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001B90
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001BA0
+, 0x00, 0x00, 0x03, 0x03, 0x06, 0x06, 0x09, 0x09, 0x09, 0x09, 0x06, 0x06, 0x03, 0x03, 0x00, 0x00 // 0x00001BB0
+, 0x00, 0x00, 0x03, 0x06, 0x06, 0x06, 0x09, 0x0D, 0x0D, 0x09, 0x06, 0x06, 0x06, 0x03, 0x00, 0x00 // 0x00001BC0
+, 0x00, 0x00, 0x06, 0x09, 0x0D, 0x0D, 0x10, 0x13, 0x13, 0x10, 0x0D, 0x0D, 0x09, 0x06, 0x00, 0x00 // 0x00001BD0
+, 0x00, 0x00, 0x0D, 0x13, 0x1B, 0x1B, 0x21, 0x28, 0x28, 0x21, 0x1B, 0x1B, 0x13, 0x0D, 0x00, 0x00 // 0x00001BE0
+, 0x00, 0x00, 0x1B, 0x28, 0x37, 0x37, 0x44, 0x52, 0x52, 0x44, 0x37, 0x37, 0x28, 0x1B, 0x00, 0x00 // 0x00001BF0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001C00
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001C10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001C20
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+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0E, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001C40
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+, 0x00, 0x00, 0x1C, 0x2A, 0x38, 0x38, 0x46, 0x54, 0x54, 0x46, 0x38, 0x38, 0x2A, 0x1C, 0x00, 0x00 // 0x00001C70
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+, 0x00, 0x00, 0x0E, 0x15, 0x1C, 0x1C, 0x23, 0x2A, 0x2A, 0x23, 0x1C, 0x1C, 0x15, 0x0E, 0x00, 0x00 // 0x00001CE0
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+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001D10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001D20
+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001D30
+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0E, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001D40
+, 0x00, 0x00, 0x07, 0x0A, 0x0E, 0x0E, 0x11, 0x15, 0x15, 0x11, 0x0E, 0x0E, 0x0A, 0x07, 0x00, 0x00 // 0x00001D50
+, 0x00, 0x00, 0x0E, 0x15, 0x1D, 0x1D, 0x24, 0x2B, 0x2B, 0x24, 0x1D, 0x1D, 0x15, 0x0E, 0x00, 0x00 // 0x00001D60
+, 0x00, 0x00, 0x1D, 0x2B, 0x3A, 0x3A, 0x48, 0x57, 0x57, 0x48, 0x3A, 0x3A, 0x2B, 0x1D, 0x00, 0x00 // 0x00001D70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001D80
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001D90
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001DA0
+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001DB0
+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0E, 0x0E, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001DC0
+, 0x00, 0x00, 0x07, 0x0A, 0x0E, 0x0E, 0x11, 0x15, 0x15, 0x11, 0x0E, 0x0E, 0x0A, 0x07, 0x00, 0x00 // 0x00001DD0
+, 0x00, 0x00, 0x0E, 0x15, 0x1D, 0x1D, 0x24, 0x2B, 0x2B, 0x24, 0x1D, 0x1D, 0x15, 0x0E, 0x00, 0x00 // 0x00001DE0
+, 0x00, 0x00, 0x1D, 0x2B, 0x3B, 0x3B, 0x49, 0x58, 0x58, 0x49, 0x3B, 0x3B, 0x2B, 0x1D, 0x00, 0x00 // 0x00001DF0
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001E00
+, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 // 0x00001E10
+, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00 // 0x00001E20
+, 0x00, 0x00, 0x03, 0x03, 0x07, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x07, 0x07, 0x03, 0x03, 0x00, 0x00 // 0x00001E30
+, 0x00, 0x00, 0x03, 0x07, 0x07, 0x07, 0x0A, 0x0F, 0x0F, 0x0A, 0x07, 0x07, 0x07, 0x03, 0x00, 0x00 // 0x00001E40
+, 0x00, 0x00, 0x07, 0x0A, 0x0F, 0x0F, 0x12, 0x16, 0x16, 0x12, 0x0F, 0x0F, 0x0A, 0x07, 0x00, 0x00 // 0x00001E50
+, 0x00, 0x00, 0x0F, 0x16, 0x1E, 0x1E, 0x25, 0x2D, 0x2D, 0x25, 0x1E, 0x1E, 0x16, 0x0F, 0x00, 0x00 // 0x00001E60
+, 0x00, 0x00, 0x1E, 0x2D, 0x3C, 0x3C, 0x4B, 0x5A, 0x5A, 0x4B, 0x3C, 0x3C, 0x2D, 0x1E, 0x00, 0x00 // 0x00001E70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00001E80
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+, 0x00, 0x00, 0x3F, 0x5E, 0x7E, 0x7E, 0x9D, 0xBD, 0xBD, 0x9D, 0x7E, 0x7E, 0x5E, 0x3F, 0x00, 0x00 // 0x00003F70
+, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00003F80
+, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00 // 0x00003F90
+, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x00, 0x00, 0x00 // 0x00003FA0
+, 0x00, 0x00, 0x07, 0x07, 0x0F, 0x0F, 0x16, 0x16, 0x16, 0x16, 0x0F, 0x0F, 0x07, 0x07, 0x00, 0x00 // 0x00003FB0
+, 0x00, 0x00, 0x07, 0x0F, 0x0F, 0x0F, 0x16, 0x1F, 0x1F, 0x16, 0x0F, 0x0F, 0x0F, 0x07, 0x00, 0x00 // 0x00003FC0
+, 0x00, 0x00, 0x0F, 0x16, 0x1F, 0x1F, 0x26, 0x2E, 0x2E, 0x26, 0x1F, 0x1F, 0x16, 0x0F, 0x00, 0x00 // 0x00003FD0
+, 0x00, 0x00, 0x1F, 0x2E, 0x3F, 0x3F, 0x4E, 0x5E, 0x5E, 0x4E, 0x3F, 0x3F, 0x2E, 0x1F, 0x00, 0x00 // 0x00003FE0
+, 0x00, 0x00, 0x3F, 0x5E, 0x7F, 0x7F, 0x9E, 0xBE, 0xBE, 0x9E, 0x7F, 0x7F, 0x5E, 0x3F, 0x00, 0x00};
diff --git a/MCUME_pico2/picogen/gwenesis/sound/sin_tab.h b/MCUME_pico2/picogen/gwenesis/sound/sin_tab.h
new file mode 100755
index 0000000..8c73012
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/sin_tab.h
@@ -0,0 +1,65 @@
+const unsigned int __in_flash() __aligned(4) sin_tab[] = {
+  4274, 3462, 3086, 2838, 2652, 2504, 2380, 2274, 2182, 2100, 2026, 1958, 1898, 1840, 1788, 1738 // 0x00000000
+, 1692, 1650, 1608, 1570, 1534, 1498, 1464, 1434, 1402, 1374, 1344, 1318, 1292, 1266, 1242, 1218 // 0x00000040
+, 1196, 1174, 1152, 1132, 1112, 1092, 1072, 1054, 1036, 1018, 1002, 984, 968, 952, 936, 922 // 0x00000080
+, 906, 892, 878, 864, 850, 836, 822, 810, 798, 784, 772, 760, 750, 738, 726, 716 // 0x000000C0
+, 704, 694, 682, 672, 662, 652, 642, 632, 622, 614, 604, 594, 586, 578, 568, 560 // 0x00000100
+, 552, 542, 534, 526, 518, 510, 502, 496, 488, 480, 472, 466, 458, 452, 444, 438 // 0x00000140
+, 430, 424, 418, 410, 404, 398, 392, 386, 380, 374, 368, 362, 356, 350, 344, 338 // 0x00000180
+, 334, 328, 322, 318, 312, 306, 302, 296, 292, 286, 282, 276, 272, 268, 262, 258 // 0x000001C0
+, 254, 250, 244, 240, 236, 232, 228, 224, 220, 216, 212, 208, 204, 200, 196, 192 // 0x00000200
+, 188, 184, 182, 178, 174, 170, 166, 164, 160, 156, 154, 150, 148, 144, 140, 138 // 0x00000240
+, 134, 132, 128, 126, 124, 120, 118, 114, 112, 110, 106, 104, 102, 98, 96, 94 // 0x00000280
+, 92, 90, 86, 84, 82, 80, 78, 76, 74, 72, 70, 68, 66, 64, 62, 60 // 0x000002C0
+, 58, 56, 54, 52, 50, 48, 46, 46, 44, 42, 40, 40, 38, 36, 34, 34 // 0x00000300
+, 32, 30, 30, 28, 26, 26, 24, 24, 22, 20, 20, 18, 18, 16, 16, 14 // 0x00000340
+, 14, 14, 12, 12, 10, 10, 10, 8, 8, 8, 6, 6, 6, 4, 4, 4 // 0x00000380
+, 4, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0 // 0x000003C0
+, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 4 // 0x00000400
+, 4, 4, 4, 6, 6, 6, 8, 8, 8, 10, 10, 10, 12, 12, 14, 14 // 0x00000440
+, 14, 16, 16, 18, 18, 20, 20, 22, 24, 24, 26, 26, 28, 30, 30, 32 // 0x00000480
+, 34, 34, 36, 38, 40, 40, 42, 44, 46, 46, 48, 50, 52, 54, 56, 58 // 0x000004C0
+, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 90, 92 // 0x00000500
+, 94, 96, 98, 102, 104, 106, 110, 112, 114, 118, 120, 124, 126, 128, 132, 134 // 0x00000540
+, 138, 140, 144, 148, 150, 154, 156, 160, 164, 166, 170, 174, 178, 182, 184, 188 // 0x00000580
+, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 250, 254 // 0x000005C0
+, 258, 262, 268, 272, 276, 282, 286, 292, 296, 302, 306, 312, 318, 322, 328, 334 // 0x00000600
+, 338, 344, 350, 356, 362, 368, 374, 380, 386, 392, 398, 404, 410, 418, 424, 430 // 0x00000640
+, 438, 444, 452, 458, 466, 472, 480, 488, 496, 502, 510, 518, 526, 534, 542, 552 // 0x00000680
+, 560, 568, 578, 586, 594, 604, 614, 622, 632, 642, 652, 662, 672, 682, 694, 704 // 0x000006C0
+, 716, 726, 738, 750, 760, 772, 784, 798, 810, 822, 836, 850, 864, 878, 892, 906 // 0x00000700
+, 922, 936, 952, 968, 984, 1002, 1018, 1036, 1054, 1072, 1092, 1112, 1132, 1152, 1174, 1196 // 0x00000740
+, 1218, 1242, 1266, 1292, 1318, 1344, 1374, 1402, 1434, 1464, 1498, 1534, 1570, 1608, 1650, 1692 // 0x00000780
+, 1738, 1788, 1840, 1898, 1958, 2026, 2100, 2182, 2274, 2380, 2504, 2652, 2838, 3086, 3462, 4274 // 0x000007C0
+, 4275, 3463, 3087, 2839, 2653, 2505, 2381, 2275, 2183, 2101, 2027, 1959, 1899, 1841, 1789, 1739 // 0x00000800
+, 1693, 1651, 1609, 1571, 1535, 1499, 1465, 1435, 1403, 1375, 1345, 1319, 1293, 1267, 1243, 1219 // 0x00000840
+, 1197, 1175, 1153, 1133, 1113, 1093, 1073, 1055, 1037, 1019, 1003, 985, 969, 953, 937, 923 // 0x00000880
+, 907, 893, 879, 865, 851, 837, 823, 811, 799, 785, 773, 761, 751, 739, 727, 717 // 0x000008C0
+, 705, 695, 683, 673, 663, 653, 643, 633, 623, 615, 605, 595, 587, 579, 569, 561 // 0x00000900
+, 553, 543, 535, 527, 519, 511, 503, 497, 489, 481, 473, 467, 459, 453, 445, 439 // 0x00000940
+, 431, 425, 419, 411, 405, 399, 393, 387, 381, 375, 369, 363, 357, 351, 345, 339 // 0x00000980
+, 335, 329, 323, 319, 313, 307, 303, 297, 293, 287, 283, 277, 273, 269, 263, 259 // 0x000009C0
+, 255, 251, 245, 241, 237, 233, 229, 225, 221, 217, 213, 209, 205, 201, 197, 193 // 0x00000A00
+, 189, 185, 183, 179, 175, 171, 167, 165, 161, 157, 155, 151, 149, 145, 141, 139 // 0x00000A40
+, 135, 133, 129, 127, 125, 121, 119, 115, 113, 111, 107, 105, 103, 99, 97, 95 // 0x00000A80
+, 93, 91, 87, 85, 83, 81, 79, 77, 75, 73, 71, 69, 67, 65, 63, 61 // 0x00000AC0
+, 59, 57, 55, 53, 51, 49, 47, 47, 45, 43, 41, 41, 39, 37, 35, 35 // 0x00000B00
+, 33, 31, 31, 29, 27, 27, 25, 25, 23, 21, 21, 19, 19, 17, 17, 15 // 0x00000B40
+, 15, 15, 13, 13, 11, 11, 11, 9, 9, 9, 7, 7, 7, 5, 5, 5 // 0x00000B80
+, 5, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1 // 0x00000BC0
+, 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 5 // 0x00000C00
+, 5, 5, 5, 7, 7, 7, 9, 9, 9, 11, 11, 11, 13, 13, 15, 15 // 0x00000C40
+, 15, 17, 17, 19, 19, 21, 21, 23, 25, 25, 27, 27, 29, 31, 31, 33 // 0x00000C80
+, 35, 35, 37, 39, 41, 41, 43, 45, 47, 47, 49, 51, 53, 55, 57, 59 // 0x00000CC0
+, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 91, 93 // 0x00000D00
+, 95, 97, 99, 103, 105, 107, 111, 113, 115, 119, 121, 125, 127, 129, 133, 135 // 0x00000D40
+, 139, 141, 145, 149, 151, 155, 157, 161, 165, 167, 171, 175, 179, 183, 185, 189 // 0x00000D80
+, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 251, 255 // 0x00000DC0
+, 259, 263, 269, 273, 277, 283, 287, 293, 297, 303, 307, 313, 319, 323, 329, 335 // 0x00000E00
+, 339, 345, 351, 357, 363, 369, 375, 381, 387, 393, 399, 405, 411, 419, 425, 431 // 0x00000E40
+, 439, 445, 453, 459, 467, 473, 481, 489, 497, 503, 511, 519, 527, 535, 543, 553 // 0x00000E80
+, 561, 569, 579, 587, 595, 605, 615, 623, 633, 643, 653, 663, 673, 683, 695, 705 // 0x00000EC0
+, 717, 727, 739, 751, 761, 773, 785, 799, 811, 823, 837, 851, 865, 879, 893, 907 // 0x00000F00
+, 923, 937, 953, 969, 985, 1003, 1019, 1037, 1055, 1073, 1093, 1113, 1133, 1153, 1175, 1197 // 0x00000F40
+, 1219, 1243, 1267, 1293, 1319, 1345, 1375, 1403, 1435, 1465, 1499, 1535, 1571, 1609, 1651, 1693 // 0x00000F80
+, 1739, 1789, 1841, 1899, 1959, 2027, 2101, 2183, 2275, 2381, 2505, 2653, 2839, 3087, 3463, 4275};
diff --git a/MCUME_pico2/picogen/gwenesis/sound/tl_tab.h b/MCUME_pico2/picogen/gwenesis/sound/tl_tab.h
new file mode 100755
index 0000000..391db36
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/tl_tab.h
@@ -0,0 +1,417 @@
+const signed int __in_flash() __aligned(4) tl_tab[] = {
+  8168, -8168, 8148, -8148, 8124, -8124, 8104, -8104, 8080, -8080, 8060, -8060, 8040, -8040, 8016, -8016 // 0x00000000
+, 7996, -7996, 7972, -7972, 7952, -7952, 7932, -7932, 7908, -7908, 7888, -7888, 7864, -7864, 7844, -7844 // 0x00000040
+, 7824, -7824, 7804, -7804, 7780, -7780, 7760, -7760, 7740, -7740, 7720, -7720, 7696, -7696, 7676, -7676 // 0x00000080
+, 7656, -7656, 7636, -7636, 7616, -7616, 7592, -7592, 7572, -7572, 7552, -7552, 7532, -7532, 7512, -7512 // 0x000000C0
+, 7492, -7492, 7472, -7472, 7452, -7452, 7432, -7432, 7412, -7412, 7392, -7392, 7372, -7372, 7352, -7352 // 0x00000100
+, 7332, -7332, 7312, -7312, 7292, -7292, 7272, -7272, 7252, -7252, 7232, -7232, 7212, -7212, 7192, -7192 // 0x00000140
+, 7176, -7176, 7156, -7156, 7136, -7136, 7116, -7116, 7096, -7096, 7076, -7076, 7060, -7060, 7040, -7040 // 0x00000180
+, 7020, -7020, 7000, -7000, 6984, -6984, 6964, -6964, 6944, -6944, 6928, -6928, 6908, -6908, 6888, -6888 // 0x000001C0
+, 6868, -6868, 6852, -6852, 6832, -6832, 6816, -6816, 6796, -6796, 6776, -6776, 6760, -6760, 6740, -6740 // 0x00000200
+, 6724, -6724, 6704, -6704, 6688, -6688, 6668, -6668, 6652, -6652, 6632, -6632, 6616, -6616, 6596, -6596 // 0x00000240
+, 6580, -6580, 6560, -6560, 6544, -6544, 6524, -6524, 6508, -6508, 6492, -6492, 6472, -6472, 6456, -6456 // 0x00000280
+, 6436, -6436, 6420, -6420, 6404, -6404, 6384, -6384, 6368, -6368, 6352, -6352, 6336, -6336, 6316, -6316 // 0x000002C0
+, 6300, -6300, 6284, -6284, 6264, -6264, 6248, -6248, 6232, -6232, 6216, -6216, 6200, -6200, 6180, -6180 // 0x00000300
+, 6164, -6164, 6148, -6148, 6132, -6132, 6116, -6116, 6100, -6100, 6080, -6080, 6064, -6064, 6048, -6048 // 0x00000340
+, 6032, -6032, 6016, -6016, 6000, -6000, 5984, -5984, 5968, -5968, 5952, -5952, 5936, -5936, 5920, -5920 // 0x00000380
+, 5904, -5904, 5888, -5888, 5872, -5872, 5856, -5856, 5840, -5840, 5824, -5824, 5808, -5808, 5792, -5792 // 0x000003C0
+, 5776, -5776, 5760, -5760, 5744, -5744, 5732, -5732, 5716, -5716, 5700, -5700, 5684, -5684, 5668, -5668 // 0x00000400
+, 5652, -5652, 5636, -5636, 5624, -5624, 5608, -5608, 5592, -5592, 5576, -5576, 5564, -5564, 5548, -5548 // 0x00000440
+, 5532, -5532, 5516, -5516, 5504, -5504, 5488, -5488, 5472, -5472, 5456, -5456, 5444, -5444, 5428, -5428 // 0x00000480
+, 5412, -5412, 5400, -5400, 5384, -5384, 5368, -5368, 5356, -5356, 5340, -5340, 5328, -5328, 5312, -5312 // 0x000004C0
+, 5296, -5296, 5284, -5284, 5268, -5268, 5256, -5256, 5240, -5240, 5228, -5228, 5212, -5212, 5200, -5200 // 0x00000500
+, 5184, -5184, 5168, -5168, 5156, -5156, 5144, -5144, 5128, -5128, 5116, -5116, 5100, -5100, 5088, -5088 // 0x00000540
+, 5072, -5072, 5060, -5060, 5044, -5044, 5032, -5032, 5020, -5020, 5004, -5004, 4992, -4992, 4976, -4976 // 0x00000580
+, 4964, -4964, 4952, -4952, 4936, -4936, 4924, -4924, 4912, -4912, 4896, -4896, 4884, -4884, 4872, -4872 // 0x000005C0
+, 4856, -4856, 4844, -4844, 4832, -4832, 4820, -4820, 4804, -4804, 4792, -4792, 4780, -4780, 4768, -4768 // 0x00000600
+, 4752, -4752, 4740, -4740, 4728, -4728, 4716, -4716, 4704, -4704, 4688, -4688, 4676, -4676, 4664, -4664 // 0x00000640
+, 4652, -4652, 4640, -4640, 4628, -4628, 4616, -4616, 4600, -4600, 4588, -4588, 4576, -4576, 4564, -4564 // 0x00000680
+, 4552, -4552, 4540, -4540, 4528, -4528, 4516, -4516, 4504, -4504, 4492, -4492, 4480, -4480, 4468, -4468 // 0x000006C0
+, 4456, -4456, 4444, -4444, 4432, -4432, 4420, -4420, 4408, -4408, 4396, -4396, 4384, -4384, 4372, -4372 // 0x00000700
+, 4360, -4360, 4348, -4348, 4336, -4336, 4324, -4324, 4312, -4312, 4300, -4300, 4288, -4288, 4276, -4276 // 0x00000740
+, 4264, -4264, 4256, -4256, 4244, -4244, 4232, -4232, 4220, -4220, 4208, -4208, 4196, -4196, 4184, -4184 // 0x00000780
+, 4176, -4176, 4164, -4164, 4152, -4152, 4140, -4140, 4128, -4128, 4120, -4120, 4108, -4108, 4096, -4096 // 0x000007C0
+, 4084, -4084, 4074, -4074, 4062, -4062, 4052, -4052, 4040, -4040, 4030, -4030, 4020, -4020, 4008, -4008 // 0x00000800
+, 3998, -3998, 3986, -3986, 3976, -3976, 3966, -3966, 3954, -3954, 3944, -3944, 3932, -3932, 3922, -3922 // 0x00000840
+, 3912, -3912, 3902, -3902, 3890, -3890, 3880, -3880, 3870, -3870, 3860, -3860, 3848, -3848, 3838, -3838 // 0x00000880
+, 3828, -3828, 3818, -3818, 3808, -3808, 3796, -3796, 3786, -3786, 3776, -3776, 3766, -3766, 3756, -3756 // 0x000008C0
+, 3746, -3746, 3736, -3736, 3726, -3726, 3716, -3716, 3706, -3706, 3696, -3696, 3686, -3686, 3676, -3676 // 0x00000900
+, 3666, -3666, 3656, -3656, 3646, -3646, 3636, -3636, 3626, -3626, 3616, -3616, 3606, -3606, 3596, -3596 // 0x00000940
+, 3588, -3588, 3578, -3578, 3568, -3568, 3558, -3558, 3548, -3548, 3538, -3538, 3530, -3530, 3520, -3520 // 0x00000980
+, 3510, -3510, 3500, -3500, 3492, -3492, 3482, -3482, 3472, -3472, 3464, -3464, 3454, -3454, 3444, -3444 // 0x000009C0
+, 3434, -3434, 3426, -3426, 3416, -3416, 3408, -3408, 3398, -3398, 3388, -3388, 3380, -3380, 3370, -3370 // 0x00000A00
+, 3362, -3362, 3352, -3352, 3344, -3344, 3334, -3334, 3326, -3326, 3316, -3316, 3308, -3308, 3298, -3298 // 0x00000A40
+, 3290, -3290, 3280, -3280, 3272, -3272, 3262, -3262, 3254, -3254, 3246, -3246, 3236, -3236, 3228, -3228 // 0x00000A80
+, 3218, -3218, 3210, -3210, 3202, -3202, 3192, -3192, 3184, -3184, 3176, -3176, 3168, -3168, 3158, -3158 // 0x00000AC0
+, 3150, -3150, 3142, -3142, 3132, -3132, 3124, -3124, 3116, -3116, 3108, -3108, 3100, -3100, 3090, -3090 // 0x00000B00
+, 3082, -3082, 3074, -3074, 3066, -3066, 3058, -3058, 3050, -3050, 3040, -3040, 3032, -3032, 3024, -3024 // 0x00000B40
+, 3016, -3016, 3008, -3008, 3000, -3000, 2992, -2992, 2984, -2984, 2976, -2976, 2968, -2968, 2960, -2960 // 0x00000B80
+, 2952, -2952, 2944, -2944, 2936, -2936, 2928, -2928, 2920, -2920, 2912, -2912, 2904, -2904, 2896, -2896 // 0x00000BC0
+, 2888, -2888, 2880, -2880, 2872, -2872, 2866, -2866, 2858, -2858, 2850, -2850, 2842, -2842, 2834, -2834 // 0x00000C00
+, 2826, -2826, 2818, -2818, 2812, -2812, 2804, -2804, 2796, -2796, 2788, -2788, 2782, -2782, 2774, -2774 // 0x00000C40
+, 2766, -2766, 2758, -2758, 2752, -2752, 2744, -2744, 2736, -2736, 2728, -2728, 2722, -2722, 2714, -2714 // 0x00000C80
+, 2706, -2706, 2700, -2700, 2692, -2692, 2684, -2684, 2678, -2678, 2670, -2670, 2664, -2664, 2656, -2656 // 0x00000CC0
+, 2648, -2648, 2642, -2642, 2634, -2634, 2628, -2628, 2620, -2620, 2614, -2614, 2606, -2606, 2600, -2600 // 0x00000D00
+, 2592, -2592, 2584, -2584, 2578, -2578, 2572, -2572, 2564, -2564, 2558, -2558, 2550, -2550, 2544, -2544 // 0x00000D40
+, 2536, -2536, 2530, -2530, 2522, -2522, 2516, -2516, 2510, -2510, 2502, -2502, 2496, -2496, 2488, -2488 // 0x00000D80
+, 2482, -2482, 2476, -2476, 2468, -2468, 2462, -2462, 2456, -2456, 2448, -2448, 2442, -2442, 2436, -2436 // 0x00000DC0
+, 2428, -2428, 2422, -2422, 2416, -2416, 2410, -2410, 2402, -2402, 2396, -2396, 2390, -2390, 2384, -2384 // 0x00000E00
+, 2376, -2376, 2370, -2370, 2364, -2364, 2358, -2358, 2352, -2352, 2344, -2344, 2338, -2338, 2332, -2332 // 0x00000E40
+, 2326, -2326, 2320, -2320, 2314, -2314, 2308, -2308, 2300, -2300, 2294, -2294, 2288, -2288, 2282, -2282 // 0x00000E80
+, 2276, -2276, 2270, -2270, 2264, -2264, 2258, -2258, 2252, -2252, 2246, -2246, 2240, -2240, 2234, -2234 // 0x00000EC0
+, 2228, -2228, 2222, -2222, 2216, -2216, 2210, -2210, 2204, -2204, 2198, -2198, 2192, -2192, 2186, -2186 // 0x00000F00
+, 2180, -2180, 2174, -2174, 2168, -2168, 2162, -2162, 2156, -2156, 2150, -2150, 2144, -2144, 2138, -2138 // 0x00000F40
+, 2132, -2132, 2128, -2128, 2122, -2122, 2116, -2116, 2110, -2110, 2104, -2104, 2098, -2098, 2092, -2092 // 0x00000F80
+, 2088, -2088, 2082, -2082, 2076, -2076, 2070, -2070, 2064, -2064, 2060, -2060, 2054, -2054, 2048, -2048 // 0x00000FC0
+, 2042, -2042, 2037, -2037, 2031, -2031, 2026, -2026, 2020, -2020, 2015, -2015, 2010, -2010, 2004, -2004 // 0x00001000
+, 1999, -1999, 1993, -1993, 1988, -1988, 1983, -1983, 1977, -1977, 1972, -1972, 1966, -1966, 1961, -1961 // 0x00001040
+, 1956, -1956, 1951, -1951, 1945, -1945, 1940, -1940, 1935, -1935, 1930, -1930, 1924, -1924, 1919, -1919 // 0x00001080
+, 1914, -1914, 1909, -1909, 1904, -1904, 1898, -1898, 1893, -1893, 1888, -1888, 1883, -1883, 1878, -1878 // 0x000010C0
+, 1873, -1873, 1868, -1868, 1863, -1863, 1858, -1858, 1853, -1853, 1848, -1848, 1843, -1843, 1838, -1838 // 0x00001100
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+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006080
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000060C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006100
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006140
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006180
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000061C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006200
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006240
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006280
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000062C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006300
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006340
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006380
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000063C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006400
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006440
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006480
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000064C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006500
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006540
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006580
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000065C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006600
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006640
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006680
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x000066C0
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006700
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006740
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1 // 0x00006780
+, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1, 1, -1};
diff --git a/MCUME_pico2/picogen/gwenesis/sound/ym2612.c b/MCUME_pico2/picogen/gwenesis/sound/ym2612.c
new file mode 100755
index 0000000..15aafc1
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/ym2612.c
@@ -0,0 +1,2427 @@
+#pragma GCC optimize("Ofast")
+#include <pico.h>
+/*
+**
+** software implementation of Yamaha FM sound generator (YM2612/YM3438)
+**
+** Original code (MAME fm.c)
+**
+** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
+** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
+**
+** Version 1.4 (final beta) 
+**
+** Additional code & fixes by Eke-Eke for Genesis Plus GX
+**
+** Huge thanks to Nemesis, most of those fixes came from his tests on Sega Genesis hardware
+** More informations at http://gendev.spritesmind.net/forum/viewtopic.php?t=386
+**
+**  TODO:
+**  - better documentation
+**  - BUSY flag emulation
+*/
+
+/*
+**  CHANGELOG:
+**
+** 2006~2011  Eke-Eke (Genesis Plus GX):
+**  - removed unused multichip support
+**  - added YM2612 Context external access functions
+**  - fixed LFO implementation:
+**      .added support for CH3 special mode: fixes various sound effects (birds in Warlock, bug sound in Aladdin...)
+**      .modified LFO behavior when switched off (AM/PM current level is held) and on (LFO step is reseted): fixes intro in Spider-Man & Venom : Separation Anxiety
+**      .improved LFO timing accuracy: now updated AFTER sample output, like EG/PG updates, and without any precision loss anymore.
+**  - improved internal timers emulation
+**  - adjusted lowest EG rates increment values
+**  - fixed Attack Rate not being updated in some specific cases (Batman & Robin intro)
+**  - fixed EG behavior when Attack Rate is maximal
+**  - fixed EG behavior when SL=0 (Mega Turrican tracks 03,09...) or/and Key ON occurs at minimal attenuation 
+**  - implemented EG output immediate changes on register writes
+**  - fixed YM2612 initial values (after the reset): fixes missing intro in B.O.B
+**  - implemented Detune overflow (Ariel, Comix Zone, Shaq Fu, Spiderman & many other games using GEMS sound engine)
+**  - implemented accurate CSM mode emulation
+**  - implemented accurate SSG-EG emulation (Asterix, Beavis&Butthead, Bubba'n Stix & many other games)
+**  - implemented accurate address/data ports behavior
+**  - added preliminar support for DAC precision
+**
+**
+** 03-08-2003 Jarek Burczynski:
+**  - fixed YM2608 initial values (after the reset)
+**  - fixed flag and irqmask handling (YM2608)
+**  - fixed BUFRDY flag handling (YM2608)
+**
+** 14-06-2003 Jarek Burczynski:
+**  - implemented all of the YM2608 status register flags
+**  - implemented support for external memory read/write via YM2608
+**  - implemented support for deltat memory limit register in YM2608 emulation
+**
+** 22-05-2003 Jarek Burczynski:
+**  - fixed LFO PM calculations (copy&paste bugfix)
+**
+** 08-05-2003 Jarek Burczynski:
+**  - fixed SSG support
+**
+** 22-04-2003 Jarek Burczynski:
+**  - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
+**
+** 15-04-2003 Jarek Burczynski:
+**  - added support for YM2608's register 0x110 - status mask
+**
+** 01-12-2002 Jarek Burczynski:
+**  - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
+**    The addressing patch used for early Neo-Geo games can be removed now.
+**
+** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
+**  - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
+**  - added emulation of YM2608 drums.
+**  - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
+**
+** 16-08-2002 Jarek Burczynski:
+**  - binary exact Envelope Generator (verified on real YM2203);
+**    identical to YM2151
+**  - corrected 'off by one' error in feedback calculations (when feedback is off)
+**  - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
+**
+** 18-12-2001 Jarek Burczynski:
+**  - added SSG-EG support (verified on real YM2203)
+**
+** 12-08-2001 Jarek Burczynski:
+**  - corrected sin_tab and tl_tab data (verified on real chip)
+**  - corrected feedback calculations (verified on real chip)
+**  - corrected phase generator calculations (verified on real chip)
+**  - corrected envelope generator calculations (verified on real chip)
+**  - corrected FM volume level (YM2610 and YM2610B).
+**  - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
+**    this was needed to calculate YM2610 FM channels output correctly.
+**    (Each FM channel is calculated as in other chips, but the output of the channel
+**    gets shifted right by one *before* sending to accumulator. That was impossible to do
+**    with previous implementation).
+**
+** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
+**  - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
+**
+** 11-06-2001 Jarek Burczynski:
+**  - corrected end of sample bug in ADPCMA_calc_cha().
+**    Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
+**
+** 08-12-98 hiro-shi:
+** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
+** move ROM limit check.(CALC_CH? -> 2610Write1/2)
+** test program (ADPCMB_TEST)
+** move ADPCM A/B end check.
+** ADPCMB repeat flag(no check)
+** change ADPCM volume rate (8->16) (32->48).
+**
+** 09-12-98 hiro-shi:
+** change ADPCM volume. (8->16, 48->64)
+** replace ym2610 ch0/3 (YM-2610B)
+** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
+** add ADPCM_SHIFT_MASK
+** change ADPCMA_DECODE_MIN/MAX.
+*/
+
+/************************************************************************/
+/*    comment of hiro-shi(Hiromitsu Shioya)                             */
+/*    YM2610(B) = OPN-B                                                 */
+/*    YM2610  : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch      */
+/*    YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch      */
+/************************************************************************/
+
+#pragma GCC optimize("Ofast")
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "ym2612.h"
+#include "../bus/gwenesis_bus.h"
+
+#if GENERATE_TABLES
+#include "ff.h"
+#endif
+
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t UINT8;
+typedef uint8_t uint8;
+typedef int32_t INT32;
+typedef int16_t INT16;
+typedef int8_t INT8;
+
+extern uint8_t snd_accurate;
+
+#define YM2612_DISABLE_LOGGING 1
+
+#if !YM2612_DISABLE_LOGGING
+#include <stdarg.h>
+void ym_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] ", frame_counter, scan_line, subs);
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define ym_log(...)
+#endif
+
+/* compiler dependence */
+#ifndef INLINE
+#define INLINE static __always_inline
+#endif
+
+/* globals */
+#define FREQ_SH     16    /* 16.16 fixed point (frequency calculations) */
+#define EG_SH       16    /* 16.16 fixed point (envelope generator timing) */
+#define LFO_SH      24    /*  8.24 fixed point (LFO calculations)       */
+#define TIMER_SH    16    /* 16.16 fixed point (timers calculations)    */
+
+#define FREQ_MASK    ((1<<FREQ_SH)-1)
+
+
+/* envelope generator */
+#define ENV_BITS    10
+#define ENV_LEN      (1<<ENV_BITS)
+#define ENV_STEP    (128.0/ENV_LEN)
+
+#define MAX_ATT_INDEX  (ENV_LEN-1) /* 1023 */
+#define MIN_ATT_INDEX  (0)      /* 0 */
+
+#define EG_ATT      4
+#define EG_DEC      3
+#define EG_SUS      2
+#define EG_REL      1
+#define EG_OFF      0
+
+/* operator unit */
+#define SIN_BITS    10
+#define SIN_LEN      (1<<SIN_BITS)
+#define SIN_MASK    (SIN_LEN-1)
+
+#define TL_RES_LEN    (256) /* 8 bits addressing (real chip) */
+
+#define TL_BITS    14 /* channel output */
+
+/*  TL_TAB_LEN is calculated as:
+*   13 - sinus amplitude bits     (Y axis)
+*   2  - sinus sign bit           (Y axis)
+*   TL_RES_LEN - sinus resolution (X axis)
+*/
+#define TL_TAB_LEN (13*2*TL_RES_LEN)
+#if GENERATE_TABLES
+static signed int tl_tab[TL_TAB_LEN];
+#else
+#include "tl_tab.h"
+#endif
+
+#define ENV_QUIET    (TL_TAB_LEN>>3)
+
+/* sin waveform table in 'decibel' scale */
+#if GENERATE_TABLES
+static unsigned int sin_tab[SIN_LEN];
+#else
+#include "sin_tab.h"
+#endif
+/* sustain level table (3dB per step) */
+/* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
+/* 1,    2,    4,    8,    16,   32,   64   (value)*/
+/* 0.75, 1.5,  3,    6,    12,   24,   48   (dB)*/
+
+/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
+/* attenuation value (10 bits) = (SL << 2) << 3 */
+#define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
+static const UINT32 sl_table[16] = {
+    SC(0),SC(1),SC(2),SC(3),SC(4),SC(5),SC(6),SC(7),
+    SC(8),SC(9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
+};
+#undef SC
+
+
+#define RATE_STEPS (8)
+static const UINT8 eg_inc[19 * RATE_STEPS] = {
+
+    /*cycle:0 1  2 3  4 5  6 7*/
+
+    /* 0 */ 0, 1, 0, 1, 0, 1, 0, 1, /* rates 00..11 0 (increment by 0 or 1) */
+    /* 1 */ 0, 1, 0, 1, 1, 1, 0, 1, /* rates 00..11 1 */
+    /* 2 */ 0, 1, 1, 1, 0, 1, 1, 1, /* rates 00..11 2 */
+    /* 3 */ 0, 1, 1, 1, 1, 1, 1, 1, /* rates 00..11 3 */
+
+    /* 4 */ 1, 1, 1, 1, 1, 1, 1, 1, /* rate 12 0 (increment by 1) */
+    /* 5 */ 1, 1, 1, 2, 1, 1, 1, 2, /* rate 12 1 */
+    /* 6 */ 1, 2, 1, 2, 1, 2, 1, 2, /* rate 12 2 */
+    /* 7 */ 1, 2, 2, 2, 1, 2, 2, 2, /* rate 12 3 */
+
+    /* 8 */ 2, 2, 2, 2, 2, 2, 2, 2, /* rate 13 0 (increment by 2) */
+    /* 9 */ 2, 2, 2, 4, 2, 2, 2, 4, /* rate 13 1 */
+    /*10 */ 2, 4, 2, 4, 2, 4, 2, 4, /* rate 13 2 */
+    /*11 */ 2, 4, 4, 4, 2, 4, 4, 4, /* rate 13 3 */
+
+    /*12 */ 4, 4, 4, 4, 4, 4, 4, 4, /* rate 14 0 (increment by 4) */
+    /*13 */ 4, 4, 4, 8, 4, 4, 4, 8, /* rate 14 1 */
+    /*14 */ 4, 8, 4, 8, 4, 8, 4, 8, /* rate 14 2 */
+    /*15 */ 4, 8, 8, 8, 4, 8, 8, 8, /* rate 14 3 */
+
+    /*16 */ 8, 8, 8, 8, 8, 8, 8, 8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
+    /*17 */ 16, 16, 16, 16, 16, 16, 16, 16, /* rates 15 2, 15 3 for attack */
+    /*18 */ 0, 0, 0, 0, 0, 0, 0, 0, /* infinity rates for attack and decay(s) */
+};
+
+
+#define O(a) (a*RATE_STEPS)
+
+/*note that there is no O(17) in this table - it's directly in the code */
+static const UINT8 eg_rate_select[32 + 64 + 32] = {
+    /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
+    /* 32 infinite time rates (same as Rate 0) */
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+    O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
+
+    /* rates 00-11 */
+    /*
+    O( 0),O( 1),O( 2),O( 3),
+    O( 0),O( 1),O( 2),O( 3),
+    */
+    O(18),O(18),O(0),O(0),
+    O(0),O(0),O(2),O(2), /* Nemesis's tests */
+
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+    O(0),O(1),O(2),O(3),
+
+    /* rate 12 */
+    O(4),O(5),O(6),O(7),
+
+    /* rate 13 */
+    O(8),O(9),O(10),O(11),
+
+    /* rate 14 */
+    O(12),O(13),O(14),O(15),
+
+    /* rate 15 */
+    O(16),O(16),O(16),O(16),
+
+    /* 32 dummy rates (same as 15 3) */
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
+    O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
+
+};
+#undef O
+
+/*rate  0,    1,    2,   3,   4,   5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15*/
+/*shift 11,   10,   9,   8,   7,   6,  5,  4,  3,  2, 1,  0,  0,  0,  0,  0 */
+/*mask  2047, 1023, 511, 255, 127, 63, 31, 15, 7,  3, 1,  0,  0,  0,  0,  0 */
+
+#define O(a) (a*1)
+static const UINT8 eg_rate_shift[32 + 64 + 32] = {
+    /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
+    /* 32 infinite time rates */
+    /* O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), */
+
+    /* fixed (should be the same as rate 0, even if it makes no difference since increment value is 0 for these rates) */
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+    O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
+
+    /* rates 00-11 */
+    O(11),O(11),O(11),O(11),
+    O(10),O(10),O(10),O(10),
+    O(9),O(9),O(9),O(9),
+    O(8),O(8),O(8),O(8),
+    O(7),O(7),O(7),O(7),
+    O(6),O(6),O(6),O(6),
+    O(5),O(5),O(5),O(5),
+    O(4),O(4),O(4),O(4),
+    O(3),O(3),O(3),O(3),
+    O(2),O(2),O(2),O(2),
+    O(1),O(1),O(1),O(1),
+    O(0),O(0),O(0),O(0),
+
+    /* rate 12 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 13 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 14 */
+    O(0),O(0),O(0),O(0),
+
+    /* rate 15 */
+    O(0),O(0),O(0),O(0),
+
+    /* 32 dummy rates (same as 15 3) */
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
+    O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0)
+
+};
+#undef O
+
+static const UINT8 dt_tab[4 * 32] = {
+    /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
+    /* FD=0 */
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    /* FD=1 */
+    0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
+    2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
+    /* FD=2 */
+    1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
+    5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 16, 16, 16, 16,
+    /* FD=3 */
+    2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
+    8, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20, 22, 22, 22, 22
+};
+
+
+/* OPN key frequency number -> key code follow table */
+/* fnum higher 4bit -> keycode lower 2bit */
+static const UINT8 opn_fktable[16] = { 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 3, 3, 3, 3, 3, 3 };
+
+
+/* 8 LFO speed parameters */
+/* each value represents number of samples that one LFO level will last for */
+static const UINT32 lfo_samples_per_step[8] = { 108, 77, 71, 67, 62, 44, 8, 5 };
+
+
+/*There are 4 different LFO AM depths available, they are:
+  0 dB, 1.4 dB, 5.9 dB, 11.8 dB
+  Here is how it is generated (in EG steps):
+
+  11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
+   5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
+   1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
+
+  (1.4 dB is loosing precision as you can see)
+
+  It's implemented as generator from 0..126 with step 2 then a shift
+  right N times, where N is:
+    8 for 0 dB
+    3 for 1.4 dB
+    1 for 5.9 dB
+    0 for 11.8 dB
+*/
+static const UINT8 lfo_ams_depth_shift[4] = { 8, 3, 1, 0 };
+
+
+/*There are 8 different LFO PM depths available, they are:
+  0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
+
+  Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
+  (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
+
+  Here we store only first quarter (positive one) of full waveform.
+  Full table (lfo_pm_table) containing all 128 waveforms is build
+  at run (init) time.
+
+  One value in table below represents 4 (four) basic LFO steps
+  (1 PM step = 4 AM steps).
+
+  For example:
+   at LFO SPEED=0 (which is 108 samples per basic LFO step)
+   one value from "lfo_pm_output" table lasts for 432 consecutive
+   samples (4*108=432) and one full LFO waveform cycle lasts for 13824
+   samples (32*432=13824; 32 because we store only a quarter of whole
+            waveform in the table below)
+*/
+static const UINT8 lfo_pm_output[7 * 8][8] = {
+    /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
+    /* FNUM BIT 4: 000 0001xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 6 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 7 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+
+    /* FNUM BIT 5: 000 0010xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 6 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 7 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+
+    /* FNUM BIT 6: 000 0100xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 4 */ { 0, 0, 0, 0, 0, 0, 0, 1 },
+    /* DEPTH 5 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 6 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+    /* DEPTH 7 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+
+    /* FNUM BIT 7: 000 1000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 2 */ { 0, 0, 0, 0, 0, 0, 1, 1 },
+    /* DEPTH 3 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 4 */ { 0, 0, 0, 1, 1, 1, 1, 2 },
+    /* DEPTH 5 */ { 0, 0, 1, 1, 2, 2, 2, 3 },
+    /* DEPTH 6 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+    /* DEPTH 7 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+
+    /* FNUM BIT 8: 001 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 1, 1, 1, 1 },
+    /* DEPTH 2 */ { 0, 0, 0, 1, 1, 1, 2, 2 },
+    /* DEPTH 3 */ { 0, 0, 1, 1, 2, 2, 3, 3 },
+    /* DEPTH 4 */ { 0, 0, 1, 2, 2, 2, 3, 4 },
+    /* DEPTH 5 */ { 0, 0, 2, 3, 4, 4, 5, 6 },
+    /* DEPTH 6 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+    /* DEPTH 7 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+
+    /* FNUM BIT 9: 010 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 2, 2, 2, 2 },
+    /* DEPTH 2 */ { 0, 0, 0, 2, 2, 2, 4, 4 },
+    /* DEPTH 3 */ { 0, 0, 2, 2, 4, 4, 6, 6 },
+    /* DEPTH 4 */ { 0, 0, 2, 4, 4, 4, 6, 8 },
+    /* DEPTH 5 */ { 0, 0, 4, 6, 8, 8, 0xa, 0xc },
+    /* DEPTH 6 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+    /* DEPTH 7 */ { 0, 0, 0x10, 0x18, 0x20, 0x20, 0x28, 0x30 },
+
+    /* FNUM BIT10: 100 0000xxxx */
+    /* DEPTH 0 */ { 0, 0, 0, 0, 0, 0, 0, 0 },
+    /* DEPTH 1 */ { 0, 0, 0, 0, 4, 4, 4, 4 },
+    /* DEPTH 2 */ { 0, 0, 0, 4, 4, 4, 8, 8 },
+    /* DEPTH 3 */ { 0, 0, 4, 4, 8, 8, 0xc, 0xc },
+    /* DEPTH 4 */ { 0, 0, 4, 8, 8, 8, 0xc, 0x10 },
+    /* DEPTH 5 */ { 0, 0, 8, 0xc, 0x10, 0x10, 0x14, 0x18 },
+    /* DEPTH 6 */ { 0, 0, 0x10, 0x18, 0x20, 0x20, 0x28, 0x30 },
+    /* DEPTH 7 */ { 0, 0, 0x20, 0x30, 0x40, 0x40, 0x50, 0x60 },
+
+};
+
+/* all 128 LFO PM waveforms */
+#if GENERATE_TABLES
+static UINT8 lfo_pm_table[128*8*16];  /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
+#else
+#include "lfo_pm_table.h"
+#endif
+/* register number to channel number , slot offset */
+#define OPN_CHAN(N) (N&3)
+#define OPN_SLOT(N) ((N>>2)&3)
+
+/* slot number */
+#define SLOT1 0
+#define SLOT2 2
+#define SLOT3 1
+#define SLOT4 3
+
+/* struct describing a single operator (SLOT) */
+typedef struct {
+    INT32* DT; /* detune          :dt_tab[DT]      */
+    UINT8 KSR; /* key scale rate  :3-KSR           */
+    UINT32 ar; /* attack rate                      */
+    UINT32 d1r; /* decay rate                       */
+    UINT32 d2r; /* sustain rate                     */
+    UINT32 rr; /* release rate                     */
+    UINT8 ksr; /* key scale rate  :kcode>>(3-KSR)  */
+    UINT32 mul; /* multiple        :ML_TABLE[ML]    */
+
+    /* Phase Generator */
+    UINT32 phase; /* phase counter */
+    INT32 Incr; /* phase step */
+
+    /* Envelope Generator */
+    UINT8 state; /* phase type */
+    UINT32 tl; /* total level: TL << 3 */
+    INT32 volume; /* envelope counter */
+    UINT32 sl; /* sustain level:sl_table[SL] */
+    UINT32 vol_out; /* current output from EG circuit (without AM from LFO) */
+
+    UINT8 eg_sh_ar; /*  (attack state)  */
+    UINT8 eg_sel_ar; /*  (attack state)  */
+    UINT8 eg_sh_d1r; /*  (decay state)   */
+    UINT8 eg_sel_d1r; /*  (decay state)   */
+    UINT8 eg_sh_d2r; /*  (sustain state) */
+    UINT8 eg_sel_d2r; /*  (sustain state) */
+    UINT8 eg_sh_rr; /*  (release state) */
+    UINT8 eg_sel_rr; /*  (release state) */
+
+    UINT8 ssg; /* SSG-EG waveform  */
+    UINT8 ssgn; /* SSG-EG negated output  */
+
+    UINT8 key; /* 0=last key was KEY OFF, 1=KEY ON */
+
+    /* LFO */
+    UINT32 AMmask; /* AM enable flag */
+} FM_SLOT;
+
+typedef struct {
+    FM_SLOT SLOT[4]; /* four SLOTs (operators) */
+
+    UINT8 ALGO; /* algorithm */
+    UINT8 FB; /* feedback shift */
+    INT32 op1_out[2]; /* op1 output for feedback */
+
+    INT32* connect1; /* SLOT1 output pointer */
+    INT32* connect3; /* SLOT3 output pointer */
+    INT32* connect2; /* SLOT2 output pointer */
+    INT32* connect4; /* SLOT4 output pointer */
+
+    INT32* mem_connect; /* where to put the delayed sample (MEM) */
+    INT32 mem_value; /* delayed sample (MEM) value */
+
+    INT32 pms; /* channel PMS */
+    UINT8 ams; /* channel AMS */
+
+    UINT32 fc; /* fnum,blk:adjusted to sample rate */
+    UINT8 kcode; /* key code */
+    UINT32 block_fnum;
+    /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+} FM_CH;
+
+#if GENERATE_TABLES
+int ym2612_OPN_ST_dt_tab[8][32];  /* DeTune table         */
+#else
+#include "ym2612_OPN_ST_dt_tab.h"
+#endif
+
+typedef struct {
+    double clock; /* master clock  (Hz)   */
+    UINT32 rate; /* sampling rate (Hz)   */
+    UINT16 address; /* address register     */
+    UINT8 status; /* status flag          */
+    UINT32 mode; /* mode  CSM / 3SLOT    */
+    UINT8 fn_h; /* freq latch           */
+    INT32 TimerBase; /* Timer base time      */
+    INT32 TA; /* timer a value        */
+    INT32 TAL; /* timer a base          */
+    INT32 TAC; /* timer a counter      */
+    INT32 TB; /* timer b value        */
+    INT32 TBL; /* timer b base          */
+    INT32 TBC; /* timer b counter      */
+} FM_ST;
+
+
+/***********************************************************/
+/* OPN unit                                                */
+/***********************************************************/
+
+/* OPN 3slot struct */
+typedef struct {
+    UINT32 fc[3]; /* fnum3,blk3: calculated */
+    UINT8 fn_h; /* freq3 latch */
+    UINT8 kcode[3]; /* key code */
+    UINT32 block_fnum[3];
+    /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+    UINT8 key_csm; /* CSM mode Key-ON flag */
+} FM_3SLOT;
+
+#if GENERATE_TABLES
+static unsigned int fn_table[4096];
+#else
+#include "fn_table.h"
+#endif
+
+/* OPN/A/B common state */
+typedef struct {
+    FM_ST ST; /* general state */
+    FM_3SLOT SL3; /* 3 slot mode state */
+    unsigned int pan[6 * 2]; /* fm channels output masks (0xffffffff = enable) */
+
+    UINT32 eg_cnt; /* global envelope generator counter */
+    UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/144/3 */
+    UINT32 eg_timer_add; /* step of eg_timer */
+    UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 3 samples (on real chip) */
+
+    /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
+       but LFO works with one more bit of a precision so we really need 4096 elements */
+#if !GENERATE_TABLES
+    const
+#endif
+    unsigned int* pfn_table; /* fnumber->increment counter */
+    UINT32 fn_max; /* max increment (required for calculating phase overflow) */
+
+    /* LFO */
+    UINT8 lfo_cnt; /* current LFO phase (out of 128) */
+    UINT32 lfo_timer; /* current LFO phase runs at LFO frequency */
+    UINT32 lfo_timer_add; /* step of lfo_timer */
+    UINT32 lfo_timer_overflow; /* LFO timer overflows every N samples (depends on LFO frequency) */
+    UINT32 LFO_AM; /* current LFO AM step */
+    UINT32 LFO_PM; /* current LFO PM step */
+} FM_OPN;
+
+/***********************************************************/
+/* YM2612 chip                                                */
+/***********************************************************/
+typedef struct {
+    FM_CH CH[6]; /* channel state */
+    UINT8 dacen; /* DAC mode  */
+    INT32 dacout; /* DAC output */
+    FM_OPN OPN; /* OPN state */
+    UINT32 divisor; /* sample rate divsor in system clock */
+} YM2612;
+
+/* emulated chip */
+static YM2612 ym2612;
+
+/* current chip state */
+static INT32 m2, c1, c2; /* Phase Modulation input for operators 2,3,4 */
+static INT32 mem; /* one sample delay memory */
+static INT32 out_fm[8]; /* outputs of working channels */
+static UINT32 bitmask; /* working channels output bitmasking (DAC quantization) */
+
+/* mirror of all OPN registers */
+static uint8_t OPNREGS[512];
+
+/* limiter */
+#define Limit(val, max,min) { \
+  if ( val > max )      val = max; \
+  else if ( val < min ) val = min; \
+}
+
+INLINE void FM_KEYON(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (!SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        /* restart Phase Generator */
+        SLOT->phase = 0;
+
+        /* reset SSG-EG inversion flag */
+        SLOT->ssgn = 0;
+
+        if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+            SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
+        }
+        else {
+            /* force attenuation level to 0 */
+            SLOT->volume = MIN_ATT_INDEX;
+
+            /* directly switch to Decay (or Sustain) */
+            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+        }
+
+        /* recalculate EG output */
+        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+        else
+            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+    }
+
+    SLOT->key = 1;
+}
+
+INLINE void FM_KEYOFF(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        if (SLOT->state > EG_REL) {
+            SLOT->state = EG_REL; /* phase -> Release */
+
+            /* SSG-EG specific update */
+            if (SLOT->ssg & 0x08) {
+                /* convert EG attenuation level */
+                if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                    SLOT->volume = (0x200 - SLOT->volume);
+
+                /* force EG attenuation level */
+                if (SLOT->volume >= 0x200) {
+                    SLOT->volume = MAX_ATT_INDEX;
+                    SLOT->state = EG_OFF;
+                }
+
+                /* recalculate EG output */
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+        }
+    }
+
+    SLOT->key = 0;
+}
+
+INLINE void FM_KEYON_CSM(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+
+    if (!SLOT->key && !ym2612.OPN.SL3.key_csm) {
+        /* restart Phase Generator */
+        SLOT->phase = 0;
+
+        /* reset SSG-EG inversion flag */
+        SLOT->ssgn = 0;
+
+        if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+            SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
+        }
+        else {
+            /* force attenuation level to 0 */
+            SLOT->volume = MIN_ATT_INDEX;
+
+            /* directly switch to Decay (or Sustain) */
+            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+        }
+
+        /* recalculate EG output */
+        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+        else
+            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+    }
+}
+
+INLINE void FM_KEYOFF_CSM(FM_CH* CH, int s) {
+    FM_SLOT* SLOT = &CH->SLOT[s];
+    if (!SLOT->key) {
+        if (SLOT->state > EG_REL) {
+            SLOT->state = EG_REL; /* phase -> Release */
+
+            /* SSG-EG specific update */
+            if (SLOT->ssg & 0x08) {
+                /* convert EG attenuation level */
+                if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                    SLOT->volume = (0x200 - SLOT->volume);
+
+                /* force EG attenuation level */
+                if (SLOT->volume >= 0x200) {
+                    SLOT->volume = MAX_ATT_INDEX;
+                    SLOT->state = EG_OFF;
+                }
+
+                /* recalculate EG output */
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+        }
+    }
+}
+
+/* CSM Key Controll */
+INLINE void CSMKeyControll(FM_CH* CH) {
+    /* all key ON (verified by Nemesis on real hardware) */
+    FM_KEYON_CSM(CH,SLOT1);
+    FM_KEYON_CSM(CH,SLOT2);
+    FM_KEYON_CSM(CH,SLOT3);
+    FM_KEYON_CSM(CH,SLOT4);
+    ym2612.OPN.SL3.key_csm = 1;
+}
+
+INLINE void INTERNAL_TIMER_A() {
+    if (ym2612.OPN.ST.mode & 0x01) {
+        if ((ym2612.OPN.ST.TAC -= ym2612.OPN.ST.TimerBase) <= 0) {
+            /* set status (if enabled) */
+            if (ym2612.OPN.ST.mode & 0x04)
+                ym2612.OPN.ST.status |= 0x01;
+
+            /* reload the counter */
+            if (ym2612.OPN.ST.TAL)
+                ym2612.OPN.ST.TAC += ym2612.OPN.ST.TAL;
+            else
+                ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
+
+            /* CSM mode auto key on */
+            if ((ym2612.OPN.ST.mode & 0xC0) == 0x80)
+                CSMKeyControll(&ym2612.CH[2]);
+        }
+    }
+}
+
+INLINE void INTERNAL_TIMER_B(int step) {
+    if (ym2612.OPN.ST.mode & 0x02) {
+        if ((ym2612.OPN.ST.TBC -= (__mul_instruction(ym2612.OPN.ST.TimerBase, step))) <= 0) {
+            /* set status (if enabled) */
+            if (ym2612.OPN.ST.mode & 0x08)
+                ym2612.OPN.ST.status |= 0x02;
+
+            /* reload the counter */
+            if (ym2612.OPN.ST.TBL)
+                ym2612.OPN.ST.TBC += ym2612.OPN.ST.TBL;
+            else
+                ym2612.OPN.ST.TBC = ym2612.OPN.ST.TBL;
+        }
+    }
+}
+
+/* OPN Mode Register Write */
+INLINE void set_timers(int v) {
+    /* b7 = CSM MODE */
+    /* b6 = 3 slot mode */
+    /* b5 = reset b */
+    /* b4 = reset a */
+    /* b3 = timer enable b */
+    /* b2 = timer enable a */
+    /* b1 = load b */
+    /* b0 = load a */
+
+    if ((ym2612.OPN.ST.mode ^ v) & 0xC0) {
+        /* phase increment need to be recalculated */
+        ym2612.CH[2].SLOT[SLOT1].Incr = -1;
+
+        /* CSM mode disabled and CSM key ON active*/
+        if (((v & 0xC0) != 0x80) && ym2612.OPN.SL3.key_csm) {
+            /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
+            ym2612.OPN.SL3.key_csm = 0;
+        }
+    }
+
+    /* reload Timers */
+    if ((v & 1) && !(ym2612.OPN.ST.mode & 1))
+        ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
+    if ((v & 2) && !(ym2612.OPN.ST.mode & 2))
+        ym2612.OPN.ST.TBC = ym2612.OPN.ST.TBL;
+
+    /* reset Timers flags */
+    ym2612.OPN.ST.status &= (~v >> 4);
+
+    ym2612.OPN.ST.mode = v;
+}
+
+/* set algorithm connection */
+INLINE void setup_connection(FM_CH* CH, int ch) {
+    INT32* carrier = &out_fm[ch];
+
+    INT32** om1 = &CH->connect1;
+    INT32** om2 = &CH->connect3;
+    INT32** oc1 = &CH->connect2;
+
+    INT32** memc = &CH->mem_connect;
+
+    switch (CH->ALGO) {
+        case 0:
+            /* M1---C1---MEM---M2---C2---OUT */
+            *om1 = &c1;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 1:
+            /* M1------+-MEM---M2---C2---OUT */
+            /*      C1-+                     */
+            *om1 = &mem;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 2:
+            /* M1-----------------+-C2---OUT */
+            /*      C1---MEM---M2-+          */
+            *om1 = &c2;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &m2;
+            break;
+        case 3:
+            /* M1---C1---MEM------+-C2---OUT */
+            /*                 M2-+          */
+            *om1 = &c1;
+            *oc1 = &mem;
+            *om2 = &c2;
+            *memc = &c2;
+            break;
+        case 4:
+            /* M1---C1-+-OUT */
+            /* M2---C2-+     */
+            /* MEM: not used */
+            *om1 = &c1;
+            *oc1 = carrier;
+            *om2 = &c2;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+        case 5:
+            /*    +----C1----+     */
+            /* M1-+-MEM---M2-+-OUT */
+            /*    +----C2----+     */
+            *om1 = 0; /* special mark */
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &m2;
+            break;
+        case 6:
+            /* M1---C1-+     */
+            /*      M2-+-OUT */
+            /*      C2-+     */
+            /* MEM: not used */
+            *om1 = &c1;
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+        case 7:
+            /* M1-+     */
+            /* C1-+-OUT */
+            /* M2-+     */
+            /* C2-+     */
+            /* MEM: not used*/
+            *om1 = carrier;
+            *oc1 = carrier;
+            *om2 = carrier;
+            *memc = &mem; /* store it anywhere where it will not be used */
+            break;
+    }
+
+    CH->connect4 = carrier;
+}
+
+/* set detune & multiple */
+INLINE void set_det_mul(FM_CH* CH, FM_SLOT* SLOT, int v) {
+    SLOT->mul = (v & 0x0f) ? __fast_mul(v & 0x0f, 2) : 1;
+    SLOT->DT = (INT32 *)ym2612_OPN_ST_dt_tab[(v >> 4) & 7];
+    CH->SLOT[SLOT1].Incr = -1;
+}
+
+/* set total level */
+INLINE void set_tl(FM_SLOT* SLOT, int v) {
+    SLOT->tl = (v & 0x7f) << (ENV_BITS - 7); /* 7bit TL */
+
+    /* recalculate EG output */
+    if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)) && (SLOT->state > EG_REL))
+        SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+    else
+        SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+}
+
+/* set attack rate & key scale  */
+INLINE void set_ar_ksr(FM_CH* CH, FM_SLOT* SLOT, int v) {
+    UINT8 old_KSR = SLOT->KSR;
+
+    SLOT->ar = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->KSR = 3 - (v >> 6);
+    if (SLOT->KSR != old_KSR) {
+        CH->SLOT[SLOT1].Incr = -1;
+    }
+
+    /* Even if it seems unnecessary to do it here, it could happen that KSR and KC  */
+    /* are modified but the resulted SLOT->ksr value (kc >> SLOT->KSR) remains unchanged. */
+    /* In such case, Attack Rate would not be recalculated by "refresh_fc_eg_slot". */
+    /* This actually fixes the intro of "The Adventures of Batman & Robin" (Eke-Eke)         */
+    if ((SLOT->ar + SLOT->ksr) < (32 + 62)) {
+        SLOT->eg_sh_ar = eg_rate_shift[SLOT->ar + SLOT->ksr];
+        SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr];
+    }
+    else {
+        /* verified by Nemesis on real hardware (Attack phase is blocked) */
+        SLOT->eg_sh_ar = 0;
+        SLOT->eg_sel_ar = 18 * RATE_STEPS;
+    }
+}
+
+/* set decay rate */
+INLINE void set_dr(FM_SLOT* SLOT, int v) {
+    SLOT->d1r = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->eg_sh_d1r = eg_rate_shift[SLOT->d1r + SLOT->ksr];
+    SLOT->eg_sel_d1r = eg_rate_select[SLOT->d1r + SLOT->ksr];
+}
+
+/* set sustain rate */
+INLINE void set_sr(FM_SLOT* SLOT, int v) {
+    SLOT->d2r = (v & 0x1f) ? 32 + ((v & 0x1f) << 1) : 0;
+
+    SLOT->eg_sh_d2r = eg_rate_shift[SLOT->d2r + SLOT->ksr];
+    SLOT->eg_sel_d2r = eg_rate_select[SLOT->d2r + SLOT->ksr];
+}
+
+/* set release rate */
+INLINE void set_sl_rr(FM_SLOT* SLOT, int v) {
+    SLOT->sl = sl_table[v >> 4];
+
+    /* check EG state changes */
+    if ((SLOT->state == EG_DEC) && (SLOT->volume >= (INT32)(SLOT->sl)))
+        SLOT->state = EG_SUS;
+
+    SLOT->rr = 34 + ((v & 0x0f) << 2);
+
+    SLOT->eg_sh_rr = eg_rate_shift[SLOT->rr + SLOT->ksr];
+    SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
+}
+
+/* advance LFO to next sample */
+INLINE void advance_lfo() {
+    if (ym2612.OPN.lfo_timer_overflow) /* LFO enabled ? */
+    {
+        /* increment LFO timer */
+        ym2612.OPN.lfo_timer += ym2612.OPN.lfo_timer_add;
+
+        /* when LFO is enabled, one level will last for 108, 77, 71, 67, 62, 44, 8 or 5 samples */
+        while (ym2612.OPN.lfo_timer >= ym2612.OPN.lfo_timer_overflow) {
+            ym2612.OPN.lfo_timer -= ym2612.OPN.lfo_timer_overflow;
+
+            /* There are 128 LFO steps */
+            ym2612.OPN.lfo_cnt = (ym2612.OPN.lfo_cnt + 1) & 127;
+
+            /* triangle */
+            /* AM: 0 to 126 step +2, 126 to 0 step -2 */
+            if (ym2612.OPN.lfo_cnt < 64)
+                ym2612.OPN.LFO_AM = __fast_mul(ym2612.OPN.lfo_cnt, 2);
+            else
+                ym2612.OPN.LFO_AM = 126 - __fast_mul((ym2612.OPN.lfo_cnt&63), 2);
+
+            /* PM works with 4 times slower clock */
+            ym2612.OPN.LFO_PM = ym2612.OPN.lfo_cnt >> 2;
+        }
+    }
+}
+
+
+INLINE void advance_eg_channels(void) {
+    unsigned int eg_cnt = ym2612.OPN.eg_cnt;
+    unsigned int i = 0;
+    unsigned int j;
+    FM_SLOT* SLOT;
+
+    do {
+        SLOT = &ym2612.CH[i].SLOT[SLOT1];
+        j = 4; /* four operators per channel */
+        do {
+            switch (SLOT->state) {
+                case EG_ATT: /* attack phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_ar) - 1))) {
+                        /* update attenuation level */
+                        SLOT->volume += (~SLOT->volume * (eg_inc[SLOT->eg_sel_ar + ((eg_cnt >> SLOT->eg_sh_ar) & 7)]))
+                                >> 4;
+
+                        /* check phase transition*/
+                        if (SLOT->volume <= MIN_ATT_INDEX) {
+                            SLOT->volume = MIN_ATT_INDEX;
+                            SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC; /* special case where SL=0 */
+                        }
+
+                        /* recalculate EG output */
+                        if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04))) /* SSG-EG Output Inversion */
+                            SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                        else
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                    }
+                    break;
+                }
+
+                case EG_DEC: /* decay phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_d1r) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200) {
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_d1r + ((eg_cnt>>SLOT->eg_sh_d1r)&7)], 4);
+
+                                /* recalculate EG output */
+                                if (SLOT->ssgn ^ (SLOT->ssg & 0x04)) /* SSG-EG Output Inversion */
+                                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                                else
+                                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((eg_cnt >> SLOT->eg_sh_d1r) & 7)];
+
+                            /* recalculate EG output */
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                        }
+
+                        /* check phase transition*/
+                        if (SLOT->volume >= (INT32)(SLOT->sl))
+                            SLOT->state = EG_SUS;
+                    }
+                    break;
+                }
+
+                case EG_SUS: /* sustain phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_d2r) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200) {
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_d2r + ((eg_cnt>>SLOT->eg_sh_d2r)&7)], 4);
+
+                                /* recalculate EG output */
+                                if (SLOT->ssgn ^ (SLOT->ssg & 0x04)) /* SSG-EG Output Inversion */
+                                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                                else
+                                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_d2r + ((eg_cnt >> SLOT->eg_sh_d2r) & 7)];
+
+                            /* check phase transition*/
+                            if (SLOT->volume >= MAX_ATT_INDEX)
+                                SLOT->volume = MAX_ATT_INDEX;
+                            /* do not change SLOT->state (verified on real chip) */
+
+                            /* recalculate EG output */
+                            SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                        }
+                    }
+                    break;
+                }
+
+                case EG_REL: /* release phase */
+                {
+                    if (!(eg_cnt & ((1 << SLOT->eg_sh_rr) - 1))) {
+                        /* SSG EG type */
+                        if (SLOT->ssg & 0x08) {
+                            /* update attenuation level */
+                            if (SLOT->volume < 0x200)
+                                SLOT->volume += __fast_mul(eg_inc[SLOT->eg_sel_rr + ((eg_cnt>>SLOT->eg_sh_rr)&7)], 4);
+
+                            /* check phase transition */
+                            if (SLOT->volume >= 0x200) {
+                                SLOT->volume = MAX_ATT_INDEX;
+                                SLOT->state = EG_OFF;
+                            }
+                        }
+                        else {
+                            /* update attenuation level */
+                            SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((eg_cnt >> SLOT->eg_sh_rr) & 7)];
+
+                            /* check phase transition*/
+                            if (SLOT->volume >= MAX_ATT_INDEX) {
+                                SLOT->volume = MAX_ATT_INDEX;
+                                SLOT->state = EG_OFF;
+                            }
+                        }
+
+                        /* recalculate EG output */
+                        SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+                    }
+                    break;
+                }
+            }
+            SLOT++;
+            j--;
+        }
+        while (j);
+        i++;
+    }
+    while (i < 6); /* 6 channels */
+}
+
+/* SSG-EG update process */
+/* The behavior is based upon Nemesis tests on real hardware */
+/* This is actually executed before each samples */
+INLINE void update_ssg_eg_channel(FM_SLOT* SLOT) {
+    unsigned int i = 4; /* four operators per channel */
+
+    do {
+        /* detect SSG-EG transition */
+        /* this is not required during release phase as the attenuation has been forced to MAX and output invert flag is not used */
+        /* if an Attack Phase is programmed, inversion can occur on each sample */
+        if ((SLOT->ssg & 0x08) && (SLOT->volume >= 0x200) && (SLOT->state > EG_REL)) {
+            if (SLOT->ssg & 0x01) /* bit 0 = hold SSG-EG */
+            {
+                /* set inversion flag */
+                if (SLOT->ssg & 0x02)
+                    SLOT->ssgn = 4;
+
+                /* force attenuation level during decay phases */
+                if ((SLOT->state != EG_ATT) && !(SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+                    SLOT->volume = MAX_ATT_INDEX;
+            }
+            else /* loop SSG-EG */
+            {
+                /* toggle output inversion flag or reset Phase Generator */
+                if (SLOT->ssg & 0x02)
+                    SLOT->ssgn ^= 4;
+                else
+                    SLOT->phase = 0;
+
+                /* same as Key ON */
+                if (SLOT->state != EG_ATT) {
+                    if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/) {
+                        SLOT->state = (SLOT->volume <= MIN_ATT_INDEX)
+                                          ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC)
+                                          : EG_ATT;
+                    }
+                    else {
+                        /* Attack Rate is maximal: directly switch to Decay or Substain */
+                        SLOT->volume = MIN_ATT_INDEX;
+                        SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
+                    }
+                }
+            }
+
+            /* recalculate EG output */
+            if (SLOT->ssgn ^ (SLOT->ssg & 0x04))
+                SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+            else
+                SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+        }
+
+        /* next slot */
+        SLOT++;
+        i--;
+    }
+    while (i);
+}
+
+INLINE void update_phase_lfo_slot(FM_SLOT* SLOT, INT32 pms, UINT32 block_fnum) {
+    INT32 lfo_fn_table_index_offset = lfo_pm_table[
+        (((block_fnum & 0x7f0) >> 4) << 7) + pms + (ym2612.OPN.LFO_PM & 0xF)];
+    if (ym2612.OPN.LFO_PM & 0x10) lfo_fn_table_index_offset = -lfo_fn_table_index_offset;
+
+    if (lfo_fn_table_index_offset) /* LFO phase modulation active */
+    {
+        UINT8 blk;
+        int kc, fc;
+
+        block_fnum = __fast_mul(block_fnum, 2) + lfo_fn_table_index_offset;
+        blk = (block_fnum & 0x7000) >> 12;
+        block_fnum = block_fnum & 0xfff;
+
+        /* keyscale code */
+        kc = (blk << 2) | opn_fktable[block_fnum >> 8];
+
+        /* (frequency) phase increment counter */
+        fc = (ym2612.OPN.pfn_table[block_fnum] >> (7 - blk)) + SLOT->DT[kc];
+
+        /* (frequency) phase overflow (credits to Nemesis) */
+        if (fc < 0) fc += ym2612.OPN.fn_max;
+
+        /* update phase */
+        SLOT->phase += (fc * SLOT->mul) >> 1;
+    }
+    else /* LFO phase modulation  = zero */
+    {
+        SLOT->phase += SLOT->Incr;
+    }
+}
+
+INLINE void update_phase_lfo_channel(FM_CH* CH) {
+    UINT32 block_fnum = CH->block_fnum;
+
+    INT32 lfo_fn_table_index_offset = lfo_pm_table[
+        (((block_fnum & 0x7f0) >> 4) << 7) + CH->pms + (ym2612.OPN.LFO_PM & 0xF)];
+    if (ym2612.OPN.LFO_PM & 0x10) lfo_fn_table_index_offset = -lfo_fn_table_index_offset;
+
+    if (lfo_fn_table_index_offset) /* LFO phase modulation active */
+    {
+        UINT8 blk;
+        int kc, fc, finc;
+
+        block_fnum = __fast_mul(block_fnum , 2) + lfo_fn_table_index_offset;
+        blk = (block_fnum & 0x7000) >> 12;
+        block_fnum = block_fnum & 0xfff;
+
+        /* keyscale code */
+        kc = (blk << 2) | opn_fktable[block_fnum >> 8];
+
+        /* (frequency) phase increment counter */
+        fc = (ym2612.OPN.pfn_table[block_fnum] >> (7 - blk));
+
+        /* (frequency) phase overflow (credits to Nemesis) */
+        finc = fc + CH->SLOT[SLOT1].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT1].phase += (finc * CH->SLOT[SLOT1].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT2].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT2].phase += (finc * CH->SLOT[SLOT2].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT3].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT3].phase += (finc * CH->SLOT[SLOT3].mul) >> 1;
+
+        finc = fc + CH->SLOT[SLOT4].DT[kc];
+        if (finc < 0) finc += ym2612.OPN.fn_max;
+        CH->SLOT[SLOT4].phase += (finc * CH->SLOT[SLOT4].mul) >> 1;
+    }
+    else /* LFO phase modulation  = zero */
+    {
+        CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
+        CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
+        CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
+        CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
+    }
+}
+
+/* update phase increment and envelope generator */
+INLINE void refresh_fc_eg_slot(FM_SLOT* SLOT, int fc, int kc) {
+    /* add detune value */
+    fc += SLOT->DT[kc];
+
+    /* (frequency) phase overflow (credits to Nemesis) */
+    if (fc < 0) fc += ym2612.OPN.fn_max;
+
+    /* (frequency) phase increment counter */
+    SLOT->Incr = (fc * SLOT->mul) >> 1;
+
+    /* ksr */
+    kc = kc >> SLOT->KSR;
+
+    if (SLOT->ksr != kc) {
+        SLOT->ksr = kc;
+
+        /* recalculate envelope generator rates */
+        if ((SLOT->ar + kc) < (32 + 62)) {
+            SLOT->eg_sh_ar = eg_rate_shift[SLOT->ar + kc];
+            SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + kc];
+        }
+        else {
+            /* verified by Nemesis on real hardware (Attack phase is blocked) */
+            SLOT->eg_sh_ar = 0;
+            SLOT->eg_sel_ar = 18 * RATE_STEPS;
+        }
+
+        SLOT->eg_sh_d1r = eg_rate_shift[SLOT->d1r + kc];
+        SLOT->eg_sel_d1r = eg_rate_select[SLOT->d1r + kc];
+
+        SLOT->eg_sh_d2r = eg_rate_shift[SLOT->d2r + kc];
+        SLOT->eg_sel_d2r = eg_rate_select[SLOT->d2r + kc];
+
+        SLOT->eg_sh_rr = eg_rate_shift[SLOT->rr + kc];
+        SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + kc];
+    }
+}
+
+/* update phase increment counters */
+INLINE void refresh_fc_eg_chan(FM_CH* CH) {
+    if (CH->SLOT[SLOT1].Incr == -1) {
+        int fc = CH->fc;
+        int kc = CH->kcode;
+        refresh_fc_eg_slot(&CH->SLOT[SLOT1], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT2], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT3], fc, kc);
+        refresh_fc_eg_slot(&CH->SLOT[SLOT4], fc, kc);
+    }
+}
+
+#define volume_calc(OP) ((OP)->vol_out + (AM & (OP)->AMmask))
+
+INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm) {
+    UINT32 p = (env << 3) + sin_tab[(((signed int)((phase & ~FREQ_MASK) + (pm << 15))) >> FREQ_SH) & SIN_MASK];
+
+    if (p >= TL_TAB_LEN)
+        return 0;
+    return tl_tab[p];
+}
+
+INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm) {
+    UINT32 p = (env << 3) + sin_tab[(((signed int)((phase & ~FREQ_MASK) + pm)) >> FREQ_SH) & SIN_MASK];
+
+    if (p >= TL_TAB_LEN)
+        return 0;
+    return tl_tab[p];
+}
+
+INLINE void chan_calc(FM_CH* CH) {
+    UINT32 AM = ym2612.OPN.LFO_AM >> CH->ams;
+    unsigned int eg_out = volume_calc(&CH->SLOT[SLOT1]);
+
+    m2 = c1 = c2 = mem = 0;
+
+    *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
+    {
+        INT32 out = CH->op1_out[0] + CH->op1_out[1];
+        CH->op1_out[0] = CH->op1_out[1];
+
+        if (!CH->connect1) {
+            /* algorithm 5  */
+            mem = c1 = c2 = CH->op1_out[0];
+        }
+        else {
+            /* other algorithms */
+            *CH->connect1 += CH->op1_out[0];
+        }
+
+        CH->op1_out[1] = 0;
+        if (eg_out < ENV_QUIET) /* SLOT 1 */
+        {
+            if (!CH->FB)
+                out = 0;
+
+            CH->op1_out[1] = op_calc1(CH->SLOT[SLOT1].phase, eg_out, (out << CH->FB));
+        }
+    }
+
+    eg_out = volume_calc(&CH->SLOT[SLOT3]);
+    if (eg_out < ENV_QUIET) /* SLOT 3 */
+        *CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, m2);
+
+    eg_out = volume_calc(&CH->SLOT[SLOT2]);
+    if (eg_out < ENV_QUIET) /* SLOT 2 */
+        *CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, c1);
+
+    eg_out = volume_calc(&CH->SLOT[SLOT4]);
+    if (eg_out < ENV_QUIET) /* SLOT 4 */
+        *CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, c2);
+
+
+    /* store current MEM */
+    CH->mem_value = mem;
+
+    /* update phase counters AFTER output calculations */
+    if (CH->pms) {
+        /* add support for 3 slot mode */
+        if ((ym2612.OPN.ST.mode & 0xC0) && (CH == &ym2612.CH[2])) {
+            update_phase_lfo_slot(&CH->SLOT[SLOT1], CH->pms, ym2612.OPN.SL3.block_fnum[1]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT2], CH->pms, ym2612.OPN.SL3.block_fnum[2]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT3], CH->pms, ym2612.OPN.SL3.block_fnum[0]);
+            update_phase_lfo_slot(&CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
+        }
+        else update_phase_lfo_channel(CH);
+    }
+    else /* no LFO phase modulation */
+    {
+        CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
+        CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
+        CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
+        CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
+    }
+}
+
+/* write a OPN mode register 0x20-0x2f */
+INLINE void OPNWriteMode(int r, int v) {
+    UINT8 c;
+    FM_CH* CH;
+
+    OPNREGS[r] = v;
+
+    switch (r) {
+        case 0x21: /* Test */
+            break;
+
+        case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/ym2612) */
+            if (v & 8) /* LFO enabled ? */
+            {
+                if (!ym2612.OPN.lfo_timer_overflow) {
+                    /* restart LFO */
+                    ym2612.OPN.lfo_cnt = 0;
+                    ym2612.OPN.lfo_timer = 0;
+                    ym2612.OPN.LFO_AM = 0;
+                    ym2612.OPN.LFO_PM = 0;
+                }
+
+                ym2612.OPN.lfo_timer_overflow = lfo_samples_per_step[v & 7] << LFO_SH;
+            }
+            else {
+                ym2612.OPN.lfo_timer_overflow = 0;
+            }
+
+            break;
+        case 0x24: /* timer A High 8*/
+            ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x03) | (((int)v) << 2);
+            ym2612.OPN.ST.TAL = (1024 - ym2612.OPN.ST.TA) << TIMER_SH;
+            break;
+        case 0x25: /* timer A Low 2*/
+            ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x3fc) | (v & 3);
+            ym2612.OPN.ST.TAL = (1024 - ym2612.OPN.ST.TA) << TIMER_SH;
+            break;
+        case 0x26: /* timer B */
+            ym2612.OPN.ST.TB = v;
+            ym2612.OPN.ST.TBL = (256 - ym2612.OPN.ST.TB) << (TIMER_SH + 4);
+            break;
+        case 0x27: /* mode, timer control */
+            set_timers(v);
+            break;
+        case 0x28: /* key on / off */
+            c = v & 0x03;
+            if (c == 3) break;
+            if (v & 0x04) c += 3; /* CH 4-6 */
+            CH = &ym2612.CH[c];
+
+            if (v & 0x10) FM_KEYON(CH,SLOT1);
+            else FM_KEYOFF(CH,SLOT1);
+            if (v & 0x20) FM_KEYON(CH,SLOT2);
+            else FM_KEYOFF(CH,SLOT2);
+            if (v & 0x40) FM_KEYON(CH,SLOT3);
+            else FM_KEYOFF(CH,SLOT3);
+            if (v & 0x80) FM_KEYON(CH,SLOT4);
+            else FM_KEYOFF(CH,SLOT4);
+            break;
+    }
+}
+
+/* write a OPN register (0x30-0xff) */
+INLINE void OPNWriteReg(int r, int v) {
+    FM_CH* CH;
+    FM_SLOT* SLOT;
+
+    OPNREGS[r] = v;
+
+    UINT8 c = OPN_CHAN(r);
+
+    if (c == 3) return; /* 0xX3,0xX7,0xXB,0xXF */
+
+    if (r >= 0x100) c += 3;
+
+    CH = &ym2612.CH[c];
+
+    SLOT = &(CH->SLOT[OPN_SLOT(r)]);
+
+    switch (r & 0xf0) {
+        case 0x30: /* DET , MUL */
+            set_det_mul(CH, SLOT, v);
+            break;
+
+        case 0x40: /* TL */
+            set_tl(SLOT, v);
+            break;
+
+        case 0x50: /* KS, AR */
+            set_ar_ksr(CH, SLOT, v);
+            break;
+
+        case 0x60: /* bit7 = AM ENABLE, DR */
+            set_dr(SLOT, v);
+            SLOT->AMmask = (v & 0x80) ? ~0 : 0;
+            break;
+
+        case 0x70: /*     SR */
+            set_sr(SLOT, v);
+            break;
+
+        case 0x80: /* SL, RR */
+            set_sl_rr(SLOT, v);
+            break;
+
+        case 0x90: /* SSG-EG */
+            SLOT->ssg = v & 0x0f;
+
+        /* recalculate EG output */
+            if (SLOT->state > EG_REL) {
+                if ((SLOT->ssg & 0x08) && (SLOT->ssgn ^ (SLOT->ssg & 0x04)))
+                    SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
+                else
+                    SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
+            }
+
+        /* SSG-EG envelope shapes :
+
+        E AtAlH
+        1 0 0 0  \\\\
+
+        1 0 0 1  \___
+
+        1 0 1 0  \/\/
+                  ___
+        1 0 1 1  \
+
+        1 1 0 0  ////
+                  ___
+        1 1 0 1  /
+
+        1 1 1 0  /\/\
+
+        1 1 1 1  /___
+
+
+        E = SSG-EG enable
+
+
+        The shapes are generated using Attack, Decay and Sustain phases.
+
+        Each single character in the diagrams above represents this whole
+        sequence:
+
+        - when KEY-ON = 1, normal Attack phase is generated (*without* any
+          difference when compared to normal mode),
+
+        - later, when envelope level reaches minimum level (max volume),
+          the EG switches to Decay phase (which works with bigger steps
+          when compared to normal mode - see below),
+
+        - later when envelope level passes the SL level,
+          the EG swithes to Sustain phase (which works with bigger steps
+          when compared to normal mode - see below),
+
+        - finally when envelope level reaches maximum level (min volume),
+          the EG switches to Attack phase again (depends on actual waveform).
+
+        Important is that when switch to Attack phase occurs, the phase counter
+        of that operator will be zeroed-out (as in normal KEY-ON) but not always.
+        (I havent found the rule for that - perhaps only when the output level is low)
+
+        The difference (when compared to normal Envelope Generator mode) is
+        that the resolution in Decay and Sustain phases is 4 times lower;
+        this results in only 256 steps instead of normal 1024.
+        In other words:
+        when SSG-EG is disabled, the step inside of the EG is one,
+        when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
+
+        Times between the level changes are the same in both modes.
+
+
+        Important:
+        Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
+        it is the same in both SSG and no-SSG modes, with this exception:
+
+        when the SSG-EG is enabled and is generating raising levels
+        (when the EG output is inverted) the SL will be found at wrong level !!!
+        For example, when SL=02:
+          0 -6 = -6dB in non-inverted EG output
+          96-6 = -90dB in inverted EG output
+        Which means that EG compares its level to SL as usual, and that the
+        output is simply inverted afterall.
+
+
+        The Yamaha's manuals say that AR should be set to 0x1f (max speed).
+        That is not necessary, but then EG will be generating Attack phase.
+
+        */
+
+
+            break;
+
+        case 0xa0:
+            switch (OPN_SLOT(r)) {
+                case 0: /* 0xa0-0xa2 : FNUM1 */
+                {
+                    UINT32 fn = (((UINT32)((ym2612.OPN.ST.fn_h) & 7)) << 8) + v;
+                    UINT8 blk = ym2612.OPN.ST.fn_h >> 3;
+                    /* keyscale code */
+                    CH->kcode = (blk << 2) | opn_fktable[fn >> 7];
+                    /* phase increment counter */
+                    CH->fc = ym2612.OPN.pfn_table[__fast_mul(fn, 2)] >> (7 - blk);
+
+                    /* store fnum in clear form for LFO PM calculations */
+                    CH->block_fnum = (blk << 11) | fn;
+
+                    CH->SLOT[SLOT1].Incr = -1;
+                    break;
+                }
+                case 1: /* 0xa4-0xa6 : FNUM2,BLK */
+                    ym2612.OPN.ST.fn_h = v & 0x3f;
+                    break;
+                case 2: /* 0xa8-0xaa : 3CH FNUM1 */
+                    if (r < 0x100) {
+                        UINT32 fn = (((UINT32)(ym2612.OPN.SL3.fn_h & 7)) << 8) + v;
+                        UINT8 blk = ym2612.OPN.SL3.fn_h >> 3;
+                        /* keyscale code */
+                        ym2612.OPN.SL3.kcode[c] = (blk << 2) | opn_fktable[fn >> 7];
+                        /* phase increment counter */
+                        ym2612.OPN.SL3.fc[c] = ym2612.OPN.pfn_table[__fast_mul(fn, 2)] >> (7 - blk);
+                        ym2612.OPN.SL3.block_fnum[c] = (blk << 11) | fn;
+                        ym2612.CH[2].SLOT[SLOT1].Incr = -1;
+                    }
+                    break;
+                case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
+                    if (r < 0x100)
+                        ym2612.OPN.SL3.fn_h = v & 0x3f;
+                    break;
+            }
+            break;
+
+        case 0xb0:
+            switch (OPN_SLOT(r)) {
+                case 0: /* 0xb0-0xb2 : FB,ALGO */
+                {
+                    int feedback = (v >> 3) & 7;
+                    CH->ALGO = v & 7;
+                    CH->FB = feedback ? feedback + 6 : 0;
+                    setup_connection(CH, c);
+                    break;
+                }
+                case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (ym2612/YM2610B/YM2610/YM2608) */
+                    /* b0-2 PMS */
+                    CH->pms = __fast_mul(v & 7, 16); /* CH->pms = PM depth * 16 (index in lfo_pm_table) */
+
+                /* b4-5 AMS */
+                    CH->ams = lfo_ams_depth_shift[(v >> 4) & 0x03];
+
+                /* PAN :  b7 = L, b6 = R */
+                // ym2612.OPN.pan[ c*2   ] = (v & 0x80) ? ~0 : 0;
+                // ym2612.OPN.pan[ c*2+1 ] = (v & 0x40) ? ~0 : 0;
+                    break;
+            }
+            break;
+    }
+}
+
+
+/* initialize time tables */
+static void init_timetables(double freqbase) {
+    int i, d;
+    double rate;
+    ym2612.OPN.pfn_table = &fn_table[0];
+#if GENERATE_TABLES
+  /* DeTune table */
+  for (d = 0;d <= 3;d++)
+  {
+    for (i = 0;i <= 31;i++)
+    {
+      rate = ((double)dt_tab[d*32 + i]) * freqbase * (1<<(FREQ_SH-10)); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
+      ym2612_OPN_ST_dt_tab[d][i]   = (INT32) rate;
+      ym2612_OPN_ST_dt_tab[d+4][i] = -ym2612_OPN_ST_dt_tab[d][i];
+    }
+  }
+
+  /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
+      but LFO works with one more bit of a precision so we really need 4096 elements */
+  /* calculate fnumber -> increment counter table */
+  for(i = 0; i < 4096; i++)
+  {
+    /* freq table for octave 7 */
+    /* OPN phase increment counter = 20bit */
+    /* the correct formula is : F-Number = (144 * fnote * 2^20 / M) / 2^(B-1) */
+    /* where sample clock is  M/144 */
+    /* this means the increment value for one clock sample is FNUM * 2^(B-1) = FNUM * 64 for octave 7 */
+    /* we also need to handle the ratio between the chip frequency and the emulated frequency (can be 1.0)  */
+    ym2612.OPN.pfn_table[i] = (unsigned int)( (double)i * 32 * freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
+  }
+	FIL f;
+	UINT bw;
+	char tmp[64];
+	const char * str = "const unsigned int __in_flash() __aligned(4) fn_table[] = {\n";
+	f_open(&f, "\\fn_table.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+  sprintf(tmp, " // freqbase: %f\n", freqbase);
+	f_write(&f, tmp, strlen(tmp), &bw);
+	for(int i = 0; i < sizeof(fn_table) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", fn_table[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+  str = "const unsigned int __in_flash() __aligned(4) ym2612_OPN_ST_dt_tab[8][32] = {\n";
+	f_open(&f, "\\ym2612_OPN_ST_dt_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+  sprintf(tmp, " // freqbase: %f\n", freqbase);
+	f_write(&f, tmp, strlen(tmp), &bw);
+	for(int i = 0; i < 8; ++i) {
+	 if (i == 0) {
+			str = " {";
+	 } else {
+			str = ", {";
+	 }
+	 f_write(&f, str, strlen(str), &bw);
+   for(int j = 0; j < 32; ++j) {
+		if (j == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", ym2612_OPN_ST_dt_tab[i][j]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+   }
+   str = " },\n";
+	 f_write(&f, str, strlen(str), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+#endif
+    /* maximal frequency is required for Phase overflow calculation, register size is 17 bits (Nemesis) */
+    ym2612.OPN.fn_max = (UINT32)((double)0x20000 * freqbase * (1 << (FREQ_SH - 10)));
+}
+
+/* prescaler set (and make time tables) */
+static void OPNSetPres(int pres) {
+    /* frequency base (ratio between FM original samplerate & desired output samplerate)*/
+    double freqbase = ym2612.OPN.ST.clock / ym2612.OPN.ST.rate / pres;
+
+    //fcipaq
+    freqbase = GWENESIS_AUDIO_SAMPLING_DIVISOR; // override the above to prevent rounding error
+
+    /* YM2612 running at original frequency (~53267 Hz) */
+    //if (config.hq_fm) freqbase  = 1.0;
+
+    /* EG is updated every 3 samples */
+    ym2612.OPN.eg_timer_add = (UINT32)((1 << EG_SH) * freqbase);
+    ym2612.OPN.eg_timer_overflow = (3) * (1 << EG_SH);
+
+    /* LFO timer increment (every samples) */
+    ym2612.OPN.lfo_timer_add = (UINT32)((1 << LFO_SH) * freqbase);
+
+    /* Timers increment (every samples) */
+    ym2612.OPN.ST.TimerBase = (int)((1 << TIMER_SH) * freqbase);
+
+    /* make time tables */
+    init_timetables(freqbase);
+}
+
+static void reset_channels(FM_CH* CH, int num) {
+    int c, s;
+
+    for (c = 0; c < num; c++) {
+        CH[c].mem_value = 0;
+        CH[c].op1_out[0] = 0;
+        CH[c].op1_out[1] = 0;
+        for (s = 0; s < 4; s++) {
+            CH[c].SLOT[s].Incr = -1;
+            CH[c].SLOT[s].key = 0;
+            CH[c].SLOT[s].phase = 0;
+            CH[c].SLOT[s].ssgn = 0;
+            CH[c].SLOT[s].state = EG_OFF;
+            CH[c].SLOT[s].volume = MAX_ATT_INDEX;
+            CH[c].SLOT[s].vol_out = MAX_ATT_INDEX;
+        }
+    }
+}
+
+/* initialize generic tables */
+static void init_tables(void) {
+    signed int i, x, d;
+    signed int n;
+    double o, m;
+#if GENERATE_TABLES
+  /* build Linear Power Table */
+  for (x=0; x<TL_RES_LEN; x++)
+  {
+    m = (1<<16) / pow(2,(x+1) * (ENV_STEP/4.0) / 8.0);
+    m = floor(m);
+
+    /* we never reach (1<<16) here due to the (x+1) */
+    /* result fits within 16 bits at maximum */
+
+    n = (int)m; /* 16 bits here */
+    n >>= 4;    /* 12 bits here */
+    if (n&1)    /* round to nearest */
+      n = (n>>1)+1;
+    else
+      n = n>>1;
+                /* 11 bits here (rounded) */
+    n <<= 2;    /* 13 bits here (as in real chip) */
+
+    /* 14 bits (with sign bit) */
+    tl_tab[ x*2 + 0 ] = n;
+    tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
+
+    /* one entry in the 'Power' table use the following format, xxxxxyyyyyyyys with:            */
+    /*        s = sign bit                                                                      */
+    /* yyyyyyyy = 8-bits decimal part (0-TL_RES_LEN)                                            */
+    /* xxxxx    = 5-bits integer 'shift' value (0-31) but, since Power table output is 13 bits, */
+    /*            any value above 13 (included) would be discarded.                             */
+    for (i=1; i<13; i++)
+    {
+      tl_tab[ x*2+0 + i*2*TL_RES_LEN ] =  (tl_tab[ x*2+0 ]>>i);
+      tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
+    }
+  }
+
+  /* build Logarithmic Sinus table */
+  for (i=0; i<SIN_LEN; i++)
+  {
+    /* non-standard sinus */
+    m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
+    /* we never reach zero here due to ((i*2)+1) */
+
+    if (m>0.0)
+      o = 8*log(1.0/m)/log(2);  /* convert to 'decibels' */
+    else
+      o = 8*log(-1.0/m)/log(2);  /* convert to 'decibels' */
+
+    o = o / (ENV_STEP/4);
+
+    n = (int)(2.0*o);
+    if (n&1)            /* round to nearest */
+      n = (n>>1)+1;
+    else
+      n = n>>1;
+
+    /* 13-bits (8.5) value is formatted for above 'Power' table */
+    sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
+  }
+
+  /* build LFO PM modulation table */
+  for(i = 0; i < 8; i++) /* 8 PM depths */
+  {
+    UINT8 fnum;
+    for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
+    {
+      UINT8 value;
+      UINT8 step;
+      UINT32 offset_depth = i;
+      UINT32 offset_fnum_bit;
+      UINT32 bit_tmp;
+
+      for (step=0; step<8; step++)
+      {
+        value = 0;
+        for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
+        {
+          if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
+          {
+            offset_fnum_bit = bit_tmp * 8;
+            value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
+          }
+        }
+        /* 16 steps for LFO PM (sinus) */
+        lfo_pm_table[(fnum * 16 * 8) + (i * 16) + step + 0] = value;
+        lfo_pm_table[(fnum * 16 * 8) + (i * 16) + (step ^ 7) + 8] = value;
+      }
+    }
+  }
+  /* build DETUNE table */
+  for (d = 0;d <= 3;d++)
+  {
+    for (i = 0;i <= 31;i++)
+    {
+      ym2612_OPN_ST_dt_tab[d][i]   = (INT32) dt_tab[d*32 + i];
+      ym2612_OPN_ST_dt_tab[d+4][i] = -ym2612_OPN_ST_dt_tab[d][i];
+    }
+  }
+	FIL f;
+	UINT bw;
+	char tmp[64];
+	const char * str = "const unsigned char __in_flash() __aligned(4) lfo_pm_table[] = {\n";
+	f_open(&f, "\\lfo_pm_table.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(lfo_pm_table); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", i - 16);
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "0x%02X", (unsigned char)lfo_pm_table[i] & 0xFF);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+	str = "const signed int __in_flash() __aligned(4) tl_tab[] = {\n";
+	f_open(&f, "\\tl_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(tl_tab) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", tl_tab[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+
+	str = "const unsigned int __in_flash() __aligned(4) sin_tab[] = {\n";
+	f_open(&f, "\\sin_tab.h", FA_CREATE_ALWAYS | FA_WRITE);
+	f_write(&f, str, strlen(str), &bw);
+	for(int i = 0; i < sizeof(sin_tab) / sizeof(int); ++i) {
+		if (i && !(i % 16)) {
+			sprintf(tmp, " // 0x%08X\n", (i - 16) * sizeof(int));
+			f_write(&f, tmp, strlen(tmp), &bw);
+		}
+		if (i == 0) {
+			str = "  ";
+		} else {
+			str = ", ";
+		}
+		f_write(&f, str, strlen(str), &bw);
+		sprintf(tmp, "%d", sin_tab[i]);
+		f_write(&f, tmp, strlen(tmp), &bw);
+	}
+	str = "};\n";
+	f_write(&f, str, strlen(str), &bw);
+	f_close(&f);
+#endif
+}
+
+/* initialize ym2612 emulator(s) */
+void YM2612Init() {
+    memset(&ym2612, 0, sizeof(YM2612));
+    ym2612.OPN.pfn_table = fn_table;
+    init_tables();
+    ym2612.OPN.ST.clock = GWENESIS_AUDIO_FREQ_NTSC;
+    ym2612.OPN.ST.rate = GWENESIS_AUDIO_FREQ_NTSC / (6 * 24) / GWENESIS_AUDIO_SAMPLING_DIVISOR;
+    OPNSetPres(6 * 24);
+    /* YM2612 prescaler is fixed to 1/6, one sample (6 mixed channels) is output for each 24 FM clocks */
+}
+
+/* reset OPN registers */
+void YM2612ResetChip(void) {
+    int i;
+
+    ym2612.OPN.eg_timer = 0;
+    ym2612.OPN.eg_cnt = 0;
+
+    ym2612.OPN.lfo_timer_overflow = 0;
+    ym2612.OPN.lfo_timer = 0;
+    ym2612.OPN.lfo_cnt = 0;
+    ym2612.OPN.LFO_AM = 0;
+    ym2612.OPN.LFO_PM = 0;
+
+    ym2612.OPN.ST.TAC = 0;
+    ym2612.OPN.ST.TBC = 0;
+
+    ym2612.OPN.SL3.key_csm = 0;
+
+    ym2612.dacen = 0;
+    ym2612.dacout = 0;
+
+    set_timers(0x30);
+    ym2612.OPN.ST.TB = 0;
+    ym2612.OPN.ST.TBL = 256 << (TIMER_SH + 4);
+    ym2612.OPN.ST.TA = 0;
+    ym2612.OPN.ST.TAL = 1024 << TIMER_SH;
+
+    reset_channels(&ym2612.CH[0], 6);
+
+    for (i = 0xb6; i >= 0xb4; i--) {
+        OPNWriteReg(i, 0xc0);
+        OPNWriteReg(i | 0x100, 0xc0);
+    }
+    for (i = 0xb2; i >= 0x30; i--) {
+        OPNWriteReg(i, 0);
+        OPNWriteReg(i | 0x100, 0);
+    }
+}
+
+/* ym2612 write */
+/* n = number  */
+/* a = address */
+/* v = value   */
+void YM2612Write(unsigned int a, unsigned int v, int target) {
+    //Sync
+    if (snd_accurate == 1)
+        ym2612_run(target);
+
+    v &= 0xff; /* adjust to 8 bit bus */
+
+    switch (a) {
+        case 0: /* address port 0 */
+            ym2612.OPN.ST.address = v;
+            break;
+
+        case 2: /* address port 1 */
+            ym2612.OPN.ST.address = v | 0x100;
+            break;
+
+        default: /* data port */
+        {
+            int addr = ym2612.OPN.ST.address; /* verified by Nemesis on real YM2612 */
+            switch (addr & 0x1f0) {
+                case 0x20: /* 0x20-0x2f Mode */
+                    switch (addr) {
+                        case 0x2a: /* DAC data (ym2612) */
+                            ym2612.dacout = ((int)v - 0x80) << 6; /* level unknown (5 is too low, 8 is too loud) */
+                            break;
+                        case 0x2b: /* DAC Sel  (ym2612) */
+                            /* b7 = dac enable */
+                            ym2612.dacen = v & 0x80;
+                            break;
+                        default: /* OPN section */
+                            /* write register */
+                            OPNWriteMode(addr, v);
+                    }
+                    break;
+                default: /* 0x30-0xff OPN section */
+                    /* write register */
+                    OPNWriteReg(addr, v);
+            }
+            break;
+        }
+    }
+}
+
+unsigned int YM2612Read(int target) {
+    // //Sync
+    if (snd_accurate == 1)
+        ym2612_run(target);
+
+    return ym2612.OPN.ST.status & 0xff;
+}
+
+extern bool sn76489_enabled;
+
+/* Generate samples for ym2612 */
+void YM2612Update(int16_t* buffer, int length) {
+    int i;
+    int lt;
+
+    /* refresh PG increments and EG rates if required */
+    refresh_fc_eg_chan(&ym2612.CH[0]);
+    refresh_fc_eg_chan(&ym2612.CH[1]);
+
+    if (!(ym2612.OPN.ST.mode & 0xC0)) {
+        refresh_fc_eg_chan(&ym2612.CH[2]);
+    }
+    else {
+        /* 3SLOT MODE (operator order is 0,1,3,2) */
+        if (ym2612.CH[2].SLOT[SLOT1].Incr == -1) {
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT1], ym2612.OPN.SL3.fc[1], ym2612.OPN.SL3.kcode[1]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT2], ym2612.OPN.SL3.fc[2], ym2612.OPN.SL3.kcode[2]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT3], ym2612.OPN.SL3.fc[0], ym2612.OPN.SL3.kcode[0]);
+            refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT4], ym2612.CH[2].fc, ym2612.CH[2].kcode);
+        }
+    }
+
+    refresh_fc_eg_chan(&ym2612.CH[3]);
+    refresh_fc_eg_chan(&ym2612.CH[4]);
+    refresh_fc_eg_chan(&ym2612.CH[5]);
+    bool inc_mode = sn76489_enabled;
+    /* buffering */
+    for (i = 0; i < length; i++) {
+        /* clear outputs */
+        out_fm[0] = 0;
+        out_fm[1] = 0;
+        out_fm[2] = 0;
+        out_fm[3] = 0;
+        out_fm[4] = 0;
+        out_fm[5] = 0;
+
+        /* update SSG-EG output */
+        update_ssg_eg_channel(&ym2612.CH[0].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[1].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[2].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[3].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[4].SLOT[SLOT1]);
+        update_ssg_eg_channel(&ym2612.CH[5].SLOT[SLOT1]);
+
+        /* calculate FM */
+        chan_calc(&ym2612.CH[0]);
+        chan_calc(&ym2612.CH[1]);
+        chan_calc(&ym2612.CH[2]);
+        chan_calc(&ym2612.CH[3]);
+        chan_calc(&ym2612.CH[4]);
+        if (!ym2612.dacen) {
+            chan_calc(&ym2612.CH[5]);
+        }
+        else {
+            /* DAC Mode */
+            out_fm[5] = ym2612.dacout;
+        }
+
+        /* advance LFO */
+        advance_lfo();
+
+        /* advance envelope generator */
+        ym2612.OPN.eg_timer += ym2612.OPN.eg_timer_add;
+        while (ym2612.OPN.eg_timer >= ym2612.OPN.eg_timer_overflow) {
+            ym2612.OPN.eg_timer -= ym2612.OPN.eg_timer_overflow;
+            ym2612.OPN.eg_cnt++;
+            advance_eg_channels();
+        }
+
+        /* 14-bit DAC inputs (range is -8192;+8191) */
+        if (out_fm[0] > 8192) out_fm[0] = 8191;
+        else if (out_fm[0] < -8192) out_fm[0] = -8192;
+        if (out_fm[1] > 8192) out_fm[1] = 8191;
+        else if (out_fm[1] < -8192) out_fm[1] = -8192;
+        if (out_fm[2] > 8192) out_fm[2] = 8191;
+        else if (out_fm[2] < -8192) out_fm[2] = -8192;
+        if (out_fm[3] > 8192) out_fm[3] = 8191;
+        else if (out_fm[3] < -8192) out_fm[3] = -8192;
+        if (out_fm[4] > 8192) out_fm[4] = 8191;
+        else if (out_fm[4] < -8192) out_fm[4] = -8192;
+        if (out_fm[5] > 8192) out_fm[5] = 8191;
+        else if (out_fm[5] < -8192) out_fm[5] = -8192;
+
+        /* 6-channels mono only  */
+        lt = out_fm[0];
+        lt += out_fm[1];
+        lt += out_fm[2];
+        lt += out_fm[3];
+        lt += out_fm[4];
+        lt += out_fm[5];
+
+        /* buffering */
+        if (inc_mode) *buffer++ += lt;
+        else *buffer++ = lt;
+        // *buffer++ += lt / (2 << (11 - snd_output_volume));
+
+        /* CSM mode: if CSM Key ON has occured, CSM Key OFF need to be sent       */
+        /* only if Timer A does not overflow again (i.e CSM Key ON not set again) */
+        ym2612.OPN.SL3.key_csm <<= 1;
+
+        /* timer A control */
+        INTERNAL_TIMER_A();
+
+        /* CSM Mode Key ON still disabled */
+        if (ym2612.OPN.SL3.key_csm & 2) {
+            /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
+            FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
+            ym2612.OPN.SL3.key_csm = 0;
+        }
+    }
+
+    /* timer B control */
+    INTERNAL_TIMER_B(length);
+}
+
+void ym2612_run(int target) {
+    /**
+      if ( ym2612_clock >= target) {
+        return;
+      }
+
+      target /= GWENESIS_AUDIO_SAMPLING_DIVISOR;
+
+      int ym2612_prev_index = ym2612_index;
+      ym2612_index += (target-ym2612_clock) / ym2612.divisor;
+      if (ym2612_index > ym2612_prev_index) {
+        YM2612Update(gwenesis_sn76489_buffer + ym2612_prev_index, ym2612_index - ym2612_prev_index);
+        ym2612_clock = ym2612_index*ym2612.divisor;
+
+      } else {
+        ym2612_index = ym2612_prev_index;
+      }*/
+}
+
+unsigned char* YM2612GetContextPtr(void) {
+    return (unsigned char *)&ym2612;
+}
+
+unsigned int YM2612GetContextSize(void) {
+    return sizeof(YM2612);
+}
+
+void YM2612Restore(unsigned char* buffer) {
+    /* save current timings */
+    double clock = ym2612.OPN.ST.clock;
+    int rate = ym2612.OPN.ST.rate;
+
+    /* restore internal state */
+    memcpy(&ym2612, buffer, sizeof(YM2612));
+
+    /* keep current timings */
+    ym2612.OPN.ST.clock = clock;
+    ym2612.OPN.ST.rate = rate;
+    OPNSetPres(6 * 24);
+
+    /* restore outputs connections */
+    setup_connection(&ym2612.CH[0], 0);
+    setup_connection(&ym2612.CH[1], 1);
+    setup_connection(&ym2612.CH[2], 2);
+    setup_connection(&ym2612.CH[3], 3);
+    setup_connection(&ym2612.CH[4], 4);
+    setup_connection(&ym2612.CH[5], 5);
+
+    /* restore TL table (DAC resolution might have been modified) */
+    init_tables();
+}
+
+void YM2612Config(unsigned char dac_bits) //,unsigned int AUDIO_FREQ_DIVISOR)
+{
+    int i;
+
+    /* DAC precision (normally 9-bit on real hardware, implemented through simple 14-bit channel output bitmasking) */
+    bitmask = ~((1 << (TL_BITS - dac_bits)) - 1);
+
+    /* update L/R panning bitmasks */
+    for (i = 0; i < 2 * 6; i++) {
+        if (ym2612.OPN.pan[i]) {
+            ym2612.OPN.pan[i] = bitmask;
+        }
+    }
+    ym2612.divisor = AUDIO_FREQ_DIVISOR;
+}
+
+void YM2612SaveRegs(uint8_t* regs) {
+    memcpy(regs, OPNREGS, sizeof(OPNREGS));
+}
+
+void YM2612LoadRegs(uint8_t* regs) {
+    int i;
+    for (i = 0; i < sizeof(OPNREGS); ++i) {
+        if (i <= 0x30)
+            OPNWriteMode(i, *regs++);
+        else
+            OPNWriteReg(i, *regs++);
+    }
+
+    /* restore outputs connections */
+    setup_connection(&ym2612.CH[0], 0);
+    setup_connection(&ym2612.CH[1], 1);
+    setup_connection(&ym2612.CH[2], 2);
+    setup_connection(&ym2612.CH[3], 3);
+    setup_connection(&ym2612.CH[4], 4);
+    setup_connection(&ym2612.CH[5], 5);
+}
+
+#if 0
+int YM2612LoadContext(unsigned char *state)
+{
+  int c,s;
+  uint8 index;
+  int bufferptr = sizeof(YM2612);
+
+  /* restore YM2612 context */
+  YM2612Restore(state);
+
+  /* restore DT table address pointer for each channel slots */
+  for( c = 0 ; c < 6 ; c++ )
+  {
+    for(s = 0 ; s < 4 ; s++ )
+    {
+      load_param(&index,sizeof(index));
+      bufferptr += sizeof(index);
+      ym2612.CH[c].SLOT[s].DT = ym2612.OPN.ST.dt_tab[index&7];
+    }
+  }
+
+  return bufferptr;
+}
+
+int YM2612SaveContext(unsigned char *state)
+{
+  int c,s;
+  uint8 index;
+  int bufferptr = sizeof(YM2612);
+
+  /* save YM2612 context */
+  memcpy(state, &ym2612, sizeof(YM2612));
+
+  /* save DT table index for each channel slots */
+  for( c = 0 ; c < 6 ; c++ )
+  {
+    for(s = 0 ; s < 4 ; s++ )
+    {
+      index = (ym2612.CH[c].SLOT[s].DT - ym2612.OPN.ST.dt_tab[0]) >> 5;
+      save_param(&index,sizeof(index));
+      bufferptr += sizeof(index);
+    }
+  }
+
+  return bufferptr;
+}
+#endif
+
+void gwenesis_ym2612_save_state() {
+}
+
+void gwenesis_ym2612_load_state() {
+}
diff --git a/MCUME_pico2/picogen/gwenesis/sound/ym2612.h b/MCUME_pico2/picogen/gwenesis/sound/ym2612.h
new file mode 100755
index 0000000..e65576b
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/ym2612.h
@@ -0,0 +1,44 @@
+/*
+**
+** software implementation of Yamaha FM sound generator (YM2612/YM3438)
+**
+** Original code (MAME fm.c)
+**
+** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
+** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
+**
+** Version 1.4 (final beta)
+**
+** Additional code & fixes by Eke-Eke for Genesis Plus GX
+**
+*/
+
+#ifndef _H_YM2612_
+#define _H_YM2612_
+
+extern int16_t gwenesis_sn76489_buffer[];
+///extern int ym2612_index;
+///extern int ym2612_clock;
+
+extern int snd_output_volume;
+
+extern void YM2612Init();
+extern void YM2612Config(unsigned char dac_bits); //,unsigned int AUDIO_FREQ_DIVISOR);
+extern void YM2612ResetChip(void);
+//extern void YM2612Update(int16_t *buffer, int length);
+extern void YM2612Write(unsigned int a, unsigned int v,  int target);
+extern void ym2612_run(int target);
+extern unsigned int YM2612Read(int target);
+
+#if 0
+extern int YM2612LoadContext(unsigned char *state);
+extern int YM2612SaveContext(unsigned char *state);
+#endif
+
+//extern void YM2612LoadRegs(uint8_t *regs);
+//extern void YM2612SaveRegs(uint8_t *regs);
+
+void gwenesis_ym2612_save_state();
+void gwenesis_ym2612_load_state();
+
+#endif /* _YM2612_ */
diff --git a/MCUME_pico2/picogen/gwenesis/sound/ym2612_OPN_ST_dt_tab.h b/MCUME_pico2/picogen/gwenesis/sound/ym2612_OPN_ST_dt_tab.h
new file mode 100755
index 0000000..f833655
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/ym2612_OPN_ST_dt_tab.h
@@ -0,0 +1,11 @@
+const unsigned int __in_flash() __aligned(4) ym2612_OPN_ST_dt_tab[8][32] = {
+ // freqbase: 6.000000
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 384, 384, 384, 384, 384, 384, 384, 384, 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3072, 3072 },
+ { 384, 384, 384, 384, 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3456, 3840, 4224, 4608, 4992, 5376, 6144, 6144, 6144, 6144 },
+ { 768, 768, 768, 768, 768, 1152, 1152, 1152, 1536, 1536, 1536, 1920, 1920, 2304, 2304, 2688, 3072, 3072, 3456, 3840, 4224, 4608, 4992, 5376, 6144, 6528, 7296, 7680, 8448, 8448, 8448, 8448 },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, -384, -384, -384, -384, -384, -384, -384, -384, -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3072, -3072 },
+ { -384, -384, -384, -384, -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3456, -3840, -4224, -4608, -4992, -5376, -6144, -6144, -6144, -6144 },
+ { -768, -768, -768, -768, -768, -1152, -1152, -1152, -1536, -1536, -1536, -1920, -1920, -2304, -2304, -2688, -3072, -3072, -3456, -3840, -4224, -4608, -4992, -5376, -6144, -6528, -7296, -7680, -8448, -8448, -8448, -8448 }
+};
diff --git a/MCUME_pico2/picogen/gwenesis/sound/z80inst.c b/MCUME_pico2/picogen/gwenesis/sound/z80inst.c
new file mode 100755
index 0000000..454faa3
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/z80inst.c
@@ -0,0 +1,342 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#pragma GCC optimize("Ofast")
+
+#include <stdio.h>
+#include <stdint.h>
+#include <assert.h>
+#include "../cpus/Z80/Z80.h"
+#include "z80inst.h"
+#include "../cpus/M68K/m68k.h"
+#include "../bus/gwenesis_bus.h"
+// #include "ym2612.h"
+#include "gwenesis_sn76489.h"
+#include "ym2612.h"
+#include "../savestate/gwenesis_savestate.h"
+
+static int bus_ack = 0;
+static int reset = 0;
+static int reset_once = 0;
+int zclk = 0;
+static int initialized = 0;
+
+extern int audio_enabled;
+extern bool sound_enabled;
+
+unsigned char *Z80_RAM;
+
+static Z80 cpu;
+
+void ResetZ80(register Z80 *R);
+
+#define Z80_INST_DISABLE_LOGGING 1
+
+#if !Z80_INST_DISABLE_LOGGING
+#include <stdarg.h>
+void z80_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s]", frame_counter, scan_line, subs);
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+	#define z80_log(...)  do {} while(0)
+#endif
+
+// Bank register used by Z80 to access M68K Memory space 1 BANK=32KByte
+int Z80_BANK;
+
+
+void z80_start() {
+    cpu.IPeriod = 1;
+    cpu.ICount = 0;
+    cpu.Trace = 0;
+    cpu.Trap = 0x0009;
+    ResetZ80(&cpu);
+    reset=1;
+    reset_once=0;
+    bus_ack=0;
+    zclk=0;
+}
+
+void z80_pulse_reset() {
+  ResetZ80(&cpu);
+}
+static int current_timeslice = 0;
+
+void z80_run(int target) {
+
+  // we are in advance,nothind to do
+current_timeslice = 0;
+  if (zclk >= target) {
+ // z80_log("z80_skip time","%1d%1d%1d||zclk=%d,tgt=%d",reset_once,bus_ack,reset, zclk, target);
+    return;
+  }
+
+  current_timeslice = target - zclk;
+
+  int rem = 0;
+  if ((reset_once == 1) && (bus_ack == 0) && (reset == 0)) {
+
+   // z80_log("z80_run", "%1d%1d%1d||zclk=%d,tgt=%d",reset_once, bus_ack, reset, zclk, target);
+    rem = ExecZ80(&cpu, current_timeslice / Z80_FREQ_DIVISOR);
+
+  }
+
+  zclk = target - rem * Z80_FREQ_DIVISOR;
+}
+
+void z80_sync(void) {
+  /*
+  get M68K cycles 
+  Execute cycles on z80 to sync with m68K
+  */
+
+  z80_run(m68k_cycles_master());
+}
+
+void z80_set_memory(unsigned char *buffer)
+{
+    Z80_RAM = buffer;
+    initialized = 1;
+}
+
+void z80_write_ctrl(unsigned int address, unsigned int value) {
+  z80_sync();
+
+  if (address == 0x1100) // BUSREQ
+  {
+    z80_log(__FUNCTION__,"BUSREQ = %d, current=%d", value,bus_ack);
+
+    // Bus request. Z80 bus on hold.
+    if (value) {
+      bus_ack = 1;
+
+
+    // Bus request cancel. Z80 runs.
+    } else {
+            bus_ack = 0;
+    }
+
+  } else if (address == 0x1200) // RESET
+  {
+    z80_log(__FUNCTION__,"RESET = %d, current=%d", value,reset);
+  
+    if (value == 0) {
+      reset = 1;
+    } else {
+
+      z80_pulse_reset();
+      reset = 0;
+      reset_once = 1;
+    }
+  }
+}
+
+unsigned int z80_read_ctrl(unsigned int address) {
+
+  z80_sync();
+
+  if (address == 0x1100) {
+
+    z80_log(__FUNCTION__,"RUNNING = %d ", bus_ack ? 0 : 1);
+    return bus_ack == 1 ? 0 : 1;
+
+  } else if (address == 0x1101) {
+    return 0x00;
+
+  } else if (address == 0x1200) {
+
+    z80_log(__FUNCTION__,"RESET = %d ", reset );
+    return reset;
+
+  } else if (address == 0x1201) {
+    return 0x00;
+  }
+  return 0xFF;
+}
+
+void z80_irq_line(unsigned int value)
+{
+    if (reset_once == 0) return;
+
+    if (value)
+        cpu.IRequest = INT_IRQ;
+    else
+        cpu.IRequest = INT_NONE;
+
+    z80_log(__FUNCTION__,"Interrupt = %d ", value);
+
+}
+
+#if 0
+
+word z80_get_reg(int reg_i) {
+    switch(reg_i) {
+        case 0: return cpu.AF.W; break;
+        case 1: return cpu.BC.W; break;
+        case 2: return cpu.DE.W; break;
+        case 3: return cpu.HL.W; break;
+        case 4: return cpu.IX.W; break;
+        case 5: return cpu.IY.W; break;
+        case 6: return cpu.PC.W; break;
+        case 7: return cpu.SP.W; break;
+    }
+}
+#endif
+
+/********************************************
+ * Z80 Bank
+ ********************************************/
+
+unsigned int zbankreg_mem_r8(unsigned int address)
+{
+      z80_log(__FUNCTION__,"Z80 bank read pointer : %06x", Z80_BANK);
+
+    return Z80_BANK;
+}
+
+static inline void zbankreg_mem_w8(unsigned int value) {
+  Z80_BANK >>= 1;
+  Z80_BANK |= (value & 1) << 8;
+  z80_log(__FUNCTION__,"Z80 bank points to: %06x", Z80_BANK << 15);
+  return;
+}
+
+static inline unsigned int zbank_mem_r8(unsigned int address)
+{
+    address &= 0x7FFF;
+    address |= (Z80_BANK << 15);
+
+    z80_log(__FUNCTION__,"Z80 bank read: %06x", address);
+    return m68k_read_memory_8(address);
+}
+
+static inline void zbank_mem_w8(unsigned int address, unsigned int value) {
+  address &= 0x7FFF;
+  address |= (Z80_BANK << 15);
+
+  z80_log(__FUNCTION__,"Z80 bank write %06x: %02x", address, value);
+  m68k_write_memory_8(address, value);
+
+}
+
+// TODO ??
+/*
+unsigned int zvdp_mem_r8(unsigned int address)
+{
+    if (address >= 0x7F00 && address < 0x7F20)
+        return vdp_mem_r8(address);
+    return 0xFF;
+}
+
+void zvdp_mem_w8(unsigned int address, unsigned int value)
+{
+    if (address >= 0x7F00 && address < 0x7F20)
+        vdp_mem_w8(address, value);
+}
+
+*/
+
+word LoopZ80(register Z80 *R)
+{
+    return 0;
+}
+
+byte RdZ80(register word Addr) {
+
+  if (Addr < 0x4000)
+    return Z80_RAM[Addr & 0x1FFF];
+
+  if (Addr < 0x6000)
+	   return (audio_enabled) ? YM2612Read(zclk + current_timeslice - (cpu.ICount * Z80_FREQ_DIVISOR)) : 0x00;
+
+  z80_log(__FUNCTION__, "addr= %x", Addr);
+
+  if (Addr >= 0x8000)
+    return zbank_mem_r8(Addr);
+
+  z80_log(__FUNCTION__, "addr= %x", Addr);
+
+  return 0xFF;
+}
+
+extern int system_clock;
+
+void WrZ80(register word Addr, register byte Value) {
+
+  // ZRAM & mirror
+  if (Addr < 0x4000) {
+    Z80_RAM[Addr&0x1FFF] = Value;
+    return;
+  }
+
+  // @4000-4003
+  if (Addr < 0x6000) {
+    z80_log("Z80","ZZYM(%x,%x) zk=%d,tgt=%d",Addr&0x3,Value, zclk, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    if (audio_enabled)
+	    YM2612Write(Addr&0x3, Value, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    return;
+  }
+
+  // @6000
+  if (Addr == 0x6000) {
+    zbankreg_mem_w8(Value);
+    return;
+  }
+
+  // @7F11
+  if (Addr ==  0x7F11) {
+    z80_log("Z80","ZZSN zk=%d,tgt=%d", zclk, zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    gwenesis_SN76489_Write(Value,zclk + current_timeslice -(cpu.ICount * Z80_FREQ_DIVISOR) );
+    return;
+  }
+ 
+  z80_log("Z80","WrZ80  %x %x", Addr, Value);
+
+  if (Addr >= 0x8000) {
+    zbank_mem_w8(Addr, Value);
+    return;
+  }
+  z80_log("Z80","WrZ80  %x %x", Addr, Value);
+
+}
+
+
+byte InZ80(register word Port) {return 0;}
+void OutZ80(register word Port, register byte Value) {;}
+void PatchZ80(register Z80 *R) {;}
+void DebugZ80(register Z80 *R) {;}
+
+void gwenesis_z80inst_save_state() {
+
+}
+
+void gwenesis_z80inst_load_state() {
+
+
+}
+
diff --git a/MCUME_pico2/picogen/gwenesis/sound/z80inst.h b/MCUME_pico2/picogen/gwenesis/sound/z80inst.h
new file mode 100755
index 0000000..b891394
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/sound/z80inst.h
@@ -0,0 +1,44 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _Z80_INTERFACE_H_
+#define _Z80_INTERFACE_H_
+
+void z80_write_ctrl(unsigned int address, unsigned int value);
+unsigned int z80_read_ctrl(unsigned int address);
+void z80_start();
+void z80_pulse_reset();
+void z80_execute(unsigned int target);
+void z80_run(int target);
+extern int zclk;
+
+void gwenesis_z80inst_save_state();
+void gwenesis_z80inst_load_state();
+
+void z80_set_memory(unsigned char *buffer);
+
+void z80_write_memory_8(unsigned int address, unsigned int value);
+void z80_write_memory_16(unsigned int address, unsigned int value);
+unsigned int z80_read_memory_16(unsigned int address);
+unsigned int z80_read_memory_8(unsigned int address);
+void z80_irq_line(unsigned int value);
+
+void gwenesis_z80inst_save_state();
+void gwenesis_z80inst_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp.h b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp.h
new file mode 100755
index 0000000..e24bb28
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp.h
@@ -0,0 +1,154 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#ifndef _gwenesis_vdp_H_
+#define _gwenesis_vdp_H_
+
+#pragma once
+
+#define BIT(v, idx) (((v) >> (idx)) & 1)
+#define BITS(v, idx, n) (((v) >> (idx)) & ((1 << (n)) - 1))
+
+// VDP registers
+#define REG0_DISABLE_DISPLAY (gwenesis_vdp_regs[0] & 1)
+#define REG0_HVLATCH BIT(gwenesis_vdp_regs[0], 1)
+#define REG0_LINE_INTERRUPT BIT(gwenesis_vdp_regs[0], 4)
+#define REG1_PAL BIT(gwenesis_vdp_regs[1], 3)
+#define REG1_240_LINE ((gwenesis_vdp_regs[1] & 0x08) >> 3)
+#define REG1_DMA_ENABLED BIT(gwenesis_vdp_regs[1], 4)
+#define REG1_VBLANK_INTERRUPT BIT(gwenesis_vdp_regs[1], 5)
+#define REG1_DISP_ENABLED BIT(gwenesis_vdp_regs[1], 6)
+#define REG2_NAMETABLE_A (BITS(gwenesis_vdp_regs[2], 3, 3) << 13)
+#define REG3_NAMETABLE_W BITS(gwenesis_vdp_regs[3], 1, 5)
+#define REG4_NAMETABLE_B (BITS(gwenesis_vdp_regs[4], 0, 3) << 13)
+//#define REG5_SAT_ADDRESS ((gwenesis_vdp_regs[5] & (mode_h40 ? 0x7E : 0x7F)) << 9)
+//#define REG5_SAT_SIZE (mode_h40 ? (1 << 10) : (1 << 9))
+#define REG5_SAT_ADDRESS ((gwenesis_vdp_regs[5] & ((gwenesis_vdp_regs[12] & 0x01) ? 0x7E : 0x7F)) << 9)
+#define REG5_SAT_SIZE ((gwenesis_vdp_regs[12] & 0x01) ? (1 << 10) : (1 << 9))
+#define REG10_LINE_COUNTER BITS(gwenesis_vdp_regs[10], 0, 8)
+#define REG10_COLUMN_COUNTER BITS(gwenesis_vdp_regs[10], 8, 15)
+#define REG11_HSCROLL_MODE ((gwenesis_vdp_regs[11] & 3))
+#define REG11_VSCROLL_MODE ((gwenesis_vdp_regs[11] & 4) >> 2)
+#define REG12_RS0 (gwenesis_vdp_regs[12] & 0x80) >> 7
+#define REG12_RS1 (gwenesis_vdp_regs[12] & 0x01) >> 0
+#define REG12_MODE_H40 (gwenesis_vdp_regs[12] & 1)
+#define REG13_HSCROLL_ADDRESS (gwenesis_vdp_regs[13] << 10)
+#define REG15_DMA_INCREMENT gwenesis_vdp_regs[15]
+#define REG16_UNUSED1 ((gwenesis_vdp_regs[16] & 0xc0) >> 6)
+#define REG16_VSCROLL_SIZE ((gwenesis_vdp_regs[16] >> 4) & 3)
+#define REG16_UNUSED2 ((gwenesis_vdp_regs[16] & 0x0c) >> 2)
+#define REG16_HSCROLL_SIZE (gwenesis_vdp_regs[16] & 3)
+#define REG17_WINDOW_HPOS BITS(gwenesis_vdp_regs[17], 0, 5)
+#define REG17_WINDOW_RIGHT ((gwenesis_vdp_regs[17] & 0x80) >> 7)
+#define REG18_WINDOW_DOWN ((gwenesis_vdp_regs[0x12] & 0x80) >> 7)
+#define REG18_WINDOW_VPOS BITS(gwenesis_vdp_regs[18], 0, 5)
+#define REG19_DMA_LENGTH (gwenesis_vdp_regs[19] | (gwenesis_vdp_regs[20] << 8))
+#define REG21_DMA_SRCADDR_LOW (gwenesis_vdp_regs[21] | (gwenesis_vdp_regs[22] << 8))
+#define REG23_DMA_SRCADDR_HIGH ((gwenesis_vdp_regs[23] & 0x7F) << 16)
+#define REG23_DMA_TYPE BITS(gwenesis_vdp_regs[23], 6, 2)
+
+//VDP status register
+#define STATUS_FIFO_EMPTY (1 << 9)
+#define STATUS_FIFO_FULL (1 << 8)
+#define STATUS_VIRQPENDING (1 << 7)
+#define STATUS_SPRITEOVERFLOW (1 << 6)
+#define STATUS_SPRITECOLLISION (1 << 5)
+#define STATUS_ODDFRAME (1 << 4)
+#define STATUS_VBLANK (1 << 3)
+#define STATUS_HBLANK (1 << 2)
+#define STATUS_DMAPROGRESS (1 << 1)
+#define STATUS_PAL (1 << 0)
+
+#define VRAM_MAX_SIZE 0x10000    // VRAM maximum size
+#define CRAM_MAX_SIZE 0x40       // CRAM maximum size
+#define VSRAM_MAX_SIZE 0x40      // VSRAM maximum size
+#define SAT_CACHE_MAX_SIZE 0x400 // SAT CACHE maximum size
+#define REG_SIZE 0x20            // REGISTERS total
+#define FIFO_SIZE 0x4            // FIFO maximum size
+
+#define COLOR_3B_TO_8B(c)  (((c) << 5) | ((c) << 2) | ((c) >> 1))
+#define CRAM_R(c)          COLOR_3B_TO_8B(BITS((c), 1, 3))
+#define CRAM_G(c)          COLOR_3B_TO_8B(BITS((c), 5, 3))
+#define CRAM_B(c)          COLOR_3B_TO_8B(BITS((c), 9, 3))
+
+#define MODE_SHI           BITS(gwenesis_vdp_regs[12], 3, 1)
+
+#define SHADOW_COLOR(r,g,b) \
+    do { r >>= 1; g >>= 1; b >>= 1; } while (0)
+#define HIGHLIGHT_COLOR(r,g,b) \
+    do { SHADOW_COLOR(r,g,b); r |= 0x80; g |= 0x80; b |= 0x80; } while(0)
+
+// While we draw the planes, we use bit 0x80 on each pixel to save the
+// high-priority flag, so that we can later prioritize.
+#define PIXATTR_HIPRI        0x80
+#define PIXATTR_LOWPRI       0x00
+#define PIXATTR_SPRITE       0x40
+#define PIXATTR_SPRITE_HIPRI 0xC0
+
+
+// After mixing code, we use free bits 0x80 and 0x40 to indicate the
+// shadow/highlight effect to apply on each pixel. Notice that we use
+// 0x80 to indicate normal drawing and 0x00 to indicate shadowing,
+// which does match exactly the semantic of PIXATTR_HIPRI. This simplifies
+// mixing code quite a bit.
+#define SHI_NORMAL(x)        ((x) | 0x80)
+#define SHI_HIGHLIGHT(x)     ((x) | 0x40)
+#define SHI_SHADOW(x)        ((x) & 0x3F)
+
+#define SHI_IS_SHADOW(x)     (!((x) & 0x80))
+#define SHI_IS_HIGHLIGHT(x)  ((x) & 0x40)
+
+void gwenesis_vdp_reset();
+void gwenesis_vdp_set_hblank();
+void gwenesis_vdp_clear_hblank();
+void gwenesis_vdp_set_vblank();
+void gwenesis_vdp_clear_vblank();
+
+unsigned int gwenesis_vdp_get_reg(int reg);
+void gwenesis_vdp_set_reg(int reg, unsigned char value);
+
+unsigned int gwenesis_vdp_read_memory_8(unsigned int address);
+unsigned int gwenesis_vdp_read_memory_16(unsigned int address);
+
+void gwenesis_vdp_write_memory_8(unsigned int address, unsigned int value);
+void gwenesis_vdp_write_memory_16(unsigned int address, unsigned int value);
+
+void gwenesis_vdp_set_buffers(unsigned char *screen_buffer, unsigned char *scaled_buffer);
+void gwenesis_vdp_set_buffer(uint8_t *ptr_screen_buffer);
+void gwenesis_vdp_get_buffer(uint16_t** ptr_screen_buffer);
+void gwenesis_vdp_render_line(int line);
+
+void gwenesis_vdp_render_config();
+
+unsigned int gwenesis_vdp_get_status();
+void gwenesis_vdp_get_debug_status(char *s);
+unsigned short gwenesis_vdp_get_cram(int index);
+void gwenesis_vdp_get_vram(unsigned char *raw_buffer, int palette);
+void gwenesis_vdp_get_vram_raw(unsigned char *raw_buffer);
+void gwenesis_vdp_get_cram_raw(unsigned char *raw_buffer);
+
+int gwenesis_vdp_vcounter();
+int gwenesis_vdp_hcounter();
+unsigned short gwenesis_vdp_hvcounter();
+
+void gwenesis_vdp_gfx_save_state();
+void gwenesis_vdp_gfx_load_state();
+void gwenesis_vdp_mem_save_state();
+void gwenesis_vdp_mem_load_state();
+
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_gfx.c b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_gfx.c
new file mode 100755
index 0000000..5fa7edf
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_gfx.c
@@ -0,0 +1,1038 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include <pico.h>
+
+#include "../cpus/M68K/m68k.h"
+#include "gwenesis_vdp.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../savestate/gwenesis_savestate.h"
+
+//#include <assert.h>
+
+#pragma GCC optimize("Ofast")
+
+extern unsigned char __aligned(4) VRAM[];
+
+extern unsigned short CRAM[]; // CRAM - Palettes
+extern unsigned char SAT_CACHE[]__attribute__((aligned(4))); // Sprite cache
+extern unsigned char gwenesis_vdp_regs[]; // Registers
+
+extern unsigned short VSRAM[]; // VSRAM - Scrolling
+
+// Define screen buffers: original and scaled for host RGB
+//unsigned char *screen, *scaled_screen;
+
+// Define SCREEN buffers for embedded 565 format
+static uint8_t* screen_buffer_line = 0;
+
+//static unsigned short *screen_buffer=0;
+
+// Overflow is the maximum size we can draw outside to avoid
+// wasting time and code in clipping. The maximum object is a 4x4 sprite,
+// so 32 pixels (on both side) is enough.
+
+#define PIX_OVERFLOW (32)
+static uint8_t render_buffer[GWENESIS_SCREEN_WIDTH + PIX_OVERFLOW * 2];
+static uint8_t sprite_buffer[GWENESIS_SCREEN_WIDTH + PIX_OVERFLOW * 2];
+
+// Define VIDEO MODE
+static int mode_h40;
+int mode_pal;
+
+// Define screen W/H
+int screen_width;
+int screen_height;
+
+int gwenesis_H32upscaler;
+
+int sprite_overflow;
+bool sprite_collision;
+
+// Window Plane and A plane spearation
+static int base_w;
+static int PlanA_firstcol;
+static int PlanA_lastcol;
+
+static int Window_firstcol;
+static int Window_lastcol;
+
+// 16 bits access to VRAM
+#define FETCH16VRAM(A)  ( (VRAM[(A)+1]) | (VRAM[(A)] << 8) )
+
+#define VDP_GFX_DISABLE_LOGGING 1
+
+#if !VDP_GFX_DISABLE_LOGGING
+#include <stdarg.h>
+void vdpg_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%03x hc:%03x", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define vdpg_log(...)
+#endif
+/******************************************************************************
+ *
+ *  set screen buffers in which the rendering occurs
+ *  Set original and scaled screen buffer for host
+ *
+ ******************************************************************************/
+//host
+/*
+void gwenesis_vdp_set_buffers(unsigned char *screen_buffer, unsigned char *scaled_buffer)
+{
+    screen = screen_buffer;
+    scaled_screen = scaled_buffer;
+}
+*/
+//embedded
+void gwenesis_vdp_set_buffer(uint8_t* ptr_screen_buffer) {
+    screen_buffer_line = ptr_screen_buffer;
+    //screen_buffer = ptr_screen_buffer;
+}
+
+void gwenesis_vdp_get_buffer(uint16_t** ptr_screen_buffer) {
+    *ptr_screen_buffer = (uint16_t *)&render_buffer[PIX_OVERFLOW];
+    //screen_buffer = ptr_screen_buffer;
+}
+
+/******************************************************************************
+ *
+ *  Draw  Sprite character /8pixels in row
+ *  without checking overdraw for pixels collision detection
+ *  with Horizontal flip variation
+ *  for Shadow/highlight :
+ *    draw in fresh line buffer using draw_pattern_xxfliph_sprite(..)
+ *  otherwise:
+ *   draw over dirty planes using draw_pattern_xxfliph_sprite_over_planes(..)
+ *
+ ******************************************************************************/
+
+#define PIX0(P) ( ((P) & 0x000000F0 ) >>   4 )
+#define PIX1(P) ( ((P) & 0x0000000F ) >>   0 )
+#define PIX2(P) ( ((P) & 0x0000F000 ) >>  12 )
+#define PIX3(P) ( ((P) & 0x00000F00 ) >>   8 )
+#define PIX4(P) ( ((P) & 0x00F00000 ) >>  20 )
+#define PIX5(P) ( ((P) & 0x000F0000 ) >>  16 )
+#define PIX6(P) ( ((P) & 0xF0000000 ) >>  28 )
+#define PIX7(P) ( ((P) & 0x0F000000 ) >>  24 )
+
+static inline __attribute__((always_inline))
+void draw_pattern_nofliph_sprite(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /*  not transparent pixel to write AND not already a sprite*/
+    if (PIX0(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX0(p);
+    if (PIX1(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX1(p);
+    if (PIX2(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX2(p);
+    if (PIX3(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX3(p);
+    if (PIX4(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX4(p);
+    if (PIX5(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX5(p);
+    if (PIX6(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX6(p);
+    if (PIX7(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX7(p);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_fliph_sprite(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /*  not transparent pixel to write AND not already a sprite*/
+    if (PIX7(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX7(p);
+    if (PIX6(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX6(p);
+    if (PIX5(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX5(p);
+    if (PIX4(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX4(p);
+    if (PIX3(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX3(p);
+    if (PIX2(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX2(p);
+    if (PIX1(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX1(p);
+    if (PIX0(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX0(p);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_nofliph_sprite_over_planes(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /* High priority */
+    if (attrs & PIXATTR_HIPRI) {
+        /*  not transparent pixel to write AND not already a sprite*/
+        if (PIX0(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX7(p);
+    }
+    /* Low priority */
+    else {
+        /*  not transparent pixel to write AND not already a sprite or higher priority*/
+        if (PIX0(p) && (scr[0] & PIXATTR_SPRITE_HIPRI) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_SPRITE_HIPRI) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_SPRITE_HIPRI) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_SPRITE_HIPRI) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_SPRITE_HIPRI) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_SPRITE_HIPRI) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_SPRITE_HIPRI) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_SPRITE_HIPRI) == 0) scr[7] = attrs | PIX7(p);
+    }
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_fliph_sprite_over_planes(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    /* High priority */
+    if (attrs & PIXATTR_HIPRI) {
+        /*  not transparent pixel to write AND not already a sprite*/
+        if (PIX7(p) && (scr[0] & PIXATTR_SPRITE) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_SPRITE) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_SPRITE) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_SPRITE) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_SPRITE) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_SPRITE) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_SPRITE) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_SPRITE) == 0) scr[7] = attrs | PIX0(p);
+    }
+    /* Low priority */
+    else {
+        /*  not transparent pixel to write AND not already a sprite or higher priority*/
+        if (PIX7(p) && (scr[0] & PIXATTR_SPRITE_HIPRI) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_SPRITE_HIPRI) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_SPRITE_HIPRI) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_SPRITE_HIPRI) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_SPRITE_HIPRI) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_SPRITE_HIPRI) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_SPRITE_HIPRI) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_SPRITE_HIPRI) == 0) scr[7] = attrs | PIX0(p);
+    }
+}
+
+/******************************************************************************
+ *
+ *  Draw  characters/8pixels in row
+ *  without checking overdraw for pixels collision detection
+ *  with Horizontal flip variation for plane A & B
+ *
+ ******************************************************************************/
+
+
+static inline __attribute__((always_inline)) void
+draw_pattern_nofliph_planeB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    const uint8_t back = gwenesis_vdp_regs[7];
+
+    if (p == 0) {
+        scr[0] = back;
+        scr[1] = back;
+        scr[2] = back;
+        scr[3] = back;
+        scr[4] = back;
+        scr[5] = back;
+        scr[6] = back;
+        scr[7] = back;
+
+        return;
+    }
+
+    scr[0] = PIX0(p) ? attrs | (PIX0(p)) : back;
+    scr[1] = PIX1(p) ? attrs | (PIX1(p)) : back;
+    scr[2] = PIX2(p) ? attrs | (PIX2(p)) : back;
+    scr[3] = PIX3(p) ? attrs | (PIX3(p)) : back;
+    scr[4] = PIX4(p) ? attrs | (PIX4(p)) : back;
+    scr[5] = PIX5(p) ? attrs | (PIX5(p)) : back;
+    scr[6] = PIX6(p) ? attrs | (PIX6(p)) : back;
+    scr[7] = PIX7(p) ? attrs | (PIX7(p)) : back;
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_fliph_planeB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    const uint8_t back = gwenesis_vdp_regs[7];
+    if (p == 0) {
+        scr[0] = back;
+        scr[1] = back;
+        scr[2] = back;
+        scr[3] = back;
+        scr[4] = back;
+        scr[5] = back;
+        scr[6] = back;
+        scr[7] = back;
+
+        return;
+    }
+
+    scr[0] = PIX7(p) ? attrs | (PIX7(p)) : back;
+    scr[1] = PIX6(p) ? attrs | (PIX6(p)) : back;
+    scr[2] = PIX5(p) ? attrs | (PIX5(p)) : back;
+    scr[3] = PIX4(p) ? attrs | (PIX4(p)) : back;
+    scr[4] = PIX3(p) ? attrs | (PIX3(p)) : back;
+    scr[5] = PIX2(p) ? attrs | (PIX2(p)) : back;
+    scr[6] = PIX1(p) ? attrs | (PIX1(p)) : back;
+    scr[7] = PIX0(p) ? attrs | (PIX0(p)) : back;
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_nofliph_planeAoverB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    if (attrs & PIXATTR_HIPRI) {
+        if (PIX0(p)) scr[0] = attrs | (PIX0(p));
+        if (PIX1(p)) scr[1] = attrs | (PIX1(p));
+        if (PIX2(p)) scr[2] = attrs | (PIX2(p));
+        if (PIX3(p)) scr[3] = attrs | (PIX3(p));
+        if (PIX4(p)) scr[4] = attrs | (PIX4(p));
+        if (PIX5(p)) scr[5] = attrs | (PIX5(p));
+        if (PIX6(p)) scr[6] = attrs | (PIX6(p));
+        if (PIX7(p)) scr[7] = attrs | (PIX7(p));
+    }
+    else {
+        if (PIX0(p) && (scr[0] & PIXATTR_HIPRI) == 0) scr[0] = attrs | PIX0(p);
+        if (PIX1(p) && (scr[1] & PIXATTR_HIPRI) == 0) scr[1] = attrs | PIX1(p);
+        if (PIX2(p) && (scr[2] & PIXATTR_HIPRI) == 0) scr[2] = attrs | PIX2(p);
+        if (PIX3(p) && (scr[3] & PIXATTR_HIPRI) == 0) scr[3] = attrs | PIX3(p);
+        if (PIX4(p) && (scr[4] & PIXATTR_HIPRI) == 0) scr[4] = attrs | PIX4(p);
+        if (PIX5(p) && (scr[5] & PIXATTR_HIPRI) == 0) scr[5] = attrs | PIX5(p);
+        if (PIX6(p) && (scr[6] & PIXATTR_HIPRI) == 0) scr[6] = attrs | PIX6(p);
+        if (PIX7(p) && (scr[7] & PIXATTR_HIPRI) == 0) scr[7] = attrs | PIX7(p);
+    }
+}
+
+static inline __attribute__((always_inline)) void
+draw_pattern_fliph_planeAoverB(uint8_t* scr, uint32_t p, uint8_t attrs) {
+    if (p == 0) return;
+
+    if (attrs & PIXATTR_HIPRI) {
+        if (PIX7(p)) scr[0] = attrs | PIX7(p);
+        if (PIX6(p)) scr[1] = attrs | PIX6(p);
+        if (PIX5(p)) scr[2] = attrs | PIX5(p);
+        if (PIX4(p)) scr[3] = attrs | PIX4(p);
+        if (PIX3(p)) scr[4] = attrs | PIX3(p);
+        if (PIX2(p)) scr[5] = attrs | PIX2(p);
+        if (PIX1(p)) scr[6] = attrs | PIX1(p);
+        if (PIX0(p)) scr[7] = attrs | PIX0(p);
+    }
+    else {
+        if (PIX7(p) && (scr[0] & PIXATTR_HIPRI) == 0) scr[0] = attrs | PIX7(p);
+        if (PIX6(p) && (scr[1] & PIXATTR_HIPRI) == 0) scr[1] = attrs | PIX6(p);
+        if (PIX5(p) && (scr[2] & PIXATTR_HIPRI) == 0) scr[2] = attrs | PIX5(p);
+        if (PIX4(p) && (scr[3] & PIXATTR_HIPRI) == 0) scr[3] = attrs | PIX4(p);
+        if (PIX3(p) && (scr[4] & PIXATTR_HIPRI) == 0) scr[4] = attrs | PIX3(p);
+        if (PIX2(p) && (scr[5] & PIXATTR_HIPRI) == 0) scr[5] = attrs | PIX2(p);
+        if (PIX1(p) && (scr[6] & PIXATTR_HIPRI) == 0) scr[6] = attrs | PIX1(p);
+        if (PIX0(p) && (scr[7] & PIXATTR_HIPRI) == 0) scr[7] = attrs | PIX0(p);
+    }
+}
+
+/******************************************************************************
+ *
+ *  Draw  characters/8pixels in row
+ *  with/without checking overdraw for pixels collision detection
+ *  used for sprites and planes drawing
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void draw_pattern_sprite(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5; //name * 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // //unsigned int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+    // uint8_t attrs = (pat_palette << 4) | ((name & 0x8000) ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8) + PIXATTR_SPRITE;
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    // unsigned int  pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_sprite(scr, pattern, attrs);
+    else
+        draw_pattern_nofliph_sprite(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_sprite_over_planes(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5 ; //* 32;
+    // int pat_palette = BITS(name, 13, 2);
+    // int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+    // uint8_t attrs = (pat_palette << 4) | (is_pat_pri ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    //uint8_t attrs = ( (name & 0x6000 ) >> 9 ) | ((name & 0x8000) ? PIXATTR_SPRITE_HIPRI : PIXATTR_SPRITE);
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8) + PIXATTR_SPRITE;
+    //uint8_t attrs = ( (name >>9) & 0x70 ) | PIXATTR_SPRITE;
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_sprite_over_planes(scr, pattern, attrs);
+    else
+        draw_pattern_nofliph_sprite_over_planes(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_planeB(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name  << 5; // * 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // unsigned int is_pat_pri = name & 0x8000;
+    //uint8_t *pattern = VRAM + pat_addr;
+
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8);
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    //  if ((*(unsigned int *)pattern) == 0 ) return;
+    // uint8_t *pattern = VRAM + ((name << 5) & 0xFFFF); //) pat_addr;
+    //uint32_t pattern = VRAM[(name & 0x07FF) << 5]; //) pat_addr;
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_planeB(scr, pattern, attrs);
+
+    else
+        draw_pattern_nofliph_planeB(scr, pattern, attrs);
+}
+
+static inline __attribute__((always_inline))
+void draw_pattern_planeA(uint8_t* scr, uint16_t name, int paty) {
+    // uint16_t pat_addr = name << 5; //* 32;
+    // uint8_t pat_palette = BITS(name, 13, 2);
+    // unsigned int is_pat_pri = name & 0x8000;
+    // uint8_t *pattern = VRAM + pat_addr;
+
+    const uint8_t attrs = ((name & 0x6000) >> 9) + ((name & 0x8000) >> 8);
+
+
+    unsigned int pattern;
+
+    // Vertical flip ?
+    // if (name & 0x1000)
+    //   pattern += (7 - paty) * 4;
+    // else
+    //   pattern += paty * 4;
+
+    // Vertical flip ?
+    if (name & 0x1000)
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul((7 - paty), 4)); //) pat_addr;
+    else
+        pattern = *(unsigned int *)(VRAM + ((name & 0x07FF) << 5) + __fast_mul(paty, 4));
+
+    // Horizontal flip ?
+    if (name & 0x0800)
+        draw_pattern_fliph_planeAoverB(scr, pattern, attrs);
+
+    else
+        draw_pattern_nofliph_planeAoverB(scr, pattern, attrs);
+}
+
+static uint16_t ntwidth_x2;
+static uint16_t ntw_mask, nth_mask;
+
+/******************************************************************************
+ *
+ *  Return the Horizontal scrolling
+ *
+ ******************************************************************************/
+
+static inline __attribute__((always_inline))
+unsigned int get_hscroll_vram(int line) {
+    switch (REG11_HSCROLL_MODE) {
+        case 0: // Full screen scrolling
+            return REG13_HSCROLL_ADDRESS;
+        case 1: // First 8 lines
+            return REG13_HSCROLL_ADDRESS + (line & 7) * 4;
+        case 2: // Every row
+            return REG13_HSCROLL_ADDRESS + (line & ~7) * 4;
+        case 3: // Every line
+            return REG13_HSCROLL_ADDRESS + line * 4;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render PLANE B on screen line
+ *
+ ******************************************************************************/
+//__attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_line_b(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    const unsigned int ntaddr = REG4_NAMETABLE_B;
+    uint16_t scrollx = FETCH16VRAM(get_hscroll_vram(line) + 2) & 0x3FF;
+    const uint16_t* vsram = &VSRAM[1];
+    const uint8_t* end = scr + screen_width;
+
+    //bool column_scrolling = BIT(gwenesis_vdp_regs[11], 2);
+    const bool column_scrolling = gwenesis_vdp_regs[11] & 0x4;
+
+    // Invert horizontal scrolling (because it goes right, but we need to offset
+    // of the first screen pixel)
+    scrollx = -scrollx;
+    uint8_t col = (scrollx >> 3) & ntw_mask;
+    const uint8_t patx = scrollx & 7;
+
+    unsigned int numcell = 0;
+    scr -= patx;
+    while (scr < end) {
+        // Calculate vertical scrolling for the current line
+        uint16_t scrolly = *vsram + line;
+        uint8_t row = (scrolly >> 3) & nth_mask;
+        uint8_t paty = scrolly & 7;
+
+        // unsigned int nt = ntaddr + row * (2 * ntwidth);
+        unsigned int nt = ntaddr + row * ntwidth_x2;
+
+        draw_pattern_planeB(scr, FETCH16VRAM(nt + __fast_mul(col , 2)), paty);
+        col = (col + 1) & ntw_mask;
+        scr += 8;
+        numcell++;
+
+        // If per-column scrolling is active, increment VSRAM pointer
+        if (column_scrolling && (numcell & 1) == 0)
+            vsram += 2;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render PLANE A and Window on screen line
+ *
+ ******************************************************************************/
+//_attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_line_aw(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    unsigned int ntaddr = REG2_NAMETABLE_A;
+    uint16_t scrollx = FETCH16VRAM(get_hscroll_vram(line) + 0) & 0x3FF;
+    uint16_t* vsram = &VSRAM[0];
+
+    // Check if we are in the window region only
+    // if it's the case, we cancel the plane A drawing
+    int Window_line = REG18_WINDOW_VPOS * 8;
+    //bool window_down = BIT(gwenesis_vdp_regs[18], 7);
+    int window_down = gwenesis_vdp_regs[18] & 0x80;
+
+    int PlanA_first = PlanA_firstcol;
+    int PlanA_last = PlanA_lastcol;
+    int Window_last = Window_lastcol;
+    int Window_first = Window_firstcol;
+
+    if (window_down) {
+        if (line > Window_line) {
+            PlanA_first = PlanA_last = 0;
+            Window_last = screen_width;
+            Window_first = 0;
+        }
+    }
+    else {
+        if (line < Window_line) {
+            PlanA_first = PlanA_last = 0;
+            Window_last = screen_width;
+            Window_first = 0;
+        }
+    }
+
+    // First draw A plane
+    uint8_t* pos = scr + PlanA_first; // scr + screen_width;
+    uint8_t* end = scr + PlanA_last; // scr + screen_width
+
+    //bool column_scrolling = BIT(gwenesis_vdp_regs[11], 2);
+    const unsigned int column_scrolling = gwenesis_vdp_regs[11] & 0x4;
+
+    // Invert horizontal scrolling (because it goes right, but we need to offset
+    // of the first screen pixel)
+    scrollx = -scrollx;
+    uint8_t col = (scrollx >> 3) & ntw_mask;
+    uint8_t patx = scrollx & 7;
+
+    unsigned int numcell = 0;
+    pos -= patx;
+    while (pos < end) {
+        // Calculate vertical scrolling for the current line
+        uint16_t scrolly = *vsram + line;
+        uint8_t row = (scrolly >> 3) & nth_mask;
+        uint8_t paty = scrolly & 7;
+
+        // unsigned int nt = ntaddr + row * (2 * ntwidth);
+        unsigned int nt = ntaddr + row * ntwidth_x2;
+
+        draw_pattern_planeA(pos, FETCH16VRAM(nt + __fast_mul(col , 2)), paty);
+
+        col = (col + 1) & ntw_mask;
+        pos += 8;
+        numcell++;
+
+        // If per-column scrolling is active, increment VSRAM pointer
+        if (column_scrolling && (numcell & 1) == 0)
+            vsram += 2;
+    }
+
+    // Second Draw Window Plane
+    int row = line >> 3;
+    int paty = line & 7;
+    //int wdwidth = (screen_width == 320 ? 64 : 32);
+    //unsigned int nt = base_w + row * 2 * wdwidth + Window_first / 4;
+
+    int wdwidth_x2 = (screen_width == 320 ? 128 : 64);
+
+    unsigned int nt = base_w + row * wdwidth_x2 + Window_first / 4;
+
+    #pragma GCC unroll(64)
+    for (int i = Window_first / 8; i < Window_last / 8; ++i) {
+        draw_pattern_planeA(end, FETCH16VRAM(nt), paty);
+        nt += 2;
+        end += 8;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render SPRITES on screen line
+ *
+ ******************************************************************************/
+
+//__attribute__((optimize("unroll-loops")))
+static inline __attribute__((always_inline))
+void draw_sprites_over_planes(int line) {
+    uint8_t* scr = &render_buffer[PIX_OVERFLOW];
+
+    //    scr = screen_buffer_line;
+
+    // uint8_t mask = mode_h40 ? 0x7E : 0x7F;
+    // uint8_t *start_table = VRAM + ((gwenesis_vdp_regs[5] & mask) << 9);
+
+    uint8_t* start_table = VRAM + REG5_SAT_ADDRESS;
+
+    // This is both the size of the table as seen by the VDP
+    // *and* the maximum number of sprites that are processed
+    // (important in case of infinite loops in links).
+    const int SPRITE_TABLE_SIZE = (screen_width == 320) ? 80 : 64;
+    const int MAX_SPRITES_PER_LINE = (screen_width == 320) ? 20 : 16;
+    const int MAX_PIXELS_PER_LINE = (screen_width == 320) ? 320 : 256;
+
+    bool masking = false, one_sprite_nonzero = false; // overdraw = false;
+    int sidx = 0, num_sprites = 0, num_pixels = 0;
+
+    for (int i = 0; (i < SPRITE_TABLE_SIZE) && sidx < (SPRITE_TABLE_SIZE); ++i) {
+        uint8_t* table = start_table + __fast_mul(sidx, 8);
+        uint8_t* cache = SAT_CACHE + __fast_mul(sidx, 8);
+        //uint8_t *cache = start_table + sidx*8;
+
+
+        int sy = ((cache[0] & 0x3) << 8) | cache[1];
+        int sx = ((table[6] & 0x3) << 8) | table[7];
+        uint16_t name = (table[4] << 8) | table[5];
+
+
+        int sh = BITS(cache[2], 0, 2) + 1;
+        int link = BITS(cache[3], 0, 7);
+
+        int isflipv = table[4] & 0x10;
+        int isfliph = table[4] & 0x8;
+
+        int sw = BITS(table[2], 2, 2) + 1;
+
+        sy -= 128;
+        if ((line >= sy) && (line < sy + __fast_mul(sh, 8))) {
+            // Sprite masking: a sprite on column 0 masks
+            // any lower-priority sprite, but with the following conditions
+            //   * it only works from the second visible sprite on each line
+            //   * if the previous line had a sprite pixel overflow, it
+            //     works even on the first sprite
+            // Notice that we need to continue parsing the table after masking
+            // to see if we reach a pixel overflow (because it would affect masking
+            // on next line).
+            if (sx == 0) {
+                if (one_sprite_nonzero || (sprite_overflow == line - 1))
+                    masking = true;
+            }
+            else
+                one_sprite_nonzero = true;
+
+            int row = (line - sy) >> 3;
+            int paty = (line - sy) & 7;
+            if (isflipv)
+                row = sh - row - 1;
+
+            sx -= 128;
+            if ((sx > (__fast_mul(-sw, 8))) && (sx < screen_width) && !masking) {
+                name += row;
+
+                if (isfliph) {
+                    name += sh * (sw - 1);
+
+                    for (int p = 0; (p < sw) && (num_pixels < MAX_PIXELS_PER_LINE); p++) {
+                        draw_pattern_sprite_over_planes(scr + sx + __fast_mul(p, 8), name, paty);
+                        name -= sh;
+                        num_pixels += 8;
+                    }
+                }
+                else {
+                    for (int p = 0; (p < sw) && (num_pixels < MAX_PIXELS_PER_LINE); p++) {
+                        draw_pattern_sprite_over_planes(scr + sx + __fast_mul(p, 8), name, paty);
+                        name += sh;
+                        num_pixels += 8;
+                    }
+                }
+            }
+            else
+                num_pixels += sw * 8;
+
+            if (num_pixels >= MAX_PIXELS_PER_LINE) {
+                sprite_overflow = line;
+                break;
+            }
+            if (++num_sprites >= MAX_SPRITES_PER_LINE)
+                break;
+        }
+
+        if (link == 0) break;
+        sidx = link;
+    }
+
+    //  if (overdraw)
+    //      sprite_collision = true;
+}
+
+static inline __attribute__((always_inline))
+void draw_sprites(int line) {
+    uint8_t* scr = &sprite_buffer[PIX_OVERFLOW];
+
+
+    //    scr = screen_buffer_line; //&sprite_buffer[PIX_OVERFLOW];
+
+    // uint8_t mask = mode_h40 ? 0x7E : 0x7F;
+    // uint8_t *start_table = VRAM + ((gwenesis_vdp_regs[5] & mask) << 9);
+
+    uint8_t* start_table = VRAM + REG5_SAT_ADDRESS;
+
+    // This is both the size of the table as seen by the VDP
+    // *and* the maximum number of sprites that are processed
+    // (important in case of infinite loops in links).
+    const int SPRITE_TABLE_SIZE = (screen_width == 320) ? 80 : 64;
+    const int MAX_SPRITES_PER_LINE = (screen_width == 320) ? 20 : 16;
+    const int MAX_PIXELS_PER_LINE = (screen_width == 320) ? 320 : 256;
+
+    bool masking = false, one_sprite_nonzero = false; // overdraw = false;
+    int sidx = 0, num_sprites = 0, num_pixels = 0;
+
+
+    for (int i = 0; i < SPRITE_TABLE_SIZE && sidx < SPRITE_TABLE_SIZE; ++i) {
+        uint8_t* table = start_table + __fast_mul(sidx, 8);
+        uint8_t* cache = start_table + __fast_mul(sidx, 8);
+
+        //uint8_t *cache = SAT_CACHE + sidx * 8;
+
+        int sy = ((cache[0] & 0x3) << 8) | cache[1];
+        int sx = ((table[6] & 0x3) << 8) | table[7];
+        uint16_t name = (table[4] << 8) | table[5];
+
+        int sh = BITS(cache[2], 0, 2) + 1;
+        int link = BITS(cache[3], 0, 7);
+
+        int isflipv = table[4] & 0x10;
+        int isfliph = table[4] & 0x8;
+
+        int sw = BITS(table[2], 2, 2) + 1;
+
+        sy -= 128;
+        if (line >= sy && line < sy + __fast_mul(sh, 8)) {
+            // Sprite masking: a sprite on column 0 masks
+            // any lower-priority sprite, but with the following conditions
+            //   * it only works from the second visible sprite on each line
+            //   * if the previous line had a sprite pixel overflow, it
+            //     works even on the first sprite
+            // Notice that we need to continue parsing the table after masking
+            // to see if we reach a pixel overflow (because it would affect masking
+            // on next line).
+            if (sx == 0) {
+                if (one_sprite_nonzero || sprite_overflow == line - 1)
+                    masking = true;
+            }
+            else
+                one_sprite_nonzero = true;
+
+            int row = (line - sy) >> 3;
+            int paty = (line - sy) & 7;
+            if (isflipv)
+                row = sh - row - 1;
+
+            sx -= 128;
+            if (sx > -__fast_mul(sw, 8) && sx < screen_width && !masking) {
+                name += row;
+
+                if (isfliph) {
+                    name += sh * (sw - 1);
+                    for (int p = 0; p < sw && num_pixels < MAX_PIXELS_PER_LINE; p++) {
+                        draw_pattern_sprite(scr + sx + __fast_mul(p, 8), name, paty);
+                        name -= sh;
+                        num_pixels += 8;
+                    }
+                }
+                else {
+                    for (int p = 0; p < sw && num_pixels < MAX_PIXELS_PER_LINE; p++) {
+                        draw_pattern_sprite(scr + sx + __fast_mul(p, 8), name, paty);
+                        name += sh;
+                        num_pixels += 8;
+                    }
+                }
+            }
+            else
+                num_pixels += __fast_mul(sw, 8);
+
+            if (num_pixels >= MAX_PIXELS_PER_LINE) {
+                sprite_overflow = line;
+                break;
+            }
+            if (++num_sprites >= MAX_SPRITES_PER_LINE)
+                break;
+        }
+
+        if (link == 0)
+            break;
+        sidx = link;
+    }
+
+    //  if (overdraw)
+    //      sprite_collision = true;
+}
+
+/******************************************************************************
+ *
+ *  Parse PLANE A/B size,scrolling at the start of image rendering
+ *
+ ******************************************************************************/
+//static unsigned short current_line[320];
+
+void __time_critical_func(gwenesis_vdp_render_config)() {
+    mode_h40 = REG12_MODE_H40;
+    mode_pal = REG1_PAL;
+
+    int ntwidth = BITS(gwenesis_vdp_regs[16], 0, 2);
+    int ntheight = BITS(gwenesis_vdp_regs[16], 4, 2);
+    ntwidth = __fast_mul((ntwidth + 1), 32);
+    ntheight = __fast_mul((ntheight + 1), 32);
+    ntw_mask = ntwidth - 1;
+    nth_mask = ntheight - 1;
+    ntwidth_x2 = ntwidth * 2;
+
+    // Window & A planes separation
+
+    if (mode_h40)
+        base_w = ((REG3_NAMETABLE_W & 0x1e) << 11);
+    else
+        base_w = ((REG3_NAMETABLE_W & 0x1f) << 11);
+
+
+    bool window_right = BIT(gwenesis_vdp_regs[17], 7);
+
+    // int window_is_bugged = 0;
+    PlanA_firstcol = 0;
+    PlanA_lastcol = screen_width;
+
+    Window_firstcol = 0;
+    Window_lastcol = 0;
+
+    if (window_right) {
+        Window_firstcol = REG17_WINDOW_HPOS * 16;
+        Window_lastcol = screen_width;
+
+        if (Window_firstcol > Window_lastcol)
+            Window_firstcol = Window_lastcol;
+
+        PlanA_firstcol = 0;
+        PlanA_lastcol = Window_firstcol;
+    }
+    else {
+        Window_firstcol = 0;
+        Window_lastcol = REG17_WINDOW_HPOS * 16;
+        if (Window_lastcol > screen_width)
+            Window_lastcol = screen_width;
+
+        PlanA_firstcol = Window_lastcol;
+        PlanA_lastcol = screen_width;
+        // if (Window_lastcol != 0)
+        //      window_is_bugged = 1;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Render a line on screen
+ *  Get selected line and render it on screen processing each plane.
+ *
+ ******************************************************************************/
+
+void gwenesis_vdp_render_line(int line) {
+    uint8_t* line_buffer = &screen_buffer_line[__fast_mul(line, screen_width)];
+    mode_h40 = REG12_MODE_H40;
+    //mode_pal = REG1_PAL;
+
+    vdpg_log(__FUNCTION__, ": %3d", line);
+
+    //unsigned int line = scan_line;
+    // if (line == 0) gwenesis_vdp_render_config();
+
+    // interlace mode not implemented
+    if (BITS(gwenesis_vdp_regs[12], 1, 2) != 0)
+        return;
+
+    if (line >= (REG1_PAL ? 240 : 224))
+        return;
+
+    // Disable display >> black SCREEN
+    if (REG0_DISABLE_DISPLAY) {
+        memset(line_buffer, 0, screen_width);
+        return;
+    }
+
+    // Display is not enabled. fill with background colour
+    if (REG1_DISP_ENABLED == 0) {
+        memset(line_buffer, 0, screen_width);
+        return;
+    }
+
+
+    const uint8_t* pb = &render_buffer[PIX_OVERFLOW];
+    uint8_t* ps = &sprite_buffer[PIX_OVERFLOW];
+
+    if (MODE_SHI)
+        memset(ps, 0, GWENESIS_SCREEN_WIDTH);
+
+    draw_line_b(line);
+    draw_line_aw(line);
+
+    /* Mode Highlight/shadow is enabled */
+    if (MODE_SHI) {
+        draw_sprites(line);
+
+        for (int x = 0; x < screen_width; x++) {
+            const uint8_t plane = pb[x];
+            const uint8_t sprite = ps[x];
+
+            if ((plane & 0xC0) < (sprite & 0xC0)) {
+                switch (sprite & 0x3F) {
+                    // Palette=3, Sprite=14 :> draw plane, force highlight
+                    case 0x3E:
+                        line_buffer[x] = 0x8410 | plane >> 1;
+                        break;
+                    // Palette=3, Sprite=15 :> draw plane, force shadow
+                    case 0x3F:
+                        line_buffer[x] = plane >> 1;
+                        break;
+                    // draw sprite, normal
+                    default:
+                        line_buffer[x] = sprite;
+                        break;
+                }
+            }
+            else {
+                line_buffer[x] = plane;
+            }
+        }
+
+        /* Normal mode*/
+    }
+    else {
+        draw_sprites_over_planes(line);
+        memcpy(line_buffer, pb, screen_width);
+    }
+}
+
+void gwenesis_vdp_gfx_save_state() {
+    /*
+    SaveState* state;
+    state = saveGwenesisStateOpenForWrite("vdp_gfx");
+    saveGwenesisStateSetBuffer(state, "render_buffer", render_buffer, sizeof(render_buffer));
+    saveGwenesisStateSetBuffer(state, "sprite_buffer", sprite_buffer, sizeof(sprite_buffer));
+    saveGwenesisStateSet(state, "mode_h40", mode_h40);
+    saveGwenesisStateSet(state, "mode_pal", mode_pal);
+    saveGwenesisStateSet(state, "screen_width", screen_width);
+    saveGwenesisStateSet(state, "screen_height", screen_height);
+    saveGwenesisStateSet(state, "sprite_overflow", sprite_overflow);
+    saveGwenesisStateSet(state, "sprite_collision", sprite_collision);
+    saveGwenesisStateSet(state, "base_w", base_w);
+    saveGwenesisStateSet(state, "PlanA_firstcol", PlanA_firstcol);
+    saveGwenesisStateSet(state, "PlanA_lastcol", PlanA_lastcol);
+    saveGwenesisStateSet(state, "Window_firstcol", Window_firstcol);
+    saveGwenesisStateSet(state, "Window_lastcol", Window_lastcol);
+    */
+}
+
+void gwenesis_vdp_gfx_load_state() {
+    /*
+      SaveState* state = saveGwenesisStateOpenForRead("vdp_gfx");
+      saveGwenesisStateGetBuffer(state, "render_buffer", render_buffer, sizeof(render_buffer));
+      saveGwenesisStateGetBuffer(state, "sprite_buffer", sprite_buffer, sizeof(sprite_buffer));
+      mode_h40 = saveGwenesisStateGet(state, "mode_h40");
+      mode_pal = saveGwenesisStateGet(state, "mode_pal");
+      screen_width = saveGwenesisStateGet(state, "screen_width");
+      screen_height = saveGwenesisStateGet(state, "screen_height");
+      sprite_overflow = saveGwenesisStateGet(state, "sprite_overflow");
+      sprite_collision = saveGwenesisStateGet(state, "sprite_collision");
+      base_w = saveGwenesisStateGet(state, "base_w");
+      PlanA_firstcol = saveGwenesisStateGet(state, "PlanA_firstcol");
+      PlanA_lastcol = saveGwenesisStateGet(state, "PlanA_lastcol");
+      Window_firstcol = saveGwenesisStateGet(state, "Window_firstcol");
+      Window_lastcol = saveGwenesisStateGet(state, "Window_lastcol");
+      */
+}
diff --git a/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_mem.c b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_mem.c
new file mode 100755
index 0000000..7860e3f
--- /dev/null
+++ b/MCUME_pico2/picogen/gwenesis/vdp/gwenesis_vdp_mem.c
@@ -0,0 +1,909 @@
+/*
+Gwenesis : Genesis & megadrive Emulator.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation, either version 3 of the License, or (at your option) any later
+version.
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program. If not, see <http://www.gnu.org/licenses/>.
+
+__author__ = "bzhxx"
+__contact__ = "https://github.com/bzhxx"
+__license__ = "GPLv3"
+
+*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include "../cpus/M68K/m68k.h"
+#include "gwenesis_vdp.h"
+#include "../io/gwenesis_io.h"
+#include "../bus/gwenesis_bus.h"
+#include "../savestate/gwenesis_savestate.h"
+
+#include <assert.h>
+//#include <graphics.h>
+#include <gwenesis/sound/gwenesis_sn76489.h>
+
+#include "pico.h"
+#pragma GCC optimize("Ofast")
+
+#define VDP_MEM_DISABLE_LOGGING 1
+
+#if !VDP_MEM_DISABLE_LOGGING
+#include <stdarg.h>
+void vdpm_log(const char *subs, const char *fmt, ...) {
+  extern int frame_counter;
+  extern int scan_line;
+
+  va_list va;
+
+  printf("%06d:%03d :[%s] vc:%04x hc:%04x hv:%04x ", frame_counter, scan_line, subs,gwenesis_vdp_vcounter(),gwenesis_vdp_hcounter(),gwenesis_vdp_hvcounter());
+
+  va_start(va, fmt);
+  vfprintf(stdout, fmt, va);
+  va_end(va);
+  printf("\n");
+}
+#else
+#define vdpm_log(...)
+#endif
+
+//#define _DMA_TRACE_
+
+/* Setup VDP Memories */
+
+//extern uint8_t emulator_framebuffer[1024*64];
+//unsigned char* VRAM = &emulator_framebuffer[0];
+unsigned char VRAM[VRAM_MAX_SIZE];
+//unsigned char* VRAM = NULL;
+
+unsigned short CRAM[CRAM_MAX_SIZE]; // CRAM - Palettes
+unsigned char SAT_CACHE[SAT_CACHE_MAX_SIZE]; // Sprite cache
+unsigned char gwenesis_vdp_regs[REG_SIZE]; // Registers
+unsigned short fifo[FIFO_SIZE]; // Fifo
+//uint8_t CRAM222[CRAM_MAX_SIZE * 4];    // CRAM - Palettes
+unsigned short VSRAM[VSRAM_MAX_SIZE]; // VSRAM - Scrolling
+
+// Define VDP control code and set initial code
+static unsigned char code_reg = 0;
+// Define VDP control address and set initial address
+static unsigned short address_reg = 0;
+// Define VDP control pending and set initial state
+int command_word_pending = 0;
+// Define VDP status and set initial status value
+unsigned short gwenesis_vdp_status = 0x3C00;
+
+extern int scan_line;
+extern bool sn76489_enabled;
+extern bool audio_enabled;
+// Define DMA
+//static unsigned int dma_length;
+//static unsigned int dma_source;
+// Define and set DMA FILL pending as initial state
+int dma_fill_pending = 0;
+
+// Define HVCounter latch and set initial state
+static int hvcounter_latch = 0;
+static int hvcounter_latched = 0;
+
+int hint_pending;
+
+
+// Define VIDEO MODE
+extern int mode_pal;
+
+extern int sprite_overflow;
+extern bool sprite_collision;
+
+// Store last address r/w
+//static unsigned int gwenesis_vdp_laddress_r=0;
+//unsigned int gwenesis_vdp_laddress_w=0;
+
+//static int DMA_RUN=0;
+
+// 16 bits access to VRAM
+#define FETCH16(A) ( ( (*(unsigned short *)&VRAM[(A)]) >> 8 ) | ( (*(unsigned short *)&VRAM[(A)]) << 8 ) )
+
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 Reset
+ *  Clear all volatile memory
+ *
+ ******************************************************************************/
+int m68k_irq_acked(int irq) {
+    /* VINT has higher priority (Fatal Rewind) */
+    if (REG1_VBLANK_INTERRUPT && (gwenesis_vdp_status & STATUS_VIRQPENDING)) {
+        /* Clear VINT pending flag */
+        gwenesis_vdp_status &= ~STATUS_VIRQPENDING;
+
+        if (hint_pending && REG0_LINE_INTERRUPT)
+            m68k_set_irq(4);
+        else
+            m68k_set_irq(0);
+    }
+    else {
+        /* Clear HINT pending flag */
+        hint_pending = 0;
+
+        /* Update IRQ status */
+        m68k_set_irq(0);
+    }
+
+    return M68K_INT_ACK_AUTOVECTOR;
+}
+
+
+void gwenesis_vdp_reset() {
+    memset(VRAM, 0, VRAM_MAX_SIZE);
+    memset(SAT_CACHE, 0, sizeof(SAT_CACHE));
+    memset(CRAM, 0, sizeof(CRAM));
+    //    memset(CRAM222, 0, sizeof(CRAM222));
+    memset(VSRAM, 0, sizeof(VSRAM));
+    memset(gwenesis_vdp_regs, 0, sizeof(gwenesis_vdp_regs));
+    command_word_pending = 0;
+    address_reg = 0;
+    code_reg = 0;
+    hint_pending = 0;
+    // _vcounter = 0;
+    gwenesis_vdp_status = 0x3C00;
+    // //line_counter_interrupt = 0;
+    hvcounter_latched = 0;
+
+    // register the M68K interrupt
+    m68k_set_int_ack_callback(m68k_irq_acked);
+}
+
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 HCOUNTER
+ *  Process SEGA 315-5313 HCOUNTER based on M68K Cycles
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+int gwenesis_vdp_hcounter() {
+    int mclk = m68k_cycles_run();
+    int pixclk;
+
+    // Accurate 9-bit hcounter emulation, from timing posted here:
+    // http://gendev.spritesmind.net/forum/viewtopic.php?p=17683#17683
+    if (REG12_MODE_H40) {
+        pixclk = mclk * 420 / VDP_CYCLES_PER_LINE;
+        pixclk += 0xD;
+        if (pixclk >= 0x16D)
+            pixclk += 0x1C9 - 0x16D;
+    }
+    else {
+        pixclk = mclk * 342 / VDP_CYCLES_PER_LINE;
+        pixclk += 0xB;
+        if (pixclk >= 0x128)
+            pixclk += 0x1D2 - 0x128;
+    }
+
+    return pixclk & 0x1FF;
+}
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 VCOUNTER
+ *  Process SEGA 315-5313 VCOUNTER based on M68K Cycles
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+int gwenesis_vdp_vcounter() {
+    int vc = scan_line;
+    int VERSION_PAL = gwenesis_vdp_status & 1;
+
+    /*
+    if (VERSION_PAL && mode_pal && (vc >= 0x10B))
+        vc += 0x1D2 - 0x10B;
+    else if (VERSION_PAL && (mode_pal==0) && (vc >= 0x103))
+        vc += 0x1CA - 0x103;
+    else if ((VERSION_PAL ==0 ) && (vc >= 0xEB))
+        vc += 0x1E5 - 0xEB;
+    assert(vc < 0x200);
+    */
+    if (VERSION_PAL && mode_pal && (vc >= 267))
+        vc = scan_line - 58;
+    else if (VERSION_PAL && (mode_pal == 0) && (vc >= 259))
+        vc = scan_line - 42;
+    else if ((VERSION_PAL == 0) && (vc >= 235))
+        vc = scan_line - 6;
+    assert(vc < 0x200);
+
+    // printf("VERSION_PAL:%d , mode_pal:%d,line:%d,vc:%d\n",VERSION_PAL,mode_pal,scan_line,vc);
+    return vc;
+}
+
+/******************************************************************************
+ *
+ *  SEGA 315-5313 HVCOUNTER
+ *  Process SEGA 315-5313 HVCOUNTER based on HCOUNTER and VCOUNTER
+ *
+ ******************************************************************************/
+//static inline __attribute__((always_inline))
+unsigned short gwenesis_vdp_hvcounter() {
+    /* H/V Counter */
+    if (hvcounter_latched == 1)
+        return hvcounter_latch;
+
+    int hc = gwenesis_vdp_hcounter();
+    int vc = gwenesis_vdp_vcounter();
+    assert(vc < 512);
+    assert(hc < 512);
+
+    return ((vc & 0xFF) << 8) | (hc >> 1);
+}
+
+//static inline __attribute__((always_inline))
+bool vblank(void) {
+    int vc = gwenesis_vdp_vcounter();
+    //  printf("vc=%d,REG1_DISP_ENABLED=%d,VBLAN?%d\n",vc,REG1_DISP_ENABLED,
+    // mode_pal?((vc >= 0xF0) && (vc < 0x1FF)):((vc >= 0xE0) && (vc < 0x1FF)));
+
+    if (REG1_DISP_ENABLED == 0)
+        return true;
+
+    if (mode_pal)
+        return ((vc >= 0xF0) && (vc < 0x1FF));
+    else
+        return ((vc >= 0xE0) && (vc < 0x1FF));
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Set Register
+ *   Write an value to specified register
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline)) void gwenesis_vdp_register_w(int reg, unsigned char value) {
+    // Mode4 is not emulated yet. Anyway, access to registers > 0xA is blocked.
+    if ((BIT(gwenesis_vdp_regs[0x1], 2) == 0) && reg > 0xA)
+        return;
+
+    gwenesis_vdp_regs[reg] = value;
+    vdpm_log(__FUNCTION__, "reg:%02d <- %02x", reg, value);
+
+
+    // Writing a register clear the first command word
+    // (see sonic3d intro wrong colors, and vdpfifotesting)
+    code_reg &= ~0x3;
+    address_reg &= ~0x3FFF;
+
+    switch (reg) {
+        case 0:
+
+            if (REG0_HVLATCH && (hvcounter_latched == 0)) {
+                hvcounter_latch = gwenesis_vdp_hvcounter();
+                hvcounter_latched = 1;
+                //printf("HVcounter latched:%x\n",hvcounter_latch);
+            }
+            else if ((REG0_HVLATCH == 0) && (hvcounter_latched == 1)) {
+                //printf("HVcounter released\n");
+                hvcounter_latched = 0;
+            }
+
+            break;
+    }
+}
+
+/******************************************************************************
+ *
+ *  Simulate FIFO
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void push_fifo(unsigned int value) {
+    fifo[3] = fifo[2];
+    fifo[2] = fifo[1];
+    fifo[1] = fifo[0];
+    fifo[0] = value;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 VRAM Write
+ *   Write an value to VRAM on specified address
+ *
+ ******************************************************************************/
+
+//static inline __attribute__((always_inline))
+void __not_in_flash_func(gwenesis_vdp_vram_write)(unsigned int address, unsigned int value) {
+    VRAM[address] = value;
+
+    // Update internal SAT Cache
+    // used in Castlevania Bloodlines
+    if (address >= REG5_SAT_ADDRESS && address < REG5_SAT_ADDRESS + REG5_SAT_SIZE)
+        SAT_CACHE[address - REG5_SAT_ADDRESS] = value;
+}
+
+static inline __attribute__((always_inline))
+unsigned short status_register_r(void) {
+    unsigned short status = gwenesis_vdp_status; // & 0xF800;
+    // unsigned short status = gwenesis_vdp_status;// & 0xFC00;
+
+    int hc = gwenesis_vdp_hcounter();
+    // int vc = gwenesis_vdp_vcounter();
+
+    // TODO: FIFO not emulated
+    status |= STATUS_FIFO_EMPTY;
+
+    // VBLANK bit
+    if (vblank())
+        status |= STATUS_VBLANK;
+
+    // HBLANK bit (see Nemesis doc, as linked in hcounter())
+    if (REG12_MODE_H40) {
+        if (hc < 0xA || hc >= 0x166)
+            status |= STATUS_HBLANK;
+    }
+    else {
+        if (hc < 0x9 || hc >= 0x126)
+            status |= STATUS_HBLANK;
+    }
+
+    if (sprite_overflow)
+        status |= STATUS_SPRITEOVERFLOW;
+    if (sprite_collision)
+        status |= STATUS_SPRITECOLLISION;
+
+    if (mode_pal)
+        status |= STATUS_PAL;
+
+    // reading the status clears the pending flag for command words
+    command_word_pending = 0;
+
+    //gwenesis_vdp_status = status;
+
+    // printf("VDP status read:%04X H?%d V?%d line=%d\n",status, status & STATUS_HBLANK ,status & STATUS_VBLANK,scan_line);
+    return status;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Get Register
+ *   Read an value from specified register
+ *
+ ******************************************************************************/
+unsigned int gwenesis_vdp_get_reg(int reg) {
+    return gwenesis_vdp_regs[reg];
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA Fill
+ *   DMA process to fill memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_fill(unsigned short value) {
+    //vdpm_log(__FUNCTION__,"@%x len:%x val:%x",REG21_DMA_SRCADDR_LOW,REG19_DMA_LENGTH,value);
+    int dma_length = REG19_DMA_LENGTH;
+
+    // This address is not required for fills,
+    // but it's still updated by the DMA engine.
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+
+    if (dma_length == 0)
+        dma_length = 0xFFFF;
+
+    /*
+    vdpm_log(__FUNCTION__, "DMA %s fill: dst:%04x, length:%d, increment:%d, value=%02x",
+        (code_reg&0xF)==1 ? "VRAM" : ( (code_reg&0xF)==3 ? "CRAM" : "VSRAM"),
+        address_reg, dma_length, REG15_DMA_INCREMENT, value>>8);
+        */
+
+    switch (code_reg & 0xF) {
+        case 0x1:
+            do {
+                gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value >> 8);
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        case 0x3: // undocumented and buggy, see vdpfifotesting
+            do {
+                uint8_t addr = (address_reg & 0x7f) >> 1;
+                CRAM[addr] = fifo[3];
+
+                //graphics_set_palette(addr, RGB888(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr])));
+                emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        case 0x5: // undocumented and buggy, see vdpfifotesting:
+            do {
+                VSRAM[(address_reg & 0x7f) >> 1] = fifo[3] & 0x03FF;
+                address_reg += REG15_DMA_INCREMENT;
+                src_addr_low++;
+            }
+            while (--dma_length);
+            break;
+        default:
+            printf("Invalid code during DMA fill\n");
+    }
+
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = src_addr_low >> 8;
+
+    // gwenesis_vdp_regs[21] = src_addr_low >> 1 & 0xFF;
+    // gwenesis_vdp_regs[22] = src_addr_low >> 9 & 0xFF;
+    // gwenesis_vdp_regs[23] = src_addr_low >> 17 & 0xFF;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA M68K
+ *   DMA process to copy from m68k to memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_m68k() {
+    int dma_length = REG19_DMA_LENGTH;
+
+    // This address is not required for fills,
+    // but it's still updated by the DMA engine.
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+    unsigned int src_addr_high = REG23_DMA_SRCADDR_HIGH;
+    unsigned int src_addr = (src_addr_high | src_addr_low) << 1;
+    unsigned int value;
+
+    if (dma_length == 0)
+        dma_length = 0xFFFF;
+
+    /*
+    vdpm_log(__FUNCTION__,"DMA M68k->%s copy: src:%04x, dst:%04x, length:%d, increment:%d",
+        (code_reg&0xF)==1 ? "VRAM" : ( (code_reg&0xF)==3 ? "CRAM" : "VSRAM"),
+        (src_addr_high | src_addr_low) << 1, address_reg, dma_length, REG15_DMA_INCREMENT);
+    */
+
+    /* Source is :
+        68K_RAM if dma_source_high == 0x00FF : FETCH16RAM(dma_source_low << 1)
+        68K_ROM otherwise                    : FETCH16ROM((dma_source_high | dma_source_low) << 1))
+    */
+
+    /* Source is 68K RAM */
+    if (src_addr & 0x800000) {
+        switch (code_reg & 0xF) {
+            case 0x1: // dest is VRAM
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    gwenesis_vdp_vram_write((address_reg) & 0xFFFF, value >> 8);
+                    gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value & 0xFF);
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x3: // dest is CRAM
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    uint8_t addr = (address_reg & 0x7f) >> 1;
+                    CRAM[addr] = value;
+
+                    //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+                    emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x5: // dest is VSRAM
+
+                do {
+                    value = FETCH16RAM(src_addr);
+                    push_fifo(value);
+                    VSRAM[(address_reg & 0x7f) >> 1] = value & 0x03FF;
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+            default: // dest in unknown
+                break;
+        }
+
+        /* source is 68K ROM */
+    }
+    else {
+        // unsigned int dma_source_address = (dma_source_high | dma_source_low) << 1;
+
+        switch (code_reg & 0xF) {
+            case 0x1: // dest is VRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    gwenesis_vdp_vram_write((address_reg) & 0xFFFF, value >> 8);
+                    gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value & 0xFF);
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x3: // dest is CRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    uint8_t addr = (address_reg & 0x7f) >> 1;
+                    CRAM[addr] = value;
+
+                    //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+                    emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+
+            case 0x5: // dest is VSRAM
+
+                do {
+                    value = FETCH16ROM(src_addr);
+                    push_fifo(value);
+                    VSRAM[(address_reg & 0x7f) >> 1] = value & 0x03FF;
+                    address_reg += REG15_DMA_INCREMENT;
+                    src_addr += 2;
+                }
+                while (--dma_length);
+                break;
+            default: // dest in unknown
+                break;
+        }
+    }
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr & 0xFF; //src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = (src_addr >> 8) & 0xFF; //src_addr_low >> 8;
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 DMA Copy
+ *   DMA process to copy from memory to memory
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_dma_copy() {
+    // DMA_RUN=1;
+
+    int dma_length = REG19_DMA_LENGTH;
+    unsigned short src_addr_low = REG21_DMA_SRCADDR_LOW;
+    //vdpm_log(__FUNCTION__,"length:%x src:%x",dma_length,src_addr_low);
+
+    do {
+        unsigned short value = VRAM[src_addr_low ^ 1];
+        gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, value);
+
+        address_reg += REG15_DMA_INCREMENT;
+        src_addr_low++;
+    }
+    while (--dma_length);
+
+    // Update DMA source address after end of transfer
+    gwenesis_vdp_regs[21] = src_addr_low & 0xFF;
+    gwenesis_vdp_regs[22] = src_addr_low >> 8;
+
+    // Clear DMA length at the end of transfer
+    gwenesis_vdp_regs[19] = gwenesis_vdp_regs[20] = 0;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read data R16
+ *   Read an data value from mapped memory on specified address
+ *   and return as word
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+unsigned int gwenesis_vdp_read_data_port_16() {
+    enum {
+        CRAM_BITMASK = 0x0EEE,
+        VSRAM_BITMASK = 0x07FF,
+        VRAM8_BITMASK = 0x00FF
+    };
+    unsigned int value;
+    command_word_pending = 0;
+
+    //if (code_reg & 1) /* check if write is set */
+    // {
+    switch (code_reg & 0xF) {
+        case 0x0:
+            // No byteswapping here
+            value = VRAM[(address_reg) & 0xFFFE] << 8;
+            value |= VRAM[(address_reg | 1) & 0xFFFF];
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+        //vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0x4:
+            if (((address_reg & 0x7f) >> 1) >= 0x28)
+                value = VSRAM[0];
+            else
+                value = VSRAM[(address_reg & 0x7f) >> 1];
+            value = (value & VSRAM_BITMASK) | (fifo[3] & ~VSRAM_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0x7F;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0x8:
+            value = CRAM[(address_reg & 0x7f) >> 1];
+            value = (value & CRAM_BITMASK) | (fifo[3] & ~CRAM_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0x7F;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        case 0xC: /* 8-Bit memory access */
+            value = VRAM[(address_reg ^ 1) & 0xFFFF];
+            value = (value & VRAM8_BITMASK) | (fifo[3] & ~VRAM8_BITMASK);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+        // vdpm_log(__FUNCTION__,"%04x",value);
+
+            return value;
+        default:
+            printf("unhandled gwenesis_vdp_read_data_port_16(%x)\n", address_reg);
+            return 0xFF;
+    }
+    // }
+    //  return 0x00;
+}
+
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to control port
+ *   Write an control value to SEGA 315-5313 control port
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_control_port_write(unsigned int value) {
+    //vdpm_log(__FUNCTION__,"%04x",value);
+
+    if (command_word_pending == 1) {
+        // second half of the command word
+        code_reg &= ~0x3C;
+        code_reg |= (value >> 2) & 0x3C;
+        address_reg &= 0x3FFF;
+        address_reg |= value << 14;
+        command_word_pending = 0;
+        //vdpm_log(__FUNCTION__,"command word 2nd code:%x address:%x", code_reg, address_reg);
+
+
+        // DMA trigger
+        if (code_reg & (1 << 5)) {
+            // Check master DMA enable, otherwise skip
+            if (REG1_DMA_ENABLED == 0)
+                return;
+
+            // gwenesis_vdp_status |= 0x2;
+            switch (REG23_DMA_TYPE) {
+                case 0:
+                case 1:
+
+                    gwenesis_vdp_dma_m68k();
+                    break;
+
+                case 2:
+
+                    // VRAM fill will trigger on next data port write
+                    dma_fill_pending = 1;
+                    break;
+
+                case 3:
+
+                    gwenesis_vdp_dma_copy();
+                    break;
+            }
+        }
+        return;
+    }
+    if ((value >> 14) == 2) {
+        gwenesis_vdp_register_w((value >> 8) & 0x1F, value & 0xFF);
+        return;
+    }
+
+    // Anything else is treated as first half of the command word
+    // We directly update the code reg and address reg
+    code_reg &= ~0x3;
+    code_reg |= value >> 14;
+    address_reg &= ~0x3FFF;
+    address_reg |= value & 0x3FFF;
+    command_word_pending = 1;
+    // vdpm_log(__FUNCTION__,"command word 1st code:%x address:%x", code_reg, address_reg);
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write data W16
+ *   Write an data value to mapped memory on specified address
+ *
+ ******************************************************************************/
+static inline __attribute__((always_inline))
+void gwenesis_vdp_write_data_port_16(unsigned int value) {
+    vdpm_log(__FUNCTION__, "%04x", value);
+
+    command_word_pending = 0;
+
+    push_fifo(value);
+
+    switch (code_reg & 0xF) {
+        case 0x1: /* VRAM write */
+            //vdpm_log(__FUNCTION__,"VRAM write : addr:%x increment:%d value:%04x",
+            // address_reg, REG15_DMA_INCREMENT, value);
+            gwenesis_vdp_vram_write(address_reg & 0xFFFF, (value >> 8) & 0xFF);
+            gwenesis_vdp_vram_write((address_reg ^ 1) & 0xFFFF, (value) & 0xFF);
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+
+            break;
+        case 0x3: /* CRAM write */
+            //vdpm_log(__FUNCTION__,"CRAM write : addr:%x increment:%d value:%04x",
+            // address_reg, REG15_DMA_INCREMENT, value);
+        {
+            uint8_t addr = (address_reg & 0x7f) >> 1;
+            CRAM[addr] = value;
+
+            //graphics_set_palette(addr, RGB888(CRAM_R(value), CRAM_G(value), CRAM_B(value)));
+            emu_SetPaletteEntry(CRAM_R(CRAM[addr]), CRAM_G(CRAM[addr]), CRAM_B(CRAM[addr]),addr);
+
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+
+            break;
+        }
+        case 0x5: /* VSRAM write */
+            //vdpm_log(__FUNCTION__,"VSRAM write : addr:%x increment:%d value:%04x",
+            //  address_reg, REG15_DMA_INCREMENT, value);
+            // printf("write dataport 16: VSRAM@%04x:%04x\n",address_reg,value);
+            VSRAM[(address_reg & 0x7f) >> 1] = value & 0X03FF;
+            address_reg += REG15_DMA_INCREMENT;
+            address_reg &= 0xFFFF;
+            break;
+        case 0x0:
+        case 0x4:
+        case 0x8: // Write operation after setting up
+            // Makes Compatible with Alladin and Ecco 2
+            break;
+        case 0x9: // VDP FIFO TEST
+            break;
+        default:
+            printf("VDP Data Port invalid");
+    }
+
+    /* if a DMA is scheduled, do it */
+    if (dma_fill_pending) {
+        dma_fill_pending = 0;
+        gwenesis_vdp_dma_fill(value);
+        return;
+    }
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 Get Status
+ *   Return current VDP Status
+ *
+ ******************************************************************************/
+unsigned int gwenesis_vdp_get_status() {
+    return gwenesis_vdp_status;
+}
+
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read from memory R8
+ *   Read an value from mapped memory on specified address
+ *   and return as byte
+ *
+ ******************************************************************************/
+//static inline
+unsigned int gwenesis_vdp_read_memory_8(unsigned int address) {
+    unsigned int ret = gwenesis_vdp_read_memory_16(address & ~1);
+    if (address & 1)
+        return ret & 0xFF;
+
+    // vdpm_log(__FUNCTION__,"%04x : %04x",address,ret);
+
+    return ret >> 8;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 read from memory R16
+ *   Read an value from mapped memory on specified address
+ *   and return as word
+ *
+ ******************************************************************************/
+//static inline
+unsigned int gwenesis_vdp_read_memory_16(unsigned int address) {
+    address &= 0x1F;
+
+    if (address < 0X4)
+        return gwenesis_vdp_read_data_port_16();
+    else if (address < 0x8)
+        return status_register_r();
+    else if (address < 0xf)
+        return gwenesis_vdp_hvcounter();
+    else
+        return 0xff;
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to memory W8
+ *   Write an byte value to mapped memory on specified address
+ *
+ ******************************************************************************/
+//static inline
+void gwenesis_vdp_write_memory_8(unsigned int address, unsigned int value) {
+    gwenesis_vdp_write_memory_16(address & ~1, (value << 8) | value);
+}
+
+/******************************************************************************
+ *
+ *   SEGA 315-5313 write to memory W16
+ *   Write an word value to mapped memory on specified address
+ *
+ ******************************************************************************/
+//static inline
+extern int system_clock;
+
+void gwenesis_vdp_write_memory_16(unsigned int address, unsigned int value) {
+    address = address & 0x1F;
+
+    if (address < 0x4) {
+        gwenesis_vdp_write_data_port_16(value);
+        return;
+    }
+    if (address < 0x8) {
+        gwenesis_vdp_control_port_write(value);
+        return;
+    }
+    if (address < 0x18) {
+        // PSG 8 bits write
+        vdpm_log(__FUNCTION__, "PSG sclk=%d,mclk=%d", system_clock, m68k_cycles_master());
+        if(audio_enabled && sn76489_enabled)
+            gwenesis_SN76489_Write(value, m68k_cycles_master());
+        return;
+    }
+    // UNHANDLED
+    printf("unhandled gwenesis_vdp_write(%x, %x)\n", address, value);
+}
+
+void gwenesis_vdp_mem_save_state() {
+}
+
+void gwenesis_vdp_mem_load_state() {
+
+}
diff --git a/MCUME_pico2/picogen/keyboard_osd.h b/MCUME_pico2/picogen/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picogen/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picogen/picogen.cpp b/MCUME_pico2/picogen/picogen.cpp
new file mode 100644
index 0000000..56e7c2c
--- /dev/null
+++ b/MCUME_pico2/picogen/picogen.cpp
@@ -0,0 +1,188 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(125000, true);
+
+//    set_sys_clock_khz(280000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+     emu_init();
+ 
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+*/
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picogen/program_config.h b/MCUME_pico2/picogen/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/picogen/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/picogenold/.DS_Store b/MCUME_pico2/picogenold/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/picogenold/.DS_Store differ
diff --git a/MCUME_pico2/picogenold/cpuintrf.h b/MCUME_pico2/picogenold/cpuintrf.h
new file mode 100644
index 0000000..d78b29d
--- /dev/null
+++ b/MCUME_pico2/picogenold/cpuintrf.h
@@ -0,0 +1,30 @@
+
+#ifndef CPUINTRF_H
+#define CPUINTRF_H
+
+#include "osd_cpu.h"
+
+#define CPU_16BIT_PORT          0x4000
+#define CPU_FLAGS_MASK          0xff00
+#define CLEAR_LINE              0
+#define ASSERT_LINE             1
+#define REG_PREVIOUSPC          -1
+#define REG_SP_CONTENTS         -2
+
+/* daisy-chain link */
+typedef struct {
+	void (*reset)(int);             /* reset callback     */
+	int  (*interrupt_entry)(int);   /* entry callback     */
+	void (*interrupt_reti)(int);    /* reti callback      */
+	int irq_param;                  /* callback paramater */
+}	Z80_DaisyChain;
+
+#define Z80_MAXDAISY	4		/* maximum of daisy chan device */
+
+#define Z80_INT_REQ     0x01    /* interrupt request mask       */
+#define Z80_INT_IEO     0x02    /* interrupt disable mask(IEO)  */
+
+#define Z80_VECTOR(device,state) (((device)<<8)|(state))
+
+
+#endif	/* CPUINTRF_H */
diff --git a/MCUME_pico2/picogenold/emu.cpp b/MCUME_pico2/picogenold/emu.cpp
new file mode 100644
index 0000000..6a94feb
--- /dev/null
+++ b/MCUME_pico2/picogenold/emu.cpp
@@ -0,0 +1,205 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+extern "C" {
+#include "shared.h"
+#include "system.h"
+}
+
+static int frameskip = 2;
+#define HAS_PSRAM 1
+
+#ifdef HAS_PSRAM
+
+#include "psram_t.h"
+
+PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO);
+
+extern "C" uint8 read_rom(int address) {
+  return (psram.psread(address)); 
+}
+
+extern "C" uint8 readb_swap_rom(int address) {
+  return(psram.psread(address^1));
+}
+
+extern "C" uint16 readw_swap_rom(int address) {
+  return psram.psread_w(address);  
+}
+extern "C" void  write_rom(int address, uint8 val)  {
+  psram.pswrite(address,val); 
+}
+#else
+#include "flash_t.h"
+
+static uint8 * flash_start;
+
+extern "C" uint8 read_rom(int address) {
+  return flash_start[address];
+}
+
+extern "C" uint8 readb_swap_rom(int address) {
+  return flash_start[address^1];
+}
+
+extern "C" uint16 readw_swap_rom(int address) {
+  uint16 * flash_start16 = (uint16*)flash_start;
+  return flash_start16[address];
+  //return psram.psread_w(address);  
+}
+
+#endif
+
+static uint8 romversion;
+extern "C" uint8 rom_version(void) {
+  return romversion;
+}
+
+static void deinterleave_block(int offset, int srcoffset)
+{
+    int i;
+    int srcaddr = offset + srcoffset;
+    uint8 * block = work_ram; // 0x4000 bytes tmp buffer 
+    for(i = 0; i < 0x4000; i += 1) {
+      block[i] = read_rom(srcaddr++);
+    }
+    for(i = 0; i < 0x2000; i += 1)
+    {
+        write_rom(srcoffset + i*2+1, block[0x2000 + (i)]);
+        write_rom(srcoffset + i*2+0, block[0x0000 + (i)]);
+    }
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+void gen_Init(void)
+{
+  emu_printf("Allocating MEM");
+#ifdef HAS_PSRAM
+  psram.begin();
+#endif  
+  mem_init();    
+  emu_printf("Allocating MEM done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void gen_Input(int click) {
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();   
+}
+
+
+void gen_Start(char * filename)
+{
+  emu_printf("load and init");  
+
+  int size;
+  int offset = 0;
+  int i;
+
+  size = emu_FileSize(filename);
+
+#ifdef HAS_PSRAM  
+  int pos = 0;
+  int n;
+  char * buf = (char*)bg_pattern_cache;
+  size = 0;
+  int f = emu_FileOpen(filename,"r+b");  
+  if (f) {
+    while ( (n = emu_FileRead(buf,0x40000,f) ) ) {
+      size += n;
+      for (int i=0; i<n; i++) {
+        write_rom(pos++,buf[i]);
+      }
+      emu_printi(size);            
+      //emu_printi(n);          
+    }
+    emu_FileClose(f);
+  }
+#else
+  flash_start = (uint8 *)flash_load(filename);  
+#endif  
+
+  if((size / 512) & 1)
+  {
+      //emu_printf("deinterleave");
+      size -= 512;
+      offset += 512;
+      for(i = 0; i < (size / 0x4000); i += 1)
+      {
+          deinterleave_block(offset, (i * 0x4000));
+      }
+  }
+  else {
+    for(i = 0; i < size; i += 2)
+    {
+        uint8 temp = read_rom(i+0);
+        write_rom(i+0,read_rom(offset+i+1));
+        write_rom(i+1, temp);
+    }
+  }
+
+  romversion = read_rom(0x0001F0);
+
+ 
+  system_init();
+
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND
+//  audio_init(22050);  
+//  emu_sndInit();
+#endif  
+#endif
+  
+  system_reset();  
+
+  emu_printf("init done");
+}
+
+void gen_Step(void) {
+
+  input.pad[0] = 0;
+
+  if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+    input.pad[0] |= INPUT_RIGHT;
+  }
+  if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+    input.pad[0] |= INPUT_LEFT;
+  }
+  if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+    input.pad[0] |= INPUT_UP;
+  }
+  if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+    input.pad[0] |= INPUT_DOWN;
+  }  
+  if ( k & MASK_JOY2_BTN) {
+    input.pad[0] |= INPUT_A; 
+  }
+
+  if (k & MASK_KEY_USER1)  input.pad[0] |= INPUT_B;
+  if (k & MASK_KEY_USER2)  input.pad[0] |= INPUT_START;
+  //if (k & MASK_KEY_USER3)  input.pad[0] |= INPUT_C;
+  
+  system_frame(frameskip); 
+  //emu_printi(emu_FrameSkip());
+
+  emu_DrawVsync();    
+}
+
+void SND_Process(void *stream, int len) {
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND
+//audio_play_sample(stream, 0, len);
+#endif  
+#endif  
+} 
diff --git a/MCUME_pico2/picogenold/emu.h b/MCUME_pico2/picogenold/emu.h
new file mode 100644
index 0000000..960a514
--- /dev/null
+++ b/MCUME_pico2/picogenold/emu.h
@@ -0,0 +1,5 @@
+extern void gen_Init(void);
+extern void gen_Step(void);
+extern void gen_Start(char * filename);
+extern void gen_Input(int click);
+
diff --git a/MCUME_pico2/picogenold/emucfg.h b/MCUME_pico2/picogenold/emucfg.h
new file mode 100644
index 0000000..141eda4
--- /dev/null
+++ b/MCUME_pico2/picogenold/emucfg.h
@@ -0,0 +1,103 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         1
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10000 // 0x10
+#define FILEBROWSER
+
+
+// Title:     <                                        >
+#define TITLE "           Genesis Emulator             "
+#define ROMSDIR "gen"
+
+#define emu_Init(ROM) {gen_Init(); gen_Start(ROM);}
+#define emu_Step(x) {gen_Step();}
+#define emu_Input(x) {gen_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picogenold/fm.c b/MCUME_pico2/picogenold/fm.c
new file mode 100644
index 0000000..279b079
--- /dev/null
+++ b/MCUME_pico2/picogenold/fm.c
@@ -0,0 +1,1495 @@
+
+#include "shared.h"
+#include <math.h>
+
+#ifndef PI
+#define PI 3.14159265358979323846
+#endif
+
+#define BUILD_OPN (BUILD_YM2612)
+#define BUILD_STEREO (BUILD_YM2612)
+#define BUILD_LFO (BUILD_YM2612)
+
+#define SIN_ENT 2048
+#define ENV_BITS 16
+#define EG_ENT   4096
+#define EG_STEP (96.0/EG_ENT) /* OPL == 0.1875 dB */
+
+#if FM_LFO_SUPPORT
+/* LFO table entries */
+#define LFO_ENT 512
+#define LFO_SHIFT (32-9)
+#define LFO_RATE 0x10000
+#endif
+
+/* -------------------- preliminary define section --------------------- */
+/* attack/decay rate time rate */
+#define OPM_ARRATE     399128
+#define OPM_DRRATE    5514396
+/* It is not checked , because I haven't YM2203 rate */
+#define OPN_ARRATE  OPM_ARRATE
+#define OPN_DRRATE  OPM_DRRATE
+
+/* PG output cut off level : 78dB(14bit)? */
+#define PG_CUT_OFF ((int)(78.0/EG_STEP))
+/* EG output cut off level : 68dB? */
+#define EG_CUT_OFF ((int)(68.0/EG_STEP))
+
+#define FREQ_BITS 24		/* frequency turn          */
+
+/* PG counter is 21bits @oct.7 */
+#define FREQ_RATE   (1<<(FREQ_BITS-21))
+#define TL_BITS    (FREQ_BITS+2)
+/* OPbit = 14(13+sign) : TL_BITS+1(sign) / output = 16bit */
+#define TL_SHIFT (TL_BITS+1-(14-16))
+
+/* output final shift */
+#define FM_OUTSB  (TL_SHIFT-FM_OUTPUT_BIT)
+#define FM_MAXOUT ((1<<(TL_SHIFT-1))-1)
+#define FM_MINOUT (-(1<<(TL_SHIFT-1)))
+
+/* -------------------- local defines , macros --------------------- */
+
+/* envelope counter position */
+#define EG_AST   0					/* start of Attack phase */
+#define EG_AED   (EG_ENT<<ENV_BITS)	/* end   of Attack phase */
+#define EG_DST   EG_AED				/* start of Decay/Sustain/Release phase */
+#define EG_DED   (EG_DST+(EG_ENT<<ENV_BITS)-1)	/* end   of Decay/Sustain/Release phase */
+#define EG_OFF   EG_DED				/* off */
+#if FM_SEG_SUPPORT
+#define EG_UST   ((2*EG_ENT)<<ENV_BITS)  /* start of SEG UPSISE */
+#define EG_UED   ((3*EG_ENT)<<ENV_BITS)  /* end of SEG UPSISE */
+#endif
+
+/* register number to channel number , slot offset */
+#define OPN_CHAN(N) (N&3)
+#define OPN_SLOT(N) ((N>>2)&3)
+#define OPM_CHAN(N) (N&7)
+#define OPM_SLOT(N) ((N>>3)&3)
+/* slot number */
+#define SLOT1 0
+#define SLOT2 2
+#define SLOT3 1
+#define SLOT4 3
+
+/* bit0 = Right enable , bit1 = Left enable */
+#define OUTD_RIGHT  1
+#define OUTD_LEFT   2
+#define OUTD_CENTER 3
+
+/* FM timer model */
+#define FM_TIMER_SINGLE (0)
+#define FM_TIMER_INTERVAL (1)
+
+/* ---------- OPN / OPM one channel  ---------- */
+typedef struct fm_slot {
+	INT32 *DT;			/* detune          :DT_TABLE[DT]       */
+	int DT2;			/* multiple,Detune2:(DT2<<4)|ML for OPM*/
+	int TL;				/* total level     :TL << 8            */
+	UINT8 KSR;			/* key scale rate  :3-KSR              */
+	const INT32 *AR;	/* attack rate     :&AR_TABLE[AR<<1]   */
+	const INT32 *DR;	/* decay rate      :&DR_TABLE[DR<<1]   */
+	const INT32 *SR;	/* sustin rate     :&DR_TABLE[SR<<1]   */
+	int   SL;			/* sustin level    :SL_TABLE[SL]       */
+	const INT32 *RR;	/* release rate    :&DR_TABLE[RR<<2+2] */
+	UINT8 SEG;			/* SSG EG type     :SSGEG              */
+	UINT8 ksr;			/* key scale rate  :kcode>>(3-KSR)     */
+	UINT32 mul;			/* multiple        :ML_TABLE[ML]       */
+	/* Phase Generator */
+	UINT32 Cnt;			/* frequency count :                   */
+	UINT32 Incr;		/* frequency step  :                   */
+	/* Envelope Generator */
+	void (*eg_next)(struct fm_slot *SLOT);	/* pointer of phase handler */
+	INT32 evc;			/* envelope counter                    */
+	INT32 eve;			/* envelope counter end point          */
+	INT32 evs;			/* envelope counter step               */
+	INT32 evsa;			/* envelope step for Attack            */
+	INT32 evsd;			/* envelope step for Decay             */
+	INT32 evss;			/* envelope step for Sustain           */
+	INT32 evsr;			/* envelope step for Release           */
+	INT32 TLL;			/* adjusted TotalLevel                 */
+	/* LFO */
+	UINT8 amon;			/* AMS enable flag              */
+	UINT32 ams;			/* AMS depth level of this SLOT */
+}FM_SLOT;
+
+typedef struct fm_chan {
+	FM_SLOT	SLOT[4];
+	UINT8 PAN;			/* PAN :NONE,LEFT,RIGHT or CENTER */
+	UINT8 ALGO;			/* Algorythm                      */
+	UINT8 FB;			/* shift count of self feed back  */
+	INT32 op1_out[2];	/* op1 output for beedback        */
+	/* Algorythm (connection) */
+	INT32 *connect1;		/* pointer of SLOT1 output    */
+	INT32 *connect2;		/* pointer of SLOT2 output    */
+	INT32 *connect3;		/* pointer of SLOT3 output    */
+	INT32 *connect4;		/* pointer of SLOT4 output    */
+	/* LFO */
+	INT32 pms;				/* PMS depth level of channel */
+	UINT32 ams;				/* AMS depth level of channel */
+	/* Phase Generator */
+	UINT32 fc;			/* fnum,blk    :adjusted to sampling rate */
+	UINT8 fn_h;			/* freq latch  :                   */
+	UINT8 kcode;		/* key code    :                   */
+} FM_CH;
+
+/* OPN/OPM common state */
+typedef struct fm_state {
+	UINT8 index;		/* chip index (number of chip) */
+	int clock;			/* master clock  (Hz)  */
+	int rate;			/* sampling rate (Hz)  */
+	double freqbase;	/* frequency base      */
+	double TimerBase;	/* Timer base time     */
+	UINT8 address;		/* address register    */
+	UINT8 irq;			/* interrupt level     */
+	UINT8 irqmask;		/* irq mask            */
+	UINT8 status;		/* status flag         */
+	UINT32 mode;		/* mode  CSM / 3SLOT   */
+	int TA;				/* timer a             */
+	int TAC;			/* timer a counter     */
+	UINT8 TB;			/* timer b             */
+	int TBC;			/* timer b counter     */
+	/* speedup customize */
+	/* local time tables */
+	INT32 DT_TABLE[8][32];	/* DeTune tables       */
+	INT32 AR_TABLE[94];		/* Atttack rate tables */
+	INT32 DR_TABLE[94];		/* Decay rate tables   */
+	/* Extention Timer and IRQ handler */
+	FM_TIMERHANDLER	Timer_Handler;
+	FM_IRQHANDLER	IRQ_Handler;
+	/* timer model single / interval */
+	UINT8 timermodel;
+}FM_ST;
+
+/* -------------------- tables --------------------- */
+
+/* sustain lebel table (3db per step) */
+/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
+#define SC(db) (int)((db*((3/EG_STEP)*(1<<ENV_BITS)))+EG_DST)
+static const int SL_TABLE[16]={
+ SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
+ SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
+};
+#undef SC
+
+/* size of TL_TABLE = sinwave(max cut_off) + cut_off(tl + ksr + envelope + ams) */
+#define TL_MAX (PG_CUT_OFF+EG_CUT_OFF+1)
+
+/* TotalLevel : 48 24 12  6  3 1.5 0.75 (dB) */
+/* TL_TABLE[ 0      to TL_MAX          ] : plus  section */
+/* TL_TABLE[ TL_MAX to TL_MAX+TL_MAX-1 ] : minus section */
+static INT32 *TL_TABLE;
+
+/* pointers to TL_TABLE with sinwave output offset */
+static INT32 *SIN_TABLE[SIN_ENT];
+
+/* envelope output curve table */
+#if FM_SEG_SUPPORT
+/* attack + decay + SSG upside + OFF */
+static INT32 ENV_CURVE[3*EG_ENT+1];
+#else
+/* attack + decay + OFF */
+static INT32 ENV_CURVE[2*EG_ENT+1];
+#endif
+/* envelope counter conversion table when change Decay to Attack phase */
+static int DRAR_TABLE[EG_ENT];
+
+#define OPM_DTTABLE OPN_DTTABLE
+static UINT8 OPN_DTTABLE[4 * 32]={
+/* this table is YM2151 and YM2612 data */
+/* FD=0 */
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+/* FD=1 */
+  0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
+  2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
+/* FD=2 */
+  1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
+  5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
+/* FD=3 */
+  2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
+  8 , 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
+};
+
+/* multiple table */
+#define ML(n) (int)(n*2)
+static const int MUL_TABLE[4*16]= {
+/* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15 */
+   ML(0.50),ML( 1.00),ML( 2.00),ML( 3.00),ML( 4.00),ML( 5.00),ML( 6.00),ML( 7.00),
+   ML(8.00),ML( 9.00),ML(10.00),ML(11.00),ML(12.00),ML(13.00),ML(14.00),ML(15.00),
+/* DT2=1 *SQL(2)   */
+   ML(0.71),ML( 1.41),ML( 2.82),ML( 4.24),ML( 5.65),ML( 7.07),ML( 8.46),ML( 9.89),
+   ML(11.30),ML(12.72),ML(14.10),ML(15.55),ML(16.96),ML(18.37),ML(19.78),ML(21.20),
+/* DT2=2 *SQL(2.5) */
+   ML( 0.78),ML( 1.57),ML( 3.14),ML( 4.71),ML( 6.28),ML( 7.85),ML( 9.42),ML(10.99),
+   ML(12.56),ML(14.13),ML(15.70),ML(17.27),ML(18.84),ML(20.41),ML(21.98),ML(23.55),
+/* DT2=3 *SQL(3)   */
+   ML( 0.87),ML( 1.73),ML( 3.46),ML( 5.19),ML( 6.92),ML( 8.65),ML(10.38),ML(12.11),
+   ML(13.84),ML(15.57),ML(17.30),ML(19.03),ML(20.76),ML(22.49),ML(24.22),ML(25.95)
+};
+#undef ML
+
+#if FM_LFO_SUPPORT
+
+#define PMS_RATE 0x400
+/* LFO runtime work */
+static UINT32 lfo_amd;
+static INT32 lfo_pmd;
+#endif
+
+/* Dummy table of Attack / Decay rate ( use when rate == 0 ) */
+static const INT32 RATE_0[32]=
+{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+/* -------------------- state --------------------- */
+
+/* some globals */
+#define TYPE_SSG    0x01    /* SSG support          */
+#define TYPE_OPN    0x02    /* OPN device           */
+#define TYPE_LFOPAN 0x04    /* OPN type LFO and PAN */
+#define TYPE_6CH    0x08    /* FM 6CH / 3CH         */
+#define TYPE_DAC    0x10    /* YM2612's DAC device  */
+#define TYPE_ADPCM  0x20    /* two ADPCM unit       */
+
+#define TYPE_YM2203 (TYPE_SSG)
+#define TYPE_YM2608 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM)
+#define TYPE_YM2610 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM)
+#define TYPE_YM2612 (TYPE_6CH |TYPE_LFOPAN |TYPE_DAC)
+
+/* current chip state */
+static void *cur_chip = 0;		/* pointer of current chip struct */
+static FM_ST  *State;			/* basic status */
+static FM_CH  *cch[8];			/* pointer of FM channels */
+#if (BUILD_LFO)
+#if FM_LFO_SUPPORT
+static UINT32 LFOCnt,LFOIncr;	/* LFO PhaseGenerator */
+#endif
+#endif
+
+/* runtime work */
+static INT32 out_ch[4];		/* channel output NONE,LEFT,RIGHT or CENTER */
+static INT32 pg_in1,pg_in2,pg_in3,pg_in4;	/* PG input of SLOTs */
+
+/* -------------------- log output  -------------------- */
+/* log output level */
+#define LOG_ERR  3      /* ERROR       */
+#define LOG_WAR  2      /* WARNING     */
+#define LOG_INF  1      /* INFORMATION */
+#define LOG_LEVEL LOG_INF
+
+/* ----- limitter ----- */
+#define Limit(val, max,min) { \
+	if ( val > max )      val = max; \
+	else if ( val < min ) val = min; \
+}
+
+/* ----- buffering one of data(STEREO chip) ----- */
+#if FM_STEREO_MIX
+/* stereo mixing */
+#define FM_BUFFERING_STEREO \
+{														\
+	/* get left & right output with clipping */			\
+	out_ch[OUTD_LEFT]  += out_ch[OUTD_CENTER];				\
+	Limit( out_ch[OUTD_LEFT] , FM_MAXOUT, FM_MINOUT );	\
+	out_ch[OUTD_RIGHT] += out_ch[OUTD_CENTER];				\
+	Limit( out_ch[OUTD_RIGHT], FM_MAXOUT, FM_MINOUT );	\
+	/* buffering */										\
+	*bufL++ = out_ch[OUTD_LEFT] >>FM_OUTSB;				\
+	*bufL++ = out_ch[OUTD_RIGHT]>>FM_OUTSB;				\
+}
+#else
+/* stereo separate */
+#define FM_BUFFERING_STEREO \
+{														\
+	/* get left & right output with clipping */			\
+	out_ch[OUTD_LEFT]  += out_ch[OUTD_CENTER];				\
+	Limit( out_ch[OUTD_LEFT] , FM_MAXOUT, FM_MINOUT );	\
+	out_ch[OUTD_RIGHT] += out_ch[OUTD_CENTER];				\
+	Limit( out_ch[OUTD_RIGHT], FM_MAXOUT, FM_MINOUT );	\
+	/* buffering */										\
+	bufL[i] = out_ch[OUTD_LEFT] >>FM_OUTSB;				\
+	bufR[i] = out_ch[OUTD_RIGHT]>>FM_OUTSB;				\
+}
+#endif
+
+#if FM_INTERNAL_TIMER
+/* ----- internal timer mode , update timer */
+/* ---------- calcrate timer A ---------- */
+#define INTERNAL_TIMER_A(ST,CSM_CH)					\
+{													\
+	if( ST->TAC &&  (ST->Timer_Handler==0) )		\
+		if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 )	\
+		{											\
+			TimerAOver( ST );						\
+			/* CSM mode total level latch and auto key on */	\
+			if( ST->mode & 0x80 )					\
+				CSMKeyControll( CSM_CH );			\
+		}											\
+}
+/* ---------- calcrate timer B ---------- */
+#define INTERNAL_TIMER_B(ST,step)						\
+{														\
+	if( ST->TBC && (ST->Timer_Handler==0) )				\
+		if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 )	\
+			TimerBOver( ST );							\
+}
+#else /* FM_INTERNAL_TIMER */
+/* external timer mode */
+#define INTERNAL_TIMER_A(ST,CSM_CH)
+#define INTERNAL_TIMER_B(ST,step)
+#endif /* FM_INTERNAL_TIMER */
+
+/* --------------------- subroutines  --------------------- */
+/* status set and IRQ handling */
+static __inline__ void FM_STATUS_SET(FM_ST *ST,int flag)
+{
+	/* set status flag */
+	ST->status |= flag;
+	if ( !(ST->irq) && (ST->status & ST->irqmask) )
+	{
+		ST->irq = 1;
+		/* callback user interrupt handler (IRQ is OFF to ON) */
+		if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->index,1);
+	}
+}
+
+/* status reset and IRQ handling */
+static __inline__ void FM_STATUS_RESET(FM_ST *ST,int flag)
+{
+	/* reset status flag */
+	ST->status &=~flag;
+	if ( (ST->irq) && !(ST->status & ST->irqmask) )
+	{
+		ST->irq = 0;
+		/* callback user interrupt handler (IRQ is ON to OFF) */
+		if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->index,0);
+	}
+}
+
+/* IRQ mask set */
+static __inline__ void FM_IRQMASK_SET(FM_ST *ST,int flag)
+{
+	ST->irqmask = flag;
+	/* IRQ handling check */
+	FM_STATUS_SET(ST,0);
+	FM_STATUS_RESET(ST,0);
+}
+
+/* ---------- event hander of Phase Generator ---------- */
+
+/* Release end -> stop counter */
+static void FM_EG_Release( FM_SLOT *SLOT )
+{
+	SLOT->evc = EG_OFF;
+	SLOT->eve = EG_OFF+1;
+	SLOT->evs = 0;
+}
+
+/* SUSTAIN end -> stop counter */
+static void FM_EG_SR( FM_SLOT *SLOT )
+{
+	SLOT->evs = 0;
+	SLOT->evc = EG_OFF;
+	SLOT->eve = EG_OFF+1;
+}
+
+/* Decay end -> Sustain */
+static void FM_EG_DR( FM_SLOT *SLOT )
+{
+	SLOT->eg_next = FM_EG_SR;
+	SLOT->evc = SLOT->SL;
+	SLOT->eve = EG_DED;
+	SLOT->evs = SLOT->evss;
+}
+
+/* Attack end -> Decay */
+static void FM_EG_AR( FM_SLOT *SLOT )
+{
+	/* next DR */
+	SLOT->eg_next = FM_EG_DR;
+	SLOT->evc = EG_DST;
+	SLOT->eve = SLOT->SL;
+	SLOT->evs = SLOT->evsd;
+}
+
+#if FM_SEG_SUPPORT
+static void FM_EG_SSG_SR( FM_SLOT *SLOT );
+
+/* SEG down side end  */
+static void FM_EG_SSG_DR( FM_SLOT *SLOT )
+{
+	if( SLOT->SEG&2){
+		/* reverce */
+		SLOT->eg_next = FM_EG_SSG_SR;
+		SLOT->evc = SLOT->SL + (EG_UST - EG_DST);
+		SLOT->eve = EG_UED;
+		SLOT->evs = SLOT->evss;
+	}else{
+		/* again */
+		SLOT->evc = EG_DST;
+	}
+	/* hold */
+	if( SLOT->SEG&1) SLOT->evs = 0;
+}
+
+/* SEG upside side end */
+static void FM_EG_SSG_SR( FM_SLOT *SLOT )
+{
+	if( SLOT->SEG&2){
+		/* reverce  */
+		SLOT->eg_next = FM_EG_SSG_DR;
+		SLOT->evc = EG_DST;
+		SLOT->eve = EG_DED;
+		SLOT->evs = SLOT->evsd;
+	}else{
+		/* again */
+		SLOT->evc = SLOT->SL + (EG_UST - EG_DST);
+	}
+	/* hold check */
+	if( SLOT->SEG&1) SLOT->evs = 0;
+}
+
+/* SEG Attack end */
+static void FM_EG_SSG_AR( FM_SLOT *SLOT )
+{
+	if( SLOT->SEG&4){	/* start direction */
+		/* next SSG-SR (upside start ) */
+		SLOT->eg_next = FM_EG_SSG_SR;
+		SLOT->evc = SLOT->SL + (EG_UST - EG_DST);
+		SLOT->eve = EG_UED;
+		SLOT->evs = SLOT->evss;
+	}else{
+		/* next SSG-DR (downside start ) */
+		SLOT->eg_next = FM_EG_SSG_DR;
+		SLOT->evc = EG_DST;
+		SLOT->eve = EG_DED;
+		SLOT->evs = SLOT->evsd;
+	}
+}
+#endif /* FM_SEG_SUPPORT */
+
+/* ----- key on of SLOT ----- */
+#define FM_KEY_IS(SLOT) ((SLOT)->eg_next!=FM_EG_Release)
+
+static __inline__ void FM_KEYON(FM_CH *CH , int s )
+{
+	FM_SLOT *SLOT = &CH->SLOT[s];
+	if( !FM_KEY_IS(SLOT) )
+	{
+		/* restart Phage Generator */
+		SLOT->Cnt = 0;
+		/* phase -> Attack */
+#if FM_SEG_SUPPORT
+		if( SLOT->SEG&8 ) SLOT->eg_next = FM_EG_SSG_AR;
+		else
+#endif
+		SLOT->eg_next = FM_EG_AR;
+		SLOT->evs     = SLOT->evsa;
+#if 0
+		/* convert decay count to attack count */
+		/* --- This caused the problem by credit sound of paper boy. --- */
+		SLOT->evc = EG_AST + DRAR_TABLE[ENV_CURVE[SLOT->evc>>ENV_BITS]];/* + SLOT->evs;*/
+#else
+		/* reset attack counter */
+		SLOT->evc = EG_AST;
+#endif
+		SLOT->eve = EG_AED;
+	}
+}
+/* ----- key off of SLOT ----- */
+static __inline__ void FM_KEYOFF(FM_CH *CH , int s )
+{
+	FM_SLOT *SLOT = &CH->SLOT[s];
+	if( FM_KEY_IS(SLOT) )
+	{
+		/* if Attack phase then adjust envelope counter */
+		if( SLOT->evc < EG_DST )
+			SLOT->evc = (ENV_CURVE[SLOT->evc>>ENV_BITS]<<ENV_BITS) + EG_DST;
+		/* phase -> Release */
+		SLOT->eg_next = FM_EG_Release;
+		SLOT->eve     = EG_DED;
+		SLOT->evs     = SLOT->evsr;
+	}
+}
+
+/* setup Algorythm and PAN connection */
+static void setup_connection( FM_CH *CH )
+{
+	INT32 *carrier = &out_ch[CH->PAN]; /* NONE,LEFT,RIGHT or CENTER */
+
+	switch( CH->ALGO ){
+	case 0:
+		/*  PG---S1---S2---S3---S4---OUT */
+		CH->connect1 = &pg_in2;
+		CH->connect2 = &pg_in3;
+		CH->connect3 = &pg_in4;
+		break;
+	case 1:
+		/*  PG---S1-+-S3---S4---OUT */
+		/*  PG---S2-+               */
+		CH->connect1 = &pg_in3;
+		CH->connect2 = &pg_in3;
+		CH->connect3 = &pg_in4;
+		break;
+	case 2:
+		/* PG---S1------+-S4---OUT */
+		/* PG---S2---S3-+          */
+		CH->connect1 = &pg_in4;
+		CH->connect2 = &pg_in3;
+		CH->connect3 = &pg_in4;
+		break;
+	case 3:
+		/* PG---S1---S2-+-S4---OUT */
+		/* PG---S3------+          */
+		CH->connect1 = &pg_in2;
+		CH->connect2 = &pg_in4;
+		CH->connect3 = &pg_in4;
+		break;
+	case 4:
+		/* PG---S1---S2-+--OUT */
+		/* PG---S3---S4-+      */
+		CH->connect1 = &pg_in2;
+		CH->connect2 = carrier;
+		CH->connect3 = &pg_in4;
+		break;
+	case 5:
+		/*         +-S2-+     */
+		/* PG---S1-+-S3-+-OUT */
+		/*         +-S4-+     */
+		CH->connect1 = 0;	/* special case */
+		CH->connect2 = carrier;
+		CH->connect3 = carrier;
+		break;
+	case 6:
+		/* PG---S1---S2-+     */
+		/* PG--------S3-+-OUT */
+		/* PG--------S4-+     */
+		CH->connect1 = &pg_in2;
+		CH->connect2 = carrier;
+		CH->connect3 = carrier;
+		break;
+	case 7:
+		/* PG---S1-+     */
+		/* PG---S2-+-OUT */
+		/* PG---S3-+     */
+		/* PG---S4-+     */
+		CH->connect1 = carrier;
+		CH->connect2 = carrier;
+		CH->connect3 = carrier;
+	}
+	CH->connect4 = carrier;
+}
+
+/* set detune & multiple */
+static __inline__ void set_det_mul(FM_ST *ST,FM_CH *CH,FM_SLOT *SLOT,int v)
+{
+	SLOT->mul = MUL_TABLE[v&0x0f];
+	SLOT->DT  = ST->DT_TABLE[(v>>4)&7];
+	CH->SLOT[SLOT1].Incr=-1;
+}
+
+/* set total level */
+static __inline__ void set_tl(FM_CH *CH,FM_SLOT *SLOT , int v,int csmflag)
+{
+	v &= 0x7f;
+	v = (v<<7)|v; /* 7bit -> 14bit */
+	SLOT->TL = (v*EG_ENT)>>14;
+	/* if it is not a CSM channel , latch the total level */
+	if( !csmflag )
+		SLOT->TLL = SLOT->TL;
+}
+
+/* set attack rate & key scale  */
+static __inline__ void set_ar_ksr(FM_CH *CH,FM_SLOT *SLOT,int v,INT32 *ar_table)
+{
+	SLOT->KSR  = 3-(v>>6);
+	SLOT->AR   = (v&=0x1f) ? &ar_table[v<<1] : RATE_0;
+	SLOT->evsa = SLOT->AR[SLOT->ksr];
+	if( SLOT->eg_next == FM_EG_AR ) SLOT->evs = SLOT->evsa;
+	CH->SLOT[SLOT1].Incr=-1;
+}
+/* set decay rate */
+static __inline__ void set_dr(FM_SLOT *SLOT,int v,INT32 *dr_table)
+{
+	SLOT->DR = (v&=0x1f) ? &dr_table[v<<1] : RATE_0;
+	SLOT->evsd = SLOT->DR[SLOT->ksr];
+	if( SLOT->eg_next == FM_EG_DR ) SLOT->evs = SLOT->evsd;
+}
+/* set sustain rate */
+static __inline__ void set_sr(FM_SLOT *SLOT,int v,INT32 *dr_table)
+{
+	SLOT->SR = (v&=0x1f) ? &dr_table[v<<1] : RATE_0;
+	SLOT->evss = SLOT->SR[SLOT->ksr];
+	if( SLOT->eg_next == FM_EG_SR ) SLOT->evs = SLOT->evss;
+}
+/* set release rate */
+static __inline__ void set_sl_rr(FM_SLOT *SLOT,int v,INT32 *dr_table)
+{
+	SLOT->SL = SL_TABLE[(v>>4)];
+	SLOT->RR = &dr_table[((v&0x0f)<<2)|2];
+	SLOT->evsr = SLOT->RR[SLOT->ksr];
+	if( SLOT->eg_next == FM_EG_Release ) SLOT->evs = SLOT->evsr;
+}
+
+/* operator output calcrator */
+#define OP_OUT(PG,EG)   SIN_TABLE[(PG/(0x1000000/SIN_ENT))&(SIN_ENT-1)][EG]
+#define OP_OUTN(PG,EG)  NOISE_TABLE[(PG/(0x1000000/SIN_ENT))&(SIN_ENT-1)][EG]
+
+/* eg calcration */
+#if FM_LFO_SUPPORT
+#define FM_CALC_EG(OUT,SLOT)						\
+{													\
+	if( (SLOT.evc += SLOT.evs) >= SLOT.eve) 		\
+		SLOT.eg_next(&(SLOT));						\
+	OUT = SLOT.TLL+ENV_CURVE[SLOT.evc>>ENV_BITS];	\
+	if(SLOT.ams)									\
+		OUT += (SLOT.ams*lfo_amd/LFO_RATE);			\
+}
+#else
+#define FM_CALC_EG(OUT,SLOT)						\
+{													\
+	if( (SLOT.evc += SLOT.evs) >= SLOT.eve) 		\
+		SLOT.eg_next(&(SLOT));						\
+	OUT = SLOT.TLL+ENV_CURVE[SLOT.evc>>ENV_BITS];	\
+}
+#endif
+
+/* ---------- calcrate one of channel ---------- */
+static __inline__ void FM_CALC_CH( FM_CH *CH )
+{
+	UINT32 eg_out1,eg_out2,eg_out3,eg_out4;  //envelope output
+
+	/* Phase Generator */
+#if FM_LFO_SUPPORT
+	INT32 pms = lfo_pmd * CH->pms / LFO_RATE;
+	if(pms)
+	{
+		pg_in1 = (CH->SLOT[SLOT1].Cnt += CH->SLOT[SLOT1].Incr + (INT32)(pms * CH->SLOT[SLOT1].Incr) / PMS_RATE);
+		pg_in2 = (CH->SLOT[SLOT2].Cnt += CH->SLOT[SLOT2].Incr + (INT32)(pms * CH->SLOT[SLOT2].Incr) / PMS_RATE);
+		pg_in3 = (CH->SLOT[SLOT3].Cnt += CH->SLOT[SLOT3].Incr + (INT32)(pms * CH->SLOT[SLOT3].Incr) / PMS_RATE);
+		pg_in4 = (CH->SLOT[SLOT4].Cnt += CH->SLOT[SLOT4].Incr + (INT32)(pms * CH->SLOT[SLOT4].Incr) / PMS_RATE);
+	}
+	else
+#endif
+	{
+		pg_in1 = (CH->SLOT[SLOT1].Cnt += CH->SLOT[SLOT1].Incr);
+		pg_in2 = (CH->SLOT[SLOT2].Cnt += CH->SLOT[SLOT2].Incr);
+		pg_in3 = (CH->SLOT[SLOT3].Cnt += CH->SLOT[SLOT3].Incr);
+		pg_in4 = (CH->SLOT[SLOT4].Cnt += CH->SLOT[SLOT4].Incr);
+	}
+
+	/* Envelope Generator */
+	FM_CALC_EG(eg_out1,CH->SLOT[SLOT1]);
+	FM_CALC_EG(eg_out2,CH->SLOT[SLOT2]);
+	FM_CALC_EG(eg_out3,CH->SLOT[SLOT3]);
+	FM_CALC_EG(eg_out4,CH->SLOT[SLOT4]);
+
+	/* Connection */
+	if( eg_out1 < EG_CUT_OFF )	/* SLOT 1 */
+	{
+		if( CH->FB ){
+			/* with self feed back */
+			pg_in1 += (CH->op1_out[0]+CH->op1_out[1])>>CH->FB;
+			CH->op1_out[1] = CH->op1_out[0];
+		}
+		CH->op1_out[0] = OP_OUT(pg_in1,eg_out1);
+		/* output slot1 */
+		if( !CH->connect1 )
+		{
+			/* algorythm 5  */
+			pg_in2 += CH->op1_out[0];
+			pg_in3 += CH->op1_out[0];
+			pg_in4 += CH->op1_out[0];
+		}else{
+			/* other algorythm */
+			*CH->connect1 += CH->op1_out[0];
+		}
+	}
+	if( eg_out2 < EG_CUT_OFF )	/* SLOT 2 */
+		*CH->connect2 += OP_OUT(pg_in2,eg_out2);
+	if( eg_out3 < EG_CUT_OFF )	/* SLOT 3 */
+		*CH->connect3 += OP_OUT(pg_in3,eg_out3);
+	if( eg_out4 < EG_CUT_OFF )	/* SLOT 4 */
+		*CH->connect4 += OP_OUT(pg_in4,eg_out4);
+}
+/* ---------- frequency counter for operater update ---------- */
+static __inline__ void CALC_FCSLOT(FM_SLOT *SLOT , int fc , int kc )
+{
+	int ksr;
+
+	/* frequency step counter */
+	SLOT->Incr= (fc+SLOT->DT[kc])*SLOT->mul;	/* verified on real chip */
+	/*	SLOT->Incr= fc*SLOT->mul + SLOT->DT[kc]; */
+	ksr = kc >> SLOT->KSR;
+	if( SLOT->ksr != ksr )
+	{
+		SLOT->ksr = ksr;
+		/* attack , decay rate recalcration */
+		SLOT->evsa = SLOT->AR[ksr];
+		SLOT->evsd = SLOT->DR[ksr];
+		SLOT->evss = SLOT->SR[ksr];
+		SLOT->evsr = SLOT->RR[ksr];
+	}
+}
+
+/* ---------- frequency counter  ---------- */
+static __inline__ void OPN_CALC_FCOUNT(FM_CH *CH )
+{
+	if( CH->SLOT[SLOT1].Incr==-1){
+		int fc = CH->fc;
+		int kc = CH->kcode;
+		CALC_FCSLOT(&CH->SLOT[SLOT1] , fc , kc );
+		CALC_FCSLOT(&CH->SLOT[SLOT2] , fc , kc );
+		CALC_FCSLOT(&CH->SLOT[SLOT3] , fc , kc );
+		CALC_FCSLOT(&CH->SLOT[SLOT4] , fc , kc );
+	}
+}
+
+/* ----------- initialize time tabls ----------- */
+static void init_timetables( FM_ST *ST , UINT8 *DTTABLE , int ARRATE , int DRRATE )
+{
+	int i,d;
+	double rate;
+
+	/* DeTune table */
+	for (d = 0;d <= 3;d++){
+		for (i = 0;i <= 31;i++){
+			rate = (double)DTTABLE[d*32 + i] * ST->freqbase * FREQ_RATE;
+			ST->DT_TABLE[d][i]   = (INT32) rate;
+			ST->DT_TABLE[d+4][i] = (INT32)-rate;
+		}
+	}
+	/* make Attack & Decay tables */
+	for (i = 0;i < 4;i++) ST->AR_TABLE[i] = ST->DR_TABLE[i] = 0;
+	for (i = 4;i < 64;i++){
+		rate  = ST->freqbase;						/* frequency rate */
+		if( i < 60 ) rate *= 1.0+(i&3)*0.25;		/* b0-1 : x1 , x1.25 , x1.5 , x1.75 */
+		rate *= 1<<((i>>2)-1);						/* b2-5 : shift bit */
+		rate *= (double)(EG_ENT<<ENV_BITS);
+		ST->AR_TABLE[i] = (INT32)(rate / ARRATE);
+		ST->DR_TABLE[i] = (INT32)(rate / DRRATE);
+	}
+	ST->AR_TABLE[62] = EG_AED;
+	ST->AR_TABLE[63] = EG_AED;
+	for (i = 64;i < 94 ;i++){	/* make for overflow area */
+		ST->AR_TABLE[i] = ST->AR_TABLE[63];
+		ST->DR_TABLE[i] = ST->DR_TABLE[63];
+	}
+
+}
+
+/* ---------- reset one of channel  ---------- */
+static void reset_channel( FM_ST *ST , FM_CH *CH , int chan )
+{
+	int c,s;
+
+	ST->mode   = 0;	/* normal mode */
+	FM_STATUS_RESET(ST,0xff);
+	ST->TA     = 0;
+	ST->TAC    = 0;
+	ST->TB     = 0;
+	ST->TBC    = 0;
+
+	for( c = 0 ; c < chan ; c++ )
+	{
+		CH[c].fc = 0;
+		CH[c].PAN = OUTD_CENTER;
+		for(s = 0 ; s < 4 ; s++ )
+		{
+			CH[c].SLOT[s].SEG = 0;
+			CH[c].SLOT[s].eg_next= FM_EG_Release;
+			CH[c].SLOT[s].evc = EG_OFF;
+			CH[c].SLOT[s].eve = EG_OFF+1;
+			CH[c].SLOT[s].evs = 0;
+		}
+	}
+}
+
+
+/* ---------- generic table initialize ---------- */
+static int FMInitTable( void )
+{
+	int s,t;
+	double rate;
+	int i,j;
+	double pom;
+
+	/* allocate total level table plus+minus section */
+	TL_TABLE = (INT32 *)emu_Malloc(2*TL_MAX*sizeof(int));
+	if( TL_TABLE == 0 ) return 0;
+	/* make total level table */
+	for (t = 0;t < TL_MAX ;t++){
+		if(t >= PG_CUT_OFF)
+			rate = 0;	/* under cut off area */
+		else
+			rate = ((1<<TL_BITS)-1)/pow(10,EG_STEP*t/20);	/* dB -> voltage */
+		TL_TABLE[       t] =  (int)rate;
+		TL_TABLE[TL_MAX+t] = -TL_TABLE[t];
+	}
+
+	/* make sinwave table (pointer of total level) */
+	for (s = 1;s <= SIN_ENT/4;s++){
+		pom = sin(2.0*PI*s/SIN_ENT); /* sin   */
+		pom = 20*log10(1/pom);	     /* -> decibel */
+		j = (int)(pom / EG_STEP);    /* TL_TABLE steps */
+		/* cut off check */
+		if(j > PG_CUT_OFF)
+			j = PG_CUT_OFF;
+		/* degree 0   -  90    , degree 180 -  90 : plus section */
+		SIN_TABLE[          s] = SIN_TABLE[SIN_ENT/2-s] = &TL_TABLE[j];
+		/* degree 180 - 270    , degree 360 - 270 : minus section */
+		SIN_TABLE[SIN_ENT/2+s] = SIN_TABLE[SIN_ENT  -s] = &TL_TABLE[TL_MAX+j];
+
+	}
+	/* degree 0 = degree 180                   = off */
+	SIN_TABLE[0] = SIN_TABLE[SIN_ENT/2]        = &TL_TABLE[PG_CUT_OFF];
+
+	/* envelope counter -> envelope output table */
+	for (i=0; i<EG_ENT; i++)
+	{
+		/* ATTACK curve */
+		/* !!!!! preliminary !!!!! */
+		pom = pow( ((double)(EG_ENT-1-i)/EG_ENT) , 8 ) * EG_ENT;
+		/* if( pom >= EG_ENT ) pom = EG_ENT-1; */
+		ENV_CURVE[i] = (int)pom;
+		/* DECAY ,RELEASE curve */
+		ENV_CURVE[(EG_DST>>ENV_BITS)+i]= i;
+#if FM_SEG_SUPPORT
+		/* DECAY UPSIDE (SSG ENV) */
+		ENV_CURVE[(EG_UST>>ENV_BITS)+i]= EG_ENT-1-i;
+#endif
+	}
+	/* off */
+	ENV_CURVE[EG_OFF>>ENV_BITS]= EG_ENT-1;
+
+	/* decay to reattack envelope converttable */
+	j = EG_ENT-1;
+	for (i=0; i<EG_ENT; i++)
+	{
+		while( j && (ENV_CURVE[j] < i) ) j--;
+		DRAR_TABLE[i] = j<<ENV_BITS;
+
+	}
+	return 1;
+}
+
+
+static void FMCloseTable( void )
+{
+	if( TL_TABLE ) emu_Free( TL_TABLE );
+	return;
+}
+
+/* OPN/OPM Mode  Register Write */
+static __inline__ void FMSetMode( FM_ST *ST ,int n,int v )
+{
+	/* b7 = CSM MODE */
+	/* b6 = 3 slot mode */
+	/* b5 = reset b */
+	/* b4 = reset a */
+	/* b3 = timer enable b */
+	/* b2 = timer enable a */
+	/* b1 = load b */
+	/* b0 = load a */
+	ST->mode = v;
+
+	/* reset Timer b flag */
+	if( v & 0x20 )
+		FM_STATUS_RESET(ST,0x02);
+	/* reset Timer a flag */
+	if( v & 0x10 )
+		FM_STATUS_RESET(ST,0x01);
+	/* load b */
+	if( v & 0x02 )
+	{
+		if( ST->TBC == 0 )
+		{
+			ST->TBC = ( 256-ST->TB)<<4;
+			/* External timer handler */
+			if (ST->Timer_Handler) (ST->Timer_Handler)(n,1,ST->TBC,ST->TimerBase);
+		}
+	}else if (ST->timermodel == FM_TIMER_INTERVAL)
+	{	/* stop interbval timer */
+		if( ST->TBC != 0 )
+		{
+			ST->TBC = 0;
+			if (ST->Timer_Handler) (ST->Timer_Handler)(n,1,0,ST->TimerBase);
+		}
+	}
+	/* load a */
+	if( v & 0x01 )
+	{
+		if( ST->TAC == 0 )
+		{
+			ST->TAC = (1024-ST->TA);
+			/* External timer handler */
+			if (ST->Timer_Handler) (ST->Timer_Handler)(n,0,ST->TAC,ST->TimerBase);
+		}
+	}else if (ST->timermodel == FM_TIMER_INTERVAL)
+	{	/* stop interbval timer */
+		if( ST->TAC != 0 )
+		{
+			ST->TAC = 0;
+			if (ST->Timer_Handler) (ST->Timer_Handler)(n,0,0,ST->TimerBase);
+		}
+	}
+}
+
+/* Timer A Overflow */
+static __inline__ void TimerAOver(FM_ST *ST)
+{
+	/* status set if enabled */
+	if(ST->mode & 0x04) FM_STATUS_SET(ST,0x01);
+	/* clear or reload the counter */
+	if (ST->timermodel == FM_TIMER_INTERVAL)
+	{
+		ST->TAC = (1024-ST->TA);
+		if (ST->Timer_Handler) (ST->Timer_Handler)(ST->index,0,ST->TAC,ST->TimerBase);
+	}
+	else ST->TAC = 0;
+}
+/* Timer B Overflow */
+static __inline__ void TimerBOver(FM_ST *ST)
+{
+	/* status set if enabled */
+	if(ST->mode & 0x08) FM_STATUS_SET(ST,0x02);
+	/* clear or reload the counter */
+	if (ST->timermodel == FM_TIMER_INTERVAL)
+	{
+		ST->TBC = ( 256-ST->TB)<<4;
+		if (ST->Timer_Handler) (ST->Timer_Handler)(ST->index,1,ST->TBC,ST->TimerBase);
+	}
+	else ST->TBC = 0;
+}
+/* CSM Key Controll */
+static __inline__ void CSMKeyControll(FM_CH *CH)
+{
+	/* all key off */
+	/* FM_KEYOFF(CH,SLOT1); */
+	/* FM_KEYOFF(CH,SLOT2); */
+	/* FM_KEYOFF(CH,SLOT3); */
+	/* FM_KEYOFF(CH,SLOT4); */
+	/* total level latch */
+	CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL;
+	CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL;
+	CH->SLOT[SLOT3].TLL = CH->SLOT[SLOT3].TL;
+	CH->SLOT[SLOT4].TLL = CH->SLOT[SLOT4].TL;
+	/* all key on */
+	FM_KEYON(CH,SLOT1);
+	FM_KEYON(CH,SLOT2);
+	FM_KEYON(CH,SLOT3);
+	FM_KEYON(CH,SLOT4);
+}
+
+#if BUILD_OPN
+/***********************************************************/
+/* OPN unit                                                */
+/***********************************************************/
+
+/* OPN 3slot struct */
+typedef struct opn_3slot {
+	UINT32  fc[3];		/* fnum3,blk3  :calcrated */
+	UINT8 fn_h[3];		/* freq3 latch            */
+	UINT8 kcode[3];		/* key code    :          */
+}FM_3SLOT;
+
+/* OPN/A/B common state */
+typedef struct opn_f {
+	UINT8 type;		/* chip type         */
+	FM_ST ST;				/* general state     */
+	FM_3SLOT SL3;			/* 3 slot mode state */
+	FM_CH *P_CH;			/* pointer of CH     */
+	UINT32 FN_TABLE[2048]; /* fnumber -> increment counter */
+#if FM_LFO_SUPPORT
+	/* LFO */
+	UINT32 LFOCnt;
+	UINT32 LFOIncr;
+	UINT32 LFO_FREQ[8];/* LFO FREQ table */
+#endif
+} FM_OPN;
+
+/* OPN key frequency number -> key code follow table */
+/* fnum higher 4bit -> keycode lower 2bit */
+static const UINT8 OPN_FKTABLE[16]={0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
+
+#if FM_LFO_SUPPORT
+/* OPN LFO waveform table */
+static INT32 OPN_LFO_wave[LFO_ENT];
+#endif
+
+static int OPNInitTable(void)
+{
+	int i;
+
+#if FM_LFO_SUPPORT
+	/* LFO wave table */
+	for(i=0;i<LFO_ENT;i++)
+	{
+		OPN_LFO_wave[i]= i<LFO_ENT/2 ? i*LFO_RATE/(LFO_ENT/2) : (LFO_ENT-i)*LFO_RATE/(LFO_ENT/2);
+	}
+#endif
+	return FMInitTable();
+}
+
+/* ---------- priscaler set(and make time tables) ---------- */
+static void OPNSetPris(FM_OPN *OPN , int pris , int TimerPris, int SSGpris)
+{
+	int i;
+
+	/* frequency base */
+	OPN->ST.freqbase = (OPN->ST.rate) ? ((double)OPN->ST.clock / OPN->ST.rate) / pris : 0;
+	/* Timer base time */
+	OPN->ST.TimerBase = 1.0/((double)OPN->ST.clock / (double)TimerPris);
+//  /* SSG part  priscaler set */
+//  if( SSGpris ) SSGClk( OPN->ST.index, OPN->ST.clock * 2 / SSGpris );
+	/* make time tables */
+	init_timetables( &OPN->ST , OPN_DTTABLE , OPN_ARRATE , OPN_DRRATE );
+	/* make fnumber -> increment counter table */
+	for( i=0 ; i < 2048 ; i++ )
+	{
+		/* it is freq table for octave 7 */
+		/* opn freq counter = 20bit */
+		OPN->FN_TABLE[i] = (UINT32)( (double)i * OPN->ST.freqbase * FREQ_RATE * (1<<7) / 2 );
+	}
+#if FM_LFO_SUPPORT
+	/* LFO freq. table */
+	{
+		/* 3.98Hz,5.56Hz,6.02Hz,6.37Hz,6.88Hz,9.63Hz,48.1Hz,72.2Hz @ 8MHz */
+#define FM_LF(Hz) ((double)LFO_ENT*(1<<LFO_SHIFT)*(Hz)/(8000000.0/144))
+		static const double freq_table[8] = { FM_LF(3.98),FM_LF(5.56),FM_LF(6.02),FM_LF(6.37),FM_LF(6.88),FM_LF(9.63),FM_LF(48.1),FM_LF(72.2) };
+#undef FM_LF
+		for(i=0;i<8;i++)
+		{
+			OPN->LFO_FREQ[i] = (UINT32)(freq_table[i] * OPN->ST.freqbase);
+		}
+	}
+#endif
+
+}
+
+/* ---------- write a OPN mode register 0x20-0x2f ---------- */
+static void OPNWriteMode(FM_OPN *OPN, int r, int v)
+{
+	UINT8 c;
+	FM_CH *CH;
+
+	switch(r){
+	case 0x21:	/* Test */
+		break;
+#if FM_LFO_SUPPORT
+	case 0x22:	/* LFO FREQ (YM2608/YM2612) */
+		if( OPN->type & TYPE_LFOPAN )
+		{
+			OPN->LFOIncr = (v&0x08) ? OPN->LFO_FREQ[v&7] : 0;
+			cur_chip = NULL;
+		}
+		break;
+#endif
+	case 0x24:	/* timer A High 8*/
+		OPN->ST.TA = (OPN->ST.TA & 0x03)|(((int)v)<<2);
+		break;
+	case 0x25:	/* timer A Low 2*/
+		OPN->ST.TA = (OPN->ST.TA & 0x3fc)|(v&3);
+		break;
+	case 0x26:	/* timer B */
+		OPN->ST.TB = v;
+		break;
+	case 0x27:	/* mode , timer controll */
+		FMSetMode( &(OPN->ST),OPN->ST.index,v );
+		break;
+	case 0x28:	/* key on / off */
+		c = v&0x03;
+		if( c == 3 ) break;
+		if( (v&0x04) && (OPN->type & TYPE_6CH) ) c+=3;
+		CH = OPN->P_CH;
+		CH = &CH[c];
+		/* csm mode */
+		/* if( c == 2 && (OPN->ST.mode & 0x80) ) break; */
+		if(v&0x10) FM_KEYON(CH,SLOT1); else FM_KEYOFF(CH,SLOT1);
+		if(v&0x20) FM_KEYON(CH,SLOT2); else FM_KEYOFF(CH,SLOT2);
+		if(v&0x40) FM_KEYON(CH,SLOT3); else FM_KEYOFF(CH,SLOT3);
+		if(v&0x80) FM_KEYON(CH,SLOT4); else FM_KEYOFF(CH,SLOT4);
+
+		break;
+	}
+}
+
+/* ---------- write a OPN register (0x30-0xff) ---------- */
+static void OPNWriteReg(FM_OPN *OPN, int r, int v)
+{
+	UINT8 c;
+	FM_CH *CH;
+	FM_SLOT *SLOT;
+
+	/* 0x30 - 0xff */
+	if( (c = OPN_CHAN(r)) == 3 ) return; /* 0xX3,0xX7,0xXB,0xXF */
+	if( (r >= 0x100) /* && (OPN->type & TYPE_6CH) */ ) c+=3;
+		CH = OPN->P_CH;
+		CH = &CH[c];
+
+	SLOT = &(CH->SLOT[OPN_SLOT(r)]);
+	switch( r & 0xf0 ) {
+	case 0x30:	/* DET , MUL */
+		set_det_mul(&OPN->ST,CH,SLOT,v);
+		break;
+	case 0x40:	/* TL */
+		set_tl(CH,SLOT,v,(c == 2) && (OPN->ST.mode & 0x80) );
+		break;
+	case 0x50:	/* KS, AR */
+		set_ar_ksr(CH,SLOT,v,OPN->ST.AR_TABLE);
+		break;
+	case 0x60:	/*     DR */
+		/* bit7 = AMS_ON ENABLE(YM2612) */
+		set_dr(SLOT,v,OPN->ST.DR_TABLE);
+#if FM_LFO_SUPPORT
+		if( OPN->type & TYPE_LFOPAN)
+		{
+			SLOT->amon = v>>7;
+			SLOT->ams = CH->ams * SLOT->amon;
+		}
+#endif
+		break;
+	case 0x70:	/*     SR */
+		set_sr(SLOT,v,OPN->ST.DR_TABLE);
+		break;
+	case 0x80:	/* SL, RR */
+		set_sl_rr(SLOT,v,OPN->ST.DR_TABLE);
+		break;
+	case 0x90:	/* SSG-EG */
+		SLOT->SEG = v&0x0f;
+		break;
+	case 0xa0:
+		switch( OPN_SLOT(r) ){
+		case 0:		/* 0xa0-0xa2 : FNUM1 */
+			{
+				UINT32 fn  = (((UINT32)( (CH->fn_h)&7))<<8) + v;
+				UINT8 blk = CH->fn_h>>3;
+				/* make keyscale code */
+				CH->kcode = (blk<<2)|OPN_FKTABLE[(fn>>7)];
+				/* make basic increment counter 32bit = 1 cycle */
+				CH->fc = OPN->FN_TABLE[fn]>>(7-blk);
+				CH->SLOT[SLOT1].Incr=-1;
+			}
+			break;
+		case 1:		/* 0xa4-0xa6 : FNUM2,BLK */
+			CH->fn_h = v&0x3f;
+			break;
+		case 2:		/* 0xa8-0xaa : 3CH FNUM1 */
+			if( r < 0x100)
+			{
+				UINT32 fn  = (((UINT32)(OPN->SL3.fn_h[c]&7))<<8) + v;
+				UINT8 blk = OPN->SL3.fn_h[c]>>3;
+				/* make keyscale code */
+				OPN->SL3.kcode[c]= (blk<<2)|OPN_FKTABLE[(fn>>7)];
+				/* make basic increment counter 32bit = 1 cycle */
+				OPN->SL3.fc[c] = OPN->FN_TABLE[fn]>>(7-blk);
+				(OPN->P_CH)[2].SLOT[SLOT1].Incr=-1;
+			}
+			break;
+		case 3:		/* 0xac-0xae : 3CH FNUM2,BLK */
+			if( r < 0x100)
+				OPN->SL3.fn_h[c] = v&0x3f;
+			break;
+		}
+		break;
+	case 0xb0:
+		switch( OPN_SLOT(r) ){
+		case 0:		/* 0xb0-0xb2 : FB,ALGO */
+			{
+				int feedback = (v>>3)&7;
+				CH->ALGO = v&7;
+				CH->FB   = feedback ? 8+1 - feedback : 0;
+				setup_connection( CH );
+			}
+			break;
+		case 1:		/* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2608) */
+			if( OPN->type & TYPE_LFOPAN)
+			{
+#if FM_LFO_SUPPORT
+				/* b0-2 PMS */
+				/* 0,3.4,6.7,10,14,20,40,80(cent) */
+				static const double pmd_table[8]={0,3.4,6.7,10,14,20,40,80};
+				static const int amd_table[4]={(int)(0/EG_STEP),(int)(1.4/EG_STEP),(int)(5.9/EG_STEP),(int)(11.8/EG_STEP) };
+				CH->pms = (INT32)( (1.5/1200.0)*pmd_table[v & 7] * PMS_RATE);
+				/* b4-5 AMS */
+				/* 0 , 1.4 , 5.9 , 11.8(dB) */
+				CH->ams = amd_table[(v>>4) & 0x03];
+				CH->SLOT[SLOT1].ams = CH->ams * CH->SLOT[SLOT1].amon;
+				CH->SLOT[SLOT2].ams = CH->ams * CH->SLOT[SLOT2].amon;
+				CH->SLOT[SLOT3].ams = CH->ams * CH->SLOT[SLOT3].amon;
+				CH->SLOT[SLOT4].ams = CH->ams * CH->SLOT[SLOT4].amon;
+#endif
+				/* PAN */
+				CH->PAN = (v>>6)&0x03; /* PAN : b6 = R , b7 = L */
+				setup_connection( CH );
+
+			}
+			break;
+		}
+		break;
+	}
+}
+#endif /* BUILD_OPN */
+
+#if BUILD_YM2612
+/*******************************************************************************/
+/*		YM2612 local section                                                   */
+/*******************************************************************************/
+/* here's the virtual YM2612 */
+typedef struct ym2612_f {
+	FM_OPN OPN;						/* OPN state       */
+	FM_CH CH[6];					/* channel state */
+	int address1;	/* address register1 */
+	/* dac output (YM2612) */
+	int dacen;
+	int dacout;
+} YM2612;
+
+static int YM2612NumChips;	/* total chip */
+static YM2612 *FM2612=NULL;	/* array of YM2612's */
+
+static int dacen;
+
+/* ---------- update one of chip ----------- */
+void YM2612UpdateOne(int num, INT16 **buffer, int length)
+{
+	YM2612 *F2612 = &(FM2612[num]);
+	FM_OPN *OPN   = &(FM2612[num].OPN);
+	int i;
+	FM_CH *ch,*ech;
+	FMSAMPLE  *bufL,*bufR;
+	int dacout  = F2612->dacout;
+
+	/* set bufer */
+	bufL = buffer[0];
+	bufR = buffer[1];
+
+	if( (void *)F2612 != cur_chip ){
+		cur_chip = (void *)F2612;
+
+		State = &OPN->ST;
+		cch[0]   = &F2612->CH[0];
+		cch[1]   = &F2612->CH[1];
+		cch[2]   = &F2612->CH[2];
+		cch[3]   = &F2612->CH[3];
+		cch[4]   = &F2612->CH[4];
+		cch[5]   = &F2612->CH[5];
+		/* DAC mode */
+		dacen = F2612->dacen;
+#if FM_LFO_SUPPORT
+		LFOCnt  = OPN->LFOCnt;
+		LFOIncr = OPN->LFOIncr;
+		if( !LFOIncr ) lfo_amd = lfo_pmd = 0;
+#endif
+	}
+	/* update frequency counter */
+	OPN_CALC_FCOUNT( cch[0] );
+	OPN_CALC_FCOUNT( cch[1] );
+	if( (State->mode & 0xc0) ){
+		/* 3SLOT MODE */
+		if( cch[2]->SLOT[SLOT1].Incr==-1){
+			/* 3 slot mode */
+			CALC_FCSLOT(&cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
+			CALC_FCSLOT(&cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
+			CALC_FCSLOT(&cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
+			CALC_FCSLOT(&cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
+		}
+	}else OPN_CALC_FCOUNT( cch[2] );
+	OPN_CALC_FCOUNT( cch[3] );
+	OPN_CALC_FCOUNT( cch[4] );
+	OPN_CALC_FCOUNT( cch[5] );
+
+	ech = dacen ? cch[4] : cch[5];
+	/* buffering */
+    for( i=0; i < length ; i++ )
+	{
+#if FM_LFO_SUPPORT
+		/* LFO */
+		if( LFOIncr )
+		{
+			lfo_amd = OPN_LFO_wave[(LFOCnt+=LFOIncr)>>LFO_SHIFT];
+			lfo_pmd = lfo_amd-(LFO_RATE/2);
+		}
+#endif
+		/* clear output acc. */
+		out_ch[OUTD_LEFT] = out_ch[OUTD_RIGHT]= out_ch[OUTD_CENTER] = 0;
+		/* calcrate channel output */
+		for(ch = cch[0] ; ch <= ech ; ch++)
+			FM_CALC_CH( ch );
+		if( dacen )  *cch[5]->connect4 += dacout;
+		/* buffering */
+		FM_BUFFERING_STEREO;
+		/* timer A controll */
+		INTERNAL_TIMER_A( State , cch[2] )
+	}
+	INTERNAL_TIMER_B(State,length)
+#if FM_LFO_SUPPORT
+	OPN->LFOCnt = LFOCnt;
+#endif
+}
+
+/* -------------------------- YM2612 ---------------------------------- */
+int YM2612Init(int num, int clock, int rate,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler)
+{
+	int i;
+
+    if (FM2612) return (-1);	/* duplicate init. */
+    cur_chip = NULL;	/* hiro-shi!! */
+
+	YM2612NumChips = num;
+
+	/* allocate extend state space */
+	if( (FM2612 = (YM2612 *)emu_Malloc(sizeof(YM2612) * YM2612NumChips))==NULL)
+		return (-1);
+	/* clear */
+	memset(FM2612,0,sizeof(YM2612) * YM2612NumChips);
+	/* allocate total level table (128kb space) */
+	if( !OPNInitTable() )
+	{
+		emu_Free( FM2612 );
+		return (-1);
+	}
+
+	for ( i = 0 ; i < YM2612NumChips; i++ ) {
+		FM2612[i].OPN.ST.index = i;
+		FM2612[i].OPN.type = TYPE_YM2612;
+		FM2612[i].OPN.P_CH = FM2612[i].CH;
+		FM2612[i].OPN.ST.clock = clock;
+		FM2612[i].OPN.ST.rate = rate;
+		/* FM2612[i].OPN.ST.irq = 0; */
+		/* FM2612[i].OPN.ST.status = 0; */
+		FM2612[i].OPN.ST.timermodel = FM_TIMER_INTERVAL;
+		/* Extend handler */
+		FM2612[i].OPN.ST.Timer_Handler = TimerHandler;
+		FM2612[i].OPN.ST.IRQ_Handler   = IRQHandler;
+		YM2612ResetChip(i);
+	}
+	return 0;
+}
+
+/* ---------- shut down emurator ----------- */
+void YM2612Shutdown()
+{
+    if (!FM2612) return;
+
+	FMCloseTable();
+	emu_Free(FM2612);
+	FM2612 = NULL;
+}
+
+/* ---------- reset one of chip ---------- */
+void YM2612ResetChip(int num)
+{
+	int i;
+	YM2612 *F2612 = &(FM2612[num]);
+	FM_OPN *OPN   = &(FM2612[num].OPN);
+
+	OPNSetPris( OPN , 12*12, 12*12, 0);
+	/* status clear */
+	FM_IRQMASK_SET(&OPN->ST,0x03);
+	OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
+
+	reset_channel( &OPN->ST , &F2612->CH[0] , 6 );
+
+	for(i = 0xb6 ; i >= 0xb4 ; i-- )
+	{
+		OPNWriteReg(OPN,i      ,0xc0);
+		OPNWriteReg(OPN,i|0x100,0xc0);
+	}
+	for(i = 0xb2 ; i >= 0x30 ; i-- )
+	{
+		OPNWriteReg(OPN,i      ,0);
+		OPNWriteReg(OPN,i|0x100,0);
+	}
+	for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0);
+	/* DAC mode clear */
+	F2612->dacen = 0;
+}
+
+/* YM2612 write */
+/* n = number  */
+/* a = address */
+/* v = value   */
+int YM2612Write(int n, int a,UINT8 v)
+{
+	YM2612 *F2612 = &(FM2612[n]);
+	int addr;
+
+	switch( a&3){
+	case 0:	/* address port 0 */
+		F2612->OPN.ST.address = v & 0xff;
+		break;
+	case 1:	/* data port 0    */
+		addr = F2612->OPN.ST.address;
+		switch( addr & 0xf0 )
+		{
+		case 0x20:	/* 0x20-0x2f Mode */
+			switch( addr )
+			{
+			case 0x2a:	/* DAC data (YM2612) */
+				F2612->dacout = ((int)v - 0x80)<<(TL_BITS-7);
+                                F2612->dacout = ((int)(v/2)-0x80)<<(TL_BITS-7);
+				break;
+			case 0x2b:	/* DAC Sel  (YM2612) */
+				/* b7 = dac enable */
+				F2612->dacen = v & 0x80;
+				cur_chip = NULL;
+				break;
+			default:	/* OPN section */
+				/* write register */
+				 OPNWriteMode(&(F2612->OPN),addr,v);
+			}
+			break;
+		default:	/* 0x30-0xff OPN section */
+			/* write register */
+			 OPNWriteReg(&(F2612->OPN),addr,v);
+		}
+		break;
+	case 2:	/* address port 1 */
+		F2612->address1 = v & 0xff;
+		break;
+	case 3:	/* data port 1    */
+		addr = F2612->address1;
+		OPNWriteReg(&(F2612->OPN),addr|0x100,v);
+		break;
+	}
+	return F2612->OPN.ST.irq;
+}
+UINT8 YM2612Read(int n,int a)
+{
+	YM2612 *F2612 = &(FM2612[n]);
+
+	switch( a&3){
+	case 0:	/* status 0 */
+		return F2612->OPN.ST.status;
+	case 1:
+	case 2:
+	case 3:
+		return F2612->OPN.ST.status;
+	}
+	return 0;
+}
+
+int YM2612TimerOver(int n,int c)
+{
+	YM2612 *F2612 = &(FM2612[n]);
+
+	if( c )
+	{	/* Timer B */
+		TimerBOver( &(F2612->OPN.ST) );
+	}
+	else
+	{	/* Timer A */
+		/* timer update */
+		TimerAOver( &(F2612->OPN.ST) );
+		/* CSM mode key,TL controll */
+		if( F2612->OPN.ST.mode & 0x80 )
+		{	/* CSM mode total level latch and auto key on */
+			CSMKeyControll( &(F2612->CH[2]) );
+		}
+	}
+	return F2612->OPN.ST.irq;
+}
+
+#endif /* BUILD_YM2612 */
diff --git a/MCUME_pico2/picogenold/fm.h b/MCUME_pico2/picogenold/fm.h
new file mode 100644
index 0000000..8e47af0
--- /dev/null
+++ b/MCUME_pico2/picogenold/fm.h
@@ -0,0 +1,181 @@
+
+#ifndef _H_FM_FM_
+#define _H_FM_FM_
+
+#define HAS_YM2612  1
+
+#define BUILD_YM2612  (HAS_YM2612 || HAS_YM3438)
+
+#define FM_STEREO_MIX       0
+#define FM_OUTPUT_BIT       16
+#define FM_INTERNAL_TIMER   0
+
+#define FM_LFO_SUPPORT      1
+#define FM_SEG_SUPPORT      0
+
+#if BUILD_YM2612
+  /* in 2612intf.c */
+  #define YM2612UpdateReq(chip) YM2612UpdateRequest(chip);
+#endif
+
+/* compiler dependence */
+#ifndef OSD_CPU_H
+#define OSD_CPU_H
+typedef unsigned char	UINT8;   /* unsigned  8bit */
+typedef unsigned short	UINT16;  /* unsigned 16bit */
+typedef unsigned int	UINT32;  /* unsigned 32bit */
+typedef signed char		INT8;    /* signed  8bit   */
+typedef signed short	INT16;   /* signed 16bit   */
+typedef signed int		INT32;   /* signed 32bit   */
+#endif
+
+#define YM2203_NUMBUF 1
+#if FM_STEREO_MIX
+  #define YM2151_NUMBUF 1
+  #define YM2608_NUMBUF 1
+  #define YM2612_NUMBUF 1
+  #define YM2610_NUMBUF 1
+#else
+  #define YM2151_NUMBUF 2    /* FM L+R */
+  #define YM2608_NUMBUF 2    /* FM L+R+ADPCM+RYTHM */
+  #define YM2610_NUMBUF 2    /* FM L+R+ADPCMA+ADPCMB */
+  #define YM2612_NUMBUF 2    /* FM L+R */
+#endif
+
+#if (FM_OUTPUT_BIT==16)
+typedef INT16 FMSAMPLE;
+typedef unsigned long FMSAMPLE_MIX;
+#endif
+#if (FM_OUTPUT_BIT==8)
+typedef unsigned char  FMSAMPLE;
+typedef unsigned short FMSAMPLE_MIX;
+#endif
+
+typedef void (*FM_TIMERHANDLER)(int n,int c,int cnt,double stepTime);
+typedef void (*FM_IRQHANDLER)(int n,int irq);
+/* FM_TIMERHANDLER : Stop or Start timer         */
+/* int n          = chip number                  */
+/* int c          = Channel 0=TimerA,1=TimerB    */
+/* int count      = timer count (0=stop)         */
+/* doube stepTime = step time of one count (sec.)*/
+
+/* FM_IRQHHANDLER : IRQ level changing sense     */
+/* int n       = chip number                     */
+/* int irq     = IRQ level 0=OFF,1=ON            */
+
+#if BUILD_YM2203
+/* -------------------- YM2203(OPN) Interface -------------------- */
+
+/*
+** Initialize YM2203 emulator(s).
+**
+** 'num'           is the number of virtual YM2203's to allocate
+** 'baseclock'
+** 'rate'          is sampling rate
+** 'TimerHandler'  timer callback handler when timer start and clear
+** 'IRQHandler'    IRQ callback handler when changed IRQ level
+** return      0 = success
+*/
+int YM2203Init(int num, int baseclock, int rate,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler);
+
+/*
+** shutdown the YM2203 emulators .. make sure that no sound system stuff
+** is touching our audio buffers ...
+*/
+void YM2203Shutdown(void);
+
+/*
+** reset all chip registers for YM2203 number 'num'
+*/
+void YM2203ResetChip(int num);
+/*
+** update one of chip
+*/
+
+void YM2203UpdateOne(int num, INT16 *buffer, int length);
+
+/*
+** Write
+** return : InterruptLevel
+*/
+int YM2203Write(int n,int a,unsigned char v);
+/*
+** Read
+** return : InterruptLevel
+*/
+unsigned char YM2203Read(int n,int a);
+
+/*
+**	Timer OverFlow
+*/
+int YM2203TimerOver(int n, int c);
+
+#endif /* BUILD_YM2203 */
+
+#if BUILD_YM2608
+/* -------------------- YM2608(OPNA) Interface -------------------- */
+int YM2608Init(int num, int baseclock, int rate,
+               void **pcmroma,int *pcmsizea,short *rhythmrom,int *rhythmpos,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler);
+void YM2608Shutdown(void);
+void YM2608ResetChip(int num);
+void YM2608UpdateOne(int num, INT16 **buffer, int length);
+
+int YM2608Write(int n, int a,unsigned char v);
+unsigned char YM2608Read(int n,int a);
+int YM2608TimerOver(int n, int c );
+#endif /* BUILD_YM2608 */
+
+#if (BUILD_YM2610||BUILD_YM2610B)
+/* -------------------- YM2610(OPNB) Interface -------------------- */
+int YM2610Init(int num, int baseclock, int rate,
+               void **pcmroma,int *pcmasize,void **pcmromb,int *pcmbsize,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler);
+void YM2610Shutdown(void);
+void YM2610ResetChip(int num);
+void YM2610UpdateOne(int num, INT16 **buffer, int length);
+#if BUILD_YM2610B
+void YM2610BUpdateOne(int num, INT16 **buffer, int length);
+#endif
+
+int YM2610Write(int n, int a,unsigned char v);
+unsigned char YM2610Read(int n,int a);
+int YM2610TimerOver(int n, int c );
+
+#endif /* BUILD_YM2610 */
+
+#if BUILD_YM2612
+int YM2612Init(int num, int baseclock, int rate,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler);
+void YM2612Shutdown(void);
+void YM2612ResetChip(int num);
+void YM2612UpdateOne(int num, INT16 **buffer, int length);
+int YM2612Write(int n, int a,unsigned char v);
+unsigned char YM2612Read(int n,int a);
+int YM2612TimerOver(int n, int c );
+
+#endif /* BUILD_YM2612 */
+
+#if BUILD_YM2151
+/* -------------------- YM2151(OPM) Interface -------------------- */
+int OPMInit(int num, int baseclock, int rate,
+               FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler);
+void OPMShutdown(void);
+void OPMResetChip(int num);
+
+void OPMUpdateOne(int num, INT16 **buffer, int length );
+/* ---- set callback hander when port CT0/1 write ----- */
+/* CT.bit0 = CT0 , CT.bit1 = CT1 */
+/*
+typedef void (*mem_write_handler)(int offset,int data);
+*/
+void OPMSetPortHander(int n,mem_write_handler PortWrite);
+/* JB 981119  - so it will match MAME's memory write functions scheme*/
+
+int YM2151Write(int n,int a,unsigned char v);
+unsigned char YM2151Read(int n,int a);
+int YM2151TimerOver(int n,int c);
+#endif /* BUILD_YM2151 */
+
+#endif /* _H_FM_FM_ */
diff --git a/MCUME_pico2/picogenold/genesis.c b/MCUME_pico2/picogenold/genesis.c
new file mode 100644
index 0000000..f1c07dd
--- /dev/null
+++ b/MCUME_pico2/picogenold/genesis.c
@@ -0,0 +1,160 @@
+/*
+    Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Charles Mac Donald
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+
+#include "shared.h"
+
+//uint8 work_ram[0x10000];    /* 68K work RAM */
+//uint8 zram[0x2000];         /* Z80 work RAM */
+uint8 zbusreq;              /* /BUSREQ from Z80 */
+uint8 zreset;               /* /RESET to Z80 */
+uint8 zbusack;              /* /BUSACK to Z80 */
+uint8 zirq;                 /* /IRQ to Z80 */
+uint32 zbank;               /* Address of Z80 bank window */
+uint8 gen_running;
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown functions                                          */
+/*--------------------------------------------------------------------------*/
+
+void gen_init(void)
+{
+    sound_init();
+    memset(&snd, 0, sizeof(snd));
+
+    m68k_set_cpu_type(M68K_CPU_TYPE_68000);
+    m68k_pulse_reset();
+    error("PC:%08X\tSP:%08X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP));
+    gen_running = 1;
+}
+
+void gen_reset(void)
+{
+    /* Clear RAM */
+    memset(work_ram, 0, WORK_RAM_SIZE);
+    memset(zram, 0, Z_RAM_SIZE);
+
+    gen_running = 1;
+    zreset  = 0;    /* Z80 is reset */
+    zbusreq = 0;    /* Z80 has control of the Z bus */
+    zbusack = 1;    /* Z80 is busy using the Z bus */
+    zbank   = 0;    /* Assume default bank is 000000-007FFF */
+    zirq    = 0;    /* No interrupts occuring */
+
+    io_reset();
+
+    /* Reset the 68000 emulator */
+    m68k_pulse_reset();
+    error("PC:%08X\tSP:%08X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP));
+    z80_reset(0);
+    z80_set_irq_callback(z80_irq_callback);
+}
+
+void gen_shutdown(void)
+{
+    int i;
+
+    /* Print 68K and Z80 state */
+    error("\n");
+    error("\nPC:%08X\tSP:%08X\tSR:%04X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP), m68k_get_reg(NULL, M68K_REG_SR));
+    for(i=0;i<8;i++)
+    {
+        error("D%d:%08X\tA%d:%08X\n", 
+            i, m68k_get_reg(NULL, M68K_REG_D0+i),
+            i, m68k_get_reg(NULL, M68K_REG_A0+i));
+    }
+
+    error("\n");
+    error("PC:%04X\tSP:%04X\n", z80_get_reg(Z80_PC), z80_get_reg(Z80_SP));
+    error("AF:%04X\tAF:%04X\n", z80_get_reg(Z80_AF), z80_get_reg(Z80_AF2));
+    error("BC:%04X\tBC:%04X\n", z80_get_reg(Z80_BC), z80_get_reg(Z80_BC2));
+    error("DE:%04X\tDE:%04X\n", z80_get_reg(Z80_DE), z80_get_reg(Z80_DE2));
+    error("HL:%04X\tHL:%04X\n", z80_get_reg(Z80_HL), z80_get_reg(Z80_HL2));
+    error("IX:%04X\tIY:%04X\n", z80_get_reg(Z80_IX), z80_get_reg(Z80_IY));
+    error("\n");
+}
+
+/*--------------------------------------------------------------------------*/
+/* Bus controller chip functions                                            */
+/*--------------------------------------------------------------------------*/
+
+int gen_busack_r(void)
+{
+    return (zbusack & 1);
+}
+
+void gen_busreq_w(int state)
+{
+    zbusreq = (state & 1);
+    zbusack = 1 ^ (zbusreq & zreset);
+
+    if(zbusreq == 0 && zreset == 1)
+    {
+        z80_execute(32);
+    }
+}
+
+void gen_reset_w(int state)
+{
+    zreset = (state & 1);
+    zbusack = 1 ^ (zbusreq & zreset);
+
+    if(zreset == 0)
+    {
+        if(snd.enabled)
+        {
+            YM2612ResetChip(0);
+        }
+
+        z80_reset(0);
+        z80_set_irq_callback(z80_irq_callback);
+    }
+}
+
+
+void gen_bank_w(int state)
+{
+    zbank = ((zbank >> 1) | ((state & 1) << 23)) & 0xFF8000;
+}
+
+
+
+int z80_irq_callback(int param)
+{
+    zirq = 0;
+    z80_set_irq_line(0, CLEAR_LINE);
+    return 0xFF;
+}
+
+int vdp_int_ack_callback(int int_level)
+{
+    switch(int_level)
+    {
+        case 4: 
+            hint_pending = 0;
+            break;
+
+        case 6: 
+            status &= ~0x0080;
+            vint_pending = 0;
+            break;
+    }
+
+    return M68K_INT_ACK_AUTOVECTOR;
+}
+
diff --git a/MCUME_pico2/picogenold/genesis.h b/MCUME_pico2/picogenold/genesis.h
new file mode 100644
index 0000000..5eca126
--- /dev/null
+++ b/MCUME_pico2/picogenold/genesis.h
@@ -0,0 +1,28 @@
+
+#ifndef _GENESIS_H_
+#define _GENESIS_H_
+
+/* Global variables */
+//extern uint8 work_ram[0x10000];
+//extern uint8 zram[0x2000];
+extern uint8 zbusreq;
+extern uint8 zbusack;
+extern uint8 zreset;
+extern uint8 zirq;
+extern uint32 zbank;
+extern uint8 gen_running;
+
+/* Function prototypes */
+void gen_init(void);
+void gen_reset(void);
+void gen_shutdown(void);
+int gen_busack_r(void);
+void gen_busreq_w(int state);
+void gen_reset_w(int state);
+void gen_bank_w(int state);
+//void bswap(uint8 *mem, int length);
+int z80_irq_callback(int param);
+void m68k_irq_ack_callback(int int_level);
+
+#endif /* _GEN_H_ */
+
diff --git a/MCUME_pico2/picogenold/genlut.h b/MCUME_pico2/picogenold/genlut.h
new file mode 100644
index 0000000..d6f29fb
--- /dev/null
+++ b/MCUME_pico2/picogenold/genlut.h
@@ -0,0 +1,20482 @@
+const uint8 lut_base[327680] = {
+0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x00,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x00,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x00,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x00,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x00,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
+0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x00,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x00,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x00,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x00,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x00,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
+0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x01,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x01,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x01,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x01,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x01,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
+0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x01,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x01,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x01,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x01,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x01,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
+0x02,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x02,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x02,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x02,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x02,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x02,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
+0x02,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x02,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x02,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x02,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
+0x02,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
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+0x03,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
+0x03,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
+0x03,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x03,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
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+0x03,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
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+0x04,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
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+0x05,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
+0x05,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
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+0x05,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x05,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
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+0x7D,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x7D,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x7D,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x7D,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBD,0x3D,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x7E,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x7E,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x7E,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBE,0x3E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,0x7E,
+0x7E,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x7E,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x7E,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x7E,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBE,0x3E,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x7F,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x7F,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x7F,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBF,0x3F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,
+0x7F,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
+0x7F,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x7F,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
+0x7F,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBF,0x3F,
+};
diff --git a/MCUME_pico2/picogenold/hcnt.h b/MCUME_pico2/picogenold/hcnt.h
new file mode 100644
index 0000000..28effe2
--- /dev/null
+++ b/MCUME_pico2/picogenold/hcnt.h
@@ -0,0 +1,68 @@
+const uint8 cycle2hc32[488] =
+{
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x05, 
+	0x05, 0x05, 0x06, 0x06, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x0A, 0x0A, 0x0A, 
+	0x0B, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x10, 0x10, 
+	0x10, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15, 0x15, 0x16, 
+	0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 
+	0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 
+	0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 
+	0x27, 0x27, 0x27, 0x28, 0x28, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C, 
+	0x2C, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x32, 
+	0x32, 0x32, 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x36, 0x37, 0x37, 0x37, 
+	0x38, 0x38, 0x38, 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x3B, 0x3B, 0x3B, 0x3C, 0x3C, 0x3D, 0x3D, 
+	0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F, 0x40, 0x40, 0x40, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, 
+	0x43, 0x43, 0x44, 0x44, 0x44, 0x45, 0x45, 0x45, 0x46, 0x46, 0x46, 0x47, 0x47, 0x47, 0x48, 0x48, 
+	0x48, 0x49, 0x49, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 0x4B, 0x4C, 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4E, 
+	0x4E, 0x4E, 0x4F, 0x4F, 0x4F, 0x50, 0x50, 0x51, 0x51, 0x51, 0x52, 0x52, 0x52, 0x53, 0x53, 0x53, 
+	0x54, 0x54, 0x54, 0x55, 0x55, 0x55, 0x56, 0x56, 0x56, 0x57, 0x57, 0x58, 0x58, 0x58, 0x59, 0x59, 
+	0x59, 0x5A, 0x5A, 0x5A, 0x5B, 0x5B, 0x5B, 0x5C, 0x5C, 0x5C, 0x5D, 0x5D, 0x5E, 0x5E, 0x5E, 0x5F, 
+	0x5F, 0x5F, 0x60, 0x60, 0x60, 0x61, 0x61, 0x61, 0x62, 0x62, 0x62, 0x63, 0x63, 0x63, 0x64, 0x64, 
+	0x65, 0x65, 0x65, 0x66, 0x66, 0x66, 0x67, 0x67, 0x67, 0x68, 0x68, 0x68, 0x69, 0x69, 0x69, 0x6A, 
+	0x6A, 0x6A, 0x6B, 0x6B, 0x6C, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D, 0x6E, 0x6E, 0x6E, 0x6F, 0x6F, 0x6F, 
+	0x70, 0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x72, 0x73, 0x73, 0x73, 0x74, 0x74, 0x74, 0x75, 0x75, 
+	0x75, 0x76, 0x76, 0x76, 0x77, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x79, 0x7A, 0x7A, 0x7A, 0x7B, 
+	0x7B, 0x7B, 0x7C, 0x7C, 0x7C, 0x7D, 0x7D, 0x7D, 0x7E, 0x7E, 0x7E, 0x7F, 0x7F, 0x80, 0x80, 0x80, 
+	0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x83, 0x83, 0x83, 0x84, 0x84, 0x84, 0x85, 0x85, 0x85, 0x86, 
+	0x86, 0x87, 0x87, 0x87, 0x88, 0x88, 0x88, 0x89, 0x89, 0x89, 0x8A, 0x8A, 0x8A, 0x8B, 0x8B, 0x8B, 
+	0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8E, 0x8F, 0x8F, 0x8F, 0x90, 0x90, 0x90, 0x91, 0x91, 
+	0x91, 0x92, 0x92, 0x92, 0x93, 0x93, 0xE9, 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEC, 
+	0xEC, 0xEC, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF, 0xF0, 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 
+	0xF2, 0xF2, 0xF2, 0xF3, 0xF3, 0xF3, 0xF4, 0xF4, 0xF4, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6, 0xF7, 0xF7, 
+	0xF7, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9, 0xF9, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB, 0xFC, 0xFC, 0xFD, 
+	0xFD, 0xFD, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 
+};
+const uint8 cycle2hc40[488] =
+{
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 
+	0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x09, 0x0A, 0x0A, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0D, 
+	0x0D, 0x0E, 0x0E, 0x0F, 0x0F, 0x10, 0x10, 0x10, 0x11, 0x11, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, 
+	0x14, 0x15, 0x15, 0x16, 0x16, 0x16, 0x17, 0x17, 0x18, 0x18, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1B, 
+	0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1E, 0x1E, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, 
+	0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 
+	0x29, 0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, 
+	0x30, 0x30, 0x31, 0x31, 0x32, 0x32, 0x33, 0x33, 0x33, 0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x36, 
+	0x37, 0x37, 0x38, 0x38, 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3B, 0x3B, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 
+	0x3E, 0x3E, 0x3F, 0x3F, 0x40, 0x40, 0x40, 0x41, 0x41, 0x42, 0x42, 0x43, 0x43, 0x43, 0x44, 0x44, 
+	0x45, 0x45, 0x46, 0x46, 0x46, 0x47, 0x47, 0x48, 0x48, 0x49, 0x49, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 
+	0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4E, 0x4E, 0x4F, 0x4F, 0x50, 0x50, 0x50, 0x51, 0x51, 0x52, 0x52, 
+	0x53, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, 0x56, 0x56, 0x57, 0x57, 0x58, 0x58, 0x59, 0x59, 
+	0x5A, 0x5A, 0x5A, 0x5B, 0x5B, 0x5C, 0x5C, 0x5D, 0x5D, 0x5D, 0x5E, 0x5E, 0x5F, 0x5F, 0x60, 0x60, 
+	0x60, 0x61, 0x61, 0x62, 0x62, 0x63, 0x63, 0x63, 0x64, 0x64, 0x65, 0x65, 0x66, 0x66, 0x67, 0x67, 
+	0x67, 0x68, 0x68, 0x69, 0x69, 0x6A, 0x6A, 0x6A, 0x6B, 0x6B, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D, 0x6E, 
+	0x6E, 0x6F, 0x6F, 0x70, 0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x73, 0x73, 0x73, 0x74, 0x74, 0x75, 
+	0x75, 0x76, 0x76, 0x77, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7A, 0x7A, 0x7A, 0x7B, 0x7B, 0x7C, 
+	0x7C, 0x7D, 0x7D, 0x7D, 0x7E, 0x7E, 0x7F, 0x7F, 0x80, 0x80, 0x80, 0x81, 0x81, 0x82, 0x82, 0x83, 
+	0x83, 0x84, 0x84, 0x84, 0x85, 0x85, 0x86, 0x86, 0x87, 0x87, 0x87, 0x88, 0x88, 0x89, 0x89, 0x8A, 
+	0x8A, 0x8A, 0x8B, 0x8B, 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8F, 0x8F, 0x90, 0x90, 0x90, 
+	0x91, 0x91, 0x92, 0x92, 0x93, 0x93, 0x94, 0x94, 0x94, 0x95, 0x95, 0x96, 0x96, 0x97, 0x97, 0x97, 
+	0x98, 0x98, 0x99, 0x99, 0x9A, 0x9A, 0x9A, 0x9B, 0x9B, 0x9C, 0x9C, 0x9D, 0x9D, 0x9D, 0x9E, 0x9E, 
+	0x9F, 0x9F, 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2, 0xA3, 0xA3, 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, 
+	0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA8, 0xA8, 0xA9, 0xA9, 0xAA, 0xAA, 0xAA, 0xAB, 0xAB, 0xAC, 0xAC, 
+	0xAD, 0xAD, 0xAD, 0xAE, 0xAE, 0xAF, 0xAF, 0xB0, 0xB0, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB3, 0xB3, 
+	0xB4, 0xB4, 0xB4, 0xB5, 0xB5, 0xB6, 0xB6, 0xE4, 0xE4, 0xE4, 0xE5, 0xE5, 0xE6, 0xE6, 0xE7, 0xE7, 
+	0xE7, 0xE8, 0xE8, 0xE9, 0xE9, 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xED, 0xED, 0xEE, 0xEE, 
+	0xEE, 0xEF, 0xEF, 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF3, 0xF3, 0xF4, 0xF4, 0xF4, 0xF5, 
+	0xF5, 0xF6, 0xF6, 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF9, 0xF9, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB, 0xFC, 
+	0xFC, 0xFD, 0xFD, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 
+};
diff --git a/MCUME_pico2/picogenold/hvc.h b/MCUME_pico2/picogenold/hvc.h
new file mode 100644
index 0000000..f966074
--- /dev/null
+++ b/MCUME_pico2/picogenold/hvc.h
@@ -0,0 +1,191 @@
+
+#ifndef _HVC_H_
+#define _HVC_H_
+
+/* V counter values for NTSC 192-line display */
+const uint8 vc_ntsc_192[262] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+    0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA,
+                                  0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+/* V counter values for NTSC 224-line display */
+const uint8 vc_ntsc_224[262] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA,
+                                  0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+/* V counter values for NTSC 240-line display */
+const uint8 vc_ntsc_240[262] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05
+};
+
+/* V counter values for PAL 192-line display */
+const uint8 vc_pal_192[313] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2,
+                                                                0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+/* V counter values for PAL 224-line display */
+const uint8 vc_pal_224[313] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+    0x00, 0x01, 0x02,
+                                                                0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+/* V counter values for PAL 240-line display */
+const uint8 vc_pal_240[313] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A,
+                0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+};
+
+/* H counter values for a 256-pixel wide display (342 pixel max.) */
+const uint8 hc_256[171] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93,
+                                                          0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+/* H counter values for a 320-pixel wide display (442 pixels max.) */
+const uint8 hc_320[211] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+    0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6,
+                            0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+uint8 *vc_table[6] = {
+    vc_ntsc_192,
+    vc_ntsc_224,
+    vc_ntsc_240,
+    vc_pal_192,
+    vc_pal_224,
+    vc_pal_240
+};
+
+uint8 *hc_table[2] = {
+    hc_256,
+    hc_320,
+};
+
+#endif /* _HVC_H_ */
+
diff --git a/MCUME_pico2/picogenold/io.c b/MCUME_pico2/picogenold/io.c
new file mode 100644
index 0000000..f619dd9
--- /dev/null
+++ b/MCUME_pico2/picogenold/io.c
@@ -0,0 +1,186 @@
+/*
+    io.c
+    I/O controller chip emulation
+*/
+
+#include "shared.h"
+
+port_t port[3];
+uint8 io_reg[0x10];
+
+
+void io_reset(void)
+{
+    /* I/O register default settings */
+    uint8 io_def[0x10] =
+    {
+        0xA0,
+        0x7F, 0x7F, 0x7F,
+        0x00, 0x00, 0x00, 
+        0xFF, 0x00, 0x00,
+        0xFF, 0x00, 0x00,  
+        0xFB, 0x00, 0x00,  
+    };
+
+    /* Initialize I/O registers */
+    memcpy(io_reg, io_def, 0x10);
+
+    /*
+        Port A : 3B pad
+        Port B : Unused
+        Port C : Unused
+    */
+    port[0].data_w = device_3b_w;   
+    port[0].data_r = device_3b_r;
+    port[1].data_w = NULL;
+    port[1].data_r = NULL;
+    port[2].data_w = NULL;
+    port[2].data_r = NULL;
+}
+
+/*--------------------------------------------------------------------------*/
+/* I/O chip functions                                                       */
+/*--------------------------------------------------------------------------*/
+
+void gen_io_w(int offset, int value)
+{
+    switch(offset)
+    {
+        case 0x01: /* Port A Data */
+            value = ((value & 0x80) | (value & io_reg[offset+3]));
+            io_reg[offset] = value;
+            if(port[0].data_w) port[0].data_w(value);
+            return;
+
+        case 0x02: /* Port B Data */
+            value = ((value & 0x80) | (value & io_reg[offset+3]));
+            io_reg[offset] = value;
+            if(port[1].data_w) port[1].data_w(value);
+            return;
+
+        case 0x03: /* Port C Data */
+            value = ((value & 0x80) | (value & io_reg[offset+3]));
+            io_reg[offset] = value;
+            if(port[2].data_w) port[2].data_w(value);
+            return;  
+
+        case 0x04: /* Port A Ctrl */
+        case 0x05: /* Port B Ctrl */
+        case 0x06: /* Port C Ctrl */
+            io_reg[offset] = value & 0xFF;
+            break;
+
+        case 0x07: /* Port A TxData */
+        case 0x0A: /* Port B TxData */
+        case 0x0D: /* Port C TxData */
+            io_reg[offset] = value;
+            break;
+
+        case 0x09: /* Port A S-Ctrl */
+        case 0x0C: /* Port B S-Ctrl */
+        case 0x0F: /* Port C S-Ctrl */
+            io_reg[offset] = (value & 0xF8);
+            break;
+    }
+}
+
+int gen_io_r(int offset)
+{
+    uint8 temp;
+    uint8 has_scd = 0x20; /* No Sega CD unit attached */
+    uint8 gen_ver = 0x00; /* Version 0 hardware */
+
+    switch(offset)
+    {
+        case 0x00: /* Version */
+            switch(rom_version())
+            {
+                case 'J':
+                    temp = 0x00;
+                    break;
+                case 'U':
+                    temp = 0x80;
+                    break;
+                case 'E':
+                    temp = 0xC0;
+                    break;
+                case 'A':
+                    temp = 0xC0;
+                    break;
+                case 'B':
+                    temp = 0xC0;
+                    break;
+                case '4':
+                    temp = 0x80;
+                    break;
+                default:
+                    temp = 0x80;
+                    break;
+            }
+            return (temp | has_scd | gen_ver);
+            break;
+
+        case 0x01: /* Port A Data */
+            if(port[0].data_r) return ((io_reg[offset] & 0x80) | port[0].data_r());
+            return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F));
+
+        case 0x02: /* Port B Data */
+            if(port[1].data_r) return ((io_reg[offset] & 0x80) | port[1].data_r());
+            return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F));
+
+        case 0x03: /* Port C Data */
+            if(port[2].data_r) return ((io_reg[offset] & 0x80) | port[2].data_r());
+            return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F));
+    }
+
+    return (io_reg[offset]);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Input callbacks                                                          */
+/*--------------------------------------------------------------------------*/
+
+uint8 pad_2b_r(void)
+{
+    uint8 temp = 0x3F;
+    if(input.pad[0] & INPUT_UP)    temp &= ~0x01;
+    if(input.pad[0] & INPUT_DOWN)  temp &= ~0x02;
+    if(input.pad[0] & INPUT_LEFT)  temp &= ~0x04;
+    if(input.pad[0] & INPUT_RIGHT) temp &= ~0x08;
+    if(input.pad[0] & INPUT_B)     temp &= ~0x10;
+    if(input.pad[0] & INPUT_C)     temp &= ~0x20;
+    return (temp);
+}
+
+static int th = 0;
+
+uint8 device_3b_r(void)
+{
+    uint8 temp = 0x3F;
+
+    if(th)
+    {
+        temp = 0x3f;
+        if(input.pad[0] & INPUT_UP)    temp &= ~0x01;
+        if(input.pad[0] & INPUT_DOWN)  temp &= ~0x02;
+        if(input.pad[0] & INPUT_LEFT)  temp &= ~0x04;
+        if(input.pad[0] & INPUT_RIGHT) temp &= ~0x08;
+        if(input.pad[0] & INPUT_B)     temp &= ~0x10;
+        if(input.pad[0] & INPUT_C)     temp &= ~0x20;
+        return (temp | 0x40);
+    }
+    else
+    {
+        temp = 0x33;
+        if(input.pad[0] & INPUT_UP)    temp &= ~0x01;
+        if(input.pad[0] & INPUT_DOWN)  temp &= ~0x02;
+        if(input.pad[0] & INPUT_A)     temp &= ~0x10;
+        if(input.pad[0] & INPUT_START) temp &= ~0x20;
+        return (temp);
+    }
+}
+
+void device_3b_w(uint8 data)
+{
+    th = (data & 0x40);
+}
diff --git a/MCUME_pico2/picogenold/io.h b/MCUME_pico2/picogenold/io.h
new file mode 100644
index 0000000..bde7901
--- /dev/null
+++ b/MCUME_pico2/picogenold/io.h
@@ -0,0 +1,36 @@
+#ifndef _IO_H_
+#define _IO_H_
+
+/*
+
+void io_reset(void);
+void io_set_version(int export, int pal, int fdd, int n);
+
+
+*/
+
+typedef struct
+{
+    void (*data_w)(uint8 data);
+    uint8 (*data_r)(void);
+} port_t;
+
+typedef struct
+{
+    uint8 state;
+} t_input_3b;
+
+/* Global variables */
+extern port_t port[3];
+extern uint8 io_reg[0x10];
+
+/* Function prototypes */
+extern void io_reset(void);
+extern void gen_io_w(int offset, int value);
+extern int gen_io_r(int offset);
+extern uint8 pad_2b_r(void);
+extern uint8 device_3b_r(void);
+extern void device_3b_w(uint8 data);
+
+#endif /* _IO_H_ */
+
diff --git a/MCUME_pico2/picogenold/keyboard_osd.h b/MCUME_pico2/picogenold/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/picogenold/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/picogenold/m68k.h b/MCUME_pico2/picogenold/m68k.h
new file mode 100644
index 0000000..1c93c2d
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68k.h
@@ -0,0 +1,339 @@
+#ifndef M68K__HEADER
+#define M68K__HEADER
+
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.3
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * This code may be freely used for non-commercial purposes as long as this
+ * copyright notice remains unaltered in the source code and any binary files
+ * containing this code in compiled form.
+ *
+ * All other lisencing terms must be negotiated with the author
+ * (Karl Stenerud).
+ *
+ * The latest version of this code can be obtained at:
+ * http://kstenerud.cjb.net
+ */
+
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+
+/* ======================================================================== */
+
+/* There are 7 levels of interrupt to the 68K.
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ */
+#define M68K_IRQ_NONE 0
+#define M68K_IRQ_1    1
+#define M68K_IRQ_2    2
+#define M68K_IRQ_3    3
+#define M68K_IRQ_4    4
+#define M68K_IRQ_5    5
+#define M68K_IRQ_6    6
+#define M68K_IRQ_7    7
+
+
+/* Special interrupt acknowledge values.
+ * Use these as special returns from the interrupt acknowledge callback
+ * (specified later in this header).
+ */
+
+/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
+ * This happens in a real 68K if VPA or AVEC is asserted during an interrupt
+ * acknowledge cycle instead of DTACK.
+ */
+#define M68K_INT_ACK_AUTOVECTOR    0xffffffff
+
+/* Causes the spurious interrupt vector (0x18) to be taken
+ * This happens in a real 68K if BERR is asserted during the interrupt
+ * acknowledge cycle (i.e. no devices responded to the acknowledge).
+ */
+#define M68K_INT_ACK_SPURIOUS      0xfffffffe
+
+
+/* CPU types for use in m68k_set_cpu_type() */
+enum
+{
+	M68K_CPU_TYPE_INVALID,
+	M68K_CPU_TYPE_68000,
+	M68K_CPU_TYPE_68010,
+	M68K_CPU_TYPE_68EC020,
+	M68K_CPU_TYPE_68020,
+	M68K_CPU_TYPE_68030,	/* Supported by disassembler ONLY */
+	M68K_CPU_TYPE_68040		/* Supported by disassembler ONLY */
+};
+
+/* Registers used by m68k_get_reg() and m68k_set_reg() */
+typedef enum
+{
+	/* Real registers */
+	M68K_REG_D0,		/* Data registers */
+	M68K_REG_D1,
+	M68K_REG_D2,
+	M68K_REG_D3,
+	M68K_REG_D4,
+	M68K_REG_D5,
+	M68K_REG_D6,
+	M68K_REG_D7,
+	M68K_REG_A0,		/* Address registers */
+	M68K_REG_A1,
+	M68K_REG_A2,
+	M68K_REG_A3,
+	M68K_REG_A4,
+	M68K_REG_A5,
+	M68K_REG_A6,
+	M68K_REG_A7,
+	M68K_REG_PC,		/* Program Counter */
+	M68K_REG_SR,		/* Status Register */
+	M68K_REG_SP,		/* The current Stack Pointer (located in A7) */
+	M68K_REG_USP,		/* User Stack Pointer */
+	M68K_REG_ISP,		/* Interrupt Stack Pointer */
+	M68K_REG_MSP,		/* Master Stack Pointer */
+	M68K_REG_SFC,		/* Source Function Code */
+	M68K_REG_DFC,		/* Destination Function Code */
+	M68K_REG_VBR,		/* Vector Base Register */
+	M68K_REG_CACR,		/* Cache Control Register */
+	M68K_REG_CAAR,		/* Cache Address Register */
+
+	/* Assumed registers */
+	/* These are cheat registers which emulate the 1-longword prefetch
+	 * present in the 68000 and 68010.
+	 */ 
+	M68K_REG_PREF_ADDR,	/* Last prefetch address */
+	M68K_REG_PREF_DATA,	/* Last prefetch data */
+
+	/* Convenience registers */
+	M68K_REG_PPC,		/* Previous value in the program counter */
+	M68K_REG_IR,		/* Instruction register */
+	M68K_REG_CPU_TYPE	/* Type of CPU being run */
+} m68k_register_t;
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */
+/* ======================================================================== */
+
+/* You will have to implement these functions */
+
+/* read/write functions called by the CPU to access memory.
+ * while values used are 32 bits, only the appropriate number
+ * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits
+ * of value should be written to memory).
+ *
+ * NOTE: I have separated the immediate and PC-relative memory fetches
+ *       from the other memory fetches because some systems require
+ *       differentiation between PROGRAM and DATA fetches (usually
+ *       for security setups such as encryption).
+ *       This separation can either be achieved by setting
+ *       M68K_SEPARATE_READS in m68kconf.h and defining
+ *       the read functions, or by setting M68K_EMULATE_FC and
+ *       making a function code callback function.
+ *       Using the callback offers better emulation coverage
+ *       because you can also monitor whether the CPU is in SYSTEM or
+ *       USER mode, but it is also slower.
+ */
+
+/* Read from anywhere */
+unsigned int  m68k_read_memory_8(unsigned int address);
+unsigned int  m68k_read_memory_16(unsigned int address);
+unsigned int  m68k_read_memory_32(unsigned int address);
+
+/* Read data immediately following the PC */
+unsigned int  m68k_read_immediate_16(unsigned int address);
+unsigned int  m68k_read_immediate_32(unsigned int address);
+
+/* Read data relative to the PC */
+unsigned int  m68k_read_pcrelative_8(unsigned int address);
+unsigned int  m68k_read_pcrelative_16(unsigned int address);
+unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+/* Memory access for the disassembler */
+unsigned int m68k_read_disassembler_8  (unsigned int address);
+unsigned int m68k_read_disassembler_16 (unsigned int address);
+unsigned int m68k_read_disassembler_32 (unsigned int address);
+
+/* Write to anywhere */
+void m68k_write_memory_8(unsigned int address, unsigned int value);
+void m68k_write_memory_16(unsigned int address, unsigned int value);
+void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+
+
+/* ======================================================================== */
+/* ============================== CALLBACKS =============================== */
+/* ======================================================================== */
+
+/* These functions allow you to set callbacks to the host when specific events
+ * occur.  Note that you must enable the corresponding value in m68kconf.h
+ * in order for these to do anything useful.
+ * Note: I have defined default callbacks which are used if you have enabled
+ * the corresponding #define in m68kconf.h but either haven't assigned a
+ * callback or have assigned a callback of NULL.
+ */
+
+/* Set the callback for an interrupt acknowledge.
+ * You must enable M68K_EMULATE_INT_ACK in m68kconf.h.
+ * The CPU will call the callback with the interrupt level being acknowledged.
+ * The host program must return either a vector from 0x02-0xff, or one of the
+ * special interrupt acknowledge values specified earlier in this header.
+ * If this is not implemented, the CPU will always assume an autovectored
+ * interrupt, and will automatically clear the interrupt request when it
+ * services the interrupt.
+ * Default behavior: return M68K_INT_ACK_AUTOVECTOR.
+ */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level));
+
+
+/* Set the callback for a breakpoint acknowledge (68010+).
+ * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h.
+ * The CPU will call the callback with whatever was in the data field of the
+ * BKPT instruction for 68020+, or 0 for 68010.
+ * Default behavior: do nothing.
+ */
+void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data));
+
+
+/* Set the callback for the RESET instruction.
+ * You must enable M68K_EMULATE_RESET in m68kconf.h.
+ * The CPU calls this callback every time it encounters a RESET instruction.
+ * Default behavior: do nothing.
+ */
+void m68k_set_reset_instr_callback(void  (*callback)(void));
+
+
+/* Set the callback for informing of a large PC change.
+ * You must enable M68K_MONITOR_PC in m68kconf.h.
+ * The CPU calls this callback with the new PC value every time the PC changes
+ * by a large value (currently set for changes by longwords).
+ * Default behavior: do nothing.
+ */
+void m68k_set_pc_changed_callback(void  (*callback)(unsigned int new_pc));
+
+
+/* Set the callback for CPU function code changes.
+ * You must enable M68K_EMULATE_FC in m68kconf.h.
+ * The CPU calls this callback with the function code before every memory
+ * access to set the CPU's function code according to what kind of memory
+ * access it is (supervisor/user, program/data and such).
+ * Default behavior: do nothing.
+ */
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc));
+
+
+/* Set a callback for the instruction cycle of the CPU.
+ * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h.
+ * The CPU calls this callback just before fetching the opcode in the
+ * instruction cycle.
+ * Default behavior: do nothing.
+ */
+void m68k_set_instr_hook_callback(void  (*callback)(void));
+
+
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */
+/* ======================================================================== */
+
+/* Use this function to set the CPU type you want to emulate.
+ * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010,
+ * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020.
+ */
+void m68k_set_cpu_type(unsigned int cpu_type);
+
+/* Pulse the RESET pin on the CPU.
+ * You *MUST* reset the CPU at least once to initialize the emulation
+ * Note: If you didn't call m68k_set_cpu_type() before resetting
+ *       the CPU for the first time, the CPU will be set to
+ *       M68K_CPU_TYPE_68000.
+ */
+void m68k_pulse_reset(void);
+
+/* execute num_cycles worth of instructions.  returns number of cycles used */
+int m68k_execute(int num_cycles);
+
+/* These functions let you read/write/modify the number of cycles left to run
+ * while m68k_execute() is running.
+ * These are useful if the 68k accesses a memory-mapped port on another device
+ * that requires immediate processing by another CPU.
+ */
+int m68k_cycles_run(void);              /* Number of cycles run so far */
+int m68k_cycles_remaining(void);        /* Number of cycles left */
+void m68k_modify_timeslice(int cycles); /* Modify cycles left */
+void m68k_end_timeslice(void);          /* End timeslice now */
+
+/* Set the IPL0-IPL2 pins on the CPU (IRQ).
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ * Setting IRQ to 0 will clear an interrupt request.
+ */
+void m68k_set_irq(unsigned int int_level);
+
+
+/* Halt the CPU as if you pulsed the HALT pin. */
+void m68k_pulse_halt(void);
+
+
+/* Context switching to allow multiple CPUs */
+
+/* Get the size of the cpu context in bytes */
+unsigned int m68k_context_size(void);
+
+/* Get a cpu context */
+unsigned int m68k_get_context(void* dst);
+
+/* set the current cpu context */
+void m68k_set_context(void* dst);
+
+/* Save the current cpu context to disk.
+ * You must provide a function pointer of the form:
+ * void save_value(char* identifier, unsigned int value)
+ */
+void m68k_save_context(	void (*save_value)(char* identifier, unsigned int value));
+
+/* Load a cpu context from disk.
+ * You must provide a function pointer of the form:
+ * unsigned int load_value(char* identifier)
+ */
+void m68k_load_context(unsigned int (*load_value)(char* identifier));
+
+
+
+/* Peek at the internals of a CPU context.  This can either be a context
+ * retrieved using m68k_get_context() or the currently running context.
+ * If context is NULL, the currently running CPU context will be used.
+ */
+unsigned int m68k_get_reg(void* context, m68k_register_t reg);
+
+/* Poke values into the internals of the currently running CPU context */
+void m68k_set_reg(m68k_register_t reg, unsigned int value);
+
+/* Check if an instruction is valid for the specified CPU type */
+unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type);
+
+/* Disassemble 1 instruction using the epecified CPU type at pc.  Stores
+ * disassembly in str_buff and returns the size of the instruction in bytes.
+ */
+unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type);
+
+
+/* ======================================================================== */
+/* ============================= CONFIGURATION ============================ */
+/* ======================================================================== */
+
+/* Import the configuration for this build */
+#include "m68kconf.h"
+
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68K__HEADER */
diff --git a/MCUME_pico2/picogenold/m68kconf.h b/MCUME_pico2/picogenold/m68kconf.h
new file mode 100644
index 0000000..18301e0
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kconf.h
@@ -0,0 +1,183 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.3
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * This code may be freely used for non-commercial purposes as long as this
+ * copyright notice remains unaltered in the source code and any binary files
+ * containing this code in compiled form.
+ *
+ * All other lisencing terms must be negotiated with the author
+ * (Karl Stenerud).
+ *
+ * The latest version of this code can be obtained at:
+ * http://kstenerud.cjb.net
+ */
+
+
+
+#ifndef M68KCONF__HEADER
+#define M68KCONF__HEADER
+
+
+/* Configuration switches.
+ * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks.
+ * OPT_SPECIFY_HANDLER causes the core to link directly to the function
+ * or macro you specify, rather than using callback functions whose pointer
+ * must be passed in using m68k_set_xxx_callback().
+ */
+#define OPT_OFF             0
+#define OPT_ON              1
+#define OPT_SPECIFY_HANDLER 2
+
+
+/* ======================================================================== */
+/* ============================== MAME STUFF ============================== */
+/* ======================================================================== */
+
+/* If you're compiling this for MAME, only change M68K_COMPILE_FOR_MAME
+ * to OPT_ON and use m68kmame.h to configure the 68k core.
+ */
+#ifndef M68K_COMPILE_FOR_MAME
+#define M68K_COMPILE_FOR_MAME      OPT_OFF
+#endif /* M68K_COMPILE_FOR_MAME */
+
+#if M68K_COMPILE_FOR_MAME == OPT_ON
+#include "m68kmame.h"
+#else
+
+
+
+/* ======================================================================== */
+/* ============================= CONFIGURATION ============================ */
+/* ======================================================================== */
+
+/* Turn on if you want to use the following M68K variants */
+#define M68K_EMULATE_010            OPT_ON
+#define M68K_EMULATE_EC020          OPT_ON
+#define M68K_EMULATE_020            OPT_ON
+
+
+/* If on, the CPU will call m68k_read_immediate_xx() for immediate addressing
+ * and m68k_read_pcrelative_xx() for PC-relative addressing.
+ * If off, all read requests from the CPU will be redirected to m68k_read_xx()
+ */
+#define M68K_SEPARATE_READS         OPT_OFF
+
+
+/* If on, CPU will call the interrupt acknowledge callback when it services an
+ * interrupt.
+ * If off, all interrupts will be autovectored and all interrupt requests will
+ * auto-clear when the interrupt is serviced.
+ */
+#define M68K_EMULATE_INT_ACK        OPT_SPECIFY_HANDLER
+#define M68K_INT_ACK_CALLBACK(A)    vdp_int_ack_callback(A)
+
+
+/* If on, CPU will call the breakpoint acknowledge callback when it encounters
+ * a breakpoint instruction and it is running a 68010+.
+ */
+#define M68K_EMULATE_BKPT_ACK       OPT_OFF
+#define M68K_BKPT_ACK_CALLBACK()    your_bkpt_ack_handler_function()
+
+
+/* If on, the CPU will monitor the trace flags and take trace exceptions
+ */
+#define M68K_EMULATE_TRACE          OPT_OFF
+
+
+/* If on, CPU will call the output reset callback when it encounters a reset
+ * instruction.
+ */
+#define M68K_EMULATE_RESET          OPT_OFF
+#define M68K_RESET_CALLBACK()       your_reset_handler_function()
+
+
+/* If on, CPU will call the set fc callback on every memory access to
+ * differentiate between user/supervisor, program/data access like a real
+ * 68000 would.  This should be enabled and the callback should be set if you
+ * want to properly emulate the m68010 or higher. (moves uses function codes
+ * to read/write data from different address spaces)
+ */
+#define M68K_EMULATE_FC             OPT_OFF
+#define M68K_SET_FC_CALLBACK(A)     your_set_fc_handler_function(A)
+
+
+/* If on, CPU will call the pc changed callback when it changes the PC by a
+ * large value.  This allows host programs to be nicer when it comes to
+ * fetching immediate data and instructions on a banked memory system.
+ */
+#define M68K_MONITOR_PC             OPT_OFF
+#define M68K_SET_PC_CALLBACK(A)     your_pc_changed_handler_function(A)
+
+
+/* If on, CPU will call the instruction hook callback before every
+ * instruction.
+ */
+#define M68K_INSTRUCTION_HOOK       OPT_OFF
+#define M68K_INSTRUCTION_CALLBACK() your_instruction_hook_function()
+
+
+/* If on, the CPU will emulate the 4-byte prefetch queue of a real 68000 */
+#define M68K_EMULATE_PREFETCH       OPT_OFF
+
+
+/* If on, the CPU will generate address error exceptions if it tries to
+ * access a word or longword at an odd address.
+ * NOTE: Do not enable this!  It is not working!
+ */
+#define M68K_EMULATE_ADDRESS_ERROR  OPT_OFF
+
+
+/* Turn on to enable logging of illegal instruction calls.
+ * M68K_LOG_FILEHANDLE must be #defined to a stdio file stream.
+ * Turn on M68K_LOG_1010_1111 to log all 1010 and 1111 calls.
+ */
+#define M68K_LOG_ENABLE             OPT_OFF
+#define M68K_LOG_1010_1111          OPT_OFF
+#define M68K_LOG_FILEHANDLE         some_file_handle
+
+
+/* ----------------------------- COMPATIBILITY ---------------------------- */
+
+/* The following options set optimizations that violate the current ANSI
+ * standard, but will be compliant under the forthcoming C9X standard.
+ */
+
+
+/* If on, the enulation core will use 64-bit integers to speed up some
+ * operations.
+*/
+#define M68K_USE_64_BIT  OPT_OFF
+
+
+/* Set to your compiler's static inline keyword to enable it, or
+ * set it to blank to disable it.
+ * If you define INLINE in the makefile, it will override this value.
+ * NOTE: not enabling inline functions will SEVERELY slow down emulation.
+ */
+#ifndef INLINE
+#define INLINE static __inline__
+#endif /* INLINE */
+
+
+/* If your environment requires special prefixes for system callback functions
+ * such as the argument to qsort(), then set them here or in the makefile.
+ */
+#ifndef DECL_SPEC
+#define DECL_SPEC
+#endif
+
+#endif /* M68K_COMPILE_FOR_MAME */
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCONF__HEADER */
diff --git a/MCUME_pico2/picogenold/m68kcpu.c b/MCUME_pico2/picogenold/m68kcpu.c
new file mode 100644
index 0000000..3f61731
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kcpu.c
@@ -0,0 +1,894 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+
+#if 0
+static const char* copyright_notice =
+"MUSASHI\n"
+"Version 3.3 (2001-01-29)\n"
+"A portable Motorola M680x0 processor emulation engine.\n"
+"Copyright 1998-2001 Karl Stenerud.  All rights reserved.\n"
+"\n"
+"This code may be freely used for non-commercial purpooses as long as this\n"
+"copyright notice remains unaltered in the source code and any binary files\n"
+"containing this code in compiled form.\n"
+"\n"
+"All other lisencing terms must be negotiated with the author\n"
+"(Karl Stenerud).\n"
+"\n"
+"The latest version of this code can be obtained at:\n"
+"http://kstenerud.cjb.net\n"
+;
+#endif
+
+
+/* ======================================================================== */
+/* ================================= NOTES ================================ */
+/* ======================================================================== */
+
+
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include "m68kops.h"
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+int  m68ki_initial_cycles;
+int  m68ki_remaining_cycles = 0;                     /* Number of clocks remaining */
+uint m68ki_tracing = 0;
+uint m68ki_address_space;
+
+#ifdef M68K_LOG_ENABLE
+char* m68ki_cpu_names[9] =
+{
+	"Invalid CPU",
+	"M68000",
+	"M68010",
+	"Invalid CPU",
+	"M68EC020"
+	"Invalid CPU",
+	"Invalid CPU",
+	"Invalid CPU",
+	"M68020"
+};
+#endif /* M68K_LOG_ENABLE */
+
+/* The CPU core */
+m68ki_cpu_core m68ki_cpu = {0};
+
+#if M68K_EMULATE_ADDRESS_ERROR
+jmp_buf m68ki_address_error_trap;
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+/* Used by shift & rotate instructions */
+const uint8 m68ki_shift_8_table[65] =
+{
+	0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff
+};
+const uint16 m68ki_shift_16_table[65] =
+{
+	0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00,
+	0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff
+};
+const uint m68ki_shift_32_table[65] =
+{
+	0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000,
+	0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000,
+	0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000,
+	0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00,
+	0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8,
+	0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+
+/* Number of clock cycles to use for exception processing.
+ * I used 4 for any vectors that are undocumented for processing times.
+ */
+const uint8 m68ki_exception_cycle_table[3][256] =
+{
+	{ /* 000 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		 50, /*  2: Bus Error                             (unemulated) */
+		 50, /*  3: Address Error                         (unemulated) */
+		 34, /*  4: Illegal Instruction                                */
+		 38, /*  5: Divide by Zero -- ASG: changed from 42             */
+		 40, /*  6: CHK -- ASG: chanaged from 44                       */
+		 34, /*  7: TRAPV                                              */
+		 34, /*  8: Privilege Violation                                */
+		 34, /*  9: Trace                                              */
+		  4, /* 10: 1010                                               */
+		  4, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 44, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 44, /* 24: Spurious Interrupt                                 */
+		 44, /* 25: Level 1 Interrupt Autovector                       */
+		 44, /* 26: Level 2 Interrupt Autovector                       */
+		 44, /* 27: Level 3 Interrupt Autovector                       */
+		 44, /* 28: Level 4 Interrupt Autovector                       */
+		 44, /* 29: Level 5 Interrupt Autovector                       */
+		 44, /* 30: Level 6 Interrupt Autovector                       */
+		 44, /* 31: Level 7 Interrupt Autovector                       */
+		 34, /* 32: TRAP #0 -- ASG: chanaged from 38                   */
+		 34, /* 33: TRAP #1                                            */
+		 34, /* 34: TRAP #2                                            */
+		 34, /* 35: TRAP #3                                            */
+		 34, /* 36: TRAP #4                                            */
+		 34, /* 37: TRAP #5                                            */
+		 34, /* 38: TRAP #6                                            */
+		 34, /* 39: TRAP #7                                            */
+		 34, /* 40: TRAP #8                                            */
+		 34, /* 41: TRAP #9                                            */
+		 34, /* 42: TRAP #10                                           */
+		 34, /* 43: TRAP #11                                           */
+		 34, /* 44: TRAP #12                                           */
+		 34, /* 45: TRAP #13                                           */
+		 34, /* 46: TRAP #14                                           */
+		 34, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	},
+	{ /* 010 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		126, /*  2: Bus Error                             (unemulated) */
+		126, /*  3: Address Error                         (unemulated) */
+		 38, /*  4: Illegal Instruction                                */
+		 44, /*  5: Divide by Zero                                     */
+		 44, /*  6: CHK                                                */
+		 34, /*  7: TRAPV                                              */
+		 38, /*  8: Privilege Violation                                */
+		 38, /*  9: Trace                                              */
+		  4, /* 10: 1010                                               */
+		  4, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 44, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 46, /* 24: Spurious Interrupt                                 */
+		 46, /* 25: Level 1 Interrupt Autovector                       */
+		 46, /* 26: Level 2 Interrupt Autovector                       */
+		 46, /* 27: Level 3 Interrupt Autovector                       */
+		 46, /* 28: Level 4 Interrupt Autovector                       */
+		 46, /* 29: Level 5 Interrupt Autovector                       */
+		 46, /* 30: Level 6 Interrupt Autovector                       */
+		 46, /* 31: Level 7 Interrupt Autovector                       */
+		 38, /* 32: TRAP #0                                            */
+		 38, /* 33: TRAP #1                                            */
+		 38, /* 34: TRAP #2                                            */
+		 38, /* 35: TRAP #3                                            */
+		 38, /* 36: TRAP #4                                            */
+		 38, /* 37: TRAP #5                                            */
+		 38, /* 38: TRAP #6                                            */
+		 38, /* 39: TRAP #7                                            */
+		 38, /* 40: TRAP #8                                            */
+		 38, /* 41: TRAP #9                                            */
+		 38, /* 42: TRAP #10                                           */
+		 38, /* 43: TRAP #11                                           */
+		 38, /* 44: TRAP #12                                           */
+		 38, /* 45: TRAP #13                                           */
+		 38, /* 46: TRAP #14                                           */
+		 38, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	},
+	{ /* 020 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		 50, /*  2: Bus Error                             (unemulated) */
+		 50, /*  3: Address Error                         (unemulated) */
+		 20, /*  4: Illegal Instruction                                */
+		 38, /*  5: Divide by Zero                                     */
+		 40, /*  6: CHK                                                */
+		 20, /*  7: TRAPV                                              */
+		 34, /*  8: Privilege Violation                                */
+		 25, /*  9: Trace                                              */
+		 20, /* 10: 1010                                               */
+		 20, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 30, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 30, /* 24: Spurious Interrupt                                 */
+		 30, /* 25: Level 1 Interrupt Autovector                       */
+		 30, /* 26: Level 2 Interrupt Autovector                       */
+		 30, /* 27: Level 3 Interrupt Autovector                       */
+		 30, /* 28: Level 4 Interrupt Autovector                       */
+		 30, /* 29: Level 5 Interrupt Autovector                       */
+		 30, /* 30: Level 6 Interrupt Autovector                       */
+		 30, /* 31: Level 7 Interrupt Autovector                       */
+		 20, /* 32: TRAP #0                                            */
+		 20, /* 33: TRAP #1                                            */
+		 20, /* 34: TRAP #2                                            */
+		 20, /* 35: TRAP #3                                            */
+		 20, /* 36: TRAP #4                                            */
+		 20, /* 37: TRAP #5                                            */
+		 20, /* 38: TRAP #6                                            */
+		 20, /* 39: TRAP #7                                            */
+		 20, /* 40: TRAP #8                                            */
+		 20, /* 41: TRAP #9                                            */
+		 20, /* 42: TRAP #10                                           */
+		 20, /* 43: TRAP #11                                           */
+		 20, /* 44: TRAP #12                                           */
+		 20, /* 45: TRAP #13                                           */
+		 20, /* 46: TRAP #14                                           */
+		 20, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	}
+};
+
+const uint8 m68ki_ea_idx_cycle_table[64] =
+{
+	 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+	 0, /* ..01.000 no memory indirect, base NULL             */
+	 5, /* ..01..01 memory indirect,    base NULL, outer NULL */
+	 7, /* ..01..10 memory indirect,    base NULL, outer 16   */
+	 7, /* ..01..11 memory indirect,    base NULL, outer 32   */
+	 0,  5,  7,  7,  0,  5,  7,  7,  0,  5,  7,  7,
+	 2, /* ..10.000 no memory indirect, base 16               */
+	 7, /* ..10..01 memory indirect,    base 16,   outer NULL */
+	 9, /* ..10..10 memory indirect,    base 16,   outer 16   */
+	 9, /* ..10..11 memory indirect,    base 16,   outer 32   */
+	 0,  7,  9,  9,  0,  7,  9,  9,  0,  7,  9,  9,
+	 6, /* ..11.000 no memory indirect, base 32               */
+	11, /* ..11..01 memory indirect,    base 32,   outer NULL */
+	13, /* ..11..10 memory indirect,    base 32,   outer 16   */
+	13, /* ..11..11 memory indirect,    base 32,   outer 32   */
+	 0, 11, 13, 13,  0, 11, 13, 13,  0, 11, 13, 13
+};
+
+
+
+/* ======================================================================== */
+/* =============================== CALLBACKS ============================== */
+/* ======================================================================== */
+
+/* Default callbacks used if the callback hasn't been set yet, or if the
+ * callback is set to NULL
+ */
+
+/* Interrupt acknowledge */
+static int default_int_ack_callback_data;
+static int default_int_ack_callback(int int_level)
+{
+	default_int_ack_callback_data = int_level;
+	CPU_INT_LEVEL = 0;
+	return M68K_INT_ACK_AUTOVECTOR;
+}
+
+/* Breakpoint acknowledge */
+static unsigned int default_bkpt_ack_callback_data;
+static void default_bkpt_ack_callback(unsigned int data)
+{
+	default_bkpt_ack_callback_data = data;
+}
+
+/* Called when a reset instruction is executed */
+static void default_reset_instr_callback(void)
+{
+}
+
+/* Called when the program counter changed by a large value */
+static unsigned int default_pc_changed_callback_data;
+static void default_pc_changed_callback(unsigned int new_pc)
+{
+	default_pc_changed_callback_data = new_pc;
+}
+
+/* Called every time there's bus activity (read/write to/from memory */
+static unsigned int default_set_fc_callback_data;
+static void default_set_fc_callback(unsigned int new_fc)
+{
+	default_set_fc_callback_data = new_fc;
+}
+
+/* Called every instruction cycle prior to execution */
+static void default_instr_hook_callback(void)
+{
+}
+
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+/* Access the internals of the CPU */
+unsigned int m68k_get_reg(void* context, m68k_register_t regnum)
+{
+	m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu;
+
+	switch(regnum)
+	{
+		case M68K_REG_D0:	return cpu->dar[0];
+		case M68K_REG_D1:	return cpu->dar[1];
+		case M68K_REG_D2:	return cpu->dar[2];
+		case M68K_REG_D3:	return cpu->dar[3];
+		case M68K_REG_D4:	return cpu->dar[4];
+		case M68K_REG_D5:	return cpu->dar[5];
+		case M68K_REG_D6:	return cpu->dar[6];
+		case M68K_REG_D7:	return cpu->dar[7];
+		case M68K_REG_A0:	return cpu->dar[8];
+		case M68K_REG_A1:	return cpu->dar[9];
+		case M68K_REG_A2:	return cpu->dar[10];
+		case M68K_REG_A3:	return cpu->dar[11];
+		case M68K_REG_A4:	return cpu->dar[12];
+		case M68K_REG_A5:	return cpu->dar[13];
+		case M68K_REG_A6:	return cpu->dar[14];
+		case M68K_REG_A7:	return cpu->dar[15];
+		case M68K_REG_PC:	return MASK_OUT_ABOVE_32(cpu->pc);
+		case M68K_REG_SR:	return	cpu->t1_flag						|
+									cpu->t0_flag						|
+									(cpu->s_flag << 11)					|
+									(cpu->m_flag << 11)					|
+									cpu->int_mask						|
+									((cpu->x_flag & XFLAG_SET) >> 4)	|
+									((cpu->n_flag & NFLAG_SET) >> 4)	|
+									((!cpu->not_z_flag) << 2)			|
+									((cpu->v_flag & VFLAG_SET) >> 6)	|
+									((cpu->c_flag & CFLAG_SET) >> 8);
+		case M68K_REG_SP:	return cpu->dar[15];
+		case M68K_REG_USP:	return cpu->s_flag ? cpu->sp[0] : cpu->dar[15];
+		case M68K_REG_ISP:	return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4];
+		case M68K_REG_MSP:	return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6];
+		case M68K_REG_SFC:	return cpu->sfc;
+		case M68K_REG_DFC:	return cpu->dfc;
+		case M68K_REG_VBR:	return cpu->vbr;
+		case M68K_REG_CACR:	return cpu->cacr;
+		case M68K_REG_CAAR:	return cpu->caar;
+		case M68K_REG_PREF_ADDR:	return cpu->pref_addr;
+		case M68K_REG_PREF_DATA:	return cpu->pref_data;
+		case M68K_REG_PPC:	return MASK_OUT_ABOVE_32(cpu->ppc);
+		case M68K_REG_IR:	return cpu->ir;
+		case M68K_REG_CPU_TYPE:
+			switch(cpu->cpu_type)
+			{
+				case CPU_TYPE_000:		return (unsigned int)M68K_CPU_TYPE_68000;
+				case CPU_TYPE_010:		return (unsigned int)M68K_CPU_TYPE_68010;
+				case CPU_TYPE_EC020:	return (unsigned int)M68K_CPU_TYPE_68EC020;
+				case CPU_TYPE_020:		return (unsigned int)M68K_CPU_TYPE_68020;
+			}
+			return M68K_CPU_TYPE_INVALID;
+		default:			return 0;
+	}
+	return 0;
+}
+
+void m68k_set_reg(m68k_register_t regnum, unsigned int value)
+{
+	switch(regnum)
+	{
+		case M68K_REG_D0:	REG_D[0] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D1:	REG_D[1] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D2:	REG_D[2] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D3:	REG_D[3] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D4:	REG_D[4] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D5:	REG_D[5] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D6:	REG_D[6] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D7:	REG_D[7] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A0:	REG_A[0] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A1:	REG_A[1] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A2:	REG_A[2] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A3:	REG_A[3] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A4:	REG_A[4] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A5:	REG_A[5] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A6:	REG_A[6] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A7:	REG_A[7] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_PC:	m68ki_jump(MASK_OUT_ABOVE_32(value)); return;
+		case M68K_REG_SR:	m68ki_set_sr(value); return;
+		case M68K_REG_SP:	REG_SP = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_USP:	if(FLAG_S)
+								REG_USP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_ISP:	if(FLAG_S && !FLAG_M)
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_ISP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_MSP:	if(FLAG_S && FLAG_M)
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_MSP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_VBR:	REG_VBR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_SFC:	REG_SFC = value & 7; return;
+		case M68K_REG_DFC:	REG_DFC = value & 7; return;
+		case M68K_REG_CACR:	REG_CACR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_CAAR:	REG_CAAR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_PPC:	REG_PPC = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_IR:	REG_IR = MASK_OUT_ABOVE_16(value); return;
+		case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return;
+		default:			return;
+	}
+}
+
+/* Set the callbacks */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level))
+{
+	CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback;
+}
+
+void m68k_set_bkpt_ack_callback(void  (*callback)(unsigned int data))
+{
+	CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback;
+}
+
+void m68k_set_reset_instr_callback(void  (*callback)(void))
+{
+	CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback;
+}
+
+void m68k_set_pc_changed_callback(void  (*callback)(unsigned int new_pc))
+{
+	CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback;
+}
+
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc))
+{
+	CALLBACK_SET_FC = callback ? callback : default_set_fc_callback;
+}
+
+void m68k_set_instr_hook_callback(void  (*callback)(void))
+{
+	CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback;
+}
+
+#include <stdio.h>
+/* Set the CPU type. */
+void m68k_set_cpu_type(unsigned int cpu_type)
+{
+	switch(cpu_type)
+	{
+		case M68K_CPU_TYPE_68000:
+			CPU_TYPE         = CPU_TYPE_000;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[0];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[0];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 2;
+			CYC_DBCC_F_NOEXP = -2;
+			CYC_DBCC_F_EXP   = 2;
+			CYC_SCC_R_FALSE  = 2;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 3;
+			CYC_SHIFT        = 1;
+			CYC_RESET        = 132;
+			return;
+		case M68K_CPU_TYPE_68010:
+			CPU_TYPE         = CPU_TYPE_010;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[1];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[1];
+			CYC_BCC_NOTAKE_B = -4;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 6;
+			CYC_SCC_R_FALSE  = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 3;
+			CYC_SHIFT        = 1;
+			CYC_RESET        = 130;
+			return;
+		case M68K_CPU_TYPE_68EC020:
+			CPU_TYPE         = CPU_TYPE_EC020;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[2];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[2];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 4;
+			CYC_SCC_R_FALSE  = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 2; 
+			CYC_SHIFT        = 0;
+			CYC_RESET        = 518;
+			return;
+		case M68K_CPU_TYPE_68020:
+			CPU_TYPE         = CPU_TYPE_020;
+			CPU_ADDRESS_MASK = 0xffffffff;
+			CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[2];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[2];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 4;
+			CYC_SCC_R_FALSE  = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 2;
+			CYC_SHIFT        = 0;
+			CYC_RESET        = 518;
+			return;
+	}
+}
+
+/* Execute some instructions until we use up num_cycles clock cycles */
+/* ASG: removed per-instruction interrupt checks */
+int m68k_execute(int num_cycles)
+{
+	/* Make sure we're not stopped */
+	if(!CPU_STOPPED)
+	{
+		/* Set our pool of clock cycles available */
+		SET_CYCLES(num_cycles);
+		m68ki_initial_cycles = num_cycles;
+
+		/* ASG: update cycles */
+		USE_CYCLES(CPU_INT_CYCLES);
+		CPU_INT_CYCLES = 0;
+
+		/* Return point if we had an address error */
+		m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */
+
+		/* Main loop.  Keep going until we run out of clock cycles */
+		do
+		{
+			/* Set tracing accodring to T1. (T0 is done inside instruction) */
+			m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
+
+			/* Set the address space for reads */
+			m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */
+
+			/* Call external hook to peek at CPU */
+			m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */
+
+			/* Record previous program counter */
+			REG_PPC = REG_PC;
+
+			/* Read an instruction and call its handler */
+			REG_IR = m68ki_read_imm_16();
+			m68ki_instruction_jump_table[REG_IR]();
+			USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+
+			/* Trace m68k_exception, if necessary */
+			m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */
+		} while(GET_CYCLES() > 0);
+
+		/* set previous PC to current PC for the next entry into the loop */
+		REG_PPC = REG_PC;
+
+		/* ASG: update cycles */
+		USE_CYCLES(CPU_INT_CYCLES);
+		CPU_INT_CYCLES = 0;
+
+		/* return how many clocks we used */
+		return m68ki_initial_cycles - GET_CYCLES();
+	}
+
+	/* We get here if the CPU is stopped or halted */
+	SET_CYCLES(0);
+	CPU_INT_CYCLES = 0;
+
+	return num_cycles;
+}
+
+
+int m68k_cycles_run(void)
+{
+	return m68ki_initial_cycles - GET_CYCLES();
+}
+
+int m68k_cycles_remaining(void)
+{
+	return GET_CYCLES();
+}
+
+/* Change the timeslice */
+void m68k_modify_timeslice(int cycles)
+{
+	m68ki_initial_cycles += cycles;
+	ADD_CYCLES(cycles);
+}
+
+
+void m68k_end_timeslice(void)
+{
+	m68ki_initial_cycles = GET_CYCLES();
+	SET_CYCLES(0);
+}
+
+
+/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
+/* KS: Modified so that IPL* bits match with mask positions in the SR
+ *     and cleaned out remenants of the interrupt controller.
+ */
+void m68k_set_irq(unsigned int int_level)
+{
+	uint old_level = CPU_INT_LEVEL;
+	CPU_INT_LEVEL = int_level << 8;
+
+	/* A transition from < 7 to 7 always interrupts (NMI) */
+	/* Note: Level 7 can also level trigger like a normal IRQ */
+	if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700)
+		m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */
+	else
+		m68ki_check_interrupts(); /* Level triggered (IRQ) */
+}
+
+
+/* Pulse the RESET line on the CPU */
+void m68k_pulse_reset(void)
+{
+	static uint emulation_initialized = 0;
+
+	/* The first call to this function initializes the opcode handler jump table */
+	if(!emulation_initialized)
+	{
+		m68ki_build_opcode_table();
+		m68k_set_int_ack_callback(NULL);
+		m68k_set_bkpt_ack_callback(NULL);
+		m68k_set_reset_instr_callback(NULL);
+		m68k_set_pc_changed_callback(NULL);
+		m68k_set_fc_callback(NULL);
+		m68k_set_instr_hook_callback(NULL);
+
+		emulation_initialized = 1;
+	}
+
+
+	if(CPU_TYPE == 0)	/* KW 990319 */
+		m68k_set_cpu_type(M68K_CPU_TYPE_68000);
+
+	/* Clear all stop levels and eat up all remaining cycles */
+	CPU_STOPPED = 0;
+	SET_CYCLES(0);
+
+	/* Turn off tracing */
+	FLAG_T1 = FLAG_T0 = 0;
+	m68ki_clear_trace();
+	/* Interrupt mask to level 7 */
+	FLAG_INT_MASK = 0x0700;
+	/* Reset VBR */
+	REG_VBR = 0;
+	/* Go to supervisor mode */
+	m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR);
+
+	/* Invalidate the prefetch queue */
+#if M68K_EMULATE_PREFETCH
+	/* Set to arbitrary number since our first fetch is from 0 */
+	CPU_PREF_ADDR = 0x1000;
+#endif /* M68K_EMULATE_PREFETCH */
+
+	/* Read the initial stack pointer and program counter */
+	m68ki_jump(0);
+	REG_SP = m68ki_read_imm_32();
+	REG_PC = m68ki_read_imm_32();
+	m68ki_jump(REG_PC);
+}
+
+/* Pulse the HALT line on the CPU */
+void m68k_pulse_halt(void)
+{
+	CPU_STOPPED |= STOP_LEVEL_HALT;
+}
+
+
+/* Get and set the current CPU context */
+/* This is to allow for multiple CPUs */
+unsigned int m68k_context_size()
+{
+	return sizeof(m68ki_cpu_core);
+}
+
+unsigned int m68k_get_context(void* dst)
+{
+	if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu;
+	return sizeof(m68ki_cpu_core);
+}
+
+void m68k_set_context(void* src)
+{
+	if(src) m68ki_cpu = *(m68ki_cpu_core*)src;
+}
+
+void m68k_save_context(	void (*save_value)(char*, unsigned int))
+{
+	if(!save_value)
+		return;
+
+	save_value("CPU_TYPE"  , m68k_get_reg(NULL, M68K_REG_CPU_TYPE));
+	save_value("D0"        , REG_D[0]);
+	save_value("D1"        , REG_D[1]);
+	save_value("D2"        , REG_D[2]);
+	save_value("D3"        , REG_D[3]);
+	save_value("D4"        , REG_D[4]);
+	save_value("D5"        , REG_D[5]);
+	save_value("D6"        , REG_D[6]);
+	save_value("D7"        , REG_D[7]);
+	save_value("A0"        , REG_A[0]);
+	save_value("A1"        , REG_A[1]);
+	save_value("A2"        , REG_A[2]);
+	save_value("A3"        , REG_A[3]);
+	save_value("A4"        , REG_A[4]);
+	save_value("A5"        , REG_A[5]);
+	save_value("A6"        , REG_A[6]);
+	save_value("A7"        , REG_A[7]);
+	save_value("PPC"       , REG_PPC);
+	save_value("PC"        , REG_PC);
+	save_value("USP"       , REG_USP);
+	save_value("ISP"       , REG_ISP);
+	save_value("MSP"       , REG_MSP);
+	save_value("VBR"       , REG_VBR);
+	save_value("SFC"       , REG_SFC);
+	save_value("DFC"       , REG_DFC);
+	save_value("CACR"      , REG_CACR);
+	save_value("CAAR"      , REG_CAAR);
+	save_value("SR"        , m68ki_get_sr());
+	save_value("INT_LEVEL" , CPU_INT_LEVEL);
+	save_value("INT_CYCLES", CPU_INT_CYCLES);
+	save_value("STOPPED"   , (CPU_STOPPED & STOP_LEVEL_STOP) != 0);
+	save_value("HALTED"    , (CPU_STOPPED & STOP_LEVEL_HALT) != 0);
+	save_value("PREF_ADDR" , CPU_PREF_ADDR);
+	save_value("PREF_DATA" , CPU_PREF_DATA);
+}
+
+void m68k_load_context(unsigned int (*load_value)(char*))
+{
+	unsigned int temp;
+
+	m68k_set_cpu_type(load_value("CPU_TYPE"));
+	REG_PPC = load_value("PPC");
+	REG_PC = load_value("PC");
+	m68ki_jump(REG_PC);
+	CPU_INT_LEVEL = 0;
+	m68ki_set_sr_noint(load_value("SR"));
+	REG_D[0]       = load_value("D0");
+	REG_D[1]       = load_value("D1");
+	REG_D[2]       = load_value("D2");
+	REG_D[3]       = load_value("D3");
+	REG_D[4]       = load_value("D4");
+	REG_D[5]       = load_value("D5");
+	REG_D[6]       = load_value("D6");
+	REG_D[7]       = load_value("D7");
+	REG_A[0]       = load_value("A0");
+	REG_A[1]       = load_value("A1");
+	REG_A[2]       = load_value("A2");
+	REG_A[3]       = load_value("A3");
+	REG_A[4]       = load_value("A4");
+	REG_A[5]       = load_value("A5");
+	REG_A[6]       = load_value("A6");
+	REG_A[7]       = load_value("A7");
+	REG_USP        = load_value("USP");
+	REG_ISP        = load_value("ISP");
+	REG_MSP        = load_value("MSP");
+	REG_VBR        = load_value("VBR");
+	REG_SFC        = load_value("SFC");
+	REG_DFC        = load_value("DFC");
+	REG_CACR       = load_value("CACR");
+	REG_CAAR       = load_value("CAAR");
+	CPU_INT_LEVEL  = load_value("INT_LEVEL");
+	CPU_INT_CYCLES = load_value("INT_CYCLES");
+
+	CPU_STOPPED = 0;
+	temp           = load_value("STOPPED");
+	if(temp) CPU_STOPPED |= STOP_LEVEL_STOP;
+	temp           = load_value("HALTED");
+	if(temp) CPU_STOPPED |= STOP_LEVEL_HALT;
+
+	CPU_PREF_ADDR  = load_value("PREF_ADDR");
+	CPU_PREF_DATA  = load_value("PREF_DATA");
+}
+
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/MCUME_pico2/picogenold/m68kcpu.h b/MCUME_pico2/picogenold/m68kcpu.h
new file mode 100644
index 0000000..31fc87d
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kcpu.h
@@ -0,0 +1,1839 @@
+#include "shared.h"
+#include <stdio.h>
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.3
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * This code may be freely used for non-commercial purposes as long as this
+ * copyright notice remains unaltered in the source code and any binary files
+ * containing this code in compiled form.
+ *
+ * All other lisencing terms must be negotiated with the author
+ * (Karl Stenerud).
+ *
+ * The latest version of this code can be obtained at:
+ * http://kstenerud.cjb.net
+ */
+
+
+
+
+#ifndef M68KCPU__HEADER
+#define M68KCPU__HEADER
+
+#include "m68k.h"
+#include <limits.h>
+
+#if M68K_EMULATE_ADDRESS_ERROR
+#include <setjmp.h>
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+/* ======================================================================== */
+/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */
+/* ======================================================================== */
+
+/* Check for > 32bit sizes */
+#if UINT_MAX > 0xffffffff
+	#define M68K_INT_GT_32_BIT  1
+#endif
+
+/* Data types used in this emulation core */
+#undef sint8
+#undef sint16
+#undef sint32
+#undef sint64
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+#undef sint
+#undef uint
+
+#define sint8  signed   char			/* ASG: changed from char to signed char */
+#define sint16 signed   short
+#define sint32 signed   long
+#define uint8  unsigned char
+#define uint16 unsigned short
+#define uint32 unsigned long
+
+/* signed and unsigned int must be at least 32 bits wide */
+#define sint   signed   int
+#define uint   unsigned int
+
+
+#if M68K_USE_64_BIT
+#define sint64 signed   long long
+#define uint64 unsigned long long
+#else
+#define sint64 sint32
+#define uint64 uint32
+#endif /* M68K_USE_64_BIT */
+
+
+
+/* Allow for architectures that don't have 8-bit sizes */
+#if UCHAR_MAX == 0xff
+	#define MAKE_INT_8(A) (sint8)(A)
+#else
+	#undef  sint8
+	#define sint8  signed   int
+	#undef  uint8
+	#define uint8  unsigned int
+	INLINE sint MAKE_INT_8(uint value)
+	{
+		return (value & 0x80) ? value | ~0xff : value & 0xff;
+	}
+#endif /* UCHAR_MAX == 0xff */
+
+
+/* Allow for architectures that don't have 16-bit sizes */
+#if USHRT_MAX == 0xffff
+	#define MAKE_INT_16(A) (sint16)(A)
+#else
+	#undef  sint16
+	#define sint16 signed   int
+	#undef  uint16
+	#define uint16 unsigned int
+	INLINE sint MAKE_INT_16(uint value)
+	{
+		return (value & 0x8000) ? value | ~0xffff : value & 0xffff;
+	}
+#endif /* USHRT_MAX == 0xffff */
+
+
+/* Allow for architectures that don't have 32-bit sizes */
+#if ULONG_MAX == 0xffffffff
+	#define MAKE_INT_32(A) (sint32)(A)
+#else
+	#undef  sint32
+	#define sint32  signed   int
+	#undef  uint32
+	#define uint32  unsigned int
+	INLINE sint MAKE_INT_32(uint value)
+	{
+		return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff;
+	}
+#endif /* ULONG_MAX == 0xffffffff */
+
+
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/* ======================================================================== */
+
+/* Exception Vectors handled by emulation */
+#define EXCEPTION_BUS_ERROR                2 /* This one is not emulated! */
+#define EXCEPTION_ADDRESS_ERROR            3 /* This one is partially emulated (doesn't stack a proper frame yet) */
+#define EXCEPTION_ILLEGAL_INSTRUCTION      4
+#define EXCEPTION_ZERO_DIVIDE              5
+#define EXCEPTION_CHK                      6
+#define EXCEPTION_TRAPV                    7
+#define EXCEPTION_PRIVILEGE_VIOLATION      8
+#define EXCEPTION_TRACE                    9
+#define EXCEPTION_1010                    10
+#define EXCEPTION_1111                    11
+#define EXCEPTION_FORMAT_ERROR            14
+#define EXCEPTION_UNINITIALIZED_INTERRUPT 15
+#define EXCEPTION_SPURIOUS_INTERRUPT      24
+#define EXCEPTION_INTERRUPT_AUTOVECTOR    24
+#define EXCEPTION_TRAP_BASE               32
+
+/* Function codes set by CPU during data/address bus activity */
+#define FUNCTION_CODE_USER_DATA          1
+#define FUNCTION_CODE_USER_PROGRAM       2
+#define FUNCTION_CODE_SUPERVISOR_DATA    5
+#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6
+#define FUNCTION_CODE_CPU_SPACE          7
+
+/* CPU types for deciding what to emulate */
+#define CPU_TYPE_000   1
+#define CPU_TYPE_010   2
+#define CPU_TYPE_EC020 4
+#define CPU_TYPE_020   8
+
+/* Different ways to stop the CPU */
+#define STOP_LEVEL_STOP 1
+#define STOP_LEVEL_HALT 2
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/* ======================================================================== */
+/* ================================ MACROS ================================ */
+/* ======================================================================== */
+
+
+/* ---------------------------- General Macros ---------------------------- */
+
+/* Bit Isolation Macros */
+#define BIT_0(A)  ((A) & 0x00000001)
+#define BIT_1(A)  ((A) & 0x00000002)
+#define BIT_2(A)  ((A) & 0x00000004)
+#define BIT_3(A)  ((A) & 0x00000008)
+#define BIT_4(A)  ((A) & 0x00000010)
+#define BIT_5(A)  ((A) & 0x00000020)
+#define BIT_6(A)  ((A) & 0x00000040)
+#define BIT_7(A)  ((A) & 0x00000080)
+#define BIT_8(A)  ((A) & 0x00000100)
+#define BIT_9(A)  ((A) & 0x00000200)
+#define BIT_A(A)  ((A) & 0x00000400)
+#define BIT_B(A)  ((A) & 0x00000800)
+#define BIT_C(A)  ((A) & 0x00001000)
+#define BIT_D(A)  ((A) & 0x00002000)
+#define BIT_E(A)  ((A) & 0x00004000)
+#define BIT_F(A)  ((A) & 0x00008000)
+#define BIT_10(A) ((A) & 0x00010000)
+#define BIT_11(A) ((A) & 0x00020000)
+#define BIT_12(A) ((A) & 0x00040000)
+#define BIT_13(A) ((A) & 0x00080000)
+#define BIT_14(A) ((A) & 0x00100000)
+#define BIT_15(A) ((A) & 0x00200000)
+#define BIT_16(A) ((A) & 0x00400000)
+#define BIT_17(A) ((A) & 0x00800000)
+#define BIT_18(A) ((A) & 0x01000000)
+#define BIT_19(A) ((A) & 0x02000000)
+#define BIT_1A(A) ((A) & 0x04000000)
+#define BIT_1B(A) ((A) & 0x08000000)
+#define BIT_1C(A) ((A) & 0x10000000)
+#define BIT_1D(A) ((A) & 0x20000000)
+#define BIT_1E(A) ((A) & 0x40000000)
+#define BIT_1F(A) ((A) & 0x80000000)
+
+/* Get the most significant bit for specific sizes */
+#define GET_MSB_8(A)  ((A) & 0x80)
+#define GET_MSB_9(A)  ((A) & 0x100)
+#define GET_MSB_16(A) ((A) & 0x8000)
+#define GET_MSB_17(A) ((A) & 0x10000)
+#define GET_MSB_32(A) ((A) & 0x80000000)
+#if M68K_USE_64_BIT
+#define GET_MSB_33(A) ((A) & 0x100000000)
+#endif /* M68K_USE_64_BIT */
+
+/* Isolate nibbles */
+#define LOW_NIBBLE(A)  ((A) & 0x0f)
+#define HIGH_NIBBLE(A) ((A) & 0xf0)
+
+/* These are used to isolate 8, 16, and 32 bit sizes */
+#define MASK_OUT_ABOVE_2(A)  ((A) & 3)
+#define MASK_OUT_ABOVE_8(A)  ((A) & 0xff)
+#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff)
+#define MASK_OUT_BELOW_2(A)  ((A) & ~3)
+#define MASK_OUT_BELOW_8(A)  ((A) & ~0xff)
+#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff)
+
+/* No need to mask if we are 32 bit */
+#if M68K_INT_GT_32BIT || M68K_USE_64_BIT
+	#define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff)
+	#define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff)
+#else
+	#define MASK_OUT_ABOVE_32(A) (A)
+	#define MASK_OUT_BELOW_32(A) 0
+#endif /* M68K_INT_GT_32BIT || M68K_USE_64_BIT */
+
+/* Simulate address lines of 68k family */
+#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)
+
+
+/* Shift & Rotate Macros. */
+#define LSL(A, C) ((A) << (C))
+#define LSR(A, C) ((A) >> (C))
+
+/* Some > 32-bit optimizations */
+#if M68K_INT_GT_32BIT
+	/* Shift left and right */
+	#define LSR_32(A, C) ((A) >> (C))
+	#define LSL_32(A, C) ((A) << (C))
+#else
+	/* We have to do this because the morons at ANSI decided that shifts
+	 * by >= data size are undefined.
+	 */
+	#define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0)
+	#define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0)
+#endif /* M68K_INT_GT_32BIT */
+
+#if M68K_USE_64_BIT
+	#define LSL_32_64(A, C) ((A) << (C))
+	#define LSR_32_64(A, C) ((A) >> (C))
+	#define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C)))
+	#define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C)))
+#endif /* M68K_USE_64_BIT */
+
+#define ROL_8(A, C)      MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C)))
+#define ROL_9(A, C)                      (LSL(A, C) | LSR(A, 9-(C)))
+#define ROL_16(A, C)    MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C)))
+#define ROL_17(A, C)                     (LSL(A, C) | LSR(A, 17-(C)))
+#define ROL_32(A, C)    MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C)))
+#define ROL_33(A, C)                     (LSL_32(A, C) | LSR_32(A, 33-(C)))
+
+#define ROR_8(A, C)      MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C)))
+#define ROR_9(A, C)                      (LSR(A, C) | LSL(A, 9-(C)))
+#define ROR_16(A, C)    MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C)))
+#define ROR_17(A, C)                     (LSR(A, C) | LSL(A, 17-(C)))
+#define ROR_32(A, C)    MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C)))
+#define ROR_33(A, C)                     (LSR_32(A, C) | LSL_32(A, 33-(C)))
+
+
+
+/* ------------------------------ CPU Access ------------------------------ */
+
+/* Access the CPU registers */
+#define CPU_TYPE         m68ki_cpu.cpu_type
+
+#define REG_DA           m68ki_cpu.dar /* easy access to data and address regs */
+#define REG_D            m68ki_cpu.dar
+#define REG_A            (m68ki_cpu.dar+8)
+#define REG_PPC 		 m68ki_cpu.ppc
+#define REG_PC           m68ki_cpu.pc
+#define REG_SP_BASE      m68ki_cpu.sp
+#define REG_USP          m68ki_cpu.sp[0]
+#define REG_ISP          m68ki_cpu.sp[4]
+#define REG_MSP          m68ki_cpu.sp[6]
+#define REG_SP           m68ki_cpu.dar[15]
+#define REG_VBR          m68ki_cpu.vbr
+#define REG_SFC          m68ki_cpu.sfc
+#define REG_DFC          m68ki_cpu.dfc
+#define REG_CACR         m68ki_cpu.cacr
+#define REG_CAAR         m68ki_cpu.caar
+#define REG_IR           m68ki_cpu.ir
+
+#define FLAG_T1          m68ki_cpu.t1_flag
+#define FLAG_T0          m68ki_cpu.t0_flag
+#define FLAG_S           m68ki_cpu.s_flag
+#define FLAG_M           m68ki_cpu.m_flag
+#define FLAG_X           m68ki_cpu.x_flag
+#define FLAG_N           m68ki_cpu.n_flag
+#define FLAG_Z           m68ki_cpu.not_z_flag
+#define FLAG_V           m68ki_cpu.v_flag
+#define FLAG_C           m68ki_cpu.c_flag
+#define FLAG_INT_MASK    m68ki_cpu.int_mask
+
+#define CPU_INT_LEVEL    m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
+#define CPU_INT_CYCLES   m68ki_cpu.int_cycles /* ASG */
+#define CPU_STOPPED      m68ki_cpu.stopped
+#define CPU_PREF_ADDR    m68ki_cpu.pref_addr
+#define CPU_PREF_DATA    m68ki_cpu.pref_data
+#define CPU_ADDRESS_MASK m68ki_cpu.address_mask
+#define CPU_SR_MASK      m68ki_cpu.sr_mask
+
+#define CYC_INSTRUCTION  m68ki_cpu.cyc_instruction
+#define CYC_EXCEPTION    m68ki_cpu.cyc_exception
+#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b
+#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w
+#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp
+#define CYC_DBCC_F_EXP   m68ki_cpu.cyc_dbcc_f_exp
+#define CYC_SCC_R_FALSE  m68ki_cpu.cyc_scc_r_false
+#define CYC_MOVEM_W      m68ki_cpu.cyc_movem_w
+#define CYC_MOVEM_L      m68ki_cpu.cyc_movem_l
+#define CYC_SHIFT        m68ki_cpu.cyc_shift
+#define CYC_RESET        m68ki_cpu.cyc_reset
+
+
+#define CALLBACK_INT_ACK     m68ki_cpu.int_ack_callback
+#define CALLBACK_BKPT_ACK    m68ki_cpu.bkpt_ack_callback
+#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback
+#define CALLBACK_PC_CHANGED  m68ki_cpu.pc_changed_callback
+#define CALLBACK_SET_FC      m68ki_cpu.set_fc_callback
+#define CALLBACK_INSTR_HOOK  m68ki_cpu.instr_hook_callback
+
+
+
+/* ----------------------------- Configuration ---------------------------- */
+
+/* These defines are dependant on the configuration defines in m68kconf.h */
+
+/* Disable certain comparisons if we're not using all CPU types */
+#if M68K_EMULATE_020
+	#define CPU_TYPE_IS_020_PLUS(A)    ((A) & CPU_TYPE_020)
+	#define CPU_TYPE_IS_020_LESS(A)    1
+#else
+	#define CPU_TYPE_IS_020_PLUS(A)    0
+	#define CPU_TYPE_IS_020_LESS(A)    1
+#endif
+
+#if M68K_EMULATE_EC020
+	#define CPU_TYPE_IS_EC020_PLUS(A)  ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))
+	#define CPU_TYPE_IS_EC020_LESS(A)  ((A) & (CPU_TYPE_000 | CPU_TYPE_010 | CPU_TYPE_EC020))
+#else
+	#define CPU_TYPE_IS_EC020_PLUS(A)  CPU_TYPE_IS_020_PLUS(A)
+	#define CPU_TYPE_IS_EC020_LESS(A)  CPU_TYPE_IS_020_LESS(A)
+#endif
+
+#if M68K_EMULATE_010
+	#define CPU_TYPE_IS_010(A)         ((A) == CPU_TYPE_010)
+	#define CPU_TYPE_IS_010_PLUS(A)    ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020))
+	#define CPU_TYPE_IS_010_LESS(A)    ((A) & (CPU_TYPE_000 | CPU_TYPE_010))
+#else
+	#define CPU_TYPE_IS_010(A)         0
+	#define CPU_TYPE_IS_010_PLUS(A)    CPU_TYPE_IS_EC020_PLUS(A)
+	#define CPU_TYPE_IS_010_LESS(A)    CPU_TYPE_IS_EC020_LESS(A)
+#endif
+
+#if M68K_EMULATE_020 || M68K_EMULATE_EC020
+	#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))
+#else
+	#define CPU_TYPE_IS_020_VARIANT(A) 0
+#endif
+
+#if M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010
+	#define CPU_TYPE_IS_000(A)         ((A) == CPU_TYPE_000)
+#else
+	#define CPU_TYPE_IS_000(A)         1
+#endif
+
+
+#if !M68K_SEPARATE_READS
+#define m68k_read_immediate_16(A) m68ki_read_program_16(A)
+#define m68k_read_immediate_32(A) m68ki_read_program_32(A)
+
+#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A)
+#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A)
+#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A)
+#endif /* M68K_SEPARATE_READS */
+
+
+/* Enable or disable callback functions */
+#if M68K_EMULATE_INT_ACK
+	#if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER
+		#define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A)
+	#else
+		#define m68ki_int_ack(A) CALLBACK_INT_ACK(A)
+	#endif
+#else
+	/* Default action is to used autovector mode, which is most common */
+	#define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR
+#endif /* M68K_EMULATE_INT_ACK */
+
+#if M68K_EMULATE_BKPT_ACK
+	#if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER
+		#define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A)
+	#else
+		#define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A)
+	#endif
+#else
+	#define m68ki_bkpt_ack(A)
+#endif /* M68K_EMULATE_BKPT_ACK */
+
+#if M68K_EMULATE_RESET
+	#if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER
+		#define m68ki_output_reset() M68K_RESET_CALLBACK()
+	#else
+		#define m68ki_output_reset() CALLBACK_RESET_INSTR()
+	#endif
+#else
+	#define m68ki_output_reset()
+#endif /* M68K_EMULATE_RESET */
+
+#if M68K_INSTRUCTION_HOOK
+	#if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER
+		#define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK()
+	#else
+		#define m68ki_instr_hook() CALLBACK_INSTR_HOOK()
+	#endif
+#else
+	#define m68ki_instr_hook()
+#endif /* M68K_INSTRUCTION_HOOK */
+
+#if M68K_MONITOR_PC
+	#if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER
+		#define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A))
+	#else
+		#define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A))
+	#endif
+#else
+	#define m68ki_pc_changed(A)
+#endif /* M68K_MONITOR_PC */
+
+
+/* Enable or disable function code emulation */
+#if M68K_EMULATE_FC
+	#if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER
+		#define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A)
+	#else
+		#define m68ki_set_fc(A) CALLBACK_SET_FC(A)
+	#endif
+	#define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA
+	#define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM
+	#define m68ki_get_address_space() m68ki_address_space
+#else
+	#define m68ki_set_fc(A)
+	#define m68ki_use_data_space()
+	#define m68ki_use_program_space()
+	#define m68ki_get_address_space() FUNCTION_CODE_USER_DATA
+#endif /* M68K_EMULATE_FC */
+
+
+/* Enable or disable trace emulation */
+#if M68K_EMULATE_TRACE
+	/* Initiates trace checking before each instruction (t1) */
+	#define m68ki_trace_t1() m68ki_tracing = FLAG_T1
+	/* adds t0 to trace checking if we encounter change of flow */
+	#define m68ki_trace_t0() m68ki_tracing |= FLAG_T0
+	/* Clear all tracing */
+	#define m68ki_clear_trace() m68ki_tracing = 0
+	/* Cause a trace exception if we are tracing */
+	#define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace()
+#else
+	#define m68ki_trace_t1()
+	#define m68ki_trace_t0()
+	#define m68ki_clear_trace()
+	#define m68ki_exception_if_trace()
+#endif /* M68K_EMULATE_TRACE */
+
+
+
+/* Address error */
+#if M68K_EMULATE_ADDRESS_ERROR
+	extern jmp_buf m68ki_address_error_trap;
+	#define m68ki_set_address_error_trap() if(setjmp(m68ki_address_error_trap)) m68ki_exception_address_error();
+	#define m68ki_check_address_error(A) if((A)&1) longjmp(m68ki_address_error_jump, 1);
+#else
+	#define m68ki_set_address_error_trap()
+	#define m68ki_check_address_error(A)
+#endif /* M68K_ADDRESS_ERROR */
+
+/* Logging */
+#if M68K_LOG_ENABLE
+	#include <stdio.h>
+	extern FILE* M68K_LOG_FILEHANDLE
+	extern char* m68ki_cpu_names[];
+
+	#define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A
+	#if M68K_LOG_1010_1111
+		#define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A
+	#else
+		#define M68K_DO_LOG_EMU(A)
+	#endif
+#else
+	#define M68K_DO_LOG(A)
+	#define M68K_DO_LOG_EMU(A)
+#endif
+
+
+
+/* -------------------------- EA / Operand Access ------------------------- */
+
+/*
+ * The general instruction format follows this pattern:
+ * .... XXX. .... .YYY
+ * where XXX is register X and YYY is register Y
+ */
+/* Data Register Isolation */
+#define DX (REG_D[(REG_IR >> 9) & 7])
+#define DY (REG_D[REG_IR & 7])
+/* Address Register Isolation */
+#define AX (REG_A[(REG_IR >> 9) & 7])
+#define AY (REG_A[REG_IR & 7])
+
+
+/* Effective Address Calculations */
+#define EA_AY_AI_8()   AY                                    /* address register indirect */
+#define EA_AY_AI_16()  EA_AY_AI_8()
+#define EA_AY_AI_32()  EA_AY_AI_8()
+#define EA_AY_PI_8()   (AY++)                                /* postincrement (size = byte) */
+#define EA_AY_PI_16()  ((AY+=2)-2)                           /* postincrement (size = word) */
+#define EA_AY_PI_32()  ((AY+=4)-4)                           /* postincrement (size = long) */
+#define EA_AY_PD_8()   (--AY)                                /* predecrement (size = byte) */
+#define EA_AY_PD_16()  (AY-=2)                               /* predecrement (size = word) */
+#define EA_AY_PD_32()  (AY-=4)                               /* predecrement (size = long) */
+#define EA_AY_DI_8()   (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_16()  EA_AY_DI_8()
+#define EA_AY_DI_32()  EA_AY_DI_8()
+#define EA_AY_IX_8()   m68ki_get_ea_ix(AY)                   /* indirect + index */
+#define EA_AY_IX_16()  EA_AY_IX_8()
+#define EA_AY_IX_32()  EA_AY_IX_8()
+
+#define EA_AX_AI_8()   AX
+#define EA_AX_AI_16()  EA_AX_AI_8()
+#define EA_AX_AI_32()  EA_AX_AI_8()
+#define EA_AX_PI_8()   (AX++)
+#define EA_AX_PI_16()  ((AX+=2)-2)
+#define EA_AX_PI_32()  ((AX+=4)-4)
+#define EA_AX_PD_8()   (--AX)
+#define EA_AX_PD_16()  (AX-=2)
+#define EA_AX_PD_32()  (AX-=4)
+#define EA_AX_DI_8()   (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_16()  EA_AX_DI_8()
+#define EA_AX_DI_32()  EA_AX_DI_8()
+#define EA_AX_IX_8()   m68ki_get_ea_ix(AX)
+#define EA_AX_IX_16()  EA_AX_IX_8()
+#define EA_AX_IX_32()  EA_AX_IX_8()
+
+#define EA_A7_PI_8()   ((REG_A[7]+=2)-2)
+#define EA_A7_PD_8()   (REG_A[7]-=2)
+
+#define EA_AW_8()      MAKE_INT_16(m68ki_read_imm_16())      /* absolute word */
+#define EA_AW_16()     EA_AW_8()
+#define EA_AW_32()     EA_AW_8()
+#define EA_AL_8()      m68ki_read_imm_32()                   /* absolute long */
+#define EA_AL_16()     EA_AL_8()
+#define EA_AL_32()     EA_AL_8()
+#define EA_PCDI_8()    m68ki_get_ea_pcdi()                   /* pc indirect + displacement */
+#define EA_PCDI_16()   EA_PCDI_8()
+#define EA_PCDI_32()   EA_PCDI_8()
+#define EA_PCIX_8()    m68ki_get_ea_pcix()                   /* pc indirect + index */
+#define EA_PCIX_16()   EA_PCIX_8()
+#define EA_PCIX_32()   EA_PCIX_8()
+
+
+#define OPER_I_8()     m68ki_read_imm_8()
+#define OPER_I_16()    m68ki_read_imm_16()
+#define OPER_I_32()    m68ki_read_imm_32()
+
+
+
+/* --------------------------- Status Register ---------------------------- */
+
+/* Flag Calculation Macros */
+#define CFLAG_8(A) (A)
+#define CFLAG_16(A) ((A)>>8)
+
+#if M68K_INT_GT_32_BIT
+	#define CFLAG_ADD_32(S, D, R) ((R)>>24)
+	#define CFLAG_SUB_32(S, D, R) ((R)>>24)
+#else
+	#define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23)
+	#define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23)
+#endif /* M68K_INT_GT_32_BIT */
+
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
+#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24)
+
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
+#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24)
+
+#define NFLAG_8(A) (A)
+#define NFLAG_16(A) ((A)>>8)
+#define NFLAG_32(A) ((A)>>24)
+#define NFLAG_64(A) ((A)>>56)
+
+#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A)
+#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A)
+#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A)
+
+
+/* Flag values */
+#define NFLAG_SET   0x80
+#define NFLAG_CLEAR 0
+#define CFLAG_SET   0x100
+#define CFLAG_CLEAR 0
+#define XFLAG_SET   0x100
+#define XFLAG_CLEAR 0
+#define VFLAG_SET   0x80
+#define VFLAG_CLEAR 0
+#define ZFLAG_SET   0
+#define ZFLAG_CLEAR 0xffffffff
+
+#define SFLAG_SET   4
+#define SFLAG_CLEAR 0
+#define MFLAG_SET   2
+#define MFLAG_CLEAR 0
+
+/* Turn flag values into 1 or 0 */
+#define XFLAG_AS_1() ((FLAG_X>>8)&1)
+#define NFLAG_AS_1() ((FLAG_N>>7)&1)
+#define VFLAG_AS_1() ((FLAG_V>>7)&1)
+#define ZFLAG_AS_1() (!FLAG_Z)
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)
+
+
+/* Conditions */
+#define COND_CS() (FLAG_C&0x100)
+#define COND_CC() (!COND_CS())
+#define COND_VS() (FLAG_V&0x80)
+#define COND_VC() (!COND_VS())
+#define COND_NE() FLAG_Z
+#define COND_EQ() (!COND_NE())
+#define COND_MI() (FLAG_N&0x80)
+#define COND_PL() (!COND_MI())
+#define COND_LT() ((FLAG_N^FLAG_V)&0x80)
+#define COND_GE() (!COND_LT())
+#define COND_HI() (COND_CC() && COND_NE())
+#define COND_LS() (COND_CS() || COND_EQ())
+#define COND_GT() (COND_GE() && COND_NE())
+#define COND_LE() (COND_LT() || COND_EQ())
+
+/* Reversed conditions */
+#define COND_NOT_CS() COND_CC()
+#define COND_NOT_CC() COND_CS()
+#define COND_NOT_VS() COND_VC()
+#define COND_NOT_VC() COND_VS()
+#define COND_NOT_NE() COND_EQ()
+#define COND_NOT_EQ() COND_NE()
+#define COND_NOT_MI() COND_PL()
+#define COND_NOT_PL() COND_MI()
+#define COND_NOT_LT() COND_GE()
+#define COND_NOT_GE() COND_LT()
+#define COND_NOT_HI() COND_LS()
+#define COND_NOT_LS() COND_HI()
+#define COND_NOT_GT() COND_LE()
+#define COND_NOT_LE() COND_GT()
+
+/* Not real conditions, but here for convenience */
+#define COND_XS() (FLAG_X&0x100)
+#define COND_XC() (!COND_XS)
+
+
+/* Get the condition code register */
+#define m68ki_get_ccr() ((COND_XS() >> 4) | \
+						 (COND_MI() >> 4) | \
+						 (COND_EQ() << 2) | \
+						 (COND_VS() >> 6) | \
+						 (COND_CS() >> 8))
+
+/* Get the status register */
+#define m68ki_get_sr() ( FLAG_T1              | \
+						 FLAG_T0              | \
+						(FLAG_S        << 11) | \
+						(FLAG_M        << 11) | \
+						 FLAG_INT_MASK        | \
+						 m68ki_get_ccr())
+
+
+
+/* ---------------------------- Cycle Counting ---------------------------- */
+
+#define ADD_CYCLES(A)    m68ki_remaining_cycles += (A)
+#define USE_CYCLES(A)    m68ki_remaining_cycles -= (A)
+#define SET_CYCLES(A)    m68ki_remaining_cycles = A
+#define GET_CYCLES()     m68ki_remaining_cycles
+#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0
+
+
+
+/* ----------------------------- Read / Write ----------------------------- */
+
+/* Read from the current address space */
+#define m68ki_read_8(A)  m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space())
+
+/* Write to the current data space */
+#define m68ki_write_8(A, V)  m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+
+/* map read immediate 8 to read immediate 16 */
+#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16())
+
+/* Map PC-relative reads */
+#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)
+#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)
+#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)
+
+/* Read from the program space */
+#define m68ki_read_program_8(A) 	m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_16(A) 	m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_32(A) 	m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+
+/* Read from the data space */
+#define m68ki_read_data_8(A) 	m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_16(A) 	m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_32(A) 	m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+
+
+
+/* ======================================================================== */
+/* =============================== PROTOTYPES ============================= */
+/* ======================================================================== */
+
+typedef struct
+{
+	uint cpu_type;     /* CPU Type: 68000, 68010, 68EC020, or 68020 */
+	uint dar[16];      /* Data and Address Registers */
+	uint ppc;		   /* Previous program counter */
+	uint pc;           /* Program Counter */
+	uint sp[7];        /* User, Interrupt, and Master Stack Pointers */
+	uint vbr;          /* Vector Base Register (m68010+) */
+	uint sfc;          /* Source Function Code Register (m68010+) */
+	uint dfc;          /* Destination Function Code Register (m68010+) */
+	uint cacr;         /* Cache Control Register (m68020, unemulated) */
+	uint caar;         /* Cache Address Register (m68020, unemulated) */
+	uint ir;           /* Instruction Register */
+	uint t1_flag;      /* Trace 1 */
+	uint t0_flag;      /* Trace 0 */
+	uint s_flag;       /* Supervisor */
+	uint m_flag;       /* Master/Interrupt state */
+	uint x_flag;       /* Extend */
+	uint n_flag;       /* Negative */
+	uint not_z_flag;   /* Zero, inverted for speedups */
+	uint v_flag;       /* Overflow */
+	uint c_flag;       /* Carry */
+	uint int_mask;     /* I0-I2 */
+	uint int_level;    /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
+	uint int_cycles;   /* ASG: extra cycles from generated interrupts */
+	uint stopped;      /* Stopped state */
+	uint pref_addr;    /* Last prefetch address */
+	uint pref_data;    /* Data in the prefetch queue */
+	uint address_mask; /* Available address pins */
+	uint sr_mask;      /* Implemented status register bits */
+
+	/* Clocks required for instructions / exceptions */
+	uint cyc_bcc_notake_b;
+	uint cyc_bcc_notake_w;
+	uint cyc_dbcc_f_noexp;
+	uint cyc_dbcc_f_exp;
+	uint cyc_scc_r_false;
+	uint cyc_movem_w;
+	uint cyc_movem_l;
+	uint cyc_shift;
+	uint cyc_reset;
+	uint8* cyc_instruction;
+	uint8* cyc_exception;
+
+	/* Callbacks to host */
+	int  (*int_ack_callback)(int int_line);           /* Interrupt Acknowledge */
+	void (*bkpt_ack_callback)(unsigned int data);     /* Breakpoint Acknowledge */
+	void (*reset_instr_callback)(void);               /* Called when a RESET instruction is encountered */
+	void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */
+	void (*set_fc_callback)(unsigned int new_fc);     /* Called when the CPU function code changes */
+	void (*instr_hook_callback)(void);                /* Called every instruction cycle prior to execution */
+
+} m68ki_cpu_core;
+
+
+extern m68ki_cpu_core m68ki_cpu;
+extern sint           m68ki_remaining_cycles;
+extern uint           m68ki_tracing;
+extern const uint8    m68ki_shift_8_table[];
+extern const uint16   m68ki_shift_16_table[];
+extern const uint     m68ki_shift_32_table[];
+extern const uint8    m68ki_exception_cycle_table[][256];
+extern uint           m68ki_address_space;
+extern const uint8    m68ki_ea_idx_cycle_table[];
+
+
+/* Read data immediately after the program counter */
+INLINE uint m68ki_read_imm_16(void);
+INLINE uint m68ki_read_imm_32(void);
+
+/* Read data with specific function code */
+INLINE uint m68ki_read_8_fc  (uint address, uint fc);
+INLINE uint m68ki_read_16_fc (uint address, uint fc);
+INLINE uint m68ki_read_32_fc (uint address, uint fc);
+
+/* Write data with specific function code */
+INLINE void m68ki_write_8_fc (uint address, uint fc, uint value);
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value);
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value);
+
+/* Indexed and PC-relative ea fetching */
+INLINE uint m68ki_get_ea_pcdi(void);
+INLINE uint m68ki_get_ea_pcix(void);
+INLINE uint m68ki_get_ea_ix(uint An);
+
+/* Operand fetching */
+INLINE uint OPER_AY_AI_8(void);
+INLINE uint OPER_AY_AI_16(void);
+INLINE uint OPER_AY_AI_32(void);
+INLINE uint OPER_AY_PI_8(void);
+INLINE uint OPER_AY_PI_16(void);
+INLINE uint OPER_AY_PI_32(void);
+INLINE uint OPER_AY_PD_8(void);
+INLINE uint OPER_AY_PD_16(void);
+INLINE uint OPER_AY_PD_32(void);
+INLINE uint OPER_AY_DI_8(void);
+INLINE uint OPER_AY_DI_16(void);
+INLINE uint OPER_AY_DI_32(void);
+INLINE uint OPER_AY_IX_8(void);
+INLINE uint OPER_AY_IX_16(void);
+INLINE uint OPER_AY_IX_32(void);
+
+INLINE uint OPER_AX_AI_8(void);
+INLINE uint OPER_AX_AI_16(void);
+INLINE uint OPER_AX_AI_32(void);
+INLINE uint OPER_AX_PI_8(void);
+INLINE uint OPER_AX_PI_16(void);
+INLINE uint OPER_AX_PI_32(void);
+INLINE uint OPER_AX_PD_8(void);
+INLINE uint OPER_AX_PD_16(void);
+INLINE uint OPER_AX_PD_32(void);
+INLINE uint OPER_AX_DI_8(void);
+INLINE uint OPER_AX_DI_16(void);
+INLINE uint OPER_AX_DI_32(void);
+INLINE uint OPER_AX_IX_8(void);
+INLINE uint OPER_AX_IX_16(void);
+INLINE uint OPER_AX_IX_32(void);
+
+INLINE uint OPER_A7_PI_8(void);
+INLINE uint OPER_A7_PD_8(void);
+
+INLINE uint OPER_AW_8(void);
+INLINE uint OPER_AW_16(void);
+INLINE uint OPER_AW_32(void);
+INLINE uint OPER_AL_8(void);
+INLINE uint OPER_AL_16(void);
+INLINE uint OPER_AL_32(void);
+INLINE uint OPER_PCDI_8(void);
+INLINE uint OPER_PCDI_16(void);
+INLINE uint OPER_PCDI_32(void);
+INLINE uint OPER_PCIX_8(void);
+INLINE uint OPER_PCIX_16(void);
+INLINE uint OPER_PCIX_32(void);
+
+/* Stack operations */
+INLINE void m68ki_push_16(uint value);
+INLINE void m68ki_push_32(uint value);
+INLINE uint m68ki_pull_16(void);
+INLINE uint m68ki_pull_32(void);
+
+/* Program flow operations */
+INLINE void m68ki_jump(uint new_pc);
+INLINE void m68ki_jump_vector(uint vector);
+INLINE void m68ki_branch_8(uint offset);
+INLINE void m68ki_branch_16(uint offset);
+INLINE void m68ki_branch_32(uint offset);
+
+/* Status register operations. */
+INLINE void m68ki_set_s_flag(uint value);            /* Only bit 2 of value should be set (i.e. 4 or 0) */
+INLINE void m68ki_set_sm_flag(uint value);           /* only bits 1 and 2 of value should be set */
+INLINE void m68ki_set_ccr(uint value);               /* set the condition code register */
+INLINE void m68ki_set_sr(uint value);                /* set the status register */
+INLINE void m68ki_set_sr_noint(uint value);          /* set the status register */
+
+/* Exception processing */
+INLINE uint m68ki_init_exception(void);              /* Initial exception processing */
+
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */
+INLINE void m68ki_stack_frame_buserr(uint pc, uint sr, uint address, uint write, uint instruction, uint fc);
+
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector);
+INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc);
+INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc);
+
+INLINE void m68ki_exception_trap(uint vector);
+INLINE void m68ki_exception_trapN(uint vector);
+INLINE void m68ki_exception_trace(void);
+INLINE void m68ki_exception_privilege_violation(void);
+INLINE void m68ki_exception_1010(void);
+INLINE void m68ki_exception_1111(void);
+INLINE void m68ki_exception_illegal(void);
+INLINE void m68ki_exception_format_error(void);
+INLINE void m68ki_exception_address_error(void);
+INLINE void m68ki_exception_interrupt(uint int_level);
+INLINE void m68ki_check_interrupts(void);            /* ASG: check for interrupts */
+
+/* quick disassembly (used for logging) */
+char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
+
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+
+/* ---------------------------- Read Immediate ---------------------------- */
+
+/* Handles all immediate reads, does address error check, function code setting,
+ * and prefetching if they are enabled in m68kconf.h
+ */
+INLINE uint m68ki_read_imm_16(void)
+{
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */
+#if M68K_EMULATE_PREFETCH
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+	}
+	REG_PC += 2;
+	return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3));
+#else
+	REG_PC += 2;
+	return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2));
+#endif /* M68K_EMULATE_PREFETCH */
+}
+INLINE uint m68ki_read_imm_32(void)
+{
+#if M68K_EMULATE_PREFETCH
+	uint temp_val;
+
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+	}
+	temp_val = CPU_PREF_DATA;
+	REG_PC += 2;
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+		temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16));
+	}
+	REG_PC += 2;
+
+	return temp_val;
+#else
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */
+	REG_PC += 4;
+	return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4));
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+
+
+/* ------------------------- Top level read/write ------------------------- */
+
+/* Handles all memory accesses (except for immediate reads if they are
+ * configured to use separate functions in m68kconf.h).
+ * All memory accesses must go through these top level functions.
+ * These functions will also check for address error and set the function
+ * code if they are enabled in m68kconf.h.
+ */
+INLINE uint m68ki_read_8_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_8(ADDRESS_68K(address));
+}
+INLINE uint m68ki_read_16_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_16(ADDRESS_68K(address));
+}
+INLINE uint m68ki_read_32_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_32(ADDRESS_68K(address));
+}
+
+INLINE void m68ki_write_8_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_8(ADDRESS_68K(address), value);
+}
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_16(ADDRESS_68K(address), value);
+}
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_32(ADDRESS_68K(address), value);
+}
+
+
+
+/* --------------------- Effective Address Calculation -------------------- */
+
+/* The program counter relative addressing modes cause operands to be
+ * retrieved from program space, not data space.
+ */
+INLINE uint m68ki_get_ea_pcdi(void)
+{
+	uint old_pc = REG_PC;
+	m68ki_use_program_space(); /* auto-disable */
+	return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+}
+
+
+INLINE uint m68ki_get_ea_pcix(void)
+{
+	m68ki_use_program_space(); /* auto-disable */
+	return m68ki_get_ea_ix(REG_PC);
+}
+
+/* Indexed addressing modes are encoded as follows:
+ *
+ * Base instruction format:
+ * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+ * x x x x x x x x x x | 1 1 0 | BASE REGISTER      (An)
+ *
+ * Base instruction format for destination EA in move instructions:
+ * F E D C | B A 9    | 8 7 6 | 5 4 3 2 1 0
+ * x x x x | BASE REG | 1 1 0 | X X X X X X       (An)
+ *
+ * Brief extension format:
+ *  F  |  E D C   |  B  |  A 9  | 8 | 7 6 5 4 3 2 1 0
+ * D/A | REGISTER | W/L | SCALE | 0 |  DISPLACEMENT
+ *
+ * Full extension format:
+ *  F     E D C      B     A 9    8   7    6    5 4       3   2 1 0
+ * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS
+ * BASE DISPLACEMENT (0, 16, 32 bit)                (bd)
+ * OUTER DISPLACEMENT (0, 16, 32 bit)               (od)
+ *
+ * D/A:     0 = Dn, 1 = An                          (Xn)
+ * W/L:     0 = W (sign extend), 1 = L              (.SIZE)
+ * SCALE:   00=1, 01=2, 10=4, 11=8                  (*SCALE)
+ * BS:      0=add base reg, 1=suppress base reg     (An suppressed)
+ * IS:      0=add index, 1=suppress index           (Xn suppressed)
+ * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long  (size of bd)
+ *
+ * IS I/IS Operation
+ * 0  000  No Memory Indirect
+ * 0  001  indir prex with null outer
+ * 0  010  indir prex with word outer
+ * 0  011  indir prex with long outer
+ * 0  100  reserved
+ * 0  101  indir postx with null outer
+ * 0  110  indir postx with word outer
+ * 0  111  indir postx with long outer
+ * 1  000  no memory indirect
+ * 1  001  mem indir with null outer
+ * 1  010  mem indir with word outer
+ * 1  011  mem indir with long outer
+ * 1  100-111  reserved
+ */
+INLINE uint m68ki_get_ea_ix(uint An)
+{
+	/* An = base register */
+	uint extension = m68ki_read_imm_16();
+	uint Xn = 0;                        /* Index register */
+	uint bd = 0;                        /* Base Displacement */
+	uint od = 0;                        /* Outer Displacement */
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+	{
+		/* Calculate index */
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+
+		/* Add base register and displacement and return */
+		return An + Xn + MAKE_INT_8(extension);
+	}
+
+	/* Brief extension format */
+	if(!BIT_8(extension))
+	{
+		/* Calculate index */
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+		/* Add scale if proper CPU type */
+		if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+			Xn <<= (extension>>9) & 3;  /* SCALE */
+
+		/* Add base register and displacement and return */
+		return An + Xn + MAKE_INT_8(extension);
+	}
+
+	/* Full extension format */
+
+	USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]);
+
+	/* Check if base register is present */
+	if(BIT_7(extension))                /* BS */
+		An = 0;                         /* An */
+
+	/* Check if index is present */
+	if(!BIT_6(extension))               /* IS */
+	{
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+		Xn <<= (extension>>9) & 3;      /* SCALE */
+	}
+
+	/* Check if base displacement is present */
+	if(BIT_5(extension))                /* BD SIZE */
+		bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());
+
+	/* If no indirect action, we are done */
+	if(!(extension&7))                  /* No Memory Indirect */
+		return An + bd + Xn;
+
+	/* Check if outer displacement is present */
+	if(BIT_1(extension))                /* I/IS:  od */
+		od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());
+
+	/* Postindex */
+	if(BIT_2(extension))                /* I/IS:  0 = preindex, 1 = postindex */
+		return m68ki_read_32(An + bd) + Xn + od;
+
+	/* Preindex */
+	return m68ki_read_32(An + bd + Xn) + od;
+}
+
+
+/* Fetch operands */
+INLINE uint OPER_AY_AI_8(void)  {uint ea = EA_AY_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PI_8(void)  {uint ea = EA_AY_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PD_8(void)  {uint ea = EA_AY_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_DI_8(void)  {uint ea = EA_AY_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_IX_8(void)  {uint ea = EA_AY_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_AX_AI_8(void)  {uint ea = EA_AX_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PI_8(void)  {uint ea = EA_AX_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PD_8(void)  {uint ea = EA_AX_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_DI_8(void)  {uint ea = EA_AX_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_IX_8(void)  {uint ea = EA_AX_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_A7_PI_8(void)  {uint ea = EA_A7_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_A7_PD_8(void)  {uint ea = EA_A7_PD_8();  return m68ki_read_8(ea); }
+
+INLINE uint OPER_AW_8(void)     {uint ea = EA_AW_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AW_16(void)    {uint ea = EA_AW_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AW_32(void)    {uint ea = EA_AW_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_AL_8(void)     {uint ea = EA_AL_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AL_16(void)    {uint ea = EA_AL_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AL_32(void)    {uint ea = EA_AL_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_PCDI_8(void)   {uint ea = EA_PCDI_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCDI_16(void)  {uint ea = EA_PCDI_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCDI_32(void)  {uint ea = EA_PCDI_32();  return m68ki_read_pcrel_32(ea);}
+INLINE uint OPER_PCIX_8(void)   {uint ea = EA_PCIX_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCIX_16(void)  {uint ea = EA_PCIX_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCIX_32(void)  {uint ea = EA_PCIX_32();  return m68ki_read_pcrel_32(ea);}
+
+
+
+/* ---------------------------- Stack Functions --------------------------- */
+
+/* Push/pull data from the stack */
+INLINE void m68ki_push_16(uint value)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+	m68ki_write_16(REG_SP, value);
+}
+
+INLINE void m68ki_push_32(uint value)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+	m68ki_write_32(REG_SP, value);
+}
+
+INLINE uint m68ki_pull_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+	return m68ki_read_16(REG_SP-2);
+}
+
+INLINE uint m68ki_pull_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+	return m68ki_read_32(REG_SP-4);
+}
+
+
+/* Increment/decrement the stack as if doing a push/pull but
+ * don't do any memory access.
+ */
+INLINE void m68ki_fake_push_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+}
+
+INLINE void m68ki_fake_push_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+}
+
+INLINE void m68ki_fake_pull_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+}
+
+INLINE void m68ki_fake_pull_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+}
+
+
+/* ----------------------------- Program Flow ----------------------------- */
+
+/* Jump to a new program location or vector.
+ * These functions will also call the pc_changed callback if it was enabled
+ * in m68kconf.h.
+ */
+INLINE void m68ki_jump(uint new_pc)
+{
+	REG_PC = new_pc;
+	m68ki_pc_changed(REG_PC);
+}
+
+INLINE void m68ki_jump_vector(uint vector)
+{
+	REG_PC = (vector<<2) + REG_VBR;
+	REG_PC = m68ki_read_data_32(REG_PC);
+	m68ki_pc_changed(REG_PC);
+}
+
+
+/* Branch to a new memory location.
+ * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h.
+ * So far I've found no problems with not calling pc_changed for 8 or 16
+ * bit branches.
+ */
+INLINE void m68ki_branch_8(uint offset)
+{
+	REG_PC += MAKE_INT_8(offset);
+}
+
+INLINE void m68ki_branch_16(uint offset)
+{
+	REG_PC += MAKE_INT_16(offset);
+}
+
+INLINE void m68ki_branch_32(uint offset)
+{
+	REG_PC += offset;
+	m68ki_pc_changed(REG_PC);
+}
+
+
+
+/* ---------------------------- Status Register --------------------------- */
+
+/* Set the S flag and change the active stack pointer.
+ * Note that value MUST be 4 or 0.
+ */
+INLINE void m68ki_set_s_flag(uint value)
+{
+	/* Backup the old stack pointer */
+	REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
+	/* Set the S flag */
+	FLAG_S = value;
+	/* Set the new stack pointer */
+	REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];
+}
+
+/* Set the S and M flags and change the active stack pointer.
+ * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M).
+ */
+INLINE void m68ki_set_sm_flag(uint value)
+{
+	/* Backup the old stack pointer */
+	REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
+	/* Set the S and M flags */
+	FLAG_S = value & SFLAG_SET;
+	FLAG_M = value & MFLAG_SET;
+	/* Set the new stack pointer */
+	REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];
+}
+
+
+/* Set the condition code register */
+INLINE void m68ki_set_ccr(uint value)
+{
+	FLAG_X = BIT_4(value)  << 4;
+	FLAG_N = BIT_3(value)  << 4;
+	FLAG_Z = !BIT_2(value);
+	FLAG_V = BIT_1(value)  << 6;
+	FLAG_C = BIT_0(value)  << 8;
+}
+
+/* Set the status register but don't check for interrupts */
+INLINE void m68ki_set_sr_noint(uint value)
+{
+	/* Mask out the "unimplemented" bits */
+	value &= CPU_SR_MASK;
+
+	/* Now set the status register */
+	FLAG_T1 = BIT_F(value);
+	FLAG_T0 = BIT_E(value);
+	FLAG_INT_MASK = value & 0x0700;
+	m68ki_set_ccr(value);
+	m68ki_set_sm_flag((value >> 11) & 6);
+}
+
+/* Set the status register and check for interrupts */
+INLINE void m68ki_set_sr(uint value)
+{
+	m68ki_set_sr_noint(value);
+	m68ki_check_interrupts();
+}
+
+
+/* ------------------------- Exception Processing ------------------------- */
+
+/* Initiate exception processing */
+INLINE uint m68ki_init_exception(void)
+{
+	/* Save the old status register */
+	uint sr = m68ki_get_sr();
+
+	/* Turn off trace flag, clear pending traces */
+	FLAG_T1 = FLAG_T0 = 0;
+	m68ki_clear_trace();
+	/* Enter supervisor mode */
+	m68ki_set_s_flag(SFLAG_SET);
+
+	return sr;
+}
+
+/* 3 word stack frame (68000 only) */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr)
+{
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 0 stack frame.
+ * This is the standard stack frame for 68010+.
+ */
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector)
+{
+	/* Stack a 3-word frame if we are 68000 */
+	if(CPU_TYPE == CPU_TYPE_000)
+	{
+		m68ki_stack_frame_3word(pc, sr);
+		return;
+	}
+	m68ki_push_16(vector<<2);
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 1 stack frame (68020).
+ * For 68020, this is the 4 word throwaway frame.
+ */
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector)
+{
+	m68ki_push_16(0x1000 | (vector<<2));
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 2 stack frame.
+ * This is used only by 68020 for trap exceptions.
+ */
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector)
+{
+	m68ki_push_32(REG_PPC);
+	m68ki_push_16(0x2000 | (vector<<2));
+	m68ki_push_32(REG_PC);
+	m68ki_push_16(sr);
+}
+
+
+/* Bus error stack frame (68000 only).
+ */
+INLINE void m68ki_stack_frame_buserr(uint pc, uint sr, uint address, uint write, uint instruction, uint fc)
+{
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+	m68ki_push_16(REG_IR);
+	m68ki_push_32(address);	/* access address */
+	/* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC
+	 * R/W  0 = write, 1 = read
+	 * I/N  0 = instruction, 1 = not
+	 * FC   3-bit function code
+	 */
+	m68ki_push_16(((!write)<<4) | ((!instruction)<<3) | fc);
+}
+
+/* Format 8 stack frame (68010).
+ * 68010 only.  This is the 29 word bus/address error frame.
+ */
+void m68ki_stack_frame_1000(uint pc, uint sr, uint vector)
+{
+	/* VERSION
+	 * NUMBER
+	 * INTERNAL INFORMATION, 16 WORDS
+	 */
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+
+	/* INSTRUCTION INPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* DATA INPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* DATA OUTPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* FAULT ADDRESS */
+	m68ki_push_32(0);
+
+	/* SPECIAL STATUS WORD */
+	m68ki_push_16(0);
+
+	/* 1000, VECTOR OFFSET */
+	m68ki_push_16(0x8000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+/* Format A stack frame (short bus fault).
+ * This is used only by 68020 for bus fault and address error
+ * if the error happens at an instruction boundary.
+ * PC stacked is address of next instruction.
+ */
+void m68ki_stack_frame_1010(uint sr, uint vector, uint pc)
+{
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA OUTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA CYCLE FAULT ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INSTRUCTION PIPE STAGE B */
+	m68ki_push_16(0);
+
+	/* INSTRUCTION PIPE STAGE C */
+	m68ki_push_16(0);
+
+	/* SPECIAL STATUS REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* 1010, VECTOR OFFSET */
+	m68ki_push_16(0xa000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+/* Format B stack frame (long bus fault).
+ * This is used only by 68020 for bus fault and address error
+ * if the error happens during instruction execution.
+ * PC stacked is address of instruction in progress.
+ */
+void m68ki_stack_frame_1011(uint sr, uint vector, uint pc)
+{
+	/* INTERNAL REGISTERS (18 words) */
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+
+	/* VERSION# (4 bits), INTERNAL INFORMATION */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTERS (3 words) */
+	m68ki_push_32(0);
+	m68ki_push_16(0);
+
+	/* DATA INTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTERS (2 words) */
+	m68ki_push_32(0);
+
+	/* STAGE B ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER (4 words) */
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+
+	/* DATA OUTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA CYCLE FAULT ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INSTRUCTION PIPE STAGE B */
+	m68ki_push_16(0);
+
+	/* INSTRUCTION PIPE STAGE C */
+	m68ki_push_16(0);
+
+	/* SPECIAL STATUS REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* 1011, VECTOR OFFSET */
+	m68ki_push_16(0xb000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+
+/* Used for Group 2 exceptions.
+ * These stack a type 2 frame on the 020.
+ */
+INLINE void m68ki_exception_trap(uint vector)
+{
+	uint sr = m68ki_init_exception();
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+		m68ki_stack_frame_0000(REG_PC, sr, vector);
+	else
+		m68ki_stack_frame_0010(sr, vector);
+
+	m68ki_jump_vector(vector);
+
+	/* Use up some clock cycles */
+	USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
+INLINE void m68ki_exception_trapN(uint vector)
+{
+	uint sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, vector);
+	m68ki_jump_vector(vector);
+
+	/* Use up some clock cycles */
+	USE_CYCLES(CYC_EXCEPTION[vector]);
+}
+
+/* Exception for trace mode */
+INLINE void m68ki_exception_trace(void)
+{
+	uint sr = m68ki_init_exception();
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+		m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE);
+	else
+		m68ki_stack_frame_0010(sr, EXCEPTION_TRACE);
+
+	m68ki_jump_vector(EXCEPTION_TRACE);
+
+	/* Trace nullifies a STOP instruction */
+	CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+	/* Use up some clock cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]);
+}
+
+/* Exception for privilege violation */
+INLINE void m68ki_exception_privilege_violation(void)
+{
+	uint sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_PRIVILEGE_VIOLATION);
+	m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for A-Line instructions */
+INLINE void m68ki_exception_1010(void)
+{
+	uint sr;
+#if M68K_LOG_1010_1111 == OPT_ON
+	M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+					 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+#endif
+
+	sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC-2, sr, EXCEPTION_1010);
+	m68ki_jump_vector(EXCEPTION_1010);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for F-Line instructions */
+INLINE void m68ki_exception_1111(void)
+{
+	uint sr;
+
+#if M68K_LOG_1010_1111 == OPT_ON
+	M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+					 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+#endif
+
+	sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC-2, sr, EXCEPTION_1111);
+	m68ki_jump_vector(EXCEPTION_1111);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for illegal instructions */
+INLINE void m68ki_exception_illegal(void)
+{
+	uint sr;
+
+	M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n",
+				 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+				 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+
+	sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_ILLEGAL_INSTRUCTION);
+	m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for format errror in RTE */
+INLINE void m68ki_exception_format_error(void)
+{
+	uint sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR);
+	m68ki_jump_vector(EXCEPTION_FORMAT_ERROR);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for address error */
+INLINE void m68ki_exception_address_error(void)
+{
+	/* Not emulated yet */
+}
+
+
+/* Service an interrupt request and start exception processing */
+void m68ki_exception_interrupt(uint int_level)
+{
+	uint vector;
+	uint sr;
+	uint new_pc;
+
+	/* Turn off the stopped state */
+	CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+	/* If we are halted, don't do anything */
+	if(CPU_STOPPED)
+		return;
+
+	/* Acknowledge the interrupt */
+	vector = m68ki_int_ack(int_level);
+
+	/* Get the interrupt vector */
+	if(vector == M68K_INT_ACK_AUTOVECTOR)
+		/* Use the autovectors.  This is the most commonly used implementation */
+		vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
+	else if(vector == M68K_INT_ACK_SPURIOUS)
+		/* Called if no devices respond to the interrupt acknowledge */
+		vector = EXCEPTION_SPURIOUS_INTERRUPT;
+	else if(vector > 255)
+	{
+		M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",
+				 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector));
+		return;
+	}
+
+	/* Start exception processing */
+	sr = m68ki_init_exception();
+
+	/* Set the interrupt mask to the level of the one being serviced */
+	FLAG_INT_MASK = int_level<<8;
+
+	/* Get the new PC */
+	new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);
+
+	/* If vector is uninitialized, call the uninitialized interrupt vector */
+	if(new_pc == 0)
+		new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR);
+
+	/* Generate a stack frame */
+	m68ki_stack_frame_0000(REG_PC, sr, vector);
+	if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Create throwaway frame */
+		m68ki_set_sm_flag(FLAG_S);	/* clear M */
+		sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */
+		m68ki_stack_frame_0001(REG_PC, sr, vector);
+	}
+
+	m68ki_jump(new_pc);
+
+	/* Defer cycle counting until later */
+	CPU_INT_CYCLES += CYC_EXCEPTION[vector];
+
+//#if !M68K_EMULATE_INT_ACK
+	/* Automatically clear IRQ if we are not using an acknowledge scheme */
+	CPU_INT_LEVEL = 0;
+//#endif /* M68K_EMULATE_INT_ACK */
+}
+
+
+/* ASG: Check for interrupts */
+INLINE void m68ki_check_interrupts(void)
+{
+	if(CPU_INT_LEVEL > FLAG_INT_MASK)
+		m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
+}
+
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCPU__HEADER */
diff --git a/MCUME_pico2/picogenold/m68kopac.c b/MCUME_pico2/picogenold/m68kopac.c
new file mode 100644
index 0000000..553497f
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kopac.c
@@ -0,0 +1,11948 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_1010(void)
+{
+	m68ki_exception_1010();
+}
+
+
+void m68k_op_1111(void)
+{
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_abcd_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_abcd_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_add_8_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pi7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pd7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = AY;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_adda_16_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
+}
+
+
+void m68k_op_adda_16_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
+}
+
+
+void m68k_op_adda_16_ai(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_AI_16()));
+}
+
+
+void m68k_op_adda_16_pi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PI_16()));
+}
+
+
+void m68k_op_adda_16_pd(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PD_16()));
+}
+
+
+void m68k_op_adda_16_di(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_DI_16()));
+}
+
+
+void m68k_op_adda_16_ix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_IX_16()));
+}
+
+
+void m68k_op_adda_16_aw(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AW_16()));
+}
+
+
+void m68k_op_adda_16_al(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AL_16()));
+}
+
+
+void m68k_op_adda_16_pcdi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCDI_16()));
+}
+
+
+void m68k_op_adda_16_pcix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCIX_16()));
+}
+
+
+void m68k_op_adda_16_i(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_adda_32_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
+}
+
+
+void m68k_op_adda_32_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
+}
+
+
+void m68k_op_adda_32_ai(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_AI_32());
+}
+
+
+void m68k_op_adda_32_pi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PI_32());
+}
+
+
+void m68k_op_adda_32_pd(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PD_32());
+}
+
+
+void m68k_op_adda_32_di(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_DI_32());
+}
+
+
+void m68k_op_adda_32_ix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_IX_32());
+}
+
+
+void m68k_op_adda_32_aw(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AW_32());
+}
+
+
+void m68k_op_adda_32_al(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AL_32());
+}
+
+
+void m68k_op_adda_32_pcdi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCDI_32());
+}
+
+
+void m68k_op_adda_32_pcix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCIX_32());
+}
+
+
+void m68k_op_adda_32_i(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_I_32());
+}
+
+
+void m68k_op_addi_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_addi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addq_8_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pi7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pd7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addq_16_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+void m68k_op_addq_16_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_addq_32_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+void m68k_op_addq_32_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addx_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_addx_16_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_addx_32_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_addx_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_16_mm(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint ea  = EA_AX_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_addx_32_mm(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint ea  = EA_AX_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_8_er_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_ai(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pi7(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pd(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pd7(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_di(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_ix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_aw(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_al(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pcdi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pcix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_i(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_ai(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pd(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_di(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_ix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_aw(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_al(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pcdi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pcix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_i(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_d(void)
+{
+	FLAG_Z = DX &= DY;
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_ai(void)
+{
+	FLAG_Z = DX &= OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pi(void)
+{
+	FLAG_Z = DX &= OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pd(void)
+{
+	FLAG_Z = DX &= OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_di(void)
+{
+	FLAG_Z = DX &= OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_ix(void)
+{
+	FLAG_Z = DX &= OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_aw(void)
+{
+	FLAG_Z = DX &= OPER_AW_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_al(void)
+{
+	FLAG_Z = DX &= OPER_AL_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pcdi(void)
+{
+	FLAG_Z = DX &= OPER_PCDI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pcix(void)
+{
+	FLAG_Z = DX &= OPER_PCIX_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_i(void)
+{
+	FLAG_Z = DX &= OPER_I_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_8_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_16_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_32_d(void)
+{
+	FLAG_Z = DY &= (OPER_I_32());
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
+}
+
+
+void m68k_op_andi_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() & src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_asr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(GET_MSB_8(src))
+		res |= m68ki_shift_8_table[shift];
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(GET_MSB_16(src))
+		res |= m68ki_shift_16_table[shift];
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(GET_MSB_32(src))
+		res |= m68ki_shift_32_table[shift];
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 8)
+		{
+			if(GET_MSB_8(src))
+				res |= m68ki_shift_8_table[shift];
+
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+			FLAG_X = FLAG_C = src << (9-shift);
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_8(src))
+		{
+			*r_dst |= 0xff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 16)
+		{
+			if(GET_MSB_16(src))
+				res |= m68ki_shift_16_table[shift];
+
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_16(src))
+		{
+			*r_dst |= 0xffff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			if(GET_MSB_32(src))
+				res |= m68ki_shift_32_table[shift];
+
+			*r_dst = res;
+
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_32(src))
+		{
+			*r_dst = 0xffffffff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_X = FLAG_C = src << shift;
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	src &= m68ki_shift_8_table[shift + 1];
+	FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
+}
+
+
+void m68k_op_asl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (8-shift);
+	src &= m68ki_shift_16_table[shift + 1];
+	FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+}
+
+
+void m68k_op_asl_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (24-shift);
+	src &= m68ki_shift_32_table[shift + 1];
+	FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+}
+
+
+void m68k_op_asl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_8_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_X = FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_16_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_32_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_bhi_8(void)
+{
+	if(COND_HI())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bls_8(void)
+{
+	if(COND_LS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bcc_8(void)
+{
+	if(COND_CC())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bcs_8(void)
+{
+	if(COND_CS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bne_8(void)
+{
+	if(COND_NE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_beq_8(void)
+{
+	if(COND_EQ())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bvc_8(void)
+{
+	if(COND_VC())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bvs_8(void)
+{
+	if(COND_VS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bpl_8(void)
+{
+	if(COND_PL())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bmi_8(void)
+{
+	if(COND_MI())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bge_8(void)
+{
+	if(COND_GE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_blt_8(void)
+{
+	if(COND_LT())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bgt_8(void)
+{
+	if(COND_GT())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_ble_8(void)
+{
+	if(COND_LE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bhi_16(void)
+{
+	if(COND_HI())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bls_16(void)
+{
+	if(COND_LS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bcc_16(void)
+{
+	if(COND_CC())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bcs_16(void)
+{
+	if(COND_CS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bne_16(void)
+{
+	if(COND_NE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_beq_16(void)
+{
+	if(COND_EQ())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bvc_16(void)
+{
+	if(COND_VC())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bvs_16(void)
+{
+	if(COND_VS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bpl_16(void)
+{
+	if(COND_PL())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bmi_16(void)
+{
+	if(COND_MI())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bge_16(void)
+{
+	if(COND_GE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_blt_16(void)
+{
+	if(COND_LT())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bgt_16(void)
+{
+	if(COND_GT())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_ble_16(void)
+{
+	if(COND_LE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bhi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bls_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bcs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bne_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_beq_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bvc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bvs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bpl_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bmi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bge_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_blt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bgt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_ble_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bchg_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst ^= mask;
+}
+
+
+void m68k_op_bchg_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst ^= mask;
+}
+
+
+void m68k_op_bchg_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bclr_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst &= ~mask;
+}
+
+
+void m68k_op_bclr_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst &= ~mask;
+}
+
+
+void m68k_op_bclr_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bfchg_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data ^= mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data &= ~mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2>>12)&7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data >>= 32 - width;
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2>>12)&7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+		uint bit;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data >>= 32 - width;
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+		uint64 insert = REG_D[(word2>>12)&7];
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		insert = MASK_OUT_ABOVE_32(insert << (32 - width));
+		FLAG_N = NFLAG_32(insert);
+		FLAG_Z = insert;
+		insert = ROR_32(insert, offset);
+
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data &= ~mask;
+		*data |= insert;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data |= mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_PCDI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_PCIX_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bkpt(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0);	/* auto-disable (see m68kcpu.h) */
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bra_8(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_bra_16(void)
+{
+	uint offset = OPER_I_16();
+	REG_PC -= 2;
+	m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+	m68ki_branch_16(offset);
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_bra_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint offset = OPER_I_32();
+		REG_PC -= 4;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_32(offset);
+		if(REG_PC == REG_PPC)
+			USE_ALL_CYCLES();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bset_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst |= mask;
+}
+
+
+void m68k_op_bset_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst |= mask;
+}
+
+
+void m68k_op_bset_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bsr_8(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+void m68k_op_bsr_16(void)
+{
+	uint offset = OPER_I_16();
+	m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	REG_PC -= 2;
+	m68ki_branch_16(offset);
+}
+
+
+void m68k_op_bsr_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint offset = OPER_I_32();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_push_32(REG_PC);
+		REG_PC -= 4;
+		m68ki_branch_32(offset);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_btst_32_r_d(void)
+{
+	FLAG_Z = DY & (1 << (DX & 0x1f));
+}
+
+
+void m68k_op_btst_8_r_ai(void)
+{
+	FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pi(void)
+{
+	FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pi7(void)
+{
+	FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pd(void)
+{
+	FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pd7(void)
+{
+	FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_di(void)
+{
+	FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_ix(void)
+{
+	FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_aw(void)
+{
+	FLAG_Z = OPER_AW_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_al(void)
+{
+	FLAG_Z = OPER_AL_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pcdi(void)
+{
+	FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pcix(void)
+{
+	FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_i(void)
+{
+	FLAG_Z = OPER_I_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_32_s_d(void)
+{
+	FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+}
+
+
+void m68k_op_btst_8_s_ai(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_AI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pi(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_PI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pi7(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_A7_PI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pd(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_PD_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pd7(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_A7_PD_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_di(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_DI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_ix(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_IX_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_aw(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AW_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_al(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AL_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pcdi(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_PCDI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pcix(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_PCIX_8() & (1 << bit);
+}
+
+
+void m68k_op_callm_32_ai(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_AI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_di(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_DI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_ix(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_IX_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_aw(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AW_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_al(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AL_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_PCDI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_pcix(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_PCIX_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pi7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_A7_PI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pd7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_A7_PD_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas2_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_32();
+		uint* compare1 = &REG_D[(word2 >> 16) & 7];
+		uint ea1 = REG_DA[(word2 >> 28) & 15];
+		uint dest1 = m68ki_read_16(ea1);
+		uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
+		uint* compare2 = &REG_D[word2 & 7];
+		uint ea2 = REG_DA[(word2 >> 12) & 15];
+		uint dest2 = m68ki_read_16(ea2);
+		uint res2;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res1);
+		FLAG_Z = MASK_OUT_ABOVE_16(res1);
+		FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
+		FLAG_C = CFLAG_16(res1);
+
+		if(COND_EQ())
+		{
+			res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
+
+			FLAG_N = NFLAG_16(res2);
+			FLAG_Z = MASK_OUT_ABOVE_16(res2);
+			FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
+			FLAG_C = CFLAG_16(res2);
+
+			if(COND_EQ())
+			{
+				USE_CYCLES(3);
+				m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
+				m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
+				return;
+			}
+		}
+		*compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
+		*compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas2_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_32();
+		uint* compare1 = &REG_D[(word2 >> 16) & 7];
+		uint ea1 = REG_DA[(word2 >> 28) & 15];
+		uint dest1 = m68ki_read_32(ea1);
+		uint res1 = dest1 - *compare1;
+		uint* compare2 = &REG_D[word2 & 7];
+		uint ea2 = REG_DA[(word2 >> 12) & 15];
+		uint dest2 = m68ki_read_32(ea2);
+		uint res2;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res1);
+		FLAG_Z = MASK_OUT_ABOVE_32(res1);
+		FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
+		FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
+
+		if(COND_EQ())
+		{
+			res2 = dest2 - *compare2;
+
+			FLAG_N = NFLAG_32(res2);
+			FLAG_Z = MASK_OUT_ABOVE_32(res2);
+			FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
+			FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
+
+			if(COND_EQ())
+			{
+				USE_CYCLES(3);
+				m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
+				m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
+				return;
+			}
+		}
+		*compare1 = dest1;
+		*compare2 = dest2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_16_d(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(DY);
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_ai(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_AI_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pi(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_PI_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pd(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_PD_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_di(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_DI_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_ix(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_IX_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_aw(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AW_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_al(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AL_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pcdi(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_PCDI_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pcix(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_PCIX_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_i(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_I_16());
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(DY);
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_AI_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_PI_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_PD_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_DI_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_IX_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AW_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AL_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_PCDI_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_PCIX_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_I_32());
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_AI_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_DI_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_IX_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AW_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AL_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCDI_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCIX_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_8(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_AI_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_DI_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_IX_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AW_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AL_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCDI_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCIX_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 1);
+
+		if(!BIT_F(word2))
+			compare = MAKE_INT_16(compare);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_AI_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_DI_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_IX_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AW_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AL_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCDI_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCIX_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 1);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_clr_8_d(void)
+{
+	DY &= 0xffffff00;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_d(void)
+{
+	DY &= 0xffff0000;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_ai(void)
+{
+	m68ki_write_16(EA_AY_AI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_pi(void)
+{
+	m68ki_write_16(EA_AY_PI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_pd(void)
+{
+	m68ki_write_16(EA_AY_PD_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_di(void)
+{
+	m68ki_write_16(EA_AY_DI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_ix(void)
+{
+	m68ki_write_16(EA_AY_IX_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_aw(void)
+{
+	m68ki_write_16(EA_AW_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_al(void)
+{
+	m68ki_write_16(EA_AL_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_d(void)
+{
+	DY = 0;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_ai(void)
+{
+	m68ki_write_32(EA_AY_AI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_pi(void)
+{
+	m68ki_write_32(EA_AY_PI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_pd(void)
+{
+	m68ki_write_32(EA_AY_PD_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_di(void)
+{
+	m68ki_write_32(EA_AY_DI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_ix(void)
+{
+	m68ki_write_32(EA_AY_IX_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_aw(void)
+{
+	m68ki_write_32(EA_AW_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_al(void)
+{
+	m68ki_write_32(EA_AL_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_cmp_8_d(void)
+{
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_ai(void)
+{
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pi(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pi7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pd(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pd7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_di(void)
+{
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_ix(void)
+{
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_aw(void)
+{
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_al(void)
+{
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pcdi(void)
+{
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pcix(void)
+{
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_i(void)
+{
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_16_d(void)
+{
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_a(void)
+{
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_ai(void)
+{
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pi(void)
+{
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pd(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_di(void)
+{
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_ix(void)
+{
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_aw(void)
+{
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_al(void)
+{
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pcdi(void)
+{
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pcix(void)
+{
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_i(void)
+{
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_32_d(void)
+{
+	uint src = DY;
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_a(void)
+{
+	uint src = AY;
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_d(void)
+{
+	uint src = MAKE_INT_16(DY);
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_a(void)
+{
+	uint src = MAKE_INT_16(AY);
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_ai(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_AI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pi(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_PI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pd(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_PD_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_di(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_DI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_ix(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_IX_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_aw(void)
+{
+	uint src = MAKE_INT_16(OPER_AW_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_al(void)
+{
+	uint src = MAKE_INT_16(OPER_AL_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pcdi(void)
+{
+	uint src = MAKE_INT_16(OPER_PCDI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pcix(void)
+{
+	uint src = MAKE_INT_16(OPER_PCIX_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_i(void)
+{
+	uint src = MAKE_INT_16(OPER_I_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_d(void)
+{
+	uint src = DY;
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_a(void)
+{
+	uint src = AY;
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_8_d(void)
+{
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(DY);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_AI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_PD_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_A7_PD_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_DI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_IX_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AW_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AL_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_8();
+		uint dst = OPER_PCDI_8();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(src, dst, res);
+		FLAG_C = CFLAG_8(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_8();
+		uint dst = OPER_PCIX_8();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(src, dst, res);
+		FLAG_C = CFLAG_8(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_16_d(void)
+{
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(DY);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_AI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_PI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_PD_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_DI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_IX_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AW_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AL_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_16();
+		uint dst = OPER_PCDI_16();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(src, dst, res);
+		FLAG_C = CFLAG_16(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_16();
+		uint dst = OPER_PCIX_16();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(src, dst, res);
+		FLAG_C = CFLAG_16(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_32_d(void)
+{
+	uint src = OPER_I_32();
+	uint dst = DY;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_AI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_PI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_PD_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_DI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_IX_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AW_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AL_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_32();
+		uint dst = OPER_PCDI_32();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(src, dst, res);
+		FLAG_C = CFLAG_SUB_32(src, dst, res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_32();
+		uint dst = OPER_PCIX_32();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(src, dst, res);
+		FLAG_C = CFLAG_SUB_32(src, dst, res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpm_8_ax7(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8_ay7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = OPER_AX_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8_axy7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = OPER_AX_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_16(void)
+{
+	uint src = OPER_AY_PI_16();
+	uint dst = OPER_AX_PI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpm_32(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = OPER_AX_PI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cpbcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpdbcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpgen_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpscc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cptrapcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/m68kopdm.c b/MCUME_pico2/picogenold/m68kopdm.c
new file mode 100644
index 0000000..e60992a
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kopdm.c
@@ -0,0 +1,13286 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_dbt_16(void)
+{
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbf_16(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+	if(res != 0xffff)
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbhi_16(void)
+{
+	if(COND_NOT_HI())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbls_16(void)
+{
+	if(COND_NOT_LS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbcc_16(void)
+{
+	if(COND_NOT_CC())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbcs_16(void)
+{
+	if(COND_NOT_CS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbne_16(void)
+{
+	if(COND_NOT_NE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbeq_16(void)
+{
+	if(COND_NOT_EQ())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbvc_16(void)
+{
+	if(COND_NOT_VC())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbvs_16(void)
+{
+	if(COND_NOT_VS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbpl_16(void)
+{
+	if(COND_NOT_PL())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbmi_16(void)
+{
+	if(COND_NOT_MI())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbge_16(void)
+{
+	if(COND_NOT_GE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dblt_16(void)
+{
+	if(COND_NOT_LT())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbgt_16(void)
+{
+	if(COND_NOT_GT())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dble_16(void)
+{
+	if(COND_NOT_LE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_divs_16_d(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(DY);
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_ai(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_AI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pi(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_PI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pd(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_PD_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_di(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_DI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_ix(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_IX_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_aw(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AW_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_al(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AL_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_PCDI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_PCIX_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_i(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_I_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divl_32_d(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor   = DY;
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = DY;
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_ai(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_AI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_AI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_PI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_PI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pd(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_PD_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_PD_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_di(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_DI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_DI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_ix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_IX_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_IX_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_aw(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AW_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AW_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_al(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AL_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AL_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pcdi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_PCDI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_PCDI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pcix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_PCIX_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_PCIX_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_i(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_I_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_I_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_eor_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_d(void)
+{
+	uint res = DY ^= DX;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_d(void)
+{
+	uint res = DY ^= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
+}
+
+
+void m68k_op_eori_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() ^ src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_exg_32_dd(void)
+{
+	uint* reg_a = &DX;
+	uint* reg_b = &DY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_exg_32_aa(void)
+{
+	uint* reg_a = &AX;
+	uint* reg_b = &AY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_exg_32_da(void)
+{
+	uint* reg_a = &DX;
+	uint* reg_b = &AY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_ext_16(void)
+{
+	uint* r_dst = &DY;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
+
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_ext_32(void)
+{
+	uint* r_dst = &DY;
+
+	*r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
+
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_extb_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint* r_dst = &DY;
+
+		*r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
+
+		FLAG_N = NFLAG_32(*r_dst);
+		FLAG_Z = *r_dst;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_illegal(void)
+{
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_jmp_32_ai(void)
+{
+	m68ki_jump(EA_AY_AI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_di(void)
+{
+	m68ki_jump(EA_AY_DI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_ix(void)
+{
+	m68ki_jump(EA_AY_IX_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_aw(void)
+{
+	m68ki_jump(EA_AW_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_al(void)
+{
+	m68ki_jump(EA_AL_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_pcdi(void)
+{
+	m68ki_jump(EA_PCDI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_pcix(void)
+{
+	m68ki_jump(EA_PCIX_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jsr_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_al(void)
+{
+	uint ea = EA_AL_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_pcdi(void)
+{
+	uint ea = EA_PCDI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_pcix(void)
+{
+	uint ea = EA_PCIX_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_lea_32_ai(void)
+{
+	AX = EA_AY_AI_32();
+}
+
+
+void m68k_op_lea_32_di(void)
+{
+	AX = EA_AY_DI_32();
+}
+
+
+void m68k_op_lea_32_ix(void)
+{
+	AX = EA_AY_IX_32();
+}
+
+
+void m68k_op_lea_32_aw(void)
+{
+	AX = EA_AW_32();
+}
+
+
+void m68k_op_lea_32_al(void)
+{
+	AX = EA_AL_32();
+}
+
+
+void m68k_op_lea_32_pcdi(void)
+{
+	AX = EA_PCDI_32();
+}
+
+
+void m68k_op_lea_32_pcix(void)
+{
+	AX = EA_PCIX_32();
+}
+
+
+void m68k_op_link_16_a7(void)
+{
+	REG_A[7] -= 4;
+	m68ki_write_32(REG_A[7], REG_A[7]);
+	REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_link_16(void)
+{
+	uint* r_dst = &AY;
+
+	m68ki_push_32(*r_dst);
+	*r_dst = REG_A[7];
+	REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_link_32_a7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_A[7] -= 4;
+		m68ki_write_32(REG_A[7], REG_A[7]);
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_link_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint* r_dst = &AY;
+
+		m68ki_push_32(*r_dst);
+		*r_dst = REG_A[7];
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_lsr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << (9-shift);
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << shift;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (8-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (24-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_X = FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_al(void)
+{
+	uint res = OPER_AL_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_i(void)
+{
+	uint res = OPER_I_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_al(void)
+{
+	uint res = OPER_AL_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_i(void)
+{
+	uint res = OPER_I_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_d(void)
+{
+	uint res = DY;
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_a(void)
+{
+	uint res = AY;
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_al(void)
+{
+	uint res = OPER_AL_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_i(void)
+{
+	uint res = OPER_I_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_PD_32();
+
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, res & 0xFFFF );
+            m68ki_write_16(ea, (res >> 16) & 0xFFFF );
+#else
+            m68ki_write_32(ea, res);
+#endif
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_movea_16_d(void)
+{
+	AX = MAKE_INT_16(DY);
+}
+
+
+void m68k_op_movea_16_a(void)
+{
+	AX = MAKE_INT_16(AY);
+}
+
+
+void m68k_op_movea_16_ai(void)
+{
+	AX = MAKE_INT_16(OPER_AY_AI_16());
+}
+
+
+void m68k_op_movea_16_pi(void)
+{
+	AX = MAKE_INT_16(OPER_AY_PI_16());
+}
+
+
+void m68k_op_movea_16_pd(void)
+{
+	AX = MAKE_INT_16(OPER_AY_PD_16());
+}
+
+
+void m68k_op_movea_16_di(void)
+{
+	AX = MAKE_INT_16(OPER_AY_DI_16());
+}
+
+
+void m68k_op_movea_16_ix(void)
+{
+	AX = MAKE_INT_16(OPER_AY_IX_16());
+}
+
+
+void m68k_op_movea_16_aw(void)
+{
+	AX = MAKE_INT_16(OPER_AW_16());
+}
+
+
+void m68k_op_movea_16_al(void)
+{
+	AX = MAKE_INT_16(OPER_AL_16());
+}
+
+
+void m68k_op_movea_16_pcdi(void)
+{
+	AX = MAKE_INT_16(OPER_PCDI_16());
+}
+
+
+void m68k_op_movea_16_pcix(void)
+{
+	AX = MAKE_INT_16(OPER_PCIX_16());
+}
+
+
+void m68k_op_movea_16_i(void)
+{
+	AX = MAKE_INT_16(OPER_I_16());
+}
+
+
+void m68k_op_movea_32_d(void)
+{
+	AX = DY;
+}
+
+
+void m68k_op_movea_32_a(void)
+{
+	AX = AY;
+}
+
+
+void m68k_op_movea_32_ai(void)
+{
+	AX = OPER_AY_AI_32();
+}
+
+
+void m68k_op_movea_32_pi(void)
+{
+	AX = OPER_AY_PI_32();
+}
+
+
+void m68k_op_movea_32_pd(void)
+{
+	AX = OPER_AY_PD_32();
+}
+
+
+void m68k_op_movea_32_di(void)
+{
+	AX = OPER_AY_DI_32();
+}
+
+
+void m68k_op_movea_32_ix(void)
+{
+	AX = OPER_AY_IX_32();
+}
+
+
+void m68k_op_movea_32_aw(void)
+{
+	AX = OPER_AW_32();
+}
+
+
+void m68k_op_movea_32_al(void)
+{
+	AX = OPER_AL_32();
+}
+
+
+void m68k_op_movea_32_pcdi(void)
+{
+	AX = OPER_PCDI_32();
+}
+
+
+void m68k_op_movea_32_pcix(void)
+{
+	AX = OPER_PCIX_32();
+}
+
+
+void m68k_op_movea_32_i(void)
+{
+	AX = OPER_I_32();
+}
+
+
+void m68k_op_move_16_frc_d(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_AI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_PI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_PD_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_DI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_IX_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AW_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AL_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_toc_d(void)
+{
+	m68ki_set_ccr(DY);
+}
+
+
+void m68k_op_move_16_toc_ai(void)
+{
+	m68ki_set_ccr(OPER_AY_AI_16());
+}
+
+
+void m68k_op_move_16_toc_pi(void)
+{
+	m68ki_set_ccr(OPER_AY_PI_16());
+}
+
+
+void m68k_op_move_16_toc_pd(void)
+{
+	m68ki_set_ccr(OPER_AY_PD_16());
+}
+
+
+void m68k_op_move_16_toc_di(void)
+{
+	m68ki_set_ccr(OPER_AY_DI_16());
+}
+
+
+void m68k_op_move_16_toc_ix(void)
+{
+	m68ki_set_ccr(OPER_AY_IX_16());
+}
+
+
+void m68k_op_move_16_toc_aw(void)
+{
+	m68ki_set_ccr(OPER_AW_16());
+}
+
+
+void m68k_op_move_16_toc_al(void)
+{
+	m68ki_set_ccr(OPER_AL_16());
+}
+
+
+void m68k_op_move_16_toc_pcdi(void)
+{
+	m68ki_set_ccr(OPER_PCDI_16());
+}
+
+
+void m68k_op_move_16_toc_pcix(void)
+{
+	m68ki_set_ccr(OPER_PCIX_16());
+}
+
+
+void m68k_op_move_16_toc_i(void)
+{
+	m68ki_set_ccr(OPER_I_16());
+}
+
+
+void m68k_op_move_16_frs_d(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_ai(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_AI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_pi(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_PI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_pd(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_PD_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_di(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_DI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_ix(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_IX_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_aw(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AW_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_al(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AL_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_d(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_set_sr(DY);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_ai(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_AI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pi(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_PI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pd(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_PD_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_di(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_DI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_ix(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_IX_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_aw(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AW_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_al(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AL_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pcdi(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_PCDI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pcix(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_PCIX_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_i(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_32_fru(void)
+{
+	if(FLAG_S)
+	{
+		AY = REG_USP;
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_32_tou(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_USP = AY;
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_movec_32_cr(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+
+			m68ki_trace_t0();		   /* auto-disable (see m68kcpu.h) */
+			switch (word2 & 0xfff)
+			{
+			case 0x000:			   /* SFC */
+				REG_DA[(word2 >> 12) & 15] = REG_SFC;
+				return;
+			case 0x001:			   /* DFC */
+				REG_DA[(word2 >> 12) & 15] = REG_DFC;
+				return;
+			case 0x002:			   /* CACR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = REG_CACR;
+					return;
+				}
+				return;
+			case 0x800:			   /* USP */
+				REG_DA[(word2 >> 12) & 15] = REG_USP;
+				return;
+			case 0x801:			   /* VBR */
+				REG_DA[(word2 >> 12) & 15] = REG_VBR;
+				return;
+			case 0x802:			   /* CAAR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = REG_CAAR;
+					return;
+				}
+				m68ki_exception_illegal();
+				break;
+			case 0x803:			   /* MSP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x804:			   /* ISP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			default:
+				m68ki_exception_illegal();
+				return;
+			}
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_movec_32_rc(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+
+			m68ki_trace_t0();		   /* auto-disable (see m68kcpu.h) */
+			switch (word2 & 0xfff)
+			{
+			case 0x000:			   /* SFC */
+				REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
+				return;
+			case 0x001:			   /* DFC */
+				REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
+				return;
+			case 0x002:			   /* CACR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_CACR = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x800:			   /* USP */
+				REG_USP = REG_DA[(word2 >> 12) & 15];
+				return;
+			case 0x801:			   /* VBR */
+				REG_VBR = REG_DA[(word2 >> 12) & 15];
+				return;
+			case 0x802:			   /* CAAR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_CAAR = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x803:			   /* MSP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					/* we are in supervisor mode so just check for M flag */
+					if(!FLAG_M)
+					{
+						REG_MSP = REG_DA[(word2 >> 12) & 15];
+						return;
+					}
+					REG_SP = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x804:			   /* ISP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					if(!FLAG_M)
+					{
+						REG_SP = REG_DA[(word2 >> 12) & 15];
+						return;
+					}
+					REG_ISP = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			default:
+				m68ki_exception_illegal();
+				return;
+			}
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_movem_16_re_pd(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			ea -= 2;
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_32_re_pd(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			ea -= 4;
+#if GENESIS_HACKS
+            m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
+            m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
+#else
+			m68ki_write_32(ea, REG_DA[15-i]);
+#endif
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_16_er_pi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_pcdi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCDI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_pcix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCIX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_32_er_pi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_pcdi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCDI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_pcix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCIX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movep_16_re(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = DX;
+
+	m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+void m68k_op_movep_32_re(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+
+	m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+void m68k_op_movep_16_er(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
+}
+
+
+void m68k_op_movep_32_er(void)
+{
+	uint ea = EA_AY_DI_32();
+
+	DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
+		+ (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
+}
+
+
+void m68k_op_moves_8_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pi7(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_A7_PI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pd7(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_A7_PD_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moveq_32(void)
+{
+	uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_AI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_PI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_PD_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_DI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_IX_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AW_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AL_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_PCDI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_PCIX_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_I_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mull_32_d(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = DY;
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = DY;
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_ai(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_AI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_AI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_PI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_PI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pd(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_PD_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_PD_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_di(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_DI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_DI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_ix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_IX_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_IX_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_aw(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AW_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AW_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_al(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AL_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AL_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pcdi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_PCDI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_PCDI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pcix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_PCIX_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_PCIX_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_i(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_I_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_I_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/m68kopnz.c b/MCUME_pico2/picogenold/m68kopnz.c
new file mode 100644
index 0000000..b5be77d
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kopnz.c
@@ -0,0 +1,8746 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_nbcd_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint dst = *r_dst;
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_nbcd_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* officially undefined */
+}
+
+
+void m68k_op_neg_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = *r_dst & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_neg_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (*r_dst & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_neg_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - *r_dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
+	FLAG_V = (*r_dst & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_neg_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_negx_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = *r_dst & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_negx_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (*r_dst & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_negx_16_ai(void)
+{
+	uint ea  = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_pi(void)
+{
+	uint ea  = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_pd(void)
+{
+	uint ea  = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_di(void)
+{
+	uint ea  = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_ix(void)
+{
+	uint ea  = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_aw(void)
+{
+	uint ea  = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_al(void)
+{
+	uint ea  = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
+	FLAG_V = (*r_dst & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_negx_32_ai(void)
+{
+	uint ea  = EA_AY_AI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_pi(void)
+{
+	uint ea  = EA_AY_PI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_pd(void)
+{
+	uint ea  = EA_AY_PD_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_di(void)
+{
+	uint ea  = EA_AY_DI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_ix(void)
+{
+	uint ea  = EA_AY_IX_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_aw(void)
+{
+	uint ea  = EA_AW_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_al(void)
+{
+	uint ea  = EA_AL_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_nop(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+}
+
+
+void m68k_op_not_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_8(~*r_dst);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_16(~*r_dst);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_ai(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pi(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pi7(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pd(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pd7(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_di(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_ix(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_aw(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_al(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pcdi(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pcix(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_i(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_ai(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pi(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pd(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_di(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_ix(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_aw(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_al(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pcdi(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pcix(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_i(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_d(void)
+{
+	uint res = DX |= DY;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_ai(void)
+{
+	uint res = DX |= OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pi(void)
+{
+	uint res = DX |= OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pd(void)
+{
+	uint res = DX |= OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_di(void)
+{
+	uint res = DX |= OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_ix(void)
+{
+	uint res = DX |= OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_aw(void)
+{
+	uint res = DX |= OPER_AW_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_al(void)
+{
+	uint res = DX |= OPER_AL_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pcdi(void)
+{
+	uint res = DX |= OPER_PCDI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pcix(void)
+{
+	uint res = DX |= OPER_PCIX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_i(void)
+{
+	uint res = DX |= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_d(void)
+{
+	uint res = DY |= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
+}
+
+
+void m68k_op_ori_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() | src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_pack_16_rr(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: DX and DY are reversed in Motorola's docs */
+		uint src = DY + OPER_I_16();
+		uint* r_dst = &DX;
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_ax7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_AY_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_AY_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_ay7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_A7_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_A7_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_axy7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint ea_src = EA_A7_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_A7_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_AY_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_AY_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pea_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_aw(void)
+{
+	uint ea = EA_AW_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_al(void)
+{
+	uint ea = EA_AL_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_pcdi(void)
+{
+	uint ea = EA_PCDI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_pcix(void)
+{
+	uint ea = EA_PCIX_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_reset(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_output_reset();		   /* auto-disable (see m68kcpu.h) */
+		USE_CYCLES(CYC_RESET);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_ror_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_8(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-orig_shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_16(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src = *r_dst;
+	uint res = ROR_32(src, shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_8(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_C = src << (8-((shift-1)&7));
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 15;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_16(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_C = (src >> ((shift - 1) & 15)) << 8;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 31;
+	uint64 src = *r_dst;
+	uint res = ROR_32(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = res;
+		FLAG_C = (src >> ((shift - 1) & 31)) << 8;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_8(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = src << orig_shift;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROL_16(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> (8-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src = *r_dst;
+	uint res = ROL_32(src, shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = src >> (24-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_8(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		if(shift != 0)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+		FLAG_C = (src & 1)<<8;
+		FLAG_N = NFLAG_8(src);
+		FLAG_Z = src;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 15;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		if(shift != 0)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+		FLAG_C = (src & 1)<<8;
+		FLAG_N = NFLAG_16(src);
+		FLAG_Z = src;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 31;
+	uint64 src = *r_dst;
+	uint res = ROL_32(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = res;
+
+		FLAG_C = (src >> (32 - shift)) << 8;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+	FLAG_C = FLAG_X = res;
+	res = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src   = *r_dst;
+	uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+	res = ROR_33_64(res, shift);
+
+	FLAG_C = FLAG_X = res >> 24;
+	res = MASK_OUT_ABOVE_32(res);
+
+	*r_dst =  res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+	uint new_x_flag = src & (1 << (shift - 1));
+
+	*r_dst = res;
+
+	FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 9;
+		uint src   = MASK_OUT_ABOVE_8(*r_dst);
+		uint res   = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res;
+		res = MASK_OUT_ABOVE_8(res);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 17;
+		uint src   = MASK_OUT_ABOVE_16(*r_dst);
+		uint res   = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 8;
+		res = MASK_OUT_ABOVE_16(res);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint   shift = orig_shift % 33;
+		uint64 src   = *r_dst;
+		uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+		res = ROR_33_64(res, shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 24;
+		res = MASK_OUT_ABOVE_32(res);
+
+		*r_dst = res;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift % 33;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+	uint new_x_flag = src & (1 << (shift - 1));
+
+	if(orig_shift != 0)
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+	if(shift != 0)
+	{
+		*r_dst = res;
+		FLAG_X = (new_x_flag != 0)<<8;
+	}
+	else
+		res = src;
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+	FLAG_C = FLAG_X = res;
+	res = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src   = *r_dst;
+	uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+	res = ROL_33_64(res, shift);
+
+	FLAG_C = FLAG_X = res >> 24;
+	res = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+	uint new_x_flag = src & (1 << (32 - shift));
+
+	*r_dst = res;
+
+	FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 9;
+		uint src   = MASK_OUT_ABOVE_8(*r_dst);
+		uint res   = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res;
+		res = MASK_OUT_ABOVE_8(res);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 17;
+		uint src   = MASK_OUT_ABOVE_16(*r_dst);
+		uint res   = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 8;
+		res = MASK_OUT_ABOVE_16(res);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint   shift = orig_shift % 33;
+		uint64 src   = *r_dst;
+		uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+		res = ROL_33_64(res, shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 24;
+		res = MASK_OUT_ABOVE_32(res);
+
+		*r_dst = res;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift % 33;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+	uint new_x_flag = src & (1 << (32 - shift));
+
+	if(orig_shift != 0)
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+	if(shift != 0)
+	{
+		*r_dst = res;
+		FLAG_X = (new_x_flag != 0)<<8;
+	}
+	else
+		res = src;
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rtd_32(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		uint new_pc = m68ki_pull_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+		m68ki_jump(new_pc);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_rte_32(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr;
+		uint new_pc;
+		uint format_word;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+
+		if(CPU_TYPE_IS_000(CPU_TYPE))
+		{
+			new_sr = m68ki_pull_16();
+			new_pc = m68ki_pull_32();
+			m68ki_jump(new_pc);
+			m68ki_set_sr(new_sr);
+			return;
+		}
+
+		if(CPU_TYPE_IS_010(CPU_TYPE))
+		{
+			format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+			if(format_word == 0)
+			{
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				return;
+			}
+			/* Not handling bus fault (9) */
+			m68ki_exception_format_error();
+			return;
+		}
+
+		/* Otherwise it's 020 */
+rte_loop:
+		format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+		switch(format_word)
+		{
+			case 0: /* Normal */
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				return;
+			case 1: /* Throwaway */
+				new_sr = m68ki_pull_16();
+				m68ki_fake_pull_32();	/* program counter */
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_set_sr_noint(new_sr);
+				goto rte_loop;
+			case 2: /* Trap */
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_fake_pull_32();	/* address */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				return;
+		}
+		/* Not handling long or short bus fault */
+		m68ki_exception_format_error();
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_rtm_32(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_rtr_32(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_set_ccr(m68ki_pull_16());
+	m68ki_jump(m68ki_pull_32());
+}
+
+
+void m68k_op_rts_32(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_jump(m68ki_pull_32());
+}
+
+
+void m68k_op_sbcd_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_sbcd_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_N = NFLAG_8(res); /* officially undefined */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_st_8_d(void)
+{
+	DY |= 0xff;
+}
+
+
+void m68k_op_st_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0xff);
+}
+
+
+void m68k_op_st_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0xff);
+}
+
+
+void m68k_op_st_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0xff);
+}
+
+
+void m68k_op_st_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0xff);
+}
+
+
+void m68k_op_sf_8_d(void)
+{
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sf_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0);
+}
+
+
+void m68k_op_sf_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0);
+}
+
+
+void m68k_op_sf_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0);
+}
+
+
+void m68k_op_sf_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0);
+}
+
+
+void m68k_op_sf_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0);
+}
+
+
+void m68k_op_sf_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0);
+}
+
+
+void m68k_op_shi_8_d(void)
+{
+	if(COND_HI())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sls_8_d(void)
+{
+	if(COND_LS())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_scc_8_d(void)
+{
+	if(COND_CC())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_scs_8_d(void)
+{
+	if(COND_CS())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sne_8_d(void)
+{
+	if(COND_NE())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_seq_8_d(void)
+{
+	if(COND_EQ())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_svc_8_d(void)
+{
+	if(COND_VC())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_svs_8_d(void)
+{
+	if(COND_VS())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_spl_8_d(void)
+{
+	if(COND_PL())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_smi_8_d(void)
+{
+	if(COND_MI())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sge_8_d(void)
+{
+	if(COND_GE())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_slt_8_d(void)
+{
+	if(COND_LT())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sgt_8_d(void)
+{
+	if(COND_GT())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sle_8_d(void)
+{
+	if(COND_LE())
+	{
+		DY |= 0xff;
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_shi_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_stop(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		CPU_STOPPED |= STOP_LEVEL_STOP;
+		m68ki_set_sr(new_sr);
+		m68ki_remaining_cycles = 0;
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_sub_8_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pi7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pd7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = AY;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_suba_16_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
+}
+
+
+void m68k_op_suba_16_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
+}
+
+
+void m68k_op_suba_16_ai(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_AI_16()));
+}
+
+
+void m68k_op_suba_16_pi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PI_16()));
+}
+
+
+void m68k_op_suba_16_pd(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PD_16()));
+}
+
+
+void m68k_op_suba_16_di(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_DI_16()));
+}
+
+
+void m68k_op_suba_16_ix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_IX_16()));
+}
+
+
+void m68k_op_suba_16_aw(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AW_16()));
+}
+
+
+void m68k_op_suba_16_al(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AL_16()));
+}
+
+
+void m68k_op_suba_16_pcdi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCDI_16()));
+}
+
+
+void m68k_op_suba_16_pcix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCIX_16()));
+}
+
+
+void m68k_op_suba_16_i(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_suba_32_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
+}
+
+
+void m68k_op_suba_32_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
+}
+
+
+void m68k_op_suba_32_ai(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_AI_32());
+}
+
+
+void m68k_op_suba_32_pi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PI_32());
+}
+
+
+void m68k_op_suba_32_pd(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PD_32());
+}
+
+
+void m68k_op_suba_32_di(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_DI_32());
+}
+
+
+void m68k_op_suba_32_ix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_IX_32());
+}
+
+
+void m68k_op_suba_32_aw(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AW_32());
+}
+
+
+void m68k_op_suba_32_al(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AL_32());
+}
+
+
+void m68k_op_suba_32_pcdi(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCDI_32());
+}
+
+
+void m68k_op_suba_32_pcix(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCIX_32());
+}
+
+
+void m68k_op_suba_32_i(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_I_32());
+}
+
+
+void m68k_op_subi_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_subi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subq_8_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pi7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pd7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subq_16_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+void m68k_op_subq_16_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_subq_32_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+void m68k_op_subq_32_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subx_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_subx_16_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_subx_32_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_subx_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_16_mm(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint ea  = EA_AX_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_subx_32_mm(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint ea  = EA_AX_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_swap_32(void)
+{
+	uint* r_dst = &DY;
+
+	FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
+	*r_dst = (*r_dst>>16) | FLAG_Z;
+
+	FLAG_Z = *r_dst;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_tas_8_d(void)
+{
+	uint* r_dst = &DY;
+
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	*r_dst |= 0x80;
+}
+
+
+void m68k_op_tas_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_tas_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+#if GENESIS_HACKS
+    /* Write-back prevented in this system */
+#else
+    m68ki_write_8(ea, dst | 0x80);
+#endif
+}
+
+
+void m68k_op_trap(void)
+{
+	/* Trap#n stacks exception frame type 0 */
+	m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf));	/* HJB 990403 */
+}
+
+
+void m68k_op_trapt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapv(void)
+{
+	if(COND_VC())
+	{
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_TRAPV);  /* HJB 990403 */
+}
+
+
+void m68k_op_tst_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_8_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_a(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = MAKE_INT_16(AY);
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_di(void)
+{
+	uint res = OPER_AY_DI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_aw(void)
+{
+	uint res = OPER_AW_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_al(void)
+{
+	uint res = OPER_AL_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_d(void)
+{
+	uint res = DY;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_a(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = AY;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_di(void)
+{
+	uint res = OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_aw(void)
+{
+	uint res = OPER_AW_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_al(void)
+{
+	uint res = OPER_AL_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unlk_32_a7(void)
+{
+	REG_A[7] = m68ki_read_32(REG_A[7]);
+}
+
+
+void m68k_op_unlk_32(void)
+{
+	uint* r_dst = &AY;
+
+	REG_A[7] = *r_dst;
+	*r_dst = m68ki_pull_32();
+}
+
+
+void m68k_op_unpk_16_rr(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: DX and DY are reversed in Motorola's docs */
+		uint src = DY;
+		uint* r_dst = &DX;
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_ax7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_AY_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_ay7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_A7_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_axy7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_A7_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_AY_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/m68kops.c b/MCUME_pico2/picogenold/m68kops.c
new file mode 100644
index 0000000..b502493
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kops.c
@@ -0,0 +1,4099 @@
+const unsigned char m68ki_cycles[1][0x10000]={
+  {
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, 
+    28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+    30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+    34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    14, 14, 14, 14, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, 
+    28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+    30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+    34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, 
+    28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+    30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+    34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, 
+    28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+    30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+    34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 16, 18, 0, 0, 0, 0, 
+    12, 12, 12, 12, 12, 12, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    14, 14, 14, 14, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    12, 12, 12, 12, 12, 12, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+    12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+    18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+    22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+    16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, 
+    28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+    30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+    34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+    8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+    10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+    14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+    8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
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+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,   },
+};
diff --git a/MCUME_pico2/picogenold/m68kops.h b/MCUME_pico2/picogenold/m68kops.h
new file mode 100644
index 0000000..4ce5cda
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kops.h
@@ -0,0 +1,1984 @@
+#ifndef M68KOPS__HEADER
+#define M68KOPS__HEADER
+
+/* ======================================================================== */
+/* ============================ OPCODE HANDLERS =========================== */
+/* ======================================================================== */
+
+
+void m68k_op_1010(void);
+void m68k_op_1111(void);
+void m68k_op_abcd_8_rr(void);
+void m68k_op_abcd_8_mm_ax7(void);
+void m68k_op_abcd_8_mm_ay7(void);
+void m68k_op_abcd_8_mm_axy7(void);
+void m68k_op_abcd_8_mm(void);
+void m68k_op_add_8_er_d(void);
+void m68k_op_add_8_er_ai(void);
+void m68k_op_add_8_er_pi(void);
+void m68k_op_add_8_er_pi7(void);
+void m68k_op_add_8_er_pd(void);
+void m68k_op_add_8_er_pd7(void);
+void m68k_op_add_8_er_di(void);
+void m68k_op_add_8_er_ix(void);
+void m68k_op_add_8_er_aw(void);
+void m68k_op_add_8_er_al(void);
+void m68k_op_add_8_er_pcdi(void);
+void m68k_op_add_8_er_pcix(void);
+void m68k_op_add_8_er_i(void);
+void m68k_op_add_16_er_d(void);
+void m68k_op_add_16_er_a(void);
+void m68k_op_add_16_er_ai(void);
+void m68k_op_add_16_er_pi(void);
+void m68k_op_add_16_er_pd(void);
+void m68k_op_add_16_er_di(void);
+void m68k_op_add_16_er_ix(void);
+void m68k_op_add_16_er_aw(void);
+void m68k_op_add_16_er_al(void);
+void m68k_op_add_16_er_pcdi(void);
+void m68k_op_add_16_er_pcix(void);
+void m68k_op_add_16_er_i(void);
+void m68k_op_add_32_er_d(void);
+void m68k_op_add_32_er_a(void);
+void m68k_op_add_32_er_ai(void);
+void m68k_op_add_32_er_pi(void);
+void m68k_op_add_32_er_pd(void);
+void m68k_op_add_32_er_di(void);
+void m68k_op_add_32_er_ix(void);
+void m68k_op_add_32_er_aw(void);
+void m68k_op_add_32_er_al(void);
+void m68k_op_add_32_er_pcdi(void);
+void m68k_op_add_32_er_pcix(void);
+void m68k_op_add_32_er_i(void);
+void m68k_op_add_8_re_ai(void);
+void m68k_op_add_8_re_pi(void);
+void m68k_op_add_8_re_pi7(void);
+void m68k_op_add_8_re_pd(void);
+void m68k_op_add_8_re_pd7(void);
+void m68k_op_add_8_re_di(void);
+void m68k_op_add_8_re_ix(void);
+void m68k_op_add_8_re_aw(void);
+void m68k_op_add_8_re_al(void);
+void m68k_op_add_16_re_ai(void);
+void m68k_op_add_16_re_pi(void);
+void m68k_op_add_16_re_pd(void);
+void m68k_op_add_16_re_di(void);
+void m68k_op_add_16_re_ix(void);
+void m68k_op_add_16_re_aw(void);
+void m68k_op_add_16_re_al(void);
+void m68k_op_add_32_re_ai(void);
+void m68k_op_add_32_re_pi(void);
+void m68k_op_add_32_re_pd(void);
+void m68k_op_add_32_re_di(void);
+void m68k_op_add_32_re_ix(void);
+void m68k_op_add_32_re_aw(void);
+void m68k_op_add_32_re_al(void);
+void m68k_op_adda_16_d(void);
+void m68k_op_adda_16_a(void);
+void m68k_op_adda_16_ai(void);
+void m68k_op_adda_16_pi(void);
+void m68k_op_adda_16_pd(void);
+void m68k_op_adda_16_di(void);
+void m68k_op_adda_16_ix(void);
+void m68k_op_adda_16_aw(void);
+void m68k_op_adda_16_al(void);
+void m68k_op_adda_16_pcdi(void);
+void m68k_op_adda_16_pcix(void);
+void m68k_op_adda_16_i(void);
+void m68k_op_adda_32_d(void);
+void m68k_op_adda_32_a(void);
+void m68k_op_adda_32_ai(void);
+void m68k_op_adda_32_pi(void);
+void m68k_op_adda_32_pd(void);
+void m68k_op_adda_32_di(void);
+void m68k_op_adda_32_ix(void);
+void m68k_op_adda_32_aw(void);
+void m68k_op_adda_32_al(void);
+void m68k_op_adda_32_pcdi(void);
+void m68k_op_adda_32_pcix(void);
+void m68k_op_adda_32_i(void);
+void m68k_op_addi_8_d(void);
+void m68k_op_addi_8_ai(void);
+void m68k_op_addi_8_pi(void);
+void m68k_op_addi_8_pi7(void);
+void m68k_op_addi_8_pd(void);
+void m68k_op_addi_8_pd7(void);
+void m68k_op_addi_8_di(void);
+void m68k_op_addi_8_ix(void);
+void m68k_op_addi_8_aw(void);
+void m68k_op_addi_8_al(void);
+void m68k_op_addi_16_d(void);
+void m68k_op_addi_16_ai(void);
+void m68k_op_addi_16_pi(void);
+void m68k_op_addi_16_pd(void);
+void m68k_op_addi_16_di(void);
+void m68k_op_addi_16_ix(void);
+void m68k_op_addi_16_aw(void);
+void m68k_op_addi_16_al(void);
+void m68k_op_addi_32_d(void);
+void m68k_op_addi_32_ai(void);
+void m68k_op_addi_32_pi(void);
+void m68k_op_addi_32_pd(void);
+void m68k_op_addi_32_di(void);
+void m68k_op_addi_32_ix(void);
+void m68k_op_addi_32_aw(void);
+void m68k_op_addi_32_al(void);
+void m68k_op_addq_8_d(void);
+void m68k_op_addq_8_ai(void);
+void m68k_op_addq_8_pi(void);
+void m68k_op_addq_8_pi7(void);
+void m68k_op_addq_8_pd(void);
+void m68k_op_addq_8_pd7(void);
+void m68k_op_addq_8_di(void);
+void m68k_op_addq_8_ix(void);
+void m68k_op_addq_8_aw(void);
+void m68k_op_addq_8_al(void);
+void m68k_op_addq_16_d(void);
+void m68k_op_addq_16_a(void);
+void m68k_op_addq_16_ai(void);
+void m68k_op_addq_16_pi(void);
+void m68k_op_addq_16_pd(void);
+void m68k_op_addq_16_di(void);
+void m68k_op_addq_16_ix(void);
+void m68k_op_addq_16_aw(void);
+void m68k_op_addq_16_al(void);
+void m68k_op_addq_32_d(void);
+void m68k_op_addq_32_a(void);
+void m68k_op_addq_32_ai(void);
+void m68k_op_addq_32_pi(void);
+void m68k_op_addq_32_pd(void);
+void m68k_op_addq_32_di(void);
+void m68k_op_addq_32_ix(void);
+void m68k_op_addq_32_aw(void);
+void m68k_op_addq_32_al(void);
+void m68k_op_addx_8_rr(void);
+void m68k_op_addx_16_rr(void);
+void m68k_op_addx_32_rr(void);
+void m68k_op_addx_8_mm_ax7(void);
+void m68k_op_addx_8_mm_ay7(void);
+void m68k_op_addx_8_mm_axy7(void);
+void m68k_op_addx_8_mm(void);
+void m68k_op_addx_16_mm(void);
+void m68k_op_addx_32_mm(void);
+void m68k_op_and_8_er_d(void);
+void m68k_op_and_8_er_ai(void);
+void m68k_op_and_8_er_pi(void);
+void m68k_op_and_8_er_pi7(void);
+void m68k_op_and_8_er_pd(void);
+void m68k_op_and_8_er_pd7(void);
+void m68k_op_and_8_er_di(void);
+void m68k_op_and_8_er_ix(void);
+void m68k_op_and_8_er_aw(void);
+void m68k_op_and_8_er_al(void);
+void m68k_op_and_8_er_pcdi(void);
+void m68k_op_and_8_er_pcix(void);
+void m68k_op_and_8_er_i(void);
+void m68k_op_and_16_er_d(void);
+void m68k_op_and_16_er_ai(void);
+void m68k_op_and_16_er_pi(void);
+void m68k_op_and_16_er_pd(void);
+void m68k_op_and_16_er_di(void);
+void m68k_op_and_16_er_ix(void);
+void m68k_op_and_16_er_aw(void);
+void m68k_op_and_16_er_al(void);
+void m68k_op_and_16_er_pcdi(void);
+void m68k_op_and_16_er_pcix(void);
+void m68k_op_and_16_er_i(void);
+void m68k_op_and_32_er_d(void);
+void m68k_op_and_32_er_ai(void);
+void m68k_op_and_32_er_pi(void);
+void m68k_op_and_32_er_pd(void);
+void m68k_op_and_32_er_di(void);
+void m68k_op_and_32_er_ix(void);
+void m68k_op_and_32_er_aw(void);
+void m68k_op_and_32_er_al(void);
+void m68k_op_and_32_er_pcdi(void);
+void m68k_op_and_32_er_pcix(void);
+void m68k_op_and_32_er_i(void);
+void m68k_op_and_8_re_ai(void);
+void m68k_op_and_8_re_pi(void);
+void m68k_op_and_8_re_pi7(void);
+void m68k_op_and_8_re_pd(void);
+void m68k_op_and_8_re_pd7(void);
+void m68k_op_and_8_re_di(void);
+void m68k_op_and_8_re_ix(void);
+void m68k_op_and_8_re_aw(void);
+void m68k_op_and_8_re_al(void);
+void m68k_op_and_16_re_ai(void);
+void m68k_op_and_16_re_pi(void);
+void m68k_op_and_16_re_pd(void);
+void m68k_op_and_16_re_di(void);
+void m68k_op_and_16_re_ix(void);
+void m68k_op_and_16_re_aw(void);
+void m68k_op_and_16_re_al(void);
+void m68k_op_and_32_re_ai(void);
+void m68k_op_and_32_re_pi(void);
+void m68k_op_and_32_re_pd(void);
+void m68k_op_and_32_re_di(void);
+void m68k_op_and_32_re_ix(void);
+void m68k_op_and_32_re_aw(void);
+void m68k_op_and_32_re_al(void);
+void m68k_op_andi_8_d(void);
+void m68k_op_andi_8_ai(void);
+void m68k_op_andi_8_pi(void);
+void m68k_op_andi_8_pi7(void);
+void m68k_op_andi_8_pd(void);
+void m68k_op_andi_8_pd7(void);
+void m68k_op_andi_8_di(void);
+void m68k_op_andi_8_ix(void);
+void m68k_op_andi_8_aw(void);
+void m68k_op_andi_8_al(void);
+void m68k_op_andi_16_d(void);
+void m68k_op_andi_16_ai(void);
+void m68k_op_andi_16_pi(void);
+void m68k_op_andi_16_pd(void);
+void m68k_op_andi_16_di(void);
+void m68k_op_andi_16_ix(void);
+void m68k_op_andi_16_aw(void);
+void m68k_op_andi_16_al(void);
+void m68k_op_andi_32_d(void);
+void m68k_op_andi_32_ai(void);
+void m68k_op_andi_32_pi(void);
+void m68k_op_andi_32_pd(void);
+void m68k_op_andi_32_di(void);
+void m68k_op_andi_32_ix(void);
+void m68k_op_andi_32_aw(void);
+void m68k_op_andi_32_al(void);
+void m68k_op_andi_16_toc(void);
+void m68k_op_andi_16_tos(void);
+void m68k_op_asr_8_s(void);
+void m68k_op_asr_16_s(void);
+void m68k_op_asr_32_s(void);
+void m68k_op_asr_8_r(void);
+void m68k_op_asr_16_r(void);
+void m68k_op_asr_32_r(void);
+void m68k_op_asr_16_ai(void);
+void m68k_op_asr_16_pi(void);
+void m68k_op_asr_16_pd(void);
+void m68k_op_asr_16_di(void);
+void m68k_op_asr_16_ix(void);
+void m68k_op_asr_16_aw(void);
+void m68k_op_asr_16_al(void);
+void m68k_op_asl_8_s(void);
+void m68k_op_asl_16_s(void);
+void m68k_op_asl_32_s(void);
+void m68k_op_asl_8_r(void);
+void m68k_op_asl_16_r(void);
+void m68k_op_asl_32_r(void);
+void m68k_op_asl_16_ai(void);
+void m68k_op_asl_16_pi(void);
+void m68k_op_asl_16_pd(void);
+void m68k_op_asl_16_di(void);
+void m68k_op_asl_16_ix(void);
+void m68k_op_asl_16_aw(void);
+void m68k_op_asl_16_al(void);
+void m68k_op_bhi_8(void);
+void m68k_op_bls_8(void);
+void m68k_op_bcc_8(void);
+void m68k_op_bcs_8(void);
+void m68k_op_bne_8(void);
+void m68k_op_beq_8(void);
+void m68k_op_bvc_8(void);
+void m68k_op_bvs_8(void);
+void m68k_op_bpl_8(void);
+void m68k_op_bmi_8(void);
+void m68k_op_bge_8(void);
+void m68k_op_blt_8(void);
+void m68k_op_bgt_8(void);
+void m68k_op_ble_8(void);
+void m68k_op_bhi_16(void);
+void m68k_op_bls_16(void);
+void m68k_op_bcc_16(void);
+void m68k_op_bcs_16(void);
+void m68k_op_bne_16(void);
+void m68k_op_beq_16(void);
+void m68k_op_bvc_16(void);
+void m68k_op_bvs_16(void);
+void m68k_op_bpl_16(void);
+void m68k_op_bmi_16(void);
+void m68k_op_bge_16(void);
+void m68k_op_blt_16(void);
+void m68k_op_bgt_16(void);
+void m68k_op_ble_16(void);
+void m68k_op_bhi_32(void);
+void m68k_op_bls_32(void);
+void m68k_op_bcc_32(void);
+void m68k_op_bcs_32(void);
+void m68k_op_bne_32(void);
+void m68k_op_beq_32(void);
+void m68k_op_bvc_32(void);
+void m68k_op_bvs_32(void);
+void m68k_op_bpl_32(void);
+void m68k_op_bmi_32(void);
+void m68k_op_bge_32(void);
+void m68k_op_blt_32(void);
+void m68k_op_bgt_32(void);
+void m68k_op_ble_32(void);
+void m68k_op_bchg_32_r_d(void);
+void m68k_op_bchg_8_r_ai(void);
+void m68k_op_bchg_8_r_pi(void);
+void m68k_op_bchg_8_r_pi7(void);
+void m68k_op_bchg_8_r_pd(void);
+void m68k_op_bchg_8_r_pd7(void);
+void m68k_op_bchg_8_r_di(void);
+void m68k_op_bchg_8_r_ix(void);
+void m68k_op_bchg_8_r_aw(void);
+void m68k_op_bchg_8_r_al(void);
+void m68k_op_bchg_32_s_d(void);
+void m68k_op_bchg_8_s_ai(void);
+void m68k_op_bchg_8_s_pi(void);
+void m68k_op_bchg_8_s_pi7(void);
+void m68k_op_bchg_8_s_pd(void);
+void m68k_op_bchg_8_s_pd7(void);
+void m68k_op_bchg_8_s_di(void);
+void m68k_op_bchg_8_s_ix(void);
+void m68k_op_bchg_8_s_aw(void);
+void m68k_op_bchg_8_s_al(void);
+void m68k_op_bclr_32_r_d(void);
+void m68k_op_bclr_8_r_ai(void);
+void m68k_op_bclr_8_r_pi(void);
+void m68k_op_bclr_8_r_pi7(void);
+void m68k_op_bclr_8_r_pd(void);
+void m68k_op_bclr_8_r_pd7(void);
+void m68k_op_bclr_8_r_di(void);
+void m68k_op_bclr_8_r_ix(void);
+void m68k_op_bclr_8_r_aw(void);
+void m68k_op_bclr_8_r_al(void);
+void m68k_op_bclr_32_s_d(void);
+void m68k_op_bclr_8_s_ai(void);
+void m68k_op_bclr_8_s_pi(void);
+void m68k_op_bclr_8_s_pi7(void);
+void m68k_op_bclr_8_s_pd(void);
+void m68k_op_bclr_8_s_pd7(void);
+void m68k_op_bclr_8_s_di(void);
+void m68k_op_bclr_8_s_ix(void);
+void m68k_op_bclr_8_s_aw(void);
+void m68k_op_bclr_8_s_al(void);
+void m68k_op_bfchg_32_d(void);
+void m68k_op_bfchg_32_ai(void);
+void m68k_op_bfchg_32_di(void);
+void m68k_op_bfchg_32_ix(void);
+void m68k_op_bfchg_32_aw(void);
+void m68k_op_bfchg_32_al(void);
+void m68k_op_bfclr_32_d(void);
+void m68k_op_bfclr_32_ai(void);
+void m68k_op_bfclr_32_di(void);
+void m68k_op_bfclr_32_ix(void);
+void m68k_op_bfclr_32_aw(void);
+void m68k_op_bfclr_32_al(void);
+void m68k_op_bfexts_32_d(void);
+void m68k_op_bfexts_32_ai(void);
+void m68k_op_bfexts_32_di(void);
+void m68k_op_bfexts_32_ix(void);
+void m68k_op_bfexts_32_aw(void);
+void m68k_op_bfexts_32_al(void);
+void m68k_op_bfexts_32_pcdi(void);
+void m68k_op_bfexts_32_pcix(void);
+void m68k_op_bfextu_32_d(void);
+void m68k_op_bfextu_32_ai(void);
+void m68k_op_bfextu_32_di(void);
+void m68k_op_bfextu_32_ix(void);
+void m68k_op_bfextu_32_aw(void);
+void m68k_op_bfextu_32_al(void);
+void m68k_op_bfextu_32_pcdi(void);
+void m68k_op_bfextu_32_pcix(void);
+void m68k_op_bfffo_32_d(void);
+void m68k_op_bfffo_32_ai(void);
+void m68k_op_bfffo_32_di(void);
+void m68k_op_bfffo_32_ix(void);
+void m68k_op_bfffo_32_aw(void);
+void m68k_op_bfffo_32_al(void);
+void m68k_op_bfffo_32_pcdi(void);
+void m68k_op_bfffo_32_pcix(void);
+void m68k_op_bfins_32_d(void);
+void m68k_op_bfins_32_ai(void);
+void m68k_op_bfins_32_di(void);
+void m68k_op_bfins_32_ix(void);
+void m68k_op_bfins_32_aw(void);
+void m68k_op_bfins_32_al(void);
+void m68k_op_bfset_32_d(void);
+void m68k_op_bfset_32_ai(void);
+void m68k_op_bfset_32_di(void);
+void m68k_op_bfset_32_ix(void);
+void m68k_op_bfset_32_aw(void);
+void m68k_op_bfset_32_al(void);
+void m68k_op_bftst_32_d(void);
+void m68k_op_bftst_32_ai(void);
+void m68k_op_bftst_32_di(void);
+void m68k_op_bftst_32_ix(void);
+void m68k_op_bftst_32_aw(void);
+void m68k_op_bftst_32_al(void);
+void m68k_op_bftst_32_pcdi(void);
+void m68k_op_bftst_32_pcix(void);
+void m68k_op_bkpt(void);
+void m68k_op_bra_8(void);
+void m68k_op_bra_16(void);
+void m68k_op_bra_32(void);
+void m68k_op_bset_32_r_d(void);
+void m68k_op_bset_8_r_ai(void);
+void m68k_op_bset_8_r_pi(void);
+void m68k_op_bset_8_r_pi7(void);
+void m68k_op_bset_8_r_pd(void);
+void m68k_op_bset_8_r_pd7(void);
+void m68k_op_bset_8_r_di(void);
+void m68k_op_bset_8_r_ix(void);
+void m68k_op_bset_8_r_aw(void);
+void m68k_op_bset_8_r_al(void);
+void m68k_op_bset_32_s_d(void);
+void m68k_op_bset_8_s_ai(void);
+void m68k_op_bset_8_s_pi(void);
+void m68k_op_bset_8_s_pi7(void);
+void m68k_op_bset_8_s_pd(void);
+void m68k_op_bset_8_s_pd7(void);
+void m68k_op_bset_8_s_di(void);
+void m68k_op_bset_8_s_ix(void);
+void m68k_op_bset_8_s_aw(void);
+void m68k_op_bset_8_s_al(void);
+void m68k_op_bsr_8(void);
+void m68k_op_bsr_16(void);
+void m68k_op_bsr_32(void);
+void m68k_op_btst_32_r_d(void);
+void m68k_op_btst_8_r_ai(void);
+void m68k_op_btst_8_r_pi(void);
+void m68k_op_btst_8_r_pi7(void);
+void m68k_op_btst_8_r_pd(void);
+void m68k_op_btst_8_r_pd7(void);
+void m68k_op_btst_8_r_di(void);
+void m68k_op_btst_8_r_ix(void);
+void m68k_op_btst_8_r_aw(void);
+void m68k_op_btst_8_r_al(void);
+void m68k_op_btst_8_r_pcdi(void);
+void m68k_op_btst_8_r_pcix(void);
+void m68k_op_btst_8_r_i(void);
+void m68k_op_btst_32_s_d(void);
+void m68k_op_btst_8_s_ai(void);
+void m68k_op_btst_8_s_pi(void);
+void m68k_op_btst_8_s_pi7(void);
+void m68k_op_btst_8_s_pd(void);
+void m68k_op_btst_8_s_pd7(void);
+void m68k_op_btst_8_s_di(void);
+void m68k_op_btst_8_s_ix(void);
+void m68k_op_btst_8_s_aw(void);
+void m68k_op_btst_8_s_al(void);
+void m68k_op_btst_8_s_pcdi(void);
+void m68k_op_btst_8_s_pcix(void);
+void m68k_op_callm_32_ai(void);
+void m68k_op_callm_32_di(void);
+void m68k_op_callm_32_ix(void);
+void m68k_op_callm_32_aw(void);
+void m68k_op_callm_32_al(void);
+void m68k_op_callm_32_pcdi(void);
+void m68k_op_callm_32_pcix(void);
+void m68k_op_cas_8_ai(void);
+void m68k_op_cas_8_pi(void);
+void m68k_op_cas_8_pi7(void);
+void m68k_op_cas_8_pd(void);
+void m68k_op_cas_8_pd7(void);
+void m68k_op_cas_8_di(void);
+void m68k_op_cas_8_ix(void);
+void m68k_op_cas_8_aw(void);
+void m68k_op_cas_8_al(void);
+void m68k_op_cas_16_ai(void);
+void m68k_op_cas_16_pi(void);
+void m68k_op_cas_16_pd(void);
+void m68k_op_cas_16_di(void);
+void m68k_op_cas_16_ix(void);
+void m68k_op_cas_16_aw(void);
+void m68k_op_cas_16_al(void);
+void m68k_op_cas_32_ai(void);
+void m68k_op_cas_32_pi(void);
+void m68k_op_cas_32_pd(void);
+void m68k_op_cas_32_di(void);
+void m68k_op_cas_32_ix(void);
+void m68k_op_cas_32_aw(void);
+void m68k_op_cas_32_al(void);
+void m68k_op_cas2_16(void);
+void m68k_op_cas2_32(void);
+void m68k_op_chk_16_d(void);
+void m68k_op_chk_16_ai(void);
+void m68k_op_chk_16_pi(void);
+void m68k_op_chk_16_pd(void);
+void m68k_op_chk_16_di(void);
+void m68k_op_chk_16_ix(void);
+void m68k_op_chk_16_aw(void);
+void m68k_op_chk_16_al(void);
+void m68k_op_chk_16_pcdi(void);
+void m68k_op_chk_16_pcix(void);
+void m68k_op_chk_16_i(void);
+void m68k_op_chk_32_d(void);
+void m68k_op_chk_32_ai(void);
+void m68k_op_chk_32_pi(void);
+void m68k_op_chk_32_pd(void);
+void m68k_op_chk_32_di(void);
+void m68k_op_chk_32_ix(void);
+void m68k_op_chk_32_aw(void);
+void m68k_op_chk_32_al(void);
+void m68k_op_chk_32_pcdi(void);
+void m68k_op_chk_32_pcix(void);
+void m68k_op_chk_32_i(void);
+void m68k_op_chk2cmp2_8_ai(void);
+void m68k_op_chk2cmp2_8_di(void);
+void m68k_op_chk2cmp2_8_ix(void);
+void m68k_op_chk2cmp2_8_aw(void);
+void m68k_op_chk2cmp2_8_al(void);
+void m68k_op_chk2cmp2_8_pcdi(void);
+void m68k_op_chk2cmp2_8_pcix(void);
+void m68k_op_chk2cmp2_16_ai(void);
+void m68k_op_chk2cmp2_16_di(void);
+void m68k_op_chk2cmp2_16_ix(void);
+void m68k_op_chk2cmp2_16_aw(void);
+void m68k_op_chk2cmp2_16_al(void);
+void m68k_op_chk2cmp2_16_pcdi(void);
+void m68k_op_chk2cmp2_16_pcix(void);
+void m68k_op_chk2cmp2_32_ai(void);
+void m68k_op_chk2cmp2_32_di(void);
+void m68k_op_chk2cmp2_32_ix(void);
+void m68k_op_chk2cmp2_32_aw(void);
+void m68k_op_chk2cmp2_32_al(void);
+void m68k_op_chk2cmp2_32_pcdi(void);
+void m68k_op_chk2cmp2_32_pcix(void);
+void m68k_op_clr_8_d(void);
+void m68k_op_clr_8_ai(void);
+void m68k_op_clr_8_pi(void);
+void m68k_op_clr_8_pi7(void);
+void m68k_op_clr_8_pd(void);
+void m68k_op_clr_8_pd7(void);
+void m68k_op_clr_8_di(void);
+void m68k_op_clr_8_ix(void);
+void m68k_op_clr_8_aw(void);
+void m68k_op_clr_8_al(void);
+void m68k_op_clr_16_d(void);
+void m68k_op_clr_16_ai(void);
+void m68k_op_clr_16_pi(void);
+void m68k_op_clr_16_pd(void);
+void m68k_op_clr_16_di(void);
+void m68k_op_clr_16_ix(void);
+void m68k_op_clr_16_aw(void);
+void m68k_op_clr_16_al(void);
+void m68k_op_clr_32_d(void);
+void m68k_op_clr_32_ai(void);
+void m68k_op_clr_32_pi(void);
+void m68k_op_clr_32_pd(void);
+void m68k_op_clr_32_di(void);
+void m68k_op_clr_32_ix(void);
+void m68k_op_clr_32_aw(void);
+void m68k_op_clr_32_al(void);
+void m68k_op_cmp_8_d(void);
+void m68k_op_cmp_8_ai(void);
+void m68k_op_cmp_8_pi(void);
+void m68k_op_cmp_8_pi7(void);
+void m68k_op_cmp_8_pd(void);
+void m68k_op_cmp_8_pd7(void);
+void m68k_op_cmp_8_di(void);
+void m68k_op_cmp_8_ix(void);
+void m68k_op_cmp_8_aw(void);
+void m68k_op_cmp_8_al(void);
+void m68k_op_cmp_8_pcdi(void);
+void m68k_op_cmp_8_pcix(void);
+void m68k_op_cmp_8_i(void);
+void m68k_op_cmp_16_d(void);
+void m68k_op_cmp_16_a(void);
+void m68k_op_cmp_16_ai(void);
+void m68k_op_cmp_16_pi(void);
+void m68k_op_cmp_16_pd(void);
+void m68k_op_cmp_16_di(void);
+void m68k_op_cmp_16_ix(void);
+void m68k_op_cmp_16_aw(void);
+void m68k_op_cmp_16_al(void);
+void m68k_op_cmp_16_pcdi(void);
+void m68k_op_cmp_16_pcix(void);
+void m68k_op_cmp_16_i(void);
+void m68k_op_cmp_32_d(void);
+void m68k_op_cmp_32_a(void);
+void m68k_op_cmp_32_ai(void);
+void m68k_op_cmp_32_pi(void);
+void m68k_op_cmp_32_pd(void);
+void m68k_op_cmp_32_di(void);
+void m68k_op_cmp_32_ix(void);
+void m68k_op_cmp_32_aw(void);
+void m68k_op_cmp_32_al(void);
+void m68k_op_cmp_32_pcdi(void);
+void m68k_op_cmp_32_pcix(void);
+void m68k_op_cmp_32_i(void);
+void m68k_op_cmpa_16_d(void);
+void m68k_op_cmpa_16_a(void);
+void m68k_op_cmpa_16_ai(void);
+void m68k_op_cmpa_16_pi(void);
+void m68k_op_cmpa_16_pd(void);
+void m68k_op_cmpa_16_di(void);
+void m68k_op_cmpa_16_ix(void);
+void m68k_op_cmpa_16_aw(void);
+void m68k_op_cmpa_16_al(void);
+void m68k_op_cmpa_16_pcdi(void);
+void m68k_op_cmpa_16_pcix(void);
+void m68k_op_cmpa_16_i(void);
+void m68k_op_cmpa_32_d(void);
+void m68k_op_cmpa_32_a(void);
+void m68k_op_cmpa_32_ai(void);
+void m68k_op_cmpa_32_pi(void);
+void m68k_op_cmpa_32_pd(void);
+void m68k_op_cmpa_32_di(void);
+void m68k_op_cmpa_32_ix(void);
+void m68k_op_cmpa_32_aw(void);
+void m68k_op_cmpa_32_al(void);
+void m68k_op_cmpa_32_pcdi(void);
+void m68k_op_cmpa_32_pcix(void);
+void m68k_op_cmpa_32_i(void);
+void m68k_op_cmpi_8_d(void);
+void m68k_op_cmpi_8_ai(void);
+void m68k_op_cmpi_8_pi(void);
+void m68k_op_cmpi_8_pi7(void);
+void m68k_op_cmpi_8_pd(void);
+void m68k_op_cmpi_8_pd7(void);
+void m68k_op_cmpi_8_di(void);
+void m68k_op_cmpi_8_ix(void);
+void m68k_op_cmpi_8_aw(void);
+void m68k_op_cmpi_8_al(void);
+void m68k_op_cmpi_8_pcdi(void);
+void m68k_op_cmpi_8_pcix(void);
+void m68k_op_cmpi_16_d(void);
+void m68k_op_cmpi_16_ai(void);
+void m68k_op_cmpi_16_pi(void);
+void m68k_op_cmpi_16_pd(void);
+void m68k_op_cmpi_16_di(void);
+void m68k_op_cmpi_16_ix(void);
+void m68k_op_cmpi_16_aw(void);
+void m68k_op_cmpi_16_al(void);
+void m68k_op_cmpi_16_pcdi(void);
+void m68k_op_cmpi_16_pcix(void);
+void m68k_op_cmpi_32_d(void);
+void m68k_op_cmpi_32_ai(void);
+void m68k_op_cmpi_32_pi(void);
+void m68k_op_cmpi_32_pd(void);
+void m68k_op_cmpi_32_di(void);
+void m68k_op_cmpi_32_ix(void);
+void m68k_op_cmpi_32_aw(void);
+void m68k_op_cmpi_32_al(void);
+void m68k_op_cmpi_32_pcdi(void);
+void m68k_op_cmpi_32_pcix(void);
+void m68k_op_cmpm_8_ax7(void);
+void m68k_op_cmpm_8_ay7(void);
+void m68k_op_cmpm_8_axy7(void);
+void m68k_op_cmpm_8(void);
+void m68k_op_cmpm_16(void);
+void m68k_op_cmpm_32(void);
+void m68k_op_cpbcc_32(void);
+void m68k_op_cpdbcc_32(void);
+void m68k_op_cpgen_32(void);
+void m68k_op_cpscc_32(void);
+void m68k_op_cptrapcc_32(void);
+void m68k_op_dbt_16(void);
+void m68k_op_dbf_16(void);
+void m68k_op_dbhi_16(void);
+void m68k_op_dbls_16(void);
+void m68k_op_dbcc_16(void);
+void m68k_op_dbcs_16(void);
+void m68k_op_dbne_16(void);
+void m68k_op_dbeq_16(void);
+void m68k_op_dbvc_16(void);
+void m68k_op_dbvs_16(void);
+void m68k_op_dbpl_16(void);
+void m68k_op_dbmi_16(void);
+void m68k_op_dbge_16(void);
+void m68k_op_dblt_16(void);
+void m68k_op_dbgt_16(void);
+void m68k_op_dble_16(void);
+void m68k_op_divs_16_d(void);
+void m68k_op_divs_16_ai(void);
+void m68k_op_divs_16_pi(void);
+void m68k_op_divs_16_pd(void);
+void m68k_op_divs_16_di(void);
+void m68k_op_divs_16_ix(void);
+void m68k_op_divs_16_aw(void);
+void m68k_op_divs_16_al(void);
+void m68k_op_divs_16_pcdi(void);
+void m68k_op_divs_16_pcix(void);
+void m68k_op_divs_16_i(void);
+void m68k_op_divu_16_d(void);
+void m68k_op_divu_16_ai(void);
+void m68k_op_divu_16_pi(void);
+void m68k_op_divu_16_pd(void);
+void m68k_op_divu_16_di(void);
+void m68k_op_divu_16_ix(void);
+void m68k_op_divu_16_aw(void);
+void m68k_op_divu_16_al(void);
+void m68k_op_divu_16_pcdi(void);
+void m68k_op_divu_16_pcix(void);
+void m68k_op_divu_16_i(void);
+void m68k_op_divl_32_d(void);
+void m68k_op_divl_32_ai(void);
+void m68k_op_divl_32_pi(void);
+void m68k_op_divl_32_pd(void);
+void m68k_op_divl_32_di(void);
+void m68k_op_divl_32_ix(void);
+void m68k_op_divl_32_aw(void);
+void m68k_op_divl_32_al(void);
+void m68k_op_divl_32_pcdi(void);
+void m68k_op_divl_32_pcix(void);
+void m68k_op_divl_32_i(void);
+void m68k_op_eor_8_d(void);
+void m68k_op_eor_8_ai(void);
+void m68k_op_eor_8_pi(void);
+void m68k_op_eor_8_pi7(void);
+void m68k_op_eor_8_pd(void);
+void m68k_op_eor_8_pd7(void);
+void m68k_op_eor_8_di(void);
+void m68k_op_eor_8_ix(void);
+void m68k_op_eor_8_aw(void);
+void m68k_op_eor_8_al(void);
+void m68k_op_eor_16_d(void);
+void m68k_op_eor_16_ai(void);
+void m68k_op_eor_16_pi(void);
+void m68k_op_eor_16_pd(void);
+void m68k_op_eor_16_di(void);
+void m68k_op_eor_16_ix(void);
+void m68k_op_eor_16_aw(void);
+void m68k_op_eor_16_al(void);
+void m68k_op_eor_32_d(void);
+void m68k_op_eor_32_ai(void);
+void m68k_op_eor_32_pi(void);
+void m68k_op_eor_32_pd(void);
+void m68k_op_eor_32_di(void);
+void m68k_op_eor_32_ix(void);
+void m68k_op_eor_32_aw(void);
+void m68k_op_eor_32_al(void);
+void m68k_op_eori_8_d(void);
+void m68k_op_eori_8_ai(void);
+void m68k_op_eori_8_pi(void);
+void m68k_op_eori_8_pi7(void);
+void m68k_op_eori_8_pd(void);
+void m68k_op_eori_8_pd7(void);
+void m68k_op_eori_8_di(void);
+void m68k_op_eori_8_ix(void);
+void m68k_op_eori_8_aw(void);
+void m68k_op_eori_8_al(void);
+void m68k_op_eori_16_d(void);
+void m68k_op_eori_16_ai(void);
+void m68k_op_eori_16_pi(void);
+void m68k_op_eori_16_pd(void);
+void m68k_op_eori_16_di(void);
+void m68k_op_eori_16_ix(void);
+void m68k_op_eori_16_aw(void);
+void m68k_op_eori_16_al(void);
+void m68k_op_eori_32_d(void);
+void m68k_op_eori_32_ai(void);
+void m68k_op_eori_32_pi(void);
+void m68k_op_eori_32_pd(void);
+void m68k_op_eori_32_di(void);
+void m68k_op_eori_32_ix(void);
+void m68k_op_eori_32_aw(void);
+void m68k_op_eori_32_al(void);
+void m68k_op_eori_16_toc(void);
+void m68k_op_eori_16_tos(void);
+void m68k_op_exg_32_dd(void);
+void m68k_op_exg_32_aa(void);
+void m68k_op_exg_32_da(void);
+void m68k_op_ext_16(void);
+void m68k_op_ext_32(void);
+void m68k_op_extb_32(void);
+void m68k_op_illegal(void);
+void m68k_op_jmp_32_ai(void);
+void m68k_op_jmp_32_di(void);
+void m68k_op_jmp_32_ix(void);
+void m68k_op_jmp_32_aw(void);
+void m68k_op_jmp_32_al(void);
+void m68k_op_jmp_32_pcdi(void);
+void m68k_op_jmp_32_pcix(void);
+void m68k_op_jsr_32_ai(void);
+void m68k_op_jsr_32_di(void);
+void m68k_op_jsr_32_ix(void);
+void m68k_op_jsr_32_aw(void);
+void m68k_op_jsr_32_al(void);
+void m68k_op_jsr_32_pcdi(void);
+void m68k_op_jsr_32_pcix(void);
+void m68k_op_lea_32_ai(void);
+void m68k_op_lea_32_di(void);
+void m68k_op_lea_32_ix(void);
+void m68k_op_lea_32_aw(void);
+void m68k_op_lea_32_al(void);
+void m68k_op_lea_32_pcdi(void);
+void m68k_op_lea_32_pcix(void);
+void m68k_op_link_16_a7(void);
+void m68k_op_link_16(void);
+void m68k_op_link_32_a7(void);
+void m68k_op_link_32(void);
+void m68k_op_lsr_8_s(void);
+void m68k_op_lsr_16_s(void);
+void m68k_op_lsr_32_s(void);
+void m68k_op_lsr_8_r(void);
+void m68k_op_lsr_16_r(void);
+void m68k_op_lsr_32_r(void);
+void m68k_op_lsr_16_ai(void);
+void m68k_op_lsr_16_pi(void);
+void m68k_op_lsr_16_pd(void);
+void m68k_op_lsr_16_di(void);
+void m68k_op_lsr_16_ix(void);
+void m68k_op_lsr_16_aw(void);
+void m68k_op_lsr_16_al(void);
+void m68k_op_lsl_8_s(void);
+void m68k_op_lsl_16_s(void);
+void m68k_op_lsl_32_s(void);
+void m68k_op_lsl_8_r(void);
+void m68k_op_lsl_16_r(void);
+void m68k_op_lsl_32_r(void);
+void m68k_op_lsl_16_ai(void);
+void m68k_op_lsl_16_pi(void);
+void m68k_op_lsl_16_pd(void);
+void m68k_op_lsl_16_di(void);
+void m68k_op_lsl_16_ix(void);
+void m68k_op_lsl_16_aw(void);
+void m68k_op_lsl_16_al(void);
+void m68k_op_move_8_d_d(void);
+void m68k_op_move_8_d_ai(void);
+void m68k_op_move_8_d_pi(void);
+void m68k_op_move_8_d_pi7(void);
+void m68k_op_move_8_d_pd(void);
+void m68k_op_move_8_d_pd7(void);
+void m68k_op_move_8_d_di(void);
+void m68k_op_move_8_d_ix(void);
+void m68k_op_move_8_d_aw(void);
+void m68k_op_move_8_d_al(void);
+void m68k_op_move_8_d_pcdi(void);
+void m68k_op_move_8_d_pcix(void);
+void m68k_op_move_8_d_i(void);
+void m68k_op_move_8_ai_d(void);
+void m68k_op_move_8_ai_ai(void);
+void m68k_op_move_8_ai_pi(void);
+void m68k_op_move_8_ai_pi7(void);
+void m68k_op_move_8_ai_pd(void);
+void m68k_op_move_8_ai_pd7(void);
+void m68k_op_move_8_ai_di(void);
+void m68k_op_move_8_ai_ix(void);
+void m68k_op_move_8_ai_aw(void);
+void m68k_op_move_8_ai_al(void);
+void m68k_op_move_8_ai_pcdi(void);
+void m68k_op_move_8_ai_pcix(void);
+void m68k_op_move_8_ai_i(void);
+void m68k_op_move_8_pi7_d(void);
+void m68k_op_move_8_pi_d(void);
+void m68k_op_move_8_pi7_ai(void);
+void m68k_op_move_8_pi7_pi(void);
+void m68k_op_move_8_pi7_pi7(void);
+void m68k_op_move_8_pi7_pd(void);
+void m68k_op_move_8_pi7_pd7(void);
+void m68k_op_move_8_pi7_di(void);
+void m68k_op_move_8_pi7_ix(void);
+void m68k_op_move_8_pi7_aw(void);
+void m68k_op_move_8_pi7_al(void);
+void m68k_op_move_8_pi7_pcdi(void);
+void m68k_op_move_8_pi7_pcix(void);
+void m68k_op_move_8_pi7_i(void);
+void m68k_op_move_8_pi_ai(void);
+void m68k_op_move_8_pi_pi(void);
+void m68k_op_move_8_pi_pi7(void);
+void m68k_op_move_8_pi_pd(void);
+void m68k_op_move_8_pi_pd7(void);
+void m68k_op_move_8_pi_di(void);
+void m68k_op_move_8_pi_ix(void);
+void m68k_op_move_8_pi_aw(void);
+void m68k_op_move_8_pi_al(void);
+void m68k_op_move_8_pi_pcdi(void);
+void m68k_op_move_8_pi_pcix(void);
+void m68k_op_move_8_pi_i(void);
+void m68k_op_move_8_pd7_d(void);
+void m68k_op_move_8_pd_d(void);
+void m68k_op_move_8_pd7_ai(void);
+void m68k_op_move_8_pd7_pi(void);
+void m68k_op_move_8_pd7_pi7(void);
+void m68k_op_move_8_pd7_pd(void);
+void m68k_op_move_8_pd7_pd7(void);
+void m68k_op_move_8_pd7_di(void);
+void m68k_op_move_8_pd7_ix(void);
+void m68k_op_move_8_pd7_aw(void);
+void m68k_op_move_8_pd7_al(void);
+void m68k_op_move_8_pd7_pcdi(void);
+void m68k_op_move_8_pd7_pcix(void);
+void m68k_op_move_8_pd7_i(void);
+void m68k_op_move_8_pd_ai(void);
+void m68k_op_move_8_pd_pi(void);
+void m68k_op_move_8_pd_pi7(void);
+void m68k_op_move_8_pd_pd(void);
+void m68k_op_move_8_pd_pd7(void);
+void m68k_op_move_8_pd_di(void);
+void m68k_op_move_8_pd_ix(void);
+void m68k_op_move_8_pd_aw(void);
+void m68k_op_move_8_pd_al(void);
+void m68k_op_move_8_pd_pcdi(void);
+void m68k_op_move_8_pd_pcix(void);
+void m68k_op_move_8_pd_i(void);
+void m68k_op_move_8_di_d(void);
+void m68k_op_move_8_di_ai(void);
+void m68k_op_move_8_di_pi(void);
+void m68k_op_move_8_di_pi7(void);
+void m68k_op_move_8_di_pd(void);
+void m68k_op_move_8_di_pd7(void);
+void m68k_op_move_8_di_di(void);
+void m68k_op_move_8_di_ix(void);
+void m68k_op_move_8_di_aw(void);
+void m68k_op_move_8_di_al(void);
+void m68k_op_move_8_di_pcdi(void);
+void m68k_op_move_8_di_pcix(void);
+void m68k_op_move_8_di_i(void);
+void m68k_op_move_8_ix_d(void);
+void m68k_op_move_8_ix_ai(void);
+void m68k_op_move_8_ix_pi(void);
+void m68k_op_move_8_ix_pi7(void);
+void m68k_op_move_8_ix_pd(void);
+void m68k_op_move_8_ix_pd7(void);
+void m68k_op_move_8_ix_di(void);
+void m68k_op_move_8_ix_ix(void);
+void m68k_op_move_8_ix_aw(void);
+void m68k_op_move_8_ix_al(void);
+void m68k_op_move_8_ix_pcdi(void);
+void m68k_op_move_8_ix_pcix(void);
+void m68k_op_move_8_ix_i(void);
+void m68k_op_move_8_aw_d(void);
+void m68k_op_move_8_aw_ai(void);
+void m68k_op_move_8_aw_pi(void);
+void m68k_op_move_8_aw_pi7(void);
+void m68k_op_move_8_aw_pd(void);
+void m68k_op_move_8_aw_pd7(void);
+void m68k_op_move_8_aw_di(void);
+void m68k_op_move_8_aw_ix(void);
+void m68k_op_move_8_aw_aw(void);
+void m68k_op_move_8_aw_al(void);
+void m68k_op_move_8_aw_pcdi(void);
+void m68k_op_move_8_aw_pcix(void);
+void m68k_op_move_8_aw_i(void);
+void m68k_op_move_8_al_d(void);
+void m68k_op_move_8_al_ai(void);
+void m68k_op_move_8_al_pi(void);
+void m68k_op_move_8_al_pi7(void);
+void m68k_op_move_8_al_pd(void);
+void m68k_op_move_8_al_pd7(void);
+void m68k_op_move_8_al_di(void);
+void m68k_op_move_8_al_ix(void);
+void m68k_op_move_8_al_aw(void);
+void m68k_op_move_8_al_al(void);
+void m68k_op_move_8_al_pcdi(void);
+void m68k_op_move_8_al_pcix(void);
+void m68k_op_move_8_al_i(void);
+void m68k_op_move_16_d_d(void);
+void m68k_op_move_16_d_a(void);
+void m68k_op_move_16_d_ai(void);
+void m68k_op_move_16_d_pi(void);
+void m68k_op_move_16_d_pd(void);
+void m68k_op_move_16_d_di(void);
+void m68k_op_move_16_d_ix(void);
+void m68k_op_move_16_d_aw(void);
+void m68k_op_move_16_d_al(void);
+void m68k_op_move_16_d_pcdi(void);
+void m68k_op_move_16_d_pcix(void);
+void m68k_op_move_16_d_i(void);
+void m68k_op_move_16_ai_d(void);
+void m68k_op_move_16_ai_a(void);
+void m68k_op_move_16_ai_ai(void);
+void m68k_op_move_16_ai_pi(void);
+void m68k_op_move_16_ai_pd(void);
+void m68k_op_move_16_ai_di(void);
+void m68k_op_move_16_ai_ix(void);
+void m68k_op_move_16_ai_aw(void);
+void m68k_op_move_16_ai_al(void);
+void m68k_op_move_16_ai_pcdi(void);
+void m68k_op_move_16_ai_pcix(void);
+void m68k_op_move_16_ai_i(void);
+void m68k_op_move_16_pi_d(void);
+void m68k_op_move_16_pi_a(void);
+void m68k_op_move_16_pi_ai(void);
+void m68k_op_move_16_pi_pi(void);
+void m68k_op_move_16_pi_pd(void);
+void m68k_op_move_16_pi_di(void);
+void m68k_op_move_16_pi_ix(void);
+void m68k_op_move_16_pi_aw(void);
+void m68k_op_move_16_pi_al(void);
+void m68k_op_move_16_pi_pcdi(void);
+void m68k_op_move_16_pi_pcix(void);
+void m68k_op_move_16_pi_i(void);
+void m68k_op_move_16_pd_d(void);
+void m68k_op_move_16_pd_a(void);
+void m68k_op_move_16_pd_ai(void);
+void m68k_op_move_16_pd_pi(void);
+void m68k_op_move_16_pd_pd(void);
+void m68k_op_move_16_pd_di(void);
+void m68k_op_move_16_pd_ix(void);
+void m68k_op_move_16_pd_aw(void);
+void m68k_op_move_16_pd_al(void);
+void m68k_op_move_16_pd_pcdi(void);
+void m68k_op_move_16_pd_pcix(void);
+void m68k_op_move_16_pd_i(void);
+void m68k_op_move_16_di_d(void);
+void m68k_op_move_16_di_a(void);
+void m68k_op_move_16_di_ai(void);
+void m68k_op_move_16_di_pi(void);
+void m68k_op_move_16_di_pd(void);
+void m68k_op_move_16_di_di(void);
+void m68k_op_move_16_di_ix(void);
+void m68k_op_move_16_di_aw(void);
+void m68k_op_move_16_di_al(void);
+void m68k_op_move_16_di_pcdi(void);
+void m68k_op_move_16_di_pcix(void);
+void m68k_op_move_16_di_i(void);
+void m68k_op_move_16_ix_d(void);
+void m68k_op_move_16_ix_a(void);
+void m68k_op_move_16_ix_ai(void);
+void m68k_op_move_16_ix_pi(void);
+void m68k_op_move_16_ix_pd(void);
+void m68k_op_move_16_ix_di(void);
+void m68k_op_move_16_ix_ix(void);
+void m68k_op_move_16_ix_aw(void);
+void m68k_op_move_16_ix_al(void);
+void m68k_op_move_16_ix_pcdi(void);
+void m68k_op_move_16_ix_pcix(void);
+void m68k_op_move_16_ix_i(void);
+void m68k_op_move_16_aw_d(void);
+void m68k_op_move_16_aw_a(void);
+void m68k_op_move_16_aw_ai(void);
+void m68k_op_move_16_aw_pi(void);
+void m68k_op_move_16_aw_pd(void);
+void m68k_op_move_16_aw_di(void);
+void m68k_op_move_16_aw_ix(void);
+void m68k_op_move_16_aw_aw(void);
+void m68k_op_move_16_aw_al(void);
+void m68k_op_move_16_aw_pcdi(void);
+void m68k_op_move_16_aw_pcix(void);
+void m68k_op_move_16_aw_i(void);
+void m68k_op_move_16_al_d(void);
+void m68k_op_move_16_al_a(void);
+void m68k_op_move_16_al_ai(void);
+void m68k_op_move_16_al_pi(void);
+void m68k_op_move_16_al_pd(void);
+void m68k_op_move_16_al_di(void);
+void m68k_op_move_16_al_ix(void);
+void m68k_op_move_16_al_aw(void);
+void m68k_op_move_16_al_al(void);
+void m68k_op_move_16_al_pcdi(void);
+void m68k_op_move_16_al_pcix(void);
+void m68k_op_move_16_al_i(void);
+void m68k_op_move_32_d_d(void);
+void m68k_op_move_32_d_a(void);
+void m68k_op_move_32_d_ai(void);
+void m68k_op_move_32_d_pi(void);
+void m68k_op_move_32_d_pd(void);
+void m68k_op_move_32_d_di(void);
+void m68k_op_move_32_d_ix(void);
+void m68k_op_move_32_d_aw(void);
+void m68k_op_move_32_d_al(void);
+void m68k_op_move_32_d_pcdi(void);
+void m68k_op_move_32_d_pcix(void);
+void m68k_op_move_32_d_i(void);
+void m68k_op_move_32_ai_d(void);
+void m68k_op_move_32_ai_a(void);
+void m68k_op_move_32_ai_ai(void);
+void m68k_op_move_32_ai_pi(void);
+void m68k_op_move_32_ai_pd(void);
+void m68k_op_move_32_ai_di(void);
+void m68k_op_move_32_ai_ix(void);
+void m68k_op_move_32_ai_aw(void);
+void m68k_op_move_32_ai_al(void);
+void m68k_op_move_32_ai_pcdi(void);
+void m68k_op_move_32_ai_pcix(void);
+void m68k_op_move_32_ai_i(void);
+void m68k_op_move_32_pi_d(void);
+void m68k_op_move_32_pi_a(void);
+void m68k_op_move_32_pi_ai(void);
+void m68k_op_move_32_pi_pi(void);
+void m68k_op_move_32_pi_pd(void);
+void m68k_op_move_32_pi_di(void);
+void m68k_op_move_32_pi_ix(void);
+void m68k_op_move_32_pi_aw(void);
+void m68k_op_move_32_pi_al(void);
+void m68k_op_move_32_pi_pcdi(void);
+void m68k_op_move_32_pi_pcix(void);
+void m68k_op_move_32_pi_i(void);
+void m68k_op_move_32_pd_d(void);
+void m68k_op_move_32_pd_a(void);
+void m68k_op_move_32_pd_ai(void);
+void m68k_op_move_32_pd_pi(void);
+void m68k_op_move_32_pd_pd(void);
+void m68k_op_move_32_pd_di(void);
+void m68k_op_move_32_pd_ix(void);
+void m68k_op_move_32_pd_aw(void);
+void m68k_op_move_32_pd_al(void);
+void m68k_op_move_32_pd_pcdi(void);
+void m68k_op_move_32_pd_pcix(void);
+void m68k_op_move_32_pd_i(void);
+void m68k_op_move_32_di_d(void);
+void m68k_op_move_32_di_a(void);
+void m68k_op_move_32_di_ai(void);
+void m68k_op_move_32_di_pi(void);
+void m68k_op_move_32_di_pd(void);
+void m68k_op_move_32_di_di(void);
+void m68k_op_move_32_di_ix(void);
+void m68k_op_move_32_di_aw(void);
+void m68k_op_move_32_di_al(void);
+void m68k_op_move_32_di_pcdi(void);
+void m68k_op_move_32_di_pcix(void);
+void m68k_op_move_32_di_i(void);
+void m68k_op_move_32_ix_d(void);
+void m68k_op_move_32_ix_a(void);
+void m68k_op_move_32_ix_ai(void);
+void m68k_op_move_32_ix_pi(void);
+void m68k_op_move_32_ix_pd(void);
+void m68k_op_move_32_ix_di(void);
+void m68k_op_move_32_ix_ix(void);
+void m68k_op_move_32_ix_aw(void);
+void m68k_op_move_32_ix_al(void);
+void m68k_op_move_32_ix_pcdi(void);
+void m68k_op_move_32_ix_pcix(void);
+void m68k_op_move_32_ix_i(void);
+void m68k_op_move_32_aw_d(void);
+void m68k_op_move_32_aw_a(void);
+void m68k_op_move_32_aw_ai(void);
+void m68k_op_move_32_aw_pi(void);
+void m68k_op_move_32_aw_pd(void);
+void m68k_op_move_32_aw_di(void);
+void m68k_op_move_32_aw_ix(void);
+void m68k_op_move_32_aw_aw(void);
+void m68k_op_move_32_aw_al(void);
+void m68k_op_move_32_aw_pcdi(void);
+void m68k_op_move_32_aw_pcix(void);
+void m68k_op_move_32_aw_i(void);
+void m68k_op_move_32_al_d(void);
+void m68k_op_move_32_al_a(void);
+void m68k_op_move_32_al_ai(void);
+void m68k_op_move_32_al_pi(void);
+void m68k_op_move_32_al_pd(void);
+void m68k_op_move_32_al_di(void);
+void m68k_op_move_32_al_ix(void);
+void m68k_op_move_32_al_aw(void);
+void m68k_op_move_32_al_al(void);
+void m68k_op_move_32_al_pcdi(void);
+void m68k_op_move_32_al_pcix(void);
+void m68k_op_move_32_al_i(void);
+void m68k_op_movea_16_d(void);
+void m68k_op_movea_16_a(void);
+void m68k_op_movea_16_ai(void);
+void m68k_op_movea_16_pi(void);
+void m68k_op_movea_16_pd(void);
+void m68k_op_movea_16_di(void);
+void m68k_op_movea_16_ix(void);
+void m68k_op_movea_16_aw(void);
+void m68k_op_movea_16_al(void);
+void m68k_op_movea_16_pcdi(void);
+void m68k_op_movea_16_pcix(void);
+void m68k_op_movea_16_i(void);
+void m68k_op_movea_32_d(void);
+void m68k_op_movea_32_a(void);
+void m68k_op_movea_32_ai(void);
+void m68k_op_movea_32_pi(void);
+void m68k_op_movea_32_pd(void);
+void m68k_op_movea_32_di(void);
+void m68k_op_movea_32_ix(void);
+void m68k_op_movea_32_aw(void);
+void m68k_op_movea_32_al(void);
+void m68k_op_movea_32_pcdi(void);
+void m68k_op_movea_32_pcix(void);
+void m68k_op_movea_32_i(void);
+void m68k_op_move_16_frc_d(void);
+void m68k_op_move_16_frc_ai(void);
+void m68k_op_move_16_frc_pi(void);
+void m68k_op_move_16_frc_pd(void);
+void m68k_op_move_16_frc_di(void);
+void m68k_op_move_16_frc_ix(void);
+void m68k_op_move_16_frc_aw(void);
+void m68k_op_move_16_frc_al(void);
+void m68k_op_move_16_toc_d(void);
+void m68k_op_move_16_toc_ai(void);
+void m68k_op_move_16_toc_pi(void);
+void m68k_op_move_16_toc_pd(void);
+void m68k_op_move_16_toc_di(void);
+void m68k_op_move_16_toc_ix(void);
+void m68k_op_move_16_toc_aw(void);
+void m68k_op_move_16_toc_al(void);
+void m68k_op_move_16_toc_pcdi(void);
+void m68k_op_move_16_toc_pcix(void);
+void m68k_op_move_16_toc_i(void);
+void m68k_op_move_16_frs_d(void);
+void m68k_op_move_16_frs_ai(void);
+void m68k_op_move_16_frs_pi(void);
+void m68k_op_move_16_frs_pd(void);
+void m68k_op_move_16_frs_di(void);
+void m68k_op_move_16_frs_ix(void);
+void m68k_op_move_16_frs_aw(void);
+void m68k_op_move_16_frs_al(void);
+void m68k_op_move_16_tos_d(void);
+void m68k_op_move_16_tos_ai(void);
+void m68k_op_move_16_tos_pi(void);
+void m68k_op_move_16_tos_pd(void);
+void m68k_op_move_16_tos_di(void);
+void m68k_op_move_16_tos_ix(void);
+void m68k_op_move_16_tos_aw(void);
+void m68k_op_move_16_tos_al(void);
+void m68k_op_move_16_tos_pcdi(void);
+void m68k_op_move_16_tos_pcix(void);
+void m68k_op_move_16_tos_i(void);
+void m68k_op_move_32_fru(void);
+void m68k_op_move_32_tou(void);
+void m68k_op_movec_32_cr(void);
+void m68k_op_movec_32_rc(void);
+void m68k_op_movem_16_re_pd(void);
+void m68k_op_movem_16_re_ai(void);
+void m68k_op_movem_16_re_di(void);
+void m68k_op_movem_16_re_ix(void);
+void m68k_op_movem_16_re_aw(void);
+void m68k_op_movem_16_re_al(void);
+void m68k_op_movem_32_re_pd(void);
+void m68k_op_movem_32_re_ai(void);
+void m68k_op_movem_32_re_di(void);
+void m68k_op_movem_32_re_ix(void);
+void m68k_op_movem_32_re_aw(void);
+void m68k_op_movem_32_re_al(void);
+void m68k_op_movem_16_er_pi(void);
+void m68k_op_movem_16_er_ai(void);
+void m68k_op_movem_16_er_di(void);
+void m68k_op_movem_16_er_ix(void);
+void m68k_op_movem_16_er_aw(void);
+void m68k_op_movem_16_er_al(void);
+void m68k_op_movem_16_er_pcdi(void);
+void m68k_op_movem_16_er_pcix(void);
+void m68k_op_movem_32_er_pi(void);
+void m68k_op_movem_32_er_ai(void);
+void m68k_op_movem_32_er_di(void);
+void m68k_op_movem_32_er_ix(void);
+void m68k_op_movem_32_er_aw(void);
+void m68k_op_movem_32_er_al(void);
+void m68k_op_movem_32_er_pcdi(void);
+void m68k_op_movem_32_er_pcix(void);
+void m68k_op_movep_16_re(void);
+void m68k_op_movep_32_re(void);
+void m68k_op_movep_16_er(void);
+void m68k_op_movep_32_er(void);
+void m68k_op_moves_8_ai(void);
+void m68k_op_moves_8_pi(void);
+void m68k_op_moves_8_pi7(void);
+void m68k_op_moves_8_pd(void);
+void m68k_op_moves_8_pd7(void);
+void m68k_op_moves_8_di(void);
+void m68k_op_moves_8_ix(void);
+void m68k_op_moves_8_aw(void);
+void m68k_op_moves_8_al(void);
+void m68k_op_moves_16_ai(void);
+void m68k_op_moves_16_pi(void);
+void m68k_op_moves_16_pd(void);
+void m68k_op_moves_16_di(void);
+void m68k_op_moves_16_ix(void);
+void m68k_op_moves_16_aw(void);
+void m68k_op_moves_16_al(void);
+void m68k_op_moves_32_ai(void);
+void m68k_op_moves_32_pi(void);
+void m68k_op_moves_32_pd(void);
+void m68k_op_moves_32_di(void);
+void m68k_op_moves_32_ix(void);
+void m68k_op_moves_32_aw(void);
+void m68k_op_moves_32_al(void);
+void m68k_op_moveq_32(void);
+void m68k_op_muls_16_d(void);
+void m68k_op_muls_16_ai(void);
+void m68k_op_muls_16_pi(void);
+void m68k_op_muls_16_pd(void);
+void m68k_op_muls_16_di(void);
+void m68k_op_muls_16_ix(void);
+void m68k_op_muls_16_aw(void);
+void m68k_op_muls_16_al(void);
+void m68k_op_muls_16_pcdi(void);
+void m68k_op_muls_16_pcix(void);
+void m68k_op_muls_16_i(void);
+void m68k_op_mulu_16_d(void);
+void m68k_op_mulu_16_ai(void);
+void m68k_op_mulu_16_pi(void);
+void m68k_op_mulu_16_pd(void);
+void m68k_op_mulu_16_di(void);
+void m68k_op_mulu_16_ix(void);
+void m68k_op_mulu_16_aw(void);
+void m68k_op_mulu_16_al(void);
+void m68k_op_mulu_16_pcdi(void);
+void m68k_op_mulu_16_pcix(void);
+void m68k_op_mulu_16_i(void);
+void m68k_op_mull_32_d(void);
+void m68k_op_mull_32_ai(void);
+void m68k_op_mull_32_pi(void);
+void m68k_op_mull_32_pd(void);
+void m68k_op_mull_32_di(void);
+void m68k_op_mull_32_ix(void);
+void m68k_op_mull_32_aw(void);
+void m68k_op_mull_32_al(void);
+void m68k_op_mull_32_pcdi(void);
+void m68k_op_mull_32_pcix(void);
+void m68k_op_mull_32_i(void);
+void m68k_op_nbcd_8_d(void);
+void m68k_op_nbcd_8_ai(void);
+void m68k_op_nbcd_8_pi(void);
+void m68k_op_nbcd_8_pi7(void);
+void m68k_op_nbcd_8_pd(void);
+void m68k_op_nbcd_8_pd7(void);
+void m68k_op_nbcd_8_di(void);
+void m68k_op_nbcd_8_ix(void);
+void m68k_op_nbcd_8_aw(void);
+void m68k_op_nbcd_8_al(void);
+void m68k_op_neg_8_d(void);
+void m68k_op_neg_8_ai(void);
+void m68k_op_neg_8_pi(void);
+void m68k_op_neg_8_pi7(void);
+void m68k_op_neg_8_pd(void);
+void m68k_op_neg_8_pd7(void);
+void m68k_op_neg_8_di(void);
+void m68k_op_neg_8_ix(void);
+void m68k_op_neg_8_aw(void);
+void m68k_op_neg_8_al(void);
+void m68k_op_neg_16_d(void);
+void m68k_op_neg_16_ai(void);
+void m68k_op_neg_16_pi(void);
+void m68k_op_neg_16_pd(void);
+void m68k_op_neg_16_di(void);
+void m68k_op_neg_16_ix(void);
+void m68k_op_neg_16_aw(void);
+void m68k_op_neg_16_al(void);
+void m68k_op_neg_32_d(void);
+void m68k_op_neg_32_ai(void);
+void m68k_op_neg_32_pi(void);
+void m68k_op_neg_32_pd(void);
+void m68k_op_neg_32_di(void);
+void m68k_op_neg_32_ix(void);
+void m68k_op_neg_32_aw(void);
+void m68k_op_neg_32_al(void);
+void m68k_op_negx_8_d(void);
+void m68k_op_negx_8_ai(void);
+void m68k_op_negx_8_pi(void);
+void m68k_op_negx_8_pi7(void);
+void m68k_op_negx_8_pd(void);
+void m68k_op_negx_8_pd7(void);
+void m68k_op_negx_8_di(void);
+void m68k_op_negx_8_ix(void);
+void m68k_op_negx_8_aw(void);
+void m68k_op_negx_8_al(void);
+void m68k_op_negx_16_d(void);
+void m68k_op_negx_16_ai(void);
+void m68k_op_negx_16_pi(void);
+void m68k_op_negx_16_pd(void);
+void m68k_op_negx_16_di(void);
+void m68k_op_negx_16_ix(void);
+void m68k_op_negx_16_aw(void);
+void m68k_op_negx_16_al(void);
+void m68k_op_negx_32_d(void);
+void m68k_op_negx_32_ai(void);
+void m68k_op_negx_32_pi(void);
+void m68k_op_negx_32_pd(void);
+void m68k_op_negx_32_di(void);
+void m68k_op_negx_32_ix(void);
+void m68k_op_negx_32_aw(void);
+void m68k_op_negx_32_al(void);
+void m68k_op_nop(void);
+void m68k_op_not_8_d(void);
+void m68k_op_not_8_ai(void);
+void m68k_op_not_8_pi(void);
+void m68k_op_not_8_pi7(void);
+void m68k_op_not_8_pd(void);
+void m68k_op_not_8_pd7(void);
+void m68k_op_not_8_di(void);
+void m68k_op_not_8_ix(void);
+void m68k_op_not_8_aw(void);
+void m68k_op_not_8_al(void);
+void m68k_op_not_16_d(void);
+void m68k_op_not_16_ai(void);
+void m68k_op_not_16_pi(void);
+void m68k_op_not_16_pd(void);
+void m68k_op_not_16_di(void);
+void m68k_op_not_16_ix(void);
+void m68k_op_not_16_aw(void);
+void m68k_op_not_16_al(void);
+void m68k_op_not_32_d(void);
+void m68k_op_not_32_ai(void);
+void m68k_op_not_32_pi(void);
+void m68k_op_not_32_pd(void);
+void m68k_op_not_32_di(void);
+void m68k_op_not_32_ix(void);
+void m68k_op_not_32_aw(void);
+void m68k_op_not_32_al(void);
+void m68k_op_or_8_er_d(void);
+void m68k_op_or_8_er_ai(void);
+void m68k_op_or_8_er_pi(void);
+void m68k_op_or_8_er_pi7(void);
+void m68k_op_or_8_er_pd(void);
+void m68k_op_or_8_er_pd7(void);
+void m68k_op_or_8_er_di(void);
+void m68k_op_or_8_er_ix(void);
+void m68k_op_or_8_er_aw(void);
+void m68k_op_or_8_er_al(void);
+void m68k_op_or_8_er_pcdi(void);
+void m68k_op_or_8_er_pcix(void);
+void m68k_op_or_8_er_i(void);
+void m68k_op_or_16_er_d(void);
+void m68k_op_or_16_er_ai(void);
+void m68k_op_or_16_er_pi(void);
+void m68k_op_or_16_er_pd(void);
+void m68k_op_or_16_er_di(void);
+void m68k_op_or_16_er_ix(void);
+void m68k_op_or_16_er_aw(void);
+void m68k_op_or_16_er_al(void);
+void m68k_op_or_16_er_pcdi(void);
+void m68k_op_or_16_er_pcix(void);
+void m68k_op_or_16_er_i(void);
+void m68k_op_or_32_er_d(void);
+void m68k_op_or_32_er_ai(void);
+void m68k_op_or_32_er_pi(void);
+void m68k_op_or_32_er_pd(void);
+void m68k_op_or_32_er_di(void);
+void m68k_op_or_32_er_ix(void);
+void m68k_op_or_32_er_aw(void);
+void m68k_op_or_32_er_al(void);
+void m68k_op_or_32_er_pcdi(void);
+void m68k_op_or_32_er_pcix(void);
+void m68k_op_or_32_er_i(void);
+void m68k_op_or_8_re_ai(void);
+void m68k_op_or_8_re_pi(void);
+void m68k_op_or_8_re_pi7(void);
+void m68k_op_or_8_re_pd(void);
+void m68k_op_or_8_re_pd7(void);
+void m68k_op_or_8_re_di(void);
+void m68k_op_or_8_re_ix(void);
+void m68k_op_or_8_re_aw(void);
+void m68k_op_or_8_re_al(void);
+void m68k_op_or_16_re_ai(void);
+void m68k_op_or_16_re_pi(void);
+void m68k_op_or_16_re_pd(void);
+void m68k_op_or_16_re_di(void);
+void m68k_op_or_16_re_ix(void);
+void m68k_op_or_16_re_aw(void);
+void m68k_op_or_16_re_al(void);
+void m68k_op_or_32_re_ai(void);
+void m68k_op_or_32_re_pi(void);
+void m68k_op_or_32_re_pd(void);
+void m68k_op_or_32_re_di(void);
+void m68k_op_or_32_re_ix(void);
+void m68k_op_or_32_re_aw(void);
+void m68k_op_or_32_re_al(void);
+void m68k_op_ori_8_d(void);
+void m68k_op_ori_8_ai(void);
+void m68k_op_ori_8_pi(void);
+void m68k_op_ori_8_pi7(void);
+void m68k_op_ori_8_pd(void);
+void m68k_op_ori_8_pd7(void);
+void m68k_op_ori_8_di(void);
+void m68k_op_ori_8_ix(void);
+void m68k_op_ori_8_aw(void);
+void m68k_op_ori_8_al(void);
+void m68k_op_ori_16_d(void);
+void m68k_op_ori_16_ai(void);
+void m68k_op_ori_16_pi(void);
+void m68k_op_ori_16_pd(void);
+void m68k_op_ori_16_di(void);
+void m68k_op_ori_16_ix(void);
+void m68k_op_ori_16_aw(void);
+void m68k_op_ori_16_al(void);
+void m68k_op_ori_32_d(void);
+void m68k_op_ori_32_ai(void);
+void m68k_op_ori_32_pi(void);
+void m68k_op_ori_32_pd(void);
+void m68k_op_ori_32_di(void);
+void m68k_op_ori_32_ix(void);
+void m68k_op_ori_32_aw(void);
+void m68k_op_ori_32_al(void);
+void m68k_op_ori_16_toc(void);
+void m68k_op_ori_16_tos(void);
+void m68k_op_pack_16_rr(void);
+void m68k_op_pack_16_mm_ax7(void);
+void m68k_op_pack_16_mm_ay7(void);
+void m68k_op_pack_16_mm_axy7(void);
+void m68k_op_pack_16_mm(void);
+void m68k_op_pea_32_ai(void);
+void m68k_op_pea_32_di(void);
+void m68k_op_pea_32_ix(void);
+void m68k_op_pea_32_aw(void);
+void m68k_op_pea_32_al(void);
+void m68k_op_pea_32_pcdi(void);
+void m68k_op_pea_32_pcix(void);
+void m68k_op_reset(void);
+void m68k_op_ror_8_s(void);
+void m68k_op_ror_16_s(void);
+void m68k_op_ror_32_s(void);
+void m68k_op_ror_8_r(void);
+void m68k_op_ror_16_r(void);
+void m68k_op_ror_32_r(void);
+void m68k_op_ror_16_ai(void);
+void m68k_op_ror_16_pi(void);
+void m68k_op_ror_16_pd(void);
+void m68k_op_ror_16_di(void);
+void m68k_op_ror_16_ix(void);
+void m68k_op_ror_16_aw(void);
+void m68k_op_ror_16_al(void);
+void m68k_op_rol_8_s(void);
+void m68k_op_rol_16_s(void);
+void m68k_op_rol_32_s(void);
+void m68k_op_rol_8_r(void);
+void m68k_op_rol_16_r(void);
+void m68k_op_rol_32_r(void);
+void m68k_op_rol_16_ai(void);
+void m68k_op_rol_16_pi(void);
+void m68k_op_rol_16_pd(void);
+void m68k_op_rol_16_di(void);
+void m68k_op_rol_16_ix(void);
+void m68k_op_rol_16_aw(void);
+void m68k_op_rol_16_al(void);
+void m68k_op_roxr_8_s(void);
+void m68k_op_roxr_16_s(void);
+void m68k_op_roxr_32_s(void);
+void m68k_op_roxr_8_r(void);
+void m68k_op_roxr_16_r(void);
+void m68k_op_roxr_32_r(void);
+void m68k_op_roxr_16_ai(void);
+void m68k_op_roxr_16_pi(void);
+void m68k_op_roxr_16_pd(void);
+void m68k_op_roxr_16_di(void);
+void m68k_op_roxr_16_ix(void);
+void m68k_op_roxr_16_aw(void);
+void m68k_op_roxr_16_al(void);
+void m68k_op_roxl_8_s(void);
+void m68k_op_roxl_16_s(void);
+void m68k_op_roxl_32_s(void);
+void m68k_op_roxl_8_r(void);
+void m68k_op_roxl_16_r(void);
+void m68k_op_roxl_32_r(void);
+void m68k_op_roxl_16_ai(void);
+void m68k_op_roxl_16_pi(void);
+void m68k_op_roxl_16_pd(void);
+void m68k_op_roxl_16_di(void);
+void m68k_op_roxl_16_ix(void);
+void m68k_op_roxl_16_aw(void);
+void m68k_op_roxl_16_al(void);
+void m68k_op_rtd_32(void);
+void m68k_op_rte_32(void);
+void m68k_op_rtm_32(void);
+void m68k_op_rtr_32(void);
+void m68k_op_rts_32(void);
+void m68k_op_sbcd_8_rr(void);
+void m68k_op_sbcd_8_mm_ax7(void);
+void m68k_op_sbcd_8_mm_ay7(void);
+void m68k_op_sbcd_8_mm_axy7(void);
+void m68k_op_sbcd_8_mm(void);
+void m68k_op_st_8_d(void);
+void m68k_op_st_8_ai(void);
+void m68k_op_st_8_pi(void);
+void m68k_op_st_8_pi7(void);
+void m68k_op_st_8_pd(void);
+void m68k_op_st_8_pd7(void);
+void m68k_op_st_8_di(void);
+void m68k_op_st_8_ix(void);
+void m68k_op_st_8_aw(void);
+void m68k_op_st_8_al(void);
+void m68k_op_sf_8_d(void);
+void m68k_op_sf_8_ai(void);
+void m68k_op_sf_8_pi(void);
+void m68k_op_sf_8_pi7(void);
+void m68k_op_sf_8_pd(void);
+void m68k_op_sf_8_pd7(void);
+void m68k_op_sf_8_di(void);
+void m68k_op_sf_8_ix(void);
+void m68k_op_sf_8_aw(void);
+void m68k_op_sf_8_al(void);
+void m68k_op_shi_8_d(void);
+void m68k_op_sls_8_d(void);
+void m68k_op_scc_8_d(void);
+void m68k_op_scs_8_d(void);
+void m68k_op_sne_8_d(void);
+void m68k_op_seq_8_d(void);
+void m68k_op_svc_8_d(void);
+void m68k_op_svs_8_d(void);
+void m68k_op_spl_8_d(void);
+void m68k_op_smi_8_d(void);
+void m68k_op_sge_8_d(void);
+void m68k_op_slt_8_d(void);
+void m68k_op_sgt_8_d(void);
+void m68k_op_sle_8_d(void);
+void m68k_op_shi_8_ai(void);
+void m68k_op_shi_8_pi(void);
+void m68k_op_shi_8_pi7(void);
+void m68k_op_shi_8_pd(void);
+void m68k_op_shi_8_pd7(void);
+void m68k_op_shi_8_di(void);
+void m68k_op_shi_8_ix(void);
+void m68k_op_shi_8_aw(void);
+void m68k_op_shi_8_al(void);
+void m68k_op_sls_8_ai(void);
+void m68k_op_sls_8_pi(void);
+void m68k_op_sls_8_pi7(void);
+void m68k_op_sls_8_pd(void);
+void m68k_op_sls_8_pd7(void);
+void m68k_op_sls_8_di(void);
+void m68k_op_sls_8_ix(void);
+void m68k_op_sls_8_aw(void);
+void m68k_op_sls_8_al(void);
+void m68k_op_scc_8_ai(void);
+void m68k_op_scc_8_pi(void);
+void m68k_op_scc_8_pi7(void);
+void m68k_op_scc_8_pd(void);
+void m68k_op_scc_8_pd7(void);
+void m68k_op_scc_8_di(void);
+void m68k_op_scc_8_ix(void);
+void m68k_op_scc_8_aw(void);
+void m68k_op_scc_8_al(void);
+void m68k_op_scs_8_ai(void);
+void m68k_op_scs_8_pi(void);
+void m68k_op_scs_8_pi7(void);
+void m68k_op_scs_8_pd(void);
+void m68k_op_scs_8_pd7(void);
+void m68k_op_scs_8_di(void);
+void m68k_op_scs_8_ix(void);
+void m68k_op_scs_8_aw(void);
+void m68k_op_scs_8_al(void);
+void m68k_op_sne_8_ai(void);
+void m68k_op_sne_8_pi(void);
+void m68k_op_sne_8_pi7(void);
+void m68k_op_sne_8_pd(void);
+void m68k_op_sne_8_pd7(void);
+void m68k_op_sne_8_di(void);
+void m68k_op_sne_8_ix(void);
+void m68k_op_sne_8_aw(void);
+void m68k_op_sne_8_al(void);
+void m68k_op_seq_8_ai(void);
+void m68k_op_seq_8_pi(void);
+void m68k_op_seq_8_pi7(void);
+void m68k_op_seq_8_pd(void);
+void m68k_op_seq_8_pd7(void);
+void m68k_op_seq_8_di(void);
+void m68k_op_seq_8_ix(void);
+void m68k_op_seq_8_aw(void);
+void m68k_op_seq_8_al(void);
+void m68k_op_svc_8_ai(void);
+void m68k_op_svc_8_pi(void);
+void m68k_op_svc_8_pi7(void);
+void m68k_op_svc_8_pd(void);
+void m68k_op_svc_8_pd7(void);
+void m68k_op_svc_8_di(void);
+void m68k_op_svc_8_ix(void);
+void m68k_op_svc_8_aw(void);
+void m68k_op_svc_8_al(void);
+void m68k_op_svs_8_ai(void);
+void m68k_op_svs_8_pi(void);
+void m68k_op_svs_8_pi7(void);
+void m68k_op_svs_8_pd(void);
+void m68k_op_svs_8_pd7(void);
+void m68k_op_svs_8_di(void);
+void m68k_op_svs_8_ix(void);
+void m68k_op_svs_8_aw(void);
+void m68k_op_svs_8_al(void);
+void m68k_op_spl_8_ai(void);
+void m68k_op_spl_8_pi(void);
+void m68k_op_spl_8_pi7(void);
+void m68k_op_spl_8_pd(void);
+void m68k_op_spl_8_pd7(void);
+void m68k_op_spl_8_di(void);
+void m68k_op_spl_8_ix(void);
+void m68k_op_spl_8_aw(void);
+void m68k_op_spl_8_al(void);
+void m68k_op_smi_8_ai(void);
+void m68k_op_smi_8_pi(void);
+void m68k_op_smi_8_pi7(void);
+void m68k_op_smi_8_pd(void);
+void m68k_op_smi_8_pd7(void);
+void m68k_op_smi_8_di(void);
+void m68k_op_smi_8_ix(void);
+void m68k_op_smi_8_aw(void);
+void m68k_op_smi_8_al(void);
+void m68k_op_sge_8_ai(void);
+void m68k_op_sge_8_pi(void);
+void m68k_op_sge_8_pi7(void);
+void m68k_op_sge_8_pd(void);
+void m68k_op_sge_8_pd7(void);
+void m68k_op_sge_8_di(void);
+void m68k_op_sge_8_ix(void);
+void m68k_op_sge_8_aw(void);
+void m68k_op_sge_8_al(void);
+void m68k_op_slt_8_ai(void);
+void m68k_op_slt_8_pi(void);
+void m68k_op_slt_8_pi7(void);
+void m68k_op_slt_8_pd(void);
+void m68k_op_slt_8_pd7(void);
+void m68k_op_slt_8_di(void);
+void m68k_op_slt_8_ix(void);
+void m68k_op_slt_8_aw(void);
+void m68k_op_slt_8_al(void);
+void m68k_op_sgt_8_ai(void);
+void m68k_op_sgt_8_pi(void);
+void m68k_op_sgt_8_pi7(void);
+void m68k_op_sgt_8_pd(void);
+void m68k_op_sgt_8_pd7(void);
+void m68k_op_sgt_8_di(void);
+void m68k_op_sgt_8_ix(void);
+void m68k_op_sgt_8_aw(void);
+void m68k_op_sgt_8_al(void);
+void m68k_op_sle_8_ai(void);
+void m68k_op_sle_8_pi(void);
+void m68k_op_sle_8_pi7(void);
+void m68k_op_sle_8_pd(void);
+void m68k_op_sle_8_pd7(void);
+void m68k_op_sle_8_di(void);
+void m68k_op_sle_8_ix(void);
+void m68k_op_sle_8_aw(void);
+void m68k_op_sle_8_al(void);
+void m68k_op_stop(void);
+void m68k_op_sub_8_er_d(void);
+void m68k_op_sub_8_er_ai(void);
+void m68k_op_sub_8_er_pi(void);
+void m68k_op_sub_8_er_pi7(void);
+void m68k_op_sub_8_er_pd(void);
+void m68k_op_sub_8_er_pd7(void);
+void m68k_op_sub_8_er_di(void);
+void m68k_op_sub_8_er_ix(void);
+void m68k_op_sub_8_er_aw(void);
+void m68k_op_sub_8_er_al(void);
+void m68k_op_sub_8_er_pcdi(void);
+void m68k_op_sub_8_er_pcix(void);
+void m68k_op_sub_8_er_i(void);
+void m68k_op_sub_16_er_d(void);
+void m68k_op_sub_16_er_a(void);
+void m68k_op_sub_16_er_ai(void);
+void m68k_op_sub_16_er_pi(void);
+void m68k_op_sub_16_er_pd(void);
+void m68k_op_sub_16_er_di(void);
+void m68k_op_sub_16_er_ix(void);
+void m68k_op_sub_16_er_aw(void);
+void m68k_op_sub_16_er_al(void);
+void m68k_op_sub_16_er_pcdi(void);
+void m68k_op_sub_16_er_pcix(void);
+void m68k_op_sub_16_er_i(void);
+void m68k_op_sub_32_er_d(void);
+void m68k_op_sub_32_er_a(void);
+void m68k_op_sub_32_er_ai(void);
+void m68k_op_sub_32_er_pi(void);
+void m68k_op_sub_32_er_pd(void);
+void m68k_op_sub_32_er_di(void);
+void m68k_op_sub_32_er_ix(void);
+void m68k_op_sub_32_er_aw(void);
+void m68k_op_sub_32_er_al(void);
+void m68k_op_sub_32_er_pcdi(void);
+void m68k_op_sub_32_er_pcix(void);
+void m68k_op_sub_32_er_i(void);
+void m68k_op_sub_8_re_ai(void);
+void m68k_op_sub_8_re_pi(void);
+void m68k_op_sub_8_re_pi7(void);
+void m68k_op_sub_8_re_pd(void);
+void m68k_op_sub_8_re_pd7(void);
+void m68k_op_sub_8_re_di(void);
+void m68k_op_sub_8_re_ix(void);
+void m68k_op_sub_8_re_aw(void);
+void m68k_op_sub_8_re_al(void);
+void m68k_op_sub_16_re_ai(void);
+void m68k_op_sub_16_re_pi(void);
+void m68k_op_sub_16_re_pd(void);
+void m68k_op_sub_16_re_di(void);
+void m68k_op_sub_16_re_ix(void);
+void m68k_op_sub_16_re_aw(void);
+void m68k_op_sub_16_re_al(void);
+void m68k_op_sub_32_re_ai(void);
+void m68k_op_sub_32_re_pi(void);
+void m68k_op_sub_32_re_pd(void);
+void m68k_op_sub_32_re_di(void);
+void m68k_op_sub_32_re_ix(void);
+void m68k_op_sub_32_re_aw(void);
+void m68k_op_sub_32_re_al(void);
+void m68k_op_suba_16_d(void);
+void m68k_op_suba_16_a(void);
+void m68k_op_suba_16_ai(void);
+void m68k_op_suba_16_pi(void);
+void m68k_op_suba_16_pd(void);
+void m68k_op_suba_16_di(void);
+void m68k_op_suba_16_ix(void);
+void m68k_op_suba_16_aw(void);
+void m68k_op_suba_16_al(void);
+void m68k_op_suba_16_pcdi(void);
+void m68k_op_suba_16_pcix(void);
+void m68k_op_suba_16_i(void);
+void m68k_op_suba_32_d(void);
+void m68k_op_suba_32_a(void);
+void m68k_op_suba_32_ai(void);
+void m68k_op_suba_32_pi(void);
+void m68k_op_suba_32_pd(void);
+void m68k_op_suba_32_di(void);
+void m68k_op_suba_32_ix(void);
+void m68k_op_suba_32_aw(void);
+void m68k_op_suba_32_al(void);
+void m68k_op_suba_32_pcdi(void);
+void m68k_op_suba_32_pcix(void);
+void m68k_op_suba_32_i(void);
+void m68k_op_subi_8_d(void);
+void m68k_op_subi_8_ai(void);
+void m68k_op_subi_8_pi(void);
+void m68k_op_subi_8_pi7(void);
+void m68k_op_subi_8_pd(void);
+void m68k_op_subi_8_pd7(void);
+void m68k_op_subi_8_di(void);
+void m68k_op_subi_8_ix(void);
+void m68k_op_subi_8_aw(void);
+void m68k_op_subi_8_al(void);
+void m68k_op_subi_16_d(void);
+void m68k_op_subi_16_ai(void);
+void m68k_op_subi_16_pi(void);
+void m68k_op_subi_16_pd(void);
+void m68k_op_subi_16_di(void);
+void m68k_op_subi_16_ix(void);
+void m68k_op_subi_16_aw(void);
+void m68k_op_subi_16_al(void);
+void m68k_op_subi_32_d(void);
+void m68k_op_subi_32_ai(void);
+void m68k_op_subi_32_pi(void);
+void m68k_op_subi_32_pd(void);
+void m68k_op_subi_32_di(void);
+void m68k_op_subi_32_ix(void);
+void m68k_op_subi_32_aw(void);
+void m68k_op_subi_32_al(void);
+void m68k_op_subq_8_d(void);
+void m68k_op_subq_8_ai(void);
+void m68k_op_subq_8_pi(void);
+void m68k_op_subq_8_pi7(void);
+void m68k_op_subq_8_pd(void);
+void m68k_op_subq_8_pd7(void);
+void m68k_op_subq_8_di(void);
+void m68k_op_subq_8_ix(void);
+void m68k_op_subq_8_aw(void);
+void m68k_op_subq_8_al(void);
+void m68k_op_subq_16_d(void);
+void m68k_op_subq_16_a(void);
+void m68k_op_subq_16_ai(void);
+void m68k_op_subq_16_pi(void);
+void m68k_op_subq_16_pd(void);
+void m68k_op_subq_16_di(void);
+void m68k_op_subq_16_ix(void);
+void m68k_op_subq_16_aw(void);
+void m68k_op_subq_16_al(void);
+void m68k_op_subq_32_d(void);
+void m68k_op_subq_32_a(void);
+void m68k_op_subq_32_ai(void);
+void m68k_op_subq_32_pi(void);
+void m68k_op_subq_32_pd(void);
+void m68k_op_subq_32_di(void);
+void m68k_op_subq_32_ix(void);
+void m68k_op_subq_32_aw(void);
+void m68k_op_subq_32_al(void);
+void m68k_op_subx_8_rr(void);
+void m68k_op_subx_16_rr(void);
+void m68k_op_subx_32_rr(void);
+void m68k_op_subx_8_mm_ax7(void);
+void m68k_op_subx_8_mm_ay7(void);
+void m68k_op_subx_8_mm_axy7(void);
+void m68k_op_subx_8_mm(void);
+void m68k_op_subx_16_mm(void);
+void m68k_op_subx_32_mm(void);
+void m68k_op_swap_32(void);
+void m68k_op_tas_8_d(void);
+void m68k_op_tas_8_ai(void);
+void m68k_op_tas_8_pi(void);
+void m68k_op_tas_8_pi7(void);
+void m68k_op_tas_8_pd(void);
+void m68k_op_tas_8_pd7(void);
+void m68k_op_tas_8_di(void);
+void m68k_op_tas_8_ix(void);
+void m68k_op_tas_8_aw(void);
+void m68k_op_tas_8_al(void);
+void m68k_op_trap(void);
+void m68k_op_trapt(void);
+void m68k_op_trapt_16(void);
+void m68k_op_trapt_32(void);
+void m68k_op_trapf(void);
+void m68k_op_trapf_16(void);
+void m68k_op_trapf_32(void);
+void m68k_op_traphi(void);
+void m68k_op_trapls(void);
+void m68k_op_trapcc(void);
+void m68k_op_trapcs(void);
+void m68k_op_trapne(void);
+void m68k_op_trapeq(void);
+void m68k_op_trapvc(void);
+void m68k_op_trapvs(void);
+void m68k_op_trappl(void);
+void m68k_op_trapmi(void);
+void m68k_op_trapge(void);
+void m68k_op_traplt(void);
+void m68k_op_trapgt(void);
+void m68k_op_traple(void);
+void m68k_op_traphi_16(void);
+void m68k_op_trapls_16(void);
+void m68k_op_trapcc_16(void);
+void m68k_op_trapcs_16(void);
+void m68k_op_trapne_16(void);
+void m68k_op_trapeq_16(void);
+void m68k_op_trapvc_16(void);
+void m68k_op_trapvs_16(void);
+void m68k_op_trappl_16(void);
+void m68k_op_trapmi_16(void);
+void m68k_op_trapge_16(void);
+void m68k_op_traplt_16(void);
+void m68k_op_trapgt_16(void);
+void m68k_op_traple_16(void);
+void m68k_op_traphi_32(void);
+void m68k_op_trapls_32(void);
+void m68k_op_trapcc_32(void);
+void m68k_op_trapcs_32(void);
+void m68k_op_trapne_32(void);
+void m68k_op_trapeq_32(void);
+void m68k_op_trapvc_32(void);
+void m68k_op_trapvs_32(void);
+void m68k_op_trappl_32(void);
+void m68k_op_trapmi_32(void);
+void m68k_op_trapge_32(void);
+void m68k_op_traplt_32(void);
+void m68k_op_trapgt_32(void);
+void m68k_op_traple_32(void);
+void m68k_op_trapv(void);
+void m68k_op_tst_8_d(void);
+void m68k_op_tst_8_ai(void);
+void m68k_op_tst_8_pi(void);
+void m68k_op_tst_8_pi7(void);
+void m68k_op_tst_8_pd(void);
+void m68k_op_tst_8_pd7(void);
+void m68k_op_tst_8_di(void);
+void m68k_op_tst_8_ix(void);
+void m68k_op_tst_8_aw(void);
+void m68k_op_tst_8_al(void);
+void m68k_op_tst_8_pcdi(void);
+void m68k_op_tst_8_pcix(void);
+void m68k_op_tst_8_i(void);
+void m68k_op_tst_16_d(void);
+void m68k_op_tst_16_a(void);
+void m68k_op_tst_16_ai(void);
+void m68k_op_tst_16_pi(void);
+void m68k_op_tst_16_pd(void);
+void m68k_op_tst_16_di(void);
+void m68k_op_tst_16_ix(void);
+void m68k_op_tst_16_aw(void);
+void m68k_op_tst_16_al(void);
+void m68k_op_tst_16_pcdi(void);
+void m68k_op_tst_16_pcix(void);
+void m68k_op_tst_16_i(void);
+void m68k_op_tst_32_d(void);
+void m68k_op_tst_32_a(void);
+void m68k_op_tst_32_ai(void);
+void m68k_op_tst_32_pi(void);
+void m68k_op_tst_32_pd(void);
+void m68k_op_tst_32_di(void);
+void m68k_op_tst_32_ix(void);
+void m68k_op_tst_32_aw(void);
+void m68k_op_tst_32_al(void);
+void m68k_op_tst_32_pcdi(void);
+void m68k_op_tst_32_pcix(void);
+void m68k_op_tst_32_i(void);
+void m68k_op_unlk_32_a7(void);
+void m68k_op_unlk_32(void);
+void m68k_op_unpk_16_rr(void);
+void m68k_op_unpk_16_mm_ax7(void);
+void m68k_op_unpk_16_mm_ay7(void);
+void m68k_op_unpk_16_mm_axy7(void);
+void m68k_op_unpk_16_mm(void);
+/* Build the opcode handler table */
+void m68ki_build_opcode_table(void);
+
+extern const void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
+extern const unsigned char m68ki_cycles[1][0x10000];
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KOPS__HEADER */
+
+
diff --git a/MCUME_pico2/picogenold/m68kops_pre.c b/MCUME_pico2/picogenold/m68kops_pre.c
new file mode 100644
index 0000000..7d1da0c
--- /dev/null
+++ b/MCUME_pico2/picogenold/m68kops_pre.c
@@ -0,0 +1,65545 @@
+#include "m68kops.h"
+
+//Opcodes are built on the host, this does not need to do anything.
+void m68ki_build_opcode_table() {}
+
+const void (*m68ki_instruction_jump_table[0x10000])(void) ={
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 
+	(void*)m68k_op_ori_8_d             , 	
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_ai            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi            , 
+	(void*)m68k_op_ori_8_pi7           , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd            , 
+	(void*)m68k_op_ori_8_pd7           , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_di            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_ix            , 
+	(void*)m68k_op_ori_8_aw            , 
+	(void*)m68k_op_ori_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_16_toc          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_ori_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_ai           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pi           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_pd           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_di           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_ix           , 
+	(void*)m68k_op_ori_16_aw           , 
+	(void*)m68k_op_ori_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_16_tos          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_ori_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_ai           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pi           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_pd           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_di           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_ix           , 
+	(void*)m68k_op_ori_32_aw           , 
+	(void*)m68k_op_ori_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_chk2cmp2_8_ai       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_di       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_ix       , 
+	(void*)m68k_op_chk2cmp2_8_aw       , 
+	(void*)m68k_op_chk2cmp2_8_al       , 
+	(void*)m68k_op_chk2cmp2_8_pcdi     , 
+	(void*)m68k_op_chk2cmp2_8_pcix     , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_andi_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_ai           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi           , 
+	(void*)m68k_op_andi_8_pi7          , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd           , 
+	(void*)m68k_op_andi_8_pd7          , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_di           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_ix           , 
+	(void*)m68k_op_andi_8_aw           , 
+	(void*)m68k_op_andi_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_16_toc         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_andi_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_ai          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pi          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_pd          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_di          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_ix          , 
+	(void*)m68k_op_andi_16_aw          , 
+	(void*)m68k_op_andi_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_16_tos         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_andi_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_ai          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pi          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_pd          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_di          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_ix          , 
+	(void*)m68k_op_andi_32_aw          , 
+	(void*)m68k_op_andi_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_chk2cmp2_16_ai      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_di      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_ix      , 
+	(void*)m68k_op_chk2cmp2_16_aw      , 
+	(void*)m68k_op_chk2cmp2_16_al      , 
+	(void*)m68k_op_chk2cmp2_16_pcdi    , 
+	(void*)m68k_op_chk2cmp2_16_pcix    , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_subi_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_ai           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi           , 
+	(void*)m68k_op_subi_8_pi7          , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd           , 
+	(void*)m68k_op_subi_8_pd7          , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_di           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_ix           , 
+	(void*)m68k_op_subi_8_aw           , 
+	(void*)m68k_op_subi_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_subi_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_ai          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pi          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_pd          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_di          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_ix          , 
+	(void*)m68k_op_subi_16_aw          , 
+	(void*)m68k_op_subi_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_subi_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_ai          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pi          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_pd          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_di          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_ix          , 
+	(void*)m68k_op_subi_32_aw          , 
+	(void*)m68k_op_subi_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_chk2cmp2_32_ai      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_di      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_ix      , 
+	(void*)m68k_op_chk2cmp2_32_aw      , 
+	(void*)m68k_op_chk2cmp2_32_al      , 
+	(void*)m68k_op_chk2cmp2_32_pcdi    , 
+	(void*)m68k_op_chk2cmp2_32_pcix    , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_addi_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_ai           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi           , 
+	(void*)m68k_op_addi_8_pi7          , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd           , 
+	(void*)m68k_op_addi_8_pd7          , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_di           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_ix           , 
+	(void*)m68k_op_addi_8_aw           , 
+	(void*)m68k_op_addi_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_addi_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_ai          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pi          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_pd          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_di          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_ix          , 
+	(void*)m68k_op_addi_16_aw          , 
+	(void*)m68k_op_addi_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_addi_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_ai          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pi          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_pd          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_di          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_ix          , 
+	(void*)m68k_op_addi_32_aw          , 
+	(void*)m68k_op_addi_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_rtm_32              , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_callm_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_di         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_ix         , 
+	(void*)m68k_op_callm_32_aw         , 
+	(void*)m68k_op_callm_32_al         , 
+	(void*)m68k_op_callm_32_pcdi       , 
+	(void*)m68k_op_callm_32_pcix       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_btst_32_s_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_ai         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi         , 
+	(void*)m68k_op_btst_8_s_pi7        , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd         , 
+	(void*)m68k_op_btst_8_s_pd7        , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_di         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_ix         , 
+	(void*)m68k_op_btst_8_s_aw         , 
+	(void*)m68k_op_btst_8_s_al         , 
+	(void*)m68k_op_btst_8_s_pcdi       , 
+	(void*)m68k_op_btst_8_s_pcix       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_bchg_32_s_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_ai         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi         , 
+	(void*)m68k_op_bchg_8_s_pi7        , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd         , 
+	(void*)m68k_op_bchg_8_s_pd7        , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_di         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_ix         , 
+	(void*)m68k_op_bchg_8_s_aw         , 
+	(void*)m68k_op_bchg_8_s_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_bclr_32_s_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_ai         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi         , 
+	(void*)m68k_op_bclr_8_s_pi7        , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd         , 
+	(void*)m68k_op_bclr_8_s_pd7        , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_di         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_ix         , 
+	(void*)m68k_op_bclr_8_s_aw         , 
+	(void*)m68k_op_bclr_8_s_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_bset_32_s_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_ai         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi         , 
+	(void*)m68k_op_bset_8_s_pi7        , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd         , 
+	(void*)m68k_op_bset_8_s_pd7        , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_di         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_ix         , 
+	(void*)m68k_op_bset_8_s_aw         , 
+	(void*)m68k_op_bset_8_s_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_eori_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_ai           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi           , 
+	(void*)m68k_op_eori_8_pi7          , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd           , 
+	(void*)m68k_op_eori_8_pd7          , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_di           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_ix           , 
+	(void*)m68k_op_eori_8_aw           , 
+	(void*)m68k_op_eori_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_16_toc         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_eori_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_ai          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pi          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_pd          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_di          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_ix          , 
+	(void*)m68k_op_eori_16_aw          , 
+	(void*)m68k_op_eori_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_16_tos         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_eori_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_ai          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pi          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_pd          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_di          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_ix          , 
+	(void*)m68k_op_eori_32_aw          , 
+	(void*)m68k_op_eori_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_ai            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi            , 
+	(void*)m68k_op_cas_8_pi7           , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd            , 
+	(void*)m68k_op_cas_8_pd7           , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_di            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_ix            , 
+	(void*)m68k_op_cas_8_aw            , 
+	(void*)m68k_op_cas_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_cmpi_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_ai           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi           , 
+	(void*)m68k_op_cmpi_8_pi7          , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd           , 
+	(void*)m68k_op_cmpi_8_pd7          , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_di           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_ix           , 
+	(void*)m68k_op_cmpi_8_aw           , 
+	(void*)m68k_op_cmpi_8_al           , 
+	(void*)m68k_op_cmpi_8_pcdi         , 
+	(void*)m68k_op_cmpi_8_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_cmpi_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_ai          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pi          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_pd          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_di          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_ix          , 
+	(void*)m68k_op_cmpi_16_aw          , 
+	(void*)m68k_op_cmpi_16_al          , 
+	(void*)m68k_op_cmpi_16_pcdi        , 
+	(void*)m68k_op_cmpi_16_pcix        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_cmpi_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_ai          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pi          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_pd          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_di          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_ix          , 
+	(void*)m68k_op_cmpi_32_aw          , 
+	(void*)m68k_op_cmpi_32_al          , 
+	(void*)m68k_op_cmpi_32_pcdi        , 
+	(void*)m68k_op_cmpi_32_pcix        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_ai           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pi           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_pd           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_di           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_ix           , 
+	(void*)m68k_op_cas_16_aw           , 
+	(void*)m68k_op_cas_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cas2_16             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_ai          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi          , 
+	(void*)m68k_op_moves_8_pi7         , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd          , 
+	(void*)m68k_op_moves_8_pd7         , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_di          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_ix          , 
+	(void*)m68k_op_moves_8_aw          , 
+	(void*)m68k_op_moves_8_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_ai         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pi         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_pd         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_di         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_ix         , 
+	(void*)m68k_op_moves_16_aw         , 
+	(void*)m68k_op_moves_16_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_ai         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pi         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_pd         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_di         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_ix         , 
+	(void*)m68k_op_moves_32_aw         , 
+	(void*)m68k_op_moves_32_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_ai           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pi           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_pd           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_di           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_ix           , 
+	(void*)m68k_op_cas_32_aw           , 
+	(void*)m68k_op_cas_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cas2_32             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_btst_32_r_d         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_movep_16_er         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_ai         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi         , 
+	(void*)m68k_op_btst_8_r_pi7        , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd         , 
+	(void*)m68k_op_btst_8_r_pd7        , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_di         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_ix         , 
+	(void*)m68k_op_btst_8_r_aw         , 
+	(void*)m68k_op_btst_8_r_al         , 
+	(void*)m68k_op_btst_8_r_pcdi       , 
+	(void*)m68k_op_btst_8_r_pcix       , 
+	(void*)m68k_op_btst_8_r_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_bchg_32_r_d         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_movep_32_er         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_ai         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi         , 
+	(void*)m68k_op_bchg_8_r_pi7        , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd         , 
+	(void*)m68k_op_bchg_8_r_pd7        , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_di         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_ix         , 
+	(void*)m68k_op_bchg_8_r_aw         , 
+	(void*)m68k_op_bchg_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_bclr_32_r_d         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_movep_16_re         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_ai         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi         , 
+	(void*)m68k_op_bclr_8_r_pi7        , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd         , 
+	(void*)m68k_op_bclr_8_r_pd7        , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_di         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_ix         , 
+	(void*)m68k_op_bclr_8_r_aw         , 
+	(void*)m68k_op_bclr_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_bset_32_r_d         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_movep_32_re         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_ai         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi         , 
+	(void*)m68k_op_bset_8_r_pi7        , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd         , 
+	(void*)m68k_op_bset_8_r_pd7        , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_di         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_ix         , 
+	(void*)m68k_op_bset_8_r_aw         , 
+	(void*)m68k_op_bset_8_r_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_move_8_aw_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_ai        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi        , 
+	(void*)m68k_op_move_8_aw_pi7       , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd        , 
+	(void*)m68k_op_move_8_aw_pd7       , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_di        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_ix        , 
+	(void*)m68k_op_move_8_aw_aw        , 
+	(void*)m68k_op_move_8_aw_al        , 
+	(void*)m68k_op_move_8_aw_pcdi      , 
+	(void*)m68k_op_move_8_aw_pcix      , 
+	(void*)m68k_op_move_8_aw_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_move_8_al_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_ai        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi        , 
+	(void*)m68k_op_move_8_al_pi7       , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd        , 
+	(void*)m68k_op_move_8_al_pd7       , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_di        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_ix        , 
+	(void*)m68k_op_move_8_al_aw        , 
+	(void*)m68k_op_move_8_al_al        , 
+	(void*)m68k_op_move_8_al_pcdi      , 
+	(void*)m68k_op_move_8_al_pcix      , 
+	(void*)m68k_op_move_8_al_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_move_8_pi_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_ai        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi        , 
+	(void*)m68k_op_move_8_pi_pi7       , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd        , 
+	(void*)m68k_op_move_8_pi_pd7       , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_di        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_ix        , 
+	(void*)m68k_op_move_8_pi_aw        , 
+	(void*)m68k_op_move_8_pi_al        , 
+	(void*)m68k_op_move_8_pi_pcdi      , 
+	(void*)m68k_op_move_8_pi_pcix      , 
+	(void*)m68k_op_move_8_pi_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_move_8_pd_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_ai        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi        , 
+	(void*)m68k_op_move_8_pd_pi7       , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd        , 
+	(void*)m68k_op_move_8_pd_pd7       , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_di        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_ix        , 
+	(void*)m68k_op_move_8_pd_aw        , 
+	(void*)m68k_op_move_8_pd_al        , 
+	(void*)m68k_op_move_8_pd_pcdi      , 
+	(void*)m68k_op_move_8_pd_pcix      , 
+	(void*)m68k_op_move_8_pd_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_move_8_d_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_ai         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi         , 
+	(void*)m68k_op_move_8_d_pi7        , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd         , 
+	(void*)m68k_op_move_8_d_pd7        , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_di         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_ix         , 
+	(void*)m68k_op_move_8_d_aw         , 
+	(void*)m68k_op_move_8_d_al         , 
+	(void*)m68k_op_move_8_d_pcdi       , 
+	(void*)m68k_op_move_8_d_pcix       , 
+	(void*)m68k_op_move_8_d_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_move_8_ai_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_ai        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi        , 
+	(void*)m68k_op_move_8_ai_pi7       , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd        , 
+	(void*)m68k_op_move_8_ai_pd7       , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_di        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_ix        , 
+	(void*)m68k_op_move_8_ai_aw        , 
+	(void*)m68k_op_move_8_ai_al        , 
+	(void*)m68k_op_move_8_ai_pcdi      , 
+	(void*)m68k_op_move_8_ai_pcix      , 
+	(void*)m68k_op_move_8_ai_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_move_8_pi7_d        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_ai       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi       , 
+	(void*)m68k_op_move_8_pi7_pi7      , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd       , 
+	(void*)m68k_op_move_8_pi7_pd7      , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_di       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_ix       , 
+	(void*)m68k_op_move_8_pi7_aw       , 
+	(void*)m68k_op_move_8_pi7_al       , 
+	(void*)m68k_op_move_8_pi7_pcdi     , 
+	(void*)m68k_op_move_8_pi7_pcix     , 
+	(void*)m68k_op_move_8_pi7_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_move_8_pd7_d        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_ai       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi       , 
+	(void*)m68k_op_move_8_pd7_pi7      , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd       , 
+	(void*)m68k_op_move_8_pd7_pd7      , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_di       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_ix       , 
+	(void*)m68k_op_move_8_pd7_aw       , 
+	(void*)m68k_op_move_8_pd7_al       , 
+	(void*)m68k_op_move_8_pd7_pcdi     , 
+	(void*)m68k_op_move_8_pd7_pcix     , 
+	(void*)m68k_op_move_8_pd7_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_move_8_di_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_ai        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi        , 
+	(void*)m68k_op_move_8_di_pi7       , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd        , 
+	(void*)m68k_op_move_8_di_pd7       , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_di        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_ix        , 
+	(void*)m68k_op_move_8_di_aw        , 
+	(void*)m68k_op_move_8_di_al        , 
+	(void*)m68k_op_move_8_di_pcdi      , 
+	(void*)m68k_op_move_8_di_pcix      , 
+	(void*)m68k_op_move_8_di_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_move_8_ix_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_ai        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi        , 
+	(void*)m68k_op_move_8_ix_pi7       , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd        , 
+	(void*)m68k_op_move_8_ix_pd7       , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_di        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_ix        , 
+	(void*)m68k_op_move_8_ix_aw        , 
+	(void*)m68k_op_move_8_ix_al        , 
+	(void*)m68k_op_move_8_ix_pcdi      , 
+	(void*)m68k_op_move_8_ix_pcix      , 
+	(void*)m68k_op_move_8_ix_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_d        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_a        , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_ai       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pi       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_pd       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_di       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_ix       , 
+	(void*)m68k_op_move_32_aw_aw       , 
+	(void*)m68k_op_move_32_aw_al       , 
+	(void*)m68k_op_move_32_aw_pcdi     , 
+	(void*)m68k_op_move_32_aw_pcix     , 
+	(void*)m68k_op_move_32_aw_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_d        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_a        , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_ai       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pi       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_pd       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_di       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_ix       , 
+	(void*)m68k_op_move_32_al_aw       , 
+	(void*)m68k_op_move_32_al_al       , 
+	(void*)m68k_op_move_32_al_pcdi     , 
+	(void*)m68k_op_move_32_al_pcix     , 
+	(void*)m68k_op_move_32_al_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_d         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_a         , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_ai        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pi        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_pd        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_di        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_ix        , 
+	(void*)m68k_op_move_32_d_aw        , 
+	(void*)m68k_op_move_32_d_al        , 
+	(void*)m68k_op_move_32_d_pcdi      , 
+	(void*)m68k_op_move_32_d_pcix      , 
+	(void*)m68k_op_move_32_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_d          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_a          , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_ai         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pi         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_pd         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_di         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_ix         , 
+	(void*)m68k_op_movea_32_aw         , 
+	(void*)m68k_op_movea_32_al         , 
+	(void*)m68k_op_movea_32_pcdi       , 
+	(void*)m68k_op_movea_32_pcix       , 
+	(void*)m68k_op_movea_32_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_d        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_a        , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_ai       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pi       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_pd       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_di       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_ix       , 
+	(void*)m68k_op_move_32_ai_aw       , 
+	(void*)m68k_op_move_32_ai_al       , 
+	(void*)m68k_op_move_32_ai_pcdi     , 
+	(void*)m68k_op_move_32_ai_pcix     , 
+	(void*)m68k_op_move_32_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_d        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_a        , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_ai       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pi       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_pd       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_di       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_ix       , 
+	(void*)m68k_op_move_32_pi_aw       , 
+	(void*)m68k_op_move_32_pi_al       , 
+	(void*)m68k_op_move_32_pi_pcdi     , 
+	(void*)m68k_op_move_32_pi_pcix     , 
+	(void*)m68k_op_move_32_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_d        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_a        , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_ai       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pi       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_pd       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_di       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_ix       , 
+	(void*)m68k_op_move_32_pd_aw       , 
+	(void*)m68k_op_move_32_pd_al       , 
+	(void*)m68k_op_move_32_pd_pcdi     , 
+	(void*)m68k_op_move_32_pd_pcix     , 
+	(void*)m68k_op_move_32_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_d        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_a        , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_ai       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pi       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_pd       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_di       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_ix       , 
+	(void*)m68k_op_move_32_di_aw       , 
+	(void*)m68k_op_move_32_di_al       , 
+	(void*)m68k_op_move_32_di_pcdi     , 
+	(void*)m68k_op_move_32_di_pcix     , 
+	(void*)m68k_op_move_32_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_d        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_a        , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_ai       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pi       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_pd       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_di       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_ix       , 
+	(void*)m68k_op_move_32_ix_aw       , 
+	(void*)m68k_op_move_32_ix_al       , 
+	(void*)m68k_op_move_32_ix_pcdi     , 
+	(void*)m68k_op_move_32_ix_pcix     , 
+	(void*)m68k_op_move_32_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_d        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_a        , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_ai       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pi       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_pd       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_di       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_ix       , 
+	(void*)m68k_op_move_16_aw_aw       , 
+	(void*)m68k_op_move_16_aw_al       , 
+	(void*)m68k_op_move_16_aw_pcdi     , 
+	(void*)m68k_op_move_16_aw_pcix     , 
+	(void*)m68k_op_move_16_aw_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_d        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_a        , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_ai       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pi       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_pd       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_di       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_ix       , 
+	(void*)m68k_op_move_16_al_aw       , 
+	(void*)m68k_op_move_16_al_al       , 
+	(void*)m68k_op_move_16_al_pcdi     , 
+	(void*)m68k_op_move_16_al_pcix     , 
+	(void*)m68k_op_move_16_al_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_d         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_a         , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_ai        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pi        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_pd        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_di        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_ix        , 
+	(void*)m68k_op_move_16_d_aw        , 
+	(void*)m68k_op_move_16_d_al        , 
+	(void*)m68k_op_move_16_d_pcdi      , 
+	(void*)m68k_op_move_16_d_pcix      , 
+	(void*)m68k_op_move_16_d_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_d          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_a          , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_ai         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pi         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_pd         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_di         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_ix         , 
+	(void*)m68k_op_movea_16_aw         , 
+	(void*)m68k_op_movea_16_al         , 
+	(void*)m68k_op_movea_16_pcdi       , 
+	(void*)m68k_op_movea_16_pcix       , 
+	(void*)m68k_op_movea_16_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_d        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_a        , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_ai       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pi       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_pd       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_di       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_ix       , 
+	(void*)m68k_op_move_16_ai_aw       , 
+	(void*)m68k_op_move_16_ai_al       , 
+	(void*)m68k_op_move_16_ai_pcdi     , 
+	(void*)m68k_op_move_16_ai_pcix     , 
+	(void*)m68k_op_move_16_ai_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_d        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_a        , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_ai       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pi       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_pd       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_di       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_ix       , 
+	(void*)m68k_op_move_16_pi_aw       , 
+	(void*)m68k_op_move_16_pi_al       , 
+	(void*)m68k_op_move_16_pi_pcdi     , 
+	(void*)m68k_op_move_16_pi_pcix     , 
+	(void*)m68k_op_move_16_pi_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_d        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_a        , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_ai       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pi       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_pd       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_di       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_ix       , 
+	(void*)m68k_op_move_16_pd_aw       , 
+	(void*)m68k_op_move_16_pd_al       , 
+	(void*)m68k_op_move_16_pd_pcdi     , 
+	(void*)m68k_op_move_16_pd_pcix     , 
+	(void*)m68k_op_move_16_pd_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_d        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_a        , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_ai       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pi       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_pd       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_di       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_ix       , 
+	(void*)m68k_op_move_16_di_aw       , 
+	(void*)m68k_op_move_16_di_al       , 
+	(void*)m68k_op_move_16_di_pcdi     , 
+	(void*)m68k_op_move_16_di_pcix     , 
+	(void*)m68k_op_move_16_di_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_d        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_a        , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_ai       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pi       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_pd       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_di       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_ix       , 
+	(void*)m68k_op_move_16_ix_aw       , 
+	(void*)m68k_op_move_16_ix_al       , 
+	(void*)m68k_op_move_16_ix_pcdi     , 
+	(void*)m68k_op_move_16_ix_pcix     , 
+	(void*)m68k_op_move_16_ix_i        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_negx_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_ai           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi           , 
+	(void*)m68k_op_negx_8_pi7          , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd           , 
+	(void*)m68k_op_negx_8_pd7          , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_di           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_ix           , 
+	(void*)m68k_op_negx_8_aw           , 
+	(void*)m68k_op_negx_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_negx_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_ai          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pi          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_pd          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_di          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_ix          , 
+	(void*)m68k_op_negx_16_aw          , 
+	(void*)m68k_op_negx_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_negx_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_ai          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pi          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_pd          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_di          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_ix          , 
+	(void*)m68k_op_negx_32_aw          , 
+	(void*)m68k_op_negx_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_move_16_frs_d       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_ai      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pi      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_pd      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_di      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_ix      , 
+	(void*)m68k_op_move_16_frs_aw      , 
+	(void*)m68k_op_move_16_frs_al      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_clr_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_ai            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi            , 
+	(void*)m68k_op_clr_8_pi7           , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd            , 
+	(void*)m68k_op_clr_8_pd7           , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_di            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_ix            , 
+	(void*)m68k_op_clr_8_aw            , 
+	(void*)m68k_op_clr_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_clr_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_ai           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pi           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_pd           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_di           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_ix           , 
+	(void*)m68k_op_clr_16_aw           , 
+	(void*)m68k_op_clr_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_clr_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_ai           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pi           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_pd           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_di           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_ix           , 
+	(void*)m68k_op_clr_32_aw           , 
+	(void*)m68k_op_clr_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_move_16_frc_d       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_ai      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pi      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_pd      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_di      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_ix      , 
+	(void*)m68k_op_move_16_frc_aw      , 
+	(void*)m68k_op_move_16_frc_al      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_neg_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_ai            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi            , 
+	(void*)m68k_op_neg_8_pi7           , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd            , 
+	(void*)m68k_op_neg_8_pd7           , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_di            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_ix            , 
+	(void*)m68k_op_neg_8_aw            , 
+	(void*)m68k_op_neg_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_neg_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_ai           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pi           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_pd           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_di           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_ix           , 
+	(void*)m68k_op_neg_16_aw           , 
+	(void*)m68k_op_neg_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_neg_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_ai           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pi           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_pd           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_di           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_ix           , 
+	(void*)m68k_op_neg_32_aw           , 
+	(void*)m68k_op_neg_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_move_16_toc_d       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_ai      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pi      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_pd      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_di      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_ix      , 
+	(void*)m68k_op_move_16_toc_aw      , 
+	(void*)m68k_op_move_16_toc_al      , 
+	(void*)m68k_op_move_16_toc_pcdi    , 
+	(void*)m68k_op_move_16_toc_pcix    , 
+	(void*)m68k_op_move_16_toc_i       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_not_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_ai            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi            , 
+	(void*)m68k_op_not_8_pi7           , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd            , 
+	(void*)m68k_op_not_8_pd7           , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_di            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_ix            , 
+	(void*)m68k_op_not_8_aw            , 
+	(void*)m68k_op_not_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_not_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_ai           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pi           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_pd           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_di           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_ix           , 
+	(void*)m68k_op_not_16_aw           , 
+	(void*)m68k_op_not_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_not_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_ai           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pi           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_pd           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_di           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_ix           , 
+	(void*)m68k_op_not_32_aw           , 
+	(void*)m68k_op_not_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_move_16_tos_d       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_ai      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pi      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_pd      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_di      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_ix      , 
+	(void*)m68k_op_move_16_tos_aw      , 
+	(void*)m68k_op_move_16_tos_al      , 
+	(void*)m68k_op_move_16_tos_pcdi    , 
+	(void*)m68k_op_move_16_tos_pcix    , 
+	(void*)m68k_op_move_16_tos_i       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_nbcd_8_d            , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32             , 
+	(void*)m68k_op_link_32_a7          , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_ai           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi           , 
+	(void*)m68k_op_nbcd_8_pi7          , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd           , 
+	(void*)m68k_op_nbcd_8_pd7          , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_di           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_ix           , 
+	(void*)m68k_op_nbcd_8_aw           , 
+	(void*)m68k_op_nbcd_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_swap_32             , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_bkpt                , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_pea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_di           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_ix           , 
+	(void*)m68k_op_pea_32_aw           , 
+	(void*)m68k_op_pea_32_al           , 
+	(void*)m68k_op_pea_32_pcdi         , 
+	(void*)m68k_op_pea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_ext_16              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_movem_16_re_ai      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_pd      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_di      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_ix      , 
+	(void*)m68k_op_movem_16_re_aw      , 
+	(void*)m68k_op_movem_16_re_al      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_ext_32              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_movem_32_re_ai      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_pd      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_di      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_ix      , 
+	(void*)m68k_op_movem_32_re_aw      , 
+	(void*)m68k_op_movem_32_re_al      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_extb_32             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_tst_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_ai            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi            , 
+	(void*)m68k_op_tst_8_pi7           , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd            , 
+	(void*)m68k_op_tst_8_pd7           , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_di            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_ix            , 
+	(void*)m68k_op_tst_8_aw            , 
+	(void*)m68k_op_tst_8_al            , 
+	(void*)m68k_op_tst_8_pcdi          , 
+	(void*)m68k_op_tst_8_pcix          , 
+	(void*)m68k_op_tst_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_d            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_a            , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_ai           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pi           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_pd           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_di           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_ix           , 
+	(void*)m68k_op_tst_16_aw           , 
+	(void*)m68k_op_tst_16_al           , 
+	(void*)m68k_op_tst_16_pcdi         , 
+	(void*)m68k_op_tst_16_pcix         , 
+	(void*)m68k_op_tst_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_d            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_a            , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_ai           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pi           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_pd           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_di           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_ix           , 
+	(void*)m68k_op_tst_32_aw           , 
+	(void*)m68k_op_tst_32_al           , 
+	(void*)m68k_op_tst_32_pcdi         , 
+	(void*)m68k_op_tst_32_pcix         , 
+	(void*)m68k_op_tst_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_tas_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_ai            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi            , 
+	(void*)m68k_op_tas_8_pi7           , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd            , 
+	(void*)m68k_op_tas_8_pd7           , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_di            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_ix            , 
+	(void*)m68k_op_tas_8_aw            , 
+	(void*)m68k_op_tas_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_mull_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_ai          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pi          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_pd          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_di          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_ix          , 
+	(void*)m68k_op_mull_32_aw          , 
+	(void*)m68k_op_mull_32_al          , 
+	(void*)m68k_op_mull_32_pcdi        , 
+	(void*)m68k_op_mull_32_pcix        , 
+	(void*)m68k_op_mull_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_divl_32_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_ai          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pi          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_pd          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_di          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_ix          , 
+	(void*)m68k_op_divl_32_aw          , 
+	(void*)m68k_op_divl_32_al          , 
+	(void*)m68k_op_divl_32_pcdi        , 
+	(void*)m68k_op_divl_32_pcix        , 
+	(void*)m68k_op_divl_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_ai      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_movem_16_er_pi      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_di      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_ix      , 
+	(void*)m68k_op_movem_16_er_aw      , 
+	(void*)m68k_op_movem_16_er_al      , 
+	(void*)m68k_op_movem_16_er_pcdi    , 
+	(void*)m68k_op_movem_16_er_pcix    , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_ai      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_movem_32_er_pi      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_di      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_ix      , 
+	(void*)m68k_op_movem_32_er_aw      , 
+	(void*)m68k_op_movem_32_er_al      , 
+	(void*)m68k_op_movem_32_er_pcdi    , 
+	(void*)m68k_op_movem_32_er_pcix    , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_trap                , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16             , 
+	(void*)m68k_op_link_16_a7          , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32             , 
+	(void*)m68k_op_unlk_32_a7          , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_tou         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_move_32_fru         , 
+	(void*)m68k_op_reset               , 
+	(void*)m68k_op_nop                 , 
+	(void*)m68k_op_stop                , 
+	(void*)m68k_op_rte_32              , 
+	(void*)m68k_op_rtd_32              , 
+	(void*)m68k_op_rts_32              , 
+	(void*)m68k_op_trapv               , 
+	(void*)m68k_op_rtr_32              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_movec_32_cr         , 
+	(void*)m68k_op_movec_32_rc         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_jsr_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_di           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_ix           , 
+	(void*)m68k_op_jsr_32_aw           , 
+	(void*)m68k_op_jsr_32_al           , 
+	(void*)m68k_op_jsr_32_pcdi         , 
+	(void*)m68k_op_jsr_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_jmp_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_di           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_ix           , 
+	(void*)m68k_op_jmp_32_aw           , 
+	(void*)m68k_op_jmp_32_al           , 
+	(void*)m68k_op_jmp_32_pcdi         , 
+	(void*)m68k_op_jmp_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_chk_32_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_ai           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pi           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_pd           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_di           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_ix           , 
+	(void*)m68k_op_chk_32_aw           , 
+	(void*)m68k_op_chk_32_al           , 
+	(void*)m68k_op_chk_32_pcdi         , 
+	(void*)m68k_op_chk_32_pcix         , 
+	(void*)m68k_op_chk_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_chk_16_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_ai           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pi           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_pd           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_di           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_ix           , 
+	(void*)m68k_op_chk_16_aw           , 
+	(void*)m68k_op_chk_16_al           , 
+	(void*)m68k_op_chk_16_pcdi         , 
+	(void*)m68k_op_chk_16_pcix         , 
+	(void*)m68k_op_chk_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_lea_32_ai           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_di           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_ix           , 
+	(void*)m68k_op_lea_32_aw           , 
+	(void*)m68k_op_lea_32_al           , 
+	(void*)m68k_op_lea_32_pcdi         , 
+	(void*)m68k_op_lea_32_pcix         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_st_8_d              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_dbt_16              , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_ai             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi             , 
+	(void*)m68k_op_st_8_pi7            , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd             , 
+	(void*)m68k_op_st_8_pd7            , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_di             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_ix             , 
+	(void*)m68k_op_st_8_aw             , 
+	(void*)m68k_op_st_8_al             , 
+	(void*)m68k_op_trapt_16            , 
+	(void*)m68k_op_trapt_32            , 
+	(void*)m68k_op_trapt               , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_sf_8_d              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_dbf_16              , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_ai             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi             , 
+	(void*)m68k_op_sf_8_pi7            , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd             , 
+	(void*)m68k_op_sf_8_pd7            , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_di             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_ix             , 
+	(void*)m68k_op_sf_8_aw             , 
+	(void*)m68k_op_sf_8_al             , 
+	(void*)m68k_op_trapf_16            , 
+	(void*)m68k_op_trapf_32            , 
+	(void*)m68k_op_trapf               , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_shi_8_d             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_dbhi_16             , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_ai            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi            , 
+	(void*)m68k_op_shi_8_pi7           , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd            , 
+	(void*)m68k_op_shi_8_pd7           , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_di            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_ix            , 
+	(void*)m68k_op_shi_8_aw            , 
+	(void*)m68k_op_shi_8_al            , 
+	(void*)m68k_op_traphi_16           , 
+	(void*)m68k_op_traphi_32           , 
+	(void*)m68k_op_traphi              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_sls_8_d             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_dbls_16             , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_ai            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi            , 
+	(void*)m68k_op_sls_8_pi7           , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd            , 
+	(void*)m68k_op_sls_8_pd7           , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_di            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_ix            , 
+	(void*)m68k_op_sls_8_aw            , 
+	(void*)m68k_op_sls_8_al            , 
+	(void*)m68k_op_trapls_16           , 
+	(void*)m68k_op_trapls_32           , 
+	(void*)m68k_op_trapls              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_scc_8_d             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_dbcc_16             , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_ai            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi            , 
+	(void*)m68k_op_scc_8_pi7           , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd            , 
+	(void*)m68k_op_scc_8_pd7           , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_di            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_ix            , 
+	(void*)m68k_op_scc_8_aw            , 
+	(void*)m68k_op_scc_8_al            , 
+	(void*)m68k_op_trapcc_16           , 
+	(void*)m68k_op_trapcc_32           , 
+	(void*)m68k_op_trapcc              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_scs_8_d             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_dbcs_16             , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_ai            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi            , 
+	(void*)m68k_op_scs_8_pi7           , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd            , 
+	(void*)m68k_op_scs_8_pd7           , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_di            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_ix            , 
+	(void*)m68k_op_scs_8_aw            , 
+	(void*)m68k_op_scs_8_al            , 
+	(void*)m68k_op_trapcs_16           , 
+	(void*)m68k_op_trapcs_32           , 
+	(void*)m68k_op_trapcs              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_sne_8_d             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_dbne_16             , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_ai            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi            , 
+	(void*)m68k_op_sne_8_pi7           , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd            , 
+	(void*)m68k_op_sne_8_pd7           , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_di            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_ix            , 
+	(void*)m68k_op_sne_8_aw            , 
+	(void*)m68k_op_sne_8_al            , 
+	(void*)m68k_op_trapne_16           , 
+	(void*)m68k_op_trapne_32           , 
+	(void*)m68k_op_trapne              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_seq_8_d             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_dbeq_16             , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_ai            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi            , 
+	(void*)m68k_op_seq_8_pi7           , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd            , 
+	(void*)m68k_op_seq_8_pd7           , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_di            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_ix            , 
+	(void*)m68k_op_seq_8_aw            , 
+	(void*)m68k_op_seq_8_al            , 
+	(void*)m68k_op_trapeq_16           , 
+	(void*)m68k_op_trapeq_32           , 
+	(void*)m68k_op_trapeq              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_svc_8_d             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_dbvc_16             , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_ai            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi            , 
+	(void*)m68k_op_svc_8_pi7           , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd            , 
+	(void*)m68k_op_svc_8_pd7           , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_di            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_ix            , 
+	(void*)m68k_op_svc_8_aw            , 
+	(void*)m68k_op_svc_8_al            , 
+	(void*)m68k_op_trapvc_16           , 
+	(void*)m68k_op_trapvc_32           , 
+	(void*)m68k_op_trapvc              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_svs_8_d             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_dbvs_16             , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_ai            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi            , 
+	(void*)m68k_op_svs_8_pi7           , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd            , 
+	(void*)m68k_op_svs_8_pd7           , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_di            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_ix            , 
+	(void*)m68k_op_svs_8_aw            , 
+	(void*)m68k_op_svs_8_al            , 
+	(void*)m68k_op_trapvs_16           , 
+	(void*)m68k_op_trapvs_32           , 
+	(void*)m68k_op_trapvs              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_spl_8_d             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_dbpl_16             , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_ai            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi            , 
+	(void*)m68k_op_spl_8_pi7           , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd            , 
+	(void*)m68k_op_spl_8_pd7           , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_di            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_ix            , 
+	(void*)m68k_op_spl_8_aw            , 
+	(void*)m68k_op_spl_8_al            , 
+	(void*)m68k_op_trappl_16           , 
+	(void*)m68k_op_trappl_32           , 
+	(void*)m68k_op_trappl              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_smi_8_d             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_dbmi_16             , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_ai            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi            , 
+	(void*)m68k_op_smi_8_pi7           , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd            , 
+	(void*)m68k_op_smi_8_pd7           , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_di            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_ix            , 
+	(void*)m68k_op_smi_8_aw            , 
+	(void*)m68k_op_smi_8_al            , 
+	(void*)m68k_op_trapmi_16           , 
+	(void*)m68k_op_trapmi_32           , 
+	(void*)m68k_op_trapmi              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_sge_8_d             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_dbge_16             , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_ai            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi            , 
+	(void*)m68k_op_sge_8_pi7           , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd            , 
+	(void*)m68k_op_sge_8_pd7           , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_di            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_ix            , 
+	(void*)m68k_op_sge_8_aw            , 
+	(void*)m68k_op_sge_8_al            , 
+	(void*)m68k_op_trapge_16           , 
+	(void*)m68k_op_trapge_32           , 
+	(void*)m68k_op_trapge              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_slt_8_d             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_dblt_16             , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_ai            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi            , 
+	(void*)m68k_op_slt_8_pi7           , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd            , 
+	(void*)m68k_op_slt_8_pd7           , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_di            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_ix            , 
+	(void*)m68k_op_slt_8_aw            , 
+	(void*)m68k_op_slt_8_al            , 
+	(void*)m68k_op_traplt_16           , 
+	(void*)m68k_op_traplt_32           , 
+	(void*)m68k_op_traplt              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_addq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_ai           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi           , 
+	(void*)m68k_op_addq_8_pi7          , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd           , 
+	(void*)m68k_op_addq_8_pd7          , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_di           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_ix           , 
+	(void*)m68k_op_addq_8_aw           , 
+	(void*)m68k_op_addq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_d           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_a           , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_ai          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pi          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_pd          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_di          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_ix          , 
+	(void*)m68k_op_addq_16_aw          , 
+	(void*)m68k_op_addq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_d           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_a           , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_ai          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pi          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_pd          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_di          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_ix          , 
+	(void*)m68k_op_addq_32_aw          , 
+	(void*)m68k_op_addq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_sgt_8_d             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_dbgt_16             , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_ai            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi            , 
+	(void*)m68k_op_sgt_8_pi7           , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd            , 
+	(void*)m68k_op_sgt_8_pd7           , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_di            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_ix            , 
+	(void*)m68k_op_sgt_8_aw            , 
+	(void*)m68k_op_sgt_8_al            , 
+	(void*)m68k_op_trapgt_16           , 
+	(void*)m68k_op_trapgt_32           , 
+	(void*)m68k_op_trapgt              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_subq_8_d            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_ai           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi           , 
+	(void*)m68k_op_subq_8_pi7          , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd           , 
+	(void*)m68k_op_subq_8_pd7          , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_di           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_ix           , 
+	(void*)m68k_op_subq_8_aw           , 
+	(void*)m68k_op_subq_8_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_d           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_a           , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_ai          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pi          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_pd          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_di          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_ix          , 
+	(void*)m68k_op_subq_16_aw          , 
+	(void*)m68k_op_subq_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_d           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_a           , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_ai          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pi          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_pd          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_di          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_ix          , 
+	(void*)m68k_op_subq_32_aw          , 
+	(void*)m68k_op_subq_32_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_sle_8_d             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_dble_16             , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_ai            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi            , 
+	(void*)m68k_op_sle_8_pi7           , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd            , 
+	(void*)m68k_op_sle_8_pd7           , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_di            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_ix            , 
+	(void*)m68k_op_sle_8_aw            , 
+	(void*)m68k_op_sle_8_al            , 
+	(void*)m68k_op_traple_16           , 
+	(void*)m68k_op_traple_32           , 
+	(void*)m68k_op_traple              , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bra_16              , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_8               , 
+	(void*)m68k_op_bra_32              , 
+	(void*)m68k_op_bsr_16              , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_8               , 
+	(void*)m68k_op_bsr_32              , 
+	(void*)m68k_op_bhi_16              , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_8               , 
+	(void*)m68k_op_bhi_32              , 
+	(void*)m68k_op_bls_16              , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_8               , 
+	(void*)m68k_op_bls_32              , 
+	(void*)m68k_op_bcc_16              , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_8               , 
+	(void*)m68k_op_bcc_32              , 
+	(void*)m68k_op_bcs_16              , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_8               , 
+	(void*)m68k_op_bcs_32              , 
+	(void*)m68k_op_bne_16              , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_8               , 
+	(void*)m68k_op_bne_32              , 
+	(void*)m68k_op_beq_16              , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_8               , 
+	(void*)m68k_op_beq_32              , 
+	(void*)m68k_op_bvc_16              , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_8               , 
+	(void*)m68k_op_bvc_32              , 
+	(void*)m68k_op_bvs_16              , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_8               , 
+	(void*)m68k_op_bvs_32              , 
+	(void*)m68k_op_bpl_16              , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_8               , 
+	(void*)m68k_op_bpl_32              , 
+	(void*)m68k_op_bmi_16              , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_8               , 
+	(void*)m68k_op_bmi_32              , 
+	(void*)m68k_op_bge_16              , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_8               , 
+	(void*)m68k_op_bge_32              , 
+	(void*)m68k_op_blt_16              , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_8               , 
+	(void*)m68k_op_blt_32              , 
+	(void*)m68k_op_bgt_16              , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_8               , 
+	(void*)m68k_op_bgt_32              , 
+	(void*)m68k_op_ble_16              , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_8               , 
+	(void*)m68k_op_ble_32              , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_moveq_32            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm           , 
+	(void*)m68k_op_sbcd_8_mm_ay7       , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm          , 
+	(void*)m68k_op_pack_16_mm_ay7      , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm          , 
+	(void*)m68k_op_unpk_16_mm_ay7      , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_or_8_er_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_ai          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi          , 
+	(void*)m68k_op_or_8_er_pi7         , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd          , 
+	(void*)m68k_op_or_8_er_pd7         , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_di          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_ix          , 
+	(void*)m68k_op_or_8_er_aw          , 
+	(void*)m68k_op_or_8_er_al          , 
+	(void*)m68k_op_or_8_er_pcdi        , 
+	(void*)m68k_op_or_8_er_pcix        , 
+	(void*)m68k_op_or_8_er_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_or_16_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_ai         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pi         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_pd         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_di         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_ix         , 
+	(void*)m68k_op_or_16_er_aw         , 
+	(void*)m68k_op_or_16_er_al         , 
+	(void*)m68k_op_or_16_er_pcdi       , 
+	(void*)m68k_op_or_16_er_pcix       , 
+	(void*)m68k_op_or_16_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_or_32_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_ai         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pi         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_pd         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_di         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_ix         , 
+	(void*)m68k_op_or_32_er_aw         , 
+	(void*)m68k_op_or_32_er_al         , 
+	(void*)m68k_op_or_32_er_pcdi       , 
+	(void*)m68k_op_or_32_er_pcix       , 
+	(void*)m68k_op_or_32_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_divu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_ai          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pi          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_pd          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_di          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_ix          , 
+	(void*)m68k_op_divu_16_aw          , 
+	(void*)m68k_op_divu_16_al          , 
+	(void*)m68k_op_divu_16_pcdi        , 
+	(void*)m68k_op_divu_16_pcix        , 
+	(void*)m68k_op_divu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_rr           , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_ax7       , 
+	(void*)m68k_op_sbcd_8_mm_axy7      , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_ai          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi          , 
+	(void*)m68k_op_or_8_re_pi7         , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd          , 
+	(void*)m68k_op_or_8_re_pd7         , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_di          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_ix          , 
+	(void*)m68k_op_or_8_re_aw          , 
+	(void*)m68k_op_or_8_re_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_rr          , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_ax7      , 
+	(void*)m68k_op_pack_16_mm_axy7     , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_ai         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pi         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_pd         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_di         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_ix         , 
+	(void*)m68k_op_or_16_re_aw         , 
+	(void*)m68k_op_or_16_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_rr          , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_ax7      , 
+	(void*)m68k_op_unpk_16_mm_axy7     , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_ai         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pi         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_pd         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_di         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_ix         , 
+	(void*)m68k_op_or_32_re_aw         , 
+	(void*)m68k_op_or_32_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_divs_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_ai          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pi          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_pd          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_di          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_ix          , 
+	(void*)m68k_op_divs_16_aw          , 
+	(void*)m68k_op_divs_16_al          , 
+	(void*)m68k_op_divs_16_pcdi        , 
+	(void*)m68k_op_divs_16_pcix        , 
+	(void*)m68k_op_divs_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm           , 
+	(void*)m68k_op_subx_8_mm_ay7       , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_sub_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_ai         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi         , 
+	(void*)m68k_op_sub_8_er_pi7        , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd         , 
+	(void*)m68k_op_sub_8_er_pd7        , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_di         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_ix         , 
+	(void*)m68k_op_sub_8_er_aw         , 
+	(void*)m68k_op_sub_8_er_al         , 
+	(void*)m68k_op_sub_8_er_pcdi       , 
+	(void*)m68k_op_sub_8_er_pcix       , 
+	(void*)m68k_op_sub_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_d         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_a         , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_ai        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pi        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_pd        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_di        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_ix        , 
+	(void*)m68k_op_sub_16_er_aw        , 
+	(void*)m68k_op_sub_16_er_al        , 
+	(void*)m68k_op_sub_16_er_pcdi      , 
+	(void*)m68k_op_sub_16_er_pcix      , 
+	(void*)m68k_op_sub_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_d         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_a         , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_ai        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pi        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_pd        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_di        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_ix        , 
+	(void*)m68k_op_sub_32_er_aw        , 
+	(void*)m68k_op_sub_32_er_al        , 
+	(void*)m68k_op_sub_32_er_pcdi      , 
+	(void*)m68k_op_sub_32_er_pcix      , 
+	(void*)m68k_op_sub_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_d           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_a           , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_ai          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pi          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_pd          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_di          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_ix          , 
+	(void*)m68k_op_suba_16_aw          , 
+	(void*)m68k_op_suba_16_al          , 
+	(void*)m68k_op_suba_16_pcdi        , 
+	(void*)m68k_op_suba_16_pcix        , 
+	(void*)m68k_op_suba_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_rr           , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_ax7       , 
+	(void*)m68k_op_subx_8_mm_axy7      , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_ai         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi         , 
+	(void*)m68k_op_sub_8_re_pi7        , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd         , 
+	(void*)m68k_op_sub_8_re_pd7        , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_di         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_ix         , 
+	(void*)m68k_op_sub_8_re_aw         , 
+	(void*)m68k_op_sub_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_rr          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_subx_16_mm          , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_ai        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pi        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_pd        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_di        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_ix        , 
+	(void*)m68k_op_sub_16_re_aw        , 
+	(void*)m68k_op_sub_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_rr          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_subx_32_mm          , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_ai        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pi        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_pd        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_di        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_ix        , 
+	(void*)m68k_op_sub_32_re_aw        , 
+	(void*)m68k_op_sub_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_d           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_a           , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_ai          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pi          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_pd          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_di          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_ix          , 
+	(void*)m68k_op_suba_32_aw          , 
+	(void*)m68k_op_suba_32_al          , 
+	(void*)m68k_op_suba_32_pcdi        , 
+	(void*)m68k_op_suba_32_pcix        , 
+	(void*)m68k_op_suba_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_1010                , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8              , 
+	(void*)m68k_op_cmpm_8_ay7          , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_cmp_8_d             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_ai            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi            , 
+	(void*)m68k_op_cmp_8_pi7           , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd            , 
+	(void*)m68k_op_cmp_8_pd7           , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_di            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_ix            , 
+	(void*)m68k_op_cmp_8_aw            , 
+	(void*)m68k_op_cmp_8_al            , 
+	(void*)m68k_op_cmp_8_pcdi          , 
+	(void*)m68k_op_cmp_8_pcix          , 
+	(void*)m68k_op_cmp_8_i             , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_d            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_a            , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_ai           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pi           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_pd           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_di           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_ix           , 
+	(void*)m68k_op_cmp_16_aw           , 
+	(void*)m68k_op_cmp_16_al           , 
+	(void*)m68k_op_cmp_16_pcdi         , 
+	(void*)m68k_op_cmp_16_pcix         , 
+	(void*)m68k_op_cmp_16_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_d            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_a            , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_ai           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pi           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_pd           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_di           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_ix           , 
+	(void*)m68k_op_cmp_32_aw           , 
+	(void*)m68k_op_cmp_32_al           , 
+	(void*)m68k_op_cmp_32_pcdi         , 
+	(void*)m68k_op_cmp_32_pcix         , 
+	(void*)m68k_op_cmp_32_i            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_d           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_a           , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_ai          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pi          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_pd          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_di          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_ix          , 
+	(void*)m68k_op_cmpa_16_aw          , 
+	(void*)m68k_op_cmpa_16_al          , 
+	(void*)m68k_op_cmpa_16_pcdi        , 
+	(void*)m68k_op_cmpa_16_pcix        , 
+	(void*)m68k_op_cmpa_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_eor_8_d             , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_ax7          , 
+	(void*)m68k_op_cmpm_8_axy7         , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_ai            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi            , 
+	(void*)m68k_op_eor_8_pi7           , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd            , 
+	(void*)m68k_op_eor_8_pd7           , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_di            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_ix            , 
+	(void*)m68k_op_eor_8_aw            , 
+	(void*)m68k_op_eor_8_al            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_eor_16_d            , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_cmpm_16             , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_ai           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pi           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_pd           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_di           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_ix           , 
+	(void*)m68k_op_eor_16_aw           , 
+	(void*)m68k_op_eor_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_eor_32_d            , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_cmpm_32             , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_ai           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pi           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_pd           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_di           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_ix           , 
+	(void*)m68k_op_eor_32_aw           , 
+	(void*)m68k_op_eor_32_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_d           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_a           , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_ai          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pi          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_pd          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_di          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_ix          , 
+	(void*)m68k_op_cmpa_32_aw          , 
+	(void*)m68k_op_cmpa_32_al          , 
+	(void*)m68k_op_cmpa_32_pcdi        , 
+	(void*)m68k_op_cmpa_32_pcix        , 
+	(void*)m68k_op_cmpa_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm           , 
+	(void*)m68k_op_abcd_8_mm_ay7       , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_and_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_ai         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi         , 
+	(void*)m68k_op_and_8_er_pi7        , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd         , 
+	(void*)m68k_op_and_8_er_pd7        , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_di         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_ix         , 
+	(void*)m68k_op_and_8_er_aw         , 
+	(void*)m68k_op_and_8_er_al         , 
+	(void*)m68k_op_and_8_er_pcdi       , 
+	(void*)m68k_op_and_8_er_pcix       , 
+	(void*)m68k_op_and_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_and_16_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_ai        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pi        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_pd        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_di        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_ix        , 
+	(void*)m68k_op_and_16_er_aw        , 
+	(void*)m68k_op_and_16_er_al        , 
+	(void*)m68k_op_and_16_er_pcdi      , 
+	(void*)m68k_op_and_16_er_pcix      , 
+	(void*)m68k_op_and_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_and_32_er_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_ai        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pi        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_pd        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_di        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_ix        , 
+	(void*)m68k_op_and_32_er_aw        , 
+	(void*)m68k_op_and_32_er_al        , 
+	(void*)m68k_op_and_32_er_pcdi      , 
+	(void*)m68k_op_and_32_er_pcix      , 
+	(void*)m68k_op_and_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_mulu_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_ai          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pi          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_pd          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_di          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_ix          , 
+	(void*)m68k_op_mulu_16_aw          , 
+	(void*)m68k_op_mulu_16_al          , 
+	(void*)m68k_op_mulu_16_pcdi        , 
+	(void*)m68k_op_mulu_16_pcix        , 
+	(void*)m68k_op_mulu_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_rr           , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_ax7       , 
+	(void*)m68k_op_abcd_8_mm_axy7      , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_ai         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi         , 
+	(void*)m68k_op_and_8_re_pi7        , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd         , 
+	(void*)m68k_op_and_8_re_pd7        , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_di         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_ix         , 
+	(void*)m68k_op_and_8_re_aw         , 
+	(void*)m68k_op_and_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_dd           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_exg_32_aa           , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_ai        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pi        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_pd        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_di        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_ix        , 
+	(void*)m68k_op_and_16_re_aw        , 
+	(void*)m68k_op_and_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_exg_32_da           , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_ai        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pi        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_pd        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_di        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_ix        , 
+	(void*)m68k_op_and_32_re_aw        , 
+	(void*)m68k_op_and_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_muls_16_d           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_ai          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pi          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_pd          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_di          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_ix          , 
+	(void*)m68k_op_muls_16_aw          , 
+	(void*)m68k_op_muls_16_al          , 
+	(void*)m68k_op_muls_16_pcdi        , 
+	(void*)m68k_op_muls_16_pcix        , 
+	(void*)m68k_op_muls_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm           , 
+	(void*)m68k_op_addx_8_mm_ay7       , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_add_8_er_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_ai         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi         , 
+	(void*)m68k_op_add_8_er_pi7        , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd         , 
+	(void*)m68k_op_add_8_er_pd7        , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_di         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_ix         , 
+	(void*)m68k_op_add_8_er_aw         , 
+	(void*)m68k_op_add_8_er_al         , 
+	(void*)m68k_op_add_8_er_pcdi       , 
+	(void*)m68k_op_add_8_er_pcix       , 
+	(void*)m68k_op_add_8_er_i          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_d         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_a         , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_ai        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pi        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_pd        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_di        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_ix        , 
+	(void*)m68k_op_add_16_er_aw        , 
+	(void*)m68k_op_add_16_er_al        , 
+	(void*)m68k_op_add_16_er_pcdi      , 
+	(void*)m68k_op_add_16_er_pcix      , 
+	(void*)m68k_op_add_16_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_d         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_a         , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_ai        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pi        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_pd        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_di        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_ix        , 
+	(void*)m68k_op_add_32_er_aw        , 
+	(void*)m68k_op_add_32_er_al        , 
+	(void*)m68k_op_add_32_er_pcdi      , 
+	(void*)m68k_op_add_32_er_pcix      , 
+	(void*)m68k_op_add_32_er_i         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_d           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_a           , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_ai          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pi          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_pd          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_di          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_ix          , 
+	(void*)m68k_op_adda_16_aw          , 
+	(void*)m68k_op_adda_16_al          , 
+	(void*)m68k_op_adda_16_pcdi        , 
+	(void*)m68k_op_adda_16_pcix        , 
+	(void*)m68k_op_adda_16_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_rr           , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_ax7       , 
+	(void*)m68k_op_addx_8_mm_axy7      , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_ai         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi         , 
+	(void*)m68k_op_add_8_re_pi7        , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd         , 
+	(void*)m68k_op_add_8_re_pd7        , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_di         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_ix         , 
+	(void*)m68k_op_add_8_re_aw         , 
+	(void*)m68k_op_add_8_re_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_rr          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_addx_16_mm          , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_ai        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pi        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_pd        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_di        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_ix        , 
+	(void*)m68k_op_add_16_re_aw        , 
+	(void*)m68k_op_add_16_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_rr          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_addx_32_mm          , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_ai        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pi        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_pd        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_di        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_ix        , 
+	(void*)m68k_op_add_32_re_aw        , 
+	(void*)m68k_op_add_32_re_al        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_d           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_a           , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_ai          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pi          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_pd          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_di          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_ix          , 
+	(void*)m68k_op_adda_32_aw          , 
+	(void*)m68k_op_adda_32_al          , 
+	(void*)m68k_op_adda_32_pcdi        , 
+	(void*)m68k_op_adda_32_pcix        , 
+	(void*)m68k_op_adda_32_i           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_ai           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pi           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_pd           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_di           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_ix           , 
+	(void*)m68k_op_asr_16_aw           , 
+	(void*)m68k_op_asr_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_ai           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pi           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_pd           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_di           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_ix           , 
+	(void*)m68k_op_asl_16_aw           , 
+	(void*)m68k_op_asl_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_ai           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pi           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_pd           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_di           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_ix           , 
+	(void*)m68k_op_lsr_16_aw           , 
+	(void*)m68k_op_lsr_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_ai           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pi           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_pd           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_di           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_ix           , 
+	(void*)m68k_op_lsl_16_aw           , 
+	(void*)m68k_op_lsl_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_ai          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pi          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_pd          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_di          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_ix          , 
+	(void*)m68k_op_roxr_16_aw          , 
+	(void*)m68k_op_roxr_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_ai          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pi          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_pd          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_di          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_ix          , 
+	(void*)m68k_op_roxl_16_aw          , 
+	(void*)m68k_op_roxl_16_al          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_ai           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pi           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_pd           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_di           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_ix           , 
+	(void*)m68k_op_ror_16_aw           , 
+	(void*)m68k_op_ror_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_ai           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pi           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_pd           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_di           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_ix           , 
+	(void*)m68k_op_rol_16_aw           , 
+	(void*)m68k_op_rol_16_al           , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_bftst_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_bftst_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_di         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_ix         , 
+	(void*)m68k_op_bftst_32_aw         , 
+	(void*)m68k_op_bftst_32_al         , 
+	(void*)m68k_op_bftst_32_pcdi       , 
+	(void*)m68k_op_bftst_32_pcix       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_bfextu_32_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_bfextu_32_ai        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_di        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_ix        , 
+	(void*)m68k_op_bfextu_32_aw        , 
+	(void*)m68k_op_bfextu_32_al        , 
+	(void*)m68k_op_bfextu_32_pcdi      , 
+	(void*)m68k_op_bfextu_32_pcix      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_bfchg_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_bfchg_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_di         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_ix         , 
+	(void*)m68k_op_bfchg_32_aw         , 
+	(void*)m68k_op_bfchg_32_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_bfexts_32_d         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_bfexts_32_ai        , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_di        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_ix        , 
+	(void*)m68k_op_bfexts_32_aw        , 
+	(void*)m68k_op_bfexts_32_al        , 
+	(void*)m68k_op_bfexts_32_pcdi      , 
+	(void*)m68k_op_bfexts_32_pcix      , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_bfclr_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_bfclr_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_di         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_ix         , 
+	(void*)m68k_op_bfclr_32_aw         , 
+	(void*)m68k_op_bfclr_32_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_bfffo_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_bfffo_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_di         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_ix         , 
+	(void*)m68k_op_bfffo_32_aw         , 
+	(void*)m68k_op_bfffo_32_al         , 
+	(void*)m68k_op_bfffo_32_pcdi       , 
+	(void*)m68k_op_bfffo_32_pcix       , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_asr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_lsr_8_s             , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_roxr_8_s            , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_ror_8_s             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_asr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_lsr_8_r             , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_roxr_8_r            , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_ror_8_r             , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_asr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_lsr_16_s            , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_roxr_16_s           , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_ror_16_s            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_asr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_lsr_16_r            , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_roxr_16_r           , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_ror_16_r            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_asr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_lsr_32_s            , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_roxr_32_s           , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_ror_32_s            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_asr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_lsr_32_r            , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_roxr_32_r           , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_ror_32_r            , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_bfset_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_bfset_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_di         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_ix         , 
+	(void*)m68k_op_bfset_32_aw         , 
+	(void*)m68k_op_bfset_32_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_asl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_lsl_8_s             , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_roxl_8_s            , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_rol_8_s             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_asl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_lsl_8_r             , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_roxl_8_r            , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_rol_8_r             , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_asl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_lsl_16_s            , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_roxl_16_s           , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_rol_16_s            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_asl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_lsl_16_r            , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_roxl_16_r           , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_rol_16_r            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_asl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_lsl_32_s            , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_roxl_32_s           , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_rol_32_s            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_asl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_lsl_32_r            , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_roxl_32_r           , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_rol_32_r            , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_bfins_32_d          , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_bfins_32_ai         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_di         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_ix         , 
+	(void*)m68k_op_bfins_32_aw         , 
+	(void*)m68k_op_bfins_32_al         , 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_illegal, 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpgen_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpdbcc_32           , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cpscc_32            , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cptrapcc_32         , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_cpbcc_32            , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 
+	(void*)m68k_op_1111                , 	
+};
+
+
diff --git a/MCUME_pico2/picogenold/macros.h b/MCUME_pico2/picogenold/macros.h
new file mode 100644
index 0000000..15762f7
--- /dev/null
+++ b/MCUME_pico2/picogenold/macros.h
@@ -0,0 +1,24 @@
+
+#ifndef _MACROS_H_
+#define _MACROS_H_
+
+
+#define READ_BYTE(BASE, ADDR) (BASE)[(ADDR)^1]
+#define READ_WORD(BASE, ADDR) (((BASE)[(ADDR)+1]<<8) |          \
+                              (BASE)[(ADDR)])
+#define READ_LONG(BASE, ADDR) (((BASE)[(ADDR)+1]<<24) |         \
+                               ((BASE)[(ADDR)+0]<<16) |      \
+                               ((BASE)[(ADDR)+3]<<8) |       \
+                                (BASE)[(ADDR)+2])
+
+#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[(ADDR)^1] = (VAL)&0xff
+#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[(ADDR)+1] = ((VAL)>>8) & 0xff;       \
+                                    (BASE)[ADDR] = (VAL)&0xff
+#define WRITE_LONG(BASE, ADDR, VAL) (BASE)[(ADDR)+1] = ((VAL)>>24) & 0xff;      \
+                                    (BASE)[(ADDR)+0] = ((VAL)>>16)&0xff;    \
+                                    (BASE)[(ADDR)+3] = ((VAL)>>8)&0xff;     \
+                                    (BASE)[(ADDR)+2] = (VAL)&0xff
+
+
+#endif /* _MACROS_H_ */
+
diff --git a/MCUME_pico2/picogenold/mem68k.c b/MCUME_pico2/picogenold/mem68k.c
new file mode 100644
index 0000000..bb2c262
--- /dev/null
+++ b/MCUME_pico2/picogenold/mem68k.c
@@ -0,0 +1,715 @@
+
+#include "shared.h"
+
+unsigned int m68k_read_bus_8(unsigned int address)
+{
+    uint16 temp = m68k_read_bus_16(address);
+    return ((address & 1) ? (temp & 0xFF) : (temp >> 8));
+}
+
+unsigned int m68k_read_bus_16(unsigned int address)
+{
+    uint16 temp = 0x4e71;
+
+    if(address >= 0xC00000)
+    {
+        return (temp);
+    }
+    else
+    {
+        return (temp & 0xFF00);
+    }
+}
+
+void m68k_unused_w(unsigned int address, unsigned int value)
+{
+//error("Unused %08X = %08X (%08X)\n", address, value, Turbo68KReadPC());
+}
+
+void m68k_unused_8_w(unsigned int address, unsigned int value)
+{
+//error("Unused %08X = %02X (%08X)\n", address, value, Turbo68KReadPC());
+}
+
+void m68k_unused_16_w(unsigned int address, unsigned int value)
+{
+//error("Unused %08X = %04X (%08X)\n", address, value, Turbo68KReadPC());
+}
+
+/*
+    Functions to handle memory accesses which cause the Genesis to halt
+    either temporarily (press RESET button to restart) or unrecoverably
+    (cycle power to restart).
+*/
+
+void m68k_lockup_w_8(unsigned int address, unsigned int value)
+{
+    error("Lockup %08X = %02X (%08X)\n", address, value, m68k_get_reg(NULL, M68K_REG_PC));
+    gen_running = 0;
+    m68k_end_timeslice();
+}
+
+void m68k_lockup_w_16(unsigned int address, unsigned int value)
+{
+    error("Lockup %08X = %04X (%08X)\n", address, value, m68k_get_reg(NULL, M68K_REG_PC));
+    gen_running = 0;
+    m68k_end_timeslice();
+}
+
+unsigned int m68k_lockup_r_8(unsigned int address)
+{
+    error("Lockup %08X.b (%08X)\n", address, m68k_get_reg(NULL, M68K_REG_PC));
+    gen_running = 0;
+    m68k_end_timeslice();
+    return -1;
+}
+
+unsigned int m68k_lockup_r_16(unsigned int address)
+{
+    error("Lockup %08X.w (%08X)\n", address, m68k_get_reg(NULL, M68K_REG_PC));
+    gen_running = 0;
+    m68k_end_timeslice();
+    return -1;
+}
+
+/*--------------------------------------------------------------------------*/
+/* 68000 memory handlers                                                    */
+/*--------------------------------------------------------------------------*/
+
+unsigned int m68k_read_memory_8(unsigned int address)
+{
+    switch((address >> 21) & 7)
+    {
+        case 0: /* ROM */
+        case 1:
+            return readb_swap_rom(address);
+
+        case 7: /* RAM */
+            return READ_BYTE(work_ram, address & 0xFFFF);
+
+        case 5: /* Z80 & I/O */
+            if(address <= 0xA0FFFF)
+            {
+                if(zbusack == 1)
+                {
+                    /* Z80 controls Z bus */
+                    return (m68k_read_bus_8(address));
+                }
+                else
+                {
+                    /* Read data from Z bus */
+                    switch(address & 0x6000)
+                    {
+                        case 0x0000: /* RAM */
+                        case 0x2000:
+                            return (zram[(address & 0x1FFF)]);
+    
+                        case 0x4000: /* YM2612 */
+                            return (fm_read(address & 3));
+
+                        case 0x6000: /* Unused */
+                            switch(address & 0xFF00)
+                            {
+                                case 0x7F00: /* VDP */
+                                    m68k_lockup_r_8(address);
+        
+                                default: /* Unused */
+                                    return (0xFF);
+                            }
+                            break;
+                    }
+                }
+            }
+            else
+            {
+                switch((address >> 8) & 0xFF)
+                {
+                    case 0x00: /* I/O CHIP */
+                        if(address <= 0xA1001F)
+                        {
+                            return (gen_io_r((address >> 1) & 0x0F));
+                        }
+                        else
+                        {
+                            return (m68k_read_bus_8(address));
+                        }
+                        break;
+
+                    case 0x10: /* MEMORY MODE */
+                        return (m68k_read_bus_8(address));
+
+                    case 0x11: /* BUSACK */
+                        if((address & 1) == 0)
+                        {
+                            return (gen_busack_r() | (m68k_read_bus_8(address) & 0xFE));
+                        }
+                        else
+                        return (m68k_read_bus_8(address));
+
+                    case 0x12: /* RESET */
+                        return (m68k_read_bus_8(address));
+
+                    case 0x13: /* TIME */
+                        return (m68k_read_bus_8(address));
+                                                           
+                    case 0x20: /* UNKNOWN */
+                        return (m68k_read_bus_8(address));
+
+                    case 0x30: /* UNKNOWN */
+                        return (m68k_read_bus_8(address));
+
+                    default: /* Unused */
+                        return (m68k_lockup_r_8(address));
+                }
+            }
+            break;
+
+        case 6: /* VDP */
+            if((address & 0xE700E0) == 0xC00000)
+            {
+                switch(address & 0x1F)
+                {
+                    case 0x00: /* DATA */
+                    case 0x02:
+                        return (vdp_data_r() >> 8);
+
+                    case 0x01: /* DATA */
+                    case 0x03:
+                        return (vdp_data_r() & 0xFF);
+
+                    case 0x04: /* CTRL */
+                    case 0x06:
+                        return ((m68k_read_bus_8(address) & 0xFC) | (vdp_ctrl_r() >> 8));
+
+                    case 0x05: /* CTRL */
+                    case 0x07:
+                        return (vdp_ctrl_r() & 0xFF);
+
+                    case 0x08: /* HVC */
+                    case 0x0A:
+                    case 0x0C:
+                    case 0x0E:
+                        return (vdp_hvc_r() >> 8);
+
+                    case 0x09: /* HVC */
+                    case 0x0B:
+                    case 0x0D:
+                    case 0x0F:
+                        return (vdp_hvc_r() & 0xFF);
+
+                    case 0x10: /* PSG */
+                    case 0x11:
+                    case 0x12:
+                    case 0x13:
+                    case 0x14:
+                    case 0x15:
+                    case 0x16:
+                    case 0x17:
+                        return (m68k_lockup_r_8(address));
+
+                    case 0x18: /* Unused */
+                    case 0x19:
+                    case 0x1A:
+                    case 0x1B:
+                    case 0x1C:
+                    case 0x1D:
+                    case 0x1E:
+                    case 0x1F:
+                        return (m68k_read_bus_8(address));
+                }
+            }
+            else
+            {
+                /* Unused */
+                return (m68k_lockup_r_8(address));
+            }
+            break;
+
+        case 2: /* Unused */
+        case 3:
+            return (m68k_read_bus_8(address));
+
+        case 4: /* Unused */
+            return (m68k_lockup_r_8(address));
+    }
+
+    return -1;
+}
+
+
+unsigned int m68k_read_memory_16(unsigned int address)
+{
+    switch((address >> 21) & 7)
+    {
+
+        case 0: /* ROM */
+        case 1:
+            return readw_swap_rom(address);
+
+        case 7: /* RAM */
+            return READ_WORD(work_ram, address & 0xFFFF);
+
+        case 5: /* Z80 & I/O */
+            if(address <= 0xA0FFFF)
+            {
+                if(zbusack == 1)
+                {
+                    return (m68k_read_bus_16(address));
+                }
+                else
+                {
+                    uint8 temp;
+
+                    switch(address & 0x6000)
+                    {
+                        case 0x0000: /* RAM */
+                        case 0x2000:
+                            temp = zram[address & 0x1FFF];
+                            return (temp << 8 | temp);
+    
+                        case 0x4000: /* YM2612 */
+                            temp = fm_read(address & 3);
+                            return (temp << 8 | temp);
+
+                        case 0x6000:
+                            switch(address & 0xFF00)
+                            {
+                                case 0x7F00: /* VDP */
+                                    m68k_lockup_r_16(address);
+        
+                                default: /* Unused */
+                                    return (0xFFFF);
+                            }
+                            break;
+                    }
+                }
+            }
+            else
+            {
+                if(address <= 0xA1001F)
+                {
+                    uint8 temp = gen_io_r((address >> 1) & 0x0F);
+                    return (temp << 8 | temp);
+                }
+                else
+                {
+                    switch((address >> 8) & 0xFF)
+                    {
+                        case 0x10: /* MEMORY MODE */
+                            return (m68k_read_bus_16(address));
+
+                        case 0x11: /* BUSACK */
+                            return ((m68k_read_bus_16(address) & 0xFEFF) | (gen_busack_r() << 8));
+
+                        case 0x12: /* RESET */
+                            return (m68k_read_bus_16(address));
+
+                        case 0x13: /* TIME */
+                            return (m68k_read_bus_16(address));
+
+                        case 0x20: /* UNKNOWN */
+                            return (m68k_read_bus_16(address));
+
+                        case 0x30: /* UNKNOWN */
+                            return (m68k_read_bus_16(address));
+
+                        default: /* Unused */
+                            return (m68k_lockup_r_16(address));
+                    }
+                }
+            }
+            break;
+
+        case 6:
+            if((address & 0xE700E0) == 0xC00000)
+            {
+                switch(address & 0x1F)
+                {
+                    case 0x00: /* DATA */
+                    case 0x02:
+                        return (vdp_data_r());
+
+                    case 0x04: /* CTRL */                  
+                    case 0x06:                             
+                        return (vdp_ctrl_r() | (m68k_read_bus_16(address) & 0xFC00));
+
+                    case 0x08: /* HVC */
+                    case 0x0A:
+                    case 0x0C:
+                    case 0x0E:
+                        return (vdp_hvc_r());
+
+                    case 0x10: /* PSG */
+                    case 0x12:
+                    case 0x14:
+                    case 0x16:
+                        return (m68k_lockup_r_16(address));
+
+                    case 0x18: /* Unused */
+                    case 0x1A:
+                    case 0x1C:
+                    case 0x1E:
+                        return (m68k_read_bus_16(address));
+                }
+            }
+            else
+            {
+                return (m68k_lockup_r_16(address));
+            }
+            break;
+
+        case 2:
+        case 3:
+            return (m68k_read_bus_16(address));
+
+        case 4:
+            return (m68k_lockup_r_16(address));
+    }
+
+    return (0xA5A5);
+}
+
+
+unsigned int m68k_read_memory_32(unsigned int address)
+{
+    /* Split into 2 reads */
+    return (m68k_read_memory_16(address + 0) << 16 | m68k_read_memory_16(address + 2));
+}
+
+
+void m68k_write_memory_8(unsigned int address, unsigned int value)
+{
+    switch((address >> 21) & 7)
+    {
+        case 7:
+            WRITE_BYTE(work_ram, address & 0xFFFF, value);
+            return;
+
+        case 6:
+            if((address & 0xE700E0) == 0xC00000)
+            {
+                switch(address & 0x1F)
+                {
+                    case 0x00: /* DATA */
+                    case 0x01:
+                    case 0x02:
+                    case 0x03:
+                        vdp_data_w(value << 8 | value);
+                        return;
+
+                    case 0x04: /* CTRL */
+                    case 0x05:
+                    case 0x06:
+                    case 0x07:
+                        vdp_ctrl_w(value << 8 | value);
+                        return;
+
+                    case 0x08: /* HVC */
+                    case 0x09:
+                    case 0x0A:
+                    case 0x0B:
+                    case 0x0C:
+                    case 0x0D:
+                    case 0x0E:
+                    case 0x0F:
+                        m68k_lockup_w_8(address, value);
+                        return;
+
+                    case 0x10: /* PSG */
+                    case 0x12:
+                    case 0x14:
+                    case 0x16:
+                        m68k_unused_8_w(address, value);
+                        return;
+
+                    case 0x11: /* PSG */
+                    case 0x13:
+                    case 0x15:
+                    case 0x17:
+                        psg_write(value);
+                        return;
+
+                    case 0x18: /* Unused */
+                    case 0x19:
+                    case 0x1A:
+                    case 0x1B:
+                    case 0x1C:
+                    case 0x1D:
+                    case 0x1E:
+                    case 0x1F:
+                        m68k_unused_8_w(address, value);
+                        return;
+                }
+            }
+            else
+            {
+                m68k_lockup_w_8(address, value);
+                return;
+            }
+
+        case 5:
+            if(address <= 0xA0FFFF)
+            {
+                if(zbusack == 1)
+                {
+                    m68k_unused_8_w(address, value);
+                    return;
+                }
+                else
+                {
+                    switch(address & 0x6000)
+                    {
+                        case 0x0000:
+                        case 0x2000:
+                            zram[(address & 0x1FFF)] = value;
+                            return;
+    
+                        case 0x4000:
+                            fm_write(address & 3, value);
+                            return;
+
+                        case 0x6000:
+                            switch(address & 0xFF00)
+                            {
+                                case 0x6000: /* BANK */
+                                    gen_bank_w(value & 1);
+                                    return;
+
+                                case 0x7F00: /* VDP */
+                                    m68k_lockup_w_8(address, value);
+                                    return;
+
+                                default: /* Unused */
+                                    m68k_unused_8_w(address, value);
+                                    return;
+                            }
+                            break;
+                    }
+                }
+            }
+            else
+            {
+                if(address <= 0xA1001F)
+                {
+                    /* I/O chip only gets /LWR */
+                    if(address & 1)
+                        gen_io_w((address >> 1) & 0x0F, value);
+                    return;
+                }
+                else
+                {
+                    /* Bus control chip registers */
+                    switch((address >> 8) & 0xFF)
+                    {
+                        case 0x10: /* MEMORY MODE */
+                            m68k_unused_8_w(address, value);
+                            return;
+
+                        case 0x11: /* BUSREQ */
+                            if((address & 1) == 0)
+                            {
+                                gen_busreq_w(value & 1);
+                            }
+                            else
+                            {
+                                m68k_unused_8_w(address, value);
+                            }
+                            return;
+
+                        case 0x12: /* RESET */
+                            gen_reset_w(value & 1);
+                            return;
+
+                        case 0x13: /* TIME */
+                            m68k_unused_8_w(address, value);
+                            return;
+
+                        case 0x20: /* UNKNOWN */
+                            m68k_unused_8_w(address, value);
+                            return;
+
+                        case 0x30: /* UNKNOWN */
+                            m68k_unused_8_w(address, value);
+                            return;
+
+                        default: /* Unused */
+                            m68k_lockup_w_8(address, value);
+                            return;
+                    }
+                }
+            }
+            break;
+
+
+        case 0: /* ROM */
+        case 1: /* ROM */
+            m68k_unused_8_w(address, value);
+            return;
+
+        case 2: /* Unused */
+        case 3:           
+            m68k_unused_8_w(address, value);
+            return;
+
+        case 4: /* Unused */
+            m68k_lockup_w_8(address, value);
+            return;
+    }
+
+}
+
+
+
+
+void m68k_write_memory_16(unsigned int address, unsigned int value)
+{
+    switch((address >> 21) & 7)
+    {
+        case 0: /* ROM */
+        case 1: /* ROM */
+            m68k_unused_16_w(address, value);
+            return;
+
+        case 2: /* Unused */
+        case 3:           
+            m68k_unused_16_w(address, value);
+            return;
+
+        case 4: /* Unused */
+            m68k_lockup_w_16(address, value);
+            return;
+
+        case 5: /* Z80 area, I/O chip, miscellaneous. */
+            if(address <= 0xA0FFFF)
+            {
+                /* Writes are ignored when the Z80 hogs the Z-bus */
+                if(zbusack == 1) {
+                    m68k_unused_8_w(address, value);
+                    return;
+                }
+
+                /* Write into Z80 address space */
+                switch(address & 0x6000)
+                {
+                    case 0x0000: /* Work RAM */
+                    case 0x2000: /* Work RAM */
+                        zram[(address & 0x1FFF)] = (value >> 8) & 0xFF;
+                        return;
+    
+                    case 0x4000: /* YM2612 */
+                        fm_write(address & 3, (value >> 8) & 0xFF);
+                        return;
+
+                    case 0x6000: /* Bank register and VDP */
+                        switch(address & 0x7F00)
+                        {
+                            case 0x6000: /* Bank register */
+                                gen_bank_w((value >> 8) & 1);
+                                return;
+
+                             case 0x7F00: /* VDP registers */
+                                m68k_lockup_w_16(address, value);
+                                return;
+
+                             default: /* Unused */
+                                m68k_unused_8_w(address, value);
+                                return;
+                        }
+                        break;
+                }
+            }
+            else
+            {
+                /* I/O chip */
+                if(address <= 0xA1001F)
+                {
+                    gen_io_w((address >> 1) & 0x0F, value & 0x00FF);
+                    return;
+                }
+                else
+                {
+                    /* Bus control chip registers */
+                    switch((address >> 8) & 0xFF)
+                    {
+                        case 0x10: /* MEMORY MODE */
+                            m68k_unused_16_w(address, value);
+                            return;
+
+                        case 0x11: /* BUSREQ */
+                            gen_busreq_w((value >> 8) & 1);
+                            return;
+
+                        case 0x12: /* RESET */
+                            gen_reset_w((value >> 8) & 1);
+                            return;
+
+                        case 0x13: /* TIME */
+                            m68k_unused_16_w(address, value);
+                            return;
+
+                        case 0x20: /* UNKNOWN */
+                            m68k_unused_16_w(address, value);
+                            return;
+
+                        case 0x30: /* UNKNOWN */
+                            m68k_unused_16_w(address, value);
+                            return;
+
+                        default: /* Unused */
+                            m68k_lockup_w_16(address, value);
+                            return;
+                    }
+                }
+            }
+            break;
+
+        case 6: /* VDP */
+            if((address & 0xE700E0) == 0xC00000)
+            {
+                switch(address & 0x1C)
+                {
+                    case 0x00: /* DATA */
+                        vdp_data_w(value);
+                        return;
+
+                    case 0x04: /* CTRL */
+                        vdp_ctrl_w(value);
+                        return;
+
+                    case 0x08: /* HV counter */
+                    case 0x0C: /* HV counter */
+                        m68k_lockup_w_16(address, value);
+                        return;
+
+                    case 0x10: /* PSG */
+                    case 0x14: /* PSG */
+                        psg_write(value & 0xFF);
+                        return;
+
+                    case 0x18: /* Unused */
+                    case 0x1C: /* Unused */
+                        m68k_unused_8_w(address, value);
+                        return;
+                }
+            }
+            else
+            {
+                /* Invalid address */
+                m68k_lockup_w_16(address, value);
+            }
+            break;
+
+        case 7: /* Work RAM */
+            WRITE_WORD(work_ram, address & 0xFFFF, value);
+            return;
+    }
+}
+
+
+void m68k_write_memory_32(unsigned int address, unsigned int value)
+{
+    /* Split into 2 writes */
+    m68k_write_memory_16(address, (value >> 16) & 0xFFFF);
+    m68k_write_memory_16(address + 2, value & 0xFFFF);
+}
+
diff --git a/MCUME_pico2/picogenold/mem68k.h b/MCUME_pico2/picogenold/mem68k.h
new file mode 100644
index 0000000..e9c54bd
--- /dev/null
+++ b/MCUME_pico2/picogenold/mem68k.h
@@ -0,0 +1,15 @@
+
+#ifndef _MEM68K_H_
+#define _MEM68K_H_
+
+/* Function prototypes */
+unsigned int m68k_read_bus_8(unsigned int address);
+unsigned int m68k_read_bus_16(unsigned int address);
+void m68k_unused_w(unsigned int address, unsigned int value);
+
+void m68k_lockup_w_8(unsigned int address, unsigned int value);
+void m68k_lockup_w_16(unsigned int address, unsigned int value);
+unsigned int m68k_lockup_r_8(unsigned int address);
+unsigned int m68k_lockup_r_16(unsigned int address);
+
+#endif /* _MEM68K_H_ */
diff --git a/MCUME_pico2/picogenold/membnk.c b/MCUME_pico2/picogenold/membnk.c
new file mode 100644
index 0000000..f056f57
--- /dev/null
+++ b/MCUME_pico2/picogenold/membnk.c
@@ -0,0 +1,327 @@
+/*
+    membnk.c --
+    Memory handlers Z80 access to the banked V-bus address space.
+*/
+
+#include "shared.h"
+
+
+void z80_write_banked_memory(unsigned int address, unsigned int data)
+{
+    switch((address >> 21) & 7)
+    {
+        case 0: /* Cartridge ROM */
+        case 1:
+            z80bank_unused_w(address, data);
+            return;
+
+        case 2: /* Unused */
+        case 3:
+            z80bank_unused_w(address, data);
+            return;
+
+        case 4: /* Unused (lockup) */
+            z80bank_lockup_w(address, data);
+            return;
+
+        case 5: /* Z80, I/O chip, etc. */
+            if(address <= 0xA0FFFF)
+            {
+                z80bank_lockup_w(address, data);
+                return;
+            }
+            else
+            {
+                switch((address >> 8) & 0xFF)
+                {
+                    case 0x00: /* I/O chip */
+                        if(address <= 0xA1001F)
+                            gen_io_w((address >> 1) & 0x0F, data);
+                        else
+                            z80bank_unused_w(address, data);
+                        return;
+
+                    case 0x10: /* DRAM refresh */
+                        z80bank_unused_w(address, data);
+                        return;
+
+                    case 0x11: /* /BUSREQ */
+                        if(address & 1)
+                            z80bank_unused_w(address, data);
+                        else
+                            gen_busreq_w(data & 1);
+                        return;
+
+                    case 0x12: /* /RESET (w) */
+                        if(address & 1)
+                            z80bank_unused_w(address, data);
+                        else
+                            gen_reset_w(data & 1);
+                        return;
+
+                    case 0x13: /* /TIME region */
+                        z80bank_unused_w(address, data);
+                        return;
+
+                    case 0x20: /* ? */
+                        z80bank_unused_w(address, data);
+                        return;
+
+                    case 0x30: /* ? */
+                        z80bank_unused_w(address, data);
+                        return;
+
+                    default: /* Invalid */
+                        z80bank_lockup_w(address, data);
+                        return;
+                }
+            }
+            return;
+
+        case 6: /* VDP */
+            z80bank_vdp_w(address, data);
+            return;
+
+        case 7: /* Work RAM */
+            WRITE_BYTE(work_ram, address & 0xFFFF, data);
+            return;
+    }
+}
+
+
+int z80_read_banked_memory(unsigned int address)
+{
+    switch((address >> 21) & 7)
+    {
+        case 0: /* Cartridge ROM */
+        case 1:
+            return readb_swap_rom(address);
+
+        case 2: /* Unused */
+        case 3:
+            return z80bank_unused_r(address);
+
+        case 4: /* Unused (lockup) */
+            return z80bank_lockup_r(address);
+
+        case 5: /* Z80, I/O chip, etc.*/
+            if(address <= 0xA0FFFF)
+            {
+                return z80bank_lockup_r(address);
+            }
+            else
+            {
+                switch((address >> 8) & 0xFF)
+                {        
+                    case 0x00: /* I/O chip */
+                        if(address <= 0xA1001F)
+                            return gen_io_r((address >> 1) & 0x0F);
+                        else
+                            return z80bank_unused_r(address);
+                        break;
+
+                    case 0x10: /* Unused */
+                        return z80bank_unused_r(address);
+
+                    case 0x11: /* /BUSACK from Z80 */
+                        /* The Z80 can't read this bit (it would be halted
+                           when the bit was zero) so we always return '1'. */
+                        return 0xFF;
+
+                    case 0x12: /* Unused */
+                        return z80bank_unused_r(address);
+
+                    case 0x13: /* /TIME region */
+                        return z80bank_unused_r(address);
+
+                    case 0x20: /* Unused */
+                        return z80bank_unused_r(address);
+
+                    case 0x30: /* Unused */
+                        return z80bank_unused_r(address);
+
+                    default: /* Lockup */
+                        return z80bank_lockup_r(address);
+                }
+            }
+            break;
+
+        case 6: /* VDP */
+            return z80bank_vdp_r(address);
+
+        case 7: /* Work RAM - can't be read on some Genesis models (!) */
+            return 0xFF;
+    }
+
+    return (-1);
+}
+
+
+void z80bank_vdp_w(int address, int data)
+{
+//    if((address & 0xE700E0) == 0xC00000)
+    if((address & 0xE700E0) == 0xC0000)
+    {
+        switch(address & 0x1F)
+        {
+            case 0x00: /* Data port */
+            case 0x01:
+            case 0x02:
+            case 0x03:
+                vdp_data_w(data << 8 | data);
+                return;
+
+            case 0x04: /* Control port */
+            case 0x05:
+            case 0x06:
+            case 0x07:
+                vdp_ctrl_w(data << 8 | data);
+                return;
+
+            case 0x08: /* Lockup (HVC) */
+            case 0x09:
+            case 0x0A:
+            case 0x0B:
+            case 0x0C:
+            case 0x0D:
+            case 0x0E:
+            case 0x0F:
+                z80bank_lockup_w(address, data);
+                return;
+
+            case 0x10: /* Unused */
+            case 0x12:
+            case 0x14:
+            case 0x16:
+                z80bank_unused_w(address, data);
+                return;
+
+            case 0x11: /* PSG */
+            case 0x13:
+            case 0x15:
+            case 0x17:
+                psg_write(data);
+                return;
+
+            case 0x18: /* Unused */
+            case 0x19:
+            case 0x1A:
+            case 0x1B:
+                z80bank_unused_w(address, data);
+                return;
+
+            case 0x1C: /* Test register */
+            case 0x1D:
+            case 0x1E:
+            case 0x1F:
+                vdp_test_w(data << 8 | data);
+                return;
+        }
+    }
+    else
+    {
+        /* Invalid VDP address */
+        z80bank_lockup_w(address, data);
+        return;
+    }
+}
+
+
+int z80bank_vdp_r(int address)
+{
+//    if((address & 0xE700E0) == 0xC00000)
+    if((address & 0xE700E0) == 0xC0000)
+    {
+        switch(address & 0x1F)
+        {
+            case 0x00: /* Data */
+            case 0x02:
+                return (vdp_data_r() >> 8) & 0xFF;
+
+            case 0x01: /* Data */
+            case 0x03:
+                return vdp_data_r() & 0xFF;
+
+            case 0x04: /* Control */
+            case 0x06:
+                return (0xFC | (vdp_ctrl_r() >> 8)) & 0xFF;
+
+            case 0x05: /* Control */
+            case 0x07:
+                return vdp_ctrl_r() & 0xFF;
+
+            case 0x08: /* HVC */
+            case 0x0A:
+            case 0x0C:
+            case 0x0E:
+                return (vdp_hvc_r() >> 8) & 0xFF;
+
+            case 0x09: /* HVC */
+            case 0x0B:
+            case 0x0D:
+            case 0x0F:
+                return vdp_hvc_r() & 0xFF;
+
+            case 0x10: /* Lockup */
+            case 0x11:
+            case 0x12:
+            case 0x13:
+            case 0x14:
+            case 0x15:
+            case 0x16:
+            case 0x17:
+                return z80bank_lockup_r(address);
+
+            case 0x18: /* Unused */
+            case 0x19:
+            case 0x1A:
+            case 0x1B:
+            case 0x1C:
+            case 0x1D:
+            case 0x1E:
+            case 0x1F:
+                return (z80bank_unused_r(address) | 0xFF);
+        }
+    }
+    else
+    {
+        /* Invalid VDP address */
+        return z80bank_lockup_r(address);
+    }
+
+    return 0xFF;
+}
+
+
+
+
+/*
+    Handlers for access to unused addresses and those which make the
+    machine lock up.
+*/
+void z80bank_unused_w(int address, int data)
+{
+    error("Z80 bank unused write %06X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC));
+}
+
+int z80bank_unused_r(int address)
+{
+    error("Z80 bank unused read %06X (%04X)\n", address, z80_get_reg(Z80_PC));
+    return (address & 1) ? 0x00 : 0xFF;
+}
+
+void z80bank_lockup_w(int address, int data)
+{
+    error("Z80 bank lockup write %06X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC));
+    gen_running = 0;
+    z80_end_timeslice();
+}
+
+int z80bank_lockup_r(int address)
+{
+    error("Z80 bank lockup read %06X (%04X)\n", address, z80_get_reg(Z80_PC));
+    gen_running = 0;
+    z80_end_timeslice();
+    return 0xFF;
+}
+
diff --git a/MCUME_pico2/picogenold/membnk.h b/MCUME_pico2/picogenold/membnk.h
new file mode 100644
index 0000000..1afc9b6
--- /dev/null
+++ b/MCUME_pico2/picogenold/membnk.h
@@ -0,0 +1,17 @@
+
+#ifndef _MEMBNK_H_
+#define _MEMBNK_H_
+
+/* Function prototypes */
+void z80_write_banked_memory(unsigned int address, unsigned int data);
+int z80_read_banked_memory(unsigned int address);
+
+void z80bank_vdp_w(int address, int data);
+int z80bank_vdp_r(int address);
+
+void z80bank_unused_w(int address, int data);
+int z80bank_unused_r(int address);
+void z80bank_lockup_w(int address, int data);
+int z80bank_lockup_r(int address);
+
+#endif /* _MEMBNK_H_ */
diff --git a/MCUME_pico2/picogenold/memory.c b/MCUME_pico2/picogenold/memory.c
new file mode 100644
index 0000000..9b69047
--- /dev/null
+++ b/MCUME_pico2/picogenold/memory.c
@@ -0,0 +1,47 @@
+#include "shared.h"
+
+
+//uint8 lwork_ram[WORK_RAM_SIZE];    /* 68K work RAM */
+//uint8 lzram[Z_RAM_SIZE];         /* Z80 work RAM */
+
+//uint8 lvram[VRAM_SIZE];
+uint8 lbg_name_dirty[BGNAMEDIRTY_SIZE];     
+uint16 lbg_name_list[BGNAME_SIZE];     
+//uint8 lbg_pattern_cache[BGPATTERN_CACH_SIZE];
+
+uint8 * vram;// = &lvram[0];
+uint8 * bg_name_dirty = &lbg_name_dirty[0];     
+uint16 * bg_name_list = &lbg_name_list[0];
+uint8 * bg_pattern_cache; // = &lbg_pattern_cache[0];
+
+
+uint8 * work_ram; // = &lwork_ram[0];
+uint8 * zram; // = &lzram[0];
+
+
+
+void mem_init(void) {
+    bg_pattern_cache = emu_Malloc(BGPATTERN_CACH_SIZE); 
+    vram = emu_Malloc(VRAM_SIZE); 
+    work_ram = emu_Malloc(WORK_RAM_SIZE); 
+    zram = emu_Malloc(Z_RAM_SIZE); 
+    //bg_pattern_cache = emu_Malloc(BGPATTERN_CACH_SIZE+1)&0xFFFFFFFE; 
+    //vram = emu_Malloc(VRAM_SIZE+1)&0xFFFFFFFE; 
+    //work_ram = emu_Malloc(WORK_RAM_SIZE+1)&0xFFFFFFFE; 
+    //zram = emu_Malloc(Z_RAM_SIZE+1)&0xFFFFFFFE; 
+}
+
+
+int mem_test(void) {
+//	for (int i=0x40000;i<OBJ_CACHE_SIZE;i++) {
+//		if (obj_pattern_cache[i] != 0) return 0;;
+//	}
+	return 1;
+}
+
+void memcpy_rom(int dst, int src, int size) {
+	while (size > 0) {   
+		write_rom(dst++, read_rom(src++));
+		size--;
+	}
+}
diff --git a/MCUME_pico2/picogenold/memory.h b/MCUME_pico2/picogenold/memory.h
new file mode 100644
index 0000000..4247bac
--- /dev/null
+++ b/MCUME_pico2/picogenold/memory.h
@@ -0,0 +1,35 @@
+#ifndef _MEMORY_H_
+#define _MEMORY_H_
+
+#include "shared.h"
+
+#define WORK_RAM_SIZE 0x10000
+#define Z_RAM_SIZE 0x2000
+
+#define VRAM_SIZE 0x10000
+#define BGNAMEDIRTY_SIZE 0x800
+#define BGNAME_SIZE 0x800
+#define BGPATTERN_CACH_SIZE 0x40000
+
+
+//extern uint8 * cart_rom;
+extern uint8 * work_ram;    /* 68K work RAM */
+extern uint8 * zram;        /* Z80 work RAM */
+
+extern uint8 * vram;
+extern uint8 * bg_name_dirty;     
+extern uint16 * bg_name_list;     
+extern uint8 * bg_pattern_cache;
+
+
+extern void  mem_init(void);
+extern int mem_test(void);
+extern uint8 rom_version(void);
+extern uint8 readb_rom(int address);
+extern uint8 readb_swap_rom(int address);
+extern uint16 readw_swap_rom(int address);
+extern void  write_rom(int address, uint8 val);
+
+extern void memcpy_rom(int dst, int src, int size);
+
+#endif
diff --git a/MCUME_pico2/picogenold/memvdp.c b/MCUME_pico2/picogenold/memvdp.c
new file mode 100644
index 0000000..f8d2b3b
--- /dev/null
+++ b/MCUME_pico2/picogenold/memvdp.c
@@ -0,0 +1,54 @@
+/*
+    memvdp.c --
+    Memory handlers for when the VDP reads the V-bus during DMA.
+*/
+
+#include "shared.h"
+
+unsigned int vdp_dma_r(unsigned int address)
+{
+    switch((address >> 21) & 7)
+    {
+        case 0: /* Cartridge ROM */
+        case 1: 
+            return readw_swap_rom(address);
+
+        case 2: /* Unused */
+        case 3: 
+            return 0xFF00;
+
+        case 4: /* Work RAM */
+        case 6:
+        case 7:
+            return READ_WORD(work_ram, address & 0xFFFF);
+
+        case 5: /* Z80 area and I/O chip */
+
+            /* Z80 area always returns $FFFF */
+            if(address <= 0xA0FFFF)
+            {
+                /* Return $FFFF only when the Z80 isn't hogging the Z-bus.
+                   (e.g. Z80 isn't reset and 68000 has the bus) */
+                return (zbusack == 0)
+                    ? 0xFFFF 
+                    : READ_WORD(work_ram, address & 0xFFFF);
+            }
+            else
+
+            /* The I/O chip and work RAM try to drive the data bus which
+               results in both values being combined in random ways when read.
+               We return the I/O chip values which seem to have precedence, */
+            if(address <= 0xA1001F)
+            {
+                uint8 temp = gen_io_r((address >> 1) & 0x0F);
+                return (temp << 8 | temp);
+            }
+            else
+
+            /* All remaining locations access work RAM */
+            return READ_WORD(work_ram, address & 0xFFFF);
+    }
+
+    return -1;
+}
+
diff --git a/MCUME_pico2/picogenold/memvdp.h b/MCUME_pico2/picogenold/memvdp.h
new file mode 100644
index 0000000..3e784b9
--- /dev/null
+++ b/MCUME_pico2/picogenold/memvdp.h
@@ -0,0 +1,8 @@
+
+#ifndef _MEMVDP_H_
+#define _MEMVDP_H_
+
+/* Function prototypes */
+unsigned int vdp_dma_r(unsigned int address);
+
+#endif /* _MEMVDP_H_ */
diff --git a/MCUME_pico2/picogenold/memz80.c b/MCUME_pico2/picogenold/memz80.c
new file mode 100644
index 0000000..34abfc9
--- /dev/null
+++ b/MCUME_pico2/picogenold/memz80.c
@@ -0,0 +1,250 @@
+/*
+    memz80.c --
+    Memory handlers for Z80 memory and port access, and the Z80 to
+    VDP interface.
+*/
+
+#define LOG_PORT 0      /* 1= Log Z80 I/O port accesses */
+
+#include "shared.h"
+
+
+unsigned int cpu_readmem16(unsigned int address)
+{
+    switch((address >> 13) & 7)
+    {
+        case 0: /* Work RAM */
+        case 1:
+            return zram[address & 0x1FFF];
+
+        case 2: /* YM2612 */
+            return fm_read(address & 3);
+
+        case 3: /* VDP */
+            if((address & 0xFF00) == 0x7F00)
+                return z80_vdp_r(address);
+            return 0xFF;
+
+        default: /* V-bus bank */
+            return z80_read_banked_memory(zbank | (address & 0x7FFF));
+    }
+
+    return 0xFF;
+}
+
+
+void cpu_writemem16(unsigned int address, unsigned int data)
+{
+    switch((address >> 13) & 7)
+    {
+        case 0: /* Work RAM */
+        case 1: 
+            zram[address & 0x1FFF] = data;
+            return;
+
+        case 2: /* YM2612 */
+            fm_write(address & 3, data);
+            return;
+
+        case 3: /* Bank register and VDP */
+            switch(address & 0xFF00)
+            {
+                case 0x6000:
+                    gen_bank_w(data & 1);
+                    return;
+
+                case 0x7F00:
+                    z80_vdp_w(address, data);
+                    return;
+
+                default:
+                    z80_unused_w(address, data);
+                    return;
+            }
+            return;
+
+        default: /* V-bus bank */
+            z80_write_banked_memory(zbank | (address & 0x7FFF), data);
+            return;
+    }
+}
+
+
+int z80_vdp_r(int address)
+{
+    switch(address & 0xFF)
+    {
+        case 0x00: /* VDP data port */
+        case 0x02:
+            return (vdp_data_r() >> 8) & 0xFF;
+                        
+        case 0x01: /* VDP data port */ 
+        case 0x03:
+            return (vdp_data_r() & 0xFF);
+
+        case 0x04: /* VDP control port */
+        case 0x06:
+            return (0xFF | ((vdp_ctrl_r() >> 8) & 3));
+                        
+        case 0x05: /* VDP control port */
+        case 0x07:
+            return (vdp_ctrl_r() & 0xFF);
+
+        case 0x08: /* HV counter */
+        case 0x0A:
+        case 0x0C:
+        case 0x0E:
+            return (vdp_hvc_r() >> 8) & 0xFF;
+
+        case 0x09: /* HV counter */
+        case 0x0B:
+        case 0x0D:
+        case 0x0F:
+            return (vdp_hvc_r() & 0xFF);
+
+        case 0x10: /* Unused (PSG) */
+        case 0x11:
+        case 0x12:
+        case 0x13:
+        case 0x14:
+        case 0x15:
+        case 0x16:
+        case 0x17:
+            return z80_lockup_r(address);
+
+        case 0x18: /* Unused */
+        case 0x19:
+        case 0x1A:
+        case 0x1B:
+            return z80_unused_r(address);
+
+        case 0x1C: /* Unused (test register) */
+        case 0x1D:
+        case 0x1E:
+        case 0x1F:
+            return z80_unused_r(address);
+
+        default: /* Invalid VDP addresses */
+            return z80_lockup_r(address);
+    }
+
+    return 0xFF;
+}
+
+
+void z80_vdp_w(int address, int data)
+{
+    switch(address & 0xFF)
+    {
+        case 0x00: /* VDP data port */
+        case 0x01: 
+        case 0x02:
+        case 0x03:
+            vdp_data_w(data << 8 | data);
+            return;
+
+        case 0x04: /* VDP control port */
+        case 0x05:
+        case 0x06:
+        case 0x07:
+            vdp_ctrl_w(data << 8 | data);
+            return;
+
+        case 0x08: /* Unused (HV counter) */
+        case 0x09:
+        case 0x0A:
+        case 0x0B:
+        case 0x0C:
+        case 0x0D:
+        case 0x0E:
+        case 0x0F:
+            z80_lockup_w(address, data);
+            return;
+
+        case 0x11: /* PSG */
+        case 0x13:
+        case 0x15:
+        case 0x17:
+            psg_write(data);
+            return;
+
+        case 0x10: /* Unused */
+        case 0x12:
+        case 0x14:
+        case 0x16:
+            z80_unused_w(address, data);
+
+        case 0x18: /* Unused */
+        case 0x19:
+        case 0x1A:
+        case 0x1B:
+            z80_unused_w(address, data);
+            return;
+
+        case 0x1C: /* Test register */
+        case 0x1D: 
+        case 0x1E:
+        case 0x1F:
+            vdp_test_w(data << 8 | data);
+            return;
+
+        default: /* Invalid VDP addresses */
+            z80_lockup_w(address, data);
+            return;
+    }
+}
+
+
+/*
+    Port handlers. Ports are unused when not in Mark III compatability mode.
+
+    Games that access ports anyway:
+    - Thunder Force IV reads port $BF in it's interrupt handler.
+*/
+
+unsigned int cpu_readport16(unsigned int port)
+{
+#if LOG_PORT
+    error("Z80 read port %04X (%04X)\n", port, z80_get_reg(Z80_PC));
+#endif    
+    return 0xFF;
+}
+
+void cpu_writeport16(unsigned int port, unsigned int data)
+{
+#if LOG_PORT
+    error("Z80 write %02X to port %04X (%04X)\n", data, port, z80_get_reg(Z80_PC));
+#endif
+}
+
+
+/*
+    Handlers for access to unused addresses and those which make the
+    machine lock up.
+*/
+void z80_unused_w(int address, int data)
+{
+    error("Z80 unused write %04X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC));    
+}
+
+int z80_unused_r(int address)
+{
+    error("Z80 unused read %04X (%04X)\n", address, z80_get_reg(Z80_PC));    
+    return 0xFF;
+}
+
+void z80_lockup_w(int address, int data)
+{
+    error("Z80 lockup write %04X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC));    
+    gen_running = 0;
+    z80_end_timeslice();
+}
+
+int z80_lockup_r(int address)
+{
+    error("Z80 lockup read %04X (%04X)\n", address, z80_get_reg(Z80_PC));
+    gen_running = 0;
+    z80_end_timeslice();
+    return 0xFF;
+}
+
diff --git a/MCUME_pico2/picogenold/memz80.h b/MCUME_pico2/picogenold/memz80.h
new file mode 100644
index 0000000..82b2139
--- /dev/null
+++ b/MCUME_pico2/picogenold/memz80.h
@@ -0,0 +1,17 @@
+
+#ifndef _MEMZ80_H_
+#define _MEMZ80_H_
+
+/* Function prototypes */
+unsigned int cpu_readmem16(unsigned int address);
+void cpu_writemem16(unsigned int address, unsigned int data);
+unsigned int cpu_readport16(unsigned int port);
+void cpu_writeport16(unsigned int port, unsigned int data);
+void z80_unused_w(int address, int data);
+int z80_unused_r(int address);
+void z80_lockup_w(int address, int data);
+int z80_lockup_r(int address);
+int z80_vdp_r(int address);
+void z80_vdp_w(int address, int data);
+
+#endif /* _MEMZ80_H_ */
diff --git a/MCUME_pico2/picogenold/musashi34/m68k.h b/MCUME_pico2/picogenold/musashi34/m68k.h
new file mode 100644
index 0000000..e2f0b27
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68k.h
@@ -0,0 +1,358 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.4
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef M68K__HEADER
+#define M68K__HEADER
+
+
+/* ======================================================================== */
+/* ============================= CONFIGURATION ============================ */
+/* ======================================================================== */
+
+/* Import the configuration for this build */
+#include "m68kconf.h"
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+
+/* ======================================================================== */
+
+/* There are 7 levels of interrupt to the 68K.
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ */
+#define M68K_IRQ_NONE 0
+#define M68K_IRQ_1    1
+#define M68K_IRQ_2    2
+#define M68K_IRQ_3    3
+#define M68K_IRQ_4    4
+#define M68K_IRQ_5    5
+#define M68K_IRQ_6    6
+#define M68K_IRQ_7    7
+
+
+/* Special interrupt acknowledge values.
+ * Use these as special returns from the interrupt acknowledge callback
+ * (specified later in this header).
+ */
+
+/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
+ * This happens in a real 68K if VPA or AVEC is asserted during an interrupt
+ * acknowledge cycle instead of DTACK.
+ */
+#define M68K_INT_ACK_AUTOVECTOR    0xffffffff
+
+/* Causes the spurious interrupt vector (0x18) to be taken
+ * This happens in a real 68K if BERR is asserted during the interrupt
+ * acknowledge cycle (i.e. no devices responded to the acknowledge).
+ */
+#define M68K_INT_ACK_SPURIOUS      0xfffffffe
+
+
+/* CPU types for use in m68k_set_cpu_type() */
+enum
+{
+	M68K_CPU_TYPE_INVALID,
+	M68K_CPU_TYPE_68000,
+	M68K_CPU_TYPE_68010,
+	M68K_CPU_TYPE_68EC020,
+	M68K_CPU_TYPE_68020,
+	M68K_CPU_TYPE_68030,	/* Supported by disassembler ONLY */
+	M68K_CPU_TYPE_68040		/* Supported by disassembler ONLY */
+};
+
+/* Registers used by m68k_get_reg() and m68k_set_reg() */
+typedef enum
+{
+	/* Real registers */
+	M68K_REG_D0,		/* Data registers */
+	M68K_REG_D1,
+	M68K_REG_D2,
+	M68K_REG_D3,
+	M68K_REG_D4,
+	M68K_REG_D5,
+	M68K_REG_D6,
+	M68K_REG_D7,
+	M68K_REG_A0,		/* Address registers */
+	M68K_REG_A1,
+	M68K_REG_A2,
+	M68K_REG_A3,
+	M68K_REG_A4,
+	M68K_REG_A5,
+	M68K_REG_A6,
+	M68K_REG_A7,
+	M68K_REG_PC,		/* Program Counter */
+	M68K_REG_SR,		/* Status Register */
+	M68K_REG_SP,		/* The current Stack Pointer (located in A7) */
+	M68K_REG_USP,		/* User Stack Pointer */
+	M68K_REG_ISP,		/* Interrupt Stack Pointer */
+	M68K_REG_MSP,		/* Master Stack Pointer */
+	M68K_REG_SFC,		/* Source Function Code */
+	M68K_REG_DFC,		/* Destination Function Code */
+	M68K_REG_VBR,		/* Vector Base Register */
+	M68K_REG_CACR,		/* Cache Control Register */
+	M68K_REG_CAAR,		/* Cache Address Register */
+
+	/* Assumed registers */
+	/* These are cheat registers which emulate the 1-longword prefetch
+	 * present in the 68000 and 68010.
+	 */
+	M68K_REG_PREF_ADDR,	/* Last prefetch address */
+	M68K_REG_PREF_DATA,	/* Last prefetch data */
+
+	/* Convenience registers */
+	M68K_REG_PPC,		/* Previous value in the program counter */
+	M68K_REG_IR,		/* Instruction register */
+	M68K_REG_CPU_TYPE	/* Type of CPU being run */
+} m68k_register_t;
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */
+/* ======================================================================== */
+
+/* You will have to implement these functions */
+
+/* read/write functions called by the CPU to access memory.
+ * while values used are 32 bits, only the appropriate number
+ * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits
+ * of value should be written to memory).
+ *
+ * NOTE: I have separated the immediate and PC-relative memory fetches
+ *       from the other memory fetches because some systems require
+ *       differentiation between PROGRAM and DATA fetches (usually
+ *       for security setups such as encryption).
+ *       This separation can either be achieved by setting
+ *       M68K_SEPARATE_READS in m68kconf.h and defining
+ *       the read functions, or by setting M68K_EMULATE_FC and
+ *       making a function code callback function.
+ *       Using the callback offers better emulation coverage
+ *       because you can also monitor whether the CPU is in SYSTEM or
+ *       USER mode, but it is also slower.
+ */
+
+/* Read from anywhere */
+unsigned int  m68k_read_memory_8(unsigned int address);
+unsigned int  m68k_read_memory_16(unsigned int address);
+unsigned int  m68k_read_memory_32(unsigned int address);
+
+/* Read data immediately following the PC */
+unsigned int  m68k_read_immediate_16(unsigned int address);
+unsigned int  m68k_read_immediate_32(unsigned int address);
+
+/* Read data relative to the PC */
+unsigned int  m68k_read_pcrelative_8(unsigned int address);
+unsigned int  m68k_read_pcrelative_16(unsigned int address);
+unsigned int  m68k_read_pcrelative_32(unsigned int address);
+
+/* Memory access for the disassembler */
+unsigned int m68k_read_disassembler_8  (unsigned int address);
+unsigned int m68k_read_disassembler_16 (unsigned int address);
+unsigned int m68k_read_disassembler_32 (unsigned int address);
+
+/* Write to anywhere */
+void m68k_write_memory_8(unsigned int address, unsigned int value);
+void m68k_write_memory_16(unsigned int address, unsigned int value);
+void m68k_write_memory_32(unsigned int address, unsigned int value);
+
+/* Special call to simulate undocumented 68k behavior when move.l with a
+ * predecrement destination mode is executed.
+ * To simulate real 68k behavior, first write the high word to
+ * [address+2], and then write the low word to [address].
+ *
+ * Enable this functionality with M68K_SIMULATE_PD_WRITES in m68kconf.h.
+ */
+void m68k_write_memory_32_pd(unsigned int address, unsigned int value);
+
+
+
+/* ======================================================================== */
+/* ============================== CALLBACKS =============================== */
+/* ======================================================================== */
+
+/* These functions allow you to set callbacks to the host when specific events
+ * occur.  Note that you must enable the corresponding value in m68kconf.h
+ * in order for these to do anything useful.
+ * Note: I have defined default callbacks which are used if you have enabled
+ * the corresponding #define in m68kconf.h but either haven't assigned a
+ * callback or have assigned a callback of NULL.
+ */
+
+/* Set the callback for an interrupt acknowledge.
+ * You must enable M68K_EMULATE_INT_ACK in m68kconf.h.
+ * The CPU will call the callback with the interrupt level being acknowledged.
+ * The host program must return either a vector from 0x02-0xff, or one of the
+ * special interrupt acknowledge values specified earlier in this header.
+ * If this is not implemented, the CPU will always assume an autovectored
+ * interrupt, and will automatically clear the interrupt request when it
+ * services the interrupt.
+ * Default behavior: return M68K_INT_ACK_AUTOVECTOR.
+ */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level));
+
+
+/* Set the callback for a breakpoint acknowledge (68010+).
+ * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h.
+ * The CPU will call the callback with whatever was in the data field of the
+ * BKPT instruction for 68020+, or 0 for 68010.
+ * Default behavior: do nothing.
+ */
+void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data));
+
+
+/* Set the callback for the RESET instruction.
+ * You must enable M68K_EMULATE_RESET in m68kconf.h.
+ * The CPU calls this callback every time it encounters a RESET instruction.
+ * Default behavior: do nothing.
+ */
+void m68k_set_reset_instr_callback(void  (*callback)(void));
+
+
+/* Set the callback for informing of a large PC change.
+ * You must enable M68K_MONITOR_PC in m68kconf.h.
+ * The CPU calls this callback with the new PC value every time the PC changes
+ * by a large value (currently set for changes by longwords).
+ * Default behavior: do nothing.
+ */
+void m68k_set_pc_changed_callback(void  (*callback)(unsigned int new_pc));
+
+
+/* Set the callback for CPU function code changes.
+ * You must enable M68K_EMULATE_FC in m68kconf.h.
+ * The CPU calls this callback with the function code before every memory
+ * access to set the CPU's function code according to what kind of memory
+ * access it is (supervisor/user, program/data and such).
+ * Default behavior: do nothing.
+ */
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc));
+
+
+/* Set a callback for the instruction cycle of the CPU.
+ * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h.
+ * The CPU calls this callback just before fetching the opcode in the
+ * instruction cycle.
+ * Default behavior: do nothing.
+ */
+void m68k_set_instr_hook_callback(void  (*callback)(void));
+
+
+
+/* ======================================================================== */
+/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */
+/* ======================================================================== */
+
+/* Use this function to set the CPU type you want to emulate.
+ * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010,
+ * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020.
+ */
+void m68k_set_cpu_type(unsigned int cpu_type);
+
+/* Do whatever initialisations the core requires.  Should be called
+ * at least once at init time.
+ */
+void m68k_init(void);
+
+/* Pulse the RESET pin on the CPU.
+ * You *MUST* reset the CPU at least once to initialize the emulation
+ * Note: If you didn't call m68k_set_cpu_type() before resetting
+ *       the CPU for the first time, the CPU will be set to
+ *       M68K_CPU_TYPE_68000.
+ */
+void m68k_pulse_reset(void);
+
+/* execute num_cycles worth of instructions.  returns number of cycles used */
+int m68k_execute(int num_cycles);
+
+/* These functions let you read/write/modify the number of cycles left to run
+ * while m68k_execute() is running.
+ * These are useful if the 68k accesses a memory-mapped port on another device
+ * that requires immediate processing by another CPU.
+ */
+int m68k_cycles_run(void);              /* Number of cycles run so far */
+int m68k_cycles_remaining(void);        /* Number of cycles left */
+void m68k_modify_timeslice(int cycles); /* Modify cycles left */
+void m68k_end_timeslice(void);          /* End timeslice now */
+
+/* Set the IPL0-IPL2 pins on the CPU (IRQ).
+ * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
+ * Setting IRQ to 0 will clear an interrupt request.
+ */
+void m68k_set_irq(unsigned int int_level);
+
+
+/* Halt the CPU as if you pulsed the HALT pin. */
+void m68k_pulse_halt(void);
+
+
+/* Context switching to allow multiple CPUs */
+
+/* Get the size of the cpu context in bytes */
+unsigned int m68k_context_size(void);
+
+/* Get a cpu context */
+unsigned int m68k_get_context(void* dst);
+
+/* set the current cpu context */
+void m68k_set_context(void* dst);
+
+/* Register the CPU state information */
+void m68k_state_register(const char *type);
+
+
+/* Peek at the internals of a CPU context.  This can either be a context
+ * retrieved using m68k_get_context() or the currently running context.
+ * If context is NULL, the currently running CPU context will be used.
+ */
+unsigned int m68k_get_reg(void* context, m68k_register_t reg);
+
+/* Poke values into the internals of the currently running CPU context */
+void m68k_set_reg(m68k_register_t reg, unsigned int value);
+
+/* Check if an instruction is valid for the specified CPU type */
+unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type);
+
+/* Disassemble 1 instruction using the epecified CPU type at pc.  Stores
+ * disassembly in str_buff and returns the size of the instruction in bytes.
+ */
+unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type);
+
+
+/* ======================================================================== */
+/* ============================== MAME STUFF ============================== */
+/* ======================================================================== */
+
+#if M68K_COMPILE_FOR_MAME == OPT_ON
+#include "m68kmame.h"
+#endif /* M68K_COMPILE_FOR_MAME */
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68K__HEADER */
diff --git a/MCUME_pico2/picogenold/musashi34/m68kconf.h b/MCUME_pico2/picogenold/musashi34/m68kconf.h
new file mode 100644
index 0000000..5f71c38
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kconf.h
@@ -0,0 +1,189 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.4
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+
+#ifndef M68KCONF__HEADER
+#define M68KCONF__HEADER
+
+
+/* Configuration switches.
+ * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks.
+ * OPT_SPECIFY_HANDLER causes the core to link directly to the function
+ * or macro you specify, rather than using callback functions whose pointer
+ * must be passed in using m68k_set_xxx_callback().
+ */
+#define OPT_OFF             0
+#define OPT_ON              1
+#define OPT_SPECIFY_HANDLER 2
+
+
+/* ======================================================================== */
+/* ============================== MAME STUFF ============================== */
+/* ======================================================================== */
+
+/* If you're compiling this for MAME, only change M68K_COMPILE_FOR_MAME
+ * to OPT_ON and use m68kmame.h to configure the 68k core.
+ */
+#ifndef M68K_COMPILE_FOR_MAME
+#define M68K_COMPILE_FOR_MAME      OPT_OFF
+#endif /* M68K_COMPILE_FOR_MAME */
+
+
+#if M68K_COMPILE_FOR_MAME == OPT_OFF
+
+
+/* ======================================================================== */
+/* ============================= CONFIGURATION ============================ */
+/* ======================================================================== */
+
+/* Turn on if you want to use the following M68K variants */
+#define M68K_EMULATE_010            OPT_ON
+#define M68K_EMULATE_EC020          OPT_ON
+#define M68K_EMULATE_020            OPT_ON
+
+
+/* If ON, the CPU will call m68k_read_immediate_xx() for immediate addressing
+ * and m68k_read_pcrelative_xx() for PC-relative addressing.
+ * If off, all read requests from the CPU will be redirected to m68k_read_xx()
+ */
+#define M68K_SEPARATE_READS         OPT_OFF
+
+
+/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a
+ * predecrement destination EA mode instead of m68k_write_32().
+ * To simulate real 68k behavior, m68k_write_32_pd() must first write the high
+ * word to [address+2], and then write the low word to [address].
+ */
+#define M68K_SIMULATE_PD_WRITES     OPT_OFF
+
+/* If ON, CPU will call the interrupt acknowledge callback when it services an
+ * interrupt.
+ * If off, all interrupts will be autovectored and all interrupt requests will
+ * auto-clear when the interrupt is serviced.
+ */
+#define M68K_EMULATE_INT_ACK        OPT_SPECIFY_HANDLER
+#define M68K_INT_ACK_CALLBACK(A)    vdp_int_ack_callback(A)
+
+
+/* If ON, CPU will call the breakpoint acknowledge callback when it encounters
+ * a breakpoint instruction and it is running a 68010+.
+ */
+#define M68K_EMULATE_BKPT_ACK       OPT_OFF
+#define M68K_BKPT_ACK_CALLBACK()    your_bkpt_ack_handler_function()
+
+
+/* If ON, the CPU will monitor the trace flags and take trace exceptions
+ */
+#define M68K_EMULATE_TRACE          OPT_OFF
+
+
+/* If ON, CPU will call the output reset callback when it encounters a reset
+ * instruction.
+ */
+#define M68K_EMULATE_RESET          OPT_OFF
+#define M68K_RESET_CALLBACK()       your_reset_handler_function()
+
+
+/* If ON, CPU will call the set fc callback on every memory access to
+ * differentiate between user/supervisor, program/data access like a real
+ * 68000 would.  This should be enabled and the callback should be set if you
+ * want to properly emulate the m68010 or higher. (moves uses function codes
+ * to read/write data from different address spaces)
+ */
+#define M68K_EMULATE_FC             OPT_OFF
+#define M68K_SET_FC_CALLBACK(A)     your_set_fc_handler_function(A)
+
+
+/* If ON, CPU will call the pc changed callback when it changes the PC by a
+ * large value.  This allows host programs to be nicer when it comes to
+ * fetching immediate data and instructions on a banked memory system.
+ */
+#define M68K_MONITOR_PC             OPT_OFF
+#define M68K_SET_PC_CALLBACK(A)     your_pc_changed_handler_function(A)
+
+
+/* If ON, CPU will call the instruction hook callback before every
+ * instruction.
+ */
+//#define M68K_INSTRUCTION_HOOK       OPT_SPECIFY_HANDLER
+#define M68K_INSTRUCTION_HOOK       OPT_OFF
+#define M68K_INSTRUCTION_CALLBACK() your_instruction_hook_function()
+
+
+/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */
+#define M68K_EMULATE_PREFETCH       OPT_OFF
+
+
+/* If ON, the CPU will generate address error exceptions if it tries to
+ * access a word or longword at an odd address.
+ * NOTE: This is only emulated properly for 68000 mode.
+ */
+#define M68K_EMULATE_ADDRESS_ERROR  OPT_OFF
+
+
+/* Turn ON to enable logging of illegal instruction calls.
+ * M68K_LOG_FILEHANDLE must be #defined to a stdio file stream.
+ * Turn on M68K_LOG_1010_1111 to log all 1010 and 1111 calls.
+ */
+#define M68K_LOG_ENABLE             OPT_OFF
+#define M68K_LOG_1010_1111          OPT_OFF
+#define M68K_LOG_FILEHANDLE         some_file_handle
+
+
+/* ----------------------------- COMPATIBILITY ---------------------------- */
+
+/* The following options set optimizations that violate the current ANSI
+ * standard, but will be compliant under the forthcoming C9X standard.
+ */
+
+
+/* If ON, the enulation core will use 64-bit integers to speed up some
+ * operations.
+*/
+#define M68K_USE_64_BIT  OPT_OFF
+
+
+/* Set to your compiler's static inline keyword to enable it, or
+ * set it to blank to disable it.
+ * If you define INLINE in the makefile, it will override this value.
+ * NOTE: not enabling inline functions will SEVERELY slow down emulation.
+ */
+#ifndef INLINE
+#define INLINE static __inline__
+#endif /* INLINE */
+
+#endif /* M68K_COMPILE_FOR_MAME */
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCONF__HEADER */
diff --git a/MCUME_pico2/picogenold/musashi34/m68kcpu.c b/MCUME_pico2/picogenold/musashi34/m68kcpu.c
new file mode 100644
index 0000000..845fffd
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kcpu.c
@@ -0,0 +1,882 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.4
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+/* ======================================================================== */
+/* ================================= NOTES ================================ */
+/* ======================================================================== */
+
+
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include "m68kops.h"
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+int  m68ki_initial_cycles;
+int  m68ki_remaining_cycles = 0;                     /* Number of clocks remaining */
+uint m68ki_tracing = 0;
+uint m68ki_address_space;
+
+#ifdef M68K_LOG_ENABLE
+char* m68ki_cpu_names[9] =
+{
+	"Invalid CPU",
+	"M68000",
+	"M68010",
+	"Invalid CPU",
+	"M68EC020"
+	"Invalid CPU",
+	"Invalid CPU",
+	"Invalid CPU",
+	"M68020"
+};
+#endif /* M68K_LOG_ENABLE */
+
+/* The CPU core */
+m68ki_cpu_core m68ki_cpu = {0};
+
+#if M68K_EMULATE_ADDRESS_ERROR
+jmp_buf m68ki_address_error_trap;
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+uint    m68ki_aerr_address;
+uint    m68ki_aerr_write_mode;
+uint    m68ki_aerr_fc;
+
+/* Used by shift & rotate instructions */
+const uint8 m68ki_shift_8_table[65] =
+{
+	0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff
+};
+const uint16 m68ki_shift_16_table[65] =
+{
+	0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00,
+	0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+	0xffff, 0xffff
+};
+const uint m68ki_shift_32_table[65] =
+{
+	0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000,
+	0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000,
+	0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000,
+	0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00,
+	0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8,
+	0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+
+/* Number of clock cycles to use for exception processing.
+ * I used 4 for any vectors that are undocumented for processing times.
+ */
+uint8 m68ki_exception_cycle_table[3][256] =
+{
+	{ /* 000 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		 50, /*  2: Bus Error                             (unemulated) */
+		 50, /*  3: Address Error                         (unemulated) */
+		 34, /*  4: Illegal Instruction                                */
+		 38, /*  5: Divide by Zero -- ASG: changed from 42             */
+		 40, /*  6: CHK -- ASG: chanaged from 44                       */
+		 34, /*  7: TRAPV                                              */
+		 34, /*  8: Privilege Violation                                */
+		 34, /*  9: Trace                                              */
+		 34, /* 10: 1010                                               */
+		 34, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 44, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 44, /* 24: Spurious Interrupt                                 */
+		 44, /* 25: Level 1 Interrupt Autovector                       */
+		 44, /* 26: Level 2 Interrupt Autovector                       */
+		 44, /* 27: Level 3 Interrupt Autovector                       */
+		 44, /* 28: Level 4 Interrupt Autovector                       */
+		 44, /* 29: Level 5 Interrupt Autovector                       */
+		 44, /* 30: Level 6 Interrupt Autovector                       */
+		 44, /* 31: Level 7 Interrupt Autovector                       */
+		 34, /* 32: TRAP #0 -- ASG: chanaged from 38                   */
+		 34, /* 33: TRAP #1                                            */
+		 34, /* 34: TRAP #2                                            */
+		 34, /* 35: TRAP #3                                            */
+		 34, /* 36: TRAP #4                                            */
+		 34, /* 37: TRAP #5                                            */
+		 34, /* 38: TRAP #6                                            */
+		 34, /* 39: TRAP #7                                            */
+		 34, /* 40: TRAP #8                                            */
+		 34, /* 41: TRAP #9                                            */
+		 34, /* 42: TRAP #10                                           */
+		 34, /* 43: TRAP #11                                           */
+		 34, /* 44: TRAP #12                                           */
+		 34, /* 45: TRAP #13                                           */
+		 34, /* 46: TRAP #14                                           */
+		 34, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	},
+	{ /* 010 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		126, /*  2: Bus Error                             (unemulated) */
+		126, /*  3: Address Error                         (unemulated) */
+		 38, /*  4: Illegal Instruction                                */
+		 44, /*  5: Divide by Zero                                     */
+		 44, /*  6: CHK                                                */
+		 34, /*  7: TRAPV                                              */
+		 38, /*  8: Privilege Violation                                */
+		 38, /*  9: Trace                                              */
+		  4, /* 10: 1010                                               */
+		  4, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 44, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 46, /* 24: Spurious Interrupt                                 */
+		 46, /* 25: Level 1 Interrupt Autovector                       */
+		 46, /* 26: Level 2 Interrupt Autovector                       */
+		 46, /* 27: Level 3 Interrupt Autovector                       */
+		 46, /* 28: Level 4 Interrupt Autovector                       */
+		 46, /* 29: Level 5 Interrupt Autovector                       */
+		 46, /* 30: Level 6 Interrupt Autovector                       */
+		 46, /* 31: Level 7 Interrupt Autovector                       */
+		 38, /* 32: TRAP #0                                            */
+		 38, /* 33: TRAP #1                                            */
+		 38, /* 34: TRAP #2                                            */
+		 38, /* 35: TRAP #3                                            */
+		 38, /* 36: TRAP #4                                            */
+		 38, /* 37: TRAP #5                                            */
+		 38, /* 38: TRAP #6                                            */
+		 38, /* 39: TRAP #7                                            */
+		 38, /* 40: TRAP #8                                            */
+		 38, /* 41: TRAP #9                                            */
+		 38, /* 42: TRAP #10                                           */
+		 38, /* 43: TRAP #11                                           */
+		 38, /* 44: TRAP #12                                           */
+		 38, /* 45: TRAP #13                                           */
+		 38, /* 46: TRAP #14                                           */
+		 38, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	},
+	{ /* 020 */
+		  4, /*  0: Reset - Initial Stack Pointer                      */
+		  4, /*  1: Reset - Initial Program Counter                    */
+		 50, /*  2: Bus Error                             (unemulated) */
+		 50, /*  3: Address Error                         (unemulated) */
+		 20, /*  4: Illegal Instruction                                */
+		 38, /*  5: Divide by Zero                                     */
+		 40, /*  6: CHK                                                */
+		 20, /*  7: TRAPV                                              */
+		 34, /*  8: Privilege Violation                                */
+		 25, /*  9: Trace                                              */
+		 20, /* 10: 1010                                               */
+		 20, /* 11: 1111                                               */
+		  4, /* 12: RESERVED                                           */
+		  4, /* 13: Coprocessor Protocol Violation        (unemulated) */
+		  4, /* 14: Format Error                                       */
+		 30, /* 15: Uninitialized Interrupt                            */
+		  4, /* 16: RESERVED                                           */
+		  4, /* 17: RESERVED                                           */
+		  4, /* 18: RESERVED                                           */
+		  4, /* 19: RESERVED                                           */
+		  4, /* 20: RESERVED                                           */
+		  4, /* 21: RESERVED                                           */
+		  4, /* 22: RESERVED                                           */
+		  4, /* 23: RESERVED                                           */
+		 30, /* 24: Spurious Interrupt                                 */
+		 30, /* 25: Level 1 Interrupt Autovector                       */
+		 30, /* 26: Level 2 Interrupt Autovector                       */
+		 30, /* 27: Level 3 Interrupt Autovector                       */
+		 30, /* 28: Level 4 Interrupt Autovector                       */
+		 30, /* 29: Level 5 Interrupt Autovector                       */
+		 30, /* 30: Level 6 Interrupt Autovector                       */
+		 30, /* 31: Level 7 Interrupt Autovector                       */
+		 20, /* 32: TRAP #0                                            */
+		 20, /* 33: TRAP #1                                            */
+		 20, /* 34: TRAP #2                                            */
+		 20, /* 35: TRAP #3                                            */
+		 20, /* 36: TRAP #4                                            */
+		 20, /* 37: TRAP #5                                            */
+		 20, /* 38: TRAP #6                                            */
+		 20, /* 39: TRAP #7                                            */
+		 20, /* 40: TRAP #8                                            */
+		 20, /* 41: TRAP #9                                            */
+		 20, /* 42: TRAP #10                                           */
+		 20, /* 43: TRAP #11                                           */
+		 20, /* 44: TRAP #12                                           */
+		 20, /* 45: TRAP #13                                           */
+		 20, /* 46: TRAP #14                                           */
+		 20, /* 47: TRAP #15                                           */
+		  4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
+		  4, /* 49: FP Inexact Result                     (unemulated) */
+		  4, /* 50: FP Divide by Zero                     (unemulated) */
+		  4, /* 51: FP Underflow                          (unemulated) */
+		  4, /* 52: FP Operand Error                      (unemulated) */
+		  4, /* 53: FP Overflow                           (unemulated) */
+		  4, /* 54: FP Signaling NAN                      (unemulated) */
+		  4, /* 55: FP Unimplemented Data Type            (unemulated) */
+		  4, /* 56: MMU Configuration Error               (unemulated) */
+		  4, /* 57: MMU Illegal Operation Error           (unemulated) */
+		  4, /* 58: MMU Access Level Violation Error      (unemulated) */
+		  4, /* 59: RESERVED                                           */
+		  4, /* 60: RESERVED                                           */
+		  4, /* 61: RESERVED                                           */
+		  4, /* 62: RESERVED                                           */
+		  4, /* 63: RESERVED                                           */
+		     /* 64-255: User Defined                                   */
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
+		  4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
+	}
+};
+
+uint8 m68ki_ea_idx_cycle_table[64] =
+{
+	 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+	 0, /* ..01.000 no memory indirect, base NULL             */
+	 5, /* ..01..01 memory indirect,    base NULL, outer NULL */
+	 7, /* ..01..10 memory indirect,    base NULL, outer 16   */
+	 7, /* ..01..11 memory indirect,    base NULL, outer 32   */
+	 0,  5,  7,  7,  0,  5,  7,  7,  0,  5,  7,  7,
+	 2, /* ..10.000 no memory indirect, base 16               */
+	 7, /* ..10..01 memory indirect,    base 16,   outer NULL */
+	 9, /* ..10..10 memory indirect,    base 16,   outer 16   */
+	 9, /* ..10..11 memory indirect,    base 16,   outer 32   */
+	 0,  7,  9,  9,  0,  7,  9,  9,  0,  7,  9,  9,
+	 6, /* ..11.000 no memory indirect, base 32               */
+	11, /* ..11..01 memory indirect,    base 32,   outer NULL */
+	13, /* ..11..10 memory indirect,    base 32,   outer 16   */
+	13, /* ..11..11 memory indirect,    base 32,   outer 32   */
+	 0, 11, 13, 13,  0, 11, 13, 13,  0, 11, 13, 13
+};
+
+
+
+/* ======================================================================== */
+/* =============================== CALLBACKS ============================== */
+/* ======================================================================== */
+
+/* Default callbacks used if the callback hasn't been set yet, or if the
+ * callback is set to NULL
+ */
+
+/* Interrupt acknowledge */
+static int default_int_ack_callback_data;
+static int default_int_ack_callback(int int_level)
+{
+	default_int_ack_callback_data = int_level;
+	CPU_INT_LEVEL = 0;
+	return M68K_INT_ACK_AUTOVECTOR;
+}
+
+/* Breakpoint acknowledge */
+static unsigned int default_bkpt_ack_callback_data;
+static void default_bkpt_ack_callback(unsigned int data)
+{
+	default_bkpt_ack_callback_data = data;
+}
+
+/* Called when a reset instruction is executed */
+static void default_reset_instr_callback(void)
+{
+}
+
+/* Called when the program counter changed by a large value */
+static unsigned int default_pc_changed_callback_data;
+static void default_pc_changed_callback(unsigned int new_pc)
+{
+	default_pc_changed_callback_data = new_pc;
+}
+
+/* Called every time there's bus activity (read/write to/from memory */
+static unsigned int default_set_fc_callback_data;
+static void default_set_fc_callback(unsigned int new_fc)
+{
+	default_set_fc_callback_data = new_fc;
+}
+
+/* Called every instruction cycle prior to execution */
+static void default_instr_hook_callback(void)
+{
+}
+
+
+#if M68K_EMULATE_ADDRESS_ERROR
+	#include <setjmp.h>
+	jmp_buf m68ki_aerr_trap;
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+/* Access the internals of the CPU */
+unsigned int m68k_get_reg(void* context, m68k_register_t regnum)
+{
+	m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu;
+
+	switch(regnum)
+	{
+		case M68K_REG_D0:	return cpu->dar[0];
+		case M68K_REG_D1:	return cpu->dar[1];
+		case M68K_REG_D2:	return cpu->dar[2];
+		case M68K_REG_D3:	return cpu->dar[3];
+		case M68K_REG_D4:	return cpu->dar[4];
+		case M68K_REG_D5:	return cpu->dar[5];
+		case M68K_REG_D6:	return cpu->dar[6];
+		case M68K_REG_D7:	return cpu->dar[7];
+		case M68K_REG_A0:	return cpu->dar[8];
+		case M68K_REG_A1:	return cpu->dar[9];
+		case M68K_REG_A2:	return cpu->dar[10];
+		case M68K_REG_A3:	return cpu->dar[11];
+		case M68K_REG_A4:	return cpu->dar[12];
+		case M68K_REG_A5:	return cpu->dar[13];
+		case M68K_REG_A6:	return cpu->dar[14];
+		case M68K_REG_A7:	return cpu->dar[15];
+		case M68K_REG_PC:	return MASK_OUT_ABOVE_32(cpu->pc);
+		case M68K_REG_SR:	return	cpu->t1_flag						|
+									cpu->t0_flag						|
+									(cpu->s_flag << 11)					|
+									(cpu->m_flag << 11)					|
+									cpu->int_mask						|
+									((cpu->x_flag & XFLAG_SET) >> 4)	|
+									((cpu->n_flag & NFLAG_SET) >> 4)	|
+									((!cpu->not_z_flag) << 2)			|
+									((cpu->v_flag & VFLAG_SET) >> 6)	|
+									((cpu->c_flag & CFLAG_SET) >> 8);
+		case M68K_REG_SP:	return cpu->dar[15];
+		case M68K_REG_USP:	return cpu->s_flag ? cpu->sp[0] : cpu->dar[15];
+		case M68K_REG_ISP:	return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4];
+		case M68K_REG_MSP:	return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6];
+		case M68K_REG_SFC:	return cpu->sfc;
+		case M68K_REG_DFC:	return cpu->dfc;
+		case M68K_REG_VBR:	return cpu->vbr;
+		case M68K_REG_CACR:	return cpu->cacr;
+		case M68K_REG_CAAR:	return cpu->caar;
+		case M68K_REG_PREF_ADDR:	return cpu->pref_addr;
+		case M68K_REG_PREF_DATA:	return cpu->pref_data;
+		case M68K_REG_PPC:	return MASK_OUT_ABOVE_32(cpu->ppc);
+		case M68K_REG_IR:	return cpu->ir;
+		case M68K_REG_CPU_TYPE:
+			switch(cpu->cpu_type)
+			{
+				case CPU_TYPE_000:		return (unsigned int)M68K_CPU_TYPE_68000;
+				case CPU_TYPE_010:		return (unsigned int)M68K_CPU_TYPE_68010;
+				case CPU_TYPE_EC020:	return (unsigned int)M68K_CPU_TYPE_68EC020;
+				case CPU_TYPE_020:		return (unsigned int)M68K_CPU_TYPE_68020;
+			}
+			return M68K_CPU_TYPE_INVALID;
+		default:			return 0;
+	}
+	return 0;
+}
+
+void m68k_set_reg(m68k_register_t regnum, unsigned int value)
+{
+	switch(regnum)
+	{
+		case M68K_REG_D0:	REG_D[0] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D1:	REG_D[1] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D2:	REG_D[2] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D3:	REG_D[3] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D4:	REG_D[4] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D5:	REG_D[5] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D6:	REG_D[6] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_D7:	REG_D[7] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A0:	REG_A[0] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A1:	REG_A[1] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A2:	REG_A[2] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A3:	REG_A[3] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A4:	REG_A[4] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A5:	REG_A[5] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A6:	REG_A[6] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_A7:	REG_A[7] = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_PC:	m68ki_jump(MASK_OUT_ABOVE_32(value)); return;
+		case M68K_REG_SR:	m68ki_set_sr(value); return;
+		case M68K_REG_SP:	REG_SP = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_USP:	if(FLAG_S)
+								REG_USP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_ISP:	if(FLAG_S && !FLAG_M)
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_ISP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_MSP:	if(FLAG_S && FLAG_M)
+								REG_SP = MASK_OUT_ABOVE_32(value);
+							else
+								REG_MSP = MASK_OUT_ABOVE_32(value);
+							return;
+		case M68K_REG_VBR:	REG_VBR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_SFC:	REG_SFC = value & 7; return;
+		case M68K_REG_DFC:	REG_DFC = value & 7; return;
+		case M68K_REG_CACR:	REG_CACR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_CAAR:	REG_CAAR = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_PPC:	REG_PPC = MASK_OUT_ABOVE_32(value); return;
+		case M68K_REG_IR:	REG_IR = MASK_OUT_ABOVE_16(value); return;
+		case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return;
+		default:			return;
+	}
+}
+
+/* Set the callbacks */
+void m68k_set_int_ack_callback(int  (*callback)(int int_level))
+{
+	CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback;
+}
+
+void m68k_set_bkpt_ack_callback(void  (*callback)(unsigned int data))
+{
+	CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback;
+}
+
+void m68k_set_reset_instr_callback(void  (*callback)(void))
+{
+	CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback;
+}
+
+void m68k_set_pc_changed_callback(void  (*callback)(unsigned int new_pc))
+{
+	CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback;
+}
+
+void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc))
+{
+	CALLBACK_SET_FC = callback ? callback : default_set_fc_callback;
+}
+
+void m68k_set_instr_hook_callback(void  (*callback)(void))
+{
+	CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback;
+}
+
+#include <stdio.h>
+/* Set the CPU type. */
+void m68k_set_cpu_type(unsigned int cpu_type)
+{
+	switch(cpu_type)
+	{
+		case M68K_CPU_TYPE_68000:
+			CPU_TYPE         = CPU_TYPE_000;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[0];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[0];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 2;
+			CYC_DBCC_F_NOEXP = -2;
+			CYC_DBCC_F_EXP   = 2;
+			CYC_SCC_R_TRUE   = 2;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 3;
+			CYC_SHIFT        = 1;
+			CYC_RESET        = 132;
+			return;
+		case M68K_CPU_TYPE_68010:
+			CPU_TYPE         = CPU_TYPE_010;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[1];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[1];
+			CYC_BCC_NOTAKE_B = -4;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 6;
+			CYC_SCC_R_TRUE   = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 3;
+			CYC_SHIFT        = 1;
+			CYC_RESET        = 130;
+			return;
+		case M68K_CPU_TYPE_68EC020:
+			CPU_TYPE         = CPU_TYPE_EC020;
+			CPU_ADDRESS_MASK = 0x00ffffff;
+			CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[2];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[2];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 4;
+			CYC_SCC_R_TRUE   = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 2;
+			CYC_SHIFT        = 0;
+			CYC_RESET        = 518;
+			return;
+		case M68K_CPU_TYPE_68020:
+			CPU_TYPE         = CPU_TYPE_020;
+			CPU_ADDRESS_MASK = 0xffffffff;
+			CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */
+			CYC_INSTRUCTION  = m68ki_cycles[2];
+			CYC_EXCEPTION    = m68ki_exception_cycle_table[2];
+			CYC_BCC_NOTAKE_B = -2;
+			CYC_BCC_NOTAKE_W = 0;
+			CYC_DBCC_F_NOEXP = 0;
+			CYC_DBCC_F_EXP   = 4;
+			CYC_SCC_R_TRUE   = 0;
+			CYC_MOVEM_W      = 2;
+			CYC_MOVEM_L      = 2;
+			CYC_SHIFT        = 0;
+			CYC_RESET        = 518;
+			return;
+	}
+}
+
+/* Execute some instructions until we use up num_cycles clock cycles */
+/* ASG: removed per-instruction interrupt checks */
+int m68k_execute(int num_cycles)
+{
+	/* Make sure we're not stopped */
+	if(!CPU_STOPPED)
+	{
+		/* Set our pool of clock cycles available */
+		SET_CYCLES(num_cycles);
+		m68ki_initial_cycles = num_cycles;
+
+		/* ASG: update cycles */
+		USE_CYCLES(CPU_INT_CYCLES);
+		CPU_INT_CYCLES = 0;
+
+		/* Return point if we had an address error */
+		m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */
+
+		/* Main loop.  Keep going until we run out of clock cycles */
+		do
+		{
+			/* Set tracing accodring to T1. (T0 is done inside instruction) */
+			m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
+
+			/* Set the address space for reads */
+			m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */
+
+			/* Call external hook to peek at CPU */
+			m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */
+
+			/* Record previous program counter */
+			REG_PPC = REG_PC;
+
+			/* Read an instruction and call its handler */
+			REG_IR = m68ki_read_imm_16();
+			m68ki_instruction_jump_table[REG_IR]();
+			USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
+
+			/* Trace m68k_exception, if necessary */
+			m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */
+		} while(GET_CYCLES() > 0);
+
+		/* set previous PC to current PC for the next entry into the loop */
+		REG_PPC = REG_PC;
+
+		/* ASG: update cycles */
+		USE_CYCLES(CPU_INT_CYCLES);
+		CPU_INT_CYCLES = 0;
+
+		/* return how many clocks we used */
+		return m68ki_initial_cycles - GET_CYCLES();
+	}
+
+	/* We get here if the CPU is stopped or halted */
+	SET_CYCLES(0);
+	CPU_INT_CYCLES = 0;
+
+	return num_cycles;
+}
+
+
+int m68k_cycles_run(void)
+{
+	return m68ki_initial_cycles - GET_CYCLES();
+}
+
+int m68k_cycles_remaining(void)
+{
+	return GET_CYCLES();
+}
+
+/* Change the timeslice */
+void m68k_modify_timeslice(int cycles)
+{
+	m68ki_initial_cycles += cycles;
+	ADD_CYCLES(cycles);
+}
+
+
+void m68k_end_timeslice(void)
+{
+	m68ki_initial_cycles = GET_CYCLES();
+	SET_CYCLES(0);
+}
+
+
+/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
+/* KS: Modified so that IPL* bits match with mask positions in the SR
+ *     and cleaned out remenants of the interrupt controller.
+ */
+void m68k_set_irq(unsigned int int_level)
+{
+	uint old_level = CPU_INT_LEVEL;
+	CPU_INT_LEVEL = int_level << 8;
+
+	/* A transition from < 7 to 7 always interrupts (NMI) */
+	/* Note: Level 7 can also level trigger like a normal IRQ */
+	if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700)
+		m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */
+	else
+		m68ki_check_interrupts(); /* Level triggered (IRQ) */
+}
+
+void m68k_init(void)
+{
+	static uint emulation_initialized = 0;
+
+	/* The first call to this function initializes the opcode handler jump table */
+	if(!emulation_initialized)
+		{
+		m68ki_build_opcode_table();
+		emulation_initialized = 1;
+	}
+
+	m68k_set_int_ack_callback(NULL);
+	m68k_set_bkpt_ack_callback(NULL);
+	m68k_set_reset_instr_callback(NULL);
+	m68k_set_pc_changed_callback(NULL);
+	m68k_set_fc_callback(NULL);
+	m68k_set_instr_hook_callback(NULL);
+}
+
+/* Pulse the RESET line on the CPU */
+void m68k_pulse_reset(void)
+{
+	/* Clear all stop levels and eat up all remaining cycles */
+	CPU_STOPPED = 0;
+	SET_CYCLES(0);
+
+	CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+	CPU_INSTR_MODE = INSTRUCTION_YES;
+
+	/* Turn off tracing */
+	FLAG_T1 = FLAG_T0 = 0;
+	m68ki_clear_trace();
+	/* Interrupt mask to level 7 */
+	FLAG_INT_MASK = 0x0700;
+	/* Reset VBR */
+	REG_VBR = 0;
+	/* Go to supervisor mode */
+	m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR);
+
+	/* Invalidate the prefetch queue */
+#if M68K_EMULATE_PREFETCH
+	/* Set to arbitrary number since our first fetch is from 0 */
+	CPU_PREF_ADDR = 0x1000;
+#endif /* M68K_EMULATE_PREFETCH */
+
+	/* Read the initial stack pointer and program counter */
+	m68ki_jump(0);
+	REG_SP = m68ki_read_imm_32();
+	REG_PC = m68ki_read_imm_32();
+	m68ki_jump(REG_PC);
+
+	CPU_RUN_MODE = RUN_MODE_NORMAL;
+}
+
+/* Pulse the HALT line on the CPU */
+void m68k_pulse_halt(void)
+{
+	CPU_STOPPED |= STOP_LEVEL_HALT;
+}
+
+
+/* Get and set the current CPU context */
+/* This is to allow for multiple CPUs */
+unsigned int m68k_context_size()
+{
+	return sizeof(m68ki_cpu_core);
+}
+
+unsigned int m68k_get_context(void* dst)
+{
+	if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu;
+	return sizeof(m68ki_cpu_core);
+}
+
+void m68k_set_context(void* src)
+{
+	if(src) m68ki_cpu = *(m68ki_cpu_core*)src;
+}
+
+
+
+/* ======================================================================== */
+/* ============================== MAME STUFF ============================== */
+/* ======================================================================== */
+
+#if M68K_COMPILE_FOR_MAME == OPT_ON
+
+#include "state.h"
+
+static struct {
+	UINT16 sr;
+	int stopped;
+	int halted;
+} m68k_substate;
+
+static void m68k_prepare_substate(void)
+{
+	m68k_substate.sr = m68ki_get_sr();
+	m68k_substate.stopped = (CPU_STOPPED & STOP_LEVEL_STOP) != 0;
+	m68k_substate.halted  = (CPU_STOPPED & STOP_LEVEL_HALT) != 0;
+}
+
+static void m68k_post_load(void)
+{
+	m68ki_set_sr_noint_nosp(m68k_substate.sr);
+	CPU_STOPPED = m68k_substate.stopped ? STOP_LEVEL_STOP : 0
+		        | m68k_substate.halted  ? STOP_LEVEL_HALT : 0;
+	m68ki_jump(REG_PC);
+}
+
+void m68k_state_register(const char *type)
+{
+	int cpu = cpu_getactivecpu();
+
+	state_save_register_UINT32(type, cpu, "D"         , REG_D, 8);
+	state_save_register_UINT32(type, cpu, "A"         , REG_A, 8);
+	state_save_register_UINT32(type, cpu, "PPC"       , &REG_PPC, 1);
+	state_save_register_UINT32(type, cpu, "PC"        , &REG_PC, 1);
+	state_save_register_UINT32(type, cpu, "USP"       , &REG_USP, 1);
+	state_save_register_UINT32(type, cpu, "ISP"       , &REG_ISP, 1);
+	state_save_register_UINT32(type, cpu, "MSP"       , &REG_MSP, 1);
+	state_save_register_UINT32(type, cpu, "VBR"       , &REG_VBR, 1);
+	state_save_register_UINT32(type, cpu, "SFC"       , &REG_SFC, 1);
+	state_save_register_UINT32(type, cpu, "DFC"       , &REG_DFC, 1);
+	state_save_register_UINT32(type, cpu, "CACR"      , &REG_CACR, 1);
+	state_save_register_UINT32(type, cpu, "CAAR"      , &REG_CAAR, 1);
+	state_save_register_UINT16(type, cpu, "SR"        , &m68k_substate.sr, 1);
+	state_save_register_UINT32(type, cpu, "INT_LEVEL" , &CPU_INT_LEVEL, 1);
+	state_save_register_UINT32(type, cpu, "INT_CYCLES", &CPU_INT_CYCLES, 1);
+	state_save_register_int   (type, cpu, "STOPPED"   , &m68k_substate.stopped);
+	state_save_register_int   (type, cpu, "HALTED"    , &m68k_substate.halted);
+	state_save_register_UINT32(type, cpu, "PREF_ADDR" , &CPU_PREF_ADDR, 1);
+	state_save_register_UINT32(type, cpu, "PREF_DATA" , &CPU_PREF_DATA, 1);
+	state_save_register_func_presave(m68k_prepare_substate);
+	state_save_register_func_postload(m68k_post_load);
+}
+
+#endif /* M68K_COMPILE_FOR_MAME */
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/MCUME_pico2/picogenold/musashi34/m68kcpu.h b/MCUME_pico2/picogenold/musashi34/m68kcpu.h
new file mode 100644
index 0000000..91e5e72
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kcpu.h
@@ -0,0 +1,1986 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.4
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+
+
+#ifndef M68KCPU__HEADER
+#define M68KCPU__HEADER
+
+#include "m68k.h"
+#include <limits.h>
+
+#if M68K_EMULATE_ADDRESS_ERROR
+#include <setjmp.h>
+#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+/* ======================================================================== */
+/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */
+/* ======================================================================== */
+
+/* Check for > 32bit sizes */
+#if UINT_MAX > 0xffffffff
+	#define M68K_INT_GT_32_BIT  1
+#else
+	#define M68K_INT_GT_32_BIT  0
+#endif
+
+/* Data types used in this emulation core */
+#undef sint8
+#undef sint16
+#undef sint32
+#undef sint64
+#undef uint8
+#undef uint16
+#undef uint32
+#undef uint64
+#undef sint
+#undef uint
+
+#define sint8  signed   char			/* ASG: changed from char to signed char */
+#define sint16 signed   short
+#define sint32 signed   long
+#define uint8  unsigned char
+#define uint16 unsigned short
+#define uint32 unsigned long
+
+/* signed and unsigned int must be at least 32 bits wide */
+#define sint   signed   int
+//newlib typedefs this
+//#define uint   unsigned int
+typedef unsigned int uint;
+
+#if M68K_USE_64_BIT
+#define sint64 signed   long long
+#define uint64 unsigned long long
+#else
+#define sint64 sint32
+#define uint64 uint32
+#endif /* M68K_USE_64_BIT */
+
+
+
+/* Allow for architectures that don't have 8-bit sizes */
+#if UCHAR_MAX == 0xff
+	#define MAKE_INT_8(A) (sint8)(A)
+#else
+	#undef  sint8
+	#define sint8  signed   int
+	#undef  uint8
+	#define uint8  unsigned int
+	INLINE sint MAKE_INT_8(uint value)
+	{
+		return (value & 0x80) ? value | ~0xff : value & 0xff;
+	}
+#endif /* UCHAR_MAX == 0xff */
+
+
+/* Allow for architectures that don't have 16-bit sizes */
+#if USHRT_MAX == 0xffff
+	#define MAKE_INT_16(A) (sint16)(A)
+#else
+	#undef  sint16
+	#define sint16 signed   int
+	#undef  uint16
+	#define uint16 unsigned int
+	INLINE sint MAKE_INT_16(uint value)
+	{
+		return (value & 0x8000) ? value | ~0xffff : value & 0xffff;
+	}
+#endif /* USHRT_MAX == 0xffff */
+
+
+/* Allow for architectures that don't have 32-bit sizes */
+#if ULONG_MAX == 0xffffffff
+	#define MAKE_INT_32(A) (sint32)(A)
+#else
+	#undef  sint32
+	#define sint32  signed   int
+	#undef  uint32
+	#define uint32  unsigned int
+	INLINE sint MAKE_INT_32(uint value)
+	{
+		return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff;
+	}
+#endif /* ULONG_MAX == 0xffffffff */
+
+
+
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/* ======================================================================== */
+
+/* Exception Vectors handled by emulation */
+#define EXCEPTION_BUS_ERROR                2 /* This one is not emulated! */
+#define EXCEPTION_ADDRESS_ERROR            3 /* This one is partially emulated (doesn't stack a proper frame yet) */
+#define EXCEPTION_ILLEGAL_INSTRUCTION      4
+#define EXCEPTION_ZERO_DIVIDE              5
+#define EXCEPTION_CHK                      6
+#define EXCEPTION_TRAPV                    7
+#define EXCEPTION_PRIVILEGE_VIOLATION      8
+#define EXCEPTION_TRACE                    9
+#define EXCEPTION_1010                    10
+#define EXCEPTION_1111                    11
+#define EXCEPTION_FORMAT_ERROR            14
+#define EXCEPTION_UNINITIALIZED_INTERRUPT 15
+#define EXCEPTION_SPURIOUS_INTERRUPT      24
+#define EXCEPTION_INTERRUPT_AUTOVECTOR    24
+#define EXCEPTION_TRAP_BASE               32
+
+/* Function codes set by CPU during data/address bus activity */
+#define FUNCTION_CODE_USER_DATA          1
+#define FUNCTION_CODE_USER_PROGRAM       2
+#define FUNCTION_CODE_SUPERVISOR_DATA    5
+#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6
+#define FUNCTION_CODE_CPU_SPACE          7
+
+/* CPU types for deciding what to emulate */
+#define CPU_TYPE_000   1
+#define CPU_TYPE_010   2
+#define CPU_TYPE_EC020 4
+#define CPU_TYPE_020   8
+
+/* Different ways to stop the CPU */
+#define STOP_LEVEL_STOP 1
+#define STOP_LEVEL_HALT 2
+
+/* Used for 68000 address error processing */
+#define INSTRUCTION_YES 0
+#define INSTRUCTION_NO  0x08
+#define MODE_READ       0x10
+#define MODE_WRITE      0
+
+#define RUN_MODE_NORMAL          0
+#define RUN_MODE_BERR_AERR_RESET 1
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/* ======================================================================== */
+/* ================================ MACROS ================================ */
+/* ======================================================================== */
+
+
+/* ---------------------------- General Macros ---------------------------- */
+
+/* Bit Isolation Macros */
+#define BIT_0(A)  ((A) & 0x00000001)
+#define BIT_1(A)  ((A) & 0x00000002)
+#define BIT_2(A)  ((A) & 0x00000004)
+#define BIT_3(A)  ((A) & 0x00000008)
+#define BIT_4(A)  ((A) & 0x00000010)
+#define BIT_5(A)  ((A) & 0x00000020)
+#define BIT_6(A)  ((A) & 0x00000040)
+#define BIT_7(A)  ((A) & 0x00000080)
+#define BIT_8(A)  ((A) & 0x00000100)
+#define BIT_9(A)  ((A) & 0x00000200)
+#define BIT_A(A)  ((A) & 0x00000400)
+#define BIT_B(A)  ((A) & 0x00000800)
+#define BIT_C(A)  ((A) & 0x00001000)
+#define BIT_D(A)  ((A) & 0x00002000)
+#define BIT_E(A)  ((A) & 0x00004000)
+#define BIT_F(A)  ((A) & 0x00008000)
+#define BIT_10(A) ((A) & 0x00010000)
+#define BIT_11(A) ((A) & 0x00020000)
+#define BIT_12(A) ((A) & 0x00040000)
+#define BIT_13(A) ((A) & 0x00080000)
+#define BIT_14(A) ((A) & 0x00100000)
+#define BIT_15(A) ((A) & 0x00200000)
+#define BIT_16(A) ((A) & 0x00400000)
+#define BIT_17(A) ((A) & 0x00800000)
+#define BIT_18(A) ((A) & 0x01000000)
+#define BIT_19(A) ((A) & 0x02000000)
+#define BIT_1A(A) ((A) & 0x04000000)
+#define BIT_1B(A) ((A) & 0x08000000)
+#define BIT_1C(A) ((A) & 0x10000000)
+#define BIT_1D(A) ((A) & 0x20000000)
+#define BIT_1E(A) ((A) & 0x40000000)
+#define BIT_1F(A) ((A) & 0x80000000)
+
+/* Get the most significant bit for specific sizes */
+#define GET_MSB_8(A)  ((A) & 0x80)
+#define GET_MSB_9(A)  ((A) & 0x100)
+#define GET_MSB_16(A) ((A) & 0x8000)
+#define GET_MSB_17(A) ((A) & 0x10000)
+#define GET_MSB_32(A) ((A) & 0x80000000)
+#if M68K_USE_64_BIT
+#define GET_MSB_33(A) ((A) & 0x100000000)
+#endif /* M68K_USE_64_BIT */
+
+/* Isolate nibbles */
+#define LOW_NIBBLE(A)  ((A) & 0x0f)
+#define HIGH_NIBBLE(A) ((A) & 0xf0)
+
+/* These are used to isolate 8, 16, and 32 bit sizes */
+#define MASK_OUT_ABOVE_2(A)  ((A) & 3)
+#define MASK_OUT_ABOVE_8(A)  ((A) & 0xff)
+#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff)
+#define MASK_OUT_BELOW_2(A)  ((A) & ~3)
+#define MASK_OUT_BELOW_8(A)  ((A) & ~0xff)
+#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff)
+
+/* No need to mask if we are 32 bit */
+#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT
+	#define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff)
+	#define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff)
+#else
+	#define MASK_OUT_ABOVE_32(A) (A)
+	#define MASK_OUT_BELOW_32(A) 0
+#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */
+
+/* Simulate address lines of 68k family */
+#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)
+
+
+/* Shift & Rotate Macros. */
+#define LSL(A, C) ((A) << (C))
+#define LSR(A, C) ((A) >> (C))
+
+/* Some > 32-bit optimizations */
+#if M68K_INT_GT_32_BIT
+	/* Shift left and right */
+	#define LSR_32(A, C) ((A) >> (C))
+	#define LSL_32(A, C) ((A) << (C))
+#else
+	/* We have to do this because the morons at ANSI decided that shifts
+	 * by >= data size are undefined.
+	 */
+	#define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0)
+	#define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0)
+#endif /* M68K_INT_GT_32_BIT */
+
+#if M68K_USE_64_BIT
+	#define LSL_32_64(A, C) ((A) << (C))
+	#define LSR_32_64(A, C) ((A) >> (C))
+	#define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C)))
+	#define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C)))
+#endif /* M68K_USE_64_BIT */
+
+#define ROL_8(A, C)      MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C)))
+#define ROL_9(A, C)                      (LSL(A, C) | LSR(A, 9-(C)))
+#define ROL_16(A, C)    MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C)))
+#define ROL_17(A, C)                     (LSL(A, C) | LSR(A, 17-(C)))
+#define ROL_32(A, C)    MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C)))
+#define ROL_33(A, C)                     (LSL_32(A, C) | LSR_32(A, 33-(C)))
+
+#define ROR_8(A, C)      MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C)))
+#define ROR_9(A, C)                      (LSR(A, C) | LSL(A, 9-(C)))
+#define ROR_16(A, C)    MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C)))
+#define ROR_17(A, C)                     (LSR(A, C) | LSL(A, 17-(C)))
+#define ROR_32(A, C)    MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C)))
+#define ROR_33(A, C)                     (LSR_32(A, C) | LSL_32(A, 33-(C)))
+
+
+
+/* ------------------------------ CPU Access ------------------------------ */
+
+/* Access the CPU registers */
+#define CPU_TYPE         m68ki_cpu.cpu_type
+
+#define REG_DA           m68ki_cpu.dar /* easy access to data and address regs */
+#define REG_D            m68ki_cpu.dar
+#define REG_A            (m68ki_cpu.dar+8)
+#define REG_PPC 		 m68ki_cpu.ppc
+#define REG_PC           m68ki_cpu.pc
+#define REG_SP_BASE      m68ki_cpu.sp
+#define REG_USP          m68ki_cpu.sp[0]
+#define REG_ISP          m68ki_cpu.sp[4]
+#define REG_MSP          m68ki_cpu.sp[6]
+#define REG_SP           m68ki_cpu.dar[15]
+#define REG_VBR          m68ki_cpu.vbr
+#define REG_SFC          m68ki_cpu.sfc
+#define REG_DFC          m68ki_cpu.dfc
+#define REG_CACR         m68ki_cpu.cacr
+#define REG_CAAR         m68ki_cpu.caar
+#define REG_IR           m68ki_cpu.ir
+
+#define FLAG_T1          m68ki_cpu.t1_flag
+#define FLAG_T0          m68ki_cpu.t0_flag
+#define FLAG_S           m68ki_cpu.s_flag
+#define FLAG_M           m68ki_cpu.m_flag
+#define FLAG_X           m68ki_cpu.x_flag
+#define FLAG_N           m68ki_cpu.n_flag
+#define FLAG_Z           m68ki_cpu.not_z_flag
+#define FLAG_V           m68ki_cpu.v_flag
+#define FLAG_C           m68ki_cpu.c_flag
+#define FLAG_INT_MASK    m68ki_cpu.int_mask
+
+#define CPU_INT_LEVEL    m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
+#define CPU_INT_CYCLES   m68ki_cpu.int_cycles /* ASG */
+#define CPU_STOPPED      m68ki_cpu.stopped
+#define CPU_PREF_ADDR    m68ki_cpu.pref_addr
+#define CPU_PREF_DATA    m68ki_cpu.pref_data
+#define CPU_ADDRESS_MASK m68ki_cpu.address_mask
+#define CPU_SR_MASK      m68ki_cpu.sr_mask
+#define CPU_INSTR_MODE   m68ki_cpu.instr_mode
+#define CPU_RUN_MODE     m68ki_cpu.run_mode
+
+#define CYC_INSTRUCTION  m68ki_cpu.cyc_instruction
+#define CYC_EXCEPTION    m68ki_cpu.cyc_exception
+#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b
+#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w
+#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp
+#define CYC_DBCC_F_EXP   m68ki_cpu.cyc_dbcc_f_exp
+#define CYC_SCC_R_TRUE   m68ki_cpu.cyc_scc_r_true
+#define CYC_MOVEM_W      m68ki_cpu.cyc_movem_w
+#define CYC_MOVEM_L      m68ki_cpu.cyc_movem_l
+#define CYC_SHIFT        m68ki_cpu.cyc_shift
+#define CYC_RESET        m68ki_cpu.cyc_reset
+
+
+#define CALLBACK_INT_ACK     m68ki_cpu.int_ack_callback
+#define CALLBACK_BKPT_ACK    m68ki_cpu.bkpt_ack_callback
+#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback
+#define CALLBACK_PC_CHANGED  m68ki_cpu.pc_changed_callback
+#define CALLBACK_SET_FC      m68ki_cpu.set_fc_callback
+#define CALLBACK_INSTR_HOOK  m68ki_cpu.instr_hook_callback
+
+
+
+/* ----------------------------- Configuration ---------------------------- */
+
+/* These defines are dependant on the configuration defines in m68kconf.h */
+
+/* Disable certain comparisons if we're not using all CPU types */
+#if M68K_EMULATE_020
+	#define CPU_TYPE_IS_020_PLUS(A)    ((A) & CPU_TYPE_020)
+	#define CPU_TYPE_IS_020_LESS(A)    1
+#else
+	#define CPU_TYPE_IS_020_PLUS(A)    0
+	#define CPU_TYPE_IS_020_LESS(A)    1
+#endif
+
+#if M68K_EMULATE_EC020
+	#define CPU_TYPE_IS_EC020_PLUS(A)  ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))
+	#define CPU_TYPE_IS_EC020_LESS(A)  ((A) & (CPU_TYPE_000 | CPU_TYPE_010 | CPU_TYPE_EC020))
+#else
+	#define CPU_TYPE_IS_EC020_PLUS(A)  CPU_TYPE_IS_020_PLUS(A)
+	#define CPU_TYPE_IS_EC020_LESS(A)  CPU_TYPE_IS_020_LESS(A)
+#endif
+
+#if M68K_EMULATE_010
+	#define CPU_TYPE_IS_010(A)         ((A) == CPU_TYPE_010)
+	#define CPU_TYPE_IS_010_PLUS(A)    ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020))
+	#define CPU_TYPE_IS_010_LESS(A)    ((A) & (CPU_TYPE_000 | CPU_TYPE_010))
+#else
+	#define CPU_TYPE_IS_010(A)         0
+	#define CPU_TYPE_IS_010_PLUS(A)    CPU_TYPE_IS_EC020_PLUS(A)
+	#define CPU_TYPE_IS_010_LESS(A)    CPU_TYPE_IS_EC020_LESS(A)
+#endif
+
+#if M68K_EMULATE_020 || M68K_EMULATE_EC020
+	#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020))
+#else
+	#define CPU_TYPE_IS_020_VARIANT(A) 0
+#endif
+
+#if M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010
+	#define CPU_TYPE_IS_000(A)         ((A) == CPU_TYPE_000)
+#else
+	#define CPU_TYPE_IS_000(A)         1
+#endif
+
+
+#if !M68K_SEPARATE_READS
+#define m68k_read_immediate_16(A) m68ki_read_program_16(A)
+#define m68k_read_immediate_32(A) m68ki_read_program_32(A)
+
+#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A)
+#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A)
+#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A)
+#endif /* M68K_SEPARATE_READS */
+
+
+/* Enable or disable callback functions */
+#if M68K_EMULATE_INT_ACK
+	#if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER
+		#define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A)
+	#else
+		#define m68ki_int_ack(A) CALLBACK_INT_ACK(A)
+	#endif
+#else
+	/* Default action is to used autovector mode, which is most common */
+	#define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR
+#endif /* M68K_EMULATE_INT_ACK */
+
+#if M68K_EMULATE_BKPT_ACK
+	#if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER
+		#define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A)
+	#else
+		#define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A)
+	#endif
+#else
+	#define m68ki_bkpt_ack(A)
+#endif /* M68K_EMULATE_BKPT_ACK */
+
+#if M68K_EMULATE_RESET
+	#if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER
+		#define m68ki_output_reset() M68K_RESET_CALLBACK()
+	#else
+		#define m68ki_output_reset() CALLBACK_RESET_INSTR()
+	#endif
+#else
+	#define m68ki_output_reset()
+#endif /* M68K_EMULATE_RESET */
+
+#if M68K_INSTRUCTION_HOOK
+	#if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER
+		#define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK()
+	#else
+		#define m68ki_instr_hook() CALLBACK_INSTR_HOOK()
+	#endif
+#else
+	#define m68ki_instr_hook()
+#endif /* M68K_INSTRUCTION_HOOK */
+
+#if M68K_MONITOR_PC
+	#if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER
+		#define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A))
+	#else
+		#define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A))
+	#endif
+#else
+	#define m68ki_pc_changed(A)
+#endif /* M68K_MONITOR_PC */
+
+
+/* Enable or disable function code emulation */
+#if M68K_EMULATE_FC
+	#if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER
+		#define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A)
+	#else
+		#define m68ki_set_fc(A) CALLBACK_SET_FC(A)
+	#endif
+	#define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA
+	#define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM
+	#define m68ki_get_address_space() m68ki_address_space
+#else
+	#define m68ki_set_fc(A)
+	#define m68ki_use_data_space()
+	#define m68ki_use_program_space()
+	#define m68ki_get_address_space() FUNCTION_CODE_USER_DATA
+#endif /* M68K_EMULATE_FC */
+
+
+/* Enable or disable trace emulation */
+#if M68K_EMULATE_TRACE
+	/* Initiates trace checking before each instruction (t1) */
+	#define m68ki_trace_t1() m68ki_tracing = FLAG_T1
+	/* adds t0 to trace checking if we encounter change of flow */
+	#define m68ki_trace_t0() m68ki_tracing |= FLAG_T0
+	/* Clear all tracing */
+	#define m68ki_clear_trace() m68ki_tracing = 0
+	/* Cause a trace exception if we are tracing */
+	#define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace()
+#else
+	#define m68ki_trace_t1()
+	#define m68ki_trace_t0()
+	#define m68ki_clear_trace()
+	#define m68ki_exception_if_trace()
+#endif /* M68K_EMULATE_TRACE */
+
+
+
+/* Address error */
+#if M68K_EMULATE_ADDRESS_ERROR
+	#include <setjmp.h>
+	extern jmp_buf m68ki_aerr_trap;
+
+	#define m68ki_set_address_error_trap() \
+		if(setjmp(m68ki_aerr_trap) != 0) \
+		{ \
+			m68ki_exception_address_error(); \
+			if(CPU_STOPPED) \
+			{ \
+				SET_CYCLES(0); \
+				CPU_INT_CYCLES = 0; \
+				return m68ki_initial_cycles; \
+			} \
+			/* ensure we don't re-enter execution loop after an
+			   address error if there's no more cycles remaining */ \
+			if(GET_CYCLES() <= 0) \
+			{ \
+				/* return how many clocks we used */ \
+				return m68ki_initial_cycles - GET_CYCLES(); \
+			} \
+		}
+
+	#define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \
+		if((ADDR)&1) \
+		{ \
+			m68ki_aerr_address = ADDR; \
+			m68ki_aerr_write_mode = WRITE_MODE; \
+			m68ki_aerr_fc = FC; \
+			longjmp(m68ki_aerr_trap, 1); \
+		}
+#else
+	#define m68ki_set_address_error_trap()
+	#define m68ki_check_address_error(ADDR, WRITE_MODE, FC)
+#endif /* M68K_ADDRESS_ERROR */
+
+/* Logging */
+#if M68K_LOG_ENABLE
+	#include <stdio.h>
+	extern FILE* M68K_LOG_FILEHANDLE
+	extern char* m68ki_cpu_names[];
+
+	#define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A
+	#if M68K_LOG_1010_1111
+		#define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A
+	#else
+		#define M68K_DO_LOG_EMU(A)
+	#endif
+#else
+	#define M68K_DO_LOG(A)
+	#define M68K_DO_LOG_EMU(A)
+#endif
+
+
+
+/* -------------------------- EA / Operand Access ------------------------- */
+
+/*
+ * The general instruction format follows this pattern:
+ * .... XXX. .... .YYY
+ * where XXX is register X and YYY is register Y
+ */
+/* Data Register Isolation */
+#define DX (REG_D[(REG_IR >> 9) & 7])
+#define DY (REG_D[REG_IR & 7])
+/* Address Register Isolation */
+#define AX (REG_A[(REG_IR >> 9) & 7])
+#define AY (REG_A[REG_IR & 7])
+
+
+/* Effective Address Calculations */
+#define EA_AY_AI_8()   AY                                    /* address register indirect */
+#define EA_AY_AI_16()  EA_AY_AI_8()
+#define EA_AY_AI_32()  EA_AY_AI_8()
+#define EA_AY_PI_8()   (AY++)                                /* postincrement (size = byte) */
+#define EA_AY_PI_16()  ((AY+=2)-2)                           /* postincrement (size = word) */
+#define EA_AY_PI_32()  ((AY+=4)-4)                           /* postincrement (size = long) */
+#define EA_AY_PD_8()   (--AY)                                /* predecrement (size = byte) */
+#define EA_AY_PD_16()  (AY-=2)                               /* predecrement (size = word) */
+#define EA_AY_PD_32()  (AY-=4)                               /* predecrement (size = long) */
+#define EA_AY_DI_8()   (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */
+#define EA_AY_DI_16()  EA_AY_DI_8()
+#define EA_AY_DI_32()  EA_AY_DI_8()
+#define EA_AY_IX_8()   m68ki_get_ea_ix(AY)                   /* indirect + index */
+#define EA_AY_IX_16()  EA_AY_IX_8()
+#define EA_AY_IX_32()  EA_AY_IX_8()
+
+#define EA_AX_AI_8()   AX
+#define EA_AX_AI_16()  EA_AX_AI_8()
+#define EA_AX_AI_32()  EA_AX_AI_8()
+#define EA_AX_PI_8()   (AX++)
+#define EA_AX_PI_16()  ((AX+=2)-2)
+#define EA_AX_PI_32()  ((AX+=4)-4)
+#define EA_AX_PD_8()   (--AX)
+#define EA_AX_PD_16()  (AX-=2)
+#define EA_AX_PD_32()  (AX-=4)
+#define EA_AX_DI_8()   (AX+MAKE_INT_16(m68ki_read_imm_16()))
+#define EA_AX_DI_16()  EA_AX_DI_8()
+#define EA_AX_DI_32()  EA_AX_DI_8()
+#define EA_AX_IX_8()   m68ki_get_ea_ix(AX)
+#define EA_AX_IX_16()  EA_AX_IX_8()
+#define EA_AX_IX_32()  EA_AX_IX_8()
+
+#define EA_A7_PI_8()   ((REG_A[7]+=2)-2)
+#define EA_A7_PD_8()   (REG_A[7]-=2)
+
+#define EA_AW_8()      MAKE_INT_16(m68ki_read_imm_16())      /* absolute word */
+#define EA_AW_16()     EA_AW_8()
+#define EA_AW_32()     EA_AW_8()
+#define EA_AL_8()      m68ki_read_imm_32()                   /* absolute long */
+#define EA_AL_16()     EA_AL_8()
+#define EA_AL_32()     EA_AL_8()
+#define EA_PCDI_8()    m68ki_get_ea_pcdi()                   /* pc indirect + displacement */
+#define EA_PCDI_16()   EA_PCDI_8()
+#define EA_PCDI_32()   EA_PCDI_8()
+#define EA_PCIX_8()    m68ki_get_ea_pcix()                   /* pc indirect + index */
+#define EA_PCIX_16()   EA_PCIX_8()
+#define EA_PCIX_32()   EA_PCIX_8()
+
+
+#define OPER_I_8()     m68ki_read_imm_8()
+#define OPER_I_16()    m68ki_read_imm_16()
+#define OPER_I_32()    m68ki_read_imm_32()
+
+
+
+/* --------------------------- Status Register ---------------------------- */
+
+/* Flag Calculation Macros */
+#define CFLAG_8(A) (A)
+#define CFLAG_16(A) ((A)>>8)
+
+#if M68K_INT_GT_32_BIT
+	#define CFLAG_ADD_32(S, D, R) ((R)>>24)
+	#define CFLAG_SUB_32(S, D, R) ((R)>>24)
+#else
+	#define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23)
+	#define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23)
+#endif /* M68K_INT_GT_32_BIT */
+
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
+#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24)
+
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
+#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24)
+
+#define NFLAG_8(A) (A)
+#define NFLAG_16(A) ((A)>>8)
+#define NFLAG_32(A) ((A)>>24)
+#define NFLAG_64(A) ((A)>>56)
+
+#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A)
+#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A)
+#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A)
+
+
+/* Flag values */
+#define NFLAG_SET   0x80
+#define NFLAG_CLEAR 0
+#define CFLAG_SET   0x100
+#define CFLAG_CLEAR 0
+#define XFLAG_SET   0x100
+#define XFLAG_CLEAR 0
+#define VFLAG_SET   0x80
+#define VFLAG_CLEAR 0
+#define ZFLAG_SET   0
+#define ZFLAG_CLEAR 0xffffffff
+
+#define SFLAG_SET   4
+#define SFLAG_CLEAR 0
+#define MFLAG_SET   2
+#define MFLAG_CLEAR 0
+
+/* Turn flag values into 1 or 0 */
+#define XFLAG_AS_1() ((FLAG_X>>8)&1)
+#define NFLAG_AS_1() ((FLAG_N>>7)&1)
+#define VFLAG_AS_1() ((FLAG_V>>7)&1)
+#define ZFLAG_AS_1() (!FLAG_Z)
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)
+
+
+/* Conditions */
+#define COND_CS() (FLAG_C&0x100)
+#define COND_CC() (!COND_CS())
+#define COND_VS() (FLAG_V&0x80)
+#define COND_VC() (!COND_VS())
+#define COND_NE() FLAG_Z
+#define COND_EQ() (!COND_NE())
+#define COND_MI() (FLAG_N&0x80)
+#define COND_PL() (!COND_MI())
+#define COND_LT() ((FLAG_N^FLAG_V)&0x80)
+#define COND_GE() (!COND_LT())
+#define COND_HI() (COND_CC() && COND_NE())
+#define COND_LS() (COND_CS() || COND_EQ())
+#define COND_GT() (COND_GE() && COND_NE())
+#define COND_LE() (COND_LT() || COND_EQ())
+
+/* Reversed conditions */
+#define COND_NOT_CS() COND_CC()
+#define COND_NOT_CC() COND_CS()
+#define COND_NOT_VS() COND_VC()
+#define COND_NOT_VC() COND_VS()
+#define COND_NOT_NE() COND_EQ()
+#define COND_NOT_EQ() COND_NE()
+#define COND_NOT_MI() COND_PL()
+#define COND_NOT_PL() COND_MI()
+#define COND_NOT_LT() COND_GE()
+#define COND_NOT_GE() COND_LT()
+#define COND_NOT_HI() COND_LS()
+#define COND_NOT_LS() COND_HI()
+#define COND_NOT_GT() COND_LE()
+#define COND_NOT_LE() COND_GT()
+
+/* Not real conditions, but here for convenience */
+#define COND_XS() (FLAG_X&0x100)
+#define COND_XC() (!COND_XS)
+
+
+/* Get the condition code register */
+#define m68ki_get_ccr() ((COND_XS() >> 4) | \
+						 (COND_MI() >> 4) | \
+						 (COND_EQ() << 2) | \
+						 (COND_VS() >> 6) | \
+						 (COND_CS() >> 8))
+
+/* Get the status register */
+#define m68ki_get_sr() ( FLAG_T1              | \
+						 FLAG_T0              | \
+						(FLAG_S        << 11) | \
+						(FLAG_M        << 11) | \
+						 FLAG_INT_MASK        | \
+						 m68ki_get_ccr())
+
+
+
+/* ---------------------------- Cycle Counting ---------------------------- */
+
+#define ADD_CYCLES(A)    m68ki_remaining_cycles += (A)
+#define USE_CYCLES(A)    m68ki_remaining_cycles -= (A)
+#define SET_CYCLES(A)    m68ki_remaining_cycles = A
+#define GET_CYCLES()     m68ki_remaining_cycles
+#define USE_ALL_CYCLES() m68ki_remaining_cycles %= CYC_INSTRUCTION[REG_IR]
+
+
+
+/* ----------------------------- Read / Write ----------------------------- */
+
+/* Read from the current address space */
+#define m68ki_read_8(A)  m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space())
+#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space())
+
+/* Write to the current data space */
+#define m68ki_write_8(A, V)  m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+
+#if M68K_SIMULATE_PD_WRITES
+#define m68ki_write_32_pd(A, V) m68ki_write_32_pd_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#else
+#define m68ki_write_32_pd(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V)
+#endif
+
+/* map read immediate 8 to read immediate 16 */
+#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16())
+
+/* Map PC-relative reads */
+#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A)
+#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A)
+#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A)
+
+/* Read from the program space */
+#define m68ki_read_program_8(A) 	m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_16(A) 	m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+#define m68ki_read_program_32(A) 	m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM)
+
+/* Read from the data space */
+#define m68ki_read_data_8(A) 	m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_16(A) 	m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+#define m68ki_read_data_32(A) 	m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA)
+
+
+
+/* ======================================================================== */
+/* =============================== PROTOTYPES ============================= */
+/* ======================================================================== */
+
+typedef struct
+{
+	uint cpu_type;     /* CPU Type: 68000, 68010, 68EC020, or 68020 */
+	uint dar[16];      /* Data and Address Registers */
+	uint ppc;		   /* Previous program counter */
+	uint pc;           /* Program Counter */
+	uint sp[7];        /* User, Interrupt, and Master Stack Pointers */
+	uint vbr;          /* Vector Base Register (m68010+) */
+	uint sfc;          /* Source Function Code Register (m68010+) */
+	uint dfc;          /* Destination Function Code Register (m68010+) */
+	uint cacr;         /* Cache Control Register (m68020, unemulated) */
+	uint caar;         /* Cache Address Register (m68020, unemulated) */
+	uint ir;           /* Instruction Register */
+	uint t1_flag;      /* Trace 1 */
+	uint t0_flag;      /* Trace 0 */
+	uint s_flag;       /* Supervisor */
+	uint m_flag;       /* Master/Interrupt state */
+	uint x_flag;       /* Extend */
+	uint n_flag;       /* Negative */
+	uint not_z_flag;   /* Zero, inverted for speedups */
+	uint v_flag;       /* Overflow */
+	uint c_flag;       /* Carry */
+	uint int_mask;     /* I0-I2 */
+	uint int_level;    /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
+	uint int_cycles;   /* ASG: extra cycles from generated interrupts */
+	uint stopped;      /* Stopped state */
+	uint pref_addr;    /* Last prefetch address */
+	uint pref_data;    /* Data in the prefetch queue */
+	uint address_mask; /* Available address pins */
+	uint sr_mask;      /* Implemented status register bits */
+	uint instr_mode;   /* Stores whether we are in instruction mode or group 0/1 exception mode */
+	uint run_mode;     /* Stores whether we are processing a reset, bus error, address error, or something else */
+
+	/* Clocks required for instructions / exceptions */
+	uint cyc_bcc_notake_b;
+	uint cyc_bcc_notake_w;
+	uint cyc_dbcc_f_noexp;
+	uint cyc_dbcc_f_exp;
+	uint cyc_scc_r_true;
+	uint cyc_movem_w;
+	uint cyc_movem_l;
+	uint cyc_shift;
+	uint cyc_reset;
+	uint8* cyc_instruction;
+	uint8* cyc_exception;
+
+	/* Callbacks to host */
+	int  (*int_ack_callback)(int int_line);           /* Interrupt Acknowledge */
+	void (*bkpt_ack_callback)(unsigned int data);     /* Breakpoint Acknowledge */
+	void (*reset_instr_callback)(void);               /* Called when a RESET instruction is encountered */
+	void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */
+	void (*set_fc_callback)(unsigned int new_fc);     /* Called when the CPU function code changes */
+	void (*instr_hook_callback)(void);                /* Called every instruction cycle prior to execution */
+
+} m68ki_cpu_core;
+
+
+extern m68ki_cpu_core m68ki_cpu;
+extern sint           m68ki_remaining_cycles;
+extern uint           m68ki_tracing;
+extern const uint8          m68ki_shift_8_table[];
+extern const uint16         m68ki_shift_16_table[];
+extern const uint           m68ki_shift_32_table[];
+extern uint8          m68ki_exception_cycle_table[][256];
+extern uint           m68ki_address_space;
+extern uint8          m68ki_ea_idx_cycle_table[];
+
+extern uint           m68ki_aerr_address;
+extern uint           m68ki_aerr_write_mode;
+extern uint           m68ki_aerr_fc;
+
+/* Read data immediately after the program counter */
+INLINE uint m68ki_read_imm_16(void);
+INLINE uint m68ki_read_imm_32(void);
+
+/* Read data with specific function code */
+INLINE uint m68ki_read_8_fc  (uint address, uint fc);
+INLINE uint m68ki_read_16_fc (uint address, uint fc);
+INLINE uint m68ki_read_32_fc (uint address, uint fc);
+
+/* Write data with specific function code */
+INLINE void m68ki_write_8_fc (uint address, uint fc, uint value);
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value);
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value);
+#if M68K_SIMULATE_PD_WRITES
+INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value);
+#endif /* M68K_SIMULATE_PD_WRITES */
+
+/* Indexed and PC-relative ea fetching */
+INLINE uint m68ki_get_ea_pcdi(void);
+INLINE uint m68ki_get_ea_pcix(void);
+INLINE uint m68ki_get_ea_ix(uint An);
+
+/* Operand fetching */
+INLINE uint OPER_AY_AI_8(void);
+INLINE uint OPER_AY_AI_16(void);
+INLINE uint OPER_AY_AI_32(void);
+INLINE uint OPER_AY_PI_8(void);
+INLINE uint OPER_AY_PI_16(void);
+INLINE uint OPER_AY_PI_32(void);
+INLINE uint OPER_AY_PD_8(void);
+INLINE uint OPER_AY_PD_16(void);
+INLINE uint OPER_AY_PD_32(void);
+INLINE uint OPER_AY_DI_8(void);
+INLINE uint OPER_AY_DI_16(void);
+INLINE uint OPER_AY_DI_32(void);
+INLINE uint OPER_AY_IX_8(void);
+INLINE uint OPER_AY_IX_16(void);
+INLINE uint OPER_AY_IX_32(void);
+
+INLINE uint OPER_AX_AI_8(void);
+INLINE uint OPER_AX_AI_16(void);
+INLINE uint OPER_AX_AI_32(void);
+INLINE uint OPER_AX_PI_8(void);
+INLINE uint OPER_AX_PI_16(void);
+INLINE uint OPER_AX_PI_32(void);
+INLINE uint OPER_AX_PD_8(void);
+INLINE uint OPER_AX_PD_16(void);
+INLINE uint OPER_AX_PD_32(void);
+INLINE uint OPER_AX_DI_8(void);
+INLINE uint OPER_AX_DI_16(void);
+INLINE uint OPER_AX_DI_32(void);
+INLINE uint OPER_AX_IX_8(void);
+INLINE uint OPER_AX_IX_16(void);
+INLINE uint OPER_AX_IX_32(void);
+
+INLINE uint OPER_A7_PI_8(void);
+INLINE uint OPER_A7_PD_8(void);
+
+INLINE uint OPER_AW_8(void);
+INLINE uint OPER_AW_16(void);
+INLINE uint OPER_AW_32(void);
+INLINE uint OPER_AL_8(void);
+INLINE uint OPER_AL_16(void);
+INLINE uint OPER_AL_32(void);
+INLINE uint OPER_PCDI_8(void);
+INLINE uint OPER_PCDI_16(void);
+INLINE uint OPER_PCDI_32(void);
+INLINE uint OPER_PCIX_8(void);
+INLINE uint OPER_PCIX_16(void);
+INLINE uint OPER_PCIX_32(void);
+
+/* Stack operations */
+INLINE void m68ki_push_16(uint value);
+INLINE void m68ki_push_32(uint value);
+INLINE uint m68ki_pull_16(void);
+INLINE uint m68ki_pull_32(void);
+
+/* Program flow operations */
+INLINE void m68ki_jump(uint new_pc);
+INLINE void m68ki_jump_vector(uint vector);
+INLINE void m68ki_branch_8(uint offset);
+INLINE void m68ki_branch_16(uint offset);
+INLINE void m68ki_branch_32(uint offset);
+
+/* Status register operations. */
+INLINE void m68ki_set_s_flag(uint value);            /* Only bit 2 of value should be set (i.e. 4 or 0) */
+INLINE void m68ki_set_sm_flag(uint value);           /* only bits 1 and 2 of value should be set */
+INLINE void m68ki_set_ccr(uint value);               /* set the condition code register */
+INLINE void m68ki_set_sr(uint value);                /* set the status register */
+INLINE void m68ki_set_sr_noint(uint value);          /* set the status register */
+
+/* Exception processing */
+INLINE uint m68ki_init_exception(void);              /* Initial exception processing */
+
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */
+INLINE void m68ki_stack_frame_buserr(uint sr);
+
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector);
+INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector);
+INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc);
+INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc);
+
+INLINE void m68ki_exception_trap(uint vector);
+INLINE void m68ki_exception_trapN(uint vector);
+INLINE void m68ki_exception_trace(void);
+INLINE void m68ki_exception_privilege_violation(void);
+INLINE void m68ki_exception_1010(void);
+INLINE void m68ki_exception_1111(void);
+INLINE void m68ki_exception_illegal(void);
+INLINE void m68ki_exception_format_error(void);
+INLINE void m68ki_exception_address_error(void);
+INLINE void m68ki_exception_interrupt(uint int_level);
+INLINE void m68ki_check_interrupts(void);            /* ASG: check for interrupts */
+
+/* quick disassembly (used for logging) */
+char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
+
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+
+/* ---------------------------- Read Immediate ---------------------------- */
+
+/* Handles all immediate reads, does address error check, function code setting,
+ * and prefetching if they are enabled in m68kconf.h
+ */
+INLINE uint m68ki_read_imm_16(void)
+{
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+#if M68K_EMULATE_PREFETCH
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+	}
+	REG_PC += 2;
+	return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3));
+#else
+	REG_PC += 2;
+	return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2));
+#endif /* M68K_EMULATE_PREFETCH */
+}
+INLINE uint m68ki_read_imm_32(void)
+{
+#if M68K_EMULATE_PREFETCH
+	uint temp_val;
+
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+	}
+	temp_val = CPU_PREF_DATA;
+	REG_PC += 2;
+	if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR)
+	{
+		CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC);
+		CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR));
+		temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16));
+	}
+	REG_PC += 2;
+
+	return temp_val;
+#else
+	m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+	REG_PC += 4;
+	return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4));
+#endif /* M68K_EMULATE_PREFETCH */
+}
+
+
+
+/* ------------------------- Top level read/write ------------------------- */
+
+/* Handles all memory accesses (except for immediate reads if they are
+ * configured to use separate functions in m68kconf.h).
+ * All memory accesses must go through these top level functions.
+ * These functions will also check for address error and set the function
+ * code if they are enabled in m68kconf.h.
+ */
+INLINE uint m68ki_read_8_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_8(ADDRESS_68K(address));
+}
+INLINE uint m68ki_read_16_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_16(ADDRESS_68K(address));
+}
+INLINE uint m68ki_read_32_fc(uint address, uint fc)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */
+	return m68k_read_memory_32(ADDRESS_68K(address));
+}
+
+INLINE void m68ki_write_8_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_8(ADDRESS_68K(address), value);
+}
+INLINE void m68ki_write_16_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_16(ADDRESS_68K(address), value);
+}
+INLINE void m68ki_write_32_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_32(ADDRESS_68K(address), value);
+}
+
+#if M68K_SIMULATE_PD_WRITES
+INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value)
+{
+	m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */
+	m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */
+	m68k_write_memory_32_pd(ADDRESS_68K(address), value);
+}
+#endif
+
+
+/* --------------------- Effective Address Calculation -------------------- */
+
+/* The program counter relative addressing modes cause operands to be
+ * retrieved from program space, not data space.
+ */
+INLINE uint m68ki_get_ea_pcdi(void)
+{
+	uint old_pc = REG_PC;
+	m68ki_use_program_space(); /* auto-disable */
+	return old_pc + MAKE_INT_16(m68ki_read_imm_16());
+}
+
+
+INLINE uint m68ki_get_ea_pcix(void)
+{
+	m68ki_use_program_space(); /* auto-disable */
+	return m68ki_get_ea_ix(REG_PC);
+}
+
+/* Indexed addressing modes are encoded as follows:
+ *
+ * Base instruction format:
+ * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+ * x x x x x x x x x x | 1 1 0 | BASE REGISTER      (An)
+ *
+ * Base instruction format for destination EA in move instructions:
+ * F E D C | B A 9    | 8 7 6 | 5 4 3 2 1 0
+ * x x x x | BASE REG | 1 1 0 | X X X X X X       (An)
+ *
+ * Brief extension format:
+ *  F  |  E D C   |  B  |  A 9  | 8 | 7 6 5 4 3 2 1 0
+ * D/A | REGISTER | W/L | SCALE | 0 |  DISPLACEMENT
+ *
+ * Full extension format:
+ *  F     E D C      B     A 9    8   7    6    5 4       3   2 1 0
+ * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS
+ * BASE DISPLACEMENT (0, 16, 32 bit)                (bd)
+ * OUTER DISPLACEMENT (0, 16, 32 bit)               (od)
+ *
+ * D/A:     0 = Dn, 1 = An                          (Xn)
+ * W/L:     0 = W (sign extend), 1 = L              (.SIZE)
+ * SCALE:   00=1, 01=2, 10=4, 11=8                  (*SCALE)
+ * BS:      0=add base reg, 1=suppress base reg     (An suppressed)
+ * IS:      0=add index, 1=suppress index           (Xn suppressed)
+ * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long  (size of bd)
+ *
+ * IS I/IS Operation
+ * 0  000  No Memory Indirect
+ * 0  001  indir prex with null outer
+ * 0  010  indir prex with word outer
+ * 0  011  indir prex with long outer
+ * 0  100  reserved
+ * 0  101  indir postx with null outer
+ * 0  110  indir postx with word outer
+ * 0  111  indir postx with long outer
+ * 1  000  no memory indirect
+ * 1  001  mem indir with null outer
+ * 1  010  mem indir with word outer
+ * 1  011  mem indir with long outer
+ * 1  100-111  reserved
+ */
+INLINE uint m68ki_get_ea_ix(uint An)
+{
+	/* An = base register */
+	uint extension = m68ki_read_imm_16();
+	uint Xn = 0;                        /* Index register */
+	uint bd = 0;                        /* Base Displacement */
+	uint od = 0;                        /* Outer Displacement */
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+	{
+		/* Calculate index */
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+
+		/* Add base register and displacement and return */
+		return An + Xn + MAKE_INT_8(extension);
+	}
+
+	/* Brief extension format */
+	if(!BIT_8(extension))
+	{
+		/* Calculate index */
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+		/* Add scale if proper CPU type */
+		if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+			Xn <<= (extension>>9) & 3;  /* SCALE */
+
+		/* Add base register and displacement and return */
+		return An + Xn + MAKE_INT_8(extension);
+	}
+
+	/* Full extension format */
+
+	USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]);
+
+	/* Check if base register is present */
+	if(BIT_7(extension))                /* BS */
+		An = 0;                         /* An */
+
+	/* Check if index is present */
+	if(!BIT_6(extension))               /* IS */
+	{
+		Xn = REG_DA[extension>>12];     /* Xn */
+		if(!BIT_B(extension))           /* W/L */
+			Xn = MAKE_INT_16(Xn);
+		Xn <<= (extension>>9) & 3;      /* SCALE */
+	}
+
+	/* Check if base displacement is present */
+	if(BIT_5(extension))                /* BD SIZE */
+		bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());
+
+	/* If no indirect action, we are done */
+	if(!(extension&7))                  /* No Memory Indirect */
+		return An + bd + Xn;
+
+	/* Check if outer displacement is present */
+	if(BIT_1(extension))                /* I/IS:  od */
+		od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16());
+
+	/* Postindex */
+	if(BIT_2(extension))                /* I/IS:  0 = preindex, 1 = postindex */
+		return m68ki_read_32(An + bd) + Xn + od;
+
+	/* Preindex */
+	return m68ki_read_32(An + bd + Xn) + od;
+}
+
+
+/* Fetch operands */
+INLINE uint OPER_AY_AI_8(void)  {uint ea = EA_AY_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PI_8(void)  {uint ea = EA_AY_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_PD_8(void)  {uint ea = EA_AY_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_DI_8(void)  {uint ea = EA_AY_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AY_IX_8(void)  {uint ea = EA_AY_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_AX_AI_8(void)  {uint ea = EA_AX_AI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PI_8(void)  {uint ea = EA_AX_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_PD_8(void)  {uint ea = EA_AX_PD_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_DI_8(void)  {uint ea = EA_AX_DI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);}
+INLINE uint OPER_AX_IX_8(void)  {uint ea = EA_AX_IX_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);}
+INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);}
+
+INLINE uint OPER_A7_PI_8(void)  {uint ea = EA_A7_PI_8();  return m68ki_read_8(ea); }
+INLINE uint OPER_A7_PD_8(void)  {uint ea = EA_A7_PD_8();  return m68ki_read_8(ea); }
+
+INLINE uint OPER_AW_8(void)     {uint ea = EA_AW_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AW_16(void)    {uint ea = EA_AW_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AW_32(void)    {uint ea = EA_AW_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_AL_8(void)     {uint ea = EA_AL_8();     return m68ki_read_8(ea); }
+INLINE uint OPER_AL_16(void)    {uint ea = EA_AL_16();    return m68ki_read_16(ea);}
+INLINE uint OPER_AL_32(void)    {uint ea = EA_AL_32();    return m68ki_read_32(ea);}
+INLINE uint OPER_PCDI_8(void)   {uint ea = EA_PCDI_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCDI_16(void)  {uint ea = EA_PCDI_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCDI_32(void)  {uint ea = EA_PCDI_32();  return m68ki_read_pcrel_32(ea);}
+INLINE uint OPER_PCIX_8(void)   {uint ea = EA_PCIX_8();   return m68ki_read_pcrel_8(ea); }
+INLINE uint OPER_PCIX_16(void)  {uint ea = EA_PCIX_16();  return m68ki_read_pcrel_16(ea);}
+INLINE uint OPER_PCIX_32(void)  {uint ea = EA_PCIX_32();  return m68ki_read_pcrel_32(ea);}
+
+
+
+/* ---------------------------- Stack Functions --------------------------- */
+
+/* Push/pull data from the stack */
+INLINE void m68ki_push_16(uint value)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+	m68ki_write_16(REG_SP, value);
+}
+
+INLINE void m68ki_push_32(uint value)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+	m68ki_write_32(REG_SP, value);
+}
+
+INLINE uint m68ki_pull_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+	return m68ki_read_16(REG_SP-2);
+}
+
+INLINE uint m68ki_pull_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+	return m68ki_read_32(REG_SP-4);
+}
+
+
+/* Increment/decrement the stack as if doing a push/pull but
+ * don't do any memory access.
+ */
+INLINE void m68ki_fake_push_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2);
+}
+
+INLINE void m68ki_fake_push_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4);
+}
+
+INLINE void m68ki_fake_pull_16(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2);
+}
+
+INLINE void m68ki_fake_pull_32(void)
+{
+	REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4);
+}
+
+
+/* ----------------------------- Program Flow ----------------------------- */
+
+/* Jump to a new program location or vector.
+ * These functions will also call the pc_changed callback if it was enabled
+ * in m68kconf.h.
+ */
+INLINE void m68ki_jump(uint new_pc)
+{
+	REG_PC = new_pc;
+	m68ki_pc_changed(REG_PC);
+}
+
+INLINE void m68ki_jump_vector(uint vector)
+{
+	REG_PC = (vector<<2) + REG_VBR;
+	REG_PC = m68ki_read_data_32(REG_PC);
+	m68ki_pc_changed(REG_PC);
+}
+
+
+/* Branch to a new memory location.
+ * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h.
+ * So far I've found no problems with not calling pc_changed for 8 or 16
+ * bit branches.
+ */
+INLINE void m68ki_branch_8(uint offset)
+{
+	REG_PC += MAKE_INT_8(offset);
+}
+
+INLINE void m68ki_branch_16(uint offset)
+{
+	REG_PC += MAKE_INT_16(offset);
+}
+
+INLINE void m68ki_branch_32(uint offset)
+{
+	REG_PC += offset;
+	m68ki_pc_changed(REG_PC);
+}
+
+
+
+/* ---------------------------- Status Register --------------------------- */
+
+/* Set the S flag and change the active stack pointer.
+ * Note that value MUST be 4 or 0.
+ */
+INLINE void m68ki_set_s_flag(uint value)
+{
+	/* Backup the old stack pointer */
+	REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
+	/* Set the S flag */
+	FLAG_S = value;
+	/* Set the new stack pointer */
+	REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];
+}
+
+/* Set the S and M flags and change the active stack pointer.
+ * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M).
+ */
+INLINE void m68ki_set_sm_flag(uint value)
+{
+	/* Backup the old stack pointer */
+	REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP;
+	/* Set the S and M flags */
+	FLAG_S = value & SFLAG_SET;
+	FLAG_M = value & MFLAG_SET;
+	/* Set the new stack pointer */
+	REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)];
+}
+
+/* Set the S and M flags.  Don't touch the stack pointer. */
+INLINE void m68ki_set_sm_flag_nosp(uint value)
+{
+	/* Set the S and M flags */
+	FLAG_S = value & SFLAG_SET;
+	FLAG_M = value & MFLAG_SET;
+}
+
+
+/* Set the condition code register */
+INLINE void m68ki_set_ccr(uint value)
+{
+	FLAG_X = BIT_4(value)  << 4;
+	FLAG_N = BIT_3(value)  << 4;
+	FLAG_Z = !BIT_2(value);
+	FLAG_V = BIT_1(value)  << 6;
+	FLAG_C = BIT_0(value)  << 8;
+}
+
+/* Set the status register but don't check for interrupts */
+INLINE void m68ki_set_sr_noint(uint value)
+{
+	/* Mask out the "unimplemented" bits */
+	value &= CPU_SR_MASK;
+
+	/* Now set the status register */
+	FLAG_T1 = BIT_F(value);
+	FLAG_T0 = BIT_E(value);
+	FLAG_INT_MASK = value & 0x0700;
+	m68ki_set_ccr(value);
+	m68ki_set_sm_flag((value >> 11) & 6);
+}
+
+/* Set the status register but don't check for interrupts nor
+ * change the stack pointer
+ */
+INLINE void m68ki_set_sr_noint_nosp(uint value)
+{
+	/* Mask out the "unimplemented" bits */
+	value &= CPU_SR_MASK;
+
+	/* Now set the status register */
+	FLAG_T1 = BIT_F(value);
+	FLAG_T0 = BIT_E(value);
+	FLAG_INT_MASK = value & 0x0700;
+	m68ki_set_ccr(value);
+	m68ki_set_sm_flag_nosp((value >> 11) & 6);
+}
+
+/* Set the status register and check for interrupts */
+INLINE void m68ki_set_sr(uint value)
+{
+	m68ki_set_sr_noint(value);
+	m68ki_check_interrupts();
+}
+
+
+/* ------------------------- Exception Processing ------------------------- */
+
+/* Initiate exception processing */
+INLINE uint m68ki_init_exception(void)
+{
+	/* Save the old status register */
+	uint sr = m68ki_get_sr();
+
+	/* Turn off trace flag, clear pending traces */
+	FLAG_T1 = FLAG_T0 = 0;
+	m68ki_clear_trace();
+	/* Enter supervisor mode */
+	m68ki_set_s_flag(SFLAG_SET);
+
+	return sr;
+}
+
+/* 3 word stack frame (68000 only) */
+INLINE void m68ki_stack_frame_3word(uint pc, uint sr)
+{
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 0 stack frame.
+ * This is the standard stack frame for 68010+.
+ */
+INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector)
+{
+	/* Stack a 3-word frame if we are 68000 */
+	if(CPU_TYPE == CPU_TYPE_000)
+	{
+		m68ki_stack_frame_3word(pc, sr);
+		return;
+	}
+	m68ki_push_16(vector<<2);
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 1 stack frame (68020).
+ * For 68020, this is the 4 word throwaway frame.
+ */
+INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector)
+{
+	m68ki_push_16(0x1000 | (vector<<2));
+	m68ki_push_32(pc);
+	m68ki_push_16(sr);
+}
+
+/* Format 2 stack frame.
+ * This is used only by 68020 for trap exceptions.
+ */
+INLINE void m68ki_stack_frame_0010(uint sr, uint vector)
+{
+	m68ki_push_32(REG_PPC);
+	m68ki_push_16(0x2000 | (vector<<2));
+	m68ki_push_32(REG_PC);
+	m68ki_push_16(sr);
+}
+
+
+/* Bus error stack frame (68000 only).
+ */
+INLINE void m68ki_stack_frame_buserr(uint sr)
+{
+	m68ki_push_32(REG_PC);
+	m68ki_push_16(sr);
+	m68ki_push_16(REG_IR);
+	m68ki_push_32(m68ki_aerr_address);	/* access address */
+	/* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC
+	 * R/W  0 = write, 1 = read
+	 * I/N  0 = instruction, 1 = not
+	 * FC   3-bit function code
+	 */
+	m68ki_push_16(m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc);
+}
+
+/* Format 8 stack frame (68010).
+ * 68010 only.  This is the 29 word bus/address error frame.
+ */
+void m68ki_stack_frame_1000(uint pc, uint sr, uint vector)
+{
+	/* VERSION
+	 * NUMBER
+	 * INTERNAL INFORMATION, 16 WORDS
+	 */
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+	m68ki_fake_push_32();
+
+	/* INSTRUCTION INPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* DATA INPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* DATA OUTPUT BUFFER */
+	m68ki_push_16(0);
+
+	/* UNUSED, RESERVED (not written) */
+	m68ki_fake_push_16();
+
+	/* FAULT ADDRESS */
+	m68ki_push_32(0);
+
+	/* SPECIAL STATUS WORD */
+	m68ki_push_16(0);
+
+	/* 1000, VECTOR OFFSET */
+	m68ki_push_16(0x8000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+/* Format A stack frame (short bus fault).
+ * This is used only by 68020 for bus fault and address error
+ * if the error happens at an instruction boundary.
+ * PC stacked is address of next instruction.
+ */
+void m68ki_stack_frame_1010(uint sr, uint vector, uint pc)
+{
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA OUTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA CYCLE FAULT ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INSTRUCTION PIPE STAGE B */
+	m68ki_push_16(0);
+
+	/* INSTRUCTION PIPE STAGE C */
+	m68ki_push_16(0);
+
+	/* SPECIAL STATUS REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* 1010, VECTOR OFFSET */
+	m68ki_push_16(0xa000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+/* Format B stack frame (long bus fault).
+ * This is used only by 68020 for bus fault and address error
+ * if the error happens during instruction execution.
+ * PC stacked is address of instruction in progress.
+ */
+void m68ki_stack_frame_1011(uint sr, uint vector, uint pc)
+{
+	/* INTERNAL REGISTERS (18 words) */
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+
+	/* VERSION# (4 bits), INTERNAL INFORMATION */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTERS (3 words) */
+	m68ki_push_32(0);
+	m68ki_push_16(0);
+
+	/* DATA INTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTERS (2 words) */
+	m68ki_push_32(0);
+
+	/* STAGE B ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER (4 words) */
+	m68ki_push_32(0);
+	m68ki_push_32(0);
+
+	/* DATA OUTPUT BUFFER (2 words) */
+	m68ki_push_32(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* DATA CYCLE FAULT ADDRESS (2 words) */
+	m68ki_push_32(0);
+
+	/* INSTRUCTION PIPE STAGE B */
+	m68ki_push_16(0);
+
+	/* INSTRUCTION PIPE STAGE C */
+	m68ki_push_16(0);
+
+	/* SPECIAL STATUS REGISTER */
+	m68ki_push_16(0);
+
+	/* INTERNAL REGISTER */
+	m68ki_push_16(0);
+
+	/* 1011, VECTOR OFFSET */
+	m68ki_push_16(0xb000 | (vector<<2));
+
+	/* PROGRAM COUNTER */
+	m68ki_push_32(pc);
+
+	/* STATUS REGISTER */
+	m68ki_push_16(sr);
+}
+
+
+/* Used for Group 2 exceptions.
+ * These stack a type 2 frame on the 020.
+ */
+INLINE void m68ki_exception_trap(uint vector)
+{
+	uint sr = m68ki_init_exception();
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+		m68ki_stack_frame_0000(REG_PC, sr, vector);
+	else
+		m68ki_stack_frame_0010(sr, vector);
+
+	m68ki_jump_vector(vector);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
+INLINE void m68ki_exception_trapN(uint vector)
+{
+	uint sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, vector);
+	m68ki_jump_vector(vector);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for trace mode */
+INLINE void m68ki_exception_trace(void)
+{
+	uint sr = m68ki_init_exception();
+
+	if(CPU_TYPE_IS_010_LESS(CPU_TYPE))
+	{
+		#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+		if(CPU_TYPE_IS_000(CPU_TYPE))
+		{
+			CPU_INSTR_MODE = INSTRUCTION_NO;
+		}
+		#endif /* M68K_EMULATE_ADDRESS_ERROR */
+		m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE);
+	}
+	else
+		m68ki_stack_frame_0010(sr, EXCEPTION_TRACE);
+
+	m68ki_jump_vector(EXCEPTION_TRACE);
+
+	/* Trace nullifies a STOP instruction */
+	CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+	/* Use up some clock cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]);
+}
+
+/* Exception for privilege violation */
+INLINE void m68ki_exception_privilege_violation(void)
+{
+	uint sr = m68ki_init_exception();
+
+	#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+	if(CPU_TYPE_IS_000(CPU_TYPE))
+	{
+		CPU_INSTR_MODE = INSTRUCTION_NO;
+	}
+	#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+	m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION);
+	m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for A-Line instructions */
+INLINE void m68ki_exception_1010(void)
+{
+	uint sr;
+#if M68K_LOG_1010_1111 == OPT_ON
+	M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+					 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+#endif
+
+	sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1010);
+	m68ki_jump_vector(EXCEPTION_1010);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for F-Line instructions */
+INLINE void m68ki_exception_1111(void)
+{
+	uint sr;
+
+#if M68K_LOG_1010_1111 == OPT_ON
+	M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+					 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+#endif
+
+	sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1111);
+	m68ki_jump_vector(EXCEPTION_1111);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for illegal instructions */
+INLINE void m68ki_exception_illegal(void)
+{
+	uint sr;
+
+	M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n",
+				 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR,
+				 m68ki_disassemble_quick(ADDRESS_68K(REG_PPC))));
+
+	sr = m68ki_init_exception();
+
+	#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+	if(CPU_TYPE_IS_000(CPU_TYPE))
+	{
+		CPU_INSTR_MODE = INSTRUCTION_NO;
+	}
+	#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+	m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION);
+	m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for format errror in RTE */
+INLINE void m68ki_exception_format_error(void)
+{
+	uint sr = m68ki_init_exception();
+	m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR);
+	m68ki_jump_vector(EXCEPTION_FORMAT_ERROR);
+
+	/* Use up some clock cycles and undo the instruction's cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]);
+}
+
+/* Exception for address error */
+INLINE void m68ki_exception_address_error(void)
+{
+	uint sr = m68ki_init_exception();
+
+	/* If we were processing a bus error, address error, or reset,
+	 * this is a catastrophic failure.
+	 * Halt the CPU
+	 */
+	if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET)
+	{
+m68k_read_memory_8(0x00ffff01);
+		CPU_STOPPED = STOP_LEVEL_HALT;
+		return;
+	}
+	CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET;
+
+	/* Note: This is implemented for 68000 only! */
+	m68ki_stack_frame_buserr(sr);
+
+	m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR);
+
+	/* Use up some clock cycles. Note that we don't need to undo the 
+	instruction's cycles here as we've longjmp:ed directly from the
+	instruction handler without passing the part of the excecute loop
+	that deducts instruction cycles */
+	USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR]); 
+}
+
+
+/* Service an interrupt request and start exception processing */
+void m68ki_exception_interrupt(uint int_level)
+{
+	uint vector;
+	uint sr;
+	uint new_pc;
+
+	#if M68K_EMULATE_ADDRESS_ERROR == OPT_ON
+	if(CPU_TYPE_IS_000(CPU_TYPE))
+	{
+		CPU_INSTR_MODE = INSTRUCTION_NO;
+	}
+	#endif /* M68K_EMULATE_ADDRESS_ERROR */
+
+	/* Turn off the stopped state */
+	CPU_STOPPED &= ~STOP_LEVEL_STOP;
+
+	/* If we are halted, don't do anything */
+	if(CPU_STOPPED)
+		return;
+
+	/* Acknowledge the interrupt */
+	vector = m68ki_int_ack(int_level);
+
+	/* Get the interrupt vector */
+	if(vector == M68K_INT_ACK_AUTOVECTOR)
+		/* Use the autovectors.  This is the most commonly used implementation */
+		vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
+	else if(vector == M68K_INT_ACK_SPURIOUS)
+		/* Called if no devices respond to the interrupt acknowledge */
+		vector = EXCEPTION_SPURIOUS_INTERRUPT;
+	else if(vector > 255)
+	{
+		M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",
+				 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector));
+		return;
+	}
+
+	/* Start exception processing */
+	sr = m68ki_init_exception();
+
+	/* Set the interrupt mask to the level of the one being serviced */
+	FLAG_INT_MASK = int_level<<8;
+
+	/* Get the new PC */
+	new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);
+
+	/* If vector is uninitialized, call the uninitialized interrupt vector */
+	if(new_pc == 0)
+		new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR);
+
+	/* Generate a stack frame */
+	m68ki_stack_frame_0000(REG_PC, sr, vector);
+	if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Create throwaway frame */
+		m68ki_set_sm_flag(FLAG_S);	/* clear M */
+		sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */
+		m68ki_stack_frame_0001(REG_PC, sr, vector);
+	}
+
+	m68ki_jump(new_pc);
+
+	/* Defer cycle counting until later */
+	CPU_INT_CYCLES += CYC_EXCEPTION[vector];
+
+#if !M68K_EMULATE_INT_ACK
+	/* Automatically clear IRQ if we are not using an acknowledge scheme */
+	CPU_INT_LEVEL = 0;
+#endif /* M68K_EMULATE_INT_ACK */
+}
+
+
+/* ASG: Check for interrupts */
+INLINE void m68ki_check_interrupts(void)
+{
+	if(CPU_INT_LEVEL > FLAG_INT_MASK)
+		m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
+}
+
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KCPU__HEADER */
diff --git a/MCUME_pico2/picogenold/musashi34/m68kdasm.c b/MCUME_pico2/picogenold/musashi34/m68kdasm.c
new file mode 100644
index 0000000..146da47
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kdasm.c
@@ -0,0 +1,3477 @@
+/* ======================================================================== */
+/* ========================= LICENSING & COPYRIGHT ======================== */
+/* ======================================================================== */
+/*
+ *                                  MUSASHI
+ *                                Version 3.4
+ *
+ * A portable Motorola M680x0 processor emulation engine.
+ * Copyright 1998-2001 Karl Stenerud.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "m68k.h"
+
+#ifndef DECL_SPEC
+#define DECL_SPEC
+#endif
+
+/* ======================================================================== */
+/* ============================ GENERAL DEFINES =========================== */
+/* ======================================================================== */
+
+/* unsigned int and int must be at least 32 bits wide */
+#undef uint
+#define uint unsigned int
+
+/* Bit Isolation Functions */
+#define BIT_0(A)  ((A) & 0x00000001)
+#define BIT_1(A)  ((A) & 0x00000002)
+#define BIT_2(A)  ((A) & 0x00000004)
+#define BIT_3(A)  ((A) & 0x00000008)
+#define BIT_4(A)  ((A) & 0x00000010)
+#define BIT_5(A)  ((A) & 0x00000020)
+#define BIT_6(A)  ((A) & 0x00000040)
+#define BIT_7(A)  ((A) & 0x00000080)
+#define BIT_8(A)  ((A) & 0x00000100)
+#define BIT_9(A)  ((A) & 0x00000200)
+#define BIT_A(A)  ((A) & 0x00000400)
+#define BIT_B(A)  ((A) & 0x00000800)
+#define BIT_C(A)  ((A) & 0x00001000)
+#define BIT_D(A)  ((A) & 0x00002000)
+#define BIT_E(A)  ((A) & 0x00004000)
+#define BIT_F(A)  ((A) & 0x00008000)
+#define BIT_10(A) ((A) & 0x00010000)
+#define BIT_11(A) ((A) & 0x00020000)
+#define BIT_12(A) ((A) & 0x00040000)
+#define BIT_13(A) ((A) & 0x00080000)
+#define BIT_14(A) ((A) & 0x00100000)
+#define BIT_15(A) ((A) & 0x00200000)
+#define BIT_16(A) ((A) & 0x00400000)
+#define BIT_17(A) ((A) & 0x00800000)
+#define BIT_18(A) ((A) & 0x01000000)
+#define BIT_19(A) ((A) & 0x02000000)
+#define BIT_1A(A) ((A) & 0x04000000)
+#define BIT_1B(A) ((A) & 0x08000000)
+#define BIT_1C(A) ((A) & 0x10000000)
+#define BIT_1D(A) ((A) & 0x20000000)
+#define BIT_1E(A) ((A) & 0x40000000)
+#define BIT_1F(A) ((A) & 0x80000000)
+
+/* These are the CPU types understood by this disassembler */
+#define TYPE_68000 1
+#define TYPE_68010 2
+#define TYPE_68020 4
+#define TYPE_68030 8
+#define TYPE_68040 16
+
+#define M68000_ONLY		TYPE_68000
+
+#define M68010_ONLY		TYPE_68010
+#define M68010_LESS		(TYPE_68000 | TYPE_68010)
+#define M68010_PLUS		(TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040)
+
+#define M68020_ONLY 	TYPE_68020
+#define M68020_LESS 	(TYPE_68010 | TYPE_68020)
+#define M68020_PLUS		(TYPE_68020 | TYPE_68030 | TYPE_68040)
+
+#define M68030_ONLY 	TYPE_68030
+#define M68030_LESS 	(TYPE_68010 | TYPE_68020 | TYPE_68030)
+#define M68030_PLUS		(TYPE_68030 | TYPE_68040)
+
+#define M68040_PLUS		TYPE_68040
+
+
+/* Extension word formats */
+#define EXT_8BIT_DISPLACEMENT(A)          ((A)&0xff)
+#define EXT_FULL(A)                       BIT_8(A)
+#define EXT_EFFECTIVE_ZERO(A)             (((A)&0xe4) == 0xc4 || ((A)&0xe2) == 0xc0)
+#define EXT_BASE_REGISTER_PRESENT(A)      (!BIT_7(A))
+#define EXT_INDEX_REGISTER_PRESENT(A)     (!BIT_6(A))
+#define EXT_INDEX_REGISTER(A)             (((A)>>12)&7)
+#define EXT_INDEX_PRE_POST(A)             (EXT_INDEX_PRESENT(A) && (A)&3)
+#define EXT_INDEX_PRE(A)                  (EXT_INDEX_PRESENT(A) && ((A)&7) < 4 && ((A)&7) != 0)
+#define EXT_INDEX_POST(A)                 (EXT_INDEX_PRESENT(A) && ((A)&7) > 4)
+#define EXT_INDEX_SCALE(A)                (((A)>>9)&3)
+#define EXT_INDEX_LONG(A)                 BIT_B(A)
+#define EXT_INDEX_AR(A)                   BIT_F(A)
+#define EXT_BASE_DISPLACEMENT_PRESENT(A)  (((A)&0x30) > 0x10)
+#define EXT_BASE_DISPLACEMENT_WORD(A)     (((A)&0x30) == 0x20)
+#define EXT_BASE_DISPLACEMENT_LONG(A)     (((A)&0x30) == 0x30)
+#define EXT_OUTER_DISPLACEMENT_PRESENT(A) (((A)&3) > 1 && ((A)&0x47) < 0x44)
+#define EXT_OUTER_DISPLACEMENT_WORD(A)    (((A)&3) == 2 && ((A)&0x47) < 0x44)
+#define EXT_OUTER_DISPLACEMENT_LONG(A)    (((A)&3) == 3 && ((A)&0x47) < 0x44)
+
+
+
+/* ======================================================================== */
+/* =============================== PROTOTYPES ============================= */
+/* ======================================================================== */
+
+/* Read data at the PC and increment PC */
+uint  read_imm_8(void);
+uint  read_imm_16(void);
+uint  read_imm_32(void);
+
+/* Read data at the PC but don't imcrement the PC */
+uint  peek_imm_8(void);
+uint  peek_imm_16(void);
+uint  peek_imm_32(void);
+
+/* make signed integers 100% portably */
+static int make_int_8(int value);
+static int make_int_16(int value);
+
+/* make a string of a hex value */
+static char* make_signed_hex_str_8(uint val);
+static char* make_signed_hex_str_16(uint val);
+static char* make_signed_hex_str_32(uint val);
+
+/* make string of ea mode */
+static char* get_ea_mode_str(uint instruction, uint size);
+
+char* get_ea_mode_str_8(uint instruction);
+char* get_ea_mode_str_16(uint instruction);
+char* get_ea_mode_str_32(uint instruction);
+
+/* make string of immediate value */
+static char* get_imm_str_s(uint size);
+static char* get_imm_str_u(uint size);
+
+char* get_imm_str_s8(void);
+char* get_imm_str_s16(void);
+char* get_imm_str_s32(void);
+
+/* Stuff to build the opcode handler jump table */
+static void  build_opcode_table(void);
+static int   valid_ea(uint opcode, uint mask);
+static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr);
+
+/* used to build opcode handler jump table */
+typedef struct
+{
+	void (*opcode_handler)(void); /* handler function */
+	uint mask;                    /* mask on opcode */
+	uint match;                   /* what to match after masking */
+	uint ea_mask;                 /* what ea modes are allowed */
+} opcode_struct;
+
+
+
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+/* Opcode handler jump table */
+static void (*g_instruction_table[0x10000])(void);
+/* Flag if disassembler initialized */
+static int  g_initialized = 0;
+
+/* Address mask to simulate address lines */
+static unsigned int g_address_mask = 0xffffffff;
+
+static char g_dasm_str[100]; /* string to hold disassembly */
+static char g_helper_str[100]; /* string to hold helpful info */
+static uint g_cpu_pc;        /* program counter */
+static uint g_cpu_ir;        /* instruction register */
+static uint g_cpu_type;
+
+/* used by ops like asr, ror, addq, etc */
+static uint g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};
+
+static uint g_5bit_data_table[32] =
+{
+	32,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
+	16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};
+
+static char* g_cc[16] =
+{"t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", "ge", "lt", "gt", "le"};
+
+static char* g_cpcc[64] =
+{/* 000    001    010    011    100    101    110    111 */
+	  "f",  "eq", "ogt", "oge", "olt", "ole", "ogl",  "or", /* 000 */
+	 "un", "ueq", "ugt", "uge", "ult", "ule",  "ne",   "t", /* 001 */
+	 "sf", "seq",  "gt",  "ge",  "lt",  "le",  "gl"  "gle", /* 010 */
+  "ngle", "ngl", "nle", "nlt", "nge", "ngt", "sne",  "st", /* 011 */
+	  "?",   "?",   "?",   "?",   "?",   "?",   "?",   "?", /* 100 */
+	  "?",   "?",   "?",   "?",   "?",   "?",   "?",   "?", /* 101 */
+	  "?",   "?",   "?",   "?",   "?",   "?",   "?",   "?", /* 110 */
+	  "?",   "?",   "?",   "?",   "?",   "?",   "?",   "?"  /* 111 */
+};
+
+
+/* ======================================================================== */
+/* =========================== UTILITY FUNCTIONS ========================== */
+/* ======================================================================== */
+
+#define LIMIT_CPU_TYPES(ALLOWED_CPU_TYPES)	\
+	if(!(g_cpu_type & ALLOWED_CPU_TYPES))	\
+	{										\
+		d68000_illegal();					\
+		return;								\
+	}
+
+#define read_imm_8()  (m68k_read_disassembler_16(((g_cpu_pc+=2)-2)&g_address_mask)&0xff)
+#define read_imm_16() m68k_read_disassembler_16(((g_cpu_pc+=2)-2)&g_address_mask)
+#define read_imm_32() m68k_read_disassembler_32(((g_cpu_pc+=4)-4)&g_address_mask)
+
+#define peek_imm_8()  (m68k_read_disassembler_16(g_cpu_pc & g_address_mask)&0xff)
+#define peek_imm_16() m68k_read_disassembler_16(g_cpu_pc & g_address_mask)
+#define peek_imm_32() m68k_read_disassembler_32(g_cpu_pc & g_address_mask)
+
+/* Fake a split interface */
+#define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0)
+#define get_ea_mode_str_16(instruction) get_ea_mode_str(instruction, 1)
+#define get_ea_mode_str_32(instruction) get_ea_mode_str(instruction, 2)
+
+#define get_imm_str_s8() get_imm_str_s(0)
+#define get_imm_str_s16() get_imm_str_s(1)
+#define get_imm_str_s32() get_imm_str_s(2)
+
+#define get_imm_str_u8() get_imm_str_u(0)
+#define get_imm_str_u16() get_imm_str_u(1)
+#define get_imm_str_u32() get_imm_str_u(2)
+
+
+/* 100% portable signed int generators */
+static int make_int_8(int value)
+{
+	return (value & 0x80) ? value | ~0xff : value & 0xff;
+}
+
+static int make_int_16(int value)
+{
+	return (value & 0x8000) ? value | ~0xffff : value & 0xffff;
+}
+
+
+/* Get string representation of hex values */
+static char* make_signed_hex_str_8(uint val)
+{
+	static char str[20];
+
+	val &= 0xff;
+
+	if(val == 0x80)
+		sprintf(str, "-$80");
+	else if(val & 0x80)
+		sprintf(str, "-$%x", (0-val) & 0x7f);
+	else
+		sprintf(str, "$%x", val & 0x7f);
+
+	return str;
+}
+
+static char* make_signed_hex_str_16(uint val)
+{
+	static char str[20];
+
+	val &= 0xffff;
+
+	if(val == 0x8000)
+		sprintf(str, "-$8000");
+	else if(val & 0x8000)
+		sprintf(str, "-$%x", (0-val) & 0x7fff);
+	else
+		sprintf(str, "$%x", val & 0x7fff);
+
+	return str;
+}
+
+static char* make_signed_hex_str_32(uint val)
+{
+	static char str[20];
+
+	val &= 0xffffffff;
+
+	if(val == 0x80000000)
+		sprintf(str, "-$80000000");
+	else if(val & 0x80000000)
+		sprintf(str, "-$%x", (0-val) & 0x7fffffff);
+	else
+		sprintf(str, "$%x", val & 0x7fffffff);
+
+	return str;
+}
+
+
+/* make string of immediate value */
+static char* get_imm_str_s(uint size)
+{
+	static char str[15];
+	if(size == 0)
+		sprintf(str, "#%s", make_signed_hex_str_8(read_imm_8()));
+	else if(size == 1)
+		sprintf(str, "#%s", make_signed_hex_str_16(read_imm_16()));
+	else
+		sprintf(str, "#%s", make_signed_hex_str_32(read_imm_32()));
+	return str;
+}
+
+static char* get_imm_str_u(uint size)
+{
+	static char str[15];
+	if(size == 0)
+		sprintf(str, "#$%x", read_imm_8() & 0xff);
+	else if(size == 1)
+		sprintf(str, "#$%x", read_imm_16() & 0xffff);
+	else
+		sprintf(str, "#$%x", read_imm_32() & 0xffffffff);
+	return str;
+}
+
+/* Make string of effective address mode */
+static char* get_ea_mode_str(uint instruction, uint size)
+{
+	static char b1[64];
+	static char b2[64];
+	static char* mode = b2;
+	uint extension;
+	uint base;
+	uint outer;
+	char base_reg[4];
+	char index_reg[8];
+	uint preindex;
+	uint postindex;
+	uint comma = 0;
+	uint temp_value;
+
+	/* Switch buffers so we don't clobber on a double-call to this function */
+	mode = mode == b1 ? b2 : b1;
+
+	switch(instruction & 0x3f)
+	{
+		case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+		/* data register direct */
+			sprintf(mode, "D%d", instruction&7);
+			break;
+		case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+		/* address register direct */
+			sprintf(mode, "A%d", instruction&7);
+			break;
+		case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+		/* address register indirect */
+			sprintf(mode, "(A%d)", instruction&7);
+			break;
+		case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+		/* address register indirect with postincrement */
+			sprintf(mode, "(A%d)+", instruction&7);
+			break;
+		case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+		/* address register indirect with predecrement */
+			sprintf(mode, "-(A%d)", instruction&7);
+			break;
+		case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+		/* address register indirect with displacement*/
+			sprintf(mode, "(%s,A%d)", make_signed_hex_str_16(read_imm_16()), instruction&7);
+			break;
+		case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+		/* address register indirect with index */
+			extension = read_imm_16();
+
+			if(EXT_FULL(extension))
+			{
+				if(EXT_EFFECTIVE_ZERO(extension))
+				{
+					strcpy(mode, "0");
+					break;
+				}
+				base = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0;
+				outer = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0;
+				if(EXT_BASE_REGISTER_PRESENT(extension))
+					sprintf(base_reg, "A%d", instruction&7);
+				else
+					*base_reg = 0;
+				if(EXT_INDEX_REGISTER_PRESENT(extension))
+				{
+					sprintf(index_reg, "%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+					if(EXT_INDEX_SCALE(extension))
+						sprintf(index_reg+strlen(index_reg), "*%d", 1 << EXT_INDEX_SCALE(extension));
+				}
+				else
+					*index_reg = 0;
+				preindex = (extension&7) > 0 && (extension&7) < 4;
+				postindex = (extension&7) > 4;
+
+				strcpy(mode, "(");
+				if(preindex || postindex)
+					strcat(mode, "[");
+				if(base)
+				{
+					strcat(mode, make_signed_hex_str_16(base));
+					comma = 1;
+				}
+				if(*base_reg)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, base_reg);
+					comma = 1;
+				}
+				if(postindex)
+				{
+					strcat(mode, "]");
+					comma = 1;
+				}
+				if(*index_reg)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, index_reg);
+					comma = 1;
+				}
+				if(preindex)
+				{
+					strcat(mode, "]");
+					comma = 1;
+				}
+				if(outer)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, make_signed_hex_str_16(outer));
+				}
+				strcat(mode, ")");
+				break;
+			}
+
+			if(EXT_8BIT_DISPLACEMENT(extension) == 0)
+				sprintf(mode, "(A%d,%c%d.%c", instruction&7, EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+			else
+				sprintf(mode, "(%s,A%d,%c%d.%c", make_signed_hex_str_8(extension), instruction&7, EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+			if(EXT_INDEX_SCALE(extension))
+				sprintf(mode+strlen(mode), "*%d", 1 << EXT_INDEX_SCALE(extension));
+			strcat(mode, ")");
+			break;
+		case 0x38:
+		/* absolute short address */
+			sprintf(mode, "$%x.w", read_imm_16());
+			break;
+		case 0x39:
+		/* absolute long address */
+			sprintf(mode, "$%x.l", read_imm_32());
+			break;
+		case 0x3a:
+		/* program counter with displacement */
+			temp_value = read_imm_16();
+			sprintf(mode, "(%s,PC)", make_signed_hex_str_16(temp_value));
+			sprintf(g_helper_str, "; ($%x)", (make_int_16(temp_value) + g_cpu_pc-2) & 0xffffffff);
+			break;
+		case 0x3b:
+		/* program counter with index */
+			extension = read_imm_16();
+
+			if(EXT_FULL(extension))
+			{
+				if(EXT_EFFECTIVE_ZERO(extension))
+				{
+					strcpy(mode, "0");
+					break;
+				}
+				base = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0;
+				outer = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0;
+				if(EXT_BASE_REGISTER_PRESENT(extension))
+					strcpy(base_reg, "PC");
+				else
+					*base_reg = 0;
+				if(EXT_INDEX_REGISTER_PRESENT(extension))
+				{
+					sprintf(index_reg, "%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+					if(EXT_INDEX_SCALE(extension))
+						sprintf(index_reg+strlen(index_reg), "*%d", 1 << EXT_INDEX_SCALE(extension));
+				}
+				else
+					*index_reg = 0;
+				preindex = (extension&7) > 0 && (extension&7) < 4;
+				postindex = (extension&7) > 4;
+
+				strcpy(mode, "(");
+				if(preindex || postindex)
+					strcat(mode, "[");
+				if(base)
+				{
+					strcat(mode, make_signed_hex_str_16(base));
+					comma = 1;
+				}
+				if(*base_reg)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, base_reg);
+					comma = 1;
+				}
+				if(postindex)
+				{
+					strcat(mode, "]");
+					comma = 1;
+				}
+				if(*index_reg)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, index_reg);
+					comma = 1;
+				}
+				if(preindex)
+				{
+					strcat(mode, "]");
+					comma = 1;
+				}
+				if(outer)
+				{
+					if(comma)
+						strcat(mode, ",");
+					strcat(mode, make_signed_hex_str_16(outer));
+				}
+				strcat(mode, ")");
+				break;
+			}
+
+			if(EXT_8BIT_DISPLACEMENT(extension) == 0)
+				sprintf(mode, "(PC,%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+			else
+				sprintf(mode, "(%s,PC,%c%d.%c", make_signed_hex_str_8(extension), EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w');
+			if(EXT_INDEX_SCALE(extension))
+				sprintf(mode+strlen(mode), "*%d", 1 << EXT_INDEX_SCALE(extension));
+			strcat(mode, ")");
+			break;
+		case 0x3c:
+		/* Immediate */
+			sprintf(mode, "%s", get_imm_str_u(size));
+			break;
+		default:
+			sprintf(mode, "INVALID %x", instruction & 0x3f);
+	}
+	return mode;
+}
+
+
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+/* Instruction handler function names follow this convention:
+ *
+ * d68000_NAME_EXTENSIONS(void)
+ * where NAME is the name of the opcode it handles and EXTENSIONS are any
+ * extensions for special instances of that opcode.
+ *
+ * Examples:
+ *   d68000_add_er_8(): add opcode, from effective address to register,
+ *                      size = byte
+ *
+ *   d68000_asr_s_8(): arithmetic shift right, static count, size = byte
+ *
+ *
+ * Common extensions:
+ * 8   : size = byte
+ * 16  : size = word
+ * 32  : size = long
+ * rr  : register to register
+ * mm  : memory to memory
+ * r   : register
+ * s   : static
+ * er  : effective address -> register
+ * re  : register -> effective address
+ * ea  : using effective address mode of operation
+ * d   : data register direct
+ * a   : address register direct
+ * ai  : address register indirect
+ * pi  : address register indirect with postincrement
+ * pd  : address register indirect with predecrement
+ * di  : address register indirect with displacement
+ * ix  : address register indirect with index
+ * aw  : absolute word
+ * al  : absolute long
+ */
+
+static void d68000_illegal(void)
+{
+	sprintf(g_dasm_str, "dc.w $%04x; ILLEGAL", g_cpu_ir);
+}
+
+static void d68000_1010(void)
+{
+	sprintf(g_dasm_str, "dc.w    $%04x; opcode 1010", g_cpu_ir);
+}
+
+
+static void d68000_1111(void)
+{
+	sprintf(g_dasm_str, "dc.w    $%04x; opcode 1111", g_cpu_ir);
+}
+
+
+static void d68000_abcd_rr(void)
+{
+	sprintf(g_dasm_str, "abcd    D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+
+static void d68000_abcd_mm(void)
+{
+	sprintf(g_dasm_str, "abcd    -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_add_er_8(void)
+{
+	sprintf(g_dasm_str, "add.b   %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+
+static void d68000_add_er_16(void)
+{
+	sprintf(g_dasm_str, "add.w   %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_add_er_32(void)
+{
+	sprintf(g_dasm_str, "add.l   %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_add_re_8(void)
+{
+	sprintf(g_dasm_str, "add.b   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_add_re_16(void)
+{
+	sprintf(g_dasm_str, "add.w   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_add_re_32(void)
+{
+	sprintf(g_dasm_str, "add.l   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_adda_16(void)
+{
+	sprintf(g_dasm_str, "adda.w  %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_adda_32(void)
+{
+	sprintf(g_dasm_str, "adda.l  %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addi_8(void)
+{
+	char* str = get_imm_str_s8();
+	sprintf(g_dasm_str, "addi.b  %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_addi_16(void)
+{
+	char* str = get_imm_str_s16();
+	sprintf(g_dasm_str, "addi.w  %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_addi_32(void)
+{
+	char* str = get_imm_str_s32();
+	sprintf(g_dasm_str, "addi.l  %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_addq_8(void)
+{
+	sprintf(g_dasm_str, "addq.b  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_addq_16(void)
+{
+	sprintf(g_dasm_str, "addq.w  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_addq_32(void)
+{
+	sprintf(g_dasm_str, "addq.l  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_addx_rr_8(void)
+{
+	sprintf(g_dasm_str, "addx.b  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addx_rr_16(void)
+{
+	sprintf(g_dasm_str, "addx.w  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addx_rr_32(void)
+{
+	sprintf(g_dasm_str, "addx.l  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addx_mm_8(void)
+{
+	sprintf(g_dasm_str, "addx.b  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addx_mm_16(void)
+{
+	sprintf(g_dasm_str, "addx.w  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_addx_mm_32(void)
+{
+	sprintf(g_dasm_str, "addx.l  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_and_er_8(void)
+{
+	sprintf(g_dasm_str, "and.b   %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_and_er_16(void)
+{
+	sprintf(g_dasm_str, "and.w   %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_and_er_32(void)
+{
+	sprintf(g_dasm_str, "and.l   %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_and_re_8(void)
+{
+	sprintf(g_dasm_str, "and.b   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_and_re_16(void)
+{
+	sprintf(g_dasm_str, "and.w   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_and_re_32(void)
+{
+	sprintf(g_dasm_str, "and.l   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_andi_8(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "andi.b  %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_andi_16(void)
+{
+	char* str = get_imm_str_u16();
+	sprintf(g_dasm_str, "andi.w  %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_andi_32(void)
+{
+	char* str = get_imm_str_u32();
+	sprintf(g_dasm_str, "andi.l  %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_andi_to_ccr(void)
+{
+	sprintf(g_dasm_str, "andi    %s, CCR", get_imm_str_u8());
+}
+
+static void d68000_andi_to_sr(void)
+{
+	sprintf(g_dasm_str, "andi    %s, SR", get_imm_str_u16());
+}
+
+static void d68000_asr_s_8(void)
+{
+	sprintf(g_dasm_str, "asr.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asr_s_16(void)
+{
+	sprintf(g_dasm_str, "asr.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asr_s_32(void)
+{
+	sprintf(g_dasm_str, "asr.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asr_r_8(void)
+{
+	sprintf(g_dasm_str, "asr.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asr_r_16(void)
+{
+	sprintf(g_dasm_str, "asr.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asr_r_32(void)
+{
+	sprintf(g_dasm_str, "asr.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asr_ea(void)
+{
+	sprintf(g_dasm_str, "asr.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_asl_s_8(void)
+{
+	sprintf(g_dasm_str, "asl.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asl_s_16(void)
+{
+	sprintf(g_dasm_str, "asl.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asl_s_32(void)
+{
+	sprintf(g_dasm_str, "asl.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_asl_r_8(void)
+{
+	sprintf(g_dasm_str, "asl.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asl_r_16(void)
+{
+	sprintf(g_dasm_str, "asl.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asl_r_32(void)
+{
+	sprintf(g_dasm_str, "asl.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_asl_ea(void)
+{
+	sprintf(g_dasm_str, "asl.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_bcc_8(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "b%-2s     %x", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + make_int_8(g_cpu_ir));
+}
+
+static void d68000_bcc_16(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "b%-2s     %x", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + make_int_16(read_imm_16()));
+}
+
+static void d68020_bcc_32(void)
+{
+	uint temp_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "b%-2s     %x; (2+)", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + read_imm_32());
+}
+
+static void d68000_bchg_r(void)
+{
+	sprintf(g_dasm_str, "bchg    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_bchg_s(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "bchg    %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_bclr_r(void)
+{
+	sprintf(g_dasm_str, "bclr    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_bclr_s(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "bclr    %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68010_bkpt(void)
+{
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	sprintf(g_dasm_str, "bkpt #%d; (1+)", g_cpu_ir&7);
+}
+
+static void d68020_bfchg(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfchg   %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width);
+}
+
+static void d68020_bfclr(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfclr   %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width);
+}
+
+static void d68020_bfexts(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfexts  %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7);
+}
+
+static void d68020_bfextu(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfextu  %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7);
+}
+
+static void d68020_bfffo(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfffo   %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7);
+}
+
+static void d68020_bfins(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfins   D%d, %s {%s:%s}; (2+)", (extension>>12)&7, get_ea_mode_str_8(g_cpu_ir), offset, width);
+}
+
+static void d68020_bfset(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bfset   %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width);
+}
+
+static void d68020_bftst(void)
+{
+	uint extension;
+	char offset[3];
+	char width[3];
+
+	LIMIT_CPU_TYPES(M68020_PLUS);
+
+	extension = read_imm_16();
+
+	if(BIT_B(extension))
+		sprintf(offset, "D%d", (extension>>6)&7);
+	else
+		sprintf(offset, "%d", (extension>>6)&31);
+	if(BIT_5(extension))
+		sprintf(width, "D%d", extension&7);
+	else
+		sprintf(width, "%d", g_5bit_data_table[extension&31]);
+	sprintf(g_dasm_str, "bftst   %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width);
+}
+
+static void d68000_bra_8(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "bra     %x", temp_pc + make_int_8(g_cpu_ir));
+}
+
+static void d68000_bra_16(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "bra     %x", temp_pc + make_int_16(read_imm_16()));
+}
+
+static void d68020_bra_32(void)
+{
+	uint temp_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "bra     %x; (2+)", temp_pc + read_imm_32());
+}
+
+static void d68000_bset_r(void)
+{
+	sprintf(g_dasm_str, "bset    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_bset_s(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "bset    %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_bsr_8(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "bsr     %x", temp_pc + make_int_8(g_cpu_ir));
+}
+
+static void d68000_bsr_16(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "bsr     %x", temp_pc + make_int_16(read_imm_16()));
+}
+
+static void d68020_bsr_32(void)
+{
+	uint temp_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "bsr     %x; (2+)", temp_pc + peek_imm_32());
+}
+
+static void d68000_btst_r(void)
+{
+	sprintf(g_dasm_str, "btst    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_btst_s(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "btst    %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_callm(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68020_ONLY);
+	str = get_imm_str_u8();
+
+	sprintf(g_dasm_str, "callm   %s, %s; (2)", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cas_8(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "cas.b   D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cas_16(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "cas.w   D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_cas_32(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "cas.l   D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_cas2_16(void)
+{
+/* CAS2 Dc1:Dc2,Du1:Dc2:(Rn1):(Rn2)
+f e d c b a 9 8 7 6 5 4 3 2 1 0
+ DARn1  0 0 0  Du1  0 0 0  Dc1
+ DARn2  0 0 0  Du2  0 0 0  Dc2
+*/
+
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_32();
+	sprintf(g_dasm_str, "cas2.w  D%d:D%d, D%d:D%d, (%c%d):(%c%d); (2+)",
+		(extension>>16)&7, extension&7, (extension>>22)&7, (extension>>6)&7,
+		BIT_1F(extension) ? 'A' : 'D', (extension>>28)&7,
+		BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68020_cas2_32(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_32();
+	sprintf(g_dasm_str, "cas2.l  D%d:D%d, D%d:D%d, (%c%d):(%c%d); (2+)",
+		(extension>>16)&7, extension&7, (extension>>22)&7, (extension>>6)&7,
+		BIT_1F(extension) ? 'A' : 'D', (extension>>28)&7,
+		BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68000_chk_16(void)
+{
+	sprintf(g_dasm_str, "chk.w   %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68020_chk_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "chk.l   %s, D%d; (2+)", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68020_chk2_cmp2_8(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "%s.b  %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_8(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68020_chk2_cmp2_16(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "%s.w  %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_16(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68020_chk2_cmp2_32(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	sprintf(g_dasm_str, "%s.l  %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_32(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68040_cinv(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	switch((g_cpu_ir>>3)&3)
+	{
+		case 0:
+			sprintf(g_dasm_str, "cinv (illegal scope); (4)");
+			break;
+		case 1:
+			sprintf(g_dasm_str, "cinvl   %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7);
+			break;
+		case 2:
+			sprintf(g_dasm_str, "cinvp   %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7);
+			break;
+		case 3:
+			sprintf(g_dasm_str, "cinva   %d; (4)", (g_cpu_ir>>6)&3);
+			break;
+	}
+}
+
+static void d68000_clr_8(void)
+{
+	sprintf(g_dasm_str, "clr.b   %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_clr_16(void)
+{
+	sprintf(g_dasm_str, "clr.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_clr_32(void)
+{
+	sprintf(g_dasm_str, "clr.l   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_cmp_8(void)
+{
+	sprintf(g_dasm_str, "cmp.b   %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmp_16(void)
+{
+	sprintf(g_dasm_str, "cmp.w   %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmp_32(void)
+{
+	sprintf(g_dasm_str, "cmp.l   %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmpa_16(void)
+{
+	sprintf(g_dasm_str, "cmpa.w  %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmpa_32(void)
+{
+	sprintf(g_dasm_str, "cmpa.l  %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmpi_8(void)
+{
+	char* str = get_imm_str_s8();
+	sprintf(g_dasm_str, "cmpi.b  %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcdi_8(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s8();
+	sprintf(g_dasm_str, "cmpi.b  %s, %s; (2+)", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcix_8(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s8();
+	sprintf(g_dasm_str, "cmpi.b  %s, %s; (2+)", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_cmpi_16(void)
+{
+	char* str;
+	str = get_imm_str_s16();
+	sprintf(g_dasm_str, "cmpi.w  %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcdi_16(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s16();
+	sprintf(g_dasm_str, "cmpi.w  %s, %s; (2+)", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcix_16(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s16();
+	sprintf(g_dasm_str, "cmpi.w  %s, %s; (2+)", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_cmpi_32(void)
+{
+	char* str;
+	str = get_imm_str_s32();
+	sprintf(g_dasm_str, "cmpi.l  %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcdi_32(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s32();
+	sprintf(g_dasm_str, "cmpi.l  %s, %s; (2+)", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_cmpi_pcix_32(void)
+{
+	char* str;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	str = get_imm_str_s32();
+	sprintf(g_dasm_str, "cmpi.l  %s, %s; (2+)", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_cmpm_8(void)
+{
+	sprintf(g_dasm_str, "cmpm.b  (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmpm_16(void)
+{
+	sprintf(g_dasm_str, "cmpm.w  (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_cmpm_32(void)
+{
+	sprintf(g_dasm_str, "cmpm.l  (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68020_cpbcc_16(void)
+{
+	uint extension;
+	uint new_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	new_pc += make_int_16(peek_imm_16());
+	sprintf(g_dasm_str, "%db%-4s  %s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[g_cpu_ir&0x3f], get_imm_str_s16(), new_pc, extension);
+}
+
+static void d68020_cpbcc_32(void)
+{
+	uint extension;
+	uint new_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+	new_pc += peek_imm_32();
+	sprintf(g_dasm_str, "%db%-4s  %s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[g_cpu_ir&0x3f], get_imm_str_s16(), new_pc, extension);
+}
+
+static void d68020_cpdbcc(void)
+{
+	uint extension1;
+	uint extension2;
+	uint new_pc = g_cpu_pc;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension1 = read_imm_16();
+	extension2 = read_imm_16();
+	new_pc += make_int_16(peek_imm_16());
+	sprintf(g_dasm_str, "%ddb%-4s D%d,%s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], g_cpu_ir&7, get_imm_str_s16(), new_pc, extension2);
+}
+
+static void d68020_cpgen(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "%dgen    %s; (2-3)", (g_cpu_ir>>9)&7, get_imm_str_u32());
+}
+
+static void d68020_cprestore(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "%drestore %s; (2-3)", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cpsave(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "%dsave   %s; (2-3)", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_cpscc(void)
+{
+	uint extension1;
+	uint extension2;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension1 = read_imm_16();
+	extension2 = read_imm_16();
+	sprintf(g_dasm_str, "%ds%-4s  %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_ea_mode_str_8(g_cpu_ir), extension2);
+}
+
+static void d68020_cptrapcc_0(void)
+{
+	uint extension1;
+	uint extension2;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension1 = read_imm_16();
+	extension2 = read_imm_16();
+	sprintf(g_dasm_str, "%dtrap%-4s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], extension2);
+}
+
+static void d68020_cptrapcc_16(void)
+{
+	uint extension1;
+	uint extension2;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension1 = read_imm_16();
+	extension2 = read_imm_16();
+	sprintf(g_dasm_str, "%dtrap%-4s %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_imm_str_u16(), extension2);
+}
+
+static void d68020_cptrapcc_32(void)
+{
+	uint extension1;
+	uint extension2;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension1 = read_imm_16();
+	extension2 = read_imm_16();
+	sprintf(g_dasm_str, "%dtrap%-4s %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_imm_str_u32(), extension2);
+}
+
+static void d68040_cpush(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	switch((g_cpu_ir>>3)&3)
+	{
+		case 0:
+			sprintf(g_dasm_str, "cpush (illegal scope); (4)");
+			break;
+		case 1:
+			sprintf(g_dasm_str, "cpushl  %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7);
+			break;
+		case 2:
+			sprintf(g_dasm_str, "cpushp  %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7);
+			break;
+		case 3:
+			sprintf(g_dasm_str, "cpusha  %d; (4)", (g_cpu_ir>>6)&3);
+			break;
+	}
+}
+
+static void d68000_dbra(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "dbra    D%d, %x", g_cpu_ir & 7, temp_pc + make_int_16(read_imm_16()));
+}
+
+static void d68000_dbcc(void)
+{
+	uint temp_pc = g_cpu_pc;
+	sprintf(g_dasm_str, "db%-2s    D%d, %x", g_cc[(g_cpu_ir>>8)&0xf], g_cpu_ir & 7, temp_pc + make_int_16(read_imm_16()));
+}
+
+static void d68000_divs(void)
+{
+	sprintf(g_dasm_str, "divs.w  %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_divu(void)
+{
+	sprintf(g_dasm_str, "divu.w  %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68020_divl(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+
+	if(BIT_A(extension))
+		sprintf(g_dasm_str, "div%c.l  %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7);
+	else if((extension&7) == ((extension>>12)&7))
+		sprintf(g_dasm_str, "div%c.l  %s, D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), (extension>>12)&7);
+	else
+		sprintf(g_dasm_str, "div%cl.l %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7);
+}
+
+static void d68000_eor_8(void)
+{
+	sprintf(g_dasm_str, "eor.b   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_eor_16(void)
+{
+	sprintf(g_dasm_str, "eor.w   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_eor_32(void)
+{
+	sprintf(g_dasm_str, "eor.l   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_eori_8(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "eori.b  %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_eori_16(void)
+{
+	char* str = get_imm_str_u16();
+	sprintf(g_dasm_str, "eori.w  %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_eori_32(void)
+{
+	char* str = get_imm_str_u32();
+	sprintf(g_dasm_str, "eori.l  %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_eori_to_ccr(void)
+{
+	sprintf(g_dasm_str, "eori    %s, CCR", get_imm_str_u8());
+}
+
+static void d68000_eori_to_sr(void)
+{
+	sprintf(g_dasm_str, "eori    %s, SR", get_imm_str_u16());
+}
+
+static void d68000_exg_dd(void)
+{
+	sprintf(g_dasm_str, "exg     D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_exg_aa(void)
+{
+	sprintf(g_dasm_str, "exg     A%d, A%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_exg_da(void)
+{
+	sprintf(g_dasm_str, "exg     D%d, A%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_ext_16(void)
+{
+	sprintf(g_dasm_str, "ext.w   D%d", g_cpu_ir&7);
+}
+
+static void d68000_ext_32(void)
+{
+	sprintf(g_dasm_str, "ext.l   D%d", g_cpu_ir&7);
+}
+
+static void d68020_extb_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "extb.l  D%d; (2+)", g_cpu_ir&7);
+}
+
+static void d68000_jmp(void)
+{
+	sprintf(g_dasm_str, "jmp     %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_jsr(void)
+{
+	sprintf(g_dasm_str, "jsr     %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_lea(void)
+{
+	sprintf(g_dasm_str, "lea     %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_link_16(void)
+{
+	sprintf(g_dasm_str, "link    A%d, %s", g_cpu_ir&7, get_imm_str_s16());
+}
+
+static void d68020_link_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "link    A%d, %s; (2+)", g_cpu_ir&7, get_imm_str_s32());
+}
+
+static void d68000_lsr_s_8(void)
+{
+	sprintf(g_dasm_str, "lsr.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsr_s_16(void)
+{
+	sprintf(g_dasm_str, "lsr.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsr_s_32(void)
+{
+	sprintf(g_dasm_str, "lsr.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsr_r_8(void)
+{
+	sprintf(g_dasm_str, "lsr.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsr_r_16(void)
+{
+	sprintf(g_dasm_str, "lsr.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsr_r_32(void)
+{
+	sprintf(g_dasm_str, "lsr.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsr_ea(void)
+{
+	sprintf(g_dasm_str, "lsr.w   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_lsl_s_8(void)
+{
+	sprintf(g_dasm_str, "lsl.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsl_s_16(void)
+{
+	sprintf(g_dasm_str, "lsl.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsl_s_32(void)
+{
+	sprintf(g_dasm_str, "lsl.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_lsl_r_8(void)
+{
+	sprintf(g_dasm_str, "lsl.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsl_r_16(void)
+{
+	sprintf(g_dasm_str, "lsl.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsl_r_32(void)
+{
+	sprintf(g_dasm_str, "lsl.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_lsl_ea(void)
+{
+	sprintf(g_dasm_str, "lsl.w   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_move_8(void)
+{
+	char* str = get_ea_mode_str_8(g_cpu_ir);
+	sprintf(g_dasm_str, "move.b  %s, %s", str, get_ea_mode_str_8(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38)));
+}
+
+static void d68000_move_16(void)
+{
+	char* str = get_ea_mode_str_16(g_cpu_ir);
+	sprintf(g_dasm_str, "move.w  %s, %s", str, get_ea_mode_str_16(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38)));
+}
+
+static void d68000_move_32(void)
+{
+	char* str = get_ea_mode_str_32(g_cpu_ir);
+	sprintf(g_dasm_str, "move.l  %s, %s", str, get_ea_mode_str_32(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38)));
+}
+
+static void d68000_movea_16(void)
+{
+	sprintf(g_dasm_str, "movea.w %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_movea_32(void)
+{
+	sprintf(g_dasm_str, "movea.l %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_move_to_ccr(void)
+{
+	sprintf(g_dasm_str, "move    %s, CCR", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68010_move_fr_ccr(void)
+{
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	sprintf(g_dasm_str, "move    CCR, %s; (1+)", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_move_fr_sr(void)
+{
+	sprintf(g_dasm_str, "move    SR, %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_move_to_sr(void)
+{
+	sprintf(g_dasm_str, "move    %s, SR", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_move_fr_usp(void)
+{
+	sprintf(g_dasm_str, "move    USP, A%d", g_cpu_ir&7);
+}
+
+static void d68000_move_to_usp(void)
+{
+	sprintf(g_dasm_str, "move    A%d, USP", g_cpu_ir&7);
+}
+
+static void d68010_movec(void)
+{
+	uint extension;
+	char* reg_name;
+	char* processor;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	extension = read_imm_16();
+
+	switch(extension & 0xfff)
+	{
+		case 0x000:
+			reg_name = "SFC";
+			processor = "1+";
+			break;
+		case 0x001:
+			reg_name = "DFC";
+			processor = "1+";
+			break;
+		case 0x800:
+			reg_name = "USP";
+			processor = "1+";
+			break;
+		case 0x801:
+			reg_name = "VBR";
+			processor = "1+";
+			break;
+		case 0x002:
+			reg_name = "CACR";
+			processor = "2+";
+			break;
+		case 0x802:
+			reg_name = "CAAR";
+			processor = "2,3";
+			break;
+		case 0x803:
+			reg_name = "MSP";
+			processor = "2+";
+			break;
+		case 0x804:
+			reg_name = "ISP";
+			processor = "2+";
+			break;
+		case 0x003:
+			reg_name = "TC";
+			processor = "4+";
+			break;
+		case 0x004:
+			reg_name = "ITT0";
+			processor = "4+";
+			break;
+		case 0x005:
+			reg_name = "ITT1";
+			processor = "4+";
+			break;
+		case 0x006:
+			reg_name = "DTT0";
+			processor = "4+";
+			break;
+		case 0x007:
+			reg_name = "DTT1";
+			processor = "4+";
+			break;
+		case 0x805:
+			reg_name = "MMUSR";
+			processor = "4+";
+			break;
+		case 0x806:
+			reg_name = "URP";
+			processor = "4+";
+			break;
+		case 0x807:
+			reg_name = "SRP";
+			processor = "4+";
+			break;
+		default:
+			reg_name = make_signed_hex_str_16(extension & 0xfff);
+			processor = "?";
+	}
+
+	if(BIT_1(g_cpu_ir))
+		sprintf(g_dasm_str, "movec %c%d, %s; (%s)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, reg_name, processor);
+	else
+		sprintf(g_dasm_str, "movec %s, %c%d; (%s)", reg_name, BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, processor);
+}
+
+static void d68000_movem_pd_16(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(15-i)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(15-(i+1)))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(7-i)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(7-(i+1)))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.w %s, %s", buffer, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_movem_pd_32(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(15-i)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(15-(i+1)))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(7-i)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(7-(i+1)))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.l %s, %s", buffer, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_movem_er_16(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<i))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(i+8)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+8+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.w %s, %s", get_ea_mode_str_16(g_cpu_ir), buffer);
+}
+
+static void d68000_movem_er_32(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<i))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(i+8)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+8+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.l %s, %s", get_ea_mode_str_32(g_cpu_ir), buffer);
+}
+
+static void d68000_movem_re_16(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<i))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(i+8)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+8+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.w %s, %s", buffer, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_movem_re_32(void)
+{
+	uint data = read_imm_16();
+	char buffer[40];
+	uint first;
+	uint run_length;
+	uint i;
+
+	buffer[0] = 0;
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<i))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "D%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-D%d", first + run_length);
+		}
+	}
+	for(i=0;i<8;i++)
+	{
+		if(data&(1<<(i+8)))
+		{
+			first = i;
+			run_length = 0;
+			while(i<7 && (data&(1<<(i+8+1))))
+			{
+				i++;
+				run_length++;
+			}
+			if(buffer[0] != 0)
+				strcat(buffer, "/");
+			sprintf(buffer+strlen(buffer), "A%d", first);
+			if(run_length > 0)
+				sprintf(buffer+strlen(buffer), "-A%d", first + run_length);
+		}
+	}
+	sprintf(g_dasm_str, "movem.l %s, %s", buffer, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_movep_re_16(void)
+{
+	sprintf(g_dasm_str, "movep.w D%d, ($%x,A%d)", (g_cpu_ir>>9)&7, read_imm_16(), g_cpu_ir&7);
+}
+
+static void d68000_movep_re_32(void)
+{
+	sprintf(g_dasm_str, "movep.l D%d, ($%x,A%d)", (g_cpu_ir>>9)&7, read_imm_16(), g_cpu_ir&7);
+}
+
+static void d68000_movep_er_16(void)
+{
+	sprintf(g_dasm_str, "movep.w ($%x,A%d), D%d", read_imm_16(), g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_movep_er_32(void)
+{
+	sprintf(g_dasm_str, "movep.l ($%x,A%d), D%d", read_imm_16(), g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68010_moves_8(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	extension = read_imm_16();
+	if(BIT_B(extension))
+		sprintf(g_dasm_str, "moves.b %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_8(g_cpu_ir));
+	else
+		sprintf(g_dasm_str, "moves.b %s, %c%d; (1+)", get_ea_mode_str_8(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68010_moves_16(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	extension = read_imm_16();
+	if(BIT_B(extension))
+		sprintf(g_dasm_str, "moves.w %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_16(g_cpu_ir));
+	else
+		sprintf(g_dasm_str, "moves.w %s, %c%d; (1+)", get_ea_mode_str_16(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68010_moves_32(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	extension = read_imm_16();
+	if(BIT_B(extension))
+		sprintf(g_dasm_str, "moves.l %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_32(g_cpu_ir));
+	else
+		sprintf(g_dasm_str, "moves.l %s, %c%d; (1+)", get_ea_mode_str_32(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7);
+}
+
+static void d68000_moveq(void)
+{
+	sprintf(g_dasm_str, "moveq   #%s, D%d", make_signed_hex_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68040_move16_pi_pi(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	sprintf(g_dasm_str, "move16  (A%d)+, (A%d)+; (4)", g_cpu_ir&7, (read_imm_16()>>12)&7);
+}
+
+static void d68040_move16_pi_al(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	sprintf(g_dasm_str, "move16  (A%d)+, %s; (4)", g_cpu_ir&7, get_imm_str_u32());
+}
+
+static void d68040_move16_al_pi(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	sprintf(g_dasm_str, "move16  %s, (A%d)+; (4)", get_imm_str_u32(), g_cpu_ir&7);
+}
+
+static void d68040_move16_ai_al(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	sprintf(g_dasm_str, "move16  (A%d), %s; (4)", g_cpu_ir&7, get_imm_str_u32());
+}
+
+static void d68040_move16_al_ai(void)
+{
+	LIMIT_CPU_TYPES(M68040_PLUS);
+	sprintf(g_dasm_str, "move16  %s, (A%d); (4)", get_imm_str_u32(), g_cpu_ir&7);
+}
+
+static void d68000_muls(void)
+{
+	sprintf(g_dasm_str, "muls.w  %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_mulu(void)
+{
+	sprintf(g_dasm_str, "mulu.w  %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68020_mull(void)
+{
+	uint extension;
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	extension = read_imm_16();
+
+	if(BIT_A(extension))
+		sprintf(g_dasm_str, "mul%c.l %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7);
+	else
+		sprintf(g_dasm_str, "mul%c.l  %s, D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), (extension>>12)&7);
+}
+
+static void d68000_nbcd(void)
+{
+	sprintf(g_dasm_str, "nbcd    %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_neg_8(void)
+{
+	sprintf(g_dasm_str, "neg.b   %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_neg_16(void)
+{
+	sprintf(g_dasm_str, "neg.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_neg_32(void)
+{
+	sprintf(g_dasm_str, "neg.l   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_negx_8(void)
+{
+	sprintf(g_dasm_str, "negx.b  %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_negx_16(void)
+{
+	sprintf(g_dasm_str, "negx.w  %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_negx_32(void)
+{
+	sprintf(g_dasm_str, "negx.l  %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_nop(void)
+{
+	sprintf(g_dasm_str, "nop");
+}
+
+static void d68000_not_8(void)
+{
+	sprintf(g_dasm_str, "not.b   %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_not_16(void)
+{
+	sprintf(g_dasm_str, "not.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_not_32(void)
+{
+	sprintf(g_dasm_str, "not.l   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_or_er_8(void)
+{
+	sprintf(g_dasm_str, "or.b    %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_or_er_16(void)
+{
+	sprintf(g_dasm_str, "or.w    %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_or_er_32(void)
+{
+	sprintf(g_dasm_str, "or.l    %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_or_re_8(void)
+{
+	sprintf(g_dasm_str, "or.b    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_or_re_16(void)
+{
+	sprintf(g_dasm_str, "or.w    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_or_re_32(void)
+{
+	sprintf(g_dasm_str, "or.l    D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_ori_8(void)
+{
+	char* str = get_imm_str_u8();
+	sprintf(g_dasm_str, "ori.b   %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_ori_16(void)
+{
+	char* str = get_imm_str_u16();
+	sprintf(g_dasm_str, "ori.w   %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_ori_32(void)
+{
+	char* str = get_imm_str_u32();
+	sprintf(g_dasm_str, "ori.l   %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_ori_to_ccr(void)
+{
+	sprintf(g_dasm_str, "ori     %s, CCR", get_imm_str_u8());
+}
+
+static void d68000_ori_to_sr(void)
+{
+	sprintf(g_dasm_str, "ori     %s, SR", get_imm_str_u16());
+}
+
+static void d68020_pack_rr(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "pack    D%d, D%d, %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16());
+}
+
+static void d68020_pack_mm(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "pack    -(A%d), -(A%d), %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16());
+}
+
+static void d68000_pea(void)
+{
+	sprintf(g_dasm_str, "pea     %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_reset(void)
+{
+	sprintf(g_dasm_str, "reset");
+}
+
+static void d68000_ror_s_8(void)
+{
+	sprintf(g_dasm_str, "ror.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_ror_s_16(void)
+{
+	sprintf(g_dasm_str, "ror.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7],g_cpu_ir&7);
+}
+
+static void d68000_ror_s_32(void)
+{
+	sprintf(g_dasm_str, "ror.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_ror_r_8(void)
+{
+	sprintf(g_dasm_str, "ror.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_ror_r_16(void)
+{
+	sprintf(g_dasm_str, "ror.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_ror_r_32(void)
+{
+	sprintf(g_dasm_str, "ror.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_ror_ea(void)
+{
+	sprintf(g_dasm_str, "ror.w   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_rol_s_8(void)
+{
+	sprintf(g_dasm_str, "rol.b   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_rol_s_16(void)
+{
+	sprintf(g_dasm_str, "rol.w   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_rol_s_32(void)
+{
+	sprintf(g_dasm_str, "rol.l   #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_rol_r_8(void)
+{
+	sprintf(g_dasm_str, "rol.b   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_rol_r_16(void)
+{
+	sprintf(g_dasm_str, "rol.w   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_rol_r_32(void)
+{
+	sprintf(g_dasm_str, "rol.l   D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_rol_ea(void)
+{
+	sprintf(g_dasm_str, "rol.w   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_roxr_s_8(void)
+{
+	sprintf(g_dasm_str, "roxr.b  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_roxr_s_16(void)
+{
+	sprintf(g_dasm_str, "roxr.w  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+
+static void d68000_roxr_s_32(void)
+{
+	sprintf(g_dasm_str, "roxr.l  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_roxr_r_8(void)
+{
+	sprintf(g_dasm_str, "roxr.b  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxr_r_16(void)
+{
+	sprintf(g_dasm_str, "roxr.w  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxr_r_32(void)
+{
+	sprintf(g_dasm_str, "roxr.l  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxr_ea(void)
+{
+	sprintf(g_dasm_str, "roxr.w  %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_roxl_s_8(void)
+{
+	sprintf(g_dasm_str, "roxl.b  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_roxl_s_16(void)
+{
+	sprintf(g_dasm_str, "roxl.w  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_roxl_s_32(void)
+{
+	sprintf(g_dasm_str, "roxl.l  #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7);
+}
+
+static void d68000_roxl_r_8(void)
+{
+	sprintf(g_dasm_str, "roxl.b  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxl_r_16(void)
+{
+	sprintf(g_dasm_str, "roxl.w  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxl_r_32(void)
+{
+	sprintf(g_dasm_str, "roxl.l  D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7);
+}
+
+static void d68000_roxl_ea(void)
+{
+	sprintf(g_dasm_str, "roxl.w  %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68010_rtd(void)
+{
+	LIMIT_CPU_TYPES(M68010_PLUS);
+	sprintf(g_dasm_str, "rtd     %s; (1+)", get_imm_str_s16());
+}
+
+static void d68000_rte(void)
+{
+	sprintf(g_dasm_str, "rte");
+}
+
+static void d68020_rtm(void)
+{
+	LIMIT_CPU_TYPES(M68020_ONLY);
+	sprintf(g_dasm_str, "rtm     %c%d; (2+)", BIT_3(g_cpu_ir) ? 'A' : 'D', g_cpu_ir&7);
+}
+
+static void d68000_rtr(void)
+{
+	sprintf(g_dasm_str, "rtr");
+}
+
+static void d68000_rts(void)
+{
+	sprintf(g_dasm_str, "rts");
+}
+
+static void d68000_sbcd_rr(void)
+{
+	sprintf(g_dasm_str, "sbcd    D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_sbcd_mm(void)
+{
+	sprintf(g_dasm_str, "sbcd    -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_scc(void)
+{
+	sprintf(g_dasm_str, "s%-2s     %s", g_cc[(g_cpu_ir>>8)&0xf], get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_stop(void)
+{
+	sprintf(g_dasm_str, "stop    %s", get_imm_str_s16());
+}
+
+static void d68000_sub_er_8(void)
+{
+	sprintf(g_dasm_str, "sub.b   %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_sub_er_16(void)
+{
+	sprintf(g_dasm_str, "sub.w   %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_sub_er_32(void)
+{
+	sprintf(g_dasm_str, "sub.l   %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_sub_re_8(void)
+{
+	sprintf(g_dasm_str, "sub.b   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_sub_re_16(void)
+{
+	sprintf(g_dasm_str, "sub.w   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_sub_re_32(void)
+{
+	sprintf(g_dasm_str, "sub.l   D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_suba_16(void)
+{
+	sprintf(g_dasm_str, "suba.w  %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_suba_32(void)
+{
+	sprintf(g_dasm_str, "suba.l  %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subi_8(void)
+{
+	char* str = get_imm_str_s8();
+	sprintf(g_dasm_str, "subi.b  %s, %s", str, get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_subi_16(void)
+{
+	char* str = get_imm_str_s16();
+	sprintf(g_dasm_str, "subi.w  %s, %s", str, get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_subi_32(void)
+{
+	char* str = get_imm_str_s32();
+	sprintf(g_dasm_str, "subi.l  %s, %s", str, get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_subq_8(void)
+{
+	sprintf(g_dasm_str, "subq.b  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_subq_16(void)
+{
+	sprintf(g_dasm_str, "subq.w  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_subq_32(void)
+{
+	sprintf(g_dasm_str, "subq.l  #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_subx_rr_8(void)
+{
+	sprintf(g_dasm_str, "subx.b  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subx_rr_16(void)
+{
+	sprintf(g_dasm_str, "subx.w  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subx_rr_32(void)
+{
+	sprintf(g_dasm_str, "subx.l  D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subx_mm_8(void)
+{
+	sprintf(g_dasm_str, "subx.b  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subx_mm_16(void)
+{
+	sprintf(g_dasm_str, "subx.w  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_subx_mm_32(void)
+{
+	sprintf(g_dasm_str, "subx.l  -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7);
+}
+
+static void d68000_swap(void)
+{
+	sprintf(g_dasm_str, "swap    D%d", g_cpu_ir&7);
+}
+
+static void d68000_tas(void)
+{
+	sprintf(g_dasm_str, "tas     %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_trap(void)
+{
+	sprintf(g_dasm_str, "trap    #$%x", g_cpu_ir&0xf);
+}
+
+static void d68020_trapcc_0(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "trap%-2s; (2+)", g_cc[(g_cpu_ir>>8)&0xf]);
+}
+
+static void d68020_trapcc_16(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "trap%-2s  %s; (2+)", g_cc[(g_cpu_ir>>8)&0xf], get_imm_str_u16());
+}
+
+static void d68020_trapcc_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "trap%-2s  %s; (2+)", g_cc[(g_cpu_ir>>8)&0xf], get_imm_str_u32());
+}
+
+static void d68000_trapv(void)
+{
+	sprintf(g_dasm_str, "trapv");
+}
+
+static void d68000_tst_8(void)
+{
+	sprintf(g_dasm_str, "tst.b   %s", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_tst_pcdi_8(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.b   %s; (2+)", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_tst_pcix_8(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.b   %s; (2+)", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68020_tst_i_8(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.b   %s; (2+)", get_ea_mode_str_8(g_cpu_ir));
+}
+
+static void d68000_tst_16(void)
+{
+	sprintf(g_dasm_str, "tst.w   %s", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_tst_a_16(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.w   %s; (2+)", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_tst_pcdi_16(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.w   %s; (2+)", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_tst_pcix_16(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.w   %s; (2+)", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68020_tst_i_16(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.w   %s; (2+)", get_ea_mode_str_16(g_cpu_ir));
+}
+
+static void d68000_tst_32(void)
+{
+	sprintf(g_dasm_str, "tst.l   %s", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_tst_a_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.l   %s; (2+)", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_tst_pcdi_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.l   %s; (2+)", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_tst_pcix_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.l   %s; (2+)", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68020_tst_i_32(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "tst.l   %s; (2+)", get_ea_mode_str_32(g_cpu_ir));
+}
+
+static void d68000_unlk(void)
+{
+	sprintf(g_dasm_str, "unlk    A%d", g_cpu_ir&7);
+}
+
+static void d68020_unpk_rr(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "unpk    D%d, D%d, %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16());
+}
+
+static void d68020_unpk_mm(void)
+{
+	LIMIT_CPU_TYPES(M68020_PLUS);
+	sprintf(g_dasm_str, "unpk    -(A%d), -(A%d), %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16());
+}
+
+
+
+/* ======================================================================== */
+/* ======================= INSTRUCTION TABLE BUILDER ====================== */
+/* ======================================================================== */
+
+/* EA Masks:
+800 = data register direct
+400 = address register direct
+200 = address register indirect
+100 = ARI postincrement
+ 80 = ARI pre-decrement
+ 40 = ARI displacement
+ 20 = ARI index
+ 10 = absolute short
+  8 = absolute long
+  4 = immediate / sr
+  2 = pc displacement
+  1 = pc idx
+*/
+
+static opcode_struct g_opcode_info[] =
+{
+/*  opcode handler    mask    match   ea mask */
+	{d68000_1010         , 0xf000, 0xa000, 0x000},
+	{d68000_1111         , 0xf000, 0xf000, 0x000},
+	{d68000_abcd_rr      , 0xf1f8, 0xc100, 0x000},
+	{d68000_abcd_mm      , 0xf1f8, 0xc108, 0x000},
+	{d68000_add_er_8     , 0xf1c0, 0xd000, 0xbff},
+	{d68000_add_er_16    , 0xf1c0, 0xd040, 0xfff},
+	{d68000_add_er_32    , 0xf1c0, 0xd080, 0xfff},
+	{d68000_add_re_8     , 0xf1c0, 0xd100, 0x3f8},
+	{d68000_add_re_16    , 0xf1c0, 0xd140, 0x3f8},
+	{d68000_add_re_32    , 0xf1c0, 0xd180, 0x3f8},
+	{d68000_adda_16      , 0xf1c0, 0xd0c0, 0xfff},
+	{d68000_adda_32      , 0xf1c0, 0xd1c0, 0xfff},
+	{d68000_addi_8       , 0xffc0, 0x0600, 0xbf8},
+	{d68000_addi_16      , 0xffc0, 0x0640, 0xbf8},
+	{d68000_addi_32      , 0xffc0, 0x0680, 0xbf8},
+	{d68000_addq_8       , 0xf1c0, 0x5000, 0xbf8},
+	{d68000_addq_16      , 0xf1c0, 0x5040, 0xff8},
+	{d68000_addq_32      , 0xf1c0, 0x5080, 0xff8},
+	{d68000_addx_rr_8    , 0xf1f8, 0xd100, 0x000},
+	{d68000_addx_rr_16   , 0xf1f8, 0xd140, 0x000},
+	{d68000_addx_rr_32   , 0xf1f8, 0xd180, 0x000},
+	{d68000_addx_mm_8    , 0xf1f8, 0xd108, 0x000},
+	{d68000_addx_mm_16   , 0xf1f8, 0xd148, 0x000},
+	{d68000_addx_mm_32   , 0xf1f8, 0xd188, 0x000},
+	{d68000_and_er_8     , 0xf1c0, 0xc000, 0xbff},
+	{d68000_and_er_16    , 0xf1c0, 0xc040, 0xbff},
+	{d68000_and_er_32    , 0xf1c0, 0xc080, 0xbff},
+	{d68000_and_re_8     , 0xf1c0, 0xc100, 0x3f8},
+	{d68000_and_re_16    , 0xf1c0, 0xc140, 0x3f8},
+	{d68000_and_re_32    , 0xf1c0, 0xc180, 0x3f8},
+	{d68000_andi_to_ccr  , 0xffff, 0x023c, 0x000},
+	{d68000_andi_to_sr   , 0xffff, 0x027c, 0x000},
+	{d68000_andi_8       , 0xffc0, 0x0200, 0xbf8},
+	{d68000_andi_16      , 0xffc0, 0x0240, 0xbf8},
+	{d68000_andi_32      , 0xffc0, 0x0280, 0xbf8},
+	{d68000_asr_s_8      , 0xf1f8, 0xe000, 0x000},
+	{d68000_asr_s_16     , 0xf1f8, 0xe040, 0x000},
+	{d68000_asr_s_32     , 0xf1f8, 0xe080, 0x000},
+	{d68000_asr_r_8      , 0xf1f8, 0xe020, 0x000},
+	{d68000_asr_r_16     , 0xf1f8, 0xe060, 0x000},
+	{d68000_asr_r_32     , 0xf1f8, 0xe0a0, 0x000},
+	{d68000_asr_ea       , 0xffc0, 0xe0c0, 0x3f8},
+	{d68000_asl_s_8      , 0xf1f8, 0xe100, 0x000},
+	{d68000_asl_s_16     , 0xf1f8, 0xe140, 0x000},
+	{d68000_asl_s_32     , 0xf1f8, 0xe180, 0x000},
+	{d68000_asl_r_8      , 0xf1f8, 0xe120, 0x000},
+	{d68000_asl_r_16     , 0xf1f8, 0xe160, 0x000},
+	{d68000_asl_r_32     , 0xf1f8, 0xe1a0, 0x000},
+	{d68000_asl_ea       , 0xffc0, 0xe1c0, 0x3f8},
+	{d68000_bcc_8        , 0xf000, 0x6000, 0x000},
+	{d68000_bcc_16       , 0xf0ff, 0x6000, 0x000},
+	{d68020_bcc_32       , 0xf0ff, 0x60ff, 0x000},
+	{d68000_bchg_r       , 0xf1c0, 0x0140, 0xbf8},
+	{d68000_bchg_s       , 0xffc0, 0x0840, 0xbf8},
+	{d68000_bclr_r       , 0xf1c0, 0x0180, 0xbf8},
+	{d68000_bclr_s       , 0xffc0, 0x0880, 0xbf8},
+	{d68020_bfchg        , 0xffc0, 0xeac0, 0xa78},
+	{d68020_bfclr        , 0xffc0, 0xecc0, 0xa78},
+	{d68020_bfexts       , 0xffc0, 0xebc0, 0xa7b},
+	{d68020_bfextu       , 0xffc0, 0xe9c0, 0xa7b},
+	{d68020_bfffo        , 0xffc0, 0xedc0, 0xa7b},
+	{d68020_bfins        , 0xffc0, 0xefc0, 0xa78},
+	{d68020_bfset        , 0xffc0, 0xeec0, 0xa78},
+	{d68020_bftst        , 0xffc0, 0xe8c0, 0xa7b},
+	{d68010_bkpt         , 0xfff8, 0x4848, 0x000},
+	{d68000_bra_8        , 0xff00, 0x6000, 0x000},
+	{d68000_bra_16       , 0xffff, 0x6000, 0x000},
+	{d68020_bra_32       , 0xffff, 0x60ff, 0x000},
+	{d68000_bset_r       , 0xf1c0, 0x01c0, 0xbf8},
+	{d68000_bset_s       , 0xffc0, 0x08c0, 0xbf8},
+	{d68000_bsr_8        , 0xff00, 0x6100, 0x000},
+	{d68000_bsr_16       , 0xffff, 0x6100, 0x000},
+	{d68020_bsr_32       , 0xffff, 0x61ff, 0x000},
+	{d68000_btst_r       , 0xf1c0, 0x0100, 0xbff},
+	{d68000_btst_s       , 0xffc0, 0x0800, 0xbfb},
+	{d68020_callm        , 0xffc0, 0x06c0, 0x27b},
+	{d68020_cas_8        , 0xffc0, 0x0ac0, 0x3f8},
+	{d68020_cas_16       , 0xffc0, 0x0cc0, 0x3f8},
+	{d68020_cas_32       , 0xffc0, 0x0ec0, 0x3f8},
+	{d68020_cas2_16      , 0xffff, 0x0cfc, 0x000},
+	{d68020_cas2_32      , 0xffff, 0x0efc, 0x000},
+	{d68000_chk_16       , 0xf1c0, 0x4180, 0xbff},
+	{d68020_chk_32       , 0xf1c0, 0x4100, 0xbff},
+	{d68020_chk2_cmp2_8  , 0xffc0, 0x00c0, 0x27b},
+	{d68020_chk2_cmp2_16 , 0xffc0, 0x02c0, 0x27b},
+	{d68020_chk2_cmp2_32 , 0xffc0, 0x04c0, 0x27b},
+	{d68040_cinv         , 0xff20, 0xf400, 0x000},
+	{d68000_clr_8        , 0xffc0, 0x4200, 0xbf8},
+	{d68000_clr_16       , 0xffc0, 0x4240, 0xbf8},
+	{d68000_clr_32       , 0xffc0, 0x4280, 0xbf8},
+	{d68000_cmp_8        , 0xf1c0, 0xb000, 0xbff},
+	{d68000_cmp_16       , 0xf1c0, 0xb040, 0xfff},
+	{d68000_cmp_32       , 0xf1c0, 0xb080, 0xfff},
+	{d68000_cmpa_16      , 0xf1c0, 0xb0c0, 0xfff},
+	{d68000_cmpa_32      , 0xf1c0, 0xb1c0, 0xfff},
+	{d68000_cmpi_8       , 0xffc0, 0x0c00, 0xbf8},
+	{d68020_cmpi_pcdi_8  , 0xffff, 0x0c3a, 0x000},
+	{d68020_cmpi_pcix_8  , 0xffff, 0x0c3b, 0x000},
+	{d68000_cmpi_16      , 0xffc0, 0x0c40, 0xbf8},
+	{d68020_cmpi_pcdi_16 , 0xffff, 0x0c7a, 0x000},
+	{d68020_cmpi_pcix_16 , 0xffff, 0x0c7b, 0x000},
+	{d68000_cmpi_32      , 0xffc0, 0x0c80, 0xbf8},
+	{d68020_cmpi_pcdi_32 , 0xffff, 0x0cba, 0x000},
+	{d68020_cmpi_pcix_32 , 0xffff, 0x0cbb, 0x000},
+	{d68000_cmpm_8       , 0xf1f8, 0xb108, 0x000},
+	{d68000_cmpm_16      , 0xf1f8, 0xb148, 0x000},
+	{d68000_cmpm_32      , 0xf1f8, 0xb188, 0x000},
+	{d68020_cpbcc_16     , 0xf1c0, 0xf080, 0x000},
+	{d68020_cpbcc_32     , 0xf1c0, 0xf0c0, 0x000},
+	{d68020_cpdbcc       , 0xf1f8, 0xf048, 0x000},
+	{d68020_cpgen        , 0xf1c0, 0xf000, 0x000},
+	{d68020_cprestore    , 0xf1c0, 0xf140, 0x37f},
+	{d68020_cpsave       , 0xf1c0, 0xf100, 0x2f8},
+	{d68020_cpscc        , 0xf1c0, 0xf040, 0xbf8},
+	{d68020_cptrapcc_0   , 0xf1ff, 0xf07c, 0x000},
+	{d68020_cptrapcc_16  , 0xf1ff, 0xf07a, 0x000},
+	{d68020_cptrapcc_32  , 0xf1ff, 0xf07b, 0x000},
+	{d68040_cpush        , 0xff20, 0xf420, 0x000},
+	{d68000_dbcc         , 0xf0f8, 0x50c8, 0x000},
+	{d68000_dbra         , 0xfff8, 0x51c8, 0x000},
+	{d68000_divs         , 0xf1c0, 0x81c0, 0xbff},
+	{d68000_divu         , 0xf1c0, 0x80c0, 0xbff},
+	{d68020_divl         , 0xffc0, 0x4c40, 0xbff},
+	{d68000_eor_8        , 0xf1c0, 0xb100, 0xbf8},
+	{d68000_eor_16       , 0xf1c0, 0xb140, 0xbf8},
+	{d68000_eor_32       , 0xf1c0, 0xb180, 0xbf8},
+	{d68000_eori_to_ccr  , 0xffff, 0x0a3c, 0x000},
+	{d68000_eori_to_sr   , 0xffff, 0x0a7c, 0x000},
+	{d68000_eori_8       , 0xffc0, 0x0a00, 0xbf8},
+	{d68000_eori_16      , 0xffc0, 0x0a40, 0xbf8},
+	{d68000_eori_32      , 0xffc0, 0x0a80, 0xbf8},
+	{d68000_exg_dd       , 0xf1f8, 0xc140, 0x000},
+	{d68000_exg_aa       , 0xf1f8, 0xc148, 0x000},
+	{d68000_exg_da       , 0xf1f8, 0xc188, 0x000},
+	{d68020_extb_32      , 0xfff8, 0x49c0, 0x000},
+	{d68000_ext_16       , 0xfff8, 0x4880, 0x000},
+	{d68000_ext_32       , 0xfff8, 0x48c0, 0x000},
+	{d68000_illegal      , 0xffff, 0x4afc, 0x000},
+	{d68000_jmp          , 0xffc0, 0x4ec0, 0x27b},
+	{d68000_jsr          , 0xffc0, 0x4e80, 0x27b},
+	{d68000_lea          , 0xf1c0, 0x41c0, 0x27b},
+	{d68000_link_16      , 0xfff8, 0x4e50, 0x000},
+	{d68020_link_32      , 0xfff8, 0x4808, 0x000},
+	{d68000_lsr_s_8      , 0xf1f8, 0xe008, 0x000},
+	{d68000_lsr_s_16     , 0xf1f8, 0xe048, 0x000},
+	{d68000_lsr_s_32     , 0xf1f8, 0xe088, 0x000},
+	{d68000_lsr_r_8      , 0xf1f8, 0xe028, 0x000},
+	{d68000_lsr_r_16     , 0xf1f8, 0xe068, 0x000},
+	{d68000_lsr_r_32     , 0xf1f8, 0xe0a8, 0x000},
+	{d68000_lsr_ea       , 0xffc0, 0xe2c0, 0x3f8},
+	{d68000_lsl_s_8      , 0xf1f8, 0xe108, 0x000},
+	{d68000_lsl_s_16     , 0xf1f8, 0xe148, 0x000},
+	{d68000_lsl_s_32     , 0xf1f8, 0xe188, 0x000},
+	{d68000_lsl_r_8      , 0xf1f8, 0xe128, 0x000},
+	{d68000_lsl_r_16     , 0xf1f8, 0xe168, 0x000},
+	{d68000_lsl_r_32     , 0xf1f8, 0xe1a8, 0x000},
+	{d68000_lsl_ea       , 0xffc0, 0xe3c0, 0x3f8},
+	{d68000_move_8       , 0xf000, 0x1000, 0xbff},
+	{d68000_move_16      , 0xf000, 0x3000, 0xfff},
+	{d68000_move_32      , 0xf000, 0x2000, 0xfff},
+	{d68000_movea_16     , 0xf1c0, 0x3040, 0xfff},
+	{d68000_movea_32     , 0xf1c0, 0x2040, 0xfff},
+	{d68000_move_to_ccr  , 0xffc0, 0x44c0, 0xbff},
+	{d68010_move_fr_ccr  , 0xffc0, 0x42c0, 0xbf8},
+	{d68000_move_to_sr   , 0xffc0, 0x46c0, 0xbff},
+	{d68000_move_fr_sr   , 0xffc0, 0x40c0, 0xbf8},
+	{d68000_move_to_usp  , 0xfff8, 0x4e60, 0x000},
+	{d68000_move_fr_usp  , 0xfff8, 0x4e68, 0x000},
+	{d68010_movec        , 0xfffe, 0x4e7a, 0x000},
+	{d68000_movem_pd_16  , 0xfff8, 0x48a0, 0x000},
+	{d68000_movem_pd_32  , 0xfff8, 0x48e0, 0x000},
+	{d68000_movem_re_16  , 0xffc0, 0x4880, 0x2f8},
+	{d68000_movem_re_32  , 0xffc0, 0x48c0, 0x2f8},
+	{d68000_movem_er_16  , 0xffc0, 0x4c80, 0x37b},
+	{d68000_movem_er_32  , 0xffc0, 0x4cc0, 0x37b},
+	{d68000_movep_er_16  , 0xf1f8, 0x0108, 0x000},
+	{d68000_movep_er_32  , 0xf1f8, 0x0148, 0x000},
+	{d68000_movep_re_16  , 0xf1f8, 0x0188, 0x000},
+	{d68000_movep_re_32  , 0xf1f8, 0x01c8, 0x000},
+	{d68010_moves_8      , 0xffc0, 0x0e00, 0x3f8},
+	{d68010_moves_16     , 0xffc0, 0x0e40, 0x3f8},
+	{d68010_moves_32     , 0xffc0, 0x0e80, 0x3f8},
+	{d68000_moveq        , 0xf100, 0x7000, 0x000},
+	{d68040_move16_pi_pi , 0xfff8, 0xf620, 0x000},
+	{d68040_move16_pi_al , 0xfff8, 0xf600, 0x000},
+	{d68040_move16_al_pi , 0xfff8, 0xf608, 0x000},
+	{d68040_move16_ai_al , 0xfff8, 0xf610, 0x000},
+	{d68040_move16_al_ai , 0xfff8, 0xf618, 0x000},
+	{d68000_muls         , 0xf1c0, 0xc1c0, 0xbff},
+	{d68000_mulu         , 0xf1c0, 0xc0c0, 0xbff},
+	{d68020_mull         , 0xffc0, 0x4c00, 0xbff},
+	{d68000_nbcd         , 0xffc0, 0x4800, 0xbf8},
+	{d68000_neg_8        , 0xffc0, 0x4400, 0xbf8},
+	{d68000_neg_16       , 0xffc0, 0x4440, 0xbf8},
+	{d68000_neg_32       , 0xffc0, 0x4480, 0xbf8},
+	{d68000_negx_8       , 0xffc0, 0x4000, 0xbf8},
+	{d68000_negx_16      , 0xffc0, 0x4040, 0xbf8},
+	{d68000_negx_32      , 0xffc0, 0x4080, 0xbf8},
+	{d68000_nop          , 0xffff, 0x4e71, 0x000},
+	{d68000_not_8        , 0xffc0, 0x4600, 0xbf8},
+	{d68000_not_16       , 0xffc0, 0x4640, 0xbf8},
+	{d68000_not_32       , 0xffc0, 0x4680, 0xbf8},
+	{d68000_or_er_8      , 0xf1c0, 0x8000, 0xbff},
+	{d68000_or_er_16     , 0xf1c0, 0x8040, 0xbff},
+	{d68000_or_er_32     , 0xf1c0, 0x8080, 0xbff},
+	{d68000_or_re_8      , 0xf1c0, 0x8100, 0x3f8},
+	{d68000_or_re_16     , 0xf1c0, 0x8140, 0x3f8},
+	{d68000_or_re_32     , 0xf1c0, 0x8180, 0x3f8},
+	{d68000_ori_to_ccr   , 0xffff, 0x003c, 0x000},
+	{d68000_ori_to_sr    , 0xffff, 0x007c, 0x000},
+	{d68000_ori_8        , 0xffc0, 0x0000, 0xbf8},
+	{d68000_ori_16       , 0xffc0, 0x0040, 0xbf8},
+	{d68000_ori_32       , 0xffc0, 0x0080, 0xbf8},
+	{d68020_pack_rr      , 0xf1f8, 0x8140, 0x000},
+	{d68020_pack_mm      , 0xf1f8, 0x8148, 0x000},
+	{d68000_pea          , 0xffc0, 0x4840, 0x27b},
+	{d68000_reset        , 0xffff, 0x4e70, 0x000},
+	{d68000_ror_s_8      , 0xf1f8, 0xe018, 0x000},
+	{d68000_ror_s_16     , 0xf1f8, 0xe058, 0x000},
+	{d68000_ror_s_32     , 0xf1f8, 0xe098, 0x000},
+	{d68000_ror_r_8      , 0xf1f8, 0xe038, 0x000},
+	{d68000_ror_r_16     , 0xf1f8, 0xe078, 0x000},
+	{d68000_ror_r_32     , 0xf1f8, 0xe0b8, 0x000},
+	{d68000_ror_ea       , 0xffc0, 0xe6c0, 0x3f8},
+	{d68000_rol_s_8      , 0xf1f8, 0xe118, 0x000},
+	{d68000_rol_s_16     , 0xf1f8, 0xe158, 0x000},
+	{d68000_rol_s_32     , 0xf1f8, 0xe198, 0x000},
+	{d68000_rol_r_8      , 0xf1f8, 0xe138, 0x000},
+	{d68000_rol_r_16     , 0xf1f8, 0xe178, 0x000},
+	{d68000_rol_r_32     , 0xf1f8, 0xe1b8, 0x000},
+	{d68000_rol_ea       , 0xffc0, 0xe7c0, 0x3f8},
+	{d68000_roxr_s_8     , 0xf1f8, 0xe010, 0x000},
+	{d68000_roxr_s_16    , 0xf1f8, 0xe050, 0x000},
+	{d68000_roxr_s_32    , 0xf1f8, 0xe090, 0x000},
+	{d68000_roxr_r_8     , 0xf1f8, 0xe030, 0x000},
+	{d68000_roxr_r_16    , 0xf1f8, 0xe070, 0x000},
+	{d68000_roxr_r_32    , 0xf1f8, 0xe0b0, 0x000},
+	{d68000_roxr_ea      , 0xffc0, 0xe4c0, 0x3f8},
+	{d68000_roxl_s_8     , 0xf1f8, 0xe110, 0x000},
+	{d68000_roxl_s_16    , 0xf1f8, 0xe150, 0x000},
+	{d68000_roxl_s_32    , 0xf1f8, 0xe190, 0x000},
+	{d68000_roxl_r_8     , 0xf1f8, 0xe130, 0x000},
+	{d68000_roxl_r_16    , 0xf1f8, 0xe170, 0x000},
+	{d68000_roxl_r_32    , 0xf1f8, 0xe1b0, 0x000},
+	{d68000_roxl_ea      , 0xffc0, 0xe5c0, 0x3f8},
+	{d68010_rtd          , 0xffff, 0x4e74, 0x000},
+	{d68000_rte          , 0xffff, 0x4e73, 0x000},
+	{d68020_rtm          , 0xfff0, 0x06c0, 0x000},
+	{d68000_rtr          , 0xffff, 0x4e77, 0x000},
+	{d68000_rts          , 0xffff, 0x4e75, 0x000},
+	{d68000_sbcd_rr      , 0xf1f8, 0x8100, 0x000},
+	{d68000_sbcd_mm      , 0xf1f8, 0x8108, 0x000},
+	{d68000_scc          , 0xf0c0, 0x50c0, 0xbf8},
+	{d68000_stop         , 0xffff, 0x4e72, 0x000},
+	{d68000_sub_er_8     , 0xf1c0, 0x9000, 0xbff},
+	{d68000_sub_er_16    , 0xf1c0, 0x9040, 0xfff},
+	{d68000_sub_er_32    , 0xf1c0, 0x9080, 0xfff},
+	{d68000_sub_re_8     , 0xf1c0, 0x9100, 0x3f8},
+	{d68000_sub_re_16    , 0xf1c0, 0x9140, 0x3f8},
+	{d68000_sub_re_32    , 0xf1c0, 0x9180, 0x3f8},
+	{d68000_suba_16      , 0xf1c0, 0x90c0, 0xfff},
+	{d68000_suba_32      , 0xf1c0, 0x91c0, 0xfff},
+	{d68000_subi_8       , 0xffc0, 0x0400, 0xbf8},
+	{d68000_subi_16      , 0xffc0, 0x0440, 0xbf8},
+	{d68000_subi_32      , 0xffc0, 0x0480, 0xbf8},
+	{d68000_subq_8       , 0xf1c0, 0x5100, 0xbf8},
+	{d68000_subq_16      , 0xf1c0, 0x5140, 0xff8},
+	{d68000_subq_32      , 0xf1c0, 0x5180, 0xff8},
+	{d68000_subx_rr_8    , 0xf1f8, 0x9100, 0x000},
+	{d68000_subx_rr_16   , 0xf1f8, 0x9140, 0x000},
+	{d68000_subx_rr_32   , 0xf1f8, 0x9180, 0x000},
+	{d68000_subx_mm_8    , 0xf1f8, 0x9108, 0x000},
+	{d68000_subx_mm_16   , 0xf1f8, 0x9148, 0x000},
+	{d68000_subx_mm_32   , 0xf1f8, 0x9188, 0x000},
+	{d68000_swap         , 0xfff8, 0x4840, 0x000},
+	{d68000_tas          , 0xffc0, 0x4ac0, 0xbf8},
+	{d68000_trap         , 0xfff0, 0x4e40, 0x000},
+	{d68020_trapcc_0     , 0xf0ff, 0x50fc, 0x000},
+	{d68020_trapcc_16    , 0xf0ff, 0x50fa, 0x000},
+	{d68020_trapcc_32    , 0xf0ff, 0x50fb, 0x000},
+	{d68000_trapv        , 0xffff, 0x4e76, 0x000},
+	{d68000_tst_8        , 0xffc0, 0x4a00, 0xbf8},
+	{d68020_tst_pcdi_8   , 0xffff, 0x4a3a, 0x000},
+	{d68020_tst_pcix_8   , 0xffff, 0x4a3b, 0x000},
+	{d68020_tst_i_8      , 0xffff, 0x4a3c, 0x000},
+	{d68000_tst_16       , 0xffc0, 0x4a40, 0xbf8},
+	{d68020_tst_a_16     , 0xfff8, 0x4a48, 0x000},
+	{d68020_tst_pcdi_16  , 0xffff, 0x4a7a, 0x000},
+	{d68020_tst_pcix_16  , 0xffff, 0x4a7b, 0x000},
+	{d68020_tst_i_16     , 0xffff, 0x4a7c, 0x000},
+	{d68000_tst_32       , 0xffc0, 0x4a80, 0xbf8},
+	{d68020_tst_a_32     , 0xfff8, 0x4a88, 0x000},
+	{d68020_tst_pcdi_32  , 0xffff, 0x4aba, 0x000},
+	{d68020_tst_pcix_32  , 0xffff, 0x4abb, 0x000},
+	{d68020_tst_i_32     , 0xffff, 0x4abc, 0x000},
+	{d68000_unlk         , 0xfff8, 0x4e58, 0x000},
+	{d68020_unpk_rr      , 0xf1f8, 0x8180, 0x000},
+	{d68020_unpk_mm      , 0xf1f8, 0x8188, 0x000},
+	{0, 0, 0, 0}
+};
+
+/* Check if opcode is using a valid ea mode */
+static int valid_ea(uint opcode, uint mask)
+{
+	if(mask == 0)
+		return 1;
+
+	switch(opcode & 0x3f)
+	{
+		case 0x00: case 0x01: case 0x02: case 0x03:
+		case 0x04: case 0x05: case 0x06: case 0x07:
+			return (mask & 0x800) != 0;
+		case 0x08: case 0x09: case 0x0a: case 0x0b:
+		case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+			return (mask & 0x400) != 0;
+		case 0x10: case 0x11: case 0x12: case 0x13:
+		case 0x14: case 0x15: case 0x16: case 0x17:
+			return (mask & 0x200) != 0;
+		case 0x18: case 0x19: case 0x1a: case 0x1b:
+		case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+			return (mask & 0x100) != 0;
+		case 0x20: case 0x21: case 0x22: case 0x23:
+		case 0x24: case 0x25: case 0x26: case 0x27:
+			return (mask & 0x080) != 0;
+		case 0x28: case 0x29: case 0x2a: case 0x2b:
+		case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+			return (mask & 0x040) != 0;
+		case 0x30: case 0x31: case 0x32: case 0x33:
+		case 0x34: case 0x35: case 0x36: case 0x37:
+			return (mask & 0x020) != 0;
+		case 0x38:
+			return (mask & 0x010) != 0;
+		case 0x39:
+			return (mask & 0x008) != 0;
+		case 0x3a:
+			return (mask & 0x002) != 0;
+		case 0x3b:
+			return (mask & 0x001) != 0;
+		case 0x3c:
+			return (mask & 0x004) != 0;
+	}
+	return 0;
+
+}
+
+/* Used by qsort */
+static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr)
+{
+	uint a = ((const opcode_struct*)aptr)->mask;
+	uint b = ((const opcode_struct*)bptr)->mask;
+
+	a = ((a & 0xAAAA) >> 1) + (a & 0x5555);
+	a = ((a & 0xCCCC) >> 2) + (a & 0x3333);
+	a = ((a & 0xF0F0) >> 4) + (a & 0x0F0F);
+	a = ((a & 0xFF00) >> 8) + (a & 0x00FF);
+
+	b = ((b & 0xAAAA) >> 1) + (b & 0x5555);
+	b = ((b & 0xCCCC) >> 2) + (b & 0x3333);
+	b = ((b & 0xF0F0) >> 4) + (b & 0x0F0F);
+	b = ((b & 0xFF00) >> 8) + (b & 0x00FF);
+
+	return b - a; /* reversed to get greatest to least sorting */
+}
+
+/* build the opcode handler jump table */
+static void build_opcode_table(void)
+{
+	uint i;
+	uint opcode;
+	opcode_struct* ostruct;
+	uint opcode_info_length = 0;
+
+	for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++)
+		opcode_info_length++;
+
+	qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits);
+
+	for(i=0;i<0x10000;i++)
+	{
+		g_instruction_table[i] = d68000_illegal; /* default to illegal */
+		opcode = i;
+		/* search through opcode info for a match */
+		for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++)
+		{
+			/* match opcode mask and allowed ea modes */
+			if((opcode & ostruct->mask) == ostruct->match)
+			{
+				/* Handle destination ea for move instructions */
+				if((ostruct->opcode_handler == d68000_move_8 ||
+					 ostruct->opcode_handler == d68000_move_16 ||
+					 ostruct->opcode_handler == d68000_move_32) &&
+					 !valid_ea(((opcode>>9)&7) | ((opcode>>3)&0x38), 0xbf8))
+						continue;
+				if(valid_ea(opcode, ostruct->ea_mask))
+				{
+					g_instruction_table[i] = ostruct->opcode_handler;
+					break;
+				}
+			}
+		}
+	}
+}
+
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+/* Disasemble one instruction at pc and store in str_buff */
+unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type)
+{
+	if(!g_initialized)
+	{
+		build_opcode_table();
+		g_initialized = 1;
+	}
+	switch(cpu_type)
+	{
+		case M68K_CPU_TYPE_68000:
+			g_cpu_type = TYPE_68000;
+			g_address_mask = 0x00ffffff;
+			break;
+		case M68K_CPU_TYPE_68010:
+			g_cpu_type = TYPE_68010;
+			g_address_mask = 0x00ffffff;
+			break;
+		case M68K_CPU_TYPE_68EC020:
+			g_cpu_type = TYPE_68020;
+			g_address_mask = 0x00ffffff;
+			break;
+		case M68K_CPU_TYPE_68020:
+			g_cpu_type = TYPE_68020;
+			g_address_mask = 0xffffffff;
+			break;
+		case M68K_CPU_TYPE_68030:
+			g_cpu_type = TYPE_68030;
+			g_address_mask = 0xffffffff;
+			break;
+		case M68K_CPU_TYPE_68040:
+			g_cpu_type = TYPE_68040;
+			g_address_mask = 0xffffffff;
+			break;
+		default:
+			return 0;
+	}
+
+	g_cpu_pc = pc;
+	g_helper_str[0] = 0;
+	g_cpu_ir = read_imm_16();
+	g_instruction_table[g_cpu_ir]();
+	sprintf(str_buff, "%s%s", g_dasm_str, g_helper_str);
+	return g_cpu_pc - pc;
+}
+
+char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type)
+{
+	static char buff[100];
+	buff[0] = 0;
+	m68k_disassemble(buff, pc, cpu_type);
+	return buff;
+}
+
+/* Check if the instruction is a valid one */
+unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type)
+{
+	if(!g_initialized)
+	{
+		build_opcode_table();
+		g_initialized = 1;
+	}
+
+	instruction &= 0xffff;
+	if(g_instruction_table[instruction] == d68000_illegal)
+		return 0;
+
+	switch(cpu_type)
+	{
+		case M68K_CPU_TYPE_68000:
+			if(g_instruction_table[instruction] == d68010_bkpt)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_move_fr_ccr)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_movec)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_moves_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_moves_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_moves_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68010_rtd)
+				return 0;
+		case M68K_CPU_TYPE_68010:
+			if(g_instruction_table[instruction] == d68020_bcc_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfchg)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfclr)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfexts)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfextu)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfffo)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfins)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bfset)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bftst)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bra_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_bsr_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_callm)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cas_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cas_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cas_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cas2_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cas2_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_chk_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_chk2_cmp2_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_chk2_cmp2_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_chk2_cmp2_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcdi_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcix_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcdi_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcix_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcdi_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cmpi_pcix_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpbcc_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpbcc_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpdbcc)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpgen)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cprestore)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpsave)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cpscc)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cptrapcc_0)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cptrapcc_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_cptrapcc_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_divl)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_extb_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_link_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_mull)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_pack_rr)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_pack_mm)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_rtm)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_trapcc_0)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_trapcc_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_trapcc_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcdi_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcix_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_i_8)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_a_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcdi_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcix_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_i_16)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_a_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcdi_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_pcix_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_tst_i_32)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_unpk_rr)
+				return 0;
+			if(g_instruction_table[instruction] == d68020_unpk_mm)
+				return 0;
+		case M68K_CPU_TYPE_68EC020:
+		case M68K_CPU_TYPE_68020:
+		case M68K_CPU_TYPE_68030:
+			if(g_instruction_table[instruction] == d68040_cinv)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_cpush)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_move16_pi_pi)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_move16_pi_al)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_move16_al_pi)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_move16_ai_al)
+				return 0;
+			if(g_instruction_table[instruction] == d68040_move16_al_ai)
+				return 0;
+	}
+	if(cpu_type != M68K_CPU_TYPE_68020 && cpu_type != M68K_CPU_TYPE_68EC020 &&
+	  (g_instruction_table[instruction] == d68020_callm ||
+	  g_instruction_table[instruction] == d68020_rtm))
+		return 0;
+
+	return 1;
+}
+
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/MCUME_pico2/picogenold/musashi34/m68kopac.c b/MCUME_pico2/picogenold/musashi34/m68kopac.c
new file mode 100644
index 0000000..3bdacfd
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kopac.c
@@ -0,0 +1,12062 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_1010(void)
+{
+	m68ki_exception_1010();
+}
+
+
+void m68k_op_1111(void)
+{
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_abcd_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_abcd_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_abcd_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res += 6;
+	res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res -= 0xa0;
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_add_8_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pi7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pd7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_8_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_16_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = AY;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_32_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_add_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_add_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_adda_16_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
+}
+
+
+void m68k_op_adda_16_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
+}
+
+
+void m68k_op_adda_16_ai(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_AI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_pi(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_PI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_pd(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_PD_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_di(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_DI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_ix(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_IX_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_aw(void)
+{
+	signed short src = MAKE_INT_16(OPER_AW_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_al(void)
+{
+	signed short src = MAKE_INT_16(OPER_AL_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_pcdi(void)
+{
+	signed short src = MAKE_INT_16(OPER_PCDI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_pcix(void)
+{
+	signed short src = MAKE_INT_16(OPER_PCIX_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_16_i(void)
+{
+	signed short src = MAKE_INT_16(OPER_I_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
+}
+
+
+void m68k_op_adda_32_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
+}
+
+
+void m68k_op_adda_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_adda_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
+}
+
+
+void m68k_op_addi_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_addi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addq_8_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pi7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_pd7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_8_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_addq_16_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+void m68k_op_addq_16_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_16_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = *r_dst;
+	uint res = src + dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_addq_32_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
+}
+
+
+void m68k_op_addq_32_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addq_32_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst;
+
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_addx_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_addx_16_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_addx_32_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_addx_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_V = VFLAG_ADD_8(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_addx_16_mm(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint ea  = EA_AX_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_V = VFLAG_ADD_16(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_addx_32_mm(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint ea  = EA_AX_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = src + dst + XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_ADD_32(src, dst, res);
+	FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_8_er_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_ai(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pi7(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pd(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pd7(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_di(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_ix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_aw(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_al(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pcdi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_pcix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_er_i(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_ai(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pd(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_di(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_ix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_aw(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_al(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pcdi(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_pcix(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_16_er_i(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_d(void)
+{
+	FLAG_Z = DX &= DY;
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_ai(void)
+{
+	FLAG_Z = DX &= OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pi(void)
+{
+	FLAG_Z = DX &= OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pd(void)
+{
+	FLAG_Z = DX &= OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_di(void)
+{
+	FLAG_Z = DX &= OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_ix(void)
+{
+	FLAG_Z = DX &= OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_aw(void)
+{
+	FLAG_Z = DX &= OPER_AW_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_al(void)
+{
+	FLAG_Z = DX &= OPER_AL_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pcdi(void)
+{
+	FLAG_Z = DX &= OPER_PCDI_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_pcix(void)
+{
+	FLAG_Z = DX &= OPER_PCIX_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_32_er_i(void)
+{
+	FLAG_Z = DX &= OPER_I_32();
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_and_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = DX & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = DX & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_and_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_and_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_8_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
+
+	FLAG_N = NFLAG_8(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = src & m68ki_read_8(ea);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_andi_16_d(void)
+{
+	FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
+
+	FLAG_N = NFLAG_16(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = src & m68ki_read_16(ea);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_andi_32_d(void)
+{
+	FLAG_Z = DY &= (OPER_I_32());
+
+	FLAG_N = NFLAG_32(FLAG_Z);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_andi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src & m68ki_read_32(ea);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_andi_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
+}
+
+
+void m68k_op_andi_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() & src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_asr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(GET_MSB_8(src))
+		res |= m68ki_shift_8_table[shift];
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(GET_MSB_16(src))
+		res |= m68ki_shift_16_table[shift];
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(GET_MSB_32(src))
+		res |= m68ki_shift_32_table[shift];
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_X = FLAG_C = src << (9-shift);
+}
+
+
+void m68k_op_asr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 8)
+		{
+			if(GET_MSB_8(src))
+				res |= m68ki_shift_8_table[shift];
+
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+			FLAG_X = FLAG_C = src << (9-shift);
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_8(src))
+		{
+			*r_dst |= 0xff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 16)
+		{
+			if(GET_MSB_16(src))
+				res |= m68ki_shift_16_table[shift];
+
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_16(src))
+		{
+			*r_dst |= 0xffff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			if(GET_MSB_32(src))
+				res |= m68ki_shift_32_table[shift];
+
+			*r_dst = res;
+
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		if(GET_MSB_32(src))
+		{
+			*r_dst = 0xffffffff;
+			FLAG_C = CFLAG_SET;
+			FLAG_X = XFLAG_SET;
+			FLAG_N = NFLAG_SET;
+			FLAG_Z = ZFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	if(GET_MSB_16(src))
+		res |= 0x8000;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = FLAG_X = src << 8;
+}
+
+
+void m68k_op_asl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_X = FLAG_C = src << shift;
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	src &= m68ki_shift_8_table[shift + 1];
+	FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
+}
+
+
+void m68k_op_asl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (8-shift);
+	src &= m68ki_shift_16_table[shift + 1];
+	FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+}
+
+
+void m68k_op_asl_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (24-shift);
+	src &= m68ki_shift_32_table[shift + 1];
+	FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+}
+
+
+void m68k_op_asl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_8_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_X = FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_16_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			src &= m68ki_shift_32_table[shift + 1];
+			FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = (!(src == 0))<<7;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_asl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_asl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	src &= 0xc000;
+	FLAG_V = (!(src == 0 || src == 0xc000))<<7;
+}
+
+
+void m68k_op_bhi_8(void)
+{
+	if(COND_HI())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bls_8(void)
+{
+	if(COND_LS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bcc_8(void)
+{
+	if(COND_CC())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bcs_8(void)
+{
+	if(COND_CS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bne_8(void)
+{
+	if(COND_NE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_beq_8(void)
+{
+	if(COND_EQ())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bvc_8(void)
+{
+	if(COND_VC())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bvs_8(void)
+{
+	if(COND_VS())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bpl_8(void)
+{
+	if(COND_PL())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bmi_8(void)
+{
+	if(COND_MI())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bge_8(void)
+{
+	if(COND_GE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_blt_8(void)
+{
+	if(COND_LT())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bgt_8(void)
+{
+	if(COND_GT())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_ble_8(void)
+{
+	if(COND_LE())
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+		return;
+	}
+	USE_CYCLES(CYC_BCC_NOTAKE_B);
+}
+
+
+void m68k_op_bhi_16(void)
+{
+	if(COND_HI())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bls_16(void)
+{
+	if(COND_LS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bcc_16(void)
+{
+	if(COND_CC())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bcs_16(void)
+{
+	if(COND_CS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bne_16(void)
+{
+	if(COND_NE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_beq_16(void)
+{
+	if(COND_EQ())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bvc_16(void)
+{
+	if(COND_VC())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bvs_16(void)
+{
+	if(COND_VS())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bpl_16(void)
+{
+	if(COND_PL())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bmi_16(void)
+{
+	if(COND_MI())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bge_16(void)
+{
+	if(COND_GE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_blt_16(void)
+{
+	if(COND_LT())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bgt_16(void)
+{
+	if(COND_GT())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_ble_16(void)
+{
+	if(COND_LE())
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_BCC_NOTAKE_W);
+}
+
+
+void m68k_op_bhi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bls_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bcs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bne_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_beq_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bvc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bvs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bpl_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bmi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bge_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_blt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bgt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_ble_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			uint offset = OPER_I_32();
+			REG_PC -= 4;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_32(offset);
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bchg_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst ^= mask;
+}
+
+
+void m68k_op_bchg_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst ^= mask;
+}
+
+
+void m68k_op_bchg_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bchg_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src ^ mask);
+}
+
+
+void m68k_op_bclr_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst &= ~mask;
+}
+
+
+void m68k_op_bclr_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst &= ~mask;
+}
+
+
+void m68k_op_bclr_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bclr_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src & ~mask);
+}
+
+
+void m68k_op_bfchg_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data ^= mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfchg_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long ^ mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte ^ mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data &= ~mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfclr_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long & ~mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte & ~mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2>>12)&7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfexts_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  = MAKE_INT_32(data) >> (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data >>= 32 - width;
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2>>12)&7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfextu_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint data;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+		offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<offset);
+
+		if((offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		REG_D[(word2 >> 12) & 7] = data;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint64 data = DY;
+		uint bit;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+		data = ROL_32(data, offset);
+		FLAG_N = NFLAG_32(data);
+		data >>= 32 - width;
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_PCDI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfffo_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		sint local_offset;
+		uint width = word2;
+		uint data;
+		uint bit;
+		uint ea = EA_PCIX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		local_offset = offset % 8;
+		if(local_offset < 0)
+		{
+			local_offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		data = m68ki_read_32(ea);
+		data = MASK_OUT_ABOVE_32(data<<local_offset);
+
+		if((local_offset+width) > 32)
+			data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
+
+		FLAG_N = NFLAG_32(data);
+		data  >>= (32 - width);
+
+		FLAG_Z = data;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
+			offset++;
+
+		REG_D[(word2>>12)&7] = offset;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+		uint64 insert = REG_D[(word2>>12)&7];
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		insert = MASK_OUT_ABOVE_32(insert << (32 - width));
+		FLAG_N = NFLAG_32(insert);
+		FLAG_Z = insert;
+		insert = ROR_32(insert, offset);
+
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data &= ~mask;
+		*data |= insert;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfins_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint insert_base = REG_D[(word2>>12)&7];
+		uint insert_long;
+		uint insert_byte;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
+		FLAG_N = NFLAG_32(insert_base);
+		FLAG_Z = insert_base;
+		insert_long = insert_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			insert_byte = MASK_OUT_ABOVE_8(insert_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		*data |= mask;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bfset_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = NFLAG_32(data_long << offset);
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		m68ki_write_32(ea, data_long | mask_long);
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+			m68ki_write_8(ea+4, data_byte | mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint offset = (word2>>6)&31;
+		uint width = word2;
+		uint* data = &DY;
+		uint64 mask;
+
+
+		if(BIT_B(word2))
+			offset = REG_D[offset&7];
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+
+		offset &= 31;
+		width = ((width-1) & 31) + 1;
+
+
+		mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask = ROR_32(mask, offset);
+
+		FLAG_N = NFLAG_32(*data<<offset);
+		FLAG_Z = *data & mask;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_AI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_DI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AY_IX_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AW_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_AL_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_PCDI_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bftst_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		sint offset = (word2>>6)&31;
+		uint width = word2;
+		uint mask_base;
+		uint data_long;
+		uint mask_long;
+		uint data_byte = 0;
+		uint mask_byte = 0;
+		uint ea = EA_PCIX_8();
+
+		if(BIT_B(word2))
+			offset = MAKE_INT_32(REG_D[offset&7]);
+		if(BIT_5(word2))
+			width = REG_D[width&7];
+
+		/* Offset is signed so we have to use ugly math =( */
+		ea += offset / 8;
+		offset %= 8;
+		if(offset < 0)
+		{
+			offset += 8;
+			ea--;
+		}
+		width = ((width-1) & 31) + 1;
+
+
+		mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
+		mask_long = mask_base >> offset;
+
+		data_long = m68ki_read_32(ea);
+		FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
+		FLAG_Z = data_long & mask_long;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+
+		if((width + offset) > 32)
+		{
+			mask_byte = MASK_OUT_ABOVE_8(mask_base);
+			data_byte = m68ki_read_8(ea+4);
+			FLAG_Z |= (data_byte & mask_byte);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bkpt(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0);	/* auto-disable (see m68kcpu.h) */
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bra_8(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_bra_16(void)
+{
+	uint offset = OPER_I_16();
+	REG_PC -= 2;
+	m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+	m68ki_branch_16(offset);
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_bra_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint offset = OPER_I_32();
+		REG_PC -= 4;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_32(offset);
+		if(REG_PC == REG_PPC)
+			USE_ALL_CYCLES();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_bset_32_r_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (DX & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst |= mask;
+}
+
+
+void m68k_op_bset_8_r_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_r_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint mask = 1 << (DX & 7);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_32_s_d(void)
+{
+	uint* r_dst = &DY;
+	uint mask = 1 << (OPER_I_8() & 0x1f);
+
+	FLAG_Z = *r_dst & mask;
+	*r_dst |= mask;
+}
+
+
+void m68k_op_bset_8_s_ai(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pi(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pi7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pd(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_pd7(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_di(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_ix(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_aw(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bset_8_s_al(void)
+{
+	uint mask = 1 << (OPER_I_8() & 7);
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+
+	FLAG_Z = src & mask;
+	m68ki_write_8(ea, src | mask);
+}
+
+
+void m68k_op_bsr_8(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
+}
+
+
+void m68k_op_bsr_16(void)
+{
+	uint offset = OPER_I_16();
+	m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	REG_PC -= 2;
+	m68ki_branch_16(offset);
+}
+
+
+void m68k_op_bsr_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint offset = OPER_I_32();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_push_32(REG_PC);
+		REG_PC -= 4;
+		m68ki_branch_32(offset);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_btst_32_r_d(void)
+{
+	FLAG_Z = DY & (1 << (DX & 0x1f));
+}
+
+
+void m68k_op_btst_8_r_ai(void)
+{
+	FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pi(void)
+{
+	FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pi7(void)
+{
+	FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pd(void)
+{
+	FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pd7(void)
+{
+	FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_di(void)
+{
+	FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_ix(void)
+{
+	FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_aw(void)
+{
+	FLAG_Z = OPER_AW_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_al(void)
+{
+	FLAG_Z = OPER_AL_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pcdi(void)
+{
+	FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_pcix(void)
+{
+	FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_8_r_i(void)
+{
+	FLAG_Z = OPER_I_8() & (1 << (DX & 7));
+}
+
+
+void m68k_op_btst_32_s_d(void)
+{
+	FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
+}
+
+
+void m68k_op_btst_8_s_ai(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_AI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pi(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_PI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pi7(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_A7_PI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pd(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_PD_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pd7(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_A7_PD_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_di(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_DI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_ix(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AY_IX_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_aw(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AW_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_al(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_AL_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pcdi(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_PCDI_8() & (1 << bit);
+}
+
+
+void m68k_op_btst_8_s_pcix(void)
+{
+	uint bit = OPER_I_8() & 7;
+
+	FLAG_Z = OPER_PCIX_8() & (1 << bit);
+}
+
+
+void m68k_op_callm_32_ai(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_AI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_di(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_DI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_ix(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AY_IX_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_aw(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AW_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_al(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_AL_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_pcdi(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_PCDI_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_callm_32_pcix(void)
+{
+	/* note: watch out for pcrelative modes */
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		uint ea = EA_PCIX_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_PC += 2;
+(void)ea;	/* just to avoid an 'unused variable' warning */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pi7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_A7_PI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_pd7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_A7_PD_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_8_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_8();
+		uint dest = m68ki_read_8(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_8(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(*compare, dest, res);
+		FLAG_C = CFLAG_8(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_8(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_16_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_16();
+		uint dest = m68ki_read_16(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - MASK_OUT_ABOVE_16(*compare);
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(*compare, dest, res);
+		FLAG_C = CFLAG_16(res);
+
+		if(COND_NE())
+			*compare = MASK_OUT_BELOW_16(*compare) | dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_AI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_PD_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_DI_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AY_IX_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AW_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint ea = EA_AL_32();
+		uint dest = m68ki_read_32(ea);
+		uint* compare = &REG_D[word2 & 7];
+		uint res = dest - *compare;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(*compare, dest, res);
+		FLAG_C = CFLAG_SUB_32(*compare, dest, res);
+
+		if(COND_NE())
+			*compare = dest;
+		else
+		{
+			USE_CYCLES(3);
+			m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
+		}
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas2_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_32();
+		uint* compare1 = &REG_D[(word2 >> 16) & 7];
+		uint ea1 = REG_DA[(word2 >> 28) & 15];
+		uint dest1 = m68ki_read_16(ea1);
+		uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
+		uint* compare2 = &REG_D[word2 & 7];
+		uint ea2 = REG_DA[(word2 >> 12) & 15];
+		uint dest2 = m68ki_read_16(ea2);
+		uint res2;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_16(res1);
+		FLAG_Z = MASK_OUT_ABOVE_16(res1);
+		FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
+		FLAG_C = CFLAG_16(res1);
+
+		if(COND_EQ())
+		{
+			res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
+
+			FLAG_N = NFLAG_16(res2);
+			FLAG_Z = MASK_OUT_ABOVE_16(res2);
+			FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
+			FLAG_C = CFLAG_16(res2);
+
+			if(COND_EQ())
+			{
+				USE_CYCLES(3);
+				m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
+				m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
+				return;
+			}
+		}
+		*compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
+		*compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cas2_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_32();
+		uint* compare1 = &REG_D[(word2 >> 16) & 7];
+		uint ea1 = REG_DA[(word2 >> 28) & 15];
+		uint dest1 = m68ki_read_32(ea1);
+		uint res1 = dest1 - *compare1;
+		uint* compare2 = &REG_D[word2 & 7];
+		uint ea2 = REG_DA[(word2 >> 12) & 15];
+		uint dest2 = m68ki_read_32(ea2);
+		uint res2;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		FLAG_N = NFLAG_32(res1);
+		FLAG_Z = MASK_OUT_ABOVE_32(res1);
+		FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
+		FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
+
+		if(COND_EQ())
+		{
+			res2 = dest2 - *compare2;
+
+			FLAG_N = NFLAG_32(res2);
+			FLAG_Z = MASK_OUT_ABOVE_32(res2);
+			FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
+			FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
+
+			if(COND_EQ())
+			{
+				USE_CYCLES(3);
+				m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
+				m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
+				return;
+			}
+		}
+		*compare1 = dest1;
+		*compare2 = dest2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_16_d(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(DY);
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_ai(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_AI_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pi(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_PI_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pd(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_PD_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_di(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_DI_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_ix(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AY_IX_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_aw(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AW_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_al(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_AL_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pcdi(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_PCDI_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_pcix(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_PCIX_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_16_i(void)
+{
+	sint src = MAKE_INT_16(DX);
+	sint bound = MAKE_INT_16(OPER_I_16());
+
+	FLAG_Z = ZFLAG_16(src); /* Undocumented */
+	FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+	FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+	if(src >= 0 && src <= bound)
+	{
+		return;
+	}
+	FLAG_N = (src < 0)<<7;
+	m68ki_exception_trap(EXCEPTION_CHK);
+}
+
+
+void m68k_op_chk_32_d(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(DY);
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_AI_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_PI_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pd(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_PD_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_DI_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AY_IX_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AW_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_AL_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_PCDI_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_PCIX_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk_32_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		sint src = MAKE_INT_32(DX);
+		sint bound = MAKE_INT_32(OPER_I_32());
+
+		FLAG_Z = ZFLAG_32(src); /* Undocumented */
+		FLAG_V = VFLAG_CLEAR;   /* Undocumented */
+		FLAG_C = CFLAG_CLEAR;   /* Undocumented */
+
+		if(src >= 0 && src <= bound)
+		{
+			return;
+		}
+		FLAG_N = (src < 0)<<7;
+		m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_PCDI_8();
+		uint lower_bound = m68ki_read_pcrel_8(ea);
+		uint upper_bound = m68ki_read_pcrel_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_PCIX_8();
+		uint lower_bound = m68ki_read_pcrel_8(ea);
+		uint upper_bound = m68ki_read_pcrel_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_AY_AI_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_AY_DI_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_AY_IX_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_AW_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_8_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
+		uint ea = EA_AL_8();
+		uint lower_bound = m68ki_read_8(ea);
+		uint upper_bound = m68ki_read_8(ea + 1);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_PCDI_16();
+		uint lower_bound = m68ki_read_pcrel_16(ea);
+		uint upper_bound = m68ki_read_pcrel_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_PCIX_16();
+		uint lower_bound = m68ki_read_pcrel_16(ea);
+		uint upper_bound = m68ki_read_pcrel_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_AY_AI_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_AY_DI_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_AY_IX_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_AW_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_16_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
+		uint ea = EA_AL_16();
+		uint lower_bound = m68ki_read_16(ea);
+		uint upper_bound = m68ki_read_16(ea + 2);
+
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
+		else
+			FLAG_C = compare - lower_bound;
+
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+		if(!BIT_F(word2))
+			FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
+		else
+			FLAG_C = upper_bound - compare;
+
+		FLAG_C = CFLAG_16(FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCDI_32();
+		uint lower_bound = m68ki_read_pcrel_32(ea);
+		uint upper_bound = m68ki_read_pcrel_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_PCIX_32();
+		uint lower_bound = m68ki_read_pcrel_32(ea);
+		uint upper_bound = m68ki_read_pcrel_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_ai(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_AI_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_di(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_DI_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_ix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AY_IX_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_aw(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AW_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_chk2cmp2_32_al(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint compare = REG_DA[(word2 >> 12) & 15];
+		uint ea = EA_AL_32();
+		uint lower_bound = m68ki_read_32(ea);
+		uint upper_bound = m68ki_read_32(ea + 4);
+
+		FLAG_C = compare - lower_bound;
+		FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
+		FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
+		if(COND_CS())
+		{
+			if(BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+			return;
+		}
+
+		FLAG_C = upper_bound - compare;
+		FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
+		if(COND_CS() && BIT_B(word2))
+				m68ki_exception_trap(EXCEPTION_CHK);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_clr_8_d(void)
+{
+	DY &= 0xffffff00;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_d(void)
+{
+	DY &= 0xffff0000;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_ai(void)
+{
+	m68ki_write_16(EA_AY_AI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_pi(void)
+{
+	m68ki_write_16(EA_AY_PI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_pd(void)
+{
+	m68ki_write_16(EA_AY_PD_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_di(void)
+{
+	m68ki_write_16(EA_AY_DI_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_ix(void)
+{
+	m68ki_write_16(EA_AY_IX_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_aw(void)
+{
+	m68ki_write_16(EA_AW_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_16_al(void)
+{
+	m68ki_write_16(EA_AL_16(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_d(void)
+{
+	DY = 0;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_ai(void)
+{
+	m68ki_write_32(EA_AY_AI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_pi(void)
+{
+	m68ki_write_32(EA_AY_PI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_pd(void)
+{
+	m68ki_write_32(EA_AY_PD_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_di(void)
+{
+	m68ki_write_32(EA_AY_DI_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_ix(void)
+{
+	m68ki_write_32(EA_AY_IX_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_aw(void)
+{
+	m68ki_write_32(EA_AW_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_clr_32_al(void)
+{
+	m68ki_write_32(EA_AL_32(), 0);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_Z = ZFLAG_SET;
+}
+
+
+void m68k_op_cmp_8_d(void)
+{
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_ai(void)
+{
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pi(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pi7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pd(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pd7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_di(void)
+{
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_ix(void)
+{
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_aw(void)
+{
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_al(void)
+{
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pcdi(void)
+{
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_pcix(void)
+{
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_8_i(void)
+{
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmp_16_d(void)
+{
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_a(void)
+{
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_ai(void)
+{
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pi(void)
+{
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pd(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_di(void)
+{
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_ix(void)
+{
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_aw(void)
+{
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_al(void)
+{
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pcdi(void)
+{
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_pcix(void)
+{
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_16_i(void)
+{
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(DX);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmp_32_d(void)
+{
+	uint src = DY;
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_a(void)
+{
+	uint src = AY;
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmp_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint dst = DX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_d(void)
+{
+	uint src = MAKE_INT_16(DY);
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_a(void)
+{
+	uint src = MAKE_INT_16(AY);
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_ai(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_AI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pi(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_PI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pd(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_PD_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_di(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_DI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_ix(void)
+{
+	uint src = MAKE_INT_16(OPER_AY_IX_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_aw(void)
+{
+	uint src = MAKE_INT_16(OPER_AW_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_al(void)
+{
+	uint src = MAKE_INT_16(OPER_AL_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pcdi(void)
+{
+	uint src = MAKE_INT_16(OPER_PCDI_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_pcix(void)
+{
+	uint src = MAKE_INT_16(OPER_PCIX_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_16_i(void)
+{
+	uint src = MAKE_INT_16(OPER_I_16());
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_d(void)
+{
+	uint src = DY;
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_a(void)
+{
+	uint src = AY;
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpa_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint dst = AX;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_8_d(void)
+{
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(DY);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_AI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_PD_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_A7_PD_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_DI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AY_IX_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AW_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint dst = OPER_AL_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpi_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_8();
+		uint dst = OPER_PCDI_8();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(src, dst, res);
+		FLAG_C = CFLAG_8(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_8();
+		uint dst = OPER_PCIX_8();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = MASK_OUT_ABOVE_8(res);
+		FLAG_V = VFLAG_SUB_8(src, dst, res);
+		FLAG_C = CFLAG_8(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_16_d(void)
+{
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(DY);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_AI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_PI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_PD_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_DI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AY_IX_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AW_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint dst = OPER_AL_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpi_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_16();
+		uint dst = OPER_PCDI_16();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(src, dst, res);
+		FLAG_C = CFLAG_16(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_16();
+		uint dst = OPER_PCIX_16();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = MASK_OUT_ABOVE_16(res);
+		FLAG_V = VFLAG_SUB_16(src, dst, res);
+		FLAG_C = CFLAG_16(res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_32_d(void)
+{
+	uint src = OPER_I_32();
+	uint dst = DY;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_AI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_PI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_PD_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_DI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AY_IX_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AW_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint dst = OPER_AL_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cmpi_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_32();
+		uint dst = OPER_PCDI_32();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(src, dst, res);
+		FLAG_C = CFLAG_SUB_32(src, dst, res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpi_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_I_32();
+		uint dst = OPER_PCIX_32();
+		uint res = dst - src;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = MASK_OUT_ABOVE_32(res);
+		FLAG_V = VFLAG_SUB_32(src, dst, res);
+		FLAG_C = CFLAG_SUB_32(src, dst, res);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_cmpm_8_ax7(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8_ay7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = OPER_AX_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8_axy7(void)
+{
+	uint src = OPER_A7_PI_8();
+	uint dst = OPER_A7_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_8(void)
+{
+	uint src = OPER_AY_PI_8();
+	uint dst = OPER_AX_PI_8();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_C = CFLAG_8(res);
+}
+
+
+void m68k_op_cmpm_16(void)
+{
+	uint src = OPER_AY_PI_16();
+	uint dst = OPER_AX_PI_16();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_C = CFLAG_16(res);
+}
+
+
+void m68k_op_cmpm_32(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint dst = OPER_AX_PI_32();
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_C = CFLAG_SUB_32(src, dst, res);
+}
+
+
+void m68k_op_cpbcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpdbcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpgen_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cpscc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+void m68k_op_cptrapcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_1111();
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/musashi34/m68kopdm.c b/MCUME_pico2/picogenold/musashi34/m68kopdm.c
new file mode 100644
index 0000000..7b15722
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kopdm.c
@@ -0,0 +1,13223 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_dbt_16(void)
+{
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbf_16(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+	if(res != 0xffff)
+	{
+		uint offset = OPER_I_16();
+		REG_PC -= 2;
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_branch_16(offset);
+		USE_CYCLES(CYC_DBCC_F_NOEXP);
+		return;
+	}
+	REG_PC += 2;
+	USE_CYCLES(CYC_DBCC_F_EXP);
+}
+
+
+void m68k_op_dbhi_16(void)
+{
+	if(COND_NOT_HI())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbls_16(void)
+{
+	if(COND_NOT_LS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbcc_16(void)
+{
+	if(COND_NOT_CC())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbcs_16(void)
+{
+	if(COND_NOT_CS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbne_16(void)
+{
+	if(COND_NOT_NE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbeq_16(void)
+{
+	if(COND_NOT_EQ())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbvc_16(void)
+{
+	if(COND_NOT_VC())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbvs_16(void)
+{
+	if(COND_NOT_VS())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbpl_16(void)
+{
+	if(COND_NOT_PL())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbmi_16(void)
+{
+	if(COND_NOT_MI())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbge_16(void)
+{
+	if(COND_NOT_GE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dblt_16(void)
+{
+	if(COND_NOT_LT())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dbgt_16(void)
+{
+	if(COND_NOT_GT())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_dble_16(void)
+{
+	if(COND_NOT_LE())
+	{
+		uint* r_dst = &DY;
+		uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		if(res != 0xffff)
+		{
+			uint offset = OPER_I_16();
+			REG_PC -= 2;
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			m68ki_branch_16(offset);
+			USE_CYCLES(CYC_DBCC_F_NOEXP);
+			return;
+		}
+		REG_PC += 2;
+		USE_CYCLES(CYC_DBCC_F_EXP);
+		return;
+	}
+	REG_PC += 2;
+}
+
+
+void m68k_op_divs_16_d(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(DY);
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_ai(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_AI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pi(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_PI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pd(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_PD_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_di(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_DI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_ix(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AY_IX_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_aw(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AW_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_al(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_AL_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_PCDI_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_PCIX_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divs_16_i(void)
+{
+	uint* r_dst = &DX;
+	sint src = MAKE_INT_16(OPER_I_16());
+	sint quotient;
+	sint remainder;
+
+	if(src != 0)
+	{
+		if((uint32)*r_dst == 0x80000000 && src == -1)
+		{
+			FLAG_Z = 0;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = 0;
+			return;
+		}
+
+		quotient = MAKE_INT_32(*r_dst) / src;
+		remainder = MAKE_INT_32(*r_dst) % src;
+
+		if(quotient == MAKE_INT_16(quotient))
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divu_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+
+	if(src != 0)
+	{
+		uint quotient = *r_dst / src;
+		uint remainder = *r_dst % src;
+
+		if(quotient < 0x10000)
+		{
+			FLAG_Z = quotient;
+			FLAG_N = NFLAG_16(quotient);
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
+			return;
+		}
+		FLAG_V = VFLAG_SET;
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+}
+
+
+void m68k_op_divl_32_d(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor   = DY;
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = DY;
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_ai(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_AI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_AI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_PI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_PI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pd(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_PD_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_PD_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_di(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_DI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_DI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_ix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AY_IX_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AY_IX_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_aw(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AW_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AW_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_al(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_AL_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_AL_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pcdi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_PCDI_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_PCDI_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_pcix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_PCIX_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_PCIX_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_divl_32_i(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 divisor = OPER_I_32();
+		uint64 dividend  = 0;
+		uint64 quotient  = 0;
+		uint64 remainder = 0;
+
+		if(divisor != 0)
+		{
+			if(BIT_A(word2))	/* 64 bit */
+			{
+				dividend = REG_D[word2 & 7];
+				dividend <<= 32;
+				dividend |= REG_D[(word2 >> 12) & 7];
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
+					if((sint64)quotient != (sint64)((sint32)quotient))
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					if(quotient > 0xffffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					remainder = dividend % divisor;
+				}
+			}
+			else	/* 32 bit */
+			{
+				dividend = REG_D[(word2 >> 12) & 7];
+				if(BIT_B(word2))	   /* signed */
+				{
+					quotient  = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
+					remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
+				}
+				else					/* unsigned */
+				{
+					quotient = dividend / divisor;
+					remainder = dividend % divisor;
+				}
+			}
+
+			REG_D[word2 & 7] = remainder;
+			REG_D[(word2 >> 12) & 7] = quotient;
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint divisor = OPER_I_32();
+		uint dividend_hi = REG_D[word2 & 7];
+		uint dividend_lo = REG_D[(word2 >> 12) & 7];
+		uint quotient = 0;
+		uint remainder = 0;
+		uint dividend_neg = 0;
+		uint divisor_neg = 0;
+		sint i;
+		uint overflow;
+
+		if(divisor != 0)
+		{
+			/* quad / long : long quotient, long remainder */
+			if(BIT_A(word2))
+			{
+				if(BIT_B(word2))	   /* signed */
+				{
+					/* special case in signed divide */
+					if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
+					{
+						REG_D[word2 & 7] = 0;
+						REG_D[(word2 >> 12) & 7] = 0x80000000;
+
+						FLAG_N = NFLAG_SET;
+						FLAG_Z = ZFLAG_CLEAR;
+						FLAG_V = VFLAG_CLEAR;
+						FLAG_C = CFLAG_CLEAR;
+						return;
+					}
+					if(GET_MSB_32(dividend_hi))
+					{
+						dividend_neg = 1;
+						dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
+						dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
+					}
+					if(GET_MSB_32(divisor))
+					{
+						divisor_neg = 1;
+						divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
+
+					}
+				}
+
+				/* if the upper long is greater than the divisor, we're overflowing. */
+				if(dividend_hi >= divisor)
+				{
+					FLAG_V = VFLAG_SET;
+					return;
+				}
+
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
+					if(remainder >= divisor)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+				for(i = 31; i >= 0; i--)
+				{
+					quotient <<= 1;
+					overflow = GET_MSB_32(remainder);
+					remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
+					if(remainder >= divisor || overflow)
+					{
+						remainder -= divisor;
+						quotient++;
+					}
+				}
+
+				if(BIT_B(word2))	   /* signed */
+				{
+					if(quotient > 0x7fffffff)
+					{
+						FLAG_V = VFLAG_SET;
+						return;
+					}
+					if(dividend_neg)
+					{
+						remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+					}
+					if(divisor_neg)
+						quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
+				}
+
+				REG_D[word2 & 7] = remainder;
+				REG_D[(word2 >> 12) & 7] = quotient;
+
+				FLAG_N = NFLAG_32(quotient);
+				FLAG_Z = quotient;
+				FLAG_V = VFLAG_CLEAR;
+				FLAG_C = CFLAG_CLEAR;
+				return;
+			}
+
+			/* long / long: long quotient, maybe long remainder */
+			if(BIT_B(word2))	   /* signed */
+			{
+				/* Special case in divide */
+				if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
+				{
+					FLAG_N = NFLAG_SET;
+					FLAG_Z = ZFLAG_CLEAR;
+					FLAG_V = VFLAG_CLEAR;
+					FLAG_C = CFLAG_CLEAR;
+					REG_D[(word2 >> 12) & 7] = 0x80000000;
+					REG_D[word2 & 7] = 0;
+					return;
+				}
+				REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
+			}
+			else
+			{
+				REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
+				quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
+			}
+
+			FLAG_N = NFLAG_32(quotient);
+			FLAG_Z = quotient;
+			FLAG_V = VFLAG_CLEAR;
+			FLAG_C = CFLAG_CLEAR;
+			return;
+		}
+		m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_eor_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_d(void)
+{
+	uint res = DY ^= DX;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eor_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = src ^ m68ki_read_8(ea);
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = src ^ m68ki_read_16(ea);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_d(void)
+{
+	uint res = DY ^= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src ^ m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_eori_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
+}
+
+
+void m68k_op_eori_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() ^ src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_exg_32_dd(void)
+{
+	uint* reg_a = &DX;
+	uint* reg_b = &DY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_exg_32_aa(void)
+{
+	uint* reg_a = &AX;
+	uint* reg_b = &AY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_exg_32_da(void)
+{
+	uint* reg_a = &DX;
+	uint* reg_b = &AY;
+	uint tmp = *reg_a;
+	*reg_a = *reg_b;
+	*reg_b = tmp;
+}
+
+
+void m68k_op_ext_16(void)
+{
+	uint* r_dst = &DY;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
+
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_ext_32(void)
+{
+	uint* r_dst = &DY;
+
+	*r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
+
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_extb_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint* r_dst = &DY;
+
+		*r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
+
+		FLAG_N = NFLAG_32(*r_dst);
+		FLAG_Z = *r_dst;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_illegal(void)
+{
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_jmp_32_ai(void)
+{
+	m68ki_jump(EA_AY_AI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_di(void)
+{
+	m68ki_jump(EA_AY_DI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_ix(void)
+{
+	m68ki_jump(EA_AY_IX_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_aw(void)
+{
+	m68ki_jump(EA_AW_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_al(void)
+{
+	m68ki_jump(EA_AL_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_pcdi(void)
+{
+	m68ki_jump(EA_PCDI_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jmp_32_pcix(void)
+{
+	m68ki_jump(EA_PCIX_32());
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	if(REG_PC == REG_PPC)
+		USE_ALL_CYCLES();
+}
+
+
+void m68k_op_jsr_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_al(void)
+{
+	uint ea = EA_AL_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_pcdi(void)
+{
+	uint ea = EA_PCDI_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_jsr_32_pcix(void)
+{
+	uint ea = EA_PCIX_32();
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_push_32(REG_PC);
+	m68ki_jump(ea);
+}
+
+
+void m68k_op_lea_32_ai(void)
+{
+	AX = EA_AY_AI_32();
+}
+
+
+void m68k_op_lea_32_di(void)
+{
+	AX = EA_AY_DI_32();
+}
+
+
+void m68k_op_lea_32_ix(void)
+{
+	AX = EA_AY_IX_32();
+}
+
+
+void m68k_op_lea_32_aw(void)
+{
+	AX = EA_AW_32();
+}
+
+
+void m68k_op_lea_32_al(void)
+{
+	AX = EA_AL_32();
+}
+
+
+void m68k_op_lea_32_pcdi(void)
+{
+	AX = EA_PCDI_32();
+}
+
+
+void m68k_op_lea_32_pcix(void)
+{
+	AX = EA_PCIX_32();
+}
+
+
+void m68k_op_link_16_a7(void)
+{
+	REG_A[7] -= 4;
+	m68ki_write_32(REG_A[7], REG_A[7]);
+	REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_link_16(void)
+{
+	uint* r_dst = &AY;
+
+	m68ki_push_32(*r_dst);
+	*r_dst = REG_A[7];
+	REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+}
+
+
+void m68k_op_link_32_a7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_A[7] -= 4;
+		m68ki_write_32(REG_A[7], REG_A[7]);
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_link_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint* r_dst = &AY;
+
+		m68ki_push_32(*r_dst);
+		*r_dst = REG_A[7];
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_lsr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << (9-shift);
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = src >> shift;
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
+			FLAG_N = NFLAG_CLEAR;
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = src >> 1;
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_CLEAR;
+	FLAG_Z = res;
+	FLAG_C = FLAG_X = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src << shift;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (8-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> (24-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = MASK_OUT_ABOVE_8(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 8)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_X = FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffffff00;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift <= 16)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_X = FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst &= 0xffff0000;
+		FLAG_X = XFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint shift = DX & 0x3f;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32(src << shift);
+
+	if(shift != 0)
+	{
+		USE_CYCLES(shift<<CYC_SHIFT);
+
+		if(shift < 32)
+		{
+			*r_dst = res;
+			FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
+			FLAG_N = NFLAG_32(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		*r_dst = 0;
+		FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
+		FLAG_N = NFLAG_CLEAR;
+		FLAG_Z = ZFLAG_SET;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_lsl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(src << 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_X = FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_al(void)
+{
+	uint res = OPER_AL_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_d_i(void)
+{
+	uint res = OPER_I_8();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ai_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_AI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi7_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pi_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_PI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd7_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_pd_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_PD_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_di_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_DI_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_ix_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AX_IX_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_aw_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AW_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_di(void)
+{
+	uint res = OPER_AY_DI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_aw(void)
+{
+	uint res = OPER_AW_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_al(void)
+{
+	uint res = OPER_AL_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pcdi(void)
+{
+	uint res = OPER_PCDI_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_pcix(void)
+{
+	uint res = OPER_PCIX_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_8_al_i(void)
+{
+	uint res = OPER_I_8();
+	uint ea = EA_AL_8();
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_al(void)
+{
+	uint res = OPER_AL_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_d_i(void)
+{
+	uint res = OPER_I_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ai_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_AI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pi_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_PI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_pd_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_PD_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_di_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_DI_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_ix_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AX_IX_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_aw_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AW_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_a(void)
+{
+	uint res = MASK_OUT_ABOVE_16(AY);
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_di(void)
+{
+	uint res = OPER_AY_DI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_aw(void)
+{
+	uint res = OPER_AW_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_al(void)
+{
+	uint res = OPER_AL_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pcdi(void)
+{
+	uint res = OPER_PCDI_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_pcix(void)
+{
+	uint res = OPER_PCIX_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_16_al_i(void)
+{
+	uint res = OPER_I_16();
+	uint ea = EA_AL_16();
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_d(void)
+{
+	uint res = DY;
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_a(void)
+{
+	uint res = AY;
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_al(void)
+{
+	uint res = OPER_AL_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_d_i(void)
+{
+	uint res = OPER_I_32();
+	uint* r_dst = &DX;
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ai_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_AI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pi_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_PI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_pd_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_PD_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_di_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_DI_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_ix_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AX_IX_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_aw_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AW_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_d(void)
+{
+	uint res = DY;
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_a(void)
+{
+	uint res = AY;
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_di(void)
+{
+	uint res = OPER_AY_DI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_aw(void)
+{
+	uint res = OPER_AW_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_al(void)
+{
+	uint res = OPER_AL_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pcdi(void)
+{
+	uint res = OPER_PCDI_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_pcix(void)
+{
+	uint res = OPER_PCIX_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_move_32_al_i(void)
+{
+	uint res = OPER_I_32();
+	uint ea = EA_AL_32();
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_movea_16_d(void)
+{
+	AX = MAKE_INT_16(DY);
+}
+
+
+void m68k_op_movea_16_a(void)
+{
+	AX = MAKE_INT_16(AY);
+}
+
+
+void m68k_op_movea_16_ai(void)
+{
+	AX = MAKE_INT_16(OPER_AY_AI_16());
+}
+
+
+void m68k_op_movea_16_pi(void)
+{
+	AX = MAKE_INT_16(OPER_AY_PI_16());
+}
+
+
+void m68k_op_movea_16_pd(void)
+{
+	AX = MAKE_INT_16(OPER_AY_PD_16());
+}
+
+
+void m68k_op_movea_16_di(void)
+{
+	AX = MAKE_INT_16(OPER_AY_DI_16());
+}
+
+
+void m68k_op_movea_16_ix(void)
+{
+	AX = MAKE_INT_16(OPER_AY_IX_16());
+}
+
+
+void m68k_op_movea_16_aw(void)
+{
+	AX = MAKE_INT_16(OPER_AW_16());
+}
+
+
+void m68k_op_movea_16_al(void)
+{
+	AX = MAKE_INT_16(OPER_AL_16());
+}
+
+
+void m68k_op_movea_16_pcdi(void)
+{
+	AX = MAKE_INT_16(OPER_PCDI_16());
+}
+
+
+void m68k_op_movea_16_pcix(void)
+{
+	AX = MAKE_INT_16(OPER_PCIX_16());
+}
+
+
+void m68k_op_movea_16_i(void)
+{
+	AX = MAKE_INT_16(OPER_I_16());
+}
+
+
+void m68k_op_movea_32_d(void)
+{
+	AX = DY;
+}
+
+
+void m68k_op_movea_32_a(void)
+{
+	AX = AY;
+}
+
+
+void m68k_op_movea_32_ai(void)
+{
+	AX = OPER_AY_AI_32();
+}
+
+
+void m68k_op_movea_32_pi(void)
+{
+	AX = OPER_AY_PI_32();
+}
+
+
+void m68k_op_movea_32_pd(void)
+{
+	AX = OPER_AY_PD_32();
+}
+
+
+void m68k_op_movea_32_di(void)
+{
+	AX = OPER_AY_DI_32();
+}
+
+
+void m68k_op_movea_32_ix(void)
+{
+	AX = OPER_AY_IX_32();
+}
+
+
+void m68k_op_movea_32_aw(void)
+{
+	AX = OPER_AW_32();
+}
+
+
+void m68k_op_movea_32_al(void)
+{
+	AX = OPER_AL_32();
+}
+
+
+void m68k_op_movea_32_pcdi(void)
+{
+	AX = OPER_PCDI_32();
+}
+
+
+void m68k_op_movea_32_pcix(void)
+{
+	AX = OPER_PCIX_32();
+}
+
+
+void m68k_op_movea_32_i(void)
+{
+	AX = OPER_I_32();
+}
+
+
+void m68k_op_move_16_frc_d(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_AI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_PI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_PD_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_DI_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AY_IX_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AW_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_frc_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		m68ki_write_16(EA_AL_16(), m68ki_get_ccr());
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_move_16_toc_d(void)
+{
+	m68ki_set_ccr(DY);
+}
+
+
+void m68k_op_move_16_toc_ai(void)
+{
+	m68ki_set_ccr(OPER_AY_AI_16());
+}
+
+
+void m68k_op_move_16_toc_pi(void)
+{
+	m68ki_set_ccr(OPER_AY_PI_16());
+}
+
+
+void m68k_op_move_16_toc_pd(void)
+{
+	m68ki_set_ccr(OPER_AY_PD_16());
+}
+
+
+void m68k_op_move_16_toc_di(void)
+{
+	m68ki_set_ccr(OPER_AY_DI_16());
+}
+
+
+void m68k_op_move_16_toc_ix(void)
+{
+	m68ki_set_ccr(OPER_AY_IX_16());
+}
+
+
+void m68k_op_move_16_toc_aw(void)
+{
+	m68ki_set_ccr(OPER_AW_16());
+}
+
+
+void m68k_op_move_16_toc_al(void)
+{
+	m68ki_set_ccr(OPER_AL_16());
+}
+
+
+void m68k_op_move_16_toc_pcdi(void)
+{
+	m68ki_set_ccr(OPER_PCDI_16());
+}
+
+
+void m68k_op_move_16_toc_pcix(void)
+{
+	m68ki_set_ccr(OPER_PCIX_16());
+}
+
+
+void m68k_op_move_16_toc_i(void)
+{
+	m68ki_set_ccr(OPER_I_16());
+}
+
+
+void m68k_op_move_16_frs_d(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_ai(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_AI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_pi(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_PI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_pd(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_PD_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_di(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_DI_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_ix(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AY_IX_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_aw(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AW_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_frs_al(void)
+{
+	if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S)	/* NS990408 */
+	{
+		uint ea = EA_AL_16();
+		m68ki_write_16(ea, m68ki_get_sr());
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_d(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_set_sr(DY);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_ai(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_AI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pi(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_PI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pd(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_PD_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_di(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_DI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_ix(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AY_IX_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_aw(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AW_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_al(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_AL_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pcdi(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_PCDI_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_pcix(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_PCIX_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_16_tos_i(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(new_sr);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_32_fru(void)
+{
+	if(FLAG_S)
+	{
+		AY = REG_USP;
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_move_32_tou(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_USP = AY;
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_movec_32_cr(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+
+			m68ki_trace_t0();		   /* auto-disable (see m68kcpu.h) */
+			switch (word2 & 0xfff)
+			{
+			case 0x000:			   /* SFC */
+				REG_DA[(word2 >> 12) & 15] = REG_SFC;
+				return;
+			case 0x001:			   /* DFC */
+				REG_DA[(word2 >> 12) & 15] = REG_DFC;
+				return;
+			case 0x002:			   /* CACR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = REG_CACR;
+					return;
+				}
+				return;
+			case 0x800:			   /* USP */
+				REG_DA[(word2 >> 12) & 15] = REG_USP;
+				return;
+			case 0x801:			   /* VBR */
+				REG_DA[(word2 >> 12) & 15] = REG_VBR;
+				return;
+			case 0x802:			   /* CAAR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = REG_CAAR;
+					return;
+				}
+				m68ki_exception_illegal();
+				break;
+			case 0x803:			   /* MSP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x804:			   /* ISP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			default:
+				m68ki_exception_illegal();
+				return;
+			}
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_movec_32_rc(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+
+			m68ki_trace_t0();		   /* auto-disable (see m68kcpu.h) */
+			switch (word2 & 0xfff)
+			{
+			case 0x000:			   /* SFC */
+				REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
+				return;
+			case 0x001:			   /* DFC */
+				REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
+				return;
+			case 0x002:			   /* CACR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_CACR = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x800:			   /* USP */
+				REG_USP = REG_DA[(word2 >> 12) & 15];
+				return;
+			case 0x801:			   /* VBR */
+				REG_VBR = REG_DA[(word2 >> 12) & 15];
+				return;
+			case 0x802:			   /* CAAR */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					REG_CAAR = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x803:			   /* MSP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					/* we are in supervisor mode so just check for M flag */
+					if(!FLAG_M)
+					{
+						REG_MSP = REG_DA[(word2 >> 12) & 15];
+						return;
+					}
+					REG_SP = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			case 0x804:			   /* ISP */
+				if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+				{
+					if(!FLAG_M)
+					{
+						REG_SP = REG_DA[(word2 >> 12) & 15];
+						return;
+					}
+					REG_ISP = REG_DA[(word2 >> 12) & 15];
+					return;
+				}
+				m68ki_exception_illegal();
+				return;
+			default:
+				m68ki_exception_illegal();
+				return;
+			}
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_movem_16_re_pd(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			ea -= 2;
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_re_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_32_re_pd(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			ea -= 4;
+			m68ki_write_32(ea, REG_DA[15-i]);
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_re_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			m68ki_write_32(ea, REG_DA[i]);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_16_er_pi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_pcdi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCDI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_pcix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCIX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_16_er_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
+			ea += 2;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_W);
+}
+
+
+void m68k_op_movem_32_er_pi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = AY;
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+	AY = ea;
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_pcdi(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCDI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_pcrel_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_pcix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_PCIX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_pcrel_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_ai(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_AI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_di(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_DI_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_ix(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AY_IX_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_aw(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AW_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movem_32_er_al(void)
+{
+	uint i = 0;
+	uint register_list = OPER_I_16();
+	uint ea = EA_AL_32();
+	uint count = 0;
+
+	for(; i < 16; i++)
+		if(register_list & (1 << i))
+		{
+			REG_DA[i] = m68ki_read_32(ea);
+			ea += 4;
+			count++;
+		}
+
+	USE_CYCLES(count<<CYC_MOVEM_L);
+}
+
+
+void m68k_op_movep_16_re(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = DX;
+
+	m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+void m68k_op_movep_32_re(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+
+	m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
+	m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
+}
+
+
+void m68k_op_movep_16_er(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint* r_dst = &DX;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
+}
+
+
+void m68k_op_movep_32_er(void)
+{
+	uint ea = EA_AY_DI_32();
+
+	DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
+		+ (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
+}
+
+
+void m68k_op_moves_8_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pi7(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_A7_PI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_pd7(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_A7_PD_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_8_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_8();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_16_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_16();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
+				return;
+			}
+			if(BIT_F(word2))		   /* Memory to address register */
+			{
+				REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to data register */
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_ai(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_AI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_pi(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_pd(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_PD_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_di(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_DI_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_ix(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AY_IX_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_aw(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AW_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moves_32_al(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		if(FLAG_S)
+		{
+			uint word2 = OPER_I_16();
+			uint ea = EA_AL_32();
+
+			m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+			if(BIT_B(word2))		   /* Register to memory */
+			{
+				m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
+				if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+					USE_CYCLES(2);
+				return;
+			}
+			/* Memory to register */
+			REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
+			if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+				USE_CYCLES(2);
+			return;
+		}
+		m68ki_exception_privilege_violation();
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_moveq_32(void)
+{
+	uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_muls_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_d(void)
+{
+	uint* r_dst = &DX;
+	uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_ai(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_AI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pi(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_PI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pd(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_PD_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_di(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_DI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_ix(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AY_IX_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_aw(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AW_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_al(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_AL_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_PCDI_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_PCIX_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mulu_16_i(void)
+{
+	uint* r_dst = &DX;
+	uint res = OPER_I_16() * MASK_OUT_ABOVE_16(*r_dst);
+
+	*r_dst = res;
+
+	FLAG_Z = res;
+	FLAG_N = NFLAG_32(res);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_mull_32_d(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = DY;
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = DY;
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_ai(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_AI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_AI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_PI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_PI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pd(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_PD_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_PD_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_di(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_DI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_DI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_ix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AY_IX_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AY_IX_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_aw(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AW_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AW_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_al(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_AL_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_AL_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pcdi(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_PCDI_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_PCDI_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_pcix(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_PCIX_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_PCIX_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+void m68k_op_mull_32_i(void)
+{
+#if M68K_USE_64_BIT
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint64 src = OPER_I_32();
+		uint64 dst = REG_D[(word2 >> 12) & 7];
+		uint64 res;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			res = (sint64)((sint32)src) * (sint64)((sint32)dst);
+			if(!BIT_A(word2))
+			{
+				FLAG_Z = MASK_OUT_ABOVE_32(res);
+				FLAG_N = NFLAG_32(res);
+				FLAG_V = ((sint64)res != (sint32)res)<<7;
+				REG_D[(word2 >> 12) & 7] = FLAG_Z;
+				return;
+			}
+			FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+			FLAG_N = NFLAG_64(res);
+			FLAG_V = VFLAG_CLEAR;
+			REG_D[word2 & 7] = (res >> 32);
+			REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+			return;
+		}
+
+		res = src * dst;
+		if(!BIT_A(word2))
+		{
+			FLAG_Z = MASK_OUT_ABOVE_32(res);
+			FLAG_N = NFLAG_32(res);
+			FLAG_V = (res > 0xffffffff)<<7;
+			REG_D[(word2 >> 12) & 7] = FLAG_Z;
+			return;
+		}
+		FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
+		FLAG_N = NFLAG_64(res);
+		FLAG_V = VFLAG_CLEAR;
+		REG_D[word2 & 7] = (res >> 32);
+		REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
+		return;
+	}
+	m68ki_exception_illegal();
+
+#else
+
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint word2 = OPER_I_16();
+		uint src = OPER_I_32();
+		uint dst = REG_D[(word2 >> 12) & 7];
+		uint neg = GET_MSB_32(src ^ dst);
+		uint src1;
+		uint src2;
+		uint dst1;
+		uint dst2;
+		uint r1;
+		uint r2;
+		uint r3;
+		uint r4;
+		uint lo;
+		uint hi;
+
+		FLAG_C = CFLAG_CLEAR;
+
+		if(BIT_B(word2))			   /* signed */
+		{
+			if(GET_MSB_32(src))
+				src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
+			if(GET_MSB_32(dst))
+				dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
+		}
+
+		src1 = MASK_OUT_ABOVE_16(src);
+		src2 = src>>16;
+		dst1 = MASK_OUT_ABOVE_16(dst);
+		dst2 = dst>>16;
+
+
+		r1 = src1 * dst1;
+		r2 = src1 * dst2;
+		r3 = src2 * dst1;
+		r4 = src2 * dst2;
+
+		lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
+		hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
+
+		if(BIT_B(word2) && neg)
+		{
+			hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
+			lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
+		}
+
+		if(BIT_A(word2))
+		{
+			REG_D[word2 & 7] = hi;
+			REG_D[(word2 >> 12) & 7] = lo;
+			FLAG_N = NFLAG_32(hi);
+			FLAG_Z = hi | lo;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+
+		REG_D[(word2 >> 12) & 7] = lo;
+		FLAG_N = NFLAG_32(lo);
+		FLAG_Z = lo;
+		if(BIT_B(word2))
+			FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
+		else
+			FLAG_V = (hi != 0) << 7;
+		return;
+	}
+	m68ki_exception_illegal();
+
+#endif
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/musashi34/m68kopnz.c b/MCUME_pico2/picogenold/musashi34/m68kopnz.c
new file mode 100644
index 0000000..a2ffbf6
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kopnz.c
@@ -0,0 +1,8817 @@
+#include "m68kcpu.h"
+
+/* ======================================================================== */
+/* ========================= INSTRUCTION HANDLERS ========================= */
+/* ======================================================================== */
+
+
+void m68k_op_nbcd_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint dst = *r_dst;
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_nbcd_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
+
+	if(res != 0x9a)
+	{
+		FLAG_V = ~res; /* Undefined V behavior */
+
+		if((res & 0x0f) == 0xa)
+			res = (res & 0xf0) + 0x10;
+
+		res = MASK_OUT_ABOVE_8(res);
+
+		FLAG_V &= res; /* Undefined V behavior part II */
+
+		m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
+
+		FLAG_Z |= res;
+		FLAG_C = CFLAG_SET;
+		FLAG_X = XFLAG_SET;
+	}
+	else
+	{
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		FLAG_X = XFLAG_CLEAR;
+	}
+	FLAG_N = NFLAG_8(res);	/* Undefined N behavior */
+}
+
+
+void m68k_op_neg_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = *r_dst & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_neg_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_C = FLAG_X = CFLAG_8(res);
+	FLAG_V = src & res;
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (*r_dst & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_neg_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_C = FLAG_X = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - *r_dst;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
+	FLAG_V = (*r_dst & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_neg_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_neg_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_negx_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = *r_dst & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_negx_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = m68ki_read_8(ea);
+	uint res = 0 - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = src & res;
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_negx_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (*r_dst & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_negx_16_ai(void)
+{
+	uint ea  = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_pi(void)
+{
+	uint ea  = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_pd(void)
+{
+	uint ea  = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_di(void)
+{
+	uint ea  = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_ix(void)
+{
+	uint ea  = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_aw(void)
+{
+	uint ea  = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_16_al(void)
+{
+	uint ea  = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = (src & res)>>8;
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_negx_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
+	FLAG_V = (*r_dst & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_negx_32_ai(void)
+{
+	uint ea  = EA_AY_AI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_pi(void)
+{
+	uint ea  = EA_AY_PI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_pd(void)
+{
+	uint ea  = EA_AY_PD_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_di(void)
+{
+	uint ea  = EA_AY_DI_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_ix(void)
+{
+	uint ea  = EA_AY_IX_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_aw(void)
+{
+	uint ea  = EA_AW_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_negx_32_al(void)
+{
+	uint ea  = EA_AL_32();
+	uint src = m68ki_read_32(ea);
+	uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
+	FLAG_V = (src & res)>>24;
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_nop(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+}
+
+
+void m68k_op_not_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_8(~*r_dst);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = MASK_OUT_ABOVE_16(~*r_dst);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_not_32_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_ai(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pi(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pi7(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pd(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pd7(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_di(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_ix(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_aw(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_al(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pcdi(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_pcix(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_er_i(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_ai(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pi(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pd(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_di(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_ix(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_aw(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_al(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pcdi(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_pcix(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_er_i(void)
+{
+	uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16()));
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_d(void)
+{
+	uint res = DX |= DY;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_ai(void)
+{
+	uint res = DX |= OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pi(void)
+{
+	uint res = DX |= OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pd(void)
+{
+	uint res = DX |= OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_di(void)
+{
+	uint res = DX |= OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_ix(void)
+{
+	uint res = DX |= OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_aw(void)
+{
+	uint res = DX |= OPER_AW_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_al(void)
+{
+	uint res = DX |= OPER_AL_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pcdi(void)
+{
+	uint res = DX |= OPER_PCDI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_pcix(void)
+{
+	uint res = DX |= OPER_PCIX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_er_i(void)
+{
+	uint res = DX |= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_or_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint res = DX | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
+
+	m68ki_write_8(ea, res);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_d(void)
+{
+	uint res = DY |= OPER_I_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint res = src | m68ki_read_32(ea);
+
+	m68ki_write_32(ea, res);
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ori_16_toc(void)
+{
+	m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
+}
+
+
+void m68k_op_ori_16_tos(void)
+{
+	if(FLAG_S)
+	{
+		uint src = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		m68ki_set_sr(m68ki_get_sr() | src);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_pack_16_rr(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: DX and DY are reversed in Motorola's docs */
+		uint src = DY + OPER_I_16();
+		uint* r_dst = &DX;
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_ax7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_AY_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_AY_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_ay7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_A7_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_A7_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm_axy7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint ea_src = EA_A7_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_A7_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pack_16_mm(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint ea_src = EA_AY_PD_8();
+		uint src = m68ki_read_8(ea_src);
+		ea_src = EA_AY_PD_8();
+		src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
+
+		m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_pea_32_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_di(void)
+{
+	uint ea = EA_AY_DI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_aw(void)
+{
+	uint ea = EA_AW_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_al(void)
+{
+	uint ea = EA_AL_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_pcdi(void)
+{
+	uint ea = EA_PCDI_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_pea_32_pcix(void)
+{
+	uint ea = EA_PCIX_32();
+
+	m68ki_push_32(ea);
+}
+
+
+void m68k_op_reset(void)
+{
+	if(FLAG_S)
+	{
+		m68ki_output_reset();		   /* auto-disable (see m68kcpu.h) */
+		USE_CYCLES(CYC_RESET);
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_ror_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_8(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-orig_shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_16(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src = *r_dst;
+	uint res = ROR_32(src, shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = src << (9-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_8(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_C = src << (8-((shift-1)&7));
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 15;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_16(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_C = (src >> ((shift - 1) & 15)) << 8;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 31;
+	uint64 src = *r_dst;
+	uint res = ROR_32(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = res;
+		FLAG_C = (src >> ((shift - 1) & 31)) << 8;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_ror_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_16(src, 1);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src << 8;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_8(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_C = src << orig_shift;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROL_16(src, shift);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> (8-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_32_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src = *r_dst;
+	uint res = ROL_32(src, shift);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_C = src >> (24-shift);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 7;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_8(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		if(shift != 0)
+		{
+			*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+			FLAG_C = src << shift;
+			FLAG_N = NFLAG_8(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+		FLAG_C = (src & 1)<<8;
+		FLAG_N = NFLAG_8(src);
+		FLAG_Z = src;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_8(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 15;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		if(shift != 0)
+		{
+			*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+			FLAG_C = (src << shift) >> 8;
+			FLAG_N = NFLAG_16(res);
+			FLAG_Z = res;
+			FLAG_V = VFLAG_CLEAR;
+			return;
+		}
+		FLAG_C = (src & 1)<<8;
+		FLAG_N = NFLAG_16(src);
+		FLAG_Z = src;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_16(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_32_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift & 31;
+	uint64 src = *r_dst;
+	uint res = ROL_32(src, shift);
+
+	if(orig_shift != 0)
+	{
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		*r_dst = res;
+
+		FLAG_C = (src >> (32 - shift)) << 8;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_N = NFLAG_32(src);
+	FLAG_Z = src;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rol_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_C = src >> 7;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+	FLAG_C = FLAG_X = res;
+	res = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src   = *r_dst;
+	uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+	res = ROR_33_64(res, shift);
+
+	FLAG_C = FLAG_X = res >> 24;
+	res = MASK_OUT_ABOVE_32(res);
+
+	*r_dst =  res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+	uint new_x_flag = src & (1 << (shift - 1));
+
+	*r_dst = res;
+
+	FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxr_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 9;
+		uint src   = MASK_OUT_ABOVE_8(*r_dst);
+		uint res   = ROR_9(src | (XFLAG_AS_1() << 8), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res;
+		res = MASK_OUT_ABOVE_8(res);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 17;
+		uint src   = MASK_OUT_ABOVE_16(*r_dst);
+		uint res   = ROR_17(src | (XFLAG_AS_1() << 16), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 8;
+		res = MASK_OUT_ABOVE_16(res);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint   shift = orig_shift % 33;
+		uint64 src   = *r_dst;
+		uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+		res = ROR_33_64(res, shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 24;
+		res = MASK_OUT_ABOVE_32(res);
+
+		*r_dst = res;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift % 33;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
+	uint new_x_flag = src & (1 << (shift - 1));
+
+	if(orig_shift != 0)
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+	if(shift != 0)
+	{
+		*r_dst = res;
+		FLAG_X = (new_x_flag != 0)<<8;
+	}
+	else
+		res = src;
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxr_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxr_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_8_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+	FLAG_C = FLAG_X = res;
+	res = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_s(void)
+{
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_32_s(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint64 src   = *r_dst;
+	uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+	res = ROL_33_64(res, shift);
+
+	FLAG_C = FLAG_X = res >> 24;
+	res = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = res;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+	uint new_x_flag = src & (1 << (32 - shift));
+
+	*r_dst = res;
+
+	FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxl_8_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 9;
+		uint src   = MASK_OUT_ABOVE_8(*r_dst);
+		uint res   = ROL_9(src | (XFLAG_AS_1() << 8), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res;
+		res = MASK_OUT_ABOVE_8(res);
+
+		*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_r(void)
+{
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint shift = orig_shift % 17;
+		uint src   = MASK_OUT_ABOVE_16(*r_dst);
+		uint res   = ROL_17(src | (XFLAG_AS_1() << 16), shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 8;
+		res = MASK_OUT_ABOVE_16(res);
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_16(*r_dst);
+	FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_32_r(void)
+{
+#if M68K_USE_64_BIT
+
+	uint*  r_dst = &DY;
+	uint   orig_shift = DX & 0x3f;
+
+	if(orig_shift != 0)
+	{
+		uint   shift = orig_shift % 33;
+		uint64 src   = *r_dst;
+		uint64 res   = src | (((uint64)XFLAG_AS_1()) << 32);
+
+		res = ROL_33_64(res, shift);
+
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+		FLAG_C = FLAG_X = res >> 24;
+		res = MASK_OUT_ABOVE_32(res);
+
+		*r_dst = res;
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		return;
+	}
+
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_Z = *r_dst;
+	FLAG_V = VFLAG_CLEAR;
+
+#else
+
+	uint* r_dst = &DY;
+	uint orig_shift = DX & 0x3f;
+	uint shift = orig_shift % 33;
+	uint src = *r_dst;
+	uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
+	uint new_x_flag = src & (1 << (32 - shift));
+
+	if(orig_shift != 0)
+		USE_CYCLES(orig_shift<<CYC_SHIFT);
+
+	if(shift != 0)
+	{
+		*r_dst = res;
+		FLAG_X = (new_x_flag != 0)<<8;
+	}
+	else
+		res = src;
+	FLAG_C = FLAG_X;
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+
+#endif
+}
+
+
+void m68k_op_roxl_16_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_roxl_16_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = m68ki_read_16(ea);
+	uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
+
+	FLAG_C = FLAG_X = res >> 8;
+	res = MASK_OUT_ABOVE_16(res);
+
+	m68ki_write_16(ea, res);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_rtd_32(void)
+{
+	if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
+	{
+		uint new_pc = m68ki_pull_32();
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
+		m68ki_jump(new_pc);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_rte_32(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr;
+		uint new_pc;
+		uint format_word;
+
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+
+		if(CPU_TYPE_IS_000(CPU_TYPE))
+		{
+			new_sr = m68ki_pull_16();
+			new_pc = m68ki_pull_32();
+			m68ki_jump(new_pc);
+			m68ki_set_sr(new_sr);
+
+			CPU_INSTR_MODE = INSTRUCTION_YES;
+			CPU_RUN_MODE = RUN_MODE_NORMAL;
+
+			return;
+		}
+
+		if(CPU_TYPE_IS_010(CPU_TYPE))
+		{
+			format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+			if(format_word == 0)
+			{
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				CPU_INSTR_MODE = INSTRUCTION_YES;
+				CPU_RUN_MODE = RUN_MODE_NORMAL;
+				return;
+			}
+			CPU_INSTR_MODE = INSTRUCTION_YES;
+			CPU_RUN_MODE = RUN_MODE_NORMAL;
+			/* Not handling bus fault (9) */
+			m68ki_exception_format_error();
+			return;
+		}
+
+		/* Otherwise it's 020 */
+rte_loop:
+		format_word = m68ki_read_16(REG_A[7]+6) >> 12;
+		switch(format_word)
+		{
+			case 0: /* Normal */
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				CPU_INSTR_MODE = INSTRUCTION_YES;
+				CPU_RUN_MODE = RUN_MODE_NORMAL;
+				return;
+			case 1: /* Throwaway */
+				new_sr = m68ki_pull_16();
+				m68ki_fake_pull_32();	/* program counter */
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_set_sr_noint(new_sr);
+				goto rte_loop;
+			case 2: /* Trap */
+				new_sr = m68ki_pull_16();
+				new_pc = m68ki_pull_32();
+				m68ki_fake_pull_16();	/* format word */
+				m68ki_fake_pull_32();	/* address */
+				m68ki_jump(new_pc);
+				m68ki_set_sr(new_sr);
+				CPU_INSTR_MODE = INSTRUCTION_YES;
+				CPU_RUN_MODE = RUN_MODE_NORMAL;
+				return;
+		}
+		/* Not handling long or short bus fault */
+		CPU_INSTR_MODE = INSTRUCTION_YES;
+		CPU_RUN_MODE = RUN_MODE_NORMAL;
+		m68ki_exception_format_error();
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_rtm_32(void)
+{
+	if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
+	{
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
+					 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
+					 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_rtr_32(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_set_ccr(m68ki_pull_16());
+	m68ki_jump(m68ki_pull_32());
+}
+
+
+void m68k_op_rts_32(void)
+{
+	m68ki_trace_t0();				   /* auto-disable (see m68kcpu.h) */
+	m68ki_jump(m68ki_pull_32());
+}
+
+
+void m68k_op_sbcd_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_sbcd_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_sbcd_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
+
+	FLAG_V = ~res; /* Undefined V behavior */
+
+	if(res > 9)
+		res -= 6;
+	res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
+	FLAG_X = FLAG_C = (res > 0x99) << 8;
+	if(FLAG_C)
+		res += 0xa0;
+
+	res = MASK_OUT_ABOVE_8(res);
+
+	FLAG_V &= res; /* Undefined V behavior part II */
+	FLAG_N = NFLAG_8(res); /* Undefined N behavior */
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_st_8_d(void)
+{
+	DY |= 0xff;
+}
+
+
+void m68k_op_st_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0xff);
+}
+
+
+void m68k_op_st_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0xff);
+}
+
+
+void m68k_op_st_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0xff);
+}
+
+
+void m68k_op_st_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0xff);
+}
+
+
+void m68k_op_st_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0xff);
+}
+
+
+void m68k_op_st_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0xff);
+}
+
+
+void m68k_op_sf_8_d(void)
+{
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sf_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), 0);
+}
+
+
+void m68k_op_sf_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), 0);
+}
+
+
+void m68k_op_sf_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), 0);
+}
+
+
+void m68k_op_sf_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), 0);
+}
+
+
+void m68k_op_sf_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), 0);
+}
+
+
+void m68k_op_sf_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), 0);
+}
+
+
+void m68k_op_sf_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), 0);
+}
+
+
+void m68k_op_shi_8_d(void)
+{
+	if(COND_HI())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sls_8_d(void)
+{
+	if(COND_LS())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_scc_8_d(void)
+{
+	if(COND_CC())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_scs_8_d(void)
+{
+	if(COND_CS())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sne_8_d(void)
+{
+	if(COND_NE())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_seq_8_d(void)
+{
+	if(COND_EQ())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_svc_8_d(void)
+{
+	if(COND_VC())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_svs_8_d(void)
+{
+	if(COND_VS())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_spl_8_d(void)
+{
+	if(COND_PL())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_smi_8_d(void)
+{
+	if(COND_MI())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sge_8_d(void)
+{
+	if(COND_GE())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_slt_8_d(void)
+{
+	if(COND_LT())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sgt_8_d(void)
+{
+	if(COND_GT())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_sle_8_d(void)
+{
+	if(COND_LE())
+	{
+		DY |= 0xff;
+		USE_CYCLES(CYC_SCC_R_TRUE);
+		return;
+	}
+	DY &= 0xffffff00;
+}
+
+
+void m68k_op_shi_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_shi_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_sls_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scc_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_scs_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_sne_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_seq_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svc_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_svs_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_spl_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_smi_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_sge_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_slt_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sgt_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_ai(void)
+{
+	m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pi(void)
+{
+	m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pi7(void)
+{
+	m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pd(void)
+{
+	m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_pd7(void)
+{
+	m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_di(void)
+{
+	m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_ix(void)
+{
+	m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_aw(void)
+{
+	m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_sle_8_al(void)
+{
+	m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0);
+}
+
+
+void m68k_op_stop(void)
+{
+	if(FLAG_S)
+	{
+		uint new_sr = OPER_I_16();
+		m68ki_trace_t0();			   /* auto-disable (see m68kcpu.h) */
+		CPU_STOPPED |= STOP_LEVEL_STOP;
+		m68ki_set_sr(new_sr);
+		if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
+			m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
+		else
+			USE_ALL_CYCLES();
+		return;
+	}
+	m68ki_exception_privilege_violation();
+}
+
+
+void m68k_op_sub_8_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pi7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pd7(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_A7_PD_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_8_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(AY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_16_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_d(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_a(void)
+{
+	uint* r_dst = &DX;
+	uint src = AY;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_ai(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_AI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pd(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_PD_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_di(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_DI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_ix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AY_IX_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_aw(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AW_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_al(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_AL_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pcdi(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCDI_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_pcix(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_PCIX_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_32_er_i(void)
+{
+	uint* r_dst = &DX;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_sub_8_re_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_8_re_al(void)
+{
+	uint ea = EA_AL_8();
+	uint src = MASK_OUT_ABOVE_8(DX);
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_ai(void)
+{
+	uint ea = EA_AY_AI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_pi(void)
+{
+	uint ea = EA_AY_PI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_pd(void)
+{
+	uint ea = EA_AY_PD_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_di(void)
+{
+	uint ea = EA_AY_DI_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_ix(void)
+{
+	uint ea = EA_AY_IX_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_aw(void)
+{
+	uint ea = EA_AW_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_16_re_al(void)
+{
+	uint ea = EA_AL_16();
+	uint src = MASK_OUT_ABOVE_16(DX);
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_ai(void)
+{
+	uint ea = EA_AY_AI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_pi(void)
+{
+	uint ea = EA_AY_PI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_pd(void)
+{
+	uint ea = EA_AY_PD_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_di(void)
+{
+	uint ea = EA_AY_DI_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_ix(void)
+{
+	uint ea = EA_AY_IX_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_aw(void)
+{
+	uint ea = EA_AW_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_sub_32_re_al(void)
+{
+	uint ea = EA_AL_32();
+	uint src = DX;
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_suba_16_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
+}
+
+
+void m68k_op_suba_16_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
+}
+
+
+void m68k_op_suba_16_ai(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_AI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_pi(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_PI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_pd(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_PD_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_di(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_DI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_ix(void)
+{
+	signed short src = MAKE_INT_16(OPER_AY_IX_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_aw(void)
+{
+	signed short src = MAKE_INT_16(OPER_AW_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_al(void)
+{
+	signed short src = MAKE_INT_16(OPER_AL_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_pcdi(void)
+{
+	signed short src = MAKE_INT_16(OPER_PCDI_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_pcix(void)
+{
+	signed short src = MAKE_INT_16(OPER_PCIX_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_16_i(void)
+{
+	signed short src = MAKE_INT_16(OPER_I_16());
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_d(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
+}
+
+
+void m68k_op_suba_32_a(void)
+{
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
+}
+
+
+void m68k_op_suba_32_ai(void)
+{
+	uint src = OPER_AY_AI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_pi(void)
+{
+	uint src = OPER_AY_PI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_pd(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_di(void)
+{
+	uint src = OPER_AY_DI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_ix(void)
+{
+	uint src = OPER_AY_IX_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_aw(void)
+{
+	uint src = OPER_AW_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_al(void)
+{
+	uint src = OPER_AL_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_pcdi(void)
+{
+	uint src = OPER_PCDI_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_pcix(void)
+{
+	uint src = OPER_PCIX_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_suba_32_i(void)
+{
+	uint src = OPER_I_32();
+	uint* r_dst = &AX;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
+}
+
+
+void m68k_op_subi_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_8();
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subi_8_ai(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pi(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pi7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pd(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_pd7(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_di(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_ix(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_aw(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_8_al(void)
+{
+	uint src = OPER_I_8();
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_16();
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subi_16_ai(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_pi(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_pd(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_di(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_ix(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_aw(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_16_al(void)
+{
+	uint src = OPER_I_16();
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = OPER_I_32();
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_subi_32_ai(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_pi(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_pd(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_di(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_ix(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_aw(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subi_32_al(void)
+{
+	uint src = OPER_I_32();
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subq_8_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pi7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_pd7(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_8_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = MASK_OUT_ABOVE_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	m68ki_write_8(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
+}
+
+
+void m68k_op_subq_16_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+void m68k_op_subq_16_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_16_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = MASK_OUT_ABOVE_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	m68ki_write_16(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_d(void)
+{
+	uint* r_dst = &DY;
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint dst = *r_dst;
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	*r_dst = FLAG_Z;
+}
+
+
+void m68k_op_subq_32_a(void)
+{
+	uint* r_dst = &AY;
+
+	*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
+}
+
+
+void m68k_op_subq_32_ai(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_AI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_pi(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_pd(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_di(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_DI_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_ix(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AY_IX_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_aw(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AW_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subq_32_al(void)
+{
+	uint src = (((REG_IR >> 9) - 1) & 7) + 1;
+	uint ea = EA_AL_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = MASK_OUT_ABOVE_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	m68ki_write_32(ea, FLAG_Z);
+}
+
+
+void m68k_op_subx_8_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_8(DY);
+	uint dst = MASK_OUT_ABOVE_8(*r_dst);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
+}
+
+
+void m68k_op_subx_16_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = MASK_OUT_ABOVE_16(DY);
+	uint dst = MASK_OUT_ABOVE_16(*r_dst);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
+}
+
+
+void m68k_op_subx_32_rr(void)
+{
+	uint* r_dst = &DX;
+	uint src = DY;
+	uint dst = *r_dst;
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	*r_dst = res;
+}
+
+
+void m68k_op_subx_8_mm_ax7(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm_ay7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm_axy7(void)
+{
+	uint src = OPER_A7_PD_8();
+	uint ea  = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_8_mm(void)
+{
+	uint src = OPER_AY_PD_8();
+	uint ea  = EA_AX_PD_8();
+	uint dst = m68ki_read_8(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_X = FLAG_C = CFLAG_8(res);
+	FLAG_V = VFLAG_SUB_8(src, dst, res);
+
+	res = MASK_OUT_ABOVE_8(res);
+	FLAG_Z |= res;
+
+	m68ki_write_8(ea, res);
+}
+
+
+void m68k_op_subx_16_mm(void)
+{
+	uint src = OPER_AY_PD_16();
+	uint ea  = EA_AX_PD_16();
+	uint dst = m68ki_read_16(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_X = FLAG_C = CFLAG_16(res);
+	FLAG_V = VFLAG_SUB_16(src, dst, res);
+
+	res = MASK_OUT_ABOVE_16(res);
+	FLAG_Z |= res;
+
+	m68ki_write_16(ea, res);
+}
+
+
+void m68k_op_subx_32_mm(void)
+{
+	uint src = OPER_AY_PD_32();
+	uint ea  = EA_AX_PD_32();
+	uint dst = m68ki_read_32(ea);
+	uint res = dst - src - XFLAG_AS_1();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
+	FLAG_V = VFLAG_SUB_32(src, dst, res);
+
+	res = MASK_OUT_ABOVE_32(res);
+	FLAG_Z |= res;
+
+	m68ki_write_32(ea, res);
+}
+
+
+void m68k_op_swap_32(void)
+{
+	uint* r_dst = &DY;
+
+	FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
+	*r_dst = (*r_dst>>16) | FLAG_Z;
+
+	FLAG_Z = *r_dst;
+	FLAG_N = NFLAG_32(*r_dst);
+	FLAG_C = CFLAG_CLEAR;
+	FLAG_V = VFLAG_CLEAR;
+}
+
+
+void m68k_op_tas_8_d(void)
+{
+	uint* r_dst = &DY;
+
+	FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
+	FLAG_N = NFLAG_8(*r_dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	*r_dst |= 0x80;
+}
+
+
+void m68k_op_tas_8_ai(void)
+{
+	uint ea = EA_AY_AI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_pi(void)
+{
+	uint ea = EA_AY_PI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_pi7(void)
+{
+	uint ea = EA_A7_PI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_pd(void)
+{
+	uint ea = EA_AY_PD_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_pd7(void)
+{
+	uint ea = EA_A7_PD_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_di(void)
+{
+	uint ea = EA_AY_DI_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_ix(void)
+{
+	uint ea = EA_AY_IX_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_aw(void)
+{
+	uint ea = EA_AW_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_tas_8_al(void)
+{
+	uint ea = EA_AL_8();
+	uint dst = m68ki_read_8(ea);
+
+	FLAG_Z = dst;
+	FLAG_N = NFLAG_8(dst);
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+	m68ki_write_8(ea, dst | 0x80);
+}
+
+
+void m68k_op_trap(void)
+{
+	/* Trap#n stacks exception frame type 0 */
+	m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf));	/* HJB 990403 */
+}
+
+
+void m68k_op_trapt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapf_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple_16(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 2;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traphi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_HI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapls_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapcs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_CS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapne_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_NE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapeq_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_EQ())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvc_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VC())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapvs_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_VS())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trappl_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_PL())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapmi_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_MI())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapge_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traplt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapgt_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_GT())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_traple_32(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		if(COND_LE())
+		{
+			m68ki_exception_trap(EXCEPTION_TRAPV);	/* HJB 990403 */
+			return;
+		}
+		REG_PC += 4;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_trapv(void)
+{
+	if(COND_VC())
+	{
+		return;
+	}
+	m68ki_exception_trap(EXCEPTION_TRAPV);  /* HJB 990403 */
+}
+
+
+void m68k_op_tst_8_d(void)
+{
+	uint res = MASK_OUT_ABOVE_8(DY);
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_ai(void)
+{
+	uint res = OPER_AY_AI_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pi(void)
+{
+	uint res = OPER_AY_PI_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pi7(void)
+{
+	uint res = OPER_A7_PI_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pd(void)
+{
+	uint res = OPER_AY_PD_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pd7(void)
+{
+	uint res = OPER_A7_PD_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_di(void)
+{
+	uint res = OPER_AY_DI_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_ix(void)
+{
+	uint res = OPER_AY_IX_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_aw(void)
+{
+	uint res = OPER_AW_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_al(void)
+{
+	uint res = OPER_AL_8();
+
+	FLAG_N = NFLAG_8(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_8_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_8_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_8_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_8();
+
+		FLAG_N = NFLAG_8(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_d(void)
+{
+	uint res = MASK_OUT_ABOVE_16(DY);
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_a(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = MAKE_INT_16(AY);
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_ai(void)
+{
+	uint res = OPER_AY_AI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pi(void)
+{
+	uint res = OPER_AY_PI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pd(void)
+{
+	uint res = OPER_AY_PD_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_di(void)
+{
+	uint res = OPER_AY_DI_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_ix(void)
+{
+	uint res = OPER_AY_IX_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_aw(void)
+{
+	uint res = OPER_AW_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_al(void)
+{
+	uint res = OPER_AL_16();
+
+	FLAG_N = NFLAG_16(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_16_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_16_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_16();
+
+		FLAG_N = NFLAG_16(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_d(void)
+{
+	uint res = DY;
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_a(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = AY;
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_ai(void)
+{
+	uint res = OPER_AY_AI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pi(void)
+{
+	uint res = OPER_AY_PI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pd(void)
+{
+	uint res = OPER_AY_PD_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_di(void)
+{
+	uint res = OPER_AY_DI_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_ix(void)
+{
+	uint res = OPER_AY_IX_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_aw(void)
+{
+	uint res = OPER_AW_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_al(void)
+{
+	uint res = OPER_AL_32();
+
+	FLAG_N = NFLAG_32(res);
+	FLAG_Z = res;
+	FLAG_V = VFLAG_CLEAR;
+	FLAG_C = CFLAG_CLEAR;
+}
+
+
+void m68k_op_tst_32_pcdi(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCDI_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_pcix(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_PCIX_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_tst_32_i(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint res = OPER_I_32();
+
+		FLAG_N = NFLAG_32(res);
+		FLAG_Z = res;
+		FLAG_V = VFLAG_CLEAR;
+		FLAG_C = CFLAG_CLEAR;
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unlk_32_a7(void)
+{
+	REG_A[7] = m68ki_read_32(REG_A[7]);
+}
+
+
+void m68k_op_unlk_32(void)
+{
+	uint* r_dst = &AY;
+
+	REG_A[7] = *r_dst;
+	*r_dst = m68ki_pull_32();
+}
+
+
+void m68k_op_unpk_16_rr(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: DX and DY are reversed in Motorola's docs */
+		uint src = DY;
+		uint* r_dst = &DX;
+
+		*r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_ax7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_AY_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_ay7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_A7_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm_axy7(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		uint src = OPER_A7_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_A7_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+void m68k_op_unpk_16_mm(void)
+{
+	if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
+	{
+		/* Note: AX and AY are reversed in Motorola's docs */
+		uint src = OPER_AY_PD_8();
+		uint ea_dst;
+
+		src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, (src >> 8) & 0xff);
+		ea_dst = EA_AX_PD_8();
+		m68ki_write_8(ea_dst, src & 0xff);
+		return;
+	}
+	m68ki_exception_illegal();
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+
diff --git a/MCUME_pico2/picogenold/musashi34/m68kops.h b/MCUME_pico2/picogenold/musashi34/m68kops.h
new file mode 100644
index 0000000..a531e73
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kops.h
@@ -0,0 +1,1988 @@
+#ifndef M68KOPS__HEADER
+#define M68KOPS__HEADER
+
+/* ======================================================================== */
+/* ============================ OPCODE HANDLERS =========================== */
+/* ======================================================================== */
+
+
+void m68k_op_1010(void);
+void m68k_op_1111(void);
+void m68k_op_abcd_8_rr(void);
+void m68k_op_abcd_8_mm_ax7(void);
+void m68k_op_abcd_8_mm_ay7(void);
+void m68k_op_abcd_8_mm_axy7(void);
+void m68k_op_abcd_8_mm(void);
+void m68k_op_add_8_er_d(void);
+void m68k_op_add_8_er_ai(void);
+void m68k_op_add_8_er_pi(void);
+void m68k_op_add_8_er_pi7(void);
+void m68k_op_add_8_er_pd(void);
+void m68k_op_add_8_er_pd7(void);
+void m68k_op_add_8_er_di(void);
+void m68k_op_add_8_er_ix(void);
+void m68k_op_add_8_er_aw(void);
+void m68k_op_add_8_er_al(void);
+void m68k_op_add_8_er_pcdi(void);
+void m68k_op_add_8_er_pcix(void);
+void m68k_op_add_8_er_i(void);
+void m68k_op_add_16_er_d(void);
+void m68k_op_add_16_er_a(void);
+void m68k_op_add_16_er_ai(void);
+void m68k_op_add_16_er_pi(void);
+void m68k_op_add_16_er_pd(void);
+void m68k_op_add_16_er_di(void);
+void m68k_op_add_16_er_ix(void);
+void m68k_op_add_16_er_aw(void);
+void m68k_op_add_16_er_al(void);
+void m68k_op_add_16_er_pcdi(void);
+void m68k_op_add_16_er_pcix(void);
+void m68k_op_add_16_er_i(void);
+void m68k_op_add_32_er_d(void);
+void m68k_op_add_32_er_a(void);
+void m68k_op_add_32_er_ai(void);
+void m68k_op_add_32_er_pi(void);
+void m68k_op_add_32_er_pd(void);
+void m68k_op_add_32_er_di(void);
+void m68k_op_add_32_er_ix(void);
+void m68k_op_add_32_er_aw(void);
+void m68k_op_add_32_er_al(void);
+void m68k_op_add_32_er_pcdi(void);
+void m68k_op_add_32_er_pcix(void);
+void m68k_op_add_32_er_i(void);
+void m68k_op_add_8_re_ai(void);
+void m68k_op_add_8_re_pi(void);
+void m68k_op_add_8_re_pi7(void);
+void m68k_op_add_8_re_pd(void);
+void m68k_op_add_8_re_pd7(void);
+void m68k_op_add_8_re_di(void);
+void m68k_op_add_8_re_ix(void);
+void m68k_op_add_8_re_aw(void);
+void m68k_op_add_8_re_al(void);
+void m68k_op_add_16_re_ai(void);
+void m68k_op_add_16_re_pi(void);
+void m68k_op_add_16_re_pd(void);
+void m68k_op_add_16_re_di(void);
+void m68k_op_add_16_re_ix(void);
+void m68k_op_add_16_re_aw(void);
+void m68k_op_add_16_re_al(void);
+void m68k_op_add_32_re_ai(void);
+void m68k_op_add_32_re_pi(void);
+void m68k_op_add_32_re_pd(void);
+void m68k_op_add_32_re_di(void);
+void m68k_op_add_32_re_ix(void);
+void m68k_op_add_32_re_aw(void);
+void m68k_op_add_32_re_al(void);
+void m68k_op_adda_16_d(void);
+void m68k_op_adda_16_a(void);
+void m68k_op_adda_16_ai(void);
+void m68k_op_adda_16_pi(void);
+void m68k_op_adda_16_pd(void);
+void m68k_op_adda_16_di(void);
+void m68k_op_adda_16_ix(void);
+void m68k_op_adda_16_aw(void);
+void m68k_op_adda_16_al(void);
+void m68k_op_adda_16_pcdi(void);
+void m68k_op_adda_16_pcix(void);
+void m68k_op_adda_16_i(void);
+void m68k_op_adda_32_d(void);
+void m68k_op_adda_32_a(void);
+void m68k_op_adda_32_ai(void);
+void m68k_op_adda_32_pi(void);
+void m68k_op_adda_32_pd(void);
+void m68k_op_adda_32_di(void);
+void m68k_op_adda_32_ix(void);
+void m68k_op_adda_32_aw(void);
+void m68k_op_adda_32_al(void);
+void m68k_op_adda_32_pcdi(void);
+void m68k_op_adda_32_pcix(void);
+void m68k_op_adda_32_i(void);
+void m68k_op_addi_8_d(void);
+void m68k_op_addi_8_ai(void);
+void m68k_op_addi_8_pi(void);
+void m68k_op_addi_8_pi7(void);
+void m68k_op_addi_8_pd(void);
+void m68k_op_addi_8_pd7(void);
+void m68k_op_addi_8_di(void);
+void m68k_op_addi_8_ix(void);
+void m68k_op_addi_8_aw(void);
+void m68k_op_addi_8_al(void);
+void m68k_op_addi_16_d(void);
+void m68k_op_addi_16_ai(void);
+void m68k_op_addi_16_pi(void);
+void m68k_op_addi_16_pd(void);
+void m68k_op_addi_16_di(void);
+void m68k_op_addi_16_ix(void);
+void m68k_op_addi_16_aw(void);
+void m68k_op_addi_16_al(void);
+void m68k_op_addi_32_d(void);
+void m68k_op_addi_32_ai(void);
+void m68k_op_addi_32_pi(void);
+void m68k_op_addi_32_pd(void);
+void m68k_op_addi_32_di(void);
+void m68k_op_addi_32_ix(void);
+void m68k_op_addi_32_aw(void);
+void m68k_op_addi_32_al(void);
+void m68k_op_addq_8_d(void);
+void m68k_op_addq_8_ai(void);
+void m68k_op_addq_8_pi(void);
+void m68k_op_addq_8_pi7(void);
+void m68k_op_addq_8_pd(void);
+void m68k_op_addq_8_pd7(void);
+void m68k_op_addq_8_di(void);
+void m68k_op_addq_8_ix(void);
+void m68k_op_addq_8_aw(void);
+void m68k_op_addq_8_al(void);
+void m68k_op_addq_16_d(void);
+void m68k_op_addq_16_a(void);
+void m68k_op_addq_16_ai(void);
+void m68k_op_addq_16_pi(void);
+void m68k_op_addq_16_pd(void);
+void m68k_op_addq_16_di(void);
+void m68k_op_addq_16_ix(void);
+void m68k_op_addq_16_aw(void);
+void m68k_op_addq_16_al(void);
+void m68k_op_addq_32_d(void);
+void m68k_op_addq_32_a(void);
+void m68k_op_addq_32_ai(void);
+void m68k_op_addq_32_pi(void);
+void m68k_op_addq_32_pd(void);
+void m68k_op_addq_32_di(void);
+void m68k_op_addq_32_ix(void);
+void m68k_op_addq_32_aw(void);
+void m68k_op_addq_32_al(void);
+void m68k_op_addx_8_rr(void);
+void m68k_op_addx_16_rr(void);
+void m68k_op_addx_32_rr(void);
+void m68k_op_addx_8_mm_ax7(void);
+void m68k_op_addx_8_mm_ay7(void);
+void m68k_op_addx_8_mm_axy7(void);
+void m68k_op_addx_8_mm(void);
+void m68k_op_addx_16_mm(void);
+void m68k_op_addx_32_mm(void);
+void m68k_op_and_8_er_d(void);
+void m68k_op_and_8_er_ai(void);
+void m68k_op_and_8_er_pi(void);
+void m68k_op_and_8_er_pi7(void);
+void m68k_op_and_8_er_pd(void);
+void m68k_op_and_8_er_pd7(void);
+void m68k_op_and_8_er_di(void);
+void m68k_op_and_8_er_ix(void);
+void m68k_op_and_8_er_aw(void);
+void m68k_op_and_8_er_al(void);
+void m68k_op_and_8_er_pcdi(void);
+void m68k_op_and_8_er_pcix(void);
+void m68k_op_and_8_er_i(void);
+void m68k_op_and_16_er_d(void);
+void m68k_op_and_16_er_ai(void);
+void m68k_op_and_16_er_pi(void);
+void m68k_op_and_16_er_pd(void);
+void m68k_op_and_16_er_di(void);
+void m68k_op_and_16_er_ix(void);
+void m68k_op_and_16_er_aw(void);
+void m68k_op_and_16_er_al(void);
+void m68k_op_and_16_er_pcdi(void);
+void m68k_op_and_16_er_pcix(void);
+void m68k_op_and_16_er_i(void);
+void m68k_op_and_32_er_d(void);
+void m68k_op_and_32_er_ai(void);
+void m68k_op_and_32_er_pi(void);
+void m68k_op_and_32_er_pd(void);
+void m68k_op_and_32_er_di(void);
+void m68k_op_and_32_er_ix(void);
+void m68k_op_and_32_er_aw(void);
+void m68k_op_and_32_er_al(void);
+void m68k_op_and_32_er_pcdi(void);
+void m68k_op_and_32_er_pcix(void);
+void m68k_op_and_32_er_i(void);
+void m68k_op_and_8_re_ai(void);
+void m68k_op_and_8_re_pi(void);
+void m68k_op_and_8_re_pi7(void);
+void m68k_op_and_8_re_pd(void);
+void m68k_op_and_8_re_pd7(void);
+void m68k_op_and_8_re_di(void);
+void m68k_op_and_8_re_ix(void);
+void m68k_op_and_8_re_aw(void);
+void m68k_op_and_8_re_al(void);
+void m68k_op_and_16_re_ai(void);
+void m68k_op_and_16_re_pi(void);
+void m68k_op_and_16_re_pd(void);
+void m68k_op_and_16_re_di(void);
+void m68k_op_and_16_re_ix(void);
+void m68k_op_and_16_re_aw(void);
+void m68k_op_and_16_re_al(void);
+void m68k_op_and_32_re_ai(void);
+void m68k_op_and_32_re_pi(void);
+void m68k_op_and_32_re_pd(void);
+void m68k_op_and_32_re_di(void);
+void m68k_op_and_32_re_ix(void);
+void m68k_op_and_32_re_aw(void);
+void m68k_op_and_32_re_al(void);
+void m68k_op_andi_8_d(void);
+void m68k_op_andi_8_ai(void);
+void m68k_op_andi_8_pi(void);
+void m68k_op_andi_8_pi7(void);
+void m68k_op_andi_8_pd(void);
+void m68k_op_andi_8_pd7(void);
+void m68k_op_andi_8_di(void);
+void m68k_op_andi_8_ix(void);
+void m68k_op_andi_8_aw(void);
+void m68k_op_andi_8_al(void);
+void m68k_op_andi_16_d(void);
+void m68k_op_andi_16_ai(void);
+void m68k_op_andi_16_pi(void);
+void m68k_op_andi_16_pd(void);
+void m68k_op_andi_16_di(void);
+void m68k_op_andi_16_ix(void);
+void m68k_op_andi_16_aw(void);
+void m68k_op_andi_16_al(void);
+void m68k_op_andi_32_d(void);
+void m68k_op_andi_32_ai(void);
+void m68k_op_andi_32_pi(void);
+void m68k_op_andi_32_pd(void);
+void m68k_op_andi_32_di(void);
+void m68k_op_andi_32_ix(void);
+void m68k_op_andi_32_aw(void);
+void m68k_op_andi_32_al(void);
+void m68k_op_andi_16_toc(void);
+void m68k_op_andi_16_tos(void);
+void m68k_op_asr_8_s(void);
+void m68k_op_asr_16_s(void);
+void m68k_op_asr_32_s(void);
+void m68k_op_asr_8_r(void);
+void m68k_op_asr_16_r(void);
+void m68k_op_asr_32_r(void);
+void m68k_op_asr_16_ai(void);
+void m68k_op_asr_16_pi(void);
+void m68k_op_asr_16_pd(void);
+void m68k_op_asr_16_di(void);
+void m68k_op_asr_16_ix(void);
+void m68k_op_asr_16_aw(void);
+void m68k_op_asr_16_al(void);
+void m68k_op_asl_8_s(void);
+void m68k_op_asl_16_s(void);
+void m68k_op_asl_32_s(void);
+void m68k_op_asl_8_r(void);
+void m68k_op_asl_16_r(void);
+void m68k_op_asl_32_r(void);
+void m68k_op_asl_16_ai(void);
+void m68k_op_asl_16_pi(void);
+void m68k_op_asl_16_pd(void);
+void m68k_op_asl_16_di(void);
+void m68k_op_asl_16_ix(void);
+void m68k_op_asl_16_aw(void);
+void m68k_op_asl_16_al(void);
+void m68k_op_bhi_8(void);
+void m68k_op_bls_8(void);
+void m68k_op_bcc_8(void);
+void m68k_op_bcs_8(void);
+void m68k_op_bne_8(void);
+void m68k_op_beq_8(void);
+void m68k_op_bvc_8(void);
+void m68k_op_bvs_8(void);
+void m68k_op_bpl_8(void);
+void m68k_op_bmi_8(void);
+void m68k_op_bge_8(void);
+void m68k_op_blt_8(void);
+void m68k_op_bgt_8(void);
+void m68k_op_ble_8(void);
+void m68k_op_bhi_16(void);
+void m68k_op_bls_16(void);
+void m68k_op_bcc_16(void);
+void m68k_op_bcs_16(void);
+void m68k_op_bne_16(void);
+void m68k_op_beq_16(void);
+void m68k_op_bvc_16(void);
+void m68k_op_bvs_16(void);
+void m68k_op_bpl_16(void);
+void m68k_op_bmi_16(void);
+void m68k_op_bge_16(void);
+void m68k_op_blt_16(void);
+void m68k_op_bgt_16(void);
+void m68k_op_ble_16(void);
+void m68k_op_bhi_32(void);
+void m68k_op_bls_32(void);
+void m68k_op_bcc_32(void);
+void m68k_op_bcs_32(void);
+void m68k_op_bne_32(void);
+void m68k_op_beq_32(void);
+void m68k_op_bvc_32(void);
+void m68k_op_bvs_32(void);
+void m68k_op_bpl_32(void);
+void m68k_op_bmi_32(void);
+void m68k_op_bge_32(void);
+void m68k_op_blt_32(void);
+void m68k_op_bgt_32(void);
+void m68k_op_ble_32(void);
+void m68k_op_bchg_32_r_d(void);
+void m68k_op_bchg_8_r_ai(void);
+void m68k_op_bchg_8_r_pi(void);
+void m68k_op_bchg_8_r_pi7(void);
+void m68k_op_bchg_8_r_pd(void);
+void m68k_op_bchg_8_r_pd7(void);
+void m68k_op_bchg_8_r_di(void);
+void m68k_op_bchg_8_r_ix(void);
+void m68k_op_bchg_8_r_aw(void);
+void m68k_op_bchg_8_r_al(void);
+void m68k_op_bchg_32_s_d(void);
+void m68k_op_bchg_8_s_ai(void);
+void m68k_op_bchg_8_s_pi(void);
+void m68k_op_bchg_8_s_pi7(void);
+void m68k_op_bchg_8_s_pd(void);
+void m68k_op_bchg_8_s_pd7(void);
+void m68k_op_bchg_8_s_di(void);
+void m68k_op_bchg_8_s_ix(void);
+void m68k_op_bchg_8_s_aw(void);
+void m68k_op_bchg_8_s_al(void);
+void m68k_op_bclr_32_r_d(void);
+void m68k_op_bclr_8_r_ai(void);
+void m68k_op_bclr_8_r_pi(void);
+void m68k_op_bclr_8_r_pi7(void);
+void m68k_op_bclr_8_r_pd(void);
+void m68k_op_bclr_8_r_pd7(void);
+void m68k_op_bclr_8_r_di(void);
+void m68k_op_bclr_8_r_ix(void);
+void m68k_op_bclr_8_r_aw(void);
+void m68k_op_bclr_8_r_al(void);
+void m68k_op_bclr_32_s_d(void);
+void m68k_op_bclr_8_s_ai(void);
+void m68k_op_bclr_8_s_pi(void);
+void m68k_op_bclr_8_s_pi7(void);
+void m68k_op_bclr_8_s_pd(void);
+void m68k_op_bclr_8_s_pd7(void);
+void m68k_op_bclr_8_s_di(void);
+void m68k_op_bclr_8_s_ix(void);
+void m68k_op_bclr_8_s_aw(void);
+void m68k_op_bclr_8_s_al(void);
+void m68k_op_bfchg_32_d(void);
+void m68k_op_bfchg_32_ai(void);
+void m68k_op_bfchg_32_di(void);
+void m68k_op_bfchg_32_ix(void);
+void m68k_op_bfchg_32_aw(void);
+void m68k_op_bfchg_32_al(void);
+void m68k_op_bfclr_32_d(void);
+void m68k_op_bfclr_32_ai(void);
+void m68k_op_bfclr_32_di(void);
+void m68k_op_bfclr_32_ix(void);
+void m68k_op_bfclr_32_aw(void);
+void m68k_op_bfclr_32_al(void);
+void m68k_op_bfexts_32_d(void);
+void m68k_op_bfexts_32_ai(void);
+void m68k_op_bfexts_32_di(void);
+void m68k_op_bfexts_32_ix(void);
+void m68k_op_bfexts_32_aw(void);
+void m68k_op_bfexts_32_al(void);
+void m68k_op_bfexts_32_pcdi(void);
+void m68k_op_bfexts_32_pcix(void);
+void m68k_op_bfextu_32_d(void);
+void m68k_op_bfextu_32_ai(void);
+void m68k_op_bfextu_32_di(void);
+void m68k_op_bfextu_32_ix(void);
+void m68k_op_bfextu_32_aw(void);
+void m68k_op_bfextu_32_al(void);
+void m68k_op_bfextu_32_pcdi(void);
+void m68k_op_bfextu_32_pcix(void);
+void m68k_op_bfffo_32_d(void);
+void m68k_op_bfffo_32_ai(void);
+void m68k_op_bfffo_32_di(void);
+void m68k_op_bfffo_32_ix(void);
+void m68k_op_bfffo_32_aw(void);
+void m68k_op_bfffo_32_al(void);
+void m68k_op_bfffo_32_pcdi(void);
+void m68k_op_bfffo_32_pcix(void);
+void m68k_op_bfins_32_d(void);
+void m68k_op_bfins_32_ai(void);
+void m68k_op_bfins_32_di(void);
+void m68k_op_bfins_32_ix(void);
+void m68k_op_bfins_32_aw(void);
+void m68k_op_bfins_32_al(void);
+void m68k_op_bfset_32_d(void);
+void m68k_op_bfset_32_ai(void);
+void m68k_op_bfset_32_di(void);
+void m68k_op_bfset_32_ix(void);
+void m68k_op_bfset_32_aw(void);
+void m68k_op_bfset_32_al(void);
+void m68k_op_bftst_32_d(void);
+void m68k_op_bftst_32_ai(void);
+void m68k_op_bftst_32_di(void);
+void m68k_op_bftst_32_ix(void);
+void m68k_op_bftst_32_aw(void);
+void m68k_op_bftst_32_al(void);
+void m68k_op_bftst_32_pcdi(void);
+void m68k_op_bftst_32_pcix(void);
+void m68k_op_bkpt(void);
+void m68k_op_bra_8(void);
+void m68k_op_bra_16(void);
+void m68k_op_bra_32(void);
+void m68k_op_bset_32_r_d(void);
+void m68k_op_bset_8_r_ai(void);
+void m68k_op_bset_8_r_pi(void);
+void m68k_op_bset_8_r_pi7(void);
+void m68k_op_bset_8_r_pd(void);
+void m68k_op_bset_8_r_pd7(void);
+void m68k_op_bset_8_r_di(void);
+void m68k_op_bset_8_r_ix(void);
+void m68k_op_bset_8_r_aw(void);
+void m68k_op_bset_8_r_al(void);
+void m68k_op_bset_32_s_d(void);
+void m68k_op_bset_8_s_ai(void);
+void m68k_op_bset_8_s_pi(void);
+void m68k_op_bset_8_s_pi7(void);
+void m68k_op_bset_8_s_pd(void);
+void m68k_op_bset_8_s_pd7(void);
+void m68k_op_bset_8_s_di(void);
+void m68k_op_bset_8_s_ix(void);
+void m68k_op_bset_8_s_aw(void);
+void m68k_op_bset_8_s_al(void);
+void m68k_op_bsr_8(void);
+void m68k_op_bsr_16(void);
+void m68k_op_bsr_32(void);
+void m68k_op_btst_32_r_d(void);
+void m68k_op_btst_8_r_ai(void);
+void m68k_op_btst_8_r_pi(void);
+void m68k_op_btst_8_r_pi7(void);
+void m68k_op_btst_8_r_pd(void);
+void m68k_op_btst_8_r_pd7(void);
+void m68k_op_btst_8_r_di(void);
+void m68k_op_btst_8_r_ix(void);
+void m68k_op_btst_8_r_aw(void);
+void m68k_op_btst_8_r_al(void);
+void m68k_op_btst_8_r_pcdi(void);
+void m68k_op_btst_8_r_pcix(void);
+void m68k_op_btst_8_r_i(void);
+void m68k_op_btst_32_s_d(void);
+void m68k_op_btst_8_s_ai(void);
+void m68k_op_btst_8_s_pi(void);
+void m68k_op_btst_8_s_pi7(void);
+void m68k_op_btst_8_s_pd(void);
+void m68k_op_btst_8_s_pd7(void);
+void m68k_op_btst_8_s_di(void);
+void m68k_op_btst_8_s_ix(void);
+void m68k_op_btst_8_s_aw(void);
+void m68k_op_btst_8_s_al(void);
+void m68k_op_btst_8_s_pcdi(void);
+void m68k_op_btst_8_s_pcix(void);
+void m68k_op_callm_32_ai(void);
+void m68k_op_callm_32_di(void);
+void m68k_op_callm_32_ix(void);
+void m68k_op_callm_32_aw(void);
+void m68k_op_callm_32_al(void);
+void m68k_op_callm_32_pcdi(void);
+void m68k_op_callm_32_pcix(void);
+void m68k_op_cas_8_ai(void);
+void m68k_op_cas_8_pi(void);
+void m68k_op_cas_8_pi7(void);
+void m68k_op_cas_8_pd(void);
+void m68k_op_cas_8_pd7(void);
+void m68k_op_cas_8_di(void);
+void m68k_op_cas_8_ix(void);
+void m68k_op_cas_8_aw(void);
+void m68k_op_cas_8_al(void);
+void m68k_op_cas_16_ai(void);
+void m68k_op_cas_16_pi(void);
+void m68k_op_cas_16_pd(void);
+void m68k_op_cas_16_di(void);
+void m68k_op_cas_16_ix(void);
+void m68k_op_cas_16_aw(void);
+void m68k_op_cas_16_al(void);
+void m68k_op_cas_32_ai(void);
+void m68k_op_cas_32_pi(void);
+void m68k_op_cas_32_pd(void);
+void m68k_op_cas_32_di(void);
+void m68k_op_cas_32_ix(void);
+void m68k_op_cas_32_aw(void);
+void m68k_op_cas_32_al(void);
+void m68k_op_cas2_16(void);
+void m68k_op_cas2_32(void);
+void m68k_op_chk_16_d(void);
+void m68k_op_chk_16_ai(void);
+void m68k_op_chk_16_pi(void);
+void m68k_op_chk_16_pd(void);
+void m68k_op_chk_16_di(void);
+void m68k_op_chk_16_ix(void);
+void m68k_op_chk_16_aw(void);
+void m68k_op_chk_16_al(void);
+void m68k_op_chk_16_pcdi(void);
+void m68k_op_chk_16_pcix(void);
+void m68k_op_chk_16_i(void);
+void m68k_op_chk_32_d(void);
+void m68k_op_chk_32_ai(void);
+void m68k_op_chk_32_pi(void);
+void m68k_op_chk_32_pd(void);
+void m68k_op_chk_32_di(void);
+void m68k_op_chk_32_ix(void);
+void m68k_op_chk_32_aw(void);
+void m68k_op_chk_32_al(void);
+void m68k_op_chk_32_pcdi(void);
+void m68k_op_chk_32_pcix(void);
+void m68k_op_chk_32_i(void);
+void m68k_op_chk2cmp2_8_pcdi(void);
+void m68k_op_chk2cmp2_8_pcix(void);
+void m68k_op_chk2cmp2_8_ai(void);
+void m68k_op_chk2cmp2_8_di(void);
+void m68k_op_chk2cmp2_8_ix(void);
+void m68k_op_chk2cmp2_8_aw(void);
+void m68k_op_chk2cmp2_8_al(void);
+void m68k_op_chk2cmp2_16_pcdi(void);
+void m68k_op_chk2cmp2_16_pcix(void);
+void m68k_op_chk2cmp2_16_ai(void);
+void m68k_op_chk2cmp2_16_di(void);
+void m68k_op_chk2cmp2_16_ix(void);
+void m68k_op_chk2cmp2_16_aw(void);
+void m68k_op_chk2cmp2_16_al(void);
+void m68k_op_chk2cmp2_32_pcdi(void);
+void m68k_op_chk2cmp2_32_pcix(void);
+void m68k_op_chk2cmp2_32_ai(void);
+void m68k_op_chk2cmp2_32_di(void);
+void m68k_op_chk2cmp2_32_ix(void);
+void m68k_op_chk2cmp2_32_aw(void);
+void m68k_op_chk2cmp2_32_al(void);
+void m68k_op_clr_8_d(void);
+void m68k_op_clr_8_ai(void);
+void m68k_op_clr_8_pi(void);
+void m68k_op_clr_8_pi7(void);
+void m68k_op_clr_8_pd(void);
+void m68k_op_clr_8_pd7(void);
+void m68k_op_clr_8_di(void);
+void m68k_op_clr_8_ix(void);
+void m68k_op_clr_8_aw(void);
+void m68k_op_clr_8_al(void);
+void m68k_op_clr_16_d(void);
+void m68k_op_clr_16_ai(void);
+void m68k_op_clr_16_pi(void);
+void m68k_op_clr_16_pd(void);
+void m68k_op_clr_16_di(void);
+void m68k_op_clr_16_ix(void);
+void m68k_op_clr_16_aw(void);
+void m68k_op_clr_16_al(void);
+void m68k_op_clr_32_d(void);
+void m68k_op_clr_32_ai(void);
+void m68k_op_clr_32_pi(void);
+void m68k_op_clr_32_pd(void);
+void m68k_op_clr_32_di(void);
+void m68k_op_clr_32_ix(void);
+void m68k_op_clr_32_aw(void);
+void m68k_op_clr_32_al(void);
+void m68k_op_cmp_8_d(void);
+void m68k_op_cmp_8_ai(void);
+void m68k_op_cmp_8_pi(void);
+void m68k_op_cmp_8_pi7(void);
+void m68k_op_cmp_8_pd(void);
+void m68k_op_cmp_8_pd7(void);
+void m68k_op_cmp_8_di(void);
+void m68k_op_cmp_8_ix(void);
+void m68k_op_cmp_8_aw(void);
+void m68k_op_cmp_8_al(void);
+void m68k_op_cmp_8_pcdi(void);
+void m68k_op_cmp_8_pcix(void);
+void m68k_op_cmp_8_i(void);
+void m68k_op_cmp_16_d(void);
+void m68k_op_cmp_16_a(void);
+void m68k_op_cmp_16_ai(void);
+void m68k_op_cmp_16_pi(void);
+void m68k_op_cmp_16_pd(void);
+void m68k_op_cmp_16_di(void);
+void m68k_op_cmp_16_ix(void);
+void m68k_op_cmp_16_aw(void);
+void m68k_op_cmp_16_al(void);
+void m68k_op_cmp_16_pcdi(void);
+void m68k_op_cmp_16_pcix(void);
+void m68k_op_cmp_16_i(void);
+void m68k_op_cmp_32_d(void);
+void m68k_op_cmp_32_a(void);
+void m68k_op_cmp_32_ai(void);
+void m68k_op_cmp_32_pi(void);
+void m68k_op_cmp_32_pd(void);
+void m68k_op_cmp_32_di(void);
+void m68k_op_cmp_32_ix(void);
+void m68k_op_cmp_32_aw(void);
+void m68k_op_cmp_32_al(void);
+void m68k_op_cmp_32_pcdi(void);
+void m68k_op_cmp_32_pcix(void);
+void m68k_op_cmp_32_i(void);
+void m68k_op_cmpa_16_d(void);
+void m68k_op_cmpa_16_a(void);
+void m68k_op_cmpa_16_ai(void);
+void m68k_op_cmpa_16_pi(void);
+void m68k_op_cmpa_16_pd(void);
+void m68k_op_cmpa_16_di(void);
+void m68k_op_cmpa_16_ix(void);
+void m68k_op_cmpa_16_aw(void);
+void m68k_op_cmpa_16_al(void);
+void m68k_op_cmpa_16_pcdi(void);
+void m68k_op_cmpa_16_pcix(void);
+void m68k_op_cmpa_16_i(void);
+void m68k_op_cmpa_32_d(void);
+void m68k_op_cmpa_32_a(void);
+void m68k_op_cmpa_32_ai(void);
+void m68k_op_cmpa_32_pi(void);
+void m68k_op_cmpa_32_pd(void);
+void m68k_op_cmpa_32_di(void);
+void m68k_op_cmpa_32_ix(void);
+void m68k_op_cmpa_32_aw(void);
+void m68k_op_cmpa_32_al(void);
+void m68k_op_cmpa_32_pcdi(void);
+void m68k_op_cmpa_32_pcix(void);
+void m68k_op_cmpa_32_i(void);
+void m68k_op_cmpi_8_d(void);
+void m68k_op_cmpi_8_ai(void);
+void m68k_op_cmpi_8_pi(void);
+void m68k_op_cmpi_8_pi7(void);
+void m68k_op_cmpi_8_pd(void);
+void m68k_op_cmpi_8_pd7(void);
+void m68k_op_cmpi_8_di(void);
+void m68k_op_cmpi_8_ix(void);
+void m68k_op_cmpi_8_aw(void);
+void m68k_op_cmpi_8_al(void);
+void m68k_op_cmpi_8_pcdi(void);
+void m68k_op_cmpi_8_pcix(void);
+void m68k_op_cmpi_16_d(void);
+void m68k_op_cmpi_16_ai(void);
+void m68k_op_cmpi_16_pi(void);
+void m68k_op_cmpi_16_pd(void);
+void m68k_op_cmpi_16_di(void);
+void m68k_op_cmpi_16_ix(void);
+void m68k_op_cmpi_16_aw(void);
+void m68k_op_cmpi_16_al(void);
+void m68k_op_cmpi_16_pcdi(void);
+void m68k_op_cmpi_16_pcix(void);
+void m68k_op_cmpi_32_d(void);
+void m68k_op_cmpi_32_ai(void);
+void m68k_op_cmpi_32_pi(void);
+void m68k_op_cmpi_32_pd(void);
+void m68k_op_cmpi_32_di(void);
+void m68k_op_cmpi_32_ix(void);
+void m68k_op_cmpi_32_aw(void);
+void m68k_op_cmpi_32_al(void);
+void m68k_op_cmpi_32_pcdi(void);
+void m68k_op_cmpi_32_pcix(void);
+void m68k_op_cmpm_8_ax7(void);
+void m68k_op_cmpm_8_ay7(void);
+void m68k_op_cmpm_8_axy7(void);
+void m68k_op_cmpm_8(void);
+void m68k_op_cmpm_16(void);
+void m68k_op_cmpm_32(void);
+void m68k_op_cpbcc_32(void);
+void m68k_op_cpdbcc_32(void);
+void m68k_op_cpgen_32(void);
+void m68k_op_cpscc_32(void);
+void m68k_op_cptrapcc_32(void);
+void m68k_op_dbt_16(void);
+void m68k_op_dbf_16(void);
+void m68k_op_dbhi_16(void);
+void m68k_op_dbls_16(void);
+void m68k_op_dbcc_16(void);
+void m68k_op_dbcs_16(void);
+void m68k_op_dbne_16(void);
+void m68k_op_dbeq_16(void);
+void m68k_op_dbvc_16(void);
+void m68k_op_dbvs_16(void);
+void m68k_op_dbpl_16(void);
+void m68k_op_dbmi_16(void);
+void m68k_op_dbge_16(void);
+void m68k_op_dblt_16(void);
+void m68k_op_dbgt_16(void);
+void m68k_op_dble_16(void);
+void m68k_op_divs_16_d(void);
+void m68k_op_divs_16_ai(void);
+void m68k_op_divs_16_pi(void);
+void m68k_op_divs_16_pd(void);
+void m68k_op_divs_16_di(void);
+void m68k_op_divs_16_ix(void);
+void m68k_op_divs_16_aw(void);
+void m68k_op_divs_16_al(void);
+void m68k_op_divs_16_pcdi(void);
+void m68k_op_divs_16_pcix(void);
+void m68k_op_divs_16_i(void);
+void m68k_op_divu_16_d(void);
+void m68k_op_divu_16_ai(void);
+void m68k_op_divu_16_pi(void);
+void m68k_op_divu_16_pd(void);
+void m68k_op_divu_16_di(void);
+void m68k_op_divu_16_ix(void);
+void m68k_op_divu_16_aw(void);
+void m68k_op_divu_16_al(void);
+void m68k_op_divu_16_pcdi(void);
+void m68k_op_divu_16_pcix(void);
+void m68k_op_divu_16_i(void);
+void m68k_op_divl_32_d(void);
+void m68k_op_divl_32_ai(void);
+void m68k_op_divl_32_pi(void);
+void m68k_op_divl_32_pd(void);
+void m68k_op_divl_32_di(void);
+void m68k_op_divl_32_ix(void);
+void m68k_op_divl_32_aw(void);
+void m68k_op_divl_32_al(void);
+void m68k_op_divl_32_pcdi(void);
+void m68k_op_divl_32_pcix(void);
+void m68k_op_divl_32_i(void);
+void m68k_op_eor_8_d(void);
+void m68k_op_eor_8_ai(void);
+void m68k_op_eor_8_pi(void);
+void m68k_op_eor_8_pi7(void);
+void m68k_op_eor_8_pd(void);
+void m68k_op_eor_8_pd7(void);
+void m68k_op_eor_8_di(void);
+void m68k_op_eor_8_ix(void);
+void m68k_op_eor_8_aw(void);
+void m68k_op_eor_8_al(void);
+void m68k_op_eor_16_d(void);
+void m68k_op_eor_16_ai(void);
+void m68k_op_eor_16_pi(void);
+void m68k_op_eor_16_pd(void);
+void m68k_op_eor_16_di(void);
+void m68k_op_eor_16_ix(void);
+void m68k_op_eor_16_aw(void);
+void m68k_op_eor_16_al(void);
+void m68k_op_eor_32_d(void);
+void m68k_op_eor_32_ai(void);
+void m68k_op_eor_32_pi(void);
+void m68k_op_eor_32_pd(void);
+void m68k_op_eor_32_di(void);
+void m68k_op_eor_32_ix(void);
+void m68k_op_eor_32_aw(void);
+void m68k_op_eor_32_al(void);
+void m68k_op_eori_8_d(void);
+void m68k_op_eori_8_ai(void);
+void m68k_op_eori_8_pi(void);
+void m68k_op_eori_8_pi7(void);
+void m68k_op_eori_8_pd(void);
+void m68k_op_eori_8_pd7(void);
+void m68k_op_eori_8_di(void);
+void m68k_op_eori_8_ix(void);
+void m68k_op_eori_8_aw(void);
+void m68k_op_eori_8_al(void);
+void m68k_op_eori_16_d(void);
+void m68k_op_eori_16_ai(void);
+void m68k_op_eori_16_pi(void);
+void m68k_op_eori_16_pd(void);
+void m68k_op_eori_16_di(void);
+void m68k_op_eori_16_ix(void);
+void m68k_op_eori_16_aw(void);
+void m68k_op_eori_16_al(void);
+void m68k_op_eori_32_d(void);
+void m68k_op_eori_32_ai(void);
+void m68k_op_eori_32_pi(void);
+void m68k_op_eori_32_pd(void);
+void m68k_op_eori_32_di(void);
+void m68k_op_eori_32_ix(void);
+void m68k_op_eori_32_aw(void);
+void m68k_op_eori_32_al(void);
+void m68k_op_eori_16_toc(void);
+void m68k_op_eori_16_tos(void);
+void m68k_op_exg_32_dd(void);
+void m68k_op_exg_32_aa(void);
+void m68k_op_exg_32_da(void);
+void m68k_op_ext_16(void);
+void m68k_op_ext_32(void);
+void m68k_op_extb_32(void);
+void m68k_op_illegal(void);
+void m68k_op_jmp_32_ai(void);
+void m68k_op_jmp_32_di(void);
+void m68k_op_jmp_32_ix(void);
+void m68k_op_jmp_32_aw(void);
+void m68k_op_jmp_32_al(void);
+void m68k_op_jmp_32_pcdi(void);
+void m68k_op_jmp_32_pcix(void);
+void m68k_op_jsr_32_ai(void);
+void m68k_op_jsr_32_di(void);
+void m68k_op_jsr_32_ix(void);
+void m68k_op_jsr_32_aw(void);
+void m68k_op_jsr_32_al(void);
+void m68k_op_jsr_32_pcdi(void);
+void m68k_op_jsr_32_pcix(void);
+void m68k_op_lea_32_ai(void);
+void m68k_op_lea_32_di(void);
+void m68k_op_lea_32_ix(void);
+void m68k_op_lea_32_aw(void);
+void m68k_op_lea_32_al(void);
+void m68k_op_lea_32_pcdi(void);
+void m68k_op_lea_32_pcix(void);
+void m68k_op_link_16_a7(void);
+void m68k_op_link_16(void);
+void m68k_op_link_32_a7(void);
+void m68k_op_link_32(void);
+void m68k_op_lsr_8_s(void);
+void m68k_op_lsr_16_s(void);
+void m68k_op_lsr_32_s(void);
+void m68k_op_lsr_8_r(void);
+void m68k_op_lsr_16_r(void);
+void m68k_op_lsr_32_r(void);
+void m68k_op_lsr_16_ai(void);
+void m68k_op_lsr_16_pi(void);
+void m68k_op_lsr_16_pd(void);
+void m68k_op_lsr_16_di(void);
+void m68k_op_lsr_16_ix(void);
+void m68k_op_lsr_16_aw(void);
+void m68k_op_lsr_16_al(void);
+void m68k_op_lsl_8_s(void);
+void m68k_op_lsl_16_s(void);
+void m68k_op_lsl_32_s(void);
+void m68k_op_lsl_8_r(void);
+void m68k_op_lsl_16_r(void);
+void m68k_op_lsl_32_r(void);
+void m68k_op_lsl_16_ai(void);
+void m68k_op_lsl_16_pi(void);
+void m68k_op_lsl_16_pd(void);
+void m68k_op_lsl_16_di(void);
+void m68k_op_lsl_16_ix(void);
+void m68k_op_lsl_16_aw(void);
+void m68k_op_lsl_16_al(void);
+void m68k_op_move_8_d_d(void);
+void m68k_op_move_8_d_ai(void);
+void m68k_op_move_8_d_pi(void);
+void m68k_op_move_8_d_pi7(void);
+void m68k_op_move_8_d_pd(void);
+void m68k_op_move_8_d_pd7(void);
+void m68k_op_move_8_d_di(void);
+void m68k_op_move_8_d_ix(void);
+void m68k_op_move_8_d_aw(void);
+void m68k_op_move_8_d_al(void);
+void m68k_op_move_8_d_pcdi(void);
+void m68k_op_move_8_d_pcix(void);
+void m68k_op_move_8_d_i(void);
+void m68k_op_move_8_ai_d(void);
+void m68k_op_move_8_ai_ai(void);
+void m68k_op_move_8_ai_pi(void);
+void m68k_op_move_8_ai_pi7(void);
+void m68k_op_move_8_ai_pd(void);
+void m68k_op_move_8_ai_pd7(void);
+void m68k_op_move_8_ai_di(void);
+void m68k_op_move_8_ai_ix(void);
+void m68k_op_move_8_ai_aw(void);
+void m68k_op_move_8_ai_al(void);
+void m68k_op_move_8_ai_pcdi(void);
+void m68k_op_move_8_ai_pcix(void);
+void m68k_op_move_8_ai_i(void);
+void m68k_op_move_8_pi7_d(void);
+void m68k_op_move_8_pi_d(void);
+void m68k_op_move_8_pi7_ai(void);
+void m68k_op_move_8_pi7_pi(void);
+void m68k_op_move_8_pi7_pi7(void);
+void m68k_op_move_8_pi7_pd(void);
+void m68k_op_move_8_pi7_pd7(void);
+void m68k_op_move_8_pi7_di(void);
+void m68k_op_move_8_pi7_ix(void);
+void m68k_op_move_8_pi7_aw(void);
+void m68k_op_move_8_pi7_al(void);
+void m68k_op_move_8_pi7_pcdi(void);
+void m68k_op_move_8_pi7_pcix(void);
+void m68k_op_move_8_pi7_i(void);
+void m68k_op_move_8_pi_ai(void);
+void m68k_op_move_8_pi_pi(void);
+void m68k_op_move_8_pi_pi7(void);
+void m68k_op_move_8_pi_pd(void);
+void m68k_op_move_8_pi_pd7(void);
+void m68k_op_move_8_pi_di(void);
+void m68k_op_move_8_pi_ix(void);
+void m68k_op_move_8_pi_aw(void);
+void m68k_op_move_8_pi_al(void);
+void m68k_op_move_8_pi_pcdi(void);
+void m68k_op_move_8_pi_pcix(void);
+void m68k_op_move_8_pi_i(void);
+void m68k_op_move_8_pd7_d(void);
+void m68k_op_move_8_pd_d(void);
+void m68k_op_move_8_pd7_ai(void);
+void m68k_op_move_8_pd7_pi(void);
+void m68k_op_move_8_pd7_pi7(void);
+void m68k_op_move_8_pd7_pd(void);
+void m68k_op_move_8_pd7_pd7(void);
+void m68k_op_move_8_pd7_di(void);
+void m68k_op_move_8_pd7_ix(void);
+void m68k_op_move_8_pd7_aw(void);
+void m68k_op_move_8_pd7_al(void);
+void m68k_op_move_8_pd7_pcdi(void);
+void m68k_op_move_8_pd7_pcix(void);
+void m68k_op_move_8_pd7_i(void);
+void m68k_op_move_8_pd_ai(void);
+void m68k_op_move_8_pd_pi(void);
+void m68k_op_move_8_pd_pi7(void);
+void m68k_op_move_8_pd_pd(void);
+void m68k_op_move_8_pd_pd7(void);
+void m68k_op_move_8_pd_di(void);
+void m68k_op_move_8_pd_ix(void);
+void m68k_op_move_8_pd_aw(void);
+void m68k_op_move_8_pd_al(void);
+void m68k_op_move_8_pd_pcdi(void);
+void m68k_op_move_8_pd_pcix(void);
+void m68k_op_move_8_pd_i(void);
+void m68k_op_move_8_di_d(void);
+void m68k_op_move_8_di_ai(void);
+void m68k_op_move_8_di_pi(void);
+void m68k_op_move_8_di_pi7(void);
+void m68k_op_move_8_di_pd(void);
+void m68k_op_move_8_di_pd7(void);
+void m68k_op_move_8_di_di(void);
+void m68k_op_move_8_di_ix(void);
+void m68k_op_move_8_di_aw(void);
+void m68k_op_move_8_di_al(void);
+void m68k_op_move_8_di_pcdi(void);
+void m68k_op_move_8_di_pcix(void);
+void m68k_op_move_8_di_i(void);
+void m68k_op_move_8_ix_d(void);
+void m68k_op_move_8_ix_ai(void);
+void m68k_op_move_8_ix_pi(void);
+void m68k_op_move_8_ix_pi7(void);
+void m68k_op_move_8_ix_pd(void);
+void m68k_op_move_8_ix_pd7(void);
+void m68k_op_move_8_ix_di(void);
+void m68k_op_move_8_ix_ix(void);
+void m68k_op_move_8_ix_aw(void);
+void m68k_op_move_8_ix_al(void);
+void m68k_op_move_8_ix_pcdi(void);
+void m68k_op_move_8_ix_pcix(void);
+void m68k_op_move_8_ix_i(void);
+void m68k_op_move_8_aw_d(void);
+void m68k_op_move_8_aw_ai(void);
+void m68k_op_move_8_aw_pi(void);
+void m68k_op_move_8_aw_pi7(void);
+void m68k_op_move_8_aw_pd(void);
+void m68k_op_move_8_aw_pd7(void);
+void m68k_op_move_8_aw_di(void);
+void m68k_op_move_8_aw_ix(void);
+void m68k_op_move_8_aw_aw(void);
+void m68k_op_move_8_aw_al(void);
+void m68k_op_move_8_aw_pcdi(void);
+void m68k_op_move_8_aw_pcix(void);
+void m68k_op_move_8_aw_i(void);
+void m68k_op_move_8_al_d(void);
+void m68k_op_move_8_al_ai(void);
+void m68k_op_move_8_al_pi(void);
+void m68k_op_move_8_al_pi7(void);
+void m68k_op_move_8_al_pd(void);
+void m68k_op_move_8_al_pd7(void);
+void m68k_op_move_8_al_di(void);
+void m68k_op_move_8_al_ix(void);
+void m68k_op_move_8_al_aw(void);
+void m68k_op_move_8_al_al(void);
+void m68k_op_move_8_al_pcdi(void);
+void m68k_op_move_8_al_pcix(void);
+void m68k_op_move_8_al_i(void);
+void m68k_op_move_16_d_d(void);
+void m68k_op_move_16_d_a(void);
+void m68k_op_move_16_d_ai(void);
+void m68k_op_move_16_d_pi(void);
+void m68k_op_move_16_d_pd(void);
+void m68k_op_move_16_d_di(void);
+void m68k_op_move_16_d_ix(void);
+void m68k_op_move_16_d_aw(void);
+void m68k_op_move_16_d_al(void);
+void m68k_op_move_16_d_pcdi(void);
+void m68k_op_move_16_d_pcix(void);
+void m68k_op_move_16_d_i(void);
+void m68k_op_move_16_ai_d(void);
+void m68k_op_move_16_ai_a(void);
+void m68k_op_move_16_ai_ai(void);
+void m68k_op_move_16_ai_pi(void);
+void m68k_op_move_16_ai_pd(void);
+void m68k_op_move_16_ai_di(void);
+void m68k_op_move_16_ai_ix(void);
+void m68k_op_move_16_ai_aw(void);
+void m68k_op_move_16_ai_al(void);
+void m68k_op_move_16_ai_pcdi(void);
+void m68k_op_move_16_ai_pcix(void);
+void m68k_op_move_16_ai_i(void);
+void m68k_op_move_16_pi_d(void);
+void m68k_op_move_16_pi_a(void);
+void m68k_op_move_16_pi_ai(void);
+void m68k_op_move_16_pi_pi(void);
+void m68k_op_move_16_pi_pd(void);
+void m68k_op_move_16_pi_di(void);
+void m68k_op_move_16_pi_ix(void);
+void m68k_op_move_16_pi_aw(void);
+void m68k_op_move_16_pi_al(void);
+void m68k_op_move_16_pi_pcdi(void);
+void m68k_op_move_16_pi_pcix(void);
+void m68k_op_move_16_pi_i(void);
+void m68k_op_move_16_pd_d(void);
+void m68k_op_move_16_pd_a(void);
+void m68k_op_move_16_pd_ai(void);
+void m68k_op_move_16_pd_pi(void);
+void m68k_op_move_16_pd_pd(void);
+void m68k_op_move_16_pd_di(void);
+void m68k_op_move_16_pd_ix(void);
+void m68k_op_move_16_pd_aw(void);
+void m68k_op_move_16_pd_al(void);
+void m68k_op_move_16_pd_pcdi(void);
+void m68k_op_move_16_pd_pcix(void);
+void m68k_op_move_16_pd_i(void);
+void m68k_op_move_16_di_d(void);
+void m68k_op_move_16_di_a(void);
+void m68k_op_move_16_di_ai(void);
+void m68k_op_move_16_di_pi(void);
+void m68k_op_move_16_di_pd(void);
+void m68k_op_move_16_di_di(void);
+void m68k_op_move_16_di_ix(void);
+void m68k_op_move_16_di_aw(void);
+void m68k_op_move_16_di_al(void);
+void m68k_op_move_16_di_pcdi(void);
+void m68k_op_move_16_di_pcix(void);
+void m68k_op_move_16_di_i(void);
+void m68k_op_move_16_ix_d(void);
+void m68k_op_move_16_ix_a(void);
+void m68k_op_move_16_ix_ai(void);
+void m68k_op_move_16_ix_pi(void);
+void m68k_op_move_16_ix_pd(void);
+void m68k_op_move_16_ix_di(void);
+void m68k_op_move_16_ix_ix(void);
+void m68k_op_move_16_ix_aw(void);
+void m68k_op_move_16_ix_al(void);
+void m68k_op_move_16_ix_pcdi(void);
+void m68k_op_move_16_ix_pcix(void);
+void m68k_op_move_16_ix_i(void);
+void m68k_op_move_16_aw_d(void);
+void m68k_op_move_16_aw_a(void);
+void m68k_op_move_16_aw_ai(void);
+void m68k_op_move_16_aw_pi(void);
+void m68k_op_move_16_aw_pd(void);
+void m68k_op_move_16_aw_di(void);
+void m68k_op_move_16_aw_ix(void);
+void m68k_op_move_16_aw_aw(void);
+void m68k_op_move_16_aw_al(void);
+void m68k_op_move_16_aw_pcdi(void);
+void m68k_op_move_16_aw_pcix(void);
+void m68k_op_move_16_aw_i(void);
+void m68k_op_move_16_al_d(void);
+void m68k_op_move_16_al_a(void);
+void m68k_op_move_16_al_ai(void);
+void m68k_op_move_16_al_pi(void);
+void m68k_op_move_16_al_pd(void);
+void m68k_op_move_16_al_di(void);
+void m68k_op_move_16_al_ix(void);
+void m68k_op_move_16_al_aw(void);
+void m68k_op_move_16_al_al(void);
+void m68k_op_move_16_al_pcdi(void);
+void m68k_op_move_16_al_pcix(void);
+void m68k_op_move_16_al_i(void);
+void m68k_op_move_32_d_d(void);
+void m68k_op_move_32_d_a(void);
+void m68k_op_move_32_d_ai(void);
+void m68k_op_move_32_d_pi(void);
+void m68k_op_move_32_d_pd(void);
+void m68k_op_move_32_d_di(void);
+void m68k_op_move_32_d_ix(void);
+void m68k_op_move_32_d_aw(void);
+void m68k_op_move_32_d_al(void);
+void m68k_op_move_32_d_pcdi(void);
+void m68k_op_move_32_d_pcix(void);
+void m68k_op_move_32_d_i(void);
+void m68k_op_move_32_ai_d(void);
+void m68k_op_move_32_ai_a(void);
+void m68k_op_move_32_ai_ai(void);
+void m68k_op_move_32_ai_pi(void);
+void m68k_op_move_32_ai_pd(void);
+void m68k_op_move_32_ai_di(void);
+void m68k_op_move_32_ai_ix(void);
+void m68k_op_move_32_ai_aw(void);
+void m68k_op_move_32_ai_al(void);
+void m68k_op_move_32_ai_pcdi(void);
+void m68k_op_move_32_ai_pcix(void);
+void m68k_op_move_32_ai_i(void);
+void m68k_op_move_32_pi_d(void);
+void m68k_op_move_32_pi_a(void);
+void m68k_op_move_32_pi_ai(void);
+void m68k_op_move_32_pi_pi(void);
+void m68k_op_move_32_pi_pd(void);
+void m68k_op_move_32_pi_di(void);
+void m68k_op_move_32_pi_ix(void);
+void m68k_op_move_32_pi_aw(void);
+void m68k_op_move_32_pi_al(void);
+void m68k_op_move_32_pi_pcdi(void);
+void m68k_op_move_32_pi_pcix(void);
+void m68k_op_move_32_pi_i(void);
+void m68k_op_move_32_pd_d(void);
+void m68k_op_move_32_pd_a(void);
+void m68k_op_move_32_pd_ai(void);
+void m68k_op_move_32_pd_pi(void);
+void m68k_op_move_32_pd_pd(void);
+void m68k_op_move_32_pd_di(void);
+void m68k_op_move_32_pd_ix(void);
+void m68k_op_move_32_pd_aw(void);
+void m68k_op_move_32_pd_al(void);
+void m68k_op_move_32_pd_pcdi(void);
+void m68k_op_move_32_pd_pcix(void);
+void m68k_op_move_32_pd_i(void);
+void m68k_op_move_32_di_d(void);
+void m68k_op_move_32_di_a(void);
+void m68k_op_move_32_di_ai(void);
+void m68k_op_move_32_di_pi(void);
+void m68k_op_move_32_di_pd(void);
+void m68k_op_move_32_di_di(void);
+void m68k_op_move_32_di_ix(void);
+void m68k_op_move_32_di_aw(void);
+void m68k_op_move_32_di_al(void);
+void m68k_op_move_32_di_pcdi(void);
+void m68k_op_move_32_di_pcix(void);
+void m68k_op_move_32_di_i(void);
+void m68k_op_move_32_ix_d(void);
+void m68k_op_move_32_ix_a(void);
+void m68k_op_move_32_ix_ai(void);
+void m68k_op_move_32_ix_pi(void);
+void m68k_op_move_32_ix_pd(void);
+void m68k_op_move_32_ix_di(void);
+void m68k_op_move_32_ix_ix(void);
+void m68k_op_move_32_ix_aw(void);
+void m68k_op_move_32_ix_al(void);
+void m68k_op_move_32_ix_pcdi(void);
+void m68k_op_move_32_ix_pcix(void);
+void m68k_op_move_32_ix_i(void);
+void m68k_op_move_32_aw_d(void);
+void m68k_op_move_32_aw_a(void);
+void m68k_op_move_32_aw_ai(void);
+void m68k_op_move_32_aw_pi(void);
+void m68k_op_move_32_aw_pd(void);
+void m68k_op_move_32_aw_di(void);
+void m68k_op_move_32_aw_ix(void);
+void m68k_op_move_32_aw_aw(void);
+void m68k_op_move_32_aw_al(void);
+void m68k_op_move_32_aw_pcdi(void);
+void m68k_op_move_32_aw_pcix(void);
+void m68k_op_move_32_aw_i(void);
+void m68k_op_move_32_al_d(void);
+void m68k_op_move_32_al_a(void);
+void m68k_op_move_32_al_ai(void);
+void m68k_op_move_32_al_pi(void);
+void m68k_op_move_32_al_pd(void);
+void m68k_op_move_32_al_di(void);
+void m68k_op_move_32_al_ix(void);
+void m68k_op_move_32_al_aw(void);
+void m68k_op_move_32_al_al(void);
+void m68k_op_move_32_al_pcdi(void);
+void m68k_op_move_32_al_pcix(void);
+void m68k_op_move_32_al_i(void);
+void m68k_op_movea_16_d(void);
+void m68k_op_movea_16_a(void);
+void m68k_op_movea_16_ai(void);
+void m68k_op_movea_16_pi(void);
+void m68k_op_movea_16_pd(void);
+void m68k_op_movea_16_di(void);
+void m68k_op_movea_16_ix(void);
+void m68k_op_movea_16_aw(void);
+void m68k_op_movea_16_al(void);
+void m68k_op_movea_16_pcdi(void);
+void m68k_op_movea_16_pcix(void);
+void m68k_op_movea_16_i(void);
+void m68k_op_movea_32_d(void);
+void m68k_op_movea_32_a(void);
+void m68k_op_movea_32_ai(void);
+void m68k_op_movea_32_pi(void);
+void m68k_op_movea_32_pd(void);
+void m68k_op_movea_32_di(void);
+void m68k_op_movea_32_ix(void);
+void m68k_op_movea_32_aw(void);
+void m68k_op_movea_32_al(void);
+void m68k_op_movea_32_pcdi(void);
+void m68k_op_movea_32_pcix(void);
+void m68k_op_movea_32_i(void);
+void m68k_op_move_16_frc_d(void);
+void m68k_op_move_16_frc_ai(void);
+void m68k_op_move_16_frc_pi(void);
+void m68k_op_move_16_frc_pd(void);
+void m68k_op_move_16_frc_di(void);
+void m68k_op_move_16_frc_ix(void);
+void m68k_op_move_16_frc_aw(void);
+void m68k_op_move_16_frc_al(void);
+void m68k_op_move_16_toc_d(void);
+void m68k_op_move_16_toc_ai(void);
+void m68k_op_move_16_toc_pi(void);
+void m68k_op_move_16_toc_pd(void);
+void m68k_op_move_16_toc_di(void);
+void m68k_op_move_16_toc_ix(void);
+void m68k_op_move_16_toc_aw(void);
+void m68k_op_move_16_toc_al(void);
+void m68k_op_move_16_toc_pcdi(void);
+void m68k_op_move_16_toc_pcix(void);
+void m68k_op_move_16_toc_i(void);
+void m68k_op_move_16_frs_d(void);
+void m68k_op_move_16_frs_ai(void);
+void m68k_op_move_16_frs_pi(void);
+void m68k_op_move_16_frs_pd(void);
+void m68k_op_move_16_frs_di(void);
+void m68k_op_move_16_frs_ix(void);
+void m68k_op_move_16_frs_aw(void);
+void m68k_op_move_16_frs_al(void);
+void m68k_op_move_16_tos_d(void);
+void m68k_op_move_16_tos_ai(void);
+void m68k_op_move_16_tos_pi(void);
+void m68k_op_move_16_tos_pd(void);
+void m68k_op_move_16_tos_di(void);
+void m68k_op_move_16_tos_ix(void);
+void m68k_op_move_16_tos_aw(void);
+void m68k_op_move_16_tos_al(void);
+void m68k_op_move_16_tos_pcdi(void);
+void m68k_op_move_16_tos_pcix(void);
+void m68k_op_move_16_tos_i(void);
+void m68k_op_move_32_fru(void);
+void m68k_op_move_32_tou(void);
+void m68k_op_movec_32_cr(void);
+void m68k_op_movec_32_rc(void);
+void m68k_op_movem_16_re_pd(void);
+void m68k_op_movem_16_re_ai(void);
+void m68k_op_movem_16_re_di(void);
+void m68k_op_movem_16_re_ix(void);
+void m68k_op_movem_16_re_aw(void);
+void m68k_op_movem_16_re_al(void);
+void m68k_op_movem_32_re_pd(void);
+void m68k_op_movem_32_re_ai(void);
+void m68k_op_movem_32_re_di(void);
+void m68k_op_movem_32_re_ix(void);
+void m68k_op_movem_32_re_aw(void);
+void m68k_op_movem_32_re_al(void);
+void m68k_op_movem_16_er_pi(void);
+void m68k_op_movem_16_er_pcdi(void);
+void m68k_op_movem_16_er_pcix(void);
+void m68k_op_movem_16_er_ai(void);
+void m68k_op_movem_16_er_di(void);
+void m68k_op_movem_16_er_ix(void);
+void m68k_op_movem_16_er_aw(void);
+void m68k_op_movem_16_er_al(void);
+void m68k_op_movem_32_er_pi(void);
+void m68k_op_movem_32_er_pcdi(void);
+void m68k_op_movem_32_er_pcix(void);
+void m68k_op_movem_32_er_ai(void);
+void m68k_op_movem_32_er_di(void);
+void m68k_op_movem_32_er_ix(void);
+void m68k_op_movem_32_er_aw(void);
+void m68k_op_movem_32_er_al(void);
+void m68k_op_movep_16_re(void);
+void m68k_op_movep_32_re(void);
+void m68k_op_movep_16_er(void);
+void m68k_op_movep_32_er(void);
+void m68k_op_moves_8_ai(void);
+void m68k_op_moves_8_pi(void);
+void m68k_op_moves_8_pi7(void);
+void m68k_op_moves_8_pd(void);
+void m68k_op_moves_8_pd7(void);
+void m68k_op_moves_8_di(void);
+void m68k_op_moves_8_ix(void);
+void m68k_op_moves_8_aw(void);
+void m68k_op_moves_8_al(void);
+void m68k_op_moves_16_ai(void);
+void m68k_op_moves_16_pi(void);
+void m68k_op_moves_16_pd(void);
+void m68k_op_moves_16_di(void);
+void m68k_op_moves_16_ix(void);
+void m68k_op_moves_16_aw(void);
+void m68k_op_moves_16_al(void);
+void m68k_op_moves_32_ai(void);
+void m68k_op_moves_32_pi(void);
+void m68k_op_moves_32_pd(void);
+void m68k_op_moves_32_di(void);
+void m68k_op_moves_32_ix(void);
+void m68k_op_moves_32_aw(void);
+void m68k_op_moves_32_al(void);
+void m68k_op_moveq_32(void);
+void m68k_op_muls_16_d(void);
+void m68k_op_muls_16_ai(void);
+void m68k_op_muls_16_pi(void);
+void m68k_op_muls_16_pd(void);
+void m68k_op_muls_16_di(void);
+void m68k_op_muls_16_ix(void);
+void m68k_op_muls_16_aw(void);
+void m68k_op_muls_16_al(void);
+void m68k_op_muls_16_pcdi(void);
+void m68k_op_muls_16_pcix(void);
+void m68k_op_muls_16_i(void);
+void m68k_op_mulu_16_d(void);
+void m68k_op_mulu_16_ai(void);
+void m68k_op_mulu_16_pi(void);
+void m68k_op_mulu_16_pd(void);
+void m68k_op_mulu_16_di(void);
+void m68k_op_mulu_16_ix(void);
+void m68k_op_mulu_16_aw(void);
+void m68k_op_mulu_16_al(void);
+void m68k_op_mulu_16_pcdi(void);
+void m68k_op_mulu_16_pcix(void);
+void m68k_op_mulu_16_i(void);
+void m68k_op_mull_32_d(void);
+void m68k_op_mull_32_ai(void);
+void m68k_op_mull_32_pi(void);
+void m68k_op_mull_32_pd(void);
+void m68k_op_mull_32_di(void);
+void m68k_op_mull_32_ix(void);
+void m68k_op_mull_32_aw(void);
+void m68k_op_mull_32_al(void);
+void m68k_op_mull_32_pcdi(void);
+void m68k_op_mull_32_pcix(void);
+void m68k_op_mull_32_i(void);
+void m68k_op_nbcd_8_d(void);
+void m68k_op_nbcd_8_ai(void);
+void m68k_op_nbcd_8_pi(void);
+void m68k_op_nbcd_8_pi7(void);
+void m68k_op_nbcd_8_pd(void);
+void m68k_op_nbcd_8_pd7(void);
+void m68k_op_nbcd_8_di(void);
+void m68k_op_nbcd_8_ix(void);
+void m68k_op_nbcd_8_aw(void);
+void m68k_op_nbcd_8_al(void);
+void m68k_op_neg_8_d(void);
+void m68k_op_neg_8_ai(void);
+void m68k_op_neg_8_pi(void);
+void m68k_op_neg_8_pi7(void);
+void m68k_op_neg_8_pd(void);
+void m68k_op_neg_8_pd7(void);
+void m68k_op_neg_8_di(void);
+void m68k_op_neg_8_ix(void);
+void m68k_op_neg_8_aw(void);
+void m68k_op_neg_8_al(void);
+void m68k_op_neg_16_d(void);
+void m68k_op_neg_16_ai(void);
+void m68k_op_neg_16_pi(void);
+void m68k_op_neg_16_pd(void);
+void m68k_op_neg_16_di(void);
+void m68k_op_neg_16_ix(void);
+void m68k_op_neg_16_aw(void);
+void m68k_op_neg_16_al(void);
+void m68k_op_neg_32_d(void);
+void m68k_op_neg_32_ai(void);
+void m68k_op_neg_32_pi(void);
+void m68k_op_neg_32_pd(void);
+void m68k_op_neg_32_di(void);
+void m68k_op_neg_32_ix(void);
+void m68k_op_neg_32_aw(void);
+void m68k_op_neg_32_al(void);
+void m68k_op_negx_8_d(void);
+void m68k_op_negx_8_ai(void);
+void m68k_op_negx_8_pi(void);
+void m68k_op_negx_8_pi7(void);
+void m68k_op_negx_8_pd(void);
+void m68k_op_negx_8_pd7(void);
+void m68k_op_negx_8_di(void);
+void m68k_op_negx_8_ix(void);
+void m68k_op_negx_8_aw(void);
+void m68k_op_negx_8_al(void);
+void m68k_op_negx_16_d(void);
+void m68k_op_negx_16_ai(void);
+void m68k_op_negx_16_pi(void);
+void m68k_op_negx_16_pd(void);
+void m68k_op_negx_16_di(void);
+void m68k_op_negx_16_ix(void);
+void m68k_op_negx_16_aw(void);
+void m68k_op_negx_16_al(void);
+void m68k_op_negx_32_d(void);
+void m68k_op_negx_32_ai(void);
+void m68k_op_negx_32_pi(void);
+void m68k_op_negx_32_pd(void);
+void m68k_op_negx_32_di(void);
+void m68k_op_negx_32_ix(void);
+void m68k_op_negx_32_aw(void);
+void m68k_op_negx_32_al(void);
+void m68k_op_nop(void);
+void m68k_op_not_8_d(void);
+void m68k_op_not_8_ai(void);
+void m68k_op_not_8_pi(void);
+void m68k_op_not_8_pi7(void);
+void m68k_op_not_8_pd(void);
+void m68k_op_not_8_pd7(void);
+void m68k_op_not_8_di(void);
+void m68k_op_not_8_ix(void);
+void m68k_op_not_8_aw(void);
+void m68k_op_not_8_al(void);
+void m68k_op_not_16_d(void);
+void m68k_op_not_16_ai(void);
+void m68k_op_not_16_pi(void);
+void m68k_op_not_16_pd(void);
+void m68k_op_not_16_di(void);
+void m68k_op_not_16_ix(void);
+void m68k_op_not_16_aw(void);
+void m68k_op_not_16_al(void);
+void m68k_op_not_32_d(void);
+void m68k_op_not_32_ai(void);
+void m68k_op_not_32_pi(void);
+void m68k_op_not_32_pd(void);
+void m68k_op_not_32_di(void);
+void m68k_op_not_32_ix(void);
+void m68k_op_not_32_aw(void);
+void m68k_op_not_32_al(void);
+void m68k_op_or_8_er_d(void);
+void m68k_op_or_8_er_ai(void);
+void m68k_op_or_8_er_pi(void);
+void m68k_op_or_8_er_pi7(void);
+void m68k_op_or_8_er_pd(void);
+void m68k_op_or_8_er_pd7(void);
+void m68k_op_or_8_er_di(void);
+void m68k_op_or_8_er_ix(void);
+void m68k_op_or_8_er_aw(void);
+void m68k_op_or_8_er_al(void);
+void m68k_op_or_8_er_pcdi(void);
+void m68k_op_or_8_er_pcix(void);
+void m68k_op_or_8_er_i(void);
+void m68k_op_or_16_er_d(void);
+void m68k_op_or_16_er_ai(void);
+void m68k_op_or_16_er_pi(void);
+void m68k_op_or_16_er_pd(void);
+void m68k_op_or_16_er_di(void);
+void m68k_op_or_16_er_ix(void);
+void m68k_op_or_16_er_aw(void);
+void m68k_op_or_16_er_al(void);
+void m68k_op_or_16_er_pcdi(void);
+void m68k_op_or_16_er_pcix(void);
+void m68k_op_or_16_er_i(void);
+void m68k_op_or_32_er_d(void);
+void m68k_op_or_32_er_ai(void);
+void m68k_op_or_32_er_pi(void);
+void m68k_op_or_32_er_pd(void);
+void m68k_op_or_32_er_di(void);
+void m68k_op_or_32_er_ix(void);
+void m68k_op_or_32_er_aw(void);
+void m68k_op_or_32_er_al(void);
+void m68k_op_or_32_er_pcdi(void);
+void m68k_op_or_32_er_pcix(void);
+void m68k_op_or_32_er_i(void);
+void m68k_op_or_8_re_ai(void);
+void m68k_op_or_8_re_pi(void);
+void m68k_op_or_8_re_pi7(void);
+void m68k_op_or_8_re_pd(void);
+void m68k_op_or_8_re_pd7(void);
+void m68k_op_or_8_re_di(void);
+void m68k_op_or_8_re_ix(void);
+void m68k_op_or_8_re_aw(void);
+void m68k_op_or_8_re_al(void);
+void m68k_op_or_16_re_ai(void);
+void m68k_op_or_16_re_pi(void);
+void m68k_op_or_16_re_pd(void);
+void m68k_op_or_16_re_di(void);
+void m68k_op_or_16_re_ix(void);
+void m68k_op_or_16_re_aw(void);
+void m68k_op_or_16_re_al(void);
+void m68k_op_or_32_re_ai(void);
+void m68k_op_or_32_re_pi(void);
+void m68k_op_or_32_re_pd(void);
+void m68k_op_or_32_re_di(void);
+void m68k_op_or_32_re_ix(void);
+void m68k_op_or_32_re_aw(void);
+void m68k_op_or_32_re_al(void);
+void m68k_op_ori_8_d(void);
+void m68k_op_ori_8_ai(void);
+void m68k_op_ori_8_pi(void);
+void m68k_op_ori_8_pi7(void);
+void m68k_op_ori_8_pd(void);
+void m68k_op_ori_8_pd7(void);
+void m68k_op_ori_8_di(void);
+void m68k_op_ori_8_ix(void);
+void m68k_op_ori_8_aw(void);
+void m68k_op_ori_8_al(void);
+void m68k_op_ori_16_d(void);
+void m68k_op_ori_16_ai(void);
+void m68k_op_ori_16_pi(void);
+void m68k_op_ori_16_pd(void);
+void m68k_op_ori_16_di(void);
+void m68k_op_ori_16_ix(void);
+void m68k_op_ori_16_aw(void);
+void m68k_op_ori_16_al(void);
+void m68k_op_ori_32_d(void);
+void m68k_op_ori_32_ai(void);
+void m68k_op_ori_32_pi(void);
+void m68k_op_ori_32_pd(void);
+void m68k_op_ori_32_di(void);
+void m68k_op_ori_32_ix(void);
+void m68k_op_ori_32_aw(void);
+void m68k_op_ori_32_al(void);
+void m68k_op_ori_16_toc(void);
+void m68k_op_ori_16_tos(void);
+void m68k_op_pack_16_rr(void);
+void m68k_op_pack_16_mm_ax7(void);
+void m68k_op_pack_16_mm_ay7(void);
+void m68k_op_pack_16_mm_axy7(void);
+void m68k_op_pack_16_mm(void);
+void m68k_op_pea_32_ai(void);
+void m68k_op_pea_32_di(void);
+void m68k_op_pea_32_ix(void);
+void m68k_op_pea_32_aw(void);
+void m68k_op_pea_32_al(void);
+void m68k_op_pea_32_pcdi(void);
+void m68k_op_pea_32_pcix(void);
+void m68k_op_reset(void);
+void m68k_op_ror_8_s(void);
+void m68k_op_ror_16_s(void);
+void m68k_op_ror_32_s(void);
+void m68k_op_ror_8_r(void);
+void m68k_op_ror_16_r(void);
+void m68k_op_ror_32_r(void);
+void m68k_op_ror_16_ai(void);
+void m68k_op_ror_16_pi(void);
+void m68k_op_ror_16_pd(void);
+void m68k_op_ror_16_di(void);
+void m68k_op_ror_16_ix(void);
+void m68k_op_ror_16_aw(void);
+void m68k_op_ror_16_al(void);
+void m68k_op_rol_8_s(void);
+void m68k_op_rol_16_s(void);
+void m68k_op_rol_32_s(void);
+void m68k_op_rol_8_r(void);
+void m68k_op_rol_16_r(void);
+void m68k_op_rol_32_r(void);
+void m68k_op_rol_16_ai(void);
+void m68k_op_rol_16_pi(void);
+void m68k_op_rol_16_pd(void);
+void m68k_op_rol_16_di(void);
+void m68k_op_rol_16_ix(void);
+void m68k_op_rol_16_aw(void);
+void m68k_op_rol_16_al(void);
+void m68k_op_roxr_8_s(void);
+void m68k_op_roxr_16_s(void);
+void m68k_op_roxr_32_s(void);
+void m68k_op_roxr_8_r(void);
+void m68k_op_roxr_16_r(void);
+void m68k_op_roxr_32_r(void);
+void m68k_op_roxr_16_ai(void);
+void m68k_op_roxr_16_pi(void);
+void m68k_op_roxr_16_pd(void);
+void m68k_op_roxr_16_di(void);
+void m68k_op_roxr_16_ix(void);
+void m68k_op_roxr_16_aw(void);
+void m68k_op_roxr_16_al(void);
+void m68k_op_roxl_8_s(void);
+void m68k_op_roxl_16_s(void);
+void m68k_op_roxl_32_s(void);
+void m68k_op_roxl_8_r(void);
+void m68k_op_roxl_16_r(void);
+void m68k_op_roxl_32_r(void);
+void m68k_op_roxl_16_ai(void);
+void m68k_op_roxl_16_pi(void);
+void m68k_op_roxl_16_pd(void);
+void m68k_op_roxl_16_di(void);
+void m68k_op_roxl_16_ix(void);
+void m68k_op_roxl_16_aw(void);
+void m68k_op_roxl_16_al(void);
+void m68k_op_rtd_32(void);
+void m68k_op_rte_32(void);
+void m68k_op_rtm_32(void);
+void m68k_op_rtr_32(void);
+void m68k_op_rts_32(void);
+void m68k_op_sbcd_8_rr(void);
+void m68k_op_sbcd_8_mm_ax7(void);
+void m68k_op_sbcd_8_mm_ay7(void);
+void m68k_op_sbcd_8_mm_axy7(void);
+void m68k_op_sbcd_8_mm(void);
+void m68k_op_st_8_d(void);
+void m68k_op_st_8_ai(void);
+void m68k_op_st_8_pi(void);
+void m68k_op_st_8_pi7(void);
+void m68k_op_st_8_pd(void);
+void m68k_op_st_8_pd7(void);
+void m68k_op_st_8_di(void);
+void m68k_op_st_8_ix(void);
+void m68k_op_st_8_aw(void);
+void m68k_op_st_8_al(void);
+void m68k_op_sf_8_d(void);
+void m68k_op_sf_8_ai(void);
+void m68k_op_sf_8_pi(void);
+void m68k_op_sf_8_pi7(void);
+void m68k_op_sf_8_pd(void);
+void m68k_op_sf_8_pd7(void);
+void m68k_op_sf_8_di(void);
+void m68k_op_sf_8_ix(void);
+void m68k_op_sf_8_aw(void);
+void m68k_op_sf_8_al(void);
+void m68k_op_shi_8_d(void);
+void m68k_op_sls_8_d(void);
+void m68k_op_scc_8_d(void);
+void m68k_op_scs_8_d(void);
+void m68k_op_sne_8_d(void);
+void m68k_op_seq_8_d(void);
+void m68k_op_svc_8_d(void);
+void m68k_op_svs_8_d(void);
+void m68k_op_spl_8_d(void);
+void m68k_op_smi_8_d(void);
+void m68k_op_sge_8_d(void);
+void m68k_op_slt_8_d(void);
+void m68k_op_sgt_8_d(void);
+void m68k_op_sle_8_d(void);
+void m68k_op_shi_8_ai(void);
+void m68k_op_shi_8_pi(void);
+void m68k_op_shi_8_pi7(void);
+void m68k_op_shi_8_pd(void);
+void m68k_op_shi_8_pd7(void);
+void m68k_op_shi_8_di(void);
+void m68k_op_shi_8_ix(void);
+void m68k_op_shi_8_aw(void);
+void m68k_op_shi_8_al(void);
+void m68k_op_sls_8_ai(void);
+void m68k_op_sls_8_pi(void);
+void m68k_op_sls_8_pi7(void);
+void m68k_op_sls_8_pd(void);
+void m68k_op_sls_8_pd7(void);
+void m68k_op_sls_8_di(void);
+void m68k_op_sls_8_ix(void);
+void m68k_op_sls_8_aw(void);
+void m68k_op_sls_8_al(void);
+void m68k_op_scc_8_ai(void);
+void m68k_op_scc_8_pi(void);
+void m68k_op_scc_8_pi7(void);
+void m68k_op_scc_8_pd(void);
+void m68k_op_scc_8_pd7(void);
+void m68k_op_scc_8_di(void);
+void m68k_op_scc_8_ix(void);
+void m68k_op_scc_8_aw(void);
+void m68k_op_scc_8_al(void);
+void m68k_op_scs_8_ai(void);
+void m68k_op_scs_8_pi(void);
+void m68k_op_scs_8_pi7(void);
+void m68k_op_scs_8_pd(void);
+void m68k_op_scs_8_pd7(void);
+void m68k_op_scs_8_di(void);
+void m68k_op_scs_8_ix(void);
+void m68k_op_scs_8_aw(void);
+void m68k_op_scs_8_al(void);
+void m68k_op_sne_8_ai(void);
+void m68k_op_sne_8_pi(void);
+void m68k_op_sne_8_pi7(void);
+void m68k_op_sne_8_pd(void);
+void m68k_op_sne_8_pd7(void);
+void m68k_op_sne_8_di(void);
+void m68k_op_sne_8_ix(void);
+void m68k_op_sne_8_aw(void);
+void m68k_op_sne_8_al(void);
+void m68k_op_seq_8_ai(void);
+void m68k_op_seq_8_pi(void);
+void m68k_op_seq_8_pi7(void);
+void m68k_op_seq_8_pd(void);
+void m68k_op_seq_8_pd7(void);
+void m68k_op_seq_8_di(void);
+void m68k_op_seq_8_ix(void);
+void m68k_op_seq_8_aw(void);
+void m68k_op_seq_8_al(void);
+void m68k_op_svc_8_ai(void);
+void m68k_op_svc_8_pi(void);
+void m68k_op_svc_8_pi7(void);
+void m68k_op_svc_8_pd(void);
+void m68k_op_svc_8_pd7(void);
+void m68k_op_svc_8_di(void);
+void m68k_op_svc_8_ix(void);
+void m68k_op_svc_8_aw(void);
+void m68k_op_svc_8_al(void);
+void m68k_op_svs_8_ai(void);
+void m68k_op_svs_8_pi(void);
+void m68k_op_svs_8_pi7(void);
+void m68k_op_svs_8_pd(void);
+void m68k_op_svs_8_pd7(void);
+void m68k_op_svs_8_di(void);
+void m68k_op_svs_8_ix(void);
+void m68k_op_svs_8_aw(void);
+void m68k_op_svs_8_al(void);
+void m68k_op_spl_8_ai(void);
+void m68k_op_spl_8_pi(void);
+void m68k_op_spl_8_pi7(void);
+void m68k_op_spl_8_pd(void);
+void m68k_op_spl_8_pd7(void);
+void m68k_op_spl_8_di(void);
+void m68k_op_spl_8_ix(void);
+void m68k_op_spl_8_aw(void);
+void m68k_op_spl_8_al(void);
+void m68k_op_smi_8_ai(void);
+void m68k_op_smi_8_pi(void);
+void m68k_op_smi_8_pi7(void);
+void m68k_op_smi_8_pd(void);
+void m68k_op_smi_8_pd7(void);
+void m68k_op_smi_8_di(void);
+void m68k_op_smi_8_ix(void);
+void m68k_op_smi_8_aw(void);
+void m68k_op_smi_8_al(void);
+void m68k_op_sge_8_ai(void);
+void m68k_op_sge_8_pi(void);
+void m68k_op_sge_8_pi7(void);
+void m68k_op_sge_8_pd(void);
+void m68k_op_sge_8_pd7(void);
+void m68k_op_sge_8_di(void);
+void m68k_op_sge_8_ix(void);
+void m68k_op_sge_8_aw(void);
+void m68k_op_sge_8_al(void);
+void m68k_op_slt_8_ai(void);
+void m68k_op_slt_8_pi(void);
+void m68k_op_slt_8_pi7(void);
+void m68k_op_slt_8_pd(void);
+void m68k_op_slt_8_pd7(void);
+void m68k_op_slt_8_di(void);
+void m68k_op_slt_8_ix(void);
+void m68k_op_slt_8_aw(void);
+void m68k_op_slt_8_al(void);
+void m68k_op_sgt_8_ai(void);
+void m68k_op_sgt_8_pi(void);
+void m68k_op_sgt_8_pi7(void);
+void m68k_op_sgt_8_pd(void);
+void m68k_op_sgt_8_pd7(void);
+void m68k_op_sgt_8_di(void);
+void m68k_op_sgt_8_ix(void);
+void m68k_op_sgt_8_aw(void);
+void m68k_op_sgt_8_al(void);
+void m68k_op_sle_8_ai(void);
+void m68k_op_sle_8_pi(void);
+void m68k_op_sle_8_pi7(void);
+void m68k_op_sle_8_pd(void);
+void m68k_op_sle_8_pd7(void);
+void m68k_op_sle_8_di(void);
+void m68k_op_sle_8_ix(void);
+void m68k_op_sle_8_aw(void);
+void m68k_op_sle_8_al(void);
+void m68k_op_stop(void);
+void m68k_op_sub_8_er_d(void);
+void m68k_op_sub_8_er_ai(void);
+void m68k_op_sub_8_er_pi(void);
+void m68k_op_sub_8_er_pi7(void);
+void m68k_op_sub_8_er_pd(void);
+void m68k_op_sub_8_er_pd7(void);
+void m68k_op_sub_8_er_di(void);
+void m68k_op_sub_8_er_ix(void);
+void m68k_op_sub_8_er_aw(void);
+void m68k_op_sub_8_er_al(void);
+void m68k_op_sub_8_er_pcdi(void);
+void m68k_op_sub_8_er_pcix(void);
+void m68k_op_sub_8_er_i(void);
+void m68k_op_sub_16_er_d(void);
+void m68k_op_sub_16_er_a(void);
+void m68k_op_sub_16_er_ai(void);
+void m68k_op_sub_16_er_pi(void);
+void m68k_op_sub_16_er_pd(void);
+void m68k_op_sub_16_er_di(void);
+void m68k_op_sub_16_er_ix(void);
+void m68k_op_sub_16_er_aw(void);
+void m68k_op_sub_16_er_al(void);
+void m68k_op_sub_16_er_pcdi(void);
+void m68k_op_sub_16_er_pcix(void);
+void m68k_op_sub_16_er_i(void);
+void m68k_op_sub_32_er_d(void);
+void m68k_op_sub_32_er_a(void);
+void m68k_op_sub_32_er_ai(void);
+void m68k_op_sub_32_er_pi(void);
+void m68k_op_sub_32_er_pd(void);
+void m68k_op_sub_32_er_di(void);
+void m68k_op_sub_32_er_ix(void);
+void m68k_op_sub_32_er_aw(void);
+void m68k_op_sub_32_er_al(void);
+void m68k_op_sub_32_er_pcdi(void);
+void m68k_op_sub_32_er_pcix(void);
+void m68k_op_sub_32_er_i(void);
+void m68k_op_sub_8_re_ai(void);
+void m68k_op_sub_8_re_pi(void);
+void m68k_op_sub_8_re_pi7(void);
+void m68k_op_sub_8_re_pd(void);
+void m68k_op_sub_8_re_pd7(void);
+void m68k_op_sub_8_re_di(void);
+void m68k_op_sub_8_re_ix(void);
+void m68k_op_sub_8_re_aw(void);
+void m68k_op_sub_8_re_al(void);
+void m68k_op_sub_16_re_ai(void);
+void m68k_op_sub_16_re_pi(void);
+void m68k_op_sub_16_re_pd(void);
+void m68k_op_sub_16_re_di(void);
+void m68k_op_sub_16_re_ix(void);
+void m68k_op_sub_16_re_aw(void);
+void m68k_op_sub_16_re_al(void);
+void m68k_op_sub_32_re_ai(void);
+void m68k_op_sub_32_re_pi(void);
+void m68k_op_sub_32_re_pd(void);
+void m68k_op_sub_32_re_di(void);
+void m68k_op_sub_32_re_ix(void);
+void m68k_op_sub_32_re_aw(void);
+void m68k_op_sub_32_re_al(void);
+void m68k_op_suba_16_d(void);
+void m68k_op_suba_16_a(void);
+void m68k_op_suba_16_ai(void);
+void m68k_op_suba_16_pi(void);
+void m68k_op_suba_16_pd(void);
+void m68k_op_suba_16_di(void);
+void m68k_op_suba_16_ix(void);
+void m68k_op_suba_16_aw(void);
+void m68k_op_suba_16_al(void);
+void m68k_op_suba_16_pcdi(void);
+void m68k_op_suba_16_pcix(void);
+void m68k_op_suba_16_i(void);
+void m68k_op_suba_32_d(void);
+void m68k_op_suba_32_a(void);
+void m68k_op_suba_32_ai(void);
+void m68k_op_suba_32_pi(void);
+void m68k_op_suba_32_pd(void);
+void m68k_op_suba_32_di(void);
+void m68k_op_suba_32_ix(void);
+void m68k_op_suba_32_aw(void);
+void m68k_op_suba_32_al(void);
+void m68k_op_suba_32_pcdi(void);
+void m68k_op_suba_32_pcix(void);
+void m68k_op_suba_32_i(void);
+void m68k_op_subi_8_d(void);
+void m68k_op_subi_8_ai(void);
+void m68k_op_subi_8_pi(void);
+void m68k_op_subi_8_pi7(void);
+void m68k_op_subi_8_pd(void);
+void m68k_op_subi_8_pd7(void);
+void m68k_op_subi_8_di(void);
+void m68k_op_subi_8_ix(void);
+void m68k_op_subi_8_aw(void);
+void m68k_op_subi_8_al(void);
+void m68k_op_subi_16_d(void);
+void m68k_op_subi_16_ai(void);
+void m68k_op_subi_16_pi(void);
+void m68k_op_subi_16_pd(void);
+void m68k_op_subi_16_di(void);
+void m68k_op_subi_16_ix(void);
+void m68k_op_subi_16_aw(void);
+void m68k_op_subi_16_al(void);
+void m68k_op_subi_32_d(void);
+void m68k_op_subi_32_ai(void);
+void m68k_op_subi_32_pi(void);
+void m68k_op_subi_32_pd(void);
+void m68k_op_subi_32_di(void);
+void m68k_op_subi_32_ix(void);
+void m68k_op_subi_32_aw(void);
+void m68k_op_subi_32_al(void);
+void m68k_op_subq_8_d(void);
+void m68k_op_subq_8_ai(void);
+void m68k_op_subq_8_pi(void);
+void m68k_op_subq_8_pi7(void);
+void m68k_op_subq_8_pd(void);
+void m68k_op_subq_8_pd7(void);
+void m68k_op_subq_8_di(void);
+void m68k_op_subq_8_ix(void);
+void m68k_op_subq_8_aw(void);
+void m68k_op_subq_8_al(void);
+void m68k_op_subq_16_d(void);
+void m68k_op_subq_16_a(void);
+void m68k_op_subq_16_ai(void);
+void m68k_op_subq_16_pi(void);
+void m68k_op_subq_16_pd(void);
+void m68k_op_subq_16_di(void);
+void m68k_op_subq_16_ix(void);
+void m68k_op_subq_16_aw(void);
+void m68k_op_subq_16_al(void);
+void m68k_op_subq_32_d(void);
+void m68k_op_subq_32_a(void);
+void m68k_op_subq_32_ai(void);
+void m68k_op_subq_32_pi(void);
+void m68k_op_subq_32_pd(void);
+void m68k_op_subq_32_di(void);
+void m68k_op_subq_32_ix(void);
+void m68k_op_subq_32_aw(void);
+void m68k_op_subq_32_al(void);
+void m68k_op_subx_8_rr(void);
+void m68k_op_subx_16_rr(void);
+void m68k_op_subx_32_rr(void);
+void m68k_op_subx_8_mm_ax7(void);
+void m68k_op_subx_8_mm_ay7(void);
+void m68k_op_subx_8_mm_axy7(void);
+void m68k_op_subx_8_mm(void);
+void m68k_op_subx_16_mm(void);
+void m68k_op_subx_32_mm(void);
+void m68k_op_swap_32(void);
+void m68k_op_tas_8_d(void);
+void m68k_op_tas_8_ai(void);
+void m68k_op_tas_8_pi(void);
+void m68k_op_tas_8_pi7(void);
+void m68k_op_tas_8_pd(void);
+void m68k_op_tas_8_pd7(void);
+void m68k_op_tas_8_di(void);
+void m68k_op_tas_8_ix(void);
+void m68k_op_tas_8_aw(void);
+void m68k_op_tas_8_al(void);
+void m68k_op_trap(void);
+void m68k_op_trapt(void);
+void m68k_op_trapt_16(void);
+void m68k_op_trapt_32(void);
+void m68k_op_trapf(void);
+void m68k_op_trapf_16(void);
+void m68k_op_trapf_32(void);
+void m68k_op_traphi(void);
+void m68k_op_trapls(void);
+void m68k_op_trapcc(void);
+void m68k_op_trapcs(void);
+void m68k_op_trapne(void);
+void m68k_op_trapeq(void);
+void m68k_op_trapvc(void);
+void m68k_op_trapvs(void);
+void m68k_op_trappl(void);
+void m68k_op_trapmi(void);
+void m68k_op_trapge(void);
+void m68k_op_traplt(void);
+void m68k_op_trapgt(void);
+void m68k_op_traple(void);
+void m68k_op_traphi_16(void);
+void m68k_op_trapls_16(void);
+void m68k_op_trapcc_16(void);
+void m68k_op_trapcs_16(void);
+void m68k_op_trapne_16(void);
+void m68k_op_trapeq_16(void);
+void m68k_op_trapvc_16(void);
+void m68k_op_trapvs_16(void);
+void m68k_op_trappl_16(void);
+void m68k_op_trapmi_16(void);
+void m68k_op_trapge_16(void);
+void m68k_op_traplt_16(void);
+void m68k_op_trapgt_16(void);
+void m68k_op_traple_16(void);
+void m68k_op_traphi_32(void);
+void m68k_op_trapls_32(void);
+void m68k_op_trapcc_32(void);
+void m68k_op_trapcs_32(void);
+void m68k_op_trapne_32(void);
+void m68k_op_trapeq_32(void);
+void m68k_op_trapvc_32(void);
+void m68k_op_trapvs_32(void);
+void m68k_op_trappl_32(void);
+void m68k_op_trapmi_32(void);
+void m68k_op_trapge_32(void);
+void m68k_op_traplt_32(void);
+void m68k_op_trapgt_32(void);
+void m68k_op_traple_32(void);
+void m68k_op_trapv(void);
+void m68k_op_tst_8_d(void);
+void m68k_op_tst_8_ai(void);
+void m68k_op_tst_8_pi(void);
+void m68k_op_tst_8_pi7(void);
+void m68k_op_tst_8_pd(void);
+void m68k_op_tst_8_pd7(void);
+void m68k_op_tst_8_di(void);
+void m68k_op_tst_8_ix(void);
+void m68k_op_tst_8_aw(void);
+void m68k_op_tst_8_al(void);
+void m68k_op_tst_8_pcdi(void);
+void m68k_op_tst_8_pcix(void);
+void m68k_op_tst_8_i(void);
+void m68k_op_tst_16_d(void);
+void m68k_op_tst_16_a(void);
+void m68k_op_tst_16_ai(void);
+void m68k_op_tst_16_pi(void);
+void m68k_op_tst_16_pd(void);
+void m68k_op_tst_16_di(void);
+void m68k_op_tst_16_ix(void);
+void m68k_op_tst_16_aw(void);
+void m68k_op_tst_16_al(void);
+void m68k_op_tst_16_pcdi(void);
+void m68k_op_tst_16_pcix(void);
+void m68k_op_tst_16_i(void);
+void m68k_op_tst_32_d(void);
+void m68k_op_tst_32_a(void);
+void m68k_op_tst_32_ai(void);
+void m68k_op_tst_32_pi(void);
+void m68k_op_tst_32_pd(void);
+void m68k_op_tst_32_di(void);
+void m68k_op_tst_32_ix(void);
+void m68k_op_tst_32_aw(void);
+void m68k_op_tst_32_al(void);
+void m68k_op_tst_32_pcdi(void);
+void m68k_op_tst_32_pcix(void);
+void m68k_op_tst_32_i(void);
+void m68k_op_unlk_32_a7(void);
+void m68k_op_unlk_32(void);
+void m68k_op_unpk_16_rr(void);
+void m68k_op_unpk_16_mm_ax7(void);
+void m68k_op_unpk_16_mm_ay7(void);
+void m68k_op_unpk_16_mm_axy7(void);
+void m68k_op_unpk_16_mm(void);
+/* Build the opcode handler table */
+void m68ki_build_opcode_table(void);
+
+typedef void (*m68ki_instruction_jump_call)(void);
+
+extern const m68ki_instruction_jump_call m68ki_instruction_jump_table[];
+//extern void (*m68ki_instruction_jump_table)(void); /* opcode handler jump table */
+//extern const unsigned char m68ki_cycles[1][0x10000];
+extern const unsigned char m68ki_cycles[1][0x10000];
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* M68KOPS__HEADER */
+
+
diff --git a/MCUME_pico2/picogenold/musashi34/m68kops_pre.c b/MCUME_pico2/picogenold/musashi34/m68kops_pre.c
new file mode 100644
index 0000000..40bee10
--- /dev/null
+++ b/MCUME_pico2/picogenold/musashi34/m68kops_pre.c
@@ -0,0 +1,69644 @@
+#include "m68kops.h"
+
+//Opcodes are built on the host, this does not need to do anything.
+void m68ki_build_opcode_table() {}
+//#include <Arduino.h>
+
+/*PROGMEM*/ const m68ki_instruction_jump_call m68ki_instruction_jump_table[]={
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_ori_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_ai            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi            , 
+	m68k_op_ori_8_pi7           , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd            , 
+	m68k_op_ori_8_pd7           , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_di            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_ix            , 
+	m68k_op_ori_8_aw            , 
+	m68k_op_ori_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_16_toc          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_ori_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_ai           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pi           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_pd           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_di           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_ix           , 
+	m68k_op_ori_16_aw           , 
+	m68k_op_ori_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_16_tos          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_ori_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_ai           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pi           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_pd           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_di           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_ix           , 
+	m68k_op_ori_32_aw           , 
+	m68k_op_ori_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_chk2cmp2_8_ai       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_di       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_ix       , 
+	m68k_op_chk2cmp2_8_aw       , 
+	m68k_op_chk2cmp2_8_al       , 
+	m68k_op_chk2cmp2_8_pcdi     , 
+	m68k_op_chk2cmp2_8_pcix     , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_andi_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_ai           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi           , 
+	m68k_op_andi_8_pi7          , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd           , 
+	m68k_op_andi_8_pd7          , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_di           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_ix           , 
+	m68k_op_andi_8_aw           , 
+	m68k_op_andi_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_16_toc         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_andi_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_ai          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pi          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_pd          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_di          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_ix          , 
+	m68k_op_andi_16_aw          , 
+	m68k_op_andi_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_16_tos         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_andi_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_ai          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pi          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_pd          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_di          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_ix          , 
+	m68k_op_andi_32_aw          , 
+	m68k_op_andi_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_chk2cmp2_16_ai      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_di      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_ix      , 
+	m68k_op_chk2cmp2_16_aw      , 
+	m68k_op_chk2cmp2_16_al      , 
+	m68k_op_chk2cmp2_16_pcdi    , 
+	m68k_op_chk2cmp2_16_pcix    , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_subi_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_ai           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi           , 
+	m68k_op_subi_8_pi7          , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd           , 
+	m68k_op_subi_8_pd7          , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_di           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_ix           , 
+	m68k_op_subi_8_aw           , 
+	m68k_op_subi_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_subi_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_ai          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pi          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_pd          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_di          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_ix          , 
+	m68k_op_subi_16_aw          , 
+	m68k_op_subi_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_subi_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_ai          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pi          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_pd          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_di          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_ix          , 
+	m68k_op_subi_32_aw          , 
+	m68k_op_subi_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_chk2cmp2_32_ai      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_di      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_ix      , 
+	m68k_op_chk2cmp2_32_aw      , 
+	m68k_op_chk2cmp2_32_al      , 
+	m68k_op_chk2cmp2_32_pcdi    , 
+	m68k_op_chk2cmp2_32_pcix    , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_addi_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_ai           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi           , 
+	m68k_op_addi_8_pi7          , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd           , 
+	m68k_op_addi_8_pd7          , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_di           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_ix           , 
+	m68k_op_addi_8_aw           , 
+	m68k_op_addi_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_addi_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_ai          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pi          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_pd          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_di          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_ix          , 
+	m68k_op_addi_16_aw          , 
+	m68k_op_addi_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_addi_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_ai          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pi          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_pd          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_di          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_ix          , 
+	m68k_op_addi_32_aw          , 
+	m68k_op_addi_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_rtm_32              , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_callm_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_di         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_ix         , 
+	m68k_op_callm_32_aw         , 
+	m68k_op_callm_32_al         , 
+	m68k_op_callm_32_pcdi       , 
+	m68k_op_callm_32_pcix       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_btst_32_s_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_ai         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi         , 
+	m68k_op_btst_8_s_pi7        , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd         , 
+	m68k_op_btst_8_s_pd7        , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_di         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_ix         , 
+	m68k_op_btst_8_s_aw         , 
+	m68k_op_btst_8_s_al         , 
+	m68k_op_btst_8_s_pcdi       , 
+	m68k_op_btst_8_s_pcix       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_bchg_32_s_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_ai         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi         , 
+	m68k_op_bchg_8_s_pi7        , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd         , 
+	m68k_op_bchg_8_s_pd7        , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_di         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_ix         , 
+	m68k_op_bchg_8_s_aw         , 
+	m68k_op_bchg_8_s_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_bclr_32_s_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_ai         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi         , 
+	m68k_op_bclr_8_s_pi7        , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd         , 
+	m68k_op_bclr_8_s_pd7        , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_di         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_ix         , 
+	m68k_op_bclr_8_s_aw         , 
+	m68k_op_bclr_8_s_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_bset_32_s_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_ai         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi         , 
+	m68k_op_bset_8_s_pi7        , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd         , 
+	m68k_op_bset_8_s_pd7        , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_di         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_ix         , 
+	m68k_op_bset_8_s_aw         , 
+	m68k_op_bset_8_s_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_eori_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_ai           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi           , 
+	m68k_op_eori_8_pi7          , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd           , 
+	m68k_op_eori_8_pd7          , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_di           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_ix           , 
+	m68k_op_eori_8_aw           , 
+	m68k_op_eori_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_16_toc         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_eori_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_ai          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pi          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_pd          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_di          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_ix          , 
+	m68k_op_eori_16_aw          , 
+	m68k_op_eori_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_16_tos         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_eori_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_ai          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pi          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_pd          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_di          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_ix          , 
+	m68k_op_eori_32_aw          , 
+	m68k_op_eori_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_ai            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi            , 
+	m68k_op_cas_8_pi7           , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd            , 
+	m68k_op_cas_8_pd7           , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_di            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_ix            , 
+	m68k_op_cas_8_aw            , 
+	m68k_op_cas_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_cmpi_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_ai           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi           , 
+	m68k_op_cmpi_8_pi7          , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd           , 
+	m68k_op_cmpi_8_pd7          , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_di           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_ix           , 
+	m68k_op_cmpi_8_aw           , 
+	m68k_op_cmpi_8_al           , 
+	m68k_op_cmpi_8_pcdi         , 
+	m68k_op_cmpi_8_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_cmpi_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_ai          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pi          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_pd          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_di          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_ix          , 
+	m68k_op_cmpi_16_aw          , 
+	m68k_op_cmpi_16_al          , 
+	m68k_op_cmpi_16_pcdi        , 
+	m68k_op_cmpi_16_pcix        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_cmpi_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_ai          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pi          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_pd          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_di          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_ix          , 
+	m68k_op_cmpi_32_aw          , 
+	m68k_op_cmpi_32_al          , 
+	m68k_op_cmpi_32_pcdi        , 
+	m68k_op_cmpi_32_pcix        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_ai           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pi           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_pd           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_di           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_ix           , 
+	m68k_op_cas_16_aw           , 
+	m68k_op_cas_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cas2_16             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_ai          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi          , 
+	m68k_op_moves_8_pi7         , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd          , 
+	m68k_op_moves_8_pd7         , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_di          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_ix          , 
+	m68k_op_moves_8_aw          , 
+	m68k_op_moves_8_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_ai         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pi         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_pd         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_di         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_ix         , 
+	m68k_op_moves_16_aw         , 
+	m68k_op_moves_16_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_ai         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pi         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_pd         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_di         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_ix         , 
+	m68k_op_moves_32_aw         , 
+	m68k_op_moves_32_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_ai           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pi           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_pd           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_di           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_ix           , 
+	m68k_op_cas_32_aw           , 
+	m68k_op_cas_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cas2_32             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_btst_32_r_d         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_movep_16_er         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_ai         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi         , 
+	m68k_op_btst_8_r_pi7        , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd         , 
+	m68k_op_btst_8_r_pd7        , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_di         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_ix         , 
+	m68k_op_btst_8_r_aw         , 
+	m68k_op_btst_8_r_al         , 
+	m68k_op_btst_8_r_pcdi       , 
+	m68k_op_btst_8_r_pcix       , 
+	m68k_op_btst_8_r_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_bchg_32_r_d         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_movep_32_er         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_ai         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi         , 
+	m68k_op_bchg_8_r_pi7        , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd         , 
+	m68k_op_bchg_8_r_pd7        , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_di         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_ix         , 
+	m68k_op_bchg_8_r_aw         , 
+	m68k_op_bchg_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_bclr_32_r_d         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_movep_16_re         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_ai         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi         , 
+	m68k_op_bclr_8_r_pi7        , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd         , 
+	m68k_op_bclr_8_r_pd7        , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_di         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_ix         , 
+	m68k_op_bclr_8_r_aw         , 
+	m68k_op_bclr_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_bset_32_r_d         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_movep_32_re         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_ai         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi         , 
+	m68k_op_bset_8_r_pi7        , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd         , 
+	m68k_op_bset_8_r_pd7        , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_di         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_ix         , 
+	m68k_op_bset_8_r_aw         , 
+	m68k_op_bset_8_r_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_move_8_aw_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_ai        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi        , 
+	m68k_op_move_8_aw_pi7       , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd        , 
+	m68k_op_move_8_aw_pd7       , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_di        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_ix        , 
+	m68k_op_move_8_aw_aw        , 
+	m68k_op_move_8_aw_al        , 
+	m68k_op_move_8_aw_pcdi      , 
+	m68k_op_move_8_aw_pcix      , 
+	m68k_op_move_8_aw_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_move_8_al_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_ai        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi        , 
+	m68k_op_move_8_al_pi7       , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd        , 
+	m68k_op_move_8_al_pd7       , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_di        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_ix        , 
+	m68k_op_move_8_al_aw        , 
+	m68k_op_move_8_al_al        , 
+	m68k_op_move_8_al_pcdi      , 
+	m68k_op_move_8_al_pcix      , 
+	m68k_op_move_8_al_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_aw        , 
+	m68k_op_move_8_pi_al        , 
+	m68k_op_move_8_pi_pcdi      , 
+	m68k_op_move_8_pi_pcix      , 
+	m68k_op_move_8_pi_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
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+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
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+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
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+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
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+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
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+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
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+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
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+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
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+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_move_8_pi_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi_ai        , 
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+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
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+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_ai        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi        , 
+	m68k_op_move_8_pi_pi7       , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd        , 
+	m68k_op_move_8_pi_pd7       , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
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+	m68k_op_move_8_pi_di        , 
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+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_di        , 
+	m68k_op_move_8_pi_ix        , 
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+	m68k_op_move_8_pi_ix        , 
+	m68k_op_move_8_pi_ix        , 
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+	m68k_op_move_8_pi_aw        , 
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+	m68k_op_illegal, 
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+	m68k_op_illegal, 
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+	m68k_op_move_8_pd_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd_ai        , 
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+	m68k_op_move_8_pd_ai        , 
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+	m68k_op_move_8_pd_ai        , 
+	m68k_op_move_8_pd_pi        , 
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+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi        , 
+	m68k_op_move_8_pd_pi7       , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd        , 
+	m68k_op_move_8_pd_pd7       , 
+	m68k_op_move_8_pd_di        , 
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+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_di        , 
+	m68k_op_move_8_pd_ix        , 
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+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_ix        , 
+	m68k_op_move_8_pd_aw        , 
+	m68k_op_move_8_pd_al        , 
+	m68k_op_move_8_pd_pcdi      , 
+	m68k_op_move_8_pd_pcix      , 
+	m68k_op_move_8_pd_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_move_8_d_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_ai         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi         , 
+	m68k_op_move_8_d_pi7        , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd         , 
+	m68k_op_move_8_d_pd7        , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_di         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_ix         , 
+	m68k_op_move_8_d_aw         , 
+	m68k_op_move_8_d_al         , 
+	m68k_op_move_8_d_pcdi       , 
+	m68k_op_move_8_d_pcix       , 
+	m68k_op_move_8_d_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_move_8_ai_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_ai        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi        , 
+	m68k_op_move_8_ai_pi7       , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd        , 
+	m68k_op_move_8_ai_pd7       , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_di        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_ix        , 
+	m68k_op_move_8_ai_aw        , 
+	m68k_op_move_8_ai_al        , 
+	m68k_op_move_8_ai_pcdi      , 
+	m68k_op_move_8_ai_pcix      , 
+	m68k_op_move_8_ai_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_move_8_pi7_d        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_ai       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi       , 
+	m68k_op_move_8_pi7_pi7      , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd       , 
+	m68k_op_move_8_pi7_pd7      , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_di       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_ix       , 
+	m68k_op_move_8_pi7_aw       , 
+	m68k_op_move_8_pi7_al       , 
+	m68k_op_move_8_pi7_pcdi     , 
+	m68k_op_move_8_pi7_pcix     , 
+	m68k_op_move_8_pi7_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_move_8_pd7_d        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_ai       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi       , 
+	m68k_op_move_8_pd7_pi7      , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd       , 
+	m68k_op_move_8_pd7_pd7      , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_di       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_ix       , 
+	m68k_op_move_8_pd7_aw       , 
+	m68k_op_move_8_pd7_al       , 
+	m68k_op_move_8_pd7_pcdi     , 
+	m68k_op_move_8_pd7_pcix     , 
+	m68k_op_move_8_pd7_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_move_8_di_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_ai        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi        , 
+	m68k_op_move_8_di_pi7       , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd        , 
+	m68k_op_move_8_di_pd7       , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_di        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_ix        , 
+	m68k_op_move_8_di_aw        , 
+	m68k_op_move_8_di_al        , 
+	m68k_op_move_8_di_pcdi      , 
+	m68k_op_move_8_di_pcix      , 
+	m68k_op_move_8_di_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_move_8_ix_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_ai        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi        , 
+	m68k_op_move_8_ix_pi7       , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd        , 
+	m68k_op_move_8_ix_pd7       , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_di        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_ix        , 
+	m68k_op_move_8_ix_aw        , 
+	m68k_op_move_8_ix_al        , 
+	m68k_op_move_8_ix_pcdi      , 
+	m68k_op_move_8_ix_pcix      , 
+	m68k_op_move_8_ix_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_d        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_a        , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_ai       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pi       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_pd       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_di       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_ix       , 
+	m68k_op_move_32_aw_aw       , 
+	m68k_op_move_32_aw_al       , 
+	m68k_op_move_32_aw_pcdi     , 
+	m68k_op_move_32_aw_pcix     , 
+	m68k_op_move_32_aw_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_d        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_a        , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_ai       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pi       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_pd       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_di       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_ix       , 
+	m68k_op_move_32_al_aw       , 
+	m68k_op_move_32_al_al       , 
+	m68k_op_move_32_al_pcdi     , 
+	m68k_op_move_32_al_pcix     , 
+	m68k_op_move_32_al_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_d         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_a         , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_ai        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pi        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_pd        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_di        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_ix        , 
+	m68k_op_move_32_d_aw        , 
+	m68k_op_move_32_d_al        , 
+	m68k_op_move_32_d_pcdi      , 
+	m68k_op_move_32_d_pcix      , 
+	m68k_op_move_32_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_d          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_a          , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_ai         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pi         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_pd         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_di         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_ix         , 
+	m68k_op_movea_32_aw         , 
+	m68k_op_movea_32_al         , 
+	m68k_op_movea_32_pcdi       , 
+	m68k_op_movea_32_pcix       , 
+	m68k_op_movea_32_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_d        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_a        , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_ai       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pi       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_pd       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_di       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_ix       , 
+	m68k_op_move_32_ai_aw       , 
+	m68k_op_move_32_ai_al       , 
+	m68k_op_move_32_ai_pcdi     , 
+	m68k_op_move_32_ai_pcix     , 
+	m68k_op_move_32_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_d        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_a        , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_ai       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pi       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_pd       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_di       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_ix       , 
+	m68k_op_move_32_pi_aw       , 
+	m68k_op_move_32_pi_al       , 
+	m68k_op_move_32_pi_pcdi     , 
+	m68k_op_move_32_pi_pcix     , 
+	m68k_op_move_32_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_d        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_a        , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_ai       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pi       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_pd       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_di       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_ix       , 
+	m68k_op_move_32_pd_aw       , 
+	m68k_op_move_32_pd_al       , 
+	m68k_op_move_32_pd_pcdi     , 
+	m68k_op_move_32_pd_pcix     , 
+	m68k_op_move_32_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_d        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_a        , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_ai       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pi       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_pd       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_di       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_ix       , 
+	m68k_op_move_32_di_aw       , 
+	m68k_op_move_32_di_al       , 
+	m68k_op_move_32_di_pcdi     , 
+	m68k_op_move_32_di_pcix     , 
+	m68k_op_move_32_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_d        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_a        , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_ai       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pi       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_pd       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_di       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_ix       , 
+	m68k_op_move_32_ix_aw       , 
+	m68k_op_move_32_ix_al       , 
+	m68k_op_move_32_ix_pcdi     , 
+	m68k_op_move_32_ix_pcix     , 
+	m68k_op_move_32_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_d        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_a        , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_ai       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pi       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_pd       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_di       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_ix       , 
+	m68k_op_move_16_aw_aw       , 
+	m68k_op_move_16_aw_al       , 
+	m68k_op_move_16_aw_pcdi     , 
+	m68k_op_move_16_aw_pcix     , 
+	m68k_op_move_16_aw_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_d        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_a        , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_ai       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pi       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_pd       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_di       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_ix       , 
+	m68k_op_move_16_al_aw       , 
+	m68k_op_move_16_al_al       , 
+	m68k_op_move_16_al_pcdi     , 
+	m68k_op_move_16_al_pcix     , 
+	m68k_op_move_16_al_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
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+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
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+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
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+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
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+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
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+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
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+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
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+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
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+	m68k_op_move_16_ai_pcix     , 
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+	m68k_op_illegal, 
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+	m68k_op_illegal, 
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+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
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+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
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+	m68k_op_move_16_pi_aw       , 
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+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
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+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
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+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
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+	m68k_op_move_16_pd_ai       , 
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+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
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+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
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+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
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+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
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+	m68k_op_move_16_di_d        , 
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+	m68k_op_move_16_di_pd       , 
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+	m68k_op_move_16_di_ix       , 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
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+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
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+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_d         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_a         , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_ai        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pi        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_pd        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_di        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_ix        , 
+	m68k_op_move_16_d_aw        , 
+	m68k_op_move_16_d_al        , 
+	m68k_op_move_16_d_pcdi      , 
+	m68k_op_move_16_d_pcix      , 
+	m68k_op_move_16_d_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_d          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_a          , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_ai         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pi         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_pd         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_di         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_ix         , 
+	m68k_op_movea_16_aw         , 
+	m68k_op_movea_16_al         , 
+	m68k_op_movea_16_pcdi       , 
+	m68k_op_movea_16_pcix       , 
+	m68k_op_movea_16_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_d        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_a        , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_ai       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pi       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_pd       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_di       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_ix       , 
+	m68k_op_move_16_ai_aw       , 
+	m68k_op_move_16_ai_al       , 
+	m68k_op_move_16_ai_pcdi     , 
+	m68k_op_move_16_ai_pcix     , 
+	m68k_op_move_16_ai_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_d        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_a        , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_ai       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pi       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_pd       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_di       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_ix       , 
+	m68k_op_move_16_pi_aw       , 
+	m68k_op_move_16_pi_al       , 
+	m68k_op_move_16_pi_pcdi     , 
+	m68k_op_move_16_pi_pcix     , 
+	m68k_op_move_16_pi_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_d        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_a        , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_ai       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pi       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_pd       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_di       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_ix       , 
+	m68k_op_move_16_pd_aw       , 
+	m68k_op_move_16_pd_al       , 
+	m68k_op_move_16_pd_pcdi     , 
+	m68k_op_move_16_pd_pcix     , 
+	m68k_op_move_16_pd_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_d        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_a        , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_ai       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pi       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_pd       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_di       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_ix       , 
+	m68k_op_move_16_di_aw       , 
+	m68k_op_move_16_di_al       , 
+	m68k_op_move_16_di_pcdi     , 
+	m68k_op_move_16_di_pcix     , 
+	m68k_op_move_16_di_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_d        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_a        , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_ai       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pi       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_pd       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_di       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_ix       , 
+	m68k_op_move_16_ix_aw       , 
+	m68k_op_move_16_ix_al       , 
+	m68k_op_move_16_ix_pcdi     , 
+	m68k_op_move_16_ix_pcix     , 
+	m68k_op_move_16_ix_i        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_negx_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_ai           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi           , 
+	m68k_op_negx_8_pi7          , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd           , 
+	m68k_op_negx_8_pd7          , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_di           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_ix           , 
+	m68k_op_negx_8_aw           , 
+	m68k_op_negx_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_negx_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_ai          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pi          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_pd          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_di          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_ix          , 
+	m68k_op_negx_16_aw          , 
+	m68k_op_negx_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_negx_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_ai          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pi          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_pd          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_di          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_ix          , 
+	m68k_op_negx_32_aw          , 
+	m68k_op_negx_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_move_16_frs_d       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_ai      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pi      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_pd      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_di      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_ix      , 
+	m68k_op_move_16_frs_aw      , 
+	m68k_op_move_16_frs_al      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_clr_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_ai            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi            , 
+	m68k_op_clr_8_pi7           , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd            , 
+	m68k_op_clr_8_pd7           , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_di            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_ix            , 
+	m68k_op_clr_8_aw            , 
+	m68k_op_clr_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_clr_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_ai           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pi           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_pd           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_di           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_ix           , 
+	m68k_op_clr_16_aw           , 
+	m68k_op_clr_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_clr_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_ai           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pi           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_pd           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_di           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_ix           , 
+	m68k_op_clr_32_aw           , 
+	m68k_op_clr_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_move_16_frc_d       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_ai      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pi      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_pd      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_di      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_ix      , 
+	m68k_op_move_16_frc_aw      , 
+	m68k_op_move_16_frc_al      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_neg_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_ai            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi            , 
+	m68k_op_neg_8_pi7           , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd            , 
+	m68k_op_neg_8_pd7           , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_di            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_ix            , 
+	m68k_op_neg_8_aw            , 
+	m68k_op_neg_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_neg_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_ai           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pi           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_pd           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_di           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_ix           , 
+	m68k_op_neg_16_aw           , 
+	m68k_op_neg_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_neg_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_ai           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pi           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_pd           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_di           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_ix           , 
+	m68k_op_neg_32_aw           , 
+	m68k_op_neg_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_move_16_toc_d       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_ai      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pi      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_pd      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_di      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_ix      , 
+	m68k_op_move_16_toc_aw      , 
+	m68k_op_move_16_toc_al      , 
+	m68k_op_move_16_toc_pcdi    , 
+	m68k_op_move_16_toc_pcix    , 
+	m68k_op_move_16_toc_i       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_not_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_ai            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi            , 
+	m68k_op_not_8_pi7           , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd            , 
+	m68k_op_not_8_pd7           , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_di            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_ix            , 
+	m68k_op_not_8_aw            , 
+	m68k_op_not_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_not_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_ai           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pi           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_pd           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_di           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_ix           , 
+	m68k_op_not_16_aw           , 
+	m68k_op_not_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_not_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_ai           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pi           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_pd           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_di           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_ix           , 
+	m68k_op_not_32_aw           , 
+	m68k_op_not_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_move_16_tos_d       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_ai      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pi      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_pd      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_di      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_ix      , 
+	m68k_op_move_16_tos_aw      , 
+	m68k_op_move_16_tos_al      , 
+	m68k_op_move_16_tos_pcdi    , 
+	m68k_op_move_16_tos_pcix    , 
+	m68k_op_move_16_tos_i       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_nbcd_8_d            , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32             , 
+	m68k_op_link_32_a7          , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_ai           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi           , 
+	m68k_op_nbcd_8_pi7          , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd           , 
+	m68k_op_nbcd_8_pd7          , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_di           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_ix           , 
+	m68k_op_nbcd_8_aw           , 
+	m68k_op_nbcd_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_swap_32             , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_bkpt                , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_pea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_di           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_ix           , 
+	m68k_op_pea_32_aw           , 
+	m68k_op_pea_32_al           , 
+	m68k_op_pea_32_pcdi         , 
+	m68k_op_pea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_ext_16              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_movem_16_re_ai      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_pd      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_di      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_ix      , 
+	m68k_op_movem_16_re_aw      , 
+	m68k_op_movem_16_re_al      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_ext_32              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_movem_32_re_ai      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_pd      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_di      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_ix      , 
+	m68k_op_movem_32_re_aw      , 
+	m68k_op_movem_32_re_al      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_extb_32             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_tst_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_ai            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi            , 
+	m68k_op_tst_8_pi7           , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd            , 
+	m68k_op_tst_8_pd7           , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_di            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_ix            , 
+	m68k_op_tst_8_aw            , 
+	m68k_op_tst_8_al            , 
+	m68k_op_tst_8_pcdi          , 
+	m68k_op_tst_8_pcix          , 
+	m68k_op_tst_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_d            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_a            , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_ai           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pi           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_pd           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_di           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_ix           , 
+	m68k_op_tst_16_aw           , 
+	m68k_op_tst_16_al           , 
+	m68k_op_tst_16_pcdi         , 
+	m68k_op_tst_16_pcix         , 
+	m68k_op_tst_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_d            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_a            , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_ai           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pi           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_pd           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_di           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_ix           , 
+	m68k_op_tst_32_aw           , 
+	m68k_op_tst_32_al           , 
+	m68k_op_tst_32_pcdi         , 
+	m68k_op_tst_32_pcix         , 
+	m68k_op_tst_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_tas_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_ai            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi            , 
+	m68k_op_tas_8_pi7           , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd            , 
+	m68k_op_tas_8_pd7           , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_di            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_ix            , 
+	m68k_op_tas_8_aw            , 
+	m68k_op_tas_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_mull_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_ai          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pi          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_pd          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_di          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_ix          , 
+	m68k_op_mull_32_aw          , 
+	m68k_op_mull_32_al          , 
+	m68k_op_mull_32_pcdi        , 
+	m68k_op_mull_32_pcix        , 
+	m68k_op_mull_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_divl_32_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_ai          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pi          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_pd          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_di          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_ix          , 
+	m68k_op_divl_32_aw          , 
+	m68k_op_divl_32_al          , 
+	m68k_op_divl_32_pcdi        , 
+	m68k_op_divl_32_pcix        , 
+	m68k_op_divl_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_ai      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_movem_16_er_pi      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_di      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_ix      , 
+	m68k_op_movem_16_er_aw      , 
+	m68k_op_movem_16_er_al      , 
+	m68k_op_movem_16_er_pcdi    , 
+	m68k_op_movem_16_er_pcix    , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_ai      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_movem_32_er_pi      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_di      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_ix      , 
+	m68k_op_movem_32_er_aw      , 
+	m68k_op_movem_32_er_al      , 
+	m68k_op_movem_32_er_pcdi    , 
+	m68k_op_movem_32_er_pcix    , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_trap                , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16             , 
+	m68k_op_link_16_a7          , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32             , 
+	m68k_op_unlk_32_a7          , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_tou         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_move_32_fru         , 
+	m68k_op_reset               , 
+	m68k_op_nop                 , 
+	m68k_op_stop                , 
+	m68k_op_rte_32              , 
+	m68k_op_rtd_32              , 
+	m68k_op_rts_32              , 
+	m68k_op_trapv               , 
+	m68k_op_rtr_32              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_movec_32_cr         , 
+	m68k_op_movec_32_rc         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_jsr_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_di           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_ix           , 
+	m68k_op_jsr_32_aw           , 
+	m68k_op_jsr_32_al           , 
+	m68k_op_jsr_32_pcdi         , 
+	m68k_op_jsr_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_jmp_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_di           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_ix           , 
+	m68k_op_jmp_32_aw           , 
+	m68k_op_jmp_32_al           , 
+	m68k_op_jmp_32_pcdi         , 
+	m68k_op_jmp_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_chk_32_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_ai           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pi           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_pd           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_di           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_ix           , 
+	m68k_op_chk_32_aw           , 
+	m68k_op_chk_32_al           , 
+	m68k_op_chk_32_pcdi         , 
+	m68k_op_chk_32_pcix         , 
+	m68k_op_chk_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_chk_16_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_ai           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pi           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_pd           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_di           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_ix           , 
+	m68k_op_chk_16_aw           , 
+	m68k_op_chk_16_al           , 
+	m68k_op_chk_16_pcdi         , 
+	m68k_op_chk_16_pcix         , 
+	m68k_op_chk_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_lea_32_ai           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_di           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_ix           , 
+	m68k_op_lea_32_aw           , 
+	m68k_op_lea_32_al           , 
+	m68k_op_lea_32_pcdi         , 
+	m68k_op_lea_32_pcix         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_st_8_d              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_dbt_16              , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_ai             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi             , 
+	m68k_op_st_8_pi7            , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd             , 
+	m68k_op_st_8_pd7            , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_di             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_ix             , 
+	m68k_op_st_8_aw             , 
+	m68k_op_st_8_al             , 
+	m68k_op_trapt_16            , 
+	m68k_op_trapt_32            , 
+	m68k_op_trapt               , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_sf_8_d              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_dbf_16              , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_ai             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi             , 
+	m68k_op_sf_8_pi7            , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd             , 
+	m68k_op_sf_8_pd7            , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_di             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_ix             , 
+	m68k_op_sf_8_aw             , 
+	m68k_op_sf_8_al             , 
+	m68k_op_trapf_16            , 
+	m68k_op_trapf_32            , 
+	m68k_op_trapf               , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_shi_8_d             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_dbhi_16             , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_ai            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi            , 
+	m68k_op_shi_8_pi7           , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd            , 
+	m68k_op_shi_8_pd7           , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_di            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_ix            , 
+	m68k_op_shi_8_aw            , 
+	m68k_op_shi_8_al            , 
+	m68k_op_traphi_16           , 
+	m68k_op_traphi_32           , 
+	m68k_op_traphi              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_sls_8_d             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_dbls_16             , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_ai            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi            , 
+	m68k_op_sls_8_pi7           , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd            , 
+	m68k_op_sls_8_pd7           , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_di            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_ix            , 
+	m68k_op_sls_8_aw            , 
+	m68k_op_sls_8_al            , 
+	m68k_op_trapls_16           , 
+	m68k_op_trapls_32           , 
+	m68k_op_trapls              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_scc_8_d             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_dbcc_16             , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_ai            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi            , 
+	m68k_op_scc_8_pi7           , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd            , 
+	m68k_op_scc_8_pd7           , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_di            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_ix            , 
+	m68k_op_scc_8_aw            , 
+	m68k_op_scc_8_al            , 
+	m68k_op_trapcc_16           , 
+	m68k_op_trapcc_32           , 
+	m68k_op_trapcc              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_scs_8_d             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_dbcs_16             , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_ai            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi            , 
+	m68k_op_scs_8_pi7           , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd            , 
+	m68k_op_scs_8_pd7           , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_di            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_ix            , 
+	m68k_op_scs_8_aw            , 
+	m68k_op_scs_8_al            , 
+	m68k_op_trapcs_16           , 
+	m68k_op_trapcs_32           , 
+	m68k_op_trapcs              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_sne_8_d             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_dbne_16             , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_ai            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi            , 
+	m68k_op_sne_8_pi7           , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd            , 
+	m68k_op_sne_8_pd7           , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_di            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_ix            , 
+	m68k_op_sne_8_aw            , 
+	m68k_op_sne_8_al            , 
+	m68k_op_trapne_16           , 
+	m68k_op_trapne_32           , 
+	m68k_op_trapne              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_seq_8_d             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_dbeq_16             , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_ai            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi            , 
+	m68k_op_seq_8_pi7           , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd            , 
+	m68k_op_seq_8_pd7           , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_di            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_ix            , 
+	m68k_op_seq_8_aw            , 
+	m68k_op_seq_8_al            , 
+	m68k_op_trapeq_16           , 
+	m68k_op_trapeq_32           , 
+	m68k_op_trapeq              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_svc_8_d             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_dbvc_16             , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_ai            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi            , 
+	m68k_op_svc_8_pi7           , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd            , 
+	m68k_op_svc_8_pd7           , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_di            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_ix            , 
+	m68k_op_svc_8_aw            , 
+	m68k_op_svc_8_al            , 
+	m68k_op_trapvc_16           , 
+	m68k_op_trapvc_32           , 
+	m68k_op_trapvc              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_svs_8_d             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_dbvs_16             , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_ai            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi            , 
+	m68k_op_svs_8_pi7           , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd            , 
+	m68k_op_svs_8_pd7           , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_di            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_ix            , 
+	m68k_op_svs_8_aw            , 
+	m68k_op_svs_8_al            , 
+	m68k_op_trapvs_16           , 
+	m68k_op_trapvs_32           , 
+	m68k_op_trapvs              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_spl_8_d             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_dbpl_16             , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_ai            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi            , 
+	m68k_op_spl_8_pi7           , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd            , 
+	m68k_op_spl_8_pd7           , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_di            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_ix            , 
+	m68k_op_spl_8_aw            , 
+	m68k_op_spl_8_al            , 
+	m68k_op_trappl_16           , 
+	m68k_op_trappl_32           , 
+	m68k_op_trappl              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_smi_8_d             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_dbmi_16             , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_ai            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi            , 
+	m68k_op_smi_8_pi7           , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd            , 
+	m68k_op_smi_8_pd7           , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_di            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_ix            , 
+	m68k_op_smi_8_aw            , 
+	m68k_op_smi_8_al            , 
+	m68k_op_trapmi_16           , 
+	m68k_op_trapmi_32           , 
+	m68k_op_trapmi              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_sge_8_d             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_dbge_16             , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_ai            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi            , 
+	m68k_op_sge_8_pi7           , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd            , 
+	m68k_op_sge_8_pd7           , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_di            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_ix            , 
+	m68k_op_sge_8_aw            , 
+	m68k_op_sge_8_al            , 
+	m68k_op_trapge_16           , 
+	m68k_op_trapge_32           , 
+	m68k_op_trapge              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_slt_8_d             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_dblt_16             , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_ai            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi            , 
+	m68k_op_slt_8_pi7           , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd            , 
+	m68k_op_slt_8_pd7           , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_di            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_ix            , 
+	m68k_op_slt_8_aw            , 
+	m68k_op_slt_8_al            , 
+	m68k_op_traplt_16           , 
+	m68k_op_traplt_32           , 
+	m68k_op_traplt              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_addq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_ai           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi           , 
+	m68k_op_addq_8_pi7          , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd           , 
+	m68k_op_addq_8_pd7          , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_di           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_ix           , 
+	m68k_op_addq_8_aw           , 
+	m68k_op_addq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_d           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_a           , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_ai          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pi          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_pd          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_di          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_ix          , 
+	m68k_op_addq_16_aw          , 
+	m68k_op_addq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_d           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_a           , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_ai          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pi          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_pd          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_di          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_ix          , 
+	m68k_op_addq_32_aw          , 
+	m68k_op_addq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_sgt_8_d             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_dbgt_16             , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_ai            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi            , 
+	m68k_op_sgt_8_pi7           , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd            , 
+	m68k_op_sgt_8_pd7           , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_di            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_ix            , 
+	m68k_op_sgt_8_aw            , 
+	m68k_op_sgt_8_al            , 
+	m68k_op_trapgt_16           , 
+	m68k_op_trapgt_32           , 
+	m68k_op_trapgt              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_subq_8_d            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_ai           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi           , 
+	m68k_op_subq_8_pi7          , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd           , 
+	m68k_op_subq_8_pd7          , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_di           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_ix           , 
+	m68k_op_subq_8_aw           , 
+	m68k_op_subq_8_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_d           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_a           , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_ai          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pi          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_pd          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_di          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_ix          , 
+	m68k_op_subq_16_aw          , 
+	m68k_op_subq_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_d           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_a           , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_ai          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pi          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_pd          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_di          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_ix          , 
+	m68k_op_subq_32_aw          , 
+	m68k_op_subq_32_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_sle_8_d             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_dble_16             , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_ai            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi            , 
+	m68k_op_sle_8_pi7           , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd            , 
+	m68k_op_sle_8_pd7           , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_di            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_ix            , 
+	m68k_op_sle_8_aw            , 
+	m68k_op_sle_8_al            , 
+	m68k_op_traple_16           , 
+	m68k_op_traple_32           , 
+	m68k_op_traple              , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bra_16              , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_8               , 
+	m68k_op_bra_32              , 
+	m68k_op_bsr_16              , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
+	m68k_op_bsr_8               , 
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+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_8               , 
+	m68k_op_ble_32              , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_illegal, 
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+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
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+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_moveq_32            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm           , 
+	m68k_op_sbcd_8_mm_ay7       , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm          , 
+	m68k_op_pack_16_mm_ay7      , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm          , 
+	m68k_op_unpk_16_mm_ay7      , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_or_8_er_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_ai          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi          , 
+	m68k_op_or_8_er_pi7         , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd          , 
+	m68k_op_or_8_er_pd7         , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_di          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_ix          , 
+	m68k_op_or_8_er_aw          , 
+	m68k_op_or_8_er_al          , 
+	m68k_op_or_8_er_pcdi        , 
+	m68k_op_or_8_er_pcix        , 
+	m68k_op_or_8_er_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_or_16_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_ai         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pi         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_pd         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_di         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_ix         , 
+	m68k_op_or_16_er_aw         , 
+	m68k_op_or_16_er_al         , 
+	m68k_op_or_16_er_pcdi       , 
+	m68k_op_or_16_er_pcix       , 
+	m68k_op_or_16_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_or_32_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_ai         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pi         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_pd         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_di         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_ix         , 
+	m68k_op_or_32_er_aw         , 
+	m68k_op_or_32_er_al         , 
+	m68k_op_or_32_er_pcdi       , 
+	m68k_op_or_32_er_pcix       , 
+	m68k_op_or_32_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_divu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_ai          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pi          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_pd          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_di          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_ix          , 
+	m68k_op_divu_16_aw          , 
+	m68k_op_divu_16_al          , 
+	m68k_op_divu_16_pcdi        , 
+	m68k_op_divu_16_pcix        , 
+	m68k_op_divu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_rr           , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_ax7       , 
+	m68k_op_sbcd_8_mm_axy7      , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_ai          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi          , 
+	m68k_op_or_8_re_pi7         , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd          , 
+	m68k_op_or_8_re_pd7         , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_di          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_ix          , 
+	m68k_op_or_8_re_aw          , 
+	m68k_op_or_8_re_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_rr          , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_ax7      , 
+	m68k_op_pack_16_mm_axy7     , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_ai         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pi         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_pd         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_di         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_ix         , 
+	m68k_op_or_16_re_aw         , 
+	m68k_op_or_16_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_rr          , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_ax7      , 
+	m68k_op_unpk_16_mm_axy7     , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_ai         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pi         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_pd         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_di         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_ix         , 
+	m68k_op_or_32_re_aw         , 
+	m68k_op_or_32_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_divs_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_ai          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pi          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_pd          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_di          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_ix          , 
+	m68k_op_divs_16_aw          , 
+	m68k_op_divs_16_al          , 
+	m68k_op_divs_16_pcdi        , 
+	m68k_op_divs_16_pcix        , 
+	m68k_op_divs_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm           , 
+	m68k_op_subx_8_mm_ay7       , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_sub_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_ai         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi         , 
+	m68k_op_sub_8_er_pi7        , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd         , 
+	m68k_op_sub_8_er_pd7        , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_di         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_ix         , 
+	m68k_op_sub_8_er_aw         , 
+	m68k_op_sub_8_er_al         , 
+	m68k_op_sub_8_er_pcdi       , 
+	m68k_op_sub_8_er_pcix       , 
+	m68k_op_sub_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_d         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_a         , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_ai        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pi        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_pd        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_di        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_ix        , 
+	m68k_op_sub_16_er_aw        , 
+	m68k_op_sub_16_er_al        , 
+	m68k_op_sub_16_er_pcdi      , 
+	m68k_op_sub_16_er_pcix      , 
+	m68k_op_sub_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_d         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_a         , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_ai        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pi        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_pd        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_di        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_ix        , 
+	m68k_op_sub_32_er_aw        , 
+	m68k_op_sub_32_er_al        , 
+	m68k_op_sub_32_er_pcdi      , 
+	m68k_op_sub_32_er_pcix      , 
+	m68k_op_sub_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_d           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_a           , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_ai          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pi          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_pd          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_di          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_ix          , 
+	m68k_op_suba_16_aw          , 
+	m68k_op_suba_16_al          , 
+	m68k_op_suba_16_pcdi        , 
+	m68k_op_suba_16_pcix        , 
+	m68k_op_suba_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_rr           , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_ax7       , 
+	m68k_op_subx_8_mm_axy7      , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_ai         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi         , 
+	m68k_op_sub_8_re_pi7        , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd         , 
+	m68k_op_sub_8_re_pd7        , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_di         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_ix         , 
+	m68k_op_sub_8_re_aw         , 
+	m68k_op_sub_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_rr          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_subx_16_mm          , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_ai        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pi        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_pd        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_di        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_ix        , 
+	m68k_op_sub_16_re_aw        , 
+	m68k_op_sub_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_rr          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_subx_32_mm          , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_ai        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pi        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_pd        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_di        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_ix        , 
+	m68k_op_sub_32_re_aw        , 
+	m68k_op_sub_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_d           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_a           , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_ai          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pi          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_pd          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_di          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_ix          , 
+	m68k_op_suba_32_aw          , 
+	m68k_op_suba_32_al          , 
+	m68k_op_suba_32_pcdi        , 
+	m68k_op_suba_32_pcix        , 
+	m68k_op_suba_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
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+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_1010                , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8              , 
+	m68k_op_cmpm_8_ay7          , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_cmp_8_d             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_ai            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi            , 
+	m68k_op_cmp_8_pi7           , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd            , 
+	m68k_op_cmp_8_pd7           , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_di            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_ix            , 
+	m68k_op_cmp_8_aw            , 
+	m68k_op_cmp_8_al            , 
+	m68k_op_cmp_8_pcdi          , 
+	m68k_op_cmp_8_pcix          , 
+	m68k_op_cmp_8_i             , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_d            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_a            , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_ai           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pi           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_pd           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_di           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_ix           , 
+	m68k_op_cmp_16_aw           , 
+	m68k_op_cmp_16_al           , 
+	m68k_op_cmp_16_pcdi         , 
+	m68k_op_cmp_16_pcix         , 
+	m68k_op_cmp_16_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_d            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_a            , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_ai           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pi           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_pd           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_di           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_ix           , 
+	m68k_op_cmp_32_aw           , 
+	m68k_op_cmp_32_al           , 
+	m68k_op_cmp_32_pcdi         , 
+	m68k_op_cmp_32_pcix         , 
+	m68k_op_cmp_32_i            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_d           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_a           , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_ai          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pi          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_pd          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_di          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_ix          , 
+	m68k_op_cmpa_16_aw          , 
+	m68k_op_cmpa_16_al          , 
+	m68k_op_cmpa_16_pcdi        , 
+	m68k_op_cmpa_16_pcix        , 
+	m68k_op_cmpa_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_eor_8_d             , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_ax7          , 
+	m68k_op_cmpm_8_axy7         , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_ai            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi            , 
+	m68k_op_eor_8_pi7           , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd            , 
+	m68k_op_eor_8_pd7           , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_di            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_ix            , 
+	m68k_op_eor_8_aw            , 
+	m68k_op_eor_8_al            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_eor_16_d            , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_cmpm_16             , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_ai           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pi           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_pd           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_di           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_ix           , 
+	m68k_op_eor_16_aw           , 
+	m68k_op_eor_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_eor_32_d            , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_cmpm_32             , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_ai           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pi           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_pd           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_di           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_ix           , 
+	m68k_op_eor_32_aw           , 
+	m68k_op_eor_32_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_d           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_a           , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_ai          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pi          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_pd          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_di          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_ix          , 
+	m68k_op_cmpa_32_aw          , 
+	m68k_op_cmpa_32_al          , 
+	m68k_op_cmpa_32_pcdi        , 
+	m68k_op_cmpa_32_pcix        , 
+	m68k_op_cmpa_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm           , 
+	m68k_op_abcd_8_mm_ay7       , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_and_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_ai         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi         , 
+	m68k_op_and_8_er_pi7        , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd         , 
+	m68k_op_and_8_er_pd7        , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_di         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_ix         , 
+	m68k_op_and_8_er_aw         , 
+	m68k_op_and_8_er_al         , 
+	m68k_op_and_8_er_pcdi       , 
+	m68k_op_and_8_er_pcix       , 
+	m68k_op_and_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_and_16_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_ai        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pi        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_pd        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_di        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_ix        , 
+	m68k_op_and_16_er_aw        , 
+	m68k_op_and_16_er_al        , 
+	m68k_op_and_16_er_pcdi      , 
+	m68k_op_and_16_er_pcix      , 
+	m68k_op_and_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_and_32_er_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_ai        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pi        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_pd        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_di        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_ix        , 
+	m68k_op_and_32_er_aw        , 
+	m68k_op_and_32_er_al        , 
+	m68k_op_and_32_er_pcdi      , 
+	m68k_op_and_32_er_pcix      , 
+	m68k_op_and_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_mulu_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_ai          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pi          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_pd          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_di          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_ix          , 
+	m68k_op_mulu_16_aw          , 
+	m68k_op_mulu_16_al          , 
+	m68k_op_mulu_16_pcdi        , 
+	m68k_op_mulu_16_pcix        , 
+	m68k_op_mulu_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_rr           , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_ax7       , 
+	m68k_op_abcd_8_mm_axy7      , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_ai         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi         , 
+	m68k_op_and_8_re_pi7        , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd         , 
+	m68k_op_and_8_re_pd7        , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_di         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_ix         , 
+	m68k_op_and_8_re_aw         , 
+	m68k_op_and_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_dd           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_exg_32_aa           , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_ai        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pi        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_pd        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_di        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_ix        , 
+	m68k_op_and_16_re_aw        , 
+	m68k_op_and_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_exg_32_da           , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_ai        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pi        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_pd        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_di        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_ix        , 
+	m68k_op_and_32_re_aw        , 
+	m68k_op_and_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_muls_16_d           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_ai          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pi          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_pd          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_di          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_ix          , 
+	m68k_op_muls_16_aw          , 
+	m68k_op_muls_16_al          , 
+	m68k_op_muls_16_pcdi        , 
+	m68k_op_muls_16_pcix        , 
+	m68k_op_muls_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm           , 
+	m68k_op_addx_8_mm_ay7       , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_add_8_er_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_ai         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi         , 
+	m68k_op_add_8_er_pi7        , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd         , 
+	m68k_op_add_8_er_pd7        , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_di         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_ix         , 
+	m68k_op_add_8_er_aw         , 
+	m68k_op_add_8_er_al         , 
+	m68k_op_add_8_er_pcdi       , 
+	m68k_op_add_8_er_pcix       , 
+	m68k_op_add_8_er_i          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_d         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_a         , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_ai        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pi        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_pd        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_di        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_ix        , 
+	m68k_op_add_16_er_aw        , 
+	m68k_op_add_16_er_al        , 
+	m68k_op_add_16_er_pcdi      , 
+	m68k_op_add_16_er_pcix      , 
+	m68k_op_add_16_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_d         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_a         , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_ai        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pi        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_pd        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_di        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_ix        , 
+	m68k_op_add_32_er_aw        , 
+	m68k_op_add_32_er_al        , 
+	m68k_op_add_32_er_pcdi      , 
+	m68k_op_add_32_er_pcix      , 
+	m68k_op_add_32_er_i         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_d           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_a           , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_ai          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pi          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_pd          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_di          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_ix          , 
+	m68k_op_adda_16_aw          , 
+	m68k_op_adda_16_al          , 
+	m68k_op_adda_16_pcdi        , 
+	m68k_op_adda_16_pcix        , 
+	m68k_op_adda_16_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_rr           , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_ax7       , 
+	m68k_op_addx_8_mm_axy7      , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_ai         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi         , 
+	m68k_op_add_8_re_pi7        , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd         , 
+	m68k_op_add_8_re_pd7        , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_di         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_ix         , 
+	m68k_op_add_8_re_aw         , 
+	m68k_op_add_8_re_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_rr          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_addx_16_mm          , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_ai        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pi        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_pd        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_di        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_ix        , 
+	m68k_op_add_16_re_aw        , 
+	m68k_op_add_16_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_rr          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_addx_32_mm          , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_ai        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pi        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_pd        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_di        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_ix        , 
+	m68k_op_add_32_re_aw        , 
+	m68k_op_add_32_re_al        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_d           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_a           , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_ai          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pi          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_pd          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_di          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_ix          , 
+	m68k_op_adda_32_aw          , 
+	m68k_op_adda_32_al          , 
+	m68k_op_adda_32_pcdi        , 
+	m68k_op_adda_32_pcix        , 
+	m68k_op_adda_32_i           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_ai           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pi           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_pd           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_di           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_ix           , 
+	m68k_op_asr_16_aw           , 
+	m68k_op_asr_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_ai           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pi           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_pd           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_di           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_ix           , 
+	m68k_op_asl_16_aw           , 
+	m68k_op_asl_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_ai           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pi           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_pd           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_di           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_ix           , 
+	m68k_op_lsr_16_aw           , 
+	m68k_op_lsr_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_ai           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pi           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_pd           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_di           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_ix           , 
+	m68k_op_lsl_16_aw           , 
+	m68k_op_lsl_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_ai          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pi          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_pd          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_di          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_ix          , 
+	m68k_op_roxr_16_aw          , 
+	m68k_op_roxr_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_ai          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pi          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_pd          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_di          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_ix          , 
+	m68k_op_roxl_16_aw          , 
+	m68k_op_roxl_16_al          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_ai           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pi           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_pd           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_di           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_ix           , 
+	m68k_op_ror_16_aw           , 
+	m68k_op_ror_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_ai           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pi           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_pd           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_di           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_ix           , 
+	m68k_op_rol_16_aw           , 
+	m68k_op_rol_16_al           , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_bftst_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_bftst_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_di         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_ix         , 
+	m68k_op_bftst_32_aw         , 
+	m68k_op_bftst_32_al         , 
+	m68k_op_bftst_32_pcdi       , 
+	m68k_op_bftst_32_pcix       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_bfextu_32_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_bfextu_32_ai        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_di        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_ix        , 
+	m68k_op_bfextu_32_aw        , 
+	m68k_op_bfextu_32_al        , 
+	m68k_op_bfextu_32_pcdi      , 
+	m68k_op_bfextu_32_pcix      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_bfchg_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_bfchg_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_di         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_ix         , 
+	m68k_op_bfchg_32_aw         , 
+	m68k_op_bfchg_32_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_bfexts_32_d         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_bfexts_32_ai        , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_di        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_ix        , 
+	m68k_op_bfexts_32_aw        , 
+	m68k_op_bfexts_32_al        , 
+	m68k_op_bfexts_32_pcdi      , 
+	m68k_op_bfexts_32_pcix      , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_bfclr_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_bfclr_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_di         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_ix         , 
+	m68k_op_bfclr_32_aw         , 
+	m68k_op_bfclr_32_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_bfffo_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_bfffo_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_di         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_ix         , 
+	m68k_op_bfffo_32_aw         , 
+	m68k_op_bfffo_32_al         , 
+	m68k_op_bfffo_32_pcdi       , 
+	m68k_op_bfffo_32_pcix       , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_asr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_lsr_8_s             , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_roxr_8_s            , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_ror_8_s             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_asr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_lsr_8_r             , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_roxr_8_r            , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_ror_8_r             , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_asr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_lsr_16_s            , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_roxr_16_s           , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_ror_16_s            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_asr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_lsr_16_r            , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_roxr_16_r           , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_ror_16_r            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_asr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_lsr_32_s            , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_roxr_32_s           , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_ror_32_s            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_asr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_lsr_32_r            , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_roxr_32_r           , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_ror_32_r            , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_bfset_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_bfset_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_di         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_ix         , 
+	m68k_op_bfset_32_aw         , 
+	m68k_op_bfset_32_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_asl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_lsl_8_s             , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_roxl_8_s            , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_rol_8_s             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_asl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_lsl_8_r             , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_roxl_8_r            , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_rol_8_r             , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_asl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_lsl_16_s            , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_roxl_16_s           , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_rol_16_s            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_asl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_lsl_16_r            , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_roxl_16_r           , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_rol_16_r            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_asl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_lsl_32_s            , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_roxl_32_s           , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_rol_32_s            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_asl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_lsl_32_r            , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_roxl_32_r           , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_rol_32_r            , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_bfins_32_d          , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_bfins_32_ai         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_di         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_ix         , 
+	m68k_op_bfins_32_aw         , 
+	m68k_op_bfins_32_al         , 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_illegal, 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpgen_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpdbcc_32           , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cpscc_32            , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cptrapcc_32         , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_cpbcc_32            , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+	m68k_op_1111                , 
+};
+
+const unsigned char m68ki_cycles[1][0x10000]={
+	{
+		8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+		16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+		22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+		16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+		22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+		16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, 
+		28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+		30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+		34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+		8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+		10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+		10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+		16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+		22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 
+		16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, 
+		22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, 
+		14, 14, 14, 14, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, 
+		28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 
+		30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, 
+		34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, 
+		8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+		10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+		10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
+		18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 
+		8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, 
+		12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 
+		14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, 
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+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 
+		4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 	},
+};
diff --git a/MCUME_pico2/picogenold/osd_cpu.h b/MCUME_pico2/picogenold/osd_cpu.h
new file mode 100644
index 0000000..cf4a553
--- /dev/null
+++ b/MCUME_pico2/picogenold/osd_cpu.h
@@ -0,0 +1,70 @@
+/*******************************************************************************
+*																			   *
+*	Define size independent data types and operations.						   *
+*																			   *
+*   The following types must be supported by all platforms:					   *
+*																			   *
+*	UINT8  - Unsigned 8-bit Integer		INT8  - Signed 8-bit integer           *
+*	UINT16 - Unsigned 16-bit Integer	INT16 - Signed 16-bit integer          *
+*	UINT32 - Unsigned 32-bit Integer	INT32 - Signed 32-bit integer          *
+*	UINT64 - Unsigned 64-bit Integer	INT64 - Signed 64-bit integer          *
+*																			   *
+*																			   *
+*   The macro names for the artithmatic operations are composed as follows:    *
+*																			   *
+*   XXX_R_A_B, where XXX - 3 letter operation code (ADD, SUB, etc.)			   *
+*					 R   - The type	of the result							   *
+*					 A   - The type of operand 1							   *
+*			         B   - The type of operand 2 (if binary operation)		   *
+*																			   *
+*				     Each type is one of: U8,8,U16,16,U32,32,U64,64			   *
+*																			   *
+*******************************************************************************/
+
+
+#ifndef OSD_CPU_H
+#define OSD_CPU_H
+
+#include "shared.h"
+
+/* Combine two 32-bit integers into a 64-bit integer */
+#define COMBINE_64_32_32(A,B)     ((((UINT64)(A))<<32) | (UINT32)(B))
+#define COMBINE_U64_U32_U32(A,B)  COMBINE_64_32_32(A,B)
+
+/* Return upper 32 bits of a 64-bit integer */
+#define HI32_32_64(A)		  (((UINT64)(A)) >> 32)
+#define HI32_U32_U64(A)		  HI32_32_64(A)
+
+/* Return lower 32 bits of a 64-bit integer */
+#define LO32_32_64(A)		  ((A) & 0xffffffff)
+#define LO32_U32_U64(A)		  LO32_32_64(A)
+
+#define DIV_64_64_32(A,B)	  ((A)/(B))
+#define DIV_U64_U64_U32(A,B)  ((A)/(UINT32)(B))
+
+#define MOD_32_64_32(A,B)	  ((A)%(B))
+#define MOD_U32_U64_U32(A,B)  ((A)%(UINT32)(B))
+
+#define MUL_64_32_32(A,B)	  ((A)*(INT64)(B))
+#define MUL_U64_U32_U32(A,B)  ((A)*(UINT64)(UINT32)(B))
+
+
+/******************************************************************************
+ * Union of UINT8, UINT16 and UINT32 in native endianess of the target
+ * This is used to access bytes and words in a machine independent manner.
+ * The upper bytes h2 and h3 normally contain zero (16 bit CPU cores)
+ * thus PAIR.d can be used to pass arguments to the memory system
+ * which expects 'int' really.
+ ******************************************************************************/
+typedef union {
+#ifdef LSB_FIRST
+	struct { UINT8 l,h,h2,h3; } b;
+	struct { UINT16 l,h; } w;
+#else
+	struct { UINT8 h3,h2,h,l; } b;
+	struct { UINT16 h,l; } w;
+#endif
+	UINT32 d;
+}	PAIR;
+
+#endif	/* defined OSD_CPU_H */
diff --git a/MCUME_pico2/picogenold/picogen.cpp b/MCUME_pico2/picogenold/picogen.cpp
new file mode 100644
index 0000000..f056b2f
--- /dev/null
+++ b/MCUME_pico2/picogenold/picogen.cpp
@@ -0,0 +1,188 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+//    set_sys_clock_khz(125000, true);
+
+    set_sys_clock_khz(250000, true);
+    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+     emu_init();
+ 
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picogenold/render.c b/MCUME_pico2/picogenold/render.c
new file mode 100644
index 0000000..5885e63
--- /dev/null
+++ b/MCUME_pico2/picogenold/render.c
@@ -0,0 +1,1065 @@
+/*
+        only update window clip on window change (?)
+        fix leftmost window/nta render and window bug
+        sprite masking isn't right in sonic/micromachines 2, but
+        seems ok in galaxy force 2
+*/
+
+
+#include "shared.h"
+#include "platform_config.h"
+
+#ifdef HAS_T4_VGA 
+#include "vga_t_dma.h"
+#endif
+extern void emu_DrawLine16(unsigned short *src, int width , int height, int line); 
+extern void emu_printf(char * text);
+
+
+#ifdef ALIGN_LONG
+
+/* Or change the names if you depend on these from elsewhere.. */
+#undef READ_LONG
+#undef WRITE_LONG
+
+
+
+       if(reg[12] & 8)
+        {
+            int j;
+            for(j = 0; j < 3; j += 1)
+            {
+                color = &vdp_palette[j][data];
+                set_color((j << 6), color);
+            }
+        }
+        else
+        {
+            color = &vdp_palette[1][data];
+            set_color(0x00, color);
+            set_color(0x40, color);
+            set_color(0x80, color);
+        }
+  
+
+
+static __inline__ uint32 READ_LONG(void *address)
+{
+    if ((uint32)address & 3)
+	{
+#ifdef LSB_FIRST  /* little endian version */
+        return ( *((uint8 *)address) +
+                (*((uint8 *)address+1) << 8)  +
+                (*((uint8 *)address+2) << 16) +
+                (*((uint8 *)address+3) << 24) );
+#else             /* big endian version */
+        return ( *((uint8 *)address+3) +
+                (*((uint8 *)address+2) << 8)  +
+                (*((uint8 *)address+1) << 16) +
+                (*((uint8 *)address)   << 24) );
+#endif  /* LSB_FIRST */
+	}
+	else
+        return *(uint32 *)address;
+}
+
+static __inline__ void WRITE_LONG(void *address, uint32 data)
+{
+    if ((uint32)address & 3)
+	{
+#ifdef LSB_FIRST
+            *((uint8 *)address) =    data;
+            *((uint8 *)address+1) = (data >> 8);
+            *((uint8 *)address+2) = (data >> 16);
+            *((uint8 *)address+3) = (data >> 24);
+#else
+            *((uint8 *)address+3) =  data;
+            *((uint8 *)address+2) = (data >> 8);
+            *((uint8 *)address+1) = (data >> 16);
+            *((uint8 *)address)   = (data >> 24);
+#endif /* LSB_FIRST */
+		return;
+  	}
+  	else
+        *(uint32 *)address = data;
+}
+
+#endif  /* ALIGN_LONG */
+
+#ifdef ALIGN_LONG
+/* Draw a single 8-pixel column */
+#define DRAW_COLUMN(ATTR, LINE) \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    ATTR >>= 16; \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++;
+
+
+/* Draw a single 16-pixel column */
+#define DRAW_COLUMN_IM2(ATTR, LINE) \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \
+    if(ATTR & 0x1000) offs ^= 0x40; \
+    src = (uint32 *)&bg_pattern_cache[offs]; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    ATTR >>= 16; \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \
+    if(ATTR & 0x1000) offs ^= 0x40; \
+    src = (uint32 *)&bg_pattern_cache[offs]; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; \
+    WRITE_LONG(dst, READ_LONG(src) | atex); \
+    dst++; \
+    src++; 
+
+#else
+
+#define DRAW_COLUMN(ATTR, LINE) \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \
+    *dst++ = (*src++ | atex); \
+    *dst++ = (*src++ | atex); \
+    ATTR >>= 16; \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \
+    *dst++ = (*src++ | atex); \
+    *dst++ = (*src++ | atex);
+
+#define DRAW_COLUMN_IM2(ATTR, LINE) \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \
+    if(ATTR & 0x1000) offs ^= 0x40; \
+    src = (uint32 *)&bg_pattern_cache[offs]; \
+    *dst++ = (*src++ | atex); \
+    *dst++ = (*src++ | atex); \
+    ATTR >>= 16; \
+    atex = atex_table[(ATTR >> 13) & 7]; \
+    offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \
+    if(ATTR & 0x1000) offs ^= 0x40; \
+    src = (uint32 *)&bg_pattern_cache[offs]; \
+    *dst++ = (*src++ | atex); \
+    *dst++ = (*src++ | atex);
+
+
+
+#endif /* ALIGN_LONG */
+
+
+
+/*
+    gcc complains about this:
+        *lb++ = table[(*lb << 8) |(*src++ | palette)]; 
+    .. claiming the result on lb is undefined.
+    So we manually advance lb and use constant offsets into the line buffer.
+*/
+#define DRAW_SPRITE_TILE \
+    lb[0] = table[(lb[0] << 8) |(*src++ | palette)]; \
+    lb[1] = table[(lb[1] << 8) |(*src++ | palette)]; \
+    lb[2] = table[(lb[2] << 8) |(*src++ | palette)]; \
+    lb[3] = table[(lb[3] << 8) |(*src++ | palette)]; \
+    lb[4] = table[(lb[4] << 8) |(*src++ | palette)]; \
+    lb[5] = table[(lb[5] << 8) |(*src++ | palette)]; \
+    lb[6] = table[(lb[6] << 8) |(*src++ | palette)]; \
+    lb[7] = table[(lb[7] << 8) |(*src++ | palette)]
+
+/* Pixel creation macros, input is four bits each */
+
+/* 3:3:2 RGB */
+#define MAKE_PIXEL_8(r,g,b)  ((r) <<  5 | (g) << 2 | ((b) >> 1))
+
+/* 5:6:5 RGB */
+#define MAKE_PIXEL_16(r,g,b) ((r) << 12 | (g) << 7 | (b) << 1)
+
+/* Clip data */
+static clip_t clip[2];
+
+/* Attribute expansion table */
+static const uint32 atex_table[] = {
+    0x00000000, 0x10101010, 0x20202020, 0x30303030,
+    0x40404040, 0x50505050, 0x60606060, 0x70707070
+};
+
+/* Sprite name look-up table */
+static uint8 name_lut[0x400];
+
+/* Sprite line buffer data */
+static uint8 object_index_count;
+
+struct {
+    uint16 ypos;
+    uint16 xpos;
+    uint16 attr;
+    uint8 size;
+    uint8 index;
+}object_info[20];
+
+/* Pixel look-up tables and table base address */
+static uint8 *lut[5];
+#include "genlut.h"
+
+/* 16-bit pixel remapping data */
+static uint16 pixel_16[0x100];
+static uint16 pixel_16_lut[3][0x200];
+
+/* Line buffers */
+static uint8 tmp_buf[0x400];                   /* Temporary buffer */
+static uint8 bg_buf[0x400];                    /* Merged background buffer */
+static uint8 nta_buf[0x400];                   /* Plane A / Window line buffer */
+static uint8 ntb_buf[0x400];                   /* Plane B line buffer */
+static uint8 obj_buf[0x400];                   /* Object layer line buffer */
+
+static uint16 line_buf[0x400];
+
+
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown routines                                           */
+/*--------------------------------------------------------------------------*/
+
+int render_init(void)
+{
+    int i;
+
+    /* Pixel look-up tables */
+    lut[0] = (uint8 *)(lut_base);
+    for(i = 1; i < LUT_MAX; i += 1)
+    {
+        lut[i] = lut[0] + (i * LUT_SIZE);
+    }
+
+    /* Make pixel data tables */
+    for(i = 0; i < 0x200; i += 1)
+    {
+        int r, g, b;
+        
+        r = (i >> 6) & 7;
+        g = (i >> 3) & 7;
+        b = (i >> 0) & 7;
+
+        pixel_16_lut[0][i] = MAKE_PIXEL_16(r,g,b);
+        pixel_16_lut[1][i] = MAKE_PIXEL_16(r<<1,g<<1,b<<1);
+        pixel_16_lut[2][i] = MAKE_PIXEL_16(r|8,g|8,b|8);
+    }
+
+
+    /* Set up color update function */
+    color_update = color_update_16;
+
+    /* Make sprite name look-up table */
+    make_name_lut();
+
+    return (1);
+}
+
+void make_name_lut(void)
+{
+    int col, row;
+    int vcol, vrow;
+    int width, height;
+    int flipx, flipy;
+    int i, name;
+
+    memset(name_lut, 0, sizeof(name_lut));
+
+    for(i = 0; i < 0x400; i += 1)
+    {
+        vcol = col = i & 3;
+        vrow = row = (i >> 2) & 3;
+        height = (i >> 4) & 3;
+        width = (i >> 6) & 3;
+        flipx = (i >> 8) & 1;
+        flipy = (i >> 9) & 1;
+
+        if(flipx)
+            vcol = (width - col);
+        if(flipy)
+            vrow = (height - row);
+
+        name = vrow + (vcol * (height + 1));
+
+        if((row > height) || col > width)
+            name = -1;
+
+        name_lut[i] = name;        
+    }
+}
+
+
+
+void render_reset(void)
+{
+    memset(&clip, 0, sizeof(clip));
+
+    memset(bg_buf, 0, sizeof(bg_buf));
+    memset(tmp_buf, 0, sizeof(tmp_buf));
+    memset(nta_buf, 0, sizeof(nta_buf));
+    memset(ntb_buf, 0, sizeof(ntb_buf));
+    memset(obj_buf, 0, sizeof(obj_buf));
+
+    //memset(&pixel_8, 0, sizeof(pixel_8));
+    memset(&pixel_16, 0, sizeof(pixel_16));
+}
+
+
+void render_shutdown(void)
+{
+}
+
+/*--------------------------------------------------------------------------*/
+/* Line render function                                                     */
+/*--------------------------------------------------------------------------*/
+
+void render_line(int line)
+{
+//    uint8 *lb = (gbitmap.remap == 1) ? tmp_buf : &gbitmap.data[(line * gbitmap.pitch)];
+    uint8 *lb = tmp_buf;
+
+    if((reg[1] & 0x40) == 0x00)
+    {
+        /* Use the overscan color to clear the screen */
+        memset(&lb[gbitmap.viewport.x], 0x40 | border, gbitmap.viewport.w);
+    }
+    else
+    {
+        update_bg_pattern_cache();
+        window_clip(line);
+
+        if(im2_flag)
+        {
+            render_ntx_im2(0, line, nta_buf);
+            render_ntx_im2(1, line, ntb_buf);
+        }
+        else
+        {
+            if(reg[0x0B] & 4)
+            {
+                render_ntx_vs(0, line, nta_buf);
+                render_ntx_vs(1, line, ntb_buf);
+            }
+            else
+            {
+                render_ntx(0, line, nta_buf);
+                render_ntx(1, line, ntb_buf);
+            }
+        }
+
+        if(im2_flag)
+              render_ntw_im2(line, nta_buf);
+        else
+              render_ntw(line, nta_buf);
+
+        if(reg[12] & 8)
+        {
+            merge(&nta_buf[0x20], &ntb_buf[0x20], &bg_buf[0x20], lut[2], (reg[12] & 1) ? 320 : 256);
+            memset(&obj_buf[0x20], 0, (reg[12] & 1) ? 320 : 256);
+
+            if(im2_flag)
+                render_obj_im2(line, obj_buf, lut[3]);
+            else
+                render_obj(line, obj_buf, lut[3]);
+
+            merge(&obj_buf[0x20], &bg_buf[0x20], &lb[0x20], lut[4], (reg[12] & 1) ? 320 : 256);
+        }
+        else
+        {
+            merge(&nta_buf[0x20], &ntb_buf[0x20], &lb[0x20], lut[0], (reg[12] & 1) ? 320 : 256);
+            if(im2_flag)
+                render_obj_im2(line, lb, lut[1]);
+            else
+                render_obj(line, lb, lut[1]);
+        }
+    }
+
+    if(reg[0] & 0x20)
+    {
+        memset(&lb[gbitmap.viewport.x], 0x40 | border, 0x08);
+    }
+
+
+    int width = (reg[12] & 1) ? 320 : 256;
+    remap_16(lb+0x20, line_buf, pixel_16, width);
+    emu_DrawLine16(line_buf, width ,256, line); 
+}
+/*--------------------------------------------------------------------------*/
+/* Window rendering                                                         */
+/*--------------------------------------------------------------------------*/
+
+void render_ntw(int line, uint8 *buf)
+{
+    int column, v_line, width;
+    uint32 *nt, *src, *dst, atex, atbuf;
+
+    v_line = (line & 7) << 3;
+    width = (reg[12] & 1) ? 7 : 6;
+
+    nt = (uint32 *)&vram[ntwb | ((line >> 3) << width)];
+    dst = (uint32 *)&buf[0x20 + (clip[1].left << 4)];
+
+    for(column = clip[1].left; column < clip[1].right; column += 1)
+    {
+        atbuf = nt[column];
+        DRAW_COLUMN(atbuf, v_line)
+    }
+}
+
+void render_ntw_im2(int line, uint8 *buf)
+{
+    int column, v_line, width;
+    uint32 *nt, *src, *dst, atex, atbuf, offs;
+
+    v_line = ((line & 7) << 1 | ((status >> 4) & 1)) << 3;
+    width = (reg[12] & 1) ? 7 : 6;
+
+    nt = (uint32 *)&vram[ntwb | ((line >> 3) << width)];
+    dst = (uint32 *)&buf[0x20 + (clip[1].left << 4)];
+
+    for(column = clip[1].left; column < clip[1].right; column += 1)
+    {
+        atbuf = nt[column];
+        DRAW_COLUMN_IM2(atbuf, v_line)
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Background plane rendering                                               */
+/*--------------------------------------------------------------------------*/
+
+void render_ntx(int which, int line, uint8 *buf)
+{
+    int column;
+    int start, end;
+    int index;
+    int shift;
+    int nametable_row_mask = (playfield_col_mask >> 1);
+    int v_line;
+    uint32 atex, atbuf, *src, *dst;
+    uint16 xascroll, xbscroll, xscroll;
+    int y_scroll;
+    uint32 *nt;
+    int vsr_shift;
+    uint32 *vs;
+    uint16 table;
+
+
+
+
+    table = (which) ? ntbb : ntab;
+
+    get_hscroll(line, &xascroll, &xbscroll);
+    xscroll = (which) ? xbscroll : xascroll;
+
+    shift = (xscroll & 0x0F);
+    index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask);
+
+    if(which)
+    {
+        start = 0;
+        end = (reg[0x0C] & 1) ? 20 : 16;
+    }
+    else
+    {
+// Looks correct if clip[0].left has 1 subtracted
+// Otherwise window has gap between endpoint and where the first normal
+// nta column starts
+
+        if(clip[0].enable == 0) return;
+        start = clip[0].left;
+        end = clip[0].right;
+        index = (index + clip[0].left) & nametable_row_mask;
+    }
+
+    vsr_shift = (which) ? 16 : 0;
+    vs = (uint32 *)&vsram[0];
+
+    y_scroll = (vs[0] >> vsr_shift) & 0xFFFF;
+
+//    int dy = line & 0x7; 
+//    int rev_line = (line & 0x1f8) + (dy^7);
+
+    y_scroll = (line + (y_scroll & 0x3FF)) & playfield_row_mask;
+
+    int dy = y_scroll & 0x7; 
+    int y_scroll2 = (y_scroll & 0x1f8) + (dy^7);
+
+
+
+
+    v_line = (y_scroll & 7) << 3;
+    int v_line2 = (y_scroll2 & 7) << 3;
+    
+    nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)];
+
+    if(shift)
+    {
+        dst = (uint32 *)&buf[0x20-(0x10-shift)];
+        atbuf = nt[(index-1) & nametable_row_mask];
+        //DRAW_COLUMN(atbuf, v_line)
+       // JMH
+        if (atbuf & 0x1000) {
+            DRAW_COLUMN(atbuf, v_line2);
+        }
+        else  {
+            DRAW_COLUMN(atbuf, v_line);
+        }  
+     }
+    buf = (buf + 0x20 + shift);
+    dst = (uint32 *)&buf[start<<4];
+
+
+
+    for(column = start; column < end; column += 1, index += 1)
+    {
+        atbuf = nt[index & nametable_row_mask];
+        // JMH
+        if (atbuf & 0x1000) {
+            DRAW_COLUMN(atbuf, v_line2);
+        }
+        else  
+        {
+            DRAW_COLUMN(atbuf, v_line);
+        }  
+    }
+
+}
+
+
+void render_ntx_im2(int which, int line, uint8 *buf)
+{
+    int column;
+    int start, end;
+    int index;
+    int shift;
+    int nametable_row_mask = (playfield_col_mask >> 1);
+    int v_line;
+    uint32 atex, atbuf, *src, *dst;
+    uint16 xascroll, xbscroll, xscroll;
+    int y_scroll;
+    uint32 *nt;
+    int vsr_shift;
+    uint32 *vs;
+    uint16 table;
+    uint32 offs;
+
+    table = (which) ? ntbb : ntab;
+
+    get_hscroll(line, &xascroll, &xbscroll);
+    xscroll = (which) ? xbscroll : xascroll;
+
+    shift = (xscroll & 0x0F);
+    index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask);
+
+    if(which)
+    {
+        start = 0;
+        end = (reg[0x0C] & 1) ? 20 : 16;
+    }
+    else
+    {
+        if(clip[0].enable == 0) return;
+        start = clip[0].left;
+        end = clip[0].right;
+        index = (index + clip[0].left) & nametable_row_mask;
+    }
+
+    vsr_shift = (which) ? 16 : 0;
+    vs = (uint32 *)&vsram[0];
+
+    y_scroll = (vs[0] >> vsr_shift) & 0xFFFF;
+    y_scroll = (line + ((y_scroll >> 1) & 0x3FF)) & playfield_row_mask;
+    v_line = (((y_scroll & 7) << 1) | ((status >> 4) & 1)) << 3;
+    nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)];
+
+    if(shift)
+    {
+        dst = (uint32 *)&buf[0x20-(0x10-shift)];
+        atbuf = nt[(index-1) & nametable_row_mask];
+        DRAW_COLUMN_IM2(atbuf, v_line)
+    }
+    buf = (buf + 0x20 + shift);
+    dst = (uint32 *)&buf[start<<4];
+
+    for(column = start; column < end; column += 1, index += 1)
+    {
+        atbuf = nt[index & nametable_row_mask];
+        DRAW_COLUMN_IM2(atbuf, v_line)
+    }
+}
+
+
+void render_ntx_vs(int which, int line, uint8 *buf)
+{
+    int column;
+    int start, end;
+    int index;
+    int shift;
+    int nametable_row_mask = (playfield_col_mask >> 1);
+    int v_line;
+    uint32 atex, atbuf, *src, *dst;
+    uint16 xascroll, xbscroll, xscroll;
+    int y_scroll;
+    uint32 *nt;
+    int vsr_shift;
+    uint32 *vs;
+    uint16 table;
+
+    table = (which) ? ntbb : ntab;
+
+    get_hscroll(line, &xascroll, &xbscroll);
+    xscroll = (which) ? xbscroll : xascroll;
+    shift = (xscroll & 0x0F);
+    index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask);
+
+    if(which)
+    {
+        start = 0;
+        end = (reg[0x0C] & 1) ? 20 : 16;
+    }
+    else
+    {
+        if(clip[0].enable == 0) return;
+        start = clip[0].left;
+        end = clip[0].right;
+        index = (index + clip[0].left) & nametable_row_mask;
+    }
+
+    vsr_shift = (which) ? 16 : 0;
+    vs = (uint32 *)&vsram[0];
+    end = (reg[0x0C] & 1) ? 20 : 16;
+
+    if(shift)
+    {
+        dst = (uint32 *)&buf[0x20-(0x10-shift)];
+        y_scroll = (line & playfield_row_mask);
+        v_line = (y_scroll & 7) << 3;
+        nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)];
+        atbuf = nt[(index-1) & nametable_row_mask];
+        DRAW_COLUMN(atbuf, v_line)
+    }
+
+    buf = (buf + 0x20 + shift);
+    dst = (uint32 *)&buf[start << 4];
+
+    for(column = start; column < end; column += 1, index += 1)
+    {
+        y_scroll = (vs[column] >> vsr_shift) & 0xFFFF;
+        y_scroll = (line + (y_scroll & 0x3FF)) & playfield_row_mask;
+        v_line = (y_scroll & 7) << 3;
+        nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)];
+        atbuf = nt[index & nametable_row_mask];
+        DRAW_COLUMN(atbuf, v_line)
+    }
+}
+/*--------------------------------------------------------------------------*/
+/* Helper functions (cache update, hscroll, window clip)                    */
+/*--------------------------------------------------------------------------*/
+
+void update_bg_pattern_cache(void)
+{
+    int i;
+    uint8 x, y, c;
+    uint16 name;
+
+    if(!bg_list_index) return;
+
+    for(i = 0; i < bg_list_index; i += 1)
+    {
+        name = bg_name_list[i];
+        bg_name_list[i] = 0;
+
+        for(y = 0; y < 8; y += 1)
+        {
+            if(bg_name_dirty[name] & (1 << y))
+            {
+                uint8 *dst = &bg_pattern_cache[name << 6];
+                uint32 bp = *(uint32 *)&vram[(name << 5) | (y << 2)];
+
+                for(x = 0; x < 8; x += 1)
+                {
+                    c = (bp >> ((x ^ 3) << 2)) & 0x0F;
+                    dst[0x00000 | (y << 3) | (x)] = (c);
+                    dst[0x20000 | (y << 3) | (x ^ 7)] = (c);
+                    //dst[0x40000 | ((y ^ 7) << 3) | (x)] = (c);
+                    //dst[0x60000 | ((y ^ 7) << 3) | (x ^ 7)] = (c);
+                }
+            }
+        }
+        bg_name_dirty[name] = 0;
+    }
+    bg_list_index = 0;
+}
+
+void get_hscroll(int line, uint16 *scrolla, uint16 *scrollb)
+{
+    switch(reg[11] & 3)
+    {
+        case 0: /* Full-screen */
+            *scrolla = *(uint16 *)&vram[hscb + 0];
+            *scrollb = *(uint16 *)&vram[hscb + 2];
+            break;
+
+        case 1: /* First 8 lines */
+            *scrolla = *(uint16 *)&vram[hscb + ((line & 7) << 2) + 0];
+            *scrollb = *(uint16 *)&vram[hscb + ((line & 7) << 2) + 2];
+            break;
+
+        case 2: /* Every 8 lines */
+            *scrolla = *(uint16 *)&vram[hscb + ((line & ~7) << 2) + 0];
+            *scrollb = *(uint16 *)&vram[hscb + ((line & ~7) << 2) + 2];
+            break;
+
+        case 3: /* Every line */
+            *scrolla = *(uint16 *)&vram[hscb + (line << 2) + 0];
+            *scrollb = *(uint16 *)&vram[hscb + (line << 2) + 2];
+            break;
+    }
+
+    *scrolla &= 0x03FF;
+    *scrollb &= 0x03FF;
+}
+
+void window_clip(int line)
+{
+    /* Window size and invert flags */
+    int hp = (reg[17] & 0x1F);
+    int hf = (reg[17] >> 7) & 1;
+    int vp = (reg[18] & 0x1F) << 3;
+    int vf = (reg[18] >> 7) & 1;
+
+    /* Display size  */
+    int sw = (reg[12] & 1) ? 20 : 16;
+
+    /* Clear clipping data */
+    memset(&clip, 0, sizeof(clip));
+
+    /* Check if line falls within window range */
+    if(vf == (line >= vp))
+    {
+        /* Window takes up entire line */
+        clip[1].right = sw;
+        clip[1].enable = 1;
+    }
+    else
+    {
+        /* Perform horizontal clipping; the results are applied in reverse
+           if the horizontal inversion flag is set */
+        int a = hf;
+        int w = hf ^ 1;
+
+        if(hp)
+        {
+            if(hp > sw)
+            {
+                /* Plane W takes up entire line */
+                clip[w].right = sw;
+                clip[w].enable = 1;
+            }
+            else
+            {
+                /* Window takes left side, Plane A takes right side */
+                clip[w].right = hp;
+                clip[a].left = hp;
+                clip[a].right = sw;
+                clip[0].enable = clip[1].enable = 1;
+            }
+        }
+        else
+        {
+            /* Plane A takes up entire line */
+            clip[a].right = sw;
+            clip[a].enable = 1;
+        }
+    }
+}
+
+
+
+
+
+
+
+/*--------------------------------------------------------------------------*/
+/* Remap functions                                                          */
+/*--------------------------------------------------------------------------*/
+void remap_16(uint8 *src, uint16 *dst, uint16 *table, int length)
+{
+    int count;
+    for(count = 0; count < length; count += 1)
+    {
+        *dst++ = table[*src++];
+    }
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Merge functions                                                          */
+/*--------------------------------------------------------------------------*/
+
+void merge(uint8 *srca, uint8 *srcb, uint8 *dst, uint8 *table, int width)
+{
+    int i;
+    for(i = 0; i < width; i += 1)
+    {
+        uint8 a = srca[i];
+        uint8 b = srcb[i];
+        uint8 c = table[(b << 8) | (a)];
+        dst[i] = c;
+    }
+}
+
+
+void color_update_16(int index, uint16 data)
+{
+    if(reg[12] & 8)
+    {
+        pixel_16[0x00 | index] = pixel_16_lut[0][data];
+        pixel_16[0x40 | index] = pixel_16_lut[1][data];
+        pixel_16[0x80 | index] = pixel_16_lut[2][data];
+    }
+    else
+    {
+        uint16 temp = pixel_16_lut[1][data];
+        pixel_16[0x00 | index] = temp;
+        pixel_16[0x40 | index] = temp;
+        pixel_16[0x80 | index] = temp;
+    }
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Object render functions                                                  */
+/*--------------------------------------------------------------------------*/
+
+void parse_satb(int line)
+{
+    static uint8 sizetab[] = {8, 16, 24, 32};
+    uint8 *p, *q, link = 0;
+    uint16 ypos;
+
+    int count;
+    int height;
+
+    int limit = (reg[12] & 1) ? 20 : 16;
+    int total = (reg[12] & 1) ? 80 : 64;
+
+    object_index_count = 0;
+
+    for(count = 0; count < total; count += 1)
+    {
+        q = &sat[link << 3];
+        p = &vram[satb + (link << 3)];
+
+        ypos = *(uint16 *)&q[0];
+
+        if(im2_flag)
+            ypos = (ypos >> 1) & 0x1FF;
+        else
+            ypos &= 0x1FF;
+
+        height = sizetab[q[3] & 3];
+
+        if((line >= ypos) && (line < (ypos + height)))
+        {
+            object_info[object_index_count].ypos = *(uint16 *)&q[0];
+            object_info[object_index_count].xpos = *(uint16 *)&p[6];
+
+            // using xpos from internal satb stops sprite x
+            // scrolling in bloodlin.bin,
+            // but this seems to go against the test prog
+//          object_info[object_index_count].xpos = *(uint16 *)&q[6];
+            object_info[object_index_count].attr = *(uint16 *)&p[4];
+            object_info[object_index_count].size = q[3];
+            object_info[object_index_count].index = count;
+
+            object_index_count += 1;
+
+            if(object_index_count == limit)
+            {
+                if(vint_pending == 0)
+                    status |= 0x40;
+                return;
+            }
+        }
+
+        link = q[2] & 0x7F;
+        if(link == 0) break;
+    }
+}
+
+void render_obj(int line, uint8 *buf, uint8 *table)
+{
+    uint16 ypos;
+    uint16 attr;
+    uint16 xpos;
+    uint8 sizetab[] = {8, 16, 24, 32};
+    uint8 size;
+    uint8 *src;
+
+    int count;
+    int pixellimit = (reg[12] & 1) ? 320 : 256;
+    int pixelcount = 0;
+    int width;
+    int height;
+    int v_line;
+    int column;
+    int sol_flag = 0;
+    int left = 0x80;
+    int right = 0x80 + ((reg[12] & 1) ? 320 : 256);
+
+    uint8 *s, *lb;
+    uint16 name, index;
+    uint8 palette;
+
+    int attr_mask, nt_row;
+
+    if(object_index_count == 0) return;
+
+    for(count = 0; count < object_index_count; count += 1)
+    {
+        size = object_info[count].size & 0x0f;
+        xpos = object_info[count].xpos;
+        xpos &= 0x1ff;
+
+        width = sizetab[(size >> 2) & 3];
+
+        if(xpos != 0) sol_flag = 1;
+        else
+        if(xpos == 0 && sol_flag) return;
+
+        if(pixelcount > pixellimit) return;
+        pixelcount += width;
+
+        if(((xpos + width) >= left) && (xpos < right))
+        {
+            ypos = object_info[count].ypos;
+            ypos &= 0x1ff;
+
+            attr = object_info[count].attr;
+//            attr_mask = (attr & 0x1800);
+            attr_mask = (attr & 0x800);
+
+            height = sizetab[size & 3];
+            palette = (attr >> 9) & 0x70;
+
+            v_line = (line - ypos);
+            nt_row = (v_line >> 3) & 3;
+
+            if (attr & 0x1000) {
+                v_line = ((v_line & 7)^0x07) << 3;
+            }
+            else {
+                v_line = ((v_line & 7)) << 3;                
+            }
+
+            name = (attr & 0x07FF);
+            s = &name_lut[((attr >> 3) & 0x300) | (size << 4) | (nt_row << 2)];
+
+            lb = (uint8 *)&buf[0x20 + (xpos - 0x80)];
+
+            width >>= 3;
+            for(column = 0; column < width; column += 1, lb+=8)
+            {
+                index = attr_mask | ((name + s[column]) & 0x07FF);
+                src = &bg_pattern_cache[(index << 6) | (v_line)];
+                DRAW_SPRITE_TILE;
+            }
+        }
+    }
+}
+
+void render_obj_im2(int line, uint8 *buf, uint8 *table)
+{
+    uint16 ypos;
+    uint16 attr;
+    uint16 xpos;
+    uint8 sizetab[] = {8, 16, 24, 32};
+    uint8 size;
+    uint8 *src;
+
+    int count;
+    int pixellimit = (reg[12] & 1) ? 320 : 256;
+    int pixelcount = 0;
+    int width;
+    int height;
+    int v_line;
+    int column;
+    int sol_flag = 0;
+    int left = 0x80;
+    int right = 0x80 + ((reg[12] & 1) ? 320 : 256);
+
+    uint8 *s, *lb;
+    uint16 name, index;
+    uint8 palette;
+    uint32 offs;
+
+    int attr_mask, nt_row;
+
+    if(object_index_count == 0) return;
+
+    for(count = 0; count < object_index_count; count += 1)
+    {
+        size = object_info[count].size & 0x0f;
+        xpos = object_info[count].xpos;
+        xpos &= 0x1ff;
+
+        width = sizetab[(size >> 2) & 3];
+
+        if(xpos != 0) sol_flag = 1;
+        else
+        if(xpos == 0 && sol_flag) return;
+
+        if(pixelcount > pixellimit) return;
+        pixelcount += width;
+
+        if(((xpos + width) >= left) && (xpos < right))
+        {
+            ypos = object_info[count].ypos;
+            ypos = (ypos >> 1) & 0x1ff;
+
+            attr = object_info[count].attr;
+//            attr_mask = (attr & 0x1800);
+            attr_mask = (attr & 0x800);
+
+            height = sizetab[size & 3];
+            palette = (attr >> 9) & 0x70;
+
+            v_line = (line - ypos);
+            nt_row = (v_line >> 3) & 3;
+            v_line = ((((v_line & 7)/*^0x07*/) << 1) | ((status >> 4) & 1)) << 3;            
+
+            name = (attr & 0x03FF);
+            s = &name_lut[((attr >> 3) & 0x300) | (size << 4) | (nt_row << 2)];
+
+            lb = (uint8 *)&buf[0x20 + (xpos - 0x80)];
+
+            width >>= 3;
+            for(column = 0; column < width; column += 1, lb+=8)
+            {
+                index = (name + s[column]) & 0x3ff;
+                offs = index << 7 | attr_mask << 6 | v_line;
+                if(attr & 0x1000) offs ^= 0x40;
+                src = &bg_pattern_cache[offs];
+                DRAW_SPRITE_TILE;
+            }
+        }
+    }
+}
diff --git a/MCUME_pico2/picogenold/render.h b/MCUME_pico2/picogenold/render.h
new file mode 100644
index 0000000..75195a4
--- /dev/null
+++ b/MCUME_pico2/picogenold/render.h
@@ -0,0 +1,39 @@
+
+#ifndef _RENDER_H_
+#define _RENDER_H_
+
+
+/* Look-up pixel table information */
+#define LUT_MAX         (5)
+#define LUT_SIZE        (0x10000)
+
+/* Clip structure */
+typedef struct
+{
+    uint8 left;
+    uint8 right;
+    uint8 enable;
+}clip_t;
+
+/* Function prototypes */
+int render_init(void);
+void render_reset(void);
+void render_shutdown(void);
+void render_line(int line);
+void render_obj(int line, uint8 *buf, uint8 *table);
+void render_obj_im2(int line, uint8 *buf, uint8 *table);
+void render_ntw(int line, uint8 *buf);
+void render_ntw_im2(int line, uint8 *buf);
+void render_ntx(int which, int line, uint8 *buf);
+void render_ntx_im2(int which, int line, uint8 *buf);
+void render_ntx_vs(int which, int line, uint8 *buf);
+void update_bg_pattern_cache(void);
+void get_hscroll(int line, uint16 *scrolla, uint16 *scrollb);
+void window_clip(int line);
+void remap_16(uint8 *src, uint16 *dst, uint16 *table, int length);
+void merge(uint8 *srca, uint8 *srcb, uint8 *dst, uint8 *table, int width);
+void color_update_16(int index, uint16 data);
+void make_name_lut(void);
+void parse_satb(int line);
+
+#endif /* _RENDER_H_ */
diff --git a/MCUME_pico2/picogenold/shared.h b/MCUME_pico2/picogenold/shared.h
new file mode 100644
index 0000000..5120897
--- /dev/null
+++ b/MCUME_pico2/picogenold/shared.h
@@ -0,0 +1,53 @@
+
+#ifndef _SHARED_H_
+#define _SHARED_H_
+
+
+#define LSB_FIRST     1
+#define SOUND_PRESENT 1
+//#define ALIGN_LONG 1
+#define GENESIS_HACKS 1
+
+
+typedef unsigned char uint8;
+typedef unsigned short int uint16;
+typedef unsigned long int uint32;
+
+typedef signed char int8;
+typedef signed short int int16;
+typedef signed long int int32;
+
+typedef unsigned char UINT8;
+typedef unsigned short int UINT16;
+typedef unsigned long int UINT32;
+
+typedef signed char INT8;
+typedef signed short int INT16;
+typedef signed long int INT32;
+
+
+
+#include <stdio.h>
+#include "macros.h"
+#include "m68k.h"
+#include "z80.h"
+#include "genesis.h"
+#include "vdp.h"
+#include "render.h"
+#include "mem68k.h"
+#include "memz80.h"
+#include "membnk.h"
+#include "memvdp.h"
+#include "system.h"
+#include "io.h"
+#include "sound.h"
+#include "fm.h"
+#include "sn76496.h"
+#include "memory.h"
+
+#define __inline__
+#define error(...)
+
+
+
+#endif /* _SHARED_H_ */
diff --git a/MCUME_pico2/picogenold/sn76496.c b/MCUME_pico2/picogenold/sn76496.c
new file mode 100644
index 0000000..575101f
--- /dev/null
+++ b/MCUME_pico2/picogenold/sn76496.c
@@ -0,0 +1,273 @@
+
+#include "shared.h"
+
+#define MAX_OUTPUT  0x7fff
+#define STEP        0x10000
+#define FB_WNOISE   0x12000
+#define FB_PNOISE   0x08000
+#define NG_PRESET   0x0F35
+
+struct SN76496
+{
+	int SampleRate;
+	unsigned int UpdateStep;
+    int VolTable[16];
+    int Register[8];
+    int LastRegister;
+    int Volume[4];
+    unsigned int RNG;
+    int NoiseFB;
+	int Period[4];
+	int Count[4];
+	int Output[4];
+};
+
+
+struct SN76496 sn[MAX_76496];
+
+
+
+void SN76496Write(int chip,int data)
+{
+	struct SN76496 *R = &sn[chip];
+
+	if (data & 0x80)
+	{
+		int r = (data & 0x70) >> 4;
+		int c = r/2;
+
+		R->LastRegister = r;
+		R->Register[r] = (R->Register[r] & 0x3f0) | (data & 0x0f);
+		switch (r)
+		{
+			case 0:	/* tone 0 : frequency */
+			case 2:	/* tone 1 : frequency */
+			case 4:	/* tone 2 : frequency */
+				R->Period[c] = R->UpdateStep * R->Register[r];
+				if (R->Period[c] == 0) R->Period[c] = R->UpdateStep;
+				if (r == 4)
+				{
+					/* update noise shift frequency */
+					if ((R->Register[6] & 0x03) == 0x03)
+						R->Period[3] = 2 * R->Period[2];
+				}
+				break;
+			case 1:	/* tone 0 : volume */
+			case 3:	/* tone 1 : volume */
+			case 5:	/* tone 2 : volume */
+			case 7:	/* noise  : volume */
+				R->Volume[c] = R->VolTable[data & 0x0f];
+				break;
+			case 6:	/* noise  : frequency, mode */
+				{
+					int n = R->Register[6];
+					R->NoiseFB = (n & 4) ? FB_WNOISE : FB_PNOISE;
+					n &= 3;
+					/* N/512,N/1024,N/2048,Tone #3 output */
+					R->Period[3] = (n == 3) ? 2 * R->Period[2] : (R->UpdateStep << (5+n));
+
+					/* reset noise shifter */
+					R->RNG = NG_PRESET;
+					R->Output[3] = R->RNG & 1;
+				}
+				break;
+		}
+	}
+	else
+	{
+		int r = R->LastRegister;
+		int c = r/2;
+
+		switch (r)
+		{
+			case 0:	/* tone 0 : frequency */
+			case 2:	/* tone 1 : frequency */
+			case 4:	/* tone 2 : frequency */
+				R->Register[r] = (R->Register[r] & 0x0f) | ((data & 0x3f) << 4);
+				R->Period[c] = R->UpdateStep * R->Register[r];
+				if (R->Period[c] == 0) R->Period[c] = R->UpdateStep;
+				if (r == 4)
+				{
+					/* update noise shift frequency */
+					if ((R->Register[6] & 0x03) == 0x03)
+						R->Period[3] = 2 * R->Period[2];
+				}
+				break;
+		}
+	}
+}
+
+
+void SN76496Update(int chip,signed short int *buffer,int length)
+{
+	int i;
+	struct SN76496 *R = &sn[chip];
+
+
+	/* If the volume is 0, increase the counter */
+	for (i = 0;i < 4;i++)
+	{
+		if (R->Volume[i] == 0)
+		{
+			/* note that I do count += length, NOT count = length + 1. You might think */
+			/* it's the same since the volume is 0, but doing the latter could cause */
+			/* interferencies when the program is rapidly modulating the volume. */
+			if (R->Count[i] <= length*STEP) R->Count[i] += length*STEP;
+		}
+	}
+
+	while (length > 0)
+	{
+		int vol[4];
+		unsigned int out;
+		int left;
+
+
+		/* vol[] keeps track of how long each square wave stays */
+		/* in the 1 position during the sample period. */
+		vol[0] = vol[1] = vol[2] = vol[3] = 0;
+
+		for (i = 0;i < 3;i++)
+		{
+			if (R->Output[i]) vol[i] += R->Count[i];
+			R->Count[i] -= STEP;
+			/* Period[i] is the half period of the square wave. Here, in each */
+			/* loop I add Period[i] twice, so that at the end of the loop the */
+			/* square wave is in the same status (0 or 1) it was at the start. */
+			/* vol[i] is also incremented by Period[i], since the wave has been 1 */
+			/* exactly half of the time, regardless of the initial position. */
+			/* If we exit the loop in the middle, Output[i] has to be inverted */
+			/* and vol[i] incremented only if the exit status of the square */
+			/* wave is 1. */
+			while (R->Count[i] <= 0)
+			{
+				R->Count[i] += R->Period[i];
+				if (R->Count[i] > 0)
+				{
+					R->Output[i] ^= 1;
+					if (R->Output[i]) vol[i] += R->Period[i];
+					break;
+				}
+				R->Count[i] += R->Period[i];
+				vol[i] += R->Period[i];
+			}
+			if (R->Output[i]) vol[i] -= R->Count[i];
+		}
+
+		left = STEP;
+		do
+		{
+			int nextevent;
+
+
+			if (R->Count[3] < left) nextevent = R->Count[3];
+			else nextevent = left;
+
+			if (R->Output[3]) vol[3] += R->Count[3];
+			R->Count[3] -= nextevent;
+			if (R->Count[3] <= 0)
+			{
+				if (R->RNG & 1) R->RNG ^= R->NoiseFB;
+				R->RNG >>= 1;
+				R->Output[3] = R->RNG & 1;
+				R->Count[3] += R->Period[3];
+				if (R->Output[3]) vol[3] += R->Period[3];
+			}
+			if (R->Output[3]) vol[3] -= R->Count[3];
+
+			left -= nextevent;
+		} while (left > 0);
+
+		out = vol[0] * R->Volume[0] + vol[1] * R->Volume[1] +
+				vol[2] * R->Volume[2] + vol[3] * R->Volume[3];
+
+		if (out > MAX_OUTPUT * STEP) out = MAX_OUTPUT * STEP;
+
+		*(buffer++) = out / STEP;
+
+		length--;
+	}
+}
+
+
+
+void SN76496_set_clock(int chip,int clock)
+{
+	struct SN76496 *R = &sn[chip];
+
+
+	/* the base clock for the tone generators is the chip clock divided by 16; */
+	/* for the noise generator, it is clock / 256. */
+	/* Here we calculate the number of steps which happen during one sample */
+	/* at the given sample rate. No. of events = sample rate / (clock/16). */
+	/* STEP is a multiplier used to turn the fraction into a fixed point */
+	/* number. */
+	R->UpdateStep = ((double)STEP * R->SampleRate * 16) / clock;
+}
+
+
+
+void SN76496_set_gain(int chip,int gain)
+{
+	struct SN76496 *R = &sn[chip];
+	int i;
+	double out;
+
+
+	gain &= 0xff;
+
+	/* increase max output basing on gain (0.2 dB per step) */
+	out = MAX_OUTPUT / 3;
+	while (gain-- > 0)
+		out *= 1.023292992;	/* = (10 ^ (0.2/20)) */
+
+	/* build volume table (2dB per step) */
+	for (i = 0;i < 15;i++)
+	{
+		/* limit volume to avoid clipping */
+		if (out > MAX_OUTPUT / 3) R->VolTable[i] = MAX_OUTPUT / 3;
+		else R->VolTable[i] = out;
+
+		out /= 1.258925412;	/* = 10 ^ (2/20) = 2dB */
+	}
+	R->VolTable[15] = 0;
+}
+
+
+
+int SN76496_init(int chip,int clock,int volume,int sample_rate)
+{
+	int i;
+	struct SN76496 *R = &sn[chip];
+
+	R->SampleRate = sample_rate;
+	SN76496_set_clock(chip,clock);
+
+	for (i = 0;i < 4;i++) R->Volume[i] = 0;
+
+	R->LastRegister = 0;
+	for (i = 0;i < 8;i+=2)
+	{
+		R->Register[i] = 0;
+		R->Register[i + 1] = 0x0f;	/* volume = 0 */
+	}
+
+	for (i = 0;i < 4;i++)
+	{
+		R->Output[i] = 0;
+		R->Period[i] = R->Count[i] = R->UpdateStep;
+	}
+	R->RNG = NG_PRESET;
+	R->Output[3] = R->RNG & 1;
+
+	return 0;
+}
+
+
+
+int SN76496_sh_start(int clock, int volume, int rate)
+{
+    SN76496_init(0, clock, volume & 0xff, rate);
+    SN76496_set_gain(0, (volume >> 8) & 0xff);
+	return 0;
+}
diff --git a/MCUME_pico2/picogenold/sn76496.h b/MCUME_pico2/picogenold/sn76496.h
new file mode 100644
index 0000000..58fd388
--- /dev/null
+++ b/MCUME_pico2/picogenold/sn76496.h
@@ -0,0 +1,21 @@
+#ifndef SN76496_H
+#define SN76496_H
+
+#define MAX_76496 1
+
+struct SN76496interface
+{
+    int num;
+	int baseclock[MAX_76496];
+	int volume[MAX_76496];
+};
+
+/* Function prototypes */
+void SN76496Write(int chip,int data);
+void SN76496Update(int chip,signed short int *buffer,int length);
+void SN76496_set_clock(int chip,int clock);
+void SN76496_set_gain(int chip,int gain);
+int SN76496_init(int chip,int clock,int volume,int sample_rate);
+int SN76496_sh_start(int clock, int volume, int rate);
+
+#endif
diff --git a/MCUME_pico2/picogenold/sound.c b/MCUME_pico2/picogenold/sound.c
new file mode 100644
index 0000000..85f20e7
--- /dev/null
+++ b/MCUME_pico2/picogenold/sound.c
@@ -0,0 +1,170 @@
+/*
+    sound.c
+    YM2612 and SN76489 emulation
+*/
+
+#include "shared.h"
+
+/* YM2612 data */
+int fm_timera_tab[0x400];   /* Precalculated timer A values */
+int fm_timerb_tab[0x100];   /* Precalculated timer B values */
+uint8 fm_reg[2][0x100];     /* Register arrays (2x256) */
+uint8 fm_latch[2];          /* Register latches */
+uint8 fm_status;            /* Read-only status flags */
+t_timer timer[2];           /* Timers A and B */
+
+/* Initialize the YM2612 and SN76489 emulation */
+void sound_init(void)
+{
+    /* Timers run at half the YM2612 input clock */
+    float clock = ((53.693175 / 7) / 2);
+    int i;
+
+    /* Make Timer A table */
+    for(i = 0; i < 1024; i += 1)
+    {
+      /* Formula is "time(us) = 72 * (1024 - A) / clock" */
+      fm_timera_tab[i] = ((int)(float)(72 * (1024 - i)) / (clock));
+    }
+
+    /* Make Timer B table */
+    for(i = 0; i < 256; i += 1)
+    {
+        /* Formula is "time(us) = 1152 * (256 - B) / clock" */
+        fm_timerb_tab[i] = (int)(float)(1152 * (256 - i)) / clock;
+    }
+}
+
+void sound_reset(void)
+{
+    if(snd.enabled)
+    {
+        YM2612ResetChip(0);
+    }
+}
+
+void fm_write(int address, int data)
+{
+    int a0 = (address & 1);
+    int a1 = (address >> 1) & 1;
+
+    if(a0)
+    {
+        /* Register data */
+        fm_reg[a1][fm_latch[a1]] = data;
+
+        /* Timer control only in set A */
+        if(a1 == 0)
+        switch(fm_latch[a1])
+        {
+            case 0x24: /* Timer A (LSB) */
+                timer[0].index = (timer[0].index & 0x0003) | (data << 2);
+                timer[0].index &= 0x03FF;
+                timer[0].base = fm_timera_tab[timer[0].index];
+                break;
+
+            case 0x25: /* Timer A (MSB) */
+                timer[0].index = (timer[0].index & 0x03FC) | (data & 3);
+                timer[0].index &= 0x03FF;
+                timer[0].base = fm_timera_tab[timer[0].index];
+                break;
+            
+            case 0x26: /* Timer B */
+                timer[1].index = data;
+                timer[1].base = timer[1].count = fm_timerb_tab[timer[1].index];
+                break;
+ 
+            case 0x27: /* Timer Control */
+
+                /* LOAD */
+                timer[0].running = (data >> 0) & 1;
+                if(timer[0].running) timer[0].count = 0;
+                timer[1].running = (data >> 1) & 1;
+                if(timer[1].running) timer[1].count = 0;
+
+                /* ENABLE */
+                timer[0].enable = (data >> 2) & 1;
+                timer[1].enable = (data >> 3) & 1;
+
+                /* RESET */
+                if(data & 0x10) fm_status &= ~1;
+                if(data & 0x20) fm_status &= ~2;
+                break;
+        }
+    }
+    else
+    {
+        /* Register latch */
+        fm_latch[a1] = data;
+    }
+
+    if(snd.enabled)
+    {
+        if(snd.fm.curStage - snd.fm.lastStage > 1)
+        {
+            int16 *tempBuffer[2];       
+            tempBuffer[0] = snd.fm.buffer[0] + snd.fm.lastStage;
+            tempBuffer[1] = snd.fm.buffer[1] + snd.fm.lastStage;
+            YM2612UpdateOne(0, (int16 **)tempBuffer, snd.fm.curStage - snd.fm.lastStage);
+            snd.fm.lastStage = snd.fm.curStage;
+        }
+
+        YM2612Write(0, address & 3, data);
+    }
+}
+
+
+int fm_read(int address)
+{
+    return (fm_status);
+}
+
+
+void fm_update_timers(void)
+{
+    int i;    
+
+    /* Process YM2612 timers */
+    for(i = 0; i < 2; i += 1)
+    {
+        /* Is the timer running? */
+        if(timer[i].running)
+        {
+            /* Each scanline takes up roughly 64 microseconds */
+            timer[i].count += 64;
+
+            /* Check if the counter overflowed */
+            if(timer[i].count > timer[i].base)
+            {
+                /* Reload counter */
+                timer[i].count = 0;
+
+                /* Disable timer */
+                timer[i].running = 0;
+
+                /* Set overflow flag (if flag setting is enabled) */
+                if(timer[i].enable)
+                {
+                    fm_status |= (1 << i);
+                }
+            }
+        }
+    }
+}
+
+void psg_write(int data)
+{
+    if(snd.enabled)
+    {
+        if(snd.psg.curStage - snd.psg.lastStage > 1)
+        {
+            int16 *tempBuffer;
+            tempBuffer = snd.psg.buffer + snd.psg.lastStage;
+            SN76496Update(0, tempBuffer, snd.psg.curStage - snd.psg.lastStage);
+            snd.psg.lastStage = snd.psg.curStage;
+        }
+
+        SN76496Write(0, data);
+    }
+}
+
diff --git a/MCUME_pico2/picogenold/sound.h b/MCUME_pico2/picogenold/sound.h
new file mode 100644
index 0000000..0a5a998
--- /dev/null
+++ b/MCUME_pico2/picogenold/sound.h
@@ -0,0 +1,30 @@
+
+#ifndef _SOUND_H_
+#define _SOUND_H_
+
+typedef struct
+{
+    int running;
+    int enable;
+    int count;
+    int base;
+    int index;
+} t_timer;
+
+/* Global variables */
+extern int fm_timera_tab[1024];
+extern int fm_timerb_tab[256];
+extern uint8 fm_reg[2][0x100];
+extern uint8 fm_latch[2];
+extern int timer_status;
+extern t_timer timer[2];
+
+/* Function prototypes */
+void sound_init(void);
+void sound_reset(void);
+void fm_write(int address, int data);
+int fm_read(int address);
+void fm_update_timers(void);
+void psg_write(int data);
+
+#endif /* _SOUND_H_ */
diff --git a/MCUME_pico2/picogenold/system.c b/MCUME_pico2/picogenold/system.c
new file mode 100644
index 0000000..e6f18a2
--- /dev/null
+++ b/MCUME_pico2/picogenold/system.c
@@ -0,0 +1,256 @@
+/*
+    Copyright (C) 1999, 2000, 2001, 2002, 2003  Charles MacDonald
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include "shared.h"
+
+t_bitmap gbitmap;
+t_input input;
+t_snd snd;
+static int sound_tbl[262];
+
+#define SND_SIZE (snd.buffer_size * sizeof(int16))
+
+
+int audio_init(int rate)
+{
+    int i;
+
+    /* 68000 and YM2612 clock */
+    float vclk = 53693175.0 / 7;
+
+    /* Z80 and SN76489 clock */
+    float zclk = 3579545.0;
+
+    /* Clear the sound data context */
+    memset(&snd, 0, sizeof(snd));
+
+    /* Make sure the requested sample rate is valid */
+    if(!rate || ((rate < 8000) | (rate > 44100)))
+    {
+        return (0);
+    }
+
+    /* Calculate the sound buffer size */
+    snd.buffer_size = (rate / 60);
+    snd.sample_rate = rate;
+
+    /* Allocate sound buffers */
+    snd.fm.buffer[0] = emu_Malloc(SND_SIZE);
+    snd.fm.buffer[1] = emu_Malloc(SND_SIZE);
+    snd.psg.buffer = emu_Malloc(SND_SIZE);
+
+    /* Make sure we could allocate everything */
+    if(!snd.fm.buffer[0] || !snd.fm.buffer[1] || !snd.psg.buffer)
+    {
+        return (0);
+    }
+
+    /* Initialize sound chip emulation */
+    SN76496_sh_start(zclk, 100, rate);
+    YM2612Init(1, vclk, rate, NULL, NULL);
+
+    /* Set audio enable flag */
+    snd.enabled = 1;
+
+    /* Make sound table */
+    for (i = 0; i < 262; i++)
+    {
+        float p = snd.buffer_size * i;
+        p = p / 262;
+    	sound_tbl[i] = p;
+    }    	
+
+    return (0);    
+}
+
+void system_init(void)
+{
+    gen_init();
+    vdp_init();
+    render_init();
+}
+
+void system_reset(void)
+{
+    gen_reset();
+    vdp_reset();
+    render_reset();
+
+    if(snd.enabled)
+    {      
+        YM2612ResetChip(0);
+        //memset(snd.buffer[0], 0, SND_SIZE);
+        //memset(snd.buffer[1], 0, SND_SIZE);
+        memset(snd.fm.buffer[0], 0, SND_SIZE);
+        memset(snd.fm.buffer[1], 0, SND_SIZE);
+        memset(snd.psg.buffer, 0, SND_SIZE);
+    }
+}
+
+void system_shutdown(void)
+{
+    gen_shutdown();
+    vdp_shutdown();
+    render_shutdown();
+}
+
+
+int system_frame(int do_skip)
+{
+    int line;
+
+    if(gen_running == 0)
+        return 0;
+
+    /* Clear V-Blank flag */
+    status &= ~0x0008;
+
+    /* Toggle even/odd flag (IM2 only) */
+    if(im2_flag)
+        status ^= 0x0010;
+
+    /* Point to start of sound buffer */
+    snd.fm.lastStage = snd.fm.curStage = 0;
+    snd.psg.lastStage = snd.psg.curStage = 0;
+
+    /* Parse sprites for line 0 (done on line 261) */
+    parse_satb(0x80);
+
+    for(line = 0; line < 262; line += 1)
+    {
+        /* Used by HV counter */
+        v_counter = line;
+
+        /* Run 68000 emulation */
+        m68k_execute(487);
+        if(!gen_running) break;
+
+        /* Run Z80 emulation (if enabled) */
+        if(zreset == 1 && zbusreq == 0)
+        {
+//            z80_execute(228);
+            if(!gen_running) break;
+        }
+
+        /* If a Z80 interrupt is still pending after a scanline, cancel it */
+        if(zirq == 1)
+        {
+            zirq = 0;
+            z80_set_irq_line(0, CLEAR_LINE);
+        }
+
+        /* Render a line of the display */
+        if(do_skip == 0)
+        {
+            if(line <  frame_end   ) render_line(line);
+            if(line <  frame_end-1 ) parse_satb(0x81 + line);
+        }
+
+        /* Do H interrupt processing */
+        if(line <= frame_end)
+        {
+            counter -= 1;
+            if(counter == -1)
+            {
+                counter = reg[10];
+                hint_pending = 1;
+                if(reg[0] & 0x10)
+                {
+                    m68k_set_irq(4);
+                }
+            }
+        }
+        else
+        {
+            counter = reg[10];
+        }
+
+        /* Do end of frame processing */
+        if(line == frame_end)
+        {
+            status |= 0x0088;
+            vint_pending = 1;
+
+            /* Give enough time to read the interrupt pending flag before
+               the interrupt actually occurs. */
+            m68k_execute(16);
+            if(!gen_running) break;
+
+            if(reg[1] & 0x20)
+            {
+                m68k_set_irq(6);
+            }
+
+            if(zreset == 1 && zbusreq == 0)
+            {
+                z80_set_irq_line(0, ASSERT_LINE);
+                zirq = 1;
+            }
+        }
+ 
+        fm_update_timers();
+
+        snd.fm.curStage = sound_tbl[line];
+        snd.psg.curStage = sound_tbl[line];
+    }
+
+    if(snd.enabled)
+    {
+        audio_update();
+    }
+
+    return gen_running;
+}
+
+void audio_update(void)
+{
+}
+
+void audio_play_sample(int16 *bufl, int16 *bufr, int length)
+{
+    int i;
+    int16 acc;
+ 
+    length = length/2;
+
+
+    int16 *tempBuffer[2];
+    tempBuffer[0] = snd.fm.buffer[0];
+    tempBuffer[1] = snd.fm.buffer[1];
+    YM2612UpdateOne(0, (int16 **)tempBuffer, length);
+    
+    tempBuffer[0] = snd.psg.buffer;
+    SN76496Update(0, tempBuffer[0], length);
+
+    for(i = 0; i < length /*snd.buffer_size*/; i += 1)
+    {
+        int16 psg = snd.psg.buffer[i] / 2;
+
+        acc = 0;
+        acc += snd.fm.buffer[0][i];
+        acc += psg;
+        //snd.buffer[0][i] = acc;
+        *bufl++ = acc;
+        
+        acc = 0;
+        acc += snd.fm.buffer[1][i];
+        acc += psg;
+        //snd.buffer[1][i] = acc;
+        *bufl++ = acc;
+    }
+}
diff --git a/MCUME_pico2/picogenold/system.h b/MCUME_pico2/picogenold/system.h
new file mode 100644
index 0000000..9ad1a7e
--- /dev/null
+++ b/MCUME_pico2/picogenold/system.h
@@ -0,0 +1,85 @@
+
+#ifndef _SYSTEM_H_
+#define _SYSTEM_H_
+
+/* Input devices */
+#define MAX_DEVICES         (8)     /* Unsure of maximum */
+#define DEVICE_2BUTTON      (0)     /* 2-button gamepad */
+#define DEVICE_3BUTTON      (1)     /* 3-button gamepad */
+#define DEVICE_6BUTTON      (2)     /* 6-button gamepad */
+
+/* Input bitmasks */
+#define INPUT_MODE      (0x00000800)
+#define INPUT_Z         (0x00000400)
+#define INPUT_Y         (0x00000200)
+#define INPUT_X         (0x00000100)
+#define INPUT_START     (0x00000080)
+#define INPUT_C         (0x00000040)
+#define INPUT_B         (0x00000020)
+#define INPUT_A         (0x00000010)
+#define INPUT_LEFT      (0x00000008)
+#define INPUT_RIGHT     (0x00000004)
+#define INPUT_DOWN      (0x00000002)
+#define INPUT_UP        (0x00000001)
+
+typedef struct
+{
+//    uint8 *data;        /* Bitmap data */
+    int width;          /* Bitmap width (32+512+32) */
+    int height;         /* Bitmap height (256) */
+//    int depth;          /* Color depth (8 bits) */
+    int pitch;          /* Width of bitmap in bytes */
+//    int granularity;    /* Size of each pixel in bytes */
+//    int remap;          /* 1= Translate pixel data */
+    struct {
+        int x;          /* X offset of viewport within bitmap */
+        int y;          /* Y offset of viewport within bitmap */
+        int w;          /* Width of viewport */
+        int h;          /* Height of viewport */
+        int ow;         /* Previous width of viewport */
+        int oh;         /* Previous height of viewport */
+        int changed;    /* 1= Viewport width or height have changed */
+    }viewport;
+}t_bitmap;  
+
+typedef struct
+{
+    uint8 dev[MAX_DEVICES];     /* Can be any of the DEVICE_* values */
+    uint32 pad[MAX_DEVICES];    /* Can be any of the INPUT_* bitmasks */
+    uint32 system;              /* Can be any of the SYSTEM_* bitmasks */
+}t_input;
+
+typedef struct
+{
+    int sample_rate;    /* Sample rate (8000-44100) */
+    int enabled;        /* 1= sound emulation is enabled */
+    int buffer_size;    /* Size of sound buffer (in bytes) */
+    int16 *buffer[2];   /* Signed 16-bit stereo sound data */
+    struct {
+        int curStage;
+        int lastStage;
+        int16 *buffer[2];   
+    } fm;
+    struct {
+        int curStage;
+        int lastStage;
+        int16 *buffer;   
+    } psg;
+}t_snd;
+
+/* Global variables */
+extern t_bitmap gbitmap;
+extern t_input input;
+extern t_snd snd;
+
+/* Function prototypes */
+void system_init(void);
+int system_frame(int skip);
+void system_reset(void);
+void system_shutdown(void);
+int audio_init(int rate);
+void audio_update(void);
+void audio_play_sample(int16 *bufl, int16 *bufr, int length);
+
+#endif /* _SYSTEM_H_ */
+
diff --git a/MCUME_pico2/picogenold/vcnt.h b/MCUME_pico2/picogenold/vcnt.h
new file mode 100644
index 0000000..f32b07f
--- /dev/null
+++ b/MCUME_pico2/picogenold/vcnt.h
@@ -0,0 +1,26 @@
+
+#ifndef _VCNT_H_
+#define _VCNT_H_
+
+static const char vc28[262] =
+{
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 
+	0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 
+	0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 
+	0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 
+	0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 
+	0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 
+	0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 
+        0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+};
+
+#endif /* _VCNT_H_ */
diff --git a/MCUME_pico2/picogenold/vdp.c b/MCUME_pico2/picogenold/vdp.c
new file mode 100644
index 0000000..85a57ad
--- /dev/null
+++ b/MCUME_pico2/picogenold/vdp.c
@@ -0,0 +1,557 @@
+
+#include "shared.h"
+#include "vcnt.h"
+#include "hcnt.h"
+#include "hvc.h"
+
+/* Pack and unpack CRAM data */
+#define PACK_CRAM(d)    ((((d)&0xE00)>>9)|(((d)&0x0E0)>>2)|(((d)&0x00E)<<5))
+#define UNPACK_CRAM(d)  ((((d)&0x1C0)>>5)|((d)&0x038)<<2|(((d)&0x007)<<9))
+
+/* Mark a pattern as dirty */
+#define MARK_BG_DIRTY(addr)                                     \
+{                                                               \
+    int name = (addr >> 5) & 0x7FF;                             \
+    if(bg_name_dirty[name] == 0)                                \
+    {                                                           \
+        bg_name_list[bg_list_index] = name;                     \
+        bg_list_index += 1;                                     \
+    }                                                           \
+    bg_name_dirty[name] |= (1 << ((addr >> 2) & 0x07));         \
+}
+
+/* Tables that define the playfield layout */
+uint8 shift_table[] = {6, 7, 0, 8};
+uint8 col_mask_table[] = {0x1F, 0x3F, 0x1F, 0x7F};
+uint16 row_mask_table[] = {0x0FF, 0x1FF, 0x2FF, 0x3FF};
+uint32 y_mask_table[] = {0x1FC0, 0x1FC0, 0x1F80, 0x1F00};
+
+uint8 sat[0x400];               /* Internal copy of sprite attribute table */
+//uint8 vram[0x10000];            /* Video RAM (64Kx8) */
+uint8 cram[0x80];               /* On-chip color RAM (64x9) */
+uint8 vsram[0x80];              /* On-chip vertical scroll RAM (40x11) */
+uint8 reg[0x20];                /* Internal VDP registers (23x8) */
+uint16 addr;                    /* Address register */
+uint16 addr_latch;              /* Latched A15, A14 of address */
+uint8 code;                     /* Code register */
+uint8 pending;                  /* Pending write flag */
+uint16 buffer;                  /* Read buffer */
+uint16 status;                  /* VDP status flags */
+uint16 ntab;                    /* Name table A base address */
+uint16 ntbb;                    /* Name table B base address */
+uint16 ntwb;                    /* Name table W base address */
+uint16 satb;                    /* Sprite attribute table base address */
+uint16 hscb;                    /* Horizontal scroll table base address */
+uint16 sat_base_mask;           /* Base bits of SAT */
+uint16 sat_addr_mask;           /* Index bits of SAT */
+uint8 is_color_dirty;           /* 1= One or more colors have changed */
+uint8 color_dirty[0x40];        /* 1= This color is dirty */
+uint8 border;                   /* Border color index */
+uint8 is_border_dirty;          /* 1= The border color has changed */
+//uint8 bg_name_dirty[0x800];     /* 1= This pattern is dirty */
+//uint16 bg_name_list[0x800];     /* List of modified pattern indices */
+uint16 bg_list_index;           /* # of modified patterns in list */
+//uint8 bg_pattern_cache[0x80000];/* Cached and flipped patterns */
+uint8 playfield_shift;          /* Width of planes A, B (in bits) */
+uint8 playfield_col_mask;       /* Vertical scroll mask */
+uint16 playfield_row_mask;      /* Horizontal scroll mask */
+uint32 y_mask;                  /* Name table Y-index bits mask */
+int hint_pending;               /* 0= Line interrupt is pending */
+int vint_pending;               /* 1= Frame interrupt is pending */
+int counter;                    /* Raster counter */
+int dma_fill;                   /* 1= DMA fill has been requested */
+int im2_flag;                   /* 1= Interlace mode 2 is being used */
+int frame_end;                  /* End-of-frame (IRQ line) */
+int v_counter;                  /* VDP scan line counter */
+int v_update;                  /* 1= VC was updated by a ctrl or HV read */
+void (*color_update)(int index, uint16 data);
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown functions                                          */
+/*--------------------------------------------------------------------------*/
+
+void vdp_init(void)
+{
+}
+
+void vdp_reset(void)
+{
+    memset(sat, 0, sizeof(sat));
+    memset(vram, 0, VRAM_SIZE);
+    memset(cram, 0, sizeof(cram));
+    memset(vsram, 0, sizeof(vsram));
+    memset(reg, 0, sizeof(reg));
+
+    addr = addr_latch = code = pending = buffer = status = 0;
+    ntab = ntbb = ntwb = satb = hscb = 0;
+    sat_base_mask = 0xFE00;
+    sat_addr_mask = 0x01FF;
+
+    /* Mark all colors as dirty to force a palette update */
+    is_color_dirty = 1;
+    memset(color_dirty, 1, 0x40);
+    border = 0x00;
+    is_border_dirty = 1;
+
+    memset(bg_name_dirty, 0, BGNAMEDIRTY_SIZE);
+    memset(bg_name_list, 0, BGNAME_SIZE);
+    bg_list_index = 0;
+    memset(bg_pattern_cache, 0, BGPATTERN_CACH_SIZE);
+
+    playfield_shift = 6;
+    playfield_col_mask = 0x1F;
+    playfield_row_mask = 0x0FF;
+    y_mask = 0x1FC0;
+
+    hint_pending = vint_pending = 0;
+    counter = 0;
+    frame_end = 0xE0;
+    v_counter = v_update = 0;
+
+    /* Initialize viewport */
+    gbitmap.viewport.x = 0x20;
+    gbitmap.viewport.y = 0x20;
+    gbitmap.viewport.w = 256;
+    gbitmap.viewport.h = 224;
+    gbitmap.viewport.oh = 256;
+    gbitmap.viewport.ow = 224;
+    gbitmap.viewport.changed = 1;
+}
+
+void vdp_shutdown(void)
+{
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Memory access functions                                                  */
+/*--------------------------------------------------------------------------*/
+
+void vdp_ctrl_w(uint16 data)
+{
+    if(pending == 0)
+    {
+        if((data & 0xC000) == 0x8000)
+        {
+            uint8 r = (data >> 8) & 0x1F;
+            uint8 d = (data >> 0) & 0xFF;
+            vdp_reg_w(r, d);
+        }
+        else
+        {
+            pending = 1;
+        }
+
+        addr = ((addr_latch & 0xC000) | (data & 0x3FFF)) & 0xFFFF;
+        code = ((code & 0x3C) | ((data >> 14) & 0x03)) & 0x3F;
+    }
+    else
+    {
+        /* Clear pending flag */
+        pending = 0;
+
+        /* Update address and code registers */
+        addr = ((addr & 0x3FFF) | ((data & 3) << 14)) & 0xFFFF;
+        code = ((code & 0x03) | ((data >> 2) & 0x3C)) & 0x3F;
+
+        /* Save address bits A15 and A14 */
+        addr_latch = (addr & 0xC000);
+
+        if((code & 0x20) && (reg[1] & 0x10))
+        {
+            switch(reg[23] & 0xC0)
+            {
+                case 0x00: /* V bus to VDP DMA */
+                case 0x40: /* V bus to VDP DMA */
+                    dma_vbus();
+                    break;
+
+                case 0x80: /* VRAM fill */
+                    dma_fill = 1;
+                    break;
+
+                case 0xC0: /* VRAM copy */
+                    dma_copy();
+                    break;
+            }
+        }
+    }
+}
+
+uint16 vdp_ctrl_r(void)
+{
+#if 0
+    int cycles = m68k_cycles_run();
+    uint16 temp = status;
+
+    /* Clear pending flag */
+    pending = 0;
+
+    /* VBlank flag is set when the screen is disabled */
+    if((reg[1] & 0x40) == 0x00)
+    {
+        temp |= 0x0008;
+    }
+
+    /* Clear collision flag on reads */
+    status &= ~0x0020;
+
+    /* Set HBlank flag based on H counter */
+    if(reg[12] & 1)
+    {
+        int hc = cycle2hc40[(cycles % 487)];
+        if((hc >= 0xB6) && (hc <= 0xFF)) temp |= 0x0004;
+    }
+    else
+    {
+        int hc = cycle2hc32[(cycles % 487)];
+        if((hc >= 0x93) && (hc <= 0xFF)) temp |= 0x0004;
+    }
+
+    /* Flag FIFO as empty */
+    temp |= 0x0200;     
+
+    /* Clear unused bits */
+    temp &= 0x03FF;  
+
+    return (temp);
+#else
+    uint16 temp = (0x4e71 & 0xFC00);
+    pending = 0;
+    status &= ~0x0020; // clear sprite hit flag on reads
+    status |= 0x0200;  // fifo empty
+    status ^= 0x0004; /* hack (red zone) */
+    temp |= (status & 0x03BF); // clear spr over
+    return (temp);
+#endif
+}
+
+
+void vdp_data_w(uint16 data)
+{
+    /* Clear pending flag */
+    pending = 0;
+
+    switch(code & 0x0F)
+    {
+        case 0x01: /* VRAM */
+            /* Byte-swap data if A0 is set */
+            if(addr & 1) data = (data >> 8) | (data << 8);
+
+            /* Copy SAT data to the internal SAT */
+            if((addr & sat_base_mask) == satb)
+            {
+                *(uint16 *)&sat[addr & sat_addr_mask] = data;
+            }
+
+            /* Only write unique data to VRAM */
+            if(data != *(uint16 *)&vram[addr & 0xFFFE])
+            {
+                /* Write data to VRAM */
+                *(uint16 *)&vram[addr & 0xFFFE] = data;
+
+                /* Update the pattern cache */
+                MARK_BG_DIRTY(addr);
+            }
+            break;
+
+        case 0x03: /* CRAM */
+            {
+                uint16 *p = (uint16 *)&cram[(addr & 0x7E)];
+                data &= 0x0EEE;
+                if(data != *p)
+                {
+                    int index = (addr >> 1) & 0x3F;
+                    *p = PACK_CRAM(data);
+
+                    if((index & 0x0F) != 0x00)
+                    {
+                        color_dirty[index] = is_color_dirty = 1;
+                    }
+
+                    if(index == border)
+                    {
+                        is_border_dirty = 1;
+                        if(color_update)
+                        {
+                            color_update(0x00, *p);
+                            color_update(0x40, *p);
+                            color_update(0x80, *p);
+                        }
+                    }
+
+                    if(color_update) color_update(index, *p);
+                }
+            }
+            break;
+          
+        case 0x05: /* VSRAM */
+            *(uint16 *)&vsram[(addr & 0x7E)] = data;
+            break;
+    }
+
+    /* Bump address register */
+    addr += reg[15];
+
+    if(dma_fill)
+    {
+        int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
+        if(!length) length = 0x10000;
+
+        do {
+            vram[(addr & 0xFFFF)] = (data >> 8) & 0xFF;
+            MARK_BG_DIRTY(addr);
+            addr += reg[15];
+        } while(--length);
+        dma_fill = 0;
+    }
+}
+
+
+uint16 vdp_data_r(void)
+{
+    uint16 temp = 0;
+
+    /* Clear pending flag */
+    pending = 0;
+
+    switch(code & 0x0F)
+    {
+        case 0x00: /* VRAM */
+            temp = *(uint16 *)&vram[(addr & 0xFFFE)];
+            break;
+
+        case 0x08: /* CRAM */
+            temp = *(uint16 *)&cram[(addr & 0x7E)];
+            temp = UNPACK_CRAM(temp);
+            break;
+
+        case 0x04: /* VSRAM */
+            temp = *(uint16 *)&vsram[(addr & 0x7E)];
+            break;
+    }
+
+    /* Bump address register */
+    addr += reg[15];
+
+    /* return data */
+    return (temp);
+}
+
+
+/*
+    The reg[] array is updated at the *end* of this function, so the new
+    register data can be compared with the previous data.
+*/
+void vdp_reg_w(uint8 r, uint8 d)
+{
+    switch(r)
+    {
+        case 0x00: /* CTRL #1 */
+
+            if(hint_pending)
+            {
+                if(d & 0x10)
+                {
+                    m68k_set_irq(4);
+                }
+                else
+                {
+                    /* Cancel pending level 4 interrupt */
+                    m68k_set_irq(0);
+                }
+            }
+            break;
+
+        case 0x01: /* CTRL #2 */
+
+            if(vint_pending)
+            {
+                if(d & 0x20)
+                {
+                    m68k_set_irq(6);
+                }
+                else
+                {
+                    /* Cancel pending level 6 interrupt */
+                    m68k_set_irq(0);
+                }
+            }
+
+            /* Change the frame timing */
+            frame_end = (d & 8) ? 0xF0 : 0xE0;
+
+            /* Check if the viewport height has actually been changed */
+            if((reg[1] & 8) != (d & 8))
+            {                
+                /* Update the height of the viewport */
+                gbitmap.viewport.oh = gbitmap.viewport.h;
+                gbitmap.viewport.h = (d & 8) ? 240 : 224;
+                gbitmap.viewport.changed = 1;                
+            }
+            break;
+
+        case 0x02: /* NTAB */
+            ntab = (d << 10) & 0xE000;
+            break;
+
+        case 0x03: /* NTWB */
+            ntwb = (d << 10) & 0xF800;
+            if(reg[12] & 1) ntwb &= 0xF000;
+            break;
+
+        case 0x04: /* NTBB */
+            ntbb = (d << 13) & 0xE000;
+            break;
+
+        case 0x05: /* SATB */
+            sat_base_mask = (reg[12] & 1) ? 0xFC00 : 0xFE00;
+            sat_addr_mask = (reg[12] & 1) ? 0x03FF : 0x01FF;
+            satb = (d << 9) & sat_base_mask;
+            break;
+
+        case 0x07:
+            d &= 0x3F;
+
+            /* Check if the border color has actually changed */
+            if(border != d)
+            {
+                /* Mark the border color as modified */
+                border = d;
+                is_border_dirty = 1;
+                if(color_update)
+                {
+                    color_update(0x00, *(uint16 *)&cram[(border << 1)]);
+                    color_update(0x40, *(uint16 *)&cram[(border << 1)]);
+                    color_update(0x80, *(uint16 *)&cram[(border << 1)]);
+                }
+            }
+            break;
+
+        case 0x0C:
+
+            /* Check if the viewport width has actually been changed */
+            if((reg[0x0C] & 1) != (d & 1))
+            {
+                /* Update the width of the viewport */
+                gbitmap.viewport.ow = gbitmap.viewport.w;
+                gbitmap.viewport.w = (d & 1) ? 320 : 256;
+                gbitmap.viewport.changed = 1;
+            }
+
+            /* See if the S/TE mode bit has changed */
+            if((reg[0x0C] & 8) != (d & 8))
+            {
+                int i;
+                reg[0x0C] = d;
+
+                /* Update colors */
+                if(color_update)
+                {
+                    for(i = 0; i < 0x40; i += 1)
+                    {
+                        color_update(i, *(uint16 *)&cram[i << 1]);                    
+                    }
+                    color_update(0x00, *(uint16 *)&cram[border << 1]);
+                    color_update(0x40, *(uint16 *)&cram[border << 1]);
+                    color_update(0x80, *(uint16 *)&cram[border << 1]);
+                }
+                /* Flush palette */
+                is_color_dirty = is_border_dirty = 1;
+                memset(color_dirty, 1, 0x40);                    
+            }
+
+            /* Check interlace mode 2 setting */
+            im2_flag = ((d & 0x06) == 0x06) ? 1 : 0;
+
+            /* The following register updates check this value */
+            reg[0x0C] = d;
+
+            /* Update display-dependant registers */
+            vdp_reg_w(0x03, reg[0x03]);
+            vdp_reg_w(0x05, reg[0x05]);
+
+            break;
+
+        case 0x0D: /* HSCB */
+            hscb = (d << 10) & 0xFC00;
+            break;
+
+        case 0x10: /* Playfield size */
+            playfield_shift = shift_table[(d & 3)];
+            playfield_col_mask = col_mask_table[(d & 3)];
+            playfield_row_mask = row_mask_table[(d >> 4) & 3];
+            y_mask = y_mask_table[(d & 3)];
+            break;
+    }
+
+    /* Write new register value */
+    reg[r] = d;
+}
+
+
+uint16 vdp_hvc_r(void)
+{
+    int cycles = m68k_cycles_run();
+    uint8 *hctab = (reg[12] & 1) ? cycle2hc40 : cycle2hc32;
+    int vc = vc28[v_counter];
+    int hc = hctab[(cycles % 487)];
+    return (vc << 8 | hc);
+}
+
+/*
+    VRAM to VRAM copy
+    Read byte from VRAM (source), write to VRAM (addr),
+    bump source and add r15 to addr.
+
+    - see how source addr is affected
+      (can it make high source byte inc?)
+*/
+void dma_copy(void)
+{
+    int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
+    int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
+    if(!length) length = 0x10000;
+
+    do {
+        uint8 temp = vram[source];
+        vram[addr] = temp;
+        MARK_BG_DIRTY(addr);
+        source = (source + 1) & 0xFFFF;
+        addr = (addr + reg[15]) & 0xFFFF;
+    } while (--length);
+
+    reg[19] = (length >> 0) & 0xFF;
+    reg[20] = (length >> 8) & 0xFF;
+}
+
+
+void dma_vbus(void)
+{
+    uint32 base, source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
+    uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
+
+    if(!length) length = 0x10000;
+    base = source;
+
+    do {
+        uint16 temp = vdp_dma_r(source);
+        source += 2;
+        source = ((base & 0xFE0000) | (source & 0x1FFFF));
+        vdp_data_w(temp);
+    } while (--length);
+
+    reg[19] = (length >> 0) & 0xFF;
+    reg[20] = (length >> 8) & 0xFF;
+
+    reg[21] = (source >> 1) & 0xFF;
+    reg[22] = (source >> 9) & 0xFF;
+    reg[23] = (reg[23] & 0x80) | ((source >> 17) & 0x7F);
+}
+
+
+void vdp_test_w(uint16 value)
+{
+}
+
+
diff --git a/MCUME_pico2/picogenold/vdp.h b/MCUME_pico2/picogenold/vdp.h
new file mode 100644
index 0000000..042ab60
--- /dev/null
+++ b/MCUME_pico2/picogenold/vdp.h
@@ -0,0 +1,53 @@
+
+#ifndef _VDP_H_
+#define _VDP_H_
+
+/* Global variables */
+extern uint8 sat[0x400];
+//extern uint8 vram[0x10000];
+extern uint8 cram[0x80];               
+extern uint8 vsram[0x80];              
+extern uint8 reg[0x20];
+extern uint16 status;
+extern uint16 ntab;                    
+extern uint16 ntbb;                    
+extern uint16 ntwb;                    
+extern uint16 satb;                    
+extern uint16 hscb;                    
+extern uint8 is_color_dirty;           
+extern uint8 color_dirty[0x40];        
+extern uint8 border;                   
+extern uint8 is_border_dirty;          
+//extern uint8 bg_name_dirty[0x800];     
+//extern uint16 bg_name_list[0x800];     
+extern uint16 bg_list_index;           
+//extern uint8 bg_pattern_cache[0x80000];
+extern uint8 playfield_shift;          
+extern uint8 playfield_col_mask;       
+extern uint16 playfield_row_mask;      
+extern uint32 y_mask;                  
+extern int vint_pending;
+extern int hint_pending;
+extern int scanline;
+extern int counter;
+extern int im2_flag;
+extern int frame_end;
+extern int v_counter, v_update;
+
+extern void (*color_update)(int index, uint16 data);
+
+/* Function prototypes */
+void vdp_init(void);
+void vdp_reset(void);
+void vdp_shutdown(void);
+void vdp_ctrl_w(uint16 data);
+uint16 vdp_ctrl_r(void);
+void vdp_data_w(uint16 data);
+uint16 vdp_data_r(void);
+void vdp_reg_w(uint8 r, uint8 d);
+uint16 vdp_hvc_r(void);
+void dma_copy(void);
+void dma_vbus(void);
+void vdp_test_w(uint16 value);
+
+#endif /* _VDP_H_ */
diff --git a/MCUME_pico2/picogenold/z80.c b/MCUME_pico2/picogenold/z80.c
new file mode 100644
index 0000000..96b2bbb
--- /dev/null
+++ b/MCUME_pico2/picogenold/z80.c
@@ -0,0 +1,4512 @@
+/*****************************************************************************
+ *
+ *	 z80.c
+ *	 Portable Z80 emulator V2.8
+ *
+ *	 Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved.
+ *
+ *	 - This source code is released as freeware for non-commercial purposes.
+ *	 - You are free to use and redistribute this code in modified or
+ *	   unmodified form, provided you list me in the credits.
+ *	 - If you modify this source code, you must add a notice to each modified
+ *	   source file that it has been changed.  If you're a nice person, you
+ *	   will clearly mark each change too.  :)
+ *	 - If you wish to use this for commercial purposes, please contact me at
+ *	   pullmoll@t-online.de
+ *	 - The author of this copywritten work reserves the right to change the
+ *	   terms of its usage and license at any time, including retroactively
+ *	 - This entire notice must remain in the source code.
+ *
+ *	 Changes in 3.2
+ *	 - Fixed undocumented flags XF & YF of RRCA, and CF and HF of
+ *	   INI/IND/OUTI/OUTD/INIR/INDR/OTIR/OTDR [Sean Young]
+ *	 Changes in 3.1
+ *	 - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes
+ *	   for readabilities sake and because the implementation was buggy
+ *	   (and I was not able to find the difference)
+ *	 Changes in 3.0
+ *	 - 'finished' switch to dynamically overrideable cycle count tables
+ *	 Changes in 2.9:
+ *	 - added methods to access and override the cycle count tables
+ *	 - fixed handling and timing of multiple DD/FD prefixed opcodes
+ *	 Changes in 2.8:
+ *	 - OUTI/OUTD/OTIR/OTDR also pre-decrement the B register now.
+ *	   This was wrong because of a bug fix on the wrong side
+ *	   (astrocade sound driver).
+ *	 Changes in 2.7:
+ *	  - removed z80_vm specific code, it's not needed (and never was).
+ *	 Changes in 2.6:
+ *	  - BUSY_LOOP_HACKS needed to call change_pc16() earlier, before
+ *		checking the opcodes at the new address, because otherwise they
+ *		might access the old (wrong or even NULL) banked memory region.
+ *		Thanks to Sean Young for finding this nasty bug.
+ *	 Changes in 2.5:
+ *	  - Burning cycles always adjusts the ICount by a multiple of 4.
+ *	  - In REPEAT_AT_ONCE cases the R register wasn't incremented twice
+ *		per repetition as it should have been. Those repeated opcodes
+ *		could also underflow the ICount.
+ *	  - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL
+ *		timing loops. I think those hacks weren't endian safe before too.
+ *	 Changes in 2.4:
+ *	  - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and
+ *		sets the Z flag. With these changes the Tehkan World Cup driver
+ *		_seems_ to work again.
+ *	 Changes in 2.3:
+ *	  - External termination of the execution loop calls z80_burn() and
+ *		z80_vm_burn() to burn an amount of cycles (R adjustment)
+ *	  - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS)
+ *		now also adjust the R register depending on the skipped opcodes.
+ *	 Changes in 2.2:
+ *	  - Fixed bugs in CPL, SCF and CCF instructions flag handling.
+ *	  - Changed variable EA and ARG16() function to UINT32; this
+ *		produces slightly more efficient code.
+ *	  - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E
+ *		are changed to calls to the X6/XE opcodes to reduce object size.
+ *		They're hardly ever used so this should not yield a speed penalty.
+ *	 New in 2.0:
+ *	  - Optional more exact Z80 emulation (#define Z80_EXACT 1) according
+ *		to a detailed description by Sean Young which can be found at:
+ *		http://www.msxnet.org/tech/Z80/z80undoc.txt
+ *****************************************************************************/
+
+
+#include "shared.h"
+#include "cpuintrf.h"
+#include "z80.h"
+
+#define cpu_readop      cpu_readmem16
+#define cpu_readop_arg  cpu_readmem16
+
+#define VERBOSE 0
+
+#if VERBOSE
+#define LOG(x)	logerror x
+#else
+#define LOG(x)
+#endif
+
+/* execute main opcodes inside a big switch statement */
+#ifndef BIG_SWITCH
+#define BIG_SWITCH			1
+#endif
+
+/* big flags array for ADD/ADC/SUB/SBC/CP results */
+//#define BIG_FLAGS_ARRAY 	1
+
+/* Set to 1 for a more exact (but somewhat slower) Z80 emulation */
+//#define Z80_EXACT			1
+
+/* on JP and JR opcodes check for tight loops */
+#define BUSY_LOOP_HACKS 	1
+
+/* check for delay loops counting down BC */
+#define TIME_LOOP_HACKS 	1
+
+#ifdef X86_ASM
+#undef	BIG_FLAGS_ARRAY
+#define BIG_FLAGS_ARRAY 	0
+#endif
+
+#if 0
+static UINT8 z80_reg_layout[] = {
+	Z80_PC, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, -1,
+	Z80_IX, Z80_IY, Z80_AF2,Z80_BC2,Z80_DE2,Z80_HL2,-1,
+	Z80_R,	Z80_I,	Z80_IM, Z80_IFF1,Z80_IFF2, -1,
+	Z80_NMI_STATE,Z80_IRQ_STATE,Z80_DC0,Z80_DC1,Z80_DC2,Z80_DC3, 0
+};
+
+static UINT8 z80_win_layout[] = {
+	27, 0,53, 4,	/* register window (top rows) */
+	 0, 0,26,22,	/* disassembler window (left colums) */
+	27, 5,53, 8,	/* memory #1 window (right, upper middle) */
+	27,14,53, 8,	/* memory #2 window (right, lower middle) */
+	 0,23,80, 1,	/* command line window (bottom rows) */
+};
+#endif
+
+/****************************************************************************/
+/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh	*/
+/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128)	*/
+/****************************************************************************/
+typedef struct {
+/* 00 */	PAIR	PREPC,PC,SP,AF,BC,DE,HL,IX,IY;
+/* 24 */	PAIR	AF2,BC2,DE2,HL2;
+/* 34 */	UINT8	R,R2,IFF1,IFF2,HALT,IM,I;
+/* 3B */	UINT8	irq_max;			/* number of daisy chain devices		*/
+/* 3C */	INT8	request_irq;		/* daisy chain next request device		*/
+/* 3D */	INT8	service_irq;		/* daisy chain next reti handling device */
+/* 3E */	UINT8	nmi_state;			/* nmi line state */
+/* 3F */	UINT8	irq_state;			/* irq line state */
+/* 40 */	UINT8	int_state[Z80_MAXDAISY];
+/* 44 */	Z80_DaisyChain irq[Z80_MAXDAISY];
+/* 84 */	int 	(*irq_callback)(int irqline);
+/* 88 */	int 	extra_cycles;		/* extra cycles for interrupts */
+}	Z80_Regs;
+
+#define CF	0x01
+#define NF	0x02
+#define PF	0x04
+#define VF	PF
+#define XF	0x08
+#define HF	0x10
+#define YF	0x20
+#define ZF	0x40
+#define SF	0x80
+
+#define INT_IRQ 0x01
+#define NMI_IRQ 0x02
+
+#define _PPC	Z80.PREPC.d 	/* previous program counter */
+
+#define _PCD	Z80.PC.d
+#define _PC 	Z80.PC.w.l
+
+#define _SPD	Z80.SP.d
+#define _SP 	Z80.SP.w.l
+
+#define _AFD	Z80.AF.d
+#define _AF 	Z80.AF.w.l
+#define _A		Z80.AF.b.h
+#define _F		Z80.AF.b.l
+
+#define _BCD	Z80.BC.d
+#define _BC 	Z80.BC.w.l
+#define _B		Z80.BC.b.h
+#define _C		Z80.BC.b.l
+
+#define _DED	Z80.DE.d
+#define _DE 	Z80.DE.w.l
+#define _D		Z80.DE.b.h
+#define _E		Z80.DE.b.l
+
+#define _HLD	Z80.HL.d
+#define _HL 	Z80.HL.w.l
+#define _H		Z80.HL.b.h
+#define _L		Z80.HL.b.l
+
+#define _IXD	Z80.IX.d
+#define _IX 	Z80.IX.w.l
+#define _HX 	Z80.IX.b.h
+#define _LX 	Z80.IX.b.l
+
+#define _IYD	Z80.IY.d
+#define _IY 	Z80.IY.w.l
+#define _HY 	Z80.IY.b.h
+#define _LY 	Z80.IY.b.l
+
+#define _I		Z80.I
+#define _R		Z80.R
+#define _R2 	Z80.R2
+#define _IM 	Z80.IM
+#define _IFF1	Z80.IFF1
+#define _IFF2	Z80.IFF2
+#define _HALT	Z80.HALT
+
+int z80_ICount;
+static Z80_Regs Z80;
+static UINT32 EA;
+static int after_EI = 0;
+
+static UINT8 SZ[256];		/* zero and sign flags */
+static UINT8 SZ_BIT[256];	/* zero, sign and parity/overflow (=zero) flags for BIT opcode */
+static UINT8 SZP[256];		/* zero, sign and parity flags */
+static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
+static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
+
+#include "z80daa.h"
+
+#if BIG_FLAGS_ARRAY
+//#include <signal.h>
+static UINT8 *SZHVC_add = 0;
+static UINT8 *SZHVC_sub = 0;
+#endif
+
+#if Z80_EXACT
+/* tmp1 value for ini/inir/outi/otir for [C.1-0][io.1-0] */
+static UINT8 irep_tmp1[4][4] = {
+	{0,0,1,0},{0,1,0,1},{1,0,1,1},{0,1,1,0}
+};
+
+/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */
+static UINT8 drep_tmp1[4][4] = {
+	{0,1,0,0},{1,0,0,1},{0,0,1,0},{0,1,0,1}
+};
+
+/* tmp2 value for all in/out repeated opcodes for B.7-0 */
+static UINT8 breg_tmp2[256] = {
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1
+};
+#endif
+
+
+static const UINT8 cc_op[0x100] = {
+ 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+ 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+ 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+ 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+ 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+ 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+ 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11};
+
+static const UINT8 cc_cb[0x100] = {
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8};
+
+static const UINT8 cc_ed[0x100] = {
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9,
+12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9,
+12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18,
+12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
+16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8};
+
+static const UINT8 cc_xy[0x100] = {
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4,
+ 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4};
+
+static const UINT8 cc_xycb[0x100] = {
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23};
+
+/* extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 */
+static const UINT8 cc_ex[0x100] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* DJNZ */
+ 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0,	/* JR NZ/JR Z */
+ 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0,	/* JR NC/JR C */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0,	/* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */
+ 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
+ 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
+ 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
+ 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2};
+
+static UINT8 *cc[6] = { cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex };
+#define Z80_TABLE_dd	Z80_TABLE_xy
+#define Z80_TABLE_fd	Z80_TABLE_xy
+
+static void take_interrupt(void);
+
+#define PROTOTYPES(tablename,prefix) \
+    static __inline__ void prefix##_00(void); static __inline__ void prefix##_01(void); static __inline__ void prefix##_02(void); static __inline__ void prefix##_03(void); \
+    static __inline__ void prefix##_04(void); static __inline__ void prefix##_05(void); static __inline__ void prefix##_06(void); static __inline__ void prefix##_07(void); \
+    static __inline__ void prefix##_08(void); static __inline__ void prefix##_09(void); static __inline__ void prefix##_0a(void); static __inline__ void prefix##_0b(void); \
+    static __inline__ void prefix##_0c(void); static __inline__ void prefix##_0d(void); static __inline__ void prefix##_0e(void); static __inline__ void prefix##_0f(void); \
+    static __inline__ void prefix##_10(void); static __inline__ void prefix##_11(void); static __inline__ void prefix##_12(void); static __inline__ void prefix##_13(void); \
+    static __inline__ void prefix##_14(void); static __inline__ void prefix##_15(void); static __inline__ void prefix##_16(void); static __inline__ void prefix##_17(void); \
+    static __inline__ void prefix##_18(void); static __inline__ void prefix##_19(void); static __inline__ void prefix##_1a(void); static __inline__ void prefix##_1b(void); \
+    static __inline__ void prefix##_1c(void); static __inline__ void prefix##_1d(void); static __inline__ void prefix##_1e(void); static __inline__ void prefix##_1f(void); \
+    static __inline__ void prefix##_20(void); static __inline__ void prefix##_21(void); static __inline__ void prefix##_22(void); static __inline__ void prefix##_23(void); \
+    static __inline__ void prefix##_24(void); static __inline__ void prefix##_25(void); static __inline__ void prefix##_26(void); static __inline__ void prefix##_27(void); \
+    static __inline__ void prefix##_28(void); static __inline__ void prefix##_29(void); static __inline__ void prefix##_2a(void); static __inline__ void prefix##_2b(void); \
+    static __inline__ void prefix##_2c(void); static __inline__ void prefix##_2d(void); static __inline__ void prefix##_2e(void); static __inline__ void prefix##_2f(void); \
+    static __inline__ void prefix##_30(void); static __inline__ void prefix##_31(void); static __inline__ void prefix##_32(void); static __inline__ void prefix##_33(void); \
+    static __inline__ void prefix##_34(void); static __inline__ void prefix##_35(void); static __inline__ void prefix##_36(void); static __inline__ void prefix##_37(void); \
+    static __inline__ void prefix##_38(void); static __inline__ void prefix##_39(void); static __inline__ void prefix##_3a(void); static __inline__ void prefix##_3b(void); \
+    static __inline__ void prefix##_3c(void); static __inline__ void prefix##_3d(void); static __inline__ void prefix##_3e(void); static __inline__ void prefix##_3f(void); \
+    static __inline__ void prefix##_40(void); static __inline__ void prefix##_41(void); static __inline__ void prefix##_42(void); static __inline__ void prefix##_43(void); \
+    static __inline__ void prefix##_44(void); static __inline__ void prefix##_45(void); static __inline__ void prefix##_46(void); static __inline__ void prefix##_47(void); \
+    static __inline__ void prefix##_48(void); static __inline__ void prefix##_49(void); static __inline__ void prefix##_4a(void); static __inline__ void prefix##_4b(void); \
+    static __inline__ void prefix##_4c(void); static __inline__ void prefix##_4d(void); static __inline__ void prefix##_4e(void); static __inline__ void prefix##_4f(void); \
+    static __inline__ void prefix##_50(void); static __inline__ void prefix##_51(void); static __inline__ void prefix##_52(void); static __inline__ void prefix##_53(void); \
+    static __inline__ void prefix##_54(void); static __inline__ void prefix##_55(void); static __inline__ void prefix##_56(void); static __inline__ void prefix##_57(void); \
+    static __inline__ void prefix##_58(void); static __inline__ void prefix##_59(void); static __inline__ void prefix##_5a(void); static __inline__ void prefix##_5b(void); \
+    static __inline__ void prefix##_5c(void); static __inline__ void prefix##_5d(void); static __inline__ void prefix##_5e(void); static __inline__ void prefix##_5f(void); \
+    static __inline__ void prefix##_60(void); static __inline__ void prefix##_61(void); static __inline__ void prefix##_62(void); static __inline__ void prefix##_63(void); \
+    static __inline__ void prefix##_64(void); static __inline__ void prefix##_65(void); static __inline__ void prefix##_66(void); static __inline__ void prefix##_67(void); \
+    static __inline__ void prefix##_68(void); static __inline__ void prefix##_69(void); static __inline__ void prefix##_6a(void); static __inline__ void prefix##_6b(void); \
+    static __inline__ void prefix##_6c(void); static __inline__ void prefix##_6d(void); static __inline__ void prefix##_6e(void); static __inline__ void prefix##_6f(void); \
+    static __inline__ void prefix##_70(void); static __inline__ void prefix##_71(void); static __inline__ void prefix##_72(void); static __inline__ void prefix##_73(void); \
+    static __inline__ void prefix##_74(void); static __inline__ void prefix##_75(void); static __inline__ void prefix##_76(void); static __inline__ void prefix##_77(void); \
+    static __inline__ void prefix##_78(void); static __inline__ void prefix##_79(void); static __inline__ void prefix##_7a(void); static __inline__ void prefix##_7b(void); \
+    static __inline__ void prefix##_7c(void); static __inline__ void prefix##_7d(void); static __inline__ void prefix##_7e(void); static __inline__ void prefix##_7f(void); \
+    static __inline__ void prefix##_80(void); static __inline__ void prefix##_81(void); static __inline__ void prefix##_82(void); static __inline__ void prefix##_83(void); \
+    static __inline__ void prefix##_84(void); static __inline__ void prefix##_85(void); static __inline__ void prefix##_86(void); static __inline__ void prefix##_87(void); \
+    static __inline__ void prefix##_88(void); static __inline__ void prefix##_89(void); static __inline__ void prefix##_8a(void); static __inline__ void prefix##_8b(void); \
+    static __inline__ void prefix##_8c(void); static __inline__ void prefix##_8d(void); static __inline__ void prefix##_8e(void); static __inline__ void prefix##_8f(void); \
+    static __inline__ void prefix##_90(void); static __inline__ void prefix##_91(void); static __inline__ void prefix##_92(void); static __inline__ void prefix##_93(void); \
+    static __inline__ void prefix##_94(void); static __inline__ void prefix##_95(void); static __inline__ void prefix##_96(void); static __inline__ void prefix##_97(void); \
+    static __inline__ void prefix##_98(void); static __inline__ void prefix##_99(void); static __inline__ void prefix##_9a(void); static __inline__ void prefix##_9b(void); \
+    static __inline__ void prefix##_9c(void); static __inline__ void prefix##_9d(void); static __inline__ void prefix##_9e(void); static __inline__ void prefix##_9f(void); \
+    static __inline__ void prefix##_a0(void); static __inline__ void prefix##_a1(void); static __inline__ void prefix##_a2(void); static __inline__ void prefix##_a3(void); \
+    static __inline__ void prefix##_a4(void); static __inline__ void prefix##_a5(void); static __inline__ void prefix##_a6(void); static __inline__ void prefix##_a7(void); \
+    static __inline__ void prefix##_a8(void); static __inline__ void prefix##_a9(void); static __inline__ void prefix##_aa(void); static __inline__ void prefix##_ab(void); \
+    static __inline__ void prefix##_ac(void); static __inline__ void prefix##_ad(void); static __inline__ void prefix##_ae(void); static __inline__ void prefix##_af(void); \
+    static __inline__ void prefix##_b0(void); static __inline__ void prefix##_b1(void); static __inline__ void prefix##_b2(void); static __inline__ void prefix##_b3(void); \
+    static __inline__ void prefix##_b4(void); static __inline__ void prefix##_b5(void); static __inline__ void prefix##_b6(void); static __inline__ void prefix##_b7(void); \
+    static __inline__ void prefix##_b8(void); static __inline__ void prefix##_b9(void); static __inline__ void prefix##_ba(void); static __inline__ void prefix##_bb(void); \
+    static __inline__ void prefix##_bc(void); static __inline__ void prefix##_bd(void); static __inline__ void prefix##_be(void); static __inline__ void prefix##_bf(void); \
+    static __inline__ void prefix##_c0(void); static __inline__ void prefix##_c1(void); static __inline__ void prefix##_c2(void); static __inline__ void prefix##_c3(void); \
+    static __inline__ void prefix##_c4(void); static __inline__ void prefix##_c5(void); static __inline__ void prefix##_c6(void); static __inline__ void prefix##_c7(void); \
+    static __inline__ void prefix##_c8(void); static __inline__ void prefix##_c9(void); static __inline__ void prefix##_ca(void); static __inline__ void prefix##_cb(void); \
+    static __inline__ void prefix##_cc(void); static __inline__ void prefix##_cd(void); static __inline__ void prefix##_ce(void); static __inline__ void prefix##_cf(void); \
+    static __inline__ void prefix##_d0(void); static __inline__ void prefix##_d1(void); static __inline__ void prefix##_d2(void); static __inline__ void prefix##_d3(void); \
+    static __inline__ void prefix##_d4(void); static __inline__ void prefix##_d5(void); static __inline__ void prefix##_d6(void); static __inline__ void prefix##_d7(void); \
+    static __inline__ void prefix##_d8(void); static __inline__ void prefix##_d9(void); static __inline__ void prefix##_da(void); static __inline__ void prefix##_db(void); \
+    static __inline__ void prefix##_dc(void); static __inline__ void prefix##_dd(void); static __inline__ void prefix##_de(void); static __inline__ void prefix##_df(void); \
+    static __inline__ void prefix##_e0(void); static __inline__ void prefix##_e1(void); static __inline__ void prefix##_e2(void); static __inline__ void prefix##_e3(void); \
+    static __inline__ void prefix##_e4(void); static __inline__ void prefix##_e5(void); static __inline__ void prefix##_e6(void); static __inline__ void prefix##_e7(void); \
+    static __inline__ void prefix##_e8(void); static __inline__ void prefix##_e9(void); static __inline__ void prefix##_ea(void); static __inline__ void prefix##_eb(void); \
+    static __inline__ void prefix##_ec(void); static __inline__ void prefix##_ed(void); static __inline__ void prefix##_ee(void); static __inline__ void prefix##_ef(void); \
+    static __inline__ void prefix##_f0(void); static __inline__ void prefix##_f1(void); static __inline__ void prefix##_f2(void); static __inline__ void prefix##_f3(void); \
+    static __inline__ void prefix##_f4(void); static __inline__ void prefix##_f5(void); static __inline__ void prefix##_f6(void); static __inline__ void prefix##_f7(void); \
+    static __inline__ void prefix##_f8(void); static __inline__ void prefix##_f9(void); static __inline__ void prefix##_fa(void); static __inline__ void prefix##_fb(void); \
+    static __inline__ void prefix##_fc(void); static __inline__ void prefix##_fd(void); static __inline__ void prefix##_fe(void); static __inline__ void prefix##_ff(void); \
+static const void (*tablename[0x100])(void) = {	\
+	prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \
+	prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \
+	prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \
+	prefix##_18,prefix##_19,prefix##_1a,prefix##_1b,prefix##_1c,prefix##_1d,prefix##_1e,prefix##_1f, \
+	prefix##_20,prefix##_21,prefix##_22,prefix##_23,prefix##_24,prefix##_25,prefix##_26,prefix##_27, \
+	prefix##_28,prefix##_29,prefix##_2a,prefix##_2b,prefix##_2c,prefix##_2d,prefix##_2e,prefix##_2f, \
+	prefix##_30,prefix##_31,prefix##_32,prefix##_33,prefix##_34,prefix##_35,prefix##_36,prefix##_37, \
+	prefix##_38,prefix##_39,prefix##_3a,prefix##_3b,prefix##_3c,prefix##_3d,prefix##_3e,prefix##_3f, \
+	prefix##_40,prefix##_41,prefix##_42,prefix##_43,prefix##_44,prefix##_45,prefix##_46,prefix##_47, \
+	prefix##_48,prefix##_49,prefix##_4a,prefix##_4b,prefix##_4c,prefix##_4d,prefix##_4e,prefix##_4f, \
+	prefix##_50,prefix##_51,prefix##_52,prefix##_53,prefix##_54,prefix##_55,prefix##_56,prefix##_57, \
+	prefix##_58,prefix##_59,prefix##_5a,prefix##_5b,prefix##_5c,prefix##_5d,prefix##_5e,prefix##_5f, \
+	prefix##_60,prefix##_61,prefix##_62,prefix##_63,prefix##_64,prefix##_65,prefix##_66,prefix##_67, \
+	prefix##_68,prefix##_69,prefix##_6a,prefix##_6b,prefix##_6c,prefix##_6d,prefix##_6e,prefix##_6f, \
+	prefix##_70,prefix##_71,prefix##_72,prefix##_73,prefix##_74,prefix##_75,prefix##_76,prefix##_77, \
+	prefix##_78,prefix##_79,prefix##_7a,prefix##_7b,prefix##_7c,prefix##_7d,prefix##_7e,prefix##_7f, \
+	prefix##_80,prefix##_81,prefix##_82,prefix##_83,prefix##_84,prefix##_85,prefix##_86,prefix##_87, \
+	prefix##_88,prefix##_89,prefix##_8a,prefix##_8b,prefix##_8c,prefix##_8d,prefix##_8e,prefix##_8f, \
+	prefix##_90,prefix##_91,prefix##_92,prefix##_93,prefix##_94,prefix##_95,prefix##_96,prefix##_97, \
+	prefix##_98,prefix##_99,prefix##_9a,prefix##_9b,prefix##_9c,prefix##_9d,prefix##_9e,prefix##_9f, \
+	prefix##_a0,prefix##_a1,prefix##_a2,prefix##_a3,prefix##_a4,prefix##_a5,prefix##_a6,prefix##_a7, \
+	prefix##_a8,prefix##_a9,prefix##_aa,prefix##_ab,prefix##_ac,prefix##_ad,prefix##_ae,prefix##_af, \
+	prefix##_b0,prefix##_b1,prefix##_b2,prefix##_b3,prefix##_b4,prefix##_b5,prefix##_b6,prefix##_b7, \
+	prefix##_b8,prefix##_b9,prefix##_ba,prefix##_bb,prefix##_bc,prefix##_bd,prefix##_be,prefix##_bf, \
+	prefix##_c0,prefix##_c1,prefix##_c2,prefix##_c3,prefix##_c4,prefix##_c5,prefix##_c6,prefix##_c7, \
+	prefix##_c8,prefix##_c9,prefix##_ca,prefix##_cb,prefix##_cc,prefix##_cd,prefix##_ce,prefix##_cf, \
+	prefix##_d0,prefix##_d1,prefix##_d2,prefix##_d3,prefix##_d4,prefix##_d5,prefix##_d6,prefix##_d7, \
+	prefix##_d8,prefix##_d9,prefix##_da,prefix##_db,prefix##_dc,prefix##_dd,prefix##_de,prefix##_df, \
+	prefix##_e0,prefix##_e1,prefix##_e2,prefix##_e3,prefix##_e4,prefix##_e5,prefix##_e6,prefix##_e7, \
+	prefix##_e8,prefix##_e9,prefix##_ea,prefix##_eb,prefix##_ec,prefix##_ed,prefix##_ee,prefix##_ef, \
+	prefix##_f0,prefix##_f1,prefix##_f2,prefix##_f3,prefix##_f4,prefix##_f5,prefix##_f6,prefix##_f7, \
+	prefix##_f8,prefix##_f9,prefix##_fa,prefix##_fb,prefix##_fc,prefix##_fd,prefix##_fe,prefix##_ff  \
+}
+
+PROTOTYPES(Z80op,op);
+PROTOTYPES(Z80cb,cb);
+PROTOTYPES(Z80dd,dd);
+PROTOTYPES(Z80ed,ed);
+PROTOTYPES(Z80fd,fd);
+PROTOTYPES(Z80xycb,xycb);
+
+/****************************************************************************/
+/* Burn an odd amount of cycles, that is instructions taking something		*/
+/* different from 4 T-states per opcode (and R increment)					*/
+/****************************************************************************/
+static __inline__ void BURNODD(int cycles, int opcodes, int cyclesum)
+{
+	if( cycles > 0 )
+	{
+		_R += (cycles / cyclesum) * opcodes;
+		z80_ICount -= (cycles / cyclesum) * cyclesum;
+	}
+}
+
+/***************************************************************
+ * define an opcode function
+ ***************************************************************/
+#define OP(prefix,opcode)  static __inline__ void prefix##_##opcode(void)
+
+/***************************************************************
+ * adjust cycle count by n T-states
+ ***************************************************************/
+#define CC(prefix,opcode) z80_ICount -= cc[Z80_TABLE_##prefix][opcode]
+
+/***************************************************************
+ * execute an opcode
+ ***************************************************************/
+#define EXEC(prefix,opcode) 									\
+{																\
+	unsigned op = opcode;										\
+	CC(prefix,op);												\
+	(*Z80##prefix[op])();										\
+}
+
+#if BIG_SWITCH
+#define EXEC_INLINE(prefix,opcode)                              \
+{																\
+	unsigned op = opcode;										\
+	CC(prefix,op);												\
+	switch(op)													\
+	{															\
+	case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \
+	case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \
+	case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \
+	case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \
+	case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \
+	case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \
+	case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \
+	case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \
+	case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \
+	case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \
+	case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \
+	case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \
+	case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \
+	case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \
+	case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \
+	case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \
+	case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \
+	case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \
+	case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \
+	case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \
+	case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \
+	case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \
+	case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \
+	case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \
+	case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \
+	case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \
+	case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \
+	case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \
+	case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \
+	case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \
+	case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \
+	case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \
+	case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \
+	case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \
+	case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \
+	case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \
+	case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \
+	case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \
+	case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \
+	case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \
+	case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \
+	case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \
+	case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \
+	case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \
+	case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \
+	case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \
+	case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \
+	case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \
+	case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \
+	case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \
+	case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \
+	case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \
+	case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \
+	case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \
+	case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \
+	case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \
+	case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \
+	case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \
+	case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \
+	case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \
+	case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \
+	case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \
+	case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \
+	case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \
+	}																																	\
+}
+#else
+#define EXEC_INLINE EXEC
+#endif
+
+
+/***************************************************************
+ * Enter HALT state; write 1 to fake port on first execution
+ ***************************************************************/
+#define ENTER_HALT {											\
+	_PC--;														\
+	_HALT = 1;													\
+	if( !after_EI ) 											\
+		z80_burn( z80_ICount ); 								\
+}
+
+/***************************************************************
+ * Leave HALT state; write 0 to fake port
+ ***************************************************************/
+#define LEAVE_HALT {											\
+	if( _HALT ) 												\
+	{															\
+		_HALT = 0;												\
+		_PC++;													\
+	}															\
+}
+
+/***************************************************************
+ * Input a byte from given I/O port
+ ***************************************************************/
+#define IN(port)   ((UINT8)cpu_readport16(port))
+
+/***************************************************************
+ * Output a byte to given I/O port
+ ***************************************************************/
+#define OUT(port,value) cpu_writeport16(port,value)
+
+/***************************************************************
+ * Read a byte from given memory location
+ ***************************************************************/
+#define RM(addr) (UINT8)cpu_readmem16(addr)
+
+/***************************************************************
+ * Read a word from given memory location
+ ***************************************************************/
+static __inline__ void RM16( UINT32 addr, PAIR *r )
+{
+	r->b.l = RM(addr);
+	r->b.h = RM((addr+1)&0xffff);
+}
+
+/***************************************************************
+ * Write a byte to given memory location
+ ***************************************************************/
+#define WM(addr,value) cpu_writemem16(addr,value)
+
+/***************************************************************
+ * Write a word to given memory location
+ ***************************************************************/
+static __inline__ void WM16( UINT32 addr, PAIR *r )
+{
+	WM(addr,r->b.l);
+	WM((addr+1)&0xffff,r->b.h);
+}
+
+/***************************************************************
+ * ROP() is identical to RM() except it is used for
+ * reading opcodes. In case of system with memory mapped I/O,
+ * this function can be used to greatly speed up emulation
+ ***************************************************************/
+static __inline__ UINT8 ROP(void)
+{
+	unsigned pc = _PCD;
+	_PC++;
+	return cpu_readop(pc);
+}
+
+/****************************************************************
+ * ARG() is identical to ROP() except it is used
+ * for reading opcode arguments. This difference can be used to
+ * support systems that use different encoding mechanisms for
+ * opcodes and opcode arguments
+ ***************************************************************/
+static __inline__ UINT8 ARG(void)
+{
+	unsigned pc = _PCD;
+	_PC++;
+	return cpu_readop_arg(pc);
+}
+
+static __inline__ UINT32 ARG16(void)
+{
+	unsigned pc = _PCD;
+	_PC += 2;
+	return cpu_readop_arg(pc) | (cpu_readop_arg((pc+1)&0xffff) << 8);
+}
+
+/***************************************************************
+ * Calculate the effective address EA of an opcode using
+ * IX+offset resp. IY+offset addressing.
+ ***************************************************************/
+#define EAX EA = (UINT32)(UINT16)(_IX+(INT8)ARG())
+#define EAY EA = (UINT32)(UINT16)(_IY+(INT8)ARG())
+
+/***************************************************************
+ * POP
+ ***************************************************************/
+#define POP(DR) { RM16( _SPD, &Z80.DR ); _SP += 2; }
+
+/***************************************************************
+ * PUSH
+ ***************************************************************/
+#define PUSH(SR) { _SP -= 2; WM16( _SPD, &Z80.SR ); }
+
+/***************************************************************
+ * JP
+ ***************************************************************/
+#if BUSY_LOOP_HACKS
+#define JP {													\
+	unsigned oldpc = _PCD-1;									\
+	_PCD = ARG16(); 											\
+	/* speed up busy loop */									\
+	if( _PCD == oldpc ) 										\
+	{															\
+		if( !after_EI ) 										\
+			BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0xc3] );	\
+	}															\
+	else														\
+	{															\
+		UINT8 op = cpu_readop(_PCD);							\
+		if( _PCD == oldpc-1 )									\
+		{														\
+			/* NOP - JP $-1 or EI - JP $-1 */					\
+			if ( op == 0x00 || op == 0xfb ) 					\
+			{													\
+				if( !after_EI ) 								\
+					BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00], \
+						2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0xc3]); \
+			}													\
+		}														\
+		else													\
+		/* LD SP,#xxxx - JP $-3 (Galaga) */ 					\
+		if( _PCD == oldpc-3 && op == 0x31 ) 					\
+		{														\
+			if( !after_EI ) 									\
+				BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31], 	\
+					2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0xc3]); \
+		}														\
+	}															\
+}
+#else
+#define JP {													\
+	_PCD = ARG16(); 											\
+}
+#endif
+
+/***************************************************************
+ * JP_COND
+ ***************************************************************/
+
+#define JP_COND(cond)											\
+	if( cond )													\
+	{															\
+		_PCD = ARG16(); 										\
+	}															\
+	else														\
+	{															\
+		_PC += 2;												\
+	}
+
+/***************************************************************
+ * JR
+ ***************************************************************/
+#define JR()													\
+{																\
+	unsigned oldpc = _PCD-1;									\
+	INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ 	\
+	_PC += arg; 			/* so don't do _PC += ARG() */      \
+	/* speed up busy loop */									\
+	if( _PCD == oldpc ) 										\
+	{															\
+		if( !after_EI ) 										\
+			BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0x18] );	\
+	}															\
+	else														\
+	{															\
+		UINT8 op = cpu_readop(_PCD);							\
+		if( _PCD == oldpc-1 )									\
+		{														\
+			/* NOP - JR $-1 or EI - JR $-1 */					\
+			if ( op == 0x00 || op == 0xfb ) 					\
+			{													\
+				if( !after_EI ) 								\
+				   BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00],	\
+					   2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0x18]); \
+			}													\
+		}														\
+		else													\
+		/* LD SP,#xxxx - JR $-3 */								\
+		if( _PCD == oldpc-3 && op == 0x31 ) 					\
+		{														\
+			if( !after_EI ) 									\
+			   BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31],		\
+				   2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0x18]); \
+		}														\
+	}															\
+}
+
+/***************************************************************
+ * JR_COND
+ ***************************************************************/
+#define JR_COND(cond,opcode)									\
+	if( cond )													\
+	{															\
+		INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \
+		_PC += arg; 			/* so don't do _PC += ARG() */  \
+		CC(ex,opcode);											\
+	}															\
+	else _PC++; 												\
+
+/***************************************************************
+ * CALL
+ ***************************************************************/
+#define CALL()													\
+	EA = ARG16();												\
+	PUSH( PC ); 												\
+    _PCD = EA;                                                  
+
+/***************************************************************
+ * CALL_COND
+ ***************************************************************/
+#define CALL_COND(cond,opcode)									\
+	if( cond )													\
+	{															\
+		EA = ARG16();											\
+		PUSH( PC ); 											\
+		_PCD = EA;												\
+		CC(ex,opcode);											\
+	}															\
+	else														\
+	{															\
+		_PC+=2; 												\
+	}
+
+/***************************************************************
+ * RET_COND
+ ***************************************************************/
+#define RET_COND(cond,opcode)									\
+	if( cond )													\
+	{															\
+		POP(PC);												\
+		CC(ex,opcode);											\
+	}
+
+/***************************************************************
+ * RETN
+ ***************************************************************/
+#define RETN	{												\
+	POP(PC);													\
+	if( _IFF1 == 0 && _IFF2 == 1 )								\
+	{															\
+		_IFF1 = 1;												\
+		if( Z80.irq_state != CLEAR_LINE ||						\
+			Z80.request_irq >= 0 )								\
+		{														\
+			take_interrupt();									\
+		}														\
+	}															\
+	else _IFF1 = _IFF2; 										\
+}
+
+/***************************************************************
+ * RETI
+ ***************************************************************/
+#define RETI	{												\
+	int device = Z80.service_irq;								\
+	POP(PC);													\
+/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */	\
+/*	_IFF1 = _IFF2;	*/											\
+	if( device >= 0 )											\
+	{															\
+		Z80.irq[device].interrupt_reti(Z80.irq[device].irq_param); \
+	}															\
+}
+
+/***************************************************************
+ * LD	R,A
+ ***************************************************************/
+#define LD_R_A {												\
+	_R = _A;													\
+	_R2 = _A & 0x80;				/* keep bit 7 of R */		\
+}
+
+/***************************************************************
+ * LD	A,R
+ ***************************************************************/
+#define LD_A_R {												\
+	_A = (_R & 0x7f) | _R2; 									\
+	_F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 );					\
+}
+
+/***************************************************************
+ * LD	I,A
+ ***************************************************************/
+#define LD_I_A {												\
+	_I = _A;													\
+}
+
+/***************************************************************
+ * LD	A,I
+ ***************************************************************/
+#define LD_A_I {												\
+	_A = _I;													\
+	_F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 );					\
+}
+
+/***************************************************************
+ * RST
+ ***************************************************************/
+#define RST(addr)												\
+	PUSH( PC ); 												\
+    _PCD = addr;                                                
+
+/***************************************************************
+ * INC	r8
+ ***************************************************************/
+static __inline__ UINT8 INC(UINT8 value)
+{
+	UINT8 res = value + 1;
+	_F = (_F & CF) | SZHV_inc[res];
+	return (UINT8)res;
+}
+
+/***************************************************************
+ * DEC	r8
+ ***************************************************************/
+static __inline__ UINT8 DEC(UINT8 value)
+{
+	UINT8 res = value - 1;
+	_F = (_F & CF) | SZHV_dec[res];
+	return res;
+}
+
+/***************************************************************
+ * RLCA
+ ***************************************************************/
+#if Z80_EXACT
+#define RLCA													\
+	_A = (_A << 1) | (_A >> 7); 								\
+	_F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF))
+#else
+#define RLCA													\
+	_A = (_A << 1) | (_A >> 7); 								\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF)
+#endif
+
+/***************************************************************
+ * RRCA
+ ***************************************************************/
+#if Z80_EXACT
+#define RRCA													\
+	_F = (_F & (SF | ZF | PF)) | (_A & CF); 					\
+	_A = (_A >> 1) | (_A << 7); 								\
+	_F |= (_A & (YF | XF) )
+#else
+#define RRCA													\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF);			\
+	_A = (_A >> 1) | (_A << 7)
+#endif
+
+/***************************************************************
+ * RLA
+ ***************************************************************/
+#if Z80_EXACT
+#define RLA {													\
+	UINT8 res = (_A << 1) | (_F & CF);							\
+	UINT8 c = (_A & 0x80) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); 		\
+	_A = res;													\
+}
+#else
+#define RLA {													\
+	UINT8 res = (_A << 1) | (_F & CF);							\
+	UINT8 c = (_A & 0x80) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | c;					\
+	_A = res;													\
+}
+#endif
+
+/***************************************************************
+ * RRA
+ ***************************************************************/
+#if Z80_EXACT
+#define RRA {													\
+	UINT8 res = (_A >> 1) | (_F << 7);							\
+	UINT8 c = (_A & 0x01) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); 		\
+	_A = res;													\
+}
+#else
+#define RRA {													\
+	UINT8 res = (_A >> 1) | (_F << 7);							\
+	UINT8 c = (_A & 0x01) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | c;					\
+	_A = res;													\
+}
+#endif
+
+/***************************************************************
+ * RRD
+ ***************************************************************/
+#define RRD {													\
+	UINT8 n = RM(_HL);											\
+	WM( _HL, (n >> 4) | (_A << 4) );							\
+	_A = (_A & 0xf0) | (n & 0x0f);								\
+	_F = (_F & CF) | SZP[_A];									\
+}
+
+/***************************************************************
+ * RLD
+ ***************************************************************/
+#define RLD {													\
+	UINT8 n = RM(_HL);											\
+	WM( _HL, (n << 4) | (_A & 0x0f) );							\
+	_A = (_A & 0xf0) | (n >> 4);								\
+	_F = (_F & CF) | SZP[_A];									\
+}
+
+/***************************************************************
+ * ADD	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define ADD(value)												\
+ asm (															\
+ " addb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n"                                     \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n"                                     \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define ADD(value)												\
+ asm (															\
+ " addb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n"                                     \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n"                                     \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define ADD(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) + value);					\
+	_F = SZHVC_add[ah | res];									\
+	_A = res;													\
+}
+#else
+#define ADD(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A + val;									\
+	_F = SZ[(UINT8)res] | ((res >> 8) & CF) |					\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5);		\
+	_A = (UINT8)res;											\
+}
+#endif
+#endif
+
+/***************************************************************
+ * ADC	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define ADC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define ADC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define ADC(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00, c = _AFD & 1;					\
+	UINT32 res = (UINT8)((ah >> 8) + value + c);				\
+	_F = SZHVC_add[(c << 16) | ah | res];						\
+	_A = res;													\
+}
+#else
+#define ADC(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A + val + (_F & CF);						\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) |					\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5);		\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * SUB	n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define SUB(value)												\
+ asm (															\
+ " subb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define SUB(value)												\
+ asm (															\
+ " subb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define SUB(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) - value);					\
+	_F = SZHVC_sub[ah | res];									\
+	_A = res;													\
+}
+#else
+#define SUB(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val;									\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A) & (_A ^ res) & 0x80) >> 5);				\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * SBC	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define SBC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define SBC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define SBC(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00, c = _AFD & 1;					\
+	UINT32 res = (UINT8)((ah >> 8) - value - c);				\
+	_F = SZHVC_sub[(c<<16) | ah | res]; 						\
+	_A = res;													\
+}
+#else
+#define SBC(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val - (_F & CF);						\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A) & (_A ^ res) & 0x80) >> 5);				\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * NEG
+ ***************************************************************/
+#define NEG {													\
+	UINT8 value = _A;											\
+	_A = 0; 													\
+	SUB(value); 												\
+}
+
+/***************************************************************
+ * DAA
+ ***************************************************************/
+#define DAA {													\
+	int idx = _A;												\
+	if( _F & CF ) idx |= 0x100; 								\
+	if( _F & HF ) idx |= 0x200; 								\
+	if( _F & NF ) idx |= 0x400; 								\
+	_AF = DAATable[idx];										\
+}
+
+/***************************************************************
+ * AND	n
+ ***************************************************************/
+#define AND(value)												\
+	_A &= value;												\
+	_F = SZP[_A] | HF
+
+/***************************************************************
+ * OR	n
+ ***************************************************************/
+#define OR(value)												\
+	_A |= value;												\
+	_F = SZP[_A]
+
+/***************************************************************
+ * XOR	n
+ ***************************************************************/
+#define XOR(value)												\
+	_A ^= value;												\
+	_F = SZP[_A]
+
+/***************************************************************
+ * CP	n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define CP(value)												\
+ asm (															\
+ " cmpb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %2,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define CP(value)												\
+ asm (															\
+ " cmpb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define CP(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) - value);					\
+	_F = SZHVC_sub[ah | res];									\
+}
+#else
+#define CP(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val;									\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		((((val ^ _A) & (_A ^ res)) >> 5) & VF);				\
+}
+#endif
+#endif
+
+/***************************************************************
+ * EX	AF,AF'
+ ***************************************************************/
+#define EX_AF { 												\
+	PAIR tmp;													\
+	tmp = Z80.AF; Z80.AF = Z80.AF2; Z80.AF2 = tmp;				\
+}
+
+/***************************************************************
+ * EX	DE,HL
+ ***************************************************************/
+#define EX_DE_HL {												\
+	PAIR tmp;													\
+	tmp = Z80.DE; Z80.DE = Z80.HL; Z80.HL = tmp;				\
+}
+
+/***************************************************************
+ * EXX
+ ***************************************************************/
+#define EXX {													\
+	PAIR tmp;													\
+	tmp = Z80.BC; Z80.BC = Z80.BC2; Z80.BC2 = tmp;				\
+	tmp = Z80.DE; Z80.DE = Z80.DE2; Z80.DE2 = tmp;				\
+	tmp = Z80.HL; Z80.HL = Z80.HL2; Z80.HL2 = tmp;				\
+}
+
+/***************************************************************
+ * EX	(SP),r16
+ ***************************************************************/
+#define EXSP(DR)												\
+{																\
+	PAIR tmp = { { 0, 0, 0, 0 } };								\
+	RM16( _SPD, &tmp ); 										\
+	WM16( _SPD, &Z80.DR );										\
+	Z80.DR = tmp;												\
+}
+
+
+/***************************************************************
+ * ADD16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define ADD16(DR,SR)											\
+ asm (															\
+ " andb $0xc4,%1        \n"                                     \
+ " addb %%dl,%%cl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " andb $0x11,%%ah      \n"                                     \
+ " orb %%ah,%1          \n"                                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (Z80.DR.d), "=r" (_F)                                    \
+ :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d)                      \
+ )
+#else
+#define ADD16(DR,SR)											\
+ asm (															\
+ " andb $0xc4,%1        \n"                                     \
+ " addb %%dl,%%cl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " andb $0x11,%%ah      \n"                                     \
+ " orb %%ah,%1          \n"                                     \
+ :"=c" (Z80.DR.d), "=r" (_F)                                    \
+ :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d)                      \
+ )
+#endif
+#else
+#define ADD16(DR,SR)											\
+{																\
+	UINT32 res = Z80.DR.d + Z80.SR.d;							\
+	_F = (_F & (SF | ZF | VF)) |								\
+		(((Z80.DR.d ^ res ^ Z80.SR.d) >> 8) & HF) | 			\
+		((res >> 16) & CF); 									\
+	Z80.DR.w.l = (UINT16)res;									\
+}
+#endif
+
+/***************************************************************
+ * ADC	r16,r16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define ADC16(Reg)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#else
+#define ADC16(Reg)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#endif
+#else
+#define ADC16(Reg)												\
+{																\
+	UINT32 res = _HLD + Z80.Reg.d + (_F & CF);					\
+	_F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) |				\
+		((res >> 16) & CF) |									\
+		((res >> 8) & SF) | 									\
+		((res & 0xffff) ? 0 : ZF) | 							\
+		(((Z80.Reg.d ^ _HLD ^ 0x8000) & (Z80.Reg.d ^ res) & 0x8000) >> 13); \
+	_HL = (UINT16)res;											\
+}
+#endif
+
+/***************************************************************
+ * SBC	r16,r16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define SBC16(Reg)												\
+asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " sbbb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " stc                  \n"                                     \
+ " adcb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#else
+#define SBC16(Reg)												\
+asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " sbbb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " stc                  \n"                                     \
+ " adcb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#endif
+#else
+#define SBC16(Reg)												\
+{																\
+	UINT32 res = _HLD - Z80.Reg.d - (_F & CF);					\
+	_F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | NF |			\
+		((res >> 16) & CF) |									\
+		((res >> 8) & SF) | 									\
+		((res & 0xffff) ? 0 : ZF) | 							\
+		(((Z80.Reg.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13);	\
+	_HL = (UINT16)res;											\
+}
+#endif
+
+/***************************************************************
+ * RLC	r8
+ ***************************************************************/
+static __inline__ UINT8 RLC(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | (res >> 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RRC	r8
+ ***************************************************************/
+static __inline__ UINT8 RRC(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (res << 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RL	r8
+ ***************************************************************/
+static __inline__ UINT8 RL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | (_F & CF)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RR	r8
+ ***************************************************************/
+static __inline__ UINT8 RR(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (_F << 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SLA	r8
+ ***************************************************************/
+static __inline__ UINT8 SLA(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = (res << 1) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SRA	r8
+ ***************************************************************/
+static __inline__ UINT8 SRA(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (res & 0x80)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SLL	r8
+ ***************************************************************/
+static __inline__ UINT8 SLL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | 0x01) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SRL	r8
+ ***************************************************************/
+static __inline__ UINT8 SRL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = (res >> 1) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * BIT	bit,r8
+ ***************************************************************/
+#define BIT(bit,reg)											\
+	_F = (_F & CF) | HF | SZ_BIT[reg & (1<<bit)]
+
+/***************************************************************
+ * BIT	bit,(IX/Y+o)
+ ***************************************************************/
+#if Z80_EXACT
+#define BIT_XY(bit,reg) 										\
+	_F = (_F & CF) | HF | (SZ_BIT[reg & (1<<bit)] & ~(YF|XF)) | ((EA>>8) & (YF|XF))
+#else
+#define BIT_XY	BIT
+#endif
+
+/***************************************************************
+ * RES	bit,r8
+ ***************************************************************/
+static __inline__ UINT8 RES(UINT8 bit, UINT8 value)
+{
+	return value & ~(1<<bit);
+}
+
+/***************************************************************
+ * SET	bit,r8
+ ***************************************************************/
+static __inline__ UINT8 SET(UINT8 bit, UINT8 value)
+{
+	return value | (1<<bit);
+}
+
+/***************************************************************
+ * LDI
+ ***************************************************************/
+#if Z80_EXACT
+#define LDI {													\
+	UINT8 io = RM(_HL); 										\
+	WM( _DE, io );												\
+	_F &= SF | ZF | CF; 										\
+	if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */		\
+	if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */		\
+	_HL++; _DE++; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define LDI {													\
+	WM( _DE, RM(_HL) ); 										\
+	_F &= SF | ZF | YF | XF | CF;								\
+	_HL++; _DE++; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * CPI
+ ***************************************************************/
+#if Z80_EXACT
+#define CPI {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL++; _BC--;												\
+	_F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF;  \
+	if( _F & HF ) res -= 1; 									\
+	if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */			\
+	if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */			\
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define CPI {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL++; _BC--;												\
+	_F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF;	\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * INI
+ ***************************************************************/
+#if Z80_EXACT
+#define INI {													\
+	UINT8 io = IN(_BC); 										\
+	_B--;														\
+	WM( _HL, io );												\
+	_HL++;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( ( ( (_C + 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; 	\
+	if( (irep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+		_F |= PF;												\
+}
+#else
+#define INI {													\
+	_B--;														\
+	WM( _HL, IN(_BC) ); 										\
+	_HL++;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * OUTI
+ ***************************************************************/
+#if Z80_EXACT
+#define OUTI {													\
+	UINT8 io = RM(_HL); 										\
+	_B--;														\
+	OUT( _BC, io ); 											\
+	_HL++;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( ( ( (_C + 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; 	\
+	if( (irep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+		_F |= PF;												\
+}
+#else
+#define OUTI {													\
+	_B--;														\
+	OUT( _BC, RM(_HL) );										\
+	_HL++;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * LDD
+ ***************************************************************/
+#if Z80_EXACT
+#define LDD {													\
+	UINT8 io = RM(_HL); 										\
+	WM( _DE, io );												\
+	_F &= SF | ZF | CF; 										\
+	if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */		\
+	if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */		\
+	_HL--; _DE--; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define LDD {													\
+	WM( _DE, RM(_HL) ); 										\
+	_F &= SF | ZF | YF | XF | CF;								\
+	_HL--; _DE--; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * CPD
+ ***************************************************************/
+#if Z80_EXACT
+#define CPD {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL--; _BC--;												\
+	_F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF;  \
+	if( _F & HF ) res -= 1; 									\
+	if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */			\
+	if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */			\
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define CPD {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL--; _BC--;												\
+	_F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF;	\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * IND
+ ***************************************************************/
+#if Z80_EXACT
+#define IND {													\
+	UINT8 io = IN(_BC); 										\
+	_B--;														\
+	WM( _HL, io );												\
+	_HL--;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( ( ( (_C - 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; 	\
+	if( (drep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+		_F |= PF;												\
+}
+#else
+#define IND {													\
+	_B--;														\
+	WM( _HL, IN(_BC) ); 										\
+	_HL--;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * OUTD
+ ***************************************************************/
+#if Z80_EXACT
+#define OUTD {													\
+	UINT8 io = RM(_HL); 										\
+	_B--;														\
+	OUT( _BC, io ); 											\
+	_HL--;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( ( ( (_C - 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; 	\
+	if( (drep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+		_F |= PF;												\
+}
+#else
+#define OUTD {													\
+	_B--;														\
+	OUT( _BC, RM(_HL) );										\
+	_HL--;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * LDIR
+ ***************************************************************/
+#define LDIR													\
+	LDI;														\
+	if( _BC )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb0);											\
+	}
+
+/***************************************************************
+ * CPIR
+ ***************************************************************/
+#define CPIR													\
+	CPI;														\
+	if( _BC && !(_F & ZF) ) 									\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb1);											\
+	}
+
+/***************************************************************
+ * INIR
+ ***************************************************************/
+#define INIR													\
+	INI;														\
+	if( _B )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb2);											\
+	}
+
+/***************************************************************
+ * OTIR
+ ***************************************************************/
+#define OTIR													\
+	OUTI;														\
+	if( _B )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb3);											\
+	}
+
+/***************************************************************
+ * LDDR
+ ***************************************************************/
+#define LDDR													\
+	LDD;														\
+	if( _BC )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb8);											\
+	}
+
+/***************************************************************
+ * CPDR
+ ***************************************************************/
+#define CPDR													\
+	CPD;														\
+	if( _BC && !(_F & ZF) ) 									\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xb9);											\
+	}
+
+/***************************************************************
+ * INDR
+ ***************************************************************/
+#define INDR													\
+	IND;														\
+	if( _B )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xba);											\
+	}
+
+/***************************************************************
+ * OTDR
+ ***************************************************************/
+#define OTDR													\
+	OUTD;														\
+	if( _B )													\
+	{															\
+		_PC -= 2;												\
+		CC(ex,0xbb);											\
+	}
+
+/***************************************************************
+ * EI
+ ***************************************************************/
+#define EI {													\
+	/* If interrupts were disabled, execute one more			\
+	 * instruction and check the IRQ line.						\
+	 * If not, simply set interrupt flip-flop 2 				\
+	 */ 														\
+	if( _IFF1 == 0 )											\
+	{															\
+		_IFF1 = _IFF2 = 1;										\
+		_PPC = _PCD;											\
+		_R++;													\
+		while( cpu_readop(_PCD) == 0xfb ) /* more EIs? */		\
+		{														\
+			CC(op,0xfb);										\
+			_PPC =_PCD; 										\
+			_PC++;												\
+			_R++;												\
+		}														\
+		if( Z80.irq_state != CLEAR_LINE ||						\
+			Z80.request_irq >= 0 )								\
+		{														\
+			after_EI = 1;	/* avoid cycle skip hacks */		\
+			EXEC(op,ROP()); 									\
+			after_EI = 0;										\
+			take_interrupt();									\
+		} else EXEC(op,ROP());									\
+	} else _IFF2 = 1;											\
+}
+
+/**********************************************************
+ * opcodes with CB prefix
+ * rotate, shift and bit operations
+ **********************************************************/
+OP(cb,00) { _B = RLC(_B);											} /* RLC  B 		  */
+OP(cb,01) { _C = RLC(_C);											} /* RLC  C 		  */
+OP(cb,02) { _D = RLC(_D);											} /* RLC  D 		  */
+OP(cb,03) { _E = RLC(_E);											} /* RLC  E 		  */
+OP(cb,04) { _H = RLC(_H);											} /* RLC  H 		  */
+OP(cb,05) { _L = RLC(_L);											} /* RLC  L 		  */
+OP(cb,06) { WM( _HL, RLC(RM(_HL)) );								} /* RLC  (HL)		  */
+OP(cb,07) { _A = RLC(_A);											} /* RLC  A 		  */
+
+OP(cb,08) { _B = RRC(_B);											} /* RRC  B 		  */
+OP(cb,09) { _C = RRC(_C);											} /* RRC  C 		  */
+OP(cb,0a) { _D = RRC(_D);											} /* RRC  D 		  */
+OP(cb,0b) { _E = RRC(_E);											} /* RRC  E 		  */
+OP(cb,0c) { _H = RRC(_H);											} /* RRC  H 		  */
+OP(cb,0d) { _L = RRC(_L);											} /* RRC  L 		  */
+OP(cb,0e) { WM( _HL, RRC(RM(_HL)) );								} /* RRC  (HL)		  */
+OP(cb,0f) { _A = RRC(_A);											} /* RRC  A 		  */
+
+OP(cb,10) { _B = RL(_B);											} /* RL   B 		  */
+OP(cb,11) { _C = RL(_C);											} /* RL   C 		  */
+OP(cb,12) { _D = RL(_D);											} /* RL   D 		  */
+OP(cb,13) { _E = RL(_E);											} /* RL   E 		  */
+OP(cb,14) { _H = RL(_H);											} /* RL   H 		  */
+OP(cb,15) { _L = RL(_L);											} /* RL   L 		  */
+OP(cb,16) { WM( _HL, RL(RM(_HL)) ); 								} /* RL   (HL)		  */
+OP(cb,17) { _A = RL(_A);											} /* RL   A 		  */
+
+OP(cb,18) { _B = RR(_B);											} /* RR   B 		  */
+OP(cb,19) { _C = RR(_C);											} /* RR   C 		  */
+OP(cb,1a) { _D = RR(_D);											} /* RR   D 		  */
+OP(cb,1b) { _E = RR(_E);											} /* RR   E 		  */
+OP(cb,1c) { _H = RR(_H);											} /* RR   H 		  */
+OP(cb,1d) { _L = RR(_L);											} /* RR   L 		  */
+OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); 								} /* RR   (HL)		  */
+OP(cb,1f) { _A = RR(_A);											} /* RR   A 		  */
+
+OP(cb,20) { _B = SLA(_B);											} /* SLA  B 		  */
+OP(cb,21) { _C = SLA(_C);											} /* SLA  C 		  */
+OP(cb,22) { _D = SLA(_D);											} /* SLA  D 		  */
+OP(cb,23) { _E = SLA(_E);											} /* SLA  E 		  */
+OP(cb,24) { _H = SLA(_H);											} /* SLA  H 		  */
+OP(cb,25) { _L = SLA(_L);											} /* SLA  L 		  */
+OP(cb,26) { WM( _HL, SLA(RM(_HL)) );								} /* SLA  (HL)		  */
+OP(cb,27) { _A = SLA(_A);											} /* SLA  A 		  */
+
+OP(cb,28) { _B = SRA(_B);											} /* SRA  B 		  */
+OP(cb,29) { _C = SRA(_C);											} /* SRA  C 		  */
+OP(cb,2a) { _D = SRA(_D);											} /* SRA  D 		  */
+OP(cb,2b) { _E = SRA(_E);											} /* SRA  E 		  */
+OP(cb,2c) { _H = SRA(_H);											} /* SRA  H 		  */
+OP(cb,2d) { _L = SRA(_L);											} /* SRA  L 		  */
+OP(cb,2e) { WM( _HL, SRA(RM(_HL)) );								} /* SRA  (HL)		  */
+OP(cb,2f) { _A = SRA(_A);											} /* SRA  A 		  */
+
+OP(cb,30) { _B = SLL(_B);											} /* SLL  B 		  */
+OP(cb,31) { _C = SLL(_C);											} /* SLL  C 		  */
+OP(cb,32) { _D = SLL(_D);											} /* SLL  D 		  */
+OP(cb,33) { _E = SLL(_E);											} /* SLL  E 		  */
+OP(cb,34) { _H = SLL(_H);											} /* SLL  H 		  */
+OP(cb,35) { _L = SLL(_L);											} /* SLL  L 		  */
+OP(cb,36) { WM( _HL, SLL(RM(_HL)) );								} /* SLL  (HL)		  */
+OP(cb,37) { _A = SLL(_A);											} /* SLL  A 		  */
+
+OP(cb,38) { _B = SRL(_B);											} /* SRL  B 		  */
+OP(cb,39) { _C = SRL(_C);											} /* SRL  C 		  */
+OP(cb,3a) { _D = SRL(_D);											} /* SRL  D 		  */
+OP(cb,3b) { _E = SRL(_E);											} /* SRL  E 		  */
+OP(cb,3c) { _H = SRL(_H);											} /* SRL  H 		  */
+OP(cb,3d) { _L = SRL(_L);											} /* SRL  L 		  */
+OP(cb,3e) { WM( _HL, SRL(RM(_HL)) );								} /* SRL  (HL)		  */
+OP(cb,3f) { _A = SRL(_A);											} /* SRL  A 		  */
+
+OP(cb,40) { BIT(0,_B);												} /* BIT  0,B		  */
+OP(cb,41) { BIT(0,_C);												} /* BIT  0,C		  */
+OP(cb,42) { BIT(0,_D);												} /* BIT  0,D		  */
+OP(cb,43) { BIT(0,_E);												} /* BIT  0,E		  */
+OP(cb,44) { BIT(0,_H);												} /* BIT  0,H		  */
+OP(cb,45) { BIT(0,_L);												} /* BIT  0,L		  */
+OP(cb,46) { BIT(0,RM(_HL)); 										} /* BIT  0,(HL)	  */
+OP(cb,47) { BIT(0,_A);												} /* BIT  0,A		  */
+
+OP(cb,48) { BIT(1,_B);												} /* BIT  1,B		  */
+OP(cb,49) { BIT(1,_C);												} /* BIT  1,C		  */
+OP(cb,4a) { BIT(1,_D);												} /* BIT  1,D		  */
+OP(cb,4b) { BIT(1,_E);												} /* BIT  1,E		  */
+OP(cb,4c) { BIT(1,_H);												} /* BIT  1,H		  */
+OP(cb,4d) { BIT(1,_L);												} /* BIT  1,L		  */
+OP(cb,4e) { BIT(1,RM(_HL)); 										} /* BIT  1,(HL)	  */
+OP(cb,4f) { BIT(1,_A);												} /* BIT  1,A		  */
+
+OP(cb,50) { BIT(2,_B);												} /* BIT  2,B		  */
+OP(cb,51) { BIT(2,_C);												} /* BIT  2,C		  */
+OP(cb,52) { BIT(2,_D);												} /* BIT  2,D		  */
+OP(cb,53) { BIT(2,_E);												} /* BIT  2,E		  */
+OP(cb,54) { BIT(2,_H);												} /* BIT  2,H		  */
+OP(cb,55) { BIT(2,_L);												} /* BIT  2,L		  */
+OP(cb,56) { BIT(2,RM(_HL)); 										} /* BIT  2,(HL)	  */
+OP(cb,57) { BIT(2,_A);												} /* BIT  2,A		  */
+
+OP(cb,58) { BIT(3,_B);												} /* BIT  3,B		  */
+OP(cb,59) { BIT(3,_C);												} /* BIT  3,C		  */
+OP(cb,5a) { BIT(3,_D);												} /* BIT  3,D		  */
+OP(cb,5b) { BIT(3,_E);												} /* BIT  3,E		  */
+OP(cb,5c) { BIT(3,_H);												} /* BIT  3,H		  */
+OP(cb,5d) { BIT(3,_L);												} /* BIT  3,L		  */
+OP(cb,5e) { BIT(3,RM(_HL)); 										} /* BIT  3,(HL)	  */
+OP(cb,5f) { BIT(3,_A);												} /* BIT  3,A		  */
+
+OP(cb,60) { BIT(4,_B);												} /* BIT  4,B		  */
+OP(cb,61) { BIT(4,_C);												} /* BIT  4,C		  */
+OP(cb,62) { BIT(4,_D);												} /* BIT  4,D		  */
+OP(cb,63) { BIT(4,_E);												} /* BIT  4,E		  */
+OP(cb,64) { BIT(4,_H);												} /* BIT  4,H		  */
+OP(cb,65) { BIT(4,_L);												} /* BIT  4,L		  */
+OP(cb,66) { BIT(4,RM(_HL)); 										} /* BIT  4,(HL)	  */
+OP(cb,67) { BIT(4,_A);												} /* BIT  4,A		  */
+
+OP(cb,68) { BIT(5,_B);												} /* BIT  5,B		  */
+OP(cb,69) { BIT(5,_C);												} /* BIT  5,C		  */
+OP(cb,6a) { BIT(5,_D);												} /* BIT  5,D		  */
+OP(cb,6b) { BIT(5,_E);												} /* BIT  5,E		  */
+OP(cb,6c) { BIT(5,_H);												} /* BIT  5,H		  */
+OP(cb,6d) { BIT(5,_L);												} /* BIT  5,L		  */
+OP(cb,6e) { BIT(5,RM(_HL)); 										} /* BIT  5,(HL)	  */
+OP(cb,6f) { BIT(5,_A);												} /* BIT  5,A		  */
+
+OP(cb,70) { BIT(6,_B);												} /* BIT  6,B		  */
+OP(cb,71) { BIT(6,_C);												} /* BIT  6,C		  */
+OP(cb,72) { BIT(6,_D);												} /* BIT  6,D		  */
+OP(cb,73) { BIT(6,_E);												} /* BIT  6,E		  */
+OP(cb,74) { BIT(6,_H);												} /* BIT  6,H		  */
+OP(cb,75) { BIT(6,_L);												} /* BIT  6,L		  */
+OP(cb,76) { BIT(6,RM(_HL)); 										} /* BIT  6,(HL)	  */
+OP(cb,77) { BIT(6,_A);												} /* BIT  6,A		  */
+
+OP(cb,78) { BIT(7,_B);												} /* BIT  7,B		  */
+OP(cb,79) { BIT(7,_C);												} /* BIT  7,C		  */
+OP(cb,7a) { BIT(7,_D);												} /* BIT  7,D		  */
+OP(cb,7b) { BIT(7,_E);												} /* BIT  7,E		  */
+OP(cb,7c) { BIT(7,_H);												} /* BIT  7,H		  */
+OP(cb,7d) { BIT(7,_L);												} /* BIT  7,L		  */
+OP(cb,7e) { BIT(7,RM(_HL)); 										} /* BIT  7,(HL)	  */
+OP(cb,7f) { BIT(7,_A);												} /* BIT  7,A		  */
+
+OP(cb,80) { _B = RES(0,_B); 										} /* RES  0,B		  */
+OP(cb,81) { _C = RES(0,_C); 										} /* RES  0,C		  */
+OP(cb,82) { _D = RES(0,_D); 										} /* RES  0,D		  */
+OP(cb,83) { _E = RES(0,_E); 										} /* RES  0,E		  */
+OP(cb,84) { _H = RES(0,_H); 										} /* RES  0,H		  */
+OP(cb,85) { _L = RES(0,_L); 										} /* RES  0,L		  */
+OP(cb,86) { WM( _HL, RES(0,RM(_HL)) );								} /* RES  0,(HL)	  */
+OP(cb,87) { _A = RES(0,_A); 										} /* RES  0,A		  */
+
+OP(cb,88) { _B = RES(1,_B); 										} /* RES  1,B		  */
+OP(cb,89) { _C = RES(1,_C); 										} /* RES  1,C		  */
+OP(cb,8a) { _D = RES(1,_D); 										} /* RES  1,D		  */
+OP(cb,8b) { _E = RES(1,_E); 										} /* RES  1,E		  */
+OP(cb,8c) { _H = RES(1,_H); 										} /* RES  1,H		  */
+OP(cb,8d) { _L = RES(1,_L); 										} /* RES  1,L		  */
+OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) );								} /* RES  1,(HL)	  */
+OP(cb,8f) { _A = RES(1,_A); 										} /* RES  1,A		  */
+
+OP(cb,90) { _B = RES(2,_B); 										} /* RES  2,B		  */
+OP(cb,91) { _C = RES(2,_C); 										} /* RES  2,C		  */
+OP(cb,92) { _D = RES(2,_D); 										} /* RES  2,D		  */
+OP(cb,93) { _E = RES(2,_E); 										} /* RES  2,E		  */
+OP(cb,94) { _H = RES(2,_H); 										} /* RES  2,H		  */
+OP(cb,95) { _L = RES(2,_L); 										} /* RES  2,L		  */
+OP(cb,96) { WM( _HL, RES(2,RM(_HL)) );								} /* RES  2,(HL)	  */
+OP(cb,97) { _A = RES(2,_A); 										} /* RES  2,A		  */
+
+OP(cb,98) { _B = RES(3,_B); 										} /* RES  3,B		  */
+OP(cb,99) { _C = RES(3,_C); 										} /* RES  3,C		  */
+OP(cb,9a) { _D = RES(3,_D); 										} /* RES  3,D		  */
+OP(cb,9b) { _E = RES(3,_E); 										} /* RES  3,E		  */
+OP(cb,9c) { _H = RES(3,_H); 										} /* RES  3,H		  */
+OP(cb,9d) { _L = RES(3,_L); 										} /* RES  3,L		  */
+OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) );								} /* RES  3,(HL)	  */
+OP(cb,9f) { _A = RES(3,_A); 										} /* RES  3,A		  */
+
+OP(cb,a0) { _B = RES(4,_B); 										} /* RES  4,B		  */
+OP(cb,a1) { _C = RES(4,_C); 										} /* RES  4,C		  */
+OP(cb,a2) { _D = RES(4,_D); 										} /* RES  4,D		  */
+OP(cb,a3) { _E = RES(4,_E); 										} /* RES  4,E		  */
+OP(cb,a4) { _H = RES(4,_H); 										} /* RES  4,H		  */
+OP(cb,a5) { _L = RES(4,_L); 										} /* RES  4,L		  */
+OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) );								} /* RES  4,(HL)	  */
+OP(cb,a7) { _A = RES(4,_A); 										} /* RES  4,A		  */
+
+OP(cb,a8) { _B = RES(5,_B); 										} /* RES  5,B		  */
+OP(cb,a9) { _C = RES(5,_C); 										} /* RES  5,C		  */
+OP(cb,aa) { _D = RES(5,_D); 										} /* RES  5,D		  */
+OP(cb,ab) { _E = RES(5,_E); 										} /* RES  5,E		  */
+OP(cb,ac) { _H = RES(5,_H); 										} /* RES  5,H		  */
+OP(cb,ad) { _L = RES(5,_L); 										} /* RES  5,L		  */
+OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) );								} /* RES  5,(HL)	  */
+OP(cb,af) { _A = RES(5,_A); 										} /* RES  5,A		  */
+
+OP(cb,b0) { _B = RES(6,_B); 										} /* RES  6,B		  */
+OP(cb,b1) { _C = RES(6,_C); 										} /* RES  6,C		  */
+OP(cb,b2) { _D = RES(6,_D); 										} /* RES  6,D		  */
+OP(cb,b3) { _E = RES(6,_E); 										} /* RES  6,E		  */
+OP(cb,b4) { _H = RES(6,_H); 										} /* RES  6,H		  */
+OP(cb,b5) { _L = RES(6,_L); 										} /* RES  6,L		  */
+OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) );								} /* RES  6,(HL)	  */
+OP(cb,b7) { _A = RES(6,_A); 										} /* RES  6,A		  */
+
+OP(cb,b8) { _B = RES(7,_B); 										} /* RES  7,B		  */
+OP(cb,b9) { _C = RES(7,_C); 										} /* RES  7,C		  */
+OP(cb,ba) { _D = RES(7,_D); 										} /* RES  7,D		  */
+OP(cb,bb) { _E = RES(7,_E); 										} /* RES  7,E		  */
+OP(cb,bc) { _H = RES(7,_H); 										} /* RES  7,H		  */
+OP(cb,bd) { _L = RES(7,_L); 										} /* RES  7,L		  */
+OP(cb,be) { WM( _HL, RES(7,RM(_HL)) );								} /* RES  7,(HL)	  */
+OP(cb,bf) { _A = RES(7,_A); 										} /* RES  7,A		  */
+
+OP(cb,c0) { _B = SET(0,_B); 										} /* SET  0,B		  */
+OP(cb,c1) { _C = SET(0,_C); 										} /* SET  0,C		  */
+OP(cb,c2) { _D = SET(0,_D); 										} /* SET  0,D		  */
+OP(cb,c3) { _E = SET(0,_E); 										} /* SET  0,E		  */
+OP(cb,c4) { _H = SET(0,_H); 										} /* SET  0,H		  */
+OP(cb,c5) { _L = SET(0,_L); 										} /* SET  0,L		  */
+OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) );								} /* SET  0,(HL)	  */
+OP(cb,c7) { _A = SET(0,_A); 										} /* SET  0,A		  */
+
+OP(cb,c8) { _B = SET(1,_B); 										} /* SET  1,B		  */
+OP(cb,c9) { _C = SET(1,_C); 										} /* SET  1,C		  */
+OP(cb,ca) { _D = SET(1,_D); 										} /* SET  1,D		  */
+OP(cb,cb) { _E = SET(1,_E); 										} /* SET  1,E		  */
+OP(cb,cc) { _H = SET(1,_H); 										} /* SET  1,H		  */
+OP(cb,cd) { _L = SET(1,_L); 										} /* SET  1,L		  */
+OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) );								} /* SET  1,(HL)	  */
+OP(cb,cf) { _A = SET(1,_A); 										} /* SET  1,A		  */
+
+OP(cb,d0) { _B = SET(2,_B); 										} /* SET  2,B		  */
+OP(cb,d1) { _C = SET(2,_C); 										} /* SET  2,C		  */
+OP(cb,d2) { _D = SET(2,_D); 										} /* SET  2,D		  */
+OP(cb,d3) { _E = SET(2,_E); 										} /* SET  2,E		  */
+OP(cb,d4) { _H = SET(2,_H); 										} /* SET  2,H		  */
+OP(cb,d5) { _L = SET(2,_L); 										} /* SET  2,L		  */
+OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) );								}/* SET  2,(HL) 	 */
+OP(cb,d7) { _A = SET(2,_A); 										} /* SET  2,A		  */
+
+OP(cb,d8) { _B = SET(3,_B); 										} /* SET  3,B		  */
+OP(cb,d9) { _C = SET(3,_C); 										} /* SET  3,C		  */
+OP(cb,da) { _D = SET(3,_D); 										} /* SET  3,D		  */
+OP(cb,db) { _E = SET(3,_E); 										} /* SET  3,E		  */
+OP(cb,dc) { _H = SET(3,_H); 										} /* SET  3,H		  */
+OP(cb,dd) { _L = SET(3,_L); 										} /* SET  3,L		  */
+OP(cb,de) { WM( _HL, SET(3,RM(_HL)) );								} /* SET  3,(HL)	  */
+OP(cb,df) { _A = SET(3,_A); 										} /* SET  3,A		  */
+
+OP(cb,e0) { _B = SET(4,_B); 										} /* SET  4,B		  */
+OP(cb,e1) { _C = SET(4,_C); 										} /* SET  4,C		  */
+OP(cb,e2) { _D = SET(4,_D); 										} /* SET  4,D		  */
+OP(cb,e3) { _E = SET(4,_E); 										} /* SET  4,E		  */
+OP(cb,e4) { _H = SET(4,_H); 										} /* SET  4,H		  */
+OP(cb,e5) { _L = SET(4,_L); 										} /* SET  4,L		  */
+OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) );								} /* SET  4,(HL)	  */
+OP(cb,e7) { _A = SET(4,_A); 										} /* SET  4,A		  */
+
+OP(cb,e8) { _B = SET(5,_B); 										} /* SET  5,B		  */
+OP(cb,e9) { _C = SET(5,_C); 										} /* SET  5,C		  */
+OP(cb,ea) { _D = SET(5,_D); 										} /* SET  5,D		  */
+OP(cb,eb) { _E = SET(5,_E); 										} /* SET  5,E		  */
+OP(cb,ec) { _H = SET(5,_H); 										} /* SET  5,H		  */
+OP(cb,ed) { _L = SET(5,_L); 										} /* SET  5,L		  */
+OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) );								} /* SET  5,(HL)	  */
+OP(cb,ef) { _A = SET(5,_A); 										} /* SET  5,A		  */
+
+OP(cb,f0) { _B = SET(6,_B); 										} /* SET  6,B		  */
+OP(cb,f1) { _C = SET(6,_C); 										} /* SET  6,C		  */
+OP(cb,f2) { _D = SET(6,_D); 										} /* SET  6,D		  */
+OP(cb,f3) { _E = SET(6,_E); 										} /* SET  6,E		  */
+OP(cb,f4) { _H = SET(6,_H); 										} /* SET  6,H		  */
+OP(cb,f5) { _L = SET(6,_L); 										} /* SET  6,L		  */
+OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) );								} /* SET  6,(HL)	  */
+OP(cb,f7) { _A = SET(6,_A); 										} /* SET  6,A		  */
+
+OP(cb,f8) { _B = SET(7,_B); 										} /* SET  7,B		  */
+OP(cb,f9) { _C = SET(7,_C); 										} /* SET  7,C		  */
+OP(cb,fa) { _D = SET(7,_D); 										} /* SET  7,D		  */
+OP(cb,fb) { _E = SET(7,_E); 										} /* SET  7,E		  */
+OP(cb,fc) { _H = SET(7,_H); 										} /* SET  7,H		  */
+OP(cb,fd) { _L = SET(7,_L); 										} /* SET  7,L		  */
+OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) );								} /* SET  7,(HL)	  */
+OP(cb,ff) { _A = SET(7,_A); 										} /* SET  7,A		  */
+
+
+/**********************************************************
+* opcodes with DD/FD CB prefix
+* rotate, shift and bit operations with (IX+o)
+**********************************************************/
+OP(xycb,00) { _B = RLC( RM(EA) ); WM( EA,_B );						} /* RLC  B=(XY+o)	  */
+OP(xycb,01) { _C = RLC( RM(EA) ); WM( EA,_C );						} /* RLC  C=(XY+o)	  */
+OP(xycb,02) { _D = RLC( RM(EA) ); WM( EA,_D );						} /* RLC  D=(XY+o)	  */
+OP(xycb,03) { _E = RLC( RM(EA) ); WM( EA,_E );						} /* RLC  E=(XY+o)	  */
+OP(xycb,04) { _H = RLC( RM(EA) ); WM( EA,_H );						} /* RLC  H=(XY+o)	  */
+OP(xycb,05) { _L = RLC( RM(EA) ); WM( EA,_L );						} /* RLC  L=(XY+o)	  */
+OP(xycb,06) { WM( EA, RLC( RM(EA) ) );								} /* RLC  (XY+o)	  */
+OP(xycb,07) { _A = RLC( RM(EA) ); WM( EA,_A );						} /* RLC  A=(XY+o)	  */
+
+OP(xycb,08) { _B = RRC( RM(EA) ); WM( EA,_B );						} /* RRC  B=(XY+o)	  */
+OP(xycb,09) { _C = RRC( RM(EA) ); WM( EA,_C );						} /* RRC  C=(XY+o)	  */
+OP(xycb,0a) { _D = RRC( RM(EA) ); WM( EA,_D );						} /* RRC  D=(XY+o)	  */
+OP(xycb,0b) { _E = RRC( RM(EA) ); WM( EA,_E );						} /* RRC  E=(XY+o)	  */
+OP(xycb,0c) { _H = RRC( RM(EA) ); WM( EA,_H );						} /* RRC  H=(XY+o)	  */
+OP(xycb,0d) { _L = RRC( RM(EA) ); WM( EA,_L );						} /* RRC  L=(XY+o)	  */
+OP(xycb,0e) { WM( EA,RRC( RM(EA) ) );								} /* RRC  (XY+o)	  */
+OP(xycb,0f) { _A = RRC( RM(EA) ); WM( EA,_A );						} /* RRC  A=(XY+o)	  */
+
+OP(xycb,10) { _B = RL( RM(EA) ); WM( EA,_B );						} /* RL   B=(XY+o)	  */
+OP(xycb,11) { _C = RL( RM(EA) ); WM( EA,_C );						} /* RL   C=(XY+o)	  */
+OP(xycb,12) { _D = RL( RM(EA) ); WM( EA,_D );						} /* RL   D=(XY+o)	  */
+OP(xycb,13) { _E = RL( RM(EA) ); WM( EA,_E );						} /* RL   E=(XY+o)	  */
+OP(xycb,14) { _H = RL( RM(EA) ); WM( EA,_H );						} /* RL   H=(XY+o)	  */
+OP(xycb,15) { _L = RL( RM(EA) ); WM( EA,_L );						} /* RL   L=(XY+o)	  */
+OP(xycb,16) { WM( EA,RL( RM(EA) ) );								} /* RL   (XY+o)	  */
+OP(xycb,17) { _A = RL( RM(EA) ); WM( EA,_A );						} /* RL   A=(XY+o)	  */
+
+OP(xycb,18) { _B = RR( RM(EA) ); WM( EA,_B );						} /* RR   B=(XY+o)	  */
+OP(xycb,19) { _C = RR( RM(EA) ); WM( EA,_C );						} /* RR   C=(XY+o)	  */
+OP(xycb,1a) { _D = RR( RM(EA) ); WM( EA,_D );						} /* RR   D=(XY+o)	  */
+OP(xycb,1b) { _E = RR( RM(EA) ); WM( EA,_E );						} /* RR   E=(XY+o)	  */
+OP(xycb,1c) { _H = RR( RM(EA) ); WM( EA,_H );						} /* RR   H=(XY+o)	  */
+OP(xycb,1d) { _L = RR( RM(EA) ); WM( EA,_L );						} /* RR   L=(XY+o)	  */
+OP(xycb,1e) { WM( EA,RR( RM(EA) ) );								} /* RR   (XY+o)	  */
+OP(xycb,1f) { _A = RR( RM(EA) ); WM( EA,_A );						} /* RR   A=(XY+o)	  */
+
+OP(xycb,20) { _B = SLA( RM(EA) ); WM( EA,_B );						} /* SLA  B=(XY+o)	  */
+OP(xycb,21) { _C = SLA( RM(EA) ); WM( EA,_C );						} /* SLA  C=(XY+o)	  */
+OP(xycb,22) { _D = SLA( RM(EA) ); WM( EA,_D );						} /* SLA  D=(XY+o)	  */
+OP(xycb,23) { _E = SLA( RM(EA) ); WM( EA,_E );						} /* SLA  E=(XY+o)	  */
+OP(xycb,24) { _H = SLA( RM(EA) ); WM( EA,_H );						} /* SLA  H=(XY+o)	  */
+OP(xycb,25) { _L = SLA( RM(EA) ); WM( EA,_L );						} /* SLA  L=(XY+o)	  */
+OP(xycb,26) { WM( EA,SLA( RM(EA) ) );								} /* SLA  (XY+o)	  */
+OP(xycb,27) { _A = SLA( RM(EA) ); WM( EA,_A );						} /* SLA  A=(XY+o)	  */
+
+OP(xycb,28) { _B = SRA( RM(EA) ); WM( EA,_B );						} /* SRA  B=(XY+o)	  */
+OP(xycb,29) { _C = SRA( RM(EA) ); WM( EA,_C );						} /* SRA  C=(XY+o)	  */
+OP(xycb,2a) { _D = SRA( RM(EA) ); WM( EA,_D );						} /* SRA  D=(XY+o)	  */
+OP(xycb,2b) { _E = SRA( RM(EA) ); WM( EA,_E );						} /* SRA  E=(XY+o)	  */
+OP(xycb,2c) { _H = SRA( RM(EA) ); WM( EA,_H );						} /* SRA  H=(XY+o)	  */
+OP(xycb,2d) { _L = SRA( RM(EA) ); WM( EA,_L );						} /* SRA  L=(XY+o)	  */
+OP(xycb,2e) { WM( EA,SRA( RM(EA) ) );								} /* SRA  (XY+o)	  */
+OP(xycb,2f) { _A = SRA( RM(EA) ); WM( EA,_A );						} /* SRA  A=(XY+o)	  */
+
+OP(xycb,30) { _B = SLL( RM(EA) ); WM( EA,_B );						} /* SLL  B=(XY+o)	  */
+OP(xycb,31) { _C = SLL( RM(EA) ); WM( EA,_C );						} /* SLL  C=(XY+o)	  */
+OP(xycb,32) { _D = SLL( RM(EA) ); WM( EA,_D );						} /* SLL  D=(XY+o)	  */
+OP(xycb,33) { _E = SLL( RM(EA) ); WM( EA,_E );						} /* SLL  E=(XY+o)	  */
+OP(xycb,34) { _H = SLL( RM(EA) ); WM( EA,_H );						} /* SLL  H=(XY+o)	  */
+OP(xycb,35) { _L = SLL( RM(EA) ); WM( EA,_L );						} /* SLL  L=(XY+o)	  */
+OP(xycb,36) { WM( EA,SLL( RM(EA) ) );								} /* SLL  (XY+o)	  */
+OP(xycb,37) { _A = SLL( RM(EA) ); WM( EA,_A );						} /* SLL  A=(XY+o)	  */
+
+OP(xycb,38) { _B = SRL( RM(EA) ); WM( EA,_B );						} /* SRL  B=(XY+o)	  */
+OP(xycb,39) { _C = SRL( RM(EA) ); WM( EA,_C );						} /* SRL  C=(XY+o)	  */
+OP(xycb,3a) { _D = SRL( RM(EA) ); WM( EA,_D );						} /* SRL  D=(XY+o)	  */
+OP(xycb,3b) { _E = SRL( RM(EA) ); WM( EA,_E );						} /* SRL  E=(XY+o)	  */
+OP(xycb,3c) { _H = SRL( RM(EA) ); WM( EA,_H );						} /* SRL  H=(XY+o)	  */
+OP(xycb,3d) { _L = SRL( RM(EA) ); WM( EA,_L );						} /* SRL  L=(XY+o)	  */
+OP(xycb,3e) { WM( EA,SRL( RM(EA) ) );								} /* SRL  (XY+o)	  */
+OP(xycb,3f) { _A = SRL( RM(EA) ); WM( EA,_A );						} /* SRL  A=(XY+o)	  */
+
+OP(xycb,40) { xycb_46();											} /* BIT  0,B=(XY+o)  */
+OP(xycb,41) { xycb_46();													  } /* BIT	0,C=(XY+o)	*/
+OP(xycb,42) { xycb_46();											} /* BIT  0,D=(XY+o)  */
+OP(xycb,43) { xycb_46();											} /* BIT  0,E=(XY+o)  */
+OP(xycb,44) { xycb_46();											} /* BIT  0,H=(XY+o)  */
+OP(xycb,45) { xycb_46();											} /* BIT  0,L=(XY+o)  */
+OP(xycb,46) { BIT_XY(0,RM(EA)); 									} /* BIT  0,(XY+o)	  */
+OP(xycb,47) { xycb_46();											} /* BIT  0,A=(XY+o)  */
+
+OP(xycb,48) { xycb_4e();											} /* BIT  1,B=(XY+o)  */
+OP(xycb,49) { xycb_4e();													  } /* BIT	1,C=(XY+o)	*/
+OP(xycb,4a) { xycb_4e();											} /* BIT  1,D=(XY+o)  */
+OP(xycb,4b) { xycb_4e();											} /* BIT  1,E=(XY+o)  */
+OP(xycb,4c) { xycb_4e();											} /* BIT  1,H=(XY+o)  */
+OP(xycb,4d) { xycb_4e();											} /* BIT  1,L=(XY+o)  */
+OP(xycb,4e) { BIT_XY(1,RM(EA)); 									} /* BIT  1,(XY+o)	  */
+OP(xycb,4f) { xycb_4e();											} /* BIT  1,A=(XY+o)  */
+
+OP(xycb,50) { xycb_56();											} /* BIT  2,B=(XY+o)  */
+OP(xycb,51) { xycb_56();													  } /* BIT	2,C=(XY+o)	*/
+OP(xycb,52) { xycb_56();											} /* BIT  2,D=(XY+o)  */
+OP(xycb,53) { xycb_56();											} /* BIT  2,E=(XY+o)  */
+OP(xycb,54) { xycb_56();											} /* BIT  2,H=(XY+o)  */
+OP(xycb,55) { xycb_56();											} /* BIT  2,L=(XY+o)  */
+OP(xycb,56) { BIT_XY(2,RM(EA)); 									} /* BIT  2,(XY+o)	  */
+OP(xycb,57) { xycb_56();											} /* BIT  2,A=(XY+o)  */
+
+OP(xycb,58) { xycb_5e();											} /* BIT  3,B=(XY+o)  */
+OP(xycb,59) { xycb_5e();													  } /* BIT	3,C=(XY+o)	*/
+OP(xycb,5a) { xycb_5e();											} /* BIT  3,D=(XY+o)  */
+OP(xycb,5b) { xycb_5e();											} /* BIT  3,E=(XY+o)  */
+OP(xycb,5c) { xycb_5e();											} /* BIT  3,H=(XY+o)  */
+OP(xycb,5d) { xycb_5e();											} /* BIT  3,L=(XY+o)  */
+OP(xycb,5e) { BIT_XY(3,RM(EA)); 									} /* BIT  3,(XY+o)	  */
+OP(xycb,5f) { xycb_5e();											} /* BIT  3,A=(XY+o)  */
+
+OP(xycb,60) { xycb_66();											} /* BIT  4,B=(XY+o)  */
+OP(xycb,61) { xycb_66();													  } /* BIT	4,C=(XY+o)	*/
+OP(xycb,62) { xycb_66();											} /* BIT  4,D=(XY+o)  */
+OP(xycb,63) { xycb_66();											} /* BIT  4,E=(XY+o)  */
+OP(xycb,64) { xycb_66();											} /* BIT  4,H=(XY+o)  */
+OP(xycb,65) { xycb_66();											} /* BIT  4,L=(XY+o)  */
+OP(xycb,66) { BIT_XY(4,RM(EA)); 									} /* BIT  4,(XY+o)	  */
+OP(xycb,67) { xycb_66();											} /* BIT  4,A=(XY+o)  */
+
+OP(xycb,68) { xycb_6e();											} /* BIT  5,B=(XY+o)  */
+OP(xycb,69) { xycb_6e();													  } /* BIT	5,C=(XY+o)	*/
+OP(xycb,6a) { xycb_6e();											} /* BIT  5,D=(XY+o)  */
+OP(xycb,6b) { xycb_6e();											} /* BIT  5,E=(XY+o)  */
+OP(xycb,6c) { xycb_6e();											} /* BIT  5,H=(XY+o)  */
+OP(xycb,6d) { xycb_6e();											} /* BIT  5,L=(XY+o)  */
+OP(xycb,6e) { BIT_XY(5,RM(EA)); 									} /* BIT  5,(XY+o)	  */
+OP(xycb,6f) { xycb_6e();											} /* BIT  5,A=(XY+o)  */
+
+OP(xycb,70) { xycb_76();											} /* BIT  6,B=(XY+o)  */
+OP(xycb,71) { xycb_76();													  } /* BIT	6,C=(XY+o)	*/
+OP(xycb,72) { xycb_76();											} /* BIT  6,D=(XY+o)  */
+OP(xycb,73) { xycb_76();											} /* BIT  6,E=(XY+o)  */
+OP(xycb,74) { xycb_76();											} /* BIT  6,H=(XY+o)  */
+OP(xycb,75) { xycb_76();											} /* BIT  6,L=(XY+o)  */
+OP(xycb,76) { BIT_XY(6,RM(EA)); 									} /* BIT  6,(XY+o)	  */
+OP(xycb,77) { xycb_76();											} /* BIT  6,A=(XY+o)  */
+
+OP(xycb,78) { xycb_7e();											} /* BIT  7,B=(XY+o)  */
+OP(xycb,79) { xycb_7e();													  } /* BIT	7,C=(XY+o)	*/
+OP(xycb,7a) { xycb_7e();											} /* BIT  7,D=(XY+o)  */
+OP(xycb,7b) { xycb_7e();											} /* BIT  7,E=(XY+o)  */
+OP(xycb,7c) { xycb_7e();											} /* BIT  7,H=(XY+o)  */
+OP(xycb,7d) { xycb_7e();											} /* BIT  7,L=(XY+o)  */
+OP(xycb,7e) { BIT_XY(7,RM(EA)); 									} /* BIT  7,(XY+o)	  */
+OP(xycb,7f) { xycb_7e();											} /* BIT  7,A=(XY+o)  */
+
+OP(xycb,80) { _B = RES(0, RM(EA) ); WM( EA,_B );					} /* RES  0,B=(XY+o)  */
+OP(xycb,81) { _C = RES(0, RM(EA) ); WM( EA,_C );					} /* RES  0,C=(XY+o)  */
+OP(xycb,82) { _D = RES(0, RM(EA) ); WM( EA,_D );					} /* RES  0,D=(XY+o)  */
+OP(xycb,83) { _E = RES(0, RM(EA) ); WM( EA,_E );					} /* RES  0,E=(XY+o)  */
+OP(xycb,84) { _H = RES(0, RM(EA) ); WM( EA,_H );					} /* RES  0,H=(XY+o)  */
+OP(xycb,85) { _L = RES(0, RM(EA) ); WM( EA,_L );					} /* RES  0,L=(XY+o)  */
+OP(xycb,86) { WM( EA, RES(0,RM(EA)) );								} /* RES  0,(XY+o)	  */
+OP(xycb,87) { _A = RES(0, RM(EA) ); WM( EA,_A );					} /* RES  0,A=(XY+o)  */
+
+OP(xycb,88) { _B = RES(1, RM(EA) ); WM( EA,_B );					} /* RES  1,B=(XY+o)  */
+OP(xycb,89) { _C = RES(1, RM(EA) ); WM( EA,_C );					} /* RES  1,C=(XY+o)  */
+OP(xycb,8a) { _D = RES(1, RM(EA) ); WM( EA,_D );					} /* RES  1,D=(XY+o)  */
+OP(xycb,8b) { _E = RES(1, RM(EA) ); WM( EA,_E );					} /* RES  1,E=(XY+o)  */
+OP(xycb,8c) { _H = RES(1, RM(EA) ); WM( EA,_H );					} /* RES  1,H=(XY+o)  */
+OP(xycb,8d) { _L = RES(1, RM(EA) ); WM( EA,_L );					} /* RES  1,L=(XY+o)  */
+OP(xycb,8e) { WM( EA, RES(1,RM(EA)) );								} /* RES  1,(XY+o)	  */
+OP(xycb,8f) { _A = RES(1, RM(EA) ); WM( EA,_A );					} /* RES  1,A=(XY+o)  */
+
+OP(xycb,90) { _B = RES(2, RM(EA) ); WM( EA,_B );					} /* RES  2,B=(XY+o)  */
+OP(xycb,91) { _C = RES(2, RM(EA) ); WM( EA,_C );					} /* RES  2,C=(XY+o)  */
+OP(xycb,92) { _D = RES(2, RM(EA) ); WM( EA,_D );					} /* RES  2,D=(XY+o)  */
+OP(xycb,93) { _E = RES(2, RM(EA) ); WM( EA,_E );					} /* RES  2,E=(XY+o)  */
+OP(xycb,94) { _H = RES(2, RM(EA) ); WM( EA,_H );					} /* RES  2,H=(XY+o)  */
+OP(xycb,95) { _L = RES(2, RM(EA) ); WM( EA,_L );					} /* RES  2,L=(XY+o)  */
+OP(xycb,96) { WM( EA, RES(2,RM(EA)) );								} /* RES  2,(XY+o)	  */
+OP(xycb,97) { _A = RES(2, RM(EA) ); WM( EA,_A );					} /* RES  2,A=(XY+o)  */
+
+OP(xycb,98) { _B = RES(3, RM(EA) ); WM( EA,_B );					} /* RES  3,B=(XY+o)  */
+OP(xycb,99) { _C = RES(3, RM(EA) ); WM( EA,_C );					} /* RES  3,C=(XY+o)  */
+OP(xycb,9a) { _D = RES(3, RM(EA) ); WM( EA,_D );					} /* RES  3,D=(XY+o)  */
+OP(xycb,9b) { _E = RES(3, RM(EA) ); WM( EA,_E );					} /* RES  3,E=(XY+o)  */
+OP(xycb,9c) { _H = RES(3, RM(EA) ); WM( EA,_H );					} /* RES  3,H=(XY+o)  */
+OP(xycb,9d) { _L = RES(3, RM(EA) ); WM( EA,_L );					} /* RES  3,L=(XY+o)  */
+OP(xycb,9e) { WM( EA, RES(3,RM(EA)) );								} /* RES  3,(XY+o)	  */
+OP(xycb,9f) { _A = RES(3, RM(EA) ); WM( EA,_A );					} /* RES  3,A=(XY+o)  */
+
+OP(xycb,a0) { _B = RES(4, RM(EA) ); WM( EA,_B );					} /* RES  4,B=(XY+o)  */
+OP(xycb,a1) { _C = RES(4, RM(EA) ); WM( EA,_C );					} /* RES  4,C=(XY+o)  */
+OP(xycb,a2) { _D = RES(4, RM(EA) ); WM( EA,_D );					} /* RES  4,D=(XY+o)  */
+OP(xycb,a3) { _E = RES(4, RM(EA) ); WM( EA,_E );					} /* RES  4,E=(XY+o)  */
+OP(xycb,a4) { _H = RES(4, RM(EA) ); WM( EA,_H );					} /* RES  4,H=(XY+o)  */
+OP(xycb,a5) { _L = RES(4, RM(EA) ); WM( EA,_L );					} /* RES  4,L=(XY+o)  */
+OP(xycb,a6) { WM( EA, RES(4,RM(EA)) );								} /* RES  4,(XY+o)	  */
+OP(xycb,a7) { _A = RES(4, RM(EA) ); WM( EA,_A );					} /* RES  4,A=(XY+o)  */
+
+OP(xycb,a8) { _B = RES(5, RM(EA) ); WM( EA,_B );					} /* RES  5,B=(XY+o)  */
+OP(xycb,a9) { _C = RES(5, RM(EA) ); WM( EA,_C );					} /* RES  5,C=(XY+o)  */
+OP(xycb,aa) { _D = RES(5, RM(EA) ); WM( EA,_D );					} /* RES  5,D=(XY+o)  */
+OP(xycb,ab) { _E = RES(5, RM(EA) ); WM( EA,_E );					} /* RES  5,E=(XY+o)  */
+OP(xycb,ac) { _H = RES(5, RM(EA) ); WM( EA,_H );					} /* RES  5,H=(XY+o)  */
+OP(xycb,ad) { _L = RES(5, RM(EA) ); WM( EA,_L );					} /* RES  5,L=(XY+o)  */
+OP(xycb,ae) { WM( EA, RES(5,RM(EA)) );								} /* RES  5,(XY+o)	  */
+OP(xycb,af) { _A = RES(5, RM(EA) ); WM( EA,_A );					} /* RES  5,A=(XY+o)  */
+
+OP(xycb,b0) { _B = RES(6, RM(EA) ); WM( EA,_B );					} /* RES  6,B=(XY+o)  */
+OP(xycb,b1) { _C = RES(6, RM(EA) ); WM( EA,_C );					} /* RES  6,C=(XY+o)  */
+OP(xycb,b2) { _D = RES(6, RM(EA) ); WM( EA,_D );					} /* RES  6,D=(XY+o)  */
+OP(xycb,b3) { _E = RES(6, RM(EA) ); WM( EA,_E );					} /* RES  6,E=(XY+o)  */
+OP(xycb,b4) { _H = RES(6, RM(EA) ); WM( EA,_H );					} /* RES  6,H=(XY+o)  */
+OP(xycb,b5) { _L = RES(6, RM(EA) ); WM( EA,_L );					} /* RES  6,L=(XY+o)  */
+OP(xycb,b6) { WM( EA, RES(6,RM(EA)) );								} /* RES  6,(XY+o)	  */
+OP(xycb,b7) { _A = RES(6, RM(EA) ); WM( EA,_A );					} /* RES  6,A=(XY+o)  */
+
+OP(xycb,b8) { _B = RES(7, RM(EA) ); WM( EA,_B );					} /* RES  7,B=(XY+o)  */
+OP(xycb,b9) { _C = RES(7, RM(EA) ); WM( EA,_C );					} /* RES  7,C=(XY+o)  */
+OP(xycb,ba) { _D = RES(7, RM(EA) ); WM( EA,_D );					} /* RES  7,D=(XY+o)  */
+OP(xycb,bb) { _E = RES(7, RM(EA) ); WM( EA,_E );					} /* RES  7,E=(XY+o)  */
+OP(xycb,bc) { _H = RES(7, RM(EA) ); WM( EA,_H );					} /* RES  7,H=(XY+o)  */
+OP(xycb,bd) { _L = RES(7, RM(EA) ); WM( EA,_L );					} /* RES  7,L=(XY+o)  */
+OP(xycb,be) { WM( EA, RES(7,RM(EA)) );								} /* RES  7,(XY+o)	  */
+OP(xycb,bf) { _A = RES(7, RM(EA) ); WM( EA,_A );					} /* RES  7,A=(XY+o)  */
+
+OP(xycb,c0) { _B = SET(0, RM(EA) ); WM( EA,_B );					} /* SET  0,B=(XY+o)  */
+OP(xycb,c1) { _C = SET(0, RM(EA) ); WM( EA,_C );					} /* SET  0,C=(XY+o)  */
+OP(xycb,c2) { _D = SET(0, RM(EA) ); WM( EA,_D );					} /* SET  0,D=(XY+o)  */
+OP(xycb,c3) { _E = SET(0, RM(EA) ); WM( EA,_E );					} /* SET  0,E=(XY+o)  */
+OP(xycb,c4) { _H = SET(0, RM(EA) ); WM( EA,_H );					} /* SET  0,H=(XY+o)  */
+OP(xycb,c5) { _L = SET(0, RM(EA) ); WM( EA,_L );					} /* SET  0,L=(XY+o)  */
+OP(xycb,c6) { WM( EA, SET(0,RM(EA)) );								} /* SET  0,(XY+o)	  */
+OP(xycb,c7) { _A = SET(0, RM(EA) ); WM( EA,_A );					} /* SET  0,A=(XY+o)  */
+
+OP(xycb,c8) { _B = SET(1, RM(EA) ); WM( EA,_B );					} /* SET  1,B=(XY+o)  */
+OP(xycb,c9) { _C = SET(1, RM(EA) ); WM( EA,_C );					} /* SET  1,C=(XY+o)  */
+OP(xycb,ca) { _D = SET(1, RM(EA) ); WM( EA,_D );					} /* SET  1,D=(XY+o)  */
+OP(xycb,cb) { _E = SET(1, RM(EA) ); WM( EA,_E );					} /* SET  1,E=(XY+o)  */
+OP(xycb,cc) { _H = SET(1, RM(EA) ); WM( EA,_H );					} /* SET  1,H=(XY+o)  */
+OP(xycb,cd) { _L = SET(1, RM(EA) ); WM( EA,_L );					} /* SET  1,L=(XY+o)  */
+OP(xycb,ce) { WM( EA, SET(1,RM(EA)) );								} /* SET  1,(XY+o)	  */
+OP(xycb,cf) { _A = SET(1, RM(EA) ); WM( EA,_A );					} /* SET  1,A=(XY+o)  */
+
+OP(xycb,d0) { _B = SET(2, RM(EA) ); WM( EA,_B );					} /* SET  2,B=(XY+o)  */
+OP(xycb,d1) { _C = SET(2, RM(EA) ); WM( EA,_C );					} /* SET  2,C=(XY+o)  */
+OP(xycb,d2) { _D = SET(2, RM(EA) ); WM( EA,_D );					} /* SET  2,D=(XY+o)  */
+OP(xycb,d3) { _E = SET(2, RM(EA) ); WM( EA,_E );					} /* SET  2,E=(XY+o)  */
+OP(xycb,d4) { _H = SET(2, RM(EA) ); WM( EA,_H );					} /* SET  2,H=(XY+o)  */
+OP(xycb,d5) { _L = SET(2, RM(EA) ); WM( EA,_L );					} /* SET  2,L=(XY+o)  */
+OP(xycb,d6) { WM( EA, SET(2,RM(EA)) );								} /* SET  2,(XY+o)	  */
+OP(xycb,d7) { _A = SET(2, RM(EA) ); WM( EA,_A );					} /* SET  2,A=(XY+o)  */
+
+OP(xycb,d8) { _B = SET(3, RM(EA) ); WM( EA,_B );					} /* SET  3,B=(XY+o)  */
+OP(xycb,d9) { _C = SET(3, RM(EA) ); WM( EA,_C );					} /* SET  3,C=(XY+o)  */
+OP(xycb,da) { _D = SET(3, RM(EA) ); WM( EA,_D );					} /* SET  3,D=(XY+o)  */
+OP(xycb,db) { _E = SET(3, RM(EA) ); WM( EA,_E );					} /* SET  3,E=(XY+o)  */
+OP(xycb,dc) { _H = SET(3, RM(EA) ); WM( EA,_H );					} /* SET  3,H=(XY+o)  */
+OP(xycb,dd) { _L = SET(3, RM(EA) ); WM( EA,_L );					} /* SET  3,L=(XY+o)  */
+OP(xycb,de) { WM( EA, SET(3,RM(EA)) );								} /* SET  3,(XY+o)	  */
+OP(xycb,df) { _A = SET(3, RM(EA) ); WM( EA,_A );					} /* SET  3,A=(XY+o)  */
+
+OP(xycb,e0) { _B = SET(4, RM(EA) ); WM( EA,_B );					} /* SET  4,B=(XY+o)  */
+OP(xycb,e1) { _C = SET(4, RM(EA) ); WM( EA,_C );					} /* SET  4,C=(XY+o)  */
+OP(xycb,e2) { _D = SET(4, RM(EA) ); WM( EA,_D );					} /* SET  4,D=(XY+o)  */
+OP(xycb,e3) { _E = SET(4, RM(EA) ); WM( EA,_E );					} /* SET  4,E=(XY+o)  */
+OP(xycb,e4) { _H = SET(4, RM(EA) ); WM( EA,_H );					} /* SET  4,H=(XY+o)  */
+OP(xycb,e5) { _L = SET(4, RM(EA) ); WM( EA,_L );					} /* SET  4,L=(XY+o)  */
+OP(xycb,e6) { WM( EA, SET(4,RM(EA)) );								} /* SET  4,(XY+o)	  */
+OP(xycb,e7) { _A = SET(4, RM(EA) ); WM( EA,_A );					} /* SET  4,A=(XY+o)  */
+
+OP(xycb,e8) { _B = SET(5, RM(EA) ); WM( EA,_B );					} /* SET  5,B=(XY+o)  */
+OP(xycb,e9) { _C = SET(5, RM(EA) ); WM( EA,_C );					} /* SET  5,C=(XY+o)  */
+OP(xycb,ea) { _D = SET(5, RM(EA) ); WM( EA,_D );					} /* SET  5,D=(XY+o)  */
+OP(xycb,eb) { _E = SET(5, RM(EA) ); WM( EA,_E );					} /* SET  5,E=(XY+o)  */
+OP(xycb,ec) { _H = SET(5, RM(EA) ); WM( EA,_H );					} /* SET  5,H=(XY+o)  */
+OP(xycb,ed) { _L = SET(5, RM(EA) ); WM( EA,_L );					} /* SET  5,L=(XY+o)  */
+OP(xycb,ee) { WM( EA, SET(5,RM(EA)) );								} /* SET  5,(XY+o)	  */
+OP(xycb,ef) { _A = SET(5, RM(EA) ); WM( EA,_A );					} /* SET  5,A=(XY+o)  */
+
+OP(xycb,f0) { _B = SET(6, RM(EA) ); WM( EA,_B );					} /* SET  6,B=(XY+o)  */
+OP(xycb,f1) { _C = SET(6, RM(EA) ); WM( EA,_C );					} /* SET  6,C=(XY+o)  */
+OP(xycb,f2) { _D = SET(6, RM(EA) ); WM( EA,_D );					} /* SET  6,D=(XY+o)  */
+OP(xycb,f3) { _E = SET(6, RM(EA) ); WM( EA,_E );					} /* SET  6,E=(XY+o)  */
+OP(xycb,f4) { _H = SET(6, RM(EA) ); WM( EA,_H );					} /* SET  6,H=(XY+o)  */
+OP(xycb,f5) { _L = SET(6, RM(EA) ); WM( EA,_L );					} /* SET  6,L=(XY+o)  */
+OP(xycb,f6) { WM( EA, SET(6,RM(EA)) );								} /* SET  6,(XY+o)	  */
+OP(xycb,f7) { _A = SET(6, RM(EA) ); WM( EA,_A );					} /* SET  6,A=(XY+o)  */
+
+OP(xycb,f8) { _B = SET(7, RM(EA) ); WM( EA,_B );					} /* SET  7,B=(XY+o)  */
+OP(xycb,f9) { _C = SET(7, RM(EA) ); WM( EA,_C );					} /* SET  7,C=(XY+o)  */
+OP(xycb,fa) { _D = SET(7, RM(EA) ); WM( EA,_D );					} /* SET  7,D=(XY+o)  */
+OP(xycb,fb) { _E = SET(7, RM(EA) ); WM( EA,_E );					} /* SET  7,E=(XY+o)  */
+OP(xycb,fc) { _H = SET(7, RM(EA) ); WM( EA,_H );					} /* SET  7,H=(XY+o)  */
+OP(xycb,fd) { _L = SET(7, RM(EA) ); WM( EA,_L );					} /* SET  7,L=(XY+o)  */
+OP(xycb,fe) { WM( EA, SET(7,RM(EA)) );								} /* SET  7,(XY+o)	  */
+OP(xycb,ff) { _A = SET(7, RM(EA) ); WM( EA,_A );					} /* SET  7,A=(XY+o)  */
+
+OP(illegal,1) {
+}
+
+/**********************************************************
+ * IX register related opcodes (DD prefix)
+ **********************************************************/
+OP(dd,00) { illegal_1(); op_00();									} /* DB   DD		  */
+OP(dd,01) { illegal_1(); op_01();									} /* DB   DD		  */
+OP(dd,02) { illegal_1(); op_02();									} /* DB   DD		  */
+OP(dd,03) { illegal_1(); op_03();									} /* DB   DD		  */
+OP(dd,04) { illegal_1(); op_04();									} /* DB   DD		  */
+OP(dd,05) { illegal_1(); op_05();									} /* DB   DD		  */
+OP(dd,06) { illegal_1(); op_06();									} /* DB   DD		  */
+OP(dd,07) { illegal_1(); op_07();									} /* DB   DD		  */
+
+OP(dd,08) { illegal_1(); op_08();									} /* DB   DD		  */
+OP(dd,09) { _R++; ADD16(IX,BC); 									} /* ADD  IX,BC 	  */
+OP(dd,0a) { illegal_1(); op_0a();									} /* DB   DD		  */
+OP(dd,0b) { illegal_1(); op_0b();									} /* DB   DD		  */
+OP(dd,0c) { illegal_1(); op_0c();									} /* DB   DD		  */
+OP(dd,0d) { illegal_1(); op_0d();									} /* DB   DD		  */
+OP(dd,0e) { illegal_1(); op_0e();									} /* DB   DD		  */
+OP(dd,0f) { illegal_1(); op_0f();									} /* DB   DD		  */
+
+OP(dd,10) { illegal_1(); op_10();									} /* DB   DD		  */
+OP(dd,11) { illegal_1(); op_11();									} /* DB   DD		  */
+OP(dd,12) { illegal_1(); op_12();									} /* DB   DD		  */
+OP(dd,13) { illegal_1(); op_13();									} /* DB   DD		  */
+OP(dd,14) { illegal_1(); op_14();									} /* DB   DD		  */
+OP(dd,15) { illegal_1(); op_15();									} /* DB   DD		  */
+OP(dd,16) { illegal_1(); op_16();									} /* DB   DD		  */
+OP(dd,17) { illegal_1(); op_17();									} /* DB   DD		  */
+
+OP(dd,18) { illegal_1(); op_18();									} /* DB   DD		  */
+OP(dd,19) { _R++; ADD16(IX,DE); 									} /* ADD  IX,DE 	  */
+OP(dd,1a) { illegal_1(); op_1a();									} /* DB   DD		  */
+OP(dd,1b) { illegal_1(); op_1b();									} /* DB   DD		  */
+OP(dd,1c) { illegal_1(); op_1c();									} /* DB   DD		  */
+OP(dd,1d) { illegal_1(); op_1d();									} /* DB   DD		  */
+OP(dd,1e) { illegal_1(); op_1e();									} /* DB   DD		  */
+OP(dd,1f) { illegal_1(); op_1f();									} /* DB   DD		  */
+
+OP(dd,20) { illegal_1(); op_20();									} /* DB   DD		  */
+OP(dd,21) { _R++; _IX = ARG16();									} /* LD   IX,w		  */
+OP(dd,22) { _R++; EA = ARG16(); WM16( EA, &Z80.IX );				} /* LD   (w),IX	  */
+OP(dd,23) { _R++; _IX++;											} /* INC  IX		  */
+OP(dd,24) { _R++; _HX = INC(_HX);									} /* INC  HX		  */
+OP(dd,25) { _R++; _HX = DEC(_HX);									} /* DEC  HX		  */
+OP(dd,26) { _R++; _HX = ARG();										} /* LD   HX,n		  */
+OP(dd,27) { illegal_1(); op_27();									} /* DB   DD		  */
+
+OP(dd,28) { illegal_1(); op_28();									} /* DB   DD		  */
+OP(dd,29) { _R++; ADD16(IX,IX); 									} /* ADD  IX,IX 	  */
+OP(dd,2a) { _R++; EA = ARG16(); RM16( EA, &Z80.IX );				} /* LD   IX,(w)	  */
+OP(dd,2b) { _R++; _IX--;											} /* DEC  IX		  */
+OP(dd,2c) { _R++; _LX = INC(_LX);									} /* INC  LX		  */
+OP(dd,2d) { _R++; _LX = DEC(_LX);									} /* DEC  LX		  */
+OP(dd,2e) { _R++; _LX = ARG();										} /* LD   LX,n		  */
+OP(dd,2f) { illegal_1(); op_2f();									} /* DB   DD		  */
+
+OP(dd,30) { illegal_1(); op_30();									} /* DB   DD		  */
+OP(dd,31) { illegal_1(); op_31();									} /* DB   DD		  */
+OP(dd,32) { illegal_1(); op_32();									} /* DB   DD		  */
+OP(dd,33) { illegal_1(); op_33();									} /* DB   DD		  */
+OP(dd,34) { _R++; EAX; WM( EA, INC(RM(EA)) );						} /* INC  (IX+o)	  */
+OP(dd,35) { _R++; EAX; WM( EA, DEC(RM(EA)) );						} /* DEC  (IX+o)	  */
+OP(dd,36) { _R++; EAX; WM( EA, ARG() ); 							} /* LD   (IX+o),n	  */
+OP(dd,37) { illegal_1(); op_37();									} /* DB   DD		  */
+
+OP(dd,38) { illegal_1(); op_38();									} /* DB   DD		  */
+OP(dd,39) { _R++; ADD16(IX,SP); 									} /* ADD  IX,SP 	  */
+OP(dd,3a) { illegal_1(); op_3a();									} /* DB   DD		  */
+OP(dd,3b) { illegal_1(); op_3b();									} /* DB   DD		  */
+OP(dd,3c) { illegal_1(); op_3c();									} /* DB   DD		  */
+OP(dd,3d) { illegal_1(); op_3d();									} /* DB   DD		  */
+OP(dd,3e) { illegal_1(); op_3e();									} /* DB   DD		  */
+OP(dd,3f) { illegal_1(); op_3f();									} /* DB   DD		  */
+
+OP(dd,40) { illegal_1(); op_40();									} /* DB   DD		  */
+OP(dd,41) { illegal_1(); op_41();									} /* DB   DD		  */
+OP(dd,42) { illegal_1(); op_42();									} /* DB   DD		  */
+OP(dd,43) { illegal_1(); op_43();									} /* DB   DD		  */
+OP(dd,44) { _R++; _B = _HX; 										} /* LD   B,HX		  */
+OP(dd,45) { _R++; _B = _LX; 										} /* LD   B,LX		  */
+OP(dd,46) { _R++; EAX; _B = RM(EA); 								} /* LD   B,(IX+o)	  */
+OP(dd,47) { illegal_1(); op_47();									} /* DB   DD		  */
+
+OP(dd,48) { illegal_1(); op_48();									} /* DB   DD		  */
+OP(dd,49) { illegal_1(); op_49();									} /* DB   DD		  */
+OP(dd,4a) { illegal_1(); op_4a();									} /* DB   DD		  */
+OP(dd,4b) { illegal_1(); op_4b();									} /* DB   DD		  */
+OP(dd,4c) { _R++; _C = _HX; 										} /* LD   C,HX		  */
+OP(dd,4d) { _R++; _C = _LX; 										} /* LD   C,LX		  */
+OP(dd,4e) { _R++; EAX; _C = RM(EA); 								} /* LD   C,(IX+o)	  */
+OP(dd,4f) { illegal_1(); op_4f();									} /* DB   DD		  */
+
+OP(dd,50) { illegal_1(); op_50();									} /* DB   DD		  */
+OP(dd,51) { illegal_1(); op_51();									} /* DB   DD		  */
+OP(dd,52) { illegal_1(); op_52();									} /* DB   DD		  */
+OP(dd,53) { illegal_1(); op_53();									} /* DB   DD		  */
+OP(dd,54) { _R++; _D = _HX; 										} /* LD   D,HX		  */
+OP(dd,55) { _R++; _D = _LX; 										} /* LD   D,LX		  */
+OP(dd,56) { _R++; EAX; _D = RM(EA); 								} /* LD   D,(IX+o)	  */
+OP(dd,57) { illegal_1(); op_57();									} /* DB   DD		  */
+
+OP(dd,58) { illegal_1(); op_58();									} /* DB   DD		  */
+OP(dd,59) { illegal_1(); op_59();									} /* DB   DD		  */
+OP(dd,5a) { illegal_1(); op_5a();									} /* DB   DD		  */
+OP(dd,5b) { illegal_1(); op_5b();									} /* DB   DD		  */
+OP(dd,5c) { _R++; _E = _HX; 										} /* LD   E,HX		  */
+OP(dd,5d) { _R++; _E = _LX; 										} /* LD   E,LX		  */
+OP(dd,5e) { _R++; EAX; _E = RM(EA); 								} /* LD   E,(IX+o)	  */
+OP(dd,5f) { illegal_1(); op_5f();									} /* DB   DD		  */
+
+OP(dd,60) { _R++; _HX = _B; 										} /* LD   HX,B		  */
+OP(dd,61) { _R++; _HX = _C; 										} /* LD   HX,C		  */
+OP(dd,62) { _R++; _HX = _D; 										} /* LD   HX,D		  */
+OP(dd,63) { _R++; _HX = _E; 										} /* LD   HX,E		  */
+OP(dd,64) { 														} /* LD   HX,HX 	  */
+OP(dd,65) { _R++; _HX = _LX;										} /* LD   HX,LX 	  */
+OP(dd,66) { _R++; EAX; _H = RM(EA); 								} /* LD   H,(IX+o)	  */
+OP(dd,67) { _R++; _HX = _A; 										} /* LD   HX,A		  */
+
+OP(dd,68) { _R++; _LX = _B; 										} /* LD   LX,B		  */
+OP(dd,69) { _R++; _LX = _C; 										} /* LD   LX,C		  */
+OP(dd,6a) { _R++; _LX = _D; 										} /* LD   LX,D		  */
+OP(dd,6b) { _R++; _LX = _E; 										} /* LD   LX,E		  */
+OP(dd,6c) { _R++; _LX = _HX;										} /* LD   LX,HX 	  */
+OP(dd,6d) { 														} /* LD   LX,LX 	  */
+OP(dd,6e) { _R++; EAX; _L = RM(EA); 								} /* LD   L,(IX+o)	  */
+OP(dd,6f) { _R++; _LX = _A; 										} /* LD   LX,A		  */
+
+OP(dd,70) { _R++; EAX; WM( EA, _B );								} /* LD   (IX+o),B	  */
+OP(dd,71) { _R++; EAX; WM( EA, _C );								} /* LD   (IX+o),C	  */
+OP(dd,72) { _R++; EAX; WM( EA, _D );								} /* LD   (IX+o),D	  */
+OP(dd,73) { _R++; EAX; WM( EA, _E );								} /* LD   (IX+o),E	  */
+OP(dd,74) { _R++; EAX; WM( EA, _H );								} /* LD   (IX+o),H	  */
+OP(dd,75) { _R++; EAX; WM( EA, _L );								} /* LD   (IX+o),L	  */
+OP(dd,76) { illegal_1(); op_76();									}		  /* DB   DD		  */
+OP(dd,77) { _R++; EAX; WM( EA, _A );								} /* LD   (IX+o),A	  */
+
+OP(dd,78) { illegal_1(); op_78();									} /* DB   DD		  */
+OP(dd,79) { illegal_1(); op_79();									} /* DB   DD		  */
+OP(dd,7a) { illegal_1(); op_7a();									} /* DB   DD		  */
+OP(dd,7b) { illegal_1(); op_7b();									} /* DB   DD		  */
+OP(dd,7c) { _R++; _A = _HX; 										} /* LD   A,HX		  */
+OP(dd,7d) { _R++; _A = _LX; 										} /* LD   A,LX		  */
+OP(dd,7e) { _R++; EAX; _A = RM(EA); 								} /* LD   A,(IX+o)	  */
+OP(dd,7f) { illegal_1(); op_7f();									} /* DB   DD		  */
+
+OP(dd,80) { illegal_1(); op_80();									} /* DB   DD		  */
+OP(dd,81) { illegal_1(); op_81();									} /* DB   DD		  */
+OP(dd,82) { illegal_1(); op_82();									} /* DB   DD		  */
+OP(dd,83) { illegal_1(); op_83();									} /* DB   DD		  */
+OP(dd,84) { _R++; ADD(_HX); 										} /* ADD  A,HX		  */
+OP(dd,85) { _R++; ADD(_LX); 										} /* ADD  A,LX		  */
+OP(dd,86) { _R++; EAX; ADD(RM(EA)); 								} /* ADD  A,(IX+o)	  */
+OP(dd,87) { illegal_1(); op_87();									} /* DB   DD		  */
+
+OP(dd,88) { illegal_1(); op_88();									} /* DB   DD		  */
+OP(dd,89) { illegal_1(); op_89();									} /* DB   DD		  */
+OP(dd,8a) { illegal_1(); op_8a();									} /* DB   DD		  */
+OP(dd,8b) { illegal_1(); op_8b();									} /* DB   DD		  */
+OP(dd,8c) { _R++; ADC(_HX); 										} /* ADC  A,HX		  */
+OP(dd,8d) { _R++; ADC(_LX); 										} /* ADC  A,LX		  */
+OP(dd,8e) { _R++; EAX; ADC(RM(EA)); 								} /* ADC  A,(IX+o)	  */
+OP(dd,8f) { illegal_1(); op_8f();									} /* DB   DD		  */
+
+OP(dd,90) { illegal_1(); op_90();									} /* DB   DD		  */
+OP(dd,91) { illegal_1(); op_91();									} /* DB   DD		  */
+OP(dd,92) { illegal_1(); op_92();									} /* DB   DD		  */
+OP(dd,93) { illegal_1(); op_93();									} /* DB   DD		  */
+OP(dd,94) { _R++; SUB(_HX); 										} /* SUB  HX		  */
+OP(dd,95) { _R++; SUB(_LX); 										} /* SUB  LX		  */
+OP(dd,96) { _R++; EAX; SUB(RM(EA)); 								} /* SUB  (IX+o)	  */
+OP(dd,97) { illegal_1(); op_97();									} /* DB   DD		  */
+
+OP(dd,98) { illegal_1(); op_98();									} /* DB   DD		  */
+OP(dd,99) { illegal_1(); op_99();									} /* DB   DD		  */
+OP(dd,9a) { illegal_1(); op_9a();									} /* DB   DD		  */
+OP(dd,9b) { illegal_1(); op_9b();									} /* DB   DD		  */
+OP(dd,9c) { _R++; SBC(_HX); 										} /* SBC  A,HX		  */
+OP(dd,9d) { _R++; SBC(_LX); 										} /* SBC  A,LX		  */
+OP(dd,9e) { _R++; EAX; SBC(RM(EA)); 								} /* SBC  A,(IX+o)	  */
+OP(dd,9f) { illegal_1(); op_9f();									} /* DB   DD		  */
+
+OP(dd,a0) { illegal_1(); op_a0();									} /* DB   DD		  */
+OP(dd,a1) { illegal_1(); op_a1();									} /* DB   DD		  */
+OP(dd,a2) { illegal_1(); op_a2();									} /* DB   DD		  */
+OP(dd,a3) { illegal_1(); op_a3();									} /* DB   DD		  */
+OP(dd,a4) { _R++; AND(_HX); 										} /* AND  HX		  */
+OP(dd,a5) { _R++; AND(_LX); 										} /* AND  LX		  */
+OP(dd,a6) { _R++; EAX; AND(RM(EA)); 								} /* AND  (IX+o)	  */
+OP(dd,a7) { illegal_1(); op_a7();									} /* DB   DD		  */
+
+OP(dd,a8) { illegal_1(); op_a8();									} /* DB   DD		  */
+OP(dd,a9) { illegal_1(); op_a9();									} /* DB   DD		  */
+OP(dd,aa) { illegal_1(); op_aa();									} /* DB   DD		  */
+OP(dd,ab) { illegal_1(); op_ab();									} /* DB   DD		  */
+OP(dd,ac) { _R++; XOR(_HX); 										} /* XOR  HX		  */
+OP(dd,ad) { _R++; XOR(_LX); 										} /* XOR  LX		  */
+OP(dd,ae) { _R++; EAX; XOR(RM(EA)); 								} /* XOR  (IX+o)	  */
+OP(dd,af) { illegal_1(); op_af();									} /* DB   DD		  */
+
+OP(dd,b0) { illegal_1(); op_b0();									} /* DB   DD		  */
+OP(dd,b1) { illegal_1(); op_b1();									} /* DB   DD		  */
+OP(dd,b2) { illegal_1(); op_b2();									} /* DB   DD		  */
+OP(dd,b3) { illegal_1(); op_b3();									} /* DB   DD		  */
+OP(dd,b4) { _R++; OR(_HX);											} /* OR   HX		  */
+OP(dd,b5) { _R++; OR(_LX);											} /* OR   LX		  */
+OP(dd,b6) { _R++; EAX; OR(RM(EA));									} /* OR   (IX+o)	  */
+OP(dd,b7) { illegal_1(); op_b7();									} /* DB   DD		  */
+
+OP(dd,b8) { illegal_1(); op_b8();									} /* DB   DD		  */
+OP(dd,b9) { illegal_1(); op_b9();									} /* DB   DD		  */
+OP(dd,ba) { illegal_1(); op_ba();									} /* DB   DD		  */
+OP(dd,bb) { illegal_1(); op_bb();									} /* DB   DD		  */
+OP(dd,bc) { _R++; CP(_HX);											} /* CP   HX		  */
+OP(dd,bd) { _R++; CP(_LX);											} /* CP   LX		  */
+OP(dd,be) { _R++; EAX; CP(RM(EA));									} /* CP   (IX+o)	  */
+OP(dd,bf) { illegal_1(); op_bf();									} /* DB   DD		  */
+
+OP(dd,c0) { illegal_1(); op_c0();									} /* DB   DD		  */
+OP(dd,c1) { illegal_1(); op_c1();									} /* DB   DD		  */
+OP(dd,c2) { illegal_1(); op_c2();									} /* DB   DD		  */
+OP(dd,c3) { illegal_1(); op_c3();									} /* DB   DD		  */
+OP(dd,c4) { illegal_1(); op_c4();									} /* DB   DD		  */
+OP(dd,c5) { illegal_1(); op_c5();									} /* DB   DD		  */
+OP(dd,c6) { illegal_1(); op_c6();									} /* DB   DD		  */
+OP(dd,c7) { illegal_1(); op_c7();									}		  /* DB   DD		  */
+
+OP(dd,c8) { illegal_1(); op_c8();									} /* DB   DD		  */
+OP(dd,c9) { illegal_1(); op_c9();									} /* DB   DD		  */
+OP(dd,ca) { illegal_1(); op_ca();									} /* DB   DD		  */
+OP(dd,cb) { _R++; EAX; EXEC(xycb,ARG());							} /* **   DD CB xx	  */
+OP(dd,cc) { illegal_1(); op_cc();									} /* DB   DD		  */
+OP(dd,cd) { illegal_1(); op_cd();									} /* DB   DD		  */
+OP(dd,ce) { illegal_1(); op_ce();									} /* DB   DD		  */
+OP(dd,cf) { illegal_1(); op_cf();									} /* DB   DD		  */
+
+OP(dd,d0) { illegal_1(); op_d0();									} /* DB   DD		  */
+OP(dd,d1) { illegal_1(); op_d1();									} /* DB   DD		  */
+OP(dd,d2) { illegal_1(); op_d2();									} /* DB   DD		  */
+OP(dd,d3) { illegal_1(); op_d3();									} /* DB   DD		  */
+OP(dd,d4) { illegal_1(); op_d4();									} /* DB   DD		  */
+OP(dd,d5) { illegal_1(); op_d5();									} /* DB   DD		  */
+OP(dd,d6) { illegal_1(); op_d6();									} /* DB   DD		  */
+OP(dd,d7) { illegal_1(); op_d7();									} /* DB   DD		  */
+
+OP(dd,d8) { illegal_1(); op_d8();									} /* DB   DD		  */
+OP(dd,d9) { illegal_1(); op_d9();									} /* DB   DD		  */
+OP(dd,da) { illegal_1(); op_da();									} /* DB   DD		  */
+OP(dd,db) { illegal_1(); op_db();									} /* DB   DD		  */
+OP(dd,dc) { illegal_1(); op_dc();									} /* DB   DD		  */
+OP(dd,dd) { illegal_1(); op_dd();									} /* DB   DD		  */
+OP(dd,de) { illegal_1(); op_de();									} /* DB   DD		  */
+OP(dd,df) { illegal_1(); op_df();									} /* DB   DD		  */
+
+OP(dd,e0) { illegal_1(); op_e0();									} /* DB   DD		  */
+OP(dd,e1) { _R++; POP(IX);											} /* POP  IX		  */
+OP(dd,e2) { illegal_1(); op_e2();									} /* DB   DD		  */
+OP(dd,e3) { _R++; EXSP(IX); 										} /* EX   (SP),IX	  */
+OP(dd,e4) { illegal_1(); op_e4();									} /* DB   DD		  */
+OP(dd,e5) { _R++; PUSH( IX );										} /* PUSH IX		  */
+OP(dd,e6) { illegal_1(); op_e6();									} /* DB   DD		  */
+OP(dd,e7) { illegal_1(); op_e7();									} /* DB   DD		  */
+
+OP(dd,e8) { illegal_1(); op_e8();									} /* DB   DD		  */
+OP(dd,e9) { _R++; _PC = _IX;                                        } /* JP   (IX)        */
+OP(dd,ea) { illegal_1(); op_ea();									} /* DB   DD		  */
+OP(dd,eb) { illegal_1(); op_eb();									} /* DB   DD		  */
+OP(dd,ec) { illegal_1(); op_ec();									} /* DB   DD		  */
+OP(dd,ed) { illegal_1(); op_ed();									} /* DB   DD		  */
+OP(dd,ee) { illegal_1(); op_ee();									} /* DB   DD		  */
+OP(dd,ef) { illegal_1(); op_ef();									} /* DB   DD		  */
+
+OP(dd,f0) { illegal_1(); op_f0();									} /* DB   DD		  */
+OP(dd,f1) { illegal_1(); op_f1();									} /* DB   DD		  */
+OP(dd,f2) { illegal_1(); op_f2();									} /* DB   DD		  */
+OP(dd,f3) { illegal_1(); op_f3();									} /* DB   DD		  */
+OP(dd,f4) { illegal_1(); op_f4();									} /* DB   DD		  */
+OP(dd,f5) { illegal_1(); op_f5();									} /* DB   DD		  */
+OP(dd,f6) { illegal_1(); op_f6();									} /* DB   DD		  */
+OP(dd,f7) { illegal_1(); op_f7();									} /* DB   DD		  */
+
+OP(dd,f8) { illegal_1(); op_f8();									} /* DB   DD		  */
+OP(dd,f9) { _R++; _SP = _IX;										} /* LD   SP,IX 	  */
+OP(dd,fa) { illegal_1(); op_fa();									} /* DB   DD		  */
+OP(dd,fb) { illegal_1(); op_fb();									} /* DB   DD		  */
+OP(dd,fc) { illegal_1(); op_fc();									} /* DB   DD		  */
+OP(dd,fd) { illegal_1(); op_fd();									} /* DB   DD		  */
+OP(dd,fe) { illegal_1(); op_fe();									} /* DB   DD		  */
+OP(dd,ff) { illegal_1(); op_ff();									} /* DB   DD		  */
+
+/**********************************************************
+ * IY register related opcodes (FD prefix)
+ **********************************************************/
+OP(fd,00) { illegal_1(); op_00();									} /* DB   FD		  */
+OP(fd,01) { illegal_1(); op_01();									} /* DB   FD		  */
+OP(fd,02) { illegal_1(); op_02();									} /* DB   FD		  */
+OP(fd,03) { illegal_1(); op_03();									} /* DB   FD		  */
+OP(fd,04) { illegal_1(); op_04();									} /* DB   FD		  */
+OP(fd,05) { illegal_1(); op_05();									} /* DB   FD		  */
+OP(fd,06) { illegal_1(); op_06();									} /* DB   FD		  */
+OP(fd,07) { illegal_1(); op_07();									} /* DB   FD		  */
+
+OP(fd,08) { illegal_1(); op_08();									} /* DB   FD		  */
+OP(fd,09) { _R++; ADD16(IY,BC); 									} /* ADD  IY,BC 	  */
+OP(fd,0a) { illegal_1(); op_0a();									} /* DB   FD		  */
+OP(fd,0b) { illegal_1(); op_0b();									} /* DB   FD		  */
+OP(fd,0c) { illegal_1(); op_0c();									} /* DB   FD		  */
+OP(fd,0d) { illegal_1(); op_0d();									} /* DB   FD		  */
+OP(fd,0e) { illegal_1(); op_0e();									} /* DB   FD		  */
+OP(fd,0f) { illegal_1(); op_0f();									} /* DB   FD		  */
+
+OP(fd,10) { illegal_1(); op_10();									} /* DB   FD		  */
+OP(fd,11) { illegal_1(); op_11();									} /* DB   FD		  */
+OP(fd,12) { illegal_1(); op_12();									} /* DB   FD		  */
+OP(fd,13) { illegal_1(); op_13();									} /* DB   FD		  */
+OP(fd,14) { illegal_1(); op_14();									} /* DB   FD		  */
+OP(fd,15) { illegal_1(); op_15();									} /* DB   FD		  */
+OP(fd,16) { illegal_1(); op_16();									} /* DB   FD		  */
+OP(fd,17) { illegal_1(); op_17();									} /* DB   FD		  */
+
+OP(fd,18) { illegal_1(); op_18();									} /* DB   FD		  */
+OP(fd,19) { _R++; ADD16(IY,DE); 									} /* ADD  IY,DE 	  */
+OP(fd,1a) { illegal_1(); op_1a();									} /* DB   FD		  */
+OP(fd,1b) { illegal_1(); op_1b();									} /* DB   FD		  */
+OP(fd,1c) { illegal_1(); op_1c();									} /* DB   FD		  */
+OP(fd,1d) { illegal_1(); op_1d();									} /* DB   FD		  */
+OP(fd,1e) { illegal_1(); op_1e();									} /* DB   FD		  */
+OP(fd,1f) { illegal_1(); op_1f();									} /* DB   FD		  */
+
+OP(fd,20) { illegal_1(); op_20();									} /* DB   FD		  */
+OP(fd,21) { _R++; _IY = ARG16();									} /* LD   IY,w		  */
+OP(fd,22) { _R++; EA = ARG16(); WM16( EA, &Z80.IY );				} /* LD   (w),IY	  */
+OP(fd,23) { _R++; _IY++;											} /* INC  IY		  */
+OP(fd,24) { _R++; _HY = INC(_HY);									} /* INC  HY		  */
+OP(fd,25) { _R++; _HY = DEC(_HY);									} /* DEC  HY		  */
+OP(fd,26) { _R++; _HY = ARG();										} /* LD   HY,n		  */
+OP(fd,27) { illegal_1(); op_27();									} /* DB   FD		  */
+
+OP(fd,28) { illegal_1(); op_28();									} /* DB   FD		  */
+OP(fd,29) { _R++; ADD16(IY,IY); 									} /* ADD  IY,IY 	  */
+OP(fd,2a) { _R++; EA = ARG16(); RM16( EA, &Z80.IY );				} /* LD   IY,(w)	  */
+OP(fd,2b) { _R++; _IY--;											} /* DEC  IY		  */
+OP(fd,2c) { _R++; _LY = INC(_LY);									} /* INC  LY		  */
+OP(fd,2d) { _R++; _LY = DEC(_LY);									} /* DEC  LY		  */
+OP(fd,2e) { _R++; _LY = ARG();										} /* LD   LY,n		  */
+OP(fd,2f) { illegal_1(); op_2f();									} /* DB   FD		  */
+
+OP(fd,30) { illegal_1(); op_30();									} /* DB   FD		  */
+OP(fd,31) { illegal_1(); op_31();									} /* DB   FD		  */
+OP(fd,32) { illegal_1(); op_32();									} /* DB   FD		  */
+OP(fd,33) { illegal_1(); op_33();									} /* DB   FD		  */
+OP(fd,34) { _R++; EAY; WM( EA, INC(RM(EA)) );						} /* INC  (IY+o)	  */
+OP(fd,35) { _R++; EAY; WM( EA, DEC(RM(EA)) );						} /* DEC  (IY+o)	  */
+OP(fd,36) { _R++; EAY; WM( EA, ARG() ); 							} /* LD   (IY+o),n	  */
+OP(fd,37) { illegal_1(); op_37();									} /* DB   FD		  */
+
+OP(fd,38) { illegal_1(); op_38();									} /* DB   FD		  */
+OP(fd,39) { _R++; ADD16(IY,SP); 									} /* ADD  IY,SP 	  */
+OP(fd,3a) { illegal_1(); op_3a();									} /* DB   FD		  */
+OP(fd,3b) { illegal_1(); op_3b();									} /* DB   FD		  */
+OP(fd,3c) { illegal_1(); op_3c();									} /* DB   FD		  */
+OP(fd,3d) { illegal_1(); op_3d();									} /* DB   FD		  */
+OP(fd,3e) { illegal_1(); op_3e();									} /* DB   FD		  */
+OP(fd,3f) { illegal_1(); op_3f();									} /* DB   FD		  */
+
+OP(fd,40) { illegal_1(); op_40();									} /* DB   FD		  */
+OP(fd,41) { illegal_1(); op_41();									} /* DB   FD		  */
+OP(fd,42) { illegal_1(); op_42();									} /* DB   FD		  */
+OP(fd,43) { illegal_1(); op_43();									} /* DB   FD		  */
+OP(fd,44) { _R++; _B = _HY; 										} /* LD   B,HY		  */
+OP(fd,45) { _R++; _B = _LY; 										} /* LD   B,LY		  */
+OP(fd,46) { _R++; EAY; _B = RM(EA); 								} /* LD   B,(IY+o)	  */
+OP(fd,47) { illegal_1(); op_47();									} /* DB   FD		  */
+
+OP(fd,48) { illegal_1(); op_48();									} /* DB   FD		  */
+OP(fd,49) { illegal_1(); op_49();									} /* DB   FD		  */
+OP(fd,4a) { illegal_1(); op_4a();									} /* DB   FD		  */
+OP(fd,4b) { illegal_1(); op_4b();									} /* DB   FD		  */
+OP(fd,4c) { _R++; _C = _HY; 										} /* LD   C,HY		  */
+OP(fd,4d) { _R++; _C = _LY; 										} /* LD   C,LY		  */
+OP(fd,4e) { _R++; EAY; _C = RM(EA); 								} /* LD   C,(IY+o)	  */
+OP(fd,4f) { illegal_1(); op_4f();									} /* DB   FD		  */
+
+OP(fd,50) { illegal_1(); op_50();									} /* DB   FD		  */
+OP(fd,51) { illegal_1(); op_51();									} /* DB   FD		  */
+OP(fd,52) { illegal_1(); op_52();									} /* DB   FD		  */
+OP(fd,53) { illegal_1(); op_53();									} /* DB   FD		  */
+OP(fd,54) { _R++; _D = _HY; 										} /* LD   D,HY		  */
+OP(fd,55) { _R++; _D = _LY; 										} /* LD   D,LY		  */
+OP(fd,56) { _R++; EAY; _D = RM(EA); 								} /* LD   D,(IY+o)	  */
+OP(fd,57) { illegal_1(); op_57();									} /* DB   FD		  */
+
+OP(fd,58) { illegal_1(); op_58();									} /* DB   FD		  */
+OP(fd,59) { illegal_1(); op_59();									} /* DB   FD		  */
+OP(fd,5a) { illegal_1(); op_5a();									} /* DB   FD		  */
+OP(fd,5b) { illegal_1(); op_5b();									} /* DB   FD		  */
+OP(fd,5c) { _R++; _E = _HY; 										} /* LD   E,HY		  */
+OP(fd,5d) { _R++; _E = _LY; 										} /* LD   E,LY		  */
+OP(fd,5e) { _R++; EAY; _E = RM(EA); 								} /* LD   E,(IY+o)	  */
+OP(fd,5f) { illegal_1(); op_5f();									} /* DB   FD		  */
+
+OP(fd,60) { _R++; _HY = _B; 										} /* LD   HY,B		  */
+OP(fd,61) { _R++; _HY = _C; 										} /* LD   HY,C		  */
+OP(fd,62) { _R++; _HY = _D; 										} /* LD   HY,D		  */
+OP(fd,63) { _R++; _HY = _E; 										} /* LD   HY,E		  */
+OP(fd,64) { _R++;													} /* LD   HY,HY 	  */
+OP(fd,65) { _R++; _HY = _LY;										} /* LD   HY,LY 	  */
+OP(fd,66) { _R++; EAY; _H = RM(EA); 								} /* LD   H,(IY+o)	  */
+OP(fd,67) { _R++; _HY = _A; 										} /* LD   HY,A		  */
+
+OP(fd,68) { _R++; _LY = _B; 										} /* LD   LY,B		  */
+OP(fd,69) { _R++; _LY = _C; 										} /* LD   LY,C		  */
+OP(fd,6a) { _R++; _LY = _D; 										} /* LD   LY,D		  */
+OP(fd,6b) { _R++; _LY = _E; 										} /* LD   LY,E		  */
+OP(fd,6c) { _R++; _LY = _HY;										} /* LD   LY,HY 	  */
+OP(fd,6d) { _R++;													} /* LD   LY,LY 	  */
+OP(fd,6e) { _R++; EAY; _L = RM(EA); 								} /* LD   L,(IY+o)	  */
+OP(fd,6f) { _R++; _LY = _A; 										} /* LD   LY,A		  */
+
+OP(fd,70) { _R++; EAY; WM( EA, _B );								} /* LD   (IY+o),B	  */
+OP(fd,71) { _R++; EAY; WM( EA, _C );								} /* LD   (IY+o),C	  */
+OP(fd,72) { _R++; EAY; WM( EA, _D );								} /* LD   (IY+o),D	  */
+OP(fd,73) { _R++; EAY; WM( EA, _E );								} /* LD   (IY+o),E	  */
+OP(fd,74) { _R++; EAY; WM( EA, _H );								} /* LD   (IY+o),H	  */
+OP(fd,75) { _R++; EAY; WM( EA, _L );								} /* LD   (IY+o),L	  */
+OP(fd,76) { illegal_1(); op_76();									}		  /* DB   FD		  */
+OP(fd,77) { _R++; EAY; WM( EA, _A );								} /* LD   (IY+o),A	  */
+
+OP(fd,78) { illegal_1(); op_78();									} /* DB   FD		  */
+OP(fd,79) { illegal_1(); op_79();									} /* DB   FD		  */
+OP(fd,7a) { illegal_1(); op_7a();									} /* DB   FD		  */
+OP(fd,7b) { illegal_1(); op_7b();									} /* DB   FD		  */
+OP(fd,7c) { _R++; _A = _HY; 										} /* LD   A,HY		  */
+OP(fd,7d) { _R++; _A = _LY; 										} /* LD   A,LY		  */
+OP(fd,7e) { _R++; EAY; _A = RM(EA); 								} /* LD   A,(IY+o)	  */
+OP(fd,7f) { illegal_1(); op_7f();									} /* DB   FD		  */
+
+OP(fd,80) { illegal_1(); op_80();									} /* DB   FD		  */
+OP(fd,81) { illegal_1(); op_81();									} /* DB   FD		  */
+OP(fd,82) { illegal_1(); op_82();									} /* DB   FD		  */
+OP(fd,83) { illegal_1(); op_83();									} /* DB   FD		  */
+OP(fd,84) { _R++; ADD(_HY); 										} /* ADD  A,HY		  */
+OP(fd,85) { _R++; ADD(_LY); 										} /* ADD  A,LY		  */
+OP(fd,86) { _R++; EAY; ADD(RM(EA)); 								} /* ADD  A,(IY+o)	  */
+OP(fd,87) { illegal_1(); op_87();									} /* DB   FD		  */
+
+OP(fd,88) { illegal_1(); op_88();									} /* DB   FD		  */
+OP(fd,89) { illegal_1(); op_89();									} /* DB   FD		  */
+OP(fd,8a) { illegal_1(); op_8a();									} /* DB   FD		  */
+OP(fd,8b) { illegal_1(); op_8b();									} /* DB   FD		  */
+OP(fd,8c) { _R++; ADC(_HY); 										} /* ADC  A,HY		  */
+OP(fd,8d) { _R++; ADC(_LY); 										} /* ADC  A,LY		  */
+OP(fd,8e) { _R++; EAY; ADC(RM(EA)); 								} /* ADC  A,(IY+o)	  */
+OP(fd,8f) { illegal_1(); op_8f();									} /* DB   FD		  */
+
+OP(fd,90) { illegal_1(); op_90();									} /* DB   FD		  */
+OP(fd,91) { illegal_1(); op_91();									} /* DB   FD		  */
+OP(fd,92) { illegal_1(); op_92();									} /* DB   FD		  */
+OP(fd,93) { illegal_1(); op_93();									} /* DB   FD		  */
+OP(fd,94) { _R++; SUB(_HY); 										} /* SUB  HY		  */
+OP(fd,95) { _R++; SUB(_LY); 										} /* SUB  LY		  */
+OP(fd,96) { _R++; EAY; SUB(RM(EA)); 								} /* SUB  (IY+o)	  */
+OP(fd,97) { illegal_1(); op_97();									} /* DB   FD		  */
+
+OP(fd,98) { illegal_1(); op_98();									} /* DB   FD		  */
+OP(fd,99) { illegal_1(); op_99();									} /* DB   FD		  */
+OP(fd,9a) { illegal_1(); op_9a();									} /* DB   FD		  */
+OP(fd,9b) { illegal_1(); op_9b();									} /* DB   FD		  */
+OP(fd,9c) { _R++; SBC(_HY); 										} /* SBC  A,HY		  */
+OP(fd,9d) { _R++; SBC(_LY); 										} /* SBC  A,LY		  */
+OP(fd,9e) { _R++; EAY; SBC(RM(EA)); 								} /* SBC  A,(IY+o)	  */
+OP(fd,9f) { illegal_1(); op_9f();									} /* DB   FD		  */
+
+OP(fd,a0) { illegal_1(); op_a0();									} /* DB   FD		  */
+OP(fd,a1) { illegal_1(); op_a1();									} /* DB   FD		  */
+OP(fd,a2) { illegal_1(); op_a2();									} /* DB   FD		  */
+OP(fd,a3) { illegal_1(); op_a3();									} /* DB   FD		  */
+OP(fd,a4) { _R++; AND(_HY); 										} /* AND  HY		  */
+OP(fd,a5) { _R++; AND(_LY); 										} /* AND  LY		  */
+OP(fd,a6) { _R++; EAY; AND(RM(EA)); 								} /* AND  (IY+o)	  */
+OP(fd,a7) { illegal_1(); op_a7();									} /* DB   FD		  */
+
+OP(fd,a8) { illegal_1(); op_a8();									} /* DB   FD		  */
+OP(fd,a9) { illegal_1(); op_a9();									} /* DB   FD		  */
+OP(fd,aa) { illegal_1(); op_aa();									} /* DB   FD		  */
+OP(fd,ab) { illegal_1(); op_ab();									} /* DB   FD		  */
+OP(fd,ac) { _R++; XOR(_HY); 										} /* XOR  HY		  */
+OP(fd,ad) { _R++; XOR(_LY); 										} /* XOR  LY		  */
+OP(fd,ae) { _R++; EAY; XOR(RM(EA)); 								} /* XOR  (IY+o)	  */
+OP(fd,af) { illegal_1(); op_af();									} /* DB   FD		  */
+
+OP(fd,b0) { illegal_1(); op_b0();									} /* DB   FD		  */
+OP(fd,b1) { illegal_1(); op_b1();									} /* DB   FD		  */
+OP(fd,b2) { illegal_1(); op_b2();									} /* DB   FD		  */
+OP(fd,b3) { illegal_1(); op_b3();									} /* DB   FD		  */
+OP(fd,b4) { _R++; OR(_HY);											} /* OR   HY		  */
+OP(fd,b5) { _R++; OR(_LY);											} /* OR   LY		  */
+OP(fd,b6) { _R++; EAY; OR(RM(EA));									} /* OR   (IY+o)	  */
+OP(fd,b7) { illegal_1(); op_b7();									} /* DB   FD		  */
+
+OP(fd,b8) { illegal_1(); op_b8();									} /* DB   FD		  */
+OP(fd,b9) { illegal_1(); op_b9();									} /* DB   FD		  */
+OP(fd,ba) { illegal_1(); op_ba();									} /* DB   FD		  */
+OP(fd,bb) { illegal_1(); op_bb();									} /* DB   FD		  */
+OP(fd,bc) { _R++; CP(_HY);											} /* CP   HY		  */
+OP(fd,bd) { _R++; CP(_LY);											} /* CP   LY		  */
+OP(fd,be) { _R++; EAY; CP(RM(EA));									} /* CP   (IY+o)	  */
+OP(fd,bf) { illegal_1(); op_bf();									} /* DB   FD		  */
+
+OP(fd,c0) { illegal_1(); op_c0();									} /* DB   FD		  */
+OP(fd,c1) { illegal_1(); op_c1();									} /* DB   FD		  */
+OP(fd,c2) { illegal_1(); op_c2();									} /* DB   FD		  */
+OP(fd,c3) { illegal_1(); op_c3();									} /* DB   FD		  */
+OP(fd,c4) { illegal_1(); op_c4();									} /* DB   FD		  */
+OP(fd,c5) { illegal_1(); op_c5();									} /* DB   FD		  */
+OP(fd,c6) { illegal_1(); op_c6();									} /* DB   FD		  */
+OP(fd,c7) { illegal_1(); op_c7();									} /* DB   FD		  */
+
+OP(fd,c8) { illegal_1(); op_c8();									} /* DB   FD		  */
+OP(fd,c9) { illegal_1(); op_c9();									} /* DB   FD		  */
+OP(fd,ca) { illegal_1(); op_ca();									} /* DB   FD		  */
+OP(fd,cb) { _R++; EAY; EXEC(xycb,ARG());							} /* **   FD CB xx	  */
+OP(fd,cc) { illegal_1(); op_cc();									} /* DB   FD		  */
+OP(fd,cd) { illegal_1(); op_cd();									} /* DB   FD		  */
+OP(fd,ce) { illegal_1(); op_ce();									} /* DB   FD		  */
+OP(fd,cf) { illegal_1(); op_cf();									} /* DB   FD		  */
+
+OP(fd,d0) { illegal_1(); op_d0();									} /* DB   FD		  */
+OP(fd,d1) { illegal_1(); op_d1();									} /* DB   FD		  */
+OP(fd,d2) { illegal_1(); op_d2();									} /* DB   FD		  */
+OP(fd,d3) { illegal_1(); op_d3();									} /* DB   FD		  */
+OP(fd,d4) { illegal_1(); op_d4();									} /* DB   FD		  */
+OP(fd,d5) { illegal_1(); op_d5();									} /* DB   FD		  */
+OP(fd,d6) { illegal_1(); op_d6();									} /* DB   FD		  */
+OP(fd,d7) { illegal_1(); op_d7();									} /* DB   FD		  */
+
+OP(fd,d8) { illegal_1(); op_d8();									} /* DB   FD		  */
+OP(fd,d9) { illegal_1(); op_d9();									} /* DB   FD		  */
+OP(fd,da) { illegal_1(); op_da();									} /* DB   FD		  */
+OP(fd,db) { illegal_1(); op_db();									} /* DB   FD		  */
+OP(fd,dc) { illegal_1(); op_dc();									} /* DB   FD		  */
+OP(fd,dd) { illegal_1(); op_dd();									} /* DB   FD		  */
+OP(fd,de) { illegal_1(); op_de();									} /* DB   FD		  */
+OP(fd,df) { illegal_1(); op_df();									} /* DB   FD		  */
+
+OP(fd,e0) { illegal_1(); op_e0();									} /* DB   FD		  */
+OP(fd,e1) { _R++; POP(IY);											} /* POP  IY		  */
+OP(fd,e2) { illegal_1(); op_e2();									} /* DB   FD		  */
+OP(fd,e3) { _R++; EXSP(IY); 										} /* EX   (SP),IY	  */
+OP(fd,e4) { illegal_1(); op_e4();									} /* DB   FD		  */
+OP(fd,e5) { _R++; PUSH( IY );										} /* PUSH IY		  */
+OP(fd,e6) { illegal_1(); op_e6();									} /* DB   FD		  */
+OP(fd,e7) { illegal_1(); op_e7();									} /* DB   FD		  */
+
+OP(fd,e8) { illegal_1(); op_e8();									} /* DB   FD		  */
+OP(fd,e9) { _R++; _PC = _IY;                                        } /* JP   (IY)        */
+OP(fd,ea) { illegal_1(); op_ea();									} /* DB   FD		  */
+OP(fd,eb) { illegal_1(); op_eb();									} /* DB   FD		  */
+OP(fd,ec) { illegal_1(); op_ec();									} /* DB   FD		  */
+OP(fd,ed) { illegal_1(); op_ed();									} /* DB   FD		  */
+OP(fd,ee) { illegal_1(); op_ee();									} /* DB   FD		  */
+OP(fd,ef) { illegal_1(); op_ef();									} /* DB   FD		  */
+
+OP(fd,f0) { illegal_1(); op_f0();									} /* DB   FD		  */
+OP(fd,f1) { illegal_1(); op_f1();									} /* DB   FD		  */
+OP(fd,f2) { illegal_1(); op_f2();									} /* DB   FD		  */
+OP(fd,f3) { illegal_1(); op_f3();									} /* DB   FD		  */
+OP(fd,f4) { illegal_1(); op_f4();									} /* DB   FD		  */
+OP(fd,f5) { illegal_1(); op_f5();									} /* DB   FD		  */
+OP(fd,f6) { illegal_1(); op_f6();									} /* DB   FD		  */
+OP(fd,f7) { illegal_1(); op_f7();									} /* DB   FD		  */
+
+OP(fd,f8) { illegal_1(); op_f8();									} /* DB   FD		  */
+OP(fd,f9) { _R++; _SP = _IY;										} /* LD   SP,IY 	  */
+OP(fd,fa) { illegal_1(); op_fa();									} /* DB   FD		  */
+OP(fd,fb) { illegal_1(); op_fb();									} /* DB   FD		  */
+OP(fd,fc) { illegal_1(); op_fc();									} /* DB   FD		  */
+OP(fd,fd) { illegal_1(); op_fd();									} /* DB   FD		  */
+OP(fd,fe) { illegal_1(); op_fe();									} /* DB   FD		  */
+OP(fd,ff) { illegal_1(); op_ff();									} /* DB   FD		  */
+
+OP(illegal,2)
+{
+}
+
+/**********************************************************
+ * special opcodes (ED prefix)
+ **********************************************************/
+OP(ed,00) { illegal_2();											} /* DB   ED		  */
+OP(ed,01) { illegal_2();											} /* DB   ED		  */
+OP(ed,02) { illegal_2();											} /* DB   ED		  */
+OP(ed,03) { illegal_2();											} /* DB   ED		  */
+OP(ed,04) { illegal_2();											} /* DB   ED		  */
+OP(ed,05) { illegal_2();											} /* DB   ED		  */
+OP(ed,06) { illegal_2();											} /* DB   ED		  */
+OP(ed,07) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,08) { illegal_2();											} /* DB   ED		  */
+OP(ed,09) { illegal_2();											} /* DB   ED		  */
+OP(ed,0a) { illegal_2();											} /* DB   ED		  */
+OP(ed,0b) { illegal_2();											} /* DB   ED		  */
+OP(ed,0c) { illegal_2();											} /* DB   ED		  */
+OP(ed,0d) { illegal_2();											} /* DB   ED		  */
+OP(ed,0e) { illegal_2();											} /* DB   ED		  */
+OP(ed,0f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,10) { illegal_2();											} /* DB   ED		  */
+OP(ed,11) { illegal_2();											} /* DB   ED		  */
+OP(ed,12) { illegal_2();											} /* DB   ED		  */
+OP(ed,13) { illegal_2();											} /* DB   ED		  */
+OP(ed,14) { illegal_2();											} /* DB   ED		  */
+OP(ed,15) { illegal_2();											} /* DB   ED		  */
+OP(ed,16) { illegal_2();											} /* DB   ED		  */
+OP(ed,17) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,18) { illegal_2();											} /* DB   ED		  */
+OP(ed,19) { illegal_2();											} /* DB   ED		  */
+OP(ed,1a) { illegal_2();											} /* DB   ED		  */
+OP(ed,1b) { illegal_2();											} /* DB   ED		  */
+OP(ed,1c) { illegal_2();											} /* DB   ED		  */
+OP(ed,1d) { illegal_2();											} /* DB   ED		  */
+OP(ed,1e) { illegal_2();											} /* DB   ED		  */
+OP(ed,1f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,20) { illegal_2();											} /* DB   ED		  */
+OP(ed,21) { illegal_2();											} /* DB   ED		  */
+OP(ed,22) { illegal_2();											} /* DB   ED		  */
+OP(ed,23) { illegal_2();											} /* DB   ED		  */
+OP(ed,24) { illegal_2();											} /* DB   ED		  */
+OP(ed,25) { illegal_2();											} /* DB   ED		  */
+OP(ed,26) { illegal_2();											} /* DB   ED		  */
+OP(ed,27) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,28) { illegal_2();											} /* DB   ED		  */
+OP(ed,29) { illegal_2();											} /* DB   ED		  */
+OP(ed,2a) { illegal_2();											} /* DB   ED		  */
+OP(ed,2b) { illegal_2();											} /* DB   ED		  */
+OP(ed,2c) { illegal_2();											} /* DB   ED		  */
+OP(ed,2d) { illegal_2();											} /* DB   ED		  */
+OP(ed,2e) { illegal_2();											} /* DB   ED		  */
+OP(ed,2f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,30) { illegal_2();											} /* DB   ED		  */
+OP(ed,31) { illegal_2();											} /* DB   ED		  */
+OP(ed,32) { illegal_2();											} /* DB   ED		  */
+OP(ed,33) { illegal_2();											} /* DB   ED		  */
+OP(ed,34) { illegal_2();											} /* DB   ED		  */
+OP(ed,35) { illegal_2();											} /* DB   ED		  */
+OP(ed,36) { illegal_2();											} /* DB   ED		  */
+OP(ed,37) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,38) { illegal_2();											} /* DB   ED		  */
+OP(ed,39) { illegal_2();											} /* DB   ED		  */
+OP(ed,3a) { illegal_2();											} /* DB   ED		  */
+OP(ed,3b) { illegal_2();											} /* DB   ED		  */
+OP(ed,3c) { illegal_2();											} /* DB   ED		  */
+OP(ed,3d) { illegal_2();											} /* DB   ED		  */
+OP(ed,3e) { illegal_2();											} /* DB   ED		  */
+OP(ed,3f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,40) { _B = IN(_BC); _F = (_F & CF) | SZP[_B]; 				} /* IN   B,(C) 	  */
+OP(ed,41) { OUT(_BC,_B);											} /* OUT  (C),B 	  */
+OP(ed,42) { SBC16( BC );											} /* SBC  HL,BC 	  */
+OP(ed,43) { EA = ARG16(); WM16( EA, &Z80.BC );						} /* LD   (w),BC	  */
+OP(ed,44) { NEG;													} /* NEG			  */
+OP(ed,45) { RETN;													} /* RETN;			  */
+OP(ed,46) { _IM = 0;												} /* IM   0 		  */
+OP(ed,47) { LD_I_A; 												} /* LD   I,A		  */
+
+OP(ed,48) { _C = IN(_BC); _F = (_F & CF) | SZP[_C]; 				} /* IN   C,(C) 	  */
+OP(ed,49) { OUT(_BC,_C);											} /* OUT  (C),C 	  */
+OP(ed,4a) { ADC16( BC );											} /* ADC  HL,BC 	  */
+OP(ed,4b) { EA = ARG16(); RM16( EA, &Z80.BC );						} /* LD   BC,(w)	  */
+OP(ed,4c) { NEG;													} /* NEG			  */
+OP(ed,4d) { RETI;													} /* RETI			  */
+OP(ed,4e) { _IM = 0;												} /* IM   0 		  */
+OP(ed,4f) { LD_R_A; 												} /* LD   R,A		  */
+
+OP(ed,50) { _D = IN(_BC); _F = (_F & CF) | SZP[_D]; 				} /* IN   D,(C) 	  */
+OP(ed,51) { OUT(_BC,_D);											} /* OUT  (C),D 	  */
+OP(ed,52) { SBC16( DE );											} /* SBC  HL,DE 	  */
+OP(ed,53) { EA = ARG16(); WM16( EA, &Z80.DE );						} /* LD   (w),DE	  */
+OP(ed,54) { NEG;													} /* NEG			  */
+OP(ed,55) { RETN;													} /* RETN;			  */
+OP(ed,56) { _IM = 1;												} /* IM   1 		  */
+OP(ed,57) { LD_A_I; 												} /* LD   A,I		  */
+
+OP(ed,58) { _E = IN(_BC); _F = (_F & CF) | SZP[_E]; 				} /* IN   E,(C) 	  */
+OP(ed,59) { OUT(_BC,_E);											} /* OUT  (C),E 	  */
+OP(ed,5a) { ADC16( DE );											} /* ADC  HL,DE 	  */
+OP(ed,5b) { EA = ARG16(); RM16( EA, &Z80.DE );						} /* LD   DE,(w)	  */
+OP(ed,5c) { NEG;													} /* NEG			  */
+OP(ed,5d) { RETI;													} /* RETI			  */
+OP(ed,5e) { _IM = 2;												} /* IM   2 		  */
+OP(ed,5f) { LD_A_R; 												} /* LD   A,R		  */
+
+OP(ed,60) { _H = IN(_BC); _F = (_F & CF) | SZP[_H]; 				} /* IN   H,(C) 	  */
+OP(ed,61) { OUT(_BC,_H);											} /* OUT  (C),H 	  */
+OP(ed,62) { SBC16( HL );											} /* SBC  HL,HL 	  */
+OP(ed,63) { EA = ARG16(); WM16( EA, &Z80.HL );						} /* LD   (w),HL	  */
+OP(ed,64) { NEG;													} /* NEG			  */
+OP(ed,65) { RETN;													} /* RETN;			  */
+OP(ed,66) { _IM = 0;												} /* IM   0 		  */
+OP(ed,67) { RRD;													} /* RRD  (HL)		  */
+
+OP(ed,68) { _L = IN(_BC); _F = (_F & CF) | SZP[_L]; 				} /* IN   L,(C) 	  */
+OP(ed,69) { OUT(_BC,_L);											} /* OUT  (C),L 	  */
+OP(ed,6a) { ADC16( HL );											} /* ADC  HL,HL 	  */
+OP(ed,6b) { EA = ARG16(); RM16( EA, &Z80.HL );						} /* LD   HL,(w)	  */
+OP(ed,6c) { NEG;													} /* NEG			  */
+OP(ed,6d) { RETI;													} /* RETI			  */
+OP(ed,6e) { _IM = 0;												} /* IM   0 		  */
+OP(ed,6f) { RLD;													} /* RLD  (HL)		  */
+
+OP(ed,70) { UINT8 res = IN(_BC); _F = (_F & CF) | SZP[res]; 		} /* IN   0,(C) 	  */
+OP(ed,71) { OUT(_BC,0); 											} /* OUT  (C),0 	  */
+OP(ed,72) { SBC16( SP );											} /* SBC  HL,SP 	  */
+OP(ed,73) { EA = ARG16(); WM16( EA, &Z80.SP );						} /* LD   (w),SP	  */
+OP(ed,74) { NEG;													} /* NEG			  */
+OP(ed,75) { RETN;													} /* RETN;			  */
+OP(ed,76) { _IM = 1;												} /* IM   1 		  */
+OP(ed,77) { illegal_2();											} /* DB   ED,77 	  */
+
+OP(ed,78) { _A = IN(_BC); _F = (_F & CF) | SZP[_A]; 				} /* IN   E,(C) 	  */
+OP(ed,79) { OUT(_BC,_A);											} /* OUT  (C),E 	  */
+OP(ed,7a) { ADC16( SP );											} /* ADC  HL,SP 	  */
+OP(ed,7b) { EA = ARG16(); RM16( EA, &Z80.SP );						} /* LD   SP,(w)	  */
+OP(ed,7c) { NEG;													} /* NEG			  */
+OP(ed,7d) { RETI;													} /* RETI			  */
+OP(ed,7e) { _IM = 2;												} /* IM   2 		  */
+OP(ed,7f) { illegal_2();											} /* DB   ED,7F 	  */
+
+OP(ed,80) { illegal_2();											} /* DB   ED		  */
+OP(ed,81) { illegal_2();											} /* DB   ED		  */
+OP(ed,82) { illegal_2();											} /* DB   ED		  */
+OP(ed,83) { illegal_2();											} /* DB   ED		  */
+OP(ed,84) { illegal_2();											} /* DB   ED		  */
+OP(ed,85) { illegal_2();											} /* DB   ED		  */
+OP(ed,86) { illegal_2();											} /* DB   ED		  */
+OP(ed,87) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,88) { illegal_2();											} /* DB   ED		  */
+OP(ed,89) { illegal_2();											} /* DB   ED		  */
+OP(ed,8a) { illegal_2();											} /* DB   ED		  */
+OP(ed,8b) { illegal_2();											} /* DB   ED		  */
+OP(ed,8c) { illegal_2();											} /* DB   ED		  */
+OP(ed,8d) { illegal_2();											} /* DB   ED		  */
+OP(ed,8e) { illegal_2();											} /* DB   ED		  */
+OP(ed,8f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,90) { illegal_2();											} /* DB   ED		  */
+OP(ed,91) { illegal_2();											} /* DB   ED		  */
+OP(ed,92) { illegal_2();											} /* DB   ED		  */
+OP(ed,93) { illegal_2();											} /* DB   ED		  */
+OP(ed,94) { illegal_2();											} /* DB   ED		  */
+OP(ed,95) { illegal_2();											} /* DB   ED		  */
+OP(ed,96) { illegal_2();											} /* DB   ED		  */
+OP(ed,97) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,98) { illegal_2();											} /* DB   ED		  */
+OP(ed,99) { illegal_2();											} /* DB   ED		  */
+OP(ed,9a) { illegal_2();											} /* DB   ED		  */
+OP(ed,9b) { illegal_2();											} /* DB   ED		  */
+OP(ed,9c) { illegal_2();											} /* DB   ED		  */
+OP(ed,9d) { illegal_2();											} /* DB   ED		  */
+OP(ed,9e) { illegal_2();											} /* DB   ED		  */
+OP(ed,9f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,a0) { LDI;													} /* LDI			  */
+OP(ed,a1) { CPI;													} /* CPI			  */
+OP(ed,a2) { INI;													} /* INI			  */
+OP(ed,a3) { OUTI;													} /* OUTI			  */
+OP(ed,a4) { illegal_2();											} /* DB   ED		  */
+OP(ed,a5) { illegal_2();											} /* DB   ED		  */
+OP(ed,a6) { illegal_2();											} /* DB   ED		  */
+OP(ed,a7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,a8) { LDD;													} /* LDD			  */
+OP(ed,a9) { CPD;													} /* CPD			  */
+OP(ed,aa) { IND;													} /* IND			  */
+OP(ed,ab) { OUTD;													} /* OUTD			  */
+OP(ed,ac) { illegal_2();											} /* DB   ED		  */
+OP(ed,ad) { illegal_2();											} /* DB   ED		  */
+OP(ed,ae) { illegal_2();											} /* DB   ED		  */
+OP(ed,af) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,b0) { LDIR;													} /* LDIR			  */
+OP(ed,b1) { CPIR;													} /* CPIR			  */
+OP(ed,b2) { INIR;													} /* INIR			  */
+OP(ed,b3) { OTIR;													} /* OTIR			  */
+OP(ed,b4) { illegal_2();											} /* DB   ED		  */
+OP(ed,b5) { illegal_2();											} /* DB   ED		  */
+OP(ed,b6) { illegal_2();											} /* DB   ED		  */
+OP(ed,b7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,b8) { LDDR;													} /* LDDR			  */
+OP(ed,b9) { CPDR;													} /* CPDR			  */
+OP(ed,ba) { INDR;													} /* INDR			  */
+OP(ed,bb) { OTDR;													} /* OTDR			  */
+OP(ed,bc) { illegal_2();											} /* DB   ED		  */
+OP(ed,bd) { illegal_2();											} /* DB   ED		  */
+OP(ed,be) { illegal_2();											} /* DB   ED		  */
+OP(ed,bf) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,c0) { illegal_2();											} /* DB   ED		  */
+OP(ed,c1) { illegal_2();											} /* DB   ED		  */
+OP(ed,c2) { illegal_2();											} /* DB   ED		  */
+OP(ed,c3) { illegal_2();											} /* DB   ED		  */
+OP(ed,c4) { illegal_2();											} /* DB   ED		  */
+OP(ed,c5) { illegal_2();											} /* DB   ED		  */
+OP(ed,c6) { illegal_2();											} /* DB   ED		  */
+OP(ed,c7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,c8) { illegal_2();											} /* DB   ED		  */
+OP(ed,c9) { illegal_2();											} /* DB   ED		  */
+OP(ed,ca) { illegal_2();											} /* DB   ED		  */
+OP(ed,cb) { illegal_2();											} /* DB   ED		  */
+OP(ed,cc) { illegal_2();											} /* DB   ED		  */
+OP(ed,cd) { illegal_2();											} /* DB   ED		  */
+OP(ed,ce) { illegal_2();											} /* DB   ED		  */
+OP(ed,cf) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,d0) { illegal_2();											} /* DB   ED		  */
+OP(ed,d1) { illegal_2();											} /* DB   ED		  */
+OP(ed,d2) { illegal_2();											} /* DB   ED		  */
+OP(ed,d3) { illegal_2();											} /* DB   ED		  */
+OP(ed,d4) { illegal_2();											} /* DB   ED		  */
+OP(ed,d5) { illegal_2();											} /* DB   ED		  */
+OP(ed,d6) { illegal_2();											} /* DB   ED		  */
+OP(ed,d7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,d8) { illegal_2();											} /* DB   ED		  */
+OP(ed,d9) { illegal_2();											} /* DB   ED		  */
+OP(ed,da) { illegal_2();											} /* DB   ED		  */
+OP(ed,db) { illegal_2();											} /* DB   ED		  */
+OP(ed,dc) { illegal_2();											} /* DB   ED		  */
+OP(ed,dd) { illegal_2();											} /* DB   ED		  */
+OP(ed,de) { illegal_2();											} /* DB   ED		  */
+OP(ed,df) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,e0) { illegal_2();											} /* DB   ED		  */
+OP(ed,e1) { illegal_2();											} /* DB   ED		  */
+OP(ed,e2) { illegal_2();											} /* DB   ED		  */
+OP(ed,e3) { illegal_2();											} /* DB   ED		  */
+OP(ed,e4) { illegal_2();											} /* DB   ED		  */
+OP(ed,e5) { illegal_2();											} /* DB   ED		  */
+OP(ed,e6) { illegal_2();											} /* DB   ED		  */
+OP(ed,e7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,e8) { illegal_2();											} /* DB   ED		  */
+OP(ed,e9) { illegal_2();											} /* DB   ED		  */
+OP(ed,ea) { illegal_2();											} /* DB   ED		  */
+OP(ed,eb) { illegal_2();											} /* DB   ED		  */
+OP(ed,ec) { illegal_2();											} /* DB   ED		  */
+OP(ed,ed) { illegal_2();											} /* DB   ED		  */
+OP(ed,ee) { illegal_2();											} /* DB   ED		  */
+OP(ed,ef) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,f0) { illegal_2();											} /* DB   ED		  */
+OP(ed,f1) { illegal_2();											} /* DB   ED		  */
+OP(ed,f2) { illegal_2();											} /* DB   ED		  */
+OP(ed,f3) { illegal_2();											} /* DB   ED		  */
+OP(ed,f4) { illegal_2();											} /* DB   ED		  */
+OP(ed,f5) { illegal_2();											} /* DB   ED		  */
+OP(ed,f6) { illegal_2();											} /* DB   ED		  */
+OP(ed,f7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,f8) { illegal_2();											} /* DB   ED		  */
+OP(ed,f9) { illegal_2();											} /* DB   ED		  */
+OP(ed,fa) { illegal_2();											} /* DB   ED		  */
+OP(ed,fb) { illegal_2();											} /* DB   ED		  */
+OP(ed,fc) { illegal_2();											} /* DB   ED		  */
+OP(ed,fd) { illegal_2();											} /* DB   ED		  */
+OP(ed,fe) { illegal_2();											} /* DB   ED		  */
+OP(ed,ff) { illegal_2();											} /* DB   ED		  */
+
+#if TIME_LOOP_HACKS
+
+#define CHECK_BC_LOOP												\
+if( _BC > 1 && _PCD < 0xfffc ) {									\
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x78 && op2==0xb1) || (op1==0x79 && op2==0xb0) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			int cnt =												\
+				cc[Z80_TABLE_op][0x78] +							\
+				cc[Z80_TABLE_op][0xb1] +							\
+				cc[Z80_TABLE_op][0x20] +							\
+				cc[Z80_TABLE_ex][0x20]; 							\
+			while( _BC > 0 && z80_ICount > cnt )					\
+			{														\
+				BURNODD( cnt, 4, cnt ); 							\
+				_BC--;												\
+			}														\
+		}															\
+		else														\
+		if( op3 == 0xc2 )											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				int cnt =											\
+					cc[Z80_TABLE_op][0x78] +						\
+					cc[Z80_TABLE_op][0xb1] +						\
+					cc[Z80_TABLE_op][0xc2] +						\
+					cc[Z80_TABLE_ex][0xc2]; 						\
+				while( _BC > 0 && z80_ICount > cnt )				\
+				{													\
+					BURNODD( cnt, 4, cnt ); 						\
+					_BC--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#define CHECK_DE_LOOP												\
+if( _DE > 1 && _PCD < 0xfffc ) {									\
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x7a && op2==0xb3) || (op1==0x7b && op2==0xb2) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			int cnt =												\
+				cc[Z80_TABLE_op][0x7a] +							\
+				cc[Z80_TABLE_op][0xb3] +							\
+				cc[Z80_TABLE_op][0x20] +							\
+				cc[Z80_TABLE_ex][0x20]; 							\
+			while( _DE > 0 && z80_ICount > cnt )					\
+			{														\
+				BURNODD( cnt, 4, cnt ); 							\
+				_DE--;												\
+			}														\
+		}															\
+		else														\
+		if( op3==0xc2 ) 											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				int cnt =											\
+					cc[Z80_TABLE_op][0x7a] +						\
+					cc[Z80_TABLE_op][0xb3] +						\
+					cc[Z80_TABLE_op][0xc2] +						\
+					cc[Z80_TABLE_ex][0xc2]; 						\
+				while( _DE > 0 && z80_ICount > cnt )				\
+				{													\
+					BURNODD( cnt, 4, cnt ); 						\
+					_DE--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#define CHECK_HL_LOOP												\
+if( _HL > 1 && _PCD < 0xfffc ) {									\
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x7c && op2==0xb5) || (op1==0x7d && op2==0xb4) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			int cnt =												\
+				cc[Z80_TABLE_op][0x7c] +							\
+				cc[Z80_TABLE_op][0xb5] +							\
+				cc[Z80_TABLE_op][0x20] +							\
+				cc[Z80_TABLE_ex][0x20]; 							\
+			while( _HL > 0 && z80_ICount > cnt )					\
+			{														\
+				BURNODD( cnt, 4, cnt ); 							\
+				_HL--;												\
+			}														\
+		}															\
+		else														\
+		if( op3==0xc2 ) 											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				int cnt =											\
+					cc[Z80_TABLE_op][0x7c] +						\
+					cc[Z80_TABLE_op][0xb5] +						\
+					cc[Z80_TABLE_op][0xc2] +						\
+					cc[Z80_TABLE_ex][0xc2]; 						\
+				while( _HL > 0 && z80_ICount > cnt )				\
+				{													\
+					BURNODD( cnt, 4, cnt ); 						\
+					_HL--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#else
+
+#define CHECK_BC_LOOP
+#define CHECK_DE_LOOP
+#define CHECK_HL_LOOP
+
+#endif
+
+/**********************************************************
+ * main opcodes
+ **********************************************************/
+OP(op,00) { 														} /* NOP			  */
+OP(op,01) { _BC = ARG16();											} /* LD   BC,w		  */
+OP(op,02) { WM( _BC, _A );											} /* LD   (BC),A	  */
+OP(op,03) { _BC++;													} /* INC  BC		  */
+OP(op,04) { _B = INC(_B);											} /* INC  B 		  */
+OP(op,05) { _B = DEC(_B);											} /* DEC  B 		  */
+OP(op,06) { _B = ARG(); 											} /* LD   B,n		  */
+OP(op,07) { RLCA;													} /* RLCA			  */
+
+OP(op,08) { EX_AF;													} /* EX   AF,AF'      */
+OP(op,09) { ADD16(HL,BC);											} /* ADD  HL,BC 	  */
+OP(op,0a) { _A = RM(_BC);											} /* LD   A,(BC)	  */
+OP(op,0b) { _BC--; CHECK_BC_LOOP;									} /* DEC  BC		  */
+OP(op,0c) { _C = INC(_C);											} /* INC  C 		  */
+OP(op,0d) { _C = DEC(_C);											} /* DEC  C 		  */
+OP(op,0e) { _C = ARG(); 											} /* LD   C,n		  */
+OP(op,0f) { RRCA;													} /* RRCA			  */
+
+OP(op,10) { _B--; JR_COND( _B, 0x10 );								} /* DJNZ o 		  */
+OP(op,11) { _DE = ARG16();											} /* LD   DE,w		  */
+OP(op,12) { WM( _DE, _A );											} /* LD   (DE),A	  */
+OP(op,13) { _DE++;													} /* INC  DE		  */
+OP(op,14) { _D = INC(_D);											} /* INC  D 		  */
+OP(op,15) { _D = DEC(_D);											} /* DEC  D 		  */
+OP(op,16) { _D = ARG(); 											} /* LD   D,n		  */
+OP(op,17) { RLA;													} /* RLA			  */
+
+OP(op,18) { JR();													} /* JR   o 		  */
+OP(op,19) { ADD16(HL,DE);											} /* ADD  HL,DE 	  */
+OP(op,1a) { _A = RM(_DE);											} /* LD   A,(DE)	  */
+OP(op,1b) { _DE--; CHECK_DE_LOOP;									} /* DEC  DE		  */
+OP(op,1c) { _E = INC(_E);											} /* INC  E 		  */
+OP(op,1d) { _E = DEC(_E);											} /* DEC  E 		  */
+OP(op,1e) { _E = ARG(); 											} /* LD   E,n		  */
+OP(op,1f) { RRA;													} /* RRA			  */
+
+OP(op,20) { JR_COND( !(_F & ZF), 0x20 );							} /* JR   NZ,o		  */
+OP(op,21) { _HL = ARG16();											} /* LD   HL,w		  */
+OP(op,22) { EA = ARG16(); WM16( EA, &Z80.HL );						} /* LD   (w),HL	  */
+OP(op,23) { _HL++;													} /* INC  HL		  */
+OP(op,24) { _H = INC(_H);											} /* INC  H 		  */
+OP(op,25) { _H = DEC(_H);											} /* DEC  H 		  */
+OP(op,26) { _H = ARG(); 											} /* LD   H,n		  */
+OP(op,27) { DAA;													} /* DAA			  */
+
+OP(op,28) { JR_COND( _F & ZF, 0x28 );								} /* JR   Z,o		  */
+OP(op,29) { ADD16(HL,HL);											} /* ADD  HL,HL 	  */
+OP(op,2a) { EA = ARG16(); RM16( EA, &Z80.HL );						} /* LD   HL,(w)	  */
+OP(op,2b) { _HL--; CHECK_HL_LOOP;									} /* DEC  HL		  */
+OP(op,2c) { _L = INC(_L);											} /* INC  L 		  */
+OP(op,2d) { _L = DEC(_L);											} /* DEC  L 		  */
+OP(op,2e) { _L = ARG(); 											} /* LD   L,n		  */
+OP(op,2f) { _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); } /* CPL			  */
+
+OP(op,30) { JR_COND( !(_F & CF), 0x30 );							} /* JR   NC,o		  */
+OP(op,31) { _SP = ARG16();											} /* LD   SP,w		  */
+OP(op,32) { EA = ARG16(); WM( EA, _A ); 							} /* LD   (w),A 	  */
+OP(op,33) { _SP++;													} /* INC  SP		  */
+OP(op,34) { WM( _HL, INC(RM(_HL)) );								} /* INC  (HL)		  */
+OP(op,35) { WM( _HL, DEC(RM(_HL)) );								} /* DEC  (HL)		  */
+OP(op,36) { WM( _HL, ARG() );										} /* LD   (HL),n	  */
+OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF));			} /* SCF			  */
+
+OP(op,38) { JR_COND( _F & CF, 0x38 );								} /* JR   C,o		  */
+OP(op,39) { ADD16(HL,SP);											} /* ADD  HL,SP 	  */
+OP(op,3a) { EA = ARG16(); _A = RM( EA );							} /* LD   A,(w) 	  */
+OP(op,3b) { _SP--;													} /* DEC  SP		  */
+OP(op,3c) { _A = INC(_A);											} /* INC  A 		  */
+OP(op,3d) { _A = DEC(_A);											} /* DEC  A 		  */
+OP(op,3e) { _A = ARG(); 											} /* LD   A,n		  */
+OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; } /* CCF			  */
+//OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; 		  } /* CCF				*/
+
+OP(op,40) { 														} /* LD   B,B		  */
+OP(op,41) { _B = _C;												} /* LD   B,C		  */
+OP(op,42) { _B = _D;												} /* LD   B,D		  */
+OP(op,43) { _B = _E;												} /* LD   B,E		  */
+OP(op,44) { _B = _H;												} /* LD   B,H		  */
+OP(op,45) { _B = _L;												} /* LD   B,L		  */
+OP(op,46) { _B = RM(_HL);											} /* LD   B,(HL)	  */
+OP(op,47) { _B = _A;												} /* LD   B,A		  */
+
+OP(op,48) { _C = _B;												} /* LD   C,B		  */
+OP(op,49) { 														} /* LD   C,C		  */
+OP(op,4a) { _C = _D;												} /* LD   C,D		  */
+OP(op,4b) { _C = _E;												} /* LD   C,E		  */
+OP(op,4c) { _C = _H;												} /* LD   C,H		  */
+OP(op,4d) { _C = _L;												} /* LD   C,L		  */
+OP(op,4e) { _C = RM(_HL);											} /* LD   C,(HL)	  */
+OP(op,4f) { _C = _A;												} /* LD   C,A		  */
+
+OP(op,50) { _D = _B;												} /* LD   D,B		  */
+OP(op,51) { _D = _C;												} /* LD   D,C		  */
+OP(op,52) { 														} /* LD   D,D		  */
+OP(op,53) { _D = _E;												} /* LD   D,E		  */
+OP(op,54) { _D = _H;												} /* LD   D,H		  */
+OP(op,55) { _D = _L;												} /* LD   D,L		  */
+OP(op,56) { _D = RM(_HL);											} /* LD   D,(HL)	  */
+OP(op,57) { _D = _A;												} /* LD   D,A		  */
+
+OP(op,58) { _E = _B;												} /* LD   E,B		  */
+OP(op,59) { _E = _C;												} /* LD   E,C		  */
+OP(op,5a) { _E = _D;												} /* LD   E,D		  */
+OP(op,5b) { 														} /* LD   E,E		  */
+OP(op,5c) { _E = _H;												} /* LD   E,H		  */
+OP(op,5d) { _E = _L;												} /* LD   E,L		  */
+OP(op,5e) { _E = RM(_HL);											} /* LD   E,(HL)	  */
+OP(op,5f) { _E = _A;												} /* LD   E,A		  */
+
+OP(op,60) { _H = _B;												} /* LD   H,B		  */
+OP(op,61) { _H = _C;												} /* LD   H,C		  */
+OP(op,62) { _H = _D;												} /* LD   H,D		  */
+OP(op,63) { _H = _E;												} /* LD   H,E		  */
+OP(op,64) { 														} /* LD   H,H		  */
+OP(op,65) { _H = _L;												} /* LD   H,L		  */
+OP(op,66) { _H = RM(_HL);											} /* LD   H,(HL)	  */
+OP(op,67) { _H = _A;												} /* LD   H,A		  */
+
+OP(op,68) { _L = _B;												} /* LD   L,B		  */
+OP(op,69) { _L = _C;												} /* LD   L,C		  */
+OP(op,6a) { _L = _D;												} /* LD   L,D		  */
+OP(op,6b) { _L = _E;												} /* LD   L,E		  */
+OP(op,6c) { _L = _H;												} /* LD   L,H		  */
+OP(op,6d) { 														} /* LD   L,L		  */
+OP(op,6e) { _L = RM(_HL);											} /* LD   L,(HL)	  */
+OP(op,6f) { _L = _A;												} /* LD   L,A		  */
+
+OP(op,70) { WM( _HL, _B );											} /* LD   (HL),B	  */
+OP(op,71) { WM( _HL, _C );											} /* LD   (HL),C	  */
+OP(op,72) { WM( _HL, _D );											} /* LD   (HL),D	  */
+OP(op,73) { WM( _HL, _E );											} /* LD   (HL),E	  */
+OP(op,74) { WM( _HL, _H );											} /* LD   (HL),H	  */
+OP(op,75) { WM( _HL, _L );											} /* LD   (HL),L	  */
+OP(op,76) { ENTER_HALT; 											} /* HALT			  */
+OP(op,77) { WM( _HL, _A );											} /* LD   (HL),A	  */
+
+OP(op,78) { _A = _B;												} /* LD   A,B		  */
+OP(op,79) { _A = _C;												} /* LD   A,C		  */
+OP(op,7a) { _A = _D;												} /* LD   A,D		  */
+OP(op,7b) { _A = _E;												} /* LD   A,E		  */
+OP(op,7c) { _A = _H;												} /* LD   A,H		  */
+OP(op,7d) { _A = _L;												} /* LD   A,L		  */
+OP(op,7e) { _A = RM(_HL);											} /* LD   A,(HL)	  */
+OP(op,7f) { 														} /* LD   A,A		  */
+
+OP(op,80) { ADD(_B);												} /* ADD  A,B		  */
+OP(op,81) { ADD(_C);												} /* ADD  A,C		  */
+OP(op,82) { ADD(_D);												} /* ADD  A,D		  */
+OP(op,83) { ADD(_E);												} /* ADD  A,E		  */
+OP(op,84) { ADD(_H);												} /* ADD  A,H		  */
+OP(op,85) { ADD(_L);												} /* ADD  A,L		  */
+OP(op,86) { ADD(RM(_HL));											} /* ADD  A,(HL)	  */
+OP(op,87) { ADD(_A);												} /* ADD  A,A		  */
+
+OP(op,88) { ADC(_B);												} /* ADC  A,B		  */
+OP(op,89) { ADC(_C);												} /* ADC  A,C		  */
+OP(op,8a) { ADC(_D);												} /* ADC  A,D		  */
+OP(op,8b) { ADC(_E);												} /* ADC  A,E		  */
+OP(op,8c) { ADC(_H);												} /* ADC  A,H		  */
+OP(op,8d) { ADC(_L);												} /* ADC  A,L		  */
+OP(op,8e) { ADC(RM(_HL));											} /* ADC  A,(HL)	  */
+OP(op,8f) { ADC(_A);												} /* ADC  A,A		  */
+
+OP(op,90) { SUB(_B);												} /* SUB  B 		  */
+OP(op,91) { SUB(_C);												} /* SUB  C 		  */
+OP(op,92) { SUB(_D);												} /* SUB  D 		  */
+OP(op,93) { SUB(_E);												} /* SUB  E 		  */
+OP(op,94) { SUB(_H);												} /* SUB  H 		  */
+OP(op,95) { SUB(_L);												} /* SUB  L 		  */
+OP(op,96) { SUB(RM(_HL));											} /* SUB  (HL)		  */
+OP(op,97) { SUB(_A);												} /* SUB  A 		  */
+
+OP(op,98) { SBC(_B);												} /* SBC  A,B		  */
+OP(op,99) { SBC(_C);												} /* SBC  A,C		  */
+OP(op,9a) { SBC(_D);												} /* SBC  A,D		  */
+OP(op,9b) { SBC(_E);												} /* SBC  A,E		  */
+OP(op,9c) { SBC(_H);												} /* SBC  A,H		  */
+OP(op,9d) { SBC(_L);												} /* SBC  A,L		  */
+OP(op,9e) { SBC(RM(_HL));											} /* SBC  A,(HL)	  */
+OP(op,9f) { SBC(_A);												} /* SBC  A,A		  */
+
+OP(op,a0) { AND(_B);												} /* AND  B 		  */
+OP(op,a1) { AND(_C);												} /* AND  C 		  */
+OP(op,a2) { AND(_D);												} /* AND  D 		  */
+OP(op,a3) { AND(_E);												} /* AND  E 		  */
+OP(op,a4) { AND(_H);												} /* AND  H 		  */
+OP(op,a5) { AND(_L);												} /* AND  L 		  */
+OP(op,a6) { AND(RM(_HL));											} /* AND  (HL)		  */
+OP(op,a7) { AND(_A);												} /* AND  A 		  */
+
+OP(op,a8) { XOR(_B);												} /* XOR  B 		  */
+OP(op,a9) { XOR(_C);												} /* XOR  C 		  */
+OP(op,aa) { XOR(_D);												} /* XOR  D 		  */
+OP(op,ab) { XOR(_E);												} /* XOR  E 		  */
+OP(op,ac) { XOR(_H);												} /* XOR  H 		  */
+OP(op,ad) { XOR(_L);												} /* XOR  L 		  */
+OP(op,ae) { XOR(RM(_HL));											} /* XOR  (HL)		  */
+OP(op,af) { XOR(_A);												} /* XOR  A 		  */
+
+OP(op,b0) { OR(_B); 												} /* OR   B 		  */
+OP(op,b1) { OR(_C); 												} /* OR   C 		  */
+OP(op,b2) { OR(_D); 												} /* OR   D 		  */
+OP(op,b3) { OR(_E); 												} /* OR   E 		  */
+OP(op,b4) { OR(_H); 												} /* OR   H 		  */
+OP(op,b5) { OR(_L); 												} /* OR   L 		  */
+OP(op,b6) { OR(RM(_HL));											} /* OR   (HL)		  */
+OP(op,b7) { OR(_A); 												} /* OR   A 		  */
+
+OP(op,b8) { CP(_B); 												} /* CP   B 		  */
+OP(op,b9) { CP(_C); 												} /* CP   C 		  */
+OP(op,ba) { CP(_D); 												} /* CP   D 		  */
+OP(op,bb) { CP(_E); 												} /* CP   E 		  */
+OP(op,bc) { CP(_H); 												} /* CP   H 		  */
+OP(op,bd) { CP(_L); 												} /* CP   L 		  */
+OP(op,be) { CP(RM(_HL));											} /* CP   (HL)		  */
+OP(op,bf) { CP(_A); 												} /* CP   A 		  */
+
+OP(op,c0) { RET_COND( !(_F & ZF), 0xc0 );							} /* RET  NZ		  */
+OP(op,c1) { POP(BC);												} /* POP  BC		  */
+OP(op,c2) { JP_COND( !(_F & ZF) );									} /* JP   NZ,a		  */
+OP(op,c3) { JP; 													} /* JP   a 		  */
+OP(op,c4) { CALL_COND( !(_F & ZF), 0xc4 );							} /* CALL NZ,a		  */
+OP(op,c5) { PUSH( BC ); 											} /* PUSH BC		  */
+OP(op,c6) { ADD(ARG()); 											} /* ADD  A,n		  */
+OP(op,c7) { RST(0x00);												} /* RST  0 		  */
+
+OP(op,c8) { RET_COND( _F & ZF, 0xc8 );								} /* RET  Z 		  */
+OP(op,c9) { POP(PC);                                                } /* RET              */
+OP(op,ca) { JP_COND( _F & ZF ); 									} /* JP   Z,a		  */
+OP(op,cb) { _R++; EXEC(cb,ROP());									} /* **** CB xx 	  */
+OP(op,cc) { CALL_COND( _F & ZF, 0xcc ); 							} /* CALL Z,a		  */
+OP(op,cd) { CALL(); 												} /* CALL a 		  */
+OP(op,ce) { ADC(ARG()); 											} /* ADC  A,n		  */
+OP(op,cf) { RST(0x08);												} /* RST  1 		  */
+
+OP(op,d0) { RET_COND( !(_F & CF), 0xd0 );							} /* RET  NC		  */
+OP(op,d1) { POP(DE);												} /* POP  DE		  */
+OP(op,d2) { JP_COND( !(_F & CF) );									} /* JP   NC,a		  */
+OP(op,d3) { unsigned n = ARG() | (_A << 8); OUT( n, _A );			} /* OUT  (n),A 	  */
+OP(op,d4) { CALL_COND( !(_F & CF), 0xd4 );							} /* CALL NC,a		  */
+OP(op,d5) { PUSH( DE ); 											} /* PUSH DE		  */
+OP(op,d6) { SUB(ARG()); 											} /* SUB  n 		  */
+OP(op,d7) { RST(0x10);												} /* RST  2 		  */
+
+OP(op,d8) { RET_COND( _F & CF, 0xd8 );								} /* RET  C 		  */
+OP(op,d9) { EXX;													} /* EXX			  */
+OP(op,da) { JP_COND( _F & CF ); 									} /* JP   C,a		  */
+OP(op,db) { unsigned n = ARG() | (_A << 8); _A = IN( n );			} /* IN   A,(n) 	  */
+OP(op,dc) { CALL_COND( _F & CF, 0xdc ); 							} /* CALL C,a		  */
+OP(op,dd) { _R++; EXEC(dd,ROP());									} /* **** DD xx 	  */
+OP(op,de) { SBC(ARG()); 											} /* SBC  A,n		  */
+OP(op,df) { RST(0x18);												} /* RST  3 		  */
+
+OP(op,e0) { RET_COND( !(_F & PF), 0xe0 );							} /* RET  PO		  */
+OP(op,e1) { POP(HL);												} /* POP  HL		  */
+OP(op,e2) { JP_COND( !(_F & PF) );									} /* JP   PO,a		  */
+OP(op,e3) { EXSP(HL);												} /* EX   HL,(SP)	  */
+OP(op,e4) { CALL_COND( !(_F & PF), 0xe4 );							} /* CALL PO,a		  */
+OP(op,e5) { PUSH( HL ); 											} /* PUSH HL		  */
+OP(op,e6) { AND(ARG()); 											} /* AND  n 		  */
+OP(op,e7) { RST(0x20);												} /* RST  4 		  */
+
+OP(op,e8) { RET_COND( _F & PF, 0xe8 );								} /* RET  PE		  */
+OP(op,e9) { _PC = _HL;                                              } /* JP   (HL)        */
+OP(op,ea) { JP_COND( _F & PF ); 									} /* JP   PE,a		  */
+OP(op,eb) { EX_DE_HL;												} /* EX   DE,HL 	  */
+OP(op,ec) { CALL_COND( _F & PF, 0xec ); 							} /* CALL PE,a		  */
+OP(op,ed) { _R++; EXEC(ed,ROP());									} /* **** ED xx 	  */
+OP(op,ee) { XOR(ARG()); 											} /* XOR  n 		  */
+OP(op,ef) { RST(0x28);												} /* RST  5 		  */
+
+OP(op,f0) { RET_COND( !(_F & SF), 0xf0 );							} /* RET  P 		  */
+OP(op,f1) { POP(AF);												} /* POP  AF		  */
+OP(op,f2) { JP_COND( !(_F & SF) );									} /* JP   P,a		  */
+OP(op,f3) { _IFF1 = _IFF2 = 0;										} /* DI 			  */
+OP(op,f4) { CALL_COND( !(_F & SF), 0xf4 );							} /* CALL P,a		  */
+OP(op,f5) { PUSH( AF ); 											} /* PUSH AF		  */
+OP(op,f6) { OR(ARG());												} /* OR   n 		  */
+OP(op,f7) { RST(0x30);												} /* RST  6 		  */
+
+OP(op,f8) { RET_COND( _F & SF, 0xf8 );								} /* RET  M 		  */
+OP(op,f9) { _SP = _HL;												} /* LD   SP,HL 	  */
+OP(op,fa) { JP_COND(_F & SF);										} /* JP   M,a		  */
+OP(op,fb) { EI; 													} /* EI 			  */
+OP(op,fc) { CALL_COND( _F & SF, 0xfc ); 							} /* CALL M,a		  */
+OP(op,fd) { _R++; EXEC(fd,ROP());									} /* **** FD xx 	  */
+OP(op,fe) { CP(ARG());												} /* CP   n 		  */
+OP(op,ff) { RST(0x38);												} /* RST  7 		  */
+
+
+static void take_interrupt(void)
+{
+	if( _IFF1 )
+	{
+        int irq_vector;
+
+		/* there isn't a valid previous program counter */
+		_PPC = -1;
+
+		/* Check if processor was halted */
+		LEAVE_HALT;
+
+		if( Z80.irq_max )			/* daisy chain mode */
+		{
+			if( Z80.request_irq >= 0 )
+			{
+				/* Clear both interrupt flip flops */
+				_IFF1 = _IFF2 = 0;
+				irq_vector = Z80.irq[Z80.request_irq].interrupt_entry(Z80.irq[Z80.request_irq].irq_param);
+				Z80.request_irq = -1;
+			} else return;
+		}
+		else
+		{
+			/* Clear both interrupt flip flops */
+			_IFF1 = _IFF2 = 0;
+			/* call back the cpu interface to retrieve the vector */
+            irq_vector = (*Z80.irq_callback)(0);
+		}
+
+		/* Interrupt mode 2. Call [Z80.I:databyte] */
+		if( _IM == 2 )
+		{
+			irq_vector = (irq_vector & 0xff) | (_I << 8);
+			PUSH( PC );
+			RM16( irq_vector, &Z80.PC );
+			/* CALL opcode timing */
+			Z80.extra_cycles += cc[Z80_TABLE_op][0xcd];
+		}
+		else
+		/* Interrupt mode 1. RST 38h */
+		if( _IM == 1 )
+		{
+			PUSH( PC );
+			_PCD = 0x0038;
+			/* RST $38 + 'interrupt latency' cycles */
+			Z80.extra_cycles += cc[Z80_TABLE_op][0xff] + cc[Z80_TABLE_ex][0xff];
+		}
+		else
+		{
+			/* Interrupt mode 0. We check for CALL and JP instructions, */
+			/* if neither of these were found we assume a 1 byte opcode */
+			/* was placed on the databus								*/
+			switch (irq_vector & 0xff0000)
+			{
+				case 0xcd0000:	/* call */
+					PUSH( PC );
+					_PCD = irq_vector & 0xffff;
+					 /* CALL $xxxx + 'interrupt latency' cycles */
+					Z80.extra_cycles += cc[Z80_TABLE_op][0xcd] + cc[Z80_TABLE_ex][0xff];
+					break;
+				case 0xc30000:	/* jump */
+					_PCD = irq_vector & 0xffff;
+					/* JP $xxxx + 2 cycles */
+					Z80.extra_cycles += cc[Z80_TABLE_op][0xc3] + cc[Z80_TABLE_ex][0xff];
+					break;
+				default:		/* rst (or other opcodes?) */
+					PUSH( PC );
+					_PCD = irq_vector & 0x0038;
+					/* RST $xx + 2 cycles */
+					Z80.extra_cycles += cc[Z80_TABLE_op][_PCD] + cc[Z80_TABLE_ex][_PCD];
+					break;
+			}
+		}
+	}
+}
+
+/****************************************************************************
+ * Reset registers to their initial values
+ ****************************************************************************/
+void z80_reset(void *param)
+{
+	Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param;
+	int i, p;
+#if BIG_FLAGS_ARRAY
+	if( !SZHVC_add || !SZHVC_sub )
+	{
+		int oldval, newval, val;
+		UINT8 *padd, *padc, *psub, *psbc;
+		/* allocate big flag arrays once */
+		SZHVC_add = (UINT8 *)genmalloc(2*256*256);
+		SZHVC_sub = (UINT8 *)genmalloc(2*256*256);
+		if( !SZHVC_add || !SZHVC_sub )
+		{
+			LOG(("Z80: failed to allocate 2 * 128K flags arrays!!!\n"));
+//			raise(SIGABRT);
+		}
+		padd = &SZHVC_add[	0*256];
+		padc = &SZHVC_add[256*256];
+		psub = &SZHVC_sub[	0*256];
+		psbc = &SZHVC_sub[256*256];
+		for (oldval = 0; oldval < 256; oldval++)
+		{
+			for (newval = 0; newval < 256; newval++)
+			{
+				/* add or adc w/o carry set */
+				val = newval - oldval;
+				*padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+#if Z80_EXACT
+				*padd |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+				if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
+				if( newval < oldval ) *padd |= CF;
+				if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
+				padd++;
+
+				/* adc with carry set */
+				val = newval - oldval - 1;
+				*padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+#if Z80_EXACT
+				*padc |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+				if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
+				if( newval <= oldval ) *padc |= CF;
+				if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
+				padc++;
+
+				/* cp, sub or sbc w/o carry set */
+				val = oldval - newval;
+				*psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+#if Z80_EXACT
+				*psub |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+				if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
+				if( newval > oldval ) *psub |= CF;
+				if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
+				psub++;
+
+				/* sbc with carry set */
+				val = oldval - newval - 1;
+				*psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+#if Z80_EXACT
+				*psbc |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+				if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
+				if( newval >= oldval ) *psbc |= CF;
+				if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
+				psbc++;
+			}
+		}
+	}
+#endif
+	for (i = 0; i < 256; i++)
+	{
+		p = 0;
+		if( i&0x01 ) ++p;
+		if( i&0x02 ) ++p;
+		if( i&0x04 ) ++p;
+		if( i&0x08 ) ++p;
+		if( i&0x10 ) ++p;
+		if( i&0x20 ) ++p;
+		if( i&0x40 ) ++p;
+		if( i&0x80 ) ++p;
+		SZ[i] = i ? i & SF : ZF;
+#if Z80_EXACT
+		SZ[i] |= (i & (YF | XF));		/* undocumented flag bits 5+3 */
+#endif
+		SZ_BIT[i] = i ? i & SF : ZF | PF;
+#if Z80_EXACT
+		SZ_BIT[i] |= (i & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+		SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
+		SZHV_inc[i] = SZ[i];
+		if( i == 0x80 ) SZHV_inc[i] |= VF;
+		if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
+		SZHV_dec[i] = SZ[i] | NF;
+		if( i == 0x7f ) SZHV_dec[i] |= VF;
+		if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
+	}
+
+	memset(&Z80, 0, sizeof(Z80));
+	_IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
+	_F = ZF;			/* Zero flag is set */
+	Z80.request_irq = -1;
+	Z80.service_irq = -1;
+	Z80.nmi_state = CLEAR_LINE;
+	Z80.irq_state = CLEAR_LINE;
+
+	if( daisy_chain )
+	{
+		while( daisy_chain->irq_param != -1 && Z80.irq_max < Z80_MAXDAISY )
+		{
+			/* set callbackhandler after reti */
+			Z80.irq[Z80.irq_max] = *daisy_chain;
+			/* device reset */
+			if( Z80.irq[Z80.irq_max].reset )
+				Z80.irq[Z80.irq_max].reset(Z80.irq[Z80.irq_max].irq_param);
+			Z80.irq_max++;
+			daisy_chain++;
+		}
+	}
+
+}
+
+void z80_exit(void)
+{
+#if BIG_FLAGS_ARRAY
+	if (SZHVC_add) genfree(SZHVC_add);
+	SZHVC_add = NULL;
+	if (SZHVC_sub) genfree(SZHVC_sub);
+	SZHVC_sub = NULL;
+#endif
+}
+
+void z80_end_timeslice(void)
+{
+    z80_ICount = 0;
+}
+
+/****************************************************************************
+ * Execute 'cycles' T-states. Return number of T-states really executed
+ ****************************************************************************/
+int z80_execute(int cycles)
+{
+	z80_ICount = cycles - Z80.extra_cycles;
+	Z80.extra_cycles = 0;
+
+	do
+	{
+		_PPC = _PCD;
+		_R++;
+        EXEC_INLINE(op,ROP());
+	} while( z80_ICount > 0 );
+
+	z80_ICount -= Z80.extra_cycles;
+	Z80.extra_cycles = 0;
+
+	return cycles - z80_ICount;
+}
+
+/****************************************************************************
+ * Burn 'cycles' T-states. Adjust R register for the lost time
+ ****************************************************************************/
+void z80_burn(int cycles)
+{
+	if( cycles > 0 )
+	{
+		/* NOP takes 4 cycles per instruction */
+		int n = (cycles + 3) / 4;
+		_R += n;
+		z80_ICount -= 4 * n;
+	}
+}
+
+/****************************************************************************
+ * Get all registers in given buffer
+ ****************************************************************************/
+unsigned z80_get_context (void *dst)
+{
+	if( dst )
+		*(Z80_Regs*)dst = Z80;
+	return sizeof(Z80_Regs);
+}
+
+/****************************************************************************
+ * Set all registers to given values
+ ****************************************************************************/
+void z80_set_context (void *src)
+{
+	if( src )
+		Z80 = *(Z80_Regs*)src;
+}
+
+/****************************************************************************
+ * Get a pointer to a cycle count table
+ ****************************************************************************/
+void *z80_get_cycle_table (int which)
+{
+	if (which >= 0 && which <= Z80_TABLE_xycb)
+		return cc[which];
+	return NULL;
+}
+
+/****************************************************************************
+ * Set a new cycle count table
+ ****************************************************************************/
+void z80_set_cycle_table (int which, void *new_table)
+{
+	if (which >= 0 && which <= Z80_TABLE_ex)
+		cc[which] = new_table;
+}
+
+/****************************************************************************
+ * Return program counter
+ ****************************************************************************/
+unsigned z80_get_pc (void)
+{
+	return _PCD;
+}
+
+/****************************************************************************
+ * Set program counter
+ ****************************************************************************/
+void z80_set_pc (unsigned val)
+{
+	_PC = val;
+}
+
+/****************************************************************************
+ * Return stack pointer
+ ****************************************************************************/
+unsigned z80_get_sp (void)
+{
+	return _SPD;
+}
+
+/****************************************************************************
+ * Set stack pointer
+ ****************************************************************************/
+void z80_set_sp (unsigned val)
+{
+	_SP = val;
+}
+
+/****************************************************************************
+ * Return a specific register
+ ****************************************************************************/
+unsigned z80_get_reg (int regnum)
+{
+	switch( regnum )
+	{
+		case Z80_PC: return Z80.PC.w.l;
+		case Z80_SP: return Z80.SP.w.l;
+		case Z80_AF: return Z80.AF.w.l;
+		case Z80_BC: return Z80.BC.w.l;
+		case Z80_DE: return Z80.DE.w.l;
+		case Z80_HL: return Z80.HL.w.l;
+		case Z80_IX: return Z80.IX.w.l;
+		case Z80_IY: return Z80.IY.w.l;
+		case Z80_R: return (Z80.R & 0x7f) | (Z80.R2 & 0x80);
+		case Z80_I: return Z80.I;
+		case Z80_AF2: return Z80.AF2.w.l;
+		case Z80_BC2: return Z80.BC2.w.l;
+		case Z80_DE2: return Z80.DE2.w.l;
+		case Z80_HL2: return Z80.HL2.w.l;
+		case Z80_IM: return Z80.IM;
+		case Z80_IFF1: return Z80.IFF1;
+		case Z80_IFF2: return Z80.IFF2;
+		case Z80_HALT: return Z80.HALT;
+		case Z80_NMI_STATE: return Z80.nmi_state;
+		case Z80_IRQ_STATE: return Z80.irq_state;
+		case Z80_DC0: return Z80.int_state[0];
+		case Z80_DC1: return Z80.int_state[1];
+		case Z80_DC2: return Z80.int_state[2];
+		case Z80_DC3: return Z80.int_state[3];
+		case REG_PREVIOUSPC: return Z80.PREPC.w.l;
+		default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0xffff )
+					return RM( offset ) | ( RM( offset + 1) << 8 );
+			}
+	}
+	return 0;
+}
+
+/****************************************************************************
+ * Set a specific register
+ ****************************************************************************/
+void z80_set_reg (int regnum, unsigned val)
+{
+	switch( regnum )
+	{
+		case Z80_PC: Z80.PC.w.l = val; break;
+		case Z80_SP: Z80.SP.w.l = val; break;
+		case Z80_AF: Z80.AF.w.l = val; break;
+		case Z80_BC: Z80.BC.w.l = val; break;
+		case Z80_DE: Z80.DE.w.l = val; break;
+		case Z80_HL: Z80.HL.w.l = val; break;
+		case Z80_IX: Z80.IX.w.l = val; break;
+		case Z80_IY: Z80.IY.w.l = val; break;
+		case Z80_R: Z80.R = val; Z80.R2 = val & 0x80; break;
+		case Z80_I: Z80.I = val; break;
+		case Z80_AF2: Z80.AF2.w.l = val; break;
+		case Z80_BC2: Z80.BC2.w.l = val; break;
+		case Z80_DE2: Z80.DE2.w.l = val; break;
+		case Z80_HL2: Z80.HL2.w.l = val; break;
+		case Z80_IM: Z80.IM = val; break;
+		case Z80_IFF1: Z80.IFF1 = val; break;
+		case Z80_IFF2: Z80.IFF2 = val; break;
+		case Z80_HALT: Z80.HALT = val; break;
+		case Z80_NMI_STATE: z80_set_nmi_line(val); break;
+		case Z80_IRQ_STATE: z80_set_irq_line(0,val); break;
+		case Z80_DC0: Z80.int_state[0] = val; break;
+		case Z80_DC1: Z80.int_state[1] = val; break;
+		case Z80_DC2: Z80.int_state[2] = val; break;
+		case Z80_DC3: Z80.int_state[3] = val; break;
+		default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0xffff )
+				{
+					WM( offset, val & 0xff );
+					WM( offset+1, (val >> 8) & 0xff );
+				}
+			}
+	}
+}
+
+/****************************************************************************
+ * Set NMI line state
+ ****************************************************************************/
+void z80_set_nmi_line(int state)
+{
+	if( Z80.nmi_state == state ) return;
+
+	Z80.nmi_state = state;
+	if( state == CLEAR_LINE ) return;
+
+	_PPC = -1;			/* there isn't a valid previous program counter */
+	LEAVE_HALT; 		/* Check if processor was halted */
+
+	_IFF1 = 0;
+	PUSH( PC );
+	_PCD = 0x0066;
+	Z80.extra_cycles += 11;
+}
+
+/****************************************************************************
+ * Set IRQ line state
+ ****************************************************************************/
+void z80_set_irq_line(int irqline, int state)
+{
+	Z80.irq_state = state;
+	if( state == CLEAR_LINE ) return;
+
+	if( Z80.irq_max )
+	{
+		int daisychain, device, int_state;
+        daisychain = (*Z80.irq_callback)(irqline);
+        daisychain = 0xFF;
+		device = daisychain >> 8;
+		int_state = daisychain & 0xff;
+
+		if( Z80.int_state[device] != int_state )
+		{
+			LOG((" change\n"));
+			/* set new interrupt status */
+			Z80.int_state[device] = int_state;
+			/* check interrupt status */
+			Z80.request_irq = Z80.service_irq = -1;
+
+			/* search higher IRQ or IEO */
+			for( device = 0 ; device < Z80.irq_max ; device ++ )
+			{
+				/* IEO = disable ? */
+				if( Z80.int_state[device] & Z80_INT_IEO )
+				{
+					Z80.request_irq = -1;		/* if IEO is disable , masking lower IRQ */
+					Z80.service_irq = device;	/* set highest interrupt service device */
+				}
+				/* IRQ = request ? */
+				if( Z80.int_state[device] & Z80_INT_REQ )
+					Z80.request_irq = device;
+			}
+			if( Z80.request_irq < 0 ) return;
+		}
+		else
+		{
+			LOG((" no change\n"));
+			return;
+		}
+	}
+	take_interrupt();
+}
+
+/****************************************************************************
+ * Set IRQ vector callback
+ ****************************************************************************/
+void z80_set_irq_callback(int (*callback)(int))
+{
+	Z80.irq_callback = callback;
+}
+
+#if 0
+/****************************************************************************
+ * Save CPU state
+ ****************************************************************************/
+void z80_state_save(void *file)
+{
+	int cpu = cpu_getactivecpu();
+	state_save_UINT16(file, "z80", cpu, "AF", &Z80.AF.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "BC", &Z80.BC.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "DE", &Z80.DE.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "HL", &Z80.HL.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "IX", &Z80.IX.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "IY", &Z80.IY.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "PC", &Z80.PC.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "SP", &Z80.SP.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "AF2", &Z80.AF2.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "BC2", &Z80.BC2.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "DE2", &Z80.DE2.w.l, 1);
+	state_save_UINT16(file, "z80", cpu, "HL2", &Z80.HL2.w.l, 1);
+	state_save_UINT8(file, "z80", cpu, "R", &Z80.R, 1);
+	state_save_UINT8(file, "z80", cpu, "R2", &Z80.R2, 1);
+	state_save_UINT8(file, "z80", cpu, "IFF1", &Z80.IFF1, 1);
+	state_save_UINT8(file, "z80", cpu, "IFF2", &Z80.IFF2, 1);
+	state_save_UINT8(file, "z80", cpu, "HALT", &Z80.HALT, 1);
+	state_save_UINT8(file, "z80", cpu, "IM", &Z80.IM, 1);
+	state_save_UINT8(file, "z80", cpu, "I", &Z80.I, 1);
+	state_save_UINT8(file, "z80", cpu, "irq_max", &Z80.irq_max, 1);
+	state_save_INT8(file, "z80", cpu, "request_irq", &Z80.request_irq, 1);
+	state_save_INT8(file, "z80", cpu, "service_irq", &Z80.service_irq, 1);
+	state_save_UINT8(file, "z80", cpu, "int_state", Z80.int_state, 4);
+	state_save_UINT8(file, "z80", cpu, "nmi_state", &Z80.nmi_state, 1);
+	state_save_UINT8(file, "z80", cpu, "irq_state", &Z80.irq_state, 1);
+	/* daisy chain needs to be saved by z80ctc.c somehow */
+}
+
+/****************************************************************************
+ * Load CPU state
+ ****************************************************************************/
+void z80_state_load(void *file)
+{
+	int cpu = cpu_getactivecpu();
+	state_load_UINT16(file, "z80", cpu, "AF", &Z80.AF.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "BC", &Z80.BC.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "DE", &Z80.DE.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "HL", &Z80.HL.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "IX", &Z80.IX.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "IY", &Z80.IY.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "PC", &Z80.PC.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "SP", &Z80.SP.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "AF2", &Z80.AF2.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "BC2", &Z80.BC2.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "DE2", &Z80.DE2.w.l, 1);
+	state_load_UINT16(file, "z80", cpu, "HL2", &Z80.HL2.w.l, 1);
+	state_load_UINT8(file, "z80", cpu, "R", &Z80.R, 1);
+	state_load_UINT8(file, "z80", cpu, "R2", &Z80.R2, 1);
+	state_load_UINT8(file, "z80", cpu, "IFF1", &Z80.IFF1, 1);
+	state_load_UINT8(file, "z80", cpu, "IFF2", &Z80.IFF2, 1);
+	state_load_UINT8(file, "z80", cpu, "HALT", &Z80.HALT, 1);
+	state_load_UINT8(file, "z80", cpu, "IM", &Z80.IM, 1);
+	state_load_UINT8(file, "z80", cpu, "I", &Z80.I, 1);
+	state_load_UINT8(file, "z80", cpu, "irq_max", &Z80.irq_max, 1);
+	state_load_INT8(file, "z80", cpu, "request_irq", &Z80.request_irq, 1);
+	state_load_INT8(file, "z80", cpu, "service_irq", &Z80.service_irq, 1);
+	state_load_UINT8(file, "z80", cpu, "int_state", Z80.int_state, 4);
+	state_load_UINT8(file, "z80", cpu, "nmi_state", &Z80.nmi_state, 1);
+	state_load_UINT8(file, "z80", cpu, "irq_state", &Z80.irq_state, 1);
+	/* daisy chain needs to be restored by z80ctc.c somehow */
+}
+
+/****************************************************************************
+ * Return a formatted string for a register
+ ****************************************************************************/
+const char *z80_info(void *context, int regnum)
+{
+	static char buffer[32][47+1];
+	static int which = 0;
+	Z80_Regs *r = context;
+
+	which = ++which % 32;
+	buffer[which][0] = '\0';
+	if( !context )
+		r = &Z80;
+
+	switch( regnum )
+	{
+		case CPU_INFO_REG+Z80_PC: sprintf(buffer[which], "PC:%04X", r->PC.w.l); break;
+		case CPU_INFO_REG+Z80_SP: sprintf(buffer[which], "SP:%04X", r->SP.w.l); break;
+		case CPU_INFO_REG+Z80_AF: sprintf(buffer[which], "AF:%04X", r->AF.w.l); break;
+		case CPU_INFO_REG+Z80_BC: sprintf(buffer[which], "BC:%04X", r->BC.w.l); break;
+		case CPU_INFO_REG+Z80_DE: sprintf(buffer[which], "DE:%04X", r->DE.w.l); break;
+		case CPU_INFO_REG+Z80_HL: sprintf(buffer[which], "HL:%04X", r->HL.w.l); break;
+		case CPU_INFO_REG+Z80_IX: sprintf(buffer[which], "IX:%04X", r->IX.w.l); break;
+		case CPU_INFO_REG+Z80_IY: sprintf(buffer[which], "IY:%04X", r->IY.w.l); break;
+		case CPU_INFO_REG+Z80_R: sprintf(buffer[which], "R:%02X", (r->R & 0x7f) | (r->R2 & 0x80)); break;
+		case CPU_INFO_REG+Z80_I: sprintf(buffer[which], "I:%02X", r->I); break;
+		case CPU_INFO_REG+Z80_AF2: sprintf(buffer[which], "AF'%04X", r->AF2.w.l); break;
+		case CPU_INFO_REG+Z80_BC2: sprintf(buffer[which], "BC'%04X", r->BC2.w.l); break;
+		case CPU_INFO_REG+Z80_DE2: sprintf(buffer[which], "DE'%04X", r->DE2.w.l); break;
+		case CPU_INFO_REG+Z80_HL2: sprintf(buffer[which], "HL'%04X", r->HL2.w.l); break;
+		case CPU_INFO_REG+Z80_IM: sprintf(buffer[which], "IM:%X", r->IM); break;
+		case CPU_INFO_REG+Z80_IFF1: sprintf(buffer[which], "IFF1:%X", r->IFF1); break;
+		case CPU_INFO_REG+Z80_IFF2: sprintf(buffer[which], "IFF2:%X", r->IFF2); break;
+		case CPU_INFO_REG+Z80_HALT: sprintf(buffer[which], "HALT:%X", r->HALT); break;
+		case CPU_INFO_REG+Z80_NMI_STATE: sprintf(buffer[which], "NMI:%X", r->nmi_state); break;
+		case CPU_INFO_REG+Z80_IRQ_STATE: sprintf(buffer[which], "IRQ:%X", r->irq_state); break;
+		case CPU_INFO_REG+Z80_DC0: if(Z80.irq_max >= 1) sprintf(buffer[which], "DC0:%X", r->int_state[0]); break;
+		case CPU_INFO_REG+Z80_DC1: if(Z80.irq_max >= 2) sprintf(buffer[which], "DC1:%X", r->int_state[1]); break;
+		case CPU_INFO_REG+Z80_DC2: if(Z80.irq_max >= 3) sprintf(buffer[which], "DC2:%X", r->int_state[2]); break;
+		case CPU_INFO_REG+Z80_DC3: if(Z80.irq_max >= 4) sprintf(buffer[which], "DC3:%X", r->int_state[3]); break;
+		case CPU_INFO_FLAGS:
+			sprintf(buffer[which], "%c%c%c%c%c%c%c%c",
+				r->AF.b.l & 0x80 ? 'S':'.',
+				r->AF.b.l & 0x40 ? 'Z':'.',
+				r->AF.b.l & 0x20 ? '5':'.',
+				r->AF.b.l & 0x10 ? 'H':'.',
+				r->AF.b.l & 0x08 ? '3':'.',
+				r->AF.b.l & 0x04 ? 'P':'.',
+				r->AF.b.l & 0x02 ? 'N':'.',
+				r->AF.b.l & 0x01 ? 'C':'.');
+			break;
+		case CPU_INFO_NAME: return "Z80";
+		case CPU_INFO_FAMILY: return "Zilog Z80";
+		case CPU_INFO_VERSION: return "3.2";
+		case CPU_INFO_FILE: return __FILE__;
+		case CPU_INFO_CREDITS: return "Copyright (C) 1998,1999 Juergen Buchmueller, all rights reserved.";
+		case CPU_INFO_REG_LAYOUT: return (const char *)z80_reg_layout;
+		case CPU_INFO_WIN_LAYOUT: return (const char *)z80_win_layout;
+	}
+	return buffer[which];
+}
+
+unsigned z80_dasm( char *buffer, unsigned pc )
+{
+#ifdef MAME_DEBUG
+	return DasmZ80( buffer, pc );
+#else
+	sprintf( buffer, "$%02X", cpu_readop(pc) );
+	return 1;
+#endif
+}
+#endif
diff --git a/MCUME_pico2/picogenold/z80.h b/MCUME_pico2/picogenold/z80.h
new file mode 100644
index 0000000..a29c1b9
--- /dev/null
+++ b/MCUME_pico2/picogenold/z80.h
@@ -0,0 +1,62 @@
+#ifndef Z80_H
+#define Z80_H
+
+#include "cpuintrf.h"
+#include "osd_cpu.h"
+
+enum {
+	Z80_PC=1, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL,
+	Z80_IX, Z80_IY,	Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2,
+	Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT,
+	Z80_NMI_STATE, Z80_IRQ_STATE, Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3
+};
+
+enum {
+	Z80_TABLE_op,
+	Z80_TABLE_cb,
+	Z80_TABLE_ed,
+	Z80_TABLE_xy,
+	Z80_TABLE_xycb,
+	Z80_TABLE_ex	/* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */
+};
+
+extern int z80_ICount;              /* T-state count                        */
+
+#define Z80_IGNORE_INT  -1          /* Ignore interrupt                     */
+#define Z80_NMI_INT 	-2			/* Execute NMI							*/
+#define Z80_IRQ_INT 	-1000		/* Execute IRQ							*/
+
+extern void z80_reset (void *param);
+extern void z80_exit (void);
+extern void z80_end_timeslice(void);
+extern int z80_execute(int cycles);
+extern void z80_burn(int cycles);
+extern unsigned z80_get_context (void *dst);
+extern void z80_set_context (void *src);
+extern void *z80_get_cycle_table (int which);
+extern void z80_set_cycle_table (int which, void *new_tbl);
+extern unsigned z80_get_pc (void);
+extern void z80_set_pc (unsigned val);
+extern unsigned z80_get_sp (void);
+extern void z80_set_sp (unsigned val);
+extern unsigned z80_get_reg (int regnum);
+extern void z80_set_reg (int regnum, unsigned val);
+extern void z80_set_nmi_line(int state);
+extern void z80_set_irq_line(int irqline, int state);
+extern void z80_set_irq_callback(int (*irq_callback)(int));
+extern void z80_state_save(void *file);
+extern void z80_state_load(void *file);
+extern const char *z80_info(void *context, int regnum);
+extern unsigned z80_dasm(char *buffer, unsigned pc);
+
+#ifdef MAME_DEBUG
+extern unsigned DasmZ80(char *buffer, unsigned pc);
+#endif
+
+unsigned int cpu_readport16(unsigned int port);
+void cpu_writeport16(unsigned int port, unsigned int data);
+unsigned int cpu_readmem16(unsigned int address);
+void cpu_writemem16(unsigned int address, unsigned int data);
+
+#endif
+
diff --git a/MCUME_pico2/picogenold/z80daa.h b/MCUME_pico2/picogenold/z80daa.h
new file mode 100644
index 0000000..b4ad6e1
--- /dev/null
+++ b/MCUME_pico2/picogenold/z80daa.h
@@ -0,0 +1,2051 @@
+static const UINT16 DAATable[0x800] = {
+  (0x00<<8)   +ZF         +VF      ,
+  (0x01<<8)                        ,
+  (0x02<<8)                        ,
+  (0x03<<8)               +VF      ,
+  (0x04<<8)                        ,
+  (0x05<<8)               +VF      ,
+  (0x06<<8)               +VF      ,
+  (0x07<<8)                        ,
+  (0x08<<8)            +XF         ,
+  (0x09<<8)            +XF+VF      ,
+  (0x10<<8)         +HF            ,
+  (0x11<<8)         +HF   +VF      ,
+  (0x12<<8)         +HF   +VF      ,
+  (0x13<<8)         +HF            ,
+  (0x14<<8)         +HF   +VF      ,
+  (0x15<<8)         +HF            ,
+  (0x10<<8)                        ,
+  (0x11<<8)               +VF      ,
+  (0x12<<8)               +VF      ,
+  (0x13<<8)                        ,
+  (0x14<<8)               +VF      ,
+  (0x15<<8)                        ,
+  (0x16<<8)                        ,
+  (0x17<<8)               +VF      ,
+  (0x18<<8)            +XF+VF      ,
+  (0x19<<8)            +XF         ,
+  (0x20<<8)      +YF+HF            ,
+  (0x21<<8)      +YF+HF   +VF      ,
+  (0x22<<8)      +YF+HF   +VF      ,
+  (0x23<<8)      +YF+HF            ,
+  (0x24<<8)      +YF+HF   +VF      ,
+  (0x25<<8)      +YF+HF            ,
+  (0x20<<8)      +YF               ,
+  (0x21<<8)      +YF      +VF      ,
+  (0x22<<8)      +YF      +VF      ,
+  (0x23<<8)      +YF               ,
+  (0x24<<8)      +YF      +VF      ,
+  (0x25<<8)      +YF               ,
+  (0x26<<8)      +YF               ,
+  (0x27<<8)      +YF      +VF      ,
+  (0x28<<8)      +YF   +XF+VF      ,
+  (0x29<<8)      +YF   +XF         ,
+  (0x30<<8)      +YF+HF   +VF      ,
+  (0x31<<8)      +YF+HF            ,
+  (0x32<<8)      +YF+HF            ,
+  (0x33<<8)      +YF+HF   +VF      ,
+  (0x34<<8)      +YF+HF            ,
+  (0x35<<8)      +YF+HF   +VF      ,
+  (0x30<<8)      +YF      +VF      ,
+  (0x31<<8)      +YF               ,
+  (0x32<<8)      +YF               ,
+  (0x33<<8)      +YF      +VF      ,
+  (0x34<<8)      +YF               ,
+  (0x35<<8)      +YF      +VF      ,
+  (0x36<<8)      +YF      +VF      ,
+  (0x37<<8)      +YF               ,
+  (0x38<<8)      +YF   +XF         ,
+  (0x39<<8)      +YF   +XF+VF      ,
+  (0x40<<8)         +HF            ,
+  (0x41<<8)         +HF   +VF      ,
+  (0x42<<8)         +HF   +VF      ,
+  (0x43<<8)         +HF            ,
+  (0x44<<8)         +HF   +VF      ,
+  (0x45<<8)         +HF            ,
+  (0x40<<8)                        ,
+  (0x41<<8)               +VF      ,
+  (0x42<<8)               +VF      ,
+  (0x43<<8)                        ,
+  (0x44<<8)               +VF      ,
+  (0x45<<8)                        ,
+  (0x46<<8)                        ,
+  (0x47<<8)               +VF      ,
+  (0x48<<8)            +XF+VF      ,
+  (0x49<<8)            +XF         ,
+  (0x50<<8)         +HF   +VF      ,
+  (0x51<<8)         +HF            ,
+  (0x52<<8)         +HF            ,
+  (0x53<<8)         +HF   +VF      ,
+  (0x54<<8)         +HF            ,
+  (0x55<<8)         +HF   +VF      ,
+  (0x50<<8)               +VF      ,
+  (0x51<<8)                        ,
+  (0x52<<8)                        ,
+  (0x53<<8)               +VF      ,
+  (0x54<<8)                        ,
+  (0x55<<8)               +VF      ,
+  (0x56<<8)               +VF      ,
+  (0x57<<8)                        ,
+  (0x58<<8)            +XF         ,
+  (0x59<<8)            +XF+VF      ,
+  (0x60<<8)      +YF+HF   +VF      ,
+  (0x61<<8)      +YF+HF            ,
+  (0x62<<8)      +YF+HF            ,
+  (0x63<<8)      +YF+HF   +VF      ,
+  (0x64<<8)      +YF+HF            ,
+  (0x65<<8)      +YF+HF   +VF      ,
+  (0x60<<8)      +YF      +VF      ,
+  (0x61<<8)      +YF               ,
+  (0x62<<8)      +YF               ,
+  (0x63<<8)      +YF      +VF      ,
+  (0x64<<8)      +YF               ,
+  (0x65<<8)      +YF      +VF      ,
+  (0x66<<8)      +YF      +VF      ,
+  (0x67<<8)      +YF               ,
+  (0x68<<8)      +YF   +XF         ,
+  (0x69<<8)      +YF   +XF+VF      ,
+  (0x70<<8)      +YF+HF            ,
+  (0x71<<8)      +YF+HF   +VF      ,
+  (0x72<<8)      +YF+HF   +VF      ,
+  (0x73<<8)      +YF+HF            ,
+  (0x74<<8)      +YF+HF   +VF      ,
+  (0x75<<8)      +YF+HF            ,
+  (0x70<<8)      +YF               ,
+  (0x71<<8)      +YF      +VF      ,
+  (0x72<<8)      +YF      +VF      ,
+  (0x73<<8)      +YF               ,
+  (0x74<<8)      +YF      +VF      ,
+  (0x75<<8)      +YF               ,
+  (0x76<<8)      +YF               ,
+  (0x77<<8)      +YF      +VF      ,
+  (0x78<<8)      +YF   +XF+VF      ,
+  (0x79<<8)      +YF   +XF         ,
+  (0x80<<8)+SF      +HF            ,
+  (0x81<<8)+SF      +HF   +VF      ,
+  (0x82<<8)+SF      +HF   +VF      ,
+  (0x83<<8)+SF      +HF            ,
+  (0x84<<8)+SF      +HF   +VF      ,
+  (0x85<<8)+SF      +HF            ,
+  (0x80<<8)+SF                     ,
+  (0x81<<8)+SF            +VF      ,
+  (0x82<<8)+SF            +VF      ,
+  (0x83<<8)+SF                     ,
+  (0x84<<8)+SF            +VF      ,
+  (0x85<<8)+SF                     ,
+  (0x86<<8)+SF                     ,
+  (0x87<<8)+SF            +VF      ,
+  (0x88<<8)+SF         +XF+VF      ,
+  (0x89<<8)+SF         +XF         ,
+  (0x90<<8)+SF      +HF   +VF      ,
+  (0x91<<8)+SF      +HF            ,
+  (0x92<<8)+SF      +HF            ,
+  (0x93<<8)+SF      +HF   +VF      ,
+  (0x94<<8)+SF      +HF            ,
+  (0x95<<8)+SF      +HF   +VF      ,
+  (0x90<<8)+SF            +VF      ,
+  (0x91<<8)+SF                     ,
+  (0x92<<8)+SF                     ,
+  (0x93<<8)+SF            +VF      ,
+  (0x94<<8)+SF                     ,
+  (0x95<<8)+SF            +VF      ,
+  (0x96<<8)+SF            +VF      ,
+  (0x97<<8)+SF                     ,
+  (0x98<<8)+SF         +XF         ,
+  (0x99<<8)+SF         +XF+VF      ,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF   +CF,
+  (0x01<<8)                     +CF,
+  (0x02<<8)                     +CF,
+  (0x03<<8)               +VF   +CF,
+  (0x04<<8)                     +CF,
+  (0x05<<8)               +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x10<<8)                     +CF,
+  (0x11<<8)               +VF   +CF,
+  (0x12<<8)               +VF   +CF,
+  (0x13<<8)                     +CF,
+  (0x14<<8)               +VF   +CF,
+  (0x15<<8)                     +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x20<<8)      +YF            +CF,
+  (0x21<<8)      +YF      +VF   +CF,
+  (0x22<<8)      +YF      +VF   +CF,
+  (0x23<<8)      +YF            +CF,
+  (0x24<<8)      +YF      +VF   +CF,
+  (0x25<<8)      +YF            +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x30<<8)      +YF      +VF   +CF,
+  (0x31<<8)      +YF            +CF,
+  (0x32<<8)      +YF            +CF,
+  (0x33<<8)      +YF      +VF   +CF,
+  (0x34<<8)      +YF            +CF,
+  (0x35<<8)      +YF      +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x40<<8)                     +CF,
+  (0x41<<8)               +VF   +CF,
+  (0x42<<8)               +VF   +CF,
+  (0x43<<8)                     +CF,
+  (0x44<<8)               +VF   +CF,
+  (0x45<<8)                     +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x50<<8)               +VF   +CF,
+  (0x51<<8)                     +CF,
+  (0x52<<8)                     +CF,
+  (0x53<<8)               +VF   +CF,
+  (0x54<<8)                     +CF,
+  (0x55<<8)               +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x60<<8)      +YF      +VF   +CF,
+  (0x61<<8)      +YF            +CF,
+  (0x62<<8)      +YF            +CF,
+  (0x63<<8)      +YF      +VF   +CF,
+  (0x64<<8)      +YF            +CF,
+  (0x65<<8)      +YF      +VF   +CF,
+  (0x66<<8)      +YF      +VF   +CF,
+  (0x67<<8)      +YF            +CF,
+  (0x68<<8)      +YF   +XF      +CF,
+  (0x69<<8)      +YF   +XF+VF   +CF,
+  (0x70<<8)      +YF+HF         +CF,
+  (0x71<<8)      +YF+HF   +VF   +CF,
+  (0x72<<8)      +YF+HF   +VF   +CF,
+  (0x73<<8)      +YF+HF         +CF,
+  (0x74<<8)      +YF+HF   +VF   +CF,
+  (0x75<<8)      +YF+HF         +CF,
+  (0x70<<8)      +YF            +CF,
+  (0x71<<8)      +YF      +VF   +CF,
+  (0x72<<8)      +YF      +VF   +CF,
+  (0x73<<8)      +YF            +CF,
+  (0x74<<8)      +YF      +VF   +CF,
+  (0x75<<8)      +YF            +CF,
+  (0x76<<8)      +YF            +CF,
+  (0x77<<8)      +YF      +VF   +CF,
+  (0x78<<8)      +YF   +XF+VF   +CF,
+  (0x79<<8)      +YF   +XF      +CF,
+  (0x80<<8)+SF      +HF         +CF,
+  (0x81<<8)+SF      +HF   +VF   +CF,
+  (0x82<<8)+SF      +HF   +VF   +CF,
+  (0x83<<8)+SF      +HF         +CF,
+  (0x84<<8)+SF      +HF   +VF   +CF,
+  (0x85<<8)+SF      +HF         +CF,
+  (0x80<<8)+SF                  +CF,
+  (0x81<<8)+SF            +VF   +CF,
+  (0x82<<8)+SF            +VF   +CF,
+  (0x83<<8)+SF                  +CF,
+  (0x84<<8)+SF            +VF   +CF,
+  (0x85<<8)+SF                  +CF,
+  (0x86<<8)+SF                  +CF,
+  (0x87<<8)+SF            +VF   +CF,
+  (0x88<<8)+SF         +XF+VF   +CF,
+  (0x89<<8)+SF         +XF      +CF,
+  (0x90<<8)+SF      +HF   +VF   +CF,
+  (0x91<<8)+SF      +HF         +CF,
+  (0x92<<8)+SF      +HF         +CF,
+  (0x93<<8)+SF      +HF   +VF   +CF,
+  (0x94<<8)+SF      +HF         +CF,
+  (0x95<<8)+SF      +HF   +VF   +CF,
+  (0x90<<8)+SF            +VF   +CF,
+  (0x91<<8)+SF                  +CF,
+  (0x92<<8)+SF                  +CF,
+  (0x93<<8)+SF            +VF   +CF,
+  (0x94<<8)+SF                  +CF,
+  (0x95<<8)+SF            +VF   +CF,
+  (0x96<<8)+SF            +VF   +CF,
+  (0x97<<8)+SF                  +CF,
+  (0x98<<8)+SF         +XF      +CF,
+  (0x99<<8)+SF         +XF+VF   +CF,
+  (0xA0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA1<<8)+SF   +YF+HF         +CF,
+  (0xA2<<8)+SF   +YF+HF         +CF,
+  (0xA3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA4<<8)+SF   +YF+HF         +CF,
+  (0xA5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA0<<8)+SF   +YF      +VF   +CF,
+  (0xA1<<8)+SF   +YF            +CF,
+  (0xA2<<8)+SF   +YF            +CF,
+  (0xA3<<8)+SF   +YF      +VF   +CF,
+  (0xA4<<8)+SF   +YF            +CF,
+  (0xA5<<8)+SF   +YF      +VF   +CF,
+  (0xA6<<8)+SF   +YF      +VF   +CF,
+  (0xA7<<8)+SF   +YF            +CF,
+  (0xA8<<8)+SF   +YF   +XF      +CF,
+  (0xA9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB0<<8)+SF   +YF+HF         +CF,
+  (0xB1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB3<<8)+SF   +YF+HF         +CF,
+  (0xB4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB5<<8)+SF   +YF+HF         +CF,
+  (0xB0<<8)+SF   +YF            +CF,
+  (0xB1<<8)+SF   +YF      +VF   +CF,
+  (0xB2<<8)+SF   +YF      +VF   +CF,
+  (0xB3<<8)+SF   +YF            +CF,
+  (0xB4<<8)+SF   +YF      +VF   +CF,
+  (0xB5<<8)+SF   +YF            +CF,
+  (0xB6<<8)+SF   +YF            +CF,
+  (0xB7<<8)+SF   +YF      +VF   +CF,
+  (0xB8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB9<<8)+SF   +YF   +XF      +CF,
+  (0xC0<<8)+SF      +HF   +VF   +CF,
+  (0xC1<<8)+SF      +HF         +CF,
+  (0xC2<<8)+SF      +HF         +CF,
+  (0xC3<<8)+SF      +HF   +VF   +CF,
+  (0xC4<<8)+SF      +HF         +CF,
+  (0xC5<<8)+SF      +HF   +VF   +CF,
+  (0xC0<<8)+SF            +VF   +CF,
+  (0xC1<<8)+SF                  +CF,
+  (0xC2<<8)+SF                  +CF,
+  (0xC3<<8)+SF            +VF   +CF,
+  (0xC4<<8)+SF                  +CF,
+  (0xC5<<8)+SF            +VF   +CF,
+  (0xC6<<8)+SF            +VF   +CF,
+  (0xC7<<8)+SF                  +CF,
+  (0xC8<<8)+SF         +XF      +CF,
+  (0xC9<<8)+SF         +XF+VF   +CF,
+  (0xD0<<8)+SF      +HF         +CF,
+  (0xD1<<8)+SF      +HF   +VF   +CF,
+  (0xD2<<8)+SF      +HF   +VF   +CF,
+  (0xD3<<8)+SF      +HF         +CF,
+  (0xD4<<8)+SF      +HF   +VF   +CF,
+  (0xD5<<8)+SF      +HF         +CF,
+  (0xD0<<8)+SF                  +CF,
+  (0xD1<<8)+SF            +VF   +CF,
+  (0xD2<<8)+SF            +VF   +CF,
+  (0xD3<<8)+SF                  +CF,
+  (0xD4<<8)+SF            +VF   +CF,
+  (0xD5<<8)+SF                  +CF,
+  (0xD6<<8)+SF                  +CF,
+  (0xD7<<8)+SF            +VF   +CF,
+  (0xD8<<8)+SF         +XF+VF   +CF,
+  (0xD9<<8)+SF         +XF      +CF,
+  (0xE0<<8)+SF   +YF+HF         +CF,
+  (0xE1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE3<<8)+SF   +YF+HF         +CF,
+  (0xE4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE5<<8)+SF   +YF+HF         +CF,
+  (0xE0<<8)+SF   +YF            +CF,
+  (0xE1<<8)+SF   +YF      +VF   +CF,
+  (0xE2<<8)+SF   +YF      +VF   +CF,
+  (0xE3<<8)+SF   +YF            +CF,
+  (0xE4<<8)+SF   +YF      +VF   +CF,
+  (0xE5<<8)+SF   +YF            +CF,
+  (0xE6<<8)+SF   +YF            +CF,
+  (0xE7<<8)+SF   +YF      +VF   +CF,
+  (0xE8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xE9<<8)+SF   +YF   +XF      +CF,
+  (0xF0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF1<<8)+SF   +YF+HF         +CF,
+  (0xF2<<8)+SF   +YF+HF         +CF,
+  (0xF3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF4<<8)+SF   +YF+HF         +CF,
+  (0xF5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF0<<8)+SF   +YF      +VF   +CF,
+  (0xF1<<8)+SF   +YF            +CF,
+  (0xF2<<8)+SF   +YF            +CF,
+  (0xF3<<8)+SF   +YF      +VF   +CF,
+  (0xF4<<8)+SF   +YF            +CF,
+  (0xF5<<8)+SF   +YF      +VF   +CF,
+  (0xF6<<8)+SF   +YF      +VF   +CF,
+  (0xF7<<8)+SF   +YF            +CF,
+  (0xF8<<8)+SF   +YF   +XF      +CF,
+  (0xF9<<8)+SF   +YF   +XF+VF   +CF,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF   +CF,
+  (0x01<<8)                     +CF,
+  (0x02<<8)                     +CF,
+  (0x03<<8)               +VF   +CF,
+  (0x04<<8)                     +CF,
+  (0x05<<8)               +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x10<<8)                     +CF,
+  (0x11<<8)               +VF   +CF,
+  (0x12<<8)               +VF   +CF,
+  (0x13<<8)                     +CF,
+  (0x14<<8)               +VF   +CF,
+  (0x15<<8)                     +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x20<<8)      +YF            +CF,
+  (0x21<<8)      +YF      +VF   +CF,
+  (0x22<<8)      +YF      +VF   +CF,
+  (0x23<<8)      +YF            +CF,
+  (0x24<<8)      +YF      +VF   +CF,
+  (0x25<<8)      +YF            +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x30<<8)      +YF      +VF   +CF,
+  (0x31<<8)      +YF            +CF,
+  (0x32<<8)      +YF            +CF,
+  (0x33<<8)      +YF      +VF   +CF,
+  (0x34<<8)      +YF            +CF,
+  (0x35<<8)      +YF      +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x40<<8)                     +CF,
+  (0x41<<8)               +VF   +CF,
+  (0x42<<8)               +VF   +CF,
+  (0x43<<8)                     +CF,
+  (0x44<<8)               +VF   +CF,
+  (0x45<<8)                     +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x50<<8)               +VF   +CF,
+  (0x51<<8)                     +CF,
+  (0x52<<8)                     +CF,
+  (0x53<<8)               +VF   +CF,
+  (0x54<<8)                     +CF,
+  (0x55<<8)               +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x06<<8)               +VF      ,
+  (0x07<<8)                        ,
+  (0x08<<8)            +XF         ,
+  (0x09<<8)            +XF+VF      ,
+  (0x0A<<8)            +XF+VF      ,
+  (0x0B<<8)            +XF         ,
+  (0x0C<<8)            +XF+VF      ,
+  (0x0D<<8)            +XF         ,
+  (0x0E<<8)            +XF         ,
+  (0x0F<<8)            +XF+VF      ,
+  (0x10<<8)         +HF            ,
+  (0x11<<8)         +HF   +VF      ,
+  (0x12<<8)         +HF   +VF      ,
+  (0x13<<8)         +HF            ,
+  (0x14<<8)         +HF   +VF      ,
+  (0x15<<8)         +HF            ,
+  (0x16<<8)                        ,
+  (0x17<<8)               +VF      ,
+  (0x18<<8)            +XF+VF      ,
+  (0x19<<8)            +XF         ,
+  (0x1A<<8)            +XF         ,
+  (0x1B<<8)            +XF+VF      ,
+  (0x1C<<8)            +XF         ,
+  (0x1D<<8)            +XF+VF      ,
+  (0x1E<<8)            +XF+VF      ,
+  (0x1F<<8)            +XF         ,
+  (0x20<<8)      +YF+HF            ,
+  (0x21<<8)      +YF+HF   +VF      ,
+  (0x22<<8)      +YF+HF   +VF      ,
+  (0x23<<8)      +YF+HF            ,
+  (0x24<<8)      +YF+HF   +VF      ,
+  (0x25<<8)      +YF+HF            ,
+  (0x26<<8)      +YF               ,
+  (0x27<<8)      +YF      +VF      ,
+  (0x28<<8)      +YF   +XF+VF      ,
+  (0x29<<8)      +YF   +XF         ,
+  (0x2A<<8)      +YF   +XF         ,
+  (0x2B<<8)      +YF   +XF+VF      ,
+  (0x2C<<8)      +YF   +XF         ,
+  (0x2D<<8)      +YF   +XF+VF      ,
+  (0x2E<<8)      +YF   +XF+VF      ,
+  (0x2F<<8)      +YF   +XF         ,
+  (0x30<<8)      +YF+HF   +VF      ,
+  (0x31<<8)      +YF+HF            ,
+  (0x32<<8)      +YF+HF            ,
+  (0x33<<8)      +YF+HF   +VF      ,
+  (0x34<<8)      +YF+HF            ,
+  (0x35<<8)      +YF+HF   +VF      ,
+  (0x36<<8)      +YF      +VF      ,
+  (0x37<<8)      +YF               ,
+  (0x38<<8)      +YF   +XF         ,
+  (0x39<<8)      +YF   +XF+VF      ,
+  (0x3A<<8)      +YF   +XF+VF      ,
+  (0x3B<<8)      +YF   +XF         ,
+  (0x3C<<8)      +YF   +XF+VF      ,
+  (0x3D<<8)      +YF   +XF         ,
+  (0x3E<<8)      +YF   +XF         ,
+  (0x3F<<8)      +YF   +XF+VF      ,
+  (0x40<<8)         +HF            ,
+  (0x41<<8)         +HF   +VF      ,
+  (0x42<<8)         +HF   +VF      ,
+  (0x43<<8)         +HF            ,
+  (0x44<<8)         +HF   +VF      ,
+  (0x45<<8)         +HF            ,
+  (0x46<<8)                        ,
+  (0x47<<8)               +VF      ,
+  (0x48<<8)            +XF+VF      ,
+  (0x49<<8)            +XF         ,
+  (0x4A<<8)            +XF         ,
+  (0x4B<<8)            +XF+VF      ,
+  (0x4C<<8)            +XF         ,
+  (0x4D<<8)            +XF+VF      ,
+  (0x4E<<8)            +XF+VF      ,
+  (0x4F<<8)            +XF         ,
+  (0x50<<8)         +HF   +VF      ,
+  (0x51<<8)         +HF            ,
+  (0x52<<8)         +HF            ,
+  (0x53<<8)         +HF   +VF      ,
+  (0x54<<8)         +HF            ,
+  (0x55<<8)         +HF   +VF      ,
+  (0x56<<8)               +VF      ,
+  (0x57<<8)                        ,
+  (0x58<<8)            +XF         ,
+  (0x59<<8)            +XF+VF      ,
+  (0x5A<<8)            +XF+VF      ,
+  (0x5B<<8)            +XF         ,
+  (0x5C<<8)            +XF+VF      ,
+  (0x5D<<8)            +XF         ,
+  (0x5E<<8)            +XF         ,
+  (0x5F<<8)            +XF+VF      ,
+  (0x60<<8)      +YF+HF   +VF      ,
+  (0x61<<8)      +YF+HF            ,
+  (0x62<<8)      +YF+HF            ,
+  (0x63<<8)      +YF+HF   +VF      ,
+  (0x64<<8)      +YF+HF            ,
+  (0x65<<8)      +YF+HF   +VF      ,
+  (0x66<<8)      +YF      +VF      ,
+  (0x67<<8)      +YF               ,
+  (0x68<<8)      +YF   +XF         ,
+  (0x69<<8)      +YF   +XF+VF      ,
+  (0x6A<<8)      +YF   +XF+VF      ,
+  (0x6B<<8)      +YF   +XF         ,
+  (0x6C<<8)      +YF   +XF+VF      ,
+  (0x6D<<8)      +YF   +XF         ,
+  (0x6E<<8)      +YF   +XF         ,
+  (0x6F<<8)      +YF   +XF+VF      ,
+  (0x70<<8)      +YF+HF            ,
+  (0x71<<8)      +YF+HF   +VF      ,
+  (0x72<<8)      +YF+HF   +VF      ,
+  (0x73<<8)      +YF+HF            ,
+  (0x74<<8)      +YF+HF   +VF      ,
+  (0x75<<8)      +YF+HF            ,
+  (0x76<<8)      +YF               ,
+  (0x77<<8)      +YF      +VF      ,
+  (0x78<<8)      +YF   +XF+VF      ,
+  (0x79<<8)      +YF   +XF         ,
+  (0x7A<<8)      +YF   +XF         ,
+  (0x7B<<8)      +YF   +XF+VF      ,
+  (0x7C<<8)      +YF   +XF         ,
+  (0x7D<<8)      +YF   +XF+VF      ,
+  (0x7E<<8)      +YF   +XF+VF      ,
+  (0x7F<<8)      +YF   +XF         ,
+  (0x80<<8)+SF      +HF            ,
+  (0x81<<8)+SF      +HF   +VF      ,
+  (0x82<<8)+SF      +HF   +VF      ,
+  (0x83<<8)+SF      +HF            ,
+  (0x84<<8)+SF      +HF   +VF      ,
+  (0x85<<8)+SF      +HF            ,
+  (0x86<<8)+SF                     ,
+  (0x87<<8)+SF            +VF      ,
+  (0x88<<8)+SF         +XF+VF      ,
+  (0x89<<8)+SF         +XF         ,
+  (0x8A<<8)+SF         +XF         ,
+  (0x8B<<8)+SF         +XF+VF      ,
+  (0x8C<<8)+SF         +XF         ,
+  (0x8D<<8)+SF         +XF+VF      ,
+  (0x8E<<8)+SF         +XF+VF      ,
+  (0x8F<<8)+SF         +XF         ,
+  (0x90<<8)+SF      +HF   +VF      ,
+  (0x91<<8)+SF      +HF            ,
+  (0x92<<8)+SF      +HF            ,
+  (0x93<<8)+SF      +HF   +VF      ,
+  (0x94<<8)+SF      +HF            ,
+  (0x95<<8)+SF      +HF   +VF      ,
+  (0x96<<8)+SF            +VF      ,
+  (0x97<<8)+SF                     ,
+  (0x98<<8)+SF         +XF         ,
+  (0x99<<8)+SF         +XF+VF      ,
+  (0x9A<<8)+SF         +XF+VF      ,
+  (0x9B<<8)+SF         +XF         ,
+  (0x9C<<8)+SF         +XF+VF      ,
+  (0x9D<<8)+SF         +XF         ,
+  (0x9E<<8)+SF         +XF         ,
+  (0x9F<<8)+SF         +XF+VF      ,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x0A<<8)            +XF+VF   +CF,
+  (0x0B<<8)            +XF      +CF,
+  (0x0C<<8)            +XF+VF   +CF,
+  (0x0D<<8)            +XF      +CF,
+  (0x0E<<8)            +XF      +CF,
+  (0x0F<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x1A<<8)            +XF      +CF,
+  (0x1B<<8)            +XF+VF   +CF,
+  (0x1C<<8)            +XF      +CF,
+  (0x1D<<8)            +XF+VF   +CF,
+  (0x1E<<8)            +XF+VF   +CF,
+  (0x1F<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x2A<<8)      +YF   +XF      +CF,
+  (0x2B<<8)      +YF   +XF+VF   +CF,
+  (0x2C<<8)      +YF   +XF      +CF,
+  (0x2D<<8)      +YF   +XF+VF   +CF,
+  (0x2E<<8)      +YF   +XF+VF   +CF,
+  (0x2F<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x3A<<8)      +YF   +XF+VF   +CF,
+  (0x3B<<8)      +YF   +XF      +CF,
+  (0x3C<<8)      +YF   +XF+VF   +CF,
+  (0x3D<<8)      +YF   +XF      +CF,
+  (0x3E<<8)      +YF   +XF      +CF,
+  (0x3F<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x4A<<8)            +XF      +CF,
+  (0x4B<<8)            +XF+VF   +CF,
+  (0x4C<<8)            +XF      +CF,
+  (0x4D<<8)            +XF+VF   +CF,
+  (0x4E<<8)            +XF+VF   +CF,
+  (0x4F<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x5A<<8)            +XF+VF   +CF,
+  (0x5B<<8)            +XF      +CF,
+  (0x5C<<8)            +XF+VF   +CF,
+  (0x5D<<8)            +XF      +CF,
+  (0x5E<<8)            +XF      +CF,
+  (0x5F<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x66<<8)      +YF      +VF   +CF,
+  (0x67<<8)      +YF            +CF,
+  (0x68<<8)      +YF   +XF      +CF,
+  (0x69<<8)      +YF   +XF+VF   +CF,
+  (0x6A<<8)      +YF   +XF+VF   +CF,
+  (0x6B<<8)      +YF   +XF      +CF,
+  (0x6C<<8)      +YF   +XF+VF   +CF,
+  (0x6D<<8)      +YF   +XF      +CF,
+  (0x6E<<8)      +YF   +XF      +CF,
+  (0x6F<<8)      +YF   +XF+VF   +CF,
+  (0x70<<8)      +YF+HF         +CF,
+  (0x71<<8)      +YF+HF   +VF   +CF,
+  (0x72<<8)      +YF+HF   +VF   +CF,
+  (0x73<<8)      +YF+HF         +CF,
+  (0x74<<8)      +YF+HF   +VF   +CF,
+  (0x75<<8)      +YF+HF         +CF,
+  (0x76<<8)      +YF            +CF,
+  (0x77<<8)      +YF      +VF   +CF,
+  (0x78<<8)      +YF   +XF+VF   +CF,
+  (0x79<<8)      +YF   +XF      +CF,
+  (0x7A<<8)      +YF   +XF      +CF,
+  (0x7B<<8)      +YF   +XF+VF   +CF,
+  (0x7C<<8)      +YF   +XF      +CF,
+  (0x7D<<8)      +YF   +XF+VF   +CF,
+  (0x7E<<8)      +YF   +XF+VF   +CF,
+  (0x7F<<8)      +YF   +XF      +CF,
+  (0x80<<8)+SF      +HF         +CF,
+  (0x81<<8)+SF      +HF   +VF   +CF,
+  (0x82<<8)+SF      +HF   +VF   +CF,
+  (0x83<<8)+SF      +HF         +CF,
+  (0x84<<8)+SF      +HF   +VF   +CF,
+  (0x85<<8)+SF      +HF         +CF,
+  (0x86<<8)+SF                  +CF,
+  (0x87<<8)+SF            +VF   +CF,
+  (0x88<<8)+SF         +XF+VF   +CF,
+  (0x89<<8)+SF         +XF      +CF,
+  (0x8A<<8)+SF         +XF      +CF,
+  (0x8B<<8)+SF         +XF+VF   +CF,
+  (0x8C<<8)+SF         +XF      +CF,
+  (0x8D<<8)+SF         +XF+VF   +CF,
+  (0x8E<<8)+SF         +XF+VF   +CF,
+  (0x8F<<8)+SF         +XF      +CF,
+  (0x90<<8)+SF      +HF   +VF   +CF,
+  (0x91<<8)+SF      +HF         +CF,
+  (0x92<<8)+SF      +HF         +CF,
+  (0x93<<8)+SF      +HF   +VF   +CF,
+  (0x94<<8)+SF      +HF         +CF,
+  (0x95<<8)+SF      +HF   +VF   +CF,
+  (0x96<<8)+SF            +VF   +CF,
+  (0x97<<8)+SF                  +CF,
+  (0x98<<8)+SF         +XF      +CF,
+  (0x99<<8)+SF         +XF+VF   +CF,
+  (0x9A<<8)+SF         +XF+VF   +CF,
+  (0x9B<<8)+SF         +XF      +CF,
+  (0x9C<<8)+SF         +XF+VF   +CF,
+  (0x9D<<8)+SF         +XF      +CF,
+  (0x9E<<8)+SF         +XF      +CF,
+  (0x9F<<8)+SF         +XF+VF   +CF,
+  (0xA0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA1<<8)+SF   +YF+HF         +CF,
+  (0xA2<<8)+SF   +YF+HF         +CF,
+  (0xA3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA4<<8)+SF   +YF+HF         +CF,
+  (0xA5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA6<<8)+SF   +YF      +VF   +CF,
+  (0xA7<<8)+SF   +YF            +CF,
+  (0xA8<<8)+SF   +YF   +XF      +CF,
+  (0xA9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAA<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAB<<8)+SF   +YF   +XF      +CF,
+  (0xAC<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAD<<8)+SF   +YF   +XF      +CF,
+  (0xAE<<8)+SF   +YF   +XF      +CF,
+  (0xAF<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB0<<8)+SF   +YF+HF         +CF,
+  (0xB1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB3<<8)+SF   +YF+HF         +CF,
+  (0xB4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB5<<8)+SF   +YF+HF         +CF,
+  (0xB6<<8)+SF   +YF            +CF,
+  (0xB7<<8)+SF   +YF      +VF   +CF,
+  (0xB8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB9<<8)+SF   +YF   +XF      +CF,
+  (0xBA<<8)+SF   +YF   +XF      +CF,
+  (0xBB<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBC<<8)+SF   +YF   +XF      +CF,
+  (0xBD<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBE<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBF<<8)+SF   +YF   +XF      +CF,
+  (0xC0<<8)+SF      +HF   +VF   +CF,
+  (0xC1<<8)+SF      +HF         +CF,
+  (0xC2<<8)+SF      +HF         +CF,
+  (0xC3<<8)+SF      +HF   +VF   +CF,
+  (0xC4<<8)+SF      +HF         +CF,
+  (0xC5<<8)+SF      +HF   +VF   +CF,
+  (0xC6<<8)+SF            +VF   +CF,
+  (0xC7<<8)+SF                  +CF,
+  (0xC8<<8)+SF         +XF      +CF,
+  (0xC9<<8)+SF         +XF+VF   +CF,
+  (0xCA<<8)+SF         +XF+VF   +CF,
+  (0xCB<<8)+SF         +XF      +CF,
+  (0xCC<<8)+SF         +XF+VF   +CF,
+  (0xCD<<8)+SF         +XF      +CF,
+  (0xCE<<8)+SF         +XF      +CF,
+  (0xCF<<8)+SF         +XF+VF   +CF,
+  (0xD0<<8)+SF      +HF         +CF,
+  (0xD1<<8)+SF      +HF   +VF   +CF,
+  (0xD2<<8)+SF      +HF   +VF   +CF,
+  (0xD3<<8)+SF      +HF         +CF,
+  (0xD4<<8)+SF      +HF   +VF   +CF,
+  (0xD5<<8)+SF      +HF         +CF,
+  (0xD6<<8)+SF                  +CF,
+  (0xD7<<8)+SF            +VF   +CF,
+  (0xD8<<8)+SF         +XF+VF   +CF,
+  (0xD9<<8)+SF         +XF      +CF,
+  (0xDA<<8)+SF         +XF      +CF,
+  (0xDB<<8)+SF         +XF+VF   +CF,
+  (0xDC<<8)+SF         +XF      +CF,
+  (0xDD<<8)+SF         +XF+VF   +CF,
+  (0xDE<<8)+SF         +XF+VF   +CF,
+  (0xDF<<8)+SF         +XF      +CF,
+  (0xE0<<8)+SF   +YF+HF         +CF,
+  (0xE1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE3<<8)+SF   +YF+HF         +CF,
+  (0xE4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE5<<8)+SF   +YF+HF         +CF,
+  (0xE6<<8)+SF   +YF            +CF,
+  (0xE7<<8)+SF   +YF      +VF   +CF,
+  (0xE8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xE9<<8)+SF   +YF   +XF      +CF,
+  (0xEA<<8)+SF   +YF   +XF      +CF,
+  (0xEB<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEC<<8)+SF   +YF   +XF      +CF,
+  (0xED<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEE<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEF<<8)+SF   +YF   +XF      +CF,
+  (0xF0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF1<<8)+SF   +YF+HF         +CF,
+  (0xF2<<8)+SF   +YF+HF         +CF,
+  (0xF3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF4<<8)+SF   +YF+HF         +CF,
+  (0xF5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF6<<8)+SF   +YF      +VF   +CF,
+  (0xF7<<8)+SF   +YF            +CF,
+  (0xF8<<8)+SF   +YF   +XF      +CF,
+  (0xF9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFA<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFB<<8)+SF   +YF   +XF      +CF,
+  (0xFC<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFD<<8)+SF   +YF   +XF      +CF,
+  (0xFE<<8)+SF   +YF   +XF      +CF,
+  (0xFF<<8)+SF   +YF   +XF+VF   +CF,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x0A<<8)            +XF+VF   +CF,
+  (0x0B<<8)            +XF      +CF,
+  (0x0C<<8)            +XF+VF   +CF,
+  (0x0D<<8)            +XF      +CF,
+  (0x0E<<8)            +XF      +CF,
+  (0x0F<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x1A<<8)            +XF      +CF,
+  (0x1B<<8)            +XF+VF   +CF,
+  (0x1C<<8)            +XF      +CF,
+  (0x1D<<8)            +XF+VF   +CF,
+  (0x1E<<8)            +XF+VF   +CF,
+  (0x1F<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x2A<<8)      +YF   +XF      +CF,
+  (0x2B<<8)      +YF   +XF+VF   +CF,
+  (0x2C<<8)      +YF   +XF      +CF,
+  (0x2D<<8)      +YF   +XF+VF   +CF,
+  (0x2E<<8)      +YF   +XF+VF   +CF,
+  (0x2F<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x3A<<8)      +YF   +XF+VF   +CF,
+  (0x3B<<8)      +YF   +XF      +CF,
+  (0x3C<<8)      +YF   +XF+VF   +CF,
+  (0x3D<<8)      +YF   +XF      +CF,
+  (0x3E<<8)      +YF   +XF      +CF,
+  (0x3F<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x4A<<8)            +XF      +CF,
+  (0x4B<<8)            +XF+VF   +CF,
+  (0x4C<<8)            +XF      +CF,
+  (0x4D<<8)            +XF+VF   +CF,
+  (0x4E<<8)            +XF+VF   +CF,
+  (0x4F<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x5A<<8)            +XF+VF   +CF,
+  (0x5B<<8)            +XF      +CF,
+  (0x5C<<8)            +XF+VF   +CF,
+  (0x5D<<8)            +XF      +CF,
+  (0x5E<<8)            +XF      +CF,
+  (0x5F<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF+NF   ,
+  (0x01<<8)                  +NF   ,
+  (0x02<<8)                  +NF   ,
+  (0x03<<8)               +VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x10<<8)                  +NF   ,
+  (0x11<<8)               +VF+NF   ,
+  (0x12<<8)               +VF+NF   ,
+  (0x13<<8)                  +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x20<<8)      +YF         +NF   ,
+  (0x21<<8)      +YF      +VF+NF   ,
+  (0x22<<8)      +YF      +VF+NF   ,
+  (0x23<<8)      +YF         +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x30<<8)      +YF      +VF+NF   ,
+  (0x31<<8)      +YF         +NF   ,
+  (0x32<<8)      +YF         +NF   ,
+  (0x33<<8)      +YF      +VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x40<<8)                  +NF   ,
+  (0x41<<8)               +VF+NF   ,
+  (0x42<<8)               +VF+NF   ,
+  (0x43<<8)                  +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x50<<8)               +VF+NF   ,
+  (0x51<<8)                  +NF   ,
+  (0x52<<8)                  +NF   ,
+  (0x53<<8)               +VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x60<<8)      +YF      +VF+NF   ,
+  (0x61<<8)      +YF         +NF   ,
+  (0x62<<8)      +YF         +NF   ,
+  (0x63<<8)      +YF      +VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x70<<8)      +YF         +NF   ,
+  (0x71<<8)      +YF      +VF+NF   ,
+  (0x72<<8)      +YF      +VF+NF   ,
+  (0x73<<8)      +YF         +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x80<<8)+SF               +NF   ,
+  (0x81<<8)+SF            +VF+NF   ,
+  (0x82<<8)+SF            +VF+NF   ,
+  (0x83<<8)+SF               +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x90<<8)+SF            +VF+NF   ,
+  (0x91<<8)+SF               +NF   ,
+  (0x92<<8)+SF               +NF   ,
+  (0x93<<8)+SF            +VF+NF   ,
+  (0x94<<8)+SF               +NF   ,
+  (0x95<<8)+SF            +VF+NF   ,
+  (0x96<<8)+SF            +VF+NF   ,
+  (0x97<<8)+SF               +NF   ,
+  (0x98<<8)+SF         +XF   +NF   ,
+  (0x99<<8)+SF         +XF+VF+NF   ,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0xA0<<8)+SF   +YF      +VF+NF+CF,
+  (0xA1<<8)+SF   +YF         +NF+CF,
+  (0xA2<<8)+SF   +YF         +NF+CF,
+  (0xA3<<8)+SF   +YF      +VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB0<<8)+SF   +YF         +NF+CF,
+  (0xB1<<8)+SF   +YF      +VF+NF+CF,
+  (0xB2<<8)+SF   +YF      +VF+NF+CF,
+  (0xB3<<8)+SF   +YF         +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xC0<<8)+SF            +VF+NF+CF,
+  (0xC1<<8)+SF               +NF+CF,
+  (0xC2<<8)+SF               +NF+CF,
+  (0xC3<<8)+SF            +VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xD0<<8)+SF               +NF+CF,
+  (0xD1<<8)+SF            +VF+NF+CF,
+  (0xD2<<8)+SF            +VF+NF+CF,
+  (0xD3<<8)+SF               +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xE0<<8)+SF   +YF         +NF+CF,
+  (0xE1<<8)+SF   +YF      +VF+NF+CF,
+  (0xE2<<8)+SF   +YF      +VF+NF+CF,
+  (0xE3<<8)+SF   +YF         +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF0<<8)+SF   +YF      +VF+NF+CF,
+  (0xF1<<8)+SF   +YF         +NF+CF,
+  (0xF2<<8)+SF   +YF         +NF+CF,
+  (0xF3<<8)+SF   +YF      +VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0x00<<8)   +ZF         +VF+NF+CF,
+  (0x01<<8)                  +NF+CF,
+  (0x02<<8)                  +NF+CF,
+  (0x03<<8)               +VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x10<<8)                  +NF+CF,
+  (0x11<<8)               +VF+NF+CF,
+  (0x12<<8)               +VF+NF+CF,
+  (0x13<<8)                  +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x20<<8)      +YF         +NF+CF,
+  (0x21<<8)      +YF      +VF+NF+CF,
+  (0x22<<8)      +YF      +VF+NF+CF,
+  (0x23<<8)      +YF         +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x30<<8)      +YF      +VF+NF+CF,
+  (0x31<<8)      +YF         +NF+CF,
+  (0x32<<8)      +YF         +NF+CF,
+  (0x33<<8)      +YF      +VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0xFA<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0xFB<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFC<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0xFD<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFE<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFF<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0x00<<8)   +ZF         +VF+NF   ,
+  (0x01<<8)                  +NF   ,
+  (0x02<<8)                  +NF   ,
+  (0x03<<8)               +VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x0A<<8)         +HF+XF+VF+NF   ,
+  (0x0B<<8)         +HF+XF   +NF   ,
+  (0x0C<<8)         +HF+XF+VF+NF   ,
+  (0x0D<<8)         +HF+XF   +NF   ,
+  (0x0E<<8)         +HF+XF   +NF   ,
+  (0x0F<<8)         +HF+XF+VF+NF   ,
+  (0x10<<8)                  +NF   ,
+  (0x11<<8)               +VF+NF   ,
+  (0x12<<8)               +VF+NF   ,
+  (0x13<<8)                  +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x1A<<8)         +HF+XF   +NF   ,
+  (0x1B<<8)         +HF+XF+VF+NF   ,
+  (0x1C<<8)         +HF+XF   +NF   ,
+  (0x1D<<8)         +HF+XF+VF+NF   ,
+  (0x1E<<8)         +HF+XF+VF+NF   ,
+  (0x1F<<8)         +HF+XF   +NF   ,
+  (0x20<<8)      +YF         +NF   ,
+  (0x21<<8)      +YF      +VF+NF   ,
+  (0x22<<8)      +YF      +VF+NF   ,
+  (0x23<<8)      +YF         +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x2A<<8)      +YF+HF+XF   +NF   ,
+  (0x2B<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2C<<8)      +YF+HF+XF   +NF   ,
+  (0x2D<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2E<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2F<<8)      +YF+HF+XF   +NF   ,
+  (0x30<<8)      +YF      +VF+NF   ,
+  (0x31<<8)      +YF         +NF   ,
+  (0x32<<8)      +YF         +NF   ,
+  (0x33<<8)      +YF      +VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x3A<<8)      +YF+HF+XF+VF+NF   ,
+  (0x3B<<8)      +YF+HF+XF   +NF   ,
+  (0x3C<<8)      +YF+HF+XF+VF+NF   ,
+  (0x3D<<8)      +YF+HF+XF   +NF   ,
+  (0x3E<<8)      +YF+HF+XF   +NF   ,
+  (0x3F<<8)      +YF+HF+XF+VF+NF   ,
+  (0x40<<8)                  +NF   ,
+  (0x41<<8)               +VF+NF   ,
+  (0x42<<8)               +VF+NF   ,
+  (0x43<<8)                  +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x4A<<8)         +HF+XF   +NF   ,
+  (0x4B<<8)         +HF+XF+VF+NF   ,
+  (0x4C<<8)         +HF+XF   +NF   ,
+  (0x4D<<8)         +HF+XF+VF+NF   ,
+  (0x4E<<8)         +HF+XF+VF+NF   ,
+  (0x4F<<8)         +HF+XF   +NF   ,
+  (0x50<<8)               +VF+NF   ,
+  (0x51<<8)                  +NF   ,
+  (0x52<<8)                  +NF   ,
+  (0x53<<8)               +VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x5A<<8)         +HF+XF+VF+NF   ,
+  (0x5B<<8)         +HF+XF   +NF   ,
+  (0x5C<<8)         +HF+XF+VF+NF   ,
+  (0x5D<<8)         +HF+XF   +NF   ,
+  (0x5E<<8)         +HF+XF   +NF   ,
+  (0x5F<<8)         +HF+XF+VF+NF   ,
+  (0x60<<8)      +YF      +VF+NF   ,
+  (0x61<<8)      +YF         +NF   ,
+  (0x62<<8)      +YF         +NF   ,
+  (0x63<<8)      +YF      +VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x6A<<8)      +YF+HF+XF+VF+NF   ,
+  (0x6B<<8)      +YF+HF+XF   +NF   ,
+  (0x6C<<8)      +YF+HF+XF+VF+NF   ,
+  (0x6D<<8)      +YF+HF+XF   +NF   ,
+  (0x6E<<8)      +YF+HF+XF   +NF   ,
+  (0x6F<<8)      +YF+HF+XF+VF+NF   ,
+  (0x70<<8)      +YF         +NF   ,
+  (0x71<<8)      +YF      +VF+NF   ,
+  (0x72<<8)      +YF      +VF+NF   ,
+  (0x73<<8)      +YF         +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x7A<<8)      +YF+HF+XF   +NF   ,
+  (0x7B<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7C<<8)      +YF+HF+XF   +NF   ,
+  (0x7D<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7E<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7F<<8)      +YF+HF+XF   +NF   ,
+  (0x80<<8)+SF               +NF   ,
+  (0x81<<8)+SF            +VF+NF   ,
+  (0x82<<8)+SF            +VF+NF   ,
+  (0x83<<8)+SF               +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x8A<<8)+SF      +HF+XF   +NF   ,
+  (0x8B<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8C<<8)+SF      +HF+XF   +NF   ,
+  (0x8D<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8E<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8F<<8)+SF      +HF+XF   +NF   ,
+  (0x90<<8)+SF            +VF+NF   ,
+  (0x91<<8)+SF               +NF   ,
+  (0x92<<8)+SF               +NF   ,
+  (0x93<<8)+SF            +VF+NF   ,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x3A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3B<<8)      +YF+HF+XF   +NF+CF,
+  (0x3C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3D<<8)      +YF+HF+XF   +NF+CF,
+  (0x3E<<8)      +YF+HF+XF   +NF+CF,
+  (0x3F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x4A<<8)         +HF+XF   +NF+CF,
+  (0x4B<<8)         +HF+XF+VF+NF+CF,
+  (0x4C<<8)         +HF+XF   +NF+CF,
+  (0x4D<<8)         +HF+XF+VF+NF+CF,
+  (0x4E<<8)         +HF+XF+VF+NF+CF,
+  (0x4F<<8)         +HF+XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x5A<<8)         +HF+XF+VF+NF+CF,
+  (0x5B<<8)         +HF+XF   +NF+CF,
+  (0x5C<<8)         +HF+XF+VF+NF+CF,
+  (0x5D<<8)         +HF+XF   +NF+CF,
+  (0x5E<<8)         +HF+XF   +NF+CF,
+  (0x5F<<8)         +HF+XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x6A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6B<<8)      +YF+HF+XF   +NF+CF,
+  (0x6C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6D<<8)      +YF+HF+XF   +NF+CF,
+  (0x6E<<8)      +YF+HF+XF   +NF+CF,
+  (0x6F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x7A<<8)      +YF+HF+XF   +NF+CF,
+  (0x7B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7C<<8)      +YF+HF+XF   +NF+CF,
+  (0x7D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7F<<8)      +YF+HF+XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x8A<<8)+SF      +HF+XF   +NF+CF,
+  (0x8B<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8C<<8)+SF      +HF+XF   +NF+CF,
+  (0x8D<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8E<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8F<<8)+SF      +HF+XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x9A<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x9B<<8)+SF      +HF+XF   +NF+CF,
+  (0x9C<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x9D<<8)+SF      +HF+XF   +NF+CF,
+  (0x9E<<8)+SF      +HF+XF   +NF+CF,
+  (0x9F<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xA0<<8)+SF   +YF      +VF+NF+CF,
+  (0xA1<<8)+SF   +YF         +NF+CF,
+  (0xA2<<8)+SF   +YF         +NF+CF,
+  (0xA3<<8)+SF   +YF      +VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xAA<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xAB<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAC<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xAD<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAE<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAF<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xB0<<8)+SF   +YF         +NF+CF,
+  (0xB1<<8)+SF   +YF      +VF+NF+CF,
+  (0xB2<<8)+SF   +YF      +VF+NF+CF,
+  (0xB3<<8)+SF   +YF         +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xBA<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xBB<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBC<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xBD<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBE<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBF<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xC0<<8)+SF            +VF+NF+CF,
+  (0xC1<<8)+SF               +NF+CF,
+  (0xC2<<8)+SF               +NF+CF,
+  (0xC3<<8)+SF            +VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xCA<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xCB<<8)+SF      +HF+XF   +NF+CF,
+  (0xCC<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xCD<<8)+SF      +HF+XF   +NF+CF,
+  (0xCE<<8)+SF      +HF+XF   +NF+CF,
+  (0xCF<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xD0<<8)+SF               +NF+CF,
+  (0xD1<<8)+SF            +VF+NF+CF,
+  (0xD2<<8)+SF            +VF+NF+CF,
+  (0xD3<<8)+SF               +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xDA<<8)+SF      +HF+XF   +NF+CF,
+  (0xDB<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDC<<8)+SF      +HF+XF   +NF+CF,
+  (0xDD<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDE<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDF<<8)+SF      +HF+XF   +NF+CF,
+  (0xE0<<8)+SF   +YF         +NF+CF,
+  (0xE1<<8)+SF   +YF      +VF+NF+CF,
+  (0xE2<<8)+SF   +YF      +VF+NF+CF,
+  (0xE3<<8)+SF   +YF         +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xEA<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xEB<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEC<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xED<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEE<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEF<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xF0<<8)+SF   +YF      +VF+NF+CF,
+  (0xF1<<8)+SF   +YF         +NF+CF,
+  (0xF2<<8)+SF   +YF         +NF+CF,
+  (0xF3<<8)+SF   +YF      +VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xFA<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xFB<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFC<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xFD<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFE<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFF<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0x00<<8)   +ZF         +VF+NF+CF,
+  (0x01<<8)                  +NF+CF,
+  (0x02<<8)                  +NF+CF,
+  (0x03<<8)               +VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x0A<<8)         +HF+XF+VF+NF+CF,
+  (0x0B<<8)         +HF+XF   +NF+CF,
+  (0x0C<<8)         +HF+XF+VF+NF+CF,
+  (0x0D<<8)         +HF+XF   +NF+CF,
+  (0x0E<<8)         +HF+XF   +NF+CF,
+  (0x0F<<8)         +HF+XF+VF+NF+CF,
+  (0x10<<8)                  +NF+CF,
+  (0x11<<8)               +VF+NF+CF,
+  (0x12<<8)               +VF+NF+CF,
+  (0x13<<8)                  +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x1A<<8)         +HF+XF   +NF+CF,
+  (0x1B<<8)         +HF+XF+VF+NF+CF,
+  (0x1C<<8)         +HF+XF   +NF+CF,
+  (0x1D<<8)         +HF+XF+VF+NF+CF,
+  (0x1E<<8)         +HF+XF+VF+NF+CF,
+  (0x1F<<8)         +HF+XF   +NF+CF,
+  (0x20<<8)      +YF         +NF+CF,
+  (0x21<<8)      +YF      +VF+NF+CF,
+  (0x22<<8)      +YF      +VF+NF+CF,
+  (0x23<<8)      +YF         +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x2A<<8)      +YF+HF+XF   +NF+CF,
+  (0x2B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2C<<8)      +YF+HF+XF   +NF+CF,
+  (0x2D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2F<<8)      +YF+HF+XF   +NF+CF,
+  (0x30<<8)      +YF      +VF+NF+CF,
+  (0x31<<8)      +YF         +NF+CF,
+  (0x32<<8)      +YF         +NF+CF,
+  (0x33<<8)      +YF      +VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x3A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3B<<8)      +YF+HF+XF   +NF+CF,
+  (0x3C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3D<<8)      +YF+HF+XF   +NF+CF,
+  (0x3E<<8)      +YF+HF+XF   +NF+CF,
+  (0x3F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x4A<<8)         +HF+XF   +NF+CF,
+  (0x4B<<8)         +HF+XF+VF+NF+CF,
+  (0x4C<<8)         +HF+XF   +NF+CF,
+  (0x4D<<8)         +HF+XF+VF+NF+CF,
+  (0x4E<<8)         +HF+XF+VF+NF+CF,
+  (0x4F<<8)         +HF+XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x5A<<8)         +HF+XF+VF+NF+CF,
+  (0x5B<<8)         +HF+XF   +NF+CF,
+  (0x5C<<8)         +HF+XF+VF+NF+CF,
+  (0x5D<<8)         +HF+XF   +NF+CF,
+  (0x5E<<8)         +HF+XF   +NF+CF,
+  (0x5F<<8)         +HF+XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x6A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6B<<8)      +YF+HF+XF   +NF+CF,
+  (0x6C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6D<<8)      +YF+HF+XF   +NF+CF,
+  (0x6E<<8)      +YF+HF+XF   +NF+CF,
+  (0x6F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x7A<<8)      +YF+HF+XF   +NF+CF,
+  (0x7B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7C<<8)      +YF+HF+XF   +NF+CF,
+  (0x7D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7F<<8)      +YF+HF+XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x8A<<8)+SF      +HF+XF   +NF+CF,
+  (0x8B<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8C<<8)+SF      +HF+XF   +NF+CF,
+  (0x8D<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8E<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8F<<8)+SF      +HF+XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF
+};
+
diff --git a/MCUME_pico2/picomsx/.DS_Store b/MCUME_pico2/picomsx/.DS_Store
new file mode 100644
index 0000000..34ebda6
Binary files /dev/null and b/MCUME_pico2/picomsx/.DS_Store differ
diff --git a/MCUME_pico2/picomsx/AY8910.c b/MCUME_pico2/picomsx/AY8910.c
new file mode 100644
index 0000000..8069ce6
--- /dev/null
+++ b/MCUME_pico2/picomsx/AY8910.c
@@ -0,0 +1,320 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.c                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.h for declarations.                              **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "AY8910.h"
+#include "Sound.h"
+#include <string.h>
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int First)
+{
+  static byte RegInit[16] =
+  {
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFD,
+    0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00
+  };
+  int J;
+
+  for(J=0;J<AY8910_CHANNELS;J++) D->Freq[J]=D->Volume[J]=0;
+  memcpy(D->R,RegInit,sizeof(D->R));
+  D->Phase[0]=D->Phase[1]=D->Phase[2]=0;
+  D->First   = First;
+  D->Sync    = AY8910_ASYNC;
+  D->Changed = 0x00;
+  D->EPeriod = 0;
+  D->ECount  = 0;
+  D->Latch   = 0x00;
+
+  /* Set sound types */
+  SetSound(0+First,SND_MELODIC);
+  SetSound(1+First,SND_MELODIC);
+  SetSound(2+First,SND_MELODIC);
+  SetSound(3+First,SND_NOISE);
+  SetSound(4+First,SND_NOISE);
+  SetSound(5+First,SND_NOISE);
+}
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V)
+{
+  D->Latch=V&0x0F;
+}
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V)
+{
+  Write8910(D,D->Latch,V);
+}
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D)
+{
+  return(D->R[D->Latch]);
+}
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V)
+{
+  register int J,I;
+
+  /* Exit if no change */
+  if((R>15)||((V==D->R[R])&&(R<8)&&(R>10))) return;
+
+  switch(R)
+  {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+    case 4:
+    case 5:
+      /* Write value */
+      D->R[R]=V;
+      /* Exit if the channel is silenced */
+      if(D->R[7]&(1<<(R>>1))) return;
+      /* Go to the first register in the pair */
+      R&=0xFE;
+      /* Compute frequency */
+      J=((int)(D->R[R+1]&0x0F)<<8)+D->R[R];
+      /* Compute channel number */
+      R>>=1;
+      /* Assign frequency */
+      D->Freq[R]=AY8910_BASE/(J+1);
+      /* Compute changed channels mask */
+      D->Changed|=1<<R;
+      break;
+
+    case 6:
+      /* Write value */
+      D->R[6]=V;
+      /* Exit if noise channels are silenced */
+      if(!(~D->R[7]&0x38)) return;
+      /* Compute and assign noise frequency */
+      J=AY8910_BASE/((V&0x1F)+1);
+      if(!(D->R[7]&0x08)) D->Freq[3]=J;
+      if(!(D->R[7]&0x10)) D->Freq[4]=J;
+      if(!(D->R[7]&0x20)) D->Freq[5]=J;
+      /* Compute changed channels mask */
+      D->Changed|=0x38&~D->R[7];
+      break;
+
+    case 7:
+      /* Find changed channels */
+      R=(V^D->R[7])&0x3F;
+      D->Changed|=R;
+      /* Write value */
+      D->R[7]=V;
+      /* Update frequencies */
+      for(J=0;R&&(J<AY8910_CHANNELS);J++,R>>=1,V>>=1)
+        if(R&1)
+        {
+          if(V&1) D->Freq[J]=0;
+          else
+          {
+            I=J<3? (((int)(D->R[J*2+1]&0x0F)<<8)+D->R[J*2]):(D->R[6]&0x1F);
+            D->Freq[J]=AY8910_BASE/(I+1);
+          }
+        }
+      break;
+      
+    case 8:
+    case 9:
+    case 10:
+      /* Write value */
+      D->R[R]=V;
+      /* Compute channel number */
+      R-=8;
+      /* Compute and assign new volume */
+      D->Volume[R+3]=D->Volume[R]=
+        V&0x10? (V&0x04? 0:255):255*(V&0x0F)/15;
+      /* Start/stop envelope */
+      D->Phase[R]=V&0x10? 1:0;
+      /* Compute changed channels mask */
+      D->Changed|=(0x09<<R)&~D->R[7];
+      break;
+
+    case 11:
+    case 12:
+      /* Write value */
+      D->R[R]=V;
+      /* Compute frequency */
+      J=((int)D->R[12]<<8)+D->R[11]+1;
+      D->EPeriod=1000*(J<<4)/AY8910_BASE;
+      D->ECount=0;
+      /* No channels changed */
+      return;
+
+    case 13:
+    case 14:
+    case 15:
+      /* Write value */
+      D->R[R]=V;
+      /* No channels changed */
+      return;
+
+    default:
+      /* Wrong register, do nothing */
+      return;
+  }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS)
+{
+  register int J,I,Step;
+
+  /* Exit if no envelope running */
+  if(!D->EPeriod) return;
+
+  /* Count milliseconds */
+  D->ECount+=mS;
+  if(D->ECount<D->EPeriod) return;
+
+  /* By how much do we change volume? */
+  Step=(D->ECount<<8)/D->EPeriod;
+
+  /* Count the remaining milliseconds */
+  D->ECount%=D->EPeriod;
+
+  for(J=0;J<3;J++)
+    if(D->Phase[J]&&(D->R[J+8]&0x10))
+      switch(D->R[13]&0x0F)
+      {
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+        case 9:
+          I=D->Volume[J]-Step;
+          D->Volume[J+3]=D->Volume[J]=I=I>=0? I:0;
+          if(!I) D->Phase[J]=0;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 4:
+        case 5:
+        case 6:
+        case 7:
+          I=D->Volume[J]+Step;
+          D->Volume[J+3]=D->Volume[J]=I=I<256? I:0;
+          if(!I) D->Phase[J]=0;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 8:
+          I=D->Volume[J]-Step;
+          D->Volume[J+3]=D->Volume[J]=I>=0? I:255;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 10:
+          if(D->Phase[J]==2)
+          {
+            I=D->Volume[J]+Step;
+            D->Volume[J+3]=D->Volume[J]=I=I<256? I:255;
+            if(I==255) D->Phase[J]=1;
+          }
+          else
+          {
+            I=D->Volume[J]-Step;
+            D->Volume[J+3]=D->Volume[J]=I=I>=0? I:0;
+            if(!I) D->Phase[J]=2;
+          }
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 11:
+          I=D->Volume[J]-Step;
+          D->Volume[J+3]=D->Volume[J]=I=I>=0? I:255;
+          if(I==255) D->Phase[J]=0;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 12:
+          I=D->Volume[J]+Step;
+          D->Volume[J+3]=D->Volume[J]=I<256? I:0;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break; 
+        case 13:
+        case 15:
+          I=D->Volume[J]+Step;
+          D->Volume[J+3]=D->Volume[J]=I<256? I:255;
+          if(I==255) D->Phase[J]=0;
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+        case 14:
+          if(D->Phase[J]==2)
+          {
+            I=D->Volume[J]-Step;
+            D->Volume[J+3]=D->Volume[J]=I=I>=0? I:0;
+            if(!I) D->Phase[J]=1;
+          }
+          else
+          {
+            I=D->Volume[J]+Step;
+            D->Volume[J+3]=D->Volume[J]=I=I<256? I:255;
+            if(I==255) D->Phase[J]=2;
+          }
+          D->Changed|=(0x09<<J)&~D->R[7];
+          break;
+      }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync)
+{
+  register int J,I;
+
+  /* Hit MIDI drums for noise channels, if requested */
+  if(Sync&AY8910_DRUMS)
+  {
+    Sync&=~AY8910_DRUMS;
+    J=0;
+    if(D->Volume[3]&&D->Freq[3]) J+=D->Volume[3];
+    if(D->Volume[4]&&D->Freq[4]) J+=D->Volume[4];
+    if(D->Volume[5]&&D->Freq[5]) J+=D->Volume[5];
+    if(J) Drum(DRM_MIDI|28,(J+2)/3);
+  }
+
+  if(Sync!=AY8910_FLUSH) D->Sync=Sync;
+
+  for(J=0,I=D->Changed;I&&(J<AY8910_CHANNELS);J++,I>>=1)
+    if(I&1) Sound(J+D->First,D->Freq[J],D->Volume[J]);
+
+  D->Changed=0x00;
+}
diff --git a/MCUME_pico2/picomsx/AY8910.h b/MCUME_pico2/picomsx/AY8910.h
new file mode 100644
index 0000000..66a843a
--- /dev/null
+++ b/MCUME_pico2/picomsx/AY8910.h
@@ -0,0 +1,91 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.h                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.c for the actual code.                           **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef AY8910_H
+#define AY8910_H
+
+#define AY8910_BASE     111861 /* Base frequency for AY8910  */
+#define AY8910_CHANNELS 6      /* 3 melodic + 3 noise chanls */
+
+#define AY8910_ASYNC    0      /* Asynchronous emulation     */
+#define AY8910_SYNC     1      /* Synchronous emulation      */
+#define AY8910_FLUSH    2      /* Flush buffers only         */
+#define AY8910_DRUMS    0x80   /* Hit drums for noise chnls  */
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** AY8910 ***************************************************/
+/** This data structure stores AY8910 state.                **/
+/*************************************************************/
+typedef struct
+{
+  byte R[16];                  /* PSG registers contents     */
+  int Freq[AY8910_CHANNELS];   /* Frequencies (0 for off)    */
+  int Volume[AY8910_CHANNELS]; /* Volumes (0..255)           */
+  int First;                   /* First used Sound() channel */
+  byte Changed;                /* Bitmap of changed channels */
+  byte Sync;                   /* AY8910_SYNC/AY8910_ASYNC   */
+  byte Latch;                  /* Latch for the register num */
+  int EPeriod;                 /* Envelope step in msecs     */
+  int ECount;                  /* Envelope step counter      */
+  byte Phase[3];               /* Envelope phase (0 for off) */
+} AY8910;
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int First);
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V);
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V);
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V);
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D);
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync);
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS);
+
+#endif /* AY8910_H */
diff --git a/MCUME_pico2/picomsx/Boot.c b/MCUME_pico2/picomsx/Boot.c
new file mode 100644
index 0000000..29b4a1c
--- /dev/null
+++ b/MCUME_pico2/picomsx/Boot.c
@@ -0,0 +1,47 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                          Boot.h                         **/
+/**                                                         **/
+/** This file contains MSX boot sector image used to create **/
+/** new disk images during FORMAT operation.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+const unsigned char BootBlock[] =
+{
+  0xEB,0xFE,0x90,0x56,0x46,0x42,0x2D,0x31,0x39,0x38,0x39,0x00,0x02,0x02,0x01,0x00,
+  0x02,0x70,0x00,0xA0,0x05,0xF9,0x03,0x00,0x09,0x00,0x02,0x00,0x00,0x00,0xD0,0xED,
+  0x53,0x58,0xC0,0x32,0xC2,0xC0,0x36,0x55,0x23,0x36,0xC0,0x31,0x1F,0xF5,0x11,0x9D,
+  0xC0,0x0E,0x0F,0xCD,0x7D,0xF3,0x3C,0x28,0x28,0x11,0x00,0x01,0x0E,0x1A,0xCD,0x7D,
+  0xF3,0x21,0x01,0x00,0x22,0xAB,0xC0,0x21,0x00,0x3F,0x11,0x9D,0xC0,0x0E,0x27,0xCD,
+  0x7D,0xF3,0xC3,0x00,0x01,0x57,0xC0,0xCD,0x00,0x00,0x79,0xE6,0xFE,0xFE,0x02,0x20,
+  0x07,0x3A,0xC2,0xC0,0xA7,0xCA,0x22,0x40,0x11,0x77,0xC0,0x0E,0x09,0xCD,0x7D,0xF3,
+  0x0E,0x07,0xCD,0x7D,0xF3,0x18,0xB4,0x42,0x6F,0x6F,0x74,0x20,0x65,0x72,0x72,0x6F,
+  0x72,0x0D,0x0A,0x50,0x72,0x65,0x73,0x73,0x20,0x61,0x6E,0x79,0x20,0x6B,0x65,0x79,
+  0x20,0x66,0x6F,0x72,0x20,0x72,0x65,0x74,0x72,0x79,0x0D,0x0A,0x24,0x00,0x4D,0x53,
+  0x58,0x44,0x4F,0x53,0x20,0x20,0x53,0x59,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF3,0x2A,
+  0x51,0xF3,0x11,0x00,0x01,0x19,0x01,0x00,0x01,0x11,0x00,0xC1,0xED,0xB0,0x3A,0xEE,
+  0xC0,0x47,0x11,0xEF,0xC0,0x21,0x00,0x00,0xCD,0x51,0x52,0xF3,0x76,0xC9,0x18,0x64,
+  0x3A,0xAF,0x80,0xF9,0xCA,0x6D,0x48,0xD3,0xA5,0x0C,0x8C,0x2F,0x9C,0xCB,0xE9,0x89,
+  0xD2,0x00,0x32,0x26,0x40,0x94,0x61,0x19,0x20,0xE6,0x80,0x6D,0x8A,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+};
diff --git a/MCUME_pico2/picomsx/Boot.h b/MCUME_pico2/picomsx/Boot.h
new file mode 100644
index 0000000..f2e883a
--- /dev/null
+++ b/MCUME_pico2/picomsx/Boot.h
@@ -0,0 +1,13 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                          Boot.h                         **/
+/**                                                         **/
+/** This file contains MSX boot sector image used to create **/
+/** new disk images during FORMAT operation.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+extern const byte BootBlock[];
diff --git a/MCUME_pico2/picomsx/Codes.h b/MCUME_pico2/picomsx/Codes.h
new file mode 100644
index 0000000..bf8dcce
--- /dev/null
+++ b/MCUME_pico2/picomsx/Codes.h
@@ -0,0 +1,385 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Codes.h                        **/
+/**                                                         **/
+/** This file contains implementation for the main table of **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->HL.B.h);break;
+case ADD_L:    M_ADD(R->HL.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
+case ADD_BYTE: I=RdZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->HL.B.h);break;
+case SUB_L:    M_SUB(R->HL.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
+case SUB_BYTE: I=RdZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->HL.B.h);break;
+case AND_L:    M_AND(R->HL.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
+case AND_BYTE: I=RdZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->HL.B.h);break;
+case OR_L:     M_OR(R->HL.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
+case OR_BYTE:  I=RdZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->HL.B.h);break;
+case ADC_L:    M_ADC(R->HL.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
+case ADC_BYTE: I=RdZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->HL.B.h);break;
+case SBC_L:    M_SBC(R->HL.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
+case SBC_BYTE: I=RdZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->HL.B.h);break;
+case XOR_L:    M_XOR(R->HL.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
+case XOR_BYTE: I=RdZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->HL.B.h);break;
+case CP_L:     M_CP(R->HL.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
+case CP_BYTE:  I=RdZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(HL);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->HL.W;break;
+case LD_SP_HL: R->SP.W=R->HL.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(HL,BC);break;
+case ADD_HL_DE:  M_ADDW(HL,DE);break;
+case ADD_HL_HL:  M_ADDW(HL,HL);break;
+case ADD_HL_SP:  M_ADDW(HL,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->HL.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->HL.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->HL.B.h);break;
+case DEC_L:    M_DEC(R->HL.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->HL.B.h);break;
+case INC_L:    M_INC(R->HL.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+
+case RLCA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(HL);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(HL);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=RdZ80(R->PC.W++);OutZ80(I,R->AF.B.h);break;
+case INA:  I=RdZ80(R->PC.W++);R->AF.B.h=InZ80(I);break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
+case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
+case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
+case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
+case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
+case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
+case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
+case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
+case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
+case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
+case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
+case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
+case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
+case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
+case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
+case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
+case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
+case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
+case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
+case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
+
+case LD_B_BYTE:   R->BC.B.h=RdZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=RdZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=RdZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=RdZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->HL.B.h=RdZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->HL.B.l=RdZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=RdZ80(R->PC.W++);break;
+case LD_xHL_BYTE: WrZ80(R->HL.W,RdZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++); 
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
+  R->HL.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
+
+default:
+  if(R->TrapBadOps)
+    printf
+    (
+      "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
+      (long)R->User,RdZ80(R->PC.W-1),R->PC.W-1
+    );
+  break;
diff --git a/MCUME_pico2/picomsx/CodesCB.h b/MCUME_pico2/picomsx/CodesCB.h
new file mode 100644
index 0000000..966a582
--- /dev/null
+++ b/MCUME_pico2/picomsx/CodesCB.h
@@ -0,0 +1,204 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesCB.h                       **/
+/**                                                         **/
+/** This file contains implementation for the CB table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
+case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
+case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
+case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
+case RLC_A: M_RLC(R->AF.B.h);break;
+
+case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
+case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
+case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
+case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
+case RRC_A: M_RRC(R->AF.B.h);break;
+
+case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
+case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
+case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
+case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
+case RL_A: M_RL(R->AF.B.h);break;
+
+case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
+case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
+case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
+case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
+case RR_A: M_RR(R->AF.B.h);break;
+
+case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
+case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
+case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
+case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
+case SLA_A: M_SLA(R->AF.B.h);break;
+
+case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
+case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
+case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
+case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
+case SRA_A: M_SRA(R->AF.B.h);break;
+
+case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
+case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
+case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
+case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
+case SLL_A: M_SLL(R->AF.B.h);break;
+
+case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
+case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
+case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
+case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
+case SRL_A: M_SRL(R->AF.B.h);break;
+    
+case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
+case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
+case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
+case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,R->AF.B.h);break;
+
+case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
+case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
+case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
+case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,R->AF.B.h);break;
+
+case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
+case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
+case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
+case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,R->AF.B.h);break;
+
+case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
+case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
+case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
+case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,R->AF.B.h);break;
+
+case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
+case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
+case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
+case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,R->AF.B.h);break;
+
+case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
+case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
+case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
+case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,R->AF.B.h);break;
+
+case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
+case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
+case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
+case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,R->AF.B.h);break;
+
+case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
+case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
+case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
+case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,R->AF.B.h);break;
+
+case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
+case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
+case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
+case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
+case RES0_A: M_RES(0,R->AF.B.h);break;
+
+case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
+case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
+case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
+case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
+case RES1_A: M_RES(1,R->AF.B.h);break;
+
+case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
+case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
+case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
+case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
+case RES2_A: M_RES(2,R->AF.B.h);break;
+
+case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
+case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
+case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
+case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
+case RES3_A: M_RES(3,R->AF.B.h);break;
+
+case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
+case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
+case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
+case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
+case RES4_A: M_RES(4,R->AF.B.h);break;
+
+case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
+case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
+case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
+case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
+case RES5_A: M_RES(5,R->AF.B.h);break;
+
+case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
+case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
+case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
+case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
+case RES6_A: M_RES(6,R->AF.B.h);break;
+
+case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
+case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
+case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
+case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
+case RES7_A: M_RES(7,R->AF.B.h);break;
+
+case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
+case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
+case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
+case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
+case SET0_A: M_SET(0,R->AF.B.h);break;
+
+case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
+case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
+case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
+case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
+case SET1_A: M_SET(1,R->AF.B.h);break;
+
+case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
+case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
+case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
+case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
+case SET2_A: M_SET(2,R->AF.B.h);break;
+
+case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
+case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
+case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
+case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
+case SET3_A: M_SET(3,R->AF.B.h);break;
+
+case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
+case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
+case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
+case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
+case SET4_A: M_SET(4,R->AF.B.h);break;
+
+case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
+case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
+case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
+case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
+case SET5_A: M_SET(5,R->AF.B.h);break;
+
+case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
+case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
+case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
+case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
+case SET6_A: M_SET(6,R->AF.B.h);break;
+
+case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
+case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
+case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
+case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
+case SET7_A: M_SET(7,R->AF.B.h);break;
diff --git a/MCUME_pico2/picomsx/CodesED.h b/MCUME_pico2/picomsx/CodesED.h
new file mode 100644
index 0000000..b10362a
--- /dev/null
+++ b/MCUME_pico2/picomsx/CodesED.h
@@ -0,0 +1,304 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesED.h                       **/
+/**                                                         **/
+/** This file contains implementation for the ED table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+/** This is a special patch for emulating BIOS calls: ********/
+case DB_FE:     PatchZ80(R);break;
+/*************************************************************/
+
+case ADC_HL_BC: M_ADCW(BC);break;
+case ADC_HL_DE: M_ADCW(DE);break;
+case ADC_HL_HL: M_ADCW(HL);break;
+case ADC_HL_SP: M_ADCW(SP);break;
+
+case SBC_HL_BC: M_SBCW(BC);break;
+case SBC_HL_DE: M_SBCW(DE);break;
+case SBC_HL_HL: M_SBCW(HL);break;
+case SBC_HL_SP: M_SBCW(SP);break;
+
+case LD_xWORDe_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+case LD_xWORDe_DE:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->DE.B.l);
+  WrZ80(J.W,R->DE.B.h);
+  break;
+case LD_xWORDe_BC:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->BC.B.l);
+  WrZ80(J.W,R->BC.B.h);
+  break;
+case LD_xWORDe_SP:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->SP.B.l);
+  WrZ80(J.W,R->SP.B.h);
+  break;
+
+case LD_HL_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+case LD_DE_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->DE.B.l=RdZ80(J.W++);
+  R->DE.B.h=RdZ80(J.W);
+  break;
+case LD_BC_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->BC.B.l=RdZ80(J.W++);
+  R->BC.B.h=RdZ80(J.W);
+  break;
+case LD_SP_xWORDe:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->SP.B.l=RdZ80(J.W++);
+  R->SP.B.h=RdZ80(J.W);
+  break;
+
+case RRD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I>>4)|(R->AF.B.h<<4);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+case RLD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+
+case LD_A_I:
+  R->AF.B.h=R->I;
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_A_R:
+  R->R++;
+  R->AF.B.h=(byte)(R->R-R->ICount);
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_I_A:   R->I=R->AF.B.h;break;
+case LD_R_A:   break;
+
+case IM_0:     R->IFF&=~(IFF_IM1|IFF_IM2);break;
+case IM_1:     R->IFF=(R->IFF&~IFF_IM2)|IFF_IM1;break;
+case IM_2:     R->IFF=(R->IFF&~IFF_IM1)|IFF_IM2;break;
+
+case RETI:     M_RET;break;
+case RETN:     if(R->IFF&IFF_2) R->IFF|=IFF_1; else R->IFF&=~IFF_1;
+               M_RET;break;
+
+case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+
+case IN_B_xC:  M_IN(R->BC.B.h);break;
+case IN_C_xC:  M_IN(R->BC.B.l);break;
+case IN_D_xC:  M_IN(R->DE.B.h);break;
+case IN_E_xC:  M_IN(R->DE.B.l);break;
+case IN_H_xC:  M_IN(R->HL.B.h);break;
+case IN_L_xC:  M_IN(R->HL.B.l);break;
+case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_F_xC:  M_IN(J.B.l);break;
+
+case OUT_xC_B: OutZ80(R->BC.B.l,R->BC.B.h);break;
+case OUT_xC_C: OutZ80(R->BC.B.l,R->BC.B.l);break;
+case OUT_xC_D: OutZ80(R->BC.B.l,R->DE.B.h);break;
+case OUT_xC_E: OutZ80(R->BC.B.l,R->DE.B.l);break;
+case OUT_xC_H: OutZ80(R->BC.B.l,R->HL.B.h);break;
+case OUT_xC_L: OutZ80(R->BC.B.l,R->HL.B.l);break;
+case OUT_xC_A: OutZ80(R->BC.B.l,R->AF.B.h);break;
+
+case INI:
+  WrZ80(R->HL.W++,InZ80(R->BC.B.l));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INIR:
+  do
+  {
+    WrZ80(R->HL.W++,InZ80(R->BC.B.l));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case IND:
+  WrZ80(R->HL.W--,InZ80(R->BC.B.l));
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INDR:
+  do
+  {
+    WrZ80(R->HL.W--,InZ80(R->BC.B.l));
+    R->BC.B.h--;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTI:
+  I=RdZ80(R->HL.W++);
+  OutZ80(R->BC.B.l,I);
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    OutZ80(R->BC.B.l,I);
+    R->BC.B.h--;
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case OUTD:
+  I=RdZ80(R->HL.W--);
+  OutZ80(R->BC.B.l,I);
+  R->BC.B.h--;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    OutZ80(R->BC.B.l,I);
+    R->BC.B.h--;
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case LDI:
+  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+  R->BC.W--;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDIR:
+  do
+  {
+    WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case LDD:
+  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+  R->BC.W--;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDDR:
+  do
+  {
+    WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case CPI:
+  I=RdZ80(R->HL.W++);
+  J.B.l=R->AF.B.h-I;
+  R->BC.W--;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    J.B.l=R->AF.B.h-I;
+    R->BC.W--;R->ICount-=21;
+  }  
+  while(R->BC.W&&J.B.l&&(R->ICount>0));
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;  
+
+case CPD:
+  I=RdZ80(R->HL.W--);
+  J.B.l=R->AF.B.h-I;
+  R->BC.W--;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    J.B.l=R->AF.B.h-I;
+    R->BC.W--;R->ICount-=21;
+  }
+  while(R->BC.W&&J.B.l);
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;
diff --git a/MCUME_pico2/picomsx/CodesXCB.h b/MCUME_pico2/picomsx/CodesXCB.h
new file mode 100644
index 0000000..76e96fa
--- /dev/null
+++ b/MCUME_pico2/picomsx/CodesXCB.h
@@ -0,0 +1,64 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXCB.h                      **/
+/**                                                         **/
+/** This file contains implementation for FD/DD-CB tables   **/
+/** of Z80 commands. It is included from Z80.c.             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
+case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
+case RL_xHL:  I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
+case RR_xHL:  I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
+case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
+case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
+case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
+case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
+
+case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
+case BIT0_H: case BIT0_L: case BIT0_A:
+case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
+case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
+case BIT1_H: case BIT1_L: case BIT1_A:
+case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
+case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
+case BIT2_H: case BIT2_L: case BIT2_A:
+case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
+case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
+case BIT3_H: case BIT3_L: case BIT3_A:
+case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
+case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
+case BIT4_H: case BIT4_L: case BIT4_A:
+case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
+case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
+case BIT5_H: case BIT5_L: case BIT5_A:
+case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
+case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
+case BIT6_H: case BIT6_L: case BIT6_A:
+case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
+case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
+case BIT7_H: case BIT7_L: case BIT7_A:
+case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
+
+case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
+case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;   
+case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;   
+case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;   
+case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;   
+case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;   
+case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;   
+case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;   
+
+case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;   
+case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break; 
+case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break; 
+case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break; 
+case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break; 
+case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break; 
+case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break; 
+case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break; 
diff --git a/MCUME_pico2/picomsx/CodesXX.h b/MCUME_pico2/picomsx/CodesXX.h
new file mode 100644
index 0000000..5bf2812
--- /dev/null
+++ b/MCUME_pico2/picomsx/CodesXX.h
@@ -0,0 +1,396 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXX.h                       **/
+/**                                                         **/
+/** This file contains implementation for FD/DD tables of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->XX.B.h);break;
+case ADD_L:    M_ADD(R->XX.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_ADD(I);break;
+case ADD_BYTE: I=RdZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->XX.B.h);break;
+case SUB_L:    M_SUB(R->XX.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_SUB(I);break;
+case SUB_BYTE: I=RdZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->XX.B.h);break;
+case AND_L:    M_AND(R->XX.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_AND(I);break;
+case AND_BYTE: I=RdZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->XX.B.h);break;
+case OR_L:     M_OR(R->XX.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_OR(I);break;
+case OR_BYTE:  I=RdZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->XX.B.h);break;
+case ADC_L:    M_ADC(R->XX.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_ADC(I);break;
+case ADC_BYTE: I=RdZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->XX.B.h);break;
+case SBC_L:    M_SBC(R->XX.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_SBC(I);break;
+case SBC_BYTE: I=RdZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->XX.B.h);break;
+case XOR_L:    M_XOR(R->XX.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_XOR(I);break;
+case XOR_BYTE: I=RdZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->XX.B.h);break;
+case CP_L:     M_CP(R->XX.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));
+               M_CP(I);break;
+case CP_BYTE:  I=RdZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(XX);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->XX.W;break;
+case LD_SP_HL: R->SP.W=R->XX.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(XX,BC);break;
+case ADD_HL_DE:  M_ADDW(XX,DE);break;
+case ADD_HL_HL:  M_ADDW(XX,XX);break;
+case ADD_HL_SP:  M_ADDW(XX,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->XX.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->XX.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->XX.B.h);break;
+case DEC_L:    M_DEC(R->XX.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
+               WrZ80(R->XX.W+(offset)RdZ80(R->PC.W++),I);
+               break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->XX.B.h);break;
+case INC_L:    M_INC(R->XX.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
+               WrZ80(R->XX.W+(offset)RdZ80(R->PC.W++),I);
+               break;
+
+case RLCA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(XX);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(XX);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: OutZ80(RdZ80(R->PC.W++),R->AF.B.h);break;
+case INA:  R->AF.B.h=InZ80(RdZ80(R->PC.W++));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
+case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
+case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
+case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
+case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
+case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
+case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
+case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
+case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
+case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
+case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
+case LD_xHL_H: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
+case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
+case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
+case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
+case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
+case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
+case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
+case LD_xHL_L: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
+case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+               WrZ80(J.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W++));break;
+
+case LD_B_BYTE:   R->BC.B.h=RdZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=RdZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=RdZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=RdZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->XX.B.h=RdZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->XX.B.l=RdZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=RdZ80(R->PC.W++);break;
+case LD_xHL_BYTE: J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+                  WrZ80(J.W,RdZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W++,R->XX.B.l);
+  WrZ80(J.W,R->XX.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->XX.B.l=RdZ80(J.W++);
+  R->XX.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=RdZ80(R->PC.W++);
+  J.B.h=RdZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
+  R->XX.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
diff --git a/MCUME_pico2/picomsx/Disk.c b/MCUME_pico2/picomsx/Disk.c
new file mode 100644
index 0000000..1949ee6
--- /dev/null
+++ b/MCUME_pico2/picomsx/Disk.c
@@ -0,0 +1,96 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                          Disk.c                         **/
+/**                                                         **/
+/** This file contains standard disk access drivers working **/
+/** with disk images from files.                            **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#include "MSX.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+
+#ifdef __BORLANDC__
+#include <io.h>
+#endif
+
+#ifdef UNIX
+#include <unistd.h>
+#endif
+
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
+static int Drives[2] = { -1,-1 };        /* Disk image files */
+static int RdOnly[2];                    /* 1 = read-only    */ 
+
+/** DiskPresent() ********************************************/
+/** Return 1 if disk drive with a given ID is present.      **/
+/*************************************************************/
+byte DiskPresent(byte ID)
+{
+  return((ID<MAXDRIVES)&&(Drives[ID]>=0));
+}
+
+/** DiskRead() ***********************************************/
+/** Read requested sector from the drive into a buffer.     **/
+/*************************************************************/
+byte DiskRead(byte ID,byte *Buf,int N)
+{
+#ifdef unused  
+  if((ID<MAXDRIVES)&&(Drives[ID]>=0))
+    if(lseek(Drives[ID],N*512L,0)==N*512L)
+      return(read(Drives[ID],Buf,512)==512);
+#endif    
+  return(0);
+}
+
+/** DiskWrite() **********************************************/
+/** Write contents of the buffer into a given sector of the **/
+/** disk.                                                   **/
+/*************************************************************/
+byte DiskWrite(byte ID,byte *Buf,int N)
+{
+#ifdef unused  
+  if((ID<MAXDRIVES)&&(Drives[ID]>=0)&&!RdOnly[ID])
+    if(lseek(Drives[ID],N*512L,0)==N*512L)
+      return(write(Drives[ID],Buf,512)==512);
+#endif    
+  return(0);
+}
+
+/** ChangeDisk() *********************************************/
+/** Change disk image in a given drive. Closes current disk **/
+/** image if Name=0 was given. Returns 1 on success or 0 on **/
+/** failure.                                                **/
+/*************************************************************/
+byte ChangeDisk(byte ID,char *Name)
+{
+#ifdef unused  
+  /* We only have MAXDRIVES drives */
+  if(ID>=MAXDRIVES) return(0);
+  /* Close previous disk image */
+  if(Drives[ID]>=0) { close(Drives[ID]);Drives[ID]=-1; }
+  /* If no disk image given, consider drive empty */
+  if(!Name) return(1);
+  /* Open new disk image */
+  Drives[ID]=open(Name,O_RDWR|O_BINARY);
+  RdOnly[ID]=0;
+  /* If failed to open for writing, open read-only */
+  if(Drives[ID]<0)
+  {
+    Drives[ID]=open(Name,O_RDONLY|O_BINARY);
+    RdOnly[ID]=1;
+  }
+#endif  
+  /* Return operation result */
+  return(Drives[ID]>=0);
+}
diff --git a/MCUME_pico2/picomsx/DiskUtil.h b/MCUME_pico2/picomsx/DiskUtil.h
new file mode 100644
index 0000000..1708cb0
--- /dev/null
+++ b/MCUME_pico2/picomsx/DiskUtil.h
@@ -0,0 +1,95 @@
+/*************************************************************/
+/**                                                         **/
+/**                diskwork.h                               **/
+/**                                                         **/
+/** Common definitions for programs working with            **/
+/**   disk-images that can be used with fMSX                **/
+/**                                                         **/
+/**                                                         **/
+/** Copyright (c) Arnold Metselaar 1996                     **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
+#define usint unsigned short int
+#define byte unsigned char
+
+#define EOF_FAT 0xFFF /* signals EOF in FAT */
+
+typedef struct de {
+  char d_fname[8];
+  char d_ext[3];
+  char d_attrib;
+  char d_reserv[10]; /* unused */
+  byte d_time[2];     /* byte-ordering of ints is machine-dependent */
+  byte d_date[2];
+  byte d_first[2];
+  byte d_size[4];
+} DirEntry;
+
+/* macros to change DirEntries */
+#define setsh(x,y) {x[0]=y;x[1]=y>>8;}
+#define setlg(x,y) {x[0]=y;x[1]=y>>8;x[2]=y>>16;x[3]=y>>24;}
+
+/* macros to read DirEntries */
+#define rdsh(x) (x[0]+(x[1]<<8))
+#define rdlg(x) (x[0]+(x[1]<<8)+(x[2]<<16)+(x[3]<<24))
+
+#define PError(x) { fprintf(stderr,"%s: ",progname); perror(x); }
+
+#define seclen 512   /* length of sector */
+#define cluslen 1024 /* length of cluster */
+
+void *xalloc(size_t len)
+{ 
+  void *p;
+
+  if (!(p=malloc(len))) 
+    {
+      puts("Out of memory\n"); exit(2);
+    }
+  return p;
+}
+
+extern byte *FAT;
+
+/* read FAT-entry from FAT in memory */
+usint ReadFAT(usint clnr)
+{ register byte *P;
+
+  P=FAT+(clnr*3)/2;
+  return (clnr&1)? (P[0]>>4)+(P[1]<<4) : P[0]+((P[1]&0x0F)<<8);
+}
+
+/* write an entry to FAT in memory */
+void WriteFAT(usint clnr, usint val)
+{ register byte *P;
+
+  P=FAT+(clnr*3)/2;
+  if (clnr&1)
+    { 
+      P[0]=(P[0]&0x0F)+(val<<4);
+      P[1]=val>>4;
+    }
+  else
+    {
+      P[0]=val;
+      P[1]=(P[1]&0xF0)+((val>>8)&0x0F);
+    }
+}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/MCUME_pico2/picomsx/I8251.c b/MCUME_pico2/picomsx/I8251.c
new file mode 100644
index 0000000..fbd4c45
--- /dev/null
+++ b/MCUME_pico2/picomsx/I8251.c
@@ -0,0 +1,196 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         I8251.c                         **/
+/**                                                         **/
+/** This file contains emulation for the Intel 8251 UART    **/
+/** chip and the 8253 timer chip implementing a generic     **/
+/** RS232 interface.                                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2004-2005                 **/
+/**               Maarten ter Huurne 2000                   **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "I8251.h"
+
+/** Reset8251 ************************************************/
+/** Reset 8251 chip, assigning In and Out to the input and  **/
+/** output streams.                                         **/
+/*************************************************************/
+void Reset8251(register I8251 *D,FILE *In,FILE *Out)
+{
+  D->IRQMask = 0x0F;  /* All interrupts on */
+  D->IRQs    = 0x00;  /* No interrupts yet */
+  D->Mode    = 1;     /* Setting mode next */
+  D->Flow    = 0x00;  /* Flow control off  */
+  D->NextChr = -1;    /* No data yet       */
+
+  /* Assign input and output streams */
+  D->In      = In? In:stdin;
+  D->Out     = Out? Out:stdout;
+}
+
+/** Rd8251 ***************************************************/
+/** Read a byte from a given 8251 register. All values of R **/
+/** will be truncated to 3 bits as there are only 8 regs.   **/
+/*************************************************************/
+byte Rd8251(register I8251 *D,register byte R)
+{
+  register int J;
+
+  /* We only have 8 addressable ports */
+  R&=0x07;
+
+  switch(R)
+  {
+    case 0: /* Data */
+      if(D->Flow)
+      {
+        if(D->NextChr<0) D->NextChr=fgetc(D->In);
+        J=D->NextChr;
+        D->NextChr=-1;
+        return((J<0? 0xFF:J)&((0x20<<((D->Control&0x0C)>>2))-1));
+      }
+      return(0xFF);
+
+    case 1: /* Status */
+      if(D->NextChr<0) D->NextChr=fgetc(D->In);
+      return(D->Flow&&(D->NextChr>=0)? 0x87:0x85);
+      /*
+      76543210
+      1.......  data set ready (dsr)
+      .1......  sync detect, sync only
+      ..1.....  framing error (fe), async only
+      ...1....  overrun error (oe)
+      ....1...  parity error (pe)
+      .....1..  transmitter empty
+      ......1.  receiver ready
+      .......1  transmitter ready
+      
+      D->Flow is checked first, so that stdin input doesn't block
+      fMSX until it's actually being read by the emulated MSX.
+      */
+
+    case 0x82: /* Status of CTS, timer/counter 2, RI and CD */
+      return(0x7F);
+      /*
+      76543210
+      1.......  CTS (Clear To Send) 0=asserted
+      .1......  timer/counter output-2 from 8253
+      ..XXXX..  reserved
+      ......1.  RI (Ring Indicator) 0=asserted
+      .......1  CD (Carrier Detect) 0=asserted
+
+      RI and CD are optional. If only one of them is implemented,
+      it must be CD. Implemented like this:
+      - CTS always returns 0 (asserted)
+      - Everything else is not implemented
+      */
+  }
+
+  /* Other RS232 ports:
+  3: not standardised    -  unused
+  4: 8253 counter 0      -  not implemented
+  5: 8253 counter 1      -  not implemented
+  6: 8253 counter 2      -  not implemented
+  7: 8253 mode register  -  write only
+  */
+
+  return(0xFF); 
+}
+
+/** Wr8251 ***************************************************/
+/** Write a byte to a given 8251 register. All values of R  **/
+/** will be truncated to 3 bits as there are only 8 regs.   **/
+/*************************************************************/
+void Wr8251(register I8251 *D,register byte R,register byte V)
+{
+  /* We only have 8 addressable ports */
+  R&=0x07;
+
+  switch(R)
+  {
+    case 0: /* Data */
+      fputc(V&((0x20<<((D->Control&0x0C)>>2))-1),D->Out);
+      fflush(D->Out);
+      return;
+      /*
+      TODO: Flush the stream at appropriate intervals, instead of
+      flushing for every single character. If flushing after every
+      character remains, make the stream unbuffered.
+      */
+
+    case 1: /* Command */
+      if(D->Mode)
+      {
+        D->Control=V;
+        D->Mode=0;
+        /* Set mode:
+        ......00  sync mode
+        ......01  async, baud rate factor is 1
+        ......10  async, baud rate factor is 16
+        ......11  async, baud rate factor is 64
+        ....00..  character length is 5 bits
+        ....01..  character length is 6 bits
+        ....10..  character length is 7 bits
+        ....11..  character length is 8 bits
+        ...1....  parity enable
+        ..1.....  even/odd parity
+        .1......  sync:  external sync detect (syndet) is an input/output
+        1.......  sync:  single/double character sync
+        00......  async: invalid
+        01......  async: 1   stop bit
+        10......  async: 1.5 stop bits
+        11......  async: 2   stop bits
+        */
+      }
+      else
+      {
+        D->Mode=V&0x40;
+        D->Flow=(V>>4)&0x02;
+        /* Execute command:
+        76543210
+        1.......  enter hunt mode (enable search for sync characters)
+        .1......  internal reset
+        ..1.....  request to send (rts)
+        ...1....  reset error flags (pe,oe,fe)
+        ....1...  send break character
+        .....1..  receive enable
+        ......1.  data terminal ready (dtr)
+        .......1  transmit enable
+
+        Only RESET (bit6) and DTR (bit2) are implemented.
+        */
+      }
+      return;
+
+    case 2: /* Interrupt mask register */
+      D->IRQMask=V;
+      return;
+      /*
+      76543210
+      XXXX....  reserved
+      ....1...  timer interrupt from 8253 channel-2 (0=enable int)
+      .....1..  sync character detect/break detect (0=enable int)
+      ......1.  transmit data ready (TxReady) (0=enable int)
+      .......1  receive data ready (RxReady) (0=enable int)
+
+      Initially all interrupts are disabled. RxReady interrupt must be
+      implemented, the others are optional.
+
+      However, currently no interrupt at all is implemented. The result
+      is that only one character is read per VDP interrupt, so serial
+      communication is 50/60 baud.
+      */
+  }
+
+  /* Other RS232 ports:
+  3: not standardised    -  unused
+  4: 8253 counter 0      -  not implemented
+  5: 8253 counter 1      -  not implemented
+  6: 8253 counter 2      -  not implemented
+  7: 8253 mode register  -  not implemented
+  */
+}
\ No newline at end of file
diff --git a/MCUME_pico2/picomsx/I8251.h b/MCUME_pico2/picomsx/I8251.h
new file mode 100644
index 0000000..bcf5c8f
--- /dev/null
+++ b/MCUME_pico2/picomsx/I8251.h
@@ -0,0 +1,57 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         I8251.h                         **/
+/**                                                         **/
+/** This file contains definitions and declarations for     **/
+/** routines in I8251.c.                                    **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2004-2005                 **/
+/**               Maarten ter Huurne 2000                   **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef I8251_H
+#define I8251_H
+
+#include <stdio.h>
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** I8251 ****************************************************/
+/** This data structure stores I8251 state.                 **/
+/*************************************************************/
+typedef struct
+{
+  byte Control;  /* 8251 ACIA control reg. */
+  byte IRQMask;  /* RS232 interrupt mask   */
+  byte IRQs;     /* RS232 interrupts       */
+  byte Mode;     /* 8251 mode/cmd select   */
+  byte Flow;     /* Flow control state     */
+  int  NextChr;  /* Next char or -1        */
+  FILE *In;      /* Input stream           */
+  FILE *Out;     /* Output stream          */
+} I8251;
+
+/** Reset8251 ************************************************/
+/** Reset 8251 chip, assigning In and Out to the input and  **/
+/** output streams.                                         **/
+/*************************************************************/
+void Reset8251(register I8251 *D,FILE *In,FILE *Out);
+
+/** Rd8251 ***************************************************/
+/** Read a byte from a given 8251 register. All values of R **/
+/** will be truncated to 3 bits as there are only 8 regs.   **/
+/*************************************************************/
+byte Rd8251(register I8251 *D,register byte R);
+
+/** Wr8251 ***************************************************/
+/** Write a byte to a given 8251 register. All values of R  **/
+/** will be truncated to 3 bits as there are only 8 regs.   **/
+/*************************************************************/
+void Wr8251(register I8251 *D,register byte R,register byte V);
+
+#endif /* I8251_H */
diff --git a/MCUME_pico2/picomsx/I8255.c b/MCUME_pico2/picomsx/I8255.c
new file mode 100644
index 0000000..cc76189
--- /dev/null
+++ b/MCUME_pico2/picomsx/I8255.c
@@ -0,0 +1,88 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                          I8255.c                        **/
+/**                                                         **/
+/** This file contains emulation for the i8255 parallel     **/
+/** port interface (PPI) chip from Intel. See I8255.h for   **/
+/** declarations.                                           **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2001-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#include "I8255.h"
+
+/** Reset8255 ************************************************/
+/** Reset the chip. Set all data to 0x00. Set all ports to  **/
+/** "input" mode.                                           **/
+/*************************************************************/
+void Reset8255(register I8255 *D)
+{
+  /* Initialize all registers and ports */
+  D->R[0]=D->Rout[0]=D->Rin[0]=0x00;
+  D->R[1]=D->Rout[1]=D->Rin[1]=0x00;
+  D->R[2]=D->Rout[2]=D->Rin[2]=0x00;
+  D->R[3]=0x9B;
+}
+
+/** Write8255 ************************************************/
+/** Write value V into i8255 register A. Returns 0 when A   **/
+/** is out of range, 1 otherwise.                           **/
+/*************************************************************/
+byte Write8255(register I8255 *D,register byte A,register byte V)
+{
+  switch(A)
+  {
+    case 0:
+    case 1:
+    case 2:
+      /* Data registers */
+      D->R[A]=V;
+      break;
+    case 3:
+      /* Control register */
+      if(V&0x80) D->R[A]=V;
+      else
+      {
+        A=1<<((V&0x0E)>>1);
+        if(V&0x01) D->R[2]|=A; else D->R[2]&=~A;
+      }
+      break;
+    default:
+      /* Invalid register */
+      return(0);
+  }
+
+  /* Set output ports */
+  V=D->R[3];
+  D->Rout[0] = V&0x10? 0x00:D->R[0];
+  D->Rout[1] = V&0x02? 0x00:D->R[1];
+  D->Rout[2] = ((V&0x01? 0x00:D->R[2])&0x0F)
+             | ((V&0x08? 0x00:D->R[2])&0xF0);
+
+  /* Done */
+  return(1);
+}
+
+/** Read8255 *************************************************/
+/** Read value from an i8255 register A. Returns 0 when A   **/
+/** is out of range.                                        **/
+/*************************************************************/
+byte Read8255(register I8255 *D,register byte A)
+{
+  switch(A)
+  {
+    case 0: return(D->R[3]&0x10? D->Rin[0]:D->R[0]);
+    case 1: return(D->R[3]&0x02? D->Rin[1]:D->R[1]);
+    case 2: return
+            (
+              ((D->R[3]&0x01? D->Rin[2]:D->R[2])&0x0F)|
+              ((D->R[3]&0x08? D->Rin[2]:D->R[2])&0xF0)
+            );
+    case 3: return(D->R[3]);
+  }
+
+  /* Invalid address */
+  return(0x00);
+}
diff --git a/MCUME_pico2/picomsx/I8255.h b/MCUME_pico2/picomsx/I8255.h
new file mode 100644
index 0000000..7d39cfe
--- /dev/null
+++ b/MCUME_pico2/picomsx/I8255.h
@@ -0,0 +1,50 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                          I8255.h                        **/
+/**                                                         **/
+/** This file contains emulation for the i8255 parallel     **/
+/** port interface (PPI) chip from Intel. See I8255.h for   **/
+/** the actual code.                                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 2001-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef I8255_H
+#define I8255_H
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** I8255 ****************************************************/
+/** This data structure stores i8255 state and port values. **/
+/*************************************************************/
+typedef struct
+{
+  byte R[4];         /* Registers    */
+  byte Rout[3];      /* Output ports */
+  byte Rin[3];       /* Input ports  */
+} I8255;
+
+/** Reset8255 ************************************************/
+/** Reset the i8255 chip. Set all data to 0x00. Set all     **/
+/** ports to "input" mode.                                  **/
+/*************************************************************/
+void Reset8255(register I8255 *D);
+
+/** Write8255 ************************************************/
+/** Write value V into i8255 register A. Returns 0 when A   **/
+/** is out of range, 1 otherwise.                           **/
+/*************************************************************/
+byte Write8255(register I8255 *D,register byte A,register byte V);
+
+/** Read8255 *************************************************/
+/** Read value from an i8255 register A. Returns 0 when A   **/
+/** is out of range.                                        **/
+/*************************************************************/
+byte Read8255(register I8255 *D,register byte A);
+
+#endif /* I8255_H */
diff --git a/MCUME_pico2/picomsx/MIDIFreq.h b/MCUME_pico2/picomsx/MIDIFreq.h
new file mode 100644
index 0000000..679f99e
--- /dev/null
+++ b/MCUME_pico2/picomsx/MIDIFreq.h
@@ -0,0 +1,1038 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                       MIDIFreq.h                        **/
+/**                                                         **/
+/** This file contains a table to convert sound frequencies **/
+/** into MIDI octave/note numbers. It is included from the  **/
+/** Sound.c and SndWin.c files.                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+{ -36, 8063 },{ -12, 8063 },{  -3, 8298 },{   3, 8358 },
+{   8, 8201 },{  12, 8063 },{  15, 8054 },{  17, 8238 },
+{  19, 8311 },{  21, 8298 },{  23, 8217 },{  25, 8080 },
+{  26, 8238 },{  27, 8358 },{  29, 8102 },{  30, 8159 },
+{  31, 8191 },{  32, 8201 },{  33, 8191 },{  34, 8164 },
+{  35, 8121 },{  36, 8063 },{  36, 8334 },{  37, 8251 },
+{  38, 8158 },{  39, 8054 },{  39, 8283 },{  40, 8162 },
+{  41, 8033 },{  41, 8238 },{  42, 8095 },{  42, 8287 },
+{  43, 8131 },{  43, 8311 },{  44, 8144 },{  44, 8314 },
+{  45, 8137 },{  45, 8298 },{  46, 8113 },{  46, 8265 },
+{  47, 8072 },{  47, 8217 },{  47, 8358 },{  48, 8155 },
+{  48, 8289 },{  49, 8080 },{  49, 8209 },{  49, 8335 },
+{  50, 8117 },{  50, 8238 },{  50, 8357 },{  51, 8132 },
+{  51, 8246 },{  51, 8358 },{  52, 8126 },{  52, 8234 },
+{  52, 8340 },{  53, 8102 },{  53, 8204 },{  53, 8305 },
+{  54, 8062 },{  54, 8159 },{  54, 8255 },{  54, 8349 },
+{  55, 8100 },{  55, 8191 },{  55, 8281 },{  56, 8028 },
+{  56, 8115 },{  56, 8201 },{  56, 8286 },{  57, 8028 },
+{  57, 8110 },{  57, 8191 },{  57, 8271 },{  57, 8350 },
+{  58, 8087 },{  58, 8164 },{  58, 8240 },{  58, 8315 },
+{  59, 8047 },{  59, 8121 },{  59, 8193 },{  59, 8264 },
+{  59, 8335 },{  60, 8063 },{  60, 8132 },{  60, 8200 },
+{  60, 8267 },{  60, 8334 },{  61, 8058 },{  61, 8123 },
+{  61, 8188 },{  61, 8251 },{  61, 8314 },{  62, 8035 },
+{  62, 8097 },{  62, 8158 },{  62, 8218 },{  62, 8278 },
+{  62, 8337 },{  63, 8054 },{  63, 8112 },{  63, 8170 },
+{  63, 8227 },{  63, 8283 },{  63, 8339 },{  64, 8053 },
+{  64, 8108 },{  64, 8162 },{  64, 8216 },{  64, 8269 },
+{  64, 8322 },{  65, 8033 },{  65, 8085 },{  65, 8137 },
+{  65, 8188 },{  65, 8238 },{  65, 8288 },{  65, 8338 },
+{  66, 8046 },{  66, 8095 },{  66, 8143 },{  66, 8191 },
+{  66, 8239 },{  66, 8287 },{  66, 8334 },{  67, 8039 },
+{  67, 8085 },{  67, 8131 },{  67, 8176 },{  67, 8222 },
+{  67, 8266 },{  67, 8311 },{  67, 8355 },{  68, 8057 },
+{  68, 8101 },{  68, 8144 },{  68, 8187 },{  68, 8230 },
+{  68, 8272 },{  68, 8314 },{  68, 8356 },{  69, 8056 },
+{  69, 8097 },{  69, 8137 },{  69, 8178 },{  69, 8218 },
+{  69, 8258 },{  69, 8298 },{  69, 8337 },{  70, 8035 },
+{  70, 8074 },{  70, 8113 },{  70, 8151 },{  70, 8189 },
+{  70, 8227 },{  70, 8265 },{  70, 8302 },{  70, 8340 },
+{  71, 8035 },{  71, 8072 },{  71, 8108 },{  71, 8145 },
+{  71, 8181 },{  71, 8217 },{  71, 8252 },{  71, 8288 },
+{  71, 8323 },{  71, 8358 },{  72, 8051 },{  72, 8086 },
+{  72, 8120 },{  72, 8155 },{  72, 8189 },{  72, 8222 },
+{  72, 8256 },{  72, 8289 },{  72, 8323 },{  72, 8356 },
+{  73, 8047 },{  73, 8080 },{  73, 8112 },{  73, 8145 },
+{  73, 8177 },{  73, 8209 },{  73, 8241 },{  73, 8272 },
+{  73, 8304 },{  73, 8335 },{  74, 8025 },{  74, 8056 },
+{  74, 8087 },{  74, 8117 },{  74, 8148 },{  74, 8178 },
+{  74, 8208 },{  74, 8238 },{  74, 8268 },{  74, 8298 },
+{  74, 8327 },{  74, 8357 },{  75, 8045 },{  75, 8074 },
+{  75, 8103 },{  75, 8132 },{  75, 8160 },{  75, 8189 },
+{  75, 8217 },{  75, 8246 },{  75, 8274 },{  75, 8302 },
+{  75, 8330 },{  75, 8358 },{  76, 8044 },{  76, 8071 },
+{  76, 8099 },{  76, 8126 },{  76, 8153 },{  76, 8180 },
+{  76, 8207 },{  76, 8234 },{  76, 8260 },{  76, 8287 },
+{  76, 8313 },{  76, 8340 },{  77, 8024 },{  77, 8051 },
+{  77, 8076 },{  77, 8102 },{  77, 8128 },{  77, 8154 },
+{  77, 8179 },{  77, 8204 },{  77, 8230 },{  77, 8255 },
+{  77, 8280 },{  77, 8305 },{  77, 8330 },{  77, 8354 },
+{  78, 8038 },{  78, 8062 },{  78, 8087 },{  78, 8111 },
+{  78, 8135 },{  78, 8159 },{  78, 8183 },{  78, 8207 },
+{  78, 8231 },{  78, 8255 },{  78, 8279 },{  78, 8302 },
+{  78, 8326 },{  78, 8349 },{  79, 8031 },{  79, 8054 },
+{  79, 8077 },{  79, 8100 },{  79, 8123 },{  79, 8146 },
+{  79, 8169 },{  79, 8191 },{  79, 8214 },{  79, 8237 },
+{  79, 8259 },{  79, 8281 },{  79, 8303 },{  79, 8326 },
+{  79, 8348 },{  80, 8028 },{  80, 8050 },{  80, 8072 },
+{  80, 8094 },{  80, 8115 },{  80, 8137 },{  80, 8159 },
+{  80, 8180 },{  80, 8201 },{  80, 8223 },{  80, 8244 },
+{  80, 8265 },{  80, 8286 },{  80, 8307 },{  80, 8328 },
+{  80, 8349 },{  81, 8028 },{  81, 8049 },{  81, 8069 },
+{  81, 8090 },{  81, 8110 },{  81, 8131 },{  81, 8151 },
+{  81, 8171 },{  81, 8191 },{  81, 8212 },{  81, 8232 },
+{  81, 8252 },{  81, 8271 },{  81, 8291 },{  81, 8311 },
+{  81, 8331 },{  81, 8350 },{  82, 8029 },{  82, 8048 },
+{  82, 8068 },{  82, 8087 },{  82, 8106 },{  82, 8126 },
+{  82, 8145 },{  82, 8164 },{  82, 8183 },{  82, 8202 },
+{  82, 8221 },{  82, 8240 },{  82, 8259 },{  82, 8277 },
+{  82, 8296 },{  82, 8315 },{  82, 8333 },{  82, 8352 },
+{  83, 8029 },{  83, 8047 },{  83, 8066 },{  83, 8084 },
+{  83, 8102 },{  83, 8121 },{  83, 8139 },{  83, 8157 },
+{  83, 8175 },{  83, 8193 },{  83, 8211 },{  83, 8229 },
+{  83, 8246 },{  83, 8264 },{  83, 8282 },{  83, 8299 },
+{  83, 8317 },{  83, 8335 },{  83, 8352 },{  84, 8028 },
+{  84, 8046 },{  84, 8063 },{  84, 8080 },{  84, 8097 },
+{  84, 8115 },{  84, 8132 },{  84, 8149 },{  84, 8166 },
+{  84, 8183 },{  84, 8200 },{  84, 8217 },{  84, 8234 },
+{  84, 8250 },{  84, 8267 },{  84, 8284 },{  84, 8300 },
+{  84, 8317 },{  84, 8334 },{  84, 8350 },{  85, 8025 },
+{  85, 8042 },{  85, 8058 },{  85, 8074 },{  85, 8091 },
+{  85, 8107 },{  85, 8123 },{  85, 8139 },{  85, 8155 },
+{  85, 8171 },{  85, 8188 },{  85, 8203 },{  85, 8219 },
+{  85, 8235 },{  85, 8251 },{  85, 8267 },{  85, 8283 },
+{  85, 8298 },{  85, 8314 },{  85, 8330 },{  85, 8345 },
+{  85, 8361 },{  86, 8035 },{  86, 8051 },{  86, 8066 },
+{  86, 8081 },{  86, 8097 },{  86, 8112 },{  86, 8127 },
+{  86, 8143 },{  86, 8158 },{  86, 8173 },{  86, 8188 },
+{  86, 8203 },{  86, 8218 },{  86, 8233 },{  86, 8248 },
+{  86, 8263 },{  86, 8278 },{  86, 8293 },{  86, 8308 },
+{  86, 8322 },{  86, 8337 },{  86, 8352 },{  87, 8025 },
+{  87, 8040 },{  87, 8054 },{  87, 8069 },{  87, 8084 },
+{  87, 8098 },{  87, 8112 },{  87, 8127 },{  87, 8141 },
+{  87, 8156 },{  87, 8170 },{  87, 8184 },{  87, 8198 },
+{  87, 8213 },{  87, 8227 },{  87, 8241 },{  87, 8255 },
+{  87, 8269 },{  87, 8283 },{  87, 8297 },{  87, 8311 },
+{  87, 8325 },{  87, 8339 },{  87, 8353 },{  88, 8025 },
+{  88, 8039 },{  88, 8053 },{  88, 8067 },{  88, 8081 },
+{  88, 8094 },{  88, 8108 },{  88, 8121 },{  88, 8135 },
+{  88, 8149 },{  88, 8162 },{  88, 8176 },{  88, 8189 },
+{  88, 8203 },{  88, 8216 },{  88, 8229 },{  88, 8243 },
+{  88, 8256 },{  88, 8269 },{  88, 8283 },{  88, 8296 },
+{  88, 8309 },{  88, 8322 },{  88, 8335 },{  88, 8348 },
+{  88, 8361 },{  89, 8033 },{  89, 8046 },{  89, 8059 },
+{  89, 8072 },{  89, 8085 },{  89, 8098 },{  89, 8111 },
+{  89, 8124 },{  89, 8137 },{  89, 8149 },{  89, 8162 },
+{  89, 8175 },{  89, 8188 },{  89, 8200 },{  89, 8213 },
+{  89, 8226 },{  89, 8238 },{  89, 8251 },{  89, 8263 },
+{  89, 8276 },{  89, 8288 },{  89, 8301 },{  89, 8313 },
+{  89, 8326 },{  89, 8338 },{  89, 8350 },{  90, 8021 },
+{  90, 8034 },{  90, 8046 },{  90, 8058 },{  90, 8070 },
+{  90, 8083 },{  90, 8095 },{  90, 8107 },{  90, 8119 },
+{  90, 8131 },{  90, 8143 },{  90, 8155 },{  90, 8167 },
+{  90, 8179 },{  90, 8191 },{  90, 8203 },{  90, 8215 },
+{  90, 8227 },{  90, 8239 },{  90, 8251 },{  90, 8263 },
+{  90, 8275 },{  90, 8287 },{  90, 8298 },{  90, 8310 },
+{  90, 8322 },{  90, 8334 },{  90, 8345 },{  90, 8357 },
+{  91, 8027 },{  91, 8039 },{  91, 8050 },{  91, 8062 },
+{  91, 8073 },{  91, 8085 },{  91, 8096 },{  91, 8108 },
+{  91, 8119 },{  91, 8131 },{  91, 8142 },{  91, 8154 },
+{  91, 8165 },{  91, 8176 },{  91, 8188 },{  91, 8199 },
+{  91, 8210 },{  91, 8222 },{  91, 8233 },{  91, 8244 },
+{  91, 8255 },{  91, 8266 },{  91, 8278 },{  91, 8289 },
+{  91, 8300 },{  91, 8311 },{  91, 8322 },{  91, 8333 },
+{  91, 8344 },{  91, 8355 },{  92, 8025 },{  92, 8036 },
+{  92, 8047 },{  92, 8057 },{  92, 8068 },{  92, 8079 },
+{  92, 8090 },{  92, 8101 },{  92, 8112 },{  92, 8123 },
+{  92, 8133 },{  92, 8144 },{  92, 8155 },{  92, 8166 },
+{  92, 8176 },{  92, 8187 },{  92, 8198 },{  92, 8208 },
+{  92, 8219 },{  92, 8230 },{  92, 8240 },{  92, 8251 },
+{  92, 8261 },{  92, 8272 },{  92, 8282 },{  92, 8293 },
+{  92, 8303 },{  92, 8314 },{  92, 8324 },{  92, 8335 },
+{  92, 8345 },{  92, 8356 },{  93, 8025 },{  93, 8035 },
+{  93, 8045 },{  93, 8056 },{  93, 8066 },{  93, 8076 },
+{  93, 8086 },{  93, 8097 },{  93, 8107 },{  93, 8117 },
+{  93, 8127 },{  93, 8137 },{  93, 8148 },{  93, 8158 },
+{  93, 8168 },{  93, 8178 },{  93, 8188 },{  93, 8198 },
+{  93, 8208 },{  93, 8218 },{  93, 8228 },{  93, 8238 },
+{  93, 8248 },{  93, 8258 },{  93, 8268 },{  93, 8278 },
+{  93, 8288 },{  93, 8298 },{  93, 8308 },{  93, 8318 },
+{  93, 8327 },{  93, 8337 },{  93, 8347 },{  93, 8357 },
+{  94, 8025 },{  94, 8035 },{  94, 8045 },{  94, 8055 },
+{  94, 8064 },{  94, 8074 },{  94, 8084 },{  94, 8093 },
+{  94, 8103 },{  94, 8113 },{  94, 8122 },{  94, 8132 },
+{  94, 8142 },{  94, 8151 },{  94, 8161 },{  94, 8170 },
+{  94, 8180 },{  94, 8189 },{  94, 8199 },{  94, 8208 },
+{  94, 8218 },{  94, 8227 },{  94, 8237 },{  94, 8246 },
+{  94, 8256 },{  94, 8265 },{  94, 8274 },{  94, 8284 },
+{  94, 8293 },{  94, 8302 },{  94, 8312 },{  94, 8321 },
+{  94, 8330 },{  94, 8340 },{  94, 8349 },{  94, 8358 },
+{  95, 8026 },{  95, 8035 },{  95, 8044 },{  95, 8054 },
+{  95, 8063 },{  95, 8072 },{  95, 8081 },{  95, 8090 },
+{  95, 8099 },{  95, 8108 },{  95, 8118 },{  95, 8127 },
+{  95, 8136 },{  95, 8145 },{  95, 8154 },{  95, 8163 },
+{  95, 8172 },{  95, 8181 },{  95, 8190 },{  95, 8199 },
+{  95, 8208 },{  95, 8217 },{  95, 8226 },{  95, 8235 },
+{  95, 8243 },{  95, 8252 },{  95, 8261 },{  95, 8270 },
+{  95, 8279 },{  95, 8288 },{  95, 8297 },{  95, 8305 },
+{  95, 8314 },{  95, 8323 },{  95, 8332 },{  95, 8340 },
+{  95, 8349 },{  95, 8358 },{  96, 8025 },{  96, 8034 },
+{  96, 8043 },{  96, 8051 },{  96, 8060 },{  96, 8069 },
+{  96, 8077 },{  96, 8086 },{  96, 8095 },{  96, 8103 },
+{  96, 8112 },{  96, 8120 },{  96, 8129 },{  96, 8137 },
+{  96, 8146 },{  96, 8155 },{  96, 8163 },{  96, 8172 },
+{  96, 8180 },{  96, 8189 },{  96, 8197 },{  96, 8205 },
+{  96, 8214 },{  96, 8222 },{  96, 8231 },{  96, 8239 },
+{  96, 8248 },{  96, 8256 },{  96, 8264 },{  96, 8273 },
+{  96, 8281 },{  96, 8289 },{  96, 8298 },{  96, 8306 },
+{  96, 8314 },{  96, 8323 },{  96, 8331 },{  96, 8339 },
+{  96, 8347 },{  96, 8356 },{  97, 8023 },{  97, 8031 },
+{  97, 8039 },{  97, 8047 },{  97, 8055 },{  97, 8064 },
+{  97, 8072 },{  97, 8080 },{  97, 8088 },{  97, 8096 },
+{  97, 8104 },{  97, 8112 },{  97, 8120 },{  97, 8129 },
+{  97, 8137 },{  97, 8145 },{  97, 8153 },{  97, 8161 },
+{  97, 8169 },{  97, 8177 },{  97, 8185 },{  97, 8193 },
+{  97, 8201 },{  97, 8209 },{  97, 8217 },{  97, 8225 },
+{  97, 8233 },{  97, 8241 },{  97, 8249 },{  97, 8256 },
+{  97, 8264 },{  97, 8272 },{  97, 8280 },{  97, 8288 },
+{  97, 8296 },{  97, 8304 },{  97, 8312 },{  97, 8319 },
+{  97, 8327 },{  97, 8335 },{  97, 8343 },{  97, 8351 },
+{  97, 8358 },{  98, 8025 },{  98, 8033 },{  98, 8040 },
+{  98, 8048 },{  98, 8056 },{  98, 8063 },{  98, 8071 },
+{  98, 8079 },{  98, 8087 },{  98, 8094 },{  98, 8102 },
+{  98, 8110 },{  98, 8117 },{  98, 8125 },{  98, 8132 },
+{  98, 8140 },{  98, 8148 },{  98, 8155 },{  98, 8163 },
+{  98, 8170 },{  98, 8178 },{  98, 8186 },{  98, 8193 },
+{  98, 8201 },{  98, 8208 },{  98, 8216 },{  98, 8223 },
+{  98, 8231 },{  98, 8238 },{  98, 8246 },{  98, 8253 },
+{  98, 8261 },{  98, 8268 },{  98, 8276 },{  98, 8283 },
+{  98, 8290 },{  98, 8298 },{  98, 8305 },{  98, 8313 },
+{  98, 8320 },{  98, 8327 },{  98, 8335 },{  98, 8342 },
+{  98, 8349 },{  98, 8357 },{  99, 8023 },{  99, 8030 },
+{  99, 8037 },{  99, 8045 },{  99, 8052 },{  99, 8059 },
+{  99, 8067 },{  99, 8074 },{  99, 8081 },{  99, 8088 },
+{  99, 8096 },{  99, 8103 },{  99, 8110 },{  99, 8117 },
+{  99, 8125 },{  99, 8132 },{  99, 8139 },{  99, 8146 },
+{  99, 8153 },{  99, 8160 },{  99, 8168 },{  99, 8175 },
+{  99, 8182 },{  99, 8189 },{  99, 8196 },{  99, 8203 },
+{  99, 8210 },{  99, 8217 },{  99, 8225 },{  99, 8232 },
+{  99, 8239 },{  99, 8246 },{  99, 8253 },{  99, 8260 },
+{  99, 8267 },{  99, 8274 },{  99, 8281 },{  99, 8288 },
+{  99, 8295 },{  99, 8302 },{  99, 8309 },{  99, 8316 },
+{  99, 8323 },{  99, 8330 },{  99, 8337 },{  99, 8344 },
+{  99, 8351 },{  99, 8358 },{ 100, 8023 },{ 100, 8030 },
+{ 100, 8037 },{ 100, 8044 },{ 100, 8051 },{ 100, 8058 },
+{ 100, 8065 },{ 100, 8071 },{ 100, 8078 },{ 100, 8085 },
+{ 100, 8092 },{ 100, 8099 },{ 100, 8106 },{ 100, 8112 },
+{ 100, 8119 },{ 100, 8126 },{ 100, 8133 },{ 100, 8140 },
+{ 100, 8146 },{ 100, 8153 },{ 100, 8160 },{ 100, 8167 },
+{ 100, 8173 },{ 100, 8180 },{ 100, 8187 },{ 100, 8194 },
+{ 100, 8200 },{ 100, 8207 },{ 100, 8214 },{ 100, 8220 },
+{ 100, 8227 },{ 100, 8234 },{ 100, 8240 },{ 100, 8247 },
+{ 100, 8254 },{ 100, 8260 },{ 100, 8267 },{ 100, 8274 },
+{ 100, 8280 },{ 100, 8287 },{ 100, 8294 },{ 100, 8300 },
+{ 100, 8307 },{ 100, 8313 },{ 100, 8320 },{ 100, 8326 },
+{ 100, 8333 },{ 100, 8340 },{ 100, 8346 },{ 100, 8353 },
+{ 100, 8359 },{ 101, 8024 },{ 101, 8031 },{ 101, 8037 },
+{ 101, 8044 },{ 101, 8051 },{ 101, 8057 },{ 101, 8063 },
+{ 101, 8070 },{ 101, 8076 },{ 101, 8083 },{ 101, 8089 },
+{ 101, 8096 },{ 101, 8102 },{ 101, 8109 },{ 101, 8115 },
+{ 101, 8122 },{ 101, 8128 },{ 101, 8134 },{ 101, 8141 },
+{ 101, 8147 },{ 101, 8154 },{ 101, 8160 },{ 101, 8166 },
+{ 101, 8173 },{ 101, 8179 },{ 101, 8185 },{ 101, 8192 },
+{ 101, 8198 },{ 101, 8204 },{ 101, 8211 },{ 101, 8217 },
+{ 101, 8223 },{ 101, 8230 },{ 101, 8236 },{ 101, 8242 },
+{ 101, 8249 },{ 101, 8255 },{ 101, 8261 },{ 101, 8267 },
+{ 101, 8274 },{ 101, 8280 },{ 101, 8286 },{ 101, 8292 },
+{ 101, 8299 },{ 101, 8305 },{ 101, 8311 },{ 101, 8317 },
+{ 101, 8324 },{ 101, 8330 },{ 101, 8336 },{ 101, 8342 },
+{ 101, 8348 },{ 101, 8354 },{ 101, 8361 },{ 102, 8025 },
+{ 102, 8032 },{ 102, 8038 },{ 102, 8044 },{ 102, 8050 },
+{ 102, 8056 },{ 102, 8062 },{ 102, 8068 },{ 102, 8075 },
+{ 102, 8081 },{ 102, 8087 },{ 102, 8093 },{ 102, 8099 },
+{ 102, 8105 },{ 102, 8111 },{ 102, 8117 },{ 102, 8123 },
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+{ 123, 8321 },{ 123, 8323 },{ 123, 8325 },{ 123, 8326 },
+{ 123, 8328 },{ 123, 8330 },{ 123, 8332 },{ 123, 8333 },
+{ 123, 8335 },{ 123, 8337 },{ 123, 8338 },{ 123, 8340 },
+{ 123, 8342 },{ 123, 8344 },{ 123, 8345 },{ 123, 8347 },
+{ 123, 8349 },{ 123, 8351 },{ 123, 8352 },{ 123, 8354 },
+{ 123, 8356 },{ 123, 8358 },{ 123, 8359 },{ 123, 8361 },
+{ 124, 8021 },{ 124, 8023 },{ 124, 8025 },{ 124, 8027 },
+{ 124, 8028 },{ 124, 8030 },{ 124, 8032 },{ 124, 8034 },
+{ 124, 8035 },{ 124, 8037 },{ 124, 8039 },{ 124, 8040 },
+{ 124, 8042 },{ 124, 8044 },{ 124, 8046 },{ 124, 8047 },
+{ 124, 8049 },{ 124, 8051 },{ 124, 8052 },{ 124, 8054 },
+{ 124, 8056 },{ 124, 8058 },{ 124, 8059 },{ 124, 8061 },
+{ 124, 8063 },{ 124, 8065 },{ 124, 8066 },{ 124, 8068 },
+{ 124, 8070 },{ 124, 8071 },{ 124, 8073 },{ 124, 8075 },
+{ 124, 8077 },{ 124, 8078 },{ 124, 8080 },{ 124, 8082 },
+{ 124, 8083 },{ 124, 8085 },{ 124, 8087 },{ 124, 8089 },
+{ 124, 8090 },{ 124, 8092 },{ 124, 8094 },{ 124, 8095 },
+{ 124, 8097 },{ 124, 8099 },{ 124, 8100 },{ 124, 8102 },
+{ 124, 8104 },{ 124, 8106 },{ 124, 8107 },{ 124, 8109 },
+{ 124, 8111 },{ 124, 8112 },{ 124, 8114 },{ 124, 8116 },
+{ 124, 8118 },{ 124, 8119 },{ 124, 8121 },{ 124, 8123 },
+{ 124, 8124 },{ 124, 8126 },{ 124, 8128 },{ 124, 8129 },
+{ 124, 8131 },{ 124, 8133 },{ 124, 8134 },{ 124, 8136 },
+{ 124, 8138 },{ 124, 8140 },{ 124, 8141 },{ 124, 8143 },
+{ 124, 8145 },{ 124, 8146 },{ 124, 8148 },{ 124, 8150 },
+{ 124, 8151 },{ 124, 8153 },{ 124, 8155 },{ 124, 8157 },
+{ 124, 8158 },{ 124, 8160 },{ 124, 8162 },{ 124, 8163 },
+{ 124, 8165 },{ 124, 8167 },{ 124, 8168 },{ 124, 8170 },
+{ 124, 8172 },{ 124, 8173 },{ 124, 8175 },{ 124, 8177 },
+{ 124, 8178 },{ 124, 8180 },{ 124, 8182 },{ 124, 8184 },
+{ 124, 8185 },{ 124, 8187 },{ 124, 8189 },{ 124, 8190 },
+{ 124, 8192 },{ 124, 8194 },{ 124, 8195 },{ 124, 8197 },
+{ 124, 8199 },{ 124, 8200 },{ 124, 8202 },{ 124, 8204 },
+{ 124, 8205 },{ 124, 8207 },{ 124, 8209 },{ 124, 8210 },
+{ 124, 8212 },{ 124, 8214 },{ 124, 8215 },{ 124, 8217 },
+{ 124, 8219 },{ 124, 8220 },{ 124, 8222 },{ 124, 8224 },
+{ 124, 8225 },{ 124, 8227 },{ 124, 8229 },{ 124, 8230 },
+{ 124, 8232 },{ 124, 8234 },{ 124, 8235 },{ 124, 8237 },
+{ 124, 8239 },{ 124, 8240 },{ 124, 8242 },{ 124, 8244 },
+{ 124, 8245 },{ 124, 8247 },{ 124, 8249 },{ 124, 8250 },
+{ 124, 8252 },{ 124, 8254 },{ 124, 8255 },{ 124, 8257 },
+{ 124, 8259 },{ 124, 8260 },{ 124, 8262 },{ 124, 8264 },
+{ 124, 8265 },{ 124, 8267 },{ 124, 8269 },{ 124, 8270 },
+{ 124, 8272 },{ 124, 8274 },{ 124, 8275 },{ 124, 8277 },
+{ 124, 8279 },{ 124, 8280 },{ 124, 8282 },{ 124, 8284 },
+{ 124, 8285 },{ 124, 8287 },{ 124, 8289 },{ 124, 8290 },
+{ 124, 8292 },{ 124, 8294 },{ 124, 8295 },{ 124, 8297 },
+{ 124, 8299 },{ 124, 8300 },{ 124, 8302 },{ 124, 8303 },
+{ 124, 8305 },{ 124, 8307 },{ 124, 8308 },{ 124, 8310 },
+{ 124, 8312 },{ 124, 8313 },{ 124, 8315 },{ 124, 8317 },
+{ 124, 8318 },{ 124, 8320 },{ 124, 8322 },{ 124, 8323 },
+{ 124, 8325 },{ 124, 8326 },{ 124, 8328 },{ 124, 8330 },
+{ 124, 8331 },{ 124, 8333 },{ 124, 8335 },{ 124, 8336 },
+{ 124, 8338 },{ 124, 8340 },{ 124, 8341 },{ 124, 8343 },
+{ 124, 8345 },{ 124, 8346 },{ 124, 8348 },{ 124, 8349 },
+{ 124, 8351 },{ 124, 8353 },{ 124, 8354 },{ 124, 8356 },
+{ 124, 8358 },{ 124, 8359 },{ 124, 8361 },{ 125, 8021 },
+{ 125, 8023 },{ 125, 8024 },{ 125, 8026 },{ 125, 8028 },
+{ 125, 8029 },{ 125, 8031 },{ 125, 8033 },{ 125, 8034 },
+{ 125, 8036 },{ 125, 8037 },{ 125, 8039 },{ 125, 8041 },
+{ 125, 8042 },{ 125, 8044 },{ 125, 8046 },{ 125, 8047 },
+{ 125, 8049 },{ 125, 8051 },{ 125, 8052 },{ 125, 8054 },
+{ 125, 8055 },{ 125, 8057 },{ 125, 8059 },{ 125, 8060 },
+{ 125, 8062 },{ 125, 8063 },{ 125, 8065 },{ 125, 8067 },
+{ 125, 8068 },{ 125, 8070 },{ 125, 8072 },{ 125, 8073 },
+{ 125, 8075 },{ 125, 8076 },{ 125, 8078 },{ 125, 8080 },
+{ 125, 8081 },{ 125, 8083 },{ 125, 8085 },{ 125, 8086 },
+{ 125, 8088 },{ 125, 8089 },{ 125, 8091 },{ 125, 8093 },
+{ 125, 8094 },{ 125, 8096 },{ 125, 8097 },{ 125, 8099 },
+{ 125, 8101 },{ 125, 8102 },{ 125, 8104 },{ 125, 8105 },
+{ 125, 8107 },{ 125, 8109 },{ 125, 8110 },{ 125, 8112 },
+{ 125, 8114 },{ 125, 8115 },{ 125, 8117 },{ 125, 8118 },
+{ 125, 8120 },{ 125, 8122 },{ 125, 8123 },{ 125, 8125 },
+{ 125, 8126 },{ 125, 8128 },{ 125, 8130 },{ 125, 8131 },
+{ 125, 8133 },{ 125, 8134 },{ 125, 8136 },{ 125, 8138 },
+{ 125, 8139 },{ 125, 8141 },{ 125, 8142 },{ 125, 8144 },
+{ 125, 8146 },{ 125, 8147 },{ 125, 8149 },{ 125, 8150 },
+{ 125, 8152 },{ 125, 8154 },{ 125, 8155 },{ 125, 8157 },
+{ 125, 8158 },{ 125, 8160 },{ 125, 8162 },{ 125, 8163 },
+{ 125, 8165 },{ 125, 8166 },{ 125, 8168 },{ 125, 8170 },
+{ 125, 8171 },{ 125, 8173 },{ 125, 8174 },{ 125, 8176 },
+{ 125, 8177 },{ 125, 8179 },{ 125, 8181 },{ 125, 8182 },
+{ 125, 8184 },{ 125, 8185 },{ 125, 8187 },{ 125, 8189 },
+{ 125, 8190 },{ 125, 8192 },{ 125, 8193 },{ 125, 8195 },
+{ 125, 8197 },{ 125, 8198 },{ 125, 8200 },{ 125, 8201 },
+{ 125, 8203 },{ 125, 8204 },{ 125, 8206 },{ 125, 8208 },
+{ 125, 8209 },{ 125, 8211 },{ 125, 8212 },{ 125, 8214 },
+{ 125, 8216 },{ 125, 8217 },{ 125, 8219 },{ 125, 8220 },
+{ 125, 8222 },{ 125, 8223 },{ 125, 8225 },{ 125, 8227 },
+{ 125, 8228 },{ 125, 8230 },{ 125, 8231 },{ 125, 8233 },
+{ 125, 8234 },{ 125, 8236 },{ 125, 8238 },{ 125, 8239 },
+{ 125, 8241 },{ 125, 8242 },{ 125, 8244 },{ 125, 8245 },
+{ 125, 8247 },{ 125, 8249 },{ 125, 8250 },{ 125, 8252 },
+{ 125, 8253 },{ 125, 8255 },{ 125, 8256 },{ 125, 8258 },
+{ 125, 8260 },{ 125, 8261 },{ 125, 8263 },{ 125, 8264 },
+{ 125, 8266 },{ 125, 8267 },{ 125, 8269 },{ 125, 8271 },
+{ 125, 8272 },{ 125, 8274 },{ 125, 8275 },{ 125, 8277 },
+{ 125, 8278 },{ 125, 8280 },{ 125, 8281 },{ 125, 8283 },
+{ 125, 8285 },{ 125, 8286 },{ 125, 8288 },{ 125, 8289 },
+{ 125, 8291 },{ 125, 8292 },{ 125, 8294 },{ 125, 8296 },
+{ 125, 8297 },{ 125, 8299 },{ 125, 8300 },{ 125, 8302 },
+{ 125, 8303 },{ 125, 8305 },{ 125, 8306 },{ 125, 8308 },
+{ 125, 8310 },{ 125, 8311 },{ 125, 8313 },{ 125, 8314 },
+{ 125, 8316 },{ 125, 8317 },{ 125, 8319 },{ 125, 8320 },
+{ 125, 8322 },{ 125, 8324 },{ 125, 8325 },{ 125, 8327 },
+{ 125, 8328 },{ 125, 8330 },{ 125, 8331 },{ 125, 8333 },
+{ 125, 8334 },{ 125, 8336 },{ 125, 8337 },{ 125, 8339 },
+{ 125, 8341 },{ 125, 8342 },{ 125, 8344 },{ 125, 8345 },
+{ 125, 8347 },{ 125, 8348 },{ 125, 8350 },{ 125, 8351 },
+{ 125, 8353 },{ 125, 8354 },{ 125, 8356 },{ 125, 8358 },
+{ 125, 8359 },{ 125, 8361 },{ 126, 8021 },{ 126, 8022 },
+{ 126, 8024 },{ 126, 8025 },{ 126, 8027 },{ 126, 8029 },
+{ 126, 8030 },{ 126, 8032 },{ 126, 8033 },{ 126, 8035 },
+{ 126, 8036 },{ 126, 8038 },{ 126, 8039 },{ 126, 8041 },
+{ 126, 8042 },{ 126, 8044 },{ 126, 8045 },{ 126, 8047 },
+{ 126, 8049 },{ 126, 8050 },{ 126, 8052 },{ 126, 8053 },
+{ 126, 8055 },{ 126, 8056 },{ 126, 8058 },{ 126, 8059 },
+{ 126, 8061 },{ 126, 8062 },{ 126, 8064 },{ 126, 8065 },
+{ 126, 8067 },{ 126, 8068 },{ 126, 8070 },{ 126, 8071 },
+{ 126, 8073 },{ 126, 8075 },{ 126, 8076 },{ 126, 8078 },
+{ 126, 8079 },{ 126, 8081 },{ 126, 8082 },{ 126, 8084 },
+{ 126, 8085 },{ 126, 8087 },{ 126, 8088 },{ 126, 8090 },
+{ 126, 8091 },{ 126, 8093 },{ 126, 8094 },{ 126, 8096 },
+{ 126, 8097 },{ 126, 8099 },{ 126, 8100 },{ 126, 8102 },
+{ 126, 8103 },{ 126, 8105 },{ 126, 8107 },{ 126, 8108 },
+{ 126, 8110 },{ 126, 8111 },{ 126, 8113 },{ 126, 8114 },
+{ 126, 8116 },{ 126, 8117 },{ 126, 8119 },{ 126, 8120 },
+{ 126, 8122 },{ 126, 8123 },{ 126, 8125 },{ 126, 8126 },
+{ 126, 8128 },{ 126, 8129 },{ 126, 8131 },{ 126, 8132 },
+{ 126, 8134 },{ 126, 8135 },{ 126, 8137 },{ 126, 8138 },
+{ 126, 8140 },{ 126, 8141 },{ 126, 8143 },{ 126, 8144 },
+{ 126, 8146 },{ 126, 8147 },{ 126, 8149 },{ 126, 8150 },
+{ 126, 8152 },{ 126, 8153 },{ 126, 8155 },{ 126, 8156 },
+{ 126, 8158 },{ 126, 8159 },{ 126, 8161 },{ 126, 8162 },
+{ 126, 8164 },{ 126, 8165 },{ 126, 8167 },{ 126, 8168 },
+{ 126, 8170 },{ 126, 8171 },{ 126, 8173 },{ 126, 8174 },
+{ 126, 8176 },{ 126, 8177 },{ 126, 8179 },{ 126, 8180 },
+{ 126, 8182 },{ 126, 8183 },{ 126, 8185 },{ 126, 8186 },
+{ 126, 8188 },{ 126, 8189 },{ 126, 8191 },{ 126, 8192 },
+{ 126, 8194 },{ 126, 8195 },{ 126, 8197 },{ 126, 8198 },
+{ 126, 8200 },{ 126, 8201 },{ 126, 8203 },{ 126, 8204 },
+{ 126, 8206 },{ 126, 8207 },{ 126, 8209 },{ 126, 8210 },
+{ 126, 8212 },{ 126, 8213 },{ 126, 8215 },{ 126, 8216 },
+{ 126, 8218 },{ 126, 8219 },{ 126, 8221 },{ 126, 8222 },
+{ 126, 8224 },{ 126, 8225 },{ 126, 8227 },{ 126, 8228 },
+{ 126, 8230 },{ 126, 8231 },{ 126, 8233 },{ 126, 8234 },
+{ 126, 8236 },{ 126, 8237 },{ 126, 8239 },{ 126, 8240 },
+{ 126, 8242 },{ 126, 8243 },{ 126, 8245 },{ 126, 8246 },
+{ 126, 8248 },{ 126, 8249 },{ 126, 8251 },{ 126, 8252 },
+{ 126, 8254 },{ 126, 8255 },{ 126, 8257 },{ 126, 8258 },
+{ 126, 8259 },{ 126, 8261 },{ 126, 8262 },{ 126, 8264 },
+{ 126, 8265 },{ 126, 8267 },{ 126, 8268 },{ 126, 8270 },
+{ 126, 8271 },{ 126, 8273 },{ 126, 8274 },{ 126, 8276 },
+{ 126, 8277 },{ 126, 8279 },{ 126, 8280 },{ 126, 8282 },
+{ 126, 8283 },{ 126, 8285 },{ 126, 8286 },{ 126, 8288 },
+{ 126, 8289 },{ 126, 8290 },{ 126, 8292 },{ 126, 8293 },
+{ 126, 8295 },{ 126, 8296 },{ 126, 8298 },{ 126, 8299 },
+{ 126, 8301 },{ 126, 8302 },{ 126, 8304 },{ 126, 8305 },
+{ 126, 8307 },{ 126, 8308 },{ 126, 8310 },{ 126, 8311 },
+{ 126, 8313 },{ 126, 8314 },{ 126, 8315 },{ 126, 8317 },
+{ 126, 8318 },{ 126, 8320 },{ 126, 8321 },{ 126, 8323 },
+{ 126, 8324 },{ 126, 8326 },{ 126, 8327 },{ 126, 8329 },
+{ 126, 8330 },{ 126, 8332 },{ 126, 8333 },{ 126, 8334 },
+{ 126, 8336 },{ 126, 8337 },{ 126, 8339 },{ 126, 8340 },
+{ 126, 8342 },{ 126, 8343 },{ 126, 8345 },{ 126, 8346 },
+{ 126, 8348 },{ 126, 8349 },{ 126, 8351 },{ 126, 8352 },
+{ 126, 8353 },{ 126, 8355 },{ 126, 8356 },{ 126, 8358 },
+{ 126, 8359 },{ 126, 8361 },{ 127, 8021 },{ 127, 8022 },
+{ 127, 8024 },{ 127, 8025 },{ 127, 8027 },{ 127, 8028 },
+{ 127, 8030 },{ 127, 8031 },{ 127, 8032 },{ 127, 8034 },
+{ 127, 8035 },{ 127, 8037 },{ 127, 8038 },{ 127, 8040 },
+{ 127, 8041 },{ 127, 8043 },{ 127, 8044 },{ 127, 8046 },
+{ 127, 8047 },{ 127, 8048 },{ 127, 8050 },{ 127, 8051 },
+{ 127, 8053 },{ 127, 8054 },{ 127, 8056 },{ 127, 8057 },
+{ 127, 8059 },{ 127, 8060 },{ 127, 8061 },{ 127, 8063 },
+{ 127, 8064 },{ 127, 8066 },{ 127, 8067 },{ 127, 8069 }
diff --git a/MCUME_pico2/picomsx/MSX.h b/MCUME_pico2/picomsx/MSX.h
new file mode 100644
index 0000000..00ac5f7
--- /dev/null
+++ b/MCUME_pico2/picomsx/MSX.h
@@ -0,0 +1,222 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                           MSX.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to the drivers **/
+/** and MSX emulation itself. See Z80.h for #defines        **/
+/** related to Z80 emulation.                               **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef MSX_H
+#define MSX_H
+
+#include "Z80.h"            /* Z80 CPU emulation             */
+#include "V9938.h"          /* V9938 VDP opcode emulation    */
+#include "AY8910.h"         /* AY8910 PSG emulation          */
+#include "YM2413.h"         /* YM2413 OPLL emulation         */
+#include "SCC.h"            /* Konami SCC chip emulation     */
+#include "I8255.h"          /* Intel 8255 PPI emulation      */
+#include "I8251.h"          /* Intel 8251 UART emulation     */
+
+#include <stdio.h>
+
+#define CPU_CLOCK    3580        /* CPU clock frequency, kHz */
+#define VDP_CLOCK    21480       /* VDP clock frequency, kHz */
+
+#define HPERIOD      1368        /* HPeriod, VDP cycles      */
+#define VPERIOD_PAL  (HPERIOD*313) /* PAL VPeriod, VDP ccls  */
+#define VPERIOD_NTSC (HPERIOD*262) /* NTSC VPeriod, VDP ccls */ 
+#define HREFRESH_240 960         /* 240dot scanline refresh  */
+#define HREFRESH_256 1024        /* 256dot scanline refresh  */
+
+#define CPU_VPERIOD  (VPERIOD_NTSC/6)
+#define CPU_V262     (VPERIOD_NTSC/6)
+#define CPU_V313     (VPERIOD_PAL/6)
+#define CPU_HPERIOD  (HPERIOD/6)
+#define CPU_H240     (HREFRESH_240/6)
+#define CPU_H256     (HREFRESH_256/6)
+
+#define INT_IE0     0x01
+#define INT_IE1     0x02
+#define INT_IE2     0x04
+
+#define PAGESIZE    0x4000L /* Size of a RAM page            */
+#define NORAM       0xFF    /* Byte to be returned from      */
+                            /* non-existing pages and ports  */
+#define MAXSCREEN   12      /* Highest screen mode supported */
+#define MAXSPRITE1  4       /* Sprites/line in SCREEN 1-3    */
+#define MAXSPRITE2  8       /* Sprites/line in SCREEN 4-8    */
+#define MAXDRIVES   2       /* Number of disk drives         */
+#define MAXDISKS    32      /* Number of disks for a drive   */
+#define MAXMAPPERS  7       /* Total defined MegaROM mappers */
+
+#define MAXCHANNELS (AY8910_CHANNELS+YM2413_CHANNELS)
+  /* Number of sound channels used by the emulation */
+
+/** Following macros can be used in screen drivers ***********/
+#define BigSprites    (VDP[1]&0x01)   /* Zoomed sprites      */
+#define Sprites16x16  (VDP[1]&0x02)   /* 16x16/8x8 sprites   */
+#define ScreenON      (VDP[1]&0x40)   /* Show screen         */
+#define SpritesOFF    (VDP[8]&0x02)   /* Don't show sprites  */
+#define SolidColor0   (VDP[8]&0x20)   /* Solid/Tran. COLOR 0 */
+#define PALVideo      (VDP[9]&0x02)   /* PAL/NTSC video      */
+#define FlipEvenOdd   (VDP[9]&0x04)   /* Flip even/odd pages */
+#define InterlaceON   (VDP[9]&0x08)   /* Interlaced screen   */
+#define ScanLines212  (VDP[9]&0x80)   /* 212/192 scanlines   */
+#define HScroll512    (VDP[25]&0x01)  /* HScroll both pages  */
+#define MaskEdges     (VDP[25]&0x02)  /* Mask 8-pixel edges  */
+#define ModeYJK       (VDP[25]&0x08)  /* YJK screen mode     */
+#define ModeYAE       (VDP[25]&0x10)  /* YJK/YAE screen mode */
+#define VScroll       VDP[23]
+#define HScroll       ((VDP[27]&0x07)|((int)(VDP[26]&0x3F)<<3))
+#define VAdjust       (-((signed char)(VDP[18])>>4))
+#define HAdjust       (-((signed char)(VDP[18]<<4)>>4))
+/*************************************************************/
+
+/** Variables used to control emulator behavior **************/
+extern byte Verbose;                  /* Debug msgs ON/OFF   */
+extern byte MSXVersion;               /* 0=MSX,1=MSX2,2=MSX2+*/
+extern byte ROMTypeA,ROMTypeB;        /* MegaROM types       */
+extern int  RAMPages,VRAMPages;       /* Number of RAM pages */
+extern int  VPeriod;                  /* CPU cycles / VBlank */
+extern int  HPeriod;                  /* CPU cycles / HBlank */
+extern byte UPeriod;                  /* Int-pts/Scr. update */
+extern byte JoyTypeA,JoyTypeB;        /* 0=No,1=Jstk,2/3=Mse */
+extern byte AutoFire;                 /* Autofire on [SPACE] */
+extern byte UseDrums;                 /* Drums for PSG noise */
+/*************************************************************/
+
+extern Z80  CPU;                      /* CPU state/registers */
+extern byte *VRAM;                    /* Video RAM           */
+extern byte VDP[64];                  /* VDP control reg-ers */
+extern byte VDPStatus[16];            /* VDP status reg-ers  */
+extern byte *ChrGen,*ChrTab,*ColTab;  /* VDP tables (screen) */
+extern byte *SprGen,*SprTab;          /* VDP tables (sprites)*/
+extern int  ChrGenM,ChrTabM,ColTabM;  /* VDP masks (screen)  */
+extern int  SprTabM;                  /* VDP masks (sprites) */
+extern byte FGColor,BGColor;          /* Colors              */
+extern byte XFGColor,XBGColor;        /* Alternative colors  */
+extern byte ScrMode;                  /* Current screen mode */
+extern int  ScanLine;                 /* Current scanline    */
+
+extern byte KeyMap[16];               /* Keyboard map        */
+extern byte ExitNow;                  /* 1: Exit emulator    */
+
+extern byte PSLReg;                   /* Primary slot reg.   */
+extern byte SSLReg;                   /* Secondary slot reg. */
+
+//extern char *DiskA;                   /* Drive A disk image  */
+//extern char *DiskB;                   /* Drive B disk image  */
+#ifdef unused
+extern char *SndName;                 /* Soundtrack log file */
+extern char *PrnName;                 /* Printer redir. file */
+extern char *CasName;                 /* Tape image file     */
+extern char *ComName;                 /* Serial redir. file  */
+extern int *CasStream;               /* Cassette I/O stream */
+#endif
+
+extern char *FontName;                /* Font file for text  */ 
+extern byte *FontBuf;                 /* Font for text modes */
+extern byte UseFont;                  /* 1: Use external font*/
+
+/** StartMSX() ***********************************************/
+/** Allocate memory, load ROM image, initialize hardware,   **/
+/** CPU and start the emulation. This function returns 0 in **/
+/** the case of failure.                                    **/
+/*************************************************************/
+int StartMSX(void);
+
+/** TrashMSX() ***********************************************/
+/** Free memory allocated by StartMSX().                    **/
+/*************************************************************/
+void TrashMSX(void);
+
+/** SaveState() **********************************************/
+/** Save emulation state to a .STA file.                    **/
+/*************************************************************/
+int SaveState(const char *FileName);
+
+/** LoadState() **********************************************/
+/** Load emulation state from a .STA file.                  **/
+/*************************************************************/
+int LoadState(const char *FileName);
+
+/** ChangeDisk() *********************************************/   
+/** Change disk image in a given drive. Closes current disk **/
+/** image if Name=0 was given. Returns 1 on success or 0 on **/
+/** failure. This function is part of generic disk drivers  **/
+/** in Disk.c. It is compiled when DISK is #defined.        **/
+/*************************************************************/
+#ifdef DISK
+byte ChangeDisk(byte ID,char *Name);
+#endif
+
+/** InitMachine() ********************************************/
+/** Allocate resources needed by the machine-dependent code.**/
+/************************************ TO BE WRITTEN BY USER **/
+int InitMachine(void);
+
+/** TrashMachine() *******************************************/
+/** Deallocate all resources taken by InitMachine().        **/
+/************************************ TO BE WRITTEN BY USER **/
+void TrashMachine(void);
+
+/** Keyboard() ***********************************************/
+/** This function is periodically called to poll keyboard.  **/
+/************************************ TO BE WRITTEN BY USER **/
+void Keyboard(void);
+
+/** Joystick() ***********************************************/
+/** Query position of a joystick connected to port N.       **/
+/** Returns 0.0.F2.F1.R.L.D.U.                              **/
+/************************************ TO BE WRITTEN BY USER **/
+byte Joystick(byte N);
+
+/** Mouse() **************************************************/
+/** Query coordinates of a mouse connected to port N.       **/
+/** Returns F2.F1.Y.Y.Y.Y.Y.Y.Y.Y.X.X.X.X.X.X.X.X.          **/
+/************************************ TO BE WRITTEN BY USER **/
+int Mouse(byte N);
+
+/** DiskPresent()/DiskRead()/DiskWrite() *********************/
+/*** These three functions are called to check for floppyd  **/
+/*** disk presence in the "drive", and to read/write given  **/
+/*** sector to the disk.                                    **/
+/************************************ TO BE WRITTEN BY USER **/
+byte DiskPresent(byte ID);
+byte DiskRead(byte ID,byte *Buf,int N);
+byte DiskWrite(byte ID,byte *Buf,int N);
+
+/** SetColor() ***********************************************/
+/** Set color N (0..15) to (R,G,B).                         **/
+/************************************ TO BE WRITTEN BY USER **/
+void SetColor(byte N,byte R,byte G,byte B);
+
+/** RefreshScreen() ******************************************/
+/** Refresh screen. This function is called in the end of   **/
+/** refresh cycle to show the entire screen.                **/
+/************************************ TO BE WRITTEN BY USER **/
+void RefreshScreen(void);
+
+/** RefreshLine#() *******************************************/
+/** Refresh line Y (0..191/211), on an appropriate SCREEN#, **/
+/** including sprites in this line.                         **/
+/************************************ TO BE WRITTEN BY USER **/
+//void RefreshLineTx80(byte Y);
+//void RefreshLine0(byte Y);
+//void RefreshLine1(byte Y);
+//void RefreshLine2(byte Y);
+//void RefreshLine3(byte Y);
+//void RefreshLine4(byte Y);
+//void RefreshLine5(byte Y);
+//void RefreshLine6(byte Y);
+//void RefreshLine7(byte Y);
+//void RefreshLine8(byte Y);
+//void RefreshLine10(byte Y);
+//void RefreshLine12(byte Y);
+
+#endif /* MSX_H */
diff --git a/MCUME_pico2/picomsx/Patch.c b/MCUME_pico2/picomsx/Patch.c
new file mode 100644
index 0000000..2ef6d1d
--- /dev/null
+++ b/MCUME_pico2/picomsx/Patch.c
@@ -0,0 +1,431 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                        Patch.c                          **/
+/**                                                         **/
+/** This file contains implementation for the PatchZ80()    **/
+/** function necessary for emulating MSX disk and tape IO.  **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "MSX.h"
+#include "Boot.h"
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h>
+
+#include "shared.h"
+
+
+#ifndef SEEK_CUR
+#define SEEK_CUR 1
+#endif
+
+void SSlot(byte Value); /* Used to switch secondary slots */
+
+/** PatchZ80() ***********************************************/
+/** Emulate BIOS calls. This function is called on an ED FE **/
+/** instruction to emulate disk/tape access, etc.           **/
+/*************************************************************/
+void PatchZ80(Z80 *R)
+{
+  static const byte TapeHeader[8] = { 0x1F,0xA6,0xDE,0xBA,0xCC,0x13,0x7D,0x74 };
+
+  static const struct
+  { int Sectors;byte Heads,Names,PerTrack,PerFAT,PerCluster; }
+  Info[8] =
+  {
+    {  720,1,112,9,2,2 },
+    { 1440,2,112,9,3,2 },
+    {  640,1,112,8,1,2 },
+    { 1280,2,112,8,2,2 },
+    {  360,1, 64,9,2,1 },
+    {  720,2,112,9,2,2 },
+    {  320,1, 64,8,1,1 },
+    {  640,2,112,8,1,2 }
+  };
+
+  byte Buf[512],Count,PS,SS,N,*P;
+  int J,I,Sector;
+  word Addr;
+
+  switch(R->PC.W-2)
+  {
+
+case 0x4010:
+/** PHYDIO: Read/write sectors to disk **************************
+*** Input:                                                    ***
+*** [F] CARRY=WRITE                  [A] Drive number (0=A:)  ***
+*** [B] Number of sectors to write   [C] Media descriptor     ***
+*** [DE] Logical sector number (starts at 0)                  ***
+*** [HL] Transfer address                                     ***
+*** Output:                                                   ***
+*** [F] CARRY=ERROR                  [A] If error: errorcode  ***
+*** [B] Number of sectors remaining (not read/written)        ***
+*** Error codes in [A] can be:                                ***
+*** 0 Write protected      8  Record not found                ***
+*** 2 Not ready            10 Write fault                     ***
+*** 4 Data (CRC) error     12 Other errors                    ***
+*** 6 Seek error                                              ***
+****************************************************************/
+{
+  //if(Verbose&0x04)
+  //  printf
+  //  (
+  //    "%s DISK %c: %d sectors starting from %04Xh [buffer at %04Xh]\n",
+  //    R->AF.B.l&C_FLAG? "WRITE":"READ",R->AF.B.h+'A',R->BC.B.h,
+  //    R->DE.W,R->HL.W
+  //  );
+
+  R->IFF|=1;
+  Addr  = R->HL.W;
+  Count = R->BC.B.h;
+
+  if(!DiskPresent(R->AF.B.h))
+  { R->AF.W=0x0201;return; }  /* No disk      -> "Not ready"        */
+  if((int)(R->DE.W)+Count>Info[R->BC.B.l-0xF8].Sectors)
+  { R->AF.W=0x0801;return; }  /* Wrong sector -> "Record not found" */
+
+  /* If data does not fit into 64kB address space, trim it */
+  if((int)(R->HL.W)+Count*512>0x10000) Count=(0x10000-R->HL.W)/512;
+
+  /* Save slot states */
+  PS=PSLReg;SS=SSLReg;
+
+  /* Turn on RAM in all slots */
+  OutZ80(0xA8,0xFF);
+  SSlot(0xAA);
+
+  if(R->AF.B.l&C_FLAG)
+    for(Sector=R->DE.W;Count--;Sector++) /* WRITE */
+    {
+      for(J=0;J<512;J++) Buf[J]=RdZ80(Addr++);
+
+      if(DiskWrite(R->AF.B.h,Buf,Sector)) R->BC.B.h--;
+      else
+      {
+        R->AF.W=0x0A01;
+        SSlot(SS);
+        OutZ80(0xA8,PS);
+        return;
+      }
+    }
+  else
+    for(Sector=R->DE.W;Count--;Sector++) /* READ */
+    {
+      if(DiskRead(R->AF.B.h,Buf,Sector)) R->BC.B.h--;
+      else
+      {
+        R->AF.W=0x0401;
+        SSlot(SS);
+        OutZ80(0xA8,PS);
+        return;
+      }
+
+      for(J=0;J<512;J++) WrZ80(Addr++,Buf[J]);
+    }
+
+  /* Restore slot states */
+  SSlot(SS);
+  OutZ80(0xA8,PS);
+
+  /* Return "Success" */
+  R->AF.B.l&=~C_FLAG;
+  return;
+}
+
+case 0x4013:
+/** DSKCHG: Check if the disk was changed ***********************
+*** Input:                                                    ***
+*** [A] Drive number (0=A:)       [B]  Media descriptor       ***
+*** [C] Media descriptor          [HL] Base address of DPB    ***
+*** Output:                                                   ***
+*** [F] CARRY=ERROR       [A] If error: errorcode (see DSKIO) ***
+*** [B] If success: 1=Unchanged, 0=Unknown, -1=Changed        ***
+*** Note:                                                     ***
+*** If the disk has been changed or may have been  changed    ***
+*** (unknown) read the boot sector or the FAT sector for disk ***
+*** media descriptor and transfer a new DPB as with GETDPB.   ***
+****************************************************************/
+{
+  //if(Verbose&0x04) printf("CHECK DISK %c\n",R->AF.B.h+'A');
+
+  R->IFF|=1;
+
+  /* If no disk, return "Not ready": */
+  if(!DiskPresent(R->AF.B.h)) { R->AF.W=0x0201;return; }
+
+  /* This requires some major work to be done: */
+  R->BC.B.h=0;R->AF.B.l&=~C_FLAG;
+
+  /* We continue with GETDPB now... */
+}
+
+case 0x4016:
+/** GETDPB: Disk format *****************************************
+*** Input:                                                    ***
+*** [A] Drive number   [B] 1st byte of FAT (media descriptor) ***
+*** [C] Media descriptor  [HL] Base address of DPB            ***
+*** Output:                                                   ***
+*** [HL+1] .. [HL+18] = DPB for specified drive               ***
+*** DPB consists of:                                          ***
+*** Name   Offset Size Description                            ***
+*** MEDIA    0     1   Media type (F8..FF)                    ***
+*** SECSIZ   1     2   Sector size (must be 2^n)              ***
+*** DIRMSK   3     1   (SECSIZE/32)-1                         ***
+*** DIRSHFT  4     1   Number of one bits in DIRMSK           ***
+*** CLUSMSK  5     1   (Sectors per cluster)-1                ***
+*** CLUSSHFT 6     1   (Number of one bits in CLUSMSK)+1      ***
+*** FIRFAT   7     2   Logical sector number of first FAT     ***
+*** FATCNT   8     1   Number of FATs                         ***
+*** MAXENT   A     1   Number of directory entries (max 254)  ***
+*** FIRREC   B     2   Logical sector number of first data    ***
+*** MAXCLUS  D     2   Number of clusters (not including      ***
+***                    reserved, FAT and directory sectors)+1 ***
+*** FATSIZ   F     1   Number of sectors used                 ***
+*** FIRDIR   10    2   FAT logical sector number of start of  ***
+***                    directory                              ***
+****************************************************************/
+{
+  int BytesPerSector,SectorsPerDisk,SectorsPerFAT,ReservedSectors;
+
+  /* If no disk, return "Not ready": */
+  if(!DiskPresent(R->AF.B.h))    { R->AF.W=0x0201;return; }
+  /* If can't read, return "Other error": */
+  if(!DiskRead(R->AF.B.h,Buf,0)) { R->AF.W=0x0C01;return; }
+
+  BytesPerSector  = (int)Buf[0x0C]*256+Buf[0x0B];
+  SectorsPerDisk  = (int)Buf[0x14]*256+Buf[0x13];
+  SectorsPerFAT   = (int)Buf[0x17]*256+Buf[0x16];
+  ReservedSectors = (int)Buf[0x0F]*256+Buf[0x0E];
+ 
+  Addr=R->HL.W+1;
+  WrZ80(Addr++,Buf[0x15]);             /* Format ID [F8h-FFh] */
+  WrZ80(Addr++,Buf[0x0B]);             /* Sector size         */
+  WrZ80(Addr++,Buf[0x0C]);
+  J=(BytesPerSector>>5)-1;
+  for(I=0;J&(1<<I);I++);
+  WrZ80(Addr++,J);                     /* Directory mask/shft */
+  WrZ80(Addr++,I);
+  J=Buf[0x0D]-1;
+  for(I=0;J&(1<<I);I++);
+  WrZ80(Addr++,J);                     /* Cluster mask/shift  */
+  WrZ80(Addr++,I+1);
+  WrZ80(Addr++,Buf[0x0E]);             /* Sector # of 1st FAT */
+  WrZ80(Addr++,Buf[0x0F]);
+  WrZ80(Addr++,Buf[0x10]);             /* Number of FATs      */
+  WrZ80(Addr++,Buf[0x11]);             /* Number of dirent-s  */
+  J=ReservedSectors+Buf[0x10]*SectorsPerFAT;
+  J+=32*Buf[0x11]/BytesPerSector;
+  WrZ80(Addr++,J&0xFF);                /* Sector # of data    */
+  WrZ80(Addr++,(J>>8)&0xFF);
+  J=(SectorsPerDisk-J)/Buf[0x0D];
+  WrZ80(Addr++,J&0xFF);                /* Number of clusters  */
+  WrZ80(Addr++,(J>>8)&0xFF);
+  WrZ80(Addr++,Buf[0x16]);             /* Sectors per FAT     */
+  J=ReservedSectors+Buf[0x10]*SectorsPerFAT;
+  WrZ80(Addr++,J&0xFF);                /* Sector # of dir.    */
+  WrZ80(Addr,(J>>8)&0xFF);
+
+  /* Return success      */
+  R->AF.B.l&=~C_FLAG;
+  return;
+}
+
+case 0x401C:
+/** DSKFMT: Disk format *****************************************
+*** Input:                                                    ***
+*** [A]  Specified choice (1-9)      [D]  Drive number (0=A:) ***
+*** [HL] Begin address of work area  [BC] Length of work area ***
+*** Output:                                                   ***
+*** [F] CARRY=ERROR                                           ***
+*** Notes:                                                    ***
+*** 1) Also writes a MSX boot sector at sector 0, clears all  ***
+***    FATs (media descriptor at first byte, 0FFh at second/  ***
+***    third byte and rest zero) and clears the directory     ***
+***    filling it with zeros.                                 ***
+*** 2) Error codes are:                                       ***
+***    0 Write protected       10 Write fault                 ***
+***    2 Not ready             12 Bad parameter               ***
+***    4 Data (CRC) error      14 Insufficient memory         ***
+***    6 Seek error            16 Other errors                ***
+***    8 Record not found                                     ***
+****************************************************************/
+{
+  R->IFF|=1;
+
+  /* If invalid choice, return "Bad parameter": */
+  if(!R->AF.B.h||(R->AF.B.h>2)) { R->AF.W=0x0C01;return; }
+  /* If no disk, return "Not ready": */
+  if(!DiskPresent(R->DE.B.h)) { R->AF.W=0x0201;return; }
+
+  /* Fill bootblock with data: */
+  P=BootBlock+3;
+  N=2-R->AF.B.h;
+  memcpy(P,"fMSXdisk",8);P+=10;    /* Manufacturer's ID   */
+  *P=Info[N].PerCluster;P+=4;      /* Sectors per cluster */
+  *P++=Info[N].Names;*P++=0x00;    /* Number of names     */
+  *P++=Info[N].Sectors&0xFF;       /* Number of sectors   */
+  *P++=(Info[N].Sectors>>8)&0xFF;
+  *P++=N+0xF8;                     /* Format ID [F8h-FFh] */
+  *P++=Info[N].PerFAT;*P++=0x00;   /* Sectors per FAT     */
+  *P++=Info[N].PerTrack;*P++=0x00; /* Sectors per track   */
+  *P++=Info[N].Heads;*P=0x00;      /* Number of heads     */
+
+  /* If can't write bootblock, return "Write protected": */
+  if(!DiskWrite(R->DE.B.h,BootBlock,0)) { R->AF.W=0x0001;return; };
+
+  /* Writing FATs: */
+  for(Sector=1,J=0;J<2;J++)
+  {
+    Buf[0]=N+0xF8;
+    Buf[1]=Buf[2]=0xFF;
+    memset(Buf+3,0x00,509);
+
+    if(!DiskWrite(R->DE.B.h,Buf,Sector++)) { R->AF.W=0x0A01;return; }
+
+    memset(Buf,0x00,512);
+
+    for(I=Info[N].PerFAT;I>1;I--)
+      if(!DiskWrite(R->DE.B.h,Buf,Sector++)) { R->AF.W=0x0A01;return; }
+  }
+
+  J=Info[N].Names/16;                     /* Directory size */
+  I=Info[N].Sectors-2*Info[N].PerFAT-J-1; /* Data size */
+
+  for(memset(Buf,0x00,512);J;J--)
+    if(!DiskWrite(R->DE.B.h,Buf,Sector++)) { R->AF.W=0x0A01;return; }
+  for(memset(Buf,0xFF,512);I;I--)
+    if(!DiskWrite(R->DE.B.h,Buf,Sector++)) { R->AF.W=0x0A01;return; }
+
+  /* Return success      */
+  R->AF.B.l&=~C_FLAG;
+  return;
+}
+
+case 0x401F:
+/** DRVOFF: Stop drives *****************************************
+*** Input:  None                                              ***
+*** Output: None                                              ***
+****************************************************************/
+  return;
+
+case 0x00E1:
+/** TAPION: Open for read and read header ***********************
+****************************************************************/
+{
+  long Pos;
+
+  //if(Verbose&0x04) printf("TAPE: Looking for header...");
+
+  R->AF.B.l|=C_FLAG;
+#ifdef unused
+  if(CasStream)
+  {
+    Pos=ftell(CasStream);
+    if(Pos&7)
+      if(fseek(CasStream,8-(Pos&7),SEEK_CUR))
+      {
+        if(Verbose&0x04) puts("FAILED");
+        rewind(CasStream);return;
+      }
+
+    while(fread(Buf,1,8,CasStream)==8)
+      if(!memcmp(Buf,TapeHeader,8))
+      {
+        if(Verbose&0x04) puts("OK");
+        R->AF.B.l&=~C_FLAG;return;
+      }
+
+    rewind(CasStream);
+  }
+
+  if(Verbose&0x04) puts("FAILED");
+#endif
+  return;
+}
+
+case 0x00E4:
+/** TAPIN: Read tape ********************************************
+****************************************************************/
+{
+  R->AF.B.l|=C_FLAG;
+
+#ifdef unused
+  if(CasStream)
+  {
+    J=fgetc(CasStream);
+    if(J<0) rewind(CasStream);
+    else { R->AF.B.h=J;R->AF.B.l&=~C_FLAG; }
+  }
+#endif
+
+  return;
+}
+
+case 0x00E7:
+/** TAPIOF: *****************************************************
+****************************************************************/
+  R->AF.B.l&=~C_FLAG;
+  return;
+
+case 0x00EA:
+/** TAPOON: *****************************************************
+****************************************************************/
+{
+  long Pos;
+
+  R->AF.B.l|=C_FLAG;
+
+#ifdef unused
+  if(CasStream)
+  {
+    Pos=ftell(CasStream);
+    if(Pos&7)
+      if(fseek(CasStream,8-(Pos&7),SEEK_CUR))
+      { R->AF.B.l|=C_FLAG;return; }
+
+    fwrite(TapeHeader,1,8,CasStream);
+    R->AF.B.l&=~C_FLAG;
+  }   
+#endif
+
+  return;
+}
+
+case 0x00ED:
+/** TAPOUT: Write tape ******************************************
+****************************************************************/
+  R->AF.B.l|=C_FLAG;
+
+#ifdef unused
+  if(CasStream)
+  {
+    fputc(R->AF.B.h,CasStream);
+    R->AF.B.l&=~C_FLAG;
+  }
+#endif
+
+  return;
+
+case 0x00F0:
+/** TAPOOF: *****************************************************
+****************************************************************/
+  R->AF.B.l&=~C_FLAG;
+  return;
+
+case 0x00F3:
+/** STMOTR: *****************************************************
+****************************************************************/
+  R->AF.B.l&=~C_FLAG;
+  return;
+
+default:
+  //printf("Unknown BIOS trap called at PC=%04Xh\n",R->PC.W-2);
+  break;
+  }
+}
diff --git a/MCUME_pico2/picomsx/SCC.c b/MCUME_pico2/picomsx/SCC.c
new file mode 100644
index 0000000..ec8aa8e
--- /dev/null
+++ b/MCUME_pico2/picomsx/SCC.c
@@ -0,0 +1,187 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                           SCC.c                         **/
+/**                                                         **/
+/** This file contains emulation for the SCC sound chip     **/
+/** produced by Konami.                                     **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "SCC.h"
+#include "Sound.h"
+#include <string.h>
+
+/** ResetSCC() ***********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void ResetSCC(register SCC *D,int First)
+{
+  int J;
+
+  /* Reset registers */
+  memset(D->R,0x00,sizeof(D->R));
+
+  /* Set instruments, frequencies, volumes */
+  for(J=0;J<SCC_CHANNELS;J++)
+  {
+    SetSound(0+First,SND_MELODIC);
+    D->Freq[J]=D->Volume[J]=0;
+  }
+
+  D->First    = First;
+  D->Sync     = SCC_ASYNC;
+  D->Changed  = 0x00;
+  D->WChanged = 0x00;
+}
+
+/** ReadSCC() ************************************************/
+/** Call this function to read contents of the generic SCC  **/
+/** sound chip registers.                                   **/
+/*************************************************************/
+byte ReadSCC(register SCC *D,register byte R)
+{
+  return(R<0x80? D->R[R]:0xFF);
+}
+           
+/** ReadSCCP() ***********************************************/
+/** Call this function to read contents of the newer SCC+   **/
+/** sound chip registers.                                   **/
+/*************************************************************/
+byte ReadSCCP(register SCC *D,register byte R)
+{
+  return(R<0xA0? D->R[R]:0xFF);
+}
+           
+/** WriteSCC() ***********************************************/
+/** Call this function to output a value V into the generic **/
+/** SCC sound chip.                                         **/
+/*************************************************************/
+void WriteSCC(register SCC *D,register byte R,register byte V)
+{
+  /* Prevent rollover */
+  if(R>=0xE0) return;
+  /* Generic SCC has one waveform less than SCC+ */
+  if(R>=0x80) { WriteSCCP(D,R+0x20,V);return; }
+  /* The last waveform applies to both channels 3 and 4 */
+  if(R>=0x60) { WriteSCCP(D,R,V);WriteSCCP(D,R+0x20,V);return; }
+  /* Other waveforms are the same */
+  WriteSCCP(D,R,V);
+}
+
+/** WriteSCCP() **********************************************/
+/** Call this function to output a value V into the newer   **/
+/** SCC+ sound chip.                                        **/
+/*************************************************************/
+void WriteSCCP(register SCC *D,register byte R,register byte V)
+{
+  register int J;
+  register byte I;
+
+  /* Exit if no change */
+  if(V==D->R[R]) return;
+
+  if((R&0xE0)==0xA0)
+  {
+    /* Emulate melodic features */
+
+    /* Save active channel mask in I */
+    I=D->R[0xAF];
+    /* Write to a register */
+    R&=0xEF;
+    D->R[R]=D->R[R+0x10]=V;
+
+    /* Melodic register number 0..15 */
+    R&=0x0F;
+    switch(R)
+    {
+      case 0: case 1: case 2: case 3: case 4:
+      case 5: case 6: case 7: case 8: case 9:
+        /* Exit if the channel is silenced */
+        if(!(I&(1<<(R>>1)))) return;
+        /* Go to the first register of the pair */
+        R=(R&0xFE)+0xA0;
+        /* Compute frequency */
+        J=((int)(D->R[R+1]&0x0F)<<8)+D->R[R];
+        /* Compute channel number */
+        R=(R&0x0F)>>1;
+        /* Assign frequency */
+        D->Freq[R]=J? SCC_BASE/J:0;
+        /* Compute changed channels mask */
+        D->Changed|=1<<R;
+        break;
+
+      case 10: case 11: case 12: case 13: case 14:
+        /* Compute channel number */
+        R-=10;
+        /* Compute and assign new volume */
+        D->Volume[R]=255*(V&0x0F)/15;
+        /* Compute changed channels mask */
+        D->Changed|=(1<<R)&I;
+        break;
+
+      case 15:
+        /* Find changed channels */
+        R=(V^I)&0x1F;
+        D->Changed|=R;
+        /* Update frequencies */
+        for(I=0;R&&(I<SCC_CHANNELS);I++,R>>=1,V>>=1)
+          if(R&1)
+          {
+            if(!(V&1)) D->Freq[I]=0;
+            else
+            {
+              J=I*2+0xA0;
+              J=((int)(D->R[J+1]&0x0F)<<8)+D->R[J];
+              D->Freq[I]=J? SCC_BASE/J:0;
+            }
+          }
+        break;
+
+      default:
+        /* Wrong register, do nothing */
+        return;
+    }
+  }
+  else
+  {
+    /* Emulate wave table features */
+
+    /* Write data to SCC */
+    D->R[R]=V;
+    /* Wrong register, do nothing */
+    if(R>=0xA0) return;
+    /* Mark channel waveform as changed */
+    D->WChanged|=1<<(R>>5);
+  }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&(D->Changed||D->WChanged)) SyncSCC(D,SCC_FLUSH);
+}
+
+/** SyncSCC() ************************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be SCC_SYNC/SCC_ASYNC to set/reset sync, or      **/
+/** SCC_FLUSH to leave sync mode as it is.                  **/
+/*************************************************************/
+void SyncSCC(register SCC *D,register byte Sync)
+{
+  register int J,I;
+
+  if(Sync!=SCC_FLUSH) D->Sync=Sync;
+
+  /* Modify waveforms */
+  for(J=0,I=D->WChanged;I&&(J<SCC_CHANNELS);J++,I>>=1)
+    if(I&1) SetWave(J+D->First,(signed char *)(D->R+(J<<5)),32,0);
+
+  /* Modify frequencies and volumes */
+  for(J=0,I=D->Changed;I&&(J<SCC_CHANNELS);J++,I>>=1)
+    if(I&1) Sound(J+D->First,D->Freq[J],D->Volume[J]);
+
+  D->Changed=D->WChanged=0x00;
+}
diff --git a/MCUME_pico2/picomsx/SCC.h b/MCUME_pico2/picomsx/SCC.h
new file mode 100644
index 0000000..f9d8ae9
--- /dev/null
+++ b/MCUME_pico2/picomsx/SCC.h
@@ -0,0 +1,80 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                           SCC.h                         **/
+/**                                                         **/
+/** This file contains definitions and declarations for     **/
+/** routines in SCC.c.                                      **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef SCC_H
+#define SCC_H
+
+#define SCC_BASE     111861    /* Base frequency for SCC     */
+#define SCC_CHANNELS 5         /* 5 melodic channels         */
+
+#define SCC_ASYNC    0         /* Asynchronous emulation     */
+#define SCC_SYNC     1         /* Synchronous emulation mode */
+#define SCC_FLUSH    2         /* Flush buffers only         */
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** SCC ******************************************************/
+/** This data structure stores SCC state.                   **/
+/*************************************************************/
+typedef struct
+{
+  byte R[256];                /* SCC register contents       */
+  int Freq[SCC_CHANNELS];     /* Frequencies (0 for off)     */
+  int Volume[SCC_CHANNELS];   /* Volumes (0..255)            */
+  int First;                  /* First used Sound() channel  */
+  byte Changed;               /* Bitmap of changed channels  */
+  byte WChanged;              /* Bitmap of changed waveforms */
+  byte Sync;                  /* SCC_SYNC/SCC_ASYNC          */
+} SCC;
+
+/** ResetSCC() ***********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void ResetSCC(register SCC *D,int First);
+
+/** ReadSCC() ************************************************/
+/** Call this function to read contents of the generic SCC  **/
+/** sound chip registers.                                   **/
+/*************************************************************/
+byte ReadSCC(register SCC *D,register byte R);
+
+/** ReadSCCP() ***********************************************/
+/** Call this function to read contents of the newer SCC+   **/
+/** sound chip registers.                                   **/
+/*************************************************************/
+byte ReadSCCP(register SCC *D,register byte R);
+           
+/** WriteSCC() ***********************************************/
+/** Call this function to output a value V into the generic **/
+/** SCC sound chip.                                         **/
+/*************************************************************/
+void WriteSCC(register SCC *D,register byte R,register byte V);
+
+/** WriteSCCP() **********************************************/
+/** Call this function to output a value V into the newer   **/
+/** SCC+ sound chip.                                        **/
+/*************************************************************/
+void WriteSCCP(register SCC *D,register byte R,register byte V);
+
+/** SyncSCC() ************************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be SCC_SYNC/SCC_ASYNC to set/reset sync, or      **/
+/** SCC_FLUSH to leave sync mode as it is.                  **/
+/*************************************************************/
+void SyncSCC(register SCC *D,register byte Sync);
+
+#endif /* SCC_H */
diff --git a/MCUME_pico2/picomsx/Sound.c b/MCUME_pico2/picomsx/Sound.c
new file mode 100644
index 0000000..9221fa7
--- /dev/null
+++ b/MCUME_pico2/picomsx/Sound.c
@@ -0,0 +1,479 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                          Sound.c                        **/
+/**                                                         **/
+/** This file file implements core part of the sound API    **/
+/** and functions needed to log soundtrack into a MIDI      **/
+/** file. See Sound.h for declarations.                     **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#include "Sound.h"
+
+#include <stdio.h>
+#include <string.h>
+
+#ifdef UNIX
+#include <unistd.h>
+#endif
+
+typedef unsigned char byte;
+typedef unsigned short word;
+
+struct SndDriverStruct SndDriver =
+{
+  (void (*)(int,int))0,
+  (void (*)(int,int))0,
+  (void (*)(int,int))0,
+  (void (*)(int,int,int))0,
+  (void (*)(int,const signed char *,int,int))0
+};
+
+#ifdef unused
+static const struct { byte Note;word Wheel; } Freqs[4096] =
+{
+#include "MIDIFreq.h"
+};
+#endif
+
+static const int Programs[5] =
+{
+  80,  /* SND_MELODIC/SND_RECTANGLE */
+  80,  /* SND_TRIANGLE */
+  122, /* SND_NOISE */
+  122, /* SND_PERIODIC */
+  80   /* SND_WAVE */
+};
+
+#ifdef unused
+static struct
+{
+  int Type;
+  int Note;
+  int Pitch;
+  int Level;
+} CH[MIDI_CHANNELS];
+
+static const char *LogName  = 0;
+static int  Logging   = MIDI_OFF;
+static int  TickCount = 0;
+static int  LastMsg   = -1;
+static FILE *MIDIOut  = 0;
+
+static void MIDISound(int Channel,int Freq,int Volume);
+static void MIDISetSound(int Channel,int Type);
+static void MIDIDrum(int Type,int Force);
+static void MIDIMessage(byte D0,byte D1,byte D2);
+static void NoteOn(byte Channel,byte Note,byte Level);
+static void NoteOff(byte Channel);
+static void WriteDelta(void);
+static void WriteTempo(int Freq);
+
+/** SHIFT() **************************************************/
+/** Make MIDI channel#10 last, as it is normally used for   **/
+/** percussion instruments only and doesn't sound nice.     **/
+/*************************************************************/
+#define SHIFT(Ch) (Ch==15? 9:Ch>8? Ch+1:Ch)
+#endif
+
+/** Sound() **************************************************/
+/** Generate sound of given frequency (Hz) and volume       **/
+/** (0..255) via given channel. Setting Freq=0 or Volume=0  **/
+/** turns sound off.                                        **/
+/*************************************************************/
+void Sound(int Channel,int Freq,int Volume)
+{
+  if(Channel<0) return;
+  Freq   = Freq<0? 0:Freq;
+  Volume = Volume<0? 0:Volume>255? 255:Volume;
+
+  /* Call sound driver if present */
+  if(SndDriver.Sound) (*SndDriver.Sound)(Channel,Freq,Volume);
+
+#ifdef unused
+  /* Log sound to MIDI file */
+  MIDISound(Channel,Freq,Volume);
+#endif  
+}
+
+/** Drum() ***************************************************/
+/** Hit a drum of given type with given force (0..255).     **/
+/** MIDI drums can be used by ORing their numbers with      **/
+/** SND_MIDI.                                               **/
+/*************************************************************/
+void Drum(int Type,int Force)
+{
+  Force = Force<0? 0:Force>255? 255:Force;
+
+  if(SndDriver.Drum) (*SndDriver.Drum)(Type,Force);
+
+#ifdef unused
+  /* Log drum to MIDI file */
+  MIDIDrum(Type,Force);
+#endif  
+}
+
+/** SetSound() ***********************************************/
+/** Set sound type at a given channel. MIDI instruments can **/
+/** be set directly by ORing their numbers with SND_MIDI.   **/
+/*************************************************************/
+void SetSound(int Channel,int Type)
+{
+  if(Channel<0) return;
+
+  if(SndDriver.SetSound) (*SndDriver.SetSound)(Channel,Type);
+
+#ifdef unused
+  /* Log instrument change to MIDI file */
+  MIDISetSound(Channel,Type);
+#endif  
+}
+
+/** SetChannels() ********************************************/
+/** Set master volume (0..255) and switch channels on/off.  **/
+/** Each channel N has corresponding bit 2^N in Switch. Set **/
+/** or reset this bit to turn the channel on or off.        **/ 
+/*************************************************************/
+void SetChannels(int Volume,int Switch)
+{
+  Volume = Volume<0? 0:Volume>255? 255:Volume;
+
+  if(SndDriver.SetChannels) (*SndDriver.SetChannels)(Volume,Switch);
+}
+
+/** SetWave() ************************************************/
+/** Set waveform for a given channel. The channel will be   **/
+/** marked with sound type SND_WAVE. Set Rate=0 if you want **/
+/** waveform to be an instrument or set it to the waveform  **/
+/** own playback rate.                                      **/
+/*************************************************************/
+void SetWave(int Channel,const signed char *Data,int Length,int Rate)
+{
+  if((Channel<0)||(Length<=0)) return;
+
+  if(SndDriver.SetWave) (*SndDriver.SetWave)(Channel,Data,Length,Rate);
+
+#ifdef unused
+  /* Log instrument change to MIDI file */
+  MIDISetSound(Channel,Rate? -1:SND_MELODIC);
+#endif  
+}
+
+#ifdef unused
+/** InitMIDI() ***********************************************/
+/** Initialize soundtrack logging into MIDI file FileName.  **/
+/** Repeated calls to InitMIDI() will close current MIDI    **/
+/** file and continue logging into a new one.               **/ 
+/*************************************************************/
+
+void InitMIDI(const char *FileName)
+{
+  int WasLogging,J;
+
+  /* Must pass a name! */
+  if(!FileName) return;
+
+  /* Memorize logging status */
+  WasLogging=Logging;
+
+  /* If MIDI logging in progress, close current file */
+  if(MIDIOut) TrashMIDI();
+
+  /* Clear instrument types */
+  for(J=0;J<MIDI_CHANNELS;J++) CH[J].Type=-1;
+
+  /* Set log file name and ticks/second parameter, no logging yet */
+  //LogName   = FileName;
+  Logging   = MIDI_OFF;
+  LastMsg   = -1;
+  TickCount = 0;
+  MIDIOut   = 0;
+
+  /* If was logging, restart */
+  if(WasLogging) MIDILogging(MIDI_ON);
+}
+
+/** TrashMIDI() **********************************************/
+/** Finish logging soundtrack and close the MIDI file.      **/
+/*************************************************************/
+void TrashMIDI(void)
+{
+  long Length;
+  int J;
+
+  /* If not logging, drop out */
+  if(!MIDIOut) return;
+  /* Turn sound off */
+  for(J=0;J<MIDI_CHANNELS;J++) NoteOff(J);
+  /* End of track */
+  MIDIMessage(0xFF,0x2F,0x00);
+  /* Put track length in file */
+  fseek(MIDIOut,0,SEEK_END);
+  Length=ftell(MIDIOut)-22;
+  fseek(MIDIOut,18,SEEK_SET);
+  fputc((Length>>24)&0xFF,MIDIOut);
+  fputc((Length>>16)&0xFF,MIDIOut);
+  fputc((Length>>8)&0xFF,MIDIOut);
+  fputc(Length&0xFF,MIDIOut);
+  /* Done logging */
+  fclose(MIDIOut);
+  Logging   = MIDI_OFF;
+  LastMsg   = -1;
+  TickCount = 0;
+  MIDIOut   = 0;
+}
+
+/** MIDILogging() ********************************************/
+/** Turn soundtrack logging on/off and return its current   **/
+/** status. Possible values of Switch are MIDI_OFF (turn    **/
+/** logging off), MIDI_ON (turn logging on), MIDI_TOGGLE    **/
+/** (toggle logging), and MIDI_QUERY (just return current   **/
+/** state of logging).                                      **/
+/*************************************************************/
+int MIDILogging(int Switch)
+{
+  static const char MThd[] = "MThd\0\0\0\006\0\0\0\1";
+                           /* ID  DataLen   Fmt Trks */
+  static const char MTrk[] = "MTrk\0\0\0\0";
+                           /* ID  TrkLen   */
+  int J,I;
+
+  /* Toggle logging if requested */
+  if(Switch==MIDI_TOGGLE) Switch=!Logging;
+
+  if((Switch==MIDI_ON)||(Switch==MIDI_OFF))
+    if(Switch^Logging)
+    {
+      /* When turning logging off, silence all channels */
+      if(!Switch&&MIDIOut)
+        for(J=0;J<MIDI_CHANNELS;J++) NoteOff(J);
+
+      /* When turning logging on, open MIDI file */
+      if(Switch&&!MIDIOut&&LogName)
+      {
+        /* No messages have been sent yet */
+        LastMsg=-1;
+
+        /* Clear all storage */
+        for(J=0;J<MIDI_CHANNELS;J++)
+          CH[J].Note=CH[J].Pitch=CH[J].Level=-1;
+
+        /* Open new file and write out the header */
+        MIDIOut=fopen(LogName,"wb");
+        if(!MIDIOut) return(MIDI_OFF);
+        if(fwrite(MThd,1,12,MIDIOut)!=12)
+        { fclose(MIDIOut);MIDIOut=0;return(MIDI_OFF); }
+        fputc((MIDI_DIVISIONS>>8)&0xFF,MIDIOut);
+        fputc(MIDI_DIVISIONS&0xFF,MIDIOut);
+        if(fwrite(MTrk,1,8,MIDIOut)!=8)
+        { fclose(MIDIOut);MIDIOut=0;return(MIDI_OFF); }
+
+        /* Write out the tempo */
+        WriteTempo(MIDI_DIVISIONS);
+      }
+
+      /* Turn logging off on failure to open MIDIOut */
+      if(!MIDIOut) Switch=MIDI_OFF;
+
+      /* Assign new switch value */
+      Logging=Switch;
+
+      /* If switching logging on... */
+      if(Switch)
+      {
+        /* Start logging without a pause */
+        TickCount=0;
+
+        /* Write instrument changes */
+        for(J=0;J<MIDI_CHANNELS;J++)
+          if((CH[J].Type>=0)&&(CH[J].Type&0x10000))
+          {
+            I=CH[J].Type&~0x10000;
+            CH[J].Type=-1;
+            MIDISetSound(J,I);
+          }
+      }
+    }
+
+  /* Return current logging status */
+  return(Logging);
+}
+
+/** MIDITicks() **********************************************/
+/** Log N 1ms MIDI ticks.                                   **/
+/*************************************************************/
+void MIDITicks(int N)
+{
+  if(Logging&&MIDIOut&&(N>0)) TickCount+=N;
+}
+
+/** MIDISound() **********************************************/
+/** Set sound frequency (Hz) and volume (0..255) for a      **/
+/** given channel.                                          **/
+/*************************************************************/
+void MIDISound(int Channel,int Freq,int Volume)
+{
+  int MIDIVolume,MIDINote,MIDIWheel;
+
+  /* If logging off, file closed, or invalid channel, drop out */
+  if(!Logging||!MIDIOut||(Channel>=MIDI_CHANNELS-1)||(Channel<0)) return;
+  /* Frequency must be in range */
+  if((Freq<MIDI_MINFREQ)||(Freq>MIDI_MAXFREQ)) Freq=0;
+  /* Volume must be in range */
+  if(Volume<0) Volume=0; else if(Volume>255) Volume=255;
+  /* Instrument number must be valid */
+  if(CH[Channel].Type<0) Freq=0;
+
+  if(!Volume||!Freq) NoteOff(Channel);
+  else
+  {
+    /* SND_TRIANGLE is twice quieter than SND_MELODIC */
+    if(CH[Channel].Type==SND_TRIANGLE) Volume=(Volume+1)/2;
+    /* Compute MIDI note parameters */
+    MIDIVolume = (127*Volume+128)/255;
+    MIDINote   = Freqs[Freq/3].Note;
+    MIDIWheel  = Freqs[Freq/3].Wheel;
+
+    /* Play new note */
+    NoteOn(Channel,MIDINote,MIDIVolume);
+
+    /* Change pitch */
+    if(CH[Channel].Pitch!=MIDIWheel)
+    {
+      MIDIMessage(0xE0+SHIFT(Channel),MIDIWheel&0x7F,(MIDIWheel>>7)&0x7F);
+      CH[Channel].Pitch=MIDIWheel;
+    }
+  }
+}
+
+/** MIDISetSound() *******************************************/
+/** Set sound type for a given channel.                     **/
+/*************************************************************/
+void MIDISetSound(int Channel,int Type)
+{
+  /* Channel must be valid */
+  if((Channel>=MIDI_CHANNELS-1)||(Channel<0)) return;
+
+  /* If instrument changed... */
+  if(CH[Channel].Type!=Type)
+  {
+    /* If logging off or file closed, drop out */
+    if(!Logging||!MIDIOut) CH[Channel].Type=Type|0x10000;
+    else
+    {
+      CH[Channel].Type=Type;
+      if(Type<0) NoteOff(Channel);
+      else
+      {
+        Type=Type&SND_MIDI? (Type&0x7F):Programs[Type%5];
+        MIDIMessage(0xC0+SHIFT(Channel),Type,255);
+      }
+    }
+  }
+}
+
+/** MIDIDrum() ***********************************************/
+/** Hit a drum of a given type with given force.            **/
+/*************************************************************/
+void MIDIDrum(int Type,int Force)
+{
+  /* If logging off or invalid channel, drop out */
+  if(!Logging||!MIDIOut) return;
+  /* The only non-MIDI drum is a click ("Low Wood Block") */
+  Type=Type&DRM_MIDI? (Type&0x7F):77;
+  MIDIMessage(0x99,Type,(Force&0xFF)/2);
+}
+
+/** MIDIMessage() ********************************************/
+/** Write out a MIDI message.                               **/
+/*************************************************************/
+void MIDIMessage(byte D0,byte D1,byte D2)
+{
+  /* Write number of ticks that passed */
+  WriteDelta();
+
+  /* Write out the command */
+  if(D0!=LastMsg) { LastMsg=D0;fputc(D0,MIDIOut); }
+
+  /* Write out the arguments */
+  if(D1<128)
+  {
+    fputc(D1,MIDIOut);
+    if(D2<128) fputc(D2,MIDIOut);
+  }
+}
+
+/** NoteOn() *************************************************/
+/** Turn on a note on a given channel.                      **/
+/*************************************************************/
+void NoteOn(byte Channel,byte Note,byte Level)
+{
+  Note  = Note>0x7F? 0x7F:Note;
+  Level = Level>0x7F? 0x7F:Level;
+
+  if((CH[Channel].Note!=Note)||(CH[Channel].Level!=Level))
+  {
+    if((CH[Channel].Note>=0)&&(CH[Channel].Note!=Note)) NoteOff(Channel);
+    MIDIMessage(0x90+SHIFT(Channel),Note,Level);
+    CH[Channel].Note=Note;
+    CH[Channel].Level=Level;
+  }
+}
+
+/** NoteOff() ************************************************/
+/** Turn off a note on a given channel.                     **/
+/*************************************************************/
+void NoteOff(byte Channel)
+{
+  if(CH[Channel].Note>=0)
+  {
+    MIDIMessage(0x80+SHIFT(Channel),CH[Channel].Note,127);
+    CH[Channel].Note=-1;
+  }
+}
+
+/** WriteDelta() *********************************************/
+/** Write number of ticks since the last MIDI command and   **/
+/** reset the counter.                                      **/
+/*************************************************************/
+void WriteDelta(void)
+{
+  if(TickCount<128) fputc(TickCount,MIDIOut);
+  else
+  {
+    if(TickCount<128*128)
+    {
+      fputc((TickCount>>7)|0x80,MIDIOut);
+      fputc(TickCount&0x7F,MIDIOut);
+    }
+    else
+    {
+      fputc(((TickCount>>14)&0x7F)|0x80,MIDIOut);
+      fputc(((TickCount>>7)&0x7F)|0x80,MIDIOut);
+      fputc(TickCount&0x7F,MIDIOut);
+    }
+  }
+
+  TickCount=0;
+}
+
+/** WriteTempo() *********************************************/
+/** Write out soundtrack tempo (Hz).                        **/
+/*************************************************************/
+void WriteTempo(int Freq)
+{
+  int J;
+
+  J=500000*MIDI_DIVISIONS*2/Freq;
+  WriteDelta();
+  fputc(0xFF,MIDIOut);
+  fputc(0x51,MIDIOut);
+  fputc(0x03,MIDIOut);
+  fputc((J>>16)&0xFF,MIDIOut);
+  fputc((J>>8)&0xFF,MIDIOut);
+  fputc(J&0xFF,MIDIOut);
+}
+#endif
diff --git a/MCUME_pico2/picomsx/Sound.h b/MCUME_pico2/picomsx/Sound.h
new file mode 100644
index 0000000..9103ca5
--- /dev/null
+++ b/MCUME_pico2/picomsx/Sound.h
@@ -0,0 +1,152 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                          Sound.h                        **/
+/**                                                         **/
+/** This file defines standard sound generation API and     **/
+/** functions needed to log soundtrack into a MIDI file.    **/
+/** See Sound.c and the sound drivers for the code.         **/ 
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2003                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef SOUND_H
+#define SOUND_H
+
+                               /* SetSound() arguments:      */
+#define SND_MELODIC     0      /* Melodic sound (default)    */
+#define SND_RECTANGLE   0      /* Rectangular wave           */
+#define SND_TRIANGLE    1      /* Triangular wave (1/2 rect.)*/
+#define SND_NOISE       2      /* White noise                */
+#define SND_PERIODIC    3      /* Periodic noise (not im-ed) */
+#define SND_WAVE        4      /* Wave sound set by SetWave()*/
+#define SND_MIDI        0x100  /* MIDI instrument (ORable)   */
+
+                               /* Drum() arguments:          */
+#define DRM_CLICK       0      /* Click (default)            */
+#define DRM_MIDI        0x100  /* MIDI drum (ORable)         */
+
+                               /* MIDI characteristics:      */
+#define MIDI_CHANNELS   16     /* Number of MIDI channels    */
+#define MIDI_MINFREQ    9      /* Min MIDI frequency (Hz)    */
+#define MIDI_MAXFREQ    12285  /* Max MIDI frequency (Hz)    */
+#define MIDI_DIVISIONS  1000   /* Number of ticks per second */
+
+                               /* MIDILogging() arguments:   */
+#define MIDI_OFF        0      /* Turn MIDI logging off      */
+#define MIDI_ON         1      /* Turn MIDI logging on       */
+#define MIDI_TOGGLE     2      /* Toggle MIDI logging        */
+#define MIDI_QUERY      3      /* Query MIDI logging status  */
+
+/** TrashSound() *********************************************/
+/** Shut down sound driver. Each driver implements its own  **/
+/** TrashSound() function.                                  **/
+/*************************************************************/
+void TrashSound(void);
+
+/** Sound() **************************************************/
+/** Generate sound of given frequency (Hz) and volume       **/
+/** (0..255) via given channel. Setting Freq=0 or Volume=0  **/
+/** turns sound off.                                        **/
+/*************************************************************/
+void Sound(int Channel,int Freq,int Volume);
+
+/** Drum() ***************************************************/
+/** Hit a drum of given type with given force (0..255).     **/
+/** MIDI drums can be used by ORing their numbers with      **/
+/** SND_MIDI.                                               **/
+/*************************************************************/
+void Drum(int Type,int Force);
+
+/** SetSound() ***********************************************/
+/** Set sound type at a given channel. MIDI instruments can **/
+/** be set directly by ORing their numbers with SND_MIDI.   **/
+/*************************************************************/
+void SetSound(int Channel,int NewType);
+
+/** SetChannels() ********************************************/
+/** Set master volume (0..255) and switch channels on/off.  **/
+/** Each channel N has corresponding bit 2^N in Switch. Set **/
+/** or reset this bit to turn the channel on or off.        **/ 
+/*************************************************************/
+void SetChannels(int Volume,int Switch);
+
+/** SetWave() ************************************************/
+/** Set waveform for a given channel. The channel will be   **/
+/** marked with sound type SND_WAVE. Set Rate=0 if you want **/
+/** waveform to be an instrument or set it to the waveform  **/
+/** own playback rate.                                      **/
+/*************************************************************/
+void SetWave(int Channel,const signed char *Data,int Length,int Rate);
+
+/** InitMIDI() ***********************************************/
+/** Initialize soundtrack logging into MIDI file FileName.  **/
+/** Repeated calls to InitMIDI() will close current MIDI    **/
+/** file and continue logging into a new one.               **/ 
+/*************************************************************/
+void InitMIDI(const char *FileName);
+
+/** TrashMIDI() **********************************************/
+/** Finish logging soundtrack and close the MIDI file.      **/
+/*************************************************************/
+void TrashMIDI(void);
+
+/** MIDILogging() ********************************************/
+/** Turn soundtrack logging on/off and return its current   **/
+/** status. Possible values of Switch are MIDI_OFF (turn    **/
+/** logging off), MIDI_ON (turn logging on), MIDI_TOGGLE    **/
+/** (toggle logging), and MIDI_QUERY (just return current   **/
+/** state of logging).                                      **/
+/*************************************************************/
+int MIDILogging(int Switch);
+
+/** MIDITicks() **********************************************/
+/** Log N 1ms MIDI ticks.                                   **/
+/*************************************************************/
+void MIDITicks(int N);
+
+#define SND_CHANNELS    16   /* Number of channels           */
+#define SND_SAMPLESIZE  128 //256  /* Max. SetWave() sample size   */
+#define SND_BUFSIZE     128 //256  /* Buffer size, <= 2^SND_BITS   */
+#define SND_BITS        8    /* Number of bits in a fragment */
+#define SND_BUFFERS     8    /* Number of fragments, >= 2    */
+    /* Bigger value results in better behaviour on loaded    */
+    /* but output gets more delayed.                         */
+
+/** InitSound() **********************************************/
+/** Initialize Unix sound driver with given synthesis rate. **/
+/** Returns Rate on success, 0 otherwise. Pass Rate=0 to    **/
+/** skip initialization and be silent. Pass Verbose!=0 to   **/
+/** see initialization messages.                            **/
+/*************************************************************/
+int InitSound(int Rate,int Verbose);
+
+/** StopSound() **********************************************/
+/** Temporarily suspend sound.                              **/
+/*************************************************************/
+void StopSound(void);
+
+/** ResumeSound() ********************************************/
+/** Resume sound after StopSound().                         **/
+/*************************************************************/
+void ResumeSound(void);
+
+
+/** SndDriver ************************************************/
+/** Each sound driver should fill this structure with       **/
+/** pointers to hardware-dependent handlers. This has to be **/
+/** done inside the InitSound() function.                   **/
+/*************************************************************/
+struct SndDriverStruct
+{
+  void (*SetSound)(int Channel,int NewType);
+  void (*Drum)(int Type,int Force);
+  void (*SetChannels)(int Volume,int Switch);
+  void (*Sound)(int Channel,int NewFreq,int NewVolume);
+  void (*SetWave)(int Channel,const signed char *Data,int Length,int Freq);
+};
+extern struct SndDriverStruct SndDriver;
+
+#endif /* SOUND_H */
+
diff --git a/MCUME_pico2/picomsx/Tables.h b/MCUME_pico2/picomsx/Tables.h
new file mode 100644
index 0000000..c08e9a0
--- /dev/null
+++ b/MCUME_pico2/picomsx/Tables.h
@@ -0,0 +1,447 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Tables.h                       **/
+/**                                                         **/
+/** This file contains tables of used by Z80 emulation to   **/
+/** compute SIGN,ZERO, PARITY flags, and decimal correction **/
+/** There are also timing tables for Z80 opcodes. This file **/
+/** is included from Z80.c.                                 **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+static const byte Cycles[256] =
+{
+   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+   8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+   7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+   7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+   5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+   5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+   5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 
+};
+
+static const byte CyclesCB[256] =
+{
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 
+};
+
+static const byte CyclesED[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
+  12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
+  12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
+  12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXX[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
+   0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+  19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXXCB[256] =
+{
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
+};
+
+static const byte ZSTable[256] =
+{
+  Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
+};
+
+static const byte PZSTable[256] =
+{
+  Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
+};
+
+static const word DAATable[2048] =
+{
+  0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,
+  0x0808,0x090C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,
+  0x180C,0x1908,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,
+  0x282C,0x2928,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,
+  0x3828,0x392C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,
+  0x480C,0x4908,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,
+  0x5808,0x590C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,
+  0x6828,0x692C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,
+  0x782C,0x7928,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,
+  0x888C,0x8988,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,
+  0x9888,0x998C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6025,0x6121,0x6221,0x6325,0x6421,0x6525,0x6625,0x6721,
+  0x6829,0x692D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7021,0x7125,0x7225,0x7321,0x7425,0x7521,0x7621,0x7725,
+  0x782D,0x7929,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8081,0x8185,0x8285,0x8381,0x8485,0x8581,0x8681,0x8785,
+  0x888D,0x8989,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9085,0x9181,0x9281,0x9385,0x9481,0x9585,0x9685,0x9781,
+  0x9889,0x998D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA0A5,0xA1A1,0xA2A1,0xA3A5,0xA4A1,0xA5A5,0xA6A5,0xA7A1,
+  0xA8A9,0xA9AD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB0A1,0xB1A5,0xB2A5,0xB3A1,0xB4A5,0xB5A1,0xB6A1,0xB7A5,
+  0xB8AD,0xB9A9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC085,0xC181,0xC281,0xC385,0xC481,0xC585,0xC685,0xC781,
+  0xC889,0xC98D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD081,0xD185,0xD285,0xD381,0xD485,0xD581,0xD681,0xD785,
+  0xD88D,0xD989,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE0A1,0xE1A5,0xE2A5,0xE3A1,0xE4A5,0xE5A1,0xE6A1,0xE7A5,
+  0xE8AD,0xE9A9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF0A5,0xF1A1,0xF2A1,0xF3A5,0xF4A1,0xF5A5,0xF6A5,0xF7A1,
+  0xF8A9,0xF9AD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0604,0x0700,0x0808,0x090C,0x0A0C,0x0B08,0x0C0C,0x0D08,
+  0x0E08,0x0F0C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1600,0x1704,0x180C,0x1908,0x1A08,0x1B0C,0x1C08,0x1D0C,
+  0x1E0C,0x1F08,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2620,0x2724,0x282C,0x2928,0x2A28,0x2B2C,0x2C28,0x2D2C,
+  0x2E2C,0x2F28,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3624,0x3720,0x3828,0x392C,0x3A2C,0x3B28,0x3C2C,0x3D28,
+  0x3E28,0x3F2C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4600,0x4704,0x480C,0x4908,0x4A08,0x4B0C,0x4C08,0x4D0C,
+  0x4E0C,0x4F08,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5604,0x5700,0x5808,0x590C,0x5A0C,0x5B08,0x5C0C,0x5D08,
+  0x5E08,0x5F0C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6624,0x6720,0x6828,0x692C,0x6A2C,0x6B28,0x6C2C,0x6D28,
+  0x6E28,0x6F2C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7620,0x7724,0x782C,0x7928,0x7A28,0x7B2C,0x7C28,0x7D2C,
+  0x7E2C,0x7F28,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8680,0x8784,0x888C,0x8988,0x8A88,0x8B8C,0x8C88,0x8D8C,
+  0x8E8C,0x8F88,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9684,0x9780,0x9888,0x998C,0x9A8C,0x9B88,0x9C8C,0x9D88,
+  0x9E88,0x9F8C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6625,0x6721,0x6829,0x692D,0x6A2D,0x6B29,0x6C2D,0x6D29,
+  0x6E29,0x6F2D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7621,0x7725,0x782D,0x7929,0x7A29,0x7B2D,0x7C29,0x7D2D,
+  0x7E2D,0x7F29,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8681,0x8785,0x888D,0x8989,0x8A89,0x8B8D,0x8C89,0x8D8D,
+  0x8E8D,0x8F89,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9685,0x9781,0x9889,0x998D,0x9A8D,0x9B89,0x9C8D,0x9D89,
+  0x9E89,0x9F8D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA6A5,0xA7A1,0xA8A9,0xA9AD,0xAAAD,0xABA9,0xACAD,0xADA9,
+  0xAEA9,0xAFAD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB6A1,0xB7A5,0xB8AD,0xB9A9,0xBAA9,0xBBAD,0xBCA9,0xBDAD,
+  0xBEAD,0xBFA9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC685,0xC781,0xC889,0xC98D,0xCA8D,0xCB89,0xCC8D,0xCD89,
+  0xCE89,0xCF8D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD681,0xD785,0xD88D,0xD989,0xDA89,0xDB8D,0xDC89,0xDD8D,
+  0xDE8D,0xDF89,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE6A1,0xE7A5,0xE8AD,0xE9A9,0xEAA9,0xEBAD,0xECA9,0xEDAD,
+  0xEEAD,0xEFA9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF6A5,0xF7A1,0xF8A9,0xF9AD,0xFAAD,0xFBA9,0xFCAD,0xFDA9,
+  0xFEA9,0xFFAD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0046,0x0102,0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,
+  0x080A,0x090E,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x1002,0x1106,0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,
+  0x180E,0x190A,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x2022,0x2126,0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,
+  0x282E,0x292A,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x3026,0x3122,0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,
+  0x382A,0x392E,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x4002,0x4106,0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,
+  0x480E,0x490A,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x5006,0x5102,0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,
+  0x580A,0x590E,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x6026,0x6122,0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,
+  0x682A,0x692E,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x7022,0x7126,0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,
+  0x782E,0x792A,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x8082,0x8186,0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,
+  0x888E,0x898A,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x9086,0x9182,0x9282,0x9386,0x9482,0x9586,0x9686,0x9782,
+  0x988A,0x998E,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xA0A7,0xA1A3,0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,
+  0xA8AB,0xA9AF,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xB0A3,0xB1A7,0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,
+  0xB8AF,0xB9AB,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xC087,0xC183,0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,
+  0xC88B,0xC98F,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xD083,0xD187,0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,
+  0xD88F,0xD98B,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xE0A3,0xE1A7,0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,
+  0xE8AF,0xE9AB,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xF0A7,0xF1A3,0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,
+  0xF8AB,0xF9AF,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0x0047,0x0103,0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,
+  0x080B,0x090F,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x1003,0x1107,0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,
+  0x180F,0x190B,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x2023,0x2127,0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,
+  0x282F,0x292B,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x3027,0x3123,0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,
+  0x382B,0x392F,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xFABE,0xFBBA,0xFCBE,0xFDBA,0xFEBA,0xFFBE,0x0046,0x0102,
+  0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x0A1E,0x0B1A,0x0C1E,0x0D1A,0x0E1A,0x0F1E,0x1002,0x1106,
+  0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x1A1A,0x1B1E,0x1C1A,0x1D1E,0x1E1E,0x1F1A,0x2022,0x2126,
+  0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x2A3A,0x2B3E,0x2C3A,0x2D3E,0x2E3E,0x2F3A,0x3026,0x3122,
+  0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x3A3E,0x3B3A,0x3C3E,0x3D3A,0x3E3A,0x3F3E,0x4002,0x4106,
+  0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x4A1A,0x4B1E,0x4C1A,0x4D1E,0x4E1E,0x4F1A,0x5006,0x5102,
+  0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x5A1E,0x5B1A,0x5C1E,0x5D1A,0x5E1A,0x5F1E,0x6026,0x6122,
+  0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x6A3E,0x6B3A,0x6C3E,0x6D3A,0x6E3A,0x6F3E,0x7022,0x7126,
+  0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x7A3A,0x7B3E,0x7C3A,0x7D3E,0x7E3E,0x7F3A,0x8082,0x8186,
+  0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x8A9A,0x8B9E,0x8C9A,0x8D9E,0x8E9E,0x8F9A,0x9086,0x9182,
+  0x9282,0x9386,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0x9A9F,0x9B9B,0x9C9F,0x9D9B,0x9E9B,0x9F9F,0xA0A7,0xA1A3,
+  0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xAABF,0xABBB,0xACBF,0xADBB,0xAEBB,0xAFBF,0xB0A3,0xB1A7,
+  0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xBABB,0xBBBF,0xBCBB,0xBDBF,0xBEBF,0xBFBB,0xC087,0xC183,
+  0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xCA9F,0xCB9B,0xCC9F,0xCD9B,0xCE9B,0xCF9F,0xD083,0xD187,
+  0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xDA9B,0xDB9F,0xDC9B,0xDD9F,0xDE9F,0xDF9B,0xE0A3,0xE1A7,
+  0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xEABB,0xEBBF,0xECBB,0xEDBF,0xEEBF,0xEFBB,0xF0A7,0xF1A3,
+  0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0xFABF,0xFBBB,0xFCBF,0xFDBB,0xFEBB,0xFFBF,0x0047,0x0103,
+  0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x0A1F,0x0B1B,0x0C1F,0x0D1B,0x0E1B,0x0F1F,0x1003,0x1107,
+  0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x1A1B,0x1B1F,0x1C1B,0x1D1F,0x1E1F,0x1F1B,0x2023,0x2127,
+  0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x2A3B,0x2B3F,0x2C3B,0x2D3F,0x2E3F,0x2F3B,0x3027,0x3123,
+  0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F
+};
diff --git a/MCUME_pico2/picomsx/V9938.c b/MCUME_pico2/picomsx/V9938.c
new file mode 100644
index 0000000..8c516b4
--- /dev/null
+++ b/MCUME_pico2/picomsx/V9938.c
@@ -0,0 +1,1058 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                         V9938.c                         **/
+/**                                                         **/
+/** This file contains implementation for the V9938 special **/
+/** graphical operations.                                   **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/**                                                         **/
+/** Completely rewritten by Alex Wulms:                     **/
+/**  - VDP Command execution 'in parallel' with CPU         **/
+/**  - Corrected behaviour of VDP commands                  **/
+/**  - Made it easier to implement correct S7/8 mapping     **/
+/**    by concentrating VRAM access in one single place     **/
+/**  - Made use of the 'in parallel' VDP command exec       **/
+/**    and correct timing. You must call the function       **/
+/**    LoopVDP() from LoopZ80 in MSX.c. You must call it    **/
+/**    exactly 256 times per screen refresh.                **/
+/** Started on       : 11-11-1999                           **/
+/** Beta release 1 on:  9-12-1999                           **/
+/** Beta release 2 on: 20-01-2000                           **/
+/**  - Corrected behaviour of VRM <-> Z80 transfer          **/
+/**  - Improved performance of the code                     **/
+/** Public release 1.0: 20-04-2000                          **/
+/*************************************************************/
+#include "V9938.h"
+#include <string.h>
+
+#include "shared.h"
+
+
+/** INLINE ***************************************************/
+/** Different compilers inline C functions differently.     **/
+/*************************************************************/
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE static
+#endif
+ 
+/*************************************************************/
+/** Other usefull defines                                   **/
+/*************************************************************/
+#define VDP_VRMP5(X, Y) (VRAM + ((Y&1023)<<7) + ((X&255)>>1))
+#define VDP_VRMP6(X, Y) (VRAM + ((Y&1023)<<7) + ((X&511)>>2))
+#define VDP_VRMP7(X, Y) (VRAM + ((Y&511)<<8) + ((X&511)>>1))
+#define VDP_VRMP8(X, Y) (VRAM + ((Y&511)<<8) + (X&255))
+
+#define VDP_VRMP(M, X, Y) VDPVRMP(M, X, Y)
+#define VDP_POINT(M, X, Y) VDPpoint(M, X, Y)
+#define VDP_PSET(M, X, Y, C, O) VDPpset(M, X, Y, C, O)
+
+#define CM_ABRT  0x0
+#define CM_POINT 0x4
+#define CM_PSET  0x5
+#define CM_SRCH  0x6
+#define CM_LINE  0x7
+#define CM_LMMV  0x8
+#define CM_LMMM  0x9
+#define CM_LMCM  0xA
+#define CM_LMMC  0xB
+#define CM_HMMV  0xC
+#define CM_HMMM  0xD
+#define CM_YMMM  0xE
+#define CM_HMMC  0xF
+
+/*************************************************************/
+/* Many VDP commands are executed in some kind of loop but   */
+/* essentially, there are only a few basic loop structures   */
+/* that are re-used. We define the loop structures that are  */
+/* re-used here so that they have to be entered only once    */
+/*************************************************************/
+#define pre_loop \
+    while ((cnt-=delta) > 0) {
+
+/* Loop over DX, DY */
+#define post__x_y(MX) \
+    if (!--ANX || ((ADX+=TX)&MX)) { \
+      if (!(--NY&1023) || (DY+=TY)==-1) \
+        break; \
+      else { \
+        ADX=DX; \
+        ANX=NX; \
+      } \
+    } \
+  }
+
+/* Loop over DX, SY, DY */
+#define post__xyy(MX) \
+    if ((ADX+=TX)&MX) { \
+      if (!(--NY&1023) || (SY+=TY)==-1 || (DY+=TY)==-1) \
+        break; \
+      else \
+        ADX=DX; \
+    } \
+  }
+
+/* Loop over SX, DX, SY, DY */
+#define post_xxyy(MX) \
+    if (!--ANX || ((ASX+=TX)&MX) || ((ADX+=TX)&MX)) { \
+      if (!(--NY&1023) || (SY+=TY)==-1 || (DY+=TY)==-1) \
+        break; \
+      else { \
+        ASX=SX; \
+        ADX=DX; \
+        ANX=NX; \
+      } \
+    } \
+  }
+
+/*************************************************************/
+/** Structures and stuff                                    **/
+/*************************************************************/
+static struct {
+  int SX,SY;
+  int DX,DY;
+  int TX,TY;
+  int NX,NY;
+  int MX;
+  int ASX,ADX,ANX;
+  byte CL;
+  byte LO;
+  byte CM;
+} MMC;
+
+/*************************************************************/
+/** Function prototypes                                     **/
+/*************************************************************/
+static byte *VDPVRMP(register byte M, register int X, register int Y);
+
+static byte VDPpoint5(register int SX, register int SY);
+static byte VDPpoint6(register int SX, register int SY);
+static byte VDPpoint7(register int SX, register int SY);
+static byte VDPpoint8(register int SX, register int SY);
+
+static byte VDPpoint(register byte SM, 
+                     register int SX, register int SY);
+
+static void VDPpsetlowlevel(register byte *P, register byte CL,
+                            register byte M, register byte OP);
+
+static void VDPpset5(register int DX, register int DY,
+                     register byte CL, register byte OP);
+static void VDPpset6(register int DX, register int DY,
+                     register byte CL, register byte OP);
+static void VDPpset7(register int DX, register int DY,
+                     register byte CL, register byte OP);
+static void VDPpset8(register int DX, register int DY,
+                     register byte CL, register byte OP);
+
+static void VDPpset(register byte SM,
+                    register int DX, register int DY,
+                    register byte CL, register byte OP);
+
+static int GetVdpTimingValue(register int *);
+
+static void SrchEngine(void);
+static void LineEngine(void);
+static void LmmvEngine(void);
+static void LmmmEngine(void);
+static void LmcmEngine(void);
+static void LmmcEngine(void);
+static void HmmvEngine(void);
+static void HmmmEngine(void);
+static void YmmmEngine(void);
+static void HmmcEngine(void);
+
+void ReportVdpCommand(register byte Op);
+
+/*************************************************************/
+/** Variables visible only in this module                   **/
+/*************************************************************/
+static byte Mask[4] = { 0x0F,0x03,0x0F,0xFF };
+static int  PPB[4]  = { 2,4,2,1 };
+static int  PPL[4]  = { 256,512,512,256 };
+static int  VdpOpsCnt=1;
+static void (*VdpEngine)(void)=0;
+
+                      /*  SprOn SprOn SprOf SprOf */
+                      /*  ScrOf ScrOn ScrOf ScrOn */
+static int srch_timing[8]={ 818, 1025,  818,  830,   /* ntsc */
+                            696,  854,  696,  684 }; /* pal  */
+static int line_timing[8]={ 1063, 1259, 1063, 1161,
+                            904,  1026, 904,  953 };
+static int hmmv_timing[8]={ 439,  549,  439,  531,
+                            366,  439,  366,  427 };
+static int lmmv_timing[8]={ 873,  1135, 873, 1056,
+                            732,  909,  732,  854 };
+static int ymmm_timing[8]={ 586,  952,  586,  610,
+                            488,  720,  488,  500 };
+static int hmmm_timing[8]={ 818,  1111, 818,  854,
+                            684,  879,  684,  708 };
+static int lmmm_timing[8]={ 1160, 1599, 1160, 1172, 
+                            964,  1257, 964,  977 };
+
+
+/** VDPVRMP() **********************************************/
+/** Calculate addr of a pixel in vram                       **/
+/*************************************************************/
+INLINE byte *VDPVRMP(byte M,int X,int Y)
+{
+  switch(M)
+  {
+    case 0: return VDP_VRMP5(X,Y);
+    case 1: return VDP_VRMP6(X,Y);
+    case 2: return VDP_VRMP7(X,Y);
+    case 3: return VDP_VRMP8(X,Y);
+  }
+
+  return(VRAM);
+}
+
+/** VDPpoint5() ***********************************************/
+/** Get a pixel on screen 5                                 **/
+/*************************************************************/
+INLINE byte VDPpoint5(int SX, int SY)
+{
+  return (*VDP_VRMP5(SX, SY) >>
+          (((~SX)&1)<<2)
+         )&15;
+}
+
+/** VDPpoint6() ***********************************************/
+/** Get a pixel on screen 6                                 **/
+/*************************************************************/
+INLINE byte VDPpoint6(int SX, int SY)
+{
+  return (*VDP_VRMP6(SX, SY) >>
+          (((~SX)&3)<<1)
+         )&3;
+}
+
+/** VDPpoint7() ***********************************************/
+/** Get a pixel on screen 7                                 **/
+/*************************************************************/
+INLINE byte VDPpoint7(int SX, int SY)
+{
+  return (*VDP_VRMP7(SX, SY) >>
+          (((~SX)&1)<<2)
+         )&15;
+}
+
+/** VDPpoint8() ***********************************************/
+/** Get a pixel on screen 8                                 **/
+/*************************************************************/
+INLINE byte VDPpoint8(int SX, int SY)
+{
+  return *VDP_VRMP8(SX, SY);
+}
+
+/** VDPpoint() ************************************************/
+/** Get a pixel on a screen                                 **/
+/*************************************************************/
+INLINE byte VDPpoint(byte SM, int SX, int SY)
+{
+  switch(SM)
+  {
+    case 0: return VDPpoint5(SX,SY);
+    case 1: return VDPpoint6(SX,SY);
+    case 2: return VDPpoint7(SX,SY);
+    case 3: return VDPpoint8(SX,SY);
+  }
+
+  return(0);
+}
+
+/** VDPpsetlowlevel() ****************************************/
+/** Low level function to set a pixel on a screen           **/
+/** Make it inline to make it fast                          **/
+/*************************************************************/
+INLINE void VDPpsetlowlevel(byte *P, byte CL, byte M, byte OP)
+{
+  switch (OP)
+  {
+    case 0: *P = (*P & M) | CL; break;
+    case 1: *P = *P & (CL | M); break;
+    case 2: *P |= CL; break;
+    case 3: *P ^= CL; break;
+    case 4: *P = (*P & M) | ~(CL | M); break;
+    case 8: if (CL) *P = (*P & M) | CL; break;
+    case 9: if (CL) *P = *P & (CL | M); break;
+    case 10: if (CL) *P |= CL; break;
+    case 11:  if (CL) *P ^= CL; break;
+    case 12:  if (CL) *P = (*P & M) | ~(CL|M); break;
+  }
+}
+
+/** VDPpset5() ***********************************************/
+/** Set a pixel on screen 5                                 **/
+/*************************************************************/
+INLINE void VDPpset5(int DX, int DY, byte CL, byte OP)
+{
+  register byte SH = ((~DX)&1)<<2;
+
+  VDPpsetlowlevel(VDP_VRMP5(DX, DY),
+                  CL << SH, ~(15<<SH), OP);
+}
+
+/** VDPpset6() ***********************************************/
+/** Set a pixel on screen 6                                 **/
+/*************************************************************/
+INLINE void VDPpset6(int DX, int DY, byte CL, byte OP)
+{
+  register byte SH = ((~DX)&3)<<1;
+
+  VDPpsetlowlevel(VDP_VRMP6(DX, DY),
+                  CL << SH, ~(3<<SH), OP);
+}
+
+/** VDPpset7() ***********************************************/
+/** Set a pixel on screen 7                                 **/
+/*************************************************************/
+INLINE void VDPpset7(int DX, int DY, byte CL, byte OP)
+{
+  register byte SH = ((~DX)&1)<<2;
+
+  VDPpsetlowlevel(VDP_VRMP7(DX, DY),
+                  CL << SH, ~(15<<SH), OP);
+}
+
+/** VDPpset8() ***********************************************/
+/** Set a pixel on screen 8                                 **/
+/*************************************************************/
+INLINE void VDPpset8(int DX, int DY, byte CL, byte OP)
+{
+  VDPpsetlowlevel(VDP_VRMP8(DX, DY),
+                  CL, 0, OP);
+}
+
+/** VDPpset() ************************************************/
+/** Set a pixel on a screen                                 **/
+/*************************************************************/
+INLINE void VDPpset(byte SM, int DX, int DY, byte CL, byte OP)
+{
+  switch (SM) {
+    case 0: VDPpset5(DX, DY, CL, OP); break;
+    case 1: VDPpset6(DX, DY, CL, OP); break;
+    case 2: VDPpset7(DX, DY, CL, OP); break;
+    case 3: VDPpset8(DX, DY, CL, OP); break;
+  }
+}
+
+/** GetVdpTimingValue() **************************************/
+/** Get timing value for a certain VDP command              **/
+/*************************************************************/
+static int GetVdpTimingValue(register int *timing_values)
+{
+  return(timing_values[((VDP[1]>>6)&1)|(VDP[8]&2)|((VDP[9]<<1)&4)]);
+}
+
+/** SrchEgine()** ********************************************/
+/** Search a dot                                            **/
+/*************************************************************/
+void SrchEngine(void)
+{
+  register int SX=MMC.SX;
+  register int SY=MMC.SY;
+  register int TX=MMC.TX;
+  register int ANX=MMC.ANX;
+  register byte CL=MMC.CL;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(srch_timing);
+  cnt = VdpOpsCnt;
+
+#define pre_srch \
+    pre_loop \
+      if ((
+#define post_srch(MX) \
+           ==CL) ^ANX) { \
+      VDPStatus[2]|=0x10; /* Border detected */ \
+      break; \
+    } \
+    if ((SX+=TX) & MX) { \
+      VDPStatus[2]&=0xEF; /* Border not detected */ \
+      break; \
+    } \
+  } 
+
+  switch (ScrMode) {
+    case 5: pre_srch VDPpoint5(SX, SY) post_srch(256)
+            break;
+    case 6: pre_srch VDPpoint6(SX, SY) post_srch(512)
+            break;
+    case 7: pre_srch VDPpoint7(SX, SY) post_srch(512)
+            break;
+    case 8: pre_srch VDPpoint8(SX, SY) post_srch(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    /* Update SX in VDP registers */
+    VDPStatus[8]=SX&0xFF;
+    VDPStatus[9]=(SX>>8)|0xFE;
+  }
+  else {
+    MMC.SX=SX;
+  }
+}
+
+/** LineEgine()** ********************************************/
+/** Draw a line                                             **/
+/*************************************************************/
+void LineEngine(void)
+{
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NX=MMC.NX;
+  register int NY=MMC.NY;
+  register int ASX=MMC.ASX;
+  register int ADX=MMC.ADX;
+  register byte CL=MMC.CL;
+  register byte LO=MMC.LO;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(line_timing);
+  cnt = VdpOpsCnt;
+
+#define post_linexmaj(MX) \
+      DX+=TX; \
+      if ((ASX-=NY)<0) { \
+        ASX+=NX; \
+        DY+=TY; \
+      } \
+      ASX&=1023; /* Mask to 10 bits range */ \
+      if (ADX++==NX || (DX&MX)) \
+        break; \
+    }
+#define post_lineymaj(MX) \
+      DY+=TY; \
+      if ((ASX-=NY)<0) { \
+        ASX+=NX; \
+        DX+=TX; \
+      } \
+      ASX&=1023; /* Mask to 10 bits range */ \
+      if (ADX++==NX || (DX&MX)) \
+        break; \
+    }
+
+  if ((VDP[45]&0x01)==0)
+    /* X-Axis is major direction */
+    switch (ScrMode) {
+      case 5: pre_loop VDPpset5(DX, DY, CL, LO); post_linexmaj(256)
+              break;
+      case 6: pre_loop VDPpset6(DX, DY, CL, LO); post_linexmaj(512)
+              break;
+      case 7: pre_loop VDPpset7(DX, DY, CL, LO); post_linexmaj(512)
+              break;
+      case 8: pre_loop VDPpset8(DX, DY, CL, LO); post_linexmaj(256)
+              break;
+    }
+  else
+    /* Y-Axis is major direction */
+    switch (ScrMode) {
+      case 5: pre_loop VDPpset5(DX, DY, CL, LO); post_lineymaj(256)
+              break;
+      case 6: pre_loop VDPpset6(DX, DY, CL, LO); post_lineymaj(512)
+              break;
+      case 7: pre_loop VDPpset7(DX, DY, CL, LO); post_lineymaj(512)
+              break;
+      case 8: pre_loop VDPpset8(DX, DY, CL, LO); post_lineymaj(256)
+              break;
+    }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+  }
+  else {
+    MMC.DX=DX;
+    MMC.DY=DY;
+    MMC.ASX=ASX;
+    MMC.ADX=ADX;
+  }
+}
+
+/** LmmvEngine() *********************************************/
+/** VDP -> Vram                                             **/
+/*************************************************************/
+void LmmvEngine(void)
+{
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NX=MMC.NX;
+  register int NY=MMC.NY;
+  register int ADX=MMC.ADX;
+  register int ANX=MMC.ANX;
+  register byte CL=MMC.CL;
+  register byte LO=MMC.LO;
+  register int cnt;
+  register int delta;
+
+  delta = GetVdpTimingValue(lmmv_timing);
+  cnt = VdpOpsCnt;
+
+  switch (ScrMode) {
+    case 5: pre_loop VDPpset5(ADX, DY, CL, LO); post__x_y(256)
+            break;
+    case 6: pre_loop VDPpset6(ADX, DY, CL, LO); post__x_y(512)
+            break;
+    case 7: pre_loop VDPpset7(ADX, DY, CL, LO); post__x_y(512)
+            break;
+    case 8: pre_loop VDPpset8(ADX, DY, CL, LO); post__x_y(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    if (!NY)
+      DY+=TY;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+    VDP[42]=NY & 0xFF;
+    VDP[43]=(NY>>8) & 0x03;
+  }
+  else {
+    MMC.DY=DY;
+    MMC.NY=NY;
+    MMC.ANX=ANX;
+    MMC.ADX=ADX;
+  }
+}
+
+/** LmmmEngine() *********************************************/
+/** Vram -> Vram                                            **/
+/*************************************************************/
+void LmmmEngine(void)
+{
+  register int SX=MMC.SX;
+  register int SY=MMC.SY;
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NX=MMC.NX;
+  register int NY=MMC.NY;
+  register int ASX=MMC.ASX;
+  register int ADX=MMC.ADX;
+  register int ANX=MMC.ANX;
+  register byte LO=MMC.LO;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(lmmm_timing);
+  cnt = VdpOpsCnt;
+
+  switch (ScrMode) {
+    case 5: pre_loop VDPpset5(ADX, DY, VDPpoint5(ASX, SY), LO); post_xxyy(256)
+            break;
+    case 6: pre_loop VDPpset6(ADX, DY, VDPpoint6(ASX, SY), LO); post_xxyy(512)
+            break;
+    case 7: pre_loop VDPpset7(ADX, DY, VDPpoint7(ASX, SY), LO); post_xxyy(512)
+            break;
+    case 8: pre_loop VDPpset8(ADX, DY, VDPpoint8(ASX, SY), LO); post_xxyy(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    if (!NY) {
+      SY+=TY;
+      DY+=TY;
+    }
+    else
+      if (SY==-1)
+        DY+=TY;
+    VDP[42]=NY & 0xFF;
+    VDP[43]=(NY>>8) & 0x03;
+    VDP[34]=SY & 0xFF;
+    VDP[35]=(SY>>8) & 0x03;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+  }
+  else {
+    MMC.SY=SY;
+    MMC.DY=DY;
+    MMC.NY=NY;
+    MMC.ANX=ANX;
+    MMC.ASX=ASX;
+    MMC.ADX=ADX;
+  }
+}
+
+/** LmcmEngine() *********************************************/
+/** Vram -> CPU                                             **/
+/*************************************************************/
+void LmcmEngine()
+{
+  if ((VDPStatus[2]&0x80)!=0x80) {
+
+    VDPStatus[7]=VDP[44]=VDP_POINT(ScrMode-5, MMC.ASX, MMC.SY);
+    VdpOpsCnt-=GetVdpTimingValue(lmmv_timing);
+    VDPStatus[2]|=0x80;
+
+    if (!--MMC.ANX || ((MMC.ASX+=MMC.TX)&MMC.MX)) {
+      if (!(--MMC.NY & 1023) || (MMC.SY+=MMC.TY)==-1) {
+        VDPStatus[2]&=0xFE;
+        VdpEngine=0;
+        if (!MMC.NY)
+          MMC.DY+=MMC.TY;
+        VDP[42]=MMC.NY & 0xFF;
+        VDP[43]=(MMC.NY>>8) & 0x03;
+        VDP[34]=MMC.SY & 0xFF;
+        VDP[35]=(MMC.SY>>8) & 0x03;
+      }
+      else {
+        MMC.ASX=MMC.SX;
+        MMC.ANX=MMC.NX;
+      }
+    }
+  }
+}
+
+/** LmmcEngine() *********************************************/
+/** CPU -> Vram                                             **/
+/*************************************************************/
+void LmmcEngine(void)
+{
+  if ((VDPStatus[2]&0x80)!=0x80) {
+    register byte SM=ScrMode-5;
+
+    VDPStatus[7]=VDP[44]&=Mask[SM];
+    VDP_PSET(SM, MMC.ADX, MMC.DY, VDP[44], MMC.LO);
+    VdpOpsCnt-=GetVdpTimingValue(lmmv_timing);
+    VDPStatus[2]|=0x80;
+
+    if (!--MMC.ANX || ((MMC.ADX+=MMC.TX)&MMC.MX)) {
+      if (!(--MMC.NY&1023) || (MMC.DY+=MMC.TY)==-1) {
+        VDPStatus[2]&=0xFE;
+        VdpEngine=0;
+        if (!MMC.NY)
+          MMC.DY+=MMC.TY;
+        VDP[42]=MMC.NY & 0xFF;
+        VDP[43]=(MMC.NY>>8) & 0x03;
+        VDP[38]=MMC.DY & 0xFF;
+        VDP[39]=(MMC.DY>>8) & 0x03;
+      }
+      else {
+        MMC.ADX=MMC.DX;
+        MMC.ANX=MMC.NX;
+      }
+    }
+  }
+}
+
+/** HmmvEngine() *********************************************/
+/** VDP --> Vram                                            **/
+/*************************************************************/
+void HmmvEngine(void)
+{
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NX=MMC.NX;
+  register int NY=MMC.NY;
+  register int ADX=MMC.ADX;
+  register int ANX=MMC.ANX;
+  register byte CL=MMC.CL;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(hmmv_timing);
+  cnt = VdpOpsCnt;
+
+  switch (ScrMode) {
+    case 5: pre_loop *VDP_VRMP5(ADX, DY) = CL; post__x_y(256)
+            break;
+    case 6: pre_loop *VDP_VRMP6(ADX, DY) = CL; post__x_y(512)
+            break;
+    case 7: pre_loop *VDP_VRMP7(ADX, DY) = CL; post__x_y(512)
+            break;
+    case 8: pre_loop *VDP_VRMP8(ADX, DY) = CL; post__x_y(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    if (!NY)
+      DY+=TY;
+    VDP[42]=NY & 0xFF;
+    VDP[43]=(NY>>8) & 0x03;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+  }
+  else {
+    MMC.DY=DY;
+    MMC.NY=NY;
+    MMC.ANX=ANX;
+    MMC.ADX=ADX;
+  }
+}
+
+/** HmmmEngine() *********************************************/
+/** Vram -> Vram                                            **/
+/*************************************************************/
+void HmmmEngine(void)
+{
+  register int SX=MMC.SX;
+  register int SY=MMC.SY;
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NX=MMC.NX;
+  register int NY=MMC.NY;
+  register int ASX=MMC.ASX;
+  register int ADX=MMC.ADX;
+  register int ANX=MMC.ANX;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(hmmm_timing);
+  cnt = VdpOpsCnt;
+
+  switch (ScrMode) {
+    case 5: pre_loop *VDP_VRMP5(ADX, DY) = *VDP_VRMP5(ASX, SY); post_xxyy(256)
+            break;
+    case 6: pre_loop *VDP_VRMP6(ADX, DY) = *VDP_VRMP6(ASX, SY); post_xxyy(512)
+            break;
+    case 7: pre_loop *VDP_VRMP7(ADX, DY) = *VDP_VRMP7(ASX, SY); post_xxyy(512)
+            break;
+    case 8: pre_loop *VDP_VRMP8(ADX, DY) = *VDP_VRMP8(ASX, SY); post_xxyy(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    if (!NY) {
+      SY+=TY;
+      DY+=TY;
+    }
+    else
+      if (SY==-1)
+        DY+=TY;
+    VDP[42]=NY & 0xFF;
+    VDP[43]=(NY>>8) & 0x03;
+    VDP[34]=SY & 0xFF;
+    VDP[35]=(SY>>8) & 0x03;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+  }
+  else {
+    MMC.SY=SY;
+    MMC.DY=DY;
+    MMC.NY=NY;
+    MMC.ANX=ANX;
+    MMC.ASX=ASX;
+    MMC.ADX=ADX;
+  }
+}
+
+/** YmmmEngine() *********************************************/
+/** Vram -> Vram                                            **/
+/*************************************************************/
+void YmmmEngine(void)
+{
+  register int SY=MMC.SY;
+  register int DX=MMC.DX;
+  register int DY=MMC.DY;
+  register int TX=MMC.TX;
+  register int TY=MMC.TY;
+  register int NY=MMC.NY;
+  register int ADX=MMC.ADX;
+  register int cnt;
+  register int delta;
+ 
+  delta = GetVdpTimingValue(ymmm_timing);
+  cnt = VdpOpsCnt;
+
+  switch (ScrMode) {
+    case 5: pre_loop *VDP_VRMP5(ADX, DY) = *VDP_VRMP5(ADX, SY); post__xyy(256)
+            break;
+    case 6: pre_loop *VDP_VRMP6(ADX, DY) = *VDP_VRMP6(ADX, SY); post__xyy(512)
+            break;
+    case 7: pre_loop *VDP_VRMP7(ADX, DY) = *VDP_VRMP7(ADX, SY); post__xyy(512)
+            break;
+    case 8: pre_loop *VDP_VRMP8(ADX, DY) = *VDP_VRMP8(ADX, SY); post__xyy(256)
+            break;
+  }
+
+  if ((VdpOpsCnt=cnt)>0) {
+    /* Command execution done */
+    VDPStatus[2]&=0xFE;
+    VdpEngine=0;
+    if (!NY) {
+      SY+=TY;
+      DY+=TY;
+    }
+    else
+      if (SY==-1)
+        DY+=TY;
+    VDP[42]=NY & 0xFF;
+    VDP[43]=(NY>>8) & 0x03;
+    VDP[34]=SY & 0xFF;
+    VDP[35]=(SY>>8) & 0x03;
+    VDP[38]=DY & 0xFF;
+    VDP[39]=(DY>>8) & 0x03;
+  }
+  else {
+    MMC.SY=SY;
+    MMC.DY=DY;
+    MMC.NY=NY;
+    MMC.ADX=ADX;
+  }
+}
+
+/** HmmcEngine() *********************************************/
+/** CPU -> Vram                                             **/
+/*************************************************************/
+void HmmcEngine(void)
+{
+  if ((VDPStatus[2]&0x80)!=0x80) {
+
+    *VDP_VRMP(ScrMode-5, MMC.ADX, MMC.DY)=VDP[44];
+    VdpOpsCnt-=GetVdpTimingValue(hmmv_timing);
+    VDPStatus[2]|=0x80;
+
+    if (!--MMC.ANX || ((MMC.ADX+=MMC.TX)&MMC.MX)) {
+      if (!(--MMC.NY&1023) || (MMC.DY+=MMC.TY)==-1) {
+        VDPStatus[2]&=0xFE;
+        VdpEngine=0;
+        if (!MMC.NY)
+          MMC.DY+=MMC.TY;
+        VDP[42]=MMC.NY & 0xFF;
+        VDP[43]=(MMC.NY>>8) & 0x03;
+        VDP[38]=MMC.DY & 0xFF;
+        VDP[39]=(MMC.DY>>8) & 0x03;
+      }
+      else {
+        MMC.ADX=MMC.DX;
+        MMC.ANX=MMC.NX;
+      }
+    }
+  }
+}
+
+/** VDPWrite() ***********************************************/
+/** Use this function to transfer pixel(s) from CPU to VDP. **/
+/*************************************************************/
+void VDPWrite(byte V)
+{
+  VDPStatus[2]&=0x7F;
+  VDPStatus[7]=VDP[44]=V;
+  if(VdpEngine&&(VdpOpsCnt>0)) VdpEngine();
+}
+
+/** VDPRead() ************************************************/
+/** Use this function to transfer pixel(s) from VDP to CPU. **/
+/*************************************************************/
+byte VDPRead(void)
+{
+  VDPStatus[2]&=0x7F;
+  if(VdpEngine&&(VdpOpsCnt>0)) VdpEngine();
+  return(VDP[44]);
+}
+
+/** ReportVdpCommand() ***************************************/
+/** Report VDP Command to be executed                       **/
+/*************************************************************/
+void ReportVdpCommand(register byte Op)
+{
+  static char *Ops[16] =
+  {
+    "SET ","AND ","OR  ","XOR ","NOT ","NOP ","NOP ","NOP ",
+    "TSET","TAND","TOR ","TXOR","TNOT","NOP ","NOP ","NOP "
+  };
+  static char *Commands[16] =
+  {
+    " ABRT"," ????"," ????"," ????","POINT"," PSET"," SRCH"," LINE",
+    " LMMV"," LMMM"," LMCM"," LMMC"," HMMV"," HMMM"," YMMM"," HMMC"
+  };
+  register byte CL, CM, LO;
+  register int SX,SY, DX,DY, NX,NY;
+
+  /* Fetch arguments */
+  CL = VDP[44];
+  SX = (VDP[32]+((int)VDP[33]<<8)) & 511;
+  SY = (VDP[34]+((int)VDP[35]<<8)) & 1023;
+  DX = (VDP[36]+((int)VDP[37]<<8)) & 511;
+  DY = (VDP[38]+((int)VDP[39]<<8)) & 1023;
+  NX = (VDP[40]+((int)VDP[41]<<8)) & 1023;
+  NY = (VDP[42]+((int)VDP[43]<<8)) & 1023;
+  CM = Op>>4;
+  LO = Op&0x0F;
+
+  printf("V9938: Opcode %02Xh %s-%s (%d,%d)->(%d,%d),%d [%d,%d]%s\n",
+         Op, Commands[CM], Ops[LO],
+         SX,SY, DX,DY, CL, VDP[45]&0x04? -NX:NX,
+         VDP[45]&0x08? -NY:NY,
+         VDP[45]&0x70? " on ExtVRAM":""
+        );
+}
+
+/** VDPDraw() ************************************************/
+/** Perform a given V9938 operation Op.                     **/
+/*************************************************************/
+byte VDPDraw(byte Op)
+{
+  register int SM;
+
+  /* V9938 ops only work in SCREENs 5-8 */
+  if (ScrMode<5)
+    return(0);
+
+  SM = ScrMode-5;         /* Screen mode index 0..3  */
+
+  MMC.CM = Op>>4;
+  if ((MMC.CM & 0x0C) != 0x0C && MMC.CM != 0)
+    /* Dot operation: use only relevant bits of color */
+    VDPStatus[7]=(VDP[44]&=Mask[SM]);
+
+  if(Verbose&0x02)
+    ReportVdpCommand(Op);
+
+  switch(Op>>4) {
+    case CM_ABRT:
+      VDPStatus[2]&=0xFE;
+      VdpEngine=0;  
+      return 1;
+    case CM_POINT:
+      VDPStatus[2]&=0xFE;
+      VdpEngine=0;  
+      VDPStatus[7]=VDP[44]=
+                   VDP_POINT(SM, VDP[32]+((int)VDP[33]<<8),
+                                 VDP[34]+((int)VDP[35]<<8));
+      return 1;
+    case CM_PSET:
+      VDPStatus[2]&=0xFE;
+      VdpEngine=0;  
+      VDP_PSET(SM, 
+               VDP[36]+((int)VDP[37]<<8),
+               VDP[38]+((int)VDP[39]<<8),
+               VDP[44],
+               Op&0x0F);
+      return 1;
+    case CM_SRCH:
+      VdpEngine=SrchEngine;
+      break;
+    case CM_LINE:
+      VdpEngine=LineEngine;
+      break;
+    case CM_LMMV:
+      VdpEngine=LmmvEngine;
+      break;
+    case CM_LMMM:
+      VdpEngine=LmmmEngine;
+      break;
+    case CM_LMCM:
+      VdpEngine=LmcmEngine;
+      break;
+    case CM_LMMC:
+      VdpEngine=LmmcEngine;
+      break;
+    case CM_HMMV:
+      VdpEngine=HmmvEngine;
+      break;
+    case CM_HMMM:
+      VdpEngine=HmmmEngine;
+      break;
+    case CM_YMMM:
+      VdpEngine=YmmmEngine;
+      break;
+    case CM_HMMC:
+      VdpEngine=HmmcEngine;  
+      break;
+    default:
+      if(Verbose&0x02) printf("V9938: Unrecognized opcode %02Xh\n",Op);
+        return(0);
+  }
+
+  /* Fetch unconditional arguments */
+  MMC.SX = (VDP[32]+((int)VDP[33]<<8)) & 511;
+  MMC.SY = (VDP[34]+((int)VDP[35]<<8)) & 1023;
+  MMC.DX = (VDP[36]+((int)VDP[37]<<8)) & 511;
+  MMC.DY = (VDP[38]+((int)VDP[39]<<8)) & 1023;
+  MMC.NY = (VDP[42]+((int)VDP[43]<<8)) & 1023;
+  MMC.TY = VDP[45]&0x08? -1:1;
+  MMC.MX = PPL[SM]; 
+  MMC.CL = VDP[44];
+  MMC.LO = Op&0x0F;
+
+  /* Argument depends on byte or dot operation */
+  if ((MMC.CM & 0x0C) == 0x0C) {
+    MMC.TX = VDP[45]&0x04? -PPB[SM]:PPB[SM];
+    MMC.NX = ((VDP[40]+((int)VDP[41]<<8)) & 1023)/PPB[SM];
+  }
+  else {
+    MMC.TX = VDP[45]&0x04? -1:1;
+    MMC.NX = (VDP[40]+((int)VDP[41]<<8)) & 1023;
+  }
+
+  /* X loop variables are treated specially for LINE command */
+  if (MMC.CM == CM_LINE) {
+    MMC.ASX=((MMC.NX-1)>>1);
+    MMC.ADX=0;
+  }
+  else {
+    MMC.ASX = MMC.SX;
+    MMC.ADX = MMC.DX;
+  }    
+
+  /* NX loop variable is treated specially for SRCH command */
+  if (MMC.CM == CM_SRCH)
+    MMC.ANX=(VDP[45]&0x02)!=0; /* Do we look for "==" or "!="? */
+  else
+    MMC.ANX = MMC.NX;
+
+  /* Command execution started */
+  VDPStatus[2]|=0x01;
+
+  /* Start execution if we still have time slices */
+  if(VdpEngine&&(VdpOpsCnt>0)) VdpEngine();
+
+  /* Operation successfull initiated */
+  return(1);
+}
+
+/** LoopVDP() ************************************************/
+/** Run X steps of active VDP command                       **/
+/*************************************************************/
+void LoopVDP(void)
+{
+  if(VdpOpsCnt<=0)
+  {
+    VdpOpsCnt+=12500;
+    if(VdpEngine&&(VdpOpsCnt>0)) VdpEngine();
+  }
+  else
+  {
+    VdpOpsCnt=12500;
+    if(VdpEngine) VdpEngine();
+  }
+}
+
diff --git a/MCUME_pico2/picomsx/V9938.h b/MCUME_pico2/picomsx/V9938.h
new file mode 100644
index 0000000..9796fb2
--- /dev/null
+++ b/MCUME_pico2/picomsx/V9938.h
@@ -0,0 +1,38 @@
+/** fMSX: portable MSX emulator ******************************/
+/**                                                         **/
+/**                         V9938.h                         **/
+/**                                                         **/
+/** This file contains declarations for V9938 special       **/
+/** graphical operations support implemented in V9938.c.    **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef V9938_H
+#define V9938_H
+
+#include "MSX.h"
+
+/** VDPWrite() ***********************************************/
+/** Use this function to transfer pixel(s) from CPU to VDP. **/
+/*************************************************************/
+void VDPWrite(register byte V);
+
+/** VDPRead() ************************************************/
+/** Use this function to transfer pixel(s) from VDP to CPU. **/
+/*************************************************************/
+byte VDPRead(void);
+
+/** VDPDraw() ************************************************/
+/** Perform a given V9938 graphical operation.              **/
+/*************************************************************/
+byte VDPDraw(register byte Op);
+
+/** LoopVDP() ************************************************/
+/** Perform a number of steps of the active operation       **/
+/*************************************************************/
+void LoopVDP(void);
+
+#endif /* V9938_H */
diff --git a/MCUME_pico2/picomsx/YM2413.c b/MCUME_pico2/picomsx/YM2413.c
new file mode 100644
index 0000000..798a596
--- /dev/null
+++ b/MCUME_pico2/picomsx/YM2413.c
@@ -0,0 +1,288 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         YM2413.c                        **/
+/**                                                         **/
+/** This file contains emulation for the OPLL sound chip    **/
+/** produced by Yamaha (also see OPL2, OPL3, OPL4 chips).   **/
+/** See YM2413.h for declarations.                          **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "YM2413.h"
+#include "Sound.h"
+#include <string.h>
+
+/** Patches2413() ********************************************/
+/** MIDI instruments corresponding to the OPLL patches.     **/
+/*************************************************************/
+static const byte Patches2413[16] =
+{
+      /*** OPLL ***/    /*** MIDI ***/
+  90, /* Original */    /* User (Polysynth) */
+  40, /* Violin */      /* Violin */
+  27, /* Guitar */      /* Electric Guitar (clean) */
+  1,  /* Piano */       /* Bright Acoustic Piano */
+  73, /* Flute */       /* Flute */
+  71, /* Clarinet */    /* Clarinet */
+  68, /* Oboe */        /* Oboe */
+  56, /* Trumpet */     /* Trumpet */
+  20, /* Organ */       /* Reed Organ */
+  58, /* Horn */        /* Tuba */
+  50, /* Synthesizer */ /* Synth Strings 1 */
+  6,  /* Harpsichord */ /* Harpsichord */
+  11, /* Vibraphone */  /* Vibraphone */
+  38, /* Synth Bass */  /* Synth Bass 1 */
+  34, /* Wood Bass */   /* Electric Bass (pick) */
+  33  /* Elec Guitar */ /* Electric Bass (finger) */
+};
+
+/** Drums2413() **********************************************/
+/** MIDI instruments corresponding to the OPLL drums.       **/
+/*************************************************************/
+static const byte Drums2413[5] =
+{
+      /*** OPLL ***/    /*** MIDI ***/
+  42, /* High Hat */    /* Closed Hi Hat */
+  49, /* Top Cymbal */  /* Crash Cymbal 1 */
+  47, /* Tom-Tom */     /* Low-Mid Tom */
+  40, /* Snare Drum */  /* Electric Snare */
+  36  /* Bass Drum */   /* Bass Drum 1 */
+};
+
+/** Synth2413() **********************************************/
+/** Synthesizer parameters corresponding to OPLL patches.   **/
+/*************************************************************/
+static const byte Synth2413[19*16] =
+{
+  0x49,0x4c,0x4c,0x32,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x61,0x61,0x1e,0x17,0xf0,0x7f,0x00,0x17,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x13,0x41,0x16,0x0e,0xfd,0xf4,0x23,0x23,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x03,0x01,0x9a,0x04,0xf3,0xf3,0x13,0xf3,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x11,0x61,0x0e,0x07,0xfa,0x64,0x70,0x17,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x22,0x21,0x1e,0x06,0xf0,0x76,0x00,0x28,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x21,0x22,0x16,0x05,0xf0,0x71,0x00,0x18,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x21,0x61,0x1d,0x07,0x82,0x80,0x17,0x17,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x23,0x21,0x2d,0x16,0x90,0x90,0x00,0x07,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x21,0x21,0x1b,0x06,0x64,0x65,0x10,0x17,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x21,0x21,0x0b,0x1a,0x85,0xa0,0x70,0x07,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x23,0x01,0x83,0x10,0xff,0xb4,0x10,0xf4,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x97,0xc1,0x20,0x07,0xff,0xf4,0x22,0x22,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x61,0x00,0x0c,0x05,0xc2,0xf6,0x40,0x44,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x01,0x56,0x03,0x94,0xc2,0x03,0x12,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x21,0x01,0x89,0x03,0xf1,0xe4,0xf0,0x23,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x07,0x21,0x14,0x00,0xee,0xf8,0xff,0xf8,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x31,0x00,0x00,0xf8,0xf7,0xf8,0xf7,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x25,0x11,0x00,0x00,0xf8,0xfa,0xf8,0x55,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+};
+
+/** Reset2413() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset2413(register YM2413 *D,int First)
+{
+  int J;
+
+  /* All registers filled with 0x00 by default */
+  memset(D->R,0x00,sizeof(D->R));
+
+  /* Set initial frequencies, volumes, and instruments */
+  for(J=0;J<YM2413_CHANNELS;J++)
+  {
+    SetSound(J+First,SND_MELODIC);
+    D->Freq[J]   = 0;
+    D->Volume[J] = 0;
+    D->R[J+0x30] = 0x0F;
+  }
+
+  D->First    = First;
+  D->Sync     = YM2413_ASYNC;
+  D->Changed  = 0x000;
+  D->PChanged = 0x000;
+  D->DChanged = 0x000;
+  D->Latch    = 0;
+}
+
+/** WrCtrl2413() *********************************************/
+/** Write a value V to the OPLL Control Port.               **/
+/*************************************************************/
+void WrCtrl2413(register YM2413 *D,register byte V)
+{
+  D->Latch=V&0x3F;
+}
+
+/** WrData2413() *********************************************/
+/** Write a value V to the OPLL Data Port.                  **/
+/*************************************************************/
+void WrData2413(register YM2413 *D,register byte V)
+{
+  Write2413(D,D->Latch,V);
+}
+
+/** Write2413() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write2413(register YM2413 *D,register byte R,register byte V)
+{
+  register byte C,Oct;
+  register int Frq;
+
+  /* OPLL registers are 0..63 */
+  R&=0x3F;
+
+  /* Lowest 4 bits are channel number */
+  C=R&0x0F;
+
+  switch(R>>4)
+  {
+    case 0:
+      switch(C)
+      {
+        case 0x0E:
+          if(V==D->R[R]) return;
+          /* Keep all drums off when drum mode is off */
+          if(!(V&0x20)) V&=0xE0;
+          /* Mark all activated drums as changed */
+          D->DChanged|=(V^D->R[R])&0x1F;
+          /* If drum mode was turned on... */
+          if((V^D->R[R])&V&0x20)
+          {
+            /* Turn off melodic channels 6,7,8 */
+            D->Freq[6]=D->Freq[7]=D->Freq[8]=0;
+            /* Mark channels 6,7,8 as changed */
+            D->Changed|=0x1C0;
+          }
+          /* Done */
+          break;
+      }
+      break;
+
+    case 1:
+      if((C>8)||(V==D->R[R])) return;
+      if(!YM2413_DRUMS(D)||(C<6))
+        if(D->R[R+0x10]&0x10)
+        {
+          /* Set channel frequency */
+          Oct=D->R[R+0x10];
+          Frq=((int)(Oct&0x01)<<8)+V;
+          Oct=(Oct&0x0E)>>1;
+          D->Freq[C]=(3125*Frq*(1<<Oct))>>15;
+
+          /* Mark channel as changed */
+          D->Changed|=1<<C;
+        }
+      /* Done */
+      break;
+
+    case 2:
+      if(C>8) return;
+      if(!YM2413_DRUMS(D)||(C<6))
+      {
+        /* Depending on whether channel is on/off... */
+        if(!(V&0x10)) D->Freq[C]=0;
+        else
+        {
+          /* Set channel frequency */
+          Frq=((int)(V&0x01)<<8)+D->R[R-0x10];
+          Oct=(V&0x0E)>>1;
+          D->Freq[C]=(3125*Frq*(1<<Oct))>>15;
+        }
+
+        /* Mark channel as changed */
+        D->Changed|=1<<C;
+      }
+      /* Done */
+      break;
+
+    case 3:
+      if((C>8)||(V==D->R[R])) return;
+      /* Register any patch changes */
+      if((V^D->R[R])&0xF0) D->PChanged|=1<<C;
+      /* Register any volume changes */
+      if((V^D->R[R])&0x0F)
+      {
+        /* Set channel volume */
+        D->Volume[C]=255*(~V&0x0F)/15;
+        /* Mark channel as changed */
+        D->Changed|=1<<C;
+      }
+      /* Register drum volume changes */
+      if(YM2413_DRUMS(D))
+        switch(C)
+        {
+          case 6: D->DChanged|=0x10&D->R[0x0E];break;
+          case 7: D->DChanged|=0x09&D->R[0x0E];break;
+          case 8: D->DChanged|=0x06&D->R[0x0E];break;
+        }
+      /* Done */
+      break;
+  }
+
+  /* Write value into the register */
+  D->R[R]=V;
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&(D->Changed||D->PChanged||D->DChanged))
+    Sync2413(D,YM2413_FLUSH);
+}
+
+/** Sync2413() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be YM2413_SYNC/YM2413_ASYNC to set/reset sync,   **/
+/** or YM2413_FLUSH to leave sync mode as it is.            **/
+/*************************************************************/
+void Sync2413(register YM2413 *D,register byte Sync)
+{
+  register int J,I;
+
+  /* Change sync mode as requested */
+  if(Sync!=YM2413_FLUSH) D->Sync=Sync;
+
+  /* Convert channel instrument changes into SetSound() calls */
+  for(J=0,I=D->PChanged;I&&(J<YM2413_CHANNELS);J++,I>>=1)
+    if(I&1) SetSound(J+D->First,SND_MIDI|Patches2413[D->R[J+0x30]>>4]);
+
+  /* Convert channel freq/volume changes into Sound() calls */
+  for(J=0,I=D->Changed;I&&(J<YM2413_CHANNELS);J++,I>>=1)
+    if(I&1) Sound(J+D->First,D->Freq[J],D->Volume[J]);
+
+  /* If there were any changes to the drums... */
+  I=D->DChanged;
+  J=D->R[0x0E];
+  if(I)
+  {
+    /* Turn drums on/off as requested */
+    if(I&0x01) Drum(DRM_MIDI|Drums2413[0],J&0x01? 255*(D->R[0x37]>>4)/15:0);
+    if(I&0x02) Drum(DRM_MIDI|Drums2413[1],J&0x02? 255*(D->R[0x38]&0x0F)/15:0);
+    if(I&0x04) Drum(DRM_MIDI|Drums2413[2],J&0x04? 255*(D->R[0x38]>>4)/15:0);
+    if(I&0x08) Drum(DRM_MIDI|Drums2413[3],J&0x08? 255*(D->R[0x37]&0x0F)/15:0);
+    if(I&0x10) Drum(DRM_MIDI|Drums2413[4],J&0x10? 255*(D->R[0x36]&0x0F)/15:0);
+  }
+
+  D->Changed=D->PChanged=D->DChanged=0x000;
+}
diff --git a/MCUME_pico2/picomsx/YM2413.h b/MCUME_pico2/picomsx/YM2413.h
new file mode 100644
index 0000000..8c267f9
--- /dev/null
+++ b/MCUME_pico2/picomsx/YM2413.h
@@ -0,0 +1,77 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                          YM2413.h                       **/
+/**                                                         **/
+/** This file contains emulation for the OPLL sound chip    **/
+/** produced by Yamaha (also see OPL2, OPL3, OPL4 chips).   **/
+/** See YM2413.h for the code.                              **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef YM2413_H
+#define YM2413_H
+
+#define YM2413_BASE     3125   /* Base frequency for OPLL    */
+#define YM2413_CHANNELS 9      /* 9 melodic channels         */
+
+#define YM2413_ASYNC    0      /* Asynchronous emulation     */
+#define YM2413_SYNC     1      /* Synchronous emulation mode */
+#define YM2413_FLUSH    2      /* Flush buffers only         */
+
+#define YM2413_DRUMS(D) ((D)->R[0x0E]&0x20)
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** YM2413 ***************************************************/
+/** This data structure stores OPLL state.                  **/
+/*************************************************************/
+typedef struct
+{
+  byte R[64];                  /* OPLL register contents     */
+  int Freq[YM2413_CHANNELS];   /* Frequencies (0 for off)    */
+  int Volume[YM2413_CHANNELS]; /* Volumes (0..255)           */
+  int First;                   /* First used Sound() channel */
+  int Changed;                 /* Bitmap of changed channels */
+  int PChanged;                /* Bitmap of changed patches  */
+  int DChanged;                /* Bitmap of changed drums    */
+  byte Sync;                   /* YM2413_SYNC/YM2413_ASYNC   */
+  byte Latch;                  /* Latch for the register num */
+} YM2413;
+
+/** Reset2413() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset2413(register YM2413 *D,int First);
+
+/** WrCtrl2413() *********************************************/
+/** Write a value V to the OPLL Control Port.               **/
+/*************************************************************/
+void WrCtrl2413(register YM2413 *D,register byte V);
+
+/** WrData2413() *********************************************/
+/** Write a value V to the OPLL Data Port.                  **/
+/*************************************************************/
+void WrData2413(register YM2413 *D,register byte V);
+
+/** Write2413() **********************************************/
+/** Call this function to output a value V into given OPLL  **/
+/** register R.                                             **/
+/*************************************************************/
+void Write2413(register YM2413 *D,register byte R,register byte V);
+
+/** Sync2413() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be YM2413_SYNC/YM2413_ASYNC to set/reset sync,   **/
+/** or YM2413_FLUSH to leave sync mode as it is.            **/
+/*************************************************************/
+void Sync2413(register YM2413 *D,register byte Sync);
+
+#endif /* YM2413_H */
diff --git a/MCUME_pico2/picomsx/Z80.c b/MCUME_pico2/picomsx/Z80.c
new file mode 100644
index 0000000..bb828d0
--- /dev/null
+++ b/MCUME_pico2/picomsx/Z80.c
@@ -0,0 +1,631 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.c                         **/
+/**                                                         **/
+/** This file contains implementation for Z80 CPU. Don't    **/
+/** forget to provide RdZ80(), WrZ80(), InZ80(), OutZ80(),  **/
+/** LoopZ80(), and PatchZ80() functions to accomodate the   **/
+/** emulated machine's architecture.                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#include "shared.h" // For endianess!!!
+
+#include "Z80.h"
+#include "Tables.h"
+#include <stdio.h>
+
+/** INLINE ***************************************************/
+/** Different compilers inline C functions differently.     **/
+/*************************************************************/
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE static
+#endif
+
+/** System-Dependent Stuff ***********************************/
+/** This is system-dependent code put here to speed things  **/
+/** up. It has to stay inlined to be fast.                  **/
+/*************************************************************/
+#ifdef COLEM
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>15][A&0x7FFF]); }
+#endif
+#ifdef MG
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>13][A&0x1FFF]); }
+#endif
+#ifdef FMSX
+extern byte *RAM[],PSL[],SSLReg;
+INLINE byte RdZ80(word A)
+{
+  if(A!=0xFFFF) return(RAM[A>>13][A&0x1FFF]);
+  else return((PSL[3]==3)? ~SSLReg:RAM[7][0x1FFF]);
+}
+#endif
+
+#define S(Fl)        R->AF.B.l|=Fl
+#define R(Fl)        R->AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
+
+#define M_RLC(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+#define M_RRC(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+#define M_RL(Rg)       \
+  if(Rg&0x80)          \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+#define M_RR(Rg)       \
+  if(Rg&0x01)          \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+  
+#define M_SLA(Rg)      \
+  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+#define M_SRA(Rg)      \
+  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+
+#define M_SLL(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+#define M_SRL(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+
+#define M_BIT(Bit,Rg)  \
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
+
+#define M_SET(Bit,Rg) Rg|=1<<Bit
+#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
+
+#define M_POP(Rg)      \
+  R->Rg.B.l=RdZ80(R->SP.W++);R->Rg.B.h=RdZ80(R->SP.W++)
+#define M_PUSH(Rg)     \
+  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+
+#define M_CALL         \
+  J.B.l=RdZ80(R->PC.W++);J.B.h=RdZ80(R->PC.W++);         \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
+  R->PC.W=J.W
+
+#define M_JP  J.B.l=RdZ80(R->PC.W++);J.B.h=RdZ80(R->PC.W);R->PC.W=J.W
+#define M_JR  R->PC.W+=(offset)RdZ80(R->PC.W)+1
+#define M_RET R->PC.B.l=RdZ80(R->SP.W++);R->PC.B.h=RdZ80(R->SP.W++)
+
+#define M_RST(Ad)      \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad
+
+#define M_LDWORD(Rg)   \
+  R->Rg.B.l=RdZ80(R->PC.W++);R->Rg.B.h=RdZ80(R->PC.W++)
+
+#define M_ADD(Rg)      \
+  J.W=R->AF.B.h+Rg;     \
+  R->AF.B.l=            \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|                        \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  R->AF.B.h=J.B.l       
+
+#define M_SUB(Rg)      \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  R->AF.B.h=J.B.l
+
+#define M_ADC(Rg)      \
+  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|              \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_SBC(Rg)      \
+  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_CP(Rg)       \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+
+#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
+#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+
+#define M_IN(Rg)        \
+  Rg=InZ80(R->BC.B.l);  \
+  R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+
+#define M_INC(Rg)       \
+  Rg++;                 \
+  R->AF.B.l=            \
+    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+    (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
+
+#define M_DEC(Rg)       \
+  Rg--;                 \
+  R->AF.B.l=            \
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+    (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
+
+#define M_ADDW(Rg1,Rg2) \
+  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
+  R->AF.B.l=                                             \
+    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
+  R->Rg1.W=J.W
+
+#define M_ADCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+   
+#define M_SBCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    N_FLAG|                                                    \
+    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+
+enum Codes
+{
+  NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
+  EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
+  DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
+  JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
+  JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
+  JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
+  JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
+  JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
+  LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
+  LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
+  LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
+  LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
+  LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
+  LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
+  LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
+  LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
+  ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
+  ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
+  SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
+  SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
+  AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
+  XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
+  OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
+  CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
+  RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
+  RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
+  RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
+  RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
+  RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
+  RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
+  RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
+  RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
+};
+
+enum CodesCB
+{
+  RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
+  RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
+  RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
+  RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
+  SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
+  SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
+  SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
+  SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
+  BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
+  BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
+  BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
+  BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
+  BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
+  BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
+  BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
+  BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
+  RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
+  RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
+  RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
+  RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
+  RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
+  RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
+  RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
+  RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
+  SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
+  SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
+  SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
+  SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
+  SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
+  SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
+  SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
+  SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
+};
+  
+enum CodesED
+{
+  DB_00,DB_01,DB_02,DB_03,DB_04,DB_05,DB_06,DB_07,
+  DB_08,DB_09,DB_0A,DB_0B,DB_0C,DB_0D,DB_0E,DB_0F,
+  DB_10,DB_11,DB_12,DB_13,DB_14,DB_15,DB_16,DB_17,
+  DB_18,DB_19,DB_1A,DB_1B,DB_1C,DB_1D,DB_1E,DB_1F,
+  DB_20,DB_21,DB_22,DB_23,DB_24,DB_25,DB_26,DB_27,
+  DB_28,DB_29,DB_2A,DB_2B,DB_2C,DB_2D,DB_2E,DB_2F,
+  DB_30,DB_31,DB_32,DB_33,DB_34,DB_35,DB_36,DB_37,
+  DB_38,DB_39,DB_3A,DB_3B,DB_3C,DB_3D,DB_3E,DB_3F,
+  IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
+  IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,DB_4C,RETI,DB_,LD_R_A,
+  IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,DB_54,DB_55,IM_1,LD_A_I,
+  IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,DB_5C,DB_5D,IM_2,LD_A_R,
+  IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,DB_64,DB_65,DB_66,RRD,
+  IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,DB_6C,DB_6D,DB_6E,RLD,
+  IN_F_xC,DB_71,SBC_HL_SP,LD_xWORDe_SP,DB_74,DB_75,DB_76,DB_77,
+  IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,DB_7C,DB_7D,DB_7E,DB_7F,
+  DB_80,DB_81,DB_82,DB_83,DB_84,DB_85,DB_86,DB_87,
+  DB_88,DB_89,DB_8A,DB_8B,DB_8C,DB_8D,DB_8E,DB_8F,
+  DB_90,DB_91,DB_92,DB_93,DB_94,DB_95,DB_96,DB_97,
+  DB_98,DB_99,DB_9A,DB_9B,DB_9C,DB_9D,DB_9E,DB_9F,
+  LDI,CPI,INI,OUTI,DB_A4,DB_A5,DB_A6,DB_A7,
+  LDD,CPD,IND,OUTD,DB_AC,DB_AD,DB_AE,DB_AF,
+  LDIR,CPIR,INIR,OTIR,DB_B4,DB_B5,DB_B6,DB_B7,
+  LDDR,CPDR,INDR,OTDR,DB_BC,DB_BD,DB_BE,DB_BF,
+  DB_C0,DB_C1,DB_C2,DB_C3,DB_C4,DB_C5,DB_C6,DB_C7,
+  DB_C8,DB_C9,DB_CA,DB_CB,DB_CC,DB_CD,DB_CE,DB_CF,
+  DB_D0,DB_D1,DB_D2,DB_D3,DB_D4,DB_D5,DB_D6,DB_D7,
+  DB_D8,DB_D9,DB_DA,DB_DB,DB_DC,DB_DD,DB_DE,DB_DF,
+  DB_E0,DB_E1,DB_E2,DB_E3,DB_E4,DB_E5,DB_E6,DB_E7,
+  DB_E8,DB_E9,DB_EA,DB_EB,DB_EC,DB_ED,DB_EE,DB_EF,
+  DB_F0,DB_F1,DB_F2,DB_F3,DB_F4,DB_F5,DB_F6,DB_F7,
+  DB_F8,DB_F9,DB_FA,DB_FB,DB_FC,DB_FD,DB_FE,DB_FF
+};
+
+static void CodesCB(register Z80 *R)
+{
+  register byte I;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesCB[I];
+  switch(I)
+  {
+#include "CodesCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (   
+          "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
+          (long)(R->User),RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IX    
+  J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
+          (long)(R->User),RdZ80(R->PC.W-2),RdZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesFDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IY
+  J.W=R->XX.W+(offset)RdZ80(R->PC.W++);
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-2),RdZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesED(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesED[I];
+  switch(I)
+  {
+#include "CodesED.h"
+    case PFX_ED:
+      R->PC.W--;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IX
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesDDCB(R);break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
+          (long)R->User,RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+static void CodesFD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IY
+  I=RdZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesFDCB(R);break;
+    default:
+        printf
+        (
+          "Unrecognized instruction: FD %02X at PC=%04X\n",
+          RdZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the register struct  **/
+/** before starting execution with Z80(). It sets the       **/
+/** registers to their supposed initial values.             **/
+/*************************************************************/
+void ResetZ80(Z80 *R)
+{
+  R->PC.W     = 0x0000;
+  R->SP.W     = 0xF000;
+  R->AF.W     = 0x0000;
+  R->BC.W     = 0x0000;
+  R->DE.W     = 0x0000;
+  R->HL.W     = 0x0000;
+  R->AF1.W    = 0x0000;
+  R->BC1.W    = 0x0000;
+  R->DE1.W    = 0x0000;
+  R->HL1.W    = 0x0000;
+  R->IX.W     = 0x0000;
+  R->IY.W     = 0x0000;
+  R->I        = 0x00;
+  R->IFF      = 0x00;
+  R->ICount   = R->IPeriod;
+  R->IRequest = INT_NONE;
+}
+
+/** ExecZ80() ************************************************/
+/** This function will execute a single Z80 opcode. It will **/
+/** then return next PC, and current register values in R.  **/
+/*************************************************************/
+word ExecZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=RdZ80(R->PC.W++);
+  R->ICount-=Cycles[I];
+  switch(I)
+  {
+#include "Codes.h"
+    case PFX_CB: CodesCB(R);break;
+    case PFX_ED: CodesED(R);break;
+    case PFX_FD: CodesFD(R);break;
+    case PFX_DD: CodesDD(R);break;
+  }
+
+  /* We are done */
+  return(R->PC.W);
+}
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(Z80 *R,word Vector)
+{
+  if((R->IFF&IFF_1)||(Vector==INT_NMI))
+  {
+    /* If HALTed, take CPU off HALT instruction */
+    if(R->IFF&IFF_HALT) { R->PC.W++;R->IFF&=~IFF_HALT; }
+
+    /* Save PC on stack */
+    M_PUSH(PC);
+
+    /* Automatically reset IRequest if needed */
+    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+
+    /* If it is NMI... */
+    if(Vector==INT_NMI)
+    {
+      /* Copy IFF1 to IFF2 */
+      if(R->IFF&IFF_1) R->IFF|=IFF_2; else R->IFF&=~IFF_2;
+      /* Clear IFF1 */
+      R->IFF&=~(IFF_1|IFF_EI);
+      /* Jump to hardwired NMI vector */
+      R->PC.W=0x0066;
+      /* Done */
+      return;
+    }
+
+    /* Further interrupts off */
+    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+
+    /* If in IM2 mode... */
+    if(R->IFF&IFF_IM2)
+    {
+      /* Make up the vector address */
+      Vector=(Vector&0xFF)|((word)(R->I)<<8);
+      /* Read the vector */
+      R->PC.B.l=RdZ80(Vector++);
+      R->PC.B.h=RdZ80(Vector);
+      /* Done */
+      return;
+    }
+
+    /* If in IM1 mode, just jump to hardwired IRQ vector */
+    if(R->IFF&IFF_IM1) { R->PC.W=0x0038;return; }
+
+    /* If in IM0 mode... */
+
+    /* Jump to a vector */
+    switch(Vector)
+    {
+      case INT_RST00: R->PC.W=0x0000;break;
+      case INT_RST08: R->PC.W=0x0008;break;
+      case INT_RST10: R->PC.W=0x0010;break;
+      case INT_RST18: R->PC.W=0x0018;break;
+      case INT_RST20: R->PC.W=0x0020;break;
+      case INT_RST28: R->PC.W=0x0028;break;
+      case INT_RST30: R->PC.W=0x0030;break;
+      case INT_RST38: R->PC.W=0x0038;break;
+    }
+  }
+}
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+word RunZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+  int ras=0;
+ 
+  for(;;)
+  {
+#ifdef DEBUG
+    /* Turn tracing on when reached trap address */
+    if(R->PC.W==R->Trap) R->Trace=1;
+    /* Call single-step debugger, exit if requested */
+    if(R->Trace)
+      if(!DebugZ80(R)) return(R->PC.W);
+#endif
+
+    I=RdZ80(R->PC.W++);
+    R->ICount-=Cycles[I];
+    switch(I)
+    {
+#include "Codes.h"
+      case PFX_CB: CodesCB(R);break;
+      case PFX_ED: CodesED(R);break;
+      case PFX_FD: CodesFD(R);break;
+      case PFX_DD: CodesDD(R);break;
+    }
+ 
+    /* If cycle counter expired... */
+    if(R->ICount<=0)
+    {
+      /* If we have come after EI, get address from IRequest */
+      /* Otherwise, get it from the loop handler             */
+      if(R->IFF&IFF_EI)
+      {
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
+        R->ICount+=R->IBackup-1;       /* Restore the ICount      */
+
+        /* Call periodic handler or set pending IRQ */
+        if(R->ICount>0) J.W=R->IRequest;
+        else
+        {
+          J.W=LoopZ80(R, &ras);        /* Call periodic handler    */
+          R->ICount+=R->IPeriod; /* Reset the cycle counter  */
+          if(J.W==INT_NONE) J.W=R->IRequest;  /* Pending IRQ */
+        }
+      }
+      else
+      {
+        J.W=LoopZ80(R, &ras);          /* Call periodic handler    */
+        R->ICount+=R->IPeriod;   /* Reset the cycle counter  */
+        if(J.W==INT_NONE) J.W=R->IRequest;    /* Pending IRQ */
+      }
+
+      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
+    }
+    if (ras == 1) break;
+  }
+
+  /* Execution stopped */
+  return(R->PC.W);
+}
diff --git a/MCUME_pico2/picomsx/Z80.h b/MCUME_pico2/picomsx/Z80.h
new file mode 100644
index 0000000..4e4c6ae
--- /dev/null
+++ b/MCUME_pico2/picomsx/Z80.h
@@ -0,0 +1,165 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to emulation   **/
+/** of Z80 CPU.                                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2005                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef Z80_H
+#define Z80_H
+
+                               /* Compilation options:       */
+/* #define DEBUG */            /* Compile debugging version  */
+/* #define LSB_FIRST */        /* Compile for low-endian CPU */
+/* #define MSB_FIRST */        /* Compile for hi-endian CPU  */
+
+                               /* LoopZ80() may return:      */
+#define INT_RST00   0x00C7     /* RST 00h                    */
+#define INT_RST08   0x00CF     /* RST 08h                    */
+#define INT_RST10   0x00D7     /* RST 10h                    */
+#define INT_RST18   0x00DF     /* RST 18h                    */
+#define INT_RST20   0x00E7     /* RST 20h                    */
+#define INT_RST28   0x00EF     /* RST 28h                    */
+#define INT_RST30   0x00F7     /* RST 30h                    */
+#define INT_RST38   0x00FF     /* RST 38h                    */
+#define INT_IRQ     INT_RST38  /* Default IRQ opcode is FFh  */
+#define INT_NMI     0xFFFD     /* Non-maskable interrupt     */
+#define INT_NONE    0xFFFF     /* No interrupt required      */
+#define INT_QUIT    0xFFFE     /* Exit the emulation         */
+
+                               /* Bits in Z80 F register:    */
+#define S_FLAG      0x80       /* 1: Result negative         */
+#define Z_FLAG      0x40       /* 1: Result is zero          */
+#define H_FLAG      0x10       /* 1: Halfcarry/Halfborrow    */
+#define P_FLAG      0x04       /* 1: Result is even          */
+#define V_FLAG      0x04       /* 1: Overflow occured        */
+#define N_FLAG      0x02       /* 1: Subtraction occured     */
+#define C_FLAG      0x01       /* 1: Carry/Borrow occured    */
+
+                               /* Bits in IFF flip-flops:    */
+#define IFF_1       0x01       /* IFF1 flip-flop             */
+#define IFF_IM1     0x02       /* 1: IM1 mode                */
+#define IFF_IM2     0x04       /* 1: IM2 mode                */
+#define IFF_2       0x08       /* IFF2 flip-flop             */
+#define IFF_EI      0x20       /* 1: EI pending              */
+#define IFF_HALT    0x80       /* 1: CPU HALTed              */
+
+/** Simple Datatypes *****************************************/
+/** NOTICE: sizeof(byte)=1 and sizeof(word)=2               **/
+/*************************************************************/
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+#ifndef WORD_TYPE_DEFINED
+#define WORD_TYPE_DEFINED
+typedef unsigned short word;
+#endif
+typedef signed char offset;
+
+/** Structured Datatypes *************************************/
+/** NOTICE: #define LSB_FIRST for machines where least      **/
+/**         signifcant byte goes first.                     **/
+/*************************************************************/
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+
+typedef struct
+{
+  pair AF,BC,DE,HL,IX,IY,PC,SP;       /* Main registers      */
+  pair AF1,BC1,DE1,HL1;               /* Shadow registers    */
+  byte IFF,I;                         /* Interrupt registers */
+  byte R;                             /* Refresh register    */
+
+  int IPeriod,ICount; /* Set IPeriod to number of CPU cycles */
+                      /* between calls to LoopZ80()          */
+  int IBackup;        /* Private, don't touch                */
+  word IRequest;      /* Set to address of pending IRQ       */
+  byte IAutoReset;    /* Set to 1 to autom. reset IRequest   */
+  byte TrapBadOps;    /* Set to 1 to warn of illegal opcodes */
+  word Trap;          /* Set Trap to address to trace from   */
+  byte Trace;         /* Set Trace=1 to start tracing        */
+  void *User;         /* Arbitrary user data (ID,RAM*,etc.)  */
+} Z80;
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the registers before **/
+/** starting execution with RunZ80(). It sets registers to  **/
+/** their initial values.                                   **/
+/*************************************************************/
+void ResetZ80(register Z80 *R);
+
+/** ExecZ80() ************************************************/
+/** This function will execute a single Z80 opcode. It will **/
+/** then return next PC, and current register values in R.  **/
+/*************************************************************/
+word ExecZ80(register Z80 *R);
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(register Z80 *R,register word Vector);
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+word RunZ80(register Z80 *R);
+
+/** RdZ80()/WrZ80() ******************************************/
+/** These functions are called when access to RAM occurs.   **/
+/** They allow to control memory access.                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void WrZ80(register word Addr,register byte Value);
+byte RdZ80(register word Addr);
+
+/** InZ80()/OutZ80() *****************************************/
+/** Z80 emulation calls these functions to read/write from  **/
+/** I/O ports. There can be 65536 I/O ports, but only first **/
+/** 256 are usually used.                                   **/
+/************************************ TO BE WRITTEN BY USER **/
+void OutZ80(register word Port,register byte Value);
+byte InZ80(register word Port);
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/** For example, it can be called to emulate BIOS calls,    **/
+/** such as disk and tape access. Replace it with an empty  **/
+/** macro for no patching.                                  **/
+/************************************ TO BE WRITTEN BY USER **/
+void PatchZ80(register Z80 *R);
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers. Emulation exits   **/
+/** if DebugZ80() returns 0.                                **/
+/*************************************************************/
+#ifdef DEBUG
+byte DebugZ80(register Z80 *R);
+#endif
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts. This    **/
+/** function must return an address of the interrupt vector **/
+/** (0x0038, 0x0066, etc.) or INT_NONE for no interrupt.    **/
+/** Return INT_QUIT to exit the emulation loop.             **/
+/************************************ TO BE WRITTEN BY USER **/
+word LoopZ80(register Z80 *R, int * ras);
+
+#endif /* Z80_H */
diff --git a/MCUME_pico2/picomsx/bios/cmos.h b/MCUME_pico2/picomsx/bios/cmos.h
new file mode 100644
index 0000000..1e01ebe
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/cmos.h
@@ -0,0 +1,5 @@
+static const uint8_t CMOS[52] = {
+0xF3,0xF0,0xF5,0xF4,0xF4,0xF1,0xF4,0xF9,0xF1,0xF6,0xF0,0xF3,0xF2,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x0A,0x00,0x00,0x00,0x05,0x02,
+0x0F,0x04,0x04,0x03,0x01,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,};
diff --git a/MCUME_pico2/picomsx/bios/disk.h b/MCUME_pico2/picomsx/bios/disk.h
new file mode 100644
index 0000000..395eaf3
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/disk.h
@@ -0,0 +1,1026 @@
+static const uint8_t DISK[16384] = {
+0x41,0x42,0x6F,0x57,0x76,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xC3,0x4D,0x74,0xC3,0x0B,0x78,0xC3,0x5F,0x78,0xC3,0x7F,0x78,0xC3,0xBE,0x78,0xC3,
+0x8E,0x77,0xC3,0x3A,0x5B,0x37,0xC3,0xB1,0x60,0xC3,0x0D,0x62,0x00,0xC3,0xB3,0x5F,
+0x2A,0x4B,0xF3,0xC9,0xDD,0xE5,0xDD,0x21,0xB7,0x00,0xCD,0xAB,0x40,0xDD,0xE1,0x30,
+0x0A,0x3E,0x03,0x32,0x36,0xF3,0x32,0x37,0xF3,0xA7,0xC9,0x3A,0x36,0xF3,0xA7,0x3A,
+0x37,0xF3,0xC0,0xDD,0xE5,0xDD,0x21,0x9C,0x00,0xCD,0xAB,0x40,0xDD,0xE1,0xC8,0x3E,
+0xFF,0x32,0x36,0xF3,0xDD,0xE5,0xDD,0x21,0x9F,0x00,0xCD,0xAB,0x40,0xDD,0xE1,0x32,
+0x37,0xF3,0xC5,0x06,0x00,0x04,0xC1,0xC9,0xE5,0x21,0x36,0xF3,0xAF,0xBE,0x77,0x23,
+0x7E,0xE1,0xC0,0xDD,0xE5,0xDD,0x21,0x9F,0x00,0xCD,0xAB,0x40,0xDD,0xE1,0xC9,0xDD,
+0xE5,0xDD,0x21,0xA2,0x00,0xCD,0xAB,0x40,0xDD,0xE1,0xC9,0xDD,0xE5,0xDD,0x21,0xA5,
+0x00,0xCD,0xAB,0x40,0xDD,0xE1,0xC9,0xDD,0x21,0x9B,0x40,0xFD,0xE5,0xFD,0x2A,0xC0,
+0xFC,0xCD,0x1C,0x00,0xFB,0xFD,0xE1,0xC9,0x3E,0x0D,0xD3,0xB4,0x3E,0x0A,0xD3,0xB5,
+0xAF,0xD3,0xB4,0x06,0x0F,0xDB,0xB5,0xE6,0x0F,0xA8,0xD3,0xB5,0x4F,0x00,0xDB,0xB5,
+0xE6,0x0F,0xB9,0xC0,0xA8,0xD3,0xB5,0x10,0xEC,0x3E,0xFF,0x32,0x38,0xF3,0x3E,0x0D,
+0xD3,0xB4,0x3E,0x09,0xD3,0xB5,0x3E,0x0A,0xD3,0xB4,0x3E,0x01,0xD3,0xB5,0x3E,0x0D,
+0xD3,0xB4,0xAF,0xD3,0xB5,0x01,0x00,0x0D,0x79,0xD3,0xB4,0xDB,0xB5,0xF5,0x0C,0x10,
+0xF7,0x3E,0x0E,0xD3,0xB4,0xAF,0xD3,0xB5,0x06,0x0D,0x0D,0x79,0xD3,0xB4,0xF1,0xD3,
+0xB5,0x10,0xF7,0x18,0x39,0x22,0x3B,0xF3,0x3A,0x38,0xF3,0xA7,0xC8,0x3A,0x4A,0xF2,
+0x47,0x3A,0x49,0xF2,0x4F,0x3A,0x48,0xF2,0x57,0x1E,0x07,0xCD,0x6C,0x7E,0x18,0x12,
+0x3A,0x38,0xF3,0xA7,0xC8,0x1E,0x00,0xCD,0x59,0x41,0x3E,0x0F,0xD3,0xB4,0x3E,0x02,
+0xD3,0xB5,0x62,0xCD,0x60,0x41,0x61,0xCD,0x60,0x41,0x60,0xCD,0x60,0x41,0x3E,0x0D,
+0xD3,0xB4,0xDB,0xB5,0xF6,0x08,0xD3,0xB5,0xC9,0xCD,0x4E,0x41,0xE6,0x04,0x18,0xF6,
+0xAF,0x2E,0x08,0xCB,0x04,0x8F,0x27,0x2D,0x20,0xF9,0xCD,0x71,0x41,0x0F,0x0F,0x0F,
+0x0F,0xF5,0x7B,0x1C,0xD3,0xB4,0xF1,0x18,0xDD,0x3A,0x38,0xF3,0xA7,0x47,0x4F,0x57,
+0x5F,0x2A,0x3B,0xF3,0xC8,0xCD,0x59,0x41,0x1E,0x0D,0xCD,0xAD,0x41,0xCD,0x23,0x55,
+0xCD,0xAD,0x41,0x32,0x49,0xF2,0xCD,0xAD,0x41,0x32,0x48,0xF2,0x1D,0xCD,0xAD,0x41,
+0x47,0xCD,0xAD,0x41,0x4F,0xCD,0xAD,0x41,0xCD,0x4E,0x41,0x37,0xC9,0xAF,0xCD,0xB5,
+0x41,0x87,0x87,0x82,0x87,0x57,0x1D,0x7B,0xD3,0xB4,0xDB,0xB5,0xE6,0x0F,0x82,0x57,
+0xC9,0x20,0x4D,0x53,0x58,0x2D,0x44,0x4F,0x53,0x20,0x76,0x65,0x72,0x2E,0x20,0x32,
+0x2E,0x32,0x20,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x31,0x39,0x38,
+0x34,0x20,0x62,0x79,0x20,0x4D,0x69,0x63,0x72,0x6F,0x73,0x6F,0x66,0x74,0x20,0x06,
+0x00,0x3E,0x22,0xC9,0xDD,0x5E,0x13,0xDD,0x56,0x14,0xCD,0x52,0xF2,0xD5,0x5D,0x54,
+0xCB,0x3C,0xCB,0x1D,0x1F,0x19,0xD1,0x19,0x17,0x7E,0x23,0x66,0x30,0x0C,0xCB,0x3C,
+0x1F,0xCB,0x3C,0x1F,0xCB,0x3C,0x1F,0xCB,0x3C,0x1F,0x6F,0x7C,0xE6,0x0F,0x67,0xB5,
+0xC9,0xD5,0x5D,0x54,0xCB,0x3C,0xCB,0x1D,0x1F,0x19,0xD1,0x19,0x17,0x30,0x18,0xCB,
+0x21,0xCB,0x10,0xCB,0x21,0xCB,0x10,0xCB,0x21,0xCB,0x10,0xCB,0x21,0xCB,0x10,0x7E,
+0xE6,0x0F,0xB1,0x77,0x23,0x70,0xC9,0x71,0x23,0x7E,0xE6,0xF0,0xB0,0x77,0xC9,0x11,
+0xB9,0xF2,0x1A,0xBE,0x23,0x13,0xC0,0x10,0xF9,0xC9,0xCD,0x55,0xF2,0x21,0xF7,0xF1,
+0x0E,0x05,0x06,0x04,0xCD,0x4F,0x42,0x20,0x2F,0x06,0x04,0x1A,0x13,0xFE,0x20,0x20,
+0x32,0x10,0xF8,0x79,0xED,0x44,0x32,0x16,0xF2,0x21,0xB9,0xF2,0x11,0x0B,0xF2,0x01,
+0x04,0x00,0xED,0xB0,0xCD,0x96,0x54,0xED,0x43,0x23,0xF2,0xED,0x53,0x21,0xF2,0x21,
+0x0B,0xF2,0xE5,0xFD,0xE1,0xF6,0x01,0xC9,0x05,0x7D,0x80,0x6F,0x7C,0xCE,0x00,0x67,
+0x0D,0x20,0xBF,0x37,0xC9,0xD5,0x21,0x0E,0x00,0x19,0x36,0x00,0xCD,0xB1,0x42,0xD1,
+0xC9,0xCD,0x0E,0x44,0xD8,0xCD,0x5A,0x42,0xD0,0xCD,0xD3,0x44,0xCD,0x58,0xF2,0xCD,
+0x0E,0x43,0xD8,0x7E,0xB7,0x28,0x35,0xFE,0xE5,0x28,0x31,0xE5,0x06,0x0B,0x11,0xB9,
+0xF2,0xCD,0x52,0x42,0x28,0x06,0xFE,0x3F,0x20,0x1B,0x10,0xF5,0xE1,0xE5,0xFD,0xE1,
+0x3A,0xC4,0xF2,0xEE,0x80,0xCB,0x7F,0xC8,0xFD,0x7E,0x0B,0xE6,0x1E,0xC8,0x3A,0xDC,
+0xF2,0xB7,0xC0,0x18,0x01,0xE1,0xCD,0x48,0x43,0x30,0xC8,0xC9,0x3A,0xFE,0xF2,0x3C,
+0x20,0x06,0x3A,0xB8,0xF2,0x32,0xFE,0xF2,0x7E,0xB7,0x20,0xEA,0x37,0xC9,0x3A,0xB8,
+0xF2,0x3C,0xDD,0xBE,0x0B,0x30,0x50,0xCD,0x5B,0xF2,0x32,0xB8,0xF2,0x4F,0xDD,0xA6,
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+0x40,0xCB,0x43,0xC0,0xCD,0x24,0x01,0xCD,0x1D,0x01,0x79,0x32,0xFB,0xBF,0xE3,0xE3,
+0x3E,0x10,0x32,0xF8,0xBF,0xE3,0xE3,0xCD,0x1D,0x01,0x18,0x25,0x3A,0xF8,0xBF,0x1F,
+0x38,0xFA,0xC9,0x3A,0xF9,0xBF,0xB7,0x20,0x11,0xC5,0x06,0x05,0xCD,0x1D,0x01,0x3E,
+0x50,0x32,0xF8,0xBF,0xE3,0xE3,0x05,0x20,0xF3,0xC1,0xCD,0x1D,0x01,0x3E,0x00,0x18,
+0xD1,0xE5,0x21,0x7B,0x11,0x2B,0x7C,0xB5,0x20,0xFB,0xE1,0xAF,0xC9,0xE5,0xD5,0xC5,
+0xCD,0x2D,0x40,0x32,0xC5,0x00,0x26,0x80,0xCD,0x24,0x00,0xFB,0x3A,0x42,0xF3,0x26,
+0x40,0xCD,0x24,0x00,0xFB,0xC1,0xD1,0xE1,0xCD,0xCF,0xFF,0xF3,0x2B,0x7C,0xC6,0x02,
+0x23,0xFA,0xB4,0x00,0x1E,0x15,0xCD,0x2E,0x01,0x3E,0xA0,0xCB,0x72,0x28,0x08,0xF6,
+0x02,0xCB,0x42,0x28,0x02,0xF6,0x08,0xE5,0xD5,0xC5,0x11,0x55,0x00,0xD5,0x32,0xF8,
+0xBF,0x01,0xFF,0xBF,0x0A,0x87,0xF0,0xDA,0x47,0x00,0x7E,0x32,0xFB,0xBF,0x23,0xC3,
+0x47,0x00,0xC1,0xD1,0xE1,0x3A,0xF8,0xBF,0xE6,0xFC,0x20,0x08,0x05,0x28,0x52,0xCD,
+0xD1,0x00,0x18,0xB8,0xFA,0xAE,0x00,0xCB,0x77,0x20,0x1F,0xF5,0xCD,0x13,0x01,0xF1,
+0x1D,0x20,0xB3,0x5F,0xCB,0x6B,0x3E,0x0A,0x20,0x36,0xCB,0x63,0x3E,0x08,0x20,0x30,
+0xCB,0x5B,0x3E,0x04,0x20,0x2A,0x3E,0x0C,0x18,0x26,0x3E,0xD0,0x32,0xF8,0xBF,0xE3,
+0xE3,0x3E,0x80,0x32,0xF8,0xBF,0xE3,0xE3,0x21,0xFF,0xBF,0x11,0x00,0x00,0x7E,0x87,
+0x38,0x0D,0xC3,0xB2,0x00,0x1B,0x7B,0xB2,0xC2,0xA1,0x00,0x3E,0x02,0x18,0x01,0xAF,
+0x37,0xE5,0xD5,0xC5,0xF5,0x3A,0x43,0xF3,0x26,0x80,0xCD,0x24,0x00,0xCD,0x68,0xF3,
+0xFB,0x3E,0x00,0x26,0x40,0xCD,0x24,0x00,0xFB,0xF1,0xC1,0xD1,0xE1,0xC9,0xCD,0x2E,
+0x01,0x24,0x24,0x3A,0xFA,0xBF,0x3C,0x32,0xFA,0xBF,0xCB,0x7A,0x20,0x03,0xFE,0x0A,
+0xD8,0xFE,0x09,0xD8,0x3E,0x01,0x32,0xFA,0xBF,0xCB,0x72,0x28,0x0B,0xCB,0x42,0x20,
+0x07,0xCB,0xC2,0x32,0xFC,0xBF,0x18,0x14,0xCB,0x82,0xAF,0x32,0xFC,0xBF,0x0C,0xCD,
+0x2E,0x01,0x3E,0x50,0x32,0xF8,0xBF,0xE3,0xE3,0xCD,0x2E,0x01,0x37,0x3F,0x18,0x40,
+0xCB,0x43,0xC0,0xCD,0x35,0x01,0xCD,0x2E,0x01,0x79,0x32,0xFB,0xBF,0xE3,0xE3,0x3E,
+0x10,0x32,0xF8,0xBF,0xE3,0xE3,0xCD,0x2E,0x01,0x18,0x25,0x3A,0xF8,0xBF,0x1F,0x38,
+0xFA,0xC9,0x3A,0xF9,0xBF,0xB7,0x20,0x11,0xC5,0x06,0x05,0xCD,0x2E,0x01,0x3E,0x50,
+0x32,0xF8,0xBF,0xE3,0xE3,0x05,0x20,0xF3,0xC1,0xCD,0x2E,0x01,0x3E,0x00,0x18,0xD1,
+0xE5,0x21,0x7B,0x11,0x2B,0x7D,0xB4,0x20,0xFB,0xE1,0xAF,0xC9,0x3E,0x0D,0xD3,0xB4,
+0xDB,0xB5,0xE6,0x04,0xF5,0xF6,0x01,0xD3,0xB5,0x3E,0x0B,0xD3,0xB4,0x78,0xD3,0xB5,
+0x3E,0x0D,0xD3,0xB4,0xF1,0xD3,0xB5,0xC9,0xEB,0xFE,0x90,0x4E,0x4D,0x53,0x20,0x20,
+0x32,0x2E,0x32,0x00,0x02,0x02,0x01,0x00,0x02,0x70,0x00,0xD0,0x02,0xF8,0x02,0x00,
+0x09,0x00,0x01,0x00,0x00,0x00,0xD0,0xED,0x53,0x59,0xC0,0x32,0xD0,0xC0,0x36,0x56,
+0x23,0x36,0xC0,0x31,0x1F,0xF5,0x11,0xAB,0xC0,0x0E,0x0F,0xCD,0x7D,0xF3,0x3C,0xCA,
+0x63,0xC0,0x11,0x00,0x01,0x0E,0x1A,0xCD,0x7D,0xF3,0x21,0x01,0x00,0x22,0xB9,0xC0,
+0x21,0x00,0x3F,0x11,0xAB,0xC0,0x0E,0x27,0xCD,0x7D,0xF3,0xC3,0x00,0x01,0x58,0xC0,
+0xCD,0x00,0x00,0x79,0xE6,0xFE,0xFE,0x02,0xC2,0x6A,0xC0,0x3A,0xD0,0xC0,0xA7,0xCA,
+0x22,0x40,0x11,0x85,0xC0,0xCD,0x77,0xC0,0x0E,0x07,0xCD,0x7D,0xF3,0x18,0xB4,0x1A,
+0x13,0xB7,0xC8,0xD5,0x5F,0x0E,0x06,0xCD,0x7D,0xF3,0xD1,0x18,0xF2,0x42,0x6F,0x6F,
+0x74,0x20,0x65,0x72,0x72,0x6F,0x72,0x0D,0x0A,0x50,0x72,0x65,0x73,0x73,0x20,0x61,
+0x6E,0x79,0x20,0x6B,0x65,0x79,0x20,0x66,0x6F,0x72,0x20,0x72,0x65,0x74,0x72,0x79,
+0x0D,0x0A,0x00,0x00,0x4D,0x53,0x58,0x44,0x4F,0x53,0x20,0x20,0x53,0x59,0x53,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0x24,0x00,0x05,0x00,0xFF,0xFF,0xFF,0xFF,
+};
diff --git a/MCUME_pico2/picomsx/bios/fmpac.h b/MCUME_pico2/picomsx/bios/fmpac.h
new file mode 100644
index 0000000..b848562
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/fmpac.h
@@ -0,0 +1,1026 @@
+static const uint8_t FMPAC[16384] = {
+0x41,0x42,0x00,0x00,0x82,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x41,0x43,0x32,0x4F,0x50,0x4C,0x4C,
+0xC3,0x64,0x40,0xC3,0x5E,0x40,0xC3,0x48,0x40,0xC3,0x2F,0x40,0xC3,0x3D,0x40,0xC5,
+0x01,0xF7,0x7F,0x0A,0x08,0x7B,0x02,0x7E,0x08,0x02,0x08,0xC1,0xC9,0xCD,0x2F,0x40,
+0x57,0x23,0xCD,0x2F,0x40,0x67,0x6A,0xC9,0x3A,0xF7,0x7F,0x08,0xD9,0xE1,0xD1,0xD5,
+0xE5,0x7B,0xD9,0x32,0xF7,0x7F,0xEB,0xED,0xB0,0x08,0x32,0xF7,0x7F,0xC9,0xC5,0xD9,
+0xE1,0xC3,0x64,0x40,0xD9,0x08,0x3A,0xF7,0x7F,0xF5,0x7B,0x32,0xF7,0x7F,0x11,0x76,
+0x40,0xD5,0xE5,0x08,0xD9,0xC9,0x08,0xF1,0x32,0xF7,0x7F,0x08,0xC9,0x00,0x00,0x00,
+0x00,0x50,0xE5,0x21,0x89,0xFD,0x11,0xB3,0x40,0x1A,0xBE,0x23,0x13,0x20,0x17,0xA7,
+0x20,0xF7,0xE1,0x3A,0x06,0x50,0x3C,0xC4,0x06,0x50,0x1E,0x01,0x21,0x80,0x40,0xCD,
+0x2C,0x40,0xD9,0xC3,0x20,0x40,0xE1,0xED,0x5B,0x80,0x40,0x7A,0xA3,0x3C,0xD5,0xC0,
+0xD1,0x37,0xC9,0x46,0x4D,0x50,0x41,0x43,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0x56,0x31,0x2E,0x33,0x20,0x31,0x39,0x38,0x38,0x20,0x30,0x34,0x20,0x32,0x36,0x00,
+0xC3,0x40,0x41,0xC3,0x7B,0x41,0xC3,0xCE,0x42,0xC3,0xDA,0x43,0xC3,0x30,0x44,0xC3,
+0x47,0x44,0xC3,0x3B,0x47,0xC9,0x26,0x47,0xAB,0x00,0xB5,0x00,0xC0,0x00,0xCC,0x00,
+0xD8,0x00,0xE5,0x00,0xF2,0x00,0x01,0x01,0x10,0x01,0x20,0x01,0x31,0x01,0x43,0x01,
+0xD3,0x7C,0xF5,0x7B,0xD3,0x7D,0xE3,0xE3,0xE3,0xE3,0xE3,0xE3,0xE3,0xE3,0xF1,0xC9,
+0xFD,0xE5,0xD5,0xC6,0x00,0x16,0x00,0x5F,0xFD,0x19,0xD1,0xD3,0x7C,0xF5,0x7B,0xD3,
+0x7D,0xFD,0x77,0x00,0xE3,0xE3,0xE3,0xE3,0xF1,0xFD,0xE1,0xC9,0xE5,0xFD,0xE5,0xE1,
+0xC6,0x00,0x85,0x6F,0x7C,0xCE,0x00,0x67,0x7E,0xE1,0xC9,0xF3,0x7D,0xE6,0xFE,0x6F,
+0xE5,0x01,0x00,0x40,0xCD,0xDC,0x41,0xC1,0x7E,0xE6,0x01,0xB1,0x77,0x23,0x70,0xC5,
+0xFD,0xE1,0xCD,0x30,0x42,0xFD,0xE5,0xE1,0x11,0x00,0x00,0x19,0x5D,0x54,0x13,0x01,
+0xA0,0x00,0x36,0x00,0xED,0xB0,0x3E,0x00,0xCD,0x3B,0x46,0x3E,0x0E,0x1E,0x00,0xCD,
+0x50,0x41,0x3C,0xCD,0x50,0x41,0x3E,0x10,0x1E,0x20,0x06,0x09,0xCD,0x50,0x41,0x3C,
+0x10,0xFA,0x3E,0x20,0x1E,0x07,0x06,0x09,0xCD,0x50,0x41,0x3C,0x10,0xFA,0x3E,0x30,
+0x1E,0xB3,0x06,0x09,0xCD,0x50,0x41,0x3C,0x10,0xFA,0xFB,0xC9,0xCD,0xF6,0x41,0xE6,
+0x0F,0x6F,0x07,0x07,0x07,0x07,0xE6,0x30,0xB5,0xE6,0x3C,0xF6,0x01,0x07,0x5F,0x16,
+0x00,0x21,0x09,0xFD,0x19,0xC9,0xC5,0xD5,0xE5,0x78,0x07,0x07,0xE6,0x03,0x47,0xDB,
+0xA8,0xCD,0x26,0x42,0xE6,0x03,0x5F,0x16,0x00,0x21,0xC1,0xFC,0x19,0x7E,0xE6,0x80,
+0xB3,0xF2,0x22,0x42,0x5F,0x23,0x23,0x23,0x23,0x7E,0x07,0x07,0xCD,0x26,0x42,0xE6,
+0x0C,0xB3,0xE1,0xD1,0xC1,0xC9,0x04,0x05,0xC8,0xC5,0x0F,0x0F,0x10,0xFC,0xC1,0xC9,
+0x21,0x43,0x42,0xFD,0xE5,0xD1,0x01,0x8B,0x00,0xED,0xB0,0x01,0x00,0x40,0xCD,0xF6,
+0x41,0xFD,0xE9,0xF5,0xFD,0xE5,0xD1,0x21,0x15,0x00,0x19,0xE5,0x21,0x7B,0x00,0x19,
+0xDD,0x21,0x37,0x00,0xDD,0x19,0xDD,0xE9,0xFE,0xFF,0x20,0x16,0xFD,0xE5,0xD1,0x21,
+0x27,0x00,0x19,0xE5,0x21,0x83,0x00,0x19,0xDD,0xE9,0x3A,0xF6,0x7F,0xF6,0x01,0x32,
+0xF6,0x7F,0xF1,0x21,0x00,0x40,0xCD,0x24,0x00,0xC9,0xEB,0x21,0xC1,0xFC,0x0E,0x00,
+0x06,0x04,0xC5,0xE5,0x7E,0xE6,0x80,0xB1,0x4F,0x06,0x01,0x07,0x30,0x02,0x06,0x04,
+0xC5,0xD5,0x79,0x26,0x40,0xCD,0x24,0x00,0xD1,0xD5,0x21,0x18,0x40,0x06,0x08,0x1A,
+0x13,0xBE,0x23,0x20,0x02,0x10,0xF8,0xD1,0xC1,0x28,0x0F,0x79,0xC6,0x04,0x4F,0x10,
+0xDF,0xE1,0xC1,0x23,0x0C,0x10,0xCB,0x3E,0xFF,0xC9,0x79,0xE1,0xC1,0xC9,0x41,0x50,
+0x52,0x4C,0x4F,0x50,0x4C,0x4C,0x50,0x41,0x43,0x32,0x4F,0x50,0x4C,0x4C,0xF3,0xE5,
+0xF5,0x01,0x00,0x40,0xCD,0xDC,0x41,0x7E,0x23,0x66,0xE6,0xFE,0x6F,0xE5,0xFD,0xE1,
+0x11,0x3D,0x00,0x19,0xE5,0xDD,0xE1,0xF1,0xB7,0x20,0x01,0x3D,0xFD,0x77,0x3A,0xE1,
+0x7E,0xFE,0x12,0xC2,0x06,0x43,0x3E,0x0E,0x1E,0x00,0xCD,0x50,0x41,0x06,0x09,0xFD,
+0x36,0x39,0x00,0xC3,0x0C,0x43,0x06,0x07,0xFD,0x36,0x39,0xFF,0xFD,0x36,0x3B,0x00,
+0xE5,0x5E,0x23,0x56,0x23,0x7A,0xB3,0xC2,0x25,0x43,0xDD,0x36,0x00,0x00,0xDD,0x36,
+0x01,0x00,0xC3,0x37,0x43,0xE3,0xEB,0x19,0xDD,0x75,0x00,0xDD,0x74,0x01,0xDD,0x36,
+0x0A,0x01,0xEB,0xE3,0xFD,0x34,0x3B,0x11,0x0B,0x00,0xDD,0x19,0x10,0xD3,0xE1,0xCD,
+0x44,0x43,0xFB,0xC9,0xFD,0xE5,0xDD,0xE1,0x11,0x3D,0x00,0xDD,0x19,0x06,0x09,0xFD,
+0x7E,0x39,0xB7,0xCA,0x74,0x43,0xDD,0x6E,0x00,0xDD,0x66,0x01,0xDD,0x75,0x02,0xDD,
+0x74,0x03,0xDD,0x36,0x04,0x01,0xDD,0x36,0x05,0x00,0xCD,0xB5,0x43,0x11,0x0B,0x00,
+0xDD,0x19,0x06,0x06,0xDD,0x6E,0x00,0xDD,0x66,0x01,0xDD,0x75,0x02,0xDD,0x74,0x03,
+0xDD,0x36,0x04,0x01,0xDD,0x36,0x05,0x00,0xDD,0x36,0x06,0x00,0xDD,0x36,0x07,0x00,
+0xDD,0x36,0x09,0x00,0xDD,0x36,0x08,0x08,0x3E,0x1F,0x80,0xCD,0x6C,0x41,0xE6,0xCF,
+0x5F,0x3E,0x1F,0x80,0xCD,0x50,0x41,0x11,0x0B,0x00,0xDD,0x19,0x10,0xC6,0xFD,0x7E,
+0x3B,0xFD,0x77,0x3C,0xC9,0x21,0xC5,0x43,0x7E,0xFE,0xFF,0xC8,0x23,0x5E,0x23,0xCD,
+0x50,0x41,0xC3,0xB8,0x43,0x0E,0x20,0x16,0x20,0x17,0x50,0x18,0xC0,0x26,0x05,0x27,
+0x05,0x28,0x01,0x36,0x03,0x37,0x33,0x38,0x33,0xFF,0xF3,0x01,0x00,0x40,0xCD,0xDC,
+0x41,0x7E,0x23,0x66,0xE6,0xFE,0x6F,0xE5,0xFD,0xE1,0x11,0x3D,0x00,0x19,0xE5,0xDD,
+0xE1,0x06,0x09,0xFD,0x7E,0x39,0xB7,0xCA,0x10,0x44,0x3E,0x0E,0x1E,0x20,0xCD,0x50,
+0x41,0xDD,0x36,0x02,0x00,0xDD,0x36,0x03,0x00,0x11,0x0B,0x00,0xDD,0x19,0x06,0x06,
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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC3,0x03,0x50,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x01,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
diff --git a/MCUME_pico2/picomsx/bios/italic.h b/MCUME_pico2/picomsx/bios/italic.h
new file mode 100644
index 0000000..906acbe
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/italic.h
@@ -0,0 +1,130 @@
+static const uint8_t ITALIC[2048] = {
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0xA5,0x81,0xA5,0x99,0x42,0x3C,
+0x3C,0x7E,0xDB,0xFF,0xFF,0xDB,0x66,0x3C,0x6C,0xFE,0xFE,0xFE,0x7C,0x38,0x10,0x00,
+0x10,0x38,0x7C,0xFE,0x7C,0x38,0x10,0x00,0x10,0x38,0x54,0xFE,0x54,0x10,0x38,0x00,
+0xFF,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,
+0x00,0x00,0x00,0x70,0x70,0x00,0x00,0x00,0x38,0x44,0x82,0x82,0x82,0x44,0x38,0x00,
+0x00,0x08,0x08,0x90,0x50,0x20,0x20,0x00,0x04,0x18,0x24,0x5C,0xFC,0x9C,0x44,0x38,
+0x78,0xB4,0x30,0xCC,0xB4,0xB4,0x84,0xFC,0x0C,0x0C,0x2C,0x6C,0xFC,0xF8,0x60,0x20,
+0xC0,0xF0,0xFC,0xF0,0x98,0x0C,0x00,0x00,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,
+0xFC,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xFC,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
+0x04,0x04,0x04,0x04,0x04,0x04,0x04,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,
+0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xFC,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
+0x00,0x00,0xFC,0x80,0x9C,0x90,0x90,0x90,0x00,0x00,0xFC,0x00,0xFC,0x00,0x00,0x00,
+0x00,0x00,0xFC,0x04,0xE4,0x24,0x24,0x24,0x24,0x24,0x24,0x24,0x24,0x24,0x24,0x24,
+0x24,0x24,0x24,0xE4,0x04,0xFC,0x00,0x00,0x00,0x00,0x00,0xFC,0x00,0xFC,0x00,0x00,
+0x90,0x90,0x90,0x9C,0x80,0xFC,0x00,0x00,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x20,0x20,0x00,0x00,0x20,0x00,
+0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00,
+0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00,0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00,
+0x40,0xA0,0x40,0xA8,0x90,0x98,0x60,0x00,0x10,0x20,0x40,0x00,0x00,0x00,0x00,0x00,
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+0x40,0x40,0x40,0xF0,0x88,0x88,0x88,0x00,0x30,0x00,0x30,0x10,0x20,0x20,0x70,0x00,
+0x18,0x00,0x18,0x08,0x10,0x10,0x90,0x60,0x20,0x20,0x28,0x30,0x60,0x50,0x48,0x00,
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+0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00,0xC0,0x20,0x20,0x10,0x20,0x20,0xC0,0x00,
+0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x50,0xF8,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xF0,0xF0,0xF0,0xF0,0x0F,0x0F,0x0F,0x0F,
+0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x3C,0x3C,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,
+0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x0F,0x0F,0x0F,0x0F,0xF0,0xF0,0xF0,0xF0,
+0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,
+0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x11,0x22,0x44,0x88,0x11,0x22,0x44,0x88,
+0x88,0x44,0x22,0x11,0x88,0x44,0x22,0x11,0xFE,0x7C,0x38,0x10,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x10,0x38,0x7C,0xFE,0x80,0xC0,0xE0,0xF0,0xE0,0xC0,0x80,0x00,
+0x01,0x03,0x07,0x0F,0x07,0x03,0x01,0x00,0xFF,0x7E,0x3C,0x18,0x18,0x3C,0x7E,0xFF,
+0x81,0xC3,0xE7,0xFF,0xFF,0xE7,0xC3,0x81,0xF0,0xF0,0xF0,0xF0,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0x33,0x33,0xCC,0xCC,0x33,0x33,0xCC,0xCC,
+0x00,0x20,0x20,0x50,0x50,0x88,0xF8,0x00,0x20,0x20,0x70,0x20,0x70,0x20,0x20,0x00,
+0x00,0x00,0x00,0x50,0x88,0xA8,0x50,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,
+0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,
+0x00,0x00,0x68,0x90,0x90,0x90,0x68,0x00,0x30,0x48,0x48,0x70,0x48,0x48,0x70,0xC0,
+0xF8,0x88,0x80,0x80,0x80,0x80,0x80,0x00,0xF8,0x50,0x50,0x50,0x50,0x50,0x98,0x00,
+0xF8,0x88,0x40,0x20,0x40,0x88,0xF8,0x00,0x00,0x00,0x78,0x90,0x90,0x90,0x60,0x00,
+0x00,0x50,0x50,0x50,0x50,0x68,0x80,0x80,0x00,0x50,0xA0,0x20,0x20,0x20,0x20,0x00,
+0xF8,0x20,0x70,0xA8,0xA8,0x70,0x20,0xF8,0x20,0x50,0x88,0xF8,0x88,0x50,0x20,0x00,
+0x70,0x88,0x88,0x88,0x50,0x50,0xD8,0x00,0x30,0x40,0x40,0x20,0x50,0x50,0x50,0x20,
+0x00,0x00,0x00,0x50,0xA8,0xA8,0x50,0x00,0x08,0x70,0xA8,0xA8,0xA8,0x70,0x80,0x00,
+0x38,0x40,0x80,0xF8,0x80,0x40,0x38,0x00,0x70,0x88,0x88,0x88,0x88,0x88,0x88,0x00,
+0x00,0xF8,0x00,0xF8,0x00,0xF8,0x00,0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0xF8,0x00,
+0xC0,0x30,0x08,0x30,0xC0,0x00,0xF8,0x00,0x18,0x60,0x80,0x60,0x18,0x00,0xF8,0x00,
+0x10,0x28,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0xA0,0x40,
+0x00,0x20,0x00,0xF8,0x00,0x20,0x00,0x00,0x00,0x50,0xA0,0x00,0x50,0xA0,0x00,0x00,
+0x00,0x18,0x24,0x24,0x18,0x00,0x00,0x00,0x00,0x30,0x78,0x78,0x30,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x20,0x20,0x20,0xA0,0x60,0x20,0x00,
+0xA0,0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x40,0xA0,0x20,0x40,0xE0,0x00,0x00,0x00,
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+0x00,0x00,0xF0,0x80,0xF0,0x88,0xF0,0x00,0x00,0x00,0x90,0x90,0x90,0xF8,0x08,0x00,
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+0x00,0x50,0x20,0x00,0x98,0xA8,0xC8,0x00,0x00,0x00,0x90,0xA0,0xC0,0xA0,0x90,0x00,
+0x00,0x00,0x38,0x28,0x28,0x48,0x88,0x00,0x00,0x00,0x88,0xD8,0xA8,0x88,0x88,0x00,
+0x00,0x00,0x88,0x88,0xF8,0x88,0x88,0x00,0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00,
+0x00,0x00,0x78,0x48,0x48,0x48,0x48,0x00,0x00,0x00,0x78,0x88,0x78,0x28,0x48,0x00,
+0x00,0x00,0xF0,0x88,0xF0,0x80,0x80,0x00,0x00,0x00,0x78,0x80,0x80,0x80,0x78,0x00,
+0x00,0x00,0xF8,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x88,0x50,0x20,0x40,0x80,0x00,
+0x00,0x00,0xA8,0x70,0x20,0x70,0xA8,0x00,0x00,0x00,0xF0,0x48,0x70,0x48,0xF0,0x00,
+0x00,0x00,0x40,0x40,0x70,0x48,0x70,0x00,0x00,0x00,0x88,0x88,0xC8,0xA8,0xC8,0x00,
+0x00,0x00,0xF0,0x08,0x70,0x08,0xF0,0x00,0x00,0x00,0xA8,0xA8,0xA8,0xA8,0xF8,0x00,
+0x00,0x00,0x70,0x88,0x38,0x88,0x70,0x00,0x00,0x00,0xA8,0xA8,0xA8,0xF8,0x08,0x00,
+0x00,0x00,0x48,0x48,0x78,0x08,0x08,0x00,0x00,0x00,0xC0,0x40,0x70,0x48,0x70,0x00,
+0x90,0xA8,0xA8,0xE8,0xA8,0xA8,0x90,0x00,0x10,0x28,0x44,0x44,0xF8,0x88,0x88,0x00,
+0x7C,0x44,0x40,0x70,0x88,0x88,0xF0,0x00,0x48,0x48,0x48,0x48,0x90,0xF8,0x08,0x00,
+0x1C,0x14,0x14,0x24,0x48,0xF8,0x88,0x00,0x7C,0x40,0x40,0x78,0x80,0x80,0xF8,0x00,
+0x10,0x38,0x54,0xA8,0xA8,0x70,0x20,0x00,0x7C,0x44,0x44,0x80,0x80,0x80,0x80,0x00,
+0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00,0x44,0x4C,0x54,0x64,0xC8,0x88,0x88,0x00,
+0x28,0x10,0x44,0x5C,0x64,0x88,0x88,0x00,0x44,0x48,0x50,0x60,0xA0,0x90,0x88,0x00,
+0x0C,0x14,0x24,0x48,0x48,0x48,0x88,0x00,0x44,0x6C,0x54,0x44,0x88,0x88,0x88,0x00,
+0x44,0x44,0x44,0xF8,0x88,0x88,0x88,0x00,0x38,0x44,0x44,0x88,0x88,0x88,0x70,0x00,
+0x7C,0x44,0x44,0x44,0x88,0x88,0x88,0x00,0x3C,0x44,0x44,0x3C,0x28,0x48,0x88,0x00,
+0x78,0x44,0x44,0x78,0x80,0x80,0x80,0x00,0x38,0x44,0x40,0x80,0x80,0x88,0x70,0x00,
+0x7C,0x10,0x10,0x10,0x20,0x20,0x20,0x00,0x44,0x44,0x44,0x38,0x08,0x08,0xF0,0x00,
+0xA8,0xA8,0x70,0x20,0x70,0xA8,0xA8,0x00,0x78,0x44,0x44,0x78,0x88,0x88,0xF0,0x00,
+0x40,0x40,0x40,0x70,0x88,0x88,0xF0,0x00,0x44,0x44,0x44,0x64,0xA8,0xA8,0xC8,0x00,
+0x78,0x04,0x04,0x38,0x08,0x08,0xF0,0x00,0x54,0x54,0x54,0xA8,0xA8,0xA8,0xF8,0x00,
+0x38,0x44,0x04,0x3C,0x08,0x88,0x70,0x00,0x54,0x54,0x54,0xA8,0xA8,0xF8,0x08,0x00,
+0x44,0x44,0x44,0x88,0x78,0x08,0x08,0x00,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,
+};
diff --git a/MCUME_pico2/picomsx/bios/kanji.h b/MCUME_pico2/picomsx/bios/kanji.h
new file mode 100644
index 0000000..c6156c5
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/kanji.h
@@ -0,0 +1,8194 @@
+static const uint8_t KANJI[131072] = {
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x38,0x38,0x38,0x38,0x38,0x38,0x10,0x00,0x00,0x00,0x00,0x00,0x38,0x38,0x38,
+0x10,0x10,0x10,0x00,0x00,0x10,0x38,0x10,0x38,0x10,0x10,0x10,0x00,0x10,0x38,0x10,
+0x44,0xEE,0x44,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xD8,0xD8,0x48,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x90,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x12,0x12,0x12,0x7F,0x24,0x24,0x24,0x00,0x00,0x00,0x00,0x00,0x24,0x24,0x24,
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+};
diff --git a/MCUME_pico2/picomsx/bios/msx.h b/MCUME_pico2/picomsx/bios/msx.h
new file mode 100644
index 0000000..805a35f
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/msx.h
@@ -0,0 +1,2050 @@
+static const uint8_t MSX[32768] = {
+0xF3,0xC3,0xD7,0x02,0xBF,0x1B,0x98,0x98,0xC3,0x83,0x26,0x00,0xC3,0xB6,0x01,0x00,
+0xC3,0x86,0x26,0x00,0xC3,0xD1,0x01,0x00,0xC3,0x45,0x1B,0x00,0xC3,0x17,0x02,0x00,
+0xC3,0x6A,0x14,0x00,0xC3,0x5E,0x02,0x00,0xC3,0x89,0x26,0x91,0x11,0x00,0x00,0x00,
+0xC3,0x05,0x02,0x00,0x00,0x00,0x00,0x00,0xC3,0x3C,0x0C,0xC3,0x9D,0x04,0xC3,0x9D,
+0x13,0xC3,0x77,0x05,0xC3,0x70,0x05,0xC3,0x7F,0x05,0xC3,0xD7,0x07,0xC3,0xCD,0x07,
+0xC3,0xEC,0x07,0xC3,0xDF,0x07,0xC3,0x15,0x08,0xC3,0x0F,0x07,0xC3,0x44,0x07,0xC3,
+0x4F,0x08,0xC3,0xF7,0x07,0x00,0xC3,0x98,0x13,0xC3,0xA8,0x06,0xC3,0x0E,0x05,0xC3,
+0x38,0x05,0xC3,0xD2,0x05,0xC3,0x1F,0x06,0xC3,0x94,0x05,0xC3,0xB4,0x05,0xC3,0x02,
+0x06,0xC3,0x59,0x06,0xC3,0xE4,0x06,0xC3,0xF9,0x06,0xC3,0x04,0x07,0xC3,0x10,0x15,
+0xC3,0xBD,0x04,0xC3,0x02,0x11,0xC3,0x0E,0x11,0xC3,0xC4,0x11,0xC3,0x6A,0x0D,0xC3,
+0xCB,0x10,0xC3,0xBC,0x08,0xC3,0x5D,0x08,0xC3,0x84,0x08,0xC3,0x9D,0x08,0xC3,0xBF,
+0x23,0xC3,0xD5,0x23,0xC3,0xCC,0x23,0xC3,0x6F,0x04,0xC3,0xFB,0x03,0xC3,0xF9,0x10,
+0xC3,0x13,0x11,0xC3,0x48,0x08,0xC3,0x8E,0x08,0xC3,0x26,0x0B,0xC3,0x15,0x0B,0xC3,
+0x2B,0x0B,0xC3,0x3B,0x08,0xC3,0xEE,0x11,0xC3,0x53,0x12,0xC3,0xAC,0x12,0xC3,0x73,
+0x12,0xC3,0x63,0x1A,0xC3,0xBC,0x1A,0xC3,0xE9,0x19,0xC3,0xF1,0x19,0xC3,0x19,0x1A,
+0xC3,0xDD,0x19,0xC3,0x84,0x13,0xC3,0xEB,0x14,0xC3,0x92,0x14,0xC3,0xC5,0x16,0xC3,
+0xEE,0x16,0xC3,0x5D,0x17,0xC3,0x3C,0x17,0xC3,0x2A,0x17,0xC3,0x0A,0x17,0xC3,0x99,
+0x15,0xC3,0xDF,0x15,0xC3,0x39,0x16,0xC3,0x40,0x16,0xC3,0x76,0x16,0xC3,0x47,0x16,
+0xC3,0x7E,0x16,0xC3,0x09,0x18,0xC3,0xC7,0x18,0xC3,0xCF,0x18,0xC3,0xE4,0x18,0xC3,
+0x7A,0x19,0xC3,0x3D,0x0F,0xC3,0x7A,0x0F,0xC3,0x4C,0x14,0xC3,0x4F,0x14,0xC3,0x49,
+0x14,0xC3,0x52,0x14,0xC3,0x8A,0x14,0xC3,0x8E,0x14,0xC3,0x5F,0x14,0xC3,0x63,0x1B,
+0xC3,0x70,0x14,0xC3,0x74,0x14,0xC3,0x68,0x04,0xC3,0xFF,0x01,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xCD,0x7E,0x02,0xFA,0xC6,0x01,0xDB,0xA8,0x57,0xA1,
+0xB0,0xCD,0x80,0xF3,0x7B,0xC9,0xE5,0xCD,0xA3,0x02,0xE3,0xC5,0xCD,0xB6,0x01,0x18,
+0x1B,0xD5,0xCD,0x7E,0x02,0xFA,0xE1,0x01,0xD1,0xDB,0xA8,0x57,0xA1,0xB0,0xC3,0x85,
+0xF3,0xE3,0xE5,0xCD,0xA3,0x02,0xD1,0xE3,0xC5,0xCD,0xD1,0x01,0xC1,0xE3,0xF5,0x78,
+0xE6,0x3F,0xB1,0xD3,0xA8,0x7D,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0xF1,0xE1,0xC9,0xFD,
+0x2A,0xC0,0xFC,0x18,0x12,0xE3,0xF5,0xD5,0x7E,0xF5,0xFD,0xE1,0x23,0x5E,0x23,0x56,
+0x23,0xD5,0xDD,0xE1,0xD1,0xF1,0xE3,0xD9,0x08,0xFD,0xE5,0xF1,0xDD,0xE5,0xE1,0xCD,
+0x7E,0x02,0xFA,0x2E,0x02,0xDB,0xA8,0xF5,0xA1,0xB0,0xD9,0xC3,0x8C,0xF3,0xCD,0xA3,
+0x02,0xF5,0xFD,0xE1,0xE5,0xC5,0x4F,0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,
+0x77,0xE5,0x08,0xD9,0xCD,0x17,0x02,0xD9,0x08,0xE1,0xC1,0xD1,0x78,0xE6,0x3F,0xB1,
+0xF3,0xD3,0xA8,0x7B,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x73,0x08,0xD9,0xC9,0xCD,0x7E,
+0x02,0xFA,0x6B,0x02,0xDB,0xA8,0xA1,0xB0,0xD3,0xA8,0xC9,0xE5,0xCD,0xA3,0x02,0x4F,
+0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE1,0x79,0x18,0xE0,0xF3,0xF5,
+0x7C,0x07,0x07,0xE6,0x03,0x5F,0x3E,0xC0,0x07,0x07,0x1D,0xF2,0x88,0x02,0x5F,0x2F,
+0x4F,0xF1,0xF5,0xE6,0x03,0x3C,0x47,0x3E,0xAB,0xC6,0x55,0x10,0xFC,0x57,0xA3,0x47,
+0xF1,0xA7,0xC9,0xF5,0x7A,0xE6,0xC0,0x4F,0xF1,0xF5,0x57,0xDB,0xA8,0x47,0xE6,0x3F,
+0xB1,0xD3,0xA8,0x7A,0x0F,0x0F,0xE6,0x03,0x57,0x3E,0xAB,0xC6,0x55,0x15,0xF2,0xBB,
+0x02,0xA3,0x57,0x7B,0x2F,0x67,0x3A,0xFF,0xFF,0x2F,0x6F,0xA4,0xB2,0x32,0xFF,0xFF,
+0x78,0xD3,0xA8,0xF1,0xE6,0x03,0xC9,0x3E,0x82,0xD3,0xAB,0xAF,0xD3,0xA8,0x3E,0x50,
+0xD3,0xAA,0x11,0xFF,0xFF,0xAF,0x4F,0xD3,0xA8,0xCB,0x21,0x06,0x00,0x21,0xFF,0xFF,
+0x36,0xF0,0x7E,0xD6,0x0F,0x20,0x0B,0x77,0x7E,0x3C,0x20,0x06,0x04,0xCB,0xC1,0x32,
+0xFF,0xFF,0x21,0x00,0xBF,0x7E,0x2F,0x77,0xBE,0x2F,0x77,0x20,0x07,0x00,0x00,0x00,
+0x25,0xFA,0x05,0x03,0x2E,0x00,0x24,0x7D,0x93,0x7C,0x9A,0x30,0x0A,0xEB,0x3A,0xFF,
+0xFF,0x2F,0x6F,0xDB,0xA8,0x67,0xF9,0x78,0xA7,0x28,0x0A,0x3A,0xFF,0xFF,0x2F,0xC6,
+0x10,0xFE,0x40,0x38,0xCA,0xDB,0xA8,0xC6,0x50,0x30,0xAC,0x21,0x00,0x00,0x39,0x7C,
+0xD3,0xA8,0x7D,0x32,0xFF,0xFF,0x79,0x07,0x07,0x07,0x07,0x4F,0x11,0xFF,0xFF,0xDB,
+0xA8,0xE6,0x3F,0xD3,0xA8,0x06,0x00,0xCB,0x01,0x30,0x0A,0x04,0x3A,0xFF,0xFF,0x2F,
+0xE6,0x3F,0x32,0xFF,0xFF,0x21,0x00,0xFE,0x7E,0x2F,0x77,0xBE,0x2F,0x77,0x20,0x09,
+0x00,0x00,0x00,0x25,0x7C,0xFE,0xC0,0x30,0xEF,0x2E,0x00,0x24,0x7D,0x93,0x7C,0x9A,
+0x30,0x0A,0xEB,0x3A,0xFF,0xFF,0x2F,0x6F,0xDB,0xA8,0x67,0xF9,0x78,0xA7,0x28,0x08,
+0x3A,0xFF,0xFF,0x2F,0xC6,0x40,0x30,0xCA,0xDB,0xA8,0xC6,0x40,0x30,0xB5,0x21,0x00,
+0x00,0x39,0x7C,0xD3,0xA8,0x7D,0x32,0xFF,0xFF,0x79,0x01,0x49,0x0C,0x11,0x81,0xF3,
+0x21,0x80,0xF3,0x36,0x00,0xED,0xB0,0x4F,0x06,0x04,0x21,0xC4,0xFC,0xCB,0x19,0x9F,
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+0xFF,0xCB,0x18,0xCD,0x1A,0x7E,0xC6,0xFF,0xCB,0x18,0x11,0xF8,0xFF,0x19,0xE3,0x70,
+0x23,0xE3,0x11,0xFE,0x3F,0x19,0x7C,0xFE,0xC0,0x38,0xBC,0xE1,0x23,0x79,0xA7,0x11,
+0x0C,0x00,0xF2,0xE0,0x7D,0xC6,0x04,0x4F,0xFE,0x90,0x38,0xA6,0xE6,0x03,0x4F,0x3E,
+0x19,0xD1,0x13,0x0C,0x79,0xFE,0x04,0x38,0x95,0x21,0xC9,0xFC,0x06,0x40,0x7E,0x87,
+0x38,0x04,0x23,0x10,0xF9,0xC9,0xCD,0x2A,0x7E,0xCD,0x24,0x00,0x2A,0xC2,0xF6,0x11,
+0x00,0xC0,0xE7,0x30,0x04,0xEB,0x22,0xC2,0xF6,0x2A,0x08,0x80,0x23,0x22,0x76,0xF6,
+0x7C,0x32,0xB1,0xFB,0xCD,0x9A,0x62,0xC3,0x01,0x46,0xCD,0x1E,0x7E,0x5A,0x79,0xC5,
+0xD5,0xCD,0x0C,0x00,0xD1,0xC1,0x57,0xB3,0x23,0xC9,0x3E,0x40,0x90,0x47,0x26,0x00,
+0x1F,0xCB,0x1C,0x1F,0xCB,0x1C,0x1F,0x1F,0xE6,0x03,0x4F,0x78,0x06,0x00,0xE5,0x21,
+0xC1,0xFC,0x09,0xE6,0x0C,0xB1,0x4F,0x7E,0xE1,0xB1,0xC9,0xCF,0xB7,0xCF,0xEF,0xCD,
+0x1C,0x52,0xC2,0x55,0x40,0xFE,0x10,0xD2,0x5A,0x47,0x22,0xA7,0xF6,0xF5,0xCD,0x1C,
+0x6C,0xF1,0xCD,0x6B,0x7E,0xCD,0xA7,0x62,0xC3,0x01,0x46,0xF5,0x2A,0x4A,0xFC,0x11,
+0xF5,0xFE,0x19,0x3D,0xF2,0x72,0x7E,0xEB,0x2A,0x74,0xF6,0x44,0x4D,0x2A,0x72,0xF6,
+0x7D,0x91,0x6F,0x7C,0x98,0x67,0xF1,0xE5,0xF5,0x01,0x8C,0x00,0x09,0x44,0x4D,0x2A,
+0xC2,0xF6,0x09,0xE7,0xD2,0x75,0x62,0xF1,0x32,0x5F,0xF8,0x6B,0x62,0x22,0x60,0xF8,
+0x2B,0x2B,0x22,0x72,0xF6,0xC1,0x7D,0x91,0x6F,0x7C,0x98,0x67,0x22,0x74,0xF6,0x2B,
+0x2B,0xC1,0xF9,0xC5,0x3A,0x5F,0xF8,0x6F,0x2C,0x26,0x00,0x29,0x19,0xEB,0xD5,0x01,
+0x09,0x01,0x73,0x23,0x72,0x23,0xEB,0x36,0x00,0x09,0xEB,0x3D,0xF2,0xC2,0x7E,0xE1,
+0x01,0x09,0x00,0x09,0x22,0x62,0xF8,0xC9,0x4D,0x53,0x58,0x20,0x20,0x73,0x79,0x73,
+0x74,0x65,0x6D,0x00,0x76,0x65,0x72,0x73,0x69,0x6F,0x6E,0x20,0x31,0x2E,0x30,0x0D,
+0x0A,0x00,0x4D,0x53,0x58,0x20,0x42,0x41,0x53,0x49,0x43,0x20,0x00,0x43,0x6F,0x70,
+0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x31,0x39,0x38,0x33,0x20,0x62,0x79,0x20,0x4D,
+0x69,0x63,0x72,0x6F,0x73,0x6F,0x66,0x74,0x0D,0x0A,0x00,0x20,0x42,0x79,0x74,0x65,
+0x73,0x20,0x66,0x72,0x65,0x65,0x00,0xD3,0xA8,0x5E,0x18,0x03,0xD3,0xA8,0x73,0x7A,
+0xD3,0xA8,0xC9,0xD3,0xA8,0x08,0xCD,0x98,0xF3,0x08,0xF1,0xD3,0xA8,0x08,0xC9,0xDD,
+0xE9,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,
+0x47,0x5A,0x47,0x5A,0x47,0x25,0x1D,0x1D,0x18,0x0E,0x00,0x00,0x00,0x00,0x00,0x08,
+0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x20,0x00,0x00,0x00,0x1B,0x00,0x38,0x00,0x18,
+0x00,0x20,0x00,0x00,0x00,0x1B,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x1B,
+0x00,0x38,0x01,0x01,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,
+0x0F,0x04,0x04,0xC3,0x00,0x00,0xC3,0x00,0x00,0x0F,0x59,0xF9,0xFF,0x01,0x32,0xF0,
+0xFB,0xF0,0xFB,0x53,0x5C,0x26,0x2D,0x0F,0x25,0x2D,0x0E,0x16,0x1F,0x53,0x5C,0x26,
+0x2D,0x0F,0x00,0x01,0x00,0x01,0x3A,0x11,0x89,0xFD,0xA7,0xC0,0x04,0xC9,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
diff --git a/MCUME_pico2/picomsx/bios/msx2.h b/MCUME_pico2/picomsx/bios/msx2.h
new file mode 100644
index 0000000..b2284ce
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/msx2.h
@@ -0,0 +1,2050 @@
+static const uint8_t MSX2[32768] = {
+0xF3,0xC3,0x16,0x04,0xBF,0x1B,0x98,0x98,0xC3,0x83,0x26,0x00,0xC3,0xF5,0x01,0x00,
+0xC3,0x86,0x26,0x00,0xC3,0x25,0x02,0x00,0xC3,0x45,0x1B,0x00,0xC3,0x17,0x02,0x00,
+0xC3,0x04,0x0C,0x00,0xC3,0x33,0x03,0x00,0xC3,0x89,0x26,0x91,0x11,0x01,0x00,0x00,
+0xC3,0xC6,0x02,0x00,0x00,0x00,0x00,0x00,0xC3,0x3C,0x0C,0xC3,0x92,0x05,0xC3,0xA0,
+0x13,0xC3,0x0A,0x06,0xC3,0x03,0x06,0xC3,0x12,0x06,0xC3,0xE1,0x07,0xC3,0xD7,0x07,
+0xC3,0x08,0x08,0xC3,0xF4,0x07,0xC3,0x3B,0x08,0xC3,0x3D,0x07,0xC3,0x80,0x07,0xC3,
+0xB1,0x08,0xC3,0x1A,0x08,0x00,0xC3,0x9B,0x13,0xC3,0x7F,0x06,0xC3,0x3E,0x06,0xC3,
+0x47,0x06,0xC3,0x4F,0x06,0xC3,0x57,0x06,0xC3,0x5F,0x06,0xC3,0x67,0x06,0xC3,0x6F,
+0x06,0xC3,0x77,0x06,0xC3,0xEC,0x06,0xC3,0x01,0x07,0xC3,0x0C,0x07,0xC3,0x0E,0x15,
+0xC3,0xB2,0x05,0xC3,0x02,0x11,0xC3,0x0E,0x11,0xC3,0xBA,0x11,0xC3,0x6A,0x0D,0xC3,
+0xCB,0x10,0xC3,0x19,0x09,0xC3,0xBA,0x08,0xC3,0xE1,0x08,0xC3,0xFA,0x08,0xC3,0xBF,
+0x23,0xC3,0xD5,0x23,0xC3,0xCC,0x23,0xC3,0x64,0x05,0xC3,0xF0,0x04,0xC3,0xF9,0x10,
+0xC3,0x13,0x11,0xC3,0x97,0x08,0xC3,0xEB,0x08,0xC3,0x3A,0x0B,0xC3,0x29,0x0B,0xC3,
+0x3F,0x0B,0xC3,0x9E,0x08,0xC3,0xE4,0x11,0xC3,0x49,0x12,0xC3,0xA2,0x12,0xC3,0x69,
+0x12,0xC3,0x63,0x1A,0xC3,0xBC,0x1A,0xC3,0xE9,0x19,0xC3,0xF1,0x19,0xC3,0x19,0x1A,
+0xC3,0xDD,0x19,0xC3,0x87,0x13,0xC3,0xE9,0x14,0xC3,0x90,0x14,0xC3,0x56,0x17,0xC3,
+0x90,0x17,0xC3,0x1F,0x18,0xC3,0xF6,0x17,0xC3,0xDC,0x17,0xC3,0xB4,0x17,0xC3,0xA5,
+0x15,0xC3,0x04,0x16,0xC3,0x51,0x16,0xC3,0x58,0x16,0xC3,0x92,0x16,0xC3,0x5F,0x16,
+0xC3,0xC3,0x16,0xC3,0x43,0x18,0xC3,0x01,0x19,0xC3,0x09,0x19,0xC3,0x1E,0x19,0xC3,
+0x94,0x19,0xC3,0x3D,0x0F,0xC3,0x7A,0x0F,0xC3,0x0E,0x14,0xC3,0x11,0x14,0xC3,0x0B,
+0x14,0xC3,0xEC,0x0B,0xC3,0x14,0x14,0xC3,0x18,0x14,0xC3,0xF9,0x0B,0xC3,0x63,0x1B,
+0xC3,0x0A,0x0C,0xC3,0x0E,0x0C,0xC3,0x5D,0x05,0xC3,0xBF,0x02,0xC3,0x95,0x02,0xC3,
+0x9B,0x02,0xC3,0xAC,0x03,0xC3,0xA9,0x06,0xC3,0x05,0x0B,0xC3,0x38,0x08,0xC3,0xC5,
+0x06,0xC3,0xB3,0x06,0xC3,0xE9,0x07,0xC3,0x69,0x07,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xF1,0x16,0xFC,0xE6,0x0C,0x0F,0x0F,0x67,0xDB,0xA8,
+0x47,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0xB4,0x5F,0x32,0xFF,0xFF,
+0x78,0xA2,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0xC5,0xD9,0x08,0xCD,0x98,0xF3,0xF3,0x08,
+0xD9,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,
+0xC5,0xFC,0x08,0xD9,0xC9,0xCD,0x53,0x03,0xFA,0x05,0x02,0xDB,0xA8,0x57,0xA1,0xB0,
+0xCD,0x80,0xF3,0x7B,0xC9,0xCD,0x8C,0x02,0x20,0x10,0xE5,0xCD,0x55,0x02,0xE3,0xCD,
+0xBE,0x7F,0x18,0x30,0x00,0x00,0x00,0xC3,0xD8,0x02,0xE5,0xCD,0x78,0x03,0xE3,0xC5,
+0xCD,0xF5,0x01,0x18,0x54,0xD5,0xCD,0x53,0x03,0xFA,0x35,0x02,0xD1,0xDB,0xA8,0x57,
+0xA1,0xB0,0xC3,0x85,0xF3,0xCD,0x8C,0x02,0xC2,0x6E,0x02,0xD1,0xE5,0xCD,0x55,0x02,
+0xE3,0xCD,0xC4,0x7F,0xE3,0xF5,0x7D,0xE6,0x3F,0xD3,0xA8,0x7C,0x32,0xFF,0xFF,0x7D,
+0xD3,0xA8,0xF1,0xE1,0xC9,0xF5,0xDB,0xA8,0x6F,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,
+0x2F,0x67,0xE6,0xF3,0x32,0xFF,0xFF,0x7D,0xE6,0xF3,0xD3,0xA8,0xF1,0xC9,0xE3,0xE5,
+0xCD,0x78,0x03,0xD1,0xE3,0xC5,0xCD,0x25,0x02,0xC1,0xE3,0xF5,0x78,0xE6,0x3F,0xB1,
+0xD3,0xA8,0x7D,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0xF1,0xE1,0xC9,0x14,0x15,0xC0,0x47,
+0x7B,0xFE,0x03,0x78,0xC9,0xCD,0x9B,0x02,0xDD,0xE1,0xC9,0xD9,0x08,0xE5,0xD5,0xC5,
+0xF5,0xED,0x57,0xF5,0xD9,0x08,0xFD,0xE5,0xFD,0x2A,0xF7,0xFA,0xCD,0x17,0x02,0xFD,
+0xE1,0x08,0xD9,0xF1,0xE2,0xB8,0x02,0xFB,0xF1,0xC1,0xD1,0xE1,0xD9,0x08,0xC9,0xFD,
+0x2A,0xC0,0xFC,0xC3,0x17,0x02,0xE3,0xF5,0xD5,0x7E,0xF5,0xFD,0xE1,0x23,0x5E,0x23,
+0x56,0x23,0xD5,0xDD,0xE1,0xD1,0xF1,0xE3,0xD9,0x08,0xFD,0xE5,0xF1,0xDD,0xE5,0xE1,
+0xCD,0x53,0x03,0xFA,0xEF,0x02,0xDB,0xA8,0xF5,0xA1,0xB0,0xD9,0xC3,0x8C,0xF3,0xF5,
+0xE6,0x03,0x20,0x06,0x7C,0xE6,0xC0,0xCA,0xB6,0x01,0xF1,0xCD,0x78,0x03,0xF5,0xFD,
+0xE1,0xE5,0xC5,0x4F,0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE5,0x08,
+0xD9,0xCD,0x17,0x02,0xD9,0x08,0xE1,0xC1,0xD1,0xED,0x57,0xF5,0x78,0xE6,0x3F,0xB1,
+0xF3,0xD3,0xA8,0x7B,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x73,0xF1,0xE2,0x30,0x03,0xFB,
+0x08,0xD9,0xC9,0xCD,0x53,0x03,0xFA,0x40,0x03,0xDB,0xA8,0xA1,0xB0,0xD3,0xA8,0xC9,
+0xE5,0xCD,0x78,0x03,0x4F,0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE1,
+0x79,0x18,0xE0,0xF3,0xF5,0x7C,0x07,0x07,0xE6,0x03,0x5F,0x3E,0xC0,0x07,0x07,0x1D,
+0xF2,0x5D,0x03,0x5F,0x2F,0x4F,0xF1,0xF5,0xE6,0x03,0x3C,0x47,0x3E,0xAB,0xC6,0x55,
+0x10,0xFC,0x57,0xA3,0x47,0xF1,0xA7,0xC9,0xF5,0x7A,0xE6,0xC0,0x4F,0xF1,0xF5,0x57,
+0xDB,0xA8,0x47,0xE6,0x3F,0xB1,0xD3,0xA8,0x7A,0x0F,0x0F,0xE6,0x03,0x57,0x3E,0xAB,
+0xC6,0x55,0x15,0xF2,0x90,0x03,0xA3,0x57,0x7B,0x2F,0x67,0x3A,0xFF,0xFF,0x2F,0x6F,
+0xA4,0xB2,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0xF1,0xE6,0x03,0xC9,0xF3,0x0E,0x00,0x11,
+0xC1,0xFC,0x21,0xC9,0xFC,0x1A,0xB1,0x4F,0xD5,0xE5,0x21,0x00,0x00,0xCD,0x1A,0x7E,
+0xE5,0x21,0x43,0x44,0xE7,0xE1,0x06,0x00,0x20,0x25,0xCD,0x1A,0x7E,0xE5,0xC5,0xD5,
+0xDD,0xE1,0x79,0xF5,0xFD,0xE1,0xC4,0x17,0x02,0xC1,0xE1,0xCD,0x1A,0x7E,0xC6,0xFF,
+0xCB,0x18,0xCD,0x1A,0x7E,0xC6,0xFF,0xCB,0x18,0xCB,0x38,0x11,0xF8,0xFF,0x19,0xE3,
+0x70,0xE3,0xE1,0x23,0x23,0x23,0x23,0x79,0xA7,0x11,0x0C,0x00,0xF2,0x0A,0x04,0xC6,
+0x04,0x4F,0xFE,0x90,0x38,0xB3,0xE6,0x03,0x4F,0x3E,0x19,0xD1,0x13,0x0C,0x79,0xFE,
+0x04,0x38,0xA2,0xC3,0x75,0x7D,0xAF,0xD3,0xFF,0x3C,0xD3,0xFE,0x3C,0xD3,0xFD,0x3C,
+0xD3,0xFC,0x3E,0x08,0xD3,0xBB,0x3E,0x82,0xD3,0xAB,0xAF,0xD3,0xA8,0xC3,0xD2,0x7B,
+0x00,0x11,0xFF,0xFF,0xAF,0x4F,0xD3,0xA8,0xCB,0x21,0x06,0x00,0x21,0xFF,0xFF,0x36,
+0xF0,0x7E,0xD6,0x0F,0x20,0x0B,0x77,0x7E,0x3C,0x20,0x06,0x04,0xCB,0xC1,0x32,0xFF,
+0xFF,0x21,0x00,0xBF,0x7E,0x2F,0x77,0xBE,0x2F,0x77,0x20,0x07,0x2C,0x20,0xF5,0x25,
+0xFA,0x54,0x04,0x2E,0x00,0x24,0x7D,0x93,0x7C,0x9A,0x30,0x0A,0xEB,0x3A,0xFF,0xFF,
+0x2F,0x6F,0xDB,0xA8,0x67,0xF9,0x78,0xA7,0x28,0x0A,0x3A,0xFF,0xFF,0x2F,0xC6,0x10,
+0xFE,0x40,0x38,0xCA,0xDB,0xA8,0xC6,0x50,0x30,0xAC,0x21,0x00,0x00,0x39,0x7C,0xD3,
+0xA8,0x7D,0x32,0xFF,0xFF,0x79,0x07,0x07,0x07,0x07,0x4F,0x11,0xFF,0xFF,0xDB,0xA8,
+0xE6,0x3F,0xD3,0xA8,0x06,0x00,0xCB,0x01,0x30,0x0A,0x04,0x3A,0xFF,0xFF,0x2F,0xE6,
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+0x2B,0x2B,0x22,0x72,0xF6,0xC1,0x7D,0x91,0x6F,0x7C,0x98,0x67,0x22,0x74,0xF6,0x2B,
+0x2B,0xC1,0xF9,0xC5,0x3A,0x5F,0xF8,0x6F,0x2C,0x26,0x00,0x29,0x19,0xEB,0xD5,0x01,
+0x09,0x01,0x73,0x23,0x72,0x23,0xEB,0x36,0x00,0x09,0xEB,0x3D,0xF2,0xC2,0x7E,0xE1,
+0x01,0x09,0x00,0x09,0x22,0x62,0xF8,0xC9,0x4D,0x53,0x58,0x20,0x20,0x73,0x79,0x73,
+0x74,0x65,0x6D,0x00,0x76,0x65,0x72,0x73,0x69,0x6F,0x6E,0x20,0x32,0x2E,0x31,0x0D,
+0x0A,0x00,0x4D,0x53,0x58,0x20,0x42,0x41,0x53,0x49,0x43,0x20,0x00,0x43,0x6F,0x70,
+0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x31,0x39,0x38,0x36,0x20,0x62,0x79,0x20,0x4D,
+0x69,0x63,0x72,0x6F,0x73,0x6F,0x66,0x74,0x0D,0x0A,0x00,0x20,0x42,0x79,0x74,0x65,
+0x73,0x20,0x66,0x72,0x65,0x65,0x00,0xD3,0xA8,0x5E,0x18,0x03,0xD3,0xA8,0x73,0x7A,
+0xD3,0xA8,0xC9,0xD3,0xA8,0x08,0xCD,0x98,0xF3,0x08,0xF1,0xD3,0xA8,0x08,0xC9,0xDD,
+0xE9,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,0x47,0x5A,
+0x47,0x5A,0x47,0x5A,0x47,0x25,0x1D,0x1D,0x18,0x0E,0x00,0x00,0x00,0x00,0x00,0x08,
+0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x20,0x00,0x00,0x00,0x1B,0x00,0x38,0x00,0x18,
+0x00,0x20,0x00,0x00,0x00,0x1B,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x1B,
+0x00,0x38,0x01,0x01,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,
+0x0F,0x04,0x04,0xC3,0x00,0x00,0xC3,0x00,0x00,0x0F,0x59,0xF9,0xFF,0x01,0x32,0xF0,
+0xFB,0xF0,0xFB,0x53,0x5C,0x26,0x2D,0x0F,0x25,0x2D,0x0E,0x16,0x1F,0x53,0x5C,0x26,
+0x2D,0x0F,0x00,0x01,0x00,0x01,0x3A,0x11,0x89,0xFD,0xA7,0xC0,0x04,0xC9,0xCD,0xD1,
+0x7F,0x5E,0x18,0x04,0xCD,0xD1,0x7F,0x73,0xDB,0xA8,0xE6,0x3F,0xD3,0xA8,0x79,0x18,
+0x15,0x0F,0x0F,0xE6,0x03,0x57,0xDB,0xA8,0x47,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,
+0x2F,0x4F,0xE6,0xFC,0xB2,0x57,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x7B,0xC9,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0xDB,0x99,0x07,0x30,0xFB,0xC3,0x1C,0x00,0xC3,0x7D,0xF3,
+};
diff --git a/MCUME_pico2/picomsx/bios/msx2ext.h b/MCUME_pico2/picomsx/bios/msx2ext.h
new file mode 100644
index 0000000..ad4bb0d
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/msx2ext.h
@@ -0,0 +1,1026 @@
+static const uint8_t MSX2EXT[16384] = {
+0x43,0x44,0x36,0x03,0x49,0x16,0x2A,0x37,0xC3,0x32,0x1D,0x00,0x00,0x00,0x00,0x00,
+0xC3,0x3A,0x1D,0x00,0xC3,0x18,0x02,0x00,0xC3,0x77,0x05,0x00,0xC3,0x62,0x02,0x00,
+0x7C,0x92,0xC0,0x7D,0x93,0xC9,0x00,0x00,0xC3,0x0E,0x06,0x00,0x00,0x00,0x00,0x00,
+0xC3,0x46,0x02,0x00,0x00,0x00,0x00,0x00,0x08,0xD9,0xF5,0xC5,0xD5,0xE5,0x08,0xD9,
+0xDD,0xE5,0xFD,0xE5,0xDD,0x21,0x38,0x00,0xFD,0x2A,0xC0,0xFC,0xCD,0x8D,0x05,0xFD,
+0xE1,0xDD,0xE1,0x08,0xD9,0xE1,0xD1,0xC1,0xF1,0x08,0xD9,0xFB,0xED,0x4D,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xC3,0xD6,0xFD,0xFB,0xC3,0x51,0x26,0xFB,0xC3,0x56,
+0x25,0xFB,0xC3,0x6F,0x25,0xFB,0xC3,0x07,0x26,0xFB,0xC3,0x2A,0x26,0xFB,0xC3,0x3F,
+0x26,0xFB,0xC3,0x48,0x26,0xFB,0xC3,0x23,0x28,0xFB,0xC3,0x0E,0x11,0xFB,0xC3,0xC4,
+0x12,0xFB,0xC3,0x42,0x13,0xFB,0xC3,0x84,0x13,0xFB,0xC3,0xAD,0x13,0xFB,0xC3,0xB5,
+0x13,0xFB,0xC3,0x26,0x14,0xFB,0xC3,0x39,0x14,0xFB,0xC3,0xE7,0x13,0xFB,0xC3,0x4B,
+0x14,0xFB,0xC3,0xFC,0x13,0xFB,0xC3,0x8C,0x14,0xFB,0xC3,0x14,0x14,0xFB,0xC3,0x98,
+0x14,0xFB,0xC3,0xDB,0x14,0xFB,0xC3,0x8F,0x15,0xFB,0xC3,0xE7,0x27,0xFB,0xC3,0x98,
+0x28,0xFB,0xC3,0xC3,0x09,0xFB,0xC3,0xE5,0x09,0xFB,0xC3,0x1A,0x0A,0xFB,0xC3,0x48,
+0x0A,0xFB,0xC3,0x98,0x0A,0xFB,0xC3,0x42,0x0B,0xFB,0xC3,0x9C,0x0B,0xFB,0xC3,0xD2,
+0x0B,0xFB,0xC3,0x22,0x0C,0xFB,0xC3,0xF5,0x06,0xFB,0xC3,0x55,0x07,0xFB,0xC3,0x6A,
+0x07,0xFB,0xC3,0x7F,0x07,0xFB,0xC3,0xD9,0x07,0xFB,0xC3,0xCB,0x08,0xFB,0xC3,0xD6,
+0x08,0xFB,0xC3,0x53,0x09,0xFB,0xC3,0xFE,0x07,0xFB,0xC3,0x64,0x08,0xFB,0xC3,0x52,
+0x0D,0xFB,0xC3,0x0F,0x0E,0xFB,0xC3,0x5D,0x0E,0xFB,0xC3,0x16,0x0F,0xFB,0xC3,0x47,
+0x06,0xFB,0xC3,0x8B,0x29,0xC9,0xC9,0xC9,0xC9,0xC9,0xC9,0xC9,0xC9,0xFB,0xC3,0xA8,
+0x06,0xFB,0xC3,0x9F,0x0F,0xFB,0xC3,0x7E,0x0F,0xFB,0xC3,0x6A,0x0F,0xFB,0xC3,0xD3,
+0x0F,0xFB,0xC3,0x8F,0x20,0xFB,0xC3,0xF6,0x1D,0xFB,0xC3,0xE5,0x1E,0xFB,0xC3,0xDF,
+0x1F,0xFB,0xC3,0xC6,0x21,0xFB,0xC3,0xE5,0x21,0xFB,0xC3,0x20,0x22,0xFB,0xC3,0x97,
+0x22,0xFB,0xC3,0xF4,0x22,0xFB,0xC3,0x07,0x23,0xFB,0xC3,0x33,0x18,0xFB,0xC3,0x62,
+0x1A,0xFB,0xC3,0x4E,0x1B,0xFB,0xC3,0x80,0x04,0xFB,0xC3,0x70,0x04,0xFB,0xC3,0x42,
+0x23,0xFB,0xC3,0xB9,0x2E,0xFB,0xC3,0x42,0x2F,0xFB,0xC3,0xDF,0x2E,0xFB,0xC3,0xA8,
+0x30,0xFB,0xC3,0xB4,0x31,0xFB,0xC3,0x6F,0x30,0xFB,0xC3,0x7C,0x30,0xFB,0xC3,0xDD,
+0x34,0xFB,0xC3,0x83,0x16,0xFB,0xC3,0xBF,0x09,0xFB,0xC3,0x00,0x00,0xFB,0xC3,0x49,
+0x10,0x78,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0x5F,0x32,0xFF,0xFF,
+0x78,0xA2,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0xC5,0xD9,0x08,0xCD,0x98,0xF3,0xF3,0x08,
+0xD9,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,
+0xC5,0xFC,0x08,0xD9,0xC9,0xFB,0xC3,0x08,0x1D,0xFB,0xC3,0x10,0x1D,0xCD,0xDD,0x02,
+0xFA,0x0D,0x02,0xDB,0xA8,0x57,0xA1,0xB0,0xCD,0x80,0xF3,0x7B,0xC9,0xE5,0xCD,0x02,
+0x03,0xE3,0xC5,0xCD,0xFD,0x01,0x18,0x1B,0xD5,0xCD,0xDD,0x02,0xFA,0x28,0x02,0xD1,
+0xDB,0xA8,0x57,0xA1,0xB0,0xC3,0x85,0xF3,0xE3,0xE5,0xCD,0x02,0x03,0xD1,0xE3,0xC5,
+0xCD,0x18,0x02,0xC1,0xE3,0xF5,0x78,0xE6,0x3F,0xB1,0xD3,0xA8,0x7D,0x32,0xFF,0xFF,
+0x78,0xD3,0xA8,0xF1,0xE1,0xC9,0xE3,0xF5,0xD5,0x7E,0xF5,0xFD,0xE1,0x23,0x5E,0x23,
+0x56,0x23,0xD5,0xDD,0xE1,0xD1,0xF1,0xE3,0xD9,0x16,0xFC,0x18,0x08,0xD9,0x16,0xF3,
+0x18,0x03,0xD9,0x16,0xF0,0x08,0xF3,0x3A,0xC1,0xFC,0xA7,0xDB,0xA8,0xFA,0x76,0x02,
+0xF5,0xA2,0xD9,0xC3,0x8C,0xF3,0x47,0x3A,0xF8,0xFA,0xE6,0x03,0x20,0x06,0x7A,0xFE,
+0xF3,0xC2,0xC1,0x01,0x78,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0x32,
+0xFF,0xFF,0x5F,0x78,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0x78,0xC5,0x21,0xA6,0x02,0xE5,
+0xF5,0xA2,0xD9,0xC3,0x8C,0xF3,0xF3,0xD9,0x08,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,
+0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,0xC5,0xFC,0x08,0xD9,0xC9,0xCD,0xDD,0x02,
+0xFA,0xCA,0x02,0xDB,0xA8,0xA1,0xB0,0xD3,0xA8,0xC9,0xE5,0xCD,0x02,0x03,0x4F,0x06,
+0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE1,0x79,0x18,0xE0,0xF3,0xF5,0x7C,
+0x07,0x07,0xE6,0x03,0x5F,0x3E,0xC0,0x07,0x07,0x1D,0xF2,0xE7,0x02,0x5F,0x2F,0x4F,
+0xF1,0xF5,0xE6,0x03,0x3C,0x47,0x3E,0xAB,0xC6,0x55,0x10,0xFC,0x57,0xA3,0x47,0xF1,
+0xA7,0xC9,0xF5,0x7A,0xE6,0xC0,0x4F,0xF1,0xF5,0x57,0xDB,0xA8,0x47,0xE6,0x3F,0xB1,
+0xD3,0xA8,0x7A,0x0F,0x0F,0xE6,0x03,0x57,0x3E,0xAB,0xC6,0x55,0x15,0xF2,0x1A,0x03,
+0xA3,0x57,0x7B,0x2F,0x67,0x3A,0xFF,0xFF,0x2F,0x6F,0xA4,0xB2,0x32,0xFF,0xFF,0x78,
+0xD3,0xA8,0xF1,0xE6,0x03,0xC9,0x21,0xF6,0x29,0x11,0xDF,0xF3,0x01,0x08,0x00,0xED,
+0xB0,0x11,0xE7,0xFF,0x01,0x10,0x00,0xED,0xB0,0xAF,0x32,0xF5,0xFA,0x32,0xF6,0xFA,
+0xCD,0x12,0x05,0x32,0xF8,0xFA,0x67,0x2E,0xF7,0x22,0xFD,0xFE,0x21,0x9C,0x3D,0x22,
+0xFF,0xFE,0x3A,0xC1,0xFC,0x32,0xF7,0xFF,0x3E,0x2C,0x32,0xFF,0xFA,0x3E,0x26,0x32,
+0x01,0xFB,0x3E,0xD3,0xD3,0xF7,0xCD,0xF3,0x36,0xAF,0x0E,0xFF,0xD3,0xD8,0x3E,0x02,
+0xD3,0xD9,0x21,0x0A,0x05,0x06,0x08,0xDB,0xD9,0xBE,0x20,0x05,0x23,0x10,0xF8,0xCB,
+0x81,0xDB,0xC0,0xFE,0xFF,0x28,0x02,0xCB,0x91,0xDB,0xF7,0xE6,0x77,0xFE,0x77,0x28,
+0x02,0xCB,0x99,0xDB,0xC8,0xFE,0xFF,0x28,0x02,0xCB,0xA1,0xAF,0xD3,0x81,0xF5,0xF1,
+0xD3,0x81,0xF5,0xF1,0xD3,0x81,0xF5,0xF1,0x3E,0x40,0xD3,0x81,0xE3,0xE3,0xDB,0x81,
+0xE6,0x3F,0xFE,0x05,0x20,0x02,0xCB,0xA9,0xDB,0xBB,0xFE,0xFF,0x28,0x02,0xCB,0xB1,
+0x79,0xD3,0xF5,0xCD,0xF7,0x1C,0x06,0x00,0xCD,0xD2,0x1C,0xFE,0x0A,0x28,0x03,0xCD,
+0x31,0x04,0xCD,0xF7,0x1C,0x06,0x03,0xCD,0xD2,0x1C,0xE6,0x01,0xF5,0xCD,0xDB,0x1C,
+0xC1,0xFE,0x51,0xD2,0xDF,0x03,0xB7,0xCA,0xDF,0x03,0x05,0x20,0x05,0xFE,0x21,0xD2,
+0xDF,0x03,0xCD,0xF7,0x1C,0x06,0x01,0xCD,0xD2,0x1C,0x57,0xCD,0xD2,0x1C,0x5F,0xCD,
+0xF8,0x17,0xCD,0x0E,0x2A,0x06,0x02,0x21,0x00,0x00,0x2B,0x7D,0xB4,0x20,0xFB,0x10,
+0xF9,0xCD,0x3C,0x06,0xAF,0x01,0x00,0x40,0xCD,0x77,0x09,0xCD,0x1A,0x0A,0xC3,0x9F,
+0x0F,0x21,0x1C,0x37,0x0E,0x02,0x06,0x0D,0x3E,0x04,0x91,0xCD,0x59,0x1A,0x06,0x0D,
+0x3E,0x0D,0x90,0xD3,0xB4,0x7E,0x23,0xFE,0xFF,0x20,0x02,0x2B,0xAF,0xD3,0xB5,0x10,
+0xEF,0x0D,0x20,0xE2,0x06,0x0D,0x3E,0x08,0xCD,0x59,0x1A,0xAF,0xCD,0x59,0x1A,0x3E,
+0x0D,0xCD,0x59,0x1A,0x3E,0x01,0xCD,0xF9,0x1C,0x06,0x0A,0x3E,0x01,0xC3,0x59,0x1A,
+0x37,0xCD,0x81,0x04,0x21,0xF2,0x7E,0xCD,0xF6,0x05,0x21,0xE4,0x7E,0xC3,0xF6,0x05,
+0xAF,0xF5,0xCD,0xF7,0x1C,0x06,0x03,0xCD,0xD2,0x1C,0x4F,0xE6,0x01,0xD1,0xF5,0xD5,
+0xC5,0x79,0x07,0x07,0xE6,0x08,0x4F,0x3A,0xE8,0xFF,0xE6,0xF7,0xB1,0x47,0x0E,0x09,
+0xCD,0x47,0x06,0xC1,0xCD,0xDB,0x1C,0x5F,0xF1,0xD5,0xF5,0xCD,0xD2,0x1C,0x32,0xE9,
+0xF3,0x32,0xF2,0xF3,0xCD,0xD2,0x1C,0x32,0xEA,0xF3,0xCD,0xD2,0x1C,0x32,0xEB,0xF3,
+0xCD,0xD2,0x1C,0x4F,0xCB,0x09,0x9F,0x47,0xF1,0x30,0x01,0x78,0x32,0xDE,0xF3,0xCB,
+0x09,0x9F,0x32,0xDB,0xF3,0xCB,0x49,0xC5,0x01,0x05,0x00,0x21,0xFC,0xF3,0x28,0x03,
+0x21,0x01,0xF4,0x11,0x06,0xF4,0xED,0xB0,0xC1,0xCB,0x09,0x9F,0x32,0x17,0xF4,0xD1,
+0xF1,0x32,0xB0,0xFC,0x32,0xAF,0xFC,0xD5,0xCD,0xBF,0x09,0xD1,0xC3,0xFF,0x1F,0x0A,
+0x00,0x00,0x01,0x0D,0x01,0x0F,0x04,0x07,0x03,0xFF,0x00,0x40,0x20,0x10,0x08,0x04,
+0x02,0x01,0xC5,0xE5,0xDB,0xA8,0xE6,0x03,0x4F,0x06,0x00,0x21,0xC1,0xFC,0x09,0xB6,
+0x4F,0x23,0x23,0x23,0x23,0x7E,0xE6,0x03,0x07,0x07,0xB1,0xE1,0xC1,0xC9,0xDD,0x21,
+0x6B,0x6E,0x18,0x2E,0xDD,0x21,0x86,0x6E,0x18,0x28,0xDD,0x21,0x6E,0x6E,0x18,0x22,
+0xDD,0x21,0x55,0x40,0x18,0x1C,0xDD,0x21,0x5A,0x47,0x18,0x16,0xDD,0x21,0x6A,0x40,
+0x18,0x10,0xDD,0x21,0x6D,0x40,0x18,0x0A,0xDD,0x21,0x75,0x62,0x18,0x04,0xDD,0x21,
+0x74,0x6E,0xC3,0x18,0x06,0xDD,0x21,0x9F,0x00,0x18,0x22,0xDD,0x21,0x90,0x00,0x18,
+0x1C,0xDD,0x21,0xC9,0x00,0x18,0x16,0xDD,0x21,0x18,0x00,0x18,0x10,0xDD,0x21,0x0C,
+0x00,0x18,0x0A,0xDD,0x21,0x14,0x00,0x18,0x04,0xDD,0x21,0xBD,0x00,0xC3,0x58,0x02,
+0xDD,0x21,0x41,0x01,0x18,0xF7,0xDD,0x21,0x68,0x01,0x18,0xF1,0xDD,0x21,0x9C,0x57,
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
diff --git a/MCUME_pico2/picomsx/bios/msx2p.h b/MCUME_pico2/picomsx/bios/msx2p.h
new file mode 100644
index 0000000..63c722a
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/msx2p.h
@@ -0,0 +1,2050 @@
+static const uint8_t MSX2P[32768] = {
+0xF3,0xC3,0x16,0x04,0xBF,0x1B,0x98,0x98,0xC3,0x83,0x26,0x00,0xC3,0xF5,0x01,0x00,
+0xC3,0x86,0x26,0x00,0xC3,0x25,0x02,0x00,0xC3,0x45,0x1B,0x00,0xC3,0x17,0x02,0x00,
+0xC3,0x04,0x0C,0x00,0xC3,0x33,0x03,0x00,0xC3,0x89,0x26,0x00,0x00,0x02,0x00,0x00,
+0xC3,0xC6,0x02,0x00,0x00,0x00,0x00,0x00,0xC3,0x3C,0x0C,0xC3,0x92,0x05,0xC3,0xA0,
+0x13,0xC3,0x0A,0x06,0xC3,0x03,0x06,0xC3,0x12,0x06,0xC3,0xE1,0x07,0xC3,0xD7,0x07,
+0xC3,0x08,0x08,0xC3,0xF4,0x07,0xC3,0x3B,0x08,0xC3,0x3D,0x07,0xC3,0x80,0x07,0xC3,
+0xB1,0x08,0xC3,0x1A,0x08,0x00,0xC3,0x9B,0x13,0xC3,0x7F,0x06,0xC3,0x3E,0x06,0xC3,
+0x47,0x06,0xC3,0x4F,0x06,0xC3,0x57,0x06,0xC3,0x5F,0x06,0xC3,0x67,0x06,0xC3,0x6F,
+0x06,0xC3,0x77,0x06,0xC3,0xEC,0x06,0xC3,0x01,0x07,0xC3,0x0C,0x07,0xC3,0x0E,0x15,
+0xC3,0xB2,0x05,0xC3,0x02,0x11,0xC3,0x0E,0x11,0xC3,0xBA,0x11,0xC3,0x6A,0x0D,0xC3,
+0xCB,0x10,0xC3,0x19,0x09,0xC3,0xBA,0x08,0xC3,0xE1,0x08,0xC3,0xFA,0x08,0xC3,0xBF,
+0x23,0xC3,0xD5,0x23,0xC3,0xCC,0x23,0xC3,0x64,0x05,0xC3,0xF0,0x04,0xC3,0xF9,0x10,
+0xC3,0x13,0x11,0xC3,0x97,0x08,0xC3,0xEB,0x08,0xC3,0x3A,0x0B,0xC3,0x29,0x0B,0xC3,
+0x3F,0x0B,0xC3,0x9E,0x08,0xC3,0xE4,0x11,0xC3,0x49,0x12,0xC3,0xA2,0x12,0xC3,0x69,
+0x12,0xC3,0x63,0x1A,0xC3,0xBC,0x1A,0xC3,0xE9,0x19,0xC3,0xF1,0x19,0xC3,0x19,0x1A,
+0xC3,0xDD,0x19,0xC3,0x87,0x13,0xC3,0xE9,0x14,0xC3,0x90,0x14,0xC3,0x56,0x17,0xC3,
+0x90,0x17,0xC3,0x1F,0x18,0xC3,0xF6,0x17,0xC3,0xDC,0x17,0xC3,0xB4,0x17,0xC3,0xA5,
+0x15,0xC3,0x04,0x16,0xC3,0x51,0x16,0xC3,0x58,0x16,0xC3,0x92,0x16,0xC3,0x5F,0x16,
+0xC3,0xC3,0x16,0xC3,0x43,0x18,0xC3,0x01,0x19,0xC3,0x09,0x19,0xC3,0x1E,0x19,0xC3,
+0x94,0x19,0xC3,0x3D,0x0F,0xC3,0x7A,0x0F,0xC3,0x0E,0x14,0xC3,0x11,0x14,0xC3,0x0B,
+0x14,0xC3,0xEC,0x0B,0xC3,0x14,0x14,0xC3,0x18,0x14,0xC3,0xF9,0x0B,0xC3,0x63,0x1B,
+0xC3,0x0A,0x0C,0xC3,0x0E,0x0C,0xC3,0x5D,0x05,0xC3,0xBF,0x02,0xC3,0x95,0x02,0xC3,
+0x9B,0x02,0xC3,0xAC,0x03,0xC3,0xA9,0x06,0xC3,0x05,0x0B,0xC3,0x38,0x08,0xC3,0xC5,
+0x06,0xC3,0xB3,0x06,0xC3,0xE9,0x07,0xC3,0x69,0x07,0xC3,0x6A,0x14,0xC3,0x6E,0x14,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xF1,0x16,0xFC,0xE6,0x0C,0x0F,0x0F,0x67,0xDB,0xA8,
+0x47,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0xB4,0x5F,0x32,0xFF,0xFF,
+0x78,0xA2,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0xC5,0xD9,0x08,0xCD,0x98,0xF3,0xF3,0x08,
+0xD9,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,
+0xC5,0xFC,0x08,0xD9,0xC9,0xCD,0x53,0x03,0xFA,0x05,0x02,0xDB,0xA8,0x57,0xA1,0xB0,
+0xCD,0x80,0xF3,0x7B,0xC9,0xCD,0x8C,0x02,0x20,0x10,0xE5,0xCD,0x55,0x02,0xE3,0xCD,
+0xBE,0x7F,0x18,0x30,0x00,0x00,0x00,0xC3,0xD8,0x02,0xE5,0xCD,0x78,0x03,0xE3,0xC5,
+0xCD,0xF5,0x01,0x18,0x54,0xD5,0xCD,0x53,0x03,0xFA,0x35,0x02,0xD1,0xDB,0xA8,0x57,
+0xA1,0xB0,0xC3,0x85,0xF3,0xCD,0x8C,0x02,0xC2,0x6E,0x02,0xD1,0xE5,0xCD,0x55,0x02,
+0xE3,0xCD,0xC4,0x7F,0xE3,0xF5,0x7D,0xE6,0x3F,0xD3,0xA8,0x7C,0x32,0xFF,0xFF,0x7D,
+0xD3,0xA8,0xF1,0xE1,0xC9,0xF5,0xDB,0xA8,0x6F,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,
+0x2F,0x67,0xE6,0xF3,0x32,0xFF,0xFF,0x7D,0xE6,0xF3,0xD3,0xA8,0xF1,0xC9,0xE3,0xE5,
+0xCD,0x78,0x03,0xD1,0xE3,0xC5,0xCD,0x25,0x02,0xC1,0xE3,0xF5,0x78,0xE6,0x3F,0xB1,
+0xD3,0xA8,0x7D,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0xF1,0xE1,0xC9,0x14,0x15,0xC0,0x47,
+0x7B,0xFE,0x03,0x78,0xC9,0xCD,0x9B,0x02,0xDD,0xE1,0xC9,0xD9,0x08,0xE5,0xD5,0xC5,
+0xF5,0xED,0x57,0xF5,0xD9,0x08,0xFD,0xE5,0xFD,0x2A,0xF7,0xFA,0xCD,0x17,0x02,0xFD,
+0xE1,0x08,0xD9,0xF1,0xE2,0xB8,0x02,0xFB,0xF1,0xC1,0xD1,0xE1,0xD9,0x08,0xC9,0xFD,
+0x2A,0xC0,0xFC,0xC3,0x17,0x02,0xE3,0xF5,0xD5,0x7E,0xF5,0xFD,0xE1,0x23,0x5E,0x23,
+0x56,0x23,0xD5,0xDD,0xE1,0xD1,0xF1,0xE3,0xD9,0x08,0xFD,0xE5,0xF1,0xDD,0xE5,0xE1,
+0xCD,0x53,0x03,0xFA,0xEF,0x02,0xDB,0xA8,0xF5,0xA1,0xB0,0xD9,0xC3,0x8C,0xF3,0xF5,
+0xE6,0x03,0x20,0x06,0x7C,0xE6,0xC0,0xCA,0xB6,0x01,0xF1,0xCD,0x78,0x03,0xF5,0xFD,
+0xE1,0xE5,0xC5,0x4F,0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE5,0x08,
+0xD9,0xCD,0x17,0x02,0xD9,0x08,0xE1,0xC1,0xD1,0xED,0x57,0xF5,0x78,0xE6,0x3F,0xB1,
+0xF3,0xD3,0xA8,0x7B,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x73,0xF1,0xE2,0x30,0x03,0xFB,
+0x08,0xD9,0xC9,0xCD,0x53,0x03,0xFA,0x40,0x03,0xDB,0xA8,0xA1,0xB0,0xD3,0xA8,0xC9,
+0xE5,0xCD,0x78,0x03,0x4F,0x06,0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE1,
+0x79,0x18,0xE0,0xF3,0xF5,0x7C,0x07,0x07,0xE6,0x03,0x5F,0x3E,0xC0,0x07,0x07,0x1D,
+0xF2,0x5D,0x03,0x5F,0x2F,0x4F,0xF1,0xF5,0xE6,0x03,0x3C,0x47,0x3E,0xAB,0xC6,0x55,
+0x10,0xFC,0x57,0xA3,0x47,0xF1,0xA7,0xC9,0xF5,0x7A,0xE6,0xC0,0x4F,0xF1,0xF5,0x57,
+0xDB,0xA8,0x47,0xE6,0x3F,0xB1,0xD3,0xA8,0x7A,0x0F,0x0F,0xE6,0x03,0x57,0x3E,0xAB,
+0xC6,0x55,0x15,0xF2,0x90,0x03,0xA3,0x57,0x7B,0x2F,0x67,0x3A,0xFF,0xFF,0x2F,0x6F,
+0xA4,0xB2,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0xF1,0xE6,0x03,0xC9,0xF3,0x0E,0x00,0x11,
+0xC1,0xFC,0x21,0xC9,0xFC,0x1A,0xB1,0x4F,0xD5,0xE5,0x21,0x00,0x00,0xCD,0x1A,0x7E,
+0xE5,0x21,0x43,0x44,0xE7,0xE1,0x06,0x00,0x20,0x25,0xCD,0x1A,0x7E,0xE5,0xC5,0xD5,
+0xDD,0xE1,0x79,0xF5,0xFD,0xE1,0xC4,0x17,0x02,0xC1,0xE1,0xCD,0x1A,0x7E,0xC6,0xFF,
+0xCB,0x18,0xCD,0x1A,0x7E,0xC6,0xFF,0xCB,0x18,0xCB,0x38,0x11,0xF8,0xFF,0x19,0xE3,
+0x70,0xE3,0xE1,0x23,0x23,0x23,0x23,0x79,0xA7,0x11,0x0C,0x00,0xF2,0x0A,0x04,0xC6,
+0x04,0x4F,0xFE,0x90,0x38,0xB3,0xE6,0x03,0x4F,0x3E,0x19,0xD1,0x13,0x0C,0x79,0xFE,
+0x04,0x38,0xA2,0xC3,0x72,0x14,0xAF,0xD3,0xFF,0x3C,0xD3,0xFE,0x3C,0xD3,0xFD,0x3C,
+0xD3,0xFC,0x3E,0x08,0xD3,0xBB,0x3E,0x82,0xD3,0xAB,0xAF,0xD3,0xA8,0x3E,0x50,0xD3,
+0xAA,0x11,0xFF,0xFF,0xAF,0x4F,0xD3,0xA8,0xCB,0x21,0x06,0x00,0x21,0xFF,0xFF,0x36,
+0xF0,0x7E,0xD6,0x0F,0x20,0x0B,0x77,0x7E,0x3C,0x20,0x06,0x04,0xCB,0xC1,0x32,0xFF,
+0xFF,0x21,0x00,0xBF,0x7E,0x2F,0x77,0xBE,0x2F,0x77,0x20,0x07,0x2C,0x20,0xF5,0x25,
+0xFA,0x54,0x04,0x2E,0x00,0x24,0x7D,0x93,0x7C,0x9A,0x30,0x0A,0xEB,0x3A,0xFF,0xFF,
+0x2F,0x6F,0xDB,0xA8,0x67,0xF9,0x78,0xA7,0x28,0x0A,0x3A,0xFF,0xFF,0x2F,0xC6,0x10,
+0xFE,0x40,0x38,0xCA,0xDB,0xA8,0xC6,0x50,0x30,0xAC,0x21,0x00,0x00,0x39,0x7C,0xD3,
+0xA8,0x7D,0x32,0xFF,0xFF,0x79,0x07,0x07,0x07,0x07,0x4F,0x11,0xFF,0xFF,0xDB,0xA8,
+0xE6,0x3F,0xD3,0xA8,0x06,0x00,0xCB,0x01,0x30,0x0A,0x04,0x3A,0xFF,0xFF,0x2F,0xE6,
+0x3F,0x32,0xFF,0xFF,0x21,0x00,0xFE,0x7E,0x2F,0x77,0xBE,0x2F,0x77,0x20,0x09,0x2C,
+0x20,0xF5,0x25,0x7C,0xFE,0xC0,0x30,0xEF,0x2E,0x00,0x24,0x7D,0x93,0x7C,0x9A,0x30,
+0x0A,0xEB,0x3A,0xFF,0xFF,0x2F,0x6F,0xDB,0xA8,0x67,0xF9,0x78,0xA7,0x28,0x08,0x3A,
+0xFF,0xFF,0x2F,0xC6,0x40,0x30,0xCA,0xDB,0xA8,0xC6,0x40,0x30,0xB5,0xC3,0x61,0x7B,
+0x3A,0xB1,0xFB,0xA7,0xC0,0xE5,0x21,0x9B,0xFC,0xF3,0x7E,0xFB,0x36,0x00,0xE1,0xA7,
+0xC8,0xFE,0x03,0x28,0x1C,0xE5,0xD5,0xC5,0xCD,0x37,0x0A,0x21,0x9B,0xFC,0xF3,0x7E,
+0xFB,0x36,0x00,0xA7,0x28,0xF8,0xF5,0xCD,0x84,0x0A,0xF1,0xC1,0xD1,0xE1,0xFE,0x03,
+0xC0,0xE5,0xCD,0x5D,0x05,0xCD,0x49,0x05,0x30,0x0A,0x21,0x6A,0xFC,0xF3,0xCD,0xF1,
+0x0E,0xFB,0xE1,0xC9,0xCD,0x9E,0x08,0x3A,0xC1,0xFC,0x26,0x40,0xCD,0x33,0x03,0xE1,
+0xAF,0xED,0x7B,0xB1,0xF6,0xC5,0xC3,0xE6,0x63,0x3A,0x6A,0xFC,0x0F,0xD0,0x2A,0x6B,
+0xFC,0x7C,0xB5,0xC8,0x2A,0x1C,0xF4,0x23,0x7C,0xB5,0xC8,0x37,0xC9,0x2A,0xF8,0xF3,
+0x22,0xFA,0xF3,0xC9,0xDB,0xAA,0xE6,0xF0,0xF6,0x07,0xD3,0xAA,0xDB,0xA9,0xE6,0x10,
+0xC0,0xDB,0xAA,0x3D,0xD3,0xAA,0xDB,0xA9,0xE6,0x02,0xC0,0xE5,0x2A,0xF8,0xF3,0x22,
+0xFA,0xF3,0xE1,0x3A,0xE1,0xFB,0xE6,0xEF,0x32,0xE1,0xFB,0x3E,0x14,0x32,0xF7,0xF3,
+0x37,0xC9,0x3E,0x07,0x1E,0x80,0xCD,0x02,0x11,0x3E,0x0F,0x1E,0xCF,0xCD,0x02,0x11,
+0x3E,0x0B,0x5F,0xCD,0x02,0x11,0xCD,0x0C,0x11,0xE6,0x40,0x32,0xAD,0xFC,0x3E,0xFF,
+0xD3,0x90,0xE5,0xD5,0xC5,0xF5,0x21,0x3F,0xFB,0x06,0x71,0xAF,0x77,0x23,0x10,0xFC,
+0x11,0x75,0xF9,0x06,0x7F,0x21,0x80,0x00,0xE5,0xD5,0xC5,0xF5,0xCD,0xD8,0x14,0xF1,
+0xC6,0x08,0x1E,0x00,0xCD,0x02,0x11,0xD6,0x08,0xF5,0x2E,0x0F,0xCD,0x11,0x0C,0xEB,
+0x21,0xFD,0x05,0x01,0x06,0x00,0xED,0xB0,0xF1,0xC1,0xE1,0xD1,0x19,0xEB,0x3C,0xFE,
+0x03,0x38,0xD5,0x3E,0x07,0x1E,0xB8,0xCD,0x02,0x11,0xC3,0x37,0x09,0x04,0x04,0x78,
+0x88,0xFF,0x00,0x3A,0xE0,0xF3,0xF6,0x40,0x18,0x05,0x3A,0xE0,0xF3,0xE6,0xBF,0x47,
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+0x00,0x00,0xDB,0x99,0x07,0x30,0xFB,0xC3,0x1C,0x00,0xC3,0xCA,0xFF,0xC3,0x7D,0xF3,
+};
diff --git a/MCUME_pico2/picomsx/bios/msx2pext.h b/MCUME_pico2/picomsx/bios/msx2pext.h
new file mode 100644
index 0000000..09f591c
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/msx2pext.h
@@ -0,0 +1,1026 @@
+static const uint8_t MSX2PEXT[16384] = {
+0x43,0x44,0x5A,0x03,0x31,0x17,0x58,0x36,0xC3,0xB9,0x1C,0x00,0x00,0x00,0x00,0x00,
+0xC3,0xC1,0x1C,0x00,0xC3,0x18,0x02,0x00,0xC3,0x87,0x27,0x00,0xC3,0x62,0x02,0x00,
+0x7C,0x92,0xC0,0x7D,0x93,0xC9,0x00,0x00,0xC3,0x24,0x28,0x00,0x00,0x00,0x00,0xF1,
+0xC3,0x46,0x02,0x01,0x1E,0x80,0x01,0x1E,0x08,0xD9,0xF5,0xC5,0xD5,0xE5,0x08,0xD9,
+0xDD,0xE5,0xFD,0xE5,0xDD,0x21,0x38,0x00,0xFD,0x2A,0xC0,0xFC,0xCD,0x9D,0x27,0xFD,
+0xE1,0xDD,0xE1,0x08,0xD9,0xE1,0xD1,0xC1,0xF1,0x08,0xD9,0xFB,0xED,0x4D,0x91,0x1B,
+0xB9,0x20,0x06,0xCD,0x34,0x0E,0xC3,0xD6,0xFD,0xFB,0xC3,0x51,0x26,0xFB,0xC3,0x33,
+0x28,0xFB,0xC3,0x4C,0x28,0xFB,0xC3,0xE4,0x28,0xFB,0xC3,0x07,0x29,0xFB,0xC3,0x1C,
+0x29,0xFB,0xC3,0x25,0x29,0xFB,0xC3,0x9B,0x29,0xFB,0xC3,0xBC,0x11,0xFB,0xC3,0x76,
+0x13,0xFB,0xC3,0xFC,0x13,0xFB,0xC3,0x3E,0x14,0xFB,0xC3,0x67,0x14,0xFB,0xC3,0x6F,
+0x14,0xFB,0xC3,0xEB,0x14,0xFB,0xC3,0xFE,0x14,0xFB,0xC3,0xA1,0x14,0xFB,0xC3,0x10,
+0x15,0xFB,0xC3,0xB6,0x14,0xFB,0xC3,0x51,0x15,0xFB,0xC3,0xD9,0x14,0xFB,0xC3,0x5D,
+0x15,0xFB,0xC3,0xA0,0x15,0xFB,0xC3,0x52,0x16,0xFB,0xC3,0x5F,0x29,0xFB,0xC3,0x75,
+0x2A,0xFB,0xC3,0x53,0x0A,0xFB,0xC3,0x75,0x0A,0xFB,0xC3,0xAA,0x0A,0xFB,0xC3,0xD8,
+0x0A,0xFB,0xC3,0x28,0x0B,0xFB,0xC3,0xE6,0x0B,0xFB,0xC3,0x40,0x0C,0xFB,0xC3,0x76,
+0x0C,0xFB,0xC3,0xC6,0x0C,0xFB,0xC3,0x6D,0x07,0xFB,0xC3,0xD1,0x07,0xFB,0xC3,0xE6,
+0x07,0xFB,0xC3,0xFB,0x07,0xFB,0xC3,0x55,0x08,0xFB,0xC3,0x5C,0x09,0xFB,0xC3,0x67,
+0x09,0xFB,0xC3,0xE4,0x09,0xFB,0xC3,0x7A,0x08,0xFB,0xC3,0xF5,0x08,0xFB,0xC3,0xF4,
+0x0D,0xFB,0xC3,0xB1,0x0E,0xFB,0xC3,0xFF,0x0E,0xFB,0xC3,0xB8,0x0F,0xFB,0xC3,0x88,
+0x06,0xFB,0xC3,0xEF,0x2B,0xFB,0xC3,0x87,0x3E,0xFB,0xC3,0x4C,0x3C,0xFB,0xC3,0x14,
+0x07,0xFB,0xC3,0x41,0x10,0xFB,0xC3,0x20,0x10,0xFB,0xC3,0x0C,0x10,0xFB,0xC3,0x75,
+0x10,0xFB,0xC3,0xDA,0x20,0xFB,0xC3,0x7D,0x1D,0xFB,0xC3,0x8B,0x1E,0xFB,0xC3,0x2A,
+0x20,0xFB,0xC3,0x11,0x22,0xFB,0xC3,0x37,0x22,0xFB,0xC3,0x7B,0x22,0xFB,0xC3,0xF2,
+0x22,0xFB,0xC3,0x5E,0x23,0xFB,0xC3,0x71,0x23,0xFB,0xC3,0x1B,0x19,0xFB,0xC3,0x53,
+0x1B,0xFB,0xC3,0x3F,0x1C,0xFB,0xC3,0xFC,0x04,0xFB,0xC3,0xD6,0x04,0xFB,0xC3,0xAC,
+0x23,0xFB,0xC3,0x32,0x2E,0xFB,0xC3,0xBB,0x2E,0xFB,0xC3,0x58,0x2E,0xFB,0xC3,0x21,
+0x30,0xFB,0xC3,0x2D,0x31,0xFB,0xC3,0xE8,0x2F,0xFB,0xC3,0xF5,0x2F,0xFB,0xC3,0x60,
+0x34,0xFB,0xC3,0x6B,0x17,0xFB,0xC3,0x4F,0x0A,0xFB,0xC3,0x00,0x00,0xFB,0xC3,0xEB,
+0x10,0x78,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0x5F,0x32,0xFF,0xFF,
+0x78,0xA2,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0xC5,0xD9,0x08,0xCD,0x98,0xF3,0xF3,0x08,
+0xD9,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,
+0xC5,0xFC,0x08,0xD9,0xC9,0xFB,0xC3,0x96,0x1C,0xFB,0xC3,0x9E,0x1C,0xCD,0xDD,0x02,
+0xFA,0x0D,0x02,0xDB,0xA8,0x57,0xA1,0xB0,0xCD,0x80,0xF3,0x7B,0xC9,0xE5,0xCD,0x02,
+0x03,0xE3,0xC5,0xCD,0xFD,0x01,0x18,0x1B,0xD5,0xCD,0xDD,0x02,0xFA,0x28,0x02,0xD1,
+0xDB,0xA8,0x57,0xA1,0xB0,0xC3,0x85,0xF3,0xE3,0xE5,0xCD,0x02,0x03,0xD1,0xE3,0xC5,
+0xCD,0x18,0x02,0xC1,0xE3,0xF5,0x78,0xE6,0x3F,0xB1,0xD3,0xA8,0x7D,0x32,0xFF,0xFF,
+0x78,0xD3,0xA8,0xF1,0xE1,0xC9,0xE3,0xF5,0xD5,0x7E,0xF5,0xFD,0xE1,0x23,0x5E,0x23,
+0x56,0x23,0xD5,0xDD,0xE1,0xD1,0xF1,0xE3,0xD9,0x16,0xFC,0x18,0x08,0xD9,0x16,0xF3,
+0x18,0x03,0xD9,0x16,0xF0,0x08,0xF3,0x3A,0xC1,0xFC,0xA7,0xDB,0xA8,0xFA,0x76,0x02,
+0xF5,0xA2,0xD9,0xC3,0x8C,0xF3,0x47,0x3A,0xF8,0xFA,0xE6,0x03,0x20,0x06,0x7A,0xFE,
+0xF3,0xC2,0xC1,0x01,0x78,0xE6,0x3F,0xD3,0xA8,0x3A,0xFF,0xFF,0x2F,0x4F,0xA2,0x32,
+0xFF,0xFF,0x5F,0x78,0xD3,0xA8,0x7B,0x32,0xC5,0xFC,0x78,0xC5,0x21,0xA6,0x02,0xE5,
+0xF5,0xA2,0xD9,0xC3,0x8C,0xF3,0xF3,0xD9,0x08,0xC1,0x78,0xE6,0x3F,0xD3,0xA8,0x79,
+0x32,0xFF,0xFF,0x78,0xD3,0xA8,0x79,0x32,0xC5,0xFC,0x08,0xD9,0xC9,0xCD,0xDD,0x02,
+0xFA,0xCA,0x02,0xDB,0xA8,0xA1,0xB0,0xD3,0xA8,0xC9,0xE5,0xCD,0x02,0x03,0x4F,0x06,
+0x00,0x7D,0xA4,0xB2,0x21,0xC5,0xFC,0x09,0x77,0xE1,0x79,0x18,0xE0,0xF3,0xF5,0x7C,
+0x07,0x07,0xE6,0x03,0x5F,0x3E,0xC0,0x07,0x07,0x1D,0xF2,0xE7,0x02,0x5F,0x2F,0x4F,
+0xF1,0xF5,0xE6,0x03,0x3C,0x47,0x3E,0xAB,0xC6,0x55,0x10,0xFC,0x57,0xA3,0x47,0xF1,
+0xA7,0xC9,0xF5,0x7A,0xE6,0xC0,0x4F,0xF1,0xF5,0x57,0xDB,0xA8,0x47,0xE6,0x3F,0xB1,
+0xD3,0xA8,0x7A,0x0F,0x0F,0xE6,0x03,0x57,0x3E,0xAB,0xC6,0x55,0x15,0xF2,0x1A,0x03,
+0xA3,0x57,0x7B,0x2F,0x67,0x3A,0xFF,0xFF,0x2F,0x6F,0xA4,0xB2,0x32,0xFF,0xFF,0x78,
+0xD3,0xA8,0xF1,0xE6,0x03,0xC9,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,
+0x31,0x39,0x38,0x38,0x20,0x62,0x79,0x20,0x41,0x53,0x43,0x49,0x49,0x20,0x63,0x6F,
+0x72,0x70,0x6F,0x72,0x61,0x74,0x69,0x6F,0x6E,0x00,0x21,0x5A,0x2C,0x11,0xDF,0xF3,
+0x01,0x08,0x00,0xED,0xB0,0x11,0xE7,0xFF,0x0E,0x10,0xED,0xB0,0x11,0xF9,0xFF,0x0E,
+0x04,0xED,0xB0,0xAF,0x32,0xF5,0xFA,0x32,0xF6,0xFA,0xCD,0x8E,0x05,0x32,0xF8,0xFA,
+0x67,0x2E,0xF7,0x22,0xFD,0xFE,0x21,0x94,0x3B,0x22,0xFF,0xFE,0x3A,0xC1,0xFC,0x32,
+0xF7,0xFF,0x21,0xFC,0xFA,0xCB,0x8E,0xCB,0xD6,0x3A,0x20,0xFB,0xCB,0x47,0x20,0x12,
+0xF6,0x01,0x32,0x20,0xFB,0x21,0xCA,0xFF,0x11,0xCB,0xFF,0x01,0x0E,0x00,0x36,0xC9,
+0xED,0xB0,0x3E,0x2C,0x32,0xFF,0xFA,0x3E,0x26,0x32,0x01,0xFB,0x3E,0xD3,0xD3,0xF7,
+0x32,0xF7,0xFA,0xAF,0xD3,0xF5,0x0E,0xFF,0xD3,0xD8,0x3E,0x02,0xD3,0xD9,0x21,0x86,
+0x05,0x06,0x08,0xDB,0xD9,0xBE,0x20,0x05,0x23,0x10,0xF8,0xCB,0x81,0xCD,0xE6,0x04,
+0x20,0x02,0xCB,0x89,0xDB,0xC0,0xFE,0xFF,0x28,0x02,0xCB,0x91,0xDB,0xF7,0xE6,0x77,
+0xFE,0x77,0x28,0x02,0xCB,0x99,0xDB,0xC8,0xFE,0xFF,0x28,0x02,0xCB,0xA1,0xAF,0xD3,
+0x81,0xF5,0xF1,0xD3,0x81,0xF5,0xF1,0xD3,0x81,0xF5,0xF1,0x3E,0x40,0xD3,0x81,0xE3,
+0xE3,0xDB,0x81,0xE6,0x3F,0xFE,0x05,0x20,0x02,0xCB,0xA9,0xDB,0xBB,0xFE,0xFF,0x28,
+0x02,0xCB,0xB1,0x79,0xD3,0xF5,0xCD,0xE6,0x04,0x20,0x05,0x21,0xFC,0xFA,0xCB,0xF6,
+0xCD,0x85,0x1C,0x06,0x00,0xCD,0x60,0x1C,0xFE,0x0A,0x28,0x03,0xCD,0x97,0x04,0xCD,
+0x85,0x1C,0x06,0x03,0xCD,0x60,0x1C,0xE6,0x01,0xF5,0xCD,0x69,0x1C,0xC1,0xFE,0x51,
+0xD2,0x3C,0x04,0xB7,0xCA,0x3C,0x04,0x05,0x20,0x05,0xFE,0x21,0xD2,0x3C,0x04,0xCD,
+0x85,0x1C,0x06,0x01,0xCD,0x60,0x1C,0x57,0xCD,0x60,0x1C,0x5F,0xCD,0xE0,0x18,0xCD,
+0x69,0x27,0x07,0x38,0x0B,0xCD,0xE1,0x05,0xE5,0xCD,0xAA,0x05,0xE1,0xCD,0x76,0x2C,
+0x3E,0x80,0xCD,0x6F,0x27,0xCD,0x7D,0x06,0xAF,0x6F,0x67,0x01,0x00,0x40,0xCD,0x08,
+0x0A,0xCD,0xAA,0x0A,0xC3,0x41,0x10,0x21,0x7B,0x05,0x0E,0x02,0x06,0x0D,0x3E,0x04,
+0x91,0xCD,0x4A,0x1B,0x06,0x0D,0x3E,0x0D,0x90,0xD3,0xB4,0x7E,0x23,0xFE,0xFF,0x20,
+0x02,0x2B,0xAF,0xD3,0xB5,0x10,0xEF,0x0D,0x20,0xE2,0x06,0x0D,0x3E,0x08,0xCD,0x4A,
+0x1B,0xAF,0xCD,0x4A,0x1B,0x3E,0x0D,0xCD,0x4A,0x1B,0x3E,0x01,0xCD,0x87,0x1C,0x06,
+0x0A,0x3E,0x01,0xC3,0x4A,0x1B,0x37,0xCD,0xFD,0x04,0x21,0xF2,0x7E,0xCD,0x0C,0x28,
+0x21,0xE4,0x7E,0xC3,0x0C,0x28,0xC5,0x3E,0x3E,0xD3,0xDA,0x3E,0x35,0xD3,0xDB,0x01,
+0x00,0x08,0xDB,0xDB,0x81,0x4F,0x10,0xFA,0xFE,0x95,0xC1,0xC9,0xAF,0xF5,0xCD,0x85,
+0x1C,0x06,0x03,0xCD,0x60,0x1C,0x4F,0xE6,0x01,0xD1,0xF5,0xD5,0xC5,0x79,0x07,0x07,
+0xE6,0x08,0x4F,0x3A,0xE8,0xFF,0xE6,0xF7,0xB1,0x47,0x0E,0x09,0xCD,0x88,0x06,0xC1,
+0xCD,0x69,0x1C,0x5F,0xF1,0xD5,0xF5,0xCD,0x60,0x1C,0x32,0xE9,0xF3,0x32,0xF2,0xF3,
+0xCD,0x60,0x1C,0x32,0xEA,0xF3,0xCD,0x60,0x1C,0x32,0xEB,0xF3,0xCD,0x60,0x1C,0x4F,
+0xCB,0x09,0x9F,0x47,0xF1,0x30,0x01,0x78,0x32,0xDE,0xF3,0xCB,0x09,0x9F,0x32,0xDB,
+0xF3,0xCB,0x49,0xC5,0x01,0x05,0x00,0x21,0xFC,0xF3,0x28,0x03,0x21,0x01,0xF4,0x11,
+0x06,0xF4,0xED,0xB0,0xC1,0xCB,0x09,0x9F,0x32,0x17,0xF4,0xD1,0xF1,0x32,0xB0,0xFC,
+0x32,0xAF,0xFC,0xD5,0xCD,0x4F,0x0A,0xD1,0xC3,0x4A,0x20,0x0A,0x00,0x00,0x01,0x0D,
+0x01,0x0F,0x04,0x07,0x03,0xFF,0x00,0x40,0x20,0x10,0x08,0x04,0x02,0x01,0xC5,0xE5,
+0xDB,0xA8,0xE6,0x03,0x4F,0x06,0x00,0x21,0xC1,0xFC,0x09,0xB6,0x4F,0x23,0x23,0x23,
+0x23,0x7E,0xE6,0x03,0x07,0x07,0xB1,0xE1,0xC1,0xC9,0x21,0xC1,0xFC,0x06,0x00,0x4E,
+0x79,0xB0,0xCD,0xCD,0x05,0xCB,0x79,0x28,0x08,0x79,0xC6,0x04,0x4F,0xCB,0x61,0x28,
+0xEF,0x23,0x04,0x78,0xFE,0x04,0x38,0xE7,0xAF,0x32,0x10,0xC0,0xC9,0xC5,0xE5,0x21,
+0x00,0x40,0x5D,0xF5,0xCD,0x93,0x27,0xF1,0x26,0x80,0x5D,0xCD,0x93,0x27,0xE1,0xC1,
+0xC9,0x21,0x00,0x00,0x11,0xC1,0xFC,0x06,0x00,0x1A,0x4F,0x79,0xB0,0xCD,0x0E,0x06,
+0xCB,0x79,0x28,0x08,0x79,0xC6,0x04,0x4F,0xCB,0x61,0x28,0xEF,0x13,0x04,0x78,0xFE,
+0x04,0x38,0xE6,0xE5,0x26,0x40,0x3A,0xC1,0xFC,0xCD,0xBD,0x02,0xE1,0xC9,0xC5,0xD5,
+0xE5,0x26,0x40,0xCD,0xBD,0x02,0xCD,0x27,0x06,0xE1,0x38,0x08,0x4F,0x06,0x00,0xA7,
+0x20,0x01,0x04,0x09,0xD1,0xC1,0xC9,0x21,0x00,0x40,0xAF,0xD3,0xFD,0x36,0xAA,0x3C,
+0xD3,0xFD,0x36,0x55,0x3D,0xD3,0xFD,0x7E,0xFE,0xAA,0x37,0x20,0x1B,0x06,0x00,0x78,
+0xD3,0xFD,0x36,0xAA,0x04,0x20,0xF8,0x78,0xD3,0xFD,0x04,0x7E,0xFE,0xAA,0x20,0x06,
+0x3E,0x55,0x77,0xBE,0x28,0xF1,0x05,0xA7,0x3E,0x02,0xD3,0xFD,0x78,0xC9,0x32,0xDE,
+0xF3,0x3A,0xAF,0xFC,0xFE,0x02,0xC9,0x3A,0xAF,0xFC,0xFE,0x04,0xC9,0x3A,0xAF,0xFC,
+0xFE,0x05,0xC9,0xCD,0xD6,0x10,0x3A,0xE0,0xF3,0xF6,0x60,0x18,0x08,0xCD,0xD6,0x10,
+0x3A,0xE0,0xF3,0xE6,0x3F,0x0E,0x01,0x47,0xED,0x57,0xF5,0xE5,0x79,0xA7,0x20,0x31,
+0x78,0x21,0xDF,0xF3,0xAE,0xE6,0x01,0x28,0x28,0x21,0xE8,0xFF,0x7E,0xE6,0xCF,0x77,
+0x78,0xE6,0x01,0x0F,0x0F,0x0F,0x0F,0xB6,0xC5,0x47,0x0E,0x09,0x21,0xF7,0xFA,0x7E,
+0xE6,0x3F,0x77,0x78,0x07,0x07,0x2F,0xE6,0xC0,0xB6,0xD3,0xF7,0x77,0xCD,0x88,0x06,
+0xC1,0x78,0xF3,0xD3,0x99,0x79,0xF6,0x80,0xD3,0x99,0xC5,0xD5,0x50,0x79,0x06,0x00,
+0xFE,0x08,0x21,0xDF,0xF3,0x38,0x10,0xFE,0x18,0x21,0xDF,0xFF,0x38,0x09,0x28,0x09,
+0xFE,0x1C,0x30,0x05,0x21,0xE1,0xFF,0x09,0x72,0xCD,0xF3,0x06,0xD1,0xC1,0xE1,0xF1,
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+0x38,0xCD,0x7A,0x38,0xDD,0x21,0x00,0x01,0x06,0x20,0xCD,0x5B,0x3A,0x3A,0x18,0xFC,
+0xA7,0x28,0x0C,0x11,0x10,0x00,0xDD,0x19,0x10,0xF0,0x1E,0x43,0xC3,0x88,0x3B,0x1E,
+0x02,0xCD,0x59,0x3B,0x21,0x18,0xFC,0x06,0x10,0x77,0x23,0x10,0xFC,0x3D,0x32,0x25,
+0xFC,0xC3,0xE7,0x38,0xF1,0xC2,0x62,0x27,0xB7,0xC2,0x3E,0x27,0xCD,0x59,0x3B,0x2A,
+0x26,0xFC,0xFD,0x74,0x05,0xFD,0x75,0x06,0x6F,0x22,0x26,0xFC,0xCD,0x14,0x39,0x3A,
+0x23,0xFC,0xA7,0xC8,0x3A,0x24,0xFC,0xFD,0x77,0x07,0xC3,0xD4,0x3A,0xCD,0x52,0x3A,
+0xAF,0x32,0x25,0xFC,0xCD,0x5C,0x3A,0x7E,0xFE,0x01,0xC8,0xE5,0xFD,0xE1,0xFD,0x7E,
+0x06,0xA7,0xC8,0xCD,0xD5,0x3A,0x2A,0x26,0xFC,0xFD,0x6E,0x06,0x22,0x26,0xFC,0x18,
+0x5C,0xE5,0xFD,0xE1,0xFD,0x7E,0x06,0xA7,0x20,0x36,0xE5,0xC5,0xCD,0x52,0x3A,0x01,
+0x01,0x7D,0xCD,0x6E,0x3A,0x28,0x08,0x0C,0x10,0xF8,0x1E,0x42,0xC3,0x88,0x3B,0x3A,
+0x23,0xFC,0xA7,0x79,0x20,0x03,0x32,0x23,0xFC,0xFD,0x4E,0x07,0xC4,0x6F,0x3A,0x32,
+0x24,0xFC,0xFD,0x77,0x07,0x4F,0x3E,0xFF,0xCD,0x6F,0x3A,0xCD,0x5C,0x3A,0xC1,0xE1,
+0x11,0x09,0x00,0x19,0xFD,0x5E,0x06,0x19,0x71,0xFD,0x34,0x06,0xC0,0xCD,0xD5,0x3A,
+0xFD,0x34,0x05,0xFD,0xE5,0xE1,0xCD,0x52,0x3A,0x21,0x27,0xFC,0x34,0x18,0x5D,0xE5,
+0xE5,0xFD,0xE1,0xCD,0x52,0x3A,0xFD,0x6E,0x06,0xFD,0x66,0x05,0xED,0x5B,0x26,0xFC,
+0xE7,0xE1,0x3F,0xD8,0xFD,0x7E,0x03,0xA7,0xFD,0x36,0x03,0x00,0xC0,0xFD,0x7E,0x06,
+0xA7,0x28,0x0F,0x01,0x09,0x00,0x09,0x4F,0x09,0x7E,0xFD,0x34,0x06,0xC0,0xFD,0x34,
+0x05,0xC9,0xFD,0x7E,0x07,0xA7,0x4F,0x3A,0x23,0xFC,0xC4,0x6E,0x3A,0xFD,0x77,0x07,
+0xCD,0xD4,0x3A,0xFD,0x7E,0x09,0xFD,0x34,0x06,0xA7,0xC9,0xE5,0xFD,0xE1,0xFD,0x71,
+0x03,0xC9,0x23,0x4E,0x23,0x46,0xC5,0xDD,0xE1,0x2B,0x2B,0xF6,0x37,0xE5,0xD5,0xC5,
+0xDD,0xE5,0xE1,0x11,0x18,0xFC,0x30,0x01,0xEB,0x01,0x10,0x00,0x18,0x17,0xF6,0x37,
+0xE5,0xD5,0xC5,0xF5,0x21,0x7F,0x00,0x06,0x00,0x09,0x11,0x28,0xFC,0xF1,0x30,0x02,
+0xEB,0x77,0x01,0x01,0x00,0xCD,0xED,0x3A,0xC1,0xD1,0xE1,0x3A,0x28,0xFC,0xA7,0xC9,
+0xE5,0xD5,0x11,0x66,0xF8,0x06,0x0B,0x1A,0xFE,0x61,0x38,0x07,0xFE,0x7B,0x30,0x03,
+0xE6,0xDF,0x12,0x13,0x10,0xF1,0xDD,0x21,0x00,0x01,0x0E,0x20,0xCD,0x5B,0x3A,0x21,
+0x18,0xFC,0x7E,0xA7,0x20,0x0B,0x11,0x10,0x00,0xDD,0x19,0x0D,0x20,0xEE,0x0C,0x18,
+0x0D,0x11,0x66,0xF8,0x06,0x0B,0x1A,0xBE,0x20,0xEC,0x13,0x23,0x10,0xF8,0xD1,0xE1,
+0x3A,0x25,0xFC,0xC9,0xF6,0x37,0xF5,0xFD,0xE5,0xE1,0x01,0x09,0x00,0x09,0x1E,0x00,
+0xFD,0x7E,0x07,0xC6,0x02,0x57,0xF1,0x38,0x01,0xEB,0x01,0x00,0x01,0x7C,0xA7,0xF2,
+0xF3,0x3A,0x7A,0xFE,0x40,0xD9,0x21,0xFF,0xFF,0x3A,0x09,0xFD,0x57,0x38,0x3B,0x0F,
+0x0F,0xE6,0xC0,0x4F,0x0F,0x0F,0x0F,0x0F,0xB1,0x4F,0xDB,0xA8,0x47,0xE6,0x33,0xB1,
+0x5F,0xF3,0xD3,0xA8,0x7A,0xE6,0x0C,0x57,0x7E,0x2F,0x4F,0xE6,0xF3,0xB2,0x77,0x7B,
+0xE6,0x3F,0x57,0x78,0xE6,0xC0,0xB2,0xFB,0xD3,0xA8,0xD9,0xED,0xB0,0xD9,0x7B,0xF3,
+0xD3,0xA8,0x79,0x77,0x78,0xFB,0xD3,0xA8,0xD9,0xC9,0x0F,0x0F,0xE6,0xC0,0x4F,0x7A,
+0xE6,0x03,0xB1,0x4F,0xDB,0xA8,0x47,0xE6,0x3C,0xB1,0x5F,0x7A,0x0F,0x0F,0xE6,0x03,
+0x57,0x7B,0xF3,0xCD,0xD7,0x51,0xFB,0xD9,0xC9,0xE5,0xFD,0xE1,0xDD,0xE5,0xC1,0xFD,
+0x71,0x01,0xFD,0x70,0x02,0xAF,0xFD,0x77,0x03,0xFD,0x77,0x05,0xFD,0x77,0x06,0x22,
+0x64,0xF8,0x73,0xC9,0xCD,0x90,0x3A,0xC2,0x62,0x27,0xA7,0xC8,0x1E,0x40,0x18,0x08,
+0x3A,0x09,0xFD,0xCB,0x77,0xC0,0x1E,0x46,0xAF,0x32,0x7C,0xF8,0xD5,0xCD,0xD6,0x27,
+0xD1,0xC3,0xDC,0x27,0x01,0xB7,0x3B,0x0A,0x03,0xB7,0xC8,0x93,0x28,0x04,0x03,0x03,
+0x18,0xF5,0x69,0x60,0x5E,0x23,0x56,0x21,0x5E,0xF5,0xE5,0x77,0x13,0x23,0x1A,0x77,
+0xB7,0x20,0xF9,0xE1,0x1E,0x01,0xC9,0x3D,0xC9,0x3B,0x40,0xD7,0x3B,0x41,0xE7,0x3B,
+0x42,0xFB,0x3B,0x43,0x09,0x3C,0x46,0x18,0x3C,0x00,0x42,0x61,0x64,0x20,0x66,0x69,
+0x6C,0x65,0x20,0x6D,0x6F,0x64,0x65,0x00,0x46,0x69,0x6C,0x65,0x20,0x73,0x74,0x69,
+0x6C,0x6C,0x20,0x6F,0x70,0x65,0x6E,0x00,0x46,0x69,0x6C,0x65,0x20,0x61,0x6C,0x72,
+0x65,0x61,0x64,0x79,0x20,0x65,0x78,0x69,0x73,0x74,0x73,0x00,0x52,0x41,0x4D,0x20,
+0x64,0x69,0x73,0x6B,0x20,0x66,0x75,0x6C,0x6C,0x00,0x54,0x6F,0x6F,0x20,0x6D,0x61,
+0x6E,0x79,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x52,0x41,0x4D,0x20,0x64,0x69,0x73,
+0x6B,0x20,0x6F,0x66,0x66,0x6C,0x69,0x6E,0x65,0x00,0x21,0xAD,0xFC,0x34,0x35,0x06,
+0x08,0x11,0xD1,0x3E,0x21,0xC1,0x3E,0x28,0x03,0x21,0xC9,0x3E,0xBE,0x28,0x0A,0x23,
+0x13,0x10,0xF9,0xCD,0x54,0x3E,0xC3,0x4A,0x3D,0x1A,0x18,0xF7,0xF5,0xCD,0x6A,0x3E,
+0xF1,0x28,0x05,0x21,0xFC,0xFA,0xCB,0x46,0xCA,0x54,0x3E,0xFE,0x41,0x38,0xCB,0xFE,
+0x5B,0x38,0x0C,0xFE,0x61,0x38,0xC3,0xFE,0x7B,0x30,0xBF,0xCB,0xBE,0x18,0x02,0xCB,
+0xFE,0xFE,0x61,0x38,0x02,0xD6,0x20,0x57,0xFE,0x58,0x28,0x1C,0x3A,0xF9,0xFA,0xB7,
+0x20,0x1B,0x7A,0xCD,0xB2,0x3D,0x7A,0xC2,0x39,0x3E,0xCD,0xA3,0x3D,0xFE,0x80,0xD0,
+0x7A,0x32,0xFA,0xFA,0x3E,0x01,0x18,0x40,0x3E,0xB0,0xC3,0x43,0x3C,0x3D,0x7A,0x20,
+0x39,0x5F,0xCD,0xB2,0x3D,0x3A,0xFA,0xFA,0x28,0x05,0xCD,0xC0,0x3D,0x18,0x0C,0xBB,
+0x20,0x10,0xFE,0x4E,0x20,0x08,0x3E,0xFD,0xCD,0x3F,0x3E,0xC3,0x4A,0x3D,0x3E,0x8F,
+0x18,0x0E,0xFE,0x4E,0x7B,0x20,0x0C,0xFE,0x59,0x28,0x08,0x32,0xFA,0xFA,0x3E,0xFD,
+0xC3,0x3F,0x3E,0x32,0xFB,0xFA,0x3E,0x02,0x18,0x71,0x21,0xFA,0xFA,0x56,0x23,0x46,
+0x4F,0xC5,0xCD,0xB2,0x3D,0xC1,0x20,0x0D,0x78,0x32,0xFA,0xFA,0x3E,0x01,0x32,0xF9,
+0xFA,0x79,0xC3,0xA1,0x3C,0x78,0xFE,0x59,0x20,0x26,0x7A,0xFE,0x43,0x28,0x14,0xFE,
+0x4C,0x28,0x41,0xFE,0x46,0x28,0x15,0xFE,0x57,0x28,0x6A,0x1E,0x49,0xC5,0xCD,0xC0,
+0x3D,0x18,0x06,0x3E,0xE1,0xC5,0xCD,0x3F,0x3E,0xC1,0x18,0x28,0x3E,0xEC,0x18,0xF5,
+0x78,0xFE,0x48,0x20,0x3A,0x7A,0xFE,0x43,0x28,0x10,0xFE,0x44,0x28,0x21,0xFE,0x54,
+0x28,0x26,0xFE,0x53,0x20,0x3F,0x3E,0x9C,0x18,0x02,0x3E,0xE1,0xCD,0x3F,0x3E,0x79,
+0xFE,0x49,0x28,0x06,0x3E,0x4A,0x59,0xCD,0x3C,0x3E,0xAF,0x32,0xF9,0xFA,0xC9,0x3E,
+0xE3,0xCD,0x3F,0x3E,0x3E,0xDE,0x18,0x02,0x3E,0xE3,0xCD,0x3F,0x3E,0x18,0xE5,0x7A,
+0xFE,0x54,0x20,0x11,0x78,0xFE,0x53,0x20,0x0C,0x79,0xFE,0x55,0x20,0x07,0x3E,0xE2,
+0xCD,0x3F,0x3E,0x18,0xD5,0x78,0x59,0xCD,0xC0,0x3D,0x18,0xCE,0xCD,0xAC,0x3D,0x47,
+0x87,0x87,0x80,0x57,0x7B,0xCD,0xB2,0x3D,0x82,0x6F,0x7A,0xFE,0x0F,0x30,0x04,0x7D,
+0xD6,0x70,0xC9,0xFE,0x23,0x30,0x04,0x7D,0xD6,0x30,0xC9,0x7D,0xD6,0x23,0x01,0xF4,
+0x3E,0x18,0x03,0x01,0x99,0x3E,0x6F,0x26,0x00,0x09,0x7E,0xC9,0xCD,0xA3,0x3D,0xE6,
+0x0F,0xC9,0xCD,0xA3,0x3D,0xD6,0x14,0xFE,0x01,0x38,0x03,0xFE,0x06,0xD8,0xAF,0xC9,
+0x57,0xCD,0xA3,0x3D,0xFE,0x0B,0x30,0x03,0x7A,0x18,0x42,0xFE,0x21,0x38,0x0C,0xFE,
+0x26,0x30,0x08,0x7A,0xCD,0x3C,0x3E,0x3E,0xDE,0x18,0x64,0x7A,0xFE,0x50,0x20,0x0A,
+0x3E,0x48,0xCD,0x3C,0x3E,0x3E,0xDF,0xC3,0x3F,0x3E,0xFE,0x4A,0x20,0x0E,0x3E,0x9C,
+0xD5,0xCD,0x3F,0x3E,0xCD,0xD7,0x3D,0xD1,0x4B,0xC3,0x3F,0x3D,0xFE,0x46,0x20,0x0F,
+0x3E,0xEC,0xD5,0xCD,0x3F,0x3E,0xD1,0x7B,0xFE,0x55,0xC8,0x3E,0x4C,0x18,0x2D,0xFE,
+0x59,0x20,0x06,0xCD,0x3C,0x3E,0x7B,0x18,0x0C,0xFE,0x57,0x20,0x0D,0xCD,0x3C,0x3E,
+0x7B,0xFE,0x49,0x28,0xE6,0xFE,0x45,0xC0,0x18,0xE1,0xFE,0x56,0x20,0x0C,0x3E,0x55,
+0xD5,0xCD,0x39,0x3E,0xCD,0xD7,0x3D,0x18,0xCD,0x5F,0x3E,0x51,0xCD,0x7C,0x3D,0x21,
+0xFC,0xFA,0xCB,0x7E,0x28,0x0E,0xFE,0xE0,0x38,0x04,0xD6,0x20,0x18,0x06,0xFE,0xA0,
+0x30,0x02,0xC6,0x20,0x2A,0xF8,0xF3,0x77,0x23,0x7D,0xFE,0x18,0x20,0x03,0x21,0xF0,
+0xFB,0x3A,0xFA,0xF3,0xBD,0xC8,0x22,0xF8,0xF3,0xC9,0x3A,0xDB,0xF3,0xA7,0xC8,0x3A,
+0xD9,0xFB,0xA7,0xC0,0x3E,0x0F,0x32,0xD9,0xFB,0xF3,0xD3,0xAB,0x3E,0x0A,0x3D,0x20,
+0xFD,0x3E,0x0E,0xD3,0xAB,0xFB,0xC9,0x21,0xFC,0xFA,0xCB,0x46,0x28,0x05,0xCB,0x86,
+0xAF,0x18,0x19,0x3A,0xAC,0xFC,0x3C,0x28,0x10,0x3A,0xEB,0xFB,0x0F,0x38,0x08,0xAF,
+0x32,0xF9,0xFA,0xCB,0xC6,0x18,0x05,0x3E,0xFF,0x32,0xAC,0xFC,0xF5,0x3E,0x0F,0xD3,
+0xA0,0xDB,0xA2,0xE6,0x7F,0x47,0xF1,0xB7,0x3E,0x80,0x28,0x01,0xAF,0xB0,0xD3,0xA1,
+0xC9,0x2A,0x3A,0x5D,0x5F,0x3F,0x3E,0x7B,0x7D,0x5C,0x40,0x3E,0x3F,0x5B,0x3C,0x7B,
+0x7D,0xB0,0xDE,0xA1,0xA5,0xDF,0xA4,0xA2,0xA3,0x0A,0x15,0x25,0x28,0x23,0x18,0x40,
+0x21,0x05,0x16,0x4B,0x01,0x0A,0x06,0x04,0x19,0x28,0x80,0x08,0x02,0x03,0x17,0x40,
+0x49,0x8C,0x47,0x22,0xFD,0xF4,0x92,0xF5,0x92,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,
+0x93,0x93,0x93,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x88,0x8D,0x8A,0x8E,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
diff --git a/MCUME_pico2/picomsx/bios/painter.h b/MCUME_pico2/picomsx/bios/painter.h
new file mode 100644
index 0000000..da85636
--- /dev/null
+++ b/MCUME_pico2/picomsx/bios/painter.h
@@ -0,0 +1,4098 @@
+static const uint8_t PAINTER[65536] = {
+0xF3,0xF7,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC3,0x46,0x02,0xFF,
+0xC3,0x89,0x00,0x00,0xC3,0x61,0x02,0x00,0xC3,0x3A,0x3F,0x00,0xC3,0xA1,0x02,0x00,
+0xC3,0x4F,0x3F,0x00,0xC3,0x61,0x03,0x00,0xC3,0x5B,0x3F,0x00,0xC3,0xB3,0x39,0x00,
+0xC3,0x8F,0x02,0x00,0xC3,0xF5,0x01,0x00,0xC3,0xDA,0x03,0xC3,0xFB,0x3B,0xC3,0xC2,
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+0x98,0x00,0x01,0x18,0x8A,0x08,0x07,0xE2,0x0C,0x22,0x04,0x02,0x07,0x01,0xC1,0x07,
+0x84,0x18,0x70,0x4C,0x43,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x21,0xE6,0x60,0x00,0x1E,0x04,0x10,
+0x00,0x00,0x00,0x10,0x00,0x00,0x03,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x00,0x1C,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x20,0x00,0x0C,
+0x20,0x0A,0x0C,0x20,0x14,0x0C,0x20,0x1E,0x0C,0x20,0x28,0x0C,0x20,0x32,0x0A,0x20,
+0x3C,0x09,0x20,0x44,0x08,0x20,0x4B,0x07,0x20,0x51,0x08,0x20,0x56,0x09,0x20,0x5C,
+0x0B,0x20,0x63,0x0A,0x20,0x6C,0x08,0x20,0x74,0x0A,0x20,0x7A,0x0A,0x00,0x82,0x0B,
+0x20,0x82,0x0B,0x20,0x8B,0x08,0x20,0x94,0x0B,0x20,0x9A,0x0D,0x20,0xA3,0x0E,0x20,
+0xAE,0x09,0x20,0xBA,0x07,0x20,0xC1,0x0C,0x20,0xC6,0x0A,0x20,0xD0,0x0A,0x20,0xD8,
+0x08,0x20,0xE0,0x0D,0x20,0xE6,0x0D,0x20,0xF1,0x0B,0x20,0xFC,0x0A,0x01,0x05,0x06,
+0x01,0x05,0x08,0x41,0x09,0x08,0x21,0x0E,0x04,0x21,0x13,0x04,0x21,0x15,0x0B,0x21,
+0x17,0x0A,0x21,0x20,0x07,0x21,0x28,0x08,0x21,0x2D,0x0A,0x21,0x33,0x09,0x21,0x3B,
+0x0B,0x21,0x42,0x0A,0x21,0x4B,0x08,0x21,0x53,0x09,0x21,0x59,0x0C,0x21,0x60,0x0B,
+0x21,0x6A,0x09,0x21,0x73,0x0B,0x21,0x7A,0x0C,0x21,0x83,0x0B,0x21,0x8D,0x0A,0x21,
+0x96,0x0B,0x21,0x9E,0x0A,0x21,0xA7,0x0C,0x21,0xAF,0x0A,0x21,0xB9,0x0D,0x21,0xC1,
+0x0A,0x21,0xCC,0x0C,0x21,0xD4,0x0D,0x21,0xDE,0x0B,0x21,0xE9,0x0B,0x21,0xF2,0x0C,
+0x21,0xFB,0x0B,0x22,0x05,0x0C,0x22,0x0E,0x06,0x22,0x18,0x0C,0x22,0x1C,0x0C,0x22,
+0x26,0x0A,0x22,0x30,0x0A,0x22,0x38,0x09,0x22,0x40,0x0E,0x22,0x47,0x09,0x22,0x53,
+0x0B,0x22,0x5A,0x0E,0x22,0x63,0x0B,0x22,0x6F,0x0D,0x22,0x78,0x07,0x22,0x83,0x0C,
+0x22,0x88,0x0A,0x22,0x92,0x0B,0x22,0x99,0x0C,0x22,0xA2,0x0D,0x22,0xAD,0x0A,0x22,
+0xB8,0x0A,0x22,0xC0,0x09,0x22,0xC8,0x0D,0x22,0xCF,0x0A,0x22,0xDA,0x0B,0x22,0xE2,
+0x0C,0x22,0xEB,0x0B,0x22,0xF5,0x05,0x02,0xFE,0x05,0x03,0x02,0x0C,0x23,0x06,0x0C,
+0x23,0x10,0x0D,0x23,0x1A,0x0C,0x23,0x25,0x09,0x23,0x2F,0x0C,0x23,0x36,0x0C,0x23,
+0x40,0x0E,0x23,0x4A,0x0D,0x23,0x56,0x0C,0x23,0x61,0x0C,0x23,0x6B,0x0C,0x23,0x75,
+0x0D,0x23,0x7F,0x0E,0x23,0x8A,0x0C,0x23,0x96,0x09,0x23,0xA0,0x0D,0x23,0xA7,0x0D,
+0x23,0xB2,0x0D,0x23,0xBD,0x09,0x23,0xC8,0x0D,0x23,0xCF,0x0C,0x23,0xDA,0x0A,0x23,
+0xE4,0x0A,0x23,0xEC,0x08,0x23,0xF4,0x0B,0x23,0xFA,0x0D,0x24,0x03,0x0B,0x24,0x0E,
+0x0C,0x24,0x17,0x0B,0x24,0x21,0x00,0x04,0x2A,0xF3,0xCD,0x60,0x54,0x58,0xCB,0x22,
+0x00,0xC2,0x3E,0xC9,0xCD,0x70,0x3F,0x11,0xC0,0xD2,0x00,0xCD,0x98,0xCA,0xC3,0xF1,
+0xCA,0xEF,0xE2,0xFF,0xEB,0xE7,0x37,0x00,0xD5,0x01,0x13,0x00,0xED,0xB0,0xAF,0x12,
+0x13,0x3A,0x25,0xFA,0xFE,0x0B,0x21,0xA0,0x02,0x30,0x0B,0x2E,0x00,0xCB,0x3F,0xCB,
+0x1D,0xCB,0x3F,0xCB,0x1D,0x67,0xEB,0x73,0x23,0x72,0x23,0xEB,0xE7,0x23,0x00,0x01,
+0x08,0x00,0xED,0xB0,0xAF,0x5F,0x57,0xE1,0xCD,0x0D,0x5C,0xEF,0x1E,0x00,0xC9,0xF0,
+0x98,0x00,0x00,0xC8,0x02,0xB0,0x01,0x40,0x02,0x08,0x40,0x00,0xD4,0x00,0xCC,0xE0,
+0x8B,0x00,0x10,0x00,0x01,0x00,0xB0,0x01,0xA2,0x01,0xE7,0x3F,0x00,0x11,0x9A,0xFD,
+0x01,0x03,0x00,0xED,0xB0,0x11,0x2E,0xC2,0x01,0x1A,0x00,0xED,0xB0,0xE5,0xD5,0x2A,
+0x00,0xC2,0x01,0x06,0x00,0xA7,0xED,0x42,0xEB,0x2B,0x72,0x2B,0x73,0xD1,0xE1,0x01,
+0x05,0x00,0xED,0xB0,0xE5,0x21,0x9F,0xFD,0xE5,0x01,0x05,0x00,0xED,0xB0,0xD1,0xE1,
+0x01,0x03,0x00,0xED,0xB0,0x3A,0x00,0xC0,0x32,0x49,0xC2,0xC9,0xC3,0x2E,0xC2,0xE1,
+0xAF,0xD3,0x99,0x3E,0x8F,0xD3,0x99,0x00,0xDB,0x99,0xF5,0x3A,0xEE,0xFF,0x47,0x0E,
+0x0F,0xCD,0x47,0x00,0xF1,0xA7,0xC3,0x00,0x00,0xF7,0x00,0xA8,0x39,0xFB,0xC3,0x48,
+0xC2,0x2A,0x39,0x00,0x7E,0x23,0xFE,0xCD,0x20,0xFA,0x7E,0x23,0xFE,0x9F,0x20,0xF4,
+0x7E,0x23,0xFE,0xFD,0x20,0xEE,0xC9,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xD5,
+};
diff --git a/MCUME_pico2/picomsx/emucfg.h b/MCUME_pico2/picomsx/emucfg.h
new file mode 100644
index 0000000..d0ddea1
--- /dev/null
+++ b/MCUME_pico2/picomsx/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x1
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "      MSX Emulator      "
+#define ROMSDIR "msx"
+
+#define emu_Init(ROM) {msx_Init(); msx_Start(ROM);}
+#define emu_Step(x) {msx_Step();}
+#define emu_Input(x) {msx_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picomsx/fmsx.c b/MCUME_pico2/picomsx/fmsx.c
new file mode 100644
index 0000000..1aeb27f
--- /dev/null
+++ b/MCUME_pico2/picomsx/fmsx.c
@@ -0,0 +1,3508 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+
+#include "shared.h"
+#include "Z80.h"            /* Z80 CPU emulation             */
+#include "MSX.h"
+#include "Sound.h"
+#include <stdlib.h>
+#include <ctype.h>
+//#include <time.h>
+
+#include "bios/cmos.h"
+#include "bios/disk.h"
+#include "bios/fmpac.h"
+#include "bios/italic.h"
+#include "bios/kanji.h"
+#include "bios/msx.h"
+#include "bios/msx2.h"
+#include "bios/msx2ext.h"
+#include "bios/msx2p.h"
+#include "bios/msx2pext.h"
+#include "bios/painter.h"
+
+#include "flash_t.h"
+
+static void RefreshLineTx80(byte Y);
+static void RefreshLine0(byte Y);
+static void RefreshLine1(byte Y);
+static void RefreshLine2(byte Y);
+static void RefreshLine3(byte Y);
+static void RefreshLine4(byte Y);
+static void RefreshLine5(byte Y);
+static void RefreshLine6(byte Y);
+static void RefreshLine7(byte Y);
+static void RefreshLine8(byte Y);
+static void RefreshLine10(byte Y);
+static void RefreshLine12(byte Y);
+
+
+/** Zero-terminated arrays of disk names for each drive ******/
+extern char *Disks[2][MAXDISKS+1];
+
+
+/**************************************
+* Local macros/typedef
+**************************************/
+#define WIDTH  272
+#define HEIGHT 228
+
+#define RGB2INT(R,G,B) ((B)|((int)(G)<<8)|((int)(R)<<16))
+
+typedef byte pixel;
+
+
+/**************************************
+* Local procedures
+**************************************/
+static void  Sprites(byte Y,pixel *Line);
+static void  ColorSprites(byte Y,byte *ZBuf);
+static pixel *RefreshBorder(byte Y,pixel C);
+static void  ClearLine(pixel *P,pixel C);
+static pixel YJKColor(int Y,int J,int K);
+
+/** Internal Functions ***************************************/
+/** These functions are defined and internally used by the  **/
+/** code in MSX.c.                                          **/
+/*************************************************************/
+byte *LoadROM(const char *Name,int Size,byte *Buf);
+byte *LoadCARTROM(const char *Name,int Size,byte *Buf);
+int  LoadCart(const char *Name,int Slot);
+int  GuessROM(const byte *Buf,int Size);
+void SetMegaROM(int Slot,byte P0,byte P1,byte P2,byte P3);
+void MapROM(word A,byte V);       /* Switch MegaROM banks            */
+void SSlot(byte V);               /* Switch secondary slots          */
+void VDPOut(byte R,byte V);       /* Write value into a VDP register */
+void Printer(byte V);             /* Send a character to a printer   */
+void PPIOut(byte New,byte Old);   /* Set PPI bits (key click, etc.)  */
+void CheckSprites(void);          /* Check collisions and 5th sprite */
+byte RTCIn(byte R);               /* Read RTC registers              */
+byte SetScreen(void);             /* Change screen mode              */
+word SetIRQ(byte IRQ);            /* Set/Reset IRQ                   */
+word StateID(void);               /* Compute emulation state ID      */
+
+static void RefreshLineF(register byte Y);
+static void RefreshLine0(register byte Y);
+static void RefreshLine1(register byte Y);
+static void RefreshLine2(register byte Y);
+static void RefreshLine3(register byte Y);
+static void RefreshLine4(register byte Y);
+static void RefreshLine5(register byte Y);
+static void RefreshLine8(register byte Y);
+static void RefreshLine10(register byte Y);
+static void RefreshLine12(register byte Y);
+//#ifdef NARROW
+static void RefreshLine7(register byte Y);
+static void RefreshLineTx80(register byte Y);
+//#endif
+
+/**************************************
+* Local variables
+**************************************/
+static unsigned int BPal[256],XPal[80],XPal0; 
+
+static int FirstLine = 18;     /* First scanline in the framebuffer */
+
+/** User-defined parameters for fMSX *************************/
+byte Verbose     = 1;              /* Debug msgs ON/OFF      */
+byte UPeriod     = 2;              /* Interrupts/scr. update */
+int  VPeriod     = CPU_VPERIOD;    /* CPU cycles per VBlank  */
+int  HPeriod     = CPU_HPERIOD;    /* CPU cycles per HBlank  */
+byte SaveCMOS    = 0;              /* Save CMOS.ROM on exit  */
+byte SaveSRAM    = 0;              /* ~ GMASTER2.RAM on exit */
+byte MSXVersion  = 1;              /* 0=MSX1,1=MSX2,2=MSX2+  */
+byte JoyTypeA    = 1;              /* 0=None,1=Joystick,     */
+byte JoyTypeB    = 0;              /* 2=MouseAsJstk,3=Mouse  */
+byte ROMTypeA    = MAXMAPPERS;     /* MegaROM types          */
+byte ROMTypeB    = MAXMAPPERS;
+int  RAMPages    = 4;              /* Number of RAM pages    */
+int  VRAMPages   = 2;              /* Number of VRAM pages   */
+byte AutoFire    = 0;              /* Autofire on [SPACE]    */
+byte UseDrums    = 0;              /* Use drms for PSG noise */
+byte ExitNow     = 0;              /* 1 = Exit the emulator  */
+
+/** Main hardware: CPU, RAM, VRAM, mappers *******************/
+Z80 CPU;                           /* Z80 CPU state and regs */
+
+byte *VRAM,*VPAGE;                 /* Video RAM              */
+
+byte *RAM[8];                      /* Main RAM (8x8kB pages) */
+byte *EmptyRAM;                    /* Empty RAM page (8kB)   */
+byte *SRAM;                        /* SRAM (battery backed)  */
+byte *MemMap[4][4][8];   /* Memory maps [PPage][SPage][Addr] */
+
+byte *RAMData;                     /* RAM Mapper contents    */
+byte RAMMapper[4];                 /* RAM Mapper state       */
+byte RAMMask;                      /* RAM Mapper mask        */
+
+byte *ROMData[2];                  /* ROM Mapper contents    */
+byte ROMMapper[2][4];              /* ROM Mappers state      */
+byte ROMMask[2];                   /* ROM Mapper masks       */
+
+byte EnWrite[4];                   /* 1 if write enabled     */
+byte PSL[4],SSL[4];                /* Lists of current slots */
+byte PSLReg,SSLReg;      /* Storage for A8h port and (FFFFh) */
+
+/** Memory blocks to free in TrashMSX() **********************/
+byte *Chunks[256];                 /* Memory blocks to free  */
+byte CCount;                       /* Number of memory blcks */
+
+
+/** Cartridge files used by fMSX *****************************/
+char CartA[128]; //"CARTA.ROM";    /* Cartridge A ROM file   */
+char *CartB      = "CARTB.ROM";    /* Cartridge B ROM file   */
+
+/** Disk images used by fMSX *********************************/
+char *DiskA      = "DRIVEA.DSK";   /* Drive A disk image  */
+char *DiskB      = "DRIVEB.DSK";   /* Drive B disk image  */
+
+/** Fixed font used by fMSX **********************************/
+char *FontName   = "DEFAULT.FNT";  /* Font file for text     */
+byte *FontBuf;                     /* Font for text modes    */
+byte UseFont     = 0;              /* Use ext. font when 1   */
+
+/** Printer **************************************************/
+#ifdef unused
+char *PrnName    = NULL;           /* Printer redirect. file */
+int *PrnStream;
+#endif
+
+/** Cassette tape ********************************************/
+#ifdef unused
+char *CasName    = "DEFAULT.CAS";  /* Tape image file        */
+int *CasStream;
+#endif
+
+/** Serial port **********************************************/
+#ifdef unused
+char *ComName    = NULL;           /* Serial redirect. file  */
+int *ComIStream;
+int *ComOStream;
+#endif
+
+/** Kanji font ROM *******************************************/
+byte *Kanji;                       /* Kanji ROM 4096x32      */
+int  KanLetter;                    /* Current letter index   */
+byte KanCount;                     /* Byte count 0..31       */
+
+/** Keyboard and mouse ***************************************/
+byte KeyMap[16];                   /* Keyboard map           */
+byte Buttons[2];                   /* Mouse button states    */
+byte MouseDX[2],MouseDY[2];        /* Mouse offsets          */
+byte OldMouseX[2],OldMouseY[2];    /* Old mouse coordinates  */
+byte MCount[2];                    /* Mouse nibble counter   */
+
+/** General I/O registers: i8255 *****************************/
+I8255 PPI;                         /* i8255 PPI at A8h-ABh   */
+byte IOReg;                        /* Storage for AAh port   */
+
+/** Sound hardware: PSG, SCC, OPLL ***************************/
+AY8910 PSG;                        /* PSG registers & state  */
+YM2413 OPLL;                       /* OPLL registers & state */
+SCC  SCChip;                       /* SCC registers & state  */
+byte SCCOn[2];                     /* 1 = SCC page active    */
+
+/** Serial I/O hardware: i8251+i8253 *************************/
+I8251 SIO;                         /* SIO registers & state  */
+
+/** Real-time clock ******************************************/
+byte RTCReg,RTCMode;               /* RTC register numbers   */
+byte RTC[4][13];                   /* RTC registers          */
+
+/** Video processor ******************************************/
+byte *ChrGen,*ChrTab,*ColTab;      /* VDP tables (screen)    */
+byte *SprGen,*SprTab;              /* VDP tables (sprites)   */
+int  ChrGenM,ChrTabM,ColTabM;      /* VDP masks (screen)     */
+int  SprTabM;                      /* VDP masks (sprites)    */
+word VAddr;                        /* VRAM address in VDP    */
+byte VKey,PKey,WKey;               /* Status keys for VDP    */
+byte FGColor,BGColor;              /* Colors                 */
+byte XFGColor,XBGColor;            /* Second set of colors   */
+byte ScrMode;                      /* Current screen mode    */
+byte VDP[64],VDPStatus[16];        /* VDP registers          */
+byte IRQPending;                   /* Pending interrupts     */
+int  ScanLine;                     /* Current scanline       */
+byte VDPData;                      /* VDP data buffer        */
+byte PLatch;                       /* Palette buffer         */
+byte ALatch;                       /* Address buffer         */
+int  Palette[16];                  /* Current palette        */
+
+/** Places in DiskROM to be patched with ED FE C9 ************/
+const word DiskPatches[] = { 0x4010,0x4013,0x4016,0x401C,0x401F,0 };
+
+/** Places in BIOS to be patched with ED FE C9 ***************/
+const word BIOSPatches[] = { 0x00E1,0x00E4,0x00E7,0x00EA,0x00ED,0x00F0,0x00F3,0 };
+
+/** Screen Mode Handlers [number of screens + 1] *************/
+const void (*RefreshLine[MAXSCREEN+2])(byte Y) =
+{
+  RefreshLine0,   /* SCR 0:  TEXT 40x24  */
+  RefreshLine1,   /* SCR 1:  TEXT 32x24  */
+  RefreshLine2,   /* SCR 2:  BLK 256x192 */
+  RefreshLine3,   /* SCR 3:  64x48x16    */
+  RefreshLine4,   /* SCR 4:  BLK 256x192 */
+  RefreshLine5,   /* SCR 5:  256x192x16  */
+  RefreshLine6,   /* SCR 6:  512x192x4   */
+  RefreshLine7,   /* SCR 7:  512x192x16  */
+  RefreshLine8,   /* SCR 8:  256x192x256 */
+  0,              /* SCR 9:  NONE        */
+  RefreshLine10,  /* SCR 10: YAE 256x192 */
+  RefreshLine10,  /* SCR 11: YAE 256x192 */
+  RefreshLine12,  /* SCR 12: YJK 256x192 */
+  RefreshLineTx80 /* SCR 0:  TEXT 80x24  */
+};
+
+/** VDP Address Register Masks *******************************/
+const struct { byte R2,R3,R4,R5,M2,M3,M4,M5; } MSK[MAXSCREEN+2] =
+{
+  { 0x7F,0x00,0x3F,0x00,0x00,0x00,0x00,0x00 }, /* SCR 0:  TEXT 40x24  */
+  { 0x7F,0xFF,0x3F,0xFF,0x00,0x00,0x00,0x00 }, /* SCR 1:  TEXT 32x24  */
+  { 0x7F,0x80,0x3C,0xFF,0x00,0x7F,0x03,0x00 }, /* SCR 2:  BLK 256x192 */
+  { 0x7F,0x00,0x3F,0xFF,0x00,0x00,0x00,0x00 }, /* SCR 3:  64x48x16    */
+  { 0x7F,0x80,0x3C,0xFC,0x00,0x7F,0x03,0x03 }, /* SCR 4:  BLK 256x192 */
+  { 0x60,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 5:  256x192x16  */
+  { 0x60,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 6:  512x192x4   */
+  { 0x20,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 7:  512x192x16  */
+  { 0x20,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 8:  256x192x256 */
+  { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }, /* SCR 9:  NONE        */
+  { 0x20,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 10: YAE 256x192 */
+  { 0x20,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 11: YAE 256x192 */
+  { 0x20,0x00,0x00,0xFC,0x1F,0x00,0x00,0x03 }, /* SCR 12: YJK 256x192 */
+  { 0x7C,0xF8,0x3F,0x00,0x03,0x07,0x00,0x00 }  /* SCR 0:  TEXT 80x24  */
+};
+
+/** MegaROM Mapper Names *************************************/
+char *ROMNames[MAXMAPPERS+1] = 
+{ 
+  "GENERIC/8kB","GENERIC/16kB","KONAMI5/8kB",
+  "KONAMI4/8kB","ASCII/8kB","ASCII/16kB",
+  "GMASTER2/SRAM","UNKNOWN"
+};
+
+static byte JoyState;
+static int ik;     // joypad key
+static int ihk;    // I2C keyboard key
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+
+static unsigned char linebuffer[WIDTH];
+
+char *Disks[2][MAXDISKS+1];     /* Disk names for each drive */
+
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+void msx_Init(void)
+{
+  /* Clear everything */
+//  CartCount=TypeCount=JoyCount=0;
+//  DiskCount[0]=DiskCount[1]=0;
+
+  /* Default disk images */
+  Disks[0][1]=Disks[1][1]=0;
+  Disks[0][0]=DiskA;
+  Disks[1][0]=DiskB;
+  /* Terminate disk lists and set initial disk names */
+//  if(DiskCount[0]) { Disks[0][DiskCount[0]]=0;DiskA=Disks[0][0]; }
+//  if(DiskCount[1]) { Disks[1][DiskCount[1]]=0;DiskB=Disks[1][0]; }
+
+  /* Start fMSX! */
+//  if(!InitMachine()) return(1);
+//  StartMSX();
+//  TrashMSX();
+//  TrashMachine();     
+  emu_printf("Allocating MEM done");
+}
+
+
+void msx_Input(int click) {
+  ihk = emu_ReadI2CKeyboard();
+  ik = emu_ReadKeys();   
+}
+
+
+
+static int SoundRate    = 0;
+static int MasterVolume = 200;
+static int MasterSwitch = (1<<SND_CHANNELS)-1;
+static int LoopFreq     = 25;
+static int NoiseGen     = 1;
+
+static struct   
+{
+  int Type;                       /* Channel type (SND_*)             */
+  int Freq;                       /* Channel frequency (Hz)           */
+  int Volume;                     /* Channel volume (0..255)          */
+
+  signed char Data[SND_SAMPLESIZE]; /* Wave data (-128..127 each)     */
+  int Length;                     /* Wave length in Data              */
+  int Rate;                       /* Wave playback rate (or 0Hz)      */
+  int Pos;                        /* Wave current position in Data    */
+
+  int Count;                      /* Phase counter                    */
+} CH[SND_CHANNELS];
+
+
+
+
+static void handleSoundCmd(unsigned char * Buf, int len)
+{
+  unsigned char R;
+  int J;
+
+  switch(R=Buf[0])
+  {
+    case 0xFF: MasterVolume=Buf[1];
+               MasterSwitch=Buf[2]+Buf[3]*256;
+               break;
+    case 0xFE: R=Buf[1];
+               J=Buf[2]+Buf[3]*256+2;
+               /* If everything is correct... */
+               if((R<SND_CHANNELS)&&(J<SND_SAMPLESIZE))
+                 //if(read(PipeFD[0],Buf,2)==2)
+                 //{
+                   J-=2;
+                   CH[R].Type   = SND_WAVE;
+                   CH[R].Rate   = Buf[0]+Buf[1]*256;
+                   CH[R].Length = J;
+                   CH[R].Count  = 0;
+                   CH[R].Pos    = 0;
+                   memcpy(CH[R].Data,&Buf[4],J);
+                   J=0;
+                   //I=read(PipeFD[0],CH[R].Data,J);
+                   //if(I>0) J-=I;
+                 //}
+
+               break;
+    case 0xFC: R=Buf[1];
+               if(R<SND_CHANNELS) CH[R].Type=Buf[2];
+               break;
+    default:   if(R<SND_CHANNELS)
+               {
+                 CH[R].Volume = Buf[1];
+                 CH[R].Freq   = Buf[2]+Buf[3]*256;
+               }
+               break;
+  }
+}
+
+static int Wave[SND_BUFSIZE];
+
+static void mixaudio(char * dest, int size) {
+  register int J,I,K,L,M,N,L1,L2,A1,A2,V;
+
+  /* Waveform generator */
+  for(J=0,M=MasterSwitch;M&&(J<SND_CHANNELS);J++,M>>=1)
+    if(CH[J].Freq&&(V=CH[J].Volume)&&(M&1))
+      switch(CH[J].Type)
+      {
+        case SND_NOISE: /* White Noise */
+          /* For high frequencies, recompute volume */
+          if(CH[J].Freq<=SoundRate) K=0x10000*CH[J].Freq/SoundRate;
+          else { V=V*SoundRate/CH[J].Freq;K=0x10000; }
+          L1=CH[J].Count;
+          V<<=7;
+          for(I=0;I<size;I++)
+          {
+            L1+=K;
+            if(L1&0xFFFF0000)
+            {
+              L1&=0xFFFF;
+              if((NoiseGen<<=1)&0x80000000) NoiseGen^=0x08000001;  
+            }
+            Wave[I]+=NoiseGen&1? V:-V;
+          }
+          CH[J].Count=L1;
+          break;
+            
+        case SND_WAVE: /* Custom Waveform */
+          /* Waveform data must have correct length! */
+          if(CH[J].Length<=0) break;
+          /* Start counting */
+          K  = CH[J].Rate>0? (SoundRate<<15)/CH[J].Freq/CH[J].Rate
+                           : (SoundRate<<15)/CH[J].Freq/CH[J].Length;
+          L1 = CH[J].Pos%CH[J].Length;
+          L2 = CH[J].Count;
+          A1 = CH[J].Data[L1]*V;
+          /* If expecting interpolation... */
+          if(L2<K)
+          {
+            /* Compute interpolation parameters */
+            A2 = CH[J].Data[(L1+1)%CH[J].Length]*V;
+            L  = (L2>>15)+1;
+            N  = ((K-(L2&0x7FFF))>>15)+1;
+          } 
+          /* Add waveform to the buffer */  
+          for(I=0;I<size;I++)
+            if(L2<K)
+            {
+              /* Interpolate linearly */
+              Wave[I]+=A1+L*(A2-A1)/N;
+              /* Next waveform step */
+              L2+=0x8000;  
+              /* Next interpolation step */
+              L++;
+            }
+            else
+            {
+              L1 = (L1+L2/K)%CH[J].Length;
+              L2 = (L2%K)+0x8000;
+              A1 = CH[J].Data[L1]*V;
+              Wave[I]+=A1;
+              /* If expecting interpolation... */
+              if(L2<K)
+              {
+                /* Compute interpolation parameters */
+                A2 = CH[J].Data[(L1+1)%CH[J].Length]*V;
+                L  = 1;
+                N  = ((K-L2)>>15)+1;  
+              }
+            }
+          /* End counting */
+          CH[J].Pos   = L1;
+          CH[J].Count = L2;
+          break;
+              
+        case SND_MELODIC:  /* Melodic Sound   */
+        case SND_TRIANGLE: /* Triangular Wave */
+        default:           /* Default Sound   */
+          /* Triangular wave has twice less volume */
+          if(CH[J].Type==SND_TRIANGLE) V=(V+1)>>1;
+          /* Do not allow frequencies that are too high */
+          if(CH[J].Freq>=SoundRate/3) break;
+          K=0x10000*CH[J].Freq/SoundRate;
+          L1=CH[J].Count;
+          V<<=7;
+          for(I=0;I<size;I++)
+          {
+            L2=L1+K;
+            Wave[I]+=L1&0x8000? (L2&0x8000? V:0):(L2&0x8000? 0:-V);
+            L1=L2;
+          }
+          CH[J].Count=L1;  
+          break;
+      }
+
+#define AUDIO_CONV(A) (128+(A))
+
+    /* Mix and convert waveforms */   
+    for(J=0;J<size;J++)
+    {
+      I=(Wave[J]*MasterVolume)>>16;
+      I=I<-128? -128:I>127? 127:I;
+      //Buf[J]=AUDIO_CONV(I);
+      *dest++ = I;
+      *dest++ = I;
+      Wave[J]=0;
+    }
+
+
+
+}
+
+/** Generate sound of given frequency (Hz) and volume       **/
+/** (0..255) via given channel.                             **/
+/*************************************************************/
+static void DSound(int Channel,int NewFreq,int NewVolume)
+{
+  unsigned char Buf[4];
+
+  if((Channel<0)||(Channel>=SND_CHANNELS)) return;
+  if(!SoundRate||!(MasterSwitch&(1<<Channel))) return;
+  if(!NewVolume||!NewFreq) { NewVolume=0;NewFreq=0; }
+
+  if((CH[Channel].Volume!=NewVolume)||(CH[Channel].Freq!=NewFreq))
+  {
+    CH[Channel].Volume = NewVolume;
+    CH[Channel].Freq   = NewFreq;
+
+    Buf[0]=Channel;
+    Buf[1]=NewVolume;
+    Buf[2]=NewFreq&0xFF;
+    Buf[3]=NewFreq>>8;
+    handleSoundCmd(Buf, 4);
+
+//    write(PipeFD[1],Buf,4);
+  }
+}
+
+/** Set master volume (0..255) and turn channels on/off.    **/
+/** Each bit in Toggle corresponds to a channel (1=on).     **/
+/*************************************************************/
+static void DSetChannels(int MVolume,int MSwitch)
+{
+  unsigned char Buf[4];
+  int J;
+
+  if(!SoundRate) return;
+
+  /* Sending new MasterVolume/MasterSwitch */
+  Buf[0]=0xFF;
+  Buf[1]=MVolume;
+  Buf[2]=MSwitch&0xFF;
+  Buf[3]=MSwitch>>8;
+  handleSoundCmd(Buf, 4);
+//  write(PipeFD[1],Buf,4);
+
+  /* Switching channels on/off */
+  for(J=0;J<SND_CHANNELS;J++)
+    if((MSwitch^MasterSwitch)&(1<<J))
+    {
+      /* Modifying channel #J */
+      Buf[0]=J;
+
+      /* Set volume/frequency */
+      if(!(MSwitch&(1<<J))) Buf[1]=Buf[2]=Buf[3]=0;
+      else
+      {
+        Buf[1]=CH[J].Volume;
+        Buf[2]=CH[J].Freq&0xFF;
+        Buf[3]=CH[J].Freq>>8;
+      }
+ 
+      /* Write out */
+      handleSoundCmd(Buf, 4);
+//      write(PipeFD[1],Buf,4);
+    }
+
+  /* Set new MasterSwitch value */
+  MasterSwitch=MSwitch;
+  MasterVolume=MVolume;
+}
+
+/** Set sound type (SND_NOISE/SND_MELODIC) for a given      **/
+/** channel.                                                **/
+/*************************************************************/
+static void DSetSound(int Channel,int NewType)
+{
+  unsigned char Buf[4];
+
+  if(!SoundRate) return;
+  if((Channel<0)||(Channel>=SND_CHANNELS)) return;
+  CH[Channel].Type=NewType;
+
+  Buf[0]=0xFC;
+  Buf[1]=Channel;
+  Buf[2]=NewType&0xFF;
+  Buf[3]=NewType>>8;
+  handleSoundCmd(Buf, 4);
+//  write(PipeFD[1],Buf,4);
+}
+
+/** Set waveform for a given channel. The channel will be   **/
+/** marked with sound type SND_WAVE. Set Rate=0 if you want **/
+/** waveform to be an instrument or set it to the waveform  **/
+/** own playback rate.                                      **/
+/*************************************************************/
+static void DSetWave(int Channel,const signed char *Data,int Length,int Rate)
+{
+  unsigned char Buf[6+SND_SAMPLESIZE];
+
+  if(!SoundRate) return;
+  if((Channel<0)||(Channel>=SND_CHANNELS)) return;
+  if((Length<=0)||(Length>SND_SAMPLESIZE)) return;
+
+  Buf[0]=0xFE;
+  Buf[1]=Channel;
+  Buf[2]=Length&0xFF;
+  Buf[3]=Length>>8;
+  Buf[4]=Rate&0xFF;
+  Buf[5]=Rate>>8;
+  memcpy(Buf+6,Data,Length);
+  handleSoundCmd(Buf, 6+Length);
+//  write(PipeFD[1],Buf,6+Length);
+}
+
+static void DDrum(int Type,int Force)
+{
+}
+
+
+void msx_Start(char * Cartridge)
+{
+  emu_printf("init started");
+ 
+
+
+  /*** MSX versions: ***/
+  static const char *Versions[] = { "MSX","MSX2","MSX2+" };
+
+  /*** Joystick types: ***/
+  static const char *JoyTypes[] =
+  {
+    "nothing","normal joystick",
+    "mouse in joystick mode","mouse in real mode"
+  };
+
+  /*** CMOS ROM default values: ***/
+  static const byte RTCInit[4][13]  =
+  {
+    {  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    {  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    {  0, 0, 0, 0,40,80,15, 4, 4, 0, 0, 0, 0 },
+    {  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+  };
+
+  /*** VDP status register states: ***/
+  static const byte VDPSInit[16] = { 0x9F,0,0x6C,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+  /*** VDP control register states: ***/
+  static const byte VDPInit[64]  =
+  {
+    0x00,0x10,0xFF,0xFF,0xFF,0xFF,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+  };
+
+  /*** Initial palette: ***/
+  static const byte PalInit[16][3] =
+  {
+    {0x00,0x00,0x00},{0x00,0x00,0x00},{0x20,0xC0,0x20},{0x60,0xE0,0x60},
+    {0x20,0x20,0xE0},{0x40,0x60,0xE0},{0xA0,0x20,0x20},{0x40,0xC0,0xE0},
+    {0xE0,0x20,0x20},{0xE0,0x60,0x60},{0xC0,0xC0,0x20},{0xC0,0xC0,0x80},
+    {0x20,0x80,0x20},{0xC0,0x40,0xA0},{0xA0,0xA0,0xA0},{0xE0,0xE0,0xE0}
+  };
+
+  int *T,I,J,K;
+  byte *P;
+  word A;
+  //FILE *F;
+
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND  
+  emu_sndInit();
+  SndDriver.SetSound    = DSetSound;
+  SndDriver.Drum        = DDrum;
+  SndDriver.SetChannels = DSetChannels;
+  SndDriver.Sound       = DSound;
+  SndDriver.SetWave     = DSetWave;
+
+  //int J;
+  /* Reset all channels */
+  for(J=0;J<SND_CHANNELS;J++)
+  {
+    CH[J].Type   = SND_MELODIC;
+    CH[J].Count  = 0;
+    CH[J].Volume = 0;
+    CH[J].Freq   = 0;
+  }  
+  SoundRate = 22050;  
+#endif  
+#else
+#endif
+  /* Zero everyting */
+#ifdef unused  
+  CasStream=PrnStream=ComIStream=ComOStream=NULL;
+#endif  
+  ROMData[0]=ROMData[1]=NULL;
+  FontBuf  = NULL;
+  VRAM     = NULL;
+  SRAM     = NULL;
+  Kanji    = NULL;
+  SaveCMOS = 0;
+  SaveSRAM = 0;
+  ExitNow  = 0;
+  CCount   = 0;
+
+  /* Calculate IPeriod from VPeriod/HPeriod */
+  if(UPeriod<1) UPeriod=1;
+  if(HPeriod<CPU_HPERIOD) HPeriod=CPU_HPERIOD;
+  if(VPeriod<CPU_VPERIOD) VPeriod=CPU_VPERIOD;
+  CPU.TrapBadOps = Verbose&0x10;
+  CPU.IPeriod    = CPU_H240;
+  CPU.IAutoReset = 0;
+
+  /* Check parameters for validity */
+  if(MSXVersion>2) MSXVersion=2;
+  if((RAMPages<(MSXVersion? 8:4))||(RAMPages>256))
+    RAMPages=MSXVersion? 8:4;
+    //RAMPages=MSXVersion? 4:4; // PATCH PICO
+  if((VRAMPages<(MSXVersion? 8:2))||(VRAMPages>8))
+    VRAMPages=MSXVersion? 8:2;
+
+  /* Number of RAM pages should be power of 2 */
+  /* Calculate RAMMask=(2^RAMPages)-1 */
+  for(J=1;J<RAMPages;J<<=1);
+  RAMPages=J;
+  RAMMask=J-1;
+
+  /* Number of VRAM pages should be a power of 2 */
+  for(J=1;J<VRAMPages;J<<=1);
+  VRAMPages=J;
+
+  /* Initialize ROMMasks to zeroes for now */
+  ROMMask[0]=ROMMask[1]=0;
+
+  /* Joystick types are in 0..3 range */
+  JoyTypeA&=3;
+  JoyTypeB&=3;
+
+  /* Allocate 16kB for the empty space (scratch RAM) */
+  if(Verbose) 
+    emu_printf("Allocating 16kB for empty space...");
+  EmptyRAM=emu_Malloc(0x4000); 
+  memset(EmptyRAM,NORAM,0x4000);
+  Chunks[CCount++]=EmptyRAM;
+
+  /* Reset memory map to the empty space */
+  for(I=0;I<4;I++)
+    for(J=0;J<4;J++)
+      for(K=0;K<8;K++)
+        MemMap[I][J][K]=EmptyRAM;
+
+  /* Allocate VRAMPages*16kB for VRAM */
+  /* 128k */
+  if(Verbose) {
+    emu_printi(VRAMPages*16);
+    emu_printf("kB for VRAM...");
+  }
+  VRAM=emu_Malloc(VRAMPages*0x4000);
+  memset(VRAM,0x00,VRAMPages*0x4000);
+  Chunks[CCount++]=VRAM;
+
+  /* Allocate RAMPages*16kB for RAM */
+  if(Verbose) {
+    emu_printi(RAMPages);
+    emu_printf("x16kB RAM pages...");
+  }
+  RAMData=emu_Malloc(RAMPages*0x4000);
+  memset(RAMData,NORAM,RAMPages*0x4000);
+  Chunks[CCount++]=RAMData;
+
+
+  if(Verbose) {
+    emu_printf("Loading ROMs for");
+    emu_printf(Versions[MSXVersion]);
+  } 
+
+
+  /* Open/load system ROM(s) */
+  switch(MSXVersion)
+  {
+    case 0:
+      if(Verbose) emu_printf("Opening MSX.ROM...");
+      //P=LoadROM("msx/roms/MSX.ROM",0x8000,0);
+      P=&MSX[0];
+      if(!P) return(0);
+      MemMap[0][0][0]=P;
+      MemMap[0][0][1]=P+0x2000;
+      MemMap[0][0][2]=P+0x4000;
+      MemMap[0][0][3]=P+0x6000;
+      break;
+
+    case 1:
+      if(Verbose) emu_printf("Opening MSX2.ROM...");
+      //P=LoadROM("msx/roms/MSX2.ROM",0x8000,0);
+      P=&MSX2[0];
+      if(!P) return(0);
+      MemMap[0][0][0]=P;
+      MemMap[0][0][1]=P+0x2000;
+      MemMap[0][0][2]=P+0x4000;
+      MemMap[0][0][3]=P+0x6000;
+      if(Verbose) emu_printf("Opening MSX2EXT.ROM...");
+      //P=LoadROM("msx/roms/MSX2EXT.ROM",0x4000,0);
+      P=&MSX2EXT[0];
+      if(!P) return(0);
+      MemMap[3][1][0]=P;
+      MemMap[3][1][1]=P+0x2000;
+      break;
+
+    case 2:
+      if(Verbose) emu_printf("Opening MSX2P.ROM...");
+      //P=LoadROM("msx/roms/MSX2P.ROM",0x8000,0);
+      P=&MSX2P[0];
+      if(!P) return(0);
+      MemMap[0][0][0]=P;
+      MemMap[0][0][1]=P+0x2000;
+      MemMap[0][0][2]=P+0x4000;
+      MemMap[0][0][3]=P+0x6000;
+      if(Verbose) emu_printf("Opening MSX2PEXT.ROM...");
+      //P=LoadROM("msx/roms/MSX2PEXT.ROM",0x4000,0);
+      P=&MSX2PEXT[0];
+      if(!P) return(0);
+      MemMap[3][1][0]=P;
+      MemMap[3][1][1]=P+0x2000;
+      break;
+  }
+
+  /* Try loading DiskROM */
+  //P=LoadROM("msx/roms/DISK.ROM",0x4000,0);
+  P=&DISK[0];
+  if(P)
+  {
+    if(Verbose) emu_printf("Opening DISK.ROM...OK");
+    MemMap[3][1][2]=P;
+    MemMap[3][1][3]=P+0x2000;
+  }
+
+/*
+  // Apply patches to BIOS
+  if(Verbose) emu_printf("Patching BIOS: ");
+  for(J=0;BIOSPatches[J];J++)
+  {
+    P=MemMap[0][0][0]+BIOSPatches[J];
+    P[0]=0xED;P[1]=0xFE;P[2]=0xC9;
+  }
+  if(Verbose) emu_printf("OK\n");
+
+  // Apply patches to BDOS 
+  if(MemMap[3][1][2]!=EmptyRAM)
+  {
+    if(Verbose) emu_printf("Patching BDOS: ");
+    for(J=0;DiskPatches[J];J++)
+    {
+      P=MemMap[3][1][2]+DiskPatches[J]-0x4000;
+      P[0]=0xED;P[1]=0xFE;P[2]=0xC9;
+    }
+    if(Verbose) emu_printf("OK\n");
+  }
+*/
+  if(Verbose) emu_printf("Loading other ROMs: ");
+
+
+  /* Try loading CMOS memory contents */
+  /*
+  if(LoadROM("msx/roms/CMOS.ROM",sizeof(RTC),(byte *)RTC))
+  { 
+    if(Verbose) emu_printf("CMOS.ROM.."); 
+  }
+  else memcpy(RTC,RTCInit,sizeof(RTC));
+  */
+
+  /* Try loading Kanji alphabet ROM */
+  /*  
+  if(Kanji=LoadROM("msx/roms/KANJI.ROM",0x20000,0))
+  { 
+    if(Verbose) emu_printf("KANJI.ROM.."); 
+  }
+  */
+
+  /* Try loading RS232 support ROM */
+  //P=LoadROM("msx/roms/RS232.ROM..",0x4000,0);
+  /*
+  P=&RS232[0];
+  if(P)
+  {
+    if(Verbose) emu_printf("RS232.ROM..");
+    MemMap[3][0][2]=P;
+    MemMap[3][0][3]=P+0x2000;
+  }
+  */
+
+  /* Try loading FM-PAC support ROM */
+  //P=LoadROM("msx/roms/FMPAC.ROM",0x4000,0);
+  P=&FMPAC[0];
+  if(P)
+  {
+    if(Verbose) emu_printf("FMPAC.ROM..");
+    MemMap[3][3][2]=P;
+    MemMap[3][3][3]=P+0x2000;
+  }
+
+  if(Verbose) emu_printf("OK\n");
+
+
+
+
+  /* Loading cartridge into slot A... */
+  strcpy(CartA, "CARTA.ROM");
+  if (Cartridge != NULL)
+    strcpy(CartA, Cartridge);
+
+  LoadCart(CartA,0);
+  J=(ROMMask[0]+1)*8192;
+
+
+  /* Guess mapper is not given */
+  if((ROMTypeA>=MAXMAPPERS)&&(J>0x8000))
+  {
+    ROMTypeA=GuessROM(ROMData[0],J);
+    if(Verbose) {
+      emu_printf("Cartridge A: Guessed");
+      emu_printf(ROMNames[ROMTypeA]);
+    }
+  }
+
+  /* For Generic/16kB carts, set ROM pages as 0:1:N-2:N-1 */
+  if((ROMTypeA==1)&&(J>0x8000))
+    SetMegaROM(0,0,1,ROMMask[0]-1,ROMMask[0]);
+
+  /* Loading cartridge into slot B... */
+  LoadCart(CartB,1);
+  J=(ROMMask[1]+1)*8192;
+
+  /* Guess mapper is not given */
+  if((ROMTypeB>=MAXMAPPERS)&&(J>0x8000))
+  {
+    ROMTypeB=GuessROM(ROMData[1],J);
+    if(Verbose) {
+      emu_printf("Cartridge B: Guessed");
+      emu_printf(ROMNames[ROMTypeB]);
+    }
+  }
+
+
+  /* For Generic/16kB carts, set ROM pages as 0:1:N-2:N-1 */
+  if((ROMTypeB==1)&&(J>0x8000))
+    SetMegaROM(1,0,1,ROMMask[1]-1,ROMMask[1]);
+
+  /* For GameMaster2, allocate and load SRAM */
+  if((ROMTypeA==6)||(ROMTypeB==6))
+  {
+    if(Verbose) emu_printf("Allocating 16kB for GameMaster2 SRAM..."); 
+    SRAM=emu_Malloc(0x4000);
+    /* Erase SRAM and add it to the list of mallocs */
+    memset(SRAM,NORAM,0x4000);
+    Chunks[CCount++]=SRAM;
+#ifdef unused
+    /* Try loading SRAM data form disk */
+    if(!(F=fopen("GMASTER2.RAM","rb"))) { 
+        emu_printf("failed opening"); 
+    }
+    else
+    {
+      if(Verbose) emu_printf("loading GMASTER2.RAM...");
+      if(fread(SRAM,1,0x2000,F)!=0x2000) 
+      { 
+        emu_printf("failed"); 
+      }
+      else
+      {
+        /* Mirror GameMaster2 SRAM as needed */
+        memcpy(SRAM+0x2000,SRAM+0x1000,0x1000);
+        memcpy(SRAM+0x3000,SRAM+0x1000,0x1000);
+        memcpy(SRAM+0x1000,SRAM,0x1000);
+      }
+      /* Done with the file */
+      fclose(F);
+    }
+#endif
+  }
+
+  /* Load MSX2-dependent cartridge ROMs: MSXDOS2 and PAINTER */
+  if(MSXVersion>0)
+  {
+    /* Find an empty slot */
+    if(MemMap[1][0][2]==EmptyRAM) J=1;
+    else if(MemMap[2][0][2]==EmptyRAM) J=2;
+         else J=0;
+
+    /* Try loading MSXDOS2 cartridge, if slot */
+    /* found and DiskROM present              */
+    if(J&&(MemMap[3][1][2]!=EmptyRAM))
+    {
+      if(J==2) ROMTypeB=1; else ROMTypeA=1;
+      if(LoadCart("MSXDOS2.ROM",J-1))
+        SetMegaROM(J-1,0,1,ROMMask[J-1]-1,ROMMask[J-1]);
+    }
+
+    /* Find an empty slot */
+    if(MemMap[1][0][2]==EmptyRAM) J=1;
+    else if(MemMap[2][0][2]==EmptyRAM) J=2;
+         else J=0;
+
+    /* Try loading PAINTER ROM if slot found */
+    if(J) LoadCart("PAINTER.ROM",J-1);
+  }
+
+  /* Try loading font */
+  if(Verbose) {
+    emu_printf("Loading font...");
+    emu_printf(FontName);
+  }
+  //FontBuf=LoadROM(FontName,0x800,0);
+
+#ifdef unused  
+  /* Open stream for a printer */
+  if(!PrnName) PrnStream=stdout;
+  else
+  {
+    if(Verbose) printf("Redirecting printer output to %s...",PrnName);
+    if(!(PrnStream=fopen(PrnName,"wb"))) PrnStream=stdout;
+  }
+#endif
+
+#ifdef unused  
+  /* Open streams for serial IO */
+  if(!ComName) { ComIStream=stdin;ComOStream=stdout; }
+  else
+  {
+    if(Verbose) printf("Redirecting serial I/O to %s...",ComName);
+    if(!(ComOStream=ComIStream=fopen(ComName,"r+b")))
+    { ComIStream=stdin;ComOStream=stdout; }
+  }
+#endif
+
+  /* Open disk images */
+#ifdef DISK
+  if(ChangeDisk(0,DiskA)) 
+    if(Verbose) {
+      emu_printf("Inserting floppy into drive A");
+      emu_printf(DiskA);
+    }  
+  if(ChangeDisk(1,DiskB))
+    if(Verbose) {
+      emu_printf("Inserting floppy into drive B");
+      emu_printf(DiskB);
+    }
+#endif /* DISK */
+
+#ifdef unused  
+  /* Open casette image */
+  if(CasName)
+    if(CasStream=fopen(CasName,"r+b"))
+      if(Verbose) {
+        emu_printf("Inserting tape");
+        emu_printf(CasName);
+      }
+#endif
+
+  if(Verbose)
+  {
+    emu_printf("Attaching joystick port A");
+    emu_printf(JoyTypes[JoyTypeA]);
+    emu_printf("Attaching joystick port B");
+    emu_printf(JoyTypes[JoyTypeB]);
+    emu_printf("Initializing memory mappers...");
+  }
+
+  for(J=0;J<4;J++)
+  {
+    EnWrite[J]=0;                      /* Write protect ON for all slots */
+    PSL[J]=SSL[J]=0;                   /* PSL=0:0:0:0, SSL=0:0:0:0       */
+    MemMap[3][2][J*2]   = RAMData+(3-J)*0x4000;        /* RAMMap=3:2:1:0 */
+    MemMap[3][2][J*2+1] = MemMap[3][2][J*2]+0x2000;
+    RAMMapper[J]        = 3-J;
+    RAM[J*2]            = MemMap[0][0][J*2];           /* Setting RAM    */
+    RAM[J*2+1]          = MemMap[0][0][J*2+1];
+  }
+
+  if(Verbose) emu_printf("Initializing VDP, PSG, OPLL, SCC, and CPU...");
+
+  /* Initialize palette */
+  for(J=0;J<16;J++)
+  {
+    Palette[J]=RGB2INT(PalInit[J][0],PalInit[J][1],PalInit[J][2]);
+    SetColor(J,PalInit[J][0],PalInit[J][1],PalInit[J][2]);
+  }
+
+  /* Reset mouse coordinates/counters */
+  for(J=0;J<2;J++)
+    Buttons[J]=MouseDX[J]=MouseDY[J]=OldMouseX[J]=OldMouseY[J]=MCount[J]=0;
+
+  /* Initialize sound logging */
+  //InitMIDI("SndName");
+
+  /* Reset sound chips */
+  Reset8910(&PSG,0);
+  ResetSCC(&SCChip,AY8910_CHANNELS);
+  Reset2413(&OPLL,AY8910_CHANNELS);
+  Sync8910(&PSG,AY8910_SYNC);
+  SyncSCC(&SCChip,SCC_SYNC);
+  Sync2413(&OPLL,YM2413_SYNC);
+
+  /* Reset serial I/O */
+#ifdef unused  
+  Reset8251(&SIO,ComIStream,ComOStream);
+#else
+  Reset8251(&SIO,NULL,NULL);
+#endif  
+  /* Reset PPI chips and slot selectors */
+  Reset8255(&PPI);
+  PPI.Rout[0]=PSLReg=0x00;
+  PPI.Rout[2]=IOReg=0x00;
+  SSLReg=0x00;
+
+  memcpy(VDP,VDPInit,sizeof(VDP));
+  memcpy(VDPStatus,VDPSInit,sizeof(VDPStatus));
+  memset(KeyMap,0xFF,16);               /* Keyboard         */
+  IRQPending=0x00;                      /* No IRQs pending  */
+  SCCOn[0]=SCCOn[1]=0;                  /* SCCs off for now */
+  RTCReg=RTCMode=0;                     /* Clock registers  */
+  KanCount=0;KanLetter=0;               /* Kanji extension  */
+  ChrTab=ColTab=ChrGen=VRAM;            /* VDP tables       */
+  SprTab=SprGen=VRAM;
+  ChrTabM=ColTabM=ChrGenM=SprTabM=~0;   /* VDP addr. masks  */
+  VPAGE=VRAM;                           /* VRAM page        */
+  FGColor=BGColor=XFGColor=XBGColor=0;  /* VDP colors       */
+  ScrMode=0;                            /* Screen mode      */
+  VKey=PKey=1;WKey=0;                   /* VDP keys         */
+  VAddr=0x0000;                         /* VRAM access addr */
+  ScanLine=0;                           /* Current scanline */
+  VDPData=NORAM;                        /* VDP data buffer  */
+  UseFont=0;                            /* Extern. font use */   
+
+  /* Set "V9958" VDP version for MSX2+ */
+  if(MSXVersion>=2) VDPStatus[1]|=0x04;
+
+  /* Reset CPU */
+  ResetZ80(&CPU);
+
+  /* Done with initialization */
+  if(Verbose)
+  {
+    emu_printi(HPeriod);
+    emu_printf("CPU cycles per HBlank");
+    emu_printi(VPeriod);
+    emu_printf("CPU cycles per VBlank");
+    emu_printi(VPeriod/HPeriod);
+    emu_printf("scanlines");
+  }
+
+
+  /* Start execution of the code */
+  if(Verbose) emu_printf("RUNNING ROM CODE...\n");
+  A=RunZ80(&CPU);
+
+
+  emu_printf("init done");
+}
+
+#define INV_KEY {255,255}
+
+struct { byte Pos,Mask; } Keys[] =
+{
+/* 0x00 */ INV_KEY,
+/* 0x01 */ INV_KEY,
+/* 0x02 */ INV_KEY,
+/* 0x03 */ INV_KEY,
+/* 0x04 */ INV_KEY,
+/* 0x05 */ INV_KEY,
+/* 0x06 */ INV_KEY,
+/* 0x07 */ INV_KEY,
+/* 0x08 */ INV_KEY,
+/* 0x09 */ INV_KEY,   // tab
+/* 0x0A */ INV_KEY,
+/* 0x0B */ INV_KEY,
+/* 0x0C */ INV_KEY,
+/* 0x0D */ {7,0x80},  // enter
+/* 0x0E */ INV_KEY,
+/* 0x0F */ INV_KEY,
+/* 0x10 */ INV_KEY,
+/* 0x11 */ INV_KEY,
+/* 0x12 */ INV_KEY,
+/* 0x13 */ INV_KEY,
+/* 0x14 */ INV_KEY,
+/* 0x15 */ INV_KEY,
+/* 0x16 */ INV_KEY,
+/* 0x17 */ INV_KEY,
+/* 0x18 */ INV_KEY,
+/* 0x19 */ INV_KEY,
+/* 0x1A */ INV_KEY,
+/* 0x1B */ INV_KEY,   // esc
+/* 0x1C */ INV_KEY,
+/* 0x1D */ INV_KEY,
+/* 0x1E */ INV_KEY,
+/* 0x1F */ INV_KEY,
+
+/* 0x20 */ {8,0x01},  // space
+/* 0x21 */ INV_KEY,   // ! exclamation mark
+/* 0x22 */ INV_KEY,   // " double quote   
+/* 0x23 */ INV_KEY,   // # dies
+/* 0x24 */ INV_KEY,   // $ dollar
+/* 0x25 */ INV_KEY,   // % percent
+/* 0x26 */ INV_KEY,   // & ampercent
+/* 0x27 */ INV_KEY,   // ' singlequote
+/* 0x28 */ INV_KEY,   // ( bracket left
+/* 0x29 */ INV_KEY,   // ) bracket right
+/* 0x2A */ INV_KEY,   // * mult
+/* 0x2B */ INV_KEY,   // + plus
+/* 0x2C */ {2,0x04},  // , comma
+/* 0x2D */ INV_KEY,   // - minus
+/* 0x2E */ INV_KEY,   // . period
+/* 0x2F */ INV_KEY,   // / slash
+
+/* 0x30 */   {0,0x01}, //'0'
+/* 0x31 */   {0,0x02}, //'1'
+/* 0x32 */   {0,0x04}, //'2'
+/* 0x33 */   {0,0x08}, //'3'
+/* 0x34 */   {0,0x10}, //'4'
+/* 0x35 */   {0,0x20}, //'5'
+/* 0x36 */   {0,0x40}, //'6'
+/* 0x37 */   {0,0x80}, //'7'
+/* 0x38 */   {1,0x01}, //'8'
+/* 0x39 */   {1,0x02}, //'9'
+
+/* 0x3A */ INV_KEY,    // : colon
+/* 0x3B */ INV_KEY,    // ; semi colon
+/* 0x3C */ INV_KEY,    // <
+/* 0x3D */ INV_KEY,    // = equal
+/* 0x3E */ INV_KEY,    // >
+/* 0x3F */ INV_KEY,    // ?
+/* 0x40 */ INV_KEY,    // @
+
+/* 0x41 */  {2,0x40}, //'A'
+/* 0x42 */  {2,0x80}, //'B'
+/* 0x43 */  {3,0x01}, //'C'
+/* 0x44 */  {3,0x02}, //'D'
+/* 0x45 */  {3,0x04}, //'E'
+/* 0x46 */  {3,0x08}, //'F'
+/* 0x47 */  {3,0x10}, //'G'
+/* 0x48 */  {3,0x20}, //'H'
+/* 0x49 */  {3,0x40}, //'I'
+/* 0x4A */  {3,0x80}, //'J'
+/* 0x4B */  {4,0x01}, //'K'
+/* 0x4C */  {4,0x02}, //'L'
+/* 0x4D */  {4,0x04}, //'M'
+/* 0x4E */  {4,0x08}, //'N'
+/* 0x4F */  {4,0x10}, //'O'
+/* 0x50 */  {4,0x20}, //'P'
+/* 0x51 */  {4,0x40}, //'Q'
+/* 0x52 */  {4,0x80}, //'R'
+/* 0x53 */  {5,0x01}, //'S'
+/* 0x54 */  {5,0x02}, //'T'
+/* 0x55 */  {5,0x04}, //'U'
+/* 0x56 */  {5,0x08}, //'V'
+/* 0x57 */  {5,0x10}, //'W'
+/* 0x58 */  {5,0x20}, //'X'
+/* 0x59 */  {5,0x40}, //'Y'
+/* 0x5A */  {5,0x80}, //'Z'
+
+/* 0x5B */ INV_KEY,  // square bracket open
+/* 0x5C */ INV_KEY,  // backslach
+/* 0x5D */ INV_KEY,  // square braquet close
+/* 0x5E */ INV_KEY,  // ^ circonflex
+/* 0x5F */ INV_KEY,  // _ undescore
+/* 0x60 */ INV_KEY,  // `backquote
+
+/* 0x61 */  {2,0x40}, //'a'
+/* 0x62 */  {2,0x80}, //'b'
+/* 0x63 */  {3,0x01}, //'c'
+/* 0x64 */  {3,0x02}, //'d'
+/* 0x65 */  {3,0x04}, //'e'
+/* 0x66 */  {3,0x08}, //'f'
+/* 0x67 */  {3,0x10}, //'g'
+/* 0x68 */  {3,0x20}, //'h'
+/* 0x69 */  {3,0x40}, //'i'
+/* 0x6A */  {3,0x80}, //'j'
+/* 0x6B */  {4,0x01}, //'k'
+/* 0x6C */  {4,0x02}, //'l'
+/* 0x6D */  {4,0x04}, //'m'
+/* 0x6E */  {4,0x08}, //'n'
+/* 0x6F */  {4,0x10}, //'o'
+/* 0x70 */  {4,0x20}, //'p'
+/* 0x71 */  {4,0x40}, //'q'
+/* 0x72 */  {4,0x80}, //'r'
+/* 0x73 */  {5,0x01}, //'s'
+/* 0x74 */  {5,0x02}, //'t'
+/* 0x75 */  {5,0x04}, //'u'
+/* 0x76 */  {5,0x08}, //'v'
+/* 0x77 */  {5,0x10}, //'w'
+/* 0x78 */  {5,0x20}, //'x'
+/* 0x79 */  {5,0x40}, //'y'
+/* 0x7A */  {5,0x80}, //'z'
+
+/* 0x7B */ INV_KEY,  // curly bracket open
+/* 0x7C */ INV_KEY,  // or
+/* 0x7D */ INV_KEY,  // curly bracket close  
+/* 0x7E */ INV_KEY,  // tilt
+/* 0x7F */ {7,0x20}, // backspace
+
+/* 0xC0 */ INV_KEY,
+/* 0xC1 */ INV_KEY,
+/* 0xC2 */ INV_KEY,   // F1
+/* 0xC3 */ INV_KEY,   // F2
+/* 0xC4 */ INV_KEY,   // F3
+/* 0xC5 */ INV_KEY,   // F4
+/* 0xC6 */ INV_KEY,   // F5
+/* 0xC7 */ INV_KEY,   // F6
+/* 0xC8 */ INV_KEY,   // F7
+/* 0xC9 */ INV_KEY,   // F8
+/* 0xCA */ INV_KEY,   // F9
+/* 0xCB */ INV_KEY,   // F10
+/* 0xCC */ INV_KEY,
+/* 0xCD */ INV_KEY,
+/* 0xCE */ INV_KEY,
+/* 0xCF */ INV_KEY,
+/* 0xD0 */ INV_KEY,
+/* 0xD1 */ INV_KEY,
+/* 0xD2 */ INV_KEY,
+/* 0xD3 */ INV_KEY,
+/* 0xD4 */ INV_KEY,   // DEL
+/* 0xD5 */ INV_KEY,
+/* 0xD6 */ INV_KEY,
+/* 0xD7 */ INV_KEY,   // U
+/* 0xD8 */ INV_KEY,   // L
+/* 0xD9 */ INV_KEY,   // R
+/* 0xDA */ INV_KEY,   // D
+/* 0xDB */ INV_KEY,
+/* 0xDC */ INV_KEY,
+/* 0xDD */ INV_KEY,
+/* 0xDE */ INV_KEY,
+/* 0xDF */ INV_KEY
+};
+
+
+void msx_Step(void) {
+  int k  = ik;
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+  
+  JoyState = 0;
+  if (k & MASK_JOY2_DOWN)  JoyState|=0x02;
+  if (k & MASK_JOY2_UP)    JoyState|=0x01;
+  if (k & MASK_JOY2_RIGHT)  JoyState|=0x04;
+  if (k & MASK_JOY2_LEFT) JoyState|=0x08;
+  if (k & MASK_JOY2_BTN) JoyState|=0x10; 
+  if (k & MASK_KEY_USER2) JoyState|=0x20;  
+
+  if (hk != 0) {
+    //emu_printh(hk);
+    KeyMap[Keys[hk].Pos] &=~ Keys[hk].Mask;   
+  }
+  else  {
+    memset(KeyMap,0xFF,16);
+  }
+
+  RunZ80(&CPU);
+
+  emu_DrawVsync();    
+}
+
+
+
+
+
+
+void SND_Process(void *stream, int len) {
+  //psg_update(stream, 0, len); 
+  mixaudio(stream, len); 
+} 
+
+
+
+
+
+void SetColor(byte N,byte R,byte G,byte B)
+{
+  XPal[N] = N; 
+  emu_SetPaletteEntry(R,G,B,N);
+}
+
+void Keyboard(void)
+{
+}
+
+byte Joystick(register byte N) { return(JoyState); }
+
+/** Mouse() **************************************************/
+/** Query coordinates of a mouse connected to port N.       **/
+/** Returns F2.F1.Y.Y.Y.Y.Y.Y.Y.Y.X.X.X.X.X.X.X.X.          **/
+/*************************************************************/
+int Mouse(register byte N)
+{
+  return(0);
+}
+
+
+
+
+
+
+/** ClearLine() **********************************************/
+/** Clear 256 pixels from P with color C.                   **/
+/*************************************************************/
+static void ClearLine(register pixel *P,register pixel C)
+{
+  register int J;
+
+  for(J=0;J<256;J++) P[J]=C;
+}
+
+/** YJKColor() ***********************************************/
+/** Given a color in YJK format, return the corresponding   **/
+/** palette entry.                                          **/
+/*************************************************************/
+static pixel YJKColor(register int Y,register int J,register int K)
+{
+  register int R,G,B;
+    
+  R=Y+J;
+  G=Y+K;
+  B=((5*Y-2*J-K)/4);
+
+  R=R<0? 0:R>31? 31:R;
+  G=G<0? 0:G>31? 31:G;
+  B=B<0? 0:B>31? 31:B;
+
+  return(BPal[(R&0x1C)|((G&0x1C)<<3)|(B>>3)]);
+}
+
+/** RefreshBorder() ******************************************/
+/** This function is called from RefreshLine#() to refresh  **/
+/** the screen border. It returns a pointer to the start of **/
+/** scanline Y in FB or 0 if scanline is beyond FB.         **/
+/*************************************************************/
+pixel *RefreshBorder(register byte Y,register pixel C)
+{
+  register pixel *P;
+  register int H;
+
+  /* First line number in the buffer */
+  if(!Y) FirstLine=(ScanLines212? 8:18)+VAdjust;
+
+  /* Return 0 if we've run out of the screen buffer due to overscan */
+  if(Y+FirstLine>=HEIGHT) return(0);
+
+  /* Set up the transparent color */
+  XPal[0]=(!BGColor||SolidColor0)? XPal0:XPal[BGColor];
+
+  /* Start of the buffer */
+  P=(pixel *)&linebuffer[0];
+
+  /* Paint top of the screen */
+  //if(!Y) for(H=WIDTH*FirstLine-1;H>=0;H--) P[H]=C;
+
+  /* Start of the line */
+  //P+=WIDTH*(FirstLine+Y);
+
+  /* Paint left/right borders */
+  for(H=(WIDTH-256)/2+HAdjust;H>0;H--) P[H-1]=C;
+  for(H=(WIDTH-256)/2-HAdjust;H>0;H--) P[WIDTH-H]=C;
+
+  /* Paint bottom of the screen */
+  //H=ScanLines212? 212:192;
+  //if(Y==H-1) for(H=WIDTH*(HEIGHT-H-FirstLine+1)-1;H>=WIDTH;H--) P[H]=C;
+
+  /* Return pointer to the scanline in FB */
+  return(P+(WIDTH-256)/2+HAdjust);
+}
+
+/** Sprites() ************************************************/
+/** This function is called from RefreshLine#() to refresh  **/
+/** sprites in SCREENs 1-3.                                 **/
+/*************************************************************/
+void Sprites(register byte Y,register pixel *Line)
+{
+  register pixel *P,C;
+  register byte H,*PT,*AT;
+  register unsigned int M;
+  register int L,K;
+
+  /* Assign initial values before counting */
+  H=Sprites16x16? 16:8;
+  C=0;M=0;L=0;
+  AT=SprTab-4;
+  Y+=VScroll;
+
+  /* Count displayed sprites */
+  do
+  {
+    M<<=1;AT+=4;L++;    /* Iterating through SprTab      */
+    K=AT[0];            /* K = sprite Y coordinate       */
+    if(K==208) break;   /* Iteration terminates if Y=208 */
+    if(K>256-H) K-=256; /* Y coordinate may be negative  */
+
+    /* Mark all valid sprites with 1s, break at MAXSPRITE1 sprites */
+    if((Y>K)&&(Y<=K+H)) { M|=1;C++;if(C==MAXSPRITE1) break; }
+  }
+  while(L<32);
+
+  /* Draw all marked sprites */
+  for(;M;M>>=1,AT-=4)
+    if(M&1)
+    {
+      C=AT[3];                  /* C = sprite attributes */
+      L=C&0x80? AT[1]-32:AT[1]; /* Sprite may be shifted left by 32 */
+      C&=0x0F;                  /* C = sprite color */
+
+      if((L<256)&&(L>-H)&&C)
+      {
+        K=AT[0];                /* K = sprite Y coordinate */
+        if(K>256-H) K-=256;     /* Y coordinate may be negative */
+
+        P=Line+L;
+        PT=SprGen+((int)(H>8? AT[2]&0xFC:AT[2])<<3)+Y-K-1;
+        C=XPal[C];
+
+        /* Mask 1: clip left sprite boundary */
+        K=L>=0? 0x0FFFF:(0x10000>>-L)-1;
+        /* Mask 2: clip right sprite boundary */
+        if(L>256-H) K^=((0x00200>>(H-8))<<(L-257+H))-1;
+        /* Get and clip the sprite data */
+        K&=((int)PT[0]<<8)|(H>8? PT[16]:0x00);
+
+        /* Draw left 8 pixels of the sprite */
+        if(K&0xFF00)
+        {
+          if(K&0x8000) P[0]=C;if(K&0x4000) P[1]=C;
+          if(K&0x2000) P[2]=C;if(K&0x1000) P[3]=C;
+          if(K&0x0800) P[4]=C;if(K&0x0400) P[5]=C;
+          if(K&0x0200) P[6]=C;if(K&0x0100) P[7]=C;
+        }
+
+        /* Draw right 8 pixels of the sprite */
+        if(K&0x00FF)
+        {
+          if(K&0x0080) P[8]=C; if(K&0x0040) P[9]=C;
+          if(K&0x0020) P[10]=C;if(K&0x0010) P[11]=C;
+          if(K&0x0008) P[12]=C;if(K&0x0004) P[13]=C;
+          if(K&0x0002) P[14]=C;if(K&0x0001) P[15]=C;
+        }
+      }
+    }
+}
+
+/** ColorSprites() *******************************************/
+/** This function is called from RefreshLine#() to refresh  **/
+/** color sprites in SCREENs 4-8. The result is returned in **/
+/** ZBuf, whose size must be 304 bytes (32+256+16).         **/
+/*************************************************************/
+void ColorSprites(register byte Y,byte *ZBuf)
+{
+  register byte C,H,J,OrThem;
+  register byte *P,*PT,*AT;
+  register int L,K;
+  register unsigned int M;
+
+  /* Clear ZBuffer and exit if sprites are off */
+  memset(ZBuf+32,0,256);
+  if(SpritesOFF) return;
+
+  /* Assign initial values before counting */
+  H=Sprites16x16? 16:8;
+  C=0;M=0;L=0;
+  AT=SprTab-4;
+  OrThem=0x00;
+
+  /* Count displayed sprites */
+  do
+  {
+    M<<=1;AT+=4;L++;          /* Iterating through SprTab      */
+    K=AT[0];                  /* Read Y from SprTab            */
+    if(K==216) break;         /* Iteration terminates if Y=216 */
+    K=(byte)(K-VScroll);      /* Sprite's actual Y coordinate  */
+    if(K>256-H) K-=256;       /* Y coordinate may be negative  */
+
+    /* Mark all valid sprites with 1s, break at MAXSPRITE2 sprites */
+    if((Y>K)&&(Y<=K+H)) { M|=1;C++;if(C==MAXSPRITE2) break; }
+  }
+  while(L<32);
+
+  /* Draw all marked sprites */
+  for(;M;M>>=1,AT-=4)
+    if(M&1)
+    {
+      K=(byte)(AT[0]-VScroll); /* K = sprite Y coordinate */
+      if(K>256-H) K-=256;      /* Y coordinate may be negative */
+
+      J=Y-K-1;
+      C=SprTab[-0x0200+((AT-SprTab)<<2)+J];
+      OrThem|=C&0x40;
+
+      if(C&0x0F)
+      {
+        PT=SprGen+((int)(H>8? AT[2]&0xFC:AT[2])<<3)+J;
+        P=ZBuf+AT[1]+(C&0x80? 0:32);
+        C&=0x0F;
+        J=PT[0];
+
+        if(OrThem&0x20)
+        {
+          if(J&0x80) P[0]|=C;if(J&0x40) P[1]|=C;
+          if(J&0x20) P[2]|=C;if(J&0x10) P[3]|=C;
+          if(J&0x08) P[4]|=C;if(J&0x04) P[5]|=C;
+          if(J&0x02) P[6]|=C;if(J&0x01) P[7]|=C;
+          if(H>8)
+          {
+            J=PT[16];
+            if(J&0x80) P[8]|=C; if(J&0x40) P[9]|=C;
+            if(J&0x20) P[10]|=C;if(J&0x10) P[11]|=C;
+            if(J&0x08) P[12]|=C;if(J&0x04) P[13]|=C;
+            if(J&0x02) P[14]|=C;if(J&0x01) P[15]|=C;
+          }
+        }
+        else
+        {
+          if(J&0x80) P[0]=C;if(J&0x40) P[1]=C;
+          if(J&0x20) P[2]=C;if(J&0x10) P[3]=C;
+          if(J&0x08) P[4]=C;if(J&0x04) P[5]=C;
+          if(J&0x02) P[6]=C;if(J&0x01) P[7]=C;
+          if(H>8)
+          {
+            J=PT[16];
+            if(J&0x80) P[8]=C; if(J&0x40) P[9]=C;
+            if(J&0x20) P[10]=C;if(J&0x10) P[11]=C;
+            if(J&0x08) P[12]=C;if(J&0x04) P[13]=C;
+            if(J&0x02) P[14]=C;if(J&0x01) P[15]=C;
+          }
+        }
+      }
+
+      /* Update overlapping flag */
+      OrThem>>=1;
+    }
+}
+
+/** RefreshLineF() *******************************************/
+/** Dummy refresh function called for non-existing screens. **/
+/*************************************************************/
+static void RefreshLineF(register byte Y)
+{
+  register pixel *P;
+
+  //if(Verbose>1)
+  //  printf
+  //  (
+  //    "ScrMODE %d: ChrTab=%X ChrGen=%X ColTab=%X SprTab=%X SprGen=%X\n",
+  //    ScrMode,ChrTab-VRAM,ChrGen-VRAM,ColTab-VRAM,SprTab-VRAM,SprGen-VRAM
+  //  );
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(P) ClearLine(P,XPal[BGColor]);
+}
+
+/** RefreshLine0() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN0.                 **/
+/*************************************************************/
+static void RefreshLine0(register byte Y)
+{
+  register pixel *P,FC,BC;
+  register byte X,*T,*G;
+
+  BC=XPal[BGColor];
+  P=RefreshBorder(Y,BC);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,BC);
+  else
+  {
+    P[0]=P[1]=P[2]=P[3]=P[4]=P[5]=P[6]=P[7]=P[8]=BC;
+
+    G=(UseFont&&FontBuf? FontBuf:ChrGen)+((Y+VScroll)&0x07);
+    T=ChrTab+40*(Y>>3);
+    FC=XPal[FGColor];
+    P+=9;
+
+    for(X=0;X<40;X++,T++,P+=6)
+    {
+      Y=G[(int)*T<<3];
+      P[0]=Y&0x80? FC:BC;P[1]=Y&0x40? FC:BC;
+      P[2]=Y&0x20? FC:BC;P[3]=Y&0x10? FC:BC;
+      P[4]=Y&0x08? FC:BC;P[5]=Y&0x04? FC:BC;
+    }
+
+    P[0]=P[1]=P[2]=P[3]=P[4]=P[5]=P[6]=BC;
+  }
+}
+
+/** RefreshLine1() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN1, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine1(register byte Y)
+{
+  register pixel *P,FC,BC;
+  register byte K,X,*T,*G;
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    Y+=VScroll;
+    G=(UseFont&&FontBuf? FontBuf:ChrGen)+(Y&0x07);
+    T=ChrTab+((int)(Y&0xF8)<<2);
+
+    for(X=0;X<32;X++,T++,P+=8)
+    {
+      K=ColTab[*T>>3];
+      FC=XPal[K>>4];
+      BC=XPal[K&0x0F];
+      K=G[(int)*T<<3];
+      P[0]=K&0x80? FC:BC;P[1]=K&0x40? FC:BC;
+      P[2]=K&0x20? FC:BC;P[3]=K&0x10? FC:BC;
+      P[4]=K&0x08? FC:BC;P[5]=K&0x04? FC:BC;
+      P[6]=K&0x02? FC:BC;P[7]=K&0x01? FC:BC;
+    }
+
+    if(!SpritesOFF) Sprites(Y,P-256);
+  }
+}
+
+/** RefreshLine2() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN2, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine2(register byte Y)
+{
+  register pixel *P,FC,BC;
+  register byte K,X,*T;
+  register int I,J;
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    Y+=VScroll;
+    T=ChrTab+((int)(Y&0xF8)<<2);
+    I=((int)(Y&0xC0)<<5)+(Y&0x07);
+
+    for(X=0;X<32;X++,T++,P+=8)
+    {
+      J=(int)*T<<3;
+      K=ColTab[(I+J)&ColTabM];
+      FC=XPal[K>>4];
+      BC=XPal[K&0x0F];
+      K=ChrGen[(I+J)&ChrGenM];
+      P[0]=K&0x80? FC:BC;P[1]=K&0x40? FC:BC;
+      P[2]=K&0x20? FC:BC;P[3]=K&0x10? FC:BC;
+      P[4]=K&0x08? FC:BC;P[5]=K&0x04? FC:BC;
+      P[6]=K&0x02? FC:BC;P[7]=K&0x01? FC:BC;
+    }
+
+    if(!SpritesOFF) Sprites(Y,P-256);
+  }
+}
+
+/** RefreshLine3() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN3, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine3(register byte Y)
+{
+  register pixel *P;
+  register byte X,K,*T,*G;
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    Y+=VScroll;
+    T=ChrTab+((int)(Y&0xF8)<<2);
+    G=ChrGen+((Y&0x1C)>>2);
+
+    for(X=0;X<32;X++,T++,P+=8)
+    {
+      K=G[(int)*T<<3];
+      P[0]=P[1]=P[2]=P[3]=XPal[K>>4];
+      P[4]=P[5]=P[6]=P[7]=XPal[K&0x0F];
+    }
+
+    if(!SpritesOFF) Sprites(Y,P-256);
+  }
+}
+
+/** RefreshLine4() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN4, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine4(register byte Y)
+{
+  register pixel *P,FC,BC;
+  register byte K,X,C,*T,*R;
+  register int I,J;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    Y+=VScroll;
+    T=ChrTab+((int)(Y&0xF8)<<2);
+    I=((int)(Y&0xC0)<<5)+(Y&0x07);
+
+    for(X=0;X<32;X++,R+=8,P+=8,T++)
+    {
+      J=(int)*T<<3;
+      K=ColTab[(I+J)&ColTabM];
+      FC=XPal[K>>4];
+      BC=XPal[K&0x0F];
+      K=ChrGen[(I+J)&ChrGenM];
+
+      C=R[0];P[0]=C? XPal[C]:(K&0x80)? FC:BC;
+      C=R[1];P[1]=C? XPal[C]:(K&0x40)? FC:BC;
+      C=R[2];P[2]=C? XPal[C]:(K&0x20)? FC:BC;
+      C=R[3];P[3]=C? XPal[C]:(K&0x10)? FC:BC;
+      C=R[4];P[4]=C? XPal[C]:(K&0x08)? FC:BC;
+      C=R[5];P[5]=C? XPal[C]:(K&0x04)? FC:BC;
+      C=R[6];P[6]=C? XPal[C]:(K&0x02)? FC:BC;
+      C=R[7];P[7]=C? XPal[C]:(K&0x01)? FC:BC;
+    }
+  }
+}
+
+/** RefreshLine5() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN5, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine5(register byte Y)
+{
+  register pixel *P;
+  register byte I,X,*T,*R;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<7)&ChrTabM&0x7FFF);
+
+    for(X=0;X<16;X++,R+=16,P+=16,T+=8)
+    {
+      I=R[0];P[0]=XPal[I? I:T[0]>>4];
+      I=R[1];P[1]=XPal[I? I:T[0]&0x0F];
+      I=R[2];P[2]=XPal[I? I:T[1]>>4];
+      I=R[3];P[3]=XPal[I? I:T[1]&0x0F];
+      I=R[4];P[4]=XPal[I? I:T[2]>>4];
+      I=R[5];P[5]=XPal[I? I:T[2]&0x0F];
+      I=R[6];P[6]=XPal[I? I:T[3]>>4];
+      I=R[7];P[7]=XPal[I? I:T[3]&0x0F];
+      I=R[8];P[8]=XPal[I? I:T[4]>>4];
+      I=R[9];P[9]=XPal[I? I:T[4]&0x0F];
+      I=R[10];P[10]=XPal[I? I:T[5]>>4];
+      I=R[11];P[11]=XPal[I? I:T[5]&0x0F];
+      I=R[12];P[12]=XPal[I? I:T[6]>>4];
+      I=R[13];P[13]=XPal[I? I:T[6]&0x0F];
+      I=R[14];P[14]=XPal[I? I:T[7]>>4];
+      I=R[15];P[15]=XPal[I? I:T[7]&0x0F];
+    }
+  }
+}
+
+/** RefreshLine8() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN8, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine8(register byte Y)
+{
+  static byte SprToScr[16] =
+  {
+    0x00,0x02,0x10,0x12,0x80,0x82,0x90,0x92,
+    0x49,0x4B,0x59,0x5B,0xC9,0xCB,0xD9,0xDB
+  };
+  register pixel *P;
+  register byte C,X,*T,*R;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,BPal[VDP[7]]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,BPal[VDP[7]]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<8)&ChrTabM&0xFFFF);
+
+    for(X=0;X<32;X++,T+=8,R+=8,P+=8)
+    {
+      C=R[0];P[0]=BPal[C? SprToScr[C]:T[0]];
+      C=R[1];P[1]=BPal[C? SprToScr[C]:T[1]];
+      C=R[2];P[2]=BPal[C? SprToScr[C]:T[2]];
+      C=R[3];P[3]=BPal[C? SprToScr[C]:T[3]];
+      C=R[4];P[4]=BPal[C? SprToScr[C]:T[4]];
+      C=R[5];P[5]=BPal[C? SprToScr[C]:T[5]];
+      C=R[6];P[6]=BPal[C? SprToScr[C]:T[6]];
+      C=R[7];P[7]=BPal[C? SprToScr[C]:T[7]];
+    }
+  }
+}
+
+/** RefreshLine10() ******************************************/
+/** Refresh line Y (0..191/211) of SCREEN10/11, including   **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine10(register byte Y)
+{
+  register pixel *P;
+  register byte C,X,*T,*R;
+  register int J,K;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,BPal[VDP[7]]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,BPal[VDP[7]]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<8)&ChrTabM&0xFFFF);
+
+    /* Draw first 4 pixels */
+    C=R[0];P[0]=C? XPal[C]:BPal[VDP[7]];
+    C=R[1];P[1]=C? XPal[C]:BPal[VDP[7]];
+    C=R[2];P[2]=C? XPal[C]:BPal[VDP[7]];
+    C=R[3];P[3]=C? XPal[C]:BPal[VDP[7]];
+    R+=4;P+=4;
+
+    for(X=0;X<63;X++,T+=4,R+=4,P+=4)
+    {
+      K=(T[0]&0x07)|((T[1]&0x07)<<3);
+      if(K&0x20) K-=64;
+      J=(T[2]&0x07)|((T[3]&0x07)<<3);
+      if(J&0x20) J-=64;
+
+      C=R[0];Y=T[0]>>3;P[0]=C? XPal[C]:Y&1? XPal[Y>>1]:YJKColor(Y,J,K);
+      C=R[1];Y=T[1]>>3;P[1]=C? XPal[C]:Y&1? XPal[Y>>1]:YJKColor(Y,J,K);
+      C=R[2];Y=T[2]>>3;P[2]=C? XPal[C]:Y&1? XPal[Y>>1]:YJKColor(Y,J,K);
+      C=R[3];Y=T[3]>>3;P[3]=C? XPal[C]:Y&1? XPal[Y>>1]:YJKColor(Y,J,K);
+    }
+  }
+}
+
+/** RefreshLine12() ******************************************/
+/** Refresh line Y (0..191/211) of SCREEN12, including      **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine12(register byte Y)
+{
+  register pixel *P;
+  register byte C,X,*T,*R;
+  register int J,K;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,BPal[VDP[7]]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,BPal[VDP[7]]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<8)&ChrTabM&0xFFFF);
+
+    if(HScroll512&&(HScroll>255)) T=(byte *)((int)T^0x10000);
+    T+=HScroll&0xFC;
+
+    /* Draw first 4 pixels */
+    C=R[0];P[0]=C? XPal[C]:BPal[VDP[7]];
+    C=R[1];P[1]=C? XPal[C]:BPal[VDP[7]];
+    C=R[2];P[2]=C? XPal[C]:BPal[VDP[7]];
+    C=R[3];P[3]=C? XPal[C]:BPal[VDP[7]];
+    R+=4;P+=4;
+
+    for(X=1;X<64;X++,T+=4,R+=4,P+=4)
+    {
+      K=(T[0]&0x07)|((T[1]&0x07)<<3);
+      if(K&0x20) K-=64;
+      J=(T[2]&0x07)|((T[3]&0x07)<<3);
+      if(J&0x20) J-=64;
+
+      C=R[0];P[0]=C? XPal[C]:YJKColor(T[0]>>3,J,K);
+      C=R[1];P[1]=C? XPal[C]:YJKColor(T[1]>>3,J,K);
+      C=R[2];P[2]=C? XPal[C]:YJKColor(T[2]>>3,J,K);
+      C=R[3];P[3]=C? XPal[C]:YJKColor(T[3]>>3,J,K);
+    }
+  }
+}
+
+//#ifdef NARROW
+
+/** RefreshLine6() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN6, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine6(register byte Y)
+{
+  register pixel *P;
+  register byte X,*T,*R,C;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,XPal[BGColor&0x03]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor&0x03]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<7)&ChrTabM&0x7FFF);
+
+    for(X=0;X<32;X++)
+    {
+      C=R[0];P[0]=XPal[C? C:T[0]>>6];
+      C=R[1];P[1]=XPal[C? C:(T[0]>>2)&0x03];
+      C=R[2];P[2]=XPal[C? C:T[1]>>6];
+      C=R[3];P[3]=XPal[C? C:(T[1]>>2)&0x03];
+      C=R[4];P[4]=XPal[C? C:T[2]>>6];
+      C=R[5];P[5]=XPal[C? C:(T[2]>>2)&0x03];
+      C=R[6];P[6]=XPal[C? C:T[3]>>6];
+      C=R[7];P[7]=XPal[C? C:(T[3]>>2)&0x03];
+      R+=8;P+=8;T+=4;
+    }
+  }
+}
+  
+/** RefreshLine7() *******************************************/
+/** Refresh line Y (0..191/211) of SCREEN7, including       **/
+/** sprites in this line.                                   **/
+/*************************************************************/
+static void RefreshLine7(register byte Y)
+{
+  register pixel *P;
+  register byte C,X,*T,*R;
+  byte ZBuf[304];
+
+  P=RefreshBorder(Y,XPal[BGColor]);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,XPal[BGColor]);
+  else
+  {
+    ColorSprites(Y,ZBuf);
+    R=ZBuf+32;
+    T=ChrTab+(((int)(Y+VScroll)<<8)&ChrTabM&0xFFFF);
+
+    for(X=0;X<32;X++)
+    {
+      C=R[0];P[0]=XPal[C? C:T[0]>>4];
+      C=R[1];P[1]=XPal[C? C:T[1]>>4];
+      C=R[2];P[2]=XPal[C? C:T[2]>>4];
+      C=R[3];P[3]=XPal[C? C:T[3]>>4];
+      C=R[4];P[4]=XPal[C? C:T[4]>>4];
+      C=R[5];P[5]=XPal[C? C:T[5]>>4];
+      C=R[6];P[6]=XPal[C? C:T[6]>>4];
+      C=R[7];P[7]=XPal[C? C:T[7]>>4];
+      R+=8;P+=8;T+=8;
+    }
+  }
+}
+
+/** RefreshLineTx80() ****************************************/
+/** Refresh line Y (0..191/211) of TEXT80.                  **/
+/*************************************************************/
+static void RefreshLineTx80(register byte Y)
+{
+  register pixel *P,FC,BC;
+  register byte X,M,*T,*C,*G;
+
+  BC=XPal[BGColor];
+  P=RefreshBorder(Y,BC);
+  if(!P) return;
+
+  if(!ScreenON) ClearLine(P,BC);
+  else
+  {
+    P[0]=P[1]=P[2]=P[3]=P[4]=P[5]=P[6]=P[7]=P[8]=BC;
+    G=(UseFont&&FontBuf? FontBuf:ChrGen)+((Y+VScroll)&0x07);
+    T=ChrTab+((80*(Y>>3))&ChrTabM);
+    C=ColTab+((10*(Y>>3))&ColTabM);
+    P+=9;
+
+    for(X=0,M=0x00;X<80;X++,T++,P+=3)
+    {
+      if(!(X&0x07)) M=*C++;
+      if(M&0x80) { FC=XPal[XFGColor];BC=XPal[XBGColor]; }
+      else       { FC=XPal[FGColor];BC=XPal[BGColor]; }
+      M<<=1;
+      Y=*(G+((int)*T<<3));
+      P[0]=Y&0xC0? FC:BC;
+      P[1]=Y&0x30? FC:BC;
+      P[2]=Y&0x0C? FC:BC;
+    }
+
+    P[0]=P[1]=P[2]=P[3]=P[4]=P[5]=P[6]=XPal[BGColor];
+  }
+}
+
+//#endif /* NARROW */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/** RdZ80() **************************************************/
+/** Z80 emulation calls this function to read a byte from   **/
+/** address A of Z80 address space. Now moved to Z80.c and  **/
+/** made inlined to speed things up.                        **/
+/*************************************************************/
+byte RdZ80(word A)
+{
+  if(A!=0xFFFF) return(RAM[A>>13][A&0x1FFF]);
+  else return(PSL[3]==3? ~SSLReg:RAM[7][0x1FFF]);
+}
+
+
+/** WrZ80() **************************************************/
+/** Z80 emulation calls this function to write byte V to    **/
+/** address A of Z80 address space.                         **/
+/*************************************************************/
+void WrZ80(word A,byte V)
+{
+  if(A!=0xFFFF)
+  {
+    if(EnWrite[A>>14]) RAM[A>>13][A&0x1FFF]=V;
+    else if((A>0x3FFF)&&(A<0xC000)) MapROM(A,V);
+  }
+  else
+  {
+    if(PSL[3]==3) SSlot(V);
+    else if(EnWrite[3]) RAM[7][A&0x1FFF]=V;
+  }
+}
+
+/** InZ80() **************************************************/
+/** Z80 emulation calls this function to read a byte from   **/
+/** a given I/O port.                                       **/
+/*************************************************************/
+byte InZ80(word Port)
+{
+  /* MSX only uses 256 IO ports */
+  Port&=0xFF;
+
+  /* Return an appropriate port value */
+  switch(Port)
+  {
+
+case 0x90: return(0xFD);                   /* Printer READY signal */
+case 0xB5: return(RTCIn(RTCReg));          /* RTC registers        */
+
+case 0xA8: /* Primary slot state   */
+case 0xA9: /* Keyboard port        */
+case 0xAA: /* General IO register  */
+case 0xAB: /* PPI control register */
+  PPI.Rin[1]=KeyMap[PPI.Rout[2]&0x0F];
+  return(Read8255(&PPI,Port-0xA8));
+
+case 0xFC: /* Mapper page at 0000h */
+case 0xFD: /* Mapper page at 4000h */
+case 0xFE: /* Mapper page at 8000h */
+case 0xFF: /* Mapper page at C000h */
+  return(RAMMapper[Port-0xFC]|~RAMMask);
+
+case 0xD9: /* Kanji support */
+  Port=Kanji? Kanji[KanLetter+KanCount]:NORAM;
+  KanCount=(KanCount+1)&0x1F;
+  return(Port);
+
+case 0x80: /* SIO data */
+case 0x81:
+case 0x82:
+case 0x83:
+case 0x84:
+case 0x85:
+case 0x86:
+case 0x87:
+  return(NORAM);
+  /*return(Rd8251(&SIO,Port&0x07));*/
+
+case 0x98: /* VRAM read port */
+  /* Read from VRAM data buffer */
+  Port=VDPData;
+  /* Reset VAddr latch sequencer */
+  VKey=1;
+  /* Fill data buffer with a new value */
+  VDPData=VPAGE[VAddr];
+  /* Increment VRAM address */
+  VAddr=(VAddr+1)&0x3FFF;
+  /* If rolled over, modify VRAM page# */
+  if(!VAddr&&(ScrMode>3))
+  {
+    VDP[14]=(VDP[14]+1)&(VRAMPages-1);
+    VPAGE=VRAM+((int)VDP[14]<<14);
+  }
+  return(Port);
+
+case 0x99: /* VDP status registers */
+  /* Read an appropriate status register */
+  Port=VDPStatus[VDP[15]];
+  /* Reset VAddr latch sequencer */
+  VKey=1;
+  /* Update status register's contents */
+  switch(VDP[15])
+  {
+    case 0: VDPStatus[0]&=0x5F;SetIRQ(~INT_IE0);break;
+    case 1: VDPStatus[1]&=0xFE;SetIRQ(~INT_IE1);break;
+    case 7: VDPStatus[7]=VDP[44]=VDPRead();break;
+  }
+  /* Return the status register value */
+  return(Port);
+
+case 0xA2: /* PSG input port */
+  /* PSG[14] returns joystick/mouse data */
+  if(PSG.Latch==14)
+  {
+    int DX,DY,L;
+
+    /* Number of a joystick port */
+    Port=PSG.R[15]&0x40? 1:0;
+    L=Port? JoyTypeB:JoyTypeA;
+
+    /* If no joystick, return dummy value */
+    if(!L) return(0x7F);
+
+    /* @@@ For debugging purposes */
+    /*printf("Reading from PSG[14]: MCount[%d]=%d PSG[15]=%02Xh Value=",Port,MCount[Port],PSG.R[15]);*/
+
+    /* Poll mouse position, if needed */
+    if((L==2)||(MCount[Port]==1))
+    {
+      /* Read new mouse coordinates */
+      L=Mouse(Port);
+      Buttons[Port]=(~L>>12)&0x30;
+      DY=(L>>8)&0xFF;
+      DX=L&0xFF;
+
+      /* Compute offsets and store coordinates  */
+      L=OldMouseX[Port]-DX;OldMouseX[Port]=DX;DX=L;
+      L=OldMouseY[Port]-DY;OldMouseY[Port]=DY;DY=L;
+
+      /* Adjust offsets */
+      MouseDX[Port]=(DX>127? 127:(DX<-127? -127:DX))&0xFF;
+      MouseDY[Port]=(DY>127? 127:(DY<-127? -127:DY))&0xFF;
+    }
+
+    /* Determine return value */
+    switch(MCount[Port])
+    {
+      case 0: /* Normal joystick */
+        if(PSG.R[15]&(Port? 0x20:0x10)) Port=0x3F;
+        else
+          if((Port? JoyTypeB:JoyTypeA)<2) Port=~Joystick(Port)&0x3F;
+          else Port=Buttons[Port]
+                   |(MouseDX[Port]? (MouseDX[Port]<128? 0x08:0x04):0x0C)
+                   |(MouseDY[Port]? (MouseDY[Port]<128? 0x02:0x01):0x03);
+        break;
+
+      case 1: Port=(MouseDX[Port]>>4)|Buttons[Port];break;
+      case 2: Port=(MouseDX[Port]&0x0F)|Buttons[Port];break;
+      case 3: Port=(MouseDY[Port]>>4)|Buttons[Port];break;
+      case 4: Port=(MouseDY[Port]&0x0F)|Buttons[Port];break;
+    }
+
+    /* @@@ For debugging purposes */
+    /*printf("%02Xh\n",Port|0x40);*/
+
+    /* 6th bit is always 1 */
+    return(Port|0x40);
+  }
+
+  /* PSG[15] resets mouse counters */
+  if(PSG.Latch==15)
+  {
+    /* @@@ For debugging purposes */
+    /*printf("Reading from PSG[15]\n");*/
+
+    /*MCount[0]=MCount[1]=0;*/
+    return(PSG.R[15]&0xF0);
+  }
+
+  /* Return PSG[0-13] as they are */
+  return(RdData8910(&PSG));
+}
+
+  /* Return NORAM for non-existing ports */
+  return(NORAM);
+}
+
+/** OutZ80() *************************************************/
+/** Z80 emulation calls this function to write byte V to a  **/
+/** given I/O port.                                         **/
+/*************************************************************/
+void OutZ80(word Port,byte Value)
+{
+  register byte I,J,K;  
+
+  Port&=0xFF;
+  switch(Port)
+  {
+
+case 0x7C: WrCtrl2413(&OPLL,Value);return;        /* OPLL Register# */
+case 0x7D: WrData2413(&OPLL,Value);return;        /* OPLL Data      */
+case 0x91: Printer(Value);return;                 /* Printer Data   */
+case 0xA0: WrCtrl8910(&PSG,Value);return;         /* PSG Register#  */
+case 0xB4: RTCReg=Value&0x0F;return;              /* RTC Register#  */ 
+
+case 0xD8: /* Upper bits of Kanji ROM address */
+  KanLetter=(KanLetter&0x1F800)|((int)(Value&0x3F)<<5);
+  KanCount=0;
+  return;
+
+case 0xD9: /* Lower bits of Kanji ROM address */
+  KanLetter=(KanLetter&0x007E0)|((int)(Value&0x3F)<<11);
+  KanCount=0;
+  return;
+
+case 0x80: /* SIO data */
+case 0x81:
+case 0x82:
+case 0x83:
+case 0x84:
+case 0x85:
+case 0x86:
+case 0x87:
+  return;
+  /*Wr8251(&SIO,Port&0x07,Value);
+  return;*/
+
+case 0x98: /* VDP Data */
+  VKey=1;
+  if(WKey)
+  {
+    /* VDP set for writing */
+    VDPData=VPAGE[VAddr]=Value;
+    VAddr=(VAddr+1)&0x3FFF;
+  }
+  else
+  {
+    /* VDP set for reading */
+    VDPData=VPAGE[VAddr];
+    VAddr=(VAddr+1)&0x3FFF;
+    VPAGE[VAddr]=Value;
+  }
+  /* If VAddr rolled over, modify VRAM page# */
+  if(!VAddr&&(ScrMode>3)) 
+  {
+    VDP[14]=(VDP[14]+1)&(VRAMPages-1);
+    VPAGE=VRAM+((int)VDP[14]<<14);
+  }
+  return;
+
+case 0x99: /* VDP Address Latch */
+  if(VKey) { ALatch=Value;VKey=0; }
+  else
+  {
+    VKey=1;
+    switch(Value&0xC0)
+    {
+      case 0x80:
+        /* Writing into VDP registers */
+        VDPOut(Value&0x3F,ALatch);
+        break;
+      case 0x00:
+      case 0x40:
+        /* Set the VRAM access address */
+        VAddr=(((word)Value<<8)+ALatch)&0x3FFF;
+        /* WKey=1 when VDP set for writing into VRAM */
+        WKey=Value&0x40;
+        /* When set for reading, perform first read */
+        if(!WKey)
+        {
+          VDPData=VPAGE[VAddr];
+          VAddr=(VAddr+1)&0x3FFF;
+          if(!VAddr&&(ScrMode>3))
+          {
+            VDP[14]=(VDP[14]+1)&(VRAMPages-1);
+            VPAGE=VRAM+((int)VDP[14]<<14);
+          }
+        }
+        break;
+    }
+  }
+  return;
+
+case 0x9A: /* VDP Palette Latch */
+  if(PKey) { PLatch=Value;PKey=0; }
+  else
+  {
+    byte R,G,B;
+    /* New palette entry written */
+    PKey=1;
+    J=VDP[16];
+    /* Compute new color components */
+    R=(PLatch&0x70)*255/112;
+    G=(Value&0x07)*255/7;
+    B=(PLatch&0x07)*255/7;
+    /* Set new color for palette entry J */
+    Palette[J]=RGB2INT(R,G,B);
+    SetColor(J,R,G,B);
+    /* Next palette entry */
+    VDP[16]=(J+1)&0x0F;
+  }
+  return;
+
+case 0x9B: /* VDP Register Access */
+  J=VDP[17]&0x3F;
+  if(J!=17) VDPOut(J,Value);
+  if(!(VDP[17]&0x80)) VDP[17]=(J+1)&0x3F;
+  return;
+
+case 0xA1: /* PSG Data */
+  /* PSG[15] is responsible for joystick/mouse */
+  if(PSG.Latch==15)
+  {
+    /* @@@ For debugging purposes */
+    /*printf("Writing PSG[15] <- %02Xh\n",Value);*/
+
+    /* For mouse, update nibble counter      */
+    /* For joystick, set nibble counter to 0 */
+    if((Value&0x0C)==0x0C) MCount[1]=0;
+    else if((JoyTypeB>2)&&((Value^PSG.R[15])&0x20))
+           MCount[1]+=MCount[1]==4? -3:1;
+
+    /* For mouse, update nibble counter      */
+    /* For joystick, set nibble counter to 0 */
+    if((Value&0x03)==0x03) MCount[0]=0;
+    else if((JoyTypeA>2)&&((Value^PSG.R[15])&0x10))
+           MCount[0]+=MCount[0]==4? -3:1;
+  }
+
+  /* Put value into a register */
+  WrData8910(&PSG,Value);
+  return;
+
+case 0xB5: /* RTC Data */
+  if(RTCReg<13)
+  {
+    /* J = register bank# now */
+    J=RTCMode&0x03;
+    /* Store the value */
+    RTC[J][RTCReg]=Value;
+    /* If CMOS modified, we need to save it */
+    if(J>1) SaveCMOS=1;
+    return;
+  }
+  /* RTC[13] is a register bank# */
+  if(RTCReg==13) RTCMode=Value;
+  return;
+
+case 0xA8: /* Primary slot state   */
+case 0xA9: /* Keyboard port        */
+case 0xAA: /* General IO register  */
+case 0xAB: /* PPI control register */
+  /* Write to PPI */
+  Write8255(&PPI,Port-0xA8,Value);
+  /* If general I/O register has changed... */
+  if(PPI.Rout[2]!=IOReg) { PPIOut(PPI.Rout[2],IOReg);IOReg=PPI.Rout[2]; }
+  /* If primary slot state has changed... */
+  if(PPI.Rout[0]!=PSLReg)
+    for(J=0,PSLReg=Value=PPI.Rout[0];J<4;J++,Value>>=2)
+    {
+      PSL[J]=Value&3;I=J<<1;
+      K=PSL[J]==3? SSL[J]:0;
+      EnWrite[J]=(K==2)&&(MemMap[3][2][I]!=EmptyRAM);
+      RAM[I]=MemMap[PSL[J]][K][I];
+      RAM[I+1]=MemMap[PSL[J]][K][I+1];
+    }
+  /* Done */  
+  return;
+
+case 0xFC: /* Mapper page at 0000h */
+case 0xFD: /* Mapper page at 4000h */
+case 0xFE: /* Mapper page at 8000h */
+case 0xFF: /* Mapper page at C000h */
+  J=Port-0xFC;
+  Value&=RAMMask;
+  if(RAMMapper[J]!=Value)
+  {
+    if(Verbose&0x08) {
+      //printf("RAM-MAPPER: block %d at %Xh\n",Value,J*0x4000);
+      emu_printf("RAM-MAPPER: block");
+      emu_printi(Value);
+      emu_printi(J*0x4000);
+    } 
+    I=J<<1;
+    RAMMapper[J]      = Value;
+    MemMap[3][2][I]   = RAMData+((int)Value<<14);
+    MemMap[3][2][I+1] = MemMap[3][2][I]+0x2000;
+    if((PSL[J]==3)&&(SSL[J]==2))
+    {
+      EnWrite[J] = 1;
+      RAM[I]     = MemMap[3][2][I];
+      RAM[I+1]   = MemMap[3][2][I+1];
+    }
+  }
+  return;
+
+  }
+}
+
+/** MapROM() *************************************************/
+/** Switch ROM Mapper pages. This function is supposed to   **/
+/** be called when ROM page registers are written to.       **/
+/*************************************************************/
+void MapROM(register word A,register byte V)
+{
+  byte I,J,K,*P;
+
+/* @@@ For debugging purposes
+printf("(%04Xh) = %02Xh at PC=%04Xh\n",A,V,CPU.PC.W);
+*/
+
+  /* J contains 16kB page number 0-3  */
+  J=A>>14;
+
+  /* I contains slot number 0/1  */
+  if(PSL[J]==1) I=0;
+  else if(PSL[J]==2) I=1;
+       else return;
+
+  /* K contains MegaROM type */
+  K=I? ROMTypeB:ROMTypeA;
+
+  /* SCC: enable/disable for no cart */
+  if(!ROMData[I]&&(A==0x9000)) SCCOn[I]=(V==0x3F)? 1:0;
+
+  /* SCC: types 0, 2, or no cart */
+  if(((A&0xFF00)==0x9800)&&SCCOn[I])
+  {
+    /* Compute SCC register number */
+    J=A&0x00FF;
+
+    /* When no MegaROM present, we allow the program */
+    /* to write into SCC wave buffer using EmptyRAM  */
+    /* as a scratch pad.                             */
+    if(!ROMData[I]&&(J<0x80)) EmptyRAM[0x1800+J]=V;
+
+    /* Output data to SCC chip */
+    WriteSCC(&SCChip,J,V);
+    return;
+  }
+
+  /* SCC+: types 0, 2, or no cart */
+  if(((A&0xFF00)==0xB800)&&SCCOn[I])
+  {
+    /* Compute SCC register number */
+    J=A&0x00FF;
+
+    /* When no MegaROM present, we allow the program */
+    /* to write into SCC wave buffer using EmptyRAM  */
+    /* as a scratch pad.                             */
+    if(!ROMData[I]&&(J<0xA0)) EmptyRAM[0x1800+J]=V;
+
+    /* Output data to SCC chip */
+    WriteSCCP(&SCChip,J,V);
+    return;
+  }
+
+  /* If no cartridge or no mapper, exit */
+  if(!ROMData[I]||!ROMMask[I]) return;
+
+  switch(K)
+  {
+    case 0: /*** Generic 8kB cartridges (Konami, etc.) ***/
+      if((A<0x4000)||(A>0xBFFF)) return;
+      J=(A-0x4000)>>13;
+      /* Turn SCC on/off on writes to 8000h-9FFFh */
+      if(J==2) SCCOn[I]=(V==0x3F)? 1:0;
+      /* Switch ROM pages */
+      V&=ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        RAM[J+2]=MemMap[I+1][0][J+2]=ROMData[I]+((int)V<<13);
+        ROMMapper[I][J]=V;
+      }
+      break;
+
+    case 1: /*** Generic 16kB cartridges (MSXDOS2, HoleInOneSpecial) ***/
+      if((A<0x4000)||(A>0xBFFF)) return;
+      J=(A&0x8000)>>14;
+      V=(V<<1)&ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        RAM[J+2]=MemMap[I+1][0][J+2]=ROMData[I]+((int)V<<13);
+        RAM[J+3]=MemMap[I+1][0][J+3]=RAM[2]+0x2000;
+        ROMMapper[I][J]=V;
+      }
+      break;
+
+    case 2: /*** KONAMI5 8kB cartridges ***/
+      if((A<0x5000)||(A>0xB000)||((A&0x1FFF)!=0x1000)) return;
+      J=(A-0x5000)>>13;
+      /* Turn SCC on/off on writes to 9000h */
+      if(J==2) SCCOn[I]=(V==0x3F)? 1:0;
+      /* Switch ROM pages */
+      V&=ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        RAM[J+2]=MemMap[I+1][0][J+2]=ROMData[I]+((int)V<<13);
+        ROMMapper[I][J]=V;
+      }
+      break;
+
+    case 3: /*** KONAMI4 8kB cartridges ***/
+      /* Page at 4000h is fixed */
+      if((A<0x6000)||(A>0xA000)||(A&0x1FFF)) return;
+      J=(A-0x4000)>>13;
+      V&=ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        RAM[J+2]=MemMap[I+1][0][J+2]=ROMData[I]+((int)V<<13);
+        ROMMapper[I][J]=V;
+      }
+      break;
+
+    case 4: /*** ASCII 8kB cartridges ***/
+      if((A<0x6000)||(A>0x7FFF)) return;
+      J=(A&0x1800)>>11;
+      V&=ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        P=ROMData[I]+((int)V<<13);
+        MemMap[I+1][0][J+2]=P;
+        ROMMapper[I][J]=V;
+        /* Only update memory when cartridge's slot selected */
+        if(PSL[(J>>1)+1]==I+1) RAM[J+2]=P;
+      }
+      break;
+
+    case 5: /*** ASCII 16kB cartridges ***/
+      if((A<0x6000)||(A>0x7FFF)) return;
+      J=(A&0x1000)>>11;
+      V=(V<<1)&ROMMask[I];
+      if(V!=ROMMapper[I][J])
+      {
+        P=ROMData[I]+((int)V<<13);
+        MemMap[I+1][0][J+2]=P;
+        MemMap[I+1][0][J+3]=P+0x2000;
+        ROMMapper[I][J]=V;
+        /* Only update memory when cartridge's slot selected */
+        if(PSL[(J>>1)+1]==I+1)
+        {
+          RAM[J+2]=P;
+          RAM[J+3]=P+0x2000;
+        }
+      }
+      break;
+
+    case 6: /*** GameMaster2+SRAM cartridge ***/
+      /* Switch ROM and SRAM pages, page at 4000h is fixed */
+      if((A>=0x6000)&&(A<=0xA000)&&!(A&0x1FFF))
+      {
+        /* If changing SRAM page... */
+        if(V&0x10)
+        {
+          /* Select SRAM page */
+          RAM[5]=MemMap[I+1][0][5]=(SRAM? SRAM:EmptyRAM)+(V&0x20? 0x2000:0);
+          /* SRAM is now on */
+          ROMMapper[I][3]=0xFF;
+        }
+        else
+        {
+          /* Figure out which ROM page gets switched */
+          J=(A-0x4000)>>13;
+          /* Compute new ROM page number */
+          V&=ROMMask[I];
+          /* If ROM page number has changed... */
+          if(V!=ROMMapper[I][J])
+          {
+            RAM[J+2]=MemMap[I+1][0][J+2]=ROMData[I]+((int)V<<13);
+            ROMMapper[I][J]=V;
+          }
+        }
+        /* Done with page switch */
+        break;
+      }
+      /* Write to SRAM */
+      if((A>=0xB000)&&(A<0xC000)&&(ROMMapper[I][3]==0xFF))
+      {
+        RAM[5][(A&0x0FFF)|0x1000]=RAM[5][A&0x0FFF]=V;
+        SaveSRAM=1;
+        break;
+      }
+      /* Done */
+      return;
+
+    default: /*** No MegaROM mapper by default ***/
+      return; 
+  }
+
+  if(Verbose&0x08)
+  {
+    /* K=1 for 16kB pages */
+    K=(K==1)||(K==5);
+
+    //printf
+    //(
+    //  "ROM-MAPPER %c: %dkB block %d at %04Xh\n",
+    //  I+'A',8*(K+1),K? (V>>1):V,J*0x2000+0x4000
+    //);
+  }
+}
+
+/** SSlot() **************************************************/
+/** Switch secondary memory slots. This function is called  **/
+/** when value in (FFFFh) changes.                          **/
+/*************************************************************/
+void SSlot(register byte V)
+{
+  register byte I,J;
+  
+  if(SSLReg!=V)
+  {
+    SSLReg=V;
+
+    for(J=0;J<4;J++,V>>=2)
+    {
+      SSL[J]=V&3;
+      if(PSL[J]==3)
+      {
+        I=J<<1;
+        EnWrite[J]=(SSL[J]==2)&&(MemMap[3][2][I]!=EmptyRAM);
+        RAM[I]=MemMap[3][SSL[J]][I];
+        RAM[I+1]=MemMap[3][SSL[J]][I+1];
+      }
+    }
+  }
+}
+
+
+/** LoadROM() ************************************************/
+/** Load a file, allocating memory as needed. Returns addr. **/
+/** of the alocated space or 0 if failed.                   **/
+/*************************************************************/
+byte *LoadROM(const char *Name,int Size,byte *Buf)
+{
+  byte *P;
+
+  /* Can't give address without size! */
+  if(Buf&&!Size) return(0);
+
+  Size = emu_FileSize(Name);
+  emu_printi(Size);
+
+  if (Size<=0) return (0);
+  
+  P=Buf? Buf:emu_Malloc(Size);
+  emu_LoadFile(Name, P, Size);
+
+  //Add a new chunk to free 
+  if(!Buf) Chunks[CCount++]=P;
+
+  return(P);
+}
+
+/** LoadCARTROM() ********************************************/
+/** Load a file. Returns addr where loaded.                 **/
+/*************************************************************/
+byte *LoadCARTROM(const char *Name,int Size,byte *Buf)
+{
+  byte *P;
+
+  Size = emu_FileSize(Name);
+  emu_printi(Size);
+
+  if (Size<=0) return (0);
+
+  if (Buf)
+  {
+    P=Buf;
+    emu_printf("Loading to ram");
+    emu_LoadFile(Name, P, Size);
+    //byte * FP = (byte *)flash_load(Name);
+    //flash_verify(P,Size);
+    return P; 
+  }
+  else
+  {
+    emu_printf("Loading to flash");
+    flash_load(Name);
+    P = (byte *)flash_start;
+    return P; 
+  }
+}
+
+/** LoadCart() ***********************************************/
+/** Load a cartridge ROM from .ROM file into given slot.    **/
+/*************************************************************/
+int LoadCart(const char *Name,int Slot)
+{
+  char C1,C2;
+  int C3,ROM64,LastFirst;
+
+  /* Check slot #, try to open file */
+  if((Slot!=0)&&(Slot!=1)) return(0);
+
+  int Size = emu_FileSize(Name);
+
+  int f = emu_FileOpen(Name,"r+b");
+  if(!f) return(0);
+  if(Verbose) emu_printf(Name);
+  if(Verbose) emu_printi(Size);
+
+  /* Check "AB" signature in a file */
+  ROM64=LastFirst=0;
+  emu_FileRead(&C1,1,f);
+  emu_FileRead(&C2,1,f);
+
+  /* Maybe this is a flat 64kB ROM? */
+  if((C1!='A')||(C2!='B')) {
+    if(Verbose) emu_printf("check next");
+    if(emu_FileSeek(f,0x4000,0)>=0)
+    {
+      emu_FileRead(&C1,1,f);
+      emu_FileRead(&C2,1,f);
+      ROM64=(C1=='A')&&(C2=='B');
+    }    
+  }
+
+  /* Maybe it is the last page that contains "AB" signature? */
+  if((C1!='A')||(C2!='B')) {
+    if(Verbose) emu_printf("check next");
+    if(emu_FileSeek(f,Size-0x4000,0)>=0)
+    {
+      emu_FileRead(&C1,1,f);
+      emu_FileRead(&C2,1,f);
+      LastFirst=(C1=='A')&&(C2=='B');
+    }    
+  }
+
+  /* If we can't find "AB" signature, drop out */     
+  if((C1!='A')||(C2!='B'))
+  {
+    if(Verbose) emu_printf("  Not a valid cartridge ROM");
+    emu_FileClose(f);
+    return(0);
+  }
+
+  if(Verbose) {
+    emu_printf(" Cartridge");
+    char slot[2] = {0,0};
+    slot[0] = 'A'+Slot;
+    emu_printf(slot);
+  } 
+
+
+
+  /* Length must be a multiple of 8kB */
+  /* Flat 64kB ROM must be 40..64kB */
+  //if(Size&0x1FFF)           { emu_printf("failed");return(0); }
+  //if(ROM64&&(Size<0xA000))  { emu_printf("failed");return(0); }
+  //if(ROM64&&(Size>0x10000)) { emu_printf("failed");return(0); }
+
+  /* Show ROM type and size */
+  //if(Verbose)
+  //  printf
+  //  (
+  //    "%dkB %s ROM...",C1/1024,
+  //    !ROM64&&(C1>0x8000)? ROMNames[Slot? ROMTypeB:ROMTypeA]:"NORMAL"
+  //  );
+
+  /* Compute size in 8kB pages */
+  Size >>= 13;
+
+  /* Calculate 2^n closest to number of pages */
+  for(C3=1;C3<Size;C3<<=1);
+
+  /* Assign ROMMask for MegaROMs */
+  ROMMask[Slot]=!ROM64&&(Size>4)? C3-1:0x00;
+
+  if ((Size*0x2000) <= 32768) 
+  {
+    // Allocate space for the ROM
+    ROMData[Slot]=emu_Malloc(C3*0x2000);
+    if(!ROMData[Slot]) { 
+      emu_printf("failed");
+      return(0); 
+    }
+    Chunks[CCount++]=ROMData[Slot];
+
+    // Try loading ROM
+    byte * P = LoadCARTROM(Name,Size*0x2000,ROMData[Slot]);
+    if(!P) { 
+      emu_printf("failed");
+      return(0); 
+    }
+    ROMData[Slot] = P;
+    // Mirror ROM if it is smaller than 2^n pages 
+    if(Size<C3) { 
+      emu_printf("mirroring rom");
+      memcpy
+      (
+        ROMData[Slot]+Size*0x2000,
+        ROMData[Slot]+(Size-C3/2)*0x2000,
+        (C3-Size)*0x2000
+      ); 
+    }
+  }
+  else 
+  {
+    ROMData[Slot] = LoadCARTROM(Name,Size*0x2000,NULL);
+  }
+
+
+  /* Set memory map depending on the ROM size */
+  switch(Size)
+  {
+    case 1:
+      /* 8kB ROMs are mirrored 8 times: 0:0:0:0:0:0:0:0 */
+      MemMap[Slot+1][0][0]=ROMData[Slot];
+      MemMap[Slot+1][0][1]=ROMData[Slot];
+      MemMap[Slot+1][0][2]=ROMData[Slot];
+      MemMap[Slot+1][0][3]=ROMData[Slot];
+      MemMap[Slot+1][0][4]=ROMData[Slot];
+      MemMap[Slot+1][0][5]=ROMData[Slot];
+      MemMap[Slot+1][0][6]=ROMData[Slot];
+      MemMap[Slot+1][0][7]=ROMData[Slot];
+      break;
+
+    case 2:
+      /* 16kB ROMs are mirrored 4 times: 0:1:0:1:0:1:0:1 */
+      MemMap[Slot+1][0][0]=ROMData[Slot];
+      MemMap[Slot+1][0][1]=ROMData[Slot]+0x2000;
+      MemMap[Slot+1][0][2]=ROMData[Slot];
+      MemMap[Slot+1][0][3]=ROMData[Slot]+0x2000;
+      MemMap[Slot+1][0][4]=ROMData[Slot];
+      MemMap[Slot+1][0][5]=ROMData[Slot]+0x2000;
+      MemMap[Slot+1][0][6]=ROMData[Slot];
+      MemMap[Slot+1][0][7]=ROMData[Slot]+0x2000;
+      break;
+
+    case 3:
+    case 4:
+      /* 24kB and 32kB ROMs are mirrored twice: 0:1:0:1:2:3:2:3 */
+      MemMap[Slot+1][0][0]=ROMData[Slot];
+      MemMap[Slot+1][0][1]=ROMData[Slot]+0x2000;
+      MemMap[Slot+1][0][2]=ROMData[Slot];
+      MemMap[Slot+1][0][3]=ROMData[Slot]+0x2000;
+      MemMap[Slot+1][0][4]=ROMData[Slot]+0x4000;
+      MemMap[Slot+1][0][5]=ROMData[Slot]+0x6000;
+      MemMap[Slot+1][0][6]=ROMData[Slot]+0x4000;
+      MemMap[Slot+1][0][7]=ROMData[Slot]+0x6000;
+      break;
+
+    default:
+      if(ROM64)
+      {
+        /* 64kB ROMs are loaded to fill slot: 0:1:2:3:4:5:6:7 */
+        MemMap[Slot+1][0][0]=ROMData[Slot];
+        MemMap[Slot+1][0][1]=ROMData[Slot]+0x2000;
+        MemMap[Slot+1][0][2]=ROMData[Slot]+0x4000;
+        MemMap[Slot+1][0][3]=ROMData[Slot]+0x6000;
+        MemMap[Slot+1][0][4]=ROMData[Slot]+0x8000;
+        MemMap[Slot+1][0][5]=ROMData[Slot]+0xA000;
+        MemMap[Slot+1][0][6]=ROMData[Slot]+0xC000;
+        MemMap[Slot+1][0][7]=ROMData[Slot]+0xE000;
+      }
+      else
+      {
+        /* MegaROMs are switched into 4000h-BFFFh */
+        if(!LastFirst) SetMegaROM(Slot,0,1,2,3);
+        else SetMegaROM(Slot,Size-2,Size-1,Size-2,Size-1);
+      }
+      break;
+  }
+
+  /* Show starting address */
+  if(Verbose) {
+    emu_printf("starts at");
+    emu_printi(MemMap[Slot+1][0][2][2]+256*MemMap[Slot+1][0][2][3]);    
+  }
+
+
+  /* Done loading cartridge */
+  return(1);
+}
+
+
+
+/** SetIRQ() *************************************************/
+/** Set or reset IRQ. Returns IRQ vector assigned to        **/
+/** CPU.IRequest. When upper bit of IRQ is 1, IRQ is reset. **/
+/*************************************************************/
+word SetIRQ(register byte IRQ)
+{
+  if(IRQ&0x80) IRQPending&=IRQ; else IRQPending|=IRQ;
+  CPU.IRequest=IRQPending? INT_IRQ:INT_NONE;
+  return(CPU.IRequest);
+}
+
+/** SetScreen() **********************************************/
+/** Change screen mode. Returns new screen mode.            **/
+/*************************************************************/
+byte SetScreen(void)
+{
+  register byte I,J;
+
+  switch(((VDP[0]&0x0E)>>1)|(VDP[1]&0x18))
+  {
+    case 0x10: J=0;break;
+    case 0x00: J=1;break;
+    case 0x01: J=2;break;
+    case 0x08: J=3;break;
+    case 0x02: J=4;break;
+    case 0x03: J=5;break;
+    case 0x04: J=6;break;
+    case 0x05: J=7;break;
+    case 0x07: J=8;break;
+    case 0x12: J=MAXSCREEN+1;break;
+    default:   J=ScrMode;break;
+  }
+
+  /* Recompute table addresses */
+  I=(J>6)&&(J!=MAXSCREEN+1)? 11:10;
+  ChrTab  = VRAM+((int)(VDP[2]&MSK[J].R2)<<I);
+  ChrGen  = VRAM+((int)(VDP[4]&MSK[J].R4)<<11);
+  ColTab  = VRAM+((int)(VDP[3]&MSK[J].R3)<<6)+((int)VDP[10]<<14);
+  SprTab  = VRAM+((int)(VDP[5]&MSK[J].R5)<<7)+((int)VDP[11]<<15);
+  SprGen  = VRAM+((int)VDP[6]<<11);
+  ChrTabM = ((int)(VDP[2]|~MSK[J].M2)<<I)|((1<<I)-1);
+  ChrGenM = ((int)(VDP[4]|~MSK[J].M4)<<11)|0x007FF;
+  ColTabM = ((int)(VDP[3]|~MSK[J].M3)<<6)|0x1C03F;
+  SprTabM = ((int)(VDP[5]|~MSK[J].M5)<<7)|0x1807F;
+
+  /* Return new screen mode */
+  ScrMode=J;
+  return(J);
+}
+
+/** SetMegaROM() *********************************************/
+/** Set MegaROM pages for a given slot. SetMegaROM() always **/
+/** assumes 8kB pages.                                      **/
+/*************************************************************/
+void SetMegaROM(int Slot,byte P0,byte P1,byte P2,byte P3)
+{
+  P0&=ROMMask[Slot];
+  P1&=ROMMask[Slot];
+  P2&=ROMMask[Slot];
+  P3&=ROMMask[Slot];
+  MemMap[Slot+1][0][2]=ROMData[Slot]+P0*0x2000;
+  MemMap[Slot+1][0][3]=ROMData[Slot]+P1*0x2000;
+  MemMap[Slot+1][0][4]=ROMData[Slot]+P2*0x2000;
+  MemMap[Slot+1][0][5]=ROMData[Slot]+P3*0x2000;
+  ROMMapper[Slot][0]=P0;
+  ROMMapper[Slot][1]=P1;
+  ROMMapper[Slot][2]=P2;
+  ROMMapper[Slot][3]=P3;
+}
+
+/** VDPOut() *************************************************/
+/** Write value into a given VDP register.                  **/
+/*************************************************************/
+void VDPOut(register byte R,register byte V)
+{ 
+  register byte J;
+
+  switch(R)  
+  {
+    case  0: /* Reset HBlank interrupt if disabled */
+             if((VDPStatus[1]&0x01)&&!(V&0x10))
+             {
+               VDPStatus[1]&=0xFE;
+               SetIRQ(~INT_IE1);
+             }
+             /* Set screen mode */
+             if(VDP[0]!=V) { VDP[0]=V;SetScreen(); }
+             break;
+    case  1: /* Set/Reset VBlank interrupt if enabled or disabled */
+             if(VDPStatus[0]&0x80) SetIRQ(V&0x20? INT_IE0:~INT_IE0);
+             /* Set screen mode */
+             if(VDP[1]!=V) { VDP[1]=V;SetScreen(); }
+             break;
+    case  2: J=(ScrMode>6)&&(ScrMode!=MAXSCREEN+1)? 11:10;
+             ChrTab  = VRAM+((int)(V&MSK[ScrMode].R2)<<J);
+             ChrTabM = ((int)(V|~MSK[ScrMode].M2)<<J)|((1<<J)-1);
+             break;
+    case  3: ColTab  = VRAM+((int)(V&MSK[ScrMode].R3)<<6)+((int)VDP[10]<<14);
+             ColTabM = ((int)(V|~MSK[ScrMode].M3)<<6)|0x1C03F;
+             break;
+    case  4: ChrGen  = VRAM+((int)(V&MSK[ScrMode].R4)<<11);
+             ChrGenM = ((int)(V|~MSK[ScrMode].M4)<<11)|0x007FF;
+             break;
+    case  5: SprTab  = VRAM+((int)(V&MSK[ScrMode].R5)<<7)+((int)VDP[11]<<15);
+             SprTabM = ((int)(V|~MSK[ScrMode].M5)<<7)|0x1807F;
+             break;
+    case  6: V&=0x3F;SprGen=VRAM+((int)V<<11);break;
+    case  7: FGColor=V>>4;BGColor=V&0x0F;break;
+    case 10: V&=0x07;
+             ColTab=VRAM+((int)(VDP[3]&MSK[ScrMode].R3)<<6)+((int)V<<14);
+             break;
+    case 11: V&=0x03;
+             SprTab=VRAM+((int)(VDP[5]&MSK[ScrMode].R5)<<7)+((int)V<<15);
+             break;
+    case 14: V&=VRAMPages-1;VPAGE=VRAM+((int)V<<14);
+             break;
+    case 15: V&=0x0F;break;
+    case 16: V&=0x0F;PKey=1;break;
+    case 17: V&=0xBF;break;
+    case 25: VDP[25]=V;
+             SetScreen();
+             break;
+    case 44: VDPWrite(V);break;
+    case 46: VDPDraw(V);break;
+  }
+
+  /* Write value into a register */
+  VDP[R]=V;
+} 
+
+/** Printer() ************************************************/
+/** Send a character to the printer.                        **/
+/*************************************************************/
+#ifdef unused
+void Printer(byte V) { fputc(V,PrnStream); }
+#else
+void Printer(byte V) {  }
+#endif
+
+/** PPIOut() *************************************************/
+/** This function is called on each write to PPI to make    **/
+/** key click sound, motor relay clicks, and so on.         **/
+/*************************************************************/
+void PPIOut(register byte New,register byte Old)
+{
+  /* Keyboard click bit */
+  if((New^Old)&0x80) Drum(DRM_CLICK,64);
+  /* Motor relay bit */
+  if((New^Old)&0x10) Drum(DRM_CLICK,255);
+}
+
+byte RTCIn(register byte R)
+{
+  register byte J;
+
+  /* Only 16 registers/mode */
+  R&=0x0F;
+
+  /* Bank mode 0..3 */
+  J=RTCMode&0x03;
+
+  if(R>12) J=R==13? RTCMode:NORAM;
+  else
+    if(J) J=RTC[J][R];
+    else
+    {
+#ifdef unused  
+      static time_t PrevTime;
+      static struct tm TM;
+
+      /* Retrieve system time if any time passed */
+      time_t CurTime=time(NULL);
+      if(CurTime!=PrevTime)
+      {
+        TM=*localtime(&CurTime);
+        PrevTime=CurTime;
+      }
+
+      /* Parse contents of last retrieved TM */
+      switch(R)
+      {
+        case 0:  J=TM.tm_sec%10;break;
+        case 1:  J=TM.tm_sec/10;break;
+        case 2:  J=TM.tm_min%10;break;
+        case 3:  J=TM.tm_min/10;break;
+        case 4:  J=TM.tm_hour%10;break;
+        case 5:  J=TM.tm_hour/10;break;
+        case 6:  J=TM.tm_wday;break;
+        case 7:  J=TM.tm_mday%10;break;
+        case 8:  J=TM.tm_mday/10;break;
+        case 9:  J=(TM.tm_mon+1)%10;break;
+        case 10: J=(TM.tm_mon+1)/10;break;
+        case 11: J=(TM.tm_year-80)%10;break;
+        case 12: J=((TM.tm_year-80)/10)%10;break;
+        default: J=0x0F;break;
+      } 
+#endif
+    }
+  /* Four upper bits are always high */
+  return(J|0xF0);
+}
+
+/** LoopZ80() ************************************************/
+/** Refresh screen, check keyboard and sprites. Call this   **/
+/** function on each interrupt.                             **/
+/*************************************************************/
+word LoopZ80(register Z80 *R, int * ras)
+//word LoopZ80(Z80 *R)
+{
+  static byte BFlag=0;
+  static byte BCount=0;
+  static int  UCount=1;
+  static byte ACount=0;
+  static byte Drawing=0;
+  register int J;
+
+  /* Flip HRefresh bit */
+  VDPStatus[2]^=0x20;
+
+  /* If HRefresh is now in progress... */
+  if(!(VDPStatus[2]&0x20))
+  {
+    /* HRefresh takes most of the scanline */
+    R->IPeriod=!ScrMode||(ScrMode==MAXSCREEN+1)? CPU_H240:CPU_H256;
+
+    /* New scanline */
+    ScanLine=ScanLine<(PALVideo? 312:261)? ScanLine+1:0;
+
+    /* If first scanline of the screen... */
+    if(!ScanLine)
+    {
+      /* Drawing now... */
+      Drawing=1;
+
+      /* Reset VRefresh bit */
+      VDPStatus[2]&=0xBF;
+
+      /* Refresh display */
+      if(UCount) UCount--;
+      else
+      {
+        UCount=UPeriod-1;
+        //RefreshScreen();
+      }
+
+      /* Blinking for TEXT80 */
+      if(BCount) BCount--;
+      else
+      {
+        BFlag=!BFlag;
+        if(!VDP[13]) { XFGColor=FGColor;XBGColor=BGColor; }
+        else
+        {
+          BCount=(BFlag? VDP[13]&0x0F:VDP[13]>>4)*10;
+          if(BCount)
+          {
+            if(BFlag) { XFGColor=FGColor;XBGColor=BGColor; }
+            else      { XFGColor=VDP[12]>>4;XBGColor=VDP[12]&0x0F; }
+          }
+        }
+      }
+    }
+
+    /* Line coincidence is active at 0..255 */
+    /* in PAL and 0..234/244 in NTSC        */
+    J=PALVideo? 256:ScanLines212? 245:235;
+
+    /* When reaching end of screen, reset line coincidence */
+    if(ScanLine==J)
+    {
+      VDPStatus[1]&=0xFE;
+      SetIRQ(~INT_IE1);
+    }
+
+    /* When line coincidence is active... */
+    if(ScanLine<J)
+    {
+      /* Line coincidence processing */
+      J=(((ScanLine+VScroll)&0xFF)-VDP[19])&0xFF;
+      if(J==2)
+      {
+        /* Set HBlank flag on line coincidence */
+        VDPStatus[1]|=0x01;
+        /* Generate IE1 interrupt */
+        if(VDP[0]&0x10) SetIRQ(INT_IE1);
+      }
+      else
+      {
+        /* Reset flag immediately if IE1 interrupt disabled */
+        if(!(VDP[0]&0x10)) VDPStatus[1]&=0xFE;
+      }
+    }
+
+    /* Return whatever interrupt is pending */
+    R->IRequest=IRQPending? INT_IRQ:INT_NONE;
+    return(R->IRequest);
+  }
+
+  /*********************************/
+  /* We come here for HBlanks only */
+  /*********************************/
+
+  /* HBlank takes HPeriod-HRefresh */
+  R->IPeriod=!ScrMode||(ScrMode==MAXSCREEN+1)? CPU_H240:CPU_H256;
+  R->IPeriod=HPeriod-R->IPeriod;
+
+  /* If last scanline of VBlank, see if we need to wait more */
+  J=PALVideo? 313:262;
+  if(ScanLine>=J-1)
+  {
+    J*=CPU_HPERIOD;
+    if(VPeriod>J) R->IPeriod+=VPeriod-J;
+  }
+
+  /* If first scanline of the bottom border... */
+  if(ScanLine==(ScanLines212? 212:192)) Drawing=0;
+
+  /* If first scanline of VBlank... */
+  J=PALVideo? (ScanLines212? 212+42:192+52):(ScanLines212? 212+18:192+28);
+  if(!Drawing&&(ScanLine==J))
+  {
+    /* Set VBlank bit, set VRefresh bit */
+    VDPStatus[0]|=0x80;
+    VDPStatus[2]|=0x40;
+
+    /* Generate VBlank interrupt */
+    if(VDP[1]&0x20) SetIRQ(INT_IE0);
+  }
+
+  /* Run V9938 engine */
+  LoopVDP();
+
+  /* Refresh scanline, possibly with the overscan */
+  if(!UCount&&Drawing&&(ScanLine<256))
+  {
+    if(!ModeYJK||(ScrMode<7)||(ScrMode>8))
+      (RefreshLine[ScrMode])(ScanLine);
+    else
+      if(ModeYAE) RefreshLine10(ScanLine);
+      else RefreshLine12(ScanLine);
+
+    emu_DrawLinePal16(&linebuffer[0], WIDTH , HEIGHT, ScanLine+FirstLine);  
+  }
+
+  /* Keyboard, sound, and other stuff always runs at line 192    */
+  /* This way, it can't be shut off by overscan tricks (Maarten) */
+  if(ScanLine==192)
+  {
+    /* Check sprites and set Collision, 5Sprites, 5thSprite bits */
+    if(!SpritesOFF&&ScrMode&&(ScrMode<MAXSCREEN+1)) CheckSprites();
+
+    /* Count MIDI ticks */
+#ifdef unused    
+    MIDITicks(VPeriod/CPU_CLOCK);
+#endif
+    /* Update AY8910 state every VPeriod/CPU_CLOCK milliseconds */
+    Loop8910(&PSG,VPeriod/CPU_CLOCK);
+
+    /* Flush changes to the sound channels */
+    Sync8910(&PSG,AY8910_FLUSH|(UseDrums? AY8910_DRUMS:0));
+    SyncSCC(&SCChip,SCC_FLUSH);
+    Sync2413(&OPLL,YM2413_FLUSH);
+
+    /* Check keyboard */
+    Keyboard();
+
+    /* Exit emulation if requested */
+    //if(ExitNow) return(INT_QUIT);
+
+    *ras = 1;
+
+    /* Autofire emulation */
+    ACount=(ACount+1)&0x07;
+    if((ACount>3)&&AutoFire) KeyMap[8]|=0x01;
+  }
+
+  /* Return whatever interrupt is pending */
+  R->IRequest=IRQPending? INT_IRQ:INT_NONE;
+  return(R->IRequest);
+}
+
+/** CheckSprites() *******************************************/
+/** Check for sprite collisions and 5th/9th sprite in a     **/
+/** row.                                                    **/
+/*************************************************************/
+void CheckSprites(void)
+{
+  register word LS,LD;
+  register byte DH,DV,*PS,*PD,*T;
+  byte I,J,N,M,*S,*D;
+
+  /* Clear 5Sprites, Collision, and 5thSprite bits */
+  VDPStatus[0]=(VDPStatus[0]&0x9F)|0x1F;
+
+  for(N=0,S=SprTab;(N<32)&&(S[0]!=208);N++,S+=4);
+  M=SolidColor0;
+
+  if(Sprites16x16)
+  {
+    for(J=0,S=SprTab;J<N;J++,S+=4)
+      if((S[3]&0x0F)||M)
+        for(I=J+1,D=S+4;I<N;I++,D+=4)
+          if((D[3]&0x0F)||M) 
+          {
+            DV=S[0]-D[0];
+            if((DV<16)||(DV>240))
+      {
+              DH=S[1]-D[1];
+              if((DH<16)||(DH>240))
+        {
+                PS=SprGen+((int)(S[2]&0xFC)<<3);
+                PD=SprGen+((int)(D[2]&0xFC)<<3);
+                if(DV<16) PD+=DV; else { DV=256-DV;PS+=DV; }
+                if(DH>240) { DH=256-DH;T=PS;PS=PD;PD=T; }
+                while(DV<16)
+                {
+                  LS=((word)*PS<<8)+*(PS+16);
+                  LD=((word)*PD<<8)+*(PD+16);
+                  if(LD&(LS>>DH)) break;
+                  else { DV++;PS++;PD++; }
+                }
+                if(DV<16) { VDPStatus[0]|=0x20;return; }
+              }
+            }
+          }
+  }
+  else
+  {
+    for(J=0,S=SprTab;J<N;J++,S+=4)
+      if((S[3]&0x0F)||M)
+        for(I=J+1,D=S+4;I<N;I++,D+=4)
+          if((D[3]&0x0F)||M)
+          {
+            DV=S[0]-D[0];
+            if((DV<8)||(DV>248))
+            {
+              DH=S[1]-D[1];
+              if((DH<8)||(DH>248))
+              {
+                PS=SprGen+((int)S[2]<<3);
+                PD=SprGen+((int)D[2]<<3);
+                if(DV<8) PD+=DV; else { DV=256-DV;PS+=DV; }
+                if(DH>248) { DH=256-DH;T=PS;PS=PD;PD=T; }
+                while((DV<8)&&!(*PD&(*PS>>DH))) { DV++;PS++;PD++; }
+                if(DV<8) { VDPStatus[0]|=0x20;return; }
+              }
+            }
+          }
+  }
+}
+
+/** GuessROM() ***********************************************/
+/** Guess MegaROM mapper of a ROM.                          **/
+/*************************************************************/
+int GuessROM(const byte *Buf,int Size)
+{
+  int J,I,ROMCount[6];
+
+  /* Clear all counters */
+  for(J=0;J<6;J++) ROMCount[J]=1;
+  ROMCount[0]+=1; /* Mapper #0 is default */
+  ROMCount[4]-=1; /* #5 preferred over #4 */
+
+  /* Count occurences of characteristic addresses */
+  for(J=0;J<Size-2;J++)
+  {
+    I=Buf[J]+((int)Buf[J+1]<<8)+((int)Buf[J+2]<<16);
+    switch(I)
+    {
+      case 0x500032: ROMCount[2]++;break;
+      case 0x900032: ROMCount[2]++;break;
+      case 0xB00032: ROMCount[2]++;break;
+      case 0x400032: ROMCount[3]++;break;
+      case 0x800032: ROMCount[3]++;break;
+      case 0xA00032: ROMCount[3]++;break;
+      case 0x680032: ROMCount[4]++;break;
+      case 0x780032: ROMCount[4]++;break;
+      case 0x600032: ROMCount[3]++;ROMCount[4]++;ROMCount[5]++;break;
+      case 0x700032: ROMCount[2]++;ROMCount[4]++;ROMCount[5]++;break;
+      case 0x77FF32: ROMCount[5]++;break;
+    }
+  }
+
+  /* Find which mapper type got more hits */
+  for(I=0,J=0;J<6;J++)
+    if(ROMCount[J]>ROMCount[I]) I=J;
+
+  /* Return the most likely mapper type */
+  return(I);
+}
diff --git a/MCUME_pico2/picomsx/fmsx.h b/MCUME_pico2/picomsx/fmsx.h
new file mode 100644
index 0000000..6b171db
--- /dev/null
+++ b/MCUME_pico2/picomsx/fmsx.h
@@ -0,0 +1,5 @@
+extern void msx_Init(void);
+extern void msx_Step(void);
+extern void msx_Start(char * filename);
+extern void msx_Input(int click);
+
diff --git a/MCUME_pico2/picomsx/keyboard_osd.h b/MCUME_pico2/picomsx/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picomsx/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picomsx/picomsx.cpp b/MCUME_pico2/picomsx/picomsx.cpp
new file mode 100644
index 0000000..252abf3
--- /dev/null
+++ b/MCUME_pico2/picomsx/picomsx.cpp
@@ -0,0 +1,201 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "fmsx.h"
+}
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+/*
+    volatile uint32_t *qmi_m0_timing=(uint32_t *)0x400d000c;
+    vreg_disable_voltage_limit();
+    vreg_set_voltage(VREG_VOLTAGE_1_40);
+    sleep_ms(10);
+    *qmi_m0_timing = 0x60007204;
+    set_sys_clock_khz(140000, false);
+    *qmi_m0_timing = 0x60007303;
+*/
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+     emu_init();
+   
+
+
+
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+   
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }  
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picomsx/program_config.h b/MCUME_pico2/picomsx/program_config.h
new file mode 100644
index 0000000..99052ee
--- /dev/null
+++ b/MCUME_pico2/picomsx/program_config.h
@@ -0,0 +1,7 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define FLASH_STORE_START 0x100000  
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/picomsx/shared.h b/MCUME_pico2/picomsx/shared.h
new file mode 100644
index 0000000..f8b73ff
--- /dev/null
+++ b/MCUME_pico2/picomsx/shared.h
@@ -0,0 +1,12 @@
+
+#ifndef _SHARED_H_
+#define _SHARED_H_
+
+
+#define SOUND_PRESENT 1
+
+#define printf(...) 
+
+#define LSB_FIRST     1
+
+#endif /* _SHARED_H_ */
diff --git a/MCUME_pico2/picoo2em/Oddemu.c b/MCUME_pico2/picoo2em/Oddemu.c
new file mode 100644
index 0000000..9f524ac
--- /dev/null
+++ b/MCUME_pico2/picoo2em/Oddemu.c
@@ -0,0 +1,210 @@
+
+/****************************************************************************
+* Module name : oddemu
+* Description : Library SMSEMU
+* Author      : J-M Harvengt 
+* History     : 14-07-97 Creation
+****************************************************************************/
+#include "vmachine.h"
+#include "vdc.h"
+#include "oddemu.h"
+
+#include "emuapi.h"
+
+/****************************************************************************
+* Local macros / typedefs
+****************************************************************************/
+#define MAX_ROM_SIZE 8192 //16384
+
+/****************************************************************************
+* Local procedures definition
+****************************************************************************/
+
+
+/****************************************************************************
+* Local data
+****************************************************************************/
+#define MAXC 1024
+static char * bios=0;   //[MAXC];
+static char * scshot=0; //[MAXC]; 
+static char * lorom=0;  //[MAX_ROM_SIZE];
+
+
+/****************************************************************************
+* Global data
+****************************************************************************/
+
+/****************************************************************************
+* Local procedures
+****************************************************************************/
+
+/****************************************************************************
+* Exported procedures
+****************************************************************************/
+
+void odd_Init(void)
+{
+	if (bios == 0) bios = (char *)emu_Malloc(MAXC);
+	if (scshot == 0) scshot = (char *)emu_Malloc(MAXC);
+	if (lorom == 0) lorom = (char *)emu_Malloc(MAX_ROM_SIZE);
+	
+	app_data.debug = 0;
+	app_data.stick[0] = 0;
+	app_data.stick[1] = 1;
+	app_data.bank = 0;
+  app_data.limit = 1;
+  app_data.sound_en = 1;
+	app_data.speed = 100;
+	app_data.wsize = 1;
+	app_data.fullscreen = 0;
+	app_data.scanlines = 0;
+	app_data.voice = 1;
+	app_data.window_title = "O2EM v";
+	app_data.svolume = 200;
+	app_data.vvolume = 100;
+	app_data.filter = 0;
+	app_data.exrom = 0;
+	app_data.crc = 0;
+	app_data.scshot = scshot;
+	app_data.euro = 0;
+	app_data.openb = 0;
+}
+
+
+static void load_bios( char *biosname)
+{
+	static char s[MAXC+10];
+	unsigned long crc;
+
+    emu_LoadFile(biosname,&rom1[0],1024);
+
+	memcpy(&rom2[0],&rom1[0],1024);
+	memcpy(&rom3[0],&rom1[0],1024);
+	memcpy(&rom4[0],&rom1[0],1024);
+
+	crc = crc32_buf(rom1,1024);
+
+	if (crc==0x8016A315)
+		emu_printf("Odyssey2 bios ROM loaded\n");
+	else if (crc==0xE20A9F41)
+		emu_printf("Videopac+ G7400 bios ROM loaded\n");
+	else
+		emu_printf("Bios ROM loaded (unknown version)\n");
+}
+
+
+static void load_cart(char *file)
+{
+	long l;
+
+    l = emu_LoadFile(file,&lorom[0],MAX_ROM_SIZE);
+
+	app_data.crc = crc32_buf(lorom, l); // crc32_file(file);
+
+	if (app_data.crc == 0xAFB23F89) app_data.exrom = 1;  /* Musician */
+	if (app_data.crc == 0x3BFEF56B) app_data.exrom = 1;  /* Four in 1 Row! */
+
+	if (((app_data.crc == 0x975AB8DA) || (app_data.crc == 0xE246A812)) && (!app_data.debug)) {
+		emu_printf("Error: file is an incomplete ROM dump\n");
+	}
+
+	if (l < 2049) {
+		app_data.bank=1;
+		memcpy(&rom1[1024],&lorom[0],l);
+		memcpy(&rom1[3072],&rom1[2048],1024); /* simulate missing A10 */
+		rom=rom1;
+		emu_printf("2K");
+	} else if (l == 3072) {
+		app_data.bank=1;
+		memcpy(&rom1[1024],&lorom[0],3072);
+		rom=rom1;
+		emu_printf("3K");
+	} else if (l == 4096) {
+		if (app_data.exrom) {
+			app_data.bank=1;
+		    memcpy(&extROM[0],&lorom[0],1024);
+		    memcpy(&rom1[1024],&lorom[1024],3072);
+			rom=rom1;
+			emu_printf("3K EXROM");
+		} else {
+			app_data.bank=2;
+		    memcpy(&rom1[1024],&lorom[0],2048);
+		    memcpy(&rom2[1024],&lorom[2048],2048);
+			memcpy(&rom1[3072],&rom1[2048],1024); /* simulate missing A10 */
+			memcpy(&rom2[3072],&rom2[2048],1024); /* simulate missing A10 */
+			rom=rom2;
+			emu_printf("4K");
+		}
+	} else if (l == 6144) {
+		app_data.bank=2;
+	    memcpy(&rom1[1024],&lorom[0],3072);
+	    memcpy(&rom2[1024],&lorom[3072],3072);
+		rom=rom2;
+		emu_printf("6K");
+	} else if (l == 8192) {
+		app_data.bank=3;
+	    memcpy(&rom1[1024],&lorom[0],2048);
+	    memcpy(&rom2[1024],&lorom[2048],2048);
+	    memcpy(&rom3[1024],&lorom[2*2048],2048);
+	    memcpy(&rom4[1024],&lorom[3*2048],2048);
+		memcpy(&rom1[3072],&rom1[2048],1024); /* simulate missing A10 */
+		memcpy(&rom2[3072],&rom2[2048],1024); /* simulate missing A10 */
+		memcpy(&rom3[3072],&rom3[2048],1024); /* simulate missing A10 */
+		memcpy(&rom4[3072],&rom4[2048],1024); /* simulate missing A10 */
+		rom=rom4;
+		emu_printf("8K");
+	} else if (l == 12288) {
+		app_data.bank=3;
+	    memcpy(&rom1[1024],&lorom[0],3072);
+	    memcpy(&rom2[1024],&lorom[3072],3072);
+	    memcpy(&rom3[1024],&lorom[2*3072],3072);
+	    memcpy(&rom4[1024],&lorom[3*3072],3072);
+		rom=rom4;
+		emu_printf("12K");
+	} else {
+		emu_printf("Invalid ROM size");
+	}
+	if ((rom1[1024+12]=='O') && (rom1[1024+13]=='P') && (rom1[1024+14]=='N') && (rom1[1024+15]=='B')) app_data.openb=1;
+	orom=rom;
+	//printf("CRC: %08lX\n",app_data.crc);
+}
+
+void odd_Start(char * filename)
+{
+	load_bios(ROMSDIR "/" "o2rom.bin");
+	load_cart(filename);
+	init_display();
+	init_cpu();
+	init_system();
+}
+
+
+//static void snd_Mixer(short *  stream, int len )
+//{
+//  audio_process(stream,  len>>2);
+//}
+
+void odd_Stop(void)
+{
+	close_audio();
+	close_display();
+}
+
+
+
+
+void odd_Step(void)
+{
+  run();
+ 
+#if SINGLELINE_RENDERING
+  unsigned char * src=(unsigned char *)getGBuf();
+  for (int y=0; y<BMPH; y++) {
+  	emu_DrawLinePal16(&src[y*BMPW], BMPW, BMPH, y);
+  }	
+#else
+	emu_DrawScreenPal16((unsigned char *)getGBuf()+BORDERW/2, BMPW-BORDERW, BMPH, BMPW);
+#endif    
+
+  emu_DrawVsync();
+}
diff --git a/MCUME_pico2/picoo2em/Oddemu.h b/MCUME_pico2/picoo2em/Oddemu.h
new file mode 100644
index 0000000..fbe3b12
--- /dev/null
+++ b/MCUME_pico2/picoo2em/Oddemu.h
@@ -0,0 +1,9 @@
+extern void odd_Init(void);
+extern void odd_Start(char * filename);
+extern void odd_Stop(void);
+extern void odd_Step(void);
+extern void odd_Input(int key);
+
+
+
+
diff --git a/MCUME_pico2/picoo2em/audio.c b/MCUME_pico2/picoo2em/audio.c
new file mode 100644
index 0000000..0a7a84a
--- /dev/null
+++ b/MCUME_pico2/picoo2em/audio.c
@@ -0,0 +1,183 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   O2 audio emulation
+ */
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "cpu.h"
+#include "types.h"
+#include "config.h"
+#include "vmachine.h"
+#include "audio.h"
+
+//#define SAMPLE_RATE 44100
+#define PERIOD1 11  //11
+#define PERIOD2 44 //44
+
+#define SOUND_BUFFER_LEN 1056
+
+#define AUD_CTRL  0xAA
+#define AUD_D0	  0xA7
+#define AUD_D1	  0xA8
+#define AUD_D2	  0xA9
+
+
+int sound_IRQ;
+//static short *stream=NULL;
+//static AUDIOSTREAM *stream=NULL;
+//FILE *sndlog=NULL;
+
+static double flt_a=0.0, flt_b=0.0;
+static unsigned char flt_prv = 0;
+
+
+static void filter(unsigned char *buf, unsigned long len);
+
+
+//void audio_process(unsigned char *buffer){
+#ifdef GP32
+void audio_process(unsigned short *buffer, int len)
+#else
+void audio_process(short *buffer, int len)
+#endif
+{
+	unsigned long aud_data;
+#ifdef GP32
+	unsigned short s;
+#else
+	short s;
+#endif
+	int volume, re_circ, noise, enabled, intena, period, pnt, cnt, rndbit, pos;
+	
+	aud_data = (VDCwrite[AUD_D2] | (VDCwrite[AUD_D1] << 8) | (VDCwrite[AUD_D0] << 16));
+
+	intena = VDCwrite[0xA0] & 0x04;
+
+	pnt = cnt = 0;
+
+	noise = VDCwrite[AUD_CTRL] & 0x10;
+	enabled = VDCwrite[AUD_CTRL] & 0x80;
+	rndbit = (enabled && noise) ? (rand()%2) : 0;
+
+	while (pnt < len/*SOUND_BUFFER_LEN*/) {
+		pos = (tweakedaudio) ? (pnt/3) : (MAXLINES-1);
+		volume = AudioVector[pos] & 0x0F;
+		enabled = AudioVector[pos] & 0x80;
+		period = (AudioVector[pos] & 0x20) ? PERIOD1 : PERIOD2;
+		re_circ = AudioVector[pos] & 0x40;
+		
+#ifdef GP32
+		s= ( (enabled) ? ((aud_data & 0x01)^rndbit) * (0x10 * volume) : 0) << 8;
+#else
+		s= (( (enabled) ? ((aud_data & 0x01)^rndbit) * (0x10 * volume) : 0) - 128) << 8 ;
+#endif
+		*buffer++ = s; 
+		*buffer++ = s;
+		pnt++;
+		cnt++;
+
+		if (cnt >= period) {
+			cnt=0;
+			aud_data = (re_circ) ? ((aud_data >> 1) | ((aud_data & 1) << 23)) : (aud_data >>= 1);
+			rndbit = (enabled && noise) ? (rand()%2) : 0;
+
+			if (enabled && intena && (!sound_IRQ)) {
+				sound_IRQ = 1;
+				ext_IRQ();
+			}		
+		}
+	}
+	
+//	if (app_data.filter) filter(buffer, SOUND_BUFFER_LEN);	
+}
+
+
+void update_audio(void) {
+//	unsigned char *p;
+	if (app_data.sound_en) {
+//		p = (unsigned char *)get_audio_stream_buffer(stream);
+//		if (p) {
+//			audio_process(p);
+//			if (sndlog) fwrite(p,1,SOUND_BUFFER_LEN,sndlog);
+//			free_audio_stream_buffer(stream);
+//		}
+   	}
+}
+
+
+void init_audio(void) {
+//	int i;
+
+	sound_IRQ=0;		
+//	set_volume(255,255);
+	init_sound_stream();
+
+//	sndlog = NULL;
+}
+
+
+void init_sound_stream(void){
+	int vol;
+	if (app_data.sound_en){
+		if (app_data.filter)
+			vol = (255*app_data.svolume)/100;
+		else
+			vol = (255*app_data.svolume)/200;
+//		stream = play_audio_stream(SOUND_BUFFER_LEN,8,0,SAMPLE_RATE,vol,128);
+//		if (!stream) {
+//			printf("Error creating audio stream!\n");
+//			app_data.sound_en=0;
+//		}
+		flt_a = flt_b = 0.0;
+		flt_prv = 0;
+	}
+}
+
+
+void mute_audio(void){
+	if (app_data.sound_en /*&& stream*/){
+//		stop_audio_stream(stream);
+//		stream=NULL;
+	}
+}
+
+
+void close_audio(void) {
+	if (app_data.sound_en /*&& stream*/) {
+//		stop_audio_stream(stream);
+	}
+	app_data.sound_en=0;
+}
+
+
+static void filter(unsigned char *buffer, unsigned long len){    
+	static unsigned char buf[SOUND_BUFFER_LEN];
+	int t;
+	unsigned long i;
+	if (len>SOUND_BUFFER_LEN) return;
+	memcpy(buf,buffer,len);	
+	for (i=0; i<len; i++){
+		t = (i==0)?(buf[0]-flt_prv):(buf[i]-buf[i-1]);
+		if (t) flt_b = (double)t;
+		flt_a += flt_b/4.0 - flt_a/80.0;
+		flt_b -= flt_b/4.0;
+		if ((flt_a>255.0)||(flt_a<-255.0)) flt_a=0.0;
+		buffer[i] = (unsigned char)((flt_a+255.0)/2.0);
+	}
+	flt_prv = buf[len-1];
+}
+
+
diff --git a/MCUME_pico2/picoo2em/audio.h b/MCUME_pico2/picoo2em/audio.h
new file mode 100644
index 0000000..ee52fa6
--- /dev/null
+++ b/MCUME_pico2/picoo2em/audio.h
@@ -0,0 +1,18 @@
+#ifndef __AUDIO_H
+#define __AUDIO_H
+
+void update_audio(void);
+void init_audio(void);
+void close_audio(void);
+void init_sound_stream(void);
+void mute_audio(void);
+#ifdef GP32
+void audio_process(unsigned short *buffer, int len);
+#else
+void audio_process(short *buffer, int len);
+#endif
+extern int sound_IRQ;
+
+#endif
+
+
diff --git a/MCUME_pico2/picoo2em/config.h b/MCUME_pico2/picoo2em/config.h
new file mode 100644
index 0000000..1c7168c
--- /dev/null
+++ b/MCUME_pico2/picoo2em/config.h
@@ -0,0 +1,8 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define O2EM_VERSION "1.01"
+#define RELEASE_DATE "(October/2002)"
+
+#endif
+
diff --git a/MCUME_pico2/picoo2em/cpu.c b/MCUME_pico2/picoo2em/cpu.c
new file mode 100644
index 0000000..477f95f
--- /dev/null
+++ b/MCUME_pico2/picoo2em/cpu.c
@@ -0,0 +1,1596 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   8048 microcontroller emulation
+ */
+
+
+#include <stdio.h>
+#include "types.h"
+#include "vmachine.h"
+//#include "voice.h"
+#include "vdc.h"
+//#include "vpp.h"
+#include "cpu.h"
+
+
+Byte acc;		/* Accumulator */
+ADDRESS pc;     /* Program counter */
+long clk;		/* clock */
+
+Byte itimer;	/* Internal timer */
+Byte reg_pnt;	/* pointer to register bank */
+Byte timer_on;  /* 0=timer off/1=timer on */
+Byte count_on;  /* 0=count off/1=count on */
+Byte psw;		/* Processor status word */
+Byte sp;		/* Stack pointer (part of psw) */
+
+Byte p1;		/* I/O port 1 */
+Byte p2; 		/* I/O port 2 */
+Byte xirq_pend; /* external IRQ pending */
+Byte tirq_pend; /* timer IRQ pending */
+Byte t_flag;    /* Timer flag */
+
+static ADDRESS lastpc;
+static ADDRESS A11;		/* PC bit 11 */
+static ADDRESS A11ff;
+static Byte bs; 		/* Register Bank (part of psw) */
+static Byte f0;			/* Flag Bit (part of psw) */
+static Byte f1;			/* Flag Bit 1 */
+static Byte ac;			/* Aux Carry (part of psw) */
+static Byte cy;	    	/* Carry flag (part of psw) */
+static Byte xirq_en;	/* external IRQ's enabled */
+static Byte tirq_en;	/* Timer IRQ enabled */
+static Byte irq_ex;		/* IRQ executing */
+
+static int master_count;
+
+
+#define push(d) {intRAM[sp++] = (d); if (sp > 23) sp = 8;}
+#define pull() (sp--, (sp < 8)?(sp=23):0, intRAM[sp])
+#define make_psw() {psw = (cy << 7) | ac | f0 | bs | 0x08; psw = psw | ((sp - 8) >> 1);}
+#define illegal(o) {}
+#define undef(i) {printf("** unimplemented instruction %x, %x**\n",i,pc);}
+
+
+void init_cpu(void){
+	pc=0;
+	sp=8;
+	bs=0;
+	p1=p2=0xFF;
+	ac=cy=f0=0;
+	A11=A11ff=0;
+	timer_on=0;
+	count_on=0;
+	reg_pnt=0;
+	tirq_en=xirq_en=irq_ex=xirq_pend=tirq_pend=0;
+}
+
+
+void ext_IRQ(void){
+	int_clk = 5; /* length of pulse on /INT */
+	if (xirq_en && !irq_ex) {
+		irq_ex=1;
+		xirq_pend=0;
+		clk+=2;
+		make_psw();
+		push(pc & 0xFF);
+		push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+		pc = 0x03;
+		A11ff=A11;
+		A11=0;
+	}
+	if (pendirq && (!xirq_en)) xirq_pend=1;
+}
+
+
+void tim_IRQ(void){
+	if (tirq_en && !irq_ex) {
+		irq_ex=2;
+		tirq_pend=0;
+		clk+=2;
+		make_psw();
+		push(pc & 0xFF);
+		push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+		pc = 0x07;
+		A11ff=A11;
+		A11=0;
+	}
+	if (pendirq && (!tirq_en)) tirq_pend=1;
+}
+
+
+void make_psw_debug(void){
+	make_psw();
+}
+
+
+
+void cpu_exec(void) {
+	Byte op;
+	ADDRESS adr;
+	Byte dat;
+	int temp;
+	
+	for (;;) {
+
+		clk=0;	
+
+		lastpc=pc;
+		op=rom[pc++];
+		switch (op) {
+			case 0x00: /* NOP */
+				clk++;
+				break;
+			case 0x01: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0x02: /* OUTL BUS,A */
+				clk+=2;
+				undef(0x02);
+				break;
+			case 0x03: /* ADD A,#data */
+				clk+=2;
+				cy=ac=0;
+				dat=rom[pc++];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x04:	/* JMP */
+				pc=rom[pc] | A11;
+				clk+=2;
+				break;
+			case 0x05: /* EN I */
+				xirq_en=1;
+				clk++;
+				break;
+			case 0x06: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x07: /* DEC A */
+				acc--;
+				clk++;
+				break;
+			case 0x08: /* INS A,BUS*/
+				clk+=2;
+				acc=in_bus();
+				break;
+			case 0x09: /* IN A,Pp */
+				acc=p1;
+				clk+=2;
+				break;
+			case 0x0A: /* IN A,Pp */
+				acc=read_P2();
+				clk+=2;
+				break;
+			case 0x0B: /* ILL */
+				clk++;
+				illegal(op);
+			case 0x0C: /* MOVD A,P4 */
+				clk+=2;
+				//acc=read_PB(0);
+				break;
+			case 0x0D: /* MOVD A,P5 */
+				clk+=2;
+				//acc=read_PB(1);
+				break;
+			case 0x0E: /* MOVD A,P6 */
+				clk+=2;
+				//acc=read_PB(2);
+				break;
+			case 0x0F: /* MOVD A,P7 */
+				clk+=2;
+				//acc=read_PB(3);
+				break;
+			case 0x10: /* INC @Ri */
+				intRAM[intRAM[reg_pnt] & 0x3F]++;
+				clk++;
+				break;
+			case 0x11: /* INC @Ri */
+				intRAM[intRAM[reg_pnt+1] & 0x3F]++;
+				clk++;
+				break;
+			case 0x12: /* JBb address */
+				clk+=2;
+				dat = rom[pc];
+				if (acc & 0x01)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x13: /* ADDC A,#data */
+				clk+=2;
+				dat=rom[pc++];
+				ac=0;
+				if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+
+			case 0x14: /* CALL */
+				make_psw();
+				adr = rom[pc] | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0x15: /* DIS I */
+				xirq_en=0;
+				clk++;
+				break;
+			case 0x16: /* JTF */
+				clk+=2;
+				dat = rom[pc];
+				if (t_flag)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				t_flag=0;
+				break;
+			case 0x17: /* INC A */
+				acc++;
+				clk++;
+				break;
+			case 0x18: /* INC Rr */
+				intRAM[reg_pnt]++;
+				clk++;
+				break;
+			case 0x19: /* INC Rr */
+				intRAM[reg_pnt+1]++;
+				clk++;
+				break;
+			case 0x1A: /* INC Rr */
+				intRAM[reg_pnt+2]++;
+				clk++;
+				break;
+			case 0x1B: /* INC Rr */
+				intRAM[reg_pnt+3]++;
+				clk++;
+				break;
+			case 0x1C: /* INC Rr */
+				intRAM[reg_pnt+4]++;
+				clk++;
+				break;
+			case 0x1D: /* INC Rr */
+				intRAM[reg_pnt+5]++;
+				clk++;
+				break;
+			case 0x1E: /* INC Rr */
+				intRAM[reg_pnt+6]++;
+				clk++;
+				break;
+			case 0x1F: /* INC Rr */
+				intRAM[reg_pnt+7]++;
+				clk++;
+				break;
+			case 0x20: /* XCH A,@Ri */
+				clk++;
+				dat=acc;
+				acc=intRAM[intRAM[reg_pnt] & 0x3F];
+				intRAM[intRAM[reg_pnt] & 0x3F] = dat;
+				break;
+			case 0x21: /* XCH A,@Ri */
+				clk++;
+				dat=acc;
+				acc=intRAM[intRAM[reg_pnt+1] & 0x3F];
+				intRAM[intRAM[reg_pnt+1] & 0x3F] = dat;
+				break;
+			case 0x22: /* ILL */
+				illegal(op);
+				break;
+			case 0x23:  /* MOV a,#data */
+				clk+=2;
+				acc = rom[pc++];
+				break;
+
+			case 0x24:  /* JMP */
+				pc=rom[pc] | 0x100 | A11;
+				clk+=2;
+				break;
+			case 0x25: /* EN TCNTI */
+				tirq_en=1;
+				clk++;
+				break;
+			case 0x26:  /* JNT0 */
+				clk+=2;
+				dat = rom[pc];
+//JMH				if (!get_voice_status())
+//					pc=(pc & 0xF00) | dat;
+//				else
+					pc++;
+				break;
+			case 0x27:  /* CLR A */
+				clk++;
+				acc=0;
+				break;
+			case 0x28: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt];
+				intRAM[reg_pnt]=dat;
+				clk++;
+				break;
+			case 0x29: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+1];
+				intRAM[reg_pnt+1]=dat;
+				clk++;
+				break;
+			case 0x2A: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+2];
+				intRAM[reg_pnt+2]=dat;
+				clk++;
+				break;
+			case 0x2B: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+3];
+				intRAM[reg_pnt+3]=dat;
+				clk++;
+				break;
+			case 0x2C: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+4];
+				intRAM[reg_pnt+4]=dat;
+				clk++;
+				break;
+			case 0x2D: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+5];
+				intRAM[reg_pnt+5]=dat;
+				clk++;
+				break;
+			case 0x2E: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+6];
+				intRAM[reg_pnt+6]=dat;
+				clk++;
+				break;
+			case 0x2F: /* XCH A,Rr */
+				dat=acc;
+				acc=intRAM[reg_pnt+7];
+				intRAM[reg_pnt+7]=dat;
+				clk++;
+				break;
+			case 0x30: /* XCHD A,@Ri */
+				clk++;
+				adr=intRAM[reg_pnt] & 0x3F;
+				dat=acc & 0x0F;
+				acc=acc & 0xF0;
+				acc=acc | (intRAM[adr] & 0x0F);
+				intRAM[adr] &= 0xF0;
+				intRAM[adr] |= dat;
+				break;
+			case 0x31: /* XCHD A,@Ri */
+				clk++;
+				adr=intRAM[reg_pnt+1] & 0x3F;
+				dat=acc & 0x0F;
+				acc=acc & 0xF0;
+				acc=acc | (intRAM[adr] & 0x0F);
+				intRAM[adr] &= 0xF0;
+				intRAM[adr] |= dat;
+				break;
+			case 0x32: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x02)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x33: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x34: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x100 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0x35: /* DIS TCNTI */
+				tirq_en=0;
+				tirq_pend=0;
+				clk++;
+				break;
+			case 0x36: /* JT0 */
+				clk+=2;
+				dat=rom[pc];
+// JMH				if (get_voice_status())
+//					pc=(pc & 0xF00) | dat;
+//				else
+					pc++;
+				break;
+			case 0x37: /* CPL A */
+				acc = acc ^ 0xFF;
+				clk++;
+				break;
+			case 0x38: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x39: /* OUTL P1,A */
+				clk+=2;
+				write_p1(acc);
+				break;
+			case 0x3A: /* OUTL P2,A */
+				clk+=2;
+				p2=acc;
+				break;
+			case 0x3B: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x3C: /* MOVD P4,A */
+				clk+=2;
+				//write_PB(0,acc);
+				break;
+			case 0x3D: /* MOVD P5,A */
+				clk+=2;
+				//write_PB(1,acc);
+				break;
+			case 0x3E: /* MOVD P6,A */
+				clk+=2;
+				//write_PB(2,acc);
+				break;
+			case 0x3F: /* MOVD P7,A */
+				clk+=2;
+				//write_PB(3,acc);
+				break;
+			case 0x40: /* ORL A,@Ri */
+				clk++;
+				acc = acc | intRAM[intRAM[reg_pnt] & 0x3F];
+				break;
+			case 0x41: /* ORL A,@Ri */
+				clk++;
+				acc = acc | intRAM[intRAM[reg_pnt+1] & 0x3F];
+				break;
+			case 0x42: /* MOV A,T */
+				clk++;
+				acc = itimer;
+				break;
+			case 0x43: /* ORL A,#data */
+				clk+=2;
+				acc = acc | rom[pc++];
+				break;
+			case 0x44:  /* JMP */
+				pc=rom[pc] | 0x200 | A11;
+				clk+=2;
+				break;
+			case 0x45: /* STRT CNT */
+				/* printf("START: %d=%d\n",master_clk/22,itimer); */
+				count_on=1;
+				clk++;
+				break;
+			case 0x46:  /* JNT1 */
+				clk+=2;
+				dat = rom[pc];
+				if (!read_t1())
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x47: /* SWAP A */
+				clk++;
+				dat=(acc & 0xF0) >> 4;
+				acc = acc << 4;
+				acc = acc | dat;
+				break;
+			case 0x48: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt];
+				break;
+			case 0x49: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+1];
+				break;
+			case 0x4A: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+2];
+				break;
+			case 0x4B: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+3];
+				break;
+			case 0x4C: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+4];
+				break;
+			case 0x4D: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+5];
+				break;
+			case 0x4E: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+6];
+				break;
+			case 0x4F: /* ORL A,Rr */
+				clk++;
+				acc = acc | intRAM[reg_pnt+7];
+				break;
+
+			case 0x50:	/* ANL A,@Ri */
+				acc = acc & intRAM[intRAM[reg_pnt] & 0x3F];
+				clk++;
+				break;
+			case 0x51:	/* ANL A,@Ri */
+				acc = acc & intRAM[intRAM[reg_pnt+1] & 0x3F];
+				clk++;
+				break;
+			case 0x52: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x04)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x53:  /* ANL A,#data */
+				clk+=2;
+				acc = acc & rom[pc++];
+				break;
+			case 0x54: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x200 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0x55: /* STRT T */
+				timer_on=1;
+				clk++;
+				break;
+			case 0x56: /* JT1 */
+				clk+=2;
+				dat = rom[pc];
+				if (read_t1())
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x57: /* DA A */
+				clk++;
+				if (((acc & 0x0F) > 0x09) || ac) acc+=6;
+				dat = (acc & 0xF0) >> 4;
+				if ((dat > 9) || cy) {
+					dat+=6;
+					cy=1;
+				}
+				else {
+					cy=0;
+				}
+				/* if (dat > 0x0F) cy=1; */
+				acc = (acc & 0x0F) | (dat << 4);
+				break;
+			case 0x58: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt];
+				break;
+			case 0x59: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+1];
+				break;
+			case 0x5A: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+2];
+				break;
+			case 0x5B: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+3];
+				break;
+			case 0x5C: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+4];
+				break;
+			case 0x5D: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+5];
+				break;
+			case 0x5E: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+6];
+				break;
+			case 0x5F: /* ANL A,Rr */
+				clk++;
+				acc = acc & intRAM[reg_pnt+7];
+				break;
+
+			case 0x60: /* ADD A,@Ri */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[intRAM[reg_pnt] & 0x3F];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x61: /* ADD A,@Ri */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x62: /* MOV T,A */
+				clk++;
+				itimer=acc;
+				break;
+			case 0x63: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x64:  /* JMP */
+				pc=rom[pc] | 0x300 | A11;
+				clk+=2;
+				break;
+			case 0x65: /* STOP TCNT */
+				clk++;
+				/* printf("STOP %d\n",master_clk/22); */
+				count_on=timer_on=0;
+				break;
+			case 0x66: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x67: /* RRC A */
+				dat=cy;
+				cy=acc & 0x01;
+				acc = acc >> 1;
+				if (dat)
+					acc = acc | 0x80;
+				else
+					acc = acc & 0x7F;
+				clk++;
+				break;
+			case 0x68: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x69: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+1];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6A: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+2];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6B: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+3];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6C: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+4];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6D: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+5];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6E: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+6];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x6F: /* ADD A,Rr */
+				clk++;
+				cy=ac=0;
+				dat=intRAM[reg_pnt+7];
+				if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
+				temp=acc+dat;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x70: /* ADDC A,@Ri */
+				clk++;
+				ac=0;
+				dat=intRAM[intRAM[reg_pnt] & 0x3F];
+				if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x71: /* ADDC A,@Ri */
+				clk++;
+				ac=0;
+				dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
+				if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+
+			case 0x72: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x08)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x73: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x74: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x300 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0x75: /* EN CLK */
+				clk++;
+				undef(op);
+				break;
+			case 0x76: /* JF1 address */
+				clk+=2;
+				dat=rom[pc];
+				if (f1)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x77: /* RR A */
+				clk++;
+				dat=acc & 0x01;
+				acc = acc >> 1;
+				if (dat)
+					acc = acc | 0x80;
+				else
+					acc = acc & 0x7f;
+				break;
+
+			case 0x78: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x79: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+1];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7A: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+2];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7B: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+3];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7C: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+4];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7D: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+5];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7E: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+6];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+			case 0x7F: /* ADDC A,Rr */
+				clk++;
+				ac=0;
+				dat=intRAM[reg_pnt+7];
+				if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
+				temp=acc+dat+cy;
+				cy=0;
+				if (temp > 0xFF) cy=1;
+				acc=(temp & 0xFF);
+				break;
+
+			case 0x80:  /* MOVX  A,@Ri */
+				acc=ext_read(intRAM[reg_pnt]);
+				clk+=2;
+				break;
+			case 0x81:  /* MOVX A,@Ri */
+				acc=ext_read(intRAM[reg_pnt+1]);
+				clk+=2;
+				break;
+			case 0x82: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0x83:  /* RET */
+				pc = ((pull() & 0x0F) << 8);
+				pc = pc | pull();
+				break;
+
+			case 0x84:  /* JMP */
+				pc=rom[pc] | 0x400 | A11;
+				clk+=2;
+				break;
+			case 0x85: /* CLR F0 */
+				clk++;
+				f0=0;
+				break;
+			case 0x86: /* JNI address */
+				clk+=2;
+				dat=rom[pc];
+				if (int_clk > 0)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+				break;
+			case 0x87: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0x88: /* BUS,#data */
+				clk+=2;
+				undef(op);
+				break;
+			case 0x89: /* ORL Pp,#data */
+				write_p1(p1 | rom[pc++]);
+				clk+=2;
+				break;
+			case 0x8A: /* ORL Pp,#data */
+				p2 = p2 | rom[pc++];
+				clk+=2;
+				break;
+			case 0x8B: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0x8C: /* ORLD P4,A */
+				//write_PB(0,read_PB(0)|acc);
+				clk+=2;
+				break;
+			case 0x8D: /* ORLD P5,A */
+				//write_PB(1,read_PB(1)|acc);
+				clk+=2;
+				break;
+			case 0x8E: /* ORLD P6,A */
+				//write_PB(2,read_PB(2)|acc);
+				clk+=2;
+				break;
+			case 0x8F: /* ORLD P7,A */
+				//write_PB(3,read_PB(3)|acc);
+				clk+=2;
+				break;
+			case 0x90:  /* MOVX @Ri,A */
+				ext_write(acc,intRAM[reg_pnt]);
+				clk+=2;
+				break;
+			case 0x91:  /* MOVX @Ri,A */
+				ext_write(acc,intRAM[reg_pnt+1]);
+				clk+=2;
+				break;
+			case 0x92: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x10)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x93:  /* RETR*/
+				/* printf("RETR %d\n",master_clk/22); */
+				clk+=2;
+				dat=pull();
+				pc = (dat & 0x0F) << 8;
+				cy = (dat & 0x80) >> 7;
+				ac = dat & 0x40;
+				f0 = dat & 0x20;
+				bs = dat & 0x10;
+				if (bs)
+					reg_pnt=24;
+				else
+					reg_pnt=0;
+				pc = pc | pull();
+				irq_ex=0;
+				A11=A11ff; 
+				break;
+			case 0x94: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x400 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0x95: /* CPL F0 */
+				f0 = f0 ^ 0x20;
+				clk++;
+				break;
+			case 0x96: /* JNZ address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc != 0)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0x97: /* CLR C */
+				cy=0;
+				clk++;
+				break;
+			case 0x98: /* ANL BUS,#data */
+				clk+=2;
+				undef(op);
+				break;
+			case 0x99: /* ANL Pp,#data */
+				write_p1(p1 & rom[pc++]);
+				clk+=2;
+				break;
+			case 0x9A: /* ANL Pp,#data */
+				p2 = p2 & rom[pc++];
+				clk+=2;
+				break;
+			case 0x9B: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0x9C: /* ANLD P4,A */
+				//write_PB(0,read_PB(0)&acc);
+				clk+=2;
+				break;
+			case 0x9D: /* ANLD P5,A */
+				//write_PB(1,read_PB(1)&acc);
+				clk+=2;
+				break;
+			case 0x9E: /* ANLD P6,A */
+				//write_PB(2,read_PB(2)&acc);
+				clk+=2;
+				break;
+			case 0x9F: /* ANLD P7,A */
+				//write_PB(3,read_PB(3)&acc);
+				clk+=2;
+				break;
+			case 0xA0: /* MOV @Ri,A */
+				intRAM[intRAM[reg_pnt] & 0x3F]=acc;
+				clk++;
+				break;
+			case 0xA1: /* MOV @Ri,A */
+				intRAM[intRAM[reg_pnt+1] & 0x3F]=acc;
+				clk++;
+				break;
+			case 0xA2: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0xA3: /* MOVP A,@A */
+				acc=rom[(pc & 0xF00) | acc];
+				clk+=2;
+				break;
+			case 0xA4:  /* JMP */
+				pc=rom[pc] | 0x500 | A11;
+				clk+=2;
+				break;
+			case 0xA5:  /* CLR F1 */
+				clk++;
+				f1=0;
+				break;
+			case 0xA6: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xA7: /* CPL C */
+				cy = cy ^ 0x01;
+				clk++;
+				break;
+			case 0xA8: /* MOV Rr,A */
+				intRAM[reg_pnt] = acc;
+				break;
+			case 0xA9: /* MOV Rr,A */
+				intRAM[reg_pnt+1] = acc;
+				break;
+			case 0xAA: /* MOV Rr,A */
+				intRAM[reg_pnt+2] = acc;
+				break;
+			case 0xAB: /* MOV Rr,A */
+				intRAM[reg_pnt+3] = acc;
+				break;
+			case 0xAC: /* MOV Rr,A */
+				intRAM[reg_pnt+4] = acc;
+				break;
+			case 0xAD: /* MOV Rr,A */
+				intRAM[reg_pnt+5] = acc;
+				break;
+			case 0xAE: /* MOV Rr,A */
+				intRAM[reg_pnt+6] = acc;
+				break;
+			case 0xAF: /* MOV Rr,A */
+				intRAM[reg_pnt+7] = acc;
+				break;
+			case 0xB0: /* MOV @Ri,#data */
+				intRAM[intRAM[reg_pnt] & 0x3F]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xB1: /* MOV @Ri,#data */
+				intRAM[intRAM[reg_pnt+1] & 0x3F]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xB2: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x20)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xB3: /* JMPP @A */
+				adr = (pc & 0xF00) | acc;
+				pc=(pc & 0xF00) | rom[adr];
+				clk+=2;
+				break;
+			case 0xB4: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x500 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0xB5: /* CPL F1 */
+				f1 = f1 ^ 0x01;
+				clk++;
+				break;
+			case 0xB6: /* JF0 address */
+				clk+=2;
+				dat=rom[pc];
+				if (f0)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xB7: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0xB8: /* MOV Rr,#data */
+				intRAM[reg_pnt]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xB9: /* MOV Rr,#data */
+				intRAM[reg_pnt+1]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBA: /* MOV Rr,#data */
+				intRAM[reg_pnt+2]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBB: /* MOV Rr,#data */
+				intRAM[reg_pnt+3]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBC: /* MOV Rr,#data */
+				intRAM[reg_pnt+4]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBD: /* MOV Rr,#data */
+				intRAM[reg_pnt+5]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBE: /* MOV Rr,#data */
+				intRAM[reg_pnt+6]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xBF: /* MOV Rr,#data */
+				intRAM[reg_pnt+7]=rom[pc++];
+				clk+=2;
+				break;
+			case 0xC0: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xC1: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xC2: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xC3: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xC4:  /* JMP */
+				pc=rom[pc] | 0x600 | A11;
+				clk+=2;
+				break;
+			case 0xC5: /* SEL RB0 */
+				bs=reg_pnt=0;
+				clk++;
+				break;
+			case 0xC6: /* JZ address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc == 0)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xC7: /* MOV A,PSW */
+			   clk++;
+			   make_psw();
+			   acc=psw;
+			   break;
+			case 0xC8: /* DEC Rr */
+				intRAM[reg_pnt]--;
+				clk++;
+				break;
+			case 0xC9: /* DEC Rr */
+				intRAM[reg_pnt+1]--;
+				clk++;
+				break;
+			case 0xCA: /* DEC Rr */
+				intRAM[reg_pnt+2]--;
+				clk++;
+				break;
+			case 0xCB: /* DEC Rr */
+				intRAM[reg_pnt+3]--;
+				clk++;
+				break;
+			case 0xCC: /* DEC Rr */
+				intRAM[reg_pnt+4]--;
+				clk++;
+				break;
+			case 0xCD: /* DEC Rr */
+				intRAM[reg_pnt+5]--;
+				clk++;
+				break;
+			case 0xCE: /* DEC Rr */
+				intRAM[reg_pnt+6]--;
+				clk++;
+				break;
+			case 0xCF: /* DEC Rr */
+				intRAM[reg_pnt+7]--;
+				clk++;
+				break;
+			case 0xD0:	/* XRL A,@Ri */
+				acc = acc ^ intRAM[intRAM[reg_pnt] & 0x3F];
+				clk++;
+				break;
+			case 0xD1:	/* XRL A,@Ri */
+				acc = acc ^ intRAM[intRAM[reg_pnt+1] & 0x3F];
+				clk++;
+				break;
+			case 0xD2: /* JBb address */
+				clk+=2;
+				dat = rom[pc];
+				if (acc & 0x40)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xD3: /* XRL A,#data */
+				clk+=2;
+				acc = acc ^ rom[pc++];
+				break;
+			case 0xD4: /* CALL */
+				make_psw();
+				adr = rom[pc] | 0x600 | A11;
+				pc++;
+				clk+=2;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0xD5: /* SEL RB1 */
+				bs=0x10;
+				reg_pnt=24;
+				clk++;
+				break;
+			case 0xD6: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xD7: /* MOV PSW,A */
+				psw=acc;
+				clk++;
+				cy = (psw & 0x80) >> 7;
+				ac = psw & 0x40;
+				f0 = psw & 0x20;
+				bs = psw & 0x10;
+				if (bs)
+					reg_pnt = 24;
+				else
+					reg_pnt = 0;
+				sp = (psw & 0x07) << 1;
+				sp+=8;
+				break;
+			case 0xD8: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt];
+				clk++;
+				break;
+			case 0xD9: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+1];
+				clk++;
+				break;
+			case 0xDA: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+2];
+				clk++;
+				break;
+			case 0xDB: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+3];
+				clk++;
+				break;
+			case 0xDC: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+4];
+				clk++;
+				break;
+			case 0xDD: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+5];
+				clk++;
+				break;
+			case 0xDE: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+6];
+				clk++;
+				break;
+			case 0xDF: /* XRL A,Rr */
+				acc = acc ^ intRAM[reg_pnt+7];
+				clk++;
+				break;
+			case 0xE0: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0xE1: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0xE2: /* ILL */
+				clk++;
+				illegal(op);
+				break;
+			case 0xE3: /* MOVP3 A,@A */
+
+				adr = 0x300 | acc;
+				acc=rom[adr];
+				clk+=2;
+				break;
+			case 0xE4:  /* JMP */
+				pc=rom[pc] | 0x700 | A11;
+				clk+=2;
+				break;
+			case 0xE5: /* SEL MB0 */
+				A11=0;
+				A11ff = 0;
+				clk++;
+				break;
+			case 0xE6: /* JNC address */
+				clk+=2;
+				dat=rom[pc];
+				if (!cy)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xE7: /* RL A */
+				clk++;
+				dat=acc & 0x80;
+				acc = acc << 1;
+				if (dat)
+					acc = acc | 0x01;
+				else
+					acc = acc & 0xFE;
+				break;
+			case 0xE8: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xE9: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+1]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+1] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xEA: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+2]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+2] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xEB: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+3]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+3] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xEC: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+4]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+4] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xED: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+5]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+5] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xEE: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+6]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+6] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xEF: /* DJNZ Rr,address */
+				clk+=2;
+				intRAM[reg_pnt+7]--;
+				dat=rom[pc];
+				if (intRAM[reg_pnt+7] != 0) {
+					pc = pc & 0xF00;
+					pc = pc | dat;
+				} else pc++;
+				break;
+			case 0xF0: /* MOV A,@Ri */
+				clk++;
+				acc=intRAM[intRAM[reg_pnt] & 0x3F];
+				break;
+			case 0xF1: /* MOV A,@Ri */
+				clk++;
+				acc=intRAM[intRAM[reg_pnt + 1] & 0x3F];
+				break;
+			case 0xF2: /* JBb address */
+				clk+=2;
+				dat=rom[pc];
+				if (acc & 0x80)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xF3: /* ILL */
+				illegal(op);
+				clk++;
+				break;
+			case 0xF4: /* CALL */
+				clk+=2;
+				make_psw();
+				adr = rom[pc] | 0x700 | A11;
+				pc++;
+				push(pc & 0xFF);
+				push(((pc & 0xF00) >> 8) | (psw & 0xF0));
+				pc = adr;
+				break;
+			case 0xF5: /* SEL MB1 */
+				if (irq_ex) {
+					A11ff = 0x800;
+				}
+				else
+				{
+					A11=0x800;
+					A11ff = 0x800;
+				}
+				clk++;
+				break;
+			case 0xF6: /* JC address */
+				clk+=2;
+				dat=rom[pc];
+				if (cy)
+					pc=(pc & 0xF00) | dat;
+				else
+					pc++;
+				break;
+			case 0xF7: /* RLC A */
+				dat=cy;
+				cy=(acc & 0x80) >> 7;
+				acc = acc << 1;
+				if (dat)
+					acc = acc | 0x01;
+				else
+					acc = acc & 0xFE;
+				clk++;
+				break;
+			case 0xF8: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt];
+				break;
+			case 0xF9: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 1];
+				break;
+			case 0xFA: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 2];
+				break;
+			case 0xFB: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 3];
+				break;
+			case 0xFC: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 4];
+				break;
+			case 0xFD: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 5];
+				break;
+			case 0xFE: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 6];
+				break;
+			case 0xFF: /* MOV A,Rr */
+				clk++;
+				acc = intRAM[reg_pnt + 7];
+				break;
+		}
+
+
+		master_clk+=clk;
+		h_clk+=clk;
+		clk_counter+=clk;
+
+		/* flag for JNI */
+		if (int_clk > clk)
+			int_clk -= clk;
+		else
+			int_clk = 0;
+
+		/* pending IRQs */
+		if (xirq_pend) ext_IRQ();
+		if (tirq_pend) tim_IRQ();
+
+		if (h_clk > LINECNT-1) {
+			h_clk-=LINECNT;
+			if (enahirq && (VDCwrite[0xA0] & 0x01)) ext_IRQ();
+			if (count_on && mstate == 0) {
+				itimer++;
+				if (itimer == 0) {
+					t_flag=1;
+					tim_IRQ();
+					if (!ccolflag) {
+						clear_collision();
+						ccolflag=1;
+					}
+					draw_region();
+				}
+			}
+		}
+
+		if (timer_on) {
+			master_count+=clk;
+			if (master_count > 31) {
+				master_count-=31;
+				itimer++;
+				if (itimer == 0) {
+					t_flag=1;
+					tim_IRQ();
+				}
+			}
+		}
+
+		if ((mstate==0) && (master_clk > VBLCLK)) 
+			handle_vbl();
+		
+		if ((mstate==1) && (master_clk > evblclk)) {
+			handle_evbl();
+			break;
+		}
+
+		if (app_data.debug) break;
+	}
+
+}
+
diff --git a/MCUME_pico2/picoo2em/cpu.h b/MCUME_pico2/picoo2em/cpu.h
new file mode 100644
index 0000000..c7d9380
--- /dev/null
+++ b/MCUME_pico2/picoo2em/cpu.h
@@ -0,0 +1,34 @@
+#ifndef CPU_H
+#define CPU_H
+
+#include "types.h"
+
+extern Byte acc;		/* Accumulator */
+extern ADDRESS pc;     /* Program counter */
+extern long clk;		/* clock */
+
+extern Byte itimer;		/* Internal timer */
+extern Byte reg_pnt;	/* pointer to register bank */
+extern Byte timer_on;  /* 0=timer off/1=timer on */
+extern Byte count_on;  /* 0=count off/1=count on */
+
+extern Byte t_flag;    /* Timer flag */
+
+extern Byte psw;		/* Processor status word */
+extern Byte sp;		/* Stack pointer (part of psw) */
+
+extern Byte p1;		/* I/O port 1 */
+extern Byte p2;    /* I/O port 2 */
+
+extern Byte xirq_pend;
+extern Byte tirq_pend;
+
+void init_cpu(void);
+void cpu_exec(void);
+void ext_IRQ(void);
+void tim_IRQ(void);
+void make_psw_debug(void);
+
+
+#endif  /* CPU_H */
+
diff --git a/MCUME_pico2/picoo2em/crc32.c b/MCUME_pico2/picoo2em/crc32.c
new file mode 100644
index 0000000..b38b4e3
--- /dev/null
+++ b/MCUME_pico2/picoo2em/crc32.c
@@ -0,0 +1,111 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   CRC32 functions used to identify files
+ */
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "crc32.h"
+//#include "pgmspace.h"
+
+static const unsigned long crc32tab[256] = {
+	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
+	0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+	0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+	0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+	0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
+	0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+	0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+	0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
+	0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
+	0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+	0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+	0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
+	0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
+	0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+	0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+	0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
+	0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+	0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+	0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+	0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
+	0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
+	0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+	0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+	0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+	0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
+	0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+	0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+	0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
+	0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
+	0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+	0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+	0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
+	0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
+	0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+	0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+	0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
+	0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+	0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+	0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+	0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
+	0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
+	0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+	0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+
+unsigned long crc32_buf(const void *buf, long len){
+	unsigned long crc = ~0;
+	unsigned char *p = (unsigned char*)buf;
+
+	while (len--) crc = (crc >> 8) ^ crc32tab[(crc ^ (*p++)) & 0xff];
+	return ~crc;
+}
+
+
+unsigned long crc32_file(const char *filename){
+	unsigned long crc = ~0;
+	FILE *f;
+	int c;
+	
+	f = fopen(filename,"rb");
+	if (f){
+		while ((c=fgetc(f)) != EOF) crc = (crc >> 8) ^ crc32tab[(crc ^ c) & 0xff];
+		fclose(f);
+	}
+	return ~crc;
+}
+
diff --git a/MCUME_pico2/picoo2em/crc32.h b/MCUME_pico2/picoo2em/crc32.h
new file mode 100644
index 0000000..e00c9a2
--- /dev/null
+++ b/MCUME_pico2/picoo2em/crc32.h
@@ -0,0 +1,7 @@
+#ifndef __CRC32_H
+#define __CRC32_H
+
+unsigned long crc32_buf(const void *buf, long len);
+unsigned long crc32_file(const char *filename);
+
+#endif
diff --git a/MCUME_pico2/picoo2em/cset.c b/MCUME_pico2/picoo2em/cset.c
new file mode 100644
index 0000000..3adbcb8
--- /dev/null
+++ b/MCUME_pico2/picoo2em/cset.c
@@ -0,0 +1,86 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   O2 character table
+ */
+
+
+#include "types.h"
+#include "cset.h"
+
+
+const Byte cset[512]= {
+0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,
+0x18,0x38,0x18,0x18,0x18,0x18,0x3C,0x00,
+0x3C,0x66,0x0C,0x18,0x30,0x60,0x7E,0x00,
+0x7C,0xC6,0x06,0x3C,0x06,0xC6,0x7C,0x00,
+0xCC,0xCC,0xCC,0xFE,0x0C,0x0C,0x0C,0x00,
+0xFE,0xC0,0xC0,0x7C,0x06,0xC6,0x7C,0x00,
+0x7C,0xC6,0xC0,0xFC,0xC6,0xC6,0x7C,0x00,
+0xFE,0x06,0x0C,0x18,0x30,0x60,0xC0,0x00,
+0x7C,0xC6,0xC6,0x7C,0xC6,0xC6,0x7C,0x00,
+0x7C,0xC6,0xC6,0x7E,0x06,0xC6,0x7C,0x00,
+0x00,0x18,0x18,0x00,0x18,0x18,0x00,0x00,
+0x18,0x7E,0x58,0x7E,0x1A,0x7E,0x18,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x3C,0x66,0x0C,0x18,0x18,0x00,0x18,0x00,
+0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xFE,0x00,
+0xFC,0xC6,0xC6,0xFC,0xC0,0xC0,0xC0,0x00,
+0x00,0x18,0x18,0x7E,0x18,0x18,0x00,0x00,
+0xC6,0xC6,0xC6,0xD6,0xFE,0xEE,0xC6,0x00,
+0xFE,0xC0,0xC0,0xF8,0xC0,0xC0,0xFE,0x00,
+0xFC,0xC6,0xC6,0xFC,0xD8,0xCC,0xC6,0x00,
+0x7E,0x18,0x18,0x18,0x18,0x18,0x18,0x00,
+0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,
+0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,
+0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,
+0x7C,0xC6,0xC6,0xC6,0xDE,0xCC,0x76,0x00,
+0x7C,0xC6,0xC0,0x7C,0x06,0xC6,0x7C,0x00,
+0xFC,0xC6,0xC6,0xC6,0xC6,0xC6,0xFC,0x00,
+0xFE,0xC0,0xC0,0xF8,0xC0,0xC0,0xC0,0x00,
+0x7C,0xC6,0xC0,0xC0,0xCE,0xC6,0x7E,0x00,
+0xC6,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0x00,
+0x06,0x06,0x06,0x06,0x06,0xC6,0x7C,0x00,
+0xC6,0xCC,0xD8,0xF0,0xD8,0xCC,0xC6,0x00,
+0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0x00,
+0x7E,0x06,0x0C,0x18,0x30,0x60,0x7E,0x00,
+0xC6,0xC6,0x6C,0x38,0x6C,0xC6,0xC6,0x00,
+0x7C,0xC6,0xC0,0xC0,0xC0,0xC6,0x7C,0x00,
+0xC6,0xC6,0xC6,0xC6,0xC6,0x6C,0x38,0x00,
+0xFC,0xC6,0xC6,0xFC,0xC6,0xC6,0xFC,0x00,
+0xC6,0xEE,0xFE,0xD6,0xC6,0xC6,0xC6,0x00,
+0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,
+0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,
+0x00,0x66,0x3C,0x18,0x3C,0x66,0x00,0x00,
+0x00,0x18,0x00,0x7E,0x00,0x18,0x00,0x00,
+0x00,0x00,0x7E,0x00,0x7E,0x00,0x00,0x00,
+0x66,0x66,0x66,0x3C,0x18,0x18,0x18,0x00,
+0xC6,0xE6,0xF6,0xFE,0xDE,0xCE,0xC6,0x00,
+0x03,0x06,0x0C,0x18,0x30,0x60,0xC0,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,
+0xCE,0xDB,0xDB,0xDB,0xDB,0xDB,0xCE,0x00,
+0x00,0x00,0x3C,0x7E,0x7E,0x7E,0x3C,0x00,
+0x1C,0x1C,0x18,0x1E,0x18,0x18,0x1C,0x00,
+0x1C,0x1C,0x18,0x1E,0x18,0x34,0x26,0x00,
+0x38,0x38,0x18,0x78,0x18,0x2C,0x64,0x00,
+0x38,0x38,0x18,0x78,0x18,0x18,0x38,0x00,
+0x00,0x18,0x0C,0xFE,0x0C,0x18,0x00,0x00,
+0x18,0x3C,0x7E,0xFF,0xFF,0x18,0x18,0x00,
+0x03,0x07,0x0F,0x1F,0x3F,0x7F,0xFF,0x00,
+0xC0,0xE0,0xF0,0xF8,0xFC,0xFE,0xFF,0x00,
+0x38,0x38,0x12,0xFE,0xB8,0x28,0x6C,0x00,
+0xC0,0x60,0x30,0x18,0x0C,0x06,0x03,0x00,
+0x00,0x00,0x0C,0x08,0x08,0x7F,0x3E,0x00,
+0x00,0x03,0x63,0xFF,0xFF,0x18,0x08,0x00,
+0x00,0x00,0x00,0x10,0x38,0xFF,0x7E,0x00,
+0x00,0x00,0x00,0x06,0x6E,0xFF,0x7E,0x00};
+
diff --git a/MCUME_pico2/picoo2em/cset.h b/MCUME_pico2/picoo2em/cset.h
new file mode 100644
index 0000000..49f7ecf
--- /dev/null
+++ b/MCUME_pico2/picoo2em/cset.h
@@ -0,0 +1,6 @@
+#ifndef __CSET_H
+#define __CSET_H
+
+extern const Byte cset[512];
+
+#endif
diff --git a/MCUME_pico2/picoo2em/emucfg.h b/MCUME_pico2/picoo2em/emucfg.h
new file mode 100644
index 0000000..136c245
--- /dev/null
+++ b/MCUME_pico2/picoo2em/emucfg.h
@@ -0,0 +1,116 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    20
+//#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    Oddysey Emulator"
+#define ROMSDIR "o2em"
+
+
+#define emu_Init(ROM) {odd_Init();odd_Start(ROM);}
+#define emu_Step() {odd_Step();}
+#define emu_Input(x) {odd_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  1,2,3,4,5,6,7,8,9,10,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"           "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  1,2,3,4,5,6,7,8,9,10,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*   
+const unsigned short key_map1[] = {
+  1, 2, 3, 4, 5, 6, 7, 8, 9, 10,  
+  35,36,40,39,42,34,23,42,43,44,
+  27,33,15,28,30,35,31,19,25,26,
+  
+  ACTION_NONE, 11,29,14,16,17,18,20,21,22,
+  ACTION_NONE, 36,34,13,32,12,24,23,ACTION_NONE,ACTION_NONE,
+  ACTION_NONE, 41}; 
+*/   
+/*
+"A  B  C  D  E  F  G  H  I  J" 
+ 11,12,13,14,15,16,17,18,19,20,
+ 
+"K  L  M  N  O  P  Q  R  S  T"                   
+ 21,22,23,24,25,26,27,28,29,30,
+ 
+"U  V  W  X  Y  Z                   
+ 31,32,33,34,35,36,37,36,39,40,
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picoo2em/keyboard_osd.h b/MCUME_pico2/picoo2em/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/picoo2em/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/picoo2em/picoo2em.cpp b/MCUME_pico2/picoo2em/picoo2em.cpp
new file mode 100644
index 0000000..5f80f11
--- /dev/null
+++ b/MCUME_pico2/picoo2em/picoo2em.cpp
@@ -0,0 +1,148 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "Oddemu.h"
+}
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+    //set_sys_clock_khz(250000, true);
+    //*((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(15, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();
+    }
+}
+
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawScreenPal16(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+        tft.writeScreenPal(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+    }
+}
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    volatile bool vb=vbl; 
+    //while (vbl==vb) {};   
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        while (vbl==vb) {};
+    } 
+}
+
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picoo2em/program_config.h b/MCUME_pico2/picoo2em/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/picoo2em/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/picoo2em/table.c b/MCUME_pico2/picoo2em/table.c
new file mode 100644
index 0000000..d7569db
--- /dev/null
+++ b/MCUME_pico2/picoo2em/table.c
@@ -0,0 +1,341 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   8048 Mnemonics
+ */
+
+
+#include "cpu.h"
+#include "table.h"
+
+
+struct lookup_tag lookup[] = {
+
+		/* 00 */ {"NOP",1,0},
+		/* 01 */ {"ILL",1,0},
+		/* 02 */ {"OUTL BUS,A",1,0},
+		/* 03 */ {"ADD A,",2,1},
+
+		/* 04 */ {"JMP",2,2},
+        /* 05 */ {"EN I",1,0},
+        /* 06 */ {"ILL",1,0},
+        /* 07 */ {"DEC A",1,0},
+
+		/* 08 */ {"INS A,BUS",1,0},
+		/* 09 */ {"IN A,P1",1,0},
+		/* 0A */ {"IN A,P2",1,0},
+		/* 0B */ {"ILL",1,0},
+
+		/* 0C */ {"MOVD A,P4",1,0},
+		/* 0D */ {"MOVD A,P5",1,0},
+		/* 0E */ {"MOVD A,P6",1,0},
+		/* 0F */ {"MOVD A,P7",1,0},
+
+        /* 10 */ {"INC @R0",1,0},
+        /* 11 */ {"INC @R1",1,0},
+		/* 12 */ {"JB0",2,3},
+		/* 13 */ {"ADDC A,",2,1},
+
+		/* 14 */ {"CALL",2,2},
+		/* 15 */ {"DIS I",1,0},
+		/* 16 */ {"JTF",2,3},
+		/* 17 */ {"INC A",1,0},
+
+		/* 18 */ {"INC R0",1,0},
+		/* 19 */ {"INC R1",1,0},
+        /* 1A */ {"INC R2",1,0},
+        /* 1B */ {"INC R3",1,0},
+
+		/* 1C */ {"INC R4",1,0},
+		/* 1D */ {"INC R5",1,0},
+        /* 1E */ {"INC R6",1,0},
+		/* 1F */ {"INC R7",1,0},
+
+		/* 20 */ {"XCH A,@R0",1,0},
+        /* 21 */ {"XCH A,@R1",1,0},
+		/* 22 */ {"ILL",1,0},
+		/* 23 */ {"MOV A,",2,1},
+
+		/* 24 */ {"JMP",2,2},
+		/* 25 */ {"EN TCNTI",1,0},
+		/* 26 */ {"JNT0",2,3},
+		/* 27 */ {"CLR A",1,0},
+
+		/* 28 */ {"XCH A,R0",1,0},
+		/* 29 */ {"XCH A,R1",1,0},
+        /* 2A */ {"XCH A,R2",1,0},
+		/* 2B */ {"XCH A,R3",1,0},
+
+		/* 2C */ {"XCH A,R4",1,0},
+		/* 2D */ {"XCH A,R5",1,0},
+		/* 2E */ {"XCH A,R6",1,0},
+		/* 2F */ {"XCH A,R7",1,0},
+
+		/* 30 */ {"XCHD A,@R0",1,0},
+		/* 31 */ {"XCHD A,@R1",1,0},
+		/* 32 */ {"JB1",2,3},
+		/* 33 */ {"ILL",1,0},
+
+		/* 34 */ {"CALL",2,2},
+		/* 35 */ {"DIS TCNTI",1,0},
+		/* 36 */ {"JT0",2,3},
+		/* 37 */ {"CPL A",1,0},
+
+		/* 38 */ {"ILL",1,0},
+		/* 39 */ {"OUTL P1,A",1,0},
+        /* 3A */ {"OUTL P2,A",1,0},
+		/* 3B */ {"ILL",1,0},
+
+		/* 3C */ {"MOVD P4,A",1,0},
+		/* 3D */ {"MOVD P5,A",1,0},
+		/* 3E */ {"MOVD P6,A",1,0},
+		/* 3F */ {"MOVD P7,A",1,0},
+
+		/* 40 */ {"ORL A,@R0",1,0},
+        /* 41 */ {"ORL A,@R1",1,0},
+		/* 42 */ {"MOV A,T",1,0},
+		/* 43 */ {"ORL A,",2,1},
+
+		/* 44 */ {"JMP",2,2},
+		/* 45 */ {"STRT CNT",1,0},
+		/* 46 */ {"JNT1",2,3},
+		/* 47 */ {"SWAP",1,0},
+
+		/* 48 */ {"ORL A,R0",1,0},
+		/* 49 */ {"ORL A,R1",1,0},
+		/* 4A */ {"ORL A,R2",1,0},
+		/* 4B */ {"ORL A,R3",1,0},
+                             
+		/* 4C */ {"ORL A,R4",1,0},
+		/* 4D */ {"ORL A,R5",1,0},
+        /* 4E */ {"ORL A,R6",1,0},
+		/* 4F */ {"ORL A,R7",1,0},
+
+		/* 50 */ {"ANL A,@R0",1,0},
+		/* 51 */ {"ANL A,@R1",1,0},
+		/* 52 */ {"JB2",2,3},
+		/* 53 */ {"ANL A,",2,1},
+
+		/* 54 */ {"CALL",2,2},
+		/* 55 */ {"STRT T",1,0},
+		/* 56 */ {"JT1",2,3},
+		/* 57 */ {"ILL",1,0},
+
+        /* 58 */ {"ANL A,R0",1,0},
+		/* 59 */ {"ANL A,R1",1,0},
+        /* 5A */ {"ANL A,R2",1,0},
+		/* 5B */ {"ANL A,R3",1,0},
+
+		/* 5C */ {"ANL A,R4",1,0},
+		/* 5D */ {"ANL A,R5",1,0},
+        /* 5E */ {"ANL A,R6",1,0},
+        /* 5F */ {"ANL A,R7",1,0},
+
+		/* 60 */ {"ADD A,@R0",1,0},
+		/* 61 */ {"ADD A,@R1",1,0},
+		/* 62 */ {"MOV T,A",1,0},
+		/* 63 */ {"ILL",1,0},
+
+		/* 64 */ {"JMP",2,2},
+		/* 65 */ {"STOP TCNT",1,0},
+		/* 66 */ {"ILL",1,0},
+		/* 67 */ {"RRC A",1,0},
+
+        /* 68 */ {"ADD A,R0",1,0},
+        /* 69 */ {"ADD A,R1",1,0},
+		/* 6A */ {"ADD A,R2",1,0},
+		/* 6B */ {"ADD A,R3",1,0},
+
+		/* 6C */ {"ADD A,R4",1,0},
+        /* 6D */ {"ADD A,R5",1,0},
+        /* 6E */ {"ADD A,R6",1,0},
+		/* 6F */ {"ADD A,R7",1,0},
+
+		/* 70 */ {"ADDC A,@R0",1,0},
+		/* 71 */ {"ADDC A,@R1",1,0},
+		/* 72 */ {"JB3",2,3},
+		/* 73 */ {"ILL",1,0},
+
+		/* 74 */ {"CALL",2,2},
+		/* 75 */ {"ENT0 CLK",1,0},
+		/* 76 */ {"JF1",2,3},
+		/* 77 */ {"RR A",1,0},
+
+        /* 78 */ {"ADDC A,R0",1,0},
+		/* 79 */ {"ADDC A,R1",1,0},
+		/* 7A */ {"ADDC A,R2",1,0},
+		/* 7B */ {"ADDC A,R3",1,0},
+
+		/* 7C */ {"ADDC A,R4",1,0},
+		/* 7D */ {"ADDC A,R5",1,0},
+        /* 7E */ {"ADDC A,R6",1,0},
+		/* 7F */ {"ADDC A,R7",1,0},
+
+		/* 80 */ {"MOVX A,@R0",1,0},
+		/* 81 */ {"MOVX A,@R1",1,0},
+        /* 82 */ {"ILL",1,0},
+        /* 83 */ {"RET",1,0},
+
+		/* 84 */ {"JMP",2,2},
+		/* 85 */ {"CLR F0",1,0},
+		/* 86 */ {"JNI",2,3},
+		/* 87 */ {"ILL",1,0},
+
+		/* 88 */ {"ORL BUS,",2,1},
+		/* 89 */ {"ORL P1,",2,1},
+		/* 8A */ {"ORL P2,",2,1},
+		/* 8B */ {"ILL",1,0},
+
+        /* 8C */ {"ORLD P4,A",1,0},
+        /* 8D */ {"ORLD P5,A",1,0},
+        /* 8E */ {"ORLD P6,A",1,0},
+		/* 8F */ {"ORLD P7,A",1,0},
+
+        /* 90 */ {"MOVX @R0,A",1,0},
+		/* 91 */ {"MOVX @R1,A",1,0},
+		/* 92 */ {"JB4",2,3},
+		/* 93 */ {"RETR",1,0},
+
+		/* 94 */ {"CALL",2,2},
+		/* 95 */ {"CPL F0",1,0},
+		/* 96 */ {"JNZ",2,3},
+		/* 97 */ {"CLR C",1,0},
+
+		/* 98 */ {"ANL BUS,",2,1},
+		/* 99 */ {"ANL P1,",2,1},
+		/* 9A */ {"ANL P2,",2,1},
+		/* 9B */ {"ILL",1,0},
+
+		/* 9C */ {"ANLD P4,A",1,0},
+		/* 9D */ {"ANLD P5,A",1,0},
+        /* 9E */ {"ANLD P6,A",1,0},
+		/* 9F */ {"ANLD P7,A",1,0},
+
+		/* A0 */ {"MOV @R0,A",1,0},
+        /* A1 */ {"MOV @R1,A",1,0},
+        /* A2 */ {"ILL",1,0},
+        /* A3 */ {"MOVP A,@A",1,0},
+
+		/* A4 */ {"JMP",2,2},
+        /* A5 */ {"CLR F1",1,0},
+		/* A6 */ {"ILL",1,0},
+		/* A7 */ {"CPL C",1,0},
+
+        /* A8 */ {"MOV R0,A",1,0},
+		/* A9 */ {"MOV R1,A",1,0},
+		/* AA */ {"MOV R2,A",1,0},
+		/* AB */ {"MOV R3,A",1,0},
+        /* AC */ {"MOV R4,A",1,0},
+        /* AD */ {"MOV R5,A",1,0},
+        /* AE */ {"MOV R6,A",1,0},
+		/* AF */ {"MOV R7,A",1,0},
+
+		/* B0 */ {"MOV @R0,",2,1},
+		/* B1 */ {"MOV @R1,",2,1},
+		/* B2 */ {"JB5",2,3},
+		/* B3 */ {"JMPP @A",1,0},
+
+		/* B4 */ {"CALL",2,2},
+		/* B5 */ {"CPL F1",1,0},
+		/* B6 */ {"JF0",2,3},
+		/* B7 */ {"ILL",1,0},
+
+		/* B8 */ {"MOV R0,",2,1},
+		/* B9 */ {"MOV R1,",2,1},
+		/* BA */ {"MOV R2,",2,1},
+		/* BB */ {"MOV R3,",2,1},
+
+		/* BC */ {"MOV R4,",2,1},
+		/* BD */ {"MOV R5,",2,1},
+		/* BE */ {"MOV R6,",2,1},
+		/* BF */ {"MOV R7,",2,1},
+
+		/* C0 */ {"ILL",1,0},
+        /* C1 */ {"ILL",1,0},
+        /* C2 */ {"ILL",1,0},
+        /* C3 */ {"ILL",1,0},
+
+		/* C4 */ {"JMP",2,2},
+        /* C5 */ {"SEL RB0",1,0},
+		/* C6 */ {"JZ",2,3},
+		/* C7 */ {"MOV A,PSW",1,0},
+
+		/* C8 */ {"DEC R0",1,0},
+		/* C9 */ {"DEC R1",1,0},
+        /* CA */ {"DEC R2",1,0},
+		/* CB */ {"DEC R3",1,0},
+
+        /* CC */ {"DEC R4",1,0},
+        /* CD */ {"DEC R5",1,0},
+		/* CE */ {"DEC R6",1,0},
+		/* CF */ {"DEC R7",1,0},
+
+		/* D0 */ {"XRL A,@R0",1,0},
+		/* D1 */ {"XRL A,@R1",1,0},
+		/* D2 */ {"JB6",2,3},
+		/* D3 */ {"XRL A,",2,1},
+
+		/* D4 */ {"CALL",2,2},
+		/* D5 */ {"SEL RB1",1,0},
+        /* D6 */ {"ILL",1,0},
+        /* D7 */ {"MOV PSW,A",1,0},
+
+		/* D8 */ {"XRL A,R0",1,0},
+		/* D9 */ {"XRL A,R1",1,0},
+        /* DA */ {"XRL A,R2",1,0},
+		/* DB */ {"XRL A,R3",1,0},
+        /* DC */ {"XRL A,R4",1,0},
+		/* DD */ {"XRL A,R5",1,0},
+        /* DE */ {"XRL A,R6",1,0},
+		/* DF */ {"XRL A,R7",1,0},
+
+		/* E0 */ {"ILL",1,0},
+        /* E1 */ {"ILL",1,0},
+        /* E2 */ {"ILL",1,0},
+        /* E3 */ {"MOVP3 A,@A",1,0},
+
+		/* E4 */ {"JMP",2,2},
+		/* E5 */ {"SEL MB0",1,0},
+		/* E6 */ {"JNC",2,3},
+		/* E7 */ {"RL A",1,0},
+
+		/* E8 */ {"DJNZ R0,",2,3},
+		/* E9 */ {"DJNZ R1,",2,3},
+		/* EA */ {"DJNZ R2,",2,3},
+		/* EB */ {"DJNZ R3,",2,3},
+		/* EC */ {"DJNZ R4,",2,3},
+		/* ED */ {"DJNZ R5,",2,3},
+		/* EE */ {"DJNZ R6,",2,3},
+		/* EF */ {"DJNZ R7,",2,3},
+
+        /* F0 */ {"MOV A,@R0",1,0},
+        /* F1 */ {"MOV A,@R1",1,0},
+		/* F2 */ {"JB7",2,3},
+		/* F3 */ {"ILL",1,0},
+
+		/* F4 */ {"CALL",2,2},
+		/* F5 */ {"SEL MB1",1,0},
+		/* F6 */ {"JC",2,3},
+		/* F7 */ {"RLC A",1,0},
+
+		/* F8 */ {"MOV A,R0",1,0},
+		/* F9 */ {"MOV A,R1",1,0},
+		/* FA */ {"MOV A,R2",1,0},
+		/* FB */ {"MOV A,R3",1,0},
+		/* FC */ {"MOV A,R4",1,0},
+		/* FD */ {"MOV A,R5",1,0},
+        /* FE */ {"MOV A,R6",1,0},
+        /* FF */ {"MOV A,R7",1,0}
+
+};
+
+
diff --git a/MCUME_pico2/picoo2em/table.h b/MCUME_pico2/picoo2em/table.h
new file mode 100644
index 0000000..2c80c59
--- /dev/null
+++ b/MCUME_pico2/picoo2em/table.h
@@ -0,0 +1,10 @@
+#ifndef __TABLE_H
+#define __TABLE_H
+
+extern struct lookup_tag {
+	signed char *mnemonic; //JMH
+	unsigned char bytes;
+	unsigned char type;
+} lookup[];
+
+#endif
diff --git a/MCUME_pico2/picoo2em/types.h b/MCUME_pico2/picoo2em/types.h
new file mode 100644
index 0000000..885e605
--- /dev/null
+++ b/MCUME_pico2/picoo2em/types.h
@@ -0,0 +1,9 @@
+#ifndef TYPES_H
+#define TYPES_H
+
+typedef unsigned char 	Byte;
+typedef unsigned short 	ADDRESS;
+#define INLINE
+
+#endif  /* TYPES_H */
+
diff --git a/MCUME_pico2/picoo2em/vdc.c b/MCUME_pico2/picoo2em/vdc.c
new file mode 100644
index 0000000..043e61e
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vdc.c
@@ -0,0 +1,468 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   O2 Video Display Controller emulation
+ */
+
+
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "types.h"
+#include "vmachine.h"
+#include "config.h"
+#include "cset.h"
+#include "cpu.h"
+#include "vpp.h"
+#include "vdc.h"
+
+#include "emuapi.h"
+
+
+typedef struct
+{
+  unsigned char r;
+  unsigned char g;
+  unsigned char b;
+} PALETTE_ENTRY;
+
+
+#define COL_SP0   0x01
+#define COL_SP1   0x02
+#define COL_SP2   0x04
+#define COL_SP3   0x08
+#define COL_VGRID 0x10
+#define COL_HGRID 0x20
+#define COL_VPP   0x40
+#define COL_CHAR  0x80
+
+#define X_START     8
+#define Y_START		24
+
+static const long colortable[16]={
+	0x000000,
+	0x0e3dd4,
+	0x00981b,
+	0x00bbd9,
+	0xc70008,
+	0xcc16b3,
+	0x9d8710,
+	0xe1dee1,
+	0x5f6e6b,
+	0x6aa1ff,
+	0x3df07a,
+	0x31ffff,
+	0xff4255,
+	0xff98ff,
+	0xd9ad5d,
+	0xffffff
+};
+
+
+
+
+/* The pointer to the graphics buffer And palette */
+
+static PALETTE_ENTRY colors[256];
+static Byte * vscreen=0; //[BMPW*BMPH];
+
+/* Collision buffer */
+static Byte * colbuf=0; //[BMPW*BMPH];
+
+Byte coltab[256];
+
+long clip_low;
+long clip_high;
+
+
+static void create_cmap(void);
+static void draw_char(Byte ypos,Byte xpos,Byte chr,Byte col);
+static void draw_grid(void);
+INLINE extern void mputvid(unsigned int ad, unsigned int len, Byte d, Byte c);
+
+
+unsigned char * getGBuf(void)
+{
+	return(vscreen);
+}
+
+void draw_region(void){
+	int i;
+
+  //emu_printi(last_line);
+
+	if (regionoff == 0xffff)
+		i = master_clk/(LINECNT-1)-5;
+	else
+		i = master_clk/22+regionoff;
+	//i = snapline(i, VDCwrite[0xA0], 0);
+
+	if (i<0) i=0;
+
+#ifdef HALFHEIGHT
+  i = i>>1;
+#else
+#endif
+ 
+ 	clip_low = last_line * (long)BMPW;
+	clip_high = i * (long)BMPW;
+	if (clip_high > BMPW*BMPH) clip_high = BMPW*BMPH;
+	if (clip_low < 0) clip_low=0; 
+	if (clip_low < clip_high) draw_display();
+	last_line=i;
+}
+
+
+#define fastmputvid1(ad,d,c) if ((ad > (unsigned long)clip_low) && (ad < (unsigned long)clip_high)) { vscreen[ad]=d; colbuf[ad] |= c; coltab[c] |= colbuf[ad];}
+#define fastmputvid2(ad,d,c) if ((ad > (unsigned long)clip_low) && (ad < (unsigned long)clip_high)) { vscreen[ad]=d; colbuf[ad] |= c; coltab[c] |= colbuf[ad];vscreen[ad+1]=d; colbuf[ad+1] |= c; coltab[c] |= colbuf[ad+1];}
+//#define fastmputvid1(ad,d,c) mputvid(ad,1,d,c);
+//#define fastmputvid2(ad,d,c) mputvid(ad,2,d,c);
+ 
+
+INLINE void mputvid(unsigned int ad, unsigned int len, Byte d, Byte c){
+	if ((ad > (unsigned long)clip_low) && (ad < (unsigned long)clip_high)) {
+		unsigned int i;
+// JMH
+        Byte d1; 
+		d1 = d;
+		if ( ((len & 3)==0) && (sizeof(unsigned long) == 4) && ((ad & 3) == 0) ) 
+		{
+			unsigned long dddd = (((unsigned long)d1) & 0xff) | ((((unsigned long)d1) & 0xff) << 8) | ((((unsigned long)d1) & 0xff) << 16) | ((((unsigned long)d1) & 0xff) << 24);
+			unsigned long cccc = (((unsigned long)c) & 0xff) | ((((unsigned long)c) & 0xff) << 8) | ((((unsigned long)c) & 0xff) << 16) | ((((unsigned long)c) & 0xff) << 24);
+			for (i=0; i<len>>2; i++) {
+				*((unsigned long*)(vscreen+ad)) = dddd;
+				cccc |= *((unsigned long*)(colbuf+ad));
+				*((unsigned long*)(colbuf+ad)) = cccc;
+				coltab[c] |= ((cccc | (cccc >> 8) | (cccc >> 16) | (cccc >> 24)) & 0xff);
+				ad += 4;
+			}
+		} else 
+		{
+			for (i=0; i<len; i++) {
+				vscreen[ad]=d1;
+				colbuf[ad] |= c;
+				coltab[c] |= colbuf[ad++];
+			}
+		}
+	}
+}
+
+static void create_cmap(void){
+  int i;
+
+  /* Initialise parts of the colors array */
+  for (i = 0; i < 16; i++) {
+      /* Use the color values from the color table */
+      colors[i+32].r = colors[i].r = (colortable[i] & 0xff0000) >> 16; //18;
+      colors[i+32].g = colors[i].g = (colortable[i] & 0x00ff00) >> 8; //10;
+      colors[i+32].b = colors[i].b = (colortable[i] & 0x0000ff) >> 0; //2;
+  }
+
+  for (i = 16; i < 32; i++) {
+      /* Half-bright colors for the 50% scanlines */
+      colors[i+32].r = colors[i].r = colors[i-16].r/2;
+      colors[i+32].g = colors[i].g = colors[i-16].g/2;
+      colors[i+32].b = colors[i].b = colors[i-16].b/2;
+  }
+	
+  for (i = 64; i < 256; i++) colors[i].r = colors[i].g = colors[i].b = 0;
+  
+  for (i=0;i<256;i++)
+  {  
+	emu_SetPaletteEntry(colors[i].r, colors[i].g, colors[i].b, i);
+  }
+
+}
+
+static void draw_char(Byte ypos,Byte xpos,Byte chr,Byte col){
+	int j,c;
+	Byte cl,d1;
+	int y,b,n;
+	unsigned int pnt;
+
+#ifdef HALFHEIGHT
+  y = ypos>>1;
+#else
+  y=(ypos & 0xFE);
+#endif
+	pnt = y * BMPW + (xpos-8)+BORDERW;
+
+	ypos = ypos >> 1;
+	n = 8 - (ypos % 8) - (chr % 8);
+	if (n < 3) n = n + 7;
+	
+#ifdef HALFHEIGHT
+  if ((pnt+BMPW*n >= (unsigned long)clip_low) && (pnt <= (unsigned long)clip_high)) {
+#else
+  if ((pnt+BMPW*2*n >= (unsigned long)clip_low) && (pnt <= (unsigned long)clip_high)) {
+#endif
+
+		c=(int)chr + ypos;
+		if (col & 0x01) c+=256;
+		if (c > 511) c=c-512;
+
+		cl = ((col & 0x0E) >> 1);
+		cl = ((cl&2) | ((cl&1)<<2) | ((cl&4)>>2)) + 8;
+
+#ifdef HALFHEIGHT
+    if ((y>0) && (y<112) && (xpos<157)) {
+#else
+    if ((y>0) && (y<232) && (xpos<157)) {
+#endif
+			for (j=0; j<n; j++) {
+				d1 = cset[c+j];
+				for (b=0; b<8; b++) {
+					if (d1 & 0x80) {
+#ifdef HALFHEIGHT
+            if ((xpos-8+b < 160) && (y+j < 120)) {
+#else
+            if ((xpos-8+b < 160) && (y+j < 240)) {
+#endif
+							fastmputvid1(pnt,cl,COL_CHAR);
+#ifdef HALFHEIGHT
+#else
+              fastmputvid1(pnt+BMPW,cl,COL_CHAR);
+#endif
+						}
+					}
+					pnt+=1;
+					d1 = d1 << 1;
+				}
+#ifdef HALFHEIGHT
+        pnt += BMPW-8;
+#else
+        pnt += BMPW*2-8;
+#endif
+			}
+		}
+	}
+}
+
+static void draw_grid(void){
+	unsigned int pnt, pn1;
+	Byte mask,d;
+	int j,i,x,w;
+	Byte color;
+
+	if (VDCwrite[0xA0] & 0x40) {
+		for(j=0; j<9; j++) {
+#ifdef HALFHEIGHT
+      pnt = (((j*12)+12) * BMPW);
+#else
+      pnt = (((j*24)+24) * BMPW);
+#endif
+			for (i=0; i<9; i++) {
+				pn1 = pnt + (i * 16) + BORDERW;
+				color = ColorVector[j*24+24];
+				fastmputvid2(pn1, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+				color = ColorVector[j*24+25];
+				fastmputvid2(pn1+BMPW, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+#ifdef HALFHEIGHT
+#else
+        color = ColorVector[j*24+26];
+        fastmputvid2(pn1+BMPW*2, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+#endif
+			}
+		}
+	}
+
+	// horizontal 
+	mask=0x01;
+	for(j=0; j<9; j++) {
+#ifdef HALFHEIGHT
+    pnt = (((j*12)+12) * BMPW);
+#else
+    pnt = (((j*24)+24) * BMPW);
+#endif
+		for (i=0; i<9; i++) {
+			pn1 = pnt + (i * 16) + BORDERW;
+#ifdef HALFHEIGHT
+      if ((pn1+BMPW*2 >= (unsigned long)clip_low) && (pn1 <= (unsigned long)clip_high)) {
+#else
+      if ((pn1+BMPW*3 >= (unsigned long)clip_low) && (pn1 <= (unsigned long)clip_high)) {
+#endif
+				d=VDCwrite[0xC0 + i];
+				if (j == 8) {
+					d=VDCwrite[0xD0+i];
+					mask=1;
+				}
+				if (d & mask)	{
+					color = ColorVector[j*24+24];
+					mputvid(pn1, 18, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+					color = ColorVector[j*24+25];
+					mputvid(pn1+BMPW, 18, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+#ifdef HALFHEIGHT
+#else
+          color = ColorVector[j*24+26];
+          mputvid(pn1+BMPW*2, 18, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_HGRID);
+#endif
+				}
+			}
+		}
+		mask = mask << 1;
+	}
+
+	// vertical
+	mask=0x01;
+	w=2;
+	if (VDCwrite[0xA0] & 0x80) w=16;
+	for(j=0; j<10; j++) {
+		pnt=(j*16);
+		mask=0x01;
+		d=VDCwrite[0xE0+j];
+		for (x=0; x<8; x++) {
+#ifdef HALFHEIGHT
+      pn1 = pnt + (((x*12)+12) * BMPW) + BORDERW;
+#else
+      pn1 = pnt + (((x*24)+24) * BMPW) + BORDERW;
+#endif
+			if (d & mask) {
+#ifdef HALFHEIGHT
+        for(i=0; i<12; i++) {
+#else
+        for(i=0; i<24; i++) {
+#endif
+					if ((pn1 >= (unsigned long)clip_low) && (pn1 <= (unsigned long)clip_high)) {
+						color = ColorVector[x*24+24+i];
+						mputvid(pn1, w, (color & 0x07) | ((color & 0x40) >> 3) | (color & 0x80 ? 0 : 8), COL_VGRID);
+					}
+					pn1+=BMPW;
+				}
+			}
+			mask = mask << 1;
+		}
+	}
+
+}
+
+
+void finish_display(void){
+	vpp_finish_bmp(vscreen, 9, 5, BMPW-9, BMPH-5, BMPW, BMPH);
+}
+
+
+void clear_collision(void){
+	load_colplus(colbuf);
+	coltab[0x01]=coltab[0x02]=0;
+	coltab[0x04]=coltab[0x08]=0;
+	coltab[0x10]=coltab[0x20]=0;
+	coltab[0x40]=coltab[0x80]=0;
+}
+
+
+void draw_display(void){
+	int i,j,x,sm,t;
+	Byte y,xt,yt,b,d1,cl,c;
+	unsigned int pnt,pnt2;
+
+#ifdef HALFHEIGHT
+  for (i=clip_low/BMPW; i<clip_high/BMPW; i++) {
+    memset(vscreen+i*BMPW, ((ColorVector[i<<1] & 0x38) >> 3) | (ColorVector[i<<1] & 0x80 ? 0 : 8), BMPW);
+  }
+#else
+  for (i=clip_low/BMPW; i<clip_high/BMPW; i++) {
+    memset(vscreen+i*BMPW, ((ColorVector[i] & 0x38) >> 3) | (ColorVector[i] & 0x80 ? 0 : 8), BMPW);
+  }
+#endif
+	
+	if (VDCwrite[0xA0] & 0x08) draw_grid();
+
+	if (useforen && (!(VDCwrite[0xA0] & 0x20))) return;
+	
+	for(i=0x10; i<0x40; i+=4) draw_char(VDCwrite[i],VDCwrite[i+1],VDCwrite[i+2],VDCwrite[i+3]);
+
+	pnt=0x40;
+	for(i=0; i<4; i++) {
+		x=y=248;
+		for (j=0; j<4; j++){
+			xt = VDCwrite[pnt+j*4+1];
+			yt = VDCwrite[pnt+j*4];
+      if ((xt<240) && (yt<240)){
+				x=xt;
+				y=yt;
+				break;
+			}
+		}
+		for(j=0; j<4; j++) {
+			draw_char(y,x,VDCwrite[pnt+2],VDCwrite[pnt+3]);
+			x+=16;
+			pnt+=4;
+		}
+	}
+	
+	c=8;
+	for (i=12; i>=0; i -=4) {
+		pnt2 = 0x80 + (i * 2);
+#ifdef HALFHEIGHT
+    y = VDCwrite[i]>>1;
+#else
+    y = VDCwrite[i];
+#endif
+		x = VDCwrite[i+1]-8;
+		t = VDCwrite[i+2];
+		cl = ((t & 0x38) >> 3);
+		cl = ((cl&2) | ((cl&1)<<2) | ((cl&4)>>2)) + 8;
+//#ifdef HALFHEIGHT
+//    if ((x<164) && (y>0) && (y<112)) {
+//#else
+    if ((x<164) && (y>0) && (y<232)) {
+//#endif
+			pnt = y * BMPW + x + BORDERW + sproff;
+			if ((pnt+BMPW*16 >= (unsigned long)clip_low) && (pnt <= (unsigned long)clip_high)) {
+				for (j=0; j<8; j++) {
+					sm = (((j%2==0) && (((t>>1) & 1) != (t & 1))) || ((j%2==1) && (t & 1))) ? 1 : 0;
+					d1 = VDCwrite[pnt2++];
+					for (b=0; b<8; b++) {
+						if (d1 & 0x01) {
+#ifdef HALFHEIGHT
+              if ((x+b+sm<160) && (y+j<129)) {
+#else
+              if ((x+b+sm<160) && (y+j<249)) {
+#endif
+								fastmputvid1(sm+pnt,cl,c);
+#ifdef HALFHEIGHT
+#else
+                fastmputvid1(sm+pnt+BMPW,cl,c);
+#endif
+							}
+						}
+						pnt += 1;
+						d1 = d1 >> 1;
+					}
+#ifdef HALFHEIGHT
+          pnt += BMPW-8;
+#else
+          pnt += BMPW*2-8;
+#endif
+				}
+			}
+		}
+		c = c >> 1;
+	}
+}
+
+
+
+
+void close_display(void) 
+{
+}
+
+void init_display(void) 
+{
+	if (vscreen==0) vscreen = (Byte *)emu_Malloc(BMPW*BMPH);
+	if (colbuf == 0) colbuf = (Byte *)emu_Malloc(BMPW*BMPH);
+
+	create_cmap();
+	memset(colbuf,0,BMPW*BMPH);
+}
+
diff --git a/MCUME_pico2/picoo2em/vdc.h b/MCUME_pico2/picoo2em/vdc.h
new file mode 100644
index 0000000..9aae77a
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vdc.h
@@ -0,0 +1,30 @@
+#ifndef __VDC_H
+#define __VDC_H
+
+#define HALFHEIGHT 1
+
+#define BORDERW 8
+#define BMPW (160+BORDERW) // 320
+#ifdef HALFHEIGHT
+#define BMPH 120
+#else
+#define BMPH 240
+#endif
+
+
+extern Byte coltab[];
+extern long clip_low;
+extern long clip_high;
+
+extern unsigned char * getGBuf(void);
+
+void init_display(void);
+void draw_display(void);
+void draw_region(void);
+void finish_display();
+void close_display(void);
+void clear_collision(void);
+
+#endif
+
+
diff --git a/MCUME_pico2/picoo2em/vmachine.c b/MCUME_pico2/picoo2em/vmachine.c
new file mode 100644
index 0000000..7438d8e
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vmachine.c
@@ -0,0 +1,679 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   Main O2 machine emulation
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <time.h>
+#include "audio.h"
+#include "types.h"
+#include "cpu.h"
+#include "config.h"
+#include "vdc.h" 
+//#include "vpp.h"
+#include "vmachine.h"
+#include "kbd.h"
+
+#include "emuapi.h"
+
+static Byte x_latch,y_latch;
+static Byte line_count;
+static int fps=FPS_NTSC;
+
+//static Byte snapedlines[MAXLINES+2*MAXSNAP][256][2]; //500+2*50 *256*2 600*512
+
+int evblclk=EVBLCLK_NTSC;
+
+struct resource app_data;
+int frame=0;
+Byte dbstick1,dbstick2;
+
+int int_clk; 	/* counter for length of /INT pulses */
+int master_clk;	/* Master clock */
+int h_clk;   /* horizontal clock */
+unsigned long clk_counter;
+int last_line;
+int key2vcnt=0;
+int mstate;
+int ccolflag=0;
+
+int pendirq=0;
+int enahirq=1;
+int useforen=0;
+long regionoff=0xffff;
+int mxsnap=2;
+int sproff=0;
+int tweakedaudio=0;
+
+Byte rom1[5120];
+Byte rom2[5120];
+Byte rom3[5120];
+Byte rom4[5120];
+
+Byte intRAM[64];
+Byte extRAM[256];
+Byte extROM[1024];
+Byte VDCwrite[256];
+Byte ColorVector[MAXLINES];
+Byte AudioVector[MAXLINES];
+Byte *rom, *orom;
+
+int key2[128];
+
+#define KEY_0 0
+#define KEY_1 1
+#define KEY_2 2
+#define KEY_3 3
+#define KEY_4 4
+#define KEY_5 5
+#define KEY_6 6
+#define KEY_7 7
+#define KEY_8 8
+#define KEY_9 9
+#define KEY_A 10
+#define KEY_B 11
+#define KEY_C 12
+#define KEY_D 13
+#define KEY_E 14
+#define KEY_F 15
+#define KEY_G 16
+#define KEY_H 17
+#define KEY_I 18
+#define KEY_J 19
+#define KEY_K 20
+#define KEY_L 21
+#define KEY_M 22
+#define KEY_N 23
+#define KEY_O 24
+#define KEY_P 25
+#define KEY_Q 26
+#define KEY_R 27
+#define KEY_S 28
+#define KEY_T 29
+#define KEY_U 30
+#define KEY_V 31
+#define KEY_W 32
+#define KEY_X 33
+#define KEY_Y 34
+#define KEY_Z 35
+#define KEY_PLUS 35
+#define KEY_MINUS 36
+#define KEY_SLASH 38
+#define KEY_ASTERISK 39
+
+#define KEY_SPACE 40
+#define KEY_EQUALS 41
+#define KEY_DEL 42
+#define KEY_ENTER 43
+#define KEY_STOP 44
+#define KEY_SLASH_PAD 45
+#define KEY_PLUS_PAD 46
+
+static unsigned int key_map[6][8]= {
+	{KEY_0,KEY_1,KEY_2,KEY_3,KEY_4,KEY_5,KEY_6,KEY_7},
+	{KEY_8,KEY_9,0,0,KEY_SPACE,KEY_SLASH,KEY_L,KEY_P},
+	{KEY_PLUS_PAD,KEY_W,KEY_E,KEY_R,KEY_T,KEY_U,KEY_I,KEY_O},
+	{KEY_Q,KEY_S,KEY_D,KEY_F,KEY_G,KEY_H,KEY_J,KEY_K},
+	{KEY_A,KEY_Z,KEY_X,KEY_C,KEY_V,KEY_B,KEY_M,KEY_STOP},
+	{KEY_MINUS,KEY_ASTERISK,KEY_SLASH_PAD,KEY_EQUALS,KEY_Y,KEY_N,KEY_DEL,KEY_ENTER}
+};
+
+
+
+
+static void do_kluges(void);
+static void setvideomode(int t);
+
+static int ik;     // joypad key
+static int ihk;    // I2C keyboard key
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+void odd_Input(int key) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();  
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  //else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  //else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  //else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  //else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  //else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+
+void run(void){
+  cpu_exec();
+}
+
+
+void handle_vbl(void){
+		update_audio();
+//		update_voice();
+//	}
+	if (!ccolflag) {
+		clear_collision();
+		ccolflag=1;
+	}
+	draw_region();
+	ext_IRQ();
+	mstate = 1;
+}
+
+
+void handle_evbl(void){
+	static long last=0;
+	static int rest_cnt=0;
+	int i;
+
+	i = (15*app_data.speed/100);
+	rest_cnt = (rest_cnt+1)%(i<5?5:i);
+	last_line=0;
+	master_clk -= evblclk;
+	frame++;
+	ccolflag=0;
+	if (!app_data.debug) {
+		finish_display();
+	}
+
+	for (i=0; i<MAXLINES; i++)  {
+		ColorVector[i] = (VDCwrite[0xA3] & 0x7f) | (p1 & 0x80);
+		AudioVector[i] = VDCwrite[0xAA];
+	}
+
+	if (key2vcnt++ > 10) {
+		key2vcnt=0;
+		for (i=0; i<128; i++) key2[i] = 0;
+		dbstick1 = dbstick2 = 0;
+	}
+	mstate=0;	
+}
+
+
+void init_system(void){
+	int i,j,k;
+
+	last_line=0;
+	dbstick1=0x00;
+	dbstick2=0x00;
+	mstate=0;
+	master_clk=0;
+	h_clk=0;
+	line_count=0;
+	itimer=0;
+	clk_counter=0;
+	for(i=0; i<256; i++) {
+		VDCwrite[i]=0;
+		extRAM[i]=0;
+	}
+	for(i=0; i<64; i++) {
+		intRAM[i]=0;
+	}
+	for (i=0; i<MAXLINES; i++) AudioVector[i] = ColorVector[i] = 0;
+	ccolflag=0;
+/*
+	for (i=0; i<MAXLINES+2*MAXSNAP; i++)
+		for (j=0; j<256; j++)
+			for (k=0; k<2; k++)
+				snapedlines[i][j][k]=0;
+*/				
+	for (i=0; i<128; i++) key2[i] = 0;
+	key2vcnt=0;
+	if (app_data.euro)
+		setvideomode(1);
+	else
+		setvideomode(0);
+	do_kluges();
+	//init_vpp();
+}
+
+
+Byte read_t1(void){
+	if ((h_clk > 16) || (master_clk > VBLCLK))
+		return 1;
+	else
+		return 0;
+}
+
+
+void write_p1(Byte d){
+	if ((d & 0x80) != (p1 & 0x80)) {
+		int i,l;
+		//l = snapline((int)((float)master_clk/22.0+0.5), VDCwrite[0xA3], 1);
+		for (i=l; i<MAXLINES; i++) ColorVector[i] = (VDCwrite[0xA3] & 0x7f) | (d & 0x80);
+	}
+	p1 = d;
+	if (app_data.bank == 2) {
+		if (p1 & 0x01)
+			rom=rom2;
+		else
+			rom=rom1;
+	}
+	if (app_data.bank == 3) {
+		switch(p1 & 0x03) {
+			case 0:
+				rom=rom1;
+				break;
+			case 1:
+				rom=rom2;
+				break;
+			case 2:
+				rom=rom3;
+				break;
+			case 3:
+				rom=rom4;
+				break;
+		}
+	}
+}
+
+
+Byte read_P2(void){
+	int i,si,so,km;
+  
+  int k=ik&0x7f;
+  int hk = ihk; //&0x7f;  
+  if (iusbhk) hk = iusbhk;
+  
+  if (k & MASK_KEY_USER1) { // 1
+    k = 1;
+  }
+
+  switch(hk) {
+    case 'q':
+    case '1':
+      hk = 2;
+      break;
+    case 'w':
+    case '2':
+      hk = 3;
+      break;
+    case 'e':
+    case '3':
+      hk = 4;
+      break;
+    case 'r':
+    case '4':
+      hk = 5;
+      break;
+    case 't':
+    case '5':
+      hk = 6;
+      break;
+    case 'y':
+    case '6':
+      hk = 7;
+      break;
+    case 'u':
+    case '7':
+      hk = 8;
+      break;
+    case 'i':
+    case '8':
+      hk = 9;
+      break;
+    case 'o':
+    case '9':
+      hk = 10;
+    case 'p':
+    case '0':
+      hk = 1;
+      break;
+    default:
+      hk = 0;
+      break;
+  };
+
+  if (!(p1 & 0x04)) {
+    si = (p2 & 7);
+    so=0xff;
+    if (si<6) {
+      for (i=0; i<8; i++) {
+        km = key_map[si][i];
+                if ( (km == (k-1)) && (k) )
+        {
+          so = i ^ 0x07;
+        }
+        else if ( (km == (hk-1)) && (hk) )
+        {
+          so = i ^ 0x07;
+        }       
+//        if ((key[km] && ((!joykeystab[km]) || (key_shifts & KB_CAPSLOCK_FLAG))) || (key2[km])) {
+//          so = i ^ 0x07;
+//        }
+      }
+    }
+
+		if (so != 0xff) {
+			p2 = p2 & 0x0F;
+			p2 = p2 | (so << 5);
+		} else {
+			p2 = p2 | 0xF0;
+		}
+	 } else {
+		p2 = p2 | 0xF0;
+	 }
+	 return(p2);
+}
+
+
+Byte ext_read(ADDRESS adr){
+	Byte d;
+	Byte si;
+	Byte m;
+	int i;
+
+	if (!(p1 & 0x08) && !(p1 & 0x40)) {
+		/* Handle VDC Read */
+		switch(adr) {
+			case 0xA1:
+				d = VDCwrite[0xA0] & 0x02;
+				if (master_clk > VBLCLK) d = d | 0x08;
+				if (h_clk < (LINECNT-7)) d = d | 0x01;
+				if (sound_IRQ) d = d | 0x04;
+				sound_IRQ=0;
+				return d;
+			case 0xA2:
+				si = VDCwrite[0xA2];
+				m=0x01;
+				d=0;
+				for(i=0; i<8; i++) {
+					if (si & m) {
+						if (coltab[1] & m) d = d | (coltab[1] & (m ^ 0xFF));
+						if (coltab[2] & m) d = d | (coltab[2] & (m ^ 0xFF));
+						if (coltab[4] & m) d = d | (coltab[4] & (m ^ 0xFF));
+						if (coltab[8] & m) d = d | (coltab[8] & (m ^ 0xFF));
+						if (coltab[0x10] & m) d = d | (coltab[0x10] & (m ^ 0xFF));
+						if (coltab[0x20] & m) d = d | (coltab[0x20] & (m ^ 0xFF));
+						if (coltab[0x80] & m) d = d | (coltab[0x80] & (m ^ 0xFF));
+					}
+					m = m << 1;
+				}
+				return d;
+			case 0xA5:
+				if (!(VDCwrite[0xA0] & 0x02)) {
+					return x_latch;
+				}
+				else {
+					x_latch = h_clk * 12;
+					return x_latch;
+				}			
+			case 0xA4:
+				if (!(VDCwrite[0xA0] & 0x02)) {
+					return y_latch;
+				}
+				else {
+					y_latch = master_clk/22;
+					if (y_latch > 241) y_latch=0xFF;
+					return y_latch;
+				}
+			default:
+				return VDCwrite[adr];
+		}
+	} else if (!(p1 & 0x10)) {
+		/* Handle ext RAM Read */
+		 return extRAM[adr & 0xFF];
+	//} else if (!(p1 & 0x20)) {
+	//	/* Read a Videopac+ register */
+	//	return vpp_read(adr);
+	} else if (app_data.exrom && (p1 & 0x02)) {
+		/* Handle read from exrom */
+		return extROM[(p2 << 8) | (adr & 0xFF)];
+	}
+
+	return 0;
+}
+
+
+Byte in_bus(void){
+	Byte si=0,d=0,mode=0,jn=0;
+    int key;
+	if ((p1 & 0x08) && (p1 & 0x10)) {
+		/* Handle joystick read */
+		if (!(p1 & 0x04)) {
+			si = (p2 & 7);
+		}
+		d=0xFF;
+
+		/* Get current input */
+		key = ik;
+   
+    app_data.stick[0]=0;
+    app_data.stick[1]=1;
+    /*  
+		if ( key & 0x80 )
+		{
+			app_data.stick[0]=1;
+			app_data.stick[1]=0;
+		}
+		else
+		{
+			app_data.stick[0]=0;
+			app_data.stick[1]=1;
+		}
+
+   
+		if (si == 1) {
+			mode = app_data.stick[0];
+			jn = 0;
+		} else {
+			mode = app_data.stick[1];
+			jn = 1;
+		}
+    */
+		mode=1;
+		
+		//if (key & 0x8000) jn=1;
+		//else jn=0;
+
+		switch(mode) {
+			case 1:			    
+                if (key & MASK_JOY2_RIGHT) d &= 0xF7;
+                if (key & MASK_JOY2_LEFT) d &= 0xFD;
+                if (key & MASK_JOY2_UP) d &= 0xFE;
+                if (key & MASK_JOY2_DOWN) d &= 0xFB;
+                if (key & MASK_JOY2_BTN) d &= 0xEF;
+				break;
+        
+			case 2: 
+                /* Get current input */
+//                if (key & JKEY_PLEFT)  d &= 0xF7;
+//                if (key & JKEY_PRIGHT) d &= 0xFD;
+//                if (key & JKEY_PUP)    d &= 0xFE;
+//                if (key & JKEY_PDOWN)  d &= 0xFB;
+//                if (key & JKEY_PSPACE) d &= 0xEF;
+				break;
+		}
+		if (si == 1) {
+			if (dbstick1) d = dbstick1;
+		} else {
+			if (dbstick2) d = dbstick2;
+		}
+   }
+   return d;
+}
+
+
+void ext_write(Byte dat, ADDRESS adr){
+	int i;
+
+	if (!(p1 & 0x08)) {
+		/* Handle VDC Write */		
+		if (adr == 0xA0){
+			if ((VDCwrite[0xA0] & 0x02) && !(dat & 0x02)) {
+				y_latch = master_clk/22;
+				x_latch = h_clk * 12;
+				if (y_latch > 241) y_latch=0xFF;
+			}
+			if ((master_clk <= VBLCLK) && (VDCwrite[0xA0] != dat)) {
+				if (!ccolflag) {
+					clear_collision();
+					ccolflag=1;
+				}
+				draw_region();
+			}
+		} else if (adr == 0xA2) {
+			clear_collision();
+			ccolflag=1;
+		} else if (adr == 0xA3){
+			int l;
+			//l = snapline((int)((float)master_clk/22.0+0.5), dat, 1);
+			for (i=l; i<MAXLINES; i++) ColorVector[i] = (dat & 0x7f) | (p1 & 0x80);
+		} else if (adr == 0xAA) {
+			for (i=master_clk/22; i<MAXLINES; i++) AudioVector[i]=dat;
+		}
+		VDCwrite[adr]=dat;
+	} else if (!(p1 & 0x10) && !(p1 & 0x40)) {
+		adr = adr & 0xFF;
+		if (adr < 0x80) {
+			/* Handle ext RAM Write */
+			extRAM[adr] = dat;
+		} else {
+			/* Handle The Voice */
+			if (!(dat & 0x20))
+			{
+//JMH				reset_voice();
+			}
+			else {
+//JMH
+//				if (adr == 0xE4)
+//					set_voice_bank(0);
+//				else if ((adr >= 0xE8) && (adr <= 0xEF))
+//					set_voice_bank(adr-0xE7);
+//				else if (((adr >= 0x80) && (adr <= 0xDF)) || ((adr >= 0xF0) && (adr <= 0xFF)))
+//					trigger_voice(adr);
+			}
+		}
+	//} else if (!(p1 & 0x20)) {
+	//	/* Write to a Videopac+ register */
+	//	vpp_write(dat,adr);
+	}
+}
+
+
+static void do_kluges(void){
+	if (app_data.crc == 0xA7344D1F) pendirq=1;				/* Atlantis */ 
+	if (app_data.crc == 0xFB83171E) pendirq=1;				/* Blockout*/
+	if (app_data.crc == 0x881CEAE4) pendirq=1;				/* Wall Street */
+
+	if (app_data.crc == 0x9E42E766) useforen=1;				/* Turtles */
+	if (app_data.crc == 0x1C750349) useforen=1;				/* Turtles (European version) */
+	if (app_data.crc == 0x202F2749) useforen=1;				/* Q*bert */
+
+	if (app_data.crc == 0xFB83171E) enahirq=0;				/* Blockout*/
+	
+	if (app_data.crc == 0xFB83171E) regionoff=1;			/* Blockout*/
+	if (app_data.crc == 0x202F2749) regionoff=1;			/* Q*bert */
+	if (app_data.crc == 0x5216771A) regionoff=1;			/* Popeye */
+	if (app_data.crc == 0x0C2E4811) regionoff=12;			/* Out of this World! / Helicopter Rescue! */
+	if (app_data.crc == 0x67069924) regionoff=11;			/* Smithereens! */
+	if (app_data.crc == 0x44D1A8A5) regionoff=11;			/* Smithereens! (European version) */
+	if (app_data.crc == 0xB936BD78) regionoff=12;			/* Type & Tell */
+	if (app_data.crc == 0xDC30AD3D) regionoff=10;			/* Dynasty! */
+	if (app_data.crc == 0x7810BAD5) regionoff=10;			/* Dynasty! (European) */
+	if (app_data.crc == 0xA7344D1F) regionoff=0;			/* Atlantis */ 
+	if (app_data.crc == 0xD0BC4EE6) regionoff=12;			/* Frogger */
+	if (app_data.crc == 0x825976A9) regionoff=0;			/* Mousing Cat 8kb */
+	if (app_data.crc == 0xF390BFEC) regionoff=0;			/* Mousing Cat 4kb */
+	if (app_data.crc == 0x3BFEF56B) regionoff=1;			/* Four in 1 Row! */
+	if (app_data.crc == 0x9BFC3E01) regionoff=10;			/* Demon Attack */
+	if (app_data.crc == 0x6CEBAB74) regionoff=12;			/* P.T. Barnum's Acrobats! (European version) */
+	if (app_data.crc == 0xE7B26A56) regionoff=12;			/* P.T. Barnum's Acrobats! (European version - Extra keys) */
+
+	if (app_data.crc == 0xFB83171E) mxsnap=3;				/* Blockout*/
+	if (app_data.crc == 0xA57E1724) mxsnap=12;				/* Catch the Ball / Noughts and Crosses */
+	if (app_data.crc == 0xFD179F6D) mxsnap=3;				/* Clay Pigeon! */
+	if (app_data.crc == 0x9BFC3E01) mxsnap=0;				/* Demon Attack */
+	if (app_data.crc == 0x9C9DDDF9) mxsnap=3;				/* Verkehr */
+	if (app_data.crc == 0x95936B07) mxsnap=3;				/* Super Cobra */
+	if (app_data.crc == 0x881CEAE4) mxsnap=3;				/* Wall Street */
+	if (app_data.crc == 0x9E42E766) mxsnap=0;				/* Turtles */
+	if (app_data.crc == 0x1C750349) mxsnap=0;				/* Turtles (European version) */
+	if (app_data.crc == 0xD0BC4EE6) mxsnap=3;				/* Frogger */
+	if (app_data.crc == 0x3BFEF56B) mxsnap=6;				/* Four in 1 Row! */
+
+	if (app_data.crc == 0xA7344D1F) setvideomode(1);		/* Atlantis */ 
+	if (app_data.crc == 0x39E31BF0) setvideomode(1);		/* Jake */
+	if (app_data.crc == 0x3351FEDA) setvideomode(1);		/* Power Lords */
+	if (app_data.crc == 0x40AE062D) setvideomode(1);		/* Power Lords (alternate) */
+	if (app_data.crc == 0xD158EEBA) setvideomode(1);		/* Labirinth */
+	if (app_data.crc == 0x26B0FF5B) setvideomode(1);		/* Nightmare */	
+	if (app_data.crc == 0xDF36683F) setvideomode(1);		/* Shark Hunter */	
+	if (app_data.crc == 0xAF307559) setvideomode(1);		/* Super Bee 8Kb */	
+	if (app_data.crc == 0x9585D511) setvideomode(1);		/* Super Bee 4Kb */	
+	if (app_data.crc == 0x58FA6766) setvideomode(1);		/* War of the Nerves */	
+	if (app_data.crc == 0x58FA6766) setvideomode(1);		/* War of the Nerves */	
+	if (app_data.crc == 0x39989464) setvideomode(1);		/* Hockey! / Soccer! */	
+	if (app_data.crc == 0xB47F3E0B) setvideomode(1);		/* Kill the Attacking Aliens Demo */	
+	if (app_data.crc == 0x3BFEF56B) setvideomode(1);		/* Four in 1 Row! */
+	if (app_data.crc == 0x68560DC7) setvideomode(1);		/* Jopac Moto Crash */
+	if (app_data.crc == 0x202F2749) setvideomode(0);		/* Q*bert */
+	if (app_data.crc == 0xFB83171E) setvideomode(0);		/* Blockout*/
+	if (app_data.crc == 0x9BFC3E01) setvideomode(0);		/* Demon Attack */	
+	if (app_data.crc == 0x239DF97D) setvideomode(0);		/* Pachinko! */	
+	if ((app_data.crc == 0xF390BFEC) || (app_data.crc == 0x825976A9)){	/* Mousing Cat */
+		setvideomode(1);
+		evblclk=7642;
+	}
+	if (app_data.crc == 0xD0BC4EE6) {						/* Frogger */
+		setvideomode(1);
+		evblclk=7642;
+	}
+	if ((app_data.crc == 0x2DCB77F0) || (app_data.crc == 0xF6882734)) {	/* Depth Charge / Marksman */
+		setvideomode(1);
+		evblclk=9000;
+	}
+	if (app_data.crc == 0x881CEAE4) {						/* Wall Street */
+		setvideomode(1);
+		evblclk=6100;
+	}
+	
+	if (app_data.crc == 0xD0BC4EE6) tweakedaudio=1;			/* Frogger */
+	if (app_data.crc == 0x5216771A) tweakedaudio=1;			/* Popeye */
+	if (app_data.crc == 0xAFB23F89) tweakedaudio=1;			/* Musician */
+
+	if (app_data.crc == 0xD3B09FEC) sproff=1;				/* Volleyball! */		
+}
+
+/*
+int snapline(int pos, Byte reg, int t){
+	int i;
+	for (i=0; i<mxsnap; i++){
+		if (snapedlines[pos+MAXSNAP-i][reg][t]) return pos-i;
+		if (snapedlines[pos+MAXSNAP+i][reg][t]) return pos+i;
+	}
+	snapedlines[pos+MAXSNAP][reg][t]=1;
+	return pos;
+}
+*/
+
+static void setvideomode(int t){
+	if (t) {
+		evblclk = EVBLCLK_PAL;
+		fps = FPS_PAL;
+	} else {
+		evblclk = EVBLCLK_NTSC;
+		fps = FPS_NTSC;
+	}
+}
+	
+
diff --git a/MCUME_pico2/picoo2em/vmachine.h b/MCUME_pico2/picoo2em/vmachine.h
new file mode 100644
index 0000000..5c97613
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vmachine.h
@@ -0,0 +1,91 @@
+#ifndef VMACHINE_H
+#define VMACHINE_H
+
+#include "types.h"
+
+#define LINECNT 21
+#define MAXLINES 500
+#define MAXSNAP 50
+
+#define VBLCLK 5493
+#define EVBLCLK_NTSC 5964
+#define EVBLCLK_PAL 7259
+
+#define FPS_NTSC 60
+#define FPS_PAL 50
+
+extern Byte dbstick1, dbstick2;
+extern int last_line;
+
+extern int evblclk;
+
+extern int master_clk;		/* Master clock */
+extern int int_clk;		/* counter for length of /INT pulses for JNI */
+extern int h_clk;   /* horizontal clock */
+extern int mstate;
+
+extern Byte rom1[];
+extern Byte rom2[];
+extern Byte rom3[];
+extern Byte rom4[];
+
+extern Byte intRAM[];
+extern Byte extRAM[];
+extern Byte extROM[];
+extern Byte VDCwrite[256];
+extern Byte ColorVector[MAXLINES];
+extern Byte AudioVector[MAXLINES];
+extern Byte *rom;
+extern Byte *orom;
+
+extern int frame;
+extern int key2[128];
+extern int key2vcnt;
+extern unsigned long clk_counter;
+extern int ccolflag;
+
+extern int enahirq;
+extern int pendirq;
+extern int useforen;
+extern long regionoff;
+extern int sproff;
+extern int tweakedaudio;
+
+Byte read_P2(void);
+int snapline(int pos, Byte reg, int t);
+void ext_write(Byte dat, ADDRESS adr);
+Byte ext_read(ADDRESS adr);
+void handle_vbl(void);
+void handle_evbl(void);
+Byte in_bus(void);
+void write_p1(Byte d);
+Byte read_t1(void);
+void init_system(void);
+void run(void);
+
+
+extern struct resource {
+	int bank;
+	int debug;
+	int stick[2];
+	int limit;
+	int sound_en;
+	int speed;
+	int wsize;
+	int fullscreen;
+	int scanlines;
+	int voice;
+	int svolume;
+	int vvolume;	
+	int exrom;
+	int filter;
+	int euro;
+	int openb;
+	unsigned long crc;
+	char *window_title;
+	char *scshot;
+} app_data;
+
+
+#endif  /* VMACHINE_H */
+
diff --git a/MCUME_pico2/picoo2em/vpp.c b/MCUME_pico2/picoo2em/vpp.c
new file mode 100644
index 0000000..cd26a78
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vpp.c
@@ -0,0 +1,488 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   Videopac+ G7400 emulation
+ */
+
+
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "types.h"
+#include "vmachine.h"
+#include "vdc.h"
+#include "vpp_cset.h"
+#include "vpp.h"
+
+#include "emuapi.h"
+
+typedef struct
+{
+  int w;
+  int h;
+  unsigned char * line;
+ // unsigned char line[320][250];
+} BITMAP;
+
+static void clear(BITMAP * bmp)
+{
+ int i,j;
+ 	bmp->line = (unsigned char *)emu_Malloc(BMPW*(BMPH+10));
+
+
+ for(i=0;i<bmp->h;i++)
+ for(j=0;j<bmp->w;j++)
+	 //bmp->line[i][j] = 0;
+	 *bmp->line++ = 0;
+} 
+
+
+static void vpp_draw_char(int x, int y, Byte ch, Byte c0, Byte c1, Byte ext, Byte dw, Byte dh, Byte ul);
+static void vpp_update_screen(void);
+
+
+static Byte LumReg = 0xff, TraReg = 0xff;
+static BITMAP svppbmp;
+static BITMAP * vppbmp = &svppbmp;
+//static Byte *colplus = NULL;
+//static Byte colplus[BMPW*BMPH];
+static int vppon = 1;
+static int vpp_cx = 0;
+static int vpp_cy = 0;
+static Byte vpp_data = 0;
+static int inc_curs=1;
+static int slice=0;
+static int vpp_y0=0;
+static Byte vpp_r=0;
+static Byte dchars[2][960];
+static Byte vpp_mem[40][32][4];
+static int frame_cnt=0;
+static int blink_st=0;
+static int slicemode=0;
+static int need_update=0;
+
+
+
+
+Byte read_PB(Byte p){
+	p &= 0x3;
+	switch (p) {
+		case 0:
+			return LumReg >> 4;
+			break;
+		case 1:
+			return LumReg & 0xf;
+			break;
+		case 2:
+			return TraReg >> 4;
+			break;
+		case 3:
+			return TraReg & 0xf;
+			break;
+	}
+	return 0;
+}
+
+
+void write_PB(Byte p, Byte val){
+	p &= 0x3;
+	val &= 0xf;
+
+	switch (p) {
+		case 0:
+			LumReg = (val<<4) | (LumReg & 0xf);
+			break;
+		case 1:
+			LumReg = (LumReg & 0xf0) | val;
+			break;
+		case 2:
+			TraReg = (val<<4) | (TraReg & 0xf);
+			break;
+		case 3:
+			TraReg = (TraReg & 0xf0) | val;
+			break;
+	}	
+	need_update = 1;
+}
+
+
+Byte vpp_read(ADDRESS adr){
+	Byte t;
+	switch (adr){
+		case 4:
+			return vpp_mem[vpp_cx][vpp_cy][1];
+		case 5:
+			if (slicemode) {
+				Byte ext, chr;
+				chr = vpp_mem[vpp_cx][vpp_cy][0];
+				ext = (vpp_mem[vpp_cx][vpp_cy][1] & 0x80) ? 1 : 0;
+				if (chr < 0xA0)
+					t = 0;
+				else {
+					t = dchars[ext][(chr-0xA0)*10+slice];
+					t = ((t&0x80)>>7) | ((t&0x40)>>5) | ((t&0x20)>>3) | ((t&0x10)>>1) | ((t&0x08)<<1) | ((t&0x04)<<3) | ((t&0x02)<<5) | ((t&0x01)<<7);
+				}
+				slice = (slice+1) % 10;
+			} else {
+				t = vpp_mem[vpp_cx][vpp_cy][0]; 
+				if (inc_curs) {
+					vpp_cx++;
+					if (vpp_cx >= 40) {
+						vpp_cx = 0;
+						vpp_cy++;
+						if (vpp_cy >= 24) vpp_cy = 0;
+					}
+				}
+			}
+			return t;
+		case 6:
+			return 0;
+		default:
+			return 0;
+	}
+}
+
+
+void vpp_write(Byte dat, ADDRESS adr){
+	switch (adr) {
+		case 0:
+			if (!slicemode) vpp_mem[vpp_cx][vpp_cy][1] = dat;
+			break;
+		case 1:
+			if (slicemode) {
+				Byte ext, chr;
+				chr = vpp_mem[vpp_cx][vpp_cy][0];
+				ext = (vpp_mem[vpp_cx][vpp_cy][1] & 0x80) ? 1 : 0;
+				if (chr >= 0xA0) dchars[ext][(chr-0xA0)*10+slice] = ((dat&0x80)>>7) | ((dat&0x40)>>5) | ((dat&0x20)>>3) | ((dat&0x10)>>1) | ((dat&0x08)<<1) | ((dat&0x04)<<3) | ((dat&0x02)<<5) | ((dat&0x01)<<7);
+				slice = (slice+1) % 10;
+			} else {
+				vpp_mem[vpp_cx][vpp_cy][0] = dat;
+				if ((dat>0x7f) && (dat<0xa0) && (!(vpp_mem[vpp_cx][vpp_cy][1] & 0x80))) {
+					vpp_mem[vpp_cx][vpp_cy][2] = dat;
+					vpp_mem[vpp_cx][vpp_cy][3] = vpp_mem[vpp_cx][vpp_cy][1];
+				} else {
+					vpp_mem[vpp_cx][vpp_cy][2] = vpp_mem[vpp_cx][vpp_cy][3] = 0;
+				}
+				if (inc_curs) {
+					vpp_cx++;
+					if (vpp_cx >= 40) {
+						vpp_cx = 0;
+						vpp_cy++;
+						if (vpp_cy >= 24) vpp_cy = 0;
+					}
+				}
+			}
+			break;
+		case 2:
+			vpp_data = dat;
+			break;
+		case 3:
+			switch (dat & 0xe0) {
+				case 0x00:	/* plus_cmd_brow */
+					vpp_cy = vpp_data & 0x1f;
+					vpp_cx = 0;
+					break;
+				case 0x20:	/* plus_cmd_loady */
+					vpp_cy = vpp_data & 0x1f;
+					break;
+				case 0x40:	/* plus_cmd_loadx */
+					vpp_cx = vpp_data % 40;
+					break;
+				case 0x60:	/* plus_cmd_incc */
+					vpp_cx++;
+					if (vpp_cx >= 40) {
+						vpp_cx = 0;
+						vpp_cy++;
+						if (vpp_cy >= 24) vpp_cy = 0;
+					}
+					break;
+				case 0x80:	/* plus_cmd_loadm */
+					slicemode = 0;
+					slice = (vpp_data & 0x1f) % 10;
+					switch (vpp_data & 0xe0) {
+						case 0x00:	/* plus_loadm_wr */
+							inc_curs = 1;
+							break;
+						case 0x20:	/* plus_loadm_rd */
+							inc_curs = 1;
+							break;
+						case 0x40:	/* plus_loadm_wrni */
+							inc_curs = 0;
+							break;
+						case 0x60:	/* plus_loadm_rdni */
+							inc_curs = 0;
+							break;
+						case 0x80:	/* plus_loadm_wrsl */
+							slicemode = 1;
+							break;
+						case 0xA0:	/* plus_loadm_rdsl */
+							slicemode = 1;
+							break;
+						default:
+							break;
+					}
+					break;
+				case 0xA0:	/* plus_cmd_loadr */
+					vpp_r = vpp_data;
+					break;
+				case 0xC0:	/* plus_cmd_loady0 */
+					vpp_y0 = (vpp_data & 0x1f) % 24;
+					break;
+				default:
+					break;
+			}
+			break;
+		default:
+			break;
+	}
+
+	need_update = 1;
+}
+
+
+void vpp_finish_bmp(Byte *vmem, int offx, int offy, int w, int h, int totw, int toth){
+	int i, x, y, t, c, nc, clrx, clry;
+	int tcol[16], m[8] = {0x01, 0x10, 0x04, 0x40, 0x02, 0x20, 0x08, 0x80};
+	Byte *pnt, *pnt2, *pnt3;
+
+	if (vppon) {
+		//memset(colplus,0,BMPW*BMPH);
+		vppon=0;
+	}
+
+	if (TraReg == 0xff) return;
+
+	vppon=1;
+	
+	frame_cnt--;
+	if (frame_cnt<=0) {
+		frame_cnt = 100;
+		blink_st = 1-blink_st;
+		need_update = 1;
+	}
+
+	if (need_update) vpp_update_screen();
+
+	for (i=0; i<8; i++) tcol[i] = tcol[i+8] = !(TraReg & m[i]);
+		
+	if (w > totw-offx) w = totw-offx;
+	if (h > toth-offy) h = toth-offy;
+
+	if (w > vppbmp->w) w = vppbmp->w;
+	if (h > vppbmp->h) h = vppbmp->h;
+	
+	clrx = clry = 0;
+	for (i=0; (!clrx) && (i<totw); i++) if (tcol[vmem[offy*totw+i]&7]) clrx=1;
+	for (i=0; (!clry) && (i<toth); i++) if (tcol[vmem[i*totw+offx]&7]) clry=1;
+	if (clrx) for (y=0; y<offy; y++) for (x=0; x<totw; x++) vmem[y*totw+x]=0;
+	if (clry) for (y=0; y<toth; y++) for (x=0; x<offx; x++) vmem[y*totw+x]=0;
+
+	for (y=0; y<h; y++){
+		pnt = vmem+(offy+y)*totw + offx;
+//		pnt2 = (Byte *)vppbmp->line[y];
+		pnt2 = (Byte *)&vppbmp->line[y*320];
+
+		x=0;
+		while (x < w) {
+			pnt3 = pnt;
+			c = *pnt++;
+			t = x++;
+
+			if ((((x+offx) & 3) == 0) && (sizeof(unsigned long)==4)) {
+				unsigned long cccc, dddd, *p = (unsigned long*) pnt;
+				int t2=x, w2=w-4;
+				cccc = (((unsigned long)c) & 0xff) | ((((unsigned long)c) & 0xff) << 8) | ((((unsigned long)c) & 0xff) << 16) | ((((unsigned long)c) & 0xff) << 24);
+				dddd = *p++;
+				while ((x<w2) && (dddd == cccc)) {
+					x += 4;
+					dddd = *p++;
+				}
+				pnt += x-t2;
+			}
+
+			if (c<16) {
+				if (tcol[c]){
+					if (app_data.openb)
+						for (i=0; i<x-t; i++) *pnt3++ = *pnt2++ & 0xf;
+					else {
+						memcpy(pnt3, pnt2, x-t);
+						pnt2 += x-t;
+					}
+				} else {
+					for (i=0; i<x-t; i++) {
+						nc = *pnt2++;
+						if ((nc & 0x10) && app_data.openb) {
+							*pnt3++ = nc & 0xf;
+						} else if (nc & 8) {
+							//colplus[pnt3++ - vmem] = 0x40;
+						} else {
+							pnt3++;
+						}
+					}
+				}
+			}
+			
+		}
+
+	}
+	
+}
+
+
+static void vpp_draw_char(int x, int y, Byte ch, Byte c0, Byte c1, Byte ext, Byte dw, Byte dh, Byte ul){
+	int xx, yy, d, m, k;
+
+	if ((x>39) || (y>24) || (ext>1)) return;
+
+	d = (dh==2) ? 5 : 0;
+
+	for (yy=0; yy<10; yy++) {
+		if (ul && (d==9))
+			k = 255;
+		else if (ch >= 0xA0)
+			k = dchars[ext][(ch-0xA0)*10 + d];
+		else if (ch >= 0x80)
+			k = 255;
+		else
+			k = vpp_cset[ext][ch * 10 + d];
+
+		m = (dw==2) ? 0x08 : 0x80;
+
+		for (xx=0; xx<8; xx++) {
+			//vppbmp->line[y*10+yy][x*8+xx] = (k & m) ? c1 : c0;
+			vppbmp->line[(y*10+yy)*320+ x*8+xx] = (k & m) ? c1 : c0;
+			if ((xx%2) || (dw==0)) m >>= 1;
+		}
+		if ((yy%2) || (dh==0)) d++;
+	}
+}
+			
+
+static void vpp_update_screen(void){
+	int i,x,y,l,chr,attr,ext,c0,c1,dw,dh,hpar,vpar,lvd,lhd,ser_chr,ser_atr,ul,conc,box;
+	int tlum[8], m[8] = {0x01, 0x10, 0x04, 0x40, 0x02, 0x20, 0x08, 0x80};
+
+	clear(vppbmp);
+
+	for (i=0; i<8; i++) tlum[i] = (LumReg & m[i]) ? 0 : 8;
+
+	vpar = lvd = 0;
+	for (y=0; y<25; y++) {
+
+		vpar = (lvd==0) ? 0 : 1-vpar;
+
+		l = (y==0) ? 31 : (y-1+vpp_y0)%24;
+		c0 = ul = conc = box = 0;
+
+		hpar = lhd = 0;
+		for (x=0; x<40; x++) {
+			hpar = (lhd==0) ? 0 : 1-hpar;
+
+			chr = vpp_mem[x][l][0];
+			attr = vpp_mem[x][l][1];
+			c1 = attr & 0x7;
+			c1 = ((c1&2) | ((c1&1)<<2) | ((c1&4)>>2));
+			ext = (attr & 0x80) ? 1 : 0;
+
+			ser_chr = vpp_mem[x][l][2];
+			ser_atr = vpp_mem[x][l][3];
+			if (ser_chr) {
+				c0 = (ser_atr>>4) & 0x7;
+				c0 = ((c0&2) | ((c0&1)<<2) | ((c0&4)>>2));
+				ul = ser_chr & 4;
+				conc = ser_chr & 1;
+				box = ser_chr & 2;
+			}
+
+			if (ext) {
+				c0 = (attr>>4) & 0x7;
+				c0 = ((c0&2) | ((c0&1)<<2) | ((c0&4)>>2));
+				dw = dh = 0;
+			} else {
+				dw = (attr & 0x20) ? (hpar ? 2 : 1) : 0;
+				dh = (attr & 0x10) ? (vpar ? 2 : 1) : 0;
+				if (dw) lhd=1;
+				if (dh) lvd=1;
+			}
+
+			if ((vpp_r & 0x80) && (!(attr & 8)) && (!blink_st)) c1=c0;
+
+			if (((y == 0) && (vpp_r & 8)) || ((y != 0) && (vpp_r & 1))) {
+				if ((!conc) || (!(vpp_r & 4))) {
+					if (box || (!(vpp_r & 2))) {
+						if ((!ext) && (attr & 0x40))
+							vpp_draw_char(x, y, chr, c1|tlum[c1], c0|tlum[c0], ext, dw, dh, ul);
+						else
+							vpp_draw_char(x, y, chr, c0|tlum[c0], c1|tlum[c1], ext, dw, dh, ul);
+					} else {
+						vpp_draw_char(x, y, 255, (app_data.openb) ? 16 : 0, 0, 0, 0, 0, 0);
+					}
+				}
+			}
+		}
+		
+	}
+
+	if (vpp_r & 0x20) {
+		for (y = vppbmp->h-1; y >= 10; y--)
+//			for (x = 0; x < vppbmp->w; x++) vppbmp->line[y][x] = vppbmp->line[(y-10)/2+10][x];
+			for (x = 0; x < vppbmp->w; x++) vppbmp->line[y*320+x] = vppbmp->line[((y-10)/2+10)*320 + x];
+	}
+
+	need_update=0;
+}
+
+
+void load_colplus(Byte *col){
+	if (vppon) {
+		//memcpy(col,colplus,BMPW*BMPH);
+	}
+	else
+		memset(col,0,BMPW*BMPH);
+}
+
+void init_vpp(void){
+	int i,j,k;
+	
+    vppbmp->w = 320;
+    vppbmp->h = 250;
+
+//	if ((!vppbmp) || (!colplus)) {
+//		fprintf(stderr,"Could not allocate memory for Videopac+ screen buffer.\n");
+//		exit(EXIT_FAILURE);
+//	}
+
+	clear(vppbmp);
+	//memset(colplus,0,BMPW*BMPH);
+
+	LumReg = TraReg = 0xff;
+	vpp_cx = 0;
+	vpp_cy = 0;
+	vpp_y0 = 0;
+	vpp_r = 0;
+	inc_curs = 1;
+	vpp_data = 0;
+	frame_cnt=0;
+	blink_st=0;
+	slice = 0;
+	slicemode=0;
+	need_update = 1;
+	vppon = 1;
+
+	for (i=0; i<2; i++)
+		for (j=0; j<960; j++) dchars[i][j] = 0;
+
+	for (i=0; i<40; i++)
+		for (j=0; j<32; j++)
+			for (k=0; k<4; k++) vpp_mem[i][j][k] = 0;
+}
+
diff --git a/MCUME_pico2/picoo2em/vpp.h b/MCUME_pico2/picoo2em/vpp.h
new file mode 100644
index 0000000..e3f8df6
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vpp.h
@@ -0,0 +1,12 @@
+#ifndef __VPP_H
+#define __VPP_H
+
+Byte read_PB(Byte p);
+void write_PB(Byte p, Byte val);
+Byte vpp_read(ADDRESS adr);
+void vpp_write(Byte dat, ADDRESS adr);
+void vpp_finish_bmp(Byte *vmem, int offx, int offy, int w, int h, int totw, int toth);
+void init_vpp(void);
+void load_colplus(Byte *col);
+
+#endif
diff --git a/MCUME_pico2/picoo2em/vpp_cset.c b/MCUME_pico2/picoo2em/vpp_cset.c
new file mode 100644
index 0000000..0ae7de8
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vpp_cset.c
@@ -0,0 +1,284 @@
+
+/*
+ *   O2EM Freeware Odyssey2 / Videopac+ Emulator
+ *
+ *   Created by Daniel Boris <dboris@comcast.net>  (c) 1997,1998
+ *
+ *   Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
+ *
+ *   http://o2em.sourceforge.net
+ *
+ *
+ *
+ *   Videopac+ character table
+ */
+
+
+#include "types.h"
+#include "vpp_cset.h"
+
+
+const Byte vpp_cset[2][1280] = {
+	{
+	/* Alphanumeric */
+	0x00,0x38,0x44,0x40,0x20,0x10,0x00,0x10,0x00,0x00,
+	0x00,0x10,0x28,0x00,0x38,0x44,0x7c,0x44,0x00,0x00,
+	0x00,0x08,0x10,0x3c,0x20,0x30,0x20,0x3c,0x00,0x00,
+	0x00,0x08,0x14,0x10,0x38,0x10,0x24,0x3c,0x00,0x00,
+	0x00,0x10,0x38,0x50,0x38,0x14,0x54,0x38,0x10,0x00,
+	0x00,0x38,0x44,0x40,0x40,0x40,0x44,0x38,0x10,0x20,
+	0x00,0x28,0x28,0x7c,0x28,0x7c,0x28,0x28,0x00,0x00,
+	0x00,0x20,0x18,0x00,0x38,0x44,0x7c,0x44,0x00,0x00,
+	0x00,0x20,0x18,0x00,0x44,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x10,0x08,0x3c,0x20,0x30,0x20,0x3c,0x00,0x00,
+	0x00,0x3c,0x50,0x50,0x58,0x50,0x50,0x3c,0x00,0x00,
+	0x00,0x08,0x14,0x3c,0x20,0x30,0x20,0x3c,0x00,0x00,
+	0x00,0x00,0x10,0x20,0x7f,0x20,0x10,0x00,0x00,0x00,
+	0x00,0x10,0x38,0x54,0x10,0x10,0x10,0x10,0x10,0x10,
+	0x00,0x00,0x08,0x04,0xfe,0x04,0x08,0x00,0x00,0x00,
+	0x10,0x10,0x10,0x10,0x10,0x10,0x54,0x38,0x10,0x00,
+	0x00,0x18,0x24,0x18,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x10,0x10,0x7c,0x10,0x10,0x00,0x7c,0x00,0x00,
+	0x00,0x08,0x10,0x38,0x44,0x7c,0x40,0x38,0x00,0x00,
+	0x00,0x28,0x00,0x38,0x44,0x7c,0x40,0x38,0x00,0x00,
+	0x00,0x28,0x00,0x30,0x10,0x10,0x10,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x38,0x40,0x40,0x40,0x38,0x10,0x20,
+	0x00,0x10,0x28,0x00,0x44,0x44,0x4c,0x34,0x00,0x00,
+	0x00,0x20,0x10,0x34,0x4c,0x44,0x4c,0x34,0x00,0x00,
+	0x00,0x00,0x10,0x00,0x7c,0x00,0x10,0x00,0x00,0x00,
+	0x00,0x20,0x10,0x38,0x44,0x7c,0x40,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x3c,0x52,0x5e,0x50,0x3e,0x00,0x00,
+	0x00,0x10,0x28,0x38,0x44,0x7c,0x40,0x38,0x00,0x00,
+	0x00,0x40,0xc0,0x40,0x44,0x4c,0x14,0x3e,0x04,0x00,
+	0x00,0x40,0xc0,0x40,0x4c,0x52,0x04,0x08,0x1e,0x00,
+	0x00,0xe0,0x20,0x40,0x24,0xcc,0x14,0x3e,0x04,0x00,
+	0x00,0x10,0x28,0x00,0x38,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,0x00,
+	0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x28,0x00,0x3c,0x20,0x30,0x20,0x3c,0x00,0x00,
+	0x00,0x10,0x28,0x34,0x4c,0x44,0x4c,0x34,0x00,0x00,
+	0x00,0x60,0x64,0x08,0x10,0x20,0x4c,0x0c,0x00,0x00,
+	0x00,0x20,0x50,0x50,0x20,0x54,0x48,0x34,0x00,0x00,
+	0x00,0x10,0x10,0x20,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x08,0x10,0x20,0x20,0x20,0x10,0x08,0x00,0x00,
+	0x00,0x20,0x10,0x08,0x08,0x08,0x10,0x20,0x00,0x00,
+	0x00,0x10,0x54,0x38,0x10,0x38,0x54,0x10,0x00,0x00,
+	0x00,0x00,0x10,0x10,0x7c,0x10,0x10,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x40,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x3c,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,
+	0x01,0x02,0x02,0x04,0x08,0x10,0x20,0x20,0x40,0x80,
+	0x00,0x10,0x28,0x44,0x44,0x44,0x28,0x10,0x00,0x00,
+	0x00,0x10,0x30,0x10,0x10,0x10,0x10,0x10,0x00,0x00,
+	0x00,0x38,0x44,0x04,0x18,0x20,0x40,0x7c,0x00,0x00,
+	0x00,0x7c,0x04,0x08,0x18,0x04,0x44,0x38,0x00,0x00,
+	0x00,0x08,0x18,0x28,0x48,0x7c,0x08,0x08,0x00,0x00,
+	0x00,0x7c,0x40,0x78,0x04,0x04,0x44,0x38,0x00,0x00,
+	0x00,0x18,0x20,0x40,0x78,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x7c,0x04,0x08,0x10,0x20,0x20,0x20,0x00,0x00,
+	0x00,0x38,0x44,0x44,0x38,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x38,0x44,0x44,0x3c,0x04,0x04,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,
+	0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x20,0x40,0x00,
+	0x00,0x04,0x08,0x10,0x20,0x10,0x08,0x04,0x00,0x00,
+	0x00,0x00,0x00,0x7c,0x00,0x7c,0x00,0x00,0x00,0x00,
+	0x00,0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00,0x00,
+	0x00,0x38,0x44,0x04,0x08,0x10,0x00,0x10,0x00,0x00,
+	0x00,0x38,0x44,0x5c,0x54,0x5c,0x40,0x38,0x00,0x00,
+	0x00,0x38,0x44,0x44,0x44,0x7c,0x44,0x44,0x00,0x00,
+	0x00,0x78,0x44,0x44,0x78,0x44,0x44,0x78,0x00,0x00,
+	0x00,0x38,0x44,0x40,0x40,0x40,0x44,0x38,0x00,0x00,
+	0x00,0x78,0x44,0x44,0x44,0x44,0x44,0x78,0x00,0x00,
+	0x00,0x7c,0x40,0x40,0x70,0x40,0x40,0x7c,0x00,0x00,
+	0x00,0x7c,0x40,0x40,0x70,0x40,0x40,0x40,0x00,0x00,
+	0x00,0x38,0x44,0x40,0x40,0x4c,0x44,0x3c,0x00,0x00,
+	0x00,0x44,0x44,0x44,0x7c,0x44,0x44,0x44,0x00,0x00,
+	0x00,0x38,0x10,0x10,0x10,0x10,0x10,0x38,0x00,0x00,
+	0x00,0x1c,0x08,0x08,0x08,0x08,0x48,0x30,0x00,0x00,
+	0x00,0x44,0x48,0x50,0x60,0x50,0x48,0x44,0x00,0x00,
+	0x00,0x40,0x40,0x40,0x40,0x40,0x40,0x7c,0x00,0x00,
+	0x00,0x44,0x6c,0x54,0x44,0x44,0x44,0x44,0x00,0x00,
+	0x00,0x44,0x44,0x64,0x54,0x4c,0x44,0x44,0x00,0x00,
+	0x00,0x38,0x44,0x44,0x44,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x78,0x44,0x44,0x78,0x40,0x40,0x40,0x00,0x00,
+	0x00,0x38,0x44,0x44,0x44,0x54,0x48,0x34,0x00,0x00,
+	0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x00,0x00,
+	0x00,0x38,0x44,0x40,0x38,0x04,0x44,0x38,0x00,0x00,
+	0x00,0x7c,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,
+	0x00,0x44,0x44,0x44,0x44,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x44,0x44,0x44,0x28,0x28,0x10,0x10,0x00,0x00,
+	0x00,0x44,0x44,0x44,0x54,0x54,0x54,0x28,0x00,0x00,
+	0x00,0x44,0x44,0x28,0x10,0x28,0x44,0x44,0x00,0x00,
+	0x00,0x44,0x44,0x28,0x10,0x10,0x10,0x10,0x00,0x00,
+	0x00,0x7c,0x04,0x08,0x10,0x20,0x40,0x7c,0x00,0x00,
+	0x00,0x1c,0x10,0x10,0x10,0x10,0x10,0x1c,0x00,0x00,
+	0x80,0x40,0x40,0x20,0x10,0x08,0x04,0x04,0x02,0x01,
+	0x00,0x38,0x08,0x08,0x08,0x08,0x08,0x38,0x00,0x00,
+	0x00,0x10,0x28,0x00,0x30,0x10,0x10,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,
+	0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x34,0x4c,0x44,0x4c,0x34,0x00,0x00,
+	0x00,0x40,0x40,0x78,0x44,0x44,0x44,0x78,0x00,0x00,
+	0x00,0x00,0x00,0x38,0x40,0x40,0x40,0x38,0x00,0x00,
+	0x00,0x04,0x04,0x3c,0x44,0x44,0x44,0x3c,0x00,0x00,
+	0x00,0x00,0x00,0x38,0x44,0x7c,0x40,0x38,0x00,0x00,
+	0x00,0x18,0x24,0x20,0x70,0x20,0x20,0x20,0x00,0x00,
+	0x00,0x00,0x00,0x3c,0x44,0x44,0x3c,0x04,0x24,0x18,
+	0x00,0x40,0x40,0x58,0x64,0x44,0x44,0x44,0x00,0x00,
+	0x00,0x10,0x00,0x30,0x10,0x10,0x10,0x38,0x00,0x00,
+	0x00,0x08,0x00,0x18,0x08,0x08,0x08,0x08,0x48,0x30,
+	0x00,0x20,0x20,0x24,0x28,0x30,0x28,0x24,0x00,0x00,
+	0x00,0x30,0x10,0x10,0x10,0x10,0x10,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x68,0x54,0x54,0x54,0x54,0x00,0x00,
+	0x00,0x00,0x00,0x58,0x64,0x44,0x44,0x44,0x00,0x00,
+	0x00,0x00,0x00,0x38,0x44,0x44,0x44,0x38,0x00,0x00,
+	0x00,0x00,0x00,0x78,0x44,0x44,0x44,0x78,0x40,0x40,
+	0x00,0x00,0x00,0x3c,0x44,0x44,0x44,0x3c,0x04,0x04,
+	0x00,0x00,0x00,0x58,0x64,0x40,0x40,0x40,0x00,0x00,
+	0x00,0x00,0x00,0x38,0x40,0x38,0x04,0x78,0x00,0x00,
+	0x00,0x20,0x20,0x38,0x20,0x20,0x20,0x18,0x00,0x00,
+	0x00,0x00,0x00,0x44,0x44,0x44,0x4c,0x34,0x00,0x00,
+	0x00,0x00,0x00,0x44,0x44,0x28,0x28,0x10,0x00,0x00,
+	0x00,0x00,0x00,0x44,0x44,0x54,0x54,0x28,0x00,0x00,
+	0x00,0x00,0x00,0x44,0x28,0x10,0x28,0x44,0x00,0x00,
+	0x00,0x00,0x00,0x44,0x44,0x4c,0x34,0x04,0x44,0x38,
+	0x00,0x00,0x00,0x7c,0x08,0x10,0x20,0x7c,0x00,0x00,
+	0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
+	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+	0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+	0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff},
+	{
+	/* Separated semi-graphic */
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x70,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x70,0x70,0x70,0x00,0x00,0x00,0x00,
+	0x70,0x70,0x00,0x70,0x70,0x70,0x00,0x00,0x00,0x00,
+	0x07,0x07,0x00,0x70,0x70,0x70,0x00,0x00,0x00,0x00,
+	0x77,0x77,0x00,0x70,0x70,0x70,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x07,0x07,0x07,0x00,0x00,0x00,0x00,
+	0x70,0x70,0x00,0x07,0x07,0x07,0x00,0x00,0x00,0x00,
+	0x07,0x07,0x00,0x07,0x07,0x07,0x00,0x00,0x00,0x00,
+	0x77,0x77,0x00,0x07,0x07,0x07,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x77,0x77,0x77,0x00,0x00,0x00,0x00,
+	0x70,0x70,0x00,0x77,0x77,0x77,0x00,0x00,0x00,0x00,
+	0x07,0x07,0x00,0x77,0x77,0x77,0x00,0x00,0x00,0x00,
+	0x77,0x77,0x00,0x77,0x77,0x77,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x70,0x00,
+	0x70,0x70,0x00,0x00,0x00,0x00,0x00,0x70,0x70,0x00,
+	0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x70,0x70,0x00,
+	0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x70,0x70,0x00,
+	0x00,0x00,0x00,0x70,0x70,0x70,0x00,0x70,0x70,0x00,
+	0x70,0x70,0x00,0x70,0x70,0x70,0x00,0x70,0x70,0x00,
+	0x07,0x07,0x00,0x70,0x70,0x70,0x00,0x70,0x70,0x00,
+	0x77,0x77,0x00,0x70,0x70,0x70,0x00,0x70,0x70,0x00,
+	0x00,0x00,0x00,0x07,0x07,0x07,0x00,0x70,0x70,0x00,
+	0x70,0x70,0x00,0x07,0x07,0x07,0x00,0x70,0x70,0x00,
+	0x07,0x07,0x00,0x07,0x07,0x07,0x00,0x70,0x70,0x00,
+	0x77,0x77,0x00,0x07,0x07,0x07,0x00,0x70,0x70,0x00,
+	0x00,0x00,0x00,0x77,0x77,0x77,0x00,0x70,0x70,0x00,
+	0x70,0x70,0x00,0x77,0x77,0x77,0x00,0x70,0x70,0x00,
+	0x07,0x07,0x00,0x77,0x77,0x77,0x00,0x70,0x70,0x00,
+	0x77,0x77,0x00,0x77,0x77,0x77,0x00,0x70,0x70,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,
+	0x70,0x70,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,
+	0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,
+	0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,
+	0x00,0x00,0x00,0x70,0x70,0x70,0x00,0x07,0x07,0x00,
+	0x70,0x70,0x00,0x70,0x70,0x70,0x00,0x07,0x07,0x00,
+	0x07,0x07,0x00,0x70,0x70,0x70,0x00,0x07,0x07,0x00,
+	0x77,0x77,0x00,0x70,0x70,0x70,0x00,0x07,0x07,0x00,
+	0x00,0x00,0x00,0x07,0x07,0x07,0x00,0x07,0x07,0x00,
+	0x70,0x70,0x00,0x07,0x07,0x07,0x00,0x07,0x07,0x00,
+	0x07,0x07,0x00,0x07,0x07,0x07,0x00,0x07,0x07,0x00,
+	0x77,0x77,0x00,0x07,0x07,0x07,0x00,0x07,0x07,0x00,
+	0x00,0x00,0x00,0x77,0x77,0x77,0x00,0x07,0x07,0x00,
+	0x70,0x70,0x00,0x77,0x77,0x77,0x00,0x07,0x07,0x00,
+	0x07,0x07,0x00,0x77,0x77,0x77,0x00,0x07,0x07,0x00,
+	0x77,0x77,0x00,0x77,0x77,0x77,0x00,0x07,0x07,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x00,
+	0x70,0x70,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x00,
+	0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x00,
+	0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x00,
+	0x00,0x00,0x00,0x70,0x70,0x70,0x00,0x77,0x77,0x00,
+	0x70,0x70,0x00,0x70,0x70,0x70,0x00,0x77,0x77,0x00,
+	0x07,0x07,0x00,0x70,0x70,0x70,0x00,0x77,0x77,0x00,
+	0x77,0x77,0x00,0x70,0x70,0x70,0x00,0x77,0x77,0x00,
+	0x00,0x00,0x00,0x07,0x07,0x07,0x00,0x77,0x77,0x00,
+	0x70,0x70,0x00,0x07,0x07,0x07,0x00,0x77,0x77,0x00,
+	0x07,0x07,0x00,0x07,0x07,0x07,0x00,0x77,0x77,0x00,
+	0x77,0x77,0x00,0x07,0x07,0x07,0x00,0x77,0x77,0x00,
+	0x00,0x00,0x00,0x77,0x77,0x77,0x00,0x77,0x77,0x00,
+	0x70,0x70,0x00,0x77,0x77,0x77,0x00,0x77,0x77,0x00,
+	0x07,0x07,0x00,0x77,0x77,0x77,0x00,0x77,0x77,0x00,
+	0x77,0x77,0x00,0x77,0x77,0x77,0x00,0x77,0x77,0x00,
+	/* Mosaic semi-graphic */
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x0f,0x0f,0x0f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xf0,0xf0,0xf0,0xf0,0x00,0x00,0x00,
+	0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0x00,0x00,0x00,
+	0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,0xf0,0x00,0x00,0x00,
+	0xff,0xff,0xff,0xf0,0xf0,0xf0,0xf0,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x0f,0x0f,0x0f,0x0f,0x00,0x00,0x00,
+	0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,0x0f,0x00,0x00,0x00,
+	0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x00,0x00,0x00,
+	0xff,0xff,0xff,0x0f,0x0f,0x0f,0x0f,0x00,0x00,0x00,
+	0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+	0xf0,0xf0,0xf0,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+	0x0f,0x0f,0x0f,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0xf0,0xf0,
+	0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0xf0,0xf0,0xf0,
+	0x0f,0x0f,0x0f,0x00,0x00,0x00,0x00,0xf0,0xf0,0xf0,
+	0xff,0xff,0xff,0x00,0x00,0x00,0x00,0xf0,0xf0,0xf0,
+	0x00,0x00,0x00,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,
+	0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,
+	0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,
+	0xff,0xff,0xff,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,
+	0x00,0x00,0x00,0x0f,0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,
+	0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,
+	0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,
+	0xff,0xff,0xff,0x0f,0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,
+	0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xf0,0xf0,0xf0,
+	0xf0,0xf0,0xf0,0xff,0xff,0xff,0xff,0xf0,0xf0,0xf0,
+	0x0f,0x0f,0x0f,0xff,0xff,0xff,0xff,0xf0,0xf0,0xf0,
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0xf0,0xf0,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0f,0x0f,0x0f,
+	0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0x0f,0x0f,0x0f,
+	0x0f,0x0f,0x0f,0x00,0x00,0x00,0x00,0x0f,0x0f,0x0f,
+	0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x0f,0x0f,0x0f,
+	0x00,0x00,0x00,0xf0,0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,
+	0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,
+	0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,
+	0xff,0xff,0xff,0xf0,0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,
+	0x00,0x00,0x00,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
+	0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
+	0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
+	0xff,0xff,0xff,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
+	0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x0f,0x0f,0x0f,
+	0xf0,0xf0,0xf0,0xff,0xff,0xff,0xff,0x0f,0x0f,0x0f,
+	0x0f,0x0f,0x0f,0xff,0xff,0xff,0xff,0x0f,0x0f,0x0f,
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0f,0x0f,0x0f,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,
+	0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0xff,0xff,0xff,
+	0x0f,0x0f,0x0f,0x00,0x00,0x00,0x00,0xff,0xff,0xff,
+	0xff,0xff,0xff,0x00,0x00,0x00,0x00,0xff,0xff,0xff,
+	0x00,0x00,0x00,0xf0,0xf0,0xf0,0xf0,0xff,0xff,0xff,
+	0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0xff,0xff,0xff,
+	0x0f,0x0f,0x0f,0xf0,0xf0,0xf0,0xf0,0xff,0xff,0xff,
+	0xff,0xff,0xff,0xf0,0xf0,0xf0,0xf0,0xff,0xff,0xff,
+	0x00,0x00,0x00,0x0f,0x0f,0x0f,0x0f,0xff,0xff,0xff,
+	0xf0,0xf0,0xf0,0x0f,0x0f,0x0f,0x0f,0xff,0xff,0xff,
+	0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0xff,0xff,0xff,
+	0xff,0xff,0xff,0x0f,0x0f,0x0f,0x0f,0xff,0xff,0xff,
+	0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+	0xf0,0xf0,0xf0,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+	0x0f,0x0f,0x0f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
+};
+
diff --git a/MCUME_pico2/picoo2em/vpp_cset.h b/MCUME_pico2/picoo2em/vpp_cset.h
new file mode 100644
index 0000000..4505177
--- /dev/null
+++ b/MCUME_pico2/picoo2em/vpp_cset.h
@@ -0,0 +1,6 @@
+#ifndef __VPP_CSET_H
+#define __VPP_CSET_H
+
+extern const Byte vpp_cset[2][1280];
+
+#endif
diff --git a/MCUME_pico2/picopce/.DS_Store b/MCUME_pico2/picopce/.DS_Store
new file mode 100644
index 0000000..89b4f55
Binary files /dev/null and b/MCUME_pico2/picopce/.DS_Store differ
diff --git a/MCUME_pico2/picopce/config.h b/MCUME_pico2/picopce/config.h
new file mode 100755
index 0000000..50b9dae
--- /dev/null
+++ b/MCUME_pico2/picopce/config.h
@@ -0,0 +1,11 @@
+// Enable debugging messages (hardware faults, fix-me, etc)
+#define ENABLE_DEBUG           0
+
+// Enable low-level tracing
+#define ENABLE_CPU_TRACING     0
+#define ENABLE_GFX_TRACING     0
+#define ENABLE_SPR_TRACING     0
+#define ENABLE_SND_TRACING     0
+#define ENABLE_IO_TRACING      0
+
+#define USE_MEM_MACROS         0
diff --git a/MCUME_pico2/picopce/emu.cpp b/MCUME_pico2/picopce/emu.cpp
new file mode 100644
index 0000000..4e0ff94
--- /dev/null
+++ b/MCUME_pico2/picopce/emu.cpp
@@ -0,0 +1,88 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+extern "C" {
+#include "pce-go/pce-go.h"
+#include "pce-go/pce.h"
+}
+
+#include "flash_t.h"
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+
+void pce_Init(void)
+{
+  emu_printf("pce_Init");   
+  emu_printf("pce_Init done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void pce_Input(int click) {
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();    
+}
+
+
+void pce_Start(char * filename)
+{
+  emu_printf("pce_Start");
+
+  int size = flash_load(filename);
+  PalettePCE(0);
+  InitPCE(22050, false, (const void *)flash_start, (size_t)size);
+
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND  
+  emu_sndInit();
+#endif  
+#else
+#endif
+
+  emu_printf("pce_Start done");
+}
+
+void pce_Step(void) {
+  RunPCE();
+  uint32_t buttons = 0;
+  if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+    buttons |= JOY_LEFT;
+  }
+  if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+    buttons |= JOY_RIGHT;
+  }
+  if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+    buttons |= JOY_UP;
+  }
+  if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+    buttons |= JOY_DOWN;
+  }  
+  if ( k & MASK_JOY2_BTN) {
+    buttons |= JOY_A;
+  }
+
+  if (k & MASK_KEY_USER3)  buttons |= JOY_B;
+  if (k & MASK_KEY_USER1)  buttons |= JOY_SELECT;
+  if (k & MASK_KEY_USER2)  buttons |= JOY_RUN;
+          
+  PCE.Joypad.regs[0] = buttons; 
+
+  //psg_update((int16_t *) audio_buffer, AUDIO_BUFFER_LENGTH, 0xff);
+  //i2s_dma_write(&i2s_config, (const int16_t *) audio_buffer);
+
+  //emu_DrawVsync();   
+}
+
+void SND_Process(void *stream, int len) {
+//  psg_update((int16*)stream, 0, len);  
+} 
diff --git a/MCUME_pico2/picopce/emu.h b/MCUME_pico2/picopce/emu.h
new file mode 100644
index 0000000..ad56515
--- /dev/null
+++ b/MCUME_pico2/picopce/emu.h
@@ -0,0 +1,5 @@
+extern void pce_Init(void);
+extern void pce_Step(void);
+extern void pce_Start(char * filename);
+extern void pce_Input(int click);
+
diff --git a/MCUME_pico2/picopce/emucfg.h b/MCUME_pico2/picopce/emucfg.h
new file mode 100644
index 0000000..b573c2d
--- /dev/null
+++ b/MCUME_pico2/picopce/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    PC Engine Emulator"
+#define ROMSDIR "pce"
+
+#define emu_Init(ROM) {pce_Init(); pce_Start(ROM);}
+#define emu_Step(x) {pce_Step();}
+#define emu_Input(x) {pce_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picopce/keyboard_osd.h b/MCUME_pico2/picopce/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picopce/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picopce/pce-go/gfx.c b/MCUME_pico2/picopce/pce-go/gfx.c
new file mode 100755
index 0000000..5fd119e
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/gfx.c
@@ -0,0 +1,484 @@
+#pragma GCC optimize("Ofast")
+#include "pico.h"
+#include "pico/runtime.h"
+// gfx.c - VDC/VCE Emulation
+//
+#include <stdlib.h>
+#include <string.h>
+#include "pce.h"
+#include "gfx.h"
+//#include "graphics.h"
+
+#define LOCKED_LINES_MAX 16
+static __aligned(4) uint8_t LOCKED_LINE[XBUF_WIDTH * LOCKED_LINES_MAX] = { 0 };
+static int locked_line = 0;
+
+#define PAL(nibble) (PAL[(L >> ((nibble) * 4)) & 15])
+
+#define V_FLIP  0x8000
+#define H_FLIP  0x0800
+
+static int last_line_counter = 0;
+static int line_counter = 0;
+
+static struct {
+	int scroll_x;
+	int scroll_y;
+	int control;
+	int latched;
+} gfx_context;
+
+static uint8_t *framebuffer_top, *framebuffer_bottom;
+
+/*
+	Draw background tiles between two lines
+*/
+static void __always_inline
+draw_tiles(int Y1, int Y2, int scroll_x, int scroll_y)
+{
+	TRACE_GFX("Rendering tiles on lines %3d - %3d\tScroll: (%3d,%3d)\n", Y1, Y2, scroll_x, scroll_y);
+
+	uint32_t _bg_w[] = { 32, 64, 128, 128 };
+	uint32_t _bg_h[] = { 32, 64 };
+
+	uint32_t bg_w = _bg_w[(IO_VDC_REG[MWR].W >> 4) & 3]; // Bits 5-4 select the width
+	uint32_t bg_h = _bg_h[(IO_VDC_REG[MWR].W >> 6) & 1]; // Bit 6 selects the height
+
+	int num_tiles = IO_VDC_SCREEN_WIDTH / 8 + 1;
+	int x;
+	int y = Y1 + scroll_y;
+	int offset = y & 7;
+	int h = MIN(8 - offset, Y2 - Y1);
+
+	y >>= 3;
+
+	uint8_t *PP = (LOCKED_LINE + XBUF_WIDTH * (Y1 - locked_line)) - (scroll_x & 7);
+
+	for (int line = Y1; line < Y2; y++) {
+		x = scroll_x / 8;
+		y &= bg_h - 1;
+		for (int n = 0; n < num_tiles; n++, x++, PP += 8) {
+			x &= bg_w - 1;
+
+			int no = PCE.VRAM[x + y * bg_w];
+
+			uint8_t *PAL = &PCE.Palette[(no >> 8) & 0x1F0];
+			uint8_t *C = (uint8_t*)(PCE.VRAM + (no & 0x7FF) * 16 + offset);
+			uint8_t *P = PP;
+
+			for (int i = 0; i < h; i++, P += XBUF_WIDTH, C += 2) {
+				uint32_t J, L, M;
+
+				J = C[0] | C[1] | C[16] | C[17];
+
+				if (!J)
+					continue;
+
+				if (P + 8 >= framebuffer_bottom) {
+					MESSAGE_DEBUG("tile overflow!\n");
+					break;
+				} else if (P < framebuffer_top) {
+					MESSAGE_DEBUG("tile underflow!\n");
+					continue;
+				}
+
+				M = C[0];
+				L = ((M & 0x88) >> 3) | ((M & 0x44) << 6) | ((M & 0x22) << 15) | ((M & 0x11) << 24);
+				M = C[1];
+				L |= ((M & 0x88) >> 2) | ((M & 0x44) << 7) | ((M & 0x22) << 16) | ((M & 0x11) << 25);
+				M = C[16];
+				L |= ((M & 0x88) >> 1) | ((M & 0x44) << 8) | ((M & 0x22) << 17) | ((M & 0x11) << 26);
+				M = C[17];
+				L |= ((M & 0x88) >> 0) | ((M & 0x44) << 9) | ((M & 0x22) << 18) | ((M & 0x11) << 27);
+
+				if (J & 0x80) P[0] = PAL(1);
+				if (J & 0x40) P[1] = PAL(3);
+				if (J & 0x20) P[2] = PAL(5);
+				if (J & 0x10) P[3] = PAL(7);
+				if (J & 0x08) P[4] = PAL(0);
+				if (J & 0x04) P[5] = PAL(2);
+				if (J & 0x02) P[6] = PAL(4);
+				if (J & 0x01) P[7] = PAL(6);
+			}
+		}
+		line += h;
+		PP += XBUF_WIDTH * h - num_tiles * 8;
+		offset = 0;
+		h = MIN(8, Y2 - line);
+	}
+}
+
+
+/*
+	Draw sprite C to framebuffer P
+*/
+static void __always_inline
+draw_sprite(uint8_t *P, const uint16_t *C, int height, uint32_t attr)
+{
+	uint8_t *PAL = &PCE.Palette[256 + ((attr & 0xF) << 4)];
+
+	bool hflip = attr & H_FLIP;
+	int inc = 1; //(attr & V_FLIP) ? -1 : 1;
+
+	if (attr & V_FLIP) {
+		inc = -1;
+		C = C + height - 1;
+	}
+
+	for (int i = 0; i < height; i++, C += inc, P += XBUF_WIDTH) {
+
+		uint32_t J = C[0] | C[16] | C[32] | C[48];
+		uint32_t L1, L2, L, M;
+
+		if (!J)
+			continue;
+
+		// This will also need to be handled in draw_sprites... (it could adjust simply constrain the height)
+		if (P + 16 >= framebuffer_bottom) {
+			MESSAGE_DEBUG("sprite overflow %d!\n", i);
+			break;
+		} else if (P < framebuffer_top) {
+			MESSAGE_DEBUG("sprite underflow %d!\n", i);
+			continue;
+		}
+
+		M = C[0];
+		L1 = ((M & 0x88) >> 3) | ((M & 0x44) << 6) | ((M & 0x22) << 15) | ((M & 0x11) << 24);
+		L2 = ((M & 0x8800) >> 11) | ((M & 0x4400) >> 2) | ((M & 0x2200) << 7) | ((M & 0x1100) << 16);
+		M = C[16];
+		L1 |= ((M & 0x88) >> 2) | ((M & 0x44) << 7) | ((M & 0x22) << 16) | ((M & 0x11) << 25);
+		L2 |= ((M & 0x8800) >> 10) | ((M & 0x4400) >> 1) | ((M & 0x2200) << 8) | ((M & 0x1100) << 17);
+		M = C[32];
+		L1 |= ((M & 0x88) >> 1) | ((M & 0x44) << 8) | ((M & 0x22) << 17) | ((M & 0x11) << 26);
+		L2 |= ((M & 0x8800) >> 9) | ((M & 0x4400) >> 0) | ((M & 0x2200) << 9) | ((M & 0x1100) << 18);
+		M = C[48];
+		L1 |= ((M & 0x88) >> 0) | ((M & 0x44) << 9) | ((M & 0x22) << 18) | ((M & 0x11) << 27);
+		L2 |= ((M & 0x8800) >> 8) | ((M & 0x4400) << 1) | ((M & 0x2200) << 10) | ((M & 0x1100) << 19);
+
+		if (hflip) {
+			L = L2;
+			if ((J & 0x8000)) P[15] = PAL(1);
+			if ((J & 0x4000)) P[14] = PAL(3);
+			if ((J & 0x2000)) P[13] = PAL(5);
+			if ((J & 0x1000)) P[12] = PAL(7);
+			if ((J & 0x0800)) P[11] = PAL(0);
+			if ((J & 0x0400)) P[10] = PAL(2);
+			if ((J & 0x0200)) P[9]  = PAL(4);
+			if ((J & 0x0100)) P[8]  = PAL(6);
+
+			L = L1;
+			if ((J & 0x80)) P[7] = PAL(1);
+			if ((J & 0x40)) P[6] = PAL(3);
+			if ((J & 0x20)) P[5] = PAL(5);
+			if ((J & 0x10)) P[4] = PAL(7);
+			if ((J & 0x08)) P[3] = PAL(0);
+			if ((J & 0x04)) P[2] = PAL(2);
+			if ((J & 0x02)) P[1] = PAL(4);
+			if ((J & 0x01)) P[0] = PAL(6);
+		} else {
+			L = L2;
+			if ((J & 0x8000)) P[0] = PAL(1);
+			if ((J & 0x4000)) P[1] = PAL(3);
+			if ((J & 0x2000)) P[2] = PAL(5);
+			if ((J & 0x1000)) P[3] = PAL(7);
+			if ((J & 0x0800)) P[4] = PAL(0);
+			if ((J & 0x0400)) P[5] = PAL(2);
+			if ((J & 0x0200)) P[6] = PAL(4);
+			if ((J & 0x0100)) P[7] = PAL(6);
+
+			L = L1;
+			if ((J & 0x80)) P[8]  = PAL(1);
+			if ((J & 0x40)) P[9]  = PAL(3);
+			if ((J & 0x20)) P[10] = PAL(5);
+			if ((J & 0x10)) P[11] = PAL(7);
+			if ((J & 0x08)) P[12] = PAL(0);
+			if ((J & 0x04)) P[13] = PAL(2);
+			if ((J & 0x02)) P[14] = PAL(4);
+			if ((J & 0x01)) P[15] = PAL(6);
+		}
+	}
+}
+
+
+/*
+	Draw sprites between two lines
+*/
+static void __always_inline // Do not inline
+draw_sprites(int Y1, int Y2, int priority)
+{
+	TRACE_GFX("Rendering sprites on lines %3d - %3d\tPriority: %d\n", Y1, Y2, priority);
+
+	// NOTE: At this time we do not respect bg sprites priority over top sprites.
+	// Example: Assume that sprite #2 is priority=0 and sprite #5 is priority=1. If they
+	// overlap then sprite #5 shouldn't be drawn because #2 > #5. But currently it will.
+
+	// We iterate sprites in reverse order because earlier sprites have
+	// higher priority and therefore must overwrite later sprites.
+
+	for (int n = 63; n >= 0; n--) {
+		const sprite_t *spr = &PCE.SPRAM[n];
+		uint32_t attr = spr->attr;
+
+		if (((attr >> 7) & 1) != priority) {
+			continue;
+		}
+
+		int y = (spr->y & 0x3FF) - 64;
+		int x = (spr->x & 0x3FF) - 32;
+		int cgx = (attr >> 8) & 1;
+		int cgy = (attr >> 12) & 3;
+		int no = (spr->no & 0x7FF);
+
+		cgy |= cgy >> 1;
+
+		no = (no >> 1) & ~(cgy * 2 + cgx);
+		no &= 0x1FF; // PCE has max of 512 sprites
+
+		TRACE_SPR("Sprite 0x%02X : X = %d, Y = %d, attr = %d, no = %d\n", n, x, y, attr, no);
+
+		// Sprite is completely outside our window, skip it
+		if (y >= Y2 || y + (cgy + 1) * 16 < Y1 || x >= IO_VDC_SCREEN_WIDTH || x + (cgx + 1) * 16 < 0) {
+			continue;
+		}
+
+		cgy *= 16;
+
+        int yi = y - locked_line;
+		uint8_t *P = LOCKED_LINE + ((attr & V_FLIP ? cgy + yi : yi) * XBUF_WIDTH) + x;
+		uint16_t *C = PCE.VRAM + (no * 64);
+
+		for (int yy = 0; yy <= cgy; yy += 16) {
+			int height = 16;
+			if (attr & V_FLIP) {
+				height = MIN(16, Y2 - yi - (cgy - yy));
+			} else {
+				int t = Y1 - y - yy;
+				if (t > 0) {
+					P += t * XBUF_WIDTH;
+					C += t;
+					height -= t;
+				}
+				height = MIN(height, Y2 - y - yy);
+			}
+
+			if (height > 0) {
+				for (int j = 0; j <= cgx; j++) {
+					draw_sprite(P + (attr & H_FLIP ? cgx - j : j) * 16, C + j * 64, height, attr);
+				}
+			} else {
+				MESSAGE_DEBUG("negative sprite height!\n");
+			}
+
+			P += ((attr & V_FLIP) ? -height : height) * XBUF_WIDTH;
+			C += height + 16 * 7;
+		}
+	}
+}
+
+
+/*
+	Hit Check Sprite#0 and others
+*/
+static inline bool
+sprite_hit_check(void)
+{
+	const sprite_t *spr = &PCE.SPRAM[0];
+	int x0 = spr->x;
+	int y0 = spr->y;
+	int w0 = (((spr->attr >> 8) & 1) + 1) * 16;
+	int h0 = (((spr->attr >> 12) & 3) + 1) * 16;
+
+	spr++;
+
+	for (int i = 1; i < 64; i++, spr++) {
+		int x = spr->x;
+		int y = spr->y;
+		int w = (((spr->attr >> 8) & 1) + 1) * 16;
+		int h = (((spr->attr >> 12) & 3) + 1) * 16;
+		if ((x < x0 + w0) && (x + w > x0) && (y < y0 + h0) && (y + h > y0))
+			return 1;
+	}
+	return 0;
+}
+
+
+IRAM_ATTR void
+gfx_latch_context(int force)
+{
+	if (!gfx_context.latched || force) { // Context is already saved + we haven't render the line using it
+		gfx_context.scroll_x = IO_VDC_REG[BXR].W;
+		gfx_context.scroll_y = IO_VDC_REG[BYR].W - PCE.ScrollYDiff;
+		gfx_context.control = IO_VDC_REG[CR].W;
+		gfx_context.latched = 1;
+	}
+}
+
+//extern uint8_t SCREEN[];
+extern void emu_DrawLine16(unsigned short *src, int width , int height, int line); 
+extern void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line); 
+/*
+	Render lines into the buffer from min_line to max_line (inclusive)
+*/
+static __always_inline void
+render_line(int ln, int sz) {
+	gfx_context.latched = 0;
+
+    // We must fill the region with color 0 first.
+    memset(LOCKED_LINE, PCE.Palette[0], XBUF_WIDTH * sz);
+    locked_line = ln;
+
+	// Sprites with priority 0 are drawn behind the tiles
+	if (gfx_context.control & 0x40) {
+		draw_sprites(ln, ln + sz, 0);
+	}
+
+	// Draw the background tiles
+	if (gfx_context.control & 0x80) {
+		draw_tiles(ln, ln + sz, gfx_context.scroll_x, gfx_context.scroll_y);
+	}
+
+	// Draw regular sprites
+	if (gfx_context.control & 0x40) {
+		draw_sprites(ln, ln + sz, 1);
+	}
+
+	// we will show this line for the time line is rendering
+	for (int i=0;i<sz;i++)
+		emu_DrawLinePal16(LOCKED_LINE+XBUF_WIDTH*i+16, 256-16, 240, ln+i);
+	//uint8_t * buf = SCREEN + (ln * XBUF_WIDTH);
+	//memcpy(buf, LOCKED_LINE, XBUF_WIDTH * sz);
+}
+
+static __always_inline void
+render_lines(int min_line, int max_line) {
+	for(int ln = min_line; ln < max_line; ln += LOCKED_LINES_MAX) {
+		render_line(ln, max_line - ln > LOCKED_LINES_MAX ? LOCKED_LINES_MAX : max_line - ln);
+	}
+}
+
+int
+gfx_init(void)
+{
+	gfx_reset(true);
+    // Assume 16 columns of scratch area around our buffer.
+    framebuffer_top = LOCKED_LINE;
+    framebuffer_bottom = LOCKED_LINE + XBUF_WIDTH * LOCKED_LINES_MAX;
+	return 0;
+}
+
+
+void
+gfx_reset(bool hard)
+{
+	last_line_counter = 0;
+	line_counter = 0;
+}
+
+
+void
+gfx_term(void)
+{
+	//
+}
+
+
+/*
+	Raises a VDC IRQ and/or process pending VDC IRQs.
+	More than one interrupt can happen in a single line on real hardware and the cpu
+	would usually receive them one by one. We use an uint32 as a 8 slot buffer.
+*/
+void
+gfx_irq(int type)
+{
+	/* If IRQ, push it on the stack */
+	if (type >= 0) {
+		PCE.VDC.pending_irqs <<= 4;
+		PCE.VDC.pending_irqs |= type & 0xF;
+	}
+
+	/* Pop the first pending vdc interrupt only if CPU.irq_lines is clear */
+	int pos = 28;
+	while (!(CPU.irq_lines & INT_IRQ1) && PCE.VDC.pending_irqs) {
+		if (PCE.VDC.pending_irqs >> pos) {
+			PCE.VDC.status |= 1 << (PCE.VDC.pending_irqs >> pos);
+			PCE.VDC.pending_irqs &= ~(0xF << pos);
+			CPU.irq_lines |= INT_IRQ1; // Notify the CPU
+		}
+		pos -= 4;
+	}
+}
+
+
+/*
+	Process one scanline
+*/
+void __time_critical_func(gfx_run)(void)
+{
+	int scanline = PCE.Scanline;
+
+	/* DMA Transfer in "progress" */
+	if (PCE.VDC.satb > DMA_TRANSFER_COUNTER) {
+		if (--PCE.VDC.satb == DMA_TRANSFER_COUNTER) {
+			if (SATBIntON) {
+				gfx_irq(VDC_STAT_DS);
+			}
+		}
+	}
+
+	/* Test raster hit */
+	if (RasHitON) {
+		if (IO_VDC_REG[RCR].W >= 0x40 && (IO_VDC_REG[RCR].W <= 0x146)) {
+			uint16_t temp_rcr = (uint16_t)(IO_VDC_REG[RCR].W - 0x40);
+			if (scanline == (temp_rcr + IO_VDC_MINLINE) % 263) {
+				TRACE_GFX("\n-----------------RASTER HIT (%d)------------------\n", scanline);
+				gfx_irq(VDC_STAT_RR);
+			}
+		}
+	}
+
+	/* Visible area */
+	if (scanline >= 14 && scanline <= 255) {
+		if (scanline == IO_VDC_MINLINE) {
+			gfx_latch_context(1);
+		}
+
+		if (scanline >= IO_VDC_MINLINE && scanline <= IO_VDC_MAXLINE) {
+			if (gfx_context.latched) {
+				render_lines(last_line_counter, line_counter);
+				last_line_counter = line_counter;
+			}
+			line_counter++;
+		}
+	}
+	/* V Blank trigger line */
+	else if (scanline == 256) {
+
+		// Draw any lines left in the context
+		gfx_latch_context(0);
+		render_lines(last_line_counter, line_counter);
+
+		// Trigger interrupts
+		if (SpHitON && sprite_hit_check()) {
+			gfx_irq(VDC_STAT_CR);
+		}
+		if (VBlankON) {
+			gfx_irq(VDC_STAT_VD);
+		}
+
+		/* VRAM to SATB DMA */
+		if (PCE.VDC.satb == DMA_TRANSFER_PENDING || AutoSATBON) {
+			memcpy(PCE.SPRAM, PCE.VRAM + IO_VDC_REG[SATB].W, 512);
+			PCE.VDC.satb = DMA_TRANSFER_COUNTER + 4;
+		}
+	}
+	/* V Blank area */
+	else {
+		gfx_context.latched = 0;
+		last_line_counter = 0;
+		line_counter = 0;
+		PCE.ScrollYDiff = 0;
+	}
+
+	/* Always call at least once (to handle pending IRQs) */
+	gfx_irq(-1);
+}
diff --git a/MCUME_pico2/picopce/pce-go/gfx.h b/MCUME_pico2/picopce/pce-go/gfx.h
new file mode 100755
index 0000000..1d6a5b4
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/gfx.h
@@ -0,0 +1,10 @@
+#pragma once
+
+#include <stdbool.h>
+
+int gfx_init(void);
+void gfx_run(void);
+void gfx_term(void);
+void gfx_irq(int type);
+void gfx_reset(bool hard);
+void gfx_latch_context(int force);
diff --git a/MCUME_pico2/picopce/pce-go/h6280.c b/MCUME_pico2/picopce/pce-go/h6280.c
new file mode 100755
index 0000000..f82c66e
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/h6280.c
@@ -0,0 +1,334 @@
+#pragma GCC optimize("Ofast")
+//  h6280.c - CPU Emulation
+//
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "pce-go.h"
+#include "pce.h"
+
+#define OPCODE(n, f) case n: f; break;
+#define Cycles PCE.Cycles
+
+#include "h6280_instr.h"
+#include "h6280_dbg.h"
+
+
+/**
+ * Reset CPU
+ **/
+void
+h6280_reset(void)
+{
+	CPU.A = CPU.X = CPU.Y = 0x00;
+	CPU.P = (FL_I|FL_B);
+	CPU.S = 0xFF;
+	CPU.PC = pce_read16(VEC_RESET);
+	CPU.irq_mask = CPU.irq_mask_delay = CPU.irq_lines = 0;
+}
+
+
+/**
+ * Log assembler instructions starting at current PC
+ **/
+void
+h6280_debug(void)
+{
+	//
+}
+
+
+/**
+ * Branch into interrupt
+ **/
+void
+h6280_irq(int type)
+{
+	interrupt(type);
+}
+
+
+/**
+ * CPU emulation
+ **/
+void
+h6280_run(int max_cycles)
+{
+	/* Handle active block transfers, ie: do nothing. (tai/tdd/tia/tin/tii) */
+	if (Cycles >= max_cycles) {
+		return;
+	}
+
+	/* Handle pending interrupts (Should be in the loop, but it's too slow) */
+	unsigned irq = CPU.irq_lines & ~CPU.irq_mask & INT_MASK;
+	if ((CPU.P & FL_I) == 0 && irq) {
+		interrupt(irq);
+	}
+
+	/* Run for roughly one scanline */
+	while (Cycles < max_cycles)
+	{
+		UBYTE opcode = imm_operand(CPU.PC);
+
+
+		TRACE_CPU("0x%4X: %s\n", CPU.PC, opcodes[opcode].name);
+
+		switch (opcode)
+		{
+			OPCODE(0x00, brk());				// BRK
+			OPCODE(0x01, ora_zpindx());			// ORA (IND,X)
+			OPCODE(0x02, sxy());				// SXY
+			OPCODE(0x03, st0());				// ST0 #$nn
+			OPCODE(0x04, tsb_zp());				// TSB $ZZ
+			OPCODE(0x05, ora_zp());				// ORA $ZZ
+			OPCODE(0x06, asl_zp());				// ASL $ZZ
+			OPCODE(0x07, rmb(0));				// RMB0 $ZZ
+			OPCODE(0x08, php());				// PHP
+			OPCODE(0x09, ora_imm());			// ORA #$nn
+			OPCODE(0x0A, asl_a());				// ASL A
+			OPCODE(0x0C, tsb_abs());			// TSB $hhll
+			OPCODE(0x0D, ora_abs());			// ORA $hhll
+			OPCODE(0x0E, asl_abs());			// ASL $hhll
+			OPCODE(0x0F, bbr(0));				// BBR0 $ZZ,$rr
+
+			OPCODE(0x10, bpl());				// BPL REL
+			OPCODE(0x11, ora_zpindy());			// ORA (IND),Y
+			OPCODE(0x12, ora_zpind());			// ORA (IND)
+			OPCODE(0x13, st1());				// ST1 #$nn
+			OPCODE(0x14, trb_zp());				// TRB $ZZ
+			OPCODE(0x15, ora_zpx());			// ORA $ZZ,X
+			OPCODE(0x16, asl_zpx());			// ASL $ZZ,X
+			OPCODE(0x17, rmb(1));				// RMB1 $ZZ
+			OPCODE(0x18, clc());				// CLC
+			OPCODE(0x19, ora_absy());			// ORA $hhll,Y
+			OPCODE(0x1A, inc_a());				// INC A
+			OPCODE(0x1C, trb_abs());			// TRB $hhll
+			OPCODE(0x1D, ora_absx());			// ORA $hhll,X
+			OPCODE(0x1E, asl_absx());			// ASL $hhll,X
+			OPCODE(0x1F, bbr(1));				// BBR1 $ZZ,$rr
+
+			OPCODE(0x20, jsr());				// JSR $hhll
+			OPCODE(0x21, and_zpindx());			// AND (IND,X)
+			OPCODE(0x22, sax());				// SAX
+			OPCODE(0x23, st2());				// ST2 #$nn
+			OPCODE(0x24, bit_zp());				// BIT $ZZ
+			OPCODE(0x25, and_zp());				// AND $ZZ
+			OPCODE(0x26, rol_zp());				// ROL $ZZ
+			OPCODE(0x27, rmb(2));				// RMB2 $ZZ
+			OPCODE(0x28, plp());				// PLP
+			OPCODE(0x29, and_imm());			// AND #$nn
+			OPCODE(0x2A, rol_a());				// ROL A
+			OPCODE(0x2C, bit_abs());			// BIT $hhll
+			OPCODE(0x2D, and_abs());			// AND $hhll
+			OPCODE(0x2E, rol_abs());			// ROL $hhll
+			OPCODE(0x2F, bbr(2));				// BBR2 $ZZ,$rr
+
+			OPCODE(0x30, bmi());				// BMI $rr
+			OPCODE(0x31, and_zpindy());			// AND (IND),Y
+			OPCODE(0x32, and_zpind());			// AND (IND)
+			OPCODE(0x34, bit_zpx());			// BIT $ZZ,X
+			OPCODE(0x35, and_zpx());			// AND $ZZ,X
+			OPCODE(0x36, rol_zpx());			// ROL $ZZ,X
+			OPCODE(0x37, rmb(3));				// RMB3 $ZZ
+			OPCODE(0x38, sec());				// SEC
+			OPCODE(0x39, and_absy());			// AND $hhll,Y
+			OPCODE(0x3A, dec_a());				// DEC A
+			OPCODE(0x3C, bit_absx());			// BIT $hhll,X
+			OPCODE(0x3D, and_absx());			// AND $hhll,X
+			OPCODE(0x3E, rol_absx());			// ROL $hhll,X
+			OPCODE(0x3F, bbr(3));				// BBR3 $ZZ,$rr
+
+			OPCODE(0x40, rti());				// RTI
+			OPCODE(0x41, eor_zpindx());			// EOR (IND,X)
+			OPCODE(0x42, say());				// SAY
+			OPCODE(0x43, tma());				// TMAi
+			OPCODE(0x44, bsr());				// BSR $rr
+			OPCODE(0x45, eor_zp());				// EOR $ZZ
+			OPCODE(0x46, lsr_zp());				// LSR $ZZ
+			OPCODE(0x47, rmb(4));				// RMB4 $ZZ
+			OPCODE(0x48, pha());				// PHA
+			OPCODE(0x49, eor_imm());			// EOR #$nn
+			OPCODE(0x4A, lsr_a());				// LSR A
+			OPCODE(0x4C, jmp());				// JMP $hhll
+			OPCODE(0x4D, eor_abs());			// EOR $hhll
+			OPCODE(0x4E, lsr_abs());			// LSR $hhll
+			OPCODE(0x4F, bbr(4));				// BBR4 $ZZ,$rr
+
+			OPCODE(0x50, bvc());				// BVC $rr
+			OPCODE(0x51, eor_zpindy());			// EOR (IND),Y
+			OPCODE(0x52, eor_zpind());			// EOR (IND)
+			OPCODE(0x53, tam());				// TAMi
+			OPCODE(0x54, csl());				// CSL
+			OPCODE(0x55, eor_zpx());			// EOR $ZZ,X
+			OPCODE(0x56, lsr_zpx());			// LSR $ZZ,X
+			OPCODE(0x57, rmb(5));				// RMB5 $ZZ
+			OPCODE(0x58, cli());				// CLI
+			OPCODE(0x59, eor_absy());			// EOR $hhll,Y
+			OPCODE(0x5A, phy());				// PHY
+			OPCODE(0x5D, eor_absx());			// EOR $hhll,X
+			OPCODE(0x5E, lsr_absx());			// LSR $hhll,X
+			OPCODE(0x5F, bbr(5));				// BBR5 $ZZ,$rr
+
+			OPCODE(0x60, rts());				// RTS
+			OPCODE(0x61, adc_zpindx());			// ADC ($ZZ,X)
+			OPCODE(0x62, cla());				// CLA
+			OPCODE(0x64, stz_zp());				// STZ $ZZ
+			OPCODE(0x65, adc_zp());				// ADC $ZZ
+			OPCODE(0x66, ror_zp());				// ROR $ZZ
+			OPCODE(0x67, rmb(6));				// RMB6 $ZZ
+			OPCODE(0x68, pla());				// PLA
+			OPCODE(0x69, adc_imm());			// ADC #$nn
+			OPCODE(0x6A, ror_a());				// ROR A
+			OPCODE(0x6C, jmp_absind());			// JMP ($hhll)
+			OPCODE(0x6D, adc_abs());			// ADC $hhll
+			OPCODE(0x6E, ror_abs());			// ROR $hhll
+			OPCODE(0x6F, bbr(6));				// BBR6 $ZZ,$rr
+
+			OPCODE(0x70, bvs());				// BVS $rr
+			OPCODE(0x71, adc_zpindy());			// ADC ($ZZ),Y
+			OPCODE(0x72, adc_zpind());			// ADC ($ZZ)
+			OPCODE(0x73, tii());				// TII $SHSL,$DHDL,$LHLL
+			OPCODE(0x74, stz_zpx());			// STZ $ZZ,X
+			OPCODE(0x75, adc_zpx());			// ADC $ZZ,X
+			OPCODE(0x76, ror_zpx());			// ROR $ZZ,X
+			OPCODE(0x77, rmb(7));				// RMB7 $ZZ
+			OPCODE(0x78, sei());				// SEI
+			OPCODE(0x79, adc_absy());			// ADC $hhll,Y
+			OPCODE(0x7A, ply());				// PLY
+			OPCODE(0x7C, jmp_absindx())			// JMP $hhll,X
+			OPCODE(0x7D, adc_absx());			// ADC $hhll,X
+			OPCODE(0x7E, ror_absx());			// ROR $hhll,X
+			OPCODE(0x7F, bbr(7));				// BBR7 $ZZ,$rr
+
+			OPCODE(0x80, bra());				// BRA $rr
+			OPCODE(0x81, sta_zpindx());			// STA (IND,X)
+			OPCODE(0x82, clx());				// CLX
+			OPCODE(0x83, tstins_zp());			// TST #$nn,$ZZ
+			OPCODE(0x84, sty_zp());				// STY $ZZ
+			OPCODE(0x85, sta_zp());				// STA $ZZ
+			OPCODE(0x86, stx_zp());				// STX $ZZ
+			OPCODE(0x87, smb(0));				// SMB0 $ZZ
+			OPCODE(0x88, dey());				// DEY
+			OPCODE(0x89, bit_imm());			// BIT #$nn
+			OPCODE(0x8A, txa());				// TXA
+			OPCODE(0x8C, sty_abs());			// STY $hhll
+			OPCODE(0x8D, sta_abs());			// STA $hhll
+			OPCODE(0x8E, stx_abs());			// STX $hhll
+			OPCODE(0x8F, bbs(0));				// BBS0 $ZZ,$rr
+
+			OPCODE(0x90, bcc());				// BCC $rr
+			OPCODE(0x91, sta_zpindy());			// STA (IND),Y
+			OPCODE(0x92, sta_zpind());			// STA (IND)
+			OPCODE(0x93, tstins_abs());			// TST #$nn,$hhll
+			OPCODE(0x94, sty_zpx());			// STY $ZZ,X
+			OPCODE(0x95, sta_zpx());			// STA $ZZ,X
+			OPCODE(0x96, stx_zpy());			// STX $ZZ,Y
+			OPCODE(0x97, smb(1));				// SMB1 $ZZ
+			OPCODE(0x98, tya());				// TYA
+			OPCODE(0x99, sta_absy());			// STA $hhll,Y
+			OPCODE(0x9A, txs());				// TXS
+			OPCODE(0x9C, stz_abs());			// STZ $hhll
+			OPCODE(0x9D, sta_absx());			// STA $hhll,X
+			OPCODE(0x9E, stz_absx());			// STZ $hhll,X
+			OPCODE(0x9F, bbs(1));				// BBS1 $ZZ,$rr
+
+			OPCODE(0xA0, ldy_imm());			// LDY #$nn
+			OPCODE(0xA1, lda_zpindx());			// LDA (IND,X)
+			OPCODE(0xA2, ldx_imm());			// LDX #$nn
+			OPCODE(0xA3, tstins_zpx());			// TST #$nn,$ZZ,X
+			OPCODE(0xA4, ldy_zp());				// LDY $ZZ
+			OPCODE(0xA5, lda_zp());				// LDA $ZZ
+			OPCODE(0xA6, ldx_zp());				// LDX $ZZ
+			OPCODE(0xA7, smb(2));				// SMB2 $ZZ
+			OPCODE(0xA8, tay());				// TAY
+			OPCODE(0xA9, lda_imm());			// LDA #$nn
+			OPCODE(0xAA, tax());				// TAX
+			OPCODE(0xAC, ldy_abs());			// LDY $hhll
+			OPCODE(0xAD, lda_abs());			// LDA $hhll
+			OPCODE(0xAE, ldx_abs());			// LDX $hhll
+			OPCODE(0xAF, bbs(2));				// BBS2 $ZZ,$rr
+
+			OPCODE(0xB0, bcs());				// BCS $rr
+			OPCODE(0xB1, lda_zpindy());			// LDA (IND),Y
+			OPCODE(0xB2, lda_zpind());			// LDA  (IND)
+			OPCODE(0xB3, tstins_absx())			// TST #$nn,$hhll,X
+			OPCODE(0xB4, ldy_zpx());			// LDY $ZZ,X
+			OPCODE(0xB5, lda_zpx());			// LDA $ZZ,X
+			OPCODE(0xB6, ldx_zpy());			// LDX $ZZ,Y
+			OPCODE(0xB7, smb(3));				// SMB3 $ZZ
+			OPCODE(0xB8, clv());				// CLV
+			OPCODE(0xB9, lda_absy());			// LDA $hhll,Y
+			OPCODE(0xBA, tsx());				// TSX
+			OPCODE(0xBC, ldy_absx());			// LDY $hhll,X
+			OPCODE(0xBD, lda_absx());			// LDA $hhll,X
+			OPCODE(0xBE, ldx_absy());			// LDX $hhll,Y
+			OPCODE(0xBF, bbs(3));				// BBS3 $ZZ,$rr
+
+			OPCODE(0xC0, cpy_imm());			// CPY #$nn
+			OPCODE(0xC1, cmp_zpindx());			// CMP (IND,X)
+			OPCODE(0xC2, cly());				// CLY
+			OPCODE(0xC3, tdd());				// TDD $SHSL,$DHDL,$LHLL
+			OPCODE(0xC4, cpy_zp());				// CPY $ZZ
+			OPCODE(0xC5, cmp_zp());				// CMP $ZZ
+			OPCODE(0xC6, dec_zp());				// DEC $ZZ
+			OPCODE(0xC7, smb(4));				// SMB4 $ZZ
+			OPCODE(0xC8, iny());				// INY
+			OPCODE(0xC9, cmp_imm());			// CMP #$nn
+			OPCODE(0xCA, dex());				// DEX
+			OPCODE(0xCC, cpy_abs());			// CPY $hhll
+			OPCODE(0xCD, cmp_abs());			// CMP $hhll
+			OPCODE(0xCE, dec_abs());			// DEC $hhll
+			OPCODE(0xCF, bbs(4));				// BBS4 $ZZ,$rr
+
+			OPCODE(0xD0, bne());				// BNE $rr
+			OPCODE(0xD1, cmp_zpindy());			// CMP (IND),Y
+			OPCODE(0xD2, cmp_zpind());			// CMP (IND)
+			OPCODE(0xD3, tin());				// TIN $SHSL,$DHDL,$LHLL
+			OPCODE(0xD4, csh());				// CSH
+			OPCODE(0xD5, cmp_zpx());			// CMP $ZZ,X
+			OPCODE(0xD6, dec_zpx());			// DEC $ZZ,X
+			OPCODE(0xD7, smb(5));				// SMB5 $ZZ
+			OPCODE(0xD8, cld());				// CLD
+			OPCODE(0xD9, cmp_absy());			// CMP $hhll,Y
+			OPCODE(0xDA, phx());				// PHX
+			OPCODE(0xDD, cmp_absx());			// CMP $hhll,X
+			OPCODE(0xDE, dec_absx());			// DEC $hhll,X
+			OPCODE(0xDF, bbs(5));				// BBS5 $ZZ,$rr
+
+			OPCODE(0xE0, cpx_imm());			// CPX #$nn
+			OPCODE(0xE1, sbc_zpindx());			// SBC (IND,X)
+			OPCODE(0xE3, tia());				// TIA $SHSL,$DHDL,$LHLL
+			OPCODE(0xE4, cpx_zp());				// CPX $ZZ
+			OPCODE(0xE5, sbc_zp());				// SBC $ZZ
+			OPCODE(0xE6, inc_zp());				// INC $ZZ
+			OPCODE(0xE7, smb(6));				// SMB6 $ZZ
+			OPCODE(0xE8, inx());				// INX
+			OPCODE(0xE9, sbc_imm());			// SBC #$nn
+			OPCODE(0xEA, nop());				// NOP
+			OPCODE(0xEC, cpx_abs());			// CPX $hhll
+			OPCODE(0xED, sbc_abs());			// SBC $hhll
+			OPCODE(0xEE, inc_abs());			// INC $hhll
+			OPCODE(0xEF, bbs(6));				// BBS6 $ZZ,$rr
+			OPCODE(0xF0, beq());				// BEQ $rr
+
+			OPCODE(0xF1, sbc_zpindy());			// SBC (IND),Y
+			OPCODE(0xF2, sbc_zpind());			// SBC (IND)
+			OPCODE(0xF3, tai());				// TAI $SHSL,$DHDL,$LHLL
+			OPCODE(0xF4, set());				// SET
+			OPCODE(0xF5, sbc_zpx());			// SBC $ZZ,X
+			OPCODE(0xF6, inc_zpx());			// INC $ZZ,X
+			OPCODE(0xF7, smb(7));				// SMB7 $ZZ
+			OPCODE(0xF8, sed());				// SED
+			OPCODE(0xF9, sbc_absy());			// SBC $hhll,Y
+			OPCODE(0xFA, plx());				// PLX
+			OPCODE(0xFD, sbc_absx());			// SBC $hhll,X
+			OPCODE(0xFE, inc_absx());			// INC $hhll,X
+			OPCODE(0xFF, bbs(7));				// BBS7 $ZZ,$rr
+
+			default:
+				// Illegal opcodes are treated as NOP
+				MESSAGE_DEBUG("Illegal opcode 0x%02X at pc=0x%04X!\n", opcode, CPU.PC);
+				nop();
+		}
+	}
+}
diff --git a/MCUME_pico2/picopce/pce-go/h6280.h b/MCUME_pico2/picopce/pce-go/h6280.h
new file mode 100755
index 0000000..ab4eee8
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/h6280.h
@@ -0,0 +1,53 @@
+#pragma once
+
+#include <stdint.h>
+
+void h6280_reset(void);
+void h6280_run(int cycles);
+void h6280_irq(int);
+void h6280_dump_state(void);
+void h6280_disassemble(void);
+
+typedef struct
+{
+	/* Registers */
+	uint16_t PC;
+	uint8_t A;
+	uint8_t X;
+	uint8_t Y;
+	uint8_t P;
+	uint8_t S;
+
+	/* Interrupts */
+	uint8_t irq_mask;
+	uint8_t irq_mask_delay;
+	uint8_t irq_lines;
+
+	/* Misc */
+	uint32_t cycles;
+	uint32_t halted;
+} h6280_t;
+
+// CPU Flags:
+#define FL_N       0x80
+#define FL_V       0x40
+#define FL_T       0x20
+#define FL_B       0x10
+#define FL_D       0x08
+#define FL_I       0x04
+#define FL_Z       0x02
+#define FL_C       0x01
+
+// Interrupts
+#define INT_IRQ2   0x01
+#define INT_IRQ1   0x02
+#define INT_TIMER  0x04
+#define INT_MASK   0x07
+
+// Vectors
+#define VEC_RESET  0xFFFE
+#define VEC_NMI    0xFFFC
+#define VEC_TIMER  0xFFFA
+#define VEC_IRQ1   0xFFF8
+#define VEC_IRQ2   0xFFF6
+#define VEC_BRK    0xFFF6
diff --git a/MCUME_pico2/picopce/pce-go/h6280_dbg.h b/MCUME_pico2/picopce/pce-go/h6280_dbg.h
new file mode 100755
index 0000000..887deb7
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/h6280_dbg.h
@@ -0,0 +1,329 @@
+#include "h6280.h"
+#include "pce.h"
+
+// Addressing modes
+#define AM_IMPL      0			/* implicit              */
+#define AM_IMMED     1			/* immediate             */
+#define AM_REL       2			/* relative              */
+#define AM_ZP        3			/* zero page             */
+#define AM_ZPX       4			/* zero page, x          */
+#define AM_ZPY       5			/* zero page, y          */
+#define AM_ZPIND     6			/* zero page indirect    */
+#define AM_ZPINDX    7			/* zero page indirect, x */
+#define AM_ZPINDY    8			/* zero page indirect, y */
+#define AM_ABS       9			/* absolute              */
+#define AM_ABSX     10			/* absolute, x           */
+#define AM_ABSY     11			/* absolute, y           */
+#define AM_ABSIND   12			/* absolute indirect     */
+#define AM_ABSINDX  13			/* absolute indirect     */
+#define AM_PSREL    14			/* pseudo-relative       */
+#define AM_TST_ZP   15			/* special 'TST' addressing mode  */
+#define AM_TST_ABS  16			/* special 'TST' addressing mode  */
+#define AM_TST_ZPX  17			/* special 'TST' addressing mode  */
+#define AM_TST_ABSX 18			/* special 'TST' addressing mode  */
+#define AM_XFER     19			/* special 7-byte transfer addressing mode  */
+
+// OpCodes
+static const struct
+{
+	uint32_t addr_mode;
+	const char name[6];
+} opcodes[0x100] = {
+	{AM_IMMED, "BRK"},		/* $00 */
+	{AM_ZPINDX, "ORA"},		/* $01 */
+	{AM_IMPL, "SXY"},		/* $02 */
+	{AM_IMMED, "ST0"},		/* $03 */
+	{AM_ZP, "TSB"},			/* $04 */
+	{AM_ZP, "ORA"},			/* $05 */
+	{AM_ZP, "ASL"},			/* $06 */
+	{AM_ZP, "RMB0"},		/* $07 */
+	{AM_IMPL, "PHP"},		/* $08 */
+	{AM_IMMED, "ORA"},		/* $09 */
+	{AM_IMPL, "ASL"},		/* $0A */
+	{AM_IMPL, "BP0"},		/* $0B */
+	{AM_ABS, "TSB"},		/* $0C */
+	{AM_ABS, "ORA"},		/* $0D */
+	{AM_ABS, "ASL"},		/* $0E */
+	{AM_PSREL, "BBR0"},		/* $0F */
+	{AM_REL, "BPL"},		/* $10 */
+	{AM_ZPINDY, "ORA"},		/* $11 */
+	{AM_ZPIND, "ORA"},		/* $12 */
+	{AM_IMMED, "ST1"},		/* $13 */
+	{AM_ZP, "TRB"},			/* $14 */
+	{AM_ZPX, "ORA"},		/* $15 */
+	{AM_ZPX, "ASL"},		/* $16 */
+	{AM_ZP, "RMB1"},		/* $17 */
+	{AM_IMPL, "CLC"},		/* $18 */
+	{AM_ABSY, "ORA"},		/* $19 */
+	{AM_IMPL, "INC"},		/* $1A */
+	{AM_IMPL, "BP1"},		/* $1B */
+	{AM_ABS, "TRB"},		/* $1C */
+	{AM_ABSX, "ORA"},		/* $1D */
+	{AM_ABSX, "ASL"},		/* $1E */
+	{AM_PSREL, "BBR1"},		/* $1F */
+	{AM_ABS, "JSR"},		/* $20 */
+	{AM_ZPINDX, "AND"},		/* $21 */
+	{AM_IMPL, "SAX"},		/* $22 */
+	{AM_IMMED, "ST2"},		/* $23 */
+	{AM_ZP, "BIT"},			/* $24 */
+	{AM_ZP, "AND"},			/* $25 */
+	{AM_ZP, "ROL"},			/* $26 */
+	{AM_ZP, "RMB2"},		/* $27 */
+	{AM_IMPL, "PLP"},		/* $28 */
+	{AM_IMMED, "AND"},		/* $29 */
+	{AM_IMPL, "ROL"},		/* $2A */
+	{AM_IMPL, "BP2"},		/* $2B */
+	{AM_ABS, "BIT"},		/* $2C */
+	{AM_ABS, "AND"},		/* $2D */
+	{AM_ABS, "ROL"},		/* $2E */
+	{AM_PSREL, "BBR2"},		/* $2F */
+	{AM_REL, "BMI"},		/* $30 */
+	{AM_ZPINDY, "AND"},		/* $31 */
+	{AM_ZPIND, "AND"},		/* $32 */
+	{AM_IMPL, "???"},		/* $33 */
+	{AM_ZPX, "BIT"},		/* $34 */
+	{AM_ZPX, "AND"},		/* $35 */
+	{AM_ZPX, "ROL"},		/* $36 */
+	{AM_ZP, "RMB3"},		/* $37 */
+	{AM_IMPL, "SEC"},		/* $38 */
+	{AM_ABSY, "AND"},		/* $39 */
+	{AM_IMPL, "DEC"},		/* $3A */
+	{AM_IMPL, "BP3"},		/* $3B */
+	{AM_ABSX, "BIT"},		/* $3C */
+	{AM_ABSX, "AND"},		/* $3D */
+	{AM_ABSX, "ROL"},		/* $3E */
+	{AM_PSREL, "BBR3"},		/* $3F */
+	{AM_IMPL, "RTI"},		/* $40 */
+	{AM_ZPINDX, "EOR"},		/* $41 */
+	{AM_IMPL, "SAY"},		/* $42 */
+	{AM_IMMED, "TMA"},		/* $43 */
+	{AM_REL, "BSR"},		/* $44 */
+	{AM_ZP, "EOR"},			/* $45 */
+	{AM_ZP, "LSR"},			/* $46 */
+	{AM_ZP, "RMB4"},		/* $47 */
+	{AM_IMPL, "PHA"},		/* $48 */
+	{AM_IMMED, "EOR"},		/* $49 */
+	{AM_IMPL, "LSR"},		/* $4A */
+	{AM_IMPL, "BP4"},		/* $4B */
+	{AM_ABS, "JMP"},		/* $4C */
+	{AM_ABS, "EOR"},		/* $4D */
+	{AM_ABS, "LSR"},		/* $4E */
+	{AM_PSREL, "BBR4"},		/* $4F */
+	{AM_REL, "BVC"},		/* $50 */
+	{AM_ZPINDY, "EOR"},		/* $51 */
+	{AM_ZPIND, "EOR"},		/* $52 */
+	{AM_IMMED, "TAM"},		/* $53 */
+	{AM_IMPL, "CSL"},		/* $54 */
+	{AM_ZPX, "EOR"},		/* $55 */
+	{AM_ZPX, "LSR"},		/* $56 */
+	{AM_ZP, "RMB5"},		/* $57 */
+	{AM_IMPL, "CLI"},		/* $58 */
+	{AM_ABSY, "EOR"},		/* $59 */
+	{AM_IMPL, "PHY"},		/* $5A */
+	{AM_IMPL, "BP5"},		/* $5B */
+	{AM_IMPL, "???"},		/* $5C */
+	{AM_ABSX, "EOR"},		/* $5D */
+	{AM_ABSX, "LSR"},		/* $5E */
+	{AM_PSREL, "BBR5"},		/* $5F */
+	{AM_IMPL, "RTS"},		/* $60 */
+	{AM_ZPINDX, "ADC"},		/* $61 */
+	{AM_IMPL, "CLA"},		/* $62 */
+	{AM_IMPL, "???"},		/* $63 */
+	{AM_ZP, "STZ"},			/* $64 */
+	{AM_ZP, "ADC"},			/* $65 */
+	{AM_ZP, "ROR"},			/* $66 */
+	{AM_ZP, "RMB6"},		/* $67 */
+	{AM_IMPL, "PLA"},		/* $68 */
+	{AM_IMMED, "ADC"},		/* $69 */
+	{AM_IMPL, "ROR"},		/* $6A */
+	{AM_IMPL, "BP6"},		/* $6B */
+	{AM_ABSIND, "JMP"},		/* $6C */
+	{AM_ABS, "ADC"},		/* $6D */
+	{AM_ABS, "ROR"},		/* $6E */
+	{AM_PSREL, "BBR6"},		/* $6F */
+	{AM_REL, "BVS"},		/* $70 */
+	{AM_ZPINDY, "ADC"},		/* $71 */
+	{AM_ZPIND, "ADC"},		/* $72 */
+	{AM_XFER, "TII"},		/* $73 */
+	{AM_ZPX, "STZ"},		/* $74 */
+	{AM_ZPX, "ADC"},		/* $75 */
+	{AM_ZPX, "ROR"},		/* $76 */
+	{AM_ZP, "RMB7"},		/* $77 */
+	{AM_IMPL, "SEI"},		/* $78 */
+	{AM_ABSY, "ADC"},		/* $79 */
+	{AM_IMPL, "PLY"},		/* $7A */
+	{AM_IMPL, "BP7"},		/* $7B */
+	{AM_ABSINDX, "JMP"},	/* $7C */
+	{AM_ABSX, "ADC"},		/* $7D */
+	{AM_ABSX, "ROR"},		/* $7E */
+	{AM_PSREL, "BBR7"},		/* $7F */
+	{AM_REL, "BRA"},		/* $80 */
+	{AM_ZPINDX, "STA"},		/* $81 */
+	{AM_IMPL, "CLX"},		/* $82 */
+	{AM_TST_ZP, "TST"},		/* $83 */
+	{AM_ZP, "STY"},			/* $84 */
+	{AM_ZP, "STA"},			/* $85 */
+	{AM_ZP, "STX"},			/* $86 */
+	{AM_ZP, "SMB0"},		/* $87 */
+	{AM_IMPL, "DEY"},		/* $88 */
+	{AM_IMMED, "BIT"},		/* $89 */
+	{AM_IMPL, "TXA"},		/* $8A */
+	{AM_IMPL, "BP8"},		/* $8B */
+	{AM_ABS, "STY"},		/* $8C */
+	{AM_ABS, "STA"},		/* $8D */
+	{AM_ABS, "STX"},		/* $8E */
+	{AM_PSREL, "BBS0"},		/* $8F */
+	{AM_REL, "BCC"},		/* $90 */
+	{AM_ZPINDY, "STA"},		/* $91 */
+	{AM_ZPIND, "STA"},		/* $92 */
+	{AM_TST_ABS, "TST"},	/* $93 */
+	{AM_ZPX, "STY"},		/* $94 */
+	{AM_ZPX, "STA"},		/* $95 */
+	{AM_ZPY, "STX"},		/* $96 */
+	{AM_ZP, "SMB1"},		/* $97 */
+	{AM_IMPL, "TYA"},		/* $98 */
+	{AM_ABSY, "STA"},		/* $99 */
+	{AM_IMPL, "TXS"},		/* $9A */
+	{AM_IMPL, "BP9"},		/* $9B */
+	{AM_ABS, "STZ"},		/* $9C */
+	{AM_ABSX, "STA"},		/* $9D */
+	{AM_ABSX, "STZ"},		/* $9E */
+	{AM_PSREL, "BBS1"},		/* $9F */
+	{AM_IMMED, "LDY"},		/* $A0 */
+	{AM_ZPINDX, "LDA"},		/* $A1 */
+	{AM_IMMED, "LDX"},		/* $A2 */
+	{AM_TST_ZPX, "TST"},	/* $A3 */
+	{AM_ZP, "LDY"},			/* $A4 */
+	{AM_ZP, "LDA"},			/* $A5 */
+	{AM_ZP, "LDX"},			/* $A6 */
+	{AM_ZP, "SMB2"},		/* $A7 */
+	{AM_IMPL, "TAY"},		/* $A8 */
+	{AM_IMMED, "LDA"},		/* $A9 */
+	{AM_IMPL, "TAX"},		/* $AA */
+	{AM_IMPL, "BPA"},		/* $AB */
+	{AM_ABS, "LDY"},		/* $AC */
+	{AM_ABS, "LDA"},		/* $AD */
+	{AM_ABS, "LDX"},		/* $AE */
+	{AM_PSREL, "BBS2"},		/* $AF */
+	{AM_REL, "BCS"},		/* $B0 */
+	{AM_ZPINDY, "LDA"},		/* $B1 */
+	{AM_ZPIND, "LDA"},		/* $B2 */
+	{AM_TST_ABSX, "TST"},	/* $B3 */
+	{AM_ZPX, "LDY"},		/* $B4 */
+	{AM_ZPX, "LDA"},		/* $B5 */
+	{AM_ZPY, "LDX"},		/* $B6 */
+	{AM_ZP, "SMB3"},		/* $B7 */
+	{AM_IMPL, "CLV"},		/* $B8 */
+	{AM_ABSY, "LDA"},		/* $B9 */
+	{AM_IMPL, "TSX"},		/* $BA */
+	{AM_IMPL, "BPB"},		/* $BB */
+	{AM_ABSX, "LDY"},		/* $BC */
+	{AM_ABSX, "LDA"},		/* $BD */
+	{AM_ABSY, "LDX"},		/* $BE */
+	{AM_PSREL, "BBS3"},		/* $BF */
+	{AM_IMMED, "CPY"},		/* $C0 */
+	{AM_ZPINDX, "CMP"},		/* $C1 */
+	{AM_IMPL, "CLY"},		/* $C2 */
+	{AM_XFER, "TDD"},		/* $C3 */
+	{AM_ZP, "CPY"},			/* $C4 */
+	{AM_ZP, "CMP"},			/* $C5 */
+	{AM_ZP, "DEC"},			/* $C6 */
+	{AM_ZP, "SMB4"},		/* $C7 */
+	{AM_IMPL, "INY"},		/* $C8 */
+	{AM_IMMED, "CMP"},		/* $C9 */
+	{AM_IMPL, "DEX"},		/* $CA */
+	{AM_IMPL, "BPC"},		/* $CB */
+	{AM_ABS, "CPY"},		/* $CC */
+	{AM_ABS, "CMP"},		/* $CD */
+	{AM_ABS, "DEC"},		/* $CE */
+	{AM_PSREL, "BBS4"},		/* $CF */
+	{AM_REL, "BNE"},		/* $D0 */
+	{AM_ZPINDY, "CMP"},		/* $D1 */
+	{AM_ZPIND, "CMP"},		/* $D2 */
+	{AM_XFER, "TIN"},		/* $D3 */
+	{AM_IMPL, "CSH"},		/* $D4 */
+	{AM_ZPX, "CMP"},		/* $D5 */
+	{AM_ZPX, "DEC"},		/* $D6 */
+	{AM_ZP, "SMB5"},		/* $D7 */
+	{AM_IMPL, "CLD"},		/* $D8 */
+	{AM_ABSY, "CMP"},		/* $D9 */
+	{AM_IMPL, "PHX"},		/* $DA */
+	{AM_IMPL, "BPD"},		/* $DB */
+	{AM_IMPL, "???"},		/* $DC */
+	{AM_ABSX, "CMP"},		/* $DD */
+	{AM_ABSX, "DEC"},		/* $DE */
+	{AM_PSREL, "BBS5"},		/* $DF */
+	{AM_IMMED, "CPX"},		/* $E0 */
+	{AM_ZPINDX, "SBC"},		/* $E1 */
+	{AM_IMPL, "???"},		/* $E2 */
+	{AM_XFER, "TIA"},		/* $E3 */
+	{AM_ZP, "CPX"},			/* $E4 */
+	{AM_ZP, "SBC"},			/* $E5 */
+	{AM_ZP, "INC"},			/* $E6 */
+	{AM_ZP, "SMB6"},		/* $E7 */
+	{AM_IMPL, "INX"},		/* $E8 */
+	{AM_IMMED, "SBC"},		/* $E9 */
+	{AM_IMPL, "NOP"},		/* $EA */
+	{AM_IMPL, "BPE"},		/* $EB */
+	{AM_ABS, "CPX"},		/* $EC */
+	{AM_ABS, "SBC"},		/* $ED */
+	{AM_ABS, "INC"},		/* $EE */
+	{AM_PSREL, "BBS6"},		/* $EF */
+	{AM_REL, "BEQ"},		/* $F0 */
+	{AM_ZPINDY, "SBC"},		/* $F1 */
+	{AM_ZPIND, "SBC"},		/* $F2 */
+	{AM_XFER, "TAI"},		/* $F3 */
+	{AM_IMPL, "SET"},		/* $F4 */
+	{AM_ZPX, "SBC"},		/* $F5 */
+	{AM_ZPX, "INC"},		/* $F6 */
+	{AM_ZP, "SMB7"},		/* $F7 */
+	{AM_IMPL, "SED"},		/* $F8 */
+	{AM_ABSY, "SBC"},		/* $F9 */
+	{AM_IMPL, "PLX"},		/* $FA */
+	{AM_IMPL, "BPF"},		/* $FB */
+	{AM_IMPL, "???"},		/* $FC */
+	{AM_ABSX, "SBC"},		/* $FD */
+	{AM_ABSX, "INC"},		/* $FE */
+	{AM_PSREL, "BBS7"}		/* $FF */
+};
+
+
+void h6280_dump_state(void)
+{
+	MESSAGE_INFO("Current h6280 status:\n");
+
+	MESSAGE_INFO("PC = 0x%04x\n", CPU.PC);
+	MESSAGE_INFO("A = 0x%02x\n", CPU.A);
+	MESSAGE_INFO("X = 0x%02x\n", CPU.X);
+	MESSAGE_INFO("Y = 0x%02x\n", CPU.Y);
+	MESSAGE_INFO("P = 0x%02x\n", CPU.P);
+	MESSAGE_INFO("S = 0x%02x\n", CPU.S);
+
+	for (int i = 0; i < 8; i++) {
+		MESSAGE_INFO("MMR[%d] = 0x%02x\n", i, PCE.MMR[i]);
+	}
+
+	// TODO: Add zero page dump
+
+	for (int i = 0x2000; i < 0xFFFF; i++) {
+
+		if ((i & 0xF) == 0) {
+			MESSAGE_INFO("%04X: ", i);
+		}
+
+		MESSAGE_INFO("%02x ", pce_read8(i));
+		if ((i & 0xF) == 0xF) {
+			MESSAGE_INFO("\n");
+		}
+		if ((i & 0x1FFF) == 0x1FFF) {
+			MESSAGE_INFO("\n-------------------------------------------------------------\n");
+		}
+	}
+}
+
+
+// Disassemble one instruction at PC
+void h6280_disassemble(void)
+{
+
+}
diff --git a/MCUME_pico2/picopce/pce-go/h6280_instr.h b/MCUME_pico2/picopce/pce-go/h6280_instr.h
new file mode 100755
index 0000000..f9b911b
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/h6280_instr.h
@@ -0,0 +1,2457 @@
+#include "h6280.h"
+
+typedef signed char SBYTE;
+typedef unsigned char UBYTE;
+typedef signed short SWORD;
+typedef unsigned short UWORD;
+
+static const UBYTE bin2bcd[0x100] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19,
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29,
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99,
+};
+
+static const UBYTE bcd2bin[0x100] = {
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0, 0, 0, 0, 0, 0,
+	0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0, 0, 0, 0, 0, 0,
+	0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0, 0, 0, 0, 0, 0,
+	0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0, 0, 0, 0, 0, 0,
+	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0, 0, 0, 0, 0, 0,
+	0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0, 0, 0, 0, 0, 0,
+	0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0, 0, 0, 0, 0, 0,
+	0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0, 0, 0, 0, 0, 0,
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0, 0, 0, 0, 0, 0,
+	0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0, 0, 0, 0, 0, 0,
+};
+
+#define ALWAYS_INLINE inline __attribute__((__always_inline__))
+#define OPCODE_FUNC static ALWAYS_INLINE void
+
+// Lucky for us FL_N is at the 7th bit position so we can save a comparison :)
+#define FLAG_NZ(val) ((val) == 0 ? FL_Z : ((val) & FL_N))
+
+// pointer to the beginning of the Zero Page area
+#define ZP_BASE (PCE.RAM)
+
+// pointer to the beginning of the Stack Area
+#define SP_BASE (PCE.RAM + 0x100)
+
+// Addressing modes:
+#define imm_operand(addr)  ({uint32_t a = (addr); PageR[a >> 13][a];})
+#define abs_operand(x)     pce_read8(pce_read16(x))
+#define absx_operand(x)    pce_read8(pce_read16(x)+CPU.X)
+#define absy_operand(x)    pce_read8(pce_read16(x)+CPU.Y)
+#define zp_operand(x)      get_8bit_zp(imm_operand(x))
+#define zpx_operand(x)     get_8bit_zp(imm_operand(x)+CPU.X)
+#define zpy_operand(x)     get_8bit_zp(imm_operand(x)+CPU.Y)
+#define zpind_operand(x)   pce_read8(get_16bit_zp(imm_operand(x)))
+#define zpindx_operand(x)  pce_read8(get_16bit_zp(imm_operand(x)+CPU.X))
+#define zpindy_operand(x)  pce_read8(get_16bit_zp(imm_operand(x))+CPU.Y)
+
+// Flag check (flags 'N' and 'Z'):
+#define chk_flnz_8bit(x) CPU.P = ((CPU.P & (~(FL_N|FL_T|FL_Z))) | FLAG_NZ(x));
+
+// Zero page access
+#define get_8bit_zp(zp_addr) ZP_BASE[(zp_addr) & 0xFF]
+#define get_16bit_zp(zp_addr) ({UBYTE x = zp_addr; get_8bit_zp(x) | get_8bit_zp(x + 1) << 8;})
+#define put_8bit_zp(zp_addr, byte) ZP_BASE[(zp_addr) & 0xFF] = (byte)
+
+// Stack access
+#define push_8bit(byte) ({*(SP_BASE + CPU.S) = (byte); CPU.S--;})
+#define push_16bit(addr) ({UWORD x = addr; push_8bit(x >> 8); push_8bit(x & 0xFF);})
+//#define pull_8bit() (*(SP_BASE + ++CPU.S))
+#define pull_8bit(x) ({ ++CPU.S; x = *(SP_BASE + CPU.S);})
+//#define pull_16bit() (pull_8bit() | pull_8bit() << 8)
+
+//
+// Implementation of actual opcodes:
+//
+
+static inline UBYTE
+adc(UBYTE acc, UBYTE val)
+{
+	/* binary mode */
+	if (!(CPU.P & FL_D))
+	{
+		SWORD sig = (SBYTE)acc;
+		UWORD usig = (UBYTE)acc;
+
+		if (CPU.P & FL_C)
+		{
+			usig++;
+			sig++;
+		}
+		sig += (SBYTE)val;
+		usig += (UBYTE)val;
+		acc = (UBYTE)(usig & 0xFF);
+
+		CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z | FL_C)) | (((sig > 127) || (sig < -128)) ? FL_V : 0) | ((usig > 255) ? FL_C : 0) | FLAG_NZ(acc);
+	}
+
+	/* decimal mode */
+	else
+	{
+		uint32_t temp = bcd2bin[acc] + bcd2bin[val];
+
+		if (CPU.P & FL_C)
+		{
+			temp++;
+		}
+
+		acc = bin2bcd[temp];
+
+		CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp > 99) ? FL_C : 0) | FLAG_NZ(acc);
+
+		Cycles++; /* decimal mode takes an extra cycle */
+	}
+
+	return acc;
+}
+
+
+static ALWAYS_INLINE void
+sbc(UBYTE val)
+{
+	/* binary mode */
+	if (!(CPU.P & FL_D))
+	{
+		SWORD sig = (SBYTE)CPU.A;
+		UWORD usig = (UBYTE)CPU.A;
+
+		if (!(CPU.P & FL_C))
+		{
+			usig--;
+			sig--;
+		}
+		sig -= (SBYTE)val;
+		usig -= (UBYTE)val;
+		CPU.A = (UBYTE)(usig & 0xFF);
+		CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z | FL_C)) | (((sig > 127) || (sig < -128)) ? FL_V : 0) | ((usig > 255) ? 0 : FL_C) | FLAG_NZ(CPU.A);
+	}
+
+	/* decimal mode */
+	else
+	{
+		int temp = (int)bcd2bin[CPU.A] - bcd2bin[val];
+
+		if (!(CPU.P & FL_C))
+		{
+			temp--;
+		}
+
+		CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp < 0) ? 0 : FL_C);
+
+		while (temp < 0)
+		{
+			temp += 100;
+		}
+
+		CPU.A = bin2bcd[temp];
+		chk_flnz_8bit(CPU.A);
+
+		Cycles++; /* decimal mode takes an extra cycle */
+	}
+}
+
+OPCODE_FUNC adc_abs(void)
+{
+	// if flag 'T' is set, use zero-page address specified by register 'X'
+	// as the accumulator...
+
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), abs_operand(CPU.PC + 1)));
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, abs_operand(CPU.PC + 1));
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC adc_absx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), absx_operand(CPU.PC + 1)));
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, absx_operand(CPU.PC + 1));
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC adc_absy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), absy_operand(CPU.PC + 1)));
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, absy_operand(CPU.PC + 1));
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC adc_imm(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), imm_operand(CPU.PC + 1)));
+		Cycles += 5;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, imm_operand(CPU.PC + 1));
+		Cycles += 2;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC adc_zp(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), zp_operand(CPU.PC + 1)));
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, zp_operand(CPU.PC + 1));
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC adc_zpx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), zpx_operand(CPU.PC + 1)));
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, zpx_operand(CPU.PC + 1));
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC adc_zpind(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), zpind_operand(CPU.PC + 1)));
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, zpind_operand(CPU.PC + 1));
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC adc_zpindx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), zpindx_operand(CPU.PC + 1)));
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, zpindx_operand(CPU.PC + 1));
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC adc_zpindy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		put_8bit_zp(CPU.X, adc(get_8bit_zp(CPU.X), zpindy_operand(CPU.PC + 1)));
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A = adc(CPU.A, zpindy_operand(CPU.PC + 1));
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_abs(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A &= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC and_absx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A &= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC and_absy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A &= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC and_imm(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 5;
+	}
+	else
+	{
+		CPU.A &= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 2;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_zp(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A &= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_zpx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A &= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_zpind(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A &= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_zpindx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A &= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC and_zpindy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp &= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A &= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC asl_a(void)
+{
+	UBYTE temp = CPU.A;
+	CPU.A <<= 1;
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp & 0x80) ? FL_C : 0) | FLAG_NZ(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC asl_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = temp1 << 1;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC asl_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = temp1 << 1;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC asl_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = temp1 << 1;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC asl_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = temp1 << 1;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC bbr(UBYTE bit)
+{
+	CPU.P &= ~FL_T;
+	if (zp_operand(CPU.PC + 1) & (1 << bit))
+	{
+		CPU.PC += 3;
+		Cycles += 6;
+	}
+	else
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 2) + 3;
+		Cycles += 8;
+	}
+}
+
+OPCODE_FUNC bbs(UBYTE bit)
+{
+	CPU.P &= ~FL_T;
+	if (zp_operand(CPU.PC + 1) & (1 << bit))
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 2) + 3;
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.PC += 3;
+		Cycles += 6;
+	}
+}
+
+OPCODE_FUNC bcc(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_C)
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+	else
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+}
+
+OPCODE_FUNC bcs(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_C)
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+	else
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+}
+
+OPCODE_FUNC beq(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_Z)
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+	else
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+}
+
+OPCODE_FUNC bit_abs(void)
+{
+	UBYTE temp = abs_operand(CPU.PC + 1);
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((CPU.A & temp) ? 0 : FL_Z);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC bit_absx(void)
+{
+	UBYTE temp = absx_operand(CPU.PC + 1);
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((CPU.A & temp) ? 0 : FL_Z);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC bit_imm(void)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((CPU.A & temp) ? 0 : FL_Z);
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC bit_zp(void)
+{
+	UBYTE temp = zp_operand(CPU.PC + 1);
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((CPU.A & temp) ? 0 : FL_Z);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC bit_zpx(void)
+{
+	UBYTE temp = zpx_operand(CPU.PC + 1);
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((CPU.A & temp) ? 0 : FL_Z);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC bmi(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_N)
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+	else
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+}
+
+OPCODE_FUNC bne(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_Z)
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+	else
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+}
+
+OPCODE_FUNC bpl(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_N)
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+	else
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+}
+
+OPCODE_FUNC bra(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC brk(void)
+{
+	MESSAGE_DEBUG("BRK opcode has been hit [PC = 0x%04x] at %s(%d)\n", CPU.PC);
+	CPU.P &= ~FL_T;
+	push_16bit(CPU.PC + 2);
+	push_8bit(CPU.P | FL_B);
+	CPU.P = (CPU.P & ~FL_D) | FL_I;
+	CPU.PC = pce_read16(VEC_BRK);
+	Cycles += 8;
+}
+
+OPCODE_FUNC bsr(void)
+{
+	CPU.P &= ~FL_T;
+	push_16bit(CPU.PC + 1);
+	CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+	Cycles += 8;
+}
+
+OPCODE_FUNC bvc(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_V)
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+	else
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+}
+
+OPCODE_FUNC bvs(void)
+{
+	CPU.P &= ~FL_T;
+	if (CPU.P & FL_V)
+	{
+		CPU.PC += (SBYTE)imm_operand(CPU.PC + 1) + 2;
+		Cycles += 4;
+	}
+	else
+	{
+		CPU.PC += 2;
+		Cycles += 2;
+	}
+}
+
+OPCODE_FUNC cla(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.A = 0;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC clc(void)
+{
+	CPU.P &= ~(FL_T | FL_C);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cld(void)
+{
+	CPU.P &= ~(FL_T | FL_D);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cli(void)
+{
+	CPU.P &= ~(FL_T | FL_I);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC clv(void)
+{
+	CPU.P &= ~(FL_V | FL_T);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC clx(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.X = 0;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cly(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.Y = 0;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cmp_abs(void)
+{
+	UBYTE temp = abs_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC cmp_absx(void)
+{
+	UBYTE temp = absx_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC cmp_absy(void)
+{
+	UBYTE temp = absy_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC cmp_imm(void)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cmp_zp(void)
+{
+	UBYTE temp = zp_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC cmp_zpx(void)
+{
+	UBYTE temp = zpx_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC cmp_zpind(void)
+{
+	UBYTE temp = zpind_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC cmp_zpindx(void)
+{
+	UBYTE temp = zpindx_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC cmp_zpindy(void)
+{
+	UBYTE temp = zpindy_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.A < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.A - temp));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC cpx_abs(void)
+{
+	UBYTE temp = abs_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.X < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.X - temp));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC cpx_imm(void)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.X < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.X - temp));
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cpx_zp(void)
+{
+	UBYTE temp = zp_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.X < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.X - temp));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC cpy_abs(void)
+{
+	UBYTE temp = abs_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.Y < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.Y - temp));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC cpy_imm(void)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.Y < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.Y - temp));
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC cpy_zp(void)
+{
+	UBYTE temp = zp_operand(CPU.PC + 1);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((CPU.Y < temp) ? 0 : FL_C) | FLAG_NZ((UBYTE)(CPU.Y - temp));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC dec_a(void)
+{
+	--CPU.A;
+	chk_flnz_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC dec_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp = pce_read8(temp_addr) - 1;
+	chk_flnz_8bit(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC dec_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp = pce_read8(temp_addr) - 1;
+	chk_flnz_8bit(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC dec_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = get_8bit_zp(zp_addr) - 1;
+	chk_flnz_8bit(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC dec_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp = get_8bit_zp(zp_addr) - 1;
+	chk_flnz_8bit(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC dex(void)
+{
+	--CPU.X;
+	chk_flnz_8bit(CPU.X);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC dey(void)
+{
+	--CPU.Y;
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC eor_abs(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A ^= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC eor_absx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A ^= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC eor_absy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A ^= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC eor_imm(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 5;
+	}
+	else
+	{
+		CPU.A ^= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 2;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC eor_zp(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A ^= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC eor_zpx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A ^= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC eor_zpind(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A ^= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC eor_zpindx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A ^= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC eor_zpindy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp ^= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A ^= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC halt(void)
+{
+	return;
+}
+
+OPCODE_FUNC inc_a(void)
+{
+	++CPU.A;
+	chk_flnz_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC inc_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp = pce_read8(temp_addr) + 1;
+	chk_flnz_8bit(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC inc_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp = pce_read8(temp_addr) + 1;
+	chk_flnz_8bit(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC inc_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = get_8bit_zp(zp_addr) + 1;
+	chk_flnz_8bit(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC inc_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp = get_8bit_zp(zp_addr) + 1;
+	chk_flnz_8bit(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC inx(void)
+{
+	++CPU.X;
+	chk_flnz_8bit(CPU.X);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC iny(void)
+{
+	++CPU.Y;
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC jmp(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.PC = pce_read16(CPU.PC + 1);
+	Cycles += 4;
+}
+
+OPCODE_FUNC jmp_absind(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.PC = pce_read16(pce_read16(CPU.PC + 1));
+	Cycles += 7;
+}
+
+OPCODE_FUNC jmp_absindx(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.PC = pce_read16(pce_read16(CPU.PC + 1) + CPU.X);
+	Cycles += 7;
+}
+
+OPCODE_FUNC jsr(void)
+{
+	CPU.P &= ~FL_T;
+	push_16bit(CPU.PC + 2);
+	CPU.PC = pce_read16(CPU.PC + 1);
+	Cycles += 7;
+}
+
+OPCODE_FUNC lda_abs(void)
+{
+	CPU.A = abs_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC lda_absx(void)
+{
+	CPU.A = absx_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC lda_absy(void)
+{
+	CPU.A = absy_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC lda_imm(void)
+{
+	CPU.A = imm_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC lda_zp(void)
+{
+	CPU.A = zp_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC lda_zpx(void)
+{
+	CPU.A = zpx_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC lda_zpind(void)
+{
+	CPU.A = zpind_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC lda_zpindx(void)
+{
+	CPU.A = zpindx_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC lda_zpindy(void)
+{
+	CPU.A = zpindy_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC ldx_abs(void)
+{
+	CPU.X = abs_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC ldx_absy(void)
+{
+	CPU.X = absy_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC ldx_imm(void)
+{
+	CPU.X = imm_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC ldx_zp(void)
+{
+	CPU.X = zp_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC ldx_zpy(void)
+{
+	CPU.X = zpy_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC ldy_abs(void)
+{
+	CPU.Y = abs_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC ldy_absx(void)
+{
+	CPU.Y = absx_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC ldy_imm(void)
+{
+	CPU.Y = imm_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC ldy_zp(void)
+{
+	CPU.Y = zp_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC ldy_zpx(void)
+{
+	CPU.Y = zpx_operand(CPU.PC + 1);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC lsr_a(void)
+{
+	UBYTE temp = CPU.A;
+	CPU.A /= 2;
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp & 1) ? FL_C : 0) | FLAG_NZ(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC lsr_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = temp1 / 2;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 1) ? FL_C : 0) | FLAG_NZ(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC lsr_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = temp1 / 2;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 1) ? FL_C : 0) | FLAG_NZ(temp);
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC lsr_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = temp1 / 2;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 1) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC lsr_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = temp1 / 2;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 1) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC nop(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC ora_abs(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A |= abs_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC ora_absx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A |= absx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC ora_absy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 8;
+	}
+	else
+	{
+		CPU.A |= absy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 5;
+	}
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC ora_imm(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 5;
+	}
+	else
+	{
+		CPU.A |= imm_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 2;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC ora_zp(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A |= zp_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC ora_zpx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 7;
+	}
+	else
+	{
+		CPU.A |= zpx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 4;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC ora_zpind(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A |= zpind_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC ora_zpindx(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A |= zpindx_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC ora_zpindy(void)
+{
+	if (CPU.P & FL_T)
+	{
+		UBYTE temp = get_8bit_zp(CPU.X);
+		temp |= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(temp);
+		put_8bit_zp(CPU.X, temp);
+		Cycles += 10;
+	}
+	else
+	{
+		CPU.A |= zpindy_operand(CPU.PC + 1);
+		chk_flnz_8bit(CPU.A);
+		Cycles += 7;
+	}
+	CPU.PC += 2;
+}
+
+OPCODE_FUNC pha(void)
+{
+	CPU.P &= ~FL_T;
+	push_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC php(void)
+{
+	CPU.P &= ~FL_T;
+	push_8bit(CPU.P);
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC phx(void)
+{
+	CPU.P &= ~FL_T;
+	push_8bit(CPU.X);
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC phy(void)
+{
+	CPU.P &= ~FL_T;
+	push_8bit(CPU.Y);
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC pla(void)
+{
+	pull_8bit(CPU.A);
+	chk_flnz_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 4;
+}
+
+OPCODE_FUNC plp(void)
+{
+	pull_8bit(CPU.P);
+	CPU.PC++;
+	Cycles += 4;
+}
+
+OPCODE_FUNC plx(void)
+{
+	pull_8bit(CPU.X);
+	chk_flnz_8bit(CPU.X);
+	CPU.PC++;
+	Cycles += 4;
+}
+
+OPCODE_FUNC ply(void)
+{
+	pull_8bit(CPU.Y);
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC++;
+	Cycles += 4;
+}
+
+OPCODE_FUNC rmb(UBYTE bit)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+	CPU.P &= ~FL_T;
+	put_8bit_zp(temp, get_8bit_zp(temp) & (~(1 << bit)));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC rol_a(void)
+{
+	UBYTE temp = CPU.A;
+	CPU.A = (CPU.A << 1) + (CPU.P & FL_C);
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp & 0x80) ? FL_C : 0) | FLAG_NZ(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC rol_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = (temp1 << 1) + (CPU.P & FL_C);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	Cycles += 7;
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC rol_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = (temp1 << 1) + (CPU.P & FL_C);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	Cycles += 7;
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC rol_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = (temp1 << 1) + (CPU.P & FL_C);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC rol_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = (temp1 << 1) + (CPU.P & FL_C);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x80) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC ror_a(void)
+{
+	UBYTE temp = CPU.A;
+	CPU.A = (CPU.A >> 1) + ((CPU.P & FL_C) ? 0x80 : 0);
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp & 0x01) ? FL_C : 0) | FLAG_NZ(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC ror_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = (temp1 >> 1) + ((CPU.P & FL_C) ? 0x80 : 0);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x01) ? FL_C : 0) | FLAG_NZ(temp);
+	Cycles += 7;
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC ror_absx(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = pce_read8(temp_addr);
+	UBYTE temp = (temp1 >> 1) + ((CPU.P & FL_C) ? 0x80 : 0);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x01) ? FL_C : 0) | FLAG_NZ(temp);
+	Cycles += 7;
+	pce_write8(temp_addr, temp);
+	CPU.PC += 3;
+}
+
+OPCODE_FUNC ror_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = (temp1 >> 1) + ((CPU.P & FL_C) ? 0x80 : 0);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x01) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC ror_zpx(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1) + CPU.X;
+	UBYTE temp1 = get_8bit_zp(zp_addr);
+	UBYTE temp = (temp1 >> 1) + ((CPU.P & FL_C) ? 0x80 : 0);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_T | FL_Z | FL_C)) | ((temp1 & 0x01) ? FL_C : 0) | FLAG_NZ(temp);
+	put_8bit_zp(zp_addr, temp);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC rti(void)
+{
+	/* FL_B reset in RTI */
+	pull_8bit(CPU.P);
+	CPU.P &= ~FL_B;
+	uint8_t t, t2;
+	pull_8bit(t);
+	pull_8bit(t2);
+	CPU.PC = (t | t2 << 8);
+	Cycles += 7;
+}
+
+OPCODE_FUNC rts(void)
+{
+	CPU.P &= ~FL_T;
+	uint8_t t, t2;
+	pull_8bit(t);
+	pull_8bit(t2);
+	CPU.PC = (t | t2 << 8) + 1;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sax(void)
+{
+	UBYTE temp = CPU.X;
+	CPU.P &= ~FL_T;
+	CPU.X = CPU.A;
+	CPU.A = temp;
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC say(void)
+{
+	UBYTE temp = CPU.Y;
+	CPU.P &= ~FL_T;
+	CPU.Y = CPU.A;
+	CPU.A = temp;
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC sbc_abs(void)
+{
+	sbc(abs_operand(CPU.PC + 1));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sbc_absx(void)
+{
+	sbc(absx_operand(CPU.PC + 1));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sbc_absy(void)
+{
+	sbc(absy_operand(CPU.PC + 1));
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sbc_imm(void)
+{
+	sbc(imm_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 2;
+}
+
+OPCODE_FUNC sbc_zp(void)
+{
+	sbc(zp_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sbc_zpx(void)
+{
+	sbc(zpx_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sbc_zpind(void)
+{
+	sbc(zpind_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sbc_zpindx(void)
+{
+	sbc(zpindx_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sbc_zpindy(void)
+{
+	sbc(zpindy_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sec(void)
+{
+	CPU.P = (CPU.P | FL_C) & ~FL_T;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC sed(void)
+{
+	CPU.P = (CPU.P | FL_D) & ~FL_T;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC sei(void)
+{
+	CPU.P = (CPU.P | FL_I) & ~FL_T;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC set(void)
+{
+	CPU.P |= FL_T;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC smb(UBYTE bit)
+{
+	UBYTE temp = imm_operand(CPU.PC + 1);
+	CPU.P &= ~FL_T;
+	put_8bit_zp(temp, get_8bit_zp(temp) | (1 << bit));
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC st0(void)
+{
+	CPU.P &= ~FL_T;
+	pce_writeIO(0, imm_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC st1(void)
+{
+	CPU.P &= ~FL_T;
+	pce_writeIO(2, imm_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC st2(void)
+{
+	CPU.P &= ~FL_T;
+	pce_writeIO(3, imm_operand(CPU.PC + 1));
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sta_abs(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1), CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sta_absx(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1) + CPU.X, CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sta_absy(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1) + CPU.Y, CPU.A);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sta_zp(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1), CPU.A);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sta_zpx(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1) + CPU.X, CPU.A);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sta_zpind(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(get_16bit_zp(imm_operand(CPU.PC + 1)), CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sta_zpindx(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(get_16bit_zp(imm_operand(CPU.PC + 1) + CPU.X), CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC sta_zpindy(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(get_16bit_zp(imm_operand(CPU.PC + 1)) + CPU.Y, CPU.A);
+	CPU.PC += 2;
+	Cycles += 7;
+}
+
+OPCODE_FUNC stx_abs(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1), CPU.X);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC stx_zp(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1), CPU.X);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC stx_zpy(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1) + CPU.Y, CPU.X);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sty_abs(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1), CPU.Y);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC sty_zp(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1), CPU.Y);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sty_zpx(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1) + CPU.X, CPU.Y);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC stz_abs(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8(pce_read16(CPU.PC + 1), 0);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC stz_absx(void)
+{
+	CPU.P &= ~FL_T;
+	pce_write8((pce_read16(CPU.PC + 1) + CPU.X), 0);
+	CPU.PC += 3;
+	Cycles += 5;
+}
+
+OPCODE_FUNC stz_zp(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1), 0);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC stz_zpx(void)
+{
+	CPU.P &= ~FL_T;
+	put_8bit_zp(imm_operand(CPU.PC + 1) + CPU.X, 0);
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC sxy(void)
+{
+	UBYTE temp = CPU.Y;
+	CPU.P &= ~FL_T;
+	CPU.Y = CPU.X;
+	CPU.X = temp;
+	CPU.PC++;
+	Cycles += 3;
+}
+
+OPCODE_FUNC tai(void)
+{
+	CPU.P &= ~FL_T;
+	UWORD from = pce_read16(CPU.PC + 1);
+	UWORD to = pce_read16(CPU.PC + 3);
+	UWORD len = pce_read16(CPU.PC + 5);
+	if ( len == 0 ) len = 0xffff;
+	UWORD alternate = 0;
+
+	Cycles += (6 * len) + 17;
+	while (len-- != 0)
+	{
+		pce_write8(to++, pce_read8(from + alternate));
+		alternate ^= 1;
+	}
+	CPU.PC += 7;
+}
+
+OPCODE_FUNC csh(void)
+{
+	PCE.Timer.cycles_per_line = 455; /* 21477270 / 3 / 60 / 263 */ /* 7.16 Mhz CPU clock */
+	CPU.PC++;
+	Cycles+=3;
+}
+
+OPCODE_FUNC csl(void)
+{
+	PCE.Timer.cycles_per_line = 113; /* 21477270 / 12 / 60 / 263 */ /* 1.78 Mhz CPU clock */
+	CPU.PC++;
+	Cycles+=3;
+}
+
+static int tamwrite = -1;
+static int tamread = 0;
+
+OPCODE_FUNC tam(void)
+{
+	UBYTE bitfld = imm_operand(CPU.PC + 1);
+
+	tamwrite = -1;
+	for (int i = 0; i < 8; i++)
+	{
+		if (bitfld & (1 << i))
+		{
+			pce_bank_set(i, CPU.A);
+			tamwrite = CPU.A;
+		}
+	}
+
+	CPU.P &= ~FL_T;
+	CPU.PC += 2;
+	Cycles += 5;
+}
+
+OPCODE_FUNC tax(void)
+{
+	CPU.X = CPU.A;
+	chk_flnz_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC tay(void)
+{
+	CPU.Y = CPU.A;
+	chk_flnz_8bit(CPU.A);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC tdd(void)
+{
+	CPU.P &= ~FL_T;
+	UWORD from = pce_read16(CPU.PC + 1);
+	UWORD to = pce_read16(CPU.PC + 3);
+	UWORD len = pce_read16(CPU.PC + 5);
+	if ( len == 0 ) len = 0xffff;
+
+	Cycles += (6 * len) + 17;
+	while (len-- != 0)
+	{
+		pce_write8(to--, pce_read8(from--));
+	}
+	CPU.PC += 7;
+}
+
+OPCODE_FUNC tia(void)
+{
+	CPU.P &= ~FL_T;
+	UWORD from = pce_read16(CPU.PC + 1);
+	UWORD to = pce_read16(CPU.PC + 3);
+	UWORD len = pce_read16(CPU.PC + 5);
+	if ( len == 0 ) len = 0xffff;
+	UWORD alternate = 0;
+
+	Cycles += (6 * len) + 17;
+	while (len-- != 0)
+	{
+		pce_write8(to + alternate, pce_read8(from++));
+		alternate ^= 1;
+	}
+	CPU.PC += 7;
+}
+
+OPCODE_FUNC tii(void)
+{
+	CPU.P &= ~FL_T;
+	UWORD from = pce_read16(CPU.PC + 1);
+	UWORD to = pce_read16(CPU.PC + 3);
+	UWORD len = pce_read16(CPU.PC + 5);
+	if ( len == 0 ) len = 0xffff;
+
+	Cycles += (6 * len) + 17;
+	while (len-- != 0)
+	{
+		pce_write8(to++, pce_read8(from++));
+	}
+	CPU.PC += 7;
+}
+
+OPCODE_FUNC tin(void)
+{
+	CPU.P &= ~FL_T;
+	UWORD from = pce_read16(CPU.PC + 1);
+	UWORD to = pce_read16(CPU.PC + 3);
+	UWORD len = pce_read16(CPU.PC + 5);
+	if ( len == 0 ) len = 0xffff;
+
+	Cycles += (6 * len) + 17;
+	while (len-- != 0)
+	{
+		pce_write8(to, pce_read8(from++));
+	}
+	CPU.PC += 7;
+}
+
+OPCODE_FUNC tma(void)
+{
+	UBYTE bitfld = imm_operand(CPU.PC + 1);
+
+	if ( bitfld & 0xff )
+	{
+		for (int i = 0; i < 8; i++)
+		{
+			if (bitfld & (1 << i))
+			{
+				CPU.A = PCE.MMR[i];
+			}
+		}
+		tamread = CPU.A;
+	} else {
+		CPU.A = ( tamwrite != -1 ) ? tamwrite : tamread ;
+	}
+	CPU.P &= ~FL_T;
+	CPU.PC += 2;
+	Cycles += 4;
+}
+
+OPCODE_FUNC trb_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp = pce_read8(temp_addr);
+	UBYTE temp1 = (~CPU.A) & temp;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp1 & (FL_N | FL_V)) | ((temp & CPU.A) ? 0 : FL_Z);
+	pce_write8(temp_addr, temp1);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC trb_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = get_8bit_zp(zp_addr);
+	UBYTE temp1 = (~CPU.A) & temp;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp1 & (FL_N | FL_V)) | ((temp & CPU.A) ? 0 : FL_Z);
+	put_8bit_zp(zp_addr, temp1);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC tsb_abs(void)
+{
+	UWORD temp_addr = pce_read16(CPU.PC + 1);
+	UBYTE temp = pce_read8(temp_addr);
+	UBYTE temp1 = CPU.A | temp;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp1 & (FL_N | FL_V)) | ((temp & CPU.A) ? 0 : FL_Z);
+	pce_write8(temp_addr, temp1);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC tsb_zp(void)
+{
+	UBYTE zp_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = get_8bit_zp(zp_addr);
+	UBYTE temp1 = CPU.A | temp;
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp1 & (FL_N | FL_V)) | ((temp & CPU.A) ? 0 : FL_Z);
+	put_8bit_zp(zp_addr, temp1);
+	CPU.PC += 2;
+	Cycles += 6;
+}
+
+OPCODE_FUNC tstins_abs(void)
+{
+	UBYTE imm_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = abs_operand(CPU.PC + 2);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((temp & imm_addr) ? 0 : FL_Z);
+	CPU.PC += 4;
+	Cycles += 8;
+}
+
+OPCODE_FUNC tstins_absx(void)
+{
+	UBYTE imm_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = absx_operand(CPU.PC + 2);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((temp & imm_addr) ? 0 : FL_Z);
+	CPU.PC += 4;
+	Cycles += 8;
+}
+
+OPCODE_FUNC tstins_zp(void)
+{
+	UBYTE imm_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = zp_operand(CPU.PC + 2);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((temp & imm_addr) ? 0 : FL_Z);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC tstins_zpx(void)
+{
+	UBYTE imm_addr = imm_operand(CPU.PC + 1);
+	UBYTE temp = zpx_operand(CPU.PC + 2);
+
+	CPU.P = (CPU.P & ~(FL_N | FL_V | FL_T | FL_Z)) | (temp & (FL_N | FL_V)) | ((temp & imm_addr) ? 0 : FL_Z);
+	CPU.PC += 3;
+	Cycles += 7;
+}
+
+OPCODE_FUNC tsx(void)
+{
+	CPU.X = CPU.S;
+	chk_flnz_8bit(CPU.S);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC txa(void)
+{
+	CPU.A = CPU.X;
+	chk_flnz_8bit(CPU.X);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC txs(void)
+{
+	CPU.P &= ~FL_T;
+	CPU.S = CPU.X;
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC tya(void)
+{
+	CPU.A = CPU.Y;
+	chk_flnz_8bit(CPU.Y);
+	CPU.PC++;
+	Cycles += 2;
+}
+
+OPCODE_FUNC interrupt(unsigned type)
+{
+	// pcetech.txt says the program should clear the irq line by reading 0x1403
+	// however in practice it seems to break many games if we don't clear it?
+
+	TRACE_CPU("CPU interrupt: %d\n", type);
+	push_16bit(CPU.PC);
+	push_8bit(CPU.P);
+	CPU.P &= ~(FL_D|FL_T);
+	CPU.P |= FL_I;
+	if (type & INT_IRQ1) {
+		CPU.irq_lines &= ~INT_IRQ1;
+		CPU.PC = pce_read16(VEC_IRQ1);
+	} else if (type & INT_IRQ2) {
+		CPU.irq_lines &= ~INT_IRQ2;
+		CPU.PC = pce_read16(VEC_IRQ2);
+	} else {
+		CPU.irq_lines &= ~INT_TIMER;
+		CPU.PC = pce_read16(VEC_TIMER);
+	}
+	Cycles += 7;
+}
diff --git a/MCUME_pico2/picopce/pce-go/pce-go.c b/MCUME_pico2/picopce/pce-go/pce-go.c
new file mode 100755
index 0000000..2773b51
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/pce-go.c
@@ -0,0 +1,424 @@
+// pce-go.c - Entry file to start/stop/reset/save emulation
+//
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "pce-go.h"
+#include "gfx.h"
+#include "psg.h"
+#include "pce.h"
+
+/**
+ * Save state file description.
+ */
+#define SVAR_1(k, v) { {k, 1, 1}, &v }
+#define SVAR_2(k, v) { {k, 2, 2}, &v }
+#define SVAR_4(k, v) { {k, 4, 4}, &v }
+#define SVAR_A(k, v) { {k, 0, sizeof(v)}, &v }
+#define SVAR_N(k, v, n) { {k, 0, n}, &v }
+#define SVAR_P(k, v, n) { {k, 5, n}, &v }
+#define SVAR_END { {"END", 0, 0}, NULL }
+
+typedef struct __attribute__((packed)) {
+    char key[12];
+    uint32_t type: 8;
+    uint32_t len: 24;
+} block_hdr_t;
+
+typedef const struct {
+    block_hdr_t desc;
+    void *ptr;
+} save_var_t;
+
+static const char SAVESTATE_HEADER[8] = "PCE_V010";
+static save_var_t SaveStateVars[] =
+        {
+                // Arrays
+                SVAR_N("RAM", PCE.RAM, 0x2000), SVAR_N("VRAM", PCE.VRAM, 0x8000 * 2),
+                SVAR_N("SPRAM", PCE.SPRAM, 64), SVAR_N("PAL", PCE.Palette, 512),
+                SVAR_A("MMR", PCE.MMR),
+
+                // CPU registers
+                SVAR_2("CPU.PC", CPU.PC), SVAR_1("CPU.A", CPU.A), SVAR_1("CPU.X", CPU.X),
+                SVAR_1("CPU.Y", CPU.Y), SVAR_1("CPU.P", CPU.P), SVAR_1("CPU.S", CPU.S),
+
+                // Misc
+                SVAR_4("Cycles", PCE.Cycles), SVAR_4("MaxCycles", PCE.MaxCycles),
+                SVAR_1("SF2", PCE.SF2),
+
+                // IRQ
+                SVAR_1("IRQ.mask", CPU.irq_mask), SVAR_1("IRQ.lines", CPU.irq_lines),
+                SVAR_1("IRQ.m_delay", CPU.irq_mask_delay),
+
+                // PSG
+                SVAR_1("PSG.ch", PCE.PSG.ch), SVAR_1("PSG.vol", PCE.PSG.volume),
+                SVAR_1("PSG.lfo_f", PCE.PSG.lfo_freq), SVAR_1("PSG.lfo_c", PCE.PSG.lfo_ctrl),
+                SVAR_N("PSG.ch0", PCE.PSG.chan[0], 40), SVAR_N("PSG.ch1", PCE.PSG.chan[1], 40),
+                SVAR_N("PSG.ch2", PCE.PSG.chan[2], 40), SVAR_N("PSG.ch3", PCE.PSG.chan[3], 40),
+                SVAR_N("PSG.ch4", PCE.PSG.chan[4], 40), SVAR_N("PSG.ch5", PCE.PSG.chan[5], 40),
+
+                // VCE
+                SVAR_A("VCE.regs", PCE.VCE.regs), SVAR_2("VCE.reg", PCE.VCE.reg),
+
+                // VDC
+                SVAR_A("VDC.regs", PCE.VDC.regs), SVAR_1("VDC.reg", PCE.VDC.reg),
+                SVAR_1("VDC.status", PCE.VDC.status), SVAR_1("VDC.satb", PCE.VDC.satb),
+                SVAR_4("VDC.irqs", PCE.VDC.pending_irqs), SVAR_1("VDC.vram", PCE.VDC.vram),
+
+                // Timer
+                SVAR_4("TMR.reload", PCE.Timer.reload), SVAR_4("TMR.running", PCE.Timer.running),
+                SVAR_4("TMR.counter", PCE.Timer.counter), SVAR_4("TMR.next", PCE.Timer.cycles_counter),
+                SVAR_4("TMR.freq", PCE.Timer.cycles_per_line),
+
+                SVAR_END
+        };
+
+#define TWO_PART_ROM 0x0001
+#define ONBOARD_RAM  0x0100
+#define US_ENCODED   0x0010
+
+static const struct {
+    const uint32_t CRC;
+    const char *Name;
+    const uint32_t Flags;
+} romFlags[] = {
+        { 0xF0ED3094, "Blazing Lazers",       TWO_PART_ROM },
+        { 0xB4A1B0F6, "Blazing Lazers",       TWO_PART_ROM },
+        { 0x55E9630D, "Legend of Hero Tonma", US_ENCODED },
+        { 0x083C956A, "Populous",             ONBOARD_RAM },
+        { 0x0A9ADE99, "Populous",             ONBOARD_RAM },
+        { 0x00000000, "Unknown", 0 },
+};
+
+static bool running = false;
+
+/**
+ * Load card into memory and set its memory map
+ */
+int LoadCard(const char *ROM, size_t fsize) {
+    int offset;
+#if 0
+
+
+    MESSAGE_INFO("Opening %s...\n", name);
+
+    FILE *fp = fopen(name, "rb");
+
+    if (fp == NULL)
+    {
+        MESSAGE_ERROR("Failed to open %s!\n", name);
+        return -1;
+    }
+
+    if (PCE.ROM != NULL) {
+        free(PCE.ROM);
+    }
+
+    // find file size
+    fseek(fp, 0, SEEK_END);
+    fsize = ftell(fp);
+#endif
+    offset = fsize & 0x1fff;
+
+    // read ROM
+    PCE.ROM = ROM;
+
+    if (PCE.ROM == NULL) {
+        MESSAGE_ERROR("Failed to allocate ROM buffer!\n");
+        return -1;
+    }
+/*
+	fseek(fp, 0, SEEK_SET);
+	fread(PCE.ROM, 1, fsize, fp);
+
+	fclose(fp);
+*/
+    PCE.ROM_SIZE = (fsize - offset) / 0x2000;
+    PCE.ROM_DATA = PCE.ROM + offset;
+    PCE.ROM_CRC = crc32_le(0, PCE.ROM, fsize);
+
+    uint32_t IDX = 0;
+    uint32_t ROM_MASK = 1;
+
+    while (ROM_MASK < PCE.ROM_SIZE) ROM_MASK <<= 1;
+    ROM_MASK--;
+
+    MESSAGE_INFO("ROM LOADED: OFFSET=%d, BANKS=%d, MASK=%03X, CRC=%08X\n",
+                 offset, PCE.ROM_SIZE, ROM_MASK, PCE.ROM_CRC);
+
+    while (romFlags[IDX].CRC) {
+        if (PCE.ROM_CRC == romFlags[IDX].CRC)
+            break;
+        IDX++;
+    }
+
+    MESSAGE_INFO("Game Name: %s\n", romFlags[IDX].Name);
+
+    // US Encrypted
+    if ((romFlags[IDX].Flags & US_ENCODED) || PCE.ROM_DATA[0x1FFF] < 0xE0) {
+        MESSAGE_INFO("This rom is probably US encrypted, decrypting...\n");
+
+        unsigned char inverted_nibble[16] = {
+                0, 8, 4, 12, 2, 10, 6, 14,
+                1, 9, 5, 13, 3, 11, 7, 15
+        };
+
+        for (int x = 0; x < PCE.ROM_SIZE * 0x2000; x++) {
+            unsigned char temp = PCE.ROM_DATA[x] & 15;
+
+            PCE.ROM_DATA[x] &= ~0x0F;
+            PCE.ROM_DATA[x] |= inverted_nibble[PCE.ROM_DATA[x] >> 4];
+
+            PCE.ROM_DATA[x] &= ~0xF0;
+            PCE.ROM_DATA[x] |= inverted_nibble[temp] << 4;
+        }
+    }
+
+    // For example with Devil Crush 512Ko
+    if (romFlags[IDX].Flags & TWO_PART_ROM)
+        PCE.ROM_SIZE = 0x30;
+
+    // Game ROM
+    for (int i = 0; i < 0x80; i++) {
+        if (PCE.ROM_SIZE == 0x30) {
+            switch (i & 0x70) {
+                case 0x00:
+                case 0x10:
+                case 0x50:
+                    PCE.MemoryMapR[i] = PCE.ROM_DATA + (i & ROM_MASK) * 0x2000;
+                    break;
+                case 0x20:
+                case 0x60:
+                    PCE.MemoryMapR[i] = PCE.ROM_DATA + ((i - 0x20) & ROM_MASK) * 0x2000;
+                    break;
+                case 0x30:
+                case 0x70:
+                    PCE.MemoryMapR[i] = PCE.ROM_DATA + ((i - 0x10) & ROM_MASK) * 0x2000;
+                    break;
+                case 0x40:
+                    PCE.MemoryMapR[i] = PCE.ROM_DATA + ((i - 0x20) & ROM_MASK) * 0x2000;
+                    break;
+            }
+        } else {
+            PCE.MemoryMapR[i] = PCE.ROM_DATA + (i & ROM_MASK) * 0x2000;
+        }
+        PCE.MemoryMapW[i] = PCE.NULLRAM;
+    }
+
+    // Allocate the card's onboard ram
+    if (romFlags[IDX].Flags & ONBOARD_RAM) {
+        // if (!PCE.ExRAM)
+        // PCE.ExRAM = malloc(0x8000);
+        PCE.MemoryMapR[0x40] = PCE.MemoryMapW[0x40] = PCE.ExRAM;
+        PCE.MemoryMapR[0x41] = PCE.MemoryMapW[0x41] = PCE.ExRAM + 0x2000;
+        PCE.MemoryMapR[0x42] = PCE.MemoryMapW[0x42] = PCE.ExRAM + 0x4000;
+        PCE.MemoryMapR[0x43] = PCE.MemoryMapW[0x43] = PCE.ExRAM + 0x6000;
+    }
+
+    // Mapper for roms >= 1.5MB (SF2, homebrews)
+    if (PCE.ROM_SIZE >= 192)
+        PCE.MemoryMapW[0x00] = PCE.IOAREA;
+
+    return 0;
+}
+
+
+/**
+ * Reset the emulator
+ */
+void
+ResetPCE(bool hard) {
+    gfx_reset(hard);
+    pce_reset(hard);
+}
+
+
+/**
+ * Initialize the emulator (allocate memory, call osd_init* functions)
+ */
+int
+InitPCE(int samplerate, bool stereo, const void *ROM, size_t fsize) {
+    if (gfx_init())
+        return 1;
+
+    if (psg_init(samplerate, stereo))
+        return 1;
+
+    if (pce_init())
+        return 1;
+
+    if (ROM && LoadCard(ROM, fsize))
+        return 1;
+
+    ResetPCE(0);
+
+    return 0;
+}
+
+
+/**
+ * Returns a 256 colors palette in the chosen depth
+ */
+void *
+PalettePCE(int bitdepth) {
+    if (bitdepth == 15) {
+        uint16_t *palette = malloc(256 * 2);
+        // ...
+        return palette;
+    }
+
+    if (bitdepth == 16) {
+        uint16_t *palette = malloc(256 * 2);
+        for (int i = 0; i < 255; i++) {
+            int r = (i & 0x1C) >> 1;
+            int g = (i & 0xe0) >> 4;
+            int b = (i & 0x03) << 2;
+            palette[i] = (((r << 12) & 0xf800) + ((g << 7) & 0x07e0) + ((b << 1) & 0x001f));
+        }
+        palette[255] = 0xFFFF;
+        return palette;
+    }
+
+    if (bitdepth == 24) {
+        uint8_t *palette = malloc(256 * 3);
+        uint8_t *ptr = palette;
+        for (int i = 0; i < 255; i++) {
+            *ptr++ = (i & 0x1C) << 2;
+            *ptr++ = (i & 0xe0) >> 1;
+            *ptr++ = (i & 0x03) << 4;
+        }
+        *ptr++ = 0xFF;
+        *ptr++ = 0xFF;
+        *ptr++ = 0xFF;
+        return palette;
+    }
+
+    for (int i = 0; i < 255; i++) {
+        emu_SetPaletteEntry((i & 0x1C) << 2,(i & 0xe0) >> 1,(i & 0x03) << 4,i);
+    }
+    emu_SetPaletteEntry(0xff,0xff,0xff,255);
+    return NULL;
+}
+
+
+/**
+ * Start the emulation
+ */
+void
+RunPCE(void) {
+    running = true;
+
+    //while (running) {
+    //    osd_input_read(PCE.Joypad.regs);
+        pce_run();
+    //    osd_vsync();
+    //}
+}
+
+
+/**
+ * Load saved state
+ */
+int LoadState(const char *name) {
+
+    MESSAGE_INFO("Loading state from %s...\n", name);
+
+    char buffer[32];
+    block_hdr_t block;
+    int ret = -1;
+    unsigned int br = 0;
+
+    FIL fp;
+    if (f_open(&fp, name, FA_READ) != FR_OK)
+        return -1;
+
+    if (FR_OK != f_read(&fp, &buffer, 8, &br) || !br || memcmp(&buffer, SAVESTATE_HEADER, 8) != 0) {
+        MESSAGE_ERROR("Loading state failed: Header mismatch\n");
+        goto _cleanup;
+    }
+
+    while (FR_OK == f_read(&fp, &block, sizeof(block), &br) && br) {
+        size_t block_end = f_tell(&fp) + block.len;
+
+        for (save_var_t *var = SaveStateVars; var->ptr; var++) {
+            if (strncmp(var->desc.key, block.key, 12) == 0) {
+                void *ptr = var->ptr;
+                size_t len = MIN((size_t) var->desc.len, (size_t) block.len);
+                //memset(ptr, 0, var->desc.len);
+                if (FR_OK != f_read(&fp, ptr, len, &br) || !br) {
+                    MESSAGE_ERROR("fread error reading block data\n");
+                    goto _cleanup;
+                }
+                if (len < var->desc.len) {
+                    memset(ptr + len, 0, var->desc.len - len);
+                }
+                MESSAGE_INFO("Loaded %s\n", var->desc.key);
+                break;
+            }
+        }
+        f_lseek(&fp, block_end);
+    }
+
+    for (int i = 0; i < 8; i++)
+        pce_bank_set(i, PCE.MMR[i]);
+
+    gfx_reset(true);
+    PCE.VDC.mode_chg = 1;
+    ret = 0;
+
+    _cleanup:
+    f_close(&fp);
+
+    return ret;
+}
+
+
+/**
+ * Save current state
+ */
+int
+SaveState(const char *name) {
+    MESSAGE_INFO("Saving state to %s...\n", name);
+
+    int ret = -1;
+    unsigned int bw = 0;
+
+    FIL fp;
+    if (f_open(&fp, name, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK)
+        return -1;
+
+    f_write(&fp, SAVESTATE_HEADER, sizeof(SAVESTATE_HEADER), &bw);
+
+    for (save_var_t *var = SaveStateVars; var->ptr; var++) {
+        void *ptr = var->ptr;
+        size_t len = var->desc.len;
+        if (FR_OK != f_write(&fp, &var->desc, sizeof(var->desc), &bw)) {
+            MESSAGE_ERROR("fwrite error desc\n");
+            goto _cleanup;
+        }
+        if (FR_OK != f_write(&fp, ptr, len, &bw)) {
+            MESSAGE_ERROR("fwrite error value\n");
+            goto _cleanup;
+        }
+        MESSAGE_INFO("Saved %s\n", var->desc.key);
+    }
+
+    ret = 0;
+
+    _cleanup:
+    f_close(&fp);
+
+    return ret;
+}
+
+
+/**
+ * Cleanup and quit (not used in retro-go)
+ */
+void
+ShutdownPCE() {
+    gfx_term();
+    psg_term();
+    pce_term();
+}
diff --git a/MCUME_pico2/picopce/pce-go/pce-go.h b/MCUME_pico2/picopce/pce-go/pce-go.h
new file mode 100755
index 0000000..acba6f0
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/pce-go.h
@@ -0,0 +1,88 @@
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "config.h"
+#include "ff.h"
+
+#ifdef RETRO_GO
+#include <rg_system.h>
+#define LOG_PRINTF(level, x...) rg_system_log(RG_LOG_USER, NULL, x)
+#define crc32_le(a, b, c) rg_crc32(a, b, c)
+#else
+//#define LOG_PRINTF(level, x...) printf(x)
+#define LOG_PRINTF(level, x...) {}
+#define IRAM_ATTR __always_inline
+#define crc32_le(a, b, c) (0)
+#endif
+
+#define MESSAGE_ERROR(x...) LOG_PRINTF(1, "!! " x)
+#define MESSAGE_WARN(x...)  LOG_PRINTF(2, " ! " x)
+#define MESSAGE_INFO(x...)  LOG_PRINTF(3, " * " x)
+#define MESSAGE_TRACE(tag, x...) LOG_PRINTF(4, " & (" tag ") " x)
+#if ENABLE_DEBUG
+#define MESSAGE_DEBUG(x...) LOG_PRINTF(4, " > " x)
+#else
+#define MESSAGE_DEBUG(x...) {}
+#endif
+
+#if ENABLE_SPR_TRACING
+#define TRACE_SPR(x...) MESSAGE_TRACE("SPR", x)
+#else
+#define TRACE_SPR(x...) {}
+#endif
+
+#if ENABLE_GFX_TRACING
+#define TRACE_GFX(x...) MESSAGE_TRACE("GFX", x)
+#else
+#define TRACE_GFX(x...) {}
+#endif
+
+#if ENABLE_IO_TRACING
+#define TRACE_IO(x...) MESSAGE_TRACE("IO", x)
+#else
+#define TRACE_IO(x...) {}
+#endif
+
+#if ENABLE_CPU_TRACING
+#define TRACE_CPU(x...) MESSAGE_TRACE("CPU", x)
+#else
+#define TRACE_CPU(x...) {}
+#endif
+
+#undef MIN
+#define MIN(a,b) ({__typeof__(a) _a = (a); __typeof__(b) _b = (b);_a < _b ? _a : _b; })
+#undef MAX
+#define MAX(a,b) ({__typeof__(a) _a = (a); __typeof__(b) _b = (b);_a > _b ? _a : _b; })
+
+#define JOY_A       0x01
+#define JOY_B       0x02
+#define JOY_SELECT  0x04
+#define JOY_RUN     0x08
+#define JOY_UP      0x10
+#define JOY_RIGHT   0x20
+#define JOY_DOWN    0x40
+#define JOY_LEFT    0x80
+
+// We need 16 bytes of scratch area on both side of each line. The 16 bytes can be shared by adjacent lines.
+// The buffer should look like [16 bytes] [line 1] [16 bytes] ... [16 bytes] [line 242] [16 bytes]
+#define XBUF_WIDTH 	(16 + 320 + 16)
+#define	XBUF_HEIGHT	(242 + 4)
+
+int LoadState(const char *name);
+int SaveState(const char *name);
+void ResetPCE(bool);
+void RunPCE(void);
+void ShutdownPCE();
+int InitPCE(int samplerate, bool stereo, const void *ROM, size_t fsize);
+// int LoadCard(const char *name);
+int LoadCard(const char *ROM, size_t size);
+void *PalettePCE(int bitdepth);
+
+extern uint8_t *osd_gfx_framebuffer(int width, int height);
+extern void osd_input_read(uint8_t joypads[8]);
+extern void osd_vsync(void);
diff --git a/MCUME_pico2/picopce/pce-go/pce.c b/MCUME_pico2/picopce/pce-go/pce.c
new file mode 100755
index 0000000..6b8a105
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/pce.c
@@ -0,0 +1,688 @@
+#pragma GCC optimize("Ofast")
+// pce.c - Machine emulation (Memory/IO/Timer)
+//
+#include <stdlib.h>
+#include <string.h>
+#include "pce-go.h"
+#include "pce.h"
+#include "gfx.h"
+
+// Global struct containing our emulated hardware status
+PCE_t PCE;
+
+// Memory Mapping
+uint8_t *PageR[8];
+uint8_t *PageW[8];
+
+static inline void timer_run(int cycles);
+
+/**
+  * Reset the hardware
+  **/
+void
+pce_reset(bool hard)
+{
+	memset(&PCE.VCE, 0, sizeof(PCE.VCE));
+	memset(&PCE.VDC, 0, sizeof(PCE.VDC));
+	memset(&PCE.PSG, 0, sizeof(PCE.PSG));
+	memset(&PCE.Timer, 0, sizeof(PCE.Timer));
+
+	if (hard) {
+		memset(PCE.RAM, 0, 0x2000);
+		memset(PCE.VRAM, 0, 0x10000);
+		memset(PCE.SPRAM, 0, 512);
+		memset(PCE.Palette, 0, 512);
+		memset(PCE.NULLRAM, 0xFF, 0x2000);
+	}
+
+	IO_VDC_REG[VPR].B.h = 0x0f;
+	IO_VDC_REG[VPR].B.l = 0x02;
+
+	PCE.SF2 = 0;
+	PCE.Timer.cycles_per_line = 113;
+	PCE.Cycles = 0;
+
+	// Reset sound generator values
+	for (int i = 0; i < PSG_CHANNELS; i++) {
+		PCE.PSG.chan[i].control = 0x80;
+	}
+
+	// Reset memory banking
+	pce_bank_set(7, 0x00);
+	pce_bank_set(6, 0x05);
+	pce_bank_set(5, 0x04);
+	pce_bank_set(4, 0x03);
+	pce_bank_set(3, 0x02);
+	pce_bank_set(2, 0x01);
+	pce_bank_set(1, 0xF8);
+	pce_bank_set(0, 0xFF);
+
+	// Reset CPU
+	h6280_reset();
+}
+
+
+/**
+  * Initialize the hardware
+  **/
+int
+pce_init(void)
+{
+	// memset(PCE.RAM, 0x00, sizeof PCE.RAM);
+	// memset(PCE.VRAM, 0x00, sizeof PCE.VRAM );
+	// memset(PCE.NULLRAM, 0x00, sizeof PCE.NULLRAM);
+	// PCE.RAM = malloc(0x2000);
+	// PCE.VRAM = malloc(0x10000);
+	// PCE.NULLRAM = malloc(0x2000);
+	PCE.IOAREA = PCE.NULLRAM + 4;
+	// PCE.MemoryMapR = calloc(256, sizeof(uint8_t *));
+	// PCE.MemoryMapW = calloc(256, sizeof(uint8_t *));
+
+	if (!PCE.RAM || !PCE.VRAM || !PCE.NULLRAM || !PCE.MemoryMapR || !PCE.MemoryMapW) {
+		pce_term();
+		return -1;
+	}
+
+	for (int i = 0; i < 0xFF; i++) {
+		PCE.MemoryMapR[i] = PCE.NULLRAM;
+		PCE.MemoryMapW[i] = PCE.NULLRAM;
+	}
+
+	PCE.MemoryMapR[0xF8] = PCE.RAM;
+	PCE.MemoryMapW[0xF8] = PCE.RAM;
+	PCE.MemoryMapR[0xFF] = PCE.IOAREA;
+	PCE.MemoryMapW[0xFF] = PCE.IOAREA;
+
+	// pce_reset();
+
+	return 0;
+}
+
+
+/**
+  * Terminate the hardware
+  **/
+void
+pce_term(void)
+{
+	// free(PCE.RAM);
+	// PCE.RAM = NULL;
+	// free(PCE.VRAM);
+	// PCE.VRAM = NULL;
+	// free(PCE.ExRAM);
+	// PCE.ExRAM = NULL;
+	// free(PCE.ROM);
+	// PCE.ROM = NULL;
+	// free(PCE.NULLRAM);
+	// PCE.NULLRAM = NULL;
+	// free(PCE.MemoryMapR);
+	// PCE.MemoryMapR = NULL;
+	// free(PCE.MemoryMapW);
+	// PCE.MemoryMapW = NULL;
+}
+
+
+/**
+  * Run emulation for one frame
+  **/
+void
+pce_run(void)
+{
+	// Handle pending video mode changes
+	if (PCE.VDC.mode_chg) {
+		PCE.VDC.screen_width = IO_VDC_SCREEN_WIDTH;
+		PCE.VDC.screen_height = IO_VDC_SCREEN_HEIGHT;
+		PCE.VDC.mode_chg = 0;
+	}
+	// Emulate!
+	for (PCE.Scanline = 0; PCE.Scanline < 263; ++PCE.Scanline) {
+		PCE.MaxCycles += PCE.Timer.cycles_per_line;
+		/*while (PCE.MaxCycles > 0) */ {
+			h6280_run(PCE.MaxCycles);
+			timer_run(PCE.Cycles);
+			PCE.MaxCycles -= PCE.Cycles;
+			PCE.Cycles = 0;
+		}
+		gfx_run();
+	}
+}
+
+
+/**
+ * Functions to access PCE hardware
+ **/
+
+static inline void
+timer_run(int cycles)
+{
+	PCE.Timer.cycles_counter -= PCE.Timer.cycles_per_line;
+
+	if (PCE.Timer.cycles_counter < 0) {
+		PCE.Timer.cycles_counter += CYCLES_PER_TIMER_TICK;
+		if (PCE.Timer.running) {
+			// Trigger when it underflows from 0
+			if (PCE.Timer.counter > 0x7F) {
+				PCE.Timer.counter = PCE.Timer.reload;
+				CPU.irq_lines |= INT_TIMER;
+			}
+			PCE.Timer.counter--;
+		}
+	}
+}
+
+
+static inline void
+cart_write(uint16_t A, uint8_t V)
+{
+	TRACE_IO("Cart Write %02x at %04x\n", V, A);
+
+	// SF2 Mapper
+	if (A >= 0xFFF0 && PCE.ROM_SIZE >= 0xC0)
+	{
+		if (PCE.SF2 != (A & 3))
+		{
+			PCE.SF2 = A & 3;
+			uint8_t *base = PCE.ROM_DATA + PCE.SF2 * (512 * 1024);
+			for (int i = 0x40; i < 0x80; i++)
+			{
+				PCE.MemoryMapR[i] = base + i * 0x2000;
+			}
+			for (int i = 0; i < 8; i++)
+			{
+				if (PCE.MMR[i] >= 0x40 && PCE.MMR[i] < 0x80)
+					pce_bank_set(i, PCE.MMR[i]);
+			}
+		}
+	}
+}
+
+
+inline uint8_t
+pce_readIO(uint16_t A)
+{
+	uint8_t ret = 0xFF; // Open Bus
+
+	// The last read value in 0800-017FF is read from the io buffer
+	if (A >= 0x800 && A < 0x1800)
+		ret = PCE.io_buffer;
+
+	switch (A & 0x1F00) {
+	case 0x0000:                /* VDC */
+		switch (A & 3) {
+		case 0:
+			ret = PCE.VDC.status;
+			PCE.VDC.status = 0;
+			break;
+		case 1:
+			ret = 0;
+			break;
+		case 2:
+			if (PCE.VDC.reg == VRR) {             // // VRAM Read Register (LSB)
+				ret = PCE.VRAM[IO_VDC_REG[MARR].W & 0x7FFF] & 0xFF;
+			} else {
+				ret = IO_VDC_REG_ACTIVE.B.l;
+			}
+			break;
+		case 3:
+			if (PCE.VDC.reg == VRR) {            // VRAM Read Register (MSB)
+				ret = PCE.VRAM[IO_VDC_REG[MARR].W & 0x7FFF] >> 8;
+				IO_VDC_REG_INC(MARR);
+			} else {
+				ret = IO_VDC_REG_ACTIVE.B.h;
+			}
+			break;
+		}
+		break;
+
+	case 0x0400:                /* VCE */
+		switch (A & 7) {
+		case 0: ret = 0xFF; break; // Write only
+		case 1: ret = 0xFF; break; // Unused
+		case 2: ret = 0xFF; break; // Write only
+		case 3: ret = 0xFF; break; // Write only
+		case 4: ret = PCE.VCE.regs[PCE.VCE.reg].B.l; break; // Color LSB (8 bit)
+		case 5: {
+			ret = (PCE.VCE.regs[PCE.VCE.reg++].B.h) | 0xFE; // Color MSB (1 bit)
+			PCE.VCE.reg &= 0x1FF;
+			break;
+		}
+		case 6: ret = 0xFF; break; // Unused
+		}
+		break;
+
+	case 0x0800:                /* PSG */
+		switch (A & 15) {
+		case 0: ret = PCE.PSG.ch; break;
+		case 1: ret = PCE.PSG.volume; break;
+		case 2: ret = PCE.PSG.chan[PCE.PSG.ch].freq_lsb; break;
+		case 3: ret = PCE.PSG.chan[PCE.PSG.ch].freq_msb; break;
+		case 4: ret = PCE.PSG.chan[PCE.PSG.ch].control; break;
+		case 5: ret = PCE.PSG.chan[PCE.PSG.ch].balance; break;
+		case 6: ret = PCE.PSG.chan[PCE.PSG.ch].wave_index; break;
+		case 7: ret = PCE.PSG.chan[PCE.PSG.ch].noise_ctrl; break;
+		case 8: ret = PCE.PSG.lfo_freq; break;
+		case 9: ret = PCE.PSG.lfo_ctrl; break;
+		}
+		break;
+
+	case 0x0C00:                /* Timer */
+		ret = (PCE.io_buffer & 0x80);
+		if (PCE.Timer.cycles_counter == PCE.Cycles)
+			ret |= (PCE.Timer.counter - 1) & 0x7F;
+		else
+			ret |= PCE.Timer.counter;
+		break;
+
+	case 0x1000:                /* Joypad */
+		ret = PCE.Joypad.regs[PCE.Joypad.counter] ^ 0xff;
+		if (PCE.Joypad.nibble & 1)
+			ret >>= 4;
+		else {
+			ret &= 15;
+			PCE.Joypad.counter = ((PCE.Joypad.counter + 1) % 5);
+		}
+		ret |= 0x30; // those 2 bits are always on, bit 6 = 0 (Jap), bit 7 = 0 (Attached cd)
+		break;
+
+	case 0x1400:                /* IRQ */
+		switch (A & 3) {
+		case 2:
+			ret = CPU.irq_mask | (PCE.io_buffer & ~INT_MASK);
+			break;
+		case 3:
+			ret = CPU.irq_lines;
+			CPU.irq_lines = 0;
+			break;
+		}
+		break;
+
+	case 0x1A00:                // Arcade Card
+		MESSAGE_INFO("Arcade Card not supported : 0x%04X\n", A);
+		break;
+
+	case 0x1800:                // CD-ROM extention
+	case 0x18C0:                // Super System Card
+		MESSAGE_INFO("CD Emulation not implemented : 0x%04X\n", A);
+		break;
+	}
+
+	TRACE_IO("IO Read %02x at %04x\n", ret, A);
+
+	// The last read value in 0800-017FF is saved in the io buffer
+	if (A >= 0x800 && A < 0x1800)
+		PCE.io_buffer = ret;
+
+	return ret;
+}
+
+
+inline void
+pce_writeIO(uint16_t A, uint8_t V)
+{
+	TRACE_IO("IO Write %02x at %04x\n", V, A);
+
+	// The last write value in 0800-017FF is saved in the io buffer
+	if (A >= 0x800 && A < 0x1800)
+		PCE.io_buffer = V;
+
+	switch (A & 0x1F00) {
+	case 0x0000:                /* VDC */
+		switch (A & 3) {
+		case 0: // Latch
+			PCE.VDC.reg = V & 31;
+			return;
+
+		case 1: // Not used
+			return;
+
+		case 2: // VDC data (LSB)
+			switch (PCE.VDC.reg & 31) {
+			case MAWR:                          // Memory Address Write Register
+				break;
+
+			case MARR:                          // Memory Address Read Register
+				break;
+
+			case VWR:                           // VRAM Write Register
+				break;
+
+			case vdc3:                          // Unused
+				break;
+
+			case vdc4:                          // Unused
+				break;
+
+			case CR:                            // Control Register
+				if (IO_VDC_REG_ACTIVE.B.l != V)
+					gfx_latch_context(0);
+				break;
+
+			case RCR:                           // Raster Compare Register
+				break;
+
+			case BXR:
+				if (IO_VDC_REG_ACTIVE.B.l != V)
+					gfx_latch_context(0);
+				break;
+
+			case BYR:                           // Vertical screen offset
+				/*
+					if (IO_VDC_REG[BYR].B.l == V)
+					return;
+					*/
+				gfx_latch_context(0);
+				PCE.ScrollYDiff = PCE.Scanline - 1 - IO_VDC_MINLINE;
+				break;
+
+			case MWR:                           // Memory Width Register
+				break;
+
+			case HSR:
+				V = 0x1F;
+				PCE.VDC.mode_chg = 1;
+				break;
+
+			case HDR:                           // Horizontal Definition
+				V &= 0x7F;
+				PCE.VDC.mode_chg = 1;
+				break;
+
+			case VPR:
+				V &= 0x1F;
+				PCE.VDC.mode_chg = 1;
+				break;
+			case VDW:
+			case VCR:
+				PCE.VDC.mode_chg = 1;
+				break;
+
+			case DCR:                           // DMA Control
+				break;
+
+			case SOUR:                          // DMA source address
+				break;
+
+			case DISTR:                         // DMA destination address
+				break;
+
+			case LENR:                          // DMA transfer from VRAM to VRAM
+				break;
+
+			case SATB:                          // DMA from VRAM to SATB
+				break;
+			}
+			IO_VDC_REG_ACTIVE.B.l = V;
+			TRACE_GFX("VDC[%02x].l=0x%02x\n", PCE.VDC.reg, V);
+			return;
+
+		case 3: // VDC data (MSB)
+			switch (PCE.VDC.reg & 31) {
+			case MAWR:                          // Memory Address Write Register
+				break;
+
+			case MARR:                          // Memory Address Read Register
+				break;
+
+			case VWR:                           // VRAM Write Register
+				// I am not 100% sure if MAWR should wrap instead, eg IO_VDC_REG[MAWR].W & 0x7FFF
+				if (IO_VDC_REG[MAWR].W < 0x8000) {
+					PCE.VRAM[IO_VDC_REG[MAWR].W] = (V << 8) | IO_VDC_REG_ACTIVE.B.l;
+				}
+				IO_VDC_REG_INC(MAWR);
+				break;
+
+			case vdc3:                          // Unused
+				break;
+
+			case vdc4:                          // Unused
+				break;
+
+			case CR:                            // Control Register
+				if (IO_VDC_REG_ACTIVE.B.h != V)
+					gfx_latch_context(0);
+				break;
+
+			case RCR:                           // Raster Compare Register
+				V &= 0x3;
+				break;
+
+			case BXR:                           // Horizontal screen offset
+				V &= 0x3;
+				if (IO_VDC_REG_ACTIVE.B.h != V) {
+					gfx_latch_context(0);
+				}
+				break;
+
+			case BYR:                           // Vertical screen offset
+				gfx_latch_context(0);
+				V &= 0x1;
+				PCE.ScrollYDiff = PCE.Scanline - 1 - IO_VDC_MINLINE;
+				if (PCE.ScrollYDiff < 0) {
+					MESSAGE_DEBUG("PCE.ScrollYDiff went negative when substraction VPR.h/.l (%d,%d)\n",
+						IO_VDC_REG[VPR].B.h, IO_VDC_REG[VPR].B.l);
+				}
+				break;
+
+			case MWR:                           // Memory Width Register
+				break;
+
+			case HSR:
+				V &= 0x7F;
+				PCE.VDC.mode_chg = 1;
+				break;
+
+			case HDR:                           // Horizontal Definition
+				V &= 0x7F;
+				TRACE_GFX("VDC[HDR].h = %d\n", V);
+				break;
+
+			case VPR:
+				V &= 0x7F;
+				PCE.VDC.mode_chg = 1;
+				break;
+			case VDW:
+				V &= 0x1;
+				PCE.VDC.mode_chg = 1;
+				break;
+			case VCR:
+				PCE.VDC.mode_chg = 1;
+				return;//not interested in the MSB of VCR
+
+			case DCR:                           // DMA Control
+				break;
+
+			case SOUR:                          // DMA source address
+				break;
+
+			case DISTR:                         // DMA destination address
+				break;
+
+			case LENR:                          // DMA transfer from VRAM to VRAM
+				IO_VDC_REG[LENR].B.h = V;
+
+				int src_inc = (IO_VDC_REG[DCR].W & 8) ? -1 : 1;
+				int dst_inc = (IO_VDC_REG[DCR].W & 4) ? -1 : 1;
+
+				while (IO_VDC_REG[LENR].W != 0xFFFF) {
+					if (IO_VDC_REG[DISTR].W < 0x8000) {
+						PCE.VRAM[IO_VDC_REG[DISTR].W] = PCE.VRAM[IO_VDC_REG[SOUR].W];
+					}
+					IO_VDC_REG[SOUR].W += src_inc;
+					IO_VDC_REG[DISTR].W += dst_inc;
+					IO_VDC_REG[LENR].W -= 1;
+				}
+
+				gfx_irq(VDC_STAT_DV);
+				return;
+
+			case SATB:                          // DMA from VRAM to SATB
+				PCE.VDC.satb = DMA_TRANSFER_PENDING;
+				break;
+			}
+			IO_VDC_REG_ACTIVE.B.h = V;
+			TRACE_GFX("VDC[%02x].h=0x%02x\n", PCE.VDC.reg, V);
+			return;
+		}
+		break;
+
+	case 0x0400:                /* VCE */
+		switch (A & 7) {
+		case 0:                                 // VCE control
+			return;
+
+		case 1:                                 // Not used
+			return;
+
+		case 2:                                 // Color table address (LSB)
+			PCE.VCE.reg &= 0x100;
+			PCE.VCE.reg |= V;
+			return;
+
+		case 3:                                 // Color table address (MSB)
+			PCE.VCE.reg &= 0xFF;
+            PCE.VCE.reg |= (V & 1) << 8;
+			return;
+
+		case 4:                                 // Color table data (LSB)
+			PCE.VCE.regs[PCE.VCE.reg].B.l = V;
+			{
+				size_t n = PCE.VCE.reg;
+				size_t c = PCE.VCE.regs[n].W >> 1;
+				if (n == 0) {
+					for (int i = 0; i < 256; i += 16)
+						PCE.Palette[i] = c;
+				} else if (n & 15)
+					PCE.Palette[n] = c;
+			}
+			return;
+
+		case 5:                                 // Color table data (MSB)
+			PCE.VCE.regs[PCE.VCE.reg].B.h = V;
+			{
+				size_t n = PCE.VCE.reg;
+				size_t c = PCE.VCE.regs[n].W >> 1;
+				if (n == 0) {
+					for (int i = 0; i < 256; i += 16)
+						PCE.Palette[i] = c;
+				} else if (n & 15)
+					PCE.Palette[n] = c;
+			}
+			PCE.VCE.reg = (PCE.VCE.reg + 1) & 0x1FF;
+			return;
+
+		case 6:                                 // Not used
+			return;
+
+		case 7:                                 // Not used
+			return;
+		}
+		break;
+
+	case 0x0800:                /* PSG */
+		switch (A & 15) {
+		case 0:                                 // Select PSG channel
+			PCE.PSG.ch = MIN(V & 7, 5);
+			return;
+
+		case 1:                                 // Select global volume
+			PCE.PSG.volume = V;
+			return;
+
+		case 2:                                 // Frequency setting, 8 lower bits
+			PCE.PSG.chan[PCE.PSG.ch].freq_lsb = V;
+			return;
+
+		case 3:                                 // Frequency setting, 4 upper bits
+			PCE.PSG.chan[PCE.PSG.ch].freq_msb = V & 0xF;
+			return;
+
+		case 4:
+			if ((V & 0xC0) == (PSG_DDA_ENABLE)) {
+				PCE.PSG.chan[PCE.PSG.ch].wave_index = 0; // Reset wave index pointer
+			}
+
+			PCE.PSG.chan[PCE.PSG.ch].control = V;
+			return;
+
+		case 5:                                 // Set channel specific volume
+			PCE.PSG.chan[PCE.PSG.ch].balance = V;
+			return;
+
+		case 6:                                 // Put a value into the waveform or direct audio buffers
+			switch (PCE.PSG.chan[PCE.PSG.ch].control & 0xC0)
+			{
+			case 0: // Write to the wave buffer and increment the counter
+				PCE.PSG.chan[PCE.PSG.ch].wave_data[PCE.PSG.chan[PCE.PSG.ch].wave_index] = V & 0x1F;
+				PCE.PSG.chan[PCE.PSG.ch].wave_index++; // Inc pointer
+				PCE.PSG.chan[PCE.PSG.ch].wave_index &= 0x1F; // Wrap at 32
+				break;
+			case PSG_CHAN_ENABLE|PSG_DDA_ENABLE: // Update DDA sample
+				PCE.PSG.chan[PCE.PSG.ch].dda_data[PCE.PSG.chan[PCE.PSG.ch].dda_index] = V & 0x1F;
+				PCE.PSG.chan[PCE.PSG.ch].dda_count = MIN(PCE.PSG.chan[PCE.PSG.ch].dda_count+1, 0x100);
+				PCE.PSG.chan[PCE.PSG.ch].dda_index = (PCE.PSG.chan[PCE.PSG.ch].dda_index+1) & 0xFF;
+				break;
+			}
+			return;
+
+		case 7:
+			PCE.PSG.chan[PCE.PSG.ch].noise_ctrl = V;
+			return;
+
+		case 8:
+			PCE.PSG.lfo_freq = V;
+			return;
+
+		case 9:
+			PCE.PSG.lfo_ctrl = V;
+			return;
+		}
+		break;
+
+	case 0x0C00:                /* Timer */
+		switch (A & 1) {
+		case 0:
+			PCE.Timer.reload = (V & 0x7F); // + 1;
+			return;
+		case 1:
+			V &= 1;
+            if (V && !PCE.Timer.running){
+                // PCE.Timer.cycles_counter = PCE.Cycles + CYCLES_PER_TIMER_TICK;
+				PCE.Timer.counter = PCE.Timer.reload;
+            }
+			PCE.Timer.running = V;
+			return;
+		}
+		break;
+
+	case 0x1000:                /* Joypad */
+		PCE.Joypad.nibble = V & 1;
+		if (V & 2)
+			PCE.Joypad.counter = 0;
+		return;
+
+	case 0x1400:                /* IRQ */
+		switch (A & 3) {
+		case 2:
+			CPU.irq_mask = V & INT_MASK;
+			return;
+		case 3:
+			CPU.irq_lines &= ~INT_TIMER;
+			return;
+		}
+		break;
+
+	case 0x1A00:                /* Arcade Card */
+		MESSAGE_INFO("Arcade Card not supported : %d into 0x%04X\n", V, A);
+		return;
+
+	case 0x1800:                /* CD-ROM extention */
+		MESSAGE_INFO("CD Emulation not implemented : %d 0x%04X\n", V, A);
+		return;
+
+	case 0x1F00:                /* Street Fighter 2 Mapper */
+		cart_write(A, V);
+		return;
+	}
+
+	MESSAGE_DEBUG("ignored I/O write: %04x,%02x at PC = %04X\n", A, V, CPU.PC);
+}
diff --git a/MCUME_pico2/picopce/pce-go/pce.h b/MCUME_pico2/picopce/pce-go/pce.h
new file mode 100755
index 0000000..675462f
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/pce.h
@@ -0,0 +1,352 @@
+#pragma once
+
+#include "pce-go.h"
+
+// System clocks (hz)
+#define CLOCK_MASTER           (21477270)
+#define CLOCK_TIMER            (CLOCK_MASTER / 3)
+#define CLOCK_CPU              (CLOCK_MASTER / 3)
+#define CLOCK_PSG              (CLOCK_MASTER / 6)
+
+// Timings (we don't support CSH/CSL yet...)
+#define CYCLES_PER_FRAME       (CLOCK_CPU / 60)
+#define CYCLES_PER_LINE        (CYCLES_PER_FRAME / 263 + 1)
+#define CYCLES_PER_TIMER_TICK  (1024) // 1097
+//#define CYCLES_PER_TIMER_TICK  (1097)
+
+typedef struct __attribute__((packed))
+{
+	uint16_t y; 	/* Vertical position */
+	uint16_t x; 	/* Horizontal position */
+	uint16_t no;   	/* Offset in VRAM */
+	uint16_t attr; 	/* Attributes */
+	/*
+		* bit 0-4 : number of the palette to be used
+		* bit 7 : background sprite
+		*          0 -> must be drawn behind tiles
+		*          1 -> must be drawn in front of tiles
+		* bit 8 : width
+		*          0 -> 16 pixels
+		*          1 -> 32 pixels
+		* bit 11 : horizontal flip
+		*          0 -> normal shape
+		*          1 -> must be draw horizontally flipped
+		* bit 13-12 : height
+		*          00 -> 16 pixels
+		*          01 -> 32 pixels
+		*          10 -> 48 pixels
+		*          11 -> 64 pixels
+		* bit 15 : vertical flip
+		*          0 -> normal shape
+		*          1 -> must be drawn vertically flipped
+	*/
+} sprite_t;
+
+// VDC Status Flags (vdc_status bit)
+typedef enum {
+	VDC_STAT_CR  = 0,	/* Sprite Collision */
+	VDC_STAT_OR  = 1,	/* Sprite Overflow */
+	VDC_STAT_RR  = 2,	/* Scanline interrupt */
+	VDC_STAT_DS  = 3,	/* End of VRAM to SATB DMA transfer */
+	VDC_STAT_DV  = 4,	/* End of VRAM to VRAM DMA transfer */
+	VDC_STAT_VD  = 5,	/* VBlank */
+	VDC_STAT_BSY = 6,	/* DMA Transfer in progress */
+} vdc_stat_t;
+
+// VDC Registers
+typedef enum {
+	MAWR 	= 0,		/* Memory Address Write Register */
+	MARR 	= 1,		/* Memory Address Read Register */
+	VRR 	= 2,		/* VRAM Read Register */
+	VWR 	= 2,		/* VRAM Write Register */
+	vdc3 	= 3,		/* Unused */
+	vdc4 	= 4,		/* Unused */
+	CR 		= 5,		/* Control Register */
+	RCR 	= 6,		/* Raster Compare Register */
+	BXR 	= 7,		/* Horizontal scroll offset */
+	BYR 	= 8,		/* Vertical scroll offset */
+	MWR 	= 9,		/* Memory Width Register */
+	HSR 	= 10,		/* Unknown, other horizontal definition */
+	HDR 	= 11,		/* Horizontal Definition */
+	VPR 	= 12,		/* Higher byte = VDS, lower byte = VSW */
+	VDW 	= 13,		/* Vertical Definition */
+	VCR 	= 14,		/* Vertical counter between restarting of display */
+	DCR 	= 15,		/* DMA Control */
+	SOUR 	= 16,		/* Source Address of DMA transfert */
+	DISTR 	= 17,		/* Destination Address of DMA transfert */
+	LENR 	= 18,		/* Length of DMA transfert */
+	SATB 	= 19		/* Address of SATB */
+} vdc_reg_t;
+
+#define PSG_CHAN_ENABLE         0x80 // bit 7
+#define PSG_DDA_ENABLE          0x40 // bit 6
+#define PSG_CHAN_VOLUME         0x1F // bits 0-4
+#define PSG_BALANCE_LEFT        0xF0 // bits 4-7
+#define PSG_BALANCE_RIGHT       0x0F // bits 0-3
+#define PSG_NOISE_ENABLE        0x80 // bit 7
+
+#define PSG_CHANNELS            6
+
+
+#include "h6280.h"
+
+
+typedef union {
+	struct {
+		uint8_t l, h;
+	} B;
+	uint16_t W;
+} UWord;
+
+typedef struct {
+	uint8_t freq_lsb;   // 2
+	uint8_t freq_msb;   // 3
+	uint8_t control;    // 4
+	uint8_t balance;    // 5
+	uint8_t wave_index; // 6
+	uint8_t noise_ctrl; // 7
+	uint8_t pad0, pad1;
+
+	uint8_t wave_data[32];
+	uint8_t dda_data[256];
+
+	uint32_t dda_count;
+	uint32_t dda_index;
+
+	uint32_t wave_accum;
+
+	int32_t noise_accum;
+	int32_t noise_level;
+	int32_t noise_rand;
+} psg_chan_t;
+
+typedef struct {
+	// Main memory
+	uint8_t RAM[0x2000];
+
+	// Video RAM
+	uint16_t VRAM[0x8000];
+
+	// Sprite RAM
+	sprite_t SPRAM[64];
+
+	// Extra RAM contained on the HuCard (Populous)
+	uint8_t ExRAM[0x8000];
+
+	// ROM memory
+	uint8_t *ROM, *ROM_DATA;
+
+	// ROM size in 0x2000 blocks
+	uint16_t ROM_SIZE;
+
+	// ROM crc
+	uint32_t ROM_CRC;
+
+	// For performance reasons we trap read/writes to unmapped areas:
+	uint8_t *IOAREA;
+	uint8_t NULLRAM[0x2000];
+
+	// PCE->PC Palette convetion array
+	// Each of the 512 available PCE colors (333 RGB -> 512 colors)
+	// got a correspondance in the 256 fixed colors palette
+	uint8_t Palette[512];
+
+	// The current rendered line on screen
+	int32_t Scanline;
+
+	//
+	int ScrollYDiff;
+
+	// Number of executed CPU cycles
+	int32_t Cycles;
+
+	// Run CPU until Cycles >= MaxCycles
+	int32_t MaxCycles;
+
+	// Value of each of the MMR registers
+	uint8_t MMR[8];
+
+	// Effective memory map
+	uint8_t *MemoryMapR[256];
+	uint8_t *MemoryMapW[256];
+
+	// Street Fighter 2 Mapper
+	uint8_t SF2;
+
+	// Remanence latch
+	uint8_t io_buffer;
+
+	// Timer
+	struct {
+		int32_t cycles_per_line;
+		int32_t cycles_counter;
+		uint32_t counter;
+		uint32_t reload;
+		uint32_t running;
+	} Timer;
+
+	// Joypad
+	struct {
+		uint8_t regs[8];		/* value of pressed button/direct for each pad */
+		uint8_t nibble;			/* used to know what nibble we must return */
+		uint8_t counter;		/* current addressed joypad */
+	} Joypad;
+
+	// Video Color Encoder
+	struct {
+		UWord regs[0x200];		/* palette info */
+		size_t reg;				/* currently selected color */
+	} VCE;
+
+	// Video Display Controller
+	struct {
+		UWord regs[32];			/* value of each VDC register */
+		size_t reg;				/* currently selected VDC register */
+		uint8_t status;			/* current VCD status (end of line, end of screen, ...) */
+		uint8_t vram;			/* VRAM DMA transfer status to happen in vblank */
+		uint8_t satb;			/* DMA transfer status to happen in vblank */
+		uint8_t mode_chg;       /* Video mode change needed at next frame */
+		uint32_t pending_irqs;	/* Pending VDC IRQs (we use it as a stack of 4bit events) */
+		uint32_t screen_width;	/* Effective resolution updated by mode_chg */
+		uint32_t screen_height;	/* Effective resolution updated by mode_chg */
+	} VDC;
+
+	// Programmable Sound Generator
+	struct {
+		uint8_t ch;             // reg 0
+		uint8_t volume;         // reg 1
+		uint8_t lfo_freq;       // reg 8
+		uint8_t lfo_ctrl;       // reg 9
+		psg_chan_t chan[PSG_CHANNELS]; // regs 2-7
+		uint8_t padding[16];
+	} PSG;
+
+	// Main Processor H6280
+	h6280_t CPU;
+
+} PCE_t;
+
+// The global structure for all hardware variables
+extern PCE_t PCE;
+#define CPU PCE.CPU
+
+// physical address on emulator machine of each of the 256 banks
+extern uint8_t *PageR[8];
+extern uint8_t *PageW[8];
+
+#define IO_VDC_REG           PCE.VDC.regs
+#define IO_VDC_REG_ACTIVE    PCE.VDC.regs[PCE.VDC.reg]
+#define IO_VDC_REG_INC(reg)  {unsigned _i[] = {1,32,64,128}; PCE.VDC.regs[(reg)].W += _i[(PCE.VDC.regs[CR].W >> 11) & 3];}
+#define IO_VDC_STATUS(bit)   ((PCE.VDC.status >> bit) & 1)
+#define IO_VDC_MINLINE       (IO_VDC_REG[VPR].B.h + IO_VDC_REG[VPR].B.l)
+#define IO_VDC_MAXLINE       (IO_VDC_MINLINE + IO_VDC_REG[VDW].W)
+#define IO_VDC_SCREEN_WIDTH  ((IO_VDC_REG[HDR].B.l + 1) * 8)
+#define IO_VDC_SCREEN_HEIGHT (IO_VDC_REG[VDW].W + 1)
+
+// Interrupt enabled
+#define SATBIntON  (IO_VDC_REG[DCR].W & 0x01)
+#define DMAIntON   (IO_VDC_REG[DCR].W & 0x02)
+#define AutoSATBON (IO_VDC_REG[DCR].W & 0x10)
+#define SpHitON    (IO_VDC_REG[CR].W & 0x01)
+#define OverON     (IO_VDC_REG[CR].W & 0x02)
+#define RasHitON   (IO_VDC_REG[CR].W & 0x04)
+#define VBlankON   (IO_VDC_REG[CR].W & 0x08)
+
+#define SpriteON   (IO_VDC_REG[CR].W & 0x40)
+#define ScreenON   (IO_VDC_REG[CR].W & 0x80)
+#define BurstMode  (IO_VDC_REG[CR].W & 0x0C)
+
+#define DMA_TRANSFER_COUNTER 0x80
+#define DMA_TRANSFER_PENDING 0x40
+
+/**
+ * Exported Functions
+ */
+
+int  pce_init(void);
+void pce_reset(bool hard);
+void pce_term(void);
+void pce_run(void);
+void pce_pause(void);
+void pce_writeIO(uint16_t A, uint8_t V);
+uint8_t pce_readIO(uint16_t A);
+
+
+/**
+ * Inlined Functions
+ */
+
+#if USE_MEM_MACROS
+
+#define pce_read8(addr) ({							\
+	uint16_t a = (addr); 							\
+	uint8_t *page = PageR[a >> 13]; 				\
+	(page == PCE.IOAREA) ? pce_readIO(a) : page[a]; \
+})
+
+#define pce_write8(addr, byte) {					\
+	uint16_t a = (addr), b = (byte); 				\
+	uint8_t *page = PageW[a >> 13]; 				\
+	if (page == PCE.IOAREA) pce_writeIO(a, b); 		\
+	else page[a] = b;								\
+}
+
+#define pce_read16(addr) ({ \
+    uint8_t *page = PageR[addr >> 13];  \
+    page[addr] | (page[addr+1] << 8);   \
+})
+
+#define pce_write161(addr, word) {					\
+	uint16_t a = (addr), w = (word); 				\
+	*((uint16_t*)(PageW[a >> 13] + a)) = w;			\
+}
+
+#else
+
+static inline uint8_t
+pce_read8(uint16_t addr)
+{
+	uint8_t *page = PageR[addr >> 13];
+
+	if (page == PCE.IOAREA)
+		return pce_readIO(addr);
+	else
+		return page[addr];
+}
+
+static inline void
+pce_write8(uint16_t addr, uint8_t byte)
+{
+	uint8_t *page = PageW[addr >> 13];
+
+	if (page == PCE.IOAREA)
+		pce_writeIO(addr, byte);
+	else
+		page[addr] = byte;
+}
+
+static inline uint16_t
+pce_read16(uint16_t addr)
+{
+    uint8_t *page = PageR[addr >> 13];
+    return page[addr] | (page[addr+1] << 8);
+}
+
+static inline void
+pce_write16(uint16_t addr, uint16_t word)
+{
+	*((uint16_t*)(PageW[addr >> 13] + (addr))) = word;
+}
+
+#endif
+
+
+static inline void
+pce_bank_set(uint8_t P, uint8_t V)
+{
+	//TRACE_IO("Bank switching (MMR[%d] = %d)\n", P, V);
+
+	PCE.MMR[P] = V;
+	PageR[P] = (PCE.MemoryMapR[V] == PCE.IOAREA) ? (PCE.IOAREA) : (PCE.MemoryMapR[V] - P * 0x2000);
+	PageW[P] = (PCE.MemoryMapW[V] == PCE.IOAREA) ? (PCE.IOAREA) : (PCE.MemoryMapW[V] - P * 0x2000);
+}
diff --git a/MCUME_pico2/picopce/pce-go/psg.c b/MCUME_pico2/picopce/pce-go/psg.c
new file mode 100755
index 0000000..e7c19fb
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/psg.c
@@ -0,0 +1,223 @@
+// psg.c - Programmable Sound Generator
+//
+#pragma GCC optimize("Ofast")
+#include "pico.h"
+#include <stdlib.h>
+#include <string.h>
+#include "pce.h"
+#include "psg.h"
+
+static const uint8_t vol_tbl[32] = {
+	100 >> 8, 451 >> 8, 508 >> 8, 573 >> 8, 646 >> 8, 728 >> 8, 821 >> 8, 925 >> 8,
+	1043 >> 8, 1175 >> 8, 1325 >> 8, 1493 >> 8, 1683 >> 8, 1898 >> 8, 2139 >> 8, 2411 >> 8,
+	2718 >> 8, 3064 >> 8, 3454 >> 8, 3893 >> 8, 4388 >> 8, 4947 >> 8, 5576 >> 8, 6285 >> 8,
+	7085 >> 8, 7986 >> 8, 9002 >> 8, 10148 >> 8, 11439 >> 8, 12894 >> 8, 14535 >> 8, 16384 >> 8
+};
+
+// The buffer should be signed but it seems to sound better
+// unsigned. I am still reviewing the implementation bellow.
+// In some games it also sounds better in 8 bit than in 16...
+// typedef uint8_t sample_t;
+typedef int16_t sample_t;
+
+static int samplerate = 22050;
+static int stereo = true;
+
+
+static inline void
+psg_update_chan(sample_t *buf, int ch, size_t dwSize)
+{
+	psg_chan_t *chan = &PCE.PSG.chan[ch];
+	int sample = 0;
+	uint32_t Tp;
+	sample_t *buf_end = buf + dwSize;
+
+	/*
+	* This gives us a volume level of (0...15).
+	*/
+	int lvol = (((chan->balance >> 4) * 1.1) * (chan->control & 0x1F)) / 32;
+	int rvol = (((chan->balance & 0xF) * 1.1) * (chan->control & 0x1F)) / 32;
+
+	if (!stereo) {
+		lvol = (lvol + rvol) / 2;
+	}
+
+	// This isn't very accurate, we don't track how long each DA sample should play
+	// but we call psg_update() often enough (10x per frame) that guessing should be good enough...
+	if (chan->dda_count) {
+		// Cycles per frame: 119318
+		// Samples per frame: 368
+
+		// Cycles per scanline: 454
+		// Samples per scanline: ~1.4
+
+		// One sample = 324 cycles
+
+		// const int cycles_per_sample = CYCLES_PER_FRAME / (host.sound.sample_freq / 60);
+
+		// float repeat = (float)elapsed / cycles_per_sample / chan->dda_count;
+		// MESSAGE_INFO("%.2f\n", repeat);
+
+		int start = (int)chan->dda_index - chan->dda_count;
+		if (start < 0)
+			start += 0x100;
+
+		int repeat = 3; // MIN(2, (dwSize / 2) / chan->dda_count) + 1;
+
+		lvol = vol_tbl[lvol << 1];
+		rvol = vol_tbl[rvol << 1];
+
+		while (buf < buf_end && (chan->dda_count || chan->control & PSG_DDA_ENABLE)) {
+			if (chan->dda_count) {
+				// sample = chan->dda_data[(start++) & 0x7F];
+				if ((sample = (chan->dda_data[(start++) & 0xFF] - 16)) >= 0)
+					sample++;
+				chan->dda_count--;
+			}
+
+			for (int i = 0; i < repeat; i++) {
+				*buf++ = (sample * lvol);
+
+				if (stereo) {
+					*buf++ = (sample * rvol);
+				}
+			}
+		}
+	}
+
+	/*
+	* Do nothing if there is no audio to be played on this channel.
+	*/
+	if (!(chan->control & PSG_CHAN_ENABLE)) {
+		chan->wave_accum = 0;
+	}
+	/*
+	* PSG Noise generation (it has priority over DDA and WAVE)
+	*/
+	else if ((ch == 4 || ch == 5) && (chan->noise_ctrl & PSG_NOISE_ENABLE)) {
+		int Np = (chan->noise_ctrl & 0x1F);
+
+		while (buf < buf_end) {
+			chan->noise_accum += 3000 + Np * 512;
+
+			if ((Tp = (chan->noise_accum / samplerate)) >= 1) {
+				if (chan->noise_rand & 0x00080000) {
+					chan->noise_rand = ((chan->noise_rand ^ 0x0004) << 1) + 1;
+					chan->noise_level = -15;
+				} else {
+					chan->noise_rand <<= 1;
+					chan->noise_level = 15;
+				}
+				chan->noise_accum -= samplerate * Tp;
+			}
+
+			*buf++ = (chan->noise_level * lvol);
+
+			if (stereo) {
+				*buf++ = (chan->noise_level * rvol);
+			}
+		}
+	}
+	/*
+	* There is 'direct access' audio to be played.
+	*/
+	else if (chan->control & PSG_DDA_ENABLE) {
+
+	}
+	/*
+	* PSG Wave generation.
+	*/
+	else if ((Tp = chan->freq_lsb + (chan->freq_msb << 8)) > 0) {
+		/*
+		 * Thank god for well commented code!  The original line of code read:
+		 * fixed_inc = ((uint32_t) (3.2 * 1118608 / samplerate) << 16) / Tp;
+		 * and had nary a comment to be found.  It took a little head scratching to get
+		 * it figured out.  The 3.2 * 1118608 comes out to 3574595.6 which is obviously
+		 * meant to represent the 3.58mhz cpu clock speed used in the pc engine to
+		 * decrement the sound 'frequency'.  I haven't figured out why the original
+		 * author had the two numbers multiplied together to get the odd value instead of
+		 * just using 3580000.  I did some checking and the value will compute the same
+		 * using either value divided by any standard soundcard samplerate.
+		 *
+		 * Taken from the PSG doc written by Paul Clifford (paul@plasma.demon.co.uk)
+		 * <in reference to the 12 bit frequency value in PSG registers 2 and 3>
+		 * "For waveform output, a copy of this value is, in effect, decremented 3,580,000
+		 *  times a second until zero is reached.  When this happens the PSG advances an
+		 *  internal pointer into the channel's waveform buffer by one."
+		 *
+		 * So all we need to do to emulate original pc engine behaviour is take our soundcard's
+		 * sampling rate into consideration with regard to the 3580000 effective pc engine
+		 * samplerate.  We use 16.16 fixed arithmetic for speed.
+		 */
+		uint32_t fixed_inc = ((CLOCK_PSG / samplerate) << 16) / Tp;
+
+		while (buf < buf_end) {
+			if ((sample = (chan->wave_data[chan->wave_index] - 16)) >= 0)
+				sample++;
+
+			*buf++ = (sample * lvol);
+
+			if (stereo) {
+				*buf++ = (sample * rvol);
+			}
+
+			chan->wave_accum += fixed_inc;
+			chan->wave_accum &= 0x1FFFFF;	/* (31 << 16) + 0xFFFF */
+			chan->wave_index = chan->wave_accum >> 16;
+		}
+	}
+
+	if (buf < buf_end) {
+		memset(buf, 0, (void*)buf_end - (void*)buf);
+	}
+}
+
+
+int
+psg_init(int _samplerate, bool _stereo)
+{
+	PCE.PSG.chan[4].noise_rand = 0x51F63101;
+	PCE.PSG.chan[5].noise_rand = 0x1F631042;
+
+	samplerate = _samplerate;
+	stereo = _stereo;
+
+	return 0;
+}
+
+
+void
+psg_term(void)
+{
+	//
+}
+
+
+void
+__time_critical_func(psg_update)(int16_t *output, size_t length, uint32_t channels)
+{
+	int lvol = (PCE.PSG.volume >> 4);
+	int rvol = (PCE.PSG.volume & 0x0F);
+
+	if (stereo) {
+		length *= 2;
+	}
+
+	memset(output, 0, length * sizeof(int16_t));
+
+	for (int i = 0; i < PSG_CHANNELS; i++)
+	{
+		sample_t mix_buffer[length + 1];
+		psg_update_chan(mix_buffer, i, length);
+
+		// We still emulate disabled channel, we just don't mix them with the output
+		if (!(channels & (1 << i)))
+			continue;
+
+#pragma GCC unroll(32)
+		for (int j = 0; j < length; j += 2) {
+			output[j] += mix_buffer[j] * lvol;
+			output[j + 1] += mix_buffer[j + 1] * rvol;
+		}
+	}
+}
diff --git a/MCUME_pico2/picopce/pce-go/psg.h b/MCUME_pico2/picopce/pce-go/psg.h
new file mode 100755
index 0000000..d1cb3b5
--- /dev/null
+++ b/MCUME_pico2/picopce/pce-go/psg.h
@@ -0,0 +1,8 @@
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+
+int psg_init(int samplerate, bool stereo);
+void psg_term(void);
+void psg_update(int16_t *output, size_t length, uint32_t channels);
diff --git a/MCUME_pico2/picopce/picopce.cpp b/MCUME_pico2/picopce/picopce.cpp
new file mode 100644
index 0000000..b89a6c5
--- /dev/null
+++ b/MCUME_pico2/picopce/picopce.cpp
@@ -0,0 +1,189 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_20);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(240000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+
+     emu_init();
+ 
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picopce/program_config.h b/MCUME_pico2/picopce/program_config.h
new file mode 100644
index 0000000..ae30c2e
--- /dev/null
+++ b/MCUME_pico2/picopce/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define FLASH_STORE_START 0x100000  
+
+#endif
diff --git a/MCUME_pico2/picopceold/.DS_Store b/MCUME_pico2/picopceold/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/picopceold/.DS_Store differ
diff --git a/MCUME_pico2/picopceold/bitflip.h b/MCUME_pico2/picopceold/bitflip.h
new file mode 100644
index 0000000..6d2b3c3
--- /dev/null
+++ b/MCUME_pico2/picopceold/bitflip.h
@@ -0,0 +1,26 @@
+
+#ifndef _BITFLIP_H_
+#define _BITFLIP_H_
+
+const uint8 bitflip[0x100] =
+{
+	0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0, 0x10, 0x90, 0x50, 0xD0, 0x30, 0xB0, 0x70, 0xF0,
+	0x08, 0x88, 0x48, 0xC8, 0x28, 0xA8, 0x68, 0xE8, 0x18, 0x98, 0x58, 0xD8, 0x38, 0xB8, 0x78, 0xF8, 
+	0x04, 0x84, 0x44, 0xC4, 0x24, 0xA4, 0x64, 0xE4, 0x14, 0x94, 0x54, 0xD4, 0x34, 0xB4, 0x74, 0xF4, 
+	0x0C, 0x8C, 0x4C, 0xCC, 0x2C, 0xAC, 0x6C, 0xEC, 0x1C, 0x9C, 0x5C, 0xDC, 0x3C, 0xBC, 0x7C, 0xFC, 
+	0x02, 0x82, 0x42, 0xC2, 0x22, 0xA2, 0x62, 0xE2, 0x12, 0x92, 0x52, 0xD2, 0x32, 0xB2, 0x72, 0xF2, 
+	0x0A, 0x8A, 0x4A, 0xCA, 0x2A, 0xAA, 0x6A, 0xEA, 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA, 
+	0x06, 0x86, 0x46, 0xC6, 0x26, 0xA6, 0x66, 0xE6, 0x16, 0x96, 0x56, 0xD6, 0x36, 0xB6, 0x76, 0xF6, 
+	0x0E, 0x8E, 0x4E, 0xCE, 0x2E, 0xAE, 0x6E, 0xEE, 0x1E, 0x9E, 0x5E, 0xDE, 0x3E, 0xBE, 0x7E, 0xFE, 
+	0x01, 0x81, 0x41, 0xC1, 0x21, 0xA1, 0x61, 0xE1, 0x11, 0x91, 0x51, 0xD1, 0x31, 0xB1, 0x71, 0xF1, 
+	0x09, 0x89, 0x49, 0xC9, 0x29, 0xA9, 0x69, 0xE9, 0x19, 0x99, 0x59, 0xD9, 0x39, 0xB9, 0x79, 0xF9, 
+	0x05, 0x85, 0x45, 0xC5, 0x25, 0xA5, 0x65, 0xE5, 0x15, 0x95, 0x55, 0xD5, 0x35, 0xB5, 0x75, 0xF5, 
+	0x0D, 0x8D, 0x4D, 0xCD, 0x2D, 0xAD, 0x6D, 0xED, 0x1D, 0x9D, 0x5D, 0xDD, 0x3D, 0xBD, 0x7D, 0xFD, 
+	0x03, 0x83, 0x43, 0xC3, 0x23, 0xA3, 0x63, 0xE3, 0x13, 0x93, 0x53, 0xD3, 0x33, 0xB3, 0x73, 0xF3, 
+	0x0B, 0x8B, 0x4B, 0xCB, 0x2B, 0xAB, 0x6B, 0xEB, 0x1B, 0x9B, 0x5B, 0xDB, 0x3B, 0xBB, 0x7B, 0xFB, 
+	0x07, 0x87, 0x47, 0xC7, 0x27, 0xA7, 0x67, 0xE7, 0x17, 0x97, 0x57, 0xD7, 0x37, 0xB7, 0x77, 0xF7, 
+    0x0F, 0x8F, 0x4F, 0xCF, 0x2F, 0xAF, 0x6F, 0xEF, 0x1F, 0x9F, 0x5F, 0xDF, 0x3F, 0xBF, 0x7F, 0xFF, 
+};
+
+#endif /* _BITFLIP_H_ */
+
diff --git a/MCUME_pico2/picopceold/bp_lut.h b/MCUME_pico2/picopceold/bp_lut.h
new file mode 100644
index 0000000..8db9151
--- /dev/null
+++ b/MCUME_pico2/picopceold/bp_lut.h
@@ -0,0 +1,4098 @@
+const uint32 bp_lut[0x10000] = {
+0x00000000,0x40000000,0x04000000,0x44000000,0x00400000,0x40400000,0x04400000,0x44400000,0x00040000,0x40040000,0x04040000,0x44040000,0x00440000,0x40440000,0x04440000,0x44440000,
+0x00004000,0x40004000,0x04004000,0x44004000,0x00404000,0x40404000,0x04404000,0x44404000,0x00044000,0x40044000,0x04044000,0x44044000,0x00444000,0x40444000,0x04444000,0x44444000,
+0x00000400,0x40000400,0x04000400,0x44000400,0x00400400,0x40400400,0x04400400,0x44400400,0x00040400,0x40040400,0x04040400,0x44040400,0x00440400,0x40440400,0x04440400,0x44440400,
+0x00004400,0x40004400,0x04004400,0x44004400,0x00404400,0x40404400,0x04404400,0x44404400,0x00044400,0x40044400,0x04044400,0x44044400,0x00444400,0x40444400,0x04444400,0x44444400,
+0x00000040,0x40000040,0x04000040,0x44000040,0x00400040,0x40400040,0x04400040,0x44400040,0x00040040,0x40040040,0x04040040,0x44040040,0x00440040,0x40440040,0x04440040,0x44440040,
+0x00004040,0x40004040,0x04004040,0x44004040,0x00404040,0x40404040,0x04404040,0x44404040,0x00044040,0x40044040,0x04044040,0x44044040,0x00444040,0x40444040,0x04444040,0x44444040,
+0x00000440,0x40000440,0x04000440,0x44000440,0x00400440,0x40400440,0x04400440,0x44400440,0x00040440,0x40040440,0x04040440,0x44040440,0x00440440,0x40440440,0x04440440,0x44440440,
+0x00004440,0x40004440,0x04004440,0x44004440,0x00404440,0x40404440,0x04404440,0x44404440,0x00044440,0x40044440,0x04044440,0x44044440,0x00444440,0x40444440,0x04444440,0x44444440,
+0x00000004,0x40000004,0x04000004,0x44000004,0x00400004,0x40400004,0x04400004,0x44400004,0x00040004,0x40040004,0x04040004,0x44040004,0x00440004,0x40440004,0x04440004,0x44440004,
+0x00004004,0x40004004,0x04004004,0x44004004,0x00404004,0x40404004,0x04404004,0x44404004,0x00044004,0x40044004,0x04044004,0x44044004,0x00444004,0x40444004,0x04444004,0x44444004,
+0x00000404,0x40000404,0x04000404,0x44000404,0x00400404,0x40400404,0x04400404,0x44400404,0x00040404,0x40040404,0x04040404,0x44040404,0x00440404,0x40440404,0x04440404,0x44440404,
+0x00004404,0x40004404,0x04004404,0x44004404,0x00404404,0x40404404,0x04404404,0x44404404,0x00044404,0x40044404,0x04044404,0x44044404,0x00444404,0x40444404,0x04444404,0x44444404,
+0x00000044,0x40000044,0x04000044,0x44000044,0x00400044,0x40400044,0x04400044,0x44400044,0x00040044,0x40040044,0x04040044,0x44040044,0x00440044,0x40440044,0x04440044,0x44440044,
+0x00004044,0x40004044,0x04004044,0x44004044,0x00404044,0x40404044,0x04404044,0x44404044,0x00044044,0x40044044,0x04044044,0x44044044,0x00444044,0x40444044,0x04444044,0x44444044,
+0x00000444,0x40000444,0x04000444,0x44000444,0x00400444,0x40400444,0x04400444,0x44400444,0x00040444,0x40040444,0x04040444,0x44040444,0x00440444,0x40440444,0x04440444,0x44440444,
+0x00004444,0x40004444,0x04004444,0x44004444,0x00404444,0x40404444,0x04404444,0x44404444,0x00044444,0x40044444,0x04044444,0x44044444,0x00444444,0x40444444,0x04444444,0x44444444,
+0x80000000,0xC0000000,0x84000000,0xC4000000,0x80400000,0xC0400000,0x84400000,0xC4400000,0x80040000,0xC0040000,0x84040000,0xC4040000,0x80440000,0xC0440000,0x84440000,0xC4440000,
+0x80004000,0xC0004000,0x84004000,0xC4004000,0x80404000,0xC0404000,0x84404000,0xC4404000,0x80044000,0xC0044000,0x84044000,0xC4044000,0x80444000,0xC0444000,0x84444000,0xC4444000,
+0x80000400,0xC0000400,0x84000400,0xC4000400,0x80400400,0xC0400400,0x84400400,0xC4400400,0x80040400,0xC0040400,0x84040400,0xC4040400,0x80440400,0xC0440400,0x84440400,0xC4440400,
+0x80004400,0xC0004400,0x84004400,0xC4004400,0x80404400,0xC0404400,0x84404400,0xC4404400,0x80044400,0xC0044400,0x84044400,0xC4044400,0x80444400,0xC0444400,0x84444400,0xC4444400,
+0x80000040,0xC0000040,0x84000040,0xC4000040,0x80400040,0xC0400040,0x84400040,0xC4400040,0x80040040,0xC0040040,0x84040040,0xC4040040,0x80440040,0xC0440040,0x84440040,0xC4440040,
+0x80004040,0xC0004040,0x84004040,0xC4004040,0x80404040,0xC0404040,0x84404040,0xC4404040,0x80044040,0xC0044040,0x84044040,0xC4044040,0x80444040,0xC0444040,0x84444040,0xC4444040,
+0x80000440,0xC0000440,0x84000440,0xC4000440,0x80400440,0xC0400440,0x84400440,0xC4400440,0x80040440,0xC0040440,0x84040440,0xC4040440,0x80440440,0xC0440440,0x84440440,0xC4440440,
+0x80004440,0xC0004440,0x84004440,0xC4004440,0x80404440,0xC0404440,0x84404440,0xC4404440,0x80044440,0xC0044440,0x84044440,0xC4044440,0x80444440,0xC0444440,0x84444440,0xC4444440,
+0x80000004,0xC0000004,0x84000004,0xC4000004,0x80400004,0xC0400004,0x84400004,0xC4400004,0x80040004,0xC0040004,0x84040004,0xC4040004,0x80440004,0xC0440004,0x84440004,0xC4440004,
+0x80004004,0xC0004004,0x84004004,0xC4004004,0x80404004,0xC0404004,0x84404004,0xC4404004,0x80044004,0xC0044004,0x84044004,0xC4044004,0x80444004,0xC0444004,0x84444004,0xC4444004,
+0x80000404,0xC0000404,0x84000404,0xC4000404,0x80400404,0xC0400404,0x84400404,0xC4400404,0x80040404,0xC0040404,0x84040404,0xC4040404,0x80440404,0xC0440404,0x84440404,0xC4440404,
+0x80004404,0xC0004404,0x84004404,0xC4004404,0x80404404,0xC0404404,0x84404404,0xC4404404,0x80044404,0xC0044404,0x84044404,0xC4044404,0x80444404,0xC0444404,0x84444404,0xC4444404,
+0x80000044,0xC0000044,0x84000044,0xC4000044,0x80400044,0xC0400044,0x84400044,0xC4400044,0x80040044,0xC0040044,0x84040044,0xC4040044,0x80440044,0xC0440044,0x84440044,0xC4440044,
+0x80004044,0xC0004044,0x84004044,0xC4004044,0x80404044,0xC0404044,0x84404044,0xC4404044,0x80044044,0xC0044044,0x84044044,0xC4044044,0x80444044,0xC0444044,0x84444044,0xC4444044,
+0x80000444,0xC0000444,0x84000444,0xC4000444,0x80400444,0xC0400444,0x84400444,0xC4400444,0x80040444,0xC0040444,0x84040444,0xC4040444,0x80440444,0xC0440444,0x84440444,0xC4440444,
+0x80004444,0xC0004444,0x84004444,0xC4004444,0x80404444,0xC0404444,0x84404444,0xC4404444,0x80044444,0xC0044444,0x84044444,0xC4044444,0x80444444,0xC0444444,0x84444444,0xC4444444,
+0x08000000,0x48000000,0x0C000000,0x4C000000,0x08400000,0x48400000,0x0C400000,0x4C400000,0x08040000,0x48040000,0x0C040000,0x4C040000,0x08440000,0x48440000,0x0C440000,0x4C440000,
+0x08004000,0x48004000,0x0C004000,0x4C004000,0x08404000,0x48404000,0x0C404000,0x4C404000,0x08044000,0x48044000,0x0C044000,0x4C044000,0x08444000,0x48444000,0x0C444000,0x4C444000,
+0x08000400,0x48000400,0x0C000400,0x4C000400,0x08400400,0x48400400,0x0C400400,0x4C400400,0x08040400,0x48040400,0x0C040400,0x4C040400,0x08440400,0x48440400,0x0C440400,0x4C440400,
+0x08004400,0x48004400,0x0C004400,0x4C004400,0x08404400,0x48404400,0x0C404400,0x4C404400,0x08044400,0x48044400,0x0C044400,0x4C044400,0x08444400,0x48444400,0x0C444400,0x4C444400,
+0x08000040,0x48000040,0x0C000040,0x4C000040,0x08400040,0x48400040,0x0C400040,0x4C400040,0x08040040,0x48040040,0x0C040040,0x4C040040,0x08440040,0x48440040,0x0C440040,0x4C440040,
+0x08004040,0x48004040,0x0C004040,0x4C004040,0x08404040,0x48404040,0x0C404040,0x4C404040,0x08044040,0x48044040,0x0C044040,0x4C044040,0x08444040,0x48444040,0x0C444040,0x4C444040,
+0x08000440,0x48000440,0x0C000440,0x4C000440,0x08400440,0x48400440,0x0C400440,0x4C400440,0x08040440,0x48040440,0x0C040440,0x4C040440,0x08440440,0x48440440,0x0C440440,0x4C440440,
+0x08004440,0x48004440,0x0C004440,0x4C004440,0x08404440,0x48404440,0x0C404440,0x4C404440,0x08044440,0x48044440,0x0C044440,0x4C044440,0x08444440,0x48444440,0x0C444440,0x4C444440,
+0x08000004,0x48000004,0x0C000004,0x4C000004,0x08400004,0x48400004,0x0C400004,0x4C400004,0x08040004,0x48040004,0x0C040004,0x4C040004,0x08440004,0x48440004,0x0C440004,0x4C440004,
+0x08004004,0x48004004,0x0C004004,0x4C004004,0x08404004,0x48404004,0x0C404004,0x4C404004,0x08044004,0x48044004,0x0C044004,0x4C044004,0x08444004,0x48444004,0x0C444004,0x4C444004,
+0x08000404,0x48000404,0x0C000404,0x4C000404,0x08400404,0x48400404,0x0C400404,0x4C400404,0x08040404,0x48040404,0x0C040404,0x4C040404,0x08440404,0x48440404,0x0C440404,0x4C440404,
+0x08004404,0x48004404,0x0C004404,0x4C004404,0x08404404,0x48404404,0x0C404404,0x4C404404,0x08044404,0x48044404,0x0C044404,0x4C044404,0x08444404,0x48444404,0x0C444404,0x4C444404,
+0x08000044,0x48000044,0x0C000044,0x4C000044,0x08400044,0x48400044,0x0C400044,0x4C400044,0x08040044,0x48040044,0x0C040044,0x4C040044,0x08440044,0x48440044,0x0C440044,0x4C440044,
+0x08004044,0x48004044,0x0C004044,0x4C004044,0x08404044,0x48404044,0x0C404044,0x4C404044,0x08044044,0x48044044,0x0C044044,0x4C044044,0x08444044,0x48444044,0x0C444044,0x4C444044,
+0x08000444,0x48000444,0x0C000444,0x4C000444,0x08400444,0x48400444,0x0C400444,0x4C400444,0x08040444,0x48040444,0x0C040444,0x4C040444,0x08440444,0x48440444,0x0C440444,0x4C440444,
+0x08004444,0x48004444,0x0C004444,0x4C004444,0x08404444,0x48404444,0x0C404444,0x4C404444,0x08044444,0x48044444,0x0C044444,0x4C044444,0x08444444,0x48444444,0x0C444444,0x4C444444,
+0x88000000,0xC8000000,0x8C000000,0xCC000000,0x88400000,0xC8400000,0x8C400000,0xCC400000,0x88040000,0xC8040000,0x8C040000,0xCC040000,0x88440000,0xC8440000,0x8C440000,0xCC440000,
+0x88004000,0xC8004000,0x8C004000,0xCC004000,0x88404000,0xC8404000,0x8C404000,0xCC404000,0x88044000,0xC8044000,0x8C044000,0xCC044000,0x88444000,0xC8444000,0x8C444000,0xCC444000,
+0x88000400,0xC8000400,0x8C000400,0xCC000400,0x88400400,0xC8400400,0x8C400400,0xCC400400,0x88040400,0xC8040400,0x8C040400,0xCC040400,0x88440400,0xC8440400,0x8C440400,0xCC440400,
+0x88004400,0xC8004400,0x8C004400,0xCC004400,0x88404400,0xC8404400,0x8C404400,0xCC404400,0x88044400,0xC8044400,0x8C044400,0xCC044400,0x88444400,0xC8444400,0x8C444400,0xCC444400,
+0x88000040,0xC8000040,0x8C000040,0xCC000040,0x88400040,0xC8400040,0x8C400040,0xCC400040,0x88040040,0xC8040040,0x8C040040,0xCC040040,0x88440040,0xC8440040,0x8C440040,0xCC440040,
+0x88004040,0xC8004040,0x8C004040,0xCC004040,0x88404040,0xC8404040,0x8C404040,0xCC404040,0x88044040,0xC8044040,0x8C044040,0xCC044040,0x88444040,0xC8444040,0x8C444040,0xCC444040,
+0x88000440,0xC8000440,0x8C000440,0xCC000440,0x88400440,0xC8400440,0x8C400440,0xCC400440,0x88040440,0xC8040440,0x8C040440,0xCC040440,0x88440440,0xC8440440,0x8C440440,0xCC440440,
+0x88004440,0xC8004440,0x8C004440,0xCC004440,0x88404440,0xC8404440,0x8C404440,0xCC404440,0x88044440,0xC8044440,0x8C044440,0xCC044440,0x88444440,0xC8444440,0x8C444440,0xCC444440,
+0x88000004,0xC8000004,0x8C000004,0xCC000004,0x88400004,0xC8400004,0x8C400004,0xCC400004,0x88040004,0xC8040004,0x8C040004,0xCC040004,0x88440004,0xC8440004,0x8C440004,0xCC440004,
+0x88004004,0xC8004004,0x8C004004,0xCC004004,0x88404004,0xC8404004,0x8C404004,0xCC404004,0x88044004,0xC8044004,0x8C044004,0xCC044004,0x88444004,0xC8444004,0x8C444004,0xCC444004,
+0x88000404,0xC8000404,0x8C000404,0xCC000404,0x88400404,0xC8400404,0x8C400404,0xCC400404,0x88040404,0xC8040404,0x8C040404,0xCC040404,0x88440404,0xC8440404,0x8C440404,0xCC440404,
+0x88004404,0xC8004404,0x8C004404,0xCC004404,0x88404404,0xC8404404,0x8C404404,0xCC404404,0x88044404,0xC8044404,0x8C044404,0xCC044404,0x88444404,0xC8444404,0x8C444404,0xCC444404,
+0x88000044,0xC8000044,0x8C000044,0xCC000044,0x88400044,0xC8400044,0x8C400044,0xCC400044,0x88040044,0xC8040044,0x8C040044,0xCC040044,0x88440044,0xC8440044,0x8C440044,0xCC440044,
+0x88004044,0xC8004044,0x8C004044,0xCC004044,0x88404044,0xC8404044,0x8C404044,0xCC404044,0x88044044,0xC8044044,0x8C044044,0xCC044044,0x88444044,0xC8444044,0x8C444044,0xCC444044,
+0x88000444,0xC8000444,0x8C000444,0xCC000444,0x88400444,0xC8400444,0x8C400444,0xCC400444,0x88040444,0xC8040444,0x8C040444,0xCC040444,0x88440444,0xC8440444,0x8C440444,0xCC440444,
+0x88004444,0xC8004444,0x8C004444,0xCC004444,0x88404444,0xC8404444,0x8C404444,0xCC404444,0x88044444,0xC8044444,0x8C044444,0xCC044444,0x88444444,0xC8444444,0x8C444444,0xCC444444,
+0x00800000,0x40800000,0x04800000,0x44800000,0x00C00000,0x40C00000,0x04C00000,0x44C00000,0x00840000,0x40840000,0x04840000,0x44840000,0x00C40000,0x40C40000,0x04C40000,0x44C40000,
+0x00804000,0x40804000,0x04804000,0x44804000,0x00C04000,0x40C04000,0x04C04000,0x44C04000,0x00844000,0x40844000,0x04844000,0x44844000,0x00C44000,0x40C44000,0x04C44000,0x44C44000,
+0x00800400,0x40800400,0x04800400,0x44800400,0x00C00400,0x40C00400,0x04C00400,0x44C00400,0x00840400,0x40840400,0x04840400,0x44840400,0x00C40400,0x40C40400,0x04C40400,0x44C40400,
+0x00804400,0x40804400,0x04804400,0x44804400,0x00C04400,0x40C04400,0x04C04400,0x44C04400,0x00844400,0x40844400,0x04844400,0x44844400,0x00C44400,0x40C44400,0x04C44400,0x44C44400,
+0x00800040,0x40800040,0x04800040,0x44800040,0x00C00040,0x40C00040,0x04C00040,0x44C00040,0x00840040,0x40840040,0x04840040,0x44840040,0x00C40040,0x40C40040,0x04C40040,0x44C40040,
+0x00804040,0x40804040,0x04804040,0x44804040,0x00C04040,0x40C04040,0x04C04040,0x44C04040,0x00844040,0x40844040,0x04844040,0x44844040,0x00C44040,0x40C44040,0x04C44040,0x44C44040,
+0x00800440,0x40800440,0x04800440,0x44800440,0x00C00440,0x40C00440,0x04C00440,0x44C00440,0x00840440,0x40840440,0x04840440,0x44840440,0x00C40440,0x40C40440,0x04C40440,0x44C40440,
+0x00804440,0x40804440,0x04804440,0x44804440,0x00C04440,0x40C04440,0x04C04440,0x44C04440,0x00844440,0x40844440,0x04844440,0x44844440,0x00C44440,0x40C44440,0x04C44440,0x44C44440,
+0x00800004,0x40800004,0x04800004,0x44800004,0x00C00004,0x40C00004,0x04C00004,0x44C00004,0x00840004,0x40840004,0x04840004,0x44840004,0x00C40004,0x40C40004,0x04C40004,0x44C40004,
+0x00804004,0x40804004,0x04804004,0x44804004,0x00C04004,0x40C04004,0x04C04004,0x44C04004,0x00844004,0x40844004,0x04844004,0x44844004,0x00C44004,0x40C44004,0x04C44004,0x44C44004,
+0x00800404,0x40800404,0x04800404,0x44800404,0x00C00404,0x40C00404,0x04C00404,0x44C00404,0x00840404,0x40840404,0x04840404,0x44840404,0x00C40404,0x40C40404,0x04C40404,0x44C40404,
+0x00804404,0x40804404,0x04804404,0x44804404,0x00C04404,0x40C04404,0x04C04404,0x44C04404,0x00844404,0x40844404,0x04844404,0x44844404,0x00C44404,0x40C44404,0x04C44404,0x44C44404,
+0x00800044,0x40800044,0x04800044,0x44800044,0x00C00044,0x40C00044,0x04C00044,0x44C00044,0x00840044,0x40840044,0x04840044,0x44840044,0x00C40044,0x40C40044,0x04C40044,0x44C40044,
+0x00804044,0x40804044,0x04804044,0x44804044,0x00C04044,0x40C04044,0x04C04044,0x44C04044,0x00844044,0x40844044,0x04844044,0x44844044,0x00C44044,0x40C44044,0x04C44044,0x44C44044,
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+0x0888C8C8,0x4888C8C8,0x0C88C8C8,0x4C88C8C8,0x08C8C8C8,0x48C8C8C8,0x0CC8C8C8,0x4CC8C8C8,0x088CC8C8,0x488CC8C8,0x0C8CC8C8,0x4C8CC8C8,0x08CCC8C8,0x48CCC8C8,0x0CCCC8C8,0x4CCCC8C8,
+0x08888CC8,0x48888CC8,0x0C888CC8,0x4C888CC8,0x08C88CC8,0x48C88CC8,0x0CC88CC8,0x4CC88CC8,0x088C8CC8,0x488C8CC8,0x0C8C8CC8,0x4C8C8CC8,0x08CC8CC8,0x48CC8CC8,0x0CCC8CC8,0x4CCC8CC8,
+0x0888CCC8,0x4888CCC8,0x0C88CCC8,0x4C88CCC8,0x08C8CCC8,0x48C8CCC8,0x0CC8CCC8,0x4CC8CCC8,0x088CCCC8,0x488CCCC8,0x0C8CCCC8,0x4C8CCCC8,0x08CCCCC8,0x48CCCCC8,0x0CCCCCC8,0x4CCCCCC8,
+0x0888888C,0x4888888C,0x0C88888C,0x4C88888C,0x08C8888C,0x48C8888C,0x0CC8888C,0x4CC8888C,0x088C888C,0x488C888C,0x0C8C888C,0x4C8C888C,0x08CC888C,0x48CC888C,0x0CCC888C,0x4CCC888C,
+0x0888C88C,0x4888C88C,0x0C88C88C,0x4C88C88C,0x08C8C88C,0x48C8C88C,0x0CC8C88C,0x4CC8C88C,0x088CC88C,0x488CC88C,0x0C8CC88C,0x4C8CC88C,0x08CCC88C,0x48CCC88C,0x0CCCC88C,0x4CCCC88C,
+0x08888C8C,0x48888C8C,0x0C888C8C,0x4C888C8C,0x08C88C8C,0x48C88C8C,0x0CC88C8C,0x4CC88C8C,0x088C8C8C,0x488C8C8C,0x0C8C8C8C,0x4C8C8C8C,0x08CC8C8C,0x48CC8C8C,0x0CCC8C8C,0x4CCC8C8C,
+0x0888CC8C,0x4888CC8C,0x0C88CC8C,0x4C88CC8C,0x08C8CC8C,0x48C8CC8C,0x0CC8CC8C,0x4CC8CC8C,0x088CCC8C,0x488CCC8C,0x0C8CCC8C,0x4C8CCC8C,0x08CCCC8C,0x48CCCC8C,0x0CCCCC8C,0x4CCCCC8C,
+0x088888CC,0x488888CC,0x0C8888CC,0x4C8888CC,0x08C888CC,0x48C888CC,0x0CC888CC,0x4CC888CC,0x088C88CC,0x488C88CC,0x0C8C88CC,0x4C8C88CC,0x08CC88CC,0x48CC88CC,0x0CCC88CC,0x4CCC88CC,
+0x0888C8CC,0x4888C8CC,0x0C88C8CC,0x4C88C8CC,0x08C8C8CC,0x48C8C8CC,0x0CC8C8CC,0x4CC8C8CC,0x088CC8CC,0x488CC8CC,0x0C8CC8CC,0x4C8CC8CC,0x08CCC8CC,0x48CCC8CC,0x0CCCC8CC,0x4CCCC8CC,
+0x08888CCC,0x48888CCC,0x0C888CCC,0x4C888CCC,0x08C88CCC,0x48C88CCC,0x0CC88CCC,0x4CC88CCC,0x088C8CCC,0x488C8CCC,0x0C8C8CCC,0x4C8C8CCC,0x08CC8CCC,0x48CC8CCC,0x0CCC8CCC,0x4CCC8CCC,
+0x0888CCCC,0x4888CCCC,0x0C88CCCC,0x4C88CCCC,0x08C8CCCC,0x48C8CCCC,0x0CC8CCCC,0x4CC8CCCC,0x088CCCCC,0x488CCCCC,0x0C8CCCCC,0x4C8CCCCC,0x08CCCCCC,0x48CCCCCC,0x0CCCCCCC,0x4CCCCCCC,
+0x88888888,0xC8888888,0x8C888888,0xCC888888,0x88C88888,0xC8C88888,0x8CC88888,0xCCC88888,0x888C8888,0xC88C8888,0x8C8C8888,0xCC8C8888,0x88CC8888,0xC8CC8888,0x8CCC8888,0xCCCC8888,
+0x8888C888,0xC888C888,0x8C88C888,0xCC88C888,0x88C8C888,0xC8C8C888,0x8CC8C888,0xCCC8C888,0x888CC888,0xC88CC888,0x8C8CC888,0xCC8CC888,0x88CCC888,0xC8CCC888,0x8CCCC888,0xCCCCC888,
+0x88888C88,0xC8888C88,0x8C888C88,0xCC888C88,0x88C88C88,0xC8C88C88,0x8CC88C88,0xCCC88C88,0x888C8C88,0xC88C8C88,0x8C8C8C88,0xCC8C8C88,0x88CC8C88,0xC8CC8C88,0x8CCC8C88,0xCCCC8C88,
+0x8888CC88,0xC888CC88,0x8C88CC88,0xCC88CC88,0x88C8CC88,0xC8C8CC88,0x8CC8CC88,0xCCC8CC88,0x888CCC88,0xC88CCC88,0x8C8CCC88,0xCC8CCC88,0x88CCCC88,0xC8CCCC88,0x8CCCCC88,0xCCCCCC88,
+0x888888C8,0xC88888C8,0x8C8888C8,0xCC8888C8,0x88C888C8,0xC8C888C8,0x8CC888C8,0xCCC888C8,0x888C88C8,0xC88C88C8,0x8C8C88C8,0xCC8C88C8,0x88CC88C8,0xC8CC88C8,0x8CCC88C8,0xCCCC88C8,
+0x8888C8C8,0xC888C8C8,0x8C88C8C8,0xCC88C8C8,0x88C8C8C8,0xC8C8C8C8,0x8CC8C8C8,0xCCC8C8C8,0x888CC8C8,0xC88CC8C8,0x8C8CC8C8,0xCC8CC8C8,0x88CCC8C8,0xC8CCC8C8,0x8CCCC8C8,0xCCCCC8C8,
+0x88888CC8,0xC8888CC8,0x8C888CC8,0xCC888CC8,0x88C88CC8,0xC8C88CC8,0x8CC88CC8,0xCCC88CC8,0x888C8CC8,0xC88C8CC8,0x8C8C8CC8,0xCC8C8CC8,0x88CC8CC8,0xC8CC8CC8,0x8CCC8CC8,0xCCCC8CC8,
+0x8888CCC8,0xC888CCC8,0x8C88CCC8,0xCC88CCC8,0x88C8CCC8,0xC8C8CCC8,0x8CC8CCC8,0xCCC8CCC8,0x888CCCC8,0xC88CCCC8,0x8C8CCCC8,0xCC8CCCC8,0x88CCCCC8,0xC8CCCCC8,0x8CCCCCC8,0xCCCCCCC8,
+0x8888888C,0xC888888C,0x8C88888C,0xCC88888C,0x88C8888C,0xC8C8888C,0x8CC8888C,0xCCC8888C,0x888C888C,0xC88C888C,0x8C8C888C,0xCC8C888C,0x88CC888C,0xC8CC888C,0x8CCC888C,0xCCCC888C,
+0x8888C88C,0xC888C88C,0x8C88C88C,0xCC88C88C,0x88C8C88C,0xC8C8C88C,0x8CC8C88C,0xCCC8C88C,0x888CC88C,0xC88CC88C,0x8C8CC88C,0xCC8CC88C,0x88CCC88C,0xC8CCC88C,0x8CCCC88C,0xCCCCC88C,
+0x88888C8C,0xC8888C8C,0x8C888C8C,0xCC888C8C,0x88C88C8C,0xC8C88C8C,0x8CC88C8C,0xCCC88C8C,0x888C8C8C,0xC88C8C8C,0x8C8C8C8C,0xCC8C8C8C,0x88CC8C8C,0xC8CC8C8C,0x8CCC8C8C,0xCCCC8C8C,
+0x8888CC8C,0xC888CC8C,0x8C88CC8C,0xCC88CC8C,0x88C8CC8C,0xC8C8CC8C,0x8CC8CC8C,0xCCC8CC8C,0x888CCC8C,0xC88CCC8C,0x8C8CCC8C,0xCC8CCC8C,0x88CCCC8C,0xC8CCCC8C,0x8CCCCC8C,0xCCCCCC8C,
+0x888888CC,0xC88888CC,0x8C8888CC,0xCC8888CC,0x88C888CC,0xC8C888CC,0x8CC888CC,0xCCC888CC,0x888C88CC,0xC88C88CC,0x8C8C88CC,0xCC8C88CC,0x88CC88CC,0xC8CC88CC,0x8CCC88CC,0xCCCC88CC,
+0x8888C8CC,0xC888C8CC,0x8C88C8CC,0xCC88C8CC,0x88C8C8CC,0xC8C8C8CC,0x8CC8C8CC,0xCCC8C8CC,0x888CC8CC,0xC88CC8CC,0x8C8CC8CC,0xCC8CC8CC,0x88CCC8CC,0xC8CCC8CC,0x8CCCC8CC,0xCCCCC8CC,
+0x88888CCC,0xC8888CCC,0x8C888CCC,0xCC888CCC,0x88C88CCC,0xC8C88CCC,0x8CC88CCC,0xCCC88CCC,0x888C8CCC,0xC88C8CCC,0x8C8C8CCC,0xCC8C8CCC,0x88CC8CCC,0xC8CC8CCC,0x8CCC8CCC,0xCCCC8CCC,
+0x8888CCCC,0xC888CCCC,0x8C88CCCC,0xCC88CCCC,0x88C8CCCC,0xC8C8CCCC,0x8CC8CCCC,0xCCC8CCCC,0x888CCCCC,0xC88CCCCC,0x8C8CCCCC,0xCC8CCCCC,0x88CCCCCC,0xC8CCCCCC,0x8CCCCCCC,0xCCCCCCCC,
+};
diff --git a/MCUME_pico2/picopceold/cpuintrf.h b/MCUME_pico2/picopceold/cpuintrf.h
new file mode 100644
index 0000000..d89ccf8
--- /dev/null
+++ b/MCUME_pico2/picopceold/cpuintrf.h
@@ -0,0 +1,12 @@
+
+#ifndef CPUINTRF_H
+#define CPUINTRF_H
+
+#include "osd_cpu.h"
+
+#define CLEAR_LINE              0
+#define ASSERT_LINE             1
+#define REG_PREVIOUSPC          -1
+#define REG_SP_CONTENTS         -2
+
+#endif	/* CPUINTRF_H */
diff --git a/MCUME_pico2/picopceold/emu.cpp b/MCUME_pico2/picopceold/emu.cpp
new file mode 100644
index 0000000..9fcd6b6
--- /dev/null
+++ b/MCUME_pico2/picopceold/emu.cpp
@@ -0,0 +1,113 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h" 
+
+extern "C" {
+#include "shared.h"
+#include "system.h"
+}
+
+static int frame_skip=1;
+
+#ifdef HAS_PSRAM
+#include "psram_t.h"
+
+PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO);
+
+extern "C" uint8 read_rom(int address) {
+  return (psram.psread(address)); 
+}
+
+extern "C" void  write_rom(int address, uint8 val)  {
+  psram.pswrite(address,val); 
+
+}
+#else
+
+#include "flash_t.h"
+int8 * flash_start;
+
+extern "C" uint8 read_rom(int address) {
+  return flash_start[address];
+}
+#endif
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+
+void pce_Init(void)
+{
+  emu_printf("Allocating MEM"); 
+#ifdef HAS_PSRAM  
+  psram.begin();
+#endif  
+  mem_init();    
+  emu_printf("Allocating MEM done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void pce_Input(int click) {
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();   
+}
+
+
+void pce_Start(char * filename)
+{
+  emu_printf("init started");
+  load_rom(filename, 0,0);
+ 
+#ifdef SOUND_PRESENT
+  system_init(22050);
+#ifdef HAS_SND  
+  emu_sndInit();
+#endif  
+#else
+  system_init(0);
+#endif
+  system_reset();
+
+  emu_printf("init done");
+}
+
+void pce_Step(void) {
+
+  input.pad[0] = 0;
+
+  if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+    input.pad[0] |= INPUT_RIGHT;
+  }
+  if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+    input.pad[0] |= INPUT_LEFT;
+  }
+  if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+    input.pad[0] |= INPUT_UP;
+  }
+  if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+    input.pad[0] |= INPUT_DOWN;
+  }  
+  if ( k & MASK_JOY2_BTN) {
+    input.pad[0] |= INPUT_B2; 
+  }
+
+  if (k & MASK_KEY_USER1)  input.pad[0] |= INPUT_B1;
+  //if (k & MASK_KEY_USER3)  input.pad[0] |= INPUT_SELECT;
+  if (k & MASK_KEY_USER2)  input.pad[0] |= INPUT_RUN;
+
+
+  system_frame(frame_skip);
+  emu_DrawVsync();    
+}
+
+void SND_Process(void *stream, int len) {
+  psg_update((int16*)stream, 0, len);  
+} 
diff --git a/MCUME_pico2/picopceold/emu.h b/MCUME_pico2/picopceold/emu.h
new file mode 100644
index 0000000..ad56515
--- /dev/null
+++ b/MCUME_pico2/picopceold/emu.h
@@ -0,0 +1,5 @@
+extern void pce_Init(void);
+extern void pce_Step(void);
+extern void pce_Start(char * filename);
+extern void pce_Input(int click);
+
diff --git a/MCUME_pico2/picopceold/emucfg.h b/MCUME_pico2/picopceold/emucfg.h
new file mode 100644
index 0000000..01f288e
--- /dev/null
+++ b/MCUME_pico2/picopceold/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         1
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    PC Engine Emulator"
+#define ROMSDIR "pce"
+
+#define emu_Init(ROM) {pce_Init(); pce_Start(ROM);}
+#define emu_Step(x) {pce_Step();}
+#define emu_Input(x) {pce_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picopceold/h6280.c b/MCUME_pico2/picopceold/h6280.c
new file mode 100644
index 0000000..c31f912
--- /dev/null
+++ b/MCUME_pico2/picopceold/h6280.c
@@ -0,0 +1,356 @@
+/*****************************************************************************
+
+	h6280.c - Portable HuC6280 emulator
+
+	Copyright (c) 1999, 2000 Bryan McPhail, mish@tendril.co.uk
+
+	This source code is based (with permission!) on the 6502 emulator by
+	Juergen Buchmueller.  It is released as part of the Mame emulator project.
+	Let me know if you intend to use this code in any other project.
+
+
+	NOTICE:
+
+	This code is around 99% complete!  Several things are unimplemented,
+	some due to lack of time, some due to lack of documentation, mainly
+	due to lack of programs using these features.
+
+	csh, csl opcodes are not supported.
+	set opcode and T flag behaviour are not supported.
+
+	I am unsure if instructions like SBC take an extra cycle when used in
+	decimal mode.  I am unsure if flag B is set upon execution of rti.
+
+	Cycle counts should be quite accurate, illegal instructions are assumed
+	to take two cycles.
+
+
+	Changelog, version 1.02:
+		JMP + indirect X (0x7c) opcode fixed.
+		SMB + RMB opcodes fixed in disassembler.
+		change_pc function calls removed.
+		TSB & TRB now set flags properly.
+		BIT opcode altered.
+
+	Changelog, version 1.03:
+		Swapped IRQ mask for IRQ1 & IRQ2 (thanks Yasuhiro)
+
+	Changelog, version 1.04, 28/9/99-22/10/99:
+		Adjusted RTI (thanks Karl)
+ 		TST opcodes fixed in disassembler (missing break statements in a case!).
+		TST behaviour fixed.
+		SMB/RMB/BBS/BBR fixed in disassembler.
+
+	Changelog, version 1.05, 8/12/99-16/12/99:
+		Added CAB's timer implementation (note: irq ack & timer reload are changed).
+		Fixed STA IDX.
+		Fixed B flag setting on BRK.
+		Assumed CSH & CSL to take 2 cycles each.
+
+		Todo:  Performance could be improved by precalculating timer fire position.
+
+	Changelog, version 1.06, 4/5/00 - last opcode bug found?
+		JMP indirect was doing a EAL++; instead of EAD++; - Obviously causing
+		a corrupt read when L = 0xff!  This fixes Bloody Wolf and Trio The Punch!
+
+	Changelog, version 1.07, 3/9/00:
+		Changed timer to be single shot - fixes Crude Buster music in level 1.
+
+    Changelog, version 1.08, 1/18/01: (Charles MacDonald)
+        Added h6280_speed to reflect current CPU speed set by CSL/CSH.
+        Added implementation of SET opcode.
+        Changed INLINE in tblh6280.h to 'static __inline__' (Allegro conflict)
+        Added FAST_MEM routines for quicker ROM/RAM access.
+
+******************************************************************************/
+#include "shared.h"
+
+#include "cpuintrf.h"
+#include "h6280.h"
+
+/* Default state of HuC6280 clock (1=7.16MHz, 0=3.58MHz) */
+int h6280_speed = 1;
+int h6280_ICount = 0;
+static  h6280_Regs  h6280;
+
+#include "h6280ops.h"
+#include "tblh6280.h"
+
+/*****************************************************************************/
+
+void h6280_reset(void)
+{
+	int i;
+
+	/* wipe out the h6280 structure */
+	memset(&h6280, 0, sizeof(h6280_Regs));
+
+	/* set I and Z flags */
+	P = _fI | _fZ;
+
+    /* stack starts at 0x01ff */
+	h6280.sp.d = 0x1ff;
+
+    /* read the reset vector into PC */
+	PCL = RDMEM(H6280_RESET_VEC);
+	PCH = RDMEM((H6280_RESET_VEC+1));
+
+	/* timer off by default */
+	h6280.timer_status=0;
+	h6280.timer_ack=1;
+
+    /* clear pending interrupts */
+	for (i = 0; i < 3; i++)
+		h6280.irq_state[i] = CLEAR_LINE;
+
+    h6280_speed = 1; /* default = 7.16MHz (?) */
+}
+
+void h6280_exit(void)
+{
+	/* nothing */
+}
+
+int h6280_execute(int cycles)
+{
+	int in,lastcycle,deltacycle;
+	h6280_ICount = cycles;
+
+    /* Subtract cycles used for taking an interrupt */
+    h6280_ICount -= h6280.extra_cycles;
+	h6280.extra_cycles = 0;
+	lastcycle = h6280_ICount;
+
+//    DEBUGLOG("h6280_execute 1\n");
+
+	/* Execute instructions */
+	do
+    {
+		h6280.ppc = h6280.pc;
+//        DEBUGLOG("h6280_execute 2 PC[%08X]\n",PCW );
+
+		/* Execute 1 instruction */
+		in=RDOP();
+		PCW++;
+//        DEBUGLOG("h6280_execute 2.5 in=[%d]\n",in);
+		insnh6280[in]();
+
+//        DEBUGLOG("h6280_execute 3\n");
+
+        /* Check internal timer */
+		if(h6280.timer_status)
+		{
+			deltacycle = lastcycle - h6280_ICount;
+			h6280.timer_value -= deltacycle;
+			if(h6280.timer_value<=0 && h6280.timer_ack==1)
+			{
+				h6280.timer_ack=h6280.timer_status=0;
+				h6280_set_irq_line(2,ASSERT_LINE);
+			}
+		}
+		lastcycle = h6280_ICount;
+//        DEBUGLOG("h6280_execute 4\n");
+
+		/* If PC has not changed we are stuck in a tight loop, may as well finish */
+		if( h6280.pc.d == h6280.ppc.d )
+		{
+			if (h6280_ICount > 0) h6280_ICount=0;
+			h6280.extra_cycles = 0;
+			return cycles;
+		}
+//        DEBUGLOG("h6280_execute 5\n");
+
+	} while (h6280_ICount > 0);
+
+	/* Subtract cycles used for taking an interrupt */
+    h6280_ICount -= h6280.extra_cycles;
+    h6280.extra_cycles = 0;
+
+    return cycles - h6280_ICount;
+}
+
+unsigned h6280_get_context (void *dst)
+{
+	if( dst )
+		*(h6280_Regs*)dst = h6280;
+	return sizeof(h6280_Regs);
+}
+
+void h6280_set_context (void *src)
+{
+	if( src )
+		h6280 = *(h6280_Regs*)src;
+}
+
+unsigned h6280_get_pc (void)
+{
+    return PCD;
+}
+
+void h6280_set_pc (unsigned val)
+{
+	PCW = val;
+}
+
+unsigned h6280_get_sp (void)
+{
+	return S;
+}
+
+void h6280_set_sp (unsigned val)
+{
+	S = val;
+}
+
+unsigned h6280_get_reg (int regnum)
+{
+	switch( regnum )
+	{
+		case H6280_PC: return PCD;
+		case H6280_S: return S;
+		case H6280_P: return P;
+		case H6280_A: return A;
+		case H6280_X: return X;
+		case H6280_Y: return Y;
+		case H6280_IRQ_MASK: return h6280.irq_mask;
+		case H6280_TIMER_STATE: return h6280.timer_status;
+		case H6280_NMI_STATE: return h6280.nmi_state;
+		case H6280_IRQ1_STATE: return h6280.irq_state[0];
+		case H6280_IRQ2_STATE: return h6280.irq_state[1];
+		case H6280_IRQT_STATE: return h6280.irq_state[2];
+		case REG_PREVIOUSPC: return h6280.ppc.d;
+		default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0x1ff )
+					return RDMEM( offset ) | ( RDMEM( offset+1 ) << 8 );
+			}
+	}
+	return 0;
+}
+
+void h6280_set_reg (int regnum, unsigned val)
+{
+	switch( regnum )
+	{
+		case H6280_PC: PCW = val; break;
+		case H6280_S: S = val; break;
+		case H6280_P: P = val; break;
+		case H6280_A: A = val; break;
+		case H6280_X: X = val; break;
+		case H6280_Y: Y = val; break;
+		case H6280_IRQ_MASK: h6280.irq_mask = val; CHECK_IRQ_LINES; break;
+		case H6280_TIMER_STATE: h6280.timer_status = val; break;
+		case H6280_NMI_STATE: h6280_set_nmi_line( val ); break;
+		case H6280_IRQ1_STATE: h6280_set_irq_line( 0, val ); break;
+		case H6280_IRQ2_STATE: h6280_set_irq_line( 1, val ); break;
+		case H6280_IRQT_STATE: h6280_set_irq_line( 2, val ); break;
+		default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0x1ff )
+				{
+					WRMEM( offset, val & 0xff );
+					WRMEM( offset+1, (val >> 8) & 0xff );
+				}
+			}
+    }
+}
+
+/*****************************************************************************/
+
+void h6280_set_nmi_line(int state)
+{
+	if (h6280.nmi_state == state) return;
+	h6280.nmi_state = state;
+	if (state != CLEAR_LINE)
+    {
+		DO_INTERRUPT(H6280_NMI_VEC);
+	}
+}
+
+void h6280_set_irq_line(int irqline, int state)
+{
+    h6280.irq_state[irqline] = state;
+
+	/* If line is cleared, just exit */
+	if (state == CLEAR_LINE) return;
+
+	/* Check if interrupts are enabled and the IRQ mask is clear */
+	CHECK_IRQ_LINES;
+}
+
+void h6280_set_irq_callback(int (*callback)(int irqline))
+{
+	h6280.irq_callback = callback;
+}
+
+int H6280_irq_status_r (int offset)
+{
+	int status;
+
+	switch (offset)
+	{
+		case 0: /* Read irq mask */
+			return h6280.irq_mask;
+
+		case 1: /* Read irq status */
+			status=0;
+			if(h6280.irq_state[1]!=CLEAR_LINE) status|=1; /* IRQ 2 */
+			if(h6280.irq_state[0]!=CLEAR_LINE) status|=2; /* IRQ 1 */
+			if(h6280.irq_state[2]!=CLEAR_LINE) status|=4; /* TIMER */
+			return status;
+	}
+
+	return 0;
+}
+
+void H6280_irq_status_w (int offset, int data)
+{
+	switch (offset)
+	{
+		case 0: /* Write irq mask */
+			h6280.irq_mask=data&0x7;
+			CHECK_IRQ_LINES;
+			break;
+
+		case 1: /* Timer irq ack - timer is reloaded here */
+			h6280.timer_value = h6280.timer_load;
+			h6280.timer_ack=1; /* Timer can't refire until ack'd */
+			break;
+	}
+}
+
+int H6280_timer_r (int offset)
+{
+	switch (offset) {
+		case 0: /* Counter value */
+			return (h6280.timer_value/1024)&127;
+
+		case 1: /* Read counter status */
+			return h6280.timer_status;
+	}
+
+	return 0;
+}
+
+void H6280_timer_w (int offset, int data)
+{
+	switch (offset) {
+		case 0: /* Counter preload */
+			h6280.timer_load=h6280.timer_value=((data&127)+1)*1024;
+			return;
+
+		case 1: /* Counter enable */
+			if(data&1)
+			{	/* stop -> start causes reload */
+				if(h6280.timer_status==0) h6280.timer_value=h6280.timer_load;
+			}
+			h6280.timer_status=data&1;
+			return;
+	}
+}
+
+/*****************************************************************************/
diff --git a/MCUME_pico2/picopceold/h6280.h b/MCUME_pico2/picopceold/h6280.h
new file mode 100644
index 0000000..a10f64b
--- /dev/null
+++ b/MCUME_pico2/picopceold/h6280.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+
+	h6280.h Portable Hu6280 emulator interface
+
+	Copyright (c) 1999 Bryan McPhail, mish@tendril.co.uk
+
+	This source code is based (with permission!) on the 6502 emulator by
+	Juergen Buchmueller.  It is released as part of the Mame emulator project.
+	Let me know if you intend to use this code in any other project.
+
+******************************************************************************/
+
+#ifndef _H6280_H
+#define _H6280_H
+
+#include "osd_cpu.h"
+
+enum {
+	H6280_PC=1, H6280_S, H6280_P, H6280_A, H6280_X, H6280_Y,
+	H6280_IRQ_MASK, H6280_TIMER_STATE,
+	H6280_NMI_STATE, H6280_IRQ1_STATE, H6280_IRQ2_STATE, H6280_IRQT_STATE
+};
+
+extern int h6280_speed;
+
+//#define LAZY_FLAGS  1
+
+#define H6280_INT_NONE	0
+#define H6280_INT_NMI	1
+#define H6280_INT_TIMER	2
+#define H6280_INT_IRQ1	3
+#define H6280_INT_IRQ2	4
+
+#define H6280_RESET_VEC	0xfffe
+#define H6280_NMI_VEC	0xfffc
+#define H6280_TIMER_VEC	0xfffa
+#define H6280_IRQ1_VEC	0xfff8
+#define H6280_IRQ2_VEC	0xfff6			/* Aka BRK vector */
+
+extern int h6280_ICount;				/* cycle count */
+
+extern void h6280_reset(void);			/* Reset registers to the initial values */
+extern void h6280_exit(void);					/* Shut down CPU */
+extern int h6280_execute(int cycles);			/* Execute cycles - returns number of cycles actually run */
+extern unsigned h6280_get_context(void *dst);	/* Get registers, return context size */
+extern void h6280_set_context(void *src);		/* Set registers */
+extern unsigned h6280_get_pc(void); 			/* Get program counter */
+extern void h6280_set_pc(unsigned val); 		/* Set program counter */
+extern unsigned h6280_get_sp(void); 			/* Get stack pointer */
+extern void h6280_set_sp(unsigned val); 		/* Set stack pointer */
+extern unsigned h6280_get_reg (int regnum);
+extern void h6280_set_reg (int regnum, unsigned val);
+extern void h6280_set_nmi_line(int state);
+extern void h6280_set_irq_line(int irqline, int state);
+extern void h6280_set_irq_callback(int (*callback)(int irqline));
+
+int H6280_irq_status_r(int offset);
+void H6280_irq_status_w(int offset, int data);
+int H6280_timer_r(int offset);
+void H6280_timer_w(int offset, int data);
+
+
+/****************************************************************************
+ * The 6280 registers.
+ ****************************************************************************/
+typedef struct
+{
+	PAIR  ppc;			/* previous program counter */
+    PAIR  pc;           /* program counter */
+    PAIR  sp;           /* stack pointer (always 100 - 1FF) */
+    PAIR  zp;           /* zero page address */
+    PAIR  ea;           /* effective address */
+    UINT8 a;            /* Accumulator */
+    UINT8 x;            /* X index register */
+    UINT8 y;            /* Y index register */
+    UINT8 p;            /* Processor status */
+    UINT8 mmr[8];       /* Hu6280 memory mapper registers */
+    UINT8 irq_mask;     /* interrupt enable/disable */
+    UINT8 timer_status; /* timer status */
+	UINT8 timer_ack;	/* timer acknowledge */
+    int timer_value;    /* timer interrupt */
+    int timer_load;		/* reload value */
+	int extra_cycles;	/* cycles used taking an interrupt */
+    int nmi_state;
+    int irq_state[3];
+    int (*irq_callback)(int irqline);
+
+#if LAZY_FLAGS
+    int NZ;             /* last value (lazy N and Z flag) */
+#endif
+}   h6280_Regs;
+
+/* Function prototypes */
+void cpu_writeport16(int port, int data);
+void cpu_writemem21(int address, int data);
+int cpu_readmem21(int address);
+
+#endif /* _H6280_H */
diff --git a/MCUME_pico2/picopceold/h6280ops.h b/MCUME_pico2/picopceold/h6280ops.h
new file mode 100644
index 0000000..d6ff61d
--- /dev/null
+++ b/MCUME_pico2/picopceold/h6280ops.h
@@ -0,0 +1,1203 @@
+
+/*****************************************************************************
+
+	h6280ops.h - Addressing modes and opcode macros for the Hu6820 cpu
+
+	Copyright (c) 1999 Bryan McPhail, mish@tendril.co.uk
+
+	This source code is based (with permission!) on the 6502 emulator by
+	Juergen Buchmueller.  It is released as part of the Mame emulator project.
+	Let me know if you intend to use this code in any other project.
+
+******************************************************************************/
+
+/* 6280 flags */
+#define _fC 0x01
+#define _fZ 0x02
+#define _fI 0x04
+#define _fD 0x08
+#define _fB 0x10
+#define _fT 0x20
+#define _fV 0x40
+#define _fN 0x80
+
+/* some shortcuts for improved readability */
+#define A	h6280.a
+#define X	h6280.x
+#define Y	h6280.y
+#define P	h6280.p
+#define S	h6280.sp.b.l
+
+#if LAZY_FLAGS
+
+#define NZ	h6280.NZ
+#define SET_NZ(n)				\
+	P &= ~_fT;					\
+    NZ = ((n & _fN) << 8) | n
+
+#else
+
+#define SET_NZ(n)				\
+	P = (P & ~(_fN|_fT|_fZ)) |	\
+		(n & _fN) | 			\
+		((n == 0) ? _fZ : 0)
+
+#endif
+
+#define EAL h6280.ea.b.l
+#define EAH h6280.ea.b.h
+#define EAW h6280.ea.w.l
+#define EAD h6280.ea.d
+
+#define ZPL h6280.zp.b.l
+#define ZPH h6280.zp.b.h
+#define ZPW h6280.zp.w.l
+#define ZPD h6280.zp.d
+
+#define PCL h6280.pc.b.l
+#define PCH h6280.pc.b.h
+#define PCW h6280.pc.w.l
+#define PCD h6280.pc.d
+
+#define DO_INTERRUPT(vector)									\
+{																\
+	h6280.extra_cycles += 7;	/* 7 cycles for an int */		\
+	PUSH(PCH);													\
+	PUSH(PCL);													\
+	COMPOSE_P(0,_fB);											\
+	PUSH(P);													\
+	P = (P & ~_fD) | _fI;	/* knock out D and set I flag */	\
+	PCL = RDMEM(vector);										\
+	PCH = RDMEM((vector+1));									\
+}
+
+#define CHECK_IRQ_LINES 										\
+	if( !(P & _fI) )											\
+	{															\
+		if ( h6280.irq_state[0] != CLEAR_LINE &&				\
+			 !(h6280.irq_mask & 0x2) )							\
+		{														\
+			DO_INTERRUPT(H6280_IRQ1_VEC);						\
+			(*h6280.irq_callback)(0);							\
+		}														\
+		else													\
+		if ( h6280.irq_state[1] != CLEAR_LINE &&				\
+			 !(h6280.irq_mask & 0x1) )							\
+		{														\
+			DO_INTERRUPT(H6280_IRQ2_VEC);						\
+			(*h6280.irq_callback)(1);							\
+        }                                                       \
+		else													\
+        if ( h6280.irq_state[2] != CLEAR_LINE &&                \
+			 !(h6280.irq_mask & 0x4) )							\
+		{														\
+			h6280.irq_state[2] = CLEAR_LINE;					\
+ 			DO_INTERRUPT(H6280_TIMER_VEC);						\
+       }                                                       	\
+    }
+
+
+/***************************************************************
+ *  RDMEM   read memory
+ ***************************************************************/
+#define RDMEM(addr) 											\
+	cpu_readmem21( (h6280.mmr[(addr)>>13] << 13) | ((addr)&0x1fff))
+
+/***************************************************************
+ *  WRMEM   write memory
+ ***************************************************************/
+#define WRMEM(addr,data)										\
+	cpu_writemem21( (h6280.mmr[(addr)>>13] << 13) | ((addr)&0x1fff),data);
+
+/***************************************************************
+ *  RDMEMW   read word from memory
+ ***************************************************************/
+#define RDMEMW(addr)											\
+    cpu_readmem21( (h6280.mmr[(addr)  >>13] << 13) | ((addr  )&0x1fff)) \
+| ( cpu_readmem21( (h6280.mmr[(addr+1)>>13] << 13) | ((addr+1)&0x1fff)) << 8 )
+
+/***************************************************************
+ *  RDMEMZ   read memory - zero page
+ ***************************************************************/
+#define RDMEMZ(addr) 											\
+    cpu_readmem21( (h6280.mmr[1] << 13) | ((addr)&0x1fff));
+
+/***************************************************************
+ *  WRMEMZ   write memory - zero page
+ ***************************************************************/
+#define WRMEMZ(addr,data) 										\
+    cpu_writemem21( (h6280.mmr[1] << 13) | ((addr)&0x1fff),data);
+
+/***************************************************************
+ *  RDZPWORD    read a word from a zero page address
+ ***************************************************************/
+#define RDZPWORD(addr)											\
+	((addr&0xff)==0xff) ?										\
+		cpu_readmem21( (h6280.mmr[1] << 13) | ((addr)&0x1fff))				\
+		+(cpu_readmem21( (h6280.mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
+		cpu_readmem21( (h6280.mmr[1] << 13) | ((addr)&0x1fff))				\
+		+(cpu_readmem21( (h6280.mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
+
+/***************************************************************
+ * push a register onto the stack
+ ***************************************************************/
+#define PUSH(Rg) cpu_writemem21( (h6280.mmr[1] << 13) | h6280.sp.d,Rg); S--
+
+/***************************************************************
+ * pull a register from the stack
+ ***************************************************************/
+#define PULL(Rg) S++; Rg = cpu_readmem21( (h6280.mmr[1] << 13) | h6280.sp.d)
+
+/***************************************************************
+ *  RDOP    read an opcode
+ ***************************************************************/
+#define RDOP()													\
+    cpu_readmem21((h6280.mmr[PCW>>13] << 13) | (PCW&0x1fff))
+
+/***************************************************************
+ *  RDOPARG read an opcode argument
+ ***************************************************************/
+#define RDOPARG()												\
+    cpu_readmem21((h6280.mmr[PCW>>13] << 13) | (PCW&0x1fff))
+
+
+/***************************************************************
+ *	BRA  branch relative
+ ***************************************************************/
+#define BRA(cond)												\
+	if (cond)													\
+	{															\
+		h6280_ICount -= 4;										\
+		tmp = RDOPARG();										\
+		PCW++;													\
+		EAW = PCW + (signed char)tmp;							\
+		PCD = EAD;												\
+	}															\
+	else														\
+	{															\
+		PCW++;													\
+		h6280_ICount -= 2;										\
+	}
+
+/***************************************************************
+ *
+ * Helper macros to build the effective address
+ *
+ ***************************************************************/
+
+/***************************************************************
+ *  EA = zero page address
+ ***************************************************************/
+#define EA_ZPG													\
+	ZPL = RDOPARG();											\
+	PCW++;														\
+	EAD = ZPD
+
+/***************************************************************
+ *  EA = zero page address + X
+ ***************************************************************/
+#define EA_ZPX													\
+	ZPL = RDOPARG() + X;										\
+	PCW++;														\
+	EAD = ZPD
+
+/***************************************************************
+ *  EA = zero page address + Y
+ ***************************************************************/
+#define EA_ZPY													\
+	ZPL = RDOPARG() + Y;										\
+	PCW++;														\
+	EAD = ZPD
+
+/***************************************************************
+ *  EA = absolute address
+ ***************************************************************/
+#define EA_ABS													\
+	EAL = RDOPARG();											\
+	PCW++;														\
+	EAH = RDOPARG();											\
+	PCW++
+
+/***************************************************************
+ *  EA = absolute address + X
+ ***************************************************************/
+#define EA_ABX                                                  \
+	EA_ABS; 													\
+	EAW += X
+
+/***************************************************************
+ *	EA = absolute address + Y
+ ***************************************************************/
+#define EA_ABY													\
+	EA_ABS; 													\
+	EAW += Y
+
+/***************************************************************
+ *	EA = zero page indirect (65c02 pre indexed w/o X)
+ ***************************************************************/
+#define EA_ZPI													\
+	ZPL = RDOPARG();											\
+	PCW++;														\
+	EAD = RDZPWORD(ZPD)
+
+/***************************************************************
+ *  EA = zero page + X indirect (pre indexed)
+ ***************************************************************/
+#define EA_IDX													\
+	ZPL = RDOPARG() + X;										\
+	PCW++;														\
+	EAD = RDZPWORD(ZPD);
+
+/***************************************************************
+ *  EA = zero page indirect + Y (post indexed)
+ ***************************************************************/
+#define EA_IDY													\
+	ZPL = RDOPARG();											\
+	PCW++;														\
+	EAD = RDZPWORD(ZPD);										\
+	EAW += Y
+
+/***************************************************************
+ *	EA = indirect (only used by JMP)
+ ***************************************************************/
+#define EA_IND													\
+	EA_ABS; 													\
+	tmp = RDMEM(EAD);											\
+	EAD++; 														\
+	EAH = RDMEM(EAD);											\
+	EAL = tmp
+
+/***************************************************************
+ *	EA = indirect plus x (only used by JMP)
+ ***************************************************************/
+#define EA_IAX                                                  \
+	EA_ABS;														\
+	EAD+=X;														\
+	tmp = RDMEM(EAD);											\
+	EAD++; 	 													\
+	EAH = RDMEM(EAD);											\
+	EAL = tmp
+
+/* read a value into tmp */
+#define RD_IMM	tmp = RDOPARG(); PCW++
+#define RD_IMM2	tmp2 = RDOPARG(); PCW++
+#define RD_ACC	tmp = A
+#define RD_ZPG	EA_ZPG; tmp = RDMEMZ(EAD)
+#define RD_ZPX	EA_ZPX; tmp = RDMEMZ(EAD)
+#define RD_ZPY	EA_ZPY; tmp = RDMEMZ(EAD)
+#define RD_ABS	EA_ABS; tmp = RDMEM(EAD)
+#define RD_ABX	EA_ABX; tmp = RDMEM(EAD)
+#define RD_ABY	EA_ABY; tmp = RDMEM(EAD)
+#define RD_ZPI	EA_ZPI; tmp = RDMEM(EAD)
+#define RD_IDX	EA_IDX; tmp = RDMEM(EAD)
+#define RD_IDY	EA_IDY; tmp = RDMEM(EAD)
+
+/* write a value from tmp */
+#define WR_ZPG	EA_ZPG; WRMEMZ(EAD, tmp)
+#define WR_ZPX	EA_ZPX; WRMEMZ(EAD, tmp)
+#define WR_ZPY	EA_ZPY; WRMEMZ(EAD, tmp)
+#define WR_ABS	EA_ABS; WRMEM(EAD, tmp)
+#define WR_ABX	EA_ABX; WRMEM(EAD, tmp)
+#define WR_ABY	EA_ABY; WRMEM(EAD, tmp)
+#define WR_ZPI	EA_ZPI; WRMEM(EAD, tmp)
+#define WR_IDX	EA_IDX; WRMEM(EAD, tmp)
+#define WR_IDY	EA_IDY; WRMEM(EAD, tmp)
+
+/* write back a value from tmp to the last EA */
+#define WB_ACC	A = (UINT8)tmp;
+#define WB_EA	WRMEM(EAD, tmp)
+#define WB_EAZ	WRMEMZ(EAD, tmp)
+
+/***************************************************************
+ *
+ * Macros to emulate the 6280 opcodes
+ *
+ ***************************************************************/
+
+/***************************************************************
+ * compose the real flag register by
+ * including N and Z and set any
+ * SET and clear any CLR bits also
+ ***************************************************************/
+#if LAZY_FLAGS
+
+#define COMPOSE_P(SET,CLR)										\
+	P = (P & ~(_fN | _fZ | CLR)) |								\
+		(NZ >> 8) | 											\
+		((NZ & 0xff) ? 0 : _fZ) |								\
+		SET
+
+#else
+
+#define COMPOSE_P(SET,CLR)										\
+	P = (P & ~CLR) | SET
+
+#endif
+
+/* 6280 ********************************************************
+ *	ADC Add with carry
+ ***************************************************************/
+#define ADC 													\
+	if (P & _fD)												\
+	{															\
+	int c = (P & _fC);											\
+	int lo = (A & 0x0f) + (tmp & 0x0f) + c; 					\
+	int hi = (A & 0xf0) + (tmp & 0xf0); 						\
+		P &= ~(_fV | _fC);										\
+		if (lo > 0x09)											\
+		{														\
+			hi += 0x10; 										\
+			lo += 0x06; 										\
+		}														\
+		if (~(A^tmp) & (A^hi) & _fN)							\
+			P |= _fV;											\
+		if (hi > 0x90)											\
+			hi += 0x60; 										\
+		if (hi & 0xff00)										\
+			P |= _fC;											\
+		A = (lo & 0x0f) + (hi & 0xf0);							\
+	}															\
+	else														\
+	{															\
+	int c = (P & _fC);											\
+	int sum = A + tmp + c;										\
+		P &= ~(_fV | _fC);										\
+		if (~(A^tmp) & (A^sum) & _fN)							\
+			P |= _fV;											\
+		if (sum & 0xff00)										\
+			P |= _fC;											\
+		A = (UINT8) sum;										\
+	}															\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	AND Logical and
+ ***************************************************************/
+#define AND 													\
+	A = (UINT8)(A & tmp);										\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	ASL Arithmetic shift left
+ ***************************************************************/
+#define ASL 													\
+	P = (P & ~_fC) | ((tmp >> 7) & _fC);						\
+	tmp = (UINT8)(tmp << 1);									\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *  BBR Branch if bit is reset
+ ***************************************************************/
+#define BBR(bit)                                                \
+    BRA(!(tmp & (1<<bit)))
+
+/* 6280 ********************************************************
+ *  BBS Branch if bit is set
+ ***************************************************************/
+#define BBS(bit)                                                \
+    BRA(tmp & (1<<bit))
+
+/* 6280 ********************************************************
+ *	BCC Branch if carry clear
+ ***************************************************************/
+#define BCC BRA(!(P & _fC))
+
+/* 6280 ********************************************************
+ *	BCS Branch if carry set
+ ***************************************************************/
+#define BCS BRA(P & _fC)
+
+/* 6280 ********************************************************
+ *	BEQ Branch if equal
+ ***************************************************************/
+#if LAZY_FLAGS
+#define BEQ BRA(!(NZ & 0xff))
+#else
+#define BEQ BRA(P & _fZ)
+#endif
+
+/* 6280 ********************************************************
+ *	BIT Bit test
+ ***************************************************************/
+#define BIT														\
+	P = (P & ~(_fN|_fV|_fT|_fZ))								\
+		| ((tmp&0x80) ? _fN:0)									\
+		| ((tmp&0x40) ? _fV:0)									\
+		| ((tmp&A)  ? 0:_fZ)
+
+/* 6280 ********************************************************
+ *	BMI Branch if minus
+ ***************************************************************/
+#if LAZY_FLAGS
+#define BMI BRA(NZ & 0x8000)
+#else
+#define BMI BRA(P & _fN)
+#endif
+
+/* 6280 ********************************************************
+ *	BNE Branch if not equal
+ ***************************************************************/
+#if LAZY_FLAGS
+#define BNE BRA(NZ & 0xff)
+#else
+#define BNE BRA(!(P & _fZ))
+#endif
+
+/* 6280 ********************************************************
+ *	BPL Branch if plus
+ ***************************************************************/
+#if LAZY_FLAGS
+#define BPL BRA(!(NZ & 0x8000))
+#else
+#define BPL BRA(!(P & _fN))
+#endif
+
+/* 6280 ********************************************************
+ *	BRK Break
+ *	increment PC, push PC hi, PC lo, flags (with B bit set),
+ *	set I flag, reset D flag and jump via IRQ vector
+ ***************************************************************/
+#define BRK 													\
+	PCW++;														\
+	PUSH(PCH);													\
+	PUSH(PCL);													\
+	PUSH(P | _fB);												\
+	P = (P & ~_fD) | _fI;										\
+	PCL = RDMEM(H6280_IRQ2_VEC); 								\
+	PCH = RDMEM(H6280_IRQ2_VEC+1)
+
+/* 6280 ********************************************************
+ *	BSR Branch to subroutine
+ ***************************************************************/
+#define BSR 													\
+	PUSH(PCH);													\
+	PUSH(PCL);													\
+	h6280_ICount -= 4; /* 4 cycles here, 4 in BRA */			\
+	BRA(1)
+
+/* 6280 ********************************************************
+ *	BVC Branch if overflow clear
+ ***************************************************************/
+#define BVC BRA(!(P & _fV))
+
+/* 6280 ********************************************************
+ *	BVS Branch if overflow set
+ ***************************************************************/
+#define BVS BRA(P & _fV)
+
+/* 6280 ********************************************************
+ *  CLA Clear accumulator
+ ***************************************************************/
+#define CLA                                                     \
+    A = 0
+
+/* 6280 ********************************************************
+ *	CLC Clear carry flag
+ ***************************************************************/
+#define CLC 													\
+	P &= ~_fC
+
+/* 6280 ********************************************************
+ *	CLD Clear decimal flag
+ ***************************************************************/
+#define CLD 													\
+	P &= ~_fD
+
+/* 6280 ********************************************************
+ *	CLI Clear interrupt flag
+ ***************************************************************/
+#define CLI 													\
+	if( P & _fI )												\
+	{															\
+		P &= ~_fI;												\
+		CHECK_IRQ_LINES;										\
+	}
+
+
+/* 6280 ********************************************************
+ *	CLV Clear overflow flag
+ ***************************************************************/
+#define CLV 													\
+	P &= ~_fV
+
+/* 6280 ********************************************************
+ *  CLX Clear index X
+ ***************************************************************/
+#define CLX                                                     \
+    X = 0
+
+/* 6280 ********************************************************
+ *  CLY Clear index Y
+ ***************************************************************/
+#define CLY                                                     \
+    Y = 0
+
+/* 6280 ********************************************************
+ *	CMP Compare accumulator
+ ***************************************************************/
+#define CMP 													\
+	P &= ~_fC;													\
+	if (A >= tmp)												\
+		P |= _fC;												\
+	SET_NZ((UINT8)(A - tmp))
+
+/* 6280 ********************************************************
+ *	CPX Compare index X
+ ***************************************************************/
+#define CPX 													\
+	P &= ~_fC;													\
+	if (X >= tmp)												\
+		P |= _fC;												\
+	SET_NZ((UINT8)(X - tmp))
+
+/* 6280 ********************************************************
+ *	CPY Compare index Y
+ ***************************************************************/
+#define CPY 													\
+	P &= ~_fC;													\
+	if (Y >= tmp)												\
+		P |= _fC;												\
+	SET_NZ((UINT8)(Y - tmp))
+
+/* 6280 ********************************************************
+ *  DEA Decrement accumulator
+ ***************************************************************/
+#define DEA                                                     \
+	A = (UINT8)--A; 											\
+    SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	DEC Decrement memory
+ ***************************************************************/
+#define DEC 													\
+	tmp = (UINT8)--tmp; 										\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *	DEX Decrement index X
+ ***************************************************************/
+#define DEX 													\
+	X = (UINT8)--X; 											\
+	SET_NZ(X)
+
+/* 6280 ********************************************************
+ *	DEY Decrement index Y
+ ***************************************************************/
+#define DEY 													\
+	Y = (UINT8)--Y; 											\
+	SET_NZ(Y)
+
+/* 6280 ********************************************************
+ *	EOR Logical exclusive or
+ ***************************************************************/
+#define EOR 													\
+	A = (UINT8)(A ^ tmp);										\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	ILL Illegal opcode
+ ***************************************************************/
+#define ILL 													\
+    h6280_ICount -= 2; /* (assumed) */                          
+
+/* 6280 ********************************************************
+ *  INA Increment accumulator
+ ***************************************************************/
+#define INA                                                     \
+	A = (UINT8)++A; 											\
+    SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	INC Increment memory
+ ***************************************************************/
+#define INC 													\
+	tmp = (UINT8)++tmp; 										\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *	INX Increment index X
+ ***************************************************************/
+#define INX 													\
+	X = (UINT8)++X; 											\
+	SET_NZ(X)
+
+/* 6280 ********************************************************
+ *	INY Increment index Y
+ ***************************************************************/
+#define INY 													\
+	Y = (UINT8)++Y; 											\
+	SET_NZ(Y)
+
+/* 6280 ********************************************************
+ *	JMP Jump to address
+ *	set PC to the effective address
+ ***************************************************************/
+#define JMP 													\
+	PCD = EAD
+
+/* 6280 ********************************************************
+ *	JSR Jump to subroutine
+ *	decrement PC (sic!) push PC hi, push PC lo and set
+ *	PC to the effective address
+ ***************************************************************/
+#define JSR 													\
+	PCW--;														\
+	PUSH(PCH);													\
+	PUSH(PCL);													\
+	PCD = EAD
+
+/* 6280 ********************************************************
+ *	LDA Load accumulator
+ ***************************************************************/
+#define LDA 													\
+	A = (UINT8)tmp; 											\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	LDX Load index X
+ ***************************************************************/
+#define LDX 													\
+	X = (UINT8)tmp; 											\
+	SET_NZ(X)
+
+/* 6280 ********************************************************
+ *	LDY Load index Y
+ ***************************************************************/
+#define LDY 													\
+	Y = (UINT8)tmp; 											\
+	SET_NZ(Y)
+
+/* 6280 ********************************************************
+ *	LSR Logic shift right
+ *	0 -> [7][6][5][4][3][2][1][0] -> C
+ ***************************************************************/
+#define LSR 													\
+	P = (P & ~_fC) | (tmp & _fC);								\
+	tmp = (UINT8)tmp >> 1;										\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *	NOP No operation
+ ***************************************************************/
+#define NOP
+
+/* 6280 ********************************************************
+ *	ORA Logical inclusive or
+ ***************************************************************/
+#define ORA 													\
+	A = (UINT8)(A | tmp);										\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	PHA Push accumulator
+ ***************************************************************/
+#define PHA 													\
+	PUSH(A)
+
+/* 6280 ********************************************************
+ *	PHP Push processor status (flags)
+ ***************************************************************/
+#define PHP 													\
+	COMPOSE_P(0,0); 											\
+	PUSH(P)
+
+/* 6280 ********************************************************
+ *  PHX Push index X
+ ***************************************************************/
+#define PHX                                                     \
+    PUSH(X)
+
+/* 6280 ********************************************************
+ *  PHY Push index Y
+ ***************************************************************/
+#define PHY                                                     \
+    PUSH(Y)
+
+/* 6280 ********************************************************
+ *	PLA Pull accumulator
+ ***************************************************************/
+#define PLA 													\
+	PULL(A);													\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	PLP Pull processor status (flags)
+ ***************************************************************/
+#if LAZY_FLAGS
+
+#define PLP 													\
+	PULL(P);													\
+	NZ = ((P & _fN) << 8) | 									\
+		 ((P & _fZ) ^ _fZ); 									\
+	CHECK_IRQ_LINES
+
+#else
+
+#define PLP 													\
+	PULL(P); 													\
+	CHECK_IRQ_LINES
+#endif
+
+/* 6280 ********************************************************
+ *  PLX Pull index X
+ ***************************************************************/
+#define PLX                                                     \
+    PULL(X)
+
+/* 6280 ********************************************************
+ *  PLY Pull index Y
+ ***************************************************************/
+#define PLY                                                     \
+    PULL(Y)
+
+/* 6280 ********************************************************
+ *  RMB Reset memory bit
+ ***************************************************************/
+#define RMB(bit)                                                \
+    tmp &= ~(1<<bit)
+
+/* 6280 ********************************************************
+ *	ROL Rotate left
+ *	new C <- [7][6][5][4][3][2][1][0] <- C
+ ***************************************************************/
+#define ROL 													\
+	tmp = (tmp << 1) | (P & _fC);								\
+	P = (P & ~_fC) | ((tmp >> 8) & _fC);						\
+	tmp = (UINT8)tmp;											\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *	ROR Rotate right
+ *	C -> [7][6][5][4][3][2][1][0] -> new C
+ ***************************************************************/
+#define ROR 													\
+	tmp |= (P & _fC) << 8;										\
+	P = (P & ~_fC) | (tmp & _fC);								\
+	tmp = (UINT8)(tmp >> 1);									\
+	SET_NZ(tmp)
+
+/* 6280 ********************************************************
+ *	RTI Return from interrupt
+ *	pull flags, pull PC lo, pull PC hi and increment PC
+ ***************************************************************/
+#if LAZY_FLAGS
+
+#define RTI 													\
+	PULL(P);													\
+	NZ = ((P & _fN) << 8) | 									\
+		 ((P & _fZ) ^ _fZ); 									\
+	PULL(PCL);													\
+	PULL(PCH);													\
+	CHECK_IRQ_LINES
+#else
+
+#define RTI 													\
+	PULL(P);													\
+	PULL(PCL);													\
+	PULL(PCH);													\
+	CHECK_IRQ_LINES
+#endif
+
+/* 6280 ********************************************************
+ *	RTS Return from subroutine
+ *	pull PC lo, PC hi and increment PC
+ ***************************************************************/
+#define RTS 													\
+	PULL(PCL);													\
+	PULL(PCH);													\
+	PCW++;														\
+
+/* 6280 ********************************************************
+ *  SAX Swap accumulator and index X
+ ***************************************************************/
+#define SAX                                                     \
+    tmp = X;                                                    \
+    X = A;                                                      \
+    A = tmp
+
+/* 6280 ********************************************************
+ *  SAY Swap accumulator and index Y
+ ***************************************************************/
+#define SAY                                                     \
+    tmp = Y;                                                    \
+    Y = A;                                                      \
+    A = tmp
+
+/* 6280 ********************************************************
+ *	SBC Subtract with carry
+ ***************************************************************/
+#define SBC 													\
+	if (P & _fD)												\
+	{															\
+	int c = (P & _fC) ^ _fC;									\
+	int sum = A - tmp - c;										\
+	int lo = (A & 0x0f) - (tmp & 0x0f) - c; 					\
+	int hi = (A & 0xf0) - (tmp & 0xf0); 						\
+		P &= ~(_fV | _fC);										\
+		if ((A^tmp) & (A^sum) & _fN)							\
+			P |= _fV;											\
+		if (lo & 0xf0)											\
+			lo -= 6;											\
+		if (lo & 0x80)											\
+			hi -= 0x10; 										\
+		if (hi & 0x0f00)										\
+			hi -= 0x60; 										\
+		if ((sum & 0xff00) == 0)								\
+			P |= _fC;											\
+		A = (lo & 0x0f) + (hi & 0xf0);							\
+	}															\
+	else														\
+	{															\
+	int c = (P & _fC) ^ _fC;									\
+	int sum = A - tmp - c;										\
+		P &= ~(_fV | _fC);										\
+		if ((A^tmp) & (A^sum) & _fN)							\
+			P |= _fV;											\
+		if ((sum & 0xff00) == 0)								\
+			P |= _fC;											\
+		A = (UINT8) sum;										\
+	}															\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	SEC Set carry flag
+ ***************************************************************/
+#define SEC 													\
+	P |= _fC
+
+/* 6280 ********************************************************
+ *	SED Set decimal flag
+ ***************************************************************/
+#define SED 													\
+	P |= _fD
+
+/* 6280 ********************************************************
+ *	SEI Set interrupt flag
+ ***************************************************************/
+#define SEI 													\
+	P |= _fI
+
+/* 6280 ********************************************************
+ *  SET Set t flag
+ *  T flag = Memory operation flag.
+ *
+ *  Instruction immediately after SET will use the byte in the zero
+ *  page area indexed by X, if it is ADC, AND, ORA, EOR with an
+ *  immediate operand.
+ *
+ *  Else, the function of the memory operation flag is ignored
+ *  and the instruction executes like normal.
+ *
+ *  Other possible uses:
+ *  Legendary Axe I/II (sed set sbc)
+ *  Bravoman (set sbc)
+ *  Magical Chase (set cpx)
+ ***************************************************************/
+
+#define SET                                                     \
+{                                                               \
+    int op, tmp;                                                \
+    op = RDOP(); /* Get next instruction */                     \
+    if((op & 0x9F) == 0x09)                                     \
+    {                                                           \
+        UINT8 acc;                                              \
+        PCW++;                                                  \
+        tmp = RDOPARG(); /* Immediate operand */                \
+        PCW++;                                                  \
+        acc = RDMEMZ(X); /* Used instead of accmulator */       \
+                                                                \
+        switch(op)                                              \
+        {                                                       \
+            case 0x09: acc = (UINT8)(acc | tmp); break; /* ORA */ \
+            case 0x29: acc = (UINT8)(acc & tmp); break; /* AND */ \
+            case 0x49: acc = (UINT8)(acc ^ tmp); break; /* EOR */ \
+            case 0x69: /* ADC */                                \
+                if(P & _fD)                                     \
+                {                                               \
+                    int c = (P & _fC);                          \
+                    int lo = (acc & 0x0F) + (tmp & 0x0F) + c;   \
+                    int hi = (acc & 0xF0) + (tmp & 0xF0);       \
+                    P &= ~(_fV | _fC);                          \
+                    if(lo > 0x09) { hi += 0x10; lo += 0x06; };  \
+                    if(~(acc^tmp) & (acc^hi) & _fN) P |= _fV;   \
+                    if(hi > 0x90) hi += 0x60;                   \
+                    if(hi & 0xFF00) P |= _fC;                   \
+                    acc = (lo & 0x0F) + (hi & 0xF0);            \
+                }                                               \
+                else                                            \
+                {                                               \
+                    int c = (P & _fC);                          \
+                    int sum = acc + tmp + c;                    \
+                    P &= ~(_fV | _fC);                          \
+                    if (~(acc^tmp) & (acc^sum) & _fN)           \
+                        P |= _fV;                               \
+                    if (sum & 0xff00)                           \
+                        P |= _fC;                               \
+                    acc = (UINT8) sum;                          \
+                }                                               \
+                break;                                          \
+        }                                                       \
+                                                                \
+        SET_NZ(acc);        /* Update flags */                  \
+        WRMEMZ(X, acc);     /* Write result back */             \
+        h6280_ICount -= 6;  /* Unsure of actual cycles used */  \
+    }                                                           \
+    P &= ~_fT;                                                  \
+}                                                               
+
+
+
+
+/* 6280 ********************************************************
+ *  CSL Clock select low
+ ***************************************************************/
+#define CSL             \
+    h6280_speed = 0
+
+/* 6280 ********************************************************
+ *  CSL Clock select high
+ ***************************************************************/
+#define CSH             \
+    h6280_speed = 1    
+
+/* 6280 ********************************************************
+ *  SMB Set memory bit
+ ***************************************************************/
+#define SMB(bit)                                                \
+    tmp |= (1<<bit)
+
+
+/* 6280 ********************************************************
+ *  ST0 Store at hardware address 0
+ ***************************************************************/
+#define ST0                                                     \
+    cpu_writeport16(0x0000,tmp)
+
+/* 6280 ********************************************************
+ *  ST1 Store at hardware address 2
+ ***************************************************************/
+#define ST1                                                     \
+    cpu_writeport16(0x0002,tmp)
+
+/* 6280 ********************************************************
+ *  ST2 Store at hardware address 3
+ ***************************************************************/
+#define ST2                                                     \
+    cpu_writeport16(0x0003,tmp)
+
+
+/* 6280 ********************************************************
+ *	STA Store accumulator
+ ***************************************************************/
+#define STA 													\
+	tmp = A
+
+/* 6280 ********************************************************
+ *	STX Store index X
+ ***************************************************************/
+#define STX 													\
+	tmp = X
+
+/* 6280 ********************************************************
+ *	STY Store index Y
+ ***************************************************************/
+#define STY 													\
+	tmp = Y
+
+/* 6280 ********************************************************
+ * STZ  Store zero
+ ***************************************************************/
+#define STZ                                                     \
+    tmp = 0
+
+/* H6280 *******************************************************
+ *  SXY Swap index X and index Y
+ ***************************************************************/
+#define SXY                                                    \
+    tmp = X;                                                   \
+    X = Y;                                                     \
+    Y = tmp
+
+/* H6280 *******************************************************
+ *  TAI
+ ***************************************************************/
+#define TAI 													\
+	from=RDMEMW(PCW);											\
+	to  =RDMEMW(PCW+2);											\
+	length=RDMEMW(PCW+4);										\
+	PCW+=6; 													\
+	alternate=0; 												\
+	while ((length--) != 0) { 									\
+		WRMEM(to,RDMEM(from+alternate)); 						\
+		to++; 													\
+		alternate ^= 1; 										\
+	}		 													\
+	h6280_ICount-=(6 * length) + 17;
+
+/* H6280 *******************************************************
+ *  TAM Transfer accumulator to memory mapper register(s)
+ ***************************************************************/
+
+
+#define TAM                                                     \
+    if (tmp&0x01) h6280.mmr[0] = A;                             \
+    if (tmp&0x02) h6280.mmr[1] = A;                             \
+    if (tmp&0x04) h6280.mmr[2] = A;                             \
+    if (tmp&0x08) h6280.mmr[3] = A;                             \
+    if (tmp&0x10) h6280.mmr[4] = A;                             \
+    if (tmp&0x20) h6280.mmr[5] = A;                             \
+    if (tmp&0x40) h6280.mmr[6] = A;                             \
+    if (tmp&0x80) h6280.mmr[7] = A
+
+
+/* 6280 ********************************************************
+ *	TAX Transfer accumulator to index X
+ ***************************************************************/
+#define TAX 													\
+	X = A;														\
+	SET_NZ(X)
+
+/* 6280 ********************************************************
+ *	TAY Transfer accumulator to index Y
+ ***************************************************************/
+#define TAY 													\
+	Y = A;														\
+	SET_NZ(Y)
+
+/* 6280 ********************************************************
+ *  TDD
+ ***************************************************************/
+#define TDD 													\
+	from=RDMEMW(PCW);											\
+	to  =RDMEMW(PCW+2);											\
+	length=RDMEMW(PCW+4);										\
+	PCW+=6; 													\
+	while ((length--) != 0) { 									\
+		WRMEM(to,RDMEM(from)); 									\
+		to--; 													\
+		from--;													\
+	}		 													\
+	h6280_ICount-=(6 * length) + 17;
+
+/* 6280 ********************************************************
+ *  TIA
+ ***************************************************************/
+#define TIA 													\
+	from=RDMEMW(PCW);											\
+	to  =RDMEMW(PCW+2);											\
+	length=RDMEMW(PCW+4);										\
+	PCW+=6; 													\
+	alternate=0; 												\
+	while ((length--) != 0) { 									\
+		WRMEM(to+alternate,RDMEM(from));						\
+		from++; 												\
+		alternate ^= 1; 										\
+	}		 													\
+	h6280_ICount-=(6 * length) + 17;
+
+/* 6280 ********************************************************
+ *  TII
+ ***************************************************************/
+#define TII 													\
+	from=RDMEMW(PCW);											\
+	to  =RDMEMW(PCW+2);											\
+	length=RDMEMW(PCW+4);										\
+	PCW+=6; 													\
+	while ((length--) != 0) { 									\
+		WRMEM(to,RDMEM(from)); 									\
+		to++; 													\
+		from++;													\
+	}		 													\
+	h6280_ICount-=(6 * length) + 17;
+
+/* 6280 ********************************************************
+ *  TIN Transfer block, source increments every loop
+ ***************************************************************/
+#define TIN 													\
+	from=RDMEMW(PCW);											\
+	to  =RDMEMW(PCW+2);											\
+	length=RDMEMW(PCW+4);										\
+	PCW+=6; 													\
+	while ((length--) != 0) { 									\
+		WRMEM(to,RDMEM(from)); 									\
+		from++;													\
+	}		 													\
+	h6280_ICount-=(6 * length) + 17;
+
+/* 6280 ********************************************************
+ *  TMA Transfer memory mapper register(s) to accumulator
+ *  the highest bit set in tmp is the one that counts
+ ***************************************************************/
+#define TMA                                                     \
+    if (tmp&0x01) A = h6280.mmr[0];                             \
+    else                                                        \
+    if (tmp&0x02) A = h6280.mmr[1];                             \
+    else                                                        \
+    if (tmp&0x04) A = h6280.mmr[2];                             \
+    else                                                        \
+    if (tmp&0x08) A = h6280.mmr[3];                             \
+    else                                                        \
+    if (tmp&0x10) A = h6280.mmr[4];                             \
+    else                                                        \
+    if (tmp&0x20) A = h6280.mmr[5];                             \
+    else                                                        \
+    if (tmp&0x40) A = h6280.mmr[6];                             \
+    else                                                        \
+    if (tmp&0x80) A = h6280.mmr[7]
+
+/* 6280 ********************************************************
+ * TRB  Test and reset bits
+ ***************************************************************/
+#define TRB                                                   	\
+	P = (P & ~(_fN|_fV|_fT|_fZ))								\
+		| ((tmp&0x80) ? _fN:0)									\
+		| ((tmp&0x40) ? _fV:0)									\
+		| ((tmp&A)  ? 0:_fZ);									\
+    tmp &= ~A
+
+/* 6280 ********************************************************
+ * TSB  Test and set bits
+ ***************************************************************/
+#define TSB                                                     \
+	P = (P & ~(_fN|_fV|_fT|_fZ))								\
+		| ((tmp&0x80) ? _fN:0)									\
+		| ((tmp&0x40) ? _fV:0)									\
+		| ((tmp&A)  ? 0:_fZ);									\
+    tmp |= A
+
+/* 6280 ********************************************************
+ *	TSX Transfer stack LSB to index X
+ ***************************************************************/
+#define TSX 													\
+	X = S;														\
+	SET_NZ(X)
+
+/* 6280 ********************************************************
+ *	TST
+ ***************************************************************/
+#define TST														\
+	P = (P & ~(_fN|_fV|_fT|_fZ))								\
+		| ((tmp2&0x80) ? _fN:0)									\
+		| ((tmp2&0x40) ? _fV:0)									\
+		| ((tmp2&tmp)  ? 0:_fZ)
+
+/* 6280 ********************************************************
+ *	TXA Transfer index X to accumulator
+ ***************************************************************/
+#define TXA 													\
+	A = X;														\
+	SET_NZ(A)
+
+/* 6280 ********************************************************
+ *	TXS Transfer index X to stack LSB
+ *	no flags changed (sic!)
+ ***************************************************************/
+#define TXS 													\
+	S = X
+
+/* 6280 ********************************************************
+ *	TYA Transfer index Y to accumulator
+ ***************************************************************/
+#define TYA 													\
+	A = Y;														\
+	SET_NZ(A)
diff --git a/MCUME_pico2/picopceold/keyboard_osd.h b/MCUME_pico2/picopceold/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picopceold/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picopceold/memory.c b/MCUME_pico2/picopceold/memory.c
new file mode 100644
index 0000000..34070c3
--- /dev/null
+++ b/MCUME_pico2/picopceold/memory.c
@@ -0,0 +1,53 @@
+#include "shared.h"
+
+//static uint8 lpceram[0x8000];
+static uint8 lvram[0x10000];
+static uint8 lobjram[0x200];
+static uint8 lbram[0x2000];
+
+static uint8 lbg_name_dirty[0x800];
+static uint16 lbg_name_list[0x800];
+static uint16 lobj_name_dirty[0x200];
+static uint16 lobj_name_list[0x200];
+static uint8 lbg_pattern_cache[BG_CACHE_SIZE];
+//static uint8 lobj_pattern_cache[OBJ_CACHE_SIZE]; 
+
+
+uint8 *  vram=&lvram[0];
+uint16 * vramw = (uint16 *)&lvram[0];
+uint8 * objram = &lobjram[0];
+uint16 *objramw = (uint16 *)&lobjram[0];
+uint8 *  pceram;// = &lpceram[0];
+#ifdef CDRAM    
+uint8 *  cdram;
+#endif
+uint8 *  bram=&lbram[0];
+
+uint8 * bg_name_dirty=&lbg_name_dirty[0];
+uint16 * bg_name_list=&lbg_name_list[0];
+uint16 * obj_name_dirty=&lobj_name_dirty[0];
+uint16 * obj_name_list=&lobj_name_list[0];
+uint8 * bg_pattern_cache;
+uint8 * obj_pattern_cache; 
+uint8 * bg_pattern_cache=&lbg_pattern_cache[0];
+//uint8 * obj_pattern_cache=&lobj_pattern_cache[0]; 
+
+#include "emuapi.h"
+
+void mem_init(void) {
+    //bg_pattern_cache = emu_Malloc(BG_CACHE_SIZE); 
+    obj_pattern_cache = emu_Malloc(OBJ_CACHE_SIZE); //0x20200000; 
+    pceram = emu_Malloc(0x8000);
+#ifdef CDRAM    
+    cdram = emu_Malloc(0x10000);
+#endif    
+    //emu_printh(obj_pattern_cache);
+}
+
+
+void memcpy_rom(int dst, int src, int size) {
+	while (size > 0) {   
+		write_rom(dst++, read_rom(src++));
+		size--;
+	}
+}
diff --git a/MCUME_pico2/picopceold/memory.h b/MCUME_pico2/picopceold/memory.h
new file mode 100644
index 0000000..8edae32
--- /dev/null
+++ b/MCUME_pico2/picopceold/memory.h
@@ -0,0 +1,32 @@
+#ifndef _MEMORY_H_
+#define _MEMORY_H_
+
+extern uint8 * vram;
+extern uint16 * vramw;
+extern uint8 * pceram;
+extern uint8 * cdram;
+extern uint8 * bram;
+
+extern uint8 * objram;
+extern uint16 *objramw;
+
+
+#define BG_CACHE_SIZE  0x20000
+#define OBJ_CACHE_SIZE 0x40000 //0x60000 //0x7E800 //0x80000
+
+extern uint8 * bg_pattern_cache;
+extern uint8 * obj_pattern_cache;
+extern uint8 * bg_name_dirty;
+extern uint16 * bg_name_list;
+extern uint16 * obj_name_dirty;
+extern uint16 * obj_name_list;
+
+
+
+
+extern void  mem_init(void);
+extern uint8 read_rom(int address);
+extern void  write_rom(int address, uint8 val);
+extern void memcpy_rom(int dst, int src, int size);
+
+#endif
diff --git a/MCUME_pico2/picopceold/osd_cpu.h b/MCUME_pico2/picopceold/osd_cpu.h
new file mode 100644
index 0000000..00d7fab
--- /dev/null
+++ b/MCUME_pico2/picopceold/osd_cpu.h
@@ -0,0 +1,79 @@
+/*******************************************************************************
+*																			   *
+*	Define size independent data types and operations.						   *
+*																			   *
+*   The following types must be supported by all platforms:					   *
+*																			   *
+*	UINT8  - Unsigned 8-bit Integer		INT8  - Signed 8-bit integer           *
+*	UINT16 - Unsigned 16-bit Integer	INT16 - Signed 16-bit integer          *
+*	UINT32 - Unsigned 32-bit Integer	INT32 - Signed 32-bit integer          *
+*	UINT64 - Unsigned 64-bit Integer	INT64 - Signed 64-bit integer          *
+*																			   *
+*																			   *
+*   The macro names for the artithmatic operations are composed as follows:    *
+*																			   *
+*   XXX_R_A_B, where XXX - 3 letter operation code (ADD, SUB, etc.)			   *
+*					 R   - The type	of the result							   *
+*					 A   - The type of operand 1							   *
+*			         B   - The type of operand 2 (if binary operation)		   *
+*																			   *
+*				     Each type is one of: U8,8,U16,16,U32,32,U64,64			   *
+*																			   *
+*******************************************************************************/
+
+
+#ifndef OSD_CPU_H
+#define OSD_CPU_H
+
+#include "shared.h"
+
+typedef unsigned char						UINT8;
+typedef unsigned short						UINT16;
+typedef unsigned int						UINT32;
+//__extension__ typedef unsigned long long	UINT64;
+typedef signed char 						INT8;
+typedef signed short						INT16;
+typedef signed int							INT32;
+//__extension__ typedef signed long long		INT64;
+
+/* Combine two 32-bit integers into a 64-bit integer */
+#define COMBINE_64_32_32(A,B)     ((((UINT64)(A))<<32) | (UINT32)(B))
+#define COMBINE_U64_U32_U32(A,B)  COMBINE_64_32_32(A,B)
+
+/* Return upper 32 bits of a 64-bit integer */
+#define HI32_32_64(A)		  (((UINT64)(A)) >> 32)
+#define HI32_U32_U64(A)		  HI32_32_64(A)
+
+/* Return lower 32 bits of a 64-bit integer */
+#define LO32_32_64(A)		  ((A) & 0xffffffff)
+#define LO32_U32_U64(A)		  LO32_32_64(A)
+
+#define DIV_64_64_32(A,B)	  ((A)/(B))
+#define DIV_U64_U64_U32(A,B)  ((A)/(UINT32)(B))
+
+#define MOD_32_64_32(A,B)	  ((A)%(B))
+#define MOD_U32_U64_U32(A,B)  ((A)%(UINT32)(B))
+
+#define MUL_64_32_32(A,B)	  ((A)*(INT64)(B))
+#define MUL_U64_U32_U32(A,B)  ((A)*(UINT64)(UINT32)(B))
+
+
+/******************************************************************************
+ * Union of UINT8, UINT16 and UINT32 in native endianess of the target
+ * This is used to access bytes and words in a machine independent manner.
+ * The upper bytes h2 and h3 normally contain zero (16 bit CPU cores)
+ * thus PAIR.d can be used to pass arguments to the memory system
+ * which expects 'int' really.
+ ******************************************************************************/
+typedef union {
+#ifdef LSB_FIRST
+	struct { UINT8 l,h,h2,h3; } b;
+	struct { UINT16 l,h; } w;
+#else
+	struct { UINT8 h3,h2,h,l; } b;
+	struct { UINT16 h,l; } w;
+#endif
+	UINT32 d;
+}	PAIR;
+
+#endif	/* defined OSD_CPU_H */
diff --git a/MCUME_pico2/picopceold/pce.c b/MCUME_pico2/picopceold/pce.c
new file mode 100644
index 0000000..db8d106
--- /dev/null
+++ b/MCUME_pico2/picopceold/pce.c
@@ -0,0 +1,439 @@
+#include "shared.h"
+#include "emuapi.h"
+
+#ifdef HAS_PSRAM
+#else
+#include "flash_t.h"
+extern int8 * flash_start;
+#endif
+
+/* System memory */
+//uint8 * pceram;         /* Work RAM */
+//uint8 * cdram;          /* CD unit RAM (64k) */
+//uint8 * bram;           /* Backup RAM (8K) */
+//static uint8 pcerom[0x100000*2];   /* HuCard ROM (1MB) */
+uint8 save_bram;        /* 1= BRAM registers were accessed */
+
+/* I/O port data */
+uint8 joy_sel = 0;
+uint8 joy_clr = 0;
+uint8 joy_cnt = 0;
+
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown functions                                          */
+/*--------------------------------------------------------------------------*/
+
+int pce_init(void)
+{
+    h6280_reset();
+    h6280_set_irq_callback(&pce_irq_callback);
+    return (1);
+}
+
+void pce_reset(void)
+{
+    joy_sel = joy_clr = joy_cnt = 0;
+    memset(pceram, 0, 0x8000);
+#ifdef CDRAM    
+    memset(cdram, 0, 0x10000);
+#endif    
+    h6280_reset();
+    h6280_set_irq_callback(&pce_irq_callback);
+}
+
+void pce_shutdown(void)
+{
+//  char buf[256];
+//	strcpy(buf, GetModulePath());
+//	strcat(buf,"\\pce.brm");
+//  if(save_bram) save_file(buf, bram, 0x2000);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Memory handlers                                                          */
+/*--------------------------------------------------------------------------*/
+
+
+void cpu_writeport16(int port, int data)
+{
+    vdc_w(port, data);
+}
+
+void cpu_writemem21(int address, int data)
+{
+    uint8 page = (address >> 13) & 0xFF;
+
+    /* RAM (F8) */
+    if(page == 0xF8 || page == 0xF9 || page == 0xFA || page == 0xFB) {
+        pceram[(address & 0x7FFF)] = data;
+        return;
+    }
+
+    /* I/O (FF) */
+    if(page == 0xFF) {
+        io_page_w(address & 0x1FFF, data);
+        return;
+    }
+    
+#ifdef CDRAM    
+    /* CD RAM */
+    if((page >= 0x80) && (page <= 0x87)) {
+        cdram[(address & 0xFFFF)] = data;
+        return;
+    }
+#endif
+    /* Backup RAM (F7) */
+    if(page == 0xF7) {
+        bram[(address & 0x1FFF)] = data;
+        return;
+    }
+
+//    DEBUGLOG("write %02X to %02X:%04X (%08X)\n", data, page, address & 0x1fff, h6280_get_reg(H6280_PC));
+}
+
+int cpu_readmem21(int address)
+{
+    uint8 page;
+
+    if(address <= 0x0FFFFF) return (read_rom(address));
+
+    page = (address >> 13) & 0xFF;
+
+    /* ROM (00-7F) */
+    if(page <= 0x7F) return (read_rom(address));
+
+    /* RAM (F8) */
+    if(page == 0xF8 || page == 0xF9 || page == 0xFA || page == 0xFB) return (pceram[(address & 0x7FFF)]);
+
+    /* I/O (FF) */
+    if(page == 0xFF) return (io_page_r(address & 0x1FFF));
+
+#ifdef CDRAM    
+    /* CD RAM */
+    if((page >= 0x80) && (page <= 0x87)) return (cdram[(address & 0xFFFF)]);
+#endif
+
+    /* Backup RAM (F7) */
+    if(page == 0xF7) return (bram[(address & 0x1FFF)]);
+
+//    DEBUGLOG("read %02X:%04X (%08X)\n", page, address & 0x1fff, h6280_get_reg(H6280_PC));
+    return (0xFF);
+}
+
+
+int pce_irq_callback(int irqline)
+{
+    return (0);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Hardware page handlers                                                   */
+/*--------------------------------------------------------------------------*/
+
+void io_page_w(int address, int data)
+{
+    switch(address & 0x1C00)
+    {
+        case 0x0000: /* VDC */
+            if(address <= 0x0003) { vdc_w(address, data); return; }
+            break;
+
+        case 0x0400: /* VCE */
+            if(address <= 0x0405) { vce_w(address, data); return; }
+            break;
+
+        case 0x0800: /* PSG */
+            if(address <= 0x0809) { psg_w(address, data); return; };
+            break;
+
+        case 0x0C00: /* Timer */
+            if(address == 0x0C00 || address == 0x0C01) { H6280_timer_w(address & 1, data); return; };
+            break;
+
+        case 0x1000: /* I/O */
+            if(address == 0x1000) { input_w(data); return; }
+            break;
+
+        case 0x1400: /* IRQ control */
+            if(address == 0x1402 || address == 0x1403) { H6280_irq_status_w(address & 1, data); return; };
+            break;
+
+        case 0x1800: /* CD-ROM */
+//            DEBUGLOG("cdrom %04X = %02X\n", address, data);
+            if(address == 0x1807) save_bram = 1;
+            break;
+
+        case 0x1C00: /* Expansion */
+            break;
+    }
+
+//    DEBUGLOG("write %02X to IO %04X (%08X)\n", data, address, h6280_get_reg(H6280_PC));
+}
+
+
+int io_page_r(int address)
+{
+    switch(address & 0x1C00)
+    {
+        case 0x0000: /* VDC */
+            if(address <= 0x0003) return (vdc_r(address));
+            break;
+
+        case 0x0400: /* VCE */
+            if(address <= 0x0405) return (vce_r(address));
+            break;
+
+        case 0x0800: /* PSG */
+            break;
+
+        case 0x0C00: /* Timer */
+            if(address == 0x0C00 || address == 0x0C01) return (H6280_timer_r(address & 1));
+            break;
+
+        case 0x1000: /* I/O */
+            if(address == 0x1000) return (input_r());
+            break;
+
+        case 0x1400: /* IRQ control */
+            if(address == 0x1402 || address == 0x1403) return (H6280_irq_status_r(address & 1));
+            break;
+
+        case 0x1800: /* CD-ROM */
+//            DEBUGLOG("cdrom %04X\n", address);
+            break;
+
+        case 0x1C00: /* Expansion */
+            break;
+    }
+
+//    DEBUGLOG("read IO %04X (%08X)\n", address, h6280_get_reg(H6280_PC));
+    return (0x00);
+}
+
+/*--------------------------------------------------------------------------*/
+/* Input routines                                                           */
+/*--------------------------------------------------------------------------*/
+
+void input_w(uint8 data)
+{
+    joy_sel = (data & 1);
+    joy_clr = (data >> 1) & 1;
+}
+
+uint8 input_r(void)
+{
+    uint8 temp = 0xFF;
+
+    if(input.pad[joy_cnt] & INPUT_LEFT)   temp &= ~0x80;
+    if(input.pad[joy_cnt] & INPUT_DOWN)   temp &= ~0x40;
+    if(input.pad[joy_cnt] & INPUT_RIGHT)  temp &= ~0x20;
+    if(input.pad[joy_cnt] & INPUT_UP)     temp &= ~0x10;
+    if(input.pad[joy_cnt] & INPUT_RUN)    temp &= ~0x08;
+    if(input.pad[joy_cnt] & INPUT_SELECT) temp &= ~0x04;
+    if(input.pad[joy_cnt] & INPUT_B2)     temp &= ~0x02;
+    if(input.pad[joy_cnt] & INPUT_B1)     temp &= ~0x01;
+
+    if(joy_sel & 1) temp >>= 4;
+    temp &= 0x0F;
+
+    /* Set D6 for TurboGrafx-16, clear for PC-Engine */
+    if(input.system & SYSTEM_TGX) temp |= 0x40;
+
+    return (temp);
+}
+
+
+
+
+
+static const unsigned long crc_table[256] = {
+  0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+  0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+  0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+  0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+  0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+  0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+  0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+  0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+  0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+  0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+  0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+  0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+  0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+  0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+  0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+  0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+  0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+  0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+  0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+  0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+  0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+  0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+  0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+  0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+  0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+  0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+  0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+  0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+  0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+  0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+  0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+  0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+  0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+  0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+  0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+  0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+  0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+  0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+  0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+  0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+  0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+  0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+  0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+  0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+  0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+  0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+  0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+  0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+  0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+  0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+  0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+  0x2d02ef8dL
+};
+
+
+
+#define DO1(pt) crc = crc_table[((int)crc ^ (read_rom(pt++))) & 0xff] ^ (crc >> 8);
+#define DO2(pt)  DO1(pt); DO1(pt);
+#define DO4(pt)  DO2(pt); DO2(pt);
+#define DO8(pt)  DO4(pt); DO4(pt);
+
+#include "pcecrc.h"
+
+
+
+
+/* split : 1= Split image (only needed for 512k versions of 384k images)
+   flip  : 1= Bit-flip image (only for some TurboGrafx-16 images) */
+#include "bitflip.h"
+
+int load_rom(char *file, int split, int flip)
+{
+  uint32 crc;
+  int size, n;
+  int pos = 0x100000;
+  //char * filename="Galaga88.pce";
+  //char * filename="BONKIII.pce";
+  //char * filename="NEWZEAL.pce";
+  char * filename=file;
+
+  size = emu_FileSize(filename);
+
+#ifdef HAS_PSRAM
+
+  uint8 * buf = obj_pattern_cache;
+  
+/*
+  size = emu_LoadFile(filename,buf,size);
+  emu_printf("file loaded");  
+  
+  for (int i=0; i<size; i++) {
+    write_rom(pos++,buf[i]);
+  }
+  emu_printf("File written to psram");  
+*/
+  
+    
+  size = 0;
+  int f = emu_FileOpen(filename, "r+b");
+  if (f) {
+    while ( (n = emu_FileRead(buf,262144,f) ) ) {
+      size += n;
+      for (int i=0; i<n; i++) {
+        write_rom(pos++,buf[i]);
+      }
+      emu_printi(size);            
+      //emu_printi(n);          
+    }
+    emu_FileClose(f);
+  }
+
+#else
+  flash_start = (uint8 *)flash_load(filename);
+#endif  
+
+  /* Check for 512-byte header */
+  int offset = 0;
+  if((size / 512) & 1)
+  {
+    size -= 0x200;
+    offset += 0x200;
+  }
+
+  /* Generate CRC and print information */
+  int pt = 0x100000 + offset;
+  int len = size;
+  crc = 0 ^ 0xffffffffL;
+  while (len >= 8)
+  {
+    DO8(pt);
+    len -= 8;
+  }
+  if (len) do {
+    DO1(pt);
+  } while (--len);
+  crc =  crc ^ 0xffffffffL;
+  
+  emu_printh(crc);
+  
+  /* Look up game CRC in the CRC database, and set up flip and
+     split options accordingly */
+  for(n = 0; n < (sizeof(pcecrc_list) / sizeof(t_pcecrc)); n += 1)
+  {
+    if(crc == pcecrc_list[n].crc)
+    {
+      if(pcecrc_list[n].flag & FLAG_BITFLIP) flip = 1;
+      if(pcecrc_list[n].flag & FLAG_SPLIT) split = 1;
+    }
+  }
+
+  
+  //flip=1;
+  //split=1;
+
+  /* Bit-flip image */
+  if(flip)
+  {
+    uint8 temp;
+    int count;
+
+    pt = 0x100000 + offset;
+    for(count = 0; count < size; count += 1)
+    {
+        temp = read_rom(pt+count);
+        write_rom(pt+count,bitflip[temp]);
+    }
+  }
+  
+
+  /* Always split 384K images */
+  if(size == 0x60000)
+  {   
+        memcpy_rom(0x00000, 0x100000 + offset + 0x00000, 0x40000);
+        memcpy_rom(0x80000, 0x100000 + offset + 0x40000, 0x20000);
+  }
+  else /* Split 512K images if requested */
+    if(split && (size == 0x80000))
+    {
+        memcpy_rom(0x00000, 0x100000 + offset + 0x00000, 0x40000);
+        memcpy_rom(0x80000, 0x100000 + offset + 0x40000, 0x40000);
+    }
+    else
+    {
+        memcpy_rom(0, 0x100000 + offset, (size > 0x100000) ? 0x100000 : size);        
+    }
+  emu_printf("done");
+  return (1);
+}
+
diff --git a/MCUME_pico2/picopceold/pce.h b/MCUME_pico2/picopceold/pce.h
new file mode 100644
index 0000000..06cddf2
--- /dev/null
+++ b/MCUME_pico2/picopceold/pce.h
@@ -0,0 +1,25 @@
+#ifndef _PCE_H_
+#define _PCE_H_
+
+/* Global data */
+extern uint8 joy_sel;
+extern uint8 joy_clr;
+extern uint8 joy_cnt;
+
+/* Function prototypes */
+int pce_init(void);
+void pce_reset(void);
+void pce_shutdown(void);
+void cpu_writeport16(int port, int data);
+void cpu_writemem21(int address, int data);
+int pce_irq_callback(int irqline);
+void io_page_w(int address, int data);
+int io_page_r(int address);
+void input_w(uint8 data);
+uint8 input_r(void);
+void bank_reset(void);
+void bank_set(int bank, int value);
+
+int load_rom(char *filename, int split, int flip);
+
+#endif /* _PCE_H_ */
diff --git a/MCUME_pico2/picopceold/pcecrc.h b/MCUME_pico2/picopceold/pcecrc.h
new file mode 100644
index 0000000..1b6b559
--- /dev/null
+++ b/MCUME_pico2/picopceold/pcecrc.h
@@ -0,0 +1,441 @@
+/* File generated by pcecrc.exe */
+
+#define FLAG_BITFLIP        (0x01)
+#define FLAG_SPLIT          (0x02)
+#define FLAG_TGX            (0x04)
+#define FLAG_BADDUMP        (0x08)
+#define FLAG_SGX            (0x10)
+
+typedef struct {
+    unsigned long int crc;
+    unsigned char flag;
+    char *name;
+} t_pcecrc;
+
+
+const t_pcecrc pcecrc_list[] = {
+    {0x8597B9D8, 0x00, "15 in 1 Mega Collection (J) (alt).PCE"},
+    {0x6C30F0AC, 0x00, "15 in 1 Mega Collection (J).pce"},
+//    {0x8C4588E2, 0x10, "1941 Counter Attack (SGX) (J).pce"},
+    {0xD206E241, 0x10, "1941 Counter Attack (SGX) (J).pce"},
+    {0xFDE08D6D, 0x00, "1943 Kai (J) (alt 1).pce"},
+    {0x79362389, 0x00, "1943 Kai (J).pce"},
+    {0x73614660, 0x00, "21-Emon (J).pce"},
+    {0x637BA71D, 0x00, "5 in 1 Fami Collection (J).pce"},
+    {0xE86249A4, 0x08, "Adventure Island (J) (bad dump).pce"},
+    {0x8E71D4F3, 0x00, "Adventure Island (J).pce"},
+    {0x5C507421, 0x00, "Aero Blasters (J) (alt 1).pce"},
+    {0x25BE2B81, 0x00, "Aero Blasters (J).pce"},
+    {0xC02B1B59, 0x04, "Aero Blasters (U).pce"},
+    {0xCA72A828, 0x00, "After Burner II (J).pce"},
+    {0xE3284BA7, 0x04, "Air Zonk (U).pce"},
+    {0x4C2126B0, 0x10, "Aldynes (SGX) (J).pce"},
+    {0x05453628, 0x02, "Alice in Wonderdream (J) (512K).pce"},
+    {0x12C4E6FD, 0x00, "Alice in Wonderdream (J).pce"},
+    {0x60EDF4E1, 0x00, "Alien Crush (J).pce"},
+    {0xB64DE6FD, 0x04, "Alien Crush (U).pce"},
+    {0x7F421A1C, 0x0C, "Andre Panza Kick Boxing (U) (bad dump 2).pce"},
+    {0x3920105A, 0x04, "Andre Panza Kick Boxing (U).pce"},
+    {0xCACC06FB, 0x00, "Ankoko Densetsu (J).pce"},
+    {0x25DE250A, 0x02, "Aoi Blink (J) (512K).pce"},
+    {0x08A09B9A, 0x00, "Aoi Blink (J).pce"},
+    {0x2B54CBA2, 0x00, "Appare! Gateball (J).pce"},
+    {0x5E4FA713, 0x00, "Artist Tool (J).pce"},
+    {0xDD175EFD, 0x00, "Atomic Robokid Special (J).pce"},
+    {0xB866D282, 0x00, "Av Poker World Gambler (J).pce"},
+    {0x8ACFC8AA, 0x00, "Ballistix (J).pce"},
+    {0x9693D259, 0x04, "Ballistix (U).pce"},
+    {0xE13A6CE8, 0x0A, "Bari Bari Densetsu (J) (512K) (bad dump).pce"},
+    {0x72A2C22C, 0x02, "Bari Bari Densetsu (J) (512K).pce"},
+    {0xC267E25D, 0x00, "Bari Bari Densetsu (J).pce"},
+    {0x4A3DF3CA, 0x00, "Barunba (J).pce"},
+    {0x92C919EA, 0x02, "Batman (J) (512K).pce"},
+    {0x106BB7B2, 0x00, "Batman (J).pce"},
+    {0x3B13AF61, 0x10, "Battle Ace (SGX) (J).pce"},
+    {0x59E44F45, 0x00, "Battle Lode Runner (J).pce"},
+    {0xDA9A2DC9, 0x04, "Battle Royale (U).pce"},
+    {0xE439F299, 0x00, "Be Ball (J) (hacked).pce"},
+    {0x261F1013, 0x00, "Be Ball (J).pce"},
+    {0x968770F6, 0x00, "Be Ball - Taisang Version (J).pce"},
+    {0xC42B6D76, 0x02, "Benkei Gaiden (J) (512K).pce"},
+    {0xE1A73797, 0x00, "Benkei Gaiden (J).pce"},
+    {0x7AA9D4DC, 0x00, "Blazing Lazers (J).pce"},
+    {0x958BCD09, 0x00, "Blodia (J).pce"},
+    {0x47AFE6D7, 0x04, "Bloody Wolf (U).pce"},
+    {0xFFD92458, 0x00, "Body Conquest 2 (J).pce"},
+    {0xB300C5D0, 0x00, "Bomberman '93 (J).pce"},
+    {0x26020C77, 0x04, "Bomberman '93 (U).pce"},
+    {0x05362516, 0x00, "Bomberman '94 (J).pce"},
+    {0x87FD22AD, 0x00, "Bomberman (J) (Pirate).pce"},
+    {0x9ABB4D1F, 0x00, "Bomberman (J).pce"},
+    {0x8BF34FFA, 0x04, "Bomberman (U).pce"},
+    {0x9913A9DE, 0x04, "Bonk 3 - Bonk's Big Adventure (U).pce"},
+    {0xD5C782F2, 0x06, "Bonk's Adventure (U) (512K).pce"},
+    {0x64301FF1, 0x04, "Bonk's Revenge (U).pce"},
+    {0xCC7D3EEB, 0x00, "Bonze Adventure (J).pce"},
+    {0x8F4D9F94, 0x00, "Bouken Danshakan Don Sunheart Hen (J).pce"},
+    {0x98850F62, 0x00, "Bouncing Ball Demo (PD).PCE"},
+    {0x2E5AC9C0, 0x04, "Boxy Boy (U).pce"},
+    {0x2BBF3090, 0x04, "Bravoman (U) (hacked).pce"},
+    {0xC9D7426A, 0x00, "Break in (J).pce"},
+    {0x0D766139, 0x00, "Bubblegum Crash (J).pce"},
+    {0x3E4EAF98, 0x02, "Bullfight Ring no Haja (J) (512K).pce"},
+    {0x5C4D1991, 0x00, "Bullfight Ring no Haja (J).pce"},
+    {0x17A47D0D, 0x02, "Burning Angels (J) (512K).pce"},
+    {0xD233C05A, 0x00, "Burning Angels (J).pce"},
+    {0x2A121F03, 0x08, "CD-ROM System Ver. 1.00 (J) (bad dump).PCE"},
+    {0x3F9F95A4, 0x00, "CD-ROM System Ver. 1.00 (J).pce"},
+    {0x52520BC6, 0x00, "CD-ROM System Ver. 2.00 (J).pce"},
+    {0xD634D931, 0x04, "CD-ROM System Ver. 2.00 (U).pce"},
+    {0x833E05F9, 0x08, "CD-ROM System Ver. 2.10 (J) (bad dump).PCE"},
+    {0xC6ADDAA1, 0x00, "CD-ROM System Ver. 2.10 (J) (hacked to report V1).pce"},
+    {0x283B74E0, 0x00, "CD-ROM System Ver. 2.10 (J).pce"},
+    {0x7D48D2FC, 0x02, "Cadash (J) (512K).pce"},
+    {0x8DC0D85F, 0x00, "Cadash (J).pce"},
+    {0xF45AFBCA, 0x04, "Cadash (U).pce"},
+    {0x3C33E016, 0x00, "Cart (maybe demo) (PD).pce"},
+    {0x76164593, 0x02, "Champion Wrestler (J) (512K).pce"},
+    {0x9EDC0AEA, 0x00, "Champion Wrestler (J).pce"},
+    {0x2CEE30EE, 0x04, "Champions Forever Boxing (U).pce"},
+    {0x033E8C4A, 0x02, "Chase HQ (J) (512K).pce"},
+    {0x6F4FD790, 0x00, "Chase HQ (J).pce"},
+    {0xE84890A5, 0x04, "Chase HQ (U).pce"},
+    {0x88796264, 0x04, "Chew-man-fu (U).pce"},
+    {0x951ED380, 0x00, "Chibi Marukochan Quiz De Pihyara (J).pce"},
+    {0xCAB21B2E, 0x00, "Chikudenya Toubee (J).pce"},
+    {0xDC268242, 0x00, "China Warrior (J) (trained).pce"},
+    {0xB552C906, 0x00, "China Warrior (J).pce"},
+    {0x767245CD, 0x04, "China Warrior (U).pce"},
+    {0x0DF57C90, 0x00, "Chouzetsu Rinjin (BravoMan) (J).PCE"},
+    {0xC3212C24, 0x00, "Circus Lido (J).pce"},
+    {0xDF804DC7, 0x02, "City Hunter (J) (512K).pce"},
+    {0xF91B055F, 0x00, "City Hunter (J).pce"},
+    {0x44F60137, 0x00, "College Pro Baseball '89 (J).pce"},
+    {0x1772B229, 0x00, "College Pro Baseball '90 (J).pce"},
+    {0x99F7A572, 0x00, "Columns (J).pce"},
+    {0xB4D29E3B, 0x00, "Coryoon Child of Dragon (J).pce"},
+    {0x44AF9BEA, 0x04, "Cratermaze (U).pce"},
+    {0x2DF97BD0, 0x00, "Cross Wiber - Cyber Combat Police (J).pce"},
+    {0xA0C97557, 0x02, "Cyber Core (J) (512K).pce"},
+    {0xF82CED24, 0x00, "Cyber Core (J) (alt 2).pce"},
+    {0xA98D276A, 0x00, "Cyber Core (J).pce"},
+    {0x390710EC, 0x04, "Cyber Core (U).pce"},
+    {0xDCD3E602, 0x02, "Cyber Cross (J) (512K).pce"},
+    {0xD0C250CA, 0x00, "Cyber Cross (J).pce"},
+    {0xB5326B16, 0x00, "Cyber Dodge (J).pce"},
+    {0xA594FAC0, 0x00, "Cyber Knight (J).pce"},
+    {0xB486A8ED, 0x10, "Dai Makai Mura (SGX) (Ghouls and Ghosts) (J).pce"},
+    {0xA326334A, 0x00, "Daichikun Crisis Do Natural (J).pce"},
+    {0xB0BA689F, 0x00, "Darius Alpha (J).pce"},
+    {0x1E1D0319, 0x10, "Darius Plus (SGX) (J) (1024K).pce"},
+    {0xBEBFE042, 0x10, "Darius Plus (SGX) (J).pce"},
+    {0xE1A88CC3, 0x0C, "Darkwing Duck (U) (bad dump 1).pce"},
+    {0x4A135429, 0x04, "Darkwing Duck (U).pce"},
+    {0xEECFA5FD, 0x04, "Davis Cup Tennis (U).pce"},
+    {0x56739BC7, 0x00, "Dead Moon (J).pce"},
+    {0x85CC9B60, 0x04, "Dead Moon (U).pce"},
+    {0x053A0F83, 0x00, "Deep Blue (J).pce"},
+    {0xC2287894, 0x04, "Deep Blue (U).pce"},
+    {0x5CF59D80, 0x00, "Detana!! Twinbee (J).pce"},
+    {0x166A0E44, 0x02, "Devil Crash (J) (512K).pce"},
+    {0x2762792B, 0x06, "Devil's Crush (U) (512K).pce"},
+    {0x1B5B1CB1, 0x00, "Die Hard (J).pce"},
+    {0x17BA3032, 0x00, "Digital Champ (J).pce"},
+    {0x633A3D48, 0x02, "Don Doko Don (J) (512K).pce"},
+    {0xF42AA73E, 0x00, "Don Doko Don (J).pce"},
+    {0xDC760A07, 0x00, "Doraemon Meikyu Daisakusen (J).pce"},
+    {0x013A747F, 0x00, "Doraemon Nobita no Dorabian Night (J).pce"},
+    {0x86087B39, 0x00, "Double Dungeons (J).pce"},
+    {0x9E86FFB0, 0x04, "Double Dungeons (U).pce"},
+    {0x85101C20, 0x00, "Download (J).pce"},
+    {0x442405D5, 0x00, "Dragon Egg! (J).pce"},
+    {0xEEB6DD43, 0x00, "Dragon Fighter (J).pce"},
+    {0x3219849C, 0x00, "Dragon Saber (J).pce"},
+    {0x01A76935, 0x00, "Dragon Spirit (J).pce"},
+    {0xDCF3675C, 0x04, "Dragon Spirit (U).pce"},
+    {0x0BE0E0A8, 0x04, "Dragon's Curse (U).pce"},
+    {0x67EC5EC4, 0x00, "Drop Rock Hora Hora (J).pce"},
+    {0x2A3E08E2, 0x04, "Drop off (U).pce"},
+    {0xF79657DD, 0x02, "Dungeon Explorer (J) (512K).pce"},
+    {0x1B1A80A2, 0x00, "Dungeon Explorer (J).PCE"},
+    {0x1E2CBCF8, 0x06, "Dungeon Explorer (U) (512K).pce"},
+    {0xB18D102D, 0x00, "Eternal City Toshi Tenso Keikaku (J).pce"},
+    {0xD50FF730, 0x00, "F-1 Dream (J).pce"},
+    {0x020DC2DF, 0x02, "F-1 Pilot (J) (512K).pce"},
+    {0x09048174, 0x00, "F-1 Pilot (J).pce"},
+    {0xD7CFD70F, 0x00, "F1 Circus '91 - World Championship (J).pce"},
+    {0xB268F2A2, 0x00, "F1 Circus '92 - The Speed of Sound (J).pce"},
+    {0xE14DEE08, 0x00, "F1 Circus (J).pce"},
+    {0x13BF0409, 0x00, "F1 Triple Battle (J).pce"},
+    {0x7424452E, 0x04, "Falcon (U).pce"},
+    {0x72CB0F9D, 0x00, "Fantasy Zone (J).pce"},
+    {0xDCA24A76, 0x04, "Fantasy Zone (U).pce"},
+    {0x1828D2E5, 0x00, "Fighting Run (J).pce"},
+    {0xC90971BA, 0x00, "Final Blaster (J).pce"},
+    {0xC8C084E3, 0x00, "Final Lap Twin (J).pce"},
+    {0x854C37B3, 0x05, "Final Lap Twin (U) (bit-flipped).pce"},
+    {0x560D2305, 0x00, "Final Match Tennis (J).pce"},
+    {0xAF2DD2AF, 0x00, "Final Soldier (J).PCE"},
+    {0x02A578C5, 0x00, "Final Soldier Special Version (J).pce"},
+    {0xE88987BB, 0x00, "Fire Pro Wrestling 2nd Bout (J).pce"},
+    {0x534E8808, 0x00, "Fire Pro Wrestling 3 - Legend Bout (J).pce"},
+    {0x90ED6575, 0x00, "Fire Pro Wrestling Combination Tag (J).pce"},
+    {0x20EF87FD, 0x00, "Formation Armed F (J).pce"},
+    {0x85A1E7B6, 0x00, "Formation Soccer Human Cup '90 (J).pce"},
+    {0x7146027C, 0x00, "Formation Soccer on J.league (J).pce"},
+    {0x95F90DEC, 0x00, "Gai Flame (J).pce"},
+    {0x6FD6827C, 0x00, "Gaia no Monsho (J).pce"},
+    {0x1A8393C6, 0x00, "Galaga '88 (J).pce"},
+    {0x6273A9D4, 0x04, "Galaga '90 (U).pce"},
+    {0x22365252, 0x00, "Game of Life (PD).PCE"},
+    {0x51A12D90, 0x04, "Games Express CD Card 1993 (U).pce"},
+    {0x27A4D11A, 0x00, "Ganbare! Golf Boys (J).pce"},
+    {0xAD450DFC, 0x00, "Genji Tsushin Agedama (Hero Agent) (J).pce"},
+    {0xB926C682, 0x00, "Genpei Touma Den (J).pce"},
+    {0x8793758C, 0x00, "Genpei Touma Den 2 (J).PCE"},
+    {0x2DB4C1FD, 0x04, "Ghost Manor (U).pce"},
+    {0x19FF94E5, 0x02, "Gokuraku Chuka Taisen (J) (512K).pce"},
+    {0x4BD38F17, 0x00, "Gomola Speed (J).pce"},
+    {0x0517DA65, 0x00, "Gradius (J).pce"},
+    {0x1F041166, 0x10, "Grandzort (SGX) (J).pce"},
+    {0xF370B58E, 0x04, "Gunboat (U).pce"},
+    {0x113DD5F0, 0x02, "Gunhed (J) (512K).pce"},
+    {0xA17D4D7E, 0x00, "Gunhed (J).pce"},
+    {0x57F183AE, 0x00, "Gunhed Hudson Gunhed Taikai (J).pce"},
+    {0xBA4D0DD4, 0x00, "Hana Tahka Daka (J).pce"},
+    {0xBF3E2CC7, 0x00, "Hani in the Sky (J).pce"},
+    {0x9897FA86, 0x00, "Hani on the Road (J).pce"},
+    {0xCC799D92, 0x00, "Hatris (J) (256K).pce"},
+    {0x44E7DF53, 0x00, "Hatris (J).pce"},
+    {0xEB923DE5, 0x00, "Heavy Unit (J).pce"},
+    {0xC7327632, 0x00, "Hisou Kihei Serd Gai Shadow (J).pce"},
+    {0x7ACB60C8, 0x00, "Hit the Ice (J).pce"},
+    {0xB01EE703, 0x00, "Hono no Tataka Tamako Dodge Danpei (J).pce"},
+    {0xF84AE70B, 0x08, "Hyperdyne Sidearms (J) (bad dump).pce"},
+    {0xE5E7B8B7, 0x00, "Hyperdyne Sidearms (J).pce"},
+    {0x4F2BD39F, 0x00, "Hyperdyne Sidearms - Taisang Version (J).pce"},
+    {0x9EC6FC6C, 0x00, "Idol Hanafuda Fan Club (J).pce"},
+    {0xA80C565F, 0x00, "Image Fight (J).pce"},
+    {0x92521F34, 0x04, "Impossamole (U).pce"},
+    {0x0AD97B04, 0x00, "J. League Greatest Eleven Soccer (J).pce"},
+    {0x348022F7, 0x04, "JJ & Jeff (U).pce"},
+    {0xEA751E82, 0x00, "Jack Nicklaus' Greatest 18 Holes of Championship Golf (J).pce"},
+    {0x57A436A2, 0x04, "Jack Nicklaus' Turbo Golf (U).pce"},
+    {0xC6FA6373, 0x00, "Jackie Chan's Action Kung Fu (J).pce"},
+    {0xED3A71F8, 0x04, "Jackie Chan's Action Kung Fu (U).pce"},
+    {0x9BB8D362, 0x00, "Jamanoid (version unknown) (PD).PCE"},
+    {0xC150637A, 0x00, "Jimmu Densho Yaksa (J).pce"},
+    {0x6A628982, 0x00, "Jyuohki (Altered Beast) (J).pce"},
+    {0xC8C7D63E, 0x00, "Jyuohki (J).pce"},
+    {0xC0AF0947, 0x00, "Kaizou Ningen Shubibiman (J) (pirate).pce"},
+    {0x109BA474, 0x00, "Kaizou Ningen Shubibiman 2 (J).pce"},
+    {0x6069C5E7, 0x00, "Kato Chan & Ken Chan (J).pce"},
+    {0x4F2844B0, 0x00, "Katutobi Takuhai Kun (J).pce"},
+    {0xB54DEBD1, 0x04, "Keith Courage in Alpha Zones (U) (hacked 1).pce"},
+    {0x73593F61, 0x02, "KickBall (J) (512K).pce"},
+    {0x8E25DC77, 0x02, "Kiki Kai Kai (J) (512K).pce"},
+    {0xC0CB5ADD, 0x00, "Kiki Kai Kai (J).pce"},
+    {0xBF52788E, 0x00, "King of Casino (J).pce"},
+    {0x589D33EB, 0x04, "King of Casino (U).pce"},
+    {0xC74FFBC9, 0x00, "Klax (J).pce"},
+    {0xDB872A64, 0x04, "Klax (U).pce"},
+    {0xC614116C, 0x00, "Knight Rider Special (J) (alt).pce"},
+    {0x61B80005, 0x00, "Knight Rider Special (J).pce"},
+    {0xA586D190, 0x08, "Kyuukyoku Tiger (Ultimate Tiger) (J) (bad dump 3).pce"},
+    {0x09509315, 0x00, "Kyuukyoku Tiger (Ultimate Tiger) (J).pce"},
+    {0xC6F764EC, 0x00, "Lady Sword (J).pce"},
+    {0xC28B0D8A, 0x00, "Legend of Hero Tonma (J).pce"},
+    {0x0258ACCB, 0x04, "Legend of Hero Tonma (U).pce"},
+    {0x088D896D, 0x04, "Legendary Axe II, The (U).PCE"},
+    {0x07A226FB, 0x04, "Legendary Axe, The (U).pce"},
+    {0xB2EF558D, 0x00, "Liquid Kids (J).pce"},
+    {0xE6EE1468, 0x00, "Lode Runner Ushina Wareta Maikyuu (J).pce"},
+    {0xA15A1F37, 0x00, "Maerchen Maze (J).PCE"},
+    {0x0C8E99AB, 0x00, "Magic PCE Demo (PD).PCE"},
+    {0xE8D01ED8, 0x00, "Magic Team Demo 2 (PD).PCE"},
+    {0xDD0EBF8C, 0x00, "Magical Chase (J).PCE"},
+    {0xF4148600, 0x00, "Mahjong Gakuen Mild (J).pce"},
+    {0xF5B90D55, 0x00, "Mahjong Gakuen Touma Shiro Tojo (J).pce"},
+    {0x2F8935AA, 0x00, "Majin Eiyu Wataru (J).pce"},
+    {0xBE62EEF5, 0x00, "Makai Hakkenden Shada (J).pce"},
+    {0xD4C5AF46, 0x00, "Makyo Densetsu (J).pce"},
+    {0xE87190F1, 0x00, "Mesopotamia (J).PCE"},
+    {0x25A02BEE, 0x00, "Metal Stoker (J).PCE"},
+    {0x93F316F7, 0x04, "Military Madness (U).pce"},
+    {0x7B96317C, 0x02, "Momo Tarou Densetsu Turbo (J) (512K).pce"},
+    {0xF2E46D25, 0x00, "Monster Pro Wrestling (J).pce"},
+    {0x745408AE, 0x00, "Moto Roader (J) (alt).pce"},
+    {0x364508DA, 0x02, "Moto Roader II (J) (512K).pce"},
+    {0x0B7F6E5F, 0x00, "Moto Roader II (J).pce"},
+    {0x2CB92290, 0x00, "Mr. Heli no Dai Bouken (J).pce"},
+    {0xB01F70C2, 0x00, "Narazumo no Sentou Butai (Bloody Wolf) (J).pce"},
+    {0x60ECAE22, 0x00, "Naxat Open (J).pce"},
+    {0xFBA3A1A4, 0x00, "Naxat Stadium - Taisang Version (J).pce"},
+    {0x65FDB863, 0x00, "Nekketsu Koukou Dodgeball Bu Pc Bangai Hen (J).pce"},
+    {0x9C49EF11, 0x00, "Neutopia (J).pce"},
+    {0xA9A94E1B, 0x04, "Neutopia (U).pce"},
+    {0x2B94AEDC, 0x00, "Neutopia II (J).pce"},
+    {0xAE26F30F, 0x04, "Neutopia II (U) (1024K).pce"},
+    {0xC4ED4307, 0x04, "Neutopia II (U).pce"},
+    {0x8E4D75A8, 0x00, "New Zealand Story, The (J).pce"},
+   
+    {0xC159761B, 0x04, "Night Creatures (U) (alt).PCE"},
+    {0xA9FAB7D2, 0x04, "Night Creatures (U).pce"},
+    {0x67573BAC, 0x00, "Ninja Gaiden (J).pce"},
+    {0xAE9FE1AA, 0x04, "Ninja Spirit (U) (hacked).pce"},
+    {0x96E0CD9D, 0x00, "Ninja Warriors, The (J).pce"},
+    {0xFF898F87, 0x00, "Operation Wolf (J).pce"},
+    {0xFAE0FC60, 0x04, "Order of the Griffon (U).pce"},
+    {0x8C565CB6, 0x00, "Ordyne (J).pce"},
+    {0xE203F223, 0x00, "OutRun (J).pce"},
+  
+    {0xB74EC562, 0x00, "Override (J).PCE"},
+    {0x14FAD3BA, 0x00, "Pac-Land (J).pce"},
+    {0x73E994A0, 0x00, "Paranoia (J) (alt 1).pce"},
+    {0x9893E0E6, 0x00, "Paranoia (J) (alt 2).pce"},
+    {0x43EFC974, 0x00, "Paranoia (J) (trained).pce"},
+    {0x51E86451, 0x00, "Parasol Stars (J).pce"},
+    {0xE6458212, 0x04, "Parasol Stars (U).PCE"},
+    {0x647718F9, 0x00, "Parodius (J).pce"},
+    {0x740491C2, 0x00, "Pc Denjin - Punkic Cyborgs (J).pce"},
+    {0xB630AB25, 0x02, "Pc Genjin (J) (512K) (alt).pce"},
+    {0x2CB5CD55, 0x00, "Pc Genjin (J).pce"},
+    {0x3028F7CA, 0x00, "Pc Genjin 2 (J).pce"},
+    {0xA170B60E, 0x00, "Pc Genjin 3 (J).PCE"},
+    {0xE8702D51, 0x00, "Photograph Boy (J).pce"},
+    {0x4938B8BB, 0x00, "Populous (J) (1024K) (overdumped 1).PCE"},
+//    {0x25E0F6E9, 0x00, "Power Drift (J).pce"},
+    {0x5E17AC2A, 0x00, "Power Drift (J).pce"},
+    
+    {0x3E647D8B, 0x00, "Power Eleven (J).pce"},
+    {0xBE8B6E3B, 0x00, "Power Gate (J).pce"},
+    {0x8F02FD20, 0x02, "Power Golf (J) (512K).pce"},
+    {0xEA324F07, 0x00, "Power Golf (J).pce"},
+    {0x69180984, 0x04, "Power League Baseball (U).PCE"},
+    {0xBB654D1C, 0x00, "Power League V (J).pce"},
+    {0x29EEC024, 0x00, "Power Sports (J).PCE"},
+    {0x8DEF5AA1, 0x00, "Power Tennis (J).pce"},
+    {0x66B167A9, 0x00, "Pro Yakyuu World Stadium '91 (J) (alt).pce"},
+    {0x34E089A9, 0x00, "Pro Yakyuu World Stadium (J).pce"},
+    {0x03883EE8, 0x00, "Psycho Chaser (J).pce"},
+    {0x8672717C, 0x08, "Puzzle Boy (J) (bad dump).pce"},
+    {0xFAA6E187, 0x00, "Puzzle Boy (J).pce"},
+    {0x965C95B3, 0x00, "Puzznic (J).pce"},
+    {0xF2E6856D, 0x00, "Quiz Toukou Shashin (J).pce"},
+    {0xCEC3D28A, 0x00, "R-Type (J) (alt).pce"},
+    {0x149D0511, 0x00, "R-Type - Taisang Version (J).PCE"},
+    {0x9E2CF932, 0x04, "R-Type Complete (U).pce"},
+    {0xF207ECAE, 0x00, "R-Type II (J).pce"},
+    {0x6EAB778C, 0x00, "R-Type II - Taisang Version (J).pce"},
+    {0xD8373DE6, 0x00, "Rabio Lepus Special (J).pce"},
+    {0x3E79734C, 0x00, "Racing Spirits (J).pce"},
+    {0xB99A85B6, 0x00, "Raiden (J) (1024K).PCE"},
+    {0x850829F2, 0x00, "Raiden (J).pce"},
+    {0xC7847DF7, 0x04, "Raiden (U).pce"},
+    {0x85B85FF9, 0x02, "Rastan Saga II (J) (512K).PCE"},
+    {0x00C38E69, 0x00, "Rastan Saga II (J).pce"},
+    {0x462256FB, 0x02, "Rock on (J) (512K).pce"},
+    {0x2FD65312, 0x00, "Rock on (J).pce"},
+    {0x91E6896F, 0x00, "Ryukyu (J).pce"},
+    {0xFAECCE20, 0x00, "Salamander (J).PCE"},
+    {0x07BC34DC, 0x04, "Samurai-Ghost (U).pce"},
+    {0x6923D736, 0x00, "Shanghai (J).pce"},
+    {0xBC655CF3, 0x00, "Shinobi (J).pce"},
+//    {0x471903C6, 0x02, "Shinobi (J).pce"},
+    
+    {0x57615647, 0x04, "Shockman (U).pce"},
+    {0x23EC8970, 0x00, "Shogi Shodan Icchokusen (J).pce"},
+    {0x457F2BC4, 0x00, "Shogi Shoshinsha Muyo (J).pce"},
+    {0x616EA179, 0x00, "Silent Debuggers, The (J).pce"},
+    {0x4CAA6BE9, 0x05, "Silent Debuggers, The (U) (bit flipped).PCE"},
+    {0xFA7E5D66, 0x04, "Silent Debuggers, The (U).pce"},
+    {0x85AA49D0, 0x06, "Sinistron (U) (512K).PCE"},
+    {0x05C20DE5, 0x00, "SlideShow (PD).PCE"},
+    {0x8420B12B, 0x00, "Soldier Blade (J).PCE"},
+    {0xF0227837, 0x04, "Somer Assault (U).pce"},
+    {0xD7921DF2, 0x00, "Son Son II (J).pce"},
+    {0x23D22D63, 0x04, "Sonic Spike (U).pce"},
+    {0xFB37DDC4, 0x00, "Soukoban World (Boxy Boy) (J).pce"},
+    {0x64580427, 0x00, "Space Harrier (J).pce"},
+    {0x99496DB3, 0x00, "Space Invaders Fukkatsu no Hi (J).pce"},
+    {0x1C6FF459, 0x00, "Spin Pair (J).pce"},
+    {0x6B319457, 0x00, "Splatterhouse (J).PCE"},
+    {0x727F4656, 0x00, "Stratego (J).pce"},
+    {0xD15CB6BB, 0x00, "Street Fighter II Champion Edition (J).pce"},
+    {0xD6FC51CE, 0x00, "Strip Fighter II (J).pce"},
+    {0xDD35451D, 0x00, "Super CD-ROM2 System Ver. 3.00 (J) (384K) (overdumped 1).pce"},
+    {0xE5D91815, 0x00, "Super CD-ROM2 System Ver. 3.00 (J) (384K) (overdumped 3).pce"},
+    {0x9759A20D, 0x01, "Super CD-ROM2 System Ver. 3.00 (J) (bit-flipped for USA).pce"},
+    {0x56488B36, 0x00, "Super Metal Crusher (J).pce"},
+    {0x5D0E3105, 0x00, "Super Star Soldier (J).pce"},
+    {0xAB3C5804, 0x04, "Super Star Soldier (U).PCE"},
+    {0x10B60601, 0x00, "TV Sports Basketball (J).pce"},
+    {0x9A41C638, 0x04, "TV Sports Basketball (U).pce"},
+    {0xDA059C9B, 0x02, "TV Sports Football (J) (512K).pce"},
+    {0x968D908A, 0x00, "TV Sports Football (J).pce"},
+    {0x14DAF737, 0x04, "TV Sports Football (U).pce"},
+    {0x4DF54B81, 0x04, "TV Sports Hockey (U) (alt).pce"},
+    {0x04BF5EAF, 0x04, "TV Sports Hockey (U).pce"},
+    {0xE7529890, 0x00, "TV Sports Ice Hockey (J).pce"},
+    {0xE415EA19, 0x00, "Takahashi Meijin no Shin Boukenjima (New Adventure Island) (J).pce"},
+    {0xC356216B, 0x04, "Takin it to the Hoop (U).pce"},
+    {0x24C82EBE, 0x0C, "Talespin (U) (bad dump 2).pce"},
+    {0xEDA32D95, 0x04, "Talespin (U).pce"},
+    {0xA6088275, 0x00, "Tatsujin (J) (alt).PCE"},
+    {0x4052FFAB, 0x08, "Tatsujin (J) (bad dump).pce"},
+    {0x231B1535, 0x00, "Tatsujin (J).pce"},
+    {0x320F5018, 0x00, "Tennokoe Memory Bank (J) (384k).pce"},
+    {0xCA12AFBA, 0x02, "Tenseiryu Saint Dragon (J) (512K).PCE"},
+    {0x2E278CCB, 0x00, "Tenseiryu Saint Dragon (J).pce"},
+    {0x1B2D0077, 0x00, "Terra Cresta II (J).pce"},
+    {0x5C3D477A, 0x00, "Text Sample 1 (PD).PCE"},
+    {0x7964A966, 0x00, "Text Sample 2 (PD).PCE"},
+    {0xDDC3E809, 0x00, "Thunder Blade (J).pce"},
+    {0x72D6860B, 0x04, "Time Cruise (U).pce"},
+    {0xCFEC1D6A, 0x00, "Time Cruise 2 (J).pce"},
+    {0x05A4B72E, 0x04, "Timeball (U).pce"},
+    {0xD20F382F, 0x00, "Titan (J).pce"},
+    {0x53B7784B, 0x00, "Toilet Kids (J).PCE"},
+    {0xBF797067, 0x02, "Tora E no Michi (J) (512K).pce"},
+    {0x82AE3B16, 0x00, "Tora E no Michi (J).pce"},
+    {0x72E00BC4, 0x00, "Tower of Druaga, The (J).pce"},
+    {0x97C5EE9A, 0x00, "Toy Shop Boys (J).pce"},
+    {0x3AEA2F8F, 0x00, "Tricky (J).pce"},
+    {0x3D30D358, 0x04, "Tricky Kick (U) (alt).pce"},
+    {0x3F982D0F, 0x04, "Turrican (U).pce"},
+    {0xA3303978, 0x00, "Valkyrie no Densetsu (J).pce"},
+    {0x04188C5C, 0x00, "Veigues Tactical Gladiator (J).pce"},
+    {0xAD6E0376, 0x04, "Veigues Tactical Gladiator (U).PCE"},
+    {0x03E28CFF, 0x00, "Victory Run (J).pce"},
+    {0x5157A395, 0x04, "Victory Run (U).pce"},
+    {0xE4124FE0, 0x04, "Vigilante (U) (alt).pce"},
+    {0xC8A412E1, 0x04, "Vigilante (U).pce"},
+    {0x34FD4EF2, 0x02, "Violent Soldier (J) (512K).pce"},
+    {0x1BC36B36, 0x00, "Violent Soldier (J).pce"},
+    {0xAD226F30, 0x00, "Volfied (J).pce"},
+    {0xBE990010, 0x00, "W-ring the Double Rings (J).pce"},
+    {0x661E475B, 0x00, "Walker Demo (PD).PCE"},
+    {0x0112D0C7, 0x00, "Wallaby!! (J).pce"},
+    {0x9B5EBC58, 0x00, "Winning Shot (J).pce"},
+    {0x59D07314, 0x00, "Wonder Momo (J).PCE"},
+    {0x38E2917D, 0x00, "Wonderboy in Monsterland (J) (alt 1).pce"},
+    {0x02DB6FE5, 0x00, "Wonderboy in Monsterland (J) (partial English Translation).pce"},
+    {0x2841FD1E, 0x00, "Wonderboy in Monsterland (J).pce"},
+    {0xBE850530, 0x00, "World Beach Volley (J).pce"},
+    {0xB3EEEA2E, 0x00, "World Circuit (J).pce"},
+    {0x951AA310, 0x04, "World Class Baseball (U) (hacked).pce"},
+    {0x11A36745, 0x00, "World Court Tennis (J).pce"},
+    {0xC4EB68A5, 0x05, "World Court Tennis (U) (bit flipped).pce"},
+    {0x70D90E20, 0x04, "World Court Tennis (U).pce"},
+    {0xA9AB2954, 0x00, "World Jockey (J).pce"},
+    {0x4161F202, 0x04, "World Sports Competition (U).pce"},
+    {0xF8F85EEC, 0x00, "Xevious (J).pce"},
+    {0x931B601F, 0x05, "Yo' Bro (U) (bit flipped).pce"},
+    {0xB24E6504, 0x04, "Yo' Bro (U).pce"},
+    {0xF131B706, 0x00, "Youkai Douchuuki (J).pce"},
+    {0xC0905CA9, 0x00, "Yuu Yuu Jinsei (J).pce"},
+    {0xEE156721, 0x00, "Zero 4 Champ (J) (alt 1).pce"},
+    {0x2E6D9712, 0x00, "Zero 4 Champ (J) (alt 2).pce"},
+    {0x67AAB7A1, 0x00, "Zipang (J).pce"},
+};
+
diff --git a/MCUME_pico2/picopceold/pcetypes.h b/MCUME_pico2/picopceold/pcetypes.h
new file mode 100644
index 0000000..558a1f5
--- /dev/null
+++ b/MCUME_pico2/picopceold/pcetypes.h
@@ -0,0 +1,17 @@
+
+#ifndef _PCE_TYPES_H_
+#define _PCE_TYPES_H_
+
+
+typedef unsigned char uint8;
+typedef unsigned short int uint16;
+typedef unsigned long int uint32;
+
+typedef signed char int8;
+typedef signed short int int16;
+typedef signed long int int32;
+
+#define NULL 0
+
+#endif /* _TYPES_H_ */
+
diff --git a/MCUME_pico2/picopceold/picopce.cpp b/MCUME_pico2/picopceold/picopce.cpp
new file mode 100644
index 0000000..7ef826f
--- /dev/null
+++ b/MCUME_pico2/picopceold/picopce.cpp
@@ -0,0 +1,188 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+#include "emu.h"
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(125000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+     emu_init();
+ 
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picopceold/psg.c b/MCUME_pico2/picopceold/psg.c
new file mode 100644
index 0000000..c47f7ba
--- /dev/null
+++ b/MCUME_pico2/picopceold/psg.c
@@ -0,0 +1,150 @@
+#include "shared.h"
+
+t_psg psg;
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown routines                                           */
+/*--------------------------------------------------------------------------*/
+
+int psg_init(void)
+{
+    memset(&psg, 0, sizeof(psg));
+    return (0);
+}
+
+void psg_reset(void)
+{
+    memset(&psg, 0, sizeof(psg));
+}
+
+void psg_shutdown(void)
+{
+}
+
+/*--------------------------------------------------------------------------*/
+/* PSG emulation                                                            */
+/*--------------------------------------------------------------------------*/
+
+void psg_w(uint16 address, uint8 data)
+{
+    switch(address)
+    {
+        case 0x0800: /* Channel select */
+            psg.select = (data & 7);
+            break;
+
+        case 0x0801: /* Global sound balance */
+            psg.globalbalance = data;
+            break;
+
+        case 0x0802: /* Channel frequency (LSB) */
+            PSGCH.frequency = (PSGCH.frequency & 0x0F00) | (data);
+            break;
+
+        case 0x0803: /* Channel frequency (MSB) */
+            PSGCH.frequency = (PSGCH.frequency & 0x00FF) | ((data & 0x0F) << 8);
+            break;
+
+        case 0x0804: /* Channel enable, DDA, volume */
+            PSGCH.control = data;
+            if((data & 0xC0) == 0x40) PSGCH.waveform_index = 0;
+            break;
+
+        case 0x0805: /* Channel balance */
+            PSGCH.balance = data;
+            break;
+
+        case 0x0806: /* Channel waveform data */
+            PSGCH.waveform[PSGCH.waveform_index] = data;
+            PSGCH.waveform_index = ((PSGCH.waveform_index + 1) & 0x1F);
+            break;
+
+        case 0x0807: /* Noise enable and frequency */
+            psg.noisectrl = data;
+            break;
+
+        case 0x0808: /* LFO frequency */
+            psg.lfofreq = data;
+            break;
+
+        case 0x0809: /* LFO trigger and control */
+            psg.lfoctrl = data;
+            break;
+    }
+}
+
+void psg_update(int16 *bufl, int16 *bufr, int length)
+{
+    /* Fill as many samples as needed */
+    while(length > 0)
+    {
+        int ch;                    /* Channel index */
+        int sample[2] = {0, 0};    /* Left and right samples */
+        int start;                 /* Skip channels 0, 1 if LFO is enabled */ 
+        int stop;                  /* Skip channels 4, 5 if noise is enabled */
+
+        start = ((psg.lfoctrl & 3) == 0) ? 0 : 2;
+        stop = (psg.noisectrl & 0x80) ? 4 : 6;
+
+        for(ch = start; ch < stop; ch += 1)
+        {
+            /* If channel is ON and DDA is OFF, play waveform data */
+            if((psg.channel[ch].control & 0xC0) == 0x80)
+            {
+                /* Global sound balance (left and right, all channels) */
+                int lbal = (psg.globalbalance >> 4) & 0x0F;
+                int rbal = (psg.globalbalance >> 0) & 0x0F;
+
+                /* Balance (left and right, this channel) */
+                int lchb = (psg.channel[ch].balance >> 4) & 0x0F;
+                int rchb = (psg.channel[ch].balance >> 0) & 0x0F;
+
+                /* Volume level (this channel) */
+                int chvl = (psg.channel[ch].control & 0x1F);
+    
+                /* Total volume levels for left and right
+                   (volume sounds too soft - not sure how to combine these) */
+                int lvol = (lbal + lchb + chvl);
+                int rvol = (rbal + rchb + chvl);
+
+                int base, step, offset, data;
+
+                /* This is the largest possible step value which is divided
+                   by the channel frequency used to increment the counter,
+                   which in turn is used to traverse the waveform buffer.
+                   3580000 (PSG clock) / 32 (length of waveform) = 111875 (base step value)
+                   That doesn't work right but multiplying it by three sounds better. */
+                base = (3580000 / 32) * 3;
+
+                /* Calculate the value to add to the counter for each sample,
+                   but don't divide by zero if the frequency is zero */
+                step = (psg.channel[ch].frequency) ? base / psg.channel[ch].frequency : 0;
+
+                /* Use upper 5 bits of 12-bit frequency as wave index */
+                offset = (psg.channel[ch].counter >> 12) & 0x1F;
+
+                /* Bump waveform index */
+                psg.channel[ch].counter += step;
+
+                /* Data is 5 bits */
+                data = (psg.channel[ch].waveform[offset] & 0x1F);
+
+                /* Add new sample to old one */
+                sample[0] = (sample[0] + (lvol * data));
+                sample[1] = (sample[1] + (rvol * data));
+            }
+        }
+
+        /* Make samples signed */
+        if(sample[0] & 0x8000) sample[0] ^= 0x8000;
+        if(sample[1] & 0x8000) sample[1] ^= 0x8000;
+
+        /* Store samples in buffer */
+        *bufl++ = sample[0]; //(sample[0]+sample[1])/2;
+        //*bufl++ = sample[1];
+        //*bufr++ = sample[1];
+
+        /* Do next sample pair */
+        --length;
+    }
+}
diff --git a/MCUME_pico2/picopceold/psg.h b/MCUME_pico2/picopceold/psg.h
new file mode 100644
index 0000000..247074b
--- /dev/null
+++ b/MCUME_pico2/picopceold/psg.h
@@ -0,0 +1,36 @@
+
+#ifndef _PSG_H_
+#define _PSG_H_
+
+/* Macro to access currently selected PSG channel */
+#define PSGCH   psg.channel[psg.select]
+
+/* PSG structure */
+typedef struct {
+    uint8 select;               /* Selected channel (0-5) */
+    uint8 globalbalance;        /* Global sound balance */
+    uint8 noisectrl;            /* Noise enable and frequency */
+    uint8 lfofreq;              /* LFO frequency */
+    uint8 lfoctrl;              /* LFO control */
+    struct {
+        int counter;            /* Waveform index counter */
+        uint16 frequency;       /* Channel frequency */
+        uint8 control;          /* Channel enable, DDA, volume */
+        uint8 balance;          /* Channel balance */
+        uint8 waveform[32];     /* Waveform data */
+        uint8 waveform_index;   /* Waveform data index */
+    } channel[8];
+}t_psg;
+
+/* Global variables */
+extern t_psg psg;
+
+/* Function prototypes */
+int psg_init(void);
+void psg_reset(void);
+void psg_shutdown(void);
+void psg_w(uint16 address, uint8 data);
+void psg_update(int16 *bufl, int16 *bufr, int length);
+
+#endif /* _PSG_H_ */
+
diff --git a/MCUME_pico2/picopceold/render.c b/MCUME_pico2/picopceold/render.c
new file mode 100644
index 0000000..cff1bd9
--- /dev/null
+++ b/MCUME_pico2/picopceold/render.c
@@ -0,0 +1,365 @@
+#include "shared.h"
+
+
+/* Bit 0 : BG enable, Bit 1 : OBJ enable */
+int plane_enable = -1;
+
+/* VCE color data to 16-bit pixel table */
+uint16 pixel[2][0x100];
+
+/* Precalculated 16-bit pixel values */
+uint16 pixel_lut[0x200];
+
+/* Pointer to 8 or 16-bit version of render_line() */
+void (*render_line)(int line) = NULL;
+
+/* List of precalculated sprite data */
+t_sprite sprite_list[0x40];
+
+/* Bitplane to packed pixel lookup table */
+//uint32 bp_lut[0x10000];
+#include "bp_lut.h"
+
+/* Used sprite data */
+uint8 used_sprite_list[0x40];
+uint8 used_sprite_index;
+
+
+extern void emu_DrawLine16(unsigned short *src, int width , int height, int line); 
+extern void emu_printf(char * text);
+
+
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown functions                                          */
+/*--------------------------------------------------------------------------*/
+
+int render_init(void)
+{
+    int i, j;
+
+    /* Make VCE data to raw pixel look-up table */
+    for(i = 0; i < 0x200; i += 1)
+    {
+        int r = (i >> 3) & 7;
+        int g = (i >> 6) & 7;
+        int b = (i >> 0) & 7;
+        pixel_lut[i] = (r << 13 | g << 8 | b << 2) & 0xE71C;
+    }
+
+    render_line = render_line_generic;
+    return (1);
+}
+
+
+void render_reset(void)
+{
+    render_line = render_line_generic;
+}
+
+
+void render_shutdown(void)
+{
+}
+
+
+int make_sprite_list(void)
+{
+    uint16 *sat = &objramw[0];
+    int xpos, ypos, name, attr;
+    int cgx, xflip, cgy, yflip;
+    int width, height;
+    int i;
+    uint32 flip;
+
+    used_sprite_index = 0;
+    memset(&used_sprite_list, 0, sizeof(used_sprite_list));
+
+    memset(&sprite_list, 0, sizeof(sprite_list));
+
+    for(i = 0; i < 0x40; i += 1)
+    {
+        ypos = sat[(i << 2) | (0)];
+        xpos = sat[(i << 2) | (1)];
+        name = sat[(i << 2) | (2)];
+        attr = sat[(i << 2) | (3)];
+
+        ypos &= 0x3FF;
+        xpos &= 0x3FF;
+
+        if(xpos && ypos)
+        {
+            ypos -= 64;
+            if(ypos >= 0x100) continue;
+            cgy = (attr >> 12) & 3;
+            cgy |= (cgy >> 1);
+            height = (cgy + 1) << 4;
+            if((ypos + height) < 0) continue;
+
+            xpos -= 32;
+            if(xpos >= 0x200) continue;
+            cgx = (attr >> 8) & 1;
+            width  = (cgx) ? 32 : 16;
+            if((xpos + width) < 0) continue;
+
+            xflip = (attr >> 11) & 1;
+            yflip = (attr >> 15) & 1;
+            flip = ((xflip << 9) /*| (yflip << 10)*/) & 0x600;
+
+            name = (name >> 1) & 0x1FF;
+            name &= ~((cgy << 1) | cgx);
+            name |= flip;
+            if(xflip && cgx) name ^= 1;
+
+            sprite_list[i].top = ypos;
+            sprite_list[i].bottom = ypos + height;
+            sprite_list[i].xpos = xpos;
+            sprite_list[i].name_left = name;
+            sprite_list[i].name_right = name ^ 1;
+            sprite_list[i].height = (height - 1);
+            sprite_list[i].palette = (attr & 0x0F) << 4;
+
+            if(yflip)
+                sprite_list[i].flags |= FLAG_YFLIP;
+
+            if(cgx)
+                sprite_list[i].flags |= FLAG_CGX;
+
+            if(!(attr & 0x80))
+                sprite_list[i].flags |= FLAG_PRIORITY;
+
+            used_sprite_list[used_sprite_index] = (i);
+            used_sprite_index += 1;
+        }
+    }
+
+    return (used_sprite_index);
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Pattern and object cache update routines                                 */
+/*--------------------------------------------------------------------------*/
+
+void update_bg_pattern_cache(void)
+{
+    int i;
+    uint8 x, y, c;
+    uint16 name, index1, index2;
+    uint32 temp;
+
+    if(!bg_list_index) return;
+
+    for(i = 0; i < bg_list_index; i += 1)
+    {
+        name = bg_name_list[i];
+        bg_name_list[i] = 0;
+
+        for(y = 0; y < 8; y += 1)
+        {
+            if(bg_name_dirty[name] & (1 << y))
+            {
+                index1 = vramw[(name << 4) | (y)];
+                index2 = vramw[(name << 4) | (y) | (8)];
+
+                temp = (bp_lut[index1] >> 2) | bp_lut[index2];
+
+                for(x = 0; x < 8; x += 1)
+                {
+                    c = (temp >> (x << 2)) & 0x0F;
+                    bg_pattern_cache[(name << 6) | (y << 3) | (x)] = (c);
+                }
+            }
+        }
+        bg_name_dirty[name] = 0;
+    }
+
+    bg_list_index = 0;
+}
+
+
+
+void update_obj_pattern_cache(void)
+{
+    int i;
+    uint16 name;
+    uint16 b0, b1, b2, b3;
+    uint8 i0, i1, i2, i3;           
+    uint8 x, y, c;
+
+    if(!obj_list_index) return;
+
+    for(i = 0; i < obj_list_index; i += 1)
+    {
+        name = obj_name_list[i];
+        obj_name_list[i] = 0;
+
+        for(y = 0; y < 0x10; y += 1)
+        {
+            if(obj_name_dirty[name] & (1 << y))
+            {
+                b0 = vramw[(name << 6) + (y) + (0x00)];
+                b1 = vramw[(name << 6) + (y) + (0x10)];
+                b2 = vramw[(name << 6) + (y) + (0x20)];
+                b3 = vramw[(name << 6) + (y) + (0x30)];
+
+                for(x = 0; x < 0x10; x += 1)
+                {
+                    i0 = (b0 >> (x ^ 0x0F)) & 1;
+                    i1 = (b1 >> (x ^ 0x0F)) & 1;
+                    i2 = (b2 >> (x ^ 0x0F)) & 1;
+                    i3 = (b3 >> (x ^ 0x0F)) & 1;
+
+                    c = (i3 << 3 | i2 << 2 | i1 << 1 | i0);
+
+                    obj_pattern_cache[(name << 8) | (y << 4) | (x)] = (c);
+                    //if (OBJ_CACHE_SIZE > 0x20000)
+                        obj_pattern_cache[0x20000 | (name << 8) | (y << 4) | (x ^ 0x0F)] = (c);
+                    //if (OBJ_CACHE_SIZE > 0x40000)
+                    //    obj_pattern_cache[0x40000 | (name << 8) | ((y ^ 0x0F) << 4) | (x)] = (c);
+                    //if (OBJ_CACHE_SIZE > 0x60000)
+                    //    obj_pattern_cache[0x60000 | (name << 8) | ((y ^ 0x0F) << 4) | (x ^ 0x0F)] = (c);
+                }
+            }
+        }
+        obj_name_dirty[name] = 0;
+    }
+    obj_list_index = 0;
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Render functions                                                         */
+/*--------------------------------------------------------------------------*/
+
+// 16 bits line rendering
+static unsigned short linebuf[1024];
+
+#define MIN(a,b) (a<b?a:b)
+void render_line_generic(int line)
+{
+    if((reg[0x05] & 0x80) && (plane_enable & 1))
+    {
+        update_bg_pattern_cache();
+        render_bg(line);
+    }
+    else
+    {
+        int i;
+        uint16 *ptr = (uint16 *)&linebuf[XOFFSET]; //&bitmap.data[(line * bitmap.pitch) + (XOFFSET * bitmap.granularity)];
+        for(i = 0; i < disp_width; i += 1) ptr[i] = pixel[0][0];                     
+    }
+
+    if((reg[0x05] & 0x40) && (plane_enable & 2))
+    {
+        update_obj_pattern_cache();
+        render_obj(line);
+    }
+   
+    emu_DrawLine16(&linebuf[XOFFSET], MIN(disp_width,256) , 240, line);
+
+}
+
+
+
+void render_bg(int line)
+{
+    uint16 *nt;
+    uint8 *src, palette;
+    uint16 *dst;   
+    int column, name, attr, x, shift, v_line, nt_scroll;
+    int xscroll = (reg[7] & 0x03FF);
+    int end = disp_nt_width;
+
+    /* Offset in pattern, in lines */
+    v_line = (y_offset & 7);
+
+    /* Offset in name table, in columns */
+    nt_scroll = (xscroll >> 3);
+
+    /* Offset in column, in pixels */
+    shift = (xscroll & 7);
+
+    /* Draw an extra tile for the last column */
+    if(shift) end += 1;
+
+    /* Point to current offset within name table */
+    nt = (uint16 *)&vram[(y_offset >> 3) << playfield_shift];
+
+    /* Point to start in line buffer */
+    dst = (uint16 *)&linebuf[XOFFSET - shift]; //&bitmap.data[(line * bitmap.pitch) + ((XOFFSET + (0 - shift)) << 1)];
+
+    /* Draw columns */
+    for(column = 0; column < end; column += 1)
+    {
+        /* Get attribute */
+        attr = nt[(column + nt_scroll) & playfield_row_mask];
+
+        /* Extract name and palette bits */
+        name = (attr & 0x07FF);
+        palette = (attr >> 8) & 0xF0;
+
+        /* Point to current pattern line */
+        src = &bg_pattern_cache[(name << 6) + (v_line << 3)];
+
+        /* Draw column */
+        for(x = 0; x < 8; x += 1)
+        {
+            dst[(column << 3) | (x)] = pixel[0][(src[x] | palette)];          
+        }
+    }
+}
+
+
+void render_obj(int line)
+{
+    t_sprite *p;
+    int j, i, x, c;
+    int name, name_mask;
+    int v_line;
+    uint8 *src;
+    int nt_line;
+    uint16 *dst;  
+
+    for(j = (used_sprite_index - 1); j >= 0; j -= 1)
+    {
+        i = used_sprite_list[j];
+        p = &sprite_list[i];
+
+        if( (line >= p->top) && (line < p->bottom))
+        {
+            v_line = (line - p->top) & p->height;
+            nt_line = v_line;
+            if(p->flags & FLAG_YFLIP) nt_line = (p->height - nt_line);
+            name_mask = ((nt_line >> 4) & 3) << 1;
+            name = (p->name_left | name_mask);
+            v_line &= 0x0F;
+            //src = &obj_pattern_cache[(name << 8) | ((v_line & 0x0f) << 4)];
+            src = &obj_pattern_cache[(name << 8) | ( (p->flags & FLAG_YFLIP?v_line ^ 0x0F:v_line) << 4)];
+            dst = (uint16 *)&linebuf[((XOFFSET+p->xpos) & 0x1ff)]; //&bitmap.data[(line * bitmap.pitch) + (((XOFFSET+p->xpos) & 0x1ff) * (bitmap.granularity))]; 
+            for(x = 0; x < 0x10; x += 1)
+            {
+                c = src[x];
+                //if ((unsigned int)&dst[x] < (unsigned int)&linebuf[400])
+               if(c) dst[x] = pixel[1][((c) | p->palette)];
+            }
+
+            if(p->flags & FLAG_CGX)
+            {
+                name = (p->name_right | name_mask);
+                //src = &obj_pattern_cache[(name << 8) | ((v_line & 0x0f) << 4)];
+                src = &obj_pattern_cache[(name << 8) | ( (p->flags & FLAG_YFLIP?v_line^ 0x0F:v_line) << 4)];
+                dst += 0x10;
+
+                for(x = 0; x < 0x10; x += 1)
+                {
+                    c = src[x];
+                    //if ((unsigned int)&dst[x] < (unsigned int)&linebuf[400])
+                   if(c) dst[x] = pixel[1][((c) | p->palette)];        
+                }
+            }             
+          
+        }
+       
+    }
+}
diff --git a/MCUME_pico2/picopceold/render.h b/MCUME_pico2/picopceold/render.h
new file mode 100644
index 0000000..502fa66
--- /dev/null
+++ b/MCUME_pico2/picopceold/render.h
@@ -0,0 +1,45 @@
+
+#ifndef _RENDER_H_
+#define _RENDER_H_
+
+#define FLAG_ENABLE         0x80    /* 1= Sprite is enabled */
+#define FLAG_PRIORITY       0x01    /* 1= Sprite behind background */
+#define FLAG_CGX            0x02    /* 1= Sprite is two patterns wide */
+#define FLAG_YFLIP          0x04    /* 1= Sprite is vertically flipped */
+
+typedef struct
+{
+    int32 top;              /* 0x00 */
+    int32 bottom;           /* 0x04 */
+    int32 xpos;             /* 0x08 */
+    uint32 name_left;       /* 0x0C */
+    uint32 name_right;      /* 0x10 */
+    uint32 height;          /* 0x14 */
+    uint8 palette;          /* 0x18 */
+    uint8 flags;            /* 0x19 */
+    uint8 filler[6];        /* 0x1A */           
+} t_sprite;
+
+/* Global data */
+extern int plane_enable;
+extern uint16 pixel[2][0x100];
+extern uint16 pixel_lut[0x200];
+extern void (*render_line)(int line);
+extern t_sprite sprite_list[0x40];
+//extern uint32 bp_lut[0x10000];
+extern const uint32 bp_lut[0x10000];
+extern uint8 used_sprite_list[0x40];
+extern uint8 used_sprite_index;
+
+/* Function prototypes */
+int render_init(void);
+void render_reset(void);
+void render_shutdown(void);
+int make_sprite_list(void);
+void update_bg_pattern_cache(void);
+void update_obj_pattern_cache(void);
+void render_line_generic(int line);
+void render_bg(int line);
+void render_obj(int line);
+
+#endif /* _RENDER_H_ */
diff --git a/MCUME_pico2/picopceold/shared.h b/MCUME_pico2/picopceold/shared.h
new file mode 100644
index 0000000..abc2a92
--- /dev/null
+++ b/MCUME_pico2/picopceold/shared.h
@@ -0,0 +1,21 @@
+
+#ifndef _SHARED_H_
+#define _SHARED_H_
+
+#define XOFFSET       0x20
+#define LSB_FIRST     1
+#define SOUND_PRESENT 1
+
+
+#include "pcetypes.h"
+#include "h6280.h"
+#include "pce.h"
+#include "vdc.h"
+#include "vce.h"
+#include "render.h"
+#include "system.h"
+#include "psg.h"
+#include "cpuintrf.h"
+#include "memory.h"
+
+#endif /* _SHARED_H_ */
diff --git a/MCUME_pico2/picopceold/system.c b/MCUME_pico2/picopceold/system.c
new file mode 100644
index 0000000..dc1162f
--- /dev/null
+++ b/MCUME_pico2/picopceold/system.c
@@ -0,0 +1,155 @@
+/*
+    Copyright (C) 2000, 2001  Charles MacDonald
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+#include "shared.h"
+
+t_bitmap bitmap;
+t_input input;
+t_snd pcesnd;
+
+
+/* Pass 0 for no sound, or 8000-44100 for desired sample rate */
+/* No error checking at the moment... */
+int system_init(int sample_rate)
+{
+    pce_init();
+    vdc_init();
+    psg_init();
+    render_init();
+#ifdef SOUND_PRESENT
+    audio_init(sample_rate);
+#endif
+    return (1);
+}
+
+#ifdef SOUND_PRESENT
+void audio_init(int rate)
+{
+    memset(&pcesnd, 0, sizeof(pcesnd));
+
+    /* Exit if no sound or invalid sample rate */
+    if(!rate || ((rate < 8000) || (rate > 44100))) return;
+    else
+    {
+        /* Buffer size = sample rate / frames per second */
+        //pcesnd.buffer_size = (rate / 60);
+
+        /* Keep local copy of sample rate for sound emulation */
+        //pcesnd.sample_rate = rate;
+
+        /* Allocate left channel buffer */
+        //pcesnd.buffer[0] = emu_Malloc(pcesnd.buffer_size * sizeof(int16));
+        //if(!pcesnd.buffer[0]) return;
+        /* Allocate right channel buffer */
+        //pcesnd.buffer[1] = emu_Malloc(pcesnd.buffer_size * sizeof(int16));
+        //if(!pcesnd.buffer[1]) return;
+
+        /* Set audio enable flag */
+        pcesnd.enabled = 1;
+    }
+}
+#endif
+
+void system_frame(int skip)
+{
+    int line;
+
+    for(y_offset = byr, line = 0; line < 262; line += 1)
+    {
+//        DEBUGLOG("system_frame 1\n");
+        if((line + 64) == (reg[6] & 0x3FF))
+        {
+            if(reg[5] & 0x04)
+            {
+                status |= STATUS_RR;
+                h6280_set_irq_line(0, ASSERT_LINE);
+            }
+        }
+//        DEBUGLOG("system_frame 2\n");
+
+        /* VBlank */
+        if(line == 240)
+        {
+            if(dvssr_trigger || (reg[0x0F] & 0x10))
+            {
+                /* Clear DVSSR write trigger */
+                dvssr_trigger = 0;
+
+                /* Copy VRAM to object RAM */
+                memcpy(objram, &vram[(reg[0x13] << 1) & 0xFFFE], 0x200);
+
+                /* Cause transfer complete interrupt if necessary */
+                if(reg[0x0F] & 0x01)
+                {
+                    status |= STATUS_DS;
+                    h6280_set_irq_line(0, ASSERT_LINE);
+                }
+
+                /* Precalculate sprite data for the next frame */
+                make_sprite_list();
+            }
+
+            /* Cause VBlank interrupt if necessary */
+            if(reg[5] & 0x0008)
+            {
+                status |= STATUS_VD;
+                h6280_set_irq_line(0, ASSERT_LINE);
+            }
+        }
+//        DEBUGLOG("system_frame 3\n");
+
+        /* 7.16 MHz = 455 cycles per line */
+        h6280_execute(455); 
+//        DEBUGLOG("system_frame 4\n");
+
+        /* Render a line of the display */
+        if((line < disp_height) && (!skip)) {
+
+            render_line(line);
+        }
+
+//        DEBUGLOG("system_frame 5\n");
+
+        /* Update internal line counter and wrap */
+        y_offset = (y_offset + 1) & playfield_col_mask;
+
+    }
+
+}
+
+void pce_sound(void)
+{
+    /* Update audio */
+    if(pcesnd.enabled) psg_update(pcesnd.buffer[0], pcesnd.buffer[1], pcesnd.buffer_size);
+}
+
+void system_reset(void)
+{
+    pce_reset();
+    vdc_reset();
+    psg_reset();
+    render_reset();
+}
+
+
+void system_shutdown(void)
+{
+    pce_shutdown();
+    vdc_shutdown();
+    psg_shutdown();
+    render_shutdown();
+}
diff --git a/MCUME_pico2/picopceold/system.h b/MCUME_pico2/picopceold/system.h
new file mode 100644
index 0000000..a6531e6
--- /dev/null
+++ b/MCUME_pico2/picopceold/system.h
@@ -0,0 +1,77 @@
+
+#ifndef _SYSTEM_H_
+#define _SYSTEM_H_
+
+/* Input devices */
+#define MAX_DEVICES         (5)     /* 1, or 5 with the MultiTap */
+#define DEVICE_2BUTTON      (0)     /* Standard 2-button pad */
+#define DEVICE_3BUTTON      (1)     /* 3-button pad */
+#define DEVICE_6BUTTON      (2)     /* 6-button pad */
+#define DEVICE_MULTITAP     (3)     /* MultiTap device */
+
+/* Input bitmasks */
+#define INPUT_B6        (0x00000800)    /* 6 button pad only */
+#define INPUT_B5        (0x00000400)    /* 6 button pad only */
+#define INPUT_B4        (0x00000200)    /* 6 button pad only */
+#define INPUT_B3        (0x00000100)    /* 3/6 button pad only */
+#define INPUT_B2        (0x00000080)
+#define INPUT_B1        (0x00000040)
+#define INPUT_RUN       (0x00000020)
+#define INPUT_SELECT    (0x00000010)
+#define INPUT_LEFT      (0x00000008)
+#define INPUT_RIGHT     (0x00000004)
+#define INPUT_DOWN      (0x00000002)
+#define INPUT_UP        (0x00000001)
+
+/* System input bitmasks */
+#define SYSTEM_TGX      (0x00000001)    /* System is 1=TGX, 0=PCE */
+
+typedef struct
+
+{
+    uint8 *data;        /* Bitmap data */
+    int width;          /* Bitmap width (32+512+32) */
+    int height;         /* Bitmap height (256) */
+    int depth;          /* Color depth (8 bits) */
+    int pitch;          /* Width of bitmap in bytes */
+    int granularity;    /* Size of each pixel in bytes */
+    struct {
+        int x;          /* X offset of viewport within bitmap */
+        int y;          /* Y offset of viewport within bitmap */
+        int w;          /* Width of viewport */
+        int h;          /* Height of viewport */
+        int ow;         /* Previous width of viewport */
+        int oh;         /* Previous height of viewport */
+        int changed;    /* 1= Viewport width or height have changed */
+    }viewport;
+}t_bitmap;  
+
+typedef struct
+{
+    uint8 dev[5];       /* Can be any of the DEVICE_* values */
+    uint32 pad[5];      /* Can be any of the INPUT_* bitmasks */
+    uint32 system;      /* Can be any of the SYSTEM_* bitmasks */
+}t_input;
+
+typedef struct
+{
+    int sample_rate;    /* Sample rate (8000-44100) */
+    int enabled;        /* 1= sound emulation is enabled */
+    int buffer_size;    /* Size of sound buffer (in bytes) */
+    int16 *buffer[2];   /* Signed 16-bit stereo sound data */
+}t_snd;
+
+/* Global variables */
+//extern t_bitmap bitmap;
+extern t_input input;
+extern t_snd pcesnd;
+
+/* Function prototypes */
+int system_init(int sample_rate);
+void audio_init(int rate);
+void system_frame(int skip);
+void system_reset(void);
+void system_shutdown(void);
+
+#endif /* _SYSTEM_H_ */
+
diff --git a/MCUME_pico2/picopceold/tblh6280.h b/MCUME_pico2/picopceold/tblh6280.h
new file mode 100644
index 0000000..d218e35
--- /dev/null
+++ b/MCUME_pico2/picopceold/tblh6280.h
@@ -0,0 +1,345 @@
+/*****************************************************************************
+
+    tblh6280.c
+
+	Copyright (c) 1999 Bryan McPhail, mish@tendril.co.uk
+
+	This source code is based (with permission!) on the 6502 emulator by
+	Juergen Buchmueller.  It is released as part of the Mame emulator project.
+	Let me know if you intend to use this code in any other project.
+
+******************************************************************************/
+
+#undef	OP
+//#define OP(nnn) static __inline__ void h6280_##nnn(void)
+#define OP(nnn) static void h6280_##nnn(void)
+
+/*****************************************************************************
+ *****************************************************************************
+ *
+ *	 Hu6280 opcodes
+ *
+ *****************************************************************************
+ * op	  temp	   cycles		      rdmem	  opc   wrmem   ******************/
+OP(000) {		   h6280_ICount -= 8;		  BRK;		   } // 8 BRK
+OP(020) {		   h6280_ICount -= 7; EA_ABS; JSR;		   } // 7 JSR  ABS
+OP(040) {		   h6280_ICount -= 7;		  RTI;		   } // 7 RTI
+OP(060) {		   h6280_ICount -= 7;		  RTS;		   } // 7 RTS
+OP(080) { int tmp;  				          BRA(1);	   } // 4 BRA  REL
+OP(0a0) { int tmp; h6280_ICount -= 2; RD_IMM; LDY;		   } // 2 LDY  IMM
+OP(0c0) { int tmp; h6280_ICount -= 2; RD_IMM; CPY;		   } // 2 CPY  IMM
+OP(0e0) { int tmp; h6280_ICount -= 2; RD_IMM; CPX;		   } // 2 CPX  IMM
+
+OP(010) { int tmp;							  BPL;		   } // 2/4 BPL  REL
+OP(030) { int tmp;							  BMI;		   } // 2/4 BMI  REL
+OP(050) { int tmp;							  BVC;		   } // 2/4 BVC  REL
+OP(070) { int tmp;							  BVS;		   } // 2/4 BVS  REL
+OP(090) { int tmp;							  BCC;		   } // 2/4 BCC  REL
+OP(0b0) { int tmp;							  BCS;		   } // 2/4 BCS  REL
+OP(0d0) { int tmp;							  BNE;		   } // 2/4 BNE  REL
+OP(0f0) { int tmp;							  BEQ;		   } // 2/4 BEQ  REL
+
+OP(001) { int tmp; h6280_ICount -= 7; RD_IDX; ORA;		   } // 7 ORA  IDX
+OP(021) { int tmp; h6280_ICount -= 7; RD_IDX; AND;		   } // 7 AND  IDX
+OP(041) { int tmp; h6280_ICount -= 7; RD_IDX; EOR;		   } // 7 EOR  IDX
+OP(061) { int tmp; h6280_ICount -= 7; RD_IDX; ADC;		   } // 7 ADC  IDX
+OP(081) { int tmp; h6280_ICount -= 7;         STA; WR_IDX; } // 7 STA  IDX
+OP(0a1) { int tmp; h6280_ICount -= 7; RD_IDX; LDA;		   } // 7 LDA  IDX
+OP(0c1) { int tmp; h6280_ICount -= 7; RD_IDX; CMP;		   } // 7 CMP  IDX
+OP(0e1) { int tmp; h6280_ICount -= 7; RD_IDX; SBC;		   } // 7 SBC  IDX
+
+OP(011) { int tmp; h6280_ICount -= 7; RD_IDY; ORA;		   } // 7 ORA  IDY
+OP(031) { int tmp; h6280_ICount -= 7; RD_IDY; AND;		   } // 7 AND  IDY
+OP(051) { int tmp; h6280_ICount -= 7; RD_IDY; EOR;		   } // 7 EOR  IDY
+OP(071) { int tmp; h6280_ICount -= 7; RD_IDY; ADC;		   } // 7 ADC  AZP
+OP(091) { int tmp; h6280_ICount -= 7;		  STA; WR_IDY; } // 7 STA  IDY
+OP(0b1) { int tmp; h6280_ICount -= 7; RD_IDY; LDA;		   } // 7 LDA  IDY
+OP(0d1) { int tmp; h6280_ICount -= 7; RD_IDY; CMP;		   } // 7 CMP  IDY
+OP(0f1) { int tmp; h6280_ICount -= 7; RD_IDY; SBC;		   } // 7 SBC  IDY
+
+OP(002) { int tmp; h6280_ICount -= 3;		  SXY;		   } // 3 SXY
+OP(022) { int tmp; h6280_ICount -= 3;		  SAX;		   } // 3 SAX
+OP(042) { int tmp; h6280_ICount -= 3;		  SAY;		   } // 3 SAY
+OP(062) {		   h6280_ICount -= 2;		  CLA;		   } // 2 CLA
+OP(082) {		   h6280_ICount -= 2;		  CLX;		   } // 2 CLX
+OP(0a2) { int tmp; h6280_ICount -= 2; RD_IMM; LDX;		   } // 2 LDX  IMM
+OP(0c2) {		   h6280_ICount -= 2;		  CLY;		   } // 2 CLY
+OP(0e2) {									  ILL;		   } // 2 ???
+
+OP(012) { int tmp; h6280_ICount -= 7; RD_ZPI; ORA;		   } // 7 ORA  ZPI
+OP(032) { int tmp; h6280_ICount -= 7; RD_ZPI; AND;		   } // 7 AND  ZPI
+OP(052) { int tmp; h6280_ICount -= 7; RD_ZPI; EOR;		   } // 7 EOR  ZPI
+OP(072) { int tmp; h6280_ICount -= 7; RD_ZPI; ADC;		   } // 7 ADC  ZPI
+OP(092) { int tmp; h6280_ICount -= 7;		  STA; WR_ZPI; } // 7 STA  ZPI
+OP(0b2) { int tmp; h6280_ICount -= 7; RD_ZPI; LDA;		   } // 7 LDA  ZPI
+OP(0d2) { int tmp; h6280_ICount -= 7; RD_ZPI; CMP;		   } // 7 CMP  ZPI
+OP(0f2) { int tmp; h6280_ICount -= 7; RD_ZPI; SBC;		   } // 7 SBC  ZPI
+
+OP(003) { int tmp; h6280_ICount -= 4; RD_IMM; ST0;		   } // 4 ST0  IMM
+OP(023) { int tmp; h6280_ICount -= 4; RD_IMM; ST2;		   } // 4 ST2  IMM
+OP(043) { int tmp; h6280_ICount -= 4; RD_IMM; TMA;		   } // 4 TMA
+OP(063) {									  ILL;		   } // 2 ???
+OP(083) { int tmp,tmp2; h6280_ICount -= 7; RD_IMM2; RD_ZPG; TST; } // 7 TST  IMM,ZPG
+OP(0a3) { int tmp,tmp2; h6280_ICount -= 7; RD_IMM2; RD_ZPX; TST; } // 7 TST  IMM,ZPX
+OP(0c3) { int to,from,length;			      TDD;		   } // 6*l+17 TDD  XFER
+OP(0e3) { int to,from,length,alternate;       TIA;		   } // 6*l+17 TIA  XFER
+
+OP(013) { int tmp; h6280_ICount -= 4; RD_IMM; ST1;		   } // 4 ST1
+OP(033) {       							  ILL;		   } // 2 ???
+OP(053) { int tmp; h6280_ICount -= 5; RD_IMM; TAM;		   } // 5 TAM  IMM
+OP(073) { int to,from,length;    			  TII;		   } // 6*l+17 TII  XFER
+OP(093) { int tmp,tmp2; h6280_ICount -= 8; RD_IMM2; RD_ABS; TST; } // 8 TST  IMM,ABS
+OP(0b3) { int tmp,tmp2; h6280_ICount -= 8; RD_IMM2; RD_ABX; TST; } // 8 TST  IMM,ABX
+OP(0d3) { int to,from,length;			      TIN;		   } // 6*l+17 TIN  XFER
+OP(0f3) { int to,from,length,alternate;       TAI;		   } // 6*l+17 TAI  XFER
+
+OP(004) { int tmp; h6280_ICount -= 6; RD_ZPG; TSB; WB_EAZ; } // 6 TSB  ZPG
+OP(024) { int tmp; h6280_ICount -= 4; RD_ZPG; BIT;		   } // 4 BIT  ZPG
+OP(044) { int tmp;							  BSR;		   } // 8 BSR  REL
+OP(064) { int tmp; h6280_ICount -= 4;		  STZ; WR_ZPG; } // 4 STZ  ZPG
+OP(084) { int tmp; h6280_ICount -= 4;		  STY; WR_ZPG; } // 4 STY  ZPG
+OP(0a4) { int tmp; h6280_ICount -= 4; RD_ZPG; LDY;		   } // 4 LDY  ZPG
+OP(0c4) { int tmp; h6280_ICount -= 4; RD_ZPG; CPY;		   } // 4 CPY  ZPG
+OP(0e4) { int tmp; h6280_ICount -= 4; RD_ZPG; CPX;		   } // 4 CPX  ZPG
+
+OP(014) { int tmp; h6280_ICount -= 6; RD_ZPG; TRB; WB_EAZ; } // 6 TRB  ZPG
+OP(034) { int tmp; h6280_ICount -= 4; RD_ZPX; BIT;		   } // 4 BIT  ZPX
+OP(054) {          h6280_ICount -= 2;         CSL;         } // 2 CSL
+OP(074) { int tmp; h6280_ICount -= 4;		  STZ; WR_ZPX; } // 4 STZ  ZPX
+OP(094) { int tmp; h6280_ICount -= 4;		  STY; WR_ZPX; } // 4 STY  ZPX
+OP(0b4) { int tmp; h6280_ICount -= 4; RD_ZPX; LDY;		   } // 4 LDY  ZPX
+OP(0d4) {          h6280_ICount -= 2;         CSH;         } // 2 CSH
+OP(0f4) {		   h6280_ICount -= 2;		  SET;		   } // 2 SET
+
+OP(005) { int tmp; h6280_ICount -= 4; RD_ZPG; ORA;		   } // 4 ORA  ZPG
+OP(025) { int tmp; h6280_ICount -= 4; RD_ZPG; AND;		   } // 4 AND  ZPG
+OP(045) { int tmp; h6280_ICount -= 4; RD_ZPG; EOR;		   } // 4 EOR  ZPG
+OP(065) { int tmp; h6280_ICount -= 4; RD_ZPG; ADC;		   } // 4 ADC  ZPG
+OP(085) { int tmp; h6280_ICount -= 4;		  STA; WR_ZPG; } // 4 STA  ZPG
+OP(0a5) { int tmp; h6280_ICount -= 4; RD_ZPG; LDA;		   } // 4 LDA  ZPG
+OP(0c5) { int tmp; h6280_ICount -= 4; RD_ZPG; CMP;		   } // 4 CMP  ZPG
+OP(0e5) { int tmp; h6280_ICount -= 4; RD_ZPG; SBC;		   } // 4 SBC  ZPG
+
+OP(015) { int tmp; h6280_ICount -= 4; RD_ZPX; ORA;		   } // 4 ORA  ZPX
+OP(035) { int tmp; h6280_ICount -= 4; RD_ZPX; AND;		   } // 4 AND  ZPX
+OP(055) { int tmp; h6280_ICount -= 4; RD_ZPX; EOR;		   } // 4 EOR  ZPX
+OP(075) { int tmp; h6280_ICount -= 4; RD_ZPX; ADC;		   } // 4 ADC  ZPX
+OP(095) { int tmp; h6280_ICount -= 4;		  STA; WR_ZPX; } // 4 STA  ZPX
+OP(0b5) { int tmp; h6280_ICount -= 4; RD_ZPX; LDA;		   } // 4 LDA  ZPX
+OP(0d5) { int tmp; h6280_ICount -= 4; RD_ZPX; CMP;		   } // 4 CMP  ZPX
+OP(0f5) { int tmp; h6280_ICount -= 4; RD_ZPX; SBC;		   } // 4 SBC  ZPX
+
+OP(006) { int tmp; h6280_ICount -= 6; RD_ZPG; ASL; WB_EAZ; } // 6 ASL  ZPG
+OP(026) { int tmp; h6280_ICount -= 6; RD_ZPG; ROL; WB_EAZ; } // 6 ROL  ZPG
+OP(046) { int tmp; h6280_ICount -= 6; RD_ZPG; LSR; WB_EAZ; } // 6 LSR  ZPG
+OP(066) { int tmp; h6280_ICount -= 6; RD_ZPG; ROR; WB_EAZ; } // 6 ROR  ZPG
+OP(086) { int tmp; h6280_ICount -= 4;		  STX; WR_ZPG; } // 4 STX  ZPG
+OP(0a6) { int tmp; h6280_ICount -= 4; RD_ZPG; LDX;		   } // 4 LDX  ZPG
+OP(0c6) { int tmp; h6280_ICount -= 6; RD_ZPG; DEC; WB_EAZ; } // 6 DEC  ZPG
+OP(0e6) { int tmp; h6280_ICount -= 6; RD_ZPG; INC; WB_EAZ; } // 6 INC  ZPG
+
+OP(016) { int tmp; h6280_ICount -= 6; RD_ZPX; ASL; WB_EAZ  } // 6 ASL  ZPX
+OP(036) { int tmp; h6280_ICount -= 6; RD_ZPX; ROL; WB_EAZ  } // 6 ROL  ZPX
+OP(056) { int tmp; h6280_ICount -= 6; RD_ZPX; LSR; WB_EAZ  } // 6 LSR  ZPX
+OP(076) { int tmp; h6280_ICount -= 6; RD_ZPX; ROR; WB_EAZ  } // 6 ROR  ZPX
+OP(096) { int tmp; h6280_ICount -= 4;		  STX; WR_ZPY; } // 4 STX  ZPY
+OP(0b6) { int tmp; h6280_ICount -= 4; RD_ZPY; LDX;		   } // 4 LDX  ZPY
+OP(0d6) { int tmp; h6280_ICount -= 6; RD_ZPX; DEC; WB_EAZ; } // 6 DEC  ZPX
+OP(0f6) { int tmp; h6280_ICount -= 6; RD_ZPX; INC; WB_EAZ; } // 6 INC  ZPX
+
+OP(007) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(0);WB_EAZ;} // 7 RMB0 ZPG
+OP(027) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(2);WB_EAZ;} // 7 RMB2 ZPG
+OP(047) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(4);WB_EAZ;} // 7 RMB4 ZPG
+OP(067) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(6);WB_EAZ;} // 7 RMB6 ZPG
+OP(087) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(0);WB_EAZ;} // 7 SMB0 ZPG
+OP(0a7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(2);WB_EAZ;} // 7 SMB2 ZPG
+OP(0c7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(4);WB_EAZ;} // 7 SMB4 ZPG
+OP(0e7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(6);WB_EAZ;} // 7 SMB6 ZPG
+
+OP(017) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(1);WB_EAZ;} // 7 RMB1 ZPG
+OP(037) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(3);WB_EAZ;} // 7 RMB3 ZPG
+OP(057) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(5);WB_EAZ;} // 7 RMB5 ZPG
+OP(077) { int tmp; h6280_ICount -= 7; RD_ZPG; RMB(7);WB_EAZ;} // 7 RMB7 ZPG
+OP(097) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(1);WB_EAZ;} // 7 SMB1 ZPG
+OP(0b7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(3);WB_EAZ;} // 7 SMB3 ZPG
+OP(0d7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(5);WB_EAZ;} // 7 SMB5 ZPG
+OP(0f7) { int tmp; h6280_ICount -= 7; RD_ZPG; SMB(7);WB_EAZ;} // 7 SMB7 ZPG
+
+OP(008) {		   h6280_ICount -= 3;		  PHP;		   } // 3 PHP
+OP(028) {		   h6280_ICount -= 4;		  PLP;		   } // 4 PLP
+OP(048) {		   h6280_ICount -= 3;		  PHA;		   } // 3 PHA
+OP(068) {		   h6280_ICount -= 4;		  PLA;		   } // 4 PLA
+OP(088) {		   h6280_ICount -= 2;		  DEY;		   } // 2 DEY
+OP(0a8) {		   h6280_ICount -= 2;		  TAY;		   } // 2 TAY
+OP(0c8) {		   h6280_ICount -= 2;		  INY;		   } // 2 INY
+OP(0e8) {		   h6280_ICount -= 2;		  INX;		   } // 2 INX
+
+OP(018) {		   h6280_ICount -= 2;		  CLC;		   } // 2 CLC
+OP(038) {		   h6280_ICount -= 2;		  SEC;		   } // 2 SEC
+OP(058) {		   h6280_ICount -= 2;		  CLI;		   } // 2 CLI
+OP(078) {		   h6280_ICount -= 2;		  SEI;		   } // 2 SEI
+OP(098) {		   h6280_ICount -= 2;		  TYA;		   } // 2 TYA
+OP(0b8) {		   h6280_ICount -= 2;		  CLV;		   } // 2 CLV
+OP(0d8) {		   h6280_ICount -= 2;		  CLD;		   } // 2 CLD
+OP(0f8) {		   h6280_ICount -= 2;		  SED;		   } // 2 SED
+
+OP(009) { int tmp; h6280_ICount -= 2; RD_IMM; ORA;		   } // 2 ORA  IMM
+OP(029) { int tmp; h6280_ICount -= 2; RD_IMM; AND;		   } // 2 AND  IMM
+OP(049) { int tmp; h6280_ICount -= 2; RD_IMM; EOR;		   } // 2 EOR  IMM
+OP(069) { int tmp; h6280_ICount -= 2; RD_IMM; ADC;		   } // 2 ADC  IMM
+OP(089) { int tmp; h6280_ICount -= 2; RD_IMM; BIT;		   } // 2 BIT  IMM
+OP(0a9) { int tmp; h6280_ICount -= 2; RD_IMM; LDA;		   } // 2 LDA  IMM
+OP(0c9) { int tmp; h6280_ICount -= 2; RD_IMM; CMP;		   } // 2 CMP  IMM
+OP(0e9) { int tmp; h6280_ICount -= 2; RD_IMM; SBC;		   } // 2 SBC  IMM
+
+OP(019) { int tmp; h6280_ICount -= 5; RD_ABY; ORA;		   } // 5 ORA  ABY
+OP(039) { int tmp; h6280_ICount -= 5; RD_ABY; AND;		   } // 5 AND  ABY
+OP(059) { int tmp; h6280_ICount -= 5; RD_ABY; EOR;		   } // 5 EOR  ABY
+OP(079) { int tmp; h6280_ICount -= 5; RD_ABY; ADC;		   } // 5 ADC  ABY
+OP(099) { int tmp; h6280_ICount -= 5;		  STA; WR_ABY; } // 5 STA  ABY
+OP(0b9) { int tmp; h6280_ICount -= 5; RD_ABY; LDA;		   } // 5 LDA  ABY
+OP(0d9) { int tmp; h6280_ICount -= 5; RD_ABY; CMP;		   } // 5 CMP  ABY
+OP(0f9) { int tmp; h6280_ICount -= 5; RD_ABY; SBC;		   } // 5 SBC  ABY
+
+OP(00a) { int tmp; h6280_ICount -= 2; RD_ACC; ASL; WB_ACC; } // 2 ASL  A
+OP(02a) { int tmp; h6280_ICount -= 2; RD_ACC; ROL; WB_ACC; } // 2 ROL  A
+OP(04a) { int tmp; h6280_ICount -= 2; RD_ACC; LSR; WB_ACC; } // 2 LSR  A
+OP(06a) { int tmp; h6280_ICount -= 2; RD_ACC; ROR; WB_ACC; } // 2 ROR  A
+OP(08a) {		   h6280_ICount -= 2;		  TXA;		   } // 2 TXA
+OP(0aa) {		   h6280_ICount -= 2;		  TAX;		   } // 2 TAX
+OP(0ca) {		   h6280_ICount -= 2;		  DEX;		   } // 2 DEX
+OP(0ea) {		   h6280_ICount -= 2;		  NOP;		   } // 2 NOP
+
+OP(01a) {		   h6280_ICount -= 2;		  INA;		   } // 2 INC  A
+OP(03a) {		   h6280_ICount -= 2;		  DEA;		   } // 2 DEC  A
+OP(05a) {		   h6280_ICount -= 3;		  PHY;		   } // 3 PHY
+OP(07a) {		   h6280_ICount -= 4;		  PLY;		   } // 4 PLY
+OP(09a) {		   h6280_ICount -= 2;		  TXS;		   } // 2 TXS
+OP(0ba) {		   h6280_ICount -= 2;		  TSX;		   } // 2 TSX
+OP(0da) {		   h6280_ICount -= 3;		  PHX;		   } // 3 PHX
+OP(0fa) {		   h6280_ICount -= 4;		  PLX;		   } // 4 PLX
+
+OP(00b) {									  ILL;		   } // 2 ???
+OP(02b) {									  ILL;		   } // 2 ???
+OP(04b) {									  ILL;		   } // 2 ???
+OP(06b) {									  ILL;		   } // 2 ???
+OP(08b) {									  ILL;		   } // 2 ???
+OP(0ab) {									  ILL;		   } // 2 ???
+OP(0cb) {									  ILL;		   } // 2 ???
+OP(0eb) {									  ILL;		   } // 2 ???
+
+OP(01b) {									  ILL;		   } // 2 ???
+OP(03b) {									  ILL;		   } // 2 ???
+OP(05b) {									  ILL;		   } // 2 ???
+OP(07b) {									  ILL;		   } // 2 ???
+OP(09b) {									  ILL;		   } // 2 ???
+OP(0bb) {									  ILL;		   } // 2 ???
+OP(0db) {									  ILL;		   } // 2 ???
+OP(0fb) {									  ILL;		   } // 2 ???
+
+OP(00c) { int tmp; h6280_ICount -= 7; RD_ABS; TSB; WB_EA;  } // 7 TSB  ABS
+OP(02c) { int tmp; h6280_ICount -= 5; RD_ABS; BIT;		   } // 5 BIT  ABS
+OP(04c) {		   h6280_ICount -= 4; EA_ABS; JMP;		   } // 4 JMP  ABS
+OP(06c) { int tmp; h6280_ICount -= 7; EA_IND; JMP;		   } // 7 JMP  IND
+OP(08c) { int tmp; h6280_ICount -= 5;		  STY; WR_ABS; } // 5 STY  ABS
+OP(0ac) { int tmp; h6280_ICount -= 5; RD_ABS; LDY;		   } // 5 LDY  ABS
+OP(0cc) { int tmp; h6280_ICount -= 5; RD_ABS; CPY;		   } // 5 CPY  ABS
+OP(0ec) { int tmp; h6280_ICount -= 5; RD_ABS; CPX;		   } // 5 CPX  ABS
+
+OP(01c) { int tmp; h6280_ICount -= 7; RD_ABS; TRB; WB_EA;  } // 7 TRB  ABS
+OP(03c) { int tmp; h6280_ICount -= 5; RD_ABX; BIT;		   } // 5 BIT  ABX
+OP(05c) {									  ILL;		   } // 2 ???
+OP(07c) { int tmp; h6280_ICount -= 7; EA_IAX; JMP;		   } // 7 JMP  IAX
+OP(09c) { int tmp; h6280_ICount -= 5;		  STZ; WR_ABS; } // 5 STZ  ABS
+OP(0bc) { int tmp; h6280_ICount -= 5; RD_ABX; LDY;		   } // 5 LDY  ABX
+OP(0dc) {									  ILL;		   } // 2 ???
+OP(0fc) {									  ILL;		   } // 2 ???
+
+OP(00d) { int tmp; h6280_ICount -= 5; RD_ABS; ORA;		   } // 5 ORA  ABS
+OP(02d) { int tmp; h6280_ICount -= 5; RD_ABS; AND;		   } // 4 AND  ABS
+OP(04d) { int tmp; h6280_ICount -= 5; RD_ABS; EOR;		   } // 4 EOR  ABS
+OP(06d) { int tmp; h6280_ICount -= 5; RD_ABS; ADC;		   } // 4 ADC  ABS
+OP(08d) { int tmp; h6280_ICount -= 5;		  STA; WR_ABS; } // 4 STA  ABS
+OP(0ad) { int tmp; h6280_ICount -= 5; RD_ABS; LDA;		   } // 4 LDA  ABS
+OP(0cd) { int tmp; h6280_ICount -= 5; RD_ABS; CMP;		   } // 4 CMP  ABS
+OP(0ed) { int tmp; h6280_ICount -= 5; RD_ABS; SBC;		   } // 4 SBC  ABS
+
+OP(01d) { int tmp; h6280_ICount -= 5; RD_ABX; ORA;		   } // 5 ORA  ABX
+OP(03d) { int tmp; h6280_ICount -= 5; RD_ABX; AND;		   } // 4 AND  ABX
+OP(05d) { int tmp; h6280_ICount -= 5; RD_ABX; EOR;		   } // 4 EOR  ABX
+OP(07d) { int tmp; h6280_ICount -= 5; RD_ABX; ADC;		   } // 4 ADC  ABX
+OP(09d) { int tmp; h6280_ICount -= 5;		  STA; WR_ABX; } // 5 STA  ABX
+OP(0bd) { int tmp; h6280_ICount -= 5; RD_ABX; LDA;		   } // 5 LDA  ABX
+OP(0dd) { int tmp; h6280_ICount -= 5; RD_ABX; CMP;		   } // 4 CMP  ABX
+OP(0fd) { int tmp; h6280_ICount -= 5; RD_ABX; SBC;		   } // 4 SBC  ABX
+
+OP(00e) { int tmp; h6280_ICount -= 7; RD_ABS; ASL; WB_EA;  } // 6 ASL  ABS
+OP(02e) { int tmp; h6280_ICount -= 7; RD_ABS; ROL; WB_EA;  } // 6 ROL  ABS
+OP(04e) { int tmp; h6280_ICount -= 7; RD_ABS; LSR; WB_EA;  } // 6 LSR  ABS
+OP(06e) { int tmp; h6280_ICount -= 7; RD_ABS; ROR; WB_EA;  } // 6 ROR  ABS
+OP(08e) { int tmp; h6280_ICount -= 5;		  STX; WR_ABS; } // 4 STX  ABS
+OP(0ae) { int tmp; h6280_ICount -= 5; RD_ABS; LDX;		   } // 5 LDX  ABS
+OP(0ce) { int tmp; h6280_ICount -= 7; RD_ABS; DEC; WB_EA;  } // 6 DEC  ABS
+OP(0ee) { int tmp; h6280_ICount -= 7; RD_ABS; INC; WB_EA;  } // 6 INC  ABS
+
+OP(01e) { int tmp; h6280_ICount -= 7; RD_ABX; ASL; WB_EA;  } // 7 ASL  ABX
+OP(03e) { int tmp; h6280_ICount -= 7; RD_ABX; ROL; WB_EA;  } // 7 ROL  ABX
+OP(05e) { int tmp; h6280_ICount -= 7; RD_ABX; LSR; WB_EA;  } // 7 LSR  ABX
+OP(07e) { int tmp; h6280_ICount -= 7; RD_ABX; ROR; WB_EA;  } // 7 ROR  ABX
+OP(09e) { int tmp; h6280_ICount -= 5;		  STZ; WR_ABX; } // 5 STZ  ABX
+OP(0be) { int tmp; h6280_ICount -= 5; RD_ABY; LDX;		   } // 4 LDX  ABY
+OP(0de) { int tmp; h6280_ICount -= 7; RD_ABX; DEC; WB_EA;  } // 7 DEC  ABX
+OP(0fe) { int tmp; h6280_ICount -= 7; RD_ABX; INC; WB_EA;  } // 7 INC  ABX
+
+OP(00f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(0);	   } // 6/8 BBR0 ZPG,REL
+OP(02f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(2);	   } // 6/8 BBR2 ZPG,REL
+OP(04f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(4);	   } // 6/8 BBR4 ZPG,REL
+OP(06f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(6);	   } // 6/8 BBR6 ZPG,REL
+OP(08f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(0);	   } // 6/8 BBS0 ZPG,REL
+OP(0af) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(2);	   } // 6/8 BBS2 ZPG,REL
+OP(0cf) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(4);	   } // 6/8 BBS4 ZPG,REL
+OP(0ef) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(6);	   } // 6/8 BBS6 ZPG,REL
+
+OP(01f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(1);	   } // 6/8 BBR1 ZPG,REL
+OP(03f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(3);	   } // 6/8 BBR3 ZPG,REL
+OP(05f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(5);	   } // 6/8 BBR5 ZPG,REL
+OP(07f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBR(7);	   } // 6/8 BBR7 ZPG,REL
+OP(09f) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(1);	   } // 6/8 BBS1 ZPG,REL
+OP(0bf) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(3);	   } // 6/8 BBS3 ZPG,REL
+OP(0df) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(5);	   } // 6/8 BBS5 ZPG,REL
+OP(0ff) { int tmp; h6280_ICount -= 4; RD_ZPG; BBS(7);	   } // 6/8 BBS7 ZPG,REL
+
+static void (*insnh6280[0x100])(void) = {
+	h6280_000,h6280_001,h6280_002,h6280_003,h6280_004,h6280_005,h6280_006,h6280_007,
+	h6280_008,h6280_009,h6280_00a,h6280_00b,h6280_00c,h6280_00d,h6280_00e,h6280_00f,
+	h6280_010,h6280_011,h6280_012,h6280_013,h6280_014,h6280_015,h6280_016,h6280_017,
+	h6280_018,h6280_019,h6280_01a,h6280_01b,h6280_01c,h6280_01d,h6280_01e,h6280_01f,
+	h6280_020,h6280_021,h6280_022,h6280_023,h6280_024,h6280_025,h6280_026,h6280_027,
+	h6280_028,h6280_029,h6280_02a,h6280_02b,h6280_02c,h6280_02d,h6280_02e,h6280_02f,
+	h6280_030,h6280_031,h6280_032,h6280_033,h6280_034,h6280_035,h6280_036,h6280_037,
+	h6280_038,h6280_039,h6280_03a,h6280_03b,h6280_03c,h6280_03d,h6280_03e,h6280_03f,
+	h6280_040,h6280_041,h6280_042,h6280_043,h6280_044,h6280_045,h6280_046,h6280_047,
+	h6280_048,h6280_049,h6280_04a,h6280_04b,h6280_04c,h6280_04d,h6280_04e,h6280_04f,
+	h6280_050,h6280_051,h6280_052,h6280_053,h6280_054,h6280_055,h6280_056,h6280_057,
+	h6280_058,h6280_059,h6280_05a,h6280_05b,h6280_05c,h6280_05d,h6280_05e,h6280_05f,
+	h6280_060,h6280_061,h6280_062,h6280_063,h6280_064,h6280_065,h6280_066,h6280_067,
+	h6280_068,h6280_069,h6280_06a,h6280_06b,h6280_06c,h6280_06d,h6280_06e,h6280_06f,
+	h6280_070,h6280_071,h6280_072,h6280_073,h6280_074,h6280_075,h6280_076,h6280_077,
+	h6280_078,h6280_079,h6280_07a,h6280_07b,h6280_07c,h6280_07d,h6280_07e,h6280_07f,
+	h6280_080,h6280_081,h6280_082,h6280_083,h6280_084,h6280_085,h6280_086,h6280_087,
+	h6280_088,h6280_089,h6280_08a,h6280_08b,h6280_08c,h6280_08d,h6280_08e,h6280_08f,
+	h6280_090,h6280_091,h6280_092,h6280_093,h6280_094,h6280_095,h6280_096,h6280_097,
+	h6280_098,h6280_099,h6280_09a,h6280_09b,h6280_09c,h6280_09d,h6280_09e,h6280_09f,
+	h6280_0a0,h6280_0a1,h6280_0a2,h6280_0a3,h6280_0a4,h6280_0a5,h6280_0a6,h6280_0a7,
+	h6280_0a8,h6280_0a9,h6280_0aa,h6280_0ab,h6280_0ac,h6280_0ad,h6280_0ae,h6280_0af,
+	h6280_0b0,h6280_0b1,h6280_0b2,h6280_0b3,h6280_0b4,h6280_0b5,h6280_0b6,h6280_0b7,
+	h6280_0b8,h6280_0b9,h6280_0ba,h6280_0bb,h6280_0bc,h6280_0bd,h6280_0be,h6280_0bf,
+	h6280_0c0,h6280_0c1,h6280_0c2,h6280_0c3,h6280_0c4,h6280_0c5,h6280_0c6,h6280_0c7,
+	h6280_0c8,h6280_0c9,h6280_0ca,h6280_0cb,h6280_0cc,h6280_0cd,h6280_0ce,h6280_0cf,
+	h6280_0d0,h6280_0d1,h6280_0d2,h6280_0d3,h6280_0d4,h6280_0d5,h6280_0d6,h6280_0d7,
+	h6280_0d8,h6280_0d9,h6280_0da,h6280_0db,h6280_0dc,h6280_0dd,h6280_0de,h6280_0df,
+	h6280_0e0,h6280_0e1,h6280_0e2,h6280_0e3,h6280_0e4,h6280_0e5,h6280_0e6,h6280_0e7,
+	h6280_0e8,h6280_0e9,h6280_0ea,h6280_0eb,h6280_0ec,h6280_0ed,h6280_0ee,h6280_0ef,
+	h6280_0f0,h6280_0f1,h6280_0f2,h6280_0f3,h6280_0f4,h6280_0f5,h6280_0f6,h6280_0f7,
+	h6280_0f8,h6280_0f9,h6280_0fa,h6280_0fb,h6280_0fc,h6280_0fd,h6280_0fe,h6280_0ff
+};
diff --git a/MCUME_pico2/picopceold/vce.c b/MCUME_pico2/picopceold/vce.c
new file mode 100644
index 0000000..e7bacae
--- /dev/null
+++ b/MCUME_pico2/picopceold/vce.c
@@ -0,0 +1,79 @@
+
+#include "shared.h"
+
+t_vce vce;
+
+void vce_w(int address, int data)
+{
+    int msb = (address & 1);
+
+    switch(address & ~1)
+    {
+        case 0x404: /* Data */
+            {
+                if(data != vce.data[((vce.addr & 0x1FF) << 1) | (msb)])
+                {
+                    vce.data[((vce.addr & 0x1FF) << 1) | (msb)] = data;
+
+                    if((vce.addr & 0x0F) != 0x00)
+                    {
+//                        uint16 temp = *(uint16 *)&vce.data[(vce.addr << 1)];    // Execute error.
+                        uint8 temp1 = vce.data[(vce.addr << 1)];
+                        uint8 temp2 = vce.data[(vce.addr << 1)+1];
+                        uint16 temp;
+#ifndef LSB_FIRST
+//                      temp = (temp >> 8) | (temp << 8);
+                        temp = (((uint16)temp1) << 8) + (uint16)temp2;
+#else
+                        temp = (((uint16)temp2) << 8) + (uint16)temp1;                      
+#endif
+                        pixel[(vce.addr >> 8) & 1][(vce.addr & 0xFF)] = pixel_lut[temp];
+                        temp = (temp >> 1) & 0xFF;
+                    }
+
+                    /* Update overscan color */
+                    if((vce.addr & 0x0F) == 0x00)
+                    {
+                        int n;
+                        uint16 temp = *(uint16 *)&vce.data[0];
+#ifndef LSB_FIRST
+                        temp = (temp >> 8) | (temp << 8);
+#endif
+                        for(n = 0; n < 0x10; n += 1)
+                            pixel[0][(n << 4)] = pixel_lut[temp];
+                        temp = (temp >> 1) & 0xFF;                                                
+                    }
+                }
+            }
+
+            /* Increment VCE address on access to the MSB data port */
+            if(msb) vce.addr += 1;
+            break;
+
+        case 0x402: /* Address */
+            if(msb)
+                vce.addr = (vce.addr & 0x00FF) | ((data & 1) << 8);
+            else
+                vce.addr = (vce.addr & 0x0100) | (data);
+            break;
+
+        case 0x0400: /* Control */
+            if(!msb) vce.ctrl = (data & 1);
+            break;
+    }
+}
+
+
+int vce_r(int address)
+{
+    int msb = (address & 1);
+
+    if((address & ~1) == 0x0404)
+    {
+        uint8 temp = vce.data[((vce.addr & 0x1FF) << 1) | (msb)];
+        if(msb) vce.addr += 1;
+        return (temp);
+    }
+
+    return (0xFF);
+}
diff --git a/MCUME_pico2/picopceold/vce.h b/MCUME_pico2/picopceold/vce.h
new file mode 100644
index 0000000..00e3ccf
--- /dev/null
+++ b/MCUME_pico2/picopceold/vce.h
@@ -0,0 +1,20 @@
+
+#ifndef _VCE_H_
+#define _VCE_H_
+
+/* Macros and defines */
+typedef struct
+{
+    uint8 ctrl;
+    uint8 data[0x400];
+    uint16 addr;
+}t_vce;
+
+/* Global data */
+extern t_vce vce;
+
+/* Function prototypes */
+void vce_w(int address, int data);
+int vce_r(int address);
+
+#endif /* _VCE_H_ */
diff --git a/MCUME_pico2/picopceold/vdc.c b/MCUME_pico2/picopceold/vdc.c
new file mode 100644
index 0000000..e520e57
--- /dev/null
+++ b/MCUME_pico2/picopceold/vdc.c
@@ -0,0 +1,271 @@
+
+#include "shared.h"
+
+#define LOG_DMA     0
+
+uint32 y_offset=0;
+uint32 byr=0;
+//uint8 vram[0x10000];
+//uint16 *vramw = (uint16 *)&vram[0];
+//uint8 objram[0x200];
+//uint16 *objramw = (uint16 *)&objram[0];
+uint16 reg[0x20];
+uint8 status;
+uint8 latch;
+uint8 addr_inc;
+uint8 vram_data_latch = 0;
+uint8 dvssr_trigger = 0;
+int playfield_shift = 6;
+uint32 playfield_col_mask = 0xFF;
+uint32 playfield_row_mask = 0x1F;
+int disp_width;
+int disp_height;
+uint32 disp_nt_width;
+int old_width = 0;
+int old_height = 0;
+int playfield_shift_table[] = {6, 7, 8, 8};
+int playfield_row_mask_table[] = {0x1F, 0x3F, 0x7F, 0x7F};
+
+
+//uint8 bg_name_dirty[0x800];
+//uint16 bg_name_list[0x800];
+uint16 bg_list_index;
+//uint8 * bg_pattern_cache;
+
+//uint16 obj_name_dirty[0x200];
+//uint16 obj_name_list[0x200];
+uint16 obj_list_index;
+//uint8 * obj_pattern_cache; 
+
+#define MARK_BG_DIRTY(addr)                                     \
+{                                                               \
+    int name = (addr >> 4) & 0x7FF;                             \
+    if(bg_name_dirty[name] == 0)                                \
+    {                                                           \
+        bg_name_list[bg_list_index] = name;                     \
+        bg_list_index += 1;                                     \
+    }                                                           \
+    bg_name_dirty[name] |= (1 << (addr & 0x07));                                 \
+}
+
+#define MARK_OBJ_DIRTY(addr)                                    \
+{                                                               \
+    int name = (addr >> 6) & 0x1FF;                             \
+    if(obj_name_dirty[name] == 0)                               \
+    {                                                           \
+        obj_name_list[obj_list_index] = name;                   \
+        obj_list_index += 1;                                    \
+    }                                                           \
+    obj_name_dirty[name] |= (1 << (addr & 0x0F));               \
+}
+
+
+
+/*--------------------------------------------------------------------------*/
+/* Memory handlers                                                          */
+/*--------------------------------------------------------------------------*/
+
+int vdc_r(int offset)
+{
+    uint8 temp;
+    uint8 msb = (offset & 1);
+
+    switch(offset)
+    {
+        case 0x0000: /* Register latch / status flags */
+            temp = status;
+            status = 0;
+            h6280_set_irq_line(0, CLEAR_LINE);
+            return (temp);
+
+        case 0x0002: /* Data port (LSB) */
+        case 0x0003: /* Data port (MSB) */
+            if(latch == 0x02)
+            {
+                temp = (vram[((reg[1] << 1) | (msb)) & 0xFFFF]);
+                if(msb) reg[1] += addr_inc;
+                return (temp);
+            }
+            break;
+    }
+
+    return (0xFF);
+}
+
+void vdc_w(int offset, int data)
+{
+    uint8 msb = (offset & 1);
+
+    switch(offset)
+    {
+        case 0x0000: /* Register latch / status flags */
+            latch = (data & 0x1F);
+            break;
+
+        case 0x0002: /* Data port (LSB) */
+        case 0x0003: /* Data port (MSB) */
+
+            if(msb)
+                reg[latch] = (reg[latch] & 0x00FF) | (data << 8);
+            else
+                reg[latch] = (reg[latch] & 0xFF00) | (data);
+
+            switch(latch)
+            {
+                case 0x02: 
+                    if(msb)
+                    {
+                        /* Form complete VRAM word */
+                        uint16 vram_word = (data << 8 | vram_data_latch);
+
+                        /* Check if data is new or not */
+                        if(vram_word != vramw[(reg[0] & 0x7FFF)])
+                        {
+                            /* Write data to VRAM */
+                            vramw[(reg[0] & 0x7FFF)] = vram_word;
+
+                            /* Mark pattern dirty tables */
+                            MARK_BG_DIRTY(reg[0]);
+                            MARK_OBJ_DIRTY(reg[0]);
+                        }
+
+                        reg[0] += addr_inc;
+                    }
+                    else
+                    {
+                        vram_data_latch = data;
+                    }
+                    break;
+
+                case 0x08:
+                    y_offset = byr = (reg[0x08] & 0x1FF);
+                    y_offset &= playfield_col_mask;
+                    break;
+
+                case 0x05:
+                    if(msb) {
+                        static uint8 add_tbl[] = {1, 32, 64, 128};
+                        addr_inc = add_tbl[(data >> 3) & 3];
+                    }
+                    break;
+
+                case 0x09:
+                    if(!msb) {
+                        playfield_shift = playfield_shift_table[(data >> 4) & 3];
+                        playfield_row_mask = playfield_row_mask_table[(data >> 4) & 3];
+                        playfield_col_mask = ((data >> 6) & 1) ? 0x01FF : 0x00FF;
+                    }
+                    break;
+
+                case 0x0B:
+                    disp_width = (1+(reg[0x0B] & 0x3F)) << 3;
+                    disp_nt_width = (disp_width >> 3);
+
+//                    if(disp_width != old_width) {
+//                        bitmap.viewport.ow = bitmap.viewport.w;
+//                        bitmap.viewport.w = old_width = disp_width;
+//                        bitmap.viewport.changed = 1;
+//                    }
+
+                    break;
+
+                case 0x0D:
+                    disp_height = 1+(reg[0x0D] & 0x01FF);
+
+//                    if(disp_height != old_height) {
+//                        bitmap.viewport.oh = bitmap.viewport.h;
+//                        bitmap.viewport.h = old_height = disp_height;
+//                        bitmap.viewport.changed = 1;
+//                    }
+                    break;
+
+                case 0x12:
+                    if(msb) vdc_do_dma();
+                    break;
+
+                case 0x13:
+                    if(msb) dvssr_trigger = 1;
+                    break;
+            }
+    }
+}
+
+/*--------------------------------------------------------------------------*/
+/* Init, reset, shutdown routines                                           */
+/*--------------------------------------------------------------------------*/
+
+int vdc_init(void)
+{
+    return (0);
+}
+
+void vdc_reset(void)
+{
+    memset(vram, 0, 0x10000);
+    memset(reg, 0, 0x20);
+    status = latch = 0;
+    addr_inc = 1;
+    dvssr_trigger = 0;
+
+    playfield_shift = 6;
+    playfield_row_mask = 0x1f;
+    playfield_col_mask = 0xff;
+
+    memset(bg_name_dirty, 0, 0x800);
+    memset(bg_name_list, 0, 0x800*2);
+    memset(bg_pattern_cache, 0, BG_CACHE_SIZE);
+    bg_list_index = 0;
+
+    memset(obj_name_dirty, 0, 0x200*2);
+    memset(obj_name_list, 0, 0x200*2);
+    memset(obj_pattern_cache, 0, OBJ_CACHE_SIZE);
+    obj_list_index = 0;
+}
+
+
+void vdc_shutdown(void)
+{
+}
+
+
+void vdc_do_dma(void)
+{
+    int did = (reg[0x0F] >> 3) & 1;
+    int sid = (reg[0x0F] >> 2) & 1;
+    int dvc = (reg[0x0F] >> 1) & 1;
+    int sour = (reg[0x10] & 0x7FFF);
+    int desr = (reg[0x11] & 0x7FFF);
+    int lenr = (reg[0x12] & 0x7FFF);
+
+#if LOG_DMA
+    error("DMA S:%04X%c D:%04X%c L:%04X\n", sour, (sid) ? '-' : '+', desr, (did) ? '-' : '+', lenr);
+#endif
+
+    /* Do VRAM -> VRAM transfer and update pattern caches */
+    do {
+        uint16 temp = vramw[(sour & 0x7FFF)];
+
+        if(temp != vramw[(desr & 0x7FFF)])
+        {
+            vramw[(desr & 0x7FFF)] = temp;
+            MARK_BG_DIRTY(desr);
+            MARK_OBJ_DIRTY(desr);
+        }
+
+        sour = (sid) ? (sour - 1) : (sour + 1);
+        desr = (did) ? (desr - 1) : (desr + 1);
+    } while (lenr--);
+
+    /* Set VRAM -> VRAM transfer completed flag */
+    status |= STATUS_DV;
+
+    /* Cause IRQ1 if enabled */
+    if(dvc)
+    {
+        h6280_set_irq_line(0, ASSERT_LINE);
+    }
+}
+
+
+/*--------------------------------------------------------------------------*/
+
diff --git a/MCUME_pico2/picopceold/vdc.h b/MCUME_pico2/picopceold/vdc.h
new file mode 100644
index 0000000..4216941
--- /dev/null
+++ b/MCUME_pico2/picopceold/vdc.h
@@ -0,0 +1,60 @@
+
+#ifndef _VDC_H_
+#define _VDC_H_
+
+/* Status register flags */
+#define STATUS_BSY      (0x40)  /* Memory access busy */
+#define STATUS_VD       (0x20)  /* Vertical blanking */
+#define STATUS_DV       (0x10)  /* VRAM -> VRAM DMA */
+#define STATUS_DS       (0x08)  /* VRAM -> SATB DMA */
+#define STATUS_RR       (0x04)  /* Line interrupt */
+#define STATUS_OR       (0x02)  /* Sprite overflow */
+#define STATUS_CR       (0x01)  /* Sprite collision */
+
+
+/* Global data */
+extern uint32 y_offset;
+extern uint32 byr;
+//extern uint8 vram[0x10000];
+//extern uint16 *vramw;
+//extern uint8 objram[0x200];
+//extern uint16 *objramw;
+extern uint16 reg[0x20];
+extern uint8 status;
+extern uint8 latch;
+extern uint8 addr_inc;
+extern uint8 vram_data_latch;
+extern uint8 dvssr_trigger;
+extern int playfield_shift;
+extern uint32 playfield_col_mask;
+extern uint32 playfield_row_mask;
+extern int disp_width;
+extern int disp_height;
+extern uint32 disp_nt_width;
+extern int old_width;
+extern int old_height;
+extern int playfield_shift_table[];
+extern int playfield_row_mask_table[];
+//extern uint8 bg_name_dirty[0x800];
+//extern uint16 bg_name_list[0x800];
+extern uint16 bg_list_index;
+//extern uint8 * bg_pattern_cache;
+//extern uint16 obj_name_dirty[0x200];
+//extern uint16 obj_name_list[0x200];
+extern uint16 obj_list_index;
+//extern uint8 * obj_pattern_cache;
+
+
+/* Function prototypes */
+int vdc_r(int offset);
+void vdc_w(int offset, int data);
+int vdc_init(void);
+void vdc_reset(void);
+void vdc_shutdown(void);
+void vdc_do_dma(void);
+void vdc_ctrl_w(int data);
+int vdc_ctrl_r(void);
+void vdc_data_w(int offset, int data);
+int vdc_data_r(int offset);
+
+#endif /* _VDC_H_ */
diff --git a/MCUME_pico2/picosms/.DS_Store b/MCUME_pico2/picosms/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/picosms/.DS_Store differ
diff --git a/MCUME_pico2/picosms/cpuintrf.h b/MCUME_pico2/picosms/cpuintrf.h
new file mode 100644
index 0000000..db20fd4
--- /dev/null
+++ b/MCUME_pico2/picosms/cpuintrf.h
@@ -0,0 +1,383 @@
+#ifndef CPUINTRF_H
+#define CPUINTRF_H
+
+
+/* The old system is obsolete and no longer supported by the core */
+#define NEW_INTERRUPT_SYSTEM    1
+
+#define MAX_IRQ_LINES   8       /* maximum number of IRQ lines per CPU */
+
+#define CLEAR_LINE		0		/* clear (a fired, held or pulsed) line */
+#define ASSERT_LINE     1       /* assert an interrupt immediately */
+#define HOLD_LINE       2       /* hold interrupt line until enable is true */
+#define PULSE_LINE		3		/* pulse interrupt line for one instruction */
+
+#define MAX_REGS		64		/* maximum number of register of any CPU */
+
+/* Values passed to the cpu_info function of a core to retrieve information */
+enum {
+	CPU_INFO_REG,
+	CPU_INFO_FLAGS=MAX_REGS,
+	CPU_INFO_NAME,
+    CPU_INFO_FAMILY,
+    CPU_INFO_VERSION,
+    CPU_INFO_FILE,
+    CPU_INFO_CREDITS,
+    CPU_INFO_REG_LAYOUT,
+	CPU_INFO_WIN_LAYOUT
+};
+
+#define CPU_IS_LE		0	/* emulated CPU is little endian */
+#define CPU_IS_BE		1	/* emulated CPU is big endian */
+
+/*
+ * This value is passed to cpu_get_reg to retrieve the previous
+ * program counter value, ie. before a CPU emulation started
+ * to fetch opcodes and arguments for the current instrution.
+ */
+#define REG_PREVIOUSPC	-1
+
+/*
+ * This value is passed to cpu_get_reg/cpu_set_reg, instead of one of
+ * the names from the enum a CPU core defines for it's registers,
+ * to get or set the contents of the memory pointed to by a stack pointer.
+ * You can specify the n'th element on the stack by (REG_SP_CONTENTS-n),
+ * ie. lower negative values. The actual element size (UINT16 or UINT32)
+ * depends on the CPU core.
+ * This is also used to replace the cpu_geturnpc() function.
+ */
+#define REG_SP_CONTENTS -2
+
+
+/* ASG 971222 -- added this generic structure */
+struct cpu_interface
+{
+    unsigned cpu_num;
+    void (*reset)(void *param);
+    void (*exit)(void);
+    int (*execute)(int cycles);
+    void (*burn)(int cycles);
+    unsigned (*get_context)(void *reg);
+    void (*set_context)(void *reg);
+    unsigned (*get_pc)(void);
+    void (*set_pc)(unsigned val);
+    unsigned (*get_sp)(void);
+    void (*set_sp)(unsigned val);
+    unsigned (*get_reg)(int regnum);
+    void (*set_reg)(int regnum, unsigned val);
+    void (*set_nmi_line)(int linestate);
+    void (*set_irq_line)(int irqline, int linestate);
+    void (*set_irq_callback)(int(*callback)(int irqline));
+    void (*internal_interrupt)(int type);
+    void (*cpu_state_save)(void *file);
+    void (*cpu_state_load)(void *file);
+    const char* (*cpu_info)(void *context,int regnum);
+    unsigned (*cpu_dasm)(char *buffer,unsigned pc);
+	unsigned num_irqs;
+	int default_vector;
+    int *icount;
+    double overclock;
+    int no_int, irq_int, nmi_int;
+    int (*memory_read)(int offset);
+    void (*memory_write)(int offset, int data);
+    void (*set_op_base)(int pc);
+	int address_shift;
+	unsigned address_bits, endianess, align_unit, max_inst_len;
+    unsigned abits1, abits2, abitsmin;
+};
+
+extern struct cpu_interface cpuintf[];
+
+void cpu_init(void);
+void cpu_run(void);
+
+/* optional watchdog */
+void watchdog_reset_w(int offset,int data);
+int watchdog_reset_r(int offset);
+/* Use this function to reset the machine */
+void machine_reset(void);
+/* Use this function to reset a single CPU */
+void cpu_set_reset_line(int cpu,int state);
+/* Use this function to halt a single CPU */
+void cpu_set_halt_line(int cpu,int state);
+
+/* This function returns CPUNUM current status (running or halted) */
+int cpu_getstatus(int cpunum);
+int cpu_gettotalcpu(void);
+int cpu_getactivecpu(void);
+void cpu_setactivecpu(int cpunum);
+
+/* Returns the current program counter */
+unsigned cpu_get_pc(void);
+/* Set the current program counter */
+void cpu_set_pc(unsigned val);
+
+/* Returns the current stack pointer */
+unsigned cpu_get_sp(void);
+/* Set the current stack pointer */
+void cpu_set_sp(unsigned val);
+
+/* Get the active CPUs context and return it's size */
+unsigned cpu_get_context(void *context);
+/* Set the active CPUs context */
+void cpu_set_context(void *context);
+
+/* Returns a specific register value (mamedbg) */
+unsigned cpu_get_reg(int regnum);
+/* Sets a specific register value (mamedbg) */
+void cpu_set_reg(int regnum, unsigned val);
+
+/* Returns previous pc (start of opcode causing read/write) */
+/* int cpu_getpreviouspc(void); */
+#define cpu_getpreviouspc() cpu_get_reg(REG_PREVIOUSPC)
+
+/* Returns the return address from the top of the stack (Z80 only) */
+/* int cpu_getreturnpc(void); */
+/* This can now be handled with a generic function */
+#define cpu_geturnpc() cpu_get_reg(REG_SP_CONTENTS)
+
+int cycles_currently_ran(void);
+int cycles_left_to_run(void);
+
+/* Returns the number of CPU cycles which take place in one video frame */
+int cpu_gettotalcycles(void);
+/* Returns the number of CPU cycles before the next interrupt handler call */
+int cpu_geticount(void);
+/* Returns the number of CPU cycles before the end of the current video frame */
+int cpu_getfcount(void);
+/* Returns the number of CPU cycles in one video frame */
+int cpu_getfperiod(void);
+/* Scales a given value by the ratio of fcount / fperiod */
+int cpu_scalebyfcount(int value);
+/* Returns the current scanline number */
+int cpu_getscanline(void);
+/* Returns the amount of time until a given scanline */
+double cpu_getscanlinetime(int scanline);
+/* Returns the duration of a single scanline */
+double cpu_getscanlineperiod(void);
+/* Returns the duration of a single scanline in cycles */
+int cpu_getscanlinecycles(void);
+/* Returns the number of cycles since the beginning of this frame */
+int cpu_getcurrentcycles(void);
+/* Returns the current horizontal beam position in pixels */
+int cpu_gethorzbeampos(void);
+/*
+  Returns the number of times the interrupt handler will be called before
+  the end of the current video frame. This is can be useful to interrupt
+  handlers to synchronize their operation. If you call this from outside
+  an interrupt handler, add 1 to the result, i.e. if it returns 0, it means
+  that the interrupt handler will be called once.
+*/
+int cpu_getiloops(void);
+
+/* Returns the current VBLANK state */
+int cpu_getvblank(void);
+
+/* Returns the number of the video frame we are currently playing */
+int cpu_getcurrentframe(void);
+
+
+/* generate a trigger after a specific period of time */
+void cpu_triggertime (double duration, int trigger);
+/* generate a trigger now */
+void cpu_trigger (int trigger);
+
+/* burn CPU cycles until a timer trigger */
+void cpu_spinuntil_trigger (int trigger);
+/* burn CPU cycles until the next interrupt */
+void cpu_spinuntil_int (void);
+/* burn CPU cycles until our timeslice is up */
+void cpu_spin (void);
+/* burn CPU cycles for a specific period of time */
+void cpu_spinuntil_time (double duration);
+
+/* yield our timeslice for a specific period of time */
+void cpu_yielduntil_trigger (int trigger);
+/* yield our timeslice until the next interrupt */
+void cpu_yielduntil_int (void);
+/* yield our current timeslice */
+void cpu_yield (void);
+/* yield our timeslice for a specific period of time */
+void cpu_yielduntil_time (double duration);
+
+/* set the NMI line state for a CPU, normally use PULSE_LINE */
+void cpu_set_nmi_line(int cpunum, int state);
+/* set the IRQ line state for a specific irq line of a CPU */
+/* normally use state HOLD_LINE, irqline 0 for first IRQ type of a cpu */
+void cpu_set_irq_line(int cpunum, int irqline, int state);
+/* this is to be called by CPU cores only! */
+void cpu_generate_internal_interrupt(int cpunum, int type);
+/* set the vector to be returned during a CPU's interrupt acknowledge cycle */
+void cpu_irq_line_vector_w(int cpunum, int irqline, int vector);
+
+/* use these in your write memory/port handles to set an IRQ vector */
+/* offset corresponds to the irq line number here */
+void cpu_0_irq_line_vector_w(int offset, int data);
+void cpu_1_irq_line_vector_w(int offset, int data);
+void cpu_2_irq_line_vector_w(int offset, int data);
+void cpu_3_irq_line_vector_w(int offset, int data);
+void cpu_4_irq_line_vector_w(int offset, int data);
+void cpu_5_irq_line_vector_w(int offset, int data);
+void cpu_6_irq_line_vector_w(int offset, int data);
+void cpu_7_irq_line_vector_w(int offset, int data);
+
+/* Obsolete functions: avoid to use them in new drivers if possible. */
+
+/* cause an interrupt on a CPU */
+void cpu_cause_interrupt(int cpu,int type);
+void cpu_clear_pending_interrupts(int cpu);
+void interrupt_enable_w(int offset,int data);
+void interrupt_vector_w(int offset,int data);
+int interrupt(void);
+int nmi_interrupt(void);
+int m68_level1_irq(void);
+int m68_level2_irq(void);
+int m68_level3_irq(void);
+int m68_level4_irq(void);
+int m68_level5_irq(void);
+int m68_level6_irq(void);
+int m68_level7_irq(void);
+int ignore_interrupt(void);
+
+/* CPU context access */
+void* cpu_getcontext (int _activecpu);
+int cpu_is_saving_context(int _activecpu);
+
+/***************************************************************************
+ * Get information for the currently active CPU
+ * cputype is a value from the CPU enum in driver.h
+ ***************************************************************************/
+/* Return number of address bits */
+unsigned cpu_address_bits(void);
+/* Return address mask */
+unsigned cpu_address_mask(void);
+/* Return address shift factor (TMS34010 bit addressing mode) */
+int cpu_address_shift(void);
+/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */
+unsigned cpu_endianess(void);
+/* Return opcode align unit (1 byte, 2 word, 4 dword) */
+unsigned cpu_align_unit(void);
+/* Return maximum instruction length */
+unsigned cpu_max_inst_len(void);
+
+/* Return name of the active CPU */
+const char *cpu_name(void);
+/* Return family name of the active CPU */
+const char *cpu_core_family(void);
+/* Return core version of the active CPU */
+const char *cpu_core_version(void);
+/* Return core filename of the active CPU */
+const char *cpu_core_file(void);
+/* Return credits info for of the active CPU */
+const char *cpu_core_credits(void);
+/* Return register layout definition for the active CPU */
+const char *cpu_reg_layout(void);
+/* Return (debugger) window layout definition for the active CPU */
+const char *cpu_win_layout(void);
+
+/* Disassemble an instruction at PC into the given buffer */
+unsigned cpu_dasm(char *buffer, unsigned pc);
+/* Return a string describing the currently set flag (status) bits of the active CPU */
+const char *cpu_flags(void);
+/* Return a string with a register name and hex value for the active CPU */
+/* regnum is a value defined in the CPU cores header files */
+const char *cpu_dump_reg(int regnum);
+/* Return a string describing the active CPUs current state */
+const char *cpu_dump_state(void);
+
+/***************************************************************************
+ * Get information for a specific CPU type
+ * cputype is a value from the CPU enum in driver.h
+ ***************************************************************************/
+/* Return address shift factor */
+/* TMS320C10 -1: word addressing mode, TMS34010 3: bit addressing mode */
+int cputype_address_shift(int cputype);
+/* Return number of address bits */
+unsigned cputype_address_bits(int cputype);
+/* Return address mask */
+unsigned cputype_address_mask(int cputype);
+/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */
+unsigned cputype_endianess(int cputype);
+/* Return opcode align unit (1 byte, 2 word, 4 dword) */
+unsigned cputype_align_unit(int cputype);
+/* Return maximum instruction length */
+unsigned cputype_max_inst_len(int cputype);
+
+/* Return name of the CPU */
+const char *cputype_name(int cputype);
+/* Return family name of the CPU */
+const char *cputype_core_family(int cputype);
+/* Return core version number of the CPU */
+const char *cputype_core_version(int cputype);
+/* Return core filename of the CPU */
+const char *cputype_core_file(int cputype);
+/* Return credits for the CPU core */
+const char *cputype_core_credits(int cputype);
+/* Return register layout definition for the CPU core */
+const char *cputype_reg_layout(int cputype);
+/* Return (debugger) window layout definition for the CPU core */
+const char *cputype_win_layout(int cputype);
+
+/***************************************************************************
+ * Get (or set) information for a numbered CPU of the running machine
+ * cpunum is a value between 0 and cpu_gettotalcpu() - 1
+ ***************************************************************************/
+/* Return number of address bits */
+unsigned cpunum_address_bits(int cputype);
+/* Return address mask */
+unsigned cpunum_address_mask(int cputype);
+/* Return endianess of the emulated CPU (CPU_LSB_FIRST or CPU_MSB_FIRST) */
+unsigned cpunum_endianess(int cputype);
+/* Return opcode align unit (1 byte, 2 word, 4 dword) */
+unsigned cpunum_align_unit(int cputype);
+/* Return maximum instruction length */
+unsigned cpunum_max_inst_len(int cputype);
+
+/* Get a register value for the specified CPU number of the running machine */
+unsigned cpunum_get_reg(int cpunum, int regnum);
+/* Set a register value for the specified CPU number of the running machine */
+void cpunum_set_reg(int cpunum, int regnum, unsigned val);
+
+/* Return (debugger) register layout definition for the CPU core */
+const char *cpunum_reg_layout(int cpunum);
+/* Return (debugger) window layout definition for the CPU core */
+const char *cpunum_win_layout(int cpunum);
+
+unsigned cpunum_dasm(int cpunum,char *buffer,unsigned pc);
+/* Return a string describing the currently set flag (status) bits of the CPU */
+const char *cpunum_flags(int cpunum);
+/* Return a string with a register name and value */
+/* regnum is a value defined in the CPU cores header files */
+const char *cpunum_dump_reg(int cpunum, int regnum);
+/* Return a string describing the CPUs current state */
+const char *cpunum_dump_state(int cpunum);
+/* Return a name for the specified cpu number */
+const char *cpunum_name(int cpunum);
+/* Return a family name for the specified cpu number */
+const char *cpunum_core_family(int cpunum);
+/* Return a version for the specified cpu number */
+const char *cpunum_core_version(int cpunum);
+/* Return a the source filename for the specified cpu number */
+const char *cpunum_core_file(int cpunum);
+/* Return a the credits for the specified cpu number */
+const char *cpunum_core_credits(int cpunum);
+
+/* Dump all of the running machines CPUs state to stderr */
+void cpu_dump_states(void);
+
+/* daisy-chain link */
+typedef struct {
+    void (*reset)(int);             /* reset callback     */
+    int  (*interrupt_entry)(int);   /* entry callback     */
+    void (*interrupt_reti)(int);    /* reti callback      */
+    int irq_param;                  /* callback paramater */
+}	Z80_DaisyChain;
+
+#define Z80_MAXDAISY	4		/* maximum of daisy chan device */
+
+#define Z80_INT_REQ     0x01    /* interrupt request mask       */
+#define Z80_INT_IEO     0x02    /* interrupt disable mask(IEO)  */
+
+#define Z80_VECTOR(device,state) (((device)<<8)|(state))
+
+#endif	/* CPUINTRF_H */
diff --git a/MCUME_pico2/picosms/emu.cpp b/MCUME_pico2/picosms/emu.cpp
new file mode 100644
index 0000000..ac54b06
--- /dev/null
+++ b/MCUME_pico2/picosms/emu.cpp
@@ -0,0 +1,169 @@
+#include <string.h>
+
+#include "emuapi.h"
+#include "iopins.h"
+
+extern "C" {
+#include "shared.h"
+}
+
+static int rom_offset = 0;
+
+#ifdef HAS_PSRAM
+
+#include "psram_t.h"
+
+PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO);
+
+extern "C" uint8 read_rom(int address) {
+  return (psram.psread(address+rom_offset));
+}
+
+extern "C" void  write_rom(int address, uint8 val)  {
+  psram.pswrite(address,val); 
+}
+#else
+#include "flash_t.h"
+
+extern "C" uint8 read_rom(int address) {
+  return flash_start[address+rom_offset];
+}
+
+#endif
+
+
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+
+void sms_Init(void)
+{
+  emu_printf("Allocating MEM");   
+#ifdef HAS_PSRAM
+  psram.begin();
+#endif
+  mem_init();    
+  emu_printf("Allocating MEM done");
+}
+
+
+static int hk = 0;
+static int k = 0;
+
+
+void sms_Input(int click) {
+
+  hk = emu_ReadI2CKeyboard();
+  k = emu_ReadKeys();   
+}
+
+
+
+void sms_Start(char * filename)
+{
+  emu_printf("load and init");  
+
+#ifdef HAS_PSRAM
+  int size = 0;
+  int pos = 0;
+  int n;
+  int i;
+  char * buf = (char*)cache;
+  int f = emu_FileOpen(filename,"r+b");
+  if (f) {
+    while ( (n = emu_FileRead(buf,CACHE_SIZE,f) ) ) {
+      size += n;
+      for (int i=0; i<n; i++) {
+        write_rom(pos++,buf[i]);
+      }
+      emu_printi(pos);            
+      //emu_printi(n);          
+    }
+    emu_FileClose(f);
+  }
+#else
+  int size = flash_load(filename);
+#endif
+
+
+
+  if((size / 512) & 1)
+  {
+    size -= 512;
+    rom_offset += 512;
+  }
+
+  cart.pages = (size / 0x4000);
+
+  int namelen = strlen(filename);    
+  emu_printf(&filename[namelen-4]);          
+  if (namelen > 4) {
+    if ( (!strcmp(&filename[namelen-4],".sms")) || (!strcmp(&filename[namelen-4],".SMS")) ) {
+      emu_printf("Master system");     
+      cart.type = TYPE_SMS;
+    }
+    else {
+      emu_printf("Game Gear");     
+      cart.type = TYPE_GG; 
+    }
+  }
+
+
+#ifdef HAS_SND
+#ifdef SOUND_PRESENT
+  system_init(22050);  
+  emu_sndInit();
+#else
+  system_init(0);
+#endif  
+#else
+  system_init(0);
+#endif
+  emu_printf("init done");
+}
+
+void sms_Step(void) 
+{
+  input.pad[0]=0;
+
+  if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) {
+    input.pad[0] |= INPUT_LEFT;
+  }
+  if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) {
+    input.pad[0] |= INPUT_RIGHT;
+  }
+  if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) {
+    input.pad[0] |= INPUT_UP;
+  }
+  if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) {
+    input.pad[0] |= INPUT_DOWN;
+  }  
+  if ( k & MASK_JOY2_BTN) {
+    input.pad[0] |= INPUT_BUTTON1; 
+  }
+
+  if (k & MASK_KEY_USER3)  {
+    input.pad[0] |= INPUT_BUTTON2;
+  }
+
+//    if(check_key(KEY_DEL))  input.system |= INPUT_HARD_RESET;
+//    if(check_key(KEY_TAB))  input.system |= (IS_GG) ? INPUT_HARD_RESET : INPUT_SOFT_RESET;
+  if (k & MASK_KEY_USER2)  input.system |= (IS_GG) ? INPUT_START : INPUT_PAUSE;
+  
+  sms_frame(0); 
+  //emu_printi(emu_FrameSkip());
+
+  emu_DrawVsync();    
+}
+
+void SND_Process(void *stream, int len) {
+#ifdef SOUND_PRESENT
+#ifdef HAS_SND
+//  audio_play_sample(stream, 0, len);
+#endif  
+#endif  
+} 
diff --git a/MCUME_pico2/picosms/emu.h b/MCUME_pico2/picosms/emu.h
new file mode 100644
index 0000000..c546f70
--- /dev/null
+++ b/MCUME_pico2/picosms/emu.h
@@ -0,0 +1,4 @@
+extern void sms_Init(void);
+extern void sms_Step(void);
+extern void sms_Start(char * filename);
+extern void sms_Input(int click);
diff --git a/MCUME_pico2/picosms/emucfg.h b/MCUME_pico2/picosms/emucfg.h
new file mode 100644
index 0000000..6228f4c
--- /dev/null
+++ b/MCUME_pico2/picosms/emucfg.h
@@ -0,0 +1,102 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         32
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                                        >
+#define TITLE "        Master System Emulator          "
+#define ROMSDIR "sms"
+
+#define emu_Init(ROM) {sms_Init(); sms_Start(ROM);}
+#define emu_Step() {sms_Step();}
+#define emu_Input(x) {sms_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,11,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,12,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234567890 "
+#define keylables_map1_1 (char *)"   #    *  "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  2,3,4,5,6,7,8,9,10,1,0,
+  0,0,0,11,0,0,0,0,12,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+/*
+const unsigned short key_map1[] = {
+  2,3,4, 
+  5,6,7, 
+  8,9,10, 
+  11,1,12};  
+*/
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picosms/fmopl.c b/MCUME_pico2/picosms/fmopl.c
new file mode 100644
index 0000000..72872a7
--- /dev/null
+++ b/MCUME_pico2/picosms/fmopl.c
@@ -0,0 +1,1319 @@
+/*
+**
+** File: fmopl.c -- software implementation of FM sound generator
+**
+** Copyright (C) 1999 Tatsuyuki Satoh , MultiArcadeMachineEmurator development
+**
+** Version 0.36f
+**
+*/
+
+#define BUILD_YM3812 1
+
+/*
+	preliminary :
+	Problem :
+	note:
+*/
+
+#include "shared.h"
+
+#ifndef PI
+#define PI 3.14159265358979323846
+#endif
+
+/* -------------------- preliminary define section --------------------- */
+/* attack/decay rate time rate */
+#define OPL_ARRATE     141280  /* RATE 4 =  2826.24ms @ 3.6MHz */
+#define OPL_DRRATE    1956000  /* RATE 4 = 39280.64ms @ 3.6MHz */
+
+#define DELTAT_MIXING_LEVEL (1) /* DELTA-T ADPCM MIXING LEVEL */
+
+#define FREQ_BITS 24			/* frequency turn          */
+
+/* counter bits = 20 , octerve 7 */
+#define FREQ_RATE   (1<<(FREQ_BITS-20))
+#define TL_BITS    (FREQ_BITS+2)
+
+/* final output shift , limit minimum and maximum */
+#define OPL_OUTSB   (TL_BITS+3-16)		/* OPL output final shift 16bit */
+#define OPL_MAXOUT (0x7fff<<OPL_OUTSB)
+#define OPL_MINOUT (-0x8000<<OPL_OUTSB)
+
+/* -------------------- quality selection --------------------- */
+
+/* sinwave entries */
+/* used static memory = SIN_ENT * 4 (byte) */
+#define SIN_ENT 2048
+
+/* output level entries (envelope,sinwave) */
+/* envelope counter lower bits */
+#define ENV_BITS 16
+/* envelope output entries */
+#define EG_ENT   4096
+/* used dynamic memory = EG_ENT*4*4(byte)or EG_ENT*6*4(byte) */
+/* used static  memory = EG_ENT*4 (byte)                     */
+
+#define EG_OFF   ((2*EG_ENT)<<ENV_BITS)  /* OFF          */
+#define EG_DED   EG_OFF
+#define EG_DST   (EG_ENT<<ENV_BITS)      /* DECAY  START */
+#define EG_AED   EG_DST
+#define EG_AST   0                       /* ATTACK START */
+
+#define EG_STEP (96.0/EG_ENT) /* OPL is 0.1875 dB step  */
+
+/* LFO table entries */
+#define VIB_ENT 512
+#define VIB_SHIFT (32-9)
+#define AMS_ENT 512
+#define AMS_SHIFT (32-9)
+
+#define VIB_RATE 256
+
+/* -------------------- local defines , macros --------------------- */
+
+/* register number to channel number , slot offset */
+#define SLOT1 0
+#define SLOT2 1
+
+/* envelope phase */
+#define ENV_MOD_RR  0x00
+#define ENV_MOD_DR  0x01
+#define ENV_MOD_AR  0x02
+
+/* -------------------- tables --------------------- */
+static const int slot_array[32]=
+{
+	 0, 2, 4, 1, 3, 5,-1,-1,
+	 6, 8,10, 7, 9,11,-1,-1,
+	12,14,16,13,15,17,-1,-1,
+	-1,-1,-1,-1,-1,-1,-1,-1
+};
+
+/* key scale level */
+#define ML (0.1875*2/EG_STEP)
+static const UINT32 KSL_TABLE[8*16]=
+{
+	/* OCT 0 */
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	/* OCT 1 */
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 0.750*ML, 1.125*ML, 1.500*ML,
+	 1.875*ML, 2.250*ML, 2.625*ML, 3.000*ML,
+	/* OCT 2 */
+	 0.000*ML, 0.000*ML, 0.000*ML, 0.000*ML,
+	 0.000*ML, 1.125*ML, 1.875*ML, 2.625*ML,
+	 3.000*ML, 3.750*ML, 4.125*ML, 4.500*ML,
+	 4.875*ML, 5.250*ML, 5.625*ML, 6.000*ML,
+	/* OCT 3 */
+	 0.000*ML, 0.000*ML, 0.000*ML, 1.875*ML,
+	 3.000*ML, 4.125*ML, 4.875*ML, 5.625*ML,
+	 6.000*ML, 6.750*ML, 7.125*ML, 7.500*ML,
+	 7.875*ML, 8.250*ML, 8.625*ML, 9.000*ML,
+	/* OCT 4 */
+	 0.000*ML, 0.000*ML, 3.000*ML, 4.875*ML,
+	 6.000*ML, 7.125*ML, 7.875*ML, 8.625*ML,
+	 9.000*ML, 9.750*ML,10.125*ML,10.500*ML,
+	10.875*ML,11.250*ML,11.625*ML,12.000*ML,
+	/* OCT 5 */
+	 0.000*ML, 3.000*ML, 6.000*ML, 7.875*ML,
+	 9.000*ML,10.125*ML,10.875*ML,11.625*ML,
+	12.000*ML,12.750*ML,13.125*ML,13.500*ML,
+	13.875*ML,14.250*ML,14.625*ML,15.000*ML,
+	/* OCT 6 */
+	 0.000*ML, 6.000*ML, 9.000*ML,10.875*ML,
+	12.000*ML,13.125*ML,13.875*ML,14.625*ML,
+	15.000*ML,15.750*ML,16.125*ML,16.500*ML,
+	16.875*ML,17.250*ML,17.625*ML,18.000*ML,
+	/* OCT 7 */
+	 0.000*ML, 9.000*ML,12.000*ML,13.875*ML,
+	15.000*ML,16.125*ML,16.875*ML,17.625*ML,
+	18.000*ML,18.750*ML,19.125*ML,19.500*ML,
+	19.875*ML,20.250*ML,20.625*ML,21.000*ML
+};
+#undef ML
+
+/* sustain lebel table (3db per step) */
+/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
+#define SC(db) (db*((3/EG_STEP)*(1<<ENV_BITS)))+EG_DST
+static const INT32 SL_TABLE[16]={
+ SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
+ SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
+};
+#undef SC
+
+#define TL_MAX (EG_ENT*2) /* limit(tl + ksr + envelope) + sinwave */
+/* TotalLevel : 48 24 12  6  3 1.5 0.75 (dB) */
+/* TL_TABLE[ 0      to TL_MAX          ] : plus  section */
+/* TL_TABLE[ TL_MAX to TL_MAX+TL_MAX-1 ] : minus section */
+static INT32 *TL_TABLE;
+
+/* pointers to TL_TABLE with sinwave output offset */
+static INT32 **SIN_TABLE;
+
+/* LFO table */
+static INT32 *AMS_TABLE;
+static INT32 *VIB_TABLE;
+
+/* envelope output curve table */
+/* attack + decay + OFF */
+static INT32 ENV_CURVE[2*EG_ENT+1];
+
+/* multiple table */
+#define ML 2
+static const UINT32 MUL_TABLE[16]= {
+/* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15 */
+   0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
+   8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
+};
+#undef ML
+
+/* dummy attack / decay rate ( when rate == 0 ) */
+static INT32 RATE_0[16]=
+{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+/* -------------------- static state --------------------- */
+
+/* lock level of common table */
+static int num_lock = 0;
+
+/* work table */
+static void *cur_chip = NULL;	/* current chip point */
+/* currenct chip state */
+/* static FMSAMPLE  *bufL,*bufR; */
+static OPL_CH *S_CH;
+static OPL_CH *E_CH;
+OPL_SLOT *SLOT7_1,*SLOT7_2,*SLOT8_1,*SLOT8_2;
+
+static INT32 outd[1];
+static INT32 ams;
+static INT32 vib;
+INT32  *ams_table;
+INT32  *vib_table;
+static INT32 amsIncr;
+static INT32 vibIncr;
+static INT32 feedback2;		/* connect for SLOT 2 */
+
+/* log output level */
+#define LOG_ERR  3      /* ERROR       */
+#define LOG_WAR  2      /* WARNING     */
+#define LOG_INF  1      /* INFORMATION */
+
+#define LOG_LEVEL LOG_INF
+
+static void Log(int level,char *format,...)
+{
+}
+
+/* --------------------- subroutines  --------------------- */
+
+static __inline__ int Limit( int val, int max, int min ) {
+	if ( val > max )
+		val = max;
+	else if ( val < min )
+		val = min;
+
+	return val;
+}
+
+/* status set and IRQ handling */
+static __inline__ void OPL_STATUS_SET(FM_OPL *OPL,int flag)
+{
+	/* set status flag */
+	OPL->status |= flag;
+	if(!(OPL->status & 0x80))
+	{
+		if(OPL->status & OPL->statusmask)
+		{	/* IRQ on */
+			OPL->status |= 0x80;
+			/* callback user interrupt handler (IRQ is OFF to ON) */
+			if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,1);
+		}
+	}
+}
+
+/* status reset and IRQ handling */
+static __inline__ void OPL_STATUS_RESET(FM_OPL *OPL,int flag)
+{
+	/* reset status flag */
+	OPL->status &=~flag;
+	if((OPL->status & 0x80))
+	{
+		if (!(OPL->status & OPL->statusmask) )
+		{
+			OPL->status &= 0x7f;
+			/* callback user interrupt handler (IRQ is ON to OFF) */
+			if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,0);
+		}
+	}
+}
+
+/* IRQ mask set */
+static __inline__ void OPL_STATUSMASK_SET(FM_OPL *OPL,int flag)
+{
+	OPL->statusmask = flag;
+	/* IRQ handling check */
+	OPL_STATUS_SET(OPL,0);
+	OPL_STATUS_RESET(OPL,0);
+}
+
+/* ----- key on  ----- */
+static __inline__ void OPL_KEYON(OPL_SLOT *SLOT)
+{
+	/* sin wave restart */
+	SLOT->Cnt = 0;
+	/* set attack */
+	SLOT->evm = ENV_MOD_AR;
+	SLOT->evs = SLOT->evsa;
+	SLOT->evc = EG_AST;
+	SLOT->eve = EG_AED;
+}
+/* ----- key off ----- */
+static __inline__ void OPL_KEYOFF(OPL_SLOT *SLOT)
+{
+	if( SLOT->evm > ENV_MOD_RR)
+	{
+		/* set envelope counter from envleope output */
+		SLOT->evm = ENV_MOD_RR;
+		if( !(SLOT->evc&EG_DST) )
+			/*SLOT->evc = (ENV_CURVE[SLOT->evc>>ENV_BITS]<<ENV_BITS) + EG_DST; */
+			SLOT->evc = EG_DST;
+		SLOT->eve = EG_DED;
+		SLOT->evs = SLOT->evsr;
+	}
+}
+
+/* ---------- calcrate Envelope Generator & Phase Generator ---------- */
+/* return : envelope output */
+static __inline__ UINT32 OPL_CALC_SLOT( OPL_SLOT *SLOT )
+{
+	/* calcrate envelope generator */
+	if( (SLOT->evc+=SLOT->evs) >= SLOT->eve )
+	{
+		switch( SLOT->evm ){
+		case ENV_MOD_AR: /* ATTACK -> DECAY1 */
+			/* next DR */
+			SLOT->evm = ENV_MOD_DR;
+			SLOT->evc = EG_DST;
+			SLOT->eve = SLOT->SL;
+			SLOT->evs = SLOT->evsd;
+			break;
+		case ENV_MOD_DR: /* DECAY -> SL or RR */
+			SLOT->evc = SLOT->SL;
+			SLOT->eve = EG_DED;
+			if(SLOT->eg_typ)
+			{
+				SLOT->evs = 0;
+			}
+			else
+			{
+				SLOT->evm = ENV_MOD_RR;
+				SLOT->evs = SLOT->evsr;
+			}
+			break;
+		case ENV_MOD_RR: /* RR -> OFF */
+			SLOT->evc = EG_OFF;
+			SLOT->eve = EG_OFF+1;
+			SLOT->evs = 0;
+			break;
+		}
+	}
+	/* calcrate envelope */
+	return SLOT->TLL+ENV_CURVE[SLOT->evc>>ENV_BITS]+(SLOT->ams ? ams : 0);
+}
+
+/* set algorythm connection */
+static void set_algorythm( OPL_CH *CH)
+{
+	INT32 *carrier = &outd[0];
+	CH->connect1 = CH->CON ? carrier : &feedback2;
+	CH->connect2 = carrier;
+}
+
+/* ---------- frequency counter for operater update ---------- */
+static __inline__ void CALC_FCSLOT(OPL_CH *CH,OPL_SLOT *SLOT)
+{
+	int ksr;
+
+	/* frequency step counter */
+	SLOT->Incr = CH->fc * SLOT->mul;
+	ksr = CH->kcode >> SLOT->KSR;
+
+	if( SLOT->ksr != ksr )
+	{
+		SLOT->ksr = ksr;
+		/* attack , decay rate recalcration */
+		SLOT->evsa = SLOT->AR[ksr];
+		SLOT->evsd = SLOT->DR[ksr];
+		SLOT->evsr = SLOT->RR[ksr];
+	}
+	SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
+}
+
+/* set multi,am,vib,EG-TYP,KSR,mul */
+static __inline__ void set_mul(FM_OPL *OPL,int slot,int v)
+{
+	OPL_CH   *CH   = &OPL->P_CH[slot/2];
+	OPL_SLOT *SLOT = &CH->SLOT[slot&1];
+
+	SLOT->mul    = MUL_TABLE[v&0x0f];
+	SLOT->KSR    = (v&0x10) ? 0 : 2;
+	SLOT->eg_typ = (v&0x20)>>5;
+	SLOT->vib    = (v&0x40);
+	SLOT->ams    = (v&0x80);
+	CALC_FCSLOT(CH,SLOT);
+}
+
+/* set ksl & tl */
+static __inline__ void set_ksl_tl(FM_OPL *OPL,int slot,int v)
+{
+	OPL_CH   *CH   = &OPL->P_CH[slot/2];
+	OPL_SLOT *SLOT = &CH->SLOT[slot&1];
+	int ksl = v>>6; /* 0 / 1.5 / 3 / 6 db/OCT */
+
+	SLOT->ksl = ksl ? 3-ksl : 31;
+	SLOT->TL  = (v&0x3f)*(0.75/EG_STEP); /* 0.75db step */
+
+	if( !(OPL->mode&0x80) )
+	{	/* not CSM latch total level */
+		SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
+	}
+}
+
+/* set attack rate & decay rate  */
+static __inline__ void set_ar_dr(FM_OPL *OPL,int slot,int v)
+{
+	OPL_CH   *CH   = &OPL->P_CH[slot/2];
+	OPL_SLOT *SLOT = &CH->SLOT[slot&1];
+	int ar = v>>4;
+	int dr = v&0x0f;
+
+	SLOT->AR = ar ? &OPL->AR_TABLE[ar<<2] : RATE_0;
+	SLOT->evsa = SLOT->AR[SLOT->ksr];
+	if( SLOT->evm == ENV_MOD_AR ) SLOT->evs = SLOT->evsa;
+
+	SLOT->DR = dr ? &OPL->DR_TABLE[dr<<2] : RATE_0;
+	SLOT->evsd = SLOT->DR[SLOT->ksr];
+	if( SLOT->evm == ENV_MOD_DR ) SLOT->evs = SLOT->evsd;
+}
+
+/* set sustain level & release rate */
+static __inline__ void set_sl_rr(FM_OPL *OPL,int slot,int v)
+{
+	OPL_CH   *CH   = &OPL->P_CH[slot/2];
+	OPL_SLOT *SLOT = &CH->SLOT[slot&1];
+	int sl = v>>4;
+	int rr = v & 0x0f;
+
+	SLOT->SL = SL_TABLE[sl];
+	if( SLOT->evm == ENV_MOD_DR ) SLOT->eve = SLOT->SL;
+	SLOT->RR = &OPL->DR_TABLE[rr<<2];
+	SLOT->evsr = SLOT->RR[SLOT->ksr];
+	if( SLOT->evm == ENV_MOD_RR ) SLOT->evs = SLOT->evsr;
+}
+
+/* operator output calcrator */
+#define OP_OUT(slot,env,con)   slot->wavetable[((slot->Cnt+con)/(0x1000000/SIN_ENT))&(SIN_ENT-1)][env]
+/* ---------- calcrate one of channel ---------- */
+static __inline__ void OPL_CALC_CH( OPL_CH *CH )
+{
+	UINT32 env_out;
+	OPL_SLOT *SLOT;
+
+	feedback2 = 0;
+	/* SLOT 1 */
+	SLOT = &CH->SLOT[SLOT1];
+	env_out=OPL_CALC_SLOT(SLOT);
+	if( env_out < EG_ENT-1 )
+	{
+		/* PG */
+		if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE);
+		else          SLOT->Cnt += SLOT->Incr;
+		/* connectoion */
+		if(CH->FB)
+		{
+			int feedback1 = (CH->op1_out[0]+CH->op1_out[1])>>CH->FB;
+			CH->op1_out[1] = CH->op1_out[0];
+			*CH->connect1 += CH->op1_out[0] = OP_OUT(SLOT,env_out,feedback1);
+		}
+		else
+		{
+			*CH->connect1 += OP_OUT(SLOT,env_out,0);
+		}
+	}else
+	{
+		CH->op1_out[1] = CH->op1_out[0];
+		CH->op1_out[0] = 0;
+	}
+	/* SLOT 2 */
+	SLOT = &CH->SLOT[SLOT2];
+	env_out=OPL_CALC_SLOT(SLOT);
+	if( env_out < EG_ENT-1 )
+	{
+		/* PG */
+		if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE);
+		else          SLOT->Cnt += SLOT->Incr;
+		/* connectoion */
+		outd[0] += OP_OUT(SLOT,env_out, feedback2);
+	}
+}
+
+/* ---------- calcrate rythm block ---------- */
+#define WHITE_NOISE_db 6.0
+static __inline__ void OPL_CALC_RH( OPL_CH *CH )
+{
+	UINT32 env_tam,env_sd,env_top,env_hh;
+	int whitenoise = (rand()&1)*(WHITE_NOISE_db/EG_STEP);
+	INT32 tone8;
+
+	OPL_SLOT *SLOT;
+	int env_out;
+
+	/* BD : same as FM serial mode and output level is large */
+	feedback2 = 0;
+	/* SLOT 1 */
+	SLOT = &CH[6].SLOT[SLOT1];
+	env_out=OPL_CALC_SLOT(SLOT);
+	if( env_out < EG_ENT-1 )
+	{
+		/* PG */
+		if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE);
+		else          SLOT->Cnt += SLOT->Incr;
+		/* connectoion */
+		if(CH[6].FB)
+		{
+			int feedback1 = (CH[6].op1_out[0]+CH[6].op1_out[1])>>CH[6].FB;
+			CH[6].op1_out[1] = CH[6].op1_out[0];
+			feedback2 = CH[6].op1_out[0] = OP_OUT(SLOT,env_out,feedback1);
+		}
+		else
+		{
+			feedback2 = OP_OUT(SLOT,env_out,0);
+		}
+	}else
+	{
+		feedback2 = 0;
+		CH[6].op1_out[1] = CH[6].op1_out[0];
+		CH[6].op1_out[0] = 0;
+	}
+	/* SLOT 2 */
+	SLOT = &CH[6].SLOT[SLOT2];
+	env_out=OPL_CALC_SLOT(SLOT);
+	if( env_out < EG_ENT-1 )
+	{
+		/* PG */
+		if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE);
+		else          SLOT->Cnt += SLOT->Incr;
+		/* connectoion */
+		outd[0] += OP_OUT(SLOT,env_out, feedback2)*2;
+	}
+    /* 
+	 SD  (17) = mul14[fnum7] + white noise
+	 TAM (15) = mul15[fnum8]
+	 TOP (18) = fnum6(mul18[fnum8]+whitenoise)
+	 HH  (14) = fnum7(mul18[fnum8]+whitenoise) + white noise
+	*/
+	env_sd =OPL_CALC_SLOT(SLOT7_2) + whitenoise;
+	env_tam=OPL_CALC_SLOT(SLOT8_1);
+	env_top=OPL_CALC_SLOT(SLOT8_2);
+	env_hh =OPL_CALC_SLOT(SLOT7_1) + whitenoise;
+
+	/* PG */
+	if(SLOT7_1->vib) SLOT7_1->Cnt += (2*SLOT7_1->Incr*vib/VIB_RATE);
+	else             SLOT7_1->Cnt += 2*SLOT7_1->Incr;
+	if(SLOT7_2->vib) SLOT7_2->Cnt += ((CH[7].fc*8)*vib/VIB_RATE);
+	else             SLOT7_2->Cnt += (CH[7].fc*8);
+	if(SLOT8_1->vib) SLOT8_1->Cnt += (SLOT8_1->Incr*vib/VIB_RATE);
+	else             SLOT8_1->Cnt += SLOT8_1->Incr;
+	if(SLOT8_2->vib) SLOT8_2->Cnt += ((CH[8].fc*48)*vib/VIB_RATE);
+	else             SLOT8_2->Cnt += (CH[8].fc*48);
+
+	tone8 = OP_OUT(SLOT8_2,whitenoise,0 );
+
+	/* SD */
+	if( env_sd < EG_ENT-1 )
+		outd[0] += OP_OUT(SLOT7_1,env_sd, 0)*8;
+	/* TAM */
+	if( env_tam < EG_ENT-1 )
+		outd[0] += OP_OUT(SLOT8_1,env_tam, 0)*2;
+	/* TOP-CY */
+	if( env_top < EG_ENT-1 )
+		outd[0] += OP_OUT(SLOT7_2,env_top,tone8)*2;
+	/* HH */
+	if( env_hh  < EG_ENT-1 )
+		outd[0] += OP_OUT(SLOT7_2,env_hh,tone8)*2;
+}
+
+/* ----------- initialize time tabls ----------- */
+static void init_timetables( FM_OPL *OPL , int ARRATE , int DRRATE )
+{
+	int i;
+	double rate;
+
+	/* make attack rate & decay rate tables */
+	for (i = 0;i < 4;i++) OPL->AR_TABLE[i] = OPL->DR_TABLE[i] = 0;
+	for (i = 4;i <= 60;i++){
+		rate  = OPL->freqbase;						/* frequency rate */
+		if( i < 60 ) rate *= 1.0+(i&3)*0.25;		/* b0-1 : x1 , x1.25 , x1.5 , x1.75 */
+		rate *= 1<<((i>>2)-1);						/* b2-5 : shift bit */
+		rate *= (double)(EG_ENT<<ENV_BITS);
+		OPL->AR_TABLE[i] = rate / ARRATE;
+		OPL->DR_TABLE[i] = rate / DRRATE;
+	}
+	for (i = 60;i < 76;i++)
+	{
+		OPL->AR_TABLE[i] = EG_AED-1;
+		OPL->DR_TABLE[i] = OPL->DR_TABLE[60];
+	}
+#if 0
+	for (i = 0;i < 64 ;i++){	/* make for overflow area */
+		Log(LOG_WAR,"rate %2d , ar %f ms , dr %f ms \n",i,
+			((double)(EG_ENT<<ENV_BITS) / OPL->AR_TABLE[i]) * (1000.0 / OPL->rate),
+			((double)(EG_ENT<<ENV_BITS) / OPL->DR_TABLE[i]) * (1000.0 / OPL->rate) );
+	}
+#endif
+}
+
+/* ---------- generic table initialize ---------- */
+static int OPLOpenTable( void )
+{
+	int s,t;
+	double rate;
+	int i,j;
+	double pom;
+
+	/* allocate dynamic tables */
+	if( (TL_TABLE = emu_Malloc(TL_MAX*2*sizeof(INT32))) == NULL)
+		return 0;
+	if( (SIN_TABLE = emu_Malloc(SIN_ENT*4 *sizeof(INT32 *))) == NULL)
+	{
+		emu_Free(TL_TABLE);
+		return 0;
+	}
+	if( (AMS_TABLE = emu_Malloc(AMS_ENT*2 *sizeof(INT32))) == NULL)
+	{
+		emu_Free(TL_TABLE);
+		emu_Free(SIN_TABLE);
+		return 0;
+	}
+	if( (VIB_TABLE = emu_Malloc(VIB_ENT*2 *sizeof(INT32))) == NULL)
+	{
+		emu_Free(TL_TABLE);
+		emu_Free(SIN_TABLE);
+		emu_Free(AMS_TABLE);
+		return 0;
+	}
+
+	/* make total level table */
+	for (t = 0;t < EG_ENT-1 ;t++){
+		rate = ((1<<TL_BITS)-1)/pow(10,EG_STEP*t/20);	/* dB -> voltage */
+		TL_TABLE[       t] =  (int)rate;
+		TL_TABLE[TL_MAX+t] = -TL_TABLE[t];
+/*		Log(LOG_INF,"TotalLevel(%3d) = %x\n",t,TL_TABLE[t]);*/
+	}
+	/* fill volume off area */
+	for ( t = EG_ENT-1; t < TL_MAX ;t++){
+		TL_TABLE[t] = TL_TABLE[TL_MAX+t] = 0;
+	}
+
+	/* make sinwave table (total level offet) */
+	/* degree 0 = degree 180                   = off */
+	SIN_TABLE[0] = SIN_TABLE[SIN_ENT/2]         = &TL_TABLE[EG_ENT-1];
+	for (s = 1;s <= SIN_ENT/4;s++){
+		pom = sin(2*PI*s/SIN_ENT); /* sin     */
+		pom = 20*log10(1/pom);	   /* decibel */
+		j = pom / EG_STEP;         /* TL_TABLE steps */
+
+        /* degree 0   -  90    , degree 180 -  90 : plus section */
+		SIN_TABLE[          s] = SIN_TABLE[SIN_ENT/2-s] = &TL_TABLE[j];
+        /* degree 180 - 270    , degree 360 - 270 : minus section */
+		SIN_TABLE[SIN_ENT/2+s] = SIN_TABLE[SIN_ENT  -s] = &TL_TABLE[TL_MAX+j];
+/*		Log(LOG_INF,"sin(%3d) = %f:%f db\n",s,pom,(double)j * EG_STEP);*/
+	}
+	for (s = 0;s < SIN_ENT;s++)
+	{
+		SIN_TABLE[SIN_ENT*1+s] = s<(SIN_ENT/2) ? SIN_TABLE[s] : &TL_TABLE[EG_ENT];
+		SIN_TABLE[SIN_ENT*2+s] = SIN_TABLE[s % (SIN_ENT/2)];
+		SIN_TABLE[SIN_ENT*3+s] = (s/(SIN_ENT/4))&1 ? &TL_TABLE[EG_ENT] : SIN_TABLE[SIN_ENT*2+s];
+	}
+
+	/* envelope counter -> envelope output table */
+	for (i=0; i<EG_ENT; i++)
+	{
+		/* ATTACK curve */
+		pom = pow( ((double)(EG_ENT-1-i)/EG_ENT) , 8 ) * EG_ENT;
+		/* if( pom >= EG_ENT ) pom = EG_ENT-1; */
+		ENV_CURVE[i] = (int)pom;
+		/* DECAY ,RELEASE curve */
+		ENV_CURVE[(EG_DST>>ENV_BITS)+i]= i;
+	}
+	/* off */
+	ENV_CURVE[EG_OFF>>ENV_BITS]= EG_ENT-1;
+	/* make LFO ams table */
+	for (i=0; i<AMS_ENT; i++)
+	{
+		pom = (1.0+sin(2*PI*i/AMS_ENT))/2; /* sin */
+		AMS_TABLE[i]         = (1.0/EG_STEP)*pom; /* 1dB   */
+		AMS_TABLE[AMS_ENT+i] = (4.8/EG_STEP)*pom; /* 4.8dB */
+	}
+	/* make LFO vibrate table */
+	for (i=0; i<VIB_ENT; i++)
+	{
+		/* 100cent = 1seminote = 6% ?? */
+		pom = (double)VIB_RATE*0.06*sin(2*PI*i/VIB_ENT); /* +-100sect step */
+		VIB_TABLE[i]         = VIB_RATE + (pom*0.07); /* +- 7cent */
+		VIB_TABLE[VIB_ENT+i] = VIB_RATE + (pom*0.14); /* +-14cent */
+		/* Log(LOG_INF,"vib %d=%d\n",i,VIB_TABLE[VIB_ENT+i]); */
+	}
+	return 1;
+}
+
+
+static void OPLCloseTable( void )
+{
+	emu_Free(TL_TABLE);
+	emu_Free(SIN_TABLE);
+	emu_Free(AMS_TABLE);
+	emu_Free(VIB_TABLE);
+}
+
+/* CSM Key Controll */
+static __inline__ void CSMKeyControll(OPL_CH *CH)
+{
+	OPL_SLOT *slot1 = &CH->SLOT[SLOT1];
+	OPL_SLOT *slot2 = &CH->SLOT[SLOT2];
+	/* all key off */
+	OPL_KEYOFF(slot1);
+	OPL_KEYOFF(slot2);
+	/* total level latch */
+	slot1->TLL = slot1->TL + (CH->ksl_base>>slot1->ksl);
+	slot1->TLL = slot1->TL + (CH->ksl_base>>slot1->ksl);
+	/* key on */
+	CH->op1_out[0] = CH->op1_out[1] = 0;
+	OPL_KEYON(slot1);
+	OPL_KEYON(slot2);
+}
+
+/* ---------- opl initialize ---------- */
+static void OPL_initalize(FM_OPL *OPL)
+{
+	int fn;
+
+	/* frequency base */
+	OPL->freqbase = (OPL->rate) ? ((double)OPL->clock / OPL->rate) / 72  : 0;
+	/* Timer base time */
+	OPL->TimerBase = 1.0/((double)OPL->clock / 72.0 );
+	/* make time tables */
+	init_timetables( OPL , OPL_ARRATE , OPL_DRRATE );
+	/* make fnumber -> increment counter table */
+	for( fn=0 ; fn < 1024 ; fn++ )
+	{
+		OPL->FN_TABLE[fn] = OPL->freqbase * fn * FREQ_RATE * (1<<7) / 2;
+	}
+	/* LFO freq.table */
+	OPL->amsIncr = OPL->rate ? (double)AMS_ENT*(1<<AMS_SHIFT) / OPL->rate * 3.7 * ((double)OPL->clock/3600000) : 0;
+	OPL->vibIncr = OPL->rate ? (double)VIB_ENT*(1<<VIB_SHIFT) / OPL->rate * 6.4 * ((double)OPL->clock/3600000) : 0;
+}
+
+/* ---------- write a OPL registers ---------- */
+void OPLWriteReg(FM_OPL *OPL, int r, int v)
+{
+	OPL_CH *CH;
+	int slot;
+	int block_fnum;
+
+	switch(r&0xe0)
+	{
+	case 0x00: /* 00-1f:controll */
+		switch(r&0x1f)
+		{
+		case 0x01:
+			/* wave selector enable */
+			if(OPL->type&OPL_TYPE_WAVESEL)
+			{
+				OPL->wavesel = v&0x20;
+				if(!OPL->wavesel)
+				{
+					/* preset compatible mode */
+					int c;
+					for(c=0;c<OPL->max_ch;c++)
+					{
+						OPL->P_CH[c].SLOT[SLOT1].wavetable = &SIN_TABLE[0];
+						OPL->P_CH[c].SLOT[SLOT2].wavetable = &SIN_TABLE[0];
+					}
+				}
+			}
+			return;
+		case 0x02:	/* Timer 1 */
+			OPL->T[0] = (256-v)*4;
+			break;
+		case 0x03:	/* Timer 2 */
+			OPL->T[1] = (256-v)*16;
+			return;
+		case 0x04:	/* IRQ clear / mask and Timer enable */
+			if(v&0x80)
+			{	/* IRQ flag clear */
+				OPL_STATUS_RESET(OPL,0x7f);
+			}
+			else
+			{	/* set IRQ mask ,timer enable*/
+				UINT8 st1 = v&1;
+				UINT8 st2 = (v>>1)&1;
+				/* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */
+				OPL_STATUS_RESET(OPL,v&0x78);
+				OPL_STATUSMASK_SET(OPL,((~v)&0x78)|0x01);
+				/* timer 2 */
+				if(OPL->st[1] != st2)
+				{
+					double interval = st2 ? (double)OPL->T[1]*OPL->TimerBase : 0.0;
+					OPL->st[1] = st2;
+					if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+1,interval);
+				}
+				/* timer 1 */
+				if(OPL->st[0] != st1)
+				{
+					double interval = st1 ? (double)OPL->T[0]*OPL->TimerBase : 0.0;
+					OPL->st[0] = st1;
+					if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+0,interval);
+				}
+			}
+			return;
+#if BUILD_Y8950
+		case 0x06:		/* Key Board OUT */
+			if(OPL->type&OPL_TYPE_KEYBOARD)
+			{
+				if(OPL->keyboardhandler_w)
+					OPL->keyboardhandler_w(OPL->keyboard_param,v);
+				else
+					Log(LOG_WAR,"OPL:write unmapped KEYBOARD port\n");
+			}
+			return;
+		case 0x07:	/* DELTA-T controll : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
+			if(OPL->type&OPL_TYPE_ADPCM)
+				YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
+			return;
+		case 0x08:	/* MODE,DELTA-T : CSM,NOTESEL,x,x,smpl,da/ad,64k,rom */
+			OPL->mode = v;
+			v&=0x1f;	/* for DELTA-T unit */
+		case 0x09:		/* START ADD */
+		case 0x0a:
+		case 0x0b:		/* STOP ADD  */
+		case 0x0c:
+		case 0x0d:		/* PRESCALE   */
+		case 0x0e:
+		case 0x0f:		/* ADPCM data */
+		case 0x10: 		/* DELTA-N    */
+		case 0x11: 		/* DELTA-N    */
+		case 0x12: 		/* EG-CTRL    */
+			if(OPL->type&OPL_TYPE_ADPCM)
+				YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
+			return;
+#if 0
+		case 0x15:		/* DAC data    */
+		case 0x16:
+		case 0x17:		/* SHIFT    */
+			return;
+		case 0x18:		/* I/O CTRL (Direction) */
+			if(OPL->type&OPL_TYPE_IO)
+				OPL->portDirection = v&0x0f;
+			return;
+		case 0x19:		/* I/O DATA */
+			if(OPL->type&OPL_TYPE_IO)
+			{
+				OPL->portLatch = v;
+				if(OPL->porthandler_w)
+					OPL->porthandler_w(OPL->port_param,v&OPL->portDirection);
+			}
+			return;
+		case 0x1a:		/* PCM data */
+			return;
+#endif
+#endif
+		}
+		break;
+	case 0x20:	/* am,vib,ksr,eg type,mul */
+		slot = slot_array[r&0x1f];
+		if(slot == -1) return;
+		set_mul(OPL,slot,v);
+		return;
+	case 0x40:
+		slot = slot_array[r&0x1f];
+		if(slot == -1) return;
+		set_ksl_tl(OPL,slot,v);
+		return;
+	case 0x60:
+		slot = slot_array[r&0x1f];
+		if(slot == -1) return;
+		set_ar_dr(OPL,slot,v);
+		return;
+	case 0x80:
+		slot = slot_array[r&0x1f];
+		if(slot == -1) return;
+		set_sl_rr(OPL,slot,v);
+		return;
+	case 0xa0:
+		switch(r)
+		{
+		case 0xbd:
+			/* amsep,vibdep,r,bd,sd,tom,tc,hh */
+			{
+			UINT8 rkey = OPL->rythm^v;
+			OPL->ams_table = &AMS_TABLE[v&0x80 ? AMS_ENT : 0];
+			OPL->vib_table = &VIB_TABLE[v&0x40 ? VIB_ENT : 0];
+			OPL->rythm  = v&0x3f;
+			if(OPL->rythm&0x20)
+			{
+#if 0
+				usrintf_showmessage("OPL Rythm mode select");
+#endif
+				/* BD key on/off */
+				if(rkey&0x10)
+				{
+					if(v&0x10)
+					{
+						OPL->P_CH[6].op1_out[0] = OPL->P_CH[6].op1_out[1] = 0;
+						OPL_KEYON(&OPL->P_CH[6].SLOT[SLOT1]);
+						OPL_KEYON(&OPL->P_CH[6].SLOT[SLOT2]);
+					}
+					else
+					{
+						OPL_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1]);
+						OPL_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2]);
+					}
+				}
+				/* SD key on/off */
+				if(rkey&0x08)
+				{
+					if(v&0x08) OPL_KEYON(&OPL->P_CH[7].SLOT[SLOT2]);
+					else       OPL_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2]);
+				}/* TAM key on/off */
+				if(rkey&0x04)
+				{
+					if(v&0x04) OPL_KEYON(&OPL->P_CH[8].SLOT[SLOT1]);
+					else       OPL_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1]);
+				}
+				/* TOP-CY key on/off */
+				if(rkey&0x02)
+				{
+					if(v&0x02) OPL_KEYON(&OPL->P_CH[8].SLOT[SLOT2]);
+					else       OPL_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2]);
+				}
+				/* HH key on/off */
+				if(rkey&0x01)
+				{
+					if(v&0x01) OPL_KEYON(&OPL->P_CH[7].SLOT[SLOT1]);
+					else       OPL_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1]);
+				}
+			}
+			}
+			return;
+		}
+		/* keyon,block,fnum */
+		if( (r&0x0f) > 8) return;
+		CH = &OPL->P_CH[r&0x0f];
+		if(!(r&0x10))
+		{	/* a0-a8 */
+			block_fnum  = (CH->block_fnum&0x1f00) | v;
+		}
+		else
+		{	/* b0-b8 */
+			int keyon = (v>>5)&1;
+			block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
+			if(CH->keyon != keyon)
+			{
+				if( (CH->keyon=keyon) )
+				{
+					CH->op1_out[0] = CH->op1_out[1] = 0;
+					OPL_KEYON(&CH->SLOT[SLOT1]);
+					OPL_KEYON(&CH->SLOT[SLOT2]);
+				}
+				else
+				{
+					OPL_KEYOFF(&CH->SLOT[SLOT1]);
+					OPL_KEYOFF(&CH->SLOT[SLOT2]);
+				}
+			}
+		}
+		/* update */
+		if(CH->block_fnum != block_fnum)
+		{
+			int blockRv = 7-(block_fnum>>10);
+			int fnum   = block_fnum&0x3ff;
+			CH->block_fnum = block_fnum;
+
+			CH->ksl_base = KSL_TABLE[block_fnum>>6];
+			CH->fc = OPL->FN_TABLE[fnum]>>blockRv;
+			CH->kcode = CH->block_fnum>>9;
+			if( (OPL->mode&0x40) && CH->block_fnum&0x100) CH->kcode |=1;
+			CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
+			CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
+		}
+		return;
+	case 0xc0:
+		/* FB,C */
+		if( (r&0x0f) > 8) return;
+		CH = &OPL->P_CH[r&0x0f];
+		{
+		int feedback = (v>>1)&7;
+		CH->FB   = feedback ? (8+1) - feedback : 0;
+		CH->CON = v&1;
+		set_algorythm(CH);
+		}
+		return;
+	case 0xe0: /* wave type */
+		slot = slot_array[r&0x1f];
+		if(slot == -1) return;
+		CH = &OPL->P_CH[slot/2];
+		if(OPL->wavesel)
+		{
+			/* Log(LOG_INF,"OPL SLOT %d wave select %d\n",slot,v&3); */
+			CH->SLOT[slot&1].wavetable = &SIN_TABLE[(v&0x03)*SIN_ENT];
+		}
+		return;
+	}
+}
+
+/* lock/unlock for common table */
+static int OPL_LockTable(void)
+{
+	num_lock++;
+	if(num_lock>1) return 0;
+	/* first time */
+	cur_chip = NULL;
+	/* allocate total level table (128kb space) */
+	if( !OPLOpenTable() )
+	{
+		num_lock--;
+		return -1;
+	}
+	return 0;
+}
+
+static void OPL_UnLockTable(void)
+{
+	if(num_lock) num_lock--;
+	if(num_lock) return;
+	/* last time */
+	cur_chip = NULL;
+	OPLCloseTable();
+}
+
+#if (BUILD_YM3812 || BUILD_YM3526)
+/*******************************************************************************/
+/*		YM3812 local section                                                   */
+/*******************************************************************************/
+
+/* ---------- update one of chip ----------- */
+void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length)
+{
+    int i;
+	int data;
+	FMSAMPLE *buf = buffer;
+	UINT32 amsCnt  = OPL->amsCnt;
+	UINT32 vibCnt  = OPL->vibCnt;
+	UINT8 rythm = OPL->rythm&0x20;
+	OPL_CH *CH,*R_CH;
+
+	if( (void *)OPL != cur_chip ){
+		cur_chip = (void *)OPL;
+		/* channel pointers */
+		S_CH = OPL->P_CH;
+		E_CH = &S_CH[9];
+		/* rythm slot */
+		SLOT7_1 = &S_CH[7].SLOT[SLOT1];
+		SLOT7_2 = &S_CH[7].SLOT[SLOT2];
+		SLOT8_1 = &S_CH[8].SLOT[SLOT1];
+		SLOT8_2 = &S_CH[8].SLOT[SLOT2];
+		/* LFO state */
+		amsIncr = OPL->amsIncr;
+		vibIncr = OPL->vibIncr;
+		ams_table = OPL->ams_table;
+		vib_table = OPL->vib_table;
+	}
+	R_CH = rythm ? &S_CH[6] : E_CH;
+    for( i=0; i < length ; i++ )
+	{
+		/*            channel A         channel B         channel C      */
+		/* LFO */
+		ams = ams_table[(amsCnt+=amsIncr)>>AMS_SHIFT];
+		vib = vib_table[(vibCnt+=vibIncr)>>VIB_SHIFT];
+		outd[0] = 0;
+		/* FM part */
+		for(CH=S_CH ; CH < R_CH ; CH++)
+			OPL_CALC_CH(CH);
+		/* Rythn part */
+		if(rythm)
+			OPL_CALC_RH(S_CH);
+		/* limit check */
+		data = Limit( outd[0] , OPL_MAXOUT, OPL_MINOUT );
+		/* store to sound buffer */
+		buf[i] = data >> OPL_OUTSB;
+	}
+
+	OPL->amsCnt = amsCnt;
+	OPL->vibCnt = vibCnt;
+}
+#endif /* (BUILD_YM3812 || BUILD_YM3526) */
+
+#if BUILD_Y8950
+
+void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length)
+{
+    int i;
+	int data;
+	FMSAMPLE *buf = buffer;
+	UINT32 amsCnt  = OPL->amsCnt;
+	UINT32 vibCnt  = OPL->vibCnt;
+	UINT8 rythm = OPL->rythm&0x20;
+	OPL_CH *CH,*R_CH;
+	YM_DELTAT *DELTAT = OPL->deltat;
+
+	/* setup DELTA-T unit */
+	YM_DELTAT_DECODE_PRESET(DELTAT);
+
+	if( (void *)OPL != cur_chip ){
+		cur_chip = (void *)OPL;
+		/* channel pointers */
+		S_CH = OPL->P_CH;
+		E_CH = &S_CH[9];
+		/* rythm slot */
+		SLOT7_1 = &S_CH[7].SLOT[SLOT1];
+		SLOT7_2 = &S_CH[7].SLOT[SLOT2];
+		SLOT8_1 = &S_CH[8].SLOT[SLOT1];
+		SLOT8_2 = &S_CH[8].SLOT[SLOT2];
+		/* LFO state */
+		amsIncr = OPL->amsIncr;
+		vibIncr = OPL->vibIncr;
+		ams_table = OPL->ams_table;
+		vib_table = OPL->vib_table;
+	}
+	R_CH = rythm ? &S_CH[6] : E_CH;
+    for( i=0; i < length ; i++ )
+	{
+		/*            channel A         channel B         channel C      */
+		/* LFO */
+		ams = ams_table[(amsCnt+=amsIncr)>>AMS_SHIFT];
+		vib = vib_table[(vibCnt+=vibIncr)>>VIB_SHIFT];
+		outd[0] = 0;
+		/* deltaT ADPCM */
+		if( DELTAT->flag )
+			YM_DELTAT_ADPCM_CALC(DELTAT);
+		/* FM part */
+		for(CH=S_CH ; CH < R_CH ; CH++)
+			OPL_CALC_CH(CH);
+		/* Rythn part */
+		if(rythm)
+			OPL_CALC_RH(S_CH);
+		/* limit check */
+		data = Limit( outd[0] , OPL_MAXOUT, OPL_MINOUT );
+		/* store to sound buffer */
+		buf[i] = data >> OPL_OUTSB;
+	}
+	OPL->amsCnt = amsCnt;
+	OPL->vibCnt = vibCnt;
+	/* deltaT START flag */
+	if( !DELTAT->flag )
+		OPL->status &= 0xfe;
+}
+#endif
+
+/* ---------- reset one of chip ---------- */
+void OPLResetChip(FM_OPL *OPL)
+{
+	int c,s;
+	int i;
+
+	/* reset chip */
+	OPL->mode   = 0;	/* normal mode */
+	OPL_STATUS_RESET(OPL,0x7f);
+	/* reset with register write */
+	OPLWriteReg(OPL,0x01,0); /* wabesel disable */
+	OPLWriteReg(OPL,0x02,0); /* Timer1 */
+	OPLWriteReg(OPL,0x03,0); /* Timer2 */
+	OPLWriteReg(OPL,0x04,0); /* IRQ mask clear */
+	for(i = 0xff ; i >= 0x20 ; i-- ) OPLWriteReg(OPL,i,0);
+	/* reset OPerator paramater */
+	for( c = 0 ; c < OPL->max_ch ; c++ )
+	{
+		OPL_CH *CH = &OPL->P_CH[c];
+		/* OPL->P_CH[c].PAN = OPN_CENTER; */
+		for(s = 0 ; s < 2 ; s++ )
+		{
+			/* wave table */
+			CH->SLOT[s].wavetable = &SIN_TABLE[0];
+			/* CH->SLOT[s].evm = ENV_MOD_RR; */
+			CH->SLOT[s].evc = EG_OFF;
+			CH->SLOT[s].eve = EG_OFF+1;
+			CH->SLOT[s].evs = 0;
+		}
+	}
+#if BUILD_Y8950
+	if(OPL->type&OPL_TYPE_ADPCM)
+	{
+		YM_DELTAT *DELTAT = OPL->deltat;
+
+		DELTAT->freqbase = OPL->freqbase;
+		DELTAT->output_pointer = outd;
+		DELTAT->portshift = 5;
+		DELTAT->output_range = DELTAT_MIXING_LEVEL<<TL_BITS;
+		YM_DELTAT_ADPCM_Reset(DELTAT,0);
+	}
+#endif
+}
+
+
+/* ----------  Create one of vietual YM3812 ----------       */
+/* 'rate'  is sampling rate and 'bufsiz' is the size of the  */
+FM_OPL *OPLCreate(int type, int clock, int rate)
+{
+	char *ptr;
+	FM_OPL *OPL;
+	int state_size;
+	int max_ch = 9; /* normaly 9 channels */
+
+	if( OPL_LockTable() ==-1) return NULL;
+	/* allocate OPL state space */
+	state_size  = sizeof(FM_OPL);
+	state_size += sizeof(OPL_CH)*max_ch;
+#if BUILD_Y8950
+	if(type&OPL_TYPE_ADPCM) state_size+= sizeof(YM_DELTAT);
+#endif
+	/* allocate memory block */
+	ptr = emu_Malloc(state_size);
+	if(ptr==NULL) return NULL;
+	/* clear */
+	memset(ptr,0,state_size);
+	OPL        = (FM_OPL *)ptr; ptr+=sizeof(FM_OPL);
+	OPL->P_CH  = (OPL_CH *)ptr; ptr+=sizeof(OPL_CH)*max_ch;
+#if BUILD_Y8950
+	if(type&OPL_TYPE_ADPCM) OPL->deltat = (YM_DELTAT *)ptr; ptr+=sizeof(YM_DELTAT);
+#endif
+	/* set channel state pointer */
+	OPL->type  = type;
+	OPL->clock = clock;
+	OPL->rate  = rate;
+	OPL->max_ch = max_ch;
+	/* init grobal tables */
+	OPL_initalize(OPL);
+	/* reset chip */
+	OPLResetChip(OPL);
+	return OPL;
+}
+
+/* ----------  Destroy one of vietual YM3812 ----------       */
+void OPLDestroy(FM_OPL *OPL)
+{
+	OPL_UnLockTable();
+	emu_Free(OPL);
+}
+
+/* ----------  Option handlers ----------       */
+
+void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset)
+{
+	OPL->TimerHandler   = TimerHandler;
+	OPL->TimerParam = channelOffset;
+}
+void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param)
+{
+	OPL->IRQHandler     = IRQHandler;
+	OPL->IRQParam = param;
+}
+void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param)
+{
+	OPL->UpdateHandler = UpdateHandler;
+	OPL->UpdateParam = param;
+}
+#if BUILD_Y8950
+void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param)
+{
+	OPL->porthandler_w = PortHandler_w;
+	OPL->porthandler_r = PortHandler_r;
+	OPL->port_param = param;
+}
+
+void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param)
+{
+	OPL->keyboardhandler_w = KeyboardHandler_w;
+	OPL->keyboardhandler_r = KeyboardHandler_r;
+	OPL->keyboard_param = param;
+}
+#endif
+/* ---------- YM3812 I/O interface ---------- */
+int OPLWrite(FM_OPL *OPL,int a,int v)
+{
+	if( !(a&1) )
+	{	/* address port */
+		OPL->address = v & 0xff;
+	}
+	else
+	{	/* data port */
+		if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0);
+		OPLWriteReg(OPL,OPL->address,v);
+	}
+	return OPL->status>>7;
+}
+
+unsigned char OPLRead(FM_OPL *OPL,int a)
+{
+	if( !(a&1) )
+	{	/* status port */
+		return OPL->status & (OPL->statusmask|0x80);
+	}
+	/* data port */
+	switch(OPL->address)
+	{
+	case 0x05: /* KeyBoard IN */
+		if(OPL->type&OPL_TYPE_KEYBOARD)
+		{
+			if(OPL->keyboardhandler_r)
+				return OPL->keyboardhandler_r(OPL->keyboard_param);
+			else
+				Log(LOG_WAR,"OPL:read unmapped KEYBOARD port\n");
+		}
+		return 0;
+#if 0
+	case 0x0f: /* ADPCM-DATA  */
+		return 0;
+#endif
+	case 0x19: /* I/O DATA    */
+		if(OPL->type&OPL_TYPE_IO)
+		{
+			if(OPL->porthandler_r)
+				return OPL->porthandler_r(OPL->port_param);
+			else
+				Log(LOG_WAR,"OPL:read unmapped I/O port\n");
+		}
+		return 0;
+	case 0x1a: /* PCM-DATA    */
+		return 0;
+	}
+	return 0;
+}
+
+int OPLTimerOver(FM_OPL *OPL,int c)
+{
+	if( c )
+	{	/* Timer B */
+		OPL_STATUS_SET(OPL,0x20);
+	}
+	else
+	{	/* Timer A */
+		OPL_STATUS_SET(OPL,0x40);
+		/* CSM mode key,TL controll */
+		if( OPL->mode & 0x80 )
+		{	/* CSM mode total level latch and auto key on */
+			int ch;
+			if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0);
+			for(ch=0;ch<9;ch++)
+				CSMKeyControll( &OPL->P_CH[ch] );
+		}
+	}
+	/* reload timer */
+	if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+c,(double)OPL->T[c]*OPL->TimerBase);
+	return OPL->status>>7;
+}
diff --git a/MCUME_pico2/picosms/fmopl.h b/MCUME_pico2/picosms/fmopl.h
new file mode 100644
index 0000000..a3484cd
--- /dev/null
+++ b/MCUME_pico2/picosms/fmopl.h
@@ -0,0 +1,142 @@
+#ifndef __FMOPL_H_
+#define __FMOPL_H_
+
+typedef void (*OPL_TIMERHANDLER)(int channel,double interval_Sec);
+typedef void (*OPL_IRQHANDLER)(int param,int irq);
+typedef void (*OPL_UPDATEHANDLER)(int param,int min_interval_us);
+typedef void (*OPL_PORTHANDLER_W)(int param,unsigned char data);
+typedef unsigned char (*OPL_PORTHANDLER_R)(int param);
+
+/* !!!!! here is private section , do not access there member direct !!!!! */
+
+#define OPL_TYPE_WAVESEL   0x01  /* waveform select    */
+#define OPL_TYPE_ADPCM     0x02  /* DELTA-T ADPCM unit */
+#define OPL_TYPE_KEYBOARD  0x04  /* keyboard interface */
+#define OPL_TYPE_IO        0x08  /* I/O port */
+
+/* ---------- OPL one of slot  ---------- */
+typedef struct fm_opl_slot {
+	INT32 TL;		/* total level     :TL << 8            */
+	INT32 TLL;		/* adjusted now TL                     */
+	UINT8  KSR;		/* key scale rate  :(shift down bit)   */
+	INT32 *AR;		/* attack rate     :&AR_TABLE[AR<<2]   */
+	INT32 *DR;		/* decay rate      :&DR_TALBE[DR<<2]   */
+	INT32 SL;		/* sustin level    :SL_TALBE[SL]       */
+	INT32 *RR;		/* release rate    :&DR_TABLE[RR<<2]   */
+	UINT8 ksl;		/* keyscale level  :(shift down bits)  */
+	UINT8 ksr;		/* key scale rate  :kcode>>KSR         */
+	UINT32 mul;		/* multiple        :ML_TABLE[ML]       */
+	UINT32 Cnt;		/* frequency count :                   */
+	UINT32 Incr;	/* frequency step  :                   */
+	/* envelope generator state */
+	UINT8 eg_typ;	/* envelope type flag                  */
+	UINT8 evm;		/* envelope phase                      */
+	INT32 evc;		/* envelope counter                    */
+	INT32 eve;		/* envelope counter end point          */
+	INT32 evs;		/* envelope counter step               */
+	INT32 evsa;	/* envelope step for AR :AR[ksr]       */
+	INT32 evsd;	/* envelope step for DR :DR[ksr]       */
+	INT32 evsr;	/* envelope step for RR :RR[ksr]       */
+	/* LFO */
+	UINT8 ams;		/* ams flag                            */
+	UINT8 vib;		/* vibrate flag                        */
+	/* wave selector */
+	INT32 **wavetable;
+}OPL_SLOT;
+
+/* ---------- OPL one of channel  ---------- */
+typedef struct fm_opl_channel {
+	OPL_SLOT SLOT[2];
+	UINT8 CON;			/* connection type                     */
+	UINT8 FB;			/* feed back       :(shift down bit)   */
+	INT32 *connect1;	/* slot1 output pointer                */
+	INT32 *connect2;	/* slot2 output pointer                */
+	INT32 op1_out[2];	/* slot1 output for selfeedback        */
+	/* phase generator state */
+	UINT32  block_fnum;	/* block+fnum      :                   */
+	UINT8 kcode;		/* key code        : KeyScaleCode      */
+	UINT32  fc;			/* Freq. Increment base                */
+	UINT32  ksl_base;	/* KeyScaleLevel Base step             */
+	UINT8 keyon;		/* key on/off flag                     */
+} OPL_CH;
+
+/* OPL state */
+typedef struct fm_opl_f {
+	UINT8 type;			/* chip type                        */
+	int clock;			/* master clock  (Hz)                */
+	int rate;			/* sampling rate (Hz)                */
+	double freqbase;	/* frequency base                    */
+	double TimerBase;	/* Timer base time (==sampling time) */
+	UINT8 address;		/* address register                  */
+	UINT8 status;		/* status flag                       */
+	UINT8 statusmask;	/* status mask                       */
+	UINT32 mode;		/* Reg.08 : CSM , notesel,etc.       */
+	/* Timer */
+	int T[2];			/* timer counter       */
+	UINT8 st[2];		/* timer enable        */
+	/* FM channel slots */
+	OPL_CH *P_CH;		/* pointer of CH       */
+	int	max_ch;			/* maximum channel     */
+	/* Rythm sention */
+	UINT8 rythm;		/* Rythm mode , key flag */
+#if BUILD_Y8950
+	/* Delta-T ADPCM unit (Y8950) */
+	YM_DELTAT *deltat;			/* DELTA-T ADPCM       */
+#endif
+	/* Keyboard / I/O interface unit (Y8950) */
+	UINT8 portDirection;
+	UINT8 portLatch;
+	OPL_PORTHANDLER_R porthandler_r;
+	OPL_PORTHANDLER_W porthandler_w;
+	int port_param;
+	OPL_PORTHANDLER_R keyboardhandler_r;
+	OPL_PORTHANDLER_W keyboardhandler_w;
+	int keyboard_param;
+	/* time tables */
+	INT32 AR_TABLE[75];	/* atttack rate tables */
+	INT32 DR_TABLE[75];	/* decay rate tables   */
+	UINT32 FN_TABLE[1024];  /* fnumber -> increment counter */
+	/* LFO */
+	INT32 *ams_table;
+	INT32 *vib_table;
+	INT32 amsCnt;
+	INT32 amsIncr;
+	INT32 vibCnt;
+	INT32 vibIncr;
+	/* wave selector enable flag */
+	UINT8 wavesel;
+	/* external event callback handler */
+	OPL_TIMERHANDLER  TimerHandler;		/* TIMER handler   */
+	int TimerParam;						/* TIMER parameter */
+	OPL_IRQHANDLER    IRQHandler;		/* IRQ handler    */
+	int IRQParam;						/* IRQ parameter  */
+	OPL_UPDATEHANDLER UpdateHandler;	/* stream update handler   */
+	int UpdateParam;					/* stream update parameter */
+} FM_OPL;
+
+/* ---------- Generic interface section ---------- */
+#define OPL_TYPE_YM3526 (0)
+#define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)
+#define OPL_TYPE_Y8950  (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)
+
+FM_OPL *OPLCreate(int type, int clock, int rate);
+void OPLDestroy(FM_OPL *OPL);
+void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset);
+void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param);
+void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param);
+/* Y8950 port handlers */
+void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param);
+void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param);
+
+void OPLResetChip(FM_OPL *OPL);
+int OPLWrite(FM_OPL *OPL,int a,int v);
+void OPLWriteReg(FM_OPL *OPL, int r, int v);
+unsigned char OPLRead(FM_OPL *OPL,int a);
+int OPLTimerOver(FM_OPL *OPL,int c);
+
+/* YM3626/YM3812 local section */
+void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);
+
+void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length);
+
+#endif
diff --git a/MCUME_pico2/picosms/keyboard_osd.h b/MCUME_pico2/picosms/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/picosms/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/picosms/memory.c b/MCUME_pico2/picosms/memory.c
new file mode 100644
index 0000000..872d82a
--- /dev/null
+++ b/MCUME_pico2/picosms/memory.c
@@ -0,0 +1,25 @@
+#include "shared.h"
+
+
+uint8 * cache;
+
+
+
+void mem_init(void) {
+    cache = emu_Malloc(CACHE_SIZE); 
+}
+
+
+int mem_test(void) {
+//	for (int i=0x40000;i<OBJ_CACHE_SIZE;i++) {
+//		if (obj_pattern_cache[i] != 0) return 0;;
+//	}
+	return 1;
+}
+
+void memcpy_rom(int dst, int src, int size) {
+	while (size > 0) {   
+		write_rom(dst++, read_rom(src++));
+		size--;
+	}
+}
diff --git a/MCUME_pico2/picosms/memory.h b/MCUME_pico2/picosms/memory.h
new file mode 100644
index 0000000..f5aac9d
--- /dev/null
+++ b/MCUME_pico2/picosms/memory.h
@@ -0,0 +1,22 @@
+#ifndef _MEMORY_H_
+#define _MEMORY_H_
+
+#include "shared.h"
+
+#define CACHE_SIZE 0x20000
+
+
+extern uint8 * cache;
+
+
+extern void  mem_init(void);
+extern int mem_test(void);
+extern uint8 rom_version(void);
+extern uint8 readb_rom(int address);
+extern uint8 readb_swap_rom(int address);
+extern uint16 readw_swap_rom(int address);
+extern void  write_rom(int address, uint8 val);
+
+extern void memcpy_rom(int dst, int src, int size);
+
+#endif
diff --git a/MCUME_pico2/picosms/picosms.cpp b/MCUME_pico2/picosms/picosms.cpp
new file mode 100644
index 0000000..1e1d77a
--- /dev/null
+++ b/MCUME_pico2/picosms/picosms.cpp
@@ -0,0 +1,343 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+//extern "C" {
+#include "emu.h"
+//}
+#include <stdio.h>
+
+#include <stdio.h>
+#include "pico_dsp.h"
+//#include "psram_spi.h"
+
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+#include "hdmi_framebuffer.h"
+
+//psram_spi_inst_t* async_spi_inst;
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, truxe);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(125000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+
+    // Overclock!
+//    set_sys_clock_khz(280000, true);
+//    stdio_init_all();
+
+     emu_init();
+   
+
+
+
+
+/*
+
+
+    psram_spi_inst_t psram_spi = psram_spi_init(pio2, 0);
+
+
+uint32_t psram_begin, psram_elapsed;
+    float psram_speed;
+
+    printf("Testing PSRAM...\n");
+
+
+    // **************** 8 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+        psram_write8(&psram_spi, addr, (addr & 0xFF));
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("8 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+
+    //psram_begin = time_us_32();
+    //for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+    //    psram_write8_async(&psram_spi, addr, (addr & 0xFF));
+    //}
+    //psram_elapsed = time_us_32() - psram_begin;
+    //psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    //printf("8 bit: PSRAM write async 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+        uint8_t result = psram_read8(&psram_spi, addr);
+        if ((uint8_t)(addr & 0xFF) != result) {
+            printf("\nPSRAM failure at address %x (%x != %x)\n", addr, addr & 0xFF, result);
+            return 1;
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("8 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** 16 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 2) {
+        psram_write16(&psram_spi, addr, (((addr + 1) & 0xFF) << 8) | (addr & 0xFF));
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("16 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 2) {
+        uint16_t result = psram_read16(&psram_spi, addr);
+        if ((uint16_t)(
+                (((addr + 1) & 0xFF) << 8) |
+                (addr & 0xFF)) != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, (
+                (((addr + 1) & 0xFF) << 8) |
+                (addr & 0xFF)), result
+            );
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 8 * 1024 * 1024 / psram_elapsed;
+    printf("16 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** 32 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 4) {
+        psram_write32(
+            &psram_spi, addr,
+            (uint32_t)(
+                (((addr + 3) & 0xFF) << 24) |
+                (((addr + 2) & 0xFF) << 16) |
+                (((addr + 1) & 0xFF) << 8)  |
+                (addr & 0XFF))
+        );
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("32 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 4) {
+        uint32_t result = psram_read32(&psram_spi, addr);
+        if ((uint32_t)(
+            (((addr + 3) & 0xFF) << 24) |
+            (((addr + 2) & 0xFF) << 16) |
+            (((addr + 1) & 0xFF) << 8)  |
+            (addr & 0XFF)) != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, (
+                (((addr + 3) & 0xFF) << 24) |
+                (((addr + 2) & 0xFF) << 16) |
+                (((addr + 1) & 0xFF) << 8)  |
+                (addr & 0XFF)), result
+            );
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 8 * 1024 * 1024 / psram_elapsed;
+    printf("32 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** n bits testing ****************
+    uint8_t write_data[256];
+    for (size_t i = 0; i < 256; ++i) {
+        write_data[i] = i;
+    }
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 256) {
+        for (uint32_t step = 0; step < 256; step += 16) {
+            psram_writen(&psram_spi, addr + step, write_data + step, 16);
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("128 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    uint8_t read_data[16];
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 256) {
+        for (uint32_t step = 0; step < 256; step += 16) {
+            psram_readn(&psram_spi, addr + step, read_data, 16);
+            if (memcmp(read_data, write_data + step, 16) != 0) {
+                printf("PSRAM failure at address %x", addr);
+                return 1;
+            }
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("128 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+*/
+
+
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(25, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();               
+    }
+}
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }
+    
+}
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picosms/program_config.h b/MCUME_pico2/picosms/program_config.h
new file mode 100644
index 0000000..ae30c2e
--- /dev/null
+++ b/MCUME_pico2/picosms/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define FLASH_STORE_START 0x100000  
+
+#endif
diff --git a/MCUME_pico2/picosms/render.c b/MCUME_pico2/picosms/render.c
new file mode 100644
index 0000000..1770155
--- /dev/null
+++ b/MCUME_pico2/picosms/render.c
@@ -0,0 +1,511 @@
+#include "shared.h"
+
+/* Background drawing function */
+static void (*render_bg)(int line);
+
+/* Pointer to output buffer */
+static byte *linebuf;
+
+/* Internal buffer for drawing non 8-bit displays */
+static byte internal_buffer[0x100];
+
+/* Pattern cache */
+//static byte cache[0x20000];
+
+/* Dirty pattern info */
+byte svram_dirty[0x200];
+byte sis_vram_dirty;
+
+/* Pixel look-up table */
+//#include "genlut.h"
+#include "smslut.h"
+//static byte lut[0x10000];
+
+
+/* Attribute expansion table */
+static UINT32 atex[4] =
+{
+    0x00000000,
+    0x10101010,
+    0x20202020,
+    0x30303030,
+};
+
+/* Display sizes */
+static int vp_vstart;
+static int vp_vend;
+static int vp_hstart;
+static int vp_hend;
+
+extern void emu_DrawLine16(unsigned short *src, int width , int height, int line);
+extern void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line); 
+extern void emu_printf(char * text);
+
+/* Macros to access memory 32-bits at a time (from MAME's drawgfx.c) */
+
+#ifdef ALIGN_DWORD
+
+static __inline__ UINT32 read_dword(void *address)
+{
+    if ((UINT32)address & 3)
+	{
+#ifdef LSB_FIRST  /* little endian version */
+        return ( *((byte *)address) +
+                (*((byte *)address+1) << 8)  +
+                (*((byte *)address+2) << 16) +
+                (*((byte *)address+3) << 24) );
+#else             /* big endian version */
+        return ( *((byte *)address+3) +
+                (*((byte *)address+2) << 8)  +
+                (*((byte *)address+1) << 16) +
+                (*((byte *)address)   << 24) );
+#endif
+	}
+	else
+        return *(UINT32 *)address;
+}
+
+
+static __inline__ void write_dword(void *address, UINT32 data)
+{
+    if ((UINT32)address & 3)
+	{
+#ifdef LSB_FIRST
+            *((byte *)address) =    data;
+            *((byte *)address+1) = (data >> 8);
+            *((byte *)address+2) = (data >> 16);
+            *((byte *)address+3) = (data >> 24);
+#else
+            *((byte *)address+3) =  data;
+            *((byte *)address+2) = (data >> 8);
+            *((byte *)address+1) = (data >> 16);
+            *((byte *)address)   = (data >> 24);
+#endif
+		return;
+  	}
+  	else
+        *(UINT32 *)address = data;
+}
+#else
+#define read_dword(address) *(UINT32 *)address
+#define write_dword(address,data) *(UINT32 *)address=data
+#endif
+
+
+/****************************************************************************/
+
+
+/* Initialize the rendering data */
+void render_init(void)
+{
+    render_reset();
+}
+
+
+/* Reset the rendering data */
+void render_reset(void)
+{
+    int i;
+
+    /* Clear display bitmap */
+//    memset(sbitmap.data, 0, sbitmap.pitch * sbitmap.height);
+
+    /* Clear palette */
+    for(i = 0; i < PALETTE_SIZE; i += 1)
+    {
+        palette_sync(i);
+    }
+
+    /* Invalidate pattern cache */
+    sis_vram_dirty = 1;
+    memset(svram_dirty, 1, 0x200);
+    memset(cache, 0, CACHE_SIZE);
+
+    /* Set up viewport size */
+    if(IS_GG)
+    {
+        vp_vstart = 24;
+        vp_vend   = 168;
+        vp_hstart = 6;
+        vp_hend   = 26;
+    }
+    else
+    {
+        vp_vstart = 0;
+        vp_vend   = 192;
+        vp_hstart = 0;
+        vp_hend   = 32;
+    }
+
+    /* Pick render routine */
+    render_bg = IS_GG ? render_bg_gg : render_bg_sms;
+}
+
+
+/* Draw a line of the display */
+void render_line(int line)
+{
+    /* Ensure we're within the viewport range */
+    if((line < vp_vstart) || (line >= vp_vend)) return;
+
+    /* Point to current line in output buffer */
+    linebuf = &internal_buffer[0];
+
+    /* Update pattern cache */
+    update_cache();
+
+    /* Blank line */
+    if( (!(vdp.reg[1] & 0x40)) || (((vdp.reg[2] & 1) == 0) && (IS_SMS)))
+    {
+        memset(linebuf + (vp_hstart << 3), BACKDROP_COLOR, BMP_WIDTH);
+    }
+    else
+    {
+        /* Draw background */
+        render_bg(line);
+
+        /* Draw sprites */
+        render_obj(line);
+
+        /* Blank leftmost column of display */
+        if(vdp.reg[0] & 0x20)
+        {
+            memset(linebuf, BACKDROP_COLOR, 8);
+        }
+    }
+    for (int i=0; i<BMP_WIDTH ;i++)
+      internal_buffer[i] &= 0x1F;
+    emu_DrawLinePal16(&internal_buffer[BMP_X_OFFSET], BMP_WIDTH , BMP_HEIGHT, line);
+}
+
+
+/* Draw the Master System background */
+void render_bg_sms(int line)
+{
+    int locked = 0;
+    int v_line = (line + vdp.reg[9]) % 224;
+    int v_row  = (v_line & 7) << 3;
+    int hscroll = ((vdp.reg[0] & 0x40) && (line < 0x10)) ? 0 : (0x100 - vdp.reg[8]);
+    int column = vp_hstart;
+    UINT16 attr;
+    UINT16 *nt = (UINT16 *)&vdp.vram[vdp.ntab + ((v_line >> 3) << 6)];
+    int nt_scroll = (hscroll >> 3);
+    int shift = (hscroll & 7);
+    UINT32 atex_mask;
+    UINT32 *cache_ptr;
+    UINT32 *linebuf_ptr = (UINT32 *)&linebuf[0 - shift];
+
+    /* Draw first column (clipped) */
+    if(shift)
+    {
+        int x, c, a;
+
+        attr = nt[(column + nt_scroll) & 0x1F];
+
+#ifndef LSB_FIRST
+        attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8));
+#endif
+        a = (attr >> 7) & 0x30;
+
+        for(x = shift; x < 8; x += 1)
+        {
+            c = cache[((attr & 0x7FF) << 6) | (v_row) | (x)];
+            linebuf[(0 - shift) + (x)  ] = ((c) | (a));
+        }
+
+        column += 1;
+    }
+
+    /* Draw a line of the background */
+    for(; column < vp_hend; column += 1)
+    {
+        /* Stop vertical scrolling for leftmost eight columns */
+        if((vdp.reg[0] & 0x80) && (!locked) && (column >= 24))
+        {
+            locked = 1;
+            v_row = (line & 7) << 3;
+            nt = (UINT16 *)&vdp.vram[((vdp.reg[2] << 10) & 0x3800) + ((line >> 3) << 6)];
+        }
+
+        /* Get name table attribute word */
+        attr = nt[(column + nt_scroll) & 0x1F];
+
+#ifndef LSB_FIRST
+        attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8));
+#endif
+        /* Expand priority and palette bits */
+        atex_mask = atex[(attr >> 11) & 3];
+
+        /* Point to a line of pattern data in cache */
+        cache_ptr = (UINT32 *)&cache[((attr & 0x7FF) << 6) | (v_row)];
+        
+        /* Copy the left half, adding the attribute bits in */
+        write_dword( &linebuf_ptr[(column << 1)] , read_dword( &cache_ptr[0] ) | (atex_mask));
+
+        /* Copy the right half, adding the attribute bits in */
+        write_dword( &linebuf_ptr[(column << 1) | (1)], read_dword( &cache_ptr[1] ) | (atex_mask));
+    }
+
+    /* Draw last column (clipped) */
+    if(shift)
+    {
+        int x, c, a;
+
+        char *p = &linebuf[(0 - shift)+(column << 3)];
+
+        attr = nt[(column + nt_scroll) & 0x1F];
+
+#ifndef LSB_FIRST
+        attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8));
+#endif
+        a = (attr >> 7) & 0x30;
+
+        for(x = 0; x < shift; x += 1)
+        {
+            c = cache[((attr & 0x7FF) << 6) | (v_row) | (x)];
+            p[x] = ((c) | (a));
+        }
+    }
+}
+
+
+/* Draw the Game Gear background */
+void render_bg_gg(int line)
+{
+    int v_line = (line + vdp.reg[9]) % 224;
+    int v_row  = (v_line & 7) << 3;
+    int hscroll = (0x100 - vdp.reg[8]);
+    int column;
+    UINT16 attr;
+    UINT16 *nt = (UINT16 *)&vdp.vram[vdp.ntab + ((v_line >> 3) << 6)];
+    int nt_scroll = (hscroll >> 3);
+    UINT32 atex_mask;
+    UINT32 *cache_ptr;
+    UINT32 *linebuf_ptr = (UINT32 *)&linebuf[0 - (hscroll & 7)];
+
+    /* Draw a line of the background */
+    for(column = vp_hstart; column <= vp_hend; column += 1)
+    {
+        /* Get name table attribute word */
+        attr = nt[(column + nt_scroll) & 0x1F];
+
+#ifndef LSB_FIRST
+        attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8));
+#endif
+        /* Expand priority and palette bits */
+        atex_mask = atex[(attr >> 11) & 3];
+
+        /* Point to a line of pattern data in cache */
+        cache_ptr = (UINT32 *)&cache[((attr & 0x7FF) << 6) | (v_row)];
+
+        /* Copy the left half, adding the attribute bits in */
+        write_dword( &linebuf_ptr[(column << 1)] , read_dword( &cache_ptr[0] ) | (atex_mask));
+
+        /* Copy the right half, adding the attribute bits in */
+        write_dword( &linebuf_ptr[(column << 1) | (1)], read_dword( &cache_ptr[1] ) | (atex_mask));
+    }
+}
+
+
+/* Draw sprites */
+void render_obj(int line)
+{
+    int i;
+
+    /* Sprite count for current line (8 max.) */
+    int count = 0;
+
+    /* Sprite dimensions */
+    int width = 8;
+    int height = (vdp.reg[1] & 0x02) ? 16 : 8;
+
+    /* Pointer to sprite attribute table */
+    byte *st = (byte *)&vdp.vram[vdp.satb];
+
+    /* Adjust dimensions for double size sprites */
+    if(vdp.reg[1] & 0x01)
+    {
+        width *= 2;
+        height *= 2;
+    }
+
+    /* Draw sprites in front-to-back order */
+    for(i = 0; i < 64; i += 1)
+    {
+        /* Sprite Y position */
+        int yp = st[i];
+
+        /* End of sprite list marker? */
+        if(yp == 208) return;
+
+        /* Actual Y position is +1 */
+        yp += 1;
+
+        /* Wrap Y coordinate for sprites > 240 */
+        if(yp > 240) yp -= 256;
+
+        /* Check if sprite falls on current line */
+        if((line >= yp) && (line < (yp + height)))
+        {
+            byte *linebuf_ptr;
+
+            /* Width of sprite */
+            int start = 0;
+            int end = width;
+
+            /* Sprite X position */
+            int xp = st[0x80 + (i << 1)];
+
+            /* Pattern name */
+            int n = st[0x81 + (i << 1)];
+
+            /* Bump sprite count */
+            count += 1;
+
+            /* Too many sprites on this line ? */
+            if((vdp.limit) && (count == 9)) return;
+
+            /* X position shift */
+            if(vdp.reg[0] & 0x08) xp -= 8;
+
+            /* Add MSB of pattern name */
+            if(vdp.reg[6] & 0x04) n |= 0x0100;
+
+            /* Mask LSB for 8x16 sprites */
+            if(vdp.reg[1] & 0x02) n &= 0x01FE;
+
+            /* Point to offset in line buffer */
+            linebuf_ptr = (byte *)&linebuf[xp];
+
+            /* Clip sprites on left edge */
+            if(xp < 0)
+            {
+                start = (0 - xp);
+            }
+
+            /* Clip sprites on right edge */
+            if((xp + width) > 256)        
+            {
+                end = (256 - xp);
+            }
+
+            /* Draw double size sprite */
+            if(vdp.reg[1] & 0x01)
+            {
+                int x;
+                byte *cache_ptr = (byte *)&cache[(n << 6) | (((line - yp) >> 1) << 3)];
+
+                /* Draw sprite line */
+                for(x = start; x < end; x += 1)
+                {
+                    /* Source pixel from cache */
+                    byte sp = cache_ptr[(x >> 1)];
+    
+                    /* Only draw opaque sprite pixels */
+                    if(sp)
+                    {
+                        /* Background pixel from line buffer */
+                        byte bg = linebuf_ptr[x];
+    
+                        /* Look up result */
+                        linebuf_ptr[x] = lut[(bg << 8) | (sp)]; /* + COL_OFFSET; */
+    
+                        /* Set sprite collision flag */
+                        if(bg & 0x40) vdp.status |= 0x20;
+                    }
+                }
+            }
+            else /* Regular size sprite (8x8 / 8x16) */
+            {
+                int x;
+                byte *cache_ptr = (byte *)&cache[(n << 6) | ((line - yp) << 3)];
+
+                /* Draw sprite line */
+                for(x = start; x < end; x += 1)
+                {
+                    /* Source pixel from cache */
+                    byte sp = cache_ptr[x];
+    
+                    /* Only draw opaque sprite pixels */
+                    if(sp)
+                    {
+                        /* Background pixel from line buffer */
+                        byte bg = linebuf_ptr[x];
+    
+                        /* Look up result */
+                        linebuf_ptr[x] = lut[(bg << 8) | (sp)]; /* + COL_OFFSET; */
+    
+                        /* Set sprite collision flag */
+                        if(bg & 0x40) vdp.status |= 0x20;
+                    }
+                }
+            }
+        }
+    }
+}
+
+
+/* Update pattern cache with modified tiles */
+void update_cache(void)
+{
+    int i, x, y, c;
+    int b0, b1, b2, b3;
+    int i0, i1, i2, i3;
+
+    if(!sis_vram_dirty) return;
+    sis_vram_dirty = 0;
+
+    for(i = 0; i < 0x200; i += 1)
+    {
+        if(svram_dirty[i])
+        {
+            svram_dirty[i] = 0;
+
+            for(y = 0; y < 8; y += 1)
+            {
+                b0 = vdp.vram[(i << 5) | (y << 2) | (0)];
+                b1 = vdp.vram[(i << 5) | (y << 2) | (1)];
+                b2 = vdp.vram[(i << 5) | (y << 2) | (2)];
+                b3 = vdp.vram[(i << 5) | (y << 2) | (3)];
+
+                for(x = 0; x < 8; x += 1)
+                {
+                    i0 = (b0 >> (7 - x)) & 1;
+                    i1 = (b1 >> (7 - x)) & 1;
+                    i2 = (b2 >> (7 - x)) & 1;
+                    i3 = (b3 >> (7 - x)) & 1;
+
+                    c = (i3 << 3 | i2 << 2 | i1 << 1 | i0);
+
+                    cache[0x00000 | (i << 6) | ((y  ) << 3) | (x  )] = c;
+                    cache[0x08000 | (i << 6) | ((y  ) << 3) | (7-x)] = c;
+                    cache[0x10000 | (i << 6) | ((7-y) << 3) | (x  )] = c;
+                    cache[0x18000 | (i << 6) | ((7-y) << 3) | (7-x)] = c;
+                }
+            }
+        }
+    }
+}
+
+/* Update a palette entry */
+void palette_sync(int index)
+{
+    int r, g, b;
+
+    if(IS_GG)
+    {
+        r = ((vdp.cram[(index << 1) | 0] >> 1) & 7) << 5;
+        g = ((vdp.cram[(index << 1) | 0] >> 5) & 7) << 5;
+        b = ((vdp.cram[(index << 1) | 1] >> 1) & 7) << 5;
+    }
+    else
+    {
+        r = ((vdp.cram[index] >> 0) & 3) << 6;
+        g = ((vdp.cram[index] >> 2) & 3) << 6;
+        b = ((vdp.cram[index] >> 4) & 3) << 6;
+    }
+
+    emu_SetPaletteEntry(r,g,b,index);
+
+    sbitmap.pal.dirty[index] = sbitmap.pal.update = 1;
+}
diff --git a/MCUME_pico2/picosms/render.h b/MCUME_pico2/picosms/render.h
new file mode 100644
index 0000000..35ab6f0
--- /dev/null
+++ b/MCUME_pico2/picosms/render.h
@@ -0,0 +1,23 @@
+
+#ifndef _RENDER_H_
+#define _RENDER_H_
+
+
+/* Used for blanking a line in whole or in part */
+#define BACKDROP_COLOR      (0x10 | (vdp.reg[7] & 0x0F))
+
+/* Global data - used by 'vdp.c' */
+extern byte svram_dirty[0x200];
+extern byte sis_vram_dirty;
+
+/* Function prototypes */
+void render_init(void);
+void render_reset(void);
+void render_bg_gg(int line);
+void render_bg_sms(int line);
+void render_obj(int line);
+void render_line(int line);
+void update_cache(void);
+void palette_sync(int index);
+
+#endif /* _RENDER_H_ */
diff --git a/MCUME_pico2/picosms/shared.h b/MCUME_pico2/picosms/shared.h
new file mode 100644
index 0000000..9c68474
--- /dev/null
+++ b/MCUME_pico2/picosms/shared.h
@@ -0,0 +1,60 @@
+
+#ifndef _SHARED_H_
+#define _SHARED_H_
+
+#define VERSION     "0.9.3"
+
+//#define ALIGN_DWORD 1
+#define LSB_FIRST 1
+#define SOUND_PRESENT 1
+
+/* Data types */
+
+typedef unsigned char 						byte;
+
+typedef unsigned char						UINT8;
+typedef unsigned short					UINT16;
+typedef unsigned int						UINT32;
+typedef signed char 						INT8;
+typedef signed short						INT16;
+typedef signed int							INT32;
+
+typedef unsigned char						uint8;
+typedef unsigned short					uint16;
+typedef unsigned int						uint32;
+typedef signed char 						int8;
+typedef signed short						int16;
+typedef signed int							int32;
+
+#define NULL 0
+
+typedef union {
+#ifdef LSB_FIRST
+	struct { UINT8 l,h,h2,h3; } b;
+	struct { UINT16 l,h; } w;
+#else
+	struct { UINT8 h3,h2,h,l; } b;
+	struct { UINT16 h,l; } w;
+#endif
+	UINT32 d;
+}	PAIR;
+
+#define __inline__
+
+/* To keep the MAME code happy */
+#define HAS_YM3812  1
+typedef signed short int FMSAMPLE;
+
+
+#include "memory.h"
+#include "z80.h"
+#include "sms.h"
+#include "vdp.h"
+#include "render.h"
+#include "sn76496.h"
+#include "fmopl.h"
+#include "ym2413.h"
+#include "system.h"
+
+#endif /* _SHARED_H_ */
+
diff --git a/MCUME_pico2/picosms/sms.c b/MCUME_pico2/picosms/sms.c
new file mode 100644
index 0000000..16afca3
--- /dev/null
+++ b/MCUME_pico2/picosms/sms.c
@@ -0,0 +1,316 @@
+#include "shared.h"
+
+/* SMS context */
+t_sms sms;
+t_input input;       /* Controller input */
+
+/* Run the virtual console emulation for one frame */
+void sms_frame(int skip_render)
+{
+    /* Take care of hard resets */
+    if(input.system & INPUT_HARD_RESET)
+    {
+        system_reset();
+    }
+
+    /* Debounce pause key */
+    if(input.system & INPUT_PAUSE)
+    {
+        if(!sms.paused)
+        {
+            sms.paused = 1;
+
+            z80_set_nmi_line(ASSERT_LINE);
+            z80_set_nmi_line(CLEAR_LINE);
+        }
+    }
+    else
+    {
+         sms.paused = 0;
+    }
+
+    if(smssnd.log) smssnd.callback(0x00);
+
+    for(vdp.line = 0; vdp.line < 262; vdp.line += 1)
+    {
+        /* Handle VDP line events */
+        vdp_run();
+
+        /* Draw the current frame */
+        if(!skip_render) render_line(vdp.line);
+
+        /* Run the Z80 for a line */
+        z80_execute(227);
+    }
+}
+
+void audio_play_sample(int16 *bufl, int16 *bufr, int length)
+{
+    length = length/2;
+
+    if(smssnd.enabled) 
+    {
+        int count;
+
+        SN76496Update(0, smssnd.psg_buffer, length, sms.psg_mask);
+        if(sms.use_fm) YM3812UpdateOne(ym3812, smssnd.fm_buffer, length);
+
+        for(count = 0; count < length; count += 1)
+        {
+            signed short left   = 0;
+            signed short right  = 0;
+            if (sms.use_fm) left = right = smssnd.fm_buffer[count];
+            left  += smssnd.psg_buffer[0][count];
+            right += smssnd.psg_buffer[1][count];
+            *bufl++ = left;
+            *bufl++ = right;
+        }
+    }
+     
+}
+
+
+
+void sms_init(void)
+{
+#if PSX
+    z80_set_context((void *)0x1F800000);
+#endif
+    cpu_reset();
+    sms_reset();
+}
+
+
+void sms_reset(void)
+{
+    memset(&input, 0, sizeof(t_input));
+
+    /* Clear SMS context */
+    memset(sms.dummy, 0, 0x2000);
+    memset(sms.ram, 0, 0x2000);
+    memset(sms.sram, 0, 0x8000);
+    sms.paused = sms.save = sms.port_3F = sms.port_F2 = sms.irq = 0x00;
+    sms.psg_mask = 0xFF;
+
+    /* Load memory maps with default values */
+    cpu_readmap[0] = 0x0000;
+    cpu_readmap[1] = 0x2000;
+    cpu_readmap[2] = 0x4000;
+    cpu_readmap[3] = 0x6000;
+    cpu_readmap[4] = 0x0000;
+    cpu_readmap[5] = 0x2000;
+    cpu_readmap[6] = sms.ram;            
+    cpu_readmap[7] = sms.ram;
+
+    cpu_writemap[0] = sms.dummy;         
+    cpu_writemap[1] = sms.dummy;
+    cpu_writemap[2] = sms.dummy;         
+    cpu_writemap[3] = sms.dummy;
+    cpu_writemap[4] = sms.dummy;         
+    cpu_writemap[5] = sms.dummy;
+    cpu_writemap[6] = sms.ram;           
+    cpu_writemap[7] = sms.ram;
+
+    sms.fcr[0] = 0x00;
+    sms.fcr[1] = 0x00;
+    sms.fcr[2] = 0x01;
+    sms.fcr[3] = 0x00;
+}
+
+
+/* Reset Z80 emulator */
+void cpu_reset(void)
+{
+    z80_reset(0);
+    z80_set_irq_callback(sms_irq_callback);
+}
+
+
+/* Write to memory */
+void cpu_writemem16(int address, int data)
+{
+    cpu_writemap[(address >> 13)][(address & 0x1FFF)] = data;
+    if(address >= 0xFFFC) sms_mapper_w(address & 3, data);
+}
+
+
+/* Write to an I/O port */
+void cpu_writeport(int port, int data)
+{
+    switch(port & 0xFF)
+    {
+        case 0x01: /* GG SIO */
+        case 0x02:
+        case 0x03:
+        case 0x04:
+        case 0x05:
+            break;
+
+        case 0x06: /* GG STEREO */
+            if(smssnd.log) {
+            smssnd.callback(0x04);
+            smssnd.callback(data);
+            }
+            sms.psg_mask = (data & 0xFF);
+            break;
+
+        case 0x7E: /* SN76489 PSG */
+        case 0x7F:
+            if(smssnd.log) {
+            smssnd.callback(0x03);
+            smssnd.callback(data);
+            }
+            if(smssnd.enabled) SN76496Write(0, data);
+            break;
+
+        case 0xBE: /* VDP DATA */
+            vdp_data_w(data);
+            break;
+
+        case 0xBD: /* VDP CTRL */ 
+        case 0xBF:
+            vdp_ctrl_w(data);
+            break;
+
+        case 0xF0: /* YM2413 */
+        case 0xF1:
+            if(smssnd.log) {
+            smssnd.callback((port & 1) ? 0x06 : 0x05);
+            smssnd.callback(data);
+            }
+            if(smssnd.enabled && sms.use_fm) ym2413_write(0, port & 1, data);
+            break;
+
+        case 0xF2: /* YM2413 DETECT */
+            if(sms.use_fm) sms.port_F2 = (data & 1);
+            break;
+
+        case 0x3F: /* TERRITORY CTRL. */
+             sms.port_3F = ((data & 0x80) | (data & 0x20) << 1) & 0xC0;
+            if(sms.country == TYPE_DOMESTIC) sms.port_3F ^= 0xC0;
+            break;
+    }
+}
+
+
+/* Read from an I/O port */
+int cpu_readport(int port)
+{
+    byte temp = 0xFF;
+
+    switch(port & 0xFF)
+    {
+        case 0x01: /* GG SIO */
+        case 0x02:
+        case 0x03:
+        case 0x04:
+        case 0x05:
+            return (0x00);
+    
+        case 0x7E: /* V COUNTER */
+            return (vdp_vcounter_r());
+            break;
+    
+        case 0x7F: /* H COUNTER */
+            return (vdp_hcounter_r());
+            break;
+    
+        case 0x00: /* INPUT #2 */
+            temp = 0xFF;
+            if(input.system & INPUT_START) temp &= ~0x80;
+            if(sms.country == TYPE_DOMESTIC) temp &= ~0x40;
+            return (temp);
+    
+        case 0xC0: /* INPUT #0 */  
+        case 0xDC:
+            temp = 0xFF;
+            if(input.pad[0] & INPUT_UP)      temp &= ~0x01;
+            if(input.pad[0] & INPUT_DOWN)    temp &= ~0x02;
+            if(input.pad[0] & INPUT_LEFT)    temp &= ~0x04;
+            if(input.pad[0] & INPUT_RIGHT)   temp &= ~0x08;
+            if(input.pad[0] & INPUT_BUTTON2) temp &= ~0x10;
+            if(input.pad[0] & INPUT_BUTTON1) temp &= ~0x20;
+            if(input.pad[1] & INPUT_UP)      temp &= ~0x40;
+            if(input.pad[1] & INPUT_DOWN)    temp &= ~0x80;
+            return (temp);
+    
+        case 0xC1: /* INPUT #1 */
+        case 0xDD:
+            temp = 0xFF;
+            if(input.pad[1] & INPUT_LEFT)    temp &= ~0x01;
+            if(input.pad[1] & INPUT_RIGHT)   temp &= ~0x02;
+            if(input.pad[1] & INPUT_BUTTON2) temp &= ~0x04;
+            if(input.pad[1] & INPUT_BUTTON1) temp &= ~0x08;
+            if(input.system & INPUT_SOFT_RESET) temp &= ~0x10;
+            return ((temp & 0x3F) | (sms.port_3F & 0xC0));
+
+        case 0xBE: /* VDP DATA */
+            return (vdp_data_r());
+    
+        case 0xBD:
+        case 0xBF: /* VDP CTRL */
+            return (vdp_ctrl_r());
+
+        case 0xF2: /* YM2413 DETECT */
+            if(sms.use_fm) return (sms.port_F2);
+            break;
+    }
+    return (0xFF);     
+}
+
+
+void sms_mapper_w(int address, int data)
+{
+    /* Calculate ROM page index */
+    byte page = (data % cart.pages);
+
+    /* Save frame control register data */
+    sms.fcr[address] = data;
+
+    switch(address)
+    {
+        case 0:
+            if(data & 8)
+            {
+                sms.save = 1;
+                /* Page in ROM */
+                cpu_readmap[4]  = &sms.sram[(data & 4) ? 0x4000 : 0x0000];
+                cpu_readmap[5]  = &sms.sram[(data & 4) ? 0x6000 : 0x2000];
+                cpu_writemap[4] = &sms.sram[(data & 4) ? 0x4000 : 0x0000];
+                cpu_writemap[5] = &sms.sram[(data & 4) ? 0x6000 : 0x2000];
+            }
+            else
+            {
+                /* Page in RAM */
+                cpu_readmap[4]  = ((sms.fcr[3] % cart.pages) << 14) + 0x0000;
+                cpu_readmap[5]  = ((sms.fcr[3] % cart.pages) << 14) + 0x2000;
+                cpu_writemap[4] = sms.dummy;
+                cpu_writemap[5] = sms.dummy;
+            }
+            break;
+
+        case 1:
+            cpu_readmap[0] = (page << 14) + 0x0000;
+            cpu_readmap[1] = (page << 14) + 0x2000;
+            break;
+
+        case 2:
+            cpu_readmap[2] = (page << 14) + 0x0000;
+            cpu_readmap[3] = (page << 14) + 0x2000;
+            break;
+
+        case 3:
+            if(!(sms.fcr[0] & 0x08))
+            {
+                cpu_readmap[4] = (page << 14) + 0x0000;
+                cpu_readmap[5] = (page << 14) + 0x2000;
+            }
+            break;
+    }
+}
+
+
+int sms_irq_callback(int param)
+{
+    return (0xFF);
+}
diff --git a/MCUME_pico2/picosms/sms.h b/MCUME_pico2/picosms/sms.h
new file mode 100644
index 0000000..c938447
--- /dev/null
+++ b/MCUME_pico2/picosms/sms.h
@@ -0,0 +1,36 @@
+
+#ifndef _SMS_H_
+#define _SMS_H_
+
+#define TYPE_OVERSEAS   (0)
+#define TYPE_DOMESTIC   (1)
+
+/* SMS context */
+typedef struct
+{
+    byte dummy[0x2000];
+    byte ram[0x2000];
+    byte sram[0x8000];
+    byte fcr[4];
+    byte paused;
+    byte save;
+    byte country;
+    byte port_3F;
+    byte port_F2;
+    byte use_fm;
+    byte irq;
+    byte psg_mask;
+}t_sms;
+
+/* Global data */
+extern t_sms sms;
+
+/* Function prototypes */
+void sms_frame(int skip_render);
+void sms_init(void);
+void sms_reset(void);
+int  sms_irq_callback(int param);
+void sms_mapper_w(int address, int data);
+void cpu_reset(void);
+
+#endif /* _SMS_H_ */
diff --git a/MCUME_pico2/picosms/smslut.h b/MCUME_pico2/picosms/smslut.h
new file mode 100644
index 0000000..6ef2da7
--- /dev/null
+++ b/MCUME_pico2/picosms/smslut.h
@@ -0,0 +1,4099 @@
+
+const uint8 lut[65536] = {
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x01,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x02,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x03,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
+0x03,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
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+};
diff --git a/MCUME_pico2/picosms/sn76496.c b/MCUME_pico2/picosms/sn76496.c
new file mode 100644
index 0000000..6966a3a
--- /dev/null
+++ b/MCUME_pico2/picosms/sn76496.c
@@ -0,0 +1,245 @@
+#include "shared.h"
+
+#define MAX_OUTPUT  0x7FFF
+#define STEP        0x10000
+#define FB_WNOISE   0x12000
+#define FB_PNOISE   0x08000
+#define NG_PRESET   0x0F35
+
+t_SN76496 sn[MAX_76496];
+
+void SN76496Write(int chip,int data)
+{
+    t_SN76496 *R = &sn[chip];
+
+
+	if (data & 0x80)
+	{
+		int r = (data & 0x70) >> 4;
+		int c = r/2;
+
+		R->LastRegister = r;
+		R->Register[r] = (R->Register[r] & 0x3f0) | (data & 0x0f);
+		switch (r)
+		{
+			case 0:	/* tone 0 : frequency */
+			case 2:	/* tone 1 : frequency */
+			case 4:	/* tone 2 : frequency */
+				R->Period[c] = R->UpdateStep * R->Register[r];
+				if (R->Period[c] == 0) R->Period[c] = R->UpdateStep;
+				if (r == 4)
+				{
+					/* update noise shift frequency */
+					if ((R->Register[6] & 0x03) == 0x03)
+						R->Period[3] = 2 * R->Period[2];
+				}
+				break;
+			case 1:	/* tone 0 : volume */
+			case 3:	/* tone 1 : volume */
+			case 5:	/* tone 2 : volume */
+			case 7:	/* noise  : volume */
+				R->Volume[c] = R->VolTable[data & 0x0f];
+				break;
+			case 6:	/* noise  : frequency, mode */
+				{
+					int n = R->Register[6];
+					R->NoiseFB = (n & 4) ? FB_WNOISE : FB_PNOISE;
+					n &= 3;
+					/* N/512,N/1024,N/2048,Tone #3 output */
+					R->Period[3] = (n == 3) ? 2 * R->Period[2] : (R->UpdateStep << (5+n));
+
+					/* reset noise shifter */
+					R->RNG = NG_PRESET;
+					R->Output[3] = R->RNG & 1;
+				}
+				break;
+		}
+	}
+	else
+	{
+		int r = R->LastRegister;
+		int c = r/2;
+
+		switch (r)
+		{
+			case 0:	/* tone 0 : frequency */
+			case 2:	/* tone 1 : frequency */
+			case 4:	/* tone 2 : frequency */
+				R->Register[r] = (R->Register[r] & 0x0f) | ((data & 0x3f) << 4);
+				R->Period[c] = R->UpdateStep * R->Register[r];
+				if (R->Period[c] == 0) R->Period[c] = R->UpdateStep;
+				if (r == 4)
+				{
+					/* update noise shift frequency */
+					if ((R->Register[6] & 0x03) == 0x03)
+						R->Period[3] = 2 * R->Period[2];
+				}
+				break;
+		}
+	}
+}
+
+
+void SN76496Update(int chip,INT16 *buffer[2],int length, unsigned char mask)
+{
+    int i, j;
+    int buffer_index = 0;
+    t_SN76496 *R = &sn[chip];
+
+	/* If the volume is 0, increase the counter */
+	for (i = 0;i < 4;i++)
+	{
+		if (R->Volume[i] == 0)
+		{
+			/* note that I do count += length, NOT count = length + 1. You might think */
+			/* it's the same since the volume is 0, but doing the latter could cause */
+			/* interferencies when the program is rapidly modulating the volume. */
+			if (R->Count[i] <= length*STEP) R->Count[i] += length*STEP;
+		}
+	}
+
+	while (length > 0)
+	{
+		int vol[4];
+        unsigned int out[2];
+		int left;
+
+
+		/* vol[] keeps track of how long each square wave stays */
+		/* in the 1 position during the sample period. */
+		vol[0] = vol[1] = vol[2] = vol[3] = 0;
+
+		for (i = 0;i < 3;i++)
+		{
+			if (R->Output[i]) vol[i] += R->Count[i];
+			R->Count[i] -= STEP;
+			/* Period[i] is the half period of the square wave. Here, in each */
+			/* loop I add Period[i] twice, so that at the end of the loop the */
+			/* square wave is in the same status (0 or 1) it was at the start. */
+			/* vol[i] is also incremented by Period[i], since the wave has been 1 */
+			/* exactly half of the time, regardless of the initial position. */
+			/* If we exit the loop in the middle, Output[i] has to be inverted */
+			/* and vol[i] incremented only if the exit status of the square */
+			/* wave is 1. */
+			while (R->Count[i] <= 0)
+			{
+				R->Count[i] += R->Period[i];
+				if (R->Count[i] > 0)
+				{
+					R->Output[i] ^= 1;
+					if (R->Output[i]) vol[i] += R->Period[i];
+					break;
+				}
+				R->Count[i] += R->Period[i];
+				vol[i] += R->Period[i];
+			}
+			if (R->Output[i]) vol[i] -= R->Count[i];
+		}
+
+		left = STEP;
+		do
+		{
+			int nextevent;
+
+
+			if (R->Count[3] < left) nextevent = R->Count[3];
+			else nextevent = left;
+
+			if (R->Output[3]) vol[3] += R->Count[3];
+			R->Count[3] -= nextevent;
+			if (R->Count[3] <= 0)
+			{
+				if (R->RNG & 1) R->RNG ^= R->NoiseFB;
+				R->RNG >>= 1;
+				R->Output[3] = R->RNG & 1;
+				R->Count[3] += R->Period[3];
+				if (R->Output[3]) vol[3] += R->Period[3];
+			}
+			if (R->Output[3]) vol[3] -= R->Count[3];
+
+			left -= nextevent;
+		} while (left > 0);
+
+        out[0] = out[1] = 0;
+        for(j = 0; j < 4; j += 1)
+        {
+            int k = vol[j] * R->Volume[j];
+            if(mask & (1 << (4+j))) out[0] += k;
+            if(mask & (1 << (0+j))) out[1] += k;
+        }
+
+        if(out[0] > MAX_OUTPUT * STEP) out[0] = MAX_OUTPUT * STEP;
+        if(out[1] > MAX_OUTPUT * STEP) out[1] = MAX_OUTPUT * STEP;
+        buffer[0][buffer_index] = out[0] / STEP;
+        buffer[1][buffer_index] = out[1] / STEP;
+
+        /* Next sample set */
+        buffer_index += 1;
+
+		length--;
+	}
+}
+
+
+
+void SN76496_set_clock(int chip,int clock)
+{
+    t_SN76496 *R = &sn[chip];
+
+	R->UpdateStep = ((double)STEP * R->SampleRate * 16) / clock;
+}
+
+
+
+void SN76496_set_gain(int chip,int gain)
+{
+    t_SN76496 *R = &sn[chip];
+	int i;
+	double out;
+
+	gain &= 0xff;
+	out = MAX_OUTPUT / 3;
+	while (gain-- > 0)
+        out *= 1.023292992;
+
+	for (i = 0;i < 15;i++)
+	{
+		if (out > MAX_OUTPUT / 3) R->VolTable[i] = MAX_OUTPUT / 3;
+		else R->VolTable[i] = out;
+        out /= 1.258925412;
+	}
+
+	R->VolTable[15] = 0;
+}
+
+
+
+int SN76496_init(int chip,int clock,int volume,int sample_rate)
+{
+	int i;
+    t_SN76496 *R = &sn[chip];
+
+	R->SampleRate = sample_rate;
+	SN76496_set_clock(chip,clock);
+
+	for (i = 0;i < 4;i++) R->Volume[i] = 0;
+
+	R->LastRegister = 0;
+	for (i = 0;i < 8;i+=2)
+	{
+		R->Register[i] = 0;
+		R->Register[i + 1] = 0x0f;	/* volume = 0 */
+	}
+
+	for (i = 0;i < 4;i++)
+	{
+		R->Output[i] = 0;
+		R->Period[i] = R->Count[i] = R->UpdateStep;
+	}
+	R->RNG = NG_PRESET;
+	R->Output[3] = R->RNG & 1;
+
+    SN76496_set_gain(0, (volume >> 8) & 0xFF);
+
+	return 0;
+}
diff --git a/MCUME_pico2/picosms/sn76496.h b/MCUME_pico2/picosms/sn76496.h
new file mode 100644
index 0000000..daff3c9
--- /dev/null
+++ b/MCUME_pico2/picosms/sn76496.h
@@ -0,0 +1,30 @@
+#ifndef SN76496_H
+#define SN76496_H
+
+#define MAX_76496 4
+
+typedef struct
+{
+	int Channel;
+	int SampleRate;
+	unsigned int UpdateStep;
+    int VolTable[16];
+    int Register[8];
+    int LastRegister;
+    int Volume[4];
+    unsigned int RNG;
+    int NoiseFB;
+	int Period[4];
+	int Count[4];
+	int Output[4];
+}t_SN76496;
+
+extern t_SN76496 sn[MAX_76496];
+
+void SN76496Write(int chip,int data);
+void SN76496Update(int chip, signed short int *buffer[2],int length,unsigned char mask);
+void SN76496_set_clock(int chip,int clock);
+void SN76496_set_gain(int chip,int gain);
+int SN76496_init(int chip,int clock,int volume,int sample_rate);
+
+#endif
diff --git a/MCUME_pico2/picosms/system.c b/MCUME_pico2/picosms/system.c
new file mode 100644
index 0000000..5809abc
--- /dev/null
+++ b/MCUME_pico2/picosms/system.c
@@ -0,0 +1,231 @@
+/*
+    Copyright (C) 1998, 1999, 2000  Charles Mac Donald
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include "shared.h"
+
+
+t_bitmap sbitmap;
+t_cart cart;                
+t_snd smssnd;
+static t_input minput;
+FM_OPL *ym3812;
+
+
+void system_init(int rate)
+{
+    /* Initialize the VDP emulation */
+    vdp_init();
+
+    /* Initialize the SMS emulation */
+    sms_init();
+
+    /* Initialize the look-up tables and related data */
+    render_init();
+
+    /* Enable sound emulation if the sample rate was specified */
+    audio_init(rate);
+
+    /* Don't save SRAM by default */
+    sms.save = 0;
+
+    /* Clear emulated button state */
+    memset(&minput, 0, sizeof(t_input));
+}
+
+
+void audio_init(int rate)
+{
+    /* Clear sound context */
+    memset(&smssnd, 0, sizeof(t_snd));
+
+    /* Reset logging data */
+    smssnd.log = 0;
+    smssnd.callback = NULL;
+
+    /* Oops.. sound is disabled */
+    if(!rate) return;
+
+    /* Calculate buffer size in samples */
+    smssnd.bufsize = (rate / 50);
+
+    /* YM3812/YM2413 sound stream */
+    smssnd.fm_buffer = (signed short int *)emu_Malloc(smssnd.bufsize * 2);
+    if(!smssnd.fm_buffer) return;
+
+    /* SN76489 sound stream */
+    smssnd.psg_buffer[0] = (signed short int *)emu_Malloc(smssnd.bufsize * 2);
+    smssnd.psg_buffer[1] = (signed short int *)emu_Malloc(smssnd.bufsize * 2);
+    if(!smssnd.psg_buffer[0] || !smssnd.psg_buffer[1]) return;
+
+    /* Set up SN76489 emulation */
+    SN76496_init(0, MASTER_CLOCK, 255, rate);
+
+    /* Set up YM3812 emulation */
+    ym3812 = OPLCreate(OPL_TYPE_YM3812, MASTER_CLOCK, rate);
+    if(!ym3812) return;
+
+    /* Set up YM2413 emulation */
+    ym2413_init(1);
+
+    /* Inform other functions that we can use sound */
+    smssnd.enabled = 1;
+}
+
+
+void system_shutdown(void)
+{
+    if(smssnd.enabled) OPLDestroy(ym3812);
+}
+
+
+void system_reset(void)
+{
+    cpu_reset();
+    vdp_reset();
+    sms_reset();
+    render_reset();
+//    system_load_sram();
+    if(smssnd.enabled)
+    {
+        OPLResetChip(ym3812);
+        ym2413_reset(0);
+    }
+}
+
+
+void system_save_state(void *fd)
+{
+    /* Save VDP context */
+    fwrite(&vdp, sizeof(t_vdp), 1, fd);
+
+    /* Save SMS context */
+    fwrite(&sms, sizeof(t_sms), 1, fd);
+
+    /* Save Z80 context */
+    fwrite(Z80_Context, sizeof(Z80_Regs), 1, fd);
+    fwrite(&after_EI, sizeof(int), 1, fd);
+
+    /* Save YM2413 registers */
+    fwrite(&ym2413[0].reg[0], 0x40, 1, fd);
+
+    /* Save SN76489 context */
+    fwrite(&sn[0], sizeof(t_SN76496), 1, fd);
+}
+
+
+void system_load_state(void *fd)
+{
+    int i;
+    byte reg[0x40];
+
+    /* Initialize everything */
+    cpu_reset();
+    system_reset();
+
+    /* Load VDP context */
+    fread(&vdp, sizeof(t_vdp), 1, fd);
+
+    /* Load SMS context */
+    fread(&sms, sizeof(t_sms), 1, fd);
+
+    /* Load Z80 context */
+    fread(Z80_Context, sizeof(Z80_Regs), 1, fd);
+    fread(&after_EI, sizeof(int), 1, fd);
+
+    /* Load YM2413 registers */
+    fread(reg, 0x40, 1, fd);
+
+    /* Load SN76489 context */
+    fread(&sn[0], sizeof(t_SN76496), 1, fd);
+
+    /* Restore callbacks */
+    z80_set_irq_callback(sms_irq_callback);
+
+    cpu_readmap[0] = 0x0000; /* 0000-3FFF */
+    cpu_readmap[1] = 0x2000;
+    cpu_readmap[2] = 0x4000; /* 4000-7FFF */
+    cpu_readmap[3] = 0x6000;
+    cpu_readmap[4] = 0x0000; /* 0000-3FFF */
+    cpu_readmap[5] = 0x2000;
+    cpu_readmap[6] = sms.ram;
+    cpu_readmap[7] = sms.ram;
+
+    cpu_writemap[0] = sms.dummy;
+    cpu_writemap[1] = sms.dummy;
+    cpu_writemap[2] = sms.dummy;         
+    cpu_writemap[3] = sms.dummy;
+    cpu_writemap[4] = sms.dummy;         
+    cpu_writemap[5] = sms.dummy;
+    cpu_writemap[6] = sms.ram;           
+    cpu_writemap[7] = sms.ram;
+
+    sms_mapper_w(3, sms.fcr[3]);
+    sms_mapper_w(2, sms.fcr[2]);
+    sms_mapper_w(1, sms.fcr[1]);
+    sms_mapper_w(0, sms.fcr[0]);
+
+    /* Force full pattern cache update */
+    sis_vram_dirty = 1;
+    memset(svram_dirty, 1, 0x200);
+
+    /* Restore palette */
+    for(i = 0; i < PALETTE_SIZE; i += 1)
+        palette_sync(i);
+
+    /* Restore sound state */
+    if(smssnd.enabled)
+    {
+        /* Restore YM2413 emulation */
+        OPLResetChip(ym3812);
+
+        /* Clear YM2413 context */
+        ym2413_reset(0);
+
+        /* Restore rhythm enable first */
+        ym2413_write(0, 0, 0x0E);
+        ym2413_write(0, 1, reg[0x0E]);
+
+        /* User instrument settings */
+        for(i = 0x00; i <= 0x07; i += 1)
+        {
+            ym2413_write(0, 0, i);
+            ym2413_write(0, 1, reg[i]);
+        }
+
+        /* Channel frequency */
+        for(i = 0x10; i <= 0x18; i += 1)
+        {
+            ym2413_write(0, 0, i);
+            ym2413_write(0, 1, reg[i]);
+        }
+
+        /* Channel frequency + ctrl. */
+        for(i = 0x20; i <= 0x28; i += 1)
+        {
+            ym2413_write(0, 0, i);
+            ym2413_write(0, 1, reg[i]);
+        }
+
+        /* Instrument and volume settings  */
+        for(i = 0x30; i <= 0x38; i += 1)
+        {
+            ym2413_write(0, 0, i);
+            ym2413_write(0, 1, reg[i]);
+        }
+    }
+}
diff --git a/MCUME_pico2/picosms/system.h b/MCUME_pico2/picosms/system.h
new file mode 100644
index 0000000..6b12d7a
--- /dev/null
+++ b/MCUME_pico2/picosms/system.h
@@ -0,0 +1,92 @@
+
+#ifndef _SYSTEM_H_
+#define _SYSTEM_H_
+
+#define PALETTE_SIZE        (0x20)
+
+/* Console / cartridge types */
+#define TYPE_SMS            (0)
+#define TYPE_GG             (1)
+
+#define IS_GG               (cart.type == TYPE_GG)
+#define IS_SMS              (cart.type == TYPE_SMS)
+
+/* Macro to get offset to actual display within bitmap */
+#define BMP_X_OFFSET        ((cart.type == TYPE_GG) ? 48 : 0)
+#define BMP_Y_OFFSET        ((cart.type == TYPE_GG) ? 24 : 0)
+
+#define BMP_WIDTH           (IS_GG ? 160 : 256)
+#define BMP_HEIGHT          (IS_GG ? 144 : 192)
+
+/* Mask for removing unused pixel data */
+#define PIXEL_MASK          (0x1F)
+
+/* These can be used for 'input.pad[]' */
+#define INPUT_UP          (0x00000001)
+#define INPUT_DOWN        (0x00000002)
+#define INPUT_LEFT        (0x00000004)
+#define INPUT_RIGHT       (0x00000008)
+#define INPUT_BUTTON2     (0x00000010)
+#define INPUT_BUTTON1     (0x00000020)
+
+/* These can be used for 'input.system' */
+#define INPUT_START       (0x00000001)    /* Game Gear only */    
+#define INPUT_PAUSE       (0x00000002)    /* Master System only */
+#define INPUT_SOFT_RESET  (0x00000004)    /* Master System only */
+#define INPUT_HARD_RESET  (0x00000008)    /* Works for either console type */
+
+/* User input structure */
+typedef struct
+{
+    int pad[2];
+    int system;
+}t_input;
+
+/* Sound emulation structure */
+typedef struct
+{
+    int enabled;
+    int bufsize;
+    signed short *fm_buffer;        /* internal use only */
+    signed short *psg_buffer[2];    /* internal use only */
+    int log;
+    void (*callback)(int data);
+}t_snd;
+
+/* Game image structure */
+typedef struct
+{
+    //byte *rom;
+    byte pages;
+    byte type;
+}t_cart;
+
+/* Bitmap structure */
+typedef struct
+{
+    struct
+    {
+        byte color[32][3];
+        byte dirty[32];
+        byte update;
+    }pal;
+}t_bitmap;
+
+/* Global variables */
+extern t_bitmap sbitmap;    /* Display bitmap */
+extern t_snd smssnd;           /* Sound streams */
+extern t_cart cart;         /* Game cartridge data */
+extern t_input input;       /* Controller input */
+extern FM_OPL *ym3812;      /* YM3812 emulator data */
+
+/* Function prototypes */
+void system_init(int rate);
+void system_shutdown(void);
+void system_reset(void);
+void system_load_sram(void);
+void system_save_state(void *fd);
+void system_load_state(void *fd);
+void audio_init(int rate);
+void audio_play_sample(int16 *bufl, int16 *bufr, int length);
+
+#endif /* _SYSTEM_H_ */
diff --git a/MCUME_pico2/picosms/vdp.c b/MCUME_pico2/picosms/vdp.c
new file mode 100644
index 0000000..ac056a7
--- /dev/null
+++ b/MCUME_pico2/picosms/vdp.c
@@ -0,0 +1,297 @@
+#include "shared.h"
+
+
+/* VDP context */
+t_vdp vdp;
+
+
+/* Return values from the V counter */
+byte vcnt[0x200] =
+{
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F,
+    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
+    0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F,
+    0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F,
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F,
+    0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
+    0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F,
+    0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF,
+    0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF,
+    0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF,
+    0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA,
+                                  0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF,
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+};
+
+/* Return values from the H counter */
+byte hcnt[0x200] =
+{
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F,
+    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
+    0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F,
+    0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F,
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F,
+    0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
+    0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F,
+    0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF,
+    0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF,
+    0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF,
+    0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF,
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9,
+                      0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F,
+    0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF,
+    0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF,
+    0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF,
+    0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF,
+    0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF,
+};
+
+
+/*--------------------------------------------------------------------------*/
+
+
+/* Initialize VDP emulation */
+void vdp_init(void)
+{
+    vdp_reset();
+}
+
+
+/* Reset VDP emulation */
+void vdp_reset(void)
+{
+    memset(&vdp, 0, sizeof(t_vdp));
+    vdp.limit = 1;
+}
+
+
+/* Write data to the VDP's control port */
+void vdp_ctrl_w(int data)
+{
+    /* Waiting for the reset of the command? */
+    if(vdp.pending == 0)
+    {
+        /* Save data for later */
+        vdp.latch = data;
+
+        /* Set pending flag */
+        vdp.pending = 1;
+    }
+    else
+    {
+        /* Clear pending flag */
+        vdp.pending = 0;
+
+        /* VDP register write */
+        if((data & 0xF0) == 0x80)
+        {
+            int r = (data & 0x0F);
+            int d = vdp.latch;
+
+            /* Store register data */
+            vdp.reg[r] = d;
+
+            /* Update table addresses */
+            vdp.ntab = (vdp.reg[2] << 10) & 0x3800;
+            vdp.satb = (vdp.reg[5] << 7) & 0x3F00;
+
+            vdp.addr = vdp.code = 0;
+        }
+        else
+        {
+            /* Extract code bits */
+            vdp.code = (data >> 6) & 3;
+
+            /* Make address */
+            vdp.addr = (data << 8 | vdp.latch);
+
+            /* Read VRAM for code 0x00 */
+            if(vdp.code == 0x00)
+            {
+                /* Load buffer with current VRAM byte */
+                vdp.buffer = vdp.vram[(vdp.addr & 0x3FFF)];
+
+                /* Bump address */
+                vdp.addr += 1;
+            }
+        }
+    }
+}
+
+
+/* Read the status flags */
+int vdp_ctrl_r(void)
+{
+    /* Save the status flags */
+    byte temp = vdp.status;
+
+    /* Clear pending flag */
+    vdp.pending = 0;
+
+    /* Clear pending interrupt and sprite collision flags */
+    vdp.status &= ~(0x80 | 0x40 | 0x20);
+
+    /* Lower the IRQ line */
+    if(sms.irq == 1)
+    {
+        sms.irq = 0;
+        z80_set_irq_line(0, CLEAR_LINE);
+    }
+
+    /* Return the old status flags */
+    return (temp);
+}
+
+
+/* Write data to the VDP's data port */
+void vdp_data_w(int data)
+{
+    int index;
+
+    /* Clear the pending flag */
+    vdp.pending = 0;
+
+    switch(vdp.code)
+    {
+        case 0: /* VRAM write */
+        case 1: /* VRAM write */
+        case 2: /* VRAM write */
+
+            /* Get current address in VRAM */
+            index = (vdp.addr & 0x3FFF);
+
+            /* Only update if data is new */
+            if(data != vdp.vram[index])
+            {
+                /* Store VRAM byte */
+                vdp.vram[index] = data;
+
+                /* Mark patterns as dirty */
+                svram_dirty[(index >> 5)] = sis_vram_dirty = 1;
+            }
+            break;
+
+        case 3: /* CRAM write */
+            if(cart.type == TYPE_GG)
+            {
+                index = (vdp.addr & 0x3F);
+                if(data != vdp.cram[index])
+                {
+                    vdp.cram[index] = data;
+                    index = (vdp.addr >> 1) & 0x1F;
+                    palette_sync(index);
+                }
+            }
+            else
+            {
+                index = (vdp.addr & 0x1F);
+                if(data != vdp.cram[index])
+                {
+                    vdp.cram[index] = data;
+                    palette_sync(index);
+                }
+            }
+            break;
+    }
+
+    /* Bump the VRAM address */
+    vdp.addr += 1;
+}
+
+
+/* Read data from the VDP's data port */
+int vdp_data_r(void)
+{
+    byte temp = 0;
+
+    /* Clear the pending flag */
+    vdp.pending = 0;
+
+    switch(vdp.code)
+    {
+        case 0: /* VRAM read */
+        case 1: /* VRAM read */
+        case 2: /* VRAM read */
+
+            /* Return the buffered value */
+            temp = vdp.buffer;
+
+            /* Get data from the current VRAM address */
+            vdp.buffer = vdp.vram[(vdp.addr & 0x3FFF)];
+            break;
+
+        case 3: /* Undefined */
+            /* Return 'no value' data */
+            temp = 0xFF;
+            break;
+    }
+
+    /* Bump address register */
+    vdp.addr += 1;
+    return (temp);
+}
+
+
+/* Process frame events */
+void vdp_run(void)
+{
+    if(vdp.line <= 0xC0)
+    {
+        if(vdp.line == 0xC0)
+        {
+            vdp.status |= 0x80;
+        }
+
+        if(vdp.line == 0)
+        {
+            vdp.left = vdp.reg[10];
+        }
+
+        if(vdp.left == 0)
+        {
+            vdp.left = vdp.reg[10];
+            vdp.status |= 0x40;
+        }
+        else
+        {
+            vdp.left -= 1;
+        }
+
+        if((vdp.status & 0x40) && (vdp.reg[0] & 0x10))
+        {
+            sms.irq = 1;
+            z80_set_irq_line(0, ASSERT_LINE);
+        }
+    }
+    else
+    {
+        vdp.left = vdp.reg[10];
+
+        if((vdp.line < 0xE0) && (vdp.status & 0x80) && (vdp.reg[1] & 0x20))
+        {
+            sms.irq = 1;
+            z80_set_irq_line(0, ASSERT_LINE);
+        }
+    }
+}
+
+
+byte vdp_vcounter_r(void)
+{
+    return (vcnt[(vdp.line & 0x1FF)]);
+}
+
+
+byte vdp_hcounter_r(void)
+{
+    int pixel = (((z80_ICount % CYCLES_PER_LINE) / 4) * 3) * 2;
+    return (hcnt[((pixel >> 1) & 0x1FF)]);
+}
diff --git a/MCUME_pico2/picosms/vdp.h b/MCUME_pico2/picosms/vdp.h
new file mode 100644
index 0000000..4e633e8
--- /dev/null
+++ b/MCUME_pico2/picosms/vdp.h
@@ -0,0 +1,45 @@
+
+#ifndef _VDP_H_
+#define _VDP_H_
+
+/* Display timing (NTSC) */
+#define MASTER_CLOCK        (3579545)
+#define LINES_PER_FRAME     (262)
+#define FRAMES_PER_SECOND   (60)
+#define CYCLES_PER_LINE     ((MASTER_CLOCK / FRAMES_PER_SECOND) / LINES_PER_FRAME)
+
+/* VDP context */
+typedef struct
+{
+    byte vram[0x4000];
+    byte cram[0x40]; 
+    byte reg[0x10];  
+    byte status;     
+    byte latch;      
+    byte pending;    
+    byte buffer;     
+    byte code;       
+    UINT16 addr;       
+    int ntab;        
+    int satb;
+    int line;
+    int left;
+    byte limit;
+}t_vdp;
+
+/* Global data */
+extern t_vdp vdp;
+
+/* Function prototypes */
+void vdp_init(void);
+void vdp_reset(void);
+void vdp_ctrl_w(int data);
+int vdp_ctrl_r(void);
+byte vdp_vcounter_r(void);
+byte vdp_hcounter_r(void);
+void vdp_data_w(int data);
+int vdp_data_r(void);
+void vdp_run(void);
+
+#endif /* _VDP_H_ */
+
diff --git a/MCUME_pico2/picosms/ym2413.c b/MCUME_pico2/picosms/ym2413.c
new file mode 100644
index 0000000..bd9af27
--- /dev/null
+++ b/MCUME_pico2/picosms/ym2413.c
@@ -0,0 +1,397 @@
+/*
+    Copyright (C) 2000  Charles Mac Donald
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    YM2413 (OPLL) emulator
+    by Charles Mac Donald
+    E-mail: cgfm2@hooked.net
+    WWW: http://cgfm2.emuviews.com
+
+    Change log:
+
+    [061300]
+    - Fixed bug where channel numbers larger than 9 could be written to
+      register groups $10-18, $20-28, $30-38.
+
+    [060800]
+    - Now the YM2413 chip number is passed to the OPL_WRITE macro,
+      and the user instrument data is stored in the YM2413 context,
+      both for multiple YM2413 emulation.
+
+    [060100]
+    - Added alternate instrument table taken from Allegro's 'fm_inst.h'.
+    - Changed source so it can compile seperately from SMS Plus.
+    - Added 'ym2413_reset' function and changed ym2413_init.
+    
+    Known issues:
+
+    - The sustain on/off flag (bit 5 of register group $20-28) is not
+      emulated. According to the manual, the release rate is set to
+      five when this bit is set.
+
+    - The table of fixed instrument values probably need to be compared
+      against a real YM2413, so they can be hand-tuned.
+
+    - The rhythm instruments sound good, but are too loud.
+      The same settings are used for channels 7, 8, 9, which can't be right.
+
+    I based the YM2413 emulation on the following documents. If you want
+    to improve it or make changes, I'd advise reading the following:
+
+    - Yamaha's YMF-272 (OPL-3) programmer's manual. (ymf272.pdf)
+      (Has useful table of how the operators map to YM3812 registers)
+
+    - Yamaha's YM2413 programmer's manual. (ym2413.lzh)
+
+    - Vladimir Arnost's OPL-3 programmer's guide. (opl3.txt)
+      (Explains operator allocation in rhythm mode)
+
+    - The YM2413 emulation from MAME. (ym2413.c/2413intf.h)
+*/
+
+#include "shared.h"
+
+/* You can replace this to output to another YM3812 emulator
+   or a perhaps a real OPL-2/OPL-3 sound chip */
+#if USE_ADLIB
+#define OPL_WRITE(c,r,d)  { outp(0x388+c*2, r); outp(0x389+c*2, d); }
+#else
+#define OPL_WRITE(c,r,d)  OPLWriteReg(ym3812, r, d)
+#endif
+
+/* YM2413 chip contexts */
+t_ym2413 ym2413[MAX_YM2413];
+
+/* Fixed instrument settings, from MAME's YM2413 emulation */
+/* This might need some tweaking... */
+unsigned char table[16][11] =
+{
+   /*   20    23    40    43    60    63    80    83    E0    E3    C0 */
+    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+#if 1 /* Instrument settings from MAME */
+    { 0x01, 0x22, 0x23, 0x07, 0xF0, 0xF0, 0x07, 0x18, 0x00, 0x00, 0x00 },
+    { 0x23, 0x01, 0x68, 0x05, 0xF2, 0x74, 0x6C, 0x89, 0x00, 0x00, 0x00 },
+    { 0x13, 0x11, 0x25, 0x00, 0xD2, 0xB2, 0xF4, 0xF4, 0x00, 0x00, 0x00 },
+    { 0x22, 0x21, 0x1B, 0x05, 0xC0, 0xA1, 0x18, 0x08, 0x00, 0x00, 0x00 },
+    { 0x22, 0x21, 0x2C, 0x03, 0xD2, 0xA1, 0x18, 0x57, 0x00, 0x00, 0x00 },
+    { 0x01, 0x22, 0xBA, 0x01, 0xF1, 0xF1, 0x1E, 0x04, 0x00, 0x00, 0x00 },
+    { 0x21, 0x21, 0x28, 0x06, 0xF1, 0xF1, 0x6B, 0x3E, 0x00, 0x00, 0x00 },
+    { 0x27, 0x21, 0x60, 0x00, 0xF0, 0xF0, 0x0D, 0x0F, 0x00, 0x00, 0x00 },
+    { 0x20, 0x21, 0x2B, 0x06, 0x85, 0xF1, 0x6D, 0x89, 0x00, 0x00, 0x00 },
+    { 0x01, 0x21, 0xBF, 0x02, 0x53, 0x62, 0x5F, 0xAE, 0x01, 0x00, 0x00 },
+    { 0x23, 0x21, 0x70, 0x07, 0xD4, 0xA3, 0x4E, 0x64, 0x01, 0x00, 0x00 },
+    { 0x2B, 0x21, 0xA4, 0x07, 0xF6, 0x93, 0x5C, 0x4D, 0x00, 0x00, 0x00 },
+    { 0x21, 0x23, 0xAD, 0x07, 0x77, 0xF1, 0x18, 0x37, 0x00, 0x00, 0x00 },
+    { 0x21, 0x21, 0x2A, 0x03, 0xF3, 0xE2, 0x29, 0x46, 0x00, 0x00, 0x00 },
+    { 0x21, 0x23, 0x37, 0x03, 0xF3, 0xE2, 0x29, 0x46, 0x00, 0x00, 0x00 },
+#else /* Instrument settings from Allegro */
+    { 0x31, 0x21, 0x15, 0x09, 0xdd, 0x56, 0x13, 0x26, 0x01, 0x00, 0x08 }, /* Violin */
+    { 0x03, 0x11, 0x54, 0x09, 0xf3, 0xf1, 0x9a, 0xe7, 0x01, 0x00, 0x0c }, /* Acoustic Guitar(steel) */
+    { 0x21, 0x21, 0x8f, 0x0c, 0xf2, 0xf2, 0x45, 0x76, 0x00, 0x00, 0x08 }, /* Acoustic Grand */
+    { 0xe1, 0xe1, 0x46, 0x09, 0x88, 0x65, 0x5f, 0x1a, 0x00, 0x00, 0x00 }, /* Flute */
+    { 0x32, 0x21, 0x90, 0x09, 0x9b, 0x72, 0x21, 0x17, 0x00, 0x00, 0x04 }, /* Clarinet */
+    { 0x21, 0x21, 0x4b, 0x09, 0xaa, 0x8f, 0x16, 0x0a, 0x01, 0x00, 0x08 }, /* Oboe */
+    { 0x21, 0x21, 0x92, 0x0a, 0x85, 0x8f, 0x17, 0x09, 0x00, 0x00, 0x0c }, /* Trumpet */
+    { 0x23, 0xb1, 0x93, 0x09, 0x97, 0x55, 0x23, 0x14, 0x01, 0x00, 0x04 }, /* Church Organ */
+    { 0x21, 0x21, 0x9b, 0x09, 0x61, 0x7f, 0x6a, 0x0a, 0x00, 0x00, 0x02 }, /* French Horn */
+    { 0x71, 0x72, 0x57, 0x09, 0x54, 0x7a, 0x05, 0x05, 0x00, 0x00, 0x0c }, /* Synth Voice */
+    { 0x21, 0x36, 0x80, 0x17, 0xa2, 0xf1, 0x01, 0xd5, 0x00, 0x00, 0x08 }, /* Harpsichord */
+    { 0x18, 0x81, 0x62, 0x09, 0xf3, 0xf2, 0xe6, 0xf6, 0x00, 0x00, 0x00 }, /* Vibraphone */
+    { 0x31, 0x31, 0x8b, 0x09, 0xf4, 0xf1, 0xe8, 0x78, 0x00, 0x00, 0x0a }, /* Synth Bass 1 */
+    { 0x21, 0xa2, 0x1e, 0x09, 0x94, 0xc3, 0x06, 0xa6, 0x00, 0x00, 0x02 }, /* Acoustic Bass */
+    { 0x03, 0x21, 0x87, 0x89, 0xf6, 0xf3, 0x22, 0xf8, 0x01, 0x00, 0x06 }, /* Electric Guitar(clean) */
+#endif
+};
+
+
+/*--------------------------------------------------------------------------*/
+
+
+void ym2413_init(int count)
+{
+    int n;
+    for(n = 0; n < count; n += 1)
+    {
+        /* Reset YM2413 data */
+        ym2413_reset(n);
+    }
+}
+
+
+void ym2413_reset(int chip)
+{
+    int n;
+
+    /* Point to current YM2413 context */
+    t_ym2413 *opll = &ym2413[chip];
+
+    /* Clear channel data context */
+    memset(opll, 0, sizeof(t_ym2413));
+
+    /* Clear all YM3812 registers */
+    for(n = 0; n < 0x100; n += 1)
+    {
+        OPL_WRITE(chip, n, 0x00);
+    }
+
+    /* Turn off rhythm mode and key-on bits */
+    opll->rhythm = 0;
+    OPL_WRITE(chip, 0xBD, 0x00);
+
+    /* Enable waveform select */
+    OPL_WRITE(chip, 0x01, 0x20);
+}
+
+
+void ym2413_write(int chip, int address, int data)
+{
+    /* Point to current YM2413 context */
+    t_ym2413 *opll = &ym2413[chip];
+
+    if(address & 1) /* Data port */
+    {
+        /* Store register data */
+        opll->reg[opll->latch] = data;
+
+        switch(opll->latch & 0x30)
+        {
+            case 0x00: /* User instrument registers */
+                switch(opll->latch & 0x0F)
+                {
+                    case 0x00: /* Misc. ctrl. (modulator) */
+                    case 0x01: /* Misc. ctrl. (carrier) */
+                    case 0x02: /* Key scale level and total level (modulator) */
+                    case 0x04: /* Attack / Decay (modulator) */
+                    case 0x05: /* Attack / Decay (carrier) */
+                    case 0x06: /* Sustain / Release (modulator) */
+                    case 0x07: /* Sustain / Release (carrier) */
+                        opll->user[(opll->latch & 0x07)] = data;
+                        break;
+    
+                    case 0x03: /* Key scale level, carrier/modulator waveform, feedback */
+    
+                        /* Key scale level (carrier) */
+                        /* Don't touch the total level (channel volume) */
+                        opll->user[3] = (opll->user[3] & 0x3F) | (data & 0xC0);
+    
+                        /* Waveform select for the modulator */
+                        opll->user[8] = (data >> 3) & 1;
+    
+                        /* Waveform select for the carrier */
+                        opll->user[9] = (data >> 4) & 1;
+    
+                        /* Store feedback level in YM3812 format */
+                        opll->user[10] = ((data & 0x07) << 1) & 0x0E;
+                        break;
+    
+                    case 0x0E: /* Rhythm enable and key-on bits */
+                        if((data & 0x20) && (opll->rhythm == 0))
+                        {
+                            opll->rhythm = 1;
+                            rhythm_mode_init(chip);
+                        }
+                        else
+                        {
+                            opll->rhythm = 0;
+                        }
+                        OPL_WRITE(chip, 0xBD, (data & 0x3F));
+                        break;
+                }
+    
+                /* If the user instrument registers were accessed, then
+                   go through each channel and update the ones that were
+                   currently using the user instrument. We can skip the
+                   last three channels in rhythm mode since they can
+                   only use percussion sounds anyways. */
+                if(opll->latch <= 0x07)
+                {
+                    int x;
+                    for(x = 0; x < ((opll->reg[0x0E] & 0x20) ? 6 : 9); x += 1)
+                        if(opll->channel[x].instrument == 0x00)
+                            load_instrument(chip, x, 0x00, opll->channel[x].volume);
+                }
+                break;
+    
+            case 0x10: /* Channel Frequency (LSB) */
+            case 0x20: /* Channel Frequency (MSB) + key-on and sustain control */
+                {
+                    int block;
+                    int frequency;
+                    int ch = (opll->latch & 0x0F);
+
+                    /* Ensure proper channel range */
+                    if(ch > 0x08) break;
+    
+                    /* Get YM2413 channel frequency */
+                    frequency = ((opll->reg[0x10 + ch] & 0xFF) | ((opll->reg[0x20 + ch] & 0x01) << 8));
+    
+                    /* Scale 9 bit frequency to 10 bits */
+                    frequency = (frequency << 1) & 0x1FFF;
+    
+                    /* Get YM2413 block */
+                    block = (opll->reg[0x20 + ch] >> 1) & 7;
+    
+                    /* Add in block */
+                    frequency |= (block << 10);
+    
+                    /* Add key-on flag */
+                    if(opll->reg[0x20 + ch] & 0x10) frequency |= 0x2000;
+    
+                    /* Save current frequency/block/key-on setting */
+                    opll->channel[ch].frequency = (frequency & 0x3FFF);
+    
+                    /* TODO: Handle sustain flag (bit 5) before key-on */
+    
+                    /* Write changes to YM3812 */
+                    OPL_WRITE(chip, 0xA0 + ch, (opll->channel[ch].frequency >> 0) & 0xFF);
+                    OPL_WRITE(chip, 0xB0 + ch, (opll->channel[ch].frequency >> 8) & 0xFF);
+                }
+                break;
+    
+            case 0x30: /* Channel Volume Level and Instrument Select */
+
+                /* Ensure proper channel range */
+                if(opll->latch > 0x38) break;
+    
+                /* If we're accessing registers 36, 37, or 38, and we're
+                   in rhythm mode, then update the individual volume
+                   settings. */
+                if((opll->latch >= 0x36) && (opll->reg[0x0E] & 0x20))
+                {
+                    switch(opll->latch & 0x0F)
+                    {
+                        case 0x06: /* Bass drum */
+                          OPL_WRITE(chip, 0x53, ((data >> 0) & 0x0F) << 2);
+                          break;
+        
+                        case 0x07: /* High hat and snare drum */
+                          OPL_WRITE(chip, 0x51, ((data >> 4) & 0x0F) << 2);
+                          OPL_WRITE(chip, 0x54, ((data >> 0) & 0x0F) << 2);
+                          break;
+        
+                        case 0x08: /* Tom-top and top cymbal */
+                          OPL_WRITE(chip, 0x52, ((data >> 4) & 0x0F) << 2);
+                          OPL_WRITE(chip, 0x55, ((data >> 0) & 0x0F) << 2);
+                          break;
+                    }
+                }
+                else /* Set the new instrument and volume for this channel */
+                {
+                    int ch = (opll->latch & 0x0F);
+                    int inst = (data >> 4) & 0x0F;
+                    int vol = (data & 0x0F) << 2;
+    
+                    load_instrument(chip, ch, inst, vol);
+                }
+                break;
+        }
+    }
+    else /* Register latch */
+    {
+        opll->latch = (data & 0x3F);
+    }
+}
+
+
+void rhythm_mode_init(int chip)
+{
+    /* Point to current YM2413 context */
+    t_ym2413 *opll = &ym2413[chip];
+
+    /* Load instrument settings for channel seven. (Bass drum) */
+    OPL_WRITE(chip, 0x30, 0x13);
+    OPL_WRITE(chip, 0x33, 0x11);
+    OPL_WRITE(chip, 0x50, 0x25);
+    OPL_WRITE(chip, 0x53, ((opll->reg[0x36] >> 0) & 0x0F) << 2);
+    OPL_WRITE(chip, 0x70, 0xD7);
+    OPL_WRITE(chip, 0x73, 0xB7);
+    OPL_WRITE(chip, 0x90, 0xF4);
+    OPL_WRITE(chip, 0x93, 0xF4);
+    OPL_WRITE(chip, 0xF0, 0x00);
+    OPL_WRITE(chip, 0xF3, 0x00);
+    OPL_WRITE(chip, 0xC6, 0x00);
+    /* Use old frequency, but strip key-on bit */
+    OPL_WRITE(chip, 0xA6, (opll->channel[6].frequency >> 0) & 0xFF);
+    OPL_WRITE(chip, 0xB6, (opll->channel[6].frequency >> 8) & 0x1F);
+
+    /* Load instrument settings for channel eight. (High hat and snare drum) */
+    OPL_WRITE(chip, 0x31, 0x13);
+    OPL_WRITE(chip, 0x34, 0x11);
+    OPL_WRITE(chip, 0x51, ((opll->reg[0x37] >> 4) & 0x0f) << 2);
+    OPL_WRITE(chip, 0x54, ((opll->reg[0x37] >> 0) & 0x0f) << 2);
+    OPL_WRITE(chip, 0x71, 0xD7);
+    OPL_WRITE(chip, 0x74, 0xB7);
+    OPL_WRITE(chip, 0x91, 0xF4);
+    OPL_WRITE(chip, 0x94, 0xF4);
+    OPL_WRITE(chip, 0xF1, 0x00);
+    OPL_WRITE(chip, 0xF4, 0x00);
+    OPL_WRITE(chip, 0xC7, 0x00);
+    /* Use old frequency, but strip key-on bit */
+    OPL_WRITE(chip, 0xA7, (opll->channel[7].frequency >> 0) & 0xFF);
+    OPL_WRITE(chip, 0xB7, (opll->channel[7].frequency >> 8) & 0x1F);
+
+    /* Load instrument settings for channel nine. (Tom-tom and top cymbal) */
+    OPL_WRITE(chip, 0x32, 0x13);
+    OPL_WRITE(chip, 0x35, 0x11);
+    OPL_WRITE(chip, 0x52, ((opll->reg[0x38] >> 4) & 0x0F) << 2);
+    OPL_WRITE(chip, 0x55, ((opll->reg[0x38] >> 0) & 0x0F) << 2);
+    OPL_WRITE(chip, 0x72, 0xD7);
+    OPL_WRITE(chip, 0x75, 0xB7);
+    OPL_WRITE(chip, 0x92, 0xF4);
+    OPL_WRITE(chip, 0x95, 0xF4);
+    OPL_WRITE(chip, 0xF2, 0x00);
+    OPL_WRITE(chip, 0xF5, 0x00);
+    OPL_WRITE(chip, 0xC8, 0x00);
+    /* Use old frequency, but strip key-on bit */
+    OPL_WRITE(chip, 0xA8, (opll->channel[8].frequency >> 0) & 0xFF);
+    OPL_WRITE(chip, 0xB8, (opll->channel[8].frequency >> 8) & 0x1F);
+}
+
+
+/* channel (0-9), instrument (0-F), volume (0-3F, YM3812 format) */
+void load_instrument(int chip, int ch, int inst, int vol)
+{
+    /* Point to current YM2413 context */
+    t_ym2413 *opll = &ym2413[chip];
+
+    /* Point to fixed instrument or user table */
+    unsigned char *param = (inst == 0) ? &opll->user[0] : &table[inst][0];
+
+    /* Maps channels to operator registers */
+    unsigned char ch2op[] = {0, 1, 2, 8, 9, 10, 16, 17, 18};
+
+    /* Make operator offset from requested channel */
+    int op = ch2op[ch];
+
+    /* Store volume level */
+    opll->channel[ch].volume = (vol & 0x3F);
+
+    /* Store instrument number */
+    opll->channel[ch].instrument = (inst & 0x0F);
+
+    /* Update instrument settings, except frequency registers */
+    OPL_WRITE(chip, 0x20 + op,  param[0]);
+    OPL_WRITE(chip, 0x23 + op,  param[1]);
+    OPL_WRITE(chip, 0x40 + op,  param[2]);
+    OPL_WRITE(chip, 0x43 + op, (param[3] & 0xC0) | opll->channel[ch].volume);
+    OPL_WRITE(chip, 0x60 + op,  param[4]);
+    OPL_WRITE(chip, 0x63 + op,  param[5]);
+    OPL_WRITE(chip, 0x80 + op,  param[6]);
+    OPL_WRITE(chip, 0x83 + op,  param[7]);
+    OPL_WRITE(chip, 0xE0 + op,  param[8]);
+    OPL_WRITE(chip, 0xE3 + op,  param[9]);
+    OPL_WRITE(chip, 0xC0 + ch,  param[10]);
+}
diff --git a/MCUME_pico2/picosms/ym2413.h b/MCUME_pico2/picosms/ym2413.h
new file mode 100644
index 0000000..0ec4d4c
--- /dev/null
+++ b/MCUME_pico2/picosms/ym2413.h
@@ -0,0 +1,33 @@
+
+#ifndef _YM2413_H_
+#define _YM2413_H_
+
+/* Total # of YM2413's that can be used at once - change as needed */
+#define MAX_YM2413  (4)
+
+/* YM2413 context */
+typedef struct
+{
+    unsigned char reg[0x40];            /* 64 registers */
+    unsigned char latch;                /* Register latch */
+    unsigned char rhythm;               /* Rhythm instruments loaded flag */
+    unsigned char user[0x10];           /* User instrument settings */
+    struct
+    {
+        unsigned short int frequency;   /* Channel frequency */
+        unsigned char volume;           /* Channel volume */
+        unsigned char instrument;       /* Channel instrument */
+    }channel[9];
+}t_ym2413;
+
+/* Global data */
+extern t_ym2413 ym2413[MAX_YM2413];
+
+/* Function prototypes */
+void ym2413_init(int count);
+void ym2413_reset(int chip);
+void ym2413_write(int chip, int address, int data);
+void load_instrument(int chip, int ch, int inst, int vol);
+void rhythm_mode_init(int chip);
+
+#endif /* _YM2413_H_ */
diff --git a/MCUME_pico2/picosms/z80.c b/MCUME_pico2/picosms/z80.c
new file mode 100644
index 0000000..bc3d014
--- /dev/null
+++ b/MCUME_pico2/picosms/z80.c
@@ -0,0 +1,4389 @@
+/*****************************************************************************
+ *
+ *	 z80.c
+ *	 Portable Z80 emulator V2.7
+ *
+ *	 Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved.
+ *
+ *	 - This source code is released as cpu_readmapfreeware for non-commercial purposes.
+ *	 - You are free to use and redistribute this code in modified or
+ *	   unmodified form, provided you list me in the credits.
+ *	 - If you modify this source code, you must add a notice to each modified
+ *	   source file that it has been changed.  If you're a nice person, you
+ *	   will clearly mark each change too.  :)
+ *	 - If you wish to use this for commercial purposes, please contact me at
+ *	   pullmoll@t-online.de
+ *	 - The author of this copywritten work reserves the right to change the
+ *     terms of its usage and license at any time, including retroactively
+ *   - This entire notice must remain in the source code.
+ *
+ *	 Changes in 2.7:
+ *	  - removed z80_vm specific code, it's not needed (and never was).
+ *   Changes in 2.6:
+ *	  - BUSY_LOOP_HACKS needed to call change_pc16() earlier, before
+ *		checking the opcodes at the new address, because otherwise they
+ *		might access the old (wrong or even NULL) banked memory region.
+ *		Thanks to Sean Young for finding this nasty bug.
+ *   Changes in 2.5:
+ *	  - Burning cycles always adjusts the ICount by a multiple of 4.
+ *	  - In REPEAT_AT_ONCE cases the R register wasn't incremented twice
+ *		per repetition as it should have been. Those repeated opcodes
+ *		could also underflow the ICount.
+ *	  - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL
+ *		timing loops. I think those hacks weren't endian safe before too.
+ *   Changes in 2.4:
+ *	  - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and
+ *		sets the Z flag. With these changes the Tehkan World Cup driver
+ *		_seems_ to work again.
+ *   Changes in 2.3:
+ *	  - External termination of the execution loop calls z80_burn() and
+ *		z80_vm_burn() to burn an amount of cycles (R adjustment)
+ *	  - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS)
+ *		now also adjust the R register depending on the skipped opcodes.
+ *   Changes in 2.2:
+ *	  - Fixed bugs in CPL, SCF and CCF instructions flag handling.
+ *	  - Changed variable EA and ARG16() function to UINT32; this
+ *		produces slightly more efficient code.
+ *	  - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E
+ *		are changed to calls to the X6/XE opcodes to reduce object size.
+ *		They're hardly ever used so this should not yield a speed penalty.
+ *	 New in 2.0:
+ *    - Optional more exact Z80 emulation (#define Z80_EXACT 1) according
+ *		to a detailed description by Sean Young which can be found at:
+ *		http://www.msxnet.org/tech/Z80/z80undoc.txt
+ *****************************************************************************/
+
+#include "cpuintrf.h"
+#include "shared.h"
+
+
+#include "shared.h"
+extern void cpu_writemem16(int address, int data);
+extern void cpu_writeport(int port, int data);
+extern int cpu_readport(int port);
+unsigned char *cpu_readmap[8];
+unsigned char *cpu_writemap[8];
+
+#define cpu_readmem16(a)  ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF])
+#define cpu_readop(a)     ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF])
+#define cpu_readop_arg(a) ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF])
+
+//#define cpu_readmem16(a)        cpu_readmap[(a) >> 13][(a) & 0x1FFF]
+//#define cpu_readop(a)           cpu_readmap[(a) >> 13][(a) & 0x1FFF]
+//#define cpu_readop_arg(a)       cpu_readmap[(a) >> 13][(a) & 0x1FFF]
+
+/* execute main opcodes inside a big switch statement */
+#ifndef BIG_SWITCH
+#define BIG_SWITCH              1
+#endif
+
+/* big flags array for ADD/ADC/SUB/SBC/CP results */
+#define BIG_FLAGS_ARRAY         1
+
+/* Set to 1 for a more exact (but somewhat slower) Z80 emulation */
+#define Z80_EXACT               1
+
+/* repetitive commands (ldir,cpdr etc.) repeat at
+   once until cycles used up or B(C) counted down. */
+#define REPEAT_AT_ONCE		1
+
+/* on JP and JR opcodes check for tight loops */
+#define BUSY_LOOP_HACKS 	1
+
+/* check for delay loops counting down BC */
+#define TIME_LOOP_HACKS 	1
+
+/* #ifdef X86_ASM */
+#undef	BIG_FLAGS_ARRAY
+#define BIG_FLAGS_ARRAY 	0
+/*#endif */
+
+/*
+#ifdef PSX
+#undef  BIG_FLAGS_ARRAY
+#define BIG_FLAGS_ARRAY         0
+#endif
+*/
+
+#define CF  0x01
+#define NF	0x02
+#define PF	0x04
+#define VF	PF
+#define XF	0x08
+#define HF	0x10
+#define YF	0x20
+#define ZF	0x40
+#define SF	0x80
+
+#define INT_IRQ 0x01
+#define NMI_IRQ 0x02
+
+#define	_PPC	Z80.PREPC.d		/* previous program counter */
+
+#define _PCD	Z80.PC.d
+#define _PC 	Z80.PC.w.l
+
+#define _SPD	Z80.SP.d
+#define _SP 	Z80.SP.w.l
+
+#define _AFD	Z80.AF.d
+#define _AF 	Z80.AF.w.l
+#define _A		Z80.AF.b.h
+#define _F		Z80.AF.b.l
+
+#define _BCD	Z80.BC.d
+#define _BC 	Z80.BC.w.l
+#define _B		Z80.BC.b.h
+#define _C		Z80.BC.b.l
+
+#define _DED	Z80.DE.d
+#define _DE 	Z80.DE.w.l
+#define _D		Z80.DE.b.h
+#define _E		Z80.DE.b.l
+
+#define _HLD	Z80.HL.d
+#define _HL 	Z80.HL.w.l
+#define _H		Z80.HL.b.h
+#define _L		Z80.HL.b.l
+
+#define _IXD	Z80.IX.d
+#define _IX 	Z80.IX.w.l
+#define _HX 	Z80.IX.b.h
+#define _LX 	Z80.IX.b.l
+
+#define _IYD	Z80.IY.d
+#define _IY 	Z80.IY.w.l
+#define _HY 	Z80.IY.b.h
+#define _LY 	Z80.IY.b.l
+
+#define _I      Z80.I
+#define _R      Z80.R
+#define _R2     Z80.R2
+#define _IM     Z80.IM
+#define _IFF1	Z80.IFF1
+#define _IFF2	Z80.IFF2
+#define _HALT	Z80.HALT
+
+int z80_ICount;
+static Z80_Regs Z80;
+Z80_Regs *Z80_Context = &Z80;
+static UINT32 EA;
+int after_EI = 0;
+
+static UINT8 SZ[256];		/* zero and sign flags */
+static UINT8 SZ_BIT[256];	/* zero, sign and parity/overflow (=zero) flags for BIT opcode */
+static UINT8 SZP[256];		/* zero, sign and parity flags */
+static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
+static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
+#include "z80daa.h"
+/*
+#if BIG_FLAGS_ARRAY
+#include <signal.h>
+static UINT8 *SZHVC_add = 0;
+static UINT8 *SZHVC_sub = 0;
+#endif
+*/
+
+#if Z80_EXACT
+/* tmp1 value for ini/inir/outi/otir for [C.1-0][io.1-0] */
+static UINT8 irep_tmp1[4][4] = {
+	{0,0,1,0},{0,1,0,1},{1,0,1,1},{0,1,1,0}
+};
+
+/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */
+static UINT8 drep_tmp1[4][4] = {
+	{0,1,0,0},{1,0,0,1},{0,0,1,0},{0,1,0,1}
+};
+
+/* tmp2 value for all in/out repeated opcodes for B.7-0 */
+static UINT8 breg_tmp2[256] = {
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,
+	0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,
+	1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1
+};
+#endif
+
+static const UINT8 cc_op[0x100] = {
+ 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+ 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+ 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+ 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+ 5,10,10,10,10,11, 7,11, 5, 4,10, 0,10,10, 7,11,
+ 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+ 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+ 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11};
+
+
+static const UINT8 cc_cb[0x100] = {
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8};
+
+static const UINT8 cc_dd[0x100] = {
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4,
+ 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4};
+
+/* dd/fd cycles are identical */
+#define cc_fd cc_dd
+
+static const UINT8 cc_xxcb[0x100] = {
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
+23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23};
+
+static const UINT8 cc_ed[0x100] = {
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9,
+12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9,
+12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18,
+12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
+16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8};
+
+static void take_interrupt(void);
+
+#define PROTOTYPES(tablename,prefix) \
+    static __inline__ void prefix##_00(void); static __inline__ void prefix##_01(void); static __inline__ void prefix##_02(void); static __inline__ void prefix##_03(void); \
+    static __inline__ void prefix##_04(void); static __inline__ void prefix##_05(void); static __inline__ void prefix##_06(void); static __inline__ void prefix##_07(void); \
+    static __inline__ void prefix##_08(void); static __inline__ void prefix##_09(void); static __inline__ void prefix##_0a(void); static __inline__ void prefix##_0b(void); \
+    static __inline__ void prefix##_0c(void); static __inline__ void prefix##_0d(void); static __inline__ void prefix##_0e(void); static __inline__ void prefix##_0f(void); \
+    static __inline__ void prefix##_10(void); static __inline__ void prefix##_11(void); static __inline__ void prefix##_12(void); static __inline__ void prefix##_13(void); \
+    static __inline__ void prefix##_14(void); static __inline__ void prefix##_15(void); static __inline__ void prefix##_16(void); static __inline__ void prefix##_17(void); \
+    static __inline__ void prefix##_18(void); static __inline__ void prefix##_19(void); static __inline__ void prefix##_1a(void); static __inline__ void prefix##_1b(void); \
+    static __inline__ void prefix##_1c(void); static __inline__ void prefix##_1d(void); static __inline__ void prefix##_1e(void); static __inline__ void prefix##_1f(void); \
+    static __inline__ void prefix##_20(void); static __inline__ void prefix##_21(void); static __inline__ void prefix##_22(void); static __inline__ void prefix##_23(void); \
+    static __inline__ void prefix##_24(void); static __inline__ void prefix##_25(void); static __inline__ void prefix##_26(void); static __inline__ void prefix##_27(void); \
+    static __inline__ void prefix##_28(void); static __inline__ void prefix##_29(void); static __inline__ void prefix##_2a(void); static __inline__ void prefix##_2b(void); \
+    static __inline__ void prefix##_2c(void); static __inline__ void prefix##_2d(void); static __inline__ void prefix##_2e(void); static __inline__ void prefix##_2f(void); \
+    static __inline__ void prefix##_30(void); static __inline__ void prefix##_31(void); static __inline__ void prefix##_32(void); static __inline__ void prefix##_33(void); \
+    static __inline__ void prefix##_34(void); static __inline__ void prefix##_35(void); static __inline__ void prefix##_36(void); static __inline__ void prefix##_37(void); \
+    static __inline__ void prefix##_38(void); static __inline__ void prefix##_39(void); static __inline__ void prefix##_3a(void); static __inline__ void prefix##_3b(void); \
+    static __inline__ void prefix##_3c(void); static __inline__ void prefix##_3d(void); static __inline__ void prefix##_3e(void); static __inline__ void prefix##_3f(void); \
+    static __inline__ void prefix##_40(void); static __inline__ void prefix##_41(void); static __inline__ void prefix##_42(void); static __inline__ void prefix##_43(void); \
+    static __inline__ void prefix##_44(void); static __inline__ void prefix##_45(void); static __inline__ void prefix##_46(void); static __inline__ void prefix##_47(void); \
+    static __inline__ void prefix##_48(void); static __inline__ void prefix##_49(void); static __inline__ void prefix##_4a(void); static __inline__ void prefix##_4b(void); \
+    static __inline__ void prefix##_4c(void); static __inline__ void prefix##_4d(void); static __inline__ void prefix##_4e(void); static __inline__ void prefix##_4f(void); \
+    static __inline__ void prefix##_50(void); static __inline__ void prefix##_51(void); static __inline__ void prefix##_52(void); static __inline__ void prefix##_53(void); \
+    static __inline__ void prefix##_54(void); static __inline__ void prefix##_55(void); static __inline__ void prefix##_56(void); static __inline__ void prefix##_57(void); \
+    static __inline__ void prefix##_58(void); static __inline__ void prefix##_59(void); static __inline__ void prefix##_5a(void); static __inline__ void prefix##_5b(void); \
+    static __inline__ void prefix##_5c(void); static __inline__ void prefix##_5d(void); static __inline__ void prefix##_5e(void); static __inline__ void prefix##_5f(void); \
+    static __inline__ void prefix##_60(void); static __inline__ void prefix##_61(void); static __inline__ void prefix##_62(void); static __inline__ void prefix##_63(void); \
+    static __inline__ void prefix##_64(void); static __inline__ void prefix##_65(void); static __inline__ void prefix##_66(void); static __inline__ void prefix##_67(void); \
+    static __inline__ void prefix##_68(void); static __inline__ void prefix##_69(void); static __inline__ void prefix##_6a(void); static __inline__ void prefix##_6b(void); \
+    static __inline__ void prefix##_6c(void); static __inline__ void prefix##_6d(void); static __inline__ void prefix##_6e(void); static __inline__ void prefix##_6f(void); \
+    static __inline__ void prefix##_70(void); static __inline__ void prefix##_71(void); static __inline__ void prefix##_72(void); static __inline__ void prefix##_73(void); \
+    static __inline__ void prefix##_74(void); static __inline__ void prefix##_75(void); static __inline__ void prefix##_76(void); static __inline__ void prefix##_77(void); \
+    static __inline__ void prefix##_78(void); static __inline__ void prefix##_79(void); static __inline__ void prefix##_7a(void); static __inline__ void prefix##_7b(void); \
+    static __inline__ void prefix##_7c(void); static __inline__ void prefix##_7d(void); static __inline__ void prefix##_7e(void); static __inline__ void prefix##_7f(void); \
+    static __inline__ void prefix##_80(void); static __inline__ void prefix##_81(void); static __inline__ void prefix##_82(void); static __inline__ void prefix##_83(void); \
+    static __inline__ void prefix##_84(void); static __inline__ void prefix##_85(void); static __inline__ void prefix##_86(void); static __inline__ void prefix##_87(void); \
+    static __inline__ void prefix##_88(void); static __inline__ void prefix##_89(void); static __inline__ void prefix##_8a(void); static __inline__ void prefix##_8b(void); \
+    static __inline__ void prefix##_8c(void); static __inline__ void prefix##_8d(void); static __inline__ void prefix##_8e(void); static __inline__ void prefix##_8f(void); \
+    static __inline__ void prefix##_90(void); static __inline__ void prefix##_91(void); static __inline__ void prefix##_92(void); static __inline__ void prefix##_93(void); \
+    static __inline__ void prefix##_94(void); static __inline__ void prefix##_95(void); static __inline__ void prefix##_96(void); static __inline__ void prefix##_97(void); \
+    static __inline__ void prefix##_98(void); static __inline__ void prefix##_99(void); static __inline__ void prefix##_9a(void); static __inline__ void prefix##_9b(void); \
+    static __inline__ void prefix##_9c(void); static __inline__ void prefix##_9d(void); static __inline__ void prefix##_9e(void); static __inline__ void prefix##_9f(void); \
+    static __inline__ void prefix##_a0(void); static __inline__ void prefix##_a1(void); static __inline__ void prefix##_a2(void); static __inline__ void prefix##_a3(void); \
+    static __inline__ void prefix##_a4(void); static __inline__ void prefix##_a5(void); static __inline__ void prefix##_a6(void); static __inline__ void prefix##_a7(void); \
+    static __inline__ void prefix##_a8(void); static __inline__ void prefix##_a9(void); static __inline__ void prefix##_aa(void); static __inline__ void prefix##_ab(void); \
+    static __inline__ void prefix##_ac(void); static __inline__ void prefix##_ad(void); static __inline__ void prefix##_ae(void); static __inline__ void prefix##_af(void); \
+    static __inline__ void prefix##_b0(void); static __inline__ void prefix##_b1(void); static __inline__ void prefix##_b2(void); static __inline__ void prefix##_b3(void); \
+    static __inline__ void prefix##_b4(void); static __inline__ void prefix##_b5(void); static __inline__ void prefix##_b6(void); static __inline__ void prefix##_b7(void); \
+    static __inline__ void prefix##_b8(void); static __inline__ void prefix##_b9(void); static __inline__ void prefix##_ba(void); static __inline__ void prefix##_bb(void); \
+    static __inline__ void prefix##_bc(void); static __inline__ void prefix##_bd(void); static __inline__ void prefix##_be(void); static __inline__ void prefix##_bf(void); \
+    static __inline__ void prefix##_c0(void); static __inline__ void prefix##_c1(void); static __inline__ void prefix##_c2(void); static __inline__ void prefix##_c3(void); \
+    static __inline__ void prefix##_c4(void); static __inline__ void prefix##_c5(void); static __inline__ void prefix##_c6(void); static __inline__ void prefix##_c7(void); \
+    static __inline__ void prefix##_c8(void); static __inline__ void prefix##_c9(void); static __inline__ void prefix##_ca(void); static __inline__ void prefix##_cb(void); \
+    static __inline__ void prefix##_cc(void); static __inline__ void prefix##_cd(void); static __inline__ void prefix##_ce(void); static __inline__ void prefix##_cf(void); \
+    static __inline__ void prefix##_d0(void); static __inline__ void prefix##_d1(void); static __inline__ void prefix##_d2(void); static __inline__ void prefix##_d3(void); \
+    static __inline__ void prefix##_d4(void); static __inline__ void prefix##_d5(void); static __inline__ void prefix##_d6(void); static __inline__ void prefix##_d7(void); \
+    static __inline__ void prefix##_d8(void); static __inline__ void prefix##_d9(void); static __inline__ void prefix##_da(void); static __inline__ void prefix##_db(void); \
+    static __inline__ void prefix##_dc(void); static __inline__ void prefix##_dd(void); static __inline__ void prefix##_de(void); static __inline__ void prefix##_df(void); \
+    static __inline__ void prefix##_e0(void); static __inline__ void prefix##_e1(void); static __inline__ void prefix##_e2(void); static __inline__ void prefix##_e3(void); \
+    static __inline__ void prefix##_e4(void); static __inline__ void prefix##_e5(void); static __inline__ void prefix##_e6(void); static __inline__ void prefix##_e7(void); \
+    static __inline__ void prefix##_e8(void); static __inline__ void prefix##_e9(void); static __inline__ void prefix##_ea(void); static __inline__ void prefix##_eb(void); \
+    static __inline__ void prefix##_ec(void); static __inline__ void prefix##_ed(void); static __inline__ void prefix##_ee(void); static __inline__ void prefix##_ef(void); \
+    static __inline__ void prefix##_f0(void); static __inline__ void prefix##_f1(void); static __inline__ void prefix##_f2(void); static __inline__ void prefix##_f3(void); \
+    static __inline__ void prefix##_f4(void); static __inline__ void prefix##_f5(void); static __inline__ void prefix##_f6(void); static __inline__ void prefix##_f7(void); \
+    static __inline__ void prefix##_f8(void); static __inline__ void prefix##_f9(void); static __inline__ void prefix##_fa(void); static __inline__ void prefix##_fb(void); \
+    static __inline__ void prefix##_fc(void); static __inline__ void prefix##_fd(void); static __inline__ void prefix##_fe(void); static __inline__ void prefix##_ff(void); \
+static const void (*tablename[0x100])(void) = {	\
+    prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \
+    prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \
+    prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \
+    prefix##_18,prefix##_19,prefix##_1a,prefix##_1b,prefix##_1c,prefix##_1d,prefix##_1e,prefix##_1f, \
+    prefix##_20,prefix##_21,prefix##_22,prefix##_23,prefix##_24,prefix##_25,prefix##_26,prefix##_27, \
+    prefix##_28,prefix##_29,prefix##_2a,prefix##_2b,prefix##_2c,prefix##_2d,prefix##_2e,prefix##_2f, \
+    prefix##_30,prefix##_31,prefix##_32,prefix##_33,prefix##_34,prefix##_35,prefix##_36,prefix##_37, \
+    prefix##_38,prefix##_39,prefix##_3a,prefix##_3b,prefix##_3c,prefix##_3d,prefix##_3e,prefix##_3f, \
+    prefix##_40,prefix##_41,prefix##_42,prefix##_43,prefix##_44,prefix##_45,prefix##_46,prefix##_47, \
+    prefix##_48,prefix##_49,prefix##_4a,prefix##_4b,prefix##_4c,prefix##_4d,prefix##_4e,prefix##_4f, \
+    prefix##_50,prefix##_51,prefix##_52,prefix##_53,prefix##_54,prefix##_55,prefix##_56,prefix##_57, \
+    prefix##_58,prefix##_59,prefix##_5a,prefix##_5b,prefix##_5c,prefix##_5d,prefix##_5e,prefix##_5f, \
+    prefix##_60,prefix##_61,prefix##_62,prefix##_63,prefix##_64,prefix##_65,prefix##_66,prefix##_67, \
+    prefix##_68,prefix##_69,prefix##_6a,prefix##_6b,prefix##_6c,prefix##_6d,prefix##_6e,prefix##_6f, \
+    prefix##_70,prefix##_71,prefix##_72,prefix##_73,prefix##_74,prefix##_75,prefix##_76,prefix##_77, \
+    prefix##_78,prefix##_79,prefix##_7a,prefix##_7b,prefix##_7c,prefix##_7d,prefix##_7e,prefix##_7f, \
+    prefix##_80,prefix##_81,prefix##_82,prefix##_83,prefix##_84,prefix##_85,prefix##_86,prefix##_87, \
+    prefix##_88,prefix##_89,prefix##_8a,prefix##_8b,prefix##_8c,prefix##_8d,prefix##_8e,prefix##_8f, \
+    prefix##_90,prefix##_91,prefix##_92,prefix##_93,prefix##_94,prefix##_95,prefix##_96,prefix##_97, \
+    prefix##_98,prefix##_99,prefix##_9a,prefix##_9b,prefix##_9c,prefix##_9d,prefix##_9e,prefix##_9f, \
+    prefix##_a0,prefix##_a1,prefix##_a2,prefix##_a3,prefix##_a4,prefix##_a5,prefix##_a6,prefix##_a7, \
+    prefix##_a8,prefix##_a9,prefix##_aa,prefix##_ab,prefix##_ac,prefix##_ad,prefix##_ae,prefix##_af, \
+    prefix##_b0,prefix##_b1,prefix##_b2,prefix##_b3,prefix##_b4,prefix##_b5,prefix##_b6,prefix##_b7, \
+    prefix##_b8,prefix##_b9,prefix##_ba,prefix##_bb,prefix##_bc,prefix##_bd,prefix##_be,prefix##_bf, \
+    prefix##_c0,prefix##_c1,prefix##_c2,prefix##_c3,prefix##_c4,prefix##_c5,prefix##_c6,prefix##_c7, \
+    prefix##_c8,prefix##_c9,prefix##_ca,prefix##_cb,prefix##_cc,prefix##_cd,prefix##_ce,prefix##_cf, \
+    prefix##_d0,prefix##_d1,prefix##_d2,prefix##_d3,prefix##_d4,prefix##_d5,prefix##_d6,prefix##_d7, \
+    prefix##_d8,prefix##_d9,prefix##_da,prefix##_db,prefix##_dc,prefix##_dd,prefix##_de,prefix##_df, \
+    prefix##_e0,prefix##_e1,prefix##_e2,prefix##_e3,prefix##_e4,prefix##_e5,prefix##_e6,prefix##_e7, \
+    prefix##_e8,prefix##_e9,prefix##_ea,prefix##_eb,prefix##_ec,prefix##_ed,prefix##_ee,prefix##_ef, \
+    prefix##_f0,prefix##_f1,prefix##_f2,prefix##_f3,prefix##_f4,prefix##_f5,prefix##_f6,prefix##_f7, \
+	prefix##_f8,prefix##_f9,prefix##_fa,prefix##_fb,prefix##_fc,prefix##_fd,prefix##_fe,prefix##_ff  \
+}
+
+PROTOTYPES(Z80op,op);
+PROTOTYPES(Z80cb,cb);
+PROTOTYPES(Z80dd,dd);
+PROTOTYPES(Z80ed,ed);
+PROTOTYPES(Z80fd,fd);
+PROTOTYPES(Z80xxcb,xxcb);
+
+/****************************************************************************/
+/* Burn an odd amount of cycles, that is instructions taking something      */
+/* different from 4 T-states per opcode (and R increment)                   */
+/****************************************************************************/
+static __inline__ void BURNODD(int cycles, int opcodes, int cyclesum)
+{
+    if( cycles > 0 )
+    {
+		_R += (cycles / cyclesum) * opcodes;
+		z80_ICount -= (cycles / cyclesum) * cyclesum;
+    }
+}
+
+/***************************************************************
+ * define an opcode function
+ ***************************************************************/
+#define OP(prefix,opcode)  static __inline__ void prefix##_##opcode(void)
+
+/***************************************************************
+ * adjust cycle count by n T-states
+ ***************************************************************/
+#define CY(cycles) z80_ICount -= cycles
+
+/***************************************************************
+ * execute an opcode
+ ***************************************************************/
+#define EXEC(prefix,opcode) 									\
+{																\
+	unsigned op = opcode;										\
+	CY(cc_##prefix[op]);										\
+	(*Z80##prefix[op])();										\
+}
+
+#if BIG_SWITCH
+#define EXEC_INLINE(prefix,opcode)								\
+{																\
+	unsigned op = opcode;										\
+	CY(cc_##prefix[op]);										\
+	switch(op)													\
+	{															\
+	case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \
+	case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \
+	case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \
+	case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \
+	case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \
+	case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \
+	case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \
+	case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \
+	case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \
+	case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \
+	case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \
+	case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \
+	case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \
+	case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \
+	case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \
+	case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \
+	case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \
+	case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \
+	case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \
+	case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \
+	case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \
+	case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \
+	case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \
+	case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \
+	case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \
+	case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \
+	case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \
+	case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \
+	case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \
+	case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \
+	case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \
+	case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \
+	case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \
+	case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \
+	case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \
+	case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \
+	case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \
+	case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \
+	case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \
+	case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \
+	case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \
+	case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \
+	case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \
+	case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \
+	case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \
+	case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \
+	case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \
+	case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \
+	case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \
+	case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \
+	case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \
+	case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \
+	case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \
+	case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \
+	case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \
+	case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \
+	case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \
+	case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \
+	case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \
+	case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \
+	case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \
+	case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \
+	case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \
+	case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \
+	}																																	\
+}
+#else
+#define EXEC_INLINE EXEC
+#endif
+
+
+/***************************************************************
+ * Enter HALT state; write 1 to fake port on first execution
+ ***************************************************************/
+#define ENTER_HALT {											\
+    _PC--;                                                      \
+    _HALT = 1;                                                  \
+	if( !after_EI ) 											\
+		z80_burn( z80_ICount ); 								\
+}
+
+/***************************************************************
+ * Leave HALT state; write 0 to fake port
+ ***************************************************************/
+#define LEAVE_HALT {                                            \
+	if( _HALT ) 												\
+	{															\
+		_HALT = 0;												\
+		_PC++;													\
+	}															\
+}
+
+/***************************************************************
+ * Input a byte from given I/O port
+ ***************************************************************/
+#define IN(port)   ((UINT8)cpu_readport(port))
+
+/***************************************************************
+ * Output a byte to given I/O port
+ ***************************************************************/
+#define OUT(port,value) cpu_writeport(port,value)
+
+/***************************************************************
+ * Read a byte from given memory location
+ ***************************************************************/
+#define RM(addr) (UINT8)cpu_readmem16(addr)
+
+/***************************************************************
+ * Read a word from given memory location
+ ***************************************************************/
+static __inline__ void RM16( UINT32 addr, PAIR *r )
+{
+	r->b.l = RM(addr);
+	r->b.h = RM((addr+1)&0xffff);
+}
+
+/***************************************************************
+ * Write a byte to given memory location
+ ***************************************************************/
+#define WM(addr,value) cpu_writemem16(addr,value)
+
+/***************************************************************
+ * Write a word to given memory location
+ ***************************************************************/
+static __inline__ void WM16( UINT32 addr, PAIR *r )
+{
+	WM(addr,r->b.l);
+	WM((addr+1)&0xffff,r->b.h);
+}
+
+/***************************************************************
+ * ROP() is identical to RM() except it is used for
+ * reading opcodes. In case of system with memory mapped I/O,
+ * this function can be used to greatly speed up emulation
+ ***************************************************************/
+static __inline__ UINT8 ROP(void)
+{
+	unsigned pc = _PCD;
+	_PC++;
+	return cpu_readop(pc);
+}
+
+/****************************************************************
+ * ARG() is identical to ROP() except it is used
+ * for reading opcode arguments. This difference can be used to
+ * support systems that use different encoding mechanisms for
+ * opcodes and opcode arguments
+ ***************************************************************/
+static __inline__ UINT8 ARG(void)
+{
+	unsigned pc = _PCD;
+    _PC++;
+	return cpu_readop_arg(pc);
+}
+
+static __inline__ UINT32 ARG16(void)
+{
+	unsigned pc = _PCD;
+    _PC += 2;
+	return cpu_readop_arg(pc) | (cpu_readop_arg((pc+1)&0xffff) << 8);
+}
+
+/***************************************************************
+ * Calculate the effective address EA of an opcode using
+ * IX+offset resp. IY+offset addressing.
+ ***************************************************************/
+#define EAX EA = (UINT32)(UINT16)(_IX+(INT8)ARG())
+#define EAY EA = (UINT32)(UINT16)(_IY+(INT8)ARG())
+
+/***************************************************************
+ * POP
+ ***************************************************************/
+#define POP(DR) { RM16( _SPD, &Z80.DR ); _SP += 2; }
+
+/***************************************************************
+ * PUSH
+ ***************************************************************/
+#define PUSH(SR) { _SP -= 2; WM16( _SPD, &Z80.SR ); }
+
+/***************************************************************
+ * JP
+ ***************************************************************/
+#if BUSY_LOOP_HACKS
+#define JP {													\
+	unsigned oldpc = _PCD-1;									\
+	_PCD = ARG16(); 											\
+    /* speed up busy loop */                                    \
+	if( _PCD == oldpc ) 										\
+	{															\
+		if( !after_EI ) 										\
+			BURNODD( z80_ICount, 1, 10 );						\
+	}															\
+	else														\
+	{															\
+		UINT8 op = cpu_readop(_PCD);							\
+		if( _PCD == oldpc-1 )									\
+		{														\
+			/* NOP - JP $-1 or EI - JP $-1 */					\
+			if ( op == 0x00 || op == 0xfb ) 					\
+			{													\
+				if( !after_EI ) 								\
+					BURNODD( z80_ICount-4, 2, 4+10 );			\
+			}													\
+		}														\
+		else													\
+		/* LD SP,#xxxx - JP $-3 (Galaga) */ 					\
+		if( _PCD == oldpc-3 && op == 0x31 ) 					\
+		{														\
+			if( !after_EI ) 									\
+				BURNODD( z80_ICount-10, 2, 10+10 ); 			\
+		}														\
+	}															\
+}
+#else
+#define JP {													\
+	_PCD = ARG16(); 											\
+}
+#endif
+
+/***************************************************************
+ * JP_COND
+ ***************************************************************/
+
+#define JP_COND(cond)											\
+	if( cond )													\
+	{															\
+		_PCD = ARG16(); 										\
+	}															\
+	else														\
+	{															\
+		_PC += 2;												\
+    }
+
+/***************************************************************
+ * JR
+ ***************************************************************/
+#define JR()													\
+{																\
+	unsigned oldpc = _PCD-1;									\
+	INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ 	\
+	_PC += arg; 			/* so don't do _PC += ARG() */      \
+    /* speed up busy loop */                                    \
+	if( _PCD == oldpc ) 										\
+	{															\
+		if( !after_EI ) 										\
+			BURNODD( z80_ICount, 1, 12 );						\
+	}															\
+	else														\
+	{															\
+		UINT8 op = cpu_readop(_PCD);							\
+		if( _PCD == oldpc-1 )									\
+		{														\
+			/* NOP - JR $-1 or EI - JR $-1 */					\
+			if ( op == 0x00 || op == 0xfb ) 					\
+			{													\
+				if( !after_EI ) 								\
+					BURNODD( z80_ICount-4, 2, 4+12 );			\
+			}													\
+		}														\
+		else													\
+		/* LD SP,#xxxx - JR $-3 */								\
+		if( _PCD == oldpc-3 && op == 0x31 ) 					\
+		{														\
+			if( !after_EI ) 									\
+				BURNODD( z80_ICount-12, 2, 10+12 ); 			\
+		}														\
+    }                                                           \
+}
+
+/***************************************************************
+ * JR_COND
+ ***************************************************************/
+#define JR_COND(cond)											\
+	if( cond )													\
+	{															\
+		INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \
+		_PC += arg; 			/* so don't do _PC += ARG() */  \
+        CY(5);                                                  \
+	}															\
+	else _PC++; 												\
+
+/***************************************************************
+ * CALL
+ ***************************************************************/
+#define CALL(cond)												\
+	if( cond )													\
+	{															\
+		EA = ARG16();											\
+		PUSH( PC ); 											\
+		_PCD = EA;												\
+        CY(7);                                                  \
+	}															\
+	else														\
+	{															\
+		_PC+=2; 												\
+	}
+
+/***************************************************************
+ * RET
+ ***************************************************************/
+#define RET(cond)												\
+	if( cond )													\
+	{															\
+		POP(PC);												\
+		CY(6);													\
+	}
+
+/***************************************************************
+ * RETN
+ ***************************************************************/
+#define RETN	{												\
+    RET(1);                                                     \
+	if( _IFF1 == 0 && _IFF2 == 1 )								\
+	{															\
+		_IFF1 = 1;												\
+		if( Z80.irq_state != CLEAR_LINE ||						\
+			Z80.request_irq >= 0 )								\
+		{														\
+			take_interrupt();									\
+        }                                                       \
+	}															\
+	else _IFF1 = _IFF2; 										\
+}
+
+/***************************************************************
+ * RETI
+ ***************************************************************/
+#define RETI	{												\
+	int device = Z80.service_irq;								\
+    RET(1);                                                     \
+/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */	\
+/*	_IFF1 = _IFF2;	*/											\
+	if( device >= 0 )											\
+	{															\
+		Z80.irq[device].interrupt_reti(Z80.irq[device].irq_param); \
+	}															\
+}
+
+/***************************************************************
+ * LD	R,A
+ ***************************************************************/
+#define LD_R_A {												\
+	_R = _A;													\
+	_R2 = _A & 0x80;				/* keep bit 7 of R */		\
+}
+
+/***************************************************************
+ * LD	A,R
+ ***************************************************************/
+#define LD_A_R {												\
+	_A = (_R & 0x7f) | _R2; 									\
+	_F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 );					\
+}
+
+/***************************************************************
+ * LD	I,A
+ ***************************************************************/
+#define LD_I_A {												\
+	_I = _A;													\
+}
+
+/***************************************************************
+ * LD	A,I
+ ***************************************************************/
+#define LD_A_I {												\
+	_A = _I;													\
+	_F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 );					\
+}
+
+/***************************************************************
+ * RST
+ ***************************************************************/
+#define RST(addr)												\
+	PUSH( PC ); 												\
+    _PCD = addr;                                                
+
+/***************************************************************
+ * INC	r8
+ ***************************************************************/
+static __inline__ UINT8 INC(UINT8 value)
+{
+	UINT8 res = value + 1;
+	_F = (_F & CF) | SZHV_inc[res];
+	return (UINT8)res;
+}
+
+/***************************************************************
+ * DEC	r8
+ ***************************************************************/
+static __inline__ UINT8 DEC(UINT8 value)
+{
+	UINT8 res = value - 1;
+	_F = (_F & CF) | SZHV_dec[res];
+    return res;
+}
+
+/***************************************************************
+ * RLCA
+ ***************************************************************/
+#if Z80_EXACT
+#define RLCA													\
+	_A = (_A << 1) | (_A >> 7); 								\
+	_F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF))
+#else
+#define RLCA                                                    \
+	_A = (_A << 1) | (_A >> 7); 								\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF)
+#endif
+
+/***************************************************************
+ * RRCA
+ ***************************************************************/
+#if Z80_EXACT
+#define RRCA                                                    \
+	_F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)); 		\
+    _A = (_A >> 1) | (_A << 7)
+#else
+#define RRCA                                                    \
+	_F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF);			\
+	_A = (_A >> 1) | (_A << 7)
+#endif
+
+/***************************************************************
+ * RLA
+ ***************************************************************/
+#if Z80_EXACT
+#define RLA {													\
+	UINT8 res = (_A << 1) | (_F & CF);							\
+	UINT8 c = (_A & 0x80) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); 		\
+	_A = res;													\
+}
+#else
+#define RLA {                                                   \
+	UINT8 res = (_A << 1) | (_F & CF);							\
+	UINT8 c = (_A & 0x80) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | YF | XF | PF)) | c;					\
+	_A = res;													\
+}
+#endif
+
+/***************************************************************
+ * RRA
+ ***************************************************************/
+#if Z80_EXACT
+#define RRA {                                                   \
+	UINT8 res = (_A >> 1) | (_F << 7);							\
+	UINT8 c = (_A & 0x01) ? CF : 0; 							\
+	_F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); 		\
+	_A = res;													\
+}
+#else
+#define RRA {                                                   \
+	UINT8 res = (_A >> 1) | (_F << 7);							\
+	UINT8 c = (_A & 0x01) ? CF : 0; 							\
+    _F = (_F & (SF | ZF | YF | XF | PF)) | c;                   \
+	_A = res;													\
+}
+#endif
+
+/***************************************************************
+ * RRD
+ ***************************************************************/
+#define RRD {													\
+	UINT8 n = RM(_HL);											\
+	WM( _HL, (n >> 4) | (_A << 4) );							\
+	_A = (_A & 0xf0) | (n & 0x0f);								\
+	_F = (_F & CF) | SZP[_A];									\
+}
+
+/***************************************************************
+ * RLD
+ ***************************************************************/
+#define RLD {                                                   \
+    UINT8 n = RM(_HL);                                          \
+	WM( _HL, (n << 4) | (_A & 0x0f) );							\
+    _A = (_A & 0xf0) | (n >> 4);                                \
+	_F = (_F & CF) | SZP[_A];									\
+}
+
+/***************************************************************
+ * ADD	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define ADD(value)												\
+ asm (															\
+ " addb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n"                                     \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n"                                     \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define ADD(value)                                              \
+ asm (															\
+ " addb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n"                                     \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n"                                     \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define ADD(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) + value);					\
+	_F = SZHVC_add[ah | res];									\
+    _A = res;                                                   \
+}
+#else
+#define ADD(value)												\
+{																\
+	unsigned val = value;										\
+    unsigned res = _A + val;                                    \
+    _F = SZ[(UINT8)res] | ((res >> 8) & CF) |                   \
+        ((_A ^ res ^ val) & HF) |                               \
+        (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5);        \
+    _A = (UINT8)res;                                            \
+}
+#endif
+#endif
+
+/***************************************************************
+ * ADC	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define ADC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define ADC(value)                                              \
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " adcb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " addb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define ADC(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00, c = _AFD & 1;					\
+	UINT32 res = (UINT8)((ah >> 8) + value + c);				\
+	_F = SZHVC_add[(c << 16) | ah | res];						\
+    _A = res;                                                   \
+}
+#else
+#define ADC(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A + val + (_F & CF);						\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) |					\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5);		\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * SUB	n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define SUB(value)												\
+ asm (															\
+ " subb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define SUB(value)                                              \
+ asm (															\
+ " subb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define SUB(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) - value);					\
+	_F = SZHVC_sub[ah | res];									\
+    _A = res;                                                   \
+}
+#else
+#define SUB(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val;									\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A) & (_A ^ res) & 0x80) >> 5);				\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * SBC	A,n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define SBC(value)												\
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %0,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define SBC(value)                                              \
+ asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define SBC(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00, c = _AFD & 1;					\
+	UINT32 res = (UINT8)((ah >> 8) - value - c);				\
+	_F = SZHVC_sub[(c<<16) | ah | res]; 						\
+    _A = res;                                                   \
+}
+#else
+#define SBC(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val - (_F & CF);						\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		(((val ^ _A) & (_A ^ res) & 0x80) >> 5);				\
+	_A = res;													\
+}
+#endif
+#endif
+
+/***************************************************************
+ * NEG
+ ***************************************************************/
+#define NEG {                                                   \
+	UINT8 value = _A;											\
+	_A = 0; 													\
+	SUB(value); 												\
+}
+
+/***************************************************************
+ * DAA
+ ***************************************************************/
+#define DAA {													\
+	int idx = _A;												\
+	if( _F & CF ) idx |= 0x100; 								\
+	if( _F & HF ) idx |= 0x200; 								\
+	if( _F & NF ) idx |= 0x400; 								\
+	_AF = DAATable[idx];										\
+}
+
+/***************************************************************
+ * AND	n
+ ***************************************************************/
+#define AND(value)												\
+	_A &= value;												\
+	_F = SZP[_A] | HF
+
+/***************************************************************
+ * OR	n
+ ***************************************************************/
+#define OR(value)												\
+	_A |= value;												\
+	_F = SZP[_A]
+
+/***************************************************************
+ * XOR	n
+ ***************************************************************/
+#define XOR(value)												\
+	_A ^= value;												\
+	_F = SZP[_A]
+
+/***************************************************************
+ * CP	n
+ ***************************************************************/
+#ifdef X86_ASM
+#if Z80_EXACT
+#define CP(value)												\
+ asm (															\
+ " cmpb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ " movb %2,%%ah         \n" /* get result */                    \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#else
+#define CP(value)                                               \
+ asm (															\
+ " cmpb %2,%0           \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n" /* al = 1 if overflow */            \
+ " stc                  \n" /* prepare to set N flag */         \
+ " adcb %1,%1           \n" /* shift to P/V bit position */     \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign, zero, half carry, carry */ \
+ " orb %%ah,%1          \n" /* combine with P/V */              \
+ :"=r" (_A), "=r" (_F)                                          \
+ :"r" (value), "1" (_F), "0" (_A)                               \
+ )
+#endif
+#else
+#if BIG_FLAGS_ARRAY
+#define CP(value)												\
+{																\
+	UINT32 ah = _AFD & 0xff00;									\
+	UINT32 res = (UINT8)((ah >> 8) - value);					\
+	_F = SZHVC_sub[ah | res];									\
+}
+#else
+#define CP(value)												\
+{																\
+	unsigned val = value;										\
+	unsigned res = _A - val;									\
+	_F = SZ[res & 0xff] | ((res >> 8) & CF) | NF |				\
+		((_A ^ res ^ val) & HF) |								\
+		((((val ^ _A) & (_A ^ res)) >> 5) & VF);				\
+}
+#endif
+#endif
+
+/***************************************************************
+ * EX   AF,AF'
+ ***************************************************************/
+#define EX_AF {                                                 \
+	PAIR tmp;													\
+    tmp = Z80.AF; Z80.AF = Z80.AF2; Z80.AF2 = tmp;              \
+}
+
+/***************************************************************
+ * EX   DE,HL
+ ***************************************************************/
+#define EX_DE_HL {                                              \
+	PAIR tmp;													\
+    tmp = Z80.DE; Z80.DE = Z80.HL; Z80.HL = tmp;                \
+}
+
+/***************************************************************
+ * EXX
+ ***************************************************************/
+#define EXX {                                                   \
+	PAIR tmp;													\
+    tmp = Z80.BC; Z80.BC = Z80.BC2; Z80.BC2 = tmp;              \
+    tmp = Z80.DE; Z80.DE = Z80.DE2; Z80.DE2 = tmp;              \
+    tmp = Z80.HL; Z80.HL = Z80.HL2; Z80.HL2 = tmp;              \
+}
+
+/***************************************************************
+ * EX   (SP),r16
+ ***************************************************************/
+#define EXSP(DR)												\
+{																\
+	PAIR tmp = { { 0, 0, 0, 0 } };								\
+	RM16( _SPD, &tmp ); 										\
+	WM16( _SPD, &Z80.DR );										\
+	Z80.DR = tmp;												\
+}
+
+
+/***************************************************************
+ * ADD16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define ADD16(DR,SR)											\
+ asm (															\
+ " andb $0xc4,%1        \n"                                     \
+ " addb %%dl,%%cl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " andb $0x11,%%ah      \n"                                     \
+ " orb %%ah,%1          \n"                                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (Z80.DR.d), "=r" (_F)                                    \
+ :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d)                      \
+ )
+#else
+#define ADD16(DR,SR)                                            \
+ asm (															\
+ " andb $0xc4,%1        \n"                                     \
+ " addb %%dl,%%cl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " andb $0x11,%%ah      \n"                                     \
+ " orb %%ah,%1          \n"                                     \
+ :"=c" (Z80.DR.d), "=r" (_F)                                    \
+ :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d)                      \
+ )
+#endif
+#else
+#define ADD16(DR,SR)											\
+{																\
+	UINT32 res = Z80.DR.d + Z80.SR.d;							\
+	_F = (_F & (SF | ZF | VF)) |								\
+		(((Z80.DR.d ^ res ^ Z80.SR.d) >> 8) & HF) | 			\
+		((res >> 16) & CF); 									\
+	Z80.DR.w.l = (UINT16)res;									\
+}
+#endif
+
+/***************************************************************
+ * ADC	r16,r16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define ADC16(Reg)												\
+ asm (                                                          \
+ " shrb $1,%1           \n"                                     \
+ " adcb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#else
+#define ADC16(Reg)                                              \
+ asm (                                                          \
+ " shrb $1,%1           \n"                                     \
+ " adcb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " adcb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " addb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#endif
+#else
+#define ADC16(Reg)												\
+{																\
+	UINT32 res = _HLD + Z80.Reg.d + (_F & CF);					\
+	_F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) |				\
+		((res >> 16) & CF) |									\
+		((res >> 8) & SF) | 									\
+		((res & 0xffff) ? 0 : ZF) | 							\
+		(((Z80.Reg.d ^ _HLD ^ 0x8000) & (Z80.Reg.d ^ res) & 0x8000) >> 13); \
+	_HL = (UINT16)res;											\
+}
+#endif
+
+/***************************************************************
+ * SBC	r16,r16
+ ***************************************************************/
+#ifdef	X86_ASM
+#if Z80_EXACT
+#define SBC16(Reg)												\
+asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " sbbb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " stc                  \n"                                     \
+ " adcb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ " movb %%ch,%%ah       \n" /* get result MSB */                \
+ " andb $0x28,%%ah      \n" /* maks flags 5+3 */                \
+ " orb %%ah,%1          \n" /* put them into flags */           \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#else
+#define SBC16(Reg)                                              \
+asm (															\
+ " shrb $1,%1           \n"                                     \
+ " sbbb %%dl,%%cl       \n"                                     \
+ " lahf                 \n"                                     \
+ " movb %%ah,%%dl       \n"                                     \
+ " sbbb %%dh,%%ch       \n"                                     \
+ " lahf                 \n"                                     \
+ " setob %1             \n"                                     \
+ " orb $0xbf,%%dl       \n" /* set all but zero */              \
+ " stc                  \n"                                     \
+ " adcb %1,%1           \n"                                     \
+ " andb $0xd1,%%ah      \n" /* sign,zero,half carry and carry */\
+ " addb %1,%1           \n"                                     \
+ " orb %%ah,%1          \n" /* overflow into P/V */             \
+ " andb %%dl,%1         \n" /* mask zero */                     \
+ :"=c" (_HLD), "=r" (_F)                                        \
+ :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d)                         \
+ )
+#endif
+#else
+#define SBC16(Reg)												\
+{																\
+	UINT32 res = _HLD - Z80.Reg.d - (_F & CF);					\
+	_F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | NF |			\
+		((res >> 16) & CF) |									\
+		((res >> 8) & SF) | 									\
+		((res & 0xffff) ? 0 : ZF) | 							\
+		(((Z80.Reg.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13);	\
+	_HL = (UINT16)res;											\
+}
+#endif
+
+/***************************************************************
+ * RLC	r8
+ ***************************************************************/
+static __inline__ UINT8 RLC(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | (res >> 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RRC	r8
+ ***************************************************************/
+static __inline__ UINT8 RRC(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (res << 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RL	r8
+ ***************************************************************/
+static __inline__ UINT8 RL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | (_F & CF)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * RR	r8
+ ***************************************************************/
+static __inline__ UINT8 RR(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (_F << 7)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SLA	r8
+ ***************************************************************/
+static __inline__ UINT8 SLA(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = (res << 1) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SRA	r8
+ ***************************************************************/
+static __inline__ UINT8 SRA(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = ((res >> 1) | (res & 0x80)) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SLL	r8
+ ***************************************************************/
+static __inline__ UINT8 SLL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x80) ? CF : 0;
+	res = ((res << 1) | 0x01) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * SRL	r8
+ ***************************************************************/
+static __inline__ UINT8 SRL(UINT8 value)
+{
+	unsigned res = value;
+	unsigned c = (res & 0x01) ? CF : 0;
+	res = (res >> 1) & 0xff;
+	_F = SZP[res] | c;
+	return res;
+}
+
+/***************************************************************
+ * BIT  bit,r8
+ ***************************************************************/
+#define BIT(bit,reg)                                            \
+	_F = (_F & CF) | HF | SZ_BIT[reg & (1<<bit)]
+
+/***************************************************************
+ * BIT	bit,(IX/Y+o)
+ ***************************************************************/
+#if Z80_EXACT
+#define BIT_XY(bit,reg)                                         \
+    _F = (_F & CF) | HF | (SZ_BIT[reg & (1<<bit)] & ~(YF|XF)) | ((EA>>8) & (YF|XF))
+#else
+#define BIT_XY	BIT
+#endif
+
+/***************************************************************
+ * RES	bit,r8
+ ***************************************************************/
+static __inline__ UINT8 RES(UINT8 bit, UINT8 value)
+{
+	return value & ~(1<<bit);
+}
+
+/***************************************************************
+ * SET  bit,r8
+ ***************************************************************/
+static __inline__ UINT8 SET(UINT8 bit, UINT8 value)
+{
+	return value | (1<<bit);
+}
+
+/***************************************************************
+ * LDI
+ ***************************************************************/
+#if Z80_EXACT
+#define LDI {													\
+	UINT8 io = RM(_HL); 										\
+	WM( _DE, io );												\
+	_F &= SF | ZF | CF; 										\
+	if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */		\
+    if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */      \
+    _HL++; _DE++; _BC--;                                        \
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define LDI {                                                   \
+	WM( _DE, RM(_HL) ); 										\
+    _F &= SF | ZF | YF | XF | CF;                               \
+	_HL++; _DE++; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * CPI
+ ***************************************************************/
+#if Z80_EXACT
+#define CPI {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL++; _BC--;												\
+	_F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF;  \
+	if( _F & HF ) res -= 1; 									\
+	if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */			\
+	if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */			\
+    if( _BC ) _F |= VF;                                         \
+}
+#else
+#define CPI {                                                   \
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL++; _BC--;												\
+	_F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF;	\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * INI
+ ***************************************************************/
+#if Z80_EXACT
+#define INI {													\
+	UINT8 io = IN(_BC); 										\
+	_B--;														\
+	WM( _HL, io );												\
+	_HL++;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( (_C + io + 1) & 0x100 ) _F |= HF | CF;					\
+    if( (irep_tmp1[_C & 3][io & 3] ^                            \
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+		_F |= PF;												\
+}
+#else
+#define INI {													\
+	_B--;														\
+	WM( _HL, IN(_BC) ); 										\
+	_HL++;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * OUTI
+ ***************************************************************/
+#if Z80_EXACT
+#define OUTI {													\
+	UINT8 io = RM(_HL); 										\
+	OUT( _BC, io ); 											\
+    _B--;                                                       \
+	_HL++;														\
+	_F = SZ[_B];												\
+	if( io & SF ) _F |= NF; 									\
+	if( (_C + io + 1) & 0x100 ) _F |= HF | CF;					\
+    if( (irep_tmp1[_C & 3][io & 3] ^                            \
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+        _F |= PF;                                               \
+}
+#else
+#define OUTI {													\
+    OUT( _BC, RM(_HL) );                                        \
+	_B--;														\
+    _HL++;                                                      \
+    _F = (_B) ? NF : NF | ZF;                                   \
+}
+#endif
+
+/***************************************************************
+ * LDD
+ ***************************************************************/
+#if Z80_EXACT
+#define LDD {													\
+	UINT8 io = RM(_HL); 										\
+	WM( _DE, io );												\
+	_F &= SF | ZF | CF; 										\
+	if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */		\
+	if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */		\
+	_HL--; _DE--; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#else
+#define LDD {                                                   \
+	WM( _DE, RM(_HL) ); 										\
+    _F &= SF | ZF | YF | XF | CF;                               \
+	_HL--; _DE--; _BC--;										\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * CPD
+ ***************************************************************/
+#if Z80_EXACT
+#define CPD {													\
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL--; _BC--;												\
+	_F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF;  \
+	if( _F & HF ) res -= 1; 									\
+	if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */			\
+	if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */			\
+    if( _BC ) _F |= VF;                                         \
+}
+#else
+#define CPD {                                                   \
+	UINT8 val = RM(_HL);										\
+	UINT8 res = _A - val;										\
+	_HL--; _BC--;												\
+	_F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF;	\
+	if( _BC ) _F |= VF; 										\
+}
+#endif
+
+/***************************************************************
+ * IND
+ ***************************************************************/
+#if Z80_EXACT
+#define IND {													\
+    UINT8 io = IN(_BC);                                         \
+	_B--;														\
+	WM( _HL, io );												\
+	_HL--;														\
+	_F = SZ[_B];												\
+    if( io & SF ) _F |= NF;                                     \
+	if( (_C + io - 1) & 0x100 ) _F |= HF | CF;					\
+	if( (drep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+        _F |= PF;                                               \
+}
+#else
+#define IND {                                                   \
+	_B--;														\
+	WM( _HL, IN(_BC) ); 										\
+	_HL--;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * OUTD
+ ***************************************************************/
+#if Z80_EXACT
+#define OUTD {													\
+	UINT8 io = RM(_HL); 										\
+	OUT( _BC, io ); 											\
+	_B--;														\
+	_HL--;														\
+	_F = SZ[_B];												\
+    if( io & SF ) _F |= NF;                                     \
+	if( (_C + io - 1) & 0x100 ) _F |= HF | CF;					\
+	if( (drep_tmp1[_C & 3][io & 3] ^							\
+		 breg_tmp2[_B] ^										\
+		 (_C >> 2) ^											\
+		 (io >> 2)) & 1 )										\
+        _F |= PF;                                               \
+}
+#else
+#define OUTD {                                                  \
+    OUT( _BC, RM(_HL) );                                        \
+	_B--;														\
+	_HL--;														\
+	_F = (_B) ? NF : NF | ZF;									\
+}
+#endif
+
+/***************************************************************
+ * LDIR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define LDIR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+	do															\
+	{															\
+		LDI;													\
+		if( _BC )												\
+		{														\
+			if( z80_ICount > 0 )								\
+			{													\
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+			else break; 										\
+		}														\
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define LDIR LDI; if( _BC ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * CPIR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define CPIR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		CPI;													\
+		if( _BC && !(_F & ZF) ) 								\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define CPIR CPI; if( _BC && !(_F & ZF) ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * INIR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define INIR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		INI;													\
+		if( _B )												\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define INIR INI; if( _B ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * OTIR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define OTIR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		OUTI;													\
+		if( _B	)												\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define OTIR OUTI; if( _B ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * LDDR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define LDDR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		LDD;													\
+		if( _BC )												\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define LDDR LDD; if( _BC ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * CPDR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define CPDR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		CPD;													\
+		if( _BC && !(_F & ZF) ) 								\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define CPDR CPD; if( _BC && !(_F & ZF) ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * INDR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define INDR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		IND;													\
+		if( _B )												\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define INDR IND; if( _B ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * OTDR
+ ***************************************************************/
+#if REPEAT_AT_ONCE
+#define OTDR {                                                  \
+	CY(5);														\
+	_PC -= 2;													\
+    do                                                          \
+	{															\
+		OUTD;													\
+		if( _B )												\
+		{														\
+			if( z80_ICount > 0 )								\
+            {                                                   \
+				_R += 2;  /* increment R twice */				\
+				CY(21); 										\
+			}													\
+            else break;                                         \
+        }                                                       \
+		else													\
+		{														\
+			_PC += 2;											\
+            z80_ICount += 5;                                    \
+            break;                                              \
+		}														\
+	} while( z80_ICount > 0 );									\
+}
+#else
+#define OTDR OUTD; if( _B ) { _PC -= 2; CY(5); }
+#endif
+
+/***************************************************************
+ * EI
+ ***************************************************************/
+#define EI {													\
+	/* If interrupts were disabled, execute one more			\
+     * instruction and check the IRQ line.                      \
+     * If not, simply set interrupt flip-flop 2                 \
+     */                                                         \
+	if( _IFF1 == 0 )											\
+	{															\
+        _IFF1 = _IFF2 = 1;                                      \
+        _PPC = _PCD;                                            \
+		_R++;													\
+		if( Z80.irq_state != CLEAR_LINE ||						\
+			Z80.request_irq >= 0 )								\
+		{														\
+			after_EI = 1;	/* avoid cycle skip hacks */		\
+			EXEC(op,ROP()); 									\
+			after_EI = 0;										\
+            take_interrupt();                                   \
+        }                                                       \
+		else EXEC(op,ROP()); 									\
+    } else _IFF2 = 1;                                           \
+}
+
+/**********************************************************
+ * opcodes with CB prefix
+ * rotate, shift and bit operations
+ **********************************************************/
+OP(cb,00) { _B = RLC(_B);											} /* RLC  B 		  */
+OP(cb,01) { _C = RLC(_C);											} /* RLC  C 		  */
+OP(cb,02) { _D = RLC(_D);											} /* RLC  D 		  */
+OP(cb,03) { _E = RLC(_E);											} /* RLC  E 		  */
+OP(cb,04) { _H = RLC(_H);											} /* RLC  H 		  */
+OP(cb,05) { _L = RLC(_L);											} /* RLC  L 		  */
+OP(cb,06) { WM( _HL, RLC(RM(_HL)) );								} /* RLC  (HL)		  */
+OP(cb,07) { _A = RLC(_A);											} /* RLC  A 		  */
+
+OP(cb,08) { _B = RRC(_B);											} /* RRC  B 		  */
+OP(cb,09) { _C = RRC(_C);											} /* RRC  C 		  */
+OP(cb,0a) { _D = RRC(_D);											} /* RRC  D 		  */
+OP(cb,0b) { _E = RRC(_E);											} /* RRC  E 		  */
+OP(cb,0c) { _H = RRC(_H);											} /* RRC  H 		  */
+OP(cb,0d) { _L = RRC(_L);											} /* RRC  L 		  */
+OP(cb,0e) { WM( _HL, RRC(RM(_HL)) );								} /* RRC  (HL)		  */
+OP(cb,0f) { _A = RRC(_A);											} /* RRC  A 		  */
+
+OP(cb,10) { _B = RL(_B);											} /* RL   B 		  */
+OP(cb,11) { _C = RL(_C);											} /* RL   C 		  */
+OP(cb,12) { _D = RL(_D);											} /* RL   D 		  */
+OP(cb,13) { _E = RL(_E);											} /* RL   E 		  */
+OP(cb,14) { _H = RL(_H);											} /* RL   H 		  */
+OP(cb,15) { _L = RL(_L);											} /* RL   L 		  */
+OP(cb,16) { WM( _HL, RL(RM(_HL)) ); 								} /* RL   (HL)		  */
+OP(cb,17) { _A = RL(_A);											} /* RL   A 		  */
+
+OP(cb,18) { _B = RR(_B);											} /* RR   B 		  */
+OP(cb,19) { _C = RR(_C);											} /* RR   C 		  */
+OP(cb,1a) { _D = RR(_D);											} /* RR   D 		  */
+OP(cb,1b) { _E = RR(_E);											} /* RR   E 		  */
+OP(cb,1c) { _H = RR(_H);											} /* RR   H 		  */
+OP(cb,1d) { _L = RR(_L);											} /* RR   L 		  */
+OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); 								} /* RR   (HL)		  */
+OP(cb,1f) { _A = RR(_A);											} /* RR   A 		  */
+
+OP(cb,20) { _B = SLA(_B);											} /* SLA  B 		  */
+OP(cb,21) { _C = SLA(_C);											} /* SLA  C 		  */
+OP(cb,22) { _D = SLA(_D);											} /* SLA  D 		  */
+OP(cb,23) { _E = SLA(_E);											} /* SLA  E 		  */
+OP(cb,24) { _H = SLA(_H);											} /* SLA  H 		  */
+OP(cb,25) { _L = SLA(_L);											} /* SLA  L 		  */
+OP(cb,26) { WM( _HL, SLA(RM(_HL)) );								} /* SLA  (HL)		  */
+OP(cb,27) { _A = SLA(_A);											} /* SLA  A 		  */
+
+OP(cb,28) { _B = SRA(_B);											} /* SRA  B 		  */
+OP(cb,29) { _C = SRA(_C);											} /* SRA  C 		  */
+OP(cb,2a) { _D = SRA(_D);											} /* SRA  D 		  */
+OP(cb,2b) { _E = SRA(_E);											} /* SRA  E 		  */
+OP(cb,2c) { _H = SRA(_H);											} /* SRA  H 		  */
+OP(cb,2d) { _L = SRA(_L);											} /* SRA  L 		  */
+OP(cb,2e) { WM( _HL, SRA(RM(_HL)) );								} /* SRA  (HL)		  */
+OP(cb,2f) { _A = SRA(_A);											} /* SRA  A 		  */
+
+OP(cb,30) { _B = SLL(_B);											} /* SLL  B 		  */
+OP(cb,31) { _C = SLL(_C);											} /* SLL  C 		  */
+OP(cb,32) { _D = SLL(_D);											} /* SLL  D 		  */
+OP(cb,33) { _E = SLL(_E);											} /* SLL  E 		  */
+OP(cb,34) { _H = SLL(_H);											} /* SLL  H 		  */
+OP(cb,35) { _L = SLL(_L);											} /* SLL  L 		  */
+OP(cb,36) { WM( _HL, SLL(RM(_HL)) );								} /* SLL  (HL)		  */
+OP(cb,37) { _A = SLL(_A);											} /* SLL  A 		  */
+
+OP(cb,38) { _B = SRL(_B);											} /* SRL  B 		  */
+OP(cb,39) { _C = SRL(_C);											} /* SRL  C 		  */
+OP(cb,3a) { _D = SRL(_D);											} /* SRL  D 		  */
+OP(cb,3b) { _E = SRL(_E);											} /* SRL  E 		  */
+OP(cb,3c) { _H = SRL(_H);											} /* SRL  H 		  */
+OP(cb,3d) { _L = SRL(_L);											} /* SRL  L 		  */
+OP(cb,3e) { WM( _HL, SRL(RM(_HL)) );								} /* SRL  (HL)		  */
+OP(cb,3f) { _A = SRL(_A);											} /* SRL  A 		  */
+
+OP(cb,40) { BIT(0,_B);												} /* BIT  0,B		  */
+OP(cb,41) { BIT(0,_C);												} /* BIT  0,C		  */
+OP(cb,42) { BIT(0,_D);												} /* BIT  0,D		  */
+OP(cb,43) { BIT(0,_E);												} /* BIT  0,E		  */
+OP(cb,44) { BIT(0,_H);												} /* BIT  0,H		  */
+OP(cb,45) { BIT(0,_L);												} /* BIT  0,L		  */
+OP(cb,46) { BIT(0,RM(_HL)); 										} /* BIT  0,(HL)	  */
+OP(cb,47) { BIT(0,_A);												} /* BIT  0,A		  */
+
+OP(cb,48) { BIT(1,_B);												} /* BIT  1,B		  */
+OP(cb,49) { BIT(1,_C);												} /* BIT  1,C		  */
+OP(cb,4a) { BIT(1,_D);												} /* BIT  1,D		  */
+OP(cb,4b) { BIT(1,_E);												} /* BIT  1,E		  */
+OP(cb,4c) { BIT(1,_H);												} /* BIT  1,H		  */
+OP(cb,4d) { BIT(1,_L);												} /* BIT  1,L		  */
+OP(cb,4e) { BIT(1,RM(_HL)); 										} /* BIT  1,(HL)	  */
+OP(cb,4f) { BIT(1,_A);												} /* BIT  1,A		  */
+
+OP(cb,50) { BIT(2,_B);												} /* BIT  2,B		  */
+OP(cb,51) { BIT(2,_C);												} /* BIT  2,C		  */
+OP(cb,52) { BIT(2,_D);												} /* BIT  2,D		  */
+OP(cb,53) { BIT(2,_E);												} /* BIT  2,E		  */
+OP(cb,54) { BIT(2,_H);												} /* BIT  2,H		  */
+OP(cb,55) { BIT(2,_L);												} /* BIT  2,L		  */
+OP(cb,56) { BIT(2,RM(_HL)); 										} /* BIT  2,(HL)	  */
+OP(cb,57) { BIT(2,_A);												} /* BIT  2,A		  */
+
+OP(cb,58) { BIT(3,_B);												} /* BIT  3,B		  */
+OP(cb,59) { BIT(3,_C);												} /* BIT  3,C		  */
+OP(cb,5a) { BIT(3,_D);												} /* BIT  3,D		  */
+OP(cb,5b) { BIT(3,_E);												} /* BIT  3,E		  */
+OP(cb,5c) { BIT(3,_H);												} /* BIT  3,H		  */
+OP(cb,5d) { BIT(3,_L);												} /* BIT  3,L		  */
+OP(cb,5e) { BIT(3,RM(_HL)); 										} /* BIT  3,(HL)	  */
+OP(cb,5f) { BIT(3,_A);												} /* BIT  3,A		  */
+
+OP(cb,60) { BIT(4,_B);												} /* BIT  4,B		  */
+OP(cb,61) { BIT(4,_C);												} /* BIT  4,C		  */
+OP(cb,62) { BIT(4,_D);												} /* BIT  4,D		  */
+OP(cb,63) { BIT(4,_E);												} /* BIT  4,E		  */
+OP(cb,64) { BIT(4,_H);												} /* BIT  4,H		  */
+OP(cb,65) { BIT(4,_L);												} /* BIT  4,L		  */
+OP(cb,66) { BIT(4,RM(_HL)); 										} /* BIT  4,(HL)	  */
+OP(cb,67) { BIT(4,_A);												} /* BIT  4,A		  */
+
+OP(cb,68) { BIT(5,_B);												} /* BIT  5,B		  */
+OP(cb,69) { BIT(5,_C);												} /* BIT  5,C		  */
+OP(cb,6a) { BIT(5,_D);												} /* BIT  5,D		  */
+OP(cb,6b) { BIT(5,_E);												} /* BIT  5,E		  */
+OP(cb,6c) { BIT(5,_H);												} /* BIT  5,H		  */
+OP(cb,6d) { BIT(5,_L);												} /* BIT  5,L		  */
+OP(cb,6e) { BIT(5,RM(_HL)); 										} /* BIT  5,(HL)	  */
+OP(cb,6f) { BIT(5,_A);												} /* BIT  5,A		  */
+
+OP(cb,70) { BIT(6,_B);												} /* BIT  6,B		  */
+OP(cb,71) { BIT(6,_C);												} /* BIT  6,C		  */
+OP(cb,72) { BIT(6,_D);												} /* BIT  6,D		  */
+OP(cb,73) { BIT(6,_E);												} /* BIT  6,E		  */
+OP(cb,74) { BIT(6,_H);												} /* BIT  6,H		  */
+OP(cb,75) { BIT(6,_L);												} /* BIT  6,L		  */
+OP(cb,76) { BIT(6,RM(_HL)); 										} /* BIT  6,(HL)	  */
+OP(cb,77) { BIT(6,_A);												} /* BIT  6,A		  */
+
+OP(cb,78) { BIT(7,_B);												} /* BIT  7,B		  */
+OP(cb,79) { BIT(7,_C);												} /* BIT  7,C		  */
+OP(cb,7a) { BIT(7,_D);												} /* BIT  7,D		  */
+OP(cb,7b) { BIT(7,_E);												} /* BIT  7,E		  */
+OP(cb,7c) { BIT(7,_H);												} /* BIT  7,H		  */
+OP(cb,7d) { BIT(7,_L);												} /* BIT  7,L		  */
+OP(cb,7e) { BIT(7,RM(_HL)); 										} /* BIT  7,(HL)	  */
+OP(cb,7f) { BIT(7,_A);												} /* BIT  7,A		  */
+
+OP(cb,80) { _B = RES(0,_B); 										} /* RES  0,B		  */
+OP(cb,81) { _C = RES(0,_C); 										} /* RES  0,C		  */
+OP(cb,82) { _D = RES(0,_D); 										} /* RES  0,D		  */
+OP(cb,83) { _E = RES(0,_E); 										} /* RES  0,E		  */
+OP(cb,84) { _H = RES(0,_H); 										} /* RES  0,H		  */
+OP(cb,85) { _L = RES(0,_L); 										} /* RES  0,L		  */
+OP(cb,86) { WM( _HL, RES(0,RM(_HL)) );								} /* RES  0,(HL)	  */
+OP(cb,87) { _A = RES(0,_A); 										} /* RES  0,A		  */
+
+OP(cb,88) { _B = RES(1,_B); 										} /* RES  1,B		  */
+OP(cb,89) { _C = RES(1,_C); 										} /* RES  1,C		  */
+OP(cb,8a) { _D = RES(1,_D); 										} /* RES  1,D		  */
+OP(cb,8b) { _E = RES(1,_E); 										} /* RES  1,E		  */
+OP(cb,8c) { _H = RES(1,_H); 										} /* RES  1,H		  */
+OP(cb,8d) { _L = RES(1,_L); 										} /* RES  1,L		  */
+OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) );								} /* RES  1,(HL)	  */
+OP(cb,8f) { _A = RES(1,_A); 										} /* RES  1,A		  */
+
+OP(cb,90) { _B = RES(2,_B); 										} /* RES  2,B		  */
+OP(cb,91) { _C = RES(2,_C); 										} /* RES  2,C		  */
+OP(cb,92) { _D = RES(2,_D); 										} /* RES  2,D		  */
+OP(cb,93) { _E = RES(2,_E); 										} /* RES  2,E		  */
+OP(cb,94) { _H = RES(2,_H); 										} /* RES  2,H		  */
+OP(cb,95) { _L = RES(2,_L); 										} /* RES  2,L		  */
+OP(cb,96) { WM( _HL, RES(2,RM(_HL)) );								} /* RES  2,(HL)	  */
+OP(cb,97) { _A = RES(2,_A); 										} /* RES  2,A		  */
+
+OP(cb,98) { _B = RES(3,_B); 										} /* RES  3,B		  */
+OP(cb,99) { _C = RES(3,_C); 										} /* RES  3,C		  */
+OP(cb,9a) { _D = RES(3,_D); 										} /* RES  3,D		  */
+OP(cb,9b) { _E = RES(3,_E); 										} /* RES  3,E		  */
+OP(cb,9c) { _H = RES(3,_H); 										} /* RES  3,H		  */
+OP(cb,9d) { _L = RES(3,_L); 										} /* RES  3,L		  */
+OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) );								} /* RES  3,(HL)	  */
+OP(cb,9f) { _A = RES(3,_A); 										} /* RES  3,A		  */
+
+OP(cb,a0) { _B = RES(4,_B); 										} /* RES  4,B		  */
+OP(cb,a1) { _C = RES(4,_C); 										} /* RES  4,C		  */
+OP(cb,a2) { _D = RES(4,_D); 										} /* RES  4,D		  */
+OP(cb,a3) { _E = RES(4,_E); 										} /* RES  4,E		  */
+OP(cb,a4) { _H = RES(4,_H); 										} /* RES  4,H		  */
+OP(cb,a5) { _L = RES(4,_L); 										} /* RES  4,L		  */
+OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) );								} /* RES  4,(HL)	  */
+OP(cb,a7) { _A = RES(4,_A); 										} /* RES  4,A		  */
+
+OP(cb,a8) { _B = RES(5,_B); 										} /* RES  5,B		  */
+OP(cb,a9) { _C = RES(5,_C); 										} /* RES  5,C		  */
+OP(cb,aa) { _D = RES(5,_D); 										} /* RES  5,D		  */
+OP(cb,ab) { _E = RES(5,_E); 										} /* RES  5,E		  */
+OP(cb,ac) { _H = RES(5,_H); 										} /* RES  5,H		  */
+OP(cb,ad) { _L = RES(5,_L); 										} /* RES  5,L		  */
+OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) );								} /* RES  5,(HL)	  */
+OP(cb,af) { _A = RES(5,_A); 										} /* RES  5,A		  */
+
+OP(cb,b0) { _B = RES(6,_B); 										} /* RES  6,B		  */
+OP(cb,b1) { _C = RES(6,_C); 										} /* RES  6,C		  */
+OP(cb,b2) { _D = RES(6,_D); 										} /* RES  6,D		  */
+OP(cb,b3) { _E = RES(6,_E); 										} /* RES  6,E		  */
+OP(cb,b4) { _H = RES(6,_H); 										} /* RES  6,H		  */
+OP(cb,b5) { _L = RES(6,_L); 										} /* RES  6,L		  */
+OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) );								} /* RES  6,(HL)	  */
+OP(cb,b7) { _A = RES(6,_A); 										} /* RES  6,A		  */
+
+OP(cb,b8) { _B = RES(7,_B); 										} /* RES  7,B		  */
+OP(cb,b9) { _C = RES(7,_C); 										} /* RES  7,C		  */
+OP(cb,ba) { _D = RES(7,_D); 										} /* RES  7,D		  */
+OP(cb,bb) { _E = RES(7,_E); 										} /* RES  7,E		  */
+OP(cb,bc) { _H = RES(7,_H); 										} /* RES  7,H		  */
+OP(cb,bd) { _L = RES(7,_L); 										} /* RES  7,L		  */
+OP(cb,be) { WM( _HL, RES(7,RM(_HL)) );								} /* RES  7,(HL)	  */
+OP(cb,bf) { _A = RES(7,_A); 										} /* RES  7,A		  */
+
+OP(cb,c0) { _B = SET(0,_B); 										} /* SET  0,B		  */
+OP(cb,c1) { _C = SET(0,_C); 										} /* SET  0,C		  */
+OP(cb,c2) { _D = SET(0,_D); 										} /* SET  0,D		  */
+OP(cb,c3) { _E = SET(0,_E); 										} /* SET  0,E		  */
+OP(cb,c4) { _H = SET(0,_H); 										} /* SET  0,H		  */
+OP(cb,c5) { _L = SET(0,_L); 										} /* SET  0,L		  */
+OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) );								} /* SET  0,(HL)	  */
+OP(cb,c7) { _A = SET(0,_A); 										} /* SET  0,A		  */
+
+OP(cb,c8) { _B = SET(1,_B); 										} /* SET  1,B		  */
+OP(cb,c9) { _C = SET(1,_C); 										} /* SET  1,C		  */
+OP(cb,ca) { _D = SET(1,_D); 										} /* SET  1,D		  */
+OP(cb,cb) { _E = SET(1,_E); 										} /* SET  1,E		  */
+OP(cb,cc) { _H = SET(1,_H); 										} /* SET  1,H		  */
+OP(cb,cd) { _L = SET(1,_L); 										} /* SET  1,L		  */
+OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) );								} /* SET  1,(HL)	  */
+OP(cb,cf) { _A = SET(1,_A); 										} /* SET  1,A		  */
+
+OP(cb,d0) { _B = SET(2,_B); 										} /* SET  2,B		  */
+OP(cb,d1) { _C = SET(2,_C); 										} /* SET  2,C		  */
+OP(cb,d2) { _D = SET(2,_D); 										} /* SET  2,D		  */
+OP(cb,d3) { _E = SET(2,_E); 										} /* SET  2,E		  */
+OP(cb,d4) { _H = SET(2,_H); 										} /* SET  2,H		  */
+OP(cb,d5) { _L = SET(2,_L); 										} /* SET  2,L		  */
+OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) );								}/* SET  2,(HL) 	 */
+OP(cb,d7) { _A = SET(2,_A); 										} /* SET  2,A		  */
+
+OP(cb,d8) { _B = SET(3,_B); 										} /* SET  3,B		  */
+OP(cb,d9) { _C = SET(3,_C); 										} /* SET  3,C		  */
+OP(cb,da) { _D = SET(3,_D); 										} /* SET  3,D		  */
+OP(cb,db) { _E = SET(3,_E); 										} /* SET  3,E		  */
+OP(cb,dc) { _H = SET(3,_H); 										} /* SET  3,H		  */
+OP(cb,dd) { _L = SET(3,_L); 										} /* SET  3,L		  */
+OP(cb,de) { WM( _HL, SET(3,RM(_HL)) );								} /* SET  3,(HL)	  */
+OP(cb,df) { _A = SET(3,_A); 										} /* SET  3,A		  */
+
+OP(cb,e0) { _B = SET(4,_B); 										} /* SET  4,B		  */
+OP(cb,e1) { _C = SET(4,_C); 										} /* SET  4,C		  */
+OP(cb,e2) { _D = SET(4,_D); 										} /* SET  4,D		  */
+OP(cb,e3) { _E = SET(4,_E); 										} /* SET  4,E		  */
+OP(cb,e4) { _H = SET(4,_H); 										} /* SET  4,H		  */
+OP(cb,e5) { _L = SET(4,_L); 										} /* SET  4,L		  */
+OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) );								} /* SET  4,(HL)	  */
+OP(cb,e7) { _A = SET(4,_A); 										} /* SET  4,A		  */
+
+OP(cb,e8) { _B = SET(5,_B); 										} /* SET  5,B		  */
+OP(cb,e9) { _C = SET(5,_C); 										} /* SET  5,C		  */
+OP(cb,ea) { _D = SET(5,_D); 										} /* SET  5,D		  */
+OP(cb,eb) { _E = SET(5,_E); 										} /* SET  5,E		  */
+OP(cb,ec) { _H = SET(5,_H); 										} /* SET  5,H		  */
+OP(cb,ed) { _L = SET(5,_L); 										} /* SET  5,L		  */
+OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) );								} /* SET  5,(HL)	  */
+OP(cb,ef) { _A = SET(5,_A); 										} /* SET  5,A		  */
+
+OP(cb,f0) { _B = SET(6,_B); 										} /* SET  6,B		  */
+OP(cb,f1) { _C = SET(6,_C); 										} /* SET  6,C		  */
+OP(cb,f2) { _D = SET(6,_D); 										} /* SET  6,D		  */
+OP(cb,f3) { _E = SET(6,_E); 										} /* SET  6,E		  */
+OP(cb,f4) { _H = SET(6,_H); 										} /* SET  6,H		  */
+OP(cb,f5) { _L = SET(6,_L); 										} /* SET  6,L		  */
+OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) );								} /* SET  6,(HL)	  */
+OP(cb,f7) { _A = SET(6,_A); 										} /* SET  6,A		  */
+
+OP(cb,f8) { _B = SET(7,_B); 										} /* SET  7,B		  */
+OP(cb,f9) { _C = SET(7,_C); 										} /* SET  7,C		  */
+OP(cb,fa) { _D = SET(7,_D); 										} /* SET  7,D		  */
+OP(cb,fb) { _E = SET(7,_E); 										} /* SET  7,E		  */
+OP(cb,fc) { _H = SET(7,_H); 										} /* SET  7,H		  */
+OP(cb,fd) { _L = SET(7,_L); 										} /* SET  7,L		  */
+OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) );								} /* SET  7,(HL)	  */
+OP(cb,ff) { _A = SET(7,_A); 										} /* SET  7,A		  */
+
+
+/**********************************************************
+* opcodes with DD/FD CB prefix
+* rotate, shift and bit operations with (IX+o)
+**********************************************************/
+OP(xxcb,00) { _B = RLC( RM(EA) ); WM( EA,_B );						} /* RLC  B=(XY+o)	  */
+OP(xxcb,01) { _C = RLC( RM(EA) ); WM( EA,_C );						} /* RLC  C=(XY+o)	  */
+OP(xxcb,02) { _D = RLC( RM(EA) ); WM( EA,_D );						} /* RLC  D=(XY+o)	  */
+OP(xxcb,03) { _E = RLC( RM(EA) ); WM( EA,_E );						} /* RLC  E=(XY+o)	  */
+OP(xxcb,04) { _H = RLC( RM(EA) ); WM( EA,_H );						} /* RLC  H=(XY+o)	  */
+OP(xxcb,05) { _L = RLC( RM(EA) ); WM( EA,_L );						} /* RLC  L=(XY+o)	  */
+OP(xxcb,06) { WM( EA, RLC( RM(EA) ) );								} /* RLC  (XY+o)	  */
+OP(xxcb,07) { _A = RLC( RM(EA) ); WM( EA,_A );						} /* RLC  A=(XY+o)	  */
+
+OP(xxcb,08) { _B = RRC( RM(EA) ); WM( EA,_B );						} /* RRC  B=(XY+o)	  */
+OP(xxcb,09) { _C = RRC( RM(EA) ); WM( EA,_C );						} /* RRC  C=(XY+o)	  */
+OP(xxcb,0a) { _D = RRC( RM(EA) ); WM( EA,_D );						} /* RRC  D=(XY+o)	  */
+OP(xxcb,0b) { _E = RRC( RM(EA) ); WM( EA,_E );						} /* RRC  E=(XY+o)	  */
+OP(xxcb,0c) { _H = RRC( RM(EA) ); WM( EA,_H );						} /* RRC  H=(XY+o)	  */
+OP(xxcb,0d) { _L = RRC( RM(EA) ); WM( EA,_L );						} /* RRC  L=(XY+o)	  */
+OP(xxcb,0e) { WM( EA,RRC( RM(EA) ) );								} /* RRC  (XY+o)	  */
+OP(xxcb,0f) { _A = RRC( RM(EA) ); WM( EA,_A );						} /* RRC  A=(XY+o)	  */
+
+OP(xxcb,10) { _B = RL( RM(EA) ); WM( EA,_B );						} /* RL   B=(XY+o)	  */
+OP(xxcb,11) { _C = RL( RM(EA) ); WM( EA,_C );						} /* RL   C=(XY+o)	  */
+OP(xxcb,12) { _D = RL( RM(EA) ); WM( EA,_D );						} /* RL   D=(XY+o)	  */
+OP(xxcb,13) { _E = RL( RM(EA) ); WM( EA,_E );						} /* RL   E=(XY+o)	  */
+OP(xxcb,14) { _H = RL( RM(EA) ); WM( EA,_H );						} /* RL   H=(XY+o)	  */
+OP(xxcb,15) { _L = RL( RM(EA) ); WM( EA,_L );						} /* RL   L=(XY+o)	  */
+OP(xxcb,16) { WM( EA,RL( RM(EA) ) );								} /* RL   (XY+o)	  */
+OP(xxcb,17) { _A = RL( RM(EA) ); WM( EA,_A );						} /* RL   A=(XY+o)	  */
+
+OP(xxcb,18) { _B = RR( RM(EA) ); WM( EA,_B );						} /* RR   B=(XY+o)	  */
+OP(xxcb,19) { _C = RR( RM(EA) ); WM( EA,_C );						} /* RR   C=(XY+o)	  */
+OP(xxcb,1a) { _D = RR( RM(EA) ); WM( EA,_D );						} /* RR   D=(XY+o)	  */
+OP(xxcb,1b) { _E = RR( RM(EA) ); WM( EA,_E );						} /* RR   E=(XY+o)	  */
+OP(xxcb,1c) { _H = RR( RM(EA) ); WM( EA,_H );						} /* RR   H=(XY+o)	  */
+OP(xxcb,1d) { _L = RR( RM(EA) ); WM( EA,_L );						} /* RR   L=(XY+o)	  */
+OP(xxcb,1e) { WM( EA,RR( RM(EA) ) );								} /* RR   (XY+o)	  */
+OP(xxcb,1f) { _A = RR( RM(EA) ); WM( EA,_A );						} /* RR   A=(XY+o)	  */
+
+OP(xxcb,20) { _B = SLA( RM(EA) ); WM( EA,_B );						} /* SLA  B=(XY+o)	  */
+OP(xxcb,21) { _C = SLA( RM(EA) ); WM( EA,_C );						} /* SLA  C=(XY+o)	  */
+OP(xxcb,22) { _D = SLA( RM(EA) ); WM( EA,_D );						} /* SLA  D=(XY+o)	  */
+OP(xxcb,23) { _E = SLA( RM(EA) ); WM( EA,_E );						} /* SLA  E=(XY+o)	  */
+OP(xxcb,24) { _H = SLA( RM(EA) ); WM( EA,_H );						} /* SLA  H=(XY+o)	  */
+OP(xxcb,25) { _L = SLA( RM(EA) ); WM( EA,_L );						} /* SLA  L=(XY+o)	  */
+OP(xxcb,26) { WM( EA,SLA( RM(EA) ) );								} /* SLA  (XY+o)	  */
+OP(xxcb,27) { _A = SLA( RM(EA) ); WM( EA,_A );						} /* SLA  A=(XY+o)	  */
+
+OP(xxcb,28) { _B = SRA( RM(EA) ); WM( EA,_B );						} /* SRA  B=(XY+o)	  */
+OP(xxcb,29) { _C = SRA( RM(EA) ); WM( EA,_C );						} /* SRA  C=(XY+o)	  */
+OP(xxcb,2a) { _D = SRA( RM(EA) ); WM( EA,_D );						} /* SRA  D=(XY+o)	  */
+OP(xxcb,2b) { _E = SRA( RM(EA) ); WM( EA,_E );						} /* SRA  E=(XY+o)	  */
+OP(xxcb,2c) { _H = SRA( RM(EA) ); WM( EA,_H );						} /* SRA  H=(XY+o)	  */
+OP(xxcb,2d) { _L = SRA( RM(EA) ); WM( EA,_L );						} /* SRA  L=(XY+o)	  */
+OP(xxcb,2e) { WM( EA,SRA( RM(EA) ) );								} /* SRA  (XY+o)	  */
+OP(xxcb,2f) { _A = SRA( RM(EA) ); WM( EA,_A );						} /* SRA  A=(XY+o)	  */
+
+OP(xxcb,30) { _B = SLL( RM(EA) ); WM( EA,_B );						} /* SLL  B=(XY+o)	  */
+OP(xxcb,31) { _C = SLL( RM(EA) ); WM( EA,_C );						} /* SLL  C=(XY+o)	  */
+OP(xxcb,32) { _D = SLL( RM(EA) ); WM( EA,_D );						} /* SLL  D=(XY+o)	  */
+OP(xxcb,33) { _E = SLL( RM(EA) ); WM( EA,_E );						} /* SLL  E=(XY+o)	  */
+OP(xxcb,34) { _H = SLL( RM(EA) ); WM( EA,_H );						} /* SLL  H=(XY+o)	  */
+OP(xxcb,35) { _L = SLL( RM(EA) ); WM( EA,_L );						} /* SLL  L=(XY+o)	  */
+OP(xxcb,36) { WM( EA,SLL( RM(EA) ) );								} /* SLL  (XY+o)	  */
+OP(xxcb,37) { _A = SLL( RM(EA) ); WM( EA,_A );						} /* SLL  A=(XY+o)	  */
+
+OP(xxcb,38) { _B = SRL( RM(EA) ); WM( EA,_B );						} /* SRL  B=(XY+o)	  */
+OP(xxcb,39) { _C = SRL( RM(EA) ); WM( EA,_C );						} /* SRL  C=(XY+o)	  */
+OP(xxcb,3a) { _D = SRL( RM(EA) ); WM( EA,_D );						} /* SRL  D=(XY+o)	  */
+OP(xxcb,3b) { _E = SRL( RM(EA) ); WM( EA,_E );						} /* SRL  E=(XY+o)	  */
+OP(xxcb,3c) { _H = SRL( RM(EA) ); WM( EA,_H );						} /* SRL  H=(XY+o)	  */
+OP(xxcb,3d) { _L = SRL( RM(EA) ); WM( EA,_L );						} /* SRL  L=(XY+o)	  */
+OP(xxcb,3e) { WM( EA,SRL( RM(EA) ) );								} /* SRL  (XY+o)	  */
+OP(xxcb,3f) { _A = SRL( RM(EA) ); WM( EA,_A );						} /* SRL  A=(XY+o)	  */
+
+OP(xxcb,40) { xxcb_46();											} /* BIT  0,B=(XY+o)  */
+OP(xxcb,41) { xxcb_46();													  } /* BIT	0,C=(XY+o)	*/
+OP(xxcb,42) { xxcb_46();											} /* BIT  0,D=(XY+o)  */
+OP(xxcb,43) { xxcb_46();											} /* BIT  0,E=(XY+o)  */
+OP(xxcb,44) { xxcb_46();											} /* BIT  0,H=(XY+o)  */
+OP(xxcb,45) { xxcb_46();											} /* BIT  0,L=(XY+o)  */
+OP(xxcb,46) { BIT_XY(0,RM(EA)); 									} /* BIT  0,(XY+o)	  */
+OP(xxcb,47) { xxcb_46();											} /* BIT  0,A=(XY+o)  */
+
+OP(xxcb,48) { xxcb_4e();											} /* BIT  1,B=(XY+o)  */
+OP(xxcb,49) { xxcb_4e();													  } /* BIT	1,C=(XY+o)	*/
+OP(xxcb,4a) { xxcb_4e();											} /* BIT  1,D=(XY+o)  */
+OP(xxcb,4b) { xxcb_4e();											} /* BIT  1,E=(XY+o)  */
+OP(xxcb,4c) { xxcb_4e();											} /* BIT  1,H=(XY+o)  */
+OP(xxcb,4d) { xxcb_4e();											} /* BIT  1,L=(XY+o)  */
+OP(xxcb,4e) { BIT_XY(1,RM(EA)); 									} /* BIT  1,(XY+o)	  */
+OP(xxcb,4f) { xxcb_4e();											} /* BIT  1,A=(XY+o)  */
+
+OP(xxcb,50) { xxcb_56();											} /* BIT  2,B=(XY+o)  */
+OP(xxcb,51) { xxcb_56();													  } /* BIT	2,C=(XY+o)	*/
+OP(xxcb,52) { xxcb_56();											} /* BIT  2,D=(XY+o)  */
+OP(xxcb,53) { xxcb_56();											} /* BIT  2,E=(XY+o)  */
+OP(xxcb,54) { xxcb_56();											} /* BIT  2,H=(XY+o)  */
+OP(xxcb,55) { xxcb_56();											} /* BIT  2,L=(XY+o)  */
+OP(xxcb,56) { BIT_XY(2,RM(EA)); 									} /* BIT  2,(XY+o)	  */
+OP(xxcb,57) { xxcb_56();											} /* BIT  2,A=(XY+o)  */
+
+OP(xxcb,58) { xxcb_5e();											} /* BIT  3,B=(XY+o)  */
+OP(xxcb,59) { xxcb_5e();													  } /* BIT	3,C=(XY+o)	*/
+OP(xxcb,5a) { xxcb_5e();											} /* BIT  3,D=(XY+o)  */
+OP(xxcb,5b) { xxcb_5e();											} /* BIT  3,E=(XY+o)  */
+OP(xxcb,5c) { xxcb_5e();											} /* BIT  3,H=(XY+o)  */
+OP(xxcb,5d) { xxcb_5e();											} /* BIT  3,L=(XY+o)  */
+OP(xxcb,5e) { BIT_XY(3,RM(EA)); 									} /* BIT  3,(XY+o)	  */
+OP(xxcb,5f) { xxcb_5e();											} /* BIT  3,A=(XY+o)  */
+
+OP(xxcb,60) { xxcb_66();											} /* BIT  4,B=(XY+o)  */
+OP(xxcb,61) { xxcb_66();													  } /* BIT	4,C=(XY+o)	*/
+OP(xxcb,62) { xxcb_66();											} /* BIT  4,D=(XY+o)  */
+OP(xxcb,63) { xxcb_66();											} /* BIT  4,E=(XY+o)  */
+OP(xxcb,64) { xxcb_66();											} /* BIT  4,H=(XY+o)  */
+OP(xxcb,65) { xxcb_66();											} /* BIT  4,L=(XY+o)  */
+OP(xxcb,66) { BIT_XY(4,RM(EA)); 									} /* BIT  4,(XY+o)	  */
+OP(xxcb,67) { xxcb_66();											} /* BIT  4,A=(XY+o)  */
+
+OP(xxcb,68) { xxcb_6e();											} /* BIT  5,B=(XY+o)  */
+OP(xxcb,69) { xxcb_6e();													  } /* BIT	5,C=(XY+o)	*/
+OP(xxcb,6a) { xxcb_6e();											} /* BIT  5,D=(XY+o)  */
+OP(xxcb,6b) { xxcb_6e();											} /* BIT  5,E=(XY+o)  */
+OP(xxcb,6c) { xxcb_6e();											} /* BIT  5,H=(XY+o)  */
+OP(xxcb,6d) { xxcb_6e();											} /* BIT  5,L=(XY+o)  */
+OP(xxcb,6e) { BIT_XY(5,RM(EA)); 									} /* BIT  5,(XY+o)	  */
+OP(xxcb,6f) { xxcb_6e();											} /* BIT  5,A=(XY+o)  */
+
+OP(xxcb,70) { xxcb_76();											} /* BIT  6,B=(XY+o)  */
+OP(xxcb,71) { xxcb_76();													  } /* BIT	6,C=(XY+o)	*/
+OP(xxcb,72) { xxcb_76();											} /* BIT  6,D=(XY+o)  */
+OP(xxcb,73) { xxcb_76();											} /* BIT  6,E=(XY+o)  */
+OP(xxcb,74) { xxcb_76();											} /* BIT  6,H=(XY+o)  */
+OP(xxcb,75) { xxcb_76();											} /* BIT  6,L=(XY+o)  */
+OP(xxcb,76) { BIT_XY(6,RM(EA)); 									} /* BIT  6,(XY+o)	  */
+OP(xxcb,77) { xxcb_76();											} /* BIT  6,A=(XY+o)  */
+
+OP(xxcb,78) { xxcb_7e();											} /* BIT  7,B=(XY+o)  */
+OP(xxcb,79) { xxcb_7e();													  } /* BIT	7,C=(XY+o)	*/
+OP(xxcb,7a) { xxcb_7e();											} /* BIT  7,D=(XY+o)  */
+OP(xxcb,7b) { xxcb_7e();											} /* BIT  7,E=(XY+o)  */
+OP(xxcb,7c) { xxcb_7e();											} /* BIT  7,H=(XY+o)  */
+OP(xxcb,7d) { xxcb_7e();											} /* BIT  7,L=(XY+o)  */
+OP(xxcb,7e) { BIT_XY(7,RM(EA)); 									} /* BIT  7,(XY+o)	  */
+OP(xxcb,7f) { xxcb_7e();											} /* BIT  7,A=(XY+o)  */
+
+OP(xxcb,80) { _B = RES(0, RM(EA) ); WM( EA,_B );					} /* RES  0,B=(XY+o)  */
+OP(xxcb,81) { _C = RES(0, RM(EA) ); WM( EA,_C );					} /* RES  0,C=(XY+o)  */
+OP(xxcb,82) { _D = RES(0, RM(EA) ); WM( EA,_D );					} /* RES  0,D=(XY+o)  */
+OP(xxcb,83) { _E = RES(0, RM(EA) ); WM( EA,_E );					} /* RES  0,E=(XY+o)  */
+OP(xxcb,84) { _H = RES(0, RM(EA) ); WM( EA,_H );					} /* RES  0,H=(XY+o)  */
+OP(xxcb,85) { _L = RES(0, RM(EA) ); WM( EA,_L );					} /* RES  0,L=(XY+o)  */
+OP(xxcb,86) { WM( EA, RES(0,RM(EA)) );								} /* RES  0,(XY+o)	  */
+OP(xxcb,87) { _A = RES(0, RM(EA) ); WM( EA,_A );					} /* RES  0,A=(XY+o)  */
+
+OP(xxcb,88) { _B = RES(1, RM(EA) ); WM( EA,_B );					} /* RES  1,B=(XY+o)  */
+OP(xxcb,89) { _C = RES(1, RM(EA) ); WM( EA,_C );					} /* RES  1,C=(XY+o)  */
+OP(xxcb,8a) { _D = RES(1, RM(EA) ); WM( EA,_D );					} /* RES  1,D=(XY+o)  */
+OP(xxcb,8b) { _E = RES(1, RM(EA) ); WM( EA,_E );					} /* RES  1,E=(XY+o)  */
+OP(xxcb,8c) { _H = RES(1, RM(EA) ); WM( EA,_H );					} /* RES  1,H=(XY+o)  */
+OP(xxcb,8d) { _L = RES(1, RM(EA) ); WM( EA,_L );					} /* RES  1,L=(XY+o)  */
+OP(xxcb,8e) { WM( EA, RES(1,RM(EA)) );								} /* RES  1,(XY+o)	  */
+OP(xxcb,8f) { _A = RES(1, RM(EA) ); WM( EA,_A );					} /* RES  1,A=(XY+o)  */
+
+OP(xxcb,90) { _B = RES(2, RM(EA) ); WM( EA,_B );					} /* RES  2,B=(XY+o)  */
+OP(xxcb,91) { _C = RES(2, RM(EA) ); WM( EA,_C );					} /* RES  2,C=(XY+o)  */
+OP(xxcb,92) { _D = RES(2, RM(EA) ); WM( EA,_D );					} /* RES  2,D=(XY+o)  */
+OP(xxcb,93) { _E = RES(2, RM(EA) ); WM( EA,_E );					} /* RES  2,E=(XY+o)  */
+OP(xxcb,94) { _H = RES(2, RM(EA) ); WM( EA,_H );					} /* RES  2,H=(XY+o)  */
+OP(xxcb,95) { _L = RES(2, RM(EA) ); WM( EA,_L );					} /* RES  2,L=(XY+o)  */
+OP(xxcb,96) { WM( EA, RES(2,RM(EA)) );								} /* RES  2,(XY+o)	  */
+OP(xxcb,97) { _A = RES(2, RM(EA) ); WM( EA,_A );					} /* RES  2,A=(XY+o)  */
+
+OP(xxcb,98) { _B = RES(3, RM(EA) ); WM( EA,_B );					} /* RES  3,B=(XY+o)  */
+OP(xxcb,99) { _C = RES(3, RM(EA) ); WM( EA,_C );					} /* RES  3,C=(XY+o)  */
+OP(xxcb,9a) { _D = RES(3, RM(EA) ); WM( EA,_D );					} /* RES  3,D=(XY+o)  */
+OP(xxcb,9b) { _E = RES(3, RM(EA) ); WM( EA,_E );					} /* RES  3,E=(XY+o)  */
+OP(xxcb,9c) { _H = RES(3, RM(EA) ); WM( EA,_H );					} /* RES  3,H=(XY+o)  */
+OP(xxcb,9d) { _L = RES(3, RM(EA) ); WM( EA,_L );					} /* RES  3,L=(XY+o)  */
+OP(xxcb,9e) { WM( EA, RES(3,RM(EA)) );								} /* RES  3,(XY+o)	  */
+OP(xxcb,9f) { _A = RES(3, RM(EA) ); WM( EA,_A );					} /* RES  3,A=(XY+o)  */
+
+OP(xxcb,a0) { _B = RES(4, RM(EA) ); WM( EA,_B );					} /* RES  4,B=(XY+o)  */
+OP(xxcb,a1) { _C = RES(4, RM(EA) ); WM( EA,_C );					} /* RES  4,C=(XY+o)  */
+OP(xxcb,a2) { _D = RES(4, RM(EA) ); WM( EA,_D );					} /* RES  4,D=(XY+o)  */
+OP(xxcb,a3) { _E = RES(4, RM(EA) ); WM( EA,_E );					} /* RES  4,E=(XY+o)  */
+OP(xxcb,a4) { _H = RES(4, RM(EA) ); WM( EA,_H );					} /* RES  4,H=(XY+o)  */
+OP(xxcb,a5) { _L = RES(4, RM(EA) ); WM( EA,_L );					} /* RES  4,L=(XY+o)  */
+OP(xxcb,a6) { WM( EA, RES(4,RM(EA)) );								} /* RES  4,(XY+o)	  */
+OP(xxcb,a7) { _A = RES(4, RM(EA) ); WM( EA,_A );					} /* RES  4,A=(XY+o)  */
+
+OP(xxcb,a8) { _B = RES(5, RM(EA) ); WM( EA,_B );					} /* RES  5,B=(XY+o)  */
+OP(xxcb,a9) { _C = RES(5, RM(EA) ); WM( EA,_C );					} /* RES  5,C=(XY+o)  */
+OP(xxcb,aa) { _D = RES(5, RM(EA) ); WM( EA,_D );					} /* RES  5,D=(XY+o)  */
+OP(xxcb,ab) { _E = RES(5, RM(EA) ); WM( EA,_E );					} /* RES  5,E=(XY+o)  */
+OP(xxcb,ac) { _H = RES(5, RM(EA) ); WM( EA,_H );					} /* RES  5,H=(XY+o)  */
+OP(xxcb,ad) { _L = RES(5, RM(EA) ); WM( EA,_L );					} /* RES  5,L=(XY+o)  */
+OP(xxcb,ae) { WM( EA, RES(5,RM(EA)) );								} /* RES  5,(XY+o)	  */
+OP(xxcb,af) { _A = RES(5, RM(EA) ); WM( EA,_A );					} /* RES  5,A=(XY+o)  */
+
+OP(xxcb,b0) { _B = RES(6, RM(EA) ); WM( EA,_B );					} /* RES  6,B=(XY+o)  */
+OP(xxcb,b1) { _C = RES(6, RM(EA) ); WM( EA,_C );					} /* RES  6,C=(XY+o)  */
+OP(xxcb,b2) { _D = RES(6, RM(EA) ); WM( EA,_D );					} /* RES  6,D=(XY+o)  */
+OP(xxcb,b3) { _E = RES(6, RM(EA) ); WM( EA,_E );					} /* RES  6,E=(XY+o)  */
+OP(xxcb,b4) { _H = RES(6, RM(EA) ); WM( EA,_H );					} /* RES  6,H=(XY+o)  */
+OP(xxcb,b5) { _L = RES(6, RM(EA) ); WM( EA,_L );					} /* RES  6,L=(XY+o)  */
+OP(xxcb,b6) { WM( EA, RES(6,RM(EA)) );								} /* RES  6,(XY+o)	  */
+OP(xxcb,b7) { _A = RES(6, RM(EA) ); WM( EA,_A );					} /* RES  6,A=(XY+o)  */
+
+OP(xxcb,b8) { _B = RES(7, RM(EA) ); WM( EA,_B );					} /* RES  7,B=(XY+o)  */
+OP(xxcb,b9) { _C = RES(7, RM(EA) ); WM( EA,_C );					} /* RES  7,C=(XY+o)  */
+OP(xxcb,ba) { _D = RES(7, RM(EA) ); WM( EA,_D );					} /* RES  7,D=(XY+o)  */
+OP(xxcb,bb) { _E = RES(7, RM(EA) ); WM( EA,_E );					} /* RES  7,E=(XY+o)  */
+OP(xxcb,bc) { _H = RES(7, RM(EA) ); WM( EA,_H );					} /* RES  7,H=(XY+o)  */
+OP(xxcb,bd) { _L = RES(7, RM(EA) ); WM( EA,_L );					} /* RES  7,L=(XY+o)  */
+OP(xxcb,be) { WM( EA, RES(7,RM(EA)) );								} /* RES  7,(XY+o)	  */
+OP(xxcb,bf) { _A = RES(7, RM(EA) ); WM( EA,_A );					} /* RES  7,A=(XY+o)  */
+
+OP(xxcb,c0) { _B = SET(0, RM(EA) ); WM( EA,_B );					} /* SET  0,B=(XY+o)  */
+OP(xxcb,c1) { _C = SET(0, RM(EA) ); WM( EA,_C );					} /* SET  0,C=(XY+o)  */
+OP(xxcb,c2) { _D = SET(0, RM(EA) ); WM( EA,_D );					} /* SET  0,D=(XY+o)  */
+OP(xxcb,c3) { _E = SET(0, RM(EA) ); WM( EA,_E );					} /* SET  0,E=(XY+o)  */
+OP(xxcb,c4) { _H = SET(0, RM(EA) ); WM( EA,_H );					} /* SET  0,H=(XY+o)  */
+OP(xxcb,c5) { _L = SET(0, RM(EA) ); WM( EA,_L );					} /* SET  0,L=(XY+o)  */
+OP(xxcb,c6) { WM( EA, SET(0,RM(EA)) );								} /* SET  0,(XY+o)	  */
+OP(xxcb,c7) { _A = SET(0, RM(EA) ); WM( EA,_A );					} /* SET  0,A=(XY+o)  */
+
+OP(xxcb,c8) { _B = SET(1, RM(EA) ); WM( EA,_B );					} /* SET  1,B=(XY+o)  */
+OP(xxcb,c9) { _C = SET(1, RM(EA) ); WM( EA,_C );					} /* SET  1,C=(XY+o)  */
+OP(xxcb,ca) { _D = SET(1, RM(EA) ); WM( EA,_D );					} /* SET  1,D=(XY+o)  */
+OP(xxcb,cb) { _E = SET(1, RM(EA) ); WM( EA,_E );					} /* SET  1,E=(XY+o)  */
+OP(xxcb,cc) { _H = SET(1, RM(EA) ); WM( EA,_H );					} /* SET  1,H=(XY+o)  */
+OP(xxcb,cd) { _L = SET(1, RM(EA) ); WM( EA,_L );					} /* SET  1,L=(XY+o)  */
+OP(xxcb,ce) { WM( EA, SET(1,RM(EA)) );								} /* SET  1,(XY+o)	  */
+OP(xxcb,cf) { _A = SET(1, RM(EA) ); WM( EA,_A );					} /* SET  1,A=(XY+o)  */
+
+OP(xxcb,d0) { _B = SET(2, RM(EA) ); WM( EA,_B );					} /* SET  2,B=(XY+o)  */
+OP(xxcb,d1) { _C = SET(2, RM(EA) ); WM( EA,_C );					} /* SET  2,C=(XY+o)  */
+OP(xxcb,d2) { _D = SET(2, RM(EA) ); WM( EA,_D );					} /* SET  2,D=(XY+o)  */
+OP(xxcb,d3) { _E = SET(2, RM(EA) ); WM( EA,_E );					} /* SET  2,E=(XY+o)  */
+OP(xxcb,d4) { _H = SET(2, RM(EA) ); WM( EA,_H );					} /* SET  2,H=(XY+o)  */
+OP(xxcb,d5) { _L = SET(2, RM(EA) ); WM( EA,_L );					} /* SET  2,L=(XY+o)  */
+OP(xxcb,d6) { WM( EA, SET(2,RM(EA)) );								} /* SET  2,(XY+o)	  */
+OP(xxcb,d7) { _A = SET(2, RM(EA) ); WM( EA,_A );					} /* SET  2,A=(XY+o)  */
+
+OP(xxcb,d8) { _B = SET(3, RM(EA) ); WM( EA,_B );					} /* SET  3,B=(XY+o)  */
+OP(xxcb,d9) { _C = SET(3, RM(EA) ); WM( EA,_C );					} /* SET  3,C=(XY+o)  */
+OP(xxcb,da) { _D = SET(3, RM(EA) ); WM( EA,_D );					} /* SET  3,D=(XY+o)  */
+OP(xxcb,db) { _E = SET(3, RM(EA) ); WM( EA,_E );					} /* SET  3,E=(XY+o)  */
+OP(xxcb,dc) { _H = SET(3, RM(EA) ); WM( EA,_H );					} /* SET  3,H=(XY+o)  */
+OP(xxcb,dd) { _L = SET(3, RM(EA) ); WM( EA,_L );					} /* SET  3,L=(XY+o)  */
+OP(xxcb,de) { WM( EA, SET(3,RM(EA)) );								} /* SET  3,(XY+o)	  */
+OP(xxcb,df) { _A = SET(3, RM(EA) ); WM( EA,_A );					} /* SET  3,A=(XY+o)  */
+
+OP(xxcb,e0) { _B = SET(4, RM(EA) ); WM( EA,_B );					} /* SET  4,B=(XY+o)  */
+OP(xxcb,e1) { _C = SET(4, RM(EA) ); WM( EA,_C );					} /* SET  4,C=(XY+o)  */
+OP(xxcb,e2) { _D = SET(4, RM(EA) ); WM( EA,_D );					} /* SET  4,D=(XY+o)  */
+OP(xxcb,e3) { _E = SET(4, RM(EA) ); WM( EA,_E );					} /* SET  4,E=(XY+o)  */
+OP(xxcb,e4) { _H = SET(4, RM(EA) ); WM( EA,_H );					} /* SET  4,H=(XY+o)  */
+OP(xxcb,e5) { _L = SET(4, RM(EA) ); WM( EA,_L );					} /* SET  4,L=(XY+o)  */
+OP(xxcb,e6) { WM( EA, SET(4,RM(EA)) );								} /* SET  4,(XY+o)	  */
+OP(xxcb,e7) { _A = SET(4, RM(EA) ); WM( EA,_A );					} /* SET  4,A=(XY+o)  */
+
+OP(xxcb,e8) { _B = SET(5, RM(EA) ); WM( EA,_B );					} /* SET  5,B=(XY+o)  */
+OP(xxcb,e9) { _C = SET(5, RM(EA) ); WM( EA,_C );					} /* SET  5,C=(XY+o)  */
+OP(xxcb,ea) { _D = SET(5, RM(EA) ); WM( EA,_D );					} /* SET  5,D=(XY+o)  */
+OP(xxcb,eb) { _E = SET(5, RM(EA) ); WM( EA,_E );					} /* SET  5,E=(XY+o)  */
+OP(xxcb,ec) { _H = SET(5, RM(EA) ); WM( EA,_H );					} /* SET  5,H=(XY+o)  */
+OP(xxcb,ed) { _L = SET(5, RM(EA) ); WM( EA,_L );					} /* SET  5,L=(XY+o)  */
+OP(xxcb,ee) { WM( EA, SET(5,RM(EA)) );								} /* SET  5,(XY+o)	  */
+OP(xxcb,ef) { _A = SET(5, RM(EA) ); WM( EA,_A );					} /* SET  5,A=(XY+o)  */
+
+OP(xxcb,f0) { _B = SET(6, RM(EA) ); WM( EA,_B );					} /* SET  6,B=(XY+o)  */
+OP(xxcb,f1) { _C = SET(6, RM(EA) ); WM( EA,_C );					} /* SET  6,C=(XY+o)  */
+OP(xxcb,f2) { _D = SET(6, RM(EA) ); WM( EA,_D );					} /* SET  6,D=(XY+o)  */
+OP(xxcb,f3) { _E = SET(6, RM(EA) ); WM( EA,_E );					} /* SET  6,E=(XY+o)  */
+OP(xxcb,f4) { _H = SET(6, RM(EA) ); WM( EA,_H );					} /* SET  6,H=(XY+o)  */
+OP(xxcb,f5) { _L = SET(6, RM(EA) ); WM( EA,_L );					} /* SET  6,L=(XY+o)  */
+OP(xxcb,f6) { WM( EA, SET(6,RM(EA)) );								} /* SET  6,(XY+o)	  */
+OP(xxcb,f7) { _A = SET(6, RM(EA) ); WM( EA,_A );					} /* SET  6,A=(XY+o)  */
+
+OP(xxcb,f8) { _B = SET(7, RM(EA) ); WM( EA,_B );					} /* SET  7,B=(XY+o)  */
+OP(xxcb,f9) { _C = SET(7, RM(EA) ); WM( EA,_C );					} /* SET  7,C=(XY+o)  */
+OP(xxcb,fa) { _D = SET(7, RM(EA) ); WM( EA,_D );					} /* SET  7,D=(XY+o)  */
+OP(xxcb,fb) { _E = SET(7, RM(EA) ); WM( EA,_E );					} /* SET  7,E=(XY+o)  */
+OP(xxcb,fc) { _H = SET(7, RM(EA) ); WM( EA,_H );					} /* SET  7,H=(XY+o)  */
+OP(xxcb,fd) { _L = SET(7, RM(EA) ); WM( EA,_L );					} /* SET  7,L=(XY+o)  */
+OP(xxcb,fe) { WM( EA, SET(7,RM(EA)) );								} /* SET  7,(XY+o)	  */
+OP(xxcb,ff) { _A = SET(7, RM(EA) ); WM( EA,_A );					} /* SET  7,A=(XY+o)  */
+
+OP(illegal,1) {
+	_PC--;
+}
+
+/**********************************************************
+ * IX register related opcodes (DD prefix)
+ **********************************************************/
+OP(dd,00) { illegal_1();											} /* DB   DD		  */
+OP(dd,01) { illegal_1();											} /* DB   DD		  */
+OP(dd,02) { illegal_1();											} /* DB   DD		  */
+OP(dd,03) { illegal_1();											} /* DB   DD		  */
+OP(dd,04) { illegal_1();											} /* DB   DD		  */
+OP(dd,05) { illegal_1();											} /* DB   DD		  */
+OP(dd,06) { illegal_1();											} /* DB   DD		  */
+OP(dd,07) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,08) { illegal_1();											} /* DB   DD		  */
+OP(dd,09) { ADD16(IX,BC);											} /* ADD  IX,BC 	  */
+OP(dd,0a) { illegal_1();											} /* DB   DD		  */
+OP(dd,0b) { illegal_1();											} /* DB   DD		  */
+OP(dd,0c) { illegal_1();											} /* DB   DD		  */
+OP(dd,0d) { illegal_1();											} /* DB   DD		  */
+OP(dd,0e) { illegal_1();											} /* DB   DD		  */
+OP(dd,0f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,10) { illegal_1();											} /* DB   DD		  */
+OP(dd,11) { illegal_1();											} /* DB   DD		  */
+OP(dd,12) { illegal_1();											} /* DB   DD		  */
+OP(dd,13) { illegal_1();											} /* DB   DD		  */
+OP(dd,14) { illegal_1();											} /* DB   DD		  */
+OP(dd,15) { illegal_1();											} /* DB   DD		  */
+OP(dd,16) { illegal_1();											} /* DB   DD		  */
+OP(dd,17) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,18) { illegal_1();											} /* DB   DD		  */
+OP(dd,19) { ADD16(IX,DE);											} /* ADD  IX,DE 	  */
+OP(dd,1a) { illegal_1();											} /* DB   DD		  */
+OP(dd,1b) { illegal_1();											} /* DB   DD		  */
+OP(dd,1c) { illegal_1();											} /* DB   DD		  */
+OP(dd,1d) { illegal_1();											} /* DB   DD		  */
+OP(dd,1e) { illegal_1();											} /* DB   DD		  */
+OP(dd,1f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,20) { illegal_1();											} /* DB   DD		  */
+OP(dd,21) { _IX = ARG16();											} /* LD   IX,w		  */
+OP(dd,22) { EA = ARG16(); WM16( EA, &Z80.IX );						} /* LD   (w),IX	  */
+OP(dd,23) { _IX++;													} /* INC  IX		  */
+OP(dd,24) { _HX = INC(_HX); 										} /* INC  HX		  */
+OP(dd,25) { _HX = DEC(_HX); 										} /* DEC  HX		  */
+OP(dd,26) { _HX = ARG();											} /* LD   HX,n		  */
+OP(dd,27) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,28) { illegal_1();											} /* DB   DD		  */
+OP(dd,29) { ADD16(IX,IX);											} /* ADD  IX,IX 	  */
+OP(dd,2a) { EA = ARG16(); RM16( EA, &Z80.IX );						} /* LD   IX,(w)	  */
+OP(dd,2b) { _IX--;													} /* DEC  IX		  */
+OP(dd,2c) { _LX = INC(_LX); 										} /* INC  LX		  */
+OP(dd,2d) { _LX = DEC(_LX); 										} /* DEC  LX		  */
+OP(dd,2e) { _LX = ARG();											} /* LD   LX,n		  */
+OP(dd,2f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,30) { illegal_1();											} /* DB   DD		  */
+OP(dd,31) { illegal_1();											} /* DB   DD		  */
+OP(dd,32) { illegal_1();											} /* DB   DD		  */
+OP(dd,33) { illegal_1();											} /* DB   DD		  */
+OP(dd,34) { EAX; WM( EA, INC(RM(EA)) ); 							} /* INC  (IX+o)	  */
+OP(dd,35) { EAX; WM( EA, DEC(RM(EA)) ); 							} /* DEC  (IX+o)	  */
+OP(dd,36) { EAX; WM( EA, ARG() );									} /* LD   (IX+o),n	  */
+OP(dd,37) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,38) { illegal_1();											} /* DB   DD		  */
+OP(dd,39) { ADD16(IX,SP);											} /* ADD  IX,SP 	  */
+OP(dd,3a) { illegal_1();											} /* DB   DD		  */
+OP(dd,3b) { illegal_1();											} /* DB   DD		  */
+OP(dd,3c) { illegal_1();											} /* DB   DD		  */
+OP(dd,3d) { illegal_1();											} /* DB   DD		  */
+OP(dd,3e) { illegal_1();											} /* DB   DD		  */
+OP(dd,3f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,40) { illegal_1();											} /* DB   DD		  */
+OP(dd,41) { illegal_1();											} /* DB   DD		  */
+OP(dd,42) { illegal_1();											} /* DB   DD		  */
+OP(dd,43) { illegal_1();											} /* DB   DD		  */
+OP(dd,44) { _B = _HX;												} /* LD   B,HX		  */
+OP(dd,45) { _B = _LX;												} /* LD   B,LX		  */
+OP(dd,46) { EAX; _B = RM(EA);										} /* LD   B,(IX+o)	  */
+OP(dd,47) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,48) { illegal_1();											} /* DB   DD		  */
+OP(dd,49) { illegal_1();											} /* DB   DD		  */
+OP(dd,4a) { illegal_1();											} /* DB   DD		  */
+OP(dd,4b) { illegal_1();											} /* DB   DD		  */
+OP(dd,4c) { _C = _HX;												} /* LD   C,HX		  */
+OP(dd,4d) { _C = _LX;												} /* LD   C,LX		  */
+OP(dd,4e) { EAX; _C = RM(EA);										} /* LD   C,(IX+o)	  */
+OP(dd,4f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,50) { illegal_1();											} /* DB   DD		  */
+OP(dd,51) { illegal_1();											} /* DB   DD		  */
+OP(dd,52) { illegal_1();											} /* DB   DD		  */
+OP(dd,53) { illegal_1();											} /* DB   DD		  */
+OP(dd,54) { _D = _HX;												} /* LD   D,HX		  */
+OP(dd,55) { _D = _LX;												} /* LD   D,LX		  */
+OP(dd,56) { EAX; _D = RM(EA);										} /* LD   D,(IX+o)	  */
+OP(dd,57) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,58) { illegal_1();											} /* DB   DD		  */
+OP(dd,59) { illegal_1();											} /* DB   DD		  */
+OP(dd,5a) { illegal_1();											} /* DB   DD		  */
+OP(dd,5b) { illegal_1();											} /* DB   DD		  */
+OP(dd,5c) { _E = _HX;												} /* LD   E,HX		  */
+OP(dd,5d) { _E = _LX;												} /* LD   E,LX		  */
+OP(dd,5e) { EAX; _E = RM(EA);										} /* LD   E,(IX+o)	  */
+OP(dd,5f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,60) { _HX = _B;												} /* LD   HX,B		  */
+OP(dd,61) { _HX = _C;												} /* LD   HX,C		  */
+OP(dd,62) { _HX = _D;												} /* LD   HX,D		  */
+OP(dd,63) { _HX = _E;												} /* LD   HX,E		  */
+OP(dd,64) { 														} /* LD   HX,HX 	  */
+OP(dd,65) { _HX = _LX;												} /* LD   HX,LX 	  */
+OP(dd,66) { EAX; _H = RM(EA);										} /* LD   H,(IX+o)	  */
+OP(dd,67) { _HX = _A;												} /* LD   HX,A		  */
+
+OP(dd,68) { _LX = _B;												} /* LD   LX,B		  */
+OP(dd,69) { _LX = _C;												} /* LD   LX,C		  */
+OP(dd,6a) { _LX = _D;												} /* LD   LX,D		  */
+OP(dd,6b) { _LX = _E;												} /* LD   LX,E		  */
+OP(dd,6c) { _LX = _HX;												} /* LD   LX,HX 	  */
+OP(dd,6d) { 														} /* LD   LX,LX 	  */
+OP(dd,6e) { EAX; _L = RM(EA);										} /* LD   L,(IX+o)	  */
+OP(dd,6f) { _LX = _A;												} /* LD   LX,A		  */
+
+OP(dd,70) { EAX; WM( EA, _B );										} /* LD   (IX+o),B	  */
+OP(dd,71) { EAX; WM( EA, _C );										} /* LD   (IX+o),C	  */
+OP(dd,72) { EAX; WM( EA, _D );										} /* LD   (IX+o),D	  */
+OP(dd,73) { EAX; WM( EA, _E );										} /* LD   (IX+o),E	  */
+OP(dd,74) { EAX; WM( EA, _H );										} /* LD   (IX+o),H	  */
+OP(dd,75) { EAX; WM( EA, _L );										} /* LD   (IX+o),L	  */
+OP(dd,76) { illegal_1();											}		  /* DB   DD		  */
+OP(dd,77) { EAX; WM( EA, _A );										} /* LD   (IX+o),A	  */
+
+OP(dd,78) { illegal_1();											} /* DB   DD		  */
+OP(dd,79) { illegal_1();											} /* DB   DD		  */
+OP(dd,7a) { illegal_1();											} /* DB   DD		  */
+OP(dd,7b) { illegal_1();											} /* DB   DD		  */
+OP(dd,7c) { _A = _HX;												} /* LD   A,HX		  */
+OP(dd,7d) { _A = _LX;												} /* LD   A,LX		  */
+OP(dd,7e) { EAX; _A = RM(EA);										} /* LD   A,(IX+o)	  */
+OP(dd,7f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,80) { illegal_1();											} /* DB   DD		  */
+OP(dd,81) { illegal_1();											} /* DB   DD		  */
+OP(dd,82) { illegal_1();											} /* DB   DD		  */
+OP(dd,83) { illegal_1();											} /* DB   DD		  */
+OP(dd,84) { ADD(_HX);												} /* ADD  A,HX		  */
+OP(dd,85) { ADD(_LX);												} /* ADD  A,LX		  */
+OP(dd,86) { EAX; ADD(RM(EA));										} /* ADD  A,(IX+o)	  */
+OP(dd,87) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,88) { illegal_1();											} /* DB   DD		  */
+OP(dd,89) { illegal_1();											} /* DB   DD		  */
+OP(dd,8a) { illegal_1();											} /* DB   DD		  */
+OP(dd,8b) { illegal_1();											} /* DB   DD		  */
+OP(dd,8c) { ADC(_HX);												} /* ADC  A,HX		  */
+OP(dd,8d) { ADC(_LX);												} /* ADC  A,LX		  */
+OP(dd,8e) { EAX; ADC(RM(EA));										} /* ADC  A,(IX+o)	  */
+OP(dd,8f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,90) { illegal_1();											} /* DB   DD		  */
+OP(dd,91) { illegal_1();											} /* DB   DD		  */
+OP(dd,92) { illegal_1();											} /* DB   DD		  */
+OP(dd,93) { illegal_1();											} /* DB   DD		  */
+OP(dd,94) { SUB(_HX);												} /* SUB  HX		  */
+OP(dd,95) { SUB(_LX);												} /* SUB  LX		  */
+OP(dd,96) { EAX; SUB(RM(EA));										} /* SUB  (IX+o)	  */
+OP(dd,97) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,98) { illegal_1();											} /* DB   DD		  */
+OP(dd,99) { illegal_1();											} /* DB   DD		  */
+OP(dd,9a) { illegal_1();											} /* DB   DD		  */
+OP(dd,9b) { illegal_1();											} /* DB   DD		  */
+OP(dd,9c) { SBC(_HX);												} /* SBC  A,HX		  */
+OP(dd,9d) { SBC(_LX);												} /* SBC  A,LX		  */
+OP(dd,9e) { EAX; SBC(RM(EA));										} /* SBC  A,(IX+o)	  */
+OP(dd,9f) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,a0) { illegal_1();											} /* DB   DD		  */
+OP(dd,a1) { illegal_1();											} /* DB   DD		  */
+OP(dd,a2) { illegal_1();											} /* DB   DD		  */
+OP(dd,a3) { illegal_1();											} /* DB   DD		  */
+OP(dd,a4) { AND(_HX);												} /* AND  HX		  */
+OP(dd,a5) { AND(_LX);												} /* AND  LX		  */
+OP(dd,a6) { EAX; AND(RM(EA));										} /* AND  (IX+o)	  */
+OP(dd,a7) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,a8) { illegal_1();											} /* DB   DD		  */
+OP(dd,a9) { illegal_1();											} /* DB   DD		  */
+OP(dd,aa) { illegal_1();											} /* DB   DD		  */
+OP(dd,ab) { illegal_1();											} /* DB   DD		  */
+OP(dd,ac) { XOR(_HX);												} /* XOR  HX		  */
+OP(dd,ad) { XOR(_LX);												} /* XOR  LX		  */
+OP(dd,ae) { EAX; XOR(RM(EA));										} /* XOR  (IX+o)	  */
+OP(dd,af) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,b0) { illegal_1();											} /* DB   DD		  */
+OP(dd,b1) { illegal_1();											} /* DB   DD		  */
+OP(dd,b2) { illegal_1();											} /* DB   DD		  */
+OP(dd,b3) { illegal_1();											} /* DB   DD		  */
+OP(dd,b4) { OR(_HX);												} /* OR   HX		  */
+OP(dd,b5) { OR(_LX);												} /* OR   LX		  */
+OP(dd,b6) { EAX; OR(RM(EA));										} /* OR   (IX+o)	  */
+OP(dd,b7) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,b8) { illegal_1();											} /* DB   DD		  */
+OP(dd,b9) { illegal_1();											} /* DB   DD		  */
+OP(dd,ba) { illegal_1();											} /* DB   DD		  */
+OP(dd,bb) { illegal_1();											} /* DB   DD		  */
+OP(dd,bc) { CP(_HX);												} /* CP   HX		  */
+OP(dd,bd) { CP(_LX);												} /* CP   LX		  */
+OP(dd,be) { EAX; CP(RM(EA));										} /* CP   (IX+o)	  */
+OP(dd,bf) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,c0) { illegal_1();											} /* DB   DD		  */
+OP(dd,c1) { illegal_1();											} /* DB   DD		  */
+OP(dd,c2) { illegal_1();											} /* DB   DD		  */
+OP(dd,c3) { illegal_1();											} /* DB   DD		  */
+OP(dd,c4) { illegal_1();											} /* DB   DD		  */
+OP(dd,c5) { illegal_1();											} /* DB   DD		  */
+OP(dd,c6) { illegal_1();											} /* DB   DD		  */
+OP(dd,c7) { illegal_1();											}		  /* DB   DD		  */
+
+OP(dd,c8) { illegal_1();											} /* DB   DD		  */
+OP(dd,c9) { illegal_1();											} /* DB   DD		  */
+OP(dd,ca) { illegal_1();											} /* DB   DD		  */
+OP(dd,cb) { EAX; EXEC(xxcb,ARG());									} /* **   DD CB xx	  */
+OP(dd,cc) { illegal_1();											} /* DB   DD		  */
+OP(dd,cd) { illegal_1();											} /* DB   DD		  */
+OP(dd,ce) { illegal_1();											} /* DB   DD		  */
+OP(dd,cf) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,d0) { illegal_1();											} /* DB   DD		  */
+OP(dd,d1) { illegal_1();											} /* DB   DD		  */
+OP(dd,d2) { illegal_1();											} /* DB   DD		  */
+OP(dd,d3) { illegal_1();											} /* DB   DD		  */
+OP(dd,d4) { illegal_1();											} /* DB   DD		  */
+OP(dd,d5) { illegal_1();											} /* DB   DD		  */
+OP(dd,d6) { illegal_1();											} /* DB   DD		  */
+OP(dd,d7) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,d8) { illegal_1();											} /* DB   DD		  */
+OP(dd,d9) { illegal_1();											} /* DB   DD		  */
+OP(dd,da) { illegal_1();											} /* DB   DD		  */
+OP(dd,db) { illegal_1();											} /* DB   DD		  */
+OP(dd,dc) { illegal_1();											} /* DB   DD		  */
+OP(dd,dd) { illegal_1();											} /* DB   DD		  */
+OP(dd,de) { illegal_1();											} /* DB   DD		  */
+OP(dd,df) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,e0) { illegal_1();											} /* DB   DD		  */
+OP(dd,e1) { POP(IX);												} /* POP  IX		  */
+OP(dd,e2) { illegal_1();											} /* DB   DD		  */
+OP(dd,e3) { EXSP(IX);												} /* EX   (SP),IX	  */
+OP(dd,e4) { illegal_1();											} /* DB   DD		  */
+OP(dd,e5) { PUSH( IX ); 											} /* PUSH IX		  */
+OP(dd,e6) { illegal_1();											} /* DB   DD		  */
+OP(dd,e7) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,e8) { illegal_1();											} /* DB   DD		  */
+OP(dd,e9) { _PC = _IX;                                              } /* JP   (IX)        */
+OP(dd,ea) { illegal_1();											} /* DB   DD		  */
+OP(dd,eb) { illegal_1();											} /* DB   DD		  */
+OP(dd,ec) { illegal_1();											} /* DB   DD		  */
+OP(dd,ed) { illegal_1();											} /* DB   DD		  */
+OP(dd,ee) { illegal_1();											} /* DB   DD		  */
+OP(dd,ef) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,f0) { illegal_1();											} /* DB   DD		  */
+OP(dd,f1) { illegal_1();											} /* DB   DD		  */
+OP(dd,f2) { illegal_1();											} /* DB   DD		  */
+OP(dd,f3) { illegal_1();											} /* DB   DD		  */
+OP(dd,f4) { illegal_1();											} /* DB   DD		  */
+OP(dd,f5) { illegal_1();											} /* DB   DD		  */
+OP(dd,f6) { illegal_1();											} /* DB   DD		  */
+OP(dd,f7) { illegal_1();											} /* DB   DD		  */
+
+OP(dd,f8) { illegal_1();											} /* DB   DD		  */
+OP(dd,f9) { _SP = _IX;												} /* LD   SP,IX 	  */
+OP(dd,fa) { illegal_1();											} /* DB   DD		  */
+OP(dd,fb) { illegal_1();											} /* DB   DD		  */
+OP(dd,fc) { illegal_1();											} /* DB   DD		  */
+OP(dd,fd) { illegal_1();											} /* DB   DD		  */
+OP(dd,fe) { illegal_1();											} /* DB   DD		  */
+OP(dd,ff) { illegal_1();											} /* DB   DD		  */
+
+/**********************************************************
+ * IY register related opcodes (FD prefix)
+ **********************************************************/
+OP(fd,00) { illegal_1();											} /* DB   FD		  */
+OP(fd,01) { illegal_1();											} /* DB   FD		  */
+OP(fd,02) { illegal_1();											} /* DB   FD		  */
+OP(fd,03) { illegal_1();											} /* DB   FD		  */
+OP(fd,04) { illegal_1();											} /* DB   FD		  */
+OP(fd,05) { illegal_1();											} /* DB   FD		  */
+OP(fd,06) { illegal_1();											} /* DB   FD		  */
+OP(fd,07) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,08) { illegal_1();											} /* DB   FD		  */
+OP(fd,09) { ADD16(IY,BC);											} /* ADD  IY,BC 	  */
+OP(fd,0a) { illegal_1();											} /* DB   FD		  */
+OP(fd,0b) { illegal_1();											} /* DB   FD		  */
+OP(fd,0c) { illegal_1();											} /* DB   FD		  */
+OP(fd,0d) { illegal_1();											} /* DB   FD		  */
+OP(fd,0e) { illegal_1();											} /* DB   FD		  */
+OP(fd,0f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,10) { illegal_1();											} /* DB   FD		  */
+OP(fd,11) { illegal_1();											} /* DB   FD		  */
+OP(fd,12) { illegal_1();											} /* DB   FD		  */
+OP(fd,13) { illegal_1();											} /* DB   FD		  */
+OP(fd,14) { illegal_1();											} /* DB   FD		  */
+OP(fd,15) { illegal_1();											} /* DB   FD		  */
+OP(fd,16) { illegal_1();											} /* DB   FD		  */
+OP(fd,17) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,18) { illegal_1();											} /* DB   FD		  */
+OP(fd,19) { ADD16(IY,DE);											} /* ADD  IY,DE 	  */
+OP(fd,1a) { illegal_1();											} /* DB   FD		  */
+OP(fd,1b) { illegal_1();											} /* DB   FD		  */
+OP(fd,1c) { illegal_1();											} /* DB   FD		  */
+OP(fd,1d) { illegal_1();											} /* DB   FD		  */
+OP(fd,1e) { illegal_1();											} /* DB   FD		  */
+OP(fd,1f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,20) { illegal_1();											} /* DB   FD		  */
+OP(fd,21) { _IY = ARG16();											} /* LD   IY,w		  */
+OP(fd,22) { EA = ARG16(); WM16( EA, &Z80.IY );						} /* LD   (w),IY	  */
+OP(fd,23) { _IY++;													} /* INC  IY		  */
+OP(fd,24) { _HY = INC(_HY); 										} /* INC  HY		  */
+OP(fd,25) { _HY = DEC(_HY); 										} /* DEC  HY		  */
+OP(fd,26) { _HY = ARG();											} /* LD   HY,n		  */
+OP(fd,27) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,28) { illegal_1();											} /* DB   FD		  */
+OP(fd,29) { ADD16(IY,IY);											} /* ADD  IY,IY 	  */
+OP(fd,2a) { EA = ARG16(); RM16( EA, &Z80.IY );						} /* LD   IY,(w)	  */
+OP(fd,2b) { _IY--;													} /* DEC  IY		  */
+OP(fd,2c) { _LY = INC(_LY); 										} /* INC  LY		  */
+OP(fd,2d) { _LY = DEC(_LY); 										} /* DEC  LY		  */
+OP(fd,2e) { _LY = ARG();											} /* LD   LY,n		  */
+OP(fd,2f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,30) { illegal_1();											} /* DB   FD		  */
+OP(fd,31) { illegal_1();											} /* DB   FD		  */
+OP(fd,32) { illegal_1();											} /* DB   FD		  */
+OP(fd,33) { illegal_1();											} /* DB   FD		  */
+OP(fd,34) { EAY; WM( EA, INC(RM(EA)) ); 							} /* INC  (IY+o)	  */
+OP(fd,35) { EAY; WM( EA, DEC(RM(EA)) ); 							} /* DEC  (IY+o)	  */
+OP(fd,36) { EAY; WM( EA, ARG() );									} /* LD   (IY+o),n	  */
+OP(fd,37) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,38) { illegal_1();											} /* DB   FD		  */
+OP(fd,39) { ADD16(IY,SP);											} /* ADD  IY,SP 	  */
+OP(fd,3a) { illegal_1();											} /* DB   FD		  */
+OP(fd,3b) { illegal_1();											} /* DB   FD		  */
+OP(fd,3c) { illegal_1();											} /* DB   FD		  */
+OP(fd,3d) { illegal_1();											} /* DB   FD		  */
+OP(fd,3e) { illegal_1();											} /* DB   FD		  */
+OP(fd,3f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,40) { illegal_1();											} /* DB   FD		  */
+OP(fd,41) { illegal_1();											} /* DB   FD		  */
+OP(fd,42) { illegal_1();											} /* DB   FD		  */
+OP(fd,43) { illegal_1();											} /* DB   FD		  */
+OP(fd,44) { _B = _HY;												} /* LD   B,HY		  */
+OP(fd,45) { _B = _LY;												} /* LD   B,LY		  */
+OP(fd,46) { EAY; _B = RM(EA);										} /* LD   B,(IY+o)	  */
+OP(fd,47) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,48) { illegal_1();											} /* DB   FD		  */
+OP(fd,49) { illegal_1();											} /* DB   FD		  */
+OP(fd,4a) { illegal_1();											} /* DB   FD		  */
+OP(fd,4b) { illegal_1();											} /* DB   FD		  */
+OP(fd,4c) { _C = _HY;												} /* LD   C,HY		  */
+OP(fd,4d) { _C = _LY;												} /* LD   C,LY		  */
+OP(fd,4e) { EAY; _C = RM(EA);										} /* LD   C,(IY+o)	  */
+OP(fd,4f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,50) { illegal_1();											} /* DB   FD		  */
+OP(fd,51) { illegal_1();											} /* DB   FD		  */
+OP(fd,52) { illegal_1();											} /* DB   FD		  */
+OP(fd,53) { illegal_1();											} /* DB   FD		  */
+OP(fd,54) { _D = _HY;												} /* LD   D,HY		  */
+OP(fd,55) { _D = _LY;												} /* LD   D,LY		  */
+OP(fd,56) { EAY; _D = RM(EA);										} /* LD   D,(IY+o)	  */
+OP(fd,57) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,58) { illegal_1();											} /* DB   FD		  */
+OP(fd,59) { illegal_1();											} /* DB   FD		  */
+OP(fd,5a) { illegal_1();											} /* DB   FD		  */
+OP(fd,5b) { illegal_1();											} /* DB   FD		  */
+OP(fd,5c) { _E = _HY;												} /* LD   E,HY		  */
+OP(fd,5d) { _E = _LY;												} /* LD   E,LY		  */
+OP(fd,5e) { EAY; _E = RM(EA);										} /* LD   E,(IY+o)	  */
+OP(fd,5f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,60) { _HY = _B;												} /* LD   HY,B		  */
+OP(fd,61) { _HY = _C;												} /* LD   HY,C		  */
+OP(fd,62) { _HY = _D;												} /* LD   HY,D		  */
+OP(fd,63) { _HY = _E;												} /* LD   HY,E		  */
+OP(fd,64) { 														} /* LD   HY,HY 	  */
+OP(fd,65) { _HY = _LY;												} /* LD   HY,LY 	  */
+OP(fd,66) { EAY; _H = RM(EA);										} /* LD   H,(IY+o)	  */
+OP(fd,67) { _HY = _A;												} /* LD   HY,A		  */
+
+OP(fd,68) { _LY = _B;												} /* LD   LY,B		  */
+OP(fd,69) { _LY = _C;												} /* LD   LY,C		  */
+OP(fd,6a) { _LY = _D;												} /* LD   LY,D		  */
+OP(fd,6b) { _LY = _E;												} /* LD   LY,E		  */
+OP(fd,6c) { _LY = _HY;												} /* LD   LY,HY 	  */
+OP(fd,6d) { 														} /* LD   LY,LY 	  */
+OP(fd,6e) { EAY; _L = RM(EA);										} /* LD   L,(IY+o)	  */
+OP(fd,6f) { _LY = _A;												} /* LD   LY,A		  */
+
+OP(fd,70) { EAY; WM( EA, _B );										} /* LD   (IY+o),B	  */
+OP(fd,71) { EAY; WM( EA, _C );										} /* LD   (IY+o),C	  */
+OP(fd,72) { EAY; WM( EA, _D );										} /* LD   (IY+o),D	  */
+OP(fd,73) { EAY; WM( EA, _E );										} /* LD   (IY+o),E	  */
+OP(fd,74) { EAY; WM( EA, _H );										} /* LD   (IY+o),H	  */
+OP(fd,75) { EAY; WM( EA, _L );										} /* LD   (IY+o),L	  */
+OP(fd,76) { illegal_1();											}		  /* DB   FD		  */
+OP(fd,77) { EAY; WM( EA, _A );										} /* LD   (IY+o),A	  */
+
+OP(fd,78) { illegal_1();											} /* DB   FD		  */
+OP(fd,79) { illegal_1();											} /* DB   FD		  */
+OP(fd,7a) { illegal_1();											} /* DB   FD		  */
+OP(fd,7b) { illegal_1();											} /* DB   FD		  */
+OP(fd,7c) { _A = _HY;												} /* LD   A,HY		  */
+OP(fd,7d) { _A = _LY;												} /* LD   A,LY		  */
+OP(fd,7e) { EAY; _A = RM(EA);										} /* LD   A,(IY+o)	  */
+OP(fd,7f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,80) { illegal_1();											} /* DB   FD		  */
+OP(fd,81) { illegal_1();											} /* DB   FD		  */
+OP(fd,82) { illegal_1();											} /* DB   FD		  */
+OP(fd,83) { illegal_1();											} /* DB   FD		  */
+OP(fd,84) { ADD(_HY);												} /* ADD  A,HY		  */
+OP(fd,85) { ADD(_LY);												} /* ADD  A,LY		  */
+OP(fd,86) { EAY; ADD(RM(EA));										} /* ADD  A,(IY+o)	  */
+OP(fd,87) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,88) { illegal_1();											} /* DB   FD		  */
+OP(fd,89) { illegal_1();											} /* DB   FD		  */
+OP(fd,8a) { illegal_1();											} /* DB   FD		  */
+OP(fd,8b) { illegal_1();											} /* DB   FD		  */
+OP(fd,8c) { ADC(_HY);												} /* ADC  A,HY		  */
+OP(fd,8d) { ADC(_LY);												} /* ADC  A,LY		  */
+OP(fd,8e) { EAY; ADC(RM(EA));										} /* ADC  A,(IY+o)	  */
+OP(fd,8f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,90) { illegal_1();											} /* DB   FD		  */
+OP(fd,91) { illegal_1();											} /* DB   FD		  */
+OP(fd,92) { illegal_1();											} /* DB   FD		  */
+OP(fd,93) { illegal_1();											} /* DB   FD		  */
+OP(fd,94) { SUB(_HY);												} /* SUB  HY		  */
+OP(fd,95) { SUB(_LY);												} /* SUB  LY		  */
+OP(fd,96) { EAY; SUB(RM(EA));										} /* SUB  (IY+o)	  */
+OP(fd,97) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,98) { illegal_1();											} /* DB   FD		  */
+OP(fd,99) { illegal_1();											} /* DB   FD		  */
+OP(fd,9a) { illegal_1();											} /* DB   FD		  */
+OP(fd,9b) { illegal_1();											} /* DB   FD		  */
+OP(fd,9c) { SBC(_HY);												} /* SBC  A,HY		  */
+OP(fd,9d) { SBC(_LY);												} /* SBC  A,LY		  */
+OP(fd,9e) { EAY; SBC(RM(EA));										} /* SBC  A,(IY+o)	  */
+OP(fd,9f) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,a0) { illegal_1();											} /* DB   FD		  */
+OP(fd,a1) { illegal_1();											} /* DB   FD		  */
+OP(fd,a2) { illegal_1();											} /* DB   FD		  */
+OP(fd,a3) { illegal_1();											} /* DB   FD		  */
+OP(fd,a4) { AND(_HY);												} /* AND  HY		  */
+OP(fd,a5) { AND(_LY);												} /* AND  LY		  */
+OP(fd,a6) { EAY; AND(RM(EA));										} /* AND  (IY+o)	  */
+OP(fd,a7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,a8) { illegal_1();											} /* DB   FD		  */
+OP(fd,a9) { illegal_1();											} /* DB   FD		  */
+OP(fd,aa) { illegal_1();											} /* DB   FD		  */
+OP(fd,ab) { illegal_1();											} /* DB   FD		  */
+OP(fd,ac) { XOR(_HY);												} /* XOR  HY		  */
+OP(fd,ad) { XOR(_LY);												} /* XOR  LY		  */
+OP(fd,ae) { EAY; XOR(RM(EA));										} /* XOR  (IY+o)	  */
+OP(fd,af) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,b0) { illegal_1();											} /* DB   FD		  */
+OP(fd,b1) { illegal_1();											} /* DB   FD		  */
+OP(fd,b2) { illegal_1();											} /* DB   FD		  */
+OP(fd,b3) { illegal_1();											} /* DB   FD		  */
+OP(fd,b4) { OR(_HY);												} /* OR   HY		  */
+OP(fd,b5) { OR(_LY);												} /* OR   LY		  */
+OP(fd,b6) { EAY; OR(RM(EA));										} /* OR   (IY+o)	  */
+OP(fd,b7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,b8) { illegal_1();											} /* DB   FD		  */
+OP(fd,b9) { illegal_1();											} /* DB   FD		  */
+OP(fd,ba) { illegal_1();											} /* DB   FD		  */
+OP(fd,bb) { illegal_1();											} /* DB   FD		  */
+OP(fd,bc) { CP(_HY);												} /* CP   HY		  */
+OP(fd,bd) { CP(_LY);												} /* CP   LY		  */
+OP(fd,be) { EAY; CP(RM(EA));										} /* CP   (IY+o)	  */
+OP(fd,bf) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,c0) { illegal_1();											} /* DB   FD		  */
+OP(fd,c1) { illegal_1();											} /* DB   FD		  */
+OP(fd,c2) { illegal_1();											} /* DB   FD		  */
+OP(fd,c3) { illegal_1();											} /* DB   FD		  */
+OP(fd,c4) { illegal_1();											} /* DB   FD		  */
+OP(fd,c5) { illegal_1();											} /* DB   FD		  */
+OP(fd,c6) { illegal_1();											} /* DB   FD		  */
+OP(fd,c7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,c8) { illegal_1();											} /* DB   FD		  */
+OP(fd,c9) { illegal_1();											} /* DB   FD		  */
+OP(fd,ca) { illegal_1();											} /* DB   FD		  */
+OP(fd,cb) { EAY; EXEC(xxcb,ARG());									} /* **   FD CB xx	  */
+OP(fd,cc) { illegal_1();											} /* DB   FD		  */
+OP(fd,cd) { illegal_1();											} /* DB   FD		  */
+OP(fd,ce) { illegal_1();											} /* DB   FD		  */
+OP(fd,cf) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,d0) { illegal_1();											} /* DB   FD		  */
+OP(fd,d1) { illegal_1();											} /* DB   FD		  */
+OP(fd,d2) { illegal_1();											} /* DB   FD		  */
+OP(fd,d3) { illegal_1();											} /* DB   FD		  */
+OP(fd,d4) { illegal_1();											} /* DB   FD		  */
+OP(fd,d5) { illegal_1();											} /* DB   FD		  */
+OP(fd,d6) { illegal_1();											} /* DB   FD		  */
+OP(fd,d7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,d8) { illegal_1();											} /* DB   FD		  */
+OP(fd,d9) { illegal_1();											} /* DB   FD		  */
+OP(fd,da) { illegal_1();											} /* DB   FD		  */
+OP(fd,db) { illegal_1();											} /* DB   FD		  */
+OP(fd,dc) { illegal_1();											} /* DB   FD		  */
+OP(fd,dd) { illegal_1();											} /* DB   FD		  */
+OP(fd,de) { illegal_1();											} /* DB   FD		  */
+OP(fd,df) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,e0) { illegal_1();											} /* DB   FD		  */
+OP(fd,e1) { POP(IY);												} /* POP  IY		  */
+OP(fd,e2) { illegal_1();											} /* DB   FD		  */
+OP(fd,e3) { EXSP(IY);												} /* EX   (SP),IY	  */
+OP(fd,e4) { illegal_1();											} /* DB   FD		  */
+OP(fd,e5) { PUSH( IY ); 											} /* PUSH IY		  */
+OP(fd,e6) { illegal_1();											} /* DB   FD		  */
+OP(fd,e7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,e8) { illegal_1();											} /* DB   FD		  */
+OP(fd,e9) { _PC = _IY;                                              } /* JP   (IY)        */
+OP(fd,ea) { illegal_1();											} /* DB   FD		  */
+OP(fd,eb) { illegal_1();											} /* DB   FD		  */
+OP(fd,ec) { illegal_1();											} /* DB   FD		  */
+OP(fd,ed) { illegal_1();											} /* DB   FD		  */
+OP(fd,ee) { illegal_1();											} /* DB   FD		  */
+OP(fd,ef) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,f0) { illegal_1();											} /* DB   FD		  */
+OP(fd,f1) { illegal_1();											} /* DB   FD		  */
+OP(fd,f2) { illegal_1();											} /* DB   FD		  */
+OP(fd,f3) { illegal_1();											} /* DB   FD		  */
+OP(fd,f4) { illegal_1();											} /* DB   FD		  */
+OP(fd,f5) { illegal_1();											} /* DB   FD		  */
+OP(fd,f6) { illegal_1();											} /* DB   FD		  */
+OP(fd,f7) { illegal_1();											} /* DB   FD		  */
+
+OP(fd,f8) { illegal_1();											} /* DB   FD		  */
+OP(fd,f9) { _SP = _IY;												} /* LD   SP,IY 	  */
+OP(fd,fa) { illegal_1();											} /* DB   FD		  */
+OP(fd,fb) { illegal_1();											} /* DB   FD		  */
+OP(fd,fc) { illegal_1();											} /* DB   FD		  */
+OP(fd,fd) { illegal_1();											} /* DB   FD		  */
+OP(fd,fe) { illegal_1();											} /* DB   FD		  */
+OP(fd,ff) { illegal_1();											} /* DB   FD		  */
+
+OP(illegal,2)
+{
+}
+
+/**********************************************************
+ * special opcodes (ED prefix)
+ **********************************************************/
+OP(ed,00) { illegal_2();											} /* DB   ED		  */
+OP(ed,01) { illegal_2();											} /* DB   ED		  */
+OP(ed,02) { illegal_2();											} /* DB   ED		  */
+OP(ed,03) { illegal_2();											} /* DB   ED		  */
+OP(ed,04) { illegal_2();											} /* DB   ED		  */
+OP(ed,05) { illegal_2();											} /* DB   ED		  */
+OP(ed,06) { illegal_2();											} /* DB   ED		  */
+OP(ed,07) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,08) { illegal_2();											} /* DB   ED		  */
+OP(ed,09) { illegal_2();											} /* DB   ED		  */
+OP(ed,0a) { illegal_2();											} /* DB   ED		  */
+OP(ed,0b) { illegal_2();											} /* DB   ED		  */
+OP(ed,0c) { illegal_2();											} /* DB   ED		  */
+OP(ed,0d) { illegal_2();											} /* DB   ED		  */
+OP(ed,0e) { illegal_2();											} /* DB   ED		  */
+OP(ed,0f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,10) { illegal_2();											} /* DB   ED		  */
+OP(ed,11) { illegal_2();											} /* DB   ED		  */
+OP(ed,12) { illegal_2();											} /* DB   ED		  */
+OP(ed,13) { illegal_2();											} /* DB   ED		  */
+OP(ed,14) { illegal_2();											} /* DB   ED		  */
+OP(ed,15) { illegal_2();											} /* DB   ED		  */
+OP(ed,16) { illegal_2();											} /* DB   ED		  */
+OP(ed,17) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,18) { illegal_2();											} /* DB   ED		  */
+OP(ed,19) { illegal_2();											} /* DB   ED		  */
+OP(ed,1a) { illegal_2();											} /* DB   ED		  */
+OP(ed,1b) { illegal_2();											} /* DB   ED		  */
+OP(ed,1c) { illegal_2();											} /* DB   ED		  */
+OP(ed,1d) { illegal_2();											} /* DB   ED		  */
+OP(ed,1e) { illegal_2();											} /* DB   ED		  */
+OP(ed,1f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,20) { illegal_2();											} /* DB   ED		  */
+OP(ed,21) { illegal_2();											} /* DB   ED		  */
+OP(ed,22) { illegal_2();											} /* DB   ED		  */
+OP(ed,23) { illegal_2();											} /* DB   ED		  */
+OP(ed,24) { illegal_2();											} /* DB   ED		  */
+OP(ed,25) { illegal_2();											} /* DB   ED		  */
+OP(ed,26) { illegal_2();											} /* DB   ED		  */
+OP(ed,27) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,28) { illegal_2();											} /* DB   ED		  */
+OP(ed,29) { illegal_2();											} /* DB   ED		  */
+OP(ed,2a) { illegal_2();											} /* DB   ED		  */
+OP(ed,2b) { illegal_2();											} /* DB   ED		  */
+OP(ed,2c) { illegal_2();											} /* DB   ED		  */
+OP(ed,2d) { illegal_2();											} /* DB   ED		  */
+OP(ed,2e) { illegal_2();											} /* DB   ED		  */
+OP(ed,2f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,30) { illegal_2();											} /* DB   ED		  */
+OP(ed,31) { illegal_2();											} /* DB   ED		  */
+OP(ed,32) { illegal_2();											} /* DB   ED		  */
+OP(ed,33) { illegal_2();											} /* DB   ED		  */
+OP(ed,34) { illegal_2();											} /* DB   ED		  */
+OP(ed,35) { illegal_2();											} /* DB   ED		  */
+OP(ed,36) { illegal_2();											} /* DB   ED		  */
+OP(ed,37) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,38) { illegal_2();											} /* DB   ED		  */
+OP(ed,39) { illegal_2();											} /* DB   ED		  */
+OP(ed,3a) { illegal_2();											} /* DB   ED		  */
+OP(ed,3b) { illegal_2();											} /* DB   ED		  */
+OP(ed,3c) { illegal_2();											} /* DB   ED		  */
+OP(ed,3d) { illegal_2();											} /* DB   ED		  */
+OP(ed,3e) { illegal_2();											} /* DB   ED		  */
+OP(ed,3f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,40) { _B = IN(_BC); _F = (_F & CF) | SZP[_B]; 				} /* IN   B,(C) 	  */
+OP(ed,41) { OUT(_BC,_B);											} /* OUT  (C),B 	  */
+OP(ed,42) { SBC16( BC );											} /* SBC  HL,BC 	  */
+OP(ed,43) { EA = ARG16(); WM16( EA, &Z80.BC );						} /* LD   (w),BC	  */
+OP(ed,44) { NEG;													} /* NEG			  */
+OP(ed,45) { RETN;													} /* RETN;			  */
+OP(ed,46) { _IM = 0;												} /* IM   0 		  */
+OP(ed,47) { LD_I_A; 												} /* LD   I,A		  */
+
+OP(ed,48) { _C = IN(_BC); _F = (_F & CF) | SZP[_C]; 				} /* IN   C,(C) 	  */
+OP(ed,49) { OUT(_BC,_C);											} /* OUT  (C),C 	  */
+OP(ed,4a) { ADC16( BC );											} /* ADC  HL,BC 	  */
+OP(ed,4b) { EA = ARG16(); RM16( EA, &Z80.BC );						} /* LD   BC,(w)	  */
+OP(ed,4c) { NEG;													} /* NEG			  */
+OP(ed,4d) { RETI;													} /* RETI			  */
+OP(ed,4e) { _IM = 0;												} /* IM   0 		  */
+OP(ed,4f) { LD_R_A; 												} /* LD   R,A		  */
+
+OP(ed,50) { _D = IN(_BC); _F = (_F & CF) | SZP[_D]; 				} /* IN   D,(C) 	  */
+OP(ed,51) { OUT(_BC,_D);											} /* OUT  (C),D 	  */
+OP(ed,52) { SBC16( DE );											} /* SBC  HL,DE 	  */
+OP(ed,53) { EA = ARG16(); WM16( EA, &Z80.DE );						} /* LD   (w),DE	  */
+OP(ed,54) { NEG;													} /* NEG			  */
+OP(ed,55) { RETN;													} /* RETN;			  */
+OP(ed,56) { _IM = 1;												} /* IM   1 		  */
+OP(ed,57) { LD_A_I; 												} /* LD   A,I		  */
+
+OP(ed,58) { _E = IN(_BC); _F = (_F & CF) | SZP[_E]; 				} /* IN   E,(C) 	  */
+OP(ed,59) { OUT(_BC,_E);											} /* OUT  (C),E 	  */
+OP(ed,5a) { ADC16( DE );											} /* ADC  HL,DE 	  */
+OP(ed,5b) { EA = ARG16(); RM16( EA, &Z80.DE );						} /* LD   DE,(w)	  */
+OP(ed,5c) { NEG;													} /* NEG			  */
+OP(ed,5d) { RETI;													} /* RETI			  */
+OP(ed,5e) { _IM = 2;												} /* IM   2 		  */
+OP(ed,5f) { LD_A_R; 												} /* LD   A,R		  */
+
+OP(ed,60) { _H = IN(_BC); _F = (_F & CF) | SZP[_H]; 				} /* IN   H,(C) 	  */
+OP(ed,61) { OUT(_BC,_H);											} /* OUT  (C),H 	  */
+OP(ed,62) { SBC16( HL );											} /* SBC  HL,HL 	  */
+OP(ed,63) { EA = ARG16(); WM16( EA, &Z80.HL );						} /* LD   (w),HL	  */
+OP(ed,64) { NEG;													} /* NEG			  */
+OP(ed,65) { RETN;													} /* RETN;			  */
+OP(ed,66) { _IM = 0;												} /* IM   0 		  */
+OP(ed,67) { RRD;													} /* RRD  (HL)		  */
+
+OP(ed,68) { _L = IN(_BC); _F = (_F & CF) | SZP[_L]; 				} /* IN   L,(C) 	  */
+OP(ed,69) { OUT(_BC,_L);											} /* OUT  (C),L 	  */
+OP(ed,6a) { ADC16( HL );											} /* ADC  HL,HL 	  */
+OP(ed,6b) { EA = ARG16(); RM16( EA, &Z80.HL );						} /* LD   HL,(w)	  */
+OP(ed,6c) { NEG;													} /* NEG			  */
+OP(ed,6d) { RETI;													} /* RETI			  */
+OP(ed,6e) { _IM = 0;												} /* IM   0 		  */
+OP(ed,6f) { RLD;													} /* RLD  (HL)		  */
+
+OP(ed,70) { UINT8 res = IN(_BC); _F = (_F & CF) | SZP[res]; 		} /* IN   0,(C) 	  */
+OP(ed,71) { OUT(_BC,0); 											} /* OUT  (C),0 	  */
+OP(ed,72) { SBC16( SP );											} /* SBC  HL,SP 	  */
+OP(ed,73) { EA = ARG16(); WM16( EA, &Z80.SP );						} /* LD   (w),SP	  */
+OP(ed,74) { NEG;													} /* NEG			  */
+OP(ed,75) { RETN;													} /* RETN;			  */
+OP(ed,76) { _IM = 1;												} /* IM   1 		  */
+OP(ed,77) { illegal_2();											} /* DB   ED,77 	  */
+
+OP(ed,78) { _A = IN(_BC); _F = (_F & CF) | SZP[_A]; 				} /* IN   E,(C) 	  */
+OP(ed,79) { OUT(_BC,_A);											} /* OUT  (C),E 	  */
+OP(ed,7a) { ADC16( SP );											} /* ADC  HL,SP 	  */
+OP(ed,7b) { EA = ARG16(); RM16( EA, &Z80.SP );						} /* LD   SP,(w)	  */
+OP(ed,7c) { NEG;													} /* NEG			  */
+OP(ed,7d) { RETI;													} /* RETI			  */
+OP(ed,7e) { _IM = 2;												} /* IM   2 		  */
+OP(ed,7f) { illegal_2();											} /* DB   ED,7F 	  */
+
+OP(ed,80) { illegal_2();											} /* DB   ED		  */
+OP(ed,81) { illegal_2();											} /* DB   ED		  */
+OP(ed,82) { illegal_2();											} /* DB   ED		  */
+OP(ed,83) { illegal_2();											} /* DB   ED		  */
+OP(ed,84) { illegal_2();											} /* DB   ED		  */
+OP(ed,85) { illegal_2();											} /* DB   ED		  */
+OP(ed,86) { illegal_2();											} /* DB   ED		  */
+OP(ed,87) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,88) { illegal_2();											} /* DB   ED		  */
+OP(ed,89) { illegal_2();											} /* DB   ED		  */
+OP(ed,8a) { illegal_2();											} /* DB   ED		  */
+OP(ed,8b) { illegal_2();											} /* DB   ED		  */
+OP(ed,8c) { illegal_2();											} /* DB   ED		  */
+OP(ed,8d) { illegal_2();											} /* DB   ED		  */
+OP(ed,8e) { illegal_2();											} /* DB   ED		  */
+OP(ed,8f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,90) { illegal_2();											} /* DB   ED		  */
+OP(ed,91) { illegal_2();											} /* DB   ED		  */
+OP(ed,92) { illegal_2();											} /* DB   ED		  */
+OP(ed,93) { illegal_2();											} /* DB   ED		  */
+OP(ed,94) { illegal_2();											} /* DB   ED		  */
+OP(ed,95) { illegal_2();											} /* DB   ED		  */
+OP(ed,96) { illegal_2();											} /* DB   ED		  */
+OP(ed,97) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,98) { illegal_2();											} /* DB   ED		  */
+OP(ed,99) { illegal_2();											} /* DB   ED		  */
+OP(ed,9a) { illegal_2();											} /* DB   ED		  */
+OP(ed,9b) { illegal_2();											} /* DB   ED		  */
+OP(ed,9c) { illegal_2();											} /* DB   ED		  */
+OP(ed,9d) { illegal_2();											} /* DB   ED		  */
+OP(ed,9e) { illegal_2();											} /* DB   ED		  */
+OP(ed,9f) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,a0) { LDI;													} /* LDI			  */
+OP(ed,a1) { CPI;													} /* CPI			  */
+OP(ed,a2) { INI;													} /* INI			  */
+OP(ed,a3) { OUTI;													} /* OUTI			  */
+OP(ed,a4) { illegal_2();											} /* DB   ED		  */
+OP(ed,a5) { illegal_2();											} /* DB   ED		  */
+OP(ed,a6) { illegal_2();											} /* DB   ED		  */
+OP(ed,a7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,a8) { LDD;													} /* LDD			  */
+OP(ed,a9) { CPD;													} /* CPD			  */
+OP(ed,aa) { IND;													} /* IND			  */
+OP(ed,ab) { OUTD;													} /* OUTD			  */
+OP(ed,ac) { illegal_2();											} /* DB   ED		  */
+OP(ed,ad) { illegal_2();											} /* DB   ED		  */
+OP(ed,ae) { illegal_2();											} /* DB   ED		  */
+OP(ed,af) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,b0) { LDIR;													} /* LDIR			  */
+OP(ed,b1) { CPIR;													} /* CPIR			  */
+OP(ed,b2) { INIR;													} /* INIR			  */
+OP(ed,b3) { OTIR;													} /* OTIR			  */
+OP(ed,b4) { illegal_2();											} /* DB   ED		  */
+OP(ed,b5) { illegal_2();											} /* DB   ED		  */
+OP(ed,b6) { illegal_2();											} /* DB   ED		  */
+OP(ed,b7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,b8) { LDDR;													} /* LDDR			  */
+OP(ed,b9) { CPDR;													} /* CPDR			  */
+OP(ed,ba) { INDR;													} /* INDR			  */
+OP(ed,bb) { OTDR;													} /* OTDR			  */
+OP(ed,bc) { illegal_2();											} /* DB   ED		  */
+OP(ed,bd) { illegal_2();											} /* DB   ED		  */
+OP(ed,be) { illegal_2();											} /* DB   ED		  */
+OP(ed,bf) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,c0) { illegal_2();											} /* DB   ED		  */
+OP(ed,c1) { illegal_2();											} /* DB   ED		  */
+OP(ed,c2) { illegal_2();											} /* DB   ED		  */
+OP(ed,c3) { illegal_2();											} /* DB   ED		  */
+OP(ed,c4) { illegal_2();											} /* DB   ED		  */
+OP(ed,c5) { illegal_2();											} /* DB   ED		  */
+OP(ed,c6) { illegal_2();											} /* DB   ED		  */
+OP(ed,c7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,c8) { illegal_2();											} /* DB   ED		  */
+OP(ed,c9) { illegal_2();											} /* DB   ED		  */
+OP(ed,ca) { illegal_2();											} /* DB   ED		  */
+OP(ed,cb) { illegal_2();											} /* DB   ED		  */
+OP(ed,cc) { illegal_2();											} /* DB   ED		  */
+OP(ed,cd) { illegal_2();											} /* DB   ED		  */
+OP(ed,ce) { illegal_2();											} /* DB   ED		  */
+OP(ed,cf) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,d0) { illegal_2();											} /* DB   ED		  */
+OP(ed,d1) { illegal_2();											} /* DB   ED		  */
+OP(ed,d2) { illegal_2();											} /* DB   ED		  */
+OP(ed,d3) { illegal_2();											} /* DB   ED		  */
+OP(ed,d4) { illegal_2();											} /* DB   ED		  */
+OP(ed,d5) { illegal_2();											} /* DB   ED		  */
+OP(ed,d6) { illegal_2();											} /* DB   ED		  */
+OP(ed,d7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,d8) { illegal_2();											} /* DB   ED		  */
+OP(ed,d9) { illegal_2();											} /* DB   ED		  */
+OP(ed,da) { illegal_2();											} /* DB   ED		  */
+OP(ed,db) { illegal_2();											} /* DB   ED		  */
+OP(ed,dc) { illegal_2();											} /* DB   ED		  */
+OP(ed,dd) { illegal_2();											} /* DB   ED		  */
+OP(ed,de) { illegal_2();											} /* DB   ED		  */
+OP(ed,df) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,e0) { illegal_2();											} /* DB   ED		  */
+OP(ed,e1) { illegal_2();											} /* DB   ED		  */
+OP(ed,e2) { illegal_2();											} /* DB   ED		  */
+OP(ed,e3) { illegal_2();											} /* DB   ED		  */
+OP(ed,e4) { illegal_2();											} /* DB   ED		  */
+OP(ed,e5) { illegal_2();											} /* DB   ED		  */
+OP(ed,e6) { illegal_2();											} /* DB   ED		  */
+OP(ed,e7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,e8) { illegal_2();											} /* DB   ED		  */
+OP(ed,e9) { illegal_2();											} /* DB   ED		  */
+OP(ed,ea) { illegal_2();											} /* DB   ED		  */
+OP(ed,eb) { illegal_2();											} /* DB   ED		  */
+OP(ed,ec) { illegal_2();											} /* DB   ED		  */
+OP(ed,ed) { illegal_2();											} /* DB   ED		  */
+OP(ed,ee) { illegal_2();											} /* DB   ED		  */
+OP(ed,ef) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,f0) { illegal_2();											} /* DB   ED		  */
+OP(ed,f1) { illegal_2();											} /* DB   ED		  */
+OP(ed,f2) { illegal_2();											} /* DB   ED		  */
+OP(ed,f3) { illegal_2();											} /* DB   ED		  */
+OP(ed,f4) { illegal_2();											} /* DB   ED		  */
+OP(ed,f5) { illegal_2();											} /* DB   ED		  */
+OP(ed,f6) { illegal_2();											} /* DB   ED		  */
+OP(ed,f7) { illegal_2();											} /* DB   ED		  */
+
+OP(ed,f8) { illegal_2();											} /* DB   ED		  */
+OP(ed,f9) { illegal_2();											} /* DB   ED		  */
+OP(ed,fa) { illegal_2();											} /* DB   ED		  */
+OP(ed,fb) { illegal_2();											} /* DB   ED		  */
+OP(ed,fc) { illegal_2();											} /* DB   ED		  */
+OP(ed,fd) { illegal_2();											} /* DB   ED		  */
+OP(ed,fe) { illegal_2();											} /* DB   ED		  */
+OP(ed,ff) { illegal_2();											} /* DB   ED		  */
+
+#if TIME_LOOP_HACKS
+
+#define CHECK_BC_LOOP                                               \
+if( _BC > 1 && _PCD < 0xfffc ) {									\
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x78 && op2==0xb1) || (op1==0x79 && op2==0xb0) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			while( _BC > 0 && z80_ICount > 4+4+12+6 )				\
+			{														\
+				BURNODD( 4+4+12+6, 4, 4+4+12+6 );					\
+				_BC--;												\
+			}														\
+		}															\
+		else														\
+		if( op3 == 0xc2 )											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				while( _BC > 0 && z80_ICount > 4+4+10+6 )			\
+				{													\
+					BURNODD( 4+4+10+6, 4, 4+4+10+6 );				\
+					_BC--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#define CHECK_DE_LOOP                                               \
+if( _DE > 1 && _PCD < 0xfffc ) {                                    \
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x7a && op2==0xb3) || (op1==0x7b && op2==0xb2) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			while( _DE > 0 && z80_ICount > 4+4+12+6 )				\
+			{														\
+				BURNODD( 4+4+12+6, 4, 4+4+12+6 );					\
+				_DE--;												\
+			}														\
+		}															\
+		else														\
+		if( op3==0xc2 ) 											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				while( _DE > 0 && z80_ICount > 4+4+10+6 )			\
+				{													\
+					BURNODD( 4+4+10+6, 4, 4+4+10+6 );				\
+					_DE--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#define CHECK_HL_LOOP                                               \
+if( _HL > 1 && _PCD < 0xfffc ) {                                    \
+	UINT8 op1 = cpu_readop(_PCD);									\
+	UINT8 op2 = cpu_readop(_PCD+1); 								\
+	if( (op1==0x7c && op2==0xb5) || (op1==0x7d && op2==0xb4) )		\
+	{																\
+		UINT8 op3 = cpu_readop(_PCD+2); 							\
+		UINT8 op4 = cpu_readop(_PCD+3); 							\
+		if( op3==0x20 && op4==0xfb )								\
+		{															\
+			while( _HL > 0 && z80_ICount > 4+4+12+6 )				\
+			{														\
+				BURNODD( 4+4+12+6, 4, 4+4+12+6 );					\
+				_HL--;												\
+			}														\
+		}															\
+		else														\
+		if( op3==0xc2 ) 											\
+		{															\
+			UINT8 ad1 = cpu_readop_arg(_PCD+3); 					\
+			UINT8 ad2 = cpu_readop_arg(_PCD+4); 					\
+			if( (ad1 + 256 * ad2) == (_PCD - 1) )					\
+			{														\
+				while( _HL > 0 && z80_ICount > 4+4+10+6 )			\
+				{													\
+					BURNODD( 4+4+10+6, 4, 4+4+10+6 );				\
+					_HL--;											\
+				}													\
+			}														\
+		}															\
+	}																\
+}
+
+#else
+
+#define CHECK_BC_LOOP
+#define CHECK_DE_LOOP
+#define CHECK_HL_LOOP
+
+#endif
+
+/**********************************************************
+ * main opcodes
+ **********************************************************/
+OP(op,00) { 														} /* NOP			  */
+OP(op,01) { _BC = ARG16();											} /* LD   BC,w		  */
+OP(op,02) { WM( _BC, _A );											} /* LD   (BC),A	  */
+OP(op,03) { _BC++;													} /* INC  BC		  */
+OP(op,04) { _B = INC(_B);											} /* INC  B 		  */
+OP(op,05) { _B = DEC(_B);											} /* DEC  B 		  */
+OP(op,06) { _B = ARG(); 											} /* LD   B,n		  */
+OP(op,07) { RLCA;													} /* RLCA			  */
+
+OP(op,08) { EX_AF;													} /* EX   AF,AF'      */
+OP(op,09) { ADD16(HL,BC);											} /* ADD  HL,BC 	  */
+OP(op,0a) { _A = RM(_BC);											} /* LD   A,(BC)	  */
+OP(op,0b) { _BC--; CHECK_BC_LOOP;									} /* DEC  BC		  */
+OP(op,0c) { _C = INC(_C);											} /* INC  C 		  */
+OP(op,0d) { _C = DEC(_C);											} /* DEC  C 		  */
+OP(op,0e) { _C = ARG(); 											} /* LD   C,n		  */
+OP(op,0f) { RRCA;													} /* RRCA			  */
+
+OP(op,10) { _B--; JR_COND(_B);										} /* DJNZ o 		  */
+OP(op,11) { _DE = ARG16();											} /* LD   DE,w		  */
+OP(op,12) { WM( _DE, _A );											} /* LD   (DE),A	  */
+OP(op,13) { _DE++;													} /* INC  DE		  */
+OP(op,14) { _D = INC(_D);											} /* INC  D 		  */
+OP(op,15) { _D = DEC(_D);											} /* DEC  D 		  */
+OP(op,16) { _D = ARG(); 											} /* LD   D,n		  */
+OP(op,17) { RLA;													} /* RLA			  */
+
+OP(op,18) { JR();													} /* JR   o 		  */
+OP(op,19) { ADD16(HL,DE);											} /* ADD  HL,DE 	  */
+OP(op,1a) { _A = RM(_DE);											} /* LD   A,(DE)	  */
+OP(op,1b) { _DE--; CHECK_DE_LOOP;									} /* DEC  DE		  */
+OP(op,1c) { _E = INC(_E);											} /* INC  E 		  */
+OP(op,1d) { _E = DEC(_E);											} /* DEC  E 		  */
+OP(op,1e) { _E = ARG(); 											} /* LD   E,n		  */
+OP(op,1f) { RRA;													} /* RRA			  */
+
+OP(op,20) { JR_COND( !(_F & ZF) );									} /* JR   NZ,o		  */
+OP(op,21) { _HL = ARG16();											} /* LD   HL,w		  */
+OP(op,22) { EA = ARG16(); WM16( EA, &Z80.HL );						} /* LD   (w),HL	  */
+OP(op,23) { _HL++;													} /* INC  HL		  */
+OP(op,24) { _H = INC(_H);											} /* INC  H 		  */
+OP(op,25) { _H = DEC(_H);											} /* DEC  H 		  */
+OP(op,26) { _H = ARG(); 											} /* LD   H,n		  */
+OP(op,27) { DAA;													} /* DAA			  */
+
+OP(op,28) { JR_COND( _F & ZF ); 									} /* JR   Z,o		  */
+OP(op,29) { ADD16(HL,HL);											} /* ADD  HL,HL 	  */
+OP(op,2a) { EA = ARG16(); RM16( EA, &Z80.HL );						} /* LD   HL,(w)	  */
+OP(op,2b) { _HL--; CHECK_HL_LOOP;									} /* DEC  HL		  */
+OP(op,2c) { _L = INC(_L);											} /* INC  L 		  */
+OP(op,2d) { _L = DEC(_L);											} /* DEC  L 		  */
+OP(op,2e) { _L = ARG(); 											} /* LD   L,n		  */
+OP(op,2f) { _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); } /* CPL			  */
+
+OP(op,30) { JR_COND( !(_F & CF) );									} /* JR   NC,o		  */
+OP(op,31) { _SP = ARG16();											} /* LD   SP,w		  */
+OP(op,32) { EA = ARG16(); WM( EA, _A ); 							} /* LD   (w),A 	  */
+OP(op,33) { _SP++;													} /* INC  SP		  */
+OP(op,34) { WM( _HL, INC(RM(_HL)) );								} /* INC  (HL)		  */
+OP(op,35) { WM( _HL, DEC(RM(_HL)) );								} /* DEC  (HL)		  */
+OP(op,36) { WM( _HL, ARG() );										} /* LD   (HL),n	  */
+OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF));			} /* SCF			  */
+
+OP(op,38) { JR_COND( _F & CF ); 									} /* JR   C,o		  */
+OP(op,39) { ADD16(HL,SP);											} /* ADD  HL,SP 	  */
+OP(op,3a) { EA = ARG16(); _A = RM( EA );							} /* LD   A,(w) 	  */
+OP(op,3b) { _SP--;													} /* DEC  SP		  */
+OP(op,3c) { _A = INC(_A);											} /* INC  A 		  */
+OP(op,3d) { _A = DEC(_A);											} /* DEC  A 		  */
+OP(op,3e) { _A = ARG(); 											} /* LD   A,n		  */
+OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; } /* CCF			  */
+/*OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; 		  } */ /* CCF				*/
+
+OP(op,40) { 														} /* LD   B,B		  */
+OP(op,41) { _B = _C;												} /* LD   B,C		  */
+OP(op,42) { _B = _D;												} /* LD   B,D		  */
+OP(op,43) { _B = _E;												} /* LD   B,E		  */
+OP(op,44) { _B = _H;												} /* LD   B,H		  */
+OP(op,45) { _B = _L;												} /* LD   B,L		  */
+OP(op,46) { _B = RM(_HL);											} /* LD   B,(HL)	  */
+OP(op,47) { _B = _A;												} /* LD   B,A		  */
+
+OP(op,48) { _C = _B;												} /* LD   C,B		  */
+OP(op,49) { 														} /* LD   C,C		  */
+OP(op,4a) { _C = _D;												} /* LD   C,D		  */
+OP(op,4b) { _C = _E;												} /* LD   C,E		  */
+OP(op,4c) { _C = _H;												} /* LD   C,H		  */
+OP(op,4d) { _C = _L;												} /* LD   C,L		  */
+OP(op,4e) { _C = RM(_HL);											} /* LD   C,(HL)	  */
+OP(op,4f) { _C = _A;												} /* LD   C,A		  */
+
+OP(op,50) { _D = _B;												} /* LD   D,B		  */
+OP(op,51) { _D = _C;												} /* LD   D,C		  */
+OP(op,52) { 														} /* LD   D,D		  */
+OP(op,53) { _D = _E;												} /* LD   D,E		  */
+OP(op,54) { _D = _H;												} /* LD   D,H		  */
+OP(op,55) { _D = _L;												} /* LD   D,L		  */
+OP(op,56) { _D = RM(_HL);											} /* LD   D,(HL)	  */
+OP(op,57) { _D = _A;												} /* LD   D,A		  */
+
+OP(op,58) { _E = _B;												} /* LD   E,B		  */
+OP(op,59) { _E = _C;												} /* LD   E,C		  */
+OP(op,5a) { _E = _D;												} /* LD   E,D		  */
+OP(op,5b) { 														} /* LD   E,E		  */
+OP(op,5c) { _E = _H;												} /* LD   E,H		  */
+OP(op,5d) { _E = _L;												} /* LD   E,L		  */
+OP(op,5e) { _E = RM(_HL);											} /* LD   E,(HL)	  */
+OP(op,5f) { _E = _A;												} /* LD   E,A		  */
+
+OP(op,60) { _H = _B;												} /* LD   H,B		  */
+OP(op,61) { _H = _C;												} /* LD   H,C		  */
+OP(op,62) { _H = _D;												} /* LD   H,D		  */
+OP(op,63) { _H = _E;												} /* LD   H,E		  */
+OP(op,64) { 														} /* LD   H,H		  */
+OP(op,65) { _H = _L;												} /* LD   H,L		  */
+OP(op,66) { _H = RM(_HL);											} /* LD   H,(HL)	  */
+OP(op,67) { _H = _A;												} /* LD   H,A		  */
+
+OP(op,68) { _L = _B;												} /* LD   L,B		  */
+OP(op,69) { _L = _C;												} /* LD   L,C		  */
+OP(op,6a) { _L = _D;												} /* LD   L,D		  */
+OP(op,6b) { _L = _E;												} /* LD   L,E		  */
+OP(op,6c) { _L = _H;												} /* LD   L,H		  */
+OP(op,6d) { 														} /* LD   L,L		  */
+OP(op,6e) { _L = RM(_HL);											} /* LD   L,(HL)	  */
+OP(op,6f) { _L = _A;												} /* LD   L,A		  */
+
+OP(op,70) { WM( _HL, _B );											} /* LD   (HL),B	  */
+OP(op,71) { WM( _HL, _C );											} /* LD   (HL),C	  */
+OP(op,72) { WM( _HL, _D );											} /* LD   (HL),D	  */
+OP(op,73) { WM( _HL, _E );											} /* LD   (HL),E	  */
+OP(op,74) { WM( _HL, _H );											} /* LD   (HL),H	  */
+OP(op,75) { WM( _HL, _L );											} /* LD   (HL),L	  */
+OP(op,76) { ENTER_HALT; 											} /* HALT			  */
+OP(op,77) { WM( _HL, _A );											} /* LD   (HL),A	  */
+
+OP(op,78) { _A = _B;												} /* LD   A,B		  */
+OP(op,79) { _A = _C;												} /* LD   A,C		  */
+OP(op,7a) { _A = _D;												} /* LD   A,D		  */
+OP(op,7b) { _A = _E;												} /* LD   A,E		  */
+OP(op,7c) { _A = _H;												} /* LD   A,H		  */
+OP(op,7d) { _A = _L;												} /* LD   A,L		  */
+OP(op,7e) { _A = RM(_HL);											} /* LD   A,(HL)	  */
+OP(op,7f) { 														} /* LD   A,A		  */
+
+OP(op,80) { ADD(_B);												} /* ADD  A,B		  */
+OP(op,81) { ADD(_C);												} /* ADD  A,C		  */
+OP(op,82) { ADD(_D);												} /* ADD  A,D		  */
+OP(op,83) { ADD(_E);												} /* ADD  A,E		  */
+OP(op,84) { ADD(_H);												} /* ADD  A,H		  */
+OP(op,85) { ADD(_L);												} /* ADD  A,L		  */
+OP(op,86) { ADD(RM(_HL));											} /* ADD  A,(HL)	  */
+OP(op,87) { ADD(_A);												} /* ADD  A,A		  */
+
+OP(op,88) { ADC(_B);												} /* ADC  A,B		  */
+OP(op,89) { ADC(_C);												} /* ADC  A,C		  */
+OP(op,8a) { ADC(_D);												} /* ADC  A,D		  */
+OP(op,8b) { ADC(_E);												} /* ADC  A,E		  */
+OP(op,8c) { ADC(_H);												} /* ADC  A,H		  */
+OP(op,8d) { ADC(_L);												} /* ADC  A,L		  */
+OP(op,8e) { ADC(RM(_HL));											} /* ADC  A,(HL)	  */
+OP(op,8f) { ADC(_A);												} /* ADC  A,A		  */
+
+OP(op,90) { SUB(_B);												} /* SUB  B 		  */
+OP(op,91) { SUB(_C);												} /* SUB  C 		  */
+OP(op,92) { SUB(_D);												} /* SUB  D 		  */
+OP(op,93) { SUB(_E);												} /* SUB  E 		  */
+OP(op,94) { SUB(_H);												} /* SUB  H 		  */
+OP(op,95) { SUB(_L);												} /* SUB  L 		  */
+OP(op,96) { SUB(RM(_HL));											} /* SUB  (HL)		  */
+OP(op,97) { SUB(_A);												} /* SUB  A 		  */
+
+OP(op,98) { SBC(_B);												} /* SBC  A,B		  */
+OP(op,99) { SBC(_C);												} /* SBC  A,C		  */
+OP(op,9a) { SBC(_D);												} /* SBC  A,D		  */
+OP(op,9b) { SBC(_E);												} /* SBC  A,E		  */
+OP(op,9c) { SBC(_H);												} /* SBC  A,H		  */
+OP(op,9d) { SBC(_L);												} /* SBC  A,L		  */
+OP(op,9e) { SBC(RM(_HL));											} /* SBC  A,(HL)	  */
+OP(op,9f) { SBC(_A);												} /* SBC  A,A		  */
+
+OP(op,a0) { AND(_B);												} /* AND  B 		  */
+OP(op,a1) { AND(_C);												} /* AND  C 		  */
+OP(op,a2) { AND(_D);												} /* AND  D 		  */
+OP(op,a3) { AND(_E);												} /* AND  E 		  */
+OP(op,a4) { AND(_H);												} /* AND  H 		  */
+OP(op,a5) { AND(_L);												} /* AND  L 		  */
+OP(op,a6) { AND(RM(_HL));											} /* AND  (HL)		  */
+OP(op,a7) { AND(_A);												} /* AND  A 		  */
+
+OP(op,a8) { XOR(_B);												} /* XOR  B 		  */
+OP(op,a9) { XOR(_C);												} /* XOR  C 		  */
+OP(op,aa) { XOR(_D);												} /* XOR  D 		  */
+OP(op,ab) { XOR(_E);												} /* XOR  E 		  */
+OP(op,ac) { XOR(_H);												} /* XOR  H 		  */
+OP(op,ad) { XOR(_L);												} /* XOR  L 		  */
+OP(op,ae) { XOR(RM(_HL));											} /* XOR  (HL)		  */
+OP(op,af) { XOR(_A);												} /* XOR  A 		  */
+
+OP(op,b0) { OR(_B); 												} /* OR   B 		  */
+OP(op,b1) { OR(_C); 												} /* OR   C 		  */
+OP(op,b2) { OR(_D); 												} /* OR   D 		  */
+OP(op,b3) { OR(_E); 												} /* OR   E 		  */
+OP(op,b4) { OR(_H); 												} /* OR   H 		  */
+OP(op,b5) { OR(_L); 												} /* OR   L 		  */
+OP(op,b6) { OR(RM(_HL));											} /* OR   (HL)		  */
+OP(op,b7) { OR(_A); 												} /* OR   A 		  */
+
+OP(op,b8) { CP(_B); 												} /* CP   B 		  */
+OP(op,b9) { CP(_C); 												} /* CP   C 		  */
+OP(op,ba) { CP(_D); 												} /* CP   D 		  */
+OP(op,bb) { CP(_E); 												} /* CP   E 		  */
+OP(op,bc) { CP(_H); 												} /* CP   H 		  */
+OP(op,bd) { CP(_L); 												} /* CP   L 		  */
+OP(op,be) { CP(RM(_HL));											} /* CP   (HL)		  */
+OP(op,bf) { CP(_A); 												} /* CP   A 		  */
+
+OP(op,c0) { RET( !(_F & ZF) );										} /* RET  NZ		  */
+OP(op,c1) { POP(BC);												} /* POP  BC		  */
+OP(op,c2) { JP_COND( !(_F & ZF) );									} /* JP   NZ,a		  */
+OP(op,c3) { JP; 													} /* JP   a 		  */
+OP(op,c4) { CALL( !(_F & ZF) ); 									} /* CALL NZ,a		  */
+OP(op,c5) { PUSH( BC ); 											} /* PUSH BC		  */
+OP(op,c6) { ADD(ARG()); 											} /* ADD  A,n		  */
+OP(op,c7) { RST(0x00);												} /* RST  0 		  */
+
+OP(op,c8) { RET( _F & ZF ); 										} /* RET  Z 		  */
+OP(op,c9) { RET(1); 												} /* RET			  */
+OP(op,ca) { JP_COND( _F & ZF ); 									} /* JP   Z,a		  */
+OP(op,cb) { _R++; EXEC(cb,ROP());									} /* **** CB xx 	  */
+OP(op,cc) { CALL( _F & ZF );										} /* CALL Z,a		  */
+OP(op,cd) { CALL(1);												} /* CALL a 		  */
+OP(op,ce) { ADC(ARG()); 											} /* ADC  A,n		  */
+OP(op,cf) { RST(0x08);												} /* RST  1 		  */
+
+OP(op,d0) { RET( !(_F & CF) );										} /* RET  NC		  */
+OP(op,d1) { POP(DE);												} /* POP  DE		  */
+OP(op,d2) { JP_COND( !(_F & CF) );									} /* JP   NC,a		  */
+OP(op,d3) { unsigned n = ARG() | (_A << 8); OUT( n, _A );			} /* OUT  (n),A 	  */
+OP(op,d4) { CALL( !(_F & CF) ); 									} /* CALL NC,a		  */
+OP(op,d5) { PUSH( DE ); 											} /* PUSH DE		  */
+OP(op,d6) { SUB(ARG()); 											} /* SUB  n 		  */
+OP(op,d7) { RST(0x10);												} /* RST  2 		  */
+
+OP(op,d8) { RET( _F & CF ); 										} /* RET  C 		  */
+OP(op,d9) { EXX;													} /* EXX			  */
+OP(op,da) { JP_COND( _F & CF ); 									} /* JP   C,a		  */
+OP(op,db) { unsigned n = ARG() | (_A << 8); _A = IN( n );			} /* IN   A,(n) 	  */
+OP(op,dc) { CALL( _F & CF );										} /* CALL C,a		  */
+OP(op,dd) { _R++; EXEC(dd,ROP());									} /* **** DD xx 	  */
+OP(op,de) { SBC(ARG()); 											} /* SBC  A,n		  */
+OP(op,df) { RST(0x18);												} /* RST  3 		  */
+
+OP(op,e0) { RET( !(_F & PF) );										} /* RET  PO		  */
+OP(op,e1) { POP(HL);												} /* POP  HL		  */
+OP(op,e2) { JP_COND( !(_F & PF) );									} /* JP   PO,a		  */
+OP(op,e3) { EXSP(HL);												} /* EX   HL,(SP)	  */
+OP(op,e4) { CALL( !(_F & PF) ); 									} /* CALL PO,a		  */
+OP(op,e5) { PUSH( HL ); 											} /* PUSH HL		  */
+OP(op,e6) { AND(ARG()); 											} /* AND  n 		  */
+OP(op,e7) { RST(0x20);												} /* RST  4 		  */
+
+OP(op,e8) { RET( _F & PF ); 										} /* RET  PE		  */
+OP(op,e9) { _PC = _HL;                                              } /* JP   (HL)        */
+OP(op,ea) { JP_COND( _F & PF ); 									} /* JP   PE,a		  */
+OP(op,eb) { EX_DE_HL;												} /* EX   DE,HL 	  */
+OP(op,ec) { CALL( _F & PF );										} /* CALL PE,a		  */
+OP(op,ed) { _R++; EXEC(ed,ROP());									} /* **** ED xx 	  */
+OP(op,ee) { XOR(ARG()); 											} /* XOR  n 		  */
+OP(op,ef) { RST(0x28);												} /* RST  5 		  */
+
+OP(op,f0) { RET( !(_F & SF) );										} /* RET  P 		  */
+OP(op,f1) { POP(AF);												} /* POP  AF		  */
+OP(op,f2) { JP_COND( !(_F & SF) );									} /* JP   P,a		  */
+OP(op,f3) { _IFF1 = _IFF2 = 0;										} /* DI 			  */
+OP(op,f4) { CALL( !(_F & SF) ); 									} /* CALL P,a		  */
+OP(op,f5) { PUSH( AF ); 											} /* PUSH AF		  */
+OP(op,f6) { OR(ARG());												} /* OR   n 		  */
+OP(op,f7) { RST(0x30);												} /* RST  6 		  */
+
+OP(op,f8) { RET(_F & SF);											} /* RET  M 		  */
+OP(op,f9) { _SP = _HL;												} /* LD   SP,HL 	  */
+OP(op,fa) { JP_COND(_F & SF);										} /* JP   M,a		  */
+OP(op,fb) { EI; 													} /* EI 			  */
+OP(op,fc) { CALL(_F & SF);											} /* CALL M,a		  */
+OP(op,fd) { _R++; EXEC(fd,ROP());									} /* **** FD xx 	  */
+OP(op,fe) { CP(ARG());												} /* CP   n 		  */
+OP(op,ff) { RST(0x38);												} /* RST  7 		  */
+
+
+static void take_interrupt(void)
+{
+    if( _IFF1 )
+    {
+        int irq_vector;
+
+        /* there isn't a valid previous program counter */
+        _PPC = -1;
+
+        /* Check if processor was halted */
+		LEAVE_HALT;
+
+        if( Z80.irq_max )           /* daisy chain mode */
+        {
+            if( Z80.request_irq >= 0 )
+            {
+                /* Clear both interrupt flip flops */
+                _IFF1 = _IFF2 = 0;
+                irq_vector = Z80.irq[Z80.request_irq].interrupt_entry(Z80.irq[Z80.request_irq].irq_param);
+                Z80.request_irq = -1;
+            } else return;
+        }
+        else
+        {
+            /* Clear both interrupt flip flops */
+            _IFF1 = _IFF2 = 0;
+            /* call back the cpu interface to retrieve the vector */
+            irq_vector = (*Z80.irq_callback)(0);
+        }
+
+        /* Interrupt mode 2. Call [Z80.I:databyte] */
+        if( _IM == 2 )
+        {
+			irq_vector = (irq_vector & 0xff) | (_I << 8);
+            PUSH( PC );
+			RM16( irq_vector, &Z80.PC );
+            Z80.extra_cycles += 19;
+        }
+        else
+        /* Interrupt mode 1. RST 38h */
+        if( _IM == 1 )
+        {
+            PUSH( PC );
+            _PCD = 0x0038;
+            Z80.extra_cycles += 11+2; /* RST $38 + 2 cycles */
+        }
+        else
+        {
+            /* Interrupt mode 0. We check for CALL and JP instructions, */
+            /* if neither of these were found we assume a 1 byte opcode */
+            /* was placed on the databus                                */
+            switch (irq_vector & 0xff0000)
+            {
+                case 0xcd0000:  /* call */
+                    PUSH( PC );
+                    Z80.extra_cycles += 5;  /* CALL $xxxx cycles (JP $xxxx follows)*/
+                case 0xc30000:  /* jump */
+                    _PCD = irq_vector & 0xffff;
+                    Z80.extra_cycles += 10 + 2; /* JP $xxxx + 2 cycles */
+                    break;
+                default:        /* rst */
+                    PUSH( PC );
+                    _PCD = irq_vector & 0x0038;
+                    Z80.extra_cycles += 11 + 2; /* RST $xx + 2 cycles */
+                    break;
+            }
+        }
+    }
+}
+
+/****************************************************************************
+ * Reset registers to their initial values
+ ****************************************************************************/
+void z80_reset(void *param)
+{
+	Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param;
+	int i, p;
+#if BIG_FLAGS_ARRAY
+	if( !SZHVC_add || !SZHVC_sub )
+    {
+		int oldval, newval, val;
+		UINT8 *padd, *padc, *psub, *psbc;
+        /* allocate big flag arrays once */
+		SZHVC_add = (UINT8 *)malloc(2*256*256);
+		SZHVC_sub = (UINT8 *)malloc(2*256*256);
+		if( !SZHVC_add || !SZHVC_sub )
+		{
+			raise(SIGABRT);
+		}
+		padd = &SZHVC_add[	0*256];
+		padc = &SZHVC_add[256*256];
+		psub = &SZHVC_sub[	0*256];
+		psbc = &SZHVC_sub[256*256];
+		for (oldval = 0; oldval < 256; oldval++)
+		{
+			for (newval = 0; newval < 256; newval++)
+			{
+				/* add or adc w/o carry set */
+				val = newval - oldval;
+				*padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+#if Z80_EXACT
+				*padd |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+                if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
+				if( newval < oldval ) *padd |= CF;
+				if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
+				padd++;
+
+				/* adc with carry set */
+				val = newval - oldval - 1;
+				*padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
+#if Z80_EXACT
+				*padc |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+                if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
+				if( newval <= oldval ) *padc |= CF;
+				if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
+				padc++;
+
+				/* cp, sub or sbc w/o carry set */
+				val = oldval - newval;
+				*psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+#if Z80_EXACT
+				*psub |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+                if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
+				if( newval > oldval ) *psub |= CF;
+				if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
+				psub++;
+
+				/* sbc with carry set */
+				val = oldval - newval - 1;
+				*psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
+#if Z80_EXACT
+				*psbc |= (newval & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+                if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
+				if( newval >= oldval ) *psbc |= CF;
+				if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
+				psbc++;
+			}
+        }
+    }
+#endif
+	for (i = 0; i < 256; i++)
+	{
+		p = 0;
+		if( i&0x01 ) ++p;
+		if( i&0x02 ) ++p;
+		if( i&0x04 ) ++p;
+		if( i&0x08 ) ++p;
+		if( i&0x10 ) ++p;
+		if( i&0x20 ) ++p;
+		if( i&0x40 ) ++p;
+		if( i&0x80 ) ++p;
+		SZ[i] = i ? i & SF : ZF;
+#if Z80_EXACT
+		SZ[i] |= (i & (YF | XF));		/* undocumented flag bits 5+3 */
+#endif
+		SZ_BIT[i] = i ? i & SF : ZF | PF;
+#if Z80_EXACT
+		SZ_BIT[i] |= (i & (YF | XF));	/* undocumented flag bits 5+3 */
+#endif
+        SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
+		SZHV_inc[i] = SZ[i];
+		if( i == 0x80 ) SZHV_inc[i] |= VF;
+		if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
+		SZHV_dec[i] = SZ[i] | NF;
+		if( i == 0x7f ) SZHV_dec[i] |= VF;
+		if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
+	}
+
+	memset(&Z80, 0, sizeof(Z80));
+	_IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
+	_F = ZF;			/* Zero flag is set */
+	Z80.request_irq = -1;
+	Z80.service_irq = -1;
+    Z80.nmi_state = CLEAR_LINE;
+	Z80.irq_state = CLEAR_LINE;
+
+    if( daisy_chain )
+	{
+		while( daisy_chain->irq_param != -1 && Z80.irq_max < Z80_MAXDAISY )
+		{
+            /* set callbackhandler after reti */
+			Z80.irq[Z80.irq_max] = *daisy_chain;
+            /* device reset */
+			if( Z80.irq[Z80.irq_max].reset )
+				Z80.irq[Z80.irq_max].reset(Z80.irq[Z80.irq_max].irq_param);
+			Z80.irq_max++;
+            daisy_chain++;
+        }
+    }
+}
+
+void z80_exit(void)
+{
+#if BIG_FLAGS_ARRAY
+	if (SZHVC_add) free(SZHVC_add);
+    SZHVC_add = 0;
+	if (SZHVC_sub) free(SZHVC_sub);
+    SZHVC_sub = 0;
+#endif
+}
+
+/****************************************************************************
+ * Execute 'cycles' T-states. Return number of T-states really executed
+ ****************************************************************************/
+int z80_execute(int cycles)
+{
+	z80_ICount = cycles - Z80.extra_cycles;
+	Z80.extra_cycles = 0;
+
+    do
+	{
+        _PPC = _PCD;
+		_R++;
+        EXEC_INLINE(op,ROP());
+	} while( z80_ICount > 0 );
+
+	z80_ICount -= Z80.extra_cycles;
+    Z80.extra_cycles = 0;
+
+    return cycles - z80_ICount;
+}
+
+/****************************************************************************
+ * Burn 'cycles' T-states. Adjust R register for the lost time
+ ****************************************************************************/
+void z80_burn(int cycles)
+{
+	if( cycles > 0 )
+	{
+		/* NOP takes 4 cycles per instruction */
+		int n = (cycles + 3) / 4;
+		_R += n;
+		z80_ICount -= 4 * n;
+	}
+}
+
+/****************************************************************************
+ * Get all registers in given buffer
+ ****************************************************************************/
+unsigned z80_get_context (void *dst)
+{
+	if( dst )
+	    *(Z80_Regs*)dst = Z80;
+	return sizeof(Z80_Regs);
+}
+
+/****************************************************************************
+ * Set all registers to given values
+ ****************************************************************************/
+void z80_set_context (void *src)
+{
+	if( src )
+		Z80 = *(Z80_Regs*)src;
+}
+
+/****************************************************************************
+ * Return program counter
+ ****************************************************************************/
+unsigned z80_get_pc (void)
+{
+    return _PCD;
+}
+
+/****************************************************************************
+ * Set program counter
+ ****************************************************************************/
+void z80_set_pc (unsigned val)
+{
+	_PC = val;
+}
+
+/****************************************************************************
+ * Return stack pointer
+ ****************************************************************************/
+unsigned z80_get_sp (void)
+{
+	return _SPD;
+}
+
+/****************************************************************************
+ * Set stack pointer
+ ****************************************************************************/
+void z80_set_sp (unsigned val)
+{
+	_SP = val;
+}
+
+/****************************************************************************
+ * Return a specific register
+ ****************************************************************************/
+unsigned z80_get_reg (int regnum)
+{
+	switch( regnum )
+	{
+		case Z80_PC: return Z80.PC.w.l;
+		case Z80_SP: return Z80.SP.w.l;
+		case Z80_AF: return Z80.AF.w.l;
+		case Z80_BC: return Z80.BC.w.l;
+		case Z80_DE: return Z80.DE.w.l;
+		case Z80_HL: return Z80.HL.w.l;
+		case Z80_IX: return Z80.IX.w.l;
+		case Z80_IY: return Z80.IY.w.l;
+        case Z80_R: return (Z80.R & 0x7f) | (Z80.R2 & 0x80);
+		case Z80_I: return Z80.I;
+		case Z80_AF2: return Z80.AF2.w.l;
+		case Z80_BC2: return Z80.BC2.w.l;
+		case Z80_DE2: return Z80.DE2.w.l;
+		case Z80_HL2: return Z80.HL2.w.l;
+		case Z80_IM: return Z80.IM;
+		case Z80_IFF1: return Z80.IFF1;
+		case Z80_IFF2: return Z80.IFF2;
+		case Z80_HALT: return Z80.HALT;
+		case Z80_NMI_STATE: return Z80.nmi_state;
+		case Z80_IRQ_STATE: return Z80.irq_state;
+		case Z80_DC0: return Z80.int_state[0];
+		case Z80_DC1: return Z80.int_state[1];
+		case Z80_DC2: return Z80.int_state[2];
+		case Z80_DC3: return Z80.int_state[3];
+        case REG_PREVIOUSPC: return Z80.PREPC.w.l;
+		default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0xffff )
+					return RM( offset ) | ( RM( offset + 1) << 8 );
+			}
+	}
+    return 0;
+}
+
+/****************************************************************************
+ * Set a specific register
+ ****************************************************************************/
+void z80_set_reg (int regnum, unsigned val)
+{
+	switch( regnum )
+	{
+		case Z80_PC: Z80.PC.w.l = val; break;
+		case Z80_SP: Z80.SP.w.l = val; break;
+		case Z80_AF: Z80.AF.w.l = val; break;
+		case Z80_BC: Z80.BC.w.l = val; break;
+		case Z80_DE: Z80.DE.w.l = val; break;
+		case Z80_HL: Z80.HL.w.l = val; break;
+		case Z80_IX: Z80.IX.w.l = val; break;
+		case Z80_IY: Z80.IY.w.l = val; break;
+        case Z80_R: Z80.R = val; Z80.R2 = val & 0x80; break;
+		case Z80_I: Z80.I = val; break;
+		case Z80_AF2: Z80.AF2.w.l = val; break;
+		case Z80_BC2: Z80.BC2.w.l = val; break;
+		case Z80_DE2: Z80.DE2.w.l = val; break;
+		case Z80_HL2: Z80.HL2.w.l = val; break;
+		case Z80_IM: Z80.IM = val; break;
+		case Z80_IFF1: Z80.IFF1 = val; break;
+		case Z80_IFF2: Z80.IFF2 = val; break;
+		case Z80_HALT: Z80.HALT = val; break;
+		case Z80_NMI_STATE: z80_set_nmi_line(val); break;
+		case Z80_IRQ_STATE: z80_set_irq_line(0,val); break;
+		case Z80_DC0: Z80.int_state[0] = val; break;
+		case Z80_DC1: Z80.int_state[1] = val; break;
+		case Z80_DC2: Z80.int_state[2] = val; break;
+		case Z80_DC3: Z80.int_state[3] = val; break;
+        default:
+			if( regnum <= REG_SP_CONTENTS )
+			{
+				unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
+				if( offset < 0xffff )
+				{
+					WM( offset, val & 0xff );
+					WM( offset+1, (val >> 8) & 0xff );
+				}
+			}
+    }
+}
+
+/****************************************************************************
+ * Set NMI line state
+ ****************************************************************************/
+void z80_set_nmi_line(int state)
+{
+	if( Z80.nmi_state == state ) return;
+
+    Z80.nmi_state = state;
+	if( state == CLEAR_LINE ) return;
+
+	_PPC = -1;			/* there isn't a valid previous program counter */
+	LEAVE_HALT; 		/* Check if processor was halted */
+
+	_IFF1 = 0;
+    PUSH( PC );
+	_PCD = 0x0066;
+	Z80.extra_cycles += 11;
+}
+
+/****************************************************************************
+ * Set IRQ line state
+ ****************************************************************************/
+void z80_set_irq_line(int irqline, int state)
+{
+    Z80.irq_state = state;
+	if( state == CLEAR_LINE ) return;
+
+	if( Z80.irq_max )
+	{
+		int daisychain, device, int_state;
+		daisychain = (*Z80.irq_callback)(irqline);
+		device = daisychain >> 8;
+		int_state = daisychain & 0xff;
+
+		if( Z80.int_state[device] != int_state )
+		{
+			/* set new interrupt status */
+            Z80.int_state[device] = int_state;
+			/* check interrupt status */
+			Z80.request_irq = Z80.service_irq = -1;
+
+            /* search higher IRQ or IEO */
+			for( device = 0 ; device < Z80.irq_max ; device ++ )
+			{
+				/* IEO = disable ? */
+				if( Z80.int_state[device] & Z80_INT_IEO )
+				{
+					Z80.request_irq = -1;		/* if IEO is disable , masking lower IRQ */
+					Z80.service_irq = device;	/* set highest interrupt service device */
+				}
+				/* IRQ = request ? */
+				if( Z80.int_state[device] & Z80_INT_REQ )
+					Z80.request_irq = device;
+			}
+			if( Z80.request_irq < 0 ) return;
+		}
+		else
+		{
+			return;
+		}
+	}
+	take_interrupt();
+}
+
+/****************************************************************************
+ * Set IRQ vector callback
+ ****************************************************************************/
+void z80_set_irq_callback(int (*callback)(int))
+{
+    Z80.irq_callback = callback;
+}
diff --git a/MCUME_pico2/picosms/z80.h b/MCUME_pico2/picosms/z80.h
new file mode 100644
index 0000000..283dd0e
--- /dev/null
+++ b/MCUME_pico2/picosms/z80.h
@@ -0,0 +1,76 @@
+#ifndef Z80_H
+#define Z80_H
+
+
+/*#define CLEAR_LINE      0*/       /* clear (a fired, held or pulsed) line */
+/*#define ASSERT_LINE     1*/       /* assert an interrupt immediately */
+
+#include "cpuintrf.h"
+
+enum {
+	Z80_PC=1, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL,
+	Z80_IX, Z80_IY,	Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2,
+	Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT,
+	Z80_NMI_STATE, Z80_IRQ_STATE, Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3,
+	Z80_NMI_NESTING
+};
+
+extern int z80_ICount;              /* T-state count                        */
+
+#define Z80_IGNORE_INT  -1          /* Ignore interrupt                     */
+#define Z80_NMI_INT 	-2			/* Execute NMI							*/
+#define Z80_IRQ_INT 	-1000		/* Execute IRQ							*/
+
+/* Port number written to when entering/leaving HALT state */
+#define Z80_HALT_PORT   0x10000
+
+extern void z80_reset (void *param);
+extern void z80_exit (void);
+extern int z80_execute(int cycles);
+extern void z80_burn(int cycles);
+extern unsigned z80_get_context (void *dst);
+extern void z80_set_context (void *src);
+extern unsigned z80_get_pc (void);
+extern void z80_set_pc (unsigned val);
+extern unsigned z80_get_sp (void);
+extern void z80_set_sp (unsigned val);
+extern unsigned z80_get_reg (int regnum);
+extern void z80_set_reg (int regnum, unsigned val);
+extern void z80_set_nmi_line(int state);
+extern void z80_set_irq_line(int irqline, int state);
+extern void z80_set_irq_callback(int (*irq_callback)(int));
+extern void z80_state_save(void *file);
+extern void z80_state_load(void *file);
+extern const char *z80_info(void *context, int regnum);
+extern unsigned z80_dasm(char *buffer, unsigned pc);
+
+#ifdef MAME_DEBUG
+extern unsigned DasmZ80(char *buffer, unsigned pc);
+#endif
+
+/****************************************************************************/
+/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh  */
+/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128)    */
+/****************************************************************************/
+typedef struct {
+/* 00 */    PAIR    PREPC,PC,SP,AF,BC,DE,HL,IX,IY;
+/* 24 */    PAIR    AF2,BC2,DE2,HL2;
+/* 34 */    UINT8   R,R2,IFF1,IFF2,HALT,IM,I;
+/* 3B */    UINT8   irq_max;            /* number of daisy chain devices        */
+/* 3C */	INT8	request_irq;		/* daisy chain next request device		*/
+/* 3D */	INT8	service_irq;		/* daisy chain next reti handling device */
+/* 3E */	UINT8	nmi_state;			/* nmi line state */
+/* 3F */	UINT8	irq_state;			/* irq line state */
+/* 40 */    UINT8   int_state[Z80_MAXDAISY];
+/* 44 */    Z80_DaisyChain irq[Z80_MAXDAISY];
+/* 84 */    int     (*irq_callback)(int irqline);
+/* 88 */    int     extra_cycles;       /* extra cycles for interrupts */
+}   Z80_Regs;
+
+extern Z80_Regs *Z80_Context;
+extern int after_EI;
+extern unsigned char *cpu_readmap[8];
+extern unsigned char *cpu_writemap[8];
+
+#endif
+
diff --git a/MCUME_pico2/picosms/z80daa.h b/MCUME_pico2/picosms/z80daa.h
new file mode 100644
index 0000000..bb10a02
--- /dev/null
+++ b/MCUME_pico2/picosms/z80daa.h
@@ -0,0 +1,2052 @@
+
+static const UINT16 DAATable[0x800] = {
+  (0x00<<8)   +ZF         +VF      ,
+  (0x01<<8)                        ,
+  (0x02<<8)                        ,
+  (0x03<<8)               +VF      ,
+  (0x04<<8)                        ,
+  (0x05<<8)               +VF      ,
+  (0x06<<8)               +VF      ,
+  (0x07<<8)                        ,
+  (0x08<<8)            +XF         ,
+  (0x09<<8)            +XF+VF      ,
+  (0x10<<8)         +HF            ,
+  (0x11<<8)         +HF   +VF      ,
+  (0x12<<8)         +HF   +VF      ,
+  (0x13<<8)         +HF            ,
+  (0x14<<8)         +HF   +VF      ,
+  (0x15<<8)         +HF            ,
+  (0x10<<8)                        ,
+  (0x11<<8)               +VF      ,
+  (0x12<<8)               +VF      ,
+  (0x13<<8)                        ,
+  (0x14<<8)               +VF      ,
+  (0x15<<8)                        ,
+  (0x16<<8)                        ,
+  (0x17<<8)               +VF      ,
+  (0x18<<8)            +XF+VF      ,
+  (0x19<<8)            +XF         ,
+  (0x20<<8)      +YF+HF            ,
+  (0x21<<8)      +YF+HF   +VF      ,
+  (0x22<<8)      +YF+HF   +VF      ,
+  (0x23<<8)      +YF+HF            ,
+  (0x24<<8)      +YF+HF   +VF      ,
+  (0x25<<8)      +YF+HF            ,
+  (0x20<<8)      +YF               ,
+  (0x21<<8)      +YF      +VF      ,
+  (0x22<<8)      +YF      +VF      ,
+  (0x23<<8)      +YF               ,
+  (0x24<<8)      +YF      +VF      ,
+  (0x25<<8)      +YF               ,
+  (0x26<<8)      +YF               ,
+  (0x27<<8)      +YF      +VF      ,
+  (0x28<<8)      +YF   +XF+VF      ,
+  (0x29<<8)      +YF   +XF         ,
+  (0x30<<8)      +YF+HF   +VF      ,
+  (0x31<<8)      +YF+HF            ,
+  (0x32<<8)      +YF+HF            ,
+  (0x33<<8)      +YF+HF   +VF      ,
+  (0x34<<8)      +YF+HF            ,
+  (0x35<<8)      +YF+HF   +VF      ,
+  (0x30<<8)      +YF      +VF      ,
+  (0x31<<8)      +YF               ,
+  (0x32<<8)      +YF               ,
+  (0x33<<8)      +YF      +VF      ,
+  (0x34<<8)      +YF               ,
+  (0x35<<8)      +YF      +VF      ,
+  (0x36<<8)      +YF      +VF      ,
+  (0x37<<8)      +YF               ,
+  (0x38<<8)      +YF   +XF         ,
+  (0x39<<8)      +YF   +XF+VF      ,
+  (0x40<<8)         +HF            ,
+  (0x41<<8)         +HF   +VF      ,
+  (0x42<<8)         +HF   +VF      ,
+  (0x43<<8)         +HF            ,
+  (0x44<<8)         +HF   +VF      ,
+  (0x45<<8)         +HF            ,
+  (0x40<<8)                        ,
+  (0x41<<8)               +VF      ,
+  (0x42<<8)               +VF      ,
+  (0x43<<8)                        ,
+  (0x44<<8)               +VF      ,
+  (0x45<<8)                        ,
+  (0x46<<8)                        ,
+  (0x47<<8)               +VF      ,
+  (0x48<<8)            +XF+VF      ,
+  (0x49<<8)            +XF         ,
+  (0x50<<8)         +HF   +VF      ,
+  (0x51<<8)         +HF            ,
+  (0x52<<8)         +HF            ,
+  (0x53<<8)         +HF   +VF      ,
+  (0x54<<8)         +HF            ,
+  (0x55<<8)         +HF   +VF      ,
+  (0x50<<8)               +VF      ,
+  (0x51<<8)                        ,
+  (0x52<<8)                        ,
+  (0x53<<8)               +VF      ,
+  (0x54<<8)                        ,
+  (0x55<<8)               +VF      ,
+  (0x56<<8)               +VF      ,
+  (0x57<<8)                        ,
+  (0x58<<8)            +XF         ,
+  (0x59<<8)            +XF+VF      ,
+  (0x60<<8)      +YF+HF   +VF      ,
+  (0x61<<8)      +YF+HF            ,
+  (0x62<<8)      +YF+HF            ,
+  (0x63<<8)      +YF+HF   +VF      ,
+  (0x64<<8)      +YF+HF            ,
+  (0x65<<8)      +YF+HF   +VF      ,
+  (0x60<<8)      +YF      +VF      ,
+  (0x61<<8)      +YF               ,
+  (0x62<<8)      +YF               ,
+  (0x63<<8)      +YF      +VF      ,
+  (0x64<<8)      +YF               ,
+  (0x65<<8)      +YF      +VF      ,
+  (0x66<<8)      +YF      +VF      ,
+  (0x67<<8)      +YF               ,
+  (0x68<<8)      +YF   +XF         ,
+  (0x69<<8)      +YF   +XF+VF      ,
+  (0x70<<8)      +YF+HF            ,
+  (0x71<<8)      +YF+HF   +VF      ,
+  (0x72<<8)      +YF+HF   +VF      ,
+  (0x73<<8)      +YF+HF            ,
+  (0x74<<8)      +YF+HF   +VF      ,
+  (0x75<<8)      +YF+HF            ,
+  (0x70<<8)      +YF               ,
+  (0x71<<8)      +YF      +VF      ,
+  (0x72<<8)      +YF      +VF      ,
+  (0x73<<8)      +YF               ,
+  (0x74<<8)      +YF      +VF      ,
+  (0x75<<8)      +YF               ,
+  (0x76<<8)      +YF               ,
+  (0x77<<8)      +YF      +VF      ,
+  (0x78<<8)      +YF   +XF+VF      ,
+  (0x79<<8)      +YF   +XF         ,
+  (0x80<<8)+SF      +HF            ,
+  (0x81<<8)+SF      +HF   +VF      ,
+  (0x82<<8)+SF      +HF   +VF      ,
+  (0x83<<8)+SF      +HF            ,
+  (0x84<<8)+SF      +HF   +VF      ,
+  (0x85<<8)+SF      +HF            ,
+  (0x80<<8)+SF                     ,
+  (0x81<<8)+SF            +VF      ,
+  (0x82<<8)+SF            +VF      ,
+  (0x83<<8)+SF                     ,
+  (0x84<<8)+SF            +VF      ,
+  (0x85<<8)+SF                     ,
+  (0x86<<8)+SF                     ,
+  (0x87<<8)+SF            +VF      ,
+  (0x88<<8)+SF         +XF+VF      ,
+  (0x89<<8)+SF         +XF         ,
+  (0x90<<8)+SF      +HF   +VF      ,
+  (0x91<<8)+SF      +HF            ,
+  (0x92<<8)+SF      +HF            ,
+  (0x93<<8)+SF      +HF   +VF      ,
+  (0x94<<8)+SF      +HF            ,
+  (0x95<<8)+SF      +HF   +VF      ,
+  (0x90<<8)+SF            +VF      ,
+  (0x91<<8)+SF                     ,
+  (0x92<<8)+SF                     ,
+  (0x93<<8)+SF            +VF      ,
+  (0x94<<8)+SF                     ,
+  (0x95<<8)+SF            +VF      ,
+  (0x96<<8)+SF            +VF      ,
+  (0x97<<8)+SF                     ,
+  (0x98<<8)+SF         +XF         ,
+  (0x99<<8)+SF         +XF+VF      ,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF   +CF,
+  (0x01<<8)                     +CF,
+  (0x02<<8)                     +CF,
+  (0x03<<8)               +VF   +CF,
+  (0x04<<8)                     +CF,
+  (0x05<<8)               +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x10<<8)                     +CF,
+  (0x11<<8)               +VF   +CF,
+  (0x12<<8)               +VF   +CF,
+  (0x13<<8)                     +CF,
+  (0x14<<8)               +VF   +CF,
+  (0x15<<8)                     +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x20<<8)      +YF            +CF,
+  (0x21<<8)      +YF      +VF   +CF,
+  (0x22<<8)      +YF      +VF   +CF,
+  (0x23<<8)      +YF            +CF,
+  (0x24<<8)      +YF      +VF   +CF,
+  (0x25<<8)      +YF            +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x30<<8)      +YF      +VF   +CF,
+  (0x31<<8)      +YF            +CF,
+  (0x32<<8)      +YF            +CF,
+  (0x33<<8)      +YF      +VF   +CF,
+  (0x34<<8)      +YF            +CF,
+  (0x35<<8)      +YF      +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x40<<8)                     +CF,
+  (0x41<<8)               +VF   +CF,
+  (0x42<<8)               +VF   +CF,
+  (0x43<<8)                     +CF,
+  (0x44<<8)               +VF   +CF,
+  (0x45<<8)                     +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x50<<8)               +VF   +CF,
+  (0x51<<8)                     +CF,
+  (0x52<<8)                     +CF,
+  (0x53<<8)               +VF   +CF,
+  (0x54<<8)                     +CF,
+  (0x55<<8)               +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x60<<8)      +YF      +VF   +CF,
+  (0x61<<8)      +YF            +CF,
+  (0x62<<8)      +YF            +CF,
+  (0x63<<8)      +YF      +VF   +CF,
+  (0x64<<8)      +YF            +CF,
+  (0x65<<8)      +YF      +VF   +CF,
+  (0x66<<8)      +YF      +VF   +CF,
+  (0x67<<8)      +YF            +CF,
+  (0x68<<8)      +YF   +XF      +CF,
+  (0x69<<8)      +YF   +XF+VF   +CF,
+  (0x70<<8)      +YF+HF         +CF,
+  (0x71<<8)      +YF+HF   +VF   +CF,
+  (0x72<<8)      +YF+HF   +VF   +CF,
+  (0x73<<8)      +YF+HF         +CF,
+  (0x74<<8)      +YF+HF   +VF   +CF,
+  (0x75<<8)      +YF+HF         +CF,
+  (0x70<<8)      +YF            +CF,
+  (0x71<<8)      +YF      +VF   +CF,
+  (0x72<<8)      +YF      +VF   +CF,
+  (0x73<<8)      +YF            +CF,
+  (0x74<<8)      +YF      +VF   +CF,
+  (0x75<<8)      +YF            +CF,
+  (0x76<<8)      +YF            +CF,
+  (0x77<<8)      +YF      +VF   +CF,
+  (0x78<<8)      +YF   +XF+VF   +CF,
+  (0x79<<8)      +YF   +XF      +CF,
+  (0x80<<8)+SF      +HF         +CF,
+  (0x81<<8)+SF      +HF   +VF   +CF,
+  (0x82<<8)+SF      +HF   +VF   +CF,
+  (0x83<<8)+SF      +HF         +CF,
+  (0x84<<8)+SF      +HF   +VF   +CF,
+  (0x85<<8)+SF      +HF         +CF,
+  (0x80<<8)+SF                  +CF,
+  (0x81<<8)+SF            +VF   +CF,
+  (0x82<<8)+SF            +VF   +CF,
+  (0x83<<8)+SF                  +CF,
+  (0x84<<8)+SF            +VF   +CF,
+  (0x85<<8)+SF                  +CF,
+  (0x86<<8)+SF                  +CF,
+  (0x87<<8)+SF            +VF   +CF,
+  (0x88<<8)+SF         +XF+VF   +CF,
+  (0x89<<8)+SF         +XF      +CF,
+  (0x90<<8)+SF      +HF   +VF   +CF,
+  (0x91<<8)+SF      +HF         +CF,
+  (0x92<<8)+SF      +HF         +CF,
+  (0x93<<8)+SF      +HF   +VF   +CF,
+  (0x94<<8)+SF      +HF         +CF,
+  (0x95<<8)+SF      +HF   +VF   +CF,
+  (0x90<<8)+SF            +VF   +CF,
+  (0x91<<8)+SF                  +CF,
+  (0x92<<8)+SF                  +CF,
+  (0x93<<8)+SF            +VF   +CF,
+  (0x94<<8)+SF                  +CF,
+  (0x95<<8)+SF            +VF   +CF,
+  (0x96<<8)+SF            +VF   +CF,
+  (0x97<<8)+SF                  +CF,
+  (0x98<<8)+SF         +XF      +CF,
+  (0x99<<8)+SF         +XF+VF   +CF,
+  (0xA0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA1<<8)+SF   +YF+HF         +CF,
+  (0xA2<<8)+SF   +YF+HF         +CF,
+  (0xA3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA4<<8)+SF   +YF+HF         +CF,
+  (0xA5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA0<<8)+SF   +YF      +VF   +CF,
+  (0xA1<<8)+SF   +YF            +CF,
+  (0xA2<<8)+SF   +YF            +CF,
+  (0xA3<<8)+SF   +YF      +VF   +CF,
+  (0xA4<<8)+SF   +YF            +CF,
+  (0xA5<<8)+SF   +YF      +VF   +CF,
+  (0xA6<<8)+SF   +YF      +VF   +CF,
+  (0xA7<<8)+SF   +YF            +CF,
+  (0xA8<<8)+SF   +YF   +XF      +CF,
+  (0xA9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB0<<8)+SF   +YF+HF         +CF,
+  (0xB1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB3<<8)+SF   +YF+HF         +CF,
+  (0xB4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB5<<8)+SF   +YF+HF         +CF,
+  (0xB0<<8)+SF   +YF            +CF,
+  (0xB1<<8)+SF   +YF      +VF   +CF,
+  (0xB2<<8)+SF   +YF      +VF   +CF,
+  (0xB3<<8)+SF   +YF            +CF,
+  (0xB4<<8)+SF   +YF      +VF   +CF,
+  (0xB5<<8)+SF   +YF            +CF,
+  (0xB6<<8)+SF   +YF            +CF,
+  (0xB7<<8)+SF   +YF      +VF   +CF,
+  (0xB8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB9<<8)+SF   +YF   +XF      +CF,
+  (0xC0<<8)+SF      +HF   +VF   +CF,
+  (0xC1<<8)+SF      +HF         +CF,
+  (0xC2<<8)+SF      +HF         +CF,
+  (0xC3<<8)+SF      +HF   +VF   +CF,
+  (0xC4<<8)+SF      +HF         +CF,
+  (0xC5<<8)+SF      +HF   +VF   +CF,
+  (0xC0<<8)+SF            +VF   +CF,
+  (0xC1<<8)+SF                  +CF,
+  (0xC2<<8)+SF                  +CF,
+  (0xC3<<8)+SF            +VF   +CF,
+  (0xC4<<8)+SF                  +CF,
+  (0xC5<<8)+SF            +VF   +CF,
+  (0xC6<<8)+SF            +VF   +CF,
+  (0xC7<<8)+SF                  +CF,
+  (0xC8<<8)+SF         +XF      +CF,
+  (0xC9<<8)+SF         +XF+VF   +CF,
+  (0xD0<<8)+SF      +HF         +CF,
+  (0xD1<<8)+SF      +HF   +VF   +CF,
+  (0xD2<<8)+SF      +HF   +VF   +CF,
+  (0xD3<<8)+SF      +HF         +CF,
+  (0xD4<<8)+SF      +HF   +VF   +CF,
+  (0xD5<<8)+SF      +HF         +CF,
+  (0xD0<<8)+SF                  +CF,
+  (0xD1<<8)+SF            +VF   +CF,
+  (0xD2<<8)+SF            +VF   +CF,
+  (0xD3<<8)+SF                  +CF,
+  (0xD4<<8)+SF            +VF   +CF,
+  (0xD5<<8)+SF                  +CF,
+  (0xD6<<8)+SF                  +CF,
+  (0xD7<<8)+SF            +VF   +CF,
+  (0xD8<<8)+SF         +XF+VF   +CF,
+  (0xD9<<8)+SF         +XF      +CF,
+  (0xE0<<8)+SF   +YF+HF         +CF,
+  (0xE1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE3<<8)+SF   +YF+HF         +CF,
+  (0xE4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE5<<8)+SF   +YF+HF         +CF,
+  (0xE0<<8)+SF   +YF            +CF,
+  (0xE1<<8)+SF   +YF      +VF   +CF,
+  (0xE2<<8)+SF   +YF      +VF   +CF,
+  (0xE3<<8)+SF   +YF            +CF,
+  (0xE4<<8)+SF   +YF      +VF   +CF,
+  (0xE5<<8)+SF   +YF            +CF,
+  (0xE6<<8)+SF   +YF            +CF,
+  (0xE7<<8)+SF   +YF      +VF   +CF,
+  (0xE8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xE9<<8)+SF   +YF   +XF      +CF,
+  (0xF0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF1<<8)+SF   +YF+HF         +CF,
+  (0xF2<<8)+SF   +YF+HF         +CF,
+  (0xF3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF4<<8)+SF   +YF+HF         +CF,
+  (0xF5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF0<<8)+SF   +YF      +VF   +CF,
+  (0xF1<<8)+SF   +YF            +CF,
+  (0xF2<<8)+SF   +YF            +CF,
+  (0xF3<<8)+SF   +YF      +VF   +CF,
+  (0xF4<<8)+SF   +YF            +CF,
+  (0xF5<<8)+SF   +YF      +VF   +CF,
+  (0xF6<<8)+SF   +YF      +VF   +CF,
+  (0xF7<<8)+SF   +YF            +CF,
+  (0xF8<<8)+SF   +YF   +XF      +CF,
+  (0xF9<<8)+SF   +YF   +XF+VF   +CF,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF   +CF,
+  (0x01<<8)                     +CF,
+  (0x02<<8)                     +CF,
+  (0x03<<8)               +VF   +CF,
+  (0x04<<8)                     +CF,
+  (0x05<<8)               +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x10<<8)                     +CF,
+  (0x11<<8)               +VF   +CF,
+  (0x12<<8)               +VF   +CF,
+  (0x13<<8)                     +CF,
+  (0x14<<8)               +VF   +CF,
+  (0x15<<8)                     +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x20<<8)      +YF            +CF,
+  (0x21<<8)      +YF      +VF   +CF,
+  (0x22<<8)      +YF      +VF   +CF,
+  (0x23<<8)      +YF            +CF,
+  (0x24<<8)      +YF      +VF   +CF,
+  (0x25<<8)      +YF            +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x30<<8)      +YF      +VF   +CF,
+  (0x31<<8)      +YF            +CF,
+  (0x32<<8)      +YF            +CF,
+  (0x33<<8)      +YF      +VF   +CF,
+  (0x34<<8)      +YF            +CF,
+  (0x35<<8)      +YF      +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x40<<8)                     +CF,
+  (0x41<<8)               +VF   +CF,
+  (0x42<<8)               +VF   +CF,
+  (0x43<<8)                     +CF,
+  (0x44<<8)               +VF   +CF,
+  (0x45<<8)                     +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x50<<8)               +VF   +CF,
+  (0x51<<8)                     +CF,
+  (0x52<<8)                     +CF,
+  (0x53<<8)               +VF   +CF,
+  (0x54<<8)                     +CF,
+  (0x55<<8)               +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x06<<8)               +VF      ,
+  (0x07<<8)                        ,
+  (0x08<<8)            +XF         ,
+  (0x09<<8)            +XF+VF      ,
+  (0x0A<<8)            +XF+VF      ,
+  (0x0B<<8)            +XF         ,
+  (0x0C<<8)            +XF+VF      ,
+  (0x0D<<8)            +XF         ,
+  (0x0E<<8)            +XF         ,
+  (0x0F<<8)            +XF+VF      ,
+  (0x10<<8)         +HF            ,
+  (0x11<<8)         +HF   +VF      ,
+  (0x12<<8)         +HF   +VF      ,
+  (0x13<<8)         +HF            ,
+  (0x14<<8)         +HF   +VF      ,
+  (0x15<<8)         +HF            ,
+  (0x16<<8)                        ,
+  (0x17<<8)               +VF      ,
+  (0x18<<8)            +XF+VF      ,
+  (0x19<<8)            +XF         ,
+  (0x1A<<8)            +XF         ,
+  (0x1B<<8)            +XF+VF      ,
+  (0x1C<<8)            +XF         ,
+  (0x1D<<8)            +XF+VF      ,
+  (0x1E<<8)            +XF+VF      ,
+  (0x1F<<8)            +XF         ,
+  (0x20<<8)      +YF+HF            ,
+  (0x21<<8)      +YF+HF   +VF      ,
+  (0x22<<8)      +YF+HF   +VF      ,
+  (0x23<<8)      +YF+HF            ,
+  (0x24<<8)      +YF+HF   +VF      ,
+  (0x25<<8)      +YF+HF            ,
+  (0x26<<8)      +YF               ,
+  (0x27<<8)      +YF      +VF      ,
+  (0x28<<8)      +YF   +XF+VF      ,
+  (0x29<<8)      +YF   +XF         ,
+  (0x2A<<8)      +YF   +XF         ,
+  (0x2B<<8)      +YF   +XF+VF      ,
+  (0x2C<<8)      +YF   +XF         ,
+  (0x2D<<8)      +YF   +XF+VF      ,
+  (0x2E<<8)      +YF   +XF+VF      ,
+  (0x2F<<8)      +YF   +XF         ,
+  (0x30<<8)      +YF+HF   +VF      ,
+  (0x31<<8)      +YF+HF            ,
+  (0x32<<8)      +YF+HF            ,
+  (0x33<<8)      +YF+HF   +VF      ,
+  (0x34<<8)      +YF+HF            ,
+  (0x35<<8)      +YF+HF   +VF      ,
+  (0x36<<8)      +YF      +VF      ,
+  (0x37<<8)      +YF               ,
+  (0x38<<8)      +YF   +XF         ,
+  (0x39<<8)      +YF   +XF+VF      ,
+  (0x3A<<8)      +YF   +XF+VF      ,
+  (0x3B<<8)      +YF   +XF         ,
+  (0x3C<<8)      +YF   +XF+VF      ,
+  (0x3D<<8)      +YF   +XF         ,
+  (0x3E<<8)      +YF   +XF         ,
+  (0x3F<<8)      +YF   +XF+VF      ,
+  (0x40<<8)         +HF            ,
+  (0x41<<8)         +HF   +VF      ,
+  (0x42<<8)         +HF   +VF      ,
+  (0x43<<8)         +HF            ,
+  (0x44<<8)         +HF   +VF      ,
+  (0x45<<8)         +HF            ,
+  (0x46<<8)                        ,
+  (0x47<<8)               +VF      ,
+  (0x48<<8)            +XF+VF      ,
+  (0x49<<8)            +XF         ,
+  (0x4A<<8)            +XF         ,
+  (0x4B<<8)            +XF+VF      ,
+  (0x4C<<8)            +XF         ,
+  (0x4D<<8)            +XF+VF      ,
+  (0x4E<<8)            +XF+VF      ,
+  (0x4F<<8)            +XF         ,
+  (0x50<<8)         +HF   +VF      ,
+  (0x51<<8)         +HF            ,
+  (0x52<<8)         +HF            ,
+  (0x53<<8)         +HF   +VF      ,
+  (0x54<<8)         +HF            ,
+  (0x55<<8)         +HF   +VF      ,
+  (0x56<<8)               +VF      ,
+  (0x57<<8)                        ,
+  (0x58<<8)            +XF         ,
+  (0x59<<8)            +XF+VF      ,
+  (0x5A<<8)            +XF+VF      ,
+  (0x5B<<8)            +XF         ,
+  (0x5C<<8)            +XF+VF      ,
+  (0x5D<<8)            +XF         ,
+  (0x5E<<8)            +XF         ,
+  (0x5F<<8)            +XF+VF      ,
+  (0x60<<8)      +YF+HF   +VF      ,
+  (0x61<<8)      +YF+HF            ,
+  (0x62<<8)      +YF+HF            ,
+  (0x63<<8)      +YF+HF   +VF      ,
+  (0x64<<8)      +YF+HF            ,
+  (0x65<<8)      +YF+HF   +VF      ,
+  (0x66<<8)      +YF      +VF      ,
+  (0x67<<8)      +YF               ,
+  (0x68<<8)      +YF   +XF         ,
+  (0x69<<8)      +YF   +XF+VF      ,
+  (0x6A<<8)      +YF   +XF+VF      ,
+  (0x6B<<8)      +YF   +XF         ,
+  (0x6C<<8)      +YF   +XF+VF      ,
+  (0x6D<<8)      +YF   +XF         ,
+  (0x6E<<8)      +YF   +XF         ,
+  (0x6F<<8)      +YF   +XF+VF      ,
+  (0x70<<8)      +YF+HF            ,
+  (0x71<<8)      +YF+HF   +VF      ,
+  (0x72<<8)      +YF+HF   +VF      ,
+  (0x73<<8)      +YF+HF            ,
+  (0x74<<8)      +YF+HF   +VF      ,
+  (0x75<<8)      +YF+HF            ,
+  (0x76<<8)      +YF               ,
+  (0x77<<8)      +YF      +VF      ,
+  (0x78<<8)      +YF   +XF+VF      ,
+  (0x79<<8)      +YF   +XF         ,
+  (0x7A<<8)      +YF   +XF         ,
+  (0x7B<<8)      +YF   +XF+VF      ,
+  (0x7C<<8)      +YF   +XF         ,
+  (0x7D<<8)      +YF   +XF+VF      ,
+  (0x7E<<8)      +YF   +XF+VF      ,
+  (0x7F<<8)      +YF   +XF         ,
+  (0x80<<8)+SF      +HF            ,
+  (0x81<<8)+SF      +HF   +VF      ,
+  (0x82<<8)+SF      +HF   +VF      ,
+  (0x83<<8)+SF      +HF            ,
+  (0x84<<8)+SF      +HF   +VF      ,
+  (0x85<<8)+SF      +HF            ,
+  (0x86<<8)+SF                     ,
+  (0x87<<8)+SF            +VF      ,
+  (0x88<<8)+SF         +XF+VF      ,
+  (0x89<<8)+SF         +XF         ,
+  (0x8A<<8)+SF         +XF         ,
+  (0x8B<<8)+SF         +XF+VF      ,
+  (0x8C<<8)+SF         +XF         ,
+  (0x8D<<8)+SF         +XF+VF      ,
+  (0x8E<<8)+SF         +XF+VF      ,
+  (0x8F<<8)+SF         +XF         ,
+  (0x90<<8)+SF      +HF   +VF      ,
+  (0x91<<8)+SF      +HF            ,
+  (0x92<<8)+SF      +HF            ,
+  (0x93<<8)+SF      +HF   +VF      ,
+  (0x94<<8)+SF      +HF            ,
+  (0x95<<8)+SF      +HF   +VF      ,
+  (0x96<<8)+SF            +VF      ,
+  (0x97<<8)+SF                     ,
+  (0x98<<8)+SF         +XF         ,
+  (0x99<<8)+SF         +XF+VF      ,
+  (0x9A<<8)+SF         +XF+VF      ,
+  (0x9B<<8)+SF         +XF         ,
+  (0x9C<<8)+SF         +XF+VF      ,
+  (0x9D<<8)+SF         +XF         ,
+  (0x9E<<8)+SF         +XF         ,
+  (0x9F<<8)+SF         +XF+VF      ,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x0A<<8)            +XF+VF   +CF,
+  (0x0B<<8)            +XF      +CF,
+  (0x0C<<8)            +XF+VF   +CF,
+  (0x0D<<8)            +XF      +CF,
+  (0x0E<<8)            +XF      +CF,
+  (0x0F<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x1A<<8)            +XF      +CF,
+  (0x1B<<8)            +XF+VF   +CF,
+  (0x1C<<8)            +XF      +CF,
+  (0x1D<<8)            +XF+VF   +CF,
+  (0x1E<<8)            +XF+VF   +CF,
+  (0x1F<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x2A<<8)      +YF   +XF      +CF,
+  (0x2B<<8)      +YF   +XF+VF   +CF,
+  (0x2C<<8)      +YF   +XF      +CF,
+  (0x2D<<8)      +YF   +XF+VF   +CF,
+  (0x2E<<8)      +YF   +XF+VF   +CF,
+  (0x2F<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x3A<<8)      +YF   +XF+VF   +CF,
+  (0x3B<<8)      +YF   +XF      +CF,
+  (0x3C<<8)      +YF   +XF+VF   +CF,
+  (0x3D<<8)      +YF   +XF      +CF,
+  (0x3E<<8)      +YF   +XF      +CF,
+  (0x3F<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x4A<<8)            +XF      +CF,
+  (0x4B<<8)            +XF+VF   +CF,
+  (0x4C<<8)            +XF      +CF,
+  (0x4D<<8)            +XF+VF   +CF,
+  (0x4E<<8)            +XF+VF   +CF,
+  (0x4F<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x5A<<8)            +XF+VF   +CF,
+  (0x5B<<8)            +XF      +CF,
+  (0x5C<<8)            +XF+VF   +CF,
+  (0x5D<<8)            +XF      +CF,
+  (0x5E<<8)            +XF      +CF,
+  (0x5F<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x66<<8)      +YF      +VF   +CF,
+  (0x67<<8)      +YF            +CF,
+  (0x68<<8)      +YF   +XF      +CF,
+  (0x69<<8)      +YF   +XF+VF   +CF,
+  (0x6A<<8)      +YF   +XF+VF   +CF,
+  (0x6B<<8)      +YF   +XF      +CF,
+  (0x6C<<8)      +YF   +XF+VF   +CF,
+  (0x6D<<8)      +YF   +XF      +CF,
+  (0x6E<<8)      +YF   +XF      +CF,
+  (0x6F<<8)      +YF   +XF+VF   +CF,
+  (0x70<<8)      +YF+HF         +CF,
+  (0x71<<8)      +YF+HF   +VF   +CF,
+  (0x72<<8)      +YF+HF   +VF   +CF,
+  (0x73<<8)      +YF+HF         +CF,
+  (0x74<<8)      +YF+HF   +VF   +CF,
+  (0x75<<8)      +YF+HF         +CF,
+  (0x76<<8)      +YF            +CF,
+  (0x77<<8)      +YF      +VF   +CF,
+  (0x78<<8)      +YF   +XF+VF   +CF,
+  (0x79<<8)      +YF   +XF      +CF,
+  (0x7A<<8)      +YF   +XF      +CF,
+  (0x7B<<8)      +YF   +XF+VF   +CF,
+  (0x7C<<8)      +YF   +XF      +CF,
+  (0x7D<<8)      +YF   +XF+VF   +CF,
+  (0x7E<<8)      +YF   +XF+VF   +CF,
+  (0x7F<<8)      +YF   +XF      +CF,
+  (0x80<<8)+SF      +HF         +CF,
+  (0x81<<8)+SF      +HF   +VF   +CF,
+  (0x82<<8)+SF      +HF   +VF   +CF,
+  (0x83<<8)+SF      +HF         +CF,
+  (0x84<<8)+SF      +HF   +VF   +CF,
+  (0x85<<8)+SF      +HF         +CF,
+  (0x86<<8)+SF                  +CF,
+  (0x87<<8)+SF            +VF   +CF,
+  (0x88<<8)+SF         +XF+VF   +CF,
+  (0x89<<8)+SF         +XF      +CF,
+  (0x8A<<8)+SF         +XF      +CF,
+  (0x8B<<8)+SF         +XF+VF   +CF,
+  (0x8C<<8)+SF         +XF      +CF,
+  (0x8D<<8)+SF         +XF+VF   +CF,
+  (0x8E<<8)+SF         +XF+VF   +CF,
+  (0x8F<<8)+SF         +XF      +CF,
+  (0x90<<8)+SF      +HF   +VF   +CF,
+  (0x91<<8)+SF      +HF         +CF,
+  (0x92<<8)+SF      +HF         +CF,
+  (0x93<<8)+SF      +HF   +VF   +CF,
+  (0x94<<8)+SF      +HF         +CF,
+  (0x95<<8)+SF      +HF   +VF   +CF,
+  (0x96<<8)+SF            +VF   +CF,
+  (0x97<<8)+SF                  +CF,
+  (0x98<<8)+SF         +XF      +CF,
+  (0x99<<8)+SF         +XF+VF   +CF,
+  (0x9A<<8)+SF         +XF+VF   +CF,
+  (0x9B<<8)+SF         +XF      +CF,
+  (0x9C<<8)+SF         +XF+VF   +CF,
+  (0x9D<<8)+SF         +XF      +CF,
+  (0x9E<<8)+SF         +XF      +CF,
+  (0x9F<<8)+SF         +XF+VF   +CF,
+  (0xA0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA1<<8)+SF   +YF+HF         +CF,
+  (0xA2<<8)+SF   +YF+HF         +CF,
+  (0xA3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA4<<8)+SF   +YF+HF         +CF,
+  (0xA5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xA6<<8)+SF   +YF      +VF   +CF,
+  (0xA7<<8)+SF   +YF            +CF,
+  (0xA8<<8)+SF   +YF   +XF      +CF,
+  (0xA9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAA<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAB<<8)+SF   +YF   +XF      +CF,
+  (0xAC<<8)+SF   +YF   +XF+VF   +CF,
+  (0xAD<<8)+SF   +YF   +XF      +CF,
+  (0xAE<<8)+SF   +YF   +XF      +CF,
+  (0xAF<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB0<<8)+SF   +YF+HF         +CF,
+  (0xB1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB3<<8)+SF   +YF+HF         +CF,
+  (0xB4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xB5<<8)+SF   +YF+HF         +CF,
+  (0xB6<<8)+SF   +YF            +CF,
+  (0xB7<<8)+SF   +YF      +VF   +CF,
+  (0xB8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xB9<<8)+SF   +YF   +XF      +CF,
+  (0xBA<<8)+SF   +YF   +XF      +CF,
+  (0xBB<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBC<<8)+SF   +YF   +XF      +CF,
+  (0xBD<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBE<<8)+SF   +YF   +XF+VF   +CF,
+  (0xBF<<8)+SF   +YF   +XF      +CF,
+  (0xC0<<8)+SF      +HF   +VF   +CF,
+  (0xC1<<8)+SF      +HF         +CF,
+  (0xC2<<8)+SF      +HF         +CF,
+  (0xC3<<8)+SF      +HF   +VF   +CF,
+  (0xC4<<8)+SF      +HF         +CF,
+  (0xC5<<8)+SF      +HF   +VF   +CF,
+  (0xC6<<8)+SF            +VF   +CF,
+  (0xC7<<8)+SF                  +CF,
+  (0xC8<<8)+SF         +XF      +CF,
+  (0xC9<<8)+SF         +XF+VF   +CF,
+  (0xCA<<8)+SF         +XF+VF   +CF,
+  (0xCB<<8)+SF         +XF      +CF,
+  (0xCC<<8)+SF         +XF+VF   +CF,
+  (0xCD<<8)+SF         +XF      +CF,
+  (0xCE<<8)+SF         +XF      +CF,
+  (0xCF<<8)+SF         +XF+VF   +CF,
+  (0xD0<<8)+SF      +HF         +CF,
+  (0xD1<<8)+SF      +HF   +VF   +CF,
+  (0xD2<<8)+SF      +HF   +VF   +CF,
+  (0xD3<<8)+SF      +HF         +CF,
+  (0xD4<<8)+SF      +HF   +VF   +CF,
+  (0xD5<<8)+SF      +HF         +CF,
+  (0xD6<<8)+SF                  +CF,
+  (0xD7<<8)+SF            +VF   +CF,
+  (0xD8<<8)+SF         +XF+VF   +CF,
+  (0xD9<<8)+SF         +XF      +CF,
+  (0xDA<<8)+SF         +XF      +CF,
+  (0xDB<<8)+SF         +XF+VF   +CF,
+  (0xDC<<8)+SF         +XF      +CF,
+  (0xDD<<8)+SF         +XF+VF   +CF,
+  (0xDE<<8)+SF         +XF+VF   +CF,
+  (0xDF<<8)+SF         +XF      +CF,
+  (0xE0<<8)+SF   +YF+HF         +CF,
+  (0xE1<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE2<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE3<<8)+SF   +YF+HF         +CF,
+  (0xE4<<8)+SF   +YF+HF   +VF   +CF,
+  (0xE5<<8)+SF   +YF+HF         +CF,
+  (0xE6<<8)+SF   +YF            +CF,
+  (0xE7<<8)+SF   +YF      +VF   +CF,
+  (0xE8<<8)+SF   +YF   +XF+VF   +CF,
+  (0xE9<<8)+SF   +YF   +XF      +CF,
+  (0xEA<<8)+SF   +YF   +XF      +CF,
+  (0xEB<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEC<<8)+SF   +YF   +XF      +CF,
+  (0xED<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEE<<8)+SF   +YF   +XF+VF   +CF,
+  (0xEF<<8)+SF   +YF   +XF      +CF,
+  (0xF0<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF1<<8)+SF   +YF+HF         +CF,
+  (0xF2<<8)+SF   +YF+HF         +CF,
+  (0xF3<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF4<<8)+SF   +YF+HF         +CF,
+  (0xF5<<8)+SF   +YF+HF   +VF   +CF,
+  (0xF6<<8)+SF   +YF      +VF   +CF,
+  (0xF7<<8)+SF   +YF            +CF,
+  (0xF8<<8)+SF   +YF   +XF      +CF,
+  (0xF9<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFA<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFB<<8)+SF   +YF   +XF      +CF,
+  (0xFC<<8)+SF   +YF   +XF+VF   +CF,
+  (0xFD<<8)+SF   +YF   +XF      +CF,
+  (0xFE<<8)+SF   +YF   +XF      +CF,
+  (0xFF<<8)+SF   +YF   +XF+VF   +CF,
+  (0x00<<8)   +ZF   +HF   +VF   +CF,
+  (0x01<<8)         +HF         +CF,
+  (0x02<<8)         +HF         +CF,
+  (0x03<<8)         +HF   +VF   +CF,
+  (0x04<<8)         +HF         +CF,
+  (0x05<<8)         +HF   +VF   +CF,
+  (0x06<<8)               +VF   +CF,
+  (0x07<<8)                     +CF,
+  (0x08<<8)            +XF      +CF,
+  (0x09<<8)            +XF+VF   +CF,
+  (0x0A<<8)            +XF+VF   +CF,
+  (0x0B<<8)            +XF      +CF,
+  (0x0C<<8)            +XF+VF   +CF,
+  (0x0D<<8)            +XF      +CF,
+  (0x0E<<8)            +XF      +CF,
+  (0x0F<<8)            +XF+VF   +CF,
+  (0x10<<8)         +HF         +CF,
+  (0x11<<8)         +HF   +VF   +CF,
+  (0x12<<8)         +HF   +VF   +CF,
+  (0x13<<8)         +HF         +CF,
+  (0x14<<8)         +HF   +VF   +CF,
+  (0x15<<8)         +HF         +CF,
+  (0x16<<8)                     +CF,
+  (0x17<<8)               +VF   +CF,
+  (0x18<<8)            +XF+VF   +CF,
+  (0x19<<8)            +XF      +CF,
+  (0x1A<<8)            +XF      +CF,
+  (0x1B<<8)            +XF+VF   +CF,
+  (0x1C<<8)            +XF      +CF,
+  (0x1D<<8)            +XF+VF   +CF,
+  (0x1E<<8)            +XF+VF   +CF,
+  (0x1F<<8)            +XF      +CF,
+  (0x20<<8)      +YF+HF         +CF,
+  (0x21<<8)      +YF+HF   +VF   +CF,
+  (0x22<<8)      +YF+HF   +VF   +CF,
+  (0x23<<8)      +YF+HF         +CF,
+  (0x24<<8)      +YF+HF   +VF   +CF,
+  (0x25<<8)      +YF+HF         +CF,
+  (0x26<<8)      +YF            +CF,
+  (0x27<<8)      +YF      +VF   +CF,
+  (0x28<<8)      +YF   +XF+VF   +CF,
+  (0x29<<8)      +YF   +XF      +CF,
+  (0x2A<<8)      +YF   +XF      +CF,
+  (0x2B<<8)      +YF   +XF+VF   +CF,
+  (0x2C<<8)      +YF   +XF      +CF,
+  (0x2D<<8)      +YF   +XF+VF   +CF,
+  (0x2E<<8)      +YF   +XF+VF   +CF,
+  (0x2F<<8)      +YF   +XF      +CF,
+  (0x30<<8)      +YF+HF   +VF   +CF,
+  (0x31<<8)      +YF+HF         +CF,
+  (0x32<<8)      +YF+HF         +CF,
+  (0x33<<8)      +YF+HF   +VF   +CF,
+  (0x34<<8)      +YF+HF         +CF,
+  (0x35<<8)      +YF+HF   +VF   +CF,
+  (0x36<<8)      +YF      +VF   +CF,
+  (0x37<<8)      +YF            +CF,
+  (0x38<<8)      +YF   +XF      +CF,
+  (0x39<<8)      +YF   +XF+VF   +CF,
+  (0x3A<<8)      +YF   +XF+VF   +CF,
+  (0x3B<<8)      +YF   +XF      +CF,
+  (0x3C<<8)      +YF   +XF+VF   +CF,
+  (0x3D<<8)      +YF   +XF      +CF,
+  (0x3E<<8)      +YF   +XF      +CF,
+  (0x3F<<8)      +YF   +XF+VF   +CF,
+  (0x40<<8)         +HF         +CF,
+  (0x41<<8)         +HF   +VF   +CF,
+  (0x42<<8)         +HF   +VF   +CF,
+  (0x43<<8)         +HF         +CF,
+  (0x44<<8)         +HF   +VF   +CF,
+  (0x45<<8)         +HF         +CF,
+  (0x46<<8)                     +CF,
+  (0x47<<8)               +VF   +CF,
+  (0x48<<8)            +XF+VF   +CF,
+  (0x49<<8)            +XF      +CF,
+  (0x4A<<8)            +XF      +CF,
+  (0x4B<<8)            +XF+VF   +CF,
+  (0x4C<<8)            +XF      +CF,
+  (0x4D<<8)            +XF+VF   +CF,
+  (0x4E<<8)            +XF+VF   +CF,
+  (0x4F<<8)            +XF      +CF,
+  (0x50<<8)         +HF   +VF   +CF,
+  (0x51<<8)         +HF         +CF,
+  (0x52<<8)         +HF         +CF,
+  (0x53<<8)         +HF   +VF   +CF,
+  (0x54<<8)         +HF         +CF,
+  (0x55<<8)         +HF   +VF   +CF,
+  (0x56<<8)               +VF   +CF,
+  (0x57<<8)                     +CF,
+  (0x58<<8)            +XF      +CF,
+  (0x59<<8)            +XF+VF   +CF,
+  (0x5A<<8)            +XF+VF   +CF,
+  (0x5B<<8)            +XF      +CF,
+  (0x5C<<8)            +XF+VF   +CF,
+  (0x5D<<8)            +XF      +CF,
+  (0x5E<<8)            +XF      +CF,
+  (0x5F<<8)            +XF+VF   +CF,
+  (0x60<<8)      +YF+HF   +VF   +CF,
+  (0x61<<8)      +YF+HF         +CF,
+  (0x62<<8)      +YF+HF         +CF,
+  (0x63<<8)      +YF+HF   +VF   +CF,
+  (0x64<<8)      +YF+HF         +CF,
+  (0x65<<8)      +YF+HF   +VF   +CF,
+  (0x00<<8)   +ZF         +VF+NF   ,
+  (0x01<<8)                  +NF   ,
+  (0x02<<8)                  +NF   ,
+  (0x03<<8)               +VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x10<<8)                  +NF   ,
+  (0x11<<8)               +VF+NF   ,
+  (0x12<<8)               +VF+NF   ,
+  (0x13<<8)                  +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x20<<8)      +YF         +NF   ,
+  (0x21<<8)      +YF      +VF+NF   ,
+  (0x22<<8)      +YF      +VF+NF   ,
+  (0x23<<8)      +YF         +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x30<<8)      +YF      +VF+NF   ,
+  (0x31<<8)      +YF         +NF   ,
+  (0x32<<8)      +YF         +NF   ,
+  (0x33<<8)      +YF      +VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x40<<8)                  +NF   ,
+  (0x41<<8)               +VF+NF   ,
+  (0x42<<8)               +VF+NF   ,
+  (0x43<<8)                  +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x50<<8)               +VF+NF   ,
+  (0x51<<8)                  +NF   ,
+  (0x52<<8)                  +NF   ,
+  (0x53<<8)               +VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x60<<8)      +YF      +VF+NF   ,
+  (0x61<<8)      +YF         +NF   ,
+  (0x62<<8)      +YF         +NF   ,
+  (0x63<<8)      +YF      +VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x70<<8)      +YF         +NF   ,
+  (0x71<<8)      +YF      +VF+NF   ,
+  (0x72<<8)      +YF      +VF+NF   ,
+  (0x73<<8)      +YF         +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x80<<8)+SF               +NF   ,
+  (0x81<<8)+SF            +VF+NF   ,
+  (0x82<<8)+SF            +VF+NF   ,
+  (0x83<<8)+SF               +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x90<<8)+SF            +VF+NF   ,
+  (0x91<<8)+SF               +NF   ,
+  (0x92<<8)+SF               +NF   ,
+  (0x93<<8)+SF            +VF+NF   ,
+  (0x94<<8)+SF               +NF   ,
+  (0x95<<8)+SF            +VF+NF   ,
+  (0x96<<8)+SF            +VF+NF   ,
+  (0x97<<8)+SF               +NF   ,
+  (0x98<<8)+SF         +XF   +NF   ,
+  (0x99<<8)+SF         +XF+VF+NF   ,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0xA0<<8)+SF   +YF      +VF+NF+CF,
+  (0xA1<<8)+SF   +YF         +NF+CF,
+  (0xA2<<8)+SF   +YF         +NF+CF,
+  (0xA3<<8)+SF   +YF      +VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB0<<8)+SF   +YF         +NF+CF,
+  (0xB1<<8)+SF   +YF      +VF+NF+CF,
+  (0xB2<<8)+SF   +YF      +VF+NF+CF,
+  (0xB3<<8)+SF   +YF         +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xC0<<8)+SF            +VF+NF+CF,
+  (0xC1<<8)+SF               +NF+CF,
+  (0xC2<<8)+SF               +NF+CF,
+  (0xC3<<8)+SF            +VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xD0<<8)+SF               +NF+CF,
+  (0xD1<<8)+SF            +VF+NF+CF,
+  (0xD2<<8)+SF            +VF+NF+CF,
+  (0xD3<<8)+SF               +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xE0<<8)+SF   +YF         +NF+CF,
+  (0xE1<<8)+SF   +YF      +VF+NF+CF,
+  (0xE2<<8)+SF   +YF      +VF+NF+CF,
+  (0xE3<<8)+SF   +YF         +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF0<<8)+SF   +YF      +VF+NF+CF,
+  (0xF1<<8)+SF   +YF         +NF+CF,
+  (0xF2<<8)+SF   +YF         +NF+CF,
+  (0xF3<<8)+SF   +YF      +VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0x00<<8)   +ZF         +VF+NF+CF,
+  (0x01<<8)                  +NF+CF,
+  (0x02<<8)                  +NF+CF,
+  (0x03<<8)               +VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x10<<8)                  +NF+CF,
+  (0x11<<8)               +VF+NF+CF,
+  (0x12<<8)               +VF+NF+CF,
+  (0x13<<8)                  +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x20<<8)      +YF         +NF+CF,
+  (0x21<<8)      +YF      +VF+NF+CF,
+  (0x22<<8)      +YF      +VF+NF+CF,
+  (0x23<<8)      +YF         +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x30<<8)      +YF      +VF+NF+CF,
+  (0x31<<8)      +YF         +NF+CF,
+  (0x32<<8)      +YF         +NF+CF,
+  (0x33<<8)      +YF      +VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0xFA<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0xFB<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFC<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0xFD<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFE<<8)+SF   +YF+HF+XF   +NF   ,
+  (0xFF<<8)+SF   +YF+HF+XF+VF+NF   ,
+  (0x00<<8)   +ZF         +VF+NF   ,
+  (0x01<<8)                  +NF   ,
+  (0x02<<8)                  +NF   ,
+  (0x03<<8)               +VF+NF   ,
+  (0x04<<8)                  +NF   ,
+  (0x05<<8)               +VF+NF   ,
+  (0x06<<8)               +VF+NF   ,
+  (0x07<<8)                  +NF   ,
+  (0x08<<8)            +XF   +NF   ,
+  (0x09<<8)            +XF+VF+NF   ,
+  (0x0A<<8)         +HF+XF+VF+NF   ,
+  (0x0B<<8)         +HF+XF   +NF   ,
+  (0x0C<<8)         +HF+XF+VF+NF   ,
+  (0x0D<<8)         +HF+XF   +NF   ,
+  (0x0E<<8)         +HF+XF   +NF   ,
+  (0x0F<<8)         +HF+XF+VF+NF   ,
+  (0x10<<8)                  +NF   ,
+  (0x11<<8)               +VF+NF   ,
+  (0x12<<8)               +VF+NF   ,
+  (0x13<<8)                  +NF   ,
+  (0x14<<8)               +VF+NF   ,
+  (0x15<<8)                  +NF   ,
+  (0x16<<8)                  +NF   ,
+  (0x17<<8)               +VF+NF   ,
+  (0x18<<8)            +XF+VF+NF   ,
+  (0x19<<8)            +XF   +NF   ,
+  (0x1A<<8)         +HF+XF   +NF   ,
+  (0x1B<<8)         +HF+XF+VF+NF   ,
+  (0x1C<<8)         +HF+XF   +NF   ,
+  (0x1D<<8)         +HF+XF+VF+NF   ,
+  (0x1E<<8)         +HF+XF+VF+NF   ,
+  (0x1F<<8)         +HF+XF   +NF   ,
+  (0x20<<8)      +YF         +NF   ,
+  (0x21<<8)      +YF      +VF+NF   ,
+  (0x22<<8)      +YF      +VF+NF   ,
+  (0x23<<8)      +YF         +NF   ,
+  (0x24<<8)      +YF      +VF+NF   ,
+  (0x25<<8)      +YF         +NF   ,
+  (0x26<<8)      +YF         +NF   ,
+  (0x27<<8)      +YF      +VF+NF   ,
+  (0x28<<8)      +YF   +XF+VF+NF   ,
+  (0x29<<8)      +YF   +XF   +NF   ,
+  (0x2A<<8)      +YF+HF+XF   +NF   ,
+  (0x2B<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2C<<8)      +YF+HF+XF   +NF   ,
+  (0x2D<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2E<<8)      +YF+HF+XF+VF+NF   ,
+  (0x2F<<8)      +YF+HF+XF   +NF   ,
+  (0x30<<8)      +YF      +VF+NF   ,
+  (0x31<<8)      +YF         +NF   ,
+  (0x32<<8)      +YF         +NF   ,
+  (0x33<<8)      +YF      +VF+NF   ,
+  (0x34<<8)      +YF         +NF   ,
+  (0x35<<8)      +YF      +VF+NF   ,
+  (0x36<<8)      +YF      +VF+NF   ,
+  (0x37<<8)      +YF         +NF   ,
+  (0x38<<8)      +YF   +XF   +NF   ,
+  (0x39<<8)      +YF   +XF+VF+NF   ,
+  (0x3A<<8)      +YF+HF+XF+VF+NF   ,
+  (0x3B<<8)      +YF+HF+XF   +NF   ,
+  (0x3C<<8)      +YF+HF+XF+VF+NF   ,
+  (0x3D<<8)      +YF+HF+XF   +NF   ,
+  (0x3E<<8)      +YF+HF+XF   +NF   ,
+  (0x3F<<8)      +YF+HF+XF+VF+NF   ,
+  (0x40<<8)                  +NF   ,
+  (0x41<<8)               +VF+NF   ,
+  (0x42<<8)               +VF+NF   ,
+  (0x43<<8)                  +NF   ,
+  (0x44<<8)               +VF+NF   ,
+  (0x45<<8)                  +NF   ,
+  (0x46<<8)                  +NF   ,
+  (0x47<<8)               +VF+NF   ,
+  (0x48<<8)            +XF+VF+NF   ,
+  (0x49<<8)            +XF   +NF   ,
+  (0x4A<<8)         +HF+XF   +NF   ,
+  (0x4B<<8)         +HF+XF+VF+NF   ,
+  (0x4C<<8)         +HF+XF   +NF   ,
+  (0x4D<<8)         +HF+XF+VF+NF   ,
+  (0x4E<<8)         +HF+XF+VF+NF   ,
+  (0x4F<<8)         +HF+XF   +NF   ,
+  (0x50<<8)               +VF+NF   ,
+  (0x51<<8)                  +NF   ,
+  (0x52<<8)                  +NF   ,
+  (0x53<<8)               +VF+NF   ,
+  (0x54<<8)                  +NF   ,
+  (0x55<<8)               +VF+NF   ,
+  (0x56<<8)               +VF+NF   ,
+  (0x57<<8)                  +NF   ,
+  (0x58<<8)            +XF   +NF   ,
+  (0x59<<8)            +XF+VF+NF   ,
+  (0x5A<<8)         +HF+XF+VF+NF   ,
+  (0x5B<<8)         +HF+XF   +NF   ,
+  (0x5C<<8)         +HF+XF+VF+NF   ,
+  (0x5D<<8)         +HF+XF   +NF   ,
+  (0x5E<<8)         +HF+XF   +NF   ,
+  (0x5F<<8)         +HF+XF+VF+NF   ,
+  (0x60<<8)      +YF      +VF+NF   ,
+  (0x61<<8)      +YF         +NF   ,
+  (0x62<<8)      +YF         +NF   ,
+  (0x63<<8)      +YF      +VF+NF   ,
+  (0x64<<8)      +YF         +NF   ,
+  (0x65<<8)      +YF      +VF+NF   ,
+  (0x66<<8)      +YF      +VF+NF   ,
+  (0x67<<8)      +YF         +NF   ,
+  (0x68<<8)      +YF   +XF   +NF   ,
+  (0x69<<8)      +YF   +XF+VF+NF   ,
+  (0x6A<<8)      +YF+HF+XF+VF+NF   ,
+  (0x6B<<8)      +YF+HF+XF   +NF   ,
+  (0x6C<<8)      +YF+HF+XF+VF+NF   ,
+  (0x6D<<8)      +YF+HF+XF   +NF   ,
+  (0x6E<<8)      +YF+HF+XF   +NF   ,
+  (0x6F<<8)      +YF+HF+XF+VF+NF   ,
+  (0x70<<8)      +YF         +NF   ,
+  (0x71<<8)      +YF      +VF+NF   ,
+  (0x72<<8)      +YF      +VF+NF   ,
+  (0x73<<8)      +YF         +NF   ,
+  (0x74<<8)      +YF      +VF+NF   ,
+  (0x75<<8)      +YF         +NF   ,
+  (0x76<<8)      +YF         +NF   ,
+  (0x77<<8)      +YF      +VF+NF   ,
+  (0x78<<8)      +YF   +XF+VF+NF   ,
+  (0x79<<8)      +YF   +XF   +NF   ,
+  (0x7A<<8)      +YF+HF+XF   +NF   ,
+  (0x7B<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7C<<8)      +YF+HF+XF   +NF   ,
+  (0x7D<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7E<<8)      +YF+HF+XF+VF+NF   ,
+  (0x7F<<8)      +YF+HF+XF   +NF   ,
+  (0x80<<8)+SF               +NF   ,
+  (0x81<<8)+SF            +VF+NF   ,
+  (0x82<<8)+SF            +VF+NF   ,
+  (0x83<<8)+SF               +NF   ,
+  (0x84<<8)+SF            +VF+NF   ,
+  (0x85<<8)+SF               +NF   ,
+  (0x86<<8)+SF               +NF   ,
+  (0x87<<8)+SF            +VF+NF   ,
+  (0x88<<8)+SF         +XF+VF+NF   ,
+  (0x89<<8)+SF         +XF   +NF   ,
+  (0x8A<<8)+SF      +HF+XF   +NF   ,
+  (0x8B<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8C<<8)+SF      +HF+XF   +NF   ,
+  (0x8D<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8E<<8)+SF      +HF+XF+VF+NF   ,
+  (0x8F<<8)+SF      +HF+XF   +NF   ,
+  (0x90<<8)+SF            +VF+NF   ,
+  (0x91<<8)+SF               +NF   ,
+  (0x92<<8)+SF               +NF   ,
+  (0x93<<8)+SF            +VF+NF   ,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x3A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3B<<8)      +YF+HF+XF   +NF+CF,
+  (0x3C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3D<<8)      +YF+HF+XF   +NF+CF,
+  (0x3E<<8)      +YF+HF+XF   +NF+CF,
+  (0x3F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x4A<<8)         +HF+XF   +NF+CF,
+  (0x4B<<8)         +HF+XF+VF+NF+CF,
+  (0x4C<<8)         +HF+XF   +NF+CF,
+  (0x4D<<8)         +HF+XF+VF+NF+CF,
+  (0x4E<<8)         +HF+XF+VF+NF+CF,
+  (0x4F<<8)         +HF+XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x5A<<8)         +HF+XF+VF+NF+CF,
+  (0x5B<<8)         +HF+XF   +NF+CF,
+  (0x5C<<8)         +HF+XF+VF+NF+CF,
+  (0x5D<<8)         +HF+XF   +NF+CF,
+  (0x5E<<8)         +HF+XF   +NF+CF,
+  (0x5F<<8)         +HF+XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x6A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6B<<8)      +YF+HF+XF   +NF+CF,
+  (0x6C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6D<<8)      +YF+HF+XF   +NF+CF,
+  (0x6E<<8)      +YF+HF+XF   +NF+CF,
+  (0x6F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x7A<<8)      +YF+HF+XF   +NF+CF,
+  (0x7B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7C<<8)      +YF+HF+XF   +NF+CF,
+  (0x7D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7F<<8)      +YF+HF+XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x8A<<8)+SF      +HF+XF   +NF+CF,
+  (0x8B<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8C<<8)+SF      +HF+XF   +NF+CF,
+  (0x8D<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8E<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8F<<8)+SF      +HF+XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF,
+  (0x9A<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x9B<<8)+SF      +HF+XF   +NF+CF,
+  (0x9C<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x9D<<8)+SF      +HF+XF   +NF+CF,
+  (0x9E<<8)+SF      +HF+XF   +NF+CF,
+  (0x9F<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xA0<<8)+SF   +YF      +VF+NF+CF,
+  (0xA1<<8)+SF   +YF         +NF+CF,
+  (0xA2<<8)+SF   +YF         +NF+CF,
+  (0xA3<<8)+SF   +YF      +VF+NF+CF,
+  (0xA4<<8)+SF   +YF         +NF+CF,
+  (0xA5<<8)+SF   +YF      +VF+NF+CF,
+  (0xA6<<8)+SF   +YF      +VF+NF+CF,
+  (0xA7<<8)+SF   +YF         +NF+CF,
+  (0xA8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xA9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xAA<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xAB<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAC<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xAD<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAE<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xAF<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xB0<<8)+SF   +YF         +NF+CF,
+  (0xB1<<8)+SF   +YF      +VF+NF+CF,
+  (0xB2<<8)+SF   +YF      +VF+NF+CF,
+  (0xB3<<8)+SF   +YF         +NF+CF,
+  (0xB4<<8)+SF   +YF      +VF+NF+CF,
+  (0xB5<<8)+SF   +YF         +NF+CF,
+  (0xB6<<8)+SF   +YF         +NF+CF,
+  (0xB7<<8)+SF   +YF      +VF+NF+CF,
+  (0xB8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xB9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xBA<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xBB<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBC<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xBD<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBE<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xBF<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xC0<<8)+SF            +VF+NF+CF,
+  (0xC1<<8)+SF               +NF+CF,
+  (0xC2<<8)+SF               +NF+CF,
+  (0xC3<<8)+SF            +VF+NF+CF,
+  (0xC4<<8)+SF               +NF+CF,
+  (0xC5<<8)+SF            +VF+NF+CF,
+  (0xC6<<8)+SF            +VF+NF+CF,
+  (0xC7<<8)+SF               +NF+CF,
+  (0xC8<<8)+SF         +XF   +NF+CF,
+  (0xC9<<8)+SF         +XF+VF+NF+CF,
+  (0xCA<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xCB<<8)+SF      +HF+XF   +NF+CF,
+  (0xCC<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xCD<<8)+SF      +HF+XF   +NF+CF,
+  (0xCE<<8)+SF      +HF+XF   +NF+CF,
+  (0xCF<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xD0<<8)+SF               +NF+CF,
+  (0xD1<<8)+SF            +VF+NF+CF,
+  (0xD2<<8)+SF            +VF+NF+CF,
+  (0xD3<<8)+SF               +NF+CF,
+  (0xD4<<8)+SF            +VF+NF+CF,
+  (0xD5<<8)+SF               +NF+CF,
+  (0xD6<<8)+SF               +NF+CF,
+  (0xD7<<8)+SF            +VF+NF+CF,
+  (0xD8<<8)+SF         +XF+VF+NF+CF,
+  (0xD9<<8)+SF         +XF   +NF+CF,
+  (0xDA<<8)+SF      +HF+XF   +NF+CF,
+  (0xDB<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDC<<8)+SF      +HF+XF   +NF+CF,
+  (0xDD<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDE<<8)+SF      +HF+XF+VF+NF+CF,
+  (0xDF<<8)+SF      +HF+XF   +NF+CF,
+  (0xE0<<8)+SF   +YF         +NF+CF,
+  (0xE1<<8)+SF   +YF      +VF+NF+CF,
+  (0xE2<<8)+SF   +YF      +VF+NF+CF,
+  (0xE3<<8)+SF   +YF         +NF+CF,
+  (0xE4<<8)+SF   +YF      +VF+NF+CF,
+  (0xE5<<8)+SF   +YF         +NF+CF,
+  (0xE6<<8)+SF   +YF         +NF+CF,
+  (0xE7<<8)+SF   +YF      +VF+NF+CF,
+  (0xE8<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xE9<<8)+SF   +YF   +XF   +NF+CF,
+  (0xEA<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xEB<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEC<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xED<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEE<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xEF<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xF0<<8)+SF   +YF      +VF+NF+CF,
+  (0xF1<<8)+SF   +YF         +NF+CF,
+  (0xF2<<8)+SF   +YF         +NF+CF,
+  (0xF3<<8)+SF   +YF      +VF+NF+CF,
+  (0xF4<<8)+SF   +YF         +NF+CF,
+  (0xF5<<8)+SF   +YF      +VF+NF+CF,
+  (0xF6<<8)+SF   +YF      +VF+NF+CF,
+  (0xF7<<8)+SF   +YF         +NF+CF,
+  (0xF8<<8)+SF   +YF   +XF   +NF+CF,
+  (0xF9<<8)+SF   +YF   +XF+VF+NF+CF,
+  (0xFA<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xFB<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFC<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0xFD<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFE<<8)+SF   +YF+HF+XF   +NF+CF,
+  (0xFF<<8)+SF   +YF+HF+XF+VF+NF+CF,
+  (0x00<<8)   +ZF         +VF+NF+CF,
+  (0x01<<8)                  +NF+CF,
+  (0x02<<8)                  +NF+CF,
+  (0x03<<8)               +VF+NF+CF,
+  (0x04<<8)                  +NF+CF,
+  (0x05<<8)               +VF+NF+CF,
+  (0x06<<8)               +VF+NF+CF,
+  (0x07<<8)                  +NF+CF,
+  (0x08<<8)            +XF   +NF+CF,
+  (0x09<<8)            +XF+VF+NF+CF,
+  (0x0A<<8)         +HF+XF+VF+NF+CF,
+  (0x0B<<8)         +HF+XF   +NF+CF,
+  (0x0C<<8)         +HF+XF+VF+NF+CF,
+  (0x0D<<8)         +HF+XF   +NF+CF,
+  (0x0E<<8)         +HF+XF   +NF+CF,
+  (0x0F<<8)         +HF+XF+VF+NF+CF,
+  (0x10<<8)                  +NF+CF,
+  (0x11<<8)               +VF+NF+CF,
+  (0x12<<8)               +VF+NF+CF,
+  (0x13<<8)                  +NF+CF,
+  (0x14<<8)               +VF+NF+CF,
+  (0x15<<8)                  +NF+CF,
+  (0x16<<8)                  +NF+CF,
+  (0x17<<8)               +VF+NF+CF,
+  (0x18<<8)            +XF+VF+NF+CF,
+  (0x19<<8)            +XF   +NF+CF,
+  (0x1A<<8)         +HF+XF   +NF+CF,
+  (0x1B<<8)         +HF+XF+VF+NF+CF,
+  (0x1C<<8)         +HF+XF   +NF+CF,
+  (0x1D<<8)         +HF+XF+VF+NF+CF,
+  (0x1E<<8)         +HF+XF+VF+NF+CF,
+  (0x1F<<8)         +HF+XF   +NF+CF,
+  (0x20<<8)      +YF         +NF+CF,
+  (0x21<<8)      +YF      +VF+NF+CF,
+  (0x22<<8)      +YF      +VF+NF+CF,
+  (0x23<<8)      +YF         +NF+CF,
+  (0x24<<8)      +YF      +VF+NF+CF,
+  (0x25<<8)      +YF         +NF+CF,
+  (0x26<<8)      +YF         +NF+CF,
+  (0x27<<8)      +YF      +VF+NF+CF,
+  (0x28<<8)      +YF   +XF+VF+NF+CF,
+  (0x29<<8)      +YF   +XF   +NF+CF,
+  (0x2A<<8)      +YF+HF+XF   +NF+CF,
+  (0x2B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2C<<8)      +YF+HF+XF   +NF+CF,
+  (0x2D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x2F<<8)      +YF+HF+XF   +NF+CF,
+  (0x30<<8)      +YF      +VF+NF+CF,
+  (0x31<<8)      +YF         +NF+CF,
+  (0x32<<8)      +YF         +NF+CF,
+  (0x33<<8)      +YF      +VF+NF+CF,
+  (0x34<<8)      +YF         +NF+CF,
+  (0x35<<8)      +YF      +VF+NF+CF,
+  (0x36<<8)      +YF      +VF+NF+CF,
+  (0x37<<8)      +YF         +NF+CF,
+  (0x38<<8)      +YF   +XF   +NF+CF,
+  (0x39<<8)      +YF   +XF+VF+NF+CF,
+  (0x3A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3B<<8)      +YF+HF+XF   +NF+CF,
+  (0x3C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x3D<<8)      +YF+HF+XF   +NF+CF,
+  (0x3E<<8)      +YF+HF+XF   +NF+CF,
+  (0x3F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x40<<8)                  +NF+CF,
+  (0x41<<8)               +VF+NF+CF,
+  (0x42<<8)               +VF+NF+CF,
+  (0x43<<8)                  +NF+CF,
+  (0x44<<8)               +VF+NF+CF,
+  (0x45<<8)                  +NF+CF,
+  (0x46<<8)                  +NF+CF,
+  (0x47<<8)               +VF+NF+CF,
+  (0x48<<8)            +XF+VF+NF+CF,
+  (0x49<<8)            +XF   +NF+CF,
+  (0x4A<<8)         +HF+XF   +NF+CF,
+  (0x4B<<8)         +HF+XF+VF+NF+CF,
+  (0x4C<<8)         +HF+XF   +NF+CF,
+  (0x4D<<8)         +HF+XF+VF+NF+CF,
+  (0x4E<<8)         +HF+XF+VF+NF+CF,
+  (0x4F<<8)         +HF+XF   +NF+CF,
+  (0x50<<8)               +VF+NF+CF,
+  (0x51<<8)                  +NF+CF,
+  (0x52<<8)                  +NF+CF,
+  (0x53<<8)               +VF+NF+CF,
+  (0x54<<8)                  +NF+CF,
+  (0x55<<8)               +VF+NF+CF,
+  (0x56<<8)               +VF+NF+CF,
+  (0x57<<8)                  +NF+CF,
+  (0x58<<8)            +XF   +NF+CF,
+  (0x59<<8)            +XF+VF+NF+CF,
+  (0x5A<<8)         +HF+XF+VF+NF+CF,
+  (0x5B<<8)         +HF+XF   +NF+CF,
+  (0x5C<<8)         +HF+XF+VF+NF+CF,
+  (0x5D<<8)         +HF+XF   +NF+CF,
+  (0x5E<<8)         +HF+XF   +NF+CF,
+  (0x5F<<8)         +HF+XF+VF+NF+CF,
+  (0x60<<8)      +YF      +VF+NF+CF,
+  (0x61<<8)      +YF         +NF+CF,
+  (0x62<<8)      +YF         +NF+CF,
+  (0x63<<8)      +YF      +VF+NF+CF,
+  (0x64<<8)      +YF         +NF+CF,
+  (0x65<<8)      +YF      +VF+NF+CF,
+  (0x66<<8)      +YF      +VF+NF+CF,
+  (0x67<<8)      +YF         +NF+CF,
+  (0x68<<8)      +YF   +XF   +NF+CF,
+  (0x69<<8)      +YF   +XF+VF+NF+CF,
+  (0x6A<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6B<<8)      +YF+HF+XF   +NF+CF,
+  (0x6C<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x6D<<8)      +YF+HF+XF   +NF+CF,
+  (0x6E<<8)      +YF+HF+XF   +NF+CF,
+  (0x6F<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x70<<8)      +YF         +NF+CF,
+  (0x71<<8)      +YF      +VF+NF+CF,
+  (0x72<<8)      +YF      +VF+NF+CF,
+  (0x73<<8)      +YF         +NF+CF,
+  (0x74<<8)      +YF      +VF+NF+CF,
+  (0x75<<8)      +YF         +NF+CF,
+  (0x76<<8)      +YF         +NF+CF,
+  (0x77<<8)      +YF      +VF+NF+CF,
+  (0x78<<8)      +YF   +XF+VF+NF+CF,
+  (0x79<<8)      +YF   +XF   +NF+CF,
+  (0x7A<<8)      +YF+HF+XF   +NF+CF,
+  (0x7B<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7C<<8)      +YF+HF+XF   +NF+CF,
+  (0x7D<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7E<<8)      +YF+HF+XF+VF+NF+CF,
+  (0x7F<<8)      +YF+HF+XF   +NF+CF,
+  (0x80<<8)+SF               +NF+CF,
+  (0x81<<8)+SF            +VF+NF+CF,
+  (0x82<<8)+SF            +VF+NF+CF,
+  (0x83<<8)+SF               +NF+CF,
+  (0x84<<8)+SF            +VF+NF+CF,
+  (0x85<<8)+SF               +NF+CF,
+  (0x86<<8)+SF               +NF+CF,
+  (0x87<<8)+SF            +VF+NF+CF,
+  (0x88<<8)+SF         +XF+VF+NF+CF,
+  (0x89<<8)+SF         +XF   +NF+CF,
+  (0x8A<<8)+SF      +HF+XF   +NF+CF,
+  (0x8B<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8C<<8)+SF      +HF+XF   +NF+CF,
+  (0x8D<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8E<<8)+SF      +HF+XF+VF+NF+CF,
+  (0x8F<<8)+SF      +HF+XF   +NF+CF,
+  (0x90<<8)+SF            +VF+NF+CF,
+  (0x91<<8)+SF               +NF+CF,
+  (0x92<<8)+SF               +NF+CF,
+  (0x93<<8)+SF            +VF+NF+CF,
+  (0x94<<8)+SF               +NF+CF,
+  (0x95<<8)+SF            +VF+NF+CF,
+  (0x96<<8)+SF            +VF+NF+CF,
+  (0x97<<8)+SF               +NF+CF,
+  (0x98<<8)+SF         +XF   +NF+CF,
+  (0x99<<8)+SF         +XF+VF+NF+CF
+};
+
diff --git a/MCUME_pico2/picospeccy/AY8910.c b/MCUME_pico2/picospeccy/AY8910.c
new file mode 100644
index 0000000..9c3984b
--- /dev/null
+++ b/MCUME_pico2/picospeccy/AY8910.c
@@ -0,0 +1,315 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.c                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.h for declarations.                              **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2014                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "AY8910.h"
+#include "emuapi.h"
+#include <string.h>
+
+static const unsigned char Envelopes[16][32] =
+{
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
+  { 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 },
+  { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+};
+
+static const int Volumes[16] =
+{ 0,1,2,4,6,8,11,16,23,32,45,64,90,128,180,255 };
+//{ 0,16,33,50,67,84,101,118,135,152,169,186,203,220,237,254 };
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int ClockHz,int First)
+{
+  static byte RegInit[16] =
+  {
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFD,
+    0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00
+  };
+  int J;
+
+  /* Reset state */
+  memcpy(D->R,RegInit,sizeof(D->R));
+  D->EPhase  = 0;
+  D->Clock   = ClockHz>>4;
+  D->First   = First;
+  D->Sync    = AY8910_ASYNC;
+  D->Changed = 0x00;
+  D->EPeriod = 0;
+  D->ECount  = 0;
+  D->Latch   = 0x00;
+
+  /* Set sound types */
+  //SetSound(0+First,SND_MELODIC);
+  //SetSound(1+First,SND_MELODIC);
+  //SetSound(2+First,SND_MELODIC);
+  //SetSound(3+First,SND_NOISE);
+  //SetSound(4+First,SND_NOISE);
+  //SetSound(5+First,SND_NOISE);
+
+  /* Silence all channels */
+  for(J=0;J<AY8910_CHANNELS;J++)
+  {
+    D->Freq[J]=D->Volume[J]=0;
+#if HAS_SND    
+    emu_sndPlaySound(J+First, 0, 0);
+#endif    
+    //Sound(J+First,0,0);
+  }
+}
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V)
+{
+  D->Latch=V&0x0F;
+}
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V)
+{
+  Write8910(D,D->Latch,V);
+}
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D)
+{
+  return(D->R[D->Latch]);
+}
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V)
+{
+  register int J,I;
+
+  switch(R)
+  {
+    case 1:
+    case 3:
+    case 5:
+      V&=0x0F;
+      /* Fall through */
+    case 0:
+    case 2:
+    case 4:
+      /* Write value */
+      D->R[R]=V;
+      /* Exit if the channel is silenced */
+      if(D->R[7]&(1<<(R>>1))) return;
+      /* Go to the first register in the pair */
+      R&=0xFE;
+      /* Compute frequency */
+      J=((int)(D->R[R+1]&0x0F)<<8)+D->R[R];
+      /* Compute channel number */
+      R>>=1;
+      /* Assign frequency */
+      D->Freq[R]=D->Clock/(J? J:0x1000);
+      /* Compute changed channels mask */
+      D->Changed|=1<<R;
+      break;
+
+    case 6:
+      /* Write value */
+      D->R[6]=V&=0x1F;
+      /* Exit if noise channels are silenced */
+      if(!(~D->R[7]&0x38)) return;
+      /* Compute and assign noise frequency */
+      /* Shouldn't do <<2, but need to keep frequency down */
+      J=D->Clock/((V&0x1F? (V&0x1F):0x20)<<2);
+      if(!(D->R[7]&0x08)) D->Freq[3]=J;
+      if(!(D->R[7]&0x10)) D->Freq[4]=J;
+      if(!(D->R[7]&0x20)) D->Freq[5]=J;
+      /* Compute changed channels mask */
+      D->Changed|=0x38&~D->R[7];
+      break;
+
+    case 7:
+      /* Find changed channels */
+      R=(V^D->R[7])&0x3F;
+      D->Changed|=R;
+      /* Write value */
+      D->R[7]=V;
+      /* Update frequencies */
+      for(J=0;R&&(J<AY8910_CHANNELS);J++,R>>=1,V>>=1)
+        if(R&1)
+        {
+          if(V&1) D->Freq[J]=0;
+          else if(J<3)
+          {
+            I=((int)(D->R[J*2+1]&0x0F)<<8)+D->R[J*2];
+            D->Freq[J]=D->Clock/(I? I:0x1000);
+          }
+          else
+          {
+            /* Shouldn't do <<2, but need to keep frequency down */
+            I=D->R[6]&0x1F;
+            D->Freq[J]=D->Clock/((I? I:0x20)<<2);
+          }
+        }
+      break;
+      
+    case 8:
+    case 9:
+    case 10:
+      /* Write value */
+      D->R[R]=V&=0x1F;
+      /* Compute channel number */
+      R-=8;
+      /* Compute and assign new volume */
+      J=Volumes[V&0x10? Envelopes[D->R[13]&0x0F][D->EPhase]:(V&0x0F)];
+      D->Volume[R]=J;
+      D->Volume[R+3]=(J+1)>>1;
+      /* Compute changed channels mask */
+      D->Changed|=(0x09<<R)&~D->R[7];
+      break;
+
+    case 11:
+    case 12:
+      /* Write value */
+      D->R[R]=V;
+      /* Compute envelope period (why not <<4?) */
+      J=((int)D->R[12]<<8)+D->R[11];
+      D->EPeriod=1000*(J? J:0x10000)/D->Clock;
+      /* No channels changed */
+      return;
+
+    case 13:
+      /* Write value */
+      D->R[R]=V&=0x0F;
+      /* Reset envelope */
+      D->ECount = 0;
+      D->EPhase = 0;
+      for(J=0;J<AY8910_CHANNELS/2;++J)
+        if(D->R[J+8]&0x10)
+        {
+          I = Volumes[Envelopes[V][0]];
+          D->Volume[J]   = I;
+          D->Volume[J+3] = (I+1)>>1;
+          D->Changed    |= (0x09<<J)&~D->R[7];
+        }
+      break;
+
+    case 14:
+    case 15:
+      /* Write value */
+      D->R[R]=V;
+      /* No channels changed */
+      return;
+
+    default:
+      /* Wrong register, do nothing */
+      return;
+  }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS)
+{
+  register int J,I;
+
+  /* Exit if no envelope running */
+  if(!D->EPeriod) return;
+
+  /* Count milliseconds */
+  D->ECount += mS;
+  if(D->ECount<D->EPeriod) return;
+
+  /* Count steps */
+  J = D->ECount/D->EPeriod;
+  D->ECount -= J*D->EPeriod;
+
+  /* Count phases */
+  D->EPhase += J;
+  if(D->EPhase>31)
+    D->EPhase = (D->R[13]&0x09)==0x08? (D->EPhase&0x1F):31;
+
+  /* Set envelope volumes for relevant channels */
+  for(I=0;I<3;++I)
+    if(D->R[I+8]&0x10)
+    {
+      J = Volumes[Envelopes[D->R[13]&0x0F][D->EPhase]];
+      D->Volume[I]   = J;
+      D->Volume[I+3] = (J+1)>>1;
+      D->Changed    |= (0x09<<I)&~D->R[7];
+    }
+
+  /* For asynchronous mode, make Sound() calls right away */
+  if(!D->Sync&&D->Changed) Sync8910(D,AY8910_FLUSH);
+}
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync)
+{
+  register int J,I;
+
+  /* Hit MIDI drums for noise channels, if requested */
+  if(Sync&AY8910_DRUMS)
+  {
+    Sync&=~AY8910_DRUMS;
+    J = (D->Freq[3]? D->Volume[3]:0)
+      + (D->Freq[4]? D->Volume[4]:0)
+      + (D->Freq[5]? D->Volume[5]:0);
+    if(J) {
+      //Drum(DRM_MIDI|28,(J+2)/3);
+    }
+  }
+
+  if(Sync!=AY8910_FLUSH) D->Sync=Sync;
+
+  for(J=0,I=D->Changed;I&&(J<AY8910_CHANNELS);J++,I>>=1)
+    if(I&1) {
+#if HAS_SND      
+      emu_sndPlaySound(J+D->First, D->Volume[J], D->Freq[J]);
+#endif      
+      //Sound(J+D->First,D->Freq[J],D->Volume[J]);
+    }
+
+  D->Changed=0x00;
+}
diff --git a/MCUME_pico2/picospeccy/AY8910.h b/MCUME_pico2/picospeccy/AY8910.h
new file mode 100755
index 0000000..b833cc6
--- /dev/null
+++ b/MCUME_pico2/picospeccy/AY8910.h
@@ -0,0 +1,97 @@
+/** EMULib Emulation Library *********************************/
+/**                                                         **/
+/**                         AY8910.h                        **/
+/**                                                         **/
+/** This file contains emulation for the AY8910 sound chip  **/
+/** produced by General Instruments, Yamaha, etc. See       **/
+/** AY8910.c for the actual code.                           **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1996-2014                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef AY8910_H
+#define AY8910_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AY8910_CHANNELS 6      /* 3 melodic + 3 noise chanls */
+
+#define AY8910_ASYNC    0      /* Asynchronous emulation     */
+#define AY8910_SYNC     1      /* Synchronous emulation      */
+#define AY8910_FLUSH    2      /* Flush buffers only         */
+#define AY8910_DRUMS    0x80   /* Hit drums for noise chnls  */
+
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef unsigned char byte;
+#endif
+
+/** AY8910 ***************************************************/
+/** This data structure stores AY8910 state.                **/
+/*************************************************************/
+typedef struct
+{
+  byte R[16];                  /* PSG registers contents     */
+  int Freq[AY8910_CHANNELS];   /* Frequencies (0 for off)    */
+  int Volume[AY8910_CHANNELS]; /* Volumes (0..255)           */
+  int Clock;                   /* Base clock used by PSG     */
+  int First;                   /* First used Sound() channel */
+  byte Changed;                /* Bitmap of changed channels */
+  byte Sync;                   /* AY8910_SYNC/AY8910_ASYNC   */
+  byte Latch;                  /* Latch for the register num */
+  int EPeriod;                 /* Envelope step in msecs     */
+  int ECount;                  /* Envelope step counter      */
+  int EPhase;                  /* Envelope phase             */
+} AY8910;
+
+/** Reset8910() **********************************************/
+/** Reset the sound chip and use sound channels from the    **/
+/** one given in First.                                     **/
+/*************************************************************/
+void Reset8910(register AY8910 *D,int ClockHz,int First);
+
+/** Write8910() **********************************************/
+/** Call this function to output a value V into the sound   **/
+/** chip.                                                   **/
+/*************************************************************/
+void Write8910(register AY8910 *D,register byte R,register byte V);
+
+/** WrCtrl8910() *********************************************/
+/** Write a value V to the PSG Control Port.                **/
+/*************************************************************/
+void WrCtrl8910(AY8910 *D,byte V);
+
+/** WrData8910() *********************************************/
+/** Write a value V to the PSG Data Port.                   **/
+/*************************************************************/
+void WrData8910(AY8910 *D,byte V);
+
+/** RdData8910() *********************************************/
+/** Read a value from the PSG Data Port.                    **/
+/*************************************************************/
+byte RdData8910(AY8910 *D);
+
+/** Sync8910() ***********************************************/
+/** Flush all accumulated changes by issuing Sound() calls  **/
+/** and set the synchronization on/off. The second argument **/
+/** should be AY8910_SYNC/AY8910_ASYNC to set/reset sync,   **/
+/** or AY8910_FLUSH to leave sync mode as it is. To emulate **/
+/** noise channels with MIDI drums, OR second argument with **/
+/** AY8910_DRUMS.                                           **/
+/*************************************************************/
+void Sync8910(register AY8910 *D,register byte Sync);
+
+/** Loop8910() ***********************************************/
+/** Call this function periodically to update volume        **/
+/** envelopes. Use mS to pass the time since the last call  **/
+/** of Loop8910() in milliseconds.                          **/
+/*************************************************************/
+void Loop8910(register AY8910 *D,int mS);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* AY8910_H */
diff --git a/MCUME_pico2/picospeccy/Codes.h b/MCUME_pico2/picospeccy/Codes.h
new file mode 100755
index 0000000..2dcee81
--- /dev/null
+++ b/MCUME_pico2/picospeccy/Codes.h
@@ -0,0 +1,385 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Codes.h                        **/
+/**                                                         **/
+/** This file contains implementation for the main table of **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->HL.B.h);break;
+case ADD_L:    M_ADD(R->HL.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->HL.W);M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->HL.B.h);break;
+case SUB_L:    M_SUB(R->HL.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->HL.W);M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->HL.B.h);break;
+case AND_L:    M_AND(R->HL.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->HL.W);M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->HL.B.h);break;
+case OR_L:     M_OR(R->HL.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->HL.W);M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->HL.B.h);break;
+case ADC_L:    M_ADC(R->HL.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->HL.W);M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->HL.B.h);break;
+case SBC_L:    M_SBC(R->HL.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->HL.W);M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->HL.B.h);break;
+case XOR_L:    M_XOR(R->HL.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->HL.W);M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->HL.B.h);break;
+case CP_L:     M_CP(R->HL.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->HL.W);M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(HL);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->HL.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->HL.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(HL,BC);break;
+case ADD_HL_DE:  M_ADDW(HL,DE);break;
+case ADD_HL_HL:  M_ADDW(HL,HL);break;
+case ADD_HL_SP:  M_ADDW(HL,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->HL.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->HL.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->HL.B.h);break;
+case DEC_L:    M_DEC(R->HL.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->HL.W);M_DEC(I);WrZ80(R->HL.W,I);break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->HL.B.h);break;
+case INC_L:    M_INC(R->HL.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->HL.W);M_INC(I);WrZ80(R->HL.W,I);break;
+
+case RLCA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=R->AF.B.h&0x80? C_FLAG:0;
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I; 
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(HL);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(HL);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->HL.B.h=R->BC.B.h;break;
+case LD_L_B:   R->HL.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: WrZ80(R->HL.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->HL.B.h=R->BC.B.l;break;
+case LD_L_C:   R->HL.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: WrZ80(R->HL.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->HL.B.h=R->DE.B.h;break;
+case LD_L_D:   R->HL.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: WrZ80(R->HL.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->HL.B.h=R->DE.B.l;break;
+case LD_L_E:   R->HL.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: WrZ80(R->HL.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->HL.B.h;break;
+case LD_C_H:   R->BC.B.l=R->HL.B.h;break;
+case LD_D_H:   R->DE.B.h=R->HL.B.h;break;
+case LD_E_H:   R->DE.B.l=R->HL.B.h;break;
+case LD_H_H:   R->HL.B.h=R->HL.B.h;break;
+case LD_L_H:   R->HL.B.l=R->HL.B.h;break;
+case LD_A_H:   R->AF.B.h=R->HL.B.h;break;
+case LD_xHL_H: WrZ80(R->HL.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->HL.B.l;break;
+case LD_C_L:   R->BC.B.l=R->HL.B.l;break;
+case LD_D_L:   R->DE.B.h=R->HL.B.l;break;
+case LD_E_L:   R->DE.B.l=R->HL.B.l;break;
+case LD_H_L:   R->HL.B.h=R->HL.B.l;break;
+case LD_L_L:   R->HL.B.l=R->HL.B.l;break;
+case LD_A_L:   R->AF.B.h=R->HL.B.l;break;
+case LD_xHL_L: WrZ80(R->HL.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->HL.B.h=R->AF.B.h;break;
+case LD_L_A:   R->HL.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: WrZ80(R->HL.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->HL.W);break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->HL.W);break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->HL.W);break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->HL.W);break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->HL.W);break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->HL.W);break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->HL.W);break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->HL.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->HL.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: WrZ80(R->HL.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++); 
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->HL.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->HL.B.h);
+  R->HL.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
+
+default:
+  if(R->TrapBadOps)
+    printf
+    (
+      "[Z80 %lX] Unrecognized instruction: %02X at PC=%04X\n",
+      (long)R->User,OpZ80(R->PC.W-1),R->PC.W-1
+    );
+  break;
diff --git a/MCUME_pico2/picospeccy/CodesCB.h b/MCUME_pico2/picospeccy/CodesCB.h
new file mode 100755
index 0000000..15fcb4f
--- /dev/null
+++ b/MCUME_pico2/picospeccy/CodesCB.h
@@ -0,0 +1,204 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesCB.h                       **/
+/**                                                         **/
+/** This file contains implementation for the CB table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_B: M_RLC(R->BC.B.h);break;  case RLC_C: M_RLC(R->BC.B.l);break;
+case RLC_D: M_RLC(R->DE.B.h);break;  case RLC_E: M_RLC(R->DE.B.l);break;
+case RLC_H: M_RLC(R->HL.B.h);break;  case RLC_L: M_RLC(R->HL.B.l);break;
+case RLC_xHL: I=RdZ80(R->HL.W);M_RLC(I);WrZ80(R->HL.W,I);break;
+case RLC_A: M_RLC(R->AF.B.h);break;
+
+case RRC_B: M_RRC(R->BC.B.h);break;  case RRC_C: M_RRC(R->BC.B.l);break;
+case RRC_D: M_RRC(R->DE.B.h);break;  case RRC_E: M_RRC(R->DE.B.l);break;
+case RRC_H: M_RRC(R->HL.B.h);break;  case RRC_L: M_RRC(R->HL.B.l);break;
+case RRC_xHL: I=RdZ80(R->HL.W);M_RRC(I);WrZ80(R->HL.W,I);break;
+case RRC_A: M_RRC(R->AF.B.h);break;
+
+case RL_B: M_RL(R->BC.B.h);break;  case RL_C: M_RL(R->BC.B.l);break;
+case RL_D: M_RL(R->DE.B.h);break;  case RL_E: M_RL(R->DE.B.l);break;
+case RL_H: M_RL(R->HL.B.h);break;  case RL_L: M_RL(R->HL.B.l);break;
+case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
+case RL_A: M_RL(R->AF.B.h);break;
+
+case RR_B: M_RR(R->BC.B.h);break;  case RR_C: M_RR(R->BC.B.l);break;
+case RR_D: M_RR(R->DE.B.h);break;  case RR_E: M_RR(R->DE.B.l);break;
+case RR_H: M_RR(R->HL.B.h);break;  case RR_L: M_RR(R->HL.B.l);break;
+case RR_xHL: I=RdZ80(R->HL.W);M_RR(I);WrZ80(R->HL.W,I);break;
+case RR_A: M_RR(R->AF.B.h);break;
+
+case SLA_B: M_SLA(R->BC.B.h);break;  case SLA_C: M_SLA(R->BC.B.l);break;
+case SLA_D: M_SLA(R->DE.B.h);break;  case SLA_E: M_SLA(R->DE.B.l);break;
+case SLA_H: M_SLA(R->HL.B.h);break;  case SLA_L: M_SLA(R->HL.B.l);break;
+case SLA_xHL: I=RdZ80(R->HL.W);M_SLA(I);WrZ80(R->HL.W,I);break;
+case SLA_A: M_SLA(R->AF.B.h);break;
+
+case SRA_B: M_SRA(R->BC.B.h);break;  case SRA_C: M_SRA(R->BC.B.l);break;
+case SRA_D: M_SRA(R->DE.B.h);break;  case SRA_E: M_SRA(R->DE.B.l);break;
+case SRA_H: M_SRA(R->HL.B.h);break;  case SRA_L: M_SRA(R->HL.B.l);break;
+case SRA_xHL: I=RdZ80(R->HL.W);M_SRA(I);WrZ80(R->HL.W,I);break;
+case SRA_A: M_SRA(R->AF.B.h);break;
+
+case SLL_B: M_SLL(R->BC.B.h);break;  case SLL_C: M_SLL(R->BC.B.l);break;
+case SLL_D: M_SLL(R->DE.B.h);break;  case SLL_E: M_SLL(R->DE.B.l);break;
+case SLL_H: M_SLL(R->HL.B.h);break;  case SLL_L: M_SLL(R->HL.B.l);break;
+case SLL_xHL: I=RdZ80(R->HL.W);M_SLL(I);WrZ80(R->HL.W,I);break;
+case SLL_A: M_SLL(R->AF.B.h);break;
+
+case SRL_B: M_SRL(R->BC.B.h);break;  case SRL_C: M_SRL(R->BC.B.l);break;
+case SRL_D: M_SRL(R->DE.B.h);break;  case SRL_E: M_SRL(R->DE.B.l);break;
+case SRL_H: M_SRL(R->HL.B.h);break;  case SRL_L: M_SRL(R->HL.B.l);break;
+case SRL_xHL: I=RdZ80(R->HL.W);M_SRL(I);WrZ80(R->HL.W,I);break;
+case SRL_A: M_SRL(R->AF.B.h);break;
+    
+case BIT0_B: M_BIT(0,R->BC.B.h);break;  case BIT0_C: M_BIT(0,R->BC.B.l);break;
+case BIT0_D: M_BIT(0,R->DE.B.h);break;  case BIT0_E: M_BIT(0,R->DE.B.l);break;
+case BIT0_H: M_BIT(0,R->HL.B.h);break;  case BIT0_L: M_BIT(0,R->HL.B.l);break;
+case BIT0_xHL: I=RdZ80(R->HL.W);M_BIT(0,I);break;
+case BIT0_A: M_BIT(0,R->AF.B.h);break;
+
+case BIT1_B: M_BIT(1,R->BC.B.h);break;  case BIT1_C: M_BIT(1,R->BC.B.l);break;
+case BIT1_D: M_BIT(1,R->DE.B.h);break;  case BIT1_E: M_BIT(1,R->DE.B.l);break;
+case BIT1_H: M_BIT(1,R->HL.B.h);break;  case BIT1_L: M_BIT(1,R->HL.B.l);break;
+case BIT1_xHL: I=RdZ80(R->HL.W);M_BIT(1,I);break;
+case BIT1_A: M_BIT(1,R->AF.B.h);break;
+
+case BIT2_B: M_BIT(2,R->BC.B.h);break;  case BIT2_C: M_BIT(2,R->BC.B.l);break;
+case BIT2_D: M_BIT(2,R->DE.B.h);break;  case BIT2_E: M_BIT(2,R->DE.B.l);break;
+case BIT2_H: M_BIT(2,R->HL.B.h);break;  case BIT2_L: M_BIT(2,R->HL.B.l);break;
+case BIT2_xHL: I=RdZ80(R->HL.W);M_BIT(2,I);break;
+case BIT2_A: M_BIT(2,R->AF.B.h);break;
+
+case BIT3_B: M_BIT(3,R->BC.B.h);break;  case BIT3_C: M_BIT(3,R->BC.B.l);break;
+case BIT3_D: M_BIT(3,R->DE.B.h);break;  case BIT3_E: M_BIT(3,R->DE.B.l);break;
+case BIT3_H: M_BIT(3,R->HL.B.h);break;  case BIT3_L: M_BIT(3,R->HL.B.l);break;
+case BIT3_xHL: I=RdZ80(R->HL.W);M_BIT(3,I);break;
+case BIT3_A: M_BIT(3,R->AF.B.h);break;
+
+case BIT4_B: M_BIT(4,R->BC.B.h);break;  case BIT4_C: M_BIT(4,R->BC.B.l);break;
+case BIT4_D: M_BIT(4,R->DE.B.h);break;  case BIT4_E: M_BIT(4,R->DE.B.l);break;
+case BIT4_H: M_BIT(4,R->HL.B.h);break;  case BIT4_L: M_BIT(4,R->HL.B.l);break;
+case BIT4_xHL: I=RdZ80(R->HL.W);M_BIT(4,I);break;
+case BIT4_A: M_BIT(4,R->AF.B.h);break;
+
+case BIT5_B: M_BIT(5,R->BC.B.h);break;  case BIT5_C: M_BIT(5,R->BC.B.l);break;
+case BIT5_D: M_BIT(5,R->DE.B.h);break;  case BIT5_E: M_BIT(5,R->DE.B.l);break;
+case BIT5_H: M_BIT(5,R->HL.B.h);break;  case BIT5_L: M_BIT(5,R->HL.B.l);break;
+case BIT5_xHL: I=RdZ80(R->HL.W);M_BIT(5,I);break;
+case BIT5_A: M_BIT(5,R->AF.B.h);break;
+
+case BIT6_B: M_BIT(6,R->BC.B.h);break;  case BIT6_C: M_BIT(6,R->BC.B.l);break;
+case BIT6_D: M_BIT(6,R->DE.B.h);break;  case BIT6_E: M_BIT(6,R->DE.B.l);break;
+case BIT6_H: M_BIT(6,R->HL.B.h);break;  case BIT6_L: M_BIT(6,R->HL.B.l);break;
+case BIT6_xHL: I=RdZ80(R->HL.W);M_BIT(6,I);break;
+case BIT6_A: M_BIT(6,R->AF.B.h);break;
+
+case BIT7_B: M_BIT(7,R->BC.B.h);break;  case BIT7_C: M_BIT(7,R->BC.B.l);break;
+case BIT7_D: M_BIT(7,R->DE.B.h);break;  case BIT7_E: M_BIT(7,R->DE.B.l);break;
+case BIT7_H: M_BIT(7,R->HL.B.h);break;  case BIT7_L: M_BIT(7,R->HL.B.l);break;
+case BIT7_xHL: I=RdZ80(R->HL.W);M_BIT(7,I);break;
+case BIT7_A: M_BIT(7,R->AF.B.h);break;
+
+case RES0_B: M_RES(0,R->BC.B.h);break;  case RES0_C: M_RES(0,R->BC.B.l);break;
+case RES0_D: M_RES(0,R->DE.B.h);break;  case RES0_E: M_RES(0,R->DE.B.l);break;
+case RES0_H: M_RES(0,R->HL.B.h);break;  case RES0_L: M_RES(0,R->HL.B.l);break;
+case RES0_xHL: I=RdZ80(R->HL.W);M_RES(0,I);WrZ80(R->HL.W,I);break;
+case RES0_A: M_RES(0,R->AF.B.h);break;
+
+case RES1_B: M_RES(1,R->BC.B.h);break;  case RES1_C: M_RES(1,R->BC.B.l);break;
+case RES1_D: M_RES(1,R->DE.B.h);break;  case RES1_E: M_RES(1,R->DE.B.l);break;
+case RES1_H: M_RES(1,R->HL.B.h);break;  case RES1_L: M_RES(1,R->HL.B.l);break;
+case RES1_xHL: I=RdZ80(R->HL.W);M_RES(1,I);WrZ80(R->HL.W,I);break;
+case RES1_A: M_RES(1,R->AF.B.h);break;
+
+case RES2_B: M_RES(2,R->BC.B.h);break;  case RES2_C: M_RES(2,R->BC.B.l);break;
+case RES2_D: M_RES(2,R->DE.B.h);break;  case RES2_E: M_RES(2,R->DE.B.l);break;
+case RES2_H: M_RES(2,R->HL.B.h);break;  case RES2_L: M_RES(2,R->HL.B.l);break;
+case RES2_xHL: I=RdZ80(R->HL.W);M_RES(2,I);WrZ80(R->HL.W,I);break;
+case RES2_A: M_RES(2,R->AF.B.h);break;
+
+case RES3_B: M_RES(3,R->BC.B.h);break;  case RES3_C: M_RES(3,R->BC.B.l);break;
+case RES3_D: M_RES(3,R->DE.B.h);break;  case RES3_E: M_RES(3,R->DE.B.l);break;
+case RES3_H: M_RES(3,R->HL.B.h);break;  case RES3_L: M_RES(3,R->HL.B.l);break;
+case RES3_xHL: I=RdZ80(R->HL.W);M_RES(3,I);WrZ80(R->HL.W,I);break;
+case RES3_A: M_RES(3,R->AF.B.h);break;
+
+case RES4_B: M_RES(4,R->BC.B.h);break;  case RES4_C: M_RES(4,R->BC.B.l);break;
+case RES4_D: M_RES(4,R->DE.B.h);break;  case RES4_E: M_RES(4,R->DE.B.l);break;
+case RES4_H: M_RES(4,R->HL.B.h);break;  case RES4_L: M_RES(4,R->HL.B.l);break;
+case RES4_xHL: I=RdZ80(R->HL.W);M_RES(4,I);WrZ80(R->HL.W,I);break;
+case RES4_A: M_RES(4,R->AF.B.h);break;
+
+case RES5_B: M_RES(5,R->BC.B.h);break;  case RES5_C: M_RES(5,R->BC.B.l);break;
+case RES5_D: M_RES(5,R->DE.B.h);break;  case RES5_E: M_RES(5,R->DE.B.l);break;
+case RES5_H: M_RES(5,R->HL.B.h);break;  case RES5_L: M_RES(5,R->HL.B.l);break;
+case RES5_xHL: I=RdZ80(R->HL.W);M_RES(5,I);WrZ80(R->HL.W,I);break;
+case RES5_A: M_RES(5,R->AF.B.h);break;
+
+case RES6_B: M_RES(6,R->BC.B.h);break;  case RES6_C: M_RES(6,R->BC.B.l);break;
+case RES6_D: M_RES(6,R->DE.B.h);break;  case RES6_E: M_RES(6,R->DE.B.l);break;
+case RES6_H: M_RES(6,R->HL.B.h);break;  case RES6_L: M_RES(6,R->HL.B.l);break;
+case RES6_xHL: I=RdZ80(R->HL.W);M_RES(6,I);WrZ80(R->HL.W,I);break;
+case RES6_A: M_RES(6,R->AF.B.h);break;
+
+case RES7_B: M_RES(7,R->BC.B.h);break;  case RES7_C: M_RES(7,R->BC.B.l);break;
+case RES7_D: M_RES(7,R->DE.B.h);break;  case RES7_E: M_RES(7,R->DE.B.l);break;
+case RES7_H: M_RES(7,R->HL.B.h);break;  case RES7_L: M_RES(7,R->HL.B.l);break;
+case RES7_xHL: I=RdZ80(R->HL.W);M_RES(7,I);WrZ80(R->HL.W,I);break;
+case RES7_A: M_RES(7,R->AF.B.h);break;
+
+case SET0_B: M_SET(0,R->BC.B.h);break;  case SET0_C: M_SET(0,R->BC.B.l);break;
+case SET0_D: M_SET(0,R->DE.B.h);break;  case SET0_E: M_SET(0,R->DE.B.l);break;
+case SET0_H: M_SET(0,R->HL.B.h);break;  case SET0_L: M_SET(0,R->HL.B.l);break;
+case SET0_xHL: I=RdZ80(R->HL.W);M_SET(0,I);WrZ80(R->HL.W,I);break;
+case SET0_A: M_SET(0,R->AF.B.h);break;
+
+case SET1_B: M_SET(1,R->BC.B.h);break;  case SET1_C: M_SET(1,R->BC.B.l);break;
+case SET1_D: M_SET(1,R->DE.B.h);break;  case SET1_E: M_SET(1,R->DE.B.l);break;
+case SET1_H: M_SET(1,R->HL.B.h);break;  case SET1_L: M_SET(1,R->HL.B.l);break;
+case SET1_xHL: I=RdZ80(R->HL.W);M_SET(1,I);WrZ80(R->HL.W,I);break;
+case SET1_A: M_SET(1,R->AF.B.h);break;
+
+case SET2_B: M_SET(2,R->BC.B.h);break;  case SET2_C: M_SET(2,R->BC.B.l);break;
+case SET2_D: M_SET(2,R->DE.B.h);break;  case SET2_E: M_SET(2,R->DE.B.l);break;
+case SET2_H: M_SET(2,R->HL.B.h);break;  case SET2_L: M_SET(2,R->HL.B.l);break;
+case SET2_xHL: I=RdZ80(R->HL.W);M_SET(2,I);WrZ80(R->HL.W,I);break;
+case SET2_A: M_SET(2,R->AF.B.h);break;
+
+case SET3_B: M_SET(3,R->BC.B.h);break;  case SET3_C: M_SET(3,R->BC.B.l);break;
+case SET3_D: M_SET(3,R->DE.B.h);break;  case SET3_E: M_SET(3,R->DE.B.l);break;
+case SET3_H: M_SET(3,R->HL.B.h);break;  case SET3_L: M_SET(3,R->HL.B.l);break;
+case SET3_xHL: I=RdZ80(R->HL.W);M_SET(3,I);WrZ80(R->HL.W,I);break;
+case SET3_A: M_SET(3,R->AF.B.h);break;
+
+case SET4_B: M_SET(4,R->BC.B.h);break;  case SET4_C: M_SET(4,R->BC.B.l);break;
+case SET4_D: M_SET(4,R->DE.B.h);break;  case SET4_E: M_SET(4,R->DE.B.l);break;
+case SET4_H: M_SET(4,R->HL.B.h);break;  case SET4_L: M_SET(4,R->HL.B.l);break;
+case SET4_xHL: I=RdZ80(R->HL.W);M_SET(4,I);WrZ80(R->HL.W,I);break;
+case SET4_A: M_SET(4,R->AF.B.h);break;
+
+case SET5_B: M_SET(5,R->BC.B.h);break;  case SET5_C: M_SET(5,R->BC.B.l);break;
+case SET5_D: M_SET(5,R->DE.B.h);break;  case SET5_E: M_SET(5,R->DE.B.l);break;
+case SET5_H: M_SET(5,R->HL.B.h);break;  case SET5_L: M_SET(5,R->HL.B.l);break;
+case SET5_xHL: I=RdZ80(R->HL.W);M_SET(5,I);WrZ80(R->HL.W,I);break;
+case SET5_A: M_SET(5,R->AF.B.h);break;
+
+case SET6_B: M_SET(6,R->BC.B.h);break;  case SET6_C: M_SET(6,R->BC.B.l);break;
+case SET6_D: M_SET(6,R->DE.B.h);break;  case SET6_E: M_SET(6,R->DE.B.l);break;
+case SET6_H: M_SET(6,R->HL.B.h);break;  case SET6_L: M_SET(6,R->HL.B.l);break;
+case SET6_xHL: I=RdZ80(R->HL.W);M_SET(6,I);WrZ80(R->HL.W,I);break;
+case SET6_A: M_SET(6,R->AF.B.h);break;
+
+case SET7_B: M_SET(7,R->BC.B.h);break;  case SET7_C: M_SET(7,R->BC.B.l);break;
+case SET7_D: M_SET(7,R->DE.B.h);break;  case SET7_E: M_SET(7,R->DE.B.l);break;
+case SET7_H: M_SET(7,R->HL.B.h);break;  case SET7_L: M_SET(7,R->HL.B.l);break;
+case SET7_xHL: I=RdZ80(R->HL.W);M_SET(7,I);WrZ80(R->HL.W,I);break;
+case SET7_A: M_SET(7,R->AF.B.h);break;
diff --git a/MCUME_pico2/picospeccy/CodesED.h b/MCUME_pico2/picospeccy/CodesED.h
new file mode 100755
index 0000000..e6deae5
--- /dev/null
+++ b/MCUME_pico2/picospeccy/CodesED.h
@@ -0,0 +1,304 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesED.h                       **/
+/**                                                         **/
+/** This file contains implementation for the ED table of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+/** This is a special patch for emulating BIOS calls: ********/
+case DB_FE:     PatchZ80(R);break;
+/*************************************************************/
+
+case ADC_HL_BC: M_ADCW(BC);break;
+case ADC_HL_DE: M_ADCW(DE);break;
+case ADC_HL_HL: M_ADCW(HL);break;
+case ADC_HL_SP: M_ADCW(SP);break;
+
+case SBC_HL_BC: M_SBCW(BC);break;
+case SBC_HL_DE: M_SBCW(DE);break;
+case SBC_HL_HL: M_SBCW(HL);break;
+case SBC_HL_SP: M_SBCW(SP);break;
+
+case LD_xWORDe_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->HL.B.l);
+  WrZ80(J.W,R->HL.B.h);
+  break;
+case LD_xWORDe_DE:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->DE.B.l);
+  WrZ80(J.W,R->DE.B.h);
+  break;
+case LD_xWORDe_BC:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->BC.B.l);
+  WrZ80(J.W,R->BC.B.h);
+  break;
+case LD_xWORDe_SP:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->SP.B.l);
+  WrZ80(J.W,R->SP.B.h);
+  break;
+
+case LD_HL_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->HL.B.l=RdZ80(J.W++);
+  R->HL.B.h=RdZ80(J.W);
+  break;
+case LD_DE_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->DE.B.l=RdZ80(J.W++);
+  R->DE.B.h=RdZ80(J.W);
+  break;
+case LD_BC_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->BC.B.l=RdZ80(J.W++);
+  R->BC.B.h=RdZ80(J.W);
+  break;
+case LD_SP_xWORDe:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->SP.B.l=RdZ80(J.W++);
+  R->SP.B.h=RdZ80(J.W);
+  break;
+
+case RRD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I>>4)|(R->AF.B.h<<4);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I&0x0F)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+case RLD:
+  I=RdZ80(R->HL.W);
+  J.B.l=(I<<4)|(R->AF.B.h&0x0F);
+  WrZ80(R->HL.W,J.B.l);
+  R->AF.B.h=(I>>4)|(R->AF.B.h&0xF0);
+  R->AF.B.l=PZSTable[R->AF.B.h]|(R->AF.B.l&C_FLAG);
+  break;
+
+case LD_A_I:
+  R->AF.B.h=R->I;
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_A_R:
+  R->R++;
+  R->AF.B.h=(byte)(R->R-R->ICount);
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|(R->IFF&IFF_2? P_FLAG:0)|ZSTable[R->AF.B.h];
+  break;
+
+case LD_I_A:   R->I=R->AF.B.h;break;
+case LD_R_A:   break;
+
+case IM_0:     R->IFF&=~(IFF_IM1|IFF_IM2);break;
+case IM_1:     R->IFF=(R->IFF&~IFF_IM2)|IFF_IM1;break;
+case IM_2:     R->IFF=(R->IFF&~IFF_IM1)|IFF_IM2;break;
+
+case RETI:
+case RETN:     if(R->IFF&IFF_2) R->IFF|=IFF_1; else R->IFF&=~IFF_1;
+               M_RET;break;
+
+case NEG:      I=R->AF.B.h;R->AF.B.h=0;M_SUB(I);break;
+
+case IN_B_xC:  M_IN(R->BC.B.h);break;
+case IN_C_xC:  M_IN(R->BC.B.l);break;
+case IN_D_xC:  M_IN(R->DE.B.h);break;
+case IN_E_xC:  M_IN(R->DE.B.l);break;
+case IN_H_xC:  M_IN(R->HL.B.h);break;
+case IN_L_xC:  M_IN(R->HL.B.l);break;
+case IN_A_xC:  M_IN(R->AF.B.h);break;
+case IN_F_xC:  M_IN(J.B.l);break;
+
+case OUT_xC_B: OutZ80(R->BC.W,R->BC.B.h);break;
+case OUT_xC_C: OutZ80(R->BC.W,R->BC.B.l);break;
+case OUT_xC_D: OutZ80(R->BC.W,R->DE.B.h);break;
+case OUT_xC_E: OutZ80(R->BC.W,R->DE.B.l);break;
+case OUT_xC_H: OutZ80(R->BC.W,R->HL.B.h);break;
+case OUT_xC_L: OutZ80(R->BC.W,R->HL.B.l);break;
+case OUT_xC_A: OutZ80(R->BC.W,R->AF.B.h);break;
+
+case INI:
+  WrZ80(R->HL.W++,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INIR:
+  do
+  {
+    WrZ80(R->HL.W++,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case IND:
+  WrZ80(R->HL.W--,InZ80(R->BC.W));
+  --R->BC.B.h;
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG);
+  break;
+
+case INDR:
+  do
+  {
+    WrZ80(R->HL.W--,InZ80(R->BC.W));
+    --R->BC.B.h;R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h) { R->AF.B.l=N_FLAG;R->PC.W-=2; }
+  else { R->AF.B.l=Z_FLAG|N_FLAG;R->ICount+=5; }
+  break;
+
+case OUTI:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W++);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTIR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W++);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case OUTD:
+  --R->BC.B.h;
+  I=RdZ80(R->HL.W--);
+  OutZ80(R->BC.W,I);
+  R->AF.B.l=N_FLAG|(R->BC.B.h? 0:Z_FLAG)|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+  break;
+
+case OTDR:
+  do
+  {
+    --R->BC.B.h;
+    I=RdZ80(R->HL.W--);
+    OutZ80(R->BC.W,I);
+    R->ICount-=21;
+  }
+  while(R->BC.B.h&&(R->ICount>0));
+  if(R->BC.B.h)
+  {
+    R->AF.B.l=N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->PC.W-=2;
+  }
+  else
+  {
+    R->AF.B.l=Z_FLAG|N_FLAG|(R->HL.B.l+I>255? (C_FLAG|H_FLAG):0);
+    R->ICount+=5;
+  }
+  break;
+
+case LDI:
+  WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDIR:
+  do
+  {
+    WrZ80(R->DE.W++,RdZ80(R->HL.W++));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case LDD:
+  WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+  --R->BC.W;
+  R->AF.B.l=(R->AF.B.l&~(N_FLAG|H_FLAG|P_FLAG))|(R->BC.W? P_FLAG:0);
+  break;
+
+case LDDR:
+  do
+  {
+    WrZ80(R->DE.W--,RdZ80(R->HL.W--));
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&(R->ICount>0));
+  R->AF.B.l&=~(N_FLAG|H_FLAG|P_FLAG);
+  if(R->BC.W) { R->AF.B.l|=N_FLAG;R->PC.W-=2; }
+  else R->ICount+=5;
+  break;
+
+case CPI:
+  I=RdZ80(R->HL.W++);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPIR:
+  do
+  {
+    I=RdZ80(R->HL.W++);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }  
+  while(R->BC.W&&J.B.l&&(R->ICount>0));
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;  
+
+case CPD:
+  I=RdZ80(R->HL.W--);
+  J.B.l=R->AF.B.h-I;
+  --R->BC.W;
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  break;
+
+case CPDR:
+  do
+  {
+    I=RdZ80(R->HL.W--);
+    J.B.l=R->AF.B.h-I;
+    --R->BC.W;R->ICount-=21;
+  }
+  while(R->BC.W&&J.B.l);
+  R->AF.B.l =
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[J.B.l]|
+    ((R->AF.B.h^I^J.B.l)&H_FLAG)|(R->BC.W? P_FLAG:0);
+  if(R->BC.W&&J.B.l) R->PC.W-=2; else R->ICount+=5;
+  break;
diff --git a/MCUME_pico2/picospeccy/CodesXCB.h b/MCUME_pico2/picospeccy/CodesXCB.h
new file mode 100755
index 0000000..d0873ce
--- /dev/null
+++ b/MCUME_pico2/picospeccy/CodesXCB.h
@@ -0,0 +1,64 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXCB.h                      **/
+/**                                                         **/
+/** This file contains implementation for FD/DD-CB tables   **/
+/** of Z80 commands. It is included from Z80.c.             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
+case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
+case RL_xHL:  I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
+case RR_xHL:  I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
+case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
+case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
+case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
+case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
+
+case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
+case BIT0_H: case BIT0_L: case BIT0_A:
+case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
+case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
+case BIT1_H: case BIT1_L: case BIT1_A:
+case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
+case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
+case BIT2_H: case BIT2_L: case BIT2_A:
+case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
+case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
+case BIT3_H: case BIT3_L: case BIT3_A:
+case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
+case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
+case BIT4_H: case BIT4_L: case BIT4_A:
+case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
+case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
+case BIT5_H: case BIT5_L: case BIT5_A:
+case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
+case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
+case BIT6_H: case BIT6_L: case BIT6_A:
+case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
+case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
+case BIT7_H: case BIT7_L: case BIT7_A:
+case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
+
+case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
+case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;   
+case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;   
+case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;   
+case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;   
+case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;   
+case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;   
+case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;   
+
+case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;   
+case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break; 
+case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break; 
+case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break; 
+case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break; 
+case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break; 
+case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break; 
+case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break; 
diff --git a/MCUME_pico2/picospeccy/CodesXX.h b/MCUME_pico2/picospeccy/CodesXX.h
new file mode 100755
index 0000000..970b30e
--- /dev/null
+++ b/MCUME_pico2/picospeccy/CodesXX.h
@@ -0,0 +1,396 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                         CodesXX.h                       **/
+/**                                                         **/
+/** This file contains implementation for FD/DD tables of   **/
+/** Z80 commands. It is included from Z80.c.                **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+
+case JR_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_NC:   if(R->AF.B.l&C_FLAG) R->PC.W++; else { R->ICount-=5;M_JR; } break;
+case JR_Z:    if(R->AF.B.l&Z_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+case JR_C:    if(R->AF.B.l&C_FLAG) { R->ICount-=5;M_JR; } else R->PC.W++; break;
+
+case JP_NZ:   if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_NC:   if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_PO:   if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_P:    if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { M_JP; } break;
+case JP_Z:    if(R->AF.B.l&Z_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_C:    if(R->AF.B.l&C_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_PE:   if(R->AF.B.l&P_FLAG) { M_JP; } else R->PC.W+=2; break;
+case JP_M:    if(R->AF.B.l&S_FLAG) { M_JP; } else R->PC.W+=2; break;
+
+case RET_NZ:  if(!(R->AF.B.l&Z_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_NC:  if(!(R->AF.B.l&C_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_PO:  if(!(R->AF.B.l&P_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_P:   if(!(R->AF.B.l&S_FLAG)) { R->ICount-=6;M_RET; } break;
+case RET_Z:   if(R->AF.B.l&Z_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_C:   if(R->AF.B.l&C_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_PE:  if(R->AF.B.l&P_FLAG)    { R->ICount-=6;M_RET; } break;
+case RET_M:   if(R->AF.B.l&S_FLAG)    { R->ICount-=6;M_RET; } break;
+
+case CALL_NZ: if(R->AF.B.l&Z_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_NC: if(R->AF.B.l&C_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_PO: if(R->AF.B.l&P_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_P:  if(R->AF.B.l&S_FLAG) R->PC.W+=2; else { R->ICount-=7;M_CALL; } break;
+case CALL_Z:  if(R->AF.B.l&Z_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_C:  if(R->AF.B.l&C_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_PE: if(R->AF.B.l&P_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+case CALL_M:  if(R->AF.B.l&S_FLAG) { R->ICount-=7;M_CALL; } else R->PC.W+=2; break;
+
+case ADD_B:    M_ADD(R->BC.B.h);break;
+case ADD_C:    M_ADD(R->BC.B.l);break;
+case ADD_D:    M_ADD(R->DE.B.h);break;
+case ADD_E:    M_ADD(R->DE.B.l);break;
+case ADD_H:    M_ADD(R->XX.B.h);break;
+case ADD_L:    M_ADD(R->XX.B.l);break;
+case ADD_A:    M_ADD(R->AF.B.h);break;
+case ADD_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADD(I);break;
+case ADD_BYTE: I=OpZ80(R->PC.W++);M_ADD(I);break;
+
+case SUB_B:    M_SUB(R->BC.B.h);break;
+case SUB_C:    M_SUB(R->BC.B.l);break;
+case SUB_D:    M_SUB(R->DE.B.h);break;
+case SUB_E:    M_SUB(R->DE.B.l);break;
+case SUB_H:    M_SUB(R->XX.B.h);break;
+case SUB_L:    M_SUB(R->XX.B.l);break;
+case SUB_A:    R->AF.B.h=0;R->AF.B.l=N_FLAG|Z_FLAG;break;
+case SUB_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SUB(I);break;
+case SUB_BYTE: I=OpZ80(R->PC.W++);M_SUB(I);break;
+
+case AND_B:    M_AND(R->BC.B.h);break;
+case AND_C:    M_AND(R->BC.B.l);break;
+case AND_D:    M_AND(R->DE.B.h);break;
+case AND_E:    M_AND(R->DE.B.l);break;
+case AND_H:    M_AND(R->XX.B.h);break;
+case AND_L:    M_AND(R->XX.B.l);break;
+case AND_A:    M_AND(R->AF.B.h);break;
+case AND_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_AND(I);break;
+case AND_BYTE: I=OpZ80(R->PC.W++);M_AND(I);break;
+
+case OR_B:     M_OR(R->BC.B.h);break;
+case OR_C:     M_OR(R->BC.B.l);break;
+case OR_D:     M_OR(R->DE.B.h);break;
+case OR_E:     M_OR(R->DE.B.l);break;
+case OR_H:     M_OR(R->XX.B.h);break;
+case OR_L:     M_OR(R->XX.B.l);break;
+case OR_A:     M_OR(R->AF.B.h);break;
+case OR_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_OR(I);break;
+case OR_BYTE:  I=OpZ80(R->PC.W++);M_OR(I);break;
+
+case ADC_B:    M_ADC(R->BC.B.h);break;
+case ADC_C:    M_ADC(R->BC.B.l);break;
+case ADC_D:    M_ADC(R->DE.B.h);break;
+case ADC_E:    M_ADC(R->DE.B.l);break;
+case ADC_H:    M_ADC(R->XX.B.h);break;
+case ADC_L:    M_ADC(R->XX.B.l);break;
+case ADC_A:    M_ADC(R->AF.B.h);break;
+case ADC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_ADC(I);break;
+case ADC_BYTE: I=OpZ80(R->PC.W++);M_ADC(I);break;
+
+case SBC_B:    M_SBC(R->BC.B.h);break;
+case SBC_C:    M_SBC(R->BC.B.l);break;
+case SBC_D:    M_SBC(R->DE.B.h);break;
+case SBC_E:    M_SBC(R->DE.B.l);break;
+case SBC_H:    M_SBC(R->XX.B.h);break;
+case SBC_L:    M_SBC(R->XX.B.l);break;
+case SBC_A:    M_SBC(R->AF.B.h);break;
+case SBC_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_SBC(I);break;
+case SBC_BYTE: I=OpZ80(R->PC.W++);M_SBC(I);break;
+
+case XOR_B:    M_XOR(R->BC.B.h);break;
+case XOR_C:    M_XOR(R->BC.B.l);break;
+case XOR_D:    M_XOR(R->DE.B.h);break;
+case XOR_E:    M_XOR(R->DE.B.l);break;
+case XOR_H:    M_XOR(R->XX.B.h);break;
+case XOR_L:    M_XOR(R->XX.B.l);break;
+case XOR_A:    R->AF.B.h=0;R->AF.B.l=P_FLAG|Z_FLAG;break;
+case XOR_xHL:  I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_XOR(I);break;
+case XOR_BYTE: I=OpZ80(R->PC.W++);M_XOR(I);break;
+
+case CP_B:     M_CP(R->BC.B.h);break;
+case CP_C:     M_CP(R->BC.B.l);break;
+case CP_D:     M_CP(R->DE.B.h);break;
+case CP_E:     M_CP(R->DE.B.l);break;
+case CP_H:     M_CP(R->XX.B.h);break;
+case CP_L:     M_CP(R->XX.B.l);break;
+case CP_A:     R->AF.B.l=N_FLAG|Z_FLAG;break;
+case CP_xHL:   I=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));
+               M_CP(I);break;
+case CP_BYTE:  I=OpZ80(R->PC.W++);M_CP(I);break;
+               
+case LD_BC_WORD: M_LDWORD(BC);break;
+case LD_DE_WORD: M_LDWORD(DE);break;
+case LD_HL_WORD: M_LDWORD(XX);break;
+case LD_SP_WORD: M_LDWORD(SP);break;
+
+case LD_PC_HL: R->PC.W=R->XX.W;JumpZ80(R->PC.W);break;
+case LD_SP_HL: R->SP.W=R->XX.W;break;
+case LD_A_xBC: R->AF.B.h=RdZ80(R->BC.W);break;
+case LD_A_xDE: R->AF.B.h=RdZ80(R->DE.W);break;
+
+case ADD_HL_BC:  M_ADDW(XX,BC);break;
+case ADD_HL_DE:  M_ADDW(XX,DE);break;
+case ADD_HL_HL:  M_ADDW(XX,XX);break;
+case ADD_HL_SP:  M_ADDW(XX,SP);break;
+
+case DEC_BC:   R->BC.W--;break;
+case DEC_DE:   R->DE.W--;break;
+case DEC_HL:   R->XX.W--;break;
+case DEC_SP:   R->SP.W--;break;
+
+case INC_BC:   R->BC.W++;break;
+case INC_DE:   R->DE.W++;break;
+case INC_HL:   R->XX.W++;break;
+case INC_SP:   R->SP.W++;break;
+
+case DEC_B:    M_DEC(R->BC.B.h);break;
+case DEC_C:    M_DEC(R->BC.B.l);break;
+case DEC_D:    M_DEC(R->DE.B.h);break;
+case DEC_E:    M_DEC(R->DE.B.l);break;
+case DEC_H:    M_DEC(R->XX.B.h);break;
+case DEC_L:    M_DEC(R->XX.B.l);break;
+case DEC_A:    M_DEC(R->AF.B.h);break;
+case DEC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_DEC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case INC_B:    M_INC(R->BC.B.h);break;
+case INC_C:    M_INC(R->BC.B.l);break;
+case INC_D:    M_INC(R->DE.B.h);break;
+case INC_E:    M_INC(R->DE.B.l);break;
+case INC_H:    M_INC(R->XX.B.h);break;
+case INC_L:    M_INC(R->XX.B.l);break;
+case INC_A:    M_INC(R->AF.B.h);break;
+case INC_xHL:  I=RdZ80(R->XX.W+(offset)RdZ80(R->PC.W));M_INC(I);
+               WrZ80(R->XX.W+(offset)OpZ80(R->PC.W++),I);
+               break;
+
+case RLCA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|I;
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RLA:
+  I=(R->AF.B.h&0x80? C_FLAG:0);
+  R->AF.B.h=(R->AF.B.h<<1)|(R->AF.B.l&C_FLAG);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRCA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(I? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+case RRA:
+  I=R->AF.B.h&0x01;
+  R->AF.B.h=(R->AF.B.h>>1)|(R->AF.B.l&C_FLAG? 0x80:0);
+  R->AF.B.l=(R->AF.B.l&~(C_FLAG|N_FLAG|H_FLAG))|I;
+  break;
+
+case RST00:    M_RST(0x0000);break;
+case RST08:    M_RST(0x0008);break;
+case RST10:    M_RST(0x0010);break;
+case RST18:    M_RST(0x0018);break;
+case RST20:    M_RST(0x0020);break;
+case RST28:    M_RST(0x0028);break;
+case RST30:    M_RST(0x0030);break;
+case RST38:    M_RST(0x0038);break;
+
+case PUSH_BC:  M_PUSH(BC);break;
+case PUSH_DE:  M_PUSH(DE);break;
+case PUSH_HL:  M_PUSH(XX);break;
+case PUSH_AF:  M_PUSH(AF);break;
+
+case POP_BC:   M_POP(BC);break;
+case POP_DE:   M_POP(DE);break;
+case POP_HL:   M_POP(XX);break;
+case POP_AF:   M_POP(AF);break;
+
+case DJNZ: if(--R->BC.B.h) { R->ICount-=5;M_JR; } else R->PC.W++;break;
+case JP:   M_JP;break;
+case JR:   M_JR;break;
+case CALL: M_CALL;break;
+case RET:  M_RET;break;
+case SCF:  S(C_FLAG);R(N_FLAG|H_FLAG);break;
+case CPL:  R->AF.B.h=~R->AF.B.h;S(N_FLAG|H_FLAG);break;
+case NOP:  break;
+case OUTA: I=OpZ80(R->PC.W++);OutZ80(I|(R->AF.W&0xFF00),R->AF.B.h);break;
+case INA:  I=OpZ80(R->PC.W++);R->AF.B.h=InZ80(I|(R->AF.W&0xFF00));break;
+
+case HALT:
+  R->PC.W--;
+  R->IFF|=IFF_HALT;
+  R->IBackup=0;
+  R->ICount=0;
+  break;
+
+case DI:
+  if(R->IFF&IFF_EI) R->ICount+=R->IBackup-1;
+  R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  break;
+
+case EI:
+  if(!(R->IFF&(IFF_1|IFF_EI)))
+  {
+    R->IFF|=IFF_2|IFF_EI;
+    R->IBackup=R->ICount;
+    R->ICount=1;
+  }
+  break;
+
+case CCF:
+  R->AF.B.l^=C_FLAG;R(N_FLAG|H_FLAG);
+  R->AF.B.l|=R->AF.B.l&C_FLAG? 0:H_FLAG;
+  break;
+
+case EXX:
+  J.W=R->BC.W;R->BC.W=R->BC1.W;R->BC1.W=J.W;
+  J.W=R->DE.W;R->DE.W=R->DE1.W;R->DE1.W=J.W;
+  J.W=R->HL.W;R->HL.W=R->HL1.W;R->HL1.W=J.W;
+  break;
+
+case EX_DE_HL: J.W=R->DE.W;R->DE.W=R->HL.W;R->HL.W=J.W;break;
+case EX_AF_AF: J.W=R->AF.W;R->AF.W=R->AF1.W;R->AF1.W=J.W;break;  
+  
+case LD_B_B:   R->BC.B.h=R->BC.B.h;break;
+case LD_C_B:   R->BC.B.l=R->BC.B.h;break;
+case LD_D_B:   R->DE.B.h=R->BC.B.h;break;
+case LD_E_B:   R->DE.B.l=R->BC.B.h;break;
+case LD_H_B:   R->XX.B.h=R->BC.B.h;break;
+case LD_L_B:   R->XX.B.l=R->BC.B.h;break;
+case LD_A_B:   R->AF.B.h=R->BC.B.h;break;
+case LD_xHL_B: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.h);break;
+
+case LD_B_C:   R->BC.B.h=R->BC.B.l;break;
+case LD_C_C:   R->BC.B.l=R->BC.B.l;break;
+case LD_D_C:   R->DE.B.h=R->BC.B.l;break;
+case LD_E_C:   R->DE.B.l=R->BC.B.l;break;
+case LD_H_C:   R->XX.B.h=R->BC.B.l;break;
+case LD_L_C:   R->XX.B.l=R->BC.B.l;break;
+case LD_A_C:   R->AF.B.h=R->BC.B.l;break;
+case LD_xHL_C: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->BC.B.l);break;
+
+case LD_B_D:   R->BC.B.h=R->DE.B.h;break;
+case LD_C_D:   R->BC.B.l=R->DE.B.h;break;
+case LD_D_D:   R->DE.B.h=R->DE.B.h;break;
+case LD_E_D:   R->DE.B.l=R->DE.B.h;break;
+case LD_H_D:   R->XX.B.h=R->DE.B.h;break;
+case LD_L_D:   R->XX.B.l=R->DE.B.h;break;
+case LD_A_D:   R->AF.B.h=R->DE.B.h;break;
+case LD_xHL_D: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.h);break;
+
+case LD_B_E:   R->BC.B.h=R->DE.B.l;break;
+case LD_C_E:   R->BC.B.l=R->DE.B.l;break;
+case LD_D_E:   R->DE.B.h=R->DE.B.l;break;
+case LD_E_E:   R->DE.B.l=R->DE.B.l;break;
+case LD_H_E:   R->XX.B.h=R->DE.B.l;break;
+case LD_L_E:   R->XX.B.l=R->DE.B.l;break;
+case LD_A_E:   R->AF.B.h=R->DE.B.l;break;
+case LD_xHL_E: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->DE.B.l);break;
+
+case LD_B_H:   R->BC.B.h=R->XX.B.h;break;
+case LD_C_H:   R->BC.B.l=R->XX.B.h;break;
+case LD_D_H:   R->DE.B.h=R->XX.B.h;break;
+case LD_E_H:   R->DE.B.l=R->XX.B.h;break;
+case LD_H_H:   R->XX.B.h=R->XX.B.h;break;
+case LD_L_H:   R->XX.B.l=R->XX.B.h;break;
+case LD_A_H:   R->AF.B.h=R->XX.B.h;break;
+case LD_xHL_H: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.h);break;
+
+case LD_B_L:   R->BC.B.h=R->XX.B.l;break;
+case LD_C_L:   R->BC.B.l=R->XX.B.l;break;
+case LD_D_L:   R->DE.B.h=R->XX.B.l;break;
+case LD_E_L:   R->DE.B.l=R->XX.B.l;break;
+case LD_H_L:   R->XX.B.h=R->XX.B.l;break;
+case LD_L_L:   R->XX.B.l=R->XX.B.l;break;
+case LD_A_L:   R->AF.B.h=R->XX.B.l;break;
+case LD_xHL_L: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->HL.B.l);break;
+
+case LD_B_A:   R->BC.B.h=R->AF.B.h;break;
+case LD_C_A:   R->BC.B.l=R->AF.B.h;break;
+case LD_D_A:   R->DE.B.h=R->AF.B.h;break;
+case LD_E_A:   R->DE.B.l=R->AF.B.h;break;
+case LD_H_A:   R->XX.B.h=R->AF.B.h;break;
+case LD_L_A:   R->XX.B.l=R->AF.B.h;break;
+case LD_A_A:   R->AF.B.h=R->AF.B.h;break;
+case LD_xHL_A: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+               WrZ80(J.W,R->AF.B.h);break;
+
+case LD_xBC_A: WrZ80(R->BC.W,R->AF.B.h);break;
+case LD_xDE_A: WrZ80(R->DE.W,R->AF.B.h);break;
+
+case LD_B_xHL:    R->BC.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_C_xHL:    R->BC.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_D_xHL:    R->DE.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_E_xHL:    R->DE.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_H_xHL:    R->HL.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_L_xHL:    R->HL.B.l=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+case LD_A_xHL:    R->AF.B.h=RdZ80(R->XX.W+(offset)OpZ80(R->PC.W++));break;
+
+case LD_B_BYTE:   R->BC.B.h=OpZ80(R->PC.W++);break;
+case LD_C_BYTE:   R->BC.B.l=OpZ80(R->PC.W++);break;
+case LD_D_BYTE:   R->DE.B.h=OpZ80(R->PC.W++);break;
+case LD_E_BYTE:   R->DE.B.l=OpZ80(R->PC.W++);break;
+case LD_H_BYTE:   R->XX.B.h=OpZ80(R->PC.W++);break;
+case LD_L_BYTE:   R->XX.B.l=OpZ80(R->PC.W++);break;
+case LD_A_BYTE:   R->AF.B.h=OpZ80(R->PC.W++);break;
+case LD_xHL_BYTE: J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+                  WrZ80(J.W,OpZ80(R->PC.W++));break;
+
+case LD_xWORD_HL:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W++,R->XX.B.l);
+  WrZ80(J.W,R->XX.B.h);
+  break;
+
+case LD_HL_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->XX.B.l=RdZ80(J.W++);
+  R->XX.B.h=RdZ80(J.W);
+  break;
+
+case LD_A_xWORD:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  R->AF.B.h=RdZ80(J.W);
+  break;
+
+case LD_xWORD_A:
+  J.B.l=OpZ80(R->PC.W++);
+  J.B.h=OpZ80(R->PC.W++);
+  WrZ80(J.W,R->AF.B.h);
+  break;
+
+case EX_HL_xSP:
+  J.B.l=RdZ80(R->SP.W);WrZ80(R->SP.W++,R->XX.B.l);
+  J.B.h=RdZ80(R->SP.W);WrZ80(R->SP.W--,R->XX.B.h);
+  R->XX.W=J.W;
+  break;
+
+case DAA:
+  J.W=R->AF.B.h;
+  if(R->AF.B.l&C_FLAG) J.W|=256;
+  if(R->AF.B.l&H_FLAG) J.W|=512;
+  if(R->AF.B.l&N_FLAG) J.W|=1024;
+  R->AF.W=DAATable[J.W];
+  break;
diff --git a/MCUME_pico2/picospeccy/Tables.h b/MCUME_pico2/picospeccy/Tables.h
new file mode 100755
index 0000000..ba1ebee
--- /dev/null
+++ b/MCUME_pico2/picospeccy/Tables.h
@@ -0,0 +1,447 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                          Tables.h                       **/
+/**                                                         **/
+/** This file contains tables of used by Z80 emulation to   **/
+/** compute SIGN,ZERO, PARITY flags, and decimal correction **/
+/** There are also timing tables for Z80 opcodes. This file **/
+/** is included from Z80.c.                                 **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+static const byte Cycles[256] =
+{
+   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
+   8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
+   7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
+   7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
+   5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
+   5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
+   5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
+   5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 
+};
+
+static const byte CyclesCB[256] =
+{
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
+   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 
+};
+
+static const byte CyclesED[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  12,12,15,20, 8,14, 8, 9,12,12,15,20, 0,14, 0, 9,
+  12,12,15,20, 0, 0, 8, 9,12,12,15,20, 0, 0, 8, 9,
+  12,12,15,20, 0, 0, 0,18,12,12,15,20, 0, 0, 0,18,
+  12, 0,15,20, 0, 0, 0, 0,12,12,15,20, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  16,16,16,16, 0, 0, 0, 0,16,16,16,16, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXX[256] =
+{
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0,14,20,10, 9, 9, 9, 0, 0,15,20,10, 9, 9, 9, 0,
+   0, 0, 0, 0,23,23,19, 0, 0,15, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
+  19,19,19,19,19,19,19,19, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 9, 9,19, 0, 0, 0, 0, 0, 9, 9,19, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0,14, 0,23, 0,15, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0, 0,10, 0, 0, 0, 0, 0, 0
+};
+
+static const byte CyclesXXCB[256] =
+{
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+  20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0,
+   0, 0, 0, 0, 0, 0,23, 0, 0, 0, 0, 0, 0, 0,23, 0
+};
+
+static const byte ZSTable[256] =
+{
+  Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
+  S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
+};
+
+static const byte PZSTable[256] =
+{
+  Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,
+  0,P_FLAG,P_FLAG,0,P_FLAG,0,0,P_FLAG,P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG,S_FLAG|P_FLAG,S_FLAG|P_FLAG,S_FLAG,
+  S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
+};
+
+static const word DAATable[2048] =
+{
+  0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,
+  0x0808,0x090C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,
+  0x180C,0x1908,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,
+  0x282C,0x2928,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,
+  0x3828,0x392C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,
+  0x480C,0x4908,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,
+  0x5808,0x590C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,
+  0x6828,0x692C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,
+  0x782C,0x7928,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,
+  0x888C,0x8988,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,
+  0x9888,0x998C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6025,0x6121,0x6221,0x6325,0x6421,0x6525,0x6625,0x6721,
+  0x6829,0x692D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7021,0x7125,0x7225,0x7321,0x7425,0x7521,0x7621,0x7725,
+  0x782D,0x7929,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8081,0x8185,0x8285,0x8381,0x8485,0x8581,0x8681,0x8785,
+  0x888D,0x8989,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9085,0x9181,0x9281,0x9385,0x9481,0x9585,0x9685,0x9781,
+  0x9889,0x998D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA0A5,0xA1A1,0xA2A1,0xA3A5,0xA4A1,0xA5A5,0xA6A5,0xA7A1,
+  0xA8A9,0xA9AD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB0A1,0xB1A5,0xB2A5,0xB3A1,0xB4A5,0xB5A1,0xB6A1,0xB7A5,
+  0xB8AD,0xB9A9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC085,0xC181,0xC281,0xC385,0xC481,0xC585,0xC685,0xC781,
+  0xC889,0xC98D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD081,0xD185,0xD285,0xD381,0xD485,0xD581,0xD681,0xD785,
+  0xD88D,0xD989,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE0A1,0xE1A5,0xE2A5,0xE3A1,0xE4A5,0xE5A1,0xE6A1,0xE7A5,
+  0xE8AD,0xE9A9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF0A5,0xF1A1,0xF2A1,0xF3A5,0xF4A1,0xF5A5,0xF6A5,0xF7A1,
+  0xF8A9,0xF9AD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0045,0x0101,0x0201,0x0305,0x0401,0x0505,0x0605,0x0701,
+  0x0809,0x090D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1001,0x1105,0x1205,0x1301,0x1405,0x1501,0x1601,0x1705,
+  0x180D,0x1909,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2021,0x2125,0x2225,0x2321,0x2425,0x2521,0x2621,0x2725,
+  0x282D,0x2929,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3025,0x3121,0x3221,0x3325,0x3421,0x3525,0x3625,0x3721,
+  0x3829,0x392D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4001,0x4105,0x4205,0x4301,0x4405,0x4501,0x4601,0x4705,
+  0x480D,0x4909,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5005,0x5101,0x5201,0x5305,0x5401,0x5505,0x5605,0x5701,
+  0x5809,0x590D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0604,0x0700,0x0808,0x090C,0x0A0C,0x0B08,0x0C0C,0x0D08,
+  0x0E08,0x0F0C,0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,
+  0x1600,0x1704,0x180C,0x1908,0x1A08,0x1B0C,0x1C08,0x1D0C,
+  0x1E0C,0x1F08,0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,
+  0x2620,0x2724,0x282C,0x2928,0x2A28,0x2B2C,0x2C28,0x2D2C,
+  0x2E2C,0x2F28,0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,
+  0x3624,0x3720,0x3828,0x392C,0x3A2C,0x3B28,0x3C2C,0x3D28,
+  0x3E28,0x3F2C,0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,
+  0x4600,0x4704,0x480C,0x4908,0x4A08,0x4B0C,0x4C08,0x4D0C,
+  0x4E0C,0x4F08,0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,
+  0x5604,0x5700,0x5808,0x590C,0x5A0C,0x5B08,0x5C0C,0x5D08,
+  0x5E08,0x5F0C,0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,
+  0x6624,0x6720,0x6828,0x692C,0x6A2C,0x6B28,0x6C2C,0x6D28,
+  0x6E28,0x6F2C,0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,
+  0x7620,0x7724,0x782C,0x7928,0x7A28,0x7B2C,0x7C28,0x7D2C,
+  0x7E2C,0x7F28,0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,
+  0x8680,0x8784,0x888C,0x8988,0x8A88,0x8B8C,0x8C88,0x8D8C,
+  0x8E8C,0x8F88,0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,
+  0x9684,0x9780,0x9888,0x998C,0x9A8C,0x9B88,0x9C8C,0x9D88,
+  0x9E88,0x9F8C,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x6625,0x6721,0x6829,0x692D,0x6A2D,0x6B29,0x6C2D,0x6D29,
+  0x6E29,0x6F2D,0x7031,0x7135,0x7235,0x7331,0x7435,0x7531,
+  0x7621,0x7725,0x782D,0x7929,0x7A29,0x7B2D,0x7C29,0x7D2D,
+  0x7E2D,0x7F29,0x8091,0x8195,0x8295,0x8391,0x8495,0x8591,
+  0x8681,0x8785,0x888D,0x8989,0x8A89,0x8B8D,0x8C89,0x8D8D,
+  0x8E8D,0x8F89,0x9095,0x9191,0x9291,0x9395,0x9491,0x9595,
+  0x9685,0x9781,0x9889,0x998D,0x9A8D,0x9B89,0x9C8D,0x9D89,
+  0x9E89,0x9F8D,0xA0B5,0xA1B1,0xA2B1,0xA3B5,0xA4B1,0xA5B5,
+  0xA6A5,0xA7A1,0xA8A9,0xA9AD,0xAAAD,0xABA9,0xACAD,0xADA9,
+  0xAEA9,0xAFAD,0xB0B1,0xB1B5,0xB2B5,0xB3B1,0xB4B5,0xB5B1,
+  0xB6A1,0xB7A5,0xB8AD,0xB9A9,0xBAA9,0xBBAD,0xBCA9,0xBDAD,
+  0xBEAD,0xBFA9,0xC095,0xC191,0xC291,0xC395,0xC491,0xC595,
+  0xC685,0xC781,0xC889,0xC98D,0xCA8D,0xCB89,0xCC8D,0xCD89,
+  0xCE89,0xCF8D,0xD091,0xD195,0xD295,0xD391,0xD495,0xD591,
+  0xD681,0xD785,0xD88D,0xD989,0xDA89,0xDB8D,0xDC89,0xDD8D,
+  0xDE8D,0xDF89,0xE0B1,0xE1B5,0xE2B5,0xE3B1,0xE4B5,0xE5B1,
+  0xE6A1,0xE7A5,0xE8AD,0xE9A9,0xEAA9,0xEBAD,0xECA9,0xEDAD,
+  0xEEAD,0xEFA9,0xF0B5,0xF1B1,0xF2B1,0xF3B5,0xF4B1,0xF5B5,
+  0xF6A5,0xF7A1,0xF8A9,0xF9AD,0xFAAD,0xFBA9,0xFCAD,0xFDA9,
+  0xFEA9,0xFFAD,0x0055,0x0111,0x0211,0x0315,0x0411,0x0515,
+  0x0605,0x0701,0x0809,0x090D,0x0A0D,0x0B09,0x0C0D,0x0D09,
+  0x0E09,0x0F0D,0x1011,0x1115,0x1215,0x1311,0x1415,0x1511,
+  0x1601,0x1705,0x180D,0x1909,0x1A09,0x1B0D,0x1C09,0x1D0D,
+  0x1E0D,0x1F09,0x2031,0x2135,0x2235,0x2331,0x2435,0x2531,
+  0x2621,0x2725,0x282D,0x2929,0x2A29,0x2B2D,0x2C29,0x2D2D,
+  0x2E2D,0x2F29,0x3035,0x3131,0x3231,0x3335,0x3431,0x3535,
+  0x3625,0x3721,0x3829,0x392D,0x3A2D,0x3B29,0x3C2D,0x3D29,
+  0x3E29,0x3F2D,0x4011,0x4115,0x4215,0x4311,0x4415,0x4511,
+  0x4601,0x4705,0x480D,0x4909,0x4A09,0x4B0D,0x4C09,0x4D0D,
+  0x4E0D,0x4F09,0x5015,0x5111,0x5211,0x5315,0x5411,0x5515,
+  0x5605,0x5701,0x5809,0x590D,0x5A0D,0x5B09,0x5C0D,0x5D09,
+  0x5E09,0x5F0D,0x6035,0x6131,0x6231,0x6335,0x6431,0x6535,
+  0x0046,0x0102,0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,
+  0x080A,0x090E,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x1002,0x1106,0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,
+  0x180E,0x190A,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x2022,0x2126,0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,
+  0x282E,0x292A,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x3026,0x3122,0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,
+  0x382A,0x392E,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x4002,0x4106,0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,
+  0x480E,0x490A,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x5006,0x5102,0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,
+  0x580A,0x590E,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x6026,0x6122,0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,
+  0x682A,0x692E,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x7022,0x7126,0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,
+  0x782E,0x792A,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x8082,0x8186,0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,
+  0x888E,0x898A,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x9086,0x9182,0x9282,0x9386,0x9482,0x9586,0x9686,0x9782,
+  0x988A,0x998E,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xA0A7,0xA1A3,0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,
+  0xA8AB,0xA9AF,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xB0A3,0xB1A7,0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,
+  0xB8AF,0xB9AB,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xC087,0xC183,0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,
+  0xC88B,0xC98F,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xD083,0xD187,0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,
+  0xD88F,0xD98B,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xE0A3,0xE1A7,0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,
+  0xE8AF,0xE9AB,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xF0A7,0xF1A3,0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,
+  0xF8AB,0xF9AF,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0x0047,0x0103,0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,
+  0x080B,0x090F,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x1003,0x1107,0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,
+  0x180F,0x190B,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x2023,0x2127,0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,
+  0x282F,0x292B,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x3027,0x3123,0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,
+  0x382B,0x392F,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x4003,0x4107,0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,
+  0x480F,0x490B,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x5007,0x5103,0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,
+  0x580B,0x590F,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x6027,0x6123,0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,
+  0x682B,0x692F,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x7023,0x7127,0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,
+  0x782F,0x792B,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x8083,0x8187,0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,
+  0x888F,0x898B,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x9087,0x9183,0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,
+  0x988B,0x998F,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0xFABE,0xFBBA,0xFCBE,0xFDBA,0xFEBA,0xFFBE,0x0046,0x0102,
+  0x0202,0x0306,0x0402,0x0506,0x0606,0x0702,0x080A,0x090E,
+  0x0A1E,0x0B1A,0x0C1E,0x0D1A,0x0E1A,0x0F1E,0x1002,0x1106,
+  0x1206,0x1302,0x1406,0x1502,0x1602,0x1706,0x180E,0x190A,
+  0x1A1A,0x1B1E,0x1C1A,0x1D1E,0x1E1E,0x1F1A,0x2022,0x2126,
+  0x2226,0x2322,0x2426,0x2522,0x2622,0x2726,0x282E,0x292A,
+  0x2A3A,0x2B3E,0x2C3A,0x2D3E,0x2E3E,0x2F3A,0x3026,0x3122,
+  0x3222,0x3326,0x3422,0x3526,0x3626,0x3722,0x382A,0x392E,
+  0x3A3E,0x3B3A,0x3C3E,0x3D3A,0x3E3A,0x3F3E,0x4002,0x4106,
+  0x4206,0x4302,0x4406,0x4502,0x4602,0x4706,0x480E,0x490A,
+  0x4A1A,0x4B1E,0x4C1A,0x4D1E,0x4E1E,0x4F1A,0x5006,0x5102,
+  0x5202,0x5306,0x5402,0x5506,0x5606,0x5702,0x580A,0x590E,
+  0x5A1E,0x5B1A,0x5C1E,0x5D1A,0x5E1A,0x5F1E,0x6026,0x6122,
+  0x6222,0x6326,0x6422,0x6526,0x6626,0x6722,0x682A,0x692E,
+  0x6A3E,0x6B3A,0x6C3E,0x6D3A,0x6E3A,0x6F3E,0x7022,0x7126,
+  0x7226,0x7322,0x7426,0x7522,0x7622,0x7726,0x782E,0x792A,
+  0x7A3A,0x7B3E,0x7C3A,0x7D3E,0x7E3E,0x7F3A,0x8082,0x8186,
+  0x8286,0x8382,0x8486,0x8582,0x8682,0x8786,0x888E,0x898A,
+  0x8A9A,0x8B9E,0x8C9A,0x8D9E,0x8E9E,0x8F9A,0x9086,0x9182,
+  0x9282,0x9386,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F,
+  0x9A9F,0x9B9B,0x9C9F,0x9D9B,0x9E9B,0x9F9F,0xA0A7,0xA1A3,
+  0xA2A3,0xA3A7,0xA4A3,0xA5A7,0xA6A7,0xA7A3,0xA8AB,0xA9AF,
+  0xAABF,0xABBB,0xACBF,0xADBB,0xAEBB,0xAFBF,0xB0A3,0xB1A7,
+  0xB2A7,0xB3A3,0xB4A7,0xB5A3,0xB6A3,0xB7A7,0xB8AF,0xB9AB,
+  0xBABB,0xBBBF,0xBCBB,0xBDBF,0xBEBF,0xBFBB,0xC087,0xC183,
+  0xC283,0xC387,0xC483,0xC587,0xC687,0xC783,0xC88B,0xC98F,
+  0xCA9F,0xCB9B,0xCC9F,0xCD9B,0xCE9B,0xCF9F,0xD083,0xD187,
+  0xD287,0xD383,0xD487,0xD583,0xD683,0xD787,0xD88F,0xD98B,
+  0xDA9B,0xDB9F,0xDC9B,0xDD9F,0xDE9F,0xDF9B,0xE0A3,0xE1A7,
+  0xE2A7,0xE3A3,0xE4A7,0xE5A3,0xE6A3,0xE7A7,0xE8AF,0xE9AB,
+  0xEABB,0xEBBF,0xECBB,0xEDBF,0xEEBF,0xEFBB,0xF0A7,0xF1A3,
+  0xF2A3,0xF3A7,0xF4A3,0xF5A7,0xF6A7,0xF7A3,0xF8AB,0xF9AF,
+  0xFABF,0xFBBB,0xFCBF,0xFDBB,0xFEBB,0xFFBF,0x0047,0x0103,
+  0x0203,0x0307,0x0403,0x0507,0x0607,0x0703,0x080B,0x090F,
+  0x0A1F,0x0B1B,0x0C1F,0x0D1B,0x0E1B,0x0F1F,0x1003,0x1107,
+  0x1207,0x1303,0x1407,0x1503,0x1603,0x1707,0x180F,0x190B,
+  0x1A1B,0x1B1F,0x1C1B,0x1D1F,0x1E1F,0x1F1B,0x2023,0x2127,
+  0x2227,0x2323,0x2427,0x2523,0x2623,0x2727,0x282F,0x292B,
+  0x2A3B,0x2B3F,0x2C3B,0x2D3F,0x2E3F,0x2F3B,0x3027,0x3123,
+  0x3223,0x3327,0x3423,0x3527,0x3627,0x3723,0x382B,0x392F,
+  0x3A3F,0x3B3B,0x3C3F,0x3D3B,0x3E3B,0x3F3F,0x4003,0x4107,
+  0x4207,0x4303,0x4407,0x4503,0x4603,0x4707,0x480F,0x490B,
+  0x4A1B,0x4B1F,0x4C1B,0x4D1F,0x4E1F,0x4F1B,0x5007,0x5103,
+  0x5203,0x5307,0x5403,0x5507,0x5607,0x5703,0x580B,0x590F,
+  0x5A1F,0x5B1B,0x5C1F,0x5D1B,0x5E1B,0x5F1F,0x6027,0x6123,
+  0x6223,0x6327,0x6423,0x6527,0x6627,0x6723,0x682B,0x692F,
+  0x6A3F,0x6B3B,0x6C3F,0x6D3B,0x6E3B,0x6F3F,0x7023,0x7127,
+  0x7227,0x7323,0x7427,0x7523,0x7623,0x7727,0x782F,0x792B,
+  0x7A3B,0x7B3F,0x7C3B,0x7D3F,0x7E3F,0x7F3B,0x8083,0x8187,
+  0x8287,0x8383,0x8487,0x8583,0x8683,0x8787,0x888F,0x898B,
+  0x8A9B,0x8B9F,0x8C9B,0x8D9F,0x8E9F,0x8F9B,0x9087,0x9183,
+  0x9283,0x9387,0x9483,0x9587,0x9687,0x9783,0x988B,0x998F
+};
diff --git a/MCUME_pico2/picospeccy/Z80.c b/MCUME_pico2/picospeccy/Z80.c
new file mode 100644
index 0000000..17f7572
--- /dev/null
+++ b/MCUME_pico2/picospeccy/Z80.c
@@ -0,0 +1,734 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.c                         **/
+/**                                                         **/
+/** This file contains implementation for Z80 CPU. Don't    **/
+/** forget to provide RdZ80(), WrZ80(), InZ80(), OutZ80(),  **/
+/** LoopZ80(), and PatchZ80() functions to accomodate the   **/
+/** emulated machine's architecture.                        **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/   
+/**     changes to this file.                               **/
+/*************************************************************/
+
+#include "platform_config.h"
+#include "Z80.h"
+#include "Tables.h"
+#include <stdio.h>
+
+#include "emuapi.h"
+
+#undef DEBUG
+/** INLINE ***************************************************/
+/** C99 standard has "inline", but older compilers used     **/
+/** __inline for the same purpose.                          **/
+/*************************************************************/
+#ifdef __C99__
+#define INLINE static inline
+#else
+#define INLINE static __inline
+#endif
+
+/** System-Dependent Stuff ***********************************/
+/** This is system-dependent code put here to speed things  **/
+/** up. It has to stay inlined to be fast.                  **/
+/*************************************************************/
+#ifdef COLEM
+#define RdZ80 RDZ80
+extern byte *ROMPage[];
+INLINE byte RdZ80(word A) { return(ROMPage[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef SPECCY
+#define RdZ80 RDZ80
+#define WrZ80 WRZ80
+extern byte *Page[],*ROM;
+INLINE byte RdZ80(word A)        { return(Page[A>>13][A&0x1FFF]); }
+INLINE void WrZ80(word A,byte V) { if(Page[A>>13]<ROM) Page[A>>13][A&0x1FFF]=V; }
+#endif
+
+#ifdef MG
+#define RdZ80 RDZ80
+extern byte *Page[];
+INLINE byte RdZ80(word A) { return(Page[A>>13][A&0x1FFF]); }
+#endif
+
+#ifdef FMSX
+#define FAST_RDOP
+extern byte *RAM[];
+INLINE byte OpZ80(word A) { return(RAM[A>>13][A&0x1FFF]); }
+#endif
+
+/** FAST_RDOP ************************************************/
+/** With this #define not present, RdZ80() should perform   **/
+/** the functions of OpZ80().                               **/
+/*************************************************************/
+#ifndef FAST_RDOP
+#define OpZ80(A) RdZ80(A)
+#endif
+
+#define S(Fl)        R->AF.B.l|=Fl
+#define R(Fl)        R->AF.B.l&=~(Fl)
+#define FLAGS(Rg,Fl) R->AF.B.l=Fl|ZSTable[Rg]
+
+#define M_RLC(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|R->AF.B.l;R->AF.B.l|=PZSTable[Rg]
+#define M_RRC(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R->AF.B.l<<7);R->AF.B.l|=PZSTable[Rg]
+#define M_RL(Rg)       \
+  if(Rg&0x80)          \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg<<1)|(R->AF.B.l&C_FLAG); \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+#define M_RR(Rg)       \
+  if(Rg&0x01)          \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg]|C_FLAG; \
+  }                    \
+  else                 \
+  {                    \
+    Rg=(Rg>>1)|(R->AF.B.l<<7);     \
+    R->AF.B.l=PZSTable[Rg];        \
+  }
+  
+#define M_SLA(Rg)      \
+  R->AF.B.l=Rg>>7;Rg<<=1;R->AF.B.l|=PZSTable[Rg]
+#define M_SRA(Rg)      \
+  R->AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);R->AF.B.l|=PZSTable[Rg]
+
+#define M_SLL(Rg)      \
+  R->AF.B.l=Rg>>7;Rg=(Rg<<1)|0x01;R->AF.B.l|=PZSTable[Rg]
+#define M_SRL(Rg)      \
+  R->AF.B.l=Rg&0x01;Rg>>=1;R->AF.B.l|=PZSTable[Rg]
+
+#define M_BIT(Bit,Rg)  \
+  R->AF.B.l=(R->AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
+
+#define M_SET(Bit,Rg) Rg|=1<<Bit
+#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
+
+#define M_POP(Rg)      \
+  R->Rg.B.l=OpZ80(R->SP.W++);R->Rg.B.h=OpZ80(R->SP.W++)
+#define M_PUSH(Rg)     \
+  WrZ80(--R->SP.W,R->Rg.B.h);WrZ80(--R->SP.W,R->Rg.B.l)
+
+#define M_CALL         \
+  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W++);         \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l); \
+  R->PC.W=J.W; \
+  JumpZ80(J.W)
+
+#define M_JP  J.B.l=OpZ80(R->PC.W++);J.B.h=OpZ80(R->PC.W);R->PC.W=J.W;JumpZ80(J.W)
+#define M_JR  R->PC.W+=(offset)OpZ80(R->PC.W)+1;JumpZ80(R->PC.W)
+#define M_RET R->PC.B.l=OpZ80(R->SP.W++);R->PC.B.h=OpZ80(R->SP.W++);JumpZ80(R->PC.W)
+
+#define M_RST(Ad)      \
+  WrZ80(--R->SP.W,R->PC.B.h);WrZ80(--R->SP.W,R->PC.B.l);R->PC.W=Ad;JumpZ80(Ad)
+
+#define M_LDWORD(Rg)   \
+  R->Rg.B.l=OpZ80(R->PC.W++);R->Rg.B.h=OpZ80(R->PC.W++)
+
+#define M_ADD(Rg)      \
+  J.W=R->AF.B.h+Rg;    \
+  R->AF.B.l=           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|                        \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);               \
+  R->AF.B.h=J.B.l       
+
+#define M_SUB(Rg)      \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);                     \
+  R->AF.B.h=J.B.l
+
+#define M_ADC(Rg)      \
+  J.W=R->AF.B.h+Rg+(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    (~(R->AF.B.h^Rg)&(Rg^J.B.l)&0x80? V_FLAG:0)| \
+    J.B.h|ZSTable[J.B.l]|              \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_SBC(Rg)      \
+  J.W=R->AF.B.h-Rg-(R->AF.B.l&C_FLAG); \
+  R->AF.B.l=                           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG);     \
+  R->AF.B.h=J.B.l
+
+#define M_CP(Rg)       \
+  J.W=R->AF.B.h-Rg;    \
+  R->AF.B.l=           \
+    ((R->AF.B.h^Rg)&(R->AF.B.h^J.B.l)&0x80? V_FLAG:0)| \
+    N_FLAG|-J.B.h|ZSTable[J.B.l]|                      \
+    ((R->AF.B.h^Rg^J.B.l)&H_FLAG)
+
+#define M_AND(Rg) R->AF.B.h&=Rg;R->AF.B.l=H_FLAG|PZSTable[R->AF.B.h]
+#define M_OR(Rg)  R->AF.B.h|=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+#define M_XOR(Rg) R->AF.B.h^=Rg;R->AF.B.l=PZSTable[R->AF.B.h]
+
+#define M_IN(Rg)        \
+  Rg=InZ80(R->BC.W);  \
+  R->AF.B.l=PZSTable[Rg]|(R->AF.B.l&C_FLAG)
+
+#define M_INC(Rg)       \
+  Rg++;                 \
+  R->AF.B.l=            \
+    (R->AF.B.l&C_FLAG)|ZSTable[Rg]|           \
+    (Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
+
+#define M_DEC(Rg)       \
+  Rg--;                 \
+  R->AF.B.l=            \
+    N_FLAG|(R->AF.B.l&C_FLAG)|ZSTable[Rg]| \
+    (Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
+
+#define M_ADDW(Rg1,Rg2) \
+  J.W=(R->Rg1.W+R->Rg2.W)&0xFFFF;                        \
+  R->AF.B.l=                                             \
+    (R->AF.B.l&~(H_FLAG|N_FLAG|C_FLAG))|                 \
+    ((R->Rg1.W^R->Rg2.W^J.W)&0x1000? H_FLAG:0)|          \
+    (((long)R->Rg1.W+(long)R->Rg2.W)&0x10000? C_FLAG:0); \
+  R->Rg1.W=J.W
+
+#define M_ADCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W+R->Rg.W+I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    (((long)R->HL.W+(long)R->Rg.W+(long)I)&0x10000? C_FLAG:0)| \
+    (~(R->HL.W^R->Rg.W)&(R->Rg.W^J.W)&0x8000? V_FLAG:0)|       \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+   
+#define M_SBCW(Rg)      \
+  I=R->AF.B.l&C_FLAG;J.W=(R->HL.W-R->Rg.W-I)&0xFFFF;           \
+  R->AF.B.l=                                                   \
+    N_FLAG|                                                    \
+    (((long)R->HL.W-(long)R->Rg.W-(long)I)&0x10000? C_FLAG:0)| \
+    ((R->HL.W^R->Rg.W)&(R->HL.W^J.W)&0x8000? V_FLAG:0)|        \
+    ((R->HL.W^R->Rg.W^J.W)&0x1000? H_FLAG:0)|                  \
+    (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                            \
+  R->HL.W=J.W
+
+enum Codes
+{
+  NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
+  EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
+  DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
+  JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
+  JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
+  JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
+  JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
+  JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
+  LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
+  LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
+  LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
+  LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
+  LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
+  LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
+  LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
+  LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
+  ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
+  ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
+  SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
+  SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
+  AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
+  XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
+  OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
+  CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
+  RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
+  RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
+  RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
+  RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
+  RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
+  RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
+  RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
+  RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
+};
+
+enum CodesCB
+{
+  RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
+  RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
+  RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
+  RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
+  SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
+  SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
+  SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
+  SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
+  BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
+  BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
+  BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
+  BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
+  BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
+  BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
+  BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
+  BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
+  RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
+  RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
+  RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
+  RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
+  RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
+  RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
+  RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
+  RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
+  SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
+  SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
+  SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
+  SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
+  SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
+  SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
+  SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
+  SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
+};
+  
+enum CodesED
+{
+  DB_00,DB_01,DB_02,DB_03,DB_04,DB_05,DB_06,DB_07,
+  DB_08,DB_09,DB_0A,DB_0B,DB_0C,DB_0D,DB_0E,DB_0F,
+  DB_10,DB_11,DB_12,DB_13,DB_14,DB_15,DB_16,DB_17,
+  DB_18,DB_19,DB_1A,DB_1B,DB_1C,DB_1D,DB_1E,DB_1F,
+  DB_20,DB_21,DB_22,DB_23,DB_24,DB_25,DB_26,DB_27,
+  DB_28,DB_29,DB_2A,DB_2B,DB_2C,DB_2D,DB_2E,DB_2F,
+  DB_30,DB_31,DB_32,DB_33,DB_34,DB_35,DB_36,DB_37,
+  DB_38,DB_39,DB_3A,DB_3B,DB_3C,DB_3D,DB_3E,DB_3F,
+  IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
+  IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,DB_4C,RETI,DB_,LD_R_A,
+  IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,DB_54,DB_55,IM_1,LD_A_I,
+  IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,DB_5C,DB_5D,IM_2,LD_A_R,
+  IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,DB_64,DB_65,DB_66,RRD,
+  IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,DB_6C,DB_6D,DB_6E,RLD,
+  IN_F_xC,DB_71,SBC_HL_SP,LD_xWORDe_SP,DB_74,DB_75,DB_76,DB_77,
+  IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,DB_7C,DB_7D,DB_7E,DB_7F,
+  DB_80,DB_81,DB_82,DB_83,DB_84,DB_85,DB_86,DB_87,
+  DB_88,DB_89,DB_8A,DB_8B,DB_8C,DB_8D,DB_8E,DB_8F,
+  DB_90,DB_91,DB_92,DB_93,DB_94,DB_95,DB_96,DB_97,
+  DB_98,DB_99,DB_9A,DB_9B,DB_9C,DB_9D,DB_9E,DB_9F,
+  LDI,CPI,INI,OUTI,DB_A4,DB_A5,DB_A6,DB_A7,
+  LDD,CPD,IND,OUTD,DB_AC,DB_AD,DB_AE,DB_AF,
+  LDIR,CPIR,INIR,OTIR,DB_B4,DB_B5,DB_B6,DB_B7,
+  LDDR,CPDR,INDR,OTDR,DB_BC,DB_BD,DB_BE,DB_BF,
+  DB_C0,DB_C1,DB_C2,DB_C3,DB_C4,DB_C5,DB_C6,DB_C7,
+  DB_C8,DB_C9,DB_CA,DB_CB,DB_CC,DB_CD,DB_CE,DB_CF,
+  DB_D0,DB_D1,DB_D2,DB_D3,DB_D4,DB_D5,DB_D6,DB_D7,
+  DB_D8,DB_D9,DB_DA,DB_DB,DB_DC,DB_DD,DB_DE,DB_DF,
+  DB_E0,DB_E1,DB_E2,DB_E3,DB_E4,DB_E5,DB_E6,DB_E7,
+  DB_E8,DB_E9,DB_EA,DB_EB,DB_EC,DB_ED,DB_EE,DB_EF,
+  DB_F0,DB_F1,DB_F2,DB_F3,DB_F4,DB_F5,DB_F6,DB_F7,
+  DB_F8,DB_F9,DB_FA,DB_FB,DB_FC,DB_FD,DB_FE,DB_FF
+};
+
+static void CodesCB(register Z80 *R)
+{
+  register byte I;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesCB[I];
+  switch(I)
+  {
+#include "CodesCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (   
+          "[Z80 %lX] Unrecognized instruction: CB %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IX    
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD CB %02X %02X at PC=%04X\n",
+          (long)(R->User),OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesFDCB(register Z80 *R)
+{
+  register pair J;
+  register byte I;
+
+#define XX IY
+  J.W=R->XX.W+(offset)OpZ80(R->PC.W++);
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXXCB[I];
+  switch(I)
+  {
+#include "CodesXCB.h"
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: FD CB %02X %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-2),OpZ80(R->PC.W-1),R->PC.W-4
+        );
+  }
+#undef XX
+}
+
+static void CodesED(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesED[I];
+  switch(I)
+  {
+#include "CodesED.h"
+    case PFX_ED:
+      R->PC.W--;break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: ED %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+}
+
+static void CodesDD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IX
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesDDCB(R);break;
+    default:
+      if(R->TrapBadOps)
+        printf
+        (
+          "[Z80 %lX] Unrecognized instruction: DD %02X at PC=%04X\n",
+          (long)R->User,OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+static void CodesFD(register Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+#define XX IY
+  I=OpZ80(R->PC.W++);
+  R->ICount-=CyclesXX[I];
+  switch(I)
+  {
+#include "CodesXX.h"
+    case PFX_FD:
+    case PFX_DD:
+      R->PC.W--;break;
+    case PFX_CB:
+      CodesFDCB(R);break;
+    default:
+        printf
+        (
+          "Unrecognized instruction: FD %02X at PC=%04X\n",
+          OpZ80(R->PC.W-1),R->PC.W-2
+        );
+  }
+#undef XX
+}
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the register struct  **/
+/** before starting execution with Z80(). It sets the       **/
+/** registers to their supposed initial values.             **/
+/*************************************************************/
+void ResetZ80(Z80 *R, register int Cycles)
+{
+  R->IPeriod  = Cycles;
+  R->PC.W     = 0x0000;
+  R->SP.W     = 0xF000;
+  R->AF.W     = 0x0000;
+  R->BC.W     = 0x0000;
+  R->DE.W     = 0x0000;
+  R->HL.W     = 0x0000;
+  R->AF1.W    = 0x0000;
+  R->BC1.W    = 0x0000;
+  R->DE1.W    = 0x0000;
+  R->HL1.W    = 0x0000;
+  R->IX.W     = 0x0000;
+  R->IY.W     = 0x0000;
+  R->I        = 0x00;
+  R->R        = 0x00;
+  R->IFF      = 0x00;
+  R->ICount   = R->IPeriod;
+  R->IRequest = INT_NONE;
+  R->IBackup  = 0;
+
+  JumpZ80(R->PC.W);
+}
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int ExecZ80(register Z80 *R,register int RunCycles)
+{
+  register byte I;
+  register pair J;
+
+  for(R->ICount=RunCycles;;)
+  {
+    while(R->ICount>0)
+    {
+#ifdef DEBUG
+      /* Turn tracing on when reached trap address */
+      if(R->PC.W==R->Trap) R->Trace=1;
+      /* Call single-step debugger, exit if requested */
+      if(R->Trace)
+        if(!DebugZ80(R)) return(R->ICount);
+#endif
+
+      /* Read opcode and count cycles */
+      I=OpZ80(R->PC.W++);
+      /* Count cycles */
+      R->ICount-=Cycles[I];
+
+      for (int l=0; l< Cycles[I] ;l++) {
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop"); 
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop"); 
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop"); 
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+if ( !emu_IsVga() ) {
+        asm volatile("nop");
+        asm volatile("nop");       
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop"); 
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");      
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop"); 
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");
+        asm volatile("nop");   
+}
+    
+      }
+      /* Interpret opcode */
+      switch(I)
+      {
+#include "Codes.h"
+        case PFX_CB: CodesCB(R);break;
+        case PFX_ED: CodesED(R);break;
+        case PFX_FD: CodesFD(R);break;
+        case PFX_DD: CodesDD(R);break;
+      }
+    }
+
+    /* Unless we have come here after EI, exit */
+    if(!(R->IFF&IFF_EI)) return(R->ICount);
+    else
+    {
+      /* Done with AfterEI state */
+      R->IFF=(R->IFF&~IFF_EI)|IFF_1;
+      /* Restore the ICount */
+      R->ICount+=R->IBackup-1;
+      /* Interrupt CPU if needed */
+      if((R->IRequest!=INT_NONE)&&(R->IRequest!=INT_QUIT)) IntZ80(R,R->IRequest);
+    }
+  }
+}
+#endif /* EXECZ80 */
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(Z80 *R,word Vector)
+{
+  /* If HALTed, take CPU off HALT instruction */
+  if(R->IFF&IFF_HALT) { R->PC.W++;R->IFF&=~IFF_HALT; }
+
+  if((R->IFF&IFF_1)||(Vector==INT_NMI))
+  {
+    /* Save PC on stack */
+    M_PUSH(PC);
+
+    /* Automatically reset IRequest if needed */
+    if(R->IAutoReset&&(Vector==R->IRequest)) R->IRequest=INT_NONE;
+
+    /* If it is NMI... */
+    if(Vector==INT_NMI)
+    {
+      /* Clear IFF1 */
+      R->IFF&=~(IFF_1|IFF_EI);
+      /* Jump to hardwired NMI vector */
+      R->PC.W=0x0066;
+      JumpZ80(0x0066);
+      /* Done */
+      return;
+    }
+
+    /* Further interrupts off */
+    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+
+    /* If in IM2 mode... */
+    if(R->IFF&IFF_IM2)
+    {
+      /* Make up the vector address */
+      Vector=(Vector&0xFF)|((word)(R->I)<<8);
+      /* Read the vector */
+      R->PC.B.l=RdZ80(Vector++);
+      R->PC.B.h=RdZ80(Vector);
+      JumpZ80(R->PC.W);
+      /* Done */
+      return;
+    }
+
+    /* If in IM1 mode, just jump to hardwired IRQ vector */
+    if(R->IFF&IFF_IM1) { R->PC.W=0x0038;JumpZ80(0x0038);return; }
+
+    /* If in IM0 mode... */
+
+    /* Jump to a vector */
+    switch(Vector)
+    {
+      case INT_RST00: R->PC.W=0x0000;JumpZ80(0x0000);break;
+      case INT_RST08: R->PC.W=0x0008;JumpZ80(0x0008);break;
+      case INT_RST10: R->PC.W=0x0010;JumpZ80(0x0010);break;
+      case INT_RST18: R->PC.W=0x0018;JumpZ80(0x0018);break;
+      case INT_RST20: R->PC.W=0x0020;JumpZ80(0x0020);break;
+      case INT_RST28: R->PC.W=0x0028;JumpZ80(0x0028);break;
+      case INT_RST30: R->PC.W=0x0030;JumpZ80(0x0030);break;
+      case INT_RST38: R->PC.W=0x0038;JumpZ80(0x0038);break;
+    }
+  }
+}
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(Z80 *R)
+{
+  register byte I;
+  register pair J;
+
+  for(;;)
+  {
+#ifdef DEBUG
+    /* Turn tracing on when reached trap address */
+    if(R->PC.W==R->Trap) R->Trace=1;
+    /* Call single-step debugger, exit if requested */
+    if(R->Trace)
+      if(!DebugZ80(R)) return(R->PC.W);
+#endif
+
+    I=OpZ80(R->PC.W++);
+    R->ICount-=Cycles[I];
+
+    switch(I)
+    {
+#include "Codes.h"
+      case PFX_CB: CodesCB(R);break;
+      case PFX_ED: CodesED(R);break;
+      case PFX_FD: CodesFD(R);break;
+      case PFX_DD: CodesDD(R);break;
+    }
+ 
+    /* If cycle counter expired... */
+    if(R->ICount<=0)
+    {
+      /* If we have come after EI, get address from IRequest */
+      /* Otherwise, get it from the loop handler             */
+      if(R->IFF&IFF_EI)
+      {
+        R->IFF=(R->IFF&~IFF_EI)|IFF_1; /* Done with AfterEI state */
+        R->ICount+=R->IBackup-1;       /* Restore the ICount      */
+
+        /* Call periodic handler or set pending IRQ */
+        if(R->ICount>0) J.W=R->IRequest;
+        else
+        {
+          J.W=LoopZ80(R);        /* Call periodic handler    */
+          R->ICount+=R->IPeriod; /* Reset the cycle counter  */
+          if(J.W==INT_NONE) J.W=R->IRequest;  /* Pending IRQ */
+        }
+      }
+      else
+      {
+        J.W=LoopZ80(R);          /* Call periodic handler    */
+        R->ICount+=R->IPeriod;   /* Reset the cycle counter  */
+        if(J.W==INT_NONE) J.W=R->IRequest;    /* Pending IRQ */
+      }
+
+      if(J.W==INT_QUIT) return(R->PC.W); /* Exit if INT_QUIT */
+      if(J.W!=INT_NONE) IntZ80(R,J.W);   /* Int-pt if needed */
+    }
+  }
+
+  /* Execution stopped */
+  return(R->PC.W);
+}
+#endif /* !EXECZ80 */
diff --git a/MCUME_pico2/picospeccy/Z80.h b/MCUME_pico2/picospeccy/Z80.h
new file mode 100644
index 0000000..87a6b40
--- /dev/null
+++ b/MCUME_pico2/picospeccy/Z80.h
@@ -0,0 +1,193 @@
+/** Z80: portable Z80 emulator *******************************/
+/**                                                         **/
+/**                           Z80.h                         **/
+/**                                                         **/
+/** This file contains declarations relevant to emulation   **/
+/** of Z80 CPU.                                             **/
+/**                                                         **/
+/** Copyright (C) Marat Fayzullin 1994-2007                 **/
+/**     You are not allowed to distribute this software     **/
+/**     commercially. Please, notify me, if you make any    **/
+/**     changes to this file.                               **/
+/*************************************************************/
+#ifndef Z80_H
+#define Z80_H
+
+ #include <stdint.h>
+
+
+#define  EXECZ80 // run a few cycles
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+                               /* Compilation options:       */
+/* #define DEBUG */            /* Compile debugging version  */
+#define LSB_FIRST         /* Compile for low-endian CPU */
+// #define MSB_FIRST         /* Compile for hi-endian CPU  */
+
+                               /* LoopZ80() may return:      */
+#define INT_RST00   0x00C7     /* RST 00h                    */
+#define INT_RST08   0x00CF     /* RST 08h                    */
+#define INT_RST10   0x00D7     /* RST 10h                    */
+#define INT_RST18   0x00DF     /* RST 18h                    */
+#define INT_RST20   0x00E7     /* RST 20h                    */
+#define INT_RST28   0x00EF     /* RST 28h                    */
+#define INT_RST30   0x00F7     /* RST 30h                    */
+#define INT_RST38   0x00FF     /* RST 38h                    */
+#define INT_IRQ     INT_RST38  /* Default IRQ opcode is FFh  */
+#define INT_NMI     0xFFFD     /* Non-maskable interrupt     */
+#define INT_NONE    0xFFFF     /* No interrupt required      */
+#define INT_QUIT    0xFFFE     /* Exit the emulation         */
+
+                               /* Bits in Z80 F register:    */
+#define S_FLAG      0x80       /* 1: Result negative         */
+#define Z_FLAG      0x40       /* 1: Result is zero          */
+#define H_FLAG      0x10       /* 1: Halfcarry/Halfborrow    */
+#define P_FLAG      0x04       /* 1: Result is even          */
+#define V_FLAG      0x04       /* 1: Overflow occured        */
+#define N_FLAG      0x02       /* 1: Subtraction occured     */
+#define C_FLAG      0x01       /* 1: Carry/Borrow occured    */
+
+                               /* Bits in IFF flip-flops:    */
+#define IFF_1       0x01       /* IFF1 flip-flop             */
+#define IFF_IM1     0x02       /* 1: IM1 mode                */
+#define IFF_IM2     0x04       /* 1: IM2 mode                */
+#define IFF_2       0x08       /* IFF2 flip-flop             */
+#define IFF_EI      0x20       /* 1: EI pending              */
+#define IFF_HALT    0x80       /* 1: CPU HALTed              */
+
+/** Simple Datatypes *****************************************/
+/** NOTICE: sizeof(byte)=1 and sizeof(word)=2               **/
+/*************************************************************/
+#ifndef BYTE_TYPE_DEFINED
+#define BYTE_TYPE_DEFINED
+typedef uint8_t byte;
+#endif
+#ifndef WORD_TYPE_DEFINED
+#define WORD_TYPE_DEFINED
+typedef uint16_t word;
+#endif
+typedef int8_t offset;
+
+/** Structured Datatypes *************************************/
+/** NOTICE: #define LSB_FIRST for machines where least      **/
+/**         signifcant byte goes first.                     **/
+/*************************************************************/
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+
+typedef struct
+{
+  pair AF,BC,DE,HL,IX,IY,PC,SP;       /* Main registers      */
+  pair AF1,BC1,DE1,HL1;               /* Shadow registers    */
+  byte IFF,I;                         /* Interrupt registers */
+  byte R;                             /* Refresh register    */
+
+  int IPeriod,ICount; /* Set IPeriod to number of CPU cycles */
+                      /* between calls to LoopZ80()          */
+  int IBackup;        /* Private, don't touch                */
+  word IRequest;      /* Set to address of pending IRQ       */
+  byte IAutoReset;    /* Set to 1 to autom. reset IRequest   */
+  byte TrapBadOps;    /* Set to 1 to warn of illegal opcodes */
+  word Trap;          /* Set Trap to address to trace from   */
+  byte Trace;         /* Set Trace=1 to start tracing        */
+  void *User;         /* Arbitrary user data (ID,RAM*,etc.)  */
+} Z80;
+
+/** ResetZ80() ***********************************************/
+/** This function can be used to reset the registers before **/
+/** starting execution with RunZ80(). It sets registers to  **/
+/** their initial values.                                   **/
+/*************************************************************/
+void ResetZ80(register Z80 *R, register int Cycles);
+
+/** ExecZ80() ************************************************/
+/** This function will execute given number of Z80 cycles.  **/
+/** It will then return the number of cycles left, possibly **/
+/** negative, and current register values in R.             **/
+/*************************************************************/
+#ifdef EXECZ80
+int ExecZ80(register Z80 *R,register int RunCycles);
+#endif
+
+/** IntZ80() *************************************************/
+/** This function will generate interrupt of given vector.  **/
+/*************************************************************/
+void IntZ80(register Z80 *R,register word Vector);
+
+/** RunZ80() *************************************************/
+/** This function will run Z80 code until an LoopZ80() call **/
+/** returns INT_QUIT. It will return the PC at which        **/
+/** emulation stopped, and current register values in R.    **/
+/*************************************************************/
+#ifndef EXECZ80
+word RunZ80(register Z80 *R);
+#endif
+
+/** RdZ80()/WrZ80() ******************************************/
+/** These functions are called when access to RAM occurs.   **/
+/** They allow to control memory access.                    **/
+/************************************ TO BE WRITTEN BY USER **/
+void WrZ80(register word Addr,register byte Value);
+byte RdZ80(register word Addr);
+
+/** InZ80()/OutZ80() *****************************************/
+/** Z80 emulation calls these functions to read/write from  **/
+/** I/O ports. There can be 65536 I/O ports, but only first **/
+/** 256 are usually used.                                   **/
+/************************************ TO BE WRITTEN BY USER **/
+void OutZ80(register word Port,register byte Value);
+byte InZ80(register word Port);
+
+/** PatchZ80() ***********************************************/
+/** Z80 emulation calls this function when it encounters a  **/
+/** special patch command (ED FE) provided for user needs.  **/
+/** For example, it can be called to emulate BIOS calls,    **/
+/** such as disk and tape access. Replace it with an empty  **/
+/** macro for no patching.                                  **/
+/************************************ TO BE WRITTEN BY USER **/
+void PatchZ80(register Z80 *R);
+
+/** DebugZ80() ***********************************************/
+/** This function should exist if DEBUG is #defined. When   **/
+/** Trace!=0, it is called after each command executed by   **/
+/** the CPU, and given the Z80 registers. Emulation exits   **/
+/** if DebugZ80() returns 0.                                **/
+/*************************************************************/
+#ifdef DEBUG
+byte DebugZ80(register Z80 *R);
+#endif
+
+/** LoopZ80() ************************************************/
+/** Z80 emulation calls this function periodically to check **/
+/** if the system hardware requires any interrupts. This    **/
+/** function must return an address of the interrupt vector **/
+/** (0x0038, 0x0066, etc.) or INT_NONE for no interrupt.    **/
+/** Return INT_QUIT to exit the emulation loop.             **/
+/************************************ TO BE WRITTEN BY USER **/
+word LoopZ80(register Z80 *R);
+
+/** JumpZ80() ************************************************/
+/** Z80 emulation calls this function when it executes a    **/
+/** JP, JR, CALL, RST, or RET. You can use JumpZ80() to     **/
+/** trap these opcodes and switch memory layout.            **/
+/************************************ TO BE WRITTEN BY USER **/
+#ifndef JUMPZ80
+#define JumpZ80(PC)
+#else
+void JumpZ80(word PC);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* Z80_H */
diff --git a/MCUME_pico2/picospeccy/emucfg.h b/MCUME_pico2/picospeccy/emucfg.h
new file mode 100644
index 0000000..036c559
--- /dev/null
+++ b/MCUME_pico2/picospeccy/emucfg.h
@@ -0,0 +1,105 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         16
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    SPECTRUM Emulator"
+#define ROMSDIR "spec"
+
+#define emu_Init(ROM) {spec_Init(); spec_Start(ROM);}
+#define emu_Step(x) {spec_Step();}
+#define emu_Input(x) {spec_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  30,31,32,33,34,35,36,37,38,39,
+  20,26, 8,21,23,28,24,12,18,19,
+   4,22, 7, 9,10,11,13,14,15,40,
+   0,29,27, 6,25, 5,17,16, 0,44,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  30+128,31+128,32+128,33+128,34+128,35+128,36+128,37+128,38+128,39+128,
+  20+128,26+128, 8+128,21+128,23+128,28+128,24+128,12+128,18+128,19+128,
+   4+128,22+128, 7+128, 9+128,10+128,11+128,13+128,14+128,15+128,40+128,
+  0,     29+128,27+128, 6+128,25+128, 5+128,17+128,16+128, 0,44+128,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  30+64,31+64,32+64,33+64,34+64,35+64,36+64,37+64,38+64,39+64,
+  20+64,26+64, 8+64,21+64,23+64,28+64,24+64,12+64,18+64,19+64,
+   4+64,22+64, 7+64, 9+64,10+64,11+64,13+64,14+64,15+64,40+64,
+  0,    29+64,27+64, 6+64,25+64, 5+64,17+64,16+64, 0,44+64,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+/*
+    {25, 6,27,29,224},// vcxz<caps shift=Lshift>
+    {10, 9, 7,22, 4}, // gfdsa
+    {23,21, 8,26,20}, // trewq
+    {34,33,32,31,30}, // 54321
+    {35,36,37,38,39}, // 67890
+    {28,24,12,18,19}, // yuiop
+    {11,13,14,15,40}, // hjkl<enter>
+    { 5,17,16,225,44},// bnm <symbshift=RSHift> <space>
+*/
+
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  20,26,8,21,23,28,24,12,18,19,39+128,
+  0, 4, 22, 7,9, 10,11,13,14,15,40,
+  0,29,27,6,25,5,17,16,16+64,44, 
+  0,0,0,0   //up,left,right,down
+  };  
+
+#define keylables_map2_0 (char *)"1234567890="
+#define keylables_map2_1 (char *)" !@#$%+&*- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  30,31,32,33,34,35,36,37,38,39,15+64,
+  0,30+64,31+64,32+64,33+64,34+64,14+64,35+64,5+64,13+64,0,
+  0, 37+64,38+64,6+64,25+64,19+64,21+64,23+64,17+64,29+64,
+  36+128,34+128,37+128,35+128   //up,left,right,down
+  };  
+
+#define keylables_map3_0 (char *)"QWERTYUIOP "
+#define keylables_map3_1 (char *)" ASDFGHJKL "
+#define keylables_map3_2 (char *)" ZXCVBNM;  "
+const unsigned short key_map3[] = {
+  20+128,26+128,8+128,21+128,23+128,28+128,24+128,12+128,18+128,19+128,0, // Upper case
+  0, 4+128, 22+128, 7+128,9+128, 10+128,11+128,13+128,14+128,15+128,0,
+  0,29+128,27+128,6+128,25+128,5+128,17+128,16+128,18+64,44+128,
+  36+128,34+128,37+128,35+128   //up,left,right,down
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picospeccy/keyboard_osd.h b/MCUME_pico2/picospeccy/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/picospeccy/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/picospeccy/picospeccy.cpp b/MCUME_pico2/picospeccy/picospeccy.cpp
new file mode 100644
index 0000000..fbdbca4
--- /dev/null
+++ b/MCUME_pico2/picospeccy/picospeccy.cpp
@@ -0,0 +1,195 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "spec.h"
+}
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);     
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(140000, true);
+
+//    set_sys_clock_khz(250000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(5, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        //uint16_t bClick = emu_DebounceLocalKeys();
+        //emu_Input(bClick);  
+        emu_Step();        
+    }
+}
+
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;   
+    volatile bool vb=vbl; 
+    while (vbl==vb) {};
+/*
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        volatile bool vb=vbl; 
+        while (vbl==vb) {};
+    }  
+*/
+}
+
+
+/*
+void emu_DrawLine8(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                        
+      tft.writeLine(width,height,line, VBuf);      
+#endif      
+    }
+} 
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA        
+        tft.writeLine16(width,height,line, VBuf);
+#else
+        tft.writeLine(width,height,line, VBuf);
+#endif        
+    }
+}  
+
+void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+#ifdef USE_VGA                
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette8);
+#else
+        tft.writeScreen(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+#endif
+    }
+}
+
+int emu_FrameSkip(void)
+{
+    return skip;
+}
+
+void * emu_LineBuffer(int line)
+{
+    return (void*)tft.getLineBuffer(line);    
+}
+*/
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+#include "hardware/pwm.h"
+void emu_sndInit() {  
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();
+  //gpio_init(AUDIO_PIN);
+  //gpio_set_dir(AUDIO_PIN, GPIO_OUT);     
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+#ifndef CUSTOM_SND 
+  //gpio_put(AUDIO_PIN, (val?1:0));
+  pwm_set_gpio_level(AUDIO_PIN, (val?255:128));
+#endif    
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picospeccy/program_config.h b/MCUME_pico2/picospeccy/program_config.h
new file mode 100644
index 0000000..91f04b3
--- /dev/null
+++ b/MCUME_pico2/picospeccy/program_config.h
@@ -0,0 +1,6 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#define KEYBOARD_ACTIVATED 1
+
+#endif
diff --git a/MCUME_pico2/picospeccy/spec.c b/MCUME_pico2/picospeccy/spec.c
new file mode 100644
index 0000000..81e59cb
--- /dev/null
+++ b/MCUME_pico2/picospeccy/spec.c
@@ -0,0 +1,618 @@
+#include "Z80.h"
+#include "spectrum.rom.h"
+#include "emuapi.h"
+#include "zx_filetyp_z80.h"
+
+#include "AY8910.h"
+#include "kbd.h"
+
+
+#define WIDTH  320
+#define HEIGHT 192
+
+#define CYCLES_PER_FRAME 69888 //3500000/50
+
+#define NBLINES (1) //(48+192+56+16) //(32+256+32)
+#define CYCLES_PER_STEP (CYCLES_PER_FRAME/NBLINES)
+
+typedef struct {
+  int port_ff;      // 0xff = emulate the port,  0x00 alwais 0xFF
+  int ts_lebo;      // left border t states
+  int ts_grap;      // graphic zone t states
+  int ts_ribo;      // right border t states
+  int ts_hore;      // horizontal retrace t states
+  int ts_line;      // to speed the calc, the sum of 4 abobe
+  int line_poin;    // lines in retraze post interrup
+  int line_upbo;    // lines of upper border
+  int line_grap;    // lines of graphic zone = 192
+  int line_bobo;    // lines of bottom border
+  int line_retr;    // lines of the retrace
+  /*
+  int TSTATES_PER_LINE;
+  int TOP_BORDER_LINES;
+  int SCANLINES;
+  int BOTTOM_BORDER_LINES;
+  int tstate_border_left;
+  int tstate_graphic_zone;
+  int tstate_border_right;
+  int hw_model;
+  int int_type;
+  int videopage;
+  int BANKM;
+  int BANK678;
+  */
+} HWOptions ;
+
+static HWOptions hwopt = { 0xFF, 24, 128, 24, 48, 224, 16, 48, 192, 48, 8 };
+//224, 64, 192, 56, 24, 128, 72};
+
+struct { unsigned char R,G,B; } Palette[16] = {
+  {   0,   0,   0},
+  {   0,   0, 205},
+  { 205,   0,   0},
+  { 205,   0, 205},
+  {   0, 205,   0},
+  {   0, 205, 205},
+  { 205, 205,   0},
+  { 212, 212, 212},
+  {   0,   0,   0},
+  {   0,   0, 255},
+  { 255,   0,   0},
+  { 255,   0, 255},
+  {   0, 255,   0},
+  {   0, 255, 255},
+  { 255, 255,   0},
+  { 255, 255, 255}
+};
+
+const byte map_qw[8][5] = {
+    {25, 6,27,29,224}, // vcxz<caps shift=Lshift>
+    {10, 9, 7,22, 4}, // gfdsa
+    {23,21, 8,26,20}, // trewq
+    {34,33,32,31,30}, // 54321
+    {35,36,37,38,39}, // 67890
+    {28,24,12,18,19}, // yuiop
+    {11,13,14,15,40}, // hjkl<enter>
+    { 5,17,16,225,44}, // bnm <symbshift=RSHift> <space>
+};
+
+static byte Z80_RAM[0xC000];                    // 48k RAM
+static Z80 myCPU;
+static byte * volatile VRAM=Z80_RAM;            // What will be displayed. Generally ZX VRAM, can be changed for alt screens.
+
+//extern const byte rom_zx48_rom[];        // 16k ROM
+static byte key_ram[8]={
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}; // Keyboard buffer
+byte out_ram;                            // Output (fe port)
+static byte kempston_ram;                       // Kempston-Joystick Buffer
+
+static int v_border=0;
+static int h_border=32;
+static int bordercolor=0;
+static byte * XBuf=0; 
+
+static int ik;
+static int ihk;
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+#define INV_KEY 0
+
+const int16_t keyboardAsciiConv[] = // Ascii to Spectrum keys
+{
+/* 0x00 */ INV_KEY,
+/* 0x01 */ INV_KEY,
+/* 0x02 */ INV_KEY,
+/* 0x03 */ INV_KEY,
+/* 0x04 */ INV_KEY,
+/* 0x05 */ INV_KEY,
+/* 0x06 */ INV_KEY,
+/* 0x07 */ INV_KEY,
+/* 0x08 */ INV_KEY,
+/* 0x09 */ INV_KEY,   // tab
+/* 0x0A */ INV_KEY,
+/* 0x0B */ INV_KEY,
+/* 0x0C */ INV_KEY,
+/* 0x0D */ 40,        // enter
+/* 0x0E */ INV_KEY,
+/* 0x0F */ INV_KEY,
+/* 0x10 */ INV_KEY,
+/* 0x11 */ INV_KEY,
+/* 0x12 */ INV_KEY,
+/* 0x13 */ INV_KEY,
+/* 0x14 */ INV_KEY,
+/* 0x15 */ INV_KEY,
+/* 0x16 */ INV_KEY,
+/* 0x17 */ INV_KEY,
+/* 0x18 */ INV_KEY,
+/* 0x19 */ INV_KEY,
+/* 0x1A */ INV_KEY,
+/* 0x1B */ INV_KEY,  // esc
+/* 0x1C */ INV_KEY,
+/* 0x1D */ INV_KEY,
+/* 0x1E */ INV_KEY,
+/* 0x1F */ INV_KEY,
+/* 0x20 */ 44,       // space
+/* 0x21 */ 30+64,    // ! exclamation mark
+/* 0x22 */ 19+64,    // " double quote   
+/* 0x23 */ 32+64,    // # dies
+/* 0x24 */ 33+64,    // $ dollar
+/* 0x25 */ 34+64,    // % percent
+/* 0x26 */ 35+64,    // & ampercent
+/* 0x27 */ INV_KEY,  // ' singlequote
+/* 0x28 */ 37+64,    // ( bracket left
+/* 0x29 */ 38+64,    // ) bracket right
+/* 0x2A */ 5+64,     // * mult
+/* 0x2B */ 14+64,    // + plus
+/* 0x2C */ 17+64,    // , comma
+/* 0x2D */ 13+64,    // - minus
+/* 0x2E */ 16+64,    // . period
+/* 0x2F */ 25+64,    // / slash
+/* 0x30 */ 39,       // 0
+/* 0x31 */ 30,       // 1
+/* 0x32 */ 31,       // 2 
+/* 0x33 */ 32,       // 3 
+/* 0x34 */ 33,       // 4
+/* 0x35 */ 34,       // 5
+/* 0x36 */ 35,       // 6
+/* 0x37 */ 36,       // 7
+/* 0x38 */ 37,       // 8
+/* 0x39 */ 38,       // 9
+/* 0x3A */ 29+64,    // : colon
+/* 0x3B */ 18+64,    // ; semi colon
+/* 0x3C */ 21+64,    // <
+/* 0x3D */ 15+64,    // = equal
+/* 0x3E */ 23+64,    // >
+/* 0x3F */ 6+64,     // ?
+/* 0x40 */ 31+64,    // @
+/* 0x41 */ 4+128,    // A
+/* 0x42 */ 5+128,    // B
+/* 0x43 */ 6+128,    // C
+/* 0x44 */ 7+128,    // D
+/* 0x45 */ 8+128,    // E
+/* 0x46 */ 9+128,    // F
+/* 0x47 */ 10+128,   // G
+/* 0x48 */ 11+128,   // H
+/* 0x49 */ 12+128,   // I
+/* 0x4A */ 13+128,   // J
+/* 0x4B */ 14+128,   // K
+/* 0x4C */ 15+128,   // L
+/* 0x4D */ 16+128,   // M
+/* 0x4E */ 17+128,   // N
+/* 0x4F */ 18+128,   // O
+/* 0x50 */ 19+128,   // P
+/* 0x51 */ 20+128,   // Q
+/* 0x52 */ 21+128,   // R
+/* 0x53 */ 22+128,   // S
+/* 0x54 */ 23+128,   // T
+/* 0x55 */ 24+128,   // U
+/* 0x56 */ 25+128,   // V
+/* 0x57 */ 26+128,   // W
+/* 0x58 */ 27+128,   // X
+/* 0x59 */ 28+128,   // Y
+/* 0x5A */ 29+128,   // Z
+/* 0x5B */ INV_KEY,  // square bracket open
+/* 0x5C */ INV_KEY,  // baclslach
+/* 0x5D */ INV_KEY,  // square braquet close
+/* 0x5E */ INV_KEY,  // ^ circonflex
+/* 0x5F */ INV_KEY,  // _ undescore
+/* 0x60 */ INV_KEY,  // `backquote
+/* 0x61 */ 4,        // a
+/* 0x62 */ 5,        // b
+/* 0x63 */ 6,        // c
+/* 0x64 */ 7,        // d
+/* 0x65 */ 8,        // e
+/* 0x66 */ 9,        // f
+/* 0x67 */ 10,       // g
+/* 0x68 */ 11,       // h
+/* 0x69 */ 12,       // i
+/* 0x6A */ 13,       // j
+/* 0x6B */ 14,       // k
+/* 0x6C */ 15,       // l
+/* 0x6D */ 16,       // m
+/* 0x6E */ 17,       // n
+/* 0x6F */ 18,       // o
+/* 0x70 */ 19,       // p
+/* 0x71 */ 20,       // q
+/* 0x72 */ 21,       // r
+/* 0x73 */ 22,       // s
+/* 0x74 */ 23,       // t
+/* 0x75 */ 24,       // u
+/* 0x76 */ 25,       // v
+/* 0x77 */ 26,       // w
+/* 0x78 */ 27,       // x
+/* 0x79 */ 28,       // y
+/* 0x7A */ 29,       // z
+/* 0x7B */ INV_KEY,  // curly bracket open
+/* 0x7C */ INV_KEY,  // or
+/* 0x7D */ INV_KEY,  // curly bracket close  
+/* 0x7E */ INV_KEY,  // tilt
+/* 0x7F */ 39+128,   // backspace
+
+/* 0xC0 */ INV_KEY,
+/* 0xC1 */ INV_KEY,
+/* 0xC2 */ INV_KEY,   // F1
+/* 0xC3 */ INV_KEY,   // F2
+/* 0xC4 */ INV_KEY,   // F3
+/* 0xC5 */ INV_KEY,   // F4
+/* 0xC6 */ INV_KEY,   // F5
+/* 0xC7 */ INV_KEY,   // F6
+/* 0xC8 */ INV_KEY,   // F7
+/* 0xC9 */ INV_KEY,   // F8
+/* 0xCA */ INV_KEY,   // F9
+/* 0xCB */ INV_KEY,   // F10
+/* 0xCC */ INV_KEY,
+/* 0xCD */ INV_KEY,
+/* 0xCE */ INV_KEY,
+/* 0xCF */ INV_KEY,
+/* 0xD0 */ INV_KEY,
+/* 0xD1 */ INV_KEY,
+/* 0xD2 */ INV_KEY,
+/* 0xD3 */ INV_KEY,
+/* 0xD4 */ INV_KEY,   // DEL
+/* 0xD5 */ INV_KEY,
+/* 0xD6 */ INV_KEY,
+/* 0xD7 */ 37+128,    // U
+/* 0xD8 */ 34+128,    // L
+/* 0xD9 */ 35+128,    // R
+/* 0xDA */ 36+128,    // D
+/* 0xDB */ INV_KEY,
+/* 0xDC */ INV_KEY,
+/* 0xDD */ INV_KEY,
+/* 0xDE */ INV_KEY,
+/* 0xDF */ INV_KEY
+};
+
+
+void spec_Input(int bClick) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();
+}
+
+void displayscanline(int y, int f_flash)
+{
+  int x, row, col, dir_p, dir_a, pixeles, tinta, papel, atributos;
+
+  row = y + v_border;    // 4 & 32 = graphical screen offset
+  col = 0;              // 32+256+32=320  4+192+4=200  (res=320x200)
+
+  for (x = 0; x < h_border; x++) {
+    XBuf[col++] = bordercolor;
+  }
+
+  dir_p = ((y & 0xC0) << 5) + ((y & 0x07) << 8) + ((y & 0x38) << 2);
+  dir_a = 0x1800 + (32 * (y >> 3));
+  
+  for (x = 0; x < 32; x++)
+  {
+    pixeles=  VRAM[dir_p++];
+    atributos=VRAM[dir_a++];
+    
+    if (((atributos & 0x80) == 0) || (f_flash == 0))
+    {
+      tinta = (atributos & 0x07) + ((atributos & 0x40) >> 3);
+      papel = (atributos & 0x78) >> 3;
+    }
+    else
+    {
+      papel = (atributos & 0x07) + ((atributos & 0x40) >> 3);
+      tinta = (atributos & 0x78) >> 3;
+    }
+    XBuf[col++] = ((pixeles & 0x80) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x40) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x20) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x10) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x08) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x04) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x02) ? tinta : papel);
+    XBuf[col++] = ((pixeles & 0x01) ? tinta : papel);
+  }
+
+  for (x = 0; x < h_border; x++) {
+    XBuf[col++] = bordercolor;
+  }
+  
+  emu_DrawLinePal16(XBuf, WIDTH, HEIGHT, y);
+}
+
+#ifdef HAS_SND
+#ifdef CUSTOM_SND 
+#define SAMSIZE 32768
+static unsigned char sam[SAMSIZE];
+static int rdsam=0;
+static int wrsam=SAMSIZE/2;
+#endif
+#endif
+
+static int lastBuzzCycle=0;
+static byte lastBuzzVal;
+
+#ifdef HAS_SND
+#ifdef CUSTOM_SND   
+void  SND_Process( short * stream, int len )
+{
+    len = len >> 1;
+    for (int i=0;i<len;i++)
+    {
+      short s = sam[rdsam]?32767:0;
+      rdsam += 180;
+      rdsam &= SAMSIZE-1;
+      *stream++ = (short)(s);
+      *stream++ = (short)(s);
+    }      
+}
+#endif
+#endif 
+
+static void displayScreen(void) {
+  int y;
+  static int f_flash = 1, f_flash2 = 0;
+  f_flash2 = (f_flash2++) % 32;
+  if (f_flash2 < 16)
+    f_flash = 1;
+  else
+    f_flash = 0;
+  
+  for (y = 0; y < HEIGHT; y++)
+    displayscanline (y, f_flash);
+ 
+  emu_DrawVsync();   
+}
+
+
+
+static void InitKeyboard(void){
+  memset(key_ram, 0xff, sizeof(key_ram));   
+}
+
+static void UpdateKeyboard (int asckey)
+{
+  int hk = keyboardAsciiConv[asckey]; 
+  memset(key_ram, 0xff, sizeof(key_ram));    
+  {
+    //if (k & MASK_KEY_USER1) hk = 39;
+    int shift = hk;
+    if (hk >=128) hk -= 128;
+    else if (hk >=64) hk -= 64;    
+    // scan all possibilities
+    for (int j=0;j<8;j++) {
+      for(int i=0;i<5;i++){
+        if ( /*(k == map_qw[j][i]) ||*/ (hk == map_qw[j][i]) ) {
+            key_ram[j] &= ~ (1<<(4-i));
+        }   
+      }  
+    } 
+    if (shift >=128) key_ram[0] &= ~ (1<<0);  // SHift 
+    else if (shift >=64) key_ram[7] &= ~ (1<<1);  // SHift symboles     
+  } 
+}
+
+
+#define MAX_Z80SIZE 49152
+
+
+int endsWith(const char * s, const char * suffix)
+{
+  int retval = 0;
+  int len = strlen(s);
+  int slen = strlen(suffix);
+  if (len > slen ) {
+    if (!strcmp(&s[len-slen], suffix)) {
+      retval = 1;
+    }
+  }
+   return (retval);  
+}
+
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+void spec_Start(char * filename) {
+  memset(Z80_RAM, 0, 0xC000);
+  if ( (endsWith(filename, "SNA")) || (endsWith(filename, "sna")) ) {
+    ZX_ReadFromFlash_SNA(&myCPU, filename); 
+  } 
+  else if ( (endsWith(filename, "Z80")) || (endsWith(filename, "z80")) ) {
+    unsigned char * game = emu_Malloc(MAX_Z80SIZE);
+    int size = emu_LoadFile(filename, game, MAX_Z80SIZE);  
+    ZX_ReadFromFlash_Z80(&myCPU, game,size); 
+    emu_Free(game);  
+  }
+#ifdef HAS_SND
+  emu_sndInit(); 
+#endif  
+}
+
+
+
+static AY8910 ay;
+
+void spec_Init(void) {
+  int J;
+  /* Set up the palette */
+  for(J=0;J<16;J++)
+    emu_SetPaletteEntry(Palette[J].R,Palette[J].G,Palette[J].B, J);
+  
+  InitKeyboard();
+ 
+  Reset8910(&ay,3500000,0);
+
+  
+  if (XBuf == 0) XBuf = (byte *)emu_Malloc(WIDTH);
+  VRAM = Z80_RAM;
+  memset(Z80_RAM, 0, sizeof(Z80_RAM));
+
+  ResetZ80(&myCPU, CYCLES_PER_FRAME);
+#if ALT_Z80CORE  
+  myCPU.RAM = Z80_RAM; 
+  Z80FlagTables();
+#endif      
+}
+
+#include "emuapi.h"
+
+void spec_Step(void) {
+  int scanl;
+  for (scanl = 0; scanl < NBLINES; scanl++) {
+    lastBuzzCycle=0;
+    ExecZ80(&myCPU,CYCLES_PER_STEP); // 3.5MHz ticks for 6 lines @ 30 kHz = 700 cycles
+#ifdef HAS_SND
+#ifdef CUSTOM_SND 
+    buzz(lastBuzzVal, CYCLES_PER_STEP);
+#endif
+#endif    
+    //busy_wait_us(1);
+    //sleep_us(1);
+  }
+
+
+#if ALT_Z80CORE
+#else
+  IntZ80(&myCPU,INT_IRQ); // must be called every 20ms
+#endif
+  displayScreen();
+
+  int k=ik; //emu_GetPad();
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+
+  kempston_ram = 0x00;
+  if (k & MASK_JOY2_BTN)
+          kempston_ram |= 0x10; //Fire
+  if (k & MASK_JOY2_UP)
+          kempston_ram |= 0x8; //Up
+  if (k & MASK_JOY2_DOWN)
+          kempston_ram |= 0x4; //Down
+  if (k & MASK_JOY2_RIGHT)
+          kempston_ram |= 0x2; //Right
+  if (k & MASK_JOY2_LEFT)
+          kempston_ram |= 0x1; //Left
+
+
+  UpdateKeyboard(hk);
+    
+  Loop8910(&ay,20);
+}
+
+
+
+#define BASERAM 0x4000
+
+
+void WrZ80(register word Addr,register byte Value)
+{
+  if (Addr >= BASERAM)
+    Z80_RAM[Addr-BASERAM]=Value;
+}
+
+byte RdZ80(register word Addr)
+{
+  if (Addr<BASERAM) 
+    return rom_zx48_rom[Addr];
+  else
+    return Z80_RAM[Addr-BASERAM];
+}
+
+
+
+void buzz(int val, int currentTstates)
+{
+  int pulse_size = (currentTstates-lastBuzzCycle);
+#ifdef HAS_SND
+#ifdef CUSTOM_SND 
+  for (int i = 0; i<pulse_size; i++ ) {
+    sam[wrsam] = lastBuzzVal?0:1;
+    wrsam += 1;
+    wrsam &= SAMSIZE-1;
+  } 
+
+  lastBuzzCycle = currentTstates;
+  lastBuzzVal = val;  
+#else
+  emu_sndPlayBuzz(pulse_size,val);
+#endif
+#endif    
+}
+
+void OutZ80(register word Port,register byte Value)
+{
+  if ((Port & 0xC002) == 0xC000) {
+    WrCtrl8910(&ay,(Value &0x0F));
+  }  
+  else if ((Port & 0xC002) == 0x8000) {
+    WrData8910(&ay,Value);
+  }    
+  else if (!(Port & 0x01)) {
+    bordercolor = (Value & 0x07);
+    byte mic = (Value & 0x08);
+    byte ear = (Value & 0x10);
+    buzz(((ear)?1:0), CYCLES_PER_STEP-myCPU.ICount);
+  }
+  else if((Port&0xFF)==0xFE) {
+    out_ram=Value; // update it
+  }
+}
+
+byte InZ80(register word port)
+{  
+    if (port == 0xFFFD) {
+      return (RdData8910(&ay));
+    }
+  
+    if((port&0xFF)==0x1F) {
+        // kempston RAM
+        return kempston_ram;
+    }
+
+    if ((port&0xFF)==0xFE) {
+        switch(port>>8) {
+            case 0xFE : return key_ram[0]; break;
+            case 0xFD : return key_ram[1]; break;
+            case 0xFB : return key_ram[2]; break;
+            case 0xF7 : return key_ram[3]; break;
+            case 0xEF : return key_ram[4]; break;
+            case 0xDF : return key_ram[5]; break;
+            case 0xBF : return key_ram[6]; break;
+            case 0x7F : return key_ram[7]; break;
+        }
+    } 
+
+    if ((port & 0xFF) == 0xFF) {  
+      if (hwopt.port_ff == 0xFF) {
+       return 0xFF;        
+      }
+      else {
+       //code = 1;
+       //if (code == 0xFF) code = 0x00;
+       return 1;
+      }
+    }    
+    return 0xFF;
+}
+
+
+void PatchZ80(register Z80 *R)
+{
+  // nothing to do
+}
+
+/*
+word LoopZ80(register Z80 *R)
+{
+  // no interrupt triggered
+  return INT_NONE;
+}
+*/
diff --git a/MCUME_pico2/picospeccy/spec.h b/MCUME_pico2/picospeccy/spec.h
new file mode 100644
index 0000000..449c85b
--- /dev/null
+++ b/MCUME_pico2/picospeccy/spec.h
@@ -0,0 +1,4 @@
+extern void spec_Init(void);
+extern void spec_Step(void);
+extern void spec_Start(char * filename);
+extern void spec_Input(int bClick);
diff --git a/MCUME_pico2/picospeccy/spectrum.rom.h b/MCUME_pico2/picospeccy/spectrum.rom.h
new file mode 100755
index 0000000..1a9f0aa
--- /dev/null
+++ b/MCUME_pico2/picospeccy/spectrum.rom.h
@@ -0,0 +1,1373 @@
+#ifndef SPECTRUM_ROM_H
+#define SPECTRUM_ROM_H
+
+static const unsigned char rom_zx48_rom[] = {
+    0xf3, 0xaf, 0x11, 0xff, 0xff, 0xc3, 0xcb, 0x11, 0x2a, 0x5d, 0x5c, 0x22,
+    0x5f, 0x5c, 0x18, 0x43, 0xc3, 0xf2, 0x15, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x2a, 0x5d, 0x5c, 0x7e, 0xcd, 0x7d, 0x00, 0xd0, 0xcd, 0x74, 0x00, 0x18,
+    0xf7, 0xff, 0xff, 0xff, 0xc3, 0x5b, 0x33, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xc5, 0x2a, 0x61, 0x5c, 0xe5, 0xc3, 0x9e, 0x16, 0xf5, 0xe5, 0x2a, 0x78,
+    0x5c, 0x23, 0x22, 0x78, 0x5c, 0x7c, 0xb5, 0x20, 0x03, 0xfd, 0x34, 0x40,
+    0xc5, 0xd5, 0xcd, 0xbf, 0x02, 0xd1, 0xc1, 0xe1, 0xf1, 0xfb, 0xc9, 0xe1,
+    0x6e, 0xfd, 0x75, 0x00, 0xed, 0x7b, 0x3d, 0x5c, 0xc3, 0xc5, 0x16, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xe5, 0x2a, 0xb0, 0x5c, 0x7c,
+    0xb5, 0x20, 0x01, 0xe9, 0xe1, 0xf1, 0xed, 0x45, 0x2a, 0x5d, 0x5c, 0x23,
+    0x22, 0x5d, 0x5c, 0x7e, 0xc9, 0xfe, 0x21, 0xd0, 0xfe, 0x0d, 0xc8, 0xfe,
+    0x10, 0xd8, 0xfe, 0x18, 0x3f, 0xd8, 0x23, 0xfe, 0x16, 0x38, 0x01, 0x23,
+    0x37, 0x22, 0x5d, 0x5c, 0xc9, 0xbf, 0x52, 0x4e, 0xc4, 0x49, 0x4e, 0x4b,
+    0x45, 0x59, 0xa4, 0x50, 0xc9, 0x46, 0xce, 0x50, 0x4f, 0x49, 0x4e, 0xd4,
+    0x53, 0x43, 0x52, 0x45, 0x45, 0x4e, 0xa4, 0x41, 0x54, 0x54, 0xd2, 0x41,
+    0xd4, 0x54, 0x41, 0xc2, 0x56, 0x41, 0x4c, 0xa4, 0x43, 0x4f, 0x44, 0xc5,
+    0x56, 0x41, 0xcc, 0x4c, 0x45, 0xce, 0x53, 0x49, 0xce, 0x43, 0x4f, 0xd3,
+    0x54, 0x41, 0xce, 0x41, 0x53, 0xce, 0x41, 0x43, 0xd3, 0x41, 0x54, 0xce,
+    0x4c, 0xce, 0x45, 0x58, 0xd0, 0x49, 0x4e, 0xd4, 0x53, 0x51, 0xd2, 0x53,
+    0x47, 0xce, 0x41, 0x42, 0xd3, 0x50, 0x45, 0x45, 0xcb, 0x49, 0xce, 0x55,
+    0x53, 0xd2, 0x53, 0x54, 0x52, 0xa4, 0x43, 0x48, 0x52, 0xa4, 0x4e, 0x4f,
+    0xd4, 0x42, 0x49, 0xce, 0x4f, 0xd2, 0x41, 0x4e, 0xc4, 0x3c, 0xbd, 0x3e,
+    0xbd, 0x3c, 0xbe, 0x4c, 0x49, 0x4e, 0xc5, 0x54, 0x48, 0x45, 0xce, 0x54,
+    0xcf, 0x53, 0x54, 0x45, 0xd0, 0x44, 0x45, 0x46, 0x20, 0x46, 0xce, 0x43,
+    0x41, 0xd4, 0x46, 0x4f, 0x52, 0x4d, 0x41, 0xd4, 0x4d, 0x4f, 0x56, 0xc5,
+    0x45, 0x52, 0x41, 0x53, 0xc5, 0x4f, 0x50, 0x45, 0x4e, 0x20, 0xa3, 0x43,
+    0x4c, 0x4f, 0x53, 0x45, 0x20, 0xa3, 0x4d, 0x45, 0x52, 0x47, 0xc5, 0x56,
+    0x45, 0x52, 0x49, 0x46, 0xd9, 0x42, 0x45, 0x45, 0xd0, 0x43, 0x49, 0x52,
+    0x43, 0x4c, 0xc5, 0x49, 0x4e, 0xcb, 0x50, 0x41, 0x50, 0x45, 0xd2, 0x46,
+    0x4c, 0x41, 0x53, 0xc8, 0x42, 0x52, 0x49, 0x47, 0x48, 0xd4, 0x49, 0x4e,
+    0x56, 0x45, 0x52, 0x53, 0xc5, 0x4f, 0x56, 0x45, 0xd2, 0x4f, 0x55, 0xd4,
+    0x4c, 0x50, 0x52, 0x49, 0x4e, 0xd4, 0x4c, 0x4c, 0x49, 0x53, 0xd4, 0x53,
+    0x54, 0x4f, 0xd0, 0x52, 0x45, 0x41, 0xc4, 0x44, 0x41, 0x54, 0xc1, 0x52,
+    0x45, 0x53, 0x54, 0x4f, 0x52, 0xc5, 0x4e, 0x45, 0xd7, 0x42, 0x4f, 0x52,
+    0x44, 0x45, 0xd2, 0x43, 0x4f, 0x4e, 0x54, 0x49, 0x4e, 0x55, 0xc5, 0x44,
+    0x49, 0xcd, 0x52, 0x45, 0xcd, 0x46, 0x4f, 0xd2, 0x47, 0x4f, 0x20, 0x54,
+    0xcf, 0x47, 0x4f, 0x20, 0x53, 0x55, 0xc2, 0x49, 0x4e, 0x50, 0x55, 0xd4,
+    0x4c, 0x4f, 0x41, 0xc4, 0x4c, 0x49, 0x53, 0xd4, 0x4c, 0x45, 0xd4, 0x50,
+    0x41, 0x55, 0x53, 0xc5, 0x4e, 0x45, 0x58, 0xd4, 0x50, 0x4f, 0x4b, 0xc5,
+    0x50, 0x52, 0x49, 0x4e, 0xd4, 0x50, 0x4c, 0x4f, 0xd4, 0x52, 0x55, 0xce,
+    0x53, 0x41, 0x56, 0xc5, 0x52, 0x41, 0x4e, 0x44, 0x4f, 0x4d, 0x49, 0x5a,
+    0xc5, 0x49, 0xc6, 0x43, 0x4c, 0xd3, 0x44, 0x52, 0x41, 0xd7, 0x43, 0x4c,
+    0x45, 0x41, 0xd2, 0x52, 0x45, 0x54, 0x55, 0x52, 0xce, 0x43, 0x4f, 0x50,
+    0xd9, 0x42, 0x48, 0x59, 0x36, 0x35, 0x54, 0x47, 0x56, 0x4e, 0x4a, 0x55,
+    0x37, 0x34, 0x52, 0x46, 0x43, 0x4d, 0x4b, 0x49, 0x38, 0x33, 0x45, 0x44,
+    0x58, 0x0e, 0x4c, 0x4f, 0x39, 0x32, 0x57, 0x53, 0x5a, 0x20, 0x0d, 0x50,
+    0x30, 0x31, 0x51, 0x41, 0xe3, 0xc4, 0xe0, 0xe4, 0xb4, 0xbc, 0xbd, 0xbb,
+    0xaf, 0xb0, 0xb1, 0xc0, 0xa7, 0xa6, 0xbe, 0xad, 0xb2, 0xba, 0xe5, 0xa5,
+    0xc2, 0xe1, 0xb3, 0xb9, 0xc1, 0xb8, 0x7e, 0xdc, 0xda, 0x5c, 0xb7, 0x7b,
+    0x7d, 0xd8, 0xbf, 0xae, 0xaa, 0xab, 0xdd, 0xde, 0xdf, 0x7f, 0xb5, 0xd6,
+    0x7c, 0xd5, 0x5d, 0xdb, 0xb6, 0xd9, 0x5b, 0xd7, 0x0c, 0x07, 0x06, 0x04,
+    0x05, 0x08, 0x0a, 0x0b, 0x09, 0x0f, 0xe2, 0x2a, 0x3f, 0xcd, 0xc8, 0xcc,
+    0xcb, 0x5e, 0xac, 0x2d, 0x2b, 0x3d, 0x2e, 0x2c, 0x3b, 0x22, 0xc7, 0x3c,
+    0xc3, 0x3e, 0xc5, 0x2f, 0xc9, 0x60, 0xc6, 0x3a, 0xd0, 0xce, 0xa8, 0xca,
+    0xd3, 0xd4, 0xd1, 0xd2, 0xa9, 0xcf, 0x2e, 0x2f, 0x11, 0xff, 0xff, 0x01,
+    0xfe, 0xfe, 0xed, 0x78, 0x2f, 0xe6, 0x1f, 0x28, 0x0e, 0x67, 0x7d, 0x14,
+    0xc0, 0xd6, 0x08, 0xcb, 0x3c, 0x30, 0xfa, 0x53, 0x5f, 0x20, 0xf4, 0x2d,
+    0xcb, 0x00, 0x38, 0xe6, 0x7a, 0x3c, 0xc8, 0xfe, 0x28, 0xc8, 0xfe, 0x19,
+    0xc8, 0x7b, 0x5a, 0x57, 0xfe, 0x18, 0xc9, 0xcd, 0x8e, 0x02, 0xc0, 0x21,
+    0x00, 0x5c, 0xcb, 0x7e, 0x20, 0x07, 0x23, 0x35, 0x2b, 0x20, 0x02, 0x36,
+    0xff, 0x7d, 0x21, 0x04, 0x5c, 0xbd, 0x20, 0xee, 0xcd, 0x1e, 0x03, 0xd0,
+    0x21, 0x00, 0x5c, 0xbe, 0x28, 0x2e, 0xeb, 0x21, 0x04, 0x5c, 0xbe, 0x28,
+    0x27, 0xcb, 0x7e, 0x20, 0x04, 0xeb, 0xcb, 0x7e, 0xc8, 0x5f, 0x77, 0x23,
+    0x36, 0x05, 0x23, 0x3a, 0x09, 0x5c, 0x77, 0x23, 0xfd, 0x4e, 0x07, 0xfd,
+    0x56, 0x01, 0xe5, 0xcd, 0x33, 0x03, 0xe1, 0x77, 0x32, 0x08, 0x5c, 0xfd,
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+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x10, 0x00, 0x00, 0x24, 0x24, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x7e, 0x24, 0x24, 0x7e, 0x24, 0x00,
+    0x00, 0x08, 0x3e, 0x28, 0x3e, 0x0a, 0x3e, 0x08, 0x00, 0x62, 0x64, 0x08,
+    0x10, 0x26, 0x46, 0x00, 0x00, 0x10, 0x28, 0x10, 0x2a, 0x44, 0x3a, 0x00,
+    0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x08,
+    0x08, 0x08, 0x04, 0x00, 0x00, 0x20, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00,
+    0x00, 0x00, 0x14, 0x08, 0x3e, 0x08, 0x14, 0x00, 0x00, 0x00, 0x08, 0x08,
+    0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,
+    0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x02, 0x04, 0x08, 0x10, 0x20, 0x00,
+    0x00, 0x3c, 0x46, 0x4a, 0x52, 0x62, 0x3c, 0x00, 0x00, 0x18, 0x28, 0x08,
+    0x08, 0x08, 0x3e, 0x00, 0x00, 0x3c, 0x42, 0x02, 0x3c, 0x40, 0x7e, 0x00,
+    0x00, 0x3c, 0x42, 0x0c, 0x02, 0x42, 0x3c, 0x00, 0x00, 0x08, 0x18, 0x28,
+    0x48, 0x7e, 0x08, 0x00, 0x00, 0x7e, 0x40, 0x7c, 0x02, 0x42, 0x3c, 0x00,
+    0x00, 0x3c, 0x40, 0x7c, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x7e, 0x02, 0x04,
+    0x08, 0x10, 0x10, 0x00, 0x00, 0x3c, 0x42, 0x3c, 0x42, 0x42, 0x3c, 0x00,
+    0x00, 0x3c, 0x42, 0x42, 0x3e, 0x02, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x10,
+    0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x10, 0x20,
+    0x00, 0x00, 0x04, 0x08, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x3e,
+    0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x10, 0x08, 0x04, 0x08, 0x10, 0x00,
+    0x00, 0x3c, 0x42, 0x04, 0x08, 0x00, 0x08, 0x00, 0x00, 0x3c, 0x4a, 0x56,
+    0x5e, 0x40, 0x3c, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x00,
+    0x00, 0x7c, 0x42, 0x7c, 0x42, 0x42, 0x7c, 0x00, 0x00, 0x3c, 0x42, 0x40,
+    0x40, 0x42, 0x3c, 0x00, 0x00, 0x78, 0x44, 0x42, 0x42, 0x44, 0x78, 0x00,
+    0x00, 0x7e, 0x40, 0x7c, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x7e, 0x40, 0x7c,
+    0x40, 0x40, 0x40, 0x00, 0x00, 0x3c, 0x42, 0x40, 0x4e, 0x42, 0x3c, 0x00,
+    0x00, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x42, 0x00, 0x00, 0x3e, 0x08, 0x08,
+    0x08, 0x08, 0x3e, 0x00, 0x00, 0x02, 0x02, 0x02, 0x42, 0x42, 0x3c, 0x00,
+    0x00, 0x44, 0x48, 0x70, 0x48, 0x44, 0x42, 0x00, 0x00, 0x40, 0x40, 0x40,
+    0x40, 0x40, 0x7e, 0x00, 0x00, 0x42, 0x66, 0x5a, 0x42, 0x42, 0x42, 0x00,
+    0x00, 0x42, 0x62, 0x52, 0x4a, 0x46, 0x42, 0x00, 0x00, 0x3c, 0x42, 0x42,
+    0x42, 0x42, 0x3c, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x7c, 0x40, 0x40, 0x00,
+    0x00, 0x3c, 0x42, 0x42, 0x52, 0x4a, 0x3c, 0x00, 0x00, 0x7c, 0x42, 0x42,
+    0x7c, 0x44, 0x42, 0x00, 0x00, 0x3c, 0x40, 0x3c, 0x02, 0x42, 0x3c, 0x00,
+    0x00, 0xfe, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x42, 0x42, 0x42,
+    0x42, 0x42, 0x3c, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, 0x00,
+    0x00, 0x42, 0x42, 0x42, 0x42, 0x5a, 0x24, 0x00, 0x00, 0x42, 0x24, 0x18,
+    0x18, 0x24, 0x42, 0x00, 0x00, 0x82, 0x44, 0x28, 0x10, 0x10, 0x10, 0x00,
+    0x00, 0x7e, 0x04, 0x08, 0x10, 0x20, 0x7e, 0x00, 0x00, 0x0e, 0x08, 0x08,
+    0x08, 0x08, 0x0e, 0x00, 0x00, 0x00, 0x40, 0x20, 0x10, 0x08, 0x04, 0x00,
+    0x00, 0x70, 0x10, 0x10, 0x10, 0x10, 0x70, 0x00, 0x00, 0x10, 0x38, 0x54,
+    0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
+    0x00, 0x1c, 0x22, 0x78, 0x20, 0x20, 0x7e, 0x00, 0x00, 0x00, 0x38, 0x04,
+    0x3c, 0x44, 0x3c, 0x00, 0x00, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x3c, 0x00,
+    0x00, 0x00, 0x1c, 0x20, 0x20, 0x20, 0x1c, 0x00, 0x00, 0x04, 0x04, 0x3c,
+    0x44, 0x44, 0x3c, 0x00, 0x00, 0x00, 0x38, 0x44, 0x78, 0x40, 0x3c, 0x00,
+    0x00, 0x0c, 0x10, 0x18, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x3c, 0x44,
+    0x44, 0x3c, 0x04, 0x38, 0x00, 0x40, 0x40, 0x78, 0x44, 0x44, 0x44, 0x00,
+    0x00, 0x10, 0x00, 0x30, 0x10, 0x10, 0x38, 0x00, 0x00, 0x04, 0x00, 0x04,
+    0x04, 0x04, 0x24, 0x18, 0x00, 0x20, 0x28, 0x30, 0x30, 0x28, 0x24, 0x00,
+    0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0c, 0x00, 0x00, 0x00, 0x68, 0x54,
+    0x54, 0x54, 0x54, 0x00, 0x00, 0x00, 0x78, 0x44, 0x44, 0x44, 0x44, 0x00,
+    0x00, 0x00, 0x38, 0x44, 0x44, 0x44, 0x38, 0x00, 0x00, 0x00, 0x78, 0x44,
+    0x44, 0x78, 0x40, 0x40, 0x00, 0x00, 0x3c, 0x44, 0x44, 0x3c, 0x04, 0x06,
+    0x00, 0x00, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x38, 0x40,
+    0x38, 0x04, 0x78, 0x00, 0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x0c, 0x00,
+    0x00, 0x00, 0x44, 0x44, 0x44, 0x44, 0x38, 0x00, 0x00, 0x00, 0x44, 0x44,
+    0x28, 0x28, 0x10, 0x00, 0x00, 0x00, 0x44, 0x54, 0x54, 0x54, 0x28, 0x00,
+    0x00, 0x00, 0x44, 0x28, 0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x44, 0x44,
+    0x44, 0x3c, 0x04, 0x38, 0x00, 0x00, 0x7c, 0x08, 0x10, 0x20, 0x7c, 0x00,
+    0x00, 0x0e, 0x08, 0x30, 0x08, 0x08, 0x0e, 0x00, 0x00, 0x08, 0x08, 0x08,
+    0x08, 0x08, 0x08, 0x00, 0x00, 0x70, 0x10, 0x0c, 0x10, 0x10, 0x70, 0x00,
+    0x00, 0x14, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x42, 0x99, 0xa1,
+    0xa1, 0x99, 0x42, 0x3c
+};
+
+#endif
diff --git a/MCUME_pico2/picospeccy/zx_filetyp_z80.c b/MCUME_pico2/picospeccy/zx_filetyp_z80.c
new file mode 100644
index 0000000..dfaf994
--- /dev/null
+++ b/MCUME_pico2/picospeccy/zx_filetyp_z80.c
@@ -0,0 +1,347 @@
+//--------------------------------------------------------------
+// File derived from: 
+// Datum    : 27.01.2014
+// Version  : 1.0
+// Autor    : UB
+// EMail    : mc-4u(@)t-online.de
+// Web      : www.mikrocontroller-4u.de
+//--------------------------------------------------------------
+#include "zx_filetyp_z80.h"
+//#include "emuapi.h"
+
+//-------------------------------------------------------------
+extern uint8_t out_ram;
+
+//--------------------------------------------------------------
+// interne Funktionen
+//--------------------------------------------------------------
+const uint8_t* p_decompFlashBlock(const uint8_t *block_adr);
+
+
+void ZX_ReadFromFlash_SNA(Z80 *regs, const char * filename)
+{
+  uint8_t snafile[27];
+  if (emu_FileOpen(filename)) {
+    if (emu_FileRead(&snafile[0], sizeof(snafile)) == sizeof(snafile)) {
+      // Load Z80 registers from SNA
+      regs->I        = snafile[ 0];
+      regs->HL1.B.l  = snafile[ 1];
+      regs->HL1.B.h  = snafile[ 2];
+      regs->DE1.B.l  = snafile[ 3];
+      regs->DE1.B.h  = snafile[ 4];
+      regs->BC1.B.l  = snafile[ 5];
+      regs->BC1.B.h  = snafile[ 6];
+      regs->AF1.B.l  = snafile[ 7];
+      regs->AF1.B.h  = snafile[ 8];
+      regs->HL.B.l   = snafile[ 9];
+      regs->HL.B.h   = snafile[10];
+      regs->DE.B.l   = snafile[11];
+      regs->DE.B.h   = snafile[12];
+      regs->BC.B.l   = snafile[13];
+      regs->BC.B.h   = snafile[14];
+      regs->IY.B.l = snafile[15];
+      regs->IY.B.h = snafile[16];
+      regs->IX.B.l = snafile[17];
+      regs->IX.B.h = snafile[18];
+ //#define IFF_1       0x01       /* IFF1 flip-flop             */
+//#define IFF_IM1     0x02       /* 1: IM1 mode                */
+//#define IFF_IM2     0x04       /* 1: IM2 mode                */
+//#define IFF_2       0x08       /* IFF2 flip-flop             */
+//#define IFF_EI      0x20       /* 1: EI pending              */
+//#define IFF_HALT    0x80       /* 1: CPU HALTed              */
+      regs->R = snafile[20]; //R.W
+      regs->AF.B.l = snafile[21];
+      regs->AF.B.h = snafile[22];
+      regs->SP.B.l =snafile[23];
+      regs->SP.B.h =snafile[24];
+      regs->IFF = 0;
+      regs->IFF |= (((snafile[19]&0x04) >>2)?IFF_1:0); //regs->IFF1 = regs->IFF2 = ...
+      regs->IFF |= (((snafile[19]&0x04) >>2)?IFF_2:0);
+      regs->IFF |= (snafile[25]<< 1); // regs->IM = snafile[25];
+      //regs->BorderColor = snafile[26];
+
+      
+
+      // load RAM from SNA
+      int direc;
+      uint8_t b;
+      for (direc=0;direc!=0xbfff;direc++)
+      {
+        emu_FileRead(&b, 1);
+        WrZ80(direc+0x4000, b);
+      }
+      emu_FileClose();
+      // SP to PC for SNA run
+      regs->PC.B.l = RdZ80(regs->SP.W);
+      regs->SP.W++;
+      regs->PC.B.h = RdZ80(regs->SP.W);
+      regs->SP.W++;                    
+    }  
+  }
+}
+
+//--------------------------------------------------------------
+// Unpack data from a file ( type = * .Z80 ) from flash
+// And copy them to the memory of the ZX - Spectrum
+//
+// Data = pointer to the start of data
+// Length = number of bytes
+//--------------------------------------------------------------
+void ZX_ReadFromFlash_Z80(Z80 *R, const uint8_t *data, uint16_t length)
+{
+  const uint8_t *ptr;
+  const uint8_t *akt_block,*next_block;
+  uint8_t value1,value2;
+  uint8_t flag_version=0;
+  uint8_t flag_compressed=0;
+  uint16_t header_len;
+  uint16_t cur_addr;
+
+  if(length==0) return;
+  if(length>0xC020) return;
+
+  //----------------------------------
+  // parsing header
+  // Byte : [0...29]
+  //----------------------------------
+
+  // Set pointer to data beginning
+  ptr=data;
+
+  R->AF.B.h=*(ptr++); // A [0]
+  R->AF.B.l=*(ptr++); // F [1]
+  R->BC.B.l=*(ptr++); // C [2]
+  R->BC.B.h=*(ptr++); // B [3]
+  R->HL.B.l=*(ptr++); // L [4]
+  R->HL.B.h=*(ptr++); // H [5]
+
+  // PC [6+7]
+  value1=*(ptr++); 
+  value2=*(ptr++);
+  R->PC.W=(value2<<8)|value1;
+  if(R->PC.W==0x0000) {
+    flag_version=1;
+  }
+  else {
+    flag_version=0;
+  } 
+
+  // SP [8+9]
+  value1=*(ptr++);
+  value2=*(ptr++);
+  R->SP.W=(value2<<8)|value1;
+
+  R->I=*(ptr++); // I [10]
+  R->R=*(ptr++); // R [11]
+  
+  // Comressed-Flag & Border [12]
+  value1=*(ptr++); 
+  value2=((value1&0x0E)>>1);
+  OutZ80(0xFE, value2); // BorderColor
+  if((value1&0x20)!=0) {
+    flag_compressed=1;
+  } else {
+    flag_compressed=0;
+  }
+
+  R->DE.B.l=*(ptr++); // E [13]
+  R->DE.B.h=*(ptr++); // D [14]
+  R->BC1.B.l=*(ptr++); // C1 [15]
+  R->BC1.B.h=*(ptr++); // B1 [16]
+  R->DE1.B.l=*(ptr++); // E1 [17]
+  R->DE1.B.h=*(ptr++); // D1 [18]
+  R->HL1.B.l=*(ptr++); // L1 [19]
+  R->HL1.B.h=*(ptr++); // H1 [20]
+  R->AF1.B.h=*(ptr++); // A1 [21]
+  R->AF1.B.l=*(ptr++); // F1 [22]
+  R->IY.B.l=*(ptr++); // Y [23]
+  R->IY.B.h=*(ptr++); // I [24]
+  R->IX.B.l=*(ptr++); // X [25]
+  R->IX.B.h=*(ptr++); // I [26]
+
+  // Interrupt-Flag [27]
+  value1=*(ptr++); 
+  if(value1!=0) {
+    // EI
+    R->IFF|=IFF_2|IFF_EI;
+  }
+  else {
+    // DI
+    R->IFF&=~(IFF_1|IFF_2|IFF_EI);
+  }
+  value1=*(ptr++); // nc [28]
+  // Interrupt-Mode [29]
+  value1=*(ptr++);  
+  if((value1&0x01)!=0) {
+    R->IFF|=IFF_IM1;
+  }
+  else {
+    R->IFF&=~IFF_IM1;
+  }
+  if((value1&0x02)!=0) {
+    R->IFF|=IFF_IM2;
+  }
+  else {
+    R->IFF&=~IFF_IM2;
+  }
+  
+  // restliche Register
+  R->ICount   = R->IPeriod;
+  R->IRequest = INT_NONE; 
+  R->IBackup  = 0;
+
+  //----------------------------------
+  // save the data in RAM
+  // Byte : [30...n]
+  //----------------------------------
+
+  cur_addr=0x4000; // RAM start
+  
+
+  if(flag_version==0) {
+    //-----------------------
+    // old Version
+    //-----------------------
+    if(flag_compressed==1) {
+      //-----------------------
+      // compressed
+      //-----------------------      
+      while(ptr<(data+length)) {
+        value1=*(ptr++);
+        if(value1!=0xED) {
+          WrZ80(cur_addr++, value1);
+        }
+        else {
+          value2=*(ptr++);
+          if(value2!=0xED) { 
+            WrZ80(cur_addr++, value1);
+            WrZ80(cur_addr++, value2);
+          }
+          else {
+            value1=*(ptr++);
+            value2=*(ptr++);
+            while(value1--) {
+              WrZ80(cur_addr++, value2);
+            }
+          }
+        }
+      }
+    }
+    else {
+      //-----------------------
+      // raw (uncompressed)
+      //-----------------------
+      while(ptr<(data+length)) {
+        value1=*(ptr++);
+        WrZ80(cur_addr++, value1);
+      }
+    }
+  }
+  else {
+    //-----------------------
+    // new Version
+    //-----------------------
+    // Header Laenge [30+31]
+    value1=*(ptr++); 
+    value2=*(ptr++);
+    header_len=(value2<<8)|value1;
+    akt_block=(uint8_t*)(ptr+header_len); 
+    // PC [32+33]
+    value1=*(ptr++); 
+    value2=*(ptr++);
+    R->PC.W=(value2<<8)|value1;
+    
+    //------------------------
+    // 1st block parsing
+    //------------------------
+    next_block=p_decompFlashBlock(akt_block);
+    //------------------------
+    // all other parsing
+    //------------------------
+    while(next_block<data+length) {
+      akt_block=next_block;
+      next_block=p_decompFlashBlock(akt_block); 
+    } 
+  }
+}
+
+
+//--------------------------------------------------------------
+// Internal function
+// Unpack and store a block of data
+// ( From flash ) the new version
+//--------------------------------------------------------------
+const uint8_t* p_decompFlashBlock(const uint8_t *block_adr)
+{
+  const uint8_t *ptr;
+  const uint8_t *next_block;
+  uint8_t value1,value2;
+  uint16_t block_len;
+  uint8_t flag_compressed=0;
+  uint8_t flag_page=0;
+  uint16_t cur_addr=0;
+
+  // pointer auf Blockanfang setzen
+  ptr=block_adr;
+
+  // Laenge vom Block
+  value1=*(ptr++);
+  value2=*(ptr++);
+  block_len=(value2<<8)|value1;
+  if(block_len==0xFFFF) {
+    block_len=0x4000;
+    flag_compressed=0;
+  }
+  else {
+    flag_compressed=1;
+  }
+ 
+  // Page vom Block
+  flag_page=*(ptr++);
+  
+  // next Block ausrechnen
+  next_block=(uint8_t*)(ptr+block_len); 
+
+  // Startadresse setzen
+  if(flag_page==4) cur_addr=0x8000;
+  if(flag_page==5) cur_addr=0xC000;
+  if(flag_page==8) cur_addr=0x4000;
+
+  if(flag_compressed==1) {
+    //-----------------------
+    // komprimiert
+    //-----------------------
+    while(ptr<(block_adr+3+block_len)) {
+      value1=*(ptr++);
+      if(value1!=0xED) {
+        WrZ80(cur_addr++, value1);
+      }
+      else {
+        value2=*(ptr++);
+        if(value2!=0xED) { 
+          WrZ80(cur_addr++, value1);
+          WrZ80(cur_addr++, value2);
+        }
+        else {
+          value1=*(ptr++);
+          value2=*(ptr++);
+          while(value1--) {
+            WrZ80(cur_addr++, value2);
+          }
+        }
+      }
+    }
+  }
+  else {
+    //-----------------------
+    // nicht komprimiert
+    //-----------------------
+    while(ptr<(block_adr+3+block_len)) {
+      value1=*(ptr++); 
+      WrZ80(cur_addr++, value1);  
+    }
+  }
+
+  return(next_block); 
+}
+
diff --git a/MCUME_pico2/picospeccy/zx_filetyp_z80.h b/MCUME_pico2/picospeccy/zx_filetyp_z80.h
new file mode 100644
index 0000000..530c1f6
--- /dev/null
+++ b/MCUME_pico2/picospeccy/zx_filetyp_z80.h
@@ -0,0 +1,6 @@
+#pragma once
+#include "Z80.h"
+
+void ZX_ReadFromFlash_SNA(Z80 *R, const char * filename);
+void ZX_ReadFromFlash_Z80(Z80 *R, const uint8_t *data, uint16_t length);
+
diff --git a/MCUME_pico2/picovcs/At2600.c b/MCUME_pico2/picovcs/At2600.c
new file mode 100644
index 0000000..b70b117
--- /dev/null
+++ b/MCUME_pico2/picovcs/At2600.c
@@ -0,0 +1,22 @@
+
+#include "Atari2600EmulatorGlobals.h"
+
+// indicates if the emulator thread is running or not
+int bThreadRunning = 0;
+
+//------------------------
+// options
+//------------------------
+byte nOptions_SkipFrames = 1;
+//int nOptions_SoundBufSize = 768;
+int nOptions_SoundOn = 1;
+//int nOptions_SoundSampleRate = 2;
+//int nOptions_SoundVolume=50;
+//int nOptions_SoundCreateRate = 341;
+int nOptions_Interlace = 0;
+int nOptions_Landscape = 0;
+int nOptions_Color = 1;
+int nOptions_P1Diff=1;
+int nOptions_P2Diff=1;
+extern int pausing = 0;
+
diff --git a/MCUME_pico2/picovcs/Atari2600EmulatorGlobals.h b/MCUME_pico2/picovcs/Atari2600EmulatorGlobals.h
new file mode 100644
index 0000000..26c2b94
--- /dev/null
+++ b/MCUME_pico2/picovcs/Atari2600EmulatorGlobals.h
@@ -0,0 +1,20 @@
+#ifndef Atari2600EmulatorGLOBALS_H
+#define Atari2600EmulatorGLOBALS_H
+
+#include "types.h"
+
+extern int bThreadRunning;
+
+extern int nOptions_SoundSampleRate;
+extern int nOptions_SoundCreateRate;
+extern int nOptions_SoundVolume;
+extern byte nOptions_SkipFrames;
+extern int nOptions_SoundBufSize;
+extern int nOptions_SoundOn;
+extern int nOptions_Interlace;
+extern int nOptions_Landscape;
+extern int nOptions_Color;
+extern int nOptions_P1Diff;
+extern int nOptions_P2Diff;
+
+#endif
diff --git a/MCUME_pico2/picovcs/Collision.c b/MCUME_pico2/picovcs/Collision.c
new file mode 100644
index 0000000..a4b1f3b
--- /dev/null
+++ b/MCUME_pico2/picovcs/Collision.c
@@ -0,0 +1,116 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: collision.c,v 1.10 1997/11/22 14:27:47 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* The 2600 collision detection code */
+
+#include <stdlib.h>
+
+#include "types.h"
+#include "address.h"
+#include "vmachine.h"
+#include "col_mask.h"
+#include "collision.h"
+
+#include "emuapi.h"
+
+/*
+   There are 6 different objects on the screen. Each takes one bit of the 
+   collision vector.
+   Bit 0: Player 0
+   Bit 1: Player 1
+   Bit 2: Missile 0
+   Bit 3: Missile 1
+   Bit 4: Ball
+   Bit 5: Playfield
+ */
+
+/* The collision vector */
+BYTE *colvect=0;
+
+/* The collision lookup table */
+unsigned short col_table[256];
+
+/* The collision state */
+unsigned short col_state;
+
+/* Resets the collision registers of the tia */
+__inline void
+reset_collisions (void)
+{
+  col_state=0;
+}
+
+/* Does collision testing on the pixel b */
+/* b: byte to test for collisions */
+/* Used to build up the collision table */
+int
+set_collisions (BYTE b)
+{
+  int res=0;
+
+  if ((b & ML0_MASK) && (b & PL1_MASK))
+    res |= M0P1_MASK;
+  if ((b & ML0_MASK) && (b & PL0_MASK))
+    res |= M0P0_MASK;
+  if ((b & ML1_MASK) && (b & PL0_MASK))
+    res |=  M1P0_MASK;
+  if ((b & ML1_MASK) && (b & PL1_MASK))
+    res |=  M1P1_MASK;
+
+  if ((b & PL0_MASK) && (b & PF_MASK))
+    res |= P0PF_MASK; 
+  if ((b & PL0_MASK) && (b & BL_MASK))
+    res |= P0BL_MASK;
+  if ((b & PL1_MASK) && (b & PF_MASK))
+    res |= P1PF_MASK ;
+  if ((b & PL1_MASK) && (b & BL_MASK))
+    res |= P1BL_MASK;
+
+  if ((b & ML0_MASK) && (b & PF_MASK))
+    res |=  M0PF_MASK;
+  if ((b & ML0_MASK) && (b & BL_MASK))
+    res |= M0BL_MASK;
+  if ((b & ML1_MASK) && (b & PF_MASK))
+    res |=  M1PF_MASK; 
+  if ((b & ML1_MASK) && (b & BL_MASK))
+    res |=  M1BL_MASK;
+
+  if ((b & BL_MASK) && (b & PF_MASK))
+    res |=BLPF_MASK;
+  if ((b & PL0_MASK) && (b & PL1_MASK))
+    res |=P0P1_MASK ;
+  if ((b & ML0_MASK) && (b & ML1_MASK))
+    res |=M0M1_MASK ;
+
+  return res;
+}
+
+
+void
+init_collisions(void)
+{
+  int i;
+
+  /* Set up the collision lookup table */ 
+  for (i = 0; i < 256; i++)
+    col_table[i] = set_collisions(i);
+
+  /* Get the colvect 8 byte aligned */
+  if (colvect == 0) colvect=(BYTE *)emu_Malloc(28*8);//calloc(28, 8);
+
+  reset_collisions();
+}
diff --git a/MCUME_pico2/picovcs/Config.h b/MCUME_pico2/picovcs/Config.h
new file mode 100644
index 0000000..1cc916e
--- /dev/null
+++ b/MCUME_pico2/picovcs/Config.h
@@ -0,0 +1,14 @@
+/*
+ * "Hacked" and faster CPU emulation
+ * For CPU debugging, NORMAL (preferred) or HACK2 should be used.
+ */
+
+//#define HACKED			/* yes */
+
+/*
+ * If you do NOT want to emulate undocumented commands, uncomment
+ * the line below, and also select "NORMAL" CPU emulation.
+ */
+
+/*#define NO_UNDOC_CMDS*/	/* no */
+
diff --git a/MCUME_pico2/picovcs/Cpu.c b/MCUME_pico2/picovcs/Cpu.c
new file mode 100644
index 0000000..c7292cb
--- /dev/null
+++ b/MCUME_pico2/picovcs/Cpu.c
@@ -0,0 +1,4980 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: cpu.c,v 1.11.1.11 1997/11/22 14:27:47 ahornby Exp $
+******************************************************************************/
+/* 
+ * 6507 CPU emulation
+ *
+ * Originally from X64
+ * Modified by Alex Hornby for use in x2600
+ * See COPYING for license terms
+ */
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "types.h"
+#include "cpu.h"
+#include "macro.h"
+#include "vmachine.h"
+#include "memory.h"
+#include "display.h"
+#include "exmacro.h"
+#include "exmacro.h"
+#include "Atari2600EmulatorGlobals.h"
+
+extern int pausing;
+
+/* CPU internals */
+ADDRESS program_counter;
+BYTE x_register, y_register, stack_pointer;
+BYTE accumulator, status_register;
+int zero_flag;
+int sign_flag;
+int overflow_flag;
+int break_flag;
+int decimal_flag;
+int interrupt_flag;
+int carry_flag;
+
+/* CPU Clock counts */
+/* Aggregate */
+CLOCK clk;
+/* Current instruction */
+CLOCK clkcount = 0;
+
+/* Electron beam adjustment values for nine and twelve colour clock ins. */
+#define BEAMNINE 5
+#define BEAMTWELVE 9
+int beamadj;
+
+/* Used in undocumented 6507 instructions */
+/* These are unusual and have no discernable use, but here it is. */
+/* val: register to be acted upon */
+/* address: address to take high byte from */
+/* index: index to add to calculated address */
+#ifndef NO_UNDOC_CMDS
+void
+u_stoshr (unsigned int val, ADDRESS address, BYTE index)
+{
+  val &= (((address >> 8) + 1) & 0xff);
+  if (((address & 0xff) + index) > 0xff)
+    address = val;
+  STORE ((address + index), val);
+}
+#endif /* UNDOC */
+
+/* Initialise the CPU */
+/* addr: reset vector address */
+/* Called from init_hardware() */
+void
+init_cpu (ADDRESS addr)
+{
+  SET_SR (0x20);
+  AC=0;
+  XR=0;
+  YR=0;	
+  SP = 0xff;
+  pc6507 = LOAD_ADDR (addr);
+  clk = 0;
+  clkcount = 0;
+}
+
+/* The main emulation loop, performs the CPU emulation */
+void
+mainloop (void)
+{
+  register BYTE b;
+//  init_hardware ();
+
+//  int i=6000;
+  int i=15200/2;
+
+while (i--) 
+{
+
+  do_screen (clkcount);
+  b = LOADEXEC (pc6507);
+  beamadj = 0;
+
+  switch (b)
+	    {
+	    case 0:
+	      {
+		pc6507++;
+		/* Force break. */
+
+		SET_BREAK (1);	/* Set break status. */
+		PUSH (UPPER (pc6507));
+		PUSH (LOWER (pc6507));	/* Push return address into the stack. */
+		PUSH (GET_SR ());	/* Push status register into the stack. */
+		SET_INTERRUPT (1);	/* Disable interrupts. */
+		pc6507 = LOAD_ADDR ((ADDRESS) 65534);	/* Jump using BRK vector (0xfffe). */
+		clkcount = 7;
+	      }
+	      break;
+
+	    case 1:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 2:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 3:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 4:
+	      {
+		pc6507 += 2;
+
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 5:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 6:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_CARRY (src & 0x80);
+		src <<= 1;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 7:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 8:
+	      {
+		register unsigned src = GET_SR ();
+		pc6507++;
+
+		PUSH (src);
+		/* First push item onto stack and then decrement SP. */
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 9:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 10:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		SET_CARRY (src & 0x80);
+		src <<= 1;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 11:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & p1);
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 12:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 13:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 14:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_CARRY (src & 0x80);
+		src <<= 1;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 15:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 16:
+/*  BPL,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if sign flag is clear. */
+		if (!IF_SIGN ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 17:
+/* ORA,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+
+		/* If low byte of address  + index reg is > 0xff then extra cycle */
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 18:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 19:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		pc6507 += 2;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 20:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 21:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 22:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		SET_CARRY (src & 0x80);
+		src <<= 1;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 23:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 24:
+	      {
+		pc6507++;
+
+
+		SET_CARRY ((0));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 25:
+/*  ORA,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 26:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 27:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + YR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 28:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 29:
+/*   ORA,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src |= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 30:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		SET_CARRY (src & 0x80);
+		src <<= 1;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 31:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		/* src = asl(src); AC = ora(src); */
+
+		SET_CARRY (src & 0x80);		/* ASL+ORA */
+		src <<= 1;
+		src |= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 32:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = p2;
+		pc6507 += 3;
+		/* Jump to subroutine. */
+		pc6507--;
+		PUSH ((pc6507 >> 8) & 0xff);	/* Push return address onto the stack. */
+		PUSH (pc6507 & 0xff);
+
+		pc6507 = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 33:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 34:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 35:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 36:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_OVERFLOW (0x40 & src);	/* Copy bit 6 to OVERFLOW flag. */
+		SET_ZERO (src & AC);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 37:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 38:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src <<= 1;
+		if (IF_CARRY ())
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 39:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 40:
+	      {
+		register unsigned src;
+		pc6507++;
+
+		/* First increment stack pointer and then pull item from stack. */
+		src = PULL ();
+
+		SET_SR ((src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 41:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 42:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		src <<= 1;
+		if (IF_CARRY ())
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 43:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & p1);
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 44:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_SIGN (src);
+		SET_OVERFLOW (0x40 & src);	/* Copy bit 6 to OVERFLOW flag. */
+		SET_ZERO (src & AC);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 45:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 46:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src <<= 1;
+		if (IF_CARRY ())
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 47:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 48:
+/*   BMI,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if sign flag is set. */
+		if (IF_SIGN ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 49:
+/*  AND,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 50:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 51:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		pc6507 += 2;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 52:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 53:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 54:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src <<= 1;
+		if (IF_CARRY ())
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 55:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 56:
+	      {
+		pc6507++;
+
+
+		SET_CARRY ((1));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 57:
+/*  AND,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 58:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 59:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE (p2 + YR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 60:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 61:
+/*   AND,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+		src &= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 62:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		src <<= 1;
+		if (IF_CARRY ())
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 63:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		/* src = rol(src); AC = and(src); */
+
+		src <<= 1;
+		if (IF_CARRY ())	/* ROL+AND */
+		  src |= 0x1;
+		SET_CARRY (src > 0xff);
+		src &= 0xff;
+
+		AC &= src;
+		SET_SIGN (AC);
+		SET_ZERO (AC);
+		/* rotated, not disturbed */
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 64:
+	      {
+		register unsigned src;
+		pc6507++;
+		/* Return from interrupt. */
+		/* Load program status and program counter from stack. */
+		src = PULL ();
+		SET_SR (src);
+		src = PULL ();
+		src |= (PULL () << 8);	/* Load return address from stack. */
+
+		pc6507 = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 65:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 66:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 67:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 68:
+	      {
+		pc6507 += 2;
+
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 69:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 70:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 71:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 72:
+/*   PHA,    IMPLIED */
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		beamadj = BEAMNINE;
+		PUSH (src);
+		/* First push item onto stack and then decrement SP. */
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 73:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 74:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 75:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & p1);
+		pc6507 += 2;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 76:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = p2;
+		pc6507 += 3;
+
+
+		pc6507 = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 77:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 78:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 79:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 80:
+/*   BVC,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if overflow flag is clear. */
+		if (!IF_OVERFLOW ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 81:
+/* EOR,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+	      }
+
+	      break;
+
+	    case 82:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 83:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		pc6507 += 2;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 84:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 85:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 86:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 87:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 88:
+	      {
+		pc6507++;
+
+
+		SET_INTERRUPT ((0));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 89:
+/*  EOR,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+	      }
+
+	      break;
+
+	    case 90:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 91:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE (p2 + YR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 92:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 93:
+/*  EOR,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src ^= AC;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src & 0xff);
+	      }
+
+	      break;
+
+	    case 94:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 95:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		/* src = lsr(src); AC = eor(src); */
+
+		SET_CARRY (src & 0x01);		/* LSR+EOR */
+		src >>= 1;
+		src ^= AC;
+		src &= 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 96:
+	      {
+		register unsigned src;
+		pc6507++;
+		/* Return from subroutine. */
+		src = PULL ();
+		src += ((PULL ()) << 8) + 1;	/* Load return address from stack and add 1. */
+
+		pc6507 = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 97:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 2;
+
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 98:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 99:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), ((BYTE) temp));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 100:
+	      {
+		pc6507 += 2;
+
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 101:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 2;
+
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 102:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 103:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE_ZERO (p1, ((BYTE) temp));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 104:
+/*   PLA,    IMPLIED */
+	      {
+		register unsigned src;
+		pc6507++;
+
+		clkcount = 4;
+		/* First increment stack pointer and then pull item from stack. */
+		src = PULL ();
+		SET_SIGN (src);	/* Change sign and zero flag accordingly. */
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 105:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 2;
+
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 106:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 107:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & p1);
+		pc6507 += 2;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 108:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD_ADDR (p2);
+		pc6507 += 3;
+
+
+		pc6507 = (src);
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 109:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 3;
+
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 110:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 111:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE (p2, ((BYTE) temp));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 112:
+/*   BVS,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if overflow flag is set. */
+		if (IF_OVERFLOW ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 113:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 2;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+	      }
+
+	      break;
+
+	    case 114:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 115:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE (LOAD_ZERO_ADDR (p1) + YR, ((BYTE) temp));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 116:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 117:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 2;
+
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 118:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 119:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE_ZERO (p1 + XR, ((BYTE) temp));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 120:
+	      {
+		pc6507++;
+
+
+		SET_INTERRUPT ((1));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 121:
+/*   ADC,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 3;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+	      }
+
+	      break;
+
+	    case 122:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 123:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE (p2 + YR, ((BYTE) temp));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 124:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 125:
+/*  ADC,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		register unsigned int temp = src + AC + (IF_CARRY ()? 1 : 0);
+		pc6507 += 3;
+
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_ZERO (temp & 0xff);		/* This is not valid in decimal mode */
+
+		/*
+		 * In decimal mode this is "correct" but not exact emulation. However,
+		 * the probability of different result when using undefined BCD codes is
+		 * less than 6%
+		 * Sign and Overflow are set between BCD fixup of the two digits  -MSM
+		 */
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (src & 0xf) + (IF_CARRY ()? 1 : 0)) > 9)
+		      temp += 6;
+
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+
+		    if (temp > 0x99)
+		      temp += 96;
+
+		    SET_CARRY (temp > 0x99);
+		  }
+		else
+		  {
+		    SET_SIGN (temp);
+		    SET_OVERFLOW (!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
+		    SET_CARRY (temp > 0xff);
+		  }
+
+		AC = ((BYTE) temp);
+	      }
+
+	      break;
+
+	    case 126:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		if (IF_CARRY ())
+		  src |= 0x100;
+		SET_CARRY (src & 0x01);
+		src >>= 1;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 127:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ror(src); AC = adc(src);
+		 * the real operation discovered by msmakela
+		 * ADC only does the BCD fixup */
+
+		temp = src >> 1;	/* ROR+ADC */
+		if (IF_CARRY ())
+		  temp |= 0x80;
+
+		SET_SIGN (temp);
+		SET_ZERO (temp);	/* Set flags like ROR does */
+
+		SET_OVERFLOW ((temp ^ src) & 0x40);	/* ROR causes this ? */
+
+		if (IF_DECIMAL ())
+		  {
+		    if ((src & 0x0f) > 4)	/* half of the normal */
+		      temp = (temp & 0xf0) | ((temp + 6) & 0xf);
+		    if (src > 0x4f)
+		      temp += 96;
+
+		    SET_CARRY (src > 0x4f);
+		  }
+		else
+		  {
+		    SET_CARRY (src & 0x80);	/* 8502 behaviour */
+		  }
+
+
+		STORE (p2 + XR, ((BYTE) temp));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 128:
+	      {
+		pc6507 += 2;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 129:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = AC;
+		pc6507 += 2;
+
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 130:
+	      {
+		pc6507 += 2;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 131:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & XR);
+		pc6507 += 2;
+
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 132:
+/*  STY,    ZERO_PAGE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = YR;
+
+		clkcount = 3;
+		pc6507 += 2;
+
+		beamadj = BEAMNINE;
+		STORE_ZERO (p1, (src));
+	      }
+
+	      break;
+
+	    case 133:
+/*   STA,    ZERO_PAGE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = AC;
+
+		clkcount = 3;
+		pc6507 += 2;
+
+		beamadj = BEAMNINE;
+		STORE_ZERO (p1, (src));
+	      }
+
+	      break;
+
+	    case 134:
+/*  STX,    ZERO_PAGE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = XR;
+
+		clkcount = 3;
+		pc6507 += 2;
+
+		beamadj = BEAMNINE;
+		STORE_ZERO (p1, (src));
+	      }
+
+	      break;
+
+	    case 135:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & XR);
+		pc6507 += 2;
+
+
+		STORE_ZERO (p1, (src));
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 136:
+	      {
+		register unsigned src = YR;
+		pc6507++;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 137:
+	      {
+		pc6507 += 2;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 138:
+	      {
+		register unsigned src = XR;
+		pc6507++;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 139:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = ((AC | 0xee) & XR & p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 140:
+/*  STY,    ABSOLUTE */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = YR;
+		pc6507 += 3;
+
+		beamadj = BEAMTWELVE;
+		STORE (p2, (src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 141:
+/*  STA,    ABSOLUTE */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = AC;
+		pc6507 += 3;
+
+		beamadj = BEAMTWELVE;
+		STORE (p2, (src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 142:
+/*  STA,    ABSOLUTE */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = XR;
+		pc6507 += 3;
+
+		beamadj = BEAMTWELVE;
+		STORE (p2, (src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 143:
+/* STX,    ABSOLUTE */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = (AC & XR);
+		pc6507 += 3;
+
+		beamadj = BEAMTWELVE;
+		STORE (p2, (src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 144:
+/*  BCC,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register hb;
+		register unsigned src = p1;
+		pc6507 += 2;
+		/* Branch if carry flag is clear. */
+		if (!IF_CARRY ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 145:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = AC;
+		pc6507 += 2;
+
+
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 146:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 147:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & XR);
+		pc6507 += 2;
+
+
+		u_stoshr (src, LOAD_ZERO_ADDR (p1), YR);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 148:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = YR;
+		clkcount = 4;
+		pc6507 += 2;
+
+		beamadj = BEAMTWELVE;
+		STORE_ZERO (p1 + XR, (src));
+	      }
+
+	      break;
+
+	    case 149:
+/*  STA,    ZERO_PAGE_X */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = AC;
+		clkcount = 4;
+		pc6507 += 2;
+
+		beamadj = BEAMTWELVE;
+		STORE_ZERO (p1 + XR, (src));
+	      }
+
+	      break;
+
+	    case 150:
+/* STX,    ZERO_PAGE_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = XR;
+		clkcount = 4;
+		pc6507 += 2;
+
+		beamadj = BEAMTWELVE;
+		STORE_ZERO (p1 + YR, (src));
+	      }
+
+	      break;
+
+	    case 151:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & XR);
+		pc6507 += 2;
+
+
+		STORE_ZERO (p1 + YR, (src));
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 152:
+	      {
+		register unsigned src = YR;
+		pc6507++;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 153:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = AC;
+		pc6507 += 3;
+
+
+		STORE (p2 + YR, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 154:
+	      {
+		register unsigned src = XR;
+		pc6507++;
+
+
+		SP = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 155:
+	      {
+		register unsigned src = (AC & XR);
+		pc6507 += 3;
+
+
+		SP = src; /* SHS */ ;
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 156:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = YR;
+		pc6507 += 3;
+
+
+		u_stoshr (src, p2, XR);
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 157:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = AC;
+		pc6507 += 3;
+
+
+		STORE (p2 + XR, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 158:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = XR;
+		pc6507 += 3;
+
+
+		u_stoshr (src, p2, YR);
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 159:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = (AC & XR);
+		pc6507 += 3;
+
+
+		u_stoshr (src, p2, YR);
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 160:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 161:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 162:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 163:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 164:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 165:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 166:
+/*      LDX,   ZERO_PAGE */
+	      {
+		register p1 = LOADEXEC (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+
+		clkcount = 3;
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+	      }
+
+	      break;
+
+	    case 167:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 168:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 169:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 170:
+	      {
+		register unsigned src = AC;
+		pc6507++;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 171:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = (AC & p1);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 172:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 173:		/* LDA absolute */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src;
+		clkcount = 4;
+		src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 174:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 175:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 176:
+/*   BCS,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if carry flag is set. */
+		if (IF_CARRY ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 177:
+/*   LDA,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 178:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 179:
+/*   LAX,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+	      }
+
+	      break;
+
+	    case 180:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 181:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 182:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + YR);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 183:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + YR);
+		pc6507 += 2;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 184:
+	      {
+		pc6507++;
+
+
+		SET_OVERFLOW ((0));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 185:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 186:
+	      {
+		register unsigned src = SP;
+		pc6507++;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 187:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = (SP & LOAD (p2 + YR));
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = SP = (src);
+	      }
+
+	      break;
+
+	    case 188:
+/*   LDY,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+	      }
+
+	      break;
+
+	    case 189:
+/*  LDA,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = (src);
+	      }
+
+	      break;
+
+	    case 190:
+/*   LDX,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+	      }
+
+	      break;
+
+	    case 191:
+/*   LAX,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		AC = XR = (src);
+	      }
+
+	      break;
+
+	    case 192:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src = YR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 193:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 194:
+	      {
+		pc6507 += 2;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 195:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		pc6507 += 2;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 196:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src = YR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 197:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 198:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 199:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 200:
+	      {
+		register unsigned src = YR;
+		pc6507++;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		YR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 201:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 202:
+	      {
+		register unsigned src = XR;
+		pc6507++;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 203:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src = (AC & XR) - src;	/* Carry is ignored (CMP) */
+		/* Overflow flag may be affected */
+		SET_CARRY (src < 0x100);
+
+		src &= 0xff;	/* No decimal mode */
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 204:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src = YR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 205:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 206:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 207:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 208:
+/*  BNE,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if  zero flag is clear. */
+		if (!IF_ZERO ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 209:
+/*   CMP,    INDIRECT_Y */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 2;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+	      }
+
+	      break;
+
+	    case 210:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		////mon (pc6507);
+	      }
+
+	      break;
+
+	    case 211:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		pc6507 += 2;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 212:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 213:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 214:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 215:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 216:
+	      {
+		pc6507++;
+
+
+		SET_DECIMAL ((0));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 217:
+/*   CMP,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+	      }
+
+	      break;
+
+	    case 218:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 219:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		pc6507 += 3;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE (p2 + YR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 220:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 221:
+/*   CMP,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		src = AC - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+	      }
+
+	      break;
+
+	    case 222:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		src = (src - 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 223:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		/* cmp(--src & 0xff));  */
+
+		src = (src - 1) & 0xff;		/* DEC+CMP */
+		SET_CARRY (AC >= src);
+		SET_SIGN (AC - src);
+		SET_ZERO (AC != src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 224:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		pc6507 += 2;
+
+		src = XR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 225:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 226:
+	      {
+		pc6507 += 2;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 227:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1 + XR));
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE (LOAD_ZERO_ADDR (p1 + XR), (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 228:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src = XR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 229:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+		clkcount = 3;
+	      }
+
+	      break;
+
+	    case 230:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		pc6507 += 2;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 231:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE_ZERO (p1, (src));
+		clkcount = 5;
+	      }
+
+	      break;
+
+	    case 232:
+	      {
+		register unsigned src = XR;
+		pc6507++;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		XR = (src);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 233:
+/*  SBC,    IMMEDIATE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+		if (!IF_DECIMAL ())
+		  {
+		    SET_SIGN (temp);
+		    SET_ZERO (temp & 0xff);	/* Sign and Zero are invalid in decimal mode */
+
+		    SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+		    SET_CARRY (temp < 0x100);
+		    AC = (temp & 0xff);
+
+		  }
+		else
+		  {
+		    int bcd1, bcd2;
+		    BYTE old_A;
+		    int C = IF_CARRY ()? 1 : 0;
+
+		    old_A = AC;
+
+		    bcd1 = fromBCD (AC);
+		    bcd2 = fromBCD (src);
+
+		    bcd1 = bcd1 - bcd2 - !C;
+
+		    if (bcd1 < 0)
+		      bcd1 = 100 - (-bcd1);
+		    AC = toBCD (bcd1);
+
+		    SET_CARRY ((old_A < (src + !C)) ? 0 : 1);
+		    SET_OVERFLOW ((old_A ^ AC) & 0x80);
+		  }
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 234:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 235:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 236:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src = XR - src;
+		SET_CARRY (src < 0x100);
+		SET_SIGN (src);
+		SET_ZERO (src &= 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 237:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 3;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 238:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		pc6507 += 3;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 239:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE (p2, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 240:
+/*   BEQ,    RELATIVE */
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = p1;
+		register BYTE hb;
+		pc6507 += 2;
+		/* Branch if  zero flag is set. */
+		if (IF_ZERO ())
+		  {
+		    hb = UPPER (pc6507);
+		    pc6507 = REL_ADDR (pc6507, src);
+		    if (brtest (hb))
+		      /* Same page */
+		      clkcount = 3;
+		    else
+		      /* Different page */
+		      clkcount = 4;
+		  }
+		else
+		  clkcount = 2;
+	      }
+
+	      break;
+
+	    case 241:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register ADDRESS p2 = LOAD_ZERO_ADDR (p1);
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 6;
+		else
+		  /* Same page */
+		  clkcount = 5;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+	      }
+
+	      break;
+
+	    case 242:
+	      {
+		pc6507++; // KILL Instruction
+		/* No such opcode. */
+		//(void) printf ("Illegal instruction.\n");
+		//verflg = 1;
+		//--pc6507;
+		//show();
+		//mon (pc6507);
+	      }
+
+	      break;
+
+	    case 243:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD (LOAD_ZERO_ADDR (p1) + YR);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE (LOAD_ZERO_ADDR (p1) + YR, (src));
+		clkcount = 8;
+	      }
+
+	      break;
+
+	    case 244:
+	      {
+		pc6507 += 2;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 245:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 2;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 246:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		pc6507 += 2;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 247:
+	      {
+		register p1 = LOAD (pc6507 + 1);
+		register unsigned src = LOAD_ZERO (p1 + XR);
+		register unsigned int temp;
+		pc6507 += 2;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE_ZERO (p1 + XR, (src));
+		clkcount = 6;
+	      }
+
+	      break;
+
+	    case 248:
+/*  SED,    IMPLIED */
+	      {
+		pc6507++;
+
+		SET_DECIMAL ((1));
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 249:
+/*  SBC,    ABSOLUTE_Y */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 3;
+
+		if (pagetest (p2, YR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+	      }
+
+	      break;
+
+	    case 250:
+	      {
+		pc6507++;
+
+		clkcount = 2;
+	      }
+
+	      break;
+
+	    case 251:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + YR);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE (p2 + YR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 252:
+	      {
+		pc6507 += 3;
+
+		clkcount = 4;
+	      }
+
+	      break;
+
+	    case 253:
+/*   SBC,    ABSOLUTE_X */
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		register unsigned int temp = AC - src - (IF_CARRY ()? 0 : 1);
+		pc6507 += 3;
+
+		if (pagetest (p2, XR))
+		  /* Over page */
+		  clkcount = 5;
+		else
+		  /* Same page */
+		  clkcount = 4;
+
+		/*
+		 * SBC is not exact either. It has 6% different results too.
+		 */
+
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = (temp & 0xff);
+	      }
+
+	      break;
+
+	    case 254:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		pc6507 += 3;
+
+		src = (src + 1) & 0xff;
+		SET_SIGN (src);
+		SET_ZERO (src);
+
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+	    case 255:
+	      {
+		register p2 = load_abs_addr ();
+		register unsigned src = LOAD (p2 + XR);
+		register unsigned int temp;
+		pc6507 += 3;
+
+
+		/* src = ++src & 0xff; AC = sbc(src); */
+
+		src = ((src + 1) & 0xff);	/* INC+SBC */
+
+		temp = AC - src - (IF_CARRY ()? 0 : 1);
+
+		SET_SIGN (temp);
+		SET_ZERO (temp & 0xff);		/* Sign and Zero are invalid in decimal mode */
+
+		SET_OVERFLOW (((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
+
+		if (IF_DECIMAL ())
+		  {
+		    if (((AC & 0xf) + (IF_CARRY ()? 1 : 0)) < (src & 0xf))
+		      temp -= 6;
+		    if (temp > 0x99)
+		      temp -= 0x60;
+		  }
+		SET_CARRY (temp < 0x100);
+
+		AC = temp;
+		/* src saved */
+		STORE (p2 + XR, (src));
+		clkcount = 7;
+	      }
+
+	      break;
+
+
+
+	    }			/* switch */
+
+	  clk += clkcount;
+
+  }		/* while(!pausing) */
+
+	
+bThreadRunning = 0;
+pausing = 0;
+
+}				/* mainloop */
diff --git a/MCUME_pico2/picovcs/Display.c b/MCUME_pico2/picovcs/Display.c
new file mode 100644
index 0000000..fa5a026
--- /dev/null
+++ b/MCUME_pico2/picovcs/Display.c
@@ -0,0 +1,108 @@
+/*****************************************************************************
+
+   This file is part of Virtual VCS, the Atari 2600 Emulator
+   ===================================================
+
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+   Modified 1996 by Daniel Boris
+   Modified 2001 by Stuart Russell
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+
+   See the file COPYING for Details.
+
+   $Id: display.c,v 1.23 1996/03/21 15:52:38 alex Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/*
+   Display handling code.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "types.h"
+#include "btypes.h"
+#include "vmachine.h"
+#include "address.h"
+#include "colours.h"
+#include "resource.h"
+#include "display.h"
+#include "emuapi.h"
+
+
+int vwidth,vheight,theight;
+uint8 * VBuf=0; //[(160)*192+8];
+char coltable[256];
+
+/* The refresh skipping counter */
+int tv_counter=0;
+
+/* Set up the colormap - original is 24bit!
+//------------------------------------------------------------------------------------
+// we use a 16 bit color palette (rrrrrggggggbbbbb). This should change based
+// on the PDA device (E-125).
+//------------------------------------------------------------------------------------*/
+static void create_cmap(void)
+{
+	int i;
+	unsigned char red,green,blue;
+
+	/* Initialise parts of the colors array */
+	for(i=0; i< 256; i++)
+	{
+		red  = (unsigned char)((colortable[i] & 0xff0000) >> 16);
+		green = (unsigned char)((colortable[i] & 0x00ff00) >> 8);
+		blue = (unsigned char)(colortable[i] & 0x0000ff);
+    emu_SetPaletteEntry(red,green,blue,i);
+	}
+}
+
+
+/* Create the main application shell */
+static void create_window()
+{
+	int i;
+
+	theight = tv_height;
+	vheight = tv_height;
+	vwidth  = tv_width;
+	create_cmap();
+	for(i=0; i<256; i++) coltable[i]=1;
+	coltable[0]=coltable[1]=coltable[2]=coltable[4]=0;
+	coltable[8]=coltable[16]=coltable[32]=coltable[64]=0;
+	coltable[128]=0;
+}
+
+
+/* The main initialiser for the X stuff */
+int tv_on()
+{
+   /* Get the basic colors */
+	unsigned long m;
+
+  if (VBuf == 0) VBuf = (uint8 *)emu_Malloc((160)*192+8);
+
+	create_window();
+
+	// if pointer size is 4 bytes, make sure the
+	// buffer is aligned on an 8 byte boundary.
+	if(sizeof(uint8*)==4)
+	{
+		m=(unsigned long)VBuf;
+		m+=8;
+		m&=0xFFFFFFF8;
+		VBuf=(uint8*)m;
+	} 
+	memset(VBuf,128,160*192);
+	return(1);
+}
+
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/Exmacro.c b/MCUME_pico2/picovcs/Exmacro.c
new file mode 100644
index 0000000..23566bf
--- /dev/null
+++ b/MCUME_pico2/picovcs/Exmacro.c
@@ -0,0 +1,69 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for Details.
+   
+   $Id: exmacro.c,v 1.6 1996/08/26 15:04:20 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* Things that used to be macros, but are now __inline functions.
+   Done for ease of debugging */
+
+#include "types.h"
+#include "extern.h"
+#include "macro.h"
+#include "memory.h"
+#include "exmacro.h"
+
+/* Loads an absolute address uising the quicker load mechanism */
+__inline ADDRESS
+load_abs_addr (void)
+{
+  return (LOADEXEC (pc6507 + 1) | (LOADEXEC (pc6507 + 2) << 8));
+}
+
+/* Used in variable cycle time indexed addressing */
+/* a: address to be incremented */
+/* b: increment value */
+/* returns: TRUE if an address increment will cross a page boundary */
+__inline int
+pagetest (ADDRESS a, BYTE b)
+{
+  return (LOWER (a) + b > 0xff);
+}
+
+/* Used in variable cycle time branches */
+/* a: high byte of new address */
+/* returns: TRUE if a branch is to the same page */
+__inline int
+brtest (BYTE a)
+{
+  return (UPPER (pc6507) == (a));
+}
+
+/* Convert from binary to BCD (Binary Coded Decimal) */
+/* a: binary value */
+/* returns: BCD value */
+__inline int
+toBCD (int a)
+{
+  return (((a % 100) / 10) << 4) | (a % 10);
+}
+
+/* Convert from BCD to binary */
+/* a: BCD value */
+/* returns: binary value */
+__inline int
+fromBCD (int a)
+{
+  return ((a >> 4) & 0xf) * 10 + (a & 0xf);
+}
diff --git a/MCUME_pico2/picovcs/Keyboard.c b/MCUME_pico2/picovcs/Keyboard.c
new file mode 100644
index 0000000..a457438
--- /dev/null
+++ b/MCUME_pico2/picovcs/Keyboard.c
@@ -0,0 +1,206 @@
+/*****************************************************************************
+
+   This file is part of Virtual VCS, the Atari 2600 Emulator
+   ===================================================
+
+   Copyright 1996 Daniel Boris. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+
+   See the file COPYING for Details.
+
+******************************************************************************/
+/*
+  This module has been completely re-written since X2600
+  This has been hacked for the E-125 by Stuart Russell
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+#include "keyboard.h"
+#include "types.h"
+#include "address.h"
+#include "vmachine.h"
+#include "extern.h"
+#include "memory.h"
+#include "display.h"
+#include "resource.h"
+#include "kbd.h"
+
+#include "emuapi.h"
+
+// this returns a byte from the key state buffer. 
+// example: KEY(0) will be expanded to: keys[SCANCODE_0]
+//#define KEY(__a) keys[SCANCODE_##__a]
+
+extern char *KeyboardGetstate(void);
+extern int pausing;
+extern int nOptions_Color;
+extern int nOptions_P1Diff;
+extern int nOptions_P2Diff;
+
+static int ik;     // joypad key
+static int ihk;    // I2C keyboard key
+static int iusbhk; // USB keyboard key
+static int prevhk; // previous keyboard key
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+  if (key <= 0x7f) iusbhk = key;
+  //else if (key == KBD_KEY_UP) iusbhk = 0xD7;  
+  //else if (key == KBD_KEY_LEFT) iusbhk = 0xD8;  
+  //else if (key == KBD_KEY_RIGHT) iusbhk = 0xD9;  
+  //else if (key == KBD_KEY_DOWN) iusbhk = 0xDA;  
+  //else if (key == KBD_KEY_BS) iusbhk = 0x7F;  
+  else
+    iusbhk = 0;
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+  iusbhk = 0;
+}
+
+
+void vcs_Input(int key) {
+  ik  = emu_GetPad();
+  ihk = emu_ReadI2CKeyboard();  
+}
+
+void keyjoy(void) {
+	BYTE v1,v2;
+
+	v1=v2=0x0f;
+	// read the keyboard state. The return value (in keys) is a pointer to a
+	// 256 byte buffer which holds the state of all the keyboard keys. If a 
+	// byte's upper bit is set to 1, the key is pressed.
+	
+	int key = ik;
+	if (key & MASK_JOY2_UP)  v1 &= 0x0E;
+	if (key & MASK_JOY2_DOWN) v1 &= 0x0D;
+	if (key & MASK_JOY2_RIGHT)  v1 &= 0x0B;
+	if (key & MASK_JOY2_LEFT)  v1 &= 0x07;
+	
+	riotRead[0x280]=(v1 << 4) | v2;
+}
+
+void keycons(void) {
+//---------------------------------------------------------
+// This function reads the state of the joysticks (buttons)
+//---------------------------------------------------------
+
+  int hk = ihk;
+  if (iusbhk) hk = iusbhk;
+  
+
+  switch(hk) {
+    case 'a':
+    case 'q':
+    case '1':
+  		//emu_printf("1");    	
+      hk = 1;
+      break;
+    case 'w':
+    case 'z':
+    case '2':
+  		//emu_printf("2");    	
+      hk = 2;
+      break;
+    case 'e':
+    case '3':
+  		//emu_printf("3");    	
+      hk = 3;
+      break;
+    case 'r':
+    case '4':
+  		//emu_printf("4");    	
+      hk = 4;
+      break;
+    default:  	
+      //hk = 0;
+      break;
+  };
+
+
+  int kswitches = 0;
+	if (hk) { 	 
+	  if (hk == 1) {
+	  	if (kswitches & 0x01)
+	  		kswitches &= ~0x01;
+	  	else	
+	  		kswitches |= 0x01;
+	  }
+	  else if (hk == 2) {
+	  	if (kswitches & 0x02)
+	  		kswitches &= ~0x02;
+	  	else	
+	  		kswitches |= 0x02;
+	  }
+	  else if (hk == 3) {
+	  	if (kswitches & 0x04)
+	  		kswitches &= ~0x04;
+	  	else	
+	  		kswitches |= 0x04;
+	  }
+	  else if (hk == 4) {
+	  	if (kswitches & 0x08)
+	  		kswitches &= ~0x08;
+	  	else	
+	  		kswitches |= 0x08;
+	  }
+  }
+
+
+	// read the keyboard state. The return value (in keys) is a pointer to a
+	// 256 byte buffer which holds the state of all the keyboard keys. If a 
+	// byte's upper bit is set to 1, the key is pressed.
+  
+	riotRead[SWCHB] |= 0x03;
+	
+	int key = ik;
+	if ( (key & MASK_KEY_USER3) || (kswitches & 0x04)  )
+    nOptions_Color = !nOptions_Color;
+    
+	if (!nOptions_Color) 
+	  riotRead[SWCHB] &= 0xF7;		/* BW */
+	else 
+		riotRead[SWCHB] |= 0x08;	/* Color */
+
+
+	if (   (kswitches & 0x02)
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+#else  
+		     || (key & MASK_KEY_USER1)
+#endif		
+		 )
+		riotRead[SWCHB] &= 0xFE;	/* Reset */
+	if (   (kswitches & 0x01)
+#if (defined(ILI9341) || defined(ST7789)) && defined(USE_VGA)
+#else  
+		     || (key & MASK_KEY_USER2)
+#endif
+		 )  
+		riotRead[SWCHB] &= 0xFD;	/* Select */
+
+	if (nOptions_P1Diff) riotRead[SWCHB] &= 0xBF; 	/* P0 amateur */
+	else riotRead[SWCHB] |= 0x40;   /* P0 pro */
+
+	if (nOptions_P2Diff) riotRead[SWCHB] &= 0x7f;    /* P1 amateur */
+	else riotRead[SWCHB] |= 0x80;	/* P1 pro */
+}
+
+void keytrig(void) {
+	// read the keyboard state. The return value (in keys) is a pointer to a
+	// 256 byte buffer which holds the state of all the keyboard keys. If a 
+	// byte's upper bit is set to 1, the key is pressed.
+	
+	int key = ik;
+	if (!(tiaWrite[VBLANK] & 0x40)) {
+		tiaRead[INPT5]=0x80;
+		if (key & MASK_JOY2_BTN)
+			tiaRead[INPT4]=0x00;
+		else
+			tiaRead[INPT4]=0x80;
+	}
+}
+
diff --git a/MCUME_pico2/picovcs/Memory.c b/MCUME_pico2/picovcs/Memory.c
new file mode 100644
index 0000000..ede0379
--- /dev/null
+++ b/MCUME_pico2/picovcs/Memory.c
@@ -0,0 +1,785 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for Details.
+   
+   $Id: memory.c,v 2.23 1997/04/06 02:19:12 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* 
+ * Holds the memory access routines to both memory and memory mapped
+ * i/o, hence memory.c
+ *
+ * Uses GNU C extensions.
+ */
+
+#include <stdio.h>
+#include "types.h"
+#include "address.h"
+#include "vmachine.h"
+#include "display.h"
+#include "raster.h"
+#include "tiasound.h"
+#include "collision.h"
+#include "col_mask.h"
+#include "options.h"
+#include "keyboard.h"
+#include "sound.h"
+#include "resource.h"
+
+
+extern CLOCK clkcount;
+extern CLOCK clk;
+extern int beamadj;
+//extern keyboard_keypad();
+extern keytrig();
+extern keyjoy();
+extern keycons();
+extern int nOptions_Landscape;
+extern int nOptions_SoundOn;
+
+
+/* Undecoded Read, for executable code etc. */
+/* a: address to read */
+/* returns: byte at address a */
+BYTE
+undecRead (ADDRESS a)
+{
+  if (a & 0x1000)
+    return theRom[a & 0xfff];
+  else
+    return theRam[a & 0x7f];
+}
+
+
+__inline void
+bank_switch_write (ADDRESS a, BYTE b)
+{
+  a&=0xfff;
+  switch (base_opts.bank)
+    {
+
+    case 1:
+      /* Atari 8k F8 */
+      switch (a)
+	{
+	case 0xff8:
+	  theRom = &theCart[0];
+	  break;
+	case 0xff9:
+	  theRom = &theCart[4096];
+	  break;
+	}
+      break;
+
+    case 2:
+      /* Atari 16k F6 */
+      switch (a)
+	{
+	case 0xff6:
+	  theRom = &theCart[0];
+	  break;
+	case 0xff7:
+	  theRom = &theCart[4096];
+	  break;
+	case 0xff8:
+	  theRom = &theCart[8192];
+	  break;
+	case 0xff9:
+	  theRom = &theCart[12288];
+	  break;
+	}
+      break;
+
+    case 3:
+      /* Parker Brothers 8k E0 */
+      {
+	ADDRESS a1;
+	if (a > 0xfdf && a < 0xfe8) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0],&theCart[a1],0x400);
+	  }
+	else if (a > 0xfe7 && a < 0xff0) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0x400],&theCart[a1],0x400);
+	  } 
+	else if (a > 0xfef && a < 0xff8) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0x800],&theCart[a1],0x400);
+	  }
+      }
+      break;
+
+    case 4:
+      /* CBS Ram Plus FA */
+      if (a < 0x100) 
+	cartRam[a & 0xff]=b;
+      else
+	{	  
+	  switch (a)
+	    {
+	    case 0xff8:
+	      theRom = &theCart[0];
+	      break;
+	    case 0xff9:
+	      theRom = &theCart[4096];
+	      break;
+	    case 0xffa:
+	      theRom = &theCart[8192];
+	      break;
+	    }
+	}
+      break;
+
+    case 5:
+      /* Atari 16k + super chip ram F6SC */
+      if (a < 0x80) 
+	cartRam[a & 0x7f] = b;
+      else
+	{
+	  switch (a)
+	    {
+	    case 0xff6:
+	      theRom = &theCart[0];
+	      break;
+	    case 0xff7:
+	      theRom = &theCart[4096];
+	      break;
+	    case 0xff8:
+	      theRom = &theCart[8192];
+	      break;
+	    case 0xff9:
+	      theRom = &theCart[12288];
+	      break;
+	    }
+	}
+      break;
+    }
+}
+
+__inline BYTE
+bank_switch_read (ADDRESS a)
+{
+  BYTE res;
+
+  a&=0xfff;
+  switch (base_opts.bank)
+    {
+    case 1:
+      /* Atari 8k F8 */
+      switch (a)
+	{
+	case 0xff8:
+	  theRom = &theCart[0];
+	  break;
+	case 0xff9:
+	  theRom = &theCart[4096];
+	  break;
+	}
+      res=theRom[a];
+      break;
+
+    case 2:
+      /* Atari 16k F6 */
+      switch (a)
+	{
+	case 0xff6:
+	  theRom = &theCart[0];
+	  break;
+	case 0xff7:
+	  theRom = &theCart[4096];
+	  break;
+	case 0xff8:
+	  theRom = &theCart[8192];
+	  break;
+	case 0xff9:
+	  theRom = &theCart[12288];
+	  break;
+	}
+      res=theRom[a];
+      break;
+
+    case 3:
+      /* Parker Brothers 8k E0 */
+      /* Parker Brothers 8k E0 */
+      {
+	ADDRESS a1;
+	if (a > 0xfdf && a < 0xfe8) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0],&theCart[a1],0x400);
+	  }
+	else if (a > 0xfe7 && a < 0xff0) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0x400],&theCart[a1],0x400);
+	  } 
+	else if (a > 0xfef && a < 0xff8) 
+	  {
+	    a1=(a&0x07)<<10;
+	    memcpy(&cartScratch[0x800],&theCart[a1],0x400);
+	  }
+      }
+      res=theRom[a];
+      break;
+
+    case 4:
+      /* CBS Ram Plus FA */
+      if (a > 0xff && a < 0x200) 
+	  res=cartRam[a & 0xff];
+      else
+	{	  
+	  switch (a)
+	    {
+	    case 0xff8:
+	      theRom = &theCart[0];
+	      break;
+	    case 0xff9:
+	      theRom = &theCart[4096];
+	      break;
+	    case 0xffa:
+	      theRom = &theCart[8192];
+	      break;
+	    }
+	  res=theRom[a];
+	}
+      break;
+
+    case 5:
+      /* Atari 16k + super chip ram F6SC */
+      if (a > 0x7f && a < 0x100) 
+	res=cartRam[a & 0x7f];
+      else
+	{
+	  switch (a)
+	    {
+	    case 0xff6:
+	      theRom = &theCart[0];
+	      break;
+	    case 0xff7:
+	      theRom = &theCart[4096];
+	      break;
+	    case 0xff8:
+	      theRom = &theCart[8192];
+	      break;
+	    case 0xff9:
+	      theRom = &theCart[12288];
+	      break;
+	    }
+	  res=theRom[a];
+	}
+      break;
+    default:
+      res=theRom[a];
+      break;
+    }
+  return res;
+}
+
+
+/* Decoded write to memory */
+/* a: address written to */
+/* b: byte value written */
+void
+decWrite (ADDRESS a, BYTE b)
+{
+  int i;
+
+  /* A Write to the ROM area */
+  if (a & 0x1000)
+    {
+      bank_switch_write (a,b);
+    }
+  /* A Write to the RAM area in Page 0 and 1 */
+  else if ((a & 0x280) == 0x80)
+    {
+      theRam[a & 0x7f] = b;
+    }
+  /* TIA */
+  else if (!(a & 0x80))
+    {
+      switch (a & 0x7f)
+	{
+	case VSYNC:
+	  if (b & 0x02)
+	    {
+	      /* Start vertical sync */
+	      vbeam_state = VSYNCSTATE;
+	    }
+	  break;
+	case VBLANK:
+	  do_vblank (b);
+	  /* Ground paddle pots */
+	  if (b & 0x80)
+	    {
+	      /* Grounded ports */
+	      tiaRead[INPT0] = 0x00;
+	      tiaRead[INPT1] = 0x00;
+	    }
+	  else
+	    {
+	      /* Processor now measures time for a logic 1 to appear
+	         at each paddle port */
+	      tiaRead[INPT0] = 0x80;
+	      tiaRead[INPT1] = 0x80;
+	      paddle[0].val = clk;
+	      paddle[1].val = clk;
+	    }
+	  /* Logic for dumped input ports */
+	  if (b & 0x40)
+	    {
+	      if (tiaWrite[VBLANK] & 0x40)
+		{
+		  tiaRead[INPT4] = 0x80;
+		  tiaRead[INPT5] = 0x80;
+		}
+//	      else
+//		{
+//		  //read_trigger ();
+//		}
+	    }
+	  tiaWrite[VBLANK] = b;
+	  break;
+	case WSYNC:
+	  /* Skip to HSYNC pulse */
+	  do_hsync ();
+	  break;
+	case RSYNC:
+	  /* used in chip testing */
+	  //dbg_message(DBG_LOTS,"ARGHH an undocumented RSYNC!\n");
+	  break;
+	case NUSIZ0:
+	  /*
+	     printf("P0 nusize: ebeamx=%d, ebeamy=%d, nusize=%02x\n",
+	     ebeamx, ebeamy, (int)b);
+	   */
+	  pl[0].nusize = b & 0x07;
+	  ml[0].width = (b & 0x30) >> 4;
+	  break;
+	case NUSIZ1:
+	  /*
+	     printf("P1 nusize: ebeamx=%d, ebeamy=%d, nusize=%02x\n",
+	     ebeamx, ebeamy, (int)b);
+	   */
+	  pl[1].nusize = b & 0x07;
+	  ml[1].width = (b & 0x30) >> 4;
+	  break;
+	case COLUP0:
+	  do_unified_change (0, b);
+	  break;
+	case COLUP1:
+	  do_unified_change (1, b);
+	  break;
+	case COLUPF:
+	  do_unified_change (2, b);
+	  break;
+	case COLUBK:
+	  /*printf("BKcolour = %d, line=%d\n", (int)(b>>1), ebeamy); */
+	  do_unified_change (3, b);
+	  break;
+	case CTRLPF:
+	  tiaWrite[CTRLPF] = b & 0x37;	/* Bitmask 00110111 */
+	  do_pfraster_change (0, 3, b & 0x01);	/* Reflection */
+	  
+	  /* Normal/Alternate priority */
+	  do_unified_change(4, (b & 0x04));
+	  
+	  /* Scores/Not scores */
+	  do_unified_change(5, (b & 0x02));
+
+	  break;
+	case REFP0:
+	  pl[0].reflect = (b & 0x08) >> 3;
+	  break;
+	case REFP1:
+	  pl[1].reflect = (b & 0x08) >> 3;
+	  break;
+	case PF0:
+	  do_pfraster_change (0, 0, b & 0xf0);
+	  break;
+	case PF1:
+	  do_pfraster_change (0, 1, b);
+	  break;
+	case PF2:
+	  do_pfraster_change (0, 2, b);
+	  break;
+	case RESP0:
+	  /* Ghost in pacman!
+	     if(beamadj == 0) {
+	     printf("RESP0: ebeamx=%d, ebeamy=%d\n",
+	     ebeamx, ebeamy); 
+	     show();
+	     } */
+	  pl[0].x = ebeamx + beamadj;
+	  /* As per page 20 Stella Programmers Guide */
+	  if (pl[0].x < 0)
+	    pl[0].x = 0;
+	  break;
+	case RESP1:
+	  /*if(beamadj == 0) {
+	     printf("RESP1: ebeamx=%d, ebeamy=%d\n",
+	     ebeamx, ebeamy);
+	     show(); 
+	     } */
+	  pl[1].x = ebeamx + beamadj;
+	  /* As per page 20 Stella Programmers Guide */
+	  if (pl[1].x < 0)
+	    pl[1].x = 0;
+	  break;
+	case RESM0:
+	  ml[0].x = ebeamx + beamadj;
+	  /* As per page 20 Stella Programmers Guide */
+	  if (ml[0].x < 0)
+	    ml[0].x = 0;
+	  break;
+	case RESM1:
+	  ml[1].x = ebeamx + beamadj;
+	  /* As per page 20 Stella Programmers Guide */
+	  if (ml[1].x < 0)
+	    ml[1].x = 0;
+	  break;
+	case RESBL:
+	  ml[2].x = ebeamx + beamadj;
+	  /* As per page 20 Stella Programmers Guide */
+	  if (ml[2].x < 0)
+	    ml[2].x = 0;
+	  break;
+	case AUDC0:
+  	  if (nOptions_SoundOn)		  Update_tia_sound(AUDC0,b & 0x0f);
+	  break;
+	case AUDC1:
+  	  if (nOptions_SoundOn) 	  Update_tia_sound(AUDC1,b & 0x0f);
+	  break;
+	case AUDF0:
+  	  if (nOptions_SoundOn) 	  Update_tia_sound(AUDF0,b & 0x1f);
+	  break;
+	case AUDF1:
+  	  if (nOptions_SoundOn) 	  Update_tia_sound(AUDF1,b & 0x1f);
+	  break;
+	case AUDV0:
+  	  if (nOptions_SoundOn) 	  Update_tia_sound(AUDV0 ,  b & 0x0f);
+	  break;
+	case AUDV1:
+  	  if (nOptions_SoundOn) 	  Update_tia_sound(AUDV1 ,  b & 0x0f);
+	  break;
+	case GRP0:
+	  do_plraster_change (0, 0, b);
+	  do_plraster_change (1, 1, b);
+	  break;
+	case GRP1:
+	  do_plraster_change (1, 0, b);
+	  do_plraster_change (0, 1, b);
+	  ml[2].vdel = ml[2].enabled;
+	  break;
+	case ENAM0:
+	  ml[0].enabled = b & 0x02;
+	  if (tiaWrite[RESMP0])
+	    ml[0].enabled = 0;
+	  break;
+	case ENAM1:
+	  ml[1].enabled = b & 0x02;
+	  if (tiaWrite[RESMP1])
+	    ml[1].enabled = 0;
+	  break;
+	case ENABL:
+	  ml[2].enabled = b & 0x02;
+	  break;
+	case HMP0:
+	  pl[0].hmm = (b >> 4);
+	  break;
+	case HMP1:
+	  pl[1].hmm = (b >> 4);
+	  break;
+	case HMM0:
+	  ml[0].hmm = (b >> 4);
+	  break;
+	case HMM1:
+	  ml[1].hmm = (b >> 4);
+	  break;
+	case HMBL:
+	  ml[2].hmm = (b >> 4);
+	  break;
+	case VDELP0:
+	  pl[0].vdel_flag = b & 0x01;
+	  break;
+	case VDELP1:
+	  pl[1].vdel_flag = b & 0x01;
+	  break;
+	case VDELBL:
+	  ml[2].vdel_flag = b & 0x01;
+	  break;
+	case RESMP0:
+	  tiaWrite[RESMP0] = b & 0x02;
+	  if (b & 0x02)
+	    {
+	      ml[0].x = pl[0].x + 4;
+	      ml[0].enabled = 0;
+	    }
+	  break;
+	case RESMP1:
+	  tiaWrite[RESMP1] = b & 0x02;
+	  if (b & 0x02)
+	    {
+	      ml[1].x = pl[1].x + 4;
+	      ml[1].enabled = 0;
+	    }
+	  break;
+	case HMOVE:
+	  /* Player 0 */
+	  if (pl[0].hmm & 0x08)
+	    pl[0].x += ((pl[0].hmm ^ 0x0f) + 1);
+	  else
+	    pl[0].x -= pl[0].hmm;
+	  if (pl[0].x > 160)
+	    pl[0].x = -68;
+	  else if (pl[0].x < -68)
+	    pl[0].x = 160;
+
+	  /* Player 2 */
+	  if (pl[1].hmm & 0x08)
+	    pl[1].x += ((pl[1].hmm ^ 0x0f) + 1);
+	  else
+	    pl[1].x -= pl[1].hmm;
+	  if (pl[1].x > 160)
+	    pl[1].x = -68;
+	  else if (pl[1].x < -68)
+	    pl[1].x = 160;
+
+	  /* Missiles */
+	  for (i = 0; i < 3; i++)
+	    {
+	      if (ml[i].hmm & 0x08)
+		ml[i].x += ((ml[i].hmm ^ 0x0f) + 1);
+	      else
+		ml[i].x -= ml[i].hmm;
+	      if (ml[i].x > 160)
+		ml[i].x = -68;
+	      else if (ml[i].x < -68)
+		ml[i].x = 160;
+	    }
+	  break;
+	case HMCLR:
+	  pl[0].hmm = 0;
+	  pl[1].hmm = 0;
+	  for (i = 0; i < 3; i++)
+	    ml[i].hmm = 0;
+	  break;
+	case CXCLR:
+	  col_state=0;
+	  break;
+	}
+    }
+  else
+    {
+      switch (a & 0x2ff)
+	{
+	  /* RIOT I/O ports */
+	case SWCHA:
+	  riotWrite[SWCHA] = b;
+	  break;
+	case SWACNT:
+	  riotWrite[SWACNT] = b;
+	  break;
+	case SWCHB:
+	case SWBCNT:
+	  /* Do nothing */
+	  break;
+
+	  /* Timer ports */
+	case TIM1T:
+	  set_timer (0, b, clkcount);
+	  break;
+	case TIM8T:
+	  set_timer (3, b, clkcount);
+	  break;
+	case TIM64T:
+	  set_timer (6, b, clkcount);
+	  break;
+	case T1024T:
+	  set_timer (10, b, clkcount);
+	  break;
+	default:
+	  //printf ("Unknown write %x\n", a);
+	  //show ();
+	  break;
+	}
+    }
+}
+
+
+/* Decoded read from memory */
+/* a: address to read */
+/* returns: byte value from address a */
+BYTE
+decRead (ADDRESS a)
+{
+  BYTE res = 65;
+
+  if (a & 0x1000)
+    {
+      a = a & 0xfff;
+      if (base_opts.bank != 0)
+	res= bank_switch_read (a);
+      else
+	res = theRom[a];
+    }
+  else if ((a & 0x280) == 0x80)
+    {
+      res = theRam[a & 0x7f];
+    }
+  else if (!(a & 0x80))
+    {
+      switch (a & 0x0f)
+	{
+	  /* TIA */
+	case CXM0P:
+	  res = (col_state & CXM0P_MASK) << 6;
+	  break;
+	case CXM1P:
+	  res = (col_state & CXM1P_MASK) << 4;
+	  break;
+	case CXP0FB:
+	  res = (col_state & CXP0FB_MASK) << 2;
+	  break;
+	case CXP1FB:
+	  res = (col_state & CXP1FB_MASK);
+	  break;
+	case CXM0FB:
+	  res = (col_state & CXM0FB_MASK) >> 2;
+	  break;
+	case CXM1FB:
+	  res = (col_state & CXM1FB_MASK) >> 4;
+	  break;
+	case CXBLPF:
+	  res = (col_state & CXBLPF_MASK) >> 5;
+	  break;
+	case CXPPMM:
+	  res = (col_state & CXPPMM_MASK) >> 7;
+	  break;
+	case INPT0:
+	  if (base_opts.lcon== PADDLE)
+	    {
+	      tiaRead[INPT0] = do_paddle (0);
+	    }
+	  else if (base_opts.lcon== KEYPAD)
+	    tiaRead[INPT0] = do_keypad (0, 0);
+	  res = tiaRead[INPT0];
+	  break;
+	case INPT1:
+	  if (base_opts.lcon== PADDLE)
+	    {
+	      tiaRead[INPT1] = do_paddle (1);
+	    }
+	  if (base_opts.lcon== KEYPAD)
+	    tiaRead[INPT1]=do_keypad (0, 1);
+	  res = tiaRead[INPT1];
+	  break;
+	case INPT2:
+	  if (base_opts.rcon == KEYPAD)
+	    tiaRead[INPT1]=do_keypad (1, 0);
+	  res = tiaRead[INPT2];
+	  break;
+	case INPT3:
+	  if (base_opts.rcon == KEYPAD)
+	     tiaRead[INPT3]=do_keypad ( 1, 1);
+	  res = tiaRead[INPT3];
+	  break;
+	case INPT4:
+	  switch (base_opts.lcon)
+	    {
+	    case KEYPAD:
+	      tiaRead[INPT4]=do_keypad ( 0, 2);
+	      break;
+	    case STICK:
+		case PADDLE:
+			keytrig();
+			res=tiaRead[INPT4];
+	      break;
+	    }
+	  res =tiaRead[INPT4];
+	  break;
+	case INPT5:
+	  switch (base_opts.rcon)
+	    {
+	    case KEYPAD:
+	      tiaRead[INPT5]=do_keypad (1, 2);
+	      break;
+	    case STICK:
+		case PADDLE:
+			keytrig();
+			res=tiaRead[INPT5];
+	      break;
+	    }
+	  res = tiaRead[INPT5];
+	  break;
+	case 0x0e:
+	case 0x0f:
+	  res = 0x0f;
+	  /* RAM, mapped to page 0 and 1 */
+	}
+    }
+  else
+    {
+      switch (a & 0x2ff)
+	{
+	  /* Timer output */
+	case INTIM:
+	case 0x285:
+	case 0x286:
+	case TIM1T:
+	case TIM8T:
+	case TIM64T:
+	case T1024T:
+	  res = do_timer (clkcount);
+	  /*printf("Timer is %d res is %d\n", res, timer_res); */
+	  break;
+	case SWCHA:
+	  switch (base_opts.lcon)
+	    {
+	    case PADDLE:
+	      if (base_opts.lcon == PADDLE)
+		{
+				keytrig();
+				res=tiaRead[INPT4];
+		}
+	      else if (base_opts.rcon == PADDLE)
+		{
+				keytrig();
+				res=tiaRead[INPT4];
+		}
+	      break;
+	    case STICK:
+				keyjoy();
+				res=riotRead[SWCHA];
+	      break;
+	    }
+	  res = riotRead[SWCHA];
+	  break;
+	  /* Switch B is hardwired to input */
+	case SWCHB:
+	case SWCHB + 0x100:
+	  keycons ();
+	  res = riotRead[SWCHB];
+	  break;
+	default:
+	  //printf ("Unknown read 0x%x\n", a & 0x2ff);
+	  //show ();
+	  res = 65;
+	  break;
+	}
+    }
+  return res;
+}
+
diff --git a/MCUME_pico2/picovcs/Memory.h b/MCUME_pico2/picovcs/Memory.h
new file mode 100644
index 0000000..303c932
--- /dev/null
+++ b/MCUME_pico2/picovcs/Memory.h
@@ -0,0 +1,32 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: memory.h,v 1.5 1996/11/24 16:55:40 ahornby Exp $
+******************************************************************************/
+
+/*
+  Prototypes for the memory interface.
+  */
+
+#ifndef VCSMEMORY_H
+#define VCSMEMORY_H
+
+__inline BYTE 
+undecRead (ADDRESS a);
+
+void 
+decWrite ( ADDRESS a, BYTE b);
+
+BYTE 
+decRead (ADDRESS a);
+
+#endif
diff --git a/MCUME_pico2/picovcs/Options.c b/MCUME_pico2/picovcs/Options.c
new file mode 100644
index 0000000..4ee7a28
--- /dev/null
+++ b/MCUME_pico2/picovcs/Options.c
@@ -0,0 +1,50 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: options.c,v 1.7 1996/11/24 16:55:40 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* Command Line Option Parser */
+#include "config.h"
+#include <stdio.h>
+#include <stdlib.h>
+
+/* *INDENT-OFF* */
+/* Options common to all ports of x2600 */
+struct BaseOptions {
+//  int rr;// unused
+  int tvtype;
+  int lcon;
+  int rcon;
+  int bank;
+  int magstep;
+  char filename[80];
+  int sound;
+  int swap;
+  int realjoy;
+  int limit;
+  int mousey;
+  int mitshm;
+  int dbg_level;
+} base_opts={0,1,1,1,1,"",1,1,1,1,1,0,0};
+
+char *argv[64];
+int argc;
+
+// was written as "(int argc, char **argv)"
+void parse_options(void)
+{  
+//  base_opts.lcon = 1;
+}
+
diff --git a/MCUME_pico2/picovcs/Raster.c b/MCUME_pico2/picovcs/Raster.c
new file mode 100644
index 0000000..5012b33
--- /dev/null
+++ b/MCUME_pico2/picovcs/Raster.c
@@ -0,0 +1,833 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for Details.
+   
+   $Id: raster.c,v 1.30 1997/11/22 14:27:47 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* Raster graphics procedures */
+
+#include <stdio.h>
+#include "btypes.h"
+//#include "systypes.h"
+#include "types.h"
+#include "address.h"
+#include "vmachine.h"
+#include "display.h"
+#include "collision.h"
+#include "options.h"
+
+/* Color lookup tables. Used to speed up rendering */
+/* The current colour lookup table */
+unsigned int *colour_lookup;  
+
+/* Colour table */
+#define P0M0_COLOUR 0
+#define P1M1_COLOUR 1
+#define PFBL_COLOUR 2
+#define BK_COLOUR 3
+
+unsigned int colour_table[4];
+extern BYTE *VBuf;
+
+extern int tv_field;
+extern int nOptions_Interlace;
+extern byte nOptions_SkipFrames;
+
+/* normal/alternate, not scores/scores*/
+int norm_val, scores_val;
+int *colour_ptrs[2][3];
+
+/* Normal priority */
+static int colour_normal[64];
+static int colour_normscoresl[64];
+static int colour_normscoresr[64];
+
+/* Alternate priority */
+static int colour_alternate[64];
+static int colour_altscoresl[64];
+static int colour_altscoresr[64];
+
+/* Playfield screen position */
+uint32 *pf_pos;
+unsigned int line_ptr;//changed
+
+/* Draw playfield register PF0 */
+/* pf: playfield structure */
+/* dir: 1=normal, 0=mirrored */
+__inline void
+draw_pf0 (PlayField *pf, int dir)
+{
+  int pfm;			/* playfield mask */
+  /* 1=forward */
+  if (dir)
+    {
+      for (pfm = 0x10; pfm < 0x100; pfm <<= 1)
+	{
+	  if (pf->pf0 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos++;
+	}
+    }
+  else
+    {
+      for (pfm = 0x80; pfm > 0x08; pfm >>= 1)
+	{
+	  if (pf->pf0 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos++;
+	}
+    }
+}
+
+/* Draw playfield register PF1 */
+/* pf: playfield structure */
+/* dir: 1=normal, 0=mirrored */
+__inline void
+draw_pf1 (PlayField *pf, int dir)
+{
+  int pfm;			/* playfield mask */
+  /* 1=forward */
+  if (dir)
+    {
+      /* do PF1 */
+      for (pfm = 0x80; pfm > 0; pfm >>= 1)
+	{
+	  if (pf->pf1 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos ++;
+	}
+    }
+  else
+    {
+      /* do PF1 */
+      for (pfm = 0x01; pfm < 0x100; pfm <<= 1)
+	{
+	  if (pf->pf1 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos ++;
+	}
+    }
+}
+
+/* Draw playfield register PF2 */
+/* pf: playfield structure */
+/* dir: 1=normal, 0=mirrored */
+__inline void
+draw_pf2 ( PlayField *pf, int dir)
+{
+  int pfm;			/* playfield mask */
+  /* 1=forward */
+  if (dir)
+    {
+      /* do PF2 */
+      for (pfm = 0x01; pfm < 0x100; pfm <<= 1)
+	{
+	  if (pf->pf2 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos ++;
+	}
+    }
+  else
+    {
+      for (pfm = 0x80; pfm > 0; pfm >>= 1)
+	{
+	  if (pf->pf2 & pfm)
+	    *(pf_pos++) = PF_MASK32;
+	  else
+	    pf_pos ++;
+	}
+    }
+}
+
+/* Update from the playfield display list */
+/* num: playfield to use. Now depreciated as only pf[0] is used */
+/* nextx: the start position of the next playfield element */
+/* pfc: the number of the next playfield change structure */
+/* pf_max: the highest playfield change structure */
+__inline void
+pf_update (int num, int nextx, int *pfc, int pf_max)
+{
+  for (; (*pfc < pf_max) && (nextx + 3 > pf_change[num][*pfc].x); (*pfc)++)
+    {
+      use_pfraster_change (&pf[num], &pf_change[num][*pfc]);
+    }
+}
+
+/* Draw the playfield */
+void
+draw_playfield (void)
+{
+  const int num = 0;		/* Stick to one playfield */
+  int pfc = 0;
+  int pf_max = pf_change_count[num];
+
+  pf_pos = (uint32 *)colvect;
+  /* First half of playfield */
+
+  pf_update (num, 0, &pfc, pf_max);
+  draw_pf0 (&pf[0], 1);
+  pf_update (num, 16, &pfc, pf_max);
+  draw_pf1 (&pf[0], 1);
+  pf_update (num, 48, &pfc, pf_max);
+  draw_pf2 (&pf[0], 1);
+
+  pf_update (num, 80, &pfc, pf_max);
+  /* Second half of playfield */
+  if (pf[0].ref)
+    {
+      draw_pf2 (&pf[0], 0);
+      pf_update (num, 112, &pfc, pf_max);
+      draw_pf1 (&pf[0], 0);
+      pf_update (num, 144, &pfc, pf_max);
+      draw_pf0 (&pf[0], 0);
+    }
+  else
+    {
+      draw_pf0 (&pf[0], 1);
+      pf_update (num, 96, &pfc, pf_max);
+      draw_pf1 (&pf[0], 1);
+      pf_update (num, 128, &pfc, pf_max);
+      draw_pf2 (&pf[0], 1);
+    }
+  /* Use last changes */
+  for (; pfc < pf_max; pfc++)
+    use_pfraster_change (&pf[num], &pf_change[num][pfc]);
+
+  pf_change_count[num] = 0;
+}
+
+/* Draws a normal (8 clocks) sized player */
+/* p: the player to draw */
+/* x: the position to draw it */
+__inline void
+pl_normal ( Player *p, int x)
+{
+  /* Set pointer to start of player graphic */
+  BYTE *ptr = colvect + x;
+  BYTE mask;
+  BYTE gr;
+
+  if (p->vdel_flag)
+    gr = p->vdel;
+  else
+    gr = p->grp;
+
+  if (p->reflect)
+    {
+      /* Reflected: start with D0 of GRP on left */
+      for (mask = 0x01; mask > 0; mask <<= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr++;
+	}
+    }
+  else
+    {
+      /* Unreflected: start with D7 of GRP on left */
+      for (mask = 0x80; mask > 0; mask >>= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr++;
+	}
+    }
+}
+
+/* Draws a double width ( 16 clocks ) player */
+/* p: the player to draw */
+/* x: the position to draw it */
+__inline void
+pl_double ( Player *p, int x)
+{
+  /* Set pointer to start of player graphic */
+  BYTE *ptr = colvect + (x);
+  BYTE mask;
+  BYTE gr;
+
+  if (p->vdel_flag)
+    gr = p->vdel;
+  else
+    gr = p->grp;
+
+  if (p->reflect)
+    {
+      for (mask = 0x01; mask > 0; mask <<= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr += 2;
+	}
+    }
+  else
+    {
+      for (mask = 0x80; mask > 0; mask >>= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr += 2;
+	}
+    }
+}
+
+/* Draws a quad sized ( 32 clocks) player */
+/* p: the player to draw */
+/* x: the position to draw it */
+__inline void
+pl_quad ( Player *p, int x)
+{
+  /* Set pointer to start of player graphic */
+  BYTE *ptr = colvect + x;
+  BYTE mask;
+  BYTE gr;
+
+  if (p->vdel_flag)
+    gr = p->vdel;
+  else
+    gr = p->grp;
+
+  if (p->reflect)
+    {
+      for (mask = 0x01; mask > 0; mask <<= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr += 4;
+	}
+    }
+  else
+    {
+      for (mask = 0x80; mask > 0; mask >>= 1)
+	{
+	  if (gr & mask)
+	    {
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	      *(ptr++) |= p->mask;
+	    }
+	  else
+	    ptr += 4;
+	}
+    }
+}
+
+/* Consume the player display list */
+__inline void
+pl_update (int num, int nextx, int *plc, int pl_max)
+{
+  for (; (*plc < pl_max) && (nextx > pl_change[num][*plc].x); (*plc)++)
+    {
+      use_plraster_change (&pl[num], &pl_change[num][*plc]);
+    }
+}
+
+/* Draw a player graphic */
+/* line: the vertical position of the raster */
+/* num: the number of player to draw, current 0 or 1 for P0 and P1 */
+static __inline void
+pl_draw (int num)
+{
+  int plc = 0;
+  int pl_max = pl_change_count[num];
+  int nextx;
+
+  pl_update (num, pl[num].x, &plc, pl_max);
+  if (pl[num].x >= 0 && pl[num].x < tv_width)
+    {
+
+      /*if(pl_max > plc)
+         use_plraster_change( &pl[num], &pl_change[num][plc++]); */
+      switch (pl[num].nusize)
+	{
+	case 0:
+	  /* One copy */
+	  pl_normal (&pl[num], pl[num].x);
+	  break;
+	case 1:
+	  /* Two copies close */
+	  pl_normal (&pl[num], pl[num].x);
+	  nextx = pl[num].x + 8 + 8;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+	  break;
+	case 2:
+	  /* Two copies medium */
+	  pl_normal (&pl[num], pl[num].x);
+	  nextx = pl[num].x + 8 + 24;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+	  break;
+	case 3:
+	  /* Three copies close */
+	  /* Pacman score line */
+	  pl_normal (&pl[num], pl[num].x);
+
+	  nextx = pl[num].x + 16;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+
+	  nextx = pl[num].x + 32;
+	  pl_update (num, nextx, &plc, pl_max);
+
+	  pl_normal (&pl[num], nextx);
+	  break;
+	case 4:
+	  /* Two copies wide */
+	  pl_normal (&pl[num], pl[num].x);
+	  nextx = pl[num].x + 8 + 56;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+	  break;
+	case 5:
+	  /* Double sized player */
+	  pl_double (&pl[num], pl[num].x);
+	  break;
+	case 6:
+	  /* Three copies medium */
+	  pl_normal (&pl[num], pl[num].x);
+	  nextx = pl[num].x + 8 + 24;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+	  nextx = pl[num].x + 8 + 56;
+	  pl_update (num, nextx, &plc, pl_max);
+	  pl_normal (&pl[num], nextx);
+	  break;
+	case 7:
+	  /* Quad sized player */
+	  pl_quad (&pl[num], pl[num].x);
+	  break;
+	}
+    }
+  /* Use last changes */
+  for (; plc < pl_max; plc++)
+    use_plraster_change (&pl[num], &pl_change[num][plc]);
+  pl_change_count[num] = 0;
+}
+
+
+/* Draw the ball graphic */
+/* line: the vertical position of the raster */
+static __inline void
+draw_ball (void)
+{
+  int i;
+  BYTE *blptr;
+  BYTE e;
+
+  if (ml[2].vdel_flag)
+    e = ml[2].vdel;
+  else
+    e = ml[2].enabled;
+
+  if (e && ml[2].x >= 0)
+    {
+      blptr = colvect + (ml[2].x);
+      switch (tiaWrite[CTRLPF] >> 4)
+	{
+	case 3:
+	  /* Eight clocks */
+	  for (i = 0; i < 8; i++)
+	    *(blptr++) |= BL_MASK;
+	  break;
+	case 2:
+	  /* Four clocks */
+	  for (i = 0; i < 4; i++)
+	    *(blptr++) |= BL_MASK;
+	  break;
+	case 1:
+	  /* Two clocks */
+	  for (i = 0; i < 2; i++)
+	    *(blptr++) |= BL_MASK;
+	  break;
+	case 0:
+	  /* One clock */
+	  *(blptr++) |= BL_MASK;
+	  break;
+	}
+    }
+}
+
+
+/* Draw a missile graphic */
+static __inline void
+do_missile (int num, BYTE * misptr)
+{
+  int i;
+
+  switch (ml[num].width)
+    {
+    case 0:
+      /* one clock */
+      *(misptr++) |= ml[num].mask;
+      break;
+    case 1:
+      /* two clocks */
+      for (i = 0; i < 2; i++)
+	*(misptr++) |= ml[num].mask;
+      break;
+    case 2:
+      /* four clocks */
+      for (i = 0; i < 4; i++)
+	*(misptr++) |= ml[num].mask;
+      break;
+    case 3:
+      /* Eight clocks */
+      for (i = 0; i < 8; i++)
+	*(misptr++) |= ml[num].mask;
+      break;
+    }				/* switch */
+}
+
+/* Draw a missile taking into account the player's position. */
+/* line: the vertical position of the raster */
+/* num: 0 for M0, 1 for M1 */
+static __inline void
+draw_missile (int num)
+{
+  BYTE *misptr;
+
+  if (ml[num].enabled && ml[num].x >= 0)
+    {
+      switch (pl[num].nusize)
+	{
+	case 0:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  break;
+	case 1:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  misptr = misptr + 16;
+	  do_missile (num, misptr);
+	  break;
+	case 2:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  misptr = misptr + 32;
+	  do_missile (num, misptr);
+	  break;
+	case 3:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  misptr = misptr + 16;
+	  do_missile (num, misptr);
+	  misptr = misptr + 16;
+	  do_missile (num, misptr);
+	  break;
+	case 4:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  misptr = misptr + 64;
+	  do_missile (num, misptr);
+	  break;
+	case 5:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  break;
+	case 6:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  misptr = misptr + 32;
+	  do_missile (num, misptr);
+	  misptr = misptr + 32;
+	  do_missile (num, misptr);
+	  break;
+	case 7:
+	  misptr = colvect + (ml[num].x);
+	  do_missile (num, misptr);
+	  break;
+
+	}
+
+    }				/* If */
+}
+
+
+/* Construct one tv raster line colvect */
+/* line: the vertical position of the raster */
+__inline void
+tv_rasterise (int line)
+{
+
+//  if (tv_field && nOptions_Interlace) line +=222;
+  line_ptr = line * vwidth;
+
+  /* Draw the playfield first */
+  draw_playfield (); 
+  
+  /* Do the ball */
+  draw_ball ();
+  
+  /* Do the player 1 graphics */
+  draw_missile (1);
+  pl_draw (1);
+  
+  /* Do the player 0 graphics */
+  draw_missile (0);
+  pl_draw (0);
+}
+
+/* Reset the collision vector */
+__inline void
+reset_vector (void)
+{
+  int i;
+  uint32 *cpos=(uint32 *)colvect;
+  for (i = 0; i < 40; i++)
+    cpos[i] = 0; 
+}
+
+
+/* draw the collision vector */
+/* Quick version with no magnification */
+__inline void
+draw_vector_q (void)
+{
+  int i;
+  int uct = 0;
+  int colind, colval;
+  unsigned int pad;
+  unsigned int tv_ptr;
+  tv_ptr=line_ptr;
+  
+  /* Check for scores */
+  if(scores_val ==2) 
+    {
+      scores_val=1;
+      colour_lookup=colour_ptrs[norm_val][scores_val];
+    }
+
+  /* Use starting changes */
+  while (uct < unified_count && unified[uct].x < 0)
+    use_unified_change (&unified[uct++]);
+
+  for (i = 0; i < 80; i++)
+    {
+      if (uct < unified_count && unified[uct].x == i)
+	use_unified_change (&unified[uct++]);
+      
+      if((colval=colvect[i])){
+	
+	/* Collision detection */
+	col_state|=col_table[colval];
+	
+	colind=colour_lookup[colval];
+	pad=colour_table[colind];
+      } else
+	pad=colour_table[BK_COLOUR];      
+
+      VBuf[tv_ptr++] = pad;
+    }
+
+  /* Check for scores */
+  if(scores_val ==1)
+    {
+      scores_val=2;
+      colour_lookup=colour_ptrs[norm_val][scores_val];
+    }
+  for (i = 80; i < 160; i++)
+    {
+      if (uct < unified_count && unified[uct].x == i)
+	use_unified_change (&unified[uct++]);
+      
+      if((colval=colvect[i])){
+	
+	/* Collision detection */
+	col_state|=col_table[colval];
+	
+	colind=colour_lookup[colval];
+	pad=colour_table[colind];
+      } else
+	pad=colour_table[BK_COLOUR];      
+
+      VBuf[tv_ptr++] = pad;
+    }
+
+  while (uct < unified_count)
+    use_unified_change (&unified[uct++]);
+  unified_count = 0;
+}
+
+/* Used for when running in frame skipping mode */
+static __inline void
+update_registers (void)
+{
+  int i, num;
+
+  /* Playfield */
+  for (i = 0; i < pf_change_count[0]; i++)
+    use_pfraster_change (&pf[0], &pf_change[0][i]);
+  pf_change_count[0] = 0;
+
+  /* Player graphics */
+  for (num = 0; num < 2; num++)
+    {
+      for (i = 0; i < pl_change_count[num]; i++)
+	use_plraster_change (&pl[num], &pl_change[num][i]);
+      pl_change_count[num] = 0;
+    }
+
+  /* Unified */
+  for (i = 0; i < unified_count; i++)
+    use_unified_change (&unified[i]);
+  unified_count = 0;
+}
+
+/* Main raster function, will have switches for different magsteps */
+/* line: the vertical position of the raster */
+void
+tv_raster (int line)
+{
+//  if ( ((tv_counter % nOptions_SkipFrames) != 0)  || (line > theight) )
+  if (line > theight)
+  {
+      update_registers ();
+  }
+  else
+  {
+      reset_vector();
+      tv_rasterise (line);
+      draw_vector_q ();
+  }
+}
+
+void
+init_raster (void)
+{
+  int i,val;
+
+  init_collisions();
+
+  /* Normal Priority */
+  for (i=0; i<64; i++)
+    {
+      if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else if (i & (BL_MASK | PF_MASK))
+	val = PFBL_COLOUR;
+      else
+	val = BK_COLOUR;     
+      colour_normal[i]=val;
+    }
+
+  /* Alternate Priority */
+  for (i=0; i<64; i++)
+    {  
+      if (i & (BL_MASK | PF_MASK))
+	val = PFBL_COLOUR;
+      else if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else
+	val = BK_COLOUR;
+      colour_alternate[i]=val;
+    }
+
+  /* Normal Scores Left */
+  for (i=0; i<64; i++)
+    {
+      if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else if (i & (BL_MASK | PF_MASK))
+	/* Use P1 colour */
+	val = P0M0_COLOUR;
+      else
+	val = BK_COLOUR;     
+      colour_normscoresl[i]=val;
+    }
+  
+  /* Normal Scores Right */
+  for (i=0; i<64; i++)
+    {
+      if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else if (i & (BL_MASK | PF_MASK))
+	/* Use P1 colour */
+	val = P1M1_COLOUR;
+      else
+	val = BK_COLOUR;     
+      colour_normscoresr[i]=val;
+    }
+
+  /* Alternate Scores Left*/
+  for (i=0; i<64; i++)
+    {  
+      if (i & (BL_MASK | PF_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else
+	val = BK_COLOUR;
+      colour_altscoresl[i]=val;
+    }
+
+  /* Alternate Scores Right*/
+  for (i=0; i<64; i++)
+    {  
+      if (i & (BL_MASK | PF_MASK))
+	val = P1M1_COLOUR;
+      else if (i & (PL0_MASK | ML0_MASK))
+	val = P0M0_COLOUR;
+      else if (i & (PL1_MASK | ML1_MASK))
+	val = P1M1_COLOUR;
+      else
+	val = BK_COLOUR;
+      colour_altscoresr[i]=val;
+    }
+  
+  colour_ptrs[0][0]=colour_normal;
+  colour_ptrs[1][0]=colour_alternate;
+  colour_ptrs[0][1]=colour_normscoresl;
+  colour_ptrs[1][1]=colour_altscoresl;
+  colour_ptrs[0][2]=colour_normscoresr;
+  colour_ptrs[1][2]=colour_altscoresr;
+  norm_val=0; scores_val=0;
+
+  colour_lookup=colour_normal;
+}
diff --git a/MCUME_pico2/picovcs/Table.c b/MCUME_pico2/picovcs/Table.c
new file mode 100644
index 0000000..67d9232
--- /dev/null
+++ b/MCUME_pico2/picovcs/Table.c
@@ -0,0 +1,646 @@
+
+
+
+
+
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for Details.
+   
+   $Id: table.c,v 1.4 1996/08/26 15:04:20 ahornby Exp $
+******************************************************************************/
+
+/*
+ * $Id: table.c,v 1.4 1996/08/26 15:04:20 ahornby Exp $
+ *
+ * This was part of the x64 Commodore 64 emulator.
+ * See README for copyright notice
+ *
+ * This file contains lookup-table which is used to translate
+ * MOS6502 machine instructions. Machine code is used as index
+ * to array called lookup. Pointer to function is then fetched
+ * from array and function is called.
+ * Timing of the undocumented opcodes is based on information
+ * in an article in C=Lehti by Kai Lindfors and Topi Maurola.
+ *
+ *
+ * Written by
+ *   Vesa-Matti Puro (vmp@lut.fi)
+ *   Jarkko Sonninen (sonninen@lut.fi)
+ *   Jouko Valta (jopi@stekt.oulu.fi)
+ *
+ */
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+#include "cpu.h"
+#include "mnemonic.h"
+
+
+/*
+ * The "mnemonic.h" file contains #defines for BRK, ORA, NOOP... which
+ * are character strings, i.e. #define BRK    "BRK"
+ * #define ORA    "ORA" . . . Used mainly to reduce typing...
+ *
+ * There are #defines for addressing modes i.e. IMPLIED, INDIRECT_X,
+ * ZERO_PAGE in "cpu.h"... These can be used to make a diassembler.
+ */
+
+#define PROGMEM
+
+PROGMEM int clength[] =
+{1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 0};
+
+PROGMEM struct lookup_tag lookup[] =
+{
+
+/****  Positive  ****/
+
+    /* 00 */
+  {BRK, IMPLIED, M_NONE, M_PC, 7, 0},	/* Pseudo Absolute */
+    /* 01 */
+  {ORA, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (Indirect,X) */
+    /* 02 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 03 */
+  {SLO, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* 04 */
+  {NOOP, ZERO_PAGE, M_NONE, M_NONE, 3, 0},
+    /* 05 */
+  {ORA, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* 06 */
+  {ASL, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* 07 */
+  {SLO, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* 08 */
+  {PHP, IMPLIED, M_SR, M_NONE, 3, 0},
+    /* 09 */
+  {ORA, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* 0a */
+  {ASL, ACCUMULATOR, M_AC, M_AC, 2, 0},		/* Accumulator */
+    /* 0b */
+  {ANC, IMMEDIATE, M_ACIM, M_ACNC, 2, 0},
+
+    /* 0c */
+  {NOOP, ABSOLUTE, M_NONE, M_NONE, 4, 0},
+    /* 0d */
+  {ORA, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* 0e */
+  {ASL, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* 0f */
+  {SLO, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* 10 */
+  {BPL, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* 11 */
+  {ORA, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (Indirect),Y */
+    /* 12 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 13 */
+  {SLO, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* 14 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* 15 */
+  {ORA, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* 16 */
+  {ASL, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* 17 */
+  {SLO, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* 18 */
+  {CLC, IMPLIED, M_NONE, M_FC, 2, 0},
+    /* 19 */
+  {ORA, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* 1a */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* 1b */
+  {SLO, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* 1c */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* 1d */
+  {ORA, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* 1e */
+  {ASL, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* 1f */
+  {SLO, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},
+
+    /* 20 */
+  {JSR, ABSOLUTE, M_ADDR, M_PC, 6, 0},
+    /* 21 */
+  {AND, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (Indirect ,X) */
+    /* 22 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 23 */
+  {RLA, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* 24 */
+  {BIT, ZERO_PAGE, M_ZERO, M_NONE, 3, 0},	/* Zeropage */
+    /* 25 */
+  {AND, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* 26 */
+  {ROL, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* 27 */
+  {RLA, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* 28 */
+  {PLP, IMPLIED, M_NONE, M_SR, 4, 0},
+    /* 29 */
+  {AND, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* 2a */
+  {ROL, ACCUMULATOR, M_AC, M_AC, 2, 0},		/* Accumulator */
+    /* 2b */
+  {ANC, IMMEDIATE, M_ACIM, M_ACNC, 2, 0},
+
+    /* 2c */
+  {BIT, ABSOLUTE, M_ABS, M_NONE, 4, 0},		/* Absolute */
+    /* 2d */
+  {AND, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* 2e */
+  {ROL, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* 2f */
+  {RLA, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* 30 */
+  {BMI, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* 31 */
+  {AND, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (Indirect),Y */
+    /* 32 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 33 */
+  {RLA, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* 34 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* 35 */
+  {AND, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* 36 */
+  {ROL, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* 37 */
+  {RLA, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* 38 */
+  {SEC, IMPLIED, M_NONE, M_FC, 2, 0},
+    /* 39 */
+  {AND, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* 3a */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* 3b */
+  {RLA, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* 3c */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* 3d */
+  {AND, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* 3e */
+  {ROL, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* 3f */
+  {RLA, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},
+
+    /* 40 */
+  {RTI, IMPLIED, M_NONE, M_PC, 6, 0},
+    /* 41 */
+  {EOR, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (Indirect,X) */
+    /* 42 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 43 */
+  {SRE, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* 44 */
+  {NOOP, ZERO_PAGE, M_NONE, M_NONE, 3, 0},
+    /* 45 */
+  {EOR, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* 46 */
+  {LSR, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* 47 */
+  {SRE, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* 48 */
+  {PHA, IMPLIED, M_AC, M_NONE, 3, 0},
+    /* 49 */
+  {EOR, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* 4a */
+  {LSR, ACCUMULATOR, M_AC, M_AC, 2, 0},		/* Accumulator */
+    /* 4b */
+  {ASR, IMMEDIATE, M_ACIM, M_AC, 2, 0},		/* (AC & IMM) >>1 */
+
+    /* 4c */
+  {JMP, ABSOLUTE, M_ADDR, M_PC, 3, 0},	/* Absolute */
+    /* 4d */
+  {EOR, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* 4e */
+  {LSR, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* 4f */
+  {SRE, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* 50 */
+  {BVC, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* 51 */
+  {EOR, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (Indirect),Y */
+    /* 52 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 53 */
+  {SRE, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* 54 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* 55 */
+  {EOR, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* 56 */
+  {LSR, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* 57 */
+  {SRE, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* 58 */
+  {CLI, IMPLIED, M_NONE, M_FI, 2, 0},
+    /* 59 */
+  {EOR, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* 5a */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* 5b */
+  {SRE, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* 5c */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* 5d */
+  {EOR, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* 5e */
+  {LSR, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* 5f */
+  {SRE, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},
+
+    /* 60 */
+  {RTS, IMPLIED, M_NONE, M_PC, 6, 0},
+    /* 61 */
+  {ADC, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (Indirect,X) */
+    /* 62 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* 63 */
+  {RRA, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* 64 */
+  {NOOP, ZERO_PAGE, M_NONE, M_NONE, 3, 0},
+    /* 65 */
+  {ADC, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* 66 */
+  {ROR, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* 67 */
+  {RRA, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* 68 */
+  {PLA, IMPLIED, M_NONE, M_AC, 4, 0},
+    /* 69 */
+  {ADC, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* 6a */
+  {ROR, ACCUMULATOR, M_AC, M_AC, 2, 0},		/* Accumulator */
+    /* 6b */
+  {ARR, IMMEDIATE, M_ACIM, M_AC, 2, 0},		/* ARR isn't typo */
+
+    /* 6c */
+  {JMP, ABS_INDIRECT, M_AIND, M_PC, 5, 0},	/* Indirect */
+    /* 6d */
+  {ADC, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* 6e */
+  {ROR, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* 6f */
+  {RRA, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* 70 */
+  {BVS, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* 71 */
+  {ADC, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (Indirect),Y */
+    /* 72 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT relative? */
+    /* 73 */
+  {RRA, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* 74 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* 75 */
+  {ADC, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* 76 */
+  {ROR, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* 77 */
+  {RRA, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* 78 */
+  {SEI, IMPLIED, M_NONE, M_FI, 2, 0},
+    /* 79 */
+  {ADC, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* 7a */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* 7b */
+  {RRA, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* 7c */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* 7d */
+  {ADC, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* 7e */
+  {ROR, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* 7f */
+  {RRA, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},
+
+/****  Negative  ****/
+
+    /* 80 */
+  {NOOP, IMMEDIATE, M_NONE, M_NONE, 2, 0},
+    /* 81 */
+  {STA, INDIRECT_X, M_AC, M_INDX, 6, 0},	/* (Indirect,X) */
+    /* 82 */
+  {NOOP, IMMEDIATE, M_NONE, M_NONE, 2, 0},
+    /* 83 */
+  {SAX, INDIRECT_X, M_ANXR, M_INDX, 6, 0},
+
+    /* 84 */
+  {STY, ZERO_PAGE, M_YR, M_ZERO, 3, 0},		/* Zeropage */
+    /* 85 */
+  {STA, ZERO_PAGE, M_AC, M_ZERO, 3, 0},		/* Zeropage */
+    /* 86 */
+  {STX, ZERO_PAGE, M_XR, M_ZERO, 3, 0},		/* Zeropage */
+    /* 87 */
+  {SAX, ZERO_PAGE, M_ANXR, M_ZERO, 3, 0},
+
+    /* 88 */
+  {DEY, IMPLIED, M_YR, M_YR, 2, 0},
+    /* 89 */
+  {NOOP, IMMEDIATE, M_NONE, M_NONE, 2, 0},
+    /* 8a */
+  {TXA, IMPLIED, M_XR, M_AC, 2, 0},
+/****  very abnormal: usually AC = AC | #$EE & XR & #$oper  ****/
+    /* 8b */
+  {ANE, IMMEDIATE, M_AXIM, M_AC, 2, 0},
+
+    /* 8c */
+  {STY, ABSOLUTE, M_YR, M_ABS, 4, 0},	/* Absolute */
+    /* 8d */
+  {STA, ABSOLUTE, M_AC, M_ABS, 4, 0},	/* Absolute */
+    /* 8e */
+  {STX, ABSOLUTE, M_XR, M_ABS, 4, 0},	/* Absolute */
+    /* 8f */
+  {SAX, ABSOLUTE, M_ANXR, M_ABS, 4, 0},
+
+    /* 90 */
+  {BCC, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* 91 */
+  {STA, INDIRECT_Y, M_AC, M_INDY, 6, 0},	/* (Indirect),Y */
+    /* 92 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT relative? */
+    /* 93 */
+  {SHA, INDIRECT_Y, M_ANXR, M_STH0, 6, 0},
+
+    /* 94 */
+  {STY, ZERO_PAGE_X, M_YR, M_ZERX, 4, 0},	/* Zeropage,X */
+    /* 95 */
+  {STA, ZERO_PAGE_X, M_AC, M_ZERX, 4, 0},	/* Zeropage,X */
+    /* 96 */
+  {STX, ZERO_PAGE_Y, M_XR, M_ZERY, 4, 0},	/* Zeropage,Y */
+    /* 97 */
+  {SAX, ZERO_PAGE_Y, M_ANXR, M_ZERY, 4, 0},
+
+    /* 98 */
+  {TYA, IMPLIED, M_YR, M_AC, 2, 0},
+    /* 99 */
+  {STA, ABSOLUTE_Y, M_AC, M_ABSY, 5, 0},	/* Absolute,Y */
+    /* 9a */
+  {TXS, IMPLIED, M_XR, M_SP, 2, 0},
+/*** This is very mysterious command ... */
+    /* 9b */
+  {SHS, ABSOLUTE_Y, M_ANXR, M_STH3, 5, 0},
+
+    /* 9c */
+  {SHY, ABSOLUTE_X, M_YR, M_STH2, 5, 0},
+    /* 9d */
+  {STA, ABSOLUTE_X, M_AC, M_ABSX, 5, 0},	/* Absolute,X */
+    /* 9e */
+  {SHX, ABSOLUTE_Y, M_XR, M_STH1, 5, 0},
+    /* 9f */
+  {SHA, ABSOLUTE_Y, M_ANXR, M_STH1, 5, 0},
+
+    /* a0 */
+  {LDY, IMMEDIATE, M_IMM, M_YR, 2, 0},	/* Immediate */
+    /* a1 */
+  {LDA, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (indirect,X) */
+    /* a2 */
+  {LDX, IMMEDIATE, M_IMM, M_XR, 2, 0},	/* Immediate */
+    /* a3 */
+  {LAX, INDIRECT_X, M_INDX, M_ACXR, 6, 0},	/* (indirect,X) */
+
+    /* a4 */
+  {LDY, ZERO_PAGE, M_ZERO, M_YR, 3, 0},		/* Zeropage */
+    /* a5 */
+  {LDA, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* a6 */
+  {LDX, ZERO_PAGE, M_ZERO, M_XR, 3, 0},		/* Zeropage */
+    /* a7 */
+  {LAX, ZERO_PAGE, M_ZERO, M_ACXR, 3, 0},
+
+    /* a8 */
+  {TAY, IMPLIED, M_AC, M_YR, 2, 0},
+    /* a9 */
+  {LDA, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* aa */
+  {TAX, IMPLIED, M_AC, M_XR, 2, 0},
+    /* ab */
+  {LXA, IMMEDIATE, M_ACIM, M_ACXR, 2, 0},	/* LXA isn't a typo */
+
+    /* ac */
+  {LDY, ABSOLUTE, M_ABS, M_YR, 4, 0},	/* Absolute */
+    /* ad */
+  {LDA, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* ae */
+  {LDX, ABSOLUTE, M_ABS, M_XR, 4, 0},	/* Absolute */
+    /* af */
+  {LAX, ABSOLUTE, M_ABS, M_ACXR, 4, 0},
+
+    /* b0 */
+  {BCS, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* b1 */
+  {LDA, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (indirect),Y */
+    /* b2 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* b3 */
+  {LAX, INDIRECT_Y, M_INDY, M_ACXR, 5, 1},
+
+    /* b4 */
+  {LDY, ZERO_PAGE_X, M_ZERX, M_YR, 4, 0},	/* Zeropage,X */
+    /* b5 */
+  {LDA, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* b6 */
+  {LDX, ZERO_PAGE_Y, M_ZERY, M_XR, 4, 0},	/* Zeropage,Y */
+    /* b7 */
+  {LAX, ZERO_PAGE_Y, M_ZERY, M_ACXR, 4, 0},
+
+    /* b8 */
+  {CLV, IMPLIED, M_NONE, M_FV, 2, 0},
+    /* b9 */
+  {LDA, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* ba */
+  {TSX, IMPLIED, M_SP, M_XR, 2, 0},
+    /* bb */
+  {LAS, ABSOLUTE_Y, M_SABY, M_ACXS, 4, 1},
+
+    /* bc */
+  {LDY, ABSOLUTE_X, M_ABSX, M_YR, 4, 1},	/* Absolute,X */
+    /* bd */
+  {LDA, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* be */
+  {LDX, ABSOLUTE_Y, M_ABSY, M_XR, 4, 1},	/* Absolute,Y */
+    /* bf */
+  {LAX, ABSOLUTE_Y, M_ABSY, M_ACXR, 4, 1},
+
+    /* c0 */
+  {CPY, IMMEDIATE, M_IMM, M_NONE, 2, 0},	/* Immediate */
+    /* c1 */
+  {CMP, INDIRECT_X, M_INDX, M_NONE, 6, 0},	/* (Indirect,X) */
+    /* c2 */
+  {NOOP, IMMEDIATE, M_NONE, M_NONE, 2, 0},	/* occasional TILT */
+    /* c3 */
+  {DCP, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* c4 */
+  {CPY, ZERO_PAGE, M_ZERO, M_NONE, 3, 0},	/* Zeropage */
+    /* c5 */
+  {CMP, ZERO_PAGE, M_ZERO, M_NONE, 3, 0},	/* Zeropage */
+    /* c6 */
+  {DEC, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* c7 */
+  {DCP, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* c8 */
+  {INY, IMPLIED, M_YR, M_YR, 2, 0},
+    /* c9 */
+  {CMP, IMMEDIATE, M_IMM, M_NONE, 2, 0},	/* Immediate */
+    /* ca */
+  {DEX, IMPLIED, M_XR, M_XR, 2, 0},
+    /* cb */
+  {SBX, IMMEDIATE, M_IMM, M_XR, 2, 0},
+
+    /* cc */
+  {CPY, ABSOLUTE, M_ABS, M_NONE, 4, 0},		/* Absolute */
+    /* cd */
+  {CMP, ABSOLUTE, M_ABS, M_NONE, 4, 0},		/* Absolute */
+    /* ce */
+  {DEC, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* cf */
+  {DCP, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* d0 */
+  {BNE, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* d1 */
+  {CMP, INDIRECT_Y, M_INDY, M_NONE, 5, 1},	/* (Indirect),Y */
+    /* d2 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* d3 */
+  {DCP, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* d4 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* d5 */
+  {CMP, ZERO_PAGE_X, M_ZERX, M_NONE, 4, 0},	/* Zeropage,X */
+    /* d6 */
+  {DEC, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* d7 */
+  {DCP, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* d8 */
+  {CLD, IMPLIED, M_NONE, M_FD, 2, 0},
+    /* d9 */
+  {CMP, ABSOLUTE_Y, M_ABSY, M_NONE, 4, 1},	/* Absolute,Y */
+    /* da */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* db */
+  {DCP, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* dc */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* dd */
+  {CMP, ABSOLUTE_X, M_ABSX, M_NONE, 4, 1},	/* Absolute,X */
+    /* de */
+  {DEC, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* df */
+  {DCP, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},
+
+    /* e0 */
+  {CPX, IMMEDIATE, M_IMM, M_NONE, 2, 0},	/* Immediate */
+    /* e1 */
+  {SBC, INDIRECT_X, M_INDX, M_AC, 6, 0},	/* (Indirect,X) */
+    /* e2 */
+  {NOOP, IMMEDIATE, M_NONE, M_NONE, 2, 0},
+    /* e3 */
+  {ISB, INDIRECT_X, M_INDX, M_INDX, 8, 0},
+
+    /* e4 */
+  {CPX, ZERO_PAGE, M_ZERO, M_NONE, 3, 0},	/* Zeropage */
+    /* e5 */
+  {SBC, ZERO_PAGE, M_ZERO, M_AC, 3, 0},		/* Zeropage */
+    /* e6 */
+  {INC, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},	/* Zeropage */
+    /* e7 */
+  {ISB, ZERO_PAGE, M_ZERO, M_ZERO, 5, 0},
+
+    /* e8 */
+  {INX, IMPLIED, M_XR, M_XR, 2, 0},
+    /* e9 */
+  {SBC, IMMEDIATE, M_IMM, M_AC, 2, 0},	/* Immediate */
+    /* ea */
+  {NOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* eb */
+  {USBC, IMMEDIATE, M_IMM, M_AC, 2, 0},		/* same as e9 */
+
+    /* ec */
+  {CPX, ABSOLUTE, M_ABS, M_NONE, 4, 0},		/* Absolute */
+    /* ed */
+  {SBC, ABSOLUTE, M_ABS, M_AC, 4, 0},	/* Absolute */
+    /* ee */
+  {INC, ABSOLUTE, M_ABS, M_ABS, 6, 0},	/* Absolute */
+    /* ef */
+  {ISB, ABSOLUTE, M_ABS, M_ABS, 6, 0},
+
+    /* f0 */
+  {BEQ, RELATIVE, M_REL, M_NONE, 2, 0},
+    /* f1 */
+  {SBC, INDIRECT_Y, M_INDY, M_AC, 5, 1},	/* (Indirect),Y */
+    /* f2 */
+  {JAM, IMPLIED, M_NONE, M_NONE, 0, 0},		/* TILT */
+    /* f3 */
+  {ISB, INDIRECT_Y, M_INDY, M_INDY, 8, 0},
+
+    /* f4 */
+  {NOOP, ZERO_PAGE_X, M_NONE, M_NONE, 4, 0},
+    /* f5 */
+  {SBC, ZERO_PAGE_X, M_ZERX, M_AC, 4, 0},	/* Zeropage,X */
+    /* f6 */
+  {INC, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},	/* Zeropage,X */
+    /* f7 */
+  {ISB, ZERO_PAGE_X, M_ZERX, M_ZERX, 6, 0},
+
+    /* f8 */
+  {SED, IMPLIED, M_NONE, M_FD, 2, 0},
+    /* f9 */
+  {SBC, ABSOLUTE_Y, M_ABSY, M_AC, 4, 1},	/* Absolute,Y */
+    /* fa */
+  {NOOP, IMPLIED, M_NONE, M_NONE, 2, 0},
+    /* fb */
+  {ISB, ABSOLUTE_Y, M_ABSY, M_ABSY, 7, 0},
+
+    /* fc */
+  {NOOP, ABSOLUTE_X, M_NONE, M_NONE, 4, 1},
+    /* fd */
+  {SBC, ABSOLUTE_X, M_ABSX, M_AC, 4, 1},	/* Absolute,X */
+    /* fe */
+  {INC, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0},	/* Absolute,X */
+    /* ff */
+  {ISB, ABSOLUTE_X, M_ABSX, M_ABSX, 7, 0}
+};
diff --git a/MCUME_pico2/picovcs/Tiasound.c b/MCUME_pico2/picovcs/Tiasound.c
new file mode 100644
index 0000000..1d87b6c
--- /dev/null
+++ b/MCUME_pico2/picovcs/Tiasound.c
@@ -0,0 +1,616 @@
+/*****************************************************************************/
+/*                                                                           */
+/* Module:  TIA Chip Sound Simulator                                         */
+/* Purpose: To emulate the sound generation hardware of the Atari TIA chip.  */
+/* Author:  Ron Fries                                                        */
+/*                                                                           */
+/* Revision History:                                                         */
+/*    10-Sep-96 - V1.0 - Initial Release                                     */
+/*    14-Jan-97 - V1.1 - Cleaned up sound output by eliminating counter      */
+/*                       reset.                                              */
+/*                                                                           */
+/*****************************************************************************/
+/*                                                                           */
+/*                 License Information and Copyright Notice                  */
+/*                 ========================================                  */
+/*                                                                           */
+/* TiaSound is Copyright(c) 1996 by Ron Fries                                */
+/*                                                                           */
+/* This library is free software; you can redistribute it and/or modify it   */
+/* under the terms of version 2 of the GNU Library General Public License    */
+/* as published by the Free Software Foundation.                             */
+/*                                                                           */
+/* This library is distributed in the hope that it will be useful, but       */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of                */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Library */
+/* General Public License for more details.                                  */
+/* To obtain a copy of the GNU Library General Public License, write to the  */
+/* Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.   */
+/*                                                                           */
+/* Any permitted reproduction of these routines, in whole or in part, must   */
+/* bear this legend.                                                         */
+/*                                                                           */
+/*****************************************************************************/
+#include "Atari2600EmulatorGlobals.h"
+
+#include "emuapi.h"
+
+
+/* define some data types to keep it platform independent */
+#define int8  char
+#define int16 short
+#define int32 int
+
+#define uint8  unsigned int8 
+#define uint16 unsigned int16
+#define uint32 unsigned int32
+
+
+/* CONSTANT DEFINITIONS */
+
+/* definitions for AUDCx (15, 16) */
+#define SET_TO_1     0x00      /* 0000 */
+#define POLY4        0x01      /* 0001 */
+#define DIV31_POLY4  0x02      /* 0010 */
+#define POLY5_POLY4  0x03      /* 0011 */
+#define PURE1         0x04      /* 0100 */
+#define PURE2        0x05      /* 0101 */
+#define DIV31_PURE   0x06      /* 0110 */
+#define POLY5_2      0x07      /* 0111 */
+#define POLY9        0x08      /* 1000 */
+#define POLY5        0x09      /* 1001 */
+#define DIV31_POLY5  0x0a      /* 1010 */
+#define POLY5_POLY5  0x0b      /* 1011 */
+#define DIV3_PURE    0x0c      /* 1100 */
+#define DIV3_PURE2   0x0d      /* 1101 */
+#define DIV93_PURE   0x0e      /* 1110 */
+#define DIV3_POLY5   0x0f      /* 1111 */
+                 
+#define DIV3_MASK    0x0c                 
+                 
+#define AUDC0        0x15
+#define AUDC1        0x16
+#define AUDF0        0x17
+#define AUDF1        0x18
+#define AUDV0        0x19
+#define AUDV1        0x1a
+
+/* the size (in entries) of the 4 polynomial tables */
+#define POLY4_SIZE  0x000f
+#define POLY5_SIZE  0x001f
+#define POLY9_SIZE  0x01ff
+
+/* channel definitions */
+#define CHAN1       0
+#define CHAN2       1
+
+//#define FALSE       0
+//#define TRUE        1
+
+
+/* LOCAL GLOBAL VARIABLE DEFINITIONS */
+
+/* structures to hold the 6 tia sound control bytes */
+uint8 AUDC[2];    /* AUDCx (15, 16) */
+uint8 AUDF[2];    /* AUDFx (17, 18) */
+uint8 AUDV[2];    /* AUDVx (19, 1A) */
+
+static uint8 Outvol[2];  /* last output volume for each channel */
+
+
+/* Initialze the bit patterns for the polynomials. */
+
+/* The 4bit and 5bit patterns are the identical ones used in the tia chip. */
+/* Though the patterns could be packed with 8 bits per byte, using only a */
+/* single bit per byte keeps the math simple, which is important for */
+/* efficient processing. */
+
+static uint8 Bit4[POLY4_SIZE] =
+      { 1,1,0,1,1,1,0,0,0,0,1,0,1,0,0 };
+
+static uint8 Bit5[POLY5_SIZE] =
+      { 0,0,1,0,1,1,0,0,1,1,1,1,1,0,0,0,1,1,0,1,1,1,0,1,0,1,0,0,0,0,1 };
+
+/* I've treated the 'Div by 31' counter as another polynomial because of */
+/* the way it operates.  It does not have a 50% duty cycle, but instead */
+/* has a 13:18 ratio (of course, 13+18 = 31).  This could also be */
+/* implemented by using counters. */
+
+static uint8 Div31[POLY5_SIZE] =
+      { 0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 };
+
+/* Rather than have a table with 511 entries, I use a random number */
+/* generator. */
+
+static uint8 Bit9[POLY9_SIZE];
+
+static uint8  P4[2]; /* Position pointer for the 4-bit POLY array */
+static uint8  P5[2]; /* Position pointer for the 5-bit POLY array */
+static uint16 P9[2]; /* Position pointer for the 9-bit POLY array */
+
+static uint8 Div_n_cnt[2];  /* Divide by n counter. one for each channel */
+static uint8 Div_n_max[2];  /* Divide by n maximum, one for each channel */
+
+
+/* In my routines, I treat the sample output as another divide by N counter. */
+/* For better accuracy, the Samp_n_cnt has a fixed binary decimal point */
+/* which has 8 binary digits to the right of the decimal point. */
+
+static uint16 Samp_n_max; /* Sample max, multiplied by 256 */
+static uint16 Samp_n_cnt; /* Sample cnt. */
+
+extern unsigned char *sounddata;
+/*****************************************************************************/
+/* Module:  Tia_sound_init()                                                 */
+/* Purpose: to handle the power-up initialization functions                  */
+/*          these functions should only be executed on a cold-restart        */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    September 10, 1996                                               */
+/*                                                                           */
+/* Inputs:  sample_freq - the value for the '30 Khz' Tia audio clock         */
+/*          playback_freq - the playback frequency in samples per second     */
+/*                                                                           */
+/* Outputs: Adjusts local globals - no return value                          */
+/*                                                                           */
+/*****************************************************************************/
+
+void Tia_sound_init (uint16 sample_freq, uint16 playback_freq)
+{
+   uint8 chan;
+   int16 n;
+
+   /* fill the 9bit polynomial with random bits */
+   for (n=0; n<POLY9_SIZE; n++)
+   {
+      Bit9[n] = rand() & 0x01;       /* fill poly9 with random bits */
+   }
+
+   /* calculate the sample 'divide by N' value based on the playback freq. */
+   Samp_n_max = (uint16)(((uint32)sample_freq<<8)/playback_freq);
+   Samp_n_cnt = 0;  /* initialize all bits of the sample counter */
+
+   /* initialize the local globals */
+   for (chan = CHAN1; chan <= CHAN2; chan++)
+   {
+      Outvol[chan] = 0;
+      Div_n_cnt[chan] = 0;
+      Div_n_max[chan] = 0;
+      AUDC[chan] = 0;
+      AUDF[chan] = 0;
+      AUDV[chan] = 0;
+      P4[chan] = 0;
+      P5[chan] = 0;
+      P9[chan] = 0;
+   }
+
+#ifdef HAS_SND
+  emu_sndInit();   
+#endif   
+}
+
+
+/*****************************************************************************/
+/* Module:  Update_tia_sound()                                               */
+/* Purpose: To process the latest control values stored in the AUDF, AUDC,   */
+/*          and AUDV s.  It pre-calculates as much information as    */
+/*          possible for better performance.  This routine has not been      */
+/*          optimized.                                                       */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    January 14, 1997                                                 */
+/*                                                                           */
+/* Inputs:  addr - the address of the parameter to be changed                */
+/*          val - the new value to be placed in the specified address        */
+/*                                                                           */
+/* Outputs: Adjusts local globals - no return value                          */
+/*                                                                           */
+/*****************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+void Update_tia_sound (uint16 addr, uint8 val)
+{
+    uint16 new_val = 0;
+    uint8 chan;
+
+	if (nOptions_SoundOn){
+    /* determine which address was changed */
+    switch (addr)
+    {
+       case AUDC0:
+          AUDC[0] = val & 0x0f;
+          chan = 0;
+          break;
+
+       case AUDC1:
+          AUDC[1] = val & 0x0f;
+          chan = 1;
+          break;
+
+       case AUDF0:
+          AUDF[0] = val & 0x1f;
+          chan = 0;
+          break;
+
+       case AUDF1:
+          AUDF[1] = val & 0x1f;
+          chan = 1;
+          break;
+
+       case AUDV0:
+          AUDV[0] = (val & 0x0f) << 3;
+          chan = 0;
+          break;
+
+       case AUDV1:
+          AUDV[1] = (val & 0x0f) << 3;
+          chan = 1;
+          break;
+
+       default:
+          chan = 255;
+          break;
+    }
+
+    /* if the output value changed */
+    if (chan != 255)
+    {
+       /* an AUDC value of 0 is a special case */
+       if (AUDC[chan] == SET_TO_1)
+       {
+          /* indicate the clock is zero so no processing will occur */
+          new_val = 0;
+
+          /* and set the output to the selected volume */
+          Outvol[chan] = AUDV[chan];
+       }
+       else
+       {
+          /* otherwise calculate the 'divide by N' value */
+          new_val = AUDF[chan] + 1;
+
+          /* if bits 2 & 3 are set, then multiply the 'div by n' count by 3 */
+          if ((AUDC[chan] & DIV3_MASK) == DIV3_MASK)
+          {
+             new_val *= 3;
+          }
+       }
+
+#ifdef HAS_SND
+         emu_sndPlaySound(chan, Outvol[chan], new_val);  
+#endif   
+
+       /* only reset those channels that have changed */
+       if (new_val != Div_n_max[chan])
+       {
+          /* reset the divide by n counters */
+          Div_n_max[chan] = new_val;
+
+          /* if the channel is now volume only or was volume only */
+          if ((Div_n_cnt[chan] == 0) || (new_val == 0))
+          {
+             /* reset the counter (otherwise let it complete the previous) */
+             Div_n_cnt[chan] = new_val;
+          }
+       }
+    }
+	}
+}
+
+
+/*****************************************************************************/
+/* Module:  Tia_process_2()                                                  */
+/* Purpose: To fill the output buffer with the sound output based on the     */
+/*          tia chip parameters.  This routine has not been optimized.       */
+/*          Though it is not used by the program, I've left it for reference.*/
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    September 10, 1996                                               */
+/*                                                                           */
+/* Inputs:  *buffer - pointer to the buffer where the audio output will      */
+/*                    be placed                                              */
+/*          n - size of the playback buffer                                  */
+/*                                                                           */
+/* Outputs: the buffer will be filled with n bytes of audio - no return val  */
+/*                                                                           */
+/*****************************************************************************/
+
+void Tia_process ( unsigned char *buffer,  uint16 n)
+{
+     uint8 chan;
+
+    /* loop until the buffer is filled */
+    while (n)
+    {
+       /* loop through the channels */
+       for (chan = CHAN1; chan <= CHAN2; chan++)
+       {
+          /* NOTE: this routine intentionally does not count down to zero */
+          /* since 0 is used as a special case - no clock */
+
+          /* if the divide by N counter can count down */
+          if (Div_n_cnt[chan] > 1)
+          {
+             /* decrement and loop */
+             Div_n_cnt[chan]--;
+          }
+          /* otherwise if we've reached the bottom */
+          else if (Div_n_cnt[chan] == 1)
+          {
+             /* reset the counter */
+             Div_n_cnt[chan] = Div_n_max[chan];
+
+             /* the P5 counter has multiple uses, so we inc it here */
+             P5[chan]++;
+             if (P5[chan] == POLY5_SIZE)
+                P5[chan] = 0;
+
+             /* check clock modifier for clock tick */
+
+             /* if we're using pure tones OR
+                   we're using DIV31 and the DIV31 bit is set OR
+                   we're using POLY5 and the POLY5 bit is set */
+             if  (((AUDC[chan] & 0x02) == 0) ||
+                 (((AUDC[chan] & 0x01) == 0) && Div31[P5[chan]]) ||
+                 (((AUDC[chan] & 0x01) == 1) &&  Bit5[P5[chan]]))
+             {
+                if (AUDC[chan] & 0x04)       /* pure modified clock selected */
+                {
+                   if (Outvol[chan])         /* if the output was set */
+                      Outvol[chan] = 0;      /* turn it off */
+                   else
+                      Outvol[chan] = AUDV[chan];   /* else turn it on */
+                }
+                else if (AUDC[chan] & 0x08)  /* check for p5/p9 */
+                {
+                   if (AUDC[chan] == POLY9)  /* check for poly9 */
+                   {
+                      /* inc the poly9 counter */
+                      P9[chan]++;
+                      if (P9[chan] == POLY9_SIZE)
+                         P9[chan] = 0;
+
+                      if (Bit9[P9[chan]])    /* if poly9 bit is set */
+                         Outvol[chan] = AUDV[chan];
+                      else
+                         Outvol[chan] = 0;
+                   }
+                   else                      /* must be poly5 */
+                   {
+                      if (Bit5[P5[chan]])
+                         Outvol[chan] = AUDV[chan];
+                      else
+                         Outvol[chan] = 0;
+                   }
+                }
+                else  /* poly4 is the only remaining option */
+                {
+                   /* inc the poly4 counter */
+                   P4[chan]++;
+                   if (P4[chan] == POLY4_SIZE)
+                      P4[chan] = 0;
+
+                   if (Bit4[P4[chan]])
+                      Outvol[chan] = AUDV[chan];
+                   else
+                      Outvol[chan] = 0;
+                }
+             }
+          }
+       }
+
+       /* decrement the sample counter - value is 256 since the lower
+          byte contains the fractional part */
+       Samp_n_cnt -= 256;
+
+       /* if the count down has reached zero */
+       if (Samp_n_cnt < 256)
+       {
+          /* adjust the sample counter */
+          Samp_n_cnt += Samp_n_max;
+
+          /* calculate the latest output value and place in buffer */
+          *(buffer++) = Outvol[0] + Outvol[1];
+          /* and indicate one less byte to process */
+          n--;
+       }
+    }
+}
+
+
+/*****************************************************************************/
+/* Module:  Tia_process()                                                    */
+/* Purpose: To fill the output buffer with the sound output based on the     */
+/*          tia chip parameters.  This routine has been optimized.           */
+/*                                                                           */
+/* Author:  Ron Fries                                                        */
+/* Date:    September 10, 1996                                               */
+/*                                                                           */
+/* Inputs:  *buffer - pointer to the buffer where the audio output will      */
+/*                    be placed                                              */
+/*          n - size of the playback buffer                                  */
+/*                                                                           */
+/* Outputs: the buffer will be filled with n bytes of audio - no return val  */
+/*                                                                           */
+/*****************************************************************************/
+
+void Tia_process_2 ( unsigned short *buffer,  uint16 n)
+{
+     uint8 audc0,audv0,audc1,audv1;
+     uint8 div_n_cnt0,div_n_cnt1;
+     uint8 p5_0, p5_1,outvol_0,outvol_1;
+
+    audc0 = AUDC[0];
+    audv0 = AUDV[0];
+    audc1 = AUDC[1];
+    audv1 = AUDV[1];
+
+    /* make temporary local copy */
+    p5_0 = P5[0];
+    p5_1 = P5[1];
+    outvol_0 = Outvol[0];
+    outvol_1 = Outvol[1];
+    div_n_cnt0 = Div_n_cnt[0];
+    div_n_cnt1 = Div_n_cnt[1];
+
+    /* loop until the buffer is filled */
+    while (n)
+    {
+       /* Process channel 0 */
+       if (div_n_cnt0 > 1)
+       {
+          div_n_cnt0--;
+       }
+       else if (div_n_cnt0 == 1)
+       {
+          div_n_cnt0 = Div_n_max[0];
+
+          /* the P5 counter has multiple uses, so we inc it here */
+          p5_0++;
+          if (p5_0 == POLY5_SIZE)
+             p5_0 = 0;
+
+          /* check clock modifier for clock tick */
+          if  (((audc0 & 0x02) == 0) ||
+              (((audc0 & 0x01) == 0) && Div31[p5_0]) ||
+              (((audc0 & 0x01) == 1) &&  Bit5[p5_0]))
+          {
+             if (audc0 & 0x04)       /* pure modified clock selected */
+             {
+                if (outvol_0)        /* if the output was set */
+                   outvol_0 = 0;     /* turn it off */
+                else
+                   outvol_0 = audv0; /* else turn it on */
+             }
+             else if (audc0 & 0x08)    /* check for p5/p9 */
+             {
+                if (audc0 == POLY9)    /* check for poly9 */
+                {
+                   /* inc the poly9 counter */
+                   P9[0]++;
+                   if (P9[0] == POLY9_SIZE)
+                      P9[0] = 0;
+
+                   if (Bit9[P9[0]])
+                      outvol_0 = audv0;
+                   else
+                      outvol_0 = 0;
+                }
+                else                        /* must be poly5 */
+                {
+                   if (Bit5[p5_0])
+                      outvol_0 = audv0;
+                   else
+                      outvol_0 = 0;
+                }
+             }
+             else  /* poly4 is the only remaining option */
+             {
+                /* inc the poly4 counter */
+                P4[0]++;
+                if (P4[0] == POLY4_SIZE)
+                   P4[0] = 0;
+
+                if (Bit4[P4[0]])
+                   outvol_0 = audv0;
+                else
+                   outvol_0 = 0;
+             }
+          }
+       }
+
+
+       /* Process channel 1 */
+       if (div_n_cnt1 > 1)
+       {
+          div_n_cnt1--;
+       }
+       else if (div_n_cnt1 == 1)
+       {
+          div_n_cnt1 = Div_n_max[1];
+
+          /* the P5 counter has multiple uses, so we inc it here */
+          p5_1++;
+          if (p5_1 == POLY5_SIZE)
+             p5_1 = 0;
+
+          /* check clock modifier for clock tick */
+          if  (((audc1 & 0x02) == 0) ||
+              (((audc1 & 0x01) == 0) && Div31[p5_1]) ||
+              (((audc1 & 0x01) == 1) &&  Bit5[p5_1]))
+          {
+             if (audc1 & 0x04)       /* pure modified clock selected */
+             {
+                if (outvol_1)        /* if the output was set */
+                   outvol_1 = 0;     /* turn it off */
+                else
+                   outvol_1 = audv1; /* else turn it on */
+             }
+             else if (audc1 & 0x08)    /* check for p5/p9 */
+             {
+                if (audc1 == POLY9)    /* check for poly9 */
+                {
+                   /* inc the poly9 counter */
+                   P9[1]++;
+                   if (P9[1] == POLY9_SIZE)
+                      P9[1] = 0;
+
+                   if (Bit9[P9[1]])
+                      outvol_1 = audv1;
+                   else
+                      outvol_1 = 0;
+                }
+                else                        /* must be poly5 */
+                {
+                   if (Bit5[p5_1])
+                      outvol_1 = audv1;
+                   else
+                      outvol_1 = 0;
+                }
+             }
+             else  /* poly4 is the only remaining option */
+             {
+                /* inc the poly4 counter */
+                P4[1]++;
+                if (P4[1] == POLY4_SIZE)
+                   P4[1] = 0;
+
+                if (Bit4[P4[1]])
+                   outvol_1 = audv1;
+                else
+                   outvol_1 = 0;
+             }
+          }
+       }
+
+       /* decrement the sample counter - value is 256 since the lower
+          byte contains the fractional part */
+       Samp_n_cnt -= 256;
+
+       /* if the count down has reached zero */
+       if (Samp_n_cnt < 256)
+       {
+          /* adjust the sample counter */
+          Samp_n_cnt += Samp_n_max;
+
+          /* calculate the latest output value and place in buffer */
+          *(buffer++) = (outvol_0 + outvol_1)*256;
+
+          /* and indicate one less byte to process */
+          n--;
+       }
+    }
+
+    /* save for next round */
+    P5[0] = p5_0;
+    P5[1] = p5_1;
+    Outvol[0] = outvol_0;
+    Outvol[1] = outvol_1;
+    Div_n_cnt[0] = div_n_cnt0;
+    Div_n_cnt[1] = div_n_cnt1;
+
+}
+
+
+
diff --git a/MCUME_pico2/picovcs/Vcsemu.c b/MCUME_pico2/picovcs/Vcsemu.c
new file mode 100644
index 0000000..72d0f2f
--- /dev/null
+++ b/MCUME_pico2/picovcs/Vcsemu.c
@@ -0,0 +1,66 @@
+#include "options.h"
+#include "vcsemu.h"
+#include "types.h"
+#include "vmachine.h"
+
+#include "emuapi.h"
+
+/****************************************************************************
+* Local macros / typedefs
+****************************************************************************/
+
+/****************************************************************************
+* Global data
+****************************************************************************/
+
+/****************************************************************************
+* Imported procedures
+****************************************************************************/
+extern void mainloop(void);
+
+/****************************************************************************
+* Local procedures
+****************************************************************************/
+
+/****************************************************************************
+* Exported procedures
+****************************************************************************/
+void vcs_Init(void)
+{
+  init_machine();	
+  init_hardware();
+  tv_on();
+}
+
+
+void vcs_Start(char * filename)
+{
+  int size = emu_LoadFile(filename, (char *)theCart, 16384); 
+  
+
+  if (size > 16384)
+    size = 16384;
+	
+  rom_size = size;
+  if (size == 2048)
+  {
+    memcpy (&theCart[2048], &theCart[0], 2048);
+    rom_size = 4096;
+  }
+  else if (size < 2048)
+  {
+    theCart[0x0ffc] = 0x00;
+    theCart[0x0ffd] = 0xf0;
+    rom_size = 4096;
+  }
+  
+  init_hardware();
+  init_banking(); 
+}
+
+
+void vcs_Step(void)
+{
+  //emu_printf("s");
+  mainloop();
+}
diff --git a/MCUME_pico2/picovcs/Vcsemu.h b/MCUME_pico2/picovcs/Vcsemu.h
new file mode 100644
index 0000000..c59f161
--- /dev/null
+++ b/MCUME_pico2/picovcs/Vcsemu.h
@@ -0,0 +1,9 @@
+extern void vcs_Init(void);
+extern void vcs_Start(char * filename);
+extern void vcs_Stop(void);
+extern void vcs_Step(void);
+extern void vcs_Input(int key);
+
+
+
+
diff --git a/MCUME_pico2/picovcs/Vmachine.c b/MCUME_pico2/picovcs/Vmachine.c
new file mode 100644
index 0000000..785891f
--- /dev/null
+++ b/MCUME_pico2/picovcs/Vmachine.c
@@ -0,0 +1,731 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: vmachine.c,v 2.22 1997/11/22 14:27:47 ahornby Exp $
+******************************************************************************/
+//This file was modified from its original version for use in PocketVCS
+// by Stuart Russell
+
+/* 
+   The virtual machine. Contains the RIOT timer code, and hardware 
+   initialisation.
+ */
+
+#include <stdio.h>
+#include "types.h"
+#include "address.h"
+#include "options.h"
+#include "display.h"
+#include "raster.h"
+#include "cpu.h"
+#include "collision.h"
+#include "sound.h"
+#include "vmachine.h"
+#include "tiasound.h"
+
+#include "emuapi.h"
+
+#define snd 1
+
+extern void BlitScreen(void);
+extern int nOptions_SoundBufSize;
+extern int nOptions_SoundOn;
+int Touchpadx=0;
+int Touchpady=0;
+//extern int Touchpadx;
+//extern int Touchpady;
+extern int nOptions_Landscape;
+extern int nOptions_SkipFrames;
+
+
+
+/* The Rom define might need altering for paged carts */
+/* Enough for 16k carts */
+int rom_size;
+
+/* Used as a simple file buffer to store the data */
+// JMH
+//BYTE theCart[16384];
+//BYTE theCart[4096];
+BYTE * theCart=0;
+
+/* Scratch area for those banking types that require memcpy() */
+//BYTE cartScratch[4096];
+BYTE * cartScratch=0;
+/* Area for those carts containing RAM */
+//BYTE cartRam[1024];
+BYTE * cartRam=0;
+
+/* Pointer to start of ROM data */
+BYTE *theRom;
+
+BYTE theRam[128];
+BYTE tiaRead[0x0e];
+BYTE tiaWrite[0x2d];
+BYTE keypad[2][4];
+
+/* These don't strictly need so much space */
+BYTE riotRead[0x298];
+BYTE riotWrite[0x298];
+
+/* 
+   Hardware addresses not programmer accessible 
+ */
+
+/* Set if whole emulator is reset */
+int reset_flag = 0;
+
+/* The timer resolution, can be 1,8,64,1024 */
+int timer_res = 32;
+int timer_count = 0;
+int timer_clks = 0;
+extern CLOCK clk;
+extern int beamadj;
+
+/* Electron beam position */
+int ebeamx, ebeamy, sbeamx;
+
+/* The state of the electron beam */
+#define VSYNCSTATE 1
+#define VBLANKSTATE 2
+#define HSYNCSTATE 4
+#define DRAWSTATE 8
+#define OVERSTATE 16
+int vbeam_state;		/* 1 2 8 or 16 */
+int hbeam_state;		/* 4 8 or 16 */
+
+/* The tv size, varies with PAL/NTSC */
+int tv_width, tv_height, tv_vsync, tv_vblank, tv_overscan, tv_frame, tv_hertz,
+  tv_hsync;
+
+
+PlayField pf[2];  
+
+Paddle paddle[4];
+
+Player pl[2];
+
+Missile ml[3];
+
+
+
+#define MAXLIST 80
+/* The various display lists */
+struct RasterChange pl_change[2][MAXLIST], pf_change[1][MAXLIST], unified[MAXLIST];
+
+/* The display list counters */
+int pl_change_count[2], pf_change_count[1], unified_count;
+
+
+/***************************************************************************
+                           Let the functions begin!
+****************************************************************************/
+void
+init_machine (void)
+{
+  if (theCart == 0) theCart = (BYTE *)emu_Malloc(16384);
+  if (cartScratch == 0) cartScratch = (BYTE *)emu_Malloc(4096);
+  if (cartRam == 0) cartRam = (BYTE *)emu_Malloc(1024);
+}
+
+/* Device independent screen initialisations */
+void
+init_screen (void)
+{
+  
+  /* Set the electron beam to the top left */
+  ebeamx = -tv_hsync;
+  ebeamy = 0;
+  sbeamx = 0;
+  vbeam_state = VSYNCSTATE;
+  hbeam_state = OVERSTATE;
+
+  tv_vsync = 3;
+  tv_hsync = 68;
+  switch (base_opts.tvtype) 
+    {
+    case NTSC:      
+      tv_width = 160;
+      tv_height = 192;
+      tv_vblank = 40;
+      tv_overscan = 30;
+      tv_frame = 262;
+      tv_hertz = 60;
+    break;
+    case PAL:
+    case SECAM:
+      tv_width = 160;
+      tv_height = 228;
+      tv_vblank = 48;
+      tv_overscan = 36;
+      tv_frame = 312;
+      tv_hertz = 50;
+      break;
+    }
+
+}
+
+/* Displays the tv screen */
+void tv_display (void)
+{
+  /* Only display if the frame is a valid one. */
+  //if ( (tv_counter % nOptions_SkipFrames) == 0)
+  //{
+	  emu_DrawScreenPal16(VBuf, tv_width, tv_height, tv_width);
+    emu_DrawVsync();
+  //}
+  //tv_counter++;
+}
+
+/* Initialise the RIOT (also known as PIA) */
+void
+init_riot (void)
+{
+  int i;
+
+  /* Reset the arrays */
+  for(i=0; i< 0x298;i++)
+    {
+      riotRead[i]=0;
+      riotWrite[i]=0;
+    }
+
+  /* Wipe the RAM */
+  for (i = 0; i < 0x80; i++)
+    theRam[i] = 0;
+
+  /* Set the timer to zero */
+  riotRead[INTIM] = 0;
+
+  /* Set the joysticks and switches to input */
+  riotWrite[SWACNT] = 0;
+  riotWrite[SWBCNT] = 0;
+
+  /* Centre the joysticks */
+  riotRead[SWCHA] = 0xff;
+  riotRead[SWCHB] = 0x0b;
+
+  /* Set the counter resolution */
+  timer_res = 32;
+  timer_count = 0;
+  timer_clks = 0;
+}
+
+/* Initialise the television interface adaptor (TIA) */
+void
+init_tia (void)
+{
+  int i;
+  for(i=0; i< 0x2d;i++)
+    {
+      tiaWrite[i]=0;
+    }
+  for(i=0; i< 0x0e;i++)
+    {
+      tiaRead[i]=0;
+    }
+
+  tiaWrite[CTRLPF] = 0x00;
+  for (i = 0; i < 2; i++)
+    {
+      pl[i].hmm = 0x0;
+      pl[i].x = 0x0;
+      pl[i].nusize = 0;
+      pl[i].grp = 0;
+      pl[i].vdel = 0;
+      pl[i].vdel_flag = 0;
+      pl_change_count[i] = 0;
+    }
+
+  pl[0].mask = PL0_MASK;
+  pl[1].mask = PL1_MASK;
+  ml[0].mask = ML0_MASK;
+  ml[1].mask = ML1_MASK;
+  reset_collisions ();
+
+  pf_change_count[0] = 0;
+  unified_count = 0;
+  for (i = 0; i < 3; i++)
+    {
+      ml[i].x = 0;
+      ml[i].hmm = 0;
+      ml[i].enabled = 0;
+      ml[i].locked = 0;
+      ml[i].width = 0;
+      ml[i].vdel = 0;
+      ml[i].vdel_flag = 0;
+    }
+  
+  tiaWrite[VBLANK] = 0;
+  tiaRead[INPT4] = 0x80;
+  tiaRead[INPT5] = 0x80;
+
+  /* Set up the colour table */
+  colour_table[P0M0_COLOUR]= 0;
+  colour_table[P1M1_COLOUR]= 0;
+  colour_table[PFBL_COLOUR] = 0;
+  colour_table[BK_COLOUR] = 0;
+}
+
+void
+init_memory(void)
+{
+  int i;
+  for(i=0;i<1024; i++)
+    cartRam[i]=0;
+  for(i=0; i<128;i++)
+    theRam[i]=0;
+}
+
+void
+init_banking (void)
+{
+  /* Set to the first bank */
+  //dbg_message(DBG_NORMAL, "rom_size is set at %d bytes\n", rom_size);
+  if (rom_size == 2048)
+    theRom = &theCart[rom_size - 2048];
+  else
+    theRom = &theCart[rom_size - 4096];
+  //JMH
+  //switch(base_opts.bank)
+  //  {
+  //  case 3:
+  //    /* Parker Brothers 8k E0 */
+  //    memcpy(&cartScratch[0xc00],&theCart[0x1c00],1024);
+  //    memcpy(&cartScratch[0],&theCart[0],3072);
+  //    theRom=cartScratch;
+  //    break;
+  //  default:
+  //    break;
+  //  }
+}
+
+extern void init_cpu( ADDRESS addr);
+
+/* Main hardware startup */
+void
+init_hardware (void)
+{
+//  dbg_message(DBG_NORMAL,"Setting Up hardware\n");
+  init_screen ();
+  init_riot ();
+  init_tia ();
+  init_raster ();
+  init_memory();
+  init_banking();
+  init_cpu (0xfffc);
+}
+
+/* Do a raster change */
+__inline void
+do_raster_change (int i, int type, int val, struct RasterChange *rc)
+{
+  rc->x = ebeamx + beamadj;
+  rc->type = type;
+  rc->val = val;
+}
+
+/* Do a raster change on the unified list */
+/* type: type of change */
+/* val: value of change */
+__inline void
+do_unified_change (int type, int val)
+{
+  if (unified_count < MAXLIST)
+    {
+      unified[unified_count].x = ebeamx + beamadj;
+      unified[unified_count].type = type;
+      unified[unified_count].val = val;
+      unified_count++;
+    }
+}
+
+/* Do a player raster change */
+/* i: player to change. 0 or 1 */
+/* type: type of change */
+/* val: value of change */
+__inline void
+do_plraster_change (int i, int type, int val)
+{
+  int plc = pl_change_count[i];
+  /*printf("Raster change i=%d, x=%d, type=%d, val=%d\n", i, x, type, val); */
+  if (plc < MAXLIST)
+    {
+      do_raster_change (i, type, val, &pl_change[i][plc]);
+      if (type == 1)
+	pl_change[i][plc].x -= 3;
+      pl_change_count[i]++;
+    }
+}
+
+/* Do a playfield raster change */
+/* i: playfield to change. Depreciated, as 0 is now only one used */
+/* type: type of change */
+/* val: value of change */
+__inline void
+do_pfraster_change (int i, int type, int val)
+{
+  int pfc = pf_change_count[i];
+  /*  
+     if(ebeamy>=100) {
+     printf("Raster change i=%d, x=%d, type=%d, val=%d\n", 
+     i, ebeamx+beamadj, type, val);
+     //show();
+     }
+   */
+  if (pfc < MAXLIST)
+    {
+      do_raster_change (i, type, val, &pf_change[i][pfc]);
+      pf_change_count[i]++;
+    }
+}
+
+
+/* Use a unified change */
+/* rc: unified change structure to use */
+__inline void
+use_unified_change (struct RasterChange *rc)
+{
+  switch (rc->type)
+    {
+    case 0:
+      /* P0MO colour */
+      colour_table[P0M0_COLOUR] = rc->val;
+      break;
+    case 1:
+      /* POM0 colour */
+      colour_table[P1M1_COLOUR] = rc->val;
+      break;
+    case 2:
+      /* PFBL colour */
+      colour_table[PFBL_COLOUR] = rc->val;
+      break;
+    case 3:
+      /* BK colour */
+      colour_table[BK_COLOUR] = rc->val;
+      break;
+    case 4:
+      /* Priority change Normal */
+      if(rc->val)
+	norm_val=1;
+      else
+	norm_val=0;
+      colour_lookup=colour_ptrs[norm_val][scores_val];
+      break;
+    case 5:
+      /* Priority change Scores */
+      if(rc->val)
+	{
+	  if(rc->x < 80)
+	    scores_val=1;
+	  else
+	    scores_val=2;
+	}
+      else
+	scores_val=0;
+      colour_lookup=colour_ptrs[norm_val][scores_val];
+      break;
+    }
+}
+
+/* Use a playfield change */
+/* pl: playfield to change */
+/* rc: change to make */
+__inline void
+use_pfraster_change (PlayField *pl, struct RasterChange *rc)
+{
+  switch (rc->type)
+    {
+    case 0:
+      /* PF0 */
+      pl->pf0 = rc->val;
+      break;
+    case 1:
+      /* PF1 */
+      pl->pf1 = rc->val;
+      break;
+    case 2:
+      /* PF2 */
+      pl->pf2 = rc->val;
+      break;
+    case 3:
+      /* Reflection */
+      pl->ref = rc->val;
+      break;
+    }
+}
+
+/* Use a player change */
+/* pl: player to change */
+/* rc: change to make */
+__inline void
+use_plraster_change ( Player *pl, struct RasterChange *rc)
+{
+  switch (rc->type)
+    {
+    case 0:
+      /* GRP */
+      pl->grp = rc->val;
+      break;
+      /* Vertical delay */
+    case 1:
+      pl->vdel = pl->grp;
+      break;
+    }
+}
+
+
+int
+do_paddle (int padnum)
+{
+  int res = 0x00;
+  int x=0;
+  if ((tiaWrite[VBLANK] & 0x80) == 0)
+    {
+	if (!nOptions_Landscape){
+		x=240-Touchpadx;
+		x=x*66;
+		if (paddle[padnum].val > x) 
+		res=0x80;
+		
+		}else{
+		x=320-Touchpady;
+		x=x*50;
+		if (paddle[padnum].val > x) 
+		res=0x80;
+		}
+		
+    if (x > clk)
+	res = 0x00;
+    }
+  return res;
+}
+
+/* Calculate the keypad rows */
+/* i.e. when reading from INPTx we don't know the row */
+BYTE
+do_keypad (int pad, int col)
+{
+  BYTE res= 0x80;
+
+//  read_keypad(pad);
+  
+  /* Bottom row */
+  if(pad==0) {
+  if( (riotWrite[SWCHA] & 0x80) && keypad[pad][col]==3)
+    res=0x00;
+  /* Third row */
+  if( (riotWrite[SWCHA] & 0x40) && keypad[pad][col]==2)
+    res=0x00;
+  if( (riotWrite[SWCHA] & 0x20) && keypad[pad][col]==1)
+    res=0x00;
+  if( (riotWrite[SWCHA] & 0x10) && keypad[pad][col]==0)
+    res=0x00;
+  } 
+  else {
+  /* Bottom row */
+  if( (riotWrite[SWCHA] & 0x80) && keypad[pad][col]==3)
+    res=0x00;
+  /* Third row */
+  if( (riotWrite[SWCHA] & 0x40) && keypad[pad][col]==2)
+    res=0x00;
+  if( (riotWrite[SWCHA] & 0x20) && keypad[pad][col]==1)
+    res=0x00;
+  if( (riotWrite[SWCHA] & 0x10) && keypad[pad][col]==0)
+    res=0x00;
+  }
+  return res;
+}
+
+
+/* 
+   Called when the timer is set .
+   Note that res is the bit shift, not absolute value.
+   Assumes that any timer interval set will last longer than the instruction
+   setting it.
+ */
+/* res: timer interval resolution as a bit shift value */
+/* count: the number of intervals to set */
+/* clkadj: the number of CPU cycles into the current instruction  */
+void
+set_timer (int res, int count, int clkadj)
+{
+  timer_count = count << res;
+  timer_clks = clk + clkadj;
+  timer_res = res;
+}
+
+/* New timer code, now only called on a read of INTIM */
+/* clkadj: the number of CPU cycles into the current instruction  */
+/* returns: the current timer value */
+BYTE
+do_timer (int clkadj)
+{
+  BYTE result;
+  int delta;
+  int value;
+
+  delta = clk - timer_clks;
+  value = delta >> timer_res;
+  if (delta <= timer_count)
+    {				/* Timer is still going down in res intervals */
+      result = value;
+    }
+  else
+    {
+      if (value == 0)
+	/* Timer is in holding period */
+	result = 0;
+      else
+	{
+	  /* Timer is descending from 0xff in clock intervals */
+	  set_timer (0, 0xff, clkadj);
+	  result = 0;
+	}
+    }
+
+  /*  printf("Timer result=%d\n", result); */
+  return result;
+}
+
+#ifdef snd
+//extern unsigned char *sounddata;
+//#define SoundBufSize 256
+//unsigned char sounddata[SoundBufSize];
+#endif
+
+/* Do the screen related part of a write to VBLANK */
+/* b: the byte written */
+void
+do_vblank (BYTE b)
+{
+	
+  if (b & 0x02)
+    {
+      /* Start vertical blank */
+      vbeam_state = VBLANKSTATE;
+#ifdef snd
+//	  Tia_process(sounddata, SoundBufSize);
+//      CESound_play_sample(sounddata, nOptions_SoundBufSize);
+#endif
+      /* Also means we can update screen */
+      tv_display ();
+    }
+  else
+    {
+      /* End vblank, and start first hsync drawing */
+      int i;
+
+      vbeam_state = DRAWSTATE;
+      hbeam_state = HSYNCSTATE;
+      /* Set up the screen */
+      for (i = 0; i < unified_count; i++)
+	use_unified_change (&unified[i]);
+      /* Hope for a WSYNC, but just in case */
+      ebeamx = -tv_hsync;
+      ebeamy = 0;
+    }
+}
+
+
+//int count = 1;
+
+/* do a horizontal sync */
+void
+do_hsync (void)
+{
+  /* Only perform heavy stuff if electron beam is in correct position */
+  if (vbeam_state == DRAWSTATE && (ebeamx > -tv_hsync))
+    {
+//      if (!(count--))
+//      {
+//        count = 2;
+      tv_raster (ebeamy);
+        
+//      }
+      /* Fix the clock value */
+      clk += (ebeamx - tv_width) / 3;
+      ebeamy++;
+    }
+  hbeam_state = HSYNCSTATE;
+  ebeamx = -tv_hsync;
+  sbeamx = 0;
+}
+
+/* Main screen logic */
+/* clks: CPU clock length of last instruction */
+__inline void
+do_screen (int clks)
+{
+  switch (vbeam_state)
+    {
+    case VSYNCSTATE:
+    case VBLANKSTATE:
+      switch (hbeam_state)
+	{
+	case HSYNCSTATE:
+	  ebeamx += clks * 3;
+	  if (ebeamx >= 0)
+	    {
+	      hbeam_state = DRAWSTATE;
+	    }
+	  break;
+	case DRAWSTATE:
+	  ebeamx += clks * 3;
+	  if (ebeamx >= tv_width)
+	    {
+	      ebeamx -= (tv_hsync + tv_width);
+	      /* Insert hsync stuff here */
+	      sbeamx = ebeamx;
+	      hbeam_state = HSYNCSTATE;
+	    }
+	  break;
+	case OVERSTATE:
+	  break;
+	}
+      break;
+    case DRAWSTATE:
+      switch (hbeam_state)
+	{
+	case HSYNCSTATE:
+	  ebeamx += clks * 3;
+	  if (ebeamx >= 0)
+	    {
+	      hbeam_state = DRAWSTATE;
+	    }
+	  break;
+	case DRAWSTATE:
+	  ebeamx += clks * 3;
+	  if (ebeamx >= tv_width)
+	    {
+	      /* Insert hsync stuff here */
+	      sbeamx = ebeamx;
+	      ebeamx -= (tv_hsync + tv_width);
+	      tv_raster (ebeamy);
+	      ebeamy++;
+	      hbeam_state = HSYNCSTATE;
+	    }
+	  if (ebeamy >= tv_height + tv_overscan)
+	    {
+	      vbeam_state = OVERSTATE;
+	      ebeamy = 0;
+	    }
+	  break;
+	case OVERSTATE:
+	  break;
+	}
+      break;
+    case OVERSTATE:
+      break;
+    }
+}
+
diff --git a/MCUME_pico2/picovcs/address.h b/MCUME_pico2/picovcs/address.h
new file mode 100644
index 0000000..1d694e4
--- /dev/null
+++ b/MCUME_pico2/picovcs/address.h
@@ -0,0 +1,110 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: address.h,v 1.4 1996/04/01 14:51:50 alex Exp $
+******************************************************************************/
+
+#ifndef ADDRESS_H 
+#define ADDRESS_H 
+
+/* Contains the addresses of the 2600 hardware */
+/* $Id: address.h,v 1.4 1996/04/01 14:51:50 alex Exp $ */
+
+/* TIA Write Addresses (6 bit) */
+
+#define VSYNC	0x00
+#define VBLANK	0x01
+#define WSYNC	0x02
+#define RSYNC	0x03
+#define NUSIZ0	0x04
+#define NUSIZ1	0x05
+#define COLUP0	0x06
+#define COLUP1	0x07
+#define COLUPF	0x08
+#define COLUBK	0x09
+#define CTRLPF	0x0A
+#define REFP0	0x0B
+#define REFP1	0x0C
+#define PF0	0x0D
+#define PF1	0x0E
+#define PF2	0x0F
+#define RESP0	0x10
+#define RESP1	0x11
+#define RESM0	0x12
+#define RESM1	0x13
+#define RESBL	0x14
+#define AUDC0	0x15
+#define AUDC1	0x16
+#define AUDF0	0x17
+#define AUDF1	0x18
+#define AUDV0	0x19
+#define AUDV1	0x1A
+#define GRP0	0x1B
+#define GRP1	0x1C
+#define ENAM0	0x1D
+#define ENAM1	0x1E
+#define ENABL	0x1F
+#define HMP0	0x20
+#define HMP1	0x21
+#define HMM0	0x22
+#define HMM1	0x23
+#define HMBL	0x24
+#define VDELP0	0x25
+#define VDELP1	0x26
+#define VDELBL	0x27
+#define RESMP0	0x28
+#define RESMP1	0x29
+#define HMOVE	0x2A
+#define HMCLR	0x2B
+#define CXCLR	0x2C
+
+/* TIA Read Addresses */
+#define CXM0P	0x0
+#define CXM1P	0x1
+#define CXP0FB	0x2
+#define CXP1FB	0x3
+#define CXM0FB	0x4
+#define CXM1FB	0x5
+#define CXBLPF	0x6
+#define CXPPMM	0x7
+#define INPT0	0x8
+#define INPT1	0x9
+#define INPT2	0xA
+#define INPT3	0xB
+#define INPT4	0xC
+#define INPT5	0xD
+
+/* RIOT Addresses */
+
+#define RAM	0x80	/* till 0xff */
+#define SWCHA	0x280
+#define SWACNT	0x281
+#define SWCHB	0x282
+#define SWBCNT	0x283
+#define INTIM	0x284
+
+#define TIM1T	0x294
+#define TIM8T	0x295
+#define TIM64T	0x296
+#define T1024T	0x297
+
+#define ROM	0xE000	/* To FFFF,0x1000-1FFF */ 
+
+#endif
+
+
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/btypes.h b/MCUME_pico2/picovcs/btypes.h
new file mode 100644
index 0000000..6431958
--- /dev/null
+++ b/MCUME_pico2/picovcs/btypes.h
@@ -0,0 +1,47 @@
+#ifndef BASICTYPES_H
+#define BASICTYPES_H
+
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned long  uint32;
+
+typedef signed char int8;
+typedef signed short int16;
+typedef signed long int32;
+
+
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef signed char offset;
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { unsigned long l,h; } DW;
+#else
+  struct { unsigned long h,l; } DW;
+#endif
+//  unsigned long long LL;
+} ullong;
+
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h,a,b; } B;
+#else
+  struct { byte b,a,h,l; } B;
+#endif
+  unsigned long DW;
+} dpair;
+
+typedef union
+{
+#ifdef LSB_FIRST
+  struct { byte l,h; } B;
+#else
+  struct { byte h,l; } B;
+#endif
+  word W;
+} pair;
+//END Added from NES
+
+#endif
diff --git a/MCUME_pico2/picovcs/c26def.h b/MCUME_pico2/picovcs/c26def.h
new file mode 100644
index 0000000..5f479e9
--- /dev/null
+++ b/MCUME_pico2/picovcs/c26def.h
@@ -0,0 +1,101 @@
+#ifndef C26DEF_H
+#define C26DEF_H
+
+/* 
+   Common 2600 (.c26) format v1.0 specification
+   -------------------------------------
+   Alex Hornby, ahornby@zetnet.co.uk
+
+
+   Introduction
+   ============
+
+   Common 2600 file format definitions. For discussion and suggestions for 
+   improvement, e-mail ahornby@zetnet.co.uk. I would like to see a fully
+   comprehensive 2600 file format develop so please copy this structure
+   and use it in your emulators.
+
+   The format has been developed due to the multitude of different banking
+   schemes for 2600 cartridges, along with the need to select an appropriate
+   control device for each game. Using the .c26 format you will be able to
+   load games without giving loads of command line switches. 
+
+   Philosophy
+   ==========
+   To avoid the format splitting into several competing ones, please do
+   not alter the format without discussing it first. I'm not trying to be
+   bossy, just to keep the common format truly common. 
+
+   Tags
+   ====
+   The format is tagged so as to be extensible and allow both forward and
+   backward compatibility. It also means that information that is not 
+   needed or known does not have to be stored. e.g. If the cartridge image
+   is not a saved game then I do not need the game state tags.
+
+   The format is a system of tags each being a tag type and the length of
+   data in that section. If a tag is not recognised then it should
+   be ignored. Each tag is a zero terminated string followed by a 32bit 
+   signed integer describing the length. If the tag is small the the length
+   integer can constitute the data item.
+
+   Case is NOT important in tag names 
+
+   Cross Platform Notes
+   ====================
+   Note that integers are stored in the Intel/DEC Alpha style. 
+   All strings are zero terminated .
+*/
+
+/* 
+   Defined TAGS
+   ============
+   
+   + Audit tags: All files should include these tags at the start of the file. 
+      
+   VERSION: Gives file format version as an integer. Currently 1
+   WRITER: Name of program that wrote file.
+   
+   + Cartridge Information tags: useful for collectors.
+   
+   CARTNAME: Name of cartridge.
+   CARTMAN:  Manufacturer of cartridge.
+   CARTAUTHOR: Name of programmer/programming team who wrote cartridge.
+   CARTSERIAL: Serial number of the cartridge.
+   
+   + Cartridge operation tags: necessary for the running of the game.   
+   
+   TVTYPE:     integer, 0=NTSC 1=PAL.
+   CONTROLLERS: Left controller BYTE then  Right controller BYTE.
+   BANKING:    Bank switching scheme.
+   DATA:       Cartridge ROM data.
+   
+   + Game state tags: used for saved games.
+   
+   CPUREGS:  CPU registers.
+   GAMEREGS: TIA and PIA registers.
+   PIARAM:   The 128 bytes of RAM from the PIA.
+
+   CARTRAM:  Cartridge RAM, if supported by the BANKING type
+   
+   */
+enum TAGTYPE { VERSION=-1, WRITER=1, 
+               CARTNAME=2, CARTMAN=3, CARTAUTHOR=4, CARTSERIAL=5,
+               TVTYPE=-2, CONTROLLERS=-3, BANKING=-4, DATA=6,
+               CPUREGS=7, GAMEREGS=8, PIARAM=9, CARTRAM=10 };
+
+char *tag_desc[]={ "VERSION", "WRITER", 
+		   "CARTNAME", "CARTMAN", "CARTAUTHOR", "CARTSERIAL",
+		   "TVTYPE", "CONTROLLERS", "BANKING", "DATA",
+		   "CPUREGS", "GAMEREGS", "PIARAM", "CARTRAM"};
+
+
+/* Tag structure */
+
+struct c26_tag {
+    int type;
+    int len;
+};
+
+
+#endif
diff --git a/MCUME_pico2/picovcs/col_mask.h b/MCUME_pico2/picovcs/col_mask.h
new file mode 100644
index 0000000..d8d0558
--- /dev/null
+++ b/MCUME_pico2/picovcs/col_mask.h
@@ -0,0 +1,45 @@
+#ifndef COL_MASK_H
+#define COL_MASK_H
+
+#define PL0_MASK  0x01
+#define PL1_MASK  0x02
+#define ML0_MASK  0x04
+#define ML1_MASK  0x08
+#define BL_MASK  0x10
+#define PF_MASK  0x20
+#define PF_MASK32  0x20202020
+
+#define M0P0_MASK 0x01
+#define M0P1_MASK 0x02
+
+#define M1P1_MASK 0x04
+#define M1P0_MASK 0x08
+
+#define P0BL_MASK  0x10
+#define P0PF_MASK  0x20
+
+#define P1BL_MASK  0x40
+#define P1PF_MASK  0x80
+
+#define M0BL_MASK  0x100
+#define M0PF_MASK  0x200
+
+#define M1BL_MASK  0x400
+#define M1PF_MASK  0x800
+
+#define BLPF_MASK  0x1000
+
+#define M0M1_MASK  0x2000
+#define P0P1_MASK  0x4000
+
+#define CXM0P_MASK   (M0P1_MASK | M0P0_MASK) 
+#define CXM1P_MASK   (M1P0_MASK | M1P1_MASK) 
+#define CXP0FB_MASK   (P0PF_MASK | P0BL_MASK) 
+#define CXP1FB_MASK   (P1PF_MASK | P1BL_MASK) 
+#define CXM0FB_MASK   (M0PF_MASK | M0BL_MASK) 
+#define CXM1FB_MASK   (M1PF_MASK | M1BL_MASK) 
+#define CXBLPF_MASK   BLPF_MASK 
+#define CXPPMM_MASK   (P0P1_MASK | M0M1_MASK)
+
+#endif
+
diff --git a/MCUME_pico2/picovcs/collision.h b/MCUME_pico2/picovcs/collision.h
new file mode 100644
index 0000000..b2d5466
--- /dev/null
+++ b/MCUME_pico2/picovcs/collision.h
@@ -0,0 +1,49 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: collision.h,v 1.5 1996/08/29 16:03:24 ahornby Exp $
+******************************************************************************/
+
+/*
+  Defines for the hardware collision detection.
+  */
+
+//#ifndef COLLISION_H
+#define COLLISION_H
+
+#include "col_mask.h"
+
+/* The collsion vector */
+extern BYTE* colvect;
+
+/* The collision lookup table */
+extern unsigned short col_table[256];
+
+/* The collision state */
+extern unsigned short col_state;
+
+extern void
+init_collisions(void);
+
+extern __inline void 
+reset_collisions(void);
+
+extern int
+set_collisions(BYTE b); 
+
+//#endif
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/colours.h b/MCUME_pico2/picovcs/colours.h
new file mode 100644
index 0000000..c935b76
--- /dev/null
+++ b/MCUME_pico2/picovcs/colours.h
@@ -0,0 +1,102 @@
+static long colortable[256] =
+{
+  /* Grey */
+  0x0, 0x1c1c1c, 0x393939, 0x595959, 
+  0x797979, 0x929292, 0xababab, 0xbcbcbc, 
+  0xcdcdcd, 0xd9d9d9, 0xe6e6e6, 0xececec, 
+  0xf2f2f2, 0xf8f8f8, 0xffffff, 0xffffff, 
+  
+  /* Gold */
+  0x391701, 0x5e2304, 0x833008, 0xa54716, 
+  0xc85f24, 0xe37820, 0xff911d, 0xffab1d, 
+  0xffc51d, 0xffce34, 0xffd84c, 0xffe651, 
+  0xfff456, 0xfff977, 0xffff98, 0xffff98, 
+  
+  /* Orange */
+  0x451904, 0x721e11, 0x9f241e, 0xb33a20, 
+  0xc85122, 0xe36920, 0xff811e, 0xff8c25, 
+  0xff982c, 0xffae38, 0xffc545, 0xffc559, 
+  0xffc66d, 0xffd587, 0xffe4a1, 0xffe4a1, 
+  
+  /* Red Orange */
+  0x4a1704, 0x7e1a0d, 0xb21d17, 0xc82119, 
+  0xdf251c, 0xec3b38, 0xfa5255, 0xfc6161, 
+  0xff706e, 0xff7f7e, 0xff8f8f, 0xff9d9e, 
+  0xffabad, 0xffb9bd, 0xffc7ce, 0xffc7ce, 
+
+  /* Pink */
+  0x50568, 0x3b136d, 0x712272, 0x8b2a8c, 
+  0xa532a6, 0xb938ba, 0xcd3ecf, 0xdb47dd, 
+  0xea51eb, 0xf45ff5, 0xfe6dff, 0xfe7afd, 
+  0xff87fb, 0xff95fd, 0xffa4ff, 0xffa4ff, 
+
+  /* Purple */
+  0x280479, 0x400984, 0x590f90, 0x70249d, 
+  0x8839aa, 0xa441c3, 0xc04adc, 0xd054ed, 
+  0xe05eff, 0xe96dff, 0xf27cff, 0xf88aff, 
+  0xff98ff, 0xfea1ff, 0xfeabff, 0xfeabff, 
+
+  /* Blue Purple */
+  0x35088a, 0x420aad, 0x500cd0, 0x6428d0, 
+  0x7945d0, 0x8d4bd4, 0xa251d9, 0xb058ec, 
+  0xbe60ff, 0xc56bff, 0xcc77ff, 0xd183ff, 
+  0xd790ff, 0xdb9dff, 0xdfaaff, 0xdfaaff, 
+
+  /* Blue */
+  0x51e81, 0x626a5, 0x82fca, 0x263dd4, 
+  0x444cde, 0x4f5aee, 0x5a68ff, 0x6575ff, 
+  0x7183ff, 0x8091ff, 0x90a0ff, 0x97a9ff, 
+  0x9fb2ff, 0xafbeff, 0xc0cbff, 0xc0cbff, 
+
+  /* Blue */
+  0xc048b, 0x2218a0, 0x382db5, 0x483ec7, 
+  0x584fda, 0x6159ec, 0x6b64ff, 0x7a74ff, 
+  0x8a84ff, 0x918eff, 0x9998ff, 0xa5a3ff, 
+  0xb1aeff, 0xb8b8ff, 0xc0c2ff, 0xc0c2ff, 
+
+  /* Light Blue */
+  0x1d295a, 0x1d3876, 0x1d4892, 0x1c5cac, 
+  0x1c71c6, 0x3286cf, 0x489bd9, 0x4ea8ec, 
+  0x55b6ff, 0x70c7ff, 0x8cd8ff, 0x93dbff, 
+  0x9bdfff, 0xafe4ff, 0xc3e9ff, 0xc3e9ff, 
+
+  /* Turquoise */
+  0x2f4302, 0x395202, 0x446103, 0x417a12, 
+  0x3e9421, 0x4a9f2e, 0x57ab3b, 0x5cbd55, 
+  0x61d070, 0x69e27a, 0x72f584, 0x7cfa8d, 
+  0x87ff97, 0x9affa6, 0xadffb6, 0xadffb6, 
+
+  /* Green blue */
+  0xa4108, 0xd540a, 0x10680d, 0x137d0f, 
+  0x169212, 0x19a514, 0x1cb917, 0x1ec919, 
+  0x21d91b, 0x47e42d, 0x6ef040, 0x78f74d, 
+  0x83ff5b, 0x9aff7a, 0xb2ff9a, 0xb2ff9a, 
+
+  /* Green */
+  0x4410b, 0x5530e, 0x66611, 0x77714, 
+  0x88817, 0x99b1a, 0xbaf1d, 0x48c41f, 
+  0x86d922, 0x8fe924, 0x99f927, 0xa8fc41, 
+  0xb7ff5b, 0xc9ff6e, 0xdcff81, 0xdcff81, 
+
+  /* Yellow Green */
+  0x2350f, 0x73f15, 0xc4a1c, 0x2d5f1e, 
+  0x4f7420, 0x598324, 0x649228, 0x82a12e, 
+  0xa1b034, 0xa9c13a, 0xb2d241, 0xc4d945, 
+  0xd6e149, 0xe4f04e, 0xf2ff53, 0xf2ff53, 
+
+  /* Orange Green */
+  0x263001, 0x243803, 0x234005, 0x51541b, 
+  0x806931, 0x978135, 0xaf993a, 0xc2a73e, 
+  0xd5b543, 0xdbc03d, 0xe1cb38, 0xe2d836, 
+  0xe3e534, 0xeff258, 0xfbff7d, 0xfbff7d, 
+
+  /* Light Orange */
+  0x401a02, 0x581f05, 0x702408, 0x8d3a13, 
+  0xab511f, 0xb56427, 0xbf7730, 0xd0853a, 
+  0xe19344, 0xeda04e, 0xf9ad58, 0xfcb75c, 
+  0xffc160, 0xffc671, 0xffcb83, 0xffcb83, 
+};
+
+
+
+
diff --git a/MCUME_pico2/picovcs/cpu.h b/MCUME_pico2/picovcs/cpu.h
new file mode 100644
index 0000000..95a4b70
--- /dev/null
+++ b/MCUME_pico2/picovcs/cpu.h
@@ -0,0 +1,182 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: cpu.h,v 1.6 1997/11/22 14:29:54 ahornby Exp $
+******************************************************************************/
+/*
+ *
+ * This file was part of x64.
+ *
+ * This file contains useful stuff when you are creating
+ * virtual machine like MCS6510 based microcomputer.
+ *
+ * Included are:
+ *	o registers
+ *	o flags in PSW
+ *      o addressing modes
+ *
+ * Written by
+ *   Vesa-Matti Puro (vmp@lut.fi)
+ *   Jarkko Sonninen (sonninen@lut.fi)
+ *   Jouko Valta (jopi@stekt.oulu.fi)
+ *
+ *
+ */
+
+#ifndef X2600_CPU_H
+#define X2600_CPU_H
+
+#include "types.h"
+
+/* 6507 Registers. */
+#define AC		accumulator
+#define XR		x_register
+#define YR		y_register
+#define SP		stack_pointer
+#define pc6507  program_counter
+#define PCH		((pc6507>>8)&0xff)
+#define PCL		(pc6507&0xff)
+
+#define ZF		zero_flag
+#define SF		sign_flag
+#define OF		overflow_flag
+#define BF		break_flag
+#define DF		decimal_flag
+#define IF		interrupt_flag
+#define CF		carry_flag
+
+
+/* Masks which indicate location of status flags in PSW. */
+#define S_SIGN		0x80
+#define S_OVERFLOW	0x40
+#define S_NOTUSED 	0x20
+#define S_BREAK		0x10
+#define S_DECIMAL	0x08
+#define S_INTERRUPT	0x04
+#define S_ZERO		0x02
+#define S_CARRY		0x01
+
+
+/* ADDRESSING MODES */
+
+#define IMPLIED		0
+#define ACCUMULATOR	1
+#define IMMEDIATE	2
+
+#define ZERO_PAGE	3
+#define ZERO_PAGE_X	4
+#define ZERO_PAGE_Y	5
+
+#define ABSOLUTE	6
+#define ABSOLUTE_X	7
+#define ABSOLUTE_Y	8
+
+#define ABS_INDIRECT	9
+#define INDIRECT_X	10
+#define INDIRECT_Y	11
+
+#define RELATIVE	12
+
+#define ASS_CODE	13
+
+
+/*
+ * Declaration for lookup-table which is used to translate MOS6502
+ * machine instructions. Machine code is used as index to array called
+ * lookup. Pointer to function is then fetched from array and function
+ * is called.
+ */
+
+extern struct lookup_tag {
+    char          *mnemonic;	/* Selfdocumenting? */
+    short          addr_mode;
+    unsigned char  source;
+    unsigned char  destination;
+    unsigned char  cycles;
+    unsigned char  pbc_fix;	/* Cycle for Page Boundary Crossing */
+}       lookup[];
+
+
+/* Addressing mode (addr_mode) is used when instruction is diassembled
+ * or assembled by diassembler or assembler. This is used i.e.
+ * in function char *sprint_opcode() in the file misc.c.
+ *
+ * MOS6502 addressing modes are #defined in the file "vmachine.h".
+ *
+ * Mnemonic is character string telling the name of the instruction.
+ */
+
+#define M_NONE	0
+#define M_AC 	1
+#define M_XR	2
+#define M_YR	3
+#define M_SP	4
+#define M_SR	5
+#define M_PC	6
+#define M_IMM	7
+#define M_ZERO	8
+#define M_ZERX	9
+#define M_ZERY	10
+#define M_ABS	11
+#define M_ABSX	12
+#define M_ABSY	13
+#define M_AIND	14
+#define M_INDX	15
+#define M_INDY	16
+#define M_REL	17
+#define M_FC	18
+#define M_FD	19
+#define M_FI	20
+#define M_FV	21
+#define M_ADDR	22
+#define M_	23
+
+#ifndef NO_UNDOC_CMDS
+#define M_ACIM	24	/* Source: AC & IMMED (bus collision) */
+#define M_ANXR	25	/* Source: AC & XR (bus collision) */
+#define M_AXIM	26	/* Source: (AC | #EE) & XR & IMMED (bus collision) */
+#define M_ACNC	27	/* Dest: M_AC and Carry = Negative */
+#define M_ACXR	28	/* Dest: M_AC, M_XR */
+
+#define M_SABY	29	/* Source: (ABS_Y & SP) (bus collision) */
+#define M_ACXS	30	/* Dest: M_AC, M_XR, M_SP */
+#define M_STH0	31	/* Dest: Store (src & Addr_Hi+1) to (Addr +0x100) */
+#define M_STH1	32
+#define M_STH2	33
+#define M_STH3	34
+
+#else
+#define M_ACIM	M_NONE
+#define M_ANXR	M_NONE
+#define M_AXIM	M_NONE
+#define M_ACNC	M_NONE
+#define M_ACXR	M_NONE
+
+#define M_SABY	M_NONE
+#define M_ACXS	M_NONE
+#define M_STH0	M_NONE
+#define M_STH1	M_NONE
+#define M_STH2	M_NONE
+#define M_STH3	M_NONE
+#endif
+
+
+
+#endif  /* X2600_CPU_H */
+
+
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/display.h b/MCUME_pico2/picovcs/display.h
new file mode 100644
index 0000000..c4c15c6
--- /dev/null
+++ b/MCUME_pico2/picovcs/display.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: display.h,v 1.13 1997/11/22 14:29:54 ahornby Exp $
+******************************************************************************/
+
+/*
+  Defines for the X11 display code.
+  */
+
+#ifndef DISPLAY_H
+#define DISPLAY_H
+
+int tv_on(void);
+void tv_display(void);
+
+extern int vwidth,vheight,theight;
+extern int tv_counter;
+extern unsigned char * VBuf;
+
+#endif
+
+
+
+
diff --git a/MCUME_pico2/picovcs/emucfg.h b/MCUME_pico2/picovcs/emucfg.h
new file mode 100644
index 0000000..2afc96a
--- /dev/null
+++ b/MCUME_pico2/picovcs/emucfg.h
@@ -0,0 +1,94 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define PALETTE_SIZE         256
+#define VID_FRAME_SKIP       0x0
+#define TFT_VBUFFER_YCROP    0
+//#define SINGLELINE_RENDERING 1
+//#define CUSTOM_SND           1
+//#define TIMER_REND           1
+#define EXTRA_HEAP           0x10
+#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    Atari2600 Emulator"
+#define ROMSDIR "2600"
+
+#define emu_Init(ROM) {vcs_Init();vcs_Start(ROM);}
+#define emu_Step() {vcs_Step();}
+#define emu_Input(x) {vcs_Input(x);}
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  1,2,3,4,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"1234       "
+#define keylables_map1_1 (char *)"           "
+#define keylables_map1_2 (char *)"           "
+const unsigned short key_map1[] = {
+  1,2,3,4,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map2_0 (char *)"           "
+#define keylables_map2_1 (char *)"           "
+#define keylables_map2_2 (char *)"           "
+const unsigned short key_map2[] = {
+  0,0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"           "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"           "
+const unsigned short key_map3[] = {
+  0,0,0,0,0,0,0,0,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,0,0,
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/picovcs/exmacro.h b/MCUME_pico2/picovcs/exmacro.h
new file mode 100644
index 0000000..d67b51a
--- /dev/null
+++ b/MCUME_pico2/picovcs/exmacro.h
@@ -0,0 +1,30 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: exmacro.h,v 1.5 1996/11/24 16:55:40 ahornby Exp $
+******************************************************************************/
+
+/*
+  Defines __inline functions that would otherwise be macros.
+  */
+
+//#ifndef EXMACRO_H
+//#define EXMACRO_H
+
+extern __inline ADDRESS load_abs_addr(void);
+extern __inline int pagetest( ADDRESS a, BYTE b);
+extern __inline int brtest( BYTE a);
+extern __inline int toBCD( int a);
+extern __inline int fromBCD( int a);
+
+//#endif
+
diff --git a/MCUME_pico2/picovcs/extern.h b/MCUME_pico2/picovcs/extern.h
new file mode 100644
index 0000000..0aa5143
--- /dev/null
+++ b/MCUME_pico2/picovcs/extern.h
@@ -0,0 +1,62 @@
+/*
+ $Id: extern.h,v 1.2 1995/12/12 16:21:39 alex Exp alex $
+ */
+
+#ifndef VCSEXTERN_H
+#define VCSEXTERN_H
+
+
+#include "types.h"	/* for BYTE, ADDRESS, etc. types and structures */
+/* #include "proto.h" */
+
+extern char *progname;
+extern int   clength[];
+
+extern BYTE  accumulator;
+extern BYTE  x_register;
+extern BYTE  y_register;
+extern BYTE  stack_pointer;
+extern BYTE  status_register;
+extern ADDRESS program_counter;
+extern CLOCK clk;
+
+extern int   zero_flag;
+extern int   sign_flag;
+extern int   overflow_flag;
+extern int   break_flag;
+extern int   decimal_flag;
+extern int   interrupt_flag;
+extern int   carry_flag;
+
+/* Debugging */
+extern int   hexflg;
+extern int   verflg;
+extern int   traceflg;
+extern int   debugflg;
+extern int   runflg;
+
+extern int   autodump;
+extern int   reuflg;
+
+
+/* Memory */
+
+extern int module;
+
+/* Keyboard & joystick */
+
+#ifdef JOYSTICK
+extern void joystick(void) ;
+extern void joyini(void) ;
+extern void joyclose(void);
+
+extern int joyfd ;
+#endif
+
+#endif
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/keyboard.h b/MCUME_pico2/picovcs/keyboard.h
new file mode 100644
index 0000000..0da9978
--- /dev/null
+++ b/MCUME_pico2/picovcs/keyboard.h
@@ -0,0 +1,7 @@
+#ifndef KEYBOARD_H
+#define KEYBOARD_H
+
+void init_keyboard(void);
+void keyboard(void);
+
+#endif
diff --git a/MCUME_pico2/picovcs/keyboard_osd.h b/MCUME_pico2/picovcs/keyboard_osd.h
new file mode 100644
index 0000000..4c31e6f
--- /dev/null
+++ b/MCUME_pico2/picovcs/keyboard_osd.h
@@ -0,0 +1,19 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
diff --git a/MCUME_pico2/picovcs/logo.h b/MCUME_pico2/picovcs/logo.h
new file mode 100644
index 0000000..41390c2
--- /dev/null
+++ b/MCUME_pico2/picovcs/logo.h
@@ -0,0 +1,194 @@
+const uint16_t logo[] PROGMEM = {
+0x0140,0x00c1,0x39e7,0x39c6,0x3a07,0x3a07,0x39e7,0x4227,0x39e6,0x39c6,0x39e7,0x39c7,0x39e6,0x31c6,0x39c6,0x39c6,0x39c6,0x39c6,0x39e7,0x3a07,0x3a07,0x39e7,0x39e6,0x3a07,0x3a07,0x39e7,0x39e7,0x39e7,0x3a07,0x39e7,0x3a07,0x3a07,0x39e7,0x3a07,0x39e7,0x31c6,0x31c6,0x31e6,0x31c6,0x3a07,0x31c6,0x39e6,0x31e6,0x39e7,0x39e7,0x31c6,0x39e6,0x39e6,0x3a07,0x39e7,0x31c6,0x3a07,0x4228,0x3a07,0x4228,0x4228,0x4248,0x3a07,0x4227,0x4227,0x3a27,0x3a27,0x39e7,0x3a07,0x3a08,0x39e7,0x31e6,0x31c6,0x39e7,0x39e7,0x39e7,0x31c6,0x2985,0x31a6,0x31c6,0x31a6,0x31a6,0x31c6,0x31a5,0x39c6,0x31a6,0x31a6,0x31c6,0x31a6,0x31a6,0x31a6,0x31c6,0x31c6,0x29a5,0x31c6,0x31a6,0x2985,0x3185,0x31a6,0x31c6,0x31a6,0x31a5,0x31a6,0x31c6,0x31c6,0x31c6,0x31c6,0x31c6,0x31c6,0x31a6,0x31a6,0x31e6,0x31a6,0x31a6,0x31a6,0x31c6,0x31a6,0x31a6,0x31a6,0x31a6,0x31c6,0x31c6,0x31a6,0x31c6,0x31a6,0x2985,0x2986,0x31a6,0x31a6,0x31c6,0x31c6,0x31a5,0x31a5,0x31a6,0x31a5,0x31c6,0x2985,0x2985,0x3185,0x3185,0x2985,0x2965,0x2985,0x2985,0x3185,0x3185,0x3185,0x2985,0x2985,0x2985,0x2985,0x3185,0x2985,0x31a6,0x3185,0x31a5,0x31a6,0x31a5,0x31a5,0x31a6,0x3185,0x3185,0x3185,0x3185,0x31a6,0x31a6,0x2985,0x31a6,0x31a5,0x31a5,0x31a5,0x31a6,0x31a6,0x2985,0x2985,0x3186,0x3185,0x31a6,0x31a5,0x31a6,0x31a6,0x3186,0x3186,0x2985,0x2985,0x31a6,0x31a6,0x31c6,0x31a6,0x31a6,0x31a6,0x3185,0x31a6,0x3186,0x3186,0x39c6,0x4208,0x4208,0x39c7,0x39e7,0x39e7,0x31a6,0x3185,0x31a6,0x3185,0x31a6,0x31a6,0x31a6,0x3185,0x31a6,0x31a6,0x3185,0x31a6,0x31a6,0x31a6,0x31a5,0x31a6,0x31a6,0x31a6,0x31a6,0x3186,0x3186,0x3185,0x3186,0x39c6,0x39c7,0x39c6,0x31a6,0x39c6,0x31c6,0x3186,0x31c6,0x39e7,0x39e7,0x39e7,0x31c6,0x39c7,0x39c7,0x39e7,0x31a6,0x39c6,0x39c6,0x39c6,0x39c6,0x39c7,0x39c7,0x39a6,0x31a6,0x31c6,0x39c6,0x39c6,0x31a6,0x39e7,0x3a07,0x4208,0x4207,0x4207,0x39e7,0x39e7,0x3a07,0x39e7,0x39e7,0x39e7,0x39e7,0x4208,0x4208,0x4207,0x39e7,0x39e7,0x39e7,0x39e7,0x39e7,0x4208,0x39c6,0x39e7,0x3a07,0x39e7,0x39e7,0x39e7,0x39c6,0x39c7,0x39e7,0x39e7,0x39e7,0x4208,0x3a07,0x39e7,0x39e7,0x39e7,0x3a07,0x3a07,0x3a07,0x3a07,0x39e7,0x39c7,0x3a07,0x3a07,0x39e7,0x39e7,0x39e7,0x3a07,0x4208,0x39e7,0x39e7,0x3a07,0x3a07,0x3a07,0x4228,0x4207,0x39c7,0x4207,0x39e7,0x39c7,0x4207,0x39e7,0x3a07,0x4208,0x4208,0x4248,0x4228,0x3a07,0x4207,0x4228,0x41e7,0x4208,0x3a07,0x3a07,
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+0x2965,0x18e3,0x18e4,0x18c3,0x10a2,0x10a2,0x18e3,0x18e3,0x18e3,0x10a3,0x18c3,0x2104,0x18a3,0x0000,0x18a2,0x18a2,0x18c3,0x18e3,0x0000,0x1061,0x20e3,0x0000,0x1062,0x0820,0x0000,0x1082,0x0861,0x1082,0x0000,0x0800,0x18a2,0x18a3,0x1082,0x1082,0x0800,0x1061,0x0820,0x0841,0x0841,0x0841,0x0000,0x10a2,0x18c2,0x0820,0x0000,0x0841,0x0000,0x0000,0x1061,0x1061,0x1041,0x0841,0x1082,0x0841,0x0841,0x1061,0x0000,0x0000,0x1081,0x0841,0x0000,0x0820,0x1082,0x0841,0x1062,0x0841,0x1082,0x0000,0x0841,0x0841,0x0020,0x0882,0x0861,0x1082,0x0020,0x0840,0x1082,0x0861,0x0861,0x0841,0x0841,0x0841,0x0861,0x0861,0x1082,0x10a2,0x0861,0x1082,0x0841,0x0861,0x0020,0x0821,0x1061,0x0861,0x1082,0x10a2,0x1082,0x0861,0x0861,0x1061,0x0821,0x0841,0x1082,0x1061,0x1082,0x10a2,0x0861,0x1082,0x0861,0x0861,0x1082,0x0841,0x1081,0x0841,0x0020,0x0861,0x0861,0x0861,0x1082,0x0882,0x0861,0x0861,0x0861,0x0861,0x0861,0x1082,0x10a2,0x1082,0x1082,0x0881,0x1081,0x1082,0x1082,0x1082,0x1082,0x0861,0x1082,0x10a2,0x10a2,0x10a2,0x0881,0x1082,0x10a2,0x1082,0x0882,0x1082,0x1082,0x1082,0x1082,0x1082,0x0841,0x0020,0x0841,0x0861,0x0861,0x1082,0x1082,0x1082,0x0861,0x1062,0x10a2,0x10a2,0x0861,0x0861,0x1082,0x0861,0x10a2,0x18c3,0x1082,0x18c3,0x1082,0x0861,0x0020,0x10a2,0x10a2,0x10a2,0x18c3,0x1082,0x1082,0x10a2,0x1082,0x10a2,0x0861,0x1082,0x10a2,0x1082,0x1082,0x1082,0x0861,0x1081,0x10a2,0x10a2,0x1082,0x10a2,0x10a2,0x0020,0x10a2,0x1082,0x0862,0x18c3,0x1082,0x10a3,0x10a2,0x18c3,0x1903,0x18c3,0x18c3,0x18c3,0x10a2,0x1082,0x18c3,0x10a2,0x10a2,0x18c3,0x18e3,0x10a3,0x18e3,0x2104,0x10c2,0x18e3,0x10a2,0x10a2,0x10a2,0x2124,0x18e3,0x18c3,0x18c3,0x18e4,0x2104,0x2104,0x2145,0x2104,0x18e3,0x2124,0x2145,0x2104,0x10a3,0x10a3,0x2104,0x2945,0x2945,0x2945,0x10a3,0x2965,0x2965,0x1904,0x2124,0x31a6,0x39c7,0x2965,0x2965,0x2945,0x3186,0x2945,0x3186,0x3186,0x39c7,0x31a6,0x39c7,0x39e7,0x39e7,0x39c7,0x39c7,0x39c7,0x39e7,0x39c7,0x39e7,0x4a49,0x3a08,0x31a7,0x4208,0x4208,0x3186,0x39e7,0x4a49,0x4228,0x4a6a,0x5acb,0x528a,0x4228,0x526a,0x4a69,0x4a29,0x2947,0x4a69,0x4a8a,0x39e7,0x52aa,0x632c,0x528a,0x5acb,0x6b6d,0x52aa,0x630c,0x632c,0x5aeb,0x5b0b,0x630c,0x632c,0x632c,0x632c,0x6b6d,0x632c,0x5aeb,0x52cb,0x5aeb,0x632c,0x632c,0x6b4d,0x5aeb,0x632c,0x738e,0x6b6d,0x73ae,0x7bef,0x73af,0x73ae,0x8410,0x6b8e,0x5b0c};
diff --git a/MCUME_pico2/picovcs/macro.h b/MCUME_pico2/picovcs/macro.h
new file mode 100644
index 0000000..e298409
--- /dev/null
+++ b/MCUME_pico2/picovcs/macro.h
@@ -0,0 +1,99 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: macro.h,v 1.7 1996/11/24 16:55:40 ahornby Exp $
+******************************************************************************/
+
+/*
+ *
+ * Originally from x64 by
+ *   Vesa-Matti Puro (vmp@lut.fi)
+ *   Jarkko Sonninen (sonninen@lut.fi)
+ * 
+ * NOTE: Can add zero page optimizations
+ */
+
+#ifndef X2600_MACRO_H
+#define X2600_MACRO_H
+
+
+#include "types.h"
+#include "cpu.h"
+
+#define LOAD(a)      		decRead(a)
+#define LOADEXEC(a)      	undecRead(a)
+//#define DLOAD(a)                dbgRead(a)
+#define LOAD_ZERO(a) 		decRead((ADDRESS)a)
+#define LOAD_ADDR(a)		((LOADEXEC(a+1)<<8)+LOADEXEC(a))  //WAS LOAD
+#define LOAD_ZERO_ADDR(a)	LOAD_ADDR(a)
+
+#define STORE(a,b)     	 	decWrite((a),(b))
+#define STORE_ZERO(a,b)         decWrite((a),(b))
+
+#define PUSH(b) 		decWrite(SP+0x100,(b));SP--
+#define PULL()			decRead((++SP)+0x100)
+
+#define UPPER(ad)		(((ad)>>8)&0xff)
+#define LOWER(ad)		((ad)&0xff)
+#define LOHI(lo,hi)             ((lo)|((hi)<<8))
+
+#define REL_ADDR(pc,src) 	(pc+((SIGNED_CHAR)src))
+
+#define SET_SIGN(a)		(SF=(a)&S_SIGN)
+#define SET_ZERO(a)		(ZF=!(a))
+#define SET_CARRY(a)  		(CF=(a))
+
+#define SET_INTERRUPT(a)	(IF=(a))
+#define SET_DECIMAL(a)		(DF=(a))
+#define SET_OVERFLOW(a)		(OF=(a))
+#define SET_BREAK(a)		(BF=(a))
+
+#define SET_SR(a)		(SF=(a) & S_SIGN,\
+				 ZF=(a) & S_ZERO,\
+				 CF=(a) & S_CARRY,\
+				 IF=(a) & S_INTERRUPT,\
+				 DF=(a) & S_DECIMAL,\
+				 OF=(a) & S_OVERFLOW,\
+				 BF=(a) & S_BREAK)
+
+#define GET_SR()		((SF ? S_SIGN : 0) |\
+				 (ZF ? S_ZERO : 0) |\
+				 (CF ? S_CARRY : 0) |\
+				 (IF ? S_INTERRUPT : 0) |\
+				 (DF ? S_DECIMAL : 0) |\
+				 (OF ? S_OVERFLOW : 0) |\
+				 (BF ? S_BREAK : 0) | S_NOTUSED)
+
+#define IF_SIGN()		SF
+#define IF_ZERO()		ZF
+#define IF_CARRY()		CF
+#define IF_INTERRUPT()		IF
+#define IF_DECIMAL()		DF
+#define IF_OVERFLOW()		OF
+#define IF_BREAK()		BF
+
+
+#define sprint_status()	 sprint_binary(GET_SR())
+
+
+#endif  /* X2600_MACRO_H */
+
+
+
+
+
+
+
+
+
+
+
diff --git a/MCUME_pico2/picovcs/mnemonic.h b/MCUME_pico2/picovcs/mnemonic.h
new file mode 100644
index 0000000..59b417d
--- /dev/null
+++ b/MCUME_pico2/picovcs/mnemonic.h
@@ -0,0 +1,149 @@
+/*
+ * $Id: mnemonic.h,v 1.1 1995/11/26 21:52:43 alex Exp alex $
+ *
+ * This file is part of Commodore 64 emulator.
+ * See README for copyright notice
+ *
+ * This file contains #defines for MOS6010 instruction mnemonics.
+ *
+ * Written by
+ *   Vesa-Matti Puro (vmp@lut.fi)
+ *   Jouko Valta (jopi@stekt.oulu.fi)
+ *
+ * $Log: mnemonic.h,v $
+ * Revision 1.1  1995/11/26 21:52:43  alex
+ * Initial revision
+ *
+ * Revision 1.6  1994/12/12  16:59:44  jopi
+ * *** empty log message ***
+ *
+ * Revision 1.5  1994/06/16  17:19:26  jopi
+ * Code reorganized and cleaned up
+ *
+ * Revision 1.4  1993/11/10  01:55:34  jopi
+ * reu, asm and disk directory fixed
+ * REL_ADDR macro and 1541 made more portable
+ *
+ * Revision 1.3  93/06/21  13:38:45  jopi
+ *  X64 version 0.2 PL 0
+ *
+ * Revision 1.2  1993/06/13  08:21:50  sonninen
+ * *** empty log message ***
+ *
+ *
+ */
+
+#ifndef X64_MNEMONIC_H
+#define X64_MNEMONIC_H
+
+
+/* INSTRUCTION MNEMONICS. */
+
+#define ADC	"ADC"
+#define AND	"AND"
+#define ASL	"ASL"
+#define BCC	"BCC"
+#define BCS	"BCS"
+#define BEQ	"BEQ"
+#define BIT	"BIT"
+#define BMI	"BMI"
+#define BNE	"BNE"
+#define BPL	"BPL"
+#define BRK	"BRK"
+#define BVC	"BVC"
+#define BVS	"BVS"
+#define CLC	"CLC"
+#define CLD	"CLD"
+#define CLI	"CLI"
+#define CLV	"CLV"
+#define CMP	"CMP"
+#define CPX	"CPX"
+#define CPY	"CPY"
+#define DEC	"DEC"
+#define DEX	"DEX"
+#define DEY	"DEY"
+#define EOR	"EOR"
+#define INC	"INC"
+#define INX	"INX"
+#define INY	"INY"
+#define JMP	"JMP"
+#define JSR	"JSR"
+#define LDA	"LDA"
+#define LDX	"LDX"
+#define LDY	"LDY"
+#define LSR	"LSR"
+#define NOOP	"NOOP"
+#define NOP	"NOP"
+#define ORA	"ORA"
+#define PHA	"PHA"
+#define PHP	"PHP"
+#define PLA	"PLA"
+#define PLP	"PLP"
+#define ROL	"ROL"
+#define ROR	"ROR"
+#define RTI	"RTI"
+#define RTS	"RTS"
+#define SBC	"SBC"
+#define SEC	"SEC"
+#define SED	"SED"
+#define SEI	"SEI"
+#define STA	"STA"
+#define STX	"STX"
+#define STY	"STY"
+#define TAX	"TAX"
+#define TAY	"TAY"
+#define TSX	"TSX"
+#define TXA	"TXA"
+#define TXS	"TXS"
+#define TYA	"TYA"
+
+#ifndef NO_UNDOC_CMDS
+#define ANC	"ANC"
+#define ANE	"ANE"
+#define ARR	"ARR"
+#define ASR	"ASR"
+#define DCP	"DCP"
+#define ISB	"ISB"
+#define JAM	"JAM"
+#define LAS	"LAS"
+#define LAX	"LAX"
+#define LXA	"LXA"
+ /* NOOP undefined NOP */
+#define RLA	"RLA"
+#define RRA	"RRA"
+#define SAX	"SAX"
+#define USBC	"USBC"	/* undefined SBC */
+#define SBX	"SBX"
+#define SHA	"SHA"
+#define SHS	"SHS"
+#define SHX	"SHX"
+#define SHY	"SHY"
+#define SLO	"SLO"
+#define SRE	"SRE"
+
+#else
+#define ANC	NOOP
+#define ANE	NOOP
+#define ARR	NOOP
+#define ASR	NOOP
+#define DCP	NOOP
+#define ISB	NOOP
+#define JAM	NOOP
+#define LAS	NOOP
+#define LAX	NOOP
+#define LXA	NOOP
+ /* NOOP undefined NOP */
+#define RLA	NOOP
+#define RRA	NOOP
+#define SAX	NOOP
+#define USBC	NOOP
+#define SBX	NOOP
+#define SHA	NOOP
+#define SHS	NOOP
+#define SHX	NOOP
+#define SHY	NOOP
+#define SLO	NOOP
+#define SRE	NOOP
+#endif
+
+#endif  /* X64_MNEMONIC_H */
diff --git a/MCUME_pico2/picovcs/options.h b/MCUME_pico2/picovcs/options.h
new file mode 100644
index 0000000..2614f66
--- /dev/null
+++ b/MCUME_pico2/picovcs/options.h
@@ -0,0 +1,26 @@
+//#ifndef OPTIONS_H
+#define OPTIONS_H
+
+enum {NTSC=0, PAL=1, SECAM=2};
+
+/* Options common to all ports of x2600 */
+extern struct BaseOptions {
+  int tvtype;
+  int lcon;
+  int rcon;
+  int bank;
+  int magstep;
+  char filename[80];
+  int sound;
+  int swap;
+  int realjoy;
+  int limit;
+  int mousey;
+  int mitshm;
+  int dbg_level;
+} base_opts;
+
+int 
+parse_options(int argc, char **argv);
+
+//#endif
diff --git a/MCUME_pico2/picovcs/picovcs.cpp b/MCUME_pico2/picovcs/picovcs.cpp
new file mode 100644
index 0000000..1c6a0ad
--- /dev/null
+++ b/MCUME_pico2/picovcs/picovcs.cpp
@@ -0,0 +1,151 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+
+extern "C" {
+#include "Vcsemu.h"
+}
+#include <stdio.h>
+#include "pico_dsp.h"
+
+volatile bool vbl=true;
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    if (vbl) {
+        vbl = false;
+    } else {
+        vbl = true;
+    }   
+    return true;
+}
+
+PICO_DSP tft;
+static int skip=0;
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+//    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+ 
+    set_sys_clock_khz(140000, true);
+
+    //set_sys_clock_khz(250000, true);
+    //*((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+    emu_init();
+    char * filename;
+#ifdef FILEBROWSER
+    while (true) {      
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;    
+            }
+            tft.waitSync();
+        }
+    }
+#endif    
+    emu_start();
+    emu_Init(filename);
+    tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(15, repeating_timer_callback, NULL, &timer);    
+    while (true) {
+        uint16_t bClick = emu_DebounceLocalKeys();
+        emu_Input(bClick);  
+        emu_Step();
+    }
+}
+
+
+static unsigned short palette16[PALETTE_SIZE];
+void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index)
+{
+    if (index<PALETTE_SIZE) {
+        palette16[index]  = RGBVAL16(r,g,b);        
+    }
+}
+
+void emu_DrawScreenPal16(unsigned char * VBuf, int width, int height, int stride) 
+{
+    if (skip == 0) {
+        tft.writeScreenPal(width,height-TFT_VBUFFER_YCROP,stride, VBuf+(TFT_VBUFFER_YCROP/2)*stride, palette16);
+    }
+}
+void emu_DrawLinePal16(unsigned char * VBuf, int width, int height, int line) 
+{
+    if (skip == 0) {
+         tft.writeLinePal(width,height,line, VBuf, palette16);
+    }
+}
+
+void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line)
+{
+    if (skip == 0) {
+        tft.writeLine(width,height,line, VBuf);
+    }
+}
+
+int emu_IsVga(void)
+{
+    return (tft.getMode() == MODE_VGA_320x240?1:0);
+}
+
+void emu_DrawVsync(void)
+{
+    skip += 1;
+    skip &= VID_FRAME_SKIP;
+    volatile bool vb=vbl; 
+    while (vbl==vb) {};   
+    /*
+    if ( emu_IsVga() ) {
+        tft.waitSync(); 
+    }
+    else {
+        while (vbl==vb) {};
+    } 
+    */
+}
+
+
+
+
+
+#ifdef HAS_SND
+#include "AudioPlaySystem.h"
+AudioPlaySystem mymixer;
+
+void emu_sndInit() {
+  tft.begin_audio(256, mymixer.snd_Mixer);
+  mymixer.start();    
+}
+
+void emu_sndPlaySound(int chan, int volume, int freq)
+{
+  if (chan < 6) {
+    mymixer.sound(chan, freq, volume); 
+  }
+}
+
+void emu_sndPlayBuzz(int size, int val) {
+  mymixer.buzz(size,val); 
+}
+
+#endif
+
+
diff --git a/MCUME_pico2/picovcs/program_config.h b/MCUME_pico2/picovcs/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/picovcs/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/picovcs/raster.h b/MCUME_pico2/picovcs/raster.h
new file mode 100644
index 0000000..0436523
--- /dev/null
+++ b/MCUME_pico2/picovcs/raster.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+
+   This file is part of Virtual 2600, the Atari 2600 Emulator
+   ==========================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: raster.h,v 1.5 1997/04/06 02:15:13 ahornby Exp $
+******************************************************************************/
+
+/*
+  The raster prototypes.
+  */
+
+#ifndef RASTER_H
+#define RASTER_H
+/* Color lookup tables. Used to speed up rendering */
+/* The current colour lookup table */
+extern int *colour_lookup;  
+
+/* Colour table */
+#define P0M0_COLOUR 0
+#define P1M1_COLOUR 1
+#define PFBL_COLOUR 2
+#define BK_COLOUR 3
+extern unsigned int colour_table[4];
+
+/* normal/alternate, not scores/scores*/
+extern int norm_val, scores_val;
+extern int *colour_ptrs[2][3];
+
+void tv_raster(int line);
+
+extern void 
+init_raster(void);
+#endif
+
+
+
diff --git a/MCUME_pico2/picovcs/resource.h b/MCUME_pico2/picovcs/resource.h
new file mode 100644
index 0000000..320059c
--- /dev/null
+++ b/MCUME_pico2/picovcs/resource.h
@@ -0,0 +1,60 @@
+//{{NO_DEPENDENCIES}}
+// Microsoft Developer Studio generated include file.
+// Used by Atari2600Emulator.rc
+//
+#define IDS_APP_TITLE                   1
+#define IDS_HELLO                       2
+#define IDC_ATARI2600EMULATOR           3
+#define IDI_ATARI2600EMULATOR           101
+#define IDM_MENU                        102
+#define IDS_HELP                        104
+#define IDD_OPTIONS                     104
+#define IDD_Error                       105
+#define IDB_CONSOLE                     109
+#define IDB_LOGO                        110
+#define IDB_CONTROLLER                  111
+#define IDD_CONSOLE                     111
+#define IDD_DIALOG1                     113
+#define IDD_DIALOG2                     114
+#define IDD_VCSINFO                     115
+#define IDS_COMMAND1                    301
+#define IDC_BUTTON1                     1001
+#define IDC_CHECK_SOUND                 1003
+#define IDC_RADIO_COLOR                 1005
+#define IDC_RADIO_P1AM                  1006
+#define IDC_RADIO_BW                    1007
+#define IDC_RADIO_P1PRO                 1008
+#define IDC_RADIO_P2PRO                 1009
+#define IDC_EDIT_SKIP_FRAMES            1010
+#define IDC_RADIO_P2AM                  1010
+#define IDC_EDIT_SLEEP                  1011
+#define IDC_CHECK_LAND                  1012
+#define IDC_SNDSPEED_SLIDER             1013
+#define IDC_SND_BUFFER                  1014
+#define IDC_VOL_SLIDER                  1016
+#define IDC_SND_RATE                    1025
+#define IDM_MAIN_COMMAND1               40001
+#define IDM_SETTINGS_CONSOLE            40002
+#define IDM_HELP_ABOUTVCS               40003
+#define ID_FILE                         40004
+#define ID_SETTINGS                     40005
+#define IDS_CAP_FILE                    40006
+#define IDM_FILE_OPEN                   40007
+#define IDM_SETTINGS_OPTIONS            40008
+#define IDM_FILE_EXIT                   40009
+#define IDS_CAP_SETTINGS                40011
+
+#define STICK                           0x01
+#define PADDLE                          0x02
+#define KEYPAD                          0x03
+
+// Next default values for new objects
+// 
+#ifdef APSTUDIO_INVOKED
+#ifndef APSTUDIO_READONLY_SYMBOLS
+#define _APS_NEXT_RESOURCE_VALUE        117
+#define _APS_NEXT_COMMAND_VALUE         40014
+#define _APS_NEXT_CONTROL_VALUE         1026
+#define _APS_NEXT_SYMED_VALUE           103
+#endif
+#endif
diff --git a/MCUME_pico2/picovcs/sound.h b/MCUME_pico2/picovcs/sound.h
new file mode 100644
index 0000000..a07fc44
--- /dev/null
+++ b/MCUME_pico2/picovcs/sound.h
@@ -0,0 +1,26 @@
+#ifndef X2600_SOUND_H
+#define X2600_SOUND_H
+
+/* $Id: sound.h,v 1.4 1996/09/04 22:37:48 ahornby Exp $ */
+
+extern void
+sound_init(void);
+
+extern void
+sound_close(void);
+
+extern void 
+sound_freq(int channel, BYTE freq);
+
+extern void
+sound_volume(int channel, BYTE vol);
+
+//extern void
+//	  Update_tia_sound(0x15 + channel, value);
+
+//sound_waveform(int channel, BYTE value);
+
+extern void
+sound_update(void);
+
+#endif
diff --git a/MCUME_pico2/picovcs/tiasound.h b/MCUME_pico2/picovcs/tiasound.h
new file mode 100644
index 0000000..c96e829
--- /dev/null
+++ b/MCUME_pico2/picovcs/tiasound.h
@@ -0,0 +1,41 @@
+/*****************************************************************************/
+/*                                                                           */
+/* Module:  TIA Chip Sound Simulator Includes, V1.0                          */
+/* Purpose: Define global function prototypes and structures for the TIA     */
+/*          Chip Sound Simulator.                                            */
+/* Author:  Ron Fries                                                        */
+/* Date:    September 10, 1996                                               */
+/*                                                                           */
+/*****************************************************************************/
+/*                                                                           */
+/*                 License Information and Copyright Notice                  */
+/*                 ========================================                  */
+/*                                                                           */
+/* TiaSound is Copyright(c) 1996 by Ron Fries                                */
+/*                                                                           */
+/* This library is free software; you can redistribute it and/or modify it   */
+/* under the terms of version 2 of the GNU Library General Public License    */
+/* as published by the Free Software Foundation.                             */
+/*                                                                           */
+/* This library is distributed in the hope that it will be useful, but       */
+/* WITHOUT ANY WARRANTY; without even the implied warranty of                */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Library */
+/* General Public License for more details.                                  */
+/* To obtain a copy of the GNU Library General Public License, write to the  */
+/* Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.   */
+/*                                                                           */
+/* Any permitted reproduction of these routines, in whole or in part, must   */
+/* bear this legend.                                                         */
+/*                                                                           */
+/*****************************************************************************/
+                
+#ifndef _TIASOUND_H
+#define _TIASOUND_H
+
+void Tia_sound_init (unsigned int sample_freq, unsigned int playback_freq);
+extern void Update_tia_sound (unsigned int addr, unsigned char val);
+extern void Tia_process_2 (register unsigned short *buffer,
+                    register unsigned int n);
+extern void Tia_process (register unsigned char *buffer,
+                    register unsigned int n);
+#endif 
diff --git a/MCUME_pico2/picovcs/types.h b/MCUME_pico2/picovcs/types.h
new file mode 100644
index 0000000..60d2ac2
--- /dev/null
+++ b/MCUME_pico2/picovcs/types.h
@@ -0,0 +1,51 @@
+/*
+ * $Id: types.h,v 1.1 1995/11/26 21:52:43 alex Exp alex $
+ *
+ * This file is part of Commodore 64 emulator.
+ * See README for copyright notice
+ *
+ * This file declares types used all over.
+ *
+ *
+ * Written by
+ *   Jarkko Sonninen (sonninen@lut.fi)
+ *   Jouko Valta (jopi@stekt.oulu.fi)
+ *
+ *
+ * $Log: types.h,v $
+ * Revision 1.1  1995/11/26 21:52:43  alex
+ * Initial revision
+ *
+ * Revision 1.4  1995/04/01  07:54:09  jopi
+ * X64 0.3 PL 0
+ * Typedef for signed char.
+ * Room for new options for Printer charsets, Basic patch, REU size.
+ *
+ * Revision 1.3  1994/12/12  16:59:44  jopi
+ * 16-bit portability
+ *
+ * Revision 1.2  1994/08/10  18:34:13  jopi
+ * More changeability
+ *
+ * Revision 1.1  1994/06/16  17:19:26  jopi
+ * Initial revision
+ *
+ */
+
+
+#ifndef X64_TYPES_H
+#define X64_TYPES_H
+
+
+typedef signed char	SIGNED_CHAR;
+/*typedef char		SIGNED_CHAR;*/
+
+typedef unsigned char 	byte;
+typedef unsigned char 	BYTE;
+typedef unsigned short 	ADDRESS;
+typedef unsigned long	CLOCK;
+
+typedef int		ADDR_T;
+/*typedef long		ADDR_T;*/
+
+#endif  /* X64_TYPES_H */
diff --git a/MCUME_pico2/picovcs/vmachine.h b/MCUME_pico2/picovcs/vmachine.h
new file mode 100644
index 0000000..33a7be1
--- /dev/null
+++ b/MCUME_pico2/picovcs/vmachine.h
@@ -0,0 +1,148 @@
+/*****************************************************************************
+
+   This file is part of x2600, the Atari 2600 Emulator
+   ===================================================
+   
+   Copyright 1996 Alex Hornby. For contributions see the file CREDITS.
+
+   This software is distributed under the terms of the GNU General Public
+   License. This is free software with ABSOLUTELY NO WARRANTY.
+   
+   See the file COPYING for details.
+   
+   $Id: vmachine.h,v 2.13 1996/11/24 16:55:40 ahornby Exp $
+******************************************************************************/
+
+
+/*
+   External definitions of the 2600 virtual machine.
+*/
+
+
+#ifndef VMACHINE_H
+#define VMACHINE_H
+//#define BYTE char
+
+extern int rom_size;
+//JMH
+extern BYTE *theCart;
+//extern BYTE theCart[4096];
+extern BYTE *theRom;
+extern BYTE *cartScratch;
+extern BYTE *cartRam;
+extern BYTE theRam[];
+extern BYTE riotRead[];
+extern BYTE riotWrite[];
+extern BYTE tiaWrite[];
+extern BYTE tiaRead[];
+extern BYTE keypad[2][4];
+
+extern int reset_flag;
+
+extern int ebeamx, ebeamy, sbeamx;
+
+#define VSYNCSTATE 1
+#define VBLANKSTATE 2
+#define HSYNCSTATE 4
+#define DRAWSTATE 8
+#define OVERSTATE 16 
+
+extern int vbeam_state, hbeam_state;
+
+extern int tv_width, tv_height, tv_vsync, tv_vblank,
+    tv_overscan, tv_frame, tv_hertz, tv_hsync;
+
+extern int timer_res, timer_count, timer_clks; 
+
+typedef struct  {
+    BYTE pf0,pf1,pf2;
+    BYTE ref;
+} PlayField;  
+
+extern PlayField pf[2];  
+
+typedef struct  {
+    int pos;
+    int val;
+} Paddle;
+
+extern Paddle paddle[4];
+typedef struct {
+  int x;
+  BYTE grp;
+  BYTE hmm;
+  BYTE vdel;
+  BYTE vdel_flag;
+  BYTE nusize;
+  BYTE reflect;
+  BYTE mask;
+} Player;
+
+extern Player pl[2];
+
+struct RasterChange {
+  int x;     /* Position at which change happened */
+  int type;  /* Type of change */
+  int val;   /* Value of change */
+} ;
+
+extern struct RasterChange pl_change[2][80], pf_change[1][80], unified[80];
+
+extern int pl_change_count[2], pf_change_count[1], unified_count;
+
+/* The missile and ball positions */
+typedef struct {
+    int x;
+    BYTE hmm;
+    BYTE locked;
+    BYTE enabled;
+    BYTE width;
+    BYTE vdel;
+    BYTE vdel_flag;
+    BYTE mask;
+} Missile;
+
+extern Missile ml[3];
+
+/****************************************************************************
+                              functions.
+*****************************************************************************/
+
+extern __inline void 
+do_plraster_change(int i, int type, int val);
+
+extern __inline void
+do_unified_change(int type, int val);
+
+extern __inline void
+use_unified_change( struct RasterChange *rc);
+
+extern __inline void 
+use_plraster_change( Player *pl, struct RasterChange *rc);
+
+extern __inline void
+do_pfraster_change(int i, int type, int val);
+
+extern __inline void
+use_pfraster_change( PlayField *pf, struct RasterChange *rc);
+
+void init_machine(void);
+void init_hardware(void);
+void init_banking(void);
+
+extern __inline void set_timer(int res, int count, int clkadj);
+extern __inline BYTE do_timer(int clkadj);
+extern __inline void do_vblank(BYTE b);
+extern __inline void do_hsync(void);
+
+int  do_paddle(int padnum);
+BYTE do_keypad(int pad, int col);
+extern __inline void do_screen(int clks);
+
+#endif
+
+
+
+
+
+
diff --git a/MCUME_pico2/psram/.gitignore b/MCUME_pico2/psram/.gitignore
new file mode 100755
index 0000000..8072471
--- /dev/null
+++ b/MCUME_pico2/psram/.gitignore
@@ -0,0 +1,4 @@
+.DS_Store
+*~
+*.swp
+*.swo
diff --git a/MCUME_pico2/psram/CMakeLists.txt b/MCUME_pico2/psram/CMakeLists.txt
new file mode 100755
index 0000000..da50310
--- /dev/null
+++ b/MCUME_pico2/psram/CMakeLists.txt
@@ -0,0 +1,46 @@
+# Generated Cmake Pico project file
+
+cmake_minimum_required(VERSION 3.13)
+
+set(CMAKE_C_STANDARD 11)
+
+project(rp2040-psram
+    VERSION 1.0.0
+    DESCRIPTION "A header-only library to allow access to SPI PSRAM via PIO on the RP2040 microcontroller."
+)
+
+add_library(rp2040-psram INTERFACE)
+
+target_sources(rp2040-psram INTERFACE
+        psram_spi.c
+)
+target_include_directories(rp2040-psram INTERFACE ${CMAKE_CURRENT_LIST_DIR})
+
+if(PICO_SDK)
+    pico_generate_pio_header(rp2040-psram ${CMAKE_CURRENT_LIST_DIR}/psram_spi.pio)
+endif(PICO_SDK)
+
+option(BUILD_PSRAM_DOCS "Build documentation" OFF)
+
+if(BUILD_PSRAM_DOCS)
+    # check if Doxygen is installed
+    find_package(Doxygen)
+    if (DOXYGEN_FOUND)
+        # set input and output files
+        set(DOXYGEN_IN ${CMAKE_CURRENT_SOURCE_DIR}/Doxyfile.in)
+        set(DOXYGEN_OUT ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile)
+
+        # request to configure the file
+        configure_file(${DOXYGEN_IN} ${DOXYGEN_OUT} @ONLY)
+        message("Doxygen build started")
+
+        # note the option ALL which allows to build the docs together with the application
+        add_custom_target( doc_doxygen ALL
+            COMMAND ${DOXYGEN_EXECUTABLE} ${DOXYGEN_OUT}
+            WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
+            COMMENT "Generating API documentation with Doxygen"
+            VERBATIM )
+    else (DOXYGEN_FOUND)
+      message("Doxygen need to be installed to generate the doxygen documentation")
+    endif (DOXYGEN_FOUND)
+endif(BUILD_PSRAM_DOCS)
diff --git a/MCUME_pico2/psram/Doxyfile.in b/MCUME_pico2/psram/Doxyfile.in
new file mode 100755
index 0000000..5661f2b
--- /dev/null
+++ b/MCUME_pico2/psram/Doxyfile.in
@@ -0,0 +1,6 @@
+PROJECT_NAME = "@CMAKE_PROJECT_NAME@"
+PROJECT_BRIEF = "@CMAKE_PROJECT_DESCRIPTION@"
+PROJECT_NUMBER = "@CMAKE_PROJECT_VERSION@"
+GENERATE_LATEX = NO
+OUTPUT_DIRECTORY = @CMAKE_CURRENT_BINARY_DIR@/docs/
+INPUT = @CMAKE_CURRENT_SOURCE_DIR@
diff --git a/MCUME_pico2/psram/LICENSE b/MCUME_pico2/psram/LICENSE
new file mode 100755
index 0000000..8fc2247
--- /dev/null
+++ b/MCUME_pico2/psram/LICENSE
@@ -0,0 +1,19 @@
+Copyright © 2023 Ian Scott
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the “Software�), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED “AS IS�, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/MCUME_pico2/psram/README.md b/MCUME_pico2/psram/README.md
new file mode 100755
index 0000000..625697e
--- /dev/null
+++ b/MCUME_pico2/psram/README.md
@@ -0,0 +1,69 @@
+# rp2040-psram
+
+A header-only C library to allow access to SPI PSRAM via PIO on the RP2040 microcontroller as used on the Raspberry Pi Pico. Due to the timing requirements of these PSRAM devices, reading data from them at high speed (>84MHz) requires the following clock behavior:
+
+- Read data needs to be sampled on the clock falling edge.
+- An extra "fudge factor" clock cycle is required before reading data.
+
+I could not get the hardware SPI interface on the RP2040 to work at high speed with this behavior, so I created a PIO SPI implementation specifically tailored to the behavior of the PSRAM chips and optimized for the highest speed possible:
+
+- A read or write command is given, followed by an optional read of data.
+- Chip select is driven by PIO.
+- DMA is used so CPU cycles are not used to service the PIO TX and RX FIFOs.
+- Special optimized functions are provided for writing 8, 16, and 32 bit data as fast as possible.
+- All functions are tagged with `__force_inline` for the fastest speed possible.
+
+Tested PSRAM chips:
+
+- apmemory APS6404L
+- Lyontek LY68L6400
+- IPUS IPS6404
+- Espressif ESP-PSRAM64H
+
+These chips have been tested as stable up to an RP2040 clock speed of 280MHz, creating an effecitve SPI clock speed of 140MHz.
+
+## Examples
+
+An example that tests the PSRAM by writing and reading 8MB of data with 8, 16, 32, and 128 bit access sizes is included in the `examples/` directory.
+
+## Using this library
+
+### Hardware connections
+
+Due to using sideset to drive the CS and SCK signals, those two pins must be on consecutive GPIOs. For example, if CS is on GPIO 0, SCK must be on GPIO 1. MOSI and MISO may be on any pin and do not need to be adjacent.
+
+QSPI support is on the roadmap for the future. If you plan on using QSPI, SIO[0] through SIO[3] must be on consecutive GPIOs.
+
+### Including in the build
+
+Clone this repository and copy to a subdirectory or add as a submodule in your project. In your project's `CMakeLists.txt` file, add the following:
+
+```
+add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/rp2040-psram rp2040-psram)
+```
+
+And then add `rp2040-psram` to your project's `target_link_libraries`.
+
+### Using in your code
+
+Include `psram_spi.h` in your file. See the [documentation for this file](https://polpo.github.io/rp2040-psram/psram__spi_8h.html) for how to initialize and use this library.
+
+The following defines _MUST_ be defined:
+
+- `PSRAM_PIN_CS` - GPIO number of the chip select pin
+- `PSRAM_PIN_SCK` - GPIO number of the clock pin
+- `PSRAM_PIN_MOSI` - GPIO number of the MOSI pin
+- `PSRAM_PIN_MISO` - GPIO number of the MISO pin
+
+Optional define:
+
+- `PSRAM_MUTEX` - Define this to put PSRAM access behind a mutex. This must be used if the PSRAM is to be used by multiple cores.
+
+
+## Projects that use rp2040-psram
+
+[PicoGUS](https://github.com/polpo/picogus) - uses PSRAM to emulate the Gravis Ultrasound's 1MB sample RAM
+
+# License
+
+rp2040-psram is licensed under the MIT license (see LICENSE)
diff --git a/MCUME_pico2/psram/examples/CMakeLists.txt b/MCUME_pico2/psram/examples/CMakeLists.txt
new file mode 100755
index 0000000..e50d63c
--- /dev/null
+++ b/MCUME_pico2/psram/examples/CMakeLists.txt
@@ -0,0 +1,57 @@
+cmake_minimum_required(VERSION 3.13)
+
+set(CMAKE_C_STANDARD 11)
+
+# Initialise pico_sdk from installed location
+# (note this can come from environment, CMake cache etc)
+set(PICO_SDK_PATH "${CMAKE_SOURCE_DIR}/../../pico/pico-sdk")
+
+# Pull in Raspberry Pi Pico SDK (must be before project)
+include(pico_sdk_import.cmake)
+
+project(psram-test C CXX ASM)
+
+set(CMAKE_BUILD_TYPE "Release")
+set(PICO_COPY_TO_RAM 1)
+
+# Initialise the Raspberry Pi Pico SDK
+pico_sdk_init()
+
+add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/.. rp2040-psram)
+
+# Add executable. Default name is the project name, version 0.1
+add_executable(psram-test psram-test.c)
+pico_set_program_version(psram-test "1.0.0")
+
+add_compile_definitions(
+    PICO_DEFAULT_UART=0
+    PICO_DEFAULT_UART_TX_PIN=0
+    PICO_DEFAULT_UART_RX_PIN=-1
+)
+
+target_compile_definitions(psram-test PRIVATE
+    # PSRAM_MUTEX=1
+    PSRAM_SPINLOCK=1
+    PSRAM_ASYNC=1
+    PSRAM_PIN_CS=9
+    PSRAM_PIN_SCK=10
+    PSRAM_PIN_MOSI=11
+    PSRAM_PIN_MISO=12
+)
+
+target_link_libraries(
+    psram-test
+    rp2040-psram
+    pico_stdlib
+    hardware_pio
+    hardware_dma
+    hardware_pll
+)
+
+pico_add_extra_outputs(psram-test)
+
+add_custom_target(
+    program
+    DEPENDS psram-test
+    COMMAND openocd -f interface/picoprobe.cfg -f target/rp2040.cfg -c "program ${CMAKE_CURRENT_BINARY_DIR}/psram-test.elf verify reset exit"
+)
diff --git a/MCUME_pico2/psram/examples/pico_sdk_import.cmake b/MCUME_pico2/psram/examples/pico_sdk_import.cmake
new file mode 100755
index 0000000..65f8a6f
--- /dev/null
+++ b/MCUME_pico2/psram/examples/pico_sdk_import.cmake
@@ -0,0 +1,73 @@
+# This is a copy of <PICO_SDK_PATH>/external/pico_sdk_import.cmake
+
+# This can be dropped into an external project to help locate this SDK
+# It should be include()ed prior to project()
+
+if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH))
+    set(PICO_SDK_PATH $ENV{PICO_SDK_PATH})
+    message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT))
+    set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT})
+    message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH))
+    set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH})
+    message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')")
+endif ()
+
+set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK")
+set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable")
+set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK")
+
+if (NOT PICO_SDK_PATH)
+    if (PICO_SDK_FETCH_FROM_GIT)
+        include(FetchContent)
+        set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR})
+        if (PICO_SDK_FETCH_FROM_GIT_PATH)
+            get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}")
+        endif ()
+        # GIT_SUBMODULES_RECURSE was added in 3.17
+        if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0")
+            FetchContent_Declare(
+                    pico_sdk
+                    GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk
+                    GIT_TAG master
+                    GIT_SUBMODULES_RECURSE FALSE
+            )
+        else ()
+            FetchContent_Declare(
+                    pico_sdk
+                    GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk
+                    GIT_TAG master
+            )
+        endif ()
+
+        if (NOT pico_sdk)
+            message("Downloading Raspberry Pi Pico SDK")
+            FetchContent_Populate(pico_sdk)
+            set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR})
+        endif ()
+        set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE})
+    else ()
+        message(FATAL_ERROR
+                "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git."
+                )
+    endif ()
+endif ()
+
+get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
+if (NOT EXISTS ${PICO_SDK_PATH})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found")
+endif ()
+
+set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake)
+if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK")
+endif ()
+
+set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
+
+include(${PICO_SDK_INIT_CMAKE_FILE})
diff --git a/MCUME_pico2/psram/examples/psram-test.c b/MCUME_pico2/psram/examples/psram-test.c
new file mode 100755
index 0000000..fdc15db
--- /dev/null
+++ b/MCUME_pico2/psram/examples/psram-test.c
@@ -0,0 +1,152 @@
+#include <stdio.h>
+#include <string.h>
+
+#include <pico/stdlib.h>
+
+#include "psram_spi.h"
+
+psram_spi_inst_t* async_spi_inst;
+
+int main()
+{
+    // Overclock!
+    set_sys_clock_khz(280000, true);
+
+    stdio_init_all();
+    
+    puts("PSRAM test - rp2040-psram v1.0.0");
+
+    puts("Initing PSRAM...");
+    psram_spi_inst_t psram_spi = psram_spi_init(pio0, -1);
+
+    uint32_t psram_begin, psram_elapsed;
+    float psram_speed;
+
+    puts("Testing PSRAM...");
+
+    // **************** 8 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+        psram_write8(&psram_spi, addr, (addr & 0xFF));
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("8 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+        psram_write8_async(&psram_spi, addr, (addr & 0xFF));
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("8 bit: PSRAM write async 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); ++addr) {
+        uint8_t result = psram_read8(&psram_spi, addr);
+        if ((uint8_t)(addr & 0xFF) != result) {
+            printf("\nPSRAM failure at address %x (%x != %x)\n", addr, addr & 0xFF, result);
+            return 1;
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("8 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** 16 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 2) {
+        psram_write16(&psram_spi, addr, (((addr + 1) & 0xFF) << 8) | (addr & 0xFF));
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("16 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 2) {
+        uint16_t result = psram_read16(&psram_spi, addr);
+        if ((uint16_t)(
+                (((addr + 1) & 0xFF) << 8) |
+                (addr & 0xFF)) != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, (
+                (((addr + 1) & 0xFF) << 8) |
+                (addr & 0xFF)), result
+            );
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 8 * 1024 * 1024 / psram_elapsed;
+    printf("16 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** 32 bits testing ****************
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 4) {
+        psram_write32(
+            &psram_spi, addr,
+            (uint32_t)(
+                (((addr + 3) & 0xFF) << 24) |
+                (((addr + 2) & 0xFF) << 16) |
+                (((addr + 1) & 0xFF) << 8)  |
+                (addr & 0XFF))
+        );
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("32 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 4) {
+        uint32_t result = psram_read32(&psram_spi, addr);
+        if ((uint32_t)(
+            (((addr + 3) & 0xFF) << 24) |
+            (((addr + 2) & 0xFF) << 16) |
+            (((addr + 1) & 0xFF) << 8)  |
+            (addr & 0XFF)) != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, (
+                (((addr + 3) & 0xFF) << 24) |
+                (((addr + 2) & 0xFF) << 16) |
+                (((addr + 1) & 0xFF) << 8)  |
+                (addr & 0XFF)), result
+            );
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 8 * 1024 * 1024 / psram_elapsed;
+    printf("32 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    // **************** n bits testing ****************
+    uint8_t write_data[256];
+    for (size_t i = 0; i < 256; ++i) {
+        write_data[i] = i;
+    }
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 256) {
+        for (uint32_t step = 0; step < 256; step += 16) {
+            psram_write(&psram_spi, addr + step, write_data + step, 16);
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("128 bit: PSRAM write 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    uint8_t read_data[16];
+    for (uint32_t addr = 0; addr < (8 * 1024 * 1024); addr += 256) {
+        for (uint32_t step = 0; step < 256; step += 16) {
+            psram_read(&psram_spi, addr + step, read_data, 16);
+            if (memcmp(read_data, write_data + step, 16) != 0) {
+                printf("PSRAM failure at address %x", addr);
+                return 1;
+            }
+        }
+    }
+    psram_elapsed = time_us_32() - psram_begin;
+    psram_speed = 1000000.0 * 8 * 1024.0 * 1024 / psram_elapsed;
+    printf("128 bit: PSRAM read 8MB in %d us, %d B/s\n", psram_elapsed, (uint32_t)psram_speed);
+
+
+}
diff --git a/MCUME_pico2/psram/psram_spi.c b/MCUME_pico2/psram/psram_spi.c
new file mode 100755
index 0000000..0b2c815
--- /dev/null
+++ b/MCUME_pico2/psram/psram_spi.c
@@ -0,0 +1,234 @@
+/******************************************************************************
+
+rp2040-psram
+
+Copyright © 2023 Ian Scott
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the “Software�), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED “AS IS�, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+******************************************************************************/
+#include "psram_spi.h"
+
+#include <stdio.h>
+
+
+#if defined(PSRAM_ASYNC) && defined(PSRAM_ASYNC_SYNCHRONIZE)
+void __isr psram_dma_complete_handler() {
+#if PSRAM_ASYNC_DMA_IRQ == 0
+    dma_hw->ints0 = 1u << async_spi_inst->async_dma_chan;
+#elif PSRAM_ASYNC_DMA_IRQ == 1
+    dma_hw->ints1 = 1u << async_spi_inst->async_dma_chan;
+#else
+#error "PSRAM_ASYNC defined without PSRAM_ASYNC_DMA_IRQ set to 0 or 1"
+#endif
+    /* putchar('@'); */
+#if defined(PSRAM_MUTEX)
+    mutex_exit(&async_spi_inst->mtx);
+#elif defined(PSRAM_SPINLOCK)
+    spin_unlock(async_spi_inst->spinlock, async_spi_inst->spin_irq_state);
+#endif
+}
+#endif // defined(PSRAM_ASYNC) && defined(PSRAM_ASYNC_SYNCHRONIZE)
+
+psram_spi_inst_t psram_spi_init_clkdiv(PIO pio, int sm, float clkdiv, bool fudge) {
+    psram_spi_inst_t spi;
+    spi.pio = pio;
+    spi.offset = pio_add_program(spi.pio, fudge ? &spi_psram_fudge_program : &spi_psram_program);
+    if (sm == -1) {
+        spi.sm = pio_claim_unused_sm(spi.pio, true);
+    } else {
+        spi.sm = sm;
+    }
+#if defined(PSRAM_MUTEX)
+    mutex_init(&spi.mtx);
+#elif defined(PSRAM_SPINLOCK)
+    int spin_id = spin_lock_claim_unused(true);
+    spi.spinlock = spin_lock_init(spin_id);
+#endif
+    //gpio_set_drive_strength(PSRAM_PIN_CS, GPIO_DRIVE_STRENGTH_4MA);
+    //gpio_set_drive_strength(PSRAM_PIN_SCK, GPIO_DRIVE_STRENGTH_4MA);
+    //gpio_set_drive_strength(PSRAM_PIN_MOSI, GPIO_DRIVE_STRENGTH_4MA);
+    
+    gpio_init(PSRAM_PIN_SCK);
+    gpio_pull_up(PSRAM_PIN_SCK);
+    gpio_init(PSRAM_PIN_MISO);
+    gpio_pull_up(PSRAM_PIN_MISO);
+    gpio_init(PSRAM_PIN_MOSI);
+    gpio_pull_up(PSRAM_PIN_MOSI);
+    gpio_init(PSRAM_PIN_CS);
+    gpio_pull_up(PSRAM_PIN_CS);
+
+    /* gpio_set_slew_rate(PSRAM_PIN_CS, GPIO_SLEW_RATE_FAST); */
+    /* gpio_set_slew_rate(PSRAM_PIN_SCK, GPIO_SLEW_RATE_FAST); */
+    /* gpio_set_slew_rate(PSRAM_PIN_MOSI, GPIO_SLEW_RATE_FAST); */
+
+    pio_spi_psram_cs_init(spi.pio, spi.sm, spi.offset, 8 /*n_bits*/, clkdiv, fudge, PSRAM_PIN_CS, PSRAM_PIN_MOSI, PSRAM_PIN_MISO);
+
+    // Write DMA channel setup
+    spi.write_dma_chan = PSR_DMA_CHANNEL; //dma_claim_unused_channel(true);
+    spi.write_dma_chan_config = dma_channel_get_default_config(spi.write_dma_chan);
+    channel_config_set_transfer_data_size(&spi.write_dma_chan_config, DMA_SIZE_8);
+    channel_config_set_read_increment(&spi.write_dma_chan_config, true);
+    channel_config_set_write_increment(&spi.write_dma_chan_config, false);
+    channel_config_set_dreq(&spi.write_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, true));
+    dma_channel_set_write_addr(spi.write_dma_chan, &spi.pio->txf[spi.sm], false);
+    dma_channel_set_config(spi.write_dma_chan, &spi.write_dma_chan_config, false);
+
+    // Read DMA channel setup
+    spi.read_dma_chan = PSR_DMA_CHANNEL+1; //dma_claim_unused_channel(true);
+    spi.read_dma_chan_config = dma_channel_get_default_config(spi.read_dma_chan);
+    channel_config_set_transfer_data_size(&spi.read_dma_chan_config, DMA_SIZE_8);
+    channel_config_set_read_increment(&spi.read_dma_chan_config, false);
+    channel_config_set_write_increment(&spi.read_dma_chan_config, true);
+    channel_config_set_dreq(&spi.read_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, false));
+    dma_channel_set_read_addr(spi.read_dma_chan, &spi.pio->rxf[spi.sm], false);
+    dma_channel_set_config(spi.read_dma_chan, &spi.read_dma_chan_config, false);
+
+#if defined(PSRAM_ASYNC)
+    // Asynchronous DMA channel setup
+    spi.async_dma_chan = dma_claim_unused_channel(true);
+    spi.async_dma_chan_config = dma_channel_get_default_config(spi.async_dma_chan);
+    channel_config_set_transfer_data_size(&spi.async_dma_chan_config, DMA_SIZE_8);
+    channel_config_set_read_increment(&spi.async_dma_chan_config, true);
+    channel_config_set_write_increment(&spi.async_dma_chan_config, false);
+    channel_config_set_dreq(&spi.async_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, true));
+    dma_channel_set_write_addr(spi.async_dma_chan, &spi.pio->txf[spi.sm], false);
+    dma_channel_set_config(spi.async_dma_chan, &spi.async_dma_chan_config, false);
+
+#if defined(PSRAM_ASYNC_COMPLETE)
+    irq_set_exclusive_handler(DMA_IRQ_0 + PSRAM_ASYNC_DMA_IRQ, psram_dma_complete_handler);
+    dma_irqn_set_channel_enabled(PSRAM_ASYNC_DMA_IRQ, spi.async_dma_chan, true);
+    irq_set_enabled(DMA_IRQ_0 + PSRAM_ASYNC_DMA_IRQ, true);
+#endif // defined(PSRAM_ASYNC_COMPLETE)
+#endif // defined(PSRAM_ASYNC)
+
+    uint8_t psram_reset_en_cmd[] = {
+        8,      // 8 bits to write
+        0,      // 0 bits to read
+        0x66u   // Reset enable command
+    };
+    pio_spi_write_read_dma_blocking(&spi, psram_reset_en_cmd, 3, 0, 0);
+    busy_wait_us(50);
+    uint8_t psram_reset_cmd[] = {
+        8,      // 8 bits to write
+        0,      // 0 bits to read
+        0x99u   // Reset command
+    };
+    pio_spi_write_read_dma_blocking(&spi, psram_reset_cmd, 3, 0, 0);
+    busy_wait_us(100);
+    
+    return spi;
+};
+
+psram_spi_inst_t psram_spi_init(PIO pio, int sm) {
+    return psram_spi_init_clkdiv(pio, sm, 1.0, true);
+}
+
+void psram_spi_uninit(psram_spi_inst_t spi, bool fudge) {
+#if defined(PSRAM_ASYNC)
+    // Asynchronous DMA channel teardown
+    dma_channel_unclaim(spi.async_dma_chan);
+#if defined(PSRAM_ASYNC_COMPLETE)
+    irq_set_enabled(DMA_IRQ_0 + PSRAM_ASYNC_DMA_IRQ, false);
+    dma_irqn_set_channel_enabled(PSRAM_ASYNC_DMA_IRQ, spi.async_dma_chan, false);
+    irq_remove_handler(DMA_IRQ_0 + PSRAM_ASYNC_DMA_IRQ, psram_dma_complete_handler);
+#endif // defined(PSRAM_ASYNC_COMPLETE)
+#endif // defined(PSRAM_ASYNC)
+
+    // Write DMA channel teardown
+    dma_channel_unclaim(spi.write_dma_chan);
+
+    // Read DMA channel teardown
+    dma_channel_unclaim(spi.read_dma_chan);
+
+#if defined(PSRAM_SPINLOCK)
+    int spin_id = spin_lock_get_num(spi.spinlock);
+    spin_lock_unclaim(spin_id);
+#endif
+
+    pio_sm_unclaim(spi.pio, spi.sm);
+    pio_remove_program(spi.pio, fudge ? &spi_psram_fudge_program : &spi_psram_program, spi.offset);
+}
+
+int test_psram(psram_spi_inst_t* psram_spi, int increment) {
+    puts("Writing PSRAM...");
+    uint8_t deadbeef[8] = {0xd, 0xe, 0xa, 0xd, 0xb, 0xe, 0xe, 0xf};
+    /* uncomment to write 8 bits at a time. the below for loop for 32-bit writes is much faster
+    for (uint32_t addr = 0; addr < (1024 * 1024); ++addr) {
+        psram_write8(psram_spi, addr, (addr & 0xFF));
+        // psram_write8_async(psram_spi, addr, (addr & 0xFF));
+    }
+    */
+    for (uint32_t addr = 0; addr < (1024 * 1024); addr += 4) {
+        uint32_t value = (uint32_t)(
+            (((addr + 3) & 0xFF) << 24) |
+            (((addr + 2) & 0xFF) << 16) |
+            (((addr + 1) & 0xFF) << 8)  |
+            (addr & 0XFF));
+        psram_write32(psram_spi, addr, value);
+    }
+    puts("Reading PSRAM...");
+    uint32_t psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (1024 * 1024); addr += increment) {
+        uint8_t result = psram_read8(psram_spi, addr);
+        uint8_t test = (uint8_t)(addr & 0xFF);
+        if (test != result) {
+            printf("\nPSRAM failure at address %x (%x != %x)\n", addr, test, result);
+            return 1;
+        }
+    }
+    uint32_t psram_elapsed = time_us_32() - psram_begin;
+    float psram_speed = 1000000.0 * 1024.0 * 1024 / psram_elapsed / increment;
+    printf("8 bit: PSRAM read in %d us, %d B/s (target 705600 B/s)\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (1024 * 1024); addr += (2 * increment)) {
+        uint16_t result = psram_read16(psram_spi, addr);
+        uint16_t test = (uint16_t)(
+            (((addr + 1) & 0xFF) << 8) |
+            (addr & 0XFF));
+        if (test != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, test, result);
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 1024 * 1024 / psram_elapsed / increment;
+    printf("16 bit: PSRAM read in %d us, %d B/s (target 1411200 B/s)\n", psram_elapsed, (uint32_t)psram_speed);
+
+    psram_begin = time_us_32();
+    for (uint32_t addr = 0; addr < (1024 * 1024); addr += (4 * increment)) {
+        uint32_t result = psram_read32(psram_spi, addr);
+        uint32_t test = (uint32_t)(
+            (((addr + 3) & 0xFF) << 24) |
+            (((addr + 2) & 0xFF) << 16) |
+            (((addr + 1) & 0xFF) << 8)  |
+            (addr & 0XFF));
+        if (test != result
+        ) {
+            printf("PSRAM failure at address %x (%x != %x) ", addr, test, result);
+            return 1;
+        }
+    }
+    psram_elapsed = (time_us_32() - psram_begin);
+    psram_speed = 1000000.0 * 1024 * 1024 / psram_elapsed / increment;
+    printf("32 bit: PSRAM read in %d us, %d B/s (target 1411200 B/s)\n", psram_elapsed, (uint32_t)psram_speed);
+    return 0;
+}
diff --git a/MCUME_pico2/psram/psram_spi.h b/MCUME_pico2/psram/psram_spi.h
new file mode 100755
index 0000000..1c7080d
--- /dev/null
+++ b/MCUME_pico2/psram/psram_spi.h
@@ -0,0 +1,615 @@
+/******************************************************************************
+
+rp2040-psram
+
+Copyright © 2023 Ian Scott
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the “Software�), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED “AS IS�, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+******************************************************************************/
+
+/**
+ * @file psram_spi.h
+ *
+ * \mainpage
+ *
+ * The interface to this file is defined in psram_spi.h. Please see the
+ * documentation for this file.
+ *
+ * The following defines _MUST_ be defined:
+ *
+ * - @c PSRAM_PIN_CS - GPIO number of the chip select pin
+ * - @c PSRAM_PIN_SCK - GPIO number of the clock pin
+ * - @c PSRAM_PIN_MOSI - GPIO number of the MOSI pin
+ * - @c PSRAM_PIN_MISO - GPIO number of the MISO pin
+ *
+ * Optional define:
+ * - @c PSRAM_MUTEX - Define this to put PSRAM access behind a mutex. This must
+ * be used if the PSRAM is to be used by multiple cores.
+ *
+ * Project homepage: https://github.com/polpo/rp2040-psram
+ */
+
+#pragma once
+#include "iopins.h"
+#include "hardware/pio.h"
+#include "hardware/gpio.h"
+#include "hardware/timer.h"
+#include "hardware/dma.h"
+#if defined(PSRAM_MUTEX)
+#include "pico/mutex.h"
+#elif defined(PSRAM_SPINLOCK)
+#include "hardware/sync.h"
+#endif
+#include <string.h>
+
+#include "psram_spi.pio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief A struct that holds the configuration for the PSRAM interface.
+ *
+ * This struct is generated by psram_spi_init() and must be passed to all calls to
+ * the psram access functions.
+ */
+typedef struct psram_spi_inst {
+    PIO pio;
+    int sm;
+    uint offset;
+#if defined(PSRAM_MUTEX)
+    mutex_t mtx;
+#elif defined(PSRAM_SPINLOCK)
+    spin_lock_t* spinlock;
+    uint32_t spin_irq_state;
+#endif
+    int write_dma_chan;
+    dma_channel_config write_dma_chan_config;
+    int read_dma_chan;
+    dma_channel_config read_dma_chan_config;
+#if defined(PSRAM_ASYNC)
+    int async_dma_chan;
+    dma_channel_config async_dma_chan_config;
+#endif
+} psram_spi_inst_t;
+
+#if defined(PSRAM_ASYNC)
+extern psram_spi_inst_t* async_spi_inst;
+#endif
+
+/**
+ * @brief Write and read raw data to the PSRAM SPI PIO, driven by the CPU
+ * without DMA. This can be used if DMA has not yet been initialized.
+ *
+ * Used to send raw commands and receive data from the PSRAM. Usually the @c
+ * psram_write*() and @c psram_read*() commands should be used instead.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param src Pointer to the source data to write.
+ * @param src_len Length of the source data in bytes.
+ * @param dst Pointer to the destination for read data, if any. Set to 0 or NULL
+ * if no data is to be read.
+ * @param dst_len Length of the destination data in bytes. Set to 0 if no data
+ * is to be read.
+ */
+__force_inline static void __time_critical_func(pio_spi_write_read_blocking)(
+        psram_spi_inst_t* spi,
+        const uint8_t* src, const size_t src_len,
+        uint8_t* dst, const size_t dst_len
+) {
+    size_t tx_remain = src_len, rx_remain = dst_len;
+
+#if defined(PSRAM_MUTEX)
+    mutex_enter_blocking(&spi->mtx); 
+#elif defined(PSRAM_SPINLOCK)
+    spi->spin_irq_state = spin_lock_blocking(spi->spinlock);
+#endif
+    io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
+    while (tx_remain) {
+        if (!pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
+            *txfifo = *src++;
+            --tx_remain;
+        }
+    }
+
+    io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
+    while (rx_remain) {
+        if (!pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
+            *dst++ = *rxfifo;
+            --rx_remain;
+        }
+    }
+
+#if defined(PSRAM_MUTEX)
+    mutex_exit(&spi->mtx);
+#elif defined(PSRAM_SPINLOCK)
+    spin_unlock(spi->spinlock, spi->spin_irq_state);
+#endif
+}
+
+/**
+ * @brief Write raw data to the PSRAM SPI PIO, driven by DMA without CPU
+ * involvement. 
+ *
+ * It's recommended to use DMA when possible as it's higher speed. Used to send
+ * raw commands to the PSRAM. This function is faster than
+ * pio_spi_write_read_dma_blocking() if no data is to be read.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param src Pointer to the source data to write.
+ * @param src_len Length of the source data in bytes.
+ */
+__force_inline static void __time_critical_func(pio_spi_write_dma_blocking)(
+        psram_spi_inst_t* spi,
+        const uint8_t* src, const size_t src_len
+) {
+#ifdef PSRAM_MUTEX
+    mutex_enter_blocking(&spi->mtx); 
+#elif defined(PSRAM_SPINLOCK)
+    spi->spin_irq_state = spin_lock_blocking(spi->spinlock);
+#endif // PSRAM_SPINLOCK
+#if defined(PSRAM_WAITDMA)
+#if defined(PSRAM_ASYNC)
+    dma_channel_wait_for_finish_blocking(spi->async_dma_chan);
+#endif // PSRAM_ASYNC
+    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
+    dma_channel_wait_for_finish_blocking(spi->read_dma_chan);
+#endif // PSRAM_WAITDMA
+    dma_channel_transfer_from_buffer_now(spi->write_dma_chan, src, src_len);
+    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
+#ifdef PSRAM_MUTEX
+    mutex_exit(&spi->mtx);
+#elif defined(PSRAM_SPINLOCK)
+    spin_unlock(spi->spinlock, spi->spin_irq_state);
+#endif // PSRAM_SPINLOCK
+}
+
+/**
+ * @brief Write and read raw data to the PSRAM SPI PIO, driven by DMA without CPU
+ * involvement. 
+ *
+ * It's recommended to use DMA when possible as it's higher speed. Used to send
+ * raw commands and receive data from the PSRAM. Usually the @c psram_write* and
+ * @c psram_read* commands should be used instead.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param src Pointer to the source data to write.
+ * @param src_len Length of the source data in bytes.
+ * @param dst Pointer to the destination for read data, if any. Set to 0 or NULL
+ * if no data is to be read.
+ * @param dst_len Length of the destination data in bytes. Set to 0 if no data
+ * is to be read.
+ */
+__force_inline static void __time_critical_func(pio_spi_write_read_dma_blocking)(
+        psram_spi_inst_t* spi,
+        const uint8_t* src, const size_t src_len,
+        uint8_t* dst, const size_t dst_len
+) {
+#ifdef PSRAM_MUTEX
+    mutex_enter_blocking(&spi->mtx); 
+#elif defined(PSRAM_SPINLOCK)
+    spi->spin_irq_state = spin_lock_blocking(spi->spinlock);
+#endif // PSRAM_SPINLOCK
+#if defined(PSRAM_WAITDMA)
+#if defined(PSRAM_ASYNC)
+    dma_channel_wait_for_finish_blocking(spi->async_dma_chan);
+#endif // PSRAM_ASYNC
+    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
+    dma_channel_wait_for_finish_blocking(spi->read_dma_chan);
+#endif // PSRAM_WAITDMA
+    dma_channel_transfer_from_buffer_now(spi->write_dma_chan, src, src_len);
+    dma_channel_transfer_to_buffer_now(spi->read_dma_chan, dst, dst_len);
+    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
+    dma_channel_wait_for_finish_blocking(spi->read_dma_chan);
+#ifdef PSRAM_MUTEX
+    mutex_exit(&spi->mtx);
+#elif defined(PSRAM_SPINLOCK)
+    spin_unlock(spi->spinlock, spi->spin_irq_state);
+#endif // PSRAM_SPINLOCK
+}
+
+/**
+ * @brief Write raw data asynchronously to the PSRAM SPI PIO, driven by DMA without CPU
+ * involvement. 
+ *
+ * Used to send raw commands to the PSRAM. Usually the @c psram_write*_async()
+ * command should be used instead.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param src Pointer to the source data to write.
+ * @param src_len Length of the source data in bytes.
+ */
+#if defined(PSRAM_ASYNC)
+__force_inline static void __time_critical_func(pio_spi_write_async)(
+        psram_spi_inst_t* spi,
+        const uint8_t* src, const size_t src_len
+) {
+#if defined(PSRAM_ASYNC_SYNCHRONIZE)
+#ifdef PSRAM_MUTEX
+    mutex_enter_blocking(&spi->mtx); 
+#elif defined(PSRAM_SPINLOCK)
+    spi->spin_irq_state = spin_lock_blocking(spi->spinlock);
+#endif // PSRAM_SPINLOCK
+#endif // defined(PSRAM_ASYNC_SYNCHRONIZE)
+    // Wait for all DMA to PSRAM to complete
+    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
+    dma_channel_wait_for_finish_blocking(spi->read_dma_chan);
+    dma_channel_wait_for_finish_blocking(spi->async_dma_chan);
+    async_spi_inst = spi;
+
+    dma_channel_transfer_from_buffer_now(spi->async_dma_chan, src, src_len);
+}
+#endif
+
+
+/**
+ * @brief Initialize the PSRAM over SPI. This function must be called before
+ * accessing PSRAM.
+ *
+ * @param pio The PIO instance to use (PIO0 or PIO1).
+ * @param sm The state machine number in the PIO module to use. If -1 is given,
+ * will use the first available state machine.
+ * @param clkdiv Clock divisor for the state machine. At RP2040 speeds greater
+ * than 280MHz, a clkdiv >1.0 is needed. For example, at 400MHz, a clkdiv of
+ * 1.6 is recommended.
+ * @param fudge Whether to insert an extra "fudge factor" of one clock cycle
+ * before reading from the PSRAM. Depending on your PCB layout or PSRAM type,
+ * you may need to do this.
+ *
+ * @return The PSRAM configuration instance. This instance should be passed to
+ * all PSRAM access functions.
+ */
+psram_spi_inst_t psram_spi_init_clkdiv(PIO pio, int sm, float clkdiv, bool fudge);
+
+/**
+ * @brief Initialize the PSRAM over SPI. This function must be called before
+ * accessing PSRAM.
+ *
+ * Defaults to a clkdiv of 1.0. This function is provided for backwards
+ * compatibility. Use psram_spi_init_clkdiv instead if you want a clkdiv other
+ * than 1.0.
+ *
+ * @param pio The PIO instance to use (PIO0 or PIO1).
+ * @param sm The state machine number in the PIO module to use. If -1 is given,
+ * will use the first available state machine.
+ *
+ * @return The PSRAM configuration instance. This instance should be passed to
+ * all PSRAM access functions.
+ */
+psram_spi_inst_t psram_spi_init(PIO pio, int sm);
+int test_psram(psram_spi_inst_t* psram_spi, int increment);
+
+void psram_spi_uninit(psram_spi_inst_t spi, bool fudge);
+
+static uint8_t write8_command[] = {
+    40,         // 40 bits write
+    0,          // 0 bits read
+    0x02u,      // Write command
+    0, 0, 0,    // Address
+    0           // 8 bits data
+};
+/**
+ * @brief Write 8 bits of data to a given address asynchronously to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement.
+ *
+ * This function is optimized to write 8 bits as quickly as possible to the
+ * PSRAM as opposed to the more general-purpose psram_write() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param val Value to write.
+ */
+#if defined(PSRAM_ASYNC)
+__force_inline static void psram_write8_async(psram_spi_inst_t* spi, uint32_t addr, uint8_t val) {
+    write8_command[3] = addr >> 16;
+    write8_command[4] = addr >> 8;
+    write8_command[5] = addr;
+    write8_command[6] = val;
+
+    pio_spi_write_async(spi, write8_command, sizeof(write8_command));
+};
+#endif
+
+
+/**
+ * @brief Write 8 bits of data to a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the write is
+ * complete.
+ *
+ * This function is optimized to write 8 bits as quickly as possible to the
+ * PSRAM as opposed to the more general-purpose psram_write() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param val Value to write.
+ */
+__force_inline static void psram_write8(psram_spi_inst_t* spi, uint32_t addr, uint8_t val) {
+    write8_command[3] = addr >> 16;
+    write8_command[4] = addr >> 8;
+    write8_command[5] = addr;
+    write8_command[6] = val;
+
+    pio_spi_write_dma_blocking(spi, write8_command, sizeof(write8_command));
+};
+
+
+static uint8_t read8_command[] = {
+    40,         // 40 bits write
+    8,          // 8 bits read
+    0x0bu,      // Fast read command
+    0, 0, 0,    // Address
+    0           // 8 delay cycles
+};
+/**
+ * @brief Read 8 bits of data from a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the read is
+ * complete.
+ *
+ * This function is optimized to read 8 bits as quickly as possible from the
+ * PSRAM as opposed to the more general-purpose psram_read() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to read from.
+ * @return The data at the specified address.
+ */
+__force_inline static uint8_t psram_read8(psram_spi_inst_t* spi, uint32_t addr) {
+    read8_command[3] = addr >> 16;
+    read8_command[4] = addr >> 8;
+    read8_command[5] = addr;
+
+    uint8_t val; 
+    pio_spi_write_read_dma_blocking(spi, read8_command, sizeof(read8_command), &val, 1);
+    return val;
+};
+
+
+static uint8_t write16_command[] = {
+    48,         // 48 bits write
+    0,          // 0 bits read
+    0x02u,      // Write command
+    0, 0, 0,    // Address
+    0, 0        // 16 bits data
+};
+/**
+ * @brief Write 16 bits of data to a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the write is
+ * complete.
+ *
+ * This function is optimized to write 16 bits as quickly as possible to the
+ * PSRAM as opposed to the more general-purpose psram_write() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param val Value to write.
+ */
+__force_inline static void psram_write16(psram_spi_inst_t* spi, uint32_t addr, uint16_t val) {
+    write16_command[3] = addr >> 16;
+    write16_command[4] = addr >> 8;
+    write16_command[5] = addr;
+    write16_command[6] = val;
+    write16_command[7] = val >> 8;
+
+    pio_spi_write_dma_blocking(spi, write16_command, sizeof(write16_command));
+};
+
+
+static uint8_t read16_command[] = {
+    40,         // 40 bits write
+    16,         // 16 bits read
+    0x0bu,      // Fast read command
+    0, 0, 0,    // Address
+    0           // 8 delay cycles
+};
+/**
+ * @brief Read 16 bits of data from a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the read is
+ * complete.
+ *
+ * This function is optimized to read 16 bits as quickly as possible from the
+ * PSRAM as opposed to the more general-purpose psram_read() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to read from.
+ * @return The data at the specified address.
+ */
+__force_inline static uint16_t psram_read16(psram_spi_inst_t* spi, uint32_t addr) {
+    read16_command[3] = addr >> 16;
+    read16_command[4] = addr >> 8;
+    read16_command[5] = addr;
+
+    uint16_t val; 
+    pio_spi_write_read_dma_blocking(spi, read16_command, sizeof(read16_command), (unsigned char*)&val, 2);
+    return val;
+};
+
+
+static uint8_t write32_command[] = {
+    64,         // 64 bits write
+    0,          // 0 bits read
+    0x02u,      // Write command
+    0, 0, 0,    // Address
+    0, 0, 0, 0  // 32 bits data
+};
+/**
+ * @brief Write 32 bits of data to a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the write is
+ * complete.
+ *
+ * This function is optimized to write 32 bits as quickly as possible to the
+ * PSRAM as opposed to the more general-purpose psram_write() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param val Value to write.
+ */
+__force_inline static void psram_write32(psram_spi_inst_t* spi, uint32_t addr, uint32_t val) {
+    // Break the address into three bytes and send read command
+    write32_command[3] = addr >> 16;
+    write32_command[4] = addr >> 8;
+    write32_command[5] = addr;
+    write32_command[6] = val;
+    write32_command[7] = val >> 8;
+    write32_command[8] = val >> 16;
+    write32_command[9] = val >> 24;
+
+    pio_spi_write_dma_blocking(spi, write32_command, sizeof(write32_command));
+};
+
+
+/**
+ * @brief Write 32 bits of data to a given address asynchronously to the PSRAM
+ * SPI PIO, driven by DMA without CPU involvement.
+ *
+ * This function is optimized to write 32 bits as quickly as possible to the
+ * PSRAM as opposed to the more general-purpose psram_write() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param val Value to write.
+ */
+__force_inline static void psram_write32_async(psram_spi_inst_t* spi, uint32_t addr, uint32_t val) {
+    // Break the address into three bytes and send read command
+    write32_command[3] = addr >> 16;
+    write32_command[4] = addr >> 8;
+    write32_command[5] = addr;
+    write32_command[6] = val;
+    write32_command[7] = val >> 8;
+    write32_command[8] = val >> 16;
+    write32_command[9] = val >> 24;
+
+    pio_spi_write_async(spi, write32_command, sizeof(write32_command));
+};
+
+
+static uint8_t read32_command[] = {
+    40,         // 40 bits write
+    32,         // 32 bits read
+    0x0bu,      // Fast read command
+    0, 0, 0,    // Address
+    0           // 8 delay cycles
+};
+/**
+ * @brief Read 32 bits of data from a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the read is
+ * complete.
+ *
+ * This function is optimized to read 32 bits as quickly as possible from the
+ * PSRAM as opposed to the more general-purpose psram_read() function.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to read from.
+ * @return The data at the specified address.
+ */
+__force_inline static uint32_t psram_read32(psram_spi_inst_t* spi, uint32_t addr) {
+    read32_command[3] = addr >> 16;
+    read32_command[4] = addr >> 8;
+    read32_command[5] = addr;
+
+    uint32_t val;
+    pio_spi_write_read_dma_blocking(spi, read32_command, sizeof(read32_command), (unsigned char*)&val, 4);
+    return val;
+};
+
+
+static uint8_t write_command[] = {
+    0,          // n bits write
+    0,          // 0 bits read
+    0x02u,      // Fast write command
+    0, 0, 0     // Address
+};
+/**
+ * @brief Write @c count bytes of data to a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the write is
+ * complete.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param src Pointer to the source data to write.
+ * @param count Number of bytes to write.
+ */
+__force_inline static void psram_writen(psram_spi_inst_t* spi, const uint32_t addr, const uint8_t* src, const size_t count) {
+    // Break the address into three bytes and send read command
+    write_command[0] = (4 + count) * 8;
+    write_command[3] = addr >> 16;
+    write_command[4] = addr >> 8;
+    write_command[5] = addr;
+
+    pio_spi_write_dma_blocking(spi, write_command, sizeof(write_command));
+    pio_spi_write_dma_blocking(spi, src, count);
+};
+
+
+static uint8_t read_command[] = {
+    40,         // 40 bits write
+    0,          // n bits read
+    0x0bu,      // Fast read command
+    0, 0, 0,    // Address
+    0           // 8 delay cycles
+};
+/**
+ * @brief Read @c count bits of data from a given address to the PSRAM SPI PIO,
+ * driven by DMA without CPU involvement, blocking until the read is
+ * complete.
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to read from.
+ * @param dst Pointer to the destination for the read data.
+ * @param count Number of bytes to read.
+ */
+__force_inline static void psram_readn(psram_spi_inst_t* spi, const uint32_t addr, uint8_t* dst, const size_t count) {
+    read_command[1] = count * 8;
+    read_command[3] = addr >> 16;
+    read_command[4] = addr >> 8;
+    read_command[5] = addr;
+
+    pio_spi_write_read_dma_blocking(spi, read_command, sizeof(read_command), dst, count);
+};
+
+
+static uint8_t write_async_fast_command[134] = {
+    0,          // n bits write
+    0,          // 0 bits read
+    0x02u      // Fast write command
+};
+/**
+ * @brief Write @c count bytes of data to a given address asynchronously to the
+ * PSRAM SPI PIO, driven by DMA without CPU involvement. 
+ *
+ * @param spi The PSRAM configuration instance returned from psram_spi_init().
+ * @param addr Address to write to.
+ * @param src Pointer to the source data to write.
+ * @param count Number of bytes to write.
+ */
+__force_inline static void psram_write_async_fast(psram_spi_inst_t* spi, uint32_t addr, uint8_t* val, const size_t count) {
+    write_async_fast_command[0] = (4 + count) * 8;
+    write_async_fast_command[3] = addr >> 16;
+    write_async_fast_command[4] = addr >> 8;
+    write_async_fast_command[5] = addr;
+
+    memcpy(write_async_fast_command + 6, val, count);
+
+    pio_spi_write_async(spi, write_async_fast_command, 6 + count);
+};
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/MCUME_pico2/psram/psram_spi.pio b/MCUME_pico2/psram/psram_spi.pio
new file mode 100755
index 0000000..785356b
--- /dev/null
+++ b/MCUME_pico2/psram/psram_spi.pio
@@ -0,0 +1,136 @@
+; rp2040-psram
+; 
+; Copyright © 2023 Ian Scott
+; 
+; Permission is hereby granted, free of charge, to any person obtaining a copy of
+; this software and associated documentation files (the “Software�), to deal in
+; the Software without restriction, including without limitation the rights to
+; use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+; of the Software, and to permit persons to whom the Software is furnished to do
+; so, subject to the following conditions:
+; 
+; The above copyright notice and this permission notice shall be included in all
+; copies or substantial portions of the Software.
+; 
+; THE SOFTWARE IS PROVIDED “AS IS�, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+; SOFTWARE.
+
+; SPI, customized as the PSRAM chips like to implement it:
+; - Data is always written first, then optionally read
+; Depending on PCB layout, introduce fudge factor:
+; - Reads in high speed mode need an extra clock cycle to synchronize
+; - Reads are done on the falling edge of SCK when > 83MHz
+
+.program spi_psram_fudge
+.side_set 2                        ; sideset bit 1 is SCK, bit 0 is CS
+begin:
+    out x, 8            side 0b01  ; x = number of bits to output. CS deasserted
+    out y, 8            side 0b01  ; y = number of bits to input
+    jmp x--, writeloop  side 0b01  ; Pre-decement x by 1 so loop has correct number of iterations
+writeloop:
+    out pins, 1         side 0b00  ; Write value on pin, lower clock. CS asserted
+    jmp x--, writeloop  side 0b10  ; Raise clock: this is when PSRAM reads the value. Loop if we have more to write
+    jmp !y, begin       side 0b00  ; If this is a write-only operation, jump back to beginning
+    nop                 side 0b10  ; Fudge factor of extra clock cycle; the PSRAM needs 1 extra for output to start appearing
+    jmp readloop_mid    side 0b00  ; Jump to middle of readloop to decrement y and get right clock phase
+readloop:
+    in pins, 1          side 0b00  ; Read value on pin, lower clock. Datasheet says to read on falling edge > 83MHz
+readloop_mid:
+    jmp y--, readloop   side 0b10  ; Raise clock. Loop if we have more to read
+
+.program spi_psram
+.side_set 2                        ; sideset bit 1 is SCK, bit 0 is CS
+begin:
+    out x, 8            side 0b01  ; x = number of bits to output. CS deasserted
+    out y, 8            side 0b01  ; y = number of bits to input
+    jmp x--, writeloop  side 0b01  ; Pre-decement x by 1 so loop has correct number of iterations
+writeloop:
+    out pins, 1         side 0b00  ; Write value on pin, lower clock. CS asserted
+    jmp x--, writeloop  side 0b10  ; Raise clock: this is when PSRAM reads the value. Loop if we have more to write
+    jmp !y, begin       side 0b00  ; If this is a write-only operation, jump back to beginning
+    jmp readloop_mid    side 0b10  ; Jump to middle of readloop to decrement y and get right clock phase
+readloop:
+    in pins, 1          side 0b10  ; Read value on pin, raise clock.
+readloop_mid:
+    jmp y--, readloop   side 0b00  ; Lower clock. Loop if we have more to read
+
+% c-sdk {
+#include "hardware/gpio.h"
+static inline void pio_spi_psram_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, bool fudge, uint pin_cs, uint pin_mosi, uint pin_miso) {
+    pio_sm_config c;
+    if (fudge) {
+        c = spi_psram_fudge_program_get_default_config(prog_offs);
+    } else {
+        c = spi_psram_program_get_default_config(prog_offs);
+    }
+    sm_config_set_out_pins(&c, pin_mosi, 1);
+    sm_config_set_in_pins(&c, pin_miso);
+    sm_config_set_sideset_pins(&c, pin_cs);
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+
+    pio_sm_set_consecutive_pindirs(pio, sm, pin_cs, 2, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin_mosi, 1, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin_miso, 1, false);
+    pio_gpio_init(pio, pin_mosi);
+    pio_gpio_init(pio, pin_cs);
+    pio_gpio_init(pio, pin_cs + 1);
+
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
+
+    pio_sm_init(pio, sm, prog_offs, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program qspi_psram
+.side_set 2
+begin:
+    out x, 8            side 0b01  ; x = number of nibbles to output. CS deasserted
+    out y, 8            side 0b01  ; y = number of nibbles to input
+    jmp x--, writeloop  side 0b01  ; Pre-decement x by 1 so loop has correct number of iterations
+writeloop:
+    out pins, 4         side 0b00  ; Write value on pins, lower clock. CS asserted
+    jmp x--, writeloop  side 0b10  ; Raise clock: this is when PSRAM reads the value. Loop if we have more to write
+    jmp !y, begin       side 0b00  ; If this is a write-only operation, jump back to beginning
+    set pindirs 0       side 0b10  ; Fudge factor of extra clock cycle; the PSRAM needs 1 extra for output to start appearing
+    nop    side 0b00  ; Jump to middle of readloop to decrement y and get right clock phase
+readloop:
+    in pins, 4          side 0b10  ; Read value on s, lower clock. Datasheet says to read on falling edge > 83MHz
+readloop_mid:
+    jmp y--, readloop   side 0b00  ; Raise clock. Loop if we have more to read
+    set pindirs 0xF     side 0b01
+
+% c-sdk {
+#include "hardware/gpio.h"
+static inline void pio_qspi_psram_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, uint pin_cs, uint pin_sio0) {
+    pio_sm_config c = qspi_psram_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_sio0, 4);
+    sm_config_set_in_pins(&c, pin_sio0);
+    sm_config_set_set_pins(&c, pin_sio0, 4);
+    sm_config_set_sideset_pins(&c, pin_cs);
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+
+    pio_sm_set_consecutive_pindirs(pio, sm, pin_cs, 2, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin_sio0, 4, true);
+    pio_gpio_init(pio, pin_sio0);
+    pio_gpio_init(pio, pin_sio0 + 1);
+    pio_gpio_init(pio, pin_sio0 + 2);
+    pio_gpio_init(pio, pin_sio0 + 3);
+    pio_gpio_init(pio, pin_cs);
+    pio_gpio_init(pio, pin_cs + 1);
+
+    hw_set_bits(&pio->input_sync_bypass, 0xfu << pin_sio0);
+
+    pio_sm_init(pio, sm, prog_offs, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/MCUME_pico2/psram/psram_t.cpp b/MCUME_pico2/psram/psram_t.cpp
new file mode 100644
index 0000000..f05c782
--- /dev/null
+++ b/MCUME_pico2/psram/psram_t.cpp
@@ -0,0 +1,192 @@
+/*
+  PSRAM driver for IPS6404
+*/
+
+#include "psram_t.h"
+
+#include <cstdio>
+
+#include <pico/stdlib.h>
+
+#include "psram_spi.h"
+
+Page PSRAM_T::pages[MAX_PAGES];
+uint8_t PSRAM_T::nbPages=0;
+int8_t PSRAM_T::top=0;
+int8_t PSRAM_T::last=0;
+
+
+
+
+#define RAM_READ  0xB
+//#define RAM_READ  0x3
+#define RAM_WRITE 0x2
+
+static psram_spi_inst_t psram_spi;
+
+
+PSRAM_T::PSRAM_T(uint8_t cs, uint8_t mosi, uint8_t sclk, uint8_t miso)
+{
+}
+
+
+void PSRAM_T::begin(void)
+{
+  psram_spi = psram_spi_init(pio2, 0);
+}
+
+
+
+uint8_t PSRAM_T::psram_read(uint32_t addr) 
+{
+  return psram_read8(&psram_spi, addr);
+}
+
+
+void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) 
+{
+  //printf("r %d %d\n", addr, n);
+  psram_readn(&psram_spi, addr, val, n); 
+}
+
+
+void PSRAM_T::psram_write(uint32_t addr, uint8_t val) 
+{
+  psram_write8(&psram_spi, addr, val); 
+}
+
+static uint8_t resp[PAGE_SIZE];
+
+
+void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) 
+{
+  printf("w %d %d\n", addr, n);
+  psram_writen(&psram_spi, addr, val, n);  
+}
+
+
+
+
+
+void PSRAM_T::pswrite(uint32_t addr, uint8_t val) 
+{
+  psram_write(addr, val);
+  //return;
+  uint32_t curPage=addr&(~(PAGE_SIZE-1));
+  for (int i=0; i<nbPages; i++) {
+    if (pages[i].pageid == curPage) {
+      pages[i].page[addr&(PAGE_SIZE-1)] = val;
+      break;
+    }
+  }   
+}
+
+
+
+
+uint8_t PSRAM_T::psread(uint32_t addr) 
+{
+  //uint8_t val = psram_read(addr);
+  //return val;
+  uint32_t curPage=addr&(~(PAGE_SIZE-1));
+  uint32_t offs = addr&(PAGE_SIZE-1);
+
+  for (int i=0; i<nbPages; i++) {
+    if (pages[i].pageid == curPage) {
+      if ( (pages[i].prev != i) && (pages[i].next != i) ) {
+        pages[pages[i].prev].next =  pages[i].next;
+        pages[pages[i].next].prev = pages[i].prev;     
+      }
+      else if (pages[i].next != i) {
+        pages[pages[i].next].prev = i;
+      }
+      else if (pages[i].prev != i) {
+        pages[pages[i].prev].next =  pages[i].prev;
+        last = pages[i].prev;        
+      }
+       // last page accessed to top
+      pages[i].prev = i; //-1;
+      pages[i].next = top;      
+      pages[top].prev = i;
+      top = i;
+      return pages[top].page[offs];
+    }
+  }
+  if (nbPages<MAX_PAGES) 
+  {
+    // add at top
+    pages[nbPages].pageid = curPage;           
+    pages[nbPages].prev = nbPages; //-1;
+    pages[nbPages].next = top;     
+    pages[top].prev = nbPages;
+    top = nbPages;
+    nbPages++;
+  }
+  else {
+      // replace last and move to top
+      int n = pages[last].prev;
+      pages[n].next = n; //-1;
+      pages[last].pageid = curPage;
+      pages[last].prev = last; //-1;
+      pages[last].next = top;      
+      pages[top].prev = last;
+      top = last;
+      last = n;
+  }
+  //emu_printi(curPage);
+  psram_read_n(curPage,&(pages[top].page[0]),PAGE_SIZE);   
+  return pages[top].page[offs];
+}
+
+uint16_t PSRAM_T::psread_w(uint32_t addr) 
+{
+  uint32_t curPage=addr&(~(PAGE_SIZE-1));
+  uint32_t offs = addr&(PAGE_SIZE-1);
+
+  for (int i=0; i<nbPages; i++) {
+    if (pages[i].pageid == curPage) {
+      if ( (pages[i].prev != i) && (pages[i].next != i) ) {
+        pages[pages[i].prev].next =  pages[i].next;
+        pages[pages[i].next].prev = pages[i].prev;     
+      }
+      else if (pages[i].next != i) {
+        pages[pages[i].next].prev = i;
+      }
+      else if (pages[i].prev != i) {
+        pages[pages[i].prev].next =  pages[i].prev;
+        last = pages[i].prev;        
+      }
+       // last page accessed to top
+      pages[i].prev = i; //-1;
+      pages[i].next = top;      
+      pages[top].prev = i;
+      top = i;     
+      return (pages[top].page[offs+1]<<8) + pages[top].page[offs];
+    }
+  }
+  if (nbPages<MAX_PAGES) 
+  {
+    // add at top
+    pages[nbPages].pageid = curPage;           
+    pages[nbPages].prev = nbPages; //-1;
+    pages[nbPages].next = top;     
+    pages[top].prev = nbPages;
+    top = nbPages;
+    nbPages++;
+  }
+  else {
+      // replace last and move to top
+      int n = pages[last].prev;
+      pages[n].next = n; //-1;
+      pages[last].pageid = curPage;
+      pages[last].prev = last; //-1;
+      pages[last].next = top;      
+      pages[top].prev = last;
+      top = last;
+      last = n;
+  }
+  //emu_printi(curPage);
+  psram_read_n(curPage,&(pages[top].page[0]),PAGE_SIZE);   
+  return (pages[top].page[offs+1]<<8) + pages[top].page[offs];
+}
+
diff --git a/MCUME_pico2/psram/psram_t.h b/MCUME_pico2/psram/psram_t.h
new file mode 100644
index 0000000..0971970
--- /dev/null
+++ b/MCUME_pico2/psram/psram_t.h
@@ -0,0 +1,50 @@
+/*
+  PSRAM driver for IPS6404
+*/
+
+#ifndef _PSRAM_T_H_
+#define _PSRAM_T_H_
+
+#ifdef __cplusplus
+
+#include "pico.h"
+#include "pico/stdlib.h"
+
+
+#define PAGE_SIZE    16 //32 //2048 //1024
+#define MAX_PAGES    8
+
+
+struct Page {
+   uint8_t  page[PAGE_SIZE];
+   uint32_t pageid;
+   int8_t next;
+   int8_t prev;
+};
+
+class PSRAM_T
+{
+  public:
+    PSRAM_T(uint8_t _CS, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12);
+    void begin(void);
+    void pswrite(uint32_t addr, uint8_t val);
+    uint8_t psread(uint32_t addr);
+    uint16_t psread_w(uint32_t addr);
+   
+  private:
+    static uint8_t psram_read(uint32_t addr);
+    static void psram_read_n(uint32_t addr, uint8_t * val, int n);
+    static void psram_write(uint32_t addr, uint8_t val);
+    static void psram_write_n(uint32_t addr, uint8_t * val, int n);
+   
+  protected:
+    static uint8_t _cs, _miso, _mosi, _sclk;
+    static Page pages[MAX_PAGES];
+    static uint8_t nbPages;
+    static int8_t top;
+    static int8_t last;
+};
+#endif
+
+#endif
+
diff --git a/MCUME_pico2/psram/readme.txt b/MCUME_pico2/psram/readme.txt
new file mode 100755
index 0000000..26bd585
--- /dev/null
+++ b/MCUME_pico2/psram/readme.txt
@@ -0,0 +1,6 @@
+
+https://github.com/polpo/rp2040-psram
+
+- Adapted for rp2350
+- Configurable via "iopins.h"
+- Add layer psram_t.h with RAM block caching
\ No newline at end of file
diff --git a/MCUME_pico2/readme.txt b/MCUME_pico2/readme.txt
new file mode 100755
index 0000000..78dd207
--- /dev/null
+++ b/MCUME_pico2/readme.txt
@@ -0,0 +1,19 @@
+
+# install PICO-SDK (or update it by pulling)
+Use pico-sdk 2.0 (for RP2350, pico2)
+------------------------------------
+git clone -b master https://github.com/raspberrypi/pico-sdk.git
+cd pico-sdk/
+git submodule update --init
+cd lib/tinyusb
+python3 tools/get_deps.py rp2040
+python3 tools/get_deps.py rp2350
+cd ..
+export PICO_SDK_PATH=/Users/jean-marcharvengt/Documents/pico/pico-sdk-2.1.0 (path to pico-sdk!)
+
+
+mkdir build
+cd build
+pico2/2w: cmake -DPICO_PLATFORM=rp2350 -DPICO_BOARD=pico2 ..
+
+make
diff --git a/MCUME_pico2/sd_driver/.DS_Store b/MCUME_pico2/sd_driver/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/sd_driver/.DS_Store differ
diff --git a/MCUME_pico2/sd_driver/readme.txt b/MCUME_pico2/sd_driver/readme.txt
new file mode 100755
index 0000000..9fb084d
--- /dev/null
+++ b/MCUME_pico2/sd_driver/readme.txt
@@ -0,0 +1,3 @@
+
+ref code ...
+- Configurable via "iopins.h"
diff --git a/MCUME_pico2/sd_driver/tf_card.c b/MCUME_pico2/sd_driver/tf_card.c
new file mode 100644
index 0000000..d1789d7
--- /dev/null
+++ b/MCUME_pico2/sd_driver/tf_card.c
@@ -0,0 +1,612 @@
+#include "tf_card.h"
+
+#include "ff.h"
+#include "diskio.h"
+
+#include "pico/stdlib.h"
+#include "iopins.h"
+
+/*--------------------------------------------------------------------------
+   SPI and Pin selection
+---------------------------------------------------------------------------*/
+static pico_fatfs_spi_config_t _config = {
+    SD_SPIREG,
+    CLK_SLOW_DEFAULT,
+    CLK_FAST_DEFAULT,
+    SD_MISO,
+    SD_CS,
+    SD_SCLK,
+    SD_MOSI,
+    true
+};
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+/* MMC/SD command */
+#define CMD0    (0)         /* GO_IDLE_STATE */
+#define CMD1    (1)         /* SEND_OP_COND (MMC) */
+#define ACMD41  (0x80+41)   /* SEND_OP_COND (SDC) */
+#define CMD8    (8)         /* SEND_IF_COND */
+#define CMD9    (9)         /* SEND_CSD */
+#define CMD10   (10)        /* SEND_CID */
+#define CMD12   (12)        /* STOP_TRANSMISSION */
+#define ACMD13  (0x80+13)   /* SD_STATUS (SDC) */
+#define CMD16   (16)        /* SET_BLOCKLEN */
+#define CMD17   (17)        /* READ_SINGLE_BLOCK */
+#define CMD18   (18)        /* READ_MULTIPLE_BLOCK */
+#define CMD23   (23)        /* SET_BLOCK_COUNT (MMC) */
+#define ACMD23  (0x80+23)   /* SET_WR_BLK_ERASE_COUNT (SDC) */
+#define CMD24   (24)        /* WRITE_BLOCK */
+#define CMD25   (25)        /* WRITE_MULTIPLE_BLOCK */
+#define CMD32   (32)        /* ERASE_ER_BLK_START */
+#define CMD33   (33)        /* ERASE_ER_BLK_END */
+#define CMD38   (38)        /* ERASE */
+#define CMD55   (55)        /* APP_CMD */
+#define CMD58   (58)        /* READ_OCR */
+
+/* MMC card type flags (MMC_GET_TYPE) */
+#define CT_MMC         0x01            /* MMC ver 3 */
+#define CT_SD1         0x02            /* SD ver 1 */
+#define CT_SD2         0x04            /* SD ver 2 */
+#define CT_SDC         (CT_SD1|CT_SD2) /* SD */
+#define CT_BLOCK       0x08            /* Block addressing */
+
+static volatile
+DSTATUS Stat = STA_NOINIT;  /* Physical drive status */
+
+static
+BYTE CardType;          /* Card type flags */
+
+static inline uint32_t _millis(void)
+{
+    return to_ms_since_boot(get_absolute_time());
+}
+
+/*-----------------------------------------------------------------------*/
+/* SPI controls (Platform dependent)                                     */
+/*-----------------------------------------------------------------------*/
+
+static inline void cs_select(uint cs_pin) {
+    asm volatile("nop \n nop \n nop"); // FIXME
+    gpio_put(cs_pin, 0);
+    asm volatile("nop \n nop \n nop"); // FIXME
+}
+
+static inline void cs_deselect(uint cs_pin) {
+    asm volatile("nop \n nop \n nop"); // FIXME
+    gpio_put(cs_pin, 1);
+    asm volatile("nop \n nop \n nop"); // FIXME
+}
+
+static void FCLK_SLOW(void)
+{
+    spi_set_baudrate(_config.spi_inst, _config.clk_slow);
+}
+
+static void FCLK_FAST(void)
+{
+    spi_set_baudrate(_config.spi_inst, _config.clk_fast);
+}
+
+static void CS_HIGH(void)
+{
+    cs_deselect(_config.pin_cs);
+}
+
+static void CS_LOW(void)
+{
+    cs_select(_config.pin_cs);
+}
+
+/* Initialize MMC interface */
+__attribute__((weak))
+void pico_fatfs_init_spi(void)
+{
+    /* GPIO pin configuration */
+    /* pull up of MISO is MUST (10Kohm external pull up is recommended) */
+    /* Set drive strength and slew rate if needed to meet wire condition */
+    gpio_init(_config.pin_sck);
+    if (false) {
+        gpio_pull_up(_config.pin_sck);
+    } else {
+        gpio_disable_pulls(_config.pin_sck);
+    }
+    //gpio_set_drive_strength(_config.pin_sck, PADS_BANK0_GPIO0_DRIVE_VALUE_4MA); // 2mA, 4mA (default), 8mA, 12mA
+    //gpio_set_slew_rate(_config.pin_sck, 0); // 0: SLOW (default), 1: FAST
+    gpio_set_function(_config.pin_sck, GPIO_FUNC_SPI);
+
+    gpio_init(_config.pin_miso);
+    if (_config.pullup) {
+        gpio_pull_up(_config.pin_miso);
+    } else {
+        gpio_disable_pulls(_config.pin_miso);
+    }
+    //gpio_set_schmitt(_config.pin_miso, 1); // 0: Off, 1: On (default)
+    gpio_set_function(_config.pin_miso, GPIO_FUNC_SPI);
+
+    gpio_init(_config.pin_mosi);
+    if (_config.pullup) {
+        gpio_pull_up(_config.pin_mosi);
+    } else {
+        gpio_disable_pulls(_config.pin_mosi);
+    }
+    //gpio_set_drive_strength(_config.pin_mosi, PADS_BANK0_GPIO0_DRIVE_VALUE_4MA); // 2mA, 4mA (default), 8mA, 12mA
+    //gpio_set_slew_rate(_config.pin_mosi, 0); // 0: SLOW (default), 1: FAST
+    gpio_set_function(_config.pin_mosi, GPIO_FUNC_SPI);
+
+    gpio_init(_config.pin_cs);
+    if (false) {
+        gpio_pull_up(_config.pin_cs);
+    } else {
+        gpio_disable_pulls(_config.pin_cs);
+    }
+    //gpio_set_drive_strength(_config.pin_cs, PADS_BANK0_GPIO0_DRIVE_VALUE_4MA); // 2mA, 4mA (default), 8mA, 12mA
+    //gpio_set_slew_rate(_config.pin_cs, 0); // 0: SLOW (default), 1: FAST
+    gpio_set_dir(_config.pin_cs, GPIO_OUT);
+
+    /* chip _select invalid*/
+    CS_HIGH();
+
+    spi_init(_config.spi_inst, _config.clk_slow);
+
+    /* SPI parameter config */
+    spi_set_format(_config.spi_inst,
+        8, /* data_bits */
+        SPI_CPOL_0, /* cpol */
+        SPI_CPHA_0, /* cpha */
+        SPI_MSB_FIRST /* order */
+    );
+}
+
+/* Exchange a byte */
+static
+BYTE xchg_spi (
+    BYTE dat    /* Data to send */
+)
+{
+    uint8_t *buff = (uint8_t *) &dat;
+    spi_write_read_blocking(_config.spi_inst, buff, buff, 1);
+    return (BYTE) *buff;
+}
+
+
+/* Receive multiple byte */
+static
+void rcvr_spi_multi (
+    BYTE *buff,     /* Pointer to data buffer */
+    UINT btr        /* Number of bytes to receive (even number) */
+)
+{
+    uint8_t *b = (uint8_t *) buff;
+    spi_read_blocking(_config.spi_inst, 0xff, b, btr);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* Wait for card ready                                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+int wait_ready (    /* 1:Ready, 0:Timeout */
+    UINT wt         /* Timeout [ms] */
+)
+{
+    BYTE d;
+
+    uint32_t t = _millis();
+    do {
+        d = xchg_spi(0xFF);
+        /* This loop takes a time. Insert rot_rdq() here for multitask envilonment. */
+    } while (d != 0xFF && _millis() < t + wt);  /* Wait for card goes ready or timeout */
+
+    return (d == 0xFF) ? 1 : 0;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Deselect card and release SPI                                         */
+/*-----------------------------------------------------------------------*/
+
+static
+void deselect (void)
+{
+    CS_HIGH();      /* Set CS# high */
+    xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Select card and wait for ready                                        */
+/*-----------------------------------------------------------------------*/
+
+static
+int _select (void)  /* 1:OK, 0:Timeout */
+{
+    CS_LOW();       /* Set CS# low */
+    xchg_spi(0xFF); /* Dummy clock (force DO enabled) */
+    if (wait_ready(500)) return 1;  /* Wait for card ready */
+
+    deselect();
+    return 0;   /* Timeout */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Receive a data packet from the MMC                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+int rcvr_datablock (    /* 1:OK, 0:Error */
+    BYTE *buff,         /* Data buffer */
+    UINT btr            /* Data block length (byte) */
+)
+{
+    BYTE token;
+
+    const uint32_t timeout = 200;
+    uint32_t t = _millis();
+    do {                            /* Wait for DataStart token in timeout of 200ms */
+        token = xchg_spi(0xFF);
+        /* This loop will take a time. Insert rot_rdq() here for multitask envilonment. */
+    } while (token == 0xFF && _millis() < t + timeout);
+    if(token != 0xFE) return 0;     /* Function fails if invalid DataStart token or timeout */
+
+    rcvr_spi_multi(buff, btr);      /* Store trailing data to the buffer */
+    xchg_spi(0xFF); xchg_spi(0xFF);         /* Discard CRC */
+
+    return 1;                       /* Function succeeded */
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* Send a command packet to the MMC                                      */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE send_cmd (     /* Return value: R1 resp (bit7==1:Failed to send) */
+    BYTE cmd,       /* Command index */
+    DWORD arg       /* Argument */
+)
+{
+    BYTE n, res;
+
+
+    if (cmd & 0x80) {   /* Send a CMD55 prior to ACMD<n> */
+        cmd &= 0x7F;
+        res = send_cmd(CMD55, 0);
+        if (res > 1) return res;
+    }
+
+    /* Select the card and wait for ready except to stop multiple block read */
+    if (cmd != CMD12) {
+        deselect();
+        if (!_select()) return 0xFF;
+    }
+
+    /* Send command packet */
+    xchg_spi(0x40 | cmd);               /* Start + command index */
+    xchg_spi((BYTE)(arg >> 24));        /* Argument[31..24] */
+    xchg_spi((BYTE)(arg >> 16));        /* Argument[23..16] */
+    xchg_spi((BYTE)(arg >> 8));         /* Argument[15..8] */
+    xchg_spi((BYTE)arg);                /* Argument[7..0] */
+    n = 0x01;                           /* Dummy CRC + Stop */
+    if (cmd == CMD0) n = 0x95;          /* Valid CRC for CMD0(0) */
+    if (cmd == CMD8) n = 0x87;          /* Valid CRC for CMD8(0x1AA) */
+    xchg_spi(n);
+
+    /* Receive command resp */
+    if (cmd == CMD12) xchg_spi(0xFF);   /* Diacard following one byte when CMD12 */
+    n = 10;                             /* Wait for response (10 bytes max) */
+    do {
+        res = xchg_spi(0xFF);
+    } while ((res & 0x80) && --n);
+
+    return res;                         /* Return received response */
+}
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize disk drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+    BYTE drv        /* Physical drive number (0) */
+)
+{
+    BYTE n, cmd, ty, ocr[4];
+    const uint32_t timeout = 1000; /* Initialization timeout = 1 sec */
+    uint32_t t;
+
+    if (drv) return STA_NOINIT;         /* Supports only drive 0 */
+    pico_fatfs_init_spi();              /* Initialize SPI */
+    sleep_ms(10);
+
+    if (Stat & STA_NODISK) return Stat; /* Is card existing in the soket? */
+
+    FCLK_SLOW();
+    for (n = 10; n; n--) xchg_spi(0xFF);    /* Send 80 dummy clocks */
+
+    ty = 0;
+    if (send_cmd(CMD0, 0) == 1) {           /* Put the card SPI/Idle state */
+        t = _millis();
+        if (send_cmd(CMD8, 0x1AA) == 1) {   /* SDv2? */
+            for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);    /* Get 32 bit return value of R7 resp */
+            if (ocr[2] == 0x01 && ocr[3] == 0xAA) {             /* Is the card supports vcc of 2.7-3.6V? */
+                while (_millis() < t + timeout && send_cmd(ACMD41, 1UL << 30)) ;    /* Wait for end of initialization with ACMD41(HCS) */
+                if (_millis() < t + timeout && send_cmd(CMD58, 0) == 0) {       /* Check CCS bit in the OCR */
+                    for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);
+                    ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2;  /* Card id SDv2 */
+                }
+            }
+        } else {    /* Not SDv2 card */
+            if (send_cmd(ACMD41, 0) <= 1)   {   /* SDv1 or MMC? */
+                ty = CT_SD1; cmd = ACMD41;  /* SDv1 (ACMD41(0)) */
+            } else {
+                ty = CT_MMC; cmd = CMD1;    /* MMCv3 (CMD1(0)) */
+            }
+            while (_millis() < t + timeout && send_cmd(cmd, 0)) ;       /* Wait for end of initialization */
+            if (_millis() >= t + timeout || send_cmd(CMD16, 512) != 0)  /* Set block length: 512 */
+                ty = 0;
+        }
+    }
+    CardType = ty;  /* Card type */
+    deselect();
+
+    if (ty) {           /* OK */
+        FCLK_FAST();            /* Set fast clock */
+  
+        Stat &= ~STA_NOINIT;    /* Clear STA_NOINIT flag */
+    } else {            /* Failed */
+        Stat = STA_NOINIT;
+    }
+
+    return Stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get disk status                                                       */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+    BYTE drv        /* Physical drive number (0) */
+)
+{
+    if (drv) return STA_NOINIT;     /* Supports only drive 0 */
+
+    return Stat;    /* Return disk status */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+    BYTE drv,       /* Physical drive number (0) */
+    BYTE *buff,     /* Pointer to the data buffer to store read data */
+    LBA_t sector,   /* Start sector number (LBA) */
+    UINT count      /* Number of sectors to read (1..128) */
+)
+{
+    if (drv || !count) return RES_PARERR;       /* Check parameter */
+    if (Stat & STA_NOINIT) return RES_NOTRDY;   /* Check if drive is ready */
+
+    if (!(CardType & CT_BLOCK)) sector *= 512;  /* LBA ot BA conversion (byte addressing cards) */
+
+    if (count == 1) {   /* Single sector read */
+        if ((send_cmd(CMD17, sector) == 0)  /* READ_SINGLE_BLOCK */
+            && rcvr_datablock(buff, 512)) {
+            count = 0;
+        }
+    }
+    else {              /* Multiple sector read */
+        if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */
+            do {
+                if (!rcvr_datablock(buff, 512)) break;
+                buff += 512;
+            } while (--count);
+            send_cmd(CMD12, 0);             /* STOP_TRANSMISSION */
+        }
+    }
+    deselect();
+
+    return count ? RES_ERROR : RES_OK;  /* Return result */
+}
+
+
+
+#if !FF_FS_READONLY && !FF_FS_NORTC
+/* get the current time */
+__attribute__((weak))
+DWORD get_fattime (void)
+{
+    return 0;
+}
+#endif
+
+#if FF_FS_READONLY == 0
+/* Transmit multiple byte */
+static
+void xmit_spi_multi (
+    const BYTE *buff,       /* Pointer to data buffer */
+    UINT btx        /* Number of bytes to transmit (even number) */
+)
+{
+    const uint8_t *b = (const uint8_t *) buff;
+    spi_write_blocking(_config.spi_inst, b, btx);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Transmit a data packet to the MMC                                     */
+/*-----------------------------------------------------------------------*/
+
+static
+int xmit_datablock (    /* 1:OK, 0:Error */
+    const BYTE *buff, /* 512 byte data block to be transmitted */
+    BYTE token /* Data/Stop token */
+)
+{
+    BYTE resp;
+    if (!wait_ready(500)) return 0;
+    xchg_spi(token); /* Xmit data token */
+    if (token != 0xFD) { /* Is data token */
+        xmit_spi_multi(buff, 512); /* Xmit the data block to the MMC */
+        xchg_spi(0xFF); /* CRC (Dummy) */
+        xchg_spi(0xFF);
+        resp = xchg_spi(0xFF); /* Reveive data response */
+        if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
+            return 0;
+    }
+    return 1;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Write sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_write (
+    BYTE drv,           /* Physical drive number (0) */
+    const BYTE *buff,   /* Ponter to the data to write */
+    LBA_t sector,       /* Start sector number (LBA) */
+    UINT count          /* Number of sectors to write (1..128) */
+)
+{
+    if (drv || !count) return RES_PARERR;       /* Check parameter */
+    if (Stat & STA_NOINIT) return RES_NOTRDY;   /* Check drive status */
+    if (Stat & STA_PROTECT) return RES_WRPRT;   /* Check write protect */
+
+    if (!(CardType & CT_BLOCK)) sector *= 512;  /* LBA ==> BA conversion (byte addressing cards) */
+
+    if (!_select()) return RES_NOTRDY;
+
+    if (count == 1) {   /* Single sector write */
+        if ((send_cmd(CMD24, sector) == 0)  /* WRITE_BLOCK */
+            && xmit_datablock(buff, 0xFE)) {
+            count = 0;
+        }
+    }
+    else {              /* Multiple sector write */
+        if (CardType & CT_SDC) send_cmd(ACMD23, count); /* Predefine number of sectors */
+        if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */
+            do {
+                if (!xmit_datablock(buff, 0xFC)) break;
+                buff += 512;
+            } while (--count);
+            if (!xmit_datablock(0, 0xFD)) count = 1;    /* STOP_TRAN token */
+        }
+    }
+    deselect();
+
+    return count ? RES_ERROR : RES_OK;  /* Return result */
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous drive controls other than data read/write               */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_ioctl (
+    BYTE drv,       /* Physical drive number (0) */
+    BYTE cmd,       /* Control command code */
+    void *buff      /* Pointer to the conrtol data */
+)
+{
+    DRESULT res;
+    BYTE n, csd[16];
+    DWORD *dp, st, ed, csize;
+
+
+    if (drv) return RES_PARERR;                 /* Check parameter */
+    if (Stat & STA_NOINIT) return RES_NOTRDY;   /* Check if drive is ready */
+
+    res = RES_ERROR;
+
+    switch (cmd) {
+    case CTRL_SYNC :        /* Wait for end of internal write process of the drive */
+        if (_select()) res = RES_OK;
+        break;
+
+    case GET_SECTOR_COUNT : /* Get drive capacity in unit of sector (DWORD) */
+        if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
+            if ((csd[0] >> 6) == 1) {   /* SDC ver 2.00 */
+                csize = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1;
+                *(DWORD*)buff = csize << 10;
+            } else {                    /* SDC ver 1.XX or MMC ver 3 */
+                n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
+                csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1;
+                *(DWORD*)buff = csize << (n - 9);
+            }
+            res = RES_OK;
+        }
+        break;
+
+    case GET_BLOCK_SIZE :   /* Get erase block size in unit of sector (DWORD) */
+        if (CardType & CT_SD2) {    /* SDC ver 2.00 */
+            if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */
+                xchg_spi(0xFF);
+                if (rcvr_datablock(csd, 16)) {              /* Read partial block */
+                    for (n = 64 - 16; n; n--) xchg_spi(0xFF);   /* Purge trailing data */
+                    *(DWORD*)buff = 16UL << (csd[10] >> 4);
+                    res = RES_OK;
+                }
+            }
+        } else {                    /* SDC ver 1.XX or MMC */
+            if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {  /* Read CSD */
+                if (CardType & CT_SD1) {    /* SDC ver 1.XX */
+                    *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1);
+                } else {                    /* MMC */
+                    *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1);
+                }
+                res = RES_OK;
+            }
+        }
+        break;
+
+    case CTRL_TRIM :    /* Erase a block of sectors (used when _USE_ERASE == 1) */
+        if (!(CardType & CT_SDC)) break;                /* Check if the card is SDC */
+        if (disk_ioctl(drv, MMC_GET_CSD, csd)) break;   /* Get CSD */
+        if (!(csd[0] >> 6) && !(csd[10] & 0x40)) break; /* Check if sector erase can be applied to the card */
+        dp = buff; st = dp[0]; ed = dp[1];              /* Load sector block */
+        if (!(CardType & CT_BLOCK)) {
+            st *= 512; ed *= 512;
+        }
+        if (send_cmd(CMD32, st) == 0 && send_cmd(CMD33, ed) == 0 && send_cmd(CMD38, 0) == 0 && wait_ready(30000)) { /* Erase sector block */
+            res = RES_OK;   /* FatFs does not check result of this command */
+        }
+        break;
+
+    default:
+        res = RES_PARERR;
+    }
+
+    deselect();
+
+    return res;
+}
+
+void pico_fatfs_set_config(pico_fatfs_spi_config_t *config)
+{
+    _config = *config;
+}
+
+int pico_fatfs_reboot_spi(void)
+{
+    return _select();
+}
diff --git a/MCUME_pico2/sd_driver/tf_card.h b/MCUME_pico2/sd_driver/tf_card.h
new file mode 100644
index 0000000..acbb081
--- /dev/null
+++ b/MCUME_pico2/sd_driver/tf_card.h
@@ -0,0 +1,47 @@
+#pragma once
+
+#include "hardware/spi.h"
+#include "hardware/clocks.h"
+
+#define CLK_SLOW_DEFAULT    (100 * KHZ)
+#define CLK_FAST_DEFAULT    (50 * MHZ)
+// CLK_FAST: actually set to clk_peri (= 125.0 MHz) / N,
+// which is determined by spi_set_baudrate() in pico-sdk/src/rp2_common/hardware_spi/spi.c
+
+/* SPI pin assignment */
+#define PIN_SPI0_MISO_DEFAULT   4   // 0, 4, 16
+#define PIN_SPI0_CS_DEFAULT     5   // 1, 5, 17
+#define PIN_SPI0_SCK_DEFAULT    6   // 2, 6, 18
+#define PIN_SPI0_MOSI_DEFAULT   7   // 3, 7, 19
+
+#define PIN_SPI1_MISO_DEFAULT   8   //  8, 12
+#define PIN_SPI1_CS_DEFAULT     9   //  9, 13
+#define PIN_SPI1_SCK_DEFAULT    10  // 10, 14
+#define PIN_SPI1_MOSI_DEFAULT   11  // 11, 15
+
+typedef struct _pico_fatfs_spi_config_t {
+    spi_inst_t  *spi_inst;  // spi0 or spi1
+    uint        clk_slow;
+    uint        clk_fast;
+    uint        pin_miso;
+    uint        pin_cs;
+    uint        pin_sck;
+    uint        pin_mosi;
+    bool        pullup;     // miso, mosi pins only
+} pico_fatfs_spi_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+* Set configuration
+*
+* @param[in] config the pointer of pico_fatfs_spi_config_t to configure with
+*/
+void pico_fatfs_set_config(pico_fatfs_spi_config_t *config);
+int pico_fatfs_reboot_spi(void);
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/MCUME_pico2/testkeymax/emucfg.h b/MCUME_pico2/testkeymax/emucfg.h
new file mode 100644
index 0000000..1a70f5e
--- /dev/null
+++ b/MCUME_pico2/testkeymax/emucfg.h
@@ -0,0 +1,86 @@
+#ifndef EMUCFG_H
+#define EMUCFG_H
+
+#define CUSTOM_SND  1
+//#define TIMER_REND  1
+#define EXTRA_HEAP  0x10
+//#define FILEBROWSER
+
+// Title:     <                        >
+#define TITLE "    keymaptest "
+#define ROMSDIR ""
+
+#ifdef KEYMAP_PRESENT
+   
+#ifdef PICOZX
+const unsigned short key_map1[] = {
+  '1','2','3','4','5','6','7','8','9','0',
+  'Q','W','E','R','T','Y','U','I','O','P',
+  'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M',0,' ',
+  145,157,29,17,157,29 //U L R D L R
+  };  
+
+const unsigned short key_map2[] = {
+  '!','@','#','$','%','&','\'','(',')','_',
+  0,0,0,'<','>',0,0,0,';','"',
+  0,0,0,0,0,'^','-','+','=',0x0D,
+  0,':',0,'?','\/','*',',','.',0,' ',
+  0,0,0,0,0,0
+  };  
+
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0, // function keys
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0,0,0,0,0,
+  0,0,0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x104,0x101,0x108,0x102,0x110,0x120,0x140,0x204,0x201,0x208, // row 1
+  0x202,0x210,0x220,0x240,0x304,0x301,0x308,0x302,0x310,0x320, // row 2
+  0x340,0x404,0x401,0x408,0x402,0x410,0x420,0x440,0x504,0x501, // row 3
+  0x020,0x508,0x502,0x510,0x520,0x540,0x604,0x601,0x040,0x608, // row 4
+  0x008,0x001,0x002,0x010,0x620,0x640 }; // cursor keys up, left, right, down, <<<, >>>
+
+#else   
+#define keylables_map1_0 (char *)"qwertyuiop\x1a"
+#define keylables_map1_1 (char *)" asdfghjkl\x19"
+#define keylables_map1_2 (char *)" zxcvbnm.\x10 "
+const unsigned short key_map1[] = {
+  'Q','W','E','R','T','Y','U','I','O','P',157,
+  0,'A','S','D','F','G','H','J','K','L',0x0D,
+  0,'Z','X','C','V','B','N','M','.',' ',
+  145,157,29,17 //U L R D
+  };  
+
+#define keylables_map2_0 (char *)"1234567890 "
+#define keylables_map2_1 (char *)" !@#$%+&*- "
+#define keylables_map2_2 (char *)" ()?/\"<>,: "
+const unsigned short key_map2[] = {
+  '1','2','3','4','5','6','7','8','9','0',0,
+  0, '!','@','#','$','%','+','&','*','-','\/',
+  0, '(',')','?','\/','"','<','>',',',':',
+  0,0,0,0
+  };  
+
+#define keylables_map3_0 (char *)"\x11\x12\x13\x14\x15\x16\x17\x18   "
+#define keylables_map3_1 (char *)"           "
+#define keylables_map3_2 (char *)"        ;= "
+const unsigned short key_map3[] = {
+  133,134,135,136,137,138,139,140,0,0,0, // function keys
+  0, 0,0,0,0,0,0,0,0,0,0,
+  0, 0,0,0,0,0,0,0,';','=',
+  0,0,0,0
+  };
+
+const unsigned short matkeys[] = {
+  0x020,0x120,0x220,0x320,0x420,0x408,0x308,0x208,0x108,0x008,0x002, // row 1
+  0x510,0x010,0x110,0x210,0x310,0x410,0x401,0x301,0x201,0x101,0x001, // row 2
+  0x520,0x102,0x202,0x302,0x402,0x404,0x304,0x204,0x104,0x004, // row 3
+  0x508,0x501,0x502,0x504 }; // cursor keys
+#endif 
+#endif
+
+#endif
diff --git a/MCUME_pico2/testkeymax/keyboard_osd.h b/MCUME_pico2/testkeymax/keyboard_osd.h
new file mode 100644
index 0000000..062eb4e
--- /dev/null
+++ b/MCUME_pico2/testkeymax/keyboard_osd.h
@@ -0,0 +1,20 @@
+
+#ifndef keyboard_osd_h_
+#define keyboard_osd_h_
+    
+extern bool virtualkeyboardIsActive(void);
+extern void drawVirtualkeyboard(void);
+extern void toggleVirtualkeyboard(bool keepOn);
+extern void handleVirtualkeyboard(void);
+
+extern bool callibrationActive(void);
+extern int  handleCallibration(uint16_t bClick);
+
+extern bool menuActive(void);
+extern char * menuSelection(void);
+extern void toggleMenu(bool on);
+extern int  handleMenu(uint16_t bClick);
+
+
+#endif
+
diff --git a/MCUME_pico2/testkeymax/program_config.h b/MCUME_pico2/testkeymax/program_config.h
new file mode 100644
index 0000000..fd6c5fd
--- /dev/null
+++ b/MCUME_pico2/testkeymax/program_config.h
@@ -0,0 +1,4 @@
+#ifndef _PROGRAM_CONFIG_H_
+#define _PROGRAM_CONFIG_H_
+
+#endif
diff --git a/MCUME_pico2/testkeymax/testkeymax.cpp b/MCUME_pico2/testkeymax/testkeymax.cpp
new file mode 100644
index 0000000..b7b7040
--- /dev/null
+++ b/MCUME_pico2/testkeymax/testkeymax.cpp
@@ -0,0 +1,198 @@
+#include "pico.h"
+#include "pico/stdlib.h"
+#include <stdio.h>
+extern "C" {
+  #include "iopins.h"  
+  #include "emuapi.h"  
+}
+#include "keyboard_osd.h"
+#include "pico_dsp.h"
+
+#define BLUE       RGBVAL16(0, 0, 170)
+#define LIGHT_BLUE RGBVAL16(0, 136, 255)
+
+PICO_DSP tft;
+static int fb_width, fb_height;
+
+
+#include "hardware/clocks.h"
+#include "hardware/vreg.h"
+
+static const char * digits = "0123456789ABCDEF";
+static int hk = 0;
+static int prevhk = 0;
+static int col=0;
+static int row=0;
+
+
+void emu_Input(uint16_t bClick) {
+    hk = emu_ReadI2CKeyboard();
+}
+
+bool repeating_timer_callback(struct repeating_timer *t) {
+    uint16_t bClick = emu_DebounceLocalKeys();
+    emu_Input(bClick);    
+    return true;
+}
+
+//extern "C" int sd_init_driver(void);
+//#include <ff.h>
+//#include <diskio.h>
+//#include "tf_card.h"
+
+int main(void) {
+//    vreg_set_voltage(VREG_VOLTAGE_1_05);
+//    set_sys_clock_khz(125000, true);    
+//    set_sys_clock_khz(150000, true);    
+//    set_sys_clock_khz(133000, true);    
+//    set_sys_clock_khz(200000, true);    
+//    set_sys_clock_khz(210000, true);    
+////    set_sys_clock_khz(230000, true);    
+//    set_sys_clock_khz(225000, true);    
+//    set_sys_clock_khz(250000, true);  
+
+    set_sys_clock_khz(120000, true);
+
+//    set_sys_clock_khz(240000, true);
+//    *((uint32_t *)(0x40010000+0x58)) = 2 << 16; //CLK_HSTX_DIV = 2 << 16; // HSTX clock/2
+
+
+ /*
+    pico_fatfs_spi_config_t config = {
+        spi0,
+        CLK_SLOW_DEFAULT,
+        CLK_FAST_DEFAULT,
+        SD_MISO,
+        SD_CS,
+        SD_SCLK,
+        SD_MOSI,
+        true  // use internal pullup
+    };
+    pico_fatfs_set_config(&config);
+*/
+/*
+    stdio_init_all();
+    FATFS fatfs;
+    FRESULT fr;
+    for (int i = 0; i < 5; i++) {
+        fr = f_mount(&fatfs, "", 1);
+        if (fr == FR_OK) { break; }
+        printf("mount error %d -> retry %d\n", fr, i);
+        pico_fatfs_reboot_spi();
+    }
+*/
+    emu_init();
+
+#ifdef FILEBROWSER
+    while (true) {    
+        if (menuActive()) {
+            uint16_t bClick = emu_DebounceLocalKeys();
+            int action = handleMenu(bClick);
+            char * filename = menuSelection();   
+            if (action == ACTION_RUN) {
+              break;  
+            }  
+            tft.waitSync();
+        }
+    }    
+#endif
+    emu_start();
+	tft.startRefresh();
+    struct repeating_timer timer;
+    add_repeating_timer_ms(20, repeating_timer_callback, NULL, &timer);      
+
+	tft.fillScreen(LIGHT_BLUE);
+	tft.get_frame_buffer_size(&fb_width, &fb_height);
+	tft.drawRect((fb_width-320)/2,(fb_height-200)/2, 320,200, BLUE);
+
+    char buf[4] = {32,32,32,0};
+	uint sys_clk = clock_get_hz(clk_sys)/1000000;
+	uint r1 = sys_clk/100;
+	uint r = sys_clk - r1*100;
+	uint r2 = r/10;
+	r = sys_clk - r1*100 - r2*10;
+	uint r3 = r;
+	buf[0] = digits[r1];
+	buf[1] = digits[r2];
+	buf[2] = digits[r3];
+	tft.drawText(8,8,buf,BLUE,LIGHT_BLUE,false);
+
+    while (true) {
+        uint16_t bClick = emu_GetPad();
+        char buf[5] = {0,0,0,0,0};
+        buf[0] = digits[(bClick>>12)&0xf];
+        buf[1] = digits[(bClick>>8)&0xf];
+        buf[2] = digits[(bClick>>4)&0xf];
+        buf[3] = digits[bClick&0xf];
+        tft.drawText(4*8,0,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),false);
+        buf[3] = 0;
+        int key = emu_ReadI2CKeyboard();
+        buf[0] = digits[(key>>8)&0xf];
+        buf[1] = digits[(key>>4)&0xf];
+        buf[2] = digits[key&0xf];        
+        tft.drawText(4*8,8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),false);
+
+        buf[2] = 0;
+        key = emu_ReadI2CKeyboard2(0);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+0*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+        key = emu_ReadI2CKeyboard2(1);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+1*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+        key = emu_ReadI2CKeyboard2(2);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+2*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+        key = emu_ReadI2CKeyboard2(3);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+3*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+        key = emu_ReadI2CKeyboard2(4);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+4*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+        key = emu_ReadI2CKeyboard2(5);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+5*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+#ifdef PICOZX        
+        key = emu_ReadI2CKeyboard2(6);
+        buf[0] = digits[(key>>4)&0xf];
+        buf[1] = digits[key&0xf];
+        tft.drawText(9*8+6*24,0*8,buf,RGBVAL16(0x00,0x00,0x00),RGBVAL16(0xFF,0xFF,0xFF),true);
+#endif
+        if ( (hk != 0) && (hk < 128) ) {
+            buf[0] = (char)(hk&0xff);  
+            buf[1] = 0;
+            tft.drawText(col*8,(row+3)*8,buf,LIGHT_BLUE,BLUE,false);
+            col += 1;
+            if (col >= 40) {
+                col=0;
+                row += 1;
+                if (row >= 25) {
+                    row=0;  
+                }
+            }
+            if (hk != prevhk) {
+                sleep_ms(200);
+            }
+            else {
+                sleep_ms(100);
+            }
+        }
+        prevhk = hk;
+        sleep_ms(20);
+    }
+}
+
+void emu_KeyboardOnDown(int keymodifer, int key) {
+}
+
+void emu_KeyboardOnUp(int keymodifer, int key) {
+}
+
+
+
+
diff --git a/MCUME_pico2/tusb_config.h b/MCUME_pico2/tusb_config.h
new file mode 100644
index 0000000..1994786
--- /dev/null
+++ b/MCUME_pico2/tusb_config.h
@@ -0,0 +1,134 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+//#ifndef TUD_OPT_HIGH_SPEED
+//#define TUD_OPT_HIGH_SPEED    1
+//#endif
+#define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// change to 0 if using on-board native micro USB
+// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   1
+//#define CFG_TUH_RPI_PIO_USB   0
+#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 0
+#define CFG_TUH_CDC                 0
+#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 0
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+
+//------------- HID -------------//
+
+#define CFG_TUH_HID_EP_BUFSIZE      64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/MCUME_pico2/usb_kbd/.DS_Store b/MCUME_pico2/usb_kbd/.DS_Store
new file mode 100644
index 0000000..5008ddf
Binary files /dev/null and b/MCUME_pico2/usb_kbd/.DS_Store differ
diff --git a/MCUME_pico2/usb_kbd/hid_app.c b/MCUME_pico2/usb_kbd/hid_app.c
new file mode 100644
index 0000000..2f47f7e
--- /dev/null
+++ b/MCUME_pico2/usb_kbd/hid_app.c
@@ -0,0 +1,457 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "kbd.h"
+#include "platform_config.h"
+
+/* ==================  Keycode translation table. ==================== */
+
+/*
+ * We only need one translation table, as this simple application only
+ * supports 102-key US layouts. We need separate translations for
+ * non-shifted and shifted keys because shift is not just a modifier:
+ * shift turns a '5' to a '$', for example. We don't need a separate
+ * column for 'ctrl', because we can handle that simply by logical
+ * AND operations on the keycode. Alt/Meta does not affect the keycode
+ * at all -- it's just a flag. 
+ */ 
+
+// TODO: fill in the rest of the non-ASCII key codes
+// There's a nice list here:
+// https://gist.github.com/ekaitz-zarraga/2b25b94b711684ba4e969e5a5723969b
+static int conv_table_uk[128][2] = 
+{
+    {0     , 0      }, /* 0x00 */ \
+    {0     , 0      }, /* 0x01 */ \
+    {0     , 0      }, /* 0x02 */ \
+    {0     , 0      }, /* 0x03 */ \
+    {'a'   , 'A'    }, /* 0x04 */ \
+    {'b'   , 'B'    }, /* 0x05 */ \
+    {'c'   , 'C'    }, /* 0x06 */ \
+    {'d'   , 'D'    }, /* 0x07 */ \
+    {'e'   , 'E'    }, /* 0x08 */ \
+    {'f'   , 'F'    }, /* 0x09 */ \
+    {'g'   , 'G'    }, /* 0x0a */ \
+    {'h'   , 'H'    }, /* 0x0b */ \
+    {'i'   , 'I'    }, /* 0x0c */ \
+    {'j'   , 'J'    }, /* 0x0d */ \
+    {'k'   , 'K'    }, /* 0x0e */ \
+    {'l'   , 'L'    }, /* 0x0f */ \
+    {'m'   , 'M'    }, /* 0x10 */ \
+    {'n'   , 'N'    }, /* 0x11 */ \
+    {'o'   , 'O'    }, /* 0x12 */ \
+    {'p'   , 'P'    }, /* 0x13 */ \
+    {'q'   , 'Q'    }, /* 0x14 */ \
+    {'r'   , 'R'    }, /* 0x15 */ \
+    {'s'   , 'S'    }, /* 0x16 */ \
+    {'t'   , 'T'    }, /* 0x17 */ \
+    {'u'   , 'U'    }, /* 0x18 */ \
+    {'v'   , 'V'    }, /* 0x19 */ \
+    {'w'   , 'W'    }, /* 0x1a */ \
+    {'x'   , 'X'    }, /* 0x1b */ \
+    {'y'   , 'Y'    }, /* 0x1c */ \
+    {'z'   , 'Z'    }, /* 0x1d */ \
+    {'1'   , '!'    }, /* 0x1e */ \
+    {'2'   , '@'    }, /* 0x1f */ \
+    {'3'   , '#'    }, /* 0x20 */ \
+    {'4'   , '$'    }, /* 0x21 */ \
+    {'5'   , '%'    }, /* 0x22 */ \
+    {'6'   , '^'    }, /* 0x23 */ \
+    {'7'   , '&'    }, /* 0x24 */ \
+    {'8'   , '*'    }, /* 0x25 */ \
+    {'9'   , '('    }, /* 0x26 */ \
+    {'0'   , ')'    }, /* 0x27 */ \
+    {KBD_KEY_ENTER  , KBD_KEY_ENTER   }, /* 0x28 */ \
+    {KBD_KEY_ESC,  KBD_KEY_ESC }, /* 0x29 */ \
+    {KBD_KEY_BS  , KBD_KEY_BS }, /* 0x2a */ \
+    {'\t'  , '\t'   }, /* 0x2b */ \
+    {' '   , ' '    }, /* 0x2c */ \
+    {'-'   , '_'    }, /* 0x2d */ \
+    {'='   , '+'    }, /* 0x2e */ \
+    {'['   , '{'    }, /* 0x2f */ \
+    {']'   , '}'    }, /* 0x30 */ \
+    {'\\'  , '|'    }, /* 0x31 */ \
+    {'#'   , '~'    }, /* 0x32 */ \
+    {';'   , ':'    }, /* 0x33 */ \
+    {'\''  , '\"'   }, /* 0x34 */ \
+    {'`'   , '~'    }, /* 0x35 */ \
+    {','   , '<'    }, /* 0x36 */ \
+    {'.'   , '>'    }, /* 0x37 */ \
+    {'/'   , '?'    }, /* 0x38 */ \
+    {KBD_KEY_CAPS , KBD_KEY_CAPS      }, /* 0x39 */ \
+    {KBD_KEY_F1 , KBD_KEY_F1}, /* 0x3a */ \
+    {KBD_KEY_F2 , KBD_KEY_F2}, /* 0x3b */ \
+    {KBD_KEY_F3 , KBD_KEY_F3}, /* 0x3c */ \
+    {KBD_KEY_F4 , KBD_KEY_F4}, /* 0x3d */ \
+    {KBD_KEY_F5 , KBD_KEY_F5}, /* 0x3e */ \
+    {KBD_KEY_F6 , KBD_KEY_F6}, /* 0x3f */ \
+    {KBD_KEY_F7 , KBD_KEY_F7}, /* 0x40 */ \
+    {KBD_KEY_F8 , KBD_KEY_F8}, /* 0x41 */ \
+    {0     , 0      }, /* 0x42 */ \
+    {0     , 0      }, /* 0x43 */ \
+    {0     , 0      }, /* 0x44 */ \
+    {0     , 0      }, /* 0x45 */ \
+    {0     , 0      }, /* 0x46 */ \
+    {0     , 0      }, /* 0x47 */ \
+    {0     , 0      }, /* 0x48 */ \
+    {0     , 0      }, /* 0x49 */ \
+    {KBD_KEY_HOME , KBD_KEY_HOME}, /* 0x4a */ \
+    {KBD_KEY_PGUP , KBD_KEY_PGUP}, /* 0x4b */ \
+    {0     , 0      }, /* 0x4c */ \
+    {KBD_KEY_END, KBD_KEY_END}, /* 0x4d */ \
+    {KBD_KEY_PGDN , KBD_KEY_PGDN }, /* 0x4e */ \
+    {KBD_KEY_RIGHT, KBD_KEY_RIGHT }, /* 0x4f */ \
+    {KBD_KEY_LEFT, KBD_KEY_LEFT }, /* 0x50 */ \
+    {KBD_KEY_DOWN, KBD_KEY_DOWN }, /* 0x51 */ \
+    {KBD_KEY_UP, KBD_KEY_UP }, /* 0x52 */ \
+    { 0   , 0       }, /* 0x53 */ \
+                                  \
+    { 0   , 0       }, /* 0x54 */ \
+    { 0   , 0       }, /* 0x55 */ \
+    { 0   , 0       }, /* 0x56 */ \
+    { 0   , 0       }, /* 0x57 */ \
+    { 0   , 0       }, /* 0x58 */ \
+    { 0   , 0       }, /* 0x59 */ \
+    { 0   , 0       }, /* 0x5a */ \
+    { 0   , 0       }, /* 0x5b */ \
+    { 0   , 0       }, /* 0x5c */ \
+    { 0   , 0       }, /* 0x5d */ \
+    { 0   , 0       }, /* 0x5e */ \
+    { 0   , 0       }, /* 0x5f */ \
+    { 0   , 0       }, /* 0x60 */ \
+    { 0   , 0       }, /* 0x61 */ \
+    { 0   , 0       }, /* 0x62 */ \
+    { 0   , 0       }, /* 0x63 */ \
+    { 0   , 0       }, /* 0x64 */ \
+    { 0   , 0       }, /* 0x65 */ \
+    { 0   , 0       }, /* 0x66 */ \
+    { 0   , 0       }, /* 0x67 */ \
+};
+
+
+
+static int conv_table_be[128][2] = 
+{
+    {0     , 0      }, /* 0x00 */ \
+    {0     , 0      }, /* 0x01 */ \
+    {0     , 0      }, /* 0x02 */ \
+    {0     , 0      }, /* 0x03 */ \
+    {'q'   , 'Q'    }, /* 0x04 */ \
+    {'b'   , 'B'    }, /* 0x05 */ \
+    {'c'   , 'C'    }, /* 0x06 */ \
+    {'d'   , 'D'    }, /* 0x07 */ \
+    {'e'   , 'E'    }, /* 0x08 */ \
+    {'f'   , 'F'    }, /* 0x09 */ \
+    {'g'   , 'G'    }, /* 0x0a */ \
+    {'h'   , 'H'    }, /* 0x0b */ \
+    {'i'   , 'I'    }, /* 0x0c */ \
+    {'j'   , 'J'    }, /* 0x0d */ \
+    {'k'   , 'K'    }, /* 0x0e */ \
+    {'l'   , 'L'    }, /* 0x0f */ \
+    {','   , '?'    }, /* 0x10 */ \
+    {'n'   , 'N'    }, /* 0x11 */ \
+    {'o'   , 'O'    }, /* 0x12 */ \
+    {'p'   , 'P'    }, /* 0x13 */ \
+    {'a'   , 'A'    }, /* 0x14 */ \
+    {'r'   , 'R'    }, /* 0x15 */ \
+    {'s'   , 'S'    }, /* 0x16 */ \
+    {'t'   , 'T'    }, /* 0x17 */ \
+    {'u'   , 'U'    }, /* 0x18 */ \
+    {'v'   , 'V'    }, /* 0x19 */ \
+    {'z'   , 'Z'    }, /* 0x1a */ \
+    {'x'   , 'X'    }, /* 0x1b */ \
+    {'y'   , 'Y'    }, /* 0x1c */ \
+    {'w'   , 'W'    }, /* 0x1d */ \
+    {'1'   , '&'    }, /* 0x1e */ \
+    {'2'   , '@'    }, /* 0x1f */ \
+    {'3'   , '\"'   }, /* 0x20 */ \
+    {'4'   , '\''   }, /* 0x21 */ \
+    {'5'   , '('    }, /* 0x22 */ \
+    {'6'   , '#'      }, /* 0x23 */ \
+    {'7'   , '*'      }, /* 0x24 */ \
+    {'8'   , '!'    }, /* 0x25 */ \
+    {'9'   , '{'    }, /* 0x26 */ \
+    {'0'   , '}'    }, /* 0x27 */ \
+    {KBD_KEY_ENTER  , KBD_KEY_ENTER   }, /* 0x28 */ \
+    {KBD_KEY_ESC,  KBD_KEY_ESC }, /* 0x29 ESC*/ \
+    {KBD_KEY_BS  , KBD_KEY_BS }, /* 0x2a */ \
+    {'\t'  , '\t'   }, /* 0x2b */ \
+    {' '   , ' '    }, /* 0x2c */ \
+    {')'   , 0      }, /* 0x2d */ \
+    {'-'   , '_'    }, /* 0x2e */ \
+    {'^'   , '['    }, /* 0x2f */ \
+    {'$'   , ']'    }, /* 0x30 */ \
+    {0     , 0      }, /* 0x31 */ \
+    {0     , 0      }, /* 0x32 */ \
+    {'m'   , 'M'    }, /* 0x33 */ \
+    {0     , '%'    }, /* 0x34 */ \
+    {0     , 0      }, /*{'`'   , '~'    },*/ /* 0x35 */ \
+    {';'   , '.'    }, /* 0x36 */ \
+    {':'   , '/'    }, /* 0x37 */ \
+    {'='   , '+'    }, /* 0x38 */ \
+    {KBD_KEY_CAPS , KBD_KEY_CAPS      }, /* 0x39 */ \
+    {KBD_KEY_F1 , KBD_KEY_F1}, /* 0x3a */ \
+    {KBD_KEY_F2 , KBD_KEY_F2}, /* 0x3b */ \
+    {KBD_KEY_F3 , KBD_KEY_F3}, /* 0x3c */ \
+    {KBD_KEY_F4 , KBD_KEY_F4}, /* 0x3d */ \
+    {KBD_KEY_F5 , KBD_KEY_F5}, /* 0x3e */ \
+    {KBD_KEY_F6 , KBD_KEY_F6}, /* 0x3f */ \
+    {KBD_KEY_F7 , KBD_KEY_F7}, /* 0x40 */ \
+    {KBD_KEY_F8 , KBD_KEY_F8}, /* 0x41 */ \
+    {0     , 0      }, /* 0x42 */ \
+    {0     , 0      }, /* 0x43 */ \
+    {0     , 0      }, /* 0x44 */ \
+    {0     , 0      }, /* 0x45 */ \
+    {0     , 0      }, /* 0x46 */ \
+    {0     , 0      }, /* 0x47 */ \
+    {0     , 0      }, /* 0x48 */ \
+    {0     , 0      }, /* 0x49 */ \
+    {KBD_KEY_HOME , KBD_KEY_HOME}, /* 0x4a */ \
+    {KBD_KEY_PGUP , KBD_KEY_PGUP}, /* 0x4b */ \
+    {0     , 0      }, /* 0x4c */ \
+    {KBD_KEY_END, KBD_KEY_END}, /* 0x4d */ \
+    {KBD_KEY_PGDN , KBD_KEY_PGDN }, /* 0x4e */ \
+    {KBD_KEY_RIGHT, KBD_KEY_RIGHT }, /* 0x4f */ \
+    {KBD_KEY_LEFT, KBD_KEY_LEFT }, /* 0x50 */ \
+    {KBD_KEY_DOWN, KBD_KEY_DOWN }, /* 0x51 */ \
+    {KBD_KEY_UP, KBD_KEY_UP }, /* 0x52 */ \
+    { 0   , 0       }, /* 0x53 */ \
+    { 0   , 0       }, /* 0x54 */ \
+    { 0   , 0       }, /* 0x55 */ \
+    { 0   , 0       }, /* 0x56 */ \
+    { 0   , 0       }, /* 0x57 */ \
+    { 0   , 0       }, /* 0x58 */ \
+    { 0   , 0       }, /* 0x59 */ \
+    { 0   , 0       }, /* 0x5a */ \
+    { 0   , 0       }, /* 0x5b */ \
+    { 0   , 0       }, /* 0x5c */ \
+    { 0   , 0       }, /* 0x5d */ \
+    { 0   , 0       }, /* 0x5e */ \
+    { 0   , 0       }, /* 0x5f */ \
+    { 0   , 0       }, /* 0x60 */ \
+    { 0   , 0       }, /* 0x61 */ \
+    { 0   , 0       }, /* 0x62 */ \
+    { 0   , 0       }, /* 0x63 */ \
+    { '<' , '>'     }, /* 0x64 */ \
+    { 0   , 0       }, /* 0x65 */ \
+    { 0   , 0       }, /* 0x66 */ \
+    { 0   , 0       }, /* 0x67 */ \
+};
+
+static KLAYOUT klayout = KEYLAYOUT;
+
+
+/* =================  End keycode translation table. ================== */
+
+/*===========================================================================
+ * is_key_held 
+ * Check whether the current key scancode is a repetition of the previous
+ * one. One USB report can contain multiple keystrokes, if one key is pressed
+ * before another is released. As each new key is pressed, a new report
+ * is delivered that contains the keystrokes of the set of keys that
+ * are down. As a result, the same keystroke can be found in multiple
+ * successive reports.  
+ * ========================================================================*/
+static inline bool is_key_held (hid_keyboard_report_t const *report, uint8_t keycode)
+{
+  for (uint8_t i=0; i < 6; i++) 
+  {
+    if (report->keycode[i] == keycode) 
+      return true;
+  }
+  return false;
+}
+
+/*===========================================================================
+ * process_kbd_report 
+ * Process a report from a keyboard device. The report will contain up
+ * to 6 keystrokes, each representing a different key that is down.
+ * We need to filter duplicate keystrokes that arise when multiple keys
+ * are pressed such that one key is pressed before another is released.
+ * This is quite common when typing quickly on a decent keyboard.  
+ * ========================================================================*/
+static void process_kbd_report (hid_keyboard_report_t const *report)
+{
+  static hid_keyboard_report_t prev_report = { 0, 0, {0} };
+  
+  bool is_lshift_pressed = report->modifier 
+    & KEYBOARD_MODIFIER_LEFTSHIFT;
+  bool is_lctrl_pressed = report->modifier 
+    & KEYBOARD_MODIFIER_LEFTCTRL;
+  bool is_lalt_pressed = report->modifier 
+    & KEYBOARD_MODIFIER_LEFTALT;  
+  bool is_rshift_pressed = report->modifier 
+    & (KEYBOARD_MODIFIER_RIGHTSHIFT);
+  bool is_rctrl_pressed = report->modifier 
+    & KEYBOARD_MODIFIER_RIGHTCTRL;
+  bool is_ralt_pressed = report->modifier 
+    & KEYBOARD_MODIFIER_RIGHTALT;  
+  for (uint8_t i=0; i < 6; i++) 
+  {
+    if (report->keycode[i]) 
+    {
+      bool found = is_key_held (&prev_report, report->keycode[i]);
+
+      if (!found) 
+      {
+        int ch; 
+        int chshift;
+        if (klayout == KLAYOUT_UK) {
+          ch = conv_table_uk[report->keycode[i]][0];
+          chshift = conv_table_uk[report->keycode[i]][(is_lshift_pressed?1:0)];
+        }
+        else if (klayout == KLAYOUT_BE) {
+          ch = conv_table_be[report->keycode[i]][0];
+          chshift = conv_table_be[report->keycode[i]][(is_lshift_pressed?1:0)];
+        }
+
+        int flags = 0;
+        if (is_lshift_pressed) flags |= KBD_FLAG_LSHIFT;
+        if (is_lctrl_pressed) flags |= KBD_FLAG_LCONTROL;
+        if (is_lalt_pressed) flags |= KBD_FLAG_LALT;
+        if (is_rshift_pressed) flags |= KBD_FLAG_RSHIFT;
+        if (is_rctrl_pressed) flags |= KBD_FLAG_RCONTROL;
+        if (is_ralt_pressed) flags |= KBD_FLAG_RALT;
+        kbd_signal_raw_key(report->keycode[i], ch, chshift, flags, KEY_PRESSED);
+        //printf("key=%d\n", report->keycode[i]);
+        //printf("flags=%d\n", flags);
+      }
+    }
+  }
+  for (uint8_t i=0; i < 6; i++) 
+  {
+    if (prev_report.keycode[i]) 
+    {
+      bool found = is_key_held (report, prev_report.keycode[i]);
+      if (!found) 
+      {
+        int ch; 
+        int chshift;
+        if (klayout == KLAYOUT_UK) {
+          ch = conv_table_uk[prev_report.keycode[i]][0];
+          chshift = conv_table_uk[prev_report.keycode[i]][(is_lshift_pressed?1:0)];
+        }
+        else if (klayout == KLAYOUT_BE) {
+          ch = conv_table_be[prev_report.keycode[i]][0];
+          chshift = conv_table_be[prev_report.keycode[i]][(is_lshift_pressed?1:0)];
+        }
+        int flags = 0;
+        if (is_lshift_pressed) flags |= KBD_FLAG_LSHIFT;
+        if (is_lctrl_pressed) flags |= KBD_FLAG_LCONTROL;
+        if (is_lalt_pressed) flags |= KBD_FLAG_LALT;
+        if (is_rshift_pressed) flags |= KBD_FLAG_RSHIFT;
+        if (is_rctrl_pressed) flags |= KBD_FLAG_RCONTROL;
+        if (is_ralt_pressed) flags |= KBD_FLAG_RALT;        
+        kbd_signal_raw_key(prev_report.keycode[i], ch, chshift, flags, KEY_RELEASED);
+      } 
+    }
+  } 
+  prev_report = *report;
+}
+ 
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+void hid_app_task(void)
+{
+  // nothing to do
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
+{
+  (void)desc_report;
+  (void)desc_len;
+  uint16_t vid, pid;
+  tuh_vid_pid_get(dev_addr, &vid, &pid);
+
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+  printf("VID = %04x, PID = %04x\r\n", vid, pid);
+
+  /* Ask for a report only if this is a keyboard device */
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+  if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD) 
+  {
+    printf("Keyboard found\n");
+    tuh_hid_receive_report (dev_addr, instance);
+  }
+
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
+{
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+{
+  (void) instance; (void) len;
+  // In principle we don't need to test that this USB report came from
+  //   a keyboard, since we are only asking for reports from keyboards.
+  // But, for future expansion, we should be systematic
+  switch (tuh_hid_interface_protocol (dev_addr, instance)) 
+  {
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      process_kbd_report ((hid_keyboard_report_t const*) report);
+      break;
+  }
+
+  // Ask the device for the next report -- asking for a report is a
+  //   one-off operation, and must be repeated by the application. 
+  tuh_hid_receive_report (dev_addr, instance);
+
+  /*
+  if ( is_sony_ds4(dev_addr) )
+  {
+    process_sony_ds4(report, len);
+  }
+
+  // continue to request to receive report
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
+  */
+}
+
+void kbd_set_locale(KLAYOUT layout)
+{
+  klayout = layout;
+}
diff --git a/MCUME_pico2/usb_kbd/kbd.h b/MCUME_pico2/usb_kbd/kbd.h
new file mode 100755
index 0000000..b63f1b4
--- /dev/null
+++ b/MCUME_pico2/usb_kbd/kbd.h
@@ -0,0 +1,50 @@
+#define KBD_FLAG_LSHIFT    0x01
+#define KBD_FLAG_LCONTROL  0x02
+#define KBD_FLAG_LALT      0x04
+#define KBD_FLAG_RSHIFT    0x08
+#define KBD_FLAG_RCONTROL  0x10
+#define KBD_FLAG_RALT      0x20
+
+#define KBD_KEY_BS         0x14 //8
+#define KBD_KEY_ENTER      13
+#define KBD_KEY_DOWN       1000
+#define KBD_KEY_UP         1001
+#define KBD_KEY_PGDN       1002
+#define KBD_KEY_PGUP       1003
+#define KBD_KEY_RIGHT      1004
+#define KBD_KEY_LEFT       1005
+#define KBD_KEY_HOME       1006
+#define KBD_KEY_END        1007
+#define KBD_KEY_ESC        1008
+#define KBD_KEY_CAPS       1010
+
+#define KBD_KEY_F1         1011
+#define KBD_KEY_F2         1012
+#define KBD_KEY_F3         1013
+#define KBD_KEY_F4         1014
+#define KBD_KEY_F5         1015
+#define KBD_KEY_F6         1016
+#define KBD_KEY_F7         1017
+#define KBD_KEY_F8         1018
+
+
+#define KEY_PRESSED  1
+#define KEY_RELEASED 0
+
+typedef enum {
+	KLAYOUT_UK = 0,
+	KLAYOUT_BE,
+} KLAYOUT;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* raw_key_down should be called whenever a key is pressed
+ * or released. */
+extern void kbd_signal_raw_key(int keycode, int code, int codeshifted, int flags, int pressed);
+extern void kbd_set_locale(KLAYOUT layout);
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file